From 313c57c0b1f43a1d562691ed6d96eb6a9cedc045 Mon Sep 17 00:00:00 2001 From: hcf <11636549+hcf85679@user.noreply.gitee.com> Date: Fri, 14 Jun 2024 10:47:50 +0800 Subject: [PATCH 1/3] Add zsda and net code --- kmod-zxdh.spec | 123 + src/crypto/zsda/Makefile | 32 + src/crypto/zsda/accdevice/Makefile | 3 + .../zsda/accdevice/zsda_common/Makefile | 6 + .../zsda/accdevice/zsda_common/zsda_alg.c | 560 + .../zsda/accdevice/zsda_common/zsda_alg.h | 119 + .../accdevice/zsda_common/zsda_common_drv.c | 105 + .../accdevice/zsda_common/zsda_common_drv.h | 33 + .../zsda/accdevice/zsda_common/zsda_isr.c | 140 + .../zsda/accdevice/zsda_common/zsda_manage.c | 131 + .../zsda/accdevice/zsda_common/zsda_manage.h | 19 + .../zsda/accdevice/zsda_common/zsda_pci.c | 120 + .../zsda/accdevice/zsda_common/zsda_pci.h | 14 + .../zsda/accdevice/zsda_common/zsda_qp.c | 674 + .../zsda/accdevice/zsda_common/zsda_qp.h | 143 + src/crypto/zsda/accdevice/zsda_pf/Makefile | 4 + src/crypto/zsda/accdevice/zsda_pf/zsda_drv.c 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%{_sbindir}/depmod +Requires(posttrans): %{_sbindir}/weak-modules +Requires(postun): %{_sbindir}/weak-modules +Requires(posttrans): %{_bindir}/sort +Requires(postun): %{_bindir}/sort + +# 构建依赖, 和内核版本对应 +BuildRequires: kernel-devel = %{kernel} +BuildRequires: kernel-headers = %{kernel} +BuildRequires: elfutils-libelf-devel +BuildRequires: gcc +BuildRequires: kmod +BuildRequires: make +BuildRequires: system-rpm-config + +Provides: %{name} = %{version}-%{release} +Obsoletes: %{name} < %{version}-%{release} + +%description +RPM Package for ZXDH Driver + +%prep +%setup -q -n kmod-%{pkg}-%{pkg_version} + +%build +pushd src/crypto/zsda +%{__make} -C /usr/src/kernels/%{kernel}.%{_arch} %{?_smp_mflags} M=$PWD modules CONFIG_ACC_ZSDA_COMMON=m CONFIG_ACC_ZSDA_PF=m CONFIG_ACC_ZSDA_VF=m +popd +pushd src/net +./build.sh m +popd + +%install +mkdir -p %{buildroot}/lib/modules/%{kernel}.%{_arch}/extra/drivers/crypto/zsda/ +%{__install} -D -t %{buildroot}/lib/modules/%{kernel}.%{_arch}/extra/drivers/crypto/zsda/ src/crypto/zsda/accdevice/zsda_common/zsda_common.ko +%{__install} -D -t %{buildroot}/lib/modules/%{kernel}.%{_arch}/extra/drivers/crypto/zsda/ src/crypto/zsda/accdevice/zsda_pf/zsda_pf.ko +%{__install} -D -t %{buildroot}/lib/modules/%{kernel}.%{_arch}/extra/drivers/crypto/zsda/ src/crypto/zsda/accdevice/zsda_vf/zsda_vf.ko +%{__install} -D -t %{buildroot}/lib/modules/%{kernel}.%{_arch}/extra/drivers/net/ethernet/dinghai/ src/net/drivers/base/zxdh_auxiliary.ko +%{__install} -D -t %{buildroot}/lib/modules/%{kernel}.%{_arch}/extra/drivers/net/ethernet/dinghai/ src/net/drivers/net/ethernet/dinghai/zxdh_cmd.ko +%{__install} -D -t %{buildroot}/lib/modules/%{kernel}.%{_arch}/extra/drivers/net/ethernet/dinghai/ src/net/drivers/net/ethernet/dinghai/zxdh_np.ko +%{__install} -D -t %{buildroot}/lib/modules/%{kernel}.%{_arch}/extra/drivers/net/ethernet/dinghai/ src/net/drivers/net/ethernet/dinghai/zxdh_ptp.ko +%{__install} -D -t %{buildroot}/lib/modules/%{kernel}.%{_arch}/extra/drivers/net/ethernet/dinghai/ src/net/drivers/net/ethernet/dinghai/zxdh_tsn.ko +%{__install} -D -t %{buildroot}/lib/modules/%{kernel}.%{_arch}/extra/drivers/net/ethernet/dinghai/ src/net/drivers/net/ethernet/dinghai/zxdh_pf.ko +%{__install} -D -t %{buildroot}/lib/modules/%{kernel}.%{_arch}/extra/drivers/net/ethernet/dinghai/ src/net/drivers/net/ethernet/dinghai/zxdh_en_aux.ko + +# Make .ko objects temporarily executable for automatic stripping +find %{buildroot}/lib/modules -type f -name \*.ko -exec chmod u+x \{\} \+ + +# Generate depmod.conf +%{__install} -d %{buildroot}/%{_sysconfdir}/depmod.d/ +for kmod in $(find %{buildroot}/lib/modules/%{kernel}.%{_arch}/extra -type f -name \*.ko -printf "%%P\n" | sort) +do + echo "override $(basename $kmod .ko) * weak-updates/$(dirname $kmod)" >> %{buildroot}/%{_sysconfdir}/depmod.d/%{pkg}.conf + echo "override $(basename $kmod .ko) * extra/$(dirname $kmod)" >> %{buildroot}/%{_sysconfdir}/depmod.d/%{pkg}.conf +done + +%clean +%{__rm} -rf %{buildroot} + +%post +depmod -a > /dev/null 2>&1 + +if [ -x "/usr/sbin/weak-modules" ]; then + printf '%s\n' "/lib/modules/%{kernel}.%{_arch}/extra/drivers/crypto/zsda/zsda_common.ko" | /usr/sbin/weak-modules --no-initramfs --add-modules + printf '%s\n' "/lib/modules/%{kernel}.%{_arch}/extra/drivers/crypto/zsda/zsda_pf.ko" | /usr/sbin/weak-modules --no-initramfs --add-modules + printf '%s\n' "/lib/modules/%{kernel}.%{_arch}/extra/drivers/crypto/zsda/zsda_vf.ko" | /usr/sbin/weak-modules --no-initramfs --add-modules + printf '%s\n' "/lib/modules/%{kernel}.%{_arch}/extra/drivers/net/ethernet/dinghai/zxdh_auxiliary.ko" | /usr/sbin/weak-modules --no-initramfs --add-modules + printf '%s\n' "/lib/modules/%{kernel}.%{_arch}/extra/drivers/net/ethernet/dinghai/zxdh_cmd.ko" | /usr/sbin/weak-modules --no-initramfs --add-modules + printf '%s\n' "/lib/modules/%{kernel}.%{_arch}/extra/drivers/net/ethernet/dinghai/zxdh_np.ko" | /usr/sbin/weak-modules --no-initramfs --add-modules + printf '%s\n' "/lib/modules/%{kernel}.%{_arch}/extra/drivers/net/ethernet/dinghai/zxdh_ptp.ko" | /usr/sbin/weak-modules --no-initramfs --add-modules + printf '%s\n' "/lib/modules/%{kernel}.%{_arch}/extra/drivers/net/ethernet/dinghai/zxdh_tsn.ko" | /usr/sbin/weak-modules --no-initramfs --add-modules + printf '%s\n' "/lib/modules/%{kernel}.%{_arch}/extra/drivers/net/ethernet/dinghai/zxdh_pf.ko" | /usr/sbin/weak-modules --no-initramfs --add-modules + printf '%s\n' "/lib/modules/%{kernel}.%{_arch}/extra/drivers/net/ethernet/dinghai/zxdh_en_aux.ko" | /usr/sbin/weak-modules --no-initramfs --add-modules +fi + +%preun +echo "/lib/modules/%{kernel}.%{_arch}/extra/drivers/crypto/zsda/zsda_common.ko" >> /var/run/rpm-%{pkg}-modules.list +echo "/lib/modules/%{kernel}.%{_arch}/extra/drivers/crypto/zsda/zsda_pf.ko" >> /var/run/rpm-%{pkg}-modules.list +echo "/lib/modules/%{kernel}.%{_arch}/extra/drivers/crypto/zsda/zsda_vf.ko" >> /var/run/rpm-%{pkg}-modules.list +echo "/lib/modules/%{kernel}.%{_arch}/extra/drivers/net/ethernet/dinghai/zxdh_auxiliary.ko" >> /var/run/rpm-%{pkg}-modules.list +echo "/lib/modules/%{kernel}.%{_arch}/extra/drivers/net/ethernet/dinghai/zxdh_cmd.ko" >> /var/run/rpm-%{pkg}-modules.list +echo "/lib/modules/%{kernel}.%{_arch}/extra/drivers/net/ethernet/dinghai/zxdh_np.ko" >> /var/run/rpm-%{pkg}-modules.list +echo "/lib/modules/%{kernel}.%{_arch}/extra/drivers/net/ethernet/dinghai/zxdh_ptp.ko" >> /var/run/rpm-%{pkg}-modules.list +echo "/lib/modules/%{kernel}.%{_arch}/extra/drivers/net/ethernet/dinghai/zxdh_tsn.ko" >> /var/run/rpm-%{pkg}-modules.list +echo "/lib/modules/%{kernel}.%{_arch}/extra/drivers/net/ethernet/dinghai/zxdh_pf.ko" >> /var/run/rpm-%{pkg}-modules.list +echo "/lib/modules/%{kernel}.%{_arch}/extra/drivers/net/ethernet/dinghai/zxdh_en_aux.ko" >> /var/run/rpm-%{pkg}-modules.list + +%postun +depmod -a > /dev/null 2>&1 + +if [ -x "/usr/sbin/weak-modules" ]; then + modules=( $(cat /var/run/rpm-%{pkg}-modules.list) ) + printf '%s\n' "${modules[@]}" | /usr/sbin/weak-modules --no-initramfs --remove-modules +fi +rm /var/run/rpm-%{pkg}-modules.list + +%files +%defattr(644,root,root,755) +%license licenses +/lib/modules/%{kernel}.%{_arch} +%config(noreplace) %{_sysconfdir}/depmod.d/%{pkg}.conf + +%changelog + diff --git a/src/crypto/zsda/Makefile b/src/crypto/zsda/Makefile new file mode 100644 index 0000000..51211ce --- /dev/null +++ b/src/crypto/zsda/Makefile @@ -0,0 +1,32 @@ + +#obj-m += accdevice/ + +ifeq ($(KERNELRELEASE),) + + # Assume the source tree is where the running kernel was built + # You should set KERNELDIR in the environment if it's elsewhere + ifndef KERNELDIR + KERNELDIR ?= /lib/modules/$(shell uname -r)/build + endif + # The current directory is passed to sub-makes as argument + PWD := $(shell pwd) + +modules: + $(MAKE) -C $(KERNELDIR) M=$(PWD) modules \ + CONFIG_ACC_ZSDA_COMMON=m \ + CONFIG_ACC_ZSDA_PF=m \ + CONFIG_ACC_ZSDA_VF=m + +modules_install: + $(MAKE) -C $(KERNELDIR) M=$(PWD) modules_install + +clean: + $(MAKE) -C $(KERNELDIR) M=$(PWD) clean + +.PHONY: modules modules_install clean + +else + # called from kernel build system: just declare what our modules are + obj-m += accdevice/ +# ast-objs := ast_cursor.o ast_drv.o ast_main.o ast_mm.o ast_mode.o ast_post.o ast_dp501.o +endif diff --git a/src/crypto/zsda/accdevice/Makefile b/src/crypto/zsda/accdevice/Makefile new file mode 100644 index 0000000..a7aa7ef --- /dev/null +++ b/src/crypto/zsda/accdevice/Makefile @@ -0,0 +1,3 @@ +obj-$(CONFIG_ACC_ZSDA_COMMON) += zsda_common/ +obj-$(CONFIG_ACC_ZSDA_PF) += zsda_pf/ +obj-$(CONFIG_ACC_ZSDA_VF) += zsda_vf/ diff --git a/src/crypto/zsda/accdevice/zsda_common/Makefile b/src/crypto/zsda/accdevice/zsda_common/Makefile new file mode 100644 index 0000000..93c8e7e --- /dev/null +++ b/src/crypto/zsda/accdevice/zsda_common/Makefile @@ -0,0 +1,6 @@ +ccflags-y := -I$(src)/../../include +ccflags-y += -I$(src)/../crypto/ +ccflags-y += -I/usr/include +obj-$(CONFIG_ACC_ZSDA_COMMON) += zsda_common.o +zsda_common-objs = zsda_manage.o zsda_alg.o zsda_qp.o zsda_common_drv.o zsda_isr.o zsda_pci.o + diff --git a/src/crypto/zsda/accdevice/zsda_common/zsda_alg.c b/src/crypto/zsda/accdevice/zsda_common/zsda_alg.c new file mode 100644 index 0000000..1fb2263 --- /dev/null +++ b/src/crypto/zsda/accdevice/zsda_common/zsda_alg.c @@ -0,0 +1,560 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright(c) 2024 ZTE Corporation */ + +#include +#include +#include "zsda_common_drv.h" +#include "zsda_alg.h" +#include "zsda_manage.h" +#include "acc_dev.h" + +static DEFINE_MUTEX(lkcf_lock); +static unsigned int acc_devs; + +static void zsda_ablkcipher_callback(struct zsda_cqe *resp, + struct zsda_crypto_request *req) +{ + int res = 0; + struct skcipher_request *sreq = req->skcipher_req; + + if (cqe_err1(resp->err1)) + res = -EINVAL; + + sreq->base.complete(&sreq->base, res); +} + +static int zsda_ablkcipher_init(struct crypto_skcipher *tfm) +{ + int reqsize; + + reqsize = sizeof(struct zsda_crypto_request) + + sizeof(struct skcipher_request); + crypto_skcipher_set_reqsize(tfm, reqsize); + + return 0; +} + +static void zsda_ablkcipher_exit(struct crypto_skcipher *tfm) +{ + struct zsda_crypto_ctx *ctx = crypto_skcipher_ctx(tfm); + struct accel_dev *inst = ctx->acc_dev; + struct device *dev; + + if (!inst) + return; + + dev = &GET_DEV(inst); + + zsda_put_instance(inst); +} + +static const unsigned char aes_sbox[256] = { + 0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5, 0x30, 0x01, 0x67, 0x2b, + 0xfe, 0xd7, 0xab, 0x76, 0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0, + 0xad, 0xd4, 0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0, 0xb7, 0xfd, 0x93, 0x26, + 0x36, 0x3f, 0xf7, 0xcc, 0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15, + 0x04, 0xc7, 0x23, 0xc3, 0x18, 0x96, 0x05, 0x9a, 0x07, 0x12, 0x80, 0xe2, + 0xeb, 0x27, 0xb2, 0x75, 0x09, 0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0, + 0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3, 0x2f, 0x84, 0x53, 0xd1, 0x00, 0xed, + 0x20, 0xfc, 0xb1, 0x5b, 0x6a, 0xcb, 0xbe, 0x39, 0x4a, 0x4c, 0x58, 0xcf, + 0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85, 0x45, 0xf9, 0x02, 0x7f, + 0x50, 0x3c, 0x9f, 0xa8, 0x51, 0xa3, 0x40, 0x8f, 0x92, 0x9d, 0x38, 0xf5, + 0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2, 0xcd, 0x0c, 0x13, 0xec, + 0x5f, 0x97, 0x44, 0x17, 0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19, 0x73, + 0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88, 0x46, 0xee, 0xb8, 0x14, + 0xde, 0x5e, 0x0b, 0xdb, 0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c, + 0xc2, 0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79, 0xe7, 0xc8, 0x37, 0x6d, + 0x8d, 0xd5, 0x4e, 0xa9, 0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08, + 0xba, 0x78, 0x25, 0x2e, 0x1c, 0xa6, 0xb4, 0xc6, 0xe8, 0xdd, 0x74, 0x1f, + 0x4b, 0xbd, 0x8b, 0x8a, 0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e, + 0x61, 0x35, 0x57, 0xb9, 0x86, 0xc1, 0x1d, 0x9e, 0xe1, 0xf8, 0x98, 0x11, + 0x69, 0xd9, 0x8e, 0x94, 0x9b, 0x1e, 0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf, + 0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68, 0x41, 0x99, 0x2d, 0x0f, + 0xb0, 0x54, 0xbb, 0x16 +}; + +static const unsigned char Rcon[11] = { 0x8d, 0x01, 0x02, 0x04, 0x08, 0x10, + 0x20, 0x40, 0x80, 0x1b, 0x36 }; + +#define GET_AES_SBOX_VAL(num) (aes_sbox[(num)]) + +static void zsda_aes_key_expansion(uint8_t *round_key, uint32_t round_num, + const uint8_t *key, uint32_t key_len) +{ + uint32_t i, j, k, nk, nr; + uint8_t tempa[4], temp; // Used for the column/row operations + + nk = key_len >> 2; // The number of 32 bit words in a key. + nr = round_num; + + // The first round key is the key itself. + for (i = 0; i < nk; ++i) { + round_key[(i * 4) + 0] = key[(i * 4) + 0]; + round_key[(i * 4) + 1] = key[(i * 4) + 1]; + round_key[(i * 4) + 2] = key[(i * 4) + 2]; + round_key[(i * 4) + 3] = key[(i * 4) + 3]; + } + + // All other round keys are found from the previous round keys. + for (i = nk; i < 4 * (nr + 1); ++i) { + k = (i - 1) * 4; + tempa[0] = round_key[k + 0]; + tempa[1] = round_key[k + 1]; + tempa[2] = round_key[k + 2]; + tempa[3] = round_key[k + 3]; + + if (i % nk == 0) { + { + const u_int8_t u8tmp = tempa[0]; + + tempa[0] = tempa[1]; + tempa[1] = tempa[2]; + tempa[2] = tempa[3]; + tempa[3] = u8tmp; + } + for (j = 0; j < 4; j++) { + temp = GET_AES_SBOX_VAL(tempa[j]); + tempa[j] = temp; + } + + tempa[0] = tempa[0] ^ Rcon[i / nk]; + } + + if (nk == 8) { + if (i % nk == 4) { + for (j = 0; j < 4; j++) { + temp = GET_AES_SBOX_VAL(tempa[j]); + tempa[j] = temp; + } + } + } + + j = i * 4; + k = (i - nk) * 4; + round_key[j + 0] = round_key[k + 0] ^ tempa[0]; + round_key[j + 1] = round_key[k + 1] ^ tempa[1]; + round_key[j + 2] = round_key[k + 2] ^ tempa[2]; + round_key[j + 3] = round_key[k + 3] ^ tempa[3]; + } +} + +void reverse_memcpy(uint8_t *dst, const uint8_t *src, size_t n) +{ + size_t i; + + for (i = 0; i < n; ++i) + dst[n - 1 - i] = src[i]; +} + +static void build_encry_key(const uint8_t *key, uint8_t *encry_key, + unsigned int keylen) +{ + unsigned int skey_len; + + skey_len = keylen / 2; + // 适配硬件所需的密钥格式 + if (skey_len == ZSDA_XTS_256_SKEY_LEN) { + reverse_memcpy(encry_key + ZSDA_XTS_256_KEY2_OFF, key + skey_len, + skey_len); + reverse_memcpy(encry_key + ZSDA_XTS_256_KEY1_OFF, key, skey_len); + } else { + reverse_memcpy(encry_key, key, keylen); + } +} + +static void build_decry_key(const uint8_t *key, uint8_t *decry_key, + unsigned int keylen) +{ + unsigned int skey_len; + uint8_t round_num; + uint8_t dec_key1[ZSDA_AES_MAX_KEY_BYTE_LEN] = { 0 }; + uint8_t aes_round_key[ZSDA_AES_MAX_EXP_BYTE_SIZE] = { 0 }; + + skey_len = keylen / 2; + + if (skey_len != ZSDA_XTS_512_KEY1_OFF && + skey_len != ZSDA_XTS_256_SKEY_LEN) + return; + + round_num = + (skey_len == 16) ? ZSDA_AES256_ROUND_NUM : ZSDA_AES512_ROUND_NUM; + + zsda_aes_key_expansion(aes_round_key, round_num, key, skey_len); + memcpy(dec_key1, aes_round_key + 16 * round_num, 16); + if (skey_len > ZSDA_XTS_256_SKEY_LEN) + memcpy(dec_key1 + 16, + aes_round_key + 16 * round_num - (skey_len - 16), + skey_len - 16); + + if (skey_len == ZSDA_XTS_256_SKEY_LEN) { + reverse_memcpy(decry_key + ZSDA_XTS_256_KEY2_OFF, key + skey_len, + skey_len); + reverse_memcpy(decry_key + ZSDA_XTS_256_KEY1_OFF, dec_key1, + skey_len); + } else { + reverse_memcpy(decry_key, key + skey_len, skey_len); + reverse_memcpy(decry_key + ZSDA_XTS_512_KEY1_OFF, dec_key1, + skey_len); + } +} + +static void zsda_init_ctx(struct zsda_crypto_ctx *ctx, const uint8_t *key, + unsigned int keylen, int mode) +{ + build_encry_key(key, ctx->encry_key, keylen); + build_decry_key(key, ctx->decry_key, keylen); + memcpy(ctx->key, key, keylen); + ctx->keylen = keylen; + ctx->mode = mode; +} + +static int zsda_alg_validate_key(unsigned int key_len, int mode) +{ + if (mode != HW_CIPHER_XTS_MODE) + return -EINVAL; + + switch (key_len) { + case AES_KEYSIZE_128 << 1: + break; + case AES_KEYSIZE_256 << 1: + break; + default: + return -EINVAL; + } + + return 0; +} + +static int zsda_init_sessions(struct zsda_crypto_ctx *ctx, const uint8_t *key, + unsigned int keylen, int mode) +{ + if (zsda_alg_validate_key(keylen, mode)) + goto bad_key; + + zsda_init_ctx(ctx, key, keylen, mode); + + return 0; +bad_key: + return -EINVAL; +} + +static int zsda_crypto_newkey(struct zsda_crypto_ctx *ctx, const u8 *key, + unsigned int keylen, int mode) +{ + struct accel_dev *inst = NULL; + struct device *dev; + int ret; + + inst = zsda_get_instance(); + if (!inst) + return -EINVAL; + dev = &GET_DEV(inst); + ctx->acc_dev = inst; + + ret = zsda_init_sessions(ctx, key, keylen, mode); + if (ret) + goto fail; + + return 0; + +fail: + ctx->acc_dev = NULL; + zsda_put_instance(inst); + return ret; +} + +static int zsda_crypto_rekey(struct zsda_crypto_ctx *ctx, const u8 *key, + unsigned int keylen, int mode) +{ + return zsda_init_sessions(ctx, key, keylen, mode); +} + +static int zsda_alg_ablkcipher_setkey(struct crypto_skcipher *tfm, const u8 *key, + unsigned int keylen, int mode) +{ + struct zsda_crypto_ctx *ctx = crypto_skcipher_ctx(tfm); + + if (ctx->acc_dev) + return zsda_crypto_rekey(ctx, key, keylen, mode); + else + return zsda_crypto_newkey(ctx, key, keylen, mode); +} + +static int zsda_ablkcipher_xts_setkey(struct crypto_skcipher *tfm, const u8 *key, + unsigned int keylen) +{ + return zsda_alg_ablkcipher_setkey(tfm, key, keylen, HW_CIPHER_XTS_MODE); +} + +#define SGL_LINK_MODULE 32 +static int zsda_fill_sgl(struct accel_dev *acc_dev, struct scatterlist *buff, + struct zsda_buf *sgl_in, phys_addr_t sgl_phy_addr) +{ + int i = 0, y = 0; + int n = sg_nents(buff); + struct scatterlist *sg; + struct device *dev = &GET_DEV(acc_dev); + + if (unlikely(!n)) + return -EINVAL; + + for_each_sg(buff, sg, n, i) { + if (y >= n) + break; + if (!sg->length) + continue; + memset(&(sgl_in[y]), 0, sizeof(struct zsda_buf)); + if (y > 0 && ((y + 1) % SGL_LINK_MODULE) == 0) { + sgl_in[y].len = 0; + sgl_in[y].addr = + sgl_phy_addr + (y + 1) * sizeof(struct zsda_buf); + sgl_in[y].type = 2; // link elment + y++; + continue; + } + + sgl_in[y].addr = dma_map_single( + dev, sg_virt(sg), sg->length, DMA_BIDIRECTIONAL); + sgl_in[y].len = sg->length; + sgl_in[y].type = 0; + // printk("sgl_addr[%d] 0x%llx\n", y, sgl_in[y].addr); + if (unlikely(dma_mapping_error(dev, sgl_in[y].addr))) { + dev_err(dev, "sgl error dma_map\n"); + return -ENOMEM; + } + y++; + } + sgl_in[y - 1].type = 1; + return 0; +} + +static int zsda_alg_sgl_to_bufl(struct accel_dev *acc_dev, + struct zsda_crypto_request *zsda_req, + struct scatterlist *sgl, + struct scatterlist *sglout) +{ + struct device *dev = &GET_DEV(acc_dev); + int i = 0, n = sg_nents(sgl), n_out = sg_nents(sglout); + struct zsda_buf *bufl = NULL, *buflout = NULL; + phys_addr_t blp = 0, bloutp = 0; + size_t sz_out, sz; + struct cookie *cookie = zsda_req->cookie; + + if (unlikely(!n) || unlikely(!n_out)) + return -EBADMSG; + + sz = PAGE_ALIGN(n * sizeof(struct zsda_buf)); + bufl = kzalloc_node(sz, GFP_KERNEL, dev_to_node(dev)); + if (!bufl) + return -ENOMEM; + blp = dma_map_single(dev, bufl, sz, DMA_TO_DEVICE); + if (unlikely(dma_mapping_error(dev, blp))) + goto err_src; + if (zsda_fill_sgl(acc_dev, sgl, bufl, blp)) + goto err_src; + cookie->src_n = n; + cookie->src_buf = bufl; + cookie->src_addr = blp; + // printk("sz=0x%x map src_addr=0x%llx\n", sz, cookie->src_addr); + sz_out = PAGE_ALIGN(n_out * sizeof(struct zsda_buf)); + buflout = kzalloc_node(sz_out, GFP_KERNEL, dev_to_node(dev)); + if (unlikely(!buflout)) + goto err_src; + bloutp = dma_map_single(dev, buflout, sz_out, DMA_TO_DEVICE); + if (unlikely(dma_mapping_error(dev, bloutp))) + goto err_dst; + if (zsda_fill_sgl(acc_dev, sglout, buflout, bloutp)) + goto err_dst; + cookie->dst_n = n_out; + cookie->dst_buf = buflout; + cookie->dst_addr = bloutp; + // printk("sz_out=0x%x map dst_addr=0x%llx\n", cookie->dst_addr, cookie->dst_addr); + cookie->zsda_req = zsda_req; + cookie->used = true; + return 0; + +err_dst: + n = sg_nents(sglout); + for (i = 0; i < n; i++) { + if (!dma_mapping_error(dev, buflout[i].addr)) + dma_unmap_single(dev, buflout[i].addr, + buflout[i].len, + DMA_BIDIRECTIONAL); + } + if (!dma_mapping_error(dev, bloutp)) + dma_unmap_single(dev, bloutp, sz_out, DMA_TO_DEVICE); + kfree(buflout); +err_src: + n = sg_nents(sgl); + for (i = 0; i < n; i++) { + if (!dma_mapping_error(dev, bufl[i].addr)) + dma_unmap_single(dev, bufl[i].addr, + bufl[i].len, + DMA_BIDIRECTIONAL); + } + if (!dma_mapping_error(dev, blp)) + dma_unmap_single(dev, blp, sz, DMA_TO_DEVICE); + kfree(bufl); + dev_err(dev, "Map err buf for dma\n"); + return -EBADMSG; +} + +static void zsda_alg_backlog_req(struct zsda_alg_req *alg_req, + struct zsda_backlog *backlog) +{ + INIT_LIST_HEAD(&alg_req->list); + + spin_lock_bh(&backlog->lock); + list_add_tail(&alg_req->list, &backlog->list); + spin_unlock_bh(&backlog->lock); + + atomic_inc(&backlog->inflights); +} + +static int zsda_ablkcipher_blk_encrypt(struct skcipher_request *req) +{ + int ret; + struct crypto_skcipher *stfm = crypto_skcipher_reqtfm(req); + struct zsda_crypto_ctx *ctx = crypto_skcipher_ctx(stfm); + struct zsda_crypto_request *zsda_req = skcipher_request_ctx(req); + struct accel_dev *acc_dev = ctx->acc_dev; + struct device *dev = &GET_DEV(acc_dev); + struct zsda_alg_req *alg_req; + struct zsda_backlog *backlog; + struct cookie *cookie; + + if (unlikely(req->cryptlen < 16)) + return -EINVAL; + cookie = kzalloc_node(sizeof(struct cookie), GFP_KERNEL, + dev_to_node(dev)); + if (unlikely(!cookie)) { + dev_err(dev, "Failed Kzalloc cookie buf\n"); + return -ENOMEM; + } + zsda_req->cookie = cookie; + zsda_req->skcipher_req = req; + zsda_req->ablkcipher_ctx = ctx; + zsda_req->cb = zsda_ablkcipher_callback; + ret = zsda_alg_sgl_to_bufl(acc_dev, zsda_req, req->src, req->dst); + if (unlikely(ret)) + return ret; + + zsda_build_req(zsda_req, ctx, ZSDA_SERVICE_ENCRYPT); + + ret = enqueue(zsda_req, ZSDA_SERVICE_ENCRYPT, false); + if (unlikely(ret)) + goto softqueue; + + return -EINPROGRESS; + +softqueue: + alg_req = &zsda_req->alg_req; + alg_req->zsda_req = zsda_req; + alg_req->base = &req->base; + backlog = &acc_dev->cfg->backlog[ZSDA_SERVICE_ENCRYPT]; + zsda_alg_backlog_req(alg_req, backlog); + return -EBUSY; +} + +static int zsda_ablkcipher_blk_decrypt(struct skcipher_request *req) +{ + int ret; + struct crypto_skcipher *stfm = crypto_skcipher_reqtfm(req); + struct zsda_crypto_ctx *ctx = crypto_skcipher_ctx(stfm); + struct zsda_crypto_request *zsda_req = skcipher_request_ctx(req); + struct accel_dev *acc_dev = ctx->acc_dev; + struct zsda_alg_req *alg_req; + struct zsda_backlog *backlog; + struct device *dev = &GET_DEV(acc_dev); + struct cookie *cookie; + + if (unlikely(req->cryptlen < 16)) + return -EINVAL; + + cookie = kzalloc_node(sizeof(struct cookie), GFP_KERNEL, + dev_to_node(dev)); + if (unlikely(!cookie)) { + dev_err(dev, "Failed Kzalloc cookie buf\n"); + return -ENOMEM; + } + zsda_req->cookie = cookie; + zsda_req->skcipher_req = req; + zsda_req->ablkcipher_ctx = ctx; + zsda_req->cb = zsda_ablkcipher_callback; + ret = zsda_alg_sgl_to_bufl(acc_dev, zsda_req, req->src, req->dst); + if (unlikely(ret)) + return ret; + + zsda_build_req(zsda_req, ctx, ZSDA_SERVICE_DECRYPT); + + ret = enqueue(zsda_req, ZSDA_SERVICE_DECRYPT, false); + if (unlikely(ret)) + goto softqueue; + + return -EINPROGRESS; + +softqueue: + alg_req = &zsda_req->alg_req; + alg_req->zsda_req = zsda_req; + alg_req->base = &req->base; + backlog = &acc_dev->cfg->backlog[ZSDA_SERVICE_DECRYPT]; + zsda_alg_backlog_req(alg_req, backlog); + return -EBUSY; +} + +static struct skcipher_alg zsda_algs[] = { { + //todo priority和name + .base = { + .cra_name = "xts(zsda_aes)", + .cra_driver_name = "zsda_aes_xts", + .cra_priority = 4001, + .cra_flags = CRYPTO_ALG_ASYNC, + //.cra_flags = CRYPTO_ALG_ASYNC | + // CRYPTO_ALG_ALLOCATES_MEMORY, + .cra_blocksize = AES_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct zsda_crypto_ctx), + .cra_alignmask = 0, + .cra_module = THIS_MODULE, + }, + + .init = zsda_ablkcipher_init, + .exit = zsda_ablkcipher_exit, + .setkey = zsda_ablkcipher_xts_setkey, + .decrypt = zsda_ablkcipher_blk_decrypt, + .encrypt = zsda_ablkcipher_blk_encrypt, + .min_keysize = 2 * AES_MIN_KEY_SIZE, + .max_keysize = 2 * AES_MAX_KEY_SIZE, + .ivsize = AES_BLOCK_SIZE, +}, +}; + +int zsda_lkcf_register(void) +{ + int ret = 0; + + mutex_lock(&lkcf_lock); + + if (++acc_devs != 1) + goto unlock; + ret = crypto_register_skciphers(zsda_algs, ARRAY_SIZE(zsda_algs)); + if (ret) { + pr_err("ZSDA:Failed register skciphers %d\n", ret); + goto unlock; + } + +unlock: + mutex_unlock(&lkcf_lock); + return ret; +} +EXPORT_SYMBOL_GPL(zsda_lkcf_register); + +void zsda_lkcf_unregister(void) +{ + mutex_lock(&lkcf_lock); + + if (--acc_devs == 0) + crypto_unregister_skciphers(zsda_algs, ARRAY_SIZE(zsda_algs)); + + mutex_unlock(&lkcf_lock); +} +EXPORT_SYMBOL_GPL(zsda_lkcf_unregister); diff --git a/src/crypto/zsda/accdevice/zsda_common/zsda_alg.h b/src/crypto/zsda/accdevice/zsda_common/zsda_alg.h new file mode 100644 index 0000000..ce12682 --- /dev/null +++ b/src/crypto/zsda/accdevice/zsda_common/zsda_alg.h @@ -0,0 +1,119 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright(c) 2024 ZTE Corporation */ +#ifndef ZSDA_ALG_H +#define ZSDA_ALG_H + +enum hw_cipher_mode_t { + HW_CIPHER_ECB_MODE = 0, /*!< ECB mode */ + HW_CIPHER_CBC_MODE = 1, /*!< CBC more */ + HW_CIPHER_CTR_MODE = 2, /*!< CTR mode */ + HW_CIPHER_XTS_MODE = 6, /*!< XTS mode */ + HW_CIPHER_MODE_DELIMITER = 7 /**< Delimiter type */ +}; + +/**************** AES KEY EXPANSION ****************/ +#define ZSDA_XTS_256_SKEY_LEN (16) +#define ZSDA_XTS_256_KEY2_OFF (16) +#define ZSDA_XTS_256_KEY1_OFF (48) +#define ZSDA_XTS_512_KEY1_OFF (32) + +#define ZSDA_AES256_ROUND_NUM (10) +#define ZSDA_AES512_ROUND_NUM (14) +#define ZSDA_AES_MAX_EXP_BYTE_SIZE (240) +#define ZSDA_AES_MAX_KEY_BYTE_LEN (32) + +struct crypto_cfg { + uint8_t slba_l[8]; + uint8_t key[64]; + uint8_t lbads : 4; + uint8_t resv1 : 4; + uint8_t resv2[7]; + uint8_t slba_h[8]; + uint8_t resv3[8]; +} __attribute__((__packed__)); + +union zsda_wqe_cfg { + struct crypto_cfg crypto; +} __attribute__((__packed__)); + +struct zsda_wqe { + uint8_t valid; + uint8_t op_code; + uint16_t sid; + uint8_t resv[3]; + uint8_t rx_sgl_type : 4; + uint8_t tx_sgl_type : 4; + uint64_t rx_addr; + uint32_t rx_length; + uint64_t tx_addr; + uint32_t tx_length; + union zsda_wqe_cfg cfg; +} __attribute__((__packed__)); + +struct zsda_cqe { + uint8_t valid; + uint8_t op_code; + uint16_t sid; + uint8_t state; + uint8_t result; + uint16_t zsda_wq_id; + uint32_t tx_real_length; + uint16_t err0; + uint16_t err1; +} __attribute__((__packed__)); + +struct zsda_crypto_ctx { + uint8_t key[256]; + uint8_t encry_key[256]; + uint8_t decry_key[256]; + uint32_t keylen; + int mode; + struct accel_dev *acc_dev; + struct crypto_skcipher *tfm; +}; + +struct zsda_alg_req { + struct zsda_crypto_request *zsda_req; + struct crypto_async_request *base; + struct list_head list; +}; + +struct zsda_buf { + uint64_t addr; + uint32_t len; + uint8_t resrvd[3]; + uint8_t type; +}; + +struct zsda_sgl { + struct zsda_buf *buffers; +}; + +struct cookie { + uint32_t used; + struct zsda_buf *src_buf; + struct zsda_buf *dst_buf; + phys_addr_t src_addr; + phys_addr_t dst_addr; + size_t src_n; + size_t dst_n; + uint16_t sid; + uint16_t valid; + struct zsda_crypto_request *zsda_req; +}; + +struct zsda_crypto_request { + struct zsda_wqe wqe; + struct cookie *cookie; + struct zsda_crypto_ctx *ablkcipher_ctx; + struct skcipher_request *skcipher_req; + struct zsda_alg_req alg_req; + void (*cb)(struct zsda_cqe *resp, struct zsda_crypto_request *req); + void *iv; + dma_addr_t iv_paddr; +}; + +int zsda_lkcf_register(void); +void zsda_lkcf_unregister(void); +void reverse_memcpy(uint8_t *dst, const uint8_t *src, size_t n); +#endif diff --git a/src/crypto/zsda/accdevice/zsda_common/zsda_common_drv.c b/src/crypto/zsda/accdevice/zsda_common/zsda_common_drv.c new file mode 100644 index 0000000..4d05947 --- /dev/null +++ b/src/crypto/zsda/accdevice/zsda_common/zsda_common_drv.c @@ -0,0 +1,105 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright(c) 2024 ZTE Corporation */ +#include +#include +#include "acc_dev.h" +#include "zsda_common_drv.h" +#include "zsda_manage.h" + +void zsda_unmap_pci_bars(struct accel_dev *accel_dev) +{ + struct accel_pci *accel_pci_dev = &accel_dev->accel_pci_dev; + int i; + + for (i = 0; i < ZSDA_PCI_MAX_BARS; i++) { + struct acc_bar *bar = &accel_pci_dev->pci_bars[i]; + + if (bar->virt_addr) { + pci_iounmap(accel_pci_dev->pci_dev, bar->virt_addr); + bar->virt_addr = NULL; + } + } +} +EXPORT_SYMBOL_GPL(zsda_unmap_pci_bars); + +int zsda_map_pci_bars(struct accel_dev *accel_dev) +{ + struct accel_pci *accel_pci_dev = &accel_dev->accel_pci_dev; + struct pci_dev *pdev = accel_pci_dev->pci_dev; + unsigned long bar_mask = 0; + unsigned int bar_nr = 0; + + bar_mask = pci_select_bars(pdev, IORESOURCE_MEM); + for_each_set_bit(bar_nr, &bar_mask, ZSDA_PCI_MAX_BARS * 2) { + struct acc_bar *bar = &accel_pci_dev->pci_bars[bar_nr / 2]; + + bar->base_addr = pci_resource_start(pdev, bar_nr); + bar->size = pci_resource_len(pdev, bar_nr); + if (!bar->base_addr || !bar->size) + continue; + bar->virt_addr = pci_iomap(pdev, bar_nr, 0); + if (!bar->virt_addr) { + dev_err(&GET_DEV(accel_dev), "Failed to map BAR %d\n", + bar_nr); + zsda_unmap_pci_bars(accel_dev); + return -EFAULT; + } + } + return 0; +} +EXPORT_SYMBOL_GPL(zsda_map_pci_bars); + +static int zsda_show(struct seq_file *m, void *v) +{ + struct accel_dev *accel_dev = m->private; + if(zsda_dev_started(accel_dev)) { + if(test_bit(ZSDA_STATUS_RUNNING, &accel_dev->status)) + seq_printf(m, "%s is in used\n", accel_dev->name); + seq_printf(m, "decrypt :%lld %lld\n", accel_dev->zsda_dbg.decry_enq, + accel_dev->zsda_dbg.decry_deq); + seq_printf(m, "encrypt :%lld %lld\n", accel_dev->zsda_dbg.encry_enq, + accel_dev->zsda_dbg.encry_deq); + } + else + seq_printf(m, "%s is no support LKCF\n", accel_dev->name); + return 0; +} + +int zsda_seq_open(struct inode *inode, struct file *file) +{ + return single_open(file, zsda_show, inode->i_private); +} +EXPORT_SYMBOL_GPL(zsda_seq_open); + +ssize_t zsda_seq_write(struct file *file, const char __user *ubuf, size_t count, loff_t *off) +{ + int ret = 0; + uint32_t val; + struct seq_file *seqf = file->private_data; + struct accel_dev *accel_dev = seqf->private; + char buf[16]; + + if (count > 15) + return -EINVAL; + if (copy_from_user(buf, ubuf, count)) + return -EFAULT; + buf[count] = '\0'; + ret = kstrtou32(buf, 10, &val); + if (unlikely(ret)) + return -EINVAL; + if(!accel_dev->lkcf_en) + return -ENODEV; + + switch (val) { + case 0: + clear_bit(ZSDA_STATUS_STARTED, &accel_dev->status); + break; + case 1: + set_bit(ZSDA_STATUS_STARTED, &accel_dev->status); + break; + default: + return -EINVAL; + } + return count; +} +EXPORT_SYMBOL_GPL(zsda_seq_write); diff --git a/src/crypto/zsda/accdevice/zsda_common/zsda_common_drv.h b/src/crypto/zsda/accdevice/zsda_common/zsda_common_drv.h new file mode 100644 index 0000000..8a25098 --- /dev/null +++ b/src/crypto/zsda/accdevice/zsda_common/zsda_common_drv.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright(c) 2024 ZTE Corporation */ +#ifndef ZSDA_COMMON_H +#define ZSDA_COMMON_H + +#include "zsda_qp.h" + +#define ZSDA_STATUS_STARTED 0 +#define ZSDA_STATUS_RUNNING 1 +#define ZSDA_STATUS_IRQ_ALLOCATED 2 + +struct device_cfg_data { + u32 irq_mode; // only 1 irq, or 8 irqs. + struct zsda_qp alg_qps[ZSDA_SERVICE_COUNT]; + struct zsda_backlog backlog[ZSDA_SERVICE_COUNT]; +}; + +struct device_hw_data { + int (*alloc_irq)(struct accel_dev *accel_dev); + void (*free_irq)(struct accel_dev *accel_dev); + void (*reset_device)(struct accel_dev *accel_dev); + void (*pre_reset)(struct accel_dev *accel_dev); + void (*post_reset)(struct accel_dev *accel_dev); + +}; + +int zsda_seq_open(struct inode *inode, struct file *file); +ssize_t zsda_seq_write(struct file *file, const char __user *ubuf, size_t count, loff_t *off); +void zsda_free_irqs(struct accel_dev *accel_dev); +int zsda_request_irqs(struct accel_dev *accel_dev); +void zsda_unmap_pci_bars(struct accel_dev *accel_dev); +int zsda_map_pci_bars(struct accel_dev *accel_dev); +#endif diff --git a/src/crypto/zsda/accdevice/zsda_common/zsda_isr.c b/src/crypto/zsda/accdevice/zsda_common/zsda_isr.c new file mode 100644 index 0000000..6b5457d --- /dev/null +++ b/src/crypto/zsda/accdevice/zsda_common/zsda_isr.c @@ -0,0 +1,140 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright(c) 2024 ZTE Corporation */ +#include +#include +#include +#include "zsda_common_drv.h" +#include "acc_addr.h" +#include "acc_dev.h" + +static void zsda_alg_send_backlog(struct accel_dev *acc_dev, + enum zsda_service_type type) +{ + struct zsda_backlog *backlog; + struct zsda_alg_req *req, *tmp; + + if (!atomic_read(&acc_dev->cfg->backlog[type].inflights)) + return; + backlog = &acc_dev->cfg->backlog[type]; + spin_lock_bh(&backlog->lock); + + list_for_each_entry_safe(req, tmp, &backlog->list, list) { + if (enqueue(req->zsda_req, type, true)) + break; + + atomic_dec(&backlog->inflights); + list_del(&req->list); + req->base->complete(req->base, -EINPROGRESS); + } + spin_unlock_bh(&backlog->lock); +} + +static void encrypt_handler(uintptr_t data) +{ + struct accel_dev *accel_dev = (void *)data; + struct qp_srv *qp; + struct zsda_qp *alg_qp = + &accel_dev->cfg->alg_qps[ZSDA_SERVICE_ENCRYPT]; + + list_for_each_entry(qp, &alg_qp->list, list) { + if (unlikely(!qp->used)) + continue; + dequeue(accel_dev, qp); + } + + zsda_alg_send_backlog(accel_dev, ZSDA_SERVICE_ENCRYPT); +} + +static void decrypt_handler(uintptr_t data) +{ + struct qp_srv *qp; + struct accel_dev *accel_dev = (void *)data; + struct zsda_qp *alg_qp = + &accel_dev->cfg->alg_qps[ZSDA_SERVICE_DECRYPT]; + + list_for_each_entry(qp, &alg_qp->list, list) { + if (unlikely(!qp->used)) + continue; + dequeue(accel_dev, qp); + } + + zsda_alg_send_backlog(accel_dev, ZSDA_SERVICE_DECRYPT); +} + +static irqreturn_t encrypt_intr_handler(int irq, void *data) +{ + struct accel_dev *accel_dev = data; + + tasklet_hi_schedule(&accel_dev->encry_task); + return IRQ_HANDLED; +} + +static irqreturn_t decrypt_intr_handler(int irq, void *data) +{ + struct accel_dev *accel_dev = data; + + tasklet_hi_schedule(&accel_dev->decry_task); + return IRQ_HANDLED; +} + +static void enable_intr(struct accel_dev *accel_dev) +{ + void __iomem *base = accel_dev->accel_pci_dev.pci_bars[ZSDA_BAR0].virt_addr; + + ZSDA_REG_WR(base, ZSDA_IO_QUE_INT_MASK_1, NOMASK); + ZSDA_REG_WR(base, ZSDA_IO_QUE_INT_MASK_2, NOMASK); +} + +int zsda_request_irqs(struct accel_dev *accel_dev) +{ + int ret = 0; + struct pci_dev *pdev = accel_dev->accel_pci_dev.pci_dev; + + tasklet_init(&accel_dev->encry_task, encrypt_handler, + (unsigned long)accel_dev); + tasklet_init(&accel_dev->decry_task, decrypt_handler, + (unsigned long)accel_dev); + ret = pci_alloc_irq_vectors(pdev, 2, 10, PCI_IRQ_MSIX); + if (ret < 0) { + pr_err("ZSDA: alloc irq failed ret %d\n", ret); + ret = -EFAULT; + goto err_alloc; + } + ret = request_irq(pci_irq_vector(pdev, ZSDA_SERVICE_ENCRYPT), encrypt_intr_handler, + IRQF_SHARED, "irq2", (void *)accel_dev); + if (ret < 0) { + pr_err("ZSDA: request irq failed ret %d\n", ret); + ret = -EFAULT; + goto err_req; + } + ret = request_irq(pci_irq_vector(pdev, ZSDA_SERVICE_DECRYPT), decrypt_intr_handler, + IRQF_SHARED, "irq3", (void *)accel_dev); + if (ret < 0) { + pr_err("ZSDA: request irq failed ret %d\n", ret); + ret = -EFAULT; + goto err_req; + } + + set_bit(ZSDA_STATUS_IRQ_ALLOCATED, &accel_dev->status); + enable_intr(accel_dev); + return ret; +err_req: + pci_free_irq_vectors(pdev); +err_alloc: + tasklet_kill(&accel_dev->encry_task); + tasklet_kill(&accel_dev->decry_task); + return ret; +} +EXPORT_SYMBOL_GPL(zsda_request_irqs); + +void zsda_free_irqs(struct accel_dev *accel_dev) +{ + struct pci_dev *pdev = accel_dev->accel_pci_dev.pci_dev; + + free_irq(pci_irq_vector(pdev, ZSDA_SERVICE_ENCRYPT), (void *)accel_dev); + free_irq(pci_irq_vector(pdev, ZSDA_SERVICE_DECRYPT), (void *)accel_dev); + tasklet_kill(&accel_dev->encry_task); + tasklet_kill(&accel_dev->decry_task); + pci_free_irq_vectors(pdev); +} +EXPORT_SYMBOL_GPL(zsda_free_irqs); diff --git a/src/crypto/zsda/accdevice/zsda_common/zsda_manage.c b/src/crypto/zsda/accdevice/zsda_common/zsda_manage.c new file mode 100644 index 0000000..c9b5712 --- /dev/null +++ b/src/crypto/zsda/accdevice/zsda_common/zsda_manage.c @@ -0,0 +1,131 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright(c) 2024 ZTE Corporation */ +#include +#include +#include +#include "zsda_common_drv.h" +#include "zsda_manage.h" +#include "acc_version.h" +#include "acc_dev.h" + +static LIST_HEAD(accel_table); +static DEFINE_MUTEX(table_lock); + +int zsda_dev_started(struct accel_dev *accel_dev) +{ + return test_bit(ZSDA_STATUS_STARTED, &accel_dev->status); +} + +static void sda_dev_pf_put(struct accel_dev *vf_accel_dev) +{ + struct accel_dev *pf_accel_dev = NULL; + struct pci_dev *pf_pci_dev = NULL; + + pf_pci_dev = vf_accel_dev->accel_pci_dev.pci_dev->physfn; + pf_accel_dev = acc_devmgr_pci_to_accel_dev(pf_pci_dev); + if (pf_accel_dev) { + if (atomic_sub_return(1, &pf_accel_dev->lkcf_ref) == 0) + module_put(pf_accel_dev->owner); + } +} + +void zsda_put_instance(struct accel_dev *accel_dev) +{ + if (atomic_sub_return(1, &accel_dev->lkcf_ref) == 0) { + module_put(accel_dev->owner); + if (accel_dev->is_vf) + sda_dev_pf_put(accel_dev); + } + clear_bit(ZSDA_STATUS_RUNNING, &accel_dev->status); +} + +static int zsda_dev_pf_get(struct accel_dev *vf_accel_dev) +{ + int ret = 0; + struct accel_dev *pf_accel_dev = NULL; + struct pci_dev *pf_pci_dev = NULL; + + pf_pci_dev = vf_accel_dev->accel_pci_dev.pci_dev->physfn; + pf_accel_dev = acc_devmgr_pci_to_accel_dev(pf_pci_dev); + if (pf_accel_dev) { + if (atomic_add_return(1, &pf_accel_dev->lkcf_ref) == 1) { + if (!try_module_get(pf_accel_dev->owner)) + ret = -EFAULT; + } + } + return ret; +} + +int zsda_dev_get(struct accel_dev *accel_dev) +{ + if (atomic_add_return(1, &accel_dev->lkcf_ref) == 1) { + if (!try_module_get(accel_dev->owner)) + return -EFAULT; + if (accel_dev->is_vf) + return zsda_dev_pf_get(accel_dev); + } + return 0; +} + +struct accel_dev *zsda_get_instance(void) +{ + struct accel_dev *accel_dev = NULL, *tmp_dev; + + list_for_each_entry(tmp_dev, &accel_table, list) { + if ((!atomic_read(&tmp_dev->lkcf_ref)) && zsda_dev_started(tmp_dev)) { + accel_dev = tmp_dev; + break; + } + } + if (accel_dev){ + if (zsda_dev_get(accel_dev)) { + dev_err(&GET_DEV(accel_dev), "Could not increment dev refctr\n"); + return NULL; + } + set_bit(ZSDA_STATUS_RUNNING, &accel_dev->status); + } + else { + pr_err("ZSDA:Could not find a device\n"); + return NULL; + } + return accel_dev; +} + +void acc_devmgr_add_dev(struct accel_dev *accel_dev) +{ + mutex_lock(&table_lock); + list_add_tail(&accel_dev->list, &accel_table); + mutex_unlock(&table_lock); +} +EXPORT_SYMBOL_GPL(acc_devmgr_add_dev); + +void acc_devmgr_rm_dev(struct accel_dev *accel_dev) +{ + mutex_lock(&table_lock); + list_del(&accel_dev->list); + mutex_unlock(&table_lock); +} +EXPORT_SYMBOL_GPL(acc_devmgr_rm_dev); + +struct accel_dev *acc_devmgr_pci_to_accel_dev(struct pci_dev *pci_dev) +{ + struct list_head *itr; + + mutex_lock(&table_lock); + list_for_each(itr, &accel_table) { + struct accel_dev *ptr = list_entry(itr, struct accel_dev, list); + + if (ptr->accel_pci_dev.pci_dev == pci_dev) { + mutex_unlock(&table_lock); + return ptr; + } + } + mutex_unlock(&table_lock); + return NULL; +} +EXPORT_SYMBOL_GPL(acc_devmgr_pci_to_accel_dev); + +MODULE_AUTHOR("ZTE"); +MODULE_LICENSE("Dual BSD/GPL"); +MODULE_DESCRIPTION("ZTE ACC ZSDA COMMON"); +MODULE_VERSION(ZSDA_DRV_VERSION); diff --git a/src/crypto/zsda/accdevice/zsda_common/zsda_manage.h b/src/crypto/zsda/accdevice/zsda_common/zsda_manage.h new file mode 100644 index 0000000..3541367 --- /dev/null +++ b/src/crypto/zsda/accdevice/zsda_common/zsda_manage.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright(c) 2024 ZTE Corporation */ +#ifndef ZSDA_MANAGE_H +#define ZSDA_MANAGE_H +#include + +#define ACC_STATUS_RESTARTING 0 +#define ACC_STATUS_STARTING 1 +#define ACC_STATUS_CONFIGURED 2 +#define ACC_STATUS_STARTED 3 + +int zsda_dev_started(struct accel_dev *accel_dev); +void acc_devmgr_add_dev(struct accel_dev *accel_dev); +void acc_devmgr_rm_dev(struct accel_dev *accel_dev); +struct accel_dev *acc_devmgr_pci_to_accel_dev(struct pci_dev *pci_dev); +struct accel_dev *zsda_get_instance(void); +void zsda_put_instance(struct accel_dev *dev); + +#endif diff --git a/src/crypto/zsda/accdevice/zsda_common/zsda_pci.c b/src/crypto/zsda/accdevice/zsda_common/zsda_pci.c new file mode 100644 index 0000000..6d1a6da --- /dev/null +++ b/src/crypto/zsda/accdevice/zsda_common/zsda_pci.c @@ -0,0 +1,120 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright(c) 2024 ZTE Corporation */ +#include +#include +#include "zsda_pci.h" +#include "zsda_common_drv.h" +#include "zsda_manage.h" +// #include "acc_compat.h" +#include "acc_version.h" +#include "acc_dev.h" + +static int sriov_enable(struct accel_dev *accel_dev, const int numvfs) +{ + if (!iommu_present(&pci_bus_type)) + dev_warn( + &(accel_dev->accel_pci_dev.pci_dev->dev), + "IOMMU should be enabled for SR-IOV to work correctly\n"); + + return pci_enable_sriov(accel_dev->accel_pci_dev.pci_dev, numvfs); +} + +static int sriov_disable(struct accel_dev *accel_dev) +{ + pci_disable_sriov(accel_dev->accel_pci_dev.pci_dev); + return 0; +} + +int zsda_sriov_configure(struct pci_dev *pdev, int numvfs) +{ + struct accel_dev *accel_dev = acc_devmgr_pci_to_accel_dev(pdev); + int totalvfs = pci_sriov_get_totalvfs(pdev); + + if (!accel_dev) { + dev_err(&pdev->dev, "Failed to find accel_dev\n"); + return -EFAULT; + } + + numvfs = (numvfs > totalvfs) ? totalvfs : numvfs; + if (numvfs) + return sriov_enable(accel_dev, numvfs); + else + return sriov_disable(accel_dev); +} +EXPORT_SYMBOL_GPL(zsda_sriov_configure); + +pci_ers_result_t zsda_err_detected(struct pci_dev *pdev, + pci_channel_state_t state) +{ + struct accel_dev *accel_dev = acc_devmgr_pci_to_accel_dev(pdev); + + dev_info(&pdev->dev, "Acceleration driver hardware error detected.\n"); + if (!accel_dev) { + dev_err(&pdev->dev, "Can't find acceleration device\n"); + return PCI_ERS_RESULT_DISCONNECT; + } + if (!accel_dev->is_vf) { + dev_err(&pdev->dev, "accel is pf\n"); + pci_clear_master(pdev); + } + + if (state == pci_channel_io_perm_failure) { + dev_err(&pdev->dev, "Can't recover from device error\n"); + return PCI_ERS_RESULT_DISCONNECT; + } + return PCI_ERS_RESULT_NEED_RESET; +} +EXPORT_SYMBOL_GPL(zsda_err_detected); + +pci_ers_result_t zsda_slot_reset(struct pci_dev *pdev) +{ + struct accel_dev *accel_dev = acc_devmgr_pci_to_accel_dev(pdev); + + if (!accel_dev) { + pr_err("ZSDA: Can't find acceleration device\n"); + return PCI_ERS_RESULT_DISCONNECT; + } + if (accel_dev->is_vf) + return PCI_ERS_RESULT_RECOVERED; + + pci_aer_clear_nonfatal_status(pdev); + sriov_disable(accel_dev); + + return PCI_ERS_RESULT_RECOVERED; +} +EXPORT_SYMBOL_GPL(zsda_slot_reset); + +void zsda_reset_prepare(struct pci_dev *pdev) +{ + struct accel_dev *accel_dev = acc_devmgr_pci_to_accel_dev(pdev); + + if (!accel_dev) { + dev_err(&pdev->dev, " Can't find acceleration device\n"); + return; + } + zsda_release_qps(accel_dev); + zsda_free_irqs(accel_dev); + sriov_disable(accel_dev); +} +EXPORT_SYMBOL_GPL(zsda_reset_prepare); + +void zsda_reset_done(struct pci_dev *pdev) +{ + struct accel_dev *accel_dev = acc_devmgr_pci_to_accel_dev(pdev); + + if (!accel_dev) { + dev_err(&pdev->dev, " Can't find acceleration device\n"); + return; + } + zsda_dev_int(accel_dev); + zsda_request_irqs(accel_dev); + set_bit(ZSDA_STATUS_STARTED, &accel_dev->status); +} +EXPORT_SYMBOL_GPL(zsda_reset_done); + +void zsda_resume(struct pci_dev *pdev) +{ + dev_info(&pdev->dev, "Acceleration driver reset completed\n"); + dev_info(&pdev->dev, "Device is up and running\n"); +} +EXPORT_SYMBOL_GPL(zsda_resume); diff --git a/src/crypto/zsda/accdevice/zsda_common/zsda_pci.h b/src/crypto/zsda/accdevice/zsda_common/zsda_pci.h new file mode 100644 index 0000000..94b1eba --- /dev/null +++ b/src/crypto/zsda/accdevice/zsda_common/zsda_pci.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright(c) 2024 ZTE Corporation */ +#ifndef ZSDA_PCI_H +#define ZSDA_PCI_H + +pci_ers_result_t zsda_err_detected(struct pci_dev *pdev, + pci_channel_state_t state); +pci_ers_result_t zsda_slot_reset(struct pci_dev *pdev); +void zsda_reset_prepare(struct pci_dev *pdev); +void zsda_reset_done(struct pci_dev *pdev); +void zsda_resume(struct pci_dev *pdev); +int zsda_sriov_configure(struct pci_dev *pdev, int numvfs); + +#endif diff --git a/src/crypto/zsda/accdevice/zsda_common/zsda_qp.c b/src/crypto/zsda/accdevice/zsda_common/zsda_qp.c new file mode 100644 index 0000000..c9d8203 --- /dev/null +++ b/src/crypto/zsda/accdevice/zsda_common/zsda_qp.c @@ -0,0 +1,674 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright(c) 2024 ZTE Corporation */ +#include +#include +#include "acc_addr.h" +#include "zsda_common_drv.h" +#include "acc_dev.h" + +#define RING_DIR_TX 0 +#define RING_DIR_RX 1 +#define CRYPTO_WQE_SIZE 128 +#define CRYPTO_CQE_SIZE 16 +#define MAX_RETRY_TIMES 30 + +static uint8_t crc8_table[256] = { + 0x0, 0x41, 0x13, 0x52, 0x26, 0x67, 0x35, 0x74, 0x4c, 0xd, 0x5f, 0x1e, + 0x6a, 0x2b, 0x79, 0x38, 0x9, 0x48, 0x1a, 0x5b, 0x2f, 0x6e, 0x3c, 0x7d, + 0x45, 0x4, 0x56, 0x17, 0x63, 0x22, 0x70, 0x31, 0x12, 0x53, 0x1, 0x40, + 0x34, 0x75, 0x27, 0x66, 0x5e, 0x1f, 0x4d, 0xc, 0x78, 0x39, 0x6b, 0x2a, + 0x1b, 0x5a, 0x8, 0x49, 0x3d, 0x7c, 0x2e, 0x6f, 0x57, 0x16, 0x44, 0x5, + 0x71, 0x30, 0x62, 0x23, 0x24, 0x65, 0x37, 0x76, 0x2, 0x43, 0x11, 0x50, + 0x68, 0x29, 0x7b, 0x3a, 0x4e, 0xf, 0x5d, 0x1c, 0x2d, 0x6c, 0x3e, 0x7f, + 0xb, 0x4a, 0x18, 0x59, 0x61, 0x20, 0x72, 0x33, 0x47, 0x6, 0x54, 0x15, + 0x36, 0x77, 0x25, 0x64, 0x10, 0x51, 0x3, 0x42, 0x7a, 0x3b, 0x69, 0x28, + 0x5c, 0x1d, 0x4f, 0xe, 0x3f, 0x7e, 0x2c, 0x6d, 0x19, 0x58, 0xa, 0x4b, + 0x73, 0x32, 0x60, 0x21, 0x55, 0x14, 0x46, 0x7, 0x48, 0x9, 0x5b, 0x1a, + 0x6e, 0x2f, 0x7d, 0x3c, 0x4, 0x45, 0x17, 0x56, 0x22, 0x63, 0x31, 0x70, + 0x41, 0x0, 0x52, 0x13, 0x67, 0x26, 0x74, 0x35, 0xd, 0x4c, 0x1e, 0x5f, + 0x2b, 0x6a, 0x38, 0x79, 0x5a, 0x1b, 0x49, 0x8, 0x7c, 0x3d, 0x6f, 0x2e, + 0x16, 0x57, 0x5, 0x44, 0x30, 0x71, 0x23, 0x62, 0x53, 0x12, 0x40, 0x1, + 0x75, 0x34, 0x66, 0x27, 0x1f, 0x5e, 0xc, 0x4d, 0x39, 0x78, 0x2a, 0x6b, + 0x6c, 0x2d, 0x7f, 0x3e, 0x4a, 0xb, 0x59, 0x18, 0x20, 0x61, 0x33, 0x72, + 0x6, 0x47, 0x15, 0x54, 0x65, 0x24, 0x76, 0x37, 0x43, 0x2, 0x50, 0x11, + 0x29, 0x68, 0x3a, 0x7b, 0xf, 0x4e, 0x1c, 0x5d, 0x7e, 0x3f, 0x6d, 0x2c, + 0x58, 0x19, 0x4b, 0xa, 0x32, 0x73, 0x21, 0x60, 0x14, 0x55, 0x7, 0x46, + 0x77, 0x36, 0x64, 0x25, 0x51, 0x10, 0x42, 0x3, 0x3b, 0x7a, 0x28, 0x69, + 0x1d, 0x5c, 0xe, 0x4f +}; + +static void zsda_release_dma(struct accel_dev *accel_dev, struct qp_srv *qp); + +static uint8_t zsda_crc8(uint8_t *message, int length) +{ + uint8_t crc = 0; + int i; + + for (i = 0; i < length; i++) + crc = crc8_table[crc ^ message[i]]; + return crc; +} + +void set_reg_8(void __iomem *addr, uint8_t val0, uint8_t val1, uint8_t val2, + uint8_t val3) +{ + uint32_t value; + uint8_t val[4]; + + val[0] = val0; + val[1] = val1; + val[2] = val2; + val[3] = val3; + memcpy(&value, val, sizeof(val)); + ZSDA_REG_WR(addr, 0, value); +} + +uint8_t get_reg_8(void __iomem *addr, uint8_t offset) +{ + uint32_t val = ZSDA_REG_RD(addr, 0); + + return *(((uint8_t *)&val) + offset); +} + +void zsda_admin_q_start(struct accel_dev *accel_dev) +{ + void __iomem *base = accel_dev->accel_pci_dev.pci_bars[ZSDA_BAR0].virt_addr; + + ZSDA_REG_WR(base, ZSDA_ADMIN_Q_START, VALID); +} + +int zsda_admin_msg_init(struct accel_pci *accel_pci_dev) +{ + void __iomem *base = accel_pci_dev->pci_bars[ZSDA_BAR0].virt_addr; + + set_reg_8(base + ZSDA_ADMIN_WQ_BASE7, 0, 0, MAGIC_RECV, 0); + set_reg_8(base + ZSDA_ADMIN_CQ_BASE7, 0, 0, MAGIC_RECV, 0); + return 0; +} + +int zsda_send_admin_msg(struct accel_pci *accel_pci_dev, void *req, uint32_t len) +{ + int i; + uint8_t wq_flag, crc; + uint32_t db, admin_db; + uint32_t retry = ADMIN_RETRY_TIMES; + void __iomem *base = accel_pci_dev->pci_bars[ZSDA_BAR0].virt_addr; + + if (len > ADMIN_BUF_DATA_LEN) + return -EINVAL; + + for (i = 0; i < ADMIN_BUF_DATA_LEN / sizeof(uint32_t); i++) + ZSDA_REG_WR(base, ZSDA_ADMIN_WQ(i), *((uint32_t *)req + i)); + + crc = zsda_crc8((uint8_t *)req, ADMIN_BUF_DATA_LEN); + set_reg_8(base + ZSDA_ADMIN_WQ_BASE7, crc, ADMIN_VER, MAGIC_SEND, 0); + admin_db = ZSDA_REG_RD(base, ZSDA_ADMIN_WQ_TAIL); + db = zsda_modulo(admin_db, 0x1ff); + ZSDA_REG_WR(base, ZSDA_ADMIN_WQ_TAIL, db); + + do { + msleep(20); + wq_flag = get_reg_8(base + ZSDA_ADMIN_WQ_BASE7, 2); + if (wq_flag == MAGIC_RECV) + return 0; + } while (retry--); + set_reg_8(base + ZSDA_ADMIN_WQ_BASE7, 0, crc, ADMIN_VER, 0); + return -EIO; +} + +int zsda_recv_admin_msg(struct accel_pci *accel_pci_dev, void *resp, + uint32_t len) +{ + int i; + uint8_t cq_flag, crc; + uint32_t retry = ADMIN_RETRY_TIMES; + uint8_t buf[ADMIN_BUF_TOTAL_LEN]; + uint32_t resp_buff[ADMIN_BUF_DATA_LEN / sizeof(uint32_t)] = { 0 }; + void __iomem *base = accel_pci_dev->pci_bars[ZSDA_BAR0].virt_addr; + struct device *dev = &accel_pci_dev->pci_dev->dev; + + if (len > ADMIN_BUF_DATA_LEN) + return -EINVAL; + do { + msleep(20); + cq_flag = get_reg_8(base + ZSDA_ADMIN_CQ_BASE7, 2); + if (cq_flag == MAGIC_SEND) + break; + } while (--retry); + if (!retry) { + dev_err(dev, "cq_flag error 0x%x\n", cq_flag); + return -EIO; + } + + for (i = 0; i < (ADMIN_BUF_DATA_LEN / sizeof(uint32_t)); i++) + resp_buff[i] = ZSDA_REG_RD(base, ZSDA_ADMIN_CQ(i)); + + memcpy(buf, resp_buff, ADMIN_BUF_DATA_LEN); + crc = get_reg_8(base + ZSDA_ADMIN_CQ_BASE7, 0); + set_reg_8(base + ZSDA_ADMIN_CQ_BASE7, 0, 0, MAGIC_RECV, 0); + if (crc != zsda_crc8(buf, ADMIN_BUF_DATA_LEN)) { + dev_err(dev, "get crc error!"); + return -EIO; + } + memcpy(resp, buf, len); + + return 0; +} + +int zsda_function_resume(struct accel_dev *accel_dev) +{ + int ret = 0; + struct zsda_admin_req_qcfg req = { 0 }; + struct zsda_admin_resp_qcfg resp = { 0 }; + struct accel_pci accel_pci_dev = accel_dev->accel_pci_dev; + + zsda_admin_msg_init(&accel_pci_dev); + req.msg_type = ZSDA_FLR_SET_FUNCTION; + ret = zsda_send_admin_msg(&accel_pci_dev, &req, sizeof(req)); + if (ret) { + dev_err(&GET_DEV(accel_dev), "Failed to send resume msg\n"); + return -EBUSY; + } + ret = zsda_recv_admin_msg(&accel_pci_dev, &resp, sizeof(resp)); + if (ret) { + dev_err(&GET_DEV(accel_dev), "Failed to recv resume msg\n"); + return -EBUSY; + } + return ret; +} + +enum zsda_service_type zsda_get_queue_cfg_by_id(struct accel_dev *accel_dev, + int qid, struct qinfo *qcfg) +{ + struct accel_pci accel_pci_dev = accel_dev->accel_pci_dev; + struct zsda_admin_req_qcfg req = { 0 }; + struct zsda_admin_resp_qcfg resp = { 0 }; + int ret = 0; + + zsda_admin_msg_init(&accel_pci_dev); + + req.msg_type = ZSDA_ADMIN_QUEUE_CFG_REQ; + req.qid = (unsigned char)qid; + ret = zsda_send_admin_msg(&accel_pci_dev, &req, sizeof(req)); + if (ret) { + dev_err(&GET_DEV(accel_dev), "Failed send to admin to get ZSDA queue configure qid = %d, request statu:%d\n", + qid, ret); + goto err_out; + } + + ret = zsda_recv_admin_msg(&accel_pci_dev, &resp, sizeof(resp)); + if (ret) { + dev_err(&GET_DEV(accel_dev), "Failed recv from admin to get ZSDA queue configure qid = %d, response status:%d\n", + qid, ret); + goto err_out; + } + + if ((resp.msg_type == ZSDA_ADMIN_QUEUE_CFG_RESP) && + (resp.qcfg.q_type < ZSDA_SERVICE_COUNT)) { + memcpy(qcfg, &resp.qcfg, sizeof(struct qinfo)); + return resp.qcfg.q_type; + } +err_out: + return ZSDA_SERVICE_COUNT; +} + +static int clear_io_queue(void __iomem *base, uint32_t id) +{ + int retry = 0; + + ZSDA_REG_WR(base, ZSDA_IO_Q_CLR_RESP(id), INVALID); + ZSDA_REG_WR(base, ZSDA_IO_Q_CLR(id), VALID); + while (ZSDA_REG_RD(base, ZSDA_IO_Q_CLR_RESP(id)) == INVALID) { + retry++; + if (retry >= MAX_RETRY_TIMES) + return -EBUSY; + msleep(20); + } + return 0; +} + +static void restore_io_queue(void __iomem *base, uint32_t id) +{ + ZSDA_REG_WR(base, ZSDA_IO_Q_CLR(id), INVALID); +} + +static int zsda_queue_create(struct accel_dev *accel_dev, + struct zsda_queue *queue, struct qinfo *qcfg, + uint8_t dir) +{ + uint64_t iova; + uint8_t *addr; + uint16_t desc_size = (dir == RING_DIR_TX) ? + CRYPTO_WQE_SIZE : + CRYPTO_CQE_SIZE; // wqe or cq size + uint32_t queue_size_bytes = ZSDA_MAX_DESC * desc_size; // queue size + + addr = dma_alloc_coherent(&GET_DEV(accel_dev), queue_size_bytes, &iova, + GFP_KERNEL); + if (!addr) + return -EFAULT; + + queue->base_phys_addr = iova; + queue->base_addr = addr; + queue->modulo_mask = 0x1ff; + queue->head = (dir == RING_DIR_TX) ? qcfg->wq_head : qcfg->cq_head; + queue->tail = (dir == RING_DIR_TX) ? qcfg->wq_tail : qcfg->cq_tail; + queue->msg_size = desc_size; + if (queue->head == 0 && queue->tail == 0) + qcfg->cycle += 1; + queue->valid = qcfg->cycle & 0xff; + queue->sid = 0; + queue->queue_size = ZSDA_MAX_DESC; + queue->io_addr = accel_dev->accel_pci_dev.pci_bars[ZSDA_BAR0].virt_addr; + memset(queue->base_addr, 0, queue_size_bytes); + + return 0; +} + +static int build_qps(struct accel_dev *accel_dev, struct qp_srv *qp, + struct qinfo *qcfg, uint32_t qid) +{ + int ret = 0; + + qp->type = qcfg->q_type; + qp->qid = qid; + spin_lock_init(&qp->lock); + atomic_set(&qp->unqueued, 0); + ret = zsda_queue_create(accel_dev, &qp->tx_q, qcfg, RING_DIR_TX); + if (unlikely(ret)) { + dev_err(&GET_DEV(accel_dev), "Tx queue create failed queue_pair_id=%u\n", qid); + return ret; + } + ZSDA_WQ_RING_BASE(qp->tx_q.io_addr, qid, qp->tx_q.base_phys_addr); + + ret = zsda_queue_create(accel_dev, &qp->rx_q, qcfg, RING_DIR_RX); + if (unlikely(ret)) { + dev_err(&GET_DEV(accel_dev), "Rx queue create failed queue_pair_id=%hu\n", qid); + return ret; + } + ZSDA_CQ_RING_BASE(qp->rx_q.io_addr, qid, qp->rx_q.base_phys_addr); + + return ret; +} + +int start_qp(void __iomem *base, uint32_t qid) +{ + int retry = 0; + + ZSDA_REG_WR(base, ZSDA_IO_Q_START(qid), Q_START); + while (ZSDA_REG_RD(base, ZSDA_IO_Q_START(qid)) == INVALID) { + retry++; + if (retry >= MAX_RETRY_TIMES) + return -EBUSY; + msleep(20); + } + return 0; +} + +int stop_qp(void __iomem *base, uint32_t qid) +{ + int retry = 0; + + ZSDA_REG_WR(base, ZSDA_IO_Q_STOP_RESP(qid), INVALID); + ZSDA_REG_WR(base, ZSDA_IO_Q_STOP(qid), Q_STOP); + + while (ZSDA_REG_RD(base, ZSDA_IO_Q_STOP_RESP(qid)) == INVALID) { + retry++; + if (retry >= MAX_RETRY_TIMES) + return -EBUSY; + msleep(20); + } + ZSDA_REG_WR(base, ZSDA_IO_Q_STOP_RESP(qid), INVALID); + + return 0; +} + +int zsda_qp_int(struct accel_dev *accel_dev, struct qp_srv *qp, + struct qinfo *qcfg, uint32_t qid) +{ + void __iomem *base = accel_dev->accel_pci_dev.pci_bars[ZSDA_BAR0].virt_addr; + int ret = 0; + + ret = build_qps(accel_dev, qp, qcfg, qid); + if (unlikely(ret)) + return ret; + + ret = clear_io_queue(base, qid); + if (unlikely(ret)) + return ret; + + restore_io_queue(base, qid); + + ret = stop_qp(base, qid); + if (unlikely(ret)) + return ret; + + ret = start_qp(base, qid); + if (unlikely(ret)) + return ret; + + return ret; +} + +static void zsda_add_qps(struct accel_dev *accel_dev, struct qp_srv *qp, + enum zsda_service_type type) +{ + struct zsda_qp *alg_qp = &accel_dev->cfg->alg_qps[type]; + + qp->used = true; + alg_qp->qp_num++; + INIT_LIST_HEAD(&qp->list); + mutex_lock(&alg_qp->lock); + list_add_tail(&qp->list, &alg_qp->list); + mutex_unlock(&alg_qp->lock); +} + +int zsda_dev_int(struct accel_dev *accel_dev) +{ + int i = 0, ret = 0; + uint32_t qp_num; + struct qinfo qcfg; + struct qp_srv *qp; + enum zsda_service_type type = ZSDA_SERVICE_COUNT; + void __iomem *base = accel_dev->accel_pci_dev.pci_bars[ZSDA_BAR0].virt_addr; + + for (i = 0; i < ZSDA_SERVICE_COUNT; i++) { + atomic_set(&accel_dev->cfg->backlog[i].inflights, 0); + INIT_LIST_HEAD(&accel_dev->cfg->backlog[i].list); + spin_lock_init(&accel_dev->cfg->backlog[i].lock); + + INIT_LIST_HEAD(&accel_dev->cfg->alg_qps[i].list); + mutex_init(&accel_dev->cfg->alg_qps[i].lock); + } + + zsda_admin_q_start(accel_dev); + ret = zsda_function_resume(accel_dev); + if (unlikely(ret)) + return ret; + + qp_num = MIN(ZSDA_REG_RD(base, 0) + 1, MAX_RING_NUM); + for (i = 0; i < qp_num; i++) { + ZSDA_REG_WR(base, ZSDA_QUE_DB_INIT(i), 0); + + type = zsda_get_queue_cfg_by_id(accel_dev, i, &qcfg); + if (type < ZSDA_SERVICE_ENCRYPT || + type > ZSDA_SERVICE_DECRYPT) + continue; + dev_info(&GET_DEV(accel_dev), "qid %d; type %d\n", i, type); + + qp = kzalloc_node(sizeof(struct qp_srv), GFP_KERNEL, + dev_to_node(&GET_DEV(accel_dev))); + + ret = zsda_qp_int(accel_dev, qp, &qcfg, i); + if (unlikely(ret)) { + zsda_release_dma(accel_dev, qp); + kfree(qp); + continue; + } + zsda_add_qps(accel_dev, qp, type); + } + + if (list_empty(&accel_dev->cfg->alg_qps[ZSDA_SERVICE_ENCRYPT].list) || + list_empty(&accel_dev->cfg->alg_qps[ZSDA_SERVICE_DECRYPT].list)){ + dev_info(&GET_DEV(accel_dev), "%s don't support Crypto", accel_dev->name); + return -EFAULT; + } + + return 0; +} +EXPORT_SYMBOL_GPL(zsda_dev_int); + +static void zsda_release_dma(struct accel_dev *accel_dev, struct qp_srv *qp) +{ + struct zsda_queue *tx_qp = &qp->tx_q; + struct zsda_queue *rx_qp = &qp->rx_q; + + if (tx_qp->base_addr != NULL) { + memset(tx_qp->base_addr, 0x0, + tx_qp->queue_size * tx_qp->msg_size); + dma_free_coherent(&GET_DEV(accel_dev), + (tx_qp->msg_size * tx_qp->queue_size), + tx_qp->base_addr, tx_qp->base_phys_addr); + } + if (rx_qp->base_addr != NULL) { + memset(rx_qp->base_addr, 0x0, + rx_qp->queue_size * rx_qp->msg_size); + dma_free_coherent(&GET_DEV(accel_dev), + (rx_qp->msg_size * rx_qp->queue_size), + rx_qp->base_addr, rx_qp->base_phys_addr); + } +} + +void zsda_release_qps(struct accel_dev *accel_dev) +{ + int i; + struct zsda_qp *alg_qp; + struct qp_srv *qp, *tmp; + void __iomem *base = accel_dev->accel_pci_dev.pci_bars[ZSDA_BAR0].virt_addr; + + clear_bit(ZSDA_STATUS_STARTED, &accel_dev->status); + for (i = 0; i < ZSDA_SERVICE_COUNT; i++) { + alg_qp = &accel_dev->cfg->alg_qps[i]; + mutex_lock(&alg_qp->lock); + list_for_each_entry_safe(qp, tmp, &alg_qp->list, list) { + if (unlikely(!qp->used)) + continue; + + while (atomic_read(&qp->unqueued)) + msleep(100); + + clear_io_queue(base, qp->qid); + + stop_qp(base, qp->qid); + + zsda_release_dma(accel_dev, qp); + list_del(&qp->list); + kfree(qp); + } + mutex_unlock(&alg_qp->lock); + } +} +EXPORT_SYMBOL_GPL(zsda_release_qps); + +struct qp_srv *get_free_qp(struct device_cfg_data *cfg, + enum zsda_service_type type) +{ + struct qp_srv *qp = NULL; + struct zsda_qp *alg_qp = &cfg->alg_qps[type]; + + list_for_each_entry(qp, &alg_qp->list, list) { + if (unlikely(!qp->used)) + continue; + if (atomic_read(&qp->unqueued) < ZSDA_MAX_DESC) { + return qp; + } + } + + return NULL; +} + +int find_next_free_cookie(struct zsda_queue *queue, void **op_cookie) +{ + uint32_t tail = queue->tail; + + if (tail >= ZSDA_MAX_DESC) + return -EINVAL; + if (op_cookie[tail] == NULL) + return tail; + else + return -EINVAL; +} + +void zsda_build_req(struct zsda_crypto_request *zsda_req, + struct zsda_crypto_ctx *ctx, enum zsda_service_type type) +{ + struct zsda_wqe *wqe = &(zsda_req->wqe); + struct cookie *cookie = zsda_req->cookie; + + wqe->tx_sgl_type = SGL_ELM_TYPE_LIST; + wqe->rx_sgl_type = SGL_ELM_TYPE_LIST; + wqe->tx_addr = cookie->dst_addr; + wqe->tx_length = zsda_req->skcipher_req->cryptlen; + wqe->rx_addr = cookie->src_addr; + wqe->rx_length = zsda_req->skcipher_req->cryptlen; + wqe->cfg.crypto.lbads = 0; + + reverse_memcpy(wqe->cfg.crypto.slba_l, + zsda_req->skcipher_req->iv + ZSDA_XTS_IV_SLBA_OFF, + sizeof(wqe->cfg.crypto.slba_l)); + reverse_memcpy(wqe->cfg.crypto.slba_h, zsda_req->skcipher_req->iv, + sizeof(wqe->cfg.crypto.slba_h)); + + if (type == ZSDA_SERVICE_ENCRYPT) { + if (ctx->keylen == 32) + wqe->op_code = ZSDA_OPC_EC_AES_XTS_256; + else + wqe->op_code = ZSDA_OPC_EC_AES_XTS_512; + memcpy(wqe->cfg.crypto.key, ctx->encry_key, + sizeof(wqe->cfg.crypto.key)); + } else { + if (ctx->keylen == 32) + wqe->op_code = ZSDA_OPC_DC_AES_XTS_256; + else + wqe->op_code = ZSDA_OPC_DC_AES_XTS_512; + memcpy(wqe->cfg.crypto.key, ctx->decry_key, + sizeof(wqe->cfg.crypto.key)); + } +} + +int enqueue(struct zsda_crypto_request *zsda_req, enum zsda_service_type type, + bool soft) +{ + int tx_tail; + struct qp_srv *qp; + struct zsda_queue *tx_queue; + struct accel_dev *acc_dev = zsda_req->ablkcipher_ctx->acc_dev; + + qp = get_free_qp(acc_dev->cfg, type); + if (qp == NULL) + return -EBUSY; + + tx_queue = &qp->tx_q; + spin_lock_bh(&qp->lock); + tx_tail = find_next_free_cookie(tx_queue, qp->op_cookies); + if (unlikely(tx_tail < 0)) { + spin_unlock_bh(&qp->lock); + return -EBUSY; + } + qp->op_cookies[tx_tail] = zsda_req->cookie; + zsda_req->wqe.valid = tx_queue->valid; + zsda_req->wqe.sid = tx_tail; + + memcpy(tx_queue->base_addr + tx_tail * tx_queue->msg_size, + &zsda_req->wqe, tx_queue->msg_size); + + tx_queue->tail = (tx_tail + 1) & tx_queue->modulo_mask; + + if (tx_queue->tail == 0) + tx_queue->valid = (tx_queue->valid+1) & 0xff; + // if (zsda_req->wqe.sid == 0x1fe) { + // printk("%s soft:%d qid:%d, valid:0x%x, len:0x%x, sid:0x%x op_code:0x%x\n", + // acc_dev->name, soft, qp->qid, zsda_req->wqe.valid, + // zsda_req->wqe.tx_length, zsda_req->wqe.sid, + // zsda_req->wqe.op_code); + // } + if (type == ZSDA_SERVICE_ENCRYPT) + acc_dev->zsda_dbg.encry_enq++; + else + acc_dev->zsda_dbg.decry_enq++; + atomic_inc(&qp->unqueued); + WRITE_WQ_TAIL(tx_queue->io_addr, qp->qid, tx_queue->tail); + + spin_unlock_bh(&qp->lock); + return 0; +} +EXPORT_SYMBOL_GPL(enqueue); + +void zsda_free_sgl(struct accel_dev *acc_dev, struct cookie *cookie) +{ + struct device *dev = &GET_DEV(acc_dev); + phys_addr_t blp = 0, bloutp = 0; + uint32_t n; + size_t sz; + int i; + + n = cookie->src_n; + sz = PAGE_ALIGN(n * sizeof(struct zsda_buf)); + for (i = 0; i < n; i++) { + if (!dma_mapping_error(dev, cookie->src_buf[i].addr)){ + dma_unmap_single(dev, cookie->src_buf[i].addr, + cookie->src_buf[i].len, + DMA_BIDIRECTIONAL); + } + } + blp = cookie->src_addr; + + if (!dma_mapping_error(dev, blp)) + dma_unmap_single(dev, blp, sz, DMA_TO_DEVICE); + kfree(cookie->src_buf); + + n = cookie->dst_n; + sz = PAGE_ALIGN(n * sizeof(struct zsda_buf)); + for (i = 0; i < n; i++) { + if (!dma_mapping_error(dev, cookie->dst_buf[i].addr)){ + dma_unmap_single(dev, cookie->dst_buf[i].addr, + cookie->dst_buf[i].len, + DMA_BIDIRECTIONAL); + } + } + bloutp = cookie->dst_addr ; + + if (!dma_mapping_error(dev, bloutp)) + dma_unmap_single(dev, bloutp, sz, DMA_TO_DEVICE); + kfree(cookie->dst_buf); + + kfree(cookie); +} + +void dequeue(struct accel_dev *acc_dev, struct qp_srv *qp) +{ + struct zsda_queue *rx_queue = &qp->rx_q; + struct zsda_cqe *cqe = NULL; + struct cookie *cookie = NULL; + uint16_t cq_head = rx_queue->sid; + int unqueued = atomic_read(&qp->unqueued); + bool dealed = 0; + + while (unqueued > 0) { + cqe = (struct zsda_cqe *)(rx_queue->base_addr + + cq_head * rx_queue->msg_size); + if (cqe_err1(cqe->err1) || !cqe_valid(cqe->err1) || + cqe->err0 != 0x0) { + if (!cqe->err1) + break; + dev_err(&GET_DEV(acc_dev), "qid:%d error cq_head:0x%x sid:0x%x, state:0x%x, real_len:0x%x, err0:0x%x, err1:0x%x unqueued:0x%x\n", + qp->qid, cq_head, cqe->sid, cqe->state, + cqe->tx_real_length, cqe->err0, cqe->err1, + unqueued); + } + dealed = 1; + cq_head = cqe->sid; + if (cq_head >= ZSDA_MAX_DESC) + break; + cookie = (struct cookie *)qp->op_cookies[cq_head]; + + cookie->zsda_req->cb(cqe, cookie->zsda_req); + zsda_free_sgl(acc_dev, cookie); + memset(cqe, 0, sizeof(struct zsda_cqe)); + qp->op_cookies[cq_head] = NULL; + unqueued = atomic_sub_return(1, &qp->unqueued); + + cq_head = (cq_head + 1) & rx_queue->modulo_mask; + rx_queue->sid = cq_head; + // if (cqe->sid == 0x1fe) { + // printk("qid:%d cycle:0x%x cq_head:0x%x sid:0x%x, unqueued:0x%x\n", + // qp->qid, cqe->valid, cq_head, cqe->sid, unqueued); + // } + + if (qp->type == ZSDA_SERVICE_ENCRYPT) + acc_dev->zsda_dbg.encry_deq++; + else + acc_dev->zsda_dbg.decry_deq++; + } + WRITE_CQ_HEAD(rx_queue->io_addr, qp->qid, rx_queue->sid); +} diff --git a/src/crypto/zsda/accdevice/zsda_common/zsda_qp.h b/src/crypto/zsda/accdevice/zsda_common/zsda_qp.h new file mode 100644 index 0000000..605b2ef --- /dev/null +++ b/src/crypto/zsda/accdevice/zsda_common/zsda_qp.h @@ -0,0 +1,143 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright(c) 2024 ZTE Corporation */ +#ifndef ZSDA_QP_H +#define ZSDA_QP_H + +// #include +#include "zsda_alg.h" + +#define ZSDA_MAX_DESC 512 +#define MAX_RING_NUM 128 +#define ZSDA_SGL_MAX_NUMBER 512 +#define ZSDA_XTS_IV_SLBA_OFF (8) + +#define ZSDA_OPC_EC_AES_XTS_256 0x0 +#define ZSDA_OPC_EC_AES_XTS_512 0x01 +#define ZSDA_OPC_DC_AES_XTS_256 0x08 +#define ZSDA_OPC_DC_AES_XTS_512 0x09 + +#define MAGIC_SEND 0xab +#define MAGIC_RECV 0xcd +#define ADMIN_VER 1 + +#define MIN(a, b) (a < b ? a : b) + +enum zsda_service_type { + ZSDA_SERVICE_COMPRESSION = 0, + ZSDA_SERVICE_DECOMPRESSION = 1, + ZSDA_SERVICE_ENCRYPT, + ZSDA_SERVICE_DECRYPT, + ZSDA_SERVICE_HASH_ENCODE, + ZSDA_SERVICE_DIFF, + ZSDA_SERVICE_EC_ENCODE, + ZSDA_SERVICE_EC_DECODE, + ZSDA_SERVICE_COUNT +}; + +enum zsda_admin_msg_id { + ZSDA_ADMIN_VERSION_REQ = 0, // 版本信息 + ZSDA_ADMIN_VERSION_RESP, + ZSDA_ADMIN_QUEUE_CFG_REQ, // 算法类型 + ZSDA_ADMIN_QUEUE_CFG_RESP, + ZSDA_ADMIN_QUEUE_CYCLE_REQ, // get cycle值 + ZSDA_ADMIN_QUEUE_CYCLE_RESP, + ZSDA_ADMIN_SET_CYCLE_REQ, // set cycle值 + ZSDA_ADMIN_SET_CYCLE_RESP, + + ZSDA_MIG_STATE_WARNING, + ZSDA_ADMIN_RESERVE, + ZSDA_FLR_SET_FUNCTION, // 关闭flr屏蔽寄存器 + ZSDA_ADMIN_MSG_VALID, + ZSDA_ADMIN_INT_TEST +}; + +enum sgl_elment_type { + SGL_ELM_TYPE_PHYS_ADDR = 1, + SGL_ELM_TYPE_LIST, + SGL_ELM_TYPE_LIST_ADDR +}; + +struct qinfo { + uint16_t q_type; + uint16_t wq_tail; + uint16_t wq_head; + uint16_t cq_tail; + uint16_t cq_head; + uint16_t cycle; +}; + +struct zsda_admin_req_qcfg { + uint16_t msg_type; + uint8_t qid; + uint8_t data[25]; +}; + +struct zsda_admin_resp_qcfg { + uint16_t msg_type; + struct qinfo qcfg; + uint8_t data[14]; +}; + +struct zsda_queue { + void __iomem *io_addr; + uint8_t *base_addr; /* Base address */ + uint64_t base_phys_addr; /* Queue physical address */ + uint32_t head; /* Shadow copy of the head */ + uint32_t tail; /* Shadow copy of the tail */ + uint32_t msg_size; + uint32_t queue_size; //512 + + /* HW queue offset */ + uint32_t csr_head; /* last written head value */ + uint32_t csr_tail; /* last written tail value */ + uint16_t modulo_mask; + /* number of responses processed since last CSR head write */ + uint8_t valid; + uint8_t rsv; + uint16_t sid; +}; + +struct qp_srv { + uint32_t qid; + enum zsda_service_type type; + bool used; + struct zsda_queue tx_q; + struct zsda_queue rx_q; + void *op_cookies[ZSDA_MAX_DESC]; + spinlock_t lock; + /**< zsda device this qp is on */ + atomic_t unqueued; + struct list_head list; +}; + +struct zsda_backlog { + atomic_t inflights; + struct list_head list; + spinlock_t lock; /* protects backlog list */ +}; + +struct zsda_qp { + uint32_t qp_num; + uint64_t enqueue; + uint64_t dequeue; + atomic_t inflights; + struct list_head list; + struct mutex lock; +}; + +#define cqe_valid(value) (value & 0x8000) +#define cqe_err1(value) (value & 0x7fff) + +static inline uint32_t zsda_modulo(uint32_t data, uint32_t modulo_mask) +{ + return (data) & (modulo_mask); +} + +int zsda_dev_int(struct accel_dev *accel_dev); +void zsda_release_qps(struct accel_dev *accel_dev); +void zsda_build_req(struct zsda_crypto_request *zsda_req, + struct zsda_crypto_ctx *ctx, enum zsda_service_type type); +int enqueue(struct zsda_crypto_request *zsda_req, enum zsda_service_type type, + bool soft); +void dequeue(struct accel_dev *acc_dev, struct qp_srv *qp); +#endif diff --git a/src/crypto/zsda/accdevice/zsda_pf/Makefile b/src/crypto/zsda/accdevice/zsda_pf/Makefile new file mode 100644 index 0000000..f5b4168 --- /dev/null +++ b/src/crypto/zsda/accdevice/zsda_pf/Makefile @@ -0,0 +1,4 @@ +ccflags-y := -I$(src)/../../include +ccflags-y += -I$(src)/../zsda_common +obj-$(CONFIG_ACC_ZSDA_PF) += zsda_pf.o +zsda_pf-objs = zsda_drv.o diff --git a/src/crypto/zsda/accdevice/zsda_pf/zsda_drv.c b/src/crypto/zsda/accdevice/zsda_pf/zsda_drv.c new file mode 100644 index 0000000..ca39579 --- /dev/null +++ b/src/crypto/zsda/accdevice/zsda_pf/zsda_drv.c @@ -0,0 +1,237 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright(c) 2024 ZTE Corporation */ +#include +#include +#include +#include +#include +#include +#include "acc_version.h" +// #include "acc_compat.h" +#include "acc_dev.h" +#include "zsda_pci.h" +#include "zsda_manage.h" +#include "zsda_common_drv.h" + +#define PCI_VENDOR_ID_ZTE 0x1cf2 +#define ZSDA_PF_PCI_DEVICE_ID 0x8050 + +#define ZSDA_SYSTEM_DEVICE(device_id) \ + {PCI_DEVICE(PCI_VENDOR_ID_ZTE, device_id)} + +static const struct pci_device_id zsda_pf_pci_tbl[] = { + ZSDA_SYSTEM_DEVICE(ZSDA_PF_PCI_DEVICE_ID), + { + 0, + } +}; +MODULE_DEVICE_TABLE(pci, zsda_pf_pci_tbl); + +static int zsda_pf_probe(struct pci_dev *dev, const struct pci_device_id *ent); +static void zsda_pf_remove(struct pci_dev *dev); + +static const struct file_operations test_debugfs_ops = { + .open = zsda_seq_open, + .read = seq_read, + .write = zsda_seq_write, + .llseek = seq_lseek, + .release = single_release, +}; + +static const struct pci_error_handlers zsda_err_handler = { + .error_detected = zsda_err_detected, + .slot_reset = zsda_slot_reset, + .reset_prepare = zsda_reset_prepare, + .reset_done = zsda_reset_done, + .resume = zsda_resume, +}; + +static struct pci_driver zsda_pf_driver = { + .id_table = zsda_pf_pci_tbl, + .name = "ZSDA-PF", + .probe = zsda_pf_probe, + .remove = zsda_pf_remove, + .err_handler = &zsda_err_handler, +#ifndef NO_SRIOV_CONFIGURE + .sriov_configure = zsda_sriov_configure, +#endif +}; + +static void zsda_pf_cleanup_pci_dev(struct accel_dev *accel_dev) +{ + pci_release_regions(accel_dev->accel_pci_dev.pci_dev); + pci_disable_device(accel_dev->accel_pci_dev.pci_dev); +} + +static void zsda_pf_cleanup_accel(struct accel_dev *accel_dev) +{ + zsda_unmap_pci_bars(accel_dev); + + kfree(accel_dev->hw_data); + accel_dev->hw_data = NULL; + kfree(accel_dev->cfg); + accel_dev->cfg = NULL; + + debugfs_remove(accel_dev->debugfs_dir); + accel_dev->debugfs_dir = NULL; + acc_devmgr_rm_dev(accel_dev); +} + +static int zsda_pf_probe(struct pci_dev *pdev, const struct pci_device_id *ent) +{ + struct accel_dev *accel_dev; + struct accel_pci *accel_pci_dev; + struct device_hw_data *hw_data; + struct device_cfg_data *hw_cfg_data; + char name[ZSDA_DEVICE_NAME_LENGTH]; + int ret = 0; + + if ((num_possible_nodes() > 1) && (dev_to_node(&pdev->dev) < 0)) { + dev_err(&pdev->dev, "Invalid NUMA configuration.\n"); + return -EINVAL; + } + + accel_dev = kzalloc_node(sizeof(struct accel_dev), GFP_KERNEL, + dev_to_node(&pdev->dev)); + if (!accel_dev) + return -ENOMEM; + + accel_pci_dev = &(accel_dev->accel_pci_dev); + accel_pci_dev->pci_dev = pdev; + + acc_devmgr_add_dev(accel_dev); + + accel_dev->owner = THIS_MODULE; + hw_data = kzalloc_node(sizeof(struct device_hw_data), GFP_KERNEL, + dev_to_node(&pdev->dev)); + if (!hw_data) { + ret = -ENOMEM; + goto out_err; + } + accel_dev->hw_data = hw_data; + + hw_cfg_data = kzalloc_node(sizeof(struct device_cfg_data), GFP_KERNEL, + dev_to_node(&pdev->dev)); + if (!hw_cfg_data) { + ret = -ENOMEM; + goto out_err; + } + accel_dev->cfg = hw_cfg_data; + + snprintf(name, sizeof(name), "zsda_%04x:%02x:%02x.%d", + pci_domain_nr(accel_dev->accel_pci_dev.pci_dev->bus), + pdev->bus->number, PCI_SLOT(pdev->devfn), + PCI_FUNC(pdev->devfn)); + memcpy(accel_dev->name, name, sizeof(name)); + dev_info(&pdev->dev, "Probe %s\n", name); + + accel_dev->debugfs_dir = debugfs_create_dir(name, NULL); + if (!accel_dev->debugfs_dir) { + dev_err(&pdev->dev, "Could not create debugfs dir %s\n", name); + ret = -EINVAL; + goto out_err; + } + + if (!debugfs_create_file("ctrl", 0444, accel_dev->debugfs_dir, + accel_dev, &test_debugfs_ops)) { + ret = -EINVAL; + goto out_err; + } + + if (pci_enable_device(pdev)) { + ret = -EFAULT; + goto out_err; + } + + if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { + if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))) { + dev_err(&pdev->dev, "No usable DMA configuration\n"); + ret = -EFAULT; + goto out_err_disable; + } else { + pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); + } + } else { + pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); + } + + if (pci_request_regions(pdev, ZSDA_PF_DEVICE_NAME)) { + ret = -EFAULT; + goto out_err_disable; + } + + ret = zsda_map_pci_bars(accel_dev); + if (unlikely(ret)) + goto out_err_free_reg; + pci_set_master(pdev); + + if(zsda_dev_int(accel_dev)) + return ret; + + ret = zsda_request_irqs(accel_dev); + if (unlikely(ret)) + goto out_err_dev_release; + + set_bit(ZSDA_STATUS_STARTED, &accel_dev->status); + accel_dev->lkcf_en = true; + zsda_lkcf_register(); + + return ret; + +out_err_dev_release: + zsda_release_qps(accel_dev); +out_err_free_reg: + pci_release_regions(accel_pci_dev->pci_dev); +out_err_disable: + pci_disable_device(accel_pci_dev->pci_dev); +out_err: + zsda_pf_cleanup_accel(accel_dev); + kfree(accel_dev); + return ret; +} + +static void zsda_pf_remove(struct pci_dev *pdev) +{ + struct accel_dev *accel_dev = acc_devmgr_pci_to_accel_dev(pdev); + + if (!accel_dev) { + pr_err("ZSDA: Driver removal failed pf\n"); + return; + } + zsda_release_qps(accel_dev); + if(test_bit(ZSDA_STATUS_IRQ_ALLOCATED, &accel_dev->status)){ + zsda_free_irqs(accel_dev); + clear_bit(ZSDA_STATUS_IRQ_ALLOCATED, &accel_dev->status); + } + zsda_sriov_configure(pdev, 0); + zsda_pf_cleanup_pci_dev(accel_dev); + zsda_pf_cleanup_accel(accel_dev); + kfree(accel_dev); + zsda_lkcf_unregister(); + +} + +static int __init zsda_pfdrv_init(void) +{ + request_module("zsda_common"); + + if (pci_register_driver(&zsda_pf_driver)) { + pr_err("ZSDA: Driver initialization failed\n"); + return -EFAULT; + } + + return 0; +} + +static void __exit zsda_pfdrv_release(void) +{ + pci_unregister_driver(&zsda_pf_driver); +} + +module_init(zsda_pfdrv_init); +module_exit(zsda_pfdrv_release); + +MODULE_AUTHOR("ZTE"); +MODULE_LICENSE("Dual BSD/GPL"); +MODULE_DESCRIPTION("ZTE ACC ZSDA PF"); +MODULE_VERSION(ZSDA_DRV_VERSION); diff --git a/src/crypto/zsda/accdevice/zsda_vf/Makefile b/src/crypto/zsda/accdevice/zsda_vf/Makefile new file mode 100644 index 0000000..2981e38 --- /dev/null +++ b/src/crypto/zsda/accdevice/zsda_vf/Makefile @@ -0,0 +1,5 @@ + +ccflags-y := -I$(src)/../../include +ccflags-y += -I$(src)/../zsda_common +obj-$(CONFIG_ACC_ZSDA_VF) += zsda_vf.o +zsda_vf-objs = zsda_drv.o diff --git a/src/crypto/zsda/accdevice/zsda_vf/zsda_drv.c b/src/crypto/zsda/accdevice/zsda_vf/zsda_drv.c new file mode 100644 index 0000000..0502062 --- /dev/null +++ b/src/crypto/zsda/accdevice/zsda_vf/zsda_drv.c @@ -0,0 +1,217 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright(c) 2024 ZTE Corporation */ +#include +#include +#include +#include +#include +#include "acc_version.h" +// #include "acc_compat.h" +#include "acc_dev.h" +#include "zsda_manage.h" +#include "zsda_common_drv.h" + +#define PCI_VENDOR_ID_ZTE 0x1cf2 +#define ZSDA_VF_PCI_DEVICE_ID 0x8051 + +#define ZSDA_SYSTEM_DEVICE(device_id) \ + {PCI_DEVICE(PCI_VENDOR_ID_ZTE, device_id)} + +static const struct pci_device_id zsda_vf_pci_tbl[] = { + ZSDA_SYSTEM_DEVICE(ZSDA_VF_PCI_DEVICE_ID), + { + 0, + } +}; +MODULE_DEVICE_TABLE(pci, zsda_vf_pci_tbl); + +static int zsda_vf_probe(struct pci_dev *dev, const struct pci_device_id *ent); +static void zsda_vf_remove(struct pci_dev *dev); + +static const struct file_operations test_debugfs_ops = { + .open = zsda_seq_open, + .read = seq_read, + .write = zsda_seq_write, + .llseek = seq_lseek, + .release = single_release, +}; + +static struct pci_driver zsda_vf_driver = { + .id_table = zsda_vf_pci_tbl, + .name = "ZSDA-VF", + .probe = zsda_vf_probe, + .remove = zsda_vf_remove, +}; + +static void zsda_vf_cleanup_pci_dev(struct accel_dev *accel_dev) +{ + pci_release_regions(accel_dev->accel_pci_dev.pci_dev); + pci_disable_device(accel_dev->accel_pci_dev.pci_dev); +} + +static void zsda_vf_cleanup_accel(struct accel_dev *accel_dev) +{ + zsda_unmap_pci_bars(accel_dev); + + kfree(accel_dev->hw_data); + accel_dev->hw_data = NULL; + kfree(accel_dev->cfg); + accel_dev->cfg = NULL; + + debugfs_remove(accel_dev->debugfs_dir); + accel_dev->debugfs_dir = NULL; + acc_devmgr_rm_dev(accel_dev); +} + +static int zsda_vf_probe(struct pci_dev *pdev, const struct pci_device_id *ent) +{ + struct accel_dev *accel_dev; + struct accel_pci *accel_pci_dev; + struct device_hw_data *hw_data; + struct device_cfg_data *hw_cfg_data; + char name[ZSDA_DEVICE_NAME_LENGTH]; + int ret = 0; + + if (num_possible_nodes() > 1 && dev_to_node(&pdev->dev) < 0) { + dev_err(&pdev->dev, "Invalid NUMA configuration.\n"); + return -EINVAL; + } + + accel_dev = kzalloc_node(sizeof(struct accel_dev), GFP_KERNEL, + dev_to_node(&pdev->dev)); + if (!accel_dev) + return -ENOMEM; + + accel_pci_dev = &(accel_dev->accel_pci_dev); + accel_pci_dev->pci_dev = pdev; + + acc_devmgr_add_dev(accel_dev); + + accel_dev->owner = THIS_MODULE; + accel_dev->is_vf = true; + hw_data = kzalloc_node(sizeof(struct device_hw_data), GFP_KERNEL, + dev_to_node(&pdev->dev)); + if (!hw_data) { + ret = -ENOMEM; + goto out_err; + } + accel_dev->hw_data = hw_data; + + hw_cfg_data = kzalloc_node(sizeof(struct device_cfg_data), GFP_KERNEL, + dev_to_node(&pdev->dev)); + if (!hw_cfg_data) { + ret = -ENOMEM; + goto out_err; + } + accel_dev->cfg = hw_cfg_data; + + snprintf(name, sizeof(name), "zsda_%02x:%02x.%d", pdev->bus->number, + PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); + memcpy(accel_dev->name, name, sizeof(name)); + dev_info(&GET_DEV(accel_dev), "probe %s\n", name); + + accel_dev->debugfs_dir = debugfs_create_dir(name, NULL); + if (!accel_dev->debugfs_dir) { + dev_err(&pdev->dev, "Could not create debugfs dir %s\n", name); + ret = -EINVAL; + goto out_err; + } + if (!debugfs_create_file("ctrl", 0444, accel_dev->debugfs_dir, + accel_dev, &test_debugfs_ops)) { + ret = -EINVAL; + goto out_err; + } + + if (pci_enable_device(pdev)) { + ret = -EFAULT; + goto out_err; + } + + if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { + if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))) { + dev_err(&pdev->dev, "No usable DMA configuration\n"); + ret = -EFAULT; + goto out_err_disable; + } else { + pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); + } + } else { + pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); + } + + if (pci_request_regions(pdev, ZSDA_VF_DEVICE_NAME)) { + ret = -EFAULT; + goto out_err_disable; + } + + ret = zsda_map_pci_bars(accel_dev); + if (unlikely(ret)) + goto out_err_free_reg; + + pci_set_master(pdev); + if(zsda_dev_int(accel_dev)) + return ret; + + ret = zsda_request_irqs(accel_dev); + if (unlikely(ret)) + goto out_err_dev_release; + + set_bit(ZSDA_STATUS_STARTED, &accel_dev->status); + accel_dev->lkcf_en = true; + zsda_lkcf_register(); + return ret; + +out_err_dev_release: + zsda_release_qps(accel_dev); +out_err_free_reg: + pci_release_regions(accel_pci_dev->pci_dev); +out_err_disable: + pci_disable_device(accel_pci_dev->pci_dev); +out_err: + zsda_vf_cleanup_accel(accel_dev); + kfree(accel_dev); + return ret; +} + +static void zsda_vf_remove(struct pci_dev *pdev) +{ + struct accel_dev *accel_dev = acc_devmgr_pci_to_accel_dev(pdev); + + if (!accel_dev) { + pr_err("ZSDA: Driver removal failed vf\n"); + return; + } + zsda_release_qps(accel_dev); + if(test_bit(ZSDA_STATUS_IRQ_ALLOCATED, &accel_dev->status)){ + zsda_free_irqs(accel_dev); + clear_bit(ZSDA_STATUS_IRQ_ALLOCATED, &accel_dev->status); + } + zsda_vf_cleanup_accel(accel_dev); + zsda_vf_cleanup_pci_dev(accel_dev); + kfree(accel_dev); + zsda_lkcf_unregister(); +} + +static int __init zsda_vfdrv_init(void) +{ + request_module("zsda_common"); + + if (pci_register_driver(&zsda_vf_driver)) { + pr_err("ZSDA: Driver initialization failed\n"); + return -EFAULT; + } + return 0; +} + +static void __exit zsda_vfdrv_release(void) +{ + pci_unregister_driver(&zsda_vf_driver); +} + +module_init(zsda_vfdrv_init); +module_exit(zsda_vfdrv_release); + +MODULE_AUTHOR("ZTE"); +MODULE_LICENSE("Dual BSD/GPL"); +MODULE_DESCRIPTION("ZTE ACC ZSDA VF"); +MODULE_VERSION(ZSDA_DRV_VERSION); diff --git a/src/crypto/zsda/include/acc_addr.h b/src/crypto/zsda/include/acc_addr.h new file mode 100644 index 0000000..c1f97d2 --- /dev/null +++ b/src/crypto/zsda/include/acc_addr.h @@ -0,0 +1,80 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright(c) 2024 ZTE Corporation */ + +#define VALID 0x1 +#define INVALID 0x0 + +#define Q_STOP 0x0 +#define Q_START 0x1 + +#define MASK 0x1 +#define NOMASK 0x0 + +#define ZSDA_BAR0 0x0 +#define ADMIN_RETRY_TIMES 500 + +#define ZSDA_ADMIN_WQ(i) (0x40 + ((i) * 0x04)) +#define ZSDA_ADMIN_WQ_BASE7 0x5C +#define ZSDA_ADMIN_CQ(i) (0x60 + ((i) * 0x04)) +#define ZSDA_ADMIN_CQ_BASE7 0x7C +#define ZSDA_ADMIN_WQ_TAIL 0x80 +#define ZSDA_ADMIN_CQ_HEAD 0x84 +#define ZSDA_ADMIN_Q_START 0x100 +#define ADMIN_BUF_DATA_LEN 0x1C +#define ADMIN_BUF_TOTAL_LEN 0x20 + +#define ZSDA_IO_QUE_INT_MASK_0 0x180 +#define ZSDA_IO_QUE_INT_MASK_1 0x184 +#define ZSDA_IO_QUE_INT_MASK_2 0x188 +#define ZSDA_IO_QUE_INT_MASK_3 0x18c +#define ZSDA_IO_QUE_INT_MASK_4 0x190 +#define ZSDA_IO_QUE_INT_MASK_5 0x194 +#define ZSDA_IO_QUE_INT_MASK_6 0x198 +#define ZSDA_IO_QUE_INT_MASK_7 0x19c +#define ZSDA_IO_QUE_INT_MASK_8 0x1a0 +#define ZSDA_IO_Q_START(i) (0x200 + ((i) * 0x04)) +#define ZSDA_IO_Q_STOP(i) (0x200 + ((i) * 0x04)) +#define ZSDA_IO_Q_STOP_RESP(i) (0x400 + ((i) * 0x04)) +#define ZSDA_IO_Q_CLR(i) (0x600 + ((i) * 0x04)) +#define ZSDA_IO_Q_CLR_RESP(i) (0x800 + ((i) * 0x04)) + +#define ZSDA_WQ_TAIL 0x1800 +#define ZSDA_CQ_HEAD 0x1804 +#define ZSDA_QUE_DB_INIT(i) (0x1c00 + ((i) * 0x04)) +#define ZSDA_WQ_LBASE 0x1000 +#define ZSDA_WQ_UBASE 0x1004 +#define ZSDA_CQ_LBASE 0x1400 +#define ZSDA_CQ_UBASE 0x1404 + +#define ZSDA_REG_WR(base, offset, val) \ +({ \ + __raw_writel(val, (((u8 *)(base)) + (offset))); \ +}) + +#define ZSDA_REG_RD(base, offset) \ +({ \ + __raw_readl((u8 *)(base) + (offset)); \ +}) + +#define ZSDA_WQ_RING_BASE(csr_base_addr, ring, value) \ +do { \ + uint32_t l_base = 0, u_base = 0; \ + l_base = (uint32_t)(value & 0xFFFFFFFF); \ + u_base = (uint32_t)((value & 0xFFFFFFFF00000000ULL) >> 32); \ + ZSDA_REG_WR(csr_base_addr, (ring<<3) + ZSDA_WQ_LBASE, l_base); \ + ZSDA_REG_WR(csr_base_addr, (ring<<3) + ZSDA_WQ_UBASE, u_base); \ +} while (0) + +#define ZSDA_CQ_RING_BASE(csr_base_addr, ring, value) \ +do { \ + uint32_t l_base = 0, u_base = 0; \ + l_base = (uint32_t)(value & 0xFFFFFFFF); \ + u_base = (uint32_t)((value & 0xFFFFFFFF00000000ULL) >> 32); \ + ZSDA_REG_WR(csr_base_addr, (ring<<3) + ZSDA_CQ_LBASE, l_base); \ + ZSDA_REG_WR(csr_base_addr, (ring<<3) + ZSDA_CQ_UBASE, u_base); \ +} while (0) + +#define WRITE_WQ_TAIL(csr_base_addr, ring, value) \ + ZSDA_REG_WR(csr_base_addr, ZSDA_WQ_TAIL + (ring << 3), value) +#define WRITE_CQ_HEAD(csr_base_addr, ring, value) \ + ZSDA_REG_WR(csr_base_addr, ZSDA_CQ_HEAD + (ring << 3), value) diff --git a/src/crypto/zsda/include/acc_dev.h b/src/crypto/zsda/include/acc_dev.h new file mode 100644 index 0000000..89f46c0 --- /dev/null +++ b/src/crypto/zsda/include/acc_dev.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright(c) 2024 ZTE Corporation */ +#ifndef ACC_DEV_H +#define ACC_DEV_H + +#include + +#define ZSDA_PCI_MAX_BARS 3 +#define ZSDA_DEVICE_NAME_LENGTH 32 +#define ZSDA_INTR_NAME_LENGTH 32 +#define ACC_DEVICE_NAME_PREFIX "acc_" +#define ZSDA_PF_DEVICE_NAME "zsda_pf" +#define ZSDA_VF_DEVICE_NAME "zsda_vf" + +struct acc_bar { + resource_size_t base_addr; + void __iomem *virt_addr; + resource_size_t size; +} __packed; + +struct accel_msix { + struct msix_entry *entries; + u32 num_entries; +} __packed; + +struct accel_pci { + struct pci_dev *pci_dev; + struct accel_msix msix_entries; + struct acc_bar pci_bars[ZSDA_PCI_MAX_BARS]; + +} __packed; + +struct zsda_dbg { + uint64_t encry_enq; + uint64_t encry_deq; + uint64_t decry_enq; + uint64_t decry_deq; +}; + +struct accel_dev { + struct list_head list; + struct device_hw_data *hw_data; + struct device_cfg_data *cfg; + struct accel_pci accel_pci_dev; + struct module *owner; + bool is_vf; + bool lkcf_en; + u32 accel_id; + unsigned long status; + atomic_t lkcf_ref; + struct dentry *debugfs_dir; + struct tasklet_struct encry_task; + struct tasklet_struct decry_task; + char name[ZSDA_DEVICE_NAME_LENGTH]; + struct zsda_dbg zsda_dbg; +}; + +#define GET_DEV(accel_dev) ((accel_dev)->accel_pci_dev.pci_dev->dev) + +#endif diff --git a/src/crypto/zsda/include/acc_version.h b/src/crypto/zsda/include/acc_version.h new file mode 100644 index 0000000..78e07a1 --- /dev/null +++ b/src/crypto/zsda/include/acc_version.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright(c) 2024 ZTE Corporation */ +#ifndef ACC_VERSION_H +#define ACC_VERSION_H + +#include +#include + +#define ZSDA_MAJOR_VERSION 4 +#define ZSDA_MINOR_VERSION 8 +#define ZSDA_BUILD_VERSION 0 +#define ZSDA_DRV_VERSION \ + __stringify(ZSDA_MAJOR_VERSION) "." __stringify( \ + ZSDA_MINOR_VERSION) "." __stringify(ZSDA_BUILD_VERSION) + +#if (KERNEL_VERSION(3, 2, 0) > LINUX_VERSION_CODE) +#define iommu_present(b) iommu_found() +#endif /* 3.2.0 */ + +#if (KERNEL_VERSION(5, 18, 0) <= LINUX_VERSION_CODE) +#define pci_set_dma_mask(pdev, mask) dma_set_mask(&(pdev)->dev, mask) +#define pci_set_consistent_dma_mask(pdev, mask) \ + dma_set_coherent_mask(&(pdev)->dev, mask) +#endif + +#endif diff --git a/src/net/Kconfig b/src/net/Kconfig new file mode 100755 index 0000000..0f115fe --- /dev/null +++ b/src/net/Kconfig @@ -0,0 +1 @@ +source "drivers/net/ethernet/dinghai" \ No newline at end of file diff --git a/src/net/Makefile b/src/net/Makefile new file mode 100755 index 0000000..c7829d2 --- /dev/null +++ b/src/net/Makefile @@ -0,0 +1,7 @@ +EXTRA_CFLAGS += -I$(CWD)/include +EXTRA_CFLAGS += -I$(CWD)/drivers/net/ethernet/dinghai/zf_mpf/epc + +subdir-ccflags-y += -include $(CWD)/autoconf.h +obj-$(CONFIG_DINGHAI_ETH) += drivers/net/ethernet/dinghai/ +obj-$(CONFIG_ZXDH_AUXILIARY) += drivers/base/ +obj-m += drivers/pcie/zxdh_pcie/ \ No newline at end of file diff --git a/src/net/README.MD b/src/net/README.MD new file mode 100644 index 0000000..7c31da7 --- /dev/null +++ b/src/net/README.MD @@ -0,0 +1,156 @@ +# 源码编译驱动 +## build +cd ./build +./build.pl -t kernel -m CONFIG_DINGHAI_ETH -m CONFIG_ZXDH_AUXILIARY -m CONFIG_DINGHAI_PF -m CONFIG_ZXDH_SF -m CONFIG_DINGHAI_EN_AUX -m HAVE_DEVLINK_ALLOC_GET_1_PARAMS -m HAVE_DEV_PM_DOMAIN_ATTACH -m HAVE_BUS_FIND_DEVICE_GET_CONST -m CONFIG_DINGHAI_DH_CMD -m CONFIG_DINGHAI_NP -m CONFIG_ZXDH_MSGQ -m CONFIG_ZXDH_1588 -m CONFIG_DINGHAI_PTP -m CONFIG_DINGHAI_TSN + +## build clean +cd ./build +./build.pl -t clean + +## 说明 +1. If you want to add/delete a compilation option or macro definition, add/delete the corresponding " -m ***" parameter. +2. You can also use the "build.sh" compilation script under the root directory of the source code: ./build.sh + +3. If you are using ZF server or your architecture is aarch64, and you want to compile the mpf.ko driver to run on ZF. +./build.pl -t kernel -m CONFIG_DINGHAI_ETH -m CONFIG_ZXDH_AUXILIARY -m CONFIG_DINGHAI_PF -m CONFIG_ZXDH_SF -m CONFIG_DINGHAI_EN_AUX -m HAVE_DEVLINK_ALLOC_GET_1_PARAMS -m HAVE_DEV_PM_DOMAIN_ATTACH -m HAVE_BUS_FIND_DEVICE_GET_CONST -m CONFIG_DINGHAI_DH_CMD -m CONFIG_DINGHAI_NP -m CONFIG_DINGHAI_ZF_MPF -m PCIE_ZF_EPC_OPEN + +4. **Note: CONFIG_DINGHAI_ZF_MPF is used for the ZF platform(aarch64), CONFIG_DINGHAI_MPF is used for the x86_64 platform, and the two cannot be used at the same time.** + +5. If you want to test 1588, you need to add the compile option CONFIG_ZXDH_1588 and open macro TIME_STAMP_1588, otherwise do not add the compile option CONFIG_ZXDH_1588. +example, +./build.pl -t kernel -m CONFIG_DINGHAI_ETH -m CONFIG_ZXDH_AUXILIARY -m CONFIG_DINGHAI_PF -m CONFIG_ZXDH_SF -m CONFIG_DINGHAI_EN_AUX -m HAVE_DEVLINK_ALLOC_GET_1_PARAMS -m HAVE_DEV_PM_DOMAIN_ATTACH -m HAVE_BUS_FIND_DEVICE_GET_CONST -m CONFIG_DINGHAI_DH_CMD -m CONFIG_DINGHAI_NP -m CONFIG_ZXDH_MSGQ -m CONFIG_ZXDH_1588 -m CONFIG_DINGHAI_PTP -m CONFIG_DINGHAI_TSN + +6. ## Modify the queue pairs +If you want to modify the queue pairs, you should add the "max_pairs=*" parameter after "insmod zxdh_en_aux.ko". If you do not add the "max_pairs=*" parameter after "insmod zxdh_en_aux.ko", the default queue pairs in the driver are used for initialization. For example: +insmod zxdh_en_aux.ko max_pairs=16 + +7. If you want to test Hot-Plug PF(hpf), you need to add the compile option CONFIG_DINGHAI_HPF. For example: +./build.pl -t kernel -m CONFIG_DINGHAI_ETH -m HAVE_DEVLINK_ALLOC_GET_1_PARAMS -m CONFIG_DINGHAI_DH_CMD -m CONFIG_DINGHAI_HPF + +8. rpm包相关 +## Compile and Install driver module +``` +cd ./build +./build.pl -t {all|install} -m CONFIG_DINGHAI_ETH -m CONFIG_ZXDH_AUXILIARY -m CONFIG_DINGHAI_PF -m CONFIG_ZXDH_SF -m CONFIG_DINGHAI_EN_AUX -m HAVE_DEVLINK_ALLOC_GET_1_PARAMS -m HAVE_DEV_PM_DOMAIN_ATTACH -m HAVE_BUS_FIND_DEVICE_GET_CONST -m CONFIG_DINGHAI_DH_CMD -m CONFIG_DINGHAI_NP +``` +- These drivers will be compiled and they will not only appear in the local directory, but also be copied to **/lib/modules/\/updates/drivers/net/ethernet/zte/zxdh/** +- The install location listed above is the default location. This may differ for various Linux distributions. +- now you can not only use `insmod` to load these drivers, but you can also use `modprobe` in any directory. `modprobe` will automatically analyze the dependencies between these drivers. eg: +``` bash +# register driver to kernel +modprobe zxdh_pf +# unregister driver from kernel +modprobe -r zxdh_pf +``` +- Use modinfo to view some information about the driver, such as version number, etc. eg: +``` bash +modinfo zxdh_en_aux +``` +- **Note:** When your compilation target is `./build.pl -t all` or `./build.pl -t install`, these drivers will be automatically loaded when the host is reset or restarted. Therefore, you must ensure that your drivers do not have bugs that cause the kernel to hang. Otherwise, they will be loaded every time the kernel is reset. Automatically load your problematic driver so that the host cannot be reset normally. + +## Uninstall driver module +``` bash +cd ./build +./build.pl -t uninstall +``` +- When your compilation target is `./build.pl -t uninstall`. After this, the host will not automatically load your driver after reset. + +## cross compile +If you want to use source code to cross-compile, for example, the host is the x86_64 platform and the target is the aarch64 platform, you need to add 3 additional parameters. +``` shell +./build.pl -t kernel -m CONFIG_DINGHAI_ETH -m CONFIG_ZXDH_AUXILIARY -m CONFIG_DINGHAI_PF -m CONFIG_DINGHAI_ZF_MPF -m CONFIG_ZXDH_SF -m CONFIG_DINGHAI_EN_AUX -m HAVE_DEVLINK_ALLOC_GET_1_PARAMS -m HAVE_DEV_PM_DOMAIN_ATTACH -m HAVE_BUS_FIND_DEVICE_GET_CONST -m CONFIG_DINGHAI_DH_CMD -m CONFIG_DINGHAI_NP --ksrc /path/kernel/source --cross_compile /path/cross/compile/tools/aarch64-pc-linux-gnu- --target_arch aarch64 +``` +- --ksrc kernel source path +- --cross_compile cross compile tools path +- --target_arch target arch + +If you want to delete the compiled product, use the following script +``` shell +./build.pl -t clean --ksrc /path/kernel/source --cross_compile /path/cross/compile/tools/aarch64-pc-linux-gnu- --target_arch aarch64 +``` +*** +# 生成驱动`RPM`包 +目前生成rpm包的脚本文件有3个, 分别是 +- `zxdh_eth_rpm_build.sh` +- `zxdh_mpf_rpm_build.sh` +- `zxdh_zf_mpf_rpm_build.sh` + +输入下面命令查看脚本文件参数用法 +``` shell +zxdh_eth_rpm_build.sh -h +zxdh_mpf_rpm_build.sh -h +zxdh_zf_mpf_rpm_build.sh -h +``` +## `zxdh_eth_rpm_build.sh`脚本 +该脚本支持交叉编译, 和使用不同内核源码编译, 具体参数见`zxdh_eth_rpm_build.sh -h` +该脚本用于生成2个rpm包 +- zxdh-eth-*****.rpm +- zxdh-smartnic-config-*******.rpm + +其中`zxdh-eth-****.rpm`包里包含的驱动ko,具体如下: +- `zxdh_cmd.ko` +- `zxdh_np.ko` +- `zxdh_pf.ko` +- `zxdh_en_aux.ko` +- `zxdh_auxiliary.ko`(内核是否支持`auxiliary`总线,都会生成该驱动) + +其中`zxdh-smartnic-config-*******.rpm`包里包含配置文件 +- `dpu_init.cfg`或者`smart-nic_init.cfg` + +## `zxdh_mpf_rpm_build.sh`脚本 +该脚本支持交叉编译, 和使用不同内核源码编译, 具体参数见`zxdh_mpf_rpm_build.sh -h` +该脚本用于生成1个rpm包 +- zxdh-mpf-*****.rpm + +其中`zxdh-mpf-*****.rpm`包里包含的驱动ko,具体如下: +- `zxdh_cmd.ko` +- `zxdh_np.ko` +- `zxdh_mpf.ko` +- `zxdh_auxiliary.ko`(内核是否支持`auxiliary`总线,都会生成该驱动) + +## `zxdh_zf_mpf_rpm_build.sh`脚本 +该脚本支持交叉编译, 但是目标架构必须是`aarch64`, 和使用不同内核源码编译, 具体参数见`zxdh_zf_mpf_rpm_build.sh -h` +该脚本用于生成1个rpm包 +- zxdh-zf-mpf-*****.rpm + +其中`zxdh-zf-mpf-*****.rpm`包里包含的驱动ko,具体如下: +- `zxdh_cmd.ko` +- `zxdh_zf_mpf.ko` + + +## rpm包命名格式 +<软件名称> - <软件版本信息> - <发布次数> - - <硬件架构平台>.rpm +- 这些变量在3个脚本中都有默认值，根据需要可进行修改 +- `zxdh-smartnic-config-1.0-1.rpm`是配置文件包，没有带 和<硬件架构平台> + + +## 交叉编译 +交叉编译生成rpm包，需要提供额外的编译参数，需要提供的额外参数如下： +- --ksrc 目标架构的内核源码路径 +- --cross-compile 交叉编译工具链路径 +- --target-arch 目标架构类型(脚本`zxdh_zf_mpf_rpm_build.sh`没有该参数) + +# rpm安装zxdh_kernel包使用方法 + +## 安装rpm包 +``` shell +rpm -ivh zxdh-eth.XXXXXXX.rpm +``` +## 卸载rpm包 +``` shell +rpm -evh zxdh-eth.XXXXXXX.rpm +``` + +## 安装驱动 +``` shell +modprobe zxdh_en_aux +``` + +## 卸载驱动 +``` shell +modprobe -r zxdh_en_aux +``` + +## 开机自动加载zxdh_en_aux驱动 +- 在`/etc/rc.d/rc.local`文件下新增一行 `modprobe zxdh_en_aux` +- 如果该文件没有可执行权限，使用`chmod a+x /etc/rc.d/rc.local` diff --git a/src/net/build.sh b/src/net/build.sh new file mode 100755 index 0000000..3ff31dc --- /dev/null +++ b/src/net/build.sh @@ -0,0 +1,63 @@ +#!/bin/bash + +path=$(pwd) + +# 定义函数 +unload_drivers() { + echo "卸载驱动" + rmmod zxdh_en_aux + rmmod zxdh_pf + rmmod zxdh_tsn + rmmod zxdh_ptp + rmmod zxdh_np + rmmod zxdh_cmd + rmmod zxdh_auxiliary +} + +compile_zxdh_kernel() { + echo "编译zxdh_kernel" + cd $path/build + ./build.pl -t clean + ./build.pl -t kernel -m CONFIG_DINGHAI_ETH -m CONFIG_ZXDH_AUXILIARY -m CONFIG_DINGHAI_PF -m CONFIG_ZXDH_SF \ + -m CONFIG_DINGHAI_EN_AUX -m HAVE_DEVLINK_ALLOC_GET_1_PARAMS -m HAVE_DEV_PM_DOMAIN_ATTACH \ + -m HAVE_BUS_FIND_DEVICE_GET_CONST -m CONFIG_DINGHAI_DH_CMD -m CONFIG_DINGHAI_NP \ + -m CONFIG_ZXDH_MSGQ -m CONFIG_ZXDH_1588 -m CONFIG_DINGHAI_PTP -m CONFIG_DINGHAI_TSN +} + +load_zxdh_kernel() { + echo "加载zxdh_kernel" + cd $path/drivers + insmod base/zxdh_auxiliary.ko + insmod net/ethernet/dinghai/zxdh_cmd.ko + insmod net/ethernet/dinghai/zxdh_np.ko + insmod net/ethernet/dinghai/zxdh_ptp.ko + insmod net/ethernet/dinghai/zxdh_tsn.ko + insmod net/ethernet/dinghai/zxdh_pf.ko + insmod net/ethernet/dinghai/zxdh_en_aux.ko +} + +# 主逻辑 +command="$1" +case "$command" in + r) unload_drivers ;; + m) compile_zxdh_kernel ;; + i) load_zxdh_kernel ;; + a) + unload_drivers + compile_zxdh_kernel + load_zxdh_kernel + ;; + *) + echo "用法：" + echo "m 编译" + echo "i 加载ko" + echo "r 移除ko" + echo "a = r + m + i" + ;; +esac + +# 检查最后一个命令的退出状态 +if [ $? -ne 0 ]; then + echo "错误：上一个命令失败！" + exit 1 +fi diff --git a/src/net/build/Makefile b/src/net/build/Makefile new file mode 100755 index 0000000..b32d748 --- /dev/null +++ b/src/net/build/Makefile @@ -0,0 +1,133 @@ +CONFIG_MK ?= $(wildcard config.mk) +ifeq (${CONFIG_MK},) + $(error Cannot find config.mk build rules) +else + include ${CONFIG_MK} +endif + +# Check that kernel version is at least 2.6.0, since we don't support 2.4.x +# kernels with the driver. We can't use minimum_kver_check since SLES 10 +# SP4's Make has a bug which causes $(eval) inside an ifeq conditional to error +# out. This was fixed in Make 3.81, but SLES 10 SP4 does not have a fix for +# this yet. +ifeq (0,$(shell [ ${KVER_CODE} -lt $(call get_kvercode,2,6,0) ]; echo "$?")) + $(warning *** Aborting the build.) + $(error This driver is not supported on kernel versions older than 2.6.0) +endif + +# Command to update initramfs or display a warning message +ifeq (${cmd_initrd},) +define cmd_initramfs +@echo "Unable to update initramfs. You may need to do this manually." +endef +else +define cmd_initramfs +@echo "Updating initramfs..." +-@$(call cmd_initrd) +endef +endif + +# Command to update udev rules or display a warning message +ifeq (${cmd_udevadm},) +define cmd_udevrules +@echo "Unable to reload udev rules in-memory representation. You may need to do this manually." +endef +else +define cmd_udevrules +@echo "Reloading udev rules in-memory representation..." +-@$(call cmd_udevadm) +endef +endif + + +DRIVER := zxdh +autoconf_h := $(CWD)/autoconf.h +ZXDH_EN_AUX_UDEV_RULE := 80-zxdh_en_aux-drivers + +LINUXINCLUDE=\ + -D__KERNEL__ \ + CFLAGS += -include $(autoconf_h) + +zxdh_en_aux_udev_rule_file: + @echo 'ACTION!="add", GOTO="drivers_end"' > ${ZXDH_EN_AUX_UDEV_RULE}.rules + @echo 'ENV{MODALIAS}=="zxdh_auxiliary:zxdh_pf.en_aux", RUN{builtin}+="kmod load zxdh_en_aux"' >> ${ZXDH_EN_AUX_UDEV_RULE}.rules + @echo 'LABEL="drivers_end"' >> ${ZXDH_EN_AUX_UDEV_RULE}.rules + + +zxdh_en_aux_udev_rule_install: zxdh_en_aux_udev_rule_file + @echo "Add zxdh_en_aux driver udev rule..." + @install -D -m 644 ${ZXDH_EN_AUX_UDEV_RULE}.rules ${INSTALL_MOD_PATH}${UDEV_RULES_DIR}/${ZXDH_EN_AUX_UDEV_RULE}.rules + $(call cmd_udevrules) + + + +zxdh_en_aux_udev_rule_uninstall: + @if [ -e ${ZXDH_EN_AUX_UDEV_RULE}.rules ] ; then \ + rm -f ${ZXDH_EN_AUX_UDEV_RULE}.rules ; \ + fi; + @if [ -e ${INSTALL_MOD_PATH}${UDEV_RULES_DIR}/${ZXDH_EN_AUX_UDEV_RULE}.rules ] ; then \ + rm -f ${INSTALL_MOD_PATH}${UDEV_RULES_DIR}/${ZXDH_EN_AUX_UDEV_RULE}.rules ; \ + fi; + $(call cmd_udevrules) + +################### +# Build kernel # +################## +kernel: + @echo "Building kernel modules..." + +$(call kernelbuild,modules) + +################### +# Install kernel # +################### +modules_install: + @echo "Installing kernel modules..." + +$(call kernelbuild, modules_install) + +############################## +# Build and install kernel # +############################## +all: kernel modules_install zxdh_en_aux_udev_rule_install + @echo "Running depmod..." + $(call cmd_depmod) + $(call cmd_initramfs) + +install: all + +############################# +# Delete module(s) binaries # +############################# +clean: + +$(call kernelbuild, clean) + -$(RM) -rf $(CWD)/autoconf.h + +############################## +# Uninstall kernel module(s) # +############################## +modules_uninstall: + rm -rf ${INSTALL_MOD_PATH}/lib/modules/${KVER}/${INSTALL_MOD_DIR} + +uninstall: clean modules_uninstall zxdh_en_aux_udev_rule_uninstall + $(call cmd_depmod) + $(call cmd_initramfs) + + +help: + @echo 'Building external (out-of-tree) modules:' + @echo ' all - default target, build and install the module(s) and update initramfs' + @echo ' kernel - build the module(s)' + @echo ' modules_install - install kernel module(s) under $(INSTALL_MOD_PATH)/lib/modules/$(KVER)/$(INSTALL_MOD_DIR)' + @echo ' install - build and install the module(s) and update initramfs' + @echo ' install modules(s) under $(INSTALL_MOD_PATH)/lib/modules/$(KVER)/$(INSTALL_MOD_DIR)' + @echo ' clean - remove generated files' + @echo ' modules_uninstall - uninstall kernel module(s) under $(INSTALL_MOD_PATH)/lib/modules/$(KVER)/$(INSTALL_MOD_DIR)' + @echo ' uninstall - remove generated files and uninstall the module(s) and update initramfs' + @echo 'Command-line option:' + @echo ' KSRC= - Path to kernel source (defaults to running kernel)' + @echo ' INSTALL_MOD_PATH= - Prefix added to default module(s) installation path' + @echo ' ($(INSTALL_MOD_PATH)/lib/modules/$(KVER)/)' + @echo ' INSTALL_MOD_DIR= - Install module(s) in subdirectory other than default' + @echo ' (.../updates/drivers/net/ethernet/ZTE/${DRIVER})' + @echo '' + +.PHONY: all kernel modules_install install clean modules_uninstall uninstall diff --git a/src/net/build/build.pl b/src/net/build/build.pl new file mode 100755 index 0000000..42bd197 --- /dev/null +++ b/src/net/build/build.pl @@ -0,0 +1,71 @@ +#!/usr/bin/perl + +use strict; +use File::Basename; +use File::Path; +use File::Find; +use File::Copy; +use File::Glob qw/:bsd_glob/; +use File::Temp; +use Cwd; +use Term::ANSIColor qw(:constants); +use Data::Dumper; +use Scalar::Util 'reftype'; + +my $CWD = getcwd; + +my $compile_arg = ""; +my $num_cores = scalar(`cat /proc/cpuinfo | grep -c '^processor'`); +$num_cores -= 1 unless $num_cores == 1; +my $autoconf_h = $CWD.'/../autoconf.h'; +my $target_name; +my $auto_config= ""; +my $ksrc = ""; +my $cross_compile = ""; +my $target_arch = ""; +my $driver_version = ""; +print $autoconf_h."\n"; + +while ( $#ARGV >= 0 ) { + my $cmd_flag = shift(@ARGV); + if ( $cmd_flag eq "-t") { + $target_name = shift(@ARGV); + $compile_arg = $compile_arg." ".$target_name; + } elsif ( $cmd_flag eq "-m" ) { + my $mod = shift(@ARGV); + $auto_config = $auto_config."\n"."#define ".$mod." 1"; + $compile_arg = $compile_arg." ".$mod."=m"; + } elsif ( $cmd_flag eq "-y" ) { + my $mod = shift(@ARGV); + $auto_config = $auto_config."\n"."#define ".$mod." 2"; + $compile_arg = $compile_arg." ".$mod."=y"; + } elsif ( $cmd_flag eq "--dri_ver" ) { + my $mod = shift(@ARGV); + $compile_arg = $compile_arg." CONFIG_DRIVER_VERSION=".$mod; + } elsif ( $cmd_flag eq "--ksrc" ) { + $ksrc = shift(@ARGV); + $compile_arg = $compile_arg." "."KSRC=".$ksrc; + } elsif ( $cmd_flag eq "--cross_compile" ) { + $cross_compile = shift(@ARGV); + $compile_arg = $compile_arg." "."CROSS_COMPILE=".$cross_compile; + } elsif ( $cmd_flag eq "--target_arch" ) { + $target_arch = shift(@ARGV); + $compile_arg = $compile_arg." "."TARGET_ARCH=".$target_arch; + } elsif ( $cmd_flag eq "-j" ) { + $num_cores = shift(@ARGV); + } elsif ( $cmd_flag eq "--help" or $cmd_flag eq "-h" ) { + usage(); + exit 0; + } +} + +system("cat >$autoconf_h</dev/null ] && \ + [ "${2}" -ge 0 -a "${2}" -le 255 2>/dev/null ] && \ + [ "${3}" -ge 0 -a "${3}" -le 255 2>/dev/null ] && \ + printf %d $$(( ( ${1} << 16 ) + ( ${2} << 8 ) + ( ${3} ) )) ) + +################ +# depmod Macro # +################ + +cmd_depmod = /sbin/depmod $(if ${SYSTEM_MAP_FILE},-e -F ${SYSTEM_MAP_FILE}) \ + $(if $(strip ${INSTALL_MOD_PATH}),-b ${INSTALL_MOD_PATH}) \ + -a ${KVER} + +################ +# dracut Macro # +################ + +cmd_initrd := $(shell \ + if which dracut > /dev/null 2>&1 ; then \ + echo "dracut --force"; \ + elif which update-initramfs > /dev/null 2>&1 ; then \ + echo "update-initramfs -u"; \ + fi ) + +################# +# udevadm Macro # +################# + +cmd_udevadm := $(shell \ + if which udevadm > /dev/null 2>&1 ; then \ + echo "udevadm control --reload"; \ + fi ) + + +##################### +# Environment tests # +##################### + +DRIVER_UPPERCASE := $(shell echo ${DRIVER} | tr "[:lower:]" "[:upper:]") + +ifeq (,${BUILD_KERNEL}) +BUILD_KERNEL=$(shell uname -r) +endif + +# Kernel Search Path +# All the places we look for kernel source +KSP := /lib/modules/${BUILD_KERNEL}/source \ + /lib/modules/${BUILD_KERNEL}/build \ + /usr/src/linux-${BUILD_KERNEL} \ + /usr/src/linux-$(${BUILD_KERNEL} | sed 's/-.*//') \ + /usr/src/kernel-headers-${BUILD_KERNEL} \ + /usr/src/kernel-source-${BUILD_KERNEL} \ + /usr/src/linux-$(${BUILD_KERNEL} | sed 's/\([0-9]*\.[0-9]*\)\..*/\1/') \ + /usr/src/linux \ + /usr/src/kernels/${BUILD_KERNEL} \ + /usr/src/kernels + +# prune the list down to only values that exist and have an include/linux +# sub-directory. We can't use include/config because some older kernels don't +# have this. +test_dir = $(shell [ -e ${dir}/include/linux ] && echo ${dir}) +KSP := $(foreach dir, ${KSP}, ${test_dir}) + +# we will use this first valid entry in the search path +ifeq (,${KSRC}) + KSRC := $(firstword ${KSP}) +endif + +ifeq (,${KSRC}) + $(warning *** Kernel header files not in any of the expected locations.) + $(warning *** Install the appropriate kernel development package, e.g.) + $(error kernel-devel, for building kernel modules and try again) +else +ifeq (/lib/modules/${BUILD_KERNEL}/source, ${KSRC}) + KOBJ := /lib/modules/${BUILD_KERNEL}/build +else + KOBJ := ${KSRC} +endif +endif + +SCRIPT_PATH := ${KSRC}/scripts +info_signed_modules = + +ifeq (,${SCRIPT_PATH}) + info_signed_modules += echo "*** Could not find sign-file script. Cannot sign driver." ; +else + SIGN_FILE_EXISTS := $(or $(and $(wildcard $(SCRIPT_PATH)/sign-file),1),) + PRIV_KEY_EXISTS := $(or $(and $(wildcard zte-linux-key.key),1),) + PUB_KEY_EXISTS := $(or $(and $(wildcard zte-linux-key.crt),1),) +ifneq ($(and $(SIGN_FILE_EXISTS),$(PRIV_KEY_EXISTS),$(PUB_KEY_EXISTS)),) + info_signed_modules += \ + echo "*** Is sign-file present: ${SIGN_FILE_EXISTS}" ; \ + echo "*** Is private key present: ${PRIV_KEY_EXISTS}" ; \ + echo "*** Is public key present: ${PUB_KEY_EXISTS}" ; + info_signed_modules += echo "*** All files are present, signing driver." ; + #sign_driver = $(shell ${SCRIPT_PATH}/sign-file sha256 zte-linux-key.key \ + zte-linux-key.crt ${DRIVER}.ko) +else + info_signed_modules += echo "*** Files are missing, cannot sign driver." ; + sign_driver = +endif +endif + +# Version file Search Path +VSP := ${KOBJ}/include/generated/utsrelease.h \ + ${KOBJ}/include/linux/utsrelease.h \ + ${KOBJ}/include/linux/version.h \ + ${KOBJ}/include/generated/uapi/linux/version.h \ + /boot/vmlinuz.version.h + +# Config file Search Path +CSP := ${KOBJ}/include/generated/autoconf.h \ + ${KOBJ}/include/linux/autoconf.h \ + /boot/vmlinuz.autoconf.h + +# System.map Search Path (for depmod) +MSP := ${KSRC}/System.map \ + /usr/lib/debug/boot/System.map-${BUILD_KERNEL} \ + /boot/System.map-${BUILD_KERNEL} + +# prune the lists down to only files that exist +test_file = $(shell [ -f ${1} ] && echo ${1}) +VSP := $(foreach file, ${VSP}, $(call test_file,${file})) +CSP := $(foreach file, ${CSP}, $(call test_file,${file})) +MSP := $(foreach file, ${MSP}, $(call test_file,${file})) + + +# and use the first valid entry in the Search Paths +ifeq (,${VERSION_FILE}) + VERSION_FILE := $(firstword ${VSP}) +endif + +ifeq (,${CONFIG_FILE}) + CONFIG_FILE := $(firstword ${CSP}) +endif + +ifeq (,${SYSTEM_MAP_FILE}) + SYSTEM_MAP_FILE := $(firstword ${MSP}) +endif + +ifeq (,$(wildcard ${VERSION_FILE})) + $(error Linux kernel source not configured - missing version header file) +endif + +ifeq (,$(wildcard ${CONFIG_FILE})) + $(error Linux kernel source not configured - missing autoconf.h) +endif + +ifeq (,$(wildcard ${SYSTEM_MAP_FILE})) + $(warning Missing System.map file - depmod will not check for missing symbols during module installation) +endif + +ifneq ($(words $(subst :, ,$(CURDIR))), 1) + $(error Sources directory '$(CURDIR)' cannot contain spaces nor colons. Rename directory or move sources to another path) +endif + +################## +# Udev Rules Dir # +################## + +test_dir = $(shell [ -e ${dir} ] && echo ${dir}) + +UDEV_RULES_DIR := /etc/udev/rules.d/ /usr/lib/udev/rules.d/ +UDEV_RULES_DIR := $(foreach dir, ${UDEV_RULES_DIR}, ${test_dir}) +UDEV_RULES_DIR := $(firstword ${UDEV_RULES_DIR}) +ifeq (, ${UDEV_RULES_DIR}) + UDEV_RULES_DIR := /etc/udev/rules.d/ +endif + + +######################## +# Extract config value # +######################## + +get_config_value = $(shell ${CC} -E -dM ${CONFIG_FILE} 2> /dev/null |\ + grep -m 1 ${1} | awk '{ print $$3 }') + +######################## +# Check module signing # +######################## + +CONFIG_MODULE_SIG_ALL := $(call get_config_value,CONFIG_MODULE_SIG_ALL) +CONFIG_MODULE_SIG_FORCE := $(call get_config_value,CONFIG_MODULE_SIG_FORCE) +CONFIG_MODULE_SIG_KEY := $(call get_config_value,CONFIG_MODULE_SIG_KEY) + +# Signing key search path +SIG_KEY_SP := ${KOBJ}/${CONFIG_MODULE_SIG_KEY} \ + ${KOBJ}/certs/signing_key.pem + +# Get system signing key file path +SIG_KEY_FILE := $(firstword $(foreach file, ${SIG_KEY_SP}, $(call test_file,${file}))) + +# print a warning if the kernel configuration attempts to sign modules but +# the signing key can't be found. +ifneq (${SIG_KEY_FILE},) +warn_signed_modules := : ; +else +warn_signed_modules := +ifeq (${CONFIG_MODULE_SIG_ALL},1) +warn_signed_modules += \ + echo "*** The target kernel has CONFIG_MODULE_SIG_ALL enabled, but" ; \ + echo "*** the signing key cannot be found. Module signing has been" ; \ + echo "*** disabled for this build." ; +endif # CONFIG_MODULE_SIG_ALL=y +ifeq (${CONFIG_MODULE_SIG_FORCE},1) + warn_signed_modules += \ + echo "warning: The target kernel has CONFIG_MODULE_SIG_FORCE enabled," ; \ + echo "warning: but the signing key cannot be found. The module must" ; \ + echo "warning: be signed manually using 'scripts/sign-file'." ; +endif # CONFIG_MODULE_SIG_FORCE +DISABLE_MODULE_SIGNING := Yes +endif + + +# get the kernel version - we use this to find the correct install path +KVER := $(shell ${CC} ${EXTRA_CFLAGS} -E -dM ${VERSION_FILE} | grep UTS_RELEASE | \ + awk '{ print $$3 }' | sed 's/\"//g') + +# assume source symlink is the same as build, otherwise adjust KOBJ +ifneq (,$(wildcard /lib/modules/${KVER}/build)) + ifneq (${KSRC},$(call readlink,/lib/modules/${KVER}/build)) + KOBJ=/lib/modules/${KVER}/build + endif +endif + +# 如果当前用户指定的KSRC不是当前正在运行的内核源码目录, 指定KOBJ和用户传入的KSRC相同 +ifeq (/lib/modules/${BUILD_KERNEL}/source, ${KSRC}) + KOBJ := /lib/modules/${BUILD_KERNEL}/build +else + KOBJ := ${KSRC} +endif + +ifeq (${KVER_CODE},) + KVER_CODE := $(shell ${CC} ${EXTRA_CFLAGS} -E -dM ${VSP} 2> /dev/null |\ + grep -m 1 LINUX_VERSION_CODE | awk '{ print $$3 }' | sed 's/\"//g') +endif + +# minimum_kver_check +# +# helper function to provide uniform output for different drivers to abort the +# build based on kernel version check. Usage: "$(call minimum_kver_check,2,6,XX)". +define _minimum_kver_check +ifeq (0,$(shell [ ${KVER_CODE} -lt $(call get_kvercode,${1},${2},${3}) ]; echo "$$?")) + $$(warning *** Aborting the build.) + $$(error This driver is not supported on kernel versions older than ${1}.${2}.${3}) +endif +endef +minimum_kver_check = $(eval $(call _minimum_kver_check,${1},${2},${3})) + +############################# +# kcompat definitions setup # +############################# + +# In most cases, kcompat flags can be checked within the driver source files +# using simple CPP checks. However, it may be necessary to check for a flag +# value within the Makefile for some specific edge cases. For example, if an +# entire feature ought to be excluded on some kernels due to missing +# functionality. +# +# To support this, kcompat_defs.h is compiled and converted into a word list +# that can be checked to determine whether a given kcompat feature flag will +# be defined for this kernel. +# +# KCOMPAT_DEFINITIONS holds the set of all macros which are defined. Note +# this does include a large number of standard/builtin definitions. +# +# Use is_kcompat_defined as a $(call) function to check whether a given flag +# is defined or undefined. For example: +# +# ifeq ($(call is_kcompat_defined,HAVE_FEATURE_FLAG),1) +# +# ifneq ($(call is_kcompat_defined,HAVE_FEATURE_FLAG),1) +# +# The is_kcompat_defined function returns 1 if the macro name is defined, +# and the empty string otherwise. +# +# There is no mechanism to extract the value of the kcompat definition. +# Supporting this would be non-trivial as Make does not have a map variable +# type. +# +# Note that only the new layout is supported. Legacy definitions in +# kcompat.h are not supported. If you need to check one of these, please +# refactor it into the new layout. + +ifneq ($(wildcard ./kcompat_defs.h),) +KCOMPAT_DEFINITIONS := $(shell ${CC} ${EXTRA_CFLAGS} -E -dM \ + -I${KOBJ}/include \ + -I${KOBJ}/include/generated/uapi \ + kcompat_defs.h | awk '{ print $$2 }') + +is_kcompat_defined = $(if $(filter ${1},${KCOMPAT_DEFINITIONS}),1,) +else +KCOMPAT_DEFINITIONS := +is_kcompat_defined = +endif + +#################### +# CCFLAGS variable # +#################### + +# set correct CCFLAGS variable for kernels older than 2.6.24 +ifeq (0,$(shell [ ${KVER_CODE} -lt $(call get_kvercode,2,6,24) ]; echo $$?)) +CCFLAGS_VAR := EXTRA_CFLAGS +else +CCFLAGS_VAR := ccflags-y +endif + +################# +# KBUILD_OUTPUT # +################# + +# Only set KBUILD_OUTPUT if the real paths of KOBJ and KSRC differ +ifneq ($(call readlink,${KSRC}),$(call readlink,${KOBJ})) +export KBUILD_OUTPUT ?= ${KOBJ} +endif + +############################ +# Module Install Directory # +############################ + +# Default to using updates/drivers/net/ethernet/zte/ path, since depmod since +# v3.1 defaults to checking updates folder first, and only checking kernels/ +# and extra afterwards. We use updates instead of kernel/* due to desire to +# prevent over-writing built-in modules files. +export INSTALL_MOD_DIR ?= updates/drivers/net/ethernet/zte/${DRIVER} + +###################### +# Kernel Build Macro # +###################### + +# kernel build function +# ${1} is the kernel build target +# ${2} may contain any extra rules to pass directly to the sub-make process +# +# This function is expected to be executed by +# @+$(call kernelbuild,,) +# from within a Makefile recipe. +# +# The following variables are expected to be defined for its use: +# GCC_I_SYS -- if set it will enable use of gcc-i-sys.sh wrapper to use -isystem +# CCFLAGS_VAR -- the CCFLAGS variable to set extra CFLAGS +# EXTRA_CFLAGS -- a set of extra CFLAGS to pass into the ccflags-y variable +# KSRC -- the location of the kernel source tree to build against +# DRIVER_UPPERCASE -- the uppercase name of the kernel module, set from DRIVER +# W -- if set, enables the W= kernel warnings options +# C -- if set, enables the C= kernel sparse build options + +CWD := $(shell dirname $(CURDIR)) +ifneq (${TARGET_ARCH}, ) +NEED_CROSS_COMPILE := Yes +ifeq (${TARGET_ARCH}, aarch64) +ARCH := arm64 +endif +endif + +kernelbuild = $(call warn_signed_modules) \ + env CWD=$(CWD) ${MAKE} \ + -C "${KSRC}" M="$(CWD)"\ + CONFIG_DINGHAI_ETH=$(CONFIG_DINGHAI_ETH) \ + CONFIG_DINGHAI_MPF=$(CONFIG_DINGHAI_MPF) \ + CONFIG_DINGHAI_HPF=$(CONFIG_DINGHAI_HPF) \ + CONFIG_DINGHAI_PF=$(CONFIG_DINGHAI_PF) \ + CONFIG_DINGHAI_ZF_MPF=$(CONFIG_DINGHAI_ZF_MPF) \ + $(if ${NEED_CROSS_COMPILE}, ARCH=$(ARCH)) \ + $(if ${NEED_CROSS_COMPILE}, CROSS_COMPILE=$(CROSS_COMPILE)) \ + $(if ${DISABLE_MODULE_SIGNING},CONFIG_MODULE_SIG=n) \ + $(if ${DISABLE_MODULE_SIGNING},CONFIG_MODULE_SIG_ALL=) \ + ${2} ${1} diff --git a/src/net/build/spec/zxdh-eth.spec.example b/src/net/build/spec/zxdh-eth.spec.example new file mode 100644 index 0000000..5a52666 --- /dev/null +++ b/src/net/build/spec/zxdh-eth.spec.example @@ -0,0 +1,530 @@ +%global IS_RHEL_VENDOR "%{_vendor}" == "redhat" || ("%{_vendor}" == "bclinux") || ("%{_vendor}" == "openEuler") + +%{!?_name: %global _name zxdh-eth} +%{!?_version: %global _version 1.0} +%{!?_release: %global _release 1} + +%{!?_config_name: %global _config_name zxdh-smartnic-config} +%{!?_config_version: %global _config_version 1.0} +%{!?_config_release: %global _config_release 1} + +%{!?ETH_DRI_VER: %global ETH_DRI_VER 1.0-1} + +%{!?KSRC: %global KSRC /lib/modules/%(uname -r)/source} +%{!?target: %global target %(uname -m)} + +%if "%{_config_name}" == "zxdh-smartnic-config" +%global _config_file smart_nic_init +%else +%global _config_file dpu_init +%endif + +Name: %{_name} +Version: %{_version} +Release: %{_release}%{?dist} +Summary: ZTE(R) PCI Express Linux Network Driver +Source: %{_name}-%{_version}-%{_release}.tar.gz +Vendor: ZTE Corporation +License: @ +ExclusiveOS: linux +Group: System Environment/Kernel +Provides: %{_name} +URL: http://support.zte.com +BuildRoot: %{_tmppath}/%{_name}-%{_version}-root + +%global debug_package %{nil} +# macros for finding system files to update at install time (pci.ids, pcitable) +%define find() %(for f in %*; do if [ -e $f ]; then echo $f; break; fi; done) +%define _pciids /usr/share/pci.ids /usr/share/hwdata/pci.ids +%define _pcitable /usr/share/kudzu/pcitable /usr/share/hwdata/pcitable /dev/null +%define pciids %find %{_pciids} +%define pcitable %find %{_pcitable} + + +Requires: kernel, findutils, gawk, bash + +%global __strip /bin/true + +%description +This package contains the ZTE(R) PCI Express Linux Network Driver. + +%package -n %{_config_name} +Version: %{_config_version} +BuildArch: noarch +Release: %{_config_release} +Group: System Environment/Base +Summary: Smart NIC initial configuration file + +%description -n %{_config_name} +The smart-nic-init package contains the initial configuration file for smart NIC. + +# set modules dir +%if %{IS_RHEL_VENDOR} +%if 0%{?fedora} +%global install_mod_dir updates +%else +%global install_mod_dir extra/%{name} +%endif +%endif + +%if "%{_vendor}" == "suse" +%global install_mod_dir updates +%endif + +%{!?install_mod_dir: %global install_mod_dir updates} + + +%prep +%setup -q -n zxdh_kernel + +%build +cd ./build +./build.pl -t clean --ksrc %{KSRC} + +%if 0%{?CROSS_COMPILE:1} +# cross compile + +./build.pl -t kernel -m CONFIG_DINGHAI_ETH -m CONFIG_ZXDH_AUXILIARY -m CONFIG_DINGHAI_PF \ + -m CONFIG_ZXDH_SF -m CONFIG_DINGHAI_EN_AUX \ + -m HAVE_DEVLINK_ALLOC_GET_1_PARAMS -m HAVE_DEV_PM_DOMAIN_ATTACH \ + -m HAVE_BUS_FIND_DEVICE_GET_CONST -m CONFIG_DINGHAI_DH_CMD \ + -m CONFIG_DINGHAI_NP -m CONFIG_ZXDH_MSGQ \ + -m CONFIG_ZXDH_1588 -m CONFIG_DINGHAI_PTP \ + -m CONFIG_DINGHAI_TSN\ + --ksrc %{KSRC} \ + --cross_compile %{CROSS_COMPILE} \ + --target_arch %{target} \ + --dri_ver %{ETH_DRI_VER} +%else +# no cross compile +./build.pl -t kernel -m CONFIG_DINGHAI_ETH -m CONFIG_ZXDH_AUXILIARY -m CONFIG_DINGHAI_PF \ + -m CONFIG_ZXDH_SF -m CONFIG_DINGHAI_EN_AUX \ + -m HAVE_DEVLINK_ALLOC_GET_1_PARAMS -m HAVE_DEV_PM_DOMAIN_ATTACH \ + -m HAVE_BUS_FIND_DEVICE_GET_CONST -m CONFIG_DINGHAI_DH_CMD \ + -m CONFIG_DINGHAI_NP -m CONFIG_ZXDH_MSGQ \ + -m CONFIG_ZXDH_1588 -m CONFIG_DINGHAI_PTP \ + -m CONFIG_DINGHAI_TSN\ + --ksrc %{KSRC} \ + --dri_ver %{ETH_DRI_VER} +%endif + +%install +cd ./build + +export INSTALL_MOD_PATH=%{buildroot} +export INSTALL_MOD_DIR=%{install_mod_dir} +export KSRC=%{KSRC} +make modules_install INSTALL_MOD_PATH=%{buildroot} INSTALL_MOD_DIR=%{install_mod_dir} KSRC=%{KSRC} + +# Remove modules files that we do not want to include +find %{buildroot}/lib/modules/ -name 'modules.*' -exec rm -f {} \; + +cd %{buildroot} +find lib -name "*.ko" -printf "/%p\n" \ + >%{_builddir}/zxdh_kernel/file.list +export _ksrc=%{KSRC} + +# Add config files +%if %{IS_RHEL_VENDOR} +%if ! 0%{?fedora} +%{__install} -d %{buildroot}%{_sysconfdir}/depmod.d/ +for module in `find . -type f -name *.ko`; +do +ko_name=${module##*/} +mod_name=${ko_name/.ko*/} +mod_path=${module/*%{name}} +mod_path=${mod_path/\/${ko_name}} +echo "override ${mod_name} * weak-updates/%{name}${mod_path}" >> %{buildroot}%{_sysconfdir}/depmod.d/%{name}-${mod_name}.conf +echo "override ${mod_name} * extra/%{name}${mod_path}" >> %{buildroot}%{_sysconfdir}/depmod.d/%{name}-${mod_name}.conf +done +%endif +%endif + +# Add zxdh_en_aux udev conf + +%{__install} -d %{buildroot}%{_sysconfdir}/udev/rules.d/ +echo 'ACTION!="add", GOTO="drivers_end"' > %{buildroot}%{_sysconfdir}/udev/rules.d/80-%{name}-zxdh_en_aux-drivers.rules +echo 'ENV{MODALIAS}=="zxdh_auxiliary:zxdh_pf.en_aux", RUN{builtin}+="kmod load zxdh_en_aux"' >> %{buildroot}%{_sysconfdir}/udev/rules.d/80-%{name}-zxdh_en_aux-drivers.rules +echo 'LABEL="drivers_end"' >> %{buildroot}%{_sysconfdir}/udev/rules.d/80-%{name}-zxdh_en_aux-drivers.rules + +cd $HOME/rpmbuild/BUILD/zxdh_kernel/build/zxdh_config +%{__install} -m 644 ./%{_config_file}.cfg %{buildroot}%{_sysconfdir} + +%clean +rm -rf %{buildroot} + +%files -f file.list +%if %{IS_RHEL_VENDOR} +%if ! 0%{?fedora} +%config(noreplace) %{_sysconfdir}/depmod.d/%{name}-*.conf +%endif +%endif + +%{_sysconfdir}/udev/rules.d/80-%{name}-zxdh_en_aux-drivers.rules + + + +%defattr(-, root, root) +%doc file.list +%doc pci.updates + +%files -n %{_config_name} +%defattr(-, root, root,-) +%config %{_sysconfdir}/%{_config_file}.cfg + +%post +if [ -d /usr/local/share/%{name} ]; then + rm -rf /usr/local/share/%{name} +fi +mkdir /usr/local/share/%{name} +cp --parents %{pciids} /usr/local/share/%{name}/ +echo "original pci.ids saved in /usr/local/share/%{name}"; +if [ "%{pcitable}" != "/dev/null" ]; then + cp --parents %{pcitable} /usr/local/share/%{name}/ + echo "original pcitable saved in /usr/local/share/%{name}"; +fi + +LD="%{_docdir}/%{name}"; +if [ -d %{_docdir}/%{name}-%{version} ]; then + LD="%{_docdir}/%{name}-%{version}"; +fi + +#Yes, this really needs bash +bash -s %{pciids} \ + %{pcitable} \ + $LD/pci.updates \ + $LD/pci.ids.new \ + $LD/pcitable.new \ + %{name} \ +<<"END" +#! /bin/bash +# For licensing information, see the file 'LICENSE' in the root folder +# $1 = system pci.ids file to update +# $2 = system pcitable file to update +# $3 = file with new entries in pci.ids file format +# $4 = pci.ids output file +# $5 = pcitable output file +# $6 = driver name for use in pcitable file + +exec 3<$1 +exec 4<$2 +exec 5<$3 +exec 6>$4 +exec 7>$5 +driver=$6 +IFS= + +# pattern matching strings +ID="[[:xdigit:]][[:xdigit:]][[:xdigit:]][[:xdigit:]]" +VEN="${ID}*" +DEV=" ${ID}*" +SUB=" ${ID}*" +TABLE_DEV="0x${ID} 0x${ID} \"*" +TABLE_SUB="0x${ID} 0x${ID} 0x${ID} 0x${ID} \"*" + +line= +table_line= +ids_in= +table_in= +vendor= +device= +ids_device= +table_device= +subven= +ids_subven= +table_subven= +subdev= +ids_subdev= +table_subdev= +ven_str= +dev_str= +sub_str= + +# force a sub-shell to fork with a new stdin +# this is needed if the shell is reading these instructions from stdin +while true +do + # get the first line of each data file to jump start things + exec 0<&3 + read -r ids_in + if [ "$2" != "/dev/null" ];then + exec 0<&4 + read -r table_in + fi + + # outer loop reads lines from the updates file + exec 0<&5 + while read -r line + do + # vendor entry + if [[ $line == $VEN ]] + then + vendor=0x${line:0:4} + ven_str=${line#${line:0:6}} + # add entry to pci.ids + exec 0<&3 + exec 1>&6 + while [[ $ids_in != $VEN || + 0x${ids_in:0:4} < $vendor ]] + do + echo "$ids_in" + read -r ids_in + done + echo "$line" + if [[ 0x${ids_in:0:4} == $vendor ]] + then + read -r ids_in + fi + + # device entry + elif [[ $line == $DEV ]] + then + device=`echo ${line:1:4} | tr "[:upper:]" "[:lower:]"` + table_device=0x${line:1:4} + dev_str=${line#${line:0:7}} + ids_device=`echo ${ids_in:1:4} | tr "[:upper:]" "[:lower:]"` + table_line="$vendor $table_device \"$driver\" \"$ven_str|$dev_str\"" + # add entry to pci.ids + exec 0<&3 + exec 1>&6 + while [[ $ids_in != $DEV || + $ids_device < $device ]] + do + if [[ $ids_in == $VEN ]] + then + break + fi + if [[ $ids_device != ${ids_in:1:4} ]] + then + echo "${ids_in:0:1}$ids_device${ids_in#${ids_in:0:5}}" + else + echo "$ids_in" + fi + read -r ids_in + ids_device=`echo ${ids_in:1:4} | tr "[:upper:]" "[:lower:]"` + done + if [[ $device != ${line:1:4} ]] + then + echo "${line:0:1}$device${line#${line:0:5}}" + else + echo "$line" + fi + if [[ $ids_device == $device ]] + then + read -r ids_in + fi + # add entry to pcitable + if [ "$2" != "/dev/null" ];then + exec 0<&4 + exec 1>&7 + while [[ $table_in != $TABLE_DEV || + ${table_in:0:6} < $vendor || + ( ${table_in:0:6} == $vendor && + ${table_in:7:6} < $table_device ) ]] + do + echo "$table_in" + read -r table_in + done + echo "$table_line" + if [[ ${table_in:0:6} == $vendor && + ${table_in:7:6} == $table_device ]] + then + read -r table_in + fi + fi + # subsystem entry + elif [[ $line == $SUB ]] + then + subven=`echo ${line:2:4} | tr "[:upper:]" "[:lower:]"` + subdev=`echo ${line:7:4} | tr "[:upper:]" "[:lower:]"` + table_subven=0x${line:2:4} + table_subdev=0x${line:7:4} + sub_str=${line#${line:0:13}} + ids_subven=`echo ${ids_in:2:4} | tr "[:upper:]" "[:lower:]"` + ids_subdev=`echo ${ids_in:7:4} | tr "[:upper:]" "[:lower:]"` + table_line="$vendor $table_device $table_subven $table_subdev \"$driver\" \"$ven_str|$sub_str\"" + # add entry to pci.ids + exec 0<&3 + exec 1>&6 + while [[ $ids_in != $SUB || + $ids_subven < $subven || + ( $ids_subven == $subven && + $ids_subdev < $subdev ) ]] + do + if [[ $ids_in == $VEN || + $ids_in == $DEV ]] + then + break + fi + if [[ ! (${ids_in:2:4} == "1014" && + ${ids_in:7:4} == "052C") ]] + then + if [[ $ids_subven != ${ids_in:2:4} || $ids_subdev != ${ids_in:7:4} ]] + then + echo "${ids_in:0:2}$ids_subven $ids_subdev${ids_in#${ids_in:0:11}}" + else + echo "$ids_in" + fi + fi + read -r ids_in + ids_subven=`echo ${ids_in:2:4} | tr "[:upper:]" "[:lower:]"` + ids_subdev=`echo ${ids_in:7:4} | tr "[:upper:]" "[:lower:]"` + done + if [[ $subven != ${line:2:4} || $subdev != ${line:7:4} ]] + then + echo "${line:0:2}$subven $subdev${line#${line:0:11}}" + else + echo "$line" + fi + if [[ $ids_subven == $subven && + $ids_subdev == $subdev ]] + then + read -r ids_in + fi + # add entry to pcitable + if [ "$2" != "/dev/null" ];then + exec 0<&4 + exec 1>&7 + while [[ $table_in != $TABLE_SUB || + ${table_in:14:6} < $table_subven || + ( ${table_in:14:6} == $table_subven && + ${table_in:21:6} < $table_subdev ) ]] + do + if [[ $table_in == $TABLE_DEV ]] + then + break + fi + if [[ ! (${table_in:14:6} == "0x1014" && + ${table_in:21:6} == "0x052C") ]] + then + echo "$table_in" + fi + read -r table_in + done + echo "$table_line" + if [[ ${table_in:14:6} == $table_subven && + ${table_in:21:6} == $table_subdev ]] + then + read -r table_in + fi + fi + fi + + exec 0<&5 + done + + # print the remainder of the original files + exec 0<&3 + exec 1>&6 + echo "$ids_in" + while read -r ids_in + do + echo "$ids_in" + done + + if [ "$2" != "/dev/null" ];then + exec 0>&4 + exec 1>&7 + echo "$table_in" + while read -r table_in + do + echo "$table_in" + done + fi + + break +done <&5 + +exec 3<&- +exec 4<&- +exec 5<&- +exec 6>&- +exec 7>&- + +END + +mv -f $LD/pci.ids.new %{pciids} +if [ "%{pcitable}" != "/dev/null" ]; then + mv -f $LD/pcitable.new %{pcitable} +fi + +uname -r | grep BOOT || /sbin/depmod -a > /dev/null 2>&1 || true + +if [ -x "/usr/sbin/weak-modules" ]; then + modules=( $(cat %{_docdir}/%{name}/file.list | grep '\.ko$' | xargs realpath) ) + printf '%s\n' "${modules[@]}" | /usr/sbin/weak-modules --no-initramfs --add-modules +fi + +if which dracut >/dev/null 2>&1; then + if [[ `cat /etc/CGSL/cgsl-customize/extra_driver.conf 2>/dev/null | grep "^[[:space:]]*update_initramfs[[:space:]]*=[[:space:]]*no"` == "" ]]; then + echo "Updating initramfs with dracut..." + if dracut --force ; then + echo "Successfully updated initramfs." + else + echo "Failed to update initramfs." + echo "You must update your initramfs image for changes to take place." + exit -1 + fi + else + echo "You must update your initrd manually for changes to take place, please execute the command: dracut --force" + fi +elif which mkinitrd >/dev/null 2>&1; then + echo "Updating initrd with mkinitrd..." + if mkinitrd; then + echo "Successfully updated initrd." + else + echo "Failed to update initrd." + echo "You must update your initrd image for changes to take place." + exit -1 + fi +else + echo "Unable to determine utility to update initrd image." + echo "You must update your initrd manually for changes to take place." + exit -1 +fi + +%preun +# save tmp list of installed kernel modules for weak-modules +cat %{_docdir}/%{name}/file.list | grep '\.ko$' | xargs realpath > /var/run/rpm-%{name}-modules.list + +rm -rf /usr/local/share/%{name} + +%postun +uname -r | grep BOOT || /sbin/depmod -a > /dev/null 2>&1 || true + +if [ -x "/usr/sbin/weak-modules" ]; then + modules=( $(cat /var/run/rpm-%{name}-modules.list) ) + printf '%s\n' "${modules[@]}" | /usr/sbin/weak-modules --no-initramfs --remove-modules +fi +rm /var/run/rpm-%{name}-modules.list + +if which dracut >/dev/null 2>&1; then + if [[ `cat /etc/CGSL/cgsl-customize/extra_driver.conf 2>/dev/null | grep "^[[:space:]]*update_initramfs[[:space:]]*=[[:space:]]*no"` == "" ]]; then + echo "Updating initramfs with dracut..." + if dracut --force ; then + echo "Successfully updated initramfs." + else + echo "Failed to update initramfs." + echo "You must update your initramfs image for changes to take place." + exit -1 + fi + else + echo "You must update your initrd manually for changes to take place, please execute the command: dracut --force" + fi +elif which mkinitrd >/dev/null 2>&1; then + echo "Updating initrd with mkinitrd..." + if mkinitrd; then + echo "Successfully updated initrd." + else + echo "Failed to update initrd." + echo "You must update your initrd image for changes to take place." + exit -1 + fi +else + echo "Unable to determine utility to update initrd image." + echo "You must update your initrd manually for changes to take place." + exit -1 +fi + +%changelog +#let's skip this for now diff --git a/src/net/build/spec/zxdh-hpf.spec.example b/src/net/build/spec/zxdh-hpf.spec.example new file mode 100644 index 0000000..3dd09b0 --- /dev/null +++ b/src/net/build/spec/zxdh-hpf.spec.example @@ -0,0 +1,484 @@ +%global IS_RHEL_VENDOR "%{_vendor}" == "redhat" || ("%{_vendor}" == "bclinux") || ("%{_vendor}" == "openEuler") + +%{!?_name: %global _name zxdh-hpf} +%{!?_version: %global _version 1.0} +%{!?_release: %global _release 1} + +%{!?HPF_DRI_VER: %global HPF_DRI_VER 1.0-1} + +%{!?KSRC: %global KSRC /lib/modules/%(uname -r)/source} +%{!?target: %global target %(uname -m)} + +Name: %{_name} +Version: %{_version} +Release: %{_release}%{?dist} +Summary: ZTE(R) PCI Express Linux Hot-Plug PF Network Driver. +Source: %{_name}-%{_version}-%{_release}.tar.gz +Vendor: ZTE Corporation +License: @ +ExclusiveOS: linux +Group: System Environment/Kernel +Provides: %{_name} +URL: http://support.zte.com +BuildRoot: %{_tmppath}/%{_name}-%{_version}-root + +%global debug_package %{nil} +# macros for finding system files to update at install time (pci.ids, pcitable) +%define find() %(for f in %*; do if [ -e $f ]; then echo $f; break; fi; done) +%define _pciids /usr/share/pci.ids /usr/share/hwdata/pci.ids +%define _pcitable /usr/share/kudzu/pcitable /usr/share/hwdata/pcitable /dev/null +%define pciids %find %{_pciids} +%define pcitable %find %{_pcitable} + + +Requires: kernel, findutils, gawk, bash +%global __strip /bin/true + +%description +This package contains the ZTE(R) PCI Express Linux Hot-Plug PF Network Driver. + + +# set modules dir +%if %{IS_RHEL_VENDOR} +%if 0%{?fedora} +%global install_mod_dir updates +%else +%global install_mod_dir extra/%{name} +%endif +%endif + +%if "%{_vendor}" == "suse" +%global install_mod_dir updates +%endif + +%{!?install_mod_dir: %global install_mod_dir updates} + + +%prep +%setup -q -n zxdh_kernel + +%build +cd ./build +./build.pl -t clean --ksrc %{KSRC} + + +%if 0%{?CROSS_COMPILE:1} +# cross compile +./build.pl -t kernel -m CONFIG_DINGHAI_ETH -m CONFIG_DINGHAI_HPF -m CONFIG_DINGHAI_DH_CMD -m HAVE_DEVLINK_ALLOC_GET_1_PARAMS\ + --ksrc %{KSRC} \ + --cross_compile %{CROSS_COMPILE} \ + --target_arch %{target} \ + --dri_ver %{HPF_DRI_VER} +%else +# no cross compile +./build.pl -t kernel -m CONFIG_DINGHAI_ETH -m CONFIG_DINGHAI_HPF -m CONFIG_DINGHAI_DH_CMD -m HAVE_DEVLINK_ALLOC_GET_1_PARAMS\ + --ksrc %{KSRC} \ + --dri_ver %{HPF_DRI_VER} +%endif + +%install +cd ./build + +export INSTALL_MOD_PATH=%{buildroot} +export INSTALL_MOD_DIR=%{install_mod_dir} +export KSRC=%{KSRC} +make modules_install INSTALL_MOD_PATH=%{buildroot} INSTALL_MOD_DIR=%{install_mod_dir} KSRC=%{KSRC} + +# Remove modules files that we do not want to include +find %{buildroot}/lib/modules/ -name 'modules.*' -exec rm -f {} \; + +cd %{buildroot} +find lib -name "*.ko" -printf "/%p\n" \ + >%{_builddir}/zxdh_kernel/hpf_file.list +export _ksrc=%{KSRC} + + +# Add config files +%if %{IS_RHEL_VENDOR} +%if ! 0%{?fedora} +%{__install} -d %{buildroot}%{_sysconfdir}/depmod.d/ +for module in `find . -type f -name *.ko`; +do +ko_name=${module##*/} +mod_name=${ko_name/.ko*/} +mod_path=${module/*%{name}} +mod_path=${mod_path/\/${ko_name}} +echo "override ${mod_name} * weak-updates/%{name}${mod_path}" >> %{buildroot}%{_sysconfdir}/depmod.d/%{name}-${mod_name}.conf +echo "override ${mod_name} * extra/%{name}${mod_path}" >> %{buildroot}%{_sysconfdir}/depmod.d/%{name}-${mod_name}.conf +done +%endif +%endif + +%clean +rm -rf %{buildroot} + + +%files -f hpf_file.list +%if %{IS_RHEL_VENDOR} +%if ! 0%{?fedora} +%config(noreplace) %{_sysconfdir}/depmod.d/%{name}-*.conf +%endif +%endif + + +%defattr(-, root, root) +%doc hpf_file.list +%doc pci.updates + + +%post +if [ -d /usr/local/share/%{name} ]; then + rm -rf /usr/local/share/%{name} +fi +mkdir /usr/local/share/%{name} +cp --parents %{pciids} /usr/local/share/%{name}/ +echo "original pci.ids saved in /usr/local/share/%{name}"; +if [ "%{pcitable}" != "/dev/null" ]; then + cp --parents %{pcitable} /usr/local/share/%{name}/ + echo "original pcitable saved in /usr/local/share/%{name}"; +fi + +LD="%{_docdir}/%{name}"; +if [ -d %{_docdir}/%{name}-%{version} ]; then + LD="%{_docdir}/%{name}-%{version}"; +fi + +#Yes, this really needs bash +bash -s %{pciids} \ + %{pcitable} \ + $LD/pci.updates \ + $LD/pci.ids.new \ + $LD/pcitable.new \ + %{name} \ +<<"END" +#! /bin/bash +# For licensing information, see the file 'LICENSE' in the root folder +# $1 = system pci.ids file to update +# $2 = system pcitable file to update +# $3 = file with new entries in pci.ids file format +# $4 = pci.ids output file +# $5 = pcitable output file +# $6 = driver name for use in pcitable file + +exec 3<$1 +exec 4<$2 +exec 5<$3 +exec 6>$4 +exec 7>$5 +driver=$6 +IFS= + +# pattern matching strings +ID="[[:xdigit:]][[:xdigit:]][[:xdigit:]][[:xdigit:]]" +VEN="${ID}*" +DEV=" ${ID}*" +SUB=" ${ID}*" +TABLE_DEV="0x${ID} 0x${ID} \"*" +TABLE_SUB="0x${ID} 0x${ID} 0x${ID} 0x${ID} \"*" + +line= +table_line= +ids_in= +table_in= +vendor= +device= +ids_device= +table_device= +subven= +ids_subven= +table_subven= +subdev= +ids_subdev= +table_subdev= +ven_str= +dev_str= +sub_str= + +# force a sub-shell to fork with a new stdin +# this is needed if the shell is reading these instructions from stdin +while true +do + # get the first line of each data file to jump start things + exec 0<&3 + read -r ids_in + if [ "$2" != "/dev/null" ];then + exec 0<&4 + read -r table_in + fi + + # outer loop reads lines from the updates file + exec 0<&5 + while read -r line + do + # vendor entry + if [[ $line == $VEN ]] + then + vendor=0x${line:0:4} + ven_str=${line#${line:0:6}} + # add entry to pci.ids + exec 0<&3 + exec 1>&6 + while [[ $ids_in != $VEN || + 0x${ids_in:0:4} < $vendor ]] + do + echo "$ids_in" + read -r ids_in + done + echo "$line" + if [[ 0x${ids_in:0:4} == $vendor ]] + then + read -r ids_in + fi + + # device entry + elif [[ $line == $DEV ]] + then + device=`echo ${line:1:4} | tr "[:upper:]" "[:lower:]"` + table_device=0x${line:1:4} + dev_str=${line#${line:0:7}} + ids_device=`echo ${ids_in:1:4} | tr "[:upper:]" "[:lower:]"` + table_line="$vendor $table_device \"$driver\" \"$ven_str|$dev_str\"" + # add entry to pci.ids + exec 0<&3 + exec 1>&6 + while [[ $ids_in != $DEV || + $ids_device < $device ]] + do + if [[ $ids_in == $VEN ]] + then + break + fi + if [[ $ids_device != ${ids_in:1:4} ]] + then + echo "${ids_in:0:1}$ids_device${ids_in#${ids_in:0:5}}" + else + echo "$ids_in" + fi + read -r ids_in + ids_device=`echo ${ids_in:1:4} | tr "[:upper:]" "[:lower:]"` + done + if [[ $device != ${line:1:4} ]] + then + echo "${line:0:1}$device${line#${line:0:5}}" + else + echo "$line" + fi + if [[ $ids_device == $device ]] + then + read -r ids_in + fi + # add entry to pcitable + if [ "$2" != "/dev/null" ];then + exec 0<&4 + exec 1>&7 + while [[ $table_in != $TABLE_DEV || + ${table_in:0:6} < $vendor || + ( ${table_in:0:6} == $vendor && + ${table_in:7:6} < $table_device ) ]] + do + echo "$table_in" + read -r table_in + done + echo "$table_line" + if [[ ${table_in:0:6} == $vendor && + ${table_in:7:6} == $table_device ]] + then + read -r table_in + fi + fi + # subsystem entry + elif [[ $line == $SUB ]] + then + subven=`echo ${line:2:4} | tr "[:upper:]" "[:lower:]"` + subdev=`echo ${line:7:4} | tr "[:upper:]" "[:lower:]"` + table_subven=0x${line:2:4} + table_subdev=0x${line:7:4} + sub_str=${line#${line:0:13}} + ids_subven=`echo ${ids_in:2:4} | tr "[:upper:]" "[:lower:]"` + ids_subdev=`echo ${ids_in:7:4} | tr "[:upper:]" "[:lower:]"` + table_line="$vendor $table_device $table_subven $table_subdev \"$driver\" \"$ven_str|$sub_str\"" + # add entry to pci.ids + exec 0<&3 + exec 1>&6 + while [[ $ids_in != $SUB || + $ids_subven < $subven || + ( $ids_subven == $subven && + $ids_subdev < $subdev ) ]] + do + if [[ $ids_in == $VEN || + $ids_in == $DEV ]] + then + break + fi + if [[ ! (${ids_in:2:4} == "1014" && + ${ids_in:7:4} == "052C") ]] + then + if [[ $ids_subven != ${ids_in:2:4} || $ids_subdev != ${ids_in:7:4} ]] + then + echo "${ids_in:0:2}$ids_subven $ids_subdev${ids_in#${ids_in:0:11}}" + else + echo "$ids_in" + fi + fi + read -r ids_in + ids_subven=`echo ${ids_in:2:4} | tr "[:upper:]" "[:lower:]"` + ids_subdev=`echo ${ids_in:7:4} | tr "[:upper:]" "[:lower:]"` + done + if [[ $subven != ${line:2:4} || $subdev != ${line:7:4} ]] + then + echo "${line:0:2}$subven $subdev${line#${line:0:11}}" + else + echo "$line" + fi + if [[ $ids_subven == $subven && + $ids_subdev == $subdev ]] + then + read -r ids_in + fi + # add entry to pcitable + if [ "$2" != "/dev/null" ];then + exec 0<&4 + exec 1>&7 + while [[ $table_in != $TABLE_SUB || + ${table_in:14:6} < $table_subven || + ( ${table_in:14:6} == $table_subven && + ${table_in:21:6} < $table_subdev ) ]] + do + if [[ $table_in == $TABLE_DEV ]] + then + break + fi + if [[ ! (${table_in:14:6} == "0x1014" && + ${table_in:21:6} == "0x052C") ]] + then + echo "$table_in" + fi + read -r table_in + done + echo "$table_line" + if [[ ${table_in:14:6} == $table_subven && + ${table_in:21:6} == $table_subdev ]] + then + read -r table_in + fi + fi + fi + + exec 0<&5 + done + + # print the remainder of the original files + exec 0<&3 + exec 1>&6 + echo "$ids_in" + while read -r ids_in + do + echo "$ids_in" + done + + if [ "$2" != "/dev/null" ];then + exec 0>&4 + exec 1>&7 + echo "$table_in" + while read -r table_in + do + echo "$table_in" + done + fi + + break +done <&5 + +exec 3<&- +exec 4<&- +exec 5<&- +exec 6>&- +exec 7>&- + +END + +mv -f $LD/pci.ids.new %{pciids} +if [ "%{pcitable}" != "/dev/null" ]; then + mv -f $LD/pcitable.new %{pcitable} +fi + +uname -r | grep BOOT || /sbin/depmod -a > /dev/null 2>&1 || true + +if [ -x "/usr/sbin/weak-modules" ]; then + modules=( $(cat %{_docdir}/%{name}/hpf_file.list | grep '\.ko$' | xargs realpath) ) + printf '%s\n' "${modules[@]}" | /usr/sbin/weak-modules --no-initramfs --add-modules +fi + +if which dracut >/dev/null 2>&1; then + if [[ `cat /etc/CGSL/cgsl-customize/extra_driver.conf 2>/dev/null | grep "^[[:space:]]*update_initramfs[[:space:]]*=[[:space:]]*no"` == "" ]]; then + echo "Updating initramfs with dracut..." + if dracut --force ; then + echo "Successfully updated initramfs." + else + echo "Failed to update initramfs." + echo "You must update your initramfs image for changes to take place." + exit -1 + fi + else + echo "You must update your initrd manually for changes to take place, please execute the command: dracut --force" + fi +elif which mkinitrd >/dev/null 2>&1; then + echo "Updating initrd with mkinitrd..." + if mkinitrd; then + echo "Successfully updated initrd." + else + echo "Failed to update initrd." + echo "You must update your initrd image for changes to take place." + exit -1 + fi +else + echo "Unable to determine utility to update initrd image." + echo "You must update your initrd manually for changes to take place." + exit -1 +fi + +%preun +# save tmp list of installed kernel modules for weak-modules +cat %{_docdir}/%{name}/hpf_file.list | grep '\.ko$' | xargs realpath > /var/run/rpm-%{name}-modules.list + +rm -rf /usr/local/share/%{name} + +%postun +uname -r | grep BOOT || /sbin/depmod -a > /dev/null 2>&1 || true + +if [ -x "/usr/sbin/weak-modules" ]; then + modules=( $(cat /var/run/rpm-%{name}-modules.list) ) + printf '%s\n' "${modules[@]}" | /usr/sbin/weak-modules --no-initramfs --remove-modules +fi +rm /var/run/rpm-%{name}-modules.list + +if which dracut >/dev/null 2>&1; then + if [[ `cat /etc/CGSL/cgsl-customize/extra_driver.conf 2>/dev/null | grep "^[[:space:]]*update_initramfs[[:space:]]*=[[:space:]]*no"` == "" ]]; then + echo "Updating initramfs with dracut..." + if dracut --force ; then + echo "Successfully updated initramfs." + else + echo "Failed to update initramfs." + echo "You must update your initramfs image for changes to take place." + exit -1 + fi + else + echo "You must update your initrd manually for changes to take place, please execute the command: dracut --force" + fi +elif which mkinitrd >/dev/null 2>&1; then + echo "Updating initrd with mkinitrd..." + if mkinitrd; then + echo "Successfully updated initrd." + else + echo "Failed to update initrd." + echo "You must update your initrd image for changes to take place." + exit -1 + fi +else + echo "Unable to determine utility to update initrd image." + echo "You must update your initrd manually for changes to take place." + exit -1 +fi + +%changelog +#let's skip this for now diff --git a/src/net/build/spec/zxdh-zf-mpf.spec.example b/src/net/build/spec/zxdh-zf-mpf.spec.example new file mode 100644 index 0000000..d918da7 --- /dev/null +++ b/src/net/build/spec/zxdh-zf-mpf.spec.example @@ -0,0 +1,494 @@ +%global IS_RHEL_VENDOR "%{_vendor}" == "redhat" || ("%{_vendor}" == "bclinux") || ("%{_vendor}" == "openEuler") + +%{!?_name: %global _name zxdh-zf-mpf} +%{!?_version: %global _version 1.0} +%{!?_release: %global _release 1} + +%{!?ZF_MPF_DRI_VER: %global ZF_MPF_DRI_VER 1.0-1} + +%{!?KSRC: %global KSRC /lib/modules/%(uname -r)/source} +%{!?target: %global target aarch64} + + +Name: %{_name} +Version: %{_version} +Release: %{_release}%{?dist} +Summary: ZTE(R) PCI Express Linux ZF MPF Network Driver +Source: %{_name}-%{_version}-%{_release}.tar.gz +Vendor: ZTE Corporation +License: @ +ExclusiveOS: linux +Group: System Environment/Kernel +Provides: %{_name} +URL: http://support.zte.com +BuildRoot: %{_tmppath}/%{_name}-%{_version}-root + +%global debug_package %{nil} +# macros for finding system files to update at install time (pci.ids, pcitable) +%define find() %(for f in %*; do if [ -e $f ]; then echo $f; break; fi; done) +%define _pciids /usr/share/pci.ids /usr/share/hwdata/pci.ids +%define _pcitable /usr/share/kudzu/pcitable /usr/share/hwdata/pcitable /dev/null +%define pciids %find %{_pciids} +%define pcitable %find %{_pcitable} + + +Requires: kernel, findutils, gawk, bash +%global __strip /bin/true + +%description +This package contains the ZTE(R) PCI Express Linux ZF MPF Network Driver. + + +# set modules dir +%if %{IS_RHEL_VENDOR} +%if 0%{?fedora} +%global install_mod_dir updates +%else +%global install_mod_dir extra/%{name} +%endif +%endif + +%if "%{_vendor}" == "suse" +%global install_mod_dir updates +%endif + +%{!?install_mod_dir: %global install_mod_dir updates} + + +%prep +%setup -q -n zxdh_kernel + +%build +cd ./build +./build.pl -t clean --ksrc %{KSRC} + + +%if 0%{?CROSS_COMPILE:1} +# cross compile +./build.pl -t kernel -m CONFIG_DINGHAI_ETH -m CONFIG_ZXDH_AUXILIARY -m CONFIG_DINGHAI_ZF_MPF \ + -m PCIE_ZF_EPC_OPEN -m CONFIG_DINGHAI_DH_CMD \ + -m CONFIG_ZXDH_SF -m HAVE_DEVLINK_ALLOC_GET_1_PARAMS \ + -m HAVE_DEV_PM_DOMAIN_ATTACH -m HAVE_BUS_FIND_DEVICE_GET_CONST \ + -m CONFIG_ZF_GDMA \ + --ksrc %{KSRC} \ + --cross_compile %{CROSS_COMPILE} \ + --target_arch %{target} \ + --dri_ver %{ZF_MPF_DRI_VER} +%else +# no cross compile +./build.pl -t kernel -m CONFIG_DINGHAI_ETH -m CONFIG_ZXDH_AUXILIARY -m CONFIG_DINGHAI_ZF_MPF \ + -m PCIE_ZF_EPC_OPEN -m CONFIG_DINGHAI_DH_CMD \ + -m CONFIG_ZXDH_SF -m HAVE_DEVLINK_ALLOC_GET_1_PARAMS \ + -m HAVE_DEV_PM_DOMAIN_ATTACH -m HAVE_BUS_FIND_DEVICE_GET_CONST \ + -m CONFIG_ZF_GDMA \ + --ksrc %{KSRC} \ + --dri_ver %{ZF_MPF_DRI_VER} +%endif + +%install +cd ./build + +export INSTALL_MOD_PATH=%{buildroot} +export INSTALL_MOD_DIR=%{install_mod_dir} +export KSRC=%{KSRC} +make modules_install INSTALL_MOD_PATH=%{buildroot} INSTALL_MOD_DIR=%{install_mod_dir} KSRC=%{KSRC} + +# Remove modules files that we do not want to include +find %{buildroot}/lib/modules/ -name 'modules.*' -exec rm -f {} \; +find %{buildroot}/lib/modules/ -name '*zf_epf.ko' -exec rm -f {} \; + +cd %{buildroot} +find lib -name "*.ko" -printf "/%p\n" \ + >%{_builddir}/zxdh_kernel/zf_mpf_file.list +export _ksrc=%{KSRC} + + +# Add config files +%if %{IS_RHEL_VENDOR} +%if ! 0%{?fedora} +%{__install} -d %{buildroot}%{_sysconfdir}/depmod.d/ +for module in `find . -type f -name *.ko`; +do +ko_name=${module##*/} +mod_name=${ko_name/.ko*/} +mod_path=${module/*%{name}} +mod_path=${mod_path/\/${ko_name}} +echo "override ${mod_name} * weak-updates/%{name}${mod_path}" >> %{buildroot}%{_sysconfdir}/depmod.d/%{name}-${mod_name}.conf +echo "override ${mod_name} * extra/%{name}${mod_path}" >> %{buildroot}%{_sysconfdir}/depmod.d/%{name}-${mod_name}.conf +done +%endif +%endif + +%clean +rm -rf %{buildroot} + + +%files -f zf_mpf_file.list +%if %{IS_RHEL_VENDOR} +%if ! 0%{?fedora} +%config(noreplace) %{_sysconfdir}/depmod.d/%{name}-*.conf +%endif +%endif + + +%defattr(-, root, root) +%doc zf_mpf_file.list +%doc pci.updates + + +%post +if [ -d /usr/local/share/%{name} ]; then + rm -rf /usr/local/share/%{name} +fi +mkdir /usr/local/share/%{name} +cp --parents %{pciids} /usr/local/share/%{name}/ +echo "original pci.ids saved in /usr/local/share/%{name}"; +if [ "%{pcitable}" != "/dev/null" ]; then + cp --parents %{pcitable} /usr/local/share/%{name}/ + echo "original pcitable saved in /usr/local/share/%{name}"; +fi + +LD="%{_docdir}/%{name}"; +if [ -d %{_docdir}/%{name}-%{version} ]; then + LD="%{_docdir}/%{name}-%{version}"; +fi + +#Yes, this really needs bash +bash -s %{pciids} \ + %{pcitable} \ + $LD/pci.updates \ + $LD/pci.ids.new \ + $LD/pcitable.new \ + %{name} \ +<<"END" +#! /bin/bash +# For licensing information, see the file 'LICENSE' in the root folder +# $1 = system pci.ids file to update +# $2 = system pcitable file to update +# $3 = file with new entries in pci.ids file format +# $4 = pci.ids output file +# $5 = pcitable output file +# $6 = driver name for use in pcitable file + +exec 3<$1 +exec 4<$2 +exec 5<$3 +exec 6>$4 +exec 7>$5 +driver=$6 +IFS= + +# pattern matching strings +ID="[[:xdigit:]][[:xdigit:]][[:xdigit:]][[:xdigit:]]" +VEN="${ID}*" +DEV=" ${ID}*" +SUB=" ${ID}*" +TABLE_DEV="0x${ID} 0x${ID} \"*" +TABLE_SUB="0x${ID} 0x${ID} 0x${ID} 0x${ID} \"*" + +line= +table_line= +ids_in= +table_in= +vendor= +device= +ids_device= +table_device= +subven= +ids_subven= +table_subven= +subdev= +ids_subdev= +table_subdev= +ven_str= +dev_str= +sub_str= + +# force a sub-shell to fork with a new stdin +# this is needed if the shell is reading these instructions from stdin +while true +do + # get the first line of each data file to jump start things + exec 0<&3 + read -r ids_in + if [ "$2" != "/dev/null" ];then + exec 0<&4 + read -r table_in + fi + + # outer loop reads lines from the updates file + exec 0<&5 + while read -r line + do + # vendor entry + if [[ $line == $VEN ]] + then + vendor=0x${line:0:4} + ven_str=${line#${line:0:6}} + # add entry to pci.ids + exec 0<&3 + exec 1>&6 + while [[ $ids_in != $VEN || + 0x${ids_in:0:4} < $vendor ]] + do + echo "$ids_in" + read -r ids_in + done + echo "$line" + if [[ 0x${ids_in:0:4} == $vendor ]] + then + read -r ids_in + fi + + # device entry + elif [[ $line == $DEV ]] + then + device=`echo ${line:1:4} | tr "[:upper:]" "[:lower:]"` + table_device=0x${line:1:4} + dev_str=${line#${line:0:7}} + ids_device=`echo ${ids_in:1:4} | tr "[:upper:]" "[:lower:]"` + table_line="$vendor $table_device \"$driver\" \"$ven_str|$dev_str\"" + # add entry to pci.ids + exec 0<&3 + exec 1>&6 + while [[ $ids_in != $DEV || + $ids_device < $device ]] + do + if [[ $ids_in == $VEN ]] + then + break + fi + if [[ $ids_device != ${ids_in:1:4} ]] + then + echo "${ids_in:0:1}$ids_device${ids_in#${ids_in:0:5}}" + else + echo "$ids_in" + fi + read -r ids_in + ids_device=`echo ${ids_in:1:4} | tr "[:upper:]" "[:lower:]"` + done + if [[ $device != ${line:1:4} ]] + then + echo "${line:0:1}$device${line#${line:0:5}}" + else + echo "$line" + fi + if [[ $ids_device == $device ]] + then + read -r ids_in + fi + # add entry to pcitable + if [ "$2" != "/dev/null" ];then + exec 0<&4 + exec 1>&7 + while [[ $table_in != $TABLE_DEV || + ${table_in:0:6} < $vendor || + ( ${table_in:0:6} == $vendor && + ${table_in:7:6} < $table_device ) ]] + do + echo "$table_in" + read -r table_in + done + echo "$table_line" + if [[ ${table_in:0:6} == $vendor && + ${table_in:7:6} == $table_device ]] + then + read -r table_in + fi + fi + # subsystem entry + elif [[ $line == $SUB ]] + then + subven=`echo ${line:2:4} | tr "[:upper:]" "[:lower:]"` + subdev=`echo ${line:7:4} | tr "[:upper:]" "[:lower:]"` + table_subven=0x${line:2:4} + table_subdev=0x${line:7:4} + sub_str=${line#${line:0:13}} + ids_subven=`echo ${ids_in:2:4} | tr "[:upper:]" "[:lower:]"` + ids_subdev=`echo ${ids_in:7:4} | tr "[:upper:]" "[:lower:]"` + table_line="$vendor $table_device $table_subven $table_subdev \"$driver\" \"$ven_str|$sub_str\"" + # add entry to pci.ids + exec 0<&3 + exec 1>&6 + while [[ $ids_in != $SUB || + $ids_subven < $subven || + ( $ids_subven == $subven && + $ids_subdev < $subdev ) ]] + do + if [[ $ids_in == $VEN || + $ids_in == $DEV ]] + then + break + fi + if [[ ! (${ids_in:2:4} == "1014" && + ${ids_in:7:4} == "052C") ]] + then + if [[ $ids_subven != ${ids_in:2:4} || $ids_subdev != ${ids_in:7:4} ]] + then + echo "${ids_in:0:2}$ids_subven $ids_subdev${ids_in#${ids_in:0:11}}" + else + echo "$ids_in" + fi + fi + read -r ids_in + ids_subven=`echo ${ids_in:2:4} | tr "[:upper:]" "[:lower:]"` + ids_subdev=`echo ${ids_in:7:4} | tr "[:upper:]" "[:lower:]"` + done + if [[ $subven != ${line:2:4} || $subdev != ${line:7:4} ]] + then + echo "${line:0:2}$subven $subdev${line#${line:0:11}}" + else + echo "$line" + fi + if [[ $ids_subven == $subven && + $ids_subdev == $subdev ]] + then + read -r ids_in + fi + # add entry to pcitable + if [ "$2" != "/dev/null" ];then + exec 0<&4 + exec 1>&7 + while [[ $table_in != $TABLE_SUB || + ${table_in:14:6} < $table_subven || + ( ${table_in:14:6} == $table_subven && + ${table_in:21:6} < $table_subdev ) ]] + do + if [[ $table_in == $TABLE_DEV ]] + then + break + fi + if [[ ! (${table_in:14:6} == "0x1014" && + ${table_in:21:6} == "0x052C") ]] + then + echo "$table_in" + fi + read -r table_in + done + echo "$table_line" + if [[ ${table_in:14:6} == $table_subven && + ${table_in:21:6} == $table_subdev ]] + then + read -r table_in + fi + fi + fi + + exec 0<&5 + done + + # print the remainder of the original files + exec 0<&3 + exec 1>&6 + echo "$ids_in" + while read -r ids_in + do + echo "$ids_in" + done + + if [ "$2" != "/dev/null" ];then + exec 0>&4 + exec 1>&7 + echo "$table_in" + while read -r table_in + do + echo "$table_in" + done + fi + + break +done <&5 + +exec 3<&- +exec 4<&- +exec 5<&- +exec 6>&- +exec 7>&- + +END + +mv -f $LD/pci.ids.new %{pciids} +if [ "%{pcitable}" != "/dev/null" ]; then + mv -f $LD/pcitable.new %{pcitable} +fi + +uname -r | grep BOOT || /sbin/depmod -a > /dev/null 2>&1 || true + +if [ -x "/usr/sbin/weak-modules" ]; then + modules=( $(cat %{_docdir}/%{name}/zf_mpf_file.list | grep '\.ko$' | xargs realpath) ) + printf '%s\n' "${modules[@]}" | /usr/sbin/weak-modules --no-initramfs --add-modules +fi + +if which dracut >/dev/null 2>&1; then + if [[ `cat /etc/CGSL/cgsl-customize/extra_driver.conf 2>/dev/null | grep "^[[:space:]]*update_initramfs[[:space:]]*=[[:space:]]*no"` == "" ]]; then + echo "Updating initramfs with dracut..." + if dracut --force ; then + echo "Successfully updated initramfs." + else + echo "Failed to update initramfs." + echo "You must update your initramfs image for changes to take place." + exit -1 + fi + else + echo "You must update your initrd manually for changes to take place, please execute the command: dracut --force" + fi +elif which mkinitrd >/dev/null 2>&1; then + echo "Updating initrd with mkinitrd..." + if mkinitrd; then + echo "Successfully updated initrd." + else + echo "Failed to update initrd." + echo "You must update your initrd image for changes to take place." + exit -1 + fi +else + echo "Unable to determine utility to update initrd image." + echo "You must update your initrd manually for changes to take place." + exit -1 +fi + +%preun +# save tmp list of installed kernel modules for weak-modules +cat %{_docdir}/%{name}/zf_mpf_file.list | grep '\.ko$' | xargs realpath > /var/run/rpm-%{name}-modules.list + +rm -rf /usr/local/share/%{name} + +%postun +uname -r | grep BOOT || /sbin/depmod -a > /dev/null 2>&1 || true + +if [ -x "/usr/sbin/weak-modules" ]; then + modules=( $(cat /var/run/rpm-%{name}-modules.list) ) + printf '%s\n' "${modules[@]}" | /usr/sbin/weak-modules --no-initramfs --remove-modules +fi +rm /var/run/rpm-%{name}-modules.list + +if which dracut >/dev/null 2>&1; then + if [[ `cat /etc/CGSL/cgsl-customize/extra_driver.conf 2>/dev/null | grep "^[[:space:]]*update_initramfs[[:space:]]*=[[:space:]]*no"` == "" ]]; then + echo "Updating initramfs with dracut..." + if dracut --force ; then + echo "Successfully updated initramfs." + else + echo "Failed to update initramfs." + echo "You must update your initramfs image for changes to take place." + exit -1 + fi + else + echo "You must update your initrd manually for changes to take place, please execute the command: dracut --force" + fi +elif which mkinitrd >/dev/null 2>&1; then + echo "Updating initrd with mkinitrd..." + if mkinitrd; then + echo "Successfully updated initrd." + else + echo "Failed to update initrd." + echo "You must update your initrd image for changes to take place." + exit -1 + fi +else + echo "Unable to determine utility to update initrd image." + echo "You must update your initrd manually for changes to take place." + exit -1 +fi + +%changelog +#let's skip this for now diff --git a/src/net/build/zxdh_config/dpu_init.cfg b/src/net/build/zxdh_config/dpu_init.cfg new file mode 100755 index 0000000..243fddf --- /dev/null +++ b/src/net/build/zxdh_config/dpu_init.cfg @@ -0,0 +1,29 @@ +{ + "device_pcie_list_api_name": "neo_get_bdf_info.py", + "flow_merge_enable": "true", + "vdpa_type": "0", + "vswitch_cfg": { + "bond_info": { + "bus_name": "pci", + "prefix": "", + "linux-device": ["1cf2:8047"], + "dpdk-device": "1cf2:8048" + }, + "vport_info": { + "bus_name": "vdev", + "prefix": "net_zxdhx_", + "max_queue_num":"8" + }, + "upcall-queue": { + "vm-queue-total-num": "1" + }, + "reinject-queue": { + "vm-queue-total-num": "1" + } + }, + "global_cfg": { + "vnic_max_num": "252", + "vnic_queue_num": "2048" + } +} + diff --git a/src/net/build/zxdh_config/smart_nic_init.cfg b/src/net/build/zxdh_config/smart_nic_init.cfg new file mode 100755 index 0000000..576b2a4 --- /dev/null +++ b/src/net/build/zxdh_config/smart_nic_init.cfg @@ -0,0 +1,26 @@ +{ + "vdpa_type": "1", + "vswitch_cfg": { + "bond_info": { + "bus_name": "pci", + "prefix": "", + "linux-device": ["1cf2:8063"], + "dpdk-device": "1cf2:8064" + }, + "vport_info": { + "bus_name": "pci", + "prefix": "", + "max_queue_num":"8" + }, + "upcall-queue": { + "vm-queue-total-num": "1" + }, + "reinject-queue": { + "vm-queue-total-num": "1" + } + }, + "global_cfg": { + "vnic_max_num": "252", + "vnic_queue_num": "2048" + } +} diff --git a/src/net/ci_cmd.sh b/src/net/ci_cmd.sh new file mode 100755 index 0000000..7c926b1 --- /dev/null +++ b/src/net/ci_cmd.sh @@ -0,0 +1,177 @@ +#!/bin/bash + +cmd=$1 + +ver_path=/zte +root_dir=$ver_path/zxdh_kernel + +function get_chg_no(){ + commit_id=$(git log --pretty=format:"%H" | head -n 1) + chg_no=$(git ls-remote | awk '/'${commit_id}'/&&/changes/' | sed 's/\//\n/g' | tail -n 2 | head -1) + echo "${chg_no}" +} + +function get_submit_info(){ + commit_id=$(git log --pretty=format:"%H" | head -n 1) + chg_no=$(git ls-remote | awk '/'${commit_id}'/&&/changes/' | sed 's/\//\n/g' | tail -n 2 | head -1) + title=$(git log --pretty=format:"%s" ${commit_id} -1) + echo "${commit_id} ${chg_no} ${title}" +} + +if [ $cmd = "verifyci" ]; then + param=$2 + if [ $param = "kw" ]; then + exit 0 + elif [ $param = "coverity" ]; then + exit 0 + elif [ $param = "compile" ]; then + build_no=$3 + chg_no=$4 + sh compile.sh verifyci ${build_no} ${chg_no} + result=$? + exit ${result} + elif [ $param = "unittest" ]; then + sh ut.sh + result=$? + exit ${result} + else + echo "unknow cmd" + exit 1 + fi +fi + +if [ $cmd = "gateci" ]; then + param=$2 + if [ $param = "compile" ]; then + build_no=$3 + chg_no=$4 + sh compile.sh gateci ${build_no} ${chg_no} + result=$? + exit ${result} + elif [ $param = "smoke" ]; then + sh smoke.sh gateci + result=$? + exit ${result} + else + echo "unknow cmd" + exit 1 + fi +fi + +if [ $cmd = "postci" ]; then + param=$2 + if [ $param = "compile" ]; then + build_no=$3 + chg_no=$4 + sh compile.sh postci ${build_no} ${chg_no} + result=$? + exit ${result} + elif [ $param = "upload" ]; then + chg_branch=$3 + env_user=$4 + env_pwd=$5 + sh upload.sh postci ${chg_branch} ${env_user} ${env_pwd} + result=$? + exit ${result} + else + echo "unknow cmd" + exit 1 + fi +fi + +if [ $cmd = "versionci" ]; then + param=$2 + cd ${root_dir} + chg_no=`get_chg_no | tail -n 1` + + if [ $param = "kw" ]; then + exit 0 + elif [ $param = "coverity" ]; then + exit 0 + elif [ $param = "smoke" ]; then + sh smoke.sh versionci + elif [ $param = "compile" ]; then + build_no=$3 + sh compile.sh versionci ${build_no} ${chg_no} + result=$? + exit ${result} + elif [ $param = "upload" ]; then + chg_branch=$3 + env_user=$4 + env_pwd=$5 + sh upload.sh versionci ${chg_branch} ${env_user} ${env_pwd} + result=$? + exit ${result} + else + echo "unknow cmd" + exit 1 + fi +fi + +if [ $cmd = "download" ]; then + chg_branch=$2 + env_user=$3 + env_pwd=$4 + + rm -rf ${ver_path}/os + mkdir -p ${ver_path}/os + art_path="https://artsz.zte.com.cn:443/artifactory/dinghai-snapshot-generic/dpu_sdk/os" + last_files=$(curl -k -u ${env_user}:${env_pwd} -X GET ${art_path}/) + for file in ${last_files} + do + if [[ ${file} =~ "href=" ]] + then + file_name=$(echo ${file#*>} | sed -e 's/<\/a>//') + curl -k -u ${env_user}:${env_pwd} -o ${ver_path}/os/${file_name} ${art_path}/${file_name} + unzip -q ${ver_path}/os/${file_name} -d ${ver_path}/os + fi + done + kernel_file1=$(ls ${ver_path}/os | grep "aarch64$") + echo $kernel_file1 + kernel_file2=$(ls ${ver_path}/os | grep "x86_64$") + echo $kernel_file2 + + NXI_NXE_DPU_host_aarch64_file=$(ls ${ver_path}/os | grep "aarch64_${NXI_Host_CGS_kernel_aarch64}$") + echo "NXI_NXE_DPU_host_aarch64_file:"$NXI_NXE_DPU_host_aarch64_file + NXI_NXE_DPU_host_x86_file=$(ls ${ver_path}/os | grep "x86_${NXI_Host_CGS_kernel_X86}$") + echo "NXI_NXE_DPU_host_x86_file:"$NXI_NXE_DPU_host_x86_file + + # if [[ ${NXI_Host_CGS_kernel_aarch64} == ${DPU_Host_CGS_kernel_aarch64} ]] + # then + # echo "The values of NXI_Host_CGS_kernel_aarch64[${NXI_Host_CGS_kernel_aarch64}] and DPU_Host_CGS_kernel_aarch64[${DPU_Host_CGS_kernel_aarch64}] are equal." + # else + # echo "The values of NXI_Host_CGS_kernel_aarch64[${NXI_Host_CGS_kernel_aarch64}] and DPU_Host_CGS_kernel_aarch64[${DPU_Host_CGS_kernel_aarch64}] are not equal." + # DPU_host_aarch64_file=$(ls ${ver_path}/os | grep "aarch64_${DPU_Host_CGS_kernel_aarch64}$") + # echo "DPU_host_aarch64_file:"$DPU_Host_CGS_kernel_aarch64 + # DPU_host_x86_file=$(ls ${ver_path}/os | grep "x86_${DPU_Host_CGS_kernel_X86}$") + # echo "DPU_host_x86_file:"$DPU_Host_CGS_kernel_X86 + # fi + + DPU_zf_aarch64_file=$(ls ${ver_path}/os | grep "aarch64_${DPU_CGS_kernel_aarch64}$") + echo "DPU_zf_aarch64_file:"$DPU_zf_aarch64_file + + rm -rf /lib/modules/${NXI_NXE_DPU_host_aarch64_file} + rm -rf /lib/modules/${NXI_NXE_DPU_host_x86_file} + rm -rf /lib/modules/${DPU_zf_aarch64_file} + # mkdir -p /lib/modules/${kernel_file1} + # mkdir -p /lib/modules/${kernel_file2} + ln -s ${ver_path}/os/${NXI_NXE_DPU_host_aarch64_file} /lib/modules/${NXI_NXE_DPU_host_aarch64_file} + ln -s ${ver_path}/os/${NXI_NXE_DPU_host_x86_file} /lib/modules/${NXI_NXE_DPU_host_x86_file} + ln -s ${ver_path}/os/${DPU_zf_aarch64_file} /lib/modules/${DPU_zf_aarch64_file} + echo "*****************cat os dir*********************" + ls -l ${ver_path}/os + echo "*****************cat kernel dir*****************" + echo $NXI_NXE_DPU_host_aarch64_file + ls -ll /lib/modules/${NXI_NXE_DPU_host_aarch64_file}/ + echo $NXI_NXE_DPU_host_x86_file + ls -ll /lib/modules/${NXI_NXE_DPU_host_x86_file}/ + echo $DPU_zf_aarch64_file + ls -ll /lib/modules/${DPU_zf_aarch64_file}/ + echo "************************************************" + exit 0 +fi + +echo "unknow cmd" +exit 1 + + diff --git a/src/net/README b/src/net/compat/config.h old mode 100644 new mode 100755 similarity index 100% rename from src/net/README rename to src/net/compat/config.h diff --git a/src/net/compile.sh b/src/net/compile.sh new file mode 100755 index 0000000..c249b03 --- /dev/null +++ b/src/net/compile.sh @@ -0,0 +1,278 @@ +#!/bin/bash + +#接收参数 +compile_stage=$1 #四种取值：verifyci、gateci、postci、versionci +build_no=$2 +chg_no=$3 +rpm_ver_no="2.24.20.02" + + +#ver_path不变，各组件只需修改root_dir +ver_path=/zte +root_dir=$ver_path/zxdh_kernel + +if [ "$compile_stage" = "verifyci" ]; then + echo "start compileing kernel for verifyci" + + NXI_NXE_DPU_host_aarch64_file=$(ls /lib/modules/ | grep "aarch64_${NXI_Host_CGS_kernel_aarch64}$") + echo "NXI_NXE_DPU_host_aarch64_file:"$NXI_NXE_DPU_host_aarch64_file + NXI_NXE_DPU_host_x86_file=$(ls /lib/modules/ | grep "x86_${NXI_Host_CGS_kernel_X86}$") + echo "NXI_NXE_DPU_host_x86_file:"$NXI_NXE_DPU_host_x86_file + DPU_zf_aarch64_file=$(ls /lib/modules/ | grep "aarch64_${DPU_CGS_kernel_aarch64}$") + echo "DPU_zf_aarch64_file:"$DPU_zf_aarch64_file + + echo "start check x86 pf driver" + compile_path=${root_dir}/build + rm -f $compile_path/zxdh_kernel_compile.txt $compile_path/zxdh_kernel_compile_fail_result.txt + cd ${compile_path} + ./build.pl -t clean --ksrc /lib/modules/$NXI_NXE_DPU_host_x86_file + ./build.pl -t kernel --ksrc /lib/modules/$NXI_NXE_DPU_host_x86_file -m CONFIG_DINGHAI_ETH -m CONFIG_ZXDH_AUXILIARY -m CONFIG_DINGHAI_PF -m CONFIG_ZXDH_SF -m CONFIG_DINGHAI_EN_AUX -m HAVE_DEVLINK_ALLOC_GET_1_PARAMS -m HAVE_DEV_PM_DOMAIN_ATTACH -m HAVE_BUS_FIND_DEVICE_GET_CONST -m CONFIG_DINGHAI_DH_CMD -m CONFIG_DINGHAI_NP -m CONFIG_ZXDH_MSGQ -m CONFIG_ZXDH_1588 -m CONFIG_DINGHAI_PTP -m CONFIG_DINGHAI_TSN \ + >>$compile_path/zxdh_kernel_compile.txt 2>$compile_path/zxdh_kernel_compile_fail_result.txt + status=$? + echo "***************print x86 en_pf_compile.txt***************" + cat $compile_path/zxdh_kernel_compile.txt + #判断结果 + if [[ $status -ne 0 ]]; then + echo "The build failed. Check $compile_path/kernel_compile_fail_result.txt for details." + cat $compile_path/zxdh_kernel_compile_fail_result.txt + exit $status + fi + echo "x86 pf driver compile success" + + echo "start check x86 hpf driver" + compile_path=${root_dir}/build + rm -f $compile_path/zxdh_kernel_compile.txt $compile_path/zxdh_kernel_compile_fail_result.txt + cd ${compile_path} + ./build.pl -t clean --ksrc /lib/modules/$NXI_NXE_DPU_host_x86_file + ./build.pl -t kernel --ksrc /lib/modules/$NXI_NXE_DPU_host_x86_file -m CONFIG_DINGHAI_ETH -m CONFIG_DINGHAI_HPF -m CONFIG_DINGHAI_DH_CMD -m HAVE_DEVLINK_ALLOC_GET_1_PARAMS \ + >>$compile_path/zxdh_kernel_compile.txt 2>$compile_path/zxdh_kernel_compile_fail_result.txt + status=$? + echo "***************print x86 hpf_compile.txt***************" + cat $compile_path/zxdh_kernel_compile.txt + #判断结果 + if [[ $status -ne 0 ]]; then + echo "The build failed. Check $compile_path/kernel_compile_fail_result.txt for details." + cat $compile_path/zxdh_kernel_compile_fail_result.txt + exit $status + fi + echo "x86 hpf driver compile success" + + echo "start check arm zf_mpf driver" + compile_path=${root_dir}/build + rm -f $compile_path/zxdh_kernel_compile.txt $compile_path/zxdh_kernel_compile_fail_result.txt + cd ${compile_path} + ./build.pl -t clean --ksrc /lib/modules/$DPU_zf_aarch64_file + ./build.pl -t kernel --ksrc /lib/modules/$DPU_zf_aarch64_file \ + --cross_compile /opt/aarch64_cgslv6.01_gcc8.3.1_glibc2.28/bin/aarch64-pc-linux-gnu- \ + --target_arch aarch64 \ + -m CONFIG_DINGHAI_ZF_MPF -m PCIE_ZF_EPC_OPEN -m CONFIG_DINGHAI_ETH -m CONFIG_ZXDH_AUXILIARY -m CONFIG_ZXDH_SF -m HAVE_DEVLINK_ALLOC_GET_1_PARAMS -m HAVE_DEV_PM_DOMAIN_ATTACH -m HAVE_BUS_FIND_DEVICE_GET_CONST -m CONFIG_DINGHAI_DH_CMD -m CONFIG_ZF_GDMA \ + >>$compile_path/zxdh_kernel_compile.txt 2>$compile_path/zxdh_kernel_compile_fail_result.txt + status=$? + echo "***************print arm zf_mpf_compile.txt***************" + cat $compile_path/zxdh_kernel_compile.txt + #判断结果 + if [[ $status -ne 0 ]]; then + echo "The build failed. Check $compile_path/kernel_compile_fail_result.txt for details." + cat $compile_path/zxdh_kernel_compile_fail_result.txt + exit $status + fi + echo "arm zf_mpf driver compile success" + exit 0 + +fi + +if [ $compile_stage = "postci" ]; then + echo "start compileing kernel for postci" + + NXI_NXE_DPU_host_aarch64_file=$(ls /lib/modules/ | grep "aarch64_${NXI_Host_CGS_kernel_aarch64}$") + echo "NXI_NXE_DPU_host_aarch64_file:"$NXI_NXE_DPU_host_aarch64_file + NXI_NXE_DPU_host_x86_file=$(ls /lib/modules/ | grep "x86_${NXI_Host_CGS_kernel_X86}$") + echo "NXI_NXE_DPU_host_x86_file:"$NXI_NXE_DPU_host_x86_file + DPU_zf_aarch64_file=$(ls /lib/modules/ | grep "aarch64_${DPU_CGS_kernel_aarch64}$") + echo "DPU_zf_aarch64_file:"$DPU_zf_aarch64_file + + #打包 + mkdir -p $root_dir/kernel-src + cd $root_dir/kernel-src + rm -f *\.tgz + date=$(date +%Y%m%d%H%M%S) + version=${rpm_ver_no} + dri_version=${rpm_ver_no}-${date} + + pf_tgz_name=$root_dir/kernel-src/zxdh-eth-${version}-${date}.src.tgz + host_hpf_tgz_name=$root_dir/kernel-src/zxdh-neo-host-hpf-${version}-${date}.src.tgz + zf_mpf_tgz_name=$root_dir/kernel-src/zxdh-neo-mpf-${version}-${date}.src.tgz + tar czvf $pf_tgz_name --exclude=$root_dir/kernel-src $root_dir + result=$? + #判断结果 + if [[ $status -ne 0 ]]; then + echo "压缩源码失败." + exit $status + fi + cp $pf_tgz_name $host_hpf_tgz_name + cp $pf_tgz_name $zf_mpf_tgz_name + echo "查看压缩包" + ls + + #开始生成rpm包 + cd $root_dir + rm -f *\.rpm + echo "[NXI/NXE]交叉编译生成host-arm下的rpm包,使用[en_pf]源码" + ./zxdh_eth_rpm_build.sh \ + --ksrc /lib/modules/$NXI_NXE_DPU_host_aarch64_file \ + --cross-compile /opt/aarch64_cgslv6.01_gcc8.3.1_glibc2.28/bin/aarch64-pc-linux-gnu- \ + --target-arch aarch64 \ + --dist .cgsl${NXI_Host_CGS_kernel_aarch64:1} \ + --rpm-driver-version "${version}" --rpm-driver-release "${date}" \ + --rpm-config-version "${version}" --rpm-config-release "${date}" --rpm-config-name zxdh-dpu-config \ + --eth-driver-version "${dri_version}" + + echo "[NXI/NXE]生成host-x86下的rpm包,使用[en_pf]源码" + ./zxdh_eth_rpm_build.sh \ + --ksrc /lib/modules/$NXI_NXE_DPU_host_x86_file \ + --dist .cgsl${NXI_Host_CGS_kernel_X86:1} \ + --rpm-driver-version "${version}" --rpm-driver-release "${date}" \ + --rpm-config-version "${version}" --rpm-config-release "${date}" \ + --eth-driver-version "${dri_version}" + + echo "[DPU]交叉编译生成host-arm下的rpm包,使用[function_hotplug]源码" + ./zxdh_hpf_rpm_build.sh \ + --ksrc /lib/modules/$NXI_NXE_DPU_host_aarch64_file \ + --cross-compile /opt/aarch64_cgslv6.01_gcc8.3.1_glibc2.28/bin/aarch64-pc-linux-gnu- \ + --target-arch aarch64 \ + --dist .cgsl${NXI_Host_CGS_kernel_aarch64:1} \ + --rpm-driver-version "${version}" --rpm-driver-release "${date}" \ + --hpf-driver-version "${dri_version}" + + echo "[DPU]生成host-x86下的rpm包,使用[function_hotplug]源码" + ./zxdh_hpf_rpm_build.sh \ + --ksrc /lib/modules/$NXI_NXE_DPU_host_x86_file \ + --dist .cgsl${NXI_Host_CGS_kernel_X86:1} \ + --rpm-driver-version "${version}" --rpm-driver-release "${date}" \ + --hpf-driver-version "${dri_version}" + + echo "[DPU]交叉编译生成zf-arm下的rpm包,使用[en_pf]源码" + ./zxdh_eth_rpm_build.sh \ + --ksrc /lib/modules/$DPU_zf_aarch64_file \ + --cross-compile /opt/aarch64_cgslv6.01_gcc8.3.1_glibc2.28/bin/aarch64-pc-linux-gnu- \ + --target-arch aarch64 \ + --dist .cgsl${DPU_CGS_kernel_aarch64:1} \ + --rpm-driver-name "zxdh-eth" \ + --rpm-driver-version "${version}" --rpm-driver-release "${date}" \ + --rpm-config-version "${version}" --rpm-config-release "${date}" \ + --eth-driver-version "${dri_version}" + + echo "[DPU]生成zf-arm下的rpm包,使用[zf_mpf]源码" + ./zxdh_zf_mpf_rpm_build.sh \ + --ksrc /lib/modules/$DPU_zf_aarch64_file \ + --cross-compile /opt/aarch64_cgslv6.01_gcc8.3.1_glibc2.28/bin/aarch64-pc-linux-gnu- \ + --dist .cgsl${DPU_CGS_kernel_aarch64:1} \ + --rpm-driver-version "${version}" --rpm-driver-release "${date}" \ + --zf-mpf-driver-version "${dri_version}" + + #TODO + echo "查看全部rpm包" + ls + + exit 0 +fi + +if [ $compile_stage = "versionci" ]; then + echo "start compileing kernel for versionci" + + NXI_NXE_DPU_host_aarch64_file=$(ls /lib/modules/ | grep "aarch64_${NXI_Host_CGS_kernel_aarch64}$") + echo "NXI_NXE_DPU_host_aarch64_file:"$NXI_NXE_DPU_host_aarch64_file + NXI_NXE_DPU_host_x86_file=$(ls /lib/modules/ | grep "x86_${NXI_Host_CGS_kernel_X86}$") + echo "NXI_NXE_DPU_host_x86_file:"$NXI_NXE_DPU_host_x86_file + DPU_zf_aarch64_file=$(ls /lib/modules/ | grep "aarch64_${DPU_CGS_kernel_aarch64}$") + echo "DPU_zf_aarch64_file:"$DPU_zf_aarch64_file + + #打包 + mkdir -p $root_dir/kernel-src + cd $root_dir/kernel-src + rm -f *\.tgz + date=$(date +%Y%m%d%H%M%S) + version=${rpm_ver_no} + dri_version=${rpm_ver_no}-${date} + + pf_tgz_name=$root_dir/kernel-src/zxdh-eth-${version}-${date}-daily.src.tgz + host_hpf_tgz_name=$root_dir/kernel-src/zxdh-neo-host-hpf-${version}-${date}-daily.src.tgz + zf_mpf_tgz_name=$root_dir/kernel-src/zxdh-neo-mpf-${version}-${date}-daily.src.tgz + tar czvf $pf_tgz_name --exclude=$root_dir/kernel-src $root_dir + result=$? + #判断结果 + if [[ $status -ne 0 ]]; then + echo "压缩源码失败." + exit $status + fi + cp $pf_tgz_name $host_hpf_tgz_name + cp $pf_tgz_name $zf_mpf_tgz_name + echo "查看压缩包" + ls + + #开始生成rpm包 + cd $root_dir + rm -f *\.rpm + echo "[NXI/NXE]交叉编译生成host-arm下的rpm包,使用[en_pf]源码" + ./zxdh_eth_rpm_build.sh \ + --ksrc /lib/modules/$NXI_NXE_DPU_host_aarch64_file \ + --cross-compile /opt/aarch64_cgslv6.01_gcc8.3.1_glibc2.28/bin/aarch64-pc-linux-gnu- \ + --target-arch aarch64 \ + --dist .cgsl${NXI_Host_CGS_kernel_aarch64:1} \ + --rpm-driver-version "${version}" --rpm-driver-release "${date}" \ + --rpm-config-version "${version}" --rpm-config-release "${date}" --rpm-config-name zxdh-dpu-config \ + --eth-driver-version "${dri_version}" + + echo "[NXI/NXE]生成host-x86下的rpm包,使用[en_pf]源码" + ./zxdh_eth_rpm_build.sh \ + --ksrc /lib/modules/$NXI_NXE_DPU_host_x86_file \ + --dist .cgsl${NXI_Host_CGS_kernel_X86:1} \ + --rpm-driver-version "${version}" --rpm-driver-release "${date}" \ + --rpm-config-version "${version}" --rpm-config-release "${date}" \ + --eth-driver-version "${dri_version}" + + echo "[DPU]交叉编译生成host-arm下的rpm包,使用[function_hotplug]源码" + ./zxdh_hpf_rpm_build.sh \ + --ksrc /lib/modules/$NXI_NXE_DPU_host_aarch64_file \ + --cross-compile /opt/aarch64_cgslv6.01_gcc8.3.1_glibc2.28/bin/aarch64-pc-linux-gnu- \ + --target-arch aarch64 \ + --dist .cgsl${NXI_Host_CGS_kernel_aarch64:1} \ + --rpm-driver-version "${version}" --rpm-driver-release "${date}" \ + --hpf-driver-version "${dri_version}" + + echo "[DPU]生成host-x86下的rpm包,使用[function_hotplug]源码" + ./zxdh_hpf_rpm_build.sh \ + --ksrc /lib/modules/$NXI_NXE_DPU_host_x86_file \ + --dist .cgsl${NXI_Host_CGS_kernel_X86:1} \ + --rpm-driver-version "${version}" --rpm-driver-release "${date}" \ + --hpf-driver-version "${dri_version}" + + echo "[DPU]交叉编译生成zf-arm下的rpm包,使用[en_pf]源码" + ./zxdh_eth_rpm_build.sh \ + --ksrc /lib/modules/$DPU_zf_aarch64_file \ + --cross-compile /opt/aarch64_cgslv6.01_gcc8.3.1_glibc2.28/bin/aarch64-pc-linux-gnu- \ + --target-arch aarch64 \ + --dist .cgsl${DPU_CGS_kernel_aarch64:1} \ + --rpm-driver-name "zxdh-eth" \ + --rpm-driver-version "${version}" --rpm-driver-release "${date}" \ + --rpm-config-version "${version}" --rpm-config-release "${date}" \ + --eth-driver-version "${dri_version}" + + echo "[DPU]生成zf-arm下的rpm包,使用[zf_mpf]源码" + ./zxdh_zf_mpf_rpm_build.sh \ + --ksrc /lib/modules/$DPU_zf_aarch64_file \ + --cross-compile /opt/aarch64_cgslv6.01_gcc8.3.1_glibc2.28/bin/aarch64-pc-linux-gnu- \ + --dist .cgsl${DPU_CGS_kernel_aarch64:1} \ + --rpm-driver-version "${version}" --rpm-driver-release "${date}" \ + --zf-mpf-driver-version "${dri_version}" + + #TODO + echo "查看全部rpm包" + ls + exit 0 +fi + +if [ $compile_stage = "gateci" ]; then + echo "gateci compile success" + exit 0 +fi diff --git a/src/net/drivers/base/Makefile b/src/net/drivers/base/Makefile new file mode 100755 index 0000000..4f40a2e --- /dev/null +++ b/src/net/drivers/base/Makefile @@ -0,0 +1,6 @@ +subdir-ccflags-y += -I$(CWD)/include +subdir-ccflags-y += -include $(CWD)/autoconf.h +ccflags-y += -Werror + +obj-m += zxdh_auxiliary.o +zxdh_auxiliary-y += en_auxiliary.o \ No newline at end of file diff --git a/src/net/drivers/base/en_auxiliary.c b/src/net/drivers/base/en_auxiliary.c new file mode 100644 index 0000000..fb7232b --- /dev/null +++ b/src/net/drivers/base/en_auxiliary.c @@ -0,0 +1,368 @@ + +#ifdef pr_fmt +#undef pr_fmt +#endif + +#define pr_fmt(fmt) "%s:%s: " fmt, KBUILD_MODNAME, __func__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_COMPAT_AUXILIARY_EXTERNAL_INIT +#include "base.h" +#endif + + +static const struct zxdh_auxiliary_device_id *zxdh_auxiliary_match_id(const struct zxdh_auxiliary_device_id *id, + const struct zxdh_auxiliary_device *auxdev) +{ + for (; id->name[0]; id++) + { + const char *p = strrchr(dev_name(&auxdev->dev), '.'); + int32_t match_size; + + if (!p) + { + continue; + } + match_size = p - dev_name(&auxdev->dev); + + /* use dev_name(&auxdev->dev) prefix before last '.' char to match to */ + if (strlen(id->name) == match_size && + !strncmp(dev_name(&auxdev->dev), id->name, match_size)) + { + return id; + } + } + + return NULL; +} + +static int32_t zxdh_auxiliary_match(struct device *dev, struct device_driver *drv) +{ + struct zxdh_auxiliary_device *auxdev = zxdh_to_auxiliary_dev(dev); + struct zxdh_auxiliary_driver *auxdrv = zxdh_to_auxiliary_drv(drv); + + return !!zxdh_auxiliary_match_id(auxdrv->id_table, auxdev); +} + +static int32_t zxdh_auxiliary_uevent(struct device *dev, struct kobj_uevent_env *env) +{ + const char *name; + const char *p; + + name = dev_name(dev); + p = strrchr(name, '.'); + + return add_uevent_var(env, "MODALIAS=%s%.*s", ZXDH_AUXILIARY_MODULE_PREFIX, (int32_t)(p - name), name); +} + +static const struct dev_pm_ops zxdh_auxiliary_dev_pm_ops = { + SET_RUNTIME_PM_OPS(pm_generic_runtime_suspend, pm_generic_runtime_resume, NULL) + SET_SYSTEM_SLEEP_PM_OPS(pm_generic_suspend, pm_generic_resume) +}; + +static int32_t zxdh_auxiliary_bus_probe(struct device *dev) +{ + struct zxdh_auxiliary_driver *auxdrv = zxdh_to_auxiliary_drv(dev->driver); + struct zxdh_auxiliary_device *auxdev = zxdh_to_auxiliary_dev(dev); + int32_t ret = 0; + +#ifdef HAVE_DEV_PM_DOMAIN_ATTACH + ret = dev_pm_domain_attach(dev, true); + + /* In case of old kernels 4.17 and below do nothing in case of + * failure of ENODEV */ + if (ret == -ENODEV) + { + ret = 0; + } + + if (ret != 0) + { + LOG_WARN("Failed to attach to PM Domain : %d\n", ret); + return ret; + } +#else + acpi_dev_pm_attach(dev, true); +#endif + + ret = auxdrv->probe(auxdev, zxdh_auxiliary_match_id(auxdrv->id_table, auxdev)); + if (ret != 0) +#ifdef HAVE_DEV_PM_DOMAIN_ATTACH + dev_pm_domain_detach(dev, true); +#else + acpi_dev_pm_detach(dev, true); +#endif + + return ret; +} + +#ifdef HAVE_BUS_TYPE_REMOVE_RETURN_VOID +static void zxdh_auxiliary_bus_remove(struct device *dev) +#else +static int32_t zxdh_auxiliary_bus_remove(struct device *dev) +#endif +{ + struct zxdh_auxiliary_driver *auxdrv = zxdh_to_auxiliary_drv(dev->driver); + struct zxdh_auxiliary_device *auxdev = zxdh_to_auxiliary_dev(dev); + + if (auxdrv->remove) + { + auxdrv->remove(auxdev); + } +#ifdef HAVE_DEV_PM_DOMAIN_ATTACH + dev_pm_domain_detach(dev, true); +#else + acpi_dev_pm_detach(dev, true); +#endif + +#ifndef HAVE_BUS_TYPE_REMOVE_RETURN_VOID + return 0; +#endif +} + +static void zxdh_auxiliary_bus_shutdown(struct device *dev) +{ + struct zxdh_auxiliary_driver *auxdrv = NULL; + struct zxdh_auxiliary_device *auxdev = NULL; + + if (dev->driver) + { + auxdrv = zxdh_to_auxiliary_drv(dev->driver); + auxdev = zxdh_to_auxiliary_dev(dev); + } + + if (auxdrv && auxdrv->shutdown) + { + auxdrv->shutdown(auxdev); + } +} + +static struct bus_type zxdh_auxiliary_bus_type = { + .name = "zxdh_auxiliary", + .probe = zxdh_auxiliary_bus_probe, + .remove = zxdh_auxiliary_bus_remove, + .shutdown = zxdh_auxiliary_bus_shutdown, + .match = zxdh_auxiliary_match, + .uevent = zxdh_auxiliary_uevent, + .pm = &zxdh_auxiliary_dev_pm_ops, +}; + +/** + * zxdh_auxiliary_device_init - check zxdh_auxiliary_device and initialize + * @auxdev: auxiliary device struct + * + * This is the second step in the three-step process to register an + * zxdh_auxiliary_device. + * + * When this function returns an error code, then the device_initialize will + * *not* have been performed, and the caller will be responsible to free any + * memory allocated for the zxdh_auxiliary_device in the error path directly. + * + * It returns 0 on success. On success, the device_initialize has been + * performed. After this point any error unwinding will need to include a call + * to zxdh_auxiliary_device_uninit(). In this post-initialize error scenario, a call + * to the device's .release callback will be triggered, and all memory clean-up + * is expected to be handled there. + */ +int32_t zxdh_auxiliary_device_init(struct zxdh_auxiliary_device *auxdev) +{ + struct device *dev = &auxdev->dev; + + if (!dev->parent) + { + LOG_ERR("zxdh_auxiliary_device has a NULL dev->parent\n"); + return -EINVAL; + } + + if (!auxdev->name) + { + LOG_ERR("zxdh_auxiliary_device has a NULL name\n"); + return -EINVAL; + } + + dev->bus = &zxdh_auxiliary_bus_type; + device_initialize(&auxdev->dev); + + return 0; +} +EXPORT_SYMBOL_GPL(zxdh_auxiliary_device_init); + +/** + * zxdh_aux_dev_add - add an auxiliary bus device + * @auxdev: auxiliary bus device to add to the bus + * @modname: name of the parent device's driver module + * + * This is the third step in the three-step process to register an + * zxdh_auxiliary_device. + * + * This function must be called after a successful call to + * zxdh_auxiliary_device_init(), which will perform the device_initialize. This + * means that if this returns an error code, then a call to + * zxdh_auxiliary_device_uninit() must be performed so that the .release callback + * will be triggered to free the memory associated with the zxdh_auxiliary_device. + * + * The expectation is that users will call the "zxdh_auxiliary_device_add" macro so + * that the caller's KBUILD_MODNAME is automatically inserted for the modname + * parameter. Only if a user requires a custom name would this version be + * called directly. + */ +int32_t zxdh_aux_dev_add(struct zxdh_auxiliary_device *auxdev, const char *modname) +{ + struct device *dev = &auxdev->dev; + int32_t ret = 0; + + if (!modname) + { + LOG_ERR( "zxdh auxiliary device modname is NULL\n"); + return -EINVAL; + } + + ret = dev_set_name(dev, "%s.%s.%d", modname, auxdev->name, auxdev->id); + if (ret != 0) + { + LOG_ERR( "zxdh auxiliary device dev_set_name failed: %d\n", ret); + return ret; + } + + ret = device_add(dev); + if (ret != 0) + { + LOG_ERR( "adding zxdh auxiliary device failed!: %d\n", ret); + } + + return ret; +} +EXPORT_SYMBOL_GPL(zxdh_aux_dev_add); + +/** + * zxdh_auxiliary_find_device - auxiliary device iterator for locating a particular device. + * @start: Device to begin with + * @data: Data to pass to match function + * @match: Callback function to check device + * + * This function returns a reference to a device that is 'found' + * for later use, as determined by the @match callback. + * + * The reference returned should be released with put_device(). + * + * The callback should return 0 if the device doesn't match and non-zero + * if it does. If the callback returns non-zero, this function will + * return to the caller and not iterate over any more devices. + */ +#if defined(HAVE_LINUX_DEVICE_BUS_H) || defined(HAVE_BUS_FIND_DEVICE_GET_CONST) +struct zxdh_auxiliary_device * +zxdh_auxiliary_find_device(struct device *start, + const void *data, + int32_t (*match)(struct device *dev, const void *data)) +#else +struct zxdh_auxiliary_device * +zxdh_auxiliary_find_device(struct device *start, + void *data, + int32_t (*match)(struct device *dev, void *data)) +#endif /* HAVE_BUS_FIND_DEVICE_GET_CONST || HAVE_LINUX_DEVICE_BUS_H */ +{ + struct device *dev = NULL; + + dev = bus_find_device(&zxdh_auxiliary_bus_type, start, data, match); + if (dev == NULL) + { + return NULL; + } + + return zxdh_to_auxiliary_dev(dev); +} +EXPORT_SYMBOL_GPL(zxdh_auxiliary_find_device); + +/** + * zxdh_aux_drv_register - register a driver for auxiliary bus devices + * @auxdrv: zxdh_auxiliary_driver structure + * @owner: owning module/driver + * @modname: KBUILD_MODNAME for parent driver + * + * The expectation is that users will call the "zxdh_auxiliary_driver_register" + * macro so that the caller's KBUILD_MODNAME is automatically inserted for the + * modname parameter. Only if a user requires a custom name would this version + * be called directly. + */ +int32_t zxdh_aux_drv_register(struct zxdh_auxiliary_driver *auxdrv, + struct module *owner, const char *modname) +{ + int32_t ret = 0; + + if (WARN_ON(!auxdrv->probe) || WARN_ON(!auxdrv->id_table)) + { + return -EINVAL; + } + + if (auxdrv->name) + { + auxdrv->driver.name = kasprintf(GFP_KERNEL, "%s.%s", modname, auxdrv->name); + } + else + { + auxdrv->driver.name = kasprintf(GFP_KERNEL, "%s", modname); + } + if (!auxdrv->driver.name) + { + return -ENOMEM; + } + + auxdrv->driver.owner = owner; + auxdrv->driver.bus = &zxdh_auxiliary_bus_type; + auxdrv->driver.mod_name = modname; + + ret = driver_register(&auxdrv->driver); + if (ret) + { + kfree(auxdrv->driver.name); + } + + return ret; +} +EXPORT_SYMBOL_GPL(zxdh_aux_drv_register); + +/** + * zxdh_auxiliary_driver_unregister - unregister a driver + * @auxdrv: zxdh_auxiliary_driver structure + */ +void zxdh_auxiliary_driver_unregister(struct zxdh_auxiliary_driver *auxdrv) +{ + driver_unregister(&auxdrv->driver); + kfree(auxdrv->driver.name); +} +EXPORT_SYMBOL_GPL(zxdh_auxiliary_driver_unregister); + +#ifdef CONFIG_COMPAT_AUXILIARY_EXTERNAL_INIT +void __init zxdh_auxiliary_bus_init(void) +{ + WARN_ON(bus_register(&zxdh_auxiliary_bus_type)); +} +#else +static int32_t __init zxdh_auxiliary_bus_init(void) +{ + return bus_register(&zxdh_auxiliary_bus_type); +} + +static void __exit zxdh_auxiliary_bus_exit(void) +{ + bus_unregister(&zxdh_auxiliary_bus_type); +} + +module_init(zxdh_auxiliary_bus_init); +module_exit(zxdh_auxiliary_bus_exit); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("Auxiliary Bus"); +MODULE_INFO(supported, "external"); +MODULE_AUTHOR("David Ertman "); +MODULE_AUTHOR("Kiran Patil "); +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/Kconfig b/src/net/drivers/net/ethernet/dinghai/Kconfig new file mode 100755 index 0000000..101de52 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/Kconfig @@ -0,0 +1,6 @@ +config DINGHAI_MPF + depends on PCI + select AUXILIARY_BUS + select NET_DEVLINK + help + DingHai Eth \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/Makefile b/src/net/drivers/net/ethernet/dinghai/Makefile new file mode 100755 index 0000000..2f40270 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/Makefile @@ -0,0 +1,71 @@ +subdir-ccflags-y += -I$(src) +subdir-ccflags-y += -I$(CWD)/include/ +subdir-ccflags-y += -include $(CWD)/autoconf.h +ccflags-y += -Werror + + +ifeq ($(CONFIG_ZXDH_MSGQ),m) +EXTRA_CFLAGS += -DZXDH_MSGQ +endif + +ifeq ($(CONFIG_DINGHAI_SEC),m) +EXTRA_CFLAGS += -DZXDH_SEC +endif + +ifeq ($(CONFIG_DRIVER_VERSION),) +EXTRA_CFLAGS += -DDRIVER_VERSION_VAL=\"1.0-1\" +$(info CONFIG_PF_MPF_DRIVER_VERSION is null, EXTRA_CFLAGS=$(EXTRA_CFLAGS)) +else +EXTRA_CFLAGS += -DDRIVER_VERSION_VAL=\"$(CONFIG_DRIVER_VERSION)\" +$(info CONFIG_PF_MPF_DRIVER_VERSION is not null, EXTRA_CFLAGS=$(EXTRA_CFLAGS)) +endif + +obj-$(CONFIG_DINGHAI_DH_CMD) += zxdh_cmd.o +zxdh_cmd-y := dh_cmd.o cmd/msg_main.o cmd/msg_chan_lock.o cmd/msg_chan_test.o + +obj-$(CONFIG_DINGHAI_MPF) += zxdh_mpf.o +zxdh_mpf-y := events.o eq.o en_mpf.o pci_irq.o en_mpf/irq.o en_mpf/events.o en_mpf/eq.o devlink.o \ + en_mpf/devlink.o en_mpf/cfg_sf.o +zxdh_mpf-$(CONFIG_ZXDH_SF) += irq_affinity.o en_sf.o en_sf/eq.o en_sf/irq.o en_sf/devlink.o + +obj-$(CONFIG_DINGHAI_ZF_MPF) += zxdh_zf_mpf.o + +ifdef PCIE_ZF_EPC_OPEN +zxdh_zf_mpf-y := events.o eq.o pci_irq.o devlink.o \ + zf_mpf/zf_mpf.o zf_mpf/zf_events.o zf_mpf/irq.o zf_mpf/eq.o zf_mpf/devlink.o zf_mpf/cfg_sf.o \ + zf_mpf/epc/pcie-zte-zf-epc.o zf_mpf/epc/pcie-zte-zf-hdma.o zf_mpf/epc/virt-dma.o zf_mpf/zxdh_reset_zf.o \ + zf_mpf/fuc_hotplug/fuc_hotplug_ioctl.o zf_mpf/fuc_hotplug/fuc_hotplug.o zf_mpf/zf_reset_finish_flag.o zf_mpf/zf_chan_ioctl.o +obj-m += zxdh_zf_epf.o +my_api-objs := zf_mpf/epc/pcie-zte-zf-epc.o +zxdh_zf_epf-y := zf_mpf/epf/pcie-zte-zf-epf.o +else +zxdh_zf_mpf-y := events.o eq.o pci_irq.o devlink.o \ + zf_mpf/zf_mpf.o zf_mpf/zf_events.o zf_mpf/irq.o zf_mpf/eq.o zf_mpf/devlink.o zf_mpf/cfg_sf.o zf_mpf/zxdh_reset_zf.o \ + zf_mpf/fuc_hotplug/fuc_hotplug_ioctl.o zf_mpf/fuc_hotplug/fuc_hotplug.o zf_mpf/zf_reset_finish_flag.o zf_mpf/zf_chan_ioctl.o +endif +zxdh_zf_mpf-$(CONFIG_ZXDH_SF) += irq_affinity.o en_sf.o en_sf/eq.o en_sf/irq.o en_sf/devlink.o +zxdh_zf_mpf-$(CONFIG_ZF_GDMA) += zf_mpf/gdma.o + +obj-$(CONFIG_DINGHAI_PF) += zxdh_pf.o +zxdh_pf-y := events.o en_pf.o eq.o pci_irq.o en_pf/irq.o en_pf/eq.o devlink.o en_pf/devlink.o en_pf/events.o \ + en_pf/msg_func.o dh_procfs.o lag/lag.o lag/lag_procfs.o plcr.o sriov_sysfs.o + +zxdh_pf-$(CONFIG_ZXDH_SF) += irq_affinity.o en_sf.o en_sf/eq.o en_sf/irq.o en_sf/devlink.o + +obj-$(CONFIG_DINGHAI_EN_AUX) += zxdh_en_aux.o +zxdh_en_aux-y := en_aux.o eq.o pci_irq.o irq_affinity.o en_aux/queue.o en_aux/en_cmd.o en_aux/eq.o \ + en_aux/events.o en_ethtool/ethtool.o en_aux/en_ioctl.o \ + en_aux/dcbnl/en_dcbnl.o en_aux/dcbnl/en_dcbnl_api.o \ + zxdh_tools/zxdh_tools_ioctl.o zxdh_tools/zxdh_tools_netlink.o +zxdh_en_aux-$(CONFIG_ZXDH_1588) += en_aux/en_1588_pkt_proc.o en_aux/en_1588_pkt_proc_func.o +zxdh_en_aux-$(CONFIG_DINGHAI_SEC) += en_aux/drs_sec_dtb.o +zxdh_en_aux-$(CONFIG_ZXDH_MSGQ) += en_aux/priv_queue.o + +obj-$(CONFIG_DINGHAI_PTP) += zxdh_ptp.o +zxdh_ptp-y :=en_ptp/tod_driver.o en_ptp/tod_driver_stub.o en_ptp/zxdh_ptp.o + +obj-$(CONFIG_DINGHAI_TSN) += zxdh_tsn.o +zxdh_tsn-y :=en_tsn/zxdh_tsn.o en_tsn/zxdh_tsn_reg.o en_tsn/zxdh_tsn_ioctl.o + +include $(CWD)/drivers/net/ethernet/dinghai/en_np/Makefile + diff --git a/src/net/drivers/net/ethernet/dinghai/cmd.c b/src/net/drivers/net/ethernet/dinghai/cmd.c new file mode 100755 index 0000000..a8e46fc --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/cmd.c @@ -0,0 +1,35 @@ +#include +#include +#include +#include + +static int32_t cmd_status_err(struct dh_core_dev *dev, int32_t err, uint16_t opcode, void *out) +{ + u8 status = DH_GET(mbox_out, out, status); + + return err; +} +static int32_t cmd_exec(struct dh_core_dev *dev, void *in, int32_t in_size, void *out, + int32_t out_size, zxdh_cmd_cbk_t callback, void *context, + bool force_polling) +{ + return 0; +} + +int32_t zxdh_cmd_do(struct dh_core_dev *dev, void *in, int32_t in_size, void *out, int32_t out_size) +{ + int32_t err = cmd_exec(dev, in, in_size, out, out_size, NULL, NULL, false); + uint16_t opcode = DH_GET(mbox_in, in, opcode); + + err = cmd_status_err(dev, err, opcode, out); + + return err; +} +EXPORT_SYMBOL(zxdh_cmd_do); + +int32_t zxdh_cmd_exec(struct dh_core_dev *dev, void *in, int32_t in_size, void *out, int32_t out_size) +{ + int32_t err = zxdh_cmd_do(dev, in, in_size, out, out_size); + + return zxdh_cmd_check(dev, err, in, out); +} \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/cmd/msg_chan_lock.c b/src/net/drivers/net/ethernet/dinghai/cmd/msg_chan_lock.c new file mode 100644 index 0000000..daf77d4 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/cmd/msg_chan_lock.c @@ -0,0 +1,179 @@ +#include +#include "msg_chan_lock.h" +#include "msg_chan_priv.h" +/***************************************** +[src/dst]时应该将消息发到硬件锁还是软件所 +src/dst: TO_RISC, TO_PFVF, TO_MPF +MPF: 1 1 1 +PF: 0 0 1 +VF: 0 0 1 +******************************************/ + +/*/PF0-7 DIRECT_CHNA/(PF0)VF0-VF32/(PF1)VF0-VF32/...*/ +struct mutex lock_array[LOCK_ARR_LENGTH] = {0}; + +uint8_t lock_type_tbl[BAR_MSG_SRC_NUM][BAR_MSG_DST_NUM] = +{ + {LOCK_TYPE_HARD, LOCK_TYPE_HARD, LOCK_TYPE_HARD}, + {LOCK_TYPE_SOFT, LOCK_TYPE_SOFT, LOCK_TYPE_HARD}, + {LOCK_TYPE_HARD, LOCK_TYPE_HARD, LOCK_TYPE_HARD} +}; + +/** + * pcieid_to_lockid - 将pcie_id转化成lock_id + * @src_pcieid: pcie_id + * @result: 软件数组的索引值 + */ +uint16_t pcieid_to_lockid(uint16_t src_pcieid, uint8_t dst) +{ + uint16_t lock_id = 0; + uint16_t pf_idx = 0; + uint16_t vf_idx = 0; + uint16_t ep_idx = 0; + + pf_idx = (src_pcieid & PCIEID_PF_IDX_MASK) >> PCIEID_PF_IDX_OFFSET; + vf_idx = (src_pcieid & PCIEID_VF_IDX_MASK); + ep_idx = (src_pcieid & PCIEID_EP_IDX_MASK) >> PCIEID_EP_IDX_OFFSET ; + switch (dst) + { + case MSG_CHAN_END_RISC: + { + if (src_pcieid & PCIEID_IS_PF_MASK) + { + lock_id = MULTIPLY_BY_8(ep_idx) + pf_idx; + } + else + { + lock_id = MULTIPLY_BY_256(ep_idx) + MULTIPLY_BY_32(pf_idx) + vf_idx + MULTIPLY_BY_32(1); + } + break; + } + case MSG_CHAN_END_VF: + { + lock_id = MULTIPLY_BY_8(ep_idx) + pf_idx + MULTIPLY_BY_32(1 + VF_NUM_PER_PF); + break; + } + case MSG_CHAN_END_PF: + { + lock_id = MULTIPLY_BY_8(ep_idx) + pf_idx + MULTIPLY_BY_32(2 + VF_NUM_PER_PF); + break; + } + default: + { + lock_id = 0; + break; + } + } + + if (lock_id >= LOCK_ARR_LENGTH) + { + lock_id = 0; + } + + return lock_id; +} + +void bar_soft_lock(uint16_t src_pcieid, uint8_t dst) +{ + uint16_t lockid = 0; + + lockid = pcieid_to_lockid(src_pcieid, dst); + mutex_lock(&lock_array[lockid]); +} + +void bar_soft_unlock(uint16_t src_pcieid, uint8_t dst) +{ + uint16_t lockid = 0; + + lockid = pcieid_to_lockid(src_pcieid, dst); + mutex_unlock(&lock_array[lockid]); +} + +void bar_hard_lock(void) +{ + return; +} + +void bar_hard_unlock(void) +{ + return; +} + +/** + * bar_init_lock_arr - 初始化软件锁数组 + * 在msg_chan模块初始化函数中调用软件锁初始化 + */ +void bar_init_lock_arr(void) +{ + int idx = 0; + + for (idx = 0; idx < ARR_LEN(lock_array); idx++) + { + mutex_init(&lock_array[idx]); + } +} + +/** + * bar_chan_lock - 通道上锁 + * @src: 消息源类型 + * @dst: 消息对端类型 + * @src_pcieid: 源pcieId + * @return: 0成功， 1失败 + */ +int bar_chan_lock(uint8_t src, uint8_t dst, uint16_t src_pcieid) +{ + uint16_t idx = 0; + uint8_t src_index = 0; + uint8_t dst_index = 0; + + src_index = bar_msg_row_index_trans(src); + dst_index = bar_msg_col_index_trans(dst); + if (src_index == BAR_MSG_SRC_ERR || dst_index == BAR_MSG_DST_ERR) + { + BAR_LOG_ERR("lock ERR: chan doesn't exist.\n"); + return BAR_MSG_ERR_TYPE; + } + idx = lock_type_tbl[src_index][dst_index]; + if (idx == LOCK_TYPE_SOFT) + { + bar_soft_lock(src_pcieid, dst); + } + else + { + bar_hard_lock(); + BAR_LOG_INFO("hard_lock.\n"); + } + return BAR_MSG_OK; +} + +/** + * bar_chan_lock - 通道解锁功能 + * @src: 消息源类型 + * @dst: 消息对端类型 + * @src_pcieid: 源pcieId + * @return: 0成功1失败 + */ +int bar_chan_unlock(uint8_t src, uint8_t dst, uint16_t src_pcieid) +{ + uint16_t idx = 0; + uint8_t src_index = 0; + uint8_t dst_index = 0; + + src_index = bar_msg_row_index_trans(src); + dst_index = bar_msg_col_index_trans(dst); + if (src_index == BAR_MSG_SRC_ERR || dst_index == BAR_MSG_DST_ERR) + { + BAR_LOG_ERR("unlock ERR: chan doesn't exist.\n"); + return BAR_MSG_ERR_TYPE; + } + idx = lock_type_tbl[src_index][dst_index]; + if (idx == LOCK_TYPE_SOFT) + { + bar_soft_unlock(src_pcieid, dst); + } + else + { + bar_hard_unlock(); + } + return BAR_MSG_OK; +} \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/cmd/msg_chan_lock.h b/src/net/drivers/net/ethernet/dinghai/cmd/msg_chan_lock.h new file mode 100644 index 0000000..beea9b0 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/cmd/msg_chan_lock.h @@ -0,0 +1,48 @@ +#ifndef _ZXDH_MSG_CHAN_LOCK_H_ +#define _ZXDH_MSG_CHAN_LOCK_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define ARR_LEN(arr) (sizeof(arr)/sizeof(arr[0])) + +/* PCIEID位域掩码*/ +#define PCIEID_IS_PF_MASK (0x0800) +#define PCIEID_PF_IDX_MASK (0x0700) +#define PCIEID_VF_IDX_MASK (0x00ff) +#define PCIEID_EP_IDX_MASK (0x7000) +#define PF0_PCIEID (0x0800) + +/* PCIEID位域偏移*/ +#define PCIEID_PF_IDX_OFFSET (8) +#define PCIEID_EP_IDX_OFFSET (12) + + + + +/* 硬件锁软件锁*/ +#define LOCK_TYPE_HARD 0 +#define LOCK_TYPE_SOFT 0 + +#define MAX_EP_NUM 4 +#define PF_NUM_PER_EP 8 +#define VF_NUM_PER_PF 32 + +#define MULTIPLY_BY_8(x) ((x) << 3) +#define MULTIPLY_BY_32(x) ((x) << 5) +#define MULTIPLY_BY_256(x) ((x) << 8) + +#define LOCK_ARR_LENGTH (MAX_EP_NUM * PF_NUM_PER_EP * (3 + VF_NUM_PER_PF)) + +void bar_init_lock_arr(void); + +int bar_chan_lock(uint8_t src, uint8_t dst, uint16_t src_pcieid); + +int bar_chan_unlock(uint8_t src, uint8_t dst, uint16_t src_pcieid); + +#ifdef __cplusplus +} +#endif + +#endif /* _ZXDH_MSG_CHAN_LOCK_H_ */ diff --git a/src/net/drivers/net/ethernet/dinghai/cmd/msg_chan_priv.h b/src/net/drivers/net/ethernet/dinghai/cmd/msg_chan_priv.h new file mode 100644 index 0000000..1533ef5 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/cmd/msg_chan_priv.h @@ -0,0 +1,294 @@ +#ifndef _ZXDH_MSG_CHAN_PRIV_H_ +#define _ZXDH_MSG_CHAN_PRIV_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include +#include +#include +/* */ +#define BAR_KFREE_PTR(ptr) { \ + if (ptr != NULL) \ + { \ + kfree(ptr); \ + } \ + ptr = NULL; \ +} + +#define BAR_LOG_ERR(fmt, arg...) DH_LOG_ERR(MODULE_CMD, fmt, ##arg); +#define BAR_LOG_INFO(fmt, arg...) DH_LOG_INFO(MODULE_CMD, fmt, ##arg); +#define BAR_LOG_DEBUG(fmt, arg...) DH_LOG_DEBUG(MODULE_CMD, fmt, ##arg); +#define BAR_LOG_WARN(fmt, arg...) DH_LOG_WARNING(MODULE_CMD, fmt, ##arg); + +#define HOST_OR_ZX 0 + +#define MAX_MSG_BUFF_NUM 0xffff + +#define BAR_ALIGN_WORD_MASK 0xffffffc +#define BAR_MSG_ADDR_CHAN_INTERVAL (1024*2) + +/* 消息类型*/ +#define BAR_CHAN_MSG_SYNC 0 +#define BAR_CHAN_MSG_ASYNC 1 +#define BAR_CHAN_MSG_NO_EMEC 0 +#define BAR_CHAN_MSG_EMEC 1 +#define BAR_CHAN_MSG_NO_ACK 0 +#define BAR_CHAN_MSG_ACK 1 + +/* payload, valid和内容的偏移*/ +#define BAR_MSG_PLAYLOAD_OFFSET (sizeof(struct bar_msg_header)) +#define BAR_MSG_LEN_OFFSET 2 +#define BAR_MSG_VALID_OFFSET 0 + +/* valid字段的掩码*/ +#define BAR_MSG_VALID_MASK 1 + +/* reps_buff的偏移*/ +#define REPS_HEADER_VALID_OFFSET 0 +#define REPS_HEADER_LEN_OFFSET 1 +#define REPS_HEADER_PAYLOAD_OFFSET 4 + +#define REPS_HEADER_REPLYED 0xff + +/* 通道状态*/ +#define BAR_MSG_CHAN_USABLE 0 +#define BAR_MSG_CHAN_USED 1 + +/* 超时时间 = 100 us *30000次轮询 = 3s*/ +#define BAR_MSG_POLLING_SPAN_US 100 +#define BAR_MSG_TIMEOUT_TH 30000 + +/* vf,pf,mpf总数*/ +#define BAR_DRIVER_TOTAL_NUM (BAR_MPF_NUM + BAR_PF_NUM + BAR_VF_NUM) + +/* bar的通道偏移*/ +#define BAR_INDEX_TO_RISC 0 +#define BAR_MPF_NUM 1 + +/* 定时器周期宏*/ +#define BAR_MSGID_FREE_THRESHOLD (jiffies + msecs_to_jiffies(2000)) + +/* 管理pf信息*/ +#define BAR_MSG_OFFSET (0x2000) +#define MPF_VENDOR_ID (0x16c3) +#define MPF_DEVICE_ID (0x8045) + +enum { + TYPE_SEND_NP = 0x0, + TYPE_SEND_DRS = 0x01, + TYPE_SEND_DTP = 0x10, + TYPE_END, +}; + +/************************************************************************** + * common.ko会工作在5中场景，不同场景每个mpf/pf/vf可以看到的bar不一样 + * 1、DPU场景下的host中：SCENE_HOST_IN_DPU + * 2、DPU场景下的ZF中： SCENE_ZF_IN_DPU + * 3、智能网卡带ddr: SCENE_NIC_WITH_DDR + * 4、智能网卡不带ddr: SCENE_NIC_NO_DDR + * 5、普卡： SCENE_STD_NIC +**************************************************************************/ +#define SCENE_TEST + +#ifdef SCENE_HOST_IN_DPU +#define BAR_PF_NUM 31 +#define BAR_VF_NUM 1024 +#define BAR_INDEX_PF_TO_VF 1 +#define BAR_INDEX_MPF_TO_MPF 1 +#define BAR_INDEX_MPF_TO_PFVF 0xff +#define BAR_INDEX_PFVF_TO_MPF 0xff +#endif + +#ifdef SCENE_ZF_IN_DPU +#define BAR_PF_NUM 7 +#define BAR_VF_NUM 128 +#define BAR_INDEX_PF_TO_VF 0xff +#define BAR_INDEX_MPF_TO_MPF 1 +#define BAR_INDEX_MPF_TO_PFVF 0xff +#define BAR_INDEX_PFVF_TO_MPF 0xff +#endif + +#ifdef SCENE_NIC_WITH_DDR +#define BAR_PF_NUM 31 +#define BAR_VF_NUM 1024 +#define BAR_INDEX_PF_TO_VF 1 +#define BAR_INDEX_MPF_TO_MPF 0xff +#define BAR_INDEX_MPF_TO_PFVF 0xff +#define BAR_INDEX_PFVF_TO_MPF 0xff +#endif + +#ifdef SCENE_NIC_NO_DDR +#define BAR_PF_NUM 31 +#define BAR_VF_NUM 1024 +#define BAR_INDEX_PF_TO_VF 1 +#define BAR_INDEX_MPF_TO_MPF 0xff +#define BAR_INDEX_MPF_TO_PFVF 1 +#define BAR_INDEX_PFVF_TO_MPF 2 +#endif + +#ifdef SCENE_STD_NIC +#define BAR_PF_NUM 7 +#define BAR_VF_NUM 256 +#define BAR_INDEX_PF_TO_VF 1 +#define BAR_INDEX_MPF_TO_MPF 0xff +#define BAR_INDEX_MPF_TO_PFVF 1 +#define BAR_INDEX_PFVF_TO_MPF 2 +#endif + +#ifdef SCENE_TEST +#define BAR_PF_NUM 7 +#define BAR_VF_NUM 256 +#define BAR_INDEX_PF_TO_VF 0 +#define BAR_INDEX_MPF_TO_MPF 0xff +#define BAR_INDEX_MPF_TO_PFVF 0 +#define BAR_INDEX_PFVF_TO_MPF 0 +#endif + +/* 左边通道还是右边通道*/ +#define BAR_SUBCHAN_INDEX_SEND 0 +#define BAR_SUBCHAN_INDEX_RECV 1 + +/* 消息源索引*/ +#define BAR_MSG_SRC_NUM 3 +#define BAR_MSG_SRC_MPF 0 +#define BAR_MSG_SRC_PF 1 +#define BAR_MSG_SRC_VF 2 +#define BAR_MSG_SRC_ERR 0xff + +/* 消息目的索引*/ +#define BAR_MSG_DST_NUM 3 +#define BAR_MSG_DST_RISC 0 +#define BAR_MSG_DST_MPF 2 +#define BAR_MSG_DST_PFVF 1 +#define BAR_MSG_DST_ERR 0xff + +/* msg_id项标志位状态*/ +#define REPS_INFO_FLAG_USABLE 0 +#define REPS_INFO_FLAG_USED 1 + +#define BAR_MSG_PAYLOAD_MAX_LEN (BAR_MSG_ADDR_CHAN_INTERVAL - sizeof(struct bar_msg_header)) + +#define BAR_MSG_POL_MASK (0x10) +#define BAR_MSG_POL_OFFSET (4) + +enum { + CHECK_STATE_OK = 0, + CHECK_STATE_EVENT_EXCEED = 1, + CHECK_STATE_EVENT_NOT_EXIST = 2, + CHECK_STATE_EVENT_ERR_RET = 4, + CHECK_STATE_EVENT_ERR_REPS_LEN = 5, +}; + +struct zxdh_pcie_bar_msg_internal +{ + uint32_t id; /**< the msg id that passing through */ + uint64_t virt_addr; /**< pcie bar mapping virtual addr */ +}; + +/* bar通道消息头 */ +struct bar_msg_header +{ + uint8_t valid: 1; /* 消息通道状态 */ + uint8_t sync: 1; /* 同步消息or异步消息*/ + uint8_t emec: 1; /* 消息是否紧急 */ + uint8_t ack: 1; /* 是否是回复消息*/ + uint8_t poll: 1; + uint8_t check; + uint16_t event_id; /* 请求的消息处理函数标识 */ + uint16_t len; /* 消息长度 */ + uint16_t msg_id; /* 消息id*/ + uint16_t src_pcieid; + uint16_t dst_pcieid; /* 用于pf给vf发消息*/ +}; + +/* 根据消息的msgid查询回复缓存的地址和长度*/ +struct msgid_reps_info +{ + void *reps_buffer; /* reps的地址*/ + uint16_t id; /* msg_id*/ + uint16_t buffer_len; /* buffer的最大长度*/ + uint16_t flag; /* 该条目是否被分配，已经非配和未被分配*/ + struct timer_list id_timer; /* 该id对应的定时器*/ +}; + +struct msix_msg +{ + uint16_t pcie_id; + uint16_t vector_risc; + uint16_t vector_pfvf; + uint16_t vector_mpf; +}; +struct offset_get_msg +{ + uint16_t pcie_id; + uint16_t type; +}; + +struct bar_offset_reps +{ + uint16_t check; + uint16_t rsv; + uint32_t offset; + uint32_t length; +}__attribute__((packed)); + +struct bar_recv_msg +{ + uint8_t replied; + uint16_t reps_len; + uint8_t rsv1; + union + { + struct bar_offset_reps offset_reps; + uint8_t data[BAR_MSG_PAYLOAD_MAX_LEN - 4]; + }; +}__attribute__((packed)); + +struct msgid_ring +{ + uint16_t msg_id; + spinlock_t lock; + struct msgid_reps_info reps_info_tbl[MAX_MSG_BUFF_NUM]; +}; + +/* 异步消息相关实体*/ +struct async_msg_entity +{ + struct task_struct *async_proc; /* 异步队列消息线程*/ + struct mutex async_qlock; /* 易怒队列入队锁*/ + struct bar_async_node *noemq_head; /* 非紧急队列头*/ + struct bar_async_node *noemq_tail; /* 非紧急队列尾部*/ + struct bar_async_node *emq_head; /* 紧急队列头*/ + struct bar_async_node *emq_tail; /* 紧急队列尾部*/ +}; + +/* 异步消息队列节点*/ +struct bar_async_node +{ + uint32_t msg_id; + void *payload_addr; /**< 消息净荷起始地址，有用户创建并填充 */ + uint64_t payload_len; /**< 消息净荷长度. */ + uint64_t subchan_addr; /**< 消息发送到哪个2K, 由virt_addr, src, dst共同决定，计算交给common来做>**/ + uint32_t event_id; /**< 消息发送模块，描述消息哪个模块发送 */ + uint16_t src_pcieid; + uint16_t dst_pcieid; /**< 消息目的的bdf号，适用于PF与VF公用4K的时候用>**/ + uint16_t emec; /**< 消息紧急类型，异步消息可以分为紧急消息和非紧急消息>**/ + uint16_t ack; + uint8_t src; + uint8_t dst; + struct bar_async_node *next; +}; + +uint8_t bar_msg_col_index_trans(uint8_t dst); +uint8_t bar_msg_row_index_trans(uint8_t src); + +#ifdef __cplusplus +} +#endif + +#endif /* _ZXDH_MSG_CHAN_PRIV_H_ */ diff --git a/src/net/drivers/net/ethernet/dinghai/cmd/msg_chan_test.c b/src/net/drivers/net/ethernet/dinghai/cmd/msg_chan_test.c new file mode 100644 index 0000000..1de7b52 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/cmd/msg_chan_test.c @@ -0,0 +1,148 @@ +#include +#include +#include +#include +#include +#include +#include +#include "cmd/msg_chan_priv.h" + +#ifdef BAR_MSG_TEST + +/*计算方法： risc时间戳 - host时间戳*/ +#define HOST_RISC_DIFF (307762) + +uint64_t print_time(char *str) +{ + ktime_t kt = ktime_get(); + s64 us_since_boot = ktime_to_us(kt); + LOG_INFO(KERN_INFO "%s timestamp: %llu us\n", str, us_since_boot); + return us_since_boot; +} +struct msg_time_statis_reps +{ + uint16_t sum_check; + + uint64_t risc_recv_msg_t; + uint64_t risc_push_msg_t; + uint64_t risc_pop_msg_t; + uint64_t risc_msg_proc_t; + uint64_t risc_notice_peer_t; +} __attribute__((packed)); + +struct msg_time_host_risc +{ + uint64_t host_send_msg_t; + uint64_t host_recv_msg_t; + struct msg_time_statis_reps risc_time; +}__attribute__((packed)); + +struct msg_time_host_risc global_time_stat = {0}; + +void print_risc_time_stamp(struct msg_time_host_risc *stat) +{ +#if 0 + LOF_INFO("host_send_msg_t: %llu us.\n", stat->host_send_msg_t); + LOF_INFO("risc_recv_msg_t: %llu us.\n", stat->risc_time.risc_recv_msg_t); + LOF_INFO("risc_push_msg_t: %llu us.\n", stat->risc_time.risc_push_msg_t); + LOF_INFO("risc_pop_msg_t: %llu us.\n", stat->risc_time.risc_pop_msg_t); + LOF_INFO("risc_msg_proc_t: %llu us.\n", stat->risc_time.risc_msg_proc_t); + LOF_INFO("risc_notice_peer_t: %llu us.\n", stat->risc_time.risc_notice_peer_t); + LOF_INFO("host_recv_msg_t: %llu us.\n", stat->host_recv_msg_t); +#endif + LOG_INFO("risc recv->msg push: %llu us.\n", stat->risc_time.risc_push_msg_t - stat->risc_time.risc_recv_msg_t); + LOG_INFO("risc push->risc pop: %llu us.\n", stat->risc_time.risc_pop_msg_t - stat->risc_time.risc_push_msg_t); + LOG_INFO("risc pop->before proc : %llu us.\n", stat->risc_time.risc_msg_proc_t- stat->risc_time.risc_pop_msg_t); + LOG_INFO("after proc->risc set valid: %llu us.\n", stat->risc_time.risc_notice_peer_t - stat->risc_time.risc_msg_proc_t); +} + +uint16_t sum_func(void *data, uint16_t len) +{ + uint64_t result = 0; + int idx = 0; + uint16_t ret = 0; + + if (data == NULL) + { + return 0; + } + + for (idx = 0; idx < len; idx++) + { + result += *((uint8_t *)data + idx); + } + + ret = (uint16_t)result; + return ret; +} + +uint16_t test_sync_send(void) +{ + struct zxdh_pci_bar_msg in = {0}; + struct zxdh_msg_recviver_mem result = {0}; + uint16_t payload_len = 0; + uint64_t bar_base_addr = 0; + void *payload_addr = NULL; + uint8_t recv_buffer[200] = {0}; + uint16_t reps = 0; + uint16_t ret = 0; + + payload_len = 100; + payload_addr = kmalloc(payload_len, GFP_KERNEL); + if (!payload_addr) + { + LOG_ERR("malloca failed"); + return 0xaa; + } + get_random_bytes(payload_addr, payload_len); + LOG_INFO("sync send msg len: %x", payload_len); + + in.src_pcieid = 0x900; + in.virt_addr = 0; + in.payload_addr = payload_addr; + in.payload_len = payload_len; + in.src = MSG_CHAN_END_MPF; + in.dst = MSG_CHAN_END_RISC; + in.event_id = 50; + + /* 构造result接收参数*/ + result.recv_buffer = recv_buffer; + result.buffer_len = sizeof(recv_buffer); + + /* 调用发送接口*/ + LOG_INFO("start to sync send test."); + global_time_stat.host_send_msg_t = print_time("before send.") + HOST_RISC_DIFF; + ret = zxdh_bar_chan_sync_msg_send(&in, &result); + global_time_stat.host_recv_msg_t = print_time("after send.") + HOST_RISC_DIFF; + + if (ret != BAR_MSG_OK) + { + LOG_ERR("sync send failed"); + ret = 0xAA; + goto out; + } + + struct msg_time_statis_reps *reps_ptr = (struct msg_time_statis_reps*)((uint8_t *)result.recv_buffer + 4); + if (reps_ptr->sum_check == sum_func(payload_addr, payload_len)) + { + memcpy(&global_time_stat.risc_time, (void*)reps_ptr, sizeof(struct msg_time_statis_reps)); + print_risc_time_stamp(&global_time_stat); + ret = 0; + LOG_ERR("reps validate success: %d", reps); + goto out; + } + else + { + LOG_ERR("reps valide failed: %d", reps); + ret = 0xAA; + } + +out: + if (!payload_addr) + { + kfree(payload_addr); + payload_addr = NULL; + } + return ret; +} +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/cmd/msg_chan_ver.h b/src/net/drivers/net/ethernet/dinghai/cmd/msg_chan_ver.h new file mode 100644 index 0000000..b3575d2 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/cmd/msg_chan_ver.h @@ -0,0 +1,16 @@ +#ifndef _ZXDH_MSG_CHAN_VERSION_H_ +#define _ZXDH_MSG_CHAN_VERSION_H_ + +#ifdef DRIVER_VERSION_VAL + #define DRV_VERSION DRIVER_VERSION_VAL +#else + #define DRV_VERSION "1.0-1" +#endif + +#define DRV_RELDATE "December 1, 2022" +#define DRV_NAME "msg_chan" +#define DRV_DESCRIPTION "DPU MSG Channel Driver" + +#define hbond_version DRV_DESCRIPTION ": v" DRV_VERSION " (" DRV_RELDATE ")\n" + +#endif /* _ZXDH_MSG_CHAN_VERSION_H_ */ \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/cmd/msg_main.c b/src/net/drivers/net/ethernet/dinghai/cmd/msg_main.c new file mode 100644 index 0000000..599e6e5 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/cmd/msg_main.c @@ -0,0 +1,31 @@ +#include +#include +#include + +#include "msg_chan_ver.h" +#include "msg_chan_priv.h" + +static int __init msg_chan_init(void) +{ + BAR_LOG_INFO("%s init. version %s\n", DRV_DESCRIPTION, DRV_VERSION); + zxdh_bar_msg_chan_init(); + +#ifdef TEST + BAR_TestApp(); +#endif + + return 0; +} + +static void __exit msg_chan_exit(void) +{ + zxdh_bar_msg_chan_remove(); + BAR_LOG_INFO("%s exit.\n", DRV_DESCRIPTION); +} + +module_init(msg_chan_init); +module_exit(msg_chan_exit); +MODULE_LICENSE("Dual BSD/GPL"); +MODULE_VERSION(DRV_VERSION); +MODULE_DESCRIPTION(DRV_DESCRIPTION ", v" DRV_VERSION); +MODULE_AUTHOR("ZTE Corporation"); diff --git a/src/net/drivers/net/ethernet/dinghai/devlink.c b/src/net/drivers/net/ethernet/dinghai/devlink.c new file mode 100755 index 0000000..f244c90 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/devlink.c @@ -0,0 +1,50 @@ +#include +#include + +#ifdef HAVE_DEVLINK_REGISTER_GET_1_PARAMS + int32_t zxdh_devlink_register(struct devlink *devlink) +#else + int32_t zxdh_devlink_register(struct devlink *devlink, struct device *dev) +#endif +{ + struct dh_core_dev *dh_dev = devlink_priv(devlink); + int32_t err = 0; + +#ifdef HAVE_DEVLINK_REGISTER_GET_1_PARAMS + devlink_register(devlink); +#else + devlink_register(devlink, dev); +#endif + + err = dh_dev->devlink_ops->params_register(devlink); + if (err != 0) + { + LOG_ERR("params_register failed: %d\n", err); + return err; + } + + return err; +} + +struct devlink *zxdh_devlink_alloc(struct device *dev, struct devlink_ops *dh_devlink_ops, size_t priv_size) +{ +#ifdef HAVE_DEVLINK_ALLOC_GET_1_PARAMS + return devlink_alloc(dh_devlink_ops, sizeof(struct dh_core_dev) + priv_size); +#else + return devlink_alloc(dh_devlink_ops, sizeof(struct dh_core_dev) + priv_size, dev); +#endif +} + +void zxdh_devlink_free(struct devlink *devlink) +{ + devlink_free(devlink); +} + +void zxdh_devlink_unregister(struct devlink *devlink) +{ + struct dh_core_dev *dev = devlink_priv(devlink); + + dev->devlink_ops->params_unregister(devlink); + + devlink_unregister(devlink); +} diff --git a/src/net/drivers/net/ethernet/dinghai/dh_cmd.c b/src/net/drivers/net/ethernet/dinghai/dh_cmd.c new file mode 100644 index 0000000..704cf4a --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/dh_cmd.c @@ -0,0 +1,1208 @@ +#include +#include +#include +#include +#include +#include +#include "cmd/msg_chan_priv.h" +#include "cmd/msg_chan_lock.h" +#include "en_aux/en_cmd.h" +#include "msg_common.h" + +/***************************************** +[src/dst]时应该将消息发到低2k(0)还是高2K(1) +src/dst: TO_RISC, TO_PFVF, TO_MPF +MPF: 0 0 0 +PF: 0 0 1 +VF: 0 1 1 +******************************************/ +uint8_t subchan_id_tbl[BAR_MSG_SRC_NUM][BAR_MSG_DST_NUM] = +{ + {BAR_SUBCHAN_INDEX_SEND, BAR_SUBCHAN_INDEX_SEND, BAR_SUBCHAN_INDEX_SEND}, + {BAR_SUBCHAN_INDEX_SEND, BAR_SUBCHAN_INDEX_SEND, BAR_SUBCHAN_INDEX_RECV}, + {BAR_SUBCHAN_INDEX_SEND, BAR_SUBCHAN_INDEX_RECV, BAR_SUBCHAN_INDEX_RECV} +}; + +uint8_t chan_id_tbl[BAR_MSG_SRC_NUM][BAR_MSG_DST_NUM] = +{ + {BAR_INDEX_TO_RISC, BAR_INDEX_MPF_TO_PFVF, BAR_INDEX_MPF_TO_MPF}, + {BAR_INDEX_TO_RISC, BAR_INDEX_PF_TO_VF, BAR_INDEX_PFVF_TO_MPF}, + {BAR_INDEX_TO_RISC, BAR_INDEX_PF_TO_VF, BAR_INDEX_PFVF_TO_MPF} +}; + +void *internal_addr; + +bool is_mpf_scaned = FALSE; + +static struct msgid_ring g_msgid_ring; + +/* 消息处理函数表*/ +zxdh_bar_chan_msg_recv_callback msg_recv_func_tbl[MSG_MODULE_NUM]; + +void bar_chan_check_chan_stats(int ret, uint64_t addr) +{ + struct bar_msg_header *hdr = (struct bar_msg_header*)addr; + + if (ret == 0) + { + return; + } + /* check bar msg_header*/ + BAR_LOG_ERR("bar msg err, ret: %d, valid: %u, msg_id: %u, event_id: %u, " + "ack: %u, src_pcieid: 0x%x, dst_pcieid: 0x%x, chan_addr: 0x%llx.\n", + ret, hdr->valid, hdr->msg_id, hdr->event_id, hdr->ack, hdr->src_pcieid, hdr->dst_pcieid, addr); +} + +uint16_t bar_msg_src_parse(struct zxdh_pci_bar_msg *in) +{ + if (in == NULL) + { + return BAR_MSG_ERR_NULL; + } + + if (in->src == MSG_CHAN_END_MPF) + { + if (!is_mpf_scaned) + { + return BAR_MSG_ERR_MPF_NOT_SCANED; + } + in->virt_addr = (uint64_t)internal_addr + BAR_MSG_OFFSET; + in->src_pcieid = PF0_PCIEID; + } + return BAR_MSG_OK; +} + +void bar_chan_sync_fill_header(uint32_t msg_id, struct zxdh_pci_bar_msg *in, struct bar_msg_header *msg_header) +{ + memset(msg_header, 0, sizeof(*msg_header)); + msg_header->sync = BAR_CHAN_MSG_SYNC; + msg_header->event_id = in->event_id; + msg_header->len = in->payload_len; + msg_header->msg_id = msg_id; + msg_header->dst_pcieid = in->dst_pcieid; + msg_header->src_pcieid = in->src_pcieid; +} + +int bar_chan_msgid_allocate(uint16_t *msgid) +{ + int ret = BAR_MSG_OK; + uint16_t msg_id = 0; + struct msgid_reps_info *msgid_reps_info = NULL; + uint16_t count = 0; + + spin_lock(&g_msgid_ring.lock); + msg_id = g_msgid_ring.msg_id; + do + { + count++; + ++msg_id; + msg_id %= MAX_MSG_BUFF_NUM; + msgid_reps_info = &g_msgid_ring.reps_info_tbl[msg_id]; + + }while(msgid_reps_info->flag != REPS_INFO_FLAG_USABLE && (count < MAX_MSG_BUFF_NUM)); + + if (count >= MAX_MSG_BUFF_NUM) + { + ret = -1; + goto out; + } + + msgid_reps_info->flag = REPS_INFO_FLAG_USED; + g_msgid_ring.msg_id = msg_id; + *msgid = msg_id; + +out: + spin_unlock(&g_msgid_ring.lock); + return ret; +} + +uint16_t bar_chan_save_recv_info(struct zxdh_msg_recviver_mem *result, uint16_t *msg_id) +{ + int ret = 0; + struct msgid_reps_info *reps_info = NULL; + + ret = bar_chan_msgid_allocate(msg_id); + if (ret == -1) + { + return BAR_MSG_ERR_MSGID; + } + reps_info = &g_msgid_ring.reps_info_tbl[*msg_id]; + reps_info->reps_buffer = result->recv_buffer; + reps_info->buffer_len = result->buffer_len; + + return BAR_MSG_OK; +} + +void bar_chan_msgid_free(uint16_t msg_id) +{ + struct msgid_reps_info *msgid_reps_info = NULL; + if (msg_id >= MAX_MSG_BUFF_NUM) + { + return; + } + msgid_reps_info = &g_msgid_ring.reps_info_tbl[msg_id]; + spin_lock(&g_msgid_ring.lock); + msgid_reps_info->flag = REPS_INFO_FLAG_USABLE; + spin_unlock(&g_msgid_ring.lock); + return; +} + +uint8_t bar_msg_row_index_trans(uint8_t src) +{ + uint8_t src_index = 0; + + switch (src) + { + case MSG_CHAN_END_MPF: + { + src_index = BAR_MSG_SRC_MPF; + break; + } + case MSG_CHAN_END_PF: + { + src_index = BAR_MSG_SRC_PF; + break; + } + case MSG_CHAN_END_VF: + { + src_index = BAR_MSG_SRC_VF; + break; + } + default: + { + src_index = BAR_MSG_SRC_ERR; + break; + } + } + return src_index; +} + +uint8_t bar_msg_col_index_trans(uint8_t dst) +{ + uint8_t dst_index = 0; + + switch (dst) + { + case MSG_CHAN_END_MPF: + { + dst_index = BAR_MSG_DST_MPF; + break; + } + case MSG_CHAN_END_PF: + { + dst_index = BAR_MSG_DST_PFVF; + break; + } + case MSG_CHAN_END_VF: + { + dst_index = BAR_MSG_DST_PFVF; + break; + } + case MSG_CHAN_END_RISC: + { + dst_index = BAR_MSG_DST_RISC; + break; + } + default: + { + dst_index = BAR_MSG_SRC_ERR; + break; + } + } + return dst_index; +} + +int bar_chan_send_para_check(struct zxdh_pci_bar_msg *in, struct zxdh_msg_recviver_mem *result) +{ + uint8_t src_index = 0; + uint8_t dst_index = 0; + + if (in == NULL || result == NULL) + { + BAR_LOG_ERR("send para ERR: null para.\n"); + return BAR_MSG_ERR_NULL_PARA; + } + + src_index = bar_msg_row_index_trans((uint8_t)in->src); + dst_index = bar_msg_col_index_trans((uint8_t)in->dst); + if (src_index == BAR_MSG_SRC_ERR || dst_index == BAR_MSG_DST_ERR) + { + BAR_LOG_ERR("send para ERR: chan doesn't exist.\n"); + return BAR_MSG_ERR_TYPE; + } + if (in->event_id > MSG_MODULE_NUM) + { + BAR_LOG_ERR("send para ERR: invalid event_id: %d.\n", in->event_id); + return BAR_MSG_ERR_MODULE; + } + if (in->payload_addr == NULL) + { + BAR_LOG_ERR("send para ERR: null message.\n"); + return BAR_MSG_ERR_BODY_NULL; + } + if (in->payload_len > BAR_MSG_PAYLOAD_MAX_LEN) + { + BAR_LOG_ERR("send para ERR: len %x is too long.\n", in->payload_len); + return BAR_MSG_ERR_LEN; + } + if (in->virt_addr == 0 || result->recv_buffer == NULL) + { + BAR_LOG_ERR("send para ERR: virt_addr or recv_buffer is NULL.\n"); + return BAR_MSG_ERR_VIRTADDR_NULL; + } + if (result->buffer_len < REPS_HEADER_PAYLOAD_OFFSET) + { + BAR_LOG_ERR("recv buffer's len: %d is short than mininal 4 bytes\n", result->buffer_len); + } + return BAR_MSG_OK; +} + +/* 根据用户提供的src和dst和当前的场景来推算2K的偏移*/ +void bar_chan_subchan_addr_get(struct zxdh_pci_bar_msg *in, uint64_t *subchan_addr) +{ + uint8_t src_index, dst_index; + uint16_t chan_id, subchan_id; + + src_index = bar_msg_row_index_trans((uint8_t)in->src); + dst_index = bar_msg_col_index_trans((uint8_t)in->dst); + + if (src_index == BAR_MSG_SRC_ERR || dst_index == BAR_MSG_DST_ERR) + { + return; + } + + chan_id = chan_id_tbl[src_index][dst_index]; + subchan_id = subchan_id_tbl[src_index][dst_index]; + *subchan_addr = in->virt_addr + (2 * chan_id + subchan_id) * BAR_MSG_ADDR_CHAN_INTERVAL; + return; +} + +int bar_chan_reg_write(uint64_t subchan_addr, uint32_t offset, uint32_t data) +{ + uint32_t algin_offset = (offset & BAR_ALIGN_WORD_MASK); + + if (algin_offset >= BAR_MSG_ADDR_CHAN_INTERVAL) + { + return -EADDRNOTAVAIL; + } + + writel(data, (volatile void*)(subchan_addr + algin_offset)); + return 0; +} + +int bar_chan_reg_read(uint64_t subchan_addr, uint32_t offset, uint32_t *pdata) +{ + uint32_t algin_offset = (offset & BAR_ALIGN_WORD_MASK); + + if (algin_offset >= BAR_MSG_ADDR_CHAN_INTERVAL) + { + return -EADDRNOTAVAIL; + } + + *pdata = readl((const volatile void *)(subchan_addr + algin_offset)); + return 0; +} + +uint16_t bar_chan_msg_header_set(uint64_t subchan_addr, struct bar_msg_header *msg_header) +{ + uint32_t *data = (uint32_t*)msg_header; + uint16_t idx = 0; + + for (idx = 0; idx < (BAR_MSG_PLAYLOAD_OFFSET >> 2); idx++) + { + bar_chan_reg_write(subchan_addr, idx * 4, *(data + idx)); + } + + return BAR_MSG_OK; +} + +uint16_t bar_chan_msg_header_get(uint64_t subchan_addr, struct bar_msg_header *msg_header) +{ + uint32_t *data = (uint32_t*)msg_header; + uint16_t idx = 0; + + for (idx = 0; idx < (BAR_MSG_PLAYLOAD_OFFSET >> 2); idx++) + { + bar_chan_reg_read(subchan_addr, idx * 4, data + idx); + } + + return BAR_MSG_OK; +} + +uint16_t bar_chan_msg_payload_set(uint64_t subchan_addr, uint8_t *msg, uint16_t len) +{ + uint32_t *data = (uint32_t*)msg; + uint32_t count = (len / sizeof(uint32_t)); + uint32_t remain = (len % sizeof(uint32_t)); + uint32_t ix = 0, remain_data = 0; + + for (ix = 0; ix < count; ix++) + { + bar_chan_reg_write(subchan_addr, 4 * ix + BAR_MSG_PLAYLOAD_OFFSET, *(data + ix)); + } + for (ix = 0; ix < remain; ix++) + { + remain_data |= *((uint8_t *)(msg + (len - remain + ix))) << (8 * ix); + } + bar_chan_reg_write(subchan_addr, 4 * count + BAR_MSG_PLAYLOAD_OFFSET, remain_data); + + return BAR_MSG_OK; +} + +uint16_t bar_chan_msg_payload_get(uint64_t subchan_addr, uint8_t *msg, uint16_t len) +{ + uint32_t *data = (uint32_t*)msg; + uint32_t count = (len / sizeof(uint32_t)); + uint32_t remain = (len % sizeof(uint32_t)); + uint32_t ix = 0, remain_data = 0; + + for (ix = 0; ix < count; ix++) + { + bar_chan_reg_read(subchan_addr, 4 * ix + BAR_MSG_PLAYLOAD_OFFSET, (data + ix)); + } + bar_chan_reg_read(subchan_addr, 4 * count + BAR_MSG_PLAYLOAD_OFFSET, &remain_data); + for (ix = 0; ix < remain; ix++) + { + *((uint8_t *)(msg + (len - remain + ix))) = remain_data >> (8 * ix); + } + return BAR_MSG_OK; +} + +uint16_t bar_chan_msg_valid_set(uint64_t subchan_addr, uint8_t valid_label) +{ + uint32_t data = 0; + + bar_chan_reg_read(subchan_addr, BAR_MSG_VALID_OFFSET, &data); + data &= (~BAR_MSG_VALID_MASK); + data |= (uint32_t)valid_label; + bar_chan_reg_write(subchan_addr, BAR_MSG_VALID_OFFSET, data); + + return BAR_MSG_OK; +} + +uint16_t bar_msg_valid_stat_get(uint64_t subchan_addr) +{ + uint32_t data = 0; + + bar_chan_reg_read(subchan_addr, BAR_MSG_VALID_OFFSET, &data); + if (BAR_MSG_CHAN_USABLE == (data & BAR_MSG_VALID_MASK)) + { + return BAR_MSG_CHAN_USABLE; + } + + return BAR_MSG_CHAN_USED; +} + +uint16_t bar_chan_msg_poltag_set(uint64_t subchan_addr, uint8_t label) +{ + uint32_t data = 0; + + bar_chan_reg_read(subchan_addr, BAR_MSG_VALID_OFFSET, &data); + data &= (~(uint32_t)BAR_MSG_POL_MASK); + data |= ((uint32_t)label << BAR_MSG_POL_OFFSET); + bar_chan_reg_write(subchan_addr, BAR_MSG_VALID_OFFSET, data); + + return BAR_MSG_OK; +} + +static uint8_t payload_temp_buf[BAR_MSG_ADDR_CHAN_INTERVAL] = {0}; +uint16_t bar_chan_msg_send(uint64_t subchan_addr, void *payload_addr, uint16_t payload_len, struct bar_msg_header *msg_header) +{ + uint8_t *msg = (uint8_t*)(payload_addr); + struct bar_msg_header hdr_read = {0}; + uint16_t valid = 0; + + bar_chan_msg_header_set(subchan_addr, msg_header); + bar_chan_msg_header_get(subchan_addr, &hdr_read); + + bar_chan_msg_payload_set(subchan_addr, msg, payload_len); + bar_chan_msg_payload_get(subchan_addr, payload_temp_buf, payload_len); + + bar_chan_msg_valid_set(subchan_addr, BAR_MSG_CHAN_USED); + valid = bar_msg_valid_stat_get(subchan_addr); + + return BAR_MSG_OK; +} + +int bar_chan_recv_func_check(uint16_t check) +{ + if (CHECK_STATE_OK == check) + { + return BAR_MSG_OK; + } + else + { + BAR_LOG_ERR("recv func check failed, check field: 0x%x", check); + return BAR_MSG_ERR_USR_RET_ERR; + } +} + +int bar_chan_sync_msg_reps_get(uint64_t subchan_addr, uint64_t recv_buffer, uint16_t buffer_len, uint16_t send_msg_id) +{ + int ret = BAR_MSG_OK; + uint16_t recv_msg_id = 0; + uint16_t recv_len = 0; + uint8_t *recv_msg = (uint8_t*)recv_buffer; + struct bar_msg_header msg_header; + struct msgid_reps_info *reps_info = NULL; + + /*从消息头中取出消息回复的长度，取出msg_id，如果msg_id对应的usable的话，该条同步回复作废*/ + memset(&msg_header, 0, sizeof(msg_header)); + bar_chan_msg_header_get(subchan_addr, &msg_header); + recv_len = msg_header.len; + recv_msg_id = msg_header.msg_id; + + if (recv_msg_id != send_msg_id) + { + BAR_LOG_ERR("send msg id: %d, but get reply msg id: %d.\n", send_msg_id, recv_msg_id); + ret = BAR_MSG_ERR_REPLY; + goto out; + } + + reps_info = &g_msgid_ring.reps_info_tbl[recv_msg_id]; + if (reps_info->flag != REPS_INFO_FLAG_USED) + { + BAR_LOG_ERR("msg_id: %d is release", recv_msg_id); + ret = BAR_MSG_ERR_REPLY; + goto out; + } + if (recv_len > buffer_len - REPS_HEADER_PAYLOAD_OFFSET) + { + BAR_LOG_ERR("reps_buf_len is %d, but reps_msg_len is %d", buffer_len, recv_len + 4); + ret = BAR_MSG_ERR_REPSBUFF_LEN; + goto out; + } + + /* 从reps_buff + 4的位置拷贝进回复数据*/ + bar_chan_msg_payload_get(subchan_addr, recv_msg + REPS_HEADER_PAYLOAD_OFFSET, recv_len); + + ret = bar_chan_recv_func_check(msg_header.check); + if (ret != BAR_MSG_OK) + { + goto out; + } + + /* 拷贝数据长度*/ + *(uint16_t*)(recv_msg + REPS_HEADER_LEN_OFFSET) = recv_len; + /* reps头valid置位*/ + *recv_msg = REPS_HEADER_REPLYED; + +out: + return ret; +} + +uint64_t subchan_addr_cal(uint64_t virt_addr, uint8_t chan_id, uint8_t subchan_id) +{ + return virt_addr + (2 * chan_id + subchan_id) * BAR_MSG_ADDR_CHAN_INTERVAL; +} + +uint64_t recv_addr_get(uint8_t src_type, uint8_t dst_type, uint64_t virt_addr) +{ + uint8_t chan_id = 0; + uint8_t subchan_id = 0; + uint8_t src = bar_msg_col_index_trans(src_type); + uint8_t dst = bar_msg_row_index_trans(dst_type); + + if (src >= BAR_MSG_SRC_NUM || dst >= BAR_MSG_DST_NUM) + { + return 0; + } + /* 接收通道id和发送通道id相同*/ + chan_id = chan_id_tbl[dst][src]; + /* 接收子通道id和发送子通道相反*/ + subchan_id = (!!subchan_id_tbl[dst][src])? BAR_SUBCHAN_INDEX_SEND : BAR_SUBCHAN_INDEX_RECV; + return subchan_addr_cal(virt_addr, chan_id, subchan_id); +} + +uint64_t reply_addr_get(uint8_t sync, uint8_t src_type, uint8_t dst_type, uint64_t virt_addr) +{ + uint8_t chan_id = 0; + uint8_t subchan_id = 0; + uint64_t recv_rep_addr = 0; + uint8_t src = bar_msg_col_index_trans(src_type); + uint8_t dst = bar_msg_row_index_trans(dst_type); + + if (src == BAR_MSG_SRC_ERR || dst == BAR_MSG_DST_ERR) + { + return 0; + } + + chan_id = chan_id_tbl[dst][src]; + subchan_id = (!!subchan_id_tbl[dst][src])? BAR_SUBCHAN_INDEX_SEND : BAR_SUBCHAN_INDEX_RECV; + if (sync == BAR_CHAN_MSG_SYNC) //同步消息 + { + recv_rep_addr = subchan_addr_cal(virt_addr, chan_id, subchan_id); + } + else + { + recv_rep_addr = subchan_addr_cal(virt_addr, chan_id, 1 - subchan_id); + } + return recv_rep_addr; +} + +uint16_t bar_chan_msg_header_check(struct bar_msg_header *msg_header) +{ + uint8_t event_id = 0; + uint16_t len = 0; + + if (msg_header == NULL) + { + return BAR_MSG_ERR_NULL; + } + if (msg_header->valid != BAR_MSG_CHAN_USED) + { + BAR_LOG_ERR("recv header ERR: valid label is not used.\n"); + return BAR_MSG_ERR_MODULE; + } + event_id = msg_header->event_id; + if (event_id >= (uint8_t)MSG_MODULE_NUM) + { + BAR_LOG_ERR("recv header ERR: invalid event_id: %d.\n", event_id); + return BAR_MSG_ERR_MODULE; + } + len = msg_header->len; + if (len > BAR_MSG_PAYLOAD_MAX_LEN) + { + BAR_LOG_ERR("recv header ERR: invalid mesg len: %d.\n", len); + return BAR_MSG_ERR_LEN; + } + if (msg_header->ack == BAR_CHAN_MSG_NO_ACK && msg_recv_func_tbl[msg_header->event_id] == NULL) + { + BAR_LOG_DEBUG("recv header ERR: module:%d doesn't register", event_id); + return BAR_MSG_ERR_MODULE_NOEXIST; + } + return BAR_MSG_OK; +} + + +/* 同步消息接收处理*/ +void bar_msg_sync_msg_proc(uint64_t reply_addr, struct bar_msg_header *msg_header, uint8_t *reciver_buff, void *dev) +{ + uint16_t reps_len = 0; + uint8_t *reps_buffer = NULL; + zxdh_bar_chan_msg_recv_callback recv_func = NULL; + + reps_buffer = kmalloc(BAR_MSG_PAYLOAD_MAX_LEN, GFP_KERNEL); + if (reps_buffer == NULL) + { + return; + } + /* 查询消息处理函数，处理消息，消息处理的结果放到reps_buffer中， 长度放到reps_len中*/ + recv_func = msg_recv_func_tbl[msg_header->event_id]; + recv_func(reciver_buff, msg_header->len, reps_buffer, &reps_len, dev); + msg_header->ack = BAR_CHAN_MSG_ACK; + msg_header->len = reps_len; + /* 计算回复消息2K的地址*/ + bar_chan_msg_header_set(reply_addr, msg_header); + bar_chan_msg_payload_set(reply_addr, reps_buffer, reps_len); + bar_chan_msg_valid_set(reply_addr, BAR_MSG_CHAN_USABLE); + + BAR_KFREE_PTR(reps_buffer); + return; +} + +/* 统一的中断处理函数*/ +int zxdh_bar_irq_recv(uint8_t src, uint8_t dst, uint64_t virt_addr, void *dev) +{ + uint64_t recv_addr = 0; + uint64_t reps_addr = 0; + struct bar_msg_header msg_header = {0}; + uint8_t *recved_msg = NULL; + uint16_t ret = 0; + + /*1 接收消息地址*/ + recv_addr = recv_addr_get(src, dst, virt_addr); + BAR_LOG_DEBUG("recv_addr: 0x%llx, \nvirt_addr: 0x%llx", recv_addr, virt_addr); + if (recv_addr == 0) + { + BAR_LOG_DEBUG("invalid driver type"); + return BAR_MSG_ERR_NULL; + } + /*2 取消息头并检查是否合法*/ + bar_chan_msg_header_get(recv_addr, &msg_header); + ret = bar_chan_msg_header_check(&msg_header); + if (ret != BAR_MSG_OK) + { + bar_chan_check_chan_stats(ret, recv_addr); + return ret; + } + /*3 创建消息payload buf，取出消息暂存*/ + recved_msg = kmalloc(msg_header.len, GFP_KERNEL); + if (recved_msg == NULL) + { + BAR_LOG_DEBUG("create temp buff failed"); + return BAR_MSG_ERR_NULL; + } + bar_chan_msg_payload_get(recv_addr, recved_msg, msg_header.len); + + /*4 根据来的是同步消息还是异步消息计算回复消息地址*/ + reps_addr = reply_addr_get(msg_header.sync, src, dst, virt_addr); + + /*5 如果是同步消息，走同步消息流程*/ + if (msg_header.sync == BAR_CHAN_MSG_SYNC) + { + bar_msg_sync_msg_proc(reps_addr, &msg_header, recved_msg, dev); + goto out; + } + + /*6 不应该为异步消息，先置位告诉对方已收到消息*/ + BAR_LOG_DEBUG("%d end set valid", dst); + //TODO set 错误码 + bar_chan_msg_poltag_set(recv_addr, 0); + bar_chan_msg_valid_set(recv_addr, BAR_MSG_CHAN_USABLE); + +out: + kfree(recved_msg); + return BAR_MSG_OK; +} +EXPORT_SYMBOL(zxdh_bar_irq_recv); + +int32_t call_msg_recv_func_tbl(uint16_t event_id, void *pay_load, uint16_t len, void *reps_buffer, uint16_t *reps_len, void *dev) +{ + zxdh_bar_chan_msg_recv_callback recv_func = NULL; + + recv_func = msg_recv_func_tbl[event_id]; + if (unlikely(recv_func == NULL)) + { + BAR_LOG_ERR("event_id[%d] unregister\n", event_id); + return BAR_MSG_ERR_MODULE_NOEXIST; + } + + return recv_func(pay_load, len, reps_buffer, reps_len, dev); +} +EXPORT_SYMBOL(call_msg_recv_func_tbl); + + +/** + * zxdh_bar_chan_sync_msg_send - 通过PCIE BAR空间发送同步消息 + * @in: 消息发送信息 + * @result: 消息结果反馈 + * @return: 0 成功，其他失败 + */ +int zxdh_bar_chan_sync_msg_send(struct zxdh_pci_bar_msg *in, struct zxdh_msg_recviver_mem *result) +{ + int ret = 0; + uint16_t valid = 0; + uint16_t time_out_cnt = 0; + uint16_t msg_id = 0; + uint64_t subchan_addr = 0; + struct bar_msg_header msg_header = {0}; + + ret = bar_msg_src_parse(in); + if (ret != BAR_MSG_OK) + { + goto out; + } + + ret = bar_chan_send_para_check(in, result); + if (ret != BAR_MSG_OK) + { + BAR_LOG_ERR("para check failed, %d.", ret); + goto out; + } + + /* 申请msg_id,并将缓存信息存放到表中*/ + ret = bar_chan_save_recv_info(result, &msg_id); + if (ret != BAR_MSG_OK) + { + BAR_LOG_ERR("msg_id allocated failed."); + goto out; + } + /* 计算2K通道的地址*/ + bar_chan_subchan_addr_get(in, &subchan_addr); + /* 填充消息头*/ + bar_chan_sync_fill_header(msg_id, in, &msg_header); + /* 给通道上锁，根据src和dst判断是分配硬件锁还是软件锁*/ + bar_chan_lock((uint8_t)in->src, (uint8_t)in->dst, in->src_pcieid); + + /* 消息头、消息体发送到bar空间， valid置位*/ + bar_chan_msg_send(subchan_addr, in->payload_addr, in->payload_len, &msg_header); + /* 轮询等待消息回复*/ + do + { + usleep_range(BAR_MSG_POLLING_SPAN_US, BAR_MSG_POLLING_SPAN_US + 10); + valid = bar_msg_valid_stat_get(subchan_addr); + time_out_cnt++; + }while((time_out_cnt < BAR_MSG_TIMEOUT_TH) && (BAR_MSG_CHAN_USED == valid)); + + /* 如果超时恢复标志位*/ + if ((BAR_MSG_TIMEOUT_TH == time_out_cnt) && (BAR_MSG_CHAN_USABLE != valid)) + { + bar_chan_msg_valid_set(subchan_addr, BAR_MSG_CHAN_USABLE); + bar_chan_msg_poltag_set(subchan_addr, 0); + BAR_LOG_ERR("BAR MSG ERR: msg_id: %d time out.\n", msg_header.msg_id); + ret = BAR_MSG_ERR_TIME_OUT; + } + else + { + /* 从消息头中取出回复消息的长度len, 从payload中取出消息内容，放到本地缓存reps_buff*/ + ret = bar_chan_sync_msg_reps_get(subchan_addr, (uint64_t)result->recv_buffer, result->buffer_len, msg_id); + } + bar_chan_msgid_free(msg_id); + /*通道解锁*/ + bar_chan_unlock((uint8_t)in->src, (uint8_t)in->dst, in->src_pcieid); + bar_chan_check_chan_stats(ret, subchan_addr); +out: + return ret; +} +EXPORT_SYMBOL(zxdh_bar_chan_sync_msg_send); + +static int bar_chan_callback_register_check(uint8_t event_id, zxdh_bar_chan_msg_recv_callback callback) +{ + if (event_id >= (uint8_t)MSG_MODULE_NUM) + { + BAR_LOG_ERR("register ERR: invalid event_id: %d.\n", event_id); + return BAR_MSG_ERR_MODULE; + } + if (callback == NULL) + { + BAR_LOG_ERR("register ERR: null callback.\n"); + return BAR_MEG_ERR_NULL_FUNC; + } + if (msg_recv_func_tbl[event_id] != NULL) + { + BAR_LOG_ERR("register ERR: repeat register.\n"); + return BAR_MSG_ERR_REPEAT_REGISTER; + } + return BAR_MSG_OK; +} + +/** + * zxdh_bar_chan_msg_recv_register - PCIE BAR空间消息方式，注册消息接收回调 + * @event_id: 注册模块id + * @callback: 模块实现的接收处理函数指针 + * @return: 0 成功，其他失败 + * 一般在驱动初始化时调用 + */ +int zxdh_bar_chan_msg_recv_register(uint8_t event_id, zxdh_bar_chan_msg_recv_callback callback) +{ + int ret = 0; + + ret = bar_chan_callback_register_check(event_id, callback); + + if (BAR_MSG_OK == ret) + { + msg_recv_func_tbl[event_id] = callback; + BAR_LOG_DEBUG("register module: %d success.\n", event_id); + } + + return ret; +} +EXPORT_SYMBOL(zxdh_bar_chan_msg_recv_register); + +/** + * zxdh_bar_chan_msg_recv_unregister - PCIE BAR空间消息方式，解注册消息接收回调 + * @event_id: 内核PCIE设备地址 + * @return:0 成功，其他失败 + * 在驱动卸载时需要调用 + */ +int zxdh_bar_chan_msg_recv_unregister(uint8_t event_id) +{ + if (event_id >= (uint8_t)MSG_MODULE_NUM) + { + BAR_LOG_ERR("unregister ERR: invalid event_id :%d.\n", event_id); + return BAR_MSG_ERR_MODULE; + } + if (msg_recv_func_tbl[event_id] == NULL) + { + BAR_LOG_ERR("unregister ERR: null proccess func.\n"); + return BAR_MSG_ERR_UNGISTER; + } + msg_recv_func_tbl[event_id] = NULL; + BAR_LOG_DEBUG("unregister module %d success.\n", event_id); + return BAR_MSG_OK; +} +EXPORT_SYMBOL(zxdh_bar_chan_msg_recv_unregister); + +int bar_mpf_addr_ioremap(void) +{ + uint64_t addr; + uint64_t len; + struct pci_dev *pdev = NULL; + + pdev = pci_get_device(MPF_VENDOR_ID, MPF_DEVICE_ID, NULL); + + if (pdev == NULL) + { + BAR_LOG_DEBUG("not found device: deviceID %x, VendorID: %x", MPF_DEVICE_ID, MPF_VENDOR_ID); + return -EINVAL; + } + + addr = pci_resource_start(pdev, 0); + len = pci_resource_len(pdev, 0); + if (addr == 0 || len == 0) + { + BAR_LOG_ERR("pci resouce addr or len is 0\n"); + return -EINVAL; + } + + internal_addr = ioremap(addr, len); + if (IS_ERR_OR_NULL(internal_addr)) + { + BAR_LOG_ERR("ioremap failed, internal_addr=0x%p\n", internal_addr); + return -ENOMEM; + } + is_mpf_scaned = TRUE; + + return BAR_MSG_OK; +} + +void bar_mpf_addr_iounmap(void) +{ + if (internal_addr != NULL) + { + iounmap(internal_addr); + } + internal_addr = NULL; + is_mpf_scaned = FALSE; + return; +} + +int bar_msgid_ring_init(void) +{ + uint16_t msg_id = 0; + struct msgid_reps_info *reps_info = NULL; + + spin_lock_init(&g_msgid_ring.lock); + for( msg_id = 0; msg_id < MAX_MSG_BUFF_NUM; msg_id++) + { + reps_info = &(g_msgid_ring.reps_info_tbl[msg_id]); + reps_info->id = msg_id; + reps_info->flag = REPS_INFO_FLAG_USABLE; + } + return BAR_MSG_OK; +} + +void bar_msgid_ring_free(void) +{ + uint16_t msg_id = 0; + struct msgid_reps_info *reps_info = NULL; + + for (msg_id = 0; msg_id < MAX_MSG_BUFF_NUM; msg_id++) + { + reps_info = &g_msgid_ring.reps_info_tbl[msg_id]; + del_timer_sync(&reps_info->id_timer); + } +} + +extern uint16_t test_sync_send(void); +int zxdh_bar_msg_chan_init(void) +{ + int16_t ret = 0; + + /* msg_id锁初始化*/ + bar_init_lock_arr(); + bar_msgid_ring_init(); + + /* 管理pf地址映射*/ + ret = bar_mpf_addr_ioremap(); + if (ret != BAR_MSG_OK) + { + BAR_LOG_DEBUG("mpf do not exit, but do not impact the msg chan.\n"); + } + +#ifdef BAR_MSG_TEST + test_sync_send(); +#endif + + return BAR_MSG_OK; +} + +void bar_chan_timer_callback(struct timer_list *timer) +{ + struct msgid_reps_info *reps_info = NULL; + + reps_info = container_of(timer, struct msgid_reps_info, id_timer); + if (reps_info->flag == REPS_INFO_FLAG_USED) + { + reps_info->reps_buffer = NULL; + reps_info->buffer_len = 0; + reps_info->flag = REPS_INFO_FLAG_USABLE; + BAR_LOG_ERR("RECV ERR: get async reply time out, free msg_id: %u.\n", reps_info->id); + } + else + { + BAR_LOG_DEBUG("RECV NOTICE: get async reply message success.\n"); + } + return; +} + +int zxdh_bar_msg_chan_remove(void) +{ + + bar_msgid_ring_free(); + /* mpf解ioremap*/ + bar_mpf_addr_iounmap(); + /* 消息链表资源释放*/ + + BAR_LOG_DEBUG("zxdh_msg_chan_bar remove success"); + + return 0; +} + +uint16_t bar_get_sum(uint8_t *ptr, uint8_t len) +{ + int idx = 0; + uint64_t sum = 0; + for (idx = 0; idx < len; idx++) + { + sum += *(ptr + idx); + } + return (uint16_t)sum; +} + +/** + * zxdh_bar_enable_chan - 驱动使能通道函数 + * @_msix_para: msix中断配置信息 + * @vport: 查询到的vport + * @return: 0 成功，其他失败 + */ +int zxdh_bar_enable_chan(struct msix_para *_msix_para, uint16_t *vport) +{ + int ret = 0; + uint8_t recv_buf[12] = {0}; + uint16_t check_token, sum_res; +#if 0 + uint32_t domain, bus, devid, function; +#endif + struct msix_msg msix_msg = {0}; + struct zxdh_pci_bar_msg in = {0}; + struct zxdh_msg_recviver_mem result = {0}; + + if (!_msix_para || !_msix_para->pdev) + { + return -BAR_MSG_ERR_NULL; + } +#if 0 + sscanf(pci_name(_msix_para->pdev), "%x:%x:%x.%u", &domain, &bus, &devid, &function); + msix_msg.bdf = BDF_ECAM(bus, devid, function); +#endif + msix_msg.pcie_id = _msix_para->pcie_id; + msix_msg.vector_risc = _msix_para->vector_risc; + msix_msg.vector_pfvf = _msix_para->vector_pfvf; + msix_msg.vector_mpf = _msix_para->vector_mpf; + + in.payload_addr = &msix_msg; + in.payload_len = sizeof(msix_msg); + in.virt_addr = _msix_para->virt_addr; + in.src = _msix_para->driver_type; + in.dst = MSG_CHAN_END_RISC; + in.event_id = MODULE_MSIX; + in.src_pcieid = _msix_para->pcie_id; + + result.recv_buffer = recv_buf; + result.buffer_len = sizeof(recv_buf); + + ret = zxdh_bar_chan_sync_msg_send(&in, &result); + if (ret != BAR_MSG_OK) + { + return -ret; + } + + check_token = *(uint16_t *)(recv_buf + 6); + sum_res = bar_get_sum((uint8_t *)&msix_msg, sizeof(msix_msg)); + if (check_token != sum_res) + { + BAR_LOG_DEBUG("expect token: 0x%x, get token: 0x%x.\n", sum_res, check_token); + return -BAR_MSG_ERR_NOT_MATCH; + } + *vport = *(uint16_t *)(recv_buf + 8); + BAR_LOG_DEBUG("vport of %s get success.\n", pci_name(_msix_para->pdev)); + return BAR_MSG_OK; +} +EXPORT_SYMBOL(zxdh_bar_enable_chan); + +int zxdh_get_bar_offset(struct bar_offset_params *paras, struct bar_offset_res *res) +{ + int ret = 0; + uint16_t check_token, sum_res; + struct offset_get_msg send_msg = {0}; + struct bar_recv_msg *recv_msg = NULL; + + struct zxdh_pci_bar_msg in = {0}; + struct zxdh_msg_recviver_mem result = {0}; + + if (!paras || !res) + { + return BAR_MSG_ERR_NULL; + } + + send_msg.pcie_id = paras->pcie_id; + send_msg.type = paras->type; + + in.payload_addr = &send_msg; + in.payload_len = sizeof(send_msg); + in.virt_addr = paras->virt_addr; + in.src = MSG_CHAN_END_PF; + in.dst = MSG_CHAN_END_RISC; + in.event_id = MODULE_OFFSET_GET; + + recv_msg = kzalloc(sizeof(struct bar_recv_msg), GFP_KERNEL); + if (recv_msg == NULL) + { + LOG_ERR("NULL ptr\n"); + return -1; + } + result.recv_buffer = recv_msg; + result.buffer_len = sizeof(struct bar_recv_msg); + + ret = zxdh_bar_chan_sync_msg_send(&in, &result); + if (ret != BAR_MSG_OK) + { + ret = -ret; + goto free_msg; + } + + check_token = recv_msg->offset_reps.check; + sum_res = bar_get_sum((uint8_t*)&send_msg, sizeof(send_msg)); + if (check_token != sum_res) + { + BAR_LOG_ERR("expect token: 0x%x, get token: 0x%x.\n", sum_res, check_token); + ret = -BAR_MSG_ERR_NOT_MATCH; + goto free_msg; + } + res->bar_offset = recv_msg->offset_reps.offset; + res->bar_length = recv_msg->offset_reps.length; + +free_msg: + kfree(recv_msg); + return ret; +} +EXPORT_SYMBOL(zxdh_get_bar_offset); + +void zxdh_bar_reset_valid(uint64_t subchan_addr) +{ + struct bar_msg_header msg_header = {0}; + + bar_chan_msg_header_get(subchan_addr, &msg_header); + + subchan_addr += BAR_MSG_ADDR_CHAN_INTERVAL; + bar_chan_msg_valid_set(subchan_addr, BAR_MSG_CHAN_USABLE); + bar_chan_msg_poltag_set(subchan_addr, 0); +} +EXPORT_SYMBOL(zxdh_bar_reset_valid); + +uint16_t zxdh_get_event_id(uint64_t subchan_addr, uint8_t src_type, uint8_t dst_type) +{ + uint8_t subchan_id = 0; + struct bar_msg_header msg_header = {0}; + uint8_t src = bar_msg_col_index_trans(src_type); + uint8_t dst = bar_msg_row_index_trans(dst_type); + + if (src == BAR_MSG_SRC_ERR || dst == BAR_MSG_DST_ERR) + { + return 0; + } + /* 接收子通道id和发送子通道相反*/ + subchan_id = (!!subchan_id_tbl[dst][src])? BAR_SUBCHAN_INDEX_SEND : BAR_SUBCHAN_INDEX_RECV; + subchan_addr += subchan_id * BAR_MSG_ADDR_CHAN_INTERVAL; + bar_chan_msg_header_get(subchan_addr, &msg_header); + return msg_header.event_id; +} +EXPORT_SYMBOL(zxdh_get_event_id); + +int32_t zxdh_send_command(uint64_t vaddr, uint16_t pcie_id, uint16_t module_id, \ + void *msg, void *ack, bool is_sync_msg) +{ + struct zxdh_pci_bar_msg in = {0}; + struct zxdh_msg_recviver_mem result = {0}; + struct bar_recv_msg *bar_reps = NULL; + int32_t ret = 0; + + if ((msg == NULL) || (ack == NULL)) + { + LOG_ERR("NULL ptr\n"); + return -1; + } + + in.payload_addr = msg; + in.payload_len = sizeof(union zxdh_msg); + + if (((pcie_id >> PFVF_FLAG_OFFSET) & 1) == 1) + { + in.src = MSG_CHAN_END_PF; + } + else + { + in.src = MSG_CHAN_END_VF; + } + + bar_reps = kzalloc(sizeof(struct bar_recv_msg), GFP_KERNEL); + if (bar_reps == NULL) + { + LOG_ERR("NULL ptr\n"); + return -1; + } + in.dst = MSG_CHAN_END_RISC; + in.event_id = module_id; + in.virt_addr = vaddr; + in.src_pcieid = pcie_id; + result.recv_buffer = bar_reps; + result.buffer_len = BAR_MSG_PAYLOAD_MAX_LEN; + + switch (module_id) + { + case MODULE_VF_BAR_MSG_TO_PF: + { + in.dst = MSG_CHAN_END_PF; + in.dst_pcieid = FIND_PF_PCIE_ID(pcie_id); + in.virt_addr += ZXDH_BAR_PFVF_MSG_OFFSET; + break; + } + case MODULE_PF_BAR_MSG_TO_VF: + { + in.dst = MSG_CHAN_END_VF; + in.dst_pcieid = ((zxdh_msg_info *)msg)->hdr_vf.dst_pcie_id; + in.virt_addr += ZXDH_BAR_PFVF_MSG_OFFSET; + break; + } + case MODULE_TBL: + { + in.payload_len = MSG_STRUCT_HD_LEN + ((zxdh_msg_info *)msg)->hdr_to_cmn.write_bytes; + break; + } + case MODULE_PF_TIMER_TO_RISC_MSG: + { + in.payload_len = MSG_STRUCT_HD_LEN + ((zxdh_msg_info *)msg)->hdr_to_cmn.write_bytes; + break; + } + case MODULE_PHYPORT_QUERY: + { + in.payload_len = sizeof(struct zxdh_port_msg); + break; + } + case MODULE_NPSDK: + { + in.payload_len = sizeof(zxdh_cfg_np_msg); + break; + } + } + + ret = zxdh_bar_chan_sync_msg_send(&in, &result); + if (ret != ZXDH_NET_ACK_OK) + { + LOG_ERR("zxdh_bar_chan_sync_msg_send failed: %d\n", ret); + ret = -ret; + goto free_reps; + } + + if (is_sync_msg && bar_reps->replied != BAR_MSG_REPS_OK) + { + LOG_ERR("reps get failed\n"); + ret = -1; + goto free_reps; + } + + if (bar_reps->reps_len > BAR_MSG_PAYLOAD_MAX_LEN) + { + LOG_ERR("reps len too long\n"); + ret = -1; + goto free_reps; + } + memcpy(ack, bar_reps->data, bar_reps->reps_len); + +free_reps: + kfree(bar_reps); + return ret; +} +EXPORT_SYMBOL(zxdh_send_command); diff --git a/src/net/drivers/net/ethernet/dinghai/dh_procfs.c b/src/net/drivers/net/ethernet/dinghai/dh_procfs.c new file mode 100644 index 0000000..bcd6fba --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/dh_procfs.c @@ -0,0 +1,85 @@ +#include + +#include "dh_procfs.h" + +#define DRV_NAME "dinghai" + +static struct fs_entry_desc fs_entry_table[] = { + { FS_ENTRY_BOND, "lag" }, + {0} +}; + +uint32_t find_fs_entry(uint32_t type) +{ + uint32_t idx = 0; + + while (fs_entry_table[idx].file_name) + { + if (type == fs_entry_table[idx].type) + { + break; + } + idx++; + } + + return idx; +} + +void zxdh_create_proc_dir(struct zxdh_proc_fs *procfs) +{ + if (!procfs->proc_dir) + { + procfs->proc_dir = proc_mkdir(DRV_NAME, NULL); + if (!procfs->proc_dir) + { + pr_warn("Warning: Cannot create /proc/%s\n", DRV_NAME); + } + } +} + +void zxdh_destroy_proc_dir(struct zxdh_proc_fs *procfs) +{ + if (procfs->proc_dir) + { + remove_proc_entry(DRV_NAME, NULL); + procfs->proc_dir = NULL; + } +} + +void zxdh_create_proc_entry(struct zxdh_proc_fs *procfs, + uint32_t type, struct seq_operations *seq_ops, void *data) +{ + uint32_t idx = 0; + char *file_name = NULL; + + if (procfs->proc_dir) + { + idx = find_fs_entry(type); + file_name = fs_entry_table[idx].file_name; + if (file_name && (idx < PROC_ENTRY_MAX)) + { + procfs->proc_entry[idx] = proc_create_seq_data(file_name, 0444, procfs->proc_dir, seq_ops, data); + if (procfs->proc_entry[idx] == NULL) + { + pr_info("Cannot create /proc/%s/%s\n", DRV_NAME, file_name); + } + } + } +} + +void zxdh_remove_proc_entry(struct zxdh_proc_fs *procfs, uint32_t type) +{ + uint32_t idx = 0; + char *file_name = NULL; + + if (procfs->proc_dir) + { + idx = find_fs_entry(type); + file_name = fs_entry_table[idx].file_name; + if (file_name && (idx < PROC_ENTRY_MAX)) + { + remove_proc_entry(file_name, procfs->proc_dir); + procfs->proc_entry[idx] = NULL; + } + } +} diff --git a/src/net/drivers/net/ethernet/dinghai/dh_procfs.h b/src/net/drivers/net/ethernet/dinghai/dh_procfs.h new file mode 100644 index 0000000..6197957 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/dh_procfs.h @@ -0,0 +1,30 @@ +#ifndef _ZXDH_PROC_FS_H_ +#define _ZXDH_PROC_FS_H_ + +#define PROC_ENTRY_MAX (16) + +struct zxdh_proc_fs +{ + struct proc_dir_entry *proc_dir; + struct proc_dir_entry *proc_entry[PROC_ENTRY_MAX]; +}; + +struct fs_entry_desc +{ + uint32_t type; + char *file_name; +}; + +enum +{ + FS_ENTRY_BOND = 0, +}; + +void zxdh_create_proc_dir(struct zxdh_proc_fs *procfs); +void zxdh_destroy_proc_dir(struct zxdh_proc_fs *procfs); +void zxdh_create_proc_entry(struct zxdh_proc_fs *procfs, + uint32_t type, struct seq_operations *seq_ops, void *data); +void zxdh_remove_proc_entry(struct zxdh_proc_fs *procfs, uint32_t type); + + +#endif /* _ZXDH_PROC_FS_H_ */ \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_aux.c b/src/net/drivers/net/ethernet/dinghai/en_aux.c new file mode 100755 index 0000000..b5c64e8 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_aux.c @@ -0,0 +1,4046 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "en_aux.h" +#include "en_ethtool/ethtool.h" +#include "en_np/table/include/dpp_tbl_api.h" +#include "en_np/table/include/dpp_tbl_comm.h" +#include "en_aux/events.h" +#include "en_aux/eq.h" +#include "en_aux/en_cmd.h" +#include "msg_common.h" +#include "en_pf.h" +#include "en_aux/en_ioctl.h" +#include +#ifdef ZXDH_MSGQ +#include "en_aux/priv_queue.h" +#endif +#include "en_aux/en_1588_pkt_proc.h" +#include "en_aux/en_cmd.h" +#include "zxdh_tools/zxdh_tools_netlink.h" +#include + +#ifdef ZXDH_DCBNL_OPEN +#include "en_aux/dcbnl/en_dcbnl.h" +#endif + +uint32_t max_pairs = ZXDH_MQ_PAIRS_NUM; +module_param(max_pairs, uint, S_IRUGO | S_IWUSR); +MODULE_PARM_DESC(max_pairs, "Max queue pairs"); + +MODULE_LICENSE("Dual BSD/GPL"); + +/* WARNING Do not use netif_carrier_on/off(), + it may affect the ethtool function */ +int32_t zxdh_en_open(struct net_device *netdev) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + int32_t i = 0; + int32_t err = 0; + DPP_PF_INFO_T pf_info = {0}; + + LOG_INFO("zxdh_en_open start\n"); + mutex_lock(&en_priv->lock); + + for (i = 0; i < en_dev->curr_queue_pairs; i++) + { + /* Make sure we have some buffers: if oom use wq */ + if (!try_fill_recv(netdev, &en_dev->rq[i], GFP_KERNEL)) + { + schedule_delayed_work(&en_dev->refill, 0); + } + + virtnet_napi_enable(en_dev->rq[i].vq, &en_dev->rq[i].napi); + virtnet_napi_tx_enable(netdev, en_dev->sq[i].vq, &en_dev->sq[i].napi); + } + + mutex_unlock(&en_priv->lock); + + if (!en_dev->link_up) + { + return 0; + } + + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + if (!en_dev->ops->is_bond(en_dev->parent)) + { + if(en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_VF) + { + return zxdh_vf_egr_port_attr_set(en_dev, EGR_FLAG_VPORT_IS_UP, 1, 0); + } + return dpp_egr_port_attr_set(&pf_info, EGR_FLAG_VPORT_IS_UP, 1); + } + + /* 给bond-pf的端口属性表配置为up */ + err = dpp_egr_port_attr_set(&pf_info, EGR_FLAG_VPORT_IS_UP, 1); + if (err != 0) + { + LOG_ERR("dpp_egr_port_attr_set bond pf failed\n"); + return err; + } + + return dpp_panel_attr_set(&pf_info, en_dev->phy_port, PANEL_FLAG_IS_UP, 1); +} + +int32_t zxdh_en_close(struct net_device *netdev) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + int32_t i = 0; + int32_t err = 0; + DPP_PF_INFO_T pf_info = {0}; + + LOG_INFO("zxdh_en_close start\n"); + /* Make sure refill_work doesn't re-enable napi! */ + cancel_delayed_work_sync(&en_dev->refill); + + for (i = 0; i < en_dev->curr_queue_pairs; i++) + { + napi_disable(&en_dev->rq[i].napi); + virtnet_napi_tx_disable(&en_dev->sq[i].napi); + } + + if (!en_dev->link_up) + { + return 0; + } + + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + if (!en_dev->ops->is_bond(en_dev->parent)) + { + if(en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_VF) + { + return zxdh_vf_egr_port_attr_set(en_dev, EGR_FLAG_VPORT_IS_UP, 0, 0); + } + return dpp_egr_port_attr_set(&pf_info, EGR_FLAG_VPORT_IS_UP, 0); + } + + /* 给bond-pf的端口属性表配置为down */ + err = dpp_egr_port_attr_set(&pf_info, EGR_FLAG_VPORT_IS_UP, 0); + if (err != 0) + { + LOG_ERR("dpp_egr_port_attr_set bond pf failed\n"); + return err; + } + + return dpp_panel_attr_set(&pf_info, en_dev->phy_port, PANEL_FLAG_IS_UP, 0); +} + +void pkt_transport_protocol_parse(int8_t next_protocol, struct zxdh_net_hdr *hdr) +{ + if (next_protocol == IPPROTO_UDP) + { + hdr->pi_hdr.pt.type_ctx.pkt_code = PCODE_UDP; + } + else if (next_protocol == IPPROTO_TCP) + { + hdr->pi_hdr.pt.type_ctx.pkt_code = PCODE_TCP; + } + else + { + hdr->pi_hdr.pt.type_ctx.pkt_code = PCODE_IP; + } + + return; +} + +void pkt_protocol_parse(struct sk_buff *skb, struct zxdh_net_hdr *hdr, int32_t flag) +{ + struct ethhdr *mach = NULL; + struct iphdr *ipv4h = NULL; + struct ipv6hdr *ipv6h = NULL; + + if (flag == 0) + { + if (skb->protocol == htons(ETH_P_IP)) + { + ipv4h = (struct iphdr *)skb_network_header(skb); + hdr->pi_hdr.pt.type_ctx.ip_type = IPV4_TYPE; + pkt_transport_protocol_parse(ipv4h->protocol, hdr); + } + else if (skb->protocol == htons(ETH_P_IPV6)) + { + ipv6h = (struct ipv6hdr *)skb_network_header(skb); + hdr->pi_hdr.pt.type_ctx.ip_type = IPV6_TYPE; + pkt_transport_protocol_parse(ipv6h->nexthdr, hdr); + } + else + { + hdr->pi_hdr.pt.type_ctx.ip_type = NOT_IP_TYPE; + } + } + else + { + mach = (struct ethhdr *)skb_inner_mac_header(skb); + if (mach->h_proto == htons(ETH_P_IP)) + { + ipv4h = (struct iphdr *)skb_inner_network_header(skb); + hdr->pi_hdr.pt.type_ctx.ip_type = IPV4_TYPE; + pkt_transport_protocol_parse(ipv4h->protocol, hdr); + } + else if (mach->h_proto == htons(ETH_P_IPV6)) + { + ipv6h = (struct ipv6hdr *)skb_inner_network_header(skb); + hdr->pi_hdr.pt.type_ctx.ip_type = IPV6_TYPE; + pkt_transport_protocol_parse(ipv6h->nexthdr, hdr); + + } + else + { + hdr->pi_hdr.pt.type_ctx.ip_type = NOT_IP_TYPE; + } + } +} + +int32_t pkt_is_vxlan(struct sk_buff *skb) +{ + switch (skb->protocol) + { + case htons(ETH_P_IP): + if (ip_hdr(skb)->protocol != IPPROTO_UDP) + { + return -1; + } + break; + + case htons(ETH_P_IPV6): + if (ipv6_hdr(skb)->nexthdr != IPPROTO_UDP) + { + return -1; + } + break; + + default: + return -1; + } + + if (skb->inner_protocol_type != ENCAP_TYPE_ETHER || skb->inner_protocol != htons(ETH_P_TEB) || + (skb_inner_mac_header(skb) - skb_transport_header(skb) != sizeof(struct udphdr) + sizeof(struct vxlanhdr))) + { + return -1; + } + + return 0; +} + +int32_t zxdh_tx_checksum_offload(struct zxdh_en_device *edev, struct sk_buff *skb, struct zxdh_net_hdr *hdr) +{ + if (skb->ip_summed != CHECKSUM_PARTIAL) + { + return 0; + } + + if ((skb->inner_protocol != 0) && (pkt_is_vxlan(skb) == 0)) + { + skb->encapsulation = 0x1; + } + + if(skb->encapsulation == 0x1) + { + if ((edev->netdev->features & NETIF_F_GSO_UDP_TUNNEL_CSUM) == 0) + { + return 0; + } + hdr->pi_hdr.bttl_pi_len = ENABLE_PI_FLAG_32B; + hdr->pd_hdr.ol_flag |= htons(0x1 << OUTER_IP_CHECKSUM_OFFSET); + pkt_protocol_parse(skb, hdr, 1); + hdr->pi_hdr.hdr_l3_offset = htons(edev->hdr_len + skb_inner_network_offset(skb)); + hdr->pi_hdr.hdr_l4_offset = htons(edev->hdr_len + skb_inner_transport_offset(skb)); + } + + hdr->pi_hdr.pkt_action_flag1 |= htons(0x1 << INNER_IP_CHECKSUM_OFFSET); + hdr->pi_hdr.pkt_action_flag2 |= 0x1 << INNER_L4_CHECKSUM_OFFSET; + return 0; +} + +static int pd_hdr_validate_vlan(struct zxdh_en_device *edev, struct sk_buff *skb, struct zxdh_net_hdr *hdr) +{ + /* pf set vf vlan is done*/ + if (edev->vlan_dev.vlan_id) + { + if (!skb_vlan_tag_present(skb)) + { + hdr->pd_hdr.cvlan.tci = htons(edev->vlan_dev.vlan_id); + hdr->pd_hdr.cvlan.tpid = (edev->vlan_dev.protcol); + hdr->pd_hdr.ol_flag |= htons(TXCAP_CTAG_INSERT_EN_BIT); + return 0; + } + else + { + hdr->pd_hdr.svlan.tci = htons(edev->vlan_dev.vlan_id); + hdr->pd_hdr.svlan.tpid = (edev->vlan_dev.protcol); + hdr->pd_hdr.ol_flag |= htons(TXCAP_STAG_INSERT_EN_BIT); + } + } + + /* insert vlan hard-accellate when skb is taged to be inserted, eg. in vlan interface case*/ + if (skb && skb_vlan_tag_present(skb)) + { + hdr->pd_hdr.cvlan.tci = htons(skb_vlan_tag_get(skb)); + hdr->pd_hdr.cvlan.tpid = (skb->vlan_proto); + hdr->pd_hdr.ol_flag |= htons(TXCAP_CTAG_INSERT_EN_BIT); + } + return 0; +} + + +int32_t pi_net_hdr_from_skb(struct zxdh_en_device *edev, struct sk_buff *skb, struct zxdh_net_hdr *hdr) +{ + uint32_t gso_type = 0; + uint16_t mss = 0; +#ifdef TIME_STAMP_1588 + int32_t ret = 0; +#endif + + memset(hdr, 0, sizeof(*hdr)); /* no info leak */ + hdr->pd_len = edev->hdr_len / HDR_2B_UNIT; + hdr->pi_hdr.bttl_pi_len = DISABLE_PI_FIELD_PARSE + ENABLE_PI_FLAG_32B; + hdr->tx_port = TX_PORT_DTP; + hdr->pi_hdr.pt.type_ctx.pkt_src = PKT_SRC_CPU; + hdr->pi_hdr.eth_port_id = INVALID_ETH_PORT_ID; + + if(edev->delay_statistics_enable) + { + pkt_delay_statistics_proc(skb, hdr, edev); + } + +// #ifdef TIME_STAMP_1588 +// ret = pkt_1588_proc_xmit(skb, hdr, edev->clock_no, edev); +// switch (ret) +// { +// case PTP_SUCCESS: +// { +// LOG_DEBUG("pkt_1588_proc_xmit success!!!\n"); +// return 0; +// } +// case IS_NOT_PTP_MSG: +// { +// LOG_DEBUG("not ptp msg!!\n"); +// break; +// } +// default: +// { +// LOG_ERR("pkt_1588_proc_xmit err!!!\n"); +// return ret; +// } +// } +// #endif + + pd_hdr_validate_vlan(edev, skb, hdr); + + mss = skb_shinfo(skb)->gso_size; + gso_type = skb_shinfo(skb)->gso_type; + if(gso_type & SKB_GSO_TCPV4) + { + mss = (mss > 0) ? min(skb_shinfo(skb)->gso_size, (uint16_t)(edev->netdev->mtu - IP_BASE_HLEN - TCP_BASE_HLEN)) + : (uint16_t)(edev->netdev->mtu - IP_BASE_HLEN - TCP_BASE_HLEN); + hdr->pi_hdr.pkt_action_flag1 |= htons((mss / ETH_MTU_4B_UNIT) + NOT_IP_FRG_CSUM_FLAG); + hdr->pi_hdr.pkt_action_flag2 |= TCP_FRG_CSUM_FLAG; /*0x24 bit21,18: 带pi,tso,计算checksum */ + } + else if(gso_type & SKB_GSO_TCPV6) + { + mss = (mss > 0) ? min(skb_shinfo(skb)->gso_size, (uint16_t)(edev->netdev->mtu - IPV6_BASE_HLEN - TCP_BASE_HLEN)) + : (uint16_t)(edev->netdev->mtu - IPV6_BASE_HLEN - TCP_BASE_HLEN); + hdr->pi_hdr.pkt_action_flag1 |= htons((mss / ETH_MTU_4B_UNIT) + NOT_IP_FRG_CSUM_FLAG); + hdr->pi_hdr.pkt_action_flag2 |= TCP_FRG_CSUM_FLAG; /*0x24 bit21,18: 带pi,tso,计算checksum */ + } + else if(gso_type & (SKB_GSO_UDP | SKB_GSO_UDP_L4 | SKB_GSO_UDP_TUNNEL | SKB_GSO_UDP_TUNNEL_CSUM)) + { + hdr->pi_hdr.pkt_action_flag1 = htons((uint16_t)(edev->netdev->mtu / ETH_MTU_4B_UNIT) + IP_FRG_CSUM_FLAG); + hdr->pi_hdr.pkt_action_flag2 |= NOT_TCP_FRG_CSUM_FLAG; + } + else + { + hdr->pi_hdr.pkt_action_flag1 |= htons((edev->netdev->mtu / ETH_MTU_4B_UNIT) + NOT_IP_FRG_CSUM_FLAG); + hdr->pi_hdr.pkt_action_flag2 |= NOT_TCP_FRG_CSUM_FLAG; + } + + if (edev->netdev->features & NETIF_F_HW_CSUM) + { + zxdh_tx_checksum_offload(edev, skb, hdr); + } + + if ((edev->ops->is_bond(edev->parent)) && + (skb->protocol == htons(ETH_P_SLOW) || skb->protocol == htons(ETH_P_PAUSE))) + { + hdr->pd_hdr.ol_flag |= htons(PANELID_EN); + hdr->pd_hdr.panel_id = edev->phy_port; + } + + #ifdef ZXDH_DCBNL_OPEN + if (NULL != skb->sk) + { + hdr->pd_hdr.ol_flag |= htons(ZXDH_DCBNL_SET_SK_PRIO(skb->sk->sk_priority)); + } + #endif + + +#ifdef TIME_STAMP_1588 + ret = pkt_1588_proc_xmit(skb, hdr, edev->clock_no, edev); + switch (ret) + { + case PTP_SUCCESS: + { + LOG_DEBUG("pkt_1588_proc_xmit success!!!\n"); + return 0; + } + case IS_NOT_PTP_MSG: + { + LOG_DEBUG("not ptp msg!!\n"); + break; + } + default: + { + LOG_ERR("pkt_1588_proc_xmit err!!!\n"); + return ret; + } + } +#endif + return 0; +} + +int32_t xmit_skb(struct net_device *netdev, struct send_queue *sq, struct sk_buff *skb) +{ + struct zxdh_net_hdr *hdr = NULL; + //const unsigned char *dest = ((struct ethhdr *)skb->data)->h_dest; + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + int32_t num_sg = 0; + unsigned hdr_len = en_dev->hdr_len; + bool can_push = false; + uint8_t *hdr_buf = sq->hdr_buf; + + can_push = en_dev->any_header_sg && + !((unsigned long)skb->data & (__alignof__(*hdr) - 1)) && + !skb_header_cloned(skb) && skb_headroom(skb) >= hdr_len; + /* Even if we can, don't push here yet as this would skew + * csum_start offset below. */ + if (can_push) + { + hdr = (struct zxdh_net_hdr *)(skb->data - hdr_len); + } + else + { + memset(hdr_buf, 0, HDR_BUFFER_LEN); + hdr = (struct zxdh_net_hdr *)hdr_buf; + } + + if (pi_net_hdr_from_skb(en_dev, skb, hdr)) + { + return -EPROTO; + } + + sg_init_table(sq->sg, skb_shinfo(skb)->nr_frags + (can_push ? 1 : 2)); + if (can_push) + { + __skb_push(skb, hdr_len); + num_sg = skb_to_sgvec(skb, sq->sg, 0, skb->len); + if (unlikely(num_sg < 0)) + { + return num_sg; + } + /* Pull header back to avoid skew in tx bytes calculations. */ + __skb_pull(skb, hdr_len); + } + else + { + sg_set_buf(sq->sg, hdr, hdr_len); + num_sg = skb_to_sgvec(skb, sq->sg + 1, 0, skb->len); + if (unlikely(num_sg < 0)) + { + return num_sg; + } + num_sg++; + } + + return virtqueue_add_outbuf(sq->vq, sq->sg, num_sg, skb, GFP_ATOMIC); +} + +netdev_tx_t zxdh_en_xmit(struct sk_buff *skb, struct net_device *netdev) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + int32_t qnum = skb_get_queue_mapping(skb); + struct send_queue *sq = &en_dev->sq[qnum]; + int32_t err = 0; + struct netdev_queue *txq = netdev_get_tx_queue(netdev, qnum); + bool kick = !netdev_xmit_more(); + bool use_napi = sq->napi.weight; + + /* Free up any pending old buffers before queueing new ones. */ + do { + if (use_napi) + { + virtqueue_disable_cb(sq->vq); + } + + free_old_xmit_skbs(netdev, sq, false); + + } while (use_napi && kick && unlikely(!virtqueue_enable_cb_delayed(sq->vq))); + + /* timestamp packet in software */ + skb_tx_timestamp(skb); + + /* Try to transmit */ + err = xmit_skb(netdev, sq, skb); + + /* This should not happen! */ + if (unlikely(err)) + { + netdev->stats.tx_fifo_errors++; + netdev->stats.tx_errors++; + if (net_ratelimit()) + { + LOG_WARN("unexpected TXQ (%d) queue failure: %d\n", qnum, err); + } + netdev->stats.tx_dropped++; + dev_kfree_skb_any(skb); + return NETDEV_TX_OK; + } + + /* If running out of space, stop queue to avoid getting packets that we + * are then unable to transmit. + * An alternative would be to force queuing layer to requeue the skb by + * returning NETDEV_TX_BUSY. However, NETDEV_TX_BUSY should not be + * returned in a normal path of operation: it means that driver is not + * maintaining the TX queue stop/start state properly, and causes + * the stack to do a non-trivial amount of useless work. + * Since most packets only take 1 or 2 ring slots, stopping the queue + * early means 16 slots are typically wasted. + */ + if (sq->vq->num_free < 2 + MAX_SKB_FRAGS) + { + netif_stop_subqueue(netdev, qnum); + en_dev->hw_stats.q_stats[qnum].q_tx_stopped++; + if (!use_napi && unlikely(!virtqueue_enable_cb_delayed(sq->vq))) + { + /* More just got used, free them then recheck. */ + free_old_xmit_skbs(netdev, sq, false); + if (sq->vq->num_free >= 2 + MAX_SKB_FRAGS) + { + netif_start_subqueue(netdev, qnum); + virtqueue_disable_cb(sq->vq); + } + } + } + + if (kick || netif_xmit_stopped(txq)) + { + if (virtqueue_kick_prepare_packed(sq->vq) && virtqueue_notify(sq->vq)) + { + u64_stats_update_begin(&sq->stats.syncp); + sq->stats.kicks++; + u64_stats_update_end(&sq->stats.syncp); + } + } + + return NETDEV_TX_OK; +} + +#ifdef HAVE_NDO_GET_STATS64 +#ifdef HAVE_VOID_NDO_GET_STATS64 +static void zxdh_en_get_netdev_stats_struct(struct net_device *netdev, struct rtnl_link_stats64 *stats) +#else +static struct rtnl_link_stats64 *zxdh_en_get_netdev_stats_struct(struct net_device *netdev, struct rtnl_link_stats64 *stats) +#endif +{ +#ifdef HAVE_VOID_NDO_GET_STATS64 + struct zxdh_en_device *en_dev = netdev_priv(netdev); + struct receive_queue *rq = NULL; + struct send_queue *sq = NULL; + uint32_t start = 0; + uint32_t i = 0; + uint64_t tpackets = 0; + uint64_t tbytes = 0; + uint64_t rpackets = 0; + uint64_t rbytes = 0; + uint64_t rdrops = 0; + uint32_t loop_cnt = en_dev->max_queue_pairs; + int32_t ret = 0; + + if (en_dev->ops->is_bond(en_dev->parent)) + { + ret = zxdh_mac_stats_get(en_dev); + if (ret != 0) + { + LOG_ERR("zxdh_mac_stats_get failed, ret: %d\n", ret); + return; + } + + stats->rx_packets = en_dev->hw_stats.phy_stats.rx_packets_phy; + stats->rx_bytes = en_dev->hw_stats.phy_stats.rx_bytes_phy; + stats->rx_errors = en_dev->hw_stats.phy_stats.rx_errors; + stats->rx_dropped = en_dev->hw_stats.phy_stats.rx_discards; + stats->tx_packets = en_dev->hw_stats.phy_stats.tx_packets_phy; + stats->tx_bytes = en_dev->hw_stats.phy_stats.tx_bytes_phy; + stats->tx_errors = en_dev->hw_stats.phy_stats.tx_errors; + stats->tx_dropped = en_dev->hw_stats.phy_stats.tx_drop; + return; + } + +#ifdef ZXDH_MSGQ + NEED_MSGQ(en_dev) + { + loop_cnt--; + } +#endif + + for (i = 0; i < loop_cnt; ++i) + { + sq = &en_dev->sq[i]; + rq = &en_dev->rq[i]; + do + { + start = u64_stats_fetch_begin_irq(&sq->stats.syncp); + tpackets = sq->stats.packets; + tbytes = sq->stats.bytes; + } while (u64_stats_fetch_retry_irq(&sq->stats.syncp, start)); + + do + { + start = u64_stats_fetch_begin_irq(&rq->stats.syncp); + rpackets = rq->stats.packets; + rbytes = rq->stats.bytes; + rdrops = rq->stats.drops; + } while (u64_stats_fetch_retry_irq(&rq->stats.syncp, start)); + + stats->rx_packets += rpackets; + stats->rx_bytes += rbytes; + stats->rx_dropped += rdrops; + stats->tx_packets += tpackets; + stats->tx_bytes += tbytes; + } + + stats->rx_errors = netdev->stats.rx_errors; + stats->tx_errors = netdev->stats.tx_errors; + stats->tx_dropped = netdev->stats.tx_dropped; + stats->tx_carrier_errors = netdev->stats.tx_carrier_errors; + return; +#else + return stats; +#endif +} +#endif/* HAVE_VOID_NDO_GET_STATS_64 */ + +static void zxdh_en_set_rx_mode(struct net_device *netdev) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + + queue_work(en_priv->events->wq, &en_dev->rx_mode_set_work); +} + +void rx_mode_set_handler(struct work_struct *work) +{ + struct zxdh_en_device *en_dev = container_of(work, struct zxdh_en_device, rx_mode_set_work); + bool promisc_changed = false; + bool allmulti_changed = false; + int32_t err = 0; + uint8_t fow = 0; + DPP_PF_INFO_T pf_info = {0}; + + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + ZXDH_AUX_INIT_COMP_CHECK(en_dev); + + if (en_dev->ops->is_bond(en_dev->parent)) + { + return; + } + + promisc_changed = en_dev->netdev->flags & IFF_PROMISC; + allmulti_changed = en_dev->netdev->flags & IFF_ALLMULTI; + if (en_dev->promisc_enabled != promisc_changed) + { + LOG_INFO("promisc_changed: %d", promisc_changed); + if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) + { + dpp_vport_uc_promisc_set(&pf_info, promisc_changed); + if (!en_dev->allmulti_enabled) + { + dpp_vport_mc_promisc_set(&pf_info, promisc_changed); + } + } + else + { + if (!en_dev->allmulti_enabled) + { + fow = 1; + } + err = zxdh_vf_port_promisc_set(en_dev, ZXDH_PROMISC_MODE, promisc_changed, fow); + if (err != 0) + { + LOG_ERR("zxdh_vf_port_promisc_set failed\n"); + return; + } + } + en_dev->promisc_enabled = promisc_changed; + } + + if (en_dev->allmulti_enabled != allmulti_changed) + { + LOG_INFO("allmulti_changed: %d", allmulti_changed); + if (!en_dev->promisc_enabled) + { + if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) + { + dpp_vport_mc_promisc_set(&pf_info, allmulti_changed); + } + else + { + err = zxdh_vf_port_promisc_set(en_dev, ZXDH_ALLMULTI_MODE, allmulti_changed, fow); + if (err != 0) + { + LOG_ERR("zxdh_vf_port_promisc_set failed\n"); + return; + } + } + } + en_dev->allmulti_enabled = allmulti_changed; + } +} + +static int zxdh_en_bar_cfg_mac(struct net_device *netdev, const char *mac) +{ + int ret = 0; + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + union zxdh_msg msg = {0}; + + memcpy(msg.payload.mac_cfg_msg.ifname, netdev->name, IFNAMSIZ); + memcpy(msg.payload.mac_cfg_msg.mac, mac, ETH_ALEN); + msg.payload.mac_cfg_msg.pannel_id = en_dev->panel_id; + + if (en_dev->ops->is_bond(en_dev->parent)) + { + msg.payload.mac_cfg_msg.pannel_id = en_dev->pannel_id; + } + msg.payload.mac_cfg_msg.ctl = 1; + + ret = zxdh_send_command_to_specify(en_dev, MODULE_CFG_MAC, &msg, &msg); + if (ret != 0 || msg.reps.flag != ZXDH_REPS_SUCC) + { + LOG_ERR("config mac info failed\n"); + return -msg.reps.flag; + } + return 0; +} + +static int zxdh_en_bar_del_mac(struct net_device *netdev) +{ + int ret = 0; + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + union zxdh_msg msg = {0}; + + msg.payload.mac_cfg_msg.pannel_id = en_dev->panel_id; + + if (en_dev->ops->is_bond(en_dev->parent)) + { + msg.payload.mac_cfg_msg.pannel_id = en_dev->pannel_id; + } + msg.payload.mac_cfg_msg.ctl = 0; + + ret = zxdh_send_command_to_specify(en_dev, MODULE_CFG_MAC, &msg, &msg); + if (ret != 0 || msg.reps.flag != ZXDH_REPS_SUCC) + { + LOG_ERR("del mac info failed.\n"); + return -msg.reps.flag; + } + return 0; +} + +static int zxdh_en_set_mac(struct net_device *netdev, void *p) +{ + struct sockaddr *addr = (struct sockaddr *)p; + struct zxdh_en_device *en_dev = NULL; + struct zxdh_en_priv *en_priv = NULL; + struct netdev_hw_addr *ha = NULL; + bool delete_flag = true; + bool add_flag = true; + int32_t ret = 0; + DPP_PF_INFO_T pf_info = {0}; + + if (!is_valid_ether_addr(addr->sa_data)) + { + LOG_INFO("invalid mac address %pM\n", addr->sa_data); + return -EADDRNOTAVAIL; + } + + if (ether_addr_equal(netdev->dev_addr, addr->sa_data)) + { + LOG_INFO("already using mac address %pM\n", addr->sa_data); + return 0; + } + + list_for_each_entry(ha, &netdev->uc.list, list) + { + if (!memcmp(ha->addr, netdev->dev_addr, netdev->addr_len)) + { + delete_flag = false; + } + + if (!memcmp(ha->addr, addr->sa_data, netdev->addr_len)) + { + add_flag = false; + } + } + + en_priv = netdev_priv(netdev); + en_dev = &en_priv->edev; + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + + if (en_dev->ops->is_bond(en_dev->parent)) + { + ether_addr_copy(netdev->dev_addr, addr->sa_data); + zxdh_en_bar_del_mac(netdev); + zxdh_en_bar_cfg_mac(netdev, netdev->dev_addr); + return 0; + } + + if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) + { + if (delete_flag) + { + ret = dpp_del_mac(&pf_info, netdev->dev_addr); + if (ret != 0) + { + LOG_ERR("pf del mac failed, retval: %d\n", ret); + return ret; + } + } + + if (add_flag) + { + ret = dpp_add_mac(&pf_info, addr->sa_data); + if (ret != 0) + { + LOG_ERR("pf add mac failed: %d\n", ret); + return ret; + } + } + + LOG_INFO("set pf new mac address %pM\n", addr->sa_data); + ether_addr_copy(netdev->dev_addr, addr->sa_data); + if (!en_dev->ops->is_upf(en_dev->parent)) + { + zxdh_en_bar_del_mac(netdev); + zxdh_en_bar_cfg_mac(netdev, netdev->dev_addr); + } + } + else + { + ret = zxdh_vf_dpp_del_mac(en_dev, netdev->dev_addr, UNFILTER_MAC, delete_flag); + if (ret != 0) + { + LOG_ERR("zxdh vf dpp del mac failed: %d\n", ret); + return ret; + } + + if (add_flag) + { + ret = zxdh_vf_dpp_add_mac(en_dev, addr->sa_data, UNFILTER_MAC); + if (ret != 0) + { + LOG_ERR("zxdh vf dpp add mac failed: %d\n", ret); + return ret; + } + en_dev->ops->set_mac(en_dev->parent, addr->sa_data); + } + + LOG_INFO("set vf new mac address %pM\n", addr->sa_data); + ether_addr_copy(netdev->dev_addr, addr->sa_data); + } + + return ret; +} + +int32_t zxdh_en_config_mtu_to_np(struct net_device *netdev, int32_t mtu_value) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + int32_t ret = 0; + DPP_PF_INFO_T pf_info = {0}; + + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + + if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) + { + dpp_panel_attr_set(&pf_info, en_dev->phy_port, PANEL_FLAG_MTU_OFFLOAD_ENABLE, 1); + dpp_panel_attr_set(&pf_info, en_dev->phy_port, PANEL_FLAG_MTU, mtu_value); + dpp_egr_port_attr_set(&pf_info, EGR_FLAG_MTU_OFFLOAD_EN_OFF, 1); + dpp_egr_port_attr_set(&pf_info, EGR_FLAG_MTU, mtu_value); + } + else + { + ret = zxdh_vf_egr_port_attr_set(en_dev, EGR_FLAG_MTU_OFFLOAD_EN_OFF, 1, 0); + if (ret != 0) + { + LOG_ERR("zxdh_vf_egr_port_attr_set config mtu enable failed: %d\n", ret); + return ret; + } + ret = zxdh_vf_egr_port_attr_set(en_dev, EGR_FLAG_MTU, mtu_value, 0); + if (ret != 0) + { + LOG_ERR("zxdh_vf_egr_port_attr_set config mut value failed: %d\n", ret); + return ret; + } + } + + return 0; +} + +static int zxdh_en_change_mtu(struct net_device *netdev, int new_mtu) +{ + int32_t ret = 0; + + if ((new_mtu < ETH_MIN_MTU) || (new_mtu > ZXDH_MAX_MTU)) + { + return -EINVAL; + } + LOG_INFO("changing MTU from %d to %d\n", netdev->mtu, new_mtu); + + netdev->mtu = new_mtu; + + ret = zxdh_en_config_mtu_to_np(netdev, new_mtu); + if (ret != 0) + { + LOG_ERR("zxdh_en_config_mtu_to_np failed: %d\n", ret); + return ret; + } + + return 0; +} + +#ifdef HAVE_TX_TIMEOUT_TXQUEUE +static void zxdh_en_tx_timeout(struct net_device *netdev, unsigned int txqueue) +{ + return; +} +#else +static void zxdh_en_tx_timeout(struct net_device *netdev) +{ + return; +} +#endif + +#ifdef HAVE_VLAN_RX_REGISTER +static void zxdh_en_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp) +{ + return; +} +#endif + +static int __attribute__((unused)) vf_vlan_rx_add_vid(struct net_device *netdev, u16 vid) +{ + int ret = 0; + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + union zxdh_msg msg = {0}; + + msg.payload.hdr.op_code = ZXDH_VLAN_FILTER_ADD; + msg.payload.hdr.vport = en_dev->vport; + msg.payload.hdr.pcie_id = en_dev->pcie_id; + msg.payload.rx_vid_add_msg.vlan_id = vid; + + ret = zxdh_send_command_to_specify(en_dev, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg); + if (ret != 0 || msg.reps.flag != ZXDH_REPS_SUCC) + { + LOG_ERR("pcieid:0x%x send msg to pf add vlan:%d failed! ret = %d, flag = 0x%x\n", + en_dev->pcie_id, + vid, + ret, + msg.reps.flag); + return -1; + } + + return 0; +} + +#if defined(HAVE_INT_NDO_VLAN_RX_ADD_VID) && defined(NETIF_F_HW_VLAN_CTAG_RX) +static int zxdh_en_vlan_rx_add_vid(struct net_device *netdev, __always_unused __be16 proto, u16 vid) +{ + int retval = 0; +#if 0 + struct zxdh_en_priv *zxdev = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &zxdev->edev; + uint16_t pcieid = en_dev->pcie_id; + + if (vid > MAX_VLAN_ID) + { + LOG_ERR("vlan id:%d input is err!\n", vid); + return -EINVAL; + } + + if ((pcieid & PF_AC_MASK) == 0) /* VF */ + { + retval = vf_vlan_rx_add_vid(netdev, vid); + goto exit; + } + + retval = dpp_add_vlan_filter(zxdev->edev.vport, vid); + if (0 != retval) + { + LOG_ERR("failed to add vlan: %d\n",vid); + goto exit; + } + LOG_INFO("pf add vlan %d succeed.\n", vid); + +exit: +#endif + return retval; +} +#elif defined(HAVE_INT_NDO_VLAN_RX_ADD_VID) && !defined(NETIF_F_HW_VLAN_CTAG_RX) +static int zxdh_en_vlan_rx_add_vid(struct net_device *netdev, u16 vid) +{ + return 0; +} +#else +static void zxdh_en_vlan_rx_add_vid(struct net_device *netdev, u16 vid) +{ + return; +} +#endif + +static int vf_vlan_rx_del_vid(struct net_device *netdev, u16 vid) +{ + int ret = 0; + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + union zxdh_msg msg = {0}; + + msg.payload.hdr.op_code = ZXDH_VLAN_FILTER_DEL; + msg.payload.hdr.vport = en_dev->vport; + msg.payload.hdr.pcie_id = en_dev->pcie_id; + msg.payload.rx_vid_del_msg.vlan_id = vid; + + ret = zxdh_send_command_to_specify(en_dev, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg); + if (ret != 0 || msg.reps.flag != ZXDH_REPS_SUCC) + { + LOG_ERR("pcieid:0x%x send msg to pf del vlan:%d failed! ret = %d, flag = 0x%x\n", + en_dev->pcie_id, + vid, + ret, + msg.reps.flag); + return -1; + } + + return 0; +} + + +#if defined(HAVE_INT_NDO_VLAN_RX_ADD_VID) && defined(NETIF_F_HW_VLAN_CTAG_RX) +static int zxdh_en_vlan_rx_kill_vid(struct net_device *netdev, __always_unused __be16 proto, u16 vid) +{ + int retval = 0; + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + uint16_t pcieid = en_dev->pcie_id; + DPP_PF_INFO_T pf_info = {0}; + + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + + if (vid > MAX_VLAN_ID) + { + LOG_ERR("vlan id:%d input is err!\n", vid); + return -EINVAL; + } + + if ((pcieid & PF_AC_MASK) == 0) /* VF */ + { + retval = vf_vlan_rx_del_vid(netdev, vid); + goto exit; + } + + retval = dpp_del_vlan_filter(&pf_info, vid); + if (0 != retval) + { + LOG_ERR("failed to del vlan: %d\n", vid); + goto exit; + } + LOG_INFO("pf del vlan %d succeed.\n", vid); + +exit: + return retval; +} +#elif defined(HAVE_INT_NDO_VLAN_RX_ADD_VID) && !defined(NETIF_F_HW_VLAN_CTAG_RX) +static int zxdh_en_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) +{ + return 0; +} +#else +static void zxdh_en_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) +{ + return; +} +#endif + +static void zxdh_en_netpoll(struct net_device *netdev) +{ + return; +} + +#ifdef HAVE_SETUP_TC +int zxdh_en_setup_tc(struct net_device *netdev, u8 tc) +{ + return 0; +} + +#ifdef NETIF_F_HW_TC +#ifdef HAVE_NDO_SETUP_TC_REMOVE_TC_TO_NETDEV +static int __zxdh_en_setup_tc(struct net_device *netdev, enum tc_setup_type type, void *type_data) +#elif defined(HAVE_NDO_SETUP_TC_CHAIN_INDEX) +static int __zxdh_en_setup_tc(struct net_device *netdev, u32 handle, + u32 chain_index, __be16 proto, + struct tc_to_netdev *tc) +#else +static int __zxdh_en_setup_tc(struct net_device *netdev, u32 handle, __be16 proto, + struct tc_to_netdev *tc) +#endif +{ + return 0; +} +#endif +#endif + +#ifdef HAVE_NDO_GET_PHYS_PORT_ID +static int zxdh_en_get_phys_port_id(struct net_device *netdev, struct netdev_phys_item_id *ppid) +{ + return 0; +} +#endif /* HAVE_NDO_GET_PHYS_PORT_ID */ + + +static void zxdh_set_en_device(struct net_device *netdev, netdev_features_t features) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + + if ((features & NETIF_F_GSO) || (features & NETIF_F_GSO_UDP) || (features & NETIF_F_GSO_UDP_L4)) + { + en_dev->drs_offload = true; + } + else if ((features & NETIF_F_TSO) || (features & NETIF_F_HW_CSUM)) + { + en_dev->dtp_offload = true; + } + else + { + en_dev->np_direction = true; + } + + return; +} + +static int zxdh_handle_feature(struct net_device *netdev, + netdev_features_t *features, + netdev_features_t wanted_features, + netdev_features_t feature, + zxdh_feature_handler feature_handler) +{ + netdev_features_t changes = wanted_features ^ netdev->features; + bool enable = !!(wanted_features & feature); + int err; + + if (!(changes & feature) || feature_handler == NULL) + { + return 0; + } + + err = feature_handler(netdev, enable); + if (err) + { + LOG_ERR("%s feature %pNF failed, err %d\n", + enable ? "Enable" : "Disable", &feature, err); + return err; + } + + ZXDH_SET_FEATURE(features, feature, enable); + return 0; +} + +static int32_t zxdh_dtp_offload_set(struct zxdh_en_device *en_dev, DPP_PF_INFO_T *pf_info) +{ + ZXDH_VPORT_T port_attr_entry = {0}; + int32_t ret = 0; + + if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) + { + ret = dpp_egr_port_attr_get(pf_info, &port_attr_entry); + if (ret != 0) + { + LOG_ERR("dpp_egr_port_attr_get failed: %d\n", ret); + return ret; + } + + if (!port_attr_entry.lro_offload && !port_attr_entry.ip_fragment_offload && + !port_attr_entry.ip_checksum_offload && !port_attr_entry.tcp_udp_checksum_offload) + { + ret = dpp_egr_port_attr_set(pf_info, EGR_FLAG_ACCELERATOR_OFFLOAD_FLAG, 0); + } + else + { + ret = dpp_egr_port_attr_set(pf_info, EGR_FLAG_ACCELERATOR_OFFLOAD_FLAG, 1); + } + + return ret; + } + + ret = zxdh_vf_egr_port_attr_get(en_dev, &port_attr_entry); + if (ret != 0) + { + LOG_ERR("dpp_egr_port_attr_get failed: %d\n", ret); + return ret; + } + + if (!port_attr_entry.lro_offload && !port_attr_entry.ip_fragment_offload && + !port_attr_entry.ip_checksum_offload && !port_attr_entry.tcp_udp_checksum_offload) + { + ret = zxdh_vf_egr_port_attr_set(en_dev, EGR_FLAG_ACCELERATOR_OFFLOAD_FLAG, 0, 0); + } + else + { + ret = zxdh_vf_egr_port_attr_set(en_dev, EGR_FLAG_ACCELERATOR_OFFLOAD_FLAG, 1, 0); + } + + return ret; +} + +static int32_t set_feature_rx_checksum(struct net_device *netdev, bool enable) +{ + int en_value = enable ? 1 : 0; + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + DPP_PF_INFO_T pf_info = {0}; + int32_t ret = 0; + + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + + if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) + { + ret = dpp_egr_port_attr_set(&pf_info, EGR_FLAG_IP_CHKSUM, enable); + if (ret != 0) + { + LOG_ERR("EGR_FLAG_IP_CHKSUM set failed: %d\n", ret); + return ret; + } + ret = dpp_egr_port_attr_set(&pf_info, EGR_FLAG_TCP_UDP_CHKSUM, enable); + if (ret != 0) + { + LOG_ERR("EGR_FLAG_TCP_UDP_CHKSUM set failed: %d\n", ret); + return ret; + } + } + else if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_VF) + { + ret = zxdh_vf_egr_port_attr_set(en_dev, EGR_FLAG_IP_CHKSUM, en_value, 0); + if (ret != 0) + { + LOG_ERR("EGR_FLAG_IP_CHKSUM set failed: %d\n", ret); + return ret; + } + ret = zxdh_vf_egr_port_attr_set(en_dev, EGR_FLAG_TCP_UDP_CHKSUM, en_value, 0); + if (ret != 0) + { + LOG_ERR("EGR_FLAG_TCP_UDP_CHKSUM set failed: %d\n", ret); + return ret; + } + } + + return zxdh_dtp_offload_set(en_dev, &pf_info); +} + +static int set_feature_tx_checksum(struct net_device *netdev, bool enable) +{ + if (enable) + { + netdev->features |= NETIF_F_HW_CSUM; + } + else + { + netdev->features &= ~NETIF_F_HW_CSUM; + } + return 0; +} + +static int set_feature_vxlan_checksum(struct net_device *netdev, bool enable) +{ + int ret = 0; + int en_value = enable ? 1 : 0; + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + DPP_PF_INFO_T pf_info = {0}; + + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + + if (enable) + { + netdev->features |= NETIF_F_GSO_UDP_TUNNEL_CSUM; + } + else + { + netdev->features &= ~NETIF_F_GSO_UDP_TUNNEL_CSUM; + } + + if(en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) + { + ret = dpp_egr_port_attr_set(&pf_info, EGR_FLAG_OUTER_IP_CHECKSUM_OFFLOAD, enable); + if (ret != 0) + { + LOG_ERR("zxdh set vxlan rx checksum failed!\n"); + return ret; + } + } + else if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_VF) + { + ret = zxdh_vf_egr_port_attr_set(en_dev, EGR_FLAG_OUTER_IP_CHECKSUM_OFFLOAD, en_value, 0); + if (ret != 0) + { + LOG_ERR("zxdh_vf_egr_port_attr_set vxlan rx checksum failed!\n"); + return ret; + } + } + + return ret; +} + +static int32_t set_feature_rxhash(struct net_device *netdev, bool enable) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + DPP_PF_INFO_T pf_info = {0}; + + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + if(en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) + { + return dpp_vport_rss_en_set(&pf_info, enable); + } + + return zxdh_vf_rss_en_set(en_dev, enable); +} + +static int32_t set_vf_cvlan_filter(struct net_device *netdev, bool enable) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + union zxdh_msg msg = {0}; + int32_t ret = 0; + + msg.payload.hdr.op_code = ZXDH_VLAN_FILTER_SET; + msg.payload.hdr.vport = en_dev->vport; + msg.payload.hdr.pcie_id = en_dev->pcie_id; + msg.payload.vlan_filter_set_msg.enable = enable; + + ret = zxdh_send_command_to_specify(en_dev, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg); + if (ret != 0 || msg.reps.flag != ZXDH_REPS_SUCC) + { + LOG_ERR("pcieid:0x%x send msg to pf set vlan filter enable:%s failed! ret = %d, flag = 0x%x\n", + en_dev->pcie_id, + enable ? "enable":"disable", + ret, + msg.reps.flag); + return -1; + } + + return 0; +} + +static int __attribute__((unused)) set_feature_cvlan_filter(struct net_device *netdev, bool enable) +{ + int ret = 0; + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + uint16_t pcieid = en_dev->pcie_id; + DPP_PF_INFO_T pf_info = {0}; + + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + + if ((pcieid & PF_AC_MASK) == 0) /* VF */ + { + ret = set_vf_cvlan_filter(netdev, enable); + goto exit; + } + + ret = dpp_vport_vlan_filter_en_set(&pf_info, enable); + +exit: + return ret; +} + +static int __attribute__((unused)) set_feature_svlan_filter(struct net_device *netdev, bool enable) +{ + int ret = 0; +#if 0 //TODO：STAG 暂时没有设置 + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + + ret = dpp_vport_vlan_qinq_en_set(en_dev->vport, enable); +#endif + return ret; +} + +int set_vf_qinq_tpid(struct net_device *netdev, uint16_t tpid) +{ + int ret = 0; + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + union zxdh_msg msg = {0}; + + msg.payload.hdr.op_code = ZXDH_SET_TPID; + msg.payload.hdr.vport = en_dev->vport; + msg.payload.tpid_cfg_msg.tpid = tpid; + + ret = zxdh_send_command_to_specify(en_dev, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg); + if (ret != 0 || msg.reps.flag != ZXDH_REPS_SUCC) + { + LOG_ERR("pcieid:0x%x send msg to vfs set tpid: 0x%x failed! ret = %d.\n", + en_dev->pcie_id, + tpid, + ret); + return -EINVAL; + } + + return 0; +} + +static int set_vf_vlan_strip(struct net_device *netdev, bool enable, uint8_t flag) +{ + int ret = 0; + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + union zxdh_msg msg = {0}; + + msg.payload.hdr.op_code = ZXDH_VLAN_OFFLOAD_SET; + msg.payload.hdr.vport = en_dev->vport; + msg.payload.hdr.pcie_id = en_dev->pcie_id; + msg.payload.vlan_strip_msg.enable = enable; + msg.payload.vlan_strip_msg.flag = flag; + + ret = zxdh_send_command_to_specify(en_dev, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg); + if (ret != 0 || msg.reps.flag != ZXDH_REPS_SUCC) + { + LOG_ERR("pcieid:0x%x send msg to vfs set vlan strip enable:%s failed! ret = %d, flag = 0x%x\n", + en_dev->pcie_id, + enable ? "enable":"disable", + ret, + msg.reps.flag); + return -EINVAL; + } + + return 0; +} + +static int set_feature_vlan_strip(struct net_device *netdev, bool enable) +{ + int ret = 0; + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + DPP_PF_INFO_T pf_info = {0}; + + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + + if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) + { + ret = dpp_vport_vlan_strip_set(&pf_info, enable); + } + else + { + ret = set_vf_vlan_strip(netdev, enable, VLAN_STRIP_MSG_TYPE); + } + + return ret; +} + + +static int set_feature_qinq_strip(struct net_device *netdev, bool enable) +{ + int ret = 0; + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + DPP_PF_INFO_T pf_info = {0}; + + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + + if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) + { + ret = dpp_vport_vlan_qinq_en_set(&pf_info, enable); + } + else + { + ret = set_vf_vlan_strip(netdev, enable, QINQ_STRIP_MSG_TYPE); + } + + return ret; +} + + +static int32_t set_feature_lro(struct net_device *netdev, bool enable) +{ + uint32_t en_value = enable ? 1 : 0; + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + DPP_PF_INFO_T pf_info = {0}; + int32_t ret = 0; + + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) + { + dpp_egr_port_attr_set(&pf_info, EGR_FLAG_IPV4_TCP_ASSEMBLE, en_value); + if (ret != 0) + { + LOG_ERR("EGR_FLAG_IPV4_TCP_ASSEMBLE set failed: %d\n", ret); + return ret; + } + dpp_egr_port_attr_set(&pf_info, EGR_FLAG_IPV6_TCP_ASSEMBLE, en_value); + if (ret != 0) + { + LOG_ERR("EGR_FLAG_IPV6_TCP_ASSEMBLE set failed: %d\n", ret); + return ret; + } + } + else + { + zxdh_vf_egr_port_attr_set(en_dev, EGR_FLAG_IPV4_TCP_ASSEMBLE, en_value, 0); + if (ret != 0) + { + LOG_ERR("EGR_FLAG_IPV4_TCP_ASSEMBLE set failed: %d\n", ret); + return ret; + } + zxdh_vf_egr_port_attr_set(en_dev, EGR_FLAG_IPV6_TCP_ASSEMBLE, en_value, 0); + if (ret != 0) + { + LOG_ERR("EGR_FLAG_IPV6_TCP_ASSEMBLE set failed: %d\n", ret); + return ret; + } + } + + return zxdh_dtp_offload_set(en_dev, &pf_info); +} + +int32_t zxdh_en_set_features(struct net_device *netdev, netdev_features_t wanted_features) +{ + int32_t ret = 0; + netdev_features_t oper_features = netdev->features; + + zxdh_set_en_device(netdev, wanted_features); + +#define ZXDH_HANDLE_FEATURE(set_feature, handler) \ + zxdh_handle_feature(netdev, &oper_features, wanted_features, set_feature, handler) + + ret |= ZXDH_HANDLE_FEATURE(NETIF_F_RXCSUM, set_feature_rx_checksum); + ret |= ZXDH_HANDLE_FEATURE(NETIF_F_HW_CSUM, set_feature_tx_checksum); + ret |= ZXDH_HANDLE_FEATURE(NETIF_F_GSO_UDP_TUNNEL_CSUM, set_feature_vxlan_checksum); + ret |= ZXDH_HANDLE_FEATURE(NETIF_F_RXHASH, set_feature_rxhash); + ret |= ZXDH_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro); + ret |= ZXDH_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_vlan_strip); + ret |= ZXDH_HANDLE_FEATURE(NETIF_F_HW_VLAN_STAG_RX, set_feature_qinq_strip); + + if (ret) + { + netdev->features = oper_features; + return -EINVAL; + } + + return 0; +} + +static uint32_t list_hw_addr_create(struct netdev_hw_addr_list *list, \ + const uint8_t *addr, int32_t addr_len, \ + uint8_t addr_type, bool global, \ + bool sync) +{ + struct netdev_hw_addr *ha = NULL; + + ha = kzalloc(sizeof(struct netdev_hw_addr), GFP_KERNEL); + if (ha == NULL) + { + LOG_ERR("Kzalloc struct netdev_hw_addr failed \n"); + return 1; + } + + /* 结构体赋值 */ + memcpy(ha->addr, addr, addr_len); + ha->type = addr_type; + ha->refcount = 1; /* 引用计数 */ + ha->global_use = global; + ha->synced = sync ? 1 : 0; + ha->sync_cnt = 0; + list_add_tail_rcu(&ha->list, &list->list); + list->count++; /* 链表节点加1 */ + + return 0; +} + +static uint32_t list_hw_addr_del(struct netdev_hw_addr_list *list, struct netdev_hw_addr *ha) +{ + int32_t refcount = ha->refcount; + + /* 引用的计数大于1，则不能删除此mac地址 */ + if (--refcount) + { + return 1; + } + + /* 从链表中删除此条目 */ + list_del_rcu(&ha->list); + + /* 释放ha结构体占用内存，rcu_head可以安全地释放ha占用的内存*/ + kfree_rcu(ha, rcu_head); + list->count--; + + return 0; +} + +bool is_this_mac_exist(struct net_device *netdev, const uint8_t *addr) +{ + struct netdev_hw_addr *ha = NULL; + bool isexist = false; + + /* 给net_device结构体上锁 */ + netif_addr_lock_bh(netdev); + + /* 判断此mac地址类型 */ + if (is_unicast_ether_addr(addr)) + { + /* 遍历单播mac地址链表 */ + list_for_each_entry(ha, &netdev->uc.list, list) + { + /* 检查该单播地址链表中是否存在此mac，且此mac地址标志为单播 */ + if ((!memcmp(ha->addr, addr, netdev->addr_len)) \ + && (ha->type == NETDEV_HW_ADDR_T_UNICAST)) + { + isexist = true; + goto out; + } + } + } + else + { + /* 遍历组播mac地址链表 */ + list_for_each_entry(ha, &netdev->mc.list, list) + { + /* 检查该组播地址链表中是否存在此mac，且此mac地址类型为组播 */ + if ((!memcmp(ha->addr, addr, netdev->addr_len)) \ + && (ha->type == NETDEV_HW_ADDR_T_MULTICAST)) + { + isexist = true; + goto out; + } + } + } + +out: + /* 给net_device结构体释放锁 */ + netif_addr_unlock_bh(netdev); + + return isexist; +} + +/** + * zxdh_dev_list_addr_add - 在地址链表中添加此mac地址 + * @netdev: 网络设备结构体 + * @addr: 要添加的mac地址 + * @addr_type: mac地址类型 + */ +int32_t zxdh_dev_list_addr_add(struct net_device *netdev, const uint8_t *addr) +{ + int32_t err = 0; + + /* 给net_device结构体上锁 */ + netif_addr_lock_bh(netdev); + + /* 判断此mac地址类型 */ + if (is_unicast_ether_addr(addr)) + { + /* 将此mac地址添加到地址链表中 */ + err = list_hw_addr_create(&netdev->uc, addr, netdev->addr_len, \ + NETDEV_HW_ADDR_T_UNICAST, false, false); + if (err != 0) + { + LOG_ERR("list_hw_addr_create failed\n"); + } + } + else + { + err = list_hw_addr_create(&netdev->mc, addr, netdev->addr_len, \ + NETDEV_HW_ADDR_T_MULTICAST, false, false); + if (err != 0) + { + LOG_ERR("list_hw_addr_create failed\n"); + } + } + + /* 给net_device结构体释放锁 */ + netif_addr_unlock_bh(netdev); + + return err; +} + +/** + * zxdh_dev_list_addr_del - 在地址链表中删除此mac地址 + * @netdev: 网络设备结构体 + * @addr: 要删除的mac地址 + * @addr_type: mac地址类型 + */ +int32_t zxdh_dev_list_addr_del(struct net_device *netdev, const uint8_t *addr) +{ + struct netdev_hw_addr *ha = NULL; + int32_t err = 0; + + /* 给net_device上锁 */ + netif_addr_lock_bh(netdev); + + if (is_unicast_ether_addr(addr)) + { + /* 遍历单播mac地址链表 */ + list_for_each_entry(ha, &netdev->uc.list, list) + { + /* 检查该单播地址链表中是否存在此mac，且此mac地址标志为单播 */ + if ((!memcmp(ha->addr, addr, netdev->addr_len)) \ + && (ha->type == NETDEV_HW_ADDR_T_UNICAST)) + { + /* 从单播地址链表中删除此mac */ + err = list_hw_addr_del(&netdev->uc, ha); + if (err != 0) + { + LOG_ERR("list_hw_addr_del failed\n"); + } + goto out; + } + } + } + else + { + /* 遍历组播mac地址链表 */ + list_for_each_entry(ha, &netdev->mc.list, list) + { + /* 检查该组播地址链表中是否存在此mac，且此mac地址标志为组播 */ + if ((!memcmp(ha->addr, addr, netdev->addr_len)) \ + && (ha->type == NETDEV_HW_ADDR_T_MULTICAST)) + { + /* 从组播地址链表中删除此mac */ + err = list_hw_addr_del(&netdev->mc, ha); + if (err != 0) + { + LOG_ERR("list_hw_addr_del failed\n"); + } + goto out; + } + } + } + +out: + /* 给net_device结构体释放锁 */ + netif_addr_unlock_bh(netdev); + + return err; +} + +#ifdef MAC_CONFIG_DEBUG +int32_t zxdh_pf_dump_all_mac(struct zxdh_en_device *en_dev) +{ + MAC_VPORT_INFO *unicast_mac_arry = NULL; + MAC_VPORT_INFO *multicast_mac_arry = NULL; + uint32_t current_unicast_num = 0; + uint32_t current_multicast_num = 0; + int32_t err = 1; + int32_t i = 0; + DPP_PF_INFO_T pf_info = {0}; + + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + + /* 开辟单播数组和组播数组*/ + unicast_mac_arry = (MAC_VPORT_INFO *)kzalloc(sizeof(MAC_VPORT_INFO)*UNICAST_MAX_NUM, GFP_KERNEL); + if (unicast_mac_arry == NULL) + { + LOG_ERR("kzalloc unicast_mac_arry failed \n"); + return err; + } + + multicast_mac_arry = (MAC_VPORT_INFO *)kzalloc(sizeof(MAC_VPORT_INFO)*MULTICAST_MAX_NUM, GFP_KERNEL); + if (multicast_mac_arry == NULL) + { + LOG_ERR("kzalloc multicast_mac_arry failed \n"); + goto out1; + } + + /* 从NP中dump所有单播mac地址*/ + err = dpp_unicast_mac_dump(&pf_info, unicast_mac_arry, ¤t_unicast_num); + if (err != 0) + { + LOG_ERR("dpp_unicast_mac_dump failed\n"); + goto out2; + } + + /* 从NP中dump所有组播mac地址*/ + err = dpp_multicast_mac_dump(&pf_info, multicast_mac_arry, ¤t_multicast_num); + if (err != 0) + { + LOG_ERR("dpp_multicast_mac_dump failed\n"); + goto out2; + } + + for(i = 0; i < current_unicast_num; ++i) + { + LOG_INFO("unicast_mac_arry[%d].vport is %#x\n", i, unicast_mac_arry[i].vport); + LOG_INFO("unicast_mac_arry[%d].mac is %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n", i, \ + unicast_mac_arry[i].addr[0], unicast_mac_arry[i].addr[1], \ + unicast_mac_arry[i].addr[2], unicast_mac_arry[i].addr[3], \ + unicast_mac_arry[i].addr[4], unicast_mac_arry[i].addr[5]); + } + for(i = 0; i < current_multicast_num; ++i) + { + LOG_INFO("multicast_mac_arry[%d].vport is %#x\n", i, multicast_mac_arry[i].vport); + LOG_INFO("multicast_mac_arry[%d].mac is %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n", i, \ + multicast_mac_arry[i].addr[0], multicast_mac_arry[i].addr[1], \ + multicast_mac_arry[i].addr[2], multicast_mac_arry[i].addr[3], \ + multicast_mac_arry[i].addr[4], multicast_mac_arry[i].addr[5]); + } + +out2: + if (multicast_mac_arry != NULL) + { + kfree(multicast_mac_arry); + } + +out1: + if (unicast_mac_arry != NULL) + { + kfree(unicast_mac_arry); + } + + return err; +} +#endif /* MAC_CONFIG_DEBUG */ + +int32_t unicast_mac_add(struct zxdh_en_device *en_dev, struct net_device *dev, \ + const uint8_t* addr, uint16_t flags) +{ + int32_t err = 0; + DPP_PF_INFO_T pf_info = {0}; + + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + + /* 判断目前所配置mac地址数量是否超过上限 */ + if (en_dev->curr_unicast_num >= DEV_UNICAST_MAX_NUM-1) + { + LOG_ERR("curr_unicast_num is beyond maximum\n"); + return -ENOSPC; + } + + /* 遍历单播地址链表，判断是否存在此单播mac */ + if (is_this_mac_exist(dev, addr)) + { + LOG_DEBUG("Mac already exists\n"); + if (!(flags & NLM_F_EXCL)) + { + return 0; + } + return -EEXIST; + } + + /* 如果待配置mac和本机mac相同，则不配置到NP中， 只将此mac添加到单播地址链表中 */ + if (!memcmp(addr, dev->dev_addr, dev->addr_len)) + { + goto out; + } + + /* 将此mac地址配置到np中 */ + if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) + { + err = dpp_add_mac(&pf_info, addr); + if (err != 0) + { + LOG_ERR("dpp_add_mac failed\n"); + return err; + } + } + else + { + err = zxdh_vf_dpp_add_mac(en_dev, addr, FILTER_MAC); + if (err != 0) + { + LOG_ERR("zxdh_vf_dpp_add_mac failed\n"); + return err; + } + } + +out: + /* 将此单播mac地址添加到地址链表中 */ + err = zxdh_dev_list_addr_add(dev, addr); + if (err != 0) + { + LOG_ERR("zxdh_dev_list_addr_add failed\n"); + return err; + } + en_dev->curr_unicast_num++; + LOG_DEBUG("curr_unicast_num is %d\n", en_dev->curr_unicast_num); + return err; +} + +bool is_ipv6_mulicast_mac(const uint8_t *mac) +{ + return ((mac[0] == 0x33) && (mac[1] == 0x33)); +} + +int32_t multicast_mac_add(struct zxdh_en_device *en_dev, struct net_device *dev, \ + const uint8_t* addr, uint16_t flags) +{ + int32_t err = 0; + DPP_PF_INFO_T pf_info = {0}; + + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + + if (is_ipv6_mulicast_mac(addr)) + { + LOG_ERR("invlaid ipv6 mac address\n"); + return -EINVAL; + } + + /* 遍历组播地址链表，判断是否存在此mac */ + if (is_this_mac_exist(dev, addr)) + { + LOG_DEBUG("Mac already exists\n"); + if (!(flags & NLM_F_EXCL)) + { + return 0; + } + return -EEXIST; + } + + /* 将此组播mac地址配置到np中 */ + if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) + { + err = dpp_multi_mac_add_member(&pf_info, addr); + if (err != 0) + { + if (err == DPP_RC_TABLE_RANGE_INVALID) + { + LOG_ERR("multicast mac is beyond 32\n"); + return -ENOSPC; + } + LOG_ERR("dpp_multi_mac_add_member failed\n"); + return err; + } + } + else + { + err = zxdh_vf_dpp_add_mac(en_dev, addr, FILTER_MAC); + if (err != 0) + { + if(err == DPP_RC_TABLE_RANGE_INVALID) + { + LOG_ERR("multicast mac is beyond 32\n"); + return -ENOSPC; + } + LOG_ERR("zxdh_vf_dpp_add_mac failed\n"); + return err; + } + } + + /* 将此组播mac地址添加到地址链表中 */ + err = zxdh_dev_list_addr_add(dev, addr); + if (err != 0) + { + LOG_ERR("zxdh_dev_list_addr_add failed\n"); + return err; + } + return err; +} + +int32_t unicast_mac_del(struct zxdh_en_device *en_dev, struct net_device *dev, const uint8_t* addr) +{ + int32_t err = 0; + DPP_PF_INFO_T pf_info = {0}; + + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + + /* 判断目前所配置mac地址数量是否小于0 */ + if (en_dev->curr_unicast_num <= 0) + { + LOG_ERR("curr_unicast_num is less than 0\n"); + return -ENOENT; + } + + /* 遍历单播地址链表，判断是否存在此mac */ + if(!is_this_mac_exist(dev, addr)) + { + LOG_DEBUG("Mac is not exists\n"); + return -ENOENT; + } + + /* 如果待删除mac和本机mac相同，则不从NP中删除，只从链表中删除 */ + if (!memcmp(addr, dev->dev_addr, dev->addr_len)) + { + goto out; + } + + /* 从np中删除此单播mac */ + if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) + { + /* 此设备为PF */ + err = dpp_del_mac(&pf_info, addr); + if (err != 0) + { + LOG_ERR("dpp_del_mac failed\n"); + return err; + } + LOG_DEBUG("dpp_del_mac succeed\n"); + } + else + { + /* 此设备为VF */ + err = zxdh_vf_dpp_del_mac(en_dev, addr, FILTER_MAC, true); + if (err != 0) + { + LOG_ERR("zxdh_vf_dpp_del_mac failed\n"); + return err; + } + LOG_DEBUG("zxdh_vf_dpp_del_mac succeed\n"); + } + +out: + /* 从链表中删除单播mac */ + err = zxdh_dev_list_addr_del(dev, addr); + if (err != 0) + { + LOG_ERR("zxdh_dev_list_addr_del failed\n"); + return err; + } + en_dev->curr_unicast_num--; + LOG_DEBUG("curr_unicast_num is %d\n", en_dev->curr_unicast_num); + return err; +} + +int32_t multicast_mac_del(struct zxdh_en_device *en_dev, struct net_device *dev, const uint8_t* addr) +{ + int32_t err = 0; + DPP_PF_INFO_T pf_info = {0}; + + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + + if (is_ipv6_mulicast_mac(addr)) + { + LOG_ERR("invlaid ipv6 mac address\n"); + return -EINVAL; + } + + /* 遍历组播地址链表，判断是否存在此组播mac，如果不存在，则返回报错 */ + if(!is_this_mac_exist(dev, addr)) + { + LOG_DEBUG("Mac is not exists\n"); + return -ENOENT; + } + + /* 从np中删除此组播mac */ + if(en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) + { + /* 此设备为PF */ + err = dpp_multi_mac_del_member(&pf_info, addr); + if (err != 0) + { + LOG_ERR("dpp_multi_mac_del_member failed\n"); + return err; + } + LOG_DEBUG("dpp_multi_mac_del_member succeed\n"); + } + else + { + /* 此设备为VF */ + err = zxdh_vf_dpp_del_mac(en_dev, addr, FILTER_MAC, true); + if (err != 0) + { + LOG_ERR("zxdh_vf_dpp_del_mac failed\n"); + return err; + } + } + + /* 从链表中删除组播mac */ + err = zxdh_dev_list_addr_del(dev, addr); + if (err != 0) + { + LOG_ERR("zxdh_dev_list_addr_del failed\n"); + return err; + } + + return err; +} + +static unsigned int mac_hash(struct zxdh_ipv6_mac_tbl *mac_tbl, const uint8_t *mac_addr) +{ + unsigned int mact_size_half = mac_tbl->ip6mact_size / 2; + uint32_t mac_part1 = (mac_addr[0] << 24) | (mac_addr[1] << 16) | (mac_addr[2] << 8) | mac_addr[3]; + uint32_t mac_part2 = (mac_addr[4] << 8) | mac_addr[5]; + + uint32_t xor = mac_part1 ^ mac_part2; + + return (jhash_1word(xor, 0) % mact_size_half); +} + +int32_t zxdh_ip6mac_to_np(struct zxdh_en_device *en_dev, struct zxdh_ipv6_mac_tbl *ip6mac_tbl, const uint8_t *ip6mac, uint8_t action, bool need_lock) +{ + int32_t err = 0; + DPP_PF_INFO_T pf_info = {0}; + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + + switch (action) + { + case ADD_IP6MAC: + { + if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) + { /* PF流程 */ + if (need_lock) + { + write_lock_bh(&ip6mac_tbl->lock); + } + /* 将此组播mac地址配置到np中 */ + err = dpp_multi_mac_add_member(&pf_info, ip6mac); + if (err != 0) + { + LOG_ERR("dpp_multi_mac_add_member failed, err:%d\n", err); + } + if (need_lock) + { + write_unlock_bh(&ip6mac_tbl->lock); + } + } + else + { /* VF流程*/ + err = zxdh_vf_dpp_add_ipv6_mac(en_dev, ip6mac); + if (err != 0) + { + LOG_ERR("zxdh_vf_dpp_add_ipv6_mac failed, err:%d\n", err); + } + } + break; + } + case DEL_IP6MAC: + { + if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) + {/* PF流程 */ + if (need_lock) + { + write_lock_bh(&ip6mac_tbl->lock); + } + err = dpp_multi_mac_del_member(&pf_info, ip6mac); + if (err != 0) + { + LOG_ERR("dpp_multi_mac_del_member failed, err:%d\n", err); + } + if (need_lock) + { + write_unlock_bh(&ip6mac_tbl->lock); + } + } + else + {/* VF流程 */ + err = zxdh_vf_dpp_del_ipv6_mac(en_dev, ip6mac); + if (err != 0) + { + LOG_ERR("zxdh_vf_dpp_del_ipv6_mac failed, err:%d\n", err); + } + } + break; + } + } + return err; +} + +int32_t zxdh_ip6mac_add(struct zxdh_en_device *en_dev, const uint32_t *addr6, const uint8_t *ip6mac) +{ + int32_t err = 0; + unsigned int mac_hash_val; + struct zxdh_ipv6_mac_tbl *ip6mac_tbl = en_dev->ops->get_ip6mac_tbl(en_dev->parent); + struct zxdh_ipv6_mac_entry *ce, *cte; + + if (!ip6mac_tbl) + { + LOG_ERR("ip6mac_tbl is NULL\n"); + return -ENXIO; + } + + err = zxdh_ip6mac_to_np(en_dev, ip6mac_tbl, ip6mac, ADD_IP6MAC, TRUE); + if (err != 0) + { + return err; + } + + mac_hash_val = mac_hash(ip6mac_tbl, ip6mac); + //如果没有报错，则说明MAC已经存在或成功存入NP + read_lock_bh(&ip6mac_tbl->lock); + list_for_each_entry(cte, &ip6mac_tbl->hash_list[mac_hash_val], list) + { + if (memcmp(cte->ipv6_mac, ip6mac, ETH_ALEN) == 0) + {//MAC已经存在 + ce = cte; + refcount_inc(&ce->refcnt); + LOG_INFO("Increase Multicast MAC Address(%pM) refcnt:%d\n", ip6mac, refcount_read(&ce->refcnt)); + read_unlock_bh(&ip6mac_tbl->lock); + return 0; + } + } + read_unlock_bh(&ip6mac_tbl->lock); + + //成功新增MAC至NP，需要更新 ip6mac_tbl + write_lock_bh(&ip6mac_tbl->lock); + if (list_empty(&ip6mac_tbl->ip6mac_free_head)) + { + write_unlock_bh(&ip6mac_tbl->lock); + err = zxdh_ip6mac_to_np(en_dev, ip6mac_tbl, ip6mac, DEL_IP6MAC, TRUE); + LOG_ERR("ip6mac_tbl overflow, can't add; del mac from NP, ret:%d\n",err); + return -ENOMEM; + } + ce = list_first_entry(&ip6mac_tbl->ip6mac_free_head, struct zxdh_ipv6_mac_entry, list); + list_del(&ce->list); + INIT_LIST_HEAD(&ce->list); + spin_lock_init(&ce->lock); + refcount_set(&ce->refcnt, 0); + list_add_tail(&ce->list, &ip6mac_tbl->hash_list[mac_hash_val]); + memcpy(ce->ipv6_mac, ip6mac, ETH_ALEN); + refcount_set(&ce->refcnt, 1); + write_unlock_bh(&ip6mac_tbl->lock); + LOG_INFO("Add New Multicast MAC Address: %pM, refcnt:%d\n", ip6mac, refcount_read(&ce->refcnt)); + + return 0; +} + +int32_t zxdh_ip6mac_del(struct zxdh_en_device *en_dev, const uint32_t *addr6, const uint8_t *ip6mac) +{ + int32_t err = 0; + struct zxdh_ipv6_mac_tbl *ip6mac_tbl = en_dev->ops->get_ip6mac_tbl(en_dev->parent); + struct zxdh_ipv6_mac_entry *ce, *cte; + unsigned int mac_hash_val; + int32_t refcnt = 0; + DPP_PF_INFO_T pf_info = {0}; + + if (!ip6mac_tbl) + { + LOG_ERR("ip6mac_tbl is NULL"); + return -ENXIO; + } + + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + + mac_hash_val = mac_hash(ip6mac_tbl, ip6mac); + + read_lock_bh(&ip6mac_tbl->lock); + list_for_each_entry(cte, &ip6mac_tbl->hash_list[mac_hash_val], list) + { + if (memcmp(cte->ipv6_mac, ip6mac, ETH_ALEN) == 0) + {//MAC存在 + ce = cte; + read_unlock_bh(&ip6mac_tbl->lock); + goto found; + } + } + read_unlock_bh(&ip6mac_tbl->lock); + LOG_INFO("Don't Found Multicast MAC Address: %pM in Hash List\n", ip6mac); + return zxdh_ip6mac_to_np(en_dev, ip6mac_tbl, ip6mac, DEL_IP6MAC, TRUE); + +found: + write_lock_bh(&ip6mac_tbl->lock); + spin_lock_bh(&ce->lock); + if (!refcount_dec_and_test(&ce->refcnt)) + { + LOG_INFO("Decrease Multicast MAC Address(%pM) refcnt:%d\n", ip6mac, refcount_read(&ce->refcnt)); + spin_unlock_bh(&ce->lock); + write_unlock_bh(&ip6mac_tbl->lock); + return err; + } + //如果引用计数减到0 + list_del(&ce->list); + INIT_LIST_HEAD(&ce->list); + list_add_tail(&ce->list, &ip6mac_tbl->ip6mac_free_head); + refcnt = refcount_read(&ce->refcnt); + spin_unlock_bh(&ce->lock); + if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_VF) + { //VF设备需要先释放锁再发消息下表，因为PF侧会加锁 + write_unlock_bh(&ip6mac_tbl->lock); + err = zxdh_ip6mac_to_np(en_dev, ip6mac_tbl, ip6mac, DEL_IP6MAC, FALSE); + } + else + { //PF设备需要带锁下表 + err = zxdh_ip6mac_to_np(en_dev, ip6mac_tbl, ip6mac, DEL_IP6MAC, FALSE); + write_unlock_bh(&ip6mac_tbl->lock); + } + LOG_INFO("Del Multicast MAC Address: %pM Completely, refcnt:%d, np ret:%d\n", ip6mac, refcnt, err); + return err; +} + +int32_t zxdh_en_set_vepa(struct zxdh_en_device *en_dev, bool setting) +{ + struct zxdh_vf_item *vf_item = NULL; + bool vepa = false; + uint16_t vf_idx = 0; + int32_t ret = 0; + DPP_PF_INFO_T pf_info = {0}; + + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + + vepa = en_dev->ops->get_vepa(en_dev->parent); + if (setting == vepa) + { + LOG_ERR("vport(0x%x) is now %s mode\n", en_dev->vport, vepa?"vepa":"veb"); + return 0; + } + + en_dev->ops->set_vepa(en_dev->parent, setting); + ret = dpp_egr_port_attr_set(&pf_info, EGR_FLAG_VEPA_EN_OFF, (uint32_t)setting); + if (ret != 0) + { + LOG_ERR("Failed to setup vport(0x%x) %s mode, ret: %d\n", en_dev->vport, setting?"vepa":"veb", ret); + return ret; + } + + for (vf_idx = 0; vf_idx < ZXDH_VF_NUM_MAX; vf_idx++) + { + vf_item = en_dev->ops->get_vf_item(en_dev->parent, vf_idx); + if (IS_ERR_OR_NULL(vf_item)) + { + break; + } + + if (vf_item->is_probed) + { + pf_info.vport = vf_item->vport; + ret = dpp_egr_port_attr_set(&pf_info, EGR_FLAG_VEPA_EN_OFF, (uint32_t)setting); + if (ret != 0) + { + LOG_ERR("Failed to setup vport(0x%x) %s mode, ret: %d\n", vf_item->vport, setting?"vepa":"veb", ret); + return ret; + } + LOG_INFO("Configure vport(0x%x) to %s mode\n", vf_item->vport, setting?"vepa":"veb"); + } + } + + LOG_INFO("Configure vport(0x%x) to %s mode\n", en_dev->vport, setting?"vepa":"veb"); + + return ret; +} + +#ifdef HAVE_FDB_OPS +#if defined(HAVE_NDO_FDB_ADD_EXTACK) +static int zxdh_en_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], + struct net_device *dev, const unsigned char *addr, + u16 vid, u16 flags, struct netlink_ext_ack *extack) +#elif defined(HAVE_NDO_FDB_ADD_VID) +static int zxdh_en_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], + struct net_device *dev, const unsigned char *addr, + u16 vid, u16 flags) +#elif defined(HAVE_NDO_FDB_ADD_NLATTR) +static int zxdh_en_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], + struct net_device *dev, const unsigned char *addr, + u16 flags) +#elif defined(USE_CONST_DEV_UC_CHAR) +static int zxdh_en_ndo_fdb_add(struct ndmsg *ndm, struct net_device *dev, + const unsigned char *addr, u16 flags) +#else +static int zxdh_en_ndo_fdb_add(struct ndmsg *ndm, struct net_device *dev, + unsigned char *addr, u16 flags) +#endif +{ + struct zxdh_en_priv *en_priv = netdev_priv(dev); + struct zxdh_en_device *en_dev = &en_priv->edev; /*aux层net_device的私有结构体 */ + int32_t err = 0; + +#ifdef MAC_CONFIG_DEBUG + LOG_DEBUG("vport is %#x\n", en_dev->vport); + LOG_DEBUG("addr is %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n", \ + addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]); + LOG_DEBUG("ndm_state is %u\n", ndm->ndm_state); +#endif /* MAC_CONFIG_DEBUG */ + + /* 检查这个设备的ndm状态是否是静态的 */ + if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) + { + LOG_ERR("FDB only supports static addresses\n"); + return -EINVAL; + } + + /* 判断mac地址是否全0 */ + if (is_zero_ether_addr(addr)) + { + LOG_ERR("Invalid mac\n"); + return -EINVAL; + } + + if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) + { + err = unicast_mac_add(en_dev, dev, addr, flags); + if (err != 0) + { + LOG_ERR("unicast_mac_add failed"); + return err; + } + } + else if (is_multicast_ether_addr(addr)) + { + err = multicast_mac_add(en_dev, dev, addr, flags); + if (err != 0) + { + LOG_ERR("multicast_mac_add failed"); + return err; + } + } + else + { + err = -EINVAL; + } + +#ifdef MAC_CONFIG_DEBUG + if(en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) + { + err = zxdh_pf_dump_all_mac(en_dev); + if (err != 0) + { + LOG_INFO("zxdh_pf_dump_all_mac failed\n"); + return err; + } + } +#endif /* MAC_CONFIG_DEBUG */ + + LOG_DEBUG("zxdh_en_ndo_fdb_add end\n"); + return err; +} + +#ifdef HAVE_NDO_FEATURES_CHECK +static netdev_features_t zxdh_en_features_check(struct sk_buff *skb, struct net_device *dev, + netdev_features_t features) +{ + return features; +} +#endif /* HAVE_NDO_FEATURES_CHECK */ + +#ifdef USE_CONST_DEV_UC_CHAR +#ifdef HAVE_NDO_FDB_ADD_VID +static int zxdh_en_ndo_fdb_del(struct ndmsg *ndm, struct nlattr **nla, struct net_device *dev, + const unsigned char *addr, u16 vid) +#else +static int zxdh_en_ndo_fdb_del(struct ndmsg *ndm, struct net_device *dev, + const unsigned char *addr) +#endif +#else +#ifdef HAVE_NDO_FDB_ADD_VID +static int zxdh_en_ndo_fdb_del(struct ndmsg *ndm, struct net_device *dev, + unsigned char *addr, u16 vid) +#else +static int zxdh_en_ndo_fdb_del(struct ndmsg *ndm, struct net_device *dev, + unsigned char *addr) +#endif +#endif +{ + struct zxdh_en_priv *en_priv = netdev_priv(dev); + struct zxdh_en_device *en_dev = &en_priv->edev; + int32_t err = 0; + +#ifdef MAC_CONFIG_DEBUG + LOG_DEBUG("the vport is %#x",en_dev->vport); + LOG_DEBUG("the addr is %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n",\ + addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]); + LOG_DEBUG("ndm_state is %u,\n", ndm->ndm_state); +#endif /* MAC_CONFIG_DEBUG */ + + /* 检查这个设备的ndm状态是否是静态的 */ + if (!(ndm->ndm_state & NUD_PERMANENT)) + { + LOG_ERR("FDB only supports static addresses\n"); + return -EINVAL; + } + + /* 地址是否全为0 */ + if (is_zero_ether_addr(addr)) + { + LOG_ERR("Invalid mac address\n"); + return -EINVAL; + } + + /* 根据mac地址类型，对相对应地址链表做删除操作 */ + if (is_unicast_ether_addr(addr)) + { + err = unicast_mac_del(en_dev, dev, addr); + if (err != 0) + { + LOG_ERR("unicast_mac_del failed\n"); + return err; + } + } + else if (is_multicast_ether_addr(addr)) + { + err = multicast_mac_del(en_dev, dev, addr); + if (err != 0) + { + LOG_ERR("multicast_mac_del failed\n"); + return err; + } + } + else + { + return -EINVAL; + } + +#ifdef MAC_CONFIG_DEBUG + if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) + { + /*先dump所有mac地址*/ + err = zxdh_pf_dump_all_mac(en_dev); + if (err != 0) + { + LOG_ERR("zxdh_pf_dump_all_mac failed\n"); + return err; + } + } +#endif /* MAC_CONFIG_DEBUG */ + + LOG_DEBUG("zxdh_en_ndo_fdb_del end\n"); + return err; +} + +#ifdef HAVE_BRIDGE_ATTRIBS +#if defined(HAVE_NDO_BRIDGE_SETLINK_EXTACK) +static int zxdh_en_ndo_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh, + u16 flags, struct netlink_ext_ack *extack) +#elif defined(HAVE_NDO_BRIDGE_SET_DEL_LINK_FLAGS) +static int zxdh_en_ndo_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh, u16 flags) +#else +static int zxdh_en_ndo_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh) +#endif +{ + struct zxdh_en_priv *en_priv = netdev_priv(dev); + struct zxdh_en_device *en_dev = &en_priv->edev; + struct nlattr *attr = NULL; + struct nlattr *br_spec = NULL; + int32_t rem = 0; + uint16_t mode = BRIDGE_MODE_UNDEF; + bool setting = false; + + if(en_dev->ops->get_coredev_type(en_dev->parent) != DH_COREDEV_PF) + { + return -EOPNOTSUPP; + } + + br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); + if (br_spec == NULL) + { + return -EINVAL; + } + + nla_for_each_nested(attr, br_spec, rem) + { + if (nla_type(attr) != IFLA_BRIDGE_MODE) + { + continue; + } + + if (nla_len(attr) < sizeof(mode)) + { + return -EINVAL; + } + + mode = nla_get_u16(attr); + if (mode > BRIDGE_MODE_VEPA) + { + return -EINVAL; + } + break; + } + + if (mode == BRIDGE_MODE_UNDEF) + { + return -EINVAL; + } + + setting = (mode == BRIDGE_MODE_VEPA) ? 1 : 0; + + return zxdh_en_set_vepa(en_dev, setting); +} + +#ifdef HAVE_NDO_BRIDGE_GETLINK_NLFLAGS +static int zxdh_en_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, + struct net_device *dev, u32 __always_unused filter_mask, + int nlflags) +#elif defined(HAVE_BRIDGE_FILTER) +static int zxdh_en_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, + struct net_device *dev, u32 __always_unused filter_mask) +#else +static int zxdh_en_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, + struct net_device *dev) +#endif /* NDO_BRIDGE_STUFF */ +{ + struct zxdh_en_priv *en_priv = netdev_priv(dev); + struct zxdh_en_device *en_dev = &en_priv->edev; + uint8_t mode = 0; + bool vepa = false; + + vepa = en_dev->ops->get_vepa(en_dev->parent); + mode = vepa ? BRIDGE_MODE_VEPA : BRIDGE_MODE_VEB; + + return ndo_dflt_bridge_getlink(skb, pid, seq, dev, mode, 0, 0, nlflags, filter_mask, NULL); +} +#endif /* HAVE_BRIDGE_ATTRIBS */ +#endif /* HAVE_FDB_OPS */ + +static int32_t zxdh_pf_notify_vf_reset(struct zxdh_en_device *en_dev, int vf_idx) +{ + int32_t retval = 0; + union zxdh_msg msg = {0}; + + msg.payload.hdr_vf.op_code = ZXDH_SET_VF_RESET; + msg.payload.hdr_vf.dst_pcie_id = FIND_VF_PCIE_ID(en_dev->pcie_id, vf_idx); + + retval = zxdh_send_command_to_specify(en_dev, MODULE_PF_BAR_MSG_TO_VF, &msg, &msg); + if(retval != 0) + { + LOG_ERR("zxdh_send_command_to_vf failed: %d\n", retval); + } + return retval; +} + +static int32_t zxdh_pf_notify_vf_set_link_state(struct zxdh_en_device *en_dev, int vf_idx, bool link_up) +{ + int32_t retval = 0; + uint16_t func_no = 0; + uint16_t pf_no = FIND_PF_ID(en_dev->pcie_id); + uint8_t link_info = 0; + uint8_t link_up_val = 0; + uint8_t phyport_val = 0; + union zxdh_msg msg = {0}; + + msg.payload.hdr_to_agt.op_code = AGENT_DEV_STATUS_NOTIFY; + msg.payload.hdr_to_agt.pcie_id = en_dev->pcie_id; + + func_no = GET_FUNC_NO(pf_no, vf_idx); + LOG_DEBUG("vf_idx:%d, func_no=0x%x\n",vf_idx,func_no); + msg.payload.pcie_msix_msg.func_no[msg.payload.pcie_msix_msg.num++] = func_no; + if(en_dev->ops->is_bond(en_dev->parent)) + { + link_up_val = link_up ? 1 : 0; + phyport_val = en_dev->ops->get_pf_phy_port(en_dev->parent); + link_info = (phyport_val & 0x0F) << 4 | (link_up_val & 0x0F); + LOG_DEBUG("phyport and link_up need write to VQM, val: 0x%x\n", link_info); + en_dev->ops->set_vf_link_info(en_dev->parent, vf_idx, link_info); + } + else + { + en_dev->ops->set_vf_link_info(en_dev->parent, vf_idx, link_up ? 1 : 0); + } + LOG_DEBUG("msg.pcie_msix_msg.num:%d\n", msg.payload.pcie_msix_msg.num); + retval = zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &msg); + if (retval != 0) + { + LOG_ERR("failed to update VF link info\n"); + } + return retval; +} + +static int32_t zxdh_pf_set_vf_link_state(struct zxdh_en_device *en_dev, int vf_idx, int link_status) +{ + int32_t retval = 0; + struct zxdh_vf_item *vf_item = NULL; + bool pf_link_up = en_dev->ops->get_pf_link_up(en_dev->parent); + + vf_item = en_dev->ops->get_vf_item(en_dev->parent, vf_idx); + switch (link_status) + { + case IFLA_VF_LINK_STATE_AUTO: + LOG_DEBUG("[SET_VF_LINK_STATE]--NDO set VF %d link state auto\n", vf_idx); + vf_item->link_forced = FALSE; + vf_item->link_up = pf_link_up; + break; + case IFLA_VF_LINK_STATE_ENABLE: + LOG_DEBUG("[SET_VF_LINK_STATE]--NDO set VF %d link state enable\n", vf_idx); + vf_item->link_forced = TRUE; + vf_item->link_up = TRUE; + break; + case IFLA_VF_LINK_STATE_DISABLE: + LOG_DEBUG("[SET_VF_LINK_STATE]--NDO set VF %d link state disable\n", vf_idx); + vf_item->link_forced = TRUE; + vf_item->link_up = FALSE; + break; + default: + LOG_ERR("[SET_VF_LINK_STATE]--NDO set VF %d - invalid link status %d\n", vf_idx, link_status); + return -EINVAL; + } + LOG_DEBUG("vf_item->is_probed: %s\n", vf_item->is_probed?"TRUE":"FALSE"); + if(vf_item->is_probed) + { + /* Notify the VF of its new link state */ + retval = zxdh_pf_notify_vf_set_link_state(en_dev, vf_idx, vf_item->link_up); + if (0 != retval) + { + LOG_ERR("[SET_VF_LINK_STATE]--Failed to set VF %d link state %d\n", vf_idx, vf_item->link_up); + return retval; + } + } + return retval; +} + +int zxdh_en_ndo_set_vf_link_state(struct net_device *netdev, int vf_idx, int link_status) +{ + int num_vfs = 0; + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + struct pci_dev *pdev = NULL; + struct dh_core_dev *dh_dev = NULL; + + dh_dev = en_dev->parent; + pdev = en_dev->ops->get_pdev(dh_dev); + num_vfs = pci_num_vf(pdev); + if ((vf_idx < 0) || (vf_idx >= num_vfs)) + { + LOG_ERR("[SET_VF_LINK_STATE]--NDO set VF link - invalid VF idx: %d\n", vf_idx); + return -EINVAL; + } + return zxdh_pf_set_vf_link_state(en_dev, vf_idx, link_status); +} + +static int32_t zxdh_pf_set_vf_port_vlan(struct zxdh_en_device *en_dev, int vf_idx, u16 vid, u8 qos, uint16_t vlan_proto) +{ + int32_t retval = 0; + struct zxdh_vf_item *vf_item = NULL; + union zxdh_msg msg = {0}; + DPP_PF_INFO_T pf_info = {0}; + + /* 获取pf本地保存的vf变量*/ + vf_item = en_dev->ops->get_vf_item(en_dev->parent, vf_idx); + if(!vf_item->is_probed) + { + LOG_DEBUG("vf %d is not probed.\n", vf_idx); + return -EINVAL; + } + + if (vf_item->vlan == vid) + { + return 0; + } + + pf_info.slot = en_dev->slot_id; + pf_info.vport = vf_item->vport; + if (vid) + { + /* vf端口Vlan strip开启*/ + retval = dpp_vport_vlan_strip_set(&pf_info, 1); + if (retval != 0) + { + LOG_ERR("dpp_vport_vlan_strip_set failed, retval: %d\n", retval); + return retval; + } + /* 将vlan_id add到表项中*/ + retval = dpp_vport_vlan_filter_en_set(&pf_info, 1); + if (retval != 0) + { + LOG_ERR("dpp_vport_vlan_filter_en_set failed, retval: %d\n", retval); + return retval; + } + + retval = dpp_add_vlan_filter(&pf_info, vid); + if (0 != retval) + { + LOG_ERR("failed to add vlan: %d\n",vid); + return retval; + } + } + else + { + /* vf端口vlan strip关闭*/ + retval = dpp_vport_vlan_strip_set(&pf_info, 0); + if (retval != 0) + { + LOG_ERR("dpp_vport_vlan_strip_set failed, retval: %d\n", retval); + return retval; + } + /* 将Vlan_id 从表项中kill*/ + retval = dpp_vport_vlan_filter_en_set(&pf_info, 0); + if (retval != 0) + { + LOG_ERR("dpp_vport_vlan_filter_en_set failed, retval: %d\n", retval); + return retval; + } + + retval = dpp_vlan_filter_init(&pf_info); + if (retval != 0) + { + LOG_ERR("dpp_vlan_filter_init failed: %d\n", retval); + return retval; + } + } + + msg.payload.hdr_vf.op_code = ZXDH_PF_SET_VF_VLAN; + msg.payload.hdr_vf.dst_pcie_id = FIND_VF_PCIE_ID(en_dev->pcie_id, vf_idx); + + msg.payload.vf_vlan_msg.vlan_id = vid; + msg.payload.vf_vlan_msg.qos = qos; + msg.payload.vf_vlan_msg.protocl = vlan_proto; + msg.payload.vf_vlan_msg.vf_idx = vf_idx; + + retval = zxdh_send_command_to_specify(en_dev, MODULE_PF_BAR_MSG_TO_VF, &msg, &msg); + if(retval != 0) + { + LOG_ERR("zxdh_send_command_to_vf failed: %d\n", retval); + return retval; + } + + /* 更新pf本地的vf vlan信息，用于ip link show显示*/ + vf_item->vlan = vid; + vf_item->qos = qos; + return retval; +} + + +int zxdh_en_ndo_set_vf_mac(struct net_device *netdev, int vf_id, u8 *mac) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + struct zxdh_vf_item *vf_item = NULL; + int32_t retval = 0; + bool delete_flag = true; + uint8_t *addr = NULL; + uint8_t i = 0; + DPP_PF_INFO_T pf_info = {0}; + + vf_item = en_dev->ops->get_vf_item(en_dev->parent, vf_id); + if (IS_ERR_OR_NULL(vf_item)) + { + LOG_ERR("Failed to get vf_item, vf_id:%d\n", vf_id); + return PTR_ERR(vf_item); + } + pf_info.slot = en_dev->slot_id; + pf_info.vport = vf_item->vport; + + if (is_multicast_ether_addr(mac)) + { + LOG_ERR("Invalid Ethernet address %pM for VF %d\n", mac, vf_id); + return -EINVAL; + } + + if (ether_addr_equal(vf_item->mac, mac)) + { + LOG_INFO("[SET_VF_MAC]--already using mac address %pM\n", mac); + return retval; + } + + if (is_zero_ether_addr(mac)) + { + eth_zero_addr(vf_item->mac); + vf_item->pf_set_mac = false; + en_dev->ops->set_vf_mac(en_dev->parent, mac, vf_id); + eth_zero_addr(vf_item->vf_mac_info.unicast_mac[0]); + goto vf_reset; + } + + for (i = 1; i < DEV_UNICAST_MAX_NUM; ++i) + { + addr = vf_item->vf_mac_info.unicast_mac[i]; + if (!memcmp(vf_item->mac, addr, netdev->addr_len)) + { + delete_flag = false; + } + } + + if (delete_flag) + { + if (!is_zero_ether_addr(vf_item->mac)) + { + retval = dpp_del_mac(&pf_info, vf_item->mac); + if (retval != 0) + { + LOG_ERR("delete vf old mac in NP failed.\n"); + return retval; + } + } + } + + vf_item->pf_set_mac = true; + en_dev->ops->set_vf_mac(en_dev->parent, mac, vf_id); + ether_addr_copy(vf_item->vf_mac_info.unicast_mac[0], mac); + ether_addr_copy(vf_item->mac, mac); + LOG_INFO("[SET_VF_MAC]--setting MAC %pM on VF %d\n", mac, vf_id); + +vf_reset: + if (vf_item->is_probed) + { + retval = zxdh_pf_notify_vf_reset(en_dev, vf_id); + if(retval != 0) + { + LOG_ERR("zxdh_pf_notify_vf_reset failed: %d\n", retval); + } + } + + return retval; +} + +#ifdef IFLA_VF_VLAN_INFO_MAX +int zxdh_en_ndo_set_vf_port_vlan(struct net_device *netdev, int vf_id, + u16 vlan_id, u8 qos, __be16 vlan_proto) +#else +int zxdh_en_ndo_set_vf_port_vlan(struct net_device *netdev, int vf_id, u16 vlan_id, u8 qos) +#endif /* IFLA_VF_VLAN_INFO_MAX */ +{ + int num_vfs = 0; + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + struct pci_dev *pdev = NULL; + struct dh_core_dev *dh_dev = NULL; + + /* Comparing with the mellnox network card, it only supports the configuration of cvlan*/ + if (vlan_proto != htons(ETH_P_8021Q)) + { + return -EPROTONOSUPPORT; + } + dh_dev = en_dev->parent; + pdev = en_dev->ops->get_pdev(dh_dev); + num_vfs = pci_num_vf(pdev); + if ((vf_id < 0) || (vf_id >= num_vfs)) + { + LOG_ERR("[SET+VF_VLAN]--NDO set VF vlan - invalid VF idx: %d\n", vf_id); + return -EINVAL; + } + return zxdh_pf_set_vf_port_vlan(en_dev, vf_id, vlan_id, qos, vlan_proto); +} + +int zxdh_en_ndo_set_vf_bw(struct net_device *netdev, int vf_id, int min_tx_rate, int max_tx_rate) +{ + return 0; +} + +int zxdh_en_ndo_get_vf_config(struct net_device *netdev, int vf_idx, struct ifla_vf_info *ivi) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + struct zxdh_vf_item *vf_item = NULL; + + vf_item = en_dev->ops->get_vf_item(en_dev->parent, vf_idx); + if (IS_ERR_OR_NULL(vf_item)) + { + LOG_ERR("Failed to get vf_item, vf_idx:%d\n", vf_idx); + return PTR_ERR(vf_item); + } + + ivi->vf = vf_idx; + + ether_addr_copy(ivi->mac, vf_item->mac); + +#ifdef HAVE_NDO_SET_VF_MIN_MAX_TX_RATE + ivi->max_tx_rate = vf_item->max_tx_rate; + ivi->min_tx_rate = vf_item->min_tx_rate; +#else + ivi->tx_rate = vf_item->max_tx_rate; +#endif + + ivi->vlan = vf_item->vlan; + ivi->qos = vf_item->qos; + +#ifdef HAVE_NDO_SET_VF_LINK_STATE + if (vf_item->link_forced == false) + { + ivi->linkstate = IFLA_VF_LINK_STATE_AUTO; + } + else if (vf_item->link_up == true) + { + ivi->linkstate = IFLA_VF_LINK_STATE_ENABLE; + } + else + { + ivi->linkstate = IFLA_VF_LINK_STATE_DISABLE; + } +#endif + +#ifdef HAVE_VF_SPOOFCHK_CONFIGURE + ivi->spoofchk = vf_item->spoofchk; +#endif + +#ifdef HAVE_NDO_SET_VF_TRUST + ivi->trusted = vf_item->trusted; +#endif + + return 0; +} + +int zxdh_en_ndo_set_vf_spoofchk(struct net_device *netdev, int vf_idx, bool enable) +{ + int ret = 0; + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + struct zxdh_vf_item *vf_item = NULL; + DPP_PF_INFO_T pf_info = {0}; + + vf_item = en_dev->ops->get_vf_item(en_dev->parent, vf_idx); + if (IS_ERR_OR_NULL(vf_item)) + { + LOG_ERR("Failed to get vf_item, vf_idx:%d\n", vf_idx); + return PTR_ERR(vf_item); + } + + pf_info.slot = en_dev->slot_id; + pf_info.vport = vf_item->vport; + vf_item->spoofchk = enable; + LOG_INFO("vf %d spoof check is %s\n", vf_idx, vf_item->spoofchk? "on" : "off"); + if (vf_item->is_probed) + { + ret = dpp_egr_port_attr_set(&pf_info, EGR_FLAG_SPOOFCHK_EN_OFF, enable); + if (0 != ret) + { + LOG_ERR("[SET_VF_SPOOFCHK]--Failed to set vf %d spookchk %s\n", vf_idx, enable ? "on" : "off"); + return ret; + } + } + return ret; +} + +#ifdef HAVE_NDO_SET_VF_TRUST +int zxdh_en_ndo_set_vf_trust(struct net_device *netdev, int vf_idx, bool setting) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + struct zxdh_vf_item *vf_item = NULL; + DPP_PF_INFO_T pf_info = {0}; + + vf_item = en_dev->ops->get_vf_item(en_dev->parent, vf_idx); + if (IS_ERR_OR_NULL(vf_item)) + { + LOG_ERR("Failed to get vf_item, vf_idx:%d\n", vf_idx); + return PTR_ERR(vf_item); + } + + pf_info.slot = en_dev->slot_id; + pf_info.vport = vf_item->vport; + vf_item->trusted = setting; + LOG_INFO("VF %u is now %strusted\n", vf_idx, setting ? "" : "un"); + if (vf_item->is_probed && !vf_item->trusted) + { + LOG_DEBUG("vport[0x%x] promisc and allmulti off\n", vf_item->vport); + vf_item->promisc = false; + vf_item->mc_promisc = false; + dpp_vport_uc_promisc_set(&pf_info, vf_item->promisc); + dpp_vport_mc_promisc_set(&pf_info, vf_item->mc_promisc); + } + + return 0; +} +#endif + +int zxdh_en_ndo_set_tx_maxrate(struct net_device *netdev, int qid, uint32_t max_rate) +{ + int rtn = 0; + zxdh_plcr_rate_limit_paras rate_limit_paras; + + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + struct dh_core_dev *dh_dev = en_dev->parent; + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev->parent); + + PLCR_FUNC_DBG_ENTER(); + + /*1. 入参检测：队列号不能超过vf下实际的队列数*/ + if (qid >= en_dev->curr_queue_pairs) + { + LOG_ERR("zxdh_en_ndo_set_tx_maxrate : invalid parameter qid=%d\n", qid); + return -EINVAL; + } +#if 0 + if (!en_dev->link_up) + { + LOG_ERR("[EN SET TX MAXRATE]--PF is not link up.\n"); + return -EINVAL; + } + link_speed = en_dev->link_speed; +#endif + + rate_limit_paras.req_type = E_RATE_LIMIT_REQ_QUEUE_BYTE; + rate_limit_paras.direction = E_RATE_LIMIT_TX; + rate_limit_paras.mode = E_RATE_LIMIT_BYTE ; + rate_limit_paras.max_rate = max_rate; + rate_limit_paras.min_rate = 0; + rate_limit_paras.queue_id = qid; + rate_limit_paras.vf_idx = PLCR_INVALID_PARAM; + rate_limit_paras.vfid = PLCR_INVALID_PARAM; + rate_limit_paras.group_id = PLCR_INVALID_PARAM; + + rtn = zxdh_plcr_unified_set_rate_limit(pf_dev, &rate_limit_paras); + PLCR_COMM_ASSERT(rtn); + + PLCR_LOG_INFO("The maxrate of tx-%d has been set to %dMbit/s\n", qid, max_rate); + + return rtn; +} + +/**-------------------------------------------------------------------------------------------------------------------@n + * 功能详述: + * - zxdh_en_ndo_set_vf_rate函数属于接口函数, 其功能是: + * - 设置vf端口发送方向，最大速率和最小保证速率 + * - 该接口会挂接到内核的钩子上，函数声明是固定的 + * + * 基于plcr的端口限速背景： + * - 1.一级flowid与vqm的2K个（接收和发送）队列是一一映射的 + * - 2.二级flow id与vf num的映射关系 + * 端口限速，需要将vf下的发送队列（即一级flow id）映射到二级flowid + * 二级flow id的资源是4K，dpu限制vf数量是1K，即二级flow id数量 > vf数量 + * 所以规定固定的映射关系：二级flow id前1K <---> 与1K个vf（发送）一一对应 + * 下面的链接整理了pf下vf转换成全局vf（0-1023）的原理 + * https://i.zte.com.cn/#/space/4e62cb2b730540ff8721c1a8552b2356/wiki/page/ff8178f1304e45dc9457e92ff196cce5/view + * - 3.vf限速的设置 + * 项目对vf提出了最小保证带宽的需求； + * 二级CAR的限速模板使用：双速率，三色算法，色敏模式 + * - 4.创建vf的其它考虑 + * 参考mlx的做法，vf创建之后，默认关联到vf组0（注意：>>>>>>>>先交付vf端口限速的需求，这一步可以暂时不实现<<<<<<<<）； + * vf创建之后，用户设置限速才会调用到这里，用户不设置限速，vf（二级flow id）就不用关联限速模板 + * + * 参数概述: + * - netdev : 网络设备结构体指针 + * - vf_id ：pf内vf的编号（从0开始） + * - min_tx_rate : 最小保证速率 + * - max_tx_rate : 最大速率 + * - 返回值类型是INT32, 含义是: 错误码，正确时为S_OK + * + * 引用(类变量,外部变量,接口函数): + * - 无 + * + * 注意：该函数挂接到pf的钩子上，只在pf下执行 + *--------------------------------------------------------------------------------------------------------------------*/ +int zxdh_en_ndo_set_vf_rate(struct net_device *netdev, int vf_id, int min_tx_rate, int max_tx_rate) +{ + int rtn; + zxdh_plcr_rate_limit_paras rate_limit_paras; + + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + struct dh_core_dev *dh_dev = en_dev->parent; + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev->parent); + + PLCR_FUNC_DBG_ENTER(); + + rate_limit_paras.req_type = E_RATE_LIMIT_REQ_VF_BYTE; + rate_limit_paras.direction = E_RATE_LIMIT_TX; + rate_limit_paras.mode = E_RATE_LIMIT_BYTE ; + rate_limit_paras.max_rate = max_tx_rate; + rate_limit_paras.min_rate = min_tx_rate; + rate_limit_paras.queue_id = PLCR_INVALID_PARAM; + rate_limit_paras.vf_idx = vf_id; + rate_limit_paras.vfid = PLCR_INVALID_PARAM; + rate_limit_paras.group_id = PLCR_INVALID_PARAM; + + rtn = zxdh_plcr_unified_set_rate_limit(pf_dev, &rate_limit_paras); + PLCR_COMM_ASSERT(rtn); + + PLCR_LOG_INFO("The Rate of VF%d has been set to: Min Tx Rate: %dMbit/s, Max Tx Rate: %dMbit/s\n", + vf_id, min_tx_rate, max_tx_rate); + + return rtn; +} + +const struct net_device_ops zxdh_netdev_ops = { + .ndo_open = zxdh_en_open, + .ndo_stop = zxdh_en_close, + .ndo_start_xmit = zxdh_en_xmit, + +#if defined(HAVE_NDO_GET_STATS64) || defined(HAVE_VOID_NDO_GET_STATS64) + .ndo_get_stats64 = zxdh_en_get_netdev_stats_struct, +#else + .ndo_get_stats = zxdh_en_get_netdev_stats_struct, +#endif + .ndo_set_rx_mode = zxdh_en_set_rx_mode, + .ndo_validate_addr = eth_validate_addr, + .ndo_set_mac_address = zxdh_en_set_mac, + +#ifdef HAVE_RHEL7_EXTENDED_MIN_MAX_MTU + .extended.ndo_change_mtu = zxdh_en_change_mtu, +#else + .ndo_change_mtu = zxdh_en_change_mtu, +#endif /* HAVE_RHEL7_EXTENDED_MIN_MAX_MTU */ + + .ndo_do_ioctl = zxdh_en_ioctl, +#ifdef ZXDH_PLCR_OPEN + .ndo_set_tx_maxrate = zxdh_en_ndo_set_tx_maxrate, +#endif + .ndo_tx_timeout = zxdh_en_tx_timeout, + +#ifdef HAVE_VLAN_RX_REGISTER + .ndo_vlan_rx_register = zxdh_en_vlan_rx_register, +#endif + .ndo_vlan_rx_add_vid = zxdh_en_vlan_rx_add_vid, + .ndo_vlan_rx_kill_vid = zxdh_en_vlan_rx_kill_vid, + +#ifdef CONFIG_NET_POLL_CONTROLLER + .ndo_poll_controller = zxdh_en_netpoll, +#endif + +#ifdef HAVE_SETUP_TC +#ifdef HAVE_RHEL7_NETDEV_OPS_EXT_NDO_SETUP_TC + .extended.ndo_setup_tc_rh = __zxdh_en_setup_tc, +#else +#ifdef NETIF_F_HW_TC + .ndo_setup_tc = __zxdh_en_setup_tc, +#else + .ndo_setup_tc = zxdh_en_setup_tc, +#endif /* NETIF_F_HW_TC */ +#endif /* HAVE_RHEL7_NETDEV_OPS_EXT_NDO_SETUP_TC */ +#endif /* HAVE_SETUP_TC */ + +#ifdef HAVE_RHEL7_NET_DEVICE_OPS_EXT + .ndo_size = sizeof(const struct net_device_ops), +#endif + +#ifdef IFLA_VF_MAX + .ndo_set_vf_mac = zxdh_en_ndo_set_vf_mac, +#ifdef HAVE_RHEL7_NETDEV_OPS_EXT_NDO_SET_VF_VLAN + .extended.ndo_set_vf_vlan = zxdh_en_ndo_set_vf_port_vlan, +#else + .ndo_set_vf_vlan = zxdh_en_ndo_set_vf_port_vlan, +#endif +#ifdef HAVE_NDO_SET_VF_MIN_MAX_TX_RATE +#ifdef ZXDH_PLCR_OPEN + .ndo_set_vf_rate = zxdh_en_ndo_set_vf_rate, +#else + .ndo_set_vf_rate = zxdh_en_ndo_set_vf_bw, +#endif +#else + .ndo_set_vf_rate = zxdh_en_ndo_set_vf_bw, +#endif + .ndo_get_vf_config = zxdh_en_ndo_get_vf_config, +#ifdef HAVE_VF_SPOOFCHK_CONFIGURE + .ndo_set_vf_spoofchk = zxdh_en_ndo_set_vf_spoofchk, +#endif +#ifdef HAVE_NDO_SET_VF_TRUST +#ifdef HAVE_RHEL7_NET_DEVICE_OPS_EXT + .extended.ndo_set_vf_trust = zxdh_en_ndo_set_vf_trust, +#else + .ndo_set_vf_trust = zxdh_en_ndo_set_vf_trust, +#endif /* HAVE_RHEL7_NET_DEVICE_OPS_EXT */ +#endif /* HAVE_NDO_SET_VF_TRUST */ +#endif /* IFLA_VF_MAX */ + +#ifdef HAVE_UDP_ENC_RX_OFFLOAD +#ifdef HAVE_VXLAN_RX_OFFLOAD +#if IS_ENABLED(CONFIG_VXLAN) + .ndo_add_vxlan_port = zxdh_en_add_vxlan_port, + .ndo_del_vxlan_port = zxdh_en_del_vxlan_port, +#endif +#endif /* HAVE_VXLAN_RX_OFFLOAD */ + +#ifdef HAVE_GENEVE_RX_OFFLOAD +#if IS_ENABLED(CONFIG_GENEVE) + .ndo_add_geneve_port = zxdh_en_add_geneve_port, + .ndo_del_geneve_port = zxdh_en_del_geneve_port, +#endif +#endif /* HAVE_GENEVE_RX_OFFLOAD */ +#endif /* HAVE_UDP_ENC_RX_OFFLOAD */ + +#ifdef HAVE_NDO_GET_PHYS_PORT_ID + .ndo_get_phys_port_id = zxdh_en_get_phys_port_id, +#endif /* HAVE_NDO_GET_PHYS_PORT_ID */ + + .ndo_set_features = zxdh_en_set_features, + +#ifdef HAVE_FDB_OPS + .ndo_fdb_add = zxdh_en_ndo_fdb_add, + .ndo_fdb_del = zxdh_en_ndo_fdb_del, +#ifdef HAVE_NDO_FEATURES_CHECK + .ndo_features_check = zxdh_en_features_check, +#endif /* HAVE_NDO_FEATURES_CHECK */ +#ifdef HAVE_BRIDGE_ATTRIBS + .ndo_bridge_getlink = zxdh_en_ndo_bridge_getlink, + .ndo_bridge_setlink = zxdh_en_ndo_bridge_setlink, +#endif /* HAVE_BRIDGE_ATTRIBS */ +#endif /* HAVE_FDB_OPS */ + +#ifdef HAVE_UDP_TUNNEL_OPS + .ndo_udp_tunnel_add = udp_tunnel_nic_add_port, + .ndo_udp_tunnel_del = udp_tunnel_nic_del_port, +#endif + +#ifdef HAVE_RHEL6_NET_DEVICE_OPS_EXT +}; + +/* RHEL6 keeps these operations in a separate structure */ +static const struct net_device_ops_ext zxdh_netdev_ops_ext = +{ + .size = sizeof(struct net_device_ops_ext), +#endif /* HAVE_RHEL6_NET_DEVICE_OPS_EXT */ + +#ifdef HAVE_NDO_SET_FEATURES + .ndo_set_features = zxdh_en_set_features, +#endif /* HAVE_NDO_SET_FEATURES */ + +#ifdef HAVE_NDO_SET_VF_LINK_STATE + .ndo_set_vf_link_state = zxdh_en_ndo_set_vf_link_state, +#endif +}; + +static void priv_flags_init(struct zxdh_en_priv *priv) +{ + priv->edev.pflags = 0; + + priv->edev.pflags &= BIT(ZXDH_PFLAG_ENABLE_LLDP); /* LLDP默认为开 */ +} + +static int32_t get_max_num_qs(struct zxdh_en_container *en_con) +{ + return en_con->ops->is_bond(en_con->parent) ? ZXDH_BOND_ETH_MQ_PAIRS_NUM : max_pairs; +} + +static int32_t fw_version_init(struct zxdh_en_device *en_dev) +{ + int32_t ret = 0; + uint8_t fw_version[ETHTOOL_FWVERS_LEN] = {0}; + uint8_t fw_version_len = 0; + + ret = zxdh_en_firmware_version_get(en_dev, fw_version, &fw_version_len); + if (ret != 0) + { + LOG_ERR("zxdh_en_firmware_version_get err, ret %d!!!!\n", ret); + return ret; + } + if (fw_version_len > ETHTOOL_FWVERS_LEN) + { + LOG_ERR("fw_version_len (%d) greater than 31!!!!\n", fw_version_len); + return -1; + } + + fw_version[ETHTOOL_FWVERS_LEN - 1] = '\0'; + en_dev->fw_version_len = ETHTOOL_FWVERS_LEN; + memcpy(en_dev->fw_version, (uint8_t *)fw_version, en_dev->fw_version_len); + LOG_INFO("fw_version:%s\n", en_dev->fw_version); + + return 0; +} + +int32_t zxdh_priv_init(struct zxdh_en_priv *priv, struct net_device *netdev) +{ + int32_t ret = 0; + struct zxdh_en_device *en_dev = &priv->edev; + + mutex_init(&priv->lock); + priv_flags_init(priv); + en_dev->msglevel = NETIF_MSG_LINK; + + /* 优先级4，暂时写死不支持 */ + en_dev->wol_support = 0; + en_dev->wolopts = 0; + + ret = fw_version_init(en_dev); + if (ret != 0) + { + LOG_ERR("fw_version_init err ret: %d\n", ret); + return ret; + } + + return 0 ; +} + +struct net_device *zxdh_create_netdev(struct zxdh_en_container *en_con) +{ + struct net_device *netdev = NULL; + struct zxdh_en_priv *en_priv = NULL; + struct dh_core_dev *dh_dev = en_con->parent; + + netdev = alloc_etherdev_mqs(sizeof(struct zxdh_en_priv), get_max_num_qs(en_con), get_max_num_qs(en_con)); + if (unlikely(netdev == NULL)) + { + LOG_ERR("alloc_etherdev_mqs() failed\n"); + return NULL; + } + + en_priv = netdev_priv(netdev); + + en_priv->edev.parent = dh_dev; + en_priv->edev.ops = en_con->ops; + en_priv->edev.netdev = netdev; + + zxdh_priv_init(en_priv, netdev); + + netif_carrier_off(netdev); + netif_tx_disable(netdev); + dev_net_set(netdev, dh_core_net(dh_dev)); + + return netdev; +} + +void zxdh_netdev_features_init(struct net_device *netdev) +{ + netdev->features |= NETIF_F_RXCSUM | + NETIF_F_HW_CSUM | + NETIF_F_TSO | + NETIF_F_SG | + NETIF_F_GSO | + NETIF_F_LRO | + NETIF_F_TSO6 | + NETIF_F_GRO | + NETIF_F_HW_VLAN_STAG_FILTER | + NETIF_F_HW_VLAN_CTAG_FILTER | + NETIF_F_GSO_UDP_TUNNEL_CSUM | + NETIF_F_RXHASH; + + netdev->hw_features |= NETIF_F_RXCSUM | + NETIF_F_HW_CSUM | + NETIF_F_TSO | + NETIF_F_SG | + NETIF_F_GSO | + NETIF_F_LRO | + NETIF_F_TSO6 | + NETIF_F_GRO | + NETIF_F_HW_VLAN_STAG_FILTER | + NETIF_F_HW_VLAN_CTAG_FILTER | + NETIF_F_GSO_UDP_TUNNEL_CSUM | + NETIF_F_HW_VLAN_CTAG_RX | + NETIF_F_HW_VLAN_CTAG_TX | + NETIF_F_HW_VLAN_STAG_RX | + NETIF_F_HW_VLAN_STAG_TX | + NETIF_F_RXHASH; + + netdev->hw_enc_features |= NETIF_F_RXCSUM | + NETIF_F_HW_CSUM | + NETIF_F_GSO_UDP_TUNNEL_CSUM; + + return; +} + +extern const struct xfrmdev_ops zxdh_xfrmdev_ops; +static void zxdh_build_nic_netdev(struct net_device *netdev) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct dh_core_dev *dh_dev = en_priv->edev.parent; + + SET_NETDEV_DEV(netdev, &dh_dev->parent->pdev->dev); + + netdev->netdev_ops = &zxdh_netdev_ops; + +#ifdef ZXDH_SEC + /*内核 sec相关*/ + netdev->features |=NETIF_F_HW_ESP; + netdev->xfrmdev_ops = &zxdh_xfrmdev_ops; +#endif + +#ifdef HAVE_RHEL6_ETHTOOL_OPS_EXT_STRUCT + zxdh_en_set_ethtool_ops_ext(netdev); +#else + zxdh_en_set_ethtool_ops(netdev); +#endif /* HAVE_RHEL6_ETHTOOL_OPS_EXT_STRUCT */ + + zxdh_netdev_features_init(netdev); +} + +int32_t zxdh_en_bond_get_mac(struct net_device *netdev, uint8_t pannel_id, uint8_t *mac) +{ + int32_t ret = 0; + union zxdh_msg msg = {0}; + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + + msg.payload.hdr_to_agt.op_code = AGENT_FLASH_MAC_READ; + msg.payload.flash_read_msg.index = pannel_id; + + ret = zxdh_send_command_to_specify(en_dev, MODULE_FLASH, &msg, &msg); + if (ret != 0) + { + LOG_ERR("zxdh_send_command_to_specify failed: %d\n", ret); + return ret; + } + + LOG_INFO("bond get mac %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n", msg.reps.flash_mac_read_msg.mac[0],\ + msg.reps.flash_mac_read_msg.mac[1],msg.reps.flash_mac_read_msg.mac[2], msg.reps.flash_mac_read_msg.mac[3],\ + msg.reps.flash_mac_read_msg.mac[4], msg.reps.flash_mac_read_msg.mac[5]); + + ether_addr_copy(mac, msg.reps.flash_mac_read_msg.mac); + return ret; +} + +int32_t zxdh_mac_addr_init(struct net_device *netdev) +{ + uint8_t mac[6] = {0}; + uint8_t pannel_id = 0; + int32_t ret = 0; + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + + if (en_dev->ops->is_bond(en_dev->parent)) + { + pannel_id = en_dev->pannel_id; + ret = zxdh_en_bond_get_mac(netdev, pannel_id, mac); + if (ret != 0) + { + LOG_ERR("zxdh_en_bond_mac_get failed: %d\n", ret); + } + } + else + { + en_dev->ops->get_mac(en_dev->parent, mac); + } + + if (!is_valid_ether_addr(mac)) + { + get_random_bytes(mac, 6); + mac[0] &= 0xfe; + LOG_INFO("set random mac %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + } + LOG_INFO("set mac %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + memcpy(netdev->dev_addr, mac, 6); + + return ret; +} + +int32_t zxdh_status_init(struct net_device *netdev) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + + if (en_dev->ops->if_init(en_dev->parent)) + { + zxdh_vp_reset(netdev); + } + + /* Disable VQ/configuration callbacks. */ + zxdh_vp_disable_cbs(netdev); + + zxdh_add_status(netdev, ZXDH_CONFIG_S_ACKNOWLEDGE); + + zxdh_add_status(netdev, ZXDH_CONFIG_S_DRIVER); + + /* fix features, not set features*/ + zxdh_pf_features_init(netdev); + + might_sleep(); + zxdh_add_status(netdev, ZXDH_CONFIG_S_FEATURES_OK); + if (!zxdh_has_status(netdev, ZXDH_CONFIG_S_FEATURES_OK)) + { + LOG_ERR("device refuses features ok\n"); + return -ENODEV; + } + + return 0; +} + +void zxdh_device_ready(struct net_device *netdev) +{ + zxdh_vp_enable_cbs(netdev); + + zxdh_add_status(netdev, ZXDH_CONFIG_S_DRIVER_OK); +} + +void zxdh_link_state_notify_kernel(struct net_device *netdev) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + + if(en_dev->ops->get_pf_link_up(en_dev->parent)) + { + netif_carrier_off(netdev); + udelay(10); + netif_carrier_on(netdev); + } + else + { + netif_carrier_on(netdev); + udelay(10); + netif_carrier_off(netdev); + } +} + +int32_t aux_get_bond_attrs(struct zxdh_en_device *en_dev, struct zxdh_lag_attrs *attr) +{ + *attr = (struct zxdh_lag_attrs) + { + .pannel_id = en_dev->pannel_id, + .vport = en_dev->vport, + .slot_id = en_dev->slot_id, + .qid[0] = en_dev->phy_index[0], + .qid[1] = en_dev->phy_index[1], + .pcie_id = en_dev->pcie_id, + .phy_port = en_dev->phy_port, + }; + + LOG_INFO("bond pf: pannel %hu, vport 0x%hx, phy_qid[0] %u, phy_qid[1] %u, pcie id 0x%x\n", + attr->pannel_id, attr->vport, attr->qid[0], attr->qid[1], attr->pcie_id); + + return 0; +} + +void aux_set_netdev_name(struct net_device *netdev, uint16_t pannel_id) +{ + struct zxdh_en_device *en_dev = NULL; + struct zxdh_en_priv *en_priv = NULL; + + en_priv = netdev_priv(netdev); + en_dev = &en_priv->edev; + + if (en_dev->ops->is_bond(en_dev->parent)) + { + netdev->dev_port = pannel_id + 1; + } +} + +int32_t zxdh_en_mtu_init(struct net_device *netdev) +{ + netdev->min_mtu = ETH_MIN_MTU; + netdev->max_mtu = ZXDH_MAX_MTU; + + return zxdh_en_config_mtu_to_np(netdev, ZXDH_DEFAULT_MTU); +} + +static int32_t zxdh_en_dev_probe(struct zxdh_auxiliary_device *adev, const struct zxdh_auxiliary_device_id *id) +{ + struct zxdh_en_container *en_container = container_of(adev, struct zxdh_en_container, adev); + struct net_device *netdev = NULL; + struct zxdh_en_priv *en_priv = NULL; + struct zxdh_en_device *en_dev = NULL; + struct zxdh_lag_attrs lag_attrs; + int32_t err = 0; + int32_t vqs_channel_num = 0; + + LOG_INFO("aux level driver probe start\n"); + + netdev = zxdh_create_netdev(en_container); + if (unlikely(netdev == NULL)) + { + LOG_ERR("zxdh_create_netdev is null\n"); + err = -ENOMEM; + goto err_create_netdev; + } + + zxdh_build_nic_netdev(netdev); + + dev_set_drvdata(&adev->dev, netdev_priv(netdev)); + + en_priv = netdev_priv(netdev); + en_dev = &en_priv->edev; + en_dev->channels_num = en_dev->ops->get_channels_num(en_dev->parent); + en_dev->ops->set_rdma_netdev(en_dev->parent, netdev); + en_dev->curr_unicast_num = 0; + en_dev->curr_multicast_num = 0; + en_dev->init_comp_flag = AUX_INIT_INCOMPLETED; + en_dev->delay_statistics_enable = 0; + + vqs_channel_num = en_dev->ops->create_vqs_channels(en_dev->parent); + if (vqs_channel_num < 0) + { + LOG_ERR("create_vqs_channels failed, vqs_channel_num: %d\n", vqs_channel_num); + err = vqs_channel_num; + goto err_create_vqs_channels; + } + + err = dh_aux_eq_table_init(en_priv); + if (err != 0) + { + LOG_ERR("Failed to alloc IRQs: %d\n", err); + goto err_eq_table_init; + } + + err = dh_aux_events_init(en_priv); + if (err != 0) + { + LOG_ERR("dh_aux_events_init failed: %d\n", err); + goto err_events_init; + } + + err = dh_aux_eq_table_create(en_priv); + if (err != 0) + { + LOG_ERR("Failed to alloc EQs: %d\n", err); + goto err_eq_table_create; + } + + err = zxdh_status_init(netdev); + if (err != 0) + { + LOG_ERR("zxdh_status_init failed: %d\n", err); + goto err_status_init; + } + + en_dev->ep_bdf = en_dev->ops->get_epbdf(en_dev->parent); + en_dev->vport = en_dev->ops->get_vport(en_dev->parent); + en_dev->pcie_id = en_dev->ops->get_pcie_id(en_dev->parent); + en_dev->slot_id = en_dev->ops->get_slot_id(en_dev->parent); + LOG_INFO("ep_bdf: 0x%x, vport: 0x%x, pcie_id: %d, slot_id: %d\n", en_dev->ep_bdf, en_dev->vport, en_dev->pcie_id, en_dev->slot_id); + + err = zxdh_vqs_init(netdev); + if (err != 0) + { + LOG_ERR("zxdh_vqs_init failed: %d\n", err); + goto err_vqs_init; + } + + if (en_dev->ops->is_upf(en_dev->parent)) + { + en_dev->hash_search_idx = 2;//FIXME + } + else if (!en_dev->ops->is_bond(en_dev->parent)) + { + err = zxdh_hash_id_get(en_dev); + if (err != 0) + { + LOG_ERR("zxdh_hash_id_get failed: %d\n", err); + goto err_do_vqs_free; + } + + err = zxdh_panel_id_get(en_dev); + if (err != 0) + { + LOG_ERR("zxdh_panel_id_get failed: %d\n", err); + goto err_do_vqs_free; + } + } + + en_dev->hash_func = ZXDH_FUNC_TOP; + if(en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) + { + if (en_dev->ops->is_bond(en_dev->parent)) + { + err = zxdh_aux_alloc_pannel(en_dev); + if (err != 0) + { + LOG_ERR("zxdh_aux_alloc_pannel failed: %d\n", err); + goto err_do_vqs_free; + } + } + else if (!en_dev->ops->is_upf(en_dev->parent)) + { + err = zxdh_phyport_get(en_dev); + if (err != 0) + { + LOG_ERR("zxdh_phyport_get failed: %d\n", err); + goto err_do_vqs_free; + } + } + + err = zxdh_mac_addr_init(netdev); + if (err != 0) + { + LOG_ERR("zxdh_mac_addr_init failed: %d\n", err); + goto err_do_vqs_free; + } + + err = zxdh_pf_port_init(netdev); + if (err != 0) + { + LOG_ERR("zxdh_pf_port_init failed: %d\n", err); + goto err_do_vqs_free; + } + } + else + { + err = zxdh_vf_dpp_port_init(netdev); + if (err != 0) + { + LOG_ERR("zxdh_vf_dpp_port_init failed: %d\n", err); + goto err_do_vqs_free; + } + } + + if (!en_dev->ops->is_bond(en_dev->parent)) + { + netdev->priv_flags &= ~IFF_RXFH_CONFIGURED; + err = zxdh_num_channels_changed(en_dev, en_dev->curr_queue_pairs); + if (err != 0) + { + LOG_ERR("zxdh_num_channels_changed failed: %d\n", err); + goto err_do_vport_free; + } + } + + err = zxdh_common_tbl_init(netdev); + if (err != 0) + { + LOG_ERR("zxdh_common_tlb_init failed: %d\n", err); + goto err_do_rxfh_free; + } + + zxdh_device_ready(netdev); + + err = zxdh_en_mtu_init(netdev); + if (err != 0) + { + LOG_ERR("zxdh_en_mtu_init failed: %d\n", err); + goto err_do_rxfh_free; + } + + en_dev->hw_stats.q_stats = kmalloc_array(max_pairs, sizeof(struct zxdh_en_queue_stats), GFP_KERNEL); + if (unlikely(en_dev->hw_stats.q_stats == NULL)) + { + LOG_ERR("hw_stats.q_stats kmalloc failed\n"); + goto err_do_rxfh_free; + } + memset(en_dev->hw_stats.q_stats, 0, max_pairs * sizeof(struct zxdh_en_queue_stats)); + memset(&en_dev->pre_stats, 0, sizeof(struct zxdh_en_vport_stats)); + + err = zxdh_en_vport_pre_stats_get(en_dev); + if(err != 0) + { + LOG_ERR("get vport pre stats failed, %d\n", err); + goto err_do_q_stats_free; + } + + aux_set_netdev_name(netdev, en_dev->pannel_id); + err = register_netdev(netdev); + if (err != 0) + { + LOG_ERR("register_netdev failed, %d\n", err); + goto err_do_q_stats_free; + } + + zxdh_en_bar_del_mac(netdev); + zxdh_en_bar_cfg_mac(netdev, netdev->dev_addr); + zxdh_link_state_notify_kernel(netdev); + + if (en_dev->ops->is_bond(en_dev->parent)) + { + aux_get_bond_attrs(en_dev, &lag_attrs); + zxdh_ldev_add_netdev(en_container->parent, en_dev->pannel_id, netdev, &lag_attrs); + } + +#ifdef ZXDH_PLCR_OPEN + err = zxdh_plcr_init(en_priv); + if (err != 0) + { + LOG_ERR("zxdh_plcr_init failed, %d\n", err); + } +#endif + + en_dev->init_comp_flag = AUX_INIT_COMPLETED; + + err = dh_aux_ipv6_notifier_init(en_priv); + if (err != 0) + { + LOG_ERR("dh_aux_ipv6_notifier_init failed: %d\n", err); + goto err_ipv6_notifier_init; + } + + if(en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) + { + en_dev->autoneg_enable = AUTONEG_ENABLE; + err = zxdh_en_phyport_init(en_dev); + if (err != 0) + { + LOG_ERR("zxdh_en_phyport_init failed: %d\n", err); + goto err_phyport_init; + } + } + +#ifdef ZXDH_MSGQ + NEED_MSGQ(en_dev) + { + err = zxdh_msgq_init(en_dev); + if (err) + { + LOG_ERR("zxdh_msgq_init failed: %d\n", err); + goto err_phyport_init; + } + } +#endif + + en_dev->ops->set_init_comp_flag(en_dev->parent); + + if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) + { + /* clear mcode gate,successfully build the scheduling tree, and then open it again */ + zxdh_dcbnl_set_tm_pport_mcode_gate_close(netdev); +#ifdef ZXDH_DCBNL_OPEN + err = zxdh_dcbnl_initialize(netdev); + if (err != 0) + { + LOG_ERR("zxdh_dcbnl_initialize failed: %d\n", err); + } +#endif + } + + en_dev->ops->set_bond_num(en_dev->parent, true); + LOG_INFO("%s: aux level driver probe completed\n", netdev->name); + + return 0; + +err_phyport_init: + dh_inet6_addr_change_notifier_unregister(&(en_dev->ipv6_notifier)); +err_ipv6_notifier_init: + if (en_dev->ops->is_bond(en_dev->parent)) + { + aux_get_bond_attrs(en_dev, &lag_attrs); + zxdh_ldev_remove_netdev(en_dev->parent, netdev, &lag_attrs); + } + unregister_netdev(netdev); +err_do_q_stats_free: + kfree(en_dev->hw_stats.q_stats); +err_do_rxfh_free: + if (!en_dev->ops->is_bond(en_dev->parent)) + { + zxdh_rxfh_del(en_dev); + } +err_do_vport_free: + zxdh_vport_uninit(netdev); +err_do_vqs_free: + zxdh_vqs_uninit(netdev); +err_vqs_init: + zxdh_add_status(netdev, ZXDH_CONFIG_S_FAILED); +err_status_init: + dh_aux_eq_table_destroy(en_priv); +err_eq_table_create: + dh_aux_events_uninit(en_priv); +err_events_init: + dh_aux_eq_table_cleanup(en_priv); +err_eq_table_init: + en_dev->ops->destroy_vqs_channels(en_dev->parent); + en_dev->ops->release_port(en_dev->parent, en_dev->pannel_id); +err_create_vqs_channels: + free_netdev(netdev); +err_create_netdev: + return err; +} + +static int32_t zxdh_en_dev_remove(struct zxdh_auxiliary_device *adev) +{ + struct zxdh_en_priv *en_priv = (struct zxdh_en_priv *)dev_get_drvdata(&adev->dev); + struct zxdh_en_device *en_dev = &en_priv->edev; + struct net_device *netdev = en_dev->netdev; + struct zxdh_lag_attrs lag_attrs; + + LOG_INFO("%s: aux level driver remove start\n", netdev->name); + + en_dev->ops->set_bond_num(en_dev->parent, false); + dh_inet6_addr_change_notifier_unregister(&(en_dev->ipv6_notifier)); +#ifdef ZXDH_MSGQ + NEED_MSGQ(en_dev) + { + zxdh_msgq_exit(en_dev); + } +#endif + +#ifdef ZXDH_PLCR_OPEN + zxdh_plcr_uninit(en_priv); +#endif + + if (en_dev->ops->is_bond(en_dev->parent)) + { + aux_get_bond_attrs(en_dev, &lag_attrs); + zxdh_ldev_remove_netdev(en_dev->parent, netdev, &lag_attrs); + } + + #ifdef ZXDH_DCBNL_OPEN + zxdh_dcbnl_ets_uninit(netdev); + #endif + + unregister_netdev(netdev); + kfree(en_dev->hw_stats.q_stats); + + if (!en_dev->ops->is_bond(en_dev->parent)) + { + zxdh_rxfh_del(en_dev); + } + + zxdh_vport_uninit(netdev); + + zxdh_vqs_uninit(netdev); + + zxdh_add_status(netdev, ZXDH_CONFIG_S_FAILED); + + dh_aux_eq_table_destroy(en_priv); + dh_aux_events_uninit(en_priv); + dh_aux_eq_table_cleanup(en_priv); + en_dev->ops->destroy_vqs_channels(en_dev->parent); + en_dev->ops->release_port(en_dev->parent, en_dev->pannel_id); + free_netdev(netdev); + LOG_INFO("aux level driver remove completed\n"); + + return 0; +} + +static void zxdh_en_dev_shutdown(struct zxdh_auxiliary_device *adev) +{ + LOG_INFO("aux level driver shutdown start\n"); + zxdh_en_dev_remove(adev); + LOG_INFO("aux level driver shutdown completed\n"); +}; + +static const struct zxdh_auxiliary_device_id zxdh_en_dev_id_table[] = { + { .name = ZXDH_PF_NAME "." ZXDH_EN_DEV_ID_NAME, }, + { }, +}; + +MODULE_DEVICE_TABLE(zxdh_auxiliary, zxdh_en_dev_id_table); + +static struct zxdh_auxiliary_driver zxdh_en_driver = { + .name = ZXDH_EN_DEV_ID_NAME, + .probe = zxdh_en_dev_probe, + .remove = zxdh_en_dev_remove, + .shutdown = zxdh_en_dev_shutdown, + .id_table = zxdh_en_dev_id_table, +}; + +int32_t zxdh_en_driver_register(void) +{ + int32_t err = 0; + + if ((max_pairs == 0) || (max_pairs >= ZXDH_MAX_PAIRS_NUM)) + { + LOG_INFO("max_pairs %u parameter is a invalid value, use the default value %u\n", max_pairs, ZXDH_MQ_PAIRS_NUM); + max_pairs = ZXDH_MQ_PAIRS_NUM; + } + + err = zxdh_auxiliary_driver_register(&zxdh_en_driver); + if (err != 0) + { + LOG_ERR("zxdh_auxiliary_driver_register failed: %d\n", err); + goto err_aux_register; + } + + err = dh_aux_msg_recv_func_register(); + if (err != 0) + { + LOG_ERR("dh_aux_msg_recv_func_register failed: %d\n", err); + goto err_msg_recv_register; + } + + err = zxdh_tools_netlink_register(); + if (err != 0) + { + LOG_ERR("zxdh_tools_msg_family register error failed: %d\n", err); + goto err_netlink_register; + } + + LOG_INFO("all driver insmod completed\n"); + + return 0; + +err_netlink_register: + dh_aux_msg_recv_func_unregister(); +err_msg_recv_register: + zxdh_auxiliary_driver_unregister(&zxdh_en_driver); +err_aux_register: + return err; +} + +void zxdh_en_driver_unregister(void) +{ + LOG_INFO("driver rmmod start\n"); + zxdh_tools_netlink_unregister(); + dh_aux_msg_recv_func_unregister(); + zxdh_auxiliary_driver_unregister(&zxdh_en_driver); +} + +module_init(zxdh_en_driver_register); +module_exit(zxdh_en_driver_unregister); diff --git a/src/net/drivers/net/ethernet/dinghai/en_aux.h b/src/net/drivers/net/ethernet/dinghai/en_aux.h new file mode 100755 index 0000000..6c7755a --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_aux.h @@ -0,0 +1,373 @@ +#ifndef __ZXDH_EN_AUX_H__ +#define __ZXDH_EN_AUX_H__ + +#include "msg_common.h" +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include +#include +#include +#include "./en_aux/queue.h" +#include "./en_aux/en_cmd.h" +#include "./en_pf.h" +#include "./en_aux/dcbnl/en_dcbnl.h" + +#define MAX_VLAN_ID 4095 + +#define PF_AC_MASK 0x800 +#define FILTER_MAC 0xAA +#define UNFILTER_MAC 0xFF + +#define AUX_INIT_INCOMPLETED 0 +#define AUX_INIT_COMPLETED 1 + +#define IS_DELAY_STATISTICS_PKT 0 +#define IS_NOT_DELAY_STATICTICS_PKT 1 + +#define ADD_IP6MAC 1 +#define DEL_IP6MAC 2 + +#define ZXDH_SET_FEATURE(features, feature, enable) \ + do { \ + if (enable) \ + { \ + *features |= feature; \ + } \ + else \ + { \ + *features &= ~feature; \ + } \ + } while (0) + +#define ZXDH_AUX_INIT_COMP_CHECK(en_dev) \ + do { \ + if (en_dev->init_comp_flag != AUX_INIT_COMPLETED) \ + { \ + return; \ + } \ + } while (0) + +typedef int (*zxdh_feature_handler)(struct net_device *netdev, bool enable); + +extern uint32_t max_pairs; + +struct zxdh_rdma_if; +struct zxdh_en_if; + +struct zxdh_en_container { + struct zxdh_auxiliary_device adev; + struct zxdh_rdma_dev_info *rdma_infos; + struct zxdh_rdma_if *rdma_ops; + struct zxdh_en_if *ops; + struct dh_core_dev *parent; + int32_t aux_id; +}; + +struct zxdh_en_queue_stats +{ + uint64_t q_rx_pkts; + uint64_t q_tx_pkts; + uint64_t q_rx_bytes; + uint64_t q_tx_bytes; + uint64_t q_tx_stopped; + uint64_t q_tx_wake; + uint64_t q_tx_dropped; +}; + +struct zxdh_en_netdev_stats +{ + uint64_t rx_packets; + uint64_t tx_packets; + uint64_t rx_bytes; + uint64_t tx_bytes; + uint64_t tx_queue_wake; + uint64_t tx_queue_stopped; + uint64_t tx_queue_dropped; +}; + +struct zxdh_en_vport_vqm_stats +{ + uint64_t rx_vport_packets; + uint64_t tx_vport_packets; + uint64_t rx_vport_bytes; + uint64_t tx_vport_bytes; + uint64_t rx_vport_dropped; +}; + +struct zxdh_en_vport_np_stats +{ + uint64_t rx_vport_broadcast_packets; + uint64_t tx_vport_broadcast_packets; + uint64_t rx_vport_mtu_drop_packets; + uint64_t tx_vport_mtu_drop_packets; + uint64_t rx_vport_mtu_drop_bytes; + uint64_t tx_vport_mtu_drop_bytes; + uint64_t rx_vport_plcr_drop_packets; + uint64_t tx_vport_plcr_drop_packets; + uint64_t rx_vport_plcr_drop_bytes; + uint64_t tx_vport_plcr_drop_bytes; +}; + + +struct zxdh_en_vport_stats +{ + struct zxdh_en_vport_vqm_stats vqm_stats; + struct zxdh_en_vport_np_stats np_stats; +}; + +struct zxdh_en_phy_stats +{ + uint64_t rx_packets_phy; + uint64_t tx_packets_phy; + uint64_t rx_bytes_phy; + uint64_t tx_bytes_phy; + uint64_t rx_errors; + uint64_t tx_errors; + uint64_t rx_discards; + uint64_t tx_drop; + uint64_t rx_multicast_phy; + uint64_t tx_multicast_phy; + uint64_t rx_broadcast_phy; + uint64_t tx_broadcast_phy; + uint64_t rx_size_64_phy; + uint64_t rx_size_65_127; + uint64_t rx_size_128_255; + uint64_t rx_size_256_511; + uint64_t rx_size_512_1023; + uint64_t rx_size_1024_1518; + uint64_t rx_size_1519_mru; + uint64_t rx_pause; + uint64_t tx_pause; +}__attribute__((packed)); + +struct zxdh_en_hw_stats +{ + struct zxdh_en_netdev_stats netdev_stats; + struct zxdh_en_vport_stats vport_stats; + struct zxdh_en_phy_stats phy_stats; + struct zxdh_en_queue_stats *q_stats; +}; + +struct zxdh_vlan_dev +{ + uint8_t qos; + uint8_t rsv; + uint16_t protcol; + uint16_t vlan_id; +}; + +/* drs sec */ +typedef struct +{ + uint64_t SecVAddr; /*每个设备的sec私有内存的虚拟基地址*/ + uint64_t SecPAddr; /*每个设备的sec私有内存的物理基地址*/ + uint32_t SecMemSize; /*每个设备的sec私有内存的大小*/ +}zxdh_sec_pri; + + +struct zxdh_en_device { + struct dh_core_dev *parent; + struct net_device *netdev; + void *msgq_dev; + struct zxdh_en_if *ops; + struct zxdh_en_hw_stats hw_stats; + struct zxdh_en_vport_stats pre_stats; + struct zxdh_vlan_dev vlan_dev; + + uint32_t device_id; + uint32_t vendor_id; + + uint64_t driver_feature; + uint64_t device_feature; + uint64_t guest_feature; + + struct list_head vqs_list; + spinlock_t vqs_list_lock; + uint32_t indir_rqt[ZXDH_INDIR_RQT_SIZE]; + + int32_t channels_num; + + /* a list of queues so we can dispatch IRQs */ + spinlock_t lock; + struct list_head virtqueues; + /* array of all queues for house-keeping */ + struct zxdh_pci_vq_info **vqs; + + struct send_queue *sq; + struct receive_queue *rq; + uint32_t status; + + /* Max # of queue pairs supported by the device */ + uint16_t curr_queue_pairs; + uint16_t max_queue_pairs; + + bool need_msgq; + /* Host can handle any s/g split between our header and packet data */ + bool any_header_sg; + /* Packet custom queue header size */ + uint8_t hdr_len; + /* Work struct for refilling if we run low on memory. */ + struct delayed_work refill; + + /* CPU hotplug instances for online & dead */ + struct hlist_node node; + struct hlist_node node_dead; + + bool np_direction; + bool drs_offload; + bool dtp_offload; + + uint32_t phy_index[ZXDH_MAX_QUEUES_NUM]; + + uint8_t link_check_bit; + uint8_t pannel_id; + uint8_t rsv[2]; + + uint16_t ep_bdf; + uint16_t pcie_id; + /* vfunc_active */ + uint16_t slot_id; + uint16_t vport; + uint8_t phy_port; + uint8_t panel_id; + uint8_t hash_search_idx; + uint8_t hash_func; + + uint32_t link_speed; + bool link_up; + uint8_t duplex; + + uint32_t speed; + uint32_t autoneg_enable; + uint32_t supported_speed_modes; + uint32_t advertising_speed_modes; + + bool promisc_enabled; + bool allmulti_enabled; + uint32_t pflags; + uint8_t clock_no; + uint32_t msglevel; + uint32_t wol_support; + uint32_t wolopts; + uint8_t fw_version[ETHTOOL_FWVERS_LEN]; + uint8_t fw_version_len; + uint32_t vf_1588_call_np_num; + uint32_t ptp_tc_enable_opt; + uint32_t delay_statistics_enable; + + struct work_struct vf_link_info_update_work; + struct work_struct link_info_irq_update_vf_work; + struct work_struct link_info_irq_process_work; + struct work_struct link_info_irq_update_np_work; + struct work_struct rx_mode_set_work; + + uint8_t curr_unicast_num; + uint8_t curr_multicast_num; + struct work_struct pf_notify_vf_link_state_work; + struct work_struct pf2vf_msg_proc_work; + struct work_struct pf_notify_vf_reset_work; + struct work_struct service_task; + struct work_struct service_riscv_task; + struct timer_list service_timer; + struct timer_list service_riscv_timer; + struct work_struct riscv2aux_msg_proc_work; + /* QoS DCB */ + struct zxdh_dcbnl_para dcb_para; + /* SEC */ + zxdh_sec_pri drs_sec_pri; + + /* initialization completion flag */ + uint8_t init_comp_flag; + + struct notifier_block ipv6_notifier; +}; + +struct zxdh_en_priv { + struct zxdh_en_device edev; + struct mutex lock; + struct dh_eq_table eq_table; + struct dh_events *events; +}; + +#define DEV_UNICAST_MAX_NUM 32 /* 每个PF/VF存储的单播mac转发表上限 */ +#define DEV_MULTICAST_MAX_NUM 32 /* 每个PF/VF存储的组播mac转发表上限 */ +#define UNICAST_MAX_NUM (DEV_UNICAST_MAX_NUM * 257) +#define MULTICAST_MAX_NUM (DEV_MULTICAST_MAX_NUM * 257) + +int32_t dh_aux_eq_table_init(struct zxdh_en_priv *en_priv); +void dh_aux_eq_table_cleanup(struct zxdh_en_priv *en_priv); +int32_t zxdh_ip6mac_add(struct zxdh_en_device *en_dev, const uint32_t *addr6, const uint8_t *ip6mac); +int32_t zxdh_ip6mac_del(struct zxdh_en_device *en_dev, const uint32_t *addr6, const uint8_t *ip6mac); +struct zxdh_rdma_if { + void *(*get_rdma_netdev)(struct dh_core_dev *dh_dev); +}; + +struct zxdh_en_if { + uint16_t (*get_channels_num)(struct dh_core_dev *dh_dev); + int32_t (*create_vqs_channels)(struct dh_core_dev *dh_dev); + void (*destroy_vqs_channels)(struct dh_core_dev *dh_dev); + void (*switch_vqs_channel)(struct dh_core_dev *dh_dev, int32_t channel, int32_t op); + int32_t (*vqs_channel_bind_handler)(struct dh_core_dev *dh_dev, int32_t vqs_channel_num, struct dh_vq_handler *handler); + void (*vqs_channel_unbind_handler)(struct dh_core_dev *dh_dev, int32_t vqs_channel_num); + int32_t (*vq_bind_channel)(struct dh_core_dev *dh_dev, int32_t channel_num, int32_t queue_index); + void (*vq_unbind_channel)(struct dh_core_dev *dh_dev, int32_t queue_index); + int32_t (*vqs_bind_eqs)(struct dh_core_dev *dh_dev, int32_t vqs_channel_num, struct list_head *vq_node); + void (*vqs_unbind_eqs)(struct dh_core_dev *dh_dev, int32_t vqs_channel_num); + void __iomem * (*vp_modern_map_vq_notify)(struct dh_core_dev *dh_dev, uint32_t index, resource_size_t *pa); + void (*vp_modern_unmap_vq_notify)(struct dh_core_dev *dh_dev, void *priv); + int32_t (*get_phy_vq)(struct dh_core_dev *dh_dev, uint16_t index); + void (*activate_phy_vq)(struct dh_core_dev *dh_dev, uint32_t phy_index, int32_t queue_size, uint64_t desc_addr, uint64_t driver_addr, uint64_t device_addr); + void (*de_activate_phy_vq)(struct dh_core_dev *dh_dev, uint32_t phy_index); + int32_t (*release_phy_vq)(struct dh_core_dev *dh_dev, uint32_t *phy_index, uint16_t total_qnum); + void (*set_status)(struct dh_core_dev *dh_dev, uint8_t status); + uint8_t (*get_status)(struct dh_core_dev *dh_dev); + void (*set_vf_mac)(struct dh_core_dev *dh_dev, uint8_t *mac, int32_t vf_id); + void (*get_vf_mac)(struct dh_core_dev *dh_dev, uint8_t *mac, int32_t vf_id); + void (*set_mac)(struct dh_core_dev *dh_dev, uint8_t *mac); + void (*get_mac)(struct dh_core_dev *dh_dev, uint8_t *mac); + uint64_t (*get_features)(struct dh_core_dev *dh_dev); + void (*set_features)(struct dh_core_dev *dh_dev, uint64_t features); + uint16_t (*get_queue_num)(struct dh_core_dev *dh_dev); + uint16_t (*get_queue_size)(struct dh_core_dev *dh_dev, uint32_t index); + void (*set_queue_enable)(struct dh_core_dev *dh_dev, uint16_t index, bool enable); + uint32_t (*get_epbdf)(struct dh_core_dev *dh_dev); + uint16_t (*get_vport)(struct dh_core_dev *dh_dev); + uint16_t (*get_pcie_id)(struct dh_core_dev *dh_dev); + uint16_t (*get_slot_id)(struct dh_core_dev *dh_dev); + bool (*is_bond)(struct dh_core_dev *dh_dev); + bool (*is_upf)(struct dh_core_dev *dh_dev); + enum dh_coredev_type (*get_coredev_type)(struct dh_core_dev *dh_dev); + struct pci_dev * (*get_pdev)(struct dh_core_dev *dh_dev); + uint64_t (*get_bar_virt_addr)(struct dh_core_dev *dh_dev, uint8_t bar_num); + int32_t (*msg_send_cmd)(struct dh_core_dev *dh_dev, uint16_t module_id, void *msg, void *ack, bool is_sync); + int32_t (*async_eq_enable)(struct dh_core_dev *dh_dev, struct dh_eq_async *eq, const char *name, bool attach); + struct zxdh_vf_item *(*get_vf_item)(struct dh_core_dev *dh_dev, uint16_t vf_idx); + void (*set_pf_link_up) (struct dh_core_dev *dh_dev, bool link_up); + bool (*get_pf_link_up) (struct dh_core_dev *dh_dev); + void (*update_pf_link_info)(struct dh_core_dev *dh_dev, struct link_info_struct *link_info_val); + int32_t (*get_pf_drv_msg)(struct dh_core_dev *dh_dev, uint8_t *drv_version, uint8_t *drv_version_len); + void (*set_vepa) (struct dh_core_dev *dh_dev, bool setting); + bool (*get_vepa) (struct dh_core_dev *dh_dev); + void (*set_bond_num)(struct dh_core_dev *dh_dev, bool add); + bool (*if_init)(struct dh_core_dev *dh_dev); + int32_t (*request_port)(struct dh_core_dev *dh_dev, void *data); + int32_t (*release_port)(struct dh_core_dev *dh_dev, uint32_t port_id); + void (*get_link_info_from_vqm)(struct dh_core_dev *dh_dev, uint8_t *link_up); + void (*set_vf_link_info)(struct dh_core_dev *dh_dev, uint16_t vf_idx, uint8_t link_up); + void (*set_pf_phy_port)(struct dh_core_dev *dh_dev, uint8_t phy_port); + void (*set_rdma_netdev)(struct dh_core_dev *dh_dev, void *data); + uint8_t (*get_pf_phy_port)(struct dh_core_dev *dh_dev); + void (*set_init_comp_flag)(struct dh_core_dev *dh_dev); + struct zxdh_ipv6_mac_tbl * (*get_ip6mac_tbl)(struct dh_core_dev *dh_dev); +}; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/en_aux/dcbnl/en_dcbnl.c b/src/net/drivers/net/ethernet/dinghai/en_aux/dcbnl/en_dcbnl.c new file mode 100644 index 0000000..34bfadd --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_aux/dcbnl/en_dcbnl.c @@ -0,0 +1,877 @@ +//#include +#include "../../en_aux.h" +#include "en_dcbnl.h" +#include "en_np/qos/include/dpp_drv_qos.h" +#include "en_aux/en_cmd.h" +#include "en_dcbnl_api.h" + +static int zxdh_dcbnl_ieee_getets(struct net_device *netdev, struct ieee_ets *ets) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + uint32_t tc = 0; + uint32_t j = 0; + + if (en_dev->ops->get_coredev_type(en_dev->parent) != DH_COREDEV_PF) + { + LOG_ERR("zxdh_dcbnl_ieee_getets: coredev type is not a PF"); + return -EOPNOTSUPP; + } + + ets->willing = 0; + + ets->ets_cap = ZXDH_DCBNL_MAX_TRAFFIC_CLASS; + + memcpy(ets->tc_tsa, en_dev->dcb_para.ets_cfg.tc_tsa, sizeof(ets->tc_tsa)); + memcpy(ets->tc_tx_bw, en_dev->dcb_para.ets_cfg.tc_tx_bw, sizeof(ets->tc_tx_bw)); + memcpy(ets->prio_tc, en_dev->dcb_para.ets_cfg.prio_tc, sizeof(ets->prio_tc)); + + for (tc = 0; tc < ZXDH_DCBNL_MAX_TRAFFIC_CLASS; tc++) + { + if (ets->tc_tsa[tc] != IEEE_8021QAZ_TSA_ETS) + { + ets->tc_tx_bw[tc] = 0; + } + } + + /* debug */ + for (j = 0; j < ZXDH_DCBNL_MAX_TRAFFIC_CLASS; j++) + { + LOG_INFO(" idx:%d, ets->tc_tsa:%d, ets->tc_tx_bw:%d, ets->prio_tc:%d \n", j, + ets->tc_tsa[j], ets->tc_tx_bw[j], ets->prio_tc[j]); + } + + return 0; +} + +static int zxdh_dcbnl_check_ets_maxtc(struct ieee_ets *ets) +{ + uint32_t i; + + for (i = 0; i < ZXDH_DCBNL_MAX_PRIORITY; i++) + { + if (ets->prio_tc[i] >= ZXDH_DCBNL_MAX_TRAFFIC_CLASS) + { + LOG_ERR("dcbnl_check_ets: Failed! TC value greater than max(%d)\n", ZXDH_DCBNL_MAX_TRAFFIC_CLASS); + return 1; + } + } + return 0; +} + +static int zxdh_dcbnl_check_ets_tcbw(struct ieee_ets *ets) +{ + bool have_ets_tc = false; + uint32_t bw_sum = 0; + uint32_t i; + + for (i = 0; i < ZXDH_DCBNL_MAX_TRAFFIC_CLASS; i++) + { + if (ets->tc_tsa[i] == IEEE_8021QAZ_TSA_ETS) + { + have_ets_tc = true; + bw_sum += ets->tc_tx_bw[i]; + } + } + + if (have_ets_tc && ((bw_sum != 100) && (bw_sum != 0))) + { + LOG_ERR("dcbnl_check_ets_tcbw: Failed! ETS BW sum is illegal\n"); + return 1; + } + + return 0; +} + +static int zxdh_dcbnl_check_ets_para(struct ieee_ets *ets) +{ + uint32_t err = 0; + + err = zxdh_dcbnl_check_ets_maxtc(ets); + if (err) + { + return -EINVAL; + } + + err = zxdh_dcbnl_check_ets_tcbw(ets); + if (err) + { + return -EINVAL; + } + LOG_INFO(" end \n"); + return 0; +} + + +static int zxdh_dcbnl_ieee_divide_tc_type(struct ieee_ets *ets, uint8_t *tc_type) +{ + uint32_t i; + + for (i = 0; i < ZXDH_DCBNL_MAX_TRAFFIC_CLASS; i++) + { + switch (ets->tc_tsa[i]) + { + case IEEE_8021QAZ_TSA_ETS: + tc_type[i] = ets->tc_tx_bw[i] ? ZXDH_DCBNL_ETS_TC : ZXDH_DCBNL_ZEROBW_ETS_TC; + break; + case IEEE_8021QAZ_TSA_STRICT: + tc_type[i] = ZXDH_DCBNL_STRICT_TC; + break; + case IEEE_8021QAZ_TSA_VENDOR: + tc_type[i] = ZXDH_DCBNL_VENDOR_TC; + break; + default: + tc_type[i] = ZXDH_DCBNL_STRICT_TC; + LOG_ERR("dcbnl: %d tsa error, change to strict \n", ets->tc_tsa[i]); + break; + } + } + + return 0; +} + +static int zxdh_dcbnl_ieee_convert_tc_bw(struct ieee_ets *ets, uint8_t *tc_type, uint8_t *tc_tx_bw) +{ + uint32_t i; + uint8_t zero_ets_bw = 0; + uint8_t zero_ets_num = 0; + + for (i = 0; i < ZXDH_DCBNL_MAX_TRAFFIC_CLASS; i++) + { + if (tc_type[i] == ZXDH_DCBNL_ZEROBW_ETS_TC) + { + zero_ets_num++; + } + } + + if (zero_ets_num) + { + zero_ets_bw = (uint8_t)ZXDH_DCBNL_MAX_BW_ALLOC / zero_ets_num; + } + + for (i = 0; i < ZXDH_DCBNL_MAX_TRAFFIC_CLASS; i++) + { + switch (tc_type[i]) + { + case ZXDH_DCBNL_ZEROBW_ETS_TC: + tc_tx_bw[i] = zero_ets_bw; + break; + case ZXDH_DCBNL_ETS_TC: + tc_tx_bw[i] = ets->tc_tx_bw[i]; + break; + case ZXDH_DCBNL_STRICT_TC: + case ZXDH_DCBNL_VENDOR_TC: + tc_tx_bw[i] = ZXDH_DCBNL_MAX_BW_ALLOC; + break; + default: + break; + } + } + /* debug */ + LOG_INFO(" zero_ets_num:%d, zero_ets_bw:%d \n", zero_ets_num, zero_ets_bw); + + return 0; +} + +static uint32_t zxdh_dcbnl_ieee_set_ets_para(struct zxdh_en_priv *en_priv, struct ieee_ets *ets) +{ + struct zxdh_en_device *en_dev = &en_priv->edev; + uint8_t tc_type[ZXDH_DCBNL_MAX_TRAFFIC_CLASS]; + uint8_t tc_tx_bw[ZXDH_DCBNL_MAX_TRAFFIC_CLASS]; + uint32_t err = 0; + uint32_t j = 0; + + zxdh_dcbnl_ieee_divide_tc_type(ets, tc_type); + + zxdh_dcbnl_ieee_convert_tc_bw(ets, tc_type, tc_tx_bw); + + err = zxdh_dcbnl_set_tc_scheduling(en_priv, tc_type, tc_tx_bw); + if (err) + { + LOG_ERR("set_tc_scheduling failed \n"); + return err; + } + + err = zxdh_dcbnl_set_ets_up_tc_map(en_priv, ets->prio_tc); + if (err) + { + LOG_ERR("set_prio_tc_map failed \n"); + return err; + } + + memcpy(en_dev->dcb_para.ets_cfg.tc_tsa, ets->tc_tsa, sizeof(ets->tc_tsa)); + memcpy(en_dev->dcb_para.ets_cfg.tc_tx_bw, ets->tc_tx_bw, sizeof(ets->tc_tx_bw)); + memcpy(en_dev->dcb_para.ets_cfg.prio_tc, ets->prio_tc, sizeof(ets->prio_tc)); + /* debug */ + for (j = 0; j < ZXDH_DCBNL_MAX_TRAFFIC_CLASS; j++) + { + LOG_INFO(" idx:%d, tc_tsa:%d, tc_tx_bw:%d, prio_tc:%d \n", j, + en_dev->dcb_para.ets_cfg.tc_tsa[j], en_dev->dcb_para.ets_cfg.tc_tx_bw[j], en_dev->dcb_para.ets_cfg.prio_tc[j]); + + LOG_INFO(" idx:%d, tc_type:%d, tc_tx_bw:%d \n", j, tc_type[j], tc_tx_bw[j]); + } + + return 0; +} + +static int zxdh_dcbnl_ieee_setets(struct net_device *netdev, struct ieee_ets *ets) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + uint32_t err; + uint32_t j = 0; + + /* debug */ + for (j = 0; j < ZXDH_DCBNL_MAX_TRAFFIC_CLASS; j++) + { + LOG_INFO(" idx:%d, ets->tc_tsa:%d, ets->tc_tx_bw:%d, ets->prio_tc:%d \n", j, + ets->tc_tsa[j], ets->tc_tx_bw[j], ets->prio_tc[j]); + } + + if (en_dev->ops->get_coredev_type(en_dev->parent) != DH_COREDEV_PF) + { + LOG_ERR(" coredev type is not a PF"); + return -EOPNOTSUPP; + } + + err = zxdh_dcbnl_check_ets_para(ets); + if (err) + { + return err; + } + + err = zxdh_dcbnl_ieee_set_ets_para(en_priv, ets); + if (err) + { + return err; + } + + return 0; +} + +static int zxdh_dcbnl_ieee_getpfc(struct net_device *netdev, struct ieee_pfc *pfc) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + uint32_t pfc_cur_tm_en = 0; + uint32_t pfc_cur_mac_en = 0; + int32_t ret = 0; + DPP_PF_INFO_T pf_info = {0}; + + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + LOG_INFO("zxdh_dcbnl_ieee_getpfc start\n"); + + /*获取端口pfc使能函数*/ + ret = zxdh_en_fc_mode_get(en_dev, &pfc_cur_mac_en); + LOG_INFO("zxdh_en_fc_mode_get:%d", pfc_cur_mac_en); + + if(0 != ret) + { + LOG_ERR("zxdh_port_pfc_enable_get failed"); + return ret; + } + ret = dpp_qmu_port_pfc_get(&pf_info, en_dev->phy_port, &pfc_cur_tm_en); + LOG_INFO("dpp_qmu_port_pfc_get:%d", pfc_cur_tm_en); + + if(ret != 0) + { + LOG_ERR("dpp_qmu_port_pfc_get failed"); + return ret; + } + if((pfc_cur_tm_en == 1)&&(pfc_cur_mac_en == BIT(SPM_FC_PFC_FULL))) + { + pfc->pfc_en = 255; + } + else if((pfc_cur_tm_en == 0)&&(pfc_cur_mac_en == BIT(SPM_FC_NONE))) + { + pfc->pfc_en = 0; + } + else + { + //ret = -1; + LOG_INFO("pfc_cur_mac_en != pfc_cur_tm_en"); + } + + LOG_INFO("zxdh_dcbnl_ieee_getpfc end\n"); + + return ret; +} + +static int zxdh_dcbnl_ieee_setpfc(struct net_device *netdev, struct ieee_pfc *pfc) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + uint32_t port_mac_en = 0; + uint32_t port_tm_en = 0; + uint32_t ret = 0; + uint32_t test_pfc_mac_en = 0; + DPP_PF_INFO_T pf_info = {0}; + + LOG_INFO("zxdh_dcbnl_ieee_setpfc start\n"); + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + //兼容现有工具考虑，后续开发工具后可以注释掉 + if(pfc->pfc_en != 0 && pfc->pfc_en != 0xff ) + { + LOG_INFO("pfc->pfc_en input invalid: %d", pfc->pfc_en); + return EINVAL; + } + + if(pfc->pfc_en != 0) + { + port_mac_en = BIT(SPM_FC_PFC_FULL); + port_tm_en = 1; + } + else + { + port_mac_en = BIT(SPM_FC_NONE); + //不使能后重新设置为初始状态阈值 + //ret = zxdh_port_th_update_to_default(en_dev); + + if(ret) + { + LOG_INFO("zxdh_port_th_update_to_last failed"); + } + } + /*tm端口pfc使能*/ + //ret |= dpp_qmu_port_pfc_set(&pf_info, en_dev->phy_port, port_tm_en); + //dpp_qmu_port_pfc_get(&pf_info, en_dev->phy_port, &test_pfc_tm_en); + //LOG_INFO("dpp_qmu_port_pfc_get: %d", test_pfc_tm_en); + + /*mac部分端口pfc使能*/ + ret |= zxdh_en_fc_mode_set(en_dev, port_mac_en); + zxdh_en_fc_mode_get(en_dev, &test_pfc_mac_en); + LOG_INFO("zxdh_port_pfc_enable_get: %d", test_pfc_mac_en); + + if(pfc->pfc_en != 0) + { + //ret = zxdh_port_th_update(en_dev); + } + + /*错误判断及打印*/ + if(0 != ret) + { + LOG_ERR("zxdh_dcbnl_ieee_setpfc pfc_en:%c failed, %d", pfc->pfc_en, ret); + } + + LOG_INFO("zxdh_dcbnl_ieee_setpfc end\n"); + + return ret; +} + +static int zxdh_dcbnl_ieee_getmaxrate(struct net_device *netdev, struct ieee_maxrate *maxrate) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + uint32_t i = 0; + uint32_t j = 0; + + if (en_dev->ops->get_coredev_type(en_dev->parent) != DH_COREDEV_PF) + { + LOG_ERR("coredev type is not a PF"); + return -EOPNOTSUPP; + } + + for (i = 0; i < ZXDH_DCBNL_MAX_TRAFFIC_CLASS; i++) + { + if (ZXDH_DCBNL_MAXRATE_KBITPS <= en_dev->dcb_para.tc_maxrate[i]) + { + maxrate->tc_maxrate[i] = 0; //0 indicates unlimited + } + else + { + maxrate->tc_maxrate[i] = en_dev->dcb_para.tc_maxrate[i]; + } + } + + /* debug */ + for (j = 0; j < ZXDH_DCBNL_MAX_TRAFFIC_CLASS; j++) + { + LOG_INFO(" tc:%d,tc_maxrate:%lld \n", j, maxrate->tc_maxrate[j]); + } + + return 0; +} + +static int zxdh_dcbnl_ieee_setmaxrate(struct net_device *netdev, struct ieee_maxrate *maxrate) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + uint32_t maxrate_kbps[ZXDH_DCBNL_MAX_TRAFFIC_CLASS] = {0}; + uint32_t err,i; + uint32_t j = 0; + + if (en_dev->ops->get_coredev_type(en_dev->parent) != DH_COREDEV_PF) + { + LOG_ERR("coredev type is not a PF"); + return -EOPNOTSUPP; + } + + /* Values are 64 bits and specified in Kbps */ + for (i = 0; i < ZXDH_DCBNL_MAX_TRAFFIC_CLASS; i++) + { + if ((maxrate->tc_maxrate[i] == 0) || (maxrate->tc_maxrate[i] >= ZXDH_DCBNL_MAXRATE_KBITPS)) + { + maxrate_kbps[i] = ZXDH_DCBNL_MAXRATE_KBITPS; + } + else if (maxrate->tc_maxrate[i] <= ZXDH_DCBNL_MINRATE_KBITPS) + { + maxrate_kbps[i] = ZXDH_DCBNL_MINRATE_KBITPS; + } + else + { + maxrate_kbps[i] = (uint32_t)maxrate->tc_maxrate[i]; + } + } + /* debug */ + for (j = 0; j < ZXDH_DCBNL_MAX_TRAFFIC_CLASS; j++) + { + LOG_INFO(" tc:%d,maxrate->tc_maxrate:%lld,maxrate_kbps:%d \n", + j, maxrate->tc_maxrate[j], maxrate_kbps[j]); + } + + err = zxdh_dcbnl_set_tc_maxrate(en_priv, maxrate_kbps); + if (err) + { + return err; + } + + return 0; +} + + +static int zxdh_dcbnl_ieee_setapp(struct net_device *netdev, struct dcb_app *app) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + struct dcb_app app_old; + bool is_new = false; + int err = 0; + + if (en_dev->ops->get_coredev_type(en_dev->parent) != DH_COREDEV_PF) + { + LOG_ERR(" coredev type is not a PF"); + return -EOPNOTSUPP; + } + + if ((app->selector != IEEE_8021QAZ_APP_SEL_DSCP) || + (app->protocol >= ZXDH_DCBNL_MAX_DSCP) || + (app->priority >= ZXDH_DCBNL_MAX_PRIORITY)) + { + return -EINVAL; + } + /* Save the old entry info */ + app_old.selector = IEEE_8021QAZ_APP_SEL_DSCP; + app_old.protocol = app->protocol; + app_old.priority = en_dev->dcb_para.dscp2prio[app->protocol]; + + LOG_INFO(" protocol:%d, priority:%d \n", app->protocol, app->priority); + + if (!en_dev->dcb_para.dscp_app_num) + { + err = zxdh_dcbnl_set_ets_trust(en_priv, ZXDH_DCBNL_ETS_TRUST_DSCP); + if (err) + { + return err; + } + } + + if (app->priority != en_dev->dcb_para.dscp2prio[app->protocol]) + { + err = zxdh_dcbnl_set_dscp2prio(en_priv, app->protocol, app->priority); + if (err) + { + zxdh_dcbnl_set_ets_trust(en_priv, ZXDH_DCBNL_ETS_TRUST_PCP); + return err; + } + } + + /* Delete the old entry if exists */ + err = dcb_ieee_delapp(netdev, &app_old); + if (err) + { + is_new = true; + } + /* Add new entry and update counter */ + err = dcb_ieee_setapp(netdev, app); + if (err) + { + return err; + } + if (is_new) + { + en_dev->dcb_para.dscp_app_num++; + } + LOG_INFO(" dscp_app_num:%d \n", en_dev->dcb_para.dscp_app_num); + + return err; +} + +static int zxdh_dcbnl_ieee_delapp(struct net_device *netdev, struct dcb_app *app) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + int err = 0; + + if (en_dev->ops->get_coredev_type(en_dev->parent) != DH_COREDEV_PF) + { + LOG_ERR("zxdh_dcbnl_ieee_delapp coredev type is not a PF"); + return -EOPNOTSUPP; + } + + if ((app->selector != IEEE_8021QAZ_APP_SEL_DSCP) || + (app->protocol >= ZXDH_DCBNL_MAX_DSCP)) + { + return -EINVAL; + } + + if (!en_dev->dcb_para.dscp_app_num) + { + return -ENOENT; + } + + if (app->priority != en_dev->dcb_para.dscp2prio[app->protocol]) + { + return -ENOENT; + } + + /* Delete the app entry */ + err = dcb_ieee_delapp(netdev, app); + if (err) + { + return err; + } + + /* Restore to default */ + err = zxdh_dcbnl_set_dscp2prio(en_priv, app->protocol, app->protocol>>3); + if (err) + { + zxdh_dcbnl_set_ets_trust(en_priv, ZXDH_DCBNL_ETS_TRUST_PCP); + return err; + } + en_dev->dcb_para.dscp_app_num--; + LOG_INFO(" protocol:%d, dscp_app_num:%d \n", app->protocol, en_dev->dcb_para.dscp_app_num); + + if (!en_dev->dcb_para.dscp_app_num) + { + err = zxdh_dcbnl_set_ets_trust(en_priv, ZXDH_DCBNL_ETS_TRUST_PCP); + } + + return err; + +} +#ifdef ZXDH_DCBNL_CEE_SUPPORT +static void zxdh_dcbnl_setpgtccfgtx(struct net_device *netdev, int tc, + uint8_t prio_type, uint8_t pgid, + uint8_t bw_pct, uint8_t up_map) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + struct zxdh_dcbnl_cee_ets *cee_ets_cfg; + uint32_t i; + + if (en_dev->ops->get_coredev_type(en_dev->parent) != DH_COREDEV_PF) + { + LOG_ERR("zxdh_dcbnl_setpgtccfgtx coredev type is not a PF"); + return; + } + + if ((tc < 0) || (tc >= ZXDH_DCBNL_MAX_TRAFFIC_CLASS)) + { + return; + } + + cee_ets_cfg = &en_dev->dcb_para.cee_ets_cfg; + for (i = 0; i < ZXDH_DCBNL_MAX_PRIORITY; i++) + { + if (up_map & BIT(i)) + { + cee_ets_cfg->prio_tc[i] = tc; + } + } + cee_ets_cfg->tc_tsa[tc] = IEEE_8021QAZ_TSA_ETS; + +} +static void zxdh_dcbnl_setpgbwgcfgtx(struct net_device *netdev, int pgid, uint8_t bw_pct) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + + if (en_dev->ops->get_coredev_type(en_dev->parent) != DH_COREDEV_PF) + { + LOG_ERR("zxdh_dcbnl_setpgbwgcfgtx coredev type is not a PF"); + return; + } + + if ((pgid >= 0) && (pgid < ZXDH_DCBNL_MAX_TRAFFIC_CLASS)) + { + en_dev->dcb_para.cee_ets_cfg.tc_tx_bw[pgid] = bw_pct; + } + LOG_INFO(" tc_tx_bw[%d]:%d \n", pgid, bw_pct); + +} + +static void zxdh_dcbnl_getpgtccfgtx(struct net_device *netdev, int prio, + uint8_t *prio_type, uint8_t *pgid, + uint8_t *bw_pct, uint8_t *up_map) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + + /* pf检查 */ + if (en_dev->ops->get_coredev_type(en_dev->parent) != DH_COREDEV_PF) + { + LOG_ERR("zxdh_dcbnl_getpgtccfgtx coredev type is not a PF"); + return; + } + + if ((prio >= 0) && (prio < ZXDH_DCBNL_MAX_PRIORITY)) + { + *pgid = en_dev->dcb_para.ets_cfg.prio_tc[prio]; + } + +} + +static void zxdh_dcbnl_getpgbwgcfgtx(struct net_device *netdev, int pgid, uint8_t *bw_pct) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + + if (en_dev->ops->get_coredev_type(en_dev->parent) != DH_COREDEV_PF) + { + LOG_ERR("zxdh_dcbnl_getpgbwgcfgtx coredev type is not a PF"); + return; + } + + if ((pgid >= 0) && (pgid < ZXDH_DCBNL_MAX_TRAFFIC_CLASS)) + { + *bw_pct = en_dev->dcb_para.ets_cfg.tc_tx_bw[pgid]; + } + +} + + +static void zxdh_dcbnl_setpgtccfgrx(struct net_device *netdev, int prio, + uint8_t prio_type, uint8_t pgid, + uint8_t bw_pct, uint8_t up_map) +{ + LOG_ERR("Rx PG TC Config Not Supported.\n"); +} + +static void zxdh_dcbnl_setpgbwgcfgrx(struct net_device *netdev, int pgid, uint8_t bw_pct) +{ + LOG_ERR("Rx PG BWG Config Not Supported.\n"); +} + + +static void zxdh_dcbnl_getpgtccfgrx(struct net_device *netdev, int prio, + uint8_t *prio_type, uint8_t *pgid, + uint8_t *bw_pct, uint8_t *up_map) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + + if (en_dev->ops->get_coredev_type(en_dev->parent) != DH_COREDEV_PF) + { + LOG_ERR("zxdh_dcbnl_getpgtccfgrx coredev type is not a PF"); + return; + } + + if ((prio >= 0) && (prio < ZXDH_DCBNL_MAX_PRIORITY)) + { + *pgid = en_dev->dcb_para.ets_cfg.prio_tc[prio]; + } + +} + +static void zxdh_dcbnl_getpgbwgcfgrx(struct net_device *netdev, int pgid, uint8_t *bw_pct) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + + if (en_dev->ops->get_coredev_type(en_dev->parent) != DH_COREDEV_PF) + { + LOG_ERR("zxdh_dcbnl_getpgbwgcfgrx coredev type is not a PF"); + return; + } + + if ((pgid >= 0) && (pgid < ZXDH_DCBNL_MAX_TRAFFIC_CLASS)) + { + *bw_pct = 0; + } + +} + +static uint8_t zxdh_dcbnl_setall(struct net_device *netdev) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + struct ieee_ets ets = {0}; + uint32_t i = 0; + uint32_t err = 0; + uint32_t j = 0; + + if (en_dev->ops->get_coredev_type(en_dev->parent) != DH_COREDEV_PF) + { + LOG_ERR("zxdh_dcbnl_setall coredev type is not a PF"); + return 1; + } + + ets.ets_cap = ZXDH_DCBNL_MAX_TRAFFIC_CLASS; + for (i = 0; i < ZXDH_DCBNL_MAX_TRAFFIC_CLASS; i++) + { + ets.tc_tx_bw[i] = en_dev->dcb_para.cee_ets_cfg.tc_tx_bw[i]; + ets.tc_rx_bw[i] = en_dev->dcb_para.cee_ets_cfg.tc_tx_bw[i]; + ets.tc_tsa[i] = en_dev->dcb_para.cee_ets_cfg.tc_tsa[i]; + } + + for (i = 0; i < ZXDH_DCBNL_MAX_PRIORITY; i++) + { + ets.prio_tc[i] = en_dev->dcb_para.cee_ets_cfg.prio_tc[i]; + } + /* debug */ + for (j = 0; j < ZXDH_DCBNL_MAX_TRAFFIC_CLASS; j++) + { + LOG_INFO(" idx:%d, tc_tsa:%d, tc_tx_bw:%d, prio_tc:%d \n", j, ets.tc_tx_bw[j], ets.tc_tsa[j], ets.prio_tc[j]); + } + + err = zxdh_dcbnl_check_ets_para(&ets); + if (err) + { + return err; + } + + err = zxdh_dcbnl_ieee_set_ets_para(en_priv, &ets); + if (err) + { + return err; + } + + return 0; +} + +static uint8_t zxdh_dcbnl_getstate(struct net_device *netdev) +{ + return ZXDH_DCBNL_CEE_STATE_UP; +} + +static uint8_t zxdh_dcbnl_setstate(struct net_device *netdev, u8 state) +{ + + return 0; +} +#endif + +static const struct dcbnl_rtnl_ops zxdh_dcbnl_ops ={ + .ieee_getets = zxdh_dcbnl_ieee_getets, + .ieee_setets = zxdh_dcbnl_ieee_setets, + .ieee_getpfc = zxdh_dcbnl_ieee_getpfc, + .ieee_setpfc = zxdh_dcbnl_ieee_setpfc, + + .ieee_getmaxrate = zxdh_dcbnl_ieee_getmaxrate, + .ieee_setmaxrate = zxdh_dcbnl_ieee_setmaxrate, + + .ieee_setapp = zxdh_dcbnl_ieee_setapp, + .ieee_delapp = zxdh_dcbnl_ieee_delapp, + +#ifdef ZXDH_DCBNL_CEE_SUPPORT + /* CEE not support */ + .setall = zxdh_dcbnl_setall, + + .getstate = zxdh_dcbnl_getstate, + .setstate = zxdh_dcbnl_setstate, + + .setpgtccfgtx = zxdh_dcbnl_setpgtccfgtx, + .setpgbwgcfgtx = zxdh_dcbnl_setpgbwgcfgtx, + .getpgtccfgtx = zxdh_dcbnl_getpgtccfgtx, + .getpgbwgcfgtx = zxdh_dcbnl_getpgbwgcfgtx, + + .setpgtccfgrx = zxdh_dcbnl_setpgtccfgrx, + .setpgbwgcfgrx = zxdh_dcbnl_setpgbwgcfgrx, + .getpgtccfgrx = zxdh_dcbnl_getpgtccfgrx, + .getpgbwgcfgrx = zxdh_dcbnl_getpgbwgcfgrx, +#endif +}; + +uint32_t zxdh_dcbnl_set_tm_pport_mcode_gate_open(struct net_device *netdev) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + uint32_t err = 0; + err = zxdh_dcbnl_set_tm_gate(en_priv, 1); + if (err) + { + LOG_ERR(" set_tm_gate close failed \n"); + } + LOG_INFO(" tm mcode gate open "); + return err; +} + +uint32_t zxdh_dcbnl_set_tm_pport_mcode_gate_close(struct net_device *netdev) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + uint32_t err = 0; + err = zxdh_dcbnl_set_tm_gate(en_priv, 0); + if (err) + { + LOG_ERR(" set_tm_gate close failed \n"); + } + LOG_INFO(" tm mcode gate close "); + return err; +} + +uint32_t zxdh_dcbnl_initialize(struct net_device *netdev) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + uint32_t err = 0; + + LOG_INFO("%s dcbnl init begin\n", netdev->name); + + err = zxdh_dcbnl_init_port_speed(en_priv); + if (err) + { + LOG_INFO("dcbnl_init_ets: init_port_speed failed \n"); + //return err; + } + + err = zxdh_dcbnl_init_ets_scheduling_tree(en_priv); + if (err) + { + LOG_ERR("dcbnl_init_ets: init_ets_scheduling_tree failed \n"); + return err; + } + + zxdh_dcbnl_printk_ets_tree(en_priv); + + zxdh_dcbnl_pfc_init(en_priv); + + en_dev->dcb_para.init_flag = ZXDH_DCBNL_INIT_FLAG; + netdev->dcbnl_ops = &zxdh_dcbnl_ops; + zxdh_dcbnl_set_tm_pport_mcode_gate_open(netdev); + LOG_INFO("%s dcbnl init ok ", netdev->name); + return 0; +} + +uint32_t zxdh_dcbnl_ets_uninit(struct net_device *netdev) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + + if (en_dev->ops->get_coredev_type(en_dev->parent) != DH_COREDEV_PF) + { + return 0; + } + LOG_INFO("%s dcbnl uninit begin\n", netdev->name); + + en_dev->dcb_para.init_flag = 0; + netdev->dcbnl_ops = NULL; + zxdh_dcbnl_set_tm_pport_mcode_gate_close(netdev); + + zxdh_dcbnl_free_flow_resources(en_priv); + + zxdh_dcbnl_free_se_resources(en_priv); + + LOG_INFO("%s dcbnl uninit ok ", netdev->name); + return 0; +} diff --git a/src/net/drivers/net/ethernet/dinghai/en_aux/dcbnl/en_dcbnl.h b/src/net/drivers/net/ethernet/dinghai/en_aux/dcbnl/en_dcbnl.h new file mode 100644 index 0000000..2ade85a --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_aux/dcbnl/en_dcbnl.h @@ -0,0 +1,213 @@ +#ifndef __ZXDH_EN_DCBNL_H__ +#define __ZXDH_EN_DCBNL_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* 启用dcb会大幅度增加初始化时间，暂时先注释 */ +//#define ZXDH_DCBNL_OPEN + +/* CEE not support */ +//#define ZXDH_DCBNL_CEE_SUPPORT + +#define ZXDH_DCBNL_INIT_FLAG (0x5a5a5a5a) +#define ZXDH_DCBNL_NULL_ID (0xffffffff) + +#define ZXDH_DCBNL_MAX_PRIORITY (8) +#define ZXDH_DCBNL_MAX_TRAFFIC_CLASS (8) + +#define ZXDH_DCBNL_MAX_DSCP (64) + +#define ZXDH_DCBNL_MAX_BW_ALLOC (100) +#define ZXDH_DCBNL_MAX_WEIGHT (512) + +#define ZXDH_DCBNL_RATEUNIT_K (1000) +#define ZXDH_DCBNL_RATEUNIT_M (1000000) +#define ZXDH_DCBNL_RATEUNIT_G (1000000000) +#define ZXDH_DCBNL_MAXRATE_KBITPS (400*1000000) +#define ZXDH_DCBNL_MINRATE_KBITPS (64) + +#define ZXDH_DCBNL_INITRATE_KBITPS (400*1000000) + +#define ZXDH_DCBNL_FLOW_RATE_CIR (0) + +#define ZXDH_DCBNL_FLOW_RATE_CBS (2000) +#define ZXDH_DCBNL_FLOW_RATE_EBS (4000) +#define ZXDH_DCBNL_PORT_RATE_CBS (4000) + +#define ZXDH_DCBNL_FLOW_RATE_CBS_REFRESH (0) +#define ZXDH_DCBNL_FLOW_RATE_EBS_REFRESH (0) + +#define ZXDH_DCBNL_FLOW_TDTH (150) + +#define ZXDH_DCBNL_CEE_STATE_UP (1) + +#define ZXDH_DCBNL_MAX_SE_NODE_NUM (12) +#define ZXDH_DCBNL_MAX_TREE_LEVEL (7) +#define ZXDH_DCBNL_ETS_TREE_ROOT_LEVEL (4) +#define ZXDH_DCBNL_ETS_TREE_FLOW_LEVEL (0) + +#define ZXDH_DCBNL_GSCHID_ID_MASK (0xFFFF) +#define ZXDH_DCBNL_GSCHID_ID_SHIFT (0) + +#define ZXDH_DCBNL_GET_GSCHID_MSG(val,mask,shift) ((val >> shift)&mask) + +enum zxdh_dcbnl_ets_trust { + ZXDH_DCBNL_ETS_TRUST_PCP = 0, + ZXDH_DCBNL_ETS_TRUST_DSCP = 1, +}; + +enum zxdh_dcbnl_ets_tc_tsa { + ZXDH_DCBNL_VENDOR_TC = 0, + ZXDH_DCBNL_STRICT_TC = 1, + ZXDH_DCBNL_ETS_TC = 2, + ZXDH_DCBNL_ZEROBW_ETS_TC = 3, +}; + +enum zxdh_dcbnl_ets_node_link_point { + ZXDH_DCBNL_ETS_NODE_NULL = 0, + ZXDH_DCBNL_ETS_NODE_VENDOR_C = 1, + ZXDH_DCBNL_ETS_NODE_STRICT_C = 2, + ZXDH_DCBNL_ETS_NODE_ETS_C = 3, + ZXDH_DCBNL_ETS_NODE_ZEROBW_ETS_C = 4, + ZXDH_DCBNL_ETS_NODE_VENDOR_E = 5, + ZXDH_DCBNL_ETS_NODE_STRICT_E = 6, + ZXDH_DCBNL_ETS_NODE_ETS_E = 7, + ZXDH_DCBNL_ETS_NODE_ZEROBW_ETS_E = 8, +}; + +enum zxdh_dcbnl_se_flow_node_type { + ZXDH_DCBNL_ETS_NODE_FQ = 0, + ZXDH_DCBNL_ETS_NODE_FQ2 = 1, + ZXDH_DCBNL_ETS_NODE_FQ4 = 2, + ZXDH_DCBNL_ETS_NODE_FQ8 = 3, + ZXDH_DCBNL_ETS_NODE_SP = 4, + ZXDH_DCBNL_ETS_NODE_WFQ = 5, + ZXDH_DCBNL_ETS_NODE_WFQ2 = 6, + ZXDH_DCBNL_ETS_NODE_WFQ4 = 7, + ZXDH_DCBNL_ETS_NODE_WFQ8 = 8, + ZXDH_DCBNL_ETS_NODE_FLOW = 9, +}; + +enum zxdh_tm_trpg_speed{ + ZXDH_TRPG_SPEED_50G = 0, + ZXDH_TRPG_SPEED_100G = 1, + ZXDH_TRPG_SPEED_200G = 2, + ZXDH_TRPG_SPEED_RDMA_400G = 3, + ZXDH_TRPG_DEFAULT = 4, + + ZXDH_TRPG_SPEED_NUM, + +}; +struct zxdh_dcbnl_ets_se_node{ + struct zxdh_dcbnl_ets_se_node *se_next; + uint64_t gsch_id; + uint32_t node_idx; + uint32_t node_type; + uint32_t se_id; + uint32_t se_link_id; + uint32_t se_link_weight; + uint32_t se_link_sp; + uint32_t link_point; +}; + +struct zxdh_dcbnl_ets_flow_node{ + struct zxdh_dcbnl_ets_flow_node *flow_next; + uint64_t gsch_id; + uint32_t flow_id; + uint32_t tc_id; + uint32_t tc_type; + uint32_t tc_tx_bw; + uint32_t td_th; + uint32_t c_linkid; + uint32_t c_weight; + uint32_t c_sp; + uint32_t c_rate; + uint32_t mode; + uint32_t e_linkid; + uint32_t e_weight; + uint32_t e_sp; + uint32_t e_rate; +}; + +struct zxdh_dcbnl_ets_node_list_head{ + struct zxdh_dcbnl_ets_se_node *se_next; + struct zxdh_dcbnl_ets_flow_node *flow_next; + uint32_t node_num; +}; + +struct zxdh_dcbnl_ets_se_flow_resource{ + uint32_t numq; + uint32_t level; + uint32_t flags; + uint32_t resource_id; + uint64_t gsch_id; +}; + +struct zxdh_dcbnl_se_tree_config{ + uint32_t level; + uint32_t idx; + uint32_t type; + uint32_t link_level; + uint32_t link_idx; + uint32_t link_weight; + uint32_t link_sp; + uint32_t link_point; +}; + +struct zxdh_dcbnl_tc_flow_config{ + uint32_t link_level; + uint32_t tc_type; + uint32_t tc_tx_bw; + uint32_t c_rate; + uint32_t e_rate; + uint32_t td_th; +}; + +struct zxdh_dcbnl_tc_flow_shape_para{ + uint32_t cir; + uint32_t cbs; + uint32_t db_en; + uint32_t eir; + uint32_t ebs; +}; + +struct zxdh_dcbnl_ieee_ets { + uint8_t willing; + uint8_t ets_cap; + uint8_t cbs; + uint8_t tc_tx_bw[ZXDH_DCBNL_MAX_TRAFFIC_CLASS]; + uint8_t tc_tsa[ZXDH_DCBNL_MAX_TRAFFIC_CLASS]; + uint8_t prio_tc[ZXDH_DCBNL_MAX_PRIORITY]; +}; + +struct zxdh_dcbnl_cee_ets { + uint8_t tc_tx_bw[ZXDH_DCBNL_MAX_TRAFFIC_CLASS]; + uint8_t tc_tsa[ZXDH_DCBNL_MAX_TRAFFIC_CLASS]; + uint8_t prio_tc[ZXDH_DCBNL_MAX_PRIORITY]; +}; + +struct zxdh_dcbnl_para { + uint32_t init_flag; + uint32_t trust; + uint32_t dscp_app_num; + uint8_t dscp2prio[ZXDH_DCBNL_MAX_DSCP]; + uint64_t tc_maxrate[ZXDH_DCBNL_MAX_TRAFFIC_CLASS]; + struct zxdh_dcbnl_ieee_ets ets_cfg; + struct zxdh_dcbnl_cee_ets cee_ets_cfg; + struct zxdh_dcbnl_ets_node_list_head ets_node_list_head[ZXDH_DCBNL_MAX_TREE_LEVEL]; +}; + +uint32_t zxdh_dcbnl_initialize(struct net_device *netdev); +uint32_t zxdh_dcbnl_ets_uninit(struct net_device *netdev); +uint32_t zxdh_dcbnl_set_tm_pport_mcode_gate_open(struct net_device *netdev); +uint32_t zxdh_dcbnl_set_tm_pport_mcode_gate_close(struct net_device *netdev); + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_aux/dcbnl/en_dcbnl_api.c b/src/net/drivers/net/ethernet/dinghai/en_aux/dcbnl/en_dcbnl_api.c new file mode 100644 index 0000000..c65759c --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_aux/dcbnl/en_dcbnl_api.c @@ -0,0 +1,1463 @@ +//#include +#include "../../en_aux.h" +#include "en_dcbnl.h" +#include "en_dcbnl_api.h" +#include "en_np/qos/include/dpp_drv_qos.h" +#include "en_np/table/include/dpp_tbl_tm.h" +#include "en_np/fc/include/dpp_drv_fc.h" +#include "en_np/sdk/include/api/dpp_pbu_api.h" + +uint32_t zxdh_dcbnl_get_se_flow_resources(struct zxdh_en_device *en_dev, + struct zxdh_dcbnl_ets_se_flow_resource *tree_resource) +{ + uint64_t gsch_id = 0; + uint32_t err = 0; + DPP_PF_INFO_T pf_info = {0}; + + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + if (tree_resource->level == ZXDH_DCBNL_ETS_TREE_ROOT_LEVEL) + { + err = dpp_sch_base_node_get(&pf_info, en_dev->phy_port, &gsch_id); + } + else + { + err = dpp_cosq_gsch_id_add(&pf_info, en_dev->phy_port, tree_resource->numq, + tree_resource->level, tree_resource->flags, &gsch_id); + } + + if (err) + { + LOG_ERR("dcbnl_init_ets: get se/flow resources failed, level: %d, type: %d, err:%d \n", + tree_resource->level, tree_resource->flags, err); + return err; + } + tree_resource->gsch_id = gsch_id; + tree_resource->resource_id = ZXDH_DCBNL_GET_GSCHID_MSG(gsch_id, ZXDH_DCBNL_GSCHID_ID_MASK, ZXDH_DCBNL_GSCHID_ID_SHIFT); + /* debug */ + LOG_INFO(" gsch_id:0x%llx,resource_id:0x%x level:%d, flags:%d\n", + gsch_id, tree_resource->resource_id,tree_resource->level, tree_resource->flags); + + return 0; +} + +uint32_t zxdh_dcbnl_find_se_link_id(struct zxdh_en_priv *en_priv, + uint32_t level, + uint32_t link_level, + uint32_t link_idx, + uint32_t link_sp, + uint32_t *link_id) +{ + struct zxdh_en_device *en_dev = &en_priv->edev; + struct zxdh_dcbnl_ets_se_node *se_link_node = NULL; + struct zxdh_dcbnl_ets_node_list_head *ets_node_list_head = &en_dev->dcb_para.ets_node_list_head[link_level]; + + *link_id = ZXDH_DCBNL_NULL_ID; + + if (level < ZXDH_DCBNL_ETS_TREE_ROOT_LEVEL) + { + if (ets_node_list_head->se_next == NULL) + { + LOG_ERR("dcbnl: no nodes in the link_level: %d \n", link_level); + return 1; + } + + se_link_node = ets_node_list_head->se_next; + + while ((NULL != se_link_node) && (se_link_node->node_idx != link_idx)) + { + se_link_node = se_link_node->se_next; + } + + if (se_link_node != NULL) + { + *link_id = se_link_node->se_id + link_sp; + } + else + { + LOG_ERR("dcbnl: find se link_id failed, link_level: %d, link_idx: %d\n", link_level, link_idx); + return 1; + } + } + + return 0; +} + +uint32_t zxdh_dcbnl_save_se_resources(struct zxdh_en_priv *en_priv, struct zxdh_dcbnl_se_tree_config *tree_node_cfg) +{ + struct zxdh_en_device *en_dev = &en_priv->edev; + struct zxdh_dcbnl_ets_se_flow_resource tree_resource = {0}; + struct zxdh_dcbnl_ets_se_node *new_se_node = NULL; + struct zxdh_dcbnl_ets_node_list_head *ets_node_list_head = NULL; + uint32_t level = 0; + uint32_t link_level = 0; + uint32_t link_idx = 0; + uint32_t link_id = 0; + uint32_t err = 0; + DPP_PF_INFO_T pf_info = {0}; + + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + + level = tree_node_cfg->level; + link_level = tree_node_cfg->link_level; + link_idx = tree_node_cfg->link_idx; + + if ((level == 0) || (level > 4) || (link_level > 5) || (level >= link_level)) + { + LOG_ERR("dcbnl_init_ets: configuration level error, level: %d, link_level: %d\n", level, link_level); + return 1; //todo：考虑使用标准的错误定义 + } + + ets_node_list_head = &en_dev->dcb_para.ets_node_list_head[level]; + + tree_resource.numq = 1; + tree_resource.level = level; + tree_resource.flags = tree_node_cfg->type; + err = zxdh_dcbnl_get_se_flow_resources(en_dev, &tree_resource); + if (err) + { + LOG_ERR("dcbnl_init_ets: get se resources failed, level: %d, idx: %d\n", + tree_resource.level, tree_node_cfg->idx); + return err; + } + + err = zxdh_dcbnl_find_se_link_id(en_priv, level, link_level, link_idx, tree_node_cfg->link_sp, &link_id); + if (err) + { + LOG_ERR("dcbnl_init_ets: find se link_id failed, link_level: %d, link_idx: %d\n", link_level, link_idx); + return err; + } + + new_se_node = kmalloc(sizeof(struct zxdh_dcbnl_ets_se_node), GFP_KERNEL); + if (NULL == new_se_node) + { + LOG_ERR("dcbnl_init_ets: kmalloc se node failed\n"); + return 1; + } + + new_se_node->se_next = NULL; + new_se_node->gsch_id = tree_resource.gsch_id; + new_se_node->node_idx = tree_node_cfg->idx; + new_se_node->node_type = tree_node_cfg->type; + new_se_node->se_id = tree_resource.resource_id; + new_se_node->se_link_id = link_id; + new_se_node->se_link_weight = tree_node_cfg->link_weight; + new_se_node->se_link_sp = tree_node_cfg->link_sp; + new_se_node->link_point = tree_node_cfg->link_point; + + if (level < ZXDH_DCBNL_ETS_TREE_ROOT_LEVEL) + { + err = dpp_crdt_se_link_set(&pf_info, new_se_node->se_id, new_se_node->se_link_id, + new_se_node->se_link_weight, new_se_node->se_link_sp); + if (err) + { + LOG_ERR("dcbnl_init_ets: dpp_crdt_se_link_set failed, level: %d, idx: %d, err:%d\n", + level, tree_node_cfg->idx, err); + kfree(new_se_node); + return err; + } + } + + new_se_node->se_next = ets_node_list_head->se_next; + ets_node_list_head->se_next = new_se_node; + + ets_node_list_head->node_num += 1; + + LOG_INFO(" level:%d, node_idx:%d, node_num:%d \n", + level, new_se_node->node_idx, ets_node_list_head->node_num); + return 0; +} + +uint32_t zxdh_dcbnl_build_ets_scheduling_tree(struct zxdh_en_priv *en_priv) +{ + uint32_t i = 0; + uint32_t err = 0; + + struct zxdh_dcbnl_se_tree_config ets_se_config_table[ZXDH_DCBNL_MAX_SE_NODE_NUM + 1] = + { + /*level idx type link_level link_idx link_weight link_sp link_point*/ + {4, 0, ZXDH_DCBNL_ETS_NODE_WFQ, 5, 0, 1, 0, ZXDH_DCBNL_ETS_NODE_NULL}, + {3, 0, ZXDH_DCBNL_ETS_NODE_FQ2, 4, 0, 1, 0, ZXDH_DCBNL_ETS_NODE_NULL}, + {2, 0, ZXDH_DCBNL_ETS_NODE_FQ4, 3, 0, 1, 0, ZXDH_DCBNL_ETS_NODE_NULL}, + {2, 1, ZXDH_DCBNL_ETS_NODE_FQ4, 3, 0, 1, 1, ZXDH_DCBNL_ETS_NODE_NULL}, + {1, 0, ZXDH_DCBNL_ETS_NODE_FQ, 2, 0, 1, 0, ZXDH_DCBNL_ETS_NODE_VENDOR_C}, + {1, 1, ZXDH_DCBNL_ETS_NODE_FQ8, 2, 0, 1, 1, ZXDH_DCBNL_ETS_NODE_STRICT_C}, + {1, 2, ZXDH_DCBNL_ETS_NODE_WFQ, 2, 0, 1, 2, ZXDH_DCBNL_ETS_NODE_ETS_C}, + {1, 3, ZXDH_DCBNL_ETS_NODE_WFQ, 2, 0, 1, 3, ZXDH_DCBNL_ETS_NODE_ZEROBW_ETS_C}, + {1, 4, ZXDH_DCBNL_ETS_NODE_FQ, 2, 1, 1, 0, ZXDH_DCBNL_ETS_NODE_VENDOR_E}, + {1, 5, ZXDH_DCBNL_ETS_NODE_FQ8, 2, 1, 1, 1, ZXDH_DCBNL_ETS_NODE_STRICT_E}, + {1, 6, ZXDH_DCBNL_ETS_NODE_WFQ, 2, 1, 1, 2, ZXDH_DCBNL_ETS_NODE_ETS_E}, + {1, 7, ZXDH_DCBNL_ETS_NODE_WFQ, 2, 1, 1, 3, ZXDH_DCBNL_ETS_NODE_ZEROBW_ETS_E}, + {0xff} + }; + + for (i = 0; i < ZXDH_DCBNL_MAX_SE_NODE_NUM && ets_se_config_table[i].level != 0xff; i++) + { + err = zxdh_dcbnl_save_se_resources(en_priv, &ets_se_config_table[i]); + if (err) + { + LOG_ERR("dcbnl_init_ets: build_tc_scheduling_tree failed, entry: %d\n", i); + return err; + } + } + + return 0; +} + +void zxdh_dcbnl_tc_map_to_link_point(uint32_t tc_type, uint32_t *c_type, uint32_t *e_type) +{ + switch (tc_type) + { + case ZXDH_DCBNL_VENDOR_TC: + *c_type = ZXDH_DCBNL_ETS_NODE_VENDOR_C; + *e_type = ZXDH_DCBNL_ETS_NODE_VENDOR_E; + break; + + case ZXDH_DCBNL_STRICT_TC: + *c_type = ZXDH_DCBNL_ETS_NODE_STRICT_C; + *e_type = ZXDH_DCBNL_ETS_NODE_STRICT_E; + break; + + case ZXDH_DCBNL_ETS_TC: + *c_type = ZXDH_DCBNL_ETS_NODE_ETS_C; + *e_type = ZXDH_DCBNL_ETS_NODE_ETS_E; + break; + + case ZXDH_DCBNL_ZEROBW_ETS_TC: + *c_type = ZXDH_DCBNL_ETS_NODE_ZEROBW_ETS_C; + *e_type = ZXDH_DCBNL_ETS_NODE_ZEROBW_ETS_E; + break; + default: + break; + } +} + +void zxdh_dcbnl_get_tc_weight_sp(uint32_t tc_type, uint32_t tc_tx_bw, uint32_t tc_id, + uint32_t *c_weight, uint32_t *e_weight, + uint32_t *c_sp, uint32_t *e_sp) +{ + if (tc_tx_bw == ZXDH_DCBNL_MAX_BW_ALLOC) + { + *c_weight = 1; + *e_weight = 1; + } + else + { + *c_weight = ZXDH_DCBNL_MAX_WEIGHT * tc_tx_bw / ZXDH_DCBNL_MAX_BW_ALLOC; + *e_weight = ZXDH_DCBNL_MAX_WEIGHT * tc_tx_bw / ZXDH_DCBNL_MAX_BW_ALLOC; + } + + if ((tc_type == ZXDH_DCBNL_STRICT_TC) && (tc_id < ZXDH_DCBNL_MAX_TRAFFIC_CLASS)) + { + *c_sp = ZXDH_DCBNL_MAX_TRAFFIC_CLASS - 1 - tc_id; + *e_sp = ZXDH_DCBNL_MAX_TRAFFIC_CLASS - 1 - tc_id; + } + else + { + *c_sp = 0; + *e_sp = 0; + } +} + +uint32_t zxdh_dcbnl_find_flow_link_se_id(struct zxdh_en_priv *en_priv, + uint32_t tc_type, uint32_t link_level, + uint32_t *c_linkid, uint32_t *e_linkid, + uint32_t c_sp, uint32_t e_sp) +{ + struct zxdh_en_device *en_dev = &en_priv->edev; + struct zxdh_dcbnl_ets_se_node *se_node = en_dev->dcb_para.ets_node_list_head[link_level].se_next; + uint32_t c_type = 0; + uint32_t e_type = 0; + + if (NULL == se_node) + { + LOG_ERR("dcbnl: find_flow_link_se_id no nodes \n"); + return 1; + } + + zxdh_dcbnl_tc_map_to_link_point(tc_type, &c_type, &e_type); + + *c_linkid = ZXDH_DCBNL_NULL_ID; + *e_linkid = ZXDH_DCBNL_NULL_ID; + + while ((NULL != se_node) && ((ZXDH_DCBNL_NULL_ID == *c_linkid) || (ZXDH_DCBNL_NULL_ID == *e_linkid))) + { + if (se_node->link_point == c_type) + { + *c_linkid = se_node->se_id + c_sp; + } + else if (se_node->link_point == e_type) + { + *e_linkid = se_node->se_id + e_sp; + } + + se_node = se_node->se_next; + } + + if ((ZXDH_DCBNL_NULL_ID == *c_linkid) || (ZXDH_DCBNL_NULL_ID == *e_linkid)) + { + LOG_ERR("dcbnl: find_flow_link_se_id failed, c_linkid: 0x%x, e_linkid: 0x%x\n", *c_linkid, *e_linkid); + return 1; + } + return 0; +} + +uint32_t zxdh_dcbnl_get_ieee_tsa(uint32_t tc_type) +{ + uint32_t tsa = 0; + switch (tc_type) + { + case ZXDH_DCBNL_ETS_TC: + case ZXDH_DCBNL_ZEROBW_ETS_TC: + tsa = IEEE_8021QAZ_TSA_ETS; + break; + case ZXDH_DCBNL_STRICT_TC: + tsa = IEEE_8021QAZ_TSA_STRICT; + break; + case ZXDH_DCBNL_VENDOR_TC: + tsa = IEEE_8021QAZ_TSA_VENDOR; + break; + default: + tsa = IEEE_8021QAZ_TSA_STRICT; + LOG_ERR("dcbnl:tsa error, change to strict \n"); + break; + } + return tsa; +} + +uint32_t zxdh_dcbnl_save_flow_resources(struct zxdh_en_priv *en_priv, + struct zxdh_dcbnl_tc_flow_config *tc_flow_config, + struct zxdh_dcbnl_ets_se_flow_resource *tree_resource, + uint32_t tc_id) +{ + struct zxdh_en_device *en_dev = &en_priv->edev; + struct zxdh_dcbnl_ets_flow_node *new_flow_node = NULL; + struct zxdh_dcbnl_ets_node_list_head *ets_node_list_head = NULL; + struct zxdh_dcbnl_tc_flow_shape_para p_para = {0}; + uint32_t c_linkid = 0; + uint32_t e_linkid = 0; + uint32_t c_weight = 0; + uint32_t e_weight = 0; + uint32_t c_sp = 0; + uint32_t e_sp = 0; + uint32_t err = 0; + DPP_PF_INFO_T pf_info = {0}; + + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + + if (tc_flow_config->link_level != 1) + { + LOG_ERR("dcbnl_init_ets: zxdh_dcbnl_save_flow_resources link_level err\n"); + return 1; + } + + ets_node_list_head = &en_dev->dcb_para.ets_node_list_head[ZXDH_DCBNL_ETS_TREE_FLOW_LEVEL]; + + if (tc_id == 0) + { + tree_resource->numq = ZXDH_DCBNL_MAX_TRAFFIC_CLASS; + tree_resource->level = ZXDH_DCBNL_ETS_TREE_FLOW_LEVEL; + tree_resource->flags = ZXDH_DCBNL_ETS_NODE_FLOW; + err = zxdh_dcbnl_get_se_flow_resources(en_dev, tree_resource); + if (err) + { + LOG_ERR("dcbnl_init_ets: get flow resources err\n"); + return err; + } + + err = dpp_tm_flowid_pport_table_set(&pf_info, en_dev->phy_port, tree_resource->resource_id); + if (err) + { + LOG_ERR("dcbnl_init_ets: flowid_pport_table_set failed, port: %d, flowid:%d, err:%d\n", + en_dev->phy_port, tree_resource->resource_id, err); + return err; + } + } + + zxdh_dcbnl_get_tc_weight_sp(tc_flow_config->tc_type, tc_flow_config->tc_tx_bw, tc_id, &c_weight, &e_weight, &c_sp, &e_sp); + + err = zxdh_dcbnl_find_flow_link_se_id(en_priv, tc_flow_config->tc_type, tc_flow_config->link_level, &c_linkid, &e_linkid, c_sp, e_sp); + if (err) + { + LOG_ERR("dcbnl_init_ets init ets: find_flow_link_se_id failed, tc_id: %d, tc_type: %d\n", + tc_id, tc_flow_config->tc_type); + return err; + } + + new_flow_node = kmalloc(sizeof(struct zxdh_dcbnl_ets_flow_node), GFP_KERNEL); + if (new_flow_node == NULL) + { + LOG_ERR("dcbnl_init_ets: kmalloc new flow node failed\n"); + return 1; + } + + new_flow_node->flow_next = NULL; + new_flow_node->gsch_id = tree_resource->gsch_id + tc_id; + new_flow_node->flow_id = tree_resource->resource_id + tc_id; + new_flow_node->tc_id = tc_id; + new_flow_node->tc_type = tc_flow_config->tc_type; + new_flow_node->tc_tx_bw = tc_flow_config->tc_tx_bw; + new_flow_node->td_th = tc_flow_config->td_th; + new_flow_node->c_linkid = c_linkid; + new_flow_node->c_weight = c_weight; + new_flow_node->c_sp = c_sp; + new_flow_node->c_rate = tc_flow_config->c_rate; + new_flow_node->mode = 1; + new_flow_node->e_linkid = e_linkid; + new_flow_node->e_weight = e_weight; + new_flow_node->e_sp = e_sp; + new_flow_node->e_rate = tc_flow_config->e_rate; + + err = dpp_flow_map_port_set(&pf_info, new_flow_node->flow_id, en_dev->phy_port); + if (err) + { + LOG_ERR("dcbnl_init_ets: dpp_flow_map_port_set failed, flow_id: %d, phy_port: %d, err:%d\n", + new_flow_node->flow_id, en_dev->phy_port, err); + kfree(new_flow_node); + return err; + } + + err = dpp_crdt_flow_link_set(&pf_info, new_flow_node->flow_id, c_linkid, c_weight, c_sp, + new_flow_node->mode, e_linkid, e_weight, e_sp); + if (err) + { + LOG_ERR("dcbnl_init_ets: dpp_crdt_flow_link_set failed, flow_id: %d, c_linkid: %d, e_linkid: %d, err:%d\n", + new_flow_node->flow_id, c_linkid, e_linkid, err); + kfree(new_flow_node); + return err; + } + + err = dpp_flow_td_th_set(&pf_info, new_flow_node->flow_id, new_flow_node->td_th); + if (err) + { + LOG_ERR("dcbnl_init_ets: dpp_flow_td_th_set failed,vport:%d flow_id: %d, td_th: %d, err:%d\n", + en_dev->vport, new_flow_node->flow_id, new_flow_node->td_th, err); + //kfree(new_flow_node); //The default is 150 + //return err; + } + + p_para.cir = new_flow_node->c_rate; + p_para.cbs = ZXDH_DCBNL_FLOW_RATE_CBS; + p_para.db_en = 1; + p_para.eir = new_flow_node->e_rate; + p_para.ebs = ZXDH_DCBNL_FLOW_RATE_EBS; + + err = dpp_flow_shape_set(&pf_info, new_flow_node->flow_id, p_para.cir, p_para.cbs, p_para.db_en, p_para.eir, p_para.ebs); + if (err) + { + LOG_ERR("dcbnl_init_ets: dpp_flow_shape_set failed, vport: %d, flow_id: %d, tc_id: %d, e_rate: %d, err:%d\n", + en_dev->vport, new_flow_node->flow_id, new_flow_node->tc_id, new_flow_node->e_rate, err); + } + LOG_INFO("dcbnl_init_ets dpp_flow_shape_set end vport%d,phy_port:%d, flow_id:%d,tc_id:%d, cir:%d, cbs:%d, db_en:%d, eir:%d,ebs:%d,err:%d \n", + en_dev->vport,en_dev->phy_port, new_flow_node->flow_id,new_flow_node->tc_id, p_para.cir, p_para.cbs, p_para.db_en, p_para.eir, p_para.ebs,err); + + new_flow_node->flow_next = ets_node_list_head->flow_next; + ets_node_list_head->flow_next = new_flow_node; + ets_node_list_head->node_num += 1; + + en_dev->dcb_para.ets_cfg.tc_tsa[tc_id] = zxdh_dcbnl_get_ieee_tsa(new_flow_node->tc_type); + en_dev->dcb_para.ets_cfg.tc_tx_bw[tc_id] = tc_flow_config->tc_tx_bw; + en_dev->dcb_para.tc_maxrate[tc_id] = new_flow_node->e_rate; + + LOG_INFO(" level:%d, tc_id:%d, flow_id:%d, node_num:%d \n", + tree_resource->level, new_flow_node->tc_id, new_flow_node->flow_id, ets_node_list_head->node_num); + + return 0; +} + +uint32_t zxdh_dcbnl_scheduling_tree_link_tc(struct zxdh_en_priv *en_priv) +{ + struct zxdh_dcbnl_ets_se_flow_resource tree_resource; + uint32_t i = 0; + uint32_t err = 0; + + struct zxdh_dcbnl_tc_flow_config ets_tc_config_table[ZXDH_DCBNL_MAX_TRAFFIC_CLASS+1] = + { + /*link_level tc_type tc_tx_bw c_rate e_rate td_th */ + {1, ZXDH_DCBNL_STRICT_TC, 100, ZXDH_DCBNL_FLOW_RATE_CIR, ZXDH_DCBNL_INITRATE_KBITPS, ZXDH_DCBNL_FLOW_TDTH}, + {1, ZXDH_DCBNL_STRICT_TC, 100, ZXDH_DCBNL_FLOW_RATE_CIR, ZXDH_DCBNL_INITRATE_KBITPS, ZXDH_DCBNL_FLOW_TDTH}, + {1, ZXDH_DCBNL_STRICT_TC, 100, ZXDH_DCBNL_FLOW_RATE_CIR, ZXDH_DCBNL_INITRATE_KBITPS, ZXDH_DCBNL_FLOW_TDTH}, + {1, ZXDH_DCBNL_STRICT_TC, 100, ZXDH_DCBNL_FLOW_RATE_CIR, ZXDH_DCBNL_INITRATE_KBITPS, ZXDH_DCBNL_FLOW_TDTH}, + {1, ZXDH_DCBNL_STRICT_TC, 100, ZXDH_DCBNL_FLOW_RATE_CIR, ZXDH_DCBNL_INITRATE_KBITPS, ZXDH_DCBNL_FLOW_TDTH}, + {1, ZXDH_DCBNL_STRICT_TC, 100, ZXDH_DCBNL_FLOW_RATE_CIR, ZXDH_DCBNL_INITRATE_KBITPS, ZXDH_DCBNL_FLOW_TDTH}, + {1, ZXDH_DCBNL_STRICT_TC, 100, ZXDH_DCBNL_FLOW_RATE_CIR, ZXDH_DCBNL_INITRATE_KBITPS, ZXDH_DCBNL_FLOW_TDTH}, + {1, ZXDH_DCBNL_STRICT_TC, 100, ZXDH_DCBNL_FLOW_RATE_CIR, ZXDH_DCBNL_INITRATE_KBITPS, ZXDH_DCBNL_FLOW_TDTH}, + {0xff} + }; + + for (i = 0; i < ZXDH_DCBNL_MAX_TRAFFIC_CLASS && ets_tc_config_table[i].link_level != 0xff; i++) + { + + err = zxdh_dcbnl_save_flow_resources(en_priv, &ets_tc_config_table[i], &tree_resource, i); + if (err) + { + LOG_ERR("dcbnl_init_ets: save_flow_resources failed, entry: %d\n", i); + return err; + } + + } + + return 0; +} + +uint32_t zxdh_dcbnl_set_ets_trust(struct zxdh_en_priv *en_priv, uint32_t trust) +{ + + struct zxdh_en_device *en_dev = &en_priv->edev; + uint32_t err = 0; + DPP_PF_INFO_T pf_info = {0}; + + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + + err = dpp_tm_pport_trust_mode_table_set(&pf_info, en_dev->phy_port, trust); + if (err) + { + LOG_ERR("dcbnl_set_ets: set_ets_trust failed, vport: %d, trust: %d, err:%d\n", en_dev->vport, trust, err); + return err; + } + en_dev->dcb_para.trust = trust; + LOG_INFO(" trust:%d \n", trust); + return 0; +} + +uint32_t zxdh_dcbnl_init_trust_and_table(struct zxdh_en_priv *en_priv) +{ + + struct zxdh_en_device *en_dev = &en_priv->edev; + uint32_t i = 0; + uint32_t err = 0; + DPP_PF_INFO_T pf_info = {0}; + + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + + for (i = 0; i < ZXDH_DCBNL_MAX_PRIORITY; i++) + { + err = dpp_tm_pport_up_map_table_set(&pf_info, en_dev->phy_port, i, i); //初始时，配置一一对应 + if (err) + { + LOG_ERR("dcbnl_init_ets: dpp_tm_pport_up_map_table_set failed, vport: %d, phy_port: %d, err:%d\n", + en_dev->vport, en_dev->phy_port, err); + return err; + } + en_dev->dcb_para.ets_cfg.prio_tc[i] = i; + } + LOG_INFO(" vport:%d,phy_port:%d prio2tc ok \n", en_dev->vport, en_dev->phy_port); + + for (i = 0; i < ZXDH_DCBNL_MAX_DSCP; i++) + { + err = dpp_tm_pport_dscp_map_table_set(&pf_info, en_dev->phy_port, i, i>>3); + if (err) + { + LOG_ERR("dcbnl_init_ets: dscp_map_table_set failed, vport: %d, phy_port: %d, err:%d\n", + en_dev->vport, en_dev->phy_port, err); + return err; + } + + en_dev->dcb_para.dscp2prio[i] = i>>3; + } + LOG_INFO("vport:%d,phy_port:%d,dscp2prio ok \n", en_dev->vport, en_dev->phy_port); + + err = zxdh_dcbnl_set_ets_trust(en_priv, ZXDH_DCBNL_ETS_TRUST_PCP); + if (err) + { + LOG_INFO("set_ets_trust failed \n"); + return err; + } + en_dev->dcb_para.trust = ZXDH_DCBNL_ETS_TRUST_PCP; + LOG_INFO(" vport:%d,phy_port:%d,trust:%d \n", en_dev->vport, en_dev->phy_port, en_dev->dcb_para.trust); + return 0; +} + +uint32_t zxdh_dcbnl_init_ets_list(struct zxdh_en_priv *en_priv) +{ + struct zxdh_en_device *en_dev = &en_priv->edev; + uint32_t level = 0; + + for (level = 0; level < ZXDH_DCBNL_MAX_TREE_LEVEL; level++) + { + en_dev->dcb_para.ets_node_list_head[level].se_next = NULL; + en_dev->dcb_para.ets_node_list_head[level].flow_next = NULL; + en_dev->dcb_para.ets_node_list_head[level].node_num = 0; + } + return 0; +} + +/* Normal release se*/ +uint32_t zxdh_dcbnl_free_se_resources(struct zxdh_en_priv *en_priv) +{ + struct zxdh_en_device *en_dev = &en_priv->edev; + struct zxdh_dcbnl_ets_se_node *se_node = NULL; + struct zxdh_dcbnl_ets_node_list_head *ets_node_list_head = NULL; + uint32_t err = 0; + uint32_t level = 0; + DPP_PF_INFO_T pf_info = {0}; + + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + + LOG_INFO(" vport:%d, phy_port:%d \n",en_dev->vport, en_dev->phy_port); + for (level = 1; level <= ZXDH_DCBNL_ETS_TREE_ROOT_LEVEL; level++) + { + ets_node_list_head = &en_dev->dcb_para.ets_node_list_head[level]; + while (NULL != ets_node_list_head->se_next) + { + se_node = ets_node_list_head->se_next; + ets_node_list_head->se_next = se_node->se_next; + if (level < ZXDH_DCBNL_ETS_TREE_ROOT_LEVEL) + { + err = dpp_crdt_del_se_link_set(&pf_info, se_node->se_id, se_node->se_id); + if (err) + { + LOG_ERR("dcbnl_free_ets: dpp_crdt_del_se_link_set failed, se_id: %d, err:%d \n", se_node->se_id, err); + } + LOG_INFO(" dpp_crdt_del_se_link_set"); + + err = dpp_cosq_gsch_id_delete(&pf_info, en_dev->phy_port, se_node->gsch_id); + if (err) + { + LOG_ERR("dcbnl_free_ets: dpp_cosq_gsch_id_delete failed, se_id: %lld, err:%d \n", se_node->gsch_id, err); + } + LOG_INFO("del se id dpp_cosq_gsch_id_delete"); + } + LOG_INFO(" free level:%d se_id:%x \n", level, se_node->se_id); + kfree(se_node); + ets_node_list_head->node_num -= 1; + LOG_INFO("current node_num:%d \n", ets_node_list_head->node_num); + } + } + + return 0; +} +/* Normal release flow*/ +uint32_t zxdh_dcbnl_free_flow_resources(struct zxdh_en_priv *en_priv) +{ + struct zxdh_en_device *en_dev = &en_priv->edev; + struct zxdh_dcbnl_ets_flow_node *flow_node = NULL; + struct zxdh_dcbnl_ets_node_list_head *ets_node_list_head = &en_dev->dcb_para.ets_node_list_head[ZXDH_DCBNL_ETS_TREE_FLOW_LEVEL]; + uint32_t err = 0; + bool have_flow = false; + DPP_PF_INFO_T pf_info = {0}; + struct zxdh_dcbnl_tc_flow_shape_para p_para = {0}; + + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + + LOG_INFO(" vport:%d, phy_port:%d \n",en_dev->vport, en_dev->phy_port); + while (NULL != ets_node_list_head->flow_next) + { + have_flow = true; + flow_node = ets_node_list_head->flow_next; + ets_node_list_head->flow_next = flow_node->flow_next; + + p_para.cir = 0; + p_para.cbs = ZXDH_DCBNL_FLOW_RATE_CBS_REFRESH; + p_para.db_en = 0; + p_para.eir = 0; + p_para.ebs = ZXDH_DCBNL_FLOW_RATE_EBS_REFRESH; + + err = dpp_flow_shape_set(&pf_info, flow_node->flow_id, p_para.cir, p_para.cbs, p_para.db_en, p_para.eir, p_para.ebs); + if (err) + { + LOG_ERR("dcbnl_set_ets: dpp_flow_shape_set failed, vport: %d, flow_id: %d, tc_id: %d, eir: %d, err:%d\n", + en_dev->vport, flow_node->flow_id, flow_node->tc_id, p_para.eir , err); + return err; + } + LOG_INFO("clean maxrate"); + err = dpp_flow_td_th_set(&pf_info, flow_node->flow_id, 0); + if (err) + { + LOG_ERR("dcbnl_free_ets: dpp_flow_td_th_set failed,vport:%d flow_id: %d, td_th: 0, err:%d\n", + en_dev->vport, flow_node->flow_id, err); + } + LOG_INFO(" clean TD "); + + err = dpp_crdt_del_flow_link_set(&pf_info, flow_node->flow_id, flow_node->flow_id); + if (err) + { + LOG_ERR("dcbnl_free_ets: dpp_crdt_del_flow_link_set failed, flow_id: %d, err:%d \n", flow_node->flow_id, err); + } + LOG_INFO(" dpp_crdt_del_flow_link_set"); + + err = dpp_cosq_gsch_id_delete(&pf_info, en_dev->phy_port, flow_node->gsch_id); + if (err) + { + LOG_ERR("dcbnl_free_ets: dpp_cosq_gsch_id_delete failed, gsch_id: %lld ,err:%d\n", flow_node->gsch_id, err); + } + LOG_INFO("del id dpp_cosq_gsch_id_delete"); + + LOG_INFO(" free level:0, flow_id:%d, tc:%d\n", flow_node->flow_id, flow_node->tc_id); + + kfree(flow_node); + ets_node_list_head->node_num -= 1; + LOG_INFO("current node_num:%d \n", ets_node_list_head->node_num); + } + + if (have_flow) + { + err = dpp_tm_flowid_pport_table_del(&pf_info, en_dev->phy_port); + if (err) + { + LOG_ERR("dcbnl_free_ets: dpp_tm_flowid_pport_table_del failed,vport:%d, phy_port: %d \n", + en_dev->vport, en_dev->phy_port); + } + LOG_INFO("del table dpp_tm_flowid_pport_table_del"); + } + + return 0; +} + +/* host no reset，risc reset? */ +uint32_t zxdh_dcbnl_check_and_free_node_memory(struct zxdh_en_priv *en_priv) +{ + struct zxdh_en_device *en_dev = &en_priv->edev; + struct zxdh_dcbnl_ets_flow_node *flow_node = NULL; + struct zxdh_dcbnl_ets_se_node *se_node = NULL; + struct zxdh_dcbnl_ets_node_list_head *ets_node_list_head = NULL; + uint32_t level = 0; + + ets_node_list_head = &en_dev->dcb_para.ets_node_list_head[ZXDH_DCBNL_ETS_TREE_FLOW_LEVEL]; + while (NULL != ets_node_list_head->flow_next) + { + flow_node = ets_node_list_head->flow_next; + ets_node_list_head->flow_next = flow_node->flow_next; + kfree(flow_node); + ets_node_list_head->node_num -= 1; + } + + for (level = 1; level < ZXDH_DCBNL_ETS_TREE_ROOT_LEVEL + 1; level++) + { + ets_node_list_head = &en_dev->dcb_para.ets_node_list_head[level]; + while (NULL != ets_node_list_head->se_next) + { + se_node = ets_node_list_head->se_next; + ets_node_list_head->se_next = se_node->se_next; + kfree(se_node); + ets_node_list_head->node_num -= 1; + } + } + + return 0; +} + +uint32_t zxdh_dcbnl_set_tc_scheduling(struct zxdh_en_priv *en_priv, uint8_t *tc_type, uint8_t *tc_tx_bw) +{ + struct zxdh_en_device *en_dev = &en_priv->edev; + struct zxdh_dcbnl_ets_flow_node *flow_node = en_dev->dcb_para.ets_node_list_head[ZXDH_DCBNL_ETS_TREE_FLOW_LEVEL].flow_next; + uint32_t tc_id = 0; + uint32_t c_linkid = 0; + uint32_t e_linkid = 0; + uint32_t c_weight = 0; + uint32_t e_weight = 0; + uint32_t c_sp = 0; + uint32_t e_sp = 0; + uint32_t i = 0; + uint32_t err = 0; + DPP_PF_INFO_T pf_info = {0}; + struct zxdh_dcbnl_tc_flow_shape_para p_para = {0}; + + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + + if (NULL == flow_node) + { + LOG_ERR("dcbnl_set_ets: set_tc_scheduling no flow in the tree\n"); + return 1; + } + + for (i = 0; i < ZXDH_DCBNL_MAX_TRAFFIC_CLASS && flow_node != NULL; i++) + { + tc_id = flow_node->tc_id; + if ((flow_node->tc_type == tc_type[tc_id]) && (flow_node->tc_tx_bw == tc_tx_bw[tc_id])) + { + LOG_INFO("Same configuration,tc_id:%d, tc_type:%d, tc_tx_bw:%d\n",tc_id, tc_type[tc_id], tc_tx_bw[tc_id]); + flow_node = flow_node->flow_next; + continue; + } + + zxdh_dcbnl_get_tc_weight_sp(tc_type[tc_id], tc_tx_bw[tc_id], tc_id, &c_weight, &e_weight, &c_sp, &e_sp); + + err = zxdh_dcbnl_find_flow_link_se_id(en_priv, tc_type[tc_id], 1, &c_linkid, &e_linkid, c_sp, e_sp); + if (err) + { + LOG_ERR("dcbnl_set_ets: find_flow_link_se_id failed, tc_id: %d, tc_type: %d\n", tc_id, tc_type[tc_id]); + return err; + } + + /* 1、清限速,刷新桶深,断流*/ + p_para.cir = 0; + p_para.cbs = ZXDH_DCBNL_FLOW_RATE_CBS_REFRESH; + p_para.db_en = 0; + p_para.eir = 0; + p_para.ebs = ZXDH_DCBNL_FLOW_RATE_EBS_REFRESH; + + LOG_INFO("clean maxrate vport%d,phy_port:%d, flow_id:%d,tc_id:%d, cir:%d, cbs:%d, db_en:%d, eir:%d,ebs:%d \n", + en_dev->vport,en_dev->phy_port, flow_node->flow_id, tc_id, p_para.cir, p_para.cbs, p_para.db_en, p_para.eir, p_para.ebs); + + err = dpp_flow_shape_set(&pf_info, flow_node->flow_id, p_para.cir, p_para.cbs, p_para.db_en, p_para.eir, p_para.ebs); + if (err) + { + LOG_ERR("dcbnl_set_ets: dpp_flow_shape_set failed, vport: %d, flow_id: %d, tc_id: %d, eir: %d, err:%d\n", + en_dev->vport, flow_node->flow_id, tc_id, p_para.eir , err); + return err; + } + + /* 2、清TD,断流*/ + err = dpp_flow_td_th_set(&pf_info, flow_node->flow_id, 0); + if (err) + { + LOG_ERR("dcbnl_set_ets: dpp_flow_td_th_set failed,vport:%d flow_id: %d, td_th: 0, err:%d\n", + en_dev->vport, flow_node->flow_id, err); + } + + /* 3、删除挂接*/ + err = dpp_crdt_del_flow_link_set(&pf_info, flow_node->flow_id, flow_node->flow_id); + if (err) + { + LOG_ERR("dcbnl_set_ets: dpp_crdt_del_flow_link_set failed, vport: %d, flow_id: %d, err:%d\n", + en_dev->vport, flow_node->flow_id, err); + return err; + } + + /* 4、重新挂接*/ + err = dpp_crdt_flow_link_set(&pf_info, flow_node->flow_id, c_linkid, c_weight, c_sp, 1, + e_linkid, e_weight, e_sp); + if (err) + { + LOG_ERR("dcbnl_set_ets: dpp_crdt_flow_link_set failed, flow_id: %d, flow_id: %d, flow_id: %d, err:%d\n", + flow_node->flow_id, c_linkid, e_linkid, err); + return err; + } + + /* 5、恢复TD*/ + err = dpp_flow_td_th_set(&pf_info, flow_node->flow_id, flow_node->td_th); + if (err) + { + LOG_ERR("dcbnl_set_ets: dpp_flow_td_th_set failed,vport:%d flow_id: %d, td_th:%d, err:%d\n", + en_dev->vport, flow_node->flow_id, flow_node->td_th, err); + } + + /* 6、恢复限速*/ + p_para.cir = ZXDH_DCBNL_FLOW_RATE_CIR; + p_para.cbs = ZXDH_DCBNL_FLOW_RATE_CBS; + p_para.db_en = 1; + p_para.eir = flow_node->e_rate; + p_para.ebs = ZXDH_DCBNL_FLOW_RATE_EBS; + + LOG_INFO("dpp_flow_shape_set begin vport%d,phy_port:%d, flow_id:%d,tc_id:%d, cir:%d, cbs:%d, db_en:%d, eir:%d,ebs:%d \n", + en_dev->vport,en_dev->phy_port, flow_node->flow_id, tc_id, p_para.cir, p_para.cbs, p_para.db_en, p_para.eir, p_para.ebs); + + err = dpp_flow_shape_set(&pf_info, flow_node->flow_id, p_para.cir, p_para.cbs, p_para.db_en, p_para.eir, p_para.ebs); + if (err) + { + LOG_ERR("dcbnl_set_ets: dpp_flow_shape_set failed, vport: %d, flow_id: %d, tc_id: %d, eir: %d, err:%d\n", + en_dev->vport, flow_node->flow_id, tc_id, p_para.eir , err); + return err; + } + LOG_INFO(" dpp_flow_shape_set end"); + flow_node->tc_type = tc_type[tc_id]; + flow_node->tc_tx_bw = tc_tx_bw[tc_id]; + + flow_node->c_linkid = c_linkid; + flow_node->c_weight = c_weight; + flow_node->c_sp = c_sp; + + flow_node->e_linkid = e_linkid; + flow_node->e_weight = e_weight; + flow_node->e_sp = e_sp; + + LOG_INFO(" tc_id:%d, tc_type:%d, c_linkid:%x, e_weight:%d, e_sp:%d ,e_linkid:%x, e_weight:%d, e_sp:%d \n", + tc_id, flow_node->tc_type, flow_node->c_linkid,flow_node->c_weight, flow_node->c_sp, flow_node->e_linkid, flow_node->e_weight, flow_node->e_sp); + + flow_node = flow_node->flow_next; + } + + return 0; +} + +uint32_t zxdh_dcbnl_set_ets_up_tc_map(struct zxdh_en_priv *en_priv, uint8_t *prio_tc) +{ + struct zxdh_en_device *en_dev = &en_priv->edev; + uint32_t i = 0; + uint32_t err = 0; + DPP_PF_INFO_T pf_info = {0}; + + LOG_INFO(" begin \n"); + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + + for (i = 0; i < ZXDH_DCBNL_MAX_PRIORITY; i++) + { + err = dpp_tm_pport_up_map_table_set(&pf_info, en_dev->phy_port, i, prio_tc[i]); + if (err) + { + LOG_ERR("dcbnl_set_ets: failed, vport: %d, prio: %d, tc: %d, err:%d\n", + en_dev->vport, i, prio_tc[i], err); + return err; + } + LOG_INFO(" vport:%d, phy_port:%d, prio:%d, tc:%d \n",en_dev->vport, en_dev->phy_port, i, prio_tc[i]); + } + return 0; +} + +uint32_t zxdh_dcbnl_set_tc_maxrate(struct zxdh_en_priv *en_priv, uint32_t *maxrate) +{ + struct zxdh_en_device *en_dev = &en_priv->edev; + struct zxdh_dcbnl_ets_flow_node *flow_node = en_dev->dcb_para.ets_node_list_head[ZXDH_DCBNL_ETS_TREE_FLOW_LEVEL].flow_next; + struct zxdh_dcbnl_tc_flow_shape_para p_para = {0}; + uint32_t tc_id = 0; + uint32_t i = 0; + uint32_t err = 0; + DPP_PF_INFO_T pf_info = {0}; + + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + + if (NULL == flow_node) + { + LOG_ERR("dcbnl_set_ets: set_tc_maxrate no flow in the tree\n"); + return 1; + } + + for (i = 0; i < ZXDH_DCBNL_MAX_TRAFFIC_CLASS && flow_node != NULL; i++) + { + tc_id = flow_node->tc_id; + if (flow_node->e_rate == maxrate[tc_id]) + { + LOG_INFO("Same configuration, tc_id:%d, maxrate:%d\n", tc_id, maxrate[tc_id]); + flow_node = flow_node->flow_next; + continue; + } + /* clean CBS、EBS*/ + p_para.cir = 0; + p_para.cbs = ZXDH_DCBNL_FLOW_RATE_CBS_REFRESH; + p_para.db_en = 0; + p_para.eir = 0; + p_para.ebs = ZXDH_DCBNL_FLOW_RATE_EBS_REFRESH; + LOG_INFO(" refresh maxrate "); + err = dpp_flow_shape_set(&pf_info, flow_node->flow_id, p_para.cir, p_para.cbs, p_para.db_en, p_para.eir, p_para.ebs); + if (err) + { + LOG_ERR("dcbnl_set_ets: dpp_flow_shape_set failed, vport: %d, flow_id: %d, tc_id: %d, eir: %d, err:%d\n", + en_dev->vport, flow_node->flow_id, tc_id, p_para.eir, err); + return err; + } + /* 2、set maxrate*/ + p_para.cir = ZXDH_DCBNL_FLOW_RATE_CIR; + p_para.cbs = ZXDH_DCBNL_FLOW_RATE_CBS; + p_para.db_en = 1; + p_para.eir = maxrate[tc_id]; + p_para.ebs = ZXDH_DCBNL_FLOW_RATE_EBS; + + LOG_INFO(" vport%d,phy_port:%d, flow_id:%d,tc_id:%d, cir:%d, cbs:%d, db_en:%d, eir:%d,ebs:%d \n", + en_dev->vport,en_dev->phy_port, flow_node->flow_id, tc_id, p_para.cir, p_para.cbs, p_para.db_en, p_para.eir, p_para.ebs); + + err = dpp_flow_shape_set(&pf_info, flow_node->flow_id, p_para.cir, p_para.cbs, p_para.db_en, p_para.eir, p_para.ebs); + if (err) + { + LOG_ERR("dcbnl_set_ets: dpp_flow_shape_set failed, vport: %d, flow_id: %d, tc_id: %d, eir: %d, err:%d\n", + en_dev->vport, flow_node->flow_id, tc_id, p_para.eir, err); + return err; + } + + flow_node->e_rate = maxrate[tc_id]; + en_dev->dcb_para.tc_maxrate[tc_id] = maxrate[tc_id]; + + flow_node = flow_node->flow_next; + + } + + return 0; +} + +uint32_t zxdh_dcbnl_set_dscp2prio(struct zxdh_en_priv *en_priv, uint16_t dscp, uint8_t prio) +{ + struct zxdh_en_device *en_dev = &en_priv->edev; + uint32_t err = 0; + DPP_PF_INFO_T pf_info = {0}; + + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + + err = dpp_tm_pport_dscp_map_table_set(&pf_info, en_dev->phy_port, dscp, prio); + if (err) + { + LOG_ERR("dcbnl_set_ets: set_dscp2prio failed, vport: %d, dscp: %d, prio: %d, err:%d\n", en_dev->vport, dscp, prio, err); + return err; + } + en_dev->dcb_para.dscp2prio[dscp] = prio; + LOG_INFO(" vport:%d, ephy_port:%d,dscp:%d, up:%d \n",en_dev->vport, en_dev->phy_port,dscp, prio); + + return 0; +} + +uint32_t zxdh_dcbnl_set_flow_td_th(struct zxdh_en_priv *en_priv, uint32_t* tc_td_th) +{ + struct zxdh_en_device *en_dev = &en_priv->edev; + struct zxdh_dcbnl_ets_flow_node *flow_node = en_dev->dcb_para.ets_node_list_head[ZXDH_DCBNL_ETS_TREE_FLOW_LEVEL].flow_next; + uint32_t err = 0; + uint32_t i = 0; + uint32_t tc_id = 0; + DPP_PF_INFO_T pf_info = {0}; + + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + + if (flow_node == NULL) + { + LOG_ERR("dcbnl_set_ets: set_flow_td_th no flow in the tree\n"); + return 1; + } + + if (tc_td_th == NULL) + { + LOG_ERR("dcbnl_set_ets: tc_td_th is null \n"); + return 1; + } + + for (i = 0; i < ZXDH_DCBNL_MAX_TRAFFIC_CLASS && flow_node != NULL; i++) + { + tc_id = flow_node->tc_id; + err = dpp_flow_td_th_set(&pf_info, flow_node->flow_id, tc_td_th[tc_id]); + if (err) + { + LOG_ERR("dcbnl_set_ets: set_flow_td_th failed, vport: %d, flow_id:%d, tc_id:%d, td_th: %d, err:%d\n", + en_dev->vport, flow_node->flow_id, tc_id, tc_td_th[tc_id], err); + return err; + } + flow_node->td_th = tc_td_th[tc_id]; + flow_node = flow_node->flow_next; + } + + return 0; +} + +uint32_t zxdh_dcbnl_get_flow_td_th(struct zxdh_en_priv *en_priv, uint32_t* tc_td_th) +{ + struct zxdh_en_device *en_dev = &en_priv->edev; + struct zxdh_dcbnl_ets_flow_node *flow_node = en_dev->dcb_para.ets_node_list_head[ZXDH_DCBNL_ETS_TREE_FLOW_LEVEL].flow_next; + uint32_t err = 0; + uint32_t i = 0; + uint32_t tc_id = 0; + DPP_PF_INFO_T pf_info = {0}; + + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + + if (flow_node == NULL) + { + LOG_ERR("get_flow_td_th no flow in the tree\n"); + return 1; + } + + if (tc_td_th == NULL) + { + LOG_ERR(" tc_td_th is null \n"); + return 1; + } + + for (i = 0; i < ZXDH_DCBNL_MAX_TRAFFIC_CLASS && flow_node != NULL; i++) + { + tc_id = flow_node->tc_id; + err = dpp_flow_td_th_get(&pf_info, flow_node->flow_id, &tc_td_th[tc_id]); + if (err) + { + LOG_ERR("get_flow_td_th failed, vport: %d, flow_id:%d, tc_id:%d, err:%d\n", + en_dev->vport, flow_node->flow_id, tc_id, err); + return err; + } + flow_node = flow_node->flow_next; + } + + return 0; +} + +uint32_t zxdh_dcbnl_init_port_speed(struct zxdh_en_priv *en_priv) +{ + struct zxdh_en_device *en_dev = &en_priv->edev; + struct zxdh_dcbnl_tc_flow_shape_para p_para = {0}; + uint32_t err = 0; + uint32_t speed = 0; + uint32_t max_speed = ZXDH_DCBNL_MAXRATE_KBITPS / ZXDH_DCBNL_RATEUNIT_K; + DPP_PF_INFO_T pf_info = {0}; + + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + + speed = en_dev->speed; + if ((0 == speed) || (speed > max_speed)) + { + LOG_INFO("get port speed is : %u ,set to max:%u\n",speed, max_speed); + speed = max_speed; + } + + p_para.cir = speed * ZXDH_DCBNL_RATEUNIT_K; //Mbps->Kbps + p_para.cbs = ZXDH_DCBNL_PORT_RATE_CBS; + p_para.db_en = 0; + p_para.eir = 0; + p_para.ebs = 0; + + LOG_INFO(" vport:%d,phy_port:%d, p_para.cir:%d, speed:%d \n", + en_dev->vport, en_dev->phy_port, p_para.cir, speed); + + err = dpp_port_shape_set(&pf_info, en_dev->phy_port, p_para.cir, p_para.cbs, 1); + if (err) + { + LOG_ERR("dcbnl_set_ets: dpp_port_shape_set failed, port:%d, speed:%d, speed:%d,err:%d \n", + en_dev->phy_port, speed, p_para.cir, err); + return err; + } + + return 0; +} + +uint32_t zxdh_dcbnl_printk_ets_tree(struct zxdh_en_priv *en_priv) +{ + struct zxdh_en_device *en_dev = &en_priv->edev; + struct zxdh_dcbnl_ets_flow_node *flow_node = NULL; + struct zxdh_dcbnl_ets_se_node *se_node = NULL; + struct zxdh_dcbnl_ets_node_list_head *ets_node_list_head = NULL; + uint32_t level = 0; + + LOG_INFO(" ***vport:%d port:%d \n", en_dev->vport,en_dev->phy_port); + + for (level = ZXDH_DCBNL_ETS_TREE_ROOT_LEVEL; level > 0; level--) + { + ets_node_list_head = &en_dev->dcb_para.ets_node_list_head[level]; + se_node = ets_node_list_head->se_next; + while (NULL != se_node) + { + LOG_INFO(" se_node *** level:%d, node_idx:%d, se_id:0x%x *** \n", + level, se_node->node_idx, se_node->se_id); + LOG_INFO(" se_node gsch_id:0x%llx, node_type:%d, se_id:0x%x \n", + se_node->gsch_id, se_node->node_type, se_node->se_id); + LOG_INFO(" se_node se_link_id:0x%x, se_link_weight:%d, se_link_sp:%d, link_point:%d \n", + se_node->se_link_id, se_node->se_link_weight, se_node->se_link_sp, se_node->link_point); + se_node = se_node->se_next; + } + } + + ets_node_list_head = &en_dev->dcb_para.ets_node_list_head[ZXDH_DCBNL_ETS_TREE_FLOW_LEVEL]; + flow_node = ets_node_list_head->flow_next; + while (NULL != flow_node) + { + LOG_INFO(" flow_node *** tc_id:%d, flow_id:%d *** \n", + flow_node->tc_id, flow_node->flow_id); + LOG_INFO(" flow_node gsch_id:0x%llx, tc_type:%d, td_th:%d \n", + flow_node->gsch_id, flow_node->tc_type, flow_node->td_th); + LOG_INFO(" flow_node c_linkid:0x%x, c_weight:%d, c_sp:%d, c_rate:%d \n", + flow_node->c_linkid, flow_node->c_weight,flow_node->c_sp,flow_node->c_rate); + LOG_INFO(" flow_node e_linkid:0x%x, e_weight:%d, e_sp:%d, e_rate:%d \n", + flow_node->e_linkid, flow_node->e_weight, flow_node->e_sp, flow_node->e_rate); + flow_node = flow_node->flow_next; + } + + return 0; +} + +uint32_t zxdh_link_speed_to_index(uint32_t link_speed) +{ + //50G以下统一按50G处理 + //暂未使用RDMA端口 + uint32_t index = ZXDH_TRPG_DEFAULT; //riscv上默认初值 + if(link_speed == 200000) + { + index = ZXDH_TRPG_SPEED_200G; + } + else if(link_speed == 100000) + { + index = ZXDH_TRPG_SPEED_100G; + } + else + { + index = ZXDH_TRPG_SPEED_50G; + } + + return index; +} + +DPP_PBU_PORT_TH_PARA_T port_th_para_tbl[ZXDH_TRPG_SPEED_NUM] = +{ + /*brief lif阈值 lif私有阈值 idma私有阈值 idma_th0 idma_th1 idma_th2 idma_th3 idma_th4 idma_th5 idma_th6 idma_th7*/ + /*单位512byte,512代表芯片处理包粒度*/ + {100, 140, 140, 110, 130, 150, 170, 190, 210, 230, 250}, //50G + {210, 280, 280, 180, 230, 280, 330, 380, 430, 480, 530}, //100G + {480, 560, 560, 370, 450, 550, 670, 770, 870, 970, 1070}, //200G + {1400, 0, 0, 1500, 1500, 1500, 1500, 1500, 1500, 1500, 1500}, //400G RDMA + {2036, 2000, 2000, 2100, 2100, 2100, 2100, 2100, 2100, 2100, 2100} //riscv上默认初始值 +}; + +DPP_PBU_PORT_COS_TH_PARA_T port_cos_th_para_tbl[ZXDH_TRPG_SPEED_NUM] = +{ + /*单位512byte*/ + {{100, 120, 140, 160, 180, 200, 220, 240}}, //50G + {{160, 210, 260, 310, 360, 410, 460, 510}}, //100G + {{320, 420, 480, 620, 720, 820, 920, 1020}}, //200G + {{1200, 1200, 2000, 2000, 2800, 2800, 2800, 2800}}, //400G RDMA + {{1650, 1700, 1750, 1800, 1850, 1900, 1950, 2000}} //riscv上默认初始值 +}; + +uint32_t flow_td_th_tbl[ZXDH_TRPG_SPEED_NUM][ZXDH_DCBNL_MAX_TRAFFIC_CLASS] = +{ + /*单位KB*/ + {72, 119, 166, 213, 260, 306, 353, 400}, //50G 梯度47 + {144, 207, 269, 332, 394, 457, 519, 582}, //100G 梯度63 + {287, 365, 443, 521, 600, 678, 756, 834}, //200G 梯度78 最小560*512/1000 + {375, 570, 766, 961, 1156, 1352, 1547, 1742}, //400G RDMA 梯度195 + {150, 150, 150, 150, 150, 150, 150, 150} //riscv上默认初始值 +}; + +uint32_t zxdh_config_param_compare_test(uint32_t tbl_index, + DPP_PBU_PORT_TH_PARA_T port_th_para, + DPP_PBU_PORT_COS_TH_PARA_T port_cos_th_para, + uint32_t *flow_td_th_para) +{ + uint32_t index = 0; + uint32_t *port_th_para_p1 = (uint32_t *)&port_th_para; + uint32_t *port_th_para_p2 = (uint32_t *)&port_cos_th_para_tbl[tbl_index]; + for(index = 0; index<11; index++) + { + if(*(port_th_para_p1+index) != *(port_th_para_p2+index)) + { + return false; + } + } + for(index = 0; indexnetdev; + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + //en_dev里面其实是包含link_speed的，填的是具体的速率值 + uint32_t tbl_index; + uint32_t index; + uint32_t pfc_cur_mac_en = 0; + uint32_t ret = 0; + uint32_t speed = 0; + uint32_t max_speed = ZXDH_DCBNL_MAXRATE_KBITPS; + uint32_t params_check = 0; + DPP_PBU_PORT_TH_PARA_T port_th_para_test = {0}; + DPP_PBU_PORT_COS_TH_PARA_T port_cos_th_para_test = {0}; + DPP_TM_SHAPE_PP_PARA_T port_shape_para_test = {0}; + uint32_t flow_td_th_para_test[ZXDH_DCBNL_MAX_TRAFFIC_CLASS] = {0}; + DPP_PF_INFO_T pf_info = {0}; + + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + LOG_INFO("port speed en_dev->speed is abnormal: %d \n",en_dev->speed) + + if(en_dev->speed) + { + speed = en_dev->speed *ZXDH_DCBNL_RATEUNIT_K; + } + + zxdh_en_fc_mode_get(en_dev, &pfc_cur_mac_en); + if(pfc_cur_mac_en == BIT(SPM_FC_NONE)) + { + LOG_INFO("port pfc & fc disable"); + return 0; + } + + //speed过滤 + if ((0 == speed) || (speed > max_speed)) + { + LOG_INFO("port speed is abnormal: %u \n",speed); + speed = max_speed; + } + ret = dpp_port_shape_set(&pf_info, en_dev->phy_port, speed, ZXDH_DCBNL_PORT_RATE_CBS, 1); + + if(en_dev->phy_port > 9) + { + LOG_INFO("en_dev->phy_port not supported"); + return 0; + } + + tbl_index = zxdh_link_speed_to_index(en_dev->link_speed); + + LOG_INFO("link_speed to tbl_index: %d", tbl_index); + + if(pfc_cur_mac_en != BIT(SPM_FC_PAUSE_RX)) + { + ret = dpp_port_th_set(&pf_info, en_dev->phy_port, port_th_para_tbl+tbl_index); + + ret |= dpp_port_cos_th_set(&pf_info, en_dev->phy_port, port_cos_th_para_tbl+tbl_index); + } + + //暂时规避fc下的td阈值改配 + //if(pfc_cur_mac_en != BIT(SPM_FC_PAUSE_TX)) + if(pfc_cur_mac_en == SPM_FC_PFC_FULL) + { + ret |= zxdh_dcbnl_set_flow_td_th(en_priv, flow_td_th_tbl[tbl_index]); + } + + /*维测需要*/ + dpp_port_th_get(&pf_info, en_dev->phy_port, &port_th_para_test); + LOG_INFO("dpp_port_th_get lif_th:%d, lif_prv:%d, idma_prv:%d \n", + port_th_para_test.lif_th, port_th_para_test.lif_prv, port_th_para_test.idma_prv); + LOG_INFO("idma_th0:%d, idma_th1:%d, idma_th2:%d, idma_th3:%d, idma_th4:%d, idma_th5:%d, idma_th6:%d, idma_th7:%d \n", + port_th_para_test.idma_th_cos0, port_th_para_test.idma_th_cos1, port_th_para_test.idma_th_cos2, port_th_para_test.idma_th_cos3, + port_th_para_test.idma_th_cos4, port_th_para_test.idma_th_cos5, port_th_para_test.idma_th_cos6, port_th_para_test.idma_th_cos7); + + dpp_port_cos_th_get(&pf_info, en_dev->phy_port, &port_cos_th_para_test); + for(index = 0; indexcos_th[0], port_cos_th_para_test->cos_th[1], port_cos_th_para_test->cos_th[2], port_cos_th_para_test->cos_th[3],\ + port_cos_th_para_test->cos_th[4], port_cos_th_para_test->cos_th[6], port_cos_th_para_test->cos_th[0], port_cos_th_para_test->cos_th[0], ) + */ + dpp_port_shape_get(&pf_info, en_dev->phy_port, &port_shape_para_test); + LOG_INFO("dpp_port_shape_get cir:%d, cbs:%d, c_en:%d\n",port_shape_para_test.cir, port_shape_para_test.cbs, port_shape_para_test.c_en); + + zxdh_dcbnl_get_flow_td_th(en_priv, flow_td_th_para_test); + for(index = 0; indexnetdev; + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + uint32_t ret = 0; + uint32_t pfc_cur_mac_en = 0; + DPP_PF_INFO_T pf_info = {0}; + + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + + zxdh_en_fc_mode_get(en_dev, &pfc_cur_mac_en); + + if(pfc_cur_mac_en != BIT(SPM_FC_PAUSE_TX)) + { + ret = dpp_port_th_set(&pf_info, en_dev->phy_port, port_th_para_tbl+ZXDH_TRPG_DEFAULT); + + ret |= dpp_port_cos_th_set(&pf_info, en_dev->phy_port, port_cos_th_para_tbl+ZXDH_TRPG_DEFAULT); + } + + if(pfc_cur_mac_en != BIT(SPM_FC_PAUSE_RX)) + { + ret |= zxdh_dcbnl_set_flow_td_th(en_priv, flow_td_th_tbl[ZXDH_TRPG_DEFAULT]); + } + + return ret; +} + +uint32_t zxdh_dcbnl_pfc_init(struct zxdh_en_priv *en_priv) +{ + struct zxdh_en_device *en_dev = &en_priv->edev; + uint32_t ret = 0; + uint32_t test_en = 0; + DPP_PF_INFO_T pf_info = {0}; + + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + + LOG_INFO("zxdh_dcbnl_pfc_init start\n"); + + ret = dpp_qmu_pfc_en_set(&pf_info, 1); + + if(ret) + { + LOG_ERR("dpp_qmu_pfc_en_set failed"); + } + + dpp_qmu_pfc_en_get(&pf_info, &test_en); + LOG_INFO("dpp_qmu_pfc_en_get:%d", test_en); + LOG_INFO("zxdh_dcbnl_pfc_init end\n"); + + return ret; +} + +uint32_t zxdh_dcbnl_init_ets_scheduling_tree(struct zxdh_en_priv *en_priv) +{ + uint32_t err = 0; + + zxdh_dcbnl_init_ets_list(en_priv); + + err = zxdh_dcbnl_build_ets_scheduling_tree(en_priv); + if (err) + { + LOG_ERR("dcbnl_init_ets: build_tc_scheduling_tree failed \n"); + goto init_ets_se_error; + } + + err = zxdh_dcbnl_scheduling_tree_link_tc(en_priv); + if (err) + { + LOG_ERR("dcbnl_init_ets: scheduling_tree_link_tc failed \n"); + goto init_ets_error; + } + + err = zxdh_dcbnl_init_trust_and_table(en_priv); + if (err) + { + LOG_ERR("dcbnl_init_ets: init_trust_and_table failed \n"); + goto init_ets_error; + } + + return 0; + +init_ets_error: + zxdh_dcbnl_free_flow_resources(en_priv); +init_ets_se_error: + zxdh_dcbnl_free_se_resources(en_priv); + LOG_INFO("dcbnl_init_ets failed \n"); + return err; +} + +uint32_t zxdh_dcbnl_set_tm_gate(struct zxdh_en_priv *en_priv, uint32_t mode) +{ + struct zxdh_en_device *en_dev = &en_priv->edev; + uint32_t err = 0; + DPP_PF_INFO_T pf_info = {0}; + + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + + if (mode == 1) + { + err = dpp_tm_pport_mcode_switch_set(&pf_info, en_dev->phy_port, 1); + if (err) + { + LOG_ERR(" set_tm_gate open failed \n"); + } + } + else if (mode == 0) + { + err = dpp_tm_pport_mcode_switch_del(&pf_info, en_dev->phy_port); + if (err) + { + LOG_ERR(" set_tm_gate close failed \n"); + } + } + else + { + LOG_ERR(" error \n"); + } + + return err; +} diff --git a/src/net/drivers/net/ethernet/dinghai/en_aux/dcbnl/en_dcbnl_api.h b/src/net/drivers/net/ethernet/dinghai/en_aux/dcbnl/en_dcbnl_api.h new file mode 100644 index 0000000..485a377 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_aux/dcbnl/en_dcbnl_api.h @@ -0,0 +1,35 @@ +#ifndef __ZXDH_EN_DCBNL_API_H__ +#define __ZXDH_EN_DCBNL_API_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +struct zxdh_en_priv; + +uint32_t zxdh_dcbnl_init_port_speed(struct zxdh_en_priv *en_priv); +uint32_t zxdh_dcbnl_init_ets_scheduling_tree(struct zxdh_en_priv *en_priv); +uint32_t zxdh_dcbnl_printk_ets_tree(struct zxdh_en_priv *en_priv); +uint32_t zxdh_dcbnl_pfc_init(struct zxdh_en_priv *en_priv); + +uint32_t zxdh_dcbnl_free_flow_resources(struct zxdh_en_priv *en_priv); +uint32_t zxdh_dcbnl_free_se_resources(struct zxdh_en_priv *en_priv); + +uint32_t zxdh_dcbnl_set_tc_scheduling(struct zxdh_en_priv *en_priv, uint8_t *tc_type, uint8_t *tc_tx_bw); +uint32_t zxdh_dcbnl_set_ets_up_tc_map(struct zxdh_en_priv *en_priv, uint8_t *prio_tc); +uint32_t zxdh_dcbnl_set_tc_maxrate(struct zxdh_en_priv *en_priv, uint32_t *maxrate); +uint32_t zxdh_dcbnl_set_ets_trust(struct zxdh_en_priv *en_priv, uint32_t trust); +uint32_t zxdh_dcbnl_set_dscp2prio(struct zxdh_en_priv *en_priv, uint16_t dscp, uint8_t prio); + +uint32_t zxdh_port_th_update(struct zxdh_en_device *en_dev); +uint32_t zxdh_port_th_update_to_default(struct zxdh_en_device *en_dev); + +uint32_t zxdh_dcbnl_set_tm_gate(struct zxdh_en_priv *en_priv, uint32_t mode); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/en_aux/drs_sec_dtb.c b/src/net/drivers/net/ethernet/dinghai/en_aux/drs_sec_dtb.c new file mode 100755 index 0000000..150b79f --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_aux/drs_sec_dtb.c @@ -0,0 +1,1060 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include "driver.h" +#include "../en_aux.h" +#include "drs_sec_dtb.h" + + + +UINT32 g_udDownloadSaNum = 1; //sa表的数量 +UINT32 gudTunnelID = 0; +UINT32 gudDtbSaNum = 1; +E_INLINE_TYPE e_gInlineType = 0; //0是inline入境 1是inline出境 +UINT64 guddAntiWindow = 2047; //得配成2047，否则覆盖不到sn为0的情况 + +UINT64 guddSecTestSaDtbPdVirAddr = 0; + +UINT32 gudSecTestSwanSrcIp = 0x0A04B007; +UINT32 gudSecTestSwanDstIp = 0x0AE3656D; + +UINT8 gudIpType = 1; +// 出入境分开下表需要将此字段置0，会影响入境下表 +UINT16 gusOutSaOffset=0; +UINT32 gudOutSaId=0; + + +UINT64 HalBttlSecRegBaseGet(struct zxdh_en_device *en_dev) +{ + PUB_CHECK_NULL_PTR_RET_ERR(en_dev); + return en_dev->ops->get_bar_virt_addr(en_dev->parent, 0) + 0x7000; //0x7000是目前sec模块寄存器基地址的固定偏移,包括PF/VF +} + + +#if 1 +static int zxdh_ipsec_cipher_id_get(u8 ealgo, char* p_alg_name,char* p_aead_name,E_HAL_SEC_IPSEC_CIPHER_ALG *p_zxdh_ealgo_id) +{ + int i = 0; + T_ZXDH_EALGO atZxdhEalgo[] = + { + {"rfc7539esp(chacha20,poly1305)","",e_HAL_IPSEC_CIPHER_CHACHA}, + }; + + if((NULL == p_alg_name)||(NULL == p_aead_name)) + { + return -1; + } + for(i=0;iaalg) + { + p_aalg_alg_name = xs->aalg->alg_name; + } + if(NULL != xs->ealg) + { + p_ealg_alg_name = xs->ealg->alg_name; + } + if(NULL != xs->aead) + { + p_aead_alg_name = xs->aead->alg_name; + } + + /*AH应该提前拦截*/ + /*空加密空认证应该提前拦截*/ + + //DH_LOG_INFO(MODULE_SEC, "xs:0x%llx\n",xs); + //DH_LOG_INFO(MODULE_SEC, "ptDtbOutSa:0x%llx\n",ptDtbOutSa); + /*应该和pcs的思路一样 ,mlx5e_xfrm_validate_state 参数校验里去把sa的赋值做了*/ + + err = zxdh_ipsec_auth_id_get(xs->props.aalgo,p_aalg_alg_name,&zxdh_auth_id); + if (err) { + DH_LOG_INFO(MODULE_SEC, "Cannot offload xfrm state aalgo:%u\n",xs->props.aalgo); + return -EINVAL; + } + err = zxdh_ipsec_cipher_id_get(xs->props.ealgo,p_ealg_alg_name,p_aead_alg_name,&zxdh_ealgo_id); + if (err) { + DH_LOG_INFO(MODULE_SEC, "Cannot offload xfrm state ealgo:%u\n",xs->props.aalgo); + return -EINVAL; + } + + //DH_LOG_INFO(MODULE_SEC, "replay_esn 0x%llx\n",xs->replay_esn); + ptDtbOutSa->ucAuthkeyLen = 0; /*默认值*/ + + /*处理单认证算法*/ + if(zxdh_auth_id == e_HAL_IPSEC_AUTH_NULL) + { + zxdh_encpy_mode = e_SEC_ENCRYP_ESP_ENCRYP_MODE; + } + else + { + ptDtbOutSa->ucAuthkeyLen = (xs->aalg->alg_key_len + 7)/8; + udIcvLen = (xs->aalg->alg_trunc_len + 7)/8; + memcpy((ptDtbOutSa->aucSaAuthKey),xs->aalg->alg_key,ptDtbOutSa->ucAuthkeyLen); + } + + if((zxdh_ealgo_id != e_HAL_IPSEC_CIPHER_NULL)&&(zxdh_auth_id != e_HAL_IPSEC_AUTH_NULL)) + { + zxdh_encpy_mode = e_SEC_ENCRYP_ESP_AUTH_AND_ESP_ENCRYP_MODE; + } + /*这里处理组合算法的4字节的salt*/ + if((zxdh_ealgo_id == e_HAL_IPSEC_CIPHER_AES_GCM)||(zxdh_ealgo_id == e_HAL_IPSEC_CIPHER_CHACHA)||(zxdh_ealgo_id == e_HAL_IPSEC_CIPHER_AES_GMAC)) + { + zxdh_encpy_mode = e_SEC_ENCRYP_ESP_COMBINED_MODE; + + ptDtbOutSa->ucCipherkeyLen = (xs->aead->alg_key_len + 7)/8 - 4; + udIcvLen = (xs->aead->alg_icv_len+ 7)/8; + memcpy(&(ptDtbOutSa->udSalt), xs->aead->alg_key + ptDtbOutSa->ucCipherkeyLen,sizeof(ptDtbOutSa->udSalt)); + memcpy((ptDtbOutSa->aucSaCipherKey),xs->aead->alg_key,ptDtbOutSa->ucCipherkeyLen); + } + /*这里处理组合算法CCM,CCM的salt是3B*/ + else if(zxdh_ealgo_id == e_HAL_IPSEC_CIPHER_AES_CCM) + { + zxdh_encpy_mode = e_SEC_ENCRYP_ESP_COMBINED_MODE; + + ptDtbOutSa->ucCipherkeyLen = (xs->aead->alg_key_len + 7)/8 - 3; + udIcvLen = (xs->aead->alg_icv_len+ 7)/8; + memcpy(&(ptDtbOutSa->udSalt), xs->aead->alg_key + ptDtbOutSa->ucCipherkeyLen,sizeof(ptDtbOutSa->udSalt)); + memcpy((ptDtbOutSa->aucSaCipherKey),xs->aead->alg_key,ptDtbOutSa->ucCipherkeyLen); + } + /*这里处理有salt的单加密算法CTR,salt是4B*/ + else if(zxdh_ealgo_id == e_HAL_IPSEC_CIPHER_AES_CTR) + { + ptDtbOutSa->ucCipherkeyLen = (xs->ealg->alg_key_len + 7)/8 - 4; + memcpy(&(ptDtbOutSa->udSalt), xs->ealg->alg_key + ptDtbOutSa->ucCipherkeyLen,sizeof(ptDtbOutSa->udSalt)); + memcpy((ptDtbOutSa->aucSaCipherKey),xs->ealg->alg_key,ptDtbOutSa->ucCipherkeyLen); + } + /*空加密算法*/ + else if(zxdh_ealgo_id == e_HAL_IPSEC_CIPHER_NULL) + { + zxdh_encpy_mode = e_SEC_ENCRYP_ESP_AUTH_MODE; + ptDtbOutSa->ucCipherkeyLen = 0; + } + /*单加密算法,且没有salt*/ + else + { + ptDtbOutSa->ucCipherkeyLen = (xs->ealg->alg_key_len + 7)/8; + memcpy((ptDtbOutSa->aucSaCipherKey),xs->ealg->alg_key,ptDtbOutSa->ucCipherkeyLen); + } + + + ptDtbOutSa->udSN = xs->replay.oseq; + ptDtbOutSa->uddProcessedByteCnt = xs->curlft.bytes; //PUB_HTON64(uddProcessedByteCnt); //没法设置,用于构造iv, 一般都是用seq构造的iv + + ptDtbOutSa->udSPI = xs->id.spi; + ptDtbOutSa->udSaId = PUB_HTON32(0x80001); //PUB_HTON32(udSaId); /*这个要软件自己管理,需要设计一下*/ + + ptDtbOutSa->ucCiperID = zxdh_ealgo_id; + ptDtbOutSa->ucAuthID = zxdh_auth_id; + + //CmdkBttlSecSaParamConstruct(UINT32 udEntryValid,E_CMDK_SEC_IPSEC_MODE eTunnelMode,UINT32 udSeqCnterOverflow,E_CMDK_LIVETIME_TYPES eLiveTimeType,E_CMDK_SEC_SA_DF_MODE eSaDfMode,E_CMDK_SEC_ENCRYP_MODE eEncryptionMode,UINT32 udIcvLen,UINT16* pusSaParam) + //E_CMDK_SEC_ENCRYP_MODE 这个只能根据算法反推 gcm ccm gmac chacha是combine gaucSecSwanIpv6Data + //udIcvLen + //mode的定义刚好一样E_CMDK_SEC_IPSEC_MODE , XFRM_MODE_TRANSPORT + /*这个地方还要根据算法做个转换 e_SEC_ENCRYP_ESP_COMBINED_MODE 暂时用GCM*/ + CmdkBttlSecSaParamConstruct(1,xs->props.mode,0,e_SEC_SA_LIVETIME_TIME_TYPE,e_SEC_SA_DF_BYPASS_MODE,zxdh_encpy_mode,udIcvLen,&usSaParam); + ptDtbOutSa->usSaParam = PUB_HTON16(usSaParam); + + + + ptDtbOutSa->usFrag_State = PUB_HTON16(0xd2c8); + + ptDtbOutSa->udLifetimeSecMax = PUB_HTON32(0xc4454766); + ptDtbOutSa->uddLifetimByteCntMax = PUB_HTON64(0xffffffffffffffff); + + ptDtbOutSa->ucProtocol = xs->id.proto; //50esp协议 51ah + ptDtbOutSa->ucTOS = 0xbb; + + /*esn相关*/ + ptDtbOutSa->ucEsnFlag = 0; /* 默认是非ESN模式 */ + if(xs->props.flags & XFRM_STATE_ESN) + { + if(NULL == xs->replay_esn) + return 1; + ptDtbOutSa->ucEsnFlag = 0xff; //ucEsnFlag; //0xff表示开启ESN,否则不开启 + ptDtbOutSa->udSN = xs->replay_esn->oseq; + ptDtbOutSa->udESN = xs->replay_esn->oseq_hi; /*不需要考虑replay_esn为null的情况?*/ + } + + /*ipv4*/ + if(AF_INET == xs->props.family) + { + ptDtbOutSa->ucIpType = 1<<6; //bit[7:6] 1:ivp4 2:ipv6 /*换成宏*/ + ptDtbOutSa->udSrcAddress0 = xs->props.saddr.a4; + ptDtbOutSa->udSrcAddress1 = 0x0; + ptDtbOutSa->udSrcAddress2 = 0x0; + ptDtbOutSa->udSrcAddress3 = 0x0; + + ptDtbOutSa->udDstAddress0 = xs->id.daddr.a4; + ptDtbOutSa->udDstAddress1 = 0x0; + ptDtbOutSa->udDstAddress2 = 0x0; + ptDtbOutSa->udDstAddress3 = 0x0; + } + /*ipv4*/ + else if(AF_INET6 == xs->props.family) + { + ptDtbOutSa->ucIpType = 2<<6; //bit[7:6] 1:ivp4 2:ipv6 /*换成宏*/ + ptDtbOutSa->udSrcAddress0 = xs->props.saddr.a6[0]; + ptDtbOutSa->udSrcAddress1 = xs->props.saddr.a6[1]; + ptDtbOutSa->udSrcAddress2 = xs->props.saddr.a6[2]; + ptDtbOutSa->udSrcAddress3 = xs->props.saddr.a6[3]; + + ptDtbOutSa->udDstAddress0 = xs->id.daddr.a6[0]; + ptDtbOutSa->udDstAddress1 = xs->id.daddr.a6[1]; + ptDtbOutSa->udDstAddress2 = xs->id.daddr.a6[2]; + ptDtbOutSa->udDstAddress3 = xs->id.daddr.a6[3]; + } + else + { + return -EINVAL; /*不可能走到这里,前面函数已经校验过了*/ + } + + ptDtbOutSa->udRSV0 = 0x0; + ptDtbOutSa->udRSV1 = 0x0; + ptDtbOutSa->udRSV2 = 0x0; + + DH_LOG_INFO(MODULE_SEC, "ptDtbOutSa->ucAuthkeyLen:0x%x\n",ptDtbOutSa->ucAuthkeyLen); + DH_LOG_INFO(MODULE_SEC, "ptDtbOutSa->ucCipherkeyLen:0x%x\n",ptDtbOutSa->ucCipherkeyLen); + DH_LOG_INFO(MODULE_SEC, "zxdh_encpy_mode:0x%x\n",zxdh_encpy_mode); + DH_LOG_INFO(MODULE_SEC, "ptDtbOutSa->ucCiperID:0x%x\n",ptDtbOutSa->ucCiperID); + DH_LOG_INFO(MODULE_SEC, "ptDtbOutSa->ucAuthID:0x%x\n",ptDtbOutSa->ucAuthID); + + + return 0; +} + +static int zxdh_ipsec_dtb_in_sa_get(struct xfrm_state *xs,T_HAL_SA_DTB_HW_IN* ptDtbInSa) +{ + int err = -EINVAL; + u16 usSaParam = 0; + u32 udIcvLen = 0; + E_HAL_SEC_IPSEC_AUTH_ALG zxdh_auth_id; + E_HAL_SEC_IPSEC_CIPHER_ALG zxdh_ealgo_id; + E_CMDK_SEC_ENCRYP_MODE zxdh_encpy_mode = e_SEC_ENCRYP_MODE_LAST; + char test_alg_name[] = "zxdh_alg_test"; + char* p_aalg_alg_name = test_alg_name; + char* p_ealg_alg_name = test_alg_name; + char* p_aead_alg_name = test_alg_name; + +/*应该和pcs的思路一样 ,mlx5e_xfrm_validate_state 参数校验里去把sa的赋值做了*/ + if(NULL != xs->aalg) + { + p_aalg_alg_name = xs->aalg->alg_name; + } + if(NULL != xs->ealg) + { + p_ealg_alg_name = xs->ealg->alg_name; + } + if(NULL != xs->aead) + { + p_aead_alg_name = xs->aead->alg_name; + } + err = zxdh_ipsec_auth_id_get(xs->props.aalgo,p_aalg_alg_name,&zxdh_auth_id); + if (err) { + DH_LOG_INFO(MODULE_SEC, "Cannot offload xfrm state aalgo:%u\n",xs->props.aalgo); + return -EINVAL; + } + err = zxdh_ipsec_cipher_id_get(xs->props.ealgo,p_ealg_alg_name,p_aead_alg_name,&zxdh_ealgo_id); + if (err) { + DH_LOG_INFO(MODULE_SEC, "Cannot offload xfrm state ealgo:%u\n",xs->props.aalgo); + return -EINVAL; + } + + ptDtbInSa->ucAuthkeyLen = 0; /*默认值*/ + + /*处理单认证算法*/ + if(zxdh_auth_id == e_HAL_IPSEC_AUTH_NULL) + { + zxdh_encpy_mode = e_SEC_ENCRYP_ESP_ENCRYP_MODE; + } + else + { + ptDtbInSa->ucAuthkeyLen = (xs->aalg->alg_key_len + 7)/8; + udIcvLen = (xs->aalg->alg_trunc_len + 7)/8; + memcpy((ptDtbInSa->aucSaAuthKey),xs->aalg->alg_key,ptDtbInSa->ucAuthkeyLen); + } + + if((zxdh_ealgo_id != e_HAL_IPSEC_CIPHER_NULL)&&(zxdh_auth_id != e_HAL_IPSEC_AUTH_NULL)) + { + zxdh_encpy_mode = e_SEC_ENCRYP_ESP_AUTH_AND_ESP_ENCRYP_MODE; + } + /*这里处理组合算法的4字节的salt*/ + if((zxdh_ealgo_id == e_HAL_IPSEC_CIPHER_AES_GCM)||(zxdh_ealgo_id == e_HAL_IPSEC_CIPHER_CHACHA)||(zxdh_ealgo_id == e_HAL_IPSEC_CIPHER_AES_GMAC)) + { + zxdh_encpy_mode = e_SEC_ENCRYP_ESP_COMBINED_MODE; + + ptDtbInSa->ucCipherkeyLen = (xs->aead->alg_key_len + 7)/8 - 4; + udIcvLen = (xs->aead->alg_icv_len+ 7)/8; + memcpy(&(ptDtbInSa->udSalt), xs->aead->alg_key + ptDtbInSa->ucCipherkeyLen,sizeof(ptDtbInSa->udSalt)); + memcpy((ptDtbInSa->aucSaCipherKey),xs->aead->alg_key,ptDtbInSa->ucCipherkeyLen); + } + /*这里处理组合算法CCM,CCM的salt是3B*/ + else if(zxdh_ealgo_id == e_HAL_IPSEC_CIPHER_AES_CCM) + { + zxdh_encpy_mode = e_SEC_ENCRYP_ESP_COMBINED_MODE; + + ptDtbInSa->ucCipherkeyLen = (xs->aead->alg_key_len + 7)/8 - 3; + udIcvLen = (xs->aead->alg_icv_len+ 7)/8; + memcpy(&(ptDtbInSa->udSalt), xs->aead->alg_key + ptDtbInSa->ucCipherkeyLen,sizeof(ptDtbInSa->udSalt)); + memcpy((ptDtbInSa->aucSaCipherKey),xs->aead->alg_key,ptDtbInSa->ucCipherkeyLen); + } + /*这里处理有salt的单加密算法CTR,salt是4B*/ + else if(zxdh_ealgo_id == e_HAL_IPSEC_CIPHER_AES_CTR) + { + ptDtbInSa->ucCipherkeyLen = (xs->ealg->alg_key_len + 7)/8 - 4; + memcpy(&(ptDtbInSa->udSalt), xs->ealg->alg_key + ptDtbInSa->ucCipherkeyLen,sizeof(ptDtbInSa->udSalt)); + memcpy((ptDtbInSa->aucSaCipherKey),xs->ealg->alg_key,ptDtbInSa->ucCipherkeyLen); + } + /*空加密算法*/ + else if(zxdh_ealgo_id == e_HAL_IPSEC_CIPHER_NULL) + { + zxdh_encpy_mode = e_SEC_ENCRYP_ESP_AUTH_MODE; + ptDtbInSa->ucCipherkeyLen = 0; + } + /*单加密算法,且没有salt*/ + else + { + ptDtbInSa->ucCipherkeyLen = (xs->ealg->alg_key_len + 7)/8; + memcpy((ptDtbInSa->aucSaCipherKey),xs->ealg->alg_key,ptDtbInSa->ucCipherkeyLen); + } + + ptDtbInSa->uddProcessedByteCnt = xs->curlft.bytes; //PUB_HTON64(uddProcessedByteCnt); //没法设置,用于构造iv, 一般都是用seq构造的iv + + ptDtbInSa->udSPI = xs->id.spi; + ptDtbInSa->udSaId = PUB_HTON32(0x80000); //PUB_HTON32(udSaId); /*这个要软件自己管理,需要设计一下*/ + + ptDtbInSa->ucCiperID = zxdh_ealgo_id; + ptDtbInSa->ucAuthID = zxdh_auth_id; + + //CmdkBttlSecSaParamConstruct(UINT32 udEntryValid,E_CMDK_SEC_IPSEC_MODE eTunnelMode,UINT32 udSeqCnterOverflow,E_CMDK_LIVETIME_TYPES eLiveTimeType,E_CMDK_SEC_SA_DF_MODE eSaDfMode,E_CMDK_SEC_ENCRYP_MODE eEncryptionMode,UINT32 udIcvLen,UINT16* pusSaParam) + //CmdkBttlSecSaParamConstruct(1,x->props.mode,不确定,e_SEC_SA_LIVETIME_BYTE_TYPE(好像硬件只支持这个),E_CMDK_SEC_SA_DF_MODE(0),) + //E_CMDK_SEC_ENCRYP_MODE 这个只能根据算法反推 gcm ccm gmac chacha是combine gaucSecSwanIpv6Data + //udIcvLen + //mode的定义刚好一样E_CMDK_SEC_IPSEC_MODE , XFRM_MODE_TRANSPORT + CmdkBttlSecSaParamConstruct(1,xs->props.mode,0,e_SEC_SA_LIVETIME_TIME_TYPE,e_SEC_SA_DF_BYPASS_MODE,zxdh_encpy_mode,udIcvLen,&usSaParam); + ptDtbInSa->usSaParam = PUB_HTON16(usSaParam); + + + + ptDtbInSa->usFrag_State = PUB_HTON16(0xd2c8); + + ptDtbInSa->udLifetimeSecMax = PUB_HTON32(0xc4454766); + ptDtbInSa->uddLifetimByteCntMax = PUB_HTON64(0xffffffffffffffff); + + ptDtbInSa->ucProtocol = xs->id.proto; //50esp协议 51ah + ptDtbInSa->ucTOS = 0xbb; + + /*esn相关*/ + ptDtbInSa->ucEsnFlag = 0; /* 默认是非ESN模式 */ + if(xs->props.flags & XFRM_STATE_ESN) + { + if(NULL == xs->replay_esn) + return 1; + ptDtbInSa->ucEsnFlag = 0xff; //ucEsnFlag; //0xff表示开启ESN,否则不开启 + ptDtbInSa->udAntiWindowHigh = PUB_HTON32(xs->replay_esn->seq_hi); /*ESN*/ + ptDtbInSa->udAntiWindowLow = PUB_HTON32(xs->replay_esn->replay_window - 1); /*窗口上限sn,这里使用窗口大小-1*/ + memcpy((void*)ptDtbInSa->aucBitmap,(void*)xs->replay_esn->bmp,xs->replay_esn->bmp_len * sizeof(__u32)); /*需要提前判断bmp_len不能太大,避免超过64(拦截窗口大小就行)*/ + } + + /*ipv4*/ + if(AF_INET == xs->props.family) + { + ptDtbInSa->ucIpType = 1<<6; //bit[7:6] 1:ivp4 2:ipv6 /*换成宏*/ + ptDtbInSa->udSrcAddress0 = xs->props.saddr.a4; + ptDtbInSa->udSrcAddress1 = 0x0; + ptDtbInSa->udSrcAddress2 = 0x0; + ptDtbInSa->udSrcAddress3 = 0x0; + + ptDtbInSa->udDstAddress0 = xs->id.daddr.a4; + ptDtbInSa->udDstAddress1 = 0x0; + ptDtbInSa->udDstAddress2 = 0x0; + ptDtbInSa->udDstAddress3 = 0x0; + } + /*ipv4*/ + else if(AF_INET6 == xs->props.family) + { + ptDtbInSa->ucIpType = 2<<6; //bit[7:6] 1:ivp4 2:ipv6 /*换成宏*/ + ptDtbInSa->udSrcAddress0 = xs->props.saddr.a6[0]; + ptDtbInSa->udSrcAddress1 = xs->props.saddr.a6[1]; + ptDtbInSa->udSrcAddress2 = xs->props.saddr.a6[2]; + ptDtbInSa->udSrcAddress3 = xs->props.saddr.a6[3]; + + ptDtbInSa->udDstAddress0 = xs->id.daddr.a6[0]; + ptDtbInSa->udDstAddress1 = xs->id.daddr.a6[1]; + ptDtbInSa->udDstAddress2 = xs->id.daddr.a6[2]; + ptDtbInSa->udDstAddress3 = xs->id.daddr.a6[3]; + } + else + { + return -EINVAL; /*不可能走到这里,前面函数已经校验过了*/ + } + + ptDtbInSa->udOutSaId = 0x0; /*内核不需要出入境sa一起下吧,固定为0*/ + ptDtbInSa->usOutSaOffset = 0x0; + + ptDtbInSa->udRSV0 = 0x0; + ptDtbInSa->udRSV1 = 0x0; + + DH_LOG_INFO(MODULE_SEC, "ptDtbInSa->ucAuthkeyLen:0x%x\n",ptDtbInSa->ucAuthkeyLen); + DH_LOG_INFO(MODULE_SEC, "ptDtbInSa->ucCipherkeyLen:0x%x\n",ptDtbInSa->ucCipherkeyLen); + DH_LOG_INFO(MODULE_SEC, "zxdh_encpy_mode:0x%x\n",zxdh_encpy_mode); + DH_LOG_INFO(MODULE_SEC, "ptDtbInSa->ucCiperID:0x%x\n",ptDtbInSa->ucCiperID); + DH_LOG_INFO(MODULE_SEC, "ptDtbInSa->ucAuthID:0x%x\n",ptDtbInSa->ucAuthID); + + + return 0; +} +#endif + + +VOID RdlSecWrite(UINT64 uddSecBase, UINT32 udRegOff, UINT32 udRegVal) +{ + PUB_WRITE_REG32(uddSecBase + udRegOff, udRegVal); +} + +UINT32 HalSecWrite(struct zxdh_en_device *en_dev, UINT32 udSecEngineId, UINT32 udRegOff, UINT32 udRegVal) +{ + UINT64 uddBttlSecBase = 0; + UINT32 udSecnBaseOff = 0; + UINT64 uddSecnBase = 0; + + PUB_CHECK_NULL_PTR_RET_ERR(en_dev); + + uddBttlSecBase = HalBttlSecRegBaseGet(en_dev); + //udSecnBaseOff = udSecEngineId * REG_SEC_IDX_OFFSET; //host不允许操作第二套 + uddSecnBase = uddBttlSecBase + udSecnBaseOff; + //DH_LOG_INFO(MODULE_SEC, "HalBttlSecRegBaseGet regBase vir:0x%llx\n",uddSecnBase); + //DH_LOG_INFO(MODULE_SEC, "HalBttlSecRegBaseGet regBase pa:0x%llx\n",virt_to_phys((void*)uddSecnBase)); + RdlSecWrite(uddSecnBase, udRegOff, udRegVal); + + return 0; +} + +UINT32 RdlSecRead(UINT64 uddSecBase, UINT32 udRegOff) +{ + return PUB_READ_REG32(uddSecBase + udRegOff); +} + +UINT32 HalSecRead(struct zxdh_en_device *en_dev, UINT32 udSecEngineId, UINT32 udRegOff) +{ + UINT64 uddBttlSecBase = 0; + UINT32 udSecnBaseOff = 0; + UINT64 uddSecnBase = 0; + + PUB_CHECK_NULL_PTR_RET_ERR(en_dev); + uddBttlSecBase = HalBttlSecRegBaseGet(en_dev); + udSecnBaseOff = udSecEngineId * REG_SEC_IDX_OFFSET; + uddSecnBase = uddBttlSecBase + udSecnBaseOff; + + return RdlSecRead(uddSecnBase, udRegOff); +} + + +UINT64 HalBttlVaToVpa(struct zxdh_en_device *en_dev, UINT64 pVaAddr) +{ + PUB_CHECK_NULL_PTR_RET_ERR(en_dev); + return (UINT64)virt_to_phys((void*)pVaAddr); +} + +UINT64 HalBttlVpaToVa(struct zxdh_en_device *en_dev, UINT64 pVpaAddr) +{ + PUB_CHECK_NULL_PTR_RET_ERR(en_dev); + return (UINT64)phys_to_virt(pVpaAddr); +} + +#if 0 +VOID PubDumpBuf(UINT8 *pucBuf, UINT32 udLen) +{ + UINT32 i = 0; + UINT32 j = 0; + UINT8 *pucPtr =NULL; + + pucPtr = pucBuf; + for( j=0; j<48; j++ ) + { + PUB_PRINTF("-"); + } + PUB_PRINTF("\n"); + + for( i=0; iops->get_vport(en_dev->parent); + + //写sa的队列锁状态寄存器CFG_DTB_QUEUE_LOCK_STATE，共128个队列,理论上应该查询 + //udRet = HalSecWrite(en_dev, udSecEngineId, REG_SEC_DTB_QUEUE_LOCK_STATE_0_3(0), PUB_BIT_SET(udLockMask,udQueIndex)); + + + //暂时沟通是，只需要将epid配置为0，下表模块就会去riscv侧下表，暂时可以不配 + udEpid = EPID(usVport) + 5; + udVfuncNum = VFUNC_NUM(usVport); + udFuncNum = FUNC_NUM(usVport); + udVfuncActive = VF_ACTIVE(usVport); + + DH_LOG_INFO(MODULE_SEC, "udEpid:0x%x,udVfuncNum:0x%x\n",udEpid,udVfuncNum); + DH_LOG_INFO(MODULE_SEC, "udFuncNum:0x%x,udVfuncActive:0x%x\n",udFuncNum,udVfuncActive); + + PUB_BIT_FIELD_SET64(udEpldVfunNum,udVfuncActive,0,1); + PUB_BIT_FIELD_SET64(udEpldVfunNum,udFuncNum,5,3); + PUB_BIT_FIELD_SET64(udEpldVfunNum,udCfgMsixVector,8,7); + PUB_BIT_FIELD_SET64(udEpldVfunNum,udVfuncNum,16,8); + PUB_BIT_FIELD_SET64(udEpldVfunNum,udEpid,24,4); + PUB_BIT_FIELD_SET64(udEpldVfunNum,udPcieDbiEn,31,1); + + //return 0; + DH_LOG_INFO(MODULE_SEC, "udEpldVfunNum = 0x%x\n",udEpldVfunNum); + HalSecWrite(en_dev, udSecEngineId, REG_SEC_CFG_EPID_V_FUNC_NUM_0_127(udQueIndex), udEpldVfunNum); + + //查询所申请队列剩余空间,如果队列剩余空间大于0则可入队； + udRegVal = HalSecRead(en_dev, udSecEngineId, REG_SEC_INFO_QUEUE_BUF_SPACE_LEFT_0_127(udQueIndex)); + if(udRegVal < 2) + { + BTTL_PRINTF("queue:%u buf empty left:%u\n",udQueIndex,udRegVal); + return 1; + } + if(udRegVal > 0x20) + { + BTTL_PRINTF("queue:%u buf left:%u\n",udQueIndex,udRegVal); + return 1; + } + + //先写DTB_ADDR[63:32],接着写DTB_ADDR[31:0],最后写usdtb_len(软件需严格遵守该顺序） + udRet = HalSecWrite(en_dev, udSecEngineId, REG_SEC_CFG_QUEUE_DTB_ADDR_H_0_127(udQueIndex), pt->DtbAddrH); + + //DH_LOG_INFO(MODULE_SEC, "pt->DtbAddrH = 0x%x\n",pt->DtbAddrH); + udRet = HalSecWrite(en_dev, udSecEngineId, REG_SEC_CFG_QUEUE_DTB_ADDR_L_0_127(udQueIndex), pt->DtbAddrL); + + //DH_LOG_INFO(MODULE_SEC, "pt->DtbAddrL = 0x%x\n",pt->DtbAddrL); + //DH_LOG_INFO(MODULE_SEC, "pt->DtbAddrVir = 0x%llx\n",HalBttlVpaToVa(en_dev,(UINT64)((UINT64)pt->DtbAddrH)<<32)+pt->DtbAddrL); + // CMD寄存器最后配 + udRet = HalSecWrite(en_dev, udSecEngineId, REG_SEC_CFG_QUEUE_DTB_LEN_0_127(udQueIndex), pt->DtbCmd); + + //DH_LOG_INFO(MODULE_SEC, "pt->DtbCmd = 0x%x\n",pt->DtbCmd); + return 0; +} + +/* + sa下表模块测试 + SA存放地址,第二套L2D uddSaL2DPhyAddr= 0x6201000000;理论上为68位，目前场景为64位 + usdtb_len =30; +*/ +//E_SA_TYPE geSaType; + +UINT32 gudTestCnt = 0; +UINT32 CmdkBttlTestSecDtbSaAdd(struct zxdh_en_device *en_dev,E_CMDK_DTB_SA_CMD_TYPE eDtbSaCmdType,E_SA_TYPE eSaType,UINT64 uddSaVirAddr,UINT32 udDtbSaIsIntEn,UINT32 udDtbLen,UINT32 udQueIndex) +{ + /* int_en指示是否产生需要中断 第29位,cmd_type=0指示为流表下发命令，cmd_type=1指示为流表dump命令 第30位 一对sa表的大小为480字节，以16字节为单位*/ + T_QUEUE_DTB_REG tDtbReg = {0}; + UINT32 udDtbCmd = 0; + UINT64 uddSaPhaAddr = 0; + UINT32 udIsDtbAckFinish = 0; + UINT32 udDtbAckRsl = 0; + UINT32 udRet = 0; + int i = 0; + + + /*入参检查*/ + //BTTL_PUB_ID_CHECK(en_dev, CMDK_BTTL_PUB_CHIP_MAX); + //BTTL_PUB_ID_CHECK(eDtbSaCmdType, E_DTB_SA_CMD_LAST); + PUB_CHECK_NULL_PTR_RET_ERR(en_dev); + + uddSaPhaAddr = (UINT64)HalBttlVaToVpa(en_dev, uddSaVirAddr); + //BTTL_PUB_0_CHECK(uddSaPhaAddr); + DH_LOG_INFO(MODULE_SEC, "uddSaVirAddr:0x%llx,uddSaPhaAddr:0x%llx\n",uddSaVirAddr,uddSaPhaAddr); + + //构造udDtbCmd + PUB_BIT_FIELD_SET64(udDtbCmd,udDtbLen>>4,0,10); + PUB_BIT_FIELD_SET64(udDtbCmd,eSaType,27,2); + PUB_BIT_FIELD_SET64(udDtbCmd,udDtbSaIsIntEn,29,1); + PUB_BIT_FIELD_SET64(udDtbCmd,eDtbSaCmdType,30,1); + + tDtbReg.DtbAddrH = (UINT32)PUB_BIT_FIELD_RIGHT_JUST_GET64(uddSaPhaAddr,32,32); + tDtbReg.DtbAddrL = (UINT32)PUB_BIT_FIELD_RIGHT_JUST_GET64(uddSaPhaAddr,0,32); + tDtbReg.DtbCmd = udDtbCmd; + + /* 配置下表寄存器 */ + for(i=0;ixso; + struct net_device *netdev = xso->dev; + struct zxdh_en_priv *en_priv = NULL; + //struct zxdh_en_device *en_dev = NULL; + struct zxdh_en_device *en_dev = NULL; + dma_addr_t dma_handle; + UINT32 dma_size = 0x1000; //暂定4K,批量下表情况下需要更多 + + UINT64 uddDtbSaVirAddr = 0; + UINT32 udSaTblLen = 0; + int ret = 0; + + en_priv = netdev_priv(netdev); + en_dev = &(en_priv->edev); + + if(unlikely(en_dev->drs_sec_pri.SecVAddr == 0)) + { + en_dev->drs_sec_pri.SecVAddr = (uint64_t)dma_alloc_coherent(netdev->dev.parent,dma_size,&dma_handle,GFP_KERNEL); + if(en_dev->drs_sec_pri.SecVAddr == 0) + { + DH_LOG_INFO(MODULE_SEC, "zxdh_ipsec_add_sa dma_alloc_coherent fail\n"); + return -1; + } + en_dev->drs_sec_pri.SecPAddr = dma_handle; + en_dev->drs_sec_pri.SecMemSize = dma_size; + } + uddDtbSaVirAddr = en_dev->drs_sec_pri.SecVAddr; + + DH_LOG_INFO(MODULE_SEC, "uddDtbSaVirAddr:0x%llx\n",uddDtbSaVirAddr); + //DH_LOG_INFO(MODULE_SEC, "xs:0x%llx\n",xs); + + memset((void*)uddDtbSaVirAddr,0,1024); + + //else if(1 == xs->xso.dir) + if(xso->flags & XFRM_OFFLOAD_INBOUND) + { + ret = zxdh_ipsec_dtb_in_sa_get(xs,(T_HAL_SA_DTB_HW_IN*)(uddDtbSaVirAddr+16)); + if(ret != 0) + { + return 1; + } + BttlPubDump((unsigned char *)uddDtbSaVirAddr, 0x210); //传入时加了16字节的回写空间 + + #if 1 + udSaTblLen = 512 - 16; + CmdkBttlTestSecDtbSaAdd(en_dev,E_DTB_SA_CMD_FLOW_DOWN,E_SATYPE_IN,uddDtbSaVirAddr,0,udSaTblLen,2); + + #endif + } + //if(2 == xs->xso.dir) + else + { + ret = zxdh_ipsec_dtb_out_sa_get(xs,(T_HAL_SA_DTB_HW_OUT*)(uddDtbSaVirAddr+16)); + if(ret != 0) + { + return 1; + } + BttlPubDump((unsigned char *)uddDtbSaVirAddr, 0x110); //传入时加了16字节的回写空间 + + #if 1 + udSaTblLen = 256 - 16; + CmdkBttlTestSecDtbSaAdd(en_dev,E_DTB_SA_CMD_FLOW_DOWN,E_SATYPE_OUT,uddDtbSaVirAddr,0,udSaTblLen,2); + #endif + } + + return 0; +} + +void zxdh_ipsec_del_sa(struct xfrm_state *xs) +{ + DH_LOG_INFO(MODULE_SEC, "zxdh_ipsec_del_sa\n"); + return; +} + +bool zxdh_ipsec_offload_ok(struct sk_buff *skb, struct xfrm_state *xs) +{ + DH_LOG_INFO(MODULE_SEC, "zxdh_ipsec_offload_ok\n"); + return true; +} + +void zxdh_ipsec_state_advance_esn (struct xfrm_state *x) +{ + DH_LOG_INFO(MODULE_SEC, "zxdh_ipsec_state_advance_esn\n"); + return; +} +void zxdh_ipsec_state_update_curlft (struct xfrm_state *x) +{ + DH_LOG_INFO(MODULE_SEC, "zxdh_ipsec_state_update_curlft\n"); + return ; +} +int zxdh_ipsec_policy_add (struct xfrm_policy *x) +{ +#if 1 + int32_t ret = 0; + UINT8 aucSip[4] = {0xc8,0xfe,0x00,0x1}; + UINT8 aucDip[4] = {0xc8,0xfe,0x00,0x2}; + UINT8 aucSipMask[4] = {0xff,0xff,0x00,0x0}; + UINT8 aucDipMask[4] = {0xff,0xff,0x00,0x0}; + /*6.2的内核才有*/ + //struct xfrm_dev_offload *xdo = &x->xdo; + //struct net_device *netdev = xdo->dev; + struct net_device *netdev = NULL; //低版本内核仅编译通过 + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + DPP_PF_INFO_T pf_info = {0}; + + DH_LOG_INFO(MODULE_SEC, "zxdh_ipsec_policy_add\n"); + + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + + /*np下表 inline sec模式 打开*/ + ret = dpp_egr_port_attr_set(&pf_info,EGR_FLAG_INLINE_SEC_OFFLOAD,1); + if (ret != 0) + { + LOG_ERR("Failed to set port_attr EGR_FLAG_INLINE_SEC_OFFLOAD !\n"); + } + + /*配置np ipset加密表*/ + ret = dpp_ipsec_enc_entry_add(&pf_info,0,aucSip,aucDip,aucSipMask,aucDipMask,1,0x80001); + if (ret != 0) + { + LOG_ERR("xfrm policy dpp_ipsec_enc_entry_add Failed!\n"); + } +#endif + + return 0; +} +void zxdh_ipsec_policy_delete (struct xfrm_policy *x) +{ + DH_LOG_INFO(MODULE_SEC, "zxdh_ipsec_policy_delete\n"); + return; +} +void zxdh_ipsec_policy_free (struct xfrm_policy *x) +{ + DH_LOG_INFO(MODULE_SEC, "zxdh_ipsec_policy_free\n"); + return; +} + +const struct xfrmdev_ops zxdh_xfrmdev_ops = +{ + .xdo_dev_state_add = zxdh_ipsec_add_sa, + .xdo_dev_state_delete = zxdh_ipsec_del_sa, + .xdo_dev_offload_ok = zxdh_ipsec_offload_ok, + //.xdo_dev_state_advance_esn = zxdh_ipsec_state_advance_esn, + //.xdo_dev_state_update_curlft = zxdh_ipsec_state_update_curlft, + //.xdo_dev_policy_add = zxdh_ipsec_policy_add, + //.xdo_dev_policy_free = zxdh_ipsec_policy_free, +}; +#endif + diff --git a/src/net/drivers/net/ethernet/dinghai/en_aux/drs_sec_dtb.h b/src/net/drivers/net/ethernet/dinghai/en_aux/drs_sec_dtb.h new file mode 100755 index 0000000..ed07b7f --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_aux/drs_sec_dtb.h @@ -0,0 +1,537 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : drs_sec.dtb.h +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : +* 完成日期 : 2024/01/29 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ +#ifndef DRS_SEC_DTB_H +#define DRS_SEC_DTB_H +/*同步pub宏定义*/ +typedef void VOID; +typedef float FLOAT; +typedef double DOUBLE; + +typedef signed char INT8; +typedef unsigned char UINT8; + +typedef char CHAR; + + +typedef signed short INT16; +typedef unsigned short UINT16; + +typedef signed int INT32; +typedef unsigned int UINT32; + + +typedef signed long long INT64; +typedef unsigned long long UINT64; + +#define BITWIDTH1 ((UINT32)0x00000001) +#define BITWIDTH2 ((UINT32)0x00000003) +#define BITWIDTH3 ((UINT32)0x00000007) +#define BITWIDTH4 ((UINT32)0x0000000f) +#define BITWIDTH5 ((UINT32)0x0000001f) +#define BITWIDTH6 ((UINT32)0x0000003f) +#define BITWIDTH7 ((UINT32)0x0000007f) +#define BITWIDTH8 ((UINT32)0x000000ff) +#define BITWIDTH9 ((UINT32)0x000001ff) +#define BITWIDTH10 ((UINT32)0x000003ff) +#define BITWIDTH11 ((UINT32)0x000007ff) +#define BITWIDTH12 ((UINT32)0x00000fff) +#define BITWIDTH13 ((UINT32)0x00001fff) +#define BITWIDTH14 ((UINT32)0x00003fff) +#define BITWIDTH15 ((UINT32)0x00007fff) +#define BITWIDTH16 ((UINT32)0x0000ffff) +#define BITWIDTH17 ((UINT32)0x0001ffff) +#define BITWIDTH18 ((UINT32)0x0003ffff) +#define BITWIDTH19 ((UINT32)0x0007ffff) +#define BITWIDTH20 ((UINT32)0x000fffff) +#define BITWIDTH21 ((UINT32)0x001fffff) +#define BITWIDTH22 ((UINT32)0x003fffff) +#define BITWIDTH23 ((UINT32)0x007fffff) +#define BITWIDTH24 ((UINT32)0x00ffffff) +#define BITWIDTH25 ((UINT32)0x01ffffff) +#define BITWIDTH26 ((UINT32)0x03ffffff) +#define BITWIDTH27 ((UINT32)0x07ffffff) +#define BITWIDTH28 ((UINT32)0x0fffffff) +#define BITWIDTH29 ((UINT32)0x1fffffff) +#define BITWIDTH30 ((UINT32)0x3fffffff) +#define BITWIDTH31 ((UINT32)0x7fffffff) +#define BITWIDTH32 ((UINT32)0xffffffff) + + + +#define PUB_OK (0) +#define PUB_ERROR (0xffffffff)/*直接定义为0xffffffff*/ + +#define BTTL_PRINTF(fmt, arg...) DH_LOG_INFO(MODULE_SEC, fmt, ##arg) +#define BTTL_PUB_PRINT_ERROR(fmt, arg...) DH_LOG_ERR(MODULE_SEC, fmt, ##arg) + + +/* 寄存器单bit位操作 */ + +/** 某bit置位，其它bit不变 */ +#define PUB_BIT_SET(reg, bit) ((reg) = ((reg) | (1u << (bit)))) + +/** 某bit清零，其它bit不变 */ +#define PUB_BIT_CLEAR(reg, bit) ((reg) = ((reg) & (~(1u << (bit))))) + +/** 获取某bit的值 (0/1) */ +#define PUB_GET_BIT_VAL(reg, bit) (((reg)>> (bit)) & 1u) + +/** 判断某bit的值是否为1 */ +#define PUB_IS_BIT_SET(reg, pos) (((reg) & (1u << (pos))) != 0x0u) + +/** 判断某bit的值是否为0 */ +#define PUB_IS_BIT_CLEAR(reg, pos) (((reg) & (1u << (pos))) == 0x0u) + +/** 某bit位填写值val,其他bit不变 */ +#define PUB_BIT_INSR(reg, bit, val) \ + ((reg) = (((reg) & (~(1u << (bit)))) | (((val) & 1u) << (bit)))) + + +#define PUB_BIT_FIELD_MASK_GET64(bitoff, bitfieldlen) \ +((((UINT64)0x01 << (bitfieldlen)) - 1) << (bitoff)) + +#define PUB_BIT_FIELD_GET64(val, bitoff, bitfieldlen) \ +((val) & PUB_BIT_FIELD_MASK_GET64(bitoff, bitfieldlen)) + +#define PUB_BIT_FIELD_SET64(var, val, bitoff, bitlen) \ +((var) = (((var) & (~ PUB_BIT_FIELD_MASK_GET64(bitoff, bitlen))) | (((UINT64)val) << (bitoff)))) + +#define PUB_BIT_FIELD_RIGHT_JUST_GET64(val, bitoff, bitfieldlen) \ +(((val) >> (bitoff)) & (((UINT64)0x01 << (bitfieldlen)) - 1)) + +/** 检查空指针，返回错误 */ +#define PUB_CHECK_NULL_PTR_RET_ERR(ptr) \ + do{\ + if(NULL == ptr){\ + DH_LOG_INFO(MODULE_SEC, "Null Ptr Err! Fuc:%s,Line:%d,File:%s\n", __FUNCTION__,__LINE__,__FILE__);\ + return PUB_ERROR;\ + }\ + }while(0) + +/** 检查空指针，返回VOID */ +#define PUB_CHECK_NULL_PTR_RET_VOID(ptr) \ + do{\ + if(NULL == ptr){\ + DH_LOG_INFO(MODULE_SEC, "Null Ptr Err! Fuc:%s,Line:%d,File:%s\n", __FUNCTION__,__LINE__,__FILE__);\ + return;\ + }\ + }while(0) + +#define PUB_CHECK_RET_VAL_RV(expr) \ + do { \ + UINT32 _ret = (expr); \ + if (PUB_OK != _ret) \ + { \ + DH_LOG_INFO(MODULE_SEC, "%s Error,Line:%d,Ret:0x%x\n", __FUNCTION__,__LINE__,_ret); \ + return _ret; \ + } \ + } while (0) + +#define BTTL_PUB_ID_CHECK(id, cmpid) \ + do{\ + if(cmpid <= (id)){\ + DH_LOG_INFO(MODULE_SEC, " ID %d <= %d check Err! Fuc:%s,Line:%d,File:%s\n", id, cmpid, __FUNCTION__,__LINE__,__FILE__);\ + return 1;\ + }\ + }while(0) + +#define BTTL_PUB_0_CHECK(value) \ + do{\ + if(0 == (value)){\ + DH_LOG_INFO(MODULE_SEC, " value %x 0 check Err! Fuc:%s,Line:%d,File:%s\n", value, __FUNCTION__,__LINE__,__FILE__);\ + return E_INVALID_VALUE;\ + }\ + }while(0) + +/* 大小端操作 */ +/** 16位数据大小端转换 */ +#define PUB_SWAP16(x) ((UINT16)((((x) >> 8) & 0xffu) | (((x) & 0xffu) << 8))) +/** 32位数据大小端转换 */ +#define PUB_SWAP32(x) \ + ((UINT32)( \ + (((UINT32)(x) & (UINT32)0x000000ffUL) << 24) | \ + (((UINT32)(x) & (UINT32)0x0000ff00UL) << 8) | \ + (((UINT32)(x) & (UINT32)0x00ff0000UL) >> 8) | \ + (((UINT32)(x) & (UINT32)0xff000000UL) >> 24) )) +/** 64位数据大小端转换 */ +#define PUB_SWAP64(x) \ + ((UINT64)( \ + (((UINT64)(x) & (UINT64)0x00000000000000ffUL) << 56) | \ + (((UINT64)(x) & (UINT64)0x000000000000ff00UL) << 40) | \ + (((UINT64)(x) & (UINT64)0x0000000000ff0000UL) << 24) | \ + (((UINT64)(x) & (UINT64)0x00000000ff000000UL) << 8 ) | \ + (((UINT64)(x) & (UINT64)0x000000ff00000000UL) >> 8 ) | \ + (((UINT64)(x) & (UINT64)0x0000ff0000000000UL) >> 24) | \ + (((UINT64)(x) & (UINT64)0x00ff000000000000UL) >> 40) | \ + (((UINT64)(x) & (UINT64)0xff00000000000000UL) >> 56) )) + + +/* 已知数据的大小端，转换为网络序 */ +#define PUB_LE_TO_NET16(x) PUB_SWAP16(x) /**< 将小端数据转换为网络序 */ +#define PUB_LE_TO_NET32(x) PUB_SWAP32(x) /**< 将小端数据转换为网络序 */ +#define PUB_LE_TO_NET64(x) PUB_SWAP64(x) /**< 将小端数据转换为网络序 */ +#define PUB_DE_TO_NET16(x) (x) /**< 将大端数据转换为网络序 */ +#define PUB_DE_TO_NET32(x) (x) /**< 将大端数据转换为网络序 */ +#define PUB_DE_TO_NET64(x) (x) /**< 将大端数据转换为网络序 */ + + +#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ + +#define PUB_LE_TO_HOST16(x) PUB_SWAP16(x) /**< 小端16位数据转换为主机序 */ +#define PUB_LE_TO_HOST32(x) PUB_SWAP32(x) /**< 小端32位数据转换为主机序 */ +#define PUB_LE_TO_HOST64(x) PUB_SWAP64(x) /**< 小端64位数据转换为主机序 */ +#define PUB_DE_TO_HOST16(x) (x) /**< 大端16位数据转换为主机序 */ +#define PUB_DE_TO_HOST32(x) (x) /**< 大端32位数据转换为主机序 */ +#define PUB_DE_TO_HOST64(x) (x) /**< 大端64位数据转换为主机序 */ +#define PUB_HTON16(x) (x) /**< 16位数据主机序转换为网络序 */ +#define PUB_HTON32(x) (x) /**< 32位数据主机序转换为网络序 */ +#define PUB_HTON64(x) (x) /**< 64位数据主机序转换为网络序 */ +#define PUB_NTOH16(x) (x) /**< 16位数据网络序转换为主机序 */ +#define PUB_NTOH32(x) (x) /**< 32位数据网络序转换为主机序 */ +#define PUB_NTOH64(x) (x) /**< 64位数据网络序转换为主机序 */ + + +#else +#define PUB_LE_TO_HOST16(x) (x) +#define PUB_LE_TO_HOST32(x) (x) +#define PUB_LE_TO_HOST64(x) (x) +#define PUB_DE_TO_HOST16(x) PUB_SWAP16(x) +#define PUB_DE_TO_HOST32(x) PUB_SWAP32(x) +#define PUB_DE_TO_HOST64(x) PUB_SWAP64(x) +#define PUB_HTON16(x) PUB_SWAP16(x) +#define PUB_HTON32(x) PUB_SWAP32(x) +#define PUB_HTON64(x) PUB_SWAP64(x) +#define PUB_NTOH16(x) PUB_SWAP16(x) +#define PUB_NTOH32(x) PUB_SWAP32(x) +#define PUB_NTOH64(x) PUB_SWAP64(x) + + +#endif + +/*因为SEC下表和NP下表硬件基本一样,这里同步NP关于EPID等定义*/ +#define VF_ACTIVE(VPORT) ((VPORT & 0x0800) >> 11) +#define EPID(VPORT) ((VPORT & 0x7000) >> 12) +#define FUNC_NUM(VPORT) ((VPORT & 0x0700) >> 8) +#define VFUNC_NUM(VPORT) ((VPORT & 0x00FF)) + +#define PF_VQM_VFID_OFFSET (1152) +#define IS_PF(VPORT) (!VF_ACTIVE(VPORT)) +#define VQM_VFID(VPORT) (IS_PF(VPORT) ? \ + (PF_VQM_VFID_OFFSET + EPID(VPORT) * 8 + FUNC_NUM(VPORT)) : \ + (EPID(VPORT) * 256 + VFUNC_NUM(VPORT))) + +#define OWNER_PF_VQM_VFID(VPORT) (PF_VQM_VFID_OFFSET + EPID(VPORT) * 8 + FUNC_NUM(VPORT)) +#define OWNER_PF_VPORT(VPORT) (((EPID(VPORT)) << 12) | ((FUNC_NUM(VPORT)) << 8)) + +#define VQM_VFID_MAX_NUM (2048) + +/*vport格式 +15 |14 13 12 | 11 |10 9 8|7 6 5 4 3 2 1 0| +rsv| ep_id |func_active|func_num| vfunc_num | +*/ +#define VPORT_EPID_BT_START (12) /*EPID起始位*/ +#define VPORT_EPID_BT_LEN (3) /*EPID长度*/ +#define VPORT_FUNC_ACTIVE_BT_START (11) /*FUNC_ACTIVE起始位*/ +#define VPORT_FUNC_ACTIVE_BT_LEN (1) /*FUNC_ACTIVE长度*/ +#define VPORT_FUNC_NUM_BT_START (8) /*FUNC_NUM起始位*/ +#define VPORT_FUNC_NUM_BT_LEN (3) /*FUNC_NUM长度*/ +#define VPORT_VFUNC_NUM_BT_START (0) /*FUNC_NUM起始位*/ +#define VPORT_VFUNC_NUM_BT_LEN (8) /*FUNC_NUM长度*/ + +/** +* @name 通用寄存器操作宏 +* @brief 读寄存器宏定义 +* @{ +*/ +#define PUB_READ_REG8(addr) (*(volatile UINT8 *)(addr)) /**< 读8位寄存器 */ +#define PUB_READ_REG16(addr) (*(volatile UINT16 *)(addr)) /**< 读16位寄存器 */ +#define PUB_READ_REG32(addr) (*(volatile UINT32 *)(addr)) /**< 读32位寄存器 */ +/** @} 通用寄存器操作宏 */ + +/** +* @name 通用寄存器操作宏 +* @brief 写寄存器宏定义 +* @{ +*/ +#define PUB_WRITE_REG8(addr, val_8) (*(volatile UINT8 *)(addr) = val_8) /**< 写8位寄存器 */ +#define PUB_WRITE_REG16(addr, val_16) (*(volatile UINT16 *)(addr) = val_16) /**< 写16位寄存器 */ +#define PUB_WRITE_REG32(addr, val_32) (*(volatile UINT32 *)(addr) = val_32) /**< 写32位寄存器 */ +/** @} 通用寄存器操作宏 */ + + +/*寄存器偏移定义*/ +#define REG_SEC_IDX_OFFSET (0x800000) /* SEC内部基地址偏移 */ + +#define REG_SEC_TOP_DTB_OFFSET (0) /*host驱动 这里为0,因为就是从dtb开始映射的*/ +/* CFG_QUEUE_DTB_ADDR_H_0_127 虚机队列入队的高地址寄存器 n=0~127 */ +#define REG_SEC_CFG_QUEUE_DTB_ADDR_H_0_127(n) (REG_SEC_TOP_DTB_OFFSET + 0x0000 + n*32) + +/* CFG_QUEUE_DTB_ADDR_L_0_127 虚机队列入队的低地址寄存器 n=0~127*/ +#define REG_SEC_CFG_QUEUE_DTB_ADDR_L_0_127(n) (REG_SEC_TOP_DTB_OFFSET + 0x0004 + n*32) + +/* CFG_QUEUE_DTB_LEN_0_127 虚机队列入队的长度寄存器 n=0~127*/ +#define REG_SEC_CFG_QUEUE_DTB_LEN_0_127(n) (REG_SEC_TOP_DTB_OFFSET + 0x0008 + n*32) + +/* INFO_QUEUE_BUF_SPACE_LEFT_0_127 靠靠靠靠靠靠?n=0~127*/ +#define REG_SEC_INFO_QUEUE_BUF_SPACE_LEFT_0_127(n) (REG_SEC_TOP_DTB_OFFSET + 0x000C + n*32) + +/* CFG_EPID_V_FUNC_NUM_0_127 SOC虚机信息配置寄存器 n=0~127*/ +#define REG_SEC_CFG_EPID_V_FUNC_NUM_0_127(n) (REG_SEC_TOP_DTB_OFFSET + 0x0010 + n*32) + +/* DTB_QUEUE_LOCK_STATE_0_3 队列锁状态寄存器,4个寄存器共128bit，对应队列0~127 n=0~3 */ +#define REG_SEC_DTB_QUEUE_LOCK_STATE_0_3(n) (REG_SEC_TOP_DTB_OFFSET + 0x4080 + n*4) + +typedef enum +{ + e_SEC_IPSEC_TRANSPORT_MODE = 0, /*传输模式*/ + e_SEC_IPSEC_TUNNEL_MODE, /*隧道模式*/ + e_SEC_IPSEC_MODE_LAST, +} E_CMDK_SEC_IPSEC_MODE; + +typedef enum +{ + e_SEC_SA_DF_BYPASS_MODE = 0, /*00 bypass DF bit*/ + e_SEC_SA_DF_CLEAR_MODE, /*01 clear*/ + e_SEC_SA_DF_SET_MODE, /*10 set*/ + e_SEC_SA_DF_COPY_MODE, /*11 copy*/ + e_SEC_SA_DF_MODE_LAST, +} E_CMDK_SEC_SA_DF_MODE; + +typedef enum +{ + E_DTB_SA_CMD_FLOW_DOWN = 0, + E_DTB_SA_CMD_DUMP, + E_DTB_SA_CMD_LAST, +} E_CMDK_DTB_SA_CMD_TYPE; + +typedef enum +{ + E_SATYPE_IN = 1, + E_SATYPE_OUT , + E_SATYPE_IN_AND_OUT = 3, +}E_SA_TYPE; + +typedef enum +{ + E_INLINE_IN, + E_INLINE_OUT, + E_INLINE_IN_AND_OUT, +}E_INLINE_TYPE; + +typedef enum +{ + e_SEC_ENCRYP_AH_MODE = 0, /*000 AH认证*/ + e_SEC_ENCRYP_ESP_AUTH_MODE, /*001 ESP完整性*/ + e_SEC_ENCRYP_ESP_ENCRYP_MODE, /*010 ESP加密*/ + e_SEC_ENCRYP_ESP_AUTH_AND_ESP_ENCRYP_MODE, /*011 ESP加密+ESP完整*/ + e_SEC_ENCRYP_ESP_COMBINED_MODE, /*100 ESP组合模式*/ + e_SEC_ENCRYP_MODE_LAST, +} E_CMDK_SEC_ENCRYP_MODE; + +typedef enum +{ + e_SEC_SA_LIVETIME_NONE_TYPE = 0, /*00 none*/ + e_SEC_SA_LIVETIME_TIME_TYPE, /*01 生存时间*/ + e_SEC_SA_LIVETIME_BYTE_TYPE, /*10 byte数*/ + e_SEC_SA_LIVETIME_PKT_TYPE, /*11 pkt数(预留,目前不支持)*/ + e_SEC_SA_LIVETIME_TYPE_LAST, +} E_CMDK_LIVETIME_TYPES; + +#pragma pack(1) +typedef struct IPV4_HEAD +{ + UINT8 ip_headlen_version; + UINT8 ip_tos; + UINT16 usTotallen; + + UINT16 usIdentify; + UINT16 ip_fragoff; + + UINT8 uclive_time; + UINT8 ucProtocal; + UINT16 usHeadChecksum; + + UINT32 udSrcIpAddr; + UINT32 udDstIpAddr; +}T_IPV4_HEAD; +#pragma pack() + +typedef struct +{ + UINT32 DtbAddrH; /*地址的高32位*/ + UINT32 DtbAddrL; /*地址的低32位,两个地址组成64位然后左移4位得到68位的真实地址*/ + UINT32 DtbCmd; /*研规上的DTB_LEN字段 */ +}T_QUEUE_DTB_REG; + +//SA下表模块使用的结构体 +typedef struct +{ + UINT32 udSPI; + UINT32 udSaId; + UINT16 usSaParam; + UINT8 ucCiperID; + UINT8 ucAuthID; + UINT8 ucCipherkeyLen; + UINT8 ucAuthkeyLen; + UINT16 usFrag_State; + + UINT32 udESN; + UINT32 udSN; + UINT64 uddProcessedByteCnt; + + UINT32 udSalt; + UINT32 udLifetimeSecMax; + UINT64 uddLifetimByteCntMax; + + UINT8 ucProtocol; + UINT8 ucTOS; + UINT8 ucEsnFlag; + UINT8 ucIpType; + UINT32 udRSV0; + UINT32 udRSV1; + UINT32 udRSV2; + + UINT32 udSrcAddress0; + UINT32 udSrcAddress1; + UINT32 udSrcAddress2; + UINT32 udSrcAddress3; + + UINT32 udDstAddress0; + UINT32 udDstAddress1; + UINT32 udDstAddress2; + UINT32 udDstAddress3; + + UINT8 aucSaCipherKey[32]; + UINT8 aucSaAuthKey[128]; +}__attribute__((packed))T_HAL_SA_DTB_HW_OUT; + + typedef struct +{ + + UINT32 udSrcAddress0; + UINT32 udSrcAddress1; + UINT32 udSrcAddress2; + UINT32 udSrcAddress3; + + UINT32 udDstAddress0; + UINT32 udDstAddress1; + UINT32 udDstAddress2; + UINT32 udDstAddress3; + + UINT32 udSPI; + UINT32 udSaId; + UINT16 usSaParam; + UINT8 ucCiperID; + UINT8 ucAuthID; + UINT8 ucCipherkeyLen; + UINT8 ucAuthkeyLen; + UINT16 usFrag_State; + + UINT32 udSalt; + UINT32 udLifetimeSecMax; + UINT64 uddLifetimByteCntMax; + + UINT8 ucProtocol; + UINT8 ucTOS; + UINT8 ucEsnFlag; + UINT8 ucIpType; + UINT16 usOutSaOffset; + UINT16 udRSV0; + UINT32 udOutSaId; + UINT32 udRSV1; + + UINT8 aucBitmap[256]; + + UINT32 udAntiWindowHigh; + UINT32 udAntiWindowLow; + UINT64 uddProcessedByteCnt; + + UINT8 aucSaCipherKey[32]; + UINT8 aucSaAuthKey[128]; +}__attribute__((packed))T_HAL_SA_DTB_HW_IN; + +typedef enum +{ + e_HAL_IPSEC_CIPHER_NULL = 0x00, + e_HAL_IPSEC_CIPHER_AES_CTR = 0x11, + e_HAL_IPSEC_CIPHER_AES_CBC = 0x12, + e_HAL_IPSEC_CIPHER_AES_ECB = 0x13, + e_HAL_IPSEC_CIPHER_AES_GCM = 0x14, + e_HAL_IPSEC_CIPHER_AES_CCM = 0x15, + e_HAL_IPSEC_CIPHER_AES_GMAC = 0x16, + /* 新增SM4算法 */ + e_HAL_IPSEC_CIPHER_SM4_CTR = 0x17, + e_HAL_IPSEC_CIPHER_SM4_CBC = 0x18, + e_HAL_IPSEC_CIPHER_SM4_ECB = 0x19, + /* 新增XTS算法 */ + e_HAL_IPSEC_CIPHER_AES_XTS = 0x1a, + e_HAL_IPSEC_CIPHER_SM4_XTS = 0x1b, + + e_HAL_IPSEC_CIPHER_DES_CBC = 0x31, + e_HAL_IPSEC_CIPHER_3DES_CBC = 0x32, + e_HAL_IPSEC_CIPHER_CHACHA = 0x50, +}E_HAL_SEC_IPSEC_CIPHER_ALG; + +typedef enum +{ + e_HAL_IPSEC_AUTH_NULL = 0x00, + + /* 新增 */ + e_HAL_IPSEC_AUTH_AES_GMAC = 0x16, /* 1 */ + e_HAL_IPSEC_AUTH_SM4_GMAC = 0x1e, + + e_HAL_IPSEC_AUTH_AES_CMAC32 = 0x22, /* 3 */ + e_HAL_IPSEC_AUTH_AES_CMAC96 = 0x23, + e_HAL_IPSEC_AUTH_AES_XCBCMAC = 0x21, + e_HAL_IPSEC_AUTH_AES_SHA1 = 0x41, /* 6 */ + e_HAL_IPSEC_AUTH_AES_SHA224 = 0x42, + e_HAL_IPSEC_AUTH_AES_SHA256 = 0x44, + e_HAL_IPSEC_AUTH_AES_SHA384 = 0x45, + e_HAL_IPSEC_AUTH_AES_SHA512 = 0x46, + e_HAL_IPSEC_AUTH_AES_MD5 = 0x43, + e_HAL_IPSEC_AUTH_SM3 = 0x47, +}E_HAL_SEC_IPSEC_AUTH_ALG; + +typedef struct +{ + char alg_name[64]; + char compat_name[64]; + E_HAL_SEC_IPSEC_CIPHER_ALG e_zxdh_ealgo_id; +}T_ZXDH_EALGO; + +typedef struct +{ + char alg_name[64]; + char compat_name[64]; + E_HAL_SEC_IPSEC_AUTH_ALG e_zxdh_auth_id; +}T_ZXDH_ALGO; + + +void BttlPubDump(unsigned char *ucBuf, UINT32 udLen); +UINT32 CmdkBttlTestSecDtbSaAdd(struct zxdh_en_device *en_dev,E_CMDK_DTB_SA_CMD_TYPE eDtbSaCmdType,E_SA_TYPE eSaType,UINT64 uddSaVirAddr,UINT32 udDtbSaIsIntEn,UINT32 udDtbLen,UINT32 udQueIndex); +void zxdh_ipsec_del_sa(struct xfrm_state *xs); +bool zxdh_ipsec_offload_ok(struct sk_buff *skb, struct xfrm_state *xs); +void zxdh_ipsec_state_advance_esn (struct xfrm_state *x); +void zxdh_ipsec_state_update_curlft (struct xfrm_state *x); +int zxdh_ipsec_policy_add (struct xfrm_policy *x); +void zxdh_ipsec_policy_delete (struct xfrm_policy *x); +void zxdh_ipsec_policy_free (struct xfrm_policy *x); + +#endif + diff --git a/src/net/drivers/net/ethernet/dinghai/en_aux/en_1588_pkt_proc.c b/src/net/drivers/net/ethernet/dinghai/en_aux/en_1588_pkt_proc.c new file mode 100644 index 0000000..79f1a12 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_aux/en_1588_pkt_proc.c @@ -0,0 +1,489 @@ +/***************************************************************************** +(C) 2023 ZTE Corporation. 版权所有. + +文件名 : en_1588_pkt_proc.c +内容摘要 : 提供PTP数据包处理相关接口 +作者/日期 : Limin / 2023.10.12 +版本 : 1.0 +*****************************************************************************/ + +#include "en_1588_pkt_proc.h" +#include "en_ioctl.h" +#include "queue.h" + +#define PTP_MESSAGE_HRD_LEN 34 +#define IPV6_HDR_LEN 40 +#define IPV6_PROT_OFFSET 6 +#define UDP_DEST_PORT_OFFSET 2 +#define VLAN_TPID 0x8100 + +/* pi头中pkt_type字段值 */ +#define PTP_EVENT_TYPE_NOSECURITY 2 +#define PTP_EVENT_TYPE_SECURITY 3 +#define PTP_GENERAL_TYPE 0 +#define PTP_TYPE_OFFSET 4 +/* 下行层四1588微码是否需要查询ipsec表 */ +#define PTP_L4_NEED_QUERY_IPSEC_TABLE 1 +#define PTP_TYPE_L4_SECURITY_OFFSET 3 + +/* L3报文类型 */ +#define ETH_TYPE_PTP 0x88f7 +#define ETH_TYPE_IPV4 0x0800 +#define ETH_TYPE_IPV6 0x86dd + +/* L4报文类型 */ +#define ETH_TYPE_UDP 0x11 +#define ETH_TYPE_TCP 0x06 + +#define UDP_HDR_LEN 0x08 +#define TCP_HDR_LEN 0x14 + +/* 报文中关键字段的长度 */ +#define ETHER_TYPE_LEN 2 +#define ETHER_MAC_LEN 6 +#define L2_PKT_HDR_LEN ((2 * ETHER_MAC_LEN) + ETHER_TYPE_LEN) + +#define IP_PROT_OFFSET 9 /* IP头中protocol字段的偏移 */ + +#define PTP_MSG_ERROR_TYPE 0xff +#define PTPHDR_CF_OFFSET 8 + +#define VLAN_LEN 4 + +extern int get_hw_timestamp(struct zxdh_en_device *en_dev, u32 *hwts); +/* PTP报文类型和处理函数对应关系结构体 */ +typedef struct +{ + uint8_t type; + int32_t (*proc_func)(struct sk_buff *skb, \ + struct zxdh_net_hdr *hdr, \ + uint8_t *ptpHdr, \ + struct time_stamps *t5g, \ + struct time_stamps *tsn, \ + uint32_t *thw, \ + struct zxdh_en_device *en_dev); +} MsgProc_t; + +typedef struct +{ + uint8_t type; + int32_t (*proc_func)(struct zxdh_net_hdr_rcv *hdr, \ + uint8_t *ptpHdr, \ + struct time_stamps *t5g, \ + struct time_stamps *tsn, \ + uint32_t *thw, \ + struct skb_shared_info *ptSkbSharedInfo, + struct zxdh_en_device *en_dev); +} MsgRcv_t; + +/* PTP报文类型和处理函数对应关系表 */ +MsgProc_t g_MsgProcTable[] = +{ + {PTP_MSG_TYPE_SYNC, pkt_proc_type_sync }, + {PTP_MSG_TYPE_DELAY_REQ, pkt_proc_type_delay_req }, + {PTP_MSG_TYPE_PDELAY_REQ, pkt_proc_type_pdelay_req }, + {PTP_MSG_TYPE_PDELAY_RESP, pkt_proc_type_pdelay_resp }, + + {PTP_MSG_TYPE_FOLLOW_UP, pkt_proc_type_follow_up }, + {PTP_MSG_TYPE_DELAY_RESP, pkt_proc_type_delay_resp }, + {PTP_MSG_TYPE_PDELAY_RESP_FOLLOW_UP, pkt_proc_type_pdelay_resp_follow_up}, + {PTP_MSG_TYPE_ANNOUNCE, pkt_proc_type_announce }, + {PTP_MSG_TYPE_SIGNALING, pkt_proc_type_signaling }, + {PTP_MSG_TYPE_MANAGEMENT, pkt_proc_type_management }, + + {PTP_MSG_ERROR_TYPE, NULL } +}; + +MsgRcv_t g_MsgRcvTable[] = +{ + {PTP_MSG_TYPE_SYNC, pkt_rcv_type_event }, + {PTP_MSG_TYPE_DELAY_REQ, pkt_rcv_type_event }, + {PTP_MSG_TYPE_PDELAY_REQ, pkt_rcv_type_event }, + {PTP_MSG_TYPE_PDELAY_RESP, pkt_rcv_type_event }, + + {PTP_MSG_TYPE_DELAY_RESP, pkt_rcv_type_delay_resp }, + + {PTP_MSG_ERROR_TYPE, NULL } +}; + +/* 判断是否为事件报文 */ +bool is_event_message(const uint8_t msg_type) +{ + if (msg_type <= PTP_MSG_TYPE_PDELAY_RESP) + { + return true; + } + return false; +} + +/* 判断是否为普通报文 */ +bool is_general_message(const uint8_t msg_type) +{ + if ((PTP_MSG_TYPE_FOLLOW_UP <= msg_type) && (msg_type <= PTP_MSG_TYPE_MANAGEMENT)) + { + return true; + } + return false; +} + +/* p得到PTP报文头位置 */ +int32_t get_hdr_point(uint8_t *pData, uint8_t *piTs0ffset, uint8_t **ptpHdr) +{ + uint16_t udp_dest_port_ptp = 0; + uint16_t offset = 0; + uint16_t temp_len = 0; + uint16_t eth_type_lay3 = ntohs(*((uint16_t*)(pData + (2 * ETHER_MAC_LEN)))); /* get Eth Type */ + uint8_t eth_type_lay4 = 0; + uint8_t eth_type_lay4_ipv6 = 0; + uint16_t eth_type_vlan_lay3 = ntohs(*((uint16_t*)(pData + (2 * ETHER_MAC_LEN) + VLAN_LEN))); + + /* 计算PTP头的偏移 */ + offset = L2_PKT_HDR_LEN; + + if ((VLAN_TPID == eth_type_lay3) && (VLAN_TPID != eth_type_vlan_lay3)) /* 单vlan偏移 */ + { + offset += VLAN_LEN; + } + else if ((VLAN_TPID == eth_type_lay3) && (VLAN_TPID == eth_type_vlan_lay3)) /* 双vlan偏移 */ + { + offset += (VLAN_LEN * 2); + } + + eth_type_lay3 = ntohs(*((uint16_t*)(pData + offset - ETHER_TYPE_LEN))); + eth_type_lay4 = *(pData + offset + IP_PROT_OFFSET); + + eth_type_lay4_ipv6 = *(pData + offset + IPV6_PROT_OFFSET); + + if ((ETH_TYPE_PTP != eth_type_lay3) && (ETH_TYPE_IPV4 != eth_type_lay3) && (ETH_TYPE_IPV6 != eth_type_lay3)) + { + LOG_ERR("unknown L3 eth type: %d\n", eth_type_lay3); + return IS_NOT_PTP_MSG; + } + + if (ETH_TYPE_IPV4 == eth_type_lay3) + { + /* IP首部第一字节: 版本(4b)+首部长度（4b），这里取低4位，长度是以4字节为单位 */ + temp_len = *(pData + offset); + temp_len = (temp_len & 0x0f) * 4; + offset += temp_len; + + /* L4类型PTP只有UDP */ + if (ETH_TYPE_UDP == eth_type_lay4) + { + udp_dest_port_ptp = ntohs(*(uint16_t *)(pData + offset + UDP_DEST_PORT_OFFSET)); + if ((udp_dest_port_ptp != 319) && (udp_dest_port_ptp != 320)) + { + LOG_ERR("UDP destination port(%hd) is not 319 or 320!!\n", udp_dest_port_ptp); + return IS_NOT_PTP_MSG; + } + temp_len = UDP_HDR_LEN; + offset += temp_len; + } + else + { + LOG_ERR("eth_type_lay4 = %c, is not UDP!!!!!\n", eth_type_lay4); + return IS_NOT_PTP_MSG; + } + } + else if(ETH_TYPE_IPV6 == eth_type_lay3) + { + temp_len = IPV6_HDR_LEN; + offset += temp_len; + + /* L4类型PTP只有UDP */ + if (ETH_TYPE_UDP == eth_type_lay4_ipv6) + { + udp_dest_port_ptp = ntohs(*(uint16_t *)(pData + offset + UDP_DEST_PORT_OFFSET)); + if ((udp_dest_port_ptp != 319) && (udp_dest_port_ptp != 320)) + { + LOG_ERR("UDP destination port(%hd) is not 319 or 320!!\n", udp_dest_port_ptp); + return IS_NOT_PTP_MSG; + } + temp_len = UDP_HDR_LEN; + offset += temp_len; + } + else + { LOG_ERR("eth_type_lay4_ipv6 = %c, is not UDP!!!!!!\n",eth_type_lay4_ipv6); + return IS_NOT_PTP_MSG; + } + } + + *ptpHdr = pData + offset; + + /* 赋值pd头的ts_offset字段 */ + *piTs0ffset = offset; + + return PTP_SUCCESS; +} + +/* 从PTP报文头中解析出报文类型 */ +uint8_t get_msgtype_from_hrd(uint8_t *hrd, const uint8_t len) +{ + uint8_t msg_type = PTP_MSG_ERROR_TYPE; + + CHECK_UNEQUAL_ERR(len, PTP_MESSAGE_HRD_LEN, -EFAULT, "error len %d!", len); + + msg_type = hrd[0] & 0x0f; + if (is_event_message(msg_type) || is_general_message(msg_type)) + { + return msg_type; + } + + LOG_ERR("error message type %d", msg_type); + return PTP_MSG_ERROR_TYPE; +} + +/* 调用PTP模块驱动接口，读取3个时间戳：两个80bit（T1，T2），一个32bit（T3） */ +#ifdef PTP_DRIVER_INTERFACE_EN +extern int get_pkt_timestamp(int32_t clock_no, struct zxdh_en_device *en_dev, struct time_stamps *ts, u32 *hwts); +#endif /* PTP_DRIVER_INTERFACE_EN */ + +int32_t get_tstamps_from_ptp(int32_t clock_no, struct time_stamps *t5g, struct time_stamps *tsn, uint32_t *thw, struct zxdh_en_device *en_dev) +{ + uint32_t hwts = 0; + struct time_stamps ts[2] = {}; + +#ifdef PTP_DRIVER_INTERFACE_EN + int32_t ret = 0; + ret = get_pkt_timestamp(clock_no, en_dev, ts, &hwts);//todo + if (unlikely(ret != 0)) + { + LOG_ERR("netdev %s get tsn clock %d failed!, ret = %d", en_dev->netdev->name,clock_no,ret); + return -1; + } +#endif /* PTP_DRIVER_INTERFACE_EN */ + + LOG_DEBUG("===GET-PTP===: hwts=%u", hwts); + LOG_DEBUG("===GET-PTP===: ts[0].s=%llu, ts[0].ns=%u", ts[0].s, ts[0].ns); + LOG_DEBUG("===GET-PTP===: ts[1].s=%llu, ts[1].ns=%u", ts[1].s, ts[1].ns); + + *t5g = ts[1]; + *tsn = ts[1]; + *thw = hwts; + + return 0; +} +#ifdef TIME_STAMP_1588 +/* 发送流程中的报文时间戳处理 */ +int32_t pkt_1588_proc_xmit(struct sk_buff *skb, struct zxdh_net_hdr *hdr, int32_t clock_no, struct zxdh_en_device *en_dev) +{ + struct time_stamps ts_5g; /* 5G时间戳，有效值80bit */ + struct time_stamps ts_tsn; /* TSN时间戳，有效值80bit */ + uint32_t ts_thw = 0; /* 硬件当前时间戳，有效值32bit */ + uint8_t *pData = NULL; + uint8_t *ptpHdr = NULL; + uint8_t ret = 0; + uint8_t i = 0; + uint8_t cnt = 0; + uint8_t msg_type = 0xff; + struct ptpHdr_t *ptPtpHdr = NULL; + + memset(&ts_5g, 0, sizeof(struct time_stamps)); + memset(&ts_tsn, 0, sizeof(struct time_stamps)); + + CHECK_EQUAL_ERR(skb, NULL, -EADDRNOTAVAIL, "skb is NULL!\n"); + CHECK_EQUAL_ERR(hdr, NULL, -EADDRNOTAVAIL, "hdr is NULL!\n"); + + pData = skb->data; + + /* 获得ptp报文头指针&赋值pd头ts_offset字段 */ + ret = get_hdr_point(pData, &(hdr->ts_offset), &ptpHdr); + CHECK_EQUAL_ERR(ptpHdr, NULL, -EADDRNOTAVAIL, "get ptp hdr failed!\n"); + CHECK_UNEQUAL_ERR(ret, 0, ret, "is not ptp msg or get hdr err!!\n"); + + ptPtpHdr = (struct ptpHdr_t *)ptpHdr; + char * phdr = (char *)ptPtpHdr; + + /* 解析PTP报文类型 */ + msg_type = get_msgtype_from_hrd(ptpHdr, PTP_MESSAGE_HRD_LEN); + CHECK_EQUAL_ERR(msg_type, PTP_MSG_ERROR_TYPE, -EFAULT, "unknow PTP msg type!\n"); + + /* 如果是事件报文，提取时间戳 */ + if (is_event_message(msg_type)) + { + ret = get_tstamps_from_ptp(clock_no, &ts_5g, &ts_tsn, &ts_thw, en_dev); + CHECK_UNEQUAL_ERR(ret, 0, -EFAULT, "get tstamps from ptp failed!\n"); + + /* ptp_type[2]的低bit2-4表示pkt_type,加密事件报文类型为2，非加密事件报文为3, */ + hdr->ptp_type[2] = (hdr->ptp_type[2] & 0x8F) + (PTP_EVENT_TYPE_NOSECURITY << PTP_TYPE_OFFSET); + if (0 != ((ptPtpHdr->flagField) & 0x0080)) + { + hdr->ptp_type[2] = (hdr->ptp_type[2] & 0x8F) + (PTP_EVENT_TYPE_SECURITY << PTP_TYPE_OFFSET); + } + } + else + { + /* 普通报文类型为0 */ + hdr->ptp_type[2] = (hdr->ptp_type[2] & 0x8F) + (PTP_GENERAL_TYPE << PTP_TYPE_OFFSET); + } + /* 层四1588报文,下行微码处理时，是否需要查ipsec表, 加密报文需要 */ + LOG_INFO("ptPtpHdr->flagField: 0x%x\n", ptPtpHdr->flagField); + if (0 != ((ptPtpHdr->flagField) & 0x0080)) + { + hdr->ptp_type[2] = (hdr->ptp_type[2] & 0xF7) + (PTP_L4_NEED_QUERY_IPSEC_TABLE << PTP_TYPE_L4_SECURITY_OFFSET); + LOG_INFO("hdr->ptp_type[2]: 0x%x\n", hdr->ptp_type[2]); + } + /* 层二发送方向的出端口需要这里指示 */ + hdr->port = en_dev->phy_port; + + /* 根据不同报文类型做不同处理 */ + cnt = sizeof(g_MsgProcTable) / sizeof(MsgProc_t); + for (i = 0; i < cnt; i++) + { + if (g_MsgProcTable[i].type == msg_type) + { + if (likely(g_MsgProcTable[i].proc_func != NULL)) + { + ret = g_MsgProcTable[i].proc_func(skb, hdr, ptpHdr, &ts_5g, &ts_tsn, &ts_thw, en_dev); + } + } + } + + return ret; +} +#endif +/* 接收流程中的报文时间戳处理 */ +int32_t pkt_1588_proc_rcv(struct sk_buff *skb, struct zxdh_net_hdr_rcv *hdr, int32_t clock_no, struct zxdh_en_device *en_dev) +{ + struct time_stamps ts_5g; /* 5G时间戳，有效值80bit */ + struct time_stamps ts_tsn; /* TSN时间戳，有效值80bit */ + uint32_t ts_thw = 0; /* 硬件当前时间戳，有效值32bit */ + uint8_t *pData = NULL; + uint8_t *ptpHdr = NULL; + int32_t ret = 0; + uint8_t i = 0; + uint8_t cnt = 0; + uint8_t msg_type = 0xff; + uint8_t piTsOffset = 0; + + memset(&ts_5g, 0, sizeof(struct time_stamps)); + memset(&ts_tsn, 0, sizeof(struct time_stamps)); + + CHECK_EQUAL_ERR(skb, NULL, -EADDRNOTAVAIL, "skb is NULL!\n"); + CHECK_EQUAL_ERR(hdr, NULL, -EADDRNOTAVAIL, "hdr is NULL!\n"); + + pData = skb->data;//TODO,大包data可能会填到非线性区，此处需要修改。 + + print_data((uint8_t *)hdr, sizeof(struct zxdh_net_hdr)+16); //todo + print_data(skb->data, skb->len); + + /* 获得ptp报文头指针&赋值pi头ts_offset字段 */ + ret = get_hdr_point(pData, &piTsOffset, &ptpHdr); + CHECK_EQUAL_ERR(ptpHdr, NULL, -EADDRNOTAVAIL, "get ptp hdr failed!\n"); + CHECK_UNEQUAL_ERR(ret, 0, ret, "is not ptp msg or get hdr err!!\n"); + + /* 解析PTP报文类型 */ + msg_type = get_msgtype_from_hrd(ptpHdr, PTP_MESSAGE_HRD_LEN); + CHECK_EQUAL_ERR(msg_type, PTP_MSG_ERROR_TYPE, -EFAULT, "unknow PTP msg type!\n"); + + /* 如果是事件报文，提取时间戳 */ + if (is_event_message(msg_type)) + { + ret = get_tstamps_from_ptp(clock_no, &ts_5g, &ts_tsn, &ts_thw, en_dev); + CHECK_UNEQUAL_ERR(ret, 0, -EFAULT, "get tstamps from ptp failed!\n"); + } + + /* 根据不同报文类型做不同处理 */ + cnt = sizeof(g_MsgRcvTable) / sizeof(MsgRcv_t); + for (i = 0; i < cnt; i++) + { + if (g_MsgRcvTable[i].type == msg_type) + { + if (likely(g_MsgRcvTable[i].proc_func != NULL)) + { + ret = g_MsgRcvTable[i].proc_func(hdr, ptpHdr, &ts_5g, &ts_tsn, &ts_thw, skb_shinfo(skb), en_dev); + } + } + } + + return ret; +} + +int32_t is_delay_statistics_pkt(uint8_t *pData) +{ + uint16_t udp_dest_port = 0; + uint16_t offset = 0; + uint16_t temp_len = 0; + uint16_t eth_type_lay3 = ntohs(*((uint16_t*)(pData + (2 * ETHER_MAC_LEN)))); /* get Eth Type */ + uint8_t eth_type_lay4 = 0; + uint8_t eth_type_lay4_ipv6 = 0; + uint16_t eth_type_vlan_lay3 = ntohs(*((uint16_t*)(pData + (2 * ETHER_MAC_LEN) + VLAN_LEN))); + + /* 计算PTP头的偏移 */ + offset = L2_PKT_HDR_LEN; + + if ((VLAN_TPID == eth_type_lay3) && (VLAN_TPID != eth_type_vlan_lay3)) /* 单vlan偏移 */ + { + offset += VLAN_LEN; + } + else if ((VLAN_TPID == eth_type_lay3) && (VLAN_TPID == eth_type_vlan_lay3)) /* 双vlan偏移 */ + { + offset += (VLAN_LEN * 2); + } + + eth_type_lay3 = ntohs(*((uint16_t*)(pData + offset - ETHER_TYPE_LEN))); + eth_type_lay4 = *(pData + offset + IP_PROT_OFFSET); + + eth_type_lay4_ipv6 = *(pData + offset + IPV6_PROT_OFFSET); + + if (ETH_TYPE_IPV4 != eth_type_lay3) + { + // LOG_ERR("unknown L4 eth type: %d\n", eth_type_lay3); + return IS_NOT_STATISTICS_PKT; + } + + if (ETH_TYPE_IPV4 == eth_type_lay3) + { + /* IP首部第一字节: 版本(4b)+首部长度（4b），这里取低4位，长度是以4字节为单位 */ + temp_len = *(pData + offset); + temp_len = (temp_len & 0x0f) * 4; + offset += temp_len; + + /* L4类型PTP只有UDP */ + if (ETH_TYPE_UDP == eth_type_lay4) + { + udp_dest_port = ntohs(*(uint16_t *)(pData + offset + UDP_DEST_PORT_OFFSET)); + if (udp_dest_port != 49184) + { + // LOG_ERR("UDP destination port(%hd) is not 49184!!\n", udp_dest_port); + return IS_NOT_STATISTICS_PKT; + } + } + else + { + // LOG_ERR("eth_type_lay4 = %c, is not UDP!!!!!\n", eth_type_lay4); + return IS_NOT_STATISTICS_PKT; + } + } + + return PTP_SUCCESS; +} + +/* delay统计报文发送流程中的时间戳处理 */ +int32_t pkt_delay_statistics_proc(struct sk_buff *skb, struct zxdh_net_hdr *hdr, struct zxdh_en_device *en_dev) +{ + uint8_t *pData = NULL; + uint8_t ret = 0; + uint32_t ts_thw = 0; + + CHECK_EQUAL_ERR(skb, NULL, -EADDRNOTAVAIL, "skb is NULL!\n"); + CHECK_EQUAL_ERR(hdr, NULL, -EADDRNOTAVAIL, "hdr is NULL!\n"); + + pData = skb->data; + + /* 检查是否是delay统计报文: udp端口号：49184 */ + if(IS_NOT_STATISTICS_PKT == is_delay_statistics_pkt(pData)) + { + return DELAY_STATISTICS_FAILED; + } + /* 时延统计使能 */ + hdr->pd_hdr.ol_flag |= htons(DELAY_STATISTICS_INSERT_EN_BIT); + + ret = get_hw_timestamp(en_dev, &ts_thw); + CHECK_UNEQUAL_ERR(ret, 0, -EFAULT, "get_hw_timestamp failed!\n"); + + /*hw的时间戳，写到 PD头的5~8字节:高29位为ns位，低3bits位为小数ns位 */ + *(uint32_t*)(&(hdr->pd_hdr.tag_idx)) = htonl(ts_thw << CPU_TX_DECIMAL_NS); /* 大端对齐 */ + + return ret; +} diff --git a/src/net/drivers/net/ethernet/dinghai/en_aux/en_1588_pkt_proc.h b/src/net/drivers/net/ethernet/dinghai/en_aux/en_1588_pkt_proc.h new file mode 100644 index 0000000..63af628 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_aux/en_1588_pkt_proc.h @@ -0,0 +1,34 @@ +/***************************************************************************** +(C) 2023 ZTE Corporation. 版权所有. + +文件名 : en_1588_pkt_proc.h +内容摘要 : 提供PTP数据包处理相关接口 +作者/日期 : Limin / 2023.10.12 +版本 : 1.0 +*****************************************************************************/ + +#ifndef _EN_1588_PKT_PROC_H_ +#define _EN_1588_PKT_PROC_H_ + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +#include "en_1588_pkt_proc_func.h" + +#define PTP_SUCCESS 0 +#define PTP_FAILED (-1) +#define IS_NOT_PTP_MSG 1 +#define IS_NOT_STATISTICS_PKT 1 +#define DELAY_STATISTICS_FAILED (-1) + +int32_t pkt_1588_proc_xmit(struct sk_buff *skb, struct zxdh_net_hdr *hdr, int32_t clock_no, struct zxdh_en_device *en_dev); +int32_t pkt_1588_proc_rcv(struct sk_buff *skb, struct zxdh_net_hdr_rcv *hdr, int32_t clock_no, struct zxdh_en_device *en_dev); +int32_t pi_1588_net_hdr_add(struct sk_buff *skb, struct zxdh_net_hdr *hdr, int32_t clock_no, struct zxdh_en_device *en_dev); +int32_t pkt_delay_statistics_proc(struct sk_buff *skb, struct zxdh_net_hdr *hdr, struct zxdh_en_device *en_dev); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* _EN_1588_PKT_PROC_H_ */ \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_aux/en_1588_pkt_proc_func.c b/src/net/drivers/net/ethernet/dinghai/en_aux/en_1588_pkt_proc_func.c new file mode 100644 index 0000000..53786dc --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_aux/en_1588_pkt_proc_func.c @@ -0,0 +1,673 @@ +/***************************************************************************** +(C) 2023 ZTE Corporation. 版权所有. + +文件名 : en_1588_pkt_proc_func.c +内容摘要 : 不同数据类型包的处理接口实现 +作者/日期 : Limin / 2023.10.12 +版本 : 1.0 +*****************************************************************************/ + +#include "en_1588_pkt_proc_func.h" +#include "en_cmd.h" +#include "en_ioctl.h" + +struct ptp_update_buff tGlobalPtpBuff = {0}; + +uint64_t htonll(uint64_t u64_host) +{ + uint64_t u64_net = 0; + uint32_t u32_host_h = 0; + uint32_t u32_host_l = 0; + + u32_host_l = u64_host & 0xffffffff; + u32_host_h = (u64_host >> 32) & 0xffffffff; + + u64_net = htonl(u32_host_l); + u64_net = ( u64_net << 32 ) | htonl(u32_host_h); + + return u64_net; +} + +/** +* @brief 计算两时间戳subtraction和minuend之差，并将差值赋值给*ptMinusRet +* @param minuend 高48bit为s位，低32bit为ns位 +*/ +int32_t bits_80_minus(struct time_stamps subtraction, Bits80_t minuend, struct time_stamps *ptMinusRet) +{ + uint64_t minusHigh48_s = 0; + uint32_t minusLow32_ns = 0; + + /* 取出80bits被减数的ns位值和s位值 */ + memcpy((uint8_t *)(&minusHigh48_s), &minuend, S_SIZE); + memcpy(&minusLow32_ns, (uint8_t *)(&minuend) + S_SIZE, NS_SIZE); + + /* minuend大端 */ + minusHigh48_s = htonll(minusHigh48_s) >> 16; + minusLow32_ns = htonl(minusLow32_ns); + + /* 如果减数值小于被减数值 */ + if ((subtraction.s < minusHigh48_s) || ((subtraction.s == minusHigh48_s) && (subtraction.ns < minusLow32_ns))) + { + LOG_ERR("The difference between the two times is negative！！"); + return PTP_RET_TIME_ERR; + } + + if (subtraction.ns > minusLow32_ns) + { + ptMinusRet->ns = subtraction.ns - minusLow32_ns; /* 赋值ns位 */ + ptMinusRet->s = subtraction.s - minusHigh48_s; /* 赋值s位 */ + } + else + { + ptMinusRet->ns = S_HOLD - (minusLow32_ns - subtraction.ns); /* 赋值ns位 */ + ptMinusRet->s = subtraction.s - minusHigh48_s - 1; /* 赋值s位 */ + } + + return PTP_RET_SUCCESS; +} + +int32_t pkt_proc_type_sync(struct sk_buff *skb, \ + struct zxdh_net_hdr *hdr, \ + uint8_t *ptpHdr, \ + struct time_stamps *t5g, \ + struct time_stamps *tsn, \ + uint32_t *thw, \ + struct zxdh_en_device *en_dev) +{ + struct SkbSharedHwtstamps_t tShhwtstamps; + struct time_stamps tMinusRet; + struct skb_shared_hwtstamps tHwtstamps5g; + struct skb_shared_hwtstamps tHwtstampsTsn; + Bits80_t tTsi; + struct ptpHdr_t * ptPtpHdr = NULL; + uint8_t *pOriginTimeStamp = NULL; + uint8_t majorSdoId = 0; + uint32_t t5gNsBig = 0; + uint64_t t5gSBig = 0; + uint32_t tsnNsBig = 0; + uint64_t tsnSBig = 0; +#ifdef TIME_STAMP_1588 + uint32_t frequency = 0; + uint64_t cfAddedVal = 0; + uint8_t *tsiTlv = NULL; + uint32_t cpuTx_ns = 0; + uint32_t cpuTx_frac_ns = 0; + uint64_t cfNs = 0; +#endif + + ptPtpHdr = (struct ptpHdr_t *)ptpHdr; + majorSdoId = ((ptPtpHdr->majorType) & 0xf0) >> 4; + pOriginTimeStamp = ptpHdr + sizeof(struct ptpHdr_t); + t5gSBig = (htonll(t5g->s)) >> 16; + t5gNsBig = htonl(t5g->ns); + tsnSBig = (htonll(tsn->s)) >> 16; + tsnNsBig = htonl(tsn->ns); + + memset(&tShhwtstamps, 0, sizeof(struct SkbSharedHwtstamps_t)); + memset(&tHwtstamps5g, 0, sizeof(struct skb_shared_hwtstamps)); + memset(&tHwtstampsTsn, 0, sizeof(struct skb_shared_hwtstamps)); + memset(&tMinusRet, 0, sizeof(struct time_stamps)); + memset(&tTsi, 0, sizeof(Bits80_t)); +#ifdef TIME_STAMP_1588 + /* 解析PTP Header的majorSdoId字段，如果是0，表示PTP消息由1588使用 */ + if (0 == majorSdoId) + { + /* 解析Flag字段低一字节bit1，如果为0，则是一步法,为1不做处理 */ + if (0 == ((ptPtpHdr->flagField) & 0x0002)) + { + memcpy(pOriginTimeStamp, &t5gSBig, S_SIZE); + memcpy(pOriginTimeStamp + S_SIZE, &t5gNsBig, NS_SIZE); + } + } + else if (1 == majorSdoId) /* 如果是1，表示PTP消息由802.1AS协议使用 */ + { + /* 解析Flag字段低一字节bit1，如果为0，则是一步法 */ + if (0 == ((ptPtpHdr->flagField) & 0x0002)) + { + /* tsn时间戳放到Sync报文的originTimestamp字段 */ + memcpy(pOriginTimeStamp, &tsnSBig, S_SIZE); + memcpy(pOriginTimeStamp + S_SIZE, &tsnNsBig, NS_SIZE); + + if (0 != ((ptPtpHdr->flagField) & 0x8000)) /* 解析Flag字段高一字节bit7，如果为1，做如下处理，为0不做处理*/ + { + frequency = *(uint32_t *)(ptpHdr + PTPHDR_FREQUENCY_OFFSET); + frequency = htonl(frequency);/* 频率比 */ + + memcpy(&tTsi, ptpHdr + PTPHDR_TSI_OFFSET, sizeof(Bits80_t)); + + bits_80_minus(*t5g, tTsi, &tMinusRet); + + /* （*t5g-*tsi）*频率比 计算结果叠加到CF字段ns位，(不会出现CF字段ns位值溢出情况) */ + cfAddedVal = (tMinusRet.s * S_HOLD + tMinusRet.ns) * frequency; + memcpy(&cfNs, ptPtpHdr->correctionField, CF_NS_SIZE); + cfNs = htonll(cfNs) >> 16; + cfNs += cfAddedVal; + cfNs = htonll(cfNs) >> 16; + memcpy(&(ptPtpHdr->correctionField[0]), &cfNs, CF_NS_SIZE); + + /* flagField字段的高1字节bit7清0 */ + ptPtpHdr->flagField = (ptPtpHdr->flagField) & 0x7f; + + /* 清除20 byte tTsi TLV为0 */ + tsiTlv = ptpHdr + PTPHDR_TSI_TLV_OFFSET; + memset(tsiTlv, 0, PTPHDR_TSI_TLV_LEN); + + /* 把Header中的messageLength值减去20 */ + ptPtpHdr->msglen = htons(ptPtpHdr->msglen); + ptPtpHdr->msglen -= PTPHDR_TSI_TLV_LEN; + ptPtpHdr->msglen = htons(ptPtpHdr->msglen); + } + } + else /* 如果为1，则是两步法 */ + { + /* 解析Flag字段高一字节bit7，如果为1，做如下处理，为0不做处理 */ + if (0 != ((ptPtpHdr->flagField) & 0x8000)) + { + memcpy(&tTsi, ptpHdr + PTPHDR_TSI_OFFSET, sizeof(Bits80_t)); + + bits_80_minus(*t5g, tTsi, &tMinusRet); + + /* （*t5g-*tsi）*频率比 计算结果叠加到CF字段ns位，(不会出现CF字段ns位值溢出情况) */ + frequency = htonl(ptPtpHdr-> msgTypeSpecific); + cfAddedVal = (tMinusRet.s * S_HOLD + tMinusRet.ns) * frequency; + memcpy(&cfNs, ptPtpHdr->correctionField, CF_NS_SIZE); + cfNs = htonll(cfNs) >> 16; + cfNs += cfAddedVal; + cfNs = htonll(cfNs) >> 16; + memcpy(&(ptPtpHdr->correctionField[0]), &cfNs, CF_NS_SIZE); + + /* 将messagetypespecific清0 */ + memset(&(ptPtpHdr->msgTypeSpecific), 0, sizeof(uint32_t)); + + /* flagField字段的高1字节bit7清0 */ + ptPtpHdr->flagField = (ptPtpHdr->flagField) & 0x7f; + + /* 清除20 byte tTsi TLV为0 */ + tsiTlv = ptpHdr + PTPHDR_TSI_TLV_OFFSET_TWO; + memset(tsiTlv, 0, PTPHDR_TSI_TLV_LEN); + + /* 把Header中的messageLength值减去20 */ + ptPtpHdr->msglen = htons(ptPtpHdr->msglen); + ptPtpHdr->msglen -= PTPHDR_TSI_TLV_LEN; + ptPtpHdr->msglen = htons(ptPtpHdr->msglen); + } + } + } + + /*PTPM的32bit的时间戳，写到 PI头的cpu_tx字段:高29位为ns位，低3bits位为小数ns位 */ + cpuTx_frac_ns = (hdr->cpu_tx) & 0x07; + cpuTx_ns = *thw << CPU_TX_DECIMAL_NS; + hdr->cpu_tx = htonl(cpuTx_ns + cpuTx_frac_ns); /* 大端对齐 */ + + /* 两个80bit时间戳（T1，T2）放到socket的ERR_QUEUE中 */ + tShhwtstamps.ts_5g_t = *t5g; + tShhwtstamps.ts_tsn_t = *tsn; + tHwtstamps5g.hwtstamp = tShhwtstamps.ts_5g_t.ns + tShhwtstamps.ts_5g_t.s * S_HOLD; + tHwtstampsTsn.hwtstamp = tShhwtstamps.ts_tsn_t.ns + tShhwtstamps.ts_tsn_t.s * S_HOLD; + skb_tstamp_tx(skb, &tHwtstamps5g); +#ifdef CGEL_TSTAMP_2_PATCH_EN + skb_tstamp_tx_2(skb, &tHwtstampsTsn); +#endif /* CGEL_TSTAMP_2_PATCH_EN */ +#endif + return PTP_RET_SUCCESS; +} + +int32_t delay_and_pdelay_req_proc(struct sk_buff *skb, \ + struct zxdh_net_hdr *hdr, \ + struct time_stamps *t5g, \ + struct time_stamps *tsn, \ + uint32_t *thw) +{ +#ifdef TIME_STAMP_1588 + struct SkbSharedHwtstamps_t tShhwtstamps; + struct skb_shared_hwtstamps tHwtstamps5g; + struct skb_shared_hwtstamps tHwtstampsTsn; + uint32_t cpuTx_ns = 0; + uint32_t cpuTx_frac_ns = 0; + + memset(&tShhwtstamps, 0, sizeof(struct SkbSharedHwtstamps_t)); + memset(&tHwtstamps5g, 0, sizeof(struct skb_shared_hwtstamps)); + memset(&tHwtstampsTsn, 0, sizeof(struct skb_shared_hwtstamps)); + /*PTPM的32bit的时间戳，写到 PI头的cpu_tx字段:高29位为ns位，低3bits位为小数ns位 */ + cpuTx_frac_ns = (hdr->cpu_tx) & 0x07; + cpuTx_ns = *thw << CPU_TX_DECIMAL_NS; + hdr->cpu_tx = htonl(cpuTx_ns + cpuTx_frac_ns); + + tShhwtstamps.ts_5g_t = *t5g; + tShhwtstamps.ts_tsn_t = *tsn; + + /* 2个80bit放到socket error queue中 */ + tHwtstamps5g.hwtstamp = tShhwtstamps.ts_5g_t.ns + tShhwtstamps.ts_5g_t.s * S_HOLD; + tHwtstampsTsn.hwtstamp = tShhwtstamps.ts_tsn_t.ns + tShhwtstamps.ts_tsn_t.s * S_HOLD; + skb_tstamp_tx(skb, &tHwtstamps5g); +#ifdef CGEL_TSTAMP_2_PATCH_EN + skb_tstamp_tx_2(skb, &tHwtstampsTsn); +#endif /* CGEL_TSTAMP_2_PATCH_EN */ +#endif + return PTP_RET_SUCCESS; +} + +int32_t pkt_proc_type_delay_req(struct sk_buff *skb, \ + struct zxdh_net_hdr *hdr, \ + uint8_t *ptpHdr, \ + struct time_stamps *t5g, \ + struct time_stamps *tsn, \ + uint32_t *thw, \ + struct zxdh_en_device *en_dev) +{ + int32_t ret = 0; + ret = delay_and_pdelay_req_proc(skb, hdr, t5g, tsn, thw); + return ret; +} + +int32_t pkt_proc_type_pdelay_req(struct sk_buff *skb, \ + struct zxdh_net_hdr *hdr, \ + uint8_t *ptpHdr, \ + struct time_stamps *t5g, \ + struct time_stamps *tsn, \ + uint32_t *thw, \ + struct zxdh_en_device *en_dev) +{ + int32_t ret = 0; + ret = delay_and_pdelay_req_proc(skb, hdr, t5g, tsn, thw); + return ret; +} + +int32_t pkt_proc_type_pdelay_resp(struct sk_buff *skb, \ + struct zxdh_net_hdr *hdr, \ + uint8_t *ptpHdr, \ + struct time_stamps *t5g, \ + struct time_stamps *tsn, \ + uint32_t *thw, \ + struct zxdh_en_device *en_dev) +{ +#ifdef TIME_STAMP_1588 + Bits80_t tReqReceTs; + struct SkbSharedHwtstamps_t tShhwtstamps; + struct skb_shared_hwtstamps tHwtstamps5g; + struct skb_shared_hwtstamps tHwtstampsTsn; + struct time_stamps tMinusRet; + struct ptpHdr_t *ptPtpHdr = NULL; + uint64_t MinusVal = 0; + uint32_t cpuTx_ns = 0; + uint32_t cpuTx_frac_ns = 0; + uint64_t cfNs = 0; + + memset(&tReqReceTs, 0, sizeof(Bits80_t)); + memset(&tShhwtstamps, 0, sizeof(struct SkbSharedHwtstamps_t)); + memset(&tMinusRet, 0, sizeof(struct time_stamps)); + memset(&tHwtstamps5g, 0, sizeof(struct skb_shared_hwtstamps)); + memset(&tHwtstampsTsn, 0, sizeof(struct skb_shared_hwtstamps)); + ptPtpHdr = (struct ptpHdr_t *)ptpHdr; + + /*PTPM的32bit的时间戳，写到 PI头的cpu_tx字段:高29位为ns位，低3bits位为小数ns位 */ + cpuTx_frac_ns = (hdr->cpu_tx) & 0x07; + cpuTx_ns = *thw << CPU_TX_DECIMAL_NS; + hdr->cpu_tx = htonl(cpuTx_ns + cpuTx_frac_ns); + + /* 解析Header中flagField的低1字节的bit1，如果是0（一步法） */ + if (0 == (ptPtpHdr->flagField & 0x0002)) + { + /* 提取requestRecieptTimestamp */ + tReqReceTs = *(Bits80_t *)(ptpHdr + sizeof(struct ptpHdr_t)); /* 记为T2 */ + + /* 将*tsn-T2的差值加到CorrectionField字段的高48bit ns位上 */ + bits_80_minus(*tsn, tReqReceTs, &tMinusRet); + MinusVal = tMinusRet.ns + tMinusRet.s * S_HOLD; + memcpy(&cfNs, ptPtpHdr->correctionField, CF_NS_SIZE); + cfNs = htonll(cfNs) >> 16; + cfNs += MinusVal; + cfNs = htonll(cfNs) >> 16; + memcpy(&(ptPtpHdr->correctionField[0]), &cfNs, CF_NS_SIZE); + } + + tShhwtstamps.ts_5g_t = *t5g; + tShhwtstamps.ts_tsn_t = *tsn; + + /* 2个80bit放到socket error queue中 */ + tHwtstamps5g.hwtstamp = tShhwtstamps.ts_5g_t.ns + tShhwtstamps.ts_5g_t.s * S_HOLD; + tHwtstampsTsn.hwtstamp = tShhwtstamps.ts_tsn_t.ns + tShhwtstamps.ts_tsn_t.s * S_HOLD; + skb_tstamp_tx(skb, &tHwtstamps5g); +#ifdef CGEL_TSTAMP_2_PATCH_EN + skb_tstamp_tx_2(skb, &tHwtstampsTsn); +#endif /* CGEL_TSTAMP_2_PATCH_EN */ +#endif + return PTP_RET_SUCCESS; +} + +/* 接收方向的事件报文的时间戳处理函数：在1588驱动中对接收方向的事件报文的时间戳处理是一致的 */ +int32_t pkt_rcv_type_event(struct zxdh_net_hdr_rcv *hdr, \ + uint8_t *ptpHdr, \ + struct time_stamps *t5g, \ + struct time_stamps *tsn, \ + uint32_t *thw, \ + struct skb_shared_info *ptSkbSharedInfo, \ + struct zxdh_en_device *en_dev) +{ +#ifdef TIME_STAMP_1588 + struct SkbSharedHwtstamps_t tShhwtstamps; + uint32_t tsRx = 0; + uint32_t tsRx_ns = 0; + uint32_t tsRx_frac_ns = 0; + int32_t MinusRetThwCpu = 0; + uint64_t temp = 0x20000000; + uint32_t i = 0; + + memset(&tShhwtstamps, 0, sizeof(struct SkbSharedHwtstamps_t)); + /* cpu_tx高29bits ns位，低3bits小数ns位 */ + tsRx = htonl(hdr->rx_ts); + + tsRx_frac_ns = tsRx & 0x07; + tsRx_ns = tsRx >> 3; + // LOG_DEBUG("hdr->rx_ts = %d, tsRx = %d, tsRx_ns = %d\n", hdr->rx_ts, tsRx, tsRx_ns); + + if (tsRx_frac_ns > 4) + { + tsRx_ns += 1; + } + // LOG_DEBUG("thw = %d, tsRx_ns = %d\n", *thw, tsRx_ns); + MinusRetThwCpu = (*thw & 0x1fffffff) - tsRx_ns; + + if(MinusRetThwCpu < 0) + { + MinusRetThwCpu += temp; + } + + LOG_DEBUG("MinusRetThwCpu = %d\n", MinusRetThwCpu); + + tShhwtstamps.ts_5g_t = *t5g; + tShhwtstamps.ts_tsn_t = *tsn; + + /* 更新两个80bits时间戳 */ + if (tShhwtstamps.ts_5g_t.ns > MinusRetThwCpu) + { + tShhwtstamps.ts_5g_t.ns -= MinusRetThwCpu; + } + else + { + for (i = 1; i < tShhwtstamps.ts_5g_t.s + 1; i++) + { + temp = i * S_HOLD + tShhwtstamps.ts_5g_t.ns; + + if (temp > MinusRetThwCpu) + { + tShhwtstamps.ts_5g_t.ns = temp - MinusRetThwCpu; + tShhwtstamps.ts_5g_t.s -= i; + break; + } + } + if (temp < MinusRetThwCpu) + { + LOG_ERR("ts_5g_t < MinusRetThwCpu!!!\n"); + } + } + + if (tShhwtstamps.ts_tsn_t.ns > MinusRetThwCpu) + { + tShhwtstamps.ts_tsn_t.ns -= MinusRetThwCpu; + } + else + { + for (i = 1; i < tShhwtstamps.ts_tsn_t.s + 1; i++) + { + temp = i * S_HOLD + tShhwtstamps.ts_tsn_t.ns; + if(temp > MinusRetThwCpu) + { + tShhwtstamps.ts_tsn_t.ns = temp - MinusRetThwCpu; + tShhwtstamps.ts_tsn_t.s -= i; + break; + } + } + if (temp < MinusRetThwCpu) + { + LOG_ERR("ts_tsn_t < MinusRetThwCpu!!!\n"); + } + } + + LOG_DEBUG("enter in pkt_rcv_type_event!!!!\n"); + LOG_DEBUG("tShhwtstamps.ts_5g_t.s = %llu, tShhwtstamps.ts_5g_t.ns = %d\n", tShhwtstamps.ts_5g_t.s, tShhwtstamps.ts_5g_t.ns); + LOG_DEBUG("tShhwtstamps.ts_tsn_t.s = %llu, tShhwtstamps.ts_tsn_t.ns = %d\n", tShhwtstamps.ts_tsn_t.s, tShhwtstamps.ts_tsn_t.ns); + + /* 2个80bit放到socket cmsg中。连同报文返回给应用 */ + ptSkbSharedInfo->hwtstamps.hwtstamp = ktime_set(tShhwtstamps.ts_5g_t.s, tShhwtstamps.ts_5g_t.ns); +#ifdef CGEL_TSTAMP_2_PATCH_EN + ptSkbSharedInfo->hwtstamps2.hwtstamp = ktime_set(tShhwtstamps.ts_tsn_t.s, tShhwtstamps.ts_tsn_t.ns); +#endif /* CGEL_TSTAMP_2_PATCH_EN */ +#endif + return PTP_RET_SUCCESS; +} + +/** +* @fn read_ts_match_info +* @brief 查询时间戳匹配信息，查询到匹配信息后更新cf字段和本地时间戳信息 +* @param msgType ptp事件报文类型 +* @return 返回值为0表示查询时间戳匹配信息成功 +*/ +int32_t read_ts_match_info(uint32_t msgType, uint8_t *ptpHdr) +{ + uint32_t mssageType = 0; + int32_t cfNum = 0; + uint32_t srcPortIdFifo = 0; + uint32_t sequeIdFifo = 0; + struct ptpHdr_t *ptPtpHdr = NULL; + uint32_t matchInfo = 0; + uint8_t srcPortId = 0; + uint64_t cfVal = 0; + + ptPtpHdr = (struct ptpHdr_t *)ptpHdr; + + CHECK_EQUAL_ERR(ptPtpHdr, NULL, -EADDRNOTAVAIL, "tPtpBuff is NULL\n"); + + srcPortId = *(uint8_t *)(ptPtpHdr->srcPortIdentity + SRCPORTID_LEN - 1); /* 只取srcPortIdentity最后一字节值 */ + + for (cfNum = 0; cfNum < tGlobalPtpBuff.cfCount; cfNum++) + { + matchInfo = tGlobalPtpBuff.ptpRegInfo[cfNum].matchInfo; + mssageType = (matchInfo >> MSGTYPE_OFFSET) & 0xf; + srcPortIdFifo = (matchInfo >> SRCPORTID_OFFSET) & 0xf; + sequeIdFifo = htons(matchInfo & 0xffff); + + if((mssageType == msgType) && \ + (srcPortIdFifo == (srcPortId & 0xf)) && \ + (sequeIdFifo == ptPtpHdr->sequenceId)) + { + LOG_DEBUG("read the match info successfully!!!\n"); + LOG_DEBUG("mssageType: %u, srcPortIdFifo: %u, sequeIdFifo: %u\n", mssageType, srcPortIdFifo, sequeIdFifo); + memcpy(&cfVal, &(tGlobalPtpBuff.ptpRegInfo[cfNum].cfVal[0]), CF_SIZE); + cfVal = htonll(cfVal); + memcpy(&(ptPtpHdr->correctionField[0]), &cfVal, CF_SIZE); + + /* 将匹配到的信息从本地buff去除 */ + tGlobalPtpBuff.cfCount--; + if (cfNum == MAX_PTP_REG_INFO_NUM - 1) + { + memset(&(tGlobalPtpBuff.ptpRegInfo[cfNum]), 0, sizeof(struct ptp_reg_info)); + return 0; + } + memcpy(&(tGlobalPtpBuff.ptpRegInfo[cfNum]), &(tGlobalPtpBuff.ptpRegInfo[cfNum + 1]), \ + (MAX_PTP_REG_INFO_NUM - cfNum - 1) * sizeof(struct ptp_reg_info)); + memset(&(tGlobalPtpBuff.ptpRegInfo[MAX_PTP_REG_INFO_NUM - 1]), 0, sizeof(struct ptp_reg_info)); + + return 0; + } + } + + return -1; +} + +#ifdef PTP_DRIVER_INTERFACE_EN +extern int32_t get_event_ts_info(struct zxdh_en_device *en_dev, struct ptp_buff* p_tsInfo, int32_t mac_number); +#endif /* PTP_DRIVER_INTERFACE_EN */ + +/** +* @fn general_encrypt_msg_proc +* @brief 使用两步法，获取、存储和处理不同的ptp加密事件报文的时间戳信息 +* @param msgType ptp事件报文类型 +*/ +int32_t general_encrypt_msg_proc(uint32_t msgType, uint8_t *ptpHdr, struct zxdh_en_device *en_dev) +{ + int32_t num = 0; + int32_t macNum = 0; + int32_t ret = 0; + struct ptpHdr_t *ptPtpHdr = NULL; + struct ptp_buff tempBuff; + + memset(&tempBuff, 0, sizeof(struct ptp_buff)); + ptPtpHdr = (struct ptpHdr_t *)ptpHdr; + + /* 判断报文是否是加密报文 */ + if (!(0x0080 == ((ptPtpHdr->flagField) & 0x0080))) + { + return ret; + } + + macNum = zxdh_pf_macpcs_num_get(en_dev); + if (macNum < 0) + { + LOG_ERR("get mac num %d err, its value should is 0-2!\n", macNum); + return -1; + } + + // LOG_INFO("ptp buff:\n "); + // print_data((uint8_t *)&tGlobalPtpBuff, sizeof(struct ptp_update_buff)); + + /* 1、从本地buff查询和处理时间戳匹配信息，并更新本地buff */ + ret = read_ts_match_info(msgType, ptpHdr); + + /* 2、从本地没匹配到信息，则读取FIFO中信息，将读取到的信息更新到本地，重新匹配 */ + if (ret != 0) + { + // LOG_INFO("cannot read the matchInfo from the BUFF!---------------"); + + #ifdef PTP_DRIVER_INTERFACE_EN + ret = get_event_ts_info(en_dev, &tempBuff, macNum); + CHECK_UNEQUAL_ERR(ret, 0, -EFAULT, "read FIFO form ptpDriver failed!!!"); + #endif /* PTP_DRIVER_INTERFACE_EN */ + + /* 2.1 将读取到到的FIFO信息，添加到本地全局buff */ + if (tempBuff.cfCount > 0) + { + if (tempBuff.cfCount + tGlobalPtpBuff.cfCount < MAX_PTP_REG_INFO_NUM) + { + memcpy(&(tGlobalPtpBuff.ptpRegInfo[tGlobalPtpBuff.cfCount]), + tempBuff.ptpRegInfo, sizeof(struct ptp_reg_info) * tempBuff.cfCount); + + tGlobalPtpBuff.cfCount += tempBuff.cfCount; + // LOG_INFO("tGlobalPtpBuff.cfCount: %u\n", tGlobalPtpBuff.cfCount); + } + else /* 当超过64组时间戳信息时 */ + { + num = tempBuff.cfCount + tGlobalPtpBuff.cfCount - MAX_PTP_REG_INFO_NUM; + + /* 丢弃掉最先存在本地的信息(此信息更大的概率匹配不上) */ + memcpy(&(tGlobalPtpBuff.ptpRegInfo[0]), &(tGlobalPtpBuff.ptpRegInfo[num]), + sizeof(struct ptp_reg_info) * (MAX_PTP_REG_INFO_NUM - num)); + tGlobalPtpBuff.cfCount -= num; + + /* 添加新的信息到本地 */ + memcpy(&(tGlobalPtpBuff.ptpRegInfo[tGlobalPtpBuff.cfCount]), + tempBuff.ptpRegInfo, sizeof(struct ptp_reg_info) * tempBuff.cfCount); + tGlobalPtpBuff.cfCount = MAX_PTP_REG_INFO_NUM; + } + + /* 2.2 在更新后的本地全局buff查询和处理匹配信息，并更新本地buff*/ + ret = read_ts_match_info(msgType, ptpHdr); + CHECK_UNEQUAL_ERR(ret, 0, -EFAULT, "cannot read the matchInfo from the local BUFF!"); + } + } + + // LOG_INFO("ptp buff:\n "); + // print_data((uint8_t *)&tGlobalPtpBuff, sizeof(struct ptp_update_buff)); + + return ret; +} + + +int32_t pkt_proc_type_follow_up(struct sk_buff *skb, \ + struct zxdh_net_hdr *hdr, \ + uint8_t *ptpHdr, \ + struct time_stamps *t5g, \ + struct time_stamps *tsn, \ + uint32_t *thw, \ + struct zxdh_en_device *en_dev) +{ + int32_t ret = 0; + ret = general_encrypt_msg_proc(PTP_MSG_TYPE_SYNC, ptpHdr, en_dev); + + return ret; +} + +int32_t pkt_proc_type_delay_resp(struct sk_buff *skb, \ + struct zxdh_net_hdr *hdr, \ + uint8_t *ptpHdr, \ + struct time_stamps *t5g, \ + struct time_stamps *tsn, \ + uint32_t *thw, \ + struct zxdh_en_device *en_dev) +{ + return 0; +} + +int32_t pkt_rcv_type_delay_resp(struct zxdh_net_hdr_rcv *hdr, \ + uint8_t *ptpHdr, \ + struct time_stamps *t5g, \ + struct time_stamps *tsn, \ + uint32_t *thw, \ + struct skb_shared_info *ptSkbSharedInfo, \ + struct zxdh_en_device *en_dev) +{ + int32_t ret = 0; + ret = general_encrypt_msg_proc(PTP_MSG_TYPE_DELAY_REQ, ptpHdr, en_dev); + + return ret; +} + +int32_t pkt_proc_type_pdelay_resp_follow_up(struct sk_buff *skb, \ + struct zxdh_net_hdr *hdr, \ + uint8_t *ptpHdr, \ + struct time_stamps *t5g, \ + struct time_stamps *tsn, \ + uint32_t *thw, \ + struct zxdh_en_device *en_dev) +{ + int32_t ret = 0; + ret = general_encrypt_msg_proc(PTP_MSG_TYPE_PDELAY_RESP, ptpHdr, en_dev); + + return ret; +} + +int32_t pkt_proc_type_announce(struct sk_buff *skb, \ + struct zxdh_net_hdr *hdr, \ + uint8_t *ptpHdr, \ + struct time_stamps *t5g, \ + struct time_stamps *tsn, \ + uint32_t *thw, \ + struct zxdh_en_device *en_dev) +{ + /* 驱动不做处理 */ + return 0; +} + +int32_t pkt_proc_type_signaling(struct sk_buff *skb, \ + struct zxdh_net_hdr *hdr, \ + uint8_t *ptpHdr, \ + struct time_stamps *t5g, \ + struct time_stamps *tsn, \ + uint32_t *thw, \ + struct zxdh_en_device *en_dev) +{ + /* 驱动不做处理 */ + return 0; +} + +int32_t pkt_proc_type_management(struct sk_buff *skb, \ + struct zxdh_net_hdr *hdr, \ + uint8_t *ptpHdr, \ + struct time_stamps *t5g, \ + struct time_stamps *tsn, \ + uint32_t *thw, \ + struct zxdh_en_device *en_dev) +{ + /* 驱动不做处理 */ + return 0; +} diff --git a/src/net/drivers/net/ethernet/dinghai/en_aux/en_1588_pkt_proc_func.h b/src/net/drivers/net/ethernet/dinghai/en_aux/en_1588_pkt_proc_func.h new file mode 100644 index 0000000..191a887 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_aux/en_1588_pkt_proc_func.h @@ -0,0 +1,233 @@ +/***************************************************************************** +(C) 2023 ZTE Corporation. 版权所有. + +文件名 : en_1588_pkt_proc_func.h +内容摘要 : 不同数据类型包的处理接口实现 +作者/日期 : Limin / 2023.10.12 +版本 : 1.0 +*****************************************************************************/ + +#ifndef _EN_1588_PKT_PROC_FUNC_H_ +#define _EN_1588_PKT_PROC_FUNC_H_ + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +#include "../en_aux.h" +#include "queue.h" + +#define PTP_REG_INFO_NUM 32 +#define MAX_PTP_REG_INFO_NUM 64 + +/* MAC FIFO相关定义 */ +#define MSGTYPE_OFFSET 20 +#define SRCPORTID_OFFSET 16 + +/* PTP报文时间戳处理函数返回值 */ +#define PTP_RET_SUCCESS 0 +#define PTP_RET_TIME_ERR (-1) + +/* CF字段ns位和s位长度 */ +#define CF_DECIMAL_NS_SIZE 2 +#define CF_NS_SIZE 6 +#define CF_SIZE 8 + +/* PTP时间戳长度 */ +#define PTP_TS_5G_LEN 10 +#define PTP_TS_TSN_LEN 10 +#define PTP_REQRECE_TS_LEN 10 + +/* PTP报文后缀相关字段偏移和长度 */ +#define PTPHDR_FREQUENCY_OFFSET 54 +#define PTPHDR_TSI_OFFSET 86 +#define PTPHDR_TSI_TLV_OFFSET 76 +#define PTPHDR_TSI_TLV_OFFSET_TWO 44 +#define PTPHDR_TSI_TLV_LEN 20 +#define ORIGINTIMESTAMP_LEN 10 +#define FOLLOWUP_TLV_LEN 32 +#define TSITLV_LEN 20 +#define SRCPORTID_LEN 10 + +/* 80bit时间戳ns位和s位长度 */ +#define S_SIZE 6 /* 高48位 */ +#define NS_SIZE 4 /* 低32位 */ +#define S_HOLD 1000000000L /* 进位阈值，即低32位达到1e9 */ + +/* pi头中cpu_tx字段，高29位为ns位，低3位为小数ns位 */ +#define CPU_TX_DECIMAL_NS 3 +#define CPU_TX_NS 29 + +typedef struct +{ + uint8_t data[S_SIZE + NS_SIZE]; +} Bits80_t; + +struct time_stamps +{ + uint64_t s; + uint32_t ns; +}; + +struct SkbSharedHwtstamps_t +{ + struct time_stamps ts_5g_t; + struct time_stamps ts_tsn_t; +}; + +struct ptpHdr_t +{ + uint8_t majorType; /* 高4位为majorSdoId，低4位为msgType */ + uint8_t versionPTP; + uint16_t msglen; + uint8_t domainNumber; + uint8_t minorSdoId; + uint16_t flagField; + uint8_t correctionField[CF_SIZE]; /* 高48位为ns位，低16字节为小数ns位 */ + uint32_t msgTypeSpecific; /* 大端 */ + uint8_t srcPortIdentity[SRCPORTID_LEN]; + uint16_t sequenceId; + uint8_t controlField; + uint8_t logMsgInterval; +} __attribute__((packed)); + + +struct ptp_reg_info +{ + uint32_t cfVal[2]; //High寄存器是ns位，Low寄存器的高16bit是ns位，低16bit是ns小数位 + uint32_t matchInfo; //保存的内容是[bit23:0]: {MessageType[23:20], sourcePortIdentity[19:16], sequenceId[15:0]} +}; + +struct ptp_buff +{ + uint32_t cfCount; + struct ptp_reg_info ptpRegInfo[PTP_REG_INFO_NUM]; +}; + +struct ptp_update_buff +{ + uint32_t cfCount; + struct ptp_reg_info ptpRegInfo[MAX_PTP_REG_INFO_NUM]; +}; + +/* PTP报文类型枚举 */ +enum +{ + /* event message types */ + PTP_MSG_TYPE_SYNC = 0, + PTP_MSG_TYPE_DELAY_REQ, + PTP_MSG_TYPE_PDELAY_REQ, + PTP_MSG_TYPE_PDELAY_RESP, + + /* general message types */ + PTP_MSG_TYPE_FOLLOW_UP = 8, + PTP_MSG_TYPE_DELAY_RESP, + PTP_MSG_TYPE_PDELAY_RESP_FOLLOW_UP, + PTP_MSG_TYPE_ANNOUNCE, + PTP_MSG_TYPE_SIGNALING, + PTP_MSG_TYPE_MANAGEMENT +}; + +uint64_t htonll(uint64_t u64_host); + +int32_t pkt_proc_type_sync(struct sk_buff *skb, \ + struct zxdh_net_hdr *hdr, \ + uint8_t *ptpHdr, \ + struct time_stamps *t5g, \ + struct time_stamps *tsn, \ + uint32_t *thw, \ + struct zxdh_en_device *en_dev); + +int32_t pkt_proc_type_delay_req(struct sk_buff *skb, \ + struct zxdh_net_hdr *hdr, \ + uint8_t *ptpHdr, \ + struct time_stamps *t5g, \ + struct time_stamps *tsn, \ + uint32_t *thw, \ + struct zxdh_en_device *en_dev); + +int32_t pkt_proc_type_pdelay_req(struct sk_buff *skb, \ + struct zxdh_net_hdr *hdr, \ + uint8_t *ptpHdr, \ + struct time_stamps *t5g, \ + struct time_stamps *tsn, \ + uint32_t *thw, \ + struct zxdh_en_device *en_dev); + +int32_t pkt_proc_type_pdelay_resp(struct sk_buff *skb, \ + struct zxdh_net_hdr *hdr, \ + uint8_t *ptpHdr, \ + struct time_stamps *t5g, \ + struct time_stamps *tsn, \ + uint32_t *thw, \ + struct zxdh_en_device *en_dev); + +int32_t pkt_proc_type_follow_up(struct sk_buff *skb, \ + struct zxdh_net_hdr *hdr, \ + uint8_t *ptpHdr, \ + struct time_stamps *t5g, \ + struct time_stamps *tsn, \ + uint32_t *thw, \ + struct zxdh_en_device *en_dev); + +int32_t pkt_proc_type_delay_resp(struct sk_buff *skb, \ + struct zxdh_net_hdr *hdr, \ + uint8_t *ptpHdr, \ + struct time_stamps *t5g, \ + struct time_stamps *tsn, \ + uint32_t *thw, \ + struct zxdh_en_device *en_dev); + +int32_t pkt_proc_type_pdelay_resp_follow_up(struct sk_buff *skb, \ + struct zxdh_net_hdr *hdr, \ + uint8_t *ptpHdr, \ + struct time_stamps *t5g, \ + struct time_stamps *tsn, \ + uint32_t *thw, \ + struct zxdh_en_device *en_dev); + +int32_t pkt_proc_type_announce(struct sk_buff *skb, \ + struct zxdh_net_hdr *hdr, \ + uint8_t *ptpHdr, \ + struct time_stamps *t5g, \ + struct time_stamps *tsn, \ + uint32_t *thw, \ + struct zxdh_en_device *en_dev); + +int32_t pkt_proc_type_signaling(struct sk_buff *skb, \ + struct zxdh_net_hdr *hdr, \ + uint8_t *ptpHdr, \ + struct time_stamps *t5g, \ + struct time_stamps *tsn, \ + uint32_t *thw, \ + struct zxdh_en_device *en_dev); + +int32_t pkt_proc_type_management(struct sk_buff *skb, \ + struct zxdh_net_hdr *hdr, \ + uint8_t *ptpHdr, \ + struct time_stamps *t5g, \ + struct time_stamps *tsn, \ + uint32_t *thw, \ + struct zxdh_en_device *en_dev); + +int32_t pkt_rcv_type_event(struct zxdh_net_hdr_rcv *hdr, \ + uint8_t *ptpHdr, \ + struct time_stamps *t5g, \ + struct time_stamps *tsn, \ + uint32_t *thw, \ + struct skb_shared_info *ptSkbSharedInfo, + struct zxdh_en_device *en_dev); + +int32_t pkt_rcv_type_delay_resp(struct zxdh_net_hdr_rcv *hdr, \ + uint8_t *ptpHdr, \ + struct time_stamps *t5g, \ + struct time_stamps *tsn, \ + uint32_t *thw, \ + struct skb_shared_info *ptSkbSharedInfo, + struct zxdh_en_device *en_dev); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* _EN_1588_PKT_PROC_FUNC_H_ */ \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_aux/en_cmd.c b/src/net/drivers/net/ethernet/dinghai/en_aux/en_cmd.c new file mode 100644 index 0000000..c80e402 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_aux/en_cmd.c @@ -0,0 +1,1560 @@ +#include +#include +#include +#include +#include +#include +#include + +#include +#include "../en_aux.h" +#include "../en_np/table/include/dpp_tbl_api.h" +#include "../msg_common.h" +#include "en_cmd.h" + +static int32_t get_common_table_msg(struct zxdh_en_device *en_dev, uint16_t pcie_id, uint8_t field, void *ack); +static int32_t write_queue_index_to_message(struct zxdh_en_device *en_dev, uint32_t queue_nums, + uint32_t field, uint16_t *bytes, uint16_t *data) +{ + uint32_t ix = 0; + uint16_t old_queue_nums = 0; + int32_t ret = 0; + union zxdh_msg msg = {0}; + + if (OP_CODE_DATA_CHAN == field) + { + *bytes = (uint16_t)((queue_nums + 1) * ZXDH_QS_PAIRS); + data[0] = (uint16_t)queue_nums; + + for (ix = 0; ix < queue_nums; ix = ix + ZXDH_QS_PAIRS) + { + data[ix + 1] = en_dev->rq[ix / ZXDH_QS_PAIRS].vq->phy_index; + data[ix + 2] = en_dev->sq[ix / ZXDH_QS_PAIRS].vq->phy_index; + } + + if (en_dev->ops->is_bond(en_dev->parent)) + { + ret = get_common_table_msg(en_dev, en_dev->pcie_id, OP_CODE_DATA_CHAN, &msg); + if (ret != 0) + { + LOG_ERR("Failed to get data queue: %d\n", ret); + return ret; + } + + old_queue_nums = msg.reps.cmn_vq_msg.queue_nums; + if (old_queue_nums == 0) + { + return 0; + } + + if ((old_queue_nums + queue_nums) > 256) + { + LOG_ERR("Exceeded the maximum number of queues, old_queue_nums(%d)\n", old_queue_nums); + return -1; + } + + *bytes = (uint16_t)((queue_nums + old_queue_nums + 1) * ZXDH_QS_PAIRS); + data[0] = (uint16_t)(queue_nums + old_queue_nums); + memcpy(data + queue_nums + 1, msg.reps.cmn_vq_msg.phy_qidx, old_queue_nums * ZXDH_QS_PAIRS); + + for (ix = 1; ix <= (queue_nums + old_queue_nums); ix++) + { + LOG_INFO("vq phy_qid: %d ", data[ix]); + } + } + } +#ifdef ZXDH_MSGQ + else if (OP_CODE_MSGQ_CHAN == field) + { + *bytes = (uint16_t)(queue_nums * ZXDH_QS_PAIRS); + data[0] = en_dev->rq[en_dev->curr_queue_pairs].vq->phy_index; + data[1] = en_dev->sq[en_dev->curr_queue_pairs].vq->phy_index; + } +#endif + + return 0; +} + +static int32_t cmd_tbl_messgae_to_riscv_send(struct zxdh_en_device *en_dev, void *payload, uint32_t pld_len) +{ + int32_t ret = 0; + struct cmd_hdr_recv *hdr_recv; + struct cmd_tbl_ack cmd_tbl_ack = {0}; + + ret = en_dev->ops->msg_send_cmd(en_dev->parent, MODULE_TBL, payload, &cmd_tbl_ack, true); + if (0 != ret) + { + LOG_ERR("en_dev->ops->msg_send_cmd failed\n"); + goto out; + } + + hdr_recv =(struct cmd_hdr_recv*)&cmd_tbl_ack; + if (hdr_recv->check != OP_CODE_TBL_STAT) + { + LOG_ERR("tbl init message recv check failed\n"); + ret = -1; + } +out: + return ret; +} + +static int32_t cmd_common_tbl_init(struct zxdh_en_device *en_dev, uint32_t queue_nums, uint32_t field) +{ + int32_t ret = 0; + union zxdh_msg msg = {0}; + + if ((2 * ZXDH_MAX_PAIRS_NUM) < queue_nums) + { + LOG_ERR("queue pairs %u out of range\n", queue_nums); + return -ENOMEM; + } + + msg.payload.hdr_to_cmn.field = field; + msg.payload.hdr_to_cmn.type = OP_CODE_WRITE; + msg.payload.hdr_to_cmn.pcie_id = en_dev->pcie_id; + ret = write_queue_index_to_message(en_dev, queue_nums, field, \ + &msg.payload.hdr_to_cmn.write_bytes, msg.payload.cmn_tbl_msg); + if (0 != ret) + { + LOG_ERR("write_queue_index_to_message failed, ret: %d\n", ret); + return ret; + } + + // 执行message send + ret = cmd_tbl_messgae_to_riscv_send(en_dev, &msg, MSG_STRUCT_HD_LEN + msg.payload.hdr_to_cmn.write_bytes); + if (0 != ret) + { + LOG_ERR("zxdh_bar_chan_sync_msg_send failed, ret: %d\n", ret); + } + + return ret; +} + +int32_t zxdh_common_tbl_init(struct net_device *netdev) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + int32_t ret = 0; + +#ifdef ZXDH_MSGQ + NEED_MSGQ(en_dev) + { + ret = cmd_common_tbl_init(en_dev, ZXDH_QS_PAIRS, OP_CODE_MSGQ_CHAN); + if (0 != ret) + { + LOG_ERR("field msgq message failed\n"); + return -1; + } + } +#endif + + ret = cmd_common_tbl_init(en_dev, en_dev->curr_queue_pairs * ZXDH_QS_PAIRS, OP_CODE_DATA_CHAN); + if (0 != ret) + { + LOG_ERR("field data message failed\n"); + return -1; + } + + return 0; +} + +int32_t zxdh_send_command_to_specify(struct zxdh_en_device *en_dev, uint16_t module_id, void *msg, void *ack) +{ + struct dh_core_dev *dh_dev = en_dev->parent; + + return en_dev->ops->msg_send_cmd(dh_dev, module_id, msg, ack, true); +} + +static int32_t get_common_table_msg(struct zxdh_en_device *en_dev, uint16_t pcie_id, \ + uint8_t field, void *ack) +{ + union zxdh_msg msg = {0}; + + msg.payload.hdr_to_cmn.type = RISC_TYPE_READ; + msg.payload.hdr_to_cmn.field = field; + msg.payload.hdr_to_cmn.pcie_id = pcie_id; + msg.payload.hdr_to_cmn.write_bytes = 0; + + return zxdh_send_command_to_specify(en_dev, MODULE_TBL, &msg, ack); +} + +int32_t zxdh_hash_id_get(struct zxdh_en_device *en_dev) +{ + int32_t ret = 0; + union zxdh_msg msg = {0}; + + ret = get_common_table_msg(en_dev, en_dev->pcie_id, RISC_FIELD_HASHID_CHANNEL, &msg); + if(ret != 0) + { + LOG_ERR("get own hash_id failed: %d\n", ret); + return ret; + } + + en_dev->hash_search_idx = msg.reps.cmn_recv_msg.value; + LOG_DEBUG("hash_id: %u\n", en_dev->hash_search_idx); + if (en_dev->hash_search_idx > ZXDH_MAX_HASH_INDEX) + { + LOG_ERR("hash_id is invalid value: %u\n", en_dev->hash_search_idx); + return -EINVAL; + } + if (en_dev->hash_search_idx == ZXDH_MAX_HASH_INDEX) //TODO:if should be delete + { + en_dev->hash_search_idx = 1; + } + + return ret; +} + +int32_t zxdh_phyport_get(struct zxdh_en_device *en_dev) +{ + int32_t ret = 0; + union zxdh_msg msg = {0}; + + ret = get_common_table_msg(en_dev, en_dev->pcie_id, RISC_FIELD_PHYPORT_CHANNEL, &msg); + if(ret != 0) + { + LOG_ERR("get own phyport failed: %d\n", ret); + return ret; + } + + en_dev->phy_port = msg.reps.cmn_recv_msg.value; + if (en_dev->phy_port == INVALID_PHY_PORT) + { + LOG_ERR("get phy_port failed\n"); + return -EINVAL; + } + en_dev->ops->set_pf_phy_port(en_dev->parent, en_dev->phy_port); + LOG_DEBUG("phy_port: %u\n", en_dev->phy_port); + + return ret; +} + +int32_t zxdh_panel_id_get(struct zxdh_en_device *en_dev) +{ + int32_t ret = 0; + union zxdh_msg msg = {0}; + + ret = get_common_table_msg(en_dev, en_dev->pcie_id, RISC_FIELD_PANEL_ID, &msg); + if(ret != 0) + { + LOG_ERR("get own phyport failed: %d\n", ret); + return ret; + } + + en_dev->panel_id = msg.reps.cmn_recv_msg.value; + if (en_dev->panel_id > MAX_PANEL_ID) + { + LOG_ERR("get panel_id failed, panel_id: %u\n", en_dev->panel_id); + return -EINVAL; + } + LOG_DEBUG("panel_id: %u\n", en_dev->panel_id); + + return ret; +} + +int32_t zxdh_pf_macpcs_num_get(struct zxdh_en_device *en_dev) +{ + int32_t phy_port = 0; + int32_t mac_num = 0; //0-2 + + phy_port = en_dev->phy_port; + + if (phy_port < 4) + { + mac_num = 0; + } + else if (phy_port < 8) + { + mac_num = 1; + } + else if (phy_port < 10) + { + mac_num = 2; + } + else + { + LOG_ERR("phy_port(%d) err, not in 0-9!!\n", phy_port); + mac_num = -1; + return mac_num; + } + + LOG_DEBUG("mac_num: %d\n", mac_num); + return mac_num; +} + +int32_t zxdh_pf_link_state_get(struct zxdh_en_device *en_dev) +{ + int32_t ret = 0; + union zxdh_msg msg = {0}; + + msg.payload.hdr_to_agt.op_code = AGENT_MAC_LINK_INFO_GET; + msg.payload.hdr_to_agt.phyport = en_dev->phy_port; + ret = zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &msg); + if (ret != 0) + { + LOG_ERR("zxdh_pf_link_state_get failed: %d\n", ret); + return ret; + } + en_dev->ops->set_pf_link_up(en_dev->parent, msg.reps.mac_set_msg.link_state); + LOG_INFO("link_up is %s\n", msg.reps.mac_set_msg.link_state ? "true" : "false"); + if(msg.reps.mac_set_msg.link_state) + { + netif_carrier_on(en_dev->netdev); + } + else + { + netif_carrier_off(en_dev->netdev); + } + return ret; +} + +int32_t zxdh_lldp_enable_set(struct zxdh_en_device *en_dev,bool lldp_enable) +{ + union zxdh_msg msg = {0}; + + msg.payload.hdr_to_agt.op_code = AGENT_DEBUG_LLDP_ENABLE_SET; + msg.payload.hdr_to_agt.port_id = en_dev->panel_id; + + if (en_dev->ops->is_bond(en_dev->parent)) + { + msg.payload.hdr_to_agt.port_id = en_dev->pannel_id; + } + msg.payload.lldp_msg.lldp_enable = lldp_enable; + + return zxdh_send_command_to_specify(en_dev, MODULE_DEBUG, &msg, &msg); +} + +int32_t zxdh_sshd_enable_set(struct zxdh_en_device *en_dev, bool sshd_enable) +{ + union zxdh_msg msg = {0}; + + if (sshd_enable) + { + msg.payload.hdr_to_agt.op_code = AGENT_SSHD_START; + } + else + { + msg.payload.hdr_to_agt.op_code = AGENT_SSHD_STOP; + } + + LOG_INFO("event id is %d\n", MODULE_LOGIN_CTRL); + return zxdh_send_command_to_specify(en_dev, MODULE_LOGIN_CTRL, &msg, &msg); +} + +int32_t zxdh_lldp_enable_get(struct zxdh_en_device *en_dev, uint32_t *lldp_enable) +{ + int32_t ret = 0; + union zxdh_msg msg = {0}; + + msg.payload.hdr_to_agt.op_code = AGENT_DEBUG_LLDP_ENABLE_GET; + msg.payload.hdr_to_agt.port_id = en_dev->panel_id; + + if (en_dev->ops->is_bond(en_dev->parent)) + { + msg.payload.hdr_to_agt.port_id = en_dev->pannel_id; + } + + ret = zxdh_send_command_to_specify(en_dev, MODULE_DEBUG, &msg, &msg); + if (ret != 0) + { + LOG_ERR("zxdh_lldp_enable_get failed: %d\n", ret); + return ret; + } + + *lldp_enable = (uint32_t)(msg.reps.debug_lldp_msg.lldp_status); + + return ret; +} + +int32_t zxdh_riscv_os_type_get(struct zxdh_en_device *en_dev, uint8_t *is_zios) +{ + int32_t ret = 0; + union zxdh_msg msg = {0}; + msg.payload.hdr_to_agt.op_code = AGENT_OS_TYPE_GET; + + ret = zxdh_send_command_to_specify(en_dev, MODULE_LOGIN_CTRL, &msg, &msg); + if (ret != 0) + { + LOG_ERR("get bus from riscv failed: %d\n", ret); + return ret; + } + + *is_zios = msg.reps.os_type_msg.is_zios; + + return ret; +} + +int32_t zxdh_ep0_bus_get(struct zxdh_en_device *en_dev, uint8_t *bus_info) +{ + int32_t ret = 0; + union zxdh_msg msg = {0}; + + msg.payload.hdr_to_agt.op_code = AGENT_EP0_BUS_GET; + + ret = zxdh_send_command_to_specify(en_dev, MODULE_LOGIN_CTRL, &msg, &msg); + if (ret != 0) + { + LOG_ERR("get bus from riscv failed: %d\n", ret); + return ret; + } + + *bus_info = msg.reps.ep0_bus_msg.bus_info; + + return ret; +} + +int8_t zxdh_debug_ip_get(struct zxdh_en_device *en_dev, int8_t *ip) +{ + int32_t ret = 0; + uint8_t bus_info = 0; + int8_t ip_address[20] = {0}; + int8_t bus_str[5]= {0}; + + sprintf(ip_address, "26.20.5"); + + ret = zxdh_ep0_bus_get(en_dev, &bus_info); + if (ret != 0) + { + LOG_ERR("zxdh_ep0_bus_get failed: %d\n", ret); + return ret; + } + + sprintf(bus_str, ".%d", bus_info); + strcat(ip_address, bus_str); /* 将bus号添加到IP地址字符串后面 */ + strcpy(ip, ip_address); + + LOG_INFO("DEBUG IP is: %s\n", ip_address); + + return ret; +} + +#define FLASH_OPEN_FW +int32_t zxdh_en_firmware_version_get(struct zxdh_en_device *en_dev, uint8_t *fw_version, uint8_t *fw_version_len) +{ +#ifdef FLASH_OPEN_FW + int32_t ret = 0; + union zxdh_msg msg = {0}; + + msg.payload.hdr_to_agt.op_code = AGENT_FLASH_FIR_VERSION_GET; + + ret = zxdh_send_command_to_specify(en_dev, MODULE_FLASH, &msg, &msg); + if (ret != 0) + { + LOG_ERR("zxdh_send_command_to_specify failed: %d\n", ret); + return ret; + } + + memcpy(fw_version, msg.reps.flash_msg.firmware_version, FW_VERSION_LEN); + *fw_version_len = FW_VERSION_LEN; +#else + uint8_t fw_version_test[] = "V2.24.10.01B4"; + + memcpy(fw_version, fw_version_test, sizeof(fw_version_test)); + *fw_version_len = sizeof(fw_version_test); +#endif + return 0; +} + +int32_t do_get_vport_stats(struct zxdh_en_device *en_dev, uint8_t np_mode, + struct zxdh_en_vport_stats *vport_stats) +{ + union zxdh_msg msg = {0}; + uint64_t rx_broadcast_cnt = 0; + uint64_t tx_broadcast_cnt = 0; + uint64_t rx_mtu_drop_pkts_cnt = 0; + uint64_t tx_mtu_drop_pkts_cnt = 0; + uint64_t rx_mtu_drop_bytes_cnt = 0; + uint64_t tx_mtu_drop_bytes_cnt = 0; + uint64_t rx_plcr_drop_pkts_cnt = 0; + uint64_t tx_plcr_drop_pkts_cnt = 0; + uint64_t rx_plcr_drop_bytes_cnt = 0; + uint64_t tx_plcr_drop_bytes_cnt = 0; + uint32_t vf_id = GET_VFID(en_dev->vport); + int32_t err = 0; + DPP_PF_INFO_T pf_info = {0}; + + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + + msg.payload.hdr_to_agt.op_code = AGENT_VQM_DEVICE_STATS_GET; + msg.payload.hdr_to_agt.vf_id = vf_id; + err = zxdh_send_command_to_specify(en_dev, MODULE_VQM, &msg, &msg); + if (err != 0) + { + LOG_ERR("zxdh_vport_stats_get failed, err: %d\n", err); + return err; + } + memcpy(&(vport_stats->vqm_stats), &(msg.reps.stats_msg), sizeof(vport_stats->vqm_stats)); + + memset(&msg, 0, sizeof(union zxdh_msg)); + + if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_VF) + { + msg.payload.hdr.op_code = ZXDH_GET_NP_STATS; + msg.payload.hdr.vport = en_dev->vport; + msg.payload.hdr.vf_id = vf_id; + msg.payload.np_stats_get_msg.clear_mode = np_mode; + err = zxdh_send_command_to_specify(en_dev, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg); + if(err != 0) + { + LOG_ERR("zxdh_send_command_to_pf failed: %d\n", err); + return err; + } + rx_broadcast_cnt = msg.reps.np_stats_msg.np_rx_broadcast; + tx_broadcast_cnt = msg.reps.np_stats_msg.np_tx_broadcast; + rx_mtu_drop_pkts_cnt = msg.reps.np_stats_msg.np_rx_mtu_drop_pkts; + tx_mtu_drop_pkts_cnt = msg.reps.np_stats_msg.np_tx_mtu_drop_pkts; + rx_mtu_drop_bytes_cnt = msg.reps.np_stats_msg.np_rx_mtu_drop_bytes; + tx_mtu_drop_bytes_cnt = msg.reps.np_stats_msg.np_tx_mtu_drop_bytes; + rx_plcr_drop_pkts_cnt = msg.reps.np_stats_msg.np_rx_plcr_drop_pkts; + tx_plcr_drop_pkts_cnt = msg.reps.np_stats_msg.np_tx_plcr_drop_pkts; + rx_plcr_drop_bytes_cnt = msg.reps.np_stats_msg.np_rx_plcr_drop_bytes; + tx_plcr_drop_bytes_cnt = msg.reps.np_stats_msg.np_tx_plcr_drop_bytes; + } + else + { + dpp_stat_port_bc_packet_rx_cnt_get(&pf_info, vf_id, np_mode, &rx_broadcast_cnt); + dpp_stat_port_bc_packet_tx_cnt_get(&pf_info, vf_id, np_mode, &tx_broadcast_cnt); + dpp_stat_MTU_packet_msg_rx_cnt_get(&pf_info, vf_id, np_mode, &rx_mtu_drop_bytes_cnt, &rx_mtu_drop_pkts_cnt); + dpp_stat_MTU_packet_msg_tx_cnt_get(&pf_info, vf_id, np_mode, &tx_mtu_drop_bytes_cnt, &tx_mtu_drop_pkts_cnt); + dpp_stat_plcr_packet_drop_rx_cnt_get(&pf_info, vf_id, np_mode, &rx_plcr_drop_bytes_cnt, &rx_plcr_drop_pkts_cnt); + dpp_stat_plcr_packet_drop_tx_cnt_get(&pf_info, vf_id, np_mode, &tx_plcr_drop_bytes_cnt, &tx_plcr_drop_pkts_cnt); + } + vport_stats->np_stats.rx_vport_broadcast_packets = rx_broadcast_cnt; + vport_stats->np_stats.tx_vport_broadcast_packets = tx_broadcast_cnt; + vport_stats->np_stats.rx_vport_mtu_drop_packets = rx_mtu_drop_pkts_cnt; + vport_stats->np_stats.tx_vport_mtu_drop_packets = tx_mtu_drop_pkts_cnt; + vport_stats->np_stats.rx_vport_mtu_drop_bytes = rx_mtu_drop_bytes_cnt; + vport_stats->np_stats.tx_vport_mtu_drop_bytes = tx_mtu_drop_bytes_cnt; + vport_stats->np_stats.rx_vport_plcr_drop_packets = rx_plcr_drop_pkts_cnt; + vport_stats->np_stats.tx_vport_plcr_drop_packets = tx_plcr_drop_pkts_cnt; + vport_stats->np_stats.rx_vport_plcr_drop_bytes = rx_plcr_drop_bytes_cnt; + vport_stats->np_stats.tx_vport_plcr_drop_bytes = tx_plcr_drop_bytes_cnt; + + return err; +} + +int32_t zxdh_en_vport_pre_stats_get(struct zxdh_en_device *en_dev) +{ + int32_t err = 0; + struct zxdh_en_vport_stats *vport_stats = &en_dev->pre_stats; + + err = do_get_vport_stats(en_dev, NP_GET_PKT_CNT, vport_stats); + if(err != 0) + { + LOG_ERR("zxdh_en_vport_pre_stat_get failed\n"); + } + return err; +} + +int32_t zxdh_vport_stats_get(struct zxdh_en_device *en_dev) +{ + int32_t err = 0; + struct zxdh_en_vport_stats *vport_stats = &en_dev->hw_stats.vport_stats; + + err = do_get_vport_stats(en_dev, NP_GET_PKT_CNT, vport_stats); + if(err != 0) + { + LOG_ERR("zxdh_vport_stats_get failed\n"); + return err; + } + + vport_stats->vqm_stats.rx_vport_packets -= en_dev->pre_stats.vqm_stats.rx_vport_packets; + vport_stats->vqm_stats.tx_vport_packets -= en_dev->pre_stats.vqm_stats.tx_vport_packets; + vport_stats->vqm_stats.rx_vport_bytes -= en_dev->pre_stats.vqm_stats.rx_vport_bytes; + vport_stats->vqm_stats.tx_vport_bytes -= en_dev->pre_stats.vqm_stats.tx_vport_bytes; + vport_stats->vqm_stats.rx_vport_dropped -= en_dev->pre_stats.vqm_stats.rx_vport_dropped; + vport_stats->np_stats.rx_vport_broadcast_packets -= en_dev->pre_stats.np_stats.rx_vport_broadcast_packets; + vport_stats->np_stats.tx_vport_broadcast_packets -= en_dev->pre_stats.np_stats.tx_vport_broadcast_packets; + vport_stats->np_stats.rx_vport_mtu_drop_packets -= en_dev->pre_stats.np_stats.rx_vport_mtu_drop_packets; + vport_stats->np_stats.tx_vport_mtu_drop_packets -= en_dev->pre_stats.np_stats.tx_vport_mtu_drop_packets; + vport_stats->np_stats.rx_vport_mtu_drop_bytes -= en_dev->pre_stats.np_stats.rx_vport_mtu_drop_bytes; + vport_stats->np_stats.tx_vport_mtu_drop_bytes -= en_dev->pre_stats.np_stats.tx_vport_mtu_drop_bytes; + vport_stats->np_stats.rx_vport_plcr_drop_packets -= en_dev->pre_stats.np_stats.rx_vport_plcr_drop_packets; + vport_stats->np_stats.tx_vport_plcr_drop_packets -= en_dev->pre_stats.np_stats.tx_vport_plcr_drop_packets; + vport_stats->np_stats.rx_vport_plcr_drop_bytes -= en_dev->pre_stats.np_stats.rx_vport_plcr_drop_bytes; + vport_stats->np_stats.tx_vport_plcr_drop_bytes -= en_dev->pre_stats.np_stats.tx_vport_plcr_drop_bytes; + return err; +} + +int32_t zxdh_mac_stats_get(struct zxdh_en_device *en_dev) +{ + union zxdh_msg msg = {0}; + int32_t err = 0; + + msg.payload.hdr_to_agt.op_code = AGENT_MAC_STATS_GET; + msg.payload.hdr_to_agt.phyport = en_dev->phy_port; + err = zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &msg); + if (err != 0) + { + LOG_ERR("zxdh_mac_stats_get failed, err: %d\n", err); + return err; + } + + if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_VF) + { + memset(&msg.reps.stats_msg, 0, sizeof(msg.reps.stats_msg)); + } + memcpy(&(en_dev->hw_stats.phy_stats), &msg.reps.stats_msg, sizeof(en_dev->hw_stats.phy_stats)); + + return err; +} + +int32_t zxdh_mac_stats_clear(struct zxdh_en_device *en_dev) +{ + union zxdh_msg msg = {0}; + int32_t err = 0; + + msg.payload.hdr_to_agt.op_code = AGENT_MAC_STATS_CLEAR; + msg.payload.hdr_to_agt.phyport = en_dev->phy_port; + err = zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &msg); + if (err != 0) + { + LOG_ERR("zxdh_mac_stats_clear failed, err: %d\n", err); + return err; + } + + return err; +} + +int32_t zxdh_en_phyport_init(struct zxdh_en_device *en_dev) +{ + union zxdh_msg msg = {0}; + int32_t err = 0; + struct link_info_struct link_info_val = {0}; + + msg.payload.hdr_to_agt.op_code = AGENT_MAC_PHYPORT_INIT; + msg.payload.hdr_to_agt.phyport = en_dev->phy_port; + if (en_dev->ops->is_upf(en_dev->parent)) + { + msg.payload.hdr_to_agt.phyport = 0; + msg.payload.hdr_to_agt.is_upf = 1; + //TODO 确定upf设备link状态获取方案 + en_dev->link_up = true; + en_dev->speed = SPEED_100000; + en_dev->ops->set_pf_link_up(en_dev->parent, en_dev->link_up); + netif_carrier_on(en_dev->netdev); + } + + err = zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &msg); + if (err != 0) + { + LOG_ERR("zxdh_send_command_to_riscv_mac failed, err: %d\n", err); + return err; + } + + en_dev->supported_speed_modes = msg.reps.mac_set_msg.speed_modes; + en_dev->advertising_speed_modes = msg.reps.mac_set_msg.speed_modes; + + link_info_val.speed = en_dev->speed; + link_info_val.autoneg_enable = en_dev->autoneg_enable; + link_info_val.supported_speed_modes = en_dev->supported_speed_modes; + link_info_val.advertising_speed_modes = en_dev->advertising_speed_modes; + link_info_val.duplex = en_dev->duplex; + en_dev->ops->update_pf_link_info(en_dev->parent, &link_info_val); + + return err; +} + +int32_t zxdh_en_autoneg_set(struct zxdh_en_device *en_dev, uint8_t enable, uint32_t speed_modes) +{ + union zxdh_msg msg = {0}; + + msg.payload.hdr_to_agt.op_code = AGENT_MAC_AUTONEG_SET; + msg.payload.hdr_to_agt.phyport = en_dev->phy_port; + msg.payload.mac_set_msg.autoneg = enable; + msg.payload.mac_set_msg.speed_modes = speed_modes; + + return zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &msg); +} + +int32_t zxdh_en_fec_mode_set(struct zxdh_en_device *en_dev, uint32_t fec_cfg) +{ + union zxdh_msg msg = {0}; + + msg.payload.hdr_to_agt.op_code = AGENT_MAC_FEC_MODE_SET; + msg.payload.hdr_to_agt.phyport = en_dev->phy_port; + msg.payload.mac_fec_mode_msg.fec_cfg = fec_cfg; + + return zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &msg); +} + +int32_t zxdh_en_fec_mode_get(struct zxdh_en_device *en_dev, uint32_t *fec_cap, uint32_t *fec_cfg, uint32_t *fec_active) +{ + union zxdh_msg msg = {0}; + int32_t err = 0; + + msg.payload.hdr_to_agt.op_code = AGENT_MAC_FEC_MODE_GET; + msg.payload.hdr_to_agt.phyport = en_dev->phy_port; + + err = zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &msg); + if (err != 0) + { + LOG_ERR("zxdh_send_command_to_riscv_mac failed, err: %d\n", err); + return err; + } + + if(fec_cap) + *fec_cap = msg.reps.mac_fec_mode_msg.fec_cap; + if(fec_cfg) + *fec_cfg = msg.reps.mac_fec_mode_msg.fec_cfg; + if(fec_active) + *fec_active = msg.reps.mac_fec_mode_msg.fec_link; + + return err; +} + +int32_t zxdh_en_fc_mode_set(struct zxdh_en_device *en_dev, uint32_t fc_mode) +{ + union zxdh_msg msg = {0}; + + msg.payload.hdr_to_agt.op_code = AGENT_MAC_FC_MODE_SET; + msg.payload.hdr_to_agt.phyport = en_dev->phy_port; + msg.payload.mac_fc_mode_msg.fc_mode = fc_mode; + + return zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &msg); +} + +int32_t zxdh_en_fc_mode_get(struct zxdh_en_device *en_dev, uint32_t *fc_mode) +{ + union zxdh_msg msg = {0}; + int32_t err = 0; + + msg.payload.hdr_to_agt.op_code = AGENT_MAC_FC_MODE_GET; + msg.payload.hdr_to_agt.phyport = en_dev->phy_port; + + err = zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &msg); + if (err != 0) + { + LOG_ERR("zxdh_send_command_to_riscv_mac failed, err: %d\n", err); + return err; + } + + if(fc_mode) + *fc_mode = msg.reps.mac_fc_mode_msg.fc_mode; + + return err; +} + +uint32_t zxdh_en_module_eeprom_read(struct zxdh_en_device *en_dev, struct zxdh_en_module_eeprom_param *query, uint8_t *data) +{ + union zxdh_msg msg = {0}; + int32_t err = 0; + + msg.payload.hdr_to_agt.op_code = AGENT_MAC_MODULE_EEPROM_READ; + msg.payload.hdr_to_agt.phyport = en_dev->phy_port; + msg.payload.module_eeprom_msg.i2c_addr = query->i2c_addr; + msg.payload.module_eeprom_msg.bank = query->bank; + msg.payload.module_eeprom_msg.page = query->page; + msg.payload.module_eeprom_msg.offset = query->offset; + msg.payload.module_eeprom_msg.length = query->length; + + err = zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &msg); + if (err != 0) + { + LOG_ERR("zxdh_send_command_to_riscv_mac failed, err: %d\n", err); + return 0; + } + + if(data) + memcpy(data, msg.reps.module_eeprom_msg.data, msg.reps.module_eeprom_msg.length); + + return msg.reps.module_eeprom_msg.length; +} + +int32_t zxdh_vf_1588_call_np_interface(struct zxdh_en_device *en_dev) +{ + int32_t ret = 0; + union zxdh_msg msg = {0}; + + msg.payload.hdr.op_code = ZXDH_VF_1588_CALL_NP; + msg.payload.hdr.vport = en_dev->vport; + msg.payload.hdr.pcie_id = en_dev->pcie_id; + msg.payload.vf_1588_call_np.vfid = VQM_VFID(msg.payload.hdr.vport); + msg.payload.vf_1588_call_np.call_np_interface_num = en_dev->vf_1588_call_np_num; + msg.payload.vf_1588_call_np.ptp_tc_enable_opt = en_dev->ptp_tc_enable_opt; + ret = zxdh_send_command_to_specify(en_dev, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg); + if(ret != 0) + { + LOG_ERR("zxdh_send_command_to_pf failed: %d\n", ret); + return ret; + } + + return ret; +} + +int32_t zxdh_vf_port_create(struct zxdh_en_device *en_dev) +{ + int32_t ret = 0; + union zxdh_msg msg = {0}; + uint8_t link_up = 0; + bool is_upf = false; + + if (en_dev->ops->is_upf(en_dev->parent)) + { + is_upf = true; + } + + msg.payload.hdr.op_code = ZXDH_VF_PORT_INIT; + msg.payload.hdr.vport = en_dev->vport; + msg.payload.hdr.pcie_id = en_dev->pcie_id; + msg.payload.vf_init_msg.base_qid = en_dev->phy_index[0]; + msg.payload.vf_init_msg.hash_search_idx = en_dev->hash_search_idx; + msg.payload.vf_init_msg.rss_enable = 1; + msg.payload.vf_init_msg.is_upf = is_upf; + + ret = zxdh_send_command_to_specify(en_dev, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg); + if(ret != 0) + { + LOG_ERR("zxdh_send_command_to_pf failed: %d\n", ret); + return ret; + } + + if (is_upf) + { + en_dev->link_up = msg.reps.vf_init_msg.link_up; + } + else + { + en_dev->ops->get_link_info_from_vqm(en_dev->parent, &link_up); + en_dev->link_up = link_up; + LOG_INFO("vf read link_up: %d from vqm\n", link_up); + } + + ether_addr_copy(en_dev->netdev->dev_addr, msg.reps.vf_init_msg.mac_addr); + en_dev->speed = msg.reps.vf_init_msg.speed; + en_dev->autoneg_enable = msg.reps.vf_init_msg.autoneg_enable; + en_dev->supported_speed_modes = msg.reps.vf_init_msg.sup_link_modes; + en_dev->advertising_speed_modes = msg.reps.vf_init_msg.adv_link_modes; + en_dev->duplex = msg.reps.vf_init_msg.duplex; + + if (!is_upf) + { + en_dev->phy_port = msg.reps.vf_init_msg.phy_port; + en_dev->ops->set_pf_phy_port(en_dev->parent, en_dev->phy_port); + } + + if (en_dev->link_up) + { + en_dev->ops->set_pf_link_up(en_dev->parent, TRUE); + netif_carrier_on(en_dev->netdev); + } + else + { + en_dev->ops->set_pf_link_up(en_dev->parent, FALSE); + netif_carrier_off(en_dev->netdev); + } + return ret; +} + +int32_t zxdh_vf_port_delete(struct zxdh_en_device *en_dev) +{ + union zxdh_msg msg = {0}; + + //dpp_np_uninit + msg.payload.hdr.op_code = ZXDH_VF_PORT_UNINIT; + msg.payload.hdr.vport = en_dev->vport; + msg.payload.hdr.pcie_id = en_dev->pcie_id; + return zxdh_send_command_to_specify(en_dev, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg); +} + +int32_t zxdh_vf_dpp_add_mac(struct zxdh_en_device *en_dev, const uint8_t *dev_addr, uint8_t filter_flag) +{ + union zxdh_msg msg = {0}; + int32_t err = 0; + + msg.payload.hdr.op_code = ZXDH_MAC_ADD; + msg.payload.hdr.vport = en_dev->vport; + msg.payload.hdr.pcie_id = en_dev->pcie_id; + msg.payload.mac_addr_set_msg.filter_flag = filter_flag; + memcpy(msg.payload.mac_addr_set_msg.mac_addr, dev_addr, en_dev->netdev->addr_len); + + err = zxdh_send_command_to_specify(en_dev, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg); + if (err != 0) + { + if (msg.reps.flag == ZXDH_REPS_BEOND_MAC) + { + return DPP_RC_TABLE_RANGE_INVALID; + } + } + return err; +} + +int32_t zxdh_vf_dpp_del_mac(struct zxdh_en_device *en_dev, const uint8_t *dev_addr, uint8_t filter_flag, bool mac_flag) +{ + union zxdh_msg msg = {0}; + + msg.payload.hdr.op_code = ZXDH_MAC_DEL; + msg.payload.hdr.vport = en_dev->vport; + msg.payload.hdr.pcie_id = en_dev->pcie_id; + msg.payload.mac_addr_set_msg.filter_flag = filter_flag; + msg.payload.mac_addr_set_msg.mac_flag = mac_flag; + memcpy(msg.payload.mac_addr_set_msg.mac_addr, dev_addr, en_dev->netdev->addr_len); + + return zxdh_send_command_to_specify(en_dev, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg); +} + +int32_t zxdh_vf_rss_en_set(struct zxdh_en_device *en_dev, uint32_t enable) +{ + union zxdh_msg msg = {0}; + + msg.payload.hdr.op_code = ZXDH_RSS_EN_SET; + msg.payload.hdr.vport = en_dev->vport; + msg.payload.hdr.pcie_id = en_dev->pcie_id; + msg.payload.rss_enable_msg.rss_enable = enable; + return zxdh_send_command_to_specify(en_dev, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg); +} + +int32_t zxdh_vf_dpp_add_ipv6_mac(struct zxdh_en_device *en_dev, const uint8_t *mac_addr) +{ + union zxdh_msg msg = {0}; + int32_t err = 0; + + msg.payload.hdr.op_code = ZXDH_IPV6_MAC_ADD; + msg.payload.hdr.vport = en_dev->vport; + msg.payload.hdr.pcie_id = en_dev->pcie_id; + memcpy(msg.payload.mac_addr_set_msg.mac_addr, mac_addr, en_dev->netdev->addr_len); + err = zxdh_send_command_to_specify(en_dev, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg); + if ((err != 0) && (msg.reps.flag == ZXDH_REPS_BEOND_MAC)) + { + LOG_ERR("Add Multicast MAC Address(%pM) Failed, Beyond Max MAC Num 32\n", mac_addr); + return DPP_RC_TABLE_RANGE_INVALID; + } + return err; +} + +int32_t zxdh_vf_dpp_del_ipv6_mac(struct zxdh_en_device *en_dev, const uint8_t *mac_addr) +{ + union zxdh_msg msg = {0}; + + msg.payload.hdr.op_code = ZXDH_IPV6_MAC_DEL; + msg.payload.hdr.vport = en_dev->vport; + msg.payload.hdr.pcie_id = en_dev->pcie_id; + memcpy(msg.payload.mac_addr_set_msg.mac_addr, mac_addr, en_dev->netdev->addr_len); + + return zxdh_send_command_to_specify(en_dev, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg); +} + +int32_t zxdh_vf_egr_port_attr_set(struct zxdh_en_device *en_dev, uint32_t mode, uint32_t value, uint8_t fow) +{ + union zxdh_msg msg = {0}; + + msg.payload.hdr.op_code = ZXDH_PORT_ATTRS_SET; + msg.payload.hdr.vport = en_dev->vport; + msg.payload.hdr.pcie_id = en_dev->pcie_id; + msg.payload.port_attr_set_msg.mode = mode; + msg.payload.port_attr_set_msg.value = value; + msg.payload.port_attr_set_msg.allmulti_follow = fow; + return zxdh_send_command_to_specify(en_dev, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg); +} + +int32_t zxdh_vf_egr_port_attr_get(struct zxdh_en_device *en_dev, ZXDH_VPORT_T *port_attr_entry) +{ + union zxdh_msg msg = {0}; + int32_t err = 0; + + msg.payload.hdr.op_code = ZXDH_PORT_ATTRS_GET; + msg.payload.hdr.vport = en_dev->vport; + msg.payload.hdr.pcie_id = en_dev->pcie_id; + err = zxdh_send_command_to_specify(en_dev, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg); + if (err != 0) + { + LOG_ERR("vf_egr_port_attr_get failed, err = %d\n", err); + return err; + } + + memcpy(port_attr_entry, &msg.reps.port_attr_get_msg.port_attr_entry, sizeof(ZXDH_VPORT_T)); + return err; +} + +int32_t zxdh_vf_port_promisc_set(struct zxdh_en_device *en_dev, uint8_t mode, uint8_t value, uint8_t fow) +{ + union zxdh_msg msg = {0}; + + msg.payload.hdr.op_code = ZXDH_PROMISC_SET; + msg.payload.hdr.vport = en_dev->vport; + msg.payload.hdr.pcie_id = en_dev->pcie_id; + msg.payload.promisc_set_msg.mode = mode; + msg.payload.promisc_set_msg.value = value; + msg.payload.promisc_set_msg.mc_follow = fow; + return zxdh_send_command_to_specify(en_dev, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg); +} + +int32_t zxdh_en_vport_create(struct zxdh_en_device *en_dev) +{ + DPP_PF_INFO_T pf_info = {0}; + + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + if (!en_dev->ops->if_init(en_dev->parent)) + { + return 0; + } + + return dpp_vport_create(&pf_info); +} + +int32_t zxdh_en_vport_delete(struct zxdh_en_device *en_dev) +{ + DPP_PF_INFO_T pf_info = {0}; + + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + if (!en_dev->ops->if_init(en_dev->parent)) + { + return 0; + } + + return dpp_vport_delete(&pf_info); +} + +int32_t zxdh_pf_vport_create(struct zxdh_en_device *en_dev) +{ + int32_t ret = 0; + DPP_PF_INFO_T pf_info = {0}; + + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + + ret = zxdh_en_vport_create(en_dev); + if (ret != 0) + { + LOG_ERR("zxdh_en_vport_create failed: %d\n", ret); + return ret; + } + + ret = dpp_vport_bond_pf(&pf_info); + if (ret != 0) + { + LOG_ERR("dpp_vport_bond_pf failed: %d\n", ret); + goto err_vport; + } + + if (en_dev->ops->is_upf(en_dev->parent)) + { + ret = dpp_egr_port_attr_set(&pf_info, EGR_FLAG_LAG_ID, 0); + if (ret != 0) + { + LOG_ERR("dpp_egr_port_attr_set lag_id 0 failed: %d\n", ret); + goto err_vport; + } + + ret = dpp_egr_port_attr_set(&pf_info, EGR_FLAG_LAG_EN_OFF, 1); + if (ret != 0) + { + LOG_ERR("dpp_egr_port_attr_set bond_en 1 failed: %d\n", ret); + goto err_vport; + } + } + else + { + ret = dpp_panel_bond_vport(&pf_info, en_dev->phy_port); + if (ret != 0) + { + LOG_ERR("dpp_panel_bond_vport failed: %d\n", ret); + goto err_vport; + } + } + + return ret; + +err_vport: + zxdh_en_vport_delete(en_dev); + return ret; +} + +int32_t zxdh_rxfh_set(struct zxdh_en_device *en_dev, uint32_t *queue_map) +{ + union zxdh_msg msg = {0}; + int32_t err = 0; + DPP_PF_INFO_T pf_info = {0}; + + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + + if (queue_map == NULL) + { + return -1; + } + + if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) + { + err = dpp_rxfh_set(&pf_info, queue_map, ZXDH_INDIR_RQT_SIZE); + if (err != 0) + { + LOG_ERR("dpp_rxfh_set failed: %d\n", err); + } + } + else + { + msg.payload.hdr.op_code = ZXDH_RXFH_SET; + msg.payload.hdr.vport = en_dev->vport; + msg.payload.hdr.pcie_id = en_dev->pcie_id; + memcpy(msg.payload.rxfh_set_msg.queue_map, queue_map, ZXDH_INDIR_RQT_SIZE * sizeof(uint32_t)); + err = en_dev->ops->msg_send_cmd(en_dev->parent, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg, true); + if(err != 0) + { + LOG_ERR("zxdh_send_command_to_pf_np failed: %d\n", err); + } + } + + return err; +} + +void zxdh_rxfh_del(struct zxdh_en_device *en_dev) +{ + union zxdh_msg msg = {0}; + int32_t err = 0; + DPP_PF_INFO_T pf_info = {0}; + + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + + if (en_dev->ops->is_bond(en_dev->parent)) + { + return; + } + + if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) + { + dpp_rxfh_del(&pf_info); + } + else + { + msg.payload.hdr.op_code = ZXDH_RXFH_DEL; + msg.payload.hdr.vport = en_dev->vport; + msg.payload.hdr.pcie_id = en_dev->pcie_id; + err = en_dev->ops->msg_send_cmd(en_dev->parent, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg, true); + if(err != 0) + { + LOG_ERR("zxdh_send_command_to_pf_np failed: %d\n", err); + } + } +} + +int32_t zxdh_ethtool_init(struct zxdh_en_device *en_dev) +{ + int32_t ret = 0; + DPP_PF_INFO_T pf_info = {0}; + + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + + ret = dpp_vport_rss_en_set(&pf_info, 1); + if (ret != 0) + { + LOG_ERR("dpp_vport_rss_en_set failed: %d\n", ret); + return ret; + } + + ret = dpp_vport_hash_funcs_set(&pf_info, en_dev->hash_func); + if (ret != 0) + { + LOG_ERR("dpp_vport_hash_funcs_set failed: %d\n", ret); + return ret; + } + + ret = dpp_rx_flow_hash_set(&pf_info, ZXDH_NET_RX_FLOW_HASH_SDFNT); + if (ret != 0) + { + LOG_ERR("zxdh_rx_flow_hash_set failed: %d\n", ret); + return ret; + } + + ret = dpp_egr_port_attr_set(&pf_info, EGR_FLAG_PORT_BASE_QID, (uint16_t)en_dev->phy_index[0]); + if (ret != 0) + { + LOG_ERR("dpp_egr_port_attr_set %d failed: %d\n", en_dev->phy_index[0], ret); + return ret; + } + + ret = dpp_egr_port_attr_set(&pf_info, EGR_FLAG_IPV4_TCP_ASSEMBLE, 1); + if (ret != 0) + { + LOG_ERR("dpp_egr_port_attr_set tcp assemble failed: %d\n", ret); + return ret; + } + + ret = dpp_egr_port_attr_set(&pf_info, EGR_FLAG_IPV6_TCP_ASSEMBLE, 1); + if (ret != 0) + { + LOG_ERR("dpp_egr_port_attr_set tcp assemble failed: %d\n", ret); + return ret; + } + + ret = dpp_egr_port_attr_set(&pf_info, EGR_FLAG_IP_CHKSUM, 1); + if (ret != 0) + { + LOG_ERR("dpp_egr_port_attr_set rx ip checksum failed: %d\n", ret); + return ret; + } + + ret = dpp_egr_port_attr_set(&pf_info, EGR_FLAG_TCP_UDP_CHKSUM, 1); + if (ret != 0) + { + LOG_ERR("dpp_egr_port_attr_set rx l4 checksum failed: %d\n", ret); + return ret; + } + + ret = dpp_egr_port_attr_set(&pf_info, EGR_FLAG_ACCELERATOR_OFFLOAD_FLAG, 1); + if (ret != 0) + { + LOG_ERR("dpp_egr_port_attr_set accelerator offload failed: %d\n", ret); + return ret; + } + + ret = dpp_egr_port_attr_set(&pf_info, EGR_FLAG_OUTER_IP_CHECKSUM_OFFLOAD, 1); + if (ret != 0) + { + LOG_ERR("dpp_egr_port_attr_set vxlan outer ip checksum failed: %d\n", ret); + return ret; + } + + ret = dpp_vport_vlan_filter_en_set(&pf_info, 0); + if (ret != 0) + { + LOG_ERR("dpp_vport_vlan_filter_en_set failed: %d\n", ret); + return ret; + } + + ret = dpp_vlan_filter_init(&pf_info); + if (ret != 0) + { + LOG_ERR("dpp_vlan_filter_init failed: %d\n", ret); + return ret; + } + + return ret; +} + +int32_t zxdh_pf_flush_mac(struct zxdh_en_device *en_dev) +{ + int32_t err = 0; + DPP_PF_INFO_T pf_info = {0}; + + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + + /* 删除此转发域所有单播mac地址 */ + err = dpp_unicast_all_mac_delete(&pf_info); + if (err != 0) + { + LOG_ERR("dpp_unicast_all_mac_delete failed\n"); + return err; + } + LOG_INFO("dpp_unicast_all_mac_delete succeed\n"); + + /* 删除此转发域中所有组播mac地址 */ + err = dpp_multicast_all_mac_delete(&pf_info); + if (err != 0) + { + LOG_ERR("dpp_multicast_all_mac_delete failed\n"); + return err; + } + LOG_INFO("dpp_multicast_all_mac_delete succeed\n"); + + return err; +} + +int32_t zxdh_pf_flush_mac_online(struct zxdh_en_device *en_dev) +{ + int32_t err = 0; + DPP_PF_INFO_T pf_info = {0}; + + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + + /* 删除此转发域所有单播mac地址 */ + err = dpp_unicast_all_mac_online_delete(&pf_info); + if (err != 0) + { + LOG_ERR("dpp_unicast_all_mac_online_delete failed:%d\n", err); + return err; + } + + /* 删除此转发域中所有组播mac地址 */ + err = dpp_multicast_all_mac_online_delete(&pf_info); + if (err != 0) + { + LOG_ERR("dpp_multicast_all_mac_online_delete failed:%d\n", err); + return err; + } + + return err; +} + +int32_t zxdh_pf_port_delete(struct net_device *netdev) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + int32_t ret = 0; + DPP_PF_INFO_T pf_info = {0}; + + if (en_dev == NULL) + { + return -1; + } + + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + dpp_vport_uc_promisc_set(&pf_info, 0); + dpp_vport_mc_promisc_set(&pf_info, 0); + + /* pf删除所有配置到np的mac地址 */ + if (!en_dev->ops->is_bond(en_dev->parent)) + { + ret = zxdh_pf_flush_mac_online(en_dev); + if (ret != 0) + { + LOG_ERR("zxdh_pf_flush_mac_online failed: %d\n", ret); + return ret; + } + } + + ret = zxdh_en_vport_delete(en_dev); + if (ret != 0) + { + LOG_ERR("dpp_vport_delete failed: %d\n", ret); + return ret; + } + + return ret; +} + +int32_t zxdh_aux_alloc_pannel(struct zxdh_en_device *en_dev) +{ + int32_t ret = 0; + struct zxdh_pannle_port port; + + ret = en_dev->ops->request_port(en_dev->parent, &port); + if (ret != 0) + { + LOG_ERR("zxdh_aux_alloc_pannel failed \n"); + goto out; + } + + en_dev->phy_port = port.phyport; + en_dev->pannel_id = port.pannel_id; + en_dev->link_check_bit = port.link_check_bit; + + LOG_INFO("bond pf: pannel %u, phyport %u check bit %u \n", + en_dev->pannel_id, en_dev->phy_port, en_dev->link_check_bit); + +out: + return ret; +} + +#if 0 +int32_t zxdh_aux_query_phyport(struct zxdh_en_device *en_dev) +{ + int32_t ret = 0; + struct aux_phyport_message recv = {0}; + struct aux_phyport_message *recv_data = &recv; + zxdh_aux_phyport_msg msg = {0}; + zxdh_aux_phyport_msg *payload = &msg; + + payload->pcie_id = en_dev->pcie_id; + payload->pannel_id = en_dev->pannel_id; + payload->rsv = en_dev->pannel_id; + + ret = en_dev->ops->msg_send_cmd(en_dev->parent, MODULE_PHYPORT_QUERY, payload, recv_data, true); + if (ret != 0) + { + LOG_ERR("zxdh_aux_query_phyport send message failed \n"); + goto out; + } + + en_dev->phy_port = recv_data->phyport; + +out: + return ret; +} +#endif +int32_t zxdh_pf_port_init(struct net_device *netdev) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + bool vepa = false; + int32_t ret = 0; + DPP_PF_INFO_T pf_info = {0}; + + if (en_dev == NULL) + { + return -1; + } + + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + +#if 0 + en_dev->ops->dpp_np_init(en_dev->parent, en_dev->vport); +#endif + + ret = zxdh_pf_vport_create(en_dev); + if (ret != 0) + { + LOG_ERR("zxdh_pf_vport_create failed: %d\n", ret); + return ret; + } + + zxdh_mac_stats_clear(en_dev); + + if (en_dev->ops->is_bond(en_dev->parent)) + { + if (!en_dev->ops->if_init(en_dev->parent)) + { + LOG_INFO("First net-device is init\n"); + return 0; + } + + /* 只将第一个网络设备的队列配置到vport属性表中 */ + ret = dpp_egr_port_attr_set(&pf_info, EGR_FLAG_PORT_BASE_QID, (uint16_t)en_dev->phy_index[0]); + if (ret != 0) + { + LOG_ERR("dpp_egr_port_attr_set %d failed: %d\n", en_dev->phy_index[0], ret); + goto err_vport; + } + return 0; + } + + vepa = en_dev->ops->get_vepa(en_dev->parent); + ret = dpp_egr_port_attr_set(&pf_info, EGR_FLAG_VEPA_EN_OFF, (uint32_t)vepa); + if (ret != 0) + { + LOG_ERR("Failed to setup vport(0x%x) %s mode, ret: %d\n", en_dev->vport, vepa?"vepa":"veb", ret); + goto err_vport; + } + LOG_INFO("Initialize vport(0x%x) to %s mode\n", en_dev->vport, vepa?"vepa":"veb"); + + ret = dpp_egr_port_attr_set(&pf_info, EGR_FLAG_HASH_SEARCH_INDEX, en_dev->hash_search_idx); + if (ret != 0) + { + LOG_ERR("dpp_egr_port_attr_set hash_search_index %u failed: %d\n", en_dev->hash_search_idx, ret); + goto err_vport; + } + + ret = zxdh_ethtool_init(en_dev); + if (ret != 0) + { + LOG_ERR("zxdh_ethtool_init failed: %d\n", ret); + return ret; + } + + /* PF删除复位前配置到np的mac */ + ret = zxdh_pf_flush_mac(en_dev); + if (ret != 0) + { + LOG_ERR("zxdh_pf_flush_mac failed: %d\n", ret); + goto err_vport; + } + + ret = dpp_add_mac(&pf_info, netdev->dev_addr); + if (ret != 0) + { + LOG_ERR("dpp_add_mac failed: %d\n", ret); + goto err_vport; + } + + dpp_vport_uc_promisc_set(&pf_info, 0); + dpp_vport_mc_promisc_set(&pf_info, 0); + + return 0; + +err_vport: + zxdh_en_vport_delete(en_dev); + return ret; +} + +int32_t zxdh_vf_get_mac(struct net_device *netdev) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + struct netdev_hw_addr *ha = NULL; + union zxdh_msg msg = {0}; + uint8_t mac[6] = {0}; + int32_t ret = 0; + bool add_flag = true; + + msg.payload.hdr.op_code = ZXDH_MAC_GET; + msg.payload.hdr.vport = en_dev->vport; + msg.payload.hdr.pcie_id = en_dev->pcie_id; + ret = zxdh_send_command_to_specify(en_dev, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg); + if (ret != 0) + { + LOG_ERR("zxdh_send_command_to_pf failed: %d\n", ret); + return ret; + } + + ether_addr_copy(mac, msg.reps.vf_mac_addr_get_msg.mac_addr); + LOG_INFO("zxdh_vf_get_mac %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + if (is_zero_ether_addr(mac)) + { + get_random_bytes(mac, 6); + mac[0] &= 0xfe; + LOG_INFO("vf set random mac %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + } + + list_for_each_entry(ha, &netdev->uc.list, list) + { + if (!memcmp(ha->addr, mac, netdev->addr_len)) + { + add_flag = false; + } + } + + if (add_flag) + { + ret = zxdh_vf_dpp_add_mac(en_dev, mac, UNFILTER_MAC); + if (ret != 0) + { + LOG_ERR("zxdh_vf_dpp_add_mac failed: %d\n", ret); + goto free_vport; + } + } + + ether_addr_copy(netdev->dev_addr, mac); + + return ret; +free_vport: + zxdh_vf_port_delete(en_dev); + return ret; +} + +int32_t zxdh_vf_dpp_port_init(struct net_device *netdev) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + int32_t ret = 0; + + ret = zxdh_vf_port_create(en_dev); + if (ret != 0) + { + LOG_ERR("zxdh_vf_port_create failed: %d\n", ret); + } + + return ret; +} + +void zxdh_vport_uninit(struct net_device *netdev) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + int32_t ret = 0; + + if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) + { + ret = zxdh_pf_port_delete(netdev); + if (ret != 0) + { + LOG_ERR("zxdh_pf_port_delete failed: %d\n", ret); + } + } + else + { + ret = zxdh_vf_port_delete(en_dev); + if (ret != 0) + { + LOG_ERR("zxdh_vf_port_delete failed: %d\n", ret); + } + } +} diff --git a/src/net/drivers/net/ethernet/dinghai/en_aux/en_cmd.h b/src/net/drivers/net/ethernet/dinghai/en_aux/en_cmd.h new file mode 100644 index 0000000..578b8dc --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_aux/en_cmd.h @@ -0,0 +1,226 @@ +#ifndef _ZXDH_EN_COMMAND_H_ +#define _ZXDH_EN_COMMAND_H_ + +#include +#include "../msg_common.h" + +#define ZXDH_QRES_TBL_LEN (300) +#define ZXDH_QS_PAIRS (2) + +#define INVALID_PHY_PORT 0xff +#define ZXDH_MAX_HASH_INDEX 6//TODO:should is 5 + +/* HASH_FUNC TYPE */ +#define ZXDH_FUNC_TOP 0x04 +#define ZXDH_FUNC_XOR 0x02 +#define ZXDH_FUNC_CRC32 0x01 + +/* RX_NFC */ +#define ZXDH_NET_RX_FLOW_HASH_MV 4 +#define ZXDH_NET_RX_FLOW_HASH_SDT 2 +#define ZXDH_NET_RX_FLOW_HASH_SDFNT 1 + +/* RISCV OPCODE */ +#define RISC_TYPE_READ 0 +#define RISC_FIELD_PANEL_ID 5 +#define RISC_FIELD_PHYPORT_CHANNEL 6 +#define RISC_FIELD_HASHID_CHANNEL 10 +#define RISC_SERVER_TIME 0xF0 + + +#define MAX_PANEL_ID 8//TODO:should is 5 + +enum riscv_op_code +{ + OP_CODE_WRITE = 1, + OP_CODE_MSGQ_CHAN = 2, + OP_CODE_DATA_CHAN = 3, + OP_CODE_MAX, +}; + +#define OP_CODE_TBL_STAT (0xaa) +#define MSG_STRUCT_HD_LEN 8 + +struct queue_index_message +{ + uint8_t type; + uint8_t field; + uint16_t ep_bdf; + uint16_t write_bytes; + uint16_t rsv; + uint16_t write_data[0]; +} __attribute__((packed)); + +struct cmd_hdr_recv +{ + uint8_t check; + uint8_t rsv; + uint16_t data_len_bytes; +}; + +struct cmd_tbl_ack +{ + struct cmd_hdr_recv hdr; + uint8_t phy_port; + uint8_t rsv[3]; +} __attribute__((packed)); + +enum zxdh_msg_chan_opc +{ + ZXDH_VPORT_GET = 4, + ZXDH_PHYPORT_GET = 6, +}; + +struct zxdh_debug_msg +{ + uint8_t opcode; + uint8_t phyport; + bool lldp_enable; +} __attribute__((packed)); + +struct zxdh_debug_rcv_msg +{ + uint8_t reps_states; + uint8_t lldp_enable; +} __attribute__((packed)); + +enum zxdh_en_link_speed_bit_indices +{ + SPM_SPEED_1X_1G = 2, + SPM_SPEED_1X_10G = 5, + SPM_SPEED_1X_25G = 6, + SPM_SPEED_1X_50G = 7, + SPM_SPEED_2X_100G = 8, + SPM_SPEED_4X_40G = 9, + SPM_SPEED_4X_100G = 10, +}; + +enum zxdh_en_fec_mode_bit_indices +{ + SPM_FEC_NONE = 0, + SPM_FEC_BASER = 1, + SPM_FEC_RS528 = 2, + SPM_FEC_RS544 = 3, +}; + +enum zxdh_en_fc_mode_bit_indices +{ + SPM_FC_NONE = 0, + SPM_FC_PAUSE_RX = 1, + SPM_FC_PAUSE_TX = 2, + SPM_FC_PAUSE_FULL = 3, + SPM_FC_PFC_FULL = 4, +}; + +struct zxdh_en_module_eeprom_param +{ + uint8_t i2c_addr; + uint8_t bank; + uint8_t page; + uint8_t offset; + uint8_t length; +}; + +#define SFF_I2C_ADDRESS_LOW (0x50) +#define SFF_I2C_ADDRESS_HIGH (0x51) + +enum zxdh_module_id { + ZXDH_MODULE_ID_SFP = 0x3, + ZXDH_MODULE_ID_QSFP = 0xC, + ZXDH_MODULE_ID_QSFP_PLUS = 0xD, + ZXDH_MODULE_ID_QSFP28 = 0x11, + ZXDH_MODULE_ID_QSFP_DD = 0x18, + ZXDH_MODULE_ID_OSFP = 0x19, + ZXDH_MODULE_ID_DSFP = 0x1B, +}; + +#define SPEED_MODES_TO_SPEED(speed_modes, speed) \ +do \ +{ \ + if (((speed_modes) & BIT(SPM_SPEED_1X_1G)) == BIT(SPM_SPEED_1X_1G)) \ + { \ + (speed) = SPEED_1000; \ + } \ + else if (((speed_modes) & BIT(SPM_SPEED_1X_10G)) == BIT(SPM_SPEED_1X_10G)) \ + { \ + (speed) = SPEED_10000; \ + } \ + else if (((speed_modes) & BIT(SPM_SPEED_1X_25G)) == BIT(SPM_SPEED_1X_25G)) \ + { \ + (speed) = SPEED_25000; \ + } \ + else if (((speed_modes) & BIT(SPM_SPEED_4X_40G)) == BIT(SPM_SPEED_4X_40G)) \ + { \ + (speed) = SPEED_40000; \ + } \ + else if (((speed_modes) & BIT(SPM_SPEED_1X_50G)) == BIT(SPM_SPEED_1X_50G)) \ + { \ + (speed) = SPEED_50000; \ + } \ + else if (((speed_modes) & BIT(SPM_SPEED_2X_100G)) == BIT(SPM_SPEED_2X_100G)) \ + { \ + (speed) = SPEED_100000; \ + } \ + else if (((speed_modes) & BIT(SPM_SPEED_4X_100G)) == BIT(SPM_SPEED_4X_100G)) \ + { \ + (speed) = SPEED_100000; \ + } \ + else \ + { \ + (speed) = SPEED_UNKNOWN; \ + } \ +} while (0) + +#define GET_VFID(vport) \ + (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) ? \ + (PF_VQM_VFID_OFFSET + EPID(vport) * 8 + FUNC_NUM(vport)) : \ + (EPID(vport) * 256 + VFUNC_NUM(vport)) \ + + +#define NP_GET_PKT_CNT 0 +#define NP_CLEAR_PKT_CNT 1 + +struct zxdh_en_device; +int32_t zxdh_common_tbl_init(struct net_device *netdev); +int32_t zxdh_en_phyport_init(struct zxdh_en_device *en_dev); +int32_t zxdh_en_autoneg_set(struct zxdh_en_device *en_dev, uint8_t enable, uint32_t speed_modes); +int32_t zxdh_vport_stats_get(struct zxdh_en_device *en_dev); +int32_t zxdh_en_vport_pre_stats_get(struct zxdh_en_device *en_dev); +int32_t zxdh_mac_stats_get(struct zxdh_en_device *en_dev); +int32_t zxdh_mac_stats_clear(struct zxdh_en_device *en_dev); +int32_t zxdh_hash_id_get(struct zxdh_en_device *en_dev); +int32_t zxdh_en_fec_mode_set(struct zxdh_en_device *en_dev, uint32_t fec_cfg); +int32_t zxdh_en_fec_mode_get(struct zxdh_en_device *en_dev, uint32_t *fec_cap, uint32_t *fec_cfg, uint32_t *fec_active); +int32_t zxdh_en_fc_mode_set(struct zxdh_en_device *en_dev, uint32_t fc_mode); +int32_t zxdh_en_fc_mode_get(struct zxdh_en_device *en_dev, uint32_t *fc_mode); +uint32_t zxdh_en_module_eeprom_read(struct zxdh_en_device *en_dev, struct zxdh_en_module_eeprom_param *query, uint8_t *data); +int32_t zxdh_lldp_enable_set(struct zxdh_en_device *en_dev, bool lldp_enable); +int32_t zxdh_sshd_enable_set(struct zxdh_en_device *en_dev, bool sshd_enable); +int32_t zxdh_vf_dpp_add_mac(struct zxdh_en_device *en_dev, const uint8_t *dev_addr, uint8_t filter_flag); +int32_t zxdh_vf_dpp_del_mac(struct zxdh_en_device *en_dev, const uint8_t *dev_addr, uint8_t filter_flag, bool mac_flag); +void zxdh_vport_uninit(struct net_device *netdev); +int32_t zxdh_pf_port_init(struct net_device *netdev); +int32_t zxdh_vf_dpp_port_init(struct net_device *netdev); +int32_t zxdh_vf_egr_port_attr_set(struct zxdh_en_device *en_dev, uint32_t mode, uint32_t value, uint8_t fow); +int32_t zxdh_vf_egr_port_attr_get(struct zxdh_en_device *en_dev, ZXDH_VPORT_T *port_attr_entry); +int32_t zxdh_vf_rss_en_set(struct zxdh_en_device *en_dev, uint32_t enable); +int32_t zxdh_num_channels_changed(struct zxdh_en_device *en_dev, uint16_t num_changed); +int32_t zxdh_send_command_to_specify(struct zxdh_en_device *en_dev, uint16_t module_id, void *msg, void *ack); +int32_t zxdh_pf_macpcs_num_get(struct zxdh_en_device *en_dev); +int32_t zxdh_lldp_enable_get(struct zxdh_en_device *en_dev, uint32_t *lldp_enable); +int32_t zxdh_vf_get_mac(struct net_device *netdev); +int32_t zxdh_rxfh_set(struct zxdh_en_device *en_dev, uint32_t *queue_map); +void zxdh_rxfh_del(struct zxdh_en_device *en_dev); +void zxdh_u32_array_print(uint32_t *array, uint16_t size); +int32_t zxdh_en_firmware_version_get(struct zxdh_en_device *en_dev, uint8_t *fw_version, uint8_t *fw_version_len); +int32_t zxdh_panel_id_get(struct zxdh_en_device *en_dev); +int32_t zxdh_vf_port_promisc_set(struct zxdh_en_device *en_dev, uint8_t mode, uint8_t value, uint8_t fow); +int32_t zxdh_phyport_get(struct zxdh_en_device *en_dev); +int32_t zxdh_vf_1588_call_np_interface(struct zxdh_en_device *en_dev); +int32_t zxdh_aux_alloc_pannel(struct zxdh_en_device *en_dev); +int8_t zxdh_debug_ip_get(struct zxdh_en_device *en_dev, int8_t *ip); +int32_t zxdh_riscv_os_type_get(struct zxdh_en_device *en_dev, uint8_t *is_zios); +int32_t zxdh_vf_dpp_add_ipv6_mac(struct zxdh_en_device *en_dev, const uint8_t *mac_addr); +int32_t zxdh_vf_dpp_del_ipv6_mac(struct zxdh_en_device *en_dev, const uint8_t *mac_addr); + +#endif /* END __ZXDH_EN_COMMAND_H_ */ diff --git a/src/net/drivers/net/ethernet/dinghai/en_aux/en_ioctl.c b/src/net/drivers/net/ethernet/dinghai/en_aux/en_ioctl.c new file mode 100644 index 0000000..f8a48fb --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_aux/en_ioctl.c @@ -0,0 +1,1463 @@ +#include +#include "en_ioctl.h" +#include "en_cmd.h" +#include "../zxdh_tools/zxdh_tools_ioctl.h" +#include "queue.h" +#include "priv_queue.h" +#include "../en_np/table/include/dpp_tbl_api.h" +#include "../en_pf/msg_func.h" +#include "../en_pf/eq.h" +#include "../en_tsn/zxdh_tsn_ioctl.h" + +extern int32_t tod_device_set_bar_virtual_addr(uint64_t virtaddr, uint16_t pcieid); +int32_t print_data(uint8_t *data, uint32_t len) +{ + int32_t i = 0; + uint32_t loopcnt = 0; + uint32_t last_line_len = 0; + uint32_t line_len = PKT_PRINT_LINE_LEN; + uint8_t last_line_data[PKT_PRINT_LINE_LEN] = {0}; + + if (len == 0) + { + return 0; + } + loopcnt = len / line_len; + last_line_len = len % line_len; + + LOG_DEBUG("***************packet data[len: %d]***************\n", len); + for (i = 0; i < loopcnt; i++) + { + LOG_INFO("%.2x %.2x %.2x %.2x %.2x %.2x %.2x %.2x %.2x %.2x %.2x %.2x %.2x %.2x %.2x %.2x\n", \ + *(data + (line_len * i) + 0), *(data + (line_len * i) + 1), *(data + (line_len * i) + 2), *(data + (line_len * i) + 3), \ + *(data + (line_len * i) + 4), *(data + (line_len * i) + 5), *(data + (line_len * i) + 6), *(data + (line_len * i) + 7), \ + *(data + (line_len * i) + 8), *(data + (line_len * i) + 9), *(data + (line_len * i) + 10), *(data + (line_len * i) + 11), \ + *(data + (line_len * i) + 12), *(data + (line_len * i) + 13), *(data + (line_len * i) + 14), *(data + (line_len * i) + 15)); + } + if (last_line_len != 0) + { + memcpy(last_line_data, (data + (line_len * i)), last_line_len); + LOG_INFO("%.2x %.2x %.2x %.2x %.2x %.2x %.2x %.2x %.2x %.2x %.2x %.2x %.2x %.2x %.2x %.2x\n", \ + last_line_data[0], last_line_data[1], last_line_data[2], last_line_data[3], \ + last_line_data[4], last_line_data[5], last_line_data[6], last_line_data[7], \ + last_line_data[8], last_line_data[9], last_line_data[10], last_line_data[11], \ + last_line_data[12], last_line_data[13], last_line_data[14], last_line_data[15]); + } + LOG_INFO("****************end packet data**************\n"); + + return 0; +} + +int32_t zxdh_read_reg_cmd(struct net_device *netdev, struct ifreq *ifr) +{ + struct zxdh_en_priv *en_priv = NULL; + struct zxdh_en_device *en_dev = NULL; + struct zxdh_en_reg *reg = NULL; + uint32_t size = sizeof(struct zxdh_en_reg); + uint64_t base_addr = 0; + uint32_t num = 0; + int32_t err = 0; + + CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n"); + CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n"); + + en_priv = netdev_priv(netdev); + CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n"); + en_dev = &en_priv->edev; + + reg = kzalloc(size, GFP_KERNEL); + CHECK_EQUAL_ERR(reg, NULL, -EADDRNOTAVAIL, "reg is null!\n"); + + if (copy_from_user(reg, ifr->ifr_ifru.ifru_data, size)) + { + LOG_ERR("copy_from_user failed\n"); + err = -EFAULT; + goto err_ret; + } + + if ((reg->num == 0) || (reg->num > MAX_ACCESS_NUM)) + { + LOG_ERR("transmit failed, reg->num=%u\n", reg->num); + err = -EFAULT; + goto err_ret; + } + + base_addr = en_dev->ops->get_bar_virt_addr(en_dev->parent, 0); + + for (num = 0; num < reg->num; num++) + { + reg->data[num] = readl((const volatile void *)(base_addr + (reg->offset & 0xfffffffc) + num * 4)); + } + + if (copy_to_user(ifr->ifr_ifru.ifru_data, reg, size)) + { + LOG_ERR("copy_to_user failed\n"); + err = -EFAULT; + } + +err_ret: + kfree(reg); + return err; +} + +int32_t zxdh_write_reg_cmd(struct net_device *netdev, struct ifreq *ifr) +{ + struct zxdh_en_priv *en_priv = NULL; + struct zxdh_en_device *en_dev = NULL; + struct zxdh_en_reg *reg = NULL; + uint32_t size = sizeof(struct zxdh_en_reg); + uint64_t base_addr = 0; + uint32_t num = 0; + int32_t err = 0; + + CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n"); + CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n"); + + en_priv = netdev_priv(netdev); + CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n"); + en_dev = &en_priv->edev; + + reg = kzalloc(size, GFP_KERNEL); + CHECK_EQUAL_ERR(reg, NULL, -EADDRNOTAVAIL, "reg is null!\n"); + + if (copy_from_user(reg, ifr->ifr_ifru.ifru_data, size)) + { + LOG_ERR("copy_from_user failed\n"); + err = -EFAULT; + goto err_ret; + } + + if ((reg->num == 0) || (reg->num > MAX_ACCESS_NUM)) + { + LOG_ERR("transmit failed, reg->num=%u\n", reg->num); + err = -EFAULT; + goto err_ret; + } + + base_addr = en_dev->ops->get_bar_virt_addr(en_dev->parent, 0); + + for (num = 0; num < reg->num; num++) + { + writel(reg->data[num], (volatile void *)(base_addr + (reg->offset & 0xfffffffc) + num * 4)); + } + +err_ret: + kfree(reg); + return err; +} + +int32_t print_vring_info(struct virtqueue *vq, struct zxdh_en_reg *reg) +{ + struct vring_virtqueue *vvq = to_vvq(vq); + + if ((reg->num + reg->data[0]) > vvq->packed.vring.num) + { + LOG_ERR("the sum of desc_index %u and desc_num %u over desc depth %u, should be [0-%u]\n", \ + reg->num, reg->data[0], vvq->packed.vring.num, vvq->packed.vring.num - 1); + return -EINVAL; + } + + zxdh_print_vring_info(vq, reg->num, reg->num + reg->data[0]); + + return 0; +} + +int32_t zxdh_get_vring_info(struct net_device *netdev, struct ifreq *ifr) +{ + struct zxdh_en_priv *en_priv = NULL; + struct zxdh_en_device *en_dev = NULL; + struct zxdh_en_reg *reg = NULL; + uint32_t size = sizeof(struct zxdh_en_reg); + struct virtqueue *vq = NULL; + int32_t ret = 0; + + CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n"); + CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n"); + + en_priv = netdev_priv(netdev); + CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n"); + en_dev = &en_priv->edev; + + reg = kzalloc(size, GFP_KERNEL); + CHECK_EQUAL_ERR(reg, NULL, -EADDRNOTAVAIL, "reg is null!\n"); + + if (copy_from_user(reg, ifr->ifr_ifru.ifru_data, size)) + { + LOG_ERR("copy_from_user failed\n"); + ret = -EFAULT; + goto err_ret; + } + + if (reg->offset >= en_dev->max_queue_pairs) + { + LOG_ERR("the queue index %u over the curr_queue_pairs %u, should be [0-%u]\n", \ + reg->offset, en_dev->curr_queue_pairs, en_dev->curr_queue_pairs - 1); + ret = -EINVAL; + goto err_ret; + } + + vq = en_dev->sq[reg->offset].vq; + LOG_INFO("******************************tx vring info****************************\n"); + ret = print_vring_info(vq, reg); + if (ret != 0) + { + LOG_ERR("print tx vring info failed!\n"); + ret = -EINVAL; + goto err_ret; + } + + vq = en_dev->rq[reg->offset].vq; + LOG_INFO("******************************rx vring info****************************\n"); + ret = print_vring_info(vq, reg); + if (ret != 0) + { + LOG_ERR("print rx vring info failed!\n"); + ret = -EINVAL; + } + +err_ret: + kfree(reg); + return ret; +} + +int32_t zxdh_en_set_clock_no(struct net_device *netdev, struct ifreq *ifr, struct zxdh_en_reg *reg) +{ + uint32_t reg_size = sizeof(struct zxdh_en_reg); + struct zxdh_en_priv *en_priv = NULL; + struct zxdh_en_device *en_dev = NULL; + + CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n"); + CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n"); + + en_priv = netdev_priv(netdev); + CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n"); + en_dev = &en_priv->edev; + + if (reg->num != 1) + { + LOG_ERR("Transmit failed[len = %d]!\n", reg->num); + goto err_ret; + } + + en_dev->clock_no = reg->data[0]; + LOG_INFO("en_dev %s clock_no = %d\n", en_dev->netdev->name, en_dev->clock_no); + + reg->num = 0; + if (unlikely(copy_to_user(ifr->ifr_ifru.ifru_data, reg, reg_size))) + { + LOG_ERR("copy_to_user failed!\n"); + goto err_ret; + } + + return 0; + +err_ret: + return -1; +} + +void copy_u32_to_u8(uint8_t *data_pkt, uint32_t *data, uint32_t pktlen) +{ + uint32_t i = 0; + + for (i = 0; i < pktlen; i++) + { + *data_pkt++ = data[i]; + } +} + +int32_t zxdh_tx_file_pkts(struct zxdh_en_priv *en_priv, struct zxdh_en_reg *reg) +{ + int32_t total_sg = 0; + uint8_t *data_pkt = NULL; + struct scatterlist *sg = NULL; + struct zxdh_en_device *en_dev = &en_priv->edev; + struct send_queue *sq = en_dev->sq; + struct page *page = NULL; + struct data_packet pkt = {0}; + uint16_t i = 0; + uint32_t len = 0; + void *ptr = NULL; + uint32_t last_buff_len = 0; + uint32_t pktLen = reg->num; + uint32_t buffLen = 4096; + + while ((ptr = virtqueue_get_buf(sq->vq, &len)) != NULL) + { + LOG_ERR("virtqueue_get_buf() != NULL, ptr=0x%llx, len=0x%x\n", (uint64_t)ptr, len); + }; + + sg = sq->sg; + pkt.buf_size = 16 * PAGE_SIZE; + page = alloc_pages(GFP_KERNEL, 4); + if (unlikely(page == NULL)) + { + LOG_ERR("page is null\n"); + goto err; + } + + pkt.buf = page_address(page); + if (unlikely(pkt.buf == NULL)) + { + LOG_ERR("pkt.buf is null\n"); + goto err1; + } + memset(pkt.buf, 0, pkt.buf_size); + + data_pkt = (uint8_t*)pkt.buf; + copy_u32_to_u8(data_pkt, reg->data, pktLen); + print_data(data_pkt, (pktLen > PKT_PRINT_LEN_MAX) ? PKT_PRINT_LEN_MAX : pktLen); + + total_sg = pktLen / buffLen; + last_buff_len = pktLen % buffLen; + if (last_buff_len != 0) + { + total_sg += 1; + } + + sg_init_table(sg, total_sg); + for (i = 0; i < total_sg; i++) + { + if (i == (total_sg - 1)) + { + sg_set_buf(&sg[i], data_pkt + (i * buffLen), ((last_buff_len != 0) ? last_buff_len : buffLen)); + } + else + { + sg_set_buf(&sg[i], data_pkt + (i * buffLen), buffLen); + } + } + + if (unlikely(virtqueue_add_outbuf(sq->vq, sg, total_sg, data_pkt, GFP_ATOMIC) != 0)) + { + LOG_ERR("virtqueue_add_outbuf failure!\n"); + goto err1; + } + + if (virtqueue_kick_prepare_packed(sq->vq) && virtqueue_notify(sq->vq)) + { + u64_stats_update_begin(&sq->stats.syncp); + sq->stats.kicks++; + u64_stats_update_end(&sq->stats.syncp); + } + + en_dev->netdev->stats.tx_packets++; + en_dev->netdev->stats.tx_bytes += pktLen; + LOG_INFO("en_dev->netdev->stats.tx_packets=%ld, tx pktLen=%d\n", en_dev->netdev->stats.tx_packets, pktLen); + + return 0; + +err1: + free_pages((uint64_t)pkt.buf, 4); +err: + return -1; +} + +int32_t zxdh_send_file_pkt(struct net_device *netdev, struct ifreq *ifr) +{ + struct zxdh_en_priv *en_priv = NULL; + struct zxdh_en_reg *reg = NULL; + uint32_t size = sizeof(struct zxdh_en_reg); + int32_t ret = 0; + + CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n"); + CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n"); + + en_priv = netdev_priv(netdev); + CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n"); + + reg = kzalloc(size, GFP_KERNEL); + CHECK_EQUAL_ERR(reg, NULL, -EADDRNOTAVAIL, "reg is null!\n"); + + if (copy_from_user(reg, ifr->ifr_ifru.ifru_data, size)) + { + LOG_ERR("copy_from_user failed\n"); + ret = -EFAULT; + goto err_ret; + } + + if ((reg->num == 0) || (reg->num > MAX_ACCESS_NUM)) + { + LOG_ERR("transmit failed, reg->num=%d\n", reg->num); + ret = -EFAULT; + goto err_ret; + } + + ret = zxdh_tx_file_pkts(en_priv, reg); + if (unlikely(ret != 0)) + { + LOG_ERR("transmit failed[ret = %d]!", ret); + ret = -1; + goto err_ret; + } + + reg->num = 0; + if (copy_to_user(ifr->ifr_ifru.ifru_data, reg, size)) + { + LOG_ERR("copy_to_user failed\n"); + ret = -EFAULT; + } + +err_ret: + kfree(reg); + return ret; +} + +#ifdef PTP_DRIVER_INTERFACE_EN +/* ptp发送加密报文时，需要调用使能函数进行使能 */ +extern int32_t enable_write_ts_to_fifo(struct zxdh_en_device *en_dev, uint32_t enable, uint32_t mac_number); +extern int32_t set_interrupt_capture_timer(struct zxdh_en_device *en_dev, uint32_t index); +extern int32_t zxdh_set_pps_selection(struct zxdh_en_device *en_dev, uint32_t pps_type, uint32_t selection); +extern int32_t zxdh_set_pd_detection(struct zxdh_en_device *en_dev, uint32_t pd_index, uint32_t pd_input1, uint32_t pd_input2); +extern int32_t zxdh_get_pd_value(struct zxdh_en_device *en_dev, uint32_t pd_index, uint32_t *pd_result); +#endif /* PTP_DRIVER_INTERFACE_EN */ +int32_t zxdh_en_enable_ptp_encrypted_msg(struct net_device *netdev, struct ifreq *ifr, struct zxdh_en_reg *reg) +{ + uint32_t reg_size = sizeof(struct zxdh_en_reg); + int32_t mac_num = 0; //0-2 + struct zxdh_en_priv *en_priv = NULL; + struct zxdh_en_device *en_dev = NULL; + uint32_t enable = 0; + int32_t ret = 0; + + LOG_INFO("enter in zxdh_en_enable_ptp_encrypted_msg\n"); + CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n"); + CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n"); + + en_priv = netdev_priv(netdev); + CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n"); + en_dev = &en_priv->edev; + + mac_num = zxdh_pf_macpcs_num_get(en_dev); + if (mac_num < 0) + { + LOG_ERR("get mac num %d err, its value should is 0-2!\n", mac_num); + goto err_ret; + } + + if (unlikely(copy_from_user(reg, ifr->ifr_ifru.ifru_data, reg_size))) + { + LOG_ERR("copy_from_user failed!\n"); + goto err_ret; + } + if (reg->num != 1) + { + LOG_ERR("Transmit failed[len = %d]!\n", reg->num); + goto err_ret; + } + + enable = reg->data[0]; + if ((enable != 0) && (enable != 1)) + { + LOG_ERR("Transmit failed[enable = %u]!\n", enable); + goto err_ret; + } + + LOG_INFO("enable = %u\n", enable); + +#ifdef PTP_DRIVER_INTERFACE_EN + /* 使能ptp加密报文发送接口 */ + ret = enable_write_ts_to_fifo(en_dev, enable, mac_num); + CHECK_UNEQUAL_ERR(ret, 0, -EFAULT, "enable ptp encrypted msg failed!!\n"); +#endif /* PTP_DRIVER_INTERFACE_EN */ + + reg->num = 0; + if (unlikely(copy_to_user(ifr->ifr_ifru.ifru_data, reg, reg_size))) + { + LOG_ERR("copy_to_user failed!\n"); + goto err_ret; + } + + return ret; + +err_ret: + return -1; +} + +int32_t zxdh_en_set_intr_capture_timer(struct net_device *netdev, struct ifreq *ifr, struct zxdh_en_reg *reg) +{ + u_int32_t index; + uint32_t reg_size = sizeof(struct zxdh_en_reg); + struct zxdh_en_priv *en_priv = NULL; + struct zxdh_en_device *en_dev = NULL; + int32_t ret = 0; + + CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n"); + CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n"); + + en_priv = netdev_priv(netdev); + CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n"); + en_dev = &en_priv->edev; + + if (reg->num != 1) + { + LOG_ERR("Transmit failed[len = %d]!", reg->num); + goto err_ret; + } + + index = reg->data[0]; + LOG_INFO("index = %d\n", index); + if (index > 4) + { + LOG_ERR("capture timer out of range!"); + goto err_ret; + } +#ifdef PTP_DRIVER_INTERFACE_EN + ret = set_interrupt_capture_timer(en_dev, index); + CHECK_UNEQUAL_ERR(ret, 0, -EFAULT, "set interrupt capture timer failed!!\n"); +#endif /* PTP_DRIVER_INTERFACE_EN */ + + reg->num = 0; + if (unlikely(copy_to_user(ifr->ifr_ifru.ifru_data, reg, reg_size))) + { + LOG_ERR("copy_to_user failed!!!\n"); + goto err_ret; + } + + return ret; + +err_ret: + return -1; + +} + +int32_t zxdh_en_set_pps_selection(struct net_device *netdev, struct ifreq *ifr, struct zxdh_en_reg *reg) +{ + uint32_t pps_type; + uint32_t selection; + uint32_t reg_size = sizeof(struct zxdh_en_reg); + struct zxdh_en_priv *en_priv = NULL; + struct zxdh_en_device *en_dev = NULL; + int32_t ret = 0; + + CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n"); + CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n"); + + en_priv = netdev_priv(netdev); + CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n"); + en_dev = &en_priv->edev; + + if (reg->num != 2) + { + LOG_ERR("Transmit failed[len = %d]!", reg->num); + goto err_ret; + } + + pps_type = reg->data[0]; + selection = reg->data[1]; + LOG_INFO("pps_type = %u, selection = %u\n", pps_type, selection); +#ifdef PTP_DRIVER_INTERFACE_EN + ret = zxdh_set_pps_selection(en_dev, pps_type, selection); + CHECK_UNEQUAL_ERR(ret, 0, -EFAULT, "set pps selection failed!!\n"); +#endif /* PTP_DRIVER_INTERFACE_EN */ + + reg->num = 0; + if (unlikely(copy_to_user(ifr->ifr_ifru.ifru_data, reg, reg_size))) + { + LOG_ERR("copy_to_user failed!!!\n"); + goto err_ret; + } + + return ret; + +err_ret: + return -1; +} + +int32_t zxdh_en_set_phase_detection(struct net_device *netdev, struct ifreq *ifr, struct zxdh_en_reg *reg) +{ + uint32_t pd_index; + uint32_t pd_input1; + uint32_t pd_input2; + uint32_t reg_size = sizeof(struct zxdh_en_reg); + struct zxdh_en_priv *en_priv = NULL; + struct zxdh_en_device *en_dev = NULL; + int32_t ret = 0; + + CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n"); + CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n"); + + en_priv = netdev_priv(netdev); + CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n"); + en_dev = &en_priv->edev; + + if (reg->num != 3) + { + LOG_ERR("Transmit failed[len = %d]!", reg->num); + goto err_ret; + } + + pd_index = reg->data[0]; + pd_input1 = reg->data[1]; + pd_input2 = reg->data[2]; + LOG_INFO("pd_index = %u, pd_input1 = %u, pd_input2 = %u\n", pd_index, pd_input1, pd_input2); +#ifdef PTP_DRIVER_INTERFACE_EN + ret = zxdh_set_pd_detection(en_dev, pd_index, pd_input1, pd_input2); + CHECK_UNEQUAL_ERR(ret, 0, -EFAULT, "set pd detection failed!!\n"); +#endif /* PTP_DRIVER_INTERFACE_EN */ + + reg->num = 0; + if (unlikely(copy_to_user(ifr->ifr_ifru.ifru_data, reg, reg_size))) + { + LOG_ERR("copy_to_user failed!!!\n"); + goto err_ret; + } + + return ret; + +err_ret: + return -1; +} + +int32_t zxdh_en_get_pd_value(struct net_device *netdev, struct ifreq *ifr, struct zxdh_en_reg *reg) +{ + uint32_t pd_index; + uint32_t pd_result; + uint32_t reg_size = sizeof(struct zxdh_en_reg); + struct zxdh_en_priv *en_priv = NULL; + struct zxdh_en_device *en_dev = NULL; + int32_t ret = 0; + + CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n"); + CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n"); + + en_priv = netdev_priv(netdev); + CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n"); + en_dev = &en_priv->edev; + + if (reg->num != 1) + { + LOG_ERR("Transmit failed[len = %d]!", reg->num); + goto err_ret; + } + + pd_index = reg->data[0]; + LOG_INFO("pd_index = %u\n", pd_index); +#ifdef PTP_DRIVER_INTERFACE_EN + ret = zxdh_get_pd_value(en_dev, pd_index, &pd_result); + CHECK_UNEQUAL_ERR(ret, 0, -EFAULT, "get pd value failed!!\n"); +#endif /* PTP_DRIVER_INTERFACE_EN */ + + reg->num = 1; + reg->data[0] = pd_result; + if (unlikely(copy_to_user(ifr->ifr_ifru.ifru_data, reg, reg_size))) + { + LOG_ERR("copy_to_user failed!!!\n"); + goto err_ret; + } + + return ret; + +err_ret: + return -1; +} + +int32_t zxdh_en_set_l2_ptp_port(struct net_device *netdev, struct ifreq *ifr, struct zxdh_en_reg *reg) +{ + uint32_t reg_size = sizeof(struct zxdh_en_reg); + struct zxdh_en_priv *en_priv = NULL; + struct zxdh_en_device *en_dev = NULL; + int32_t ret = 0; + DPP_PF_INFO_T pf_info = {0}; + + CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n"); + CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n"); + + en_priv = netdev_priv(netdev); + CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n"); + en_dev = &en_priv->edev; + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + + LOG_INFO("reg->num: %d", reg->num); + LOG_INFO("reg->offset: %d", reg->offset); + if (reg->num != 1) + { + LOG_ERR("Transmit failed[len = %d]!", reg->num); + goto err_ret; + } + + en_dev->vf_1588_call_np_num = PTP_PORT_VFID_SET; + LOG_INFO("en_dev->vport: 0x%x, IS_PF(en_dev->vport): %d", en_dev->vport, IS_PF(en_dev->vport)); + if (IS_PF(en_dev->vport)) + { + ret = dpp_ptp_port_vfid_set(&pf_info, VQM_VFID(en_dev->vport)); + if (ret != 0) + { + LOG_ERR("dpp_ptp_port_vfid_set failed!!!\n"); + goto err_ret; + } + } + else + { + ret = zxdh_vf_1588_call_np_interface(en_dev); + if (ret != 0) + { + LOG_ERR("zxdh_vf_1588_call_np_interface failed!!!\n"); + goto err_ret; + } + } + + reg->num = 0; + if (unlikely(copy_to_user(ifr->ifr_ifru.ifru_data, reg, reg_size))) + { + LOG_ERR("copy_to_user failed!!!\n"); + goto err_ret; + } + LOG_INFO("dpp_ptp_port_vfid_set success"); + + return ret; + +err_ret: + return -1; +} + +int32_t zxdh_en_set_ptp_tc_enable(struct net_device *netdev, struct ifreq *ifr, struct zxdh_en_reg *reg) +{ + uint32_t reg_size = sizeof(struct zxdh_en_reg); + struct zxdh_en_priv *en_priv = NULL; + struct zxdh_en_device *en_dev = NULL; + int32_t ret = 0; + DPP_PF_INFO_T pf_info = {0}; + + CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n"); + CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n"); + + en_priv = netdev_priv(netdev); + CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n"); + en_dev = &en_priv->edev; + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + + if (reg->num != 1) + { + LOG_ERR("Transmit failed[len = %d]!", reg->num); + goto err_ret; + } + + en_dev->ptp_tc_enable_opt = reg->data[0]; + LOG_INFO("en_dev->ptp_tc_enable_opt = %u\n", en_dev->ptp_tc_enable_opt); + + en_dev->vf_1588_call_np_num = PTP_TC_ENABLE_SET; + + if (IS_PF(en_dev->vport)) + { + ret = dpp_ptp_tc_enable_set(&pf_info, en_dev->ptp_tc_enable_opt); + if (ret != 0) + { + LOG_ERR("dpp_ptp_tc_enable_set failed!!!\n"); + goto err_ret; + } + } + else + { + ret = zxdh_vf_1588_call_np_interface(en_dev); + if (ret != 0) + { + LOG_ERR("zxdh_vf_1588_call_np_interface failed!!!\n"); + goto err_ret; + } + } + + reg->num = 0; + if (unlikely(copy_to_user(ifr->ifr_ifru.ifru_data, reg, reg_size))) + { + goto err_ret; + } + + return ret; + +err_ret: + return -1; +} + +int32_t zxdh_en_set_synce_recovery_port(struct net_device *netdev, struct ifreq *ifr, struct zxdh_en_reg *reg) +{ + uint32_t reg_size = sizeof(struct zxdh_en_reg); + struct zxdh_en_priv *en_priv = NULL; + struct zxdh_en_device *en_dev = NULL; + int32_t ret = 0; + union zxdh_msg msg = {0}; + int32_t err = 0; + + CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n"); + CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n"); + + en_priv = netdev_priv(netdev); + CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n"); + en_dev = &en_priv->edev; + + if (reg->num != 1) + { + LOG_ERR("Transmit failed[len = %d]!", reg->num); + goto err_ret; + } + + msg.payload.hdr_to_agt.op_code = AGENT_MAC_RECOVERY_CLK_SET; + msg.payload.hdr_to_agt.phyport = en_dev->phy_port; + msg.payload.synce_clk_recovery_port.clk_speed = reg->data[0]; + LOG_INFO("phyport = %u, clk_speed = %u\n", msg.payload.hdr_to_agt.phyport, msg.payload.synce_clk_recovery_port.clk_speed); + err = zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &msg); + if (err != 0) + { + LOG_ERR("zxdh_en_set_synce_recovery_port failed, err: %d\n", err); + return err; + } + + reg->num = 0; + if (unlikely(copy_to_user(ifr->ifr_ifru.ifru_data, reg, reg_size))) + { + goto err_ret; + } + + return ret; + +err_ret: + return -1; +} + +int32_t zxdh_en_get_synce_clk_stats(struct net_device *netdev, struct ifreq *ifr, struct zxdh_en_reg *reg) +{ + uint32_t reg_size = sizeof(struct zxdh_en_reg); + struct zxdh_en_priv *en_priv = NULL; + struct zxdh_en_device *en_dev = NULL; + int32_t ret = 0; + union zxdh_msg msg = {0}; + int32_t err = 0; + + CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n"); + CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n"); + + en_priv = netdev_priv(netdev); + CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n"); + en_dev = &en_priv->edev; + + if (reg->num != 1) + { + LOG_ERR("Transmit failed[len = %d]!", reg->num); + goto err_ret; + } + + msg.payload.hdr_to_agt.op_code = AGENT_MAC_SYNCE_CLK_STATS_GET; + msg.payload.hdr_to_agt.phyport = en_dev->phy_port; + LOG_INFO("phyport = %u\n", msg.payload.hdr_to_agt.phyport); + err = zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &msg); + if (err != 0) + { + LOG_ERR("zxdh_en_get_synce_clk_stats failed, err: %d\n", err); + return err; + } + + reg->num = 1; + reg->data[0] = msg.reps.synce_clk_recovery_port.clk_stats; + if (unlikely(copy_to_user(ifr->ifr_ifru.ifru_data, reg, reg_size))) + { + goto err_ret; + } + LOG_INFO("num = %u, clk_stats: 0x%x\n", reg->num, reg->data[0]); + + return ret; + +err_ret: + return -1; +} + +int32_t zxdh_en_set_spm_port_tstamp_enable(struct net_device *netdev, struct ifreq *ifr, struct zxdh_en_reg *reg) +{ + uint32_t reg_size = sizeof(struct zxdh_en_reg); + struct zxdh_en_priv *en_priv = NULL; + struct zxdh_en_device *en_dev = NULL; + int32_t ret = 0; + union zxdh_msg msg = {0}; + int32_t err = 0; + + CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n"); + CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n"); + + en_priv = netdev_priv(netdev); + CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n"); + en_dev = &en_priv->edev; + + if (reg->num != 2) + { + LOG_ERR("Transmit failed[len = %d]!", reg->num); + goto err_ret; + } + + msg.payload.hdr_to_agt.op_code = AGENT_MAC_PORT_TSTAMP_ENABLE_SET; + msg.payload.hdr_to_agt.phyport = en_dev->phy_port; // 0~9 + msg.payload.mac_tstamp_msg.tx_enable = reg->data[0]; + msg.payload.mac_tstamp_msg.rx_enable = reg->data[1]; + LOG_INFO("phyport = %u, tx_enable: %u, rx_enable: %u\n", msg.payload.hdr_to_agt.phyport, msg.payload.mac_tstamp_msg.tx_enable, msg.payload.mac_tstamp_msg.rx_enable); + err = zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &msg); + if (err != 0) + { + LOG_ERR("zxdh_en_set_spm_port_tstamp_enable failed, err: %d\n", err); + return err; + } + + reg->num = 0; + if (unlikely(copy_to_user(ifr->ifr_ifru.ifru_data, reg, reg_size))) + { + goto err_ret; + } + + return ret; + +err_ret: + return -1; +} + +int32_t zxdh_en_get_spm_port_tstamp_enable(struct net_device *netdev, struct ifreq *ifr, struct zxdh_en_reg *reg) +{ + uint32_t reg_size = sizeof(struct zxdh_en_reg); + struct zxdh_en_priv *en_priv = NULL; + struct zxdh_en_device *en_dev = NULL; + int32_t ret = 0; + union zxdh_msg msg = {0}; + int32_t err = 0; + + CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n"); + CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n"); + + en_priv = netdev_priv(netdev); + CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n"); + en_dev = &en_priv->edev; + + msg.payload.hdr_to_agt.op_code = AGENT_MAC_PORT_TSTAMP_ENABLE_GET; + msg.payload.hdr_to_agt.phyport = en_dev->phy_port; // 0~9 + LOG_INFO("phyport = %u\n", msg.payload.hdr_to_agt.phyport); + err = zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &msg); + if (err != 0) + { + LOG_ERR("zxdh_en_get_spm_port_tstamp_enable failed, err: %d\n", err); + return err; + } + + reg->num = 2; + reg->data[0] = msg.reps.mac_tstamp_msg.tx_enable; + reg->data[1] = msg.reps.mac_tstamp_msg.rx_enable; + LOG_INFO("tx_enable: %u, rx_enable: %u\n", msg.reps.mac_tstamp_msg.tx_enable, msg.reps.mac_tstamp_msg.rx_enable); + + if (unlikely(copy_to_user(ifr->ifr_ifru.ifru_data, reg, reg_size))) + { + goto err_ret; + } + + return ret; + +err_ret: + return -1; +} + +int32_t zxdh_en_set_spm_port_tstamp_mode(struct net_device *netdev, struct ifreq *ifr, struct zxdh_en_reg *reg) +{ + uint32_t reg_size = sizeof(struct zxdh_en_reg); + struct zxdh_en_priv *en_priv = NULL; + struct zxdh_en_device *en_dev = NULL; + int32_t ret = 0; + union zxdh_msg msg = {0}; + int32_t err = 0; + + CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n"); + CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n"); + + en_priv = netdev_priv(netdev); + CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n"); + en_dev = &en_priv->edev; + + if (reg->num != 2) + { + LOG_ERR("Transmit failed[len = %d]!", reg->num); + goto err_ret; + } + + msg.payload.hdr_to_agt.op_code = AGENT_MAC_PORT_TSTAMP_MODE_SET; + msg.payload.hdr_to_agt.phyport = en_dev->phy_port;// 0~9 + msg.payload.mac_tstamp_msg.tx_mode = reg->data[0]; + msg.payload.mac_tstamp_msg.rx_mode = reg->data[1]; + LOG_INFO("phyport = %u, tx_mode: %u, rx_mode: %u\n", msg.payload.hdr_to_agt.phyport, msg.payload.mac_tstamp_msg.tx_mode, msg.payload.mac_tstamp_msg.rx_mode); + err = zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &msg); + if (err != 0) + { + LOG_ERR("zxdh_en_set_spm_port_tstamp_mode failed, err: %d\n", err); + return err; + } + + reg->num = 0; + if (unlikely(copy_to_user(ifr->ifr_ifru.ifru_data, reg, reg_size))) + { + goto err_ret; + } + + return ret; + +err_ret: + return -1; +} + +int32_t zxdh_en_get_spm_port_tstamp_mode(struct net_device *netdev, struct ifreq *ifr, struct zxdh_en_reg *reg) +{ + uint32_t reg_size = sizeof(struct zxdh_en_reg); + struct zxdh_en_priv *en_priv = NULL; + struct zxdh_en_device *en_dev = NULL; + union zxdh_msg msg = {0}; + int32_t err = 0; + + CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n"); + CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n"); + + en_priv = netdev_priv(netdev); + CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n"); + en_dev = &en_priv->edev; + + msg.payload.hdr_to_agt.op_code = AGENT_MAC_PORT_TSTAMP_MODE_GET; + msg.payload.hdr_to_agt.phyport = en_dev->phy_port;// 0~9 + LOG_INFO("phyport = %u\n", msg.payload.hdr_to_agt.phyport); + err = zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &msg); + if (err != 0) + { + LOG_ERR("zxdh_en_get_spm_port_tstamp_mode failed, err: %d\n", err); + return err; + } + + reg->num = 2; + reg->data[0] = msg.reps.mac_tstamp_msg.tx_mode; + reg->data[1] = msg.reps.mac_tstamp_msg.rx_mode; + LOG_INFO("tx_mode: %u, rx_mode: %u\n", msg.reps.mac_tstamp_msg.tx_mode, msg.reps.mac_tstamp_msg.rx_mode); + + if (unlikely(copy_to_user(ifr->ifr_ifru.ifru_data, reg, reg_size))) + { + goto err_ret; + } + + return 0; + +err_ret: + return -1; +} + +/* 配置时延测量功能是否打开, 维测功能 */ +int32_t zxdh_en_set_delay_statistics_enable(struct net_device *netdev, struct ifreq *ifr, struct zxdh_en_reg *reg) +{ + uint32_t reg_size = sizeof(struct zxdh_en_reg); + struct zxdh_en_priv *en_priv = NULL; + struct zxdh_en_device *en_dev = NULL; + int32_t ret = 0; + + CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n"); + CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n"); + + en_priv = netdev_priv(netdev); + CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n"); + en_dev = &en_priv->edev; + + if (reg->num != 1) + { + LOG_ERR("Transmit failed[len = %d]!", reg->num); + goto err_ret; + } + + en_dev->delay_statistics_enable = reg->data[0]; + LOG_INFO("en_dev->delay_statistics_enable = %u\n", en_dev->delay_statistics_enable); + + reg->num = 0; + if (unlikely(copy_to_user(ifr->ifr_ifru.ifru_data, reg, reg_size))) + { + goto err_ret; + } + + return ret; + +err_ret: + return -1; +} + +int32_t zxdh_en_get_delay_statistics_value(struct net_device *netdev, struct ifreq *ifr, struct zxdh_en_reg *reg) +{ + uint32_t reg_size = sizeof(struct zxdh_en_reg); + struct zxdh_en_priv *en_priv = NULL; + struct zxdh_en_device *en_dev = NULL; + int32_t ret = 0; + union zxdh_msg msg = {0}; + + CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n"); + CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n"); + + en_priv = netdev_priv(netdev); + CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n"); + en_dev = &en_priv->edev; + + msg.payload.hdr_to_agt.op_code = AGENT_MAC_PORT_DELAY_VALUE_GET; + msg.payload.hdr_to_agt.phyport = en_dev->phy_port;// 0~9 + LOG_INFO("phyport = %u\n", msg.payload.hdr_to_agt.phyport); + ret = zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &msg); + if (ret != 0) + { + LOG_ERR("zxdh_en_get_delay_statistics_value failed, ret: %d\n", ret); + return ret; + } + + reg->num = 4; + reg->data[0] = (uint32_t)(msg.reps.delay_statistics_val.min_delay & 0xffffffff); + reg->data[1] = (uint32_t)((msg.reps.delay_statistics_val.min_delay >> 32) & 0xffffffff); + reg->data[2] = (uint32_t)(msg.reps.delay_statistics_val.max_delay & 0xffffffff); + reg->data[3] = (uint32_t)((msg.reps.delay_statistics_val.max_delay >> 32) & 0xffffffff); + LOG_INFO("delay val: min_delay: %llu, max_delay: %llu\n", msg.reps.delay_statistics_val.min_delay, \ + msg.reps.delay_statistics_val.max_delay); + if (unlikely(copy_to_user(ifr->ifr_ifru.ifru_data, reg, reg_size))) + { + goto err_ret; + } + + return 0; + +err_ret: + return -1; +} + +int32_t zxdh_en_clear_delay_statistics_value(struct net_device *netdev, struct ifreq *ifr, struct zxdh_en_reg *reg) +{ + uint32_t reg_size = sizeof(struct zxdh_en_reg); + struct zxdh_en_priv *en_priv = NULL; + struct zxdh_en_device *en_dev = NULL; + int32_t ret = 0; + union zxdh_msg msg = {0}; + + CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n"); + CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n"); + + en_priv = netdev_priv(netdev); + CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n"); + en_dev = &en_priv->edev; + + msg.payload.hdr_to_agt.op_code = AGENT_MAC_PORT_DELAY_VALUE_CLR; + msg.payload.hdr_to_agt.phyport = en_dev->phy_port;// 0~9 + LOG_INFO("phyport = %u\n", msg.payload.hdr_to_agt.phyport); + ret = zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &msg); + if (ret != 0) + { + LOG_ERR("zxdh_en_clear_delay_statistics_value failed, ret: %d\n", ret); + return ret; + } + + reg->num = 0; + if (unlikely(copy_to_user(ifr->ifr_ifru.ifru_data, reg, reg_size))) + { + goto err_ret; + } + + return 0; + +err_ret: + return -1; +} + +struct zxdh_en_ptp_ioctl_table ioctl_ptp_table[] = +{ + {PTP_SET_CLOCK_NO, zxdh_en_set_clock_no}, + {PTP_ENABLE_PTP_ENCRYPTED_MSG, zxdh_en_enable_ptp_encrypted_msg}, + {PTP_SET_INTR_CAPTURE_TIMER, zxdh_en_set_intr_capture_timer}, + {PTP_SET_PP1S_SELECTION, zxdh_en_set_pps_selection}, + {PTP_SET_PHASE_DETECTION, zxdh_en_set_phase_detection}, + {PTP_GET_PD_VALUE, zxdh_en_get_pd_value}, + {PTP_SET_L2PTP_PORT, zxdh_en_set_l2_ptp_port}, + {PTP_SET_PTP_EC_ENABLE, zxdh_en_set_ptp_tc_enable}, + {PTP_SET_SYNCE_CLK_PORT, zxdh_en_set_synce_recovery_port}, + {PTP_GET_SYNCE_CLK_STATS, zxdh_en_get_synce_clk_stats}, + {PTP_SET_SPM_PORT_TSTAMP_ENABLE, zxdh_en_set_spm_port_tstamp_enable}, + {PTP_GET_SPM_PORT_TSTAMP_ENABLE, zxdh_en_get_spm_port_tstamp_enable}, + {PTP_SET_SPM_PORT_TSTAMP_MODE, zxdh_en_set_spm_port_tstamp_mode}, + {PTP_GET_SPM_PORT_TSTAMP_MODE, zxdh_en_get_spm_port_tstamp_mode}, + {PTP_SET_DELAY_STATISTICS_ENABLE, zxdh_en_set_delay_statistics_enable}, + {PTP_GET_DELAY_STATISTICS_VALUE, zxdh_en_get_delay_statistics_value}, + {PTP_CLR_DELAY_STATISTICS_VALUE, zxdh_en_clear_delay_statistics_value} +}; + +int32_t ptp_table_match_func(struct net_device *netdev, struct ifreq *ifr, struct zxdh_en_reg *reg) +{ + uint32_t i = 0; + uint32_t ret = 0; + uint32_t table_size = sizeof(ioctl_ptp_table) / sizeof(struct zxdh_en_ioctl_table); + for(i = 0; i < table_size; i++) + { + if((reg->offset == ioctl_ptp_table[i].cmd) && (ioctl_ptp_table[i].func != NULL)) + { + ret = ioctl_ptp_table[i].func(netdev, ifr, reg); + break; + } + } + return ret; +} + +int32_t zxdh_en_ptp_func(struct net_device *netdev, struct ifreq *ifr) +{ + struct zxdh_en_reg *reg = NULL; + uint32_t reg_size = sizeof(struct zxdh_en_reg); + + CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n"); + CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n"); + + reg = kzalloc(reg_size, GFP_KERNEL); + CHECK_EQUAL_ERR(reg, NULL, -EADDRNOTAVAIL, "reg is null!\n"); + + if (unlikely(copy_from_user(reg, ifr->ifr_ifru.ifru_data, reg_size))) + { + LOG_ERR("copy_from_user failed!\n"); + goto err_ret; + } + + if(-1 == ptp_table_match_func(netdev, ifr, reg)) + { + LOG_ERR("ptp_table_match_func failed!\n"); + goto err_ret; + } + + kfree(reg); + return 0; + +err_ret: + kfree(reg); + return -1; +} + +int32_t zxdh_en_pps_func(struct net_device *netdev, struct ifreq *ifr) +{ + struct zxdh_en_priv *en_priv = NULL; + struct zxdh_en_device *en_dev = NULL; + struct dh_core_dev *dh_dev = NULL; + struct zxdh_pf_device *pf_dev = NULL; + struct dh_eq_table *table = NULL; + struct dh_pf_eq_table *table_priv = NULL; + uint64_t virtaddr = 0x0; + struct dh_irq *expps = NULL; + struct dh_irq *lopps = NULL; + union zxdh_msg msg = {0}; + int32_t err = 0; + + CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n"); + CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n"); + + en_priv = netdev_priv(netdev); + en_dev = &en_priv->edev; + dh_dev = en_dev->parent->parent; + pf_dev = dh_core_priv(dh_dev); + + table = &dh_dev->eq_table; + table_priv = table->priv; + + LOG_ERR("pf_dev->pci_ioremap_addr[0]: 0x%llx\n", pf_dev->pci_ioremap_addr[0]); + + virtaddr = pf_dev->pci_ioremap_addr[0] + ZXDH_BAR_MSG_OFFSET; + tod_device_set_bar_virtual_addr(virtaddr, pf_dev->pcie_id); + + expps = table_priv->async_irq_tbl[3]; + lopps = table_priv->async_irq_tbl[4]; + + msg.payload.msg_pps.pcieid = pf_dev->pcie_id; + msg.payload.msg_pps.extern_pps_vector = expps->index; + msg.payload.msg_pps.local_pps_vector = lopps->index; + err = zxdh_send_command_to_specify(en_dev, MODULE_PPS, &msg, &msg); + if (err != 0) + { + LOG_ERR("zxdh_en_pps_func failed, err: %d\n", err); + return err; + } + + return 0; +} + +#ifdef ZXDH_MSGQ +int32_t zxdh_msgq_msg_send(struct net_device *netdev, struct ifreq *ifr) +{ + struct zxdh_en_device *en_dev = NULL; + struct msgq_dev *msgq_dev = NULL; + struct zxdh_en_reg *reg = NULL; + struct msgq_pkt_info pkt_info = {0}; + uint32_t size = sizeof(struct zxdh_en_reg); + struct reps_info reps = {0}; + uint32_t loop_cnt = 0; + uint32_t i = 0; + int32_t err = -2; + uint64_t start_us = 0; + uint64_t end_us = 0; + + CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n"); + CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n"); + en_dev = netdev_priv(netdev); + CHECK_EQUAL_ERR(en_dev, NULL, -EADDRNOTAVAIL, "en_dev is null!\n"); + msgq_dev = (struct msgq_dev *)en_dev->msgq_dev; + CHECK_EQUAL_ERR(msgq_dev, NULL, -EADDRNOTAVAIL, "msgq_dev is null!\n"); + + reg = kzalloc(size, GFP_KERNEL); + CHECK_EQUAL_ERR(reg, NULL, -EADDRNOTAVAIL, "reg is null!\n"); + + if (unlikely(copy_from_user(reg, ifr->ifr_ifru.ifru_data, size))) + { + LOG_ERR("copy_from_user failed!\n"); + goto err_ret; + } + + pkt_info.event_id = MODULE_DEMO; + pkt_info.timeout_us = 500000; + pkt_info.len = reg->data[0] + PRIV_HEADER_LEN; + pkt_info.no_reps = (reg->data[1] == 0) ? false : true; + loop_cnt = reg->data[2]; + if (loop_cnt == 0) + { + goto err_ret; + } + + if (loop_cnt > 100000000) + { + loop_cnt = 100000000; + } + + reps.len = 14000; + reps.addr = vmalloc(reps.len); + if (reps.addr == NULL) + { + LOG_ERR("vmalloc failed!\n"); + goto err_ret; + } + + LOG_DEBUG("len: %d, no_reps: %d, loop_cnt: %d\n", \ + pkt_info.len, pkt_info.no_reps, loop_cnt); + + start_us = jiffies_to_usecs(jiffies); + for (i = 0; i < loop_cnt; ++i) + { + pkt_info.addr = kzalloc(pkt_info.len, GFP_KERNEL); + if(pkt_info.addr == NULL) + { + err = -3; + break; + }; + err = zxdh_msgq_send_cmd(msgq_dev, &pkt_info, &reps); + } + + end_us = jiffies_to_usecs(jiffies); + if (i != 0) + { + LOG_DEBUG("exec_time: %lld us, single_time: %lld us\n", \ + end_us- start_us, (end_us- start_us) / i); + } + + reg->num = -err; + if (unlikely(copy_to_user(ifr->ifr_ifru.ifru_data, reg, size))) + { + LOG_ERR("copy_to_user failed!\n"); + } + + if (pkt_info.is_async && !pkt_info.no_reps) + { + usleep_range(pkt_info.timeout_us, pkt_info.timeout_us + 100); + } + + vfree(reps.addr); +err_ret: + kfree(reg); + return err; +} + +int32_t zxdh_msgq_dev_config(struct net_device *netdev, struct ifreq *ifr) +{ + uint32_t reg_size = sizeof(struct zxdh_en_reg); + struct zxdh_en_device *en_dev = NULL; + struct msgq_dev *msgq_dev = NULL; + struct zxdh_en_reg *reg = NULL; + + CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n"); + CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n"); + en_dev = netdev_priv(netdev); + CHECK_EQUAL_ERR(en_dev, NULL, -EADDRNOTAVAIL, "en_dev is null!\n"); + msgq_dev = (struct msgq_dev *)en_dev->msgq_dev; + CHECK_EQUAL_ERR(msgq_dev, NULL, -EADDRNOTAVAIL, "msgq_dev is null!\n"); + + reg = kzalloc(reg_size, GFP_KERNEL); + CHECK_EQUAL_ERR(reg, NULL, -EADDRNOTAVAIL, "reg is null!\n"); + + if (unlikely(copy_from_user(reg, ifr->ifr_ifru.ifru_data, reg_size))) + { + LOG_ERR("copy_from_user failed!\n"); + goto err_ret; + } + + if (reg->data[1] == MSGQ_PRINT_STA) + { + LOG_DEBUG("msgq_rx_pkts: %lld\n", msgq_dev->rq_priv->stats.packets); + LOG_DEBUG("msgq_rx_kicks: %lld\n", msgq_dev->rq_priv->stats.kicks); + LOG_DEBUG("msgq_rx_bytes: %lld\n", msgq_dev->rq_priv->stats.bytes); + LOG_DEBUG("msgq_rx_drops: %lld\n", msgq_dev->rq_priv->stats.drops); + LOG_DEBUG("msgq_rx_errs: %lld\n", msgq_dev->rq_priv->stats.xdp_drops); + + LOG_DEBUG("msgq_tx_pkts: %lld\n", msgq_dev->sq_priv->stats.packets); + LOG_DEBUG("msgq_tx_bytes: %lld\n", msgq_dev->sq_priv->stats.bytes); + LOG_DEBUG("msgq_tx_kicks: %lld\n", msgq_dev->sq_priv->stats.kicks); + LOG_DEBUG("msgq_tx_timeouts: %lld\n", msgq_dev->sq_priv->stats.tx_timeouts); + LOG_DEBUG("msgq_tx_errs: %lld\n", msgq_dev->sq_priv->stats.xdp_tx_drops); + + kfree(reg); + return 0; + } + + msgq_dev->loopback = (reg->data[0] != 0 ? true : false); + msgq_dev->print_flag = reg->data[1]; + LOG_INFO("msgq_dev->print_flag = %d\n", msgq_dev->print_flag); + LOG_INFO("msgq_dev->loopback = %d\n", msgq_dev->loopback); + + if (unlikely(copy_to_user(ifr->ifr_ifru.ifru_data, reg, reg_size))) + { + LOG_ERR("copy_to_user failed!\n"); + goto err_ret; + } + + kfree(reg); + return 0; + +err_ret: + kfree(reg); + return -1; +} +#endif + +struct zxdh_en_ioctl_table ioctl_table[] = +{ + {SIOCGMIIREG, zxdh_read_reg_cmd}, + {SIOCSMIIREG, zxdh_write_reg_cmd}, + {SIOCDEVPRIVATE_VQ_INFO, zxdh_get_vring_info}, + {SIOCDEVPRIVATE_SEND_FILE_PKT, zxdh_send_file_pkt}, +#ifdef ZXDH_MSGQ + {SIOCDEVPRIVATE_MSGQ_SNED, zxdh_msgq_msg_send}, + {SIOCDEVPRIVATE_MSGQ_CONFIG, zxdh_msgq_dev_config}, +#endif + {SIOCDEVPRIVATE_PTP_FUNC, zxdh_en_ptp_func}, + {SIOCDEVPRIVATE_PPS_FUNC, zxdh_en_pps_func}, + {SIOCDEVPRIVATE_TSN_FUNC, zxdh_en_tsn_func}, + {SIOCDEVPRIVATE_DH_TOOLS, zxdh_tools_ioctl_dispatcher}, +}; + +int32_t ioctl_table_match_func(struct net_device *netdev, struct ifreq *ifr, int32_t cmd, + struct zxdh_en_ioctl_table *func_table, uint32_t table_size) +{ + int32_t ret = 0; + uint32_t i = 0; + + CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n"); + for (i = 0; i < table_size; i++) + { + if ((func_table[i].cmd == cmd) && (func_table[i].func != NULL)) + { + ret = func_table[i].func(netdev, ifr); + break; + } + } + + return ret; +} + +int32_t zxdh_en_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) +{ + uint32_t table_size = sizeof(ioctl_table) / sizeof(struct zxdh_en_ioctl_table); + + return ioctl_table_match_func(netdev, ifr, cmd, ioctl_table, table_size); +} diff --git a/src/net/drivers/net/ethernet/dinghai/en_aux/en_ioctl.h b/src/net/drivers/net/ethernet/dinghai/en_aux/en_ioctl.h new file mode 100644 index 0000000..1b2e5c4 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_aux/en_ioctl.h @@ -0,0 +1,101 @@ +#ifndef _EN_IOCTL_H_ +#define _EN_IOCTL_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "../en_aux.h" + +#define SIOCDEVPRIVATE_WRITE_MAC (SIOCDEVPRIVATE + 1) +#define SIOCDEVPRIVATE_VQ_INFO (SIOCDEVPRIVATE + 2) +#define SIOCDEVPRIVATE_MSGQ_SNED (SIOCDEVPRIVATE + 3) +#define SIOCDEVPRIVATE_MSGQ_CONFIG (SIOCDEVPRIVATE + 4) +#define SIOCDEVPRIVATE_SEND_FILE_PKT (SIOCDEVPRIVATE + 6) +#define SIOCDEVPRIVATE_PTP_FUNC (SIOCDEVPRIVATE + 9) +#define SIOCDEVPRIVATE_PPS_FUNC (SIOCDEVPRIVATE + 10) +#define SIOCDEVPRIVATE_TSN_FUNC (SIOCDEVPRIVATE + 11) +#define SIOCDEVPRIVATE_DH_TOOLS (SIOCDEVPRIVATE + 13) + +#define PTP_SET_CLOCK_NO (0) +#define PTP_ENABLE_PTP_ENCRYPTED_MSG (1) +#define PTP_SET_INTR_CAPTURE_TIMER (2) +#define PTP_SET_PP1S_SELECTION (3) +#define PTP_SET_PHASE_DETECTION (4) +#define PTP_GET_PD_VALUE (5) +#define PTP_SET_L2PTP_PORT (6) +#define PTP_SET_PTP_EC_ENABLE (7) +#define PTP_SET_SYNCE_CLK_PORT (8) +#define PTP_GET_SYNCE_CLK_STATS (9) +#define PTP_SET_SPM_PORT_TSTAMP_ENABLE (10) +#define PTP_GET_SPM_PORT_TSTAMP_ENABLE (11) +#define PTP_SET_SPM_PORT_TSTAMP_MODE (12) +#define PTP_GET_SPM_PORT_TSTAMP_MODE (13) +#define PTP_SET_DELAY_STATISTICS_ENABLE (14) +#define PTP_GET_DELAY_STATISTICS_VALUE (15) +#define PTP_CLR_DELAY_STATISTICS_VALUE (16) + +#define PI_HDR_MAX_NUM 128 +#define GET_LOW32 0x00000000ffffffff +#define MIN_ALIGN_BYTE 64 +#define SEND_PKT_CNT_MAX 0xffffffff +#define PKT_PRINT_LINE_LEN 16 +#define PKT_PRINT_LEN_MAX (16 * 1024) + +#define CONFIG_RISC_PCS_LOOPB_OPCODE 13 +#define CONFIG_RISC_PCS_NORMAL_OPCODE 14 + +#define MSG_MODULE_DEBUG_RISC 20 + +#define MAX_ACCESS_NUM 500 +struct zxdh_en_reg +{ + uint32_t offset; + uint32_t num; + uint32_t data[MAX_ACCESS_NUM]; +}; + +struct risc_config_mac_msg +{ + uint8_t op_code; + uint8_t phyport; + uint8_t spm_speed; + uint8_t spm_fec; + uint8_t loop_enable; +}; + +struct risc_config_userspace +{ + uint8_t op_code; + uint8_t arg_num; + uint8_t filestr_size; + uint8_t file[100]; +}; + +struct data_packet +{ + void *buf; + uint32_t buf_size; +}; + +struct zxdh_en_ioctl_table +{ + int32_t cmd; + int32_t (*func)(struct net_device *netdev, struct ifreq *ifr); +}; + +struct zxdh_en_ptp_ioctl_table +{ + int32_t cmd; + int32_t (*func)(struct net_device *netdev, struct ifreq *ifr, struct zxdh_en_reg *reg); +}; + +int32_t print_data(uint8_t *data, uint32_t len); +int32_t zxdh_en_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/src/net/drivers/net/ethernet/dinghai/en_aux/eq.c b/src/net/drivers/net/ethernet/dinghai/en_aux/eq.c new file mode 100644 index 0000000..e63fb8d --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_aux/eq.c @@ -0,0 +1,333 @@ +#include +#include +#include +#include "eq.h" + +static int32_t dh_eq_async_link_info_int_bond_pf(struct notifier_block *nb, unsigned long action, void *data) +{ + struct dh_eq_async *eq_link_info_async = container_of(nb, struct dh_eq_async, irq_nb); + struct zxdh_en_priv *en_priv = (struct zxdh_en_priv *)eq_link_info_async->priv; + struct zxdh_en_device *en_dev = &en_priv->edev; + uint8_t link_up = 0; + uint8_t link_info = 0; + uint8_t bit_value = 0; + + if (en_dev == NULL) + { + LOG_ERR("null ptr\n"); + return -1; + } + + if(!en_dev->ops->is_bond(en_dev->parent)) + { + LOG_INFO("isn't bond_pf exit\n"); + return 0; + } + + //读取state寄存器中第en_dev->link_check_bit位的值 + en_dev->ops->get_link_info_from_vqm(en_dev->parent, &link_info); + bit_value = (link_info >> en_dev->link_check_bit) & 0x01; + LOG_INFO("[aux level] netdev:%s read VQM[0x%x]: link_check_bit[%d]-bit_value[%d]\n", en_dev->netdev->name, link_info, en_dev->link_check_bit, bit_value); + link_up |= bit_value; + + en_dev->link_up = link_up; + queue_work(en_priv->events->wq, &en_dev->link_info_irq_update_np_work); + + if(link_up == 0) + { + netif_carrier_off(en_dev->netdev); + en_dev->speed = SPEED_UNKNOWN; + en_dev->duplex = DUPLEX_UNKNOWN; + } + else + { + netif_carrier_on(en_dev->netdev); + queue_work(en_priv->events->wq, &en_dev->link_info_irq_process_work); + } + + return 0; +} + +static int32_t dh_eq_async_link_info_int(struct notifier_block *nb, unsigned long action, void *data) +{ + struct dh_eq_async *eq_link_info_async = container_of(nb, struct dh_eq_async, irq_nb); + struct zxdh_en_priv *en_priv = (struct zxdh_en_priv *)eq_link_info_async->priv; + struct zxdh_en_device *en_dev = &en_priv->edev; + uint8_t link_up = 0; + uint8_t link_info = 0; + uint8_t phyport_val = 0; + + //判断是否为bond_pf + if (en_dev == NULL) + { + LOG_ERR("null ptr\n"); + return -1; + } + + if(en_dev->ops->is_bond(en_dev->parent)) + { + LOG_INFO("is bond_pf, exit\n"); + return 0; + } + + if(en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_VF && (en_dev->device_id==0x8042)) + { + //调用读取state后四位获取phoport、读取前四位，获取link_up信息 + en_dev->ops->get_link_info_from_vqm(en_dev->parent, &link_info); + link_up = link_info & 0x0F; + phyport_val = (link_info >> 4) & 0x0F; + LOG_INFO("[bond_vf netdev %s] read VQM[0x%x]: phyport[0x%x] link_up[%d]\n", en_dev->netdev->name, link_info, phyport_val, link_up); + en_dev->phy_port = phyport_val; + } + else + { + en_dev->ops->get_link_info_from_vqm(en_dev->parent, &link_up); + } + + en_dev->link_up = link_up; + queue_work(en_priv->events->wq, &en_dev->link_info_irq_update_np_work); + if(link_up == 0) + { + en_dev->ops->set_pf_link_up(en_dev->parent, FALSE); + netif_carrier_off(en_dev->netdev); + en_dev->speed = SPEED_UNKNOWN; + en_dev->duplex = DUPLEX_UNKNOWN; + } + else + { + en_dev->ops->set_pf_link_up(en_dev->parent, TRUE); + netif_carrier_on(en_dev->netdev); + queue_work(en_priv->events->wq, &en_dev->link_info_irq_process_work); + } + + if(en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) + { + LOG_INFO("pf update all vf\n"); + queue_work(en_priv->events->wq, &en_dev->link_info_irq_update_vf_work); + } + return 0; +} + +static int32_t dh_eq_async_riscv_int(struct notifier_block *nb, unsigned long action, void *data) +{ + struct dh_eq_async * eq_riscv_async = container_of(nb, struct dh_eq_async, irq_nb); + struct zxdh_en_priv *en_priv = (struct zxdh_en_priv *)eq_riscv_async->priv; + struct zxdh_en_device *en_dev = &en_priv->edev; + struct dh_eq_table *eq_table = &en_priv->eq_table; + struct dh_events *events = en_priv->events; + struct dh_event_nb *event_nb = NULL; + uint64_t virt_addr = 0; + int32_t event_type = 0; + uint16_t event_idx = 0; + uint16_t i = 0; + + if(en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_VF) + { + return 0; + } + + virt_addr = en_dev->ops->get_bar_virt_addr(en_dev->parent, 0) + ZXDH_BAR_MSG_OFFSET; + event_idx = zxdh_get_event_id(virt_addr, MSG_CHAN_END_RISC, MSG_CHAN_END_PF); + event_type = dh_eq_event_type_get(event_idx); + LOG_INFO("------------- event_idx: %d, event_type: %d------------\n", event_idx, event_type); + + if(events == NULL) + { + LOG_ERR("riscv_irq trigger, events is null\n"); + return 0; + } + + for (i = 0; i < events->evt_num; i++) + { + event_nb = &events->notifiers[i]; + + if (event_type == event_nb->nb.event_type) + { + LOG_INFO("en_aux async riscv irq_handler called\n"); + atomic_notifier_call_chain(&eq_table->nh[event_type], event_type, NULL); + return 0; + } + } + + return 0; +} + +static int32_t dh_eq_async_pf_int(struct notifier_block *nb, unsigned long action, void *data) +{ + struct dh_eq_async * eq_pf_async = container_of(nb, struct dh_eq_async, irq_nb); + struct zxdh_en_priv *en_priv = (struct zxdh_en_priv *)eq_pf_async->priv; + struct zxdh_en_device *en_dev = &en_priv->edev; + struct dh_eq_table *eq_table = &en_priv->eq_table; + struct dh_events *events = en_priv->events; + struct dh_event_nb *event_nb = NULL; + uint64_t virt_addr = 0; + int32_t event_type = 0; + uint16_t event_idx = 0; + uint16_t i = 0; + + if(en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) + { + return 0; + } + + virt_addr = en_dev->ops->get_bar_virt_addr(en_dev->parent, 0) + ZXDH_BAR_MSG_OFFSET + ZXDH_BAR_PFVF_MSG_OFFSET; + event_idx = zxdh_get_event_id(virt_addr, MSG_CHAN_END_PF, MSG_CHAN_END_VF); + event_type = dh_eq_event_type_get(event_idx); + LOG_INFO("------------- event_idx: %d, event_type: %d------------\n", event_idx, event_type); + + for (i = 0; i < events->evt_num; i++) + { + event_nb = &events->notifiers[i]; + + if (event_type == event_nb->nb.event_type) + { + LOG_INFO("en_aux async pf irq_handler called\n"); + atomic_notifier_call_chain(&eq_table->nh[event_type], event_type, NULL); + return 0; + } + } + + return 0; +} + +struct dh_aux_async_eq_table +{ + char name[64]; + notifier_fn_t async_int; +}; + +static struct dh_aux_async_eq_table dh_aux_async_eq_tbl[] = +{ + {"riscv", dh_eq_async_riscv_int}, + {"pf", dh_eq_async_pf_int}, + {"link_info", dh_eq_async_link_info_int}, + {"link_info", dh_eq_async_link_info_int_bond_pf}, +}; + +static int32_t dh_aux_setup_async_eq(struct zxdh_en_priv *en_priv, \ + struct dh_eq_async *eq, const char *name, \ + notifier_fn_t call) +{ + struct zxdh_en_device *en_dev = &en_priv->edev; + int32_t err = 0; + + spin_lock_init(&eq->lock);//unused + eq->priv = en_priv; + eq->irq_nb.notifier_call = call; + err = en_dev->ops->async_eq_enable(en_dev->parent, eq, name, true); + if (err != 0) + { + LOG_ERR("failed to enable %s EQ %d\n", name, err); + } + + return err; +} + +static void cleanup_async_eq(struct zxdh_en_priv *en_priv, struct dh_eq_async *eq, const char *name) +{ + struct zxdh_en_device *en_dev = &en_priv->edev; + int32_t err = 0; + + err = en_dev->ops->async_eq_enable(en_dev->parent, eq, name, false); + if (err != 0) + { + LOG_ERR("failed to disable %s EQ %d\n", name, err); + } +} + +static void destroy_async_eqs(struct zxdh_en_priv *en_priv) +{ + struct dh_eq_table *table = &en_priv->eq_table; + struct dh_aux_eq_table *table_priv = table->priv; + int32_t i = 0; + + for (i = 0; i < ZXDH_AUX_ASYNC_EQ_NUM; ++i) + { + cleanup_async_eq(en_priv, &table_priv->async_eq_tbl[i], dh_aux_async_eq_tbl[i].name); + } +} + +void dh_aux_eq_table_destroy(struct zxdh_en_priv *en_priv) +{ + destroy_async_eqs(en_priv); +} + +void dh_aux_eq_table_cleanup(struct zxdh_en_priv *en_priv) +{ + kvfree(en_priv->eq_table.priv); +} + +int32_t dh_aux_eq_table_init(struct zxdh_en_priv *en_priv) +{ + struct dh_eq_table *eq_table; + struct dh_aux_eq_table *table_priv = NULL; + int32_t err = 0; + uint32_t i = 0; + + eq_table = &en_priv->eq_table; + + table_priv = kvzalloc(sizeof(*table_priv), GFP_KERNEL); + if (unlikely(table_priv == NULL)) + { + LOG_ERR("dh_aux_eq_table kvzalloc failed\n"); + err = -ENOMEM; + goto err_table_priv; + } + + eq_table->priv = table_priv; + + mutex_init(&eq_table->lock); + for (i = 0; i < DH_EVENT_TYPE_MAX; i++) + { + ATOMIC_INIT_NOTIFIER_HEAD(&eq_table->nh[i]); + } + + eq_table->irq_table = NULL; + + return 0; + +err_table_priv: + return err; +} + +static int32_t create_async_eqs(struct zxdh_en_priv *en_priv) +{ + struct dh_eq_table *eq_table = &en_priv->eq_table; + struct dh_aux_eq_table *table_priv = eq_table->priv; + int32_t err = 0; + int32_t i = 0; + int32_t j = 0; + + for (i = 0; i < ZXDH_AUX_ASYNC_EQ_NUM; ++i) + { + err = dh_aux_setup_async_eq(en_priv, &table_priv->async_eq_tbl[i], \ + dh_aux_async_eq_tbl[i].name, dh_aux_async_eq_tbl[i].async_int); + if (err != 0) + { + LOG_ERR("Failed to setup aux_async_eq_tbl[%d]\n", i); + goto err_setup_async_eq; + } + } + + return err; + +err_setup_async_eq: + for (j = 0; j < i; ++j) + { + cleanup_async_eq(en_priv, &table_priv->async_eq_tbl[j], dh_aux_async_eq_tbl[j].name); + } + return err; +} + +int32_t dh_aux_eq_table_create(struct zxdh_en_priv *en_priv) +{ + int32_t err = 0; + + err = create_async_eqs(en_priv); + if (err != 0) + { + LOG_ERR("Failed to create async EQs\n"); + } + + return err; +} diff --git a/src/net/drivers/net/ethernet/dinghai/en_aux/eq.h b/src/net/drivers/net/ethernet/dinghai/en_aux/eq.h new file mode 100644 index 0000000..c9d2444 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_aux/eq.h @@ -0,0 +1,24 @@ +#ifndef __DINGHAI_EN_AUX_EQ_H__ +#define __DINGHAI_EN_AUX_EQ_H__ + +#include "../en_aux.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define ZXDH_AUX_ASYNC_EQ_NUM 4 +struct dh_aux_eq_table { + struct dh_eq_async async_eq_tbl[ZXDH_AUX_ASYNC_EQ_NUM]; +}; + +int32_t dh_aux_eq_table_init(struct zxdh_en_priv *en_priv); +int32_t dh_aux_eq_table_create(struct zxdh_en_priv *en_priv); +void dh_aux_eq_table_destroy(struct zxdh_en_priv *en_priv); +void dh_aux_eq_table_cleanup(struct zxdh_en_priv *en_priv); + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_aux/events.c b/src/net/drivers/net/ethernet/dinghai/en_aux/events.c new file mode 100644 index 0000000..1dd5fee --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_aux/events.c @@ -0,0 +1,824 @@ +#include +#include +#include +#include +#include +#include +#include +#include "events.h" +#include "en_cmd.h" +#include "../msg_common.h" +#include "../en_np/table/include/dpp_tbl_api.h" +#include "../zxdh_tools/zxdh_tools_netlink.h" +#include "dcbnl/en_dcbnl_api.h" +#include "zxic_common.h" +#include +#include +#include +#include +#include +#include // 对于VLAN设备 +#include // 对于bonding设备 +#include + +static int32_t pf2vf_notifier(struct notifier_block *, unsigned long, void *); +static int32_t riscv2aux_notifier(struct notifier_block *, unsigned long, void *); + +void rx_mode_set_handler(struct work_struct *work); + +static struct dh_nb aux_events[] = { + {.nb.notifier_call = pf2vf_notifier, .event_type = DH_EVENT_TYPE_NOTIFY_PF_TO_VF}, + {.nb.notifier_call = riscv2aux_notifier, .event_type = DH_EVENT_TYPE_NOTIFY_RISCV_TO_AUX}, +}; + +static int32_t do_pf_vf_inet6_update_mac_to_np(struct zxdh_en_device *en_dev, const struct in6_addr *ipv6_addr, unsigned long action) +{ + int32_t ret = 0; + struct in6_addr sol_addr={0}; + uint8_t mcast_mac[ETH_ALEN]; + + // 打印IPv6地址，使用%pI6c格式化IPv6地址，确保正确显示 + LOG_INFO("IPv6 address changed on interface %s, %s address: %pI6c\n", + en_dev->netdev->name, (action == 1) ? "add" : (action == 2) ? "del" : "unknown action with", ipv6_addr); + // Calculate the multicast MAC address from the IPv6 address + addrconf_addr_solict_mult(ipv6_addr, &sol_addr); + ipv6_eth_mc_map(&sol_addr, mcast_mac); + LOG_INFO("Multicast MAC Address: %pM\n", mcast_mac); + + switch (action) { + case NETDEV_UP: + { + ret = zxdh_ip6mac_add(en_dev, ipv6_addr->s6_addr32, mcast_mac); + if (ret != 0) + { + LOG_ERR("zxdh_ip6mac_add failed"); + } + break; + } + case NETDEV_DOWN: + { + ret = zxdh_ip6mac_del(en_dev, ipv6_addr->s6_addr32, mcast_mac); + if (ret != 0) + { + LOG_ERR("zxdh_ip6mac_del failed"); + } + break; + } + default: + break; + } + return ret; +} + +static int32_t do_bond_master_inet6_update_mac_to_np(struct net_device *notifier_dev, const struct in6_addr *ipv6_addr, struct zxdh_en_device *en_dev, unsigned long action) +{ + int32_t ret = 0; + struct list_head *iter = NULL; + struct slave *slave_dev = NULL; + struct bonding *bond = netdev_priv(notifier_dev); + + // 遍历所有slave设备 + if (!bond_has_slaves(bond)) + { + LOG_INFO("Bond device %s don't have slave\n", notifier_dev->name); + return 0; + } + + bond_for_each_slave(bond, slave_dev, iter) + { + if (strcmp(en_dev->netdev->name, slave_dev->dev->name) != 0) + { + continue; + } + LOG_INFO("Bond device %s have slave device: %s\n", notifier_dev->name, slave_dev->dev->name); + ret = do_pf_vf_inet6_update_mac_to_np(en_dev, ipv6_addr, action); + if (ret != 0) + { + return ret; + } + } + return 0; +} + +static int32_t inet6_addr_change_notifier(struct notifier_block *nb, unsigned long action, void *data) +{ + struct inet6_ifaddr *ifa = NULL; + struct net_device *notifier_dev = NULL; //触发事件的网络设备 + struct zxdh_en_device *en_dev = container_of(nb, struct zxdh_en_device, ipv6_notifier); //处理此回调函数的设备 + + if(data == NULL) + { + LOG_ERR("data is NULL"); + return NOTIFY_OK; + } + + ifa = (struct inet6_ifaddr *)data; + notifier_dev = ifa->idev->dev; + + if (notifier_dev == NULL) + { + LOG_ERR("notifier_dev is NULL"); + return NOTIFY_OK; + } + + // 检查是否为vlan设备 + if (is_vlan_dev(notifier_dev)) + notifier_dev = vlan_dev_real_dev(notifier_dev); + + // 检查是否为bond master设备 + if (netif_is_bond_master(notifier_dev)) + return do_bond_master_inet6_update_mac_to_np(notifier_dev, &ifa->addr, en_dev, action); + + // 检查是否为自定义设备 + if (strcmp(en_dev->netdev->name, notifier_dev->name) == 0) + return do_pf_vf_inet6_update_mac_to_np(en_dev, &ifa->addr, action); + + return NOTIFY_OK; +} + +static void vf_link_info_update_handler(struct work_struct *_work) +{ + struct zxdh_en_device *en_dev = container_of(_work, struct zxdh_en_device, vf_link_info_update_work); + union zxdh_msg msg = {0}; + struct zxdh_vf_item *vf_item = NULL; + int32_t err = 0; + uint16_t vf_idx = 0; + struct pci_dev *pdev = NULL; + uint16_t num_vfs = 0; + bool pf_link_up = false; + + ZXDH_AUX_INIT_COMP_CHECK(en_dev); + pf_link_up = en_dev->ops->get_pf_link_up(en_dev->parent); + pdev = en_dev->ops->get_pdev(en_dev->parent); + num_vfs = pci_num_vf(pdev); + + msg.payload.hdr_vf.op_code = ZXDH_SET_VF_LINK_STATE; + msg.payload.link_state_msg.is_link_force_set = FALSE; + + msg.payload.link_state_msg.link_up = pf_link_up; + msg.payload.link_state_msg.speed = en_dev->speed; + msg.payload.link_state_msg.autoneg_enable = en_dev->autoneg_enable; + msg.payload.link_state_msg.supported_speed_modes = en_dev->supported_speed_modes; + msg.payload.link_state_msg.advertising_speed_modes = en_dev->advertising_speed_modes; + + for (vf_idx = 0; vf_idx < num_vfs; vf_idx++) + { + vf_item = en_dev->ops->get_vf_item(en_dev->parent, vf_idx); + msg.payload.hdr_vf.dst_pcie_id = FIND_VF_PCIE_ID(en_dev->pcie_id, vf_idx); + if(vf_item->is_probed) + { + msg.payload.link_state_msg.link_forced = vf_item->link_forced; + err = zxdh_send_command_to_specify(en_dev, MODULE_PF_BAR_MSG_TO_VF, &msg, &msg); + if (err != 0) + { + LOG_ERR("failed to update VF[%d]\n", vf_idx); + } + } + } +} + +static void link_info_irq_update_vf_handler(struct work_struct *_work) +{ + struct zxdh_en_device *en_dev = container_of(_work, struct zxdh_en_device, link_info_irq_update_vf_work); + struct zxdh_vf_item *vf_item = NULL; + int32_t err = 0; + uint16_t vf_idx = 0; + struct pci_dev *pdev = NULL; + uint16_t num_vfs = 0; + bool pf_link_up = en_dev->ops->get_pf_link_up(en_dev->parent); + uint16_t func_no = 0; + uint16_t pf_no = FIND_PF_ID(en_dev->pcie_id); + union zxdh_msg msg = {0}; + + LOG_INFO("is called\n"); + ZXDH_AUX_INIT_COMP_CHECK(en_dev); + msg.payload.hdr_to_agt.op_code = AGENT_DEV_STATUS_NOTIFY; + msg.payload.hdr_to_agt.pcie_id = en_dev->pcie_id; + pdev = en_dev->ops->get_pdev(en_dev->parent); + num_vfs = pci_num_vf(pdev); + for (vf_idx = 0; vf_idx < num_vfs; vf_idx++) + { + vf_item = en_dev->ops->get_vf_item(en_dev->parent, vf_idx); + if(vf_item->link_forced == FALSE && vf_item->is_probed) + { + func_no = GET_FUNC_NO(pf_no, vf_idx); + LOG_INFO("vf_idx:%d, func_no=0x%x\n",vf_idx,func_no); + msg.payload.pcie_msix_msg.func_no[msg.payload.pcie_msix_msg.num++] = func_no; + en_dev->ops->set_vf_link_info(en_dev->parent, vf_idx, pf_link_up ? 1 : 0); + } + } + LOG_INFO("msg.payload.pcie_msix_msg.num:%d\n",msg.payload.pcie_msix_msg.num); + if(msg.payload.pcie_msix_msg.num > 0) + { + err = zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &msg); + if (err != 0) + { + LOG_ERR("failed to update VF link info\n"); + } + } +} + +static void link_info_irq_process_handler(struct work_struct *_work) +{ + struct zxdh_en_device *en_dev = container_of(_work, struct zxdh_en_device, link_info_irq_process_work); + int32_t ret = 0; + union zxdh_msg msg = {0}; + struct link_info_struct link_info_val = {0}; + + ZXDH_AUX_INIT_COMP_CHECK(en_dev); + + msg.payload.hdr_to_agt.op_code = AGENT_MAC_LINK_INFO_GET; + msg.payload.hdr_to_agt.phyport = en_dev->phy_port; + ret = zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &msg); + if (ret != 0) + { + LOG_ERR("get speed and duplex from agent failed: %d\n", ret); + return; + } + en_dev->speed = msg.reps.mac_set_msg.speed; + en_dev->duplex = msg.reps.mac_set_msg.duplex; + LOG_DEBUG("netdev:%s, phy_port:0x%x, speed:%d, duplex:0x%x\n", en_dev->netdev->name, en_dev->phy_port, en_dev->speed, en_dev->duplex); + + if(en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) + { + link_info_val.speed = en_dev->speed; + link_info_val.autoneg_enable = en_dev->autoneg_enable; + link_info_val.supported_speed_modes = en_dev->supported_speed_modes; + link_info_val.advertising_speed_modes = en_dev->advertising_speed_modes; + link_info_val.duplex = en_dev->duplex; + + en_dev->ops->update_pf_link_info(en_dev->parent, &link_info_val); + + //zxdh_port_th_update(en_dev); + } + + return; +} + +static void link_info_irq_update_np_work_handler(struct work_struct *_work) +{ + struct zxdh_en_device *en_dev = container_of(_work, struct zxdh_en_device, link_info_irq_update_np_work); + DPP_PF_INFO_T pf_info = {0}; + + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + + ZXDH_AUX_INIT_COMP_CHECK(en_dev); + if (!en_dev->ops->is_bond(en_dev->parent)) + { + if (!netif_running(en_dev->netdev)) + { + return; + } + if(en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_VF) + { + zxdh_vf_egr_port_attr_set(en_dev, EGR_FLAG_VPORT_IS_UP, en_dev->link_up, 0); + } + else + { + dpp_egr_port_attr_set(&pf_info, EGR_FLAG_VPORT_IS_UP, en_dev->link_up); + } + return; + } + + if (!en_dev->link_up) + { + dpp_panel_attr_set(&pf_info, en_dev->phy_port, PANEL_FLAG_IS_UP, 0); + } + else + { + if (en_dev->netdev->flags & IFF_UP) + { + dpp_panel_attr_set(&pf_info, en_dev->phy_port, PANEL_FLAG_IS_UP, 1); + } + } +} + +static void en_aux_spoof_check(struct zxdh_en_device *en_dev) +{ + uint64_t ssvpc = 0; + uint16_t en_aux_pf_id = 0; + uint32_t ret = 0; + uint16_t num_vfs = 0; + struct pci_dev *pdev = NULL; + struct dh_core_dev *dh_dev = NULL; + DPP_PF_INFO_T pf_info = {0}; + + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + + dh_dev = en_dev->parent; + pdev = en_dev->ops->get_pdev(dh_dev); + num_vfs = pci_num_vf(pdev); + + if (!IS_PF(en_dev->vport)) + { + return; + } + if (num_vfs == 0) + { + return; + } + + en_aux_pf_id = DH_AUX_PF_ID_OFFSET(en_dev->vport); + // spoof static register clear to 0 after read + ret = dpp_stat_spoof_packet_drop_cnt_get(&pf_info, en_aux_pf_id, 1, &ssvpc); + if (ret != 0) + { + LOG_ERR("Failed to get spoof check dropped packets number.\n"); + return; + } + if (!ssvpc) + { + return; + } + LOG_INFO("%llu Spoofed packets detected in EP%d, PF%d\n", ssvpc, EPID(en_dev->vport), FUNC_NUM(en_dev->vport)); + return; +} + +static void en_aux_service_task(struct work_struct *_work) +{ + struct zxdh_en_device *en_dev = container_of(_work, struct zxdh_en_device, service_task); + + ZXDH_AUX_INIT_COMP_CHECK(en_dev); + en_aux_spoof_check(en_dev); +} + +static void en_aux_service_timer(struct timer_list *t) +{ + unsigned long next_event_offset = HZ * 2; + struct zxdh_en_device *en_dev = from_timer(en_dev, t, service_timer); + struct zxdh_en_priv *en_priv = container_of(en_dev, struct zxdh_en_priv, edev); + + /* Reset the timer */ + mod_timer(&en_dev->service_timer, next_event_offset + jiffies); + queue_work(en_priv->events->wq, &en_dev->service_task); +} + +static void en_aux_service_riscv_task(struct work_struct *_work) +{ + int32_t retval = 0; + union zxdh_msg msg = {0}; + + time64_t time64; + struct rtc_time tm; + unsigned long next_event_offset = HZ * 259200; + + struct zxdh_en_device *en_dev = container_of(_work, struct zxdh_en_device, service_riscv_task); + + if (!IS_PF(en_dev->vport)) + { + return; + } + + msg.payload.hdr_to_cmn.pcie_id = en_dev->pcie_id;; + msg.payload.hdr_to_cmn.write_bytes = 9; + msg.payload.hdr_to_cmn.type = RISC_SERVER_TIME; + msg.payload.hdr_to_cmn.field = 0; + + time64 = ktime_get_real_seconds(); + time64 += 28800;//CST比UST晚八个小时 + rtc_time64_to_tm(time64, &tm); + + msg.payload.time_cfg_msg.tmmng_type = 0xF0; + msg.payload.time_cfg_msg.dir = 0x2; + msg.payload.time_cfg_msg.year = tm.tm_year + 1900; + msg.payload.time_cfg_msg.month = tm.tm_mon + 1; + msg.payload.time_cfg_msg.day = tm.tm_mday; + msg.payload.time_cfg_msg.hour = tm.tm_hour; + msg.payload.time_cfg_msg.min = tm.tm_min; + msg.payload.time_cfg_msg.sec = tm.tm_sec; + + + LOG_INFO("send msg timer to riscv:%d-%d-%d %d:%d:%d\n", msg.payload.time_cfg_msg.year, msg.payload.time_cfg_msg.month, msg.payload.time_cfg_msg.day, msg.payload.time_cfg_msg.hour, msg.payload.time_cfg_msg.min, msg.payload.time_cfg_msg.sec); + ZXDH_AUX_INIT_COMP_CHECK(en_dev); + + retval = zxdh_send_command_to_specify(en_dev, MODULE_PF_TIMER_TO_RISC_MSG, &msg, &msg); + if (retval != 0) + { + LOG_ERR("zxdh_send_command_to_riscv failed: %d\n", retval); + } + + mod_timer(&en_dev->service_riscv_timer, next_event_offset + jiffies); +} + +static void en_aux_service_riscv_timer(struct timer_list *t) +{ + unsigned long next_event_offset = HZ * 60; + struct zxdh_en_device *en_dev = from_timer(en_dev, t, service_riscv_timer); + struct zxdh_en_priv *en_priv = container_of(en_dev, struct zxdh_en_priv, edev); + + /* Reset the timer */ + mod_timer(&en_dev->service_riscv_timer, next_event_offset + jiffies); + queue_work(en_priv->events->wq, &en_dev->service_riscv_task); +} + +static void pf2vf_msg_proc_work_handler(struct work_struct *_work) +{ + struct zxdh_en_device *en_dev = container_of(_work, struct zxdh_en_device, pf2vf_msg_proc_work); + uint64_t virt_addr = 0; + + LOG_INFO("is called\n"); + ZXDH_AUX_INIT_COMP_CHECK(en_dev); + virt_addr = en_dev->ops->get_bar_virt_addr(en_dev->parent, 0) + ZXDH_BAR_MSG_OFFSET + ZXDH_BAR_PFVF_MSG_OFFSET; + zxdh_bar_irq_recv(MSG_CHAN_END_PF, MSG_CHAN_END_VF, virt_addr, en_dev); +} + +static int32_t pf2vf_notifier(struct notifier_block *nb, unsigned long type, void *data) +{ + struct dh_event_nb *event_nb = dh_nb_cof(nb, struct dh_event_nb, nb); + struct zxdh_en_priv *en_priv = (struct zxdh_en_priv *)event_nb->ctx; + + LOG_INFO("is called\n"); + queue_work(en_priv->events->wq, &en_priv->edev.pf2vf_msg_proc_work); + + return NOTIFY_OK; +} + +static void riscv2aux_msg_proc_work_handler(struct work_struct *_work) +{ + struct zxdh_en_device *en_dev = container_of(_work, struct zxdh_en_device, riscv2aux_msg_proc_work); + uint64_t virt_addr = 0; + uint16_t src = MSG_CHAN_END_RISC; + uint16_t dst = MSG_CHAN_END_PF; + + LOG_INFO("is called\n"); + ZXDH_AUX_INIT_COMP_CHECK(en_dev); + virt_addr = en_dev->ops->get_bar_virt_addr(en_dev->parent, 0) + ZXDH_BAR_MSG_OFFSET; + zxdh_bar_irq_recv(src, dst, virt_addr, en_dev); +} + +static int32_t riscv2aux_notifier(struct notifier_block *nb, unsigned long type, void *data) +{ + struct dh_event_nb *event_nb = dh_nb_cof(nb, struct dh_event_nb, nb); + struct zxdh_en_priv *en_priv = (struct zxdh_en_priv *)event_nb->ctx; + LOG_INFO("is called\n"); + queue_work(en_priv->events->wq, &en_priv->edev.riscv2aux_msg_proc_work); + + return NOTIFY_OK; +} + +void pf_notify_vf_reset_handler(struct work_struct *work) +{ + int32_t ret = 0; + struct zxdh_en_device *en_dev = container_of(work, struct zxdh_en_device, pf_notify_vf_reset_work); + struct net_device *netdev = en_dev->netdev; + + LOG_INFO("pf_notify_vf_reset_handler is called\n"); + ZXDH_AUX_INIT_COMP_CHECK(en_dev); + ret = zxdh_vf_get_mac(netdev); + if (ret != 0) + { + LOG_ERR("zxdh_vf_get_mac failed: %d\n", ret); + } +} + +typedef uint32_t (*zxdh_pf_msg_func)(zxdh_msg_info *msg, zxdh_reps_info *reps, struct zxdh_en_device *en_dev); + +typedef struct +{ + zxdh_msg_op_code op_code; + uint8_t proc_name[ZXDH_MSG_TYPE_CNT_MAX]; + zxdh_pf_msg_func msg_proc; +} zxdh_pf_msg_proc; + +static uint32_t zxdh_set_vf_link_state(zxdh_msg_info *msg, zxdh_reps_info *reps, struct zxdh_en_device *en_dev) +{ + uint32_t ret = 0; + uint16_t vf_idx = msg->hdr_vf.dst_pcie_id & (0xff); + + if(!msg->link_state_msg.is_link_force_set) + { + en_dev->speed = msg->link_state_msg.speed; + en_dev->autoneg_enable = msg->link_state_msg.autoneg_enable; + en_dev->supported_speed_modes = msg->link_state_msg.supported_speed_modes; + en_dev->advertising_speed_modes = msg->link_state_msg.advertising_speed_modes; + if(msg->link_state_msg.link_forced) + { + return 0; + } + } + + en_dev->ops->set_pf_link_up(en_dev->parent, msg->link_state_msg.link_up); + if(en_dev->ops->get_pf_link_up(en_dev->parent)) + { + netif_carrier_on(en_dev->netdev); + } + else + { + netif_carrier_off(en_dev->netdev); + } + LOG_INFO("[VF GET MSG FROM PF]--VF[%d] link_state[%s] update success!\n", vf_idx, en_dev->ops->get_pf_link_up(en_dev->parent)?"TRUE":"FALSE"); + return ret; +} + +static uint32_t zxdh_set_vf_reset(zxdh_msg_info *msg, zxdh_reps_info *reps, struct zxdh_en_device *en_dev) +{ + struct zxdh_en_priv *en_priv = netdev_priv(en_dev->netdev); + queue_work(en_priv->events->wq, &en_priv->edev.pf_notify_vf_reset_work); + return 0; +} + +static uint32_t zxdh_set_vf_vlan(zxdh_msg_info *msg, zxdh_reps_info *reps, struct zxdh_en_device *edev) +{ + uint32_t ret = 0; + /* update local var*/ + edev->vlan_dev.vlan_id = msg->vf_vlan_msg.vlan_id; + edev->vlan_dev.qos = msg->vf_vlan_msg.qos; + edev->vlan_dev.protcol = msg->vf_vlan_msg.protocl; + + return ret; +} + +static uint32_t zxdh_pf_get_vf_queue(zxdh_msg_info *msg, zxdh_reps_info *reps, struct zxdh_en_device *edev) +{ + uint32_t ret = 0; + uint32_t vir_queue_start; + uint32_t vir_queue_num; + uint32_t queue_index; + uint32_t queue_num; + uint32_t max_queue_num = edev->curr_queue_pairs; + + PLCR_LOG_INFO("vf's edev->vport = 0x%x\n", edev->vport); + PLCR_LOG_INFO("vf's max_queue_num(pairs) = 0x%x\n", max_queue_num); + PLCR_LOG_INFO("edev->device_id = %x\n", edev->device_id); + PLCR_LOG_INFO("edev->rq[0].vq->phy_index = %x\n", edev->rq[0].vq->phy_index); + PLCR_LOG_INFO("edev->sq[0].vq->phy_index = %x\n", edev->sq[0].vq->phy_index); + + vir_queue_start = msg->plcr_pf_get_vf_queue_info_msg.vir_queue_start; + vir_queue_num = msg->plcr_pf_get_vf_queue_info_msg.vir_queue_num; + + PLCR_LOG_INFO("vir_queue_start = 0x%x\n", vir_queue_start); + PLCR_LOG_INFO("vir_queue_num = 0x%x\n", vir_queue_num); + + if(max_queue_num > (vir_queue_num + vir_queue_num)) + { + max_queue_num = vir_queue_num + vir_queue_num; + } + + for(queue_index=vir_queue_start, queue_num = 0; queue_indexplcr_pf_get_vf_queue_info_rsp.phy_rxq[queue_num] = edev->rq[queue_num].vq->phy_index; + reps->plcr_pf_get_vf_queue_info_rsp.phy_txq[queue_num] = edev->sq[queue_num].vq->phy_index; + } + + reps->plcr_pf_get_vf_queue_info_rsp.phy_queue_num = queue_num; + + PLCR_LOG_INFO("queue_num = 0x%x\n", queue_num); + + return ret; +} + +zxdh_pf_msg_proc pf_msg_proc[] = +{ + {ZXDH_SET_VF_LINK_STATE, "set_vf_link_state", zxdh_set_vf_link_state}, + {ZXDH_SET_VF_RESET, "set_vf_reset", zxdh_set_vf_reset}, + {ZXDH_PF_SET_VF_VLAN, "pf_set_vf_vlan", zxdh_set_vf_vlan}, + {ZXDH_PF_GET_VF_QUEUE_INFO, "pf_get_vf_queue_info", zxdh_pf_get_vf_queue}, +}; + +int32_t zxdh_vf_msg_recv_func(void *pay_load, uint16_t len, void *reps_buffer, uint16_t *reps_len, void *dev) +{ + zxdh_msg_info *msg = (zxdh_msg_info *)pay_load; + zxdh_reps_info *reps = (zxdh_reps_info *)reps_buffer; + struct zxdh_en_device *en_dev = (struct zxdh_en_device *)dev; + int32_t ret = 0; + int32_t i = 0; + int32_t num = 0; + + LOG_INFO("is called\n"); + if (len != sizeof(union zxdh_msg)) + { + LOG_ERR("invalid data_len\n"); + return -1; + } + + if (en_dev == NULL) + { + LOG_ERR("dev is NULL\n"); + return -1; + } + + num = sizeof(pf_msg_proc)/sizeof(zxdh_pf_msg_proc); + + for (i = 0; i < num; i++) + { + *reps_len = sizeof(union zxdh_msg); + if (pf_msg_proc[i].op_code == msg->hdr_vf.op_code) + { + LOG_INFO("%s is called", pf_msg_proc[i].proc_name); + ret = pf_msg_proc[i].msg_proc(msg, reps, en_dev); + if (ret != 0) + { + reps->flag = ZXDH_REPS_FAIL; + LOG_ERR("%s failed, ret: %d\n", pf_msg_proc[i].proc_name, ret); + return -1; + } + reps->flag = ZXDH_REPS_SUCC; + return 0; + } + } + + LOG_ERR("invalid op_code: [%u]\n", msg->hdr_vf.op_code); + return -2; +} + +int32_t dh_aux_ipv6_notifier_init(struct zxdh_en_priv *en_priv) +{ + int32_t ret = 0; + struct zxdh_en_device *en_dev = &en_priv->edev; + en_dev->ipv6_notifier.notifier_call = inet6_addr_change_notifier; + en_dev->ipv6_notifier.priority = 0; + ret = dh_inet6_addr_change_notifier_register(&(en_dev->ipv6_notifier)); + if (ret) + { + LOG_ERR("Failed to register inet6addr_notifier, ret:%d\n",ret); + return ret; + } + LOG_INFO("netdev:%s ipv6_notifier_init success\n", en_dev->netdev->name); + return ret; +} + +int32_t dh_aux_events_init(struct zxdh_en_priv *en_priv) +{ + struct dh_events *events = NULL; + struct zxdh_en_device *en_dev = &en_priv->edev; + int32_t i = 0; + int32_t ret = 0; + uint32_t evt_num = ARRAY_SIZE(aux_events); + + if (!en_dev->ops->if_init(en_dev->parent)) + { + evt_num -= 1; + } + + events = kzalloc((sizeof(*events) + evt_num * sizeof(struct dh_event_nb)), GFP_KERNEL); + if (unlikely(events == NULL)) + { + LOG_ERR("events kzalloc failed: %p\n", events); + ret = -ENOMEM; + goto err_events_kzalloc; + } + + events->evt_num = evt_num; + events->dev = NULL; + en_priv->events = events; + events->wq = create_singlethread_workqueue("dh_aux_events"); + if (!events->wq) + { + LOG_ERR("events->wq create_singlethread_workqueue failed: %p\n", events->wq); + ret = -ENOMEM; + goto err_create_wq; + } + + INIT_WORK(&en_dev->vf_link_info_update_work, vf_link_info_update_handler); + INIT_WORK(&en_dev->link_info_irq_update_vf_work, link_info_irq_update_vf_handler); + INIT_WORK(&en_dev->link_info_irq_process_work, link_info_irq_process_handler); + INIT_WORK(&en_dev->link_info_irq_update_np_work, link_info_irq_update_np_work_handler); + INIT_WORK(&en_dev->rx_mode_set_work, rx_mode_set_handler); + INIT_WORK(&en_dev->pf2vf_msg_proc_work, pf2vf_msg_proc_work_handler); + INIT_WORK(&en_dev->pf_notify_vf_reset_work, pf_notify_vf_reset_handler); + INIT_WORK(&en_dev->service_task, en_aux_service_task); + INIT_WORK(&en_dev->service_riscv_task, en_aux_service_riscv_task); + INIT_WORK(&en_dev->riscv2aux_msg_proc_work, riscv2aux_msg_proc_work_handler); + + timer_setup(&en_dev->service_timer, en_aux_service_timer, 0); + ret = mod_timer(&en_dev->service_timer, jiffies); + if (ret) + { + LOG_ERR("timer add failed\n"); + goto err_mod_timer; + } + + timer_setup(&en_dev->service_riscv_timer, en_aux_service_riscv_timer, 0); + ret = mod_timer(&en_dev->service_riscv_timer, jiffies); + if (ret) + { + LOG_ERR("timer add failed\n"); + goto err_riscv_timer; + } + + for (i = 0; i < evt_num; i++) + { + events->notifiers[i].nb = aux_events[i]; + events->notifiers[i].ctx = en_priv; + dh_eq_notifier_register(&en_priv->eq_table, &events->notifiers[i].nb); + } + + return ret; + +err_riscv_timer: + del_timer(&en_dev->service_riscv_timer); +err_mod_timer: + del_timer(&en_dev->service_timer); + destroy_workqueue(events->wq); +err_create_wq: + kfree(events); +err_events_kzalloc: + return ret; +} + +void dh_aux_events_uninit(struct zxdh_en_priv *en_priv) +{ + struct dh_events *events = en_priv->events; + struct zxdh_en_device *en_dev = &en_priv->edev; + int32_t i = 0; + + for (i = events->evt_num - 1; i >= 0 ; i--) + { + dh_eq_notifier_unregister(&en_priv->eq_table, &events->notifiers[i].nb); + } + + del_timer(&en_dev->service_timer); + del_timer(&en_dev->service_riscv_timer); + destroy_workqueue(en_priv->events->wq); + kfree(en_priv->events); + + return; +} + +static int32_t mgr_test_cnt(void *data, uint16_t len, void *reps, uint16_t *reps_len, void *dev) +{ + uint8_t *pay_load = (uint8_t *)data; + uint8_t *reps_buffer = (uint8_t *)reps; + uint16_t idx = 0; + uint16_t sum = 0; + + if (reps_buffer == NULL) + { + return 0; + } + + for (idx = 0; idx < len; idx++) + { + sum += pay_load[idx]; + } + + reps_buffer[0] = (uint8_t)sum; + reps_buffer[1] = (uint8_t)(sum >> 8); + *reps_len = 2; + return 0; +} + +static int32_t msgq_test_func(void *data, uint16_t len, void *reps, uint16_t *reps_len, void *dev) +{ + if (reps == NULL) + { + return 0; + } + + *reps_len = len; + return 0; +} + +int32_t dh_aux_msg_recv_func_register(void) +{ + int32_t ret = 0; + + ret = zxdh_bar_chan_msg_recv_register(MODULE_PF_BAR_MSG_TO_VF, zxdh_vf_msg_recv_func); + if (0 != ret) + { + LOG_ERR("event_id[%d] register failed: %d\n", MODULE_PF_BAR_MSG_TO_VF, ret); + return ret; + } + + ret = zxdh_bar_chan_msg_recv_register(MODULE_DHTOOL, zxdh_tools_sendto_user_netlink); + if (0 != ret) + { + LOG_ERR("event_id[%d] register failed: %d\n", MODULE_DHTOOL, ret); + goto unregister_pf_to_vf; + } + + ret = zxdh_bar_chan_msg_recv_register(MODULE_DEMO, mgr_test_cnt); + if (0 != ret) + { + LOG_ERR("event_id[%d] register failed: %d\n", MODULE_MSGQ, ret); + goto unregister_dhtool; + } + + ret = zxdh_bar_chan_msg_recv_register(MODULE_MSGQ, msgq_test_func); + if (0 != ret) + { + LOG_ERR("event_id[%d] register failed: %d\n", MODULE_MSGQ, ret); + goto unregister_demo; + } + + return ret; +unregister_demo: + zxdh_bar_chan_msg_recv_unregister(MODULE_DEMO); +unregister_dhtool: + zxdh_bar_chan_msg_recv_unregister(MODULE_DHTOOL); +unregister_pf_to_vf: + zxdh_bar_chan_msg_recv_unregister(MODULE_PF_BAR_MSG_TO_VF); + return ret; +} + +void dh_aux_msg_recv_func_unregister(void) +{ + zxdh_bar_chan_msg_recv_unregister(MODULE_MSGQ); + zxdh_bar_chan_msg_recv_unregister(MODULE_DEMO); + zxdh_bar_chan_msg_recv_unregister(MODULE_DHTOOL); + zxdh_bar_chan_msg_recv_unregister(MODULE_PF_BAR_MSG_TO_VF); + return; +} diff --git a/src/net/drivers/net/ethernet/dinghai/en_aux/events.h b/src/net/drivers/net/ethernet/dinghai/en_aux/events.h new file mode 100644 index 0000000..5734856 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_aux/events.h @@ -0,0 +1,24 @@ +#ifndef __ZXDH_PF_EVENTS_H__ +#define __ZXDH_PF_EVENTS_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include "en_aux.h" +#include "../en_np/table/include/dpp_tbl_comm.h" + +#define DH_AUX_PF_ID_OFFSET(vport) (EPID(vport) * 8 + FUNC_NUM(vport)) + +int32_t dh_aux_events_init(struct zxdh_en_priv *en_priv); +void dh_aux_events_uninit(struct zxdh_en_priv *en_priv); +int32_t dh_aux_msg_recv_func_register(void); +void dh_aux_msg_recv_func_unregister(void); +int32_t dh_aux_ipv6_notifier_init(struct zxdh_en_priv *en_priv); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/en_aux/priv_queue.c b/src/net/drivers/net/ethernet/dinghai/en_aux/priv_queue.c new file mode 100644 index 0000000..e29058e --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_aux/priv_queue.c @@ -0,0 +1,812 @@ + +#include +#include +#include +#include +#include "priv_queue.h" + +static void poll_timer_callback(struct timer_list *this_timer) +{ + struct msgq_dev *msgq_dev = from_timer(msgq_dev, this_timer, poll_timer); + struct msg_buff *this_msg_buff = NULL; + uint16_t i = 0; + uint32_t tx_timeouts = 0; + + if (msgq_dev == NULL) + { + LOG_ERR("msgq_dev is NULL\n"); + return; + } + + for (i = 0; i < MSGQ_MAX_MSG_BUFF_NUM; ++i) + { + if (msgq_dev->free_cnt == 0) + { + msgq_dev->timer_in_use = false; + return; + } + this_msg_buff = &msgq_dev->msg_buff_ring[i]; + + if (!this_msg_buff->using || !this_msg_buff->need_free) + { + continue; + } + + if (this_msg_buff->timeout_cnt == 0) + { + *(this_msg_buff->data_len) = 0; + this_msg_buff->data = NULL; + msgq_dev->free_cnt--; + tx_timeouts++; + LOG_ERR("msg[%d] get callback out of time\n", i); + this_msg_buff->using = false; + continue; + } + this_msg_buff->timeout_cnt--; + } + + u64_stats_update_begin(&msgq_dev->sq_priv->stats.syncp); + msgq_dev->sq_priv->stats.tx_timeouts += tx_timeouts; + u64_stats_update_end(&msgq_dev->sq_priv->stats.syncp); + + mod_timer(this_timer, jiffies + msecs_to_jiffies(TIMER_DELAY_US)); +} + +static uint32_t msgq_get_mergeable_buf_len(struct receive_queue *rq, struct ewma_pkt_len *avg_pkt_len) +{ + const size_t hdr_len = PRIV_HEADER_LEN; + uint32_t len = 0; + + len = hdr_len + clamp_t(uint32_t, ewma_pkt_len_read(avg_pkt_len), rq->min_buf_len, PAGE_SIZE - hdr_len); + + return ALIGN(len, L1_CACHE_BYTES); +} + +static int32_t msgq_add_recvbuf_mergeable(struct receive_queue *rq, gfp_t gfp) +{ + struct page_frag *alloc_frag = &rq->alloc_frag; + char *buf = NULL; + void *ctx = NULL; + int32_t err = 0; + uint32_t len = 0; + uint32_t hole = 0; + + len = msgq_get_mergeable_buf_len(rq, &rq->mrg_avg_pkt_len); + if (unlikely(!skb_page_frag_refill(len, alloc_frag, gfp))) + { + return -ENOMEM; + } + + buf = (char *)page_address(alloc_frag->page) + alloc_frag->offset; + get_page(alloc_frag->page); + alloc_frag->offset += len; + hole = alloc_frag->size - alloc_frag->offset; + if (hole < len) + { + len += hole; + alloc_frag->offset += hole; + } + + sg_init_one(rq->sg, buf, len); + ctx = (void *)(unsigned long)len; + err = virtqueue_add_inbuf_ctx(rq->vq, rq->sg, 1, buf, ctx, gfp); + if (err < 0) + { + put_page(virt_to_head_page(buf)); + } + + return err; +} + +static bool msgq_try_fill_recv(struct receive_queue *rq, gfp_t gfp) +{ + int32_t err = 0; + bool oom = 0; + unsigned long flags = 0; + + do + { + err = msgq_add_recvbuf_mergeable(rq, gfp); + oom = err == -ENOMEM; + if (err) + { + break; + } + } while (rq->vq->num_free); + + if (virtqueue_kick_prepare_packed(rq->vq) && virtqueue_notify(rq->vq)) + { + flags = u64_stats_update_begin_irqsave(&rq->stats.syncp); + rq->stats.kicks++; + u64_stats_update_end_irqrestore(&rq->stats.syncp, flags); + } + + return !oom; +} + +uint32_t msgq_mergeable_min_buf_len(struct virtqueue *vq) +{ + const uint32_t hdr_len = PRIV_HEADER_LEN; + uint32_t rq_size = virtqueue_get_vring_size(vq); + uint32_t min_buf_len = DIV_ROUND_UP(BUFF_LEN, rq_size); + + return max(max(min_buf_len, hdr_len) - hdr_len, (uint32_t)GOOD_PACKET_LEN); +} + +static int32_t msgq_privq_init(struct msgq_dev *msgq_dev, struct net_device *netdev) +{ + struct receive_queue *rq = msgq_dev->rq_priv; + struct send_queue *sq = msgq_dev->sq_priv; + + rq->pages = NULL; + rq->min_buf_len = msgq_mergeable_min_buf_len(rq->vq); + netif_napi_add(netdev, &rq->napi, zxdh_msgq_poll, NAPI_POLL_WEIGHT); + netif_tx_napi_add(netdev, &sq->napi, NULL, NAPI_POLL_WEIGHT); + + sg_init_table(rq->sg, ARRAY_SIZE(rq->sg)); + ewma_pkt_len_init(&rq->mrg_avg_pkt_len); + sg_init_table(sq->sg, ARRAY_SIZE(sq->sg)); + + u64_stats_init(&rq->stats.syncp); + u64_stats_init(&sq->stats.syncp); + + if (!msgq_try_fill_recv(rq, GFP_KERNEL)) + { + LOG_ERR("msgq_try_fill_recv failed\n"); + ZXDH_FREE_PTR(msgq_dev); + return MSGQ_RET_ERR_CHANNEL_NOT_READY; + } + + msgq_dev->msgq_enable = true; + virtnet_napi_enable(rq->vq, &rq->napi); + LOG_INFO("zxdh_msgq_init success\n"); + return MSGQ_RET_OK; +} + +int32_t zxdh_msgq_init(struct zxdh_en_device *en_dev) +{ + struct msgq_dev *msgq_dev = NULL; + int32_t idx = 0; + DPP_PF_INFO_T pf_info = {0}; + + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + en_dev->msgq_dev = kzalloc(sizeof(struct msgq_dev), GFP_KERNEL); + ZXDH_CHECK_PTR_RETURN(en_dev->msgq_dev); + + idx = en_dev->max_queue_pairs - ZXDH_PQ_PAIRS_NUM; + msgq_dev = (struct msgq_dev *)en_dev->msgq_dev; + msgq_dev->sq_priv = &en_dev->sq[idx]; + msgq_dev->rq_priv = &en_dev->rq[idx]; + msgq_dev->msgq_vfid = (uint16_t)VQM_VFID(en_dev->vport); + msgq_dev->msgq_rqid = (uint16_t)msgq_dev->rq_priv->vq->phy_index; + + dpp_vport_create_by_vqm_vfid(&pf_info, RISCV_COMMON_VFID); + spin_lock_init(&msgq_dev->sn_lock); + spin_lock_init(&msgq_dev->tx_lock); + mutex_init(&msgq_dev->mlock); + timer_setup(&msgq_dev->poll_timer, poll_timer_callback, 0); + + return msgq_privq_init(msgq_dev, en_dev->netdev); +} + +void zxdh_msgq_exit(struct zxdh_en_device *en_dev) +{ + struct msgq_dev *msgq_dev = (struct msgq_dev *)en_dev->msgq_dev; + + if (msgq_dev == NULL) + { + LOG_ERR("msgq_dev is null!\n"); + return; + } + + msgq_dev->msgq_enable = false; + napi_disable(&msgq_dev->rq_priv->napi); + del_timer(&msgq_dev->poll_timer); + + ZXDH_FREE_PTR(msgq_dev); + LOG_INFO("zxdh_msg_chan_pkt remove success\n"); +} + +void msgq_print_data(uint8_t *buf, uint32_t len, uint8_t flag) +{ + uint32_t print_len = 0; + + if (flag == MSGQ_PRINT_HDR) + { + print_len = PRIV_HEADER_LEN; + } + else if (flag == MSGQ_PRINT_128B) + { + print_len = len > 128 ? 128 : len; + } + else if (flag == MSGQ_PRINT_ALL) + { + print_len = len; + } + print_data(buf, print_len); +} + +static int32_t zxdh_msg_para_check(struct msgq_pkt_info *msg, struct reps_info *reps) +{ + ZXDH_CHECK_PTR_RETURN(msg); + ZXDH_CHECK_PTR_RETURN(msg->addr); + + if ((msg->len == 0) || (msg->len > MSGQ_MAX_ADDR_LEN)) + { + LOG_ERR("invalid data_len: %d\n", msg->len); + goto free_addr; + } + + if (msg->event_id >= MSG_MODULE_NUM) + { + LOG_ERR("invalid event_id\n"); + goto free_addr; + } + + if (msg->no_reps) + { + return MSGQ_RET_OK; + } + + ZXDH_CHECK_PTR_GOTO_ERR(reps, free_addr); + ZXDH_CHECK_PTR_GOTO_ERR(reps->addr, free_addr); + if (reps->len == 0) + { + LOG_ERR("invalid reps_len: %d\n", reps->len); + goto free_addr; + } + + return MSGQ_RET_OK; +free_addr: + ZXDH_FREE_PTR(msg->addr); + return MSGQ_RET_ERR_INVALID_PARA; +} + +static int32_t zxdh_sequence_num_get(struct msgq_dev *msgq_dev, uint16_t *sequence_num) +{ + uint16_t sn = 0; + uint16_t loop = 0; + + spin_lock(&msgq_dev->sn_lock); + sn = msgq_dev->sequence_num; + + for (loop = 0; loop < MSGQ_MAX_MSG_BUFF_NUM; loop++) + { + if (!msgq_dev->msg_buff_ring[sn].using) + { + *sequence_num = sn; + msgq_dev->msg_buff_ring[sn].using = true; + msgq_dev->msg_buff_ring[sn].valid = false; + msgq_dev->free_cnt++; + SEQUENCE_NUM_ADD(sn); + break; + } + SEQUENCE_NUM_ADD(sn); + } + + msgq_dev->sequence_num = sn; + spin_unlock(&msgq_dev->sn_lock); + + if (loop == MSGQ_MAX_MSG_BUFF_NUM) + { + return MSGQ_RET_ERR_CHAN_BUSY; + } + + return MSGQ_RET_OK; +} + +static int32_t page_send_cmd(struct send_queue *sq, uint8_t *buf, uint16_t buf_len, uint8_t print) +{ + uint16_t i = 0; + int32_t err = 0; + uint16_t total_sg = 0; + uint16_t last_buff_len = 0; + + if (print != 0) + { + LOG_DEBUG("send pkt start\n"); + msgq_print_data(buf, buf_len, print); + } + + total_sg = buf_len / BUFF_LEN; + last_buff_len = buf_len % BUFF_LEN; + if (last_buff_len != 0) + { + total_sg += 1; + } + + sg_init_table(sq->sg, total_sg); + for (i = 0; i < total_sg; ++i) + { + if (i == (total_sg - 1)) + { + sg_set_buf(&sq->sg[i], buf + (i * BUFF_LEN), ((last_buff_len != 0) ? (last_buff_len) : (BUFF_LEN))); + } + else + { + sg_set_buf(&sq->sg[i], buf + (i * BUFF_LEN), BUFF_LEN); + } + } + + err = virtqueue_add_outbuf(sq->vq, sq->sg, total_sg, buf, GFP_ATOMIC); + ZXDH_CHECK_RET_GOTO_ERR(err, free_addr, "virtqueue_add_outbuf failed: %d\n", err); + + if (virtqueue_kick_prepare_packed(sq->vq) && virtqueue_notify(sq->vq)) + { + u64_stats_update_begin(&sq->stats.syncp); + sq->stats.kicks++; + u64_stats_update_end(&sq->stats.syncp); + } + return err; + +free_addr: + return MSGQ_RET_ERR_VQ_BROKEN; +} + +static int32_t zxdh_msgq_pkt_send(struct msgq_dev *msgq_dev, \ + struct msgq_pkt_info *pkt_info, uint16_t sn) +{ + struct priv_queues_net_hdr *hdr = (struct priv_queues_net_hdr *)pkt_info->addr; + void *buf = NULL; + uint32_t len = 0; + + if (spin_trylock(&msgq_dev->tx_lock)) + { + while ((buf = virtqueue_get_buf(msgq_dev->sq_priv->vq, &len)) != NULL) + { + ZXDH_FREE_PTR(buf); + }; + spin_unlock(&msgq_dev->tx_lock); + } + + memset(hdr, 0, PRIV_HEADER_LEN); + hdr->tx_port = TX_PORT_NP; + hdr->pd_len = PRIV_HEADER_LEN / 2; + hdr->pi_hdr.pi_type = DEFAULT_PI_TYPE; + hdr->pi_hdr.pkt_type = CONTROL_MSG_TYPE; + hdr->pi_hdr.vfid_dst = htons(RISCV_COMMON_VFID); + hdr->pi_hdr.qid_dst = htons(RISCV_COMMON_QID); + hdr->pi_hdr.vfid_src = htons(msgq_dev->msgq_vfid); + hdr->pi_hdr.qid_src = htons(msgq_dev->msgq_rqid); + hdr->pi_hdr.event_id = pkt_info->event_id; + hdr->pi_hdr.sequence_num = sn; + if (sn == NO_REPS_SEQUENCE_NUM) + { + hdr->pi_hdr.msg_type = NO_REPS_MSG; + } + if (msgq_dev->loopback) + { + hdr->pi_hdr.event_id = MODULE_MSGQ; + hdr->pi_hdr.vfid_dst = hdr->pi_hdr.vfid_src; + hdr->pi_hdr.qid_dst = hdr->pi_hdr.qid_src; + } + + return page_send_cmd(msgq_dev->sq_priv, pkt_info->addr, \ + pkt_info->len, msgq_dev->print_flag); +} + +int32_t zxdh_msgq_send_cmd(struct msgq_dev *msgq_dev, \ + struct msgq_pkt_info *pkt_info, struct reps_info *reps) +{ + uint16_t sn = NO_REPS_SEQUENCE_NUM; + uint16_t sync_poll_cnt = 0; + int32_t err = 0; + int32_t i = 0; + uint32_t tx_timeouts = 0; + uint32_t tx_errs = 0; + + err = zxdh_msg_para_check(pkt_info, reps); + ZXDH_CHECK_RET_GOTO_ERR(err, tx_err, "zxdh_msg_para_check failed: %d\n", err); + + ZXDH_CHECK_PTR_GOTO_ERR(msgq_dev, free_addr); + CHECK_CHANNEL_USABLE(msgq_dev, err, free_addr); + + if (!pkt_info->no_reps) + { + err = zxdh_sequence_num_get(msgq_dev, &sn); + ZXDH_CHECK_RET_GOTO_ERR(err, free_addr, \ + "zxdh_sequence_num_get failed: %d\n", err); + } + + mutex_lock(&msgq_dev->mlock); + err = zxdh_msgq_pkt_send(msgq_dev, pkt_info, sn); + mutex_unlock(&msgq_dev->mlock); + ZXDH_CHECK_RET_GOTO_ERR(err, free_addr, "zxdh_msgq_pkt_send failed: %d\n", err); + + if (pkt_info->no_reps) + { + return MSGQ_RET_OK; + } + + msgq_dev->msg_buff_ring[sn].data = &reps->addr; + msgq_dev->msg_buff_ring[sn].data_len = &reps->len; + msgq_dev->msg_buff_ring[sn].timeout_cnt = pkt_info->timeout_us / TIMER_DELAY_US; + if (!pkt_info->is_async) + { + sync_poll_cnt = pkt_info->timeout_us / 10; + for (i = 0; i < sync_poll_cnt; ++i) + { + usleep_range(5, 10); + if (!msgq_dev->msg_buff_ring[sn].using && + msgq_dev->msg_buff_ring[sn].valid) + { + return MSGQ_RET_OK; + } + } + err = MSGQ_RET_ERR_CALLBACK_OUT_OF_TIME; + goto free_sn; + } + else + { + msgq_dev->msg_buff_ring[sn].need_free = true; + if (!msgq_dev->timer_in_use) + { + mod_timer(&msgq_dev->poll_timer, jiffies + usecs_to_jiffies(TIMER_DELAY_US)); + msgq_dev->timer_in_use = true; + } + } + return MSGQ_RET_OK; + +free_addr: + ZXDH_FREE_PTR(pkt_info->addr); +tx_err: + tx_errs++; +free_sn: + if ((sn != NO_REPS_SEQUENCE_NUM) && (sn < MSGQ_MAX_MSG_BUFF_NUM)) + { + LOG_ERR("timeout, sn[%d] is free\n", sn); + msgq_dev->msg_buff_ring[sn].using = false; + tx_timeouts++; + msgq_dev->free_cnt--; + } + u64_stats_update_begin(&msgq_dev->sq_priv->stats.syncp); + msgq_dev->sq_priv->stats.xdp_tx_drops += tx_errs; + msgq_dev->sq_priv->stats.tx_timeouts += tx_timeouts; + u64_stats_update_end(&msgq_dev->sq_priv->stats.syncp); + return err; +} + +static void zxdh_swap_dst_and_src(uint16_t *dst, uint16_t *src) +{ + uint16_t temp = 0; + + temp = *dst; + *dst = *src; + *src = temp; +} + +static int32_t zxdh_pi_header_check(struct pi_header *hdr) +{ + if (hdr->pi_type != DEFAULT_PI_TYPE) + { + LOG_ERR("INVALID_PI_TYPE: %d\n", hdr->pi_type); + return MSGQ_RET_ERR_CALLBACK_FAIL; + } + + if (hdr->pkt_type != CONTROL_MSG_TYPE) + { + LOG_ERR("INVALID_PKT_TYPE: %d\n", hdr->pkt_type); + return MSGQ_RET_ERR_CALLBACK_FAIL; + } + + if (hdr->msg_type > NO_REPS_MSG) + { + LOG_ERR("INVALID_MSG_TYPE: %d\n", hdr->msg_type); + return MSGQ_RET_ERR_CALLBACK_FAIL; + } + + if (hdr->event_id >= MSG_MODULE_NUM) + { + LOG_ERR("INVALID_MSG_MODULE_ID: %d\n", hdr->event_id); + return MSGQ_RET_ERR_CALLBACK_FAIL; + } + + if (hdr->err_code != MSGQ_RET_OK) + { + LOG_ERR("MSG_ERR_CODE: %d\n", hdr->err_code); + return MSGQ_RET_ERR_CALLBACK_FAIL; + } + + return MSGQ_RET_OK; +} + +static void rx_free_pages(struct msgq_dev *msgq_dev, void *buf, uint32_t len) +{ + if (msgq_dev->print_flag == MSGQ_PRINT_ALL) + { + print_data((uint8_t *)buf, len); + LOG_DEBUG("buf: 0x%llx refcnt: %d\n", (uint64_t)buf, \ + page_ref_count(virt_to_head_page(buf))); + } + put_page(virt_to_head_page(buf)); +} + +static int32_t zxdh_response_msg_handle(struct msgq_dev *msgq_dev, \ + struct virtnet_rq_stats *stats, uint16_t num_buf, void *buf, uint32_t len) +{ + struct priv_queues_net_hdr *hdr = (struct priv_queues_net_hdr *)buf; + uint16_t sn = hdr->pi_hdr.sequence_num; + int32_t err = MSGQ_RET_OK; + struct msg_buff *tmp_buff = NULL; + uint32_t max_len = 0; + uint32_t pkt_len = 0; + + if (sn >= MSGQ_MAX_MSG_BUFF_NUM) + { + LOG_ERR("INVALID_SEQUENCE_NUM: %d\n", sn); + err = MSGQ_RET_ERR; + goto put_page; + } + + tmp_buff = &msgq_dev->msg_buff_ring[sn]; + if (!tmp_buff->using) + { + LOG_ERR("buff[%d] is free\n", sn); + err = MSGQ_RET_ERR_CALLBACK_OUT_OF_TIME; + goto put_page; + } + ZXDH_CHECK_PTR_GOTO_ERR(*tmp_buff->data, put_page); + + max_len = *(tmp_buff->data_len); + pkt_len = len - PRIV_HEADER_LEN; + if (pkt_len > max_len) + { + LOG_ERR("buf_len: %d > tmp_buff->data_len: %d\n", pkt_len, max_len); + err = MSGQ_RET_ERR_REPS_LEN_NOT_ENOUGH; + goto put_page; + } + + memcpy(*tmp_buff->data, (uint8_t *)buf + PRIV_HEADER_LEN, pkt_len); + while (--num_buf != 0) + { + rx_free_pages(msgq_dev, buf, len); + buf = virtqueue_get_buf(msgq_dev->rq_priv->vq, &len); + if (unlikely(buf == NULL)) + { + LOG_ERR("msgq rx error: %dth buffers missing\n", num_buf); + stats->drops++; + err = MSGQ_RET_ERR_RX_INVALID_NUM_BUF; + goto out; + } + + if ((len + pkt_len) > max_len) + { + LOG_ERR("buf_len: %d > tmp_buff->data_len: %d\n", len + pkt_len, max_len); + err = MSGQ_RET_ERR_REPS_LEN_NOT_ENOUGH; + goto put_page; + } + + stats->bytes += len; + memcpy((*tmp_buff->data) + pkt_len, buf, len); + pkt_len += len; + } + *(tmp_buff->data_len) = pkt_len; + tmp_buff->valid = true; + stats->xdp_drops--; + +put_page: + put_page(virt_to_head_page(buf)); +out: + if (tmp_buff != NULL) + { + tmp_buff->using = false; + tmp_buff->data = NULL; + msgq_dev->free_cnt--; + } + return err; +} + +static int32_t zxdh_callback_msg_handle(struct zxdh_en_device *en_dev, \ + uint8_t *buf_addr, uint32_t buf_len) +{ + struct msgq_dev *msgq_dev = (struct msgq_dev *)en_dev->msgq_dev; + int32_t err = BAR_MSG_ERR_MODULE_NOEXIST; + uint8_t *reps_addr = NULL; + uint16_t reps_len = MAX_PACKET_LEN; + uint16_t hdr_len = PRIV_HEADER_LEN; + struct priv_queues_net_hdr *hdr = NULL; + + hdr = (struct priv_queues_net_hdr *)buf_addr; + if (hdr->pi_hdr.msg_type == NO_REPS_MSG) + { + return call_msg_recv_func_tbl(hdr->pi_hdr.event_id, \ + buf_addr + hdr_len, buf_len - hdr_len, NULL, 0, en_dev); + } + + reps_addr = kzalloc(MSGQ_MAX_ADDR_LEN, GFP_ATOMIC); + ZXDH_CHECK_PTR_RETURN(reps_addr); + memcpy(reps_addr, buf_addr, hdr_len); + hdr = (struct priv_queues_net_hdr *)reps_addr; + + if (hdr->pi_hdr.event_id < MSG_MODULE_NUM) + { + err = call_msg_recv_func_tbl(hdr->pi_hdr.event_id, \ + buf_addr + hdr_len, buf_len - hdr_len, \ + reps_addr + hdr_len, &reps_len, en_dev); + hdr->pi_hdr.msg_type = ACK_MSG; + } + + if (err == BAR_MSG_ERR_MODULE_NOEXIST) + { + hdr->pi_hdr.err_code = ERR_CODE_EVENT_UNREGIST; + } + else if ((err != MSGQ_RET_OK) || (reps_len > MAX_PACKET_LEN)) + { + LOG_ERR("get reps failed, reps_len:%d\n", reps_len); + hdr->pi_hdr.err_code = ERR_CODE_EVENT_FAIL; + } + + zxdh_swap_dst_and_src(&hdr->pi_hdr.vfid_dst, &hdr->pi_hdr.vfid_src); + zxdh_swap_dst_and_src(&hdr->pi_hdr.qid_dst, &hdr->pi_hdr.qid_src); + + return page_send_cmd(msgq_dev->sq_priv, \ + reps_addr, reps_len + hdr_len, msgq_dev->print_flag); +} + +static void msgq_receive_buf(struct zxdh_en_device *en_dev, struct receive_queue *rq, + void *buf, uint32_t len, void **ctx, struct virtnet_rq_stats *stats) +{ + struct net_device *netdev = en_dev->netdev; + struct priv_queues_net_hdr *hdr = (struct priv_queues_net_hdr *)buf; + uint16_t num_buf = vqm16_to_cpu(netdev, hdr->num_buffers); + struct msgq_dev *msgq_dev = (struct msgq_dev *)en_dev->msgq_dev; + int32_t err = MSGQ_RET_OK; + uint8_t *tmp_addr = NULL; + uint32_t tmp_addr_len = len; + bool free_tmp_addr = false; + + if (msgq_dev->print_flag != 0) + { + LOG_DEBUG("receive pkt start, num_buf: %d\n", num_buf); + msgq_print_data((uint8_t *)buf, len, msgq_dev->print_flag); + } + + stats->xdp_drops++; + err = zxdh_pi_header_check(&hdr->pi_hdr); + ZXDH_CHECK_RET_GOTO_ERR(err, free_pages, "invalid pi_header\n"); + + if (hdr->pi_hdr.msg_type == ACK_MSG) + { + err = zxdh_response_msg_handle(msgq_dev, stats, num_buf, buf, len); + goto free_addr; + } + else if (num_buf == 1) + { + err = zxdh_callback_msg_handle(en_dev, (uint8_t *)buf, len); + } + else + { + tmp_addr = kzalloc(MSGQ_MAX_ADDR_LEN, GFP_ATOMIC); + ZXDH_CHECK_PTR_GOTO_ERR(tmp_addr, free_pages); + memcpy(tmp_addr, buf, tmp_addr_len); + free_tmp_addr = true; + while (--num_buf != 0) + { + rx_free_pages(msgq_dev, buf, len); + buf = virtqueue_get_buf_ctx_packed(rq->vq, &len, ctx); + if (unlikely(buf == NULL)) + { + LOG_ERR("msgq rx error: %dth buffers missing\n", num_buf); + stats->drops++; + goto free_addr; + } + + memcpy(tmp_addr + tmp_addr_len, buf, len); + tmp_addr_len += len; + } + err = zxdh_callback_msg_handle(en_dev, tmp_addr, tmp_addr_len); + } + stats->xdp_drops--; + +free_pages: + put_page(virt_to_head_page(buf)); +free_addr: + if (free_tmp_addr) + { + ZXDH_FREE_PTR(tmp_addr); + } + stats->bytes += tmp_addr_len; + return; +} + +static int32_t zxdh_msgq_receive(struct receive_queue *rq, int32_t budget) +{ + struct zxdh_en_device *en_dev = netdev_priv(rq->vq->vdev); + struct virtnet_rq_stats stats = {}; + uint32_t len = 0; + void *buf = NULL; + int32_t i = 0; + void *ctx = NULL; + uint64_t *item = NULL; + + while (stats.packets < budget && (buf = virtqueue_get_buf_ctx_packed(rq->vq, &len, &ctx))) + { + msgq_receive_buf(en_dev, rq, buf, len, &ctx, &stats); + stats.packets++; + } + + if (rq->vq->num_free > min((uint32_t)budget, virtqueue_get_vring_size(rq->vq)) / 2) + { + if (!msgq_try_fill_recv(rq, GFP_ATOMIC)) + { + LOG_ERR("msgq_try_fill_recv failed\n"); + } + } + + u64_stats_update_begin(&rq->stats.syncp); + for (i = 0; i < VIRTNET_RQ_STATS_LEN; i++) + { + size_t offset = virtnet_rq_stats_desc[i].offset; + item = (uint64_t *)((uint8_t *)&rq->stats + offset); + *item += *(uint64_t *)((uint8_t *)&stats + offset); + } + u64_stats_update_end(&rq->stats.syncp); + + return stats.packets; +} + +static void free_old_xmit_bufs(struct net_device *netdev, struct send_queue *sq) +{ + uint32_t len = 0; + uint32_t packets = 0; + uint32_t bytes = 0; + void *buf = NULL; + + while ((buf = virtqueue_get_buf(sq->vq, &len)) != NULL) + { + bytes += len; + packets++; + ZXDH_FREE_PTR(buf); + } + + if (!packets) + { + return; + } + + u64_stats_update_begin(&sq->stats.syncp); + sq->stats.bytes += bytes; + sq->stats.packets += packets; + u64_stats_update_end(&sq->stats.syncp); +} + +static void msgq_poll_cleantx(struct receive_queue *rq) +{ + struct zxdh_en_priv *en_priv = netdev_priv(rq->vq->vdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + struct msgq_dev *msgq_dev = (struct msgq_dev *)en_dev->msgq_dev; + struct send_queue *sq = msgq_dev->sq_priv; + + if (!sq->napi.weight) + { + return; + } + + if (spin_trylock(&msgq_dev->tx_lock)) + { + free_old_xmit_bufs(en_dev->netdev, sq); + spin_unlock(&msgq_dev->tx_lock); + } +} + +int zxdh_msgq_poll(struct napi_struct *napi, int budget) +{ + struct receive_queue *rq = container_of(napi, struct receive_queue, napi); + struct zxdh_en_device *en_dev = netdev_priv(rq->vq->vdev); + struct msgq_dev *msgq_dev = (struct msgq_dev *)en_dev->msgq_dev; + uint32_t received = 0; + + if (msgq_dev->msgq_enable) + { + msgq_poll_cleantx(rq); + received = zxdh_msgq_receive(rq, budget); + } + + if (received < budget) + { + virtqueue_napi_complete(napi, rq->vq, received); + } + + return received; +} diff --git a/src/net/drivers/net/ethernet/dinghai/en_aux/priv_queue.h b/src/net/drivers/net/ethernet/dinghai/en_aux/priv_queue.h new file mode 100644 index 0000000..3ad57da --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_aux/priv_queue.h @@ -0,0 +1,225 @@ +#ifndef __ZXDH_PRIV_QUEUE_H__ +#define __ZXDH_PRIV_QUEUE_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include +#include +#include "queue.h" +#include "../en_aux.h" +#include "../../dinghai/en_np/table/include/dpp_tbl_api.h" + +#define MSGQ_TEST 1 + +#define MSGQ_RET_OK 0 +#define MSGQ_RET_ERR (-1) +#define MSGQ_RET_ERR_NULL_PTR (-2) +#define MSGQ_RET_ERR_INVALID_PARA (-3) +#define MSGQ_RET_ERR_CHANNEL_NOT_READY (-5) +#define MSGQ_RET_ERR_CHAN_BUSY (-6) +#define MSGQ_RET_ERR_VQ_BROKEN (-7) +#define MSGQ_RET_ERR_CALLBACK_OUT_OF_TIME (-8) +#define MSGQ_RET_ERR_CALLBACK_FAIL (-9) +#define MSGQ_RET_ERR_REPS_LEN_NOT_ENOUGH (-10) +#define MSGQ_RET_ERR_RX_INVALID_NUM_BUF (-11) + +struct reps_info +{ + uint32_t len; + uint8_t *addr; +}; + +struct msgq_pkt_info +{ + uint32_t timeout_us; + uint16_t event_id; + bool is_async; + bool no_reps; + uint8_t msg_priority; + uint8_t rsv; + uint32_t len; + uint8_t *addr; +} __attribute__((packed)); + +/* msg_chan_pkt Definitions */ +#define MAX_PACKET_LEN (MSGQ_MAX_ADDR_LEN - PRIV_HEADER_LEN) +#define MSGQ_MAX_ADDR_LEN 14000 +#define NO_REPS_SEQUENCE_NUM 0x8000 + +#define TIMER_DELAY_US 100 +#define MSGQ_MAX_MSG_BUFF_NUM 1024 +#define BUFF_LEN 4096 + +#define PRIV_HEADER_LEN sizeof(struct priv_queues_net_hdr) +#define DEFAULT_PI_TYPE 0x00 /*NP*/ +#define CONTROL_MSG_TYPE 0x1f +#define NEED_REPS_MSG 0x00 +#define ACK_MSG 0x01 +#define NO_REPS_MSG 0x02 + +#define RISCV_COMMON_VFID (1192) +#define RISCV_COMMON_QID (4092) + +enum msgq_err_code +{ + ERR_CODE_INVALID_EVENTID = 1, + ERR_CODE_EVENT_UNREGIST, + ERR_CODE_INVALID_ACK, + ERR_CODE_EVENT_FAIL, + ERR_CODE_INVALID_REPS_LEN, + ERR_CODE_PEER_BROKEN, +}; + +struct pi_header +{ + uint8_t pi_type; + uint8_t pkt_type; + uint16_t event_id; + uint16_t vfid_dst; + uint16_t qid_dst; + uint16_t vfid_src; + uint16_t qid_src; + uint16_t sequence_num; + uint8_t msg_priority; + uint8_t msg_type; + uint8_t err_code; + uint8_t rsv[3]; +}; + +struct msgq_pi_info +{ + uint16_t event_id; + uint16_t vfid_dst; + uint16_t qid_dst; + uint16_t vfid_src; + uint16_t qid_src; + uint16_t sequence_num; +} __attribute__((packed)); + +struct priv_queues_net_hdr +{ + uint8_t tx_port; + uint8_t pd_len; + uint8_t num_buffers; + uint8_t rsv; + struct pi_header pi_hdr; +}; + +struct msg_buff +{ + bool using; + bool valid; + bool need_free; + uint32_t timeout_cnt; + uint8_t **data; + uint32_t *data_len; +} __attribute__((packed)); + +#define MSGQ_PRINT_HDR 1 +#define MSGQ_PRINT_128B 2 +#define MSGQ_PRINT_ALL 3 +#define MSGQ_PRINT_STA 4 + +struct msgq_dev +{ + bool msgq_enable; + bool timer_in_use; + bool loopback; + uint8_t print_flag; + uint16_t sequence_num; + uint16_t free_cnt; + uint16_t msgq_vfid; + uint16_t msgq_rqid; + struct send_queue *sq_priv; + struct receive_queue *rq_priv; + struct mutex mlock; + struct spinlock sn_lock; + struct spinlock tx_lock; + struct msg_buff msg_buff_ring[MSGQ_MAX_MSG_BUFF_NUM]; + struct timer_list poll_timer; +} __attribute__((packed)); + +#define CHECK_CHANNEL_USABLE(msgq, ret, err) \ +do \ +{ \ + if (!(msgq)->msgq_enable) \ + { \ + LOG_ERR("msgq unable\n"); \ + ret = MSGQ_RET_ERR_CHANNEL_NOT_READY; \ + goto err; \ + } \ +} while (0) + +#define ZXDH_CHECK_RET_RETURN(ret, fmt, arg...) \ +do \ +{ \ + if ((ret) != MSGQ_RET_OK) \ + { \ + LOG_ERR(fmt, ##arg); \ + return (ret); \ + } \ +} while (0) + +#define ZXDH_CHECK_RET_GOTO_ERR(ret, err, fmt, arg...) \ +do \ +{ \ + if ((ret) != MSGQ_RET_OK) \ + { \ + LOG_ERR(fmt, ##arg); \ + goto err; \ + } \ +} while (0) + +#define ZXDH_CHECK_PTR_RETURN(ptr) \ +do \ +{ \ + if (unlikely((ptr) == NULL)) \ + { \ + LOG_ERR("null pointer\n"); \ + return MSGQ_RET_ERR_NULL_PTR; \ + } \ +} while (0) + +#define ZXDH_CHECK_PTR_GOTO_ERR(ptr, err) \ +do \ +{ \ + if (unlikely((ptr) == NULL)) \ + { \ + LOG_ERR("null pointer\n"); \ + goto err; \ + } \ +} while (0) + +#define ZXDH_FREE_PTR(ptr) \ +do \ +{ \ + if ((ptr) != NULL) \ + { \ + kfree(ptr); \ + (ptr) = NULL; \ + } \ +} while (0) + +#define SEQUENCE_NUM_ADD(id) \ +do \ +{ \ + (id)++; \ + (id) %= MSGQ_MAX_MSG_BUFF_NUM; \ +} while (0) + +int32_t zxdh_msgq_init(struct zxdh_en_device *en_dev); +void zxdh_msgq_exit(struct zxdh_en_device *en_dev); +int32_t print_data(uint8_t *data, uint32_t len); +int32_t zxdh_msgq_send_cmd(struct msgq_dev *msgq_dev, struct msgq_pkt_info *pkt_info, struct reps_info *reps); +int zxdh_msgq_poll(struct napi_struct *napi, int budget); + +#ifdef __cplusplus +} +#endif + +#endif /* __ZXDH_PRIV_QUEUE_H__ */ diff --git a/src/net/drivers/net/ethernet/dinghai/en_aux/queue.c b/src/net/drivers/net/ethernet/dinghai/en_aux/queue.c new file mode 100644 index 0000000..1493e6d --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_aux/queue.c @@ -0,0 +1,2913 @@ +#include +#include +#include +#include +#include +#include +#include +#include "../en_aux.h" +#include "queue.h" +#ifdef TIME_STAMP_1588 +#include "en_1588_pkt_proc.h" +#endif +#ifdef ZXDH_MSGQ +#include "priv_queue.h" +#endif + +static uint32_t features_table[] = +{ + ZXDH_NET_F_MRG_RXBUF, ZXDH_NET_F_STATUS, ZXDH_NET_F_CTRL_VQ, ZXDH_NET_F_MQ, \ + ZXDH_RING_F_INDIRECT_DESC, ZXDH_RING_F_EVENT_IDX, ZXDH_F_VERSION_1, ZXDH_F_RING_PACKED +}; + +void zxdh_print_vring_info(struct virtqueue *vq, uint32_t desc_index, uint32_t desc_num) +{ + struct vring_virtqueue *vvq = to_vvq(vq); + struct vring_packed_desc *desc = NULL; + uint32_t i = 0; + + LOG_INFO("phy_index : %d\n", vq->phy_index); + LOG_INFO("num free : %d\n", vq->num_free); + LOG_INFO("vring address : 0x%llx\n", (uint64_t)&vvq->packed.vring); + LOG_INFO("vring size : %d\n", vvq->packed.vring.num); + LOG_INFO("last_used_idx : %d\n", vvq->last_used_idx); + LOG_INFO("avail_wrap_counter: %d\n", vvq->packed.avail_wrap_counter); + LOG_INFO("used_wrap_counter : %d\n", vvq->packed.used_wrap_counter); + LOG_INFO("next_avail_idx : %d\n", vvq->packed.next_avail_idx); + LOG_INFO("free head : %d\n", vvq->free_head); + LOG_INFO("driver->flags : 0x%x\n", vvq->packed.vring.driver->flags); + LOG_INFO("driver->off_wrap : %d\n", vvq->packed.vring.driver->off_wrap); + LOG_INFO("device->flags : 0x%x\n", vvq->packed.vring.device->flags); + LOG_INFO("device->off_wrap : %d\n", vvq->packed.vring.device->off_wrap); + LOG_INFO("DESC[x]:\tDESC_ADDR\t[BUFFER_ADDR]\t\t[LEN]\t\t[ID]\t[FLAG]\n"); + + desc = vvq->packed.vring.desc; + for (i = desc_index; i < desc_num; i++) + { + LOG_INFO("DESC[%d] 0x%llx:\t0x%016llx\t0x%08x\t%8d\t0x%x\n", \ + i, (uint64_t)desc, desc->addr, desc->len, desc->id, desc->flags); + desc++; + } + + return; +} + +/* enable irq handlers */ +void zxdh_vp_enable_cbs(struct net_device *netdev) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + int32_t i = 0; + + for (i = 0; i< en_dev->channels_num; i++) + { + en_dev->ops->switch_vqs_channel(en_dev->parent, i, 1); + } +} + +/* disable irq handlers */ +void zxdh_vp_disable_cbs(struct net_device *netdev) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + int32_t i = 0; + + for (i = 0; i< en_dev->channels_num; i++) + { + en_dev->ops->switch_vqs_channel(en_dev->parent, i, 0); + } +} + +void zxdh_vp_reset(struct net_device *netdev) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + + /* 0 status means a reset. */ + en_dev->ops->set_status(en_dev->parent, 0); + + /* After writing 0 to device_status, the driver MUST wait for a read of + * device_status to return 0 before reinitializing the device. + * This will flush out the status write, and flush in device writes, + * including MSI-X interrupts, if any. + */ + LOG_INFO("vp reset: get_status start\n"); + while (en_dev->ops->get_status(en_dev->parent) != 0) + { + msleep(1); + } + LOG_INFO("vp reset: get_status stop\n"); + + return; +} + +void zxdh_add_status(struct net_device *netdev, uint32_t status) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + uint8_t dev_status = 0; + + might_sleep(); + + dev_status = en_dev->ops->get_status(en_dev->parent); + + en_dev->ops->set_status(en_dev->parent, (dev_status | status)); + + return; +} + +bool zxdh_has_status(struct net_device *netdev, uint32_t sbit) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + uint8_t dev_status = 0; + + dev_status = en_dev->ops->get_status(en_dev->parent); + + return (dev_status & sbit); +} + +void zxdh_pf_features_init(struct net_device *netdev) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + uint32_t i = 0; + uint64_t features = 0; + + en_dev->device_feature = en_dev->ops->get_features(en_dev->parent); + en_dev->device_feature |= BIT(34); + en_dev->driver_feature = 0; + + for (i = 0; i < ARRAY_SIZE(features_table); i++) + { + features = features_table[i]; + en_dev->driver_feature |= (1ULL << features); + } + en_dev->guest_feature = en_dev->device_feature & 0xfffffff5dfffffff; + LOG_INFO("device_feature: 0x%llx, guest_feature: 0x%llx\n", en_dev->device_feature, en_dev->guest_feature); + en_dev->ops->set_features(en_dev->parent, en_dev->guest_feature); + + return; +} + +bool zxdh_has_feature(struct net_device *netdev, uint32_t fbit) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + + return en_dev->guest_feature & BIT_ULL(fbit); +} + +int32_t vq2txq(struct virtqueue *vq) +{ + return (vq->index - 1) / 2; +} + +int32_t txq2vq(int32_t txq) +{ + return txq * 2 + 1; +} +int32_t vq2rxq(struct virtqueue *vq) +{ + return vq->index / 2; +} + +int32_t rxq2vq(int32_t rxq) +{ + return rxq * 2; +} + +inline void vqm_mb(bool weak_barriers) +{ + if (weak_barriers) + { + virt_mb(); + } + else + { + mb(); + } +} + +inline void vqm_rmb(bool weak_barriers) +{ + if (weak_barriers) + { + virt_rmb(); + } + else + { + dma_rmb(); + } +} + +inline void vqm_wmb(bool weak_barriers) +{ + if (weak_barriers) + { + virt_wmb(); + } + else + { + dma_wmb(); + } +} + +void vring_del_virtqueue(struct virtqueue *_vq) +{ + struct zxdh_en_priv *en_priv = netdev_priv(_vq->vdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + struct vring_virtqueue *vq = to_vvq(_vq); + + spin_lock(&en_dev->vqs_list_lock); + list_del(&_vq->list); + spin_unlock(&en_dev->vqs_list_lock); + + if (vq->we_own_ring) + { + vring_free_queue(vq->vq.vdev, + vq->packed.ring_size_in_bytes, + vq->packed.vring.desc, + vq->packed.ring_dma_addr); + + vring_free_queue(vq->vq.vdev, + vq->packed.event_size_in_bytes, + vq->packed.vring.driver, + vq->packed.driver_event_dma_addr); + + vring_free_queue(vq->vq.vdev, + vq->packed.event_size_in_bytes, + vq->packed.vring.device, + vq->packed.device_event_dma_addr); + + kfree(vq->packed.desc_state); + vq->packed.desc_state = NULL; + kfree(vq->packed.desc_extra); + vq->packed.desc_extra = NULL; + } + + kfree(vq); + vq = NULL; +} + +void del_vq(struct zxdh_pci_vq_info *info) +{ + struct virtqueue *vq = info->vq; + struct zxdh_en_priv *en_priv = netdev_priv(vq->vdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + + en_dev->ops->vq_unbind_channel(en_dev->parent, vq->phy_index); + + en_dev->ops->vp_modern_unmap_vq_notify(en_dev->parent, vq->priv); + + vring_del_virtqueue(vq); +} + +void vp_del_vq(struct virtqueue *vq) +{ + struct zxdh_en_priv *en_priv = netdev_priv(vq->vdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + struct zxdh_pci_vq_info *info = en_dev->vqs[vq->index]; + unsigned long flags; + + spin_lock_irqsave(&en_dev->lock, flags); + list_del(&info->node); + spin_unlock_irqrestore(&en_dev->lock, flags); + + del_vq(info); + kfree(info); + en_dev->vqs[vq->index] = NULL; +} + +void vp_detach_vqs(void *para) +{ + struct net_device *netdev = para; + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + struct virtqueue *vq; + struct virtqueue *n; + + list_for_each_entry_safe(vq, n, &en_dev->vqs_list, list) + { + vp_del_vq(vq); + } +} + +void vp_del_vqs(struct net_device *netdev) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + + vp_detach_vqs(netdev); + + kfree(en_dev->vqs); + en_dev->vqs = NULL; +} + +/** + * virtqueue_get_vring_size - return the size of the virtqueue's vring + * @_vq: the struct virtqueue containing the vring of interest. + * + * Returns the size of the vring. This is mainly used for boasting to + * userspace. Unlike other operations, this need not be serialized. + */ +uint32_t virtqueue_get_vring_size(struct virtqueue *_vq) +{ + struct vring_virtqueue *vq = to_vvq(_vq); + + return vq->packed.vring.num; +} + +dma_addr_t virtqueue_get_desc_addr(struct virtqueue *_vq) +{ + struct vring_virtqueue *vq = to_vvq(_vq); + + BUG_ON(!vq->we_own_ring); + + return vq->packed.ring_dma_addr; +} + +dma_addr_t virtqueue_get_avail_addr(struct virtqueue *_vq) +{ + struct vring_virtqueue *vq = to_vvq(_vq); + + BUG_ON(!vq->we_own_ring); + + return vq->packed.driver_event_dma_addr; +} + +dma_addr_t virtqueue_get_used_addr(struct virtqueue *_vq) +{ + struct vring_virtqueue *vq = to_vvq(_vq); + + BUG_ON(!vq->we_own_ring); + + return vq->packed.device_event_dma_addr; +} + +bool vqm_has_dma_quirk(struct net_device *netdev) +{ + /* + * Note the reverse polarity of the quirk feature (compared to most + * other features), this is for compatibility with legacy systems. + */ + return !zxdh_has_feature(netdev, ZXDH_F_ACCESS_PLATFORM); +} + +bool vring_use_dma_api(struct net_device *netdev) +{ + if (!vqm_has_dma_quirk(netdev)) + { + return true; + } + + /* Otherwise, we are left to guess. */ + /* + * In theory, it's possible to have a buggy QEMU-supposed + * emulated Q35 IOMMU and Xen enabled at the same time. On + * such a configuration, zxdh has never worked and will + * not work without an even larger kludge. Instead, enable + * the DMA API if we're a Xen guest, which at least allows + * all of the sensible Xen configurations to work correctly. + */ + if (xen_domain()) + { + return true; + } + + return false; +} + +void vring_free_queue(struct net_device *netdev, size_t size, void *queue, dma_addr_t dma_handle) +{ + if (vring_use_dma_api(netdev)) + { + dma_free_coherent(netdev->dev.parent, size, queue, dma_handle); + } + else + { + free_pages_exact(queue, PAGE_ALIGN(size)); + } +} + +void *vring_alloc_queue(struct net_device *netdev, size_t size, dma_addr_t *dma_handle, gfp_t flag) +{ + if (vring_use_dma_api(netdev)) + { + return dma_alloc_coherent(netdev->dev.parent, size, dma_handle, flag); + } + else + { + void *queue = alloc_pages_exact(PAGE_ALIGN(size), flag); + + if (queue) + { + phys_addr_t phys_addr = virt_to_phys(queue); + *dma_handle = (dma_addr_t)phys_addr; + + /* + * Sanity check: make sure we dind't truncate + * the address. The only arches I can find that + * have 64-bit phys_addr_t but 32-bit dma_addr_t + * are certain non-highmem MIPS and x86 + * configurations, but these configurations + * should never allocate physical pages above 32 + * bits, so this is fine. Just in case, throw a + * warning and abort if we end up with an + * unrepresentable address. + */ + if (WARN_ON_ONCE(*dma_handle != phys_addr)) + { + free_pages_exact(queue, PAGE_ALIGN(size)); + return NULL; + } + } + return queue; + } +} + +struct vring_desc_extra *vring_alloc_desc_extra(struct vring_virtqueue *vq, uint32_t num) +{ + struct vring_desc_extra *desc_extra = NULL; + uint32_t i = 0; + + desc_extra = kmalloc_array(num, sizeof(struct vring_desc_extra), GFP_KERNEL); + if (unlikely(desc_extra == NULL)) + { + LOG_ERR("desc_extra kmalloc_array failed\n"); + return NULL; + } + + memset(desc_extra, 0, num * sizeof(struct vring_desc_extra)); + + for (i = 0; i < num - 1; i++) + { + desc_extra[i].next = i + 1; + } + + return desc_extra; +} + +struct virtqueue *vring_create_virtqueue_packed(uint32_t index, + uint32_t num, + uint32_t vring_align, + struct net_device *netdev, + bool weak_barriers, + bool may_reduce_num, + bool context, + bool (*notify)(struct virtqueue *), + void (*callback)(struct virtqueue *), + const char *name) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + struct vring_virtqueue *vq = NULL; + struct vring_packed_desc *ring = NULL; + struct vring_packed_desc_event *driver = NULL; + struct vring_packed_desc_event *device = NULL; + dma_addr_t ring_dma_addr; + dma_addr_t driver_event_dma_addr; + dma_addr_t device_event_dma_addr; + size_t ring_size_in_bytes; + size_t event_size_in_bytes; + + ring_size_in_bytes = num * sizeof(struct vring_packed_desc); + + ring = vring_alloc_queue(netdev, ring_size_in_bytes, &ring_dma_addr, GFP_KERNEL|__GFP_NOWARN|__GFP_ZERO); + if (unlikely(ring == NULL)) + { + LOG_ERR("ring vring_alloc_queue failed\n"); + goto err_ring; + } + + event_size_in_bytes = sizeof(struct vring_packed_desc_event); + + driver = vring_alloc_queue(netdev, event_size_in_bytes, &driver_event_dma_addr, GFP_KERNEL|__GFP_NOWARN|__GFP_ZERO); + if (unlikely(driver == NULL)) + { + LOG_ERR("driver vring_alloc_queue failed\n"); + goto err_driver; + } + + device = vring_alloc_queue(netdev, event_size_in_bytes, &device_event_dma_addr, GFP_KERNEL|__GFP_NOWARN|__GFP_ZERO); + if (unlikely(device == NULL)) + { + LOG_ERR("device vring_alloc_queue failed\n"); + goto err_device; + } + + vq = kmalloc(sizeof(*vq), GFP_KERNEL); + if (unlikely(vq == NULL)) + { + LOG_ERR("vq kmalloc failed\n"); + goto err_vq; + } + + vq->vq.callback = callback; + vq->vq.vdev = netdev; + vq->vq.name = name; + vq->vq.num_free = num; + vq->vq.index = index; + vq->we_own_ring = true; + vq->notify = notify; + vq->weak_barriers = weak_barriers; + vq->broken = false; + vq->last_used_idx = 0; + vq->event_triggered = false; + vq->num_added = 0; + vq->packed_ring = true; + vq->use_dma_api = vring_use_dma_api(netdev); +#ifdef DEBUG + vq->in_use = false; + vq->last_add_time_valid = false; +#endif + + vq->indirect = zxdh_has_feature(netdev, ZXDH_RING_F_INDIRECT_DESC) && !context; + vq->event = zxdh_has_feature(netdev, ZXDH_RING_F_EVENT_IDX); + + if (zxdh_has_feature(netdev, ZXDH_F_ORDER_PLATFORM)) + { + vq->weak_barriers = false; + } + + vq->packed.ring_dma_addr = ring_dma_addr; + vq->packed.driver_event_dma_addr = driver_event_dma_addr; + vq->packed.device_event_dma_addr = device_event_dma_addr; + + vq->packed.ring_size_in_bytes = ring_size_in_bytes; + vq->packed.event_size_in_bytes = event_size_in_bytes; + + vq->packed.vring.num = num; + vq->packed.vring.desc = ring; + vq->packed.vring.driver = driver; + vq->packed.vring.device = device; + + vq->packed.next_avail_idx = 0; + vq->packed.avail_wrap_counter = 1; + vq->packed.used_wrap_counter = 1; + vq->packed.event_flags_shadow = 0; + vq->packed.avail_used_flags = 1 << VRING_PACKED_DESC_F_AVAIL; + + vq->packed.desc_state = kmalloc_array(num, sizeof(struct vring_desc_state_packed), GFP_KERNEL); + if (unlikely(vq->packed.desc_state == NULL)) + { + LOG_ERR("vq->packed.desc_state kmalloc_array failed\n"); + goto err_desc_state; + } + + memset(vq->packed.desc_state, 0, num * sizeof(struct vring_desc_state_packed)); + + /* Put everything in free lists. */ + vq->free_head = 0; + + vq->packed.desc_extra = vring_alloc_desc_extra(vq, num); + if (unlikely(vq->packed.desc_extra == NULL)) + { + LOG_ERR("vq->packed.desc_extra vring_alloc_desc_extra failed\n"); + goto err_desc_extra; + } + + /* No callback? Tell other side not to bother us. */ + if (!callback) + { + vq->packed.event_flags_shadow = VRING_PACKED_EVENT_FLAG_DISABLE; + vq->packed.vring.driver->flags = cpu_to_le16(vq->packed.event_flags_shadow); + } + + spin_lock(&en_dev->vqs_list_lock); + list_add_tail(&vq->vq.list, &en_dev->vqs_list); + spin_unlock(&en_dev->vqs_list_lock); + + return &vq->vq; + +err_desc_extra: + kfree(vq->packed.desc_state); + vq->packed.desc_state = NULL; +err_desc_state: + kfree(vq); + vq = NULL; +err_vq: + vring_free_queue(netdev, event_size_in_bytes, device, device_event_dma_addr); +err_device: + vring_free_queue(netdev, event_size_in_bytes, driver, driver_event_dma_addr); +err_driver: + vring_free_queue(netdev, ring_size_in_bytes, ring, ring_dma_addr); +err_ring: + return NULL; +} + +/* the notify function used when creating a virt queue */ +bool vp_notify(struct virtqueue *vq) +{ + /* we write the queue's selector into the notification register to + * signal the other end */ + iowrite16(vq->phy_index, (void __iomem *)vq->priv); + + return true; +} + +struct virtqueue *vp_setup_vq(struct net_device *netdev, unsigned index, + void (*callback)(struct virtqueue *vq), + const char *name, bool ctx, uint16_t channel_num) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + struct zxdh_pci_vq_info *info = kmalloc(sizeof *info, GFP_KERNEL); + struct virtqueue *vq = NULL; + struct virtqueue *n = NULL; + unsigned long flags; + uint16_t num = 0; + int32_t err = 0; + struct dh_vq_handler vq_handler; + + /* fill out our structure that represents an active queue */ + if (unlikely(info == NULL)) + { + LOG_ERR("info kmalloc failed\n"); + return ERR_PTR(-ENOMEM); + } + + /*if (index >= en_dev->ops->get_queue_num(en_dev->parent)) + { + LOG_ERR("index over queue nums\n"); + return ERR_PTR(-ENOENT); + }*/ + + /* Check if queue is either not available or already active. */ + num = en_dev->ops->get_queue_size(en_dev->parent, en_dev->phy_index[index]); + // if (!num || zxdh_get_queue_enable(en_dev, en_dev->phy_index[index])) + // { + // return ERR_PTR(-ENOENT); + // } + num = ZXDH_PF_MIN_DESC_NUM; + + if (num & (num - 1)) + { + LOG_ERR("bad queue size %u\n", num); + err = -ENOMEM; + goto out_info; + } + + /* create the vring */ + vq = vring_create_virtqueue_packed(index, num, SMP_CACHE_BYTES, en_dev->netdev, + true, true, ctx, vp_notify, callback, name); + if (vq == NULL) + { + LOG_ERR("create the vring failed\n"); + err = -ENOMEM; + goto out_info; + } + + /* activate the queue */ + en_dev->ops->activate_phy_vq(en_dev->parent, en_dev->phy_index[index], virtqueue_get_vring_size(vq), virtqueue_get_desc_addr(vq), virtqueue_get_avail_addr(vq), virtqueue_get_used_addr(vq)); + + vq->priv = (void __force *)en_dev->ops->vp_modern_map_vq_notify(en_dev->parent, en_dev->phy_index[index], NULL); + if (!vq->priv) + { + LOG_ERR("vp_modern_map_vq_notify failed\n"); + err = -ENOMEM; + goto err_map_notify; + } + + vq->phy_index = en_dev->phy_index[index]; + vq->index = index; + info->channel_num = channel_num; + + memset(&vq_handler, 0, sizeof(struct dh_vq_handler)); + vq_handler.callback = dh_eq_vqs_vring_int; + if (channel_num < (en_dev->ops->get_channels_num(en_dev->parent))) + { + err = en_dev->ops->vqs_channel_bind_handler(en_dev->parent, channel_num, &vq_handler); + if (err < 0) + { + LOG_ERR("vqs_channel_bind_handler failed: %d\n", err); + goto err_vqs_channel_bind_handler; + } + } + + if (channel_num >= (en_dev->ops->get_channels_num(en_dev->parent))) + { + channel_num = en_dev->ops->get_channels_num(en_dev->parent) - 1; + } + err = en_dev->ops->vq_bind_channel(en_dev->parent, channel_num, en_dev->phy_index[index]); + if (err < 0) + { + LOG_ERR("vq_bind_channel failed: %d\n", err); + goto err_vq_bind_channel; + } + + if (callback) + { + spin_lock_irqsave(&en_dev->lock, flags); + err = en_dev->ops->vqs_bind_eqs(en_dev->parent, channel_num, &info->node); + spin_unlock_irqrestore(&en_dev->lock, flags); + if (err < 0) + { + LOG_ERR("vqs_bind_eqs failed: %d\n", err); + goto err_vqs_bind_eqs; + } + } + else + { + INIT_LIST_HEAD(&info->node); + } + + info->vq = vq; + en_dev->vqs[index] = info; + return vq; + +err_vqs_bind_eqs: + list_for_each_entry_safe(vq, n, &en_dev->vqs_list, list) + { + en_dev->ops->vq_unbind_channel(en_dev->parent, vq->phy_index); + } +err_vq_bind_channel: + if (channel_num < (en_dev->ops->get_channels_num(en_dev->parent))) + { + en_dev->ops->vqs_channel_unbind_handler(en_dev->parent, channel_num); + } +err_vqs_channel_bind_handler: + en_dev->ops->vp_modern_unmap_vq_notify(en_dev->parent, (void __iomem __force *)vq->priv); +err_map_notify: + vring_del_virtqueue(vq); +out_info: + kfree(info); + en_dev->vqs[index] = NULL; + return ERR_PTR(err); +} + +uint32_t get_mergeable_buf_len(struct receive_queue *rq, struct ewma_pkt_len *avg_pkt_len, uint32_t room) +{ + const size_t hdr_len = sizeof(struct zxdh_net_hdr); + uint32_t len = 0; + + if (room) + { + return PAGE_SIZE - room; + } + + len = hdr_len + clamp_t(uint32_t, ewma_pkt_len_read(avg_pkt_len), rq->min_buf_len, PAGE_SIZE - hdr_len); + + return ALIGN(len, L1_CACHE_BYTES); +} + +/* + * The DMA ops on various arches are rather gnarly right now, and + * making all of the arch DMA ops work on the vring device itself + * is a mess. For now, we use the parent device for DMA ops. + */ +static inline struct device *vring_dma_dev(const struct vring_virtqueue *vq) +{ + return vq->vq.vdev->dev.parent; //todo +} + +/* Map one sg entry. */ +dma_addr_t vring_map_one_sg(const struct vring_virtqueue *vq, struct scatterlist *sg, enum dma_data_direction direction) +{ + if (!vq->use_dma_api) + { + return (dma_addr_t)sg_phys(sg); + } + + /* + * We can't use dma_map_sg, because we don't use scatterlists in + * the way it expects (we don't guarantee that the scatterlist + * will exist for the lifetime of the mapping). + */ + return dma_map_page(vring_dma_dev(vq), sg_page(sg), sg->offset, sg->length, direction); +} + +dma_addr_t vring_map_single(const struct vring_virtqueue *vq, + void *cpu_addr, size_t size, + enum dma_data_direction direction) +{ + if (!vq->use_dma_api) + { + return (dma_addr_t)virt_to_phys(cpu_addr); + } + + return dma_map_single(vring_dma_dev(vq), cpu_addr, size, direction); +} + +int32_t vring_mapping_error(const struct vring_virtqueue *vq, dma_addr_t addr) +{ + if (!vq->use_dma_api) + { + return 0; + } + + return dma_mapping_error(vring_dma_dev(vq), addr); +} + +/* + * Packed ring specific functions - *_packed(). + */ +void vring_unmap_state_packed(const struct vring_virtqueue *vq, struct vring_desc_extra *state) +{ + uint16_t flags = 0; + + if (!vq->use_dma_api) + { + return; + } + + flags = state->flags; + if (flags & VRING_DESC_F_INDIRECT) + { + dma_unmap_single(vring_dma_dev(vq), + state->addr, state->len, + (flags & VRING_DESC_F_WRITE) ? + DMA_FROM_DEVICE : DMA_TO_DEVICE); + } + else + { + dma_unmap_page(vring_dma_dev(vq), + state->addr, state->len, + (flags & VRING_DESC_F_WRITE) ? + DMA_FROM_DEVICE : DMA_TO_DEVICE); + } +} + +void vring_unmap_desc_packed(const struct vring_virtqueue *vq, struct vring_packed_desc *desc) +{ + uint16_t flags = 0; + + if (!vq->use_dma_api) + { + return; + } + + flags = le16_to_cpu(desc->flags); + + if (flags & VRING_DESC_F_INDIRECT) + { + dma_unmap_single(vring_dma_dev(vq), + le64_to_cpu(desc->addr), + le32_to_cpu(desc->len), + (flags & VRING_DESC_F_WRITE) ? + DMA_FROM_DEVICE : DMA_TO_DEVICE); + } + else + { + dma_unmap_page(vring_dma_dev(vq), + le64_to_cpu(desc->addr), + le32_to_cpu(desc->len), + (flags & VRING_DESC_F_WRITE) ? + DMA_FROM_DEVICE : DMA_TO_DEVICE); + } +} + +void *mergeable_len_to_ctx(uint32_t truesize, uint32_t headroom) +{ + return (void *)(unsigned long)((headroom << MRG_CTX_HEADER_SHIFT) | truesize); +} + +inline bool virtqueue_use_indirect(struct virtqueue *_vq, unsigned int total_sg) +{ + struct vring_virtqueue *vq = to_vvq(_vq); + + /* + * If the host supports indirect descriptor tables, and we have multiple + * buffers, then go indirect. FIXME: tune this threshold + */ + return (vq->indirect && total_sg > 1 && vq->vq.num_free); +} + +struct vring_packed_desc *alloc_indirect_packed(unsigned int total_sg, gfp_t gfp) +{ + struct vring_packed_desc *desc = NULL; + + /* + * We require lowmem mappings for the descriptors because + * otherwise virt_to_phys will give us bogus addresses in the + * virtqueue. + */ + gfp &= ~__GFP_HIGHMEM; + + desc = kmalloc_array(total_sg, sizeof(struct vring_packed_desc), gfp); + + return desc; +} + +int virtqueue_add_indirect_packed(struct vring_virtqueue *vq, + struct scatterlist *sgs[], + unsigned int total_sg, + unsigned int out_sgs, + unsigned int in_sgs, + void *data, + gfp_t gfp) +{ + struct vring_packed_desc *desc = NULL; + struct scatterlist *sg = NULL; + uint32_t i = 0; + uint32_t n = 0; + uint32_t err_idx = 0; + uint16_t head = 0; + uint16_t id = 0; + dma_addr_t addr; + + head = vq->packed.next_avail_idx; + desc = alloc_indirect_packed(total_sg, gfp); + if (desc == NULL) + { + LOG_ERR("desc alloc_indirect_packed failed\n"); + return -ENOMEM; + } + + if (unlikely(vq->vq.num_free < 1)) + { + LOG_DEBUG("can't add buf len 1 - avail = 0\n"); + kfree(desc); + END_USE(vq); + return -ENOSPC; + } + + i = 0; + id = vq->free_head; + BUG_ON(id == vq->packed.vring.num); + + for (n = 0; n < out_sgs + in_sgs; n++) + { + for (sg = sgs[n]; sg; sg = sg_next(sg)) + { + addr = vring_map_one_sg(vq, sg, n < out_sgs ? DMA_TO_DEVICE : DMA_FROM_DEVICE); + if (vring_mapping_error(vq, addr)) + { + LOG_ERR("vring_map_one_sg error\n"); + goto unmap_release; + } + + desc[i].flags = cpu_to_le16(n < out_sgs ? 0 : VRING_DESC_F_WRITE); + desc[i].addr = cpu_to_le64(addr); + desc[i].len = cpu_to_le32(sg->length); + i++; + } + } + + /* Now that the indirect table is filled in, map it. */ + addr = vring_map_single(vq, desc, total_sg * sizeof(struct vring_packed_desc), DMA_TO_DEVICE); + if (vring_mapping_error(vq, addr)) + { + LOG_ERR("vring_map_single error\n"); + goto unmap_release; + } + + vq->packed.vring.desc[head].addr = cpu_to_le64(addr); + vq->packed.vring.desc[head].len = cpu_to_le32(total_sg * sizeof(struct vring_packed_desc)); + vq->packed.vring.desc[head].id = cpu_to_le16(id); + + if (vq->use_dma_api) + { + vq->packed.desc_extra[id].addr = addr; + vq->packed.desc_extra[id].len = total_sg * sizeof(struct vring_packed_desc); + vq->packed.desc_extra[id].flags = VRING_DESC_F_INDIRECT | vq->packed.avail_used_flags; + } + + /* + * A driver MUST NOT make the first descriptor in the list + * available before all subsequent descriptors comprising + * the list are made available. + */ + vqm_wmb(vq->weak_barriers); + vq->packed.vring.desc[head].flags = cpu_to_le16(VRING_DESC_F_INDIRECT | vq->packed.avail_used_flags); + + /* We're using some buffers from the free list. */ + vq->vq.num_free -= 1; + + /* Update free pointer */ + n = head + 1; + if (n >= vq->packed.vring.num) + { + n = 0; + vq->packed.avail_wrap_counter ^= 1; + vq->packed.avail_used_flags ^= + 1 << VRING_PACKED_DESC_F_AVAIL | + 1 << VRING_PACKED_DESC_F_USED; + } + vq->packed.next_avail_idx = n; + vq->free_head = vq->packed.desc_extra[id].next; + + /* Store token and indirect buffer state. */ + vq->packed.desc_state[id].num = 1; + vq->packed.desc_state[id].data = data; + vq->packed.desc_state[id].indir_desc = desc; + vq->packed.desc_state[id].last = id; + + vq->num_added += 1; + + //LOG_DEBUG("added buffer head %i to %p\n", head, vq); + END_USE(vq); + + return 0; + +unmap_release: + err_idx = i; + + for (i = 0; i < err_idx; i++) + { + vring_unmap_desc_packed(vq, &desc[i]); + } + + kfree(desc); + + END_USE(vq); + return -ENOMEM; +} + +int32_t virtqueue_add_packed(struct virtqueue *_vq, + struct scatterlist *sgs[], + uint32_t total_sg, + uint32_t out_sgs, + uint32_t in_sgs, + void *data, + void *ctx, + gfp_t gfp) +{ + struct vring_virtqueue *vq = to_vvq(_vq); + struct vring_packed_desc *desc = NULL; + struct scatterlist *sg = NULL; + uint32_t i = 0; + uint32_t n = 0; + uint32_t c = 0; + uint32_t descs_used = 0; + uint32_t err_idx = 0; + __le16 head_flags = 0; + __le16 flags = 0; + uint16_t head = 0; + uint16_t id = 0; + uint16_t prev = 0; + uint16_t curr = 0; + uint16_t avail_used_flags = 0; + int32_t err = 0; + + START_USE(vq); + + BUG_ON(data == NULL); + BUG_ON(ctx && vq->indirect); + + if (unlikely(vq->broken)) + { + LOG_ERR("vq->broken\n"); + END_USE(vq); + return -EIO; + } + + LAST_ADD_TIME_UPDATE(vq); + + BUG_ON(total_sg == 0); + + if (virtqueue_use_indirect(_vq, total_sg)) + { + err = virtqueue_add_indirect_packed(vq, sgs, total_sg, out_sgs, in_sgs, data, gfp); + if (err != -ENOMEM) + { + END_USE(vq); + return err; + } + /* fall back on direct */ + } + + head = vq->packed.next_avail_idx; + avail_used_flags = vq->packed.avail_used_flags; + + WARN_ON_ONCE(total_sg > vq->packed.vring.num && !vq->indirect); + + desc = vq->packed.vring.desc; + i = head; + descs_used = total_sg; + + if (unlikely(vq->vq.num_free < descs_used)) + { + LOG_ERR("can't add buf len %i - avail = %i\n", descs_used, vq->vq.num_free); + END_USE(vq); + return -ENOSPC; + } + + id = vq->free_head; + BUG_ON(id == vq->packed.vring.num); + + curr = id; + c = 0; + for (n = 0; n < out_sgs + in_sgs; n++) + { + for (sg = sgs[n]; sg; sg = sg_next(sg)) + { + dma_addr_t addr = vring_map_one_sg(vq, sg, n < out_sgs ? DMA_TO_DEVICE : DMA_FROM_DEVICE); + if (vring_mapping_error(vq, addr)) + { + LOG_ERR("vring_map_one_sg error\n"); + goto unmap_release; + } + + flags = cpu_to_le16(vq->packed.avail_used_flags | + (++c == total_sg ? 0 : VRING_DESC_F_NEXT) | + (n < out_sgs ? 0 : VRING_DESC_F_WRITE)); + + desc[i].addr = cpu_to_le64(addr); + desc[i].len = cpu_to_le32(sg->length); + desc[i].id = cpu_to_le16(id); + + if (i == head) + { + head_flags = flags; + } + else + { + desc[i].flags = flags; + } + + if (unlikely(vq->use_dma_api)) + { + vq->packed.desc_extra[curr].addr = addr; + vq->packed.desc_extra[curr].len = sg->length; + vq->packed.desc_extra[curr].flags = le16_to_cpu(flags); + } + prev = curr; + curr = vq->packed.desc_extra[curr].next; + + if ((unlikely(++i >= vq->packed.vring.num))) + { + i = 0; + vq->packed.avail_used_flags ^= + 1 << VRING_PACKED_DESC_F_AVAIL | + 1 << VRING_PACKED_DESC_F_USED; + } + } + } + + if (i < head) + { + vq->packed.avail_wrap_counter ^= 1; + } + + /* We're using some buffers from the free list. */ + vq->vq.num_free -= descs_used; + + /* Update free pointer */ + vq->packed.next_avail_idx = i; + vq->free_head = curr; + + /* Store token. */ + vq->packed.desc_state[id].num = descs_used; + vq->packed.desc_state[id].data = data; + vq->packed.desc_state[id].indir_desc = ctx; + vq->packed.desc_state[id].last = prev; + + /* + * A driver MUST NOT make the first descriptor in the list + * available before all subsequent descriptors comprising + * the list are made available. + */ + vqm_wmb(vq->weak_barriers); + vq->packed.vring.desc[head].flags = head_flags; + vq->num_added += descs_used; + + //LOG_INFO("added buffer head %i to %p\n", head, vq); + END_USE(vq); + + return 0; + +unmap_release: + err_idx = i; + i = head; + curr = vq->free_head; + + vq->packed.avail_used_flags = avail_used_flags; + + for (n = 0; n < total_sg; n++) + { + if (i == err_idx) + { + break; + } + + vring_unmap_state_packed(vq, &vq->packed.desc_extra[curr]); + curr = vq->packed.desc_extra[curr].next; + i++; + if (i >= vq->packed.vring.num) + { + i = 0; + } + } + + END_USE(vq); + return -EIO; +} + +/** + * virtqueue_add_inbuf_ctx - expose input buffers to other end + * @vq: the struct virtqueue we're talking about. + * @sg: scatterlist (must be well-formed and terminated!) + * @num: the number of entries in @sg writable by other side + * @data: the token identifying the buffer. + * @ctx: extra context for the token + * @gfp: how to do memory allocations (if necessary). + * + * Caller must ensure we don't call this with other virtqueue operations + * at the same time (except where noted). + * + * Returns zero or a negative error (ie. ENOSPC, ENOMEM, EIO). + */ +int32_t virtqueue_add_inbuf_ctx(struct virtqueue *vq, + struct scatterlist *sg, uint32_t num, + void *data, + void *ctx, + gfp_t gfp) +{ + return virtqueue_add_packed(vq, &sg, num, 0, 1, data, ctx, gfp); +} + +bool is_used_desc_packed(struct vring_virtqueue *vq, uint16_t idx, bool used_wrap_counter) +{ + bool avail = false; + bool used = false; + uint16_t flags = 0; + + flags = le16_to_cpu(vq->packed.vring.desc[idx].flags); + avail = !!(flags & (1 << VRING_PACKED_DESC_F_AVAIL)); + used = !!(flags & (1 << VRING_PACKED_DESC_F_USED)); + + return avail == used && used == used_wrap_counter; +} + +bool virtqueue_poll_packed(struct virtqueue *_vq, uint16_t off_wrap) +{ + struct vring_virtqueue *vq = to_vvq(_vq); + bool wrap_counter = false; + uint16_t used_idx = 0; + + wrap_counter = off_wrap >> VRING_PACKED_EVENT_F_WRAP_CTR; + used_idx = off_wrap & ~(1 << VRING_PACKED_EVENT_F_WRAP_CTR); + + return is_used_desc_packed(vq, used_idx, wrap_counter); +} + +/** + * virtqueue_poll - query pending used buffers + * @_vq: the struct virtqueue we're talking about. + * @last_used_idx: virtqueue state (from call to virtqueue_enable_cb_prepare). + * + * Returns "true" if there are pending used buffers in the queue. + * + * This does not need to be serialized. + */ +bool virtqueue_poll(struct virtqueue *_vq, unsigned last_used_idx) +{ + struct vring_virtqueue *vq = to_vvq(_vq); + + if (unlikely(vq->broken)) + { + LOG_ERR("vq->broken\n"); + return false; + } + + vqm_mb(vq->weak_barriers); + return virtqueue_poll_packed(_vq, last_used_idx); +} + +unsigned virtqueue_enable_cb_prepare_packed(struct virtqueue *_vq) +{ + struct vring_virtqueue *vq = to_vvq(_vq); + + START_USE(vq); + + /* + * We optimistically turn back on interrupts, then check if there was + * more to do. + */ + if (vq->event) + { + vq->packed.vring.driver->off_wrap = + cpu_to_le16(vq->last_used_idx | (vq->packed.used_wrap_counter << VRING_PACKED_EVENT_F_WRAP_CTR)); + /* + * We need to update event offset and event wrap + * counter first before updating event flags. + */ + vqm_wmb(vq->weak_barriers); + } + + if (vq->packed.event_flags_shadow == VRING_PACKED_EVENT_FLAG_DISABLE) + { + vq->packed.event_flags_shadow = vq->event ? + VRING_PACKED_EVENT_FLAG_DESC : + VRING_PACKED_EVENT_FLAG_ENABLE; + vq->packed.vring.driver->flags = cpu_to_le16(vq->packed.event_flags_shadow); + } + + END_USE(vq); + return vq->last_used_idx | ((uint16_t)vq->packed.used_wrap_counter << VRING_PACKED_EVENT_F_WRAP_CTR); +} + +int32_t virtqueue_enable_cb_prepare(struct virtqueue *_vq) +{ + struct vring_virtqueue *vq = to_vvq(_vq); + + if (vq->event_triggered) + { + vq->event_triggered = false; + } + + return virtqueue_enable_cb_prepare_packed(_vq); +} + +bool more_used_packed(struct vring_virtqueue *vq) +{ + return is_used_desc_packed(vq, vq->last_used_idx, vq->packed.used_wrap_counter); +} + +void detach_buf_packed(struct vring_virtqueue *vq, uint32_t id, void **ctx) +{ + struct vring_desc_state_packed *state = NULL; + struct vring_packed_desc *desc = NULL; + uint32_t i = 0; + uint32_t curr = 0; + + state = &vq->packed.desc_state[id]; + + /* Clear data ptr. */ + state->data = NULL; + + vq->packed.desc_extra[state->last].next = vq->free_head; + vq->free_head = id; + vq->vq.num_free += state->num; + + if (unlikely(vq->use_dma_api)) + { + curr = id; + for (i = 0; i < state->num; i++) + { + vring_unmap_state_packed(vq, &vq->packed.desc_extra[curr]); + curr = vq->packed.desc_extra[curr].next; + } + } + + if (vq->indirect) + { + uint32_t len; + + /* Free the indirect table, if any, now that it's unmapped. */ + desc = state->indir_desc; + if (!desc) + { + return; + } + + if (vq->use_dma_api) + { + len = vq->packed.desc_extra[id].len; + for (i = 0; i < len / sizeof(struct vring_packed_desc); i++) + { + vring_unmap_desc_packed(vq, &desc[i]); + } + } + kfree(desc); + state->indir_desc = NULL; + } + else if (ctx) + { + *ctx = state->indir_desc; + } +} + +void *virtqueue_get_buf_ctx_packed(struct virtqueue *_vq, uint32_t *len, void **ctx) +{ + struct vring_virtqueue *vq = to_vvq(_vq); + uint16_t last_used = 0; + uint16_t id = 0; + void *ret = NULL; + + START_USE(vq); + + if (unlikely(vq->broken)) + { + END_USE(vq); + return NULL; + } + + if (!more_used_packed(vq)) + { + //LOG_ERR("no more buffers in queue\n"); + END_USE(vq); + return NULL; + } + + /* Only get used elements after they have been exposed by host. */ + vqm_rmb(vq->weak_barriers); + + last_used = vq->last_used_idx; + id = le16_to_cpu(vq->packed.vring.desc[last_used].id); + *len = le32_to_cpu(vq->packed.vring.desc[last_used].len); + + if (unlikely(id >= vq->packed.vring.num)) + { + zxdh_print_vring_info(_vq, 0, vq->packed.vring.num); + BAD_RING(vq, "id %u out of range\n", id); + return NULL; + } + if (unlikely(!vq->packed.desc_state[id].data)) + { + zxdh_print_vring_info(_vq, 0, vq->packed.vring.num); + BAD_RING(vq, "id %u is not a head!\n", id); + return NULL; + } + + /* detach_buf_packed clears data, so grab it now. */ + ret = vq->packed.desc_state[id].data; + detach_buf_packed(vq, id, ctx); + + vq->last_used_idx += vq->packed.desc_state[id].num; + if (unlikely(vq->last_used_idx >= vq->packed.vring.num)) + { + vq->last_used_idx -= vq->packed.vring.num; + vq->packed.used_wrap_counter ^= 1; + } + + /* + * If we expect an interrupt for the next entry, tell host + * by writing event index and flush out the write before + * the read in the next get_buf call. + */ + if (vq->packed.event_flags_shadow == VRING_PACKED_EVENT_FLAG_DESC) + vqm_store_mb(vq->weak_barriers, + &vq->packed.vring.driver->off_wrap, + cpu_to_le16(vq->last_used_idx | + (vq->packed.used_wrap_counter << + VRING_PACKED_EVENT_F_WRAP_CTR))); + + LAST_ADD_TIME_INVALID(vq); + + END_USE(vq); + return ret; +} + +void *virtqueue_get_buf(struct virtqueue *_vq, uint32_t *len) +{ + return virtqueue_get_buf_ctx_packed(_vq, len, NULL); +} + +/* + * private is used to chain pages for big packets, put the whole + * most recent used list in the beginning for reuse + */ +void give_pages(struct receive_queue *rq, struct page *page) +{ + struct page *end = NULL; + + /* Find end of list, sew whole thing into vi->rq.pages. */ + for (end = page; end->private; end = (struct page *)end->private); + end->private = (unsigned long)rq->pages; + rq->pages = page; +} + +void free_old_xmit_skbs(struct net_device *netdev, struct send_queue *sq, bool in_napi) +{ + uint32_t len = 0; + uint32_t packets = 0; + uint32_t bytes = 0; + void *ptr = NULL; + + while ((ptr = virtqueue_get_buf(sq->vq, &len)) != NULL) + { + struct sk_buff *skb = ptr; + + //LOG_DEBUG("sent skb %p\n", skb); + + bytes += skb->len; + napi_consume_skb(skb, in_napi); + packets++; + } + + /* Avoid overhead when no packets have been processed + * happens when called speculatively from start_xmit. + */ + if (!packets) + { + return; + } + + u64_stats_update_begin(&sq->stats.syncp); + sq->stats.bytes += bytes; + sq->stats.packets += packets; + netdev->stats.tx_bytes += bytes; + netdev->stats.tx_packets += packets; + u64_stats_update_end(&sq->stats.syncp); +} + +void virtqueue_disable_cb_packed(struct virtqueue *_vq) +{ + struct vring_virtqueue *vq = to_vvq(_vq); + + if (vq->packed.event_flags_shadow != VRING_PACKED_EVENT_FLAG_DISABLE) + { + vq->packed.event_flags_shadow = VRING_PACKED_EVENT_FLAG_DISABLE; + vq->packed.vring.driver->flags = cpu_to_le16(vq->packed.event_flags_shadow); + } +} + +/** + * virtqueue_disable_cb - disable callbacks + * @_vq: the struct virtqueue we're talking about. + * + * Note that this is not necessarily synchronous, hence unreliable and only + * useful as an optimization. + * + * Unlike other operations, this need not be serialized. + */ +void virtqueue_disable_cb(struct virtqueue *_vq) +{ + struct vring_virtqueue *vq = to_vvq(_vq); + + /* If device triggered an event already it won't trigger one again: + * no need to disable. + */ + if (vq->event_triggered) + { + return; + } + + virtqueue_disable_cb_packed(_vq); +} + +void virtqueue_napi_schedule(struct napi_struct *napi, struct virtqueue *vq) +{ + if (napi_schedule_prep(napi)) + { + virtqueue_disable_cb(vq); + __napi_schedule(napi); + } +} + +void virtnet_napi_enable(struct virtqueue *vq, struct napi_struct *napi) +{ + napi_enable(napi); + + /* If all buffers were filled by other side before we napi_enabled, we + * won't get another interrupt, so process any outstanding packets now. + * Call local_bh_enable after to trigger softIRQ processing. + */ + local_bh_disable(); + virtqueue_napi_schedule(napi, vq); + local_bh_enable(); +} + +void virtnet_napi_tx_enable(struct net_device *netdev, struct virtqueue *vq, struct napi_struct *napi) +{ + if (!napi->weight) + { + return; + } + + virtnet_napi_enable(vq, napi); + + return; +} + +void virtnet_napi_tx_disable(struct napi_struct *napi) +{ + if (napi->weight) + { + napi_disable(napi); + } +} + +int virtnet_poll_tx(struct napi_struct *napi, int budget) +{ + struct send_queue *sq = container_of(napi, struct send_queue, napi); + struct zxdh_en_priv *en_priv = netdev_priv(sq->vq->vdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + uint32_t index = vq2txq(sq->vq); + struct netdev_queue *txq = NULL; + int32_t opaque = 0; + bool done = false; + + txq = netdev_get_tx_queue(en_dev->netdev, index); + __netif_tx_lock(txq, raw_smp_processor_id()); + virtqueue_disable_cb(sq->vq); + free_old_xmit_skbs(en_dev->netdev, sq, true); + + if (sq->vq->num_free >= 2 + MAX_SKB_FRAGS) + { + netif_tx_wake_queue(txq); + } + + opaque = virtqueue_enable_cb_prepare(sq->vq); + + done = napi_complete_done(napi, 0); + + if (!done) + { + virtqueue_disable_cb(sq->vq); + } + + __netif_tx_unlock(txq); + + if (done) + { + if (unlikely(virtqueue_poll(sq->vq, opaque))) + { + if (napi_schedule_prep(napi)) + { + __netif_tx_lock(txq, raw_smp_processor_id()); + virtqueue_disable_cb(sq->vq); + __netif_tx_unlock(txq); + __napi_schedule(napi); + } + } + } + + return 0; +} + +bool virtqueue_enable_cb_delayed_packed(struct virtqueue *_vq) +{ + struct vring_virtqueue *vq = to_vvq(_vq); + uint16_t used_idx = 0; + uint16_t wrap_counter = 0; + uint16_t bufs = 0; + + START_USE(vq); + + /* + * We optimistically turn back on interrupts, then check if there was + * more to do. + */ + + if (vq->event) + { + /* TODO: tune this threshold */ + bufs = (vq->packed.vring.num - vq->vq.num_free) * 3 / 4; + wrap_counter = vq->packed.used_wrap_counter; + + used_idx = vq->last_used_idx + bufs; + if (used_idx >= vq->packed.vring.num) + { + used_idx -= vq->packed.vring.num; + wrap_counter ^= 1; + } + + vq->packed.vring.driver->off_wrap = cpu_to_le16(used_idx | + (wrap_counter << VRING_PACKED_EVENT_F_WRAP_CTR)); + + /* + * We need to update event offset and event wrap + * counter first before updating event flags. + */ + vqm_wmb(vq->weak_barriers); + } + + if (vq->packed.event_flags_shadow == VRING_PACKED_EVENT_FLAG_DISABLE) + { + vq->packed.event_flags_shadow = vq->event ? + VRING_PACKED_EVENT_FLAG_DESC : + VRING_PACKED_EVENT_FLAG_ENABLE; + vq->packed.vring.driver->flags = cpu_to_le16(vq->packed.event_flags_shadow); + } + + /* + * We need to update event suppression structure first + * before re-checking for more used buffers. + */ + vqm_mb(vq->weak_barriers); + + if (is_used_desc_packed(vq, vq->last_used_idx, vq->packed.used_wrap_counter)) + { + END_USE(vq); + return false; + } + + END_USE(vq); + return true; +} +uint16_t __vqm16_to_cpu(bool little_endian, __vqm16 val) +{ + if (little_endian) + { + return le16_to_cpu((__force __le16)val); + } + else + { + return be16_to_cpu((__force __be16)val); + } +} + +static inline bool zxdh_legacy_is_little_endian(void) +{ +#ifdef __LITTLE_ENDIAN + return true; +#else + return false; +#endif +} + +bool zxdh_is_little_endian(struct net_device *dev) +{ + return zxdh_has_feature(dev, ZXDH_F_VERSION_1) || zxdh_legacy_is_little_endian(); +} + +/* Memory accessors */ +uint16_t vqm16_to_cpu(struct net_device *netdev, __vqm16 val) +{ + return __vqm16_to_cpu(zxdh_is_little_endian(netdev), val); +} + +uint32_t mergeable_ctx_to_headroom(void *mrg_ctx) +{ + return (unsigned long)mrg_ctx >> MRG_CTX_HEADER_SHIFT; +} + +uint32_t mergeable_ctx_to_truesize(void *mrg_ctx) +{ + return (unsigned long)mrg_ctx & ((1 << MRG_CTX_HEADER_SHIFT) - 1); +} + +/** + * virtqueue_enable_cb_delayed - restart callbacks after disable_cb. + * @_vq: the struct virtqueue we're talking about. + * + * This re-enables callbacks but hints to the other side to delay + * interrupts until most of the available buffers have been processed; + * it returns "false" if there are many pending buffers in the queue, + * to detect a possible race between the driver checking for more work, + * and enabling callbacks. + * + * Caller must ensure we don't call this with other virtqueue + * operations at the same time (except where noted). + */ +bool virtqueue_enable_cb_delayed(struct virtqueue *_vq) +{ + struct vring_virtqueue *vq = to_vvq(_vq); + + if (vq->event_triggered) + { + vq->event_triggered = false; + } + + return virtqueue_enable_cb_delayed_packed(_vq); +} + +void virtnet_poll_cleantx(struct receive_queue *rq) +{ + struct zxdh_en_priv *en_priv = netdev_priv(rq->vq->vdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + uint32_t index = vq2rxq(rq->vq); + struct send_queue *sq = &en_dev->sq[index]; + struct netdev_queue *txq = netdev_get_tx_queue(en_dev->netdev, index); + + if (!sq->napi.weight) + { + return; + } + + if (__netif_tx_trylock(txq)) + { + do + { + virtqueue_disable_cb(sq->vq); + free_old_xmit_skbs(en_dev->netdev, sq, true); + } while (unlikely(!virtqueue_enable_cb_delayed(sq->vq))); + + if (sq->vq->num_free >= 2 + MAX_SKB_FRAGS) + { + netif_tx_wake_queue(txq); + } + + __netif_tx_unlock(txq); + } +} + +inline struct zxdh_net_hdr *skb_vnet_hdr(struct sk_buff *skb) +{ + return (struct zxdh_net_hdr *)skb->cb; +} + +/* Called from bottom half context */ +struct sk_buff *page_to_skb(struct zxdh_en_device *en_dev, + struct receive_queue *rq, + struct page *page, uint32_t offset, + uint32_t len, uint32_t truesize, + uint32_t metasize, uint32_t headroom) +{ + struct sk_buff *skb = NULL; + struct zxdh_net_hdr *hdr = NULL; + uint32_t copy = 0; + uint32_t hdr_len = 0; + struct page *page_to_free = NULL; + int32_t tailroom = 0; + int32_t shinfo_size = 0; + char *p = NULL; + char *hdr_p = NULL; + char *buf = NULL; + uint32_t hdr_len_tmp = 0; + + p = page_address(page) + offset; + hdr_p = p; + + hdr_len = (((struct zxdh_net_hdr *)hdr_p)->pd_len) * HDR_2B_UNIT; + + /* If headroom is not 0, there is an offset between the beginning of the + * data and the allocated space, otherwise the data and the allocated + * space are aligned. + * + * Buffers with headroom use PAGE_SIZE as alloc size, see + * add_recvbuf_mergeable() + get_mergeable_buf_len() + */ + truesize = headroom ? PAGE_SIZE : truesize; + tailroom = truesize - headroom; + buf = p - headroom; + + len -= hdr_len; + offset += hdr_len; + p += hdr_len; + tailroom -= hdr_len + len; + + shinfo_size = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); + + /* copy small packet so we can reuse these pages */ + if (!NET_IP_ALIGN && len > GOOD_COPY_LEN && tailroom >= shinfo_size) + { + skb = build_skb(buf, truesize); + if (unlikely(!skb)) + { + LOG_ERR("build_skb is null\n"); + return NULL; + } + + skb_reserve(skb, p - buf); + skb_put(skb, len); + + page = (struct page *)page->private; + if (page) + { + give_pages(rq, page); + } + goto ok; + } + + /* copy small packet so we can reuse these pages for small data */ + skb = napi_alloc_skb(&rq->napi, GOOD_COPY_LEN); + if (unlikely(!skb)) + { + LOG_ERR("napi_alloc_skb is null\n"); + return NULL; + } + + /* Copy all frame if it fits skb->head */ + if (len <= skb_tailroom(skb)) + { + copy = len; + } + else + { + copy = ETH_HLEN + metasize; + } + skb_put_data(skb, p, copy); + + len -= copy; + offset += copy; + + if (len) + { + skb_add_rx_frag(skb, 0, page, offset, len, truesize); + } + else + { + page_to_free = page; + } + +ok: + hdr = skb_vnet_hdr(skb); + hdr_len_tmp = hdr_len > 48 ? 48 : hdr_len; //todo + memcpy(hdr, hdr_p, hdr_len_tmp); + //memcpy(hdr, hdr_p, hdr_len); + + if (page_to_free) + { + put_page(page_to_free); + } + + if (metasize) + { + __skb_pull(skb, metasize); + skb_metadata_set(skb, metasize); + } + + return skb; +} +/** + * virtqueue_add_outbuf - expose output buffers to other end + * @vq: the struct virtqueue we're talking about. + * @sg: scatterlist (must be well-formed and terminated!) + * @num: the number of entries in @sg readable by other side + * @data: the token identifying the buffer. + * @gfp: how to do memory allocations (if necessary). + * + * Caller must ensure we don't call this with other virtqueue operations + * at the same time (except where noted). + * + * Returns zero or a negative error (ie. ENOSPC, ENOMEM, EIO). + */ +int32_t virtqueue_add_outbuf(struct virtqueue *vq, struct scatterlist *sg, uint32_t num, void *data, gfp_t gfp) +{ + return virtqueue_add_packed(vq, &sg, num, 1, 0, data, NULL, gfp); +} + +struct sk_buff *receive_mergeable(struct net_device *netdev, + struct zxdh_en_device *en_dev, + struct receive_queue *rq, + void *buf, + void *ctx, + uint32_t len, + struct virtnet_rq_stats *stats) +{ + struct zxdh_net_hdr *hdr = buf; + uint16_t num_buf = vqm16_to_cpu(netdev, hdr->num_buffers); + struct page *page = virt_to_head_page(buf); + int32_t offset = buf - page_address(page); + struct sk_buff *head_skb = NULL; + struct sk_buff *curr_skb = NULL; + uint32_t truesize = mergeable_ctx_to_truesize(ctx); + uint32_t headroom = mergeable_ctx_to_headroom(ctx); + uint32_t metasize = 0; + + stats->bytes += (len - (hdr->pd_len * HDR_2B_UNIT)); + netdev->stats.rx_bytes += (len - (hdr->pd_len * HDR_2B_UNIT)); + + if (unlikely(len > truesize)) + { + LOG_ERR("%s: rx error: len %u exceeds truesize %lu\n", netdev->name, len, (unsigned long)ctx); + netdev->stats.rx_length_errors++; + netdev->stats.rx_errors++; + goto err_skb; + } + + head_skb = page_to_skb(en_dev, rq, page, offset, len, truesize, metasize, headroom); + curr_skb = head_skb; + + if (unlikely(!curr_skb)) + { + LOG_ERR("page_to_skb is null\n"); + goto err_skb; + } + while (--num_buf) + { + int32_t num_skb_frags; + + buf = virtqueue_get_buf_ctx_packed(rq->vq, &len, &ctx); + if (unlikely(!buf)) + { + LOG_ERR("%s: rx error: %d buffers out of %d missing\n", netdev->name, num_buf, vqm16_to_cpu(netdev, hdr->num_buffers)); + netdev->stats.rx_length_errors++; + netdev->stats.rx_errors++; + goto err_buf; + } + + stats->bytes += len; + netdev->stats.rx_bytes += len; + page = virt_to_head_page(buf); + + truesize = mergeable_ctx_to_truesize(ctx); + if (unlikely(len > truesize)) + { + LOG_ERR("%s: rx error: len %u exceeds truesize %lu\n", netdev->name, len, (unsigned long)ctx); + netdev->stats.rx_length_errors++; + netdev->stats.rx_errors++; + goto err_skb; + } + + num_skb_frags = skb_shinfo(curr_skb)->nr_frags; + if (unlikely(num_skb_frags == MAX_SKB_FRAGS)) + { + struct sk_buff *nskb = alloc_skb(0, GFP_ATOMIC); + + if (unlikely(!nskb)) + { + LOG_ERR("alloc_skb is null\n"); + goto err_skb; + } + if (curr_skb == head_skb) + { + skb_shinfo(curr_skb)->frag_list = nskb; + } + else + { + curr_skb->next = nskb; + } + curr_skb = nskb; + head_skb->truesize += nskb->truesize; + num_skb_frags = 0; + } + + if (curr_skb != head_skb) + { + head_skb->data_len += len; + head_skb->len += len; + head_skb->truesize += truesize; + } + offset = buf - page_address(page); + + if (skb_can_coalesce(curr_skb, num_skb_frags, page, offset)) + { + put_page(page); + skb_coalesce_rx_frag(curr_skb, num_skb_frags - 1, len, truesize); + } + else + { + skb_add_rx_frag(curr_skb, num_skb_frags, page, offset, len, truesize); + } + } + + ewma_pkt_len_add(&rq->mrg_avg_pkt_len, head_skb->len); + return head_skb; + +err_skb: + put_page(page); + while (num_buf-- > 1) + { + buf = virtqueue_get_buf(rq->vq, &len); + if (unlikely(!buf)) + { + LOG_ERR("%s: rx error: %d buffers missing\n", netdev->name, num_buf); + netdev->stats.rx_length_errors++; + netdev->stats.rx_errors++; + break; + } + stats->bytes += len; + page = virt_to_head_page(buf); + put_page(page); + } +err_buf: + stats->drops++; + netdev->stats.rx_dropped++; + dev_kfree_skb(head_skb); + return NULL; +} + +static bool is_dev_configed_vlan(struct zxdh_en_device *en_dev) +{ + return (en_dev->vlan_dev.vlan_id != 0); +} + +void receive_buf(struct zxdh_en_device *en_dev, struct receive_queue *rq, + void *buf, uint32_t len, void **ctx, + struct virtnet_rq_stats *stats) +{ + bool vlan_striped, qinq_striped; + struct net_device *netdev = en_dev->netdev; + struct sk_buff *skb = NULL; + struct zxdh_net_hdr_rcv *hdr_rcv = (struct zxdh_net_hdr_rcv *)buf; + +#ifdef TIME_STAMP_1588 + int32_t ret = 0; +#endif + + if (unlikely(len < (hdr_rcv->pd_len * HDR_2B_UNIT) + ETH_HLEN)) + { + LOG_ERR("%s: short packet %i\n", netdev->name, len); + netdev->stats.rx_length_errors++; + netdev->stats.rx_errors++; + + put_page(virt_to_head_page(buf)); + return; + } + + skb = receive_mergeable(netdev, en_dev, rq, buf, ctx, len, stats); + + if (unlikely(!skb)) + { + LOG_ERR("skb receive_mergeable null\n"); + return; + } + + /* rx packet contain the strip label & open rxvlan offloading*/ + vlan_striped = hdr_rcv->pd_hdr.flags & RX_VLAN_STRIPED_MASK && !is_dev_configed_vlan(en_dev); + qinq_striped = hdr_rcv->pd_hdr.flags & RX_QINQ_STRIPED_MASK; + if ((netdev->features & NETIF_F_HW_VLAN_CTAG_RX) && (vlan_striped || qinq_striped)) + { + u16 vid = htons(hdr_rcv->pd_hdr.striped_ctci) & RX_TPID_VLAN_ID_MASK; + __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); + } + + if ((netdev->features & NETIF_F_RXCSUM) && !(hdr_rcv->pi_hdr.error_code[1] & PI_HDR_L4_CHKSUM_ERROR_CODE) + && !(hdr_rcv->pi_hdr.error_code[0] & PI_HDR_L3_CHKSUM_ERROR_CODE) && !(hdr_rcv->pd_hdr.flags & OUTER_IP_CHKSUM_ERROT_CODE)) + { + skb->ip_summed = CHECKSUM_UNNECESSARY; + } + else + { + skb->ip_summed = CHECKSUM_NONE; + } + +#ifdef TIME_STAMP_1588 + ret = pkt_1588_proc_rcv(skb, hdr_rcv, en_dev->clock_no, en_dev); + if ((ret != PTP_SUCCESS) && (ret != IS_NOT_PTP_MSG)) + { + LOG_ERR("pkt_1588_proc_rcv err!!!\n"); + return; + } +#endif + + skb_record_rx_queue(skb, vq2rxq(rq->vq)); + skb->protocol = eth_type_trans(skb, netdev); + + //LOG_INFO("receiving skb proto 0x%04x len %i type %i\n", ntohs(skb->protocol), skb->len, skb->pkt_type); + + napi_gro_receive(&rq->napi, skb); + return; +} + +/** + * virtqueue_notify - second half of split virtqueue_kick call. + * @_vq: the struct virtqueue + * + * This does not need to be serialized. + * + * Returns false if host notify failed or queue is broken, otherwise true. + */ +bool virtqueue_notify(struct virtqueue *_vq) +{ + struct vring_virtqueue *vq = to_vvq(_vq); + + if (unlikely(vq->broken)) + { + LOG_ERR("vq->broken\n"); + return false; + } + + /* Prod other side to tell it about changes. */ + if (!vq->notify(_vq)) + { + LOG_ERR("vq->notify(_vq) failed\n"); + vq->broken = true; + return false; + } + + return true; +} + +int32_t add_recvbuf_mergeable(struct zxdh_en_device *en_dev, struct receive_queue *rq, gfp_t gfp) +{ + struct page_frag *alloc_frag = &rq->alloc_frag; + uint32_t headroom = 0; + uint32_t tailroom = 0; + uint32_t room = SKB_DATA_ALIGN(headroom + tailroom); + char *buf = NULL; + void *ctx = NULL; + int32_t err = 0; + uint32_t len = 0; + uint32_t hole = 0; + + /* Extra tailroom is needed to satisfy XDP's assumption. This + * means rx frags coalescing won't work, but consider we've + * disabled GSO for XDP, it won't be a big issue. + */ + len = get_mergeable_buf_len(rq, &rq->mrg_avg_pkt_len, room); + if (unlikely(!skb_page_frag_refill(len + room, alloc_frag, gfp))) + { + LOG_ERR("skb_page_frag_refill failed\n"); + return -ENOMEM; + } + + buf = (char *)page_address(alloc_frag->page) + alloc_frag->offset; + buf += headroom; /* advance address leaving hole at front of pkt */ + get_page(alloc_frag->page); + alloc_frag->offset += len + room; + hole = alloc_frag->size - alloc_frag->offset; + if (hole < len + room) + { + /* To avoid internal fragmentation, if there is very likely not + * enough space for another buffer, add the remaining space to + * the current buffer. + */ + len += hole; + alloc_frag->offset += hole; + } + + sg_init_one(rq->sg, buf, len); + ctx = mergeable_len_to_ctx(len, headroom); + err = virtqueue_add_inbuf_ctx(rq->vq, rq->sg, 1, buf, ctx, gfp); + if (err < 0) + { + put_page(virt_to_head_page(buf)); + } + + return err; +} + +/* Assuming a given event_idx value from the other side, if + * we have just incremented index from old to new_idx, + * should we trigger an event? */ +int32_t vring_need_event(__u16 event_idx, __u16 new_idx, __u16 old) +{ + /* Note: Xen has similar logic for notification hold-off + * in include/xen/interface/io/ring.h with req_event and req_prod + * corresponding to event_idx + 1 and new_idx respectively. + * Note also that req_event and req_prod in Xen start at 1, + * event indexes in custom queue start at 0. */ + return (__u16)(new_idx - event_idx - 1) < (__u16)(new_idx - old); +} + +bool virtqueue_kick_prepare_packed(struct virtqueue *_vq) +{ + struct vring_virtqueue *vq = to_vvq(_vq); + uint16_t new = 0; + uint16_t old = 0; + uint16_t off_wrap = 0; + uint16_t flags = 0; + uint16_t wrap_counter = 0; + uint16_t event_idx = 0; + bool needs_kick = false; + union + { + struct + { + __le16 off_wrap; + __le16 flags; + }; + uint32_t u32; + } snapshot; + + START_USE(vq); + + /* + * We need to expose the new flags value before checking notification + * suppressions. + */ + vqm_mb(vq->weak_barriers); + + old = vq->packed.next_avail_idx - vq->num_added; + new = vq->packed.next_avail_idx; + vq->num_added = 0; + + snapshot.u32 = *(uint32_t *)vq->packed.vring.device; + flags = le16_to_cpu(snapshot.flags); + + LAST_ADD_TIME_CHECK(vq); + LAST_ADD_TIME_INVALID(vq); + + if (flags != VRING_PACKED_EVENT_FLAG_DESC) + { + needs_kick = (flags != VRING_PACKED_EVENT_FLAG_DISABLE); + goto out; + } + + off_wrap = le16_to_cpu(snapshot.off_wrap); + + wrap_counter = off_wrap >> VRING_PACKED_EVENT_F_WRAP_CTR; + event_idx = off_wrap & ~(1 << VRING_PACKED_EVENT_F_WRAP_CTR); + if (wrap_counter != vq->packed.avail_wrap_counter) + { + event_idx -= vq->packed.vring.num; + } + + needs_kick = vring_need_event(event_idx, new, old); +out: + END_USE(vq); + return needs_kick; +} + +/* + * Returns false if we couldn't fill entirely (OOM). + * + * Normally run in the receive path, but can also be run from ndo_open + * before we're receiving packets, or from refill_work which is + * careful to disable receiving (using napi_disable). + */ +bool try_fill_recv(struct net_device *netdev, struct receive_queue *rq, gfp_t gfp) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + int32_t err = 0; + bool oom = 0; + unsigned long flags = 0; + + do + { + err = add_recvbuf_mergeable(en_dev, rq, gfp); + oom = err == -ENOMEM; + if (err) + { + break; + } + } while (rq->vq->num_free); + + if (virtqueue_kick_prepare_packed(rq->vq) && virtqueue_notify(rq->vq)) + { + flags = u64_stats_update_begin_irqsave(&rq->stats.syncp); + rq->stats.kicks++; + u64_stats_update_end_irqrestore(&rq->stats.syncp, flags); + } + + return !oom; +} + +int32_t virtnet_receive(struct receive_queue *rq, int32_t budget) +{ + struct net_device *netdev = rq->vq->vdev; + struct zxdh_en_priv *en_priv = netdev_priv(rq->vq->vdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + struct virtnet_rq_stats stats = {}; + uint32_t len = 0; + void *buf = NULL; + int32_t i = 0; + void *ctx = NULL; + + while (stats.packets < budget && (buf = virtqueue_get_buf_ctx_packed(rq->vq, &len, &ctx))) + { + receive_buf(en_dev, rq, buf, len, ctx, &stats); + stats.packets++; + netdev->stats.rx_packets++; + } + + if (rq->vq->num_free > min((uint32_t)budget, virtqueue_get_vring_size(rq->vq)) / 2) + { + if (!try_fill_recv(rq->vq->vdev, rq, GFP_ATOMIC)) + { + schedule_delayed_work(&en_dev->refill, 0); + } + } + + u64_stats_update_begin(&rq->stats.syncp); + for (i = 0; i < VIRTNET_RQ_STATS_LEN; i++) + { + size_t offset = virtnet_rq_stats_desc[i].offset; + uint64_t *item; + + item = (uint64_t *)((uint8_t *)&rq->stats + offset); + *item += *(uint64_t *)((uint8_t *)&stats + offset); + } + u64_stats_update_end(&rq->stats.syncp); + + return stats.packets; +} + +void virtqueue_napi_complete(struct napi_struct *napi, struct virtqueue *vq, int32_t processed) +{ + int32_t opaque = 0; + + opaque = virtqueue_enable_cb_prepare(vq); + if (napi_complete_done(napi, processed)) + { + if (unlikely(virtqueue_poll(vq, opaque))) + { + virtqueue_napi_schedule(napi, vq); + } + } + else + { + virtqueue_disable_cb(vq); + } +} + +int virtnet_poll(struct napi_struct *napi, int budget) +{ + struct receive_queue *rq = container_of(napi, struct receive_queue, napi); + uint32_t received = 0; + + virtnet_poll_cleantx(rq); + + received = virtnet_receive(rq, budget); + + /* Out of packets? */ + if (received < budget) + { + virtqueue_napi_complete(napi, rq->vq, received); + } + + return received; +} + +int32_t virtnet_alloc_queues(struct zxdh_en_device *en_dev) +{ + int32_t i = 0; + + en_dev->sq = kcalloc(en_dev->max_queue_pairs, sizeof(*en_dev->sq), GFP_KERNEL); + if (unlikely(en_dev->sq == NULL)) + { + LOG_ERR("en_dev->sq kcalloc failed\n"); + goto err_sq; + } + + en_dev->rq = kcalloc(en_dev->max_queue_pairs, sizeof(*en_dev->rq), GFP_KERNEL); + if (unlikely(en_dev->rq == NULL)) + { + LOG_ERR("en_dev->rq kcalloc failed\n"); + goto err_rq; + } + + INIT_DELAYED_WORK(&en_dev->refill, refill_work); + + for (i = 0; i < en_dev->curr_queue_pairs; i++) + { + en_dev->rq[i].pages = NULL; + netif_napi_add(en_dev->netdev, &en_dev->rq[i].napi, virtnet_poll, NAPI_POLL_WEIGHT); + netif_tx_napi_add(en_dev->netdev, &en_dev->sq[i].napi, virtnet_poll_tx, NAPI_POLL_WEIGHT); + + sg_init_table(en_dev->rq[i].sg, ARRAY_SIZE(en_dev->rq[i].sg)); + ewma_pkt_len_init(&en_dev->rq[i].mrg_avg_pkt_len); + sg_init_table(en_dev->sq[i].sg, ARRAY_SIZE(en_dev->sq[i].sg)); + + u64_stats_init(&en_dev->rq[i].stats.syncp); + u64_stats_init(&en_dev->sq[i].stats.syncp); + } + + return 0; + +err_rq: + kfree(en_dev->sq); + en_dev->sq = NULL; +err_sq: + return -ENOMEM; +} + +/** + * virtqueue_set_affinity - setting affinity for a virtqueue + * @vq: the virtqueue + * @cpu_mask: the cpu no. + * + * Pay attention the function are best-effort: the affinity hint may not be set + * due to config support, irq type and sharing. + * + */ +int32_t virtqueue_set_affinity(struct virtqueue *vq, const struct cpumask *cpu_mask) +{ + if (!vq->callback) + { + LOG_ERR("vq->callback is null\n"); + return -EINVAL; + } + + return 0; +} + +void refill_work(struct work_struct *work) +{ + int32_t i = 0; + bool still_empty = false; + struct zxdh_en_device *en_dev = container_of(work, struct zxdh_en_device, refill.work); + + for (i = 0; i < en_dev->curr_queue_pairs; i++) + { + struct receive_queue *rq = &en_dev->rq[i]; + + napi_disable(&rq->napi); + still_empty = !try_fill_recv(en_dev->netdev, rq, GFP_KERNEL); + virtnet_napi_enable(rq->vq, &rq->napi); + + /* In theory, this can happen: if we don't get any buffers in + * we will *never* try to fill again. + */ + if (still_empty) + { + schedule_delayed_work(&en_dev->refill, HZ/2); + } + } +} + +int32_t dh_eq_vqs_vring_int(struct notifier_block *nb, unsigned long action, void *data) +{ + struct dh_eq_vq *eq_vq = container_of(nb, struct dh_eq_vq, irq_nb); + struct dh_eq_vqs *eq_vqs = container_of(eq_vq, struct dh_eq_vqs, vq_s); + struct list_head *item = NULL; + struct zxdh_pci_vq_info *info = NULL; + struct vring_virtqueue *vq = NULL; + + list_for_each(item, &eq_vqs->vqs) + { + info = list_entry(item, struct zxdh_pci_vq_info, node); + + vq = to_vvq(info->vq); + if (!more_used_packed(vq)) + { + continue; + } + + if (unlikely(vq->broken)) + { + LOG_ERR("vq:%d is broken\n", info->vq->phy_index); + continue; + } + + /* Just a hint for performance: so it's ok that this can be racy! */ + if (vq->event) + { + vq->event_triggered = true; + } + + if (vq->vq.callback) + { + vq->vq.callback(&vq->vq); + } + } + + return 0; +} + +static DEFINE_SPINLOCK(vp_find_lock); + +int32_t vp_find_vqs_msix(struct net_device *netdev, unsigned nvqs, + struct virtqueue *vqs[], vq_callback_t *callbacks[], + const char * const names[], const bool *ctx) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + int32_t err = 0; + uint16_t qidx = 0; + int32_t phy_index = -1; + + en_dev->vqs = kcalloc(nvqs, sizeof(*en_dev->vqs), GFP_KERNEL); + if (unlikely(en_dev->vqs == NULL)) + { + LOG_ERR("en_dev->vqs kcalloc failed\n"); + return -ENOMEM; + } + + spin_lock(&vp_find_lock); + for (qidx = 0; qidx < nvqs; ++qidx) + { + phy_index = en_dev->ops->get_phy_vq(en_dev->parent, qidx); + if(phy_index < 0) + { + LOG_ERR("get_phy_vq failed: %d\n", phy_index); + err = phy_index; + goto err; + } + en_dev->phy_index[qidx] = phy_index; + + vqs[qidx] = vp_setup_vq(netdev, qidx, callbacks[qidx], names[qidx], ctx ? ctx[qidx] : false, qidx); + if (IS_ERR_OR_NULL(vqs[qidx])) + { + err = PTR_ERR(vqs[qidx]); + LOG_ERR("vp_setup_vq failed: %d\n", err); + goto err; + } + + en_dev->ops->set_queue_enable(en_dev->parent, phy_index, true); + } + spin_unlock(&vp_find_lock); + return 0; + +err: + en_dev->ops->release_phy_vq(en_dev->parent, en_dev->phy_index, qidx+1); + spin_unlock(&vp_find_lock); + vp_del_vqs(netdev); + return err; +} + +/* How large should a single buffer be so a queue full of these can fit at + * least one full packet? + * Logic below assumes the mergeable buffer header is used. + */ +uint32_t mergeable_min_buf_len(struct zxdh_en_device *en_dev, struct virtqueue *vq) +{ + const uint32_t hdr_len = sizeof(struct zxdh_net_hdr); + uint32_t rq_size = virtqueue_get_vring_size(vq); + uint32_t packet_len = en_dev->netdev->max_mtu; + uint32_t buf_len = hdr_len + ETH_HLEN + VLAN_HLEN + packet_len; + uint32_t min_buf_len = DIV_ROUND_UP(buf_len, rq_size); + + return max(max(min_buf_len, hdr_len) - hdr_len, (uint32_t)GOOD_PACKET_LEN); +} + +void zxdh_en_recv_pkts(struct virtqueue *rvq) +{ + struct zxdh_en_priv *en_priv = netdev_priv(rvq->vdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + struct receive_queue *rq = &en_dev->rq[vq2rxq(rvq)]; + + virtqueue_napi_schedule(&rq->napi, rvq); +} + +void zxdh_en_xmit_pkts(struct virtqueue *tvq) +{ + struct zxdh_en_priv *en_priv = netdev_priv(tvq->vdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + struct napi_struct *napi = &en_dev->sq[vq2txq(tvq)].napi; + + /* Suppress further interrupts. */ + virtqueue_disable_cb(tvq); + + if (napi->weight) + { + virtqueue_napi_schedule(napi, tvq); + } + else + { + /* We were probably waiting for more output buffers. */ + netif_wake_subqueue(en_dev->netdev, vq2txq(tvq)); + en_dev->hw_stats.q_stats[vq2txq(tvq)].q_tx_wake++; + } +} + +int32_t virtnet_find_vqs(struct zxdh_en_device *en_dev) +{ + vq_callback_t **callbacks = NULL; + struct virtqueue **vqs = NULL; + int32_t ret = -ENOMEM; + int32_t i = 0; + int32_t total_vqs = 0; + const char **names = NULL; + bool *ctx = NULL; + + total_vqs = en_dev->max_queue_pairs * 2; + + /* Allocate space for find_vqs parameters */ + vqs = kcalloc(total_vqs, sizeof(*vqs), GFP_KERNEL); + if (unlikely(vqs == NULL)) + { + LOG_ERR("vqs kcalloc failed\n"); + goto err_vq; + } + + callbacks = kmalloc_array(total_vqs, sizeof(*callbacks), GFP_KERNEL); + if (unlikely(callbacks == NULL)) + { + LOG_ERR("callbacks kmalloc_array failed\n"); + goto err_callback; + } + + names = kmalloc_array(total_vqs, sizeof(*names), GFP_KERNEL); + if (unlikely(names == NULL)) + { + LOG_ERR("names kmalloc_array failed\n"); + goto err_names; + } + + ctx = kcalloc(total_vqs, sizeof(*ctx), GFP_KERNEL); + if (unlikely(ctx == NULL)) + { + LOG_ERR("ctx kmalloc failed\n"); + goto err_ctx; + } + + /* Allocate/initialize parameters for services send/receive virtqueues */ + for (i = 0; i < en_dev->max_queue_pairs; i++) + { + callbacks[rxq2vq(i)] = zxdh_en_recv_pkts; + callbacks[txq2vq(i)] = zxdh_en_xmit_pkts; + sprintf(en_dev->rq[i].name, "input.%d", i); + sprintf(en_dev->sq[i].name, "output.%d", i); + names[rxq2vq(i)] = en_dev->rq[i].name; + names[txq2vq(i)] = en_dev->sq[i].name; + if (ctx) + { + ctx[rxq2vq(i)] = true; + } + } + + ret = vp_find_vqs_msix(en_dev->netdev, total_vqs, vqs, callbacks, names, ctx); + if (ret) + { + LOG_ERR("vp_find_vqs_msix failed: %d\n", ret); + goto err_find; + } + + for (i = 0; i < en_dev->max_queue_pairs; i++) + { + en_dev->rq[i].vq = vqs[rxq2vq(i)]; + en_dev->rq[i].min_buf_len = mergeable_min_buf_len(en_dev, en_dev->rq[i].vq); + en_dev->sq[i].vq = vqs[txq2vq(i)]; + } + +err_find: + kfree(ctx); + ctx = NULL; +err_ctx: + kfree(names); + names = NULL; +err_names: + kfree(callbacks); + callbacks = NULL; +err_callback: + kfree(vqs); + vqs = NULL; +err_vq: + return ret; +} + +void virtnet_free_queues(struct zxdh_en_device *en_dev) +{ + int32_t i = 0; + + for (i = 0; i < en_dev->max_queue_pairs; i++) + { + netif_napi_del(&en_dev->rq[i].napi); + netif_napi_del(&en_dev->sq[i].napi); + } + + /* We called __netif_napi_del(), + * we need to respect an RCU grace period before freeing zxdev->rq + */ + synchronize_net(); + + kfree(en_dev->rq); + kfree(en_dev->sq); +} + +void *virtqueue_detach_unused_buf_packed(struct virtqueue *_vq) +{ + struct vring_virtqueue *vq = to_vvq(_vq); + uint32_t i = 0; + void *buf = NULL; + + START_USE(vq); + + for (i = 0; i < vq->packed.vring.num; i++) + { + if (!vq->packed.desc_state[i].data) + { + continue; + } + + /* detach_buf clears data, so grab it now. */ + buf = vq->packed.desc_state[i].data; + detach_buf_packed(vq, i, NULL); + END_USE(vq); + return buf; + } + + /* That should have freed everything. */ + BUG_ON(vq->vq.num_free != vq->packed.vring.num); + + END_USE(vq); + return NULL; +} + +void zxdh_free_unused_bufs(struct net_device *netdev) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + struct virtqueue *vq = NULL; + void *buf = NULL; + int32_t i = 0; + + for (i = 0; i < en_dev->max_queue_pairs; i++) + { + vq = en_dev->sq[i].vq; + while ((buf = virtqueue_detach_unused_buf_packed(vq)) != NULL) + { +#ifdef ZXDH_MSGQ + if (i == (en_dev->max_queue_pairs - 1)) + { + NEED_MSGQ(en_dev) + { + ZXDH_FREE_PTR(buf); + continue; + } + } +#endif + dev_kfree_skb(buf); + } + } + + for (i = 0; i < en_dev->max_queue_pairs; i++) + { + vq = en_dev->rq[i].vq; + while ((buf = virtqueue_detach_unused_buf_packed(vq)) != NULL) + { + put_page(virt_to_head_page(buf)); + } + } +} + +struct page *get_a_page(struct receive_queue *rq, gfp_t gfp_mask) +{ + struct page *p = rq->pages; + + if (p) + { + rq->pages = (struct page *)p->private; + /* clear private here, it is used to chain pages */ + p->private = 0; + } + else + { + p = alloc_page(gfp_mask); + } + return p; +} + +void _free_receive_bufs(struct zxdh_en_device *en_dev) +{ + int32_t i = 0; + + for (i = 0; i < en_dev->max_queue_pairs; i++) + { + while (en_dev->rq[i].pages) + { + __free_pages(get_a_page(&en_dev->rq[i], GFP_KERNEL), 0); + } + } +} + +void zxdh_free_receive_bufs(struct net_device *netdev) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + + rtnl_lock(); + _free_receive_bufs(en_dev); + rtnl_unlock(); +} + +void zxdh_free_receive_page_frags(struct net_device *netdev) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + int32_t i = 0; + + for (i = 0; i < en_dev->max_queue_pairs; i++) + { + if (en_dev->rq[i].alloc_frag.page) + { + put_page(en_dev->rq[i].alloc_frag.page); + } + } +} + +void zxdh_virtnet_del_vqs(struct net_device *netdev) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + + vp_del_vqs(netdev); + en_dev->ops->vqs_unbind_eqs(en_dev->parent, (en_dev->max_queue_pairs * 2 - 1)); + en_dev->ops->vqs_channel_unbind_handler(en_dev->parent, (en_dev->max_queue_pairs * 2 - 1)); + virtnet_free_queues(en_dev); +} + +void zxdh_vqs_uninit(struct net_device *netdev) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + + zxdh_vp_reset(netdev); + + cancel_delayed_work_sync(&en_dev->refill); + zxdh_free_unused_bufs(netdev); + zxdh_free_receive_bufs(netdev); + zxdh_free_receive_page_frags(netdev); + zxdh_virtnet_del_vqs(netdev); + en_dev->ops->release_phy_vq(en_dev->parent, en_dev->phy_index, en_dev->max_queue_pairs*2); +} + +int32_t zxdh_vqs_init(struct net_device *netdev) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + int32_t ret = 0; + + en_dev->hdr_len = sizeof(struct zxdh_net_hdr); + en_dev->any_header_sg = zxdh_has_feature(netdev, ZXDH_F_ANY_LAYOUT); + en_dev->netdev->needed_headroom = en_dev->hdr_len; + en_dev->max_queue_pairs = max_pairs; + memset(en_dev->phy_index, 0xFF, sizeof(en_dev->phy_index)); + + if (en_dev->ops->is_bond(en_dev->parent)) + { + en_dev->max_queue_pairs = ZXDH_BOND_ETH_MQ_PAIRS_NUM; + } + en_dev->curr_queue_pairs = en_dev->max_queue_pairs; + +#ifdef ZXDH_MSGQ + IS_MSGQ_DEV(en_dev) + { + en_dev->need_msgq = true; + en_dev->max_queue_pairs += ZXDH_PQ_PAIRS_NUM; + LOG_INFO("max_queue_pairs: %d\n", en_dev->max_queue_pairs); + } +#endif + + INIT_LIST_HEAD(&en_dev->vqs_list); + spin_lock_init(&en_dev->vqs_list_lock); + + INIT_LIST_HEAD(&en_dev->virtqueues); + spin_lock_init(&en_dev->lock); + + /* Allocate services send & receive queues */ + ret = virtnet_alloc_queues(en_dev); + if (ret) + { + LOG_ERR("virtnet_alloc_queues failed: %d\n", ret); + return ret; + } + + ret = virtnet_find_vqs(en_dev); + if (ret) + { + LOG_ERR("virtnet_find_vqs failed: %d\n", ret); + goto err_find_vqs; + } + + rtnl_lock(); + netif_set_real_num_tx_queues(en_dev->netdev, en_dev->curr_queue_pairs); + rtnl_unlock(); + rtnl_lock(); + netif_set_real_num_rx_queues(en_dev->netdev, en_dev->curr_queue_pairs); + rtnl_unlock(); + + return 0; + +err_find_vqs: + virtnet_free_queues(en_dev); + return ret; +} diff --git a/src/net/drivers/net/ethernet/dinghai/en_aux/queue.h b/src/net/drivers/net/ethernet/dinghai/en_aux/queue.h new file mode 100644 index 0000000..0c370d7 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_aux/queue.h @@ -0,0 +1,830 @@ +#ifndef __ZXDH_QUEUE_H__ +#define __ZXDH_QUEUE_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/*======================================================== + * 是否走1588处理流程（1588pd头宏开关）: + * 在提交代码时候这里注释掉，在使用1588功能时需要打开。 + *=========================================================*/ +// #define TIME_STAMP_1588 + +/*======================================================== + * 是否打开依赖PTP驱动的接口调用代码: + * 在提交代码时候这里注释掉，在实际调试时需要打开。 + *=========================================================*/ +#define PTP_DRIVER_INTERFACE_EN + +/**======================================================== + * 是否打开依赖os时间戳补丁接口的代码: + * 在提交代码时候这里注释掉，在实际调试时需要打开。 + *=========================================================*/ +/* #define CGEL_TSTAMP_2_PATCH_EN TODO 补丁不可用*/ + +/* 判断两个值是否相等，相等表示出错，打印信息后返回指定值 */ +#define CHECK_EQUAL_ERR(a, b, c, fmt, arg...) \ +do { \ + if (unlikely(a == b)) \ + { \ + LOG_ERR(fmt, ##arg); \ + return c; \ + } \ +} while(0) + +/* 判断两个值是否不等，不等表示出错，打印信息后返回指定值 */ +#define CHECK_UNEQUAL_ERR(a, b, c, fmt, arg...) \ +do { \ + if (unlikely(a != b)) \ + { \ + LOG_ERR(fmt, ##arg); \ + return c; \ + } \ +} while(0) + +#define ZXDH_MQ_PAIRS_NUM 8 +#define ZXDH_PQ_PAIRS_NUM 1 +#define ZXDH_MAX_PAIRS_NUM 128 +#define ZXDH_BOND_ETH_MQ_PAIRS_NUM 1 +#define ZXDH_MAX_QUEUES_NUM 4096 +#define ZXDH_PF_MAX_BAR_VAL 0x5 +#define ZXDH_PF_BAR0 0 +#define ZXDH_PF_MAX_DESC_NUM (32 * 1024) +#define ZXDH_PF_MIN_DESC_NUM 1024 +#define ZXDH_INDIR_RQT_SIZE 256 +#define ZXDH_NET_HASH_KEY_SIZE 40 + +#define VQM_HOST_BAR_OFFSET 0x0 +#define PHY_VQ_REG_OFFSET 0x5000 +#define LOCK_VQ_REG_OFFSET 0x90 +#define ZXDH_PHY_REG_BITS 32 +#define ZXDH_PF_LOCK_ENABLE_MASK 0x1 +#define ZXDH_PF_RELEASE_LOCK_VAL 0 +#define ZXDH_PF_GET_PHY_INDEX_DONE 1 +#define ZXDH_PF_GET_PHY_INDEX_BIT 1 +#define ZXDH_PF_WAIT_COUNT 2048 +#define ZXDH_PF_DELAY_US 10 +#define ZXDH_PF_RQ_TYPE 0 +#define ZXDH_PF_TQ_TYPE 1 +#define ZXDH_PF_POWER_INDEX2 2 + +#define MSG_PAYLOAD_FIX_FIELD 8 +#define MSG_CHAN_PF_MODULE_ID 0 +#define MSG_PAYLOAD_TYPE_WRITE 1 +#define MSG_PAYLOAD_FIELD_MSG_CHL 2 +#define MSG_PAYLOAD_FIELD_DATA_CHL 3 +#define MSG_PAYLOAD_MSG_CHL_SLEN 4 +#define MSG_RECV_BUF_LEN 6 + +#define ZXDH_MAC_NUM 6 +#define ZXDH_MAX_MTU 14000 +#define ZXDH_DEFAULT_MTU 1500 + +/* The feature bitmap for zxdh net */ +#define ZXDH_NET_F_MRG_RXBUF 15 /* Host can merge receive buffers. */ +#define ZXDH_NET_F_STATUS 16 /* net_config.status available */ +#define ZXDH_NET_F_CTRL_VQ 17 /* Control channel available */ +#define ZXDH_NET_F_MQ 22 /* Device supports Receive Flow Steering */ +#define ZXDH_F_ANY_LAYOUT 27 /* Can the device handle any descriptor layout? */ +#define ZXDH_RING_F_INDIRECT_DESC 28 /* We support indirect buffer descriptors */ + +/* The Guest publishes the used index for which it expects an interrupt + * at the end of the avail ring. Host should ignore the avail->flags field. */ +/* The Host publishes the avail index for which it expects a kick + * at the end of the used ring. Guest should ignore the used->flags field. */ +#define ZXDH_RING_F_EVENT_IDX 29 + +#define ZXDH_F_VERSION_1 32 /* v1.0 compliant */ + +/* + * If clear - device has the platform DMA (e.g. IOMMU) bypass quirk feature. + * If set - use platform DMA tools to access the memory. + * + * Note the reverse polarity (compared to most other features), + * this is for compatibility with legacy systems. + */ +#define ZXDH_F_ACCESS_PLATFORM 33 + +/* This feature indicates support for the packed virtqueue layout. */ +#define ZXDH_F_RING_PACKED 34 + +/* + * This feature indicates that memory accesses by the driver and the + * device are ordered in a way described by the platform. + */ +#define ZXDH_F_ORDER_PLATFORM 36 + +/* This marks a buffer as continuing via the next field. */ +#define VRING_DESC_F_NEXT 1 +/* This marks a buffer as write-only (otherwise read-only). */ +#define VRING_DESC_F_WRITE 2 +/* This means the buffer contains a list of buffer descriptors. */ +#define VRING_DESC_F_INDIRECT 4 + +/* + * Mark a descriptor as available or used in packed ring. + * Notice: they are defined as shifts instead of shifted values. + */ +#define VRING_PACKED_DESC_F_AVAIL 7 +#define VRING_PACKED_DESC_F_USED 15 + +/* The Host uses this in used->flags to advise the Guest: don't kick me when + * you add a buffer. It's unreliable, so it's simply an optimization. Guest + * will still kick if it's out of buffers. */ +#define VRING_USED_F_NO_NOTIFY 1 +/* The Guest uses this in avail->flags to advise the Host: don't interrupt me + * when you consume a buffer. It's unreliable, so it's simply an + * optimization. */ +#define VRING_AVAIL_F_NO_INTERRUPT 1 + +/* Enable events in packed ring. */ +#define VRING_PACKED_EVENT_FLAG_ENABLE 0x0 +/* Disable events in packed ring. */ +#define VRING_PACKED_EVENT_FLAG_DISABLE 0x1 +/* + * Enable events for a specific descriptor in packed ring. + * (as specified by Descriptor Ring Change Event Offset/Wrap Counter). + * Only valid if ZXDH_RING_F_EVENT_IDX has been negotiated. + */ +#define VRING_PACKED_EVENT_FLAG_DESC 0x2 + +/* + * Wrap counter bit shift in event suppression structure + * of packed ring. + */ +#define VRING_PACKED_EVENT_F_WRAP_CTR 15 + +/* Alignment requirements for vring elements */ +#define VRING_AVAIL_ALIGN_SIZE 2 +#define VRING_USED_ALIGN_SIZE 4 +#define VRING_DESC_ALIGN_SIZE 16 + +#define MRG_CTX_HEADER_SHIFT 22 + + +/* FIXME: MTU in config. */ +#define GOOD_PACKET_LEN (ETH_HLEN + VLAN_HLEN + ETH_DATA_LEN) +#define GOOD_COPY_LEN 128 + + +#define TX_PORT_NP 0x00 +#define TX_PORT_DRS 0x01 +#define TX_PORT_DTP 0x02 +#define HDR_2B_UNIT 2 +#define ENABLE_PI_FLAG_32B 0x1 +#define DISABLE_PI_FIELD_PARSE 0x80 +#define IPV4_TYPE 0x0 +#define IPV6_TYPE 0x1 +#define NOT_IP_TYPE 0x2 +#define PKT_SRC_NP 0x0 +#define PKT_SRC_CPU 0x1 +#define PCODE_IP 0x1 +#define PCODE_TCP 0x2 +#define PCODE_UDP 0x3 +#define INVALID_ETH_PORT_ID 0xff +#define ETH_MTU_4B_UNIT 4 +#define IP_FRG_CSUM_FLAG 0x8000 +#define NOT_IP_FRG_CSUM_FLAG 0x6000 +#define TCP_FRG_CSUM_FLAG 0x24 +#define NOT_TCP_FRG_CSUM_FLAG 0x30 +#define HDR_2B_UNIT 2 + +#define HDR_BUFFER_LEN 100 +#define IP_BASE_HLEN 20 +#define IPV6_BASE_HLEN 40 +#define TCP_BASE_HLEN 20 + +#define OUTER_IP_CHECKSUM_OFFSET (12) +#define INNER_IP_CHECKSUM_OFFSET (15) +#define INNER_L4_CHECKSUM_OFFSET (2) +#define PI_HDR_L3_CHKSUM_ERROR_CODE (0xff) +#define PI_HDR_L4_CHKSUM_ERROR_CODE (0xff) +#define OUTER_IP_CHKSUM_ERROT_CODE (0x20) + +#define RX_VLAN_STRIPED_MASK (1 << 4) +#define RX_QINQ_STRIPED_MASK (1 << 14) +#define RX_TPID_VLAN_ID_MASK (0xfff) + +/* PD header offload flags */ +#define PANELID_EN (1 << 15) + +/* PD header sk_prio */ +#define ZXDH_DCBNL_SET_SK_PRIO(sk_prio) ((0x7 & sk_prio) << 8) + +/* + * __vqm{16,32,64} have the following meaning: + * - __u{16,32,64} for zxdh devices in legacy mode, accessed in native endian + * - __le{16,32,64} for standard-compliant zxdh devices + */ +typedef __u16 __bitwise __vqm16; +typedef __u32 __bitwise __vqm32; +typedef __u64 __bitwise __vqm64; + + +/* Constants for MSI-X */ +/* Use first vector for configuration changes, second and the rest for + * virtqueues Thus, we need at least 2 vectors for MSI. */ +enum +{ + VP_MSIX_CONFIG_VECTOR = 0, + VP_MSIX_VQ_VECTOR = 1, +}; + + +struct vring_packed_desc_event +{ + /* Descriptor Ring Change Event Offset/Wrap Counter. */ + __le16 off_wrap; + /* Descriptor Ring Change Event Flags. */ + __le16 flags; +}; + +struct vring_packed_desc +{ + /* Buffer Address. */ + __le64 addr; + /* Buffer Length. */ + __le32 len; + /* Buffer ID. */ + __le16 id; + /* The flags depending on descriptor type. */ + __le16 flags; +}; + +struct vring_desc_state_packed +{ + void *data; /* Data for callback. */ + struct vring_packed_desc *indir_desc; /* Indirect descriptor, if any. */ + uint16_t num; /* Descriptor list length. */ + uint16_t last; /* The last desc state in a list. */ +}; + +struct vring_desc_extra +{ + dma_addr_t addr; /* Buffer DMA addr. */ + uint32_t len; /* Buffer length. */ + uint16_t flags; /* Descriptor flags. */ + uint16_t next; /* The next desc state in a list. */ +}; + +union pkt_type_t +{ + uint8_t pkt_type; + struct + { + uint8_t pkt_code:5; + uint8_t pkt_src:1; + uint8_t ip_type:2; + }type_ctx; +}__attribute__((packed)); + +struct pi_net_hdr +{ + uint8_t bttl_pi_len; + union pkt_type_t pt; + uint16_t vlan_id; + uint32_t ipv6_exp_flags; + uint16_t hdr_l3_offset; + uint16_t hdr_l4_offset; + uint8_t eth_port_id; + uint8_t pkt_action_flag2; + uint16_t pkt_action_flag1; + uint8_t sa_index[8]; + uint8_t error_code[2]; + uint8_t rsv[6]; +}__attribute__((packed)); + +struct pd_net_hdr_tx +{ +#define TXCAP_STAG_INSERT_EN_BIT (1 << 14) +#define TXCAP_CTAG_INSERT_EN_BIT (1 << 13) +#define DELAY_STATISTICS_INSERT_EN_BIT (1 << 7) + uint16_t ol_flag; + uint8_t rsv; + uint8_t panel_id; + uint8_t tag_idx; + uint8_t tag_data; + uint16_t vfid; + struct { + uint16_t tpid; + uint16_t tci; + } svlan; + struct { + uint16_t tpid; + uint16_t tci; + } cvlan; +}__attribute__((packed)); + + +struct pd_net_hdr_rx +{ +#define RX_PD_HEAD_VLAN_STRIP_BIT (1 << 28) + uint32_t flags; + uint32_t rss_hash; + uint32_t fd; + uint16_t striped_stci; + uint16_t striped_ctci; + uint8_t tag_idx; + uint8_t tag_data; + uint16_t src_port; + uint16_t outer_pkt_type; + uint16_t inner_pkt_type; +}__attribute__((packed)); + +/* zxdh net header */ +struct zxdh_net_hdr +{ + uint8_t tx_port; //bit7:2 rsv; bit1:0 00:np, 01:DRS, 10:DTP + uint8_t pd_len; //bit7 rsv; bit6:0 L2报文前的描述符长度，以2B为单位 + uint8_t num_buffers; //表示接收方向num buffers字段 + uint8_t rsv; //保留 + + struct pi_net_hdr pi_hdr; + struct pd_net_hdr_tx pd_hdr; +}__attribute__((packed)); + +struct zxdh_net_1588_hdr +{ + uint8_t tx_port; //bit7:2 rsv; bit1:0 00:np, 01:DRS, 10:DTP + uint8_t pd_len; //bit7 rsv; bit6:0 L2报文前的描述符长度，以2B为单位 + uint8_t num_buffers; //表示接收方向num buffers字段 + uint8_t rsv; //保留 + + struct pi_net_hdr pi_hdr; + struct pd_net_hdr_tx pd_hdr; + + uint8_t ptp_type[3]; /* 低bit0-16预留，bit17-19 pkt_type, bit23 ptp_udp */ + uint8_t ts_offset; + uint32_t cpu_tx; + uint8_t port; /* egress_port/ingress_port, L4报文此字段无用 */ + uint8_t rsv1[4]; + uint8_t sec_1588_key[3]; +}__attribute__((packed)); + +struct zxdh_net_hdr_rcv +{ + uint8_t tx_port; //bit7:2 rsv; bit1:0 00:np, 01:DRS, 10:DTP + uint8_t pd_len; //bit7 rsv; bit6:0 L2报文前的描述符长度，以2B为单位 + uint8_t num_buffers; //表示接收方向num buffers字段 + uint8_t rsv; //保留 + + struct pi_net_hdr pi_hdr; + struct pd_net_hdr_rx pd_hdr; +}__attribute__((packed)); + +struct zxdh_net_1588_hdr_rcv +{ + uint8_t tx_port; //bit7:2 rsv; bit1:0 00:np, 01:DRS, 10:DTP + uint8_t pd_len; //bit7 rsv; bit6:0 L2报文前的描述符长度，以2B为单位 + uint8_t num_buffers; //表示接收方向num buffers字段 + uint8_t rsv; //保留 + + struct pi_net_hdr pi_hdr; + struct pd_net_hdr_rx pd_hdr; + + uint8_t egress_port; + uint8_t ptp_type[2]; /* 低bit0-8预留，bit9-11 pkt_type, bit 12-14预留，bit15 ptp_udp */ + uint8_t ts_offset; + uint32_t rx_ts; +}__attribute__((packed)); + +#ifdef DEBUG +/* For development, we want to crash whenever the ring is screwed. */ +#define BAD_RING(_vq, fmt, args...) \ + do { \ + LOG_ERR("%s:"fmt, (_vq)->vq.name, ##args); \ + BUG(); \ + } while (0) +/* Caller is supposed to guarantee no reentry. */ +#define START_USE(_vq) \ + do { \ + if ((_vq)->in_use) \ + panic("%s:in_use = %i\n", \ + (_vq)->vq.name, (_vq)->in_use); \ + (_vq)->in_use = __LINE__; \ + } while (0) +#define END_USE(_vq) \ + do { BUG_ON(!(_vq)->in_use); (_vq)->in_use = 0; } while(0) +#define LAST_ADD_TIME_UPDATE(_vq) \ + do { \ + ktime_t now = ktime_get(); \ + \ + /* No kick or get, with .1 second between? Warn. */ \ + if ((_vq)->last_add_time_valid) \ + WARN_ON(ktime_to_ms(ktime_sub(now, \ + (_vq)->last_add_time)) > 100); \ + (_vq)->last_add_time = now; \ + (_vq)->last_add_time_valid = true; \ + } while (0) +#define LAST_ADD_TIME_CHECK(_vq) \ + do { \ + if ((_vq)->last_add_time_valid) { \ + WARN_ON(ktime_to_ms(ktime_sub(ktime_get(), \ + (_vq)->last_add_time)) > 100); \ + } \ + } while (0) +#define LAST_ADD_TIME_INVALID(_vq) \ + ((_vq)->last_add_time_valid = false) +#else +#define BAD_RING(_vq, fmt, args...) \ + do { \ + LOG_ERR("%s:"fmt, (_vq)->vq.name, ##args); \ + (_vq)->broken = true; \ + } while (0) +#define START_USE(vq) +#define END_USE(vq) +#define LAST_ADD_TIME_UPDATE(vq) +#define LAST_ADD_TIME_CHECK(vq) +#define LAST_ADD_TIME_INVALID(vq) +#endif + + +#define vqm_store_mb(weak_barriers, p, v) \ +do { \ + if (weak_barriers) { \ + virt_store_mb(*p, v); \ + } else { \ + WRITE_ONCE(*p, v); \ + mb(); \ + } \ +} while (0) \ + + +/* This is the PCI capability header: */ +struct zxdh_pci_cap +{ + __u8 cap_vndr; /* Generic PCI field: PCI_CAP_ID_VNDR */ + __u8 cap_next; /* Generic PCI field: next ptr. */ + __u8 cap_len; /* Generic PCI field: capability length */ + __u8 cfg_type; /* Identifies the structure. */ + __u8 bar; /* Where to find it. */ + __u8 id; /* Multiple capabilities of the same type */ + __u8 padding[2]; /* Pad to full dword. */ + __le32 offset; /* Offset within bar. */ + __le32 length; /* Length of the structure, in bytes. */ +}; + +struct zxdh_pci_notify_cap +{ + struct zxdh_pci_cap cap; + __le32 notify_off_multiplier; /* Multiplier for queue_notify_off. */ +}; + +struct virtqueue +{ + struct list_head list; + void (*callback)(struct virtqueue *vq); + const char *name; + struct net_device *vdev; + uint32_t index; + uint32_t phy_index; + uint32_t num_free; + void *priv; +}; + +/* custom queue ring descriptors: 16 bytes. These can chain together via "next". */ +struct vring_desc +{ + /* Address (guest-physical). */ + uint64_t addr; + /* Length. */ + uint32_t len; + /* The flags as indicated above. */ + uint16_t flags; + /* We chain unused descriptors via this, too */ + uint16_t next; +}; + +struct vring_avail +{ + uint16_t flags; + uint16_t idx; + uint16_t ring[]; +}; + +/* u32 is used here for ids for padding reasons. */ +struct vring_used_elem +{ + /* Index of start of used descriptor chain. */ + uint32_t id; + /* Total length of the descriptor chain which was used (written to) */ + uint32_t len; +}; + +typedef struct vring_used_elem __attribute__((aligned(VRING_USED_ALIGN_SIZE))) + vring_used_elem_t; + +struct vring_used +{ + uint16_t flags; + uint16_t idx; + vring_used_elem_t ring[]; +}; + +typedef struct vring_desc __attribute__((aligned(VRING_DESC_ALIGN_SIZE))) + vring_desc_t; +typedef struct vring_avail __attribute__((aligned(VRING_AVAIL_ALIGN_SIZE))) + vring_avail_t; +typedef struct vring_used __attribute__((aligned(VRING_USED_ALIGN_SIZE))) + vring_used_t; + +struct vring +{ + uint32_t num; + + vring_desc_t *desc; + + vring_avail_t *avail; + + vring_used_t *used; +}; + +struct vring_virtqueue +{ + struct virtqueue vq; + + /* Is this a packed ring? */ + bool packed_ring; + + /* Is DMA API used? */ + bool use_dma_api; + + /* Can we use weak barriers? */ + bool weak_barriers; + + /* Other side has made a mess, don't try any more. */ + bool broken; + + /* Host supports indirect buffers */ + bool indirect; + + /* Host publishes avail event idx */ + bool event; + + /* Head of free buffer list. */ + uint32_t free_head; + /* Number we've added since last sync. */ + uint32_t num_added; + + /* Last used index we've seen. */ + uint16_t last_used_idx; + + /* Hint for event idx: already triggered no need to disable. */ + bool event_triggered; + + /* Available for packed ring */ + struct + { + /* Actual memory layout for this queue. */ + struct + { + uint32_t num; + struct vring_packed_desc *desc; + struct vring_packed_desc_event *driver; + struct vring_packed_desc_event *device; + } vring; + + /* Driver ring wrap counter. */ + bool avail_wrap_counter; + + /* Device ring wrap counter. */ + bool used_wrap_counter; + + /* Avail used flags. */ + uint16_t avail_used_flags; + + /* Index of the next avail descriptor. */ + uint16_t next_avail_idx; + + /* + * Last written value to driver->flags in + * guest byte order. + */ + uint16_t event_flags_shadow; + + /* Per-descriptor state. */ + struct vring_desc_state_packed *desc_state; + struct vring_desc_extra *desc_extra; + + /* DMA address and size information */ + dma_addr_t ring_dma_addr; + dma_addr_t driver_event_dma_addr; + dma_addr_t device_event_dma_addr; + size_t ring_size_in_bytes; + size_t event_size_in_bytes; + } packed; + + /* How to notify other side. FIXME: commonalize hcalls! */ + bool (*notify)(struct virtqueue *vq); + + /* DMA, allocation, and size information */ + bool we_own_ring; + +#ifdef DEBUG + /* They're supposed to lock for us. */ + uint32_t in_use; + + /* Figure out if their kicks are too delayed. */ + bool last_add_time_valid; + ktime_t last_add_time; +#endif +}; + +struct zxdh_pci_vq_info +{ + /* the actual virtqueue */ + struct virtqueue *vq; + + /* the list node for the virtqueues list */ + struct list_head node; + + /* channel num map 1-1 to vector*/ + unsigned channel_num; +}; + +struct virtnet_stat_desc +{ + char desc[ETH_GSTRING_LEN]; + size_t offset; +}; + +struct virtnet_sq_stats +{ + struct u64_stats_sync syncp; + uint64_t packets; + uint64_t bytes; + uint64_t xdp_tx; + uint64_t xdp_tx_drops; + uint64_t kicks; + uint64_t tx_timeouts; +}; + +struct virtnet_rq_stats +{ + struct u64_stats_sync syncp; + uint64_t packets; + uint64_t bytes; + uint64_t drops; + uint64_t xdp_packets; + uint64_t xdp_tx; + uint64_t xdp_redirects; + uint64_t xdp_drops; + uint64_t kicks; +}; +#define VIRTNET_SQ_STAT(m) offsetof(struct virtnet_sq_stats, m) +#define VIRTNET_RQ_STAT(m) offsetof(struct virtnet_rq_stats, m) + +static const struct virtnet_stat_desc virtnet_sq_stats_desc[] = +{ + { "packets", VIRTNET_SQ_STAT(packets) }, + { "bytes", VIRTNET_SQ_STAT(bytes) }, + { "xdp_tx", VIRTNET_SQ_STAT(xdp_tx) }, + { "xdp_tx_drops", VIRTNET_SQ_STAT(xdp_tx_drops) }, + { "kicks", VIRTNET_SQ_STAT(kicks) }, + { "tx_timeouts", VIRTNET_SQ_STAT(tx_timeouts) }, +}; + +static const struct virtnet_stat_desc virtnet_rq_stats_desc[] = +{ + { "packets", VIRTNET_RQ_STAT(packets) }, + { "bytes", VIRTNET_RQ_STAT(bytes) }, + { "drops", VIRTNET_RQ_STAT(drops) }, + { "xdp_packets", VIRTNET_RQ_STAT(xdp_packets) }, + { "xdp_tx", VIRTNET_RQ_STAT(xdp_tx) }, + { "xdp_redirects", VIRTNET_RQ_STAT(xdp_redirects) }, + { "xdp_drops", VIRTNET_RQ_STAT(xdp_drops) }, + { "kicks", VIRTNET_RQ_STAT(kicks) }, +}; + +#define VIRTNET_SQ_STATS_LEN ARRAY_SIZE(virtnet_sq_stats_desc) +#define VIRTNET_RQ_STATS_LEN ARRAY_SIZE(virtnet_rq_stats_desc) + +/* RX packet size EWMA. The average packet size is used to determine the packet + * buffer size when refilling RX rings. As the entire RX ring may be refilled + * at once, the weight is chosen so that the EWMA will be insensitive to short- + * term, transient changes in packet size. + */ +DECLARE_EWMA(pkt_len, 0, 64) + + +/* Internal representation of a send virtqueue */ +struct send_queue +{ + /* Virtqueue associated with this send _queue */ + struct virtqueue *vq; + + /* TX: fragments + linear part + custom queue header */ + struct scatterlist sg[MAX_SKB_FRAGS + 2]; + + /* Name of the send queue: output.$index */ + char name[40]; + + struct virtnet_sq_stats stats; + + struct napi_struct napi; + + uint8_t hdr_buf[HDR_BUFFER_LEN]; +}; + +/* Internal representation of a receive virtqueue */ +struct receive_queue +{ + /* Virtqueue associated with this receive_queue */ + struct virtqueue *vq; + + struct napi_struct napi; + + struct bpf_prog __rcu *xdp_prog; + + struct virtnet_rq_stats stats; + + /* Chain pages by the private ptr. */ + struct page *pages; + + /* Average packet length for mergeable receive buffers. */ + struct ewma_pkt_len mrg_avg_pkt_len; //todo + + /* Page frag for packet buffer allocation. */ + struct page_frag alloc_frag; + + /* RX: fragments + linear part + custom queue header */ + struct scatterlist sg[MAX_SKB_FRAGS + 2]; + + /* Min single buffer size for mergeable buffers case. */ + uint32_t min_buf_len; + + /* Name of this receive queue: input.$index */ + char name[40]; + + struct xdp_rxq_info xdp_rxq; +}; + +#define to_vvq(_vq) container_of(_vq, struct vring_virtqueue, vq) + +typedef void vq_callback_t(struct virtqueue *); + + +void zxdh_print_vring_info(struct virtqueue *vq, uint32_t desc_index, uint32_t desc_num); +void virtnet_napi_enable(struct virtqueue *vq, struct napi_struct *napi); +void virtnet_napi_tx_enable(struct net_device *netdev, struct virtqueue *vq, struct napi_struct *napi); +void virtnet_napi_tx_disable(struct napi_struct *napi); +void refill_work(struct work_struct *work); +int virtnet_poll(struct napi_struct *napi, int budget); +int virtnet_poll_tx(struct napi_struct *napi, int budget); +int32_t txq2vq(int32_t txq); +int32_t rxq2vq(int32_t rxq); +uint16_t vqm16_to_cpu(struct net_device *netdev, __vqm16 val); +uint8_t vp_get_status(struct net_device *netdev); +void vp_set_status(struct net_device *netdev, uint8_t status); +void vp_set_reset_status(struct net_device *netdev, uint8_t status); +void zxdh_add_status(struct net_device *netdev, uint32_t status); +void zxdh_vp_enable_cbs(struct net_device *netdev); +void zxdh_vp_disable_cbs(struct net_device *netdev); +void zxdh_vp_reset(struct net_device *netdev); +void vring_free_queue(struct net_device *netdev, size_t size, void *queue, dma_addr_t dma_handle); +netdev_tx_t start_xmit(struct sk_buff *skb, struct net_device *netdev); +bool try_fill_recv(struct net_device *netdev, struct receive_queue *rq, gfp_t gfp); +inline struct zxdh_net_hdr *skb_vnet_hdr(struct sk_buff *skb); +int32_t virtqueue_add_outbuf(struct virtqueue *vq, struct scatterlist *sg, uint32_t num, void *data, gfp_t gfp); +void virtqueue_disable_cb(struct virtqueue *_vq); +void free_old_xmit_skbs(struct net_device *netdev, struct send_queue *sq, bool in_napi); +bool virtqueue_enable_cb_delayed(struct virtqueue *_vq); +bool virtqueue_kick_prepare_packed(struct virtqueue *_vq); +bool virtqueue_notify(struct virtqueue *_vq); +void zxdh_pf_features_init(struct net_device *netdev); +bool zxdh_has_feature(struct net_device *netdev, uint32_t fbit); +bool zxdh_has_status(struct net_device *netdev, uint32_t sbit); +void zxdh_free_unused_bufs(struct net_device *netdev); +void zxdh_free_receive_bufs(struct net_device *netdev); +void zxdh_free_receive_page_frags(struct net_device *netdev); +void zxdh_virtnet_del_vqs(struct net_device *netdev); +void zxdh_vqs_uninit(struct net_device *netdev); +int32_t zxdh_vqs_init(struct net_device *netdev); +int32_t dh_eq_vqs_vring_int(struct notifier_block *nb, unsigned long action, void *data); +int32_t vq2rxq(struct virtqueue *vq); +void *virtqueue_get_buf(struct virtqueue *_vq, uint32_t *len); +void *virtqueue_get_buf_ctx_packed(struct virtqueue *_vq, uint32_t *len, void **ctx); +uint32_t virtqueue_get_vring_size(struct virtqueue *_vq); +void virtqueue_napi_complete(struct napi_struct *napi, struct virtqueue *vq, int32_t processed); +int32_t virtqueue_add_inbuf_ctx(struct virtqueue *vq, + struct scatterlist *sg, uint32_t num, + void *data, + void *ctx, + gfp_t gfp); +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/en_ethtool/ethtool.c b/src/net/drivers/net/ethernet/dinghai/en_ethtool/ethtool.c new file mode 100644 index 0000000..3794403 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_ethtool/ethtool.c @@ -0,0 +1,1997 @@ +#include +#include +#include +#include +#include +#include +#include "../en_aux/queue.h" +#include "../en_aux.h" +#include "../en_aux/en_cmd.h" +#include "../en_np/table/include/dpp_tbl_api.h" +#include "ethtool.h" +#include "linux/dinghai/dh_cmd.h" +#include "../msg_common.h" + +MODULE_LICENSE("Dual BSD/GPL"); + +#define PF_DRV_NAME "zxdh_pf" +#define VF_DRV_NAME "zxdh_vf" +#define DRV_NAME(VPORT) (IS_PF(VPORT) ? PF_DRV_NAME : VF_DRV_NAME) +#define ETHTOOL_LINK_MODE_MASK_MAX_KERNEL_NBITS 32 +#define MAX_DRV_NAME_LEN 32 +#define MAX_DRV_VERSION_LEN 32 +#define PCI_BUS(PCI_BDF) ((PCI_BDF >> 8) & 0xff) + +#define ZXDH_EN_LINK_MODE_ADD(ks, name, sup) \ +do \ +{ \ + if (sup) \ + { \ + ethtool_link_ksettings_add_link_mode((ks), supported, name); \ + } \ + else \ + { \ + ethtool_link_ksettings_add_link_mode((ks), advertising, name); \ + } \ +} while (0) + +#define ZXDH_EN_SPEED_MODE_TO_ETHTOOL(en_dev, bit, sup) \ + sup ? ((en_dev->supported_speed_modes) & BIT(bit)) == BIT(bit) : \ + ((en_dev->advertising_speed_modes) & BIT(bit)) == BIT(bit) + +#define GET_FEC_LINK_FLAG (0) +#define GET_FEC_CFG_FLAG (1) +#define GET_FEC_CAP_FLAG (2) + +static const uint32_t fec_2_ethtool_fecparam[] = +{ + [SPM_FEC_NONE] = ETHTOOL_FEC_OFF, + [SPM_FEC_BASER] = ETHTOOL_FEC_BASER, + [SPM_FEC_RS528] = ETHTOOL_FEC_RS, + [SPM_FEC_RS544] = ETHTOOL_FEC_RS, +}; + +static uint32_t zxdh_en_fec_to_ethtool_fecparam(uint32_t fec_mode, uint32_t flag) +{ + int32_t i; + uint32_t fecparam_cap = 0; + + if(!fec_mode) + { + if(flag == GET_FEC_LINK_FLAG) + return ETHTOOL_FEC_NONE; + else if(flag == GET_FEC_CFG_FLAG) + return ETHTOOL_FEC_AUTO; + } + + for(i = 0; i < ARRAY_SIZE(fec_2_ethtool_fecparam); i++) + { + if(fec_mode & BIT(i)) + { + fecparam_cap |= fec_2_ethtool_fecparam[i]; + } + } + + if(flag == GET_FEC_CAP_FLAG) + fecparam_cap |= ETHTOOL_FEC_AUTO; + + return fecparam_cap; +} + +static void zxdh_en_fec_to_link_ksettings(uint32_t fec_mode, + struct ethtool_link_ksettings *ks, + bool sup) +{ + if(fec_mode & BIT(SPM_FEC_NONE)) + ZXDH_EN_LINK_MODE_ADD(ks, FEC_NONE, sup); + if(fec_mode & BIT(SPM_FEC_BASER)) + ZXDH_EN_LINK_MODE_ADD(ks, FEC_BASER, sup); + if(fec_mode & BIT(SPM_FEC_RS528) || + fec_mode & BIT(SPM_FEC_RS544)) + ZXDH_EN_LINK_MODE_ADD(ks, FEC_RS, sup); +} + +static void zxdh_en_fec_link_ksettings_get(struct zxdh_en_device *en_dev, + struct ethtool_link_ksettings *ks) +{ + int32_t ret; + uint32_t fec_cap; + uint32_t fec_active; + + ret = zxdh_en_fec_mode_get(en_dev, &fec_cap, NULL, &fec_active); + if(ret) + { + LOG_ERR("zxdh_en_fec_mode_get failed!\n"); + return; + } + //LOG_INFO("fec_cap=0x%x, fec_active=0x%x\n", fec_cap, fec_active); + + zxdh_en_fec_to_link_ksettings(fec_cap, ks, true); + zxdh_en_fec_to_link_ksettings(fec_active, ks, false); + + return; +} + +static void zxdh_en_pause_link_ksettings_get(struct zxdh_en_device *en_dev, + struct ethtool_link_ksettings *ks) +{ + int32_t err; + uint32_t fc_mode; + + err = zxdh_en_fc_mode_get(en_dev, &fc_mode); + if(err != 0) + { + LOG_ERR("zxdh_en_fc_mode_get failed!\n"); + return; + } + + ZXDH_EN_LINK_MODE_ADD(ks, Pause, true); + + if(fc_mode == BIT(SPM_FC_PAUSE_FULL)) + ZXDH_EN_LINK_MODE_ADD(ks, Pause, false); + else if(fc_mode == BIT(SPM_FC_PAUSE_RX) || fc_mode == BIT(SPM_FC_PAUSE_TX)) + ZXDH_EN_LINK_MODE_ADD(ks, Asym_Pause, false); + + return; +} + +static void zxdh_en_phytype_to_ethtool(struct zxdh_en_device *en_dev, struct ethtool_link_ksettings *ks, bool sup) +{ + //0x20000020020 + if (ZXDH_EN_SPEED_MODE_TO_ETHTOOL(en_dev, SPM_SPEED_1X_1G, sup)) + { + ZXDH_EN_LINK_MODE_ADD(ks, 1000baseT_Full, sup); + ZXDH_EN_LINK_MODE_ADD(ks, 1000baseKX_Full, sup); + ZXDH_EN_LINK_MODE_ADD(ks, 1000baseX_Full, sup); + } + + //0x5C0000081000 + if (ZXDH_EN_SPEED_MODE_TO_ETHTOOL(en_dev, SPM_SPEED_1X_10G, sup)) + { + ZXDH_EN_LINK_MODE_ADD(ks, 10000baseT_Full, sup); + ZXDH_EN_LINK_MODE_ADD(ks, 10000baseKR_Full, sup); + ZXDH_EN_LINK_MODE_ADD(ks, 10000baseCR_Full, sup); + ZXDH_EN_LINK_MODE_ADD(ks, 10000baseSR_Full, sup); + ZXDH_EN_LINK_MODE_ADD(ks, 10000baseLR_Full, sup); + ZXDH_EN_LINK_MODE_ADD(ks, 10000baseER_Full, sup); + } + + //0x380000000 + if (ZXDH_EN_SPEED_MODE_TO_ETHTOOL(en_dev, SPM_SPEED_1X_25G, sup)) + { + ZXDH_EN_LINK_MODE_ADD(ks, 25000baseCR_Full, sup); + ZXDH_EN_LINK_MODE_ADD(ks, 25000baseKR_Full, sup); + ZXDH_EN_LINK_MODE_ADD(ks, 25000baseSR_Full, sup); + } + + //0x10C00000000 + if (ZXDH_EN_SPEED_MODE_TO_ETHTOOL(en_dev, SPM_SPEED_1X_50G, sup)) + { + ZXDH_EN_LINK_MODE_ADD(ks, 50000baseCR2_Full, sup); + ZXDH_EN_LINK_MODE_ADD(ks, 50000baseKR2_Full, sup); + ZXDH_EN_LINK_MODE_ADD(ks, 50000baseSR2_Full, sup); + } + + //0x7800000 + if (ZXDH_EN_SPEED_MODE_TO_ETHTOOL(en_dev, SPM_SPEED_4X_40G, sup)) + { + ZXDH_EN_LINK_MODE_ADD(ks, 40000baseKR4_Full, sup); + ZXDH_EN_LINK_MODE_ADD(ks, 40000baseCR4_Full, sup); + ZXDH_EN_LINK_MODE_ADD(ks, 40000baseSR4_Full, sup); + ZXDH_EN_LINK_MODE_ADD(ks, 40000baseLR4_Full, sup); + } + + //0xF000000000 + if (ZXDH_EN_SPEED_MODE_TO_ETHTOOL(en_dev, SPM_SPEED_4X_100G, sup)) + { + ZXDH_EN_LINK_MODE_ADD(ks, 100000baseKR4_Full, sup); + ZXDH_EN_LINK_MODE_ADD(ks, 100000baseSR4_Full, sup); + ZXDH_EN_LINK_MODE_ADD(ks, 100000baseCR4_Full, sup); + ZXDH_EN_LINK_MODE_ADD(ks, 100000baseLR4_ER4_Full, sup); + } + + //0x1E00000000000000 + if (ZXDH_EN_SPEED_MODE_TO_ETHTOOL(en_dev, SPM_SPEED_2X_100G, sup)) + { + ZXDH_EN_LINK_MODE_ADD(ks, 100000baseKR2_Full, sup); + ZXDH_EN_LINK_MODE_ADD(ks, 100000baseSR2_Full, sup); + ZXDH_EN_LINK_MODE_ADD(ks, 100000baseCR2_Full, sup); + ZXDH_EN_LINK_MODE_ADD(ks, 100000baseLR2_ER2_FR2_Full, sup); + } + + return; +} + +static void zxdh_en_ethtool_to_phytype(struct ethtool_link_ksettings *ks, uint32_t *speed_modes) +{ + if (ethtool_link_ksettings_test_link_mode(ks, advertising, 1000baseT_Full)) + { + *speed_modes |= BIT(SPM_SPEED_1X_1G); + } + + if (ethtool_link_ksettings_test_link_mode(ks, advertising, 10000baseT_Full)) + { + *speed_modes |= BIT(SPM_SPEED_1X_10G); + } + + if (ethtool_link_ksettings_test_link_mode(ks, advertising, 25000baseCR_Full)) + { + *speed_modes |= BIT(SPM_SPEED_1X_25G); + } + + if (ethtool_link_ksettings_test_link_mode(ks, advertising, 50000baseCR2_Full)) + { + *speed_modes |= BIT(SPM_SPEED_1X_50G); + } + + if (ethtool_link_ksettings_test_link_mode(ks, advertising, 40000baseKR4_Full)) + { + *speed_modes |= BIT(SPM_SPEED_4X_40G); + } + + if (ethtool_link_ksettings_test_link_mode(ks, advertising, 100000baseKR4_Full)) + { + *speed_modes |= BIT(SPM_SPEED_4X_100G); + } + + if (ethtool_link_ksettings_test_link_mode(ks, advertising, 100000baseKR2_Full)) + { + *speed_modes |= BIT(SPM_SPEED_2X_100G); + } + + return; +} + +static int32_t zxdh_en_speed_to_speed_modes(uint32_t speed, uint32_t *speed_modes, uint32_t sup_modes) +{ + switch (speed) + { + case SPEED_1000: + { + *speed_modes |= BIT(SPM_SPEED_1X_1G); + break; + } + case SPEED_10000: + { + *speed_modes |= BIT(SPM_SPEED_1X_10G); + break; + } + case SPEED_25000: + { + *speed_modes |= BIT(SPM_SPEED_1X_25G); + break; + } + case SPEED_40000: + { + *speed_modes |= BIT(SPM_SPEED_4X_40G); + break; + } + case SPEED_50000: + { + *speed_modes |= BIT(SPM_SPEED_1X_50G); + break; + } + case SPEED_100000: + { + *speed_modes |= BIT(SPM_SPEED_2X_100G); + *speed_modes |= BIT(SPM_SPEED_4X_100G); + break; + } + default: + { + return -EINVAL; + } + } + + *speed_modes &= sup_modes; + if (*speed_modes == 0) + { + return -EINVAL; + } + + return 0; +} + +static int32_t zxdh_en_get_link_ksettings(struct net_device *netdev, + struct ethtool_link_ksettings *ks) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + + ethtool_link_ksettings_zero_link_mode(ks, supported); + ethtool_link_ksettings_zero_link_mode(ks, advertising); + + ks->base.port = PORT_FIBRE; + ks->base.autoneg = en_dev->autoneg_enable; + ethtool_link_ksettings_add_link_mode(ks, supported, FIBRE); + ethtool_link_ksettings_add_link_mode(ks, supported, Autoneg); + + if (en_dev->autoneg_enable == AUTONEG_ENABLE) + { + ethtool_link_ksettings_add_link_mode(ks, advertising, Autoneg); + } + + ks->base.speed = en_dev->speed; + if ((!netif_running(netdev)) || (!netif_carrier_ok(netdev))) + { + ks->base.speed = SPEED_UNKNOWN; + } + ks->base.duplex = ks->base.speed == SPEED_UNKNOWN ? DUPLEX_UNKNOWN : DUPLEX_FULL; + + zxdh_en_phytype_to_ethtool(en_dev, ks, true); + zxdh_en_phytype_to_ethtool(en_dev, ks, false); + + if(en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) + { + zxdh_en_fec_link_ksettings_get(en_dev, ks); + zxdh_en_pause_link_ksettings_get(en_dev, ks); + } + + return 0; +} + +static int32_t zxdh_en_set_link_ksettings(struct net_device *netdev, + const struct ethtool_link_ksettings *ks) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + struct ethtool_link_ksettings safe_ks; + uint32_t advertising_link_modes = 0; + uint32_t off_speed_modes = 0; + uint32_t on_speed_modes = 0; + int32_t err = 0; + + if(en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_VF) + { + return 0; + } + if (ks->base.duplex == DUPLEX_HALF) + { + return -ENAVAIL; + } + + memset(&safe_ks, 0, sizeof(safe_ks)); + ethtool_link_ksettings_zero_link_mode(&safe_ks, supported); + ethtool_link_ksettings_zero_link_mode(&safe_ks, advertising); + + if (ks->base.autoneg == AUTONEG_DISABLE) + { + err = zxdh_en_speed_to_speed_modes(ks->base.speed, &off_speed_modes, + en_dev->supported_speed_modes); + LOG_DEBUG("set speed: %d, off_speed_modes: 0x%x\n", ks->base.speed, off_speed_modes); + if (err != 0) + { + LOG_ERR("zxdh_en_speed_to_speed_mode failed: %d\n", err); + return -EOPNOTSUPP; + } + + advertising_link_modes = off_speed_modes; + } + else + { + zxdh_en_phytype_to_ethtool(en_dev, &safe_ks, true); + if (!bitmap_intersects(ks->link_modes.advertising, + safe_ks.link_modes.supported, __ETHTOOL_LINK_MODE_MASK_NBITS)) + { + LOG_ERR("link_mode not supported\n"); + return -EOPNOTSUPP; + } + + bitmap_and(safe_ks.link_modes.advertising, ks->link_modes.advertising, + safe_ks.link_modes.supported, __ETHTOOL_LINK_MODE_MASK_NBITS); + zxdh_en_ethtool_to_phytype(&safe_ks, &on_speed_modes); + LOG_DEBUG("on_speed_modes: 0x%x\n", on_speed_modes); + advertising_link_modes = on_speed_modes; + } + + if ((advertising_link_modes == en_dev->advertising_speed_modes) && + (ks->base.autoneg == en_dev->autoneg_enable)) + { + LOG_DEBUG("nothing changed\n"); + return 0; + } + + safe_ks.base.speed = en_dev->speed; + en_dev->speed = SPEED_UNKNOWN; + LOG_INFO("autoneg %d, link_modes: 0x%x\n", ks->base.autoneg, advertising_link_modes); + err = zxdh_en_autoneg_set(en_dev, ks->base.autoneg, advertising_link_modes); + if (err != 0) + { + en_dev->speed = safe_ks.base.speed; + LOG_ERR("zxdh_en_autoneg_set failed: %d\n", err); + return err; + } + else + { + en_dev->autoneg_enable = ks->base.autoneg; + en_dev->advertising_speed_modes = advertising_link_modes; + en_dev->link_up = false; + netif_carrier_off(netdev); + en_dev->ops->set_pf_link_up(en_dev->parent, FALSE); //TODO:是否需要更新pf信息？ + queue_work(en_priv->events->wq, &en_priv->edev.vf_link_info_update_work); + queue_work(en_priv->events->wq, &en_priv->edev.link_info_irq_update_np_work); + } + + return err; +} + +static uint32_t zxdh_en_get_link(struct net_device *netdev) +{ + return netif_carrier_ok(netdev) ? 1 : 0; +} + +static int zxdh_en_get_eeprom_len(struct net_device *netdev) +{ + return 0; +} + +static int zxdh_en_get_eeprom(struct net_device *netdev, struct ethtool_eeprom *eeprom, u8 *bytes) +{ + return 0; +} + +static int zxdh_en_set_eeprom(struct net_device *netdev, struct ethtool_eeprom *eeprom, u8 *bytes) +{ + return 0; +} + +static void zxdh_en_get_ringparam(struct net_device *netdev, struct ethtool_ringparam *ring) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + + ring->rx_max_pending = ZXDH_PF_MAX_DESC_NUM; + ring->tx_max_pending = ZXDH_PF_MAX_DESC_NUM; + ring->rx_pending = en_dev->ops->get_queue_size(en_dev->parent, en_dev->phy_index[0]); + ring->tx_pending = en_dev->ops->get_queue_size(en_dev->parent, en_dev->phy_index[1]); + + return; +} + +static int zxdh_en_set_ringparam(struct net_device *netdev, struct ethtool_ringparam *ring) +{ + LOG_ERR("not supported\n"); + return -1; +} + +static void zxdh_en_get_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *pause) +{ + int32_t err; + uint32_t fc_mode; + struct zxdh_en_device *en_dev = netdev_priv(netdev); + + if(en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_VF) + { + return; + } + + err = zxdh_en_fc_mode_get(en_dev, &fc_mode); + if(err != 0) + { + LOG_ERR("zxdh_en_fc_mode_get failed!\n"); + return; + } + + pause->autoneg = 0; + + switch(fc_mode) + { + case BIT(SPM_FC_PAUSE_FULL): + { + pause->rx_pause = 1; + pause->tx_pause = 1; + break; + } + case BIT(SPM_FC_PAUSE_RX): + { + pause->rx_pause = 1; + pause->tx_pause = 0; + break; + } + case BIT(SPM_FC_PAUSE_TX): + { + pause->rx_pause = 0; + pause->tx_pause = 1; + break; + } + default: + { + pause->rx_pause = 0; + pause->tx_pause = 0; + break; + } + } + + return; +} + +static int32_t zxdh_en_set_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *pause) +{ + int32_t err; + uint32_t fc_mode_cur; + uint32_t fc_mode_cfg; + struct zxdh_en_device *en_dev = netdev_priv(netdev); + + if(en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_VF) + { + return -EOPNOTSUPP; + } + + if(pause->autoneg) + { + LOG_ERR("not support pause autoneg!\n"); + return -EOPNOTSUPP; + } + + err = zxdh_en_fc_mode_get(en_dev, &fc_mode_cur); + if(err != 0) + { + LOG_ERR("zxdh_en_fc_mode_get failed!\n"); + return err; + } + + if((pause->rx_pause || pause->tx_pause) && (fc_mode_cur == BIT(SPM_FC_PFC_FULL))) + { + LOG_ERR("warning, ethtool cfg pause on, this will lead to pfc off!\n"); + } + + if(pause->rx_pause && pause->tx_pause) + { + fc_mode_cfg = BIT(SPM_FC_PAUSE_FULL); + } + else if(pause->rx_pause) + { + fc_mode_cfg = BIT(SPM_FC_PAUSE_RX); + } + else if(pause->tx_pause) + { + fc_mode_cfg = BIT(SPM_FC_PAUSE_TX); + } + else + { + if(fc_mode_cur == BIT(SPM_FC_PFC_FULL)) + fc_mode_cfg = BIT(SPM_FC_PFC_FULL); + else + fc_mode_cfg = BIT(SPM_FC_NONE); + } + + if(fc_mode_cfg != fc_mode_cur) + { + err = zxdh_en_fc_mode_set(en_dev, fc_mode_cfg); + if(err != 0) + { + LOG_ERR("zxdh_en_fc_mode_set failed!\n"); + return err; + } + } + + return 0; +} + +static int32_t zxdh_en_get_fecparam(struct net_device *netdev, struct ethtool_fecparam *fecparam) +{ + int32_t err; + uint32_t fec_cfg; + uint32_t fec_active; + struct zxdh_en_device *en_dev = netdev_priv(netdev); + + if(en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_VF) + { + return -EOPNOTSUPP; + } + + err = zxdh_en_fec_mode_get(en_dev, NULL, &fec_cfg, &fec_active); + if(err != 0) + { + LOG_ERR("zxdh_en_fec_mode_get failed!\n"); + return err; + } + + fecparam->fec = zxdh_en_fec_to_ethtool_fecparam(fec_cfg, GET_FEC_CFG_FLAG); + fecparam->active_fec = zxdh_en_fec_to_ethtool_fecparam(fec_active, GET_FEC_LINK_FLAG); + + //LOG_INFO("fec_cfg=0x%x, fecparam->fec=0x%x, fec_active=0x%x, fecparam->active_fec=0x%x\n", + // fec_cfg, fecparam->fec, fec_active, fecparam->active_fec); + + return 0; +} + +static int32_t zxdh_en_set_fecparam(struct net_device *netdev, struct ethtool_fecparam *fecparam) +{ + int32_t i; + int32_t err; + uint32_t fec_cap; + uint32_t fec_cfg = 0; + uint32_t fecparam_cap; + struct zxdh_en_device *en_dev = netdev_priv(netdev); + + if(en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_VF) + { + return -EOPNOTSUPP; + } + + err = zxdh_en_fec_mode_get(en_dev, &fec_cap, NULL, NULL); + if(err != 0) + { + LOG_ERR("zxdh_en_fec_mode_get failed!\n"); + return err; + } + fecparam_cap = zxdh_en_fec_to_ethtool_fecparam(fec_cap, GET_FEC_CAP_FLAG); + + if((fecparam->fec | fecparam_cap) != fecparam_cap) + { + LOG_ERR("fecparam->fec 0x%x unsupport !\n", fecparam->fec); + return -EOPNOTSUPP; + } + + for(i = 0; i < ARRAY_SIZE(fec_2_ethtool_fecparam); i++) + { + if(fecparam->fec == fec_2_ethtool_fecparam[i]) + { + fec_cfg |= BIT(i); + } + } + + if(!fec_cfg && (fecparam->fec != ETHTOOL_FEC_AUTO)) + { + LOG_ERR("fecparam->fec 0x%x unsupport !\n", fecparam->fec); + return -EOPNOTSUPP; + } + + //LOG_INFO("fecparam_cap=0x%x, fec_cap=0x%x, fecparam->fec=0x%x, fec_cfg=0x%x\n", + // fecparam_cap, fec_cap, fecparam->fec, fec_cfg); + + err = zxdh_en_fec_mode_set(en_dev, fec_cfg); + if(err != 0) + { + LOG_ERR("zxdh_en_fec_mode_set failed!\n"); + return err; + } + + return 0; +} + +static int32_t zxdh_en_get_module_info(struct net_device *netdev, struct ethtool_modinfo *modinfo) +{ + uint32_t read_bytes; + uint8_t data[2] = {0}; + struct zxdh_en_module_eeprom_param query = {0}; + struct zxdh_en_device *en_dev = netdev_priv(netdev); + + if(en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_VF) + { + return -EOPNOTSUPP; + } + + query.i2c_addr = SFF_I2C_ADDRESS_LOW; + query.page = 0; + query.offset = 0; + query.length = 2; + read_bytes = zxdh_en_module_eeprom_read(en_dev, &query, data); + if(read_bytes != query.length) + { + LOG_ERR("zxdh_en_module_eeprom_read failed!\n"); + return -EIO; + } + + switch(data[0]) + { + case ZXDH_MODULE_ID_SFP: + modinfo->type = ETH_MODULE_SFF_8472; + modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; + break; + case ZXDH_MODULE_ID_QSFP: + modinfo->type = ETH_MODULE_SFF_8436; + modinfo->eeprom_len = ETH_MODULE_SFF_8436_MAX_LEN; + break; + case ZXDH_MODULE_ID_QSFP_PLUS: + case ZXDH_MODULE_ID_QSFP28: + if(data[1] < 3) + { + modinfo->type = ETH_MODULE_SFF_8436; + modinfo->eeprom_len = ETH_MODULE_SFF_8436_MAX_LEN; + } + else + { + modinfo->type = ETH_MODULE_SFF_8636; + modinfo->eeprom_len = ETH_MODULE_SFF_8636_MAX_LEN; + } + break; + default: + LOG_ERR("can not recognize module identifier 0x%x!\n", data[0]); + return -EINVAL; + } + + return 0; +} + +static int32_t zxdh_en_get_module_eeprom(struct net_device *netdev, struct ethtool_eeprom *ee, u8 *data) +{ + struct zxdh_en_module_eeprom_param query = {0}; + struct zxdh_en_device *en_dev = netdev_priv(netdev); + uint32_t offset = ee->offset; + uint32_t length = ee->len; + uint8_t identifier; + uint32_t offset_boundary = 0; + uint32_t total_read_bytes = 0; + uint32_t read_bytes = 0; + + if(en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_VF) + { + return -EOPNOTSUPP; + } + + //LOG_INFO("offset %u, len %u\n", ee->offset, ee->len); + + if(!ee->len) + return -EINVAL; + + memset(data, 0, ee->len); + + query.i2c_addr = SFF_I2C_ADDRESS_LOW; + query.bank = 0; + query.page = 0; + query.offset = 0; + query.length = 1; + read_bytes = zxdh_en_module_eeprom_read(en_dev, &query, &identifier); + if(read_bytes != query.length) + { + LOG_ERR("zxdh_en_module_eeprom_read failed!\n"); + return -EIO; + } + + while(total_read_bytes < ee->len) + { + if(identifier == ZXDH_MODULE_ID_SFP) + { + if(offset < 256) + { + query.i2c_addr = SFF_I2C_ADDRESS_LOW; + query.page = 0; + query.offset = offset; + } + else + { + query.i2c_addr = SFF_I2C_ADDRESS_HIGH; + query.page = 0; + query.offset = offset - 256; + } + offset_boundary = (query.offset < 128) ? 128 : 256; + query.length = ((query.offset + length) > offset_boundary) ? (offset_boundary - query.offset) : length; + } + else if(identifier == ZXDH_MODULE_ID_QSFP || + identifier == ZXDH_MODULE_ID_QSFP_PLUS || + identifier == ZXDH_MODULE_ID_QSFP28) + { + query.i2c_addr = SFF_I2C_ADDRESS_LOW; + if(offset < 256) + { + query.page = 0; + query.offset = offset; + } + else + { + query.page = (offset - 256) / 128 + 1; + query.offset = offset - 128 * query.page; + } + offset_boundary = (query.offset < 128) ? 128 : 256; + query.length = ((query.offset + length) > offset_boundary) ? (offset_boundary - query.offset) : length; + } + else + { + LOG_ERR("can not recognize module identifier 0x%x!\n", identifier); + return -EINVAL; + } + + read_bytes = zxdh_en_module_eeprom_read(en_dev, &query, data + total_read_bytes); + if(read_bytes != query.length) + { + LOG_ERR("zxdh_en_module_eeprom_read failed!\n"); + return -EIO; + } + + total_read_bytes += read_bytes; + offset += read_bytes; + length -= read_bytes; + } + + return 0; +} + +#ifdef HAVE_ETHTOOL_GET_MODULE_EEPROM_BY_PAGE +static int32_t zxdh_en_get_module_eeprom_by_page(struct net_device *netdev, + const struct ethtool_module_eeprom *page_data, + struct netlink_ext_ack *extack) +{ + struct zxdh_en_module_eeprom_param query = {0}; + struct zxdh_en_device *en_dev = netdev_priv(netdev); + uint32_t read_bytes = 0; + + if(en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_VF) + { + return -EOPNOTSUPP; + } + + //LOG_INFO("offset %u, length %u, page %u, bank %u, i2c_address %u\n", + // page_data->offset, page_data->length, page_data->page, page_data->bank, page_data->i2c_address); + + if(!page_data->length) + return -EINVAL; + + memset(page_data->data, 0, page_data->length); + + query.i2c_addr = page_data->i2c_address; + query.bank = page_data->bank; + query.page = page_data->page; + query.offset = page_data->offset; + query.length = page_data->length; + read_bytes = zxdh_en_module_eeprom_read(en_dev, &query, page_data->data); + if(read_bytes != query.length) + { + LOG_ERR("zxdh_en_module_eeprom_read failed!\n"); + return -EIO; + } + + return read_bytes; +} +#endif + +static void zxdh_en_diag_test(struct net_device *netdev, struct ethtool_test *eth_test, u64 *data) +{ + +} + +static int32_t zxdh_lldp_enable_proc(struct net_device *netdev, bool enable) +{ + int32_t ret = 0; + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + + ret = zxdh_lldp_enable_set(&en_priv->edev, enable); + if (0 != ret) + { + LOG_ERR("%s lldp failed!\n", enable ? "enable" : "disable"); + return ret; + } + + return ret; +} + +static int32_t zxdh_sshd_enable_proc(struct net_device *netdev, bool enable) +{ + int32_t ret = 0; + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + + ret = zxdh_sshd_enable_set(&en_priv->edev, enable); + if (0 != ret) + { + LOG_ERR("%s riscv sshd failed!\n", enable ? "enable" : "disable"); + return ret; + } + + return ret; +} + +typedef int32_t (*zxdh_pflag_handler)(struct net_device *netdev, bool enable); + +struct flag_desc +{ + uint8_t name[ETH_GSTRING_LEN]; + uint32_t bitno; + zxdh_pflag_handler handler; +}; + +#define ZXDH_PRIV_DESC(_name, _bitno, _handler) \ +{ \ + .name = _name, \ + .bitno = _bitno, \ + .handler = _handler, \ +} + +static const struct flag_desc zxdh_gstrings_priv_flags[] = +{ + ZXDH_PRIV_DESC("enable_lldp", ZXDH_PFLAG_ENABLE_LLDP, zxdh_lldp_enable_proc), + ZXDH_PRIV_DESC("enable_sshd", ZXDH_PFLAG_ENABLE_SSHD, zxdh_sshd_enable_proc), + ZXDH_PRIV_DESC("debug_ip", ZXDH_PFLAG_IP, NULL), +}; + +#define ZXDH_PRIV_FALG_ARRAY_SIZE ARRAY_SIZE(zxdh_gstrings_priv_flags) + +static void zxdh_en_get_strings(struct net_device *netdev, u32 stringset, u8 *data) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + uint16_t i = 0; + int8_t ip[20] = {0}; + uint8_t is_zios = 0; + int32_t ret = 0; + + switch (stringset) + { + case ETH_SS_STATS: + { + snprintf(data, ETH_GSTRING_LEN, "rx_packets");//get stat from netdev->stats + ZXDH_ADD_STRING(data, "tx_packets"); + ZXDH_ADD_STRING(data, "rx_bytes"); + ZXDH_ADD_STRING(data, "tx_bytes"); + ZXDH_ADD_STRING(data, "tx_queue_wake"); + ZXDH_ADD_STRING(data, "tx_queue_stopped"); + ZXDH_ADD_STRING(data, "tx_queue_dropped"); + + ZXDH_ADD_STRING(data, "rx_vport_packets");//get stat from np & vqm + ZXDH_ADD_STRING(data, "tx_vport_packets"); + ZXDH_ADD_STRING(data, "rx_vport_bytes"); + ZXDH_ADD_STRING(data, "tx_vport_bytes"); + ZXDH_ADD_STRING(data, "rx_vport_dropped"); + ZXDH_ADD_STRING(data, "rx_vport_broadcast_packets"); + ZXDH_ADD_STRING(data, "tx_vport_broadcast_packets"); + ZXDH_ADD_STRING(data, "rx_vport_mtu_drop_packets"); + ZXDH_ADD_STRING(data, "tx_vport_mtu_drop_packets"); + ZXDH_ADD_STRING(data, "rx_vport_mtu_drop_bytes"); + ZXDH_ADD_STRING(data, "tx_vport_mtu_drop_bytes"); + ZXDH_ADD_STRING(data, "rx_vport_plcr_drop_packets"); + ZXDH_ADD_STRING(data, "tx_vport_plcr_drop_packets"); + ZXDH_ADD_STRING(data, "rx_vport_plcr_drop_bytes"); + ZXDH_ADD_STRING(data, "tx_vport_plcr_drop_bytes"); + + ZXDH_ADD_STRING(data, "rx_packets_phy");//get stat from mac + ZXDH_ADD_STRING(data, "tx_packets_phy"); + ZXDH_ADD_STRING(data, "rx_bytes_phy"); + ZXDH_ADD_STRING(data, "tx_bytes_phy"); + ZXDH_ADD_STRING(data, "rx_errors_phy"); + ZXDH_ADD_STRING(data, "tx_errors_phy"); + ZXDH_ADD_STRING(data, "rx_drop_phy"); + ZXDH_ADD_STRING(data, "tx_drop_phy"); + ZXDH_ADD_STRING(data, "rx_multicast_phy"); + ZXDH_ADD_STRING(data, "tx_multicast_phy"); + ZXDH_ADD_STRING(data, "rx_broadcast_phy"); + ZXDH_ADD_STRING(data, "tx_broadcast_phy"); + ZXDH_ADD_STRING(data, "rx_size_64_phy"); + ZXDH_ADD_STRING(data, "rx_size_65_127"); + ZXDH_ADD_STRING(data, "rx_size_128_255"); + ZXDH_ADD_STRING(data, "rx_size_256_511"); + ZXDH_ADD_STRING(data, "rx_size_512_1023"); + ZXDH_ADD_STRING(data, "rx_size_1024_1518"); + ZXDH_ADD_STRING(data, "rx_size_1519_mru"); + ZXDH_ADD_STRING(data, "rx_pause"); + ZXDH_ADD_STRING(data, "tx_pause"); + + for (i = 0; i < en_dev->curr_queue_pairs; i++) + { + ZXDH_ADD_QUEUE_STRING(data, "rx_pkts", i); + ZXDH_ADD_QUEUE_STRING(data, "tx_pkts", i); + ZXDH_ADD_QUEUE_STRING(data, "rx_bytes", i); + ZXDH_ADD_QUEUE_STRING(data, "tx_bytes", i); + ZXDH_ADD_QUEUE_STRING(data, "tx_stopped", i); + ZXDH_ADD_QUEUE_STRING(data, "tx_wake", i); + ZXDH_ADD_QUEUE_STRING(data, "tx_dropped", i); + } + break; + } + case ETH_SS_PRIV_FLAGS: + { + for (i = 0; i < ZXDH_NUM_PFLAGS; i++) + { + strncpy(data + i * ETH_GSTRING_LEN, zxdh_gstrings_priv_flags[i].name, ETH_GSTRING_LEN); + } + + /* 获取riscv的os类型 */ + ret = zxdh_riscv_os_type_get(en_dev, &is_zios); + if (ret != 0) + { + LOG_ERR("zxdh_riscv_os_type_get failed"); + break; + } + + /* 修改登录方式 */ + if (is_zios == ZIOS_TYPE) + { + strncpy(data + ZXDH_PFLAG_ENABLE_SSHD * ETH_GSTRING_LEN, "enable_telnetd", ETH_GSTRING_LEN); + } + + /* 获取debug口的ip地址*/ + ret = zxdh_debug_ip_get(en_dev, ip); + if (ret != 0) + { + LOG_ERR("ip get failed"); + break; + } + strncpy(data + ZXDH_PFLAG_IP * ETH_GSTRING_LEN, ip, ETH_GSTRING_LEN); + break; + } + default: + { + LOG_ERR("invalid para\n"); + break; + } + } + + return; +} + +static int32_t zxdh_handle_pflag(struct net_device *netdev, + uint32_t wanted_flags, + enum zxdh_priv_flag flag) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + bool enable = !!(wanted_flags & BIT(flag)); + uint32_t changes = wanted_flags ^ en_priv->edev.pflags; + int32_t err = 0; + + /* 判断设置的值是否改变&改变的位是否为flag位 */ + if (!(changes & BIT(flag))) + { + return 0; + } + + if (flag == ZXDH_PFLAG_IP) + { + LOG_INFO("debug ip can not be changed"); + return 0; + } + + err = zxdh_gstrings_priv_flags[flag].handler(netdev, enable); + if (0 != err) + { + LOG_ERR("%s private flag '%s' failed err %d\n", \ + enable ? "Enable" : "Disable", zxdh_gstrings_priv_flags[flag].name, err); + return err; + } + + ZXDH_SET_PFLAG(en_priv->edev.pflags, flag, enable); + + if (flag == ZXDH_PFLAG_ENABLE_SSHD) /* 同步debug的ip状态*/ + { + ZXDH_SET_PFLAG(en_priv->edev.pflags, ZXDH_PFLAG_IP, enable); + } + return 0; +} + + +static int32_t zxdh_en_set_priv_flags(struct net_device *netdev, uint32_t pflags) +{ + enum zxdh_priv_flag pflag = 0; + int32_t err = 0; + + for (pflag = 0; pflag < ZXDH_NUM_PFLAGS; pflag++) + { + err = zxdh_handle_pflag(netdev, pflags, pflag); + if (0 != err) + { + break; + } + } + + return err; +} + +static uint32_t zxdh_en_get_priv_flags(struct net_device *netdev) +{ + int32_t ret = 0; + uint32_t flag_lldp = 0; + uint32_t lldp_mask = 0; + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + + ret = zxdh_lldp_enable_get(&en_priv->edev, &flag_lldp); + if ((ret != 0) && (flag_lldp != 0) && (flag_lldp != 1)) + { + LOG_ERR("zxdh_lldp_enable_get err, ret(%d), flag_lldp(%u).\n", ret, flag_lldp); + return en_priv->edev.pflags; + } + + flag_lldp = flag_lldp << ZXDH_PFLAG_ENABLE_LLDP; + + lldp_mask = 0xFFFFFFFF ^ BIT(ZXDH_PFLAG_ENABLE_LLDP); + en_priv->edev.pflags = (en_priv->edev.pflags & lldp_mask) | flag_lldp; + + return en_priv->edev.pflags; +} + +static int zxdh_en_get_regs_len(struct net_device *netdev) +{ +#define ZXDH_REGS_LEN (128 * 1024) + return ZXDH_REGS_LEN * sizeof(uint32_t); +} + +static void zxdh_en_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p) +{ + +} + +static void zxdh_en_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + + wol->supported = en_dev->wol_support; + if (wol->supported == 0) + { + return; + } + wol->wolopts = en_dev->wolopts; +} + +static int zxdh_en_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) +{ + return 0; +} + +static uint32_t zxdh_en_get_msglevel(struct net_device *netdev) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + + return en_dev->msglevel; +} + +static void zxdh_en_set_msglevel(struct net_device *netdev, uint32_t data) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + en_dev->msglevel = data; +} + +static int zxdh_en_nway_reset(struct net_device *netdev) +{ + return 0; +} + +#ifdef HAVE_ETHTOOL_SET_PHYS_ID +static int zxdh_en_set_phys_id(struct net_device *netdev, enum ethtool_phys_id_state state) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + union zxdh_msg msg = {0}; + + switch (state) + { + case ETHTOOL_ID_ACTIVE: + { + msg.payload.mac_set_msg.blink_enable = 1; + break; + } + case ETHTOOL_ID_INACTIVE: + { + msg.payload.mac_set_msg.blink_enable = 0; + break; + } + default: + return -EOPNOTSUPP; + } + msg.payload.hdr_to_agt.op_code = AGENT_MAC_LED_BLINK; + msg.payload.hdr_to_agt.phyport = en_dev->phy_port; + LOG_DEBUG("send phyport %d, blink_enable=%d\n", en_dev->phy_port, msg.payload.mac_set_msg.blink_enable); + + return zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &msg); +} +#else +static int zxdh_en_phys_id(struct net_device *netdev, u32 data) +{ + return 0; +} +#endif /* HAVE_ETHTOOL_SET_PHYS_ID */ + +int32_t zxdh_en_self_test_num(void) +{ + return 0; +} + +#ifdef HAVE_ETHTOOL_GET_SSET_COUNT +static int32_t zxdh_en_get_sset_count(struct net_device *netdev, int sset) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + + switch (sset) + { + case ETH_SS_STATS: + { + return ZXDH_NET_PF_STATS_NUM(en_dev); + } + case ETH_SS_PRIV_FLAGS: + { + return ZXDH_NUM_PFLAGS; + } + case ETH_SS_TEST: + { + return zxdh_en_self_test_num(); + } + default: + { + return -EOPNOTSUPP; + } + } + + return 0; +} +#endif + +static void zxdh_en_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *drvinfo) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + int32_t ret = 0; + uint8_t drv_name_len = 0; + uint8_t drv_version[MAX_DRV_VERSION_LEN] = {0}; + uint8_t drv_version_len = 0; + uint16_t vport = 0; + + ret = en_dev->ops->get_pf_drv_msg(en_dev->parent, drv_version, &drv_version_len); + if (drv_version_len > MAX_DRV_NAME_LEN) + { + LOG_ERR("drv_version_len(%hhu) greater than %u", drv_version_len, MAX_DRV_NAME_LEN); + drv_version_len = MAX_DRV_NAME_LEN; + } + + vport = en_dev->vport; + drv_name_len = sizeof(DRV_NAME(vport)); + if (drv_name_len > MAX_DRV_NAME_LEN) + { + LOG_ERR("drv_name_len(%hhu) greater than %u", drv_name_len, MAX_DRV_NAME_LEN); + drv_name_len = MAX_DRV_NAME_LEN; + } + + memcpy(drvinfo->driver, DRV_NAME(vport), drv_name_len); + memcpy(drvinfo->version, drv_version, drv_version_len); + + strlcpy(drvinfo->bus_info, dev_name(en_dev->parent->parent->device), sizeof(drvinfo->bus_info)); + + drvinfo->n_priv_flags = ZXDH_NUM_PFLAGS; + drvinfo->n_stats = ZXDH_NET_PF_STATS_NUM(en_dev); + drvinfo->eedump_len = zxdh_en_get_eeprom_len(netdev); + drvinfo->regdump_len = zxdh_en_get_regs_len(netdev); + drvinfo->testinfo_len = zxdh_en_self_test_num(); + + memcpy(drvinfo->fw_version, en_dev->fw_version, en_dev->fw_version_len); +} + +int32_t zxdh_stats_update(struct zxdh_en_device *en_dev) +{ + uint16_t i = 0; + int32_t ret = 0; + + ret = zxdh_vport_stats_get(en_dev); + if (ret != 0) + { + LOG_ERR("zxdh_mac_stats_get failed, ret: %d\n", ret); + return -1; + } + + ret = zxdh_mac_stats_get(en_dev); + if (ret != 0) + { + LOG_ERR("zxdh_mac_stats_get failed, ret: %d\n", ret); + return -1; + } + + memset(&en_dev->hw_stats.netdev_stats, 0, sizeof(en_dev->hw_stats.netdev_stats)); + for (i = 0; i < en_dev->curr_queue_pairs; i++) + { + /* queue software statistics */ + en_dev->hw_stats.q_stats[i].q_rx_pkts = en_dev->rq[i].stats.packets; + en_dev->hw_stats.q_stats[i].q_tx_pkts = en_dev->sq[i].stats.packets; + en_dev->hw_stats.q_stats[i].q_rx_bytes = en_dev->rq[i].stats.bytes; + en_dev->hw_stats.q_stats[i].q_tx_bytes = en_dev->sq[i].stats.bytes; + + en_dev->hw_stats.netdev_stats.rx_packets += en_dev->rq[i].stats.packets; + en_dev->hw_stats.netdev_stats.tx_packets += en_dev->sq[i].stats.packets; + en_dev->hw_stats.netdev_stats.rx_bytes += en_dev->rq[i].stats.bytes; + en_dev->hw_stats.netdev_stats.tx_bytes += en_dev->sq[i].stats.bytes; + en_dev->hw_stats.netdev_stats.tx_queue_wake += en_dev->hw_stats.q_stats[i].q_tx_wake; + en_dev->hw_stats.netdev_stats.tx_queue_stopped += en_dev->hw_stats.q_stats[i].q_tx_stopped; + en_dev->hw_stats.netdev_stats.tx_queue_dropped += en_dev->hw_stats.q_stats[i].q_tx_dropped; + } + + return ret; +} + +static void zxdh_en_get_ethtool_stats(struct net_device *netdev, struct ethtool_stats *stats, u64 *data) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + uint32_t offset = ZXDH_NETDEV_STATS_NUM + ZXDH_MAC_STATS_NUM + ZXDH_VPORT_STATS_NUM; + + zxdh_stats_update(en_dev); + memcpy(data, &en_dev->hw_stats, ZXDH_NET_PF_STATS_NUM(en_dev) * sizeof(uint64_t)); + memcpy(data + offset, en_dev->hw_stats.q_stats, (en_dev->curr_queue_pairs * ZXDH_QUEUE_STATS_NUM) * sizeof(uint64_t)); + + return; +} + +static int zxdh_en_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ec) +{ + return 0; +} + +static int zxdh_en_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ec) +{ + return 0; +} + +static int zxdh_en_get_ts_info(struct net_device *netdev, struct ethtool_ts_info *info) +{ + return 0; +} + +#ifdef CONFIG_PM_RUNTIME +static int zxdh_en_ethtool_begin(struct net_device *netdev) +{ + return 0; +} + +static void zxdh_en_ethtool_complete(struct net_device *netdev) +{ + +} +#endif + +#ifndef HAVE_NDO_SET_FEATURES +static int zxdh_en_get_rx_csum(struct net_device *netdev) +{ + return 0; +} + +static int zxdh_en_set_rx_csum(struct net_device *netdev, u32 data) +{ + return 0; +} + +static int zxdh_en_set_tx_csum(struct net_device *netdev, u32 data) +{ + return 0; +} + +#ifdef NETIF_F_TSO +static int zxdh_en_set_tso(struct net_device *netdev, u32 data) +{ + return 0; +} +#endif /* NETIF_F_TSO */ + +#ifdef ETHTOOL_GFLAGS +static int zxdh_en_set_flags(struct net_device *netdev, u32 data) +{ + return 0; +} +#endif /* ETHTOOL_GFLAGS */ +#endif /* HAVE_NDO_SET_FEATURES */ + +static int zxdh_en_get_eee(struct net_device *netdev, struct ethtool_eee *edata) +{ + return 0; +} + +static int zxdh_en_set_eee(struct net_device *netdev, struct ethtool_eee *edata) +{ + return 0; +} +#ifdef ETHTOOL_GRXFHINDIR +#ifdef HAVE_ETHTOOL_GRXFHINDIR_SIZE +static u32 zxdh_en_get_rxfh_indir_size(struct net_device *netdev) +{ + return ZXDH_INDIR_RQT_SIZE; +} + +static u32 zxdh_en_get_rxfh_key_size(struct net_device *netdev) +{ + return ZXDH_NET_HASH_KEY_SIZE; +} + +#if (defined(ETHTOOL_GRSSH) && !defined(HAVE_ETHTOOL_GSRSSH)) +#ifdef HAVE_RXFH_HASHFUNC +static int zxdh_en_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key, u8 *hfunc) +#else +static int zxdh_en_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key) +#endif /* HAVE_RXFH_HASHFUNC */ +#else +static int zxdh_en_get_rxfh_indir(struct net_device *netdev, u32 *indir) +#endif /* HAVE_ETHTOOL_GSRSSH */ +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + union zxdh_msg msg = {0}; + int32_t ret = 0; + uint8_t func = 0; + DPP_PF_INFO_T pf_info = {0}; + + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + + LOG_INFO("zxdh_en_get_rxfh start\n"); + if (indir != NULL) + { + memcpy(indir, en_dev->indir_rqt, sizeof(uint32_t) * ZXDH_INDIR_RQT_SIZE); + } + + if (key != NULL) + { + LOG_INFO("get key is called\n"); + if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) + { + ret = dpp_thash_key_get(&pf_info, key, ZXDH_NET_HASH_KEY_SIZE); + } + else + { + msg.payload.hdr.op_code = ZXDH_THASH_KEY_GET; + msg.payload.hdr.vport = en_dev->vport; + msg.payload.hdr.pcie_id = en_dev->pcie_id; + ret = en_dev->ops->msg_send_cmd(en_dev->parent, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg, true); + if (ret == 0) + { + memcpy(key, msg.reps.thash_key_set_msg.key_map, ZXDH_NET_HASH_KEY_SIZE); + } + } + } + + if (hfunc != NULL) + { + func = en_dev->hash_func; + switch (func) + { + case ZXDH_FUNC_TOP: + { + *hfunc = ETH_RSS_HASH_TOP; + break; + } + case ZXDH_FUNC_XOR: + { + *hfunc = ETH_RSS_HASH_XOR; + break; + } + case ZXDH_FUNC_CRC32: + { + *hfunc = ETH_RSS_HASH_CRC32; + break; + } + default: + { + return -EOPNOTSUPP; + } + } + } + + return ret; +} +#else +static int zxdh_en_get_rxfh_indir(struct net_device *netdev, struct ethtool_rxfh_indir *indir) +{ + return 0; +} +#endif /* HAVE_ETHTOOL_GRXFHINDIR_SIZE */ +#endif /* ETHTOOL_GRXFHINDIR */ + +static int32_t zxdh_indir_to_queue_map(struct zxdh_en_device *en_dev, const uint32_t *indir) +{ + uint32_t *queue_map = NULL; + int32_t err = 0; + uint16_t i = 0; + uint16_t j = 0; + + queue_map = kzalloc(ZXDH_INDIR_RQT_SIZE * sizeof(uint32_t), GFP_KERNEL); + if (queue_map == NULL) + { + LOG_ERR("queue_map is NULL\n"); + return -ENOMEM; + } + for (i = 0; i < ZXDH_INDIR_RQT_SIZE; i++) + { + j = indir[i]; + queue_map[i] = en_dev->phy_index[2 * j]; + } + err = zxdh_rxfh_set(en_dev, queue_map); + kfree(queue_map); + if (err != 0) + { + LOG_ERR("zxdh_rxfh_set failed: %d\n", err); + return err; + } + + memcpy(en_dev->indir_rqt, indir, ZXDH_INDIR_RQT_SIZE * sizeof(uint32_t)); + + return err; +} + +#ifdef HAVE_ETHTOOL_GRXFHINDIR_SIZE +#if (defined(ETHTOOL_GRSSH) && !defined(HAVE_ETHTOOL_GSRSSH)) +#ifdef HAVE_RXFH_HASHFUNC +static int zxdh_en_set_rxfh(struct net_device *netdev, const u32 *indir, const u8 *key, const u8 hfunc) +#else +static int zxdh_en_set_rxfh(struct net_device *netdev, const u32 *indir, const u8 *key) +#endif /* HAVE_RXFH_HASHFUNC */ +#else +static int zxdh_en_set_rxfh_indir(struct net_device *netdev, const u32 *indir) +#endif /* HAVE_ETHTOOL_GSRSSH */ +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + union zxdh_msg msg = {0}; + int32_t ret = 0; + uint8_t func = 0; + DPP_PF_INFO_T pf_info = {0}; + + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + + LOG_INFO("zxdh_en_set_rxfh_indir start\n"); + switch (hfunc) + { + case ETH_RSS_HASH_NO_CHANGE: + { + break; + } + case ETH_RSS_HASH_TOP: + { + func = ZXDH_FUNC_TOP; + break; + } + case ETH_RSS_HASH_XOR: + { + func = ZXDH_FUNC_XOR; + break; + } + case ETH_RSS_HASH_CRC32: + { + func = ZXDH_FUNC_CRC32; + break; + } + default: + { + return -EOPNOTSUPP; + } + } + + if ((hfunc != ETH_RSS_HASH_NO_CHANGE) && (func != en_dev->hash_func)) + { + LOG_DEBUG("func: %u\n", func); + if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) + { + ret = dpp_vport_hash_funcs_set(&pf_info, func); + } + else + { + msg.payload.hdr.op_code = ZXDH_HASH_FUNC_SET; + msg.payload.hdr.vport = en_dev->vport; + msg.payload.hdr.pcie_id = en_dev->pcie_id; + msg.payload.hfunc_set_msg.func = func; + ret = en_dev->ops->msg_send_cmd(en_dev->parent, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg, true); + } + if (ret != 0) + { + LOG_ERR("hunc set failed: %d", ret); + return ret; + } + en_dev->hash_func = func; + } + + if (indir != NULL) + { + LOG_DEBUG("set indir is called\n"); + ret = zxdh_indir_to_queue_map(en_dev, indir); + if (ret != 0) + { + LOG_ERR("indir set failed: %d", ret); + return ret; + } + } + + if (key != NULL) + { + LOG_DEBUG("set thash key is called\n"); + if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) + { + ret = dpp_thash_key_set(&pf_info, (uint8_t *)key, ZXDH_NET_HASH_KEY_SIZE); + } + else + { + memset(&msg, 0, sizeof(union zxdh_msg)); + msg.payload.hdr.op_code = ZXDH_THASH_KEY_SET; + msg.payload.hdr.vport = en_dev->vport; + msg.payload.hdr.pcie_id = en_dev->pcie_id; + memcpy(msg.payload.thash_key_set_msg.key_map, key, ZXDH_NET_HASH_KEY_SIZE); + ret = en_dev->ops->msg_send_cmd(en_dev->parent, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg, true); + } + } + + return ret; +} +#else +static int zxdh_en_set_rxfh_indir(struct net_device *netdev, struct ethtool_cmd *ecmd) +{ + return 0; +} +#endif +#ifdef ETHTOOL_GCHANNELS +static void zxdh_en_get_channels(struct net_device *netdev, struct ethtool_channels *ch) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + union zxdh_msg msg = {0}; + int32_t err = 0; + DPP_PF_INFO_T pf_info = {0}; + + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + + ch->max_combined = max_pairs; + ch->combined_count = en_dev->curr_queue_pairs; + + if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) + { + err = dpp_rxfh_get(&pf_info, msg.payload.rxfh_set_msg.queue_map, ZXDH_INDIR_RQT_SIZE); + if (err != 0) + { + LOG_ERR("dpp_rxfh_get failed: %d\n", err); + return; + } + + LOG_DEBUG("*******pf_queue_map*******\n"); + zxdh_u32_array_print(msg.payload.rxfh_set_msg.queue_map, ZXDH_INDIR_RQT_SIZE); + } + else + { + msg.payload.hdr.op_code = ZXDH_RXFH_GET; + msg.payload.hdr.vport = en_dev->vport; + msg.payload.hdr.pcie_id = en_dev->pcie_id; + err = en_dev->ops->msg_send_cmd(en_dev->parent, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg, true); + if (err != 0) + { + LOG_ERR("dpp_rxfh_get failed: %d\n", err); + return; + } + + LOG_DEBUG("*******vf_queue_map*******\n"); + zxdh_u32_array_print(msg.reps.rxfh_get_msg.queue_map, ZXDH_INDIR_RQT_SIZE); + } +} +#endif /* ETHTOOL_GCHANNELS */ + +int32_t zxdh_num_channels_changed(struct zxdh_en_device *en_dev, uint16_t num_changed) +{ + uint32_t indir[ZXDH_INDIR_RQT_SIZE] = {0}; + int32_t err = 0; + uint16_t i = 0; + + if (!netif_is_rxfh_configured(en_dev->netdev)) + { + LOG_INFO("indir_is_default\n"); + for (i = 0; i < ZXDH_INDIR_RQT_SIZE; ++i) + { + indir[i] = i % num_changed; + } + + err = zxdh_indir_to_queue_map(en_dev, indir); + if (err != 0) + { + LOG_ERR("zxdh_indir_to_queue_map failed: %d\n", err); + return err; + } + } + + en_dev->curr_queue_pairs = num_changed; + + return err; +} + +#ifdef ETHTOOL_SCHANNELS +static int zxdh_en_set_channels(struct net_device *netdev, struct ethtool_channels *ch) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + int32_t ret = 0; + + LOG_INFO("zxdh_en_set_channels start\n"); + /* verify that the number of channels does not invalidate any current + * flow director rules + */ + //TODO + + /* We don't support separate rx/tx channels. + * We don't allow setting 'other' channels. + */ + if (ch->rx_count || ch->tx_count || ch->other_count) + { + LOG_ERR("not supported\n"); + return -EINVAL; + } + + if ((ch->combined_count > max_pairs) || (ch->combined_count == 0)) + { + LOG_ERR("invalid para\n"); + return -EINVAL; + } + + if (ch->combined_count == en_dev->curr_queue_pairs) + { + return 0; + } + + ret = zxdh_num_channels_changed(en_dev, ch->combined_count); + if (ret != 0) + { + LOG_ERR("zxdh_num_channels_changed failed: %d\n", ret); + return -1; + } + + netif_set_real_num_tx_queues(netdev, en_dev->curr_queue_pairs); + netif_set_real_num_rx_queues(netdev, en_dev->curr_queue_pairs); + + return 0; +} +#endif + +static int zxdh_en_get_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd, +#ifdef HAVE_ETHTOOL_GET_RXNFC_VOID_RULE_LOCS + void *rule_locs) +#else + u32 *rule_locs) +#endif +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + union zxdh_msg msg = {0}; + uint32_t hash_mode = 0; + int32_t ret = 0; + DPP_PF_INFO_T pf_info = {0}; + + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + + LOG_INFO("zxdh_en_get_rxnfc start\n"); + if (cmd->cmd == ETHTOOL_GRXRINGS) + { + cmd->data = en_dev->curr_queue_pairs; + return 0; + } + + if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) + { + ret = dpp_rx_flow_hash_get(&pf_info, &hash_mode); + } + else + { + msg.payload.hdr.op_code = ZXDH_RX_FLOW_HASH_GET; + msg.payload.hdr.vport = en_dev->vport; + msg.payload.hdr.pcie_id = en_dev->pcie_id; + ret = en_dev->ops->msg_send_cmd(en_dev->parent, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg, true); + hash_mode = msg.reps.rx_flow_hash_set_msg.hash_mode; + } + if (ret != 0) + { + return ret; + } + + LOG_DEBUG("hash_mode: %u\n", hash_mode); + switch (hash_mode) + { + case ZXDH_NET_RX_FLOW_HASH_MV: + { + cmd->data = RXH_L2DA + RXH_VLAN; + break; + } + case ZXDH_NET_RX_FLOW_HASH_SDT: + { + cmd->data = RXH_L3_PROTO + RXH_IP_SRC + RXH_IP_DST; + break; + } + case ZXDH_NET_RX_FLOW_HASH_SDFNT: + { + cmd->data = RXH_L3_PROTO + RXH_IP_SRC + RXH_IP_DST + RXH_L4_B_0_1 + RXH_L4_B_2_3; + break; + } + default: + { + LOG_ERR("invalid hash_mode\n"); + return -1; + } + } + + return 0; +} + +static int zxdh_en_set_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + union zxdh_msg msg = {0}; + uint32_t hash_mode = 0; + int32_t ret = 0; + DPP_PF_INFO_T pf_info = {0}; + + pf_info.slot = en_dev->slot_id; + pf_info.vport = en_dev->vport; + + LOG_INFO("zxdh_en_set_rxnfc start\n"); + switch (cmd->data) + { + /* input parameter mv */ + case (RXH_L2DA + RXH_VLAN): + { + hash_mode = ZXDH_NET_RX_FLOW_HASH_MV; + break; + } + /* input parameter sdt */ + case (RXH_L3_PROTO + RXH_IP_SRC + RXH_IP_DST): + { + hash_mode = ZXDH_NET_RX_FLOW_HASH_SDT; + break; + } + /* input parameter sdfnt */ + case (RXH_L3_PROTO + RXH_IP_SRC + RXH_IP_DST + RXH_L4_B_0_1 + RXH_L4_B_2_3): + { + hash_mode = ZXDH_NET_RX_FLOW_HASH_SDFNT; + break; + } + default: + { + LOG_ERR("invalid para, support mv, sdt, sdfnt\n"); + return -EOPNOTSUPP; + } + } + + LOG_DEBUG("hash_mode: %u\n", hash_mode); + if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) + { + ret = dpp_rx_flow_hash_set(&pf_info, hash_mode); + } + else + { + msg.payload.hdr.op_code = ZXDH_RX_FLOW_HASH_SET; + msg.payload.hdr.vport = en_dev->vport; + msg.payload.hdr.pcie_id = en_dev->pcie_id; + msg.payload.rx_flow_hash_set_msg.hash_mode = hash_mode; + ret = en_dev->ops->msg_send_cmd(en_dev->parent, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg, true); + } + + return ret; +} + +static const struct ethtool_ops zxdh_en_ethtool_ops = +{ +#ifdef HAVE_ETHTOOL_COALESCE_PARAMS_SUPPORT + .supported_coalesce_params = ETHTOOL_COALESCE_MAX_FRAMES, //ETHTOOL_COALESCE_USECS, +#endif + .get_drvinfo = zxdh_en_get_drvinfo, + .get_link_ksettings = zxdh_en_get_link_ksettings, + .set_link_ksettings = zxdh_en_set_link_ksettings, + .get_regs_len = zxdh_en_get_regs_len, + .get_regs = zxdh_en_get_regs, + .get_wol = zxdh_en_get_wol, + .set_wol = zxdh_en_set_wol, + .get_msglevel = zxdh_en_get_msglevel, + .set_msglevel = zxdh_en_set_msglevel, + .nway_reset = zxdh_en_nway_reset, + .get_link = zxdh_en_get_link, + .get_eeprom_len = zxdh_en_get_eeprom_len, + .get_eeprom = zxdh_en_get_eeprom, + .set_eeprom = zxdh_en_set_eeprom, + .get_ringparam = zxdh_en_get_ringparam, + .set_ringparam = zxdh_en_set_ringparam, + .get_pauseparam = zxdh_en_get_pauseparam, + .set_pauseparam = zxdh_en_set_pauseparam, + .get_fecparam = zxdh_en_get_fecparam, + .set_fecparam = zxdh_en_set_fecparam, + .get_module_info = zxdh_en_get_module_info, + .get_module_eeprom = zxdh_en_get_module_eeprom, +#ifdef HAVE_ETHTOOL_GET_MODULE_EEPROM_BY_PAGE + .get_module_eeprom_by_page = zxdh_en_get_module_eeprom_by_page, +#endif + .self_test = zxdh_en_diag_test, + .get_strings = zxdh_en_get_strings, + .get_priv_flags = zxdh_en_get_priv_flags, + .set_priv_flags = zxdh_en_set_priv_flags, +#ifndef HAVE_RHEL6_ETHTOOL_OPS_EXT_STRUCT +#ifdef HAVE_ETHTOOL_SET_PHYS_ID + .set_phys_id = zxdh_en_set_phys_id, +#else + .phys_id = zxdh_en_phys_id, +#endif /* HAVE_ETHTOOL_SET_PHYS_ID */ +#endif /* HAVE_RHEL6_ETHTOOL_OPS_EXT_STRUCT */ + +#ifdef HAVE_ETHTOOL_GET_SSET_COUNT + .get_sset_count = zxdh_en_get_sset_count, +#else + .get_stats_count = zxdh_en_get_stats_count, + .self_test_count = zxdh_en_diag_test_count, +#endif + .get_ethtool_stats = zxdh_en_get_ethtool_stats, + +#ifdef HAVE_ETHTOOL_GET_PERM_ADDR + .get_perm_addr = ethtool_op_get_perm_addr, +#endif + .get_coalesce = zxdh_en_get_coalesce, + .set_coalesce = zxdh_en_set_coalesce, +#ifndef HAVE_RHEL6_ETHTOOL_OPS_EXT_STRUCT +#ifdef HAVE_ETHTOOL_GET_TS_INFO + .get_ts_info = zxdh_en_get_ts_info, +#endif /* HAVE_ETHTOOL_GET_TS_INFO */ +#endif /* HAVE_RHEL6_ETHTOOL_OPS_EXT_STRUCT */ +#ifdef CONFIG_PM_RUNTIME + .begin = zxdh_en_ethtool_begin, + .complete = zxdh_en_ethtool_complete, +#endif /* CONFIG_PM_RUNTIME */ +#ifndef HAVE_NDO_SET_FEATURES + .get_rx_csum = zxdh_en_get_rx_csum, + .set_rx_csum = zxdh_en_set_rx_csum, + .get_tx_csum = ethtool_op_get_tx_csum, + .set_tx_csum = zxdh_en_set_tx_csum, + .get_sg = ethtool_op_get_sg, + .set_sg = ethtool_op_set_sg, +#ifdef NETIF_F_TSO + .get_tso = ethtool_op_get_tso, + .set_tso = zxdh_en_set_tso, +#endif +#ifdef ETHTOOL_GFLAGS + .get_flags = ethtool_op_get_flags, + .set_flags = zxdh_en_set_flags, +#endif /* ETHTOOL_GFLAGS */ +#endif /* HAVE_NDO_SET_FEATURES */ +#ifdef ETHTOOL_GADV_COAL + .get_advcoal = zxdh_en_get_adv_coal, + .set_advcoal = zxdh_en_set_dmac_coal, +#endif /* ETHTOOL_GADV_COAL */ +#ifndef HAVE_RHEL6_ETHTOOL_OPS_EXT_STRUCT +#ifdef ETHTOOL_GEEE + .get_eee = zxdh_en_get_eee, +#endif +#ifdef ETHTOOL_SEEE + .set_eee = zxdh_en_set_eee, +#endif +#ifdef ETHTOOL_GRXFHINDIR +#ifdef HAVE_ETHTOOL_GRXFHINDIR_SIZE + .get_rxfh_indir_size = zxdh_en_get_rxfh_indir_size, + .get_rxfh_key_size = zxdh_en_get_rxfh_key_size, +#endif /* HAVE_ETHTOOL_GRSFHINDIR_SIZE */ +#if (defined(ETHTOOL_GRSSH) && !defined(HAVE_ETHTOOL_GSRSSH)) + .get_rxfh = zxdh_en_get_rxfh, +#else + .get_rxfh_indir = zxdh_en_get_rxfh_indir, +#endif /* HAVE_ETHTOOL_GSRSSH */ +#endif /* ETHTOOL_GRXFHINDIR */ +#ifdef ETHTOOL_SRXFHINDIR +#if (defined(ETHTOOL_GRSSH) && !defined(HAVE_ETHTOOL_GSRSSH)) + .set_rxfh = zxdh_en_set_rxfh, +#else + .set_rxfh_indir = zxdh_en_set_rxfh_indir, +#endif /* HAVE_ETHTOOL_GSRSSH */ +#endif /* ETHTOOL_SRXFHINDIR */ +#ifdef ETHTOOL_GCHANNELS + .get_channels = zxdh_en_get_channels, +#endif /* ETHTOOL_GCHANNELS */ +#ifdef ETHTOOL_SCHANNELS + .set_channels = zxdh_en_set_channels, +#endif /* ETHTOOL_SCHANNELS */ +#endif /* HAVE_RHEL6_ETHTOOL_OPS_EXT_STRUCT */ +#ifdef ETHTOOL_GRXFH + .get_rxnfc = zxdh_en_get_rxnfc, + .set_rxnfc = zxdh_en_set_rxnfc, +#endif +}; + +#ifdef HAVE_RHEL6_ETHTOOL_OPS_EXT_STRUCT +static const struct ethtool_ops_ext zxdh_en_ethtool_ops_ext = +{ + .size = sizeof(struct ethtool_ops_ext), + .get_ts_info = zxdh_en_get_ts_info, + .set_phys_id = zxdh_en_set_phys_id, + .get_eee = zxdh_en_get_eee, + .set_eee = zxdh_en_set_eee, +#ifdef HAVE_ETHTOOL_GRXFHINDIR_SIZE + .get_rxfh_indir_size = zxdh_en_get_rxfh_indir_size, +#endif /* HAVE_ETHTOOL_GRSFHINDIR_SIZE */ + .get_rxfh_indir = zxdh_en_get_rxfh_indir, + .set_rxfh_indir = zxdh_en_set_rxfh_indir, + .get_channels = zxdh_en_get_channels, + .set_channels = zxdh_en_set_channels, +}; + +void zxdh_en_set_ethtool_ops_ext(struct net_device *netdev) +{ + netdev->ethtool_ops = &zxdh_en_ethtool_ops; + set_ethtool_ops_ext(netdev, &zxdh_en_ethtool_ops_ext); +} +#else +void zxdh_en_set_ethtool_ops(struct net_device *netdev) +{ + netdev->ethtool_ops = &zxdh_en_ethtool_ops; +} +#endif /* HAVE_RHEL6_ETHTOOL_OPS_EXT_STRUCT */ + diff --git a/src/net/drivers/net/ethernet/dinghai/en_ethtool/ethtool.h b/src/net/drivers/net/ethernet/dinghai/en_ethtool/ethtool.h new file mode 100644 index 0000000..fb8fb3d --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_ethtool/ethtool.h @@ -0,0 +1,68 @@ +#ifndef __ZXDH_EN_ETHTOOL_H__ +#define __ZXDH_EN_ETHTOOL_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +enum zxdh_priv_flag +{ + ZXDH_PFLAG_ENABLE_LLDP, + ZXDH_PFLAG_ENABLE_SSHD, + ZXDH_PFLAG_IP=2, + ZXDH_NUM_PFLAGS, /* Keep last */ +}; + +#define ZXDH_SET_PFLAG(pflags, flag, enable) \ + do \ + { \ + if (enable) \ + { \ + pflags |= BIT(flag); \ + } \ + else \ + { \ + pflags &= ~(BIT(flag)); \ + } \ + } while (0) + +#define ZXDH_ADD_STRING(data, str) \ +do \ +{ \ + data += ETH_GSTRING_LEN; \ + snprintf(data, ETH_GSTRING_LEN, str); \ +} while (0) + +#define ZXDH_ADD_QUEUE_STRING(data, str, i) \ +do \ +{ \ + data += ETH_GSTRING_LEN; \ + snprintf(data, ETH_GSTRING_LEN, "queue[%u]_%s", i, str); \ +} while (0) + +#define ZXDH_NETDEV_STATS_NUM (sizeof(struct zxdh_en_netdev_stats) / sizeof(uint64_t)) +#define ZXDH_VPORT_STATS_NUM (sizeof(struct zxdh_en_vport_stats) / sizeof(uint64_t)) +#define ZXDH_MAC_STATS_NUM (sizeof(struct zxdh_en_phy_stats) / sizeof(uint64_t)) +#define ZXDH_QUEUE_STATS_NUM (sizeof(struct zxdh_en_queue_stats) / sizeof(uint64_t)) + +#define ZXDH_NET_PF_STATS_NUM(en_dev) \ + (ZXDH_NETDEV_STATS_NUM + ZXDH_MAC_STATS_NUM + ZXDH_VPORT_STATS_NUM + \ + en_dev->curr_queue_pairs * ZXDH_QUEUE_STATS_NUM) + +#define ZXDH_GET_PFLAG(pflags, flag) (!!(pflags & (BIT(flag)))) + +#ifdef HAVE_RHEL6_ETHTOOL_OPS_EXT_STRUCT +void zxdh_en_set_ethtool_ops_ext(struct net_device *netdev); +#else +void zxdh_en_set_ethtool_ops(struct net_device *netdev); +#endif /* HAVE_RHEL6_ETHTOOL_OPS_EXT_STRUCT */ + +#define ZIOS_TYPE 0XAA +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_mpf.c b/src/net/drivers/net/ethernet/dinghai/en_mpf.c new file mode 100755 index 0000000..1b65f40 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_mpf.c @@ -0,0 +1,301 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "./en_mpf/events.h" +#include "./en_mpf/eq.h" +#include "./en_mpf/irq.h" +#include "en_mpf.h" +#include "en_mpf/cfg_sf.h" + +MODULE_LICENSE("Dual BSD/GPL"); + +uint32_t dh_debug_mask; +module_param_named(debug_mask, dh_debug_mask, uint, 0644); +MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0"); + +extern struct devlink_ops dh_mpf_devlink_ops; +extern struct dh_core_devlink_ops dh_mpf_core_devlink_ops; + +int32_t dh_mpf_pci_init(struct dh_core_dev *dev) +{ + int32_t ret = 0; + struct dh_en_mpf_dev *mpf_dev = NULL; + + pci_set_drvdata(dev->pdev, dev); + + ret = pci_enable_device(dev->pdev); + if (ret != 0) + { + dev_err(dev->device, "pci_enable_device failed: %d\n", ret); + return -ENOMEM; + } + + ret = dma_set_mask_and_coherent(dev->device, DMA_BIT_MASK(64)); + if (ret != 0) + { + ret = dma_set_mask_and_coherent(dev->device, DMA_BIT_MASK(32)); + if (ret != 0) + { + dev_err(dev->device, "dma_set_mask_and_coherent failed: %d\n", ret); + goto err_pci; + } + } + + ret = pci_request_selected_regions(dev->pdev, pci_select_bars(dev->pdev, IORESOURCE_MEM), "dh-mpf"); + if (ret != 0) + { + dev_err(dev->device, "pci_request_selected_regions failed: %d\n", ret); + goto err_pci; + } + + pci_enable_pcie_error_reporting(dev->pdev); + pci_set_master(dev->pdev); + ret = pci_save_state(dev->pdev); + if (ret != 0) + { + dev_err(dev->device, "pci_save_state failed: %d\n", ret); + goto err_pci_save_state; + } + + mpf_dev = dh_core_priv(dev); + mpf_dev->pci_ioremap_addr = (uint64_t)ioremap(pci_resource_start(dev->pdev, 0), pci_resource_len(dev->pdev, 0)); + LOG_INFO("pci_ioremap_addr=0x%llx, ioremap(0x%llx, 0x%llx)\n", mpf_dev->pci_ioremap_addr, pci_resource_start(dev->pdev, 0), pci_resource_len(dev->pdev, 0)); + if (mpf_dev->pci_ioremap_addr == 0) + { + ret = -1; + LOG_ERR("ioremap(0x%llx, 0x%llx) failed\n", pci_resource_start(dev->pdev, 0), pci_resource_len(dev->pdev, 0)); + goto err_pci_save_state; + } + + return 0; + +err_pci_save_state: + pci_disable_pcie_error_reporting(dev->pdev); + pci_release_selected_regions(dev->pdev, pci_select_bars(dev->pdev, IORESOURCE_MEM)); +err_pci: + pci_disable_device(dev->pdev); + return ret; +} + +static const struct pci_device_id dh_mpf_pci_table[] = { + { PCI_DEVICE(ZXDH_MPF_VENDOR_ID, ZXDH_MPF_DEVICE_ID), 0 }, + { 0, } +}; + +MODULE_DEVICE_TABLE(pci, dh_mpf_pci_table); + +void dh_mpf_pci_close(struct dh_core_dev *dev) +{ + struct dh_en_mpf_dev *mpf_dev = NULL; + + mpf_dev = dh_core_priv(dev); + iounmap((void *)mpf_dev->pci_ioremap_addr); + pci_disable_pcie_error_reporting(dev->pdev); + pci_release_selected_regions(dev->pdev, pci_select_bars(dev->pdev, IORESOURCE_MEM)); + pci_disable_device(dev->pdev); + + return; +} + +static int32_t dh_mpf_probe(struct pci_dev *pdev, const struct pci_device_id *id) +{ + struct dh_core_dev *dh_dev = NULL; + struct devlink *devlink = NULL; + int32_t err = 0; + + LOG_INFO("mpf driver start to probe\n"); + + devlink = zxdh_devlink_alloc(&pdev->dev, &dh_mpf_devlink_ops, sizeof(struct dh_en_mpf_dev)); + if (devlink == NULL) + { + dev_err(&pdev->dev, "devlink alloc failed\n"); + return -ENOMEM; + } + + dh_dev = devlink_priv(devlink); + dh_dev->device = &pdev->dev; + dh_dev->pdev = pdev; + dh_dev->devlink_ops = &dh_mpf_core_devlink_ops; + + err = dh_mpf_pci_init(dh_dev); + if (err != 0) + { + dev_err(&pdev->dev, "dh_mpf_pci_init failed: %d\n", err); + goto err_devlink_cleanup; + } + + err = dh_mpf_irq_table_init(dh_dev); + if (err != 0) + { + dh_err(dh_dev, "Failed to alloc IRQs\n"); + goto err_pci; + } + + err = dh_mpf_eq_table_init(dh_dev); + if (err != 0) + { + dh_err(dh_dev, "Failed to alloc IRQs\n"); + goto err_eq_table_init; + } + + err = dh_mpf_irq_table_create(dh_dev); + if (err != 0) + { + dh_err(dh_dev, "Failed to alloc IRQs\n"); + goto err_irq_table_create; + } + + err = dh_mpf_eq_table_create(dh_dev); + if (err != 0) + { + dh_err(dh_dev, "Failed to alloc EQs\n"); + goto err_eq_table_create; + } + + err = dh_mpf_events_init(dh_dev); + if (err != 0) + { + dh_err(dh_dev, "failed to initialize events\n"); + goto err_events_init_cleanup; + } + +#ifdef HAVE_DEVLINK_REGISTER_GET_1_PARAMS + zxdh_devlink_register(devlink); +#else + zxdh_devlink_register(devlink, &pdev->dev); +#endif + + LOG_INFO("mpf driver probe completed\n"); + return 0; + +err_events_init_cleanup: + dh_mpf_eq_table_destroy(dh_dev); +err_eq_table_create: + dh_mpf_irq_table_destroy(dh_dev); +err_irq_table_create: + dh_eq_table_cleanup(dh_dev); +err_eq_table_init: + dh_irq_table_cleanup(dh_dev); +err_pci: + dh_mpf_pci_close(dh_dev); +err_devlink_cleanup: + zxdh_devlink_free(devlink); + return err; +} + +static void dh_mpf_remove(struct pci_dev *pdev) +{ + struct dh_core_dev *dh_dev = pci_get_drvdata(pdev); + struct devlink *devlink = priv_to_devlink(dh_dev); + LOG_INFO("mpf driver start to remove"); + + zxdh_devlink_unregister(devlink); + dh_mpf_events_uninit(dh_dev); + dh_mpf_eq_table_destroy(dh_dev); + dh_mpf_irq_table_destroy(dh_dev); + dh_eq_table_cleanup(dh_dev); + dh_irq_table_cleanup(dh_dev); + dh_mpf_pci_close(dh_dev); + zxdh_devlink_free(devlink); + + pci_set_drvdata(pdev, NULL); + LOG_INFO("mpf driver remove completed\n"); +} + +static int32_t dh_mpf_suspend(struct pci_dev *pdev, pm_message_t state) +{ + + return 0; +} + +static int32_t dh_mpf_resume(struct pci_dev *pdev) +{ + + return 0; +} + +static void dh_mpf_shutdown(struct pci_dev *pdev) +{ + dh_mpf_remove(pdev); +} + +static pci_ers_result_t dh_pci_err_detected(struct pci_dev *pdev, + pci_channel_state_t state) +{ + return PCI_ERS_RESULT_NONE; +} + +static pci_ers_result_t dh_mpf_pci_slot_reset(struct pci_dev *pdev) +{ + return PCI_ERS_RESULT_NONE; +} + +static void dh_mpf_pci_resume(struct pci_dev *pdev) +{ + +} + +static const struct pci_error_handlers dh_mpf_err_handler = { + .error_detected = dh_pci_err_detected, + .slot_reset = dh_mpf_pci_slot_reset, + .resume = dh_mpf_pci_resume +}; + +static struct pci_driver dh_mpf_driver = { + .name = KBUILD_MODNAME, + .id_table = dh_mpf_pci_table, + .probe = dh_mpf_probe, + .remove = dh_mpf_remove, + .suspend = dh_mpf_suspend, + .resume = dh_mpf_resume, + .shutdown = dh_mpf_shutdown, + .err_handler = &dh_mpf_err_handler, +}; + +static int32_t __init init(void) +{ + int32_t err = 0; + + err = pci_register_driver(&dh_mpf_driver); + if (err != 0) + { + LOG_ERR("pci_register_driver failed: %d\n", err); + return err; + } + +#ifdef CONFIG_ZXDH_SF + err = zxdh_mpf_sf_driver_register(); + if (err != 0) + { + LOG_ERR("zxdh_en_sf_driver_register failed: %d\n", err); + goto err_sf; + } +#endif + + LOG_INFO("zxdh_mpf driver init success\n"); + + return 0; + +err_sf: + pci_unregister_driver(&dh_mpf_driver); + return err; +} + +static void __exit cleanup(void) +{ +#ifdef CONFIG_ZXDH_SF + zxdh_mpf_sf_driver_uregister(); +#endif + pci_unregister_driver(&dh_mpf_driver); + + LOG_INFO("zxdh_mpf driver remove success\n"); +} + +module_init(init); +module_exit(cleanup); diff --git a/src/net/drivers/net/ethernet/dinghai/en_mpf.h b/src/net/drivers/net/ethernet/dinghai/en_mpf.h new file mode 100755 index 0000000..cd1ee3c --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_mpf.h @@ -0,0 +1,32 @@ +#ifndef __ZXDH_EN_MPF_H__ +#define __ZXDH_EN_MPF_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#define ZXDH_MPF_VENDOR_ID 0x1111 +#define ZXDH_MPF_DEVICE_ID 0x1041 + +#define ZXDH_BAR1_CHAN_OFFSET 0x2000//0x7801000 +#define ZXDH_BAR2_CHAN_OFFSET 0x3000//0x7802000 + +struct dh_en_mpf_dev { + uint16_t ep_bdf; + uint16_t pcie_id; + uint16_t vport; + + uint64_t pci_ioremap_addr; + + struct work_struct dh_np_sdk_from_risc; + struct work_struct dh_np_sdk_from_pf; +}; + +#ifdef __cplusplus +} +#endif + +#endif /* __ZXDH_EN_MPF_H__ */ \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_mpf/cfg_sf.c b/src/net/drivers/net/ethernet/dinghai/en_mpf/cfg_sf.c new file mode 100755 index 0000000..1ddde92 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_mpf/cfg_sf.c @@ -0,0 +1,54 @@ +#include +#include +#include + +#include "cfg_sf.h" + +static int32_t zxdh_cfg_resume(struct zxdh_auxiliary_device *adev) +{ + return 0; +} + +static int32_t zxdh_cfg_suspend(struct zxdh_auxiliary_device *adev, pm_message_t state) +{ + return 0; +} + +static int32_t zxdh_cfg_probe(struct zxdh_auxiliary_device *adev, + const struct zxdh_auxiliary_device_id *id) +{ + struct cfg_sf_dev * __attribute__((unused)) cfg_sf_dev = container_of(adev, struct cfg_sf_dev, adev); + + return 0; +} + +static int32_t zxdh_cfg_remove(struct zxdh_auxiliary_device *adev) +{ + return 0; +} + +static const struct zxdh_auxiliary_device_id zxdh_cfg_id_table[] = { + { .name = ZXDH_EN_SF_NAME ".mpf_cfg", }, + {}, +}; + +//MODULE_DEVICE_TABLE(auxiliary_zxdh_id_table, zxdh_cfg_id_table); + +static struct zxdh_auxiliary_driver zxdh_cfg_driver = { + .name = "mpf_cfg", + .probe = zxdh_cfg_probe, + .remove = zxdh_cfg_remove, + .suspend = zxdh_cfg_suspend, + .resume = zxdh_cfg_resume, + .id_table = zxdh_cfg_id_table, +}; + +int32_t zxdh_mpf_sf_driver_register(void) +{ + return zxdh_auxiliary_driver_register(&zxdh_cfg_driver);; +} + +void zxdh_mpf_sf_driver_uregister(void) +{ + zxdh_auxiliary_driver_unregister(&zxdh_cfg_driver);; +} diff --git a/src/net/drivers/net/ethernet/dinghai/en_mpf/cfg_sf.h b/src/net/drivers/net/ethernet/dinghai/en_mpf/cfg_sf.h new file mode 100755 index 0000000..ec0fdd0 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_mpf/cfg_sf.h @@ -0,0 +1,30 @@ +#ifndef __ZXDH_MPF_CFG_SF_H__ +#define __ZXDH_MPF_CFG_SF_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +struct cfg_sf_ops { + +}; + +struct cfg_sf_dev { + struct zxdh_auxiliary_device adev; + struct dh_core_dev *dh_dev; + struct cfg_sf_ops *ops; +}; + +int32_t zxdh_mpf_sf_driver_register(void); +void zxdh_mpf_sf_driver_uregister(void); + + +#ifdef __cplusplus +} +#endif + + +#endif \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_mpf/devlink.c b/src/net/drivers/net/ethernet/dinghai/en_mpf/devlink.c new file mode 100755 index 0000000..e89a752 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_mpf/devlink.c @@ -0,0 +1,130 @@ +#include +#include +#include "devlink.h" + +struct devlink_ops dh_mpf_devlink_ops = { + +}; + +enum { + DH_MPF_PARAMS_MAX, +}; + +static int32_t __attribute__((unused)) sample_check(struct dh_core_dev *dev) +{ + return 1; +} + +enum dh_mpf_devlink_param_id { + DH_MPF_DEVLINK_PARAM_ID_BASE = DEVLINK_PARAM_GENERIC_ID_MAX, + DH_MPF_DEVLINK_PARAM_ID_SAMPLE, +}; + + +static int32_t dh_devlink_sample_set(struct devlink *devlink, uint32_t id, + struct devlink_param_gset_ctx *ctx) +{ + struct dh_core_dev * __attribute__((unused)) dev = devlink_priv(devlink); + + return 0; +} + +static int32_t dh_devlink_sample_get(struct devlink *devlink, uint32_t id, + struct devlink_param_gset_ctx *ctx) +{ + struct dh_core_dev * __attribute__((unused)) dev = devlink_priv(devlink); + + return 0; +} + +#ifdef HAVE_DEVLINK_PARAM_REGISTER +static const struct devlink_params { + const char *name; + int32_t (*check)(struct dh_core_dev *dev); + struct devlink_param param; +} devlink_params[] = { + [DH_MPF_PARAMS_MAX] = { .name = "sample", + .check = &sample_check, + .param = DEVLINK_PARAM_DRIVER(DH_MPF_DEVLINK_PARAM_ID_SAMPLE, + "sample", DEVLINK_PARAM_TYPE_BOOL, + BIT(DEVLINK_PARAM_CMODE_RUNTIME),dh_devlink_sample_get, + dh_devlink_sample_set, + NULL), + } +}; + +static int32_t params_register(struct devlink *devlink) +{ + int32_t i = 0; + int32_t err = 0; + struct dh_core_dev *dh_dev = devlink_priv(devlink); + + for (i = 0; i < ARRAY_SIZE(devlink_params); i++) + { + if(devlink_params[i].check(dh_dev)) + { + err = devlink_param_register(devlink, &devlink_params[i].param); + if (err) + { + goto rollback; + } + } + } + + return 0; + +rollback: + if (i == 0) + { + return err; + } + + for (; i > 0; i--) + { + devlink_param_unregister(devlink, &devlink_params[i].param); + } + + return err; +} + +static int32_t params_unregister(struct devlink *devlink) +{ + int32_t i = 0; + + for (i = 0; i < ARRAY_SIZE(devlink_params); i++) + { + devlink_param_unregister(devlink, &devlink_params[i].param); + } + + return 0; +} +#else +static struct devlink_param devlink_params [] = { + [DH_MPF_PARAMS_MAX] = DEVLINK_PARAM_DRIVER(DH_MPF_DEVLINK_PARAM_ID_SAMPLE, + "sample", DEVLINK_PARAM_TYPE_BOOL, + BIT(DEVLINK_PARAM_CMODE_RUNTIME),dh_devlink_sample_get, + dh_devlink_sample_set, + NULL), +}; + +static int32_t params_register(struct devlink *devlink) +{ + struct dh_core_dev * __attribute__((unused)) dh_dev = devlink_priv(devlink); + int32_t err = 0; + + err = devlink_params_register(devlink, devlink_params, ARRAY_SIZE(devlink_params)); + + return err; +} +static int32_t params_unregister(struct devlink *devlink) +{ + devlink_params_unregister(devlink, devlink_params, ARRAY_SIZE(devlink_params)); + + return 0; +} +#endif + +struct dh_core_devlink_ops dh_mpf_core_devlink_ops = { + .params_register = params_register, + .params_unregister = params_unregister +}; diff --git a/src/net/drivers/net/ethernet/dinghai/en_mpf/devlink.h b/src/net/drivers/net/ethernet/dinghai/en_mpf/devlink.h new file mode 100755 index 0000000..a45fd10 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_mpf/devlink.h @@ -0,0 +1,16 @@ +#ifndef __ZXDH_MPF_DEVLINK_H__ +#define __ZXDH_MPF_DEVLINK_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + + + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_mpf/eq.c b/src/net/drivers/net/ethernet/dinghai/en_mpf/eq.c new file mode 100755 index 0000000..0d8b612 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_mpf/eq.c @@ -0,0 +1,235 @@ +#include +#include +#include +#include +#include "irq.h" +#include "eq.h" +#include "../en_mpf.h" + +struct dh_mpf_eq_table { + struct dh_irq **comp_irqs; + struct dh_irq *async_risc_irq; + struct dh_irq *async_pf_irq; + struct dh_eq_async async_risc_eq; + struct dh_eq_async async_pf_eq; +}; + +static int32_t create_async_eqs(struct dh_core_dev *dev); + +static int32_t __attribute__((unused)) create_eq_map(struct dh_eq_param *param) +{ + int32_t err = 0; + + /* inform device*/ + return err; +} + +int32_t dh_mpf_eq_table_init(struct dh_core_dev *dev) +{ + struct dh_eq_table *eq_table; + struct dh_mpf_eq_table *table_priv = NULL; + int32_t err = 0; + + eq_table = &dev->eq_table; + + table_priv = kvzalloc(sizeof(*table_priv), GFP_KERNEL); + if (unlikely(table_priv == NULL)) + { + err = -ENOMEM; + goto err_table_priv; + } + + dh_eq_table_init(dev, table_priv); + + return 0; + +err_table_priv: + kvfree(eq_table); + return err; +} + +/*todo*/ +int32_t dh_eq_get_comp_eqs(struct dh_core_dev *dev) +{ + return 0; +} + +static int32_t create_comp_eqs(struct dh_core_dev *dev) +{ + return 0; +} + +static int32_t destroy_async_eq(struct dh_core_dev *dev) +{ + struct dh_eq_table *eq_table = &dev->eq_table; + + mutex_lock(&eq_table->lock); + /*unmap inform device*/ + mutex_unlock(&eq_table->lock); + + return 0; +} + +static void cleanup_async_eq(struct dh_core_dev *dev, + struct dh_eq_async *eq, const char *name) +{ + dh_eq_disable(dev, &eq->core, &eq->irq_nb); +} + +static void destroy_async_eqs(struct dh_core_dev *dev) +{ + struct dh_eq_table *table = &dev->eq_table; + struct dh_mpf_eq_table *table_priv = table->priv; + + cleanup_async_eq(dev, &table_priv->async_risc_eq, "riscv"); + cleanup_async_eq(dev, &table_priv->async_pf_eq, "pf"); + destroy_async_eq(dev); + dh_irqs_release_vectors(&table_priv->async_risc_irq, 1); + dh_irqs_release_vectors(&table_priv->async_pf_irq, 1); +} + +void destroy_comp_eqs(struct dh_core_dev *dev) +{ + +} + +void dh_mpf_eq_table_destroy(struct dh_core_dev *dev) +{ + destroy_comp_eqs(dev); + destroy_async_eqs(dev); +} + +int32_t dh_mpf_eq_table_create(struct dh_core_dev *dev) +{ + int32_t err = 0; + + err = create_async_eqs(dev); + if (err != 0) + { + dh_err(dev, "Failed to create async EQs\n"); + goto err_async_eqs; + } + + err = create_comp_eqs(dev); + if (err != 0) + { + dh_err(dev, "Failed to create completion EQs\n"); + goto err_comp_eqs; + } + + return 0; + +err_comp_eqs: + destroy_async_eqs(dev); +err_async_eqs: + return err; +} + +/*create eventq*/ +static int32_t create_async_eq(struct dh_core_dev *dev, struct dh_irq *risc, struct dh_irq *pf) +{ + struct dh_eq_table *eq_table = &dev->eq_table; + struct dh_en_mpf_dev *mpf_dev = dh_core_priv(dev); + struct msix_para in = {0}; + int32_t err = 0; + + in.vector_risc = risc->index; + in.vector_pfvf = pf->index; + in.vector_mpf = 0xff; + in.driver_type = MSG_CHAN_END_PF;//TODO + in.pdev = dev->pdev; + in.virt_addr = mpf_dev->pci_ioremap_addr + ZXDH_BAR1_CHAN_OFFSET; + + mutex_lock(&eq_table->lock); + + err = zxdh_bar_enable_chan(&in, &mpf_dev->vport); + + mutex_unlock(&eq_table->lock); + + return err; +} + +static int32_t dh_eq_async_riscv_int(struct notifier_block *nb, unsigned long action, void *data) +{ + struct dh_eq_async *eq_riscv_async = container_of(nb, struct dh_eq_async, irq_nb); + struct dh_core_dev *dev = (struct dh_core_dev *)eq_riscv_async->priv; + struct dh_eq_table *eq_table = &dev->eq_table; + + atomic_notifier_call_chain(&eq_table->nh[DH_EVENT_TYPE_NOTIFY_RISC_TO_MPF], DH_EVENT_TYPE_NOTIFY_RISC_TO_MPF, NULL); + + return 0; +} + +static int32_t dh_eq_async_mpf_int(struct notifier_block *nb, unsigned long action, void *data) +{ + struct dh_eq_async *eq_riscv_async = container_of(nb, struct dh_eq_async, irq_nb); + struct dh_core_dev *dev = (struct dh_core_dev *)eq_riscv_async->priv; + struct dh_eq_table *eq_table = &dev->eq_table; + + atomic_notifier_call_chain(&eq_table->nh[DH_EVENT_TYPE_NOTIFY_PF_TO_MPF], DH_EVENT_TYPE_NOTIFY_PF_TO_MPF, NULL); + + return 0; +} + +static int32_t create_async_eqs(struct dh_core_dev *dev) +{ + struct dh_eq_table *table = &dev->eq_table; + struct dh_mpf_eq_table *table_priv = table->priv; + struct dh_eq_param param = {}; + int32_t err = 0; + + dh_dbg(dev, "start\r\n"); + table_priv->async_risc_irq = dh_mpf_async_irq_request(dev); + if (IS_ERR_OR_NULL(table_priv->async_risc_irq)) + { + dh_err(dev, "Failed to get async_risc_irq\n"); + return PTR_ERR(table_priv->async_risc_irq); + } + + table_priv->async_pf_irq = dh_mpf_async_irq_request(dev); + if (IS_ERR_OR_NULL(table_priv->async_pf_irq)) + { + err = PTR_ERR(table_priv->async_pf_irq); + dh_err(dev, "Failed to get async_pf_irq\n"); + goto err_irq_request; + } + + err = create_async_eq(dev, table_priv->async_risc_irq, table_priv->async_pf_irq); + if (err != 0) + { + dh_err(dev, "Failed to create async_eq\n"); + goto err_create_async_eq; + } + + param = (struct dh_eq_param) { + .irq = table_priv->async_risc_irq, + .nent = 10, + .event_type = DH_EVENT_QUEUE_TYPE_RISCV /* used for inform dpu */ + }; + err = setup_async_eq(dev, &table_priv->async_risc_eq, ¶m, dh_eq_async_riscv_int, "riscv", dev); + if (err != 0) + { + dh_err(dev, "Failed to setup async_risc_eq\n"); + goto err_setup_async_eq; + } + + param.irq = table_priv->async_pf_irq, + err = setup_async_eq(dev, &table_priv->async_pf_eq, ¶m, dh_eq_async_mpf_int, "pf", dev); + if (err != 0) + { + dh_err(dev, "Failed to setup async_pf_eq\n"); + goto cleanup_async_eq; + } + + return 0; + +cleanup_async_eq: + cleanup_async_eq(dev, &table_priv->async_risc_eq, "riscv"); +err_setup_async_eq: + destroy_async_eq(dev); +err_create_async_eq: + dh_irqs_release_vectors(&table_priv->async_pf_irq, 1); +err_irq_request: + dh_irqs_release_vectors(&table_priv->async_risc_irq, 1); + return err; +} \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_mpf/eq.h b/src/net/drivers/net/ethernet/dinghai/en_mpf/eq.h new file mode 100755 index 0000000..4aaaaae --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_mpf/eq.h @@ -0,0 +1,19 @@ +#ifndef __ZXDH_MPF_EQ_H__ +#define __ZXDH_MPF_EQ_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +int32_t dh_mpf_eq_table_init(struct dh_core_dev *dev); + +int32_t dh_mpf_eq_table_create(struct dh_core_dev *dev); +void dh_mpf_eq_table_destroy(struct dh_core_dev *dev); + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_mpf/events.c b/src/net/drivers/net/ethernet/dinghai/en_mpf/events.c new file mode 100755 index 0000000..35aaf52 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_mpf/events.c @@ -0,0 +1,132 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include "events.h" +#include "../en_mpf.h" + +static int32_t riscv_notifier(struct notifier_block *nb, unsigned long type, void *data); +static int32_t pf_notifier(struct notifier_block *nb, unsigned long type, void *data); + +static struct dh_nb mpf_events[] = { + {.nb.notifier_call = riscv_notifier, .event_type = DH_EVENT_TYPE_NOTIFY_RISC_TO_MPF}, + {.nb.notifier_call = pf_notifier, .event_type = DH_EVENT_TYPE_NOTIFY_PF_TO_MPF} +}; + +static int32_t riscv_notifier(struct notifier_block *nb, unsigned long type, void *data) +{ + struct dh_event_nb *event_nb = dh_nb_cof(nb, struct dh_event_nb, nb); + struct dh_core_dev *dh_dev = (struct dh_core_dev *)event_nb->ctx; + struct dh_en_mpf_dev *mpf_dev = dh_core_priv(dh_dev); + + zxdh_events_work_enqueue(dh_dev, &mpf_dev->dh_np_sdk_from_risc); + + return NOTIFY_OK; +} + +static int32_t pf_notifier(struct notifier_block *nb, unsigned long type, void *data) +{ + struct dh_event_nb *event_nb = dh_nb_cof(nb, struct dh_event_nb, nb); + struct dh_core_dev *dh_dev = (struct dh_core_dev *)event_nb->ctx; + struct dh_en_mpf_dev *mpf_dev = dh_core_priv(dh_dev); + + zxdh_events_work_enqueue(dh_dev, &mpf_dev->dh_np_sdk_from_pf); + + return NOTIFY_OK; +} + +void np_sdk_handler_from_risc(struct work_struct *p_work) +{ + struct dh_en_mpf_dev *mpf_dev = container_of(p_work, struct dh_en_mpf_dev, dh_np_sdk_from_risc); + + LOG_INFO("is called\n"); + zxdh_bar_irq_recv(MSG_CHAN_END_RISC, MSG_CHAN_END_MPF, mpf_dev->pci_ioremap_addr + ZXDH_BAR1_CHAN_OFFSET, NULL); + return; +} + +void np_sdk_handler_from_pf(struct work_struct *p_work) +{ + struct dh_en_mpf_dev *mpf_dev = container_of(p_work, struct dh_en_mpf_dev, dh_np_sdk_from_pf); + + LOG_INFO("is called\n"); + zxdh_bar_irq_recv(MSG_CHAN_END_PF, MSG_CHAN_END_MPF, mpf_dev->pci_ioremap_addr + ZXDH_BAR2_CHAN_OFFSET, NULL); + return; +} + +void zxdh_events_start(struct dh_core_dev *dev) +{ + struct dh_events *events = dev->events; + int32_t i; + int32_t err; + + for (i = 0; i < ARRAY_SIZE(mpf_events); i++) + { + events->notifiers[i].nb = mpf_events[i]; + events->notifiers[i].ctx = dev; + err = dh_eq_notifier_register(&dev->eq_table, &events->notifiers[i].nb); + if (err != 0) + { + LOG_ERR("i: %d, err: %d.\n", i, err); + } + } +} + +int32_t dh_mpf_events_init(struct dh_core_dev *dev) +{ + struct dh_events *events = NULL; + struct dh_en_mpf_dev *mpf_dev = dh_core_priv(dev); + int32_t ret = 0; + + events = kzalloc((sizeof(*events) + ARRAY_SIZE(mpf_events) * sizeof(struct dh_event_nb)), GFP_KERNEL); + if (unlikely(events == NULL)) + { + LOG_ERR("events kzalloc failed: %p\n", events); + ret = -ENOMEM; + goto err_events_kzalloc; + } + + events->evt_num = ARRAY_SIZE(mpf_events); + events->dev = dev; + dev->events = events; + events->wq = create_singlethread_workqueue("dh_mpf_events"); + if (!events->wq) + { + LOG_ERR("events->wq create_singlethread_workqueue failed: %p\n", events->wq); + ret = -ENOMEM; + goto err_create_wq; + } + + INIT_WORK(&mpf_dev->dh_np_sdk_from_risc, np_sdk_handler_from_risc); + INIT_WORK(&mpf_dev->dh_np_sdk_from_pf, np_sdk_handler_from_pf); + + zxdh_events_start(dev); + + return 0; + +err_create_wq: + kfree(events); +err_events_kzalloc: + return ret; +} + +void dh_events_stop(struct dh_core_dev *dev) +{ + struct dh_events *events = dev->events; + int32_t i = 0; + + for (i = ARRAY_SIZE(mpf_events) - 1; i >= 0 ; i--) + { + dh_eq_notifier_unregister(&dev->eq_table, &events->notifiers[i].nb); + } + + zxdh_events_cleanup(dev); +} + +void dh_mpf_events_uninit(struct dh_core_dev *dev) +{ + return dh_events_stop(dev); +} \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_mpf/events.h b/src/net/drivers/net/ethernet/dinghai/en_mpf/events.h new file mode 100755 index 0000000..496097e --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_mpf/events.h @@ -0,0 +1,18 @@ +#ifndef __ZXDH_MPF_EVENTS_H__ +#define __ZXDH_MPF_EVENTS_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +int32_t dh_mpf_events_init(struct dh_core_dev *dev); +void dh_mpf_events_uninit(struct dh_core_dev *dev); +void zxdh_events_start(struct dh_core_dev *dev); + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_mpf/irq.c b/src/net/drivers/net/ethernet/dinghai/en_mpf/irq.c new file mode 100755 index 0000000..a1ccaab --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_mpf/irq.c @@ -0,0 +1,171 @@ +#include +#include +#include +#include "irq.h" + +#define ZXDH_MPF_ASYNC_IRQ_MIN_COMP 0 +#define ZXDH_MPF_ASYNC_IRQ_MAX_COMP 1 + +#define ZXDH_MPF_COMP_IRQ_MIN_COMP 0 +#define ZXDH_MPF_COMP_IRQ_MAX_COMP 1 + +#ifndef CONFIG_DINGHAI_ZF_MPF +#define ZXDH_MPF_ASYNC_IRQ_NUM 2 +#else +#define ZXDH_MPF_ASYNC_IRQ_NUM 6 +#endif + +struct dh_mpf_irq_table { + struct dh_irq_pool *mpf_comp_pool; + struct dh_irq_pool *mpf_async_pool; +}; + +struct dh_irq_range { + int32_t start; + int32_t size; +}; + +static struct dh_irq_range zxdh_get_mpf_range(struct dh_core_dev *dev) +{ + struct dh_irq_range tmp = { + .start = 0, + .size = ZXDH_MPF_ASYNC_IRQ_NUM + }; + + return tmp; +} +static struct dh_irq_range zxdh_get_comp_mpf_range(struct dh_core_dev *dev) +{ + struct dh_irq_range tmp = { + .start = ZXDH_MPF_ASYNC_IRQ_NUM + 1, + .size = ZXDH_MPF_ASYNC_IRQ_NUM + 1 + }; + + return tmp; +} + +static int32_t irq_pools_init(struct dh_core_dev *dev) +{ + struct dh_irq_table *table = &dev->irq_table; + int32_t err = 0; + struct dh_irq_range irq_range; + struct dh_mpf_irq_table * mpf_irq_table = table->priv; + + /* init mpf_pool */ + irq_range = zxdh_get_mpf_range(dev); + + mpf_irq_table->mpf_async_pool = irq_pool_alloc(dev, irq_range.start, irq_range.size, "zxdh_mpf_msg", + ZXDH_MPF_ASYNC_IRQ_MIN_COMP, + ZXDH_MPF_ASYNC_IRQ_MAX_COMP); + if (IS_ERR_OR_NULL(mpf_irq_table->mpf_async_pool)) + { + return PTR_ERR(mpf_irq_table->mpf_async_pool); + } + + /* init sf_comp_pool */ + irq_range = zxdh_get_comp_mpf_range(dev); + + mpf_irq_table->mpf_comp_pool = irq_pool_alloc(dev, irq_range.start, + irq_range.size, "zxdh_mpf_comp", + ZXDH_MPF_COMP_IRQ_MIN_COMP, + ZXDH_MPF_COMP_IRQ_MAX_COMP); + if (IS_ERR_OR_NULL(mpf_irq_table->mpf_comp_pool)) + { + err = PTR_ERR(mpf_irq_table->mpf_comp_pool); + goto err_mpf_comp; + } + + mpf_irq_table->mpf_comp_pool->irqs_per_cpu = kcalloc(nr_cpu_ids, sizeof(u16), GFP_KERNEL); + if (unlikely(mpf_irq_table->mpf_comp_pool->irqs_per_cpu == NULL)) + { + err = -ENOMEM; + goto err_irqs_per_cpu; + } + + return 0; + +err_irqs_per_cpu: + irq_pool_free(mpf_irq_table->mpf_comp_pool); +err_mpf_comp: + irq_pool_free(mpf_irq_table->mpf_async_pool); + return err; +} + +static void irq_pools_destroy(struct dh_irq_table *table) +{ + struct dh_mpf_irq_table *mpf_irq_table = (struct dh_mpf_irq_table *)table->priv; + + irq_pool_free(mpf_irq_table->mpf_comp_pool); + irq_pool_free(mpf_irq_table->mpf_async_pool); +} + +/*todo*/ +static int32_t zxdh_get_total_vec(struct dh_core_dev *dev) +{ + return ZXDH_MPF_ASYNC_IRQ_NUM; +} + +int32_t dh_mpf_irq_table_create(struct dh_core_dev *dev) +{ + int32_t total_vec = 0; + int32_t err = 0; + + total_vec = zxdh_get_total_vec(dev); + + total_vec = pci_alloc_irq_vectors(dev->pdev, total_vec, total_vec, PCI_IRQ_MSIX); + if (total_vec < 0) + { + dh_err(dev, "pci_alloc_irq_vectors failed: %d\n", total_vec); + return total_vec; + } + + err = irq_pools_init(dev); + if (err != 0) + { + pci_free_irq_vectors(dev->pdev); + } + + return err; +} + +void dh_mpf_irq_table_destroy(struct dh_core_dev *dev) +{ + struct dh_irq_table *table = &dev->irq_table; + + /* There are cases where IRQs still will be in used when we reaching + * to here. Hence, making sure all the irqs are released. + */ + irq_pools_destroy(table); + pci_free_irq_vectors(dev->pdev); +} + +struct dh_irq *dh_mpf_async_irq_request(struct dh_core_dev *dev) +{ + struct dh_irq_table *table = &dev->irq_table; + struct dh_mpf_irq_table *mpf_irq_table = (struct dh_mpf_irq_table *)table->priv; + + struct dh_irq *irq = zxdh_get_irq_of_pool(dev, mpf_irq_table->mpf_async_pool); + if (IS_ERR_OR_NULL(irq)) + dh_err(dev, "irq=0x%llx\r\n", (unsigned long long)irq); + dh_dbg(dev, "end\r\n"); + return irq; +} + +/* irq_table API */ +int32_t dh_mpf_irq_table_init(struct dh_core_dev *dev) +{ + struct dh_irq_table *irq_table; + struct dh_mpf_irq_table * mpf_irq_table = NULL; + + irq_table = &dev->irq_table; + + mpf_irq_table = kvzalloc(sizeof(*mpf_irq_table), GFP_KERNEL); + if (unlikely(mpf_irq_table == NULL)) + { + return -ENOMEM; + } + + irq_table->priv = mpf_irq_table; + + return 0; +} diff --git a/src/net/drivers/net/ethernet/dinghai/en_mpf/irq.h b/src/net/drivers/net/ethernet/dinghai/en_mpf/irq.h new file mode 100755 index 0000000..8cb582b --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_mpf/irq.h @@ -0,0 +1,20 @@ +#ifndef __ZXDH_MPF_IRQ_H__ +#define __ZXDH_MPF_IRQ_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +struct dh_irq *dh_mpf_async_irq_request(struct dh_core_dev *dev); +void dh_mpf_irq_table_destroy(struct dh_core_dev *dev); +int32_t dh_mpf_irq_table_create(struct dh_core_dev *dev); +int32_t dh_mpf_irq_table_init(struct dh_core_dev *dev); + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_mpf/tc.c b/src/net/drivers/net/ethernet/dinghai/en_mpf/tc.c new file mode 100755 index 0000000..e69de29 diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/.clang-format b/src/net/drivers/net/ethernet/dinghai/en_np/.clang-format new file mode 100644 index 0000000..983c4fc --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/.clang-format @@ -0,0 +1,176 @@ +--- +# 语言: None, Cpp, Java, JavaScript, ObjC, Proto, TableGen, TextProto +Language: Cpp +# BasedOnStyle: LLVM +# 访问说明符(public、private等)的偏移 +AccessModifierOffset: -4 +# 开括号(开圆括号、开尖括号、开方括号)后的对齐: Align, DontAlign, AlwaysBreak(总是在开括号后换行) +AlignAfterOpenBracket: Align +# 连续赋值时，对齐所有等号 +AlignConsecutiveAssignments: true +# 连续声明时，对齐所有声明的变量名 +AlignConsecutiveDeclarations: false +# 左对齐逃脱换行(使用反斜杠换行)的反斜杠 +AlignEscapedNewlinesLeft: true +# 水平对齐二元和三元表达式的操作数 +AlignOperands: true +# 对齐连续的尾随的注释 +AlignTrailingComments: true +# 允许函数声明的所有参数在放在下一行 +AllowAllParametersOfDeclarationOnNextLine: false +# 允许短的块放在同一行 +AllowShortBlocksOnASingleLine: false +# 允许短的case标签放在同一行 +AllowShortCaseLabelsOnASingleLine: false +# 允许短的函数放在同一行: None, InlineOnly(定义在类中), Empty(空函数), Inline(定义在类中，空函数), All +AllowShortFunctionsOnASingleLine: Empty +# 允许短的if语句保持在同一行 +AllowShortIfStatementsOnASingleLine: false +# 允许短的循环保持在同一行 +AllowShortLoopsOnASingleLine: false +# 总是在定义返回类型后换行(deprecated) +AlwaysBreakAfterDefinitionReturnType: None +# 总是在返回类型后换行: None, All, TopLevel(顶级函数，不包括在类中的函数), +# AllDefinitions(所有的定义，不包括声明), TopLevelDefinitions(所有的顶级函数的定义) +AlwaysBreakAfterReturnType: None +# 总是在多行string字面量前换行 +AlwaysBreakBeforeMultilineStrings: false +# 总是在template声明后换行 +AlwaysBreakTemplateDeclarations: true +# false表示函数实参要么都在同一行，要么都各自一行 +BinPackArguments: true +# false表示所有形参要么都在同一行，要么都各自一行 +BinPackParameters: true +# 大括号换行，只有当BreakBeforeBraces设置为Custom时才有效 +BraceWrapping: + # class定义后面 + AfterClass: false + # 控制语句后面 + AfterControlStatement: false + # enum定义后面 + AfterEnum: false + # 函数定义后面 + AfterFunction: false + # 命名空间定义后面 + AfterNamespace: false + # ObjC定义后面 + AfterObjCDeclaration: false + # struct定义后面 + AfterStruct: false + # union定义后面 + AfterUnion: false + # catch之前 + BeforeCatch: true + # else之前 + BeforeElse: true + # 缩进大括号 + IndentBraces: false +# 在二元运算符前换行: None(在操作符后换行), NonAssignment(在非赋值的操作符前换行), All(在操作符前换行) +BreakBeforeBinaryOperators: NonAssignment +# 在大括号前换行: Attach(始终将大括号附加到周围的上下文), Linux(除函数、命名空间和类定义，与Attach类似), +# Mozilla(除枚举、函数、记录定义，与Attach类似), Stroustrup(除函数定义、catch、else，与Attach类似), +# Allman(总是在大括号前换行), GNU(总是在大括号前换行，并对于控制语句的大括号增加额外的缩进), WebKit(在函数前换行), Custom +# 注：这里认为语句块也属于函数 +BreakBeforeBraces: Allman +# 在三元运算符前换行 +BreakBeforeTernaryOperators: true +# 在构造函数的初始化列表的逗号前换行 +BreakConstructorInitializersBeforeComma: false +# 每行字符的限制，0表示没有限制 +ColumnLimit: 120 +# 描述具有特殊意义的注释的正则表达式，它不应该被分割为多行或以其它方式改变 +CommentPragmas: '^ IWYU pragma:' +# 构造函数的初始化列表要么都在同一行，要么都各自一行 +ConstructorInitializerAllOnOneLineOrOnePerLine: false +# 构造函数的初始化列表的缩进宽度 +ConstructorInitializerIndentWidth: 4 +# 延续的行的缩进宽度 +ContinuationIndentWidth: 4 +# 去除C++11的列表初始化的大括号{后和}前的空格 +Cpp11BracedListStyle: true +# 继承最常用的指针和引用的对齐方式 +DerivePointerAlignment: false +# 关闭格式化 +DisableFormat: false +# 自动检测函数的调用和定义是否被格式为每行一个参数(Experimental) +ExperimentalAutoDetectBinPacking: false +# 宏对齐 使用VSCode所带的clang-format 在linux下也可以支持这个属性:) +AlignConsecutiveMacros: true +# 需要被解读为foreach循环而不是函数调用的宏 +ForEachMacros: [ foreach, Q_FOREACH, BOOST_FOREACH ] +# 对#include进行排序，匹配了某正则表达式的#include拥有对应的优先级，匹配不到的则默认优先级为INT_MAX(优先级越小排序越靠前)， +# 可以定义负数优先级从而保证某些#include永远在最前面 +IncludeCategories: + - Regex: '^"(llvm|llvm-c|clang|clang-c)/' + Priority: 2 + - Regex: '^(<|"(gtest|isl|json)/)' + Priority: 3 + - Regex: '.*' + Priority: 1 +# 缩进case标签 +IndentCaseLabels: true +# 缩进宽度 +IndentWidth: 4 +# 函数返回类型换行时，缩进函数声明或函数定义的函数名 +IndentWrappedFunctionNames: false +# 保留在块开始处的空行 +KeepEmptyLinesAtTheStartOfBlocks: true +# 开始一个块的宏的正则表达式 +MacroBlockBegin: '' +# 结束一个块的宏的正则表达式 +MacroBlockEnd: '' +# 连续空行的最大数量 +MaxEmptyLinesToKeep: 1 +# 命名空间的缩进: None, Inner(缩进嵌套的命名空间中的内容), All +NamespaceIndentation: Inner +# 使用ObjC块时缩进宽度 +ObjCBlockIndentWidth: 4 +# 在ObjC的@property后添加一个空格 +ObjCSpaceAfterProperty: false +# 在ObjC的protocol列表前添加一个空格 +ObjCSpaceBeforeProtocolList: true +# 在call(后对函数调用换行的penalty +PenaltyBreakBeforeFirstCallParameter: 19 +# 在一个注释中引入换行的penalty +PenaltyBreakComment: 300 +# 第一次在<<前换行的penalty +PenaltyBreakFirstLessLess: 120 +# 在一个字符串字面量中引入换行的penalty +PenaltyBreakString: 1000 +# 对于每个在行字符数限制之外的字符的penalty +PenaltyExcessCharacter: 1000000 +# 将函数的返回类型放到它自己的行的penalty +PenaltyReturnTypeOnItsOwnLine: 60 +# 指针和引用的对齐: Left, Right, Middle +PointerAlignment: Right +# 允许重新排版注释 +ReflowComments: true +# 允许排序#include +SortIncludes: false +# 在C风格类型转换后添加空格 +SpaceAfterCStyleCast: false +# 在赋值运算符之前添加空格 +SpaceBeforeAssignmentOperators: true +# 开圆括号之前添加一个空格: Never, ControlStatements, Always +SpaceBeforeParens: ControlStatements +# 在空的圆括号中添加空格 +SpaceInEmptyParentheses: false +# 在尾随的评论前添加的空格数(只适用于//) +SpacesBeforeTrailingComments: 2 +# 在尖括号的<后和>前添加空格 +SpacesInAngles: false +# 在容器(ObjC和JavaScript的数组和字典等)字面量中添加空格 +SpacesInContainerLiterals: false +# 在C风格类型转换的括号中添加空格 +SpacesInCStyleCastParentheses: false +# 在圆括号的(后和)前添加空格 +SpacesInParentheses: false +# 在方括号的[后和]前添加空格，lamda表达式和未指明大小的数组的声明不受影响 +SpacesInSquareBrackets: false +# 标准: Cpp03, Cpp11, Auto +Standard: Cpp03 +# tab宽度 +TabWidth: 4 +# 使用tab字符: Never, ForIndentation, ForContinuationAndIndentation, Always +UseTab: Never +... diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/.gitignore b/src/net/drivers/net/ethernet/dinghai/en_np/.gitignore new file mode 100644 index 0000000..8e5814e --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/.gitignore @@ -0,0 +1,13 @@ +*.o.cmd +*.o +*.o.d +*.ko.cmd +*.symvers +*.ko +*.mod.c +*.order +*.symvers.cmd +*.mod.cmd +*.order.cmd +*.mod +.tmp_versions/ diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/Makefile b/src/net/drivers/net/ethernet/dinghai/en_np/Makefile new file mode 100644 index 0000000..973d07b --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/Makefile @@ -0,0 +1,21 @@ +subdirs := en_np/agent/ +subdirs += en_np/cmd/ +subdirs += en_np/comm/ +subdirs += en_np/driver/ +subdirs += en_np/init/ +subdirs += en_np/netlink/ +subdirs += en_np/sdk/ +subdirs += en_np/table/ +subdirs += en_np/qos/ +subdirs += en_np/fc/ + +dinghai_root := $(CWD)/drivers/net/ethernet/dinghai +include $(dinghai_root)/en_np/Makefile.include + +src_files := +include $(foreach subdir, $(subdirs), $(dinghai_root)/$(subdir)Kbuild.include) +obj_files := $(src_files:.c=.o) + +obj-$(CONFIG_DINGHAI_NP) += zxdh_np.o +zxdh_np-y := $(obj_files) +# zxdh_np-$(CONFIG_DINGHAI_DH_CMD) += dh_cmd.o cmd/msg_chan_netlink.o cmd/msg_chan_lock.o diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/Makefile.include b/src/net/drivers/net/ethernet/dinghai/en_np/Makefile.include new file mode 100644 index 0000000..2ad68fe --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/Makefile.include @@ -0,0 +1,58 @@ +abs_include := -I$(dinghai_root)/en_np/agent/include +abs_include += -I$(dinghai_root)/en_np/cmd/include +abs_include += -I$(dinghai_root)/en_np/comm/include +abs_include += -I$(dinghai_root)/en_np/driver/include +abs_include += -I$(dinghai_root)/en_np/init/include +abs_include += -I$(dinghai_root)/en_np/netlink/include +abs_include += -I$(dinghai_root)/en_np/sdk/include/api +abs_include += -I$(dinghai_root)/en_np/sdk/include/dev/chip +abs_include += -I$(dinghai_root)/en_np/sdk/include/dev/init +abs_include += -I$(dinghai_root)/en_np/sdk/include/dev/module/cfg +abs_include += -I$(dinghai_root)/en_np/sdk/include/dev/module/dbg +abs_include += -I$(dinghai_root)/en_np/sdk/include/dev/module/ddos +abs_include += -I$(dinghai_root)/en_np/sdk/include/dev/module/dma +abs_include += -I$(dinghai_root)/en_np/sdk/include/dev/module/nppu +abs_include += -I$(dinghai_root)/en_np/sdk/include/dev/module/oam +abs_include += -I$(dinghai_root)/en_np/sdk/include/dev/module/ppu +abs_include += -I$(dinghai_root)/en_np/sdk/include/dev/module/se +abs_include += -I$(dinghai_root)/en_np/sdk/include/dev/module/table/sdt +abs_include += -I$(dinghai_root)/en_np/sdk/include/dev/module/table/se +abs_include += -I$(dinghai_root)/en_np/sdk/include/dev/module/tm +abs_include += -I$(dinghai_root)/en_np/sdk/include/dev/reg +abs_include += -I$(dinghai_root)/en_np/sdk/include/diag +abs_include += -I$(dinghai_root)/en_np/table/include +abs_include += -I$(dinghai_root)/en_np/qos/include +abs_include += -I$(dinghai_root)/en_np/fc/include + +abs_include += -I$(dinghai_root)/../../../../include/linux/dinghai +# ZF_MPF delete -msse -msse2 +# ccflags-y += $(abs_include) -DMACRO_CPU64 -DDPP_FOR_PCIE -DDPP_FLOW_HW_INIT +ccflags-y += $(abs_include) -DMACRO_CPU64 -DDPP_FOR_PCIE + +# ifeq (${ARCH},arm64) +# ccflags-y += -DDPP_FOR_AARCH64 +# endif + +dpp-rm-files := *.ko +dpp-rm-files += *.mod.c +dpp-rm-files += *.symvers +dpp-rm-files += *.order +dpp-rm-files += *.o +dpp-rm-files += .*.cmd +dpp-rm-files += .tmp_versions +dpp-rm-files += *.mod +export dpp-rm-files + +clean := -f $(DPP_KO_MAKEFILE_DIR)/Makefile.clean obj + +# echo command. +# Short version is used, if $(quiet) equals `quiet_', otherwise full one. +echo-cmd = $(if $($(quiet)cmd_$(1)), echo ' $($(quiet)cmd_$(1))';) + +# sink stdout for 'make -s' + redirect := + quiet_redirect := +silent_redirect := exec >/dev/null; + +# printing commands +cmd = @set -e; $(echo-cmd) $($(quiet)redirect) $(cmd_$(1)) \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/agent/Kbuild.include b/src/net/drivers/net/ethernet/dinghai/en_np/agent/Kbuild.include new file mode 100644 index 0000000..2c53485 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/agent/Kbuild.include @@ -0,0 +1,4 @@ +cur_dir := en_np/agent/ +subdirs := source/ +src_files += +include $(foreach subdir, $(subdirs), $(dinghai_root)/$(cur_dir)$(subdir)/Kbuild.include) \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/agent/include/dpp_agent_channel.h b/src/net/drivers/net/ethernet/dinghai/en_np/agent/include/dpp_agent_channel.h new file mode 100644 index 0000000..5bc1759 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/agent/include/dpp_agent_channel.h @@ -0,0 +1,158 @@ +#ifndef DPP_AGENT_CHANNEL_H +#define DPP_AGENT_CHANNEL_H + +#include "zxic_common.h" +#include "dpp_dev.h" +#include "dpp_type_api.h" + +#define BUFFER_LEN_MAX (256) +#define REG_REPS_LEN (8) +#define CHANNEL_REPS_LEN (4) +#define NP_AGENT_ID (16) +#define MSG_REP_OFFSET (4) +#define MSG_REP_VALID (0Xff) +#define MSG_REP_LEN_OFFSET (1) +#define SCHE_RSP_LEN (2) +#define SCHE_REQ_VALID (0Xffff) +#define PROFILEID_REQ_VALID (0Xffff) +#define EPID_LEVEL (4) + +#pragma pack(1) + +typedef enum dpp_agent_msg_type +{ + DPP_REG_MSG = 0, + DPP_DTB_MSG, + DPP_TM_MSG, + DPP_PLCR_MSG, + DPP_TLB_MSG, + DPP_FLR_MSG, + DPP_RESET_MSG, + DPP_MSG_MAX +} MSG_TYPE_E; + +typedef enum dpp_agent_msg_oper +{ + DPP_WR = 0, + DPP_RD, + DPP_WR_RD_MAX +} MSG_OPER_E; + +typedef enum dpp_msg_dtb_oper +{ + QUEUE_REQUEST = 0, + QUEUE_RELEASE = 1, +} MSG_DTB_OPER_E; + +typedef enum dpp_msg_tm_oper +{ + SEID_REQUEST = 0, + SEID_RELEASE = 1, + SEID_QUERY = 2 +} MSG_TM_OPER_E; + +typedef enum dpp_msg_plcr_oper +{ + PROFILEID_REQUEST = 0, + PROFILEID_RELEASE = 1, +} MSG_PLCR_OPER_E; +typedef enum dpp_cosq_sche_type +{ + FQ_SCHE = 0, + FQ2_SCHE = 1, + FQ4_SCHE = 2, + FQ8_SCHE = 3, + SP_SCHE = 4, + WFQ_SCHE = 5, + WFQ2_SCHE = 6, + WFQ4_SCHE = 7, + WFQ8_SCHE = 8, + FLOW_SCHE = 9, + SCHE_TYPE = 10 +} DPP_COSQ_SCHE_TYPE; + +typedef enum dpp_agent_msg_csflag +{ + DPP_CS_ADDR_FLAG = 0, + DPP_CS_REGNO_FLAG, + DPP_CS_FLAG_MAX +} MSG_CSFLAG_E; + +typedef struct dpp_agent_channel_reg_msg +{ + ZXIC_UINT8 devId; + ZXIC_UINT8 type; + ZXIC_UINT8 subtype; + ZXIC_UINT8 oper; + ZXIC_UINT32 reg_no; + ZXIC_UINT32 addr; + ZXIC_UINT32 val_len; + ZXIC_UINT32 val[32]; +} DPP_AGENT_CHANNEL_REG_MSG_T; + +typedef struct dpp_agent_channel_dtb_msg +{ + ZXIC_UINT8 devId; + ZXIC_UINT8 type; + ZXIC_UINT8 oper; + ZXIC_UINT8 rsv; + ZXIC_UINT8 name[32]; + ZXIC_UINT32 vport; + ZXIC_UINT32 queue_id; +} DPP_AGENT_CHANNEL_DTB_MSG_T; +typedef struct dpp_agent_channel_tm_msg +{ + ZXIC_UINT8 devId; + ZXIC_UINT8 type; + ZXIC_UINT8 oper; + ZXIC_UINT8 num; + ZXIC_UINT32 port; + ZXIC_UINT32 vport; + ZXIC_UINT32 sche_level; + ZXIC_UINT32 sche_type; + ZXIC_UINT32 se_id; +} DPP_AGENT_CHANNEL_TM_MSG_T; +typedef struct dpp_agent_channel_plcr_msg +{ + ZXIC_UINT8 devId; + ZXIC_UINT8 type; + ZXIC_UINT8 oper; + ZXIC_UINT8 rsv; + ZXIC_UINT32 vport; + ZXIC_UINT32 car_type; + ZXIC_UINT32 profile_id; +} DPP_AGENT_CHANNEL_PLCR_MSG_T; +typedef struct dpp_agent_channel_msg +{ + ZXIC_UINT32 msg_len; + ZXIC_VOID *msg; +} DPP_AGENT_CHANNEL_MSG_T; + +#pragma pack() + +DPP_STATUS dpp_agent_channel_init(ZXIC_VOID); +DPP_STATUS dpp_agent_channel_exit(ZXIC_VOID); +DPP_STATUS dpp_agent_channel_sync_send(DPP_DEV_T *dev, DPP_AGENT_CHANNEL_MSG_T *pMsg, + ZXIC_UINT32 *pData, ZXIC_UINT32 rep_len); +DPP_STATUS dpp_agent_channel_reg_sync_send(DPP_DEV_T *dev, DPP_AGENT_CHANNEL_REG_MSG_T *pMsg, + ZXIC_UINT32 *pData, ZXIC_UINT32 rep_len); +DPP_STATUS dpp_agent_channel_reg_write(DPP_DEV_T *dev, ZXIC_UINT32 reg_type, ZXIC_UINT32 reg_no, + ZXIC_UINT32 reg_width, ZXIC_UINT32 addr, ZXIC_UINT32 *pData); +DPP_STATUS dpp_agent_channel_reg_read(DPP_DEV_T *dev, ZXIC_UINT32 reg_type, ZXIC_UINT32 reg_no, + ZXIC_UINT32 reg_width, ZXIC_UINT32 addr, ZXIC_UINT32 *pData); +DPP_STATUS dpp_agent_channel_dtb_sync_send(DPP_DEV_T *dev, DPP_AGENT_CHANNEL_DTB_MSG_T *pMsg, + ZXIC_UINT32 *pData, ZXIC_UINT32 rep_len); +DPP_STATUS dpp_agent_channel_dtb_queue_request(DPP_DEV_T *dev, ZXIC_CONST ZXIC_UINT8 *p_name, ZXIC_UINT32 vport_info, ZXIC_UINT32 *p_queue_id); +DPP_STATUS dpp_agent_channel_dtb_queue_release(DPP_DEV_T *dev, ZXIC_CONST ZXIC_UINT8 *p_name, ZXIC_UINT32 queue_id); + +DPP_STATUS dpp_agent_channel_tm_sync_send(DPP_DEV_T *dev, DPP_AGENT_CHANNEL_TM_MSG_T *pMsg, ZXIC_UINT32 *pData, ZXIC_UINT32 rep_len); +DPP_STATUS dpp_agent_channel_tm_seid_request(DPP_DEV_T *dev, ZXIC_UINT32 port, ZXIC_UINT32 vport, ZXIC_UINT32 sche_level, ZXIC_UINT32 sche_type, ZXIC_UINT32 num, ZXIC_UINT32 *p_se_id); +DPP_STATUS dpp_agent_channel_tm_seid_release(DPP_DEV_T *dev, ZXIC_UINT32 port, ZXIC_UINT32 vport, ZXIC_UINT32 sche_level, ZXIC_UINT32 sche_type, ZXIC_UINT32 num, ZXIC_UINT32 se_id); + +DPP_STATUS dpp_agent_channel_tm_base_node_get(DPP_DEV_T *dev, ZXIC_UINT32 port, ZXIC_UINT32 vport, ZXIC_UINT32 *p_se_id); + +DPP_STATUS dpp_agent_channel_plcr_sync_send(DPP_DEV_T *dev, DPP_AGENT_CHANNEL_PLCR_MSG_T *pMsg, ZXIC_UINT32 *pData, ZXIC_UINT32 rep_len); +DPP_STATUS dpp_agent_channel_plcr_profileid_request(DPP_DEV_T *dev, ZXIC_UINT32 vport, ZXIC_UINT32 car_type, ZXIC_UINT32 *p_profileid); +DPP_STATUS dpp_agent_channel_plcr_profileid_release(DPP_DEV_T *dev, ZXIC_UINT32 vport, ZXIC_UINT32 car_type, ZXIC_UINT32 profileid); + +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/agent/source/Kbuild.include b/src/net/drivers/net/ethernet/dinghai/en_np/agent/source/Kbuild.include new file mode 100644 index 0000000..557a672 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/agent/source/Kbuild.include @@ -0,0 +1,2 @@ +cur_dir := en_np/agent/source/ +src_files += $(addprefix $(cur_dir),$(notdir $(wildcard $(dinghai_root)/$(cur_dir)*.c))) \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/agent/source/dpp_agent_channel.c b/src/net/drivers/net/ethernet/dinghai/en_np/agent/source/dpp_agent_channel.c new file mode 100644 index 0000000..e280cb7 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/agent/source/dpp_agent_channel.c @@ -0,0 +1,476 @@ +#include "dpp_agent_channel.h" +#include "dh_cmd.h" +#include "dpp_dev.h" + +DPP_STATUS dpp_agent_channel_init() +{ + // zxdh_bar_msg_chan_init(); + return DPP_OK; +} + +DPP_STATUS dpp_agent_channel_exit() +{ + // zxdh_bar_msg_chan_remove(); + return DPP_OK; +} + +DPP_STATUS dpp_agent_channel_reg_sync_send(DPP_DEV_T *dev, DPP_AGENT_CHANNEL_REG_MSG_T *pMsg, + ZXIC_UINT32 *pData, ZXIC_UINT32 rep_len) +{ + DPP_STATUS ret = DPP_OK; + DPP_AGENT_CHANNEL_MSG_T agentMsg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_POINT(pMsg); + + agentMsg.msg = (ZXIC_VOID *)pMsg; + agentMsg.msg_len = sizeof(DPP_AGENT_CHANNEL_REG_MSG_T); + + ret = dpp_agent_channel_sync_send(dev, &agentMsg, pData, rep_len); + if (DPP_OK != ret) + { + ZXIC_COMM_TRACE_ERROR("%s: dpp_agent_channel_sync_send failed\n", __FUNCTION__); + return DPP_ERR; + } + + ret = *pData; + if (DPP_OK != ret) + { + ZXIC_COMM_TRACE_ERROR("%s: dpp_agent_channel_sync_send failed in buffer\n", __FUNCTION__); + return DPP_ERR; + } + + return DPP_OK; +} + +DPP_STATUS dpp_agent_channel_sync_send(DPP_DEV_T *dev, DPP_AGENT_CHANNEL_MSG_T *pMsg, + ZXIC_UINT32 *pData, ZXIC_UINT32 rep_len) +{ + DPP_STATUS ret = DPP_OK; + ZXIC_UINT8 *reply_ptr = NULL; + ZXIC_UINT16 reply_msg_len = 0; + ZXIC_UINT32 *recv_buffer = NULL; + + struct zxdh_pci_bar_msg in = {0}; + struct zxdh_msg_recviver_mem result = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_POINT(pMsg); + + recv_buffer = (ZXIC_UINT32 *)kmalloc(rep_len + CHANNEL_REPS_LEN, GFP_KERNEL); + ZXIC_COMM_CHECK_POINT(recv_buffer); + ZXIC_COMM_MEMSET(recv_buffer, 0, rep_len + CHANNEL_REPS_LEN); + + in.virt_addr = DEV_PCIE_MSG_ADDR(dev); + in.payload_addr = pMsg->msg; + in.payload_len = pMsg->msg_len; + in.src = MSG_CHAN_END_PF; + in.dst = MSG_CHAN_END_RISC; + in.event_id = NP_AGENT_ID; + in.src_pcieid = DEV_PCIE_ID(dev); + + result.buffer_len = rep_len + CHANNEL_REPS_LEN; + result.recv_buffer = recv_buffer; + + ZXIC_COMM_TRACE_DEBUG("%s: in.virt_addr 0x%llx.\n", __FUNCTION__, in.virt_addr); + + ret = zxdh_bar_chan_sync_msg_send(&in, &result); + ZXIC_COMM_CHECK_RC_MEMORY_FREE(ret, "zxdh_bar_chan_sync_msg_send", recv_buffer); + + reply_ptr = (ZXIC_UINT8 *)(result.recv_buffer); + if (MSG_REP_VALID == *reply_ptr) + { + reply_msg_len = *(ZXIC_UINT16 *)(reply_ptr + MSG_REP_LEN_OFFSET); + memcpy(pData, reply_ptr + MSG_REP_OFFSET, ((reply_msg_len > rep_len) ? rep_len : reply_msg_len)); + + kfree(recv_buffer); + return DPP_OK; + } + + kfree(recv_buffer); + + ZXIC_COMM_TRACE_ERROR("%s: zxdh_bar_chan_sync_msg_send failed.\n", __FUNCTION__); + + return DPP_ERR; +} + +DPP_STATUS dpp_agent_channel_reg_write(DPP_DEV_T *dev, ZXIC_UINT32 reg_type, ZXIC_UINT32 reg_no, + ZXIC_UINT32 reg_width, ZXIC_UINT32 addr, ZXIC_UINT32 *pData) +{ + DPP_STATUS ret = 0; + ZXIC_UINT32 resp_len = 0; + ZXIC_UINT8 *resp_buffer = NULL; + + DPP_AGENT_CHANNEL_REG_MSG_T msgcfg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_POINT(pData); + + msgcfg.devId = 0; + msgcfg.type = DPP_REG_MSG; + msgcfg.subtype = reg_type; + msgcfg.oper = DPP_WR; + msgcfg.reg_no = reg_no; + msgcfg.addr = addr; + msgcfg.val_len = reg_width / 4; + memcpy(msgcfg.val, pData, reg_width); + + resp_len = reg_width + 4; + resp_buffer = (ZXIC_UINT8 *)kmalloc(resp_len, GFP_KERNEL); + ZXIC_COMM_CHECK_POINT(resp_buffer); + + memset(resp_buffer, 0, resp_len); + + ret = dpp_agent_channel_reg_sync_send(dev, &msgcfg, (ZXIC_UINT32 *)resp_buffer, resp_len); + + if (DPP_OK != ret) + { + ZXIC_COMM_TRACE_ERROR("%s: dpp_agent_channel_reg_sync_send failed\n", __FUNCTION__); + kfree(resp_buffer); + return DPP_ERR; + } + + if (DPP_OK != *((ZXIC_UINT32 *)resp_buffer)) + { + ZXIC_COMM_TRACE_ERROR("%s: dpp_agent_channel_reg_sync_send failed in buffer\n", __FUNCTION__); + kfree(resp_buffer); + return DPP_ERR; + } + + memcpy(pData, resp_buffer + 4, reg_width); + + kfree(resp_buffer); + + return DPP_OK; +} + +DPP_STATUS dpp_agent_channel_reg_read(DPP_DEV_T *dev, ZXIC_UINT32 reg_type, ZXIC_UINT32 reg_no, ZXIC_UINT32 reg_width, ZXIC_UINT32 addr, + ZXIC_UINT32 *pData) +{ + DPP_STATUS ret = 0; + ZXIC_UINT32 resp_len = 0; + ZXIC_UINT8 *resp_buffer = NULL; + + DPP_AGENT_CHANNEL_REG_MSG_T msgcfg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_POINT(pData); + + msgcfg.devId = 0; + msgcfg.type = DPP_REG_MSG; + msgcfg.subtype = reg_type; + msgcfg.oper = DPP_RD; + msgcfg.reg_no = reg_no; + msgcfg.addr = addr; + msgcfg.val_len = reg_width / 4; + + resp_len = reg_width + 4; + resp_buffer = (ZXIC_UINT8 *)kmalloc(resp_len, GFP_KERNEL); + ZXIC_COMM_CHECK_POINT(resp_buffer); + + memset(resp_buffer, 0, resp_len); + + ret = dpp_agent_channel_reg_sync_send(dev, &msgcfg, (ZXIC_UINT32 *)resp_buffer, resp_len); + + if (DPP_OK != ret) + { + ZXIC_COMM_TRACE_ERROR("%s: dpp_agent_channel_reg_sync_send failed\n", __FUNCTION__); + kfree(resp_buffer); + return DPP_ERR; + } + + if (DPP_OK != *((ZXIC_UINT32 *)resp_buffer)) + { + ZXIC_COMM_TRACE_ERROR("%s: dpp_agent_channel_reg_sync_send failed in buffer\n", __FUNCTION__); + kfree(resp_buffer); + return DPP_ERR; + } + + memcpy(pData, resp_buffer + 4, reg_width); + + kfree(resp_buffer); + + return DPP_OK; +} + +DPP_STATUS dpp_agent_channel_dtb_sync_send(DPP_DEV_T *dev, DPP_AGENT_CHANNEL_DTB_MSG_T *pMsg, ZXIC_UINT32 *pData, ZXIC_UINT32 rep_len) +{ + DPP_STATUS ret = DPP_OK; + + DPP_AGENT_CHANNEL_MSG_T agentMsg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_POINT(pMsg); + ZXIC_COMM_CHECK_POINT(pData); + + agentMsg.msg = (ZXIC_VOID *)pMsg; + agentMsg.msg_len = sizeof(DPP_AGENT_CHANNEL_DTB_MSG_T); + + ret = dpp_agent_channel_sync_send(dev, &agentMsg, pData, rep_len); + if (DPP_OK != ret) + { + ZXIC_COMM_TRACE_ERROR("%s: dpp_agent_channel_sync_send failed\n", __FUNCTION__); + return DPP_ERR; + } + + return DPP_OK; +} + +DPP_STATUS dpp_agent_channel_dtb_queue_request(DPP_DEV_T *dev, ZXIC_CONST ZXIC_UINT8 *p_name, ZXIC_UINT32 vport_info, ZXIC_UINT32 *p_queue_id) +{ + DPP_STATUS ret = DPP_OK; + ZXIC_UINT32 rsp_buff[2] = {0}; + ZXIC_UINT32 msg_result = 0; + ZXIC_UINT32 queue_id = 0; + + DPP_AGENT_CHANNEL_DTB_MSG_T msgcfg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + + msgcfg.devId = DEV_ID(dev); + msgcfg.type = DPP_DTB_MSG; + msgcfg.oper = QUEUE_REQUEST; + ZXIC_COMM_MEMCPY(msgcfg.name, p_name, ZXIC_COMM_STRLEN(p_name)); + msgcfg.vport = vport_info; + + ZXIC_COMM_TRACE_INFO("%s: msgcfg.name = %s.\n", __FUNCTION__, msgcfg.name); + + ret = dpp_agent_channel_dtb_sync_send(dev, &msgcfg, rsp_buff, ZXIC_SIZEOF(rsp_buff)); + ZXIC_COMM_CHECK_RC_NO_ASSERT(ret, "dpp_agent_channel_dtb_sync_send"); + + msg_result = rsp_buff[0]; + queue_id = rsp_buff[1]; + + ZXIC_COMM_TRACE_INFO("%s: msg_result: %d.\n", __FUNCTION__, msg_result); + ZXIC_COMM_TRACE_INFO("%s: queue_id: %d.\n", __FUNCTION__, queue_id); + + *p_queue_id = queue_id; + + return msg_result; +} + +DPP_STATUS dpp_agent_channel_dtb_queue_release(DPP_DEV_T *dev, ZXIC_CONST ZXIC_UINT8 *p_name, ZXIC_UINT32 queue_id) +{ + DPP_STATUS ret = DPP_OK; + ZXIC_UINT32 msg_result = 0; + ZXIC_UINT32 rsp_buff[2] = {0}; + + DPP_AGENT_CHANNEL_DTB_MSG_T msgcfg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + + msgcfg.devId = DEV_ID(dev); + msgcfg.type = DPP_DTB_MSG; + msgcfg.oper = QUEUE_RELEASE; + msgcfg.queue_id = queue_id; + ZXIC_COMM_MEMCPY(msgcfg.name, p_name, ZXIC_COMM_STRLEN(p_name)); + + ZXIC_COMM_TRACE_INFO("%s: msgcfg.name = %s.\n", __FUNCTION__, msgcfg.name); + + ret = dpp_agent_channel_dtb_sync_send(dev, &msgcfg, rsp_buff, ZXIC_SIZEOF(rsp_buff)); + ZXIC_COMM_CHECK_RC_NO_ASSERT(ret, "dpp_agent_channel_dtb_sync_send"); + + msg_result = rsp_buff[0]; + ZXIC_COMM_TRACE_INFO("%s: msg_result: %d.\n", __FUNCTION__, msg_result); + + return msg_result; +} + +DPP_STATUS dpp_agent_channel_tm_sync_send(DPP_DEV_T *dev, DPP_AGENT_CHANNEL_TM_MSG_T *pMsg, ZXIC_UINT32 *pData, ZXIC_UINT32 rep_len) +{ + DPP_STATUS ret = DPP_OK; + DPP_AGENT_CHANNEL_MSG_T agentMsg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_POINT(pMsg); + ZXIC_COMM_CHECK_POINT(pData); + + agentMsg.msg = (ZXIC_VOID *)pMsg; + agentMsg.msg_len = sizeof(DPP_AGENT_CHANNEL_TM_MSG_T); + + ret = dpp_agent_channel_sync_send(dev, &agentMsg, pData, rep_len); + + if (DPP_OK != ret) + { + ZXIC_COMM_TRACE_ERROR("%s: dpp_agent_channel_sync_send failed\n", __FUNCTION__); + return DPP_ERR; + } + + // ret = *(ZXIC_UINT8 *)pData; + // if (DPP_OK != ret) + // { + // ZXIC_COMM_TRACE_ERROR("%s: dpp_agent_channel_tm_sync_send failed in buffer\n", __FUNCTION__); + // return DPP_ERR; + // } + + return DPP_OK; +} + +DPP_STATUS dpp_agent_channel_tm_seid_request(DPP_DEV_T *dev, ZXIC_UINT32 port, ZXIC_UINT32 vport, ZXIC_UINT32 sche_level, ZXIC_UINT32 sche_type, ZXIC_UINT32 num, ZXIC_UINT32 *p_se_id) +{ + DPP_STATUS ret = DPP_OK; + ZXIC_UINT32 resp_buffer[2] = {0}; + + DPP_AGENT_CHANNEL_TM_MSG_T msgcfg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_POINT(p_se_id); + + msgcfg.devId = 0; + msgcfg.type = DPP_TM_MSG; + msgcfg.oper = SEID_REQUEST; + msgcfg.port = port; + msgcfg.vport = vport; + msgcfg.sche_level = sche_level; + msgcfg.sche_type = sche_type; + msgcfg.num = num; + msgcfg.se_id = SCHE_REQ_VALID; + + if (FLOW_SCHE != sche_type) + { + msgcfg.num = 1; + } + + ret = dpp_agent_channel_tm_sync_send(dev, &msgcfg, resp_buffer, sizeof(resp_buffer)); + ZXIC_COMM_CHECK_RC_NO_ASSERT(ret, "dpp_agent_channel_tm_sync_send"); + + memcpy(p_se_id, resp_buffer, sizeof(ZXIC_UINT32)*SCHE_RSP_LEN); + + return ret; +} + +DPP_STATUS dpp_agent_channel_tm_seid_release(DPP_DEV_T *dev, ZXIC_UINT32 port, ZXIC_UINT32 vport, ZXIC_UINT32 sche_level, ZXIC_UINT32 sche_type, ZXIC_UINT32 num, ZXIC_UINT32 se_id) +{ + DPP_STATUS ret = DPP_OK; + ZXIC_UINT32 resp_buffer[2] = {0}; + + DPP_AGENT_CHANNEL_TM_MSG_T msgcfg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + + msgcfg.devId = 0; + msgcfg.type = DPP_TM_MSG; + msgcfg.oper = SEID_RELEASE; + msgcfg.port = port; + msgcfg.vport = vport; + msgcfg.sche_level = sche_level; + msgcfg.sche_type = sche_type; + msgcfg.num = num; + msgcfg.se_id = se_id; + + if (FLOW_SCHE != sche_type) + { + msgcfg.num = 1; + } + + ret = dpp_agent_channel_tm_sync_send(dev, &msgcfg, resp_buffer, sizeof(resp_buffer)); + ZXIC_COMM_CHECK_RC_NO_ASSERT(ret, "dpp_agent_channel_tm_sync_send"); + + ret = *(ZXIC_UINT8*)resp_buffer; + + return ret; +} + +DPP_STATUS dpp_agent_channel_tm_base_node_get(DPP_DEV_T *dev, ZXIC_UINT32 port, ZXIC_UINT32 vport, ZXIC_UINT32 *p_se_id) +{ + DPP_STATUS ret = DPP_OK; + ZXIC_UINT32 resp_buffer[2] = {0}; + + DPP_AGENT_CHANNEL_TM_MSG_T msgcfg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_POINT(p_se_id); + + msgcfg.devId = 0; + msgcfg.type = DPP_TM_MSG; + msgcfg.oper = SEID_QUERY; + msgcfg.port = port; + msgcfg.vport = vport; + msgcfg.sche_level = EPID_LEVEL; + msgcfg.sche_type = WFQ_SCHE; + msgcfg.num = 1; + msgcfg.se_id = SCHE_REQ_VALID; + + ret = dpp_agent_channel_tm_sync_send(dev, &msgcfg, resp_buffer, sizeof(resp_buffer)); + ZXIC_COMM_CHECK_RC_NO_ASSERT(ret, "dpp_agent_channel_tm_sync_send"); + + memcpy(p_se_id, resp_buffer, sizeof(ZXIC_UINT32)*SCHE_RSP_LEN); + + return ret; +} + +DPP_STATUS dpp_agent_channel_plcr_sync_send(DPP_DEV_T *dev, DPP_AGENT_CHANNEL_PLCR_MSG_T *pMsg, ZXIC_UINT32 *pData, ZXIC_UINT32 rep_len) +{ + DPP_STATUS ret = DPP_OK; + DPP_AGENT_CHANNEL_MSG_T agentMsg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_POINT(pMsg); + + agentMsg.msg = (ZXIC_VOID *)pMsg; + agentMsg.msg_len = sizeof(DPP_AGENT_CHANNEL_PLCR_MSG_T); + + ret = dpp_agent_channel_sync_send(dev, &agentMsg, pData, rep_len); + if (DPP_OK != ret) + { + ZXIC_COMM_TRACE_ERROR("%s: dpp_agent_channel_sync_send failed\n", __FUNCTION__); + return DPP_ERR; + } + + // ret = *(ZXIC_UINT8*)pData; + // if (DPP_OK != ret) + // { + // ZXIC_COMM_TRACE_ERROR("%s: dpp_agent_channel_sync_send failed in buffer\n", __FUNCTION__); + // return DPP_ERR; + // } + + return DPP_OK; +} + +DPP_STATUS dpp_agent_channel_plcr_profileid_request(DPP_DEV_T *dev, ZXIC_UINT32 vport, ZXIC_UINT32 car_type, ZXIC_UINT32 *p_profileid) +{ + DPP_STATUS ret = DPP_OK; + ZXIC_UINT32 resp_buffer[2] = {0}; + + DPP_AGENT_CHANNEL_PLCR_MSG_T msgcfg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_POINT(p_profileid); + + msgcfg.devId = 0; + msgcfg.type = DPP_PLCR_MSG; + msgcfg.oper = PROFILEID_REQUEST; + msgcfg.vport = vport; + msgcfg.car_type = car_type; + msgcfg.profile_id = PROFILEID_REQ_VALID; + + ret = dpp_agent_channel_plcr_sync_send(dev, &msgcfg, resp_buffer, sizeof(resp_buffer)); + ZXIC_COMM_CHECK_RC_NO_ASSERT(ret, "dpp_agent_channel_plcr_sync_send"); + + memcpy(p_profileid, resp_buffer, sizeof(ZXIC_UINT32)*SCHE_RSP_LEN); + + return ret; +} + +DPP_STATUS dpp_agent_channel_plcr_profileid_release(DPP_DEV_T *dev, ZXIC_UINT32 vport, ZXIC_UINT32 car_type, ZXIC_UINT32 profileid) +{ + DPP_STATUS ret = DPP_OK; + ZXIC_UINT32 resp_buffer[2] = {0}; + + DPP_AGENT_CHANNEL_PLCR_MSG_T msgcfg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + + msgcfg.devId = 0; + msgcfg.type = DPP_PLCR_MSG; + msgcfg.oper = PROFILEID_RELEASE; + msgcfg.vport = vport; + msgcfg.profile_id = profileid; + + ret = dpp_agent_channel_plcr_sync_send(dev, &msgcfg, resp_buffer, sizeof(resp_buffer)); + ZXIC_COMM_CHECK_RC_NO_ASSERT(ret, "dpp_agent_channel_plcr_sync_send"); + + ret = *(ZXIC_UINT8*)resp_buffer; + + return ret; +} diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/cmd/Kbuild.include b/src/net/drivers/net/ethernet/dinghai/en_np/cmd/Kbuild.include new file mode 100644 index 0000000..8b4d1a2 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/cmd/Kbuild.include @@ -0,0 +1,4 @@ +cur_dir := en_np/cmd/ +subdirs := source/ +src_files += +include $(foreach subdir, $(subdirs), $(dinghai_root)/$(cur_dir)$(subdir)/Kbuild.include) \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/cmd/include/dpp_cmd_init.h b/src/net/drivers/net/ethernet/dinghai/en_np/cmd/include/dpp_cmd_init.h new file mode 100644 index 0000000..1f3e6bf --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/cmd/include/dpp_cmd_init.h @@ -0,0 +1,16 @@ +//generate function cmdlist from symbol file + +#ifndef DPP_CMD_INIT_H +#define DPP_CMD_INIT_H + +#include "zxic_common.h" + +#define MSG_ID_MSG_DPP_CMD_SHELL ((ZXIC_UINT32)(100)) +typedef struct { + ZXIC_UINT32 msgId; + ZXIC_UINT8 command[256]; +} T_MSG_CMD_SHELL; + +ZXIC_UINT32 dpp_cmd_init(ZXIC_VOID); + +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/cmd/include/dpp_cmd_shell.h b/src/net/drivers/net/ethernet/dinghai/en_np/cmd/include/dpp_cmd_shell.h new file mode 100644 index 0000000..a12705a --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/cmd/include/dpp_cmd_shell.h @@ -0,0 +1,49 @@ +//generate function cmdlist from symbol file + +#ifndef DPP_CMD_SHELL_H +#define DPP_CMD_SHELL_H + +#include "zxic_common.h" +#include "dpp_dtb.h" +#include "dpp_tbl_diag.h" + +typedef struct +{ + ZXIC_CHAR *name; + ZXIC_CHAR *doc; + ZXIC_VOID *func; +} DPP_COMMAND; + +ZXIC_UINT32 dpp_cmd_help(ZXIC_VOID); + +DPP_COMMAND dpp_commands[] = { + { "dpp_cmd_help", "none", dpp_cmd_help}, + { "zxic_comm_set_print_level", "debug_level", zxic_comm_set_print_level }, + { "zxic_comm_set_print_en", "enable", zxic_comm_set_print_en }, + { "diag_dpp_vport_mac_add", "slot vport mac0...5", diag_dpp_vport_mac_add }, + { "diag_dpp_vport_mac_del", "slot vport mac0...5", diag_dpp_vport_mac_del }, + { "diag_dpp_vport_mac_prt", "slot vport", diag_dpp_vport_mac_prt }, + { "diag_dpp_vport_mc_mac_add", "slot vport mac0...5", diag_dpp_vport_mc_mac_add }, + { "diag_dpp_vport_mc_mac_del", "slot vport mac0...5", diag_dpp_vport_mc_mac_del }, + { "diag_dpp_vport_mc_mac_prt", "slot vport", diag_dpp_vport_mc_mac_prt }, + { "diag_dpp_vport_table_set", "slot vport attr value", diag_dpp_vport_table_set }, + { "diag_dpp_vport_table_prt", "slot vport", diag_dpp_vport_table_prt }, + { "diag_dpp_vport_panel_table_set", "slot vport panel_id attr value", diag_dpp_vport_panel_table_set }, + { "diag_dpp_vport_panel_table_prt", "slot vport panel_id", diag_dpp_vport_panel_table_prt }, + { "diag_dpp_vport_bc_table_set", "slot vport enable", diag_dpp_vport_bc_table_set }, + { "diag_dpp_vport_bc_table_prt", "slot vport", diag_dpp_vport_bc_table_prt }, + { "diag_dpp_vport_uc_promisc_table_set", "slot vport enable", diag_dpp_vport_uc_promisc_table_set }, + { "diag_dpp_vport_uc_promisc_table_prt", "slot vport", diag_dpp_vport_uc_promisc_table_prt }, + { "diag_dpp_vport_mc_promisc_table_set", "slot vport enable", diag_dpp_vport_mc_promisc_table_set }, + { "diag_dpp_vport_mc_promisc_table_prt", "slot vport", diag_dpp_vport_mc_promisc_table_prt }, + { "dpp_dtb_prt_disable", "none", dpp_dtb_prt_disable }, + { "dpp_dtb_prt_enable", "none", dpp_dtb_prt_enable }, + { "dpp_dtb_debug_fun_enable", "none", dpp_dtb_debug_fun_enable }, + { "dpp_dtb_debug_fun_disable", "none", dpp_dtb_debug_fun_disable }, + { "dpp_dtb_soft_perf_test_set", "value", dpp_dtb_soft_perf_test_set }, + { "dpp_dtb_hardware_perf_test_set", "value", dpp_dtb_hardware_perf_test_set }, + { "dpp_dtb_down_table_overtime_set", "times_s", dpp_dtb_down_table_overtime_set }, + { "dpp_dtb_dump_table_overtime_set", "times_s", dpp_dtb_dump_table_overtime_set }, +}; + +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/cmd/source/Kbuild.include b/src/net/drivers/net/ethernet/dinghai/en_np/cmd/source/Kbuild.include new file mode 100644 index 0000000..8101b6a --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/cmd/source/Kbuild.include @@ -0,0 +1,2 @@ +cur_dir := en_np/cmd/source/ +src_files += $(addprefix $(cur_dir),$(notdir $(wildcard $(dinghai_root)/$(cur_dir)*.c))) \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/cmd/source/dpp_cmd_init.c b/src/net/drivers/net/ethernet/dinghai/en_np/cmd/source/dpp_cmd_init.c new file mode 100644 index 0000000..4e9ac09 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/cmd/source/dpp_cmd_init.c @@ -0,0 +1,33 @@ +#include "zxic_common.h" +#include "dpp_netlink.h" +#include "dpp_cmd_init.h" + +extern ZXIC_CHAR* dpp_cmd_trim(ZXIC_CHAR* line); +extern ZXIC_UINT32 dpp_cmd_exec(ZXIC_CHAR* line); + +ZXIC_UINT32 dpp_cmd_msg_proc(ZXIC_VOID *msg_body, ZXIC_UINT32 msg_len, ZXIC_VOID **resp, ZXIC_UINT32 *reps_len) +{ + ZXIC_CHAR *line = NULL; + T_MSG_CMD_SHELL *msg = (T_MSG_CMD_SHELL*)(msg_body); + + ZXIC_COMM_CHECK_POINT(msg); + + line = dpp_cmd_trim(msg->command); + ZXIC_COMM_CHECK_POINT(line); + + if (*line) + { + ZXIC_COMM_PRINT("---------------------------------------------------\n"); + dpp_cmd_exec(line); + ZXIC_COMM_PRINT("---------------------------------------------------\n"); + } + + return DPP_OK; +} + +ZXIC_UINT32 dpp_cmd_init(ZXIC_VOID) +{ + dpp_netlink_regist_msg_proc_fun(MSG_ID_MSG_DPP_CMD_SHELL, dpp_cmd_msg_proc); + + return DPP_OK; +} diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/cmd/source/dpp_cmd_shell.c b/src/net/drivers/net/ethernet/dinghai/en_np/cmd/source/dpp_cmd_shell.c new file mode 100644 index 0000000..f96bf02 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/cmd/source/dpp_cmd_shell.c @@ -0,0 +1,296 @@ +#include "linux/string.h" +#include "zxic_common.h" +#include "dpp_cmd_shell.h" + +#ifndef whitespace +#define whitespace(c) (((c) == ' ') || ((c) == '\t')) +#endif + +#define DPP_CMD_ARG_NUM_MAX (15) + +ZXIC_UINT32 dpp_cmd_help(ZXIC_VOID) +{ + ZXIC_UINT32 i = 0; + ZXIC_UINT32 list_index = 0; + + list_index = sizeof(dpp_commands) / sizeof(dpp_commands[0]); + + for (i = 0; i < list_index; i++) + { + ZXIC_COMM_PRINT("%-40s | %s\n", dpp_commands[i].name, dpp_commands[i].doc); + } + + return DPP_OK; +} + +ZXIC_UINT32 dpp_cmd_atoi(ZXIC_CHAR* str) +{ + ZXIC_UINT32 n = 0; + ZXIC_SINT32 rc = 0; + + if(str == NULL) + { + return 0x0; + } + + if((str[0] == '0') && (str[1] == 'x')) + { + rc = sscanf(str, "0x%x", &n); + } + else if((str[0] == '0') && (str[1] == 'X')) + { + rc = sscanf(str, "0X%x", &n); + } + else + { + rc = sscanf(str, "%u", &n); + } + + if (rc < 0) + { + return 0; + } + + return n; +} + +DPP_COMMAND* dpp_cmd_find(ZXIC_CHAR* name) +{ + ZXIC_UINT32 i = 0; + ZXIC_UINT32 list_index = 0; + + list_index = sizeof(dpp_commands) / sizeof(dpp_commands[0]); + + for (i = 0; i < list_index; i++) + { + if (strcmp(name, dpp_commands[i].name) == 0) + { + return (&dpp_commands[i]); + } + } + + return ((DPP_COMMAND *)NULL); +} + +ZXIC_UINT32 dpp_cmd_strtok(ZXIC_CHAR *str, ZXIC_CHAR** arg_v, ZXIC_UINT32* arg_num) +{ + ZXIC_CHAR* p_tok = NULL; + ZXIC_CONST ZXIC_CHAR* delim = " ();\t"; + ZXIC_UINT32 i = 0; + + ZXIC_COMM_CHECK_POINT(str); + ZXIC_COMM_CHECK_POINT(arg_v); + ZXIC_COMM_CHECK_POINT(arg_num); + + ZXIC_COMM_MEMSET(arg_v, 0, DPP_CMD_ARG_NUM_MAX * sizeof(ZXIC_CHAR*)); + + p_tok = strsep(&str, delim); + ZXIC_COMM_CHECK_POINT(p_tok); + + arg_v[0] = p_tok; + + i = 1; + while (p_tok && (i < DPP_CMD_ARG_NUM_MAX)) + { + p_tok = strsep(&str, delim); + if (p_tok == NULL) + { + break; + } + arg_v[i++] = p_tok; + } + + *arg_num = i; + + return DPP_OK; +} + +ZXIC_CHAR* dpp_cmd_trim(ZXIC_CHAR* line) +{ + ZXIC_CHAR* s; + ZXIC_CHAR* t; + + ZXIC_COMM_CHECK_POINT_RETURN_NULL(line); + + for (s = line; whitespace(*s); s++) + ; + + if (*s == 0) + { + return (s); + } + + t = s + strlen(s) - 1; + while ((t > s) && whitespace(*t)) + t--; + *++t = '\0'; + + return s; +} + +ZXIC_UINT32 dpp_cmd_exec(ZXIC_CHAR* line) +{ + ZXIC_UINT32 i = 0; + ZXIC_UINT32 rc = DPP_OK; + ZXIC_UINT32 arg_num = 0; + ZXIC_UINT32 len = 0; + ZXIC_CHAR* word = 0; + ZXIC_CHAR* arg_v[DPP_CMD_ARG_NUM_MAX] = {0}; + DPP_COMMAND* command = NULL; + + ZXIC_UINT32 (*func0)(ZXIC_VOID); + ZXIC_UINT32 (*func1)(ZXIC_UINT32); + ZXIC_UINT32 (*func2)(ZXIC_UINT32, ZXIC_UINT32); + ZXIC_UINT32 (*func3)(ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32); + ZXIC_UINT32 (*func4)(ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32); + ZXIC_UINT32 (*func5)(ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32); + ZXIC_UINT32 (*func6)(ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32); + ZXIC_UINT32 (*func7)(ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32); + ZXIC_UINT32 (*func8)(ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32); + ZXIC_UINT32 (*func9)(ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32); + ZXIC_UINT32 (*func10)(ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32); + ZXIC_UINT32 (*func11)(ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, + ZXIC_UINT32); + ZXIC_UINT32 (*func12)(ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, + ZXIC_UINT32, ZXIC_UINT32); + + ZXIC_COMM_CHECK_POINT(line); + + len = ZXIC_COMM_STRLEN(line); + if(0 == len) + { + ZXIC_COMM_PRINT("%s: len is 0.\n", __FUNCTION__); + return DPP_OK; + } + + i = 0; + while(line[i % (len + 1)] && whitespace(line[i % (len + 1)])) + { + i++; + } + word = line + i; + + while(line[i % (len + 1)] && !whitespace(line[i % (len + 1)])) + { + i++; + } + + if(line[i % (len + 1)]) + { + line[i++] = '\0'; + } + + command = dpp_cmd_find(word); + ZXIC_COMM_CHECK_POINT(command); + ZXIC_COMM_CHECK_POINT(command->func); + + while(whitespace(line[i % (len + 1)])) + { + i++; + } + + word = line + i; + + rc = dpp_cmd_strtok(word, arg_v, &arg_num); + ZXIC_COMM_CHECK_RC(rc, "dpp_cmd_strtok"); + ZXIC_COMM_CHECK_INDEX(arg_num, 0, DPP_CMD_ARG_NUM_MAX); + + switch (arg_num) + { + case 0: + { + func0 = command->func; + ((*(func0)) ()); + break; + } + case 1: + { + func1 = command->func; + ((*(func1)) (dpp_cmd_atoi(arg_v[0]))); + break; + } + case 2: + { + func2 = command->func; + ((*(func2)) (dpp_cmd_atoi(arg_v[0]), dpp_cmd_atoi(arg_v[1]))); + break; + } + case 3: + { + func3 = command->func; + ((*(func3)) (dpp_cmd_atoi(arg_v[0]), dpp_cmd_atoi(arg_v[1]), dpp_cmd_atoi(arg_v[2]))); + break; + } + case 4: + { + func4 = command->func; + ((*(func4)) (dpp_cmd_atoi(arg_v[0]), dpp_cmd_atoi(arg_v[1]), dpp_cmd_atoi(arg_v[2]), dpp_cmd_atoi(arg_v[3]))); + break; + } + case 5: + { + func5 = command->func; + ((*(func5)) (dpp_cmd_atoi(arg_v[0]), dpp_cmd_atoi(arg_v[1]), dpp_cmd_atoi(arg_v[2]), dpp_cmd_atoi(arg_v[3]), dpp_cmd_atoi(arg_v[4]))); + break; + } + case 6: + { + func6 = command->func; + ((*(func6)) (dpp_cmd_atoi(arg_v[0]), dpp_cmd_atoi(arg_v[1]), dpp_cmd_atoi(arg_v[2]), dpp_cmd_atoi(arg_v[3]), dpp_cmd_atoi(arg_v[4]), + dpp_cmd_atoi(arg_v[5]))); + break; + } + case 7: + { + func7 = command->func; + ((*(func7)) (dpp_cmd_atoi(arg_v[0]), dpp_cmd_atoi(arg_v[1]), dpp_cmd_atoi(arg_v[2]), dpp_cmd_atoi(arg_v[3]), dpp_cmd_atoi(arg_v[4]), + dpp_cmd_atoi(arg_v[5]), dpp_cmd_atoi(arg_v[6]))); + break; + } + case 8: + { + func8 = command->func; + ((*(func8)) (dpp_cmd_atoi(arg_v[0]), dpp_cmd_atoi(arg_v[1]), dpp_cmd_atoi(arg_v[2]), dpp_cmd_atoi(arg_v[3]), dpp_cmd_atoi(arg_v[4]), + dpp_cmd_atoi(arg_v[5]), dpp_cmd_atoi(arg_v[6]), dpp_cmd_atoi(arg_v[7]))); + break; + } + case 9: + { + func9 = command->func; + ((*(func9)) (dpp_cmd_atoi(arg_v[0]), dpp_cmd_atoi(arg_v[1]), dpp_cmd_atoi(arg_v[2]), dpp_cmd_atoi(arg_v[3]), dpp_cmd_atoi(arg_v[4]), + dpp_cmd_atoi(arg_v[5]), dpp_cmd_atoi(arg_v[6]), dpp_cmd_atoi(arg_v[7]), dpp_cmd_atoi(arg_v[8]))); + break; + } + case 10: + { + func10 = command->func; + ((*(func10)) (dpp_cmd_atoi(arg_v[0]), dpp_cmd_atoi(arg_v[1]), dpp_cmd_atoi(arg_v[2]), dpp_cmd_atoi(arg_v[3]), dpp_cmd_atoi(arg_v[4]), + dpp_cmd_atoi(arg_v[5]), dpp_cmd_atoi(arg_v[6]), dpp_cmd_atoi(arg_v[7]), dpp_cmd_atoi(arg_v[8]), dpp_cmd_atoi(arg_v[9]))); + break; + } + case 11: + { + func11 = command->func; + ((*(func11)) (dpp_cmd_atoi(arg_v[0]), dpp_cmd_atoi(arg_v[1]), dpp_cmd_atoi(arg_v[2]), dpp_cmd_atoi(arg_v[3]), dpp_cmd_atoi(arg_v[4]), + dpp_cmd_atoi(arg_v[5]), dpp_cmd_atoi(arg_v[6]), dpp_cmd_atoi(arg_v[7]), dpp_cmd_atoi(arg_v[8]), dpp_cmd_atoi(arg_v[9]), + dpp_cmd_atoi(arg_v[10]))); + break; + } + case 12: + { + func12 = command->func; + ((*(func12)) (dpp_cmd_atoi(arg_v[0]), dpp_cmd_atoi(arg_v[1]), dpp_cmd_atoi(arg_v[2]), dpp_cmd_atoi(arg_v[3]), dpp_cmd_atoi(arg_v[4]), + dpp_cmd_atoi(arg_v[5]), dpp_cmd_atoi(arg_v[6]), dpp_cmd_atoi(arg_v[7]), dpp_cmd_atoi(arg_v[8]), dpp_cmd_atoi(arg_v[9]), + dpp_cmd_atoi(arg_v[10]),dpp_cmd_atoi(arg_v[11]))); + break; + } + default: + { + ZXIC_COMM_PRINT("%s: err [arg_num:%d] oversize.\n", __FUNCTION__, arg_num); + break; + } + + } + + return DPP_OK; +} diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/comm/Kbuild.include b/src/net/drivers/net/ethernet/dinghai/en_np/comm/Kbuild.include new file mode 100644 index 0000000..a4b84d0 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/comm/Kbuild.include @@ -0,0 +1,4 @@ +cur_dir := en_np/comm/ +subdirs := source/ +src_files += +include $(foreach subdir, $(subdirs), $(dinghai_root)/$(cur_dir)$(subdir)/Kbuild.include) \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_avl_tree.h b/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_avl_tree.h new file mode 100644 index 0000000..a4c829c --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_avl_tree.h @@ -0,0 +1,97 @@ +/********************************************************************* + * 版权所有 (C)2012, 深圳市中兴通讯股份有限公司。 + * + * 文件名称：zxic_avl_tree.h + * 文件标识： + * 内容摘要：// 本文件从pfe_index 移植过来 + * 其它说明：// 其它内容的说明 + * 当前版本： + * 作 者： + * 完成日期： + * + * 修 改: 蒋文明10124041 2012.04.26移植到NSE项目 + ********************************************************************/ +#ifndef __ZXIC_COMM_AVL_TREE_H__ +#define __ZXIC_COMM_AVL_TREE_H__ + + +/* Since the trees are balanced, their heignse will never be large. */ +#define avl_maxheight 41 /* why this? a small exercise */ +#define heightoftree(tree) ((tree) == NULL ? 0 : (tree)->avl_height) + +struct _ZXIC_AVL_CFG; +struct _ZXIC_AVL_NODE; + +#define ZXIC_LIST_ENTRY(ptr, type, member) \ + ((type *)((ZXIC_UINT8 *)(ptr)-(((unsigned long)(&((type *)64)->member)) - 64))) + +#define ZXIC_GET_AVL_KEY_ADDR(p_avl_cfg,key_index) \ + ((p_avl_cfg->p_key_base)+(p_avl_cfg->key_len*(key_index))); + +typedef ZXIC_SINT32 (*ZXIC_KEY_CMP_FUNC)(void *p_new_key, void *p_old_key, ZXIC_UINT32 key_len); + +typedef struct _ZXIC_AVL_NODE +{ + void *p_key; + //void *p_owner; /*the owner of this node*/ + ZXIC_UINT32 result; /*该节点的索引*/ + ZXIC_SINT32 avl_height; + struct _ZXIC_AVL_NODE *p_avl_left; + struct _ZXIC_AVL_NODE *p_avl_right; + D_NODE avl_node_list;/*the data is owner*/ +} ZXIC_AVL_NODE; + +typedef struct _ZXIC_AVL_CFG +{ + + ZXIC_AVL_NODE *p_root; + ZXIC_UINT32 avl_node_num; /*avl 中已使用节点的数目*/ + D_HEAD avl_node_list_head; /*avl 线索化节点的头节点*/ + ZXIC_UINT32 key_len; + ZXIC_UINT32 item_num; + ZXIC_KEY_CMP_FUNC avl_cmp_func; + ZXIC_UINT8 *p_key_base; + ZXIC_AVL_NODE *p_avl_node_base; + ZXIC_LISTSTACK_MANGER *p_avl_node_liststack; + + ZXIC_UINT32 is_dynamic; /*是否支持avl 的节点动态生成，1:支持;0:不支持*/ + ZXIC_UINT32 is_init; + +} ZXIC_AVL_CFG; + + + +ZXIC_RTN32 zxic_comm_avl_init(ZXIC_AVL_CFG* p_avl_cfg, /* avl配置*/ + ZXIC_UINT32 item_num, /* 插入键值的数目,如果为0表示动态申请节点*/ + ZXIC_UINT32 key_length, /* 插入键值的长度，以字节为单位*/ + ZXIC_KEY_CMP_FUNC avl_cmp_func); /* 键值比较函数,使用默认比较函数可以为NULL, + 如果按整型比较，需要用户提供比较函数*/ +ZXIC_RTN32 zxic_comm_avl_insert(ZXIC_AVL_CFG* p_avl_cfg, + void* p_new_key, + ZXIC_UINT32* p_index); + +ZXIC_RTN32 zxic_comm_avl_remove(ZXIC_AVL_CFG* p_avl_cfg, + void* p_delete_key, + void* p_out); + +ZXIC_RTN32 zxic_comm_avl_find(ZXIC_AVL_CFG* p_avl_cfg, + void* p_find_key, + void* p_out); + +ZXIC_RTN32 zxic_comm_avl_destroy(ZXIC_AVL_CFG* p_avl_cfg ); + + + + +ZXIC_UINT32 ic_comm_avl_get_node_num(ZXIC_AVL_CFG* p_avl_cfg); +ZXIC_UINT32 ic_comm_avl_is_none(ZXIC_AVL_CFG* p_avl_cfg); +ZXIC_RTN32 ic_comm_avl_get_1st_key(ZXIC_AVL_CFG* p_avl_cfg, void *p_key_out); +ZXIC_RTN32 ic_comm_avl_get_last_key(ZXIC_AVL_CFG* p_avl_cfg, void *p_key_out); +ZXIC_RTN32 ic_comm_avl_get_1st_node(ZXIC_AVL_CFG* p_avl_cfg, ZXIC_AVL_NODE** p_node_out); +ZXIC_RTN32 ic_comm_avl_get_last_node(ZXIC_AVL_CFG* p_avl_cfg, ZXIC_AVL_NODE** p_node_out); + +ZXIC_RTN32 zxic_comm_avl_show_info(ZXIC_AVL_CFG* p_avl_cfg); + +#endif/*__ZXIC_AVL_TREE_H__*/ + + diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_double_link.h b/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_double_link.h new file mode 100644 index 0000000..2b6afbd --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_double_link.h @@ -0,0 +1,109 @@ +/***************************************************************************** + * 版权所有 (C)2008-2010, 深圳市中兴通讯股份有限公司。 + * + * 文件名称： zxic_comm_double_link.h + * 文件标识： + * 内容摘要： 双链表实现 + * 其它说明： + * 当前版本： V1.00.10 + * 作 者： + * 完成日期： 2012年2月14日 + * 当前责任人-1：ChenWei188471 + * 当前责任人-2： + * 历史责任人-3: + * + * 修改记录： + * 修改日期： 版 本 号 修 改 人 修改内容 + 1 20120214 V1.00.10 ChenWei188471 创建 + 2 + *****************************************************************************/ + +#ifndef _ZXIC_COMM_DOUBLE_LINK_H +#define _ZXIC_COMM_DOUBLE_LINK_H +#define TEST_NUMBER (255) + + + + +/************************************************************************** + * double_link api * + **************************************************************************/ +typedef struct _d_node +{ + void *data; + struct _d_node *prev; + struct _d_node *next; +}D_NODE; + +typedef struct _d_head +{ + ZXIC_UINT32 used; + ZXIC_UINT32 maxnum; + D_NODE *p_next; + D_NODE *p_prev; +}D_HEAD; + +typedef ZXIC_SINT32 (*CMP_FUNC)(D_NODE* data1,D_NODE* data2,void* ); + +typedef ZXIC_RTN32 (*fun_free)(void *); + +ZXIC_RTN32 zxic_comm_double_link_insert_1st (D_NODE *newnode, D_HEAD *head); +ZXIC_RTN32 zxic_comm_double_link_insert_aft (D_NODE *newnode, D_NODE *oldnode,D_HEAD*head); +ZXIC_RTN32 zxic_comm_double_link_insert_pre (D_NODE *newnode, D_NODE *oldnode,D_HEAD*head); +ZXIC_RTN32 zxic_comm_double_link_insert_last(D_NODE *newnode, D_HEAD *head); +ZXIC_RTN32 zxic_comm_double_link_merge_list (D_HEAD *d_list, D_HEAD *s_list); + +ZXIC_RTN32 zxic_comm_double_link_insert_sort(D_NODE *newnode, D_HEAD *head, CMP_FUNC fuc,void*); + +ZXIC_RTN32 zxic_comm_double_link_search (D_NODE *data, D_HEAD *head); +ZXIC_RTN32 zxic_comm_double_link_del (D_NODE *data, D_HEAD *head); +ZXIC_RTN32 zxic_comm_double_link_init (ZXIC_UINT32 elmemtnum, D_HEAD *head); +ZXIC_RTN32 zxic_comm_double_link_insert_merge(D_NODE *p_newnode,D_HEAD *p_head,ZXIC_UINT32 is_head); + +/*fun指向的是释放dnode指向的空间，如果没有，可以传NULL*/ +ZXIC_RTN32 zxic_comm_dlink_release(D_HEAD *p_head,fun_free fun); +ZXIC_SINT32 zxic_comm_double_link_default_cmp_fuc(D_NODE* p_data1,D_NODE* p_data2,void*); + +ZXIC_RTN32 zxic_comm_double_link_del_pos(D_HEAD *p_head,void* cmp_data,fun_free fun); +ZXIC_RTN32 zxic_comm_double_link_insert_cmp(D_HEAD *p_head, void* cmp_data, ZXIC_UINT32 *is_same); + +#define INIT_D_NODE(ptr,pdata) \ + do{\ + (ptr)->data = pdata;\ + (ptr)->prev = NULL;\ + (ptr)->next = NULL;\ + }while(0) + + +/*add by lius +将0转 换成(TYPE*)，结构以内存空间首地址0作为起始地址，则成员地址为偏移地址；*/ +#define MEM_OFF(type,member) \ + (ZXIC_COMM_PTR_TO_VAL(&(((type*)0)->member))) + +/*根据当前双链表的指针，找到本节点的指针*/ +#define STRUCT_ENTRY_POINT(ptr, type, member) \ + ((type *)(ZXIC_COMM_PTR_TO_VAL(ptr)-MEM_OFF(type,member))) + +/* 不依据0，找结构体首地址 */ +#define MEM_OFF_NOT_NULL(type,member) \ + (ZXIC_COMM_PTR_TO_VAL(&(((type*)4)->member)) - ZXIC_COMM_PTR_TO_VAL(((type*)4))) + +/* 为了消除原STRUCT_ENTRY_POINT中“直接解引用 NULL”的coverity */ +#define GET_STRUCT_ENTRY_POINT(ptr, type, member) \ + ((type *)(ZXIC_COMM_PTR_TO_VAL(ptr)-MEM_OFF_NOT_NULL(type,member))) + +#define DLINK_IS_FULL(p_dlink) \ + ((p_dlink)->used == (p_dlink)->maxnum) + + +ZXIC_RTN32 zxic_comm_double_link_sort (D_HEAD *p_head, CMP_FUNC cmp_fuc); +ZXIC_RTN32 zxic_comm_double_link_swap (D_NODE *p_pre, D_NODE *p_next); +ZXIC_RTN32 zxic_comm_double_link_test (ZXIC_VOID ); +ZXIC_RTN32 zxic_comm_double_link_print (D_HEAD *p_head); +ZXIC_RTN32 zxic_comm_double_link_del_by_data(D_HEAD *p_head,ZXIC_VOID* cmp_data,fun_free fun); +ZXIC_RTN32 zxic_comm_double_link_del_by_info(D_HEAD *p_head, void* cmp_data, CMP_FUNC cmp_fuc, ZXIC_UINT32 *p_deled_num); + + + +#endif + diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_doublelink_index.h b/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_doublelink_index.h new file mode 100644 index 0000000..c966195 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_doublelink_index.h @@ -0,0 +1,166 @@ +/***************************************************************************** + * 版权所有 (C)2008-2010, 深圳市中兴通讯股份有限公司。 + * + * 文件名称：zxic_doublelink_index.h + * 文件标识： + * 内容摘要：zxic_doublelink_index.c 的头文件， 这里定义了.c文件需要用到的数据结构， + 并且申明了提供外部模块调用的接口函数 + * 其它说明： 其它内容的说明 + * 当前版本： + * 作 者：HuangHe(170389) Z T E 中兴 + * 完成日期：2009-02-16 + * 当前责任人-1：HuangHe Z T E 中兴 + * 当前责任人-2： + * 历史责任人-3: + * + * 修改记录： + * 修改日期： 版 本 号 修 改 人 修改内容 + 1 yyyymmdd V*.* 姓名工号 + 2 + *****************************************************************************/ +#ifndef __ZXIC_COMM_DOUBLELINK_INDEX_H__ +#define __ZXIC_COMM_DOUBLELINK_INDEX_H__ + +/************************** include head files *****************************/ + +/************************** type define *****************************/ +#define DOUBLELINK_CHECKSUM ((ZXIC_UINT32)(0xAABBBAAB)) + + +/************************** const variables **************************/ +#define DOUBLELINK_INVALID_PREVIOUS (0x0) +#define DOUBLELINK_INVALID_NEXT (0x0) +#define DOUBLELINK_USED_FLAG ((ZXIC_UINT32)(0xffffffff)) +#define DOUBLELINK_LASTEST_ELEMENT ((ZXIC_UINT32)(0x0ffffffe)) + +/************************************************************************** + * double_link_index api * + **************************************************************************/ + +/** + * NAME: DLINK_NODE + * + * DESCRIPTION: Structure Node the information of the doublelink. + **/ +typedef struct +{ + ZXIC_UINT32 dw_next_node; /*后一个节点*/ + ZXIC_UINT32 dw_pre_node; /*前一个节点*/ + ZXIC_UINT32 dw_self_node; /*当前一个节点*/ + +}DLINK_NODE; + +/** + * NAME: FTMCOMM_DOUBLELINK_MANGER + * + * DESCRIPTION: Structure containing the information required by the + * implementation of the doublelink. +**/ + +typedef struct _FtmComm_DoubleLink_Manager +{ + /* + * p_array is a pointer to the array of elements used to track which + * indexes have been allocated. + */ + DLINK_NODE *p_array; + + /* + * numElements is the number of indexes managed by this instance of the + * index_pool. + */ + ZXIC_UINT32 capacity; + + /* + * currFreeElement stores a free element for where to alloc next free element. + * This helps prevent looping over a large sections of the array each time + * a new index is allocated. + */ + ZXIC_UINT32 free_num; + + ZXIC_UINT32 used_num; + + ZXIC_UINT32 first_used; + + ZXIC_UINT32 last_used; + + ZXIC_UINT32 first_free; + + ZXIC_UINT32 last_free; + /* + * offset is an adjustment value, allowing the caller to prevent certain + * indexes from being allocated. This value is only meaningful to the + * client, and does not affect how the indexes are managed within the + * doublelink. + */ + ZXIC_UINT32 offset; + + ZXIC_UINT32 check_sum; /*用来检查传入的地址是否是双链表管理结构地址*/ + +}ZXIC_DOUBLELINK_MANGER; + + +ZXIC_RTN32 zxic_comm_dlink_manage_create(ZXIC_UINT32 dw_element_num, + ZXIC_UINT32 dw_offset, + ZXIC_DOUBLELINK_MANGER **p_dlink); + + +ZXIC_RTN32 zxic_comm_dlink_alloc (ZXIC_DOUBLELINK_MANGER *p_dlink, + ZXIC_UINT32 *index); + + +ZXIC_RTN32 zxic_comm_dlink_free (ZXIC_DOUBLELINK_MANGER *p_dlink, + ZXIC_UINT32 index); + + +ZXIC_RTN32 zxic_comm_dlink_get_next (ZXIC_DOUBLELINK_MANGER *p_dlink, + ZXIC_UINT32 dw_index, + ZXIC_UINT32 *p_next_index); + + +ZXIC_RTN32 zxic_comm_dlink_manage_clear (ZXIC_DOUBLELINK_MANGER *p_dlink); + + +ZXIC_RTN32 zxic_comm_dlink_get_previous (ZXIC_DOUBLELINK_MANGER *p_dlink, + ZXIC_UINT32 dw_index, + ZXIC_UINT32 *p_pre_index); + +ZXIC_RTN32 zxic_comm_dlink_is_used (ZXIC_DOUBLELINK_MANGER *p_dlink, + ZXIC_UINT32 dw_index, + ZXIC_UINT8 *p_is_used); + + +ZXIC_RTN32 zxic_comm_dlink_first_free (ZXIC_DOUBLELINK_MANGER *p_dlink, + ZXIC_UINT32 *p_index); + + +ZXIC_RTN32 zxic_comm_dlink_first_used (ZXIC_DOUBLELINK_MANGER *p_dlink, + ZXIC_UINT32 *p_index); + + + +ZXIC_RTN32 zxic_comm_dlink_manage_reset (ZXIC_DOUBLELINK_MANGER *p_dlink); + +ZXIC_RTN32 zxic_comm_dlink_get_curr_info (ZXIC_DOUBLELINK_MANGER *p_dlink, + ZXIC_UINT32 *p_free_num, + ZXIC_UINT32 *p_curr_free_index); + +ZXIC_RTN32 zxic_comm_dlink_last_used (ZXIC_DOUBLELINK_MANGER *p_dlink, + ZXIC_UINT32 *p_index); + +ZXIC_RTN32 zxic_comm_dlink_used_num (ZXIC_DOUBLELINK_MANGER *p_dlink, + ZXIC_UINT32 *p_num); + +ZXIC_RTN32 zxic_comm_dlink_show_node_info (ZXIC_DOUBLELINK_MANGER *p_dlink, + ZXIC_UINT32 dw_node_index); + +ZXIC_RTN32 zxic_comm_dlink_show_current_status(ZXIC_DOUBLELINK_MANGER *p_dlink); + + +ZXIC_RTN32 zxic_comm_dlink_self_test(ZXIC_VOID); + + + +#endif + + diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_index_ctrl.h b/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_index_ctrl.h new file mode 100644 index 0000000..9b887af --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_index_ctrl.h @@ -0,0 +1,77 @@ +/********************************************************************* +* 版权所有 (C)2001, 深圳市中兴通讯股份有限公司。 +* +* 文件名称： +* 文件标识： +* 内容摘要: +* 其它说明: +* +* +* 当前版本： +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT : 100% +* 作 者： +* 完成日期：2010-10-29 +********************************************************************/ +#ifndef _ZXIC_COMM_INDEX_CONTROLLER_H_ +#define _ZXIC_COMM_INDEX_CONTROLLER_H_ + +//#include "zxic_common.h" +//#include "zxic_comm_rb_tree.h" +//#include "zxic_comm_double_link.h" + + +#define ZXIC_INDEX_EXPAND_MAX_NUM (900) +#define INDEX_KEY_LENGTH (4) +typedef struct zxic_index_ctrl_cfg +{ + + ZXIC_UINT32 index_cursor_current ; + ZXIC_UINT32 index_cursor_last ; + ZXIC_UINT32 index_cursor_max_cur ; + ZXIC_UINT32 index_ctrl_is_init ; + ZXIC_UINT32* p_index_buf ; + + ZXIC_RB_CFG index_ctrl_rb_tree ; + ZXIC_RB_CFG rcd_ctrl_rb_tree ; + + D_HEAD *p_index_ctrl_link ; +}ZXIC_INDEX_CTRL_CFG; + +typedef struct _zxic_index_api_params +{ + ZXIC_UINT32 zxic_expand_num ; /*the expand num of this item */ + ZXIC_UINT32 zxic_opera_mode ; /*0:add;1:del;2:sch */ + ZXIC_UINT32 zxic_rsp_isexit ; /*the rsp of whether is exit */ + ZXIC_UINT32 *p_zxic_out_index ; /*the address of response */ + ZXIC_VOID *p_zxic_data ; /*the data of inserting in tcam*/ + +} ZXIC_INDEX_API_PARAMS; + +typedef enum functionNo /* 接口提供的表操作类型 */ +{ + INDEX_CTRL_ADD, + INDEX_CTRL_ADD_FROM_LAST, + INDEX_CTRL_DEL, + INDEX_CTRL_SEARCH, + INDEX_CTRL_UNDEFINED +}FUNCTION_NO; + + + + +ZXIC_RTN32 zxic_comm_indexctrl_get_free_index(ZXIC_INDEX_CTRL_CFG *p_table_info,ZXIC_UINT32 func_type,ZXIC_UINT32 *p_free_index_num); +ZXIC_RTN32 zxic_comm_indexctrl_add_from_last(ZXIC_INDEX_CTRL_CFG *p_table_info,ZXIC_VOID *data,ZXIC_UINT32 expand_num,ZXIC_UINT32 *out_index); +ZXIC_RTN32 zxic_comm_indexctrl_sch(ZXIC_INDEX_CTRL_CFG *p_table_info,ZXIC_VOID *data,ZXIC_UINT32 *p_is_exit,ZXIC_UINT32 *out_index); +ZXIC_RTN32 zxic_comm_indexctrl_extcommand(ZXIC_INDEX_API_PARAMS *p_zxic_api_params,ZXIC_INDEX_CTRL_CFG *p_table_info) ; +ZXIC_RTN32 zxic_comm_indexctrl_add(ZXIC_INDEX_CTRL_CFG *p_table_info,ZXIC_VOID *data,ZXIC_UINT32 expand_num,ZXIC_UINT32 *out_index); +ZXIC_RTN32 zxic_comm_indexctrl_init(ZXIC_INDEX_CTRL_CFG *p_table_info,ZXIC_UINT32 index_max_num,ZXIC_UINT32 table_key_len); +ZXIC_RTN32 zxic_comm_indexctrl_getindex_from_last(ZXIC_INDEX_CTRL_CFG *p_table_info,ZXIC_UINT32 *p_index_out); +ZXIC_RTN32 zxic_comm_indexctrl_del(ZXIC_INDEX_CTRL_CFG *p_table_info,ZXIC_VOID *data,ZXIC_UINT32 *out_index); +ZXIC_RTN32 zxic_comm_indexctrl_getindex(ZXIC_INDEX_CTRL_CFG *p_table_info,ZXIC_UINT32 *p_index_out); +ZXIC_SINT32 zxic_comm_indexctrl_cmp_key(ZXIC_VOID *new_key, ZXIC_VOID *old_key,ZXIC_UINT32 key_len); + + +#endif + + diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_index_fill.h b/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_index_fill.h new file mode 100644 index 0000000..3dcf520 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_index_fill.h @@ -0,0 +1,69 @@ +/***************************************************************************** + * 版权所有 (C)2001-2015, 深圳市中兴通讯股份有限公司。 + * + * 文件名称： zxic_index_fill.h + * 文件标识： + * 内容摘要： 索引空位填充源代码头文件 + * 其它说明： + * 当前版本： + * 作 者： ChenWei10088471 + * 完成日期： + * 当前责任人-1： + * 当前责任人-2： + * + * DEPARTMENT : ASIC_FPGA_R&D_Dept + * MANUAL_PERCENT : 100% + *****************************************************************************/ + +#ifndef _ZXIC_COMM_INDEX_FILL_H +#define _ZXIC_COMM_INDEX_FILL_H + + +typedef ZXIC_RTN32 (*INDEXFILL_SWAP_FUNC)(ZXIC_UINT32 old_index,ZXIC_UINT32 new_index,ZXIC_VOID *p_cfg); + + +typedef struct +{ + ZXIC_RB_TN rb_node; + ZXIC_UINT32 position; + ZXIC_UINT32 usednum; +}INDEX_FILL_NODE; + +typedef struct +{ + ZXIC_RB_CFG fill_rb; + ZXIC_UINT32 index_num; + INDEX_FILL_NODE *fill_node; + INDEXFILL_SWAP_FUNC swap_fun; + ZXIC_UINT32 total_used; +}INDEX_FILL_CFG; + +ZXIC_RTN32 ic_comm_node_data_free(void *p_data); + + +ZXIC_RTN32 zxic_comm_indexfill_init(INDEX_FILL_CFG *p_fill_cfg, + ZXIC_UINT32 index_num, + ZXIC_KEY_CMP_FUNC p_cmp_fun, + INDEXFILL_SWAP_FUNC p_swap_fun, + ZXIC_UINT32 key_len); + +ZXIC_RTN32 zxic_comm_indexfill_free(INDEX_FILL_CFG *p_fill_cfg, + ZXIC_UINT32 free_index, + ZXIC_VOID* p_rb_key, + ZXIC_UINT32 *out_index); + +ZXIC_RTN32 zxic_comm_indexfill_destroy(INDEX_FILL_CFG *p_fill_cfg); + +ZXIC_RTN32 zxic_comm_indexfill_store(INDEX_FILL_CFG *p_fill_cfg, ZXIC_UINT32 *p_size, ZXIC_UINT8 **p_data_buff); + +ZXIC_RTN32 zxic_comm_indexfill_show_all_position(INDEX_FILL_CFG *p_fill_cfg); +ZXIC_RTN32 zxic_comm_indexfill_clear(INDEX_FILL_CFG *p_fill_cfg); + +#define ICMINF_GET_NODE_LASTPOS(p_inf_node) \ + ((p_inf_node)->position + (p_inf_node)->usednum -1) + +#define ICMINF_GET_NODE_FSTPOS(p_inf_node) \ + ((p_inf_node)->position) + +#endif + diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_index_fill_type.h b/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_index_fill_type.h new file mode 100644 index 0000000..ae4f64a --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_index_fill_type.h @@ -0,0 +1,96 @@ +/***************************************************************************** + * 版权所有 (C)2001-2015, 深圳市中兴通讯股份有限公司。 + * + * 文件名称： zxic_index_fill.h + * 文件标识： + * 内容摘要： 索引空位填充源代码头文件 + * 其它说明： + * 当前版本： + * 作 者： ChenWei10088471 + * 完成日期： + * 当前责任人-1： + * 当前责任人-2： + * + * DEPARTMENT : ASIC_FPGA_R&D_Dept + * MANUAL_PERCENT : 100% + *****************************************************************************/ + +#ifndef _ZXIC_COMM_INDEX_FILL_TYPE_H +#define _ZXIC_COMM_INDEX_FILL_TYPE_H + +typedef ZXIC_RTN32 (*INDEXFILL_TYPE_SWAP_FUNC)(ZXIC_UINT32 old_index,ZXIC_UINT32 new_index,ZXIC_VOID *p_cfg); + +typedef struct +{ + ZXIC_UINT32 is_used; /* 0空闲，1已分配 */ + ZXIC_UINT32 prio; +}INDEX_FILL_TYPE_INDEX_STATUS; /* is_used==0时，不关心prio */ + +typedef struct +{ + ZXIC_RB_TN prio_rb_node; /* prio_rb_tree中的节点 */ + ZXIC_RB_CFG idx_rb_cfg; /* 以index为key，详细记录每个prio的每个index信息 */ + ZXIC_UINT32 prio; /* prio值*/ +}INDEX_FILL_TYPE_PRIO_NODE; + +typedef struct { + ZXIC_UINT32 prio; +} SSP4_INDEX_FILL_TYPE_PRIO_RB_KEY; /* prio红黑树的key */ + +typedef struct +{ + ZXIC_RB_CFG prio_rb; /* 每type的prio红黑树，以prio为key */ + D_HEAD mv_list_head; /* 同type的移位链表 */ + ZXIC_VOID *p_cfg; /* type相关的其他参数定义，外部自行定义 */ +}INDEX_FILL_TYPE_MNG_CFG; + +typedef struct +{ + ZXIC_UINT32 index_num; /* 本池的索引数量 */ + ZXIC_UINT32 total_used; /* 本池已使用的索引数量 */ + ZXIC_UINT32 prio_max; /* 最大优先级范围 */ + ZXIC_UINT32 global_max_num; /* 全局最大数量*/ + INDEX_FILL_TYPE_INDEX_STATUS *p_idx_status; /* 全局索引池状态位记录数组指针 */ + INDEXFILL_TYPE_SWAP_FUNC swap_fun; /* 向前或者向后挤压时的移位操作函数 */ +}INDEX_FILL_TYPE_INDEX_POOL_CFG; /* 多种type共享的索引池 */ + + + +ZXIC_UINT32 zxic_comm_indexfill_type_idx_status_get(INDEX_FILL_TYPE_INDEX_STATUS *index_status, + ZXIC_UINT32 index, + ZXIC_UINT32 *used_status_flag, + ZXIC_UINT32 *used_status_prio); + + +ZXIC_UINT32 zxic_comm_indexfill_type_idx_status_set(INDEX_FILL_TYPE_INDEX_STATUS *index_status, + ZXIC_UINT32 index, + ZXIC_UINT32 prio, + ZXIC_UINT32 used_flag); + +ZXIC_RTN32 zxic_comm_indexfill_type_init(INDEX_FILL_TYPE_INDEX_POOL_CFG *p_fill_type_index_pool_cfg, + ZXIC_UINT32 index_num, + ZXIC_UINT32 prio_max, + ZXIC_UINT32 global_max_num, + INDEXFILL_TYPE_SWAP_FUNC p_swap_fun); + +ZXIC_RTN32 zxic_comm_indexfill_type_rb_init(INDEX_FILL_TYPE_MNG_CFG *p_fill_type_mng_cfg); + +/* 多张type共享的索引记录 */ +/* 每种type，一个prio红黑树管理结构，一个prio+index红黑树管理结构 */ +ZXIC_RTN32 zxic_comm_indexfill_type_alloc(INDEX_FILL_TYPE_INDEX_POOL_CFG *p_fill_type_index_pool_cfg, + INDEX_FILL_TYPE_MNG_CFG *p_fill_type_mng_cfg, + ZXIC_UINT32 prio, + ZXIC_UINT32 *out_index); +/* 多张type共享的索引记录 */ +/* 每种type，一个prio红黑树管理结构，一个prio+index红黑树管理结构 */ +ZXIC_RTN32 zxic_comm_indexfill_type_free(INDEX_FILL_TYPE_INDEX_POOL_CFG *p_fill_type_index_pool_cfg, + INDEX_FILL_TYPE_MNG_CFG *p_fill_type_mng_cfg, + ZXIC_UINT32 free_index, + ZXIC_UINT32 *out_index); + +ZXIC_RTN32 zxic_comm_indexfill_type_show_all_position(INDEX_FILL_TYPE_INDEX_POOL_CFG *p_fill_type_index_pool_cfg, + INDEX_FILL_TYPE_MNG_CFG *p_fill_type_mng_cfg); + + +#endif + diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_index_reserve.h b/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_index_reserve.h new file mode 100644 index 0000000..3a6e8ac --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_index_reserve.h @@ -0,0 +1,78 @@ +/***************************************************************************** + * 版权所有 (C)2001-2015, 深圳市中兴通讯股份有限公司。 + * + * 文件名称： zxic_index_reserve.h + * 文件标识： + * 内容摘要： 索引预留算法源代码头文件 + * 其它说明： + * 当前版本： + * 作 者： ChenWei10088471 + * 完成日期： + * 当前责任人-1： + * 当前责任人-2： + * + * DEPARTMENT : ASIC_FPGA_R&D_Dept + * MANUAL_PERCENT : 100% + *****************************************************************************/ +#ifndef _ZXIC_COMM_INDEX_RESERVE_H +#define _ZXIC_COMM_INDEX_RESERVE_H + +#define CMP_MODE_LOW (0) +#define CMP_MODE_HIGH (1) +typedef ZXIC_UINT32 (*SWAP_FUNC)(ZXIC_UINT32 old_index,ZXIC_UINT32 new_index); +typedef ZXIC_UINT32 (*LOCAL_SWAP_FUNC)(ZXIC_VOID *p_cfg,ZXIC_UINT32 old_index,ZXIC_UINT32 new_index); + +typedef struct +{ + ZXIC_UINT32 head_curr; + ZXIC_UINT32 tail_curr; +}INDEX_CURR; + +typedef struct +{ + ZXIC_UINT32 old_handle; + ZXIC_UINT32 new_handle; +}INR_SWAP_NODE; + +typedef struct _index_res_cfg +{ + ZXIC_UINT32 total_num; + ZXIC_UINT32 space_num; + ZXIC_UINT32* index_prop; + ZXIC_RB_CFG* index_usedrb; + ZXIC_RB_CFG* index_freerb; + ZXIC_RB_TN* index_node; + SWAP_FUNC swap_fun; + LOCAL_SWAP_FUNC local_fun; + INDEX_CURR* index_curr; + D_HEAD swap_list; + ZXIC_UINT32 total_used; + ZXIC_UINT32 is_init; + ZXIC_UINT32 indexres_id; +}INDEX_RES_CFG; +ZXIC_VOID zxic_comm_rb_tn_relation_clear(ZXIC_RB_TN *rb_tn_node); + +ZXIC_RTN32 zxic_comm_indexres_init(INDEX_RES_CFG *p_indexres_cfg, /*配置句柄*/ + ZXIC_UINT32 arg_total_num, /*索引总数*/ + ZXIC_UINT32 arg_space_num, /*空间总数*/ + ZXIC_UINT32* arg_index_prop, /*空间大小，若用户提供，则按用户提供的进行空间分配，否则平均分配所有空间*/ + SWAP_FUNC p_swap_fun, + LOCAL_SWAP_FUNC local_fun); /*重排函数，注册则调用，否则不调*/ + +ZXIC_RTN32 zxic_comm_indexres_alloc(INDEX_RES_CFG *p_indexres_cfg, /*配置句柄*/ + ZXIC_UINT32 space_val, /*空间序列*/ + ZXIC_UINT32 *out_index); /*出参，分配的索引*/ + +ZXIC_RTN32 zxic_comm_indexres_free(INDEX_RES_CFG *p_indexres_cfg, + ZXIC_UINT32 space_val, + ZXIC_UINT32 free_index); + +ZXIC_RTN32 zxic_comm_indexres_destory(INDEX_RES_CFG *p_indexres_cfg); + +ZXIC_RTN32 zxic_comm_indexres_reset(INDEX_RES_CFG *p_indexres_cfg); + +ZXIC_RTN32 zxic_comm_indexres_showinfo(INDEX_RES_CFG *p_indexres_cfg);/*重置整个索引空间，恢复到最初的配置状态，注意，此时所有的索引都需要在未使用状态*/ + + +#endif + diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_liststack.h b/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_liststack.h new file mode 100644 index 0000000..cac0dda --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_liststack.h @@ -0,0 +1,95 @@ +/***************************************************************************** + * 版权所有 (C)2001-2005, 深圳市中兴通讯股份有限公司。 + * + * 文件名称： Rtm_ListStack.h + * 文件标识： + * 内容摘要： 链表栈管理头文件 + * 其它说明： 释放的元素放到队头 + * 当前版本： ZXR10 V2.6 + * 作 者： 郑纪伟 + * 完成日期： 2006-9-27 10:34 + * 当前责任人-1： + * 当前责任人-2： + * + * 修改记录1： + * 修改日期：2006-9-27 10:34 + * 版 本 号：ZXR10 V2.6 + * 修 改 人：郑纪伟 + * 修改内容：创建 + * + *修改记录2： + * 修改文件名称：ftmcomm_liststack.h + * 修改日期：2008-10-16 15:14 + * 版 本 号：ZXR10 V2.6 + * 修 改 人：HuangHe 170389 + * 修改内容：移植到T8000项目使用 + *修改记录3： + * 修改文件名称：zxic_liststack.h + * 修改日期：2012-03-15 15:14 + * 版 本 号：ZXR10 V2.6 + * 修 改 人：JiangWenming 12010401 + * 修改内容：移植到NSE项目使用 + * + *****************************************************************************/ +#ifndef __ZXIC_COMM_LIST_STACK_H__ +#define __ZXIC_COMM_LIST_STACK_H__ + + +/************************************************************************** + * 宏定义 * + **************************************************************************/ + +#define LISTSTACK_MAX_ELEMENT ((ZXIC_UINT32)(0x0ffffffe)) +#define LISTSTACK_INVALID_INDEX (0) +#define ALLOC_NUMBER (0x3) +/************************************************************************** + * liststack api * + **************************************************************************/ + +typedef struct _s_freelink +{ + ZXIC_UINT32 index; + ZXIC_UINT32 next; +}ZXIC_COMM_FREELINK; + + +typedef struct _s_List_Stack_Manager +{ + ZXIC_COMM_FREELINK *p_array; + + ZXIC_UINT32 capacity; + + ZXIC_UINT32 p_head; + + ZXIC_UINT32 free_num; + ZXIC_UINT32 used_num; + +}ZXIC_LISTSTACK_MANGER; + +/* +**zxic_comm_liststack_creat: +*/ + +ZXIC_RTN32 zxic_comm_liststack_creat (ZXIC_UINT32 element_num, + ZXIC_LISTSTACK_MANGER **p_list); + +/* +**NOTE:index allocated from 0: +*/ +ZXIC_RTN32 zxic_comm_liststack_alloc (ZXIC_LISTSTACK_MANGER *p_list, + ZXIC_UINT32 *index); +ZXIC_RTN32 zxic_comm_liststack_free (ZXIC_LISTSTACK_MANGER* p_list, + ZXIC_UINT32 index); +ZXIC_RTN32 zxic_comm_liststack_destroy(ZXIC_LISTSTACK_MANGER* p_list); +ZXIC_RTN32 zxic_comm_liststack_alloc_spec_index(ZXIC_LISTSTACK_MANGER* p_list, ZXIC_UINT32 index); + +ZXIC_RTN32 zxic_comm_liststack_show_used(ZXIC_LISTSTACK_MANGER* p_list, ZXIC_UINT32 line_number ); +ZXIC_RTN32 zxic_comm_liststack_show_free (ZXIC_LISTSTACK_MANGER* p_list, ZXIC_UINT32 line_number ); + + + +#endif /* end "_FTMCOMM_LIST_STACK_H" */ + + + + diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_rb_tree.h b/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_rb_tree.h new file mode 100644 index 0000000..cc3787c --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_rb_tree.h @@ -0,0 +1,128 @@ +/***************************************************************************** + * 版权所有 (C)2001-2015, 深圳市中兴通讯股份有限公司。 + * + * 文件名称： zxic_comm_rb_tree.h + * 文件标识： + * 内容摘要： + * 其它说明： + * 当前版本： + * 作 者： ChenWei10088471 + * 完成日期： + * 当前责任人-1： + * 当前责任人-2： + * + * DEPARTMENT : ASIC_FPGA_R&D_Dept + * MANUAL_PERCENT : 100% + *****************************************************************************/ + +#ifndef _ZXIC_COMM_RB_TREE_H +#define _ZXIC_COMM_RB_TREE_H + +#include "zxic_comm_double_link.h" +#include "zxic_comm_liststack.h" + +#define ZXIC_RBT_RED (0x1) +#define ZXIC_RBT_BLACK (0x2) +#define ZXIC_RBT_MAX_DEPTH (128) + +typedef ZXIC_SINT32 (*ZXIC_RB_CMPFUN)(ZXIC_VOID *p_new,ZXIC_VOID *p_old,ZXIC_UINT32 keysize); + + +typedef struct _rb_tn +{ + ZXIC_VOID *p_key; + ZXIC_UINT32 color_lsv; /*last 2 bits indicate color, bit2-31 if dynamic=0 indicate list val*/ + struct _rb_tn *p_left; + struct _rb_tn *p_right; + struct _rb_tn *p_parent; + D_NODE tn_ln; +}ZXIC_RB_TN; + +typedef struct _rb_cfg +{ + ZXIC_UINT32 key_size; + ZXIC_UINT32 is_dynamic; /* 1 - customer manage memory;0 - alloc all memory*/ + ZXIC_RB_TN *p_root; /* rb tree root node */ + D_HEAD tn_list; + ZXIC_RB_CMPFUN p_cmpfun; + ZXIC_LISTSTACK_MANGER *p_lsm; /* list stack manage*/ + ZXIC_UINT8 *p_keybase; + ZXIC_RB_TN *p_tnbase; + ZXIC_UINT32 is_init; +}ZXIC_RB_CFG; + + + +#define GET_TN_COLOR(p_tn) \ + ((p_tn == NULL) ? ZXIC_RBT_BLACK :(p_tn)->color_lsv & 0x3) + +#define SET_TN_COLOR(p_tn,color) \ + do{\ + (p_tn)->color_lsv &= 0xfffffffc;\ + (p_tn)->color_lsv |= (color & 0x3);\ + }while(0) + + + +#define GET_TN_LSV(p_tn) \ + ((p_tn)->color_lsv >> 2 ) + +#define SET_TN_LSV(p_tn,list_val) \ + do{\ + (p_tn)->color_lsv &= 0x3;\ + (p_tn)->color_lsv |= ((list_val) << 2); \ + }while(0) + + +/*init the rb node ,be careful init_color is red*/ +#define INIT_RBT_TN(p_tn,p_newkey) \ + do{\ + (p_tn)->p_key = p_newkey; \ + (p_tn)->color_lsv= 0; \ + (p_tn)->p_left = NULL; \ + (p_tn)->p_right = NULL; \ + (p_tn)->p_parent = NULL; \ + INIT_D_NODE(&((p_tn)->tn_ln),(p_tn));\ + }while(0) + +ZXIC_RTN32 zxic_comm_rb_init(ZXIC_RB_CFG *p_rb_cfg, + ZXIC_UINT32 total_num, + ZXIC_UINT32 key_size, + ZXIC_RB_CMPFUN cmpfun); + + +ZXIC_RTN32 zxic_comm_rb_insert(ZXIC_RB_CFG *p_rb_cfg, + ZXIC_VOID *p_key, + ZXIC_VOID *out_val); + +ZXIC_RTN32 zxic_comm_rb_delete(ZXIC_RB_CFG *p_rb_cfg, + ZXIC_VOID *p_key, + ZXIC_VOID *out_val); + +ZXIC_RTN32 zxic_comm_rb_search(ZXIC_RB_CFG *p_rb_cfg, + ZXIC_VOID *p_key, + ZXIC_VOID *out_val); + +ZXIC_RTN32 zxic_comm_rb_destroy(ZXIC_RB_CFG *p_rb_cfg); + +ZXIC_RB_TN *zxic_comm_rb_get_1st_tn(ZXIC_RB_CFG *p_rb_cfg); + +ZXIC_RB_TN *zxic_comm_rb_get_last_tn(ZXIC_RB_CFG *p_rb_cfg); + +ZXIC_RTN32 zxic_comm_rb_get_1st_key(ZXIC_RB_CFG* p_rb_cfg, ZXIC_VOID *p_key_out); + +ZXIC_RTN32 zxic_comm_rb_get_last_key(ZXIC_RB_CFG* p_rb_cfg, ZXIC_VOID *p_key_out); + +ZXIC_RTN32 zxic_comm_rb_insert_spec_index(ZXIC_RB_CFG *p_rb_cfg, ZXIC_VOID *p_key, ZXIC_UINT32 in_idx); + + +#define ZXIC_RBT_RC_BASE (0x1000) + +#define ZXIC_RBT_RC_UPDATE (ZXIC_RBT_RC_BASE | 0x1) +#define ZXIC_RBT_RC_SRHFAIL (ZXIC_RBT_RC_BASE | 0x2) +#define ZXIC_RBT_RC_FULL (ZXIC_RBT_RC_BASE | 0x3) +#define ZXIC_RBT_ISEMPTY_ERR (ZXIC_RBT_RC_BASE | 0x4) +#define ZXIC_RBT_PARA_INVALID (ZXIC_RBT_RC_BASE | 0x5) + +#endif + diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_socket.h b/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_socket.h new file mode 100644 index 0000000..aff6ef3 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_socket.h @@ -0,0 +1,157 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : zxic_comm_socket.h +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : 王春雷 +* 完成日期 : 2014/02/08 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ + +#ifndef _ZXIC_COMM_SOCKET_H_ +#define _ZXIC_COMM_SOCKET_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef ZXIC_OS_WIN +#include +typedef SOCKET ZXIC_SOCKET; + +#else +#include +#include +#include +#include +typedef ZXIC_SINT32 ZXIC_SOCKET; +#endif + +typedef struct sockaddr SOCKADDR; +typedef struct sockaddr_in SOCKADDR_IN; + + +#define ZXIC_SOCK_VALID (0) +#define ZXIC_SOCK_INVALID (-1) +#define ZXIC_SOCK_NUM_MAX (16) + +#define ZXIC_SOCK_INADDR_ANY (0x00000000) +#define ZXIC_SOCK_INADDR_LOOPBACK (0x7f000001) +#define ZXIC_SOCK_INADDR_BROADCAST (0xffffffff) +#define ZXIC_SOCK_INADDR_NONE (0xffffffff) + +/* socket domain */ +#define ZXIC_SOCK_AF_INET AF_INET /* internetwork: UDP, TCP, etc. */ +#define ZXIC_SOCK_AF_INET6 AF_INET6 /* Internetwork Version 6 */ + +/* socket type */ +#define ZXIC_SOCK_STREAM SOCK_STREAM /* stream socket */ +#define ZXIC_SOCK_DGRAM SOCK_DGRAM /* datagram socket */ +#define ZXIC_SOCK_RAW SOCK_RAW /* raw-protocol interface */ +#define ZXIC_SOCK_RDM SOCK_RDM /* reliably-delivered message */ +#define ZXIC_SOCK_SEQPACKET SOCK_SEQPACKET /* sequenced packet stream */ + +/* socket protocol */ +#define ZXIC_SOCK_IPPROTO_IP IPPROTO_IP /* dummy for IP */ +#define ZXIC_SOCK_IPPROTO_TCP IPPROTO_TCP /* tcp */ +#define ZXIC_SOCK_IPPROTO_UDP IPPROTO_UDP /* user datagram protocol */ + +/* socket level */ +#define ZXIC_SOCK_SOL_SOCKET SOL_SOCKET /* options for socket level */ + +/* socket OptName */ +#define ZXIC_SOCK_SO_DEBUG SO_DEBUG /* turn on debugging info recording */ +#define ZXIC_SOCK_SO_ACCEPTCONN SO_ACCEPTCONN /* socket has had listen() */ +#define ZXIC_SOCK_SO_REUSEADDR SO_REUSEADDR /* allow local address reuse */ +#define ZXIC_SOCK_SO_KEEPALIVE SO_KEEPALIVE /* keep connections alive */ +#define ZXIC_SOCK_SO_DONTROUTE SO_DONTROUTE /* just use interface addresses */ +#define ZXIC_SOCK_SO_BROADCAST SO_BROADCAST /* permit sending of broadcast msgs */ +#define ZXIC_SOCK_SO_USELOOPBACK SO_USELOOPBACK /* bypass hardware when possible */ +#define ZXIC_SOCK_SO_LINGER SO_LINGER /* linger on close if data present */ +#define ZXIC_SOCK_SO_OOBINLINE SO_OOBINLINE /* leave received OOB data in line */ +#define ZXIC_SOCK_SO_SNDBUF SO_SNDBUF /* send buffer size */ +#define ZXIC_SOCK_SO_RCVBUF SO_RCVBUF /* receive buffer size */ +#define ZXIC_SOCK_SO_SNDLOWAT SO_SNDLOWAT /* send low-water mark */ +#define ZXIC_SOCK_SO_RCVLOWAT SO_RCVLOWAT /* receive low-water mark */ +#define ZXIC_SOCK_SO_SNDTIMEO SO_SNDTIMEO /* send timeout */ +#define ZXIC_SOCK_SO_RCVTIMEO SO_RCVTIMEO /* receive timeout */ +#define ZXIC_SOCK_SO_ERROR SO_ERROR /* get error status and clear */ +#define ZXIC_SOCK_SO_TYPE SO_TYPE /* get socket type */ + + +#define ZXIC_TCP_OP_NODELAY TCP_NODELAY + +typedef struct zxic_comm_sock_addr_t +{ + ZXIC_UINT32 family; + ZXIC_UINT32 port; + ZXIC_UINT32 addr; +}ZXIC_SOCK_ADDR_T; + +typedef struct zxic_comm_sock_mgr_t +{ + ZXIC_UINT32 is_init; + ZXIC_UINT32 count; + ZXIC_SOCKET socks[ZXIC_SOCK_NUM_MAX]; + ZXIC_UINT8 sock_vld[ZXIC_SOCK_NUM_MAX]; + ZXIC_MUTEX_T mutex; +}ZXIC_SOCK_MGR_T; + +/* API */ +ZXIC_RTN32 zxic_comm_sock_init(ZXIC_VOID); +ZXIC_RTN32 zxic_comm_sock_service_start(ZXIC_VOID); +ZXIC_RTN32 zxic_comm_sock_service_close(ZXIC_VOID); +ZXIC_RTN32 zxic_comm_sock_create(ZXIC_SOCKET *p_socket, + ZXIC_SINT32 domain, + ZXIC_SINT32 type, + ZXIC_SINT32 protocol); + +ZXIC_RTN32 zxic_comm_sock_set_opt(ZXIC_SOCKET sock, + ZXIC_SINT32 level, + ZXIC_SINT32 opt_name, + ZXIC_VOID *p_opt_val, + ZXIC_UINT32 opt_len); + +ZXIC_RTN32 zxic_comm_sock_get_opt(ZXIC_SOCKET sock, + ZXIC_SINT32 level, + ZXIC_SINT32 opt_name, + ZXIC_VOID *p_opt_val, + ZXIC_UINT32 *p_opt_len); + +ZXIC_RTN32 zxic_comm_sock_bind_listen(ZXIC_SOCKET sock, + ZXIC_SOCK_ADDR_T *p_sock_addr); + +ZXIC_RTN32 zxic_comm_sock_accpet(ZXIC_SOCKET listen_sock, + ZXIC_SOCKET *p_cnnt_sock, + ZXIC_SOCK_ADDR_T *p_sock_addr); + +ZXIC_RTN32 zxic_comm_sock_connect(ZXIC_SOCKET sock, + ZXIC_SOCK_ADDR_T *p_sock_addr); + +ZXIC_SINT32 zxic_comm_sock_send(ZXIC_SOCKET sock, + ZXIC_CHAR *p_buf, + ZXIC_SINT32 len, + ZXIC_SINT32 flag); + +ZXIC_SINT32 zxic_comm_sock_recv(ZXIC_SOCKET sock, + ZXIC_CHAR *p_buf, + ZXIC_SINT32 len, + ZXIC_SINT32 flag); + +ZXIC_RTN32 zxic_comm_sock_close(ZXIC_SOCKET sock); + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_thread.h b/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_thread.h new file mode 100644 index 0000000..f07d090 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_thread.h @@ -0,0 +1,95 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : zxic_comm_thread.h +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : 王春雷 +* 完成日期 : 2014/02/08 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ + +#ifndef _ZXIC_COMM_THREAD_H_ +#define _ZXIC_COMM_THREAD_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef ZXIC_OS_LINUX +#include +#include +#endif + +#define THREAD_NAME_MAX (64) +#define ZXIC_THREAD_TIME_INFINITE (0xFFFFFFFF) /* Infinite timeout */ + +typedef ZXIC_VOID* (*ZXIC_THREAD_FUNC) (ZXIC_VOID*); + +/* Thread ID */ +typedef struct zxic_comm_thread_id_t +{ +#ifdef ZXIC_OS_WIN + HANDLE id; +#else + //pthread_t id; + int id; +#endif +}ZXIC_THREAD_ID_T; + +/* Thread CreateFlag */ +#define ZXIC_THREAD_FLAG_DETACH (1 << 0) +#define ZXIC_THREAD_FLAG_EXPLICIT_SCHED (1 << 1) + +typedef struct zxic_comm_thread_info_t +{ + ZXIC_CHAR name[THREAD_NAME_MAX]; /* 线程名 */ + ZXIC_UINT32 priority; /* 优先级 */ + ZXIC_UINT32 stack_size; /* 初始栈大小，以字节为单位 */ + ZXIC_UINT32 create_flag; /* 线程标志 */ + ZXIC_THREAD_ID_T id; /* 线程ID */ + ZXIC_THREAD_FUNC thread_func; /* 线程函数 */ + ZXIC_VOID* p_arg; /* 线程入参 */ + ZXIC_UINT32 is_valid; /* 是否有效 */ +}ZXIC_THREAD_INFO_T; + +/* API */ +ZXIC_RTN32 zxic_comm_thread_info_init(ZXIC_VOID); +ZXIC_RTN32 zxic_comm_thread_info_add(ZXIC_THREAD_ID_T* p_thread_id, + ZXIC_CONST ZXIC_CHAR* p_name, + ZXIC_UINT32 priority, + ZXIC_UINT32 stack_size, + ZXIC_UINT32 create_flag, + ZXIC_THREAD_FUNC p_thread_func, + ZXIC_VOID* p_arg, + ZXIC_UINT32* p_info_index); +ZXIC_RTN32 zxic_comm_thread_info_del(ZXIC_THREAD_ID_T *p_thread_id); +ZXIC_RTN32 zxic_comm_thread_info_print(ZXIC_VOID); + +ZXIC_RTN32 zxic_comm_thread_create(ZXIC_CONST ZXIC_CHAR *p_name, + ZXIC_UINT32 priority, + ZXIC_UINT32 stack_size, + ZXIC_UINT32 create_flag, + ZXIC_THREAD_FUNC thread_func, + ZXIC_VOID *p_arg, + ZXIC_THREAD_ID_T *p_thread_id); + +ZXIC_RTN32 zxic_comm_thread_exit(ZXIC_VOID); +ZXIC_RTN32 zxic_comm_thread_wait(ZXIC_THREAD_ID_T *p_thread_id, ZXIC_DWORD wait_time); +ZXIC_RTN32 zxic_comm_thread_close_handle(ZXIC_THREAD_ID_T *p_thread_id); + +#ifdef __cplusplus +} +#endif + + +#endif + diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_common.h b/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_common.h new file mode 100644 index 0000000..59ea706 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_common.h @@ -0,0 +1,2674 @@ +/************************************************************** +* 版权所有 (C)2013-2020, 深圳市中兴通讯股份有限公司 +* 文件名称 : zxic_common.h +* 文件标识 : +* 内容摘要 : 大部分的项目,只需要感知这一个头文件即可, + 其包括了变量定义/打印/日志/参数校验/互斥锁/bit流拼接等常用定义和功能 +* 其它说明 : 编译宏：ZXIC_OS_WIN/ZXIC_RELEASE/MACRO_CPU64 +* 当前版本 : +* 作 者 : +* 完成日期 : 2020/07/20 +* DEPARTMENT: 有线开发四部-系统软件团队 +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ +#ifndef __ZXIC_COMMON_H__ +#define __ZXIC_COMMON_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* +编译宏说明 +ZXIC_OS_WIN :若不导入该宏,则默认为 ZXIC_OS_LINUX +ZXIC_RELEASE:若不导入该宏,则默认为 ZXIC_DEBUG +MACRO_CPU64 :若不导入该宏,则默认为32位操作系统 +*/ + +#include "zxic_private_top.h" +#include "zxic_private.h" +//#include +//#include +//#include +#include +#include +//#include +//#include +#include +//#include +#include +//#include + +#ifdef ZXIC_OS_WIN /* 编译宏导入 */ +#include +#include +#include +#include +#pragma warning (disable:4996) +#else +#include +#include +#include +//#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#endif + +#if ZXIC_REAL("数据类型定义") +/* 无符号整数 */ +#define ZXIC_UINT8 unsigned char +#define ZXIC_UINT16 unsigned short + +#ifndef ZXIC_UINT32 +#define ZXIC_UINT32 unsigned int +#endif + +#ifndef ZXIC_UINT64 +#define ZXIC_UINT64 unsigned long long +#endif +#define ZXIC_DWORD unsigned long /* 慎用,注意:WIN系统:32bits LINUX系统:64bits */ +#define ZXIC_SIZE_T size_t /* 32位系统:uint32 64位系统:uint64 */ + +/* 有符号整数 */ +#define ZXIC_CHAR char /* char默认为unsigned还是signed取决于编译器,定义字符可用 */ +#define ZXIC_SINT8 signed char +#define ZXIC_SINT16 signed short + +#ifndef ZXIC_SINT32 +#define ZXIC_SINT32 signed int +#endif + +#ifndef ZXIC_SINT64 +#define ZXIC_SINT64 signed long long +#endif + +#define ZXIC_SDWORD long + +/* 浮点数 */ +//#define ZXIC_FLOAT float +//#define ZXIC_DOUBLE double +//#define ZXIC_LDOUBLE long double +#define ZXIC_FLOAT int +#define ZXIC_DOUBLE long +#define ZXIC_LDOUBLE long long + +/* 文件类型 */ +typedef struct file ZXIC_FILE; + +/* */ +#define ZXIC_VOL volatile +#define ZXIC_VOID void +#define ZXIC_CONST const +#define ZXIC_RTN32 ZXIC_UINT32 + +#ifdef MACRO_CPU64 /* 64位系统编译宏导入,慎重修改 */ +#define ZXIC_ADDR_T ZXIC_UINT64 +#define ZXIC_SIZEOF(x) (sizeof(x) & 0xFFFFFFFFU) /* 在64位环境下，sizeof的长度是64b */ +#define ZXIC_SIZEOF_T(x) ((ZXIC_UINT32)(sizeof(x) & 0xFFFFFFFF)) + +#else +#define ZXIC_ADDR_T ZXIC_UINT32 +#define ZXIC_SIZEOF(x) (sizeof(x)) +#define ZXIC_SIZEOF_T(x) (sizeof(x)) +#endif + +/* 特殊变量 */ +#define ZXIC_NULL (0) +#define ZXIC_OK (0U) /* 后面加U,防止32位系统64位系统常量的默认长度不一致 */ +#define ZXIC_ERR (1U) +#define ZXIC_TRUE (1U) +#define ZXIC_FALSE (0U) +#define ZXIC_UINT8_MAX (0xFFU) +#define ZXIC_UINT32_MAX (0xFFFFFFFFU) +#define ZXIC_ULONG_MAX (0xFFFFFFFFFFFFFFFFUL) +#define ZXIC_SINT_MAX (0x7FFFFFFF) +#define ZXIC_SINT_MIN (-ZXIC_SINT_MAX - 1) + + +#define ZXIC_UINT64_MASK (0xFFFFFFFFFFFFFFFFULL) +#define ZXIC_UINT32_MASK (0xFFFFFFFFU) +#define ZXIC_UINT16_MASK (0xFFFFU) +#define ZXIC_UINT8_MASK (0xFFU) +#endif /* END 数据类型定义 */ + +#if ZXIC_REAL("宏函数定义") +#define ZXIC_COMM_MEMCMP ic_comm_memcmp +#define ZXIC_COMM_MEMSET memset +#define ZXIC_COMM_MEMMOVE memmove +#define ZXIC_COMM_MEMSET_S ic_comm_memset_s +#define ZXIC_COMM_MEMCPY ic_comm_memcpy +#define ZXIC_COMM_MEMCPY_S ic_comm_memcpy_s +#define ZXIC_COMM_STRLEN strlen +#define ZXIC_COMM_STRNLEN strnlen +#define ZXIC_COMM_STRNLEN_S ic_comm_strnlen_s +#define ZXIC_COMM_STRCPY strcpy +#define ZXIC_COMM_STRCPY_S ic_comm_strcpy_s +#define ZXIC_COMM_STRNCPY strncpy +#define ZXIC_COMM_STRNCPY_S ic_comm_strncpy_s +#define ZXIC_COMM_STRCMP strcmp +#define ZXIC_COMM_STRNCMP ic_comm_strncmp +#define ZXIC_COMM_STRTOK strtok +#define ZXIC_COMM_STRTOK_S ic_comm_strtok_s +#define ZXIC_COMM_STRCAT_S ic_comm_strcat_s +#define ZXIC_COMM_STRNCAT_S ic_comm_strncat_s + +//#define ZXIC_COMM_FOPEN fopen +#define ZXIC_COMM_FOPEN filp_open +//#define ZXIC_COMM_FCLOSE fclose +#define ZXIC_COMM_FCLOSE(a) filp_close(a,NULL) +#define ZXIC_COMM_FGETS fgets +#define ZXIC_COMM_FPUTS fputs +#define ZXIC_COMM_FREAD fread + +// #define ZXIC_COMM_FPRINTF fprintf +// #define ZXIC_COMM_FPRINTF(a,b,c) printk(b,c) +#define ZXIC_COMM_SSCANF ic_comm_sscanf +#define ZXIC_COMM_FSCANF (void)fscanf +#define ZXIC_COMM_SNPRINTF_S ic_comm_snprintf_s +#define ZXIC_COMM_VSNPRINTF_S ic_comm_vsnprintf_s + +#define ZXIC_COMM_TIME time +#define ZXIC_COMM_ATOI atoi + +#ifdef ZXIC_OS_WIN +#define ZXIC_COMM_ACCESS _access +#define ZXIC_COMM_SNPRINTF _snprintf +#define ZXIC_COMM_VSNPRINTF _vsnprintf +#define ZXIC_COMM_GETPID _getpid +#else +#define ZXIC_COMM_ACCESS kern_path +/*#define ZXIC_COMM_SNPRINTF snprintf*/ +#define ZXIC_COMM_SNPRINTF(a,b,c...) __snprintf_chk(a,b,0,b,c) +#define ZXIC_COMM_VSNPRINTF vsnprintf +#define ZXIC_COMM_GETPID getpid +#endif + +#ifdef MACRO_CPU64 /* 64位系统编译宏导入,慎重修改 */ +#define ZXIC_COMM_PTR_TO_VAL(p) ((ZXIC_UINT64)(p)) +#define ZXIC_COMM_VAL_TO_PTR(v) ((ZXIC_VOID *)((ZXIC_UINT64)(v))) +#define ZXIC_SSIZE_T ZXIC_SINT64 +#else +#define ZXIC_COMM_PTR_TO_VAL(p) ((ZXIC_UINT32)(p)) +#define ZXIC_COMM_VAL_TO_PTR(v) ((ZXIC_VOID *)(long)((ZXIC_UINT32)(v))) +#define ZXIC_SSIZE_T ZXIC_SINT32 + +#endif + +#ifdef ZXIC_OS_WIN +#define ZXIC_COMM_STRCASECMP stricmp +#else +#define ZXIC_COMM_STRCASECMP strcasecmp +#endif + +#define ZXIC_COMM_FFLUSH (ZXIC_VOID)fflush +#define ZXIC_COMM_SPRINTF (ZXIC_VOID)sprintf + + + +#ifdef ZXIC_RELEASE /* 编译宏控制,默认编译为DEBUG版本 */ +#define ZXIC_COMM_ASSERT(x) +#else + #ifdef ZXIC_FOR_FUZZER + #define ZXIC_COMM_ASSERT(x) + #else + #define ZXIC_COMM_ASSERT(x) + #endif +#endif + +#endif /* END 宏函数定义 */ + +#define ZXIC_COMM_MEMORY_MAX_B_SIZE (200 * 1024 * 1024) /* 200M */ +#define ZXIC_COMM_STRNLEN_MAX (0xffffffff) + +#if ZXIC_REAL("打印-print") +#if ZXIC_REAL("开关") +ZXIC_VOID zxic_comm_set_print_en (ZXIC_UINT32 enable); +ZXIC_RTN32 zxic_comm_get_print_en (ZXIC_VOID); +ZXIC_VOID zxic_comm_set_print_level(ZXIC_TRACE_LEVEL debug_level); +ZXIC_RTN32 zxic_comm_get_print_level(ZXIC_VOID); +#endif +#if ZXIC_REAL("功能") +ZXIC_VOID ZXIC_COMM_PRINT(ZXIC_CONST ZXIC_CHAR *format, ...); +ZXIC_VOID ZXIC_COMM_TRACE_ERROR(ZXIC_CONST ZXIC_CHAR *format, ...); +ZXIC_VOID ZXIC_COMM_TRACE_INFO(ZXIC_CONST ZXIC_CHAR *format, ...); +ZXIC_VOID ZXIC_COMM_TRACE_DEBUG(ZXIC_CONST ZXIC_CHAR *format, ...); +ZXIC_VOID ZXIC_COMM_TRACE_ALL(ZXIC_CONST ZXIC_CHAR *format, ...); + +ZXIC_VOID ZXIC_COMM_TRACE_DEV_ERROR(ZXIC_UINT32 dev_id, ZXIC_CONST ZXIC_CHAR *format, ...); +ZXIC_VOID ZXIC_COMM_TRACE_DEV_INFO(ZXIC_UINT32 dev_id, ZXIC_CONST ZXIC_CHAR *format, ...); +ZXIC_VOID ZXIC_COMM_TRACE_DEV_DEBUG(ZXIC_UINT32 dev_id,ZXIC_CONST ZXIC_CHAR *format, ...); +ZXIC_VOID ZXIC_COMM_TRACE_DEV_ALL(ZXIC_UINT32 dev_id, ZXIC_CONST ZXIC_CHAR *format, ...); + +ZXIC_VOID ZXIC_COMM_DBGCNT64_PRINT (ZXIC_CONST ZXIC_CHAR * name, ZXIC_UINT64 value); +ZXIC_VOID ZXIC_COMM_DBGCNT32_PRINT (ZXIC_CONST ZXIC_CHAR * name, ZXIC_UINT32 value); +ZXIC_VOID ZXIC_COMM_DBGCNT32_PAR_PRINT (ZXIC_CONST ZXIC_CHAR * name, ZXIC_UINT32 parm, ZXIC_UINT32 value); + +#endif +#endif + +#if ZXIC_REAL("互斥锁") +ZXIC_RTN32 zxic_comm_mutex_create (ZXIC_MUTEX_T *p_mutex); +ZXIC_RTN32 zxic_comm_mutex_lock (ZXIC_MUTEX_T *p_mutex); +ZXIC_RTN32 zxic_comm_mutex_unlock (ZXIC_MUTEX_T *p_mutex); +ZXIC_RTN32 zxic_comm_mutex_destroy(ZXIC_MUTEX_T *p_mutex); +#endif + +#if ZXIC_REAL("信号量") +ZXIC_RTN32 zxic_comm_sem_create(ZXIC_SEM_T *p_sem, ZXIC_SINT32 share, ZXIC_SINT32 IniCount, ZXIC_SINT32 MaxCount); +ZXIC_RTN32 zxic_comm_sem_release(ZXIC_SEM_T *p_sem); +ZXIC_RTN32 zxic_comm_sem_wait(ZXIC_SEM_T *p_sem); +#endif + +#if ZXIC_REAL("参数检查") + +#if ZXIC_REAL("NO DEV_ID & ASSERT") +#define ZXIC_COMM_CHECK_RC(rc,becall)\ + do{\ + if(ZXIC_OK != rc)\ + {\ + ZXIC_COMM_TRACE_ERROR("\n ZXIC %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,becall);\ + ZXIC_COMM_ASSERT(0);\ + return rc;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_RC_MEMORY_FREE(rc, becall, ptr)\ + do{\ + if (ZXIC_OK != rc)\ + {\ + ZXIC_COMM_TRACE_ERROR("\n ZXICP %s:%d [ErrorCode:0x%x], %s Call %s Fail!\n", __FILE__, __LINE__, rc, __FUNCTION__, becall);\ + ZXIC_COMM_FREE(ptr);\ + ZXIC_COMM_ASSERT(0);\ + return rc;\ + }\ + } while(0) + +#define ZXIC_COMM_CHECK_POINT(point)\ + do{\ + if(ZXIC_NULL == (point))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);\ + ZXIC_COMM_ASSERT(0);\ + return ZXIC_PAR_CHK_POINT_NULL;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_POINT_MEMORY_FREE(point, ptr)\ + do{\ + if(ZXIC_NULL == (point))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);\ + ZXIC_COMM_FREE(ptr);\ + ZXIC_COMM_ASSERT(0);\ + return ZXIC_PAR_CHK_POINT_NULL;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_POINT_EMEMORY_FREE2PTR(point, ptr0, ptr1)\ + do{\ + if(ZXIC_NULL == (point))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);\ + ZXIC_COMM_FREE(ptr0);\ + ZXIC_COMM_FREE(ptr1);\ + ZXIC_COMM_ASSERT(0);\ + return ZXIC_PAR_CHK_POINT_NULL;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_POINT_RETURN_NULL(point)\ + do{\ + if(ZXIC_NULL == (point))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);\ + ZXIC_COMM_ASSERT(0);\ + return ZXIC_NULL;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_INDEX(val,min,max)\ + do{\ + if(ZXIC_PAR_CHK_INVALID_INDEX == zxic_comm_index_check(val, min, max))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\ + ZXIC_COMM_ASSERT(0);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + else if(ZXIC_PAR_CHK_INVALID_RANGE == zxic_comm_index_check(val, min, max))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\ + ZXIC_COMM_ASSERT(0);\ + return ZXIC_PAR_CHK_INVALID_RANGE;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_INDEX_EQUAL(val,equal)\ + do{\ + if(val == equal)\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [equal=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, equal, __FUNCTION__);\ + ZXIC_COMM_ASSERT(0);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_INDEX_EQUAL_RETURN_OK(val,equal)\ + do{\ + if(val == equal)\ + {\ + return ZXIC_OK;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_INDEX_NOT_EQUAL(val,equal)\ + do{\ + if(val != equal)\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [equal=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, equal, __FUNCTION__);\ + ZXIC_COMM_ASSERT(0);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_INDEX_UPPER(val,max)\ + do{\ + if((val) > (max))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, max, __FUNCTION__);\ + ZXIC_COMM_ASSERT(0);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_INDEX_LOWER(val,min)\ + do{\ + if((val) < (min))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, __FUNCTION__);\ + ZXIC_COMM_ASSERT(0);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_INDEX_BOTH(val,min,max)\ + do{\ + if(((val) < (min)) || ((val) > (max)))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\ + ZXIC_COMM_ASSERT(0);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_INDEX_UPPER_MEMORY_FREE(val,max,ptr)\ + do{\ + if((val) > (max))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, max, __FUNCTION__);\ + ZXIC_COMM_FREE(ptr);\ + ZXIC_COMM_ASSERT(0);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_INDEX_LOWER_MEMORY_FREE(val,min,ptr)\ + do{\ + if((val) < (min))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, __FUNCTION__);\ + ZXIC_COMM_FREE(ptr);\ + ZXIC_COMM_ASSERT(0);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_INDEX_BOTH_MEMORY_FREE(val,min,max,ptr)\ + do{\ + if(((val) < (min)) || ((val) > (max)))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\ + ZXIC_COMM_FREE(ptr);\ + ZXIC_COMM_ASSERT(0);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_MEMORY_FREE(val0,val1,ptr)\ + do{\ + if((ZXIC_UINT32_MAX - (val0)) < (val1))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\ + ZXIC_COMM_FREE(ptr);\ + ZXIC_COMM_ASSERT(0);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(val0,val1)\ + do{\ + if((ZXIC_UINT32_MAX - (val0)) < (val1))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\ + ZXIC_COMM_ASSERT(0);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + }while(0) + + +#define ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_64(val0,val1)\ +do{\ + if((ZXIC_ULONG_MAX - (val0)) < (val1))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[val0=0x%016llx] INVALID] [val1=0x%016llx] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\ + ZXIC_COMM_ASSERT(0);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ +}while(0) + +#define ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_UNLOCK(val0, val1, mutex)\ + do{\ + if((ZXIC_UINT32_MAX - (val0)) < (val1))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\ + if(0 != zxic_comm_mutex_unlock(mutex))\ + {\ + ZXIC_COMM_TRACE_ERROR("File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", __FILE__, __FUNCTION__, __LINE__);\ + }\ + ZXIC_COMM_ASSERT(0);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW(val0,val1)\ + do{\ + if((val0) < (val1))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\ + ZXIC_COMM_ASSERT(0);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW_64(val0,val1)\ +do{\ + if((val0) < (val1))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[val0=0x%016llx] INVALID] [val1=0x%016llx] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\ + ZXIC_COMM_ASSERT(0);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ +}while(0) + +#define ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW_UNLOCK(val0, val1, mutex)\ +do{\ +if((val0) < (val1))\ +{\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\ + if(0 != zxic_comm_mutex_unlock(mutex))\ + {\ + ZXIC_COMM_TRACE_ERROR("File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", __FILE__, __FUNCTION__, __LINE__);\ + }\ + ZXIC_COMM_ASSERT(0);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ +}\ +}while(0) + +#define ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW(val0,val1)\ +do{\ + if(((val0) > 0) && ((ZXIC_UINT32_MAX / (val0)) < (val1)))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\ + ZXIC_COMM_ASSERT(0);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ +}while(0) +#define ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW_64(val0,val1)\ +do{\ + if(((val0) > 0) && ((ZXIC_ULONG_MAX / (val0)) < (val1)))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[val0=0x%016llx] INVALID] [val1=0x%016llx] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\ + ZXIC_COMM_ASSERT(0);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ +}while(0) + +#define ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW_UNLOCK(val0, val1, mutex)\ +do{\ + if(((val0) > 0) && ((ZXIC_UINT32_MAX / (val0)) < (val1)))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\ + if(0 != zxic_comm_mutex_unlock(mutex))\ + {\ + ZXIC_COMM_TRACE_ERROR("File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", __FILE__, __FUNCTION__, __LINE__);\ + }\ + ZXIC_COMM_ASSERT(0);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ +}while(0) + +#define ZXIC_COMM_CHECK_INDEX_RETURN_NULL(val,min,max)\ + do{\ + if(ZXIC_PAR_CHK_INVALID_INDEX == zxic_comm_index_check(val, min, max))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\ + ZXIC_COMM_ASSERT(0);\ + return ZXIC_NULL;\ + }\ + else if(ZXIC_PAR_CHK_INVALID_RANGE == zxic_comm_index_check(val, min, max))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\ + ZXIC_COMM_ASSERT(0);\ + return ZXIC_NULL;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_RC_UNLOCK(rc, becall, mutex)\ + do{\ + if(ZXIC_OK != rc)\ + {\ + ZXIC_COMM_TRACE_ERROR("\n ZXIC %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,becall);\ + if(0 != zxic_comm_mutex_unlock(mutex))\ + { \ + ZXIC_COMM_TRACE_ERROR("File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", __FILE__, __FUNCTION__, __LINE__);\ + } \ + ZXIC_COMM_ASSERT(0);\ + return rc;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_RC_CLOSE_FP(rc, becall, fp)\ + do{\ + if(ZXIC_OK != rc)\ + {\ + ZXIC_COMM_TRACE_ERROR("\n ZXIC %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,becall);\ + if(ZXIC_COMM_FCLOSE(fp))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n ZXIC %s:%d !-- %s close file Fail!\n",__FILE__,__LINE__,__FUNCTION__);\ + }\ + ZXIC_COMM_ASSERT(0);\ + return rc;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_POINT_CLOSE_FP(point, fp)\ + do{\ + if(NULL == (point))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);\ + if (ZXIC_COMM_FCLOSE(fp))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n ZXIC %s:%d !-- %s close file Fail!\n",__FILE__,__LINE__,__FUNCTION__);\ + }\ + ZXIC_COMM_ASSERT(0);\ + return ZXIC_PAR_CHK_POINT_NULL;\ + }\ + }while(0)\ + + +#define ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_RETURN(val0, val1)\ + do{\ + if((0xFFFFFFFF - (val0)) < (val1))\ + {\ + ZXIC_COMM_TRACE_ERROR("ICM %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\ + return;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW_RETURN(val0, val1)\ + do{\ + if(val0 < val1)\ + {\ + ZXIC_COMM_TRACE_ERROR("ICM %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\ + return;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_CLOSE_FP_NO_ASSERT(dev_id, val0, val1, fp)\ + do{\ + if((0xFFFFFFFF - (val0)) < (val1))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "ICM %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\ + if (ZXIC_COMM_FCLOSE(fp))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n ICM %s:%d !-- %s close file Fail!\n",__FILE__,__LINE__,__FUNCTION__);\ + }\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_CLOSE_FP_NO_ASSERT(dev_id, val0, val1, fp)\ + do{\ + if((val0 > 0) && ((0xFFFFFFFF / (val0)) < (val1)))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "ICM %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\ + if (ZXIC_COMM_FCLOSE(fp))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n ICM %s:%d !-- %s close file Fail!\n",__FILE__,__LINE__,__FUNCTION__);\ + }\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + }while(0) + +#endif + +#if ZXIC_REAL("NO DEV_ID & NO ASSERT") +#define ZXIC_COMM_CHECK_RC_NO_ASSERT(rc,becall)\ + do{\ + if(ZXIC_OK != rc)\ + {\ + ZXIC_COMM_TRACE_ERROR("\n ZXIC %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,becall);\ + return rc;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_RC_NO_ASSERT_UNLOCK(rc, becall, mutex)\ + do{\ + if(ZXIC_OK != rc)\ + {\ + ZXIC_COMM_TRACE_ERROR("\n ZXIC %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,becall);\ + if(0 != zxic_comm_mutex_unlock(mutex))\ + { \ + ZXIC_COMM_TRACE_ERROR("File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", __FILE__, __FUNCTION__, __LINE__);\ + } \ + return rc;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, becall, ptr)\ + do{\ + if (ZXIC_OK != rc)\ + {\ + ZXIC_COMM_TRACE_ERROR("\n ZXICP %s:%d [ErrorCode:0x%x], %s Call %s Fail!\n", __FILE__, __LINE__, rc, __FUNCTION__, becall);\ + ZXIC_COMM_FREE(ptr);\ + return rc;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_RC_MEMORY_FREE2PTR_NO_ASSERT(rc, becall, ptr1, ptr2)\ + do{\ + if (ZXIC_OK != rc)\ + {\ + ZXIC_COMM_TRACE_ERROR("\n ZXICP %s:%d [ErrorCode:0x%x], %s Call %s Fail!\n", __FILE__, __LINE__, rc, __FUNCTION__, becall);\ + ZXIC_COMM_FREE(ptr1);\ + ZXIC_COMM_FREE(ptr2);\ + return rc;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_RC_MEMORY_FREE3PTR_NO_ASSERT(rc, becall, ptr1, ptr2, ptr3)\ + do{\ + if (ZXIC_OK != rc)\ + {\ + ZXIC_COMM_TRACE_ERROR("\n ZXICP %s:%d [ErrorCode:0x%x], %s Call %s Fail!\n", __FILE__, __LINE__, rc, __FUNCTION__, becall);\ + ZXIC_COMM_FREE(ptr1);\ + ZXIC_COMM_FREE(ptr2);\ + ZXIC_COMM_FREE(ptr3);\ + return rc;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_POINT_NO_ASSERT(point)\ + do{\ + if(ZXIC_NULL == (point))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);\ + return ZXIC_PAR_CHK_POINT_NULL;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_POINT_CLOSE_FP_NO_ASSERT(point, fp)\ + do{\ + if(NULL == (point))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);\ + if (ZXIC_COMM_FCLOSE(fp))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n ZXIC %s:%d !-- %s close file Fail!\n",__FILE__,__LINE__,__FUNCTION__);\ + }\ + return ZXIC_PAR_CHK_POINT_NULL;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_POINT_MEMORY_FREE_NO_ASSERT(point,ptr)\ + do{\ + if(ZXIC_NULL == (point))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);\ + ZXIC_COMM_FREE(ptr);\ + return ZXIC_PAR_CHK_POINT_NULL;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_POINT_MEMORY_FREE2PTR_NO_ASSERT(point, ptr1, ptr2)\ + do{\ + if(ZXIC_NULL == (point))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);\ + ZXIC_COMM_FREE(ptr1);\ + ZXIC_COMM_FREE(ptr2);\ + return ZXIC_PAR_CHK_POINT_NULL;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_POINT_MEMORY_FREE3PTR_NO_ASSERT(point, ptr1, ptr2, ptr3)\ + do{\ + if(ZXIC_NULL == (point))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);\ + ZXIC_COMM_FREE(ptr1);\ + ZXIC_COMM_FREE(ptr2);\ + ZXIC_COMM_FREE(ptr3);\ + return ZXIC_PAR_CHK_POINT_NULL;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_INDEX_NO_ASSERT(val,min,max)\ + do{\ + if(ZXIC_PAR_CHK_INVALID_INDEX == zxic_comm_index_check(val, min, max))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + else if(ZXIC_PAR_CHK_INVALID_RANGE == zxic_comm_index_check(val, min, max))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\ + return ZXIC_PAR_CHK_INVALID_RANGE;\ + }\ + }while (0) + +#define ZXIC_COMM_CHECK_INDEX_NO_ASSERT_UNLOCK(val, min, max, mutex)\ + do{\ + if(ZXIC_PAR_CHK_INVALID_INDEX == zxic_comm_index_check(val, min, max))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\ + if(0 != zxic_comm_mutex_unlock(mutex))\ + { \ + ZXIC_COMM_TRACE_ERROR("File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", __FILE__, __FUNCTION__, __LINE__);\ + } \ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + else if(ZXIC_PAR_CHK_INVALID_RANGE == zxic_comm_index_check(val, min, max))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\ + if(0 != zxic_comm_mutex_unlock(mutex))\ + { \ + ZXIC_COMM_TRACE_ERROR("File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", __FILE__, __FUNCTION__, __LINE__);\ + } \ + return ZXIC_PAR_CHK_INVALID_RANGE;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_INDEX_UPPER_NO_ASSERT(val, max)\ + do{\ + if((val) > (max))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, max, __FUNCTION__);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_INDEX_UPPER_NO_ASSERT_UNLOCK(val, max, mutex)\ + do{\ + if((val) > (max))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, max, __FUNCTION__);\ + if(0 != zxic_comm_mutex_unlock(mutex))\ + { \ + ZXIC_COMM_TRACE_ERROR("File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", __FILE__, __FUNCTION__, __LINE__);\ + } \ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_INDEX_UPPER_MEMORY_FREE_NO_ASSERT(val, max, ptr)\ + do{\ + if((val) > (max))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, max, __FUNCTION__);\ + ZXIC_COMM_FREE(ptr);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_INDEX_LOWER_NO_ASSERT(val,min)\ + do{\ + if((val) < (min))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, __FUNCTION__);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_INDEX_LOWER_NO_ASSERT_UNLOCK(val, min, mutex)\ + do{\ + if((val) < (min))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, __FUNCTION__);\ + if(0 != zxic_comm_mutex_unlock(mutex))\ + { \ + ZXIC_COMM_TRACE_ERROR("File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", __FILE__, __FUNCTION__, __LINE__);\ + } \ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_INDEX_LOWER_MEMORY_FREE_NO_ASSERT(val,min,ptr)\ + do{\ + if((val) < (min))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, __FUNCTION__);\ + ZXIC_COMM_FREE(ptr);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_INDEX_BOTH_NO_ASSERT(val, min, max)\ + do{\ + if(((val) < (min)) || ((val) > (max)))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_INDEX_BOTH_NO_ASSERT_UNLOCK(val, min, max, mutex)\ + do{\ + if(((val) < (min)) || ((val) > (max)))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\ + if(0 != zxic_comm_mutex_unlock(mutex))\ + { \ + ZXIC_COMM_TRACE_ERROR("File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", __FILE__, __FUNCTION__, __LINE__);\ + } \ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_INDEX_BOTH_MEMORY_FREE_NO_ASSERT(val, min, max, ptr)\ + do{\ + if(((val) < (min)) || ((val) > (max)))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\ + ZXIC_COMM_FREE(ptr);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(val0, val1)\ + do{\ + if((ZXIC_UINT32_MAX - (val0)) < (val1))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_64_NO_ASSERT(val0,val1)\ + do{\ + if((ZXIC_ULONG_MAX - (val0)) < (val1))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT_UNLOCK(val0, val1, mutex)\ +do{\ + if((ZXIC_UINT32_MAX - (val0)) < (val1))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\ + if(0 != zxic_comm_mutex_unlock(mutex))\ + {\ + ZXIC_COMM_TRACE_ERROR("File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", __FILE__, __FUNCTION__, __LINE__);\ + }\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ +}while(0) + +#define ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW_NO_ASSERT(val0, val1)\ + do{\ + if((val0) < (val1))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW_NO_ASSERT_UNLOCK(val0, val1, mutex)\ + do{\ + if((val0) < (val1))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\ + if(0 != zxic_comm_mutex_unlock(mutex))\ + {\ + ZXIC_COMM_TRACE_ERROR("File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", __FILE__, __FUNCTION__, __LINE__);\ + }\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW_NO_ASSERT(val0, val1)\ + do{\ + if(((val0) > 0) && ((ZXIC_UINT32_MAX / (val0)) < (val1)))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW_NO_ASSERT_UNLOCK(val0, val1, mutex)\ + do{\ + if(((val0) > 0) && ((ZXIC_UINT32_MAX / (val0)) < (val1)))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\ + if(0 != zxic_comm_mutex_unlock(mutex))\ + {\ + ZXIC_COMM_TRACE_ERROR("File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", __FILE__, __FUNCTION__, __LINE__);\ + }\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_INDEX_RETURN_VOID_NO_ASSERT(val,min,max)\ + do{\ + if(ZXIC_PAR_CHK_INVALID_INDEX == zxic_comm_index_check(val, min, max))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\ + return ;\ + }\ + else if(ZXIC_PAR_CHK_INVALID_RANGE == zxic_comm_index_check(val, min, max))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\ + return ;\ + }\ + }while (0) + +#define ZXIC_COMM_CHECK_INDEX_RETURN_NULL_NO_ASSERT(val,min,max)\ + do{\ + if(ZXIC_PAR_CHK_INVALID_INDEX == zxic_comm_index_check(val, min, max))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\ + return ZXIC_NULL;\ + }\ + else if(ZXIC_PAR_CHK_INVALID_RANGE == zxic_comm_index_check(val, min, max))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\ + return ZXIC_NULL;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_INDEX_CLOSE_FP_NO_ASSERT(val,min,max,fp)\ + do{\ + if(ZXIC_PAR_CHK_INVALID_INDEX == zxic_comm_index_check(val, min, max))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\ + if (ZXIC_COMM_FCLOSE(fp))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n ZXIC %s:%d !-- %s close file Fail!\n",__FILE__,__LINE__,__FUNCTION__);\ + }\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + else if(ZXIC_PAR_CHK_INVALID_RANGE == zxic_comm_index_check(val, min, max))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\ + if (ZXIC_COMM_FCLOSE(fp))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n ZXIC %s:%d !-- %s close file Fail!\n",__FILE__,__LINE__,__FUNCTION__);\ + }\ + return ZXIC_PAR_CHK_INVALID_RANGE;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_INDEX_MEMORY_FREE_NO_ASSERT(val,min,max,ptr)\ + do{\ + if(ZXIC_PAR_CHK_INVALID_INDEX == zxic_comm_index_check(val, min, max))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\ + ZXIC_COMM_FREE(ptr);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + else if(ZXIC_PAR_CHK_INVALID_RANGE == zxic_comm_index_check(val, min, max))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\ + ZXIC_COMM_FREE(ptr);\ + return ZXIC_PAR_CHK_INVALID_RANGE;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_INDEX_MEMORY_FREE2PTR_NO_ASSERT(val, min, max, ptr1, ptr2)\ + do{\ + if(ZXIC_PAR_CHK_INVALID_INDEX == zxic_comm_index_check(val, min, max))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\ + ZXIC_COMM_FREE(ptr1);\ + ZXIC_COMM_FREE(ptr2);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + else if(ZXIC_PAR_CHK_INVALID_RANGE == zxic_comm_index_check(val, min, max))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\ + ZXIC_COMM_FREE(ptr1);\ + ZXIC_COMM_FREE(ptr2);\ + return ZXIC_PAR_CHK_INVALID_RANGE;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_INDEX_MEMORY_FREE3PTR_NO_ASSERT(val, min, max, ptr1, ptr2, ptr3)\ + do{\ + if(ZXIC_PAR_CHK_INVALID_INDEX == zxic_comm_index_check(val, min, max))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\ + ZXIC_COMM_FREE(ptr1);\ + ZXIC_COMM_FREE(ptr2);\ + ZXIC_COMM_FREE(ptr3);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + else if(ZXIC_PAR_CHK_INVALID_RANGE == zxic_comm_index_check(val, min, max))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\ + ZXIC_COMM_FREE(ptr1);\ + ZXIC_COMM_FREE(ptr2);\ + ZXIC_COMM_FREE(ptr3);\ + return ZXIC_PAR_CHK_INVALID_RANGE;\ + }\ + }while(0) + +#endif + +#if ZXIC_REAL("DEV_ID & ASSERT") + +#define ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, becall)\ + do{\ + if(ZXIC_OK != rc)\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ZXIC %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,becall);\ + ZXIC_COMM_ASSERT(0);\ + return rc;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_DEV_RC_NULL(dev_id,rc,becall)\ + do{\ + if(ZXIC_OK != rc)\ + {\ + ZXIC_COMM_TRACE_ERROR("\n ZXIC %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,becall);\ + ZXIC_COMM_ASSERT(0);\ + return NULL;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_DEV_RC_UNLOCK(dev_id,rc, becall, mutex)\ + do{\ + if(ZXIC_OK != rc)\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ZXIC %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,becall);\ + if(0 != zxic_comm_mutex_unlock(mutex))\ + { \ + ZXIC_COMM_TRACE_ERROR("File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", __FILE__, __FUNCTION__, __LINE__);\ + } \ + ZXIC_COMM_ASSERT(0);\ + return rc;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_DEV_RC_CLOSE_FP(dev_id, rc, becall, fp)\ + do{\ + if(ZXIC_OK != rc)\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n ZXIC %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,becall);\ + if(ZXIC_COMM_FCLOSE(fp))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n ZXIC %s:%d !-- %s close file Fail!\n",__FILE__,__LINE__,__FUNCTION__);\ + }\ + ZXIC_COMM_ASSERT(0);\ + return rc;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_DEV_RC_MEMORY_FREE(dev_id, rc, becall, ptr)\ + do{\ + if (ZXIC_OK != rc)\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n ZXICP %s:%d [ErrorCode:0x%x], %s Call %s Fail!\n", __FILE__, __LINE__, rc, __FUNCTION__, becall);\ + ZXIC_COMM_FREE(ptr);\ + ZXIC_COMM_ASSERT(0);\ + return rc;\ + }\ + } while (0) + +#define ZXIC_COMM_CHECK_DEV_POINT(dev_id, point)\ + do{\ + if(NULL == (point))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);\ + ZXIC_COMM_ASSERT(0);\ + return ZXIC_PAR_CHK_POINT_NULL;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_DEV_POINT_MEMORY_FREE(dev_id, point, ptr)\ + do{\ + if(ZXIC_NULL == (point))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);\ + ZXIC_COMM_FREE(ptr);\ + ZXIC_COMM_ASSERT(0);\ + return ZXIC_PAR_CHK_POINT_NULL;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_DEV_POINT_EMEMORY_FREE2PTR(dev_id, point, ptr0, ptr1)\ + do{\ + if(ZXIC_NULL == (point))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);\ + ZXIC_COMM_FREE(ptr0);\ + ZXIC_COMM_FREE(ptr1);\ + ZXIC_COMM_ASSERT(0);\ + return ZXIC_PAR_CHK_POINT_NULL;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_DEV_POINT_RETURN_NULL(dev_id,point)\ + do{\ + if(NULL == (point))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);\ + ZXIC_COMM_ASSERT(0);\ + return ZXIC_NULL;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_DEV_POINT_UNLOCK(dev_id,point,mutex)\ + do{\ + if(NULL == (point))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);\ + if(0 != zxic_comm_mutex_unlock(mutex))\ + { \ + ZXIC_COMM_TRACE_ERROR("File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", __FILE__, __FUNCTION__, __LINE__);\ + } \ + ZXIC_COMM_ASSERT(0);\ + return ZXIC_PAR_CHK_POINT_NULL;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_DEV_POINT_CLOSE_FP(dev_id, point, fp)\ + do{\ + if(NULL == (point))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);\ + if (ZXIC_COMM_FCLOSE(fp))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n ZXIC %s:%d !-- %s close file Fail!\n",__FILE__,__LINE__,__FUNCTION__);\ + }\ + ZXIC_COMM_ASSERT(0);\ + return ZXIC_PAR_CHK_POINT_NULL;\ + }\ + }while(0)\ + +#define ZXIC_COMM_CHECK_DEV_INDEX(dev_id,val,min,max)\ + do{\ + if(ZXIC_PAR_CHK_INVALID_INDEX == zxic_comm_dev_index_check(dev_id, val, min, max))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\ + ZXIC_COMM_ASSERT(0);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + else if(ZXIC_PAR_CHK_INVALID_RANGE == zxic_comm_dev_index_check(dev_id, val, min, max))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\ + ZXIC_COMM_ASSERT(0);\ + return ZXIC_PAR_CHK_INVALID_RANGE;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_DEV_INDEX_UPPER(dev_id,val,max)\ + do{\ + if((val) > (max))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, max, __FUNCTION__);\ + ZXIC_COMM_ASSERT(0);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_DEV_INDEX_LOWER(dev_id,val,min)\ + do{\ + if((val) < (min))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, __FUNCTION__);\ + ZXIC_COMM_ASSERT(0);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_DEV_INDEX_BOTH(dev_id,val,min,max)\ + do{\ + if(((val) < (min)) || ((val) > (max)))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\ + ZXIC_COMM_ASSERT(0);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_DEV_INDEX_UPPER_MEMORY_FREE(dev_id,val,max,ptr)\ + do{\ + if((val) > (max))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, max, __FUNCTION__);\ + ZXIC_COMM_FREE(ptr);\ + ZXIC_COMM_ASSERT(0);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_DEV_INDEX_LOWER_MEMORY_FREE(dev_id,val,min,ptr)\ + do{\ + if((val) < (min))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, __FUNCTION__);\ + ZXIC_COMM_FREE(ptr);\ + ZXIC_COMM_ASSERT(0);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_DEV_INDEX_BOTH_MEMORY_FREE(dev_id,val,min,max,ptr)\ + do{\ + if(((val) < (min)) || ((val) > (max)))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\ + ZXIC_COMM_FREE(ptr);\ + ZXIC_COMM_ASSERT(0);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_DEV_INDEX_RETURN_NULL(dev_id,val,min,max)\ + do{\ + if(ZXIC_PAR_CHK_INVALID_INDEX == zxic_comm_index_check(val, min, max))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\ + ZXIC_COMM_ASSERT(0);\ + return ZXIC_NULL;\ + }\ + else if(ZXIC_PAR_CHK_INVALID_RANGE == zxic_comm_index_check(val, min, max))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\ + ZXIC_COMM_ASSERT(0);\ + return ZXIC_NULL;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_DEV_ID(dev_id)\ + do{\ + if(ZXIC_PAR_CHK_INVALID_INDEX == zxic_comm_index_check(dev_id, 0, zxic_comm_channel_max_get() - 1))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, dev_id, 0, zxic_comm_channel_max_get() - 1, __FUNCTION__);\ + ZXIC_COMM_ASSERT(0);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + else if(ZXIC_PAR_CHK_INVALID_RANGE == zxic_comm_index_check(dev_id, 0, zxic_comm_channel_max_get() - 1))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, dev_id, 0, zxic_comm_channel_max_get() - 1, __FUNCTION__);\ + ZXIC_COMM_ASSERT(0);\ + return ZXIC_PAR_CHK_INVALID_RANGE;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW(dev_id,val0,val1)\ + do{\ + if((ZXIC_UINT32_MAX - (val0)) < (val1))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\ + ZXIC_COMM_ASSERT(0);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_64(dev_id,val0,val1)\ + do{\ + if((ZXIC_ULONG_MAX - (val0)) < (val1))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[val0=0x%016llx] INVALID] [val1=0x%016llx] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\ + ZXIC_COMM_ASSERT(0);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_DEV_INDEX_SUB_OVERFLOW(dev_id, val0, val1)\ + do{\ + if((val0) < (val1))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\ + ZXIC_COMM_ASSERT(0);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW(dev_id,val0,val1)\ + do{\ + if(((val0) > 0) && ((ZXIC_UINT32_MAX / (val0)) < (val1)))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\ + ZXIC_COMM_ASSERT(0);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_64(dev_id, val0, val1)\ + do{\ + if(((val0) > 0) && ((0xFFFFFFFFFFFFFFFF / (val0)) < (val1)))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[val0=0x%016llx] INVALID] [val1=0x%016llx] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\ + ZXIC_COMM_ASSERT(0);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + }while(0) + + +#endif + +#if ZXIC_REAL("DEV_ID & NO ASSERT") +#define ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id,rc,becall)\ + do{\ + if(ZXIC_OK != rc)\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ZXIC %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,becall);\ + return rc;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(dev_id,rc, becall, mutex)\ + do{\ + if(ZXIC_OK != rc)\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ZXIC %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,becall);\ + if(0 != zxic_comm_mutex_unlock(mutex))\ + { \ + ZXIC_COMM_TRACE_ERROR("File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", __FILE__, __FUNCTION__, __LINE__);\ + } \ + return rc;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_DEV_RC_CLOSE_FP_NO_ASSERT(dev_id, rc, becall, fp)\ + do{\ + if(ZXIC_OK != rc)\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ZXIC %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,becall);\ + if (ZXIC_COMM_FCLOSE(fp))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n ZXIC %s:%d !-- %s close file Fail!\n",__FILE__,__LINE__,__FUNCTION__);\ + }\ + return rc;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_DEV_RC_MEMORY_FREE_NO_ASSERT(dev_id, rc, becall, ptr)\ +do{\ + if (ZXIC_OK != rc)\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n ZXICP %s:%d [ErrorCode:0x%x], %s Call %s Fail!\n", __FILE__, __LINE__, rc, __FUNCTION__, becall);\ + ZXIC_COMM_FREE(ptr);\ + return rc;\ + }\ +} while (0) +#define ZXIC_COMM_CHECK_DEV_RC_MEMORY_FREE2PTR_NO_ASSERT(dev_id, rc, becall, ptr1, ptr2)\ +do{\ + if (ZXIC_OK != rc)\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n ZXICP %s:%d [ErrorCode:0x%x], %s Call %s Fail!\n", __FILE__, __LINE__, rc, __FUNCTION__, becall);\ + ZXIC_COMM_FREE(ptr1);\ + ZXIC_COMM_FREE(ptr2);\ + return rc;\ + }\ +} while (0) +#define ZXIC_COMM_CHECK_DEV_RC_MEMORY_FREE3PTR_NO_ASSERT(dev_id, rc, becall, ptr1, ptr2, ptr3)\ +do{\ + if (ZXIC_OK != rc)\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n ZXICP %s:%d [ErrorCode:0x%x], %s Call %s Fail!\n", __FILE__, __LINE__, rc, __FUNCTION__, becall);\ + ZXIC_COMM_FREE(ptr1);\ + ZXIC_COMM_FREE(ptr2);\ + ZXIC_COMM_FREE(ptr3);\ + return rc;\ + }\ +} while (0) + +#define ZXIC_COMM_CHECK_DEV_POINT_NO_ASSERT(dev_id,point)\ + do{\ + if(NULL == (point))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);\ + return ZXIC_PAR_CHK_POINT_NULL;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_DEV_POINT_RETURN_NULL_NO_ASSERT(dev_id,point)\ + do{\ + if(ZXIC_NULL == (point))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);\ + return ZXIC_NULL;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_DEV_POINT_CLOSE_FP_NO_ASSERT(dev_id, point, fp)\ + do{\ + if(NULL == (point))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);\ + if (ZXIC_COMM_FCLOSE(fp))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n ZXIC %s:%d !-- %s close file Fail!\n",__FILE__,__LINE__,__FUNCTION__);\ + }\ + return ZXIC_PAR_CHK_POINT_NULL;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_DEV_POINT_MEMORY_FREE_NO_ASSERT(dev_id,point,ptr)\ + do{\ + if(ZXIC_NULL == (point))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);\ + ZXIC_COMM_FREE(ptr);\ + return ZXIC_PAR_CHK_POINT_NULL;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_DEV_POINT_MEMORY_FREE2PTR_NO_ASSERT(dev_id, point, ptr1, ptr2)\ + do{\ + if(ZXIC_NULL == (point))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);\ + ZXIC_COMM_FREE(ptr1);\ + ZXIC_COMM_FREE(ptr2);\ + return ZXIC_PAR_CHK_POINT_NULL;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_DEV_POINT_MEMORY_FREE3PTR_NO_ASSERT(dev_id, point, ptr1, ptr2, ptr3)\ + do{\ + if(ZXIC_NULL == (point))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);\ + ZXIC_COMM_FREE(ptr1);\ + ZXIC_COMM_FREE(ptr2);\ + ZXIC_COMM_FREE(ptr3);\ + return ZXIC_PAR_CHK_POINT_NULL;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id,val,min,max)\ + do{\ + if(ZXIC_PAR_CHK_INVALID_INDEX == zxic_comm_dev_index_check(dev_id, val, min, max))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + else if(ZXIC_PAR_CHK_INVALID_RANGE == zxic_comm_dev_index_check(dev_id, val, min, max))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\ + return ZXIC_PAR_CHK_INVALID_RANGE;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT_UNLOCK(dev_id, val, min, max, mutex)\ + do{\ + if(ZXIC_PAR_CHK_INVALID_INDEX == zxic_comm_dev_index_check(dev_id, val, min, max))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\ + if(0 != zxic_comm_mutex_unlock(mutex))\ + { \ + ZXIC_COMM_TRACE_ERROR("File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", __FILE__, __FUNCTION__, __LINE__);\ + } \ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + else if(ZXIC_PAR_CHK_INVALID_RANGE == zxic_comm_dev_index_check(dev_id, val, min, max))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\ + if(0 != zxic_comm_mutex_unlock(mutex))\ + { \ + ZXIC_COMM_TRACE_ERROR("File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", __FILE__, __FUNCTION__, __LINE__);\ + } \ + return ZXIC_PAR_CHK_INVALID_RANGE;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_DEV_INDEX_UPPER_NO_ASSERT(dev_id,val,max)\ + do{\ + if((val) > (max))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, max, __FUNCTION__);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_DEV_INDEX_UPPER_NO_ASSERT_UNLOCK(dev_id, val, max, mutex)\ + do{\ + if((val) > (max))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, max, __FUNCTION__);\ + if(0 != zxic_comm_mutex_unlock(mutex))\ + { \ + ZXIC_COMM_TRACE_ERROR("File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", __FILE__, __FUNCTION__, __LINE__);\ + } \ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_DEV_INDEX_UPPER_MEMORY_FREE_NO_ASSERT(dev_id,val,max,ptr)\ + do{\ + if((val) > (max))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, max, __FUNCTION__);\ + ZXIC_COMM_FREE(ptr);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + }while(0) + + +#define ZXIC_COMM_CHECK_DEV_INDEX_LOWER_NO_ASSERT(dev_id,val,min)\ + do{\ + if((val) < (min))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, __FUNCTION__);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_DEV_INDEX_LOWER_NO_ASSERT_UNLOCK(dev_id, val, min, mutex)\ + do{\ + if((val) < (min))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, __FUNCTION__);\ + if(0 != zxic_comm_mutex_unlock(mutex))\ + { \ + ZXIC_COMM_TRACE_ERROR("File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", __FILE__, __FUNCTION__, __LINE__);\ + } \ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_DEV_INDEX_LOWER_MEMORY_FREE_NO_ASSERT(dev_id,val,min,ptr)\ + do{\ + if((val) < (min))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, __FUNCTION__);\ + ZXIC_COMM_FREE(ptr);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + }while(0) + + +#define ZXIC_COMM_CHECK_DEV_INDEX_BOTH_NO_ASSERT(dev_id,val,min,max)\ + do{\ + if(((val) < (min)) || ((val) > (max)))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_DEV_INDEX_BOTH_NO_ASSERT_UNLOCK(dev_id, val, min, max, mutex)\ + do{\ + if(((val) < (min)) || ((val) > (max)))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\ + if(0 != zxic_comm_mutex_unlock(mutex))\ + { \ + ZXIC_COMM_TRACE_ERROR("File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", __FILE__, __FUNCTION__, __LINE__);\ + } \ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_DEV_INDEX_BOTH_MEMORY_FREE_NO_ASSERT(dev_id,val,min,max,ptr)\ + do{\ + if(((val) < (min)) || ((val) > (max)))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\ + ZXIC_COMM_FREE(ptr);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_DEV_INDEX_RETURN_NULL_NO_ASSERT(dev_id,val,min,max)\ + do{\ + if(ZXIC_PAR_CHK_INVALID_INDEX == zxic_comm_index_check(val, min, max))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\ + return ZXIC_NULL;\ + }\ + else if(ZXIC_PAR_CHK_INVALID_RANGE == zxic_comm_index_check(val, min, max))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\ + return ZXIC_NULL;\ + }\ + }while(0) + + +#define ZXIC_COMM_CHECK_DEV_INDEX_MEMORY_FREE_NO_ASSERT(dev_id,val,min,max,ptr)\ + do{\ + if(ZXIC_PAR_CHK_INVALID_INDEX == zxic_comm_dev_index_check(dev_id, val, min, max))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\ + ZXIC_COMM_FREE(ptr);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + else if(ZXIC_PAR_CHK_INVALID_RANGE == zxic_comm_dev_index_check(dev_id, val, min, max))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\ + ZXIC_COMM_FREE(ptr);\ + return ZXIC_PAR_CHK_INVALID_RANGE;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_DEV_INDEX_MEMORY_FREE2PTR_NO_ASSERT(dev_id, val, min, max, ptr1, ptr2)\ + do{\ + if(ZXIC_PAR_CHK_INVALID_INDEX == zxic_comm_dev_index_check(dev_id, val, min, max))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\ + ZXIC_COMM_FREE(ptr1);\ + ZXIC_COMM_FREE(ptr2);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + else if(ZXIC_PAR_CHK_INVALID_RANGE == zxic_comm_dev_index_check(dev_id, val, min, max))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\ + ZXIC_COMM_FREE(ptr1);\ + ZXIC_COMM_FREE(ptr2);\ + return ZXIC_PAR_CHK_INVALID_RANGE;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_DEV_INDEX_MEMORY_FREE3PTR_NO_ASSERT(dev_id, val, min, max, ptr1, ptr2, ptr3)\ + do{\ + if(ZXIC_PAR_CHK_INVALID_INDEX == zxic_comm_dev_index_check(dev_id, val, min, max))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\ + ZXIC_COMM_FREE(ptr1);\ + ZXIC_COMM_FREE(ptr2);\ + ZXIC_COMM_FREE(ptr3);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + else if(ZXIC_PAR_CHK_INVALID_RANGE == zxic_comm_dev_index_check(dev_id, val, min, max))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\ + ZXIC_COMM_FREE(ptr1);\ + ZXIC_COMM_FREE(ptr2);\ + ZXIC_COMM_FREE(ptr3);\ + return ZXIC_PAR_CHK_INVALID_RANGE;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_DEV_ID_NO_ASSERT(dev_id)\ + do{\ + if(ZXIC_PAR_CHK_INVALID_INDEX == zxic_comm_index_check(dev_id, 0, zxic_comm_channel_max_get() - 1))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, dev_id, 0, zxic_comm_channel_max_get() - 1, __FUNCTION__);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + else if(ZXIC_PAR_CHK_INVALID_RANGE == zxic_comm_index_check(dev_id, 0, zxic_comm_channel_max_get() - 1))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, dev_id, 0, zxic_comm_channel_max_get() - 1, __FUNCTION__);\ + return ZXIC_PAR_CHK_INVALID_RANGE;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_DEV_ID_RETURN_NULL_NO_ASSERT(dev_id)\ + do{\ + if(ZXIC_PAR_CHK_INVALID_INDEX == zxic_comm_index_check(dev_id, 0, zxic_comm_channel_max_get() - 1))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, dev_id, 0, zxic_comm_channel_max_get() - 1, __FUNCTION__);\ + return ZXIC_NULL;\ + }\ + else if(ZXIC_PAR_CHK_INVALID_RANGE == zxic_comm_index_check(dev_id, 0, zxic_comm_channel_max_get() - 1))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, dev_id, 0, zxic_comm_channel_max_get() - 1, __FUNCTION__);\ + return ZXIC_NULL;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_DEV_INDEX_SUB_OVERFLOW_NO_ASSERT(dev_id, val0, val1)\ + do{\ + if((val0) < (val1))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_DEV_INDEX_SUB_OVERFLOW_NO_ASSERT_UNLOCK(dev_id, val0, val1, mutex)\ + do{\ + if((val0) < (val1))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\ + if(0 != zxic_comm_mutex_unlock(mutex))\ + {\ + ZXIC_COMM_TRACE_ERROR("File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", __FILE__, __FUNCTION__, __LINE__);\ + }\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(dev_id,val0,val1)\ + do{\ + if((ZXIC_UINT32_MAX - (val0)) < (val1))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT_UNLOCK(dev_id,val0,val1,mutex)\ + do{\ + if((ZXIC_UINT32_MAX - (val0)) < (val1))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\ + if(0 != zxic_comm_mutex_unlock(mutex))\ + {\ + ZXIC_COMM_TRACE_ERROR("File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", __FILE__, __FUNCTION__, __LINE__);\ + }\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_64_NO_ASSERT(dev_id,val0,val1)\ + do{\ + if((ZXIC_ULONG_MAX - (val0)) < (val1))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[val0=0x%016llx] INVALID] [val1=0x%016llx] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id,val0,val1)\ + do{\ + if(((val0) > 0) && ((ZXIC_UINT32_MAX / (val0)) < (val1)))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT_UNLOCK(dev_id,val0,val1,mutex)\ + do{\ + if(((val0) > 0) && ((ZXIC_UINT32_MAX / (val0)) < (val1)))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\ + if(0 != zxic_comm_mutex_unlock(mutex))\ + {\ + ZXIC_COMM_TRACE_ERROR("File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", __FILE__, __FUNCTION__, __LINE__);\ + }\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_64_NO_ASSERT(dev_id,val0,val1)\ + do{\ + if(((val0) > 0) && ((ZXIC_ULONG_MAX/ (val0)) < (val1)))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + }while(0) + +#endif +#if ZXIC_REAL("return no code") +#define ZXIC_COMM_CHECK_RC_RETURN_NONE(rc,becall)\ + do{\ + if(ZXIC_OK != rc)\ + {\ + ZXIC_COMM_TRACE_ERROR("\n ZXIC %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,becall);\ + ZXIC_COMM_ASSERT(0);\ + return;\ + }\ + }while(0) + +/* 不带返回值,用于VOID类型函数 */ +#define ZXIC_COMM_CHECK_POINT_RETURN_NONE(point)\ + do{\ + if(ZXIC_NULL == (point))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);\ + ZXIC_COMM_ASSERT(0);\ + return;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_RETURN_NONE(val0,val1)\ + do{\ + if((ZXIC_UINT32_MAX - (val0)) < (val1))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\ + ZXIC_COMM_ASSERT(0);\ + return;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW_RETURN_NONE(val0,val1)\ + do{\ + if((val0) < (val1))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\ + ZXIC_COMM_ASSERT(0);\ + return;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW_RETURN_NONE(val0,val1)\ + do{\ + if(((val0) > 0) && ((ZXIC_UINT32_MAX / (val0)) < (val1)))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\ + ZXIC_COMM_ASSERT(0);\ + return;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_INDEX_UPPER_RETURN_NONE(val,max)\ + do{\ + if((val) > (max))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, max, __FUNCTION__);\ + ZXIC_COMM_ASSERT(0);\ + return;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_INDEX_LOWER_RETURN_NONE(val,min)\ + do{\ + if((val) < (min))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, __FUNCTION__);\ + ZXIC_COMM_ASSERT(0);\ + return;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_INDEX_BOTH_RETURN_NONE(val,min,max)\ + do{\ + if(((val) < (min)) || ((val) > (max)))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\ + ZXIC_COMM_ASSERT(0);\ + return;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_INDEX_UPPER_MEMORY_FREE_RETURN_NONE(val,max,ptr)\ + do{\ + if((val) > (max))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, max, __FUNCTION__);\ + ZXIC_COMM_FREE(ptr);\ + ZXIC_COMM_ASSERT(0);\ + return;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_INDEX_LOWER_MEMORY_FREE_RETURN_NONE(val,min,ptr)\ + do{\ + if((val) < (min))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, __FUNCTION__);\ + ZXIC_COMM_FREE(ptr);\ + ZXIC_COMM_ASSERT(0);\ + return;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_INDEX_BOTH_MEMORY_FREE_RETURN_NONE(val,min,max,ptr)\ + do{\ + if(((val) < (min)) || ((val) > (max)))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\ + ZXIC_COMM_FREE(ptr);\ + ZXIC_COMM_ASSERT(0);\ + return;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_DEV_RC_RETURN_NONE(dev_id, rc, becall)\ + do{\ + if(ZXIC_OK != rc)\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ZXIC %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,becall);\ + ZXIC_COMM_ASSERT(0);\ + return;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_DEV_POINT_RETURN_NONE(dev_id,point)\ + do{\ + if(NULL == (point))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);\ + ZXIC_COMM_ASSERT(0);\ + return;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_DEV_INDEX_UPPER_RETURN_NONE(dev_id,val,max)\ + do{\ + if((val) > (max))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, max, __FUNCTION__);\ + ZXIC_COMM_ASSERT(0);\ + return;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_DEV_INDEX_LOWER_RETURN_NONE(dev_id,val,min)\ + do{\ + if((val) < (min))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, __FUNCTION__);\ + ZXIC_COMM_ASSERT(0);\ + return;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_DEV_INDEX_BOTH_RETURN_NONE(dev_id,val,min,max)\ + do{\ + if(((val) < (min)) || ((val) > (max)))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\ + ZXIC_COMM_ASSERT(0);\ + return;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_DEV_INDEX_UPPER_MEMORY_FREE_RETURN_NONE(dev_id,val,max,ptr)\ + do{\ + if((val) > (max))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, max, __FUNCTION__);\ + ZXIC_COMM_FREE(ptr);\ + ZXIC_COMM_ASSERT(0);\ + return;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_DEV_INDEX_LOWER_MEMORY_FREE_RETURN_NONE(dev_id,val,min,ptr)\ + do{\ + if((val) < (min))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, __FUNCTION__);\ + ZXIC_COMM_FREE(ptr);\ + ZXIC_COMM_ASSERT(0);\ + return;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_DEV_INDEX_BOTH_MEMORY_FREE_RETURN_NONE(dev_id,val,min,max,ptr)\ + do{\ + if(((val) < (min)) || ((val) > (max)))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\ + ZXIC_COMM_FREE(ptr);\ + ZXIC_COMM_ASSERT(0);\ + return;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_RETURN_NONE(dev_id,val0,val1)\ + do{\ + if((ZXIC_UINT32_MAX - (val0)) < (val1))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\ + ZXIC_COMM_ASSERT(0);\ + return;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_64_RETURN_NONE(dev_id,val0,val1)\ + do{\ + if((ZXIC_ULONG_MAX - (val0)) < (val1))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[val0=0x%016llx] INVALID] [val1=0x%016llx] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\ + ZXIC_COMM_ASSERT(0);\ + return;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_DEV_INDEX_SUB_OVERFLOW_RETURN_NONE(dev_id, val0, val1)\ + do{\ + if((val0) < (val1))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\ + ZXIC_COMM_ASSERT(0);\ + return;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_RETURN_NONE(dev_id,val0,val1)\ + do{\ + if(((val0) > 0) && ((ZXIC_UINT32_MAX / (val0)) < (val1)))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\ + ZXIC_COMM_ASSERT(0);\ + return;\ + }\ + }while(0) +#endif + +#if ZXIC_REAL("return no code & no assert") +#define ZXIC_COMM_CHECK_RC_RETURN_NONE_NO_ASSERT(rc,becall)\ + do{\ + if(ZXIC_OK != rc)\ + {\ + ZXIC_COMM_TRACE_ERROR("\n ZXIC %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,becall);\ + return;\ + }\ + }while(0) + +/* 不带返回值,用于VOID类型函数 */ +#define ZXIC_COMM_CHECK_POINT_RETURN_NONE_NO_ASSERT(point)\ + do{\ + if(ZXIC_NULL == (point))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);\ + return;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_RETURN_NONE_NO_ASSERT(val0,val1)\ + do{\ + if((ZXIC_UINT32_MAX - (val0)) < (val1))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\ + return;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW_RETURN_NONE_NO_ASSERT(val0,val1)\ + do{\ + if((val0) < (val1))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\ + return;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW_RETURN_NONE_NO_ASSERT(val0,val1)\ + do{\ + if(((val0) > 0) && ((ZXIC_UINT32_MAX / (val0)) < (val1)))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\ + return;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_INDEX_UPPER_RETURN_NONE_NO_ASSERT(val,max)\ + do{\ + if((val) > (max))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, max, __FUNCTION__);\ + return;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_INDEX_LOWER_RETURN_NONE_NO_ASSERT(val,min)\ + do{\ + if((val) < (min))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, __FUNCTION__);\ + return;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_INDEX_BOTH_RETURN_NONE_NO_ASSERT(val,min,max)\ + do{\ + if(((val) < (min)) || ((val) > (max)))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\ + return;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_INDEX_UPPER_MEMORY_FREE_RETURN_NONE_NO_ASSERT(val,max,ptr)\ + do{\ + if((val) > (max))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, max, __FUNCTION__);\ + ZXIC_COMM_FREE(ptr);\ + return;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_INDEX_LOWER_MEMORY_FREE_RETURN_NONE_NO_ASSERT(val,min,ptr)\ + do{\ + if((val) < (min))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, __FUNCTION__);\ + ZXIC_COMM_FREE(ptr);\ + return;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_INDEX_BOTH_MEMORY_FREE_RETURN_NONE_NO_ASSERT(val,min,max,ptr)\ + do{\ + if(((val) < (min)) || ((val) > (max)))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\ + ZXIC_COMM_FREE(ptr);\ + return;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_DEV_RC_RETURN_NONE_NO_ASSERT(dev_id, rc, becall)\ + do{\ + if(ZXIC_OK != rc)\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ZXIC %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,becall);\ + return;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_DEV_POINT_RETURN_NONE_NO_ASSERT(dev_id,point)\ + do{\ + if(NULL == (point))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);\ + return;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_DEV_INDEX_UPPER_RETURN_NONE_NO_ASSERT(dev_id,val,max)\ + do{\ + if((val) > (max))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, max, __FUNCTION__);\ + return;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_DEV_INDEX_LOWER_RETURN_NONE_NO_ASSERT(dev_id,val,min)\ + do{\ + if((val) < (min))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, __FUNCTION__);\ + return;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_DEV_INDEX_BOTH_RETURN_NONE_NO_ASSERT(dev_id,val,min,max)\ + do{\ + if(((val) < (min)) || ((val) > (max)))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\ + return;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_DEV_INDEX_UPPER_MEMORY_FREE_RETURN_NONE_NO_ASSERT(dev_id,val,max,ptr)\ + do{\ + if((val) > (max))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, max, __FUNCTION__);\ + ZXIC_COMM_FREE(ptr);\ + return;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_DEV_INDEX_LOWER_MEMORY_FREE_RETURN_NONE_NO_ASSERT(dev_id,val,min,ptr)\ + do{\ + if((val) < (min))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, __FUNCTION__);\ + ZXIC_COMM_FREE(ptr);\ + return;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_DEV_INDEX_BOTH_MEMORY_FREE_RETURN_NONE_NO_ASSERT(dev_id,val,min,max,ptr)\ + do{\ + if(((val) < (min)) || ((val) > (max)))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\ + ZXIC_COMM_FREE(ptr);\ + return;\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_RETURN_NONE_NO_ASSERT(dev_id,val0,val1)\ + do{\ + if((ZXIC_UINT32_MAX - (val0)) < (val1))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\ + return;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_DEV_INDEX_SUB_OVERFLOW_RETURN_NONE_NO_ASSERT(dev_id, val0, val1)\ + do{\ + if((val0) < (val1))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\ + return;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_RETURN_NONE_NO_ASSERT(dev_id,val0,val1)\ + do{\ + if(((val0) > 0) && ((ZXIC_UINT32_MAX / (val0)) < (val1)))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\ + return;\ + }\ + }while(0) +#endif + +#if ZXIC_REAL("no return") +#define ZXIC_COMM_CHECK_RC_NONE(rc,becall)\ + do{\ + if(ZXIC_OK != rc)\ + {\ + ZXIC_COMM_TRACE_ERROR("\n ZXIC %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,becall);\ + ZXIC_COMM_ASSERT(0);\ + }\ + }while(0) + +/* 不带返回值,用于VOID类型函数 */ +#define ZXIC_COMM_CHECK_POINT_NONE(point)\ + do{\ + if(ZXIC_NULL == (point))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);\ + ZXIC_COMM_ASSERT(0);\ + }\ + }while(0) + +/* 不带返回值,用于VOID类型函数 */ +#define ZXIC_COMM_CHECK_INDEX_NONE(val,min,max)\ + do{\ + if (ZXIC_OK != zxic_comm_index_check(val, min, max));\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_INDEX_UPPER_NONE(val,max)\ + do{\ + if((val) > (max))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, max, __FUNCTION__);\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NONE(val0,val1)\ + do{\ + if((ZXIC_UINT32_MAX - (val0)) < (val1))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\ + ZXIC_COMM_ASSERT(0);\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW_NONE(val0,val1)\ + do{\ + if((val0) < (val1))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\ + ZXIC_COMM_ASSERT(0);\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW_NONE(val0,val1)\ + do{\ + if(((val0) > 0) && ((ZXIC_UINT32_MAX / (val0)) < (val1)))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\ + ZXIC_COMM_ASSERT(0);\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_INDEX_LOWER_NONE(val,min)\ + do{\ + if((val) < (min))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, __FUNCTION__);\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_INDEX_BOTH_NONE(val,min,max)\ + do{\ + if(((val) < (min)) || ((val) > (max)))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_DEV_RC_NONE(dev_id, rc, becall)\ + do{\ + if(ZXIC_OK != rc)\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ZXIC %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,becall);\ + ZXIC_COMM_ASSERT(0);\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_DEV_POINT_NONE(dev_id,point)\ + do{\ + if(NULL == (point))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);\ + ZXIC_COMM_ASSERT(0);\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_DEV_INDEX_NONE(dev_id,val,min,max)\ + do{\ + if(ZXIC_PAR_CHK_INVALID_INDEX == zxic_comm_dev_index_check(dev_id, val, min, max))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\ + }\ + else if(ZXIC_PAR_CHK_INVALID_RANGE == zxic_comm_dev_index_check(dev_id, val, min, max))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_DEV_INDEX_UPPER_NONE(dev_id,val,max)\ + do{\ + if((val) > (max))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, max, __FUNCTION__);\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_DEV_INDEX_LOWER_NONE(dev_id,val,min)\ + do{\ + if((val) < (min))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, __FUNCTION__);\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_DEV_INDEX_BOTH_NONE(dev_id,val,min,max)\ + do{\ + if(((val) < (min)) || ((val) > (max)))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\ + }\ + }while(0) +#define ZXIC_COMM_CHECK_DEV_RC_INT(dev_id,check_rc,rc,becall)\ + do{\ + if(check_rc < 0)\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ICM %s:%d [ErrorCode:0x%x] [rc:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,check_rc, rc,__FUNCTION__,becall);\ + ZXIC_COMM_ASSERT(0);\ + return rc;\ + }\ + }while(0) + +#endif +#if ZXIC_REAL("no print") +#define ZXIC_COMM_CHECK_RC_NO_PRINT(rc,error_code)\ +do{\ + if(ZXIC_OK != rc)\ + {\ + ZXIC_COMM_ASSERT(0);\ + return error_code;\ + }\ +}while(0) +#define ZXIC_COMM_CHECK_RC_UNLOCK_NO_PRINT(rc, p_mutex, error_code)\ +do{\ + if(ZXIC_OK != rc)\ + {\ + (ZXIC_VOID)zxic_comm_mutex_unlock(p_mutex);\ + ZXIC_COMM_ASSERT(0);\ + return error_code;\ + }\ +}while(0) + +#define ZXIC_COMM_CHECK_POINT_NO_PRINT(point)\ +do{\ + if(ZXIC_NULL == (point))\ + {\ + ZXIC_COMM_ASSERT(0);\ + return ZXIC_PAR_CHK_POINT_NULL;\ + }\ +}while(0) +#define ZXIC_COMM_CHECK_POINT_NO_PRINT_UNLOCK(point,p_mutex)\ +do{\ + if(ZXIC_NULL == (point))\ + {\ + (ZXIC_VOID)zxic_comm_mutex_unlock(p_mutex);\ + ZXIC_COMM_ASSERT(0);\ + return ZXIC_PAR_CHK_POINT_NULL;\ + }\ +}while(0) + +#define ZXIC_COMM_CHECK_RC_POINT_NO_PRINT(point,rc)\ + do{\ + if(ZXIC_NULL == (point))\ + {\ + ZXIC_COMM_ASSERT(0);\ + return rc;\ + }\ + }while(0) + +#define ZXIC_COMM_CHECK_INDEX_NO_PRINT_UNLOCK(val,min,max,p_mutex)\ +do{\ + if(ZXIC_PAR_CHK_INVALID_INDEX == zxic_comm_index_check(val, min, max))\ + {\ + (ZXIC_VOID)zxic_comm_mutex_unlock(p_mutex);\ + ZXIC_COMM_ASSERT(0);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + else if(ZXIC_PAR_CHK_INVALID_RANGE == zxic_comm_index_check(val, min, max))\ + {\ + (ZXIC_VOID)zxic_comm_mutex_unlock(p_mutex);\ + ZXIC_COMM_ASSERT(0);\ + return ZXIC_PAR_CHK_INVALID_RANGE;\ + }\ +}while(0) +#define ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW_NO_PRINT_UNLOCK(val0, val1, mutex)\ + do{\ + if((val0) < (val1))\ + {\ + if(0 != zxic_comm_mutex_unlock(mutex))\ + {\ + ZXIC_COMM_ASSERT(0);\ + return ZXIC_PAR_CHK_INVALID_PARA;\ + }\ + ZXIC_COMM_ASSERT(0);\ + return ZXIC_PAR_CHK_INVALID_INDEX;\ + }\ + }while(0) + +#endif +#endif /* ZXIC_REAL("参数检查") */ + + +//#ifdef ZXIC_FOR_LLT +#if ZXIC_REAL("UT_TEST") +#define ZXIC_CHECK_DEV_UT_RC(dev_id, rc, val, becall)\ + do{\ + if (val != rc)\ + {\ + ZXIC_COMM_PRINT("\n ZXICP %s:%d [ErrorCode:0x%x], %s Call %s Fail!\n", __FILE__, __LINE__, rc, __FUNCTION__, becall);\ + zxic_comm_ut_detail_trace_dev_error(dev_id, "\n ZXICP %s:%d [ErrorCode:0x%x], %s Call %s Fail!\n", __FILE__, __LINE__, rc, __FUNCTION__, becall);\ + return ZXIC_E_LLT_CHECK;\ + }\ + } while (0) +#endif + +#if ZXIC_REAL("字节序") +/* DWORD变量字节序转换 */ +#define ZXIC_COMM_CONVERT32(dw_data) \ + ((((dw_data)&0xff)<<24)|(((dw_data)&0xff00)<<8)\ + |(((dw_data)&0xff0000)>>8)|(((dw_data)&0xff000000)>>24)) +/* WORD变量字节序转换 */ +#define ZXIC_COMM_CONVERT16(w_data) \ + ((((w_data)&0xff)<<8)|(((w_data)&0xff00)>>8)) + +/* WORD变量字节序转换 */ +#define ZXIC_COMM_CONVERT32_16b(w_data) \ + ((((w_data)&0xffff)<<16)|(((w_data)&0xffff0000)>>16)) + +ZXIC_VOID zxic_comm_swap_en_set(ZXIC_UINT32 enable); +ZXIC_RTN32 zxic_comm_swap_en_get(ZXIC_VOID); +ZXIC_RTN32 zxic_comm_is_big_endian(ZXIC_VOID); +ZXIC_RTN32 zxic_comm_endian_prt(ZXIC_VOID); +ZXIC_VOID zxic_comm_swap(ZXIC_UINT8 *p_uc_data, ZXIC_UINT32 dw_byte_len); +ZXIC_VOID zxic_comm_swap_16b(ZXIC_UINT8 *p_uc_data, ZXIC_UINT32 dw_byte_len); +ZXIC_UINT64 ZXIC_COMM_COUNTER64_BUILD(ZXIC_UINT32 hi, ZXIC_UINT32 lo); +#endif + +#if ZXIC_REAL("内存") +ZXIC_UINT32 zxic_comm_get_malloc_num(ZXIC_VOID); +ZXIC_UINT32 zxic_comm_get_malloc_size(ZXIC_VOID); +ZXIC_VOID zxic_clr_malloc_num(ZXIC_VOID); + +#define ZXIC_COMM_FREE(p_data) \ +do{\ + ic_comm_free_record();\ + kfree(p_data);\ + p_data = ZXIC_NULL; \ +}while(0) + +#define ZXIC_COMM_MALLOC(size) ic_comm_malloc_memory(size) + +#define ZXIC_COMM_ALLOC_MEMORY(ptr,size) \ + do{\ + (ptr) = ZXIC_COMM_MALLOC(size);\ + ZXIC_COMM_CHECK_POINT(ptr);\ + ZXIC_COMM_MEMSET((ptr),0,size);\ + }while(0) +#define ZXIC_COMM_ALLOC_MEMORY_DEV(dev_id,ptr,size) \ + do{\ + (ptr) = ZXIC_COMM_MALLOC(size);\ + ZXIC_COMM_CHECK_DEV_POINT(dev_id,ptr);\ + ZXIC_COMM_MEMSET((ptr),0,size);\ + }while(0) + + +#endif + +#if ZXIC_REAL("延时") +// ZXIC_VOID zxic_comm_sleep(ZXIC_UINT32 milliseconds); +ZXIC_VOID zxic_comm_msleep(ZXIC_UINT32 millisecond); +ZXIC_VOID zxic_comm_udelay(ZXIC_UINT32 microseconds); +ZXIC_VOID zxic_comm_delay(ZXIC_UINT32 milliseconds); +ZXIC_DOUBLE zxic_comm_get_ticks_s(ZXIC_VOID); +ZXIC_DOUBLE zxic_comm_get_ticks_ms(ZXIC_VOID); +ZXIC_DOUBLE zxic_get_ticks_uses(ZXIC_VOID); +#endif + +#if ZXIC_REAL("bit操作") + +/* ZXIC_UINT32 写某几bit的值 */ +#define ZXIC_COMM_MASK_BIT(intType,_bitNum_)\ + (( intType )( 0x1U << (_bitNum_) )) + +#define ZXIC_COMM_GET_BIT_MASK( _intType_, _bitQnt_ )\ + ( (_intType_)( ( (_bitQnt_) < 32 ) \ + ? ( (_intType_) ZXIC_COMM_MASK_BIT( _intType_ , ( (_bitQnt_) & 0x1F ) ) - 1 ) \ + : ((_intType_)(0xffffffff)) ) ) + +#define ZXIC_COMM_UINT32_WRITE_BITS( _uiDst_, _uiSrc_, _uiStartPos_, _uiLen_ )\ +do{\ + ( _uiDst_ ) = ( ( _uiDst_ ) & ~( ZXIC_COMM_GET_BIT_MASK( ZXIC_UINT32 , ( _uiLen_ ) ) << ( _uiStartPos_ ) ) ) |\ + ( ( ( _uiSrc_ ) & ZXIC_COMM_GET_BIT_MASK( ZXIC_UINT32 , ( _uiLen_ ) ) ) << ( _uiStartPos_ ) );\ +}while(0) + +#define ZXIC_COMM_UINT32_WRITE_BITS_ZERO(_uiDst_, _uiStartPos_, _uiLen_ )\ +do{\ + ( _uiDst_ ) = ( ( _uiDst_ ) & ~( ZXIC_COMM_GET_BIT_MASK( ZXIC_UINT32 , ( _uiLen_ ) ) << ( _uiStartPos_ ) ) );\ +}while(0) + +#define ZXIC_COMM_UINT32_GET_BITS(_uiDst_ ,_uiSrc_, _uiStartPos_, _uiLen_)\ +do{\ + ( _uiDst_ ) =( ( (_uiSrc_) >> (_uiStartPos_) ) & \ + ( ZXIC_COMM_GET_BIT_MASK( ZXIC_UINT32 , (_uiLen_) ) ) );\ + }while(0) + +#define ZXIC_COMM_UINT32_GET_RETURN_BITS(_uiSrc_, _uiStartPos_, _uiLen_)\ + ( ( (_uiSrc_) >> (_uiStartPos_) ) & \ + ( ZXIC_COMM_GET_BIT_MASK( ZXIC_UINT32 , (_uiLen_) ) ) )\ + +/* ZXIC_UINT64 写某几bit的值 */ +#define ZXIC_COMM_MASK_BIT_64(intType,_bitNum_)\ + (( intType )( 0x1ULL << (_bitNum_) )) + +#define ZXIC_COMM_GET_64_BIT_MASK( _intType_, _bitQnt_ )\ + ( (_intType_)( ( (_bitQnt_) < 64 ) \ + ? ( (_intType_) ZXIC_COMM_MASK_BIT_64( _intType_ , ( (_bitQnt_) & 0x3F ) ) - 1 ) \ + : ((_intType_)(0xFFFFFFFFFFFFFFFFULL)) ) ) + +#define ZXIC_COMM_UINT64_WRITE_BITS( _uiDst_, _uiSrc_, _uiStartPos_, _uiLen_ )\ +do{\ + ( _uiDst_ ) = ( ( _uiDst_ ) & ~( ZXIC_COMM_GET_64_BIT_MASK( ZXIC_UINT64 , ( _uiLen_ ) ) << ( _uiStartPos_ ) ) ) |\ + ( ( ( _uiSrc_ ) & ZXIC_COMM_GET_64_BIT_MASK( ZXIC_UINT64 , ( _uiLen_ ) ) ) << ( _uiStartPos_ ) );\ +}while(0) + +/* Base type for declarations */ +#define ZXIC_COMM_BITDCL ZXIC_UINT32 +#define ZXIC_COMM_BITWID (32) + +/* (internal) Number of ZXICP_BITDCLs needed to contain _max bits */ +#define NPE_BITDCLSIZE(_max) (((_max) + ZXIC_COMM_BITWID - 1) / ZXIC_COMM_BITWID) + +/* Size for giving to malloc and memset to handle _max bits */ +#define ZXIC_COMM_BITALLOCSIZE(_max) (NPE_BITDCLSIZE(_max) * sizeof (ZXIC_COMM_BITDCL)) + + +/* (internal) Generic operation macro on bit array _a, with bit _b */ +#define NPE_BITOP(_a, _b, _op) (((_a)[(_b) / ZXIC_COMM_BITWID]) _op (1U << ((_b) % ZXIC_COMM_BITWID))) + +/* Specific operations */ +#define ZXIC_COMM_BITGET(_a, _b) NPE_BITOP(_a, _b, &) +#define ZXIC_COMM_BITSET(_a, _b) NPE_BITOP(_a, _b, |=) +#define ZXIC_COMM_BITCLR(_a, _b) NPE_BITOP(_a, _b, &= ~) + + +ZXIC_RTN32 zxic_comm_bit_count(ZXIC_UINT32 data); +ZXIC_RTN32 zxic_comm_read_bits(ZXIC_UINT8 * p_base, ZXIC_UINT32 base_size_bit, ZXIC_UINT32 * p_data, ZXIC_UINT32 start_bit, ZXIC_UINT32 end_bit); +ZXIC_RTN32 zxic_comm_write_bits(ZXIC_UINT8 * p_base, ZXIC_UINT32 base_size_bit, ZXIC_UINT32 data, ZXIC_UINT32 start_bit, ZXIC_UINT32 end_bit); +ZXIC_RTN32 zxic_comm_write_bits_ex(ZXIC_UINT8 * p_base, ZXIC_UINT32 base_size_bit, ZXIC_UINT32 data, ZXIC_UINT32 msb_start_pos, ZXIC_UINT32 len); +ZXIC_RTN32 zxic_comm_read_bits_ex(ZXIC_UINT8 * p_base, ZXIC_UINT32 base_size_bit, ZXIC_UINT32 * p_data, ZXIC_UINT32 msb_start_pos, ZXIC_UINT32 len); +ZXIC_RTN32 zxic_comm_write_bits_op(ZXIC_UINT8* p_src_dat, ZXIC_UINT32 src_size_bit, ZXIC_UINT32 input_data, ZXIC_UINT32 start_bit, ZXIC_UINT32 end_bit); +ZXIC_RTN32 zxic_comm_read_bits_op(ZXIC_UINT8* p_src_dat, ZXIC_UINT32 src_size_bit, ZXIC_UINT32* p_out_data, ZXIC_UINT32 start_bit, ZXIC_UINT32 end_bit); +#endif + +#if ZXIC_REAL("算数运算") +ZXIC_UINT64 zxic_comm_get_gcd (ZXIC_UINT64 a, ZXIC_UINT64 b); +ZXIC_RTN32 zxic_comm_multi_big_integer(ZXIC_CONST ZXIC_CHAR* num1,ZXIC_CONST ZXIC_CHAR* num2,ZXIC_CHAR* str_num); +ZXIC_RTN32 zxic_comm_div_big_integer(ZXIC_CONST ZXIC_CHAR *num1,ZXIC_CONST ZXIC_CHAR *num2,ZXIC_UINT32 *quo_val); +ZXIC_SINT32 zxic_comm_sub_stract(ZXIC_SINT32 *p1,ZXIC_SINT32 *p2,ZXIC_SINT32 len1,ZXIC_SINT32 len2 ); +ZXIC_SINT32 zxic_comm_cmpm_calc(ZXIC_UINT64 cm_cal, ZXIC_UINT64 pm_cal, ZXIC_UINT32* cm, ZXIC_UINT32* pm); +ZXIC_VOID zxic_comm_pm_cm_cal(ZXIC_UINT64 cm_y, ZXIC_UINT64 pm_y, ZXIC_UINT32* cm, ZXIC_UINT32* pm); +#endif + +#if ZXIC_REAL("字符串") +ZXIC_RTN32 zxic_comm_strcasecmp(ZXIC_CHAR *str1, ZXIC_CHAR* str2); +ZXIC_UINT8 zxic_comm_char_to_hex(ZXIC_UINT8 c); +ZXIC_DWORD zxic_comm_ipaddr_to_dword(ZXIC_CONST ZXIC_CHAR *p_addr); +ZXIC_RTN32 zxic_comm_char_to_number(ZXIC_CHAR a, ZXIC_CHAR b, ZXIC_UINT8 *number); +ZXIC_CHAR *zxic_comm_strlower(ZXIC_CHAR *str); +ZXIC_RTN32 ic_comm_check_str_size(ZXIC_CHAR* str); +ZXIC_SIZE_T ic_comm_getAbsValue(ZXIC_UINT8* dest, ZXIC_CONST ZXIC_UINT8* src); +ZXIC_VOID ic_comm_memset_s(void* dest, ZXIC_SIZE_T dmax, ZXIC_UINT8 c, ZXIC_SIZE_T n); +ZXIC_SINT32 ic_comm_memcmp(void* str1, const void* str2, ZXIC_SIZE_T n); +ZXIC_SINT32 ic_comm_strncmp(const ZXIC_CHAR* str1, const ZXIC_CHAR* str2, ZXIC_SIZE_T n); + + +#endif + +#if ZXIC_REAL("dma内存分配") +#define ZXIC_DMA_PHY_ADDR dma_addr_t +ZXIC_RTN32 zxic_comm_dma_mem_malloc(ZXIC_ADDR_T *vir_addr,ZXIC_ADDR_T *phy_addr,ZXIC_UINT32 dma_size); +ZXIC_RTN32 zxic_comm_dma_mem_free(ZXIC_ADDR_T vir_addr,ZXIC_ADDR_T phy_addr,ZXIC_UINT32 dma_size); +#endif + +#if ZXIC_REAL("OTHER") +#define MIN_VAL(x,y) ((x)<=(y) ? (x) : (y)) +#define MAX_VAL(x,y) ((x)<=(y) ? (y) : (x)) +#define ZXIC_COMM_DM_TO_X(d, m) ((d) & ~(m)) +#define ZXIC_COMM_DM_TO_Y(d, m) (~(d) & ~(m)) +#define ZXIC_COMM_XY_TO_MASK(x, y) (~(x) & ~(y)) +#define ZXIC_COMM_XY_TO_DATA(x, y) (x) /* valid only when mask is 0 */ +#define ZXIC_RD_CNT_MAX (50) + +/* 新增常用数据掩码 */ +#define ZXIC_COMM_WORD64_MASK (0xFFFFFFFFFFFFFFFFULL) +#define ZXIC_COMM_WORD32_MASK (0xFFFFFFFFU) +#define ZXIC_COMM_WORD16_MASK (0xFFFFU) +#define ZXIC_COMM_BYTE_MASK (0xFFU) + +ZXIC_RTN32 ZXIC_COMM_GET_MASK_VALUE(ZXIC_UINT32 total, ZXIC_UINT32 masklen); +ZXIC_UINT32 zxic_comm_random(ZXIC_VOID); +ZXIC_VOID zxic_comm_channel_max_set(ZXIC_UINT32 dev_max); + +ZXIC_RTN32 zxic_comm_channel_max_get(ZXIC_VOID); + +ZXIC_VOID zxic_comm_dbgcnt64_select_print(const ZXIC_CHAR * name, ZXIC_UINT64 value, ZXIC_UINT32 prt_mode); + +ZXIC_VOID zxic_comm_dbgcnt64_select_par_print(const ZXIC_CHAR * name, ZXIC_UINT32 parm, ZXIC_UINT64 value, ZXIC_UINT32 prt_mode); + +ZXIC_VOID zxic_comm_dbgcnt32_select_print(const ZXIC_CHAR * name, ZXIC_UINT32 value, ZXIC_UINT32 prt_mode); + +ZXIC_VOID zxic_comm_dbgcnt32_select_par_print(const ZXIC_CHAR * name, ZXIC_UINT32 parm, ZXIC_UINT32 value, ZXIC_UINT32 prt_mode); + +#define ZXIC_COMM_CHECK_ADD_CNT(x,y) (((0xffffffff - (x)) < (y)) ? ((y) - (0xffffffff - (x)) - 1) : ((x) + (y))) +#define ZXIC_COMM_CHECK_ADD_CNT_WORD64(x,y) (((0xffffffffffffffff - (x)) < (y)) ? ((y) - (0xffffffffffffffff - (x)) - 1) : ((x) + (y))) +#endif + +#if ZXIC_REAL("UT_TEST") + +ZXIC_VOID zxic_comm_ut_detail_info_trace(const ZXIC_CHAR *format, ...); + +ZXIC_VOID zxic_comm_ut_result_info_trace(const ZXIC_CHAR *format, ...); + +ZXIC_VOID zxic_comm_ut_detail_trace_error(const ZXIC_CHAR *format, ...); + +ZXIC_VOID zxic_comm_ut_detail_trace_dev_error(ZXIC_UINT32 dev_id, const ZXIC_CHAR *format, ...); + +#endif + + + + +#if ZXIC_REAL("头文件") +#include "zxic_comm_double_link.h" +#include "zxic_comm_doublelink_index.h" +#include "zxic_comm_liststack.h" +#include "zxic_comm_avl_tree.h" +#include "zxic_comm_rb_tree.h" +#include "zxic_comm_index_ctrl.h" +#include "zxic_comm_index_reserve.h" +#include "zxic_comm_index_fill.h" +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* end __ZXIC_COMMON_H__ */ + diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_private.h b/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_private.h new file mode 100644 index 0000000..76a4e7a --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_private.h @@ -0,0 +1,117 @@ +/************************************************************** +* 版权所有 (C)2013-2020, 深圳市中兴通讯股份有限公司 +* 文件名称 : +* 文件标识 : +* 内容摘要 : 集合几个文件用到的定义，不对外部开放 +* 其它说明 : +* 当前版本 : +* 作 者 : +* 完成日期 : 2020/07/20 +* DEPARTMENT: 有线开发四部-系统软件团队 +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ +#ifndef __ZXIC_PRIVATE_H__ +#define __ZXIC_PRIVATE_H__ + +#if ZXIC_REAL("日志相关") +#include +#include +#include +#define ZXIC_TRACE_LOG_FILE_GZ_MAX_CNT (50) /* 最大压缩后日志文件数 */ + +typedef struct zxic_log_file_info +{ + char fname[50]; + struct file *p_log_fp; + unsigned int f_size; /* 日志文件大小上限，以字节为单位 */ +}ZXIC_LOG_FILE_INFO; + + +#endif /* ZXIC_REAL("日志相关") */ + +#if ZXIC_REAL("打印相关") + typedef enum + { + ZXIC_TRACE_PRINT = 0, + ZXIC_TRACE_ERROR_PRINT = 1, + ZXIC_TRACE_INFO_PRINT , + ZXIC_TRACE_DEBUG_PRINT , + ZXIC_TRACE_ALL_PRINT , + ZXIC_TRACE_INVALID_PRINT + } ZXIC_TRACE_LEVEL; + + typedef enum zxic_log_file_type_e + { + ZXIC_LOG_SDK = 0, /*SDK日常配置记录*/ + ZXIC_LOG_INIT = 1, /*初始化日志记录*/ + ZXIC_LOG_LIF = 2, /*LIF日志记录*/ + ZXIC_LOG_SERDES = 3, /*SERDES日志记录*/ + ZXIC_LOG_SE_ERAM = 4, /*SE ERAM日志记录*/ + ZXIC_LOG_SE_HBM = 5, /*SE HBM日志记录*/ + ZXIC_LOG_SE_OTHER = 6, /*SE other （se 部分模块）日志记录*/ + ZXIC_LOG_REG = 7, /*寄存器和打桩信息日志记录，特殊使用*/ + ZXIC_LOG_DEBUG = 8, /*打印，诊断计数打印等日志记录*/ + ZXIC_LOG_DUMP = 9, /*捞数据日志记录，特殊使用*/ + ZXIC_LOG_SE_LPM_SAMPLE_V4 = 10, /*SE LPM_V4样本打印记录*/ + ZXIC_LOG_SE_LPM_SAMPLE_V6 = 11, /*SE LPM_V4样本打印记录*/ + ZXIC_LOG_UT_DETAIL = 12, /* ut check 失败信息 */ + ZXIC_LOG_UT_RESULT = 13, /* utcheck 统计信息 */ + ZXIC_LOG_SE_HASH = 14, /*SE HASH日志记录*/ + ZXIC_LOG_SE_ACL = 15, /*SE ACL日志记录*/ + ZXIC_LOG_SLT = 16, /*SLT 日志记录*/ + ZXIC_LOG_SDS_COMM = 17, /*SERDES COMM 库日志记录 */ + ZXIC_LOG_THREAD = 31, /*多线程log打印,注意多线程占用了31b~26b*/ + ZXIC_LOG_MAX, + } ZXIC_LOG_FILE_TYPE_E; + +#define ZXIC_THREAD_ID_NUM_MAX (2048) + +#define ZXIC_MALLOC_MAX_B_SIZE (0xC800000U) /* 200M */ + +#endif /* ZXIC_REAL("打印相关") */ + +#if ZXIC_REAL("互斥锁相关") +typedef struct zxic_mutex_t +{ +#ifdef ZXIC_OS_WIN + HANDLE mutex; +#else + struct mutex mutex; +#endif +}ZXIC_MUTEX_T; +#endif + +#if ZXIC_REAL("信号量相关") +typedef struct zxic_sem_t +{ + #ifdef ZXIC_OS_WIN + HANDLE sem; + #else + struct semaphore sem; + #endif +}ZXIC_SEM_T; +#endif + +void *ic_comm_sdk_print_regist(void); +unsigned int ic_comm_callback_print_get(void* pExcCall); +unsigned int ic_comm_callback_err_log_get(void* pExcCall); +void ic_comm_set_os_callback(ZXIC_OS_CALLBACK *p_os_cb); +void ic_comm_malloc_record(unsigned int size); +void ic_comm_free_record(void); +/***********************************************************/ +/** 从path_name所指的目录中查找符合参数的执行文件，找到后便执行该文件， + 然后将第二个参数argv传给该欲执行的文件,请参照execv用法,异常时候返回-1 +* @return +* @remark 无 +* @see +* @author pj @date 2020/03/30 +************************************************************/ +int zxic_system(const char *path_name, char *const argv[]); + +#endif /* end __ZXIC_COMMON_TOP_H__ */ diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_private_top.h b/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_private_top.h new file mode 100644 index 0000000..1951518 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_private_top.h @@ -0,0 +1,194 @@ +/************************************************************** +* 版权所有 (C)2013-2020, 深圳市中兴通讯股份有限公司 +* 文件名称 : zxic_comm_top.h +* 文件标识 : +* 内容摘要 :提供少许 common.h 开头就要用到的宏 +* 其它说明 : 项目线不需要感知 +* 当前版本 : +* 作 者 : +* 完成日期 : 2020/07/20 +* DEPARTMENT: 有线开发四部-系统软件团队 +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ +#ifndef __ZXIC_PRIVATE_TOP_H__ +#define __ZXIC_PRIVATE_TOP_H__ + +//#include +//#include +//#include +#include +#include +//#include +//#include +#include +//#include +#include +#include + +#define ZXIC_REAL(x) (1U) /* 用于#if 对同一类的代码进行 分段 */ +#define ZXIC_NOREAL(x) (0U) /* 用于#if 对同一类的代码进行 分段 */ + +#ifndef ZXIC_OS_WIN /* 操作系统类型导入,编译宏控制 */ +#define ZXIC_OS_LINUX /* 默认为LINUX操作系统 */ +#endif + +#if ZXIC_REAL("内存") +typedef void* (*ZXIC_OS_MEM_MALLOC)(unsigned int mem_size); +typedef void (*ZXIC_OS_MEM_FREE)(void *p_free); + +typedef struct _zxic_os_callback +{ + ZXIC_OS_MEM_MALLOC p_mem_malloc; + ZXIC_OS_MEM_FREE p_mem_free; +} ZXIC_OS_CALLBACK; +#endif + +#if ZXIC_REAL("大小端") +/*大小端序专用*/ +typedef union zxic_endian_u +{ + unsigned int a; + unsigned char b; +} ZXIC_ENDIAN_U; +#endif + +#if ZXIC_REAL("异常返回值宏定义") +#define ZXIC_RC_BASE (0x1000U) + +/* bit_stream */ +#define ZXIC_BIT_STREAM_BASE (ZXIC_RC_BASE | 0x100) +#define ZXIC_BIT_STREAM_INDEX_ERR (ZXIC_BIT_STREAM_BASE | 0x001) +#define ZXIC_BIT_STREAM_DATA_TOO_BIG (ZXIC_BIT_STREAM_BASE | 0x002) + +/* parameter check */ +#define ZXIC_PARAMETER_CHK_BASE (ZXIC_RC_BASE | 0x200) +#define ZXIC_PAR_CHK_POINT_NULL (ZXIC_PARAMETER_CHK_BASE | 0x001) +#define ZXIC_PAR_CHK_ARGIN_ZERO (ZXIC_PARAMETER_CHK_BASE | 0x002) +#define ZXIC_PAR_CHK_ARGIN_OVERFLOW (ZXIC_PARAMETER_CHK_BASE | 0x003) +#define ZXIC_PAR_CHK_ARGIN_ERROR (ZXIC_PARAMETER_CHK_BASE | 0x004) +#define ZXIC_PAR_CHK_INVALID_INDEX (ZXIC_PARAMETER_CHK_BASE | 0x005) +#define ZXIC_PAR_CHK_INVALID_RANGE (ZXIC_PARAMETER_CHK_BASE | 0x006) +#define ZXIC_PAR_CHK_INVALID_DEV_ID (ZXIC_PARAMETER_CHK_BASE | 0x007) +#define ZXIC_PAR_CHK_INVALID_PARA (ZXIC_PARAMETER_CHK_BASE | 0x008) + +/* mutex lock */ +#define ZXIC_MUTEX_LOCK_BASE (ZXIC_RC_BASE | 0x300) +#define ZXIC_MUTEX_LOCK_INIT_FAIL (ZXIC_MUTEX_LOCK_BASE | 0x001) +#define ZXIC_MUTEX_LOCK_LOCK_FAIL (ZXIC_MUTEX_LOCK_BASE | 0x002) +#define ZXIC_MUTEX_LOCK_ULOCK_FAIL (ZXIC_MUTEX_LOCK_BASE | 0X003) +#define ZXIC_MUTEX_LOCK_DESTROY_FAIL (ZXIC_MUTEX_LOCK_BASE | 0X004) + +/* thread */ +#define ZXIC_THREAD_BASE (ZXIC_RC_BASE | 0x400) +#define ZXIC_THREAD_INFO_ADD_FAIL (ZXIC_THREAD_BASE | 0x001) +#define ZXIC_THREAD_CREATE_FAIL (ZXIC_THREAD_BASE | 0x002) + +/* socket */ +#define ZXIC_SOCKET_BASE (ZXIC_RC_BASE | 0x400) +#define ZXIC_SOKET_SERVICE_START_FAIL (ZXIC_THREAD_BASE | 0x001) +#define ZXIC_SOKET_SERVICE_CLOSE_FAIL (ZXIC_THREAD_BASE | 0x002) +#define ZXIC_SOKET_SET_PARA_FAIL (ZXIC_THREAD_BASE | 0x003) +#define ZXIC_SOKET_CREATE_FAIL (ZXIC_THREAD_BASE | 0x004) +#define ZXIC_SOKET_BIND_LISTEN_FAIL (ZXIC_THREAD_BASE | 0x005) +#define ZXIC_SOKET_CONNECT_FAIL (ZXIC_THREAD_BASE | 0x006) +#define ZXIC_SOKET_CLOSE_FAIL (ZXIC_THREAD_BASE | 0x007) +#define ZXIC_SOKET_GET_PARA_FAIL (ZXIC_THREAD_BASE | 0x008) + + +/* double link */ +#define ZXIC_DOUBLE_LINK_BASE (ZXIC_RC_BASE | 0x500) +#define ZXIC_DOUBLE_LINK_ELEMENT_NUM_ERR (ZXIC_DOUBLE_LINK_BASE | 0x001) +#define ZXIC_DOUBLE_LINK_MALLOC_FAIL (ZXIC_DOUBLE_LINK_BASE | 0x002) +#define ZXIC_DOUBLE_LINK_POINT_NULL (ZXIC_DOUBLE_LINK_BASE | 0x003) +#define ZXIC_DOUBLE_LINK_CHK_SUM_ERR (ZXIC_DOUBLE_LINK_BASE | 0x004) +#define ZXIC_DOUBLE_LINK_NO_EXIST_FREENODE (ZXIC_DOUBLE_LINK_BASE | 0x005) +#define ZXIC_DOUBLE_LINK_FREE_INDX_INVALID (ZXIC_DOUBLE_LINK_BASE | 0x006) +#define ZXIC_DOUBLE_LINK_NO_EXIST_PRENODE (ZXIC_DOUBLE_LINK_BASE | 0x007) +#define ZXIC_DOUBLE_LINK_INPUT_INDX_INVALID (ZXIC_DOUBLE_LINK_BASE | 0x008) +#define ZXIC_DOUBLE_LINK_INIT_ELEMENT_NUM_ERR (ZXIC_DOUBLE_LINK_BASE | 0x009) + + +/* index ctrl */ +#define ZXIC_INDEX_CTRL_BASE (ZXIC_RC_BASE | 0x600) +#define ZXIC_INDEX_CTRL_TREE_FULL (ZXIC_INDEX_CTRL_BASE | 0x001) +#define ZXIC_INDEX_CTRL_SAME_RECORD (ZXIC_INDEX_CTRL_BASE | 0x002) +#define ZXIC_INDEX_CTRL_OPER_MODE_ERR (ZXIC_INDEX_CTRL_BASE | 0x003) + +/* index reverse */ +#define ZXIC_INDEX_RSV_BASE (ZXIC_RC_BASE | 0x700) +#define ZXIC_INDEX_RESERVE_GET_INDX_FAIL (ZXIC_INDEX_RSV_BASE | 0x001) +#define ZXIC_INDEX_RESERVE_BORROW_HIG_FAIL (ZXIC_INDEX_RSV_BASE | 0x002) +#define ZXIC_INDEX_RESERVE_BORROW_LOW_FAIL (ZXIC_INDEX_RSV_BASE | 0x003) +#define ZXIC_INDEX_RESERVE_ALLOCI_INDX_FAIL (ZXIC_INDEX_RSV_BASE | 0x004) +#define ZXIC_INDEX_RESERVE_FREE_INDX_FAIL (ZXIC_INDEX_RSV_BASE | 0x005) +#define ZXIC_INDEX_RESERVE_RESET_INDX_FAIL (ZXIC_INDEX_RSV_BASE | 0x006) + +/* list stack */ +#define ZXIC_LIST_STACK_BASE (ZXIC_RC_BASE | 0x800) +#define ZXIC_LIST_STACK_ELEMENT_NUM_ERR (ZXIC_LIST_STACK_BASE | 0x001) +#define ZXIC_LIST_STACK_POINT_NULL (ZXIC_LIST_STACK_BASE | 0x002) +#define ZXIC_LIST_STACK_ALLOC_MEMORY_FAIL (ZXIC_LIST_STACK_BASE | 0x003) +#define ZXIC_LIST_STACK_ISEMPTY_ERR (ZXIC_LIST_STACK_BASE | 0x004) +#define ZXIC_LIST_STACK_FREE_INDEX_INVALID (ZXIC_LIST_STACK_BASE | 0x005) +#define ZXIC_LIST_STACK_ALLOC_INDEX_INVALID (ZXIC_LIST_STACK_BASE | 0x006) +#define ZXIC_LIST_STACK_ALLOC_INDEX_USED (ZXIC_LIST_STACK_BASE | 0x007) + +/* avl tree */ +#define ZXIC_AVL_TREE_BASE (ZXIC_RC_BASE | 0x900) +#define ZXIC_AVL_TREE_INVALID_INDEX (ZXIC_AVL_TREE_BASE | 0x001) +#define ZXIC_AVL_TREE_SORT_INIT_INPUT_PARA_ERR (ZXIC_AVL_TREE_BASE | 0x002) +#define ZXIC_AVL_TREE_SORT_ISEMPTY_ERR (ZXIC_AVL_TREE_BASE | 0x003) +#define ZXIC_AVL_TREE_SORT_INSERT_SAME_KEY (ZXIC_AVL_TREE_BASE | 0x004) +#define ZXIC_AVL_TREE_SORT_IS_FULL (ZXIC_AVL_TREE_BASE | 0x005) +#define ZXIC_AVL_TREE_KEY_SIZE_ERR (ZXIC_AVL_TREE_BASE | 0x006) + +/* index fill */ +#define ZXIC_INDEX_FILL_BASE (ZXIC_RC_BASE | 0xA00) +#define ZXIC_INDEX_FILL_FULL (ZXIC_INDEX_FILL_BASE | 0x001) +#define ZXIC_INDEX_DEL_FAIL (ZXIC_INDEX_FILL_BASE | 0x002) + +#define ZXIC_COMM_LOG_BASE (ZXIC_RC_BASE | 0xB00) +#define ZXIC_COMM_LOG_MUTEX_CREATE_FAIL (ZXIC_COMM_LOG_BASE | 0x001) +#define ZXIC_COMM_LOG_MUTEX_LOCK_FAIL (ZXIC_COMM_LOG_BASE | 0x002) +#define ZXIC_COMM_LOG_FILE_RENAME_FAIL (ZXIC_COMM_LOG_BASE | 0x003) +#define ZXIC_COMM_LOG_FILE_DELETE_FAIL (ZXIC_COMM_LOG_BASE | 0x004) + +/* index fill type */ +#define ZXIC_INDEX_FILL_TYPE_BASE (ZXIC_RC_BASE | 0xC00) +#define ZXIC_INDEX_FILL_TYPE_FULL (ZXIC_INDEX_FILL_TYPE_BASE | 0x001) +#define ZXIC_INDEX_DEL_TYPE_FAIL (ZXIC_INDEX_FILL_TYPE_BASE | 0x002) + +#define ZXIC_COMM_C_INVALID_PARAM (ZXIC_COMM_LOG_BASE | 0x005) + +#define ZXIC_E_LLT_CHECK (25) +#define ZXIC_E_LLT_ASSERT (26) + +#endif /* END 返回值宏定义 */ + +#if ZXIC_REAL("") +signed int ic_comm_snprintf_s(char *buffer, size_t sizeofbuf, size_t count, const char *format, ...); +signed int ic_comm_vsnprintf_s(char *buffer, size_t sizeofbuf, size_t count, const char *format, va_list ap); +signed int ic_comm_sscanf(const char * src, const char * format, ...); +char *ic_comm_strcpy_s( char *pcDst, size_t dwMaxSize, const char *pcSrc); +char *ic_comm_strncpy_s( char *pcDst, size_t dwMaxSize, const char *pcSrc, size_t dwCount ); +unsigned int ic_comm_memcpy(void* dest, const void* src, size_t n); +unsigned int ic_comm_memcpy_s(void* dest, size_t dest_len, const void* src, size_t n); +char *ic_comm_strcat_s( char *pcDst, size_t dwMaxSize, const char *pcSrc ); +char *ic_comm_strncat_s( char *pcDst, size_t dwMaxSize, const char *pcSrc, size_t dwCount ); +size_t ic_comm_strnlen_s( const char *str, size_t MaxCount); +char* ic_comm_strtok_s(char* string_org, const char* demial, char** context); +ZXIC_OS_CALLBACK* zxic_comm_get_os_callback(void); +void* ic_comm_malloc_memory(unsigned int size); +void ic_comm_free_record(void); +unsigned int zxic_comm_index_check(unsigned int val, unsigned int min, unsigned int max); +unsigned int zxic_comm_dev_index_check(unsigned int dev_id, unsigned int val, unsigned int min, unsigned int max); +unsigned int zxic_comm_index_check(unsigned int val, unsigned int min, unsigned int max); +#endif + +#endif /* end __ZXIC_COMMON_TOP_H__ */ diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_slt.h b/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_slt.h new file mode 100644 index 0000000..d23ebcc --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_slt.h @@ -0,0 +1,751 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : zxic_slt.h +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : PJ +* 完成日期 : 2022/03/26 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ + +#ifndef __ZXIC_SLT_H__ +#define __ZXIC_SLT_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +#define ZXIC_SLT_CASE_PASS (0U) +#define ZXIC_SLT_CASE_FAILURE (1U) + +#define ZXIC_SLT_ERR_INFO_LEN (255U) +#define ZXIC_SLT_CASE_MAX_NUM (255U) +#define ZXIC_SLT_DEV_ID_MAX_NUM (4U) +#define ZXIC_SLT_CHIP_ID_LEN (3U) + +/* 封装类型，不同产品含义不同，暂时定义最大支持5个*/ +#define ZXIC_SLT_MAX_ENCAP (5U) + + +/* BIN_CODE 编码*/ +#define ZXIC_SLT_BIN_CODE_PASS ZXIC_SLT_CASE_PASS +#define ZXIC_SLT_BIN_CODE_SERDES_FAIL (1U)/* sredes类检测*/ +#define ZXIC_SLT_BIN_CODE_FLOW_FAIL (2U)/* pvt类检测 FLOW通流类*/ +#define ZXIC_SLT_BIN_CODE_RAM_FAIL (3U)/* RAM类检测*/ +#define ZXIC_SLT_BIN_CODE_HBM_DDR_FAIL (4U)/* hbm类检测*/ +#define ZXIC_SLT_BIN_CODE_OTHER_FAIL (5U)/* PLL EFUSE PCIE RISCV */ +#define ZXIC_SLT_BIN_CODE_MIX_FAIL (6U)/* 上述多种类型的混合*/ + + + + +/* 测试用例全集case_no定义*/ +typedef enum zxic_slt_case_no_e +{ + ZXIC_SLT_CASE_PLL_LOCK_STATUS_CHECK = (0x08U), + /* efuse锁定相关测试用例 */ + ZXIC_SLT_CASE_EFUSE_CHECK = (0x09U), + + + + + /* serdes用例编号范围0x10~0x7f*/ + /* lifx(LIF0 LIF1 LIF2)接口serdes prbs相关测试用例 0x10~0x2f*/ + ZXIC_SLT_CASE_SERDES_LIFX_PRBS_1G = (0x10U), + ZXIC_SLT_CASE_SERDES_LIFX_PRBS_3G = (0x11U), + ZXIC_SLT_CASE_SERDES_LIFX_PRBS_5G = (0x12U), + ZXIC_SLT_CASE_SERDES_LIFX_PRBS_6G = (0x13U), + ZXIC_SLT_CASE_SERDES_LIFX_PRBS_9G = (0x14U), + ZXIC_SLT_CASE_SERDES_LIFX_PRBS_10G = (0x15U), + ZXIC_SLT_CASE_SERDES_LIFX_PRBS_12G = (0x16U), + ZXIC_SLT_CASE_SERDES_LIFX_PRBS_15G = (0x17U), + ZXIC_SLT_CASE_SERDES_LIFX_PRBS_20G = (0x18U), + ZXIC_SLT_CASE_SERDES_LIFX_PRBS_25G = (0x19U), + ZXIC_SLT_CASE_SERDES_LIFX_PRBS_26G = (0x1aU), + ZXIC_SLT_CASE_SERDES_LIFX_PRBS_27G = (0x1bU), + ZXIC_SLT_CASE_SERDES_LIFX_PRBS_28G = (0x1cU), + ZXIC_SLT_CASE_SERDES_LIFX_PRBS_30G = (0x1dU), + ZXIC_SLT_CASE_SERDES_LIFX_PRBS_50G = (0x1fU), + ZXIC_SLT_CASE_SERDES_LIFX_PRBS_51G = (0x20U), + ZXIC_SLT_CASE_SERDES_LIFX_PRBS_53G = (0x21U), + ZXIC_SLT_CASE_SERDES_LIFX_PRBS_55G = (0x22U), + ZXIC_SLT_CASE_SERDES_LIFX_PRBS_56G = (0x23U), + ZXIC_SLT_CASE_SERDES_LIFX_PRBS_57G = (0x24U), + ZXIC_SLT_CASE_SERDES_LIFX_PRBS_98G = (0x25U), + ZXIC_SLT_CASE_SERDES_LIFX_PRBS_106G = (0x26U), + ZXIC_SLT_CASE_SERDES_LIFX_PRBS_111G = (0x27U), + ZXIC_SLT_CASE_SERDES_LIFX_PRBS_112G = (0x28U), + + + /* lifc接口serdes相关测试用例 0x30~0x37*/ + ZXIC_SLT_CASE_SERDES_LIFC_PRBS_1G = (0x30U), + ZXIC_SLT_CASE_SERDES_LIFC_PRBS_10G = (0x31U), + ZXIC_SLT_CASE_SERDES_LIFC_PRBS_25G = (0x32U), + ZXIC_SLT_CASE_SERDES_LIFC_PRBS_53G = (0x33U), + + /* lifc eth 接口发包测试相关测试用例 0x38~0x3f*/ + ZXIC_SLT_CASE_PORT_LIFC_SD_1G = (0x38U), + ZXIC_SLT_CASE_PORT_LIFC_SD_10G = (0x39U), + ZXIC_SLT_CASE_PORT_LIFC_SD_25G = (0x3aU), + ZXIC_SLT_CASE_PORT_LIFC_SD_53G = (0x3bU), + + /* 外部查找的interlaken-la接口*/ + ZXIC_SLT_CASE_SERDES_INTERLAKEN_LA = (0x3fU), + + + /* lif0 eth 接口发包测试相关测试用例 0x40~0x5f*/ + ZXIC_SLT_CASE_PORT_LIFO_SD_1G = (0x40U), + ZXIC_SLT_CASE_PORT_LIFO_SD_5G = (0x41U), + ZXIC_SLT_CASE_PORT_LIFO_SD_10G = (0x42U), + ZXIC_SLT_CASE_PORT_LIFO_SD_12G = (0x43U), + ZXIC_SLT_CASE_PORT_LIFO_SD_25G = (0x44U), + ZXIC_SLT_CASE_PORT_LIFO_SD_26G = (0x45U), + ZXIC_SLT_CASE_PORT_LIFO_SD_51G = (0x46U), + ZXIC_SLT_CASE_PORT_LIFO_SD_53G = (0x47U), + ZXIC_SLT_CASE_PORT_LIFO_SD_106G = (0x48U), + ZXIC_SLT_CASE_PORT_LIFO_SD_112G = (0x49U), + ZXIC_SLT_CASE_PORT_LIFO_SD_20G = (0x4AU), + + + /* lif0 intlk接口发包测试相关测试用例 0x60~0x6f*/ + ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_3G = (0x60U), + ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_6G = (0x61U), + ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_10G = (0x62U), + ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_12G = (0x63U), + ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_25G = (0x64U), + ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_28G = (0x65U), + ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_30G = (0x66U), + ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_50G = (0x67U), + ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_51G = (0x68U), + ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_53G = (0x69U), + ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_56G = (0x6aU), + ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_106G = (0x6bU), + ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_112G = (0x6cU), + + + /* 交换侧lif1 FEC测试相关测试用例 0x70~0x7f*/ + ZXIC_SLT_CASE_SERDES_LIF1_FEC_25G = (0x70U), + ZXIC_SLT_CASE_SERDES_LIF1_FEC_26G = (0x71U), + ZXIC_SLT_CASE_SERDES_LIF1_FEC_28G = (0x72U), + ZXIC_SLT_CASE_SERDES_LIF1_FEC_50G = (0x73U), + ZXIC_SLT_CASE_SERDES_LIF1_FEC_53G = (0x74U), + ZXIC_SLT_CASE_SERDES_LIF1_FEC_56G = (0x75U), + ZXIC_SLT_CASE_SERDES_LIF1_FEC_98G = (0x76U), + ZXIC_SLT_CASE_SERDES_LIF1_FEC_106G = (0x77U), + ZXIC_SLT_CASE_SERDES_LIF1_FEC_112G = (0x78U), + + + + + /*片内ram用例编号范围0x80~0x87*/ + /* CPU可读写寄存器测试用例 */ + ZXIC_SLT_CASE_REG_CPU_W_R = (0x80U), + /* CPU可读写ram测试用例 */ + ZXIC_SLT_CASE_RAM_CPU_W_R = (0x81U), + /* RAM表项读写测试(微码)*/ + ZXIC_SLT_CASE_RAM_MC_W_R = (0x82U), + /* RAM表项读写测试 memtest86(微码)*/ + ZXIC_SLT_CASE_RAM_MC_MEMTEST86 = (0x83U), + + + + + /* HBM/DDR用例编号范围 0x90~0x9f*/ + /*mbist测试*/ + ZXIC_SLT_CASE_HBM_DDR_CTRL_BIST = (0x90U), + /* HBM/DDR表项CPU读写测试*/ + ZXIC_SLT_CASE_HBM_DDR_CPU_W_R = (0x91U), + /* HBM/DDR表项读写测试(微码)*/ + ZXIC_SLT_CASE_HBM_DDR_MC_W_R = (0x92U), + /* HBM/DDR表项读写测试 memtest86(微码)*/ + ZXIC_SLT_CASE_HBM_DDR_MC_MEMTEST86 = (0x93U), + /* HBM/DDR TM覆盖测试*/ + ZXIC_SLT_CASE_HBM_DDR_TM_TEST = (0x94U), + + + + + + /* 发流测试和全业务PVT测试用例编号范围 0xa0~0xaf*/ + /* 数据路径测试用例 */ + ZXIC_SLT_CASE_PKT_FLOW_NOM = (0xA0U), + /* OAM发包测试用例 */ + ZXIC_SLT_CASE_OAM_SEND_PKT = (0xA1U), + /* se查表全集测试 */ + ZXIC_SLT_CASE_PKT_FLOW_SE_FULL = (0xA2U), + /* tm全队列测试用例 */ + ZXIC_SLT_CASE_PKT_FLOW_TM_FULL = (0xA3U), + /* LIFC口测试用例 */ + ZXIC_SLT_CASE_PKT_FLOW_LIFC = (0xA4U), + + /* 芯片PVT 功耗、温度和电压测试用例 */ + ZXIC_SLT_CASE_PVT_EXCEED_POWER_TEST = (0xA8U), + ZXIC_SLT_CASE_PVT_EXCEED_TEM_VOLT_TEST = (0xA9U), + ZXIC_SLT_CASE_PVT_EXCEED_HBM_TEMPER_TEST = (0xAaU), + + + + + + /* 其他测试用例编号范围0xb0~0xff*/ + /* 调压测试*/ + ZXIC_SLT_CASE_VOLT_TEST = (0xB0U), + /* 时钟频偏测试 */ + ZXIC_SLT_CASE_CLK_TEST = (0xB1U), + + /* PCIE压力测试 */ + ZXIC_SLT_CASE_PCIE_W_R_TEST = (0xB2U), + /* 下述两个测试用例必须放在最后执行 */ + /* PCIE建链测试 */ + ZXIC_SLT_CASE_PCIE_TEST = (0xB3U), + /* RISCV测试用例 */ + ZXIC_SLT_CASE_RISCV_W_R_TEST = (0xB4U), + + ZXIC_SLT_CASE_MAX, +} ZXIC_SLT_CASE_NO_E; + + +#if ZXIC_REAL("ERR_CODE") +#define ZXIC_SLT_RC_BASE (0x100U) + + + #define ZXIC_SLT_TEST_CASE_FNC_POINT_NULL (ZXIC_SLT_RC_BASE | 0x1) + #define ZXIC_SLT_CASE_PLL_LOCK_STATUS_CHECK_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PLL_LOCK_STATUS_CHECK) + #define ZXIC_SLT_CASE_EFUSE_CHECK_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_EFUSE_CHECK) + + /* lifx*/ + #define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_1G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_1G) + #define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_3G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_3G) + #define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_5G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_5G) + #define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_6G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_6G) + #define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_9G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_9G) + #define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_10G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_10G) + #define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_12G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_12G) + #define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_15G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_15G) + #define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_20G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_20G) + #define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_25G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_25G) + #define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_26G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_26G) + #define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_27G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_27G) + #define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_28G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_28G) + #define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_30G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_30G) + #define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_50G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_50G) + #define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_51G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_51G) + #define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_53G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_53G) + #define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_55G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_55G) + #define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_56G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_56G) + #define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_57G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_57G) + #define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_98G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_98G) + #define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_106G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_106G) + #define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_111G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_111G) + #define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_112G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_112G) + + /* lifc*/ + #define ZXIC_SLT_CASE_SERDES_LIFC_PRBS_1G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFC_PRBS_1G) + #define ZXIC_SLT_CASE_SERDES_LIFC_PRBS_10G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFC_PRBS_10G) + #define ZXIC_SLT_CASE_SERDES_LIFC_PRBS_25G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFC_PRBS_25G) + #define ZXIC_SLT_CASE_SERDES_LIFC_PRBS_53G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFC_PRBS_53G) + + /* lifc */ + #define ZXIC_SLT_CASE_PORT_LIFC_SD_1G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFC_SD_1G ) + #define ZXIC_SLT_CASE_PORT_LIFC_SD_10G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFC_SD_10G) + #define ZXIC_SLT_CASE_PORT_LIFC_SD_25G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFC_SD_25G) + #define ZXIC_SLT_CASE_PORT_LIFC_SD_53G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFC_SD_53G) + + /* lif0 ETH*/ + #define ZXIC_SLT_CASE_PORT_LIFO_SD_1G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_1G) + #define ZXIC_SLT_CASE_PORT_LIFO_SD_5G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_5G) + #define ZXIC_SLT_CASE_PORT_LIFO_SD_10G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_10G) + #define ZXIC_SLT_CASE_PORT_LIFO_SD_12G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_12G) + #define ZXIC_SLT_CASE_PORT_LIFO_SD_25G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_25G) + #define ZXIC_SLT_CASE_PORT_LIFO_SD_26G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_26G) + #define ZXIC_SLT_CASE_PORT_LIFO_SD_51G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_51G) + #define ZXIC_SLT_CASE_PORT_LIFO_SD_53G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_53G) + #define ZXIC_SLT_CASE_PORT_LIFO_SD_106G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_106G) + #define ZXIC_SLT_CASE_PORT_LIFO_SD_112G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_112G) + #define ZXIC_SLT_CASE_PORT_LIFO_SD_20G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_20G) + + /* lif0 intlk*/ + #define ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_3G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_3G ) + #define ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_6G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_6G ) + #define ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_10G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_10G ) + #define ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_12G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_12G ) + #define ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_25G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_25G ) + #define ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_28G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_28G ) + #define ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_30G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_30G ) + #define ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_50G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_50G ) + #define ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_51G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_51G ) + #define ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_53G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_53G ) + #define ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_56G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_56G ) + #define ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_106G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_106G) + #define ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_112G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_112G ) + + +/* lif1*/ +#define ZXIC_SLT_CASE_SERDES_LIF1_FEC_25G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIF1_FEC_25G) +#define ZXIC_SLT_CASE_SERDES_LIF1_FEC_26G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIF1_FEC_26G) +#define ZXIC_SLT_CASE_SERDES_LIF1_FEC_28G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIF1_FEC_28G) +#define ZXIC_SLT_CASE_SERDES_LIF1_FEC_50G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIF1_FEC_50G) +#define ZXIC_SLT_CASE_SERDES_LIF1_FEC_53G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIF1_FEC_53G) +#define ZXIC_SLT_CASE_SERDES_LIF1_FEC_56G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIF1_FEC_56G) +#define ZXIC_SLT_CASE_SERDES_LIF1_FEC_98G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIF1_FEC_98G) +#define ZXIC_SLT_CASE_SERDES_LIF1_FEC_106G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIF1_FEC_106G) +#define ZXIC_SLT_CASE_SERDES_LIF1_FEC_112G_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIF1_FEC_112G) + +/* 外部查找的interlaken-la接口*/ +#define ZXIC_SLT_CASE_SERDES_INTELAKEN_LA_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_INTELAKEN_LA) + + + /*片内ram读写测试*/ + #define ZXIC_SLT_CASE_RAM_CPU_W_R_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_RAM_CPU_W_R ) + #define ZXIC_SLT_CASE_REG_CPU_W_R_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_REG_CPU_W_R ) + #define ZXIC_SLT_CASE_RAM_MC_W_R_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_RAM_MC_W_R ) + #define ZXIC_SLT_CASE_RAM_MC_MEMTEST86_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_RAM_MC_MEMTEST86 ) + + /* HBM/DDR */ + #define ZXIC_SLT_CASE_HBM_DDR_CTRL_BIST_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_HBM_DDR_CTRL_BIST ) + #define ZXIC_SLT_CASE_HBM_DDR_MC_W_R_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_HBM_DDR_MC_W_R ) + #define ZXIC_SLT_CASE_HBM_DDR_MC_MEMTEST86_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_HBM_DDR_MC_MEMTEST86 ) + #define ZXIC_SLT_CASE_HBM_DDR_CPU_W_R_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_HBM_DDR_CPU_W_R ) + #define ZXIC_SLT_CASE_HBM_DDR_TM_TEST_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_HBM_DDR_TM_TEST ) + + + /* 发流测试和全业务PVT测试*/ + #define ZXIC_SLT_CASE_PKT_FLOW_NOM_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PKT_FLOW_NOM ) + #define ZXIC_SLT_CASE_OAM_SEND_PKT_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_OAM_SEND_PKT ) + #define ZXIC_SLT_CASE_PKT_FLOW_SE_FULL_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PKT_FLOW_SE_FULL ) + #define ZXIC_SLT_CASE_PKT_FLOW_TM_FULL_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PKT_FLOW_TM_FULL ) + #define ZXIC_SLT_CASE_PKT_FLOW_LIFC_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PKT_FLOW_LIFC ) + + #define ZXIC_SLT_CASE_PVT_EXCEED_POWER_TEST_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PVT_EXCEED_POWER_TEST ) + #define ZXIC_SLT_CASE_PVT_EXCEED_TEM_VOLT_TEST_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PVT_EXCEED_TEM_VOLT_TEST ) + #define ZXIC_SLT_CASE_PVT_EXCEED_HBM_TEMPER_TEST_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PVT_EXCEED_HBM_TEMPER_TEST) + + + #define ZXIC_SLT_CASE_PCIE_TEST_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PCIE_TEST ) + #define ZXIC_SLT_CASE_PCIE_W_R_TEST_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PCIE_W_R_TEST ) + #define ZXIC_SLT_CASE_RISCV_W_R_TEST_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_RISCV_W_R_TEST) + #define ZXIC_SLT_CASE_VOLT_TEST_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_VOLT_TEST ) + #define ZXIC_SLT_CASE_CLK_TEST_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_CLK_TEST) + +#endif + + +typedef struct zxic_slt_err_info_mng_t +{ + ZXIC_UINT32 err_code; /*参见ERR_CODE定义*/ + const ZXIC_CHAR * err_info; +} ZXIC_SLT_ERR_INFO_MNG_T; + + +typedef struct zxic_slt_init_ctrl_t +{ + ZXIC_ADDR_T pcie_vir_baddr; /**< @brief PCIe映射虚拟基地址*/ + ZXIC_ADDR_T riscv_vir_baddr; /**< @brief RISCV映射虚拟基地址 */ + ZXIC_ADDR_T dma_vir_baddr; /**< @brief DMA映射虚拟地址*/ + ZXIC_ADDR_T dma_phy_baddr; /**< @brief DMA内存物理地址*/ +}ZXIC_SLT_INIT_CTRL_T; + + +typedef struct zxic_slt_case_para_t + +{ + ZXIC_UINT32 chip_id[ZXIC_SLT_CHIP_ID_LEN]; /* 返回对应芯片ID */ + ZXIC_UINT32 case_num; /* 返回执行SLT 用例数 */ + ZXIC_UINT32 case_no[ZXIC_SLT_CASE_MAX_NUM]; /* 返回执行SLT 用例编号列表 */ + ZXIC_UINT32 case_result[ZXIC_SLT_CASE_MAX_NUM]; /* 返回执行SLT 用例对应结果，成功返回值或错误码 */ + ZXIC_UINT32 bin_code; /* 返回 SLT 执行分BIN码 */ + ZXIC_DOUBLE temp; /* 返回 SLT 用例测试前初始温度 */ + ZXIC_DOUBLE volt; /* 返回 SLT 用例测试前核电压 */ + +} ZXIC_SLT_CASE_PARA_T; + + + +/*case 函数标准定义*/ +typedef ZXIC_RTN32 (*ZXIC_SLT_INST_CASE_FN)(ZXIC_UINT32 device_id); + +typedef struct zxic_slt_case_mng_t +{ + const ZXIC_CHAR * case_name; /*用例名称*/ + ZXIC_UINT32 case_no; /*参见ZXIC_SLT_CASE_NO_E定义*/ + ZXIC_SLT_INST_CASE_FN inst_case_fn; /*单个case函数指针*/ +} ZXIC_SLT_CASE_MNG_T; + + + +/* 功耗类型定义*/ +typedef enum zxic_slt_power_type_t +{ + ZXIC_SLT_POWER_VCC_SSP4_CORE = (0x0U), + ZXIC_SLT_POWER_VCC0V75_SSP4_SERDES_DVDD = (0x1U), + ZXIC_SLT_POWER_VCC0V75_SSP4_SERDES_AVDDL = (0x2U), + ZXIC_SLT_POWER_VCC1V2_SSP4_SERDES_AVDDH = (0x3U), + ZXIC_SLT_POWER_VCC1V2_SSP4_HBM_VDDQ = (0x4U), + + ZXIC_SLT_POWER_VCC0V75_SSP4_AVDD = (0x5U), + ZXIC_SLT_POWER_VCC1V2_SSP4_AVDD = (0x6U), + ZXIC_SLT_POWER_VCC1V2_SSP4_GPIO_DVDD = (0x7U), + ZXIC_SLT_POWER_VCC2V5_SSP4_VPP = (0x8U), + + ZXIC_SLT_POWER_TYPE_MAX, + +}ZXIC_SLT_POWER_TYPE_T; + +typedef struct zxic_slt_power_t +{ + + ZXIC_DOUBLE volt; /* 电压值 */ + ZXIC_DOUBLE cur; /* 电流值 */ + ZXIC_UINT32 type; /* 功耗编码，参见ZXIC_SLT_POWER_TYPE_T定义 */ +}ZXIC_SLT_POWER_T; + +typedef struct zxic_slt_power_para_t +{ + ZXIC_SLT_POWER_T *p_para; + ZXIC_UINT32 num; /* 有效功耗个数 */ +}ZXIC_SLT_POWER_PARA_T; + + + +/* 电压类型定义*/ +typedef enum zxic_slt_volt_type_t +{ + ZXIC_SLT_VOLT_VCC_SSP4_CORE = (0x0U), + ZXIC_SLT_VOLT_VCC0V75_SSP4_SERDES_DVDD = (0x1U), + ZXIC_SLT_VOLT_VCC0V75_SSP4_SERDES_AVDDL = (0x2U), + ZXIC_SLT_VOLT_VCC1V2_SSP4_SERDES_AVDDH = (0x3U), + ZXIC_SLT_VOLT_VCC1V2_SSP4_HBM_VDDQ = (0x4U), + + ZXIC_SLT_VOLT_TYPE_MAX, + +}ZXIC_SLT_VOLT_TYPE_T; + +typedef struct zxic_slt_volt_t +{ + + ZXIC_UINT32 percent; /* 调压上下浮动值，百分比*100,例如上调1%，传入数值1*/ + ZXIC_UINT32 flag; /* 正偏：0 负偏：1 */ + ZXIC_UINT32 vol_type; /* 电压类型，参见ZXIC_SLT_VOLT_TYPE_T定义 */ +}ZXIC_SLT_VOLT_T; + +typedef struct zxic_slt_volt_para_t +{ + ZXIC_SLT_VOLT_T *p_para; + ZXIC_UINT32 num; /* 有效调压个数 */ +}ZXIC_SLT_VOLT_PARA_T; + + + +/* 时钟类型定义*/ +typedef enum zxic_slt_clk_type_t +{ + ZXIC_SLT_CLK_AU5327_A = (0x0U),/*SSP4 SOCKET 单板AU5327#1 HOST_100M*/ + ZXIC_SLT_CLK_AU5327_B = (0x1U),/*SSP4 SOCKET 单板AU5327#1 PLL_SYS_CLK/SERDES 156.25M*/ + ZXIC_SLT_CLK_AU5327_C = (0x2U),/*SSP4 SOCKET 单板AU5327#1 PLL_LOCAL_CLK 156.25M*/ + ZXIC_SLT_CLK_AU5327_D = (0x3U),/*SSP4 SOCKET 单板AU5327#1 PLL_TS_CLK 125M*/ + + ZXIC_SLT_CLK_TYPE_MAX, + + +}ZXIC_SLT_CLK_TYPE_T; + +typedef struct zxic_slt_clk_t +{ + + ZXIC_UINT32 value; /* 时钟拉偏值，单位HZ(PPM),1PPM = 1HZ（1MHZ=1000KHZ=1000000HZ）*/ + ZXIC_UINT32 flag; /* 正偏：0 负偏：1 */ + ZXIC_UINT32 clk_type; /* 时钟类型，参见ZXIC_SLT_CLK_TYPE_T定义 */ +}ZXIC_SLT_CLK_T; + +typedef struct zxic_slt_clk_para_t +{ + ZXIC_SLT_CLK_T *p_para; + ZXIC_UINT32 num; /* 有效拉偏时钟个数 */ +}ZXIC_SLT_CLK_PARA_T; + + + +#if ZXIC_REAL("define_for_bsp") +/***********************************************************/ +/** 功耗获取函数 +* @param ZXIC_SLT_CASE_GETPOWER_FN +* @param device_id +* @param p_para +* +* @return +* @remark 无 +* @see +* @author PJ @date 2022/04/28 +************************************************************/ +typedef ZXIC_RTN32 (*ZXIC_SLT_CASE_GETPOWER_FN)(ZXIC_UINT32 device_id, ZXIC_SLT_POWER_PARA_T *p_para); + + +/***********************************************************/ +/** riscv测试函数 +* @param ZXIC_SLT_CASE_RISCV_FN +* @param device_id +* @param reg_addr 寄存器地址 +* @param wr_data 写入寄存器的值 +* @param rd_data 期望从寄存器中读出的值 +* +* @return +* @remark 无 +* @see +* @author PJ @date 2022/04/28 +************************************************************/ +typedef ZXIC_RTN32 (*ZXIC_SLT_CASE_RISCV_FN)(ZXIC_UINT32 device_id, ZXIC_UINT32 reg_addr, ZXIC_UINT32 wr_data, ZXIC_UINT32 rd_data); + + +/***********************************************************/ +/** PCIE测试函数 +* @param ZXIC_SLT_CASE_PCIE_FN +* @param device_id +* @param times pcie建链测试次数 +* +* @return +* @remark 无 +* @see +* @author PJ @date 2022/04/28 +************************************************************/ +typedef ZXIC_RTN32 (*ZXIC_SLT_CASE_PCIE_FN)(ZXIC_UINT32 device_id, ZXIC_UINT32 times); + + +/***********************************************************/ +/** 调电压函数 +* @param ZXIC_SLT_CASE_ADJUST_VOLT_FN +* @param device_id +* @param p_para +* +* @return +* @remark 无 +* @see +* @author PJ @date 2022/04/28 +************************************************************/ +typedef ZXIC_RTN32 (*ZXIC_SLT_CASE_ADJUST_VOLT_FN)(ZXIC_UINT32 device_id,ZXIC_SLT_VOLT_PARA_T *p_para); + + +/***********************************************************/ +/** 调时钟函数 +* @param ZXIC_SLT_CASE_ADJUST_CLK_FN +* @param device_id +* @param p_para +* +* @return +* @remark 无 +* @see +* @author PJ @date 2022/04/28 +************************************************************/ +typedef ZXIC_RTN32 (*ZXIC_SLT_CASE_ADJUST_CLK_FN)(ZXIC_UINT32 device_id,ZXIC_SLT_CLK_PARA_T *p_para); + + +/*BSP回调函数定义*/ +typedef struct zxic_slt_bsp_register_fn_t +{ + ZXIC_SLT_CASE_GETPOWER_FN zxic_slt_power_fn; + ZXIC_SLT_CASE_RISCV_FN zxic_slt_riscv_fn; + ZXIC_SLT_CASE_PCIE_FN zxic_slt_pcie_fn; + ZXIC_SLT_CASE_ADJUST_VOLT_FN zxic_slt_volt_fn; + ZXIC_SLT_CASE_ADJUST_CLK_FN zxic_slt_clk_fn; + +} ZXIC_SLT_BSP_REGISTER_FN_T; + +#endif + +#if ZXIC_REAL("define_for_sdk") +/***********************************************************/ +/** 初始化函数 +* @param ZXIC_SLT_INIT_FN +* @param device_id +* @param chip_type 用于区分不同封装类型 +* @param p_init_ctrl 参见ZXIC_SLT_INIT_CTRL_T定义 +* +* @return +* @remark 无 +* @see +* @author PJ @date 2022/04/22 +************************************************************/ +typedef ZXIC_RTN32 (*ZXIC_SLT_INIT_FN)(ZXIC_UINT32 device_id,ZXIC_UINT32 chip_type,ZXIC_SLT_INIT_CTRL_T *p_init_ctrl); + + + + +/* Chip_ID 组成结构说明： +** Chip_ID = efuse里面的wafer批次号+wafer片号+x坐标+Y坐标组合而成 +** wafer批次号: 48bit lot_id5~0 +** wafer片号: 5bit wafer_no +** x坐标: 8bit x_addr +** Y坐标: 8bit y_addr +** chip_id2 = lot_id5[7:3] +** chip_id1 = lot_id5[2:0] + lot_id4 + lot_id3 + lot_id2 + lot_id1[7:3] +** chip_id0 = lot_id1[2:0] + lot_id0 + wafer_no[4:0] + x_addr + y_addr*/ + +/***********************************************************/ +/** 执行测试用例之前的预处理函数,用来获取chip_id,温度，电压信息 +* @param ZXIC_SLT_PRE_FN +* @param device_id +* @param chip_type 用于区分不同封装类型 +* @param p_chip_id 返回芯片的chip_id信息(参见上述格式说明） +* @param p_temp 返回 SLT 用例测试前初始温度 +* @param p_volt 返回 SLT 用例测试前核电压 +* +* @return +* @remark 无 +* @see +* @author PJ @date 2022/03/29 +************************************************************/ +typedef ZXIC_RTN32 (*ZXIC_SLT_PRE_FN)(ZXIC_UINT32 device_id,ZXIC_UINT32 chip_type,ZXIC_UINT32 *p_chip_id, ZXIC_DOUBLE *p_temp,ZXIC_DOUBLE *p_volt); + +/***********************************************************/ +/** 用例执行函数 +* @param ZXIC_SLT_ALL_CASE_FN +* @param device_id +* @param chip_type 用于区分不同封装类型 +* @param p_case_num 返回执行SLT 用例数 +* @param p_case_no 返回执行SLT 用例编号列表 +* @param p_case_result 返回执行SLT 用例对应结果，成功返回值或错误码 +* +* @return +* @remark 无 +* @see +* @author PJ @date 2022/03/29 +************************************************************/ +typedef ZXIC_RTN32 (*ZXIC_SLT_ALL_CASE_FN)(ZXIC_UINT32 device_id,ZXIC_UINT32 chip_type,ZXIC_UINT32 *p_case_num,ZXIC_UINT32 *p_case_no,ZXIC_UINT32 *p_case_result); + +/*SDK回调函数定义*/ +typedef struct zxic_slt_register_fn_t +{ + ZXIC_SLT_INIT_FN zxic_slt_init_fn; /* 初始化函数 */ + ZXIC_SLT_PRE_FN zxic_slt_pre_fn; /* 预处理函数 */ + ZXIC_SLT_ALL_CASE_FN zxic_slt_all_case_fn; /* 用例执行函数*/ + +} ZXIC_SLT_REGISTER_FN_T; + +#endif + + + +#if ZXIC_REAL("fn for sdk") +/***********************************************************/ +/** 回调功能注册函数，不区分芯片ID，仅注册一次即可，提供给SDK设置 +* @return +* @remark 无 +* @see +* @author PJ @date 2020/05/03 +************************************************************/ +ZXIC_RTN32 zxic_slt_register_fn_set(ZXIC_SLT_REGISTER_FN_T *pExcCall); + +/***********************************************************/ +/** 获取POWER函数 +* @param pExcCall +* +* @return +* @remark 无 +* @see +* @author PJ @date 2020/05/03 +************************************************************/ +ZXIC_RTN32 zxic_slt_callback_getpower(ZXIC_VOID *pExcCall); + +/***********************************************************/ +/** 获取MODI函数 +* @param pExcCall +* +* @return +* @remark 无 +* @see +* @author PJ @date 2020/05/03 +************************************************************/ +ZXIC_RTN32 zxic_slt_callback_riscv(ZXIC_VOID *pExcCall); + +/***********************************************************/ +/** 获PCIE函数 +* @param pExcCall +* +* @return +* @remark 无 +* @see +* @author PJ @date 2020/05/03 +************************************************************/ +ZXIC_RTN32 zxic_slt_callback_pcie(ZXIC_VOID *pExcCall); + +/***********************************************************/ +/** 获取VOLT函数 +* @param pExcCall +* +* @return +* @remark 无 +* @see +* @author PJ @date 2020/05/03 +************************************************************/ +ZXIC_RTN32 zxic_slt_callback_adjust_volt(ZXIC_VOID *pExcCall); + +/***********************************************************/ +/** 获取CLK函数 +* @param pExcCall +* +* @return +* @remark 无 +* @see +* @author PJ @date 2020/05/03 +************************************************************/ +ZXIC_RTN32 zxic_slt_callback_adjust_clk(ZXIC_VOID *pExcCall); + + +#endif + + +#if ZXIC_REAL("fn for bsp") + +/***********************************************************/ +/** 回调功能注册函数，不区分芯片ID，仅注册一次即可，提供给SDK设置 +* @return +* @remark 无 +* @see +* @author PJ @date 2020/05/03 +************************************************************/ +ZXIC_RTN32 zxic_slt_bsp_register_fn_set(ZXIC_SLT_BSP_REGISTER_FN_T *pExcCall); + + +/***********************************************************/ +/** 设置是否删除log标记,提供给BSP调用 +* @return +* @remark 无 +* @see +* @author PJ @date 2020/05/03 +************************************************************/ +ZXIC_VOID zxic_slt_log_rm_flag_set(ZXIC_UINT32 log_rm_flag); + + +/***********************************************************/ +/** 执行SDK SLT 所有用例测试,提供给BSP调用 +* @param dev_id +* @param chip_type 芯片封装类型 +* @param p_init_ctrl 详细参见ZXIC_SLT_INIT_CTRL_T说明 +* @param p_case_para 详细参见ZXIC_SLT_CASE_PARA_T说明 +* +* @return +* @remark 无 +* @see +* @author PJ @date 2022/03/29 +************************************************************/ +ZXIC_RTN32 zxic_slt_all_case_test(ZXIC_UINT32 dev_id,ZXIC_UINT32 chip_type, ZXIC_SLT_INIT_CTRL_T *p_init_ctrl,ZXIC_SLT_CASE_PARA_T *p_case_para); + +#endif + + + +#ifdef __cplusplus +} +#endif + +#endif /* end __ZXIC_SLT_H__ */ + diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/comm/source/Kbuild.include b/src/net/drivers/net/ethernet/dinghai/en_np/comm/source/Kbuild.include new file mode 100644 index 0000000..540959a --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/comm/source/Kbuild.include @@ -0,0 +1,2 @@ +cur_dir := en_np/comm/source/ +src_files += $(addprefix $(cur_dir),$(notdir $(wildcard $(dinghai_root)/$(cur_dir)*.c))) \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/comm/source/zxic_comm_double_link.c b/src/net/drivers/net/ethernet/dinghai/en_np/comm/source/zxic_comm_double_link.c new file mode 100644 index 0000000..9a36d06 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/comm/source/zxic_comm_double_link.c @@ -0,0 +1,605 @@ +/***************************************************************************** + * 版权所有 (C)2008-2010, 深圳市中兴通讯股份有限公司。 + * + * 文件名称： zxic_comm_double_link.c + * 文件标识： + * 内容摘要： 双链表实现 + * 其它说明： + * 当前版本： V1.00.10 + * 作 者： + * 完成日期： 2012年2月14日 + * 当前责任人-1：ChenWei188471 + * 当前责任人-2： + * 历史责任人-3: + * + * 修改记录： + * 修改日期： 版 本 号 修 改 人 修改内容 + 1 20120214 V1.00.10 ChenWei188471 创建 + 2 + *****************************************************************************/ + +#include "zxic_common.h" +#include "zxic_comm_double_link.h" + +/*当前节点都插在头节点之后,新插入的节点永远在第一个*/ +ZXIC_RTN32 zxic_comm_double_link_insert_1st(D_NODE *p_newnode,D_HEAD *p_head) +{ + ZXIC_COMM_CHECK_POINT(p_newnode); + ZXIC_COMM_CHECK_POINT(p_head); + + ZXIC_COMM_CHECK_INDEX((p_head->used+1), 1, p_head->maxnum); + + ZXIC_COMM_ASSERT(!(!p_head->p_next&& p_head->p_prev)); + ZXIC_COMM_ASSERT(!(p_head->p_next && !p_head->p_prev)); + + p_newnode->next = p_head->p_next; + p_newnode->prev = NULL;/*新节点前驱为NULL*/ + + if(p_head->p_next) + { + p_head->p_next->prev = p_newnode; + } + else + { + p_head->p_prev = p_newnode; + } + + p_head->p_next = p_newnode; + p_head->used++; + + + return ZXIC_OK; +} + +/*目的是配合sort函数实现相同节点无需重复写入*/ +ZXIC_RTN32 zxic_comm_double_link_insert_cmp(D_HEAD *p_head, void* cmp_data, ZXIC_UINT32 *is_same) +{ + D_NODE *p_dn = 0; + + *is_same = 0; + + p_dn = p_head->p_next; + + while(p_dn) + { + if(*(ZXIC_UINT32*)cmp_data == *(ZXIC_UINT32*)p_dn->data) + { + *is_same = 1; + + break; + } + + p_dn = p_dn->next; + } + + return ZXIC_OK; +} + +ZXIC_RTN32 zxic_comm_double_link_insert_merge(D_NODE *p_newnode,D_HEAD *p_head,ZXIC_UINT32 is_head) +{ + D_NODE *p_dn = 0; + ZXIC_UINT32 is_same = 0; + + p_dn = p_head->p_next; + + while(p_dn) + { + if(p_dn->data == p_newnode->data) + { + is_same = 1; + break; + } + + p_dn = p_dn->next; + } + + if(! is_same ) + { + if (is_head) + { + return zxic_comm_double_link_insert_1st(p_newnode, p_head); + } + else + { + return zxic_comm_double_link_insert_last(p_newnode, p_head); + } + } + + return ZXIC_OK; + +} + +/* 在OLD节点之后插入 */ +ZXIC_RTN32 zxic_comm_double_link_insert_aft(D_NODE *p_newnode,D_NODE *p_oldnode,D_HEAD*p_head) +{ + + + ZXIC_COMM_CHECK_POINT(p_newnode); + ZXIC_COMM_CHECK_POINT(p_oldnode); + ZXIC_COMM_CHECK_POINT(p_head); + + ZXIC_COMM_CHECK_INDEX((p_head->used+1), 1, p_head->maxnum); + + ZXIC_COMM_ASSERT(!(!p_head->p_next&& p_head->p_prev)); + ZXIC_COMM_ASSERT(!(p_head->p_next && !p_head->p_prev)); + + p_newnode->next = p_oldnode->next; + p_newnode->prev = p_oldnode; + + if(p_oldnode->next) + { + p_oldnode->next->prev = p_newnode; + } + else + { + p_head->p_prev = p_newnode; + } + + p_oldnode->next = p_newnode; + p_head->used++; + + return ZXIC_OK; +} + +/* 在OLD节点前插入 */ +ZXIC_RTN32 zxic_comm_double_link_insert_pre(D_NODE *p_newnode,D_NODE *p_oldnode,D_HEAD*p_head) +{ + + ZXIC_COMM_CHECK_POINT(p_newnode); + ZXIC_COMM_CHECK_POINT(p_oldnode); + ZXIC_COMM_CHECK_POINT(p_head); + + ZXIC_COMM_CHECK_INDEX((p_head->used+1), 1, p_head->maxnum); + + ZXIC_COMM_ASSERT(!(!p_head->p_next&& p_head->p_prev)); + ZXIC_COMM_ASSERT(!(p_head->p_next && !p_head->p_prev)); + + p_newnode->next = p_oldnode; + p_newnode->prev = p_oldnode->prev; + + if(p_oldnode->prev) + { + p_oldnode->prev->next = p_newnode; + } + else + { + p_head->p_next = p_newnode; + } + + p_oldnode->prev = p_newnode; + p_head->used++; + + return ZXIC_OK; +} +ZXIC_RTN32 zxic_comm_double_link_insert_last(D_NODE *p_newnode,D_HEAD* p_head) +{ + D_NODE *p_dnode = NULL; + + ZXIC_COMM_CHECK_POINT(p_newnode); + ZXIC_COMM_CHECK_POINT(p_head); + + ZXIC_COMM_CHECK_INDEX((p_head->used+1), 1, p_head->maxnum); + + ZXIC_COMM_ASSERT(!(!p_head->p_next&& p_head->p_prev)); + ZXIC_COMM_ASSERT(!(p_head->p_next && !p_head->p_prev)); + + + p_dnode = p_head->p_prev; + + + if(!p_dnode) + { + p_head->p_next = p_newnode; + p_head->p_prev = p_newnode; + p_newnode->next = NULL; + p_newnode->prev = NULL; + } + else + { + p_newnode->prev = p_dnode; + p_newnode->next = NULL; + p_head->p_prev = p_newnode; + p_dnode->next = p_newnode; + } + + p_head->used++; + + return ZXIC_OK; +} +ZXIC_RTN32 zxic_comm_double_link_del(D_NODE *delnode,D_HEAD *p_head) +{ + D_NODE *next = NULL; + D_NODE *pre = NULL; + + ZXIC_COMM_CHECK_POINT(delnode); + ZXIC_COMM_CHECK_POINT(p_head); + + ZXIC_COMM_CHECK_INDEX(p_head->used, 1, p_head->maxnum); + + next = delnode->next; + pre = delnode->prev; + + if(next) + { + next->prev = delnode->prev; + } + else + { + p_head->p_prev= delnode->prev; + } + + if(pre) + { + pre->next = delnode->next; + } + else + { + p_head->p_next = delnode->next; + } + + p_head->used--; + delnode->next = NULL; + delnode->prev = NULL; + return ZXIC_OK; +} + + +ZXIC_RTN32 zxic_comm_double_link_init(ZXIC_UINT32 elmemtnum,D_HEAD *p_head) +{ + ZXIC_UINT32 err_code = 0; + + + ZXIC_COMM_CHECK_POINT(p_head); + + if(elmemtnum == 0 ) + { + err_code = ZXIC_DOUBLE_LINK_INIT_ELEMENT_NUM_ERR; + ZXIC_COMM_TRACE_ERROR("\nError:[0x%x] zxic_doule_link_init Element Num Err !",err_code); + return err_code; + } + + p_head->maxnum = elmemtnum; + p_head->used = 0; + p_head->p_next = NULL; + p_head->p_prev = NULL; + + return ZXIC_OK; +} + +ZXIC_RTN32 zxic_comm_dlink_release(D_HEAD *p_head,fun_free fun) +{ + ZXIC_UINT32 rc = 0; + D_NODE *p_node = NULL; + + ZXIC_COMM_CHECK_POINT(p_head); + + while(p_head->used) + { + p_node = p_head->p_next; + + if(NULL != fun) + { + rc = fun(p_node->data); + ZXIC_COMM_CHECK_RC(rc, "fun"); + } + + rc = zxic_comm_double_link_del(p_node,p_head); + ZXIC_COMM_CHECK_RC(rc, "zxic_comm_double_link_del"); + + ZXIC_COMM_FREE(p_node); + } + + return ZXIC_OK; +} +/*connetc the s_list to d_list */ + +ZXIC_RTN32 zxic_comm_double_link_merge_list(D_HEAD *d_list,D_HEAD *s_list) +{ + if(d_list->p_prev) + { + d_list->p_prev->next = s_list->p_next; + } + else + { + ZXIC_COMM_ASSERT(!d_list->p_next); + d_list->p_next = s_list->p_next; + } + + if(s_list->p_next) + { + ZXIC_COMM_ASSERT(s_list->p_prev); + s_list->p_next->prev = d_list->p_prev; + d_list->p_prev = s_list->p_prev; + } + + d_list->used += s_list->used; + + return ZXIC_OK; +} +/********************************************************************* + * 函数名称：zxic_comm_double_link_insert_sort + * 功能描述: + * 函数功能简介 + * 插入排序， + * 输入参数： + * 输出参数： + * 返 回 值：ZXIC_RTN32 + * 全局变量： + * 注 释： +============================================================ + * 修改记录: + * 修改日期 版本号 修改人 修改内容 +============================================================ + * 2012-03-19 jiangwenming + + ******************************************************************/ +ZXIC_RTN32 zxic_comm_double_link_insert_sort(D_NODE *p_newnode,D_HEAD *p_head,CMP_FUNC cmp_fuc,void* cmp_data) +{ + D_NODE* pre_node = NULL; + + ZXIC_COMM_CHECK_POINT(p_head); + ZXIC_COMM_CHECK_POINT(p_newnode); + + if(NULL == cmp_fuc ) + { + cmp_fuc = zxic_comm_double_link_default_cmp_fuc; + } + + ZXIC_COMM_CHECK_INDEX((p_head->used+1), 1, p_head->maxnum); + + /*此时表中的数据，已经排序了，再插入时，只需从表头开始比较，然后插入适当位置*/ + if( 0 == p_head->used ) + { + return zxic_comm_double_link_insert_1st(p_newnode,p_head); + } + else + { + pre_node = p_head->p_next; + + while(NULL!=pre_node) + { + /*新节点的键值小于等于当前的键值*/ + if(cmp_fuc(p_newnode,pre_node,cmp_data) <= 0) + { + return zxic_comm_double_link_insert_pre(p_newnode,pre_node,p_head); + } + else + { + pre_node = pre_node->next; + } + } + + /*循环结束后，说明插入的节点大于链表中的所有节点，需要在尾部插入*/ + return zxic_comm_double_link_insert_last(p_newnode,p_head); + } +} + + +/********************************************************************* + * 函数名称：zxic_comm_double_link_del_pos + * 功能描述: + * 函数功能简介 + * 根据node中指定的信息删除节点 + * 输入参数： + * 输出参数： + * 返 回 值：ZXIC_RTN32 + * 全局变量： + * 注 释： 根据指定的信息，可能会删除多个 +============================================================ + * 修改记录: + * 修改日期 版本号 修改人 修改内容 +============================================================ + * 2020-11-11 徐晨曦 + + ******************************************************************/ +ZXIC_RTN32 zxic_comm_double_link_del_by_info(D_HEAD *p_head, void* cmp_data, CMP_FUNC cmp_fuc, ZXIC_UINT32 *p_deled_num) +{ + ZXIC_UINT32 rc = 0; + ZXIC_UINT32 is_same = 0; + + D_NODE *p; + D_NODE *p_cur_node = ZXIC_NULL; + + if(NULL == cmp_fuc ) + { + cmp_fuc = zxic_comm_double_link_default_cmp_fuc; + } + + p = p_head->p_next; + + while(p) + { + /*新节点的键值等于当前的键值*/ + if(cmp_fuc(cmp_data, p,cmp_data) == 0) + { + rc = zxic_comm_double_link_del(p, p_head); + ZXIC_COMM_CHECK_RC(rc, "zxic_comm_double_link_del"); + + p_cur_node = p; + p = p->next; + + ZXIC_COMM_FREE(p_cur_node); + is_same ++; + continue; + } + + p = p->next; + } + + if(0 == is_same) + { + return ZXIC_ERR; + } + + *p_deled_num = is_same; + + ZXIC_COMM_TRACE_DEBUG(" DOUBLE LINK DEL NUM %d \n", is_same); + + return ZXIC_OK; +} + +/********************************************************************* + * 函数名称：zxic_comm_double_link_del_pos + * 功能描述: + * 函数功能简介 + * 删除指定位置的数据 + * 输入参数： + * 输出参数： + * 返 回 值：ZXIC_RTN32 + * 全局变量： + * 注 释： +============================================================ + * 修改记录: + * 修改日期 版本号 修改人 修改内容 +============================================================ + * 2012-03-19 jiangwenming + + ******************************************************************/ +ZXIC_RTN32 zxic_comm_double_link_del_pos(D_HEAD *p_head,void* cmp_data,fun_free fun) +{ + ZXIC_UINT32 rc = 0; + ZXIC_UINT32 is_same = 0; + + D_NODE *p; + + p = p_head->p_next; + + while(p) + { + if(*(ZXIC_UINT32*)cmp_data == *(ZXIC_UINT32*)p->data) + { + is_same = 1; + + break; + } + + p = p->next; + } + + if(is_same) + { + rc = zxic_comm_double_link_del(p, p_head); + ZXIC_COMM_CHECK_RC(rc, "zxic_comm_double_link_del"); + + if(NULL != fun) + { + rc = fun(p->data); + ZXIC_COMM_CHECK_RC(rc, "fun"); + } + + ZXIC_COMM_FREE(p); + } + + return ZXIC_OK; +} + +/********************************************************************* + * 函数名称：zxic_comm_double_link_swap + * 功能描述: + * 函数功能简介 + * 交换链表中的两个节点 + * 输入参数： + * 输出参数： + * 返 回 值：ZXIC_RTN32 + * 全局变量： + * 注 释： +============================================================ + * 修改记录: + * 修改日期 版本号 修改人 修改内容 +============================================================ + * 2012-03-19 jiangwenming + + ******************************************************************/ +ZXIC_RTN32 zxic_comm_double_link_print(D_HEAD *p_head) +{ + + D_NODE *p_pre = NULL; + D_NODE *p_next = NULL; + + ZXIC_COMM_CHECK_POINT(p_head); + /*正向打印*/ + p_next = p_head->p_next; + ZXIC_COMM_PRINT("*************sequ order***********\n"); + + while(p_next) + { + ZXIC_COMM_PRINT("==>%d",*(ZXIC_UINT32*)(p_next->data)); + p_next=p_next->next; + } + + /*反向打印*/ + ZXIC_COMM_PRINT("\n\n*************reverve order***********\n"); + p_pre=p_head->p_prev; + + while(p_pre != NULL) + { + ZXIC_COMM_PRINT("==>%d",*(ZXIC_UINT32*)(p_pre->data)); + p_pre = p_pre->prev; + } + + return ZXIC_OK; + +} + +ZXIC_SINT32 zxic_comm_double_link_default_cmp_fuc(D_NODE* p_data1,D_NODE* p_data2,void* p_data) +{ + ZXIC_UINT32 data1= *(ZXIC_UINT32*)p_data1->data; + ZXIC_UINT32 data2= *(ZXIC_UINT32*)p_data2->data; + + if(data1>data2) + { + return 1; + } + else if(data1==data2) + { + return 0; + } + else + { + return -1; + } +} + +ZXIC_RTN32 zxic_comm_double_link_del_by_data(D_HEAD *p_head,ZXIC_VOID* cmp_data,fun_free fun) +{ + ZXIC_UINT32 rc = 0; + ZXIC_UINT32 is_same = 0; + + D_NODE *p; + + p = p_head->p_next; + + while(p) + { + if(cmp_data == p->data) + { + is_same = 1; + + break; + } + p = p->next; + } + + if(is_same) + { + rc = zxic_comm_double_link_del(p,p_head); + ZXIC_COMM_CHECK_RC(rc, "zxic_comm_double_link_del"); + if(NULL != fun) + { + rc = fun(p->data); + ZXIC_COMM_CHECK_RC(rc, "fun"); + } + + ZXIC_COMM_FREE(p); + } + else + { + ZXIC_COMM_TRACE_ERROR("\nError:data not exist. FUNCTION : %s!\n", __FUNCTION__); + } + + return ZXIC_OK; +} + + + + diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/comm/source/zxic_comm_index_fill.c b/src/net/drivers/net/ethernet/dinghai/en_np/comm/source/zxic_comm_index_fill.c new file mode 100644 index 0000000..c3d1da4 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/comm/source/zxic_comm_index_fill.c @@ -0,0 +1,420 @@ +/***************************************************************************** + * 版权所有 (C)2001-2015, 深圳市中兴通讯股份有限公司。 + * + * 文件名称： zxic_index_fill.c + * 文件标识： + * 内容摘要： 索引空位填充源代码头文件 + * 其它说明： + * 当前版本： + * 作 者： ChenWei10088471 + * 完成日期： + * 当前责任人-1： + * 当前责任人-2： + * + * DEPARTMENT : ASIC_FPGA_R&D_Dept + * MANUAL_PERCENT : 100% + *****************************************************************************/ +#include "zxic_common.h" +#include "zxic_comm_index_fill.h" +#include "zxic_comm_double_link.h" + +/***********************************************************/ +/** 释放数据节点 +* @param p_data +* +* @return +* @remark 无 +* @see +* @author ChenWei10088471 @date 2014/02/07 +************************************************************/ +ZXIC_RTN32 ic_comm_node_data_free(void *p_data) +{ + ZXIC_COMM_CHECK_POINT(p_data); + ZXIC_COMM_FREE(p_data); + + return ZXIC_OK; +} + +ZXIC_RTN32 zxic_comm_indexfill_init(INDEX_FILL_CFG *p_fill_cfg,ZXIC_UINT32 index_num,ZXIC_KEY_CMP_FUNC p_cmp_fun,INDEXFILL_SWAP_FUNC p_swap_fun,ZXIC_UINT32 key_len) +{ + ZXIC_UINT32 rtn = 0; + + p_fill_cfg->index_num = index_num; + p_fill_cfg->total_used = 0; + p_fill_cfg->swap_fun = p_swap_fun; + + rtn = zxic_comm_rb_init(&p_fill_cfg->fill_rb,0,key_len,p_cmp_fun); + ZXIC_COMM_CHECK_RC(rtn,"zxic_comm_rb_init"); + + return ZXIC_OK; +} +/* 前向挤压 */ +ZXIC_RTN32 zxic_comm_indexfill_handle_position_right(INDEX_FILL_CFG *p_fill_cfg,INDEX_FILL_NODE* p_start,INDEX_FILL_NODE* p_end) +{ + ZXIC_UINT32 rtn = 0; + + INDEX_FILL_NODE *p_cur_node = p_start; + INDEX_FILL_NODE *p_nxt_node = (INDEX_FILL_NODE *)STRUCT_ENTRY_POINT(p_cur_node->rb_node.tn_ln.next,ZXIC_RB_TN,tn_ln); + INDEX_FILL_NODE *p_pre_node = NULL; + + while(p_cur_node != p_end) + { + if(ICMINF_GET_NODE_LASTPOS(p_cur_node) + 1 < ICMINF_GET_NODE_FSTPOS(p_nxt_node)) + { + break; + } + else + { + p_cur_node = p_nxt_node; + + if(p_cur_node->rb_node.tn_ln.next) + { + p_nxt_node = (INDEX_FILL_NODE *)STRUCT_ENTRY_POINT(p_cur_node->rb_node.tn_ln.next,ZXIC_RB_TN,tn_ln); + } + } + } + + ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW(p_fill_cfg->index_num, 1); + if(p_cur_node == p_end && p_fill_cfg->index_num - 1 == ICMINF_GET_NODE_LASTPOS(p_end)) + { + return ZXIC_INDEX_FILL_FULL; + } + + p_pre_node = (INDEX_FILL_NODE *)STRUCT_ENTRY_POINT(p_cur_node->rb_node.tn_ln.prev,ZXIC_RB_TN,tn_ln); + + while(p_cur_node != p_start) + { + if(p_fill_cfg->swap_fun) + { + rtn = p_fill_cfg->swap_fun(ICMINF_GET_NODE_FSTPOS(p_cur_node),ICMINF_GET_NODE_LASTPOS(p_cur_node) + 1,p_fill_cfg); + } + + ICMINF_GET_NODE_FSTPOS(p_cur_node) = ICMINF_GET_NODE_FSTPOS(p_cur_node) + 1; + + p_cur_node = p_pre_node; + + if(p_cur_node->rb_node.tn_ln.prev) + { + p_pre_node = (INDEX_FILL_NODE *)STRUCT_ENTRY_POINT(p_cur_node->rb_node.tn_ln.prev,ZXIC_RB_TN,tn_ln); + } + } + + if(p_fill_cfg->swap_fun) + { + rtn = p_fill_cfg->swap_fun(ICMINF_GET_NODE_FSTPOS(p_start),ICMINF_GET_NODE_LASTPOS(p_start)+1,p_fill_cfg); + } + + ICMINF_GET_NODE_FSTPOS(p_start) = ICMINF_GET_NODE_FSTPOS(p_start) + 1; + + return rtn; +} +/* 后向挤压 */ +ZXIC_RTN32 zxic_comm_indexfill_handle_position_left(INDEX_FILL_CFG *p_fill_cfg,INDEX_FILL_NODE* p_start,INDEX_FILL_NODE* p_end) +{ + ZXIC_UINT32 rtn = 0; + + INDEX_FILL_NODE *p_cur_node = p_start; + INDEX_FILL_NODE *p_nxt_node = (INDEX_FILL_NODE *)STRUCT_ENTRY_POINT(p_cur_node->rb_node.tn_ln.prev,ZXIC_RB_TN,tn_ln); + INDEX_FILL_NODE *p_pre_node = NULL; + + while(p_cur_node != p_end) + { + ZXIC_COMM_CHECK_POINT(p_nxt_node); + ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(p_nxt_node->position, p_nxt_node->usednum); + ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW((p_nxt_node->position + p_nxt_node->usednum), 1); + + if(ICMINF_GET_NODE_FSTPOS(p_cur_node) -1 > ICMINF_GET_NODE_LASTPOS(p_nxt_node)) + { + break; + } + else + { + p_cur_node = p_nxt_node; + + if(p_cur_node->rb_node.tn_ln.prev) + { + p_nxt_node = (INDEX_FILL_NODE *)STRUCT_ENTRY_POINT(p_cur_node->rb_node.tn_ln.prev,ZXIC_RB_TN,tn_ln); + } + } + } + + if(p_cur_node == p_end && 0 == ICMINF_GET_NODE_FSTPOS(p_end)) + { + return ZXIC_INDEX_FILL_FULL; + } + + p_pre_node = (INDEX_FILL_NODE *)STRUCT_ENTRY_POINT(p_cur_node->rb_node.tn_ln.next,ZXIC_RB_TN,tn_ln); + + while(p_cur_node != p_start) + { + if(p_fill_cfg->swap_fun)/*将最后一个移动到本节点第一个*/ + { + rtn = p_fill_cfg->swap_fun(ICMINF_GET_NODE_LASTPOS(p_cur_node),ICMINF_GET_NODE_FSTPOS(p_cur_node)-1,p_fill_cfg); + + } + + ICMINF_GET_NODE_FSTPOS(p_cur_node) = ICMINF_GET_NODE_FSTPOS(p_cur_node)-1; + + p_cur_node = p_pre_node; + + if(p_cur_node->rb_node.tn_ln.next) + { + p_pre_node = (INDEX_FILL_NODE *)STRUCT_ENTRY_POINT(p_cur_node->rb_node.tn_ln.next,ZXIC_RB_TN,tn_ln); + } + } + + if(p_fill_cfg->swap_fun) + { + rtn = p_fill_cfg->swap_fun(ICMINF_GET_NODE_LASTPOS(p_start),ICMINF_GET_NODE_FSTPOS(p_start)-1,p_fill_cfg); + } + + ICMINF_GET_NODE_FSTPOS(p_start) = ICMINF_GET_NODE_FSTPOS(p_start) -1; + + return rtn; +} + +ZXIC_RTN32 zxic_comm_indexfill_free(INDEX_FILL_CFG *p_fill_cfg,ZXIC_UINT32 free_index,ZXIC_VOID* p_rb_key,ZXIC_UINT32 *out_index) +{ + ZXIC_UINT32 rtn = 0; + ZXIC_RB_TN *p_rb_out = NULL; + INDEX_FILL_NODE *p_inf_node = NULL; + + rtn = zxic_comm_rb_search(&p_fill_cfg->fill_rb, p_rb_key, &p_rb_out); + + if ((!p_rb_out)||(rtn!=ZXIC_OK) ) + { + ZXIC_COMM_TRACE_ERROR("\n srh fail ,the key is not exist"); + return ZXIC_INDEX_DEL_FAIL; + } + + p_inf_node = (INDEX_FILL_NODE *)p_rb_out; + + ZXIC_COMM_ASSERT(p_inf_node->usednum); + + ZXIC_COMM_CHECK_INDEX(free_index,ICMINF_GET_NODE_FSTPOS(p_inf_node),ICMINF_GET_NODE_LASTPOS(p_inf_node)); + + *out_index = free_index; + + if(free_index == ICMINF_GET_NODE_FSTPOS(p_inf_node)) + { + p_inf_node->position++; + } + else if(free_index != ICMINF_GET_NODE_LASTPOS(p_inf_node)) + { + *out_index = ICMINF_GET_NODE_FSTPOS(p_inf_node); + + if(p_fill_cfg->swap_fun) + { + p_fill_cfg->swap_fun(ICMINF_GET_NODE_FSTPOS(p_inf_node), free_index, p_fill_cfg); + } + + p_inf_node->position++; + } + else + { + ZXIC_COMM_TRACE_DEBUG("\n Free the last position,do nothing \n"); + } + + p_inf_node->usednum--; + + if(p_inf_node->usednum == 0) + { + rtn = zxic_comm_rb_delete(&p_fill_cfg->fill_rb,p_rb_key,&p_rb_out); + ZXIC_COMM_CHECK_RC(rtn,"zxic_comm_rb_delete"); + + if(!p_rb_out) + { + ZXIC_COMM_TRACE_ERROR("\n srh fail ,the key is not exist"); + return ZXIC_INDEX_DEL_FAIL; + } + + ZXIC_COMM_FREE(p_inf_node->rb_node.p_key); + + ZXIC_COMM_FREE(p_inf_node); + } + else + { + /*ICMINF_GET_NODE_FSTPOS(p_inf_node) = ICMINF_GET_NODE_FSTPOS(p_inf_node)-1;*/ + } + + ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW(p_fill_cfg->total_used, 1); + p_fill_cfg->total_used--; + + return ZXIC_OK; +} + +ZXIC_RTN32 zxic_comm_indexfill_destroy(INDEX_FILL_CFG *p_fill_cfg) +{ + ZXIC_UINT32 rtn = 0; + + rtn = zxic_comm_dlink_release(&p_fill_cfg->fill_rb.tn_list,ic_comm_node_data_free); + ZXIC_COMM_CHECK_RC(rtn,"zxic_comm_dlink_release"); + + ZXIC_COMM_MEMSET(p_fill_cfg,0,ZXIC_SIZEOF(INDEX_FILL_CFG)); + + return ZXIC_OK; +} + +ZXIC_RTN32 zxic_comm_indexfill_show_all_position(INDEX_FILL_CFG *p_fill_cfg) +{ + ZXIC_UINT32 i = 0; + ZXIC_UINT32 j = 0; + D_NODE *p_node = NULL; + INDEX_FILL_NODE *p_inf_node = NULL; + + p_node = p_fill_cfg->fill_rb.tn_list.p_next; + + ZXIC_COMM_PRINT("\n *************************Used Position*************************\n"); + + while(p_node) + { + ZXIC_COMM_PRINT("\n ==== Num [%d ] ==== :",i); + + p_inf_node = (INDEX_FILL_NODE *)(STRUCT_ENTRY_POINT(p_node,ZXIC_RB_TN,tn_ln)); + + for(j = 0 ;j < p_inf_node->usednum;j++) + { + ZXIC_COMM_PRINT(" %d ",ICMINF_GET_NODE_FSTPOS(p_inf_node)+ j); + + if (j != 0 && j % 8 == 0) + { + ZXIC_COMM_PRINT("\n "); + } + } + + ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(i, 1); + i++; + + p_node = p_node->next; + } + + ZXIC_COMM_PRINT("\n*******End*******\n"); + + return ZXIC_OK; + +} + +ZXIC_RTN32 zxic_comm_indexfill_store(INDEX_FILL_CFG *p_fill_cfg, ZXIC_UINT32 *p_size, ZXIC_UINT8 **p_data_buff) +{ + ZXIC_UINT32 rtn = 0; + ZXIC_UINT32 i = 0; + ZXIC_UINT32 used_node_num = 0; + ZXIC_UINT32 rb_node_size = 0; + ZXIC_UINT32 max_index_num = 0; + ZXIC_UINT32 buff_offset = 0; + ZXIC_UINT32 tmp_val = 0; + D_NODE *p_node = NULL; + INDEX_FILL_NODE *p_inf_node = NULL; + ZXIC_UINT8 *p_item_buff = NULL; + ZXIC_UINT32 item_buff_offset = 0; + /* + | used_node_num | rb_node_size | max_index_num |//head + | node_start_index | node_used_num | rb_key ... ... |//item + */ + + ZXIC_COMM_CHECK_POINT(p_fill_cfg); + ZXIC_COMM_CHECK_POINT(p_size); + //item size + rb_node_size = p_fill_cfg->fill_rb.key_size + 8;/*sizeof(ZXIC_UINT32) + sizeof(ZXIC_UINT32);*/ + max_index_num = p_fill_cfg->index_num; + + p_node = p_fill_cfg->fill_rb.tn_list.p_next; + + ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(used_node_num, 1); + while(p_node) + { + //p_inf_node = (INDEX_FILL_NODE *)(STRUCT_ENTRY_POINT(p_node,ZXIC_RB_TN,tn_ln)); + used_node_num++; + p_node = p_node->next; + } + tmp_val = ZXIC_SIZEOF(ZXIC_UINT32) * 3; + ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW(rb_node_size, used_node_num); + ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(tmp_val, rb_node_size * used_node_num); + *p_size = tmp_val + rb_node_size * used_node_num; + + *p_data_buff = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(*p_size); + ZXIC_COMM_CHECK_POINT(*p_data_buff); + ZXIC_COMM_MEMSET(*p_data_buff, 0, *p_size); + + buff_offset = 0; + + ZXIC_COMM_MEMCPY_S(*p_data_buff + buff_offset, ZXIC_SIZEOF(ZXIC_UINT32), &used_node_num, ZXIC_SIZEOF(ZXIC_UINT32)); + buff_offset += ZXIC_SIZEOF(ZXIC_UINT32); + ZXIC_COMM_MEMCPY_S(*p_data_buff + buff_offset, ZXIC_SIZEOF(ZXIC_UINT32), &rb_node_size, ZXIC_SIZEOF(ZXIC_UINT32)); + buff_offset += ZXIC_SIZEOF(ZXIC_UINT32); + ZXIC_COMM_MEMCPY_S(*p_data_buff + buff_offset, ZXIC_SIZEOF(ZXIC_UINT32), &max_index_num, ZXIC_SIZEOF(ZXIC_UINT32)); + buff_offset += ZXIC_SIZEOF(ZXIC_UINT32); + + p_item_buff = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(rb_node_size); + ZXIC_COMM_CHECK_POINT(p_item_buff); + ZXIC_COMM_MEMSET(p_item_buff, 0, rb_node_size); + + for(i = 0; i < used_node_num; i++) + { + if(0 == i) + { + p_node = p_fill_cfg->fill_rb.tn_list.p_next; + ZXIC_COMM_CHECK_POINT_MEMORY_FREE(p_node, p_item_buff); + } + else + { + p_node = p_node->next; + ZXIC_COMM_CHECK_POINT_MEMORY_FREE(p_node, p_item_buff); + } + item_buff_offset = 0; + + p_inf_node = (INDEX_FILL_NODE *)(STRUCT_ENTRY_POINT(p_node,ZXIC_RB_TN,tn_ln)); + + ZXIC_COMM_MEMCPY_S(p_item_buff + item_buff_offset, ZXIC_SIZEOF(ZXIC_UINT32), &(p_inf_node->position), ZXIC_SIZEOF(ZXIC_UINT32)); + item_buff_offset += ZXIC_SIZEOF(ZXIC_UINT32); + ZXIC_COMM_MEMCPY_S(p_item_buff + item_buff_offset, ZXIC_SIZEOF(ZXIC_UINT32), &(p_inf_node->usednum), ZXIC_SIZEOF(ZXIC_UINT32)); + item_buff_offset += ZXIC_SIZEOF(ZXIC_UINT32); + ZXIC_COMM_MEMCPY_S(p_item_buff + item_buff_offset, p_fill_cfg->fill_rb.key_size, p_inf_node->rb_node.p_key, p_fill_cfg->fill_rb.key_size); + + ZXIC_COMM_MEMCPY_S(*p_data_buff + buff_offset, rb_node_size, p_item_buff, rb_node_size); + + ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_MEMORY_FREE(buff_offset, rb_node_size, p_item_buff); + buff_offset += rb_node_size; + } + + ZXIC_COMM_ASSERT(buff_offset == *p_size); + + ZXIC_COMM_FREE(p_item_buff); + + return rtn; +} + +ZXIC_RTN32 zxic_comm_indexfill_clear(INDEX_FILL_CFG *p_fill_cfg) +{ + ZXIC_UINT32 rtn = 0; + ZXIC_UINT32 key_len = p_fill_cfg->fill_rb.key_size; + ZXIC_KEY_CMP_FUNC p_cmp_fun = p_fill_cfg->fill_rb.p_cmpfun; + INDEX_FILL_NODE *fill_node; + D_NODE *p_curnode = NULL; + void *cur_data; + p_curnode = p_fill_cfg->fill_rb.tn_list.p_next; + + while(p_curnode) + { + cur_data = p_curnode->data; + p_curnode = p_curnode->next; + fill_node = cur_data; + ZXIC_COMM_FREE(fill_node->rb_node.p_key); + ZXIC_COMM_FREE(fill_node); + + } + + rtn = zxic_comm_rb_destroy(&p_fill_cfg->fill_rb); + ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_rb_destroy"); + + rtn = zxic_comm_rb_init(&p_fill_cfg->fill_rb, 0, key_len, p_cmp_fun); + ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_rb_init"); + + + p_fill_cfg->total_used = 0; + + + return ZXIC_OK; +} + + diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/comm/source/zxic_comm_liststack.c b/src/net/drivers/net/ethernet/dinghai/en_np/comm/source/zxic_comm_liststack.c new file mode 100644 index 0000000..ae40a07 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/comm/source/zxic_comm_liststack.c @@ -0,0 +1,431 @@ +/***************************************************************************** + * 版权所有 (C)2001-2006, 深圳市中兴通讯股份有限公司。 + * + * 文件名称： Rtm_ListStack.c + * 文件标识： + * 内容摘要： 链表栈管理文件 + + * 其它说明： 链表栈的管理方式，后进先出,释放的元素挂到队头 + + * 当前版本： ZXR10 V2.6 + * 作 者： 郑纪伟 + * 完成日期： 2006-9-27 10:34 + * 当前责任人-1： + * 当前责任人-2： + * + * 修改记录1： + * 修改日期：2006-9-27 10:34 + * 版 本 号：ZXR10 V2.6 + * 修 改 人：郑纪伟 + * 修改内容：创建 + * + * 修改记录2： + * 文件名称：ftmcomm_liststack.c + * 修改日期：2008-10-16 15:08 + * 版 本 号：ZXR10 V2.6 + * 修 改 人：HuangHe 170389 + * 修改内容：移植到T8000项目使用 + * + *修改记录3： + * 修改文件名称：zxic_liststack.c + * 修改日期：2012-03-15 15:14 + * 版 本 号：ZXR10 V2.6 + * 修 改 人：JiangWenming 12010401 + * 修改内容：移植到NSE项目使用 + * + *****************************************************************************/ +#include "zxic_common.h" + + +ZXIC_RTN32 zxic_comm_liststack_creat(ZXIC_UINT32 element_num, ZXIC_LISTSTACK_MANGER** p_list) +{ + ZXIC_LISTSTACK_MANGER* p_local_list = NULL; + ZXIC_UINT32 dw_list_size = 0; + ZXIC_UINT32 dw_manage_size = 0; + ZXIC_UINT32 dw_actual_element_num = 0; + ZXIC_UINT32 i = 0; + + /*611002174859 zj068187 检查双重指针*/ + if (NULL == p_list) + { + ZXIC_COMM_PRINT("\n p_list is NULL!\n"); + return ZXIC_LIST_STACK_POINT_NULL; + + } + if(element_num <= 0) + { + *p_list = NULL; + ZXIC_COMM_PRINT( "\n FtmComm_ListStackCreat_dwElementNum <=0"); + return ZXIC_LIST_STACK_ELEMENT_NUM_ERR; + + } + + if(element_num>LISTSTACK_MAX_ELEMENT-1) + { + dw_actual_element_num = LISTSTACK_MAX_ELEMENT; + } + else + { + dw_actual_element_num = element_num + 1; /*10124041 index from 0*/ + } + + + + dw_list_size = (dw_actual_element_num * ZXIC_SIZEOF(ZXIC_COMM_FREELINK))&0xffffffff; + dw_manage_size = (ZXIC_SIZEOF(ZXIC_LISTSTACK_MANGER) + dw_list_size)&0xffffffff; + + p_local_list = (ZXIC_LISTSTACK_MANGER*)ZXIC_COMM_MALLOC(dw_manage_size); + + if(p_local_list == NULL) + { + *p_list = NULL; + ZXIC_COMM_PRINT( "\n zxic_comm_liststack_creat Fail \n"); + return ZXIC_LIST_STACK_ALLOC_MEMORY_FAIL; + + } + + ZXIC_COMM_MEMSET(p_local_list,0,dw_manage_size); + + p_local_list->p_array = (ZXIC_COMM_FREELINK*)((ZXIC_UINT8 *)p_local_list+ZXIC_SIZEOF(ZXIC_LISTSTACK_MANGER)); + + p_local_list->capacity = dw_actual_element_num; + p_local_list->free_num = dw_actual_element_num - 1; /* for index = 0 is reserved */ + p_local_list->used_num = 0; + + for(i=1; i<(dw_actual_element_num-1); i++) + { + p_local_list->p_array[i].index = i; + p_local_list->p_array[i].next = i+1; + } + + p_local_list->p_array[0].index = 0; + p_local_list->p_array[0].next = 0; + + p_local_list->p_array[dw_actual_element_num-1].index = dw_actual_element_num-1; + p_local_list->p_array[dw_actual_element_num-1].next = 0xffffffff; + + p_local_list->p_head = p_local_list->p_array[1].index; + + *p_list = p_local_list; + + return ZXIC_OK; + +} + + +ZXIC_RTN32 zxic_comm_liststack_alloc (ZXIC_LISTSTACK_MANGER* p_list,ZXIC_UINT32 *p_index) +{ + ZXIC_UINT32 dw_alloc_index = 0; + ZXIC_UINT32 dw_next_free = 0; + + if(p_list == NULL) + { + *p_index = LISTSTACK_INVALID_INDEX; + ZXIC_COMM_PRINT("\n zxic_comm_liststack_alloc! ERROR LINE:%d\n ",__LINE__); + return ZXIC_LIST_STACK_POINT_NULL; + + } + + if((p_list->p_head) == LISTSTACK_INVALID_INDEX) + { + *p_index = LISTSTACK_INVALID_INDEX; + + /*ZXIC_COMM_PRINT("\n zxic_comm_liststack_alloc is full! LINE:%d\n ",__LINE__);*/ + return ZXIC_LIST_STACK_ISEMPTY_ERR; + + } + + dw_alloc_index = p_list->p_head; + + dw_next_free = p_list->p_array[dw_alloc_index].next; + p_list->p_array[dw_alloc_index].next = LISTSTACK_INVALID_INDEX; + + if(dw_next_free != 0xffffffff) /* ZXIC_UINT32 - 1 为0xffffffff*/ + { + p_list->p_head = p_list->p_array[dw_next_free].index; + } + else + { + p_list->p_head = LISTSTACK_INVALID_INDEX; + } + + *p_index = dw_alloc_index - 1; /*减1是为了使索引从0开始分配*/ + + p_list->free_num--; + p_list->used_num++; + + /*分配一个条目后，判断队列是否变为空，若变为空，则头指向无效索引*/ + if((p_list->free_num == 0) || (p_list->used_num == (p_list->capacity-1))) + { + /*ZXIC_COMM_PRINT("\n zxic_comm_liststack_alloc! ERROR LINE:%d\n ",__LINE__);*/ + p_list->p_head = LISTSTACK_INVALID_INDEX; + } + + return ZXIC_OK; + +} + +ZXIC_RTN32 zxic_comm_liststack_free (ZXIC_LISTSTACK_MANGER* p_list,ZXIC_UINT32 index) +{ + ZXIC_UINT32 dw_free_index = 0; + ZXIC_UINT32 dw_prev_free = 0; + ZXIC_UINT32 dw_index = 0; + + ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(index, 1); + dw_index = index + 1; /*加1是为了使索引从0开始分配*/ + + if(p_list == NULL) + { + + ZXIC_COMM_PRINT("\n zxic_comm_liststack_free is null! LINE:%d\n ",__LINE__); + return ZXIC_LIST_STACK_POINT_NULL; + } + + + + if (dw_index >= p_list->capacity) + { + + ZXIC_COMM_PRINT("\n zxic_comm_liststack_free is null! LINE:%d\n ",__LINE__); + return ZXIC_LIST_STACK_FREE_INDEX_INVALID; + + } + + if(p_list->p_array[dw_index].next != LISTSTACK_INVALID_INDEX) + { + return ZXIC_OK; + } + + dw_free_index = dw_index; + dw_prev_free = p_list->p_head; + + if(dw_prev_free != 0) + { + p_list->p_array[dw_free_index].next = p_list->p_array[dw_prev_free].index; + } + else + { + p_list->p_array[dw_free_index].next = 0xffffffff; + } + + /* 释放的元素挂到队头*/ + p_list->p_head = p_list->p_array[dw_free_index].index; + + p_list->free_num++; + p_list->used_num--; + + return ZXIC_OK; + +} + +ZXIC_RTN32 zxic_comm_liststack_alloc_spec_index(ZXIC_LISTSTACK_MANGER* p_list, ZXIC_UINT32 index) +{ + ZXIC_UINT32 dw_free_index = 0; + ZXIC_UINT32 dw_index = 0; + + ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(index, 1); + dw_index = index + 1; //加1是为了使索引从0开始分配 + if(p_list == NULL) + { + ZXIC_COMM_PRINT("\n zxic_comm_liststack_alloc_spec_index: address is full! ERROR LINE:%d\n ",__LINE__); + return ZXIC_LIST_STACK_POINT_NULL; + } + + if((p_list->p_head) == LISTSTACK_INVALID_INDEX) + { + //ZXIC_COMM_PRINT("\n zxic_comm_liststack_alloc is full! LINE:%d\n ",__LINE__); + return ZXIC_LIST_STACK_ISEMPTY_ERR; + + } + + if(dw_index >= p_list->capacity) + { + ZXIC_COMM_PRINT("\n zxic_comm_liststack_alloc_spec_index: input invalid index! LINE:%d\n ",__LINE__); + return ZXIC_LIST_STACK_ALLOC_INDEX_INVALID; + } + + if(p_list->p_array[dw_index].next == LISTSTACK_INVALID_INDEX) + { + ZXIC_COMM_PRINT("\n zxic_comm_liststack_alloc_spec_index: index is used, not alloc again! LINE:%d\n ",__LINE__); + return ZXIC_LIST_STACK_ALLOC_INDEX_USED; + } + else + { + if(p_list->p_head == dw_index) + { + if(p_list->p_array[dw_index].next != 0xffffffff) + { + p_list->p_head = p_list->p_array[dw_index].next; + } + else + { + p_list->p_head = LISTSTACK_INVALID_INDEX; + } + } + else + { + dw_free_index = p_list->p_head; + while(p_list->p_array[dw_free_index].next != 0xffffffff) + { + if(p_list->p_array[dw_free_index].next == dw_index) + { + p_list->p_array[dw_free_index].next = p_list->p_array[dw_index].next; + break; + } + dw_free_index = p_list->p_array[dw_free_index].next; + } + } + + p_list->p_array[dw_index].next = LISTSTACK_INVALID_INDEX; + p_list->free_num--; + p_list->used_num++; + } + + /*分配一个条目后，判断队列是否变为空，若变为空，则头指向无效索引*/ + if((p_list->free_num == 0) || (p_list->used_num == (p_list->capacity-1))) + { + //ZXIC_COMM_PRINT("\n zxic_comm_liststack_alloc! ERROR LINE:%d\n ",__LINE__); + p_list->p_head = LISTSTACK_INVALID_INDEX; + } + + return ZXIC_OK; + +} + + +ZXIC_RTN32 zxic_comm_liststack_destroy(ZXIC_LISTSTACK_MANGER* p_list) +{ + if(p_list == NULL) + { + ZXIC_COMM_PRINT("\n zxic_comm_liststack_destroy! LINE:%d\n ",__LINE__); + return ZXIC_LIST_STACK_POINT_NULL; + } + ZXIC_COMM_FREE(p_list); + + return ZXIC_OK; + +} + +ZXIC_RTN32 zxic_comm_liststack_showlist_info (ZXIC_LISTSTACK_MANGER* p_list) +{ + ZXIC_COMM_PRINT( "\n\t List: 0x%p", (void*)p_list ); + ZXIC_COMM_PRINT( "\n\t Array: 0x%p", (void*)p_list->p_array ); + ZXIC_COMM_PRINT( "\n\t capacity: 0x%x", p_list->capacity ); + ZXIC_COMM_PRINT( "\n\t p_head: 0x%x", p_list->p_head ); + ZXIC_COMM_PRINT( "\n\t free_num: 0x%x", p_list->free_num ); + ZXIC_COMM_PRINT( "\n\t used_num: 0x%x\n", p_list->used_num ); + + return 0; +} + +ZXIC_RTN32 zxic_comm_liststack_show_used(ZXIC_LISTSTACK_MANGER* p_list, ZXIC_UINT32 line_number ) +{ + ZXIC_RTN32 rc = 0; + ZXIC_UINT32 i = 0; + ZXIC_UINT32 used_number = 0; + ZXIC_UINT32 dw_index = 0; + ZXIC_UINT32 dw_last_free_idx = 0; + + if(p_list == NULL) + { + ZXIC_COMM_PRINT ( "\n Please Input Param!" ); + return 0; + } + + if ( line_number == 0 ) + { + line_number = 32; + } + + rc = zxic_comm_liststack_showlist_info ( p_list ); + ZXIC_COMM_CHECK_RC(rc, "zxic_comm_liststack_showlist_info"); + ZXIC_COMM_PRINT ( "\n" ); + + /*611002175032 zj068187 begin*/ + if(LISTSTACK_INVALID_INDEX == p_list->p_head) + { + ZXIC_COMM_PRINT("\n The index are all used!\n"); + } + + dw_index = p_list->p_head; + ZXIC_COMM_CHECK_INDEX_UPPER(dw_index, (p_list->capacity - 1)); + while(LISTSTACK_INVALID_INDEX != p_list->p_array[dw_index].next) + { + dw_index = p_list->p_array[dw_index].next; + ZXIC_COMM_CHECK_INDEX_UPPER(dw_index, (p_list->capacity - 1)); + } + + dw_last_free_idx = p_list->p_array[dw_index].index; + /*611002175032 zj068187 end*/ + + for ( i = 1; i < p_list->capacity; i++ ) + { + /*611002175032 zj068187 modify*/ + if((LISTSTACK_INVALID_INDEX == p_list->p_array[i].next) + &&(dw_last_free_idx != p_list->p_array[i].index)) + { + ZXIC_COMM_PRINT ( " 0x%x", i ); + used_number++; + + if ( ( used_number % line_number ) == 0 ) + { + ZXIC_COMM_PRINT ( "\n" ); + } + } + } + + ZXIC_COMM_PRINT ( "\n used_number: 0x%x", used_number ); + + return ZXIC_OK; +} + +ZXIC_RTN32 zxic_comm_liststack_show_free (ZXIC_LISTSTACK_MANGER* p_list, ZXIC_UINT32 line_number ) +{ + ZXIC_RTN32 rc = 0; + ZXIC_UINT32 i = 0; + ZXIC_UINT32 index = 0; + ZXIC_UINT32 free_number = 0; + + if(p_list == NULL) + { + ZXIC_COMM_PRINT ( "\n Please Input Param!" ); + return 0; + } + + if ( line_number == 0 ) + { + line_number = 32; + } + + rc = zxic_comm_liststack_showlist_info ( p_list ); + ZXIC_COMM_CHECK_RC(rc, "zxic_comm_liststack_showlist_info"); + ZXIC_COMM_PRINT ( "\n" ); + + index = p_list->p_head; + + for ( i = p_list->capacity - 1; i != 0; i-- ) + { + if ( index != LISTSTACK_INVALID_INDEX ) + { + ZXIC_COMM_PRINT ( " 0x%x", index ); + free_number++; + + index = p_list->p_array[index].next; + + if ( ( free_number % line_number ) == 0 ) + { + ZXIC_COMM_PRINT ( "\n" ); + } + } + else + { + break; + } + } + + ZXIC_COMM_PRINT ( "\n free_number: 0x%x", free_number ); + + return ZXIC_OK; +} + + diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/comm/source/zxic_comm_mutex_lock.c b/src/net/drivers/net/ethernet/dinghai/en_np/comm/source/zxic_comm_mutex_lock.c new file mode 100644 index 0000000..91529d7 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/comm/source/zxic_comm_mutex_lock.c @@ -0,0 +1,179 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : zxic_sal.c +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : 王春雷 +* 完成日期 : 2014/02/07 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ + +#include "zxic_common.h" +#include "zxic_private.h" + +#ifdef ZXIC_OS_WIN +#define ZXIC_MUTEX_WAITTIME_MAX (INFINITE) /* 互斥锁最大等待时间 */ +#else +#define ZXIC_MUTEX_WAITTIME_MAX (5000) /* 互斥锁最大等待时间:5000ms */ +#endif + +/***********************************************************/ +/** 初始化互斥量 +* @param p_mutex 互斥量 +* +* @return +* @remark 无 +* @see +* @author 王春雷 @date 2014/02/07 +************************************************************/ +ZXIC_RTN32 zxic_comm_mutex_create(ZXIC_MUTEX_T *p_mutex) +{ + // ZXIC_SINT32 rc = 0; + + ZXIC_COMM_CHECK_POINT(p_mutex); + +#ifdef ZXIC_OS_WIN + p_mutex->mutex = CreateMutex(ZXIC_NULL, ZXIC_FALSE, ZXIC_NULL); + if(p_mutex->mutex == 0) + { + ZXIC_COMM_TRACE_ERROR("\nErrCode[ 0x%x ]: Create mutex failed.", ZXIC_MUTEX_LOCK_INIT_FAIL); + return ZXIC_MUTEX_LOCK_INIT_FAIL; + } +#else + /*rc = pthread_mutex_init(&p_mutex->mutex, NULL); + if(rc != 0) + { + ZXIC_COMM_TRACE_ERROR("\nErrCode[ 0x%x ]: Create mutex failed", ZXIC_MUTEX_LOCK_INIT_FAIL); + return ZXIC_MUTEX_LOCK_INIT_FAIL; + }*/ + mutex_init(&p_mutex->mutex); +#endif + + return ZXIC_OK; +} + +/***********************************************************/ +/** 互斥量加锁 +* @param p_mutex +* +* @return +* @remark 无 +* @see +* @author 王春雷 @date 2014/02/07 +************************************************************/ +ZXIC_RTN32 zxic_comm_mutex_lock(ZXIC_MUTEX_T *p_mutex) +{ + ZXIC_SINT32 rc = 0; +#ifndef ZXIC_FOR_FUZZER + ZXIC_COMM_CHECK_POINT(p_mutex); + + #ifdef ZXIC_OS_WIN + switch(WaitForSingleObject(p_mutex->mutex, ZXIC_MUTEX_WAITTIME_MAX)) + { + case (WAIT_OBJECT_0): + { + /* wait mutex success. */ + break; + } + default: + { + ZXIC_COMM_TRACE_ERROR("\nErrCode[ 0x%x ]: WaitForSingleObject failed.", ZXIC_MUTEX_LOCK_LOCK_FAIL); + ZXIC_COMM_ASSERT(0); + return ZXIC_MUTEX_LOCK_LOCK_FAIL; + } + } + #else + /*rc = pthread_mutex_lock(&p_mutex->mutex); + if(rc != 0) + { + ZXIC_COMM_TRACE_ERROR("\nErrCode[ 0x%x ]: Get mutex lock fail.", ZXIC_MUTEX_LOCK_LOCK_FAIL); + //ZXIC_COMM_ASSERT(0); + //return ZXIC_MUTEX_LOCK_LOCK_FAIL; + return rc; + }*/ + mutex_lock(&p_mutex->mutex); + #endif +#endif + + return rc; +} + +/***********************************************************/ +/** 互斥量解锁 +* @param p_mutex +* +* @return +* @remark 无 +* @see +* @author 王春雷 @date 2014/02/07 +************************************************************/ +ZXIC_RTN32 zxic_comm_mutex_unlock(ZXIC_MUTEX_T *p_mutex) +{ + ZXIC_SINT32 rc = 0; +#ifndef ZXIC_FOR_FUZZER + + ZXIC_COMM_CHECK_POINT(p_mutex); + + #ifdef ZXIC_OS_WIN + if(!ReleaseMutex(p_mutex->mutex)) + { + ZXIC_COMM_TRACE_ERROR("\nErrCode[ 0x%x ]: ReleaseMutex failed.", ZXIC_MUTEX_LOCK_ULOCK_FAIL); + return ZXIC_MUTEX_LOCK_ULOCK_FAIL; + } + #else + /*rc = pthread_mutex_unlock(&p_mutex->mutex); + if(rc != 0) + { + ZXIC_COMM_TRACE_ERROR("\nErrCode[ 0x%x ]: Release mutex lock fail.", ZXIC_MUTEX_LOCK_ULOCK_FAIL); + return ZXIC_MUTEX_LOCK_ULOCK_FAIL; + }*/ + mutex_unlock(&p_mutex->mutex); + #endif +#endif + + return rc; +} + +/***********************************************************/ +/** 销毁互斥量 +* @param p_mutex +* +* @return +* @remark 无 +* @see +* @author 王春雷 @date 2014/02/07 +************************************************************/ +ZXIC_RTN32 zxic_comm_mutex_destroy(ZXIC_MUTEX_T *p_mutex) +{ + // ZXIC_SINT32 rc = 0; + + ZXIC_COMM_CHECK_POINT(p_mutex); + +#ifdef ZXIC_OS_WIN + if(p_mutex->mutex == 0) + { + ZXIC_COMM_TRACE_ERROR("\nErrCode[ 0x%x ]: Destroy mutex failed.", ZXIC_MUTEX_LOCK_DESTROY_FAIL); + return ZXIC_MUTEX_LOCK_DESTROY_FAIL; + } + CloseHandle(p_mutex->mutex); +#else + /*rc = pthread_mutex_destroy(&p_mutex->mutex); + if(rc != 0) + { + ZXIC_COMM_TRACE_ERROR("\nErrCode[ 0x%x ]: Destroy mutex fail", ZXIC_MUTEX_LOCK_DESTROY_FAIL); + return ZXIC_MUTEX_LOCK_DESTROY_FAIL; + }*/ + mutex_destroy(&p_mutex->mutex); +#endif + + return ZXIC_OK; +} \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/comm/source/zxic_comm_print.c b/src/net/drivers/net/ethernet/dinghai/en_np/comm/source/zxic_comm_print.c new file mode 100644 index 0000000..64a6f74 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/comm/source/zxic_comm_print.c @@ -0,0 +1,446 @@ +/************************************************************** +* 版权所有 (C)2013-2020, 深圳市中兴通讯股份有限公司 +* 文件名称 : zxic_comm_print.c +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : xuchenxi_10235594 +* 完成日期 : 2020/07/20 +* DEPARTMENT: 有线开发四部-系统软件团队 +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ +#include "zxic_common.h" +#include "zxic_private.h" +#include "log.h" + +#if ZXIC_REAL("全局变量定义") +ZXIC_UINT32 g_zxic_print_level = ZXIC_TRACE_ERROR_PRINT; /*打印级别,默认为INFO*/ +ZXIC_UINT32 g_zxic_print_en = 1; /*界面打印控制开关*/ +#endif + +#if ZXIC_REAL("开关") +/***********************************************************/ +/** 设置打印开关，决定ZXIC_COMM_PRINT等调试打印函数是否输出到屏幕 +* @param enable 0-不打印到屏幕，1-打印到屏幕 +* +* @return +* @remark 无 +* @see +* @author zhaisyu @date 2018/10/25 +************************************************************/ +ZXIC_VOID zxic_comm_set_print_en(ZXIC_UINT32 enable) +{ + g_zxic_print_en = enable; +} + +ZXIC_RTN32 zxic_comm_get_print_en(ZXIC_VOID) +{ + return g_zxic_print_en; +} + +/***********************************************************/ +/** 设置Debug打印级别 +* @param debug_level 0打印级别最低，4打印级别最高，即打印的东西最多 +* +* @return +* @remark 无 +* @see +* @author ChenWei10088471 @date 2014/02/07 +************************************************************/ +ZXIC_VOID zxic_comm_set_print_level(ZXIC_UINT32 debug_level) +{ + g_zxic_print_level = debug_level; +} + +/***********************************************************/ +/** 获取Debug打印级别 +* @param ZXIC_VOID +* +* @return +* @remark 无 +* @see +* @author ChenWei10088471 @date 2014/02/07 +************************************************************/ +ZXIC_RTN32 zxic_comm_get_print_level(ZXIC_VOID) +{ + return g_zxic_print_level; +} + +#endif + +#if ZXIC_REAL("打印函数") +ZXIC_VOID ZXIC_COMM_PRINT(ZXIC_CONST ZXIC_CHAR *format, ...) +{ + va_list ap; + ZXIC_CHAR szBuffer[1024]; + + ZXIC_COMM_ASSERT(format); + + va_start(ap, format); + { + ZXIC_COMM_VSNPRINTF_S(szBuffer, ZXIC_SIZEOF(szBuffer), ZXIC_SIZEOF(szBuffer), format, ap); + if (g_zxic_print_en) + { + DH_LOG_INFO(MODULE_NP, "%s", szBuffer); + } + } + va_end(ap); +} + +/***********************************************************/ +/** Error信息打印函数 +* @param format +* +* @return +* @remark 无 +* @see +* @author ChenWei10088471 @date 2014/02/07 +************************************************************/ +ZXIC_VOID ZXIC_COMM_TRACE_ERROR(ZXIC_CONST ZXIC_CHAR *format, ...) +{ + va_list ap; + ZXIC_CHAR szBuffer[1024]; + + ZXIC_COMM_ASSERT(format); + + if (zxic_comm_get_print_level() == 0 || zxic_comm_get_print_level() >= ZXIC_TRACE_INVALID_PRINT) + { + return; + } + + va_start(ap, format); + { + ZXIC_COMM_VSNPRINTF_S(szBuffer, ZXIC_SIZEOF(szBuffer), 1024, format, ap); + if (zxic_comm_get_print_en()) + { + DH_LOG_ERR(MODULE_NP, "%s", szBuffer); + } + } + va_end(ap); +} + +/***********************************************************/ +/** Info信息打印函数 +* @param format +* +* @return +* @remark 无 +* @see +* @author ChenWei10088471 @date 2014/02/07 +************************************************************/ +ZXIC_VOID ZXIC_COMM_TRACE_INFO(ZXIC_CONST ZXIC_CHAR *format, ...) +{ + va_list ap; + ZXIC_CHAR szBuffer[1024]; + + ZXIC_COMM_ASSERT(format); + + if (zxic_comm_get_print_level() == 0 || zxic_comm_get_print_level() >= ZXIC_TRACE_INVALID_PRINT) + { + return; + } + + if (zxic_comm_get_print_level() >= ZXIC_TRACE_INFO_PRINT) + { + va_start(ap, format); + { + ZXIC_COMM_VSNPRINTF_S(szBuffer, ZXIC_SIZEOF(szBuffer), 1024, format, ap); + if (zxic_comm_get_print_en()) + { + DH_LOG_INFO(MODULE_NP, "%s", szBuffer); + } + } + va_end(ap); + } +} + +/***********************************************************/ +/** Debug信息打印函数 +* @param format +* +* @return +* @remark 无 +* @see +* @author ChenWei10088471 @date 2014/02/07 +************************************************************/ +ZXIC_VOID ZXIC_COMM_TRACE_DEBUG(ZXIC_CONST ZXIC_CHAR *format, ...) +{ + va_list ap; + ZXIC_CHAR szBuffer[1024]; + + ZXIC_COMM_ASSERT(format); + + if (zxic_comm_get_print_level() == 0 || zxic_comm_get_print_level() >= ZXIC_TRACE_INVALID_PRINT) + { + return; + } + + if (zxic_comm_get_print_level() >= ZXIC_TRACE_DEBUG_PRINT) + { + va_start(ap, format); + { + ZXIC_COMM_VSNPRINTF_S(szBuffer, ZXIC_SIZEOF(szBuffer), 1024, format, ap); + if (zxic_comm_get_print_en()) + { + DH_LOG_DEBUG(MODULE_NP, "%s", szBuffer); + } + } + va_end(ap); + } +} + +/***********************************************************/ +/** 所有调试信息打印函数 +* @param format +* +* @return +* @remark 无 +* @see +* @author ChenWei10088471 @date 2014/02/07 +************************************************************/ +ZXIC_VOID ZXIC_COMM_TRACE_ALL(ZXIC_CONST ZXIC_CHAR *format, ...) +{ + va_list ap; + ZXIC_CHAR szBuffer[1024]; + + ZXIC_COMM_ASSERT(format); + + if (zxic_comm_get_print_level() == 0 || zxic_comm_get_print_level() >= ZXIC_TRACE_INVALID_PRINT) + { + return; + } + + if (zxic_comm_get_print_level() >= ZXIC_TRACE_ALL_PRINT) + { + va_start(ap, format); + { + ZXIC_COMM_VSNPRINTF_S(szBuffer, ZXIC_SIZEOF(szBuffer), 1024, format, ap); + if (zxic_comm_get_print_en()) + { + DH_LOG_DEBUG(MODULE_NP, "%s", szBuffer); + } + } + va_end(ap); + } +} + +/***********************************************************/ +/** 支持多芯片的Error信息打印函数 +* 打印级别为1及以上时执行打印 +* @param dev_id +* @param format +* +* @return +* @remark 无 +* @see +* @author xcx @date 2020/07/20 +************************************************************/ +ZXIC_VOID ZXIC_COMM_TRACE_DEV_ERROR(ZXIC_UINT32 dev_id, ZXIC_CONST ZXIC_CHAR *format, ...) +{ + va_list ap; + ZXIC_CHAR szBuffer[768 - 32] = {0}; + ZXIC_CHAR devBuffer[1024] = {0}; + + ZXIC_COMM_ASSERT(format); + + if (zxic_comm_get_print_level() == 0 || zxic_comm_get_print_level() >= ZXIC_TRACE_INVALID_PRINT || dev_id > 3) + { + return; + } + + if (zxic_comm_get_print_level() >= ZXIC_TRACE_ERROR_PRINT) + { + ZXIC_COMM_SNPRINTF_S(devBuffer, ZXIC_SIZEOF(devBuffer), ZXIC_SIZEOF(devBuffer), "Dev_id[%u]_ERROR: ", dev_id); + + va_start(ap, format); + { + ZXIC_COMM_VSNPRINTF_S(szBuffer, ZXIC_SIZEOF(szBuffer), ZXIC_SIZEOF(szBuffer), format, ap); + ZXIC_COMM_STRNCAT_S(devBuffer, 1024, szBuffer, ZXIC_COMM_STRNLEN_S(szBuffer, ZXIC_SIZEOF(szBuffer))); + + if (zxic_comm_get_print_en()) + { + DH_LOG_ERR(MODULE_NP, "%s", devBuffer); + } + } + va_end(ap); + } +} + +/***********************************************************/ +/** 支持多芯片的Info信息打印函数 +* 打印级别为2及以上时执行打印 +* @param dev_id +* @param format +* +* @return +* @remark 无 +* @see +* @author wcl @date 2018/09/08 +************************************************************/ +ZXIC_VOID ZXIC_COMM_TRACE_DEV_INFO(ZXIC_UINT32 dev_id, ZXIC_CONST ZXIC_CHAR *format, ...) +{ + va_list ap; + ZXIC_CHAR szBuffer[768 - 32] = {0}; + ZXIC_CHAR devBuffer[1024] = {0}; + + ZXIC_COMM_ASSERT(format); + + if (zxic_comm_get_print_level() == 0 || zxic_comm_get_print_level() >= ZXIC_TRACE_INVALID_PRINT || dev_id > 3) + { + return; + } + + if (zxic_comm_get_print_level() >= ZXIC_TRACE_INFO_PRINT) + { + ZXIC_COMM_SNPRINTF_S(devBuffer, ZXIC_SIZEOF(devBuffer), ZXIC_SIZEOF(devBuffer), "Dev_id[%u]_INFO: ", dev_id); + + va_start(ap, format); + { + ZXIC_COMM_VSNPRINTF_S(szBuffer, ZXIC_SIZEOF(szBuffer), ZXIC_SIZEOF(szBuffer), format, ap); + ZXIC_COMM_STRNCAT_S(devBuffer, 1024, szBuffer, ZXIC_COMM_STRNLEN_S(szBuffer, ZXIC_SIZEOF(szBuffer))); + + if (zxic_comm_get_print_en()) + { + DH_LOG_INFO(MODULE_NP, "%s", devBuffer); + } + } + va_end(ap); + } +} + +/***********************************************************/ +/** 支持多芯片的Debug信息打印函数 +* @param dev_id +* @param format +* +* @return +* @remark 无 +* @see +* @author wcl @date 2018/09/08 +************************************************************/ +ZXIC_VOID ZXIC_COMM_TRACE_DEV_DEBUG(ZXIC_UINT32 dev_id,ZXIC_CONST ZXIC_CHAR *format, ...) +{ + va_list ap; + ZXIC_CHAR szBuffer[768 - 32] = {0}; + ZXIC_CHAR devBuffer[1024] = {0}; + + ZXIC_COMM_ASSERT(format); + + if (zxic_comm_get_print_level() == 0 || zxic_comm_get_print_level() >= ZXIC_TRACE_INVALID_PRINT || dev_id > 3) + { + return; + } + + if (zxic_comm_get_print_level() >= ZXIC_TRACE_DEBUG_PRINT) + { + ZXIC_COMM_SNPRINTF_S(devBuffer, ZXIC_SIZEOF(devBuffer), ZXIC_SIZEOF(devBuffer), "Dev_id[%u]_DEBUG: ", dev_id); + + va_start(ap, format); + { + ZXIC_COMM_VSNPRINTF_S(szBuffer, ZXIC_SIZEOF(szBuffer), ZXIC_SIZEOF(szBuffer), format, ap); + ZXIC_COMM_STRNCAT_S(devBuffer, 1024, szBuffer, ZXIC_COMM_STRNLEN_S(szBuffer, ZXIC_SIZEOF(szBuffer))); + + if (zxic_comm_get_print_en()) + { + DH_LOG_DEBUG(MODULE_NP, "%s", devBuffer); + } + } + va_end(ap); + } +} + +/***********************************************************/ +/** 支持多芯片的所有调试信息打印函数 +* @param dev_id +* @param format +* +* @return +* @remark 无 +* @see +* @author wcl @date 2018/09/08 +************************************************************/ +ZXIC_VOID ZXIC_COMM_TRACE_DEV_ALL(ZXIC_UINT32 dev_id, ZXIC_CONST ZXIC_CHAR *format, ...) +{ + va_list ap; + ZXIC_CHAR szBuffer[768 - 32] = {0}; + ZXIC_CHAR devBuffer[1024] = {0}; + + ZXIC_COMM_ASSERT(format); + + if (zxic_comm_get_print_level() == 0 || zxic_comm_get_print_level() >= ZXIC_TRACE_INVALID_PRINT || dev_id > 3) + { + return; + } + + if (zxic_comm_get_print_level() >= ZXIC_TRACE_ALL_PRINT) + { + ZXIC_COMM_SNPRINTF_S(devBuffer, ZXIC_SIZEOF(devBuffer), ZXIC_SIZEOF(devBuffer), "Dev_id[%u]_ALL:", dev_id); + + va_start(ap, format); + { + ZXIC_COMM_VSNPRINTF_S(szBuffer, ZXIC_SIZEOF(szBuffer), ZXIC_SIZEOF(szBuffer), format, ap); + ZXIC_COMM_STRNCAT_S(devBuffer, 1024, szBuffer, ZXIC_COMM_STRNLEN_S(szBuffer, ZXIC_SIZEOF(szBuffer))); + + if (zxic_comm_get_print_en()) + { + DH_LOG_DEBUG(MODULE_NP, "%s", devBuffer); + } + } + va_end(ap); + } +} +#endif + +#if ZXIC_REAL("") + +ZXIC_VOID ZXIC_COMM_DBGCNT64_PRINT(ZXIC_CONST ZXIC_CHAR * name, ZXIC_UINT64 value) +{ + ZXIC_CHAR temp_buff[50] = {0}; + + if (-1 == ZXIC_COMM_SNPRINTF_S(temp_buff, 50, 50, "0x%016llx", value)) + { + return; + } + + ZXIC_COMM_PRINT("%-50s : %18s\n", name, temp_buff); +} + +ZXIC_VOID ZXIC_COMM_DBGCNT32_PRINT(ZXIC_CONST ZXIC_CHAR * name, ZXIC_UINT32 value) +{ + ZXIC_CHAR temp_buff[50] = {0}; + + if (-1 == ZXIC_COMM_SNPRINTF_S(temp_buff, 50, 50, "0x%08x", value)) + { + return; + } + + ZXIC_COMM_PRINT("%-50s : %18s\n", name, temp_buff); +} + +/** 双参数打印 */ +ZXIC_VOID ZXIC_COMM_DBGCNT32_PAR_PRINT(ZXIC_CONST ZXIC_CHAR * name, ZXIC_UINT32 parm, ZXIC_UINT32 value) +{ + ZXIC_CHAR temp_buff[50] = {0}; + ZXIC_CHAR vlaue_buff[18] = {0}; + + if (-1 == ZXIC_COMM_SNPRINTF_S(temp_buff, 50, 50, name, parm)) + { + return; + } + + if (-1 == ZXIC_COMM_SNPRINTF_S(vlaue_buff, 18, 18, "0x%08x", value)) + { + return; + } + + ZXIC_COMM_PRINT("%-50s : %18s\n", temp_buff, vlaue_buff); +} + +#endif \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/comm/source/zxic_comm_rb_tree.c b/src/net/drivers/net/ethernet/dinghai/en_np/comm/source/zxic_comm_rb_tree.c new file mode 100644 index 0000000..5ae63c9 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/comm/source/zxic_comm_rb_tree.c @@ -0,0 +1,1059 @@ +/***************************************************************************** + * 版权所有 (C)2001-2015, 深圳市中兴通讯股份有限公司。 + * + * 文件名称： zxic_comm_rb_tree.c + * 文件标识： + * 内容摘要： + * 其它说明： + * 当前版本： + * 作 者： ChenWei10088471 + * 完成日期： + * 当前责任人-1： + * 当前责任人-2： + * + * DEPARTMENT : ASIC_FPGA_R&D_Dept + * MANUAL_PERCENT : 100% + *****************************************************************************/ +#include "zxic_common.h" +#include "zxic_comm_rb_tree.h" +#include "zxic_comm_double_link.h" + +ZXIC_SINT32 zxic_comm_rb_def_cmp(ZXIC_VOID *p_new, ZXIC_VOID *p_old, ZXIC_UINT32 key_size) +{ + return ZXIC_COMM_MEMCMP(p_new, p_old, key_size); +} + +ZXIC_RTN32 zxic_comm_rb_init(ZXIC_RB_CFG *p_rb_cfg, + ZXIC_UINT32 total_num, + ZXIC_UINT32 key_size, + ZXIC_RB_CMPFUN cmpfun ) +{ + ZXIC_UINT32 rtn = ZXIC_OK; + ZXIC_UINT32 malloc_size = 0; + ZXIC_UINT32 memset_size = 0; + + ZXIC_COMM_CHECK_POINT(p_rb_cfg); + if (p_rb_cfg->is_init) + { + ZXIC_COMM_TRACE_ERROR("\n zxic_comm_rb_init already init!"); + return ZXIC_OK; + } + + p_rb_cfg->key_size = key_size; + p_rb_cfg->p_root = NULL; + + if (cmpfun) + { + p_rb_cfg->p_cmpfun = cmpfun; + } + else + { + p_rb_cfg->p_cmpfun = zxic_comm_rb_def_cmp; + } + + if (total_num) + { + p_rb_cfg->is_dynamic = 0; + + rtn = zxic_comm_double_link_init(total_num, &p_rb_cfg->tn_list); + ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_double_link_init"); + + rtn = zxic_comm_liststack_creat(total_num, &p_rb_cfg->p_lsm); + ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_liststack_creat"); + + p_rb_cfg->p_keybase = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(total_num * p_rb_cfg->key_size); + ZXIC_COMM_CHECK_POINT(p_rb_cfg->p_keybase); + memset_size = total_num * p_rb_cfg->key_size; + ZXIC_COMM_MEMSET(p_rb_cfg->p_keybase, 0, memset_size); + + malloc_size = (ZXIC_SIZEOF(ZXIC_RB_TN) * total_num) & ZXIC_UINT32_MASK; + + p_rb_cfg->p_tnbase = (ZXIC_RB_TN*)ZXIC_COMM_MALLOC(malloc_size); + ZXIC_COMM_CHECK_POINT(p_rb_cfg->p_tnbase); + ZXIC_COMM_MEMSET(p_rb_cfg->p_tnbase, 0, total_num * ZXIC_SIZEOF(ZXIC_RB_TN)); + } + else /*totalnum = 0 indicate that customer manage the memory*/ + { + p_rb_cfg->is_dynamic = 1; + + rtn = zxic_comm_double_link_init(0xFFFFFFFF, &p_rb_cfg->tn_list); + ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_double_link_init"); + } + p_rb_cfg->is_init = 1; + + return ZXIC_OK; +} + +ZXIC_RTN32 zxic_comm_rb_destroy(ZXIC_RB_CFG *p_rb_cfg) +{ + ZXIC_UINT32 rtn = 0; + + ZXIC_COMM_CHECK_POINT(p_rb_cfg); + /*静态才使用*/ + if (0 == p_rb_cfg->is_dynamic) + { + zxic_comm_liststack_destroy(p_rb_cfg->p_lsm); + } + if (NULL != p_rb_cfg->p_keybase) + { + ZXIC_COMM_FREE(p_rb_cfg->p_keybase); + p_rb_cfg->p_keybase = NULL; + } + + if (NULL != p_rb_cfg->p_tnbase) + { + ZXIC_COMM_FREE(p_rb_cfg->p_tnbase); + p_rb_cfg->p_tnbase = NULL; + } + + ZXIC_COMM_MEMSET(p_rb_cfg, 0, ZXIC_SIZEOF(ZXIC_RB_CFG)); + + return rtn; +} + +ZXIC_VOID zxic_comm_rb_swich_color(ZXIC_RB_TN *p_tn1, ZXIC_RB_TN *p_tn2) +{ + ZXIC_UINT32 color1, color2; + + ZXIC_COMM_CHECK_POINT_NONE(p_tn1); + ZXIC_COMM_CHECK_POINT_NONE(p_tn2); + + color1 = GET_TN_COLOR(p_tn1); + color2 = GET_TN_COLOR(p_tn2); + + SET_TN_COLOR(p_tn1, color2); + SET_TN_COLOR(p_tn2, color1); + + return; +} + + +ZXIC_RB_TN* zxic_comm_rb_get_brotn(ZXIC_RB_TN *p_cur_tn) +{ + ZXIC_COMM_CHECK_POINT_RETURN_NULL(p_cur_tn); + ZXIC_COMM_CHECK_POINT_RETURN_NULL(p_cur_tn->p_parent); + + return (p_cur_tn->p_parent->p_left == p_cur_tn) ? p_cur_tn->p_parent->p_right : p_cur_tn->p_parent->p_left; +} + + +ZXIC_RTN32 zxic_comm_rb_handle_ins(ZXIC_RB_CFG *p_rb_cfg, + ZXIC_RB_TN ***stack_tn, + ZXIC_UINT32 stack_top) +{ + ZXIC_RB_TN **pp_cur_tn = NULL; + ZXIC_RB_TN *p_cur_tn = NULL; + ZXIC_RB_TN **pp_tmp_tn = NULL; + ZXIC_RB_TN *p_tmp_tn = NULL; + + ZXIC_COMM_CHECK_POINT(p_rb_cfg); + ZXIC_COMM_CHECK_POINT(stack_tn); + + while (stack_top > 0) + { + pp_cur_tn = stack_tn[stack_top]; + p_cur_tn = *pp_cur_tn; + + if (!p_cur_tn->p_parent) /*root must be black*/ + { + SET_TN_COLOR(p_cur_tn, ZXIC_RBT_BLACK); + break; + } + else if (GET_TN_COLOR(p_cur_tn->p_parent) == ZXIC_RBT_RED) + { + ZXIC_RB_TN *p_unc_tn = zxic_comm_rb_get_brotn(p_cur_tn->p_parent); + + ZXIC_COMM_ASSERT(p_cur_tn->p_parent == *stack_tn[stack_top - 1]); + + if (GET_TN_COLOR(p_unc_tn) == ZXIC_RBT_RED) /*unc is red,so we change the black of parent and unc*/ + { + ZXIC_COMM_ASSERT(p_unc_tn); + SET_TN_COLOR(p_cur_tn->p_parent, ZXIC_RBT_BLACK); + SET_TN_COLOR(p_unc_tn, ZXIC_RBT_BLACK); + + ZXIC_COMM_ASSERT(p_cur_tn->p_parent->p_parent == *stack_tn[stack_top - 2]); + + SET_TN_COLOR(p_cur_tn->p_parent->p_parent, ZXIC_RBT_RED); + stack_top -= 2; + } + else /*we need shift ,p_cur_tn->parent->parent*/ + { + ZXIC_RB_TN *p_bro_tn = NULL; + + pp_tmp_tn = stack_tn[stack_top - 2]; + p_tmp_tn = *pp_tmp_tn; + + + if (p_cur_tn->p_parent == p_tmp_tn->p_left && p_cur_tn == p_cur_tn->p_parent->p_left) + { + *pp_tmp_tn = p_cur_tn->p_parent; + + p_bro_tn = zxic_comm_rb_get_brotn(p_cur_tn); + p_cur_tn->p_parent->p_parent = p_tmp_tn->p_parent; + + p_tmp_tn->p_left = p_bro_tn; + p_tmp_tn->p_parent = p_cur_tn->p_parent; + p_cur_tn->p_parent->p_right = p_tmp_tn; + + if (p_bro_tn) + { + p_bro_tn->p_parent = p_tmp_tn; + } + + zxic_comm_rb_swich_color(*pp_tmp_tn, p_tmp_tn); + } + else if (p_cur_tn->p_parent == p_tmp_tn->p_left && p_cur_tn == p_cur_tn->p_parent->p_right) + { + *pp_tmp_tn = p_cur_tn; + + p_cur_tn->p_parent->p_right = p_cur_tn->p_left; + + if (p_cur_tn->p_left) + { + p_cur_tn->p_left->p_parent = p_cur_tn->p_parent; + } + + p_cur_tn->p_parent->p_parent = p_cur_tn; + p_tmp_tn->p_left = p_cur_tn->p_right; + + if (p_cur_tn->p_right) + { + p_cur_tn->p_right->p_parent = p_tmp_tn; + } + + p_cur_tn->p_left = p_cur_tn->p_parent; + p_cur_tn->p_right = p_tmp_tn; + + p_cur_tn->p_parent = p_tmp_tn->p_parent; + p_tmp_tn->p_parent = p_cur_tn; + + zxic_comm_rb_swich_color(*pp_tmp_tn, p_tmp_tn); + } + else if (p_cur_tn->p_parent == p_tmp_tn->p_right && p_cur_tn == p_cur_tn->p_parent->p_right) + { + *pp_tmp_tn = p_cur_tn->p_parent; + p_bro_tn = zxic_comm_rb_get_brotn(p_cur_tn); + + p_cur_tn->p_parent->p_parent = p_tmp_tn->p_parent; + + p_tmp_tn->p_right = p_cur_tn->p_parent->p_left; + p_tmp_tn->p_parent = p_cur_tn->p_parent; + p_cur_tn->p_parent->p_left = p_tmp_tn; + + if (p_bro_tn) + { + p_bro_tn->p_parent = p_tmp_tn; + } + + zxic_comm_rb_swich_color(*pp_tmp_tn, p_tmp_tn); + } + else + { + *pp_tmp_tn = p_cur_tn; + p_cur_tn->p_parent->p_left = p_cur_tn->p_right; + + if (p_cur_tn->p_right) + { + p_cur_tn->p_right->p_parent = p_cur_tn->p_parent; + } + + p_cur_tn->p_parent->p_parent = p_cur_tn; + p_tmp_tn->p_right = p_cur_tn->p_left; + + if (p_cur_tn->p_left) + { + p_cur_tn->p_left->p_parent = p_tmp_tn; + } + + p_cur_tn->p_right = p_cur_tn->p_parent; + p_cur_tn->p_left = p_tmp_tn; + + p_cur_tn->p_parent = p_tmp_tn->p_parent; + p_tmp_tn->p_parent = p_cur_tn; + + zxic_comm_rb_swich_color(*pp_tmp_tn, p_tmp_tn); + + } + + /*change color*/ + + /* SET_TN_COLOR(p_cur_tn->p_parent,ZXIC_RBT_BLACK); + SET_TN_COLOR(p_tmp_tn,ZXIC_RBT_RED); */ + break; + } + } + else /*parent is black ,nothing to do ,end*/ + { + break; + } + } + + return ZXIC_OK; +} + + +ZXIC_RTN32 zxic_comm_rb_insert(ZXIC_RB_CFG *p_rb_cfg, + ZXIC_VOID *p_key, + ZXIC_VOID *out_val) +{ + ZXIC_UINT32 rtn = 0; + ZXIC_UINT32 stack_top = 1; + ZXIC_SINT32 cmprtn = 0; + ZXIC_UINT32 lsm_out = 0; + + ZXIC_RB_TN **stack_tn[ZXIC_RBT_MAX_DEPTH] = {0}; + //ZXIC_RB_TN **pp_tmp_tn = NULL; + ZXIC_RB_TN *p_cur_tn = NULL; + ZXIC_RB_TN *p_pre_tn = NULL; + ZXIC_RB_TN **pp_cur_tn = NULL; + ZXIC_VOID *p_cur_key = NULL; + ZXIC_RB_TN *p_ins_tn = p_key; + + ZXIC_COMM_CHECK_POINT(p_rb_cfg); + ZXIC_COMM_CHECK_POINT(p_key); + + p_cur_key = p_rb_cfg->is_dynamic ? ((ZXIC_RB_TN*)p_key)->p_key : p_key; + + pp_cur_tn = &p_rb_cfg->p_root; + + for (;;) + { + p_cur_tn = *pp_cur_tn; + + if (!p_cur_tn) /*find the insert position*/ + { + if (p_rb_cfg->is_dynamic == 0) + { + rtn = zxic_comm_liststack_alloc(p_rb_cfg->p_lsm, &lsm_out); + + if (rtn == ZXIC_LIST_STACK_ISEMPTY_ERR) + { + return ZXIC_RBT_RC_FULL; + } + + ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_liststack_alloc"); + + p_ins_tn = p_rb_cfg->p_tnbase + lsm_out; + + ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW( p_rb_cfg->key_size, lsm_out); + INIT_RBT_TN(p_ins_tn, p_rb_cfg->key_size * lsm_out + p_rb_cfg->p_keybase); + + ZXIC_COMM_MEMCPY_S(p_ins_tn->p_key, p_rb_cfg->key_size, p_key, p_rb_cfg->key_size); + + SET_TN_LSV(p_ins_tn, lsm_out); + + if (out_val) + { + *((ZXIC_UINT32*)out_val) = lsm_out; + } + } + else + { + INIT_D_NODE(&p_ins_tn->tn_ln, p_ins_tn); + } + + /*all insert tn color set to red*/ + SET_TN_COLOR(p_ins_tn, ZXIC_RBT_RED); + + /*insert list*/ + if (cmprtn < 0) + { + rtn = zxic_comm_double_link_insert_pre(&p_ins_tn->tn_ln, &p_pre_tn->tn_ln, &p_rb_cfg->tn_list); + ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_double_link_insert_pre"); + } + else if (cmprtn > 0) + { + rtn = zxic_comm_double_link_insert_aft(&p_ins_tn->tn_ln, &p_pre_tn->tn_ln, &p_rb_cfg->tn_list); + ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_double_link_insert_aft"); + } + else + { + /*first insert*/ + ZXIC_COMM_ASSERT(!p_pre_tn); + + rtn = zxic_comm_double_link_insert_1st(&p_ins_tn->tn_ln, &p_rb_cfg->tn_list); + ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_double_link_insert_1st"); + } + + /*get out loop */ + break; + } + + ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(stack_top, 1); + stack_tn[stack_top++] = pp_cur_tn; + p_pre_tn = p_cur_tn; + cmprtn = p_rb_cfg->p_cmpfun(p_cur_key, p_cur_tn->p_key, p_rb_cfg->key_size); + + if (cmprtn > 0) + { + pp_cur_tn = &p_cur_tn->p_right; + } + else if (cmprtn < 0) + { + pp_cur_tn = &p_cur_tn->p_left; + } + else + { + ZXIC_COMM_TRACE_ALL("info ,rb_key is same \n"); + + if (p_rb_cfg->is_dynamic) + { + if (out_val) + { + *((ZXIC_RB_TN**)out_val) = p_cur_tn; + } + } + else + { + if (out_val) + { + *((ZXIC_UINT32*)out_val) = GET_TN_LSV(p_cur_tn); + } + } + + return ZXIC_RBT_RC_UPDATE; + } + } + + /*handle parenet ptr*/ + //pp_tmp_tn = stack_tn[stack_top - 1]; + + /*p_ins_tn->p_parent = stack_top != 1 ? *pp_tmp_tn : NULL;*/ + p_ins_tn->p_parent = (stack_top != 1) ? *stack_tn[stack_top - 1] : NULL; + + stack_tn[stack_top] = pp_cur_tn; + + *pp_cur_tn = p_ins_tn; + + rtn = zxic_comm_rb_handle_ins(p_rb_cfg, stack_tn, stack_top); + ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_rb_handle_ins"); + + /* 新插入时也返回 */ + if (p_rb_cfg->is_dynamic) + { + if (out_val) + { + *((ZXIC_RB_TN**)out_val) = p_ins_tn; + } + } + + return ZXIC_OK; +} + + + +ZXIC_RTN32 zxic_comm_rb_handle_del(ZXIC_RB_CFG *p_rb_cfg, + ZXIC_RB_TN***stack_tn, + ZXIC_UINT32 stack_top) +{ + ZXIC_RB_TN **pp_cur_tn = NULL; + ZXIC_RB_TN *p_cur_tn = NULL; + ZXIC_RB_TN *p_tmp_tn = NULL; + ZXIC_RB_TN *p_unc_tn = NULL; + ZXIC_RB_TN *p_par_tn = NULL; + + ZXIC_COMM_CHECK_POINT(p_rb_cfg); + ZXIC_COMM_CHECK_POINT(stack_tn); + + while (stack_top > 1 ) + { + pp_cur_tn = stack_tn[stack_top]; + p_cur_tn = *pp_cur_tn; + + p_par_tn = *stack_tn[stack_top - 1]; + + if (p_cur_tn && p_cur_tn->p_parent) + { + p_unc_tn = zxic_comm_rb_get_brotn(p_cur_tn); + } + else if (p_cur_tn && !p_cur_tn->p_parent) + { + ZXIC_COMM_ASSERT(p_par_tn == p_cur_tn->p_parent); + + SET_TN_COLOR(p_cur_tn, ZXIC_RBT_BLACK); + + break; + } + else + { + ZXIC_COMM_ASSERT(!p_cur_tn); + + if (p_par_tn) + { + p_unc_tn = p_par_tn->p_left ? p_par_tn->p_left : p_par_tn->p_right; + } + else + { + break; + } + } + + if (p_unc_tn) + { + ZXIC_COMM_ASSERT(p_unc_tn->p_parent == p_par_tn); + } + + if (GET_TN_COLOR(p_unc_tn) == ZXIC_RBT_RED) /*shift */ + { + ZXIC_COMM_CHECK_INDEX_BOTH(stack_top, 1, (ZXIC_RBT_MAX_DEPTH - 2)); + if (p_unc_tn == p_par_tn->p_left) /*shift right */ + { + *stack_tn[stack_top - 1] = p_unc_tn; + p_unc_tn->p_parent = p_par_tn->p_parent; + p_par_tn->p_left = p_unc_tn->p_right; + + if (p_unc_tn->p_right) + { + p_unc_tn->p_right->p_parent = p_par_tn; + } + + p_par_tn->p_parent = p_unc_tn; + p_unc_tn->p_right = p_par_tn; + + stack_tn[stack_top++] = &p_unc_tn->p_right; + ZXIC_COMM_CHECK_INDEX_UPPER(stack_top, (ZXIC_RBT_MAX_DEPTH - 1)); + stack_tn[stack_top] = &p_par_tn->p_right; + } + else /*shift left*/ + { + ZXIC_COMM_ASSERT(p_unc_tn == p_par_tn->p_right); + *stack_tn[stack_top - 1] = p_unc_tn; + p_unc_tn->p_parent = p_par_tn->p_parent; + p_par_tn->p_right = p_unc_tn->p_left; + + if (p_unc_tn->p_left) + { + p_unc_tn->p_left->p_parent = p_par_tn; + } + + p_par_tn->p_parent = p_unc_tn; + p_unc_tn->p_left = p_par_tn; + + stack_tn[stack_top++] = &p_unc_tn->p_left; + ZXIC_COMM_CHECK_INDEX_UPPER(stack_top, (ZXIC_RBT_MAX_DEPTH - 1)); + stack_tn[stack_top] = &p_par_tn->p_left; + } + + zxic_comm_rb_swich_color(p_unc_tn, p_par_tn); + } + else if (!p_unc_tn) + { + /*this branch will never run ,consider too much*/ + ZXIC_COMM_ASSERT(0); + ZXIC_COMM_ASSERT(GET_TN_COLOR(p_par_tn) == ZXIC_RBT_RED); + + SET_TN_COLOR(p_par_tn, ZXIC_RBT_BLACK); + + break; + } + else + { + if (GET_TN_COLOR(p_unc_tn->p_left) == ZXIC_RBT_BLACK && GET_TN_COLOR(p_unc_tn->p_right) == ZXIC_RBT_BLACK) + { + if (GET_TN_COLOR(p_unc_tn->p_parent) == ZXIC_RBT_BLACK) + { + SET_TN_COLOR(p_unc_tn, ZXIC_RBT_RED); + stack_top--; + } + else + { + ZXIC_COMM_ASSERT(GET_TN_COLOR(p_unc_tn->p_parent) == ZXIC_RBT_RED); + + zxic_comm_rb_swich_color(p_unc_tn->p_parent, p_unc_tn); + + break; + } + } + else if (p_unc_tn == p_par_tn->p_right) + { + if (GET_TN_COLOR(p_unc_tn->p_right) == ZXIC_RBT_RED) /*shift left*/ + { + *stack_tn[stack_top - 1] = p_unc_tn; + p_unc_tn->p_parent = p_par_tn->p_parent; + p_par_tn->p_right = p_unc_tn->p_left; + + if (p_unc_tn->p_left) + { + p_unc_tn->p_left->p_parent = p_par_tn; + } + + p_par_tn->p_parent = p_unc_tn; + p_unc_tn->p_left = p_par_tn; + + zxic_comm_rb_swich_color(p_unc_tn, p_par_tn); + + SET_TN_COLOR(p_unc_tn->p_right, ZXIC_RBT_BLACK); + + break; + } + else + { + ZXIC_COMM_ASSERT(GET_TN_COLOR(p_unc_tn->p_left) == ZXIC_RBT_RED); + + p_tmp_tn = p_unc_tn->p_left; + + p_par_tn->p_right = p_tmp_tn; + p_tmp_tn->p_parent = p_par_tn; + p_unc_tn->p_left = p_tmp_tn->p_right; + + if (p_tmp_tn->p_right) + { + p_tmp_tn->p_right->p_parent = p_unc_tn; + } + + p_tmp_tn->p_right = p_unc_tn; + p_unc_tn->p_parent = p_tmp_tn; + + zxic_comm_rb_swich_color(p_tmp_tn, p_unc_tn); + } + } + else + { + ZXIC_COMM_ASSERT(p_unc_tn == p_par_tn->p_left); + + if (GET_TN_COLOR(p_unc_tn->p_left) == ZXIC_RBT_RED) /*shift right*/ + { + *stack_tn[stack_top - 1] = p_unc_tn; + p_unc_tn->p_parent = p_par_tn->p_parent; + p_par_tn->p_left = p_unc_tn->p_right; + + if (p_unc_tn->p_right) + { + p_unc_tn->p_right->p_parent = p_par_tn; + } + + p_par_tn->p_parent = p_unc_tn; + p_unc_tn->p_right = p_par_tn; + + zxic_comm_rb_swich_color(p_unc_tn, p_par_tn); + + SET_TN_COLOR(p_unc_tn->p_left, ZXIC_RBT_BLACK); + break; + } + else + { + ZXIC_COMM_ASSERT(GET_TN_COLOR(p_unc_tn->p_right) == ZXIC_RBT_RED); + + p_tmp_tn = p_unc_tn->p_right; + + p_par_tn->p_left = p_tmp_tn; + p_tmp_tn->p_parent = p_par_tn; + p_unc_tn->p_right = p_tmp_tn->p_left; + + if (p_tmp_tn->p_left) + { + p_tmp_tn->p_left->p_parent = p_unc_tn; + } + + p_tmp_tn->p_left = p_unc_tn; + p_unc_tn->p_parent = p_tmp_tn; + + zxic_comm_rb_swich_color(p_tmp_tn, p_unc_tn); + } + } + } + } + + return ZXIC_OK; +} + +ZXIC_RTN32 zxic_comm_rb_delete(ZXIC_RB_CFG *p_rb_cfg, + ZXIC_VOID *p_key, + ZXIC_VOID *out_val) +{ + ZXIC_UINT32 rtn = 0; + ZXIC_UINT32 stack_top = 1; + ZXIC_SINT32 cmprtn = 0; + ZXIC_UINT32 rsv_stack = 0; + ZXIC_UINT32 del_is_red = 0; + + ZXIC_RB_TN **stack_tn[ZXIC_RBT_MAX_DEPTH] = {0}; + ZXIC_RB_TN *p_cur_tn = NULL; + ZXIC_RB_TN **pp_cur_tn = NULL; + ZXIC_VOID *p_cur_key = NULL; + ZXIC_RB_TN *p_rsv_tn = NULL; + ZXIC_RB_TN *p_del_tn = NULL; + + ZXIC_COMM_CHECK_POINT(p_rb_cfg); + ZXIC_COMM_CHECK_POINT(out_val); + + p_cur_key = p_key; + + pp_cur_tn = &p_rb_cfg->p_root; + + for (;;) + { + p_cur_tn = *pp_cur_tn; + + if (!p_cur_tn) + { + /*ZXIC_COMM_TRACE_ERROR("\n error ,the key is not exist !");*/ + return ZXIC_RBT_RC_SRHFAIL; + } + ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(stack_top, 1); + stack_tn[stack_top++] = pp_cur_tn; + + cmprtn = p_rb_cfg->p_cmpfun(p_cur_key, p_cur_tn->p_key, p_rb_cfg->key_size); + + if (cmprtn > 0) + { + pp_cur_tn = &p_cur_tn->p_right; + } + else if (cmprtn < 0) + { + pp_cur_tn = &p_cur_tn->p_left; + } + else + { + ZXIC_COMM_TRACE_ALL(" find the key!\n"); + + break; + } + } + ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW(stack_top, 1); + rsv_stack = stack_top - 1; /*save stack pos*/ + p_rsv_tn = p_cur_tn; + + pp_cur_tn = &p_cur_tn->p_right; + p_cur_tn = *pp_cur_tn; + + if (p_cur_tn) + { + + ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(stack_top, 1); + stack_tn[stack_top++] = pp_cur_tn; + + pp_cur_tn = &p_cur_tn->p_left; + p_cur_tn = *pp_cur_tn; + + while (p_cur_tn) + { + ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(stack_top, 1); + stack_tn[stack_top++] = pp_cur_tn; + pp_cur_tn = &p_cur_tn->p_left; + p_cur_tn = *pp_cur_tn; + } + + /*get the del tn*/ + ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW(stack_top, 1); + p_del_tn = *stack_tn[stack_top - 1]; + + /*set tn is left child to cur place*/ + *stack_tn[stack_top - 1] = p_del_tn->p_right; + + if (p_del_tn->p_right) + { + p_del_tn->p_right->p_parent = p_del_tn->p_parent; + } + + /*rsv the del tn info for delete*/ + if (GET_TN_COLOR(p_del_tn) == ZXIC_RBT_RED) + { + del_is_red = 1; + } + + /*replace the delete val*/ + ZXIC_COMM_CHECK_INDEX_UPPER(rsv_stack, (ZXIC_RBT_MAX_DEPTH - 2)); + *stack_tn[rsv_stack] = p_del_tn; + + stack_tn[rsv_stack + 1] = &p_del_tn->p_right; + + SET_TN_COLOR(p_del_tn, GET_TN_COLOR(p_rsv_tn)); + p_del_tn->p_parent = p_rsv_tn->p_parent; + + p_del_tn->p_left = p_rsv_tn->p_left; + + if (p_rsv_tn->p_left) + { + p_rsv_tn->p_left->p_parent = p_del_tn; + } + + p_del_tn->p_right = p_rsv_tn->p_right; + + if (p_rsv_tn->p_right) + { + p_rsv_tn->p_right->p_parent = p_del_tn; + } + } + else + { + if (GET_TN_COLOR(p_rsv_tn) == ZXIC_RBT_RED) + { + del_is_red = 1; + } + + ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW(stack_top, 1); + *stack_tn[stack_top - 1] = p_rsv_tn->p_left; + + if (p_rsv_tn->p_left) + { + p_rsv_tn->p_left->p_parent = p_rsv_tn->p_parent; + } + } + + ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW(stack_top, 1); + stack_top--; + ZXIC_COMM_CHECK_INDEX_UPPER(stack_top, (ZXIC_RBT_MAX_DEPTH - 1)); + if (GET_TN_COLOR(*stack_tn[stack_top]) == ZXIC_RBT_RED) + { + SET_TN_COLOR(*stack_tn[stack_top], ZXIC_RBT_BLACK); + } + else if (!del_is_red) /*del node is red ,do nothing*/ + { + rtn = zxic_comm_rb_handle_del(p_rb_cfg, stack_tn, stack_top); + ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_rb_handle_del"); + } + + /*clear the node from the list */ + rtn = zxic_comm_double_link_del(&p_rsv_tn->tn_ln, &p_rb_cfg->tn_list); + ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_double_link_del"); + + if (p_rb_cfg->is_dynamic) + { + *(ZXIC_RB_TN**)out_val = p_rsv_tn; + } + else + { + rtn = zxic_comm_liststack_free(p_rb_cfg->p_lsm, GET_TN_LSV(p_rsv_tn)); + ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_liststack_free"); + + *(ZXIC_UINT32*)out_val = GET_TN_LSV(p_rsv_tn); + + ZXIC_COMM_MEMSET(p_rsv_tn->p_key, 0, p_rb_cfg->key_size); + ZXIC_COMM_MEMSET(p_rsv_tn, 0, ZXIC_SIZEOF(ZXIC_RB_TN)); + } + + return ZXIC_OK; +} + +/* 注意此处传入的p_key和insert时候传入的p_key不是同一个东西 */ +ZXIC_RTN32 zxic_comm_rb_search(ZXIC_RB_CFG *p_rb_cfg, + ZXIC_VOID *p_key, + ZXIC_VOID *out_val) +{ + ZXIC_SINT32 cmprtn = 0; + ZXIC_RB_TN *p_cur_tn = NULL; + + ZXIC_COMM_CHECK_POINT(p_rb_cfg); + ZXIC_COMM_CHECK_POINT(p_key); + ZXIC_COMM_CHECK_POINT(out_val); + + p_cur_tn = p_rb_cfg->p_root; + + while (p_cur_tn) + { + cmprtn = p_rb_cfg->p_cmpfun(p_key, p_cur_tn->p_key, p_rb_cfg->key_size); + + if (cmprtn > 0) + { + p_cur_tn = p_cur_tn->p_right; + } + else if (cmprtn < 0) + { + p_cur_tn = p_cur_tn->p_left; + } + else + { + break; + } + } + + if (!p_cur_tn) + { + ZXIC_COMM_TRACE_ALL("rb srh fail \n"); + return ZXIC_RBT_RC_SRHFAIL; + } + + if (p_rb_cfg->is_dynamic) + { + *(ZXIC_RB_TN**)out_val = p_cur_tn; + } + else + { + *(ZXIC_UINT32*)out_val = GET_TN_LSV(p_cur_tn); + } + + return ZXIC_OK; +} + +ZXIC_SINT32 zxic_comm_rb_is_none(ZXIC_RB_CFG* p_rb_cfg) +{ + ZXIC_COMM_CHECK_POINT(p_rb_cfg); + + if (0 == p_rb_cfg->tn_list.used) + { + return 1; + } + else + { + return 0; + } +} + +ZXIC_RB_TN *zxic_comm_rb_get_1st_tn(ZXIC_RB_CFG *p_rb_cfg) +{ + ZXIC_COMM_CHECK_POINT_RETURN_NULL(p_rb_cfg); + + return (p_rb_cfg->p_root) ? p_rb_cfg->tn_list.p_next->data : NULL; +} + +ZXIC_RTN32 zxic_comm_rb_get_1st_key(ZXIC_RB_CFG* p_rb_cfg, ZXIC_VOID *p_key_out) +{ + D_NODE *rb_list_node = NULL; + ZXIC_RB_TN *p_rb_node = NULL; + + ZXIC_COMM_CHECK_POINT(p_rb_cfg); + ZXIC_COMM_CHECK_POINT(p_key_out); + + if (zxic_comm_rb_is_none(p_rb_cfg)) + { + return ZXIC_RBT_ISEMPTY_ERR; + } + + rb_list_node = p_rb_cfg->tn_list.p_next; + ZXIC_COMM_CHECK_POINT(rb_list_node); + + p_rb_node = (ZXIC_RB_TN *)rb_list_node->data; + ZXIC_COMM_CHECK_POINT(p_rb_node); + + ZXIC_COMM_MEMCPY_S(p_key_out, p_rb_cfg->key_size, p_rb_node->p_key, p_rb_cfg->key_size); + + return ZXIC_OK; +} + +ZXIC_RB_TN *zxic_comm_rb_get_last_tn(ZXIC_RB_CFG *p_rb_cfg) +{ + ZXIC_COMM_CHECK_POINT_RETURN_NULL(p_rb_cfg); + + return (p_rb_cfg->p_root) ? p_rb_cfg->tn_list.p_prev->data : NULL; +} + +ZXIC_RTN32 zxic_comm_rb_get_last_key(ZXIC_RB_CFG* p_rb_cfg, ZXIC_VOID *p_key_out) +{ + D_NODE *p_rb_list_node = NULL; + ZXIC_RB_TN *p_rb_node = NULL; + + ZXIC_COMM_CHECK_POINT(p_rb_cfg); + + if (zxic_comm_rb_is_none(p_rb_cfg)) + { + return ZXIC_RBT_ISEMPTY_ERR; + } + + p_rb_list_node = p_rb_cfg->tn_list.p_prev; + + p_rb_node = (ZXIC_RB_TN *)p_rb_list_node->data; + ZXIC_COMM_MEMCPY_S(p_key_out, p_rb_cfg->key_size, p_rb_node->p_key, p_rb_cfg->key_size); + + return ZXIC_OK; +} + +/* 不支持动态内存分配模式, 此函数仅用于CPU软复位 */ +ZXIC_RTN32 zxic_comm_rb_insert_spec_index(ZXIC_RB_CFG *p_rb_cfg, ZXIC_VOID *p_key, ZXIC_UINT32 in_idx) +{ + ZXIC_UINT32 rtn = 0; + ZXIC_UINT32 stack_top = 1; + ZXIC_SINT32 cmprtn = 0; + + ZXIC_RB_TN **stack_tn[ZXIC_RBT_MAX_DEPTH] = {0}; + //ZXIC_RB_TN **pp_tmp_tn = NULL; + ZXIC_RB_TN *p_cur_tn = NULL; + ZXIC_RB_TN *p_pre_tn = NULL; + ZXIC_RB_TN **pp_cur_tn = NULL; + ZXIC_VOID *p_cur_key = NULL; + ZXIC_RB_TN *p_ins_tn = p_key; + + ZXIC_COMM_CHECK_POINT(p_rb_cfg); + ZXIC_COMM_CHECK_POINT(p_key); + + if (p_rb_cfg->is_dynamic) + { + ZXIC_COMM_PRINT("zxic_comm_rb_insert_spec_index: dynamic mode is not support ! Error"); + return ZXIC_RBT_PARA_INVALID; + } + + p_cur_key = p_key; + + pp_cur_tn = &p_rb_cfg->p_root; + + for (;;) + { + p_cur_tn = *pp_cur_tn; + + if (!p_cur_tn) /*find the insert position*/ + { + rtn = zxic_comm_liststack_alloc_spec_index(p_rb_cfg->p_lsm, in_idx); + ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_liststack_alloc_spec_index"); + + p_ins_tn = p_rb_cfg->p_tnbase + in_idx; + + ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW(p_rb_cfg->key_size, in_idx); + INIT_RBT_TN(p_ins_tn, p_rb_cfg->key_size * in_idx + p_rb_cfg->p_keybase); + + ZXIC_COMM_MEMCPY_S(p_ins_tn->p_key, p_rb_cfg->key_size, p_key, p_rb_cfg->key_size); + + SET_TN_LSV(p_ins_tn, in_idx); + + /*all insert tn color set to red*/ + SET_TN_COLOR(p_ins_tn, ZXIC_RBT_RED); + + /*insert list*/ + if (cmprtn < 0) + { + rtn = zxic_comm_double_link_insert_pre(&p_ins_tn->tn_ln, &p_pre_tn->tn_ln, &p_rb_cfg->tn_list); + ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_double_link_insert_pre"); + } + else if (cmprtn > 0) + { + rtn = zxic_comm_double_link_insert_aft(&p_ins_tn->tn_ln, &p_pre_tn->tn_ln, &p_rb_cfg->tn_list); + ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_double_link_insert_aft"); + } + else + { + /*first insert*/ + ZXIC_COMM_ASSERT(!p_pre_tn); + + rtn = zxic_comm_double_link_insert_1st(&p_ins_tn->tn_ln, &p_rb_cfg->tn_list); + ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_double_link_insert_1st"); + } + + /*get out loop */ + break; + } + + + ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(stack_top, 1); + stack_tn[stack_top++] = pp_cur_tn; + p_pre_tn = p_cur_tn; + cmprtn = p_rb_cfg->p_cmpfun(p_cur_key, p_cur_tn->p_key, p_rb_cfg->key_size); + + if (cmprtn > 0) + { + pp_cur_tn = &p_cur_tn->p_right; + } + else if (cmprtn < 0) + { + pp_cur_tn = &p_cur_tn->p_left; + } + else + { + ZXIC_COMM_TRACE_ALL("info ,rb_key is same \n"); + + return ZXIC_RBT_RC_UPDATE; + } + } + + /*handle parenet ptr*/ + p_ins_tn->p_parent = (stack_top != 1) ? *stack_tn[stack_top - 1] : NULL; + + stack_tn[stack_top] = pp_cur_tn; + + *pp_cur_tn = p_ins_tn; + + rtn = zxic_comm_rb_handle_ins(p_rb_cfg, stack_tn, stack_top); + ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_rb_handle_ins"); + + return ZXIC_OK; +} + + diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/comm/source/zxic_common.c b/src/net/drivers/net/ethernet/dinghai/en_np/comm/source/zxic_common.c new file mode 100644 index 0000000..89306a2 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/comm/source/zxic_common.c @@ -0,0 +1,1009 @@ +/************************************************************** +* 版权所有 (C)2013-2020, 深圳市中兴通讯股份有限公司 +* 文件名称 : zxic_common.c +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : xuchenxi_10235594 +* 完成日期 : 2020/07/20 +* DEPARTMENT: 有线开发四部-系统软件团队 +* MANUAL_PERCENT: 0% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ +#include "zxic_common.h" + +#if ZXIC_REAL("全局变量") +ZXIC_UINT32 g_zxic_malloc_num = 0; +ZXIC_UINT32 g_zxic_malloc_size = 0; /* 单位字节 */ +ZXIC_UINT32 g_zxic_byte_swap_en = 1; +ZXIC_UINT32 g_zxic_comm_channel_max = 4; +#endif + +#if ZXIC_REAL("内存") +/***********************************************************/ +/** 释放内存 +* @param p_data +* +* @return +* @remark 无 +* @see +* @author ChenWei10088471 @date 2014/02/07 +************************************************************/ +ZXIC_VOID ic_comm_free_record(void) +{ + if (g_zxic_malloc_num > 0) + { + g_zxic_malloc_num--; + } + else + { + ZXIC_COMM_TRACE_ERROR("Note:g_zxicp_malloc_num is zero now\n"); + } +} + +/***********************************************************/ +/** 分配内存 +* @param size +* +* @return +* @remark 无 +* @see +* @author ChenWei10088471 @date 2014/02/07 +************************************************************/ +ZXIC_VOID* ic_comm_malloc_memory(ZXIC_UINT32 size) +{ + /* 独立安全测评 限定申请内存的大小 */ + if(size > ZXIC_MALLOC_MAX_B_SIZE) + { + ZXIC_COMM_TRACE_ERROR("malloc size err, size more than 200M \n"); + return ZXIC_NULL; + } + if (g_zxic_malloc_num < ZXIC_UINT32_MAX) + { + g_zxic_malloc_num++; + } + else + { + ZXIC_COMM_TRACE_ERROR("Note:g_zxicp_malloc_num is maxvalue now, reset 0\n"); + g_zxic_malloc_num = 0; + } + + if (g_zxic_malloc_size < (ZXIC_UINT32_MAX - size)) + { + g_zxic_malloc_size += size; + } + else + { + ZXIC_COMM_TRACE_INFO("Note:g_zxic_malloc_size[0x%x] and size[0x%x] sum is over maxvalue now, reset 0\n", g_zxic_malloc_size, size); + g_zxic_malloc_size = 0; + } + return kmalloc(size,GFP_KERNEL); +} +#endif /* 内存 */ + +#if ZXIC_REAL("延时") +/***********************************************************/ +/** 毫秒级延时 +* @param milliseconds +* +* @return +* @remark 无 +* @see +* @author ChenWei10088471 @date 2014/02/07 +************************************************************/ +// ZXIC_VOID zxic_comm_sleep(ZXIC_UINT32 milliseconds) +// { +// /* 打桩测试不需要延时 modify by zhangjintao 2022.01.21 */ +// #ifndef ZXIC_FOR_LLT +// #ifdef ZXIC_OS_WIN +// Sleep(milliseconds); +// #else +// ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW_NONE((ZXIC_UINT32)milliseconds, 1000); + +// msleep(milliseconds); +// #endif +// #endif +// } + +/***********************************************************/ +/** 微秒级延时,互坼锁中使用 +* @param milliseconds +* +* @return +* @remark +* @see +* @author fyl @date 2020/04/09 +************************************************************/ +ZXIC_VOID zxic_comm_udelay(ZXIC_UINT32 microseconds) +{ +#ifndef ZXIC_FOR_LLT + + ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW_NONE(microseconds, 1); + + udelay(microseconds); +#endif +} + +/***********************************************************/ +/** 毫秒级延时,互坼锁中使用 +* @param milliseconds +* +* @return +* @remark 无 +* @see +* @author ChenWei10088471 @date 2014/02/07 +************************************************************/ +ZXIC_VOID zxic_comm_delay(ZXIC_UINT32 milliseconds) +{ +#ifndef ZXIC_FOR_LLT + // ZXIC_UINT32 i = 0; + + ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW_NONE(milliseconds, 1); + // while (--milliseconds != 0) + // { + // for (i = 0; i < 600; i++); + // } + mdelay(milliseconds); +#endif +} + +/***********************************************************/ +/** LINUX :毫秒级延时 + WINDOWS:毫秒级延时 +* @param millisecond +* +* @return +* @remark 无 +* @see +* @author ChenWei10088471 @date 2014/02/07 +************************************************************/ +ZXIC_VOID zxic_comm_msleep(ZXIC_UINT32 millisecond) +{ +#ifndef ZXIC_FOR_LLT +#ifdef ZXIC_OS_WIN + Sleep(millisecond); +#else + msleep(millisecond); +#endif +#endif +} + +/***********************************************************/ +/**获取时间函数，毫秒 +* @param total +* @param masklen +* +* @return +* @remark 无 +* @see +* @author ChenWei10088471 @date 2014/02/07 +************************************************************/ +ZXIC_DOUBLE zxic_comm_get_ticks_ms() +{ +#ifdef ZXIC_OS_WIN + return (ZXIC_FLOAT)GetTickCount(); +#else + struct timespec64 tv = {0}; + get_timespec64(&tv, ZXIC_NULL); + return (ZXIC_DOUBLE)1000 * tv.tv_sec + (ZXIC_DOUBLE)tv.tv_nsec / 1000; +#endif +} +#endif + +#if ZXIC_REAL("字节序") +/***********************************************************/ +/** 判断CPU的大小端字节序 +* @param ZXIC_VOID +* +* @return 0-小端；1-大端 +* @remark 无 +* @see +* @author ChenWei10088471 @date 2014/02/07 +************************************************************/ +ZXIC_RTN32 zxic_comm_is_big_endian(ZXIC_VOID) +{ + ZXIC_ENDIAN_U c_data; + + c_data.a = 1; + + if (c_data.b == 1) + { + return 0; + } + else + { + return 1; + } +} + +/***********************************************************/ +/** 字节序转换，以4字节为单位进行转序 +* @param p_uc_data +* @param dw_byte_len +* +* @return +* @remark 无 +* @see +* @author ChenWei10088471 @date 2014/02/07 +************************************************************/ +ZXIC_VOID zxic_comm_swap(ZXIC_UINT8 *p_uc_data, ZXIC_UINT32 dw_byte_len) +{ + ZXIC_UINT32 dw_byte_num = 0; + ZXIC_UINT8 uc_byte_mode = 0; + ZXIC_UINT32 uc_is_big_flag = 0; + ZXIC_UINT32 i = 0; + ZXIC_UINT16 *p_w_tmp = ZXIC_NULL; + ZXIC_UINT32 *p_dw_tmp = ZXIC_NULL; + + if (g_zxic_byte_swap_en) + { + + p_dw_tmp = (ZXIC_UINT32 *)(p_uc_data); + + uc_is_big_flag = zxic_comm_is_big_endian(); + + if (uc_is_big_flag) + { + return; + } + else + { + dw_byte_num = dw_byte_len >> 2; + uc_byte_mode = dw_byte_len % 4 & 0xff; + + for (i = 0; i < dw_byte_num; i++) + { + (*p_dw_tmp) = ZXIC_COMM_CONVERT32(*p_dw_tmp); + p_dw_tmp++; + } + + if (uc_byte_mode > 1) + { + p_w_tmp = (ZXIC_UINT16 *)(p_dw_tmp); + (*p_w_tmp) = ZXIC_COMM_CONVERT16(*p_w_tmp); + } + } + } + + return; +} + +/***********************************************************/ +/** WORD32拼装成WORD64 +* @param hi 高32bit +* @param lo 低32bit +* +* @return WORD64 +* @remark 无 +* @see +* @author pj @date 2019/10/22 +************************************************************/ +ZXIC_UINT64 ZXIC_COMM_COUNTER64_BUILD(ZXIC_UINT32 hi, ZXIC_UINT32 lo) +{ + ZXIC_UINT64 value = hi; + + value = value << 32; + value = value | lo; + + return value; +} +#endif + +#if ZXIC_REAL("bit操作") +/***********************************************************/ +/** 将数据写入缓存区的指定bit位置，一次只能写入32bit的数据 + p_base的低字节存放数据的低比特，高字节存放数据的高比特。 +* @param p_base 数据缓存区指针 +* @param base_size_bit 缓存总的bit位宽 +* @param data 数据, 比特顺序左低右高，小端比特序 +* @param start_bit 起始bit位置(必须小于结束bit位置) +* @param end_bit 结束bit位置 +* +* @return +* @remark exp: + ZXIC_UINT8 data0[4] = {0x22, 0x44, 0x66, 0x88}; + zxic_comm_write_bits(data0, 32, 0xAABBCC, 0,23); + ZXIC_COMM_PRINT("0x%02X %02X %02X %02X \n", data0[0], data0[1], data0[2], data0[3]); + 输出:0xAA BB CC 88 + +* @see +* @author ChenWei10088471 @date 2014/02/07 +************************************************************/ +ZXIC_RTN32 zxic_comm_write_bits(ZXIC_UINT8 * p_base, + ZXIC_UINT32 base_size_bit, + ZXIC_UINT32 data, + ZXIC_UINT32 start_bit, + ZXIC_UINT32 end_bit) +{ + ZXIC_UINT32 len = 0; + ZXIC_UINT32 start_byte_index = 0; + ZXIC_UINT32 end_byte_index = 0; + ZXIC_UINT8 mask_value = 0; + ZXIC_UINT32 byte_num = 0; + ZXIC_UINT32 buffer_size = 0; + + if (0 != (base_size_bit % 8)) + { + ZXIC_COMM_TRACE_ERROR("\n buffer must be:%d", __LINE__); + //assert(0); + return ZXIC_BIT_STREAM_INDEX_ERR; + } + + if (start_bit > end_bit) + { + ZXIC_COMM_TRACE_ERROR("\nend_bit cannot be less than start_bit:%d", __LINE__); + //assert(0); + return ZXIC_BIT_STREAM_INDEX_ERR; + } + + if (base_size_bit < end_bit) + { + ZXIC_COMM_TRACE_ERROR("\nend_bit exceeds the base_size!line:%d,base_size_bit:%d end_bit:%d", + __LINE__, base_size_bit, end_bit); + //assert(0); + return ZXIC_BIT_STREAM_INDEX_ERR; + } + + ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW(end_bit, start_bit); + ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(end_bit - start_bit, 1); + + len = end_bit - start_bit + 1; + buffer_size = base_size_bit / 8; + + /*寄存器位宽需要时2的次方，如不是，需要累加到最近的2的次方*/ + /*用于解决KW检查中zxic_comm_write_bits_ex出现的内存泄漏错误*/ + ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW(buffer_size, 1); + ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(buffer_size, 1); + + while (0 != (buffer_size & (buffer_size - 1))) + { + buffer_size += 1; + } + + if (buffer_size != base_size_bit / 8) + { + ZXIC_COMM_TRACE_ALL("\n buffer size[0x%x] is not 2^n: add up to [0x%x]", base_size_bit / 8, buffer_size); + } + + + + /*一次只能写32bit*/ + ZXIC_COMM_CHECK_INDEX(len, 1, 32); + + if (data > (ZXIC_UINT32)(0xffffffff >> (32 - len))) + { + ZXIC_COMM_PRINT("\nValue is too big to write in the bit field!:%d,data:%x,len:%x", + __LINE__, data, (ZXIC_UINT32)(0xffffffff >> (32 - len))); + return ZXIC_BIT_STREAM_DATA_TOO_BIG; + } + + end_byte_index = (end_bit >> 3); + start_byte_index = (start_bit >> 3); + + if (start_byte_index == end_byte_index) + { + mask_value = ((0xFE << (7 - (start_bit & 7))) & 0xff); + mask_value |= (((1 << (7 - (end_bit & 7))) - 1)& 0xff); + p_base[end_byte_index] &= mask_value; + p_base[end_byte_index] |= (((data << (7 - (end_bit & 7)))) & 0xff); + return ZXIC_OK; + } + + if (7 != (end_bit & 7)) + { + mask_value = ((0x7f >> (end_bit & 7)) & 0xff); + p_base[end_byte_index] &= mask_value; + p_base[end_byte_index] |= ((data << (7 - (end_bit & 7))) & 0xff); + end_byte_index--; + data >>= 1 + (end_bit & 7); + } + + for (byte_num = end_byte_index; byte_num > start_byte_index; byte_num--) + { + /* critical */ + p_base[byte_num & (buffer_size - 1)] = data & 0xff; + data >>= 8; + } + + mask_value = ((0xFE << (7 - (start_bit & 7))) & 0xff); + p_base[byte_num] &= mask_value; + p_base[byte_num] |= data; + + return ZXIC_OK; +} + +/***********************************************************/ +/** 从缓存区中读取指定bit位置的数据，一次最多只能读32bit +* @param p_base 数据缓存区指针 +* @param base_size_bit 缓存区总的bit位宽 +* @param p_data 返回数据的指针 +* @param start_bit 起始bit位置(必须小于结束bit位置) +* @param end_bit 结束bit位置 +* +* @return +* @remark exp: + ZXIC_UINT8 data0[4] = {0x22, 0x44, 0x66, 0x88}; + ZXIC_UINT32 test_a = 0; + zxic_comm_read_bits(data0, 32, &test_a, 0, 23); + 输出: test_a = 0x224466 +* @see +* @author ChenWei10088471 @date 2014/02/07 +************************************************************/ +ZXIC_RTN32 zxic_comm_read_bits(ZXIC_UINT8* p_base, + ZXIC_UINT32 base_size_bit, + ZXIC_UINT32* p_data, + ZXIC_UINT32 start_bit, + ZXIC_UINT32 end_bit) +{ + ZXIC_UINT32 len = 0; + ZXIC_UINT32 start_byte_index = 0; + ZXIC_UINT32 end_byte_index = 0; + ZXIC_UINT32 byte_num = 0; + ZXIC_UINT32 buffer_size = 0; + + if (0 != (base_size_bit % 8)) + { + ZXIC_COMM_TRACE_ERROR("\n buffer must be:%d", __LINE__); + return ZXIC_BIT_STREAM_INDEX_ERR; + } + + if (start_bit > end_bit) + { + ZXIC_COMM_TRACE_ERROR("\nend_bit cannot be less than start_bit:%d", __LINE__); + return ZXIC_BIT_STREAM_INDEX_ERR; + } + + if (base_size_bit < end_bit) + { + ZXIC_COMM_TRACE_ERROR("\nend_bit exceeds the base_size:%d,end_bit:%d", __LINE__, end_bit); + return ZXIC_BIT_STREAM_INDEX_ERR; + } + + len = end_bit - start_bit + 1; + buffer_size = base_size_bit / 8; + + /*寄存器位宽需要时2的次方，如不是，需要累加到最近的2的次方*/ + /*用于解决KW检查中zxic_comm_read_bits_ex出现的内存泄漏错误*/ + ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW(buffer_size, 1); + + while (0 != (buffer_size & (buffer_size - 1))) + { + buffer_size += 1; + } + + if (buffer_size != base_size_bit / 8) + { + ZXIC_COMM_TRACE_ALL("\n buffer size[0x%x] is not 2^n: add up to [0x%x]", base_size_bit / 8, buffer_size); + } + + /*先将返回的数据清零*/ + *p_data = 0; + + /*一次最多只能读32bit*/ + ZXIC_COMM_CHECK_INDEX(len, 1, 32); + + end_byte_index = (end_bit >> 3); + start_byte_index = (start_bit >> 3); + + if (start_byte_index == end_byte_index) + { + *p_data = (ZXIC_UINT32)(((p_base[start_byte_index] >> (7U - (end_bit & 7))) & (0xff >> (8U - len))) & 0xff); + return ZXIC_OK; + } + + if (start_bit & 7) + { + *p_data = (p_base[start_byte_index] & (0xff >> (start_bit & 7))) & ZXIC_UINT8_MASK; + start_byte_index++; + } + + for (byte_num = start_byte_index; byte_num < end_byte_index; byte_num++) + { + *p_data <<= 8; + + ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(*p_data, p_base[byte_num]); + *p_data += p_base[byte_num]; + } + + *p_data <<= 1 + (end_bit & 7); + /* critical */ + ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(*p_data, (((p_base[byte_num & (buffer_size - 1)] & (0xff << (7 - (end_bit & 7)))) >> (7 - (end_bit & 7))) & 0xff)); + *p_data += ((p_base[byte_num & (buffer_size - 1)] & (0xff << (7 - (end_bit & 7)))) >> (7 - (end_bit & 7))) & 0xff; + + return ZXIC_OK; +} + +/***********************************************************/ +/** 比特流拼装，比特流的形式为: p_base的低字节存放 + 数据的高比特，高字节存放数据的低比特。 +* @param p_base +* @param base_size_bit +* @param data 数据, 比特顺序左高右低，大端比特序 +* @param msb_start_pos 数据最高比特的位置 +* @param len 数据长度 +* +* @return +* @remark exp: + ZXIC_UINT8 data0[4] = {0x22, 0x44, 0x66, 0x88}; + zxic_comm_write_bits_ex(data0, 32, 0x123456, 23,24); + ZXIC_COMM_PRINT("0x%02X %02X %02X %02X \n", data0[0], data0[1], data0[2], data0[3]); + 输出：0x22 12 34 56 + +* @see +* @author 王春雷 @date 2014/03/08 +************************************************************/ +ZXIC_RTN32 zxic_comm_write_bits_ex(ZXIC_UINT8 * p_base, + ZXIC_UINT32 base_size_bit, + ZXIC_UINT32 data, + ZXIC_UINT32 msb_start_pos, + ZXIC_UINT32 len) +{ + ZXIC_RTN32 rtn = ZXIC_OK; + ZXIC_COMM_CHECK_POINT(p_base); + + ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW(base_size_bit, 1); + ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(base_size_bit - 1, msb_start_pos); + ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(base_size_bit - 1 - msb_start_pos, len); + ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW(base_size_bit - 1 - msb_start_pos + len, 1); + + rtn = zxic_comm_write_bits(p_base, + base_size_bit, + data, + (base_size_bit - 1 - msb_start_pos), + (base_size_bit - 1 - msb_start_pos + len - 1)); + + return rtn; +} + +/***********************************************************/ +/** 从比特流中读取数据，比特流的形式为: p_base的低字节存放 + 数据的高比特，高字节存放数据的低比特。 +* @param p_base +* @param base_size_bit +* @param p_data +* @param msb_start_pos +* @param len +* +* @return +* @remark exp: + ZXIC_UINT8 data0[4] = {0x22, 0x44, 0x66, 0x88}; + zxic_comm_read_bits_ex(data0, 32, &test_a, 23, 24); + ZXIC_COMM_PRINT("0test_a = 0x%x \n", test_a); + 输出: 0test_a = 0x446688 + +* @see +* @author 王春雷 @date 2014/03/08 +************************************************************/ +ZXIC_RTN32 zxic_comm_read_bits_ex(ZXIC_UINT8 * p_base, + ZXIC_UINT32 base_size_bit, + ZXIC_UINT32 * p_data, + ZXIC_UINT32 msb_start_pos, + ZXIC_UINT32 len) +{ + ZXIC_RTN32 rtn = ZXIC_OK; + ZXIC_COMM_CHECK_POINT(p_base); + ZXIC_COMM_CHECK_POINT(p_data); + + ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW(base_size_bit, 1); + ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(base_size_bit - 1, msb_start_pos); + ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(base_size_bit - 1 - msb_start_pos, len); + ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW(base_size_bit - 1 - msb_start_pos + len, 1); + + rtn = zxic_comm_read_bits(p_base, + base_size_bit, + p_data, + (base_size_bit - 1 - msb_start_pos), + (base_size_bit - 1 - msb_start_pos + len - 1)); + return rtn; +} +#endif /* */ + +#if ZXIC_REAL("字符串") +/***********************************************************/ +/** +* @param buffer 目标字符串 +* @param sizeofbuf sizeofbuffer +* @param count 要拷贝字节数 +* @param format +* +* @return 待拷贝的实际字符串长度 +* @remark snprintf +* @see +* @author sj @date 2020/12/09 +************************************************************/ +ZXIC_SINT32 ic_comm_snprintf_s(ZXIC_CHAR *buffer, ZXIC_SIZE_T sizeofbuf, ZXIC_SIZE_T count, const ZXIC_CHAR *format, ...) +{ + va_list ap; + ZXIC_SINT32 ret = -1; + + if ((ZXIC_NULL == buffer)||(ZXIC_NULL == format)) + { + ZXIC_COMM_TRACE_ERROR("\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__); + return ret; + } + if (!count) + { + ZXIC_COMM_TRACE_ERROR("\n ZXIC %s:%d[Error:count err], FUNCTION : %s!\n", __FILE__, __LINE__, __FUNCTION__); + return ret; + } + va_start(ap, format); + ret = ZXIC_COMM_VSNPRINTF_S(buffer, sizeofbuf, count, format, ap); + va_end(ap); + + if (ret == -1) + { + ZXIC_COMM_TRACE_ERROR("\n ZXIC %s:%d[Error:snprintf_s err], FUNCTION : %s!\n", __FILE__, __LINE__, __FUNCTION__); + } + return ret; +} +/***********************************************************/ +/** +* @param buffer 目标字符串 +* @param sizeofbuf sizeofbuffer +* @param count 要拷贝字节数 +* @param format +* +* @return 待拷贝的实际字符串长度 +* @remark vsnprintf +* @see +* @author sj @date 2020/12/09 +************************************************************/ +ZXIC_SINT32 ic_comm_vsnprintf_s(ZXIC_CHAR *buffer, ZXIC_SIZE_T sizeofbuf, ZXIC_SIZE_T count, const ZXIC_CHAR *format, va_list ap) +{ + ZXIC_SINT32 ret = -1; + + if ((ZXIC_NULL == buffer)||(ZXIC_NULL == format)) + { + ZXIC_COMM_TRACE_ERROR("\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__); + return ret; + } + if (!count) + { + ZXIC_COMM_TRACE_ERROR("\n ZXIC %s:%d[Error:count err], FUNCTION : %s!\n", __FILE__, __LINE__, __FUNCTION__); + return ret; + } + if (count < sizeofbuf) + { + sizeofbuf = count; + } +#ifdef ZXIC_OS_WIN + ret = _vsnprintf(buffer, sizeofbuf, format, ap); +#else + ret = vsnprintf(buffer, sizeofbuf, format, ap); +#endif + if (ret == -1) + { + ZXIC_COMM_TRACE_ERROR("\n ZXIC %s:%d[Error:vsnprintf err], FUNCTION : %s!\n", __FILE__, __LINE__, __FUNCTION__); + } + return ret; +} + +/***********************************************************/ +/** +* @param pcDst 　　 目的地址 +* @param dwMaxSize　目的长度 +* @param pcSrc 　　 源地址 +* @param dwCount　 要复制的最大字符数 +* +* @return +* @remark 将源地址的字符拷贝到目的字符数组; +* @see +* @author +************************************************************/ +ZXIC_CHAR *ic_comm_strncpy_s( ZXIC_CHAR *pcDst, size_t dwMaxSize, ZXIC_CONST ZXIC_CHAR *pcSrc, size_t dwCount ) +{ + size_t dwIndex = 1, dwCopyNum = dwCount; + ZXIC_CHAR *pcResult = pcDst; + + ZXIC_COMM_CHECK_RC_POINT_NO_PRINT(pcDst, pcResult); + ZXIC_COMM_CHECK_RC_POINT_NO_PRINT(pcSrc, pcResult); + + if (( dwMaxSize <= 1 ) || (dwMaxSize > ZXIC_COMM_MEMORY_MAX_B_SIZE) || ( dwCount == 0 ) ) + { + return pcResult; + } + + /* 计算拷贝的字符长度，不含结束符 */ + if ( dwCount >= dwMaxSize ) + { + dwCopyNum = dwMaxSize - 1; + } + + if (ic_comm_getAbsValue((unsigned ZXIC_CHAR*)pcDst, (ZXIC_CONST ZXIC_UINT8*)pcSrc) < dwCopyNum) + { + return pcResult; + } + + while ( '\0' != ( *pcDst++ = *pcSrc++ ) ) + { + /* 判断拷贝字符数是否等于dwCopyNum，等于就退出 */ + /* 由于判断放在循环体内，进行判断前已经拷贝了一次，所以i初试值为1 */ + if ( dwIndex++ >= dwCopyNum ) + { + *pcDst = '\0'; + + return pcResult; + } + } + + /* 本处的处理是为了保持和库函数中的解释一致，对于源串长度小于dwCopyNum，剩余部分全部填0 */ + while ( dwIndex++ <= dwCopyNum ) + { + *pcDst++ = '\0'; + } + + return pcResult; +} + +ZXIC_SIZE_T ic_comm_getAbsValue(ZXIC_UINT8* dest, ZXIC_CONST ZXIC_UINT8* src) +{ + return dest > src ? (dest - src) : (src - dest); +} +/***********************************************************/ +/** +* @param dest 　　目的地址 +* @param src 　源地址 +* @param n　　 要复制的长度 +* +* @return +* @remark 从源地址拷贝若干字节的长度到目的内存处 +* @see +* @author +************************************************************/ +ZXIC_RTN32 ic_comm_memcpy(ZXIC_VOID* dest, ZXIC_CONST ZXIC_VOID* src, size_t n) +{ + ZXIC_COMM_CHECK_POINT(dest); + ZXIC_COMM_CHECK_POINT(src); + + /* memcpy 的大小限制在200M */ + if(n > 200 * 1024 * 1024) + { + return ZXIC_PAR_CHK_INVALID_PARA; + } + + if (ic_comm_getAbsValue((ZXIC_UINT8*)dest, (ZXIC_CONST ZXIC_UINT8*)src) < n) + { + return ZXIC_ERR; + } +#ifdef ZXIC_OS_WIN + memcpy(dest, src, n); +#else + //__memcpy_chk(dest, src, n, n); + memcpy(dest,src,n); +#endif + return ZXIC_OK; +} +/***********************************************************/ +/** +* @param dest 　　目的地址 +* @param dest_len　目的长度 +* @param src 　源地址 +* @param n　　 要复制的长度 +* +* @return +* @remark 从源地址拷贝若干字节的长度到目的内存处,增加源目的长度之间的检查 +* @see +* @author +************************************************************/ +ZXIC_RTN32 ic_comm_memcpy_s(ZXIC_VOID* dest, size_t dest_len, const void* src, size_t n) +{ + ZXIC_COMM_CHECK_POINT(dest); + ZXIC_COMM_CHECK_POINT(src); + + /* memcpy 的大小限制在200M */ + if(n > 200 * 1024 * 1024) + { + return ZXIC_PAR_CHK_INVALID_PARA; + } + + if (ic_comm_getAbsValue((ZXIC_UINT8 *)dest, (ZXIC_CONST ZXIC_UINT8*)src) < n) + { + return ZXIC_PAR_CHK_ARGIN_ERROR; + } +#ifdef ZXIC_OS_WIN + if (dest_len < n) + { + return ZXIC_ERR; + } + memcpy(dest, src, n); +#else + //__memcpy_chk(dest, src, n, dest_len); + memcpy(dest, src, n); +#endif + return ZXIC_OK; +} + +/***********************************************************/ +/** +* @param pcDst 　　 目的地址 +* @param dwMaxSize　目的长度 +* @param pcSrc 　　 源地址 +* @param dwCount 　 待连接的字符数 +* +* @return +* @remark 字符串连接函数，将pcSrc的dwCount字符复制到pcDst的字符串后，覆盖"\0"; +* @see +* @author +************************************************************/ +ZXIC_CHAR *ic_comm_strncat_s( ZXIC_CHAR *pcDst, size_t dwMaxSize, ZXIC_CONST ZXIC_CHAR *pcSrc, size_t dwCount ) +{ + ZXIC_SIZE_T dwIndex = 1, dwCopyNum = 0; + ZXIC_CHAR *pcResult = pcDst; + + ZXIC_COMM_CHECK_RC_POINT_NO_PRINT(pcDst, pcResult); + ZXIC_COMM_CHECK_RC_POINT_NO_PRINT(pcSrc, pcResult); + + if (( dwMaxSize == 0 ) || (dwMaxSize > ZXIC_COMM_MEMORY_MAX_B_SIZE) || ( dwCount == 0 ) ) + { + return pcResult; + } + + /* 计算目的串的长度 */ + while ( ( *pcDst++ != '\0' ) && ( ++dwCopyNum < dwMaxSize ) ) + { + } + + if ( dwCopyNum >= dwMaxSize ) + { + return pcResult; + } + + dwCopyNum = dwMaxSize - dwCopyNum; /* 计算剩余的缓冲区长度 */ + + /* 计算拷贝的字符长度，不含结束符 */ + if ( dwCount >= dwCopyNum ) + { + dwCopyNum = dwCopyNum - 1; + } + else + { + dwCopyNum = dwCount; + } + + if (dwCopyNum == 0) /* 宋志强 修正pcDst 空间刚好满导致内存越界的问题 */ + { + return pcResult; + } + + pcDst --; + + if (ic_comm_getAbsValue((unsigned ZXIC_CHAR*)pcDst, (const unsigned ZXIC_CHAR*)pcSrc) < dwCopyNum) + { + return pcResult; + } + + while ( '\0' != ( *pcDst++ = *pcSrc++ ) ) + { + /* 判断拷贝字符数是否等于dwCopyNum，等于就退出 */ + /* 由于判断放在循环体内，进行判断前已经拷贝了一次，所以i初试值为1 */ + if ( dwIndex++ >= dwCopyNum ) + { + *pcDst = '\0'; + + return pcResult; + } + } + + /* 本处的处理是为了保持和库函数中的解释一致，对于源串长度小于dwCopyNum，剩余部分全部填0 */ + while ( dwIndex++ <= dwCopyNum ) + { + *pcDst++ = '\0'; + } + + return pcResult; +} + +/***********************************************************/ +/** +* @param str 　　字符串首地址 +* @param MaxCount　可返回的最大长度,若计算的长度大于该长度，则返回MaxCount； +* +* @return +* @remark 计算字符串的长度 +* @see +* @author +************************************************************/ +ZXIC_SIZE_T ic_comm_strnlen_s( const ZXIC_CHAR *str, ZXIC_SIZE_T MaxCount) +{ + return (str == 0)? 0: ZXIC_COMM_STRNLEN(str, MaxCount); +} + +ZXIC_VOID ic_comm_memset_s(void* dest, ZXIC_SIZE_T dmax, ZXIC_UINT8 c, ZXIC_SIZE_T n) +{ + if ((ZXIC_NULL == dest) || (dmax > ZXIC_COMM_MEMORY_MAX_B_SIZE) || (0 == n) || (n > dmax)) + { + ZXIC_COMM_TRACE_ERROR("zxic_memset_s para err:ptr is null or size err.\n"); + return; + } + memset(dest, c, n); +} + +ZXIC_SINT32 ic_comm_memcmp(void* str1, const void* str2, ZXIC_SIZE_T n) +{ + if ((ZXIC_NULL == str1) || (ZXIC_NULL == str2)|| (n > ZXIC_COMM_MEMORY_MAX_B_SIZE) || (0 == n)) + { + ZXIC_COMM_TRACE_ERROR("zxic_memcmp para err:ptr is null or size more than 200M.\n"); + return 0x7fffffff; + } + return memcmp(str1, str2, n); +} +#endif + +ZXIC_RTN32 zxic_comm_random() +{ + +#ifdef ZXIC_OS_WIN + /* return RtlGenRandom(); Modify by wcl, 20200424, Windows版本编译失败,先改回rand */ + return rand(); +#else + ZXIC_UINT8 buff[4] = {0}; + ZXIC_UINT32 ticks = 0; + ZXIC_UINT32 random_d = 0; + struct timespec64 tv; + ZXIC_UINT32 result_len = 0; + struct file *fd = NULL; + loff_t pos = 0; + + //fd = open("/dev/urandom", O_RDONLY); + fd = filp_open("/dev/urandom",O_RDONLY,0); + + if(NULL==fd) + { + get_timespec64(&tv, ZXIC_NULL); + ticks = ((tv.tv_sec & ZXIC_UINT32_MAX) + (tv.tv_nsec & ZXIC_UINT32_MAX)) & ZXIC_UINT32_MAX; + random_d = ticks; + } + else if ((result_len = (kernel_read(fd, buff, ZXIC_SIZEOF(buff),&pos) & 0xFFFFFFFF)) != ZXIC_SIZEOF(buff)) + { + get_timespec64(&tv, ZXIC_NULL); + ticks = ((tv.tv_sec & ZXIC_UINT32_MAX) + (tv.tv_nsec & ZXIC_UINT32_MAX)) & ZXIC_UINT32_MAX; + random_d = ticks; + filp_close(fd,NULL); + } + else + { + random_d = (((buff[0] << 24) & 0xff000000) | + ((buff[1] << 16) & 0x00ff0000) | + ((buff[2] << 8) & 0x0000ff00) | + (buff[3] & 0x000000ff)); + filp_close(fd,NULL); + } + + return random_d; +#endif + +} + +/***********************************************************/ +/** 设置最大通道数 +* @param dev_max 设置的最大设备数 +* +* @return +* @remark 无 +* @see +* @author lihk @date 2021/03/31 +************************************************************/ +ZXIC_VOID zxic_comm_channel_max_set(ZXIC_UINT32 dev_max) +{ + g_zxic_comm_channel_max = dev_max; +} + +/***********************************************************/ +/** 获取最大通道数 +* @param +* +* @return +* @remark 无 +* @see +* @author lihk @date 2021/03/31 +************************************************************/ +ZXIC_RTN32 zxic_comm_channel_max_get(ZXIC_VOID) +{ + return g_zxic_comm_channel_max; +} diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/comm/source/zxic_private_top.c b/src/net/drivers/net/ethernet/dinghai/en_np/comm/source/zxic_private_top.c new file mode 100644 index 0000000..8e5d260 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/comm/source/zxic_private_top.c @@ -0,0 +1,148 @@ +/************************************************************** +* 版权所有 (C)2013-2020, 深圳市中兴通讯股份有限公司 +* 文件名称 : zxic_common.c +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : xuchenxi_10235594 +* 完成日期 : 2020/07/20 +* DEPARTMENT: 有线开发四部-系统软件团队 +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ +#include "zxic_private_top.h" +#include "zxic_common.h" +#include +//#include +//#include +#include +#include +#include +//#include +//#include +//#include +#include + +#ifdef ZXIC_OS_WIN +#include +#include +#include +#include +#pragma warning (disable:4996) +#else +//#include +#include +#include +#include +#include +#include +#include +#include +#endif + +#if ZXIC_REAL("参数检查函数定义") +/***********************************************************/ +/** +* @param val +* @param min +* @param max +* +* @return +* @remark 无 +* @see +* @author XXX @date 2019/07/13 +************************************************************/ +ZXIC_RTN32 zxic_comm_index_check(ZXIC_UINT32 val, ZXIC_UINT32 min, ZXIC_UINT32 max) +{ + if (min <= max) + { + if (0 == min) + { + if ((val) > (max)) + { + return ZXIC_PAR_CHK_INVALID_INDEX; + } + } + else + { + if ((val) < (min) || (val) > (max)) + { + return ZXIC_PAR_CHK_INVALID_INDEX; + } + } + } + else + { + return ZXIC_PAR_CHK_INVALID_RANGE; + } + + return ZXIC_OK; +} + +/***********************************************************/ +/** +* @param dev_id +* @param val +* @param min +* @param max +* +* @return +* @remark 无 +* @see +* @author PJ @date 2019/07/13 +************************************************************/ +ZXIC_RTN32 zxic_comm_dev_index_check(ZXIC_UINT32 dev_id, + ZXIC_UINT32 val, + ZXIC_UINT32 min, + ZXIC_UINT32 max) +{ + if (min <= max) + { + if (0 == min) + { + if ((val) > (max)) + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "ZXIC %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__); + return ZXIC_PAR_CHK_INVALID_INDEX; + } + } + else + { + if ((val) < (min) || (val) > (max)) + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "ZXIC %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__); + return ZXIC_PAR_CHK_INVALID_INDEX; + } + } + } + else + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "ZXIC %s:%d[Error:RANGE INVALID] [val=0x%x,min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__); + return ZXIC_PAR_CHK_INVALID_RANGE; + } + + return ZXIC_OK; +} + +#endif + + + + + + + + + + + + + + + diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/dpp_kshell b/src/net/drivers/net/ethernet/dinghai/en_np/dpp_kshell new file mode 100755 index 0000000000000000000000000000000000000000..96cc61d30213aaee14c387d0486377c20b472a49 GIT binary patch literal 4477496 zcmd443tUuH_cwk}5WL{vH8M>!yk-Ta=8a;M(ZQfd#ndt{2#PldhO|sYf#f(&VP@Ig z?sl=PCrK#{)I@u%$gIq)$Zm%)vx{b$^8c>2&Y9T*Oi$16|Nh?3>+{5%_1$ajz4lsb z@4fauXU;5hB#mkk6r@@InrK&RM4gCx$Yt{2oUiJL_j9Z^K>)}jqD1VqgEjdz;j>))z34jS)Z2N4Ui)}|LMO7lX0xo zUI4qqn3Y3>iH!Az94{}%L4SbG(fvQ2H=kifcJu7qb%bppGN}dISV|E+2OGO`s4@b*H;1f z&jzUf(g6DJ3xMAfp#Gf!@ZACGxhw#G+W`E%0`TVth_@2~`db{Jo-YEldtm@PGywi? zfcozYpwHC-;^B_~_|5=+zb-(#Ezxci{;U7*$pCiyIzYP@2jKrW0RO)N@Fxf0r`05? zzLKDy2+-fe0QOG`&~CE;?LH8|ZZ`y||5N~df&arbutQk@Jx>LwCpv(hivraDc>q06259%P0Q{!| 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zt7~17`&HLE0j9ZyoXAU+wEVd-Chh9a1^szI*PUZ94sDXC{$FkXaWO;rayO=wJNcrG z>qT=va@UgLUp~G_$=AATRJG1=-hF7ti~=v`!ON7qKS!zjMP&%mip^@dilXBy=%^#Opb~H8UKB#K6O+s$t0J5=~kXe XV$~d(wr9$vhb86T%4g_Ebr}6WYq7iu literal 0 HcmV?d00001 diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/driver/Kbuild.include b/src/net/drivers/net/ethernet/dinghai/en_np/driver/Kbuild.include new file mode 100644 index 0000000..3327213 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/driver/Kbuild.include @@ -0,0 +1,4 @@ +cur_dir := en_np/driver/ +subdirs := source/ +src_files += +include $(foreach subdir, $(subdirs), $(dinghai_root)/$(cur_dir)$(subdir)/Kbuild.include) \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/driver/include/dpp_drv_acl.h b/src/net/drivers/net/ethernet/dinghai/en_np/driver/include/dpp_drv_acl.h new file mode 100644 index 0000000..340d346 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/driver/include/dpp_drv_acl.h @@ -0,0 +1,85 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_drv_acl.h +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : +* 完成日期 : 2014/01/27 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ + +#ifndef DPP_DRV_ACL_H +#define DPP_DRV_ACL_H + +#include "zxic_common.h" +#include "dpp_apt_se_api.h" + +/* etcam级联地址划分 */ +#define ZXDH_FD_AS_ERAM_BAADDR (ZXIC_UINT32)(0x38000) +#define ZXDH_FD_AS_ERAM_DEPTH (ZXIC_UINT32)(2048) + +#define ZXDH_IPSEC_ENC_AS_ERAM_BAADDR (ZXIC_UINT32)(0x38B00) +#define ZXDH_IPSEC_ENC_AS_ERAM_DEPTH (ZXIC_UINT32)(1024) + +/* etcam表项 0~7 */ +#define ZXDH_ACL_FD_CFG_ID (ZXIC_UINT32)(0) +#define ZXDH_ACL_TBL_ID1 (ZXIC_UINT32)(1) +#define ZXDH_ACL_TBL_ID2 (ZXIC_UINT32)(2) +#define ZXDH_ACL_TBL_ID3 (ZXIC_UINT32)(3) +#define ZXDH_ACL_TBL_ID4 (ZXIC_UINT32)(4) +#define ZXDH_ACL_TBL_ID5 (ZXIC_UINT32)(5) +#define ZXDH_ACL_TBL_ID6 (ZXIC_UINT32)(6) +#define ZXDH_ACL_TBL_ID7 (ZXIC_UINT32)(7) + +typedef struct zxdh_ipsec_enc_key +{ + ZXIC_UINT8 dip[16]; + ZXIC_UINT8 sip[16]; + ZXIC_UINT32 rsv2; + ZXIC_UINT32 rsv1; +}ZXDH_IPSEC_ENC_KEY; + +typedef struct zxdh_ipsec_enc_mask +{ + ZXIC_UINT8 dip[16]; + ZXIC_UINT8 sip[16]; + ZXIC_UINT32 rsv2; + ZXIC_UINT32 rsv1; +}ZXDH_IPSEC_ENC_MASK; + +typedef struct zxdh_ipsec_enc_entry +{ + ZXIC_UINT32 sa_id; + ZXIC_UINT32 rsv; + ZXIC_UINT32 hit_flag; +}ZXDH_IPSEC_ENC_ENTRY; + +typedef struct zxdh_ipsec_enc_t +{ + ZXIC_UINT32 index; + ZXDH_IPSEC_ENC_KEY key; + ZXDH_IPSEC_ENC_MASK mask; + ZXDH_IPSEC_ENC_ENTRY entry; +} ZXDH_IPSEC_ENC_T; + +ZXIC_UINT32 dpp_apt_set_ipsec_enc_data(ZXIC_VOID *pData,DPP_ACL_ENTRY_EX_T *aclEntry); +ZXIC_UINT32 dpp_apt_get_ipsec_enc_data(ZXIC_VOID *pData,DPP_ACL_ENTRY_EX_T *aclEntry); + +typedef struct dpp_acl_init_t +{ + ZXIC_UINT32 tbl_num; + DPP_APT_ACL_TABLE_T *acl; +} DPP_ACL_INIT_T; + +extern DPP_ACL_INIT_T g_aclTable; + +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/driver/include/dpp_drv_eram.h b/src/net/drivers/net/ethernet/dinghai/en_np/driver/include/dpp_drv_eram.h new file mode 100644 index 0000000..5b3f058 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/driver/include/dpp_drv_eram.h @@ -0,0 +1,262 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_drv_eram.h +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : +* 完成日期 : 2014/01/27 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ + +#ifndef DPP_DRV_ERAM_H +#define DPP_DRV_ERAM_H + +#include "zxic_common.h" +#include "dpp_apt_se_api.h" + +#define ZXDH_VXLAN_ERAM_BAADDR ((ZXIC_UINT32)(0x8000)) +#define ZXDH_VXLAN_ERAM_DEPTH ((ZXIC_UINT32)(2)) + +#define ZXDH_VPORT_ATTR_ERAM_BAADDR ((ZXIC_UINT32)(0x8001)) +#define ZXDH_VPORT_ATTR_ERAM_DEPTH ((ZXIC_UINT32)(1280)) + +#define ZXDH_PANEL_PORT_ATTR_ERAM_BAADDR ((ZXIC_UINT32)(0x87F9)) +#define ZXDH_PANEL_PORT_ATTR_ERAM_DEPTH ((ZXIC_UINT32)(16)) + +#define ZXDH_RSS_TO_VQID_ERAM_BAADDR ((ZXIC_UINT32)(0x8809)) +#define ZXDH_RSS_TO_VQID_ERAM_DEPTH ((ZXIC_UINT32)(38144)) + +#define ZXDH_VLAN_FILTER_ERAM_BAADDR ((ZXIC_UINT32)(0x11D09)) +#define ZXDH_VLAN_FILTER_ERAM_DEPTH ((ZXIC_UINT32)(71680)) + +#define ZXDH_LAG_ERAM_BAADDR ((ZXIC_UINT32)(0x23509)) +#define ZXDH_LAG_ERAM_DEPTH ((ZXIC_UINT32)(8)) + +#define ZXDH_BC_ERAM_BAADDR ((ZXIC_UINT32)(0x2350D)) +#define ZXDH_BC_ERAM_DEPTH ((ZXIC_UINT32)(256)) + +#define ZXDH_STAT_PPU_ERAM_BAADDR ((ZXIC_UINT32)(0x68000)) +#define ZXDH_STAT_PPU_ERAM_DEPTH ((ZXIC_UINT32)(0x1C000)) // 此数值以64bit为单位 + +#define ZXDH_DSCP_TO_UP_ERAM_BAADDR ((ZXIC_UINT32)(0x2370D)) +#define ZXDH_DSCP_TO_UP_ERAM_DEPTH ((ZXIC_UINT32)(1024)) + +#define ZXDH_UP_TO_TC_ERAM_BAADDR ((ZXIC_UINT32)(0x2390D)) +#define ZXDH_UP_TO_TC_ERAM_DEPTH ((ZXIC_UINT32)(128)) + +#define ZXDH_VHCA_ERAM_BAADDR ((ZXIC_UINT32)(0x40000)) +#define ZXDH_VHCA_ERAM_DEPTH ((ZXIC_UINT32)(0x800)) + +#define ZXDH_UC_PROMISC_ERAM_BAADDR ((ZXIC_UINT32)(0x2398E)) +#define ZXDH_UC_PROMISC_ERAM_DEPTH ((ZXIC_UINT32)(256)) + +#define ZXDH_MC_PROMISC_ERAM_BAADDR ((ZXIC_UINT32)(0x23A8E)) +#define ZXDH_MC_PROMISC_ERAM_DEPTH ((ZXIC_UINT32)(256)) + +typedef struct zxdh_vxlan_t +{ + ZXIC_UINT64 port : 16; + ZXIC_UINT64 rsv : 47; + ZXIC_UINT64 hit_flag : 1; +} ZXDH_VXLAN_T; + +typedef struct zxdh_vport_t +{ + ZXIC_UINT32 tpid/* : 16; */; + ZXIC_UINT32 vhca/* : 10; */; + ZXIC_UINT32 uplink_port/* : 6; */; + + ZXIC_UINT32 rss_hash_factor/* : 8; */; + ZXIC_UINT32 hash_alg/* : 4; */; + ZXIC_UINT32 panel_id/* : 4; */; + + ZXIC_UINT32 lag_id/* : 3; */; + ZXIC_UINT32 pf_vqm_vfid/* : 11; */; + ZXIC_UINT32 rsv3/* : 2; */; + + ZXIC_UINT32 mtu/* : 16; */; + + ZXIC_UINT32 port_base_qid/* : 12; */; + ZXIC_UINT32 hash_search_index/* : 3; */; + ZXIC_UINT32 rsv1/* : 1; */; + + ZXIC_UINT32 tm_enable/* : 1; */; + ZXIC_UINT32 ingress_meter_enable/* : 1; */; + ZXIC_UINT32 egress_meter_enable/* : 1; */; + ZXIC_UINT32 ingress_meter_mode/* : 1; */; + ZXIC_UINT32 egress_meter_mode/* : 1; */; + ZXIC_UINT32 fd_enable/* : 1; */; + ZXIC_UINT32 vepa_enable/* : 1; */; + ZXIC_UINT32 spoof_check_enable/* : 1; */; + + ZXIC_UINT32 inline_sec_offload/* : 1; */; + ZXIC_UINT32 ovs_enable/* : 1; */; + ZXIC_UINT32 lag_enable/* : 1; */; + ZXIC_UINT32 is_passthrough/* : 1; */; + ZXIC_UINT32 is_vf/* : 1; */; + ZXIC_UINT32 virtion_version/* : 2; */; + ZXIC_UINT32 virtio_enable/* : 1; */; + + ZXIC_UINT32 accelerator_offload_flag/* : 1; */; + ZXIC_UINT32 lro_offload/* : 1; */; + ZXIC_UINT32 ip_fragment_offload/* : 1; */; + ZXIC_UINT32 tcp_udp_checksum_offload/* : 1; */; + ZXIC_UINT32 ip_checksum_offload/* : 1; */; + ZXIC_UINT32 outer_ip_checksum_offload/* : 1; */; + ZXIC_UINT32 is_up/* : 1; */; + ZXIC_UINT32 allmulticast_enable/* : 1; */; + + ZXIC_UINT32 hw_bond_enable/* : 1; */; + ZXIC_UINT32 rdma_offload_enable/* : 1; */; + ZXIC_UINT32 vlan_filter_enable/* : 1; */; + ZXIC_UINT32 vlan_strip_offload/* : 1; */; + ZXIC_UINT32 qinq_vlan_strip_offload/* : 1; */; + ZXIC_UINT32 rss_enable/* : 1; */; + ZXIC_UINT32 mtu_offload_enable/* : 1; */; + ZXIC_UINT32 hit_flag/*: 1; */; +} ZXDH_VPORT_T; + +typedef struct zxdh_panel_port_t +{ + ZXIC_UINT32 rsv7 /* : 16; */; + ZXIC_UINT32 ovs_pf_vfid /* : 11; */; + ZXIC_UINT32 rsv6 /* : 5; */; + ZXIC_UINT32 pf_memport_qid /* : 12; */; + ZXIC_UINT32 rsv5 /* : 4; */; + ZXIC_UINT32 bond_pf_vqm_vfid /* : 11; */; + ZXIC_UINT32 rsv4 /* : 2; */; + ZXIC_UINT32 is_up /* : 1; */; + ZXIC_UINT32 bond_link_up /* : 1; */; + ZXIC_UINT32 hw_bond_enable /* : 1; */; + ZXIC_UINT32 mtu /* : 16; */; + ZXIC_UINT32 mtu_offload_enable /* : 1; */; + ZXIC_UINT32 rsv3 /* : 3; */; + ZXIC_UINT32 tm_base_queue /* : 12; */; + ZXIC_UINT32 ptp_port_vfid /* : 11; */; + ZXIC_UINT32 rsv2 /* : 5; */; + ZXIC_UINT32 pf_vqm_vfid /* : 11 */; + ZXIC_UINT32 tm_shape_enable /* : 1; */; + ZXIC_UINT32 ptp_tc_enable /* : 2; */; + ZXIC_UINT32 trust_mode /* : 1; */; + ZXIC_UINT32 hit_flag /* : 1; */; +} ZXDH_PANEL_PORT_T; + +typedef struct zxdh_dscp_to_up_t +{ + ZXIC_UINT32 rsv2 /* : 32; */; + ZXIC_UINT32 up /* : 3; */; + ZXIC_UINT32 rsv1 /* : 28; */; + ZXIC_UINT32 hit_flag /* : 1; */; +} ZXDH_DSCP_TO_UP_T; + +typedef struct zxdh_up_to_tc_t +{ + ZXIC_UINT32 rsv2 /* : 32; */; + ZXIC_UINT32 tc /* : 3; */; + ZXIC_UINT32 rsv1 /* : 28; */; + ZXIC_UINT32 hit_flag /* : 1; */; +} ZXDH_UP_TO_TC_T; + +typedef struct zxdh_rss_to_vqid_t +{ + ZXIC_UINT32 vqm_qid[8]; + ZXIC_UINT32 hit_flag; +} ZXDH_RSS_TO_VQID_T; + +typedef struct zxdh_vlan_filter_t +{ + ZXIC_UINT8 vport_bitmap[15]; + ZXIC_UINT8 rsv : 7; + ZXIC_UINT8 hit_flag : 1; + +} ZXDH_VLAN_FILTER_T; + +typedef struct zxdh_lag_t +{ + ZXIC_UINT32 member_bitmap; + ZXIC_UINT32 rsv2; + ZXIC_UINT32 hash_factor; + ZXIC_UINT32 bond_mode; + ZXIC_UINT32 member_num; + ZXIC_UINT32 rsv1; + ZXIC_UINT32 hit_flag; +} ZXDH_LAG_T; + +typedef struct zxdh_bc_t +{ + ZXIC_UINT64 bc_bitmap; + ZXIC_UINT32 rsv2; + ZXIC_UINT32 rsv1; + ZXIC_UINT32 hit_flag; +} ZXDH_BC_T; + +typedef struct zxdh_promisc_t +{ + ZXIC_UINT64 bitmap; + ZXIC_UINT32 rsv2; + ZXIC_UINT32 rsv1; + ZXIC_UINT32 pf_enable; + ZXIC_UINT32 hit_flag; +} ZXDH_PROMISC_T; + +typedef struct zxdh_vhca_t +{ + ZXIC_UINT32 rsv2; + ZXIC_UINT32 vqm_vfid; + ZXIC_UINT32 rsv1; + ZXIC_UINT32 valid; +} ZXDH_VHCA_T; + +/*************eram call back ****************/ +ZXIC_UINT32 dpp_apt_set_vxlan_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4]); +ZXIC_UINT32 dpp_apt_get_vxlan_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4]); + +ZXIC_UINT32 dpp_apt_set_vport_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4]); +ZXIC_UINT32 dpp_apt_get_vport_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4]); + +ZXIC_UINT32 dpp_apt_set_panel_port_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4]); +ZXIC_UINT32 dpp_apt_get_panel_port_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4]); + +ZXIC_UINT32 dpp_apt_set_dscp_to_up_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4]); +ZXIC_UINT32 dpp_apt_get_dscp_to_up_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4]); + +ZXIC_UINT32 dpp_apt_set_up_to_tc_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4]); +ZXIC_UINT32 dpp_apt_get_up_to_tc_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4]); + +ZXIC_UINT32 dpp_apt_set_rss_to_vqid_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4]); +ZXIC_UINT32 dpp_apt_get_rss_to_vqid_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4]); + +ZXIC_UINT32 dpp_apt_set_vlan_filter_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4]); +ZXIC_UINT32 dpp_apt_get_vlan_filter_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4]); + +ZXIC_UINT32 dpp_apt_set_lag_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4]); +ZXIC_UINT32 dpp_apt_get_lag_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4]); + +ZXIC_UINT32 dpp_apt_set_bc_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4]); +ZXIC_UINT32 dpp_apt_get_bc_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4]); + +ZXIC_UINT32 dpp_apt_set_promisc_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4]); +ZXIC_UINT32 dpp_apt_get_promisc_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4]); + +ZXIC_UINT32 dpp_apt_set_vhca_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4]); +ZXIC_UINT32 dpp_apt_get_vhca_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4]); + + +typedef struct dpp_eram_init_t +{ + ZXIC_UINT32 tbl_num; + DPP_APT_ERAM_TABLE_T *eram; +} DPP_ERAM_INIT_T; + +extern DPP_ERAM_INIT_T g_eRamTable; + +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/driver/include/dpp_drv_hash.h b/src/net/drivers/net/ethernet/dinghai/en_np/driver/include/dpp_drv_hash.h new file mode 100644 index 0000000..8b30f8f --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/driver/include/dpp_drv_hash.h @@ -0,0 +1,97 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_drv_hash.h +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : +* 完成日期 : 2014/01/27 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ +#ifndef DPP_DRV_HASH_H +#define DPP_DRV_HASH_H + +#include "zxic_common.h" +#include "dpp_apt_se_api.h" + +#define ZXDH_L2ENTRY_KEEPALIVE_ERAM_BAADDR (ZXIC_UINT32)(0x0) /* L2转发表保活标志表 */ + +/* hash-function for hash tbl */ +#define ZXDH_HASH_FUNC0 (ZXIC_UINT8)(0) +#define ZXDH_HASH_FUNC1 (ZXIC_UINT8)(1) +#define ZXDH_HASH_FUNC2 (ZXIC_UINT8)(2) +#define ZXDH_HASH_FUNC3 (ZXIC_UINT8)(3) + +/* L2 forward */ +typedef struct zxdh_l2_fwd_key +{ + ZXIC_UINT8 dmac_addr[6]; /**< @brief key */ + ZXIC_UINT16 rsv /* : 16; */; +} ZXDH_L2_FWD_KEY; + +typedef struct zxdh_l2_fwd_entry +{ + ZXIC_UINT32 vqm_vfid /* : 11;*/; + ZXIC_UINT32 rsv /* : 20; */; + ZXIC_UINT32 hit_flag /* : 1; */; +}ZXDH_L2_FWD_ENTRY; + +typedef struct zxdh_l2_fwd_t +{ + ZXDH_L2_FWD_KEY key; + ZXDH_L2_FWD_ENTRY entry; +} ZXDH_L2_ENTRY_T; + +/* multicast */ +typedef struct zxdh_mc_key +{ + ZXIC_UINT8 mc_mac[6]; + ZXIC_UINT32 group_id; + ZXIC_UINT32 rsv; +}ZXDH_MC_KEY; + +typedef struct zxdh_mc_entry +{ + ZXIC_UINT64 mc_bitmap; + ZXIC_UINT32 rsv2; + ZXIC_UINT32 rsv1; + ZXIC_UINT32 mc_pf_enable; + ZXIC_UINT32 hit_flag; +}ZXDH_MC_ENTRY; + +typedef struct zxdh_mc_t +{ + ZXDH_MC_KEY key; + ZXDH_MC_ENTRY entry; +} ZXDH_MC_T; + +ZXIC_UINT32 dpp_apt_set_l2entry_data(ZXIC_VOID *pData, DPP_HASH_ENTRY *pEntry); +ZXIC_UINT32 dpp_apt_get_l2entry_data(ZXIC_VOID *pData, DPP_HASH_ENTRY *pEntry); + +ZXIC_UINT32 dpp_apt_set_mc_data(ZXIC_VOID *pData, DPP_HASH_ENTRY *pEntry); +ZXIC_UINT32 dpp_apt_get_mc_data(ZXIC_VOID *pData, DPP_HASH_ENTRY *pEntry); + +typedef struct dpp_hash_init_t +{ + ZXIC_UINT32 func_num; + DPP_APT_HASH_FUNC_RES_T *func; + ZXIC_UINT32 bulk_num; + DPP_APT_HASH_BULK_RES_T *bulk; + ZXIC_UINT32 ser_num; + DPP_APT_HASH_TABLE_T *ser; +} DPP_HASH_INIT_T; + +extern DPP_HASH_INIT_T g_hashTable; + +DPP_STATUS dpp_apt_dtb_hash_table_unicast_mac_dump(DPP_DEV_T *dev, ZXIC_UINT32 queue_id, ZXIC_UINT32 sdt_no, ZXDH_L2_ENTRY_T *pHashDataArr, ZXIC_UINT32 *p_entry_num); +DPP_STATUS dpp_apt_dtb_hash_table_multicast_mac_dump(DPP_DEV_T *dev, ZXIC_UINT32 queue_id, ZXIC_UINT32 sdt_no, ZXDH_MC_T *pHashDataArr, ZXIC_UINT32 *p_entry_num); + +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/driver/include/dpp_drv_init.h b/src/net/drivers/net/ethernet/dinghai/en_np/driver/include/dpp_drv_init.h new file mode 100644 index 0000000..57da29a --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/driver/include/dpp_drv_init.h @@ -0,0 +1,33 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_drv_init.h +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : +* 完成日期 : 2014/01/27 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ + +#ifndef DPP_DRV_INIT_H +#define DPP_DRV_INIT_H + +#include "zxic_common.h" +#include "dpp_type_api.h" +#include "dpp_dev.h" + +DPP_STATUS dpp_flow_init(DPP_DEV_T *dev); +DPP_STATUS dpp_flow_uninit(ZXIC_UINT32 dev_id); + +DPP_STATUS dpp_flow_data_all_flush(DPP_DEV_T *dev, ZXIC_UINT32 queue_id); + +#endif + diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/driver/include/dpp_drv_sdt.h b/src/net/drivers/net/ethernet/dinghai/en_np/driver/include/dpp_drv_sdt.h new file mode 100644 index 0000000..4c8ca49 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/driver/include/dpp_drv_sdt.h @@ -0,0 +1,62 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_drv_sdt.h +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : +* 完成日期 : 2014/01/27 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ +#ifndef DPP_DRV_SDT_H +#define DPP_DRV_SDT_H + +#include "zxic_common.h" + +/*************SDT配置***************************/ +/* eram直接表 */ +#define ZXDH_SDT_VXLAN_ATTR_TABLE (ZXIC_UINT32)(0) +#define ZXDH_SDT_VPORT_ATTR_TABLE (ZXIC_UINT32)(1) +#define ZXDH_SDT_PANEL_PORT_ATTR_TABLE (ZXIC_UINT32)(2) +#define ZXDH_SDT_RSS_TO_VQID_TABLE (ZXIC_UINT32)(3) +#define ZXDH_SDT_VLAN_FILTER_TABLE (ZXIC_UINT32)(4) +#define ZXDH_SDT_LAG_TABLE (ZXIC_UINT32)(5) +#define ZXDH_SDT_BC_TABLE (ZXIC_UINT32)(6) +#define ZXDH_SDT_DSCP_TO_UP_TABLE (ZXIC_UINT32)(7) +#define ZXDH_SDT_UP_TO_TC_TABLE (ZXIC_UINT32)(8) +#define ZXDH_SDT_VHCA_TABLE (ZXIC_UINT32)(50) +#define ZXDH_SDT_UC_PROMISC_TABLE (ZXIC_UINT32)(10) +#define ZXDH_SDT_MC_PROMISC_TABLE (ZXIC_UINT32)(11) + +/* hash表 */ +#define ZXDH_SDT_L2_ENTRY_TABLE_PHYPORT0 (ZXIC_UINT32)(64) +#define ZXDH_SDT_L2_ENTRY_TABLE_PHYPORT1 (ZXIC_UINT32)(65) +#define ZXDH_SDT_L2_ENTRY_TABLE_PHYPORT2 (ZXIC_UINT32)(66) +#define ZXDH_SDT_L2_ENTRY_TABLE_PHYPORT3 (ZXIC_UINT32)(67) +#define ZXDH_SDT_L2_ENTRY_TABLE_PHYPORT4 (ZXIC_UINT32)(68) +#define ZXDH_SDT_L2_ENTRY_TABLE_PHYPORT5 (ZXIC_UINT32)(69) + +#define ZXDH_SDT_MC_TABLE_PHYPORT0 (ZXIC_UINT32)(76) +#define ZXDH_SDT_MC_TABLE_PHYPORT1 (ZXIC_UINT32)(77) +#define ZXDH_SDT_MC_TABLE_PHYPORT2 (ZXIC_UINT32)(78) +#define ZXDH_SDT_MC_TABLE_PHYPORT3 (ZXIC_UINT32)(79) +#define ZXDH_SDT_MC_TABLE_PHYPORT4 (ZXIC_UINT32)(80) +#define ZXDH_SDT_MC_TABLE_PHYPORT5 (ZXIC_UINT32)(81) + +/* etcam表 */ +#define ZXDH_SDT_FD_CFG_TABLE (ZXIC_UINT32)(130) +#define ZXDH_SDT_IPSEC_ENC_TABLE (ZXIC_UINT32)(131) + +/* 抓包使能 */ +#define ZXDH_SDT_CLUTH_DISABLE (ZXIC_UINT32)(0) +#define ZXDH_SDT_CLUTH_ENABLE (ZXIC_UINT32)(1) + +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/driver/source/Kbuild.include b/src/net/drivers/net/ethernet/dinghai/en_np/driver/source/Kbuild.include new file mode 100644 index 0000000..e99b0f3 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/driver/source/Kbuild.include @@ -0,0 +1,2 @@ +cur_dir := en_np/driver/source/ +src_files += $(addprefix $(cur_dir),$(notdir $(wildcard $(dinghai_root)/$(cur_dir)*.c))) \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/driver/source/dpp_drv_acl.c b/src/net/drivers/net/ethernet/dinghai/en_np/driver/source/dpp_drv_acl.c new file mode 100644 index 0000000..a0f1354 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/driver/source/dpp_drv_acl.c @@ -0,0 +1,162 @@ +#include "dpp_apt_se_api.h" +#include "dpp_se_api.h" +#include "dpp_se_diag.h" +#include "dpp_drv_sdt.h" +#include "dpp_drv_acl.h" + +static DPP_APT_ACL_TABLE_T g_aclSdtTable[] = +{ + { + ZXDH_SDT_FD_CFG_TABLE, + { // sdt表 + DPP_SDT_TBLT_eTCAM, /** <@brief 查找表项类型 DPP_SDT_TABLE_TYPE_E */ + 0, /** <@brief etcam通道 */ + DPP_ACL_KEY_640b, /** <@brief etcam键值长度 DPP_ACL_KEY_MODE_E */ + ZXDH_ACL_TBL_ID2, /** <@brief etcam表项号 */ + DPP_ETCAM_NO_AS_RSP_MODE_32, /** <@brief handle模式返回位宽,非级联 0:默认32bit */ + 1, /** <@brief 级联eram使能 */ + ZXDH_FD_AS_ERAM_BAADDR, /** <@brief 级联eram基地址 */ + DPP_ACL_AS_MODE_128b, /** <@brief 级联返回位宽 DPP_ACL_AS_MODE_E */ + ZXDH_FD_AS_ERAM_DEPTH, /** <@brief 表项深度，越界检查 */ + 0, /** <@brief 抓包使能 */ + }, + { // res表 + DPP_ACL_PRI_SPECIFY, /** <@brief pri_mode */ + 2048, /** <@brief entry_num */ + 4, /** <@brief block_num */ + {2,3,4,5,0,0,0,0}, /** <@brief block_index */ + }, + NULL, /** <@brief 结构体转换为码流 */ + NULL, /** <@brief 码流转换为结构体 */ + }, + { + ZXDH_SDT_IPSEC_ENC_TABLE, + { // sdt表 + DPP_SDT_TBLT_eTCAM, /** <@brief 查找表项类型 DPP_SDT_TABLE_TYPE_E */ + 0, /** <@brief etcam通道 */ + DPP_ACL_KEY_320b, /** <@brief etcam键值长度 DPP_ACL_KEY_MODE_E */ + ZXDH_ACL_TBL_ID3, /** <@brief etcam表项号 */ + DPP_ETCAM_NO_AS_RSP_MODE_32, /** <@brief handle模式返回位宽,非级联 0:默认32bit */ + 1, /** <@brief 级联eram使能 */ + ZXDH_IPSEC_ENC_AS_ERAM_BAADDR, /** <@brief 级联eram基地址 */ + DPP_ACL_AS_MODE_64b, /** <@brief 级联返回位宽 DPP_ACL_AS_MODE_E */ + ZXDH_IPSEC_ENC_AS_ERAM_DEPTH, /** <@brief 表项深度，越界检查 */ + 0, /** <@brief 抓包使能 */ + }, + { // res表 + DPP_ACL_PRI_SPECIFY, /** <@brief pri_mode */ + 256, /** <@brief entry_num */ + 1, /** <@brief block_num */ + {6,0,0,0,0,0,0,0}, /** <@brief block_index */ + }, + dpp_apt_set_ipsec_enc_data, /** <@brief 结构体转换为码流 */ + dpp_apt_get_ipsec_enc_data, /** <@brief 码流转换为结构体 */ + }, +}; + +ZXIC_UINT32 dpp_apt_set_ipsec_enc_data(ZXIC_VOID *pData, DPP_ACL_ENTRY_EX_T *aclEntry) +{ + ZXIC_UINT32 key_data = 0; + ZXIC_UINT32 key_mask = 0; + ZXIC_UINT32 rst = 0; + + ZXDH_IPSEC_ENC_T *ipsec_enc_table = pData; + + ZXIC_COMM_CHECK_POINT(aclEntry); + ZXIC_COMM_CHECK_POINT(ipsec_enc_table); + + aclEntry->pri = ipsec_enc_table->index; + + if(aclEntry->key_data) + { + ZXIC_COMM_UINT32_WRITE_BITS(key_data, ipsec_enc_table->key.rsv1, 0, 32); + zxic_comm_swap((ZXIC_UINT8 *)&key_data, sizeof(ZXIC_UINT32)); + ZXIC_COMM_MEMCPY(aclEntry->key_data, &key_data, sizeof(ZXIC_UINT32)); + + ZXIC_COMM_UINT32_WRITE_BITS(key_data, ipsec_enc_table->key.rsv2, 0, 32); + zxic_comm_swap((ZXIC_UINT8 *)&key_data, sizeof(ZXIC_UINT32)); + ZXIC_COMM_MEMCPY(aclEntry->key_data + 4, &key_data, sizeof(ZXIC_UINT32)); + + ZXIC_COMM_MEMCPY(aclEntry->key_data + 8, ipsec_enc_table->key.sip, 16); + ZXIC_COMM_MEMCPY(aclEntry->key_data + 24, ipsec_enc_table->key.dip, 16); + } + + if(aclEntry->key_mask) + { + ZXIC_COMM_UINT32_WRITE_BITS(key_mask, ipsec_enc_table->mask.rsv1, 0, 32); + zxic_comm_swap((ZXIC_UINT8 *)&key_mask, sizeof(ZXIC_UINT32)); + ZXIC_COMM_MEMCPY(aclEntry->key_mask, &key_mask, sizeof(ZXIC_UINT32)); + + ZXIC_COMM_UINT32_WRITE_BITS(key_mask, ipsec_enc_table->mask.rsv2, 0, 32); + zxic_comm_swap((ZXIC_UINT8 *)&key_mask, sizeof(ZXIC_UINT32)); + ZXIC_COMM_MEMCPY(aclEntry->key_mask + 4, &key_mask, sizeof(ZXIC_UINT32)); + + ZXIC_COMM_MEMCPY(aclEntry->key_mask + 8, ipsec_enc_table->mask.sip, 16); + ZXIC_COMM_MEMCPY(aclEntry->key_mask + 24, ipsec_enc_table->mask.dip, 16); + } + + if(aclEntry->p_as_rslt) + { + ZXIC_COMM_UINT32_WRITE_BITS(rst, ipsec_enc_table->entry.hit_flag, 31, 1); + ZXIC_COMM_UINT32_WRITE_BITS(rst, ipsec_enc_table->entry.rsv, 0, 31); + zxic_comm_swap((ZXIC_UINT8 *)&rst, sizeof(ZXIC_UINT32)); + ZXIC_COMM_MEMCPY(aclEntry->p_as_rslt, &rst, sizeof(ZXIC_UINT32)); + + ZXIC_COMM_UINT32_WRITE_BITS(rst, ipsec_enc_table->entry.sa_id, 0, 32); + zxic_comm_swap((ZXIC_UINT8 *)&rst, sizeof(ZXIC_UINT32)); + ZXIC_COMM_MEMCPY(aclEntry->p_as_rslt + 4, &rst, sizeof(ZXIC_UINT32)); + } + + return DPP_OK; +} + +ZXIC_UINT32 dpp_apt_get_ipsec_enc_data(ZXIC_VOID *pData, DPP_ACL_ENTRY_EX_T *aclEntry) +{ + ZXDH_IPSEC_ENC_T *ipsec_enc_table = pData; + + ZXIC_COMM_CHECK_POINT(aclEntry); + ZXIC_COMM_CHECK_POINT(ipsec_enc_table); + + ipsec_enc_table->index = aclEntry->pri; + + if(aclEntry->key_data) + { + zxic_comm_swap(aclEntry->key_data, sizeof(ZXIC_UINT32)); + ZXIC_COMM_UINT32_GET_BITS(ipsec_enc_table->key.rsv1, *(ZXIC_UINT32 *)(aclEntry->key_data), 0, 32); + + zxic_comm_swap(aclEntry->key_data + 4, sizeof(ZXIC_UINT32)); + ZXIC_COMM_UINT32_GET_BITS(ipsec_enc_table->key.rsv2, *(ZXIC_UINT32 *)(aclEntry->key_data + 4), 0, 32); + + ZXIC_COMM_MEMCPY(ipsec_enc_table->key.sip, aclEntry->key_data + 8, 16); + ZXIC_COMM_MEMCPY(ipsec_enc_table->key.dip, aclEntry->key_data + 24, 16); + } + + if(aclEntry->key_mask) + { + zxic_comm_swap(aclEntry->key_mask, sizeof(ZXIC_UINT32)); + ZXIC_COMM_UINT32_GET_BITS(ipsec_enc_table->mask.rsv1, *(ZXIC_UINT32 *)(aclEntry->key_mask), 0, 32); + + zxic_comm_swap(aclEntry->key_mask + 4, sizeof(ZXIC_UINT32)); + ZXIC_COMM_UINT32_GET_BITS(ipsec_enc_table->mask.rsv2, *(ZXIC_UINT32 *)(aclEntry->key_mask + 4), 0, 32); + + ZXIC_COMM_MEMCPY(ipsec_enc_table->mask.sip, aclEntry->key_mask + 8, 16); + ZXIC_COMM_MEMCPY(ipsec_enc_table->mask.dip, aclEntry->key_mask + 24, 16); + } + + if(aclEntry->p_as_rslt) + { + zxic_comm_swap(aclEntry->p_as_rslt, sizeof(ZXIC_UINT32)); + ZXIC_COMM_UINT32_GET_BITS(ipsec_enc_table->entry.hit_flag, *(ZXIC_UINT32 *)(aclEntry->p_as_rslt), 31, 1); + ZXIC_COMM_UINT32_GET_BITS(ipsec_enc_table->entry.rsv, *(ZXIC_UINT32 *)(aclEntry->p_as_rslt), 0, 31); + + zxic_comm_swap(aclEntry->p_as_rslt + 4, sizeof(ZXIC_UINT32)); + ZXIC_COMM_UINT32_GET_BITS(ipsec_enc_table->entry.sa_id, *(ZXIC_UINT32 *)(aclEntry->p_as_rslt + 4), 0, 32); + } + + return DPP_OK; +} + +DPP_ACL_INIT_T g_aclTable = { + .tbl_num = sizeof(g_aclSdtTable) / sizeof(DPP_APT_ACL_TABLE_T), + .acl = g_aclSdtTable, +}; diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/driver/source/dpp_drv_eram.c b/src/net/drivers/net/ethernet/dinghai/en_np/driver/source/dpp_drv_eram.c new file mode 100644 index 0000000..22eeb50 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/driver/source/dpp_drv_eram.c @@ -0,0 +1,675 @@ +#include "dpp_apt_se_api.h" +#include "dpp_se_api.h" +#include "dpp_drv_sdt.h" +#include "dpp_drv_eram.h" + +static DPP_APT_ERAM_TABLE_T g_eRamSdtTable[] = +{ + { + ZXDH_SDT_VXLAN_ATTR_TABLE, + { + DPP_SDT_TBLT_eRAM, /** <@brief 查找表项类型 */ + ERAM128_TBL_64b, /** <@brief eRam返回位宽 */ + ZXDH_VXLAN_ERAM_BAADDR, /** <@brief eRam表项基地址，128bit为单位 */ + ZXDH_VXLAN_ERAM_DEPTH, /** <@brief 表项深度，作为越界检查使用 */ + ZXDH_SDT_CLUTH_DISABLE /** <@brief 抓包使能 */ + }, + ERAM128_OPR_64b, /** 操作位宽 */ + RD_MODE_HOLD, /** 所有表项都为：RD_MODE_HOLD */ + dpp_apt_set_vxlan_data, + dpp_apt_get_vxlan_data + }, + { + ZXDH_SDT_VPORT_ATTR_TABLE, + { + DPP_SDT_TBLT_eRAM, + ERAM128_TBL_128b, + ZXDH_VPORT_ATTR_ERAM_BAADDR, + ZXDH_VPORT_ATTR_ERAM_DEPTH, + ZXDH_SDT_CLUTH_DISABLE + }, + ERAM128_OPR_128b, + RD_MODE_HOLD, + dpp_apt_set_vport_data, + dpp_apt_get_vport_data + }, + { + ZXDH_SDT_PANEL_PORT_ATTR_TABLE, + { + DPP_SDT_TBLT_eRAM, + ERAM128_TBL_128b, + ZXDH_PANEL_PORT_ATTR_ERAM_BAADDR, + ZXDH_PANEL_PORT_ATTR_ERAM_DEPTH, + ZXDH_SDT_CLUTH_DISABLE + }, + ERAM128_OPR_128b, + RD_MODE_HOLD, + dpp_apt_set_panel_port_data, + dpp_apt_get_panel_port_data + }, + { + ZXDH_SDT_RSS_TO_VQID_TABLE, + { + DPP_SDT_TBLT_eRAM, + ERAM128_TBL_128b, + ZXDH_RSS_TO_VQID_ERAM_BAADDR, + ZXDH_RSS_TO_VQID_ERAM_DEPTH, + ZXDH_SDT_CLUTH_DISABLE + }, + ERAM128_OPR_128b, + RD_MODE_HOLD, + dpp_apt_set_rss_to_vqid_data, + dpp_apt_get_rss_to_vqid_data + }, + { + ZXDH_SDT_VLAN_FILTER_TABLE, + { + DPP_SDT_TBLT_eRAM, + ERAM128_TBL_128b, + ZXDH_VLAN_FILTER_ERAM_BAADDR, + ZXDH_VLAN_FILTER_ERAM_DEPTH, + ZXDH_SDT_CLUTH_DISABLE + }, + ERAM128_OPR_128b, + RD_MODE_HOLD, + dpp_apt_set_vlan_filter_data, + dpp_apt_get_vlan_filter_data + }, + { + ZXDH_SDT_LAG_TABLE, + { + DPP_SDT_TBLT_eRAM, + ERAM128_TBL_64b, + ZXDH_LAG_ERAM_BAADDR, + ZXDH_LAG_ERAM_DEPTH, + ZXDH_SDT_CLUTH_DISABLE + }, + ERAM128_OPR_64b, + RD_MODE_HOLD, + dpp_apt_set_lag_data, + dpp_apt_get_lag_data + }, + { + ZXDH_SDT_BC_TABLE, + { + DPP_SDT_TBLT_eRAM, + ERAM128_TBL_128b, + ZXDH_BC_ERAM_BAADDR, + ZXDH_BC_ERAM_DEPTH, + ZXDH_SDT_CLUTH_DISABLE + }, + ERAM128_OPR_128b, + RD_MODE_HOLD, + dpp_apt_set_bc_data, + dpp_apt_get_bc_data + }, + { + ZXDH_SDT_DSCP_TO_UP_TABLE, + { + DPP_SDT_TBLT_eRAM, + ERAM128_TBL_64b, + ZXDH_DSCP_TO_UP_ERAM_BAADDR, + ZXDH_DSCP_TO_UP_ERAM_DEPTH, + ZXDH_SDT_CLUTH_DISABLE + }, + ERAM128_OPR_64b, + RD_MODE_HOLD, + dpp_apt_set_dscp_to_up_data, + dpp_apt_get_dscp_to_up_data + }, + { + ZXDH_SDT_UP_TO_TC_TABLE, + { + DPP_SDT_TBLT_eRAM, + ERAM128_TBL_64b, + ZXDH_UP_TO_TC_ERAM_BAADDR, + ZXDH_UP_TO_TC_ERAM_DEPTH, + ZXDH_SDT_CLUTH_DISABLE + }, + ERAM128_OPR_64b, + RD_MODE_HOLD, + dpp_apt_set_up_to_tc_data, + dpp_apt_get_up_to_tc_data + }, + { + ZXDH_SDT_VHCA_TABLE, + { + DPP_SDT_TBLT_eRAM, + ERAM128_TBL_64b, + ZXDH_VHCA_ERAM_BAADDR, + ZXDH_VHCA_ERAM_DEPTH, + ZXDH_SDT_CLUTH_DISABLE + }, + ERAM128_OPR_64b, + RD_MODE_HOLD, + dpp_apt_set_vhca_data, + dpp_apt_get_vhca_data + }, + { + ZXDH_SDT_UC_PROMISC_TABLE, + { + DPP_SDT_TBLT_eRAM, + ERAM128_TBL_128b, + ZXDH_UC_PROMISC_ERAM_BAADDR, + ZXDH_UC_PROMISC_ERAM_DEPTH, + ZXDH_SDT_CLUTH_DISABLE + }, + ERAM128_OPR_128b, + RD_MODE_HOLD, + dpp_apt_set_promisc_data, + dpp_apt_get_promisc_data + }, + { + ZXDH_SDT_MC_PROMISC_TABLE, + { + DPP_SDT_TBLT_eRAM, + ERAM128_TBL_128b, + ZXDH_MC_PROMISC_ERAM_BAADDR, + ZXDH_MC_PROMISC_ERAM_DEPTH, + ZXDH_SDT_CLUTH_DISABLE + }, + ERAM128_OPR_128b, + RD_MODE_HOLD, + dpp_apt_set_promisc_data, + dpp_apt_get_promisc_data + }, +}; + +DPP_ERAM_INIT_T g_eRamTable = { + .tbl_num = sizeof(g_eRamSdtTable) / sizeof(DPP_APT_ERAM_TABLE_T), + .eram = g_eRamSdtTable, +}; + +ZXIC_UINT32 dpp_apt_set_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4], ZXIC_UINT32 size) +{ + if (pData == NULL) + { + return DPP_ERR; + } + memcpy(buff, pData, size); + return DPP_OK; +} + +ZXIC_UINT32 dpp_apt_get_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4],ZXIC_UINT32 size) +{ + if (pData == NULL) + { + return DPP_ERR; + } + memcpy(pData, buff, size); + return DPP_OK; +} + +ZXIC_UINT32 dpp_apt_set_vxlan_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4]) +{ + return dpp_apt_set_data(pData, buff, sizeof(ZXDH_VXLAN_T)); +} + +ZXIC_UINT32 dpp_apt_get_vxlan_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4]) +{ + return dpp_apt_get_data(pData, buff, sizeof(ZXDH_VXLAN_T)); +} + +ZXIC_UINT32 dpp_apt_set_vport_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4]) +{ + ZXDH_VPORT_T *port_attr = (ZXDH_VPORT_T *)pData; + + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->hit_flag, 31, 1); + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->mtu_offload_enable, 30, 1); + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->rss_enable, 29, 1); + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->qinq_vlan_strip_offload, 28, 1); + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->vlan_strip_offload, 27, 1); + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->vlan_filter_enable, 26, 1); + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->rdma_offload_enable, 25, 1); + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->hw_bond_enable, 24, 1); + + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->allmulticast_enable, 23, 1); + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->is_up, 22, 1); + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->outer_ip_checksum_offload, 21, 1); + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->ip_checksum_offload, 20, 1); + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->tcp_udp_checksum_offload, 19, 1); + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->ip_fragment_offload, 18, 1); + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->lro_offload, 17, 1); + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->accelerator_offload_flag, 16, 1); + + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->virtio_enable, 15, 1); + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->virtion_version, 13, 2); + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->is_vf, 12, 1); + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->is_passthrough, 11, 1); + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->lag_enable, 10, 1); + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->ovs_enable, 9, 1); + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->inline_sec_offload, 8, 1); + + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->spoof_check_enable, 7, 1); + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->vepa_enable, 6, 1); + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->fd_enable, 5, 1); + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->egress_meter_mode, 4, 1); + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->ingress_meter_mode, 3, 1); + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->egress_meter_enable, 2, 1); + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->ingress_meter_enable, 1, 1); + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->tm_enable, 0, 1); + + ZXIC_COMM_UINT32_WRITE_BITS(buff[1], port_attr->rsv1, 31, 1); + ZXIC_COMM_UINT32_WRITE_BITS(buff[1], port_attr->hash_search_index, 28, 3); + ZXIC_COMM_UINT32_WRITE_BITS(buff[1], port_attr->port_base_qid, 16, 12); + + ZXIC_COMM_UINT32_WRITE_BITS(buff[1], port_attr->mtu, 0, 16); + + ZXIC_COMM_UINT32_WRITE_BITS(buff[2], port_attr->rsv3, 30, 2); + ZXIC_COMM_UINT32_WRITE_BITS(buff[2], port_attr->pf_vqm_vfid, 19, 11); + ZXIC_COMM_UINT32_WRITE_BITS(buff[2], port_attr->lag_id, 16, 3); + + ZXIC_COMM_UINT32_WRITE_BITS(buff[2], port_attr->panel_id, 12, 4); + ZXIC_COMM_UINT32_WRITE_BITS(buff[2], port_attr->hash_alg, 8, 4); + ZXIC_COMM_UINT32_WRITE_BITS(buff[2], port_attr->rss_hash_factor, 0, 8); + + ZXIC_COMM_UINT32_WRITE_BITS(buff[3], port_attr->uplink_port, 26, 6); + ZXIC_COMM_UINT32_WRITE_BITS(buff[3], port_attr->vhca, 16, 10); + ZXIC_COMM_UINT32_WRITE_BITS(buff[3], port_attr->tpid, 0, 16); + + + return DPP_OK; +} + +ZXIC_UINT32 dpp_apt_get_vport_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4]) +{ + ZXDH_VPORT_T *port_attr = (ZXDH_VPORT_T *)pData; + + ZXIC_COMM_UINT32_GET_BITS(port_attr->hit_flag, buff[0], 31, 1); + ZXIC_COMM_UINT32_GET_BITS(port_attr->mtu_offload_enable, buff[0], 30, 1); + ZXIC_COMM_UINT32_GET_BITS(port_attr->rss_enable, buff[0], 29, 1); + ZXIC_COMM_UINT32_GET_BITS(port_attr->qinq_vlan_strip_offload, buff[0], 28, 1); + ZXIC_COMM_UINT32_GET_BITS(port_attr->vlan_strip_offload, buff[0], 27, 1); + ZXIC_COMM_UINT32_GET_BITS(port_attr->vlan_filter_enable, buff[0], 26, 1); + ZXIC_COMM_UINT32_GET_BITS(port_attr->rdma_offload_enable, buff[0], 25, 1); + ZXIC_COMM_UINT32_GET_BITS(port_attr->hw_bond_enable, buff[0], 24, 1); + + ZXIC_COMM_UINT32_GET_BITS(port_attr->allmulticast_enable, buff[0], 23, 1); + ZXIC_COMM_UINT32_GET_BITS(port_attr->is_up, buff[0], 22, 1); + ZXIC_COMM_UINT32_GET_BITS(port_attr->outer_ip_checksum_offload, buff[0], 21, 1); + ZXIC_COMM_UINT32_GET_BITS(port_attr->ip_checksum_offload, buff[0], 20, 1); + ZXIC_COMM_UINT32_GET_BITS(port_attr->tcp_udp_checksum_offload, buff[0], 19, 1); + ZXIC_COMM_UINT32_GET_BITS(port_attr->ip_fragment_offload, buff[0], 18, 1); + ZXIC_COMM_UINT32_GET_BITS(port_attr->lro_offload, buff[0], 17, 1); + ZXIC_COMM_UINT32_GET_BITS(port_attr->accelerator_offload_flag, buff[0], 16, 1); + + ZXIC_COMM_UINT32_GET_BITS(port_attr->virtio_enable, buff[0], 15, 1); + ZXIC_COMM_UINT32_GET_BITS(port_attr->virtion_version, buff[0], 13, 2); + ZXIC_COMM_UINT32_GET_BITS(port_attr->is_vf, buff[0], 12, 1); + ZXIC_COMM_UINT32_GET_BITS(port_attr->is_passthrough, buff[0], 11, 1); + ZXIC_COMM_UINT32_GET_BITS(port_attr->lag_enable, buff[0], 10, 1); + ZXIC_COMM_UINT32_GET_BITS(port_attr->ovs_enable, buff[0], 9, 1); + ZXIC_COMM_UINT32_GET_BITS(port_attr->inline_sec_offload, buff[0], 8, 1); + + ZXIC_COMM_UINT32_GET_BITS(port_attr->spoof_check_enable, buff[0], 7, 1); + ZXIC_COMM_UINT32_GET_BITS(port_attr->vepa_enable, buff[0], 6, 1); + ZXIC_COMM_UINT32_GET_BITS(port_attr->fd_enable, buff[0], 5, 1); + ZXIC_COMM_UINT32_GET_BITS(port_attr->egress_meter_mode, buff[0], 4, 1); + ZXIC_COMM_UINT32_GET_BITS(port_attr->ingress_meter_mode, buff[0], 3, 1); + ZXIC_COMM_UINT32_GET_BITS(port_attr->egress_meter_enable, buff[0], 2, 1); + ZXIC_COMM_UINT32_GET_BITS(port_attr->ingress_meter_enable, buff[0], 1, 1); + ZXIC_COMM_UINT32_GET_BITS(port_attr->tm_enable, buff[0], 0, 1); + + ZXIC_COMM_UINT32_GET_BITS(port_attr->rsv1, buff[1], 31, 1); + ZXIC_COMM_UINT32_GET_BITS(port_attr->hash_search_index, buff[1], 28, 3); + ZXIC_COMM_UINT32_GET_BITS(port_attr->port_base_qid, buff[1], 16, 12); + + ZXIC_COMM_UINT32_GET_BITS(port_attr->mtu, buff[1], 0, 16); + + ZXIC_COMM_UINT32_GET_BITS(port_attr->rsv3, buff[2], 30, 2); + ZXIC_COMM_UINT32_GET_BITS(port_attr->pf_vqm_vfid, buff[2], 19, 11); + ZXIC_COMM_UINT32_GET_BITS(port_attr->lag_id, buff[2], 16, 3); + + ZXIC_COMM_UINT32_GET_BITS(port_attr->panel_id, buff[2], 12, 4); + ZXIC_COMM_UINT32_GET_BITS(port_attr->hash_alg, buff[2], 8, 4); + ZXIC_COMM_UINT32_GET_BITS(port_attr->rss_hash_factor, buff[2], 0, 8); + + ZXIC_COMM_UINT32_GET_BITS(port_attr->uplink_port, buff[3], 26, 6); + ZXIC_COMM_UINT32_GET_BITS(port_attr->vhca, buff[3], 16, 10); + ZXIC_COMM_UINT32_GET_BITS(port_attr->tpid, buff[3], 0, 16); + + return DPP_OK; + +} + +ZXIC_UINT32 dpp_apt_set_panel_port_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4]) +{ + ZXDH_PANEL_PORT_T* attr = (ZXDH_PANEL_PORT_T*)pData; + + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], attr->hit_flag, 31, 1); + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], attr->trust_mode, 30, 1); + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], attr->ptp_tc_enable, 28, 2); + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], attr->tm_shape_enable, 27, 1); + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], attr->pf_vqm_vfid, 16, 11); + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], attr->rsv2, 11, 5); + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], attr->ptp_port_vfid, 0, 11); + ZXIC_COMM_UINT32_WRITE_BITS(buff[1], attr->tm_base_queue, 20, 12); + ZXIC_COMM_UINT32_WRITE_BITS(buff[1], attr->rsv3, 17, 3); + ZXIC_COMM_UINT32_WRITE_BITS(buff[1], attr->mtu_offload_enable, 16, 1); + ZXIC_COMM_UINT32_WRITE_BITS(buff[1], attr->mtu, 0, 16); + + ZXIC_COMM_UINT32_WRITE_BITS(buff[2], attr->hw_bond_enable, 31, 1); + ZXIC_COMM_UINT32_WRITE_BITS(buff[2], attr->bond_link_up, 30, 1); + ZXIC_COMM_UINT32_WRITE_BITS(buff[2], attr->is_up, 29, 1); + ZXIC_COMM_UINT32_WRITE_BITS(buff[2], attr->rsv4, 27, 2); + ZXIC_COMM_UINT32_WRITE_BITS(buff[2], attr->bond_pf_vqm_vfid, 16, 11); + ZXIC_COMM_UINT32_WRITE_BITS(buff[2], attr->rsv5, 12, 4); + ZXIC_COMM_UINT32_WRITE_BITS(buff[2], attr->pf_memport_qid, 0, 12); + + ZXIC_COMM_UINT32_WRITE_BITS(buff[3], attr->rsv6, 27, 5); + ZXIC_COMM_UINT32_WRITE_BITS(buff[3], attr->ovs_pf_vfid, 16, 11); + ZXIC_COMM_UINT32_WRITE_BITS(buff[3], attr->rsv7, 0, 16); + + return DPP_OK; +} + +ZXIC_UINT32 dpp_apt_get_panel_port_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4]) +{ + ZXDH_PANEL_PORT_T* attr = (ZXDH_PANEL_PORT_T*)pData; + + ZXIC_COMM_UINT32_GET_BITS(attr->hit_flag, buff[0], 31, 1); + ZXIC_COMM_UINT32_GET_BITS(attr->trust_mode, buff[0], 30, 1); + ZXIC_COMM_UINT32_GET_BITS(attr->ptp_tc_enable, buff[0], 28, 2); + ZXIC_COMM_UINT32_GET_BITS(attr->tm_shape_enable, buff[0], 27, 1); + ZXIC_COMM_UINT32_GET_BITS(attr->pf_vqm_vfid, buff[0], 16, 11); + ZXIC_COMM_UINT32_GET_BITS(attr->rsv2, buff[0], 11, 5); + ZXIC_COMM_UINT32_GET_BITS(attr->ptp_port_vfid, buff[0], 0, 11); + ZXIC_COMM_UINT32_GET_BITS(attr->tm_base_queue, buff[1], 20, 12); + ZXIC_COMM_UINT32_GET_BITS(attr->rsv3, buff[1], 17, 3); + ZXIC_COMM_UINT32_GET_BITS(attr->mtu_offload_enable, buff[1], 16, 1); + ZXIC_COMM_UINT32_GET_BITS(attr->mtu, buff[1], 0, 16); + + ZXIC_COMM_UINT32_GET_BITS(attr->hw_bond_enable, buff[2], 31, 1); + ZXIC_COMM_UINT32_GET_BITS(attr->bond_link_up, buff[2], 30, 1); + ZXIC_COMM_UINT32_GET_BITS(attr->is_up, buff[2], 29, 1); + ZXIC_COMM_UINT32_GET_BITS(attr->rsv4, buff[2], 27, 2); + ZXIC_COMM_UINT32_GET_BITS(attr->bond_pf_vqm_vfid, buff[2], 16, 11); + ZXIC_COMM_UINT32_GET_BITS(attr->rsv5, buff[2], 12, 4); + ZXIC_COMM_UINT32_GET_BITS(attr->pf_memport_qid, buff[2], 0, 12); + + ZXIC_COMM_UINT32_GET_BITS(attr->rsv6, buff[3], 27, 5); + ZXIC_COMM_UINT32_GET_BITS(attr->ovs_pf_vfid, buff[3], 16, 11); + ZXIC_COMM_UINT32_GET_BITS(attr->rsv7, buff[3], 0, 16); + + return DPP_OK; +} + +ZXIC_UINT32 dpp_apt_set_dscp_to_up_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4]) +{ + ZXDH_DSCP_TO_UP_T* attr = (ZXDH_DSCP_TO_UP_T*)pData; + + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], attr->hit_flag, 31, 1); + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], attr->rsv1, 3, 28); + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], attr->up, 0, 3); + + ZXIC_COMM_UINT32_WRITE_BITS(buff[1], attr->rsv2, 0, 32); + + return DPP_OK; +} + +ZXIC_UINT32 dpp_apt_get_dscp_to_up_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4]) +{ + ZXDH_DSCP_TO_UP_T* attr = (ZXDH_DSCP_TO_UP_T*)pData; + + ZXIC_COMM_UINT32_GET_BITS(attr->hit_flag, buff[0], 31, 1); + ZXIC_COMM_UINT32_GET_BITS(attr->rsv1, buff[0], 3, 28); + ZXIC_COMM_UINT32_GET_BITS(attr->up, buff[0], 0, 3); + + ZXIC_COMM_UINT32_GET_BITS(attr->rsv2, buff[1], 0, 32); + + return DPP_OK; +} + +ZXIC_UINT32 dpp_apt_set_up_to_tc_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4]) +{ + ZXDH_UP_TO_TC_T* attr = (ZXDH_UP_TO_TC_T*)pData; + + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], attr->hit_flag, 31, 1); + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], attr->rsv1, 3, 28); + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], attr->tc, 0, 3); + + ZXIC_COMM_UINT32_WRITE_BITS(buff[1], attr->rsv2, 0, 32); + + return DPP_OK; +} + +ZXIC_UINT32 dpp_apt_get_up_to_tc_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4]) +{ + ZXDH_UP_TO_TC_T* attr = (ZXDH_UP_TO_TC_T*)pData; + + ZXIC_COMM_UINT32_GET_BITS(attr->hit_flag, buff[0], 31, 1); + ZXIC_COMM_UINT32_GET_BITS(attr->rsv1, buff[0], 3, 28); + ZXIC_COMM_UINT32_GET_BITS(attr->tc, buff[0], 0, 3); + + ZXIC_COMM_UINT32_GET_BITS(attr->rsv2, buff[1], 0, 32); + + return DPP_OK; +} + +ZXIC_UINT32 dpp_apt_set_rss_to_vqid_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4]) +{ + ZXDH_RSS_TO_VQID_T *attr = (ZXDH_RSS_TO_VQID_T*)pData; + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], attr->hit_flag, 31, 1); + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], attr->vqm_qid[0], 16, 15); + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], attr->vqm_qid[1], 0, 16); + + ZXIC_COMM_UINT32_WRITE_BITS(buff[1], attr->vqm_qid[2], 16, 16); + ZXIC_COMM_UINT32_WRITE_BITS(buff[1], attr->vqm_qid[3], 0, 16); + + ZXIC_COMM_UINT32_WRITE_BITS(buff[2], attr->vqm_qid[4], 16, 16); + ZXIC_COMM_UINT32_WRITE_BITS(buff[2], attr->vqm_qid[5], 0, 16); + + ZXIC_COMM_UINT32_WRITE_BITS(buff[3], attr->vqm_qid[6], 16, 16); + ZXIC_COMM_UINT32_WRITE_BITS(buff[3], attr->vqm_qid[7], 0, 16); + + return DPP_OK; +} + +ZXIC_UINT32 dpp_apt_get_rss_to_vqid_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4]) +{ + ZXDH_RSS_TO_VQID_T *attr = (ZXDH_RSS_TO_VQID_T*)pData; + + ZXIC_COMM_UINT32_GET_BITS(attr->hit_flag, buff[0], 31, 1); + ZXIC_COMM_UINT32_GET_BITS(attr->vqm_qid[0], buff[0], 16, 15); + ZXIC_COMM_UINT32_GET_BITS(attr->vqm_qid[1], buff[0], 0, 16); + + ZXIC_COMM_UINT32_GET_BITS(attr->vqm_qid[2], buff[1],16, 16); + ZXIC_COMM_UINT32_GET_BITS(attr->vqm_qid[3], buff[1], 0, 16); + + ZXIC_COMM_UINT32_GET_BITS(attr->vqm_qid[4], buff[2], 16, 16); + ZXIC_COMM_UINT32_GET_BITS(attr->vqm_qid[5], buff[2], 0, 16); + + ZXIC_COMM_UINT32_GET_BITS(attr->vqm_qid[6], buff[3], 16, 16); + ZXIC_COMM_UINT32_GET_BITS(attr->vqm_qid[7], buff[3], 0, 16); + + return DPP_OK; +} + +ZXIC_UINT32 dpp_apt_set_vlan_filter_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4]) +{ + ZXDH_VLAN_FILTER_T *vlan_filter_table = (ZXDH_VLAN_FILTER_T *)pData; + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], vlan_filter_table->hit_flag, 31, 1); + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], vlan_filter_table->rsv, 24, 7); + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], vlan_filter_table->vport_bitmap[0], 16, 8); + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], vlan_filter_table->vport_bitmap[1], 8, 8); + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], vlan_filter_table->vport_bitmap[2], 0, 8); + + ZXIC_COMM_UINT32_WRITE_BITS(buff[1], vlan_filter_table->vport_bitmap[3], 24, 8); + ZXIC_COMM_UINT32_WRITE_BITS(buff[1], vlan_filter_table->vport_bitmap[4], 16, 8); + ZXIC_COMM_UINT32_WRITE_BITS(buff[1], vlan_filter_table->vport_bitmap[5], 8, 8); + ZXIC_COMM_UINT32_WRITE_BITS(buff[1], vlan_filter_table->vport_bitmap[6], 0, 8); + + ZXIC_COMM_UINT32_WRITE_BITS(buff[2], vlan_filter_table->vport_bitmap[7], 24, 8); + ZXIC_COMM_UINT32_WRITE_BITS(buff[2], vlan_filter_table->vport_bitmap[8], 16, 8); + ZXIC_COMM_UINT32_WRITE_BITS(buff[2], vlan_filter_table->vport_bitmap[9], 8, 8); + ZXIC_COMM_UINT32_WRITE_BITS(buff[2], vlan_filter_table->vport_bitmap[10], 0, 8); + + ZXIC_COMM_UINT32_WRITE_BITS(buff[3], vlan_filter_table->vport_bitmap[11], 24, 8); + ZXIC_COMM_UINT32_WRITE_BITS(buff[3], vlan_filter_table->vport_bitmap[12], 16, 8); + ZXIC_COMM_UINT32_WRITE_BITS(buff[3], vlan_filter_table->vport_bitmap[13], 8, 8); + ZXIC_COMM_UINT32_WRITE_BITS(buff[3], vlan_filter_table->vport_bitmap[14], 0, 8); + return DPP_OK; +} + +ZXIC_UINT32 dpp_apt_get_vlan_filter_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4]) +{ + ZXDH_VLAN_FILTER_T *vlan_filter_table = (ZXDH_VLAN_FILTER_T *)pData; + ZXIC_COMM_UINT32_GET_BITS(vlan_filter_table->hit_flag, buff[0], 31, 1); + ZXIC_COMM_UINT32_GET_BITS(vlan_filter_table->rsv, buff[0], 24, 7); + ZXIC_COMM_UINT32_GET_BITS(vlan_filter_table->vport_bitmap[0], buff[0], 16, 8); + ZXIC_COMM_UINT32_GET_BITS(vlan_filter_table->vport_bitmap[1], buff[0], 8, 8); + ZXIC_COMM_UINT32_GET_BITS(vlan_filter_table->vport_bitmap[2], buff[0], 0, 8); + + ZXIC_COMM_UINT32_GET_BITS(vlan_filter_table->vport_bitmap[3], buff[1], 24, 8); + ZXIC_COMM_UINT32_GET_BITS(vlan_filter_table->vport_bitmap[4], buff[1], 16, 8); + ZXIC_COMM_UINT32_GET_BITS(vlan_filter_table->vport_bitmap[5], buff[1], 8, 8); + ZXIC_COMM_UINT32_GET_BITS(vlan_filter_table->vport_bitmap[6], buff[1], 0, 8); + + ZXIC_COMM_UINT32_GET_BITS(vlan_filter_table->vport_bitmap[7], buff[2], 24, 8); + ZXIC_COMM_UINT32_GET_BITS(vlan_filter_table->vport_bitmap[8], buff[2], 16, 8); + ZXIC_COMM_UINT32_GET_BITS(vlan_filter_table->vport_bitmap[9], buff[2], 8, 8); + ZXIC_COMM_UINT32_GET_BITS(vlan_filter_table->vport_bitmap[10], buff[2], 0, 8); + + ZXIC_COMM_UINT32_GET_BITS(vlan_filter_table->vport_bitmap[11], buff[3], 24, 8); + ZXIC_COMM_UINT32_GET_BITS(vlan_filter_table->vport_bitmap[12], buff[3], 16, 8); + ZXIC_COMM_UINT32_GET_BITS(vlan_filter_table->vport_bitmap[13], buff[3], 8, 8); + ZXIC_COMM_UINT32_GET_BITS(vlan_filter_table->vport_bitmap[14], buff[3], 0, 8); + return DPP_OK; +} + +ZXIC_UINT32 dpp_apt_set_lag_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4]) +{ + ZXDH_LAG_T *lag_entry = (ZXDH_LAG_T *)pData; + + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], lag_entry->hit_flag, 31, 1); + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], lag_entry->rsv1, 27, 4); + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], lag_entry->member_num, 24, 3); + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], lag_entry->bond_mode, 16, 8); + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], lag_entry->hash_factor, 8, 8); + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], lag_entry->rsv2, 0, 8); + + ZXIC_COMM_UINT32_WRITE_BITS(buff[1], lag_entry->rsv2, 16, 16); + ZXIC_COMM_UINT32_WRITE_BITS(buff[1], lag_entry->member_bitmap, 0, 16); + + return DPP_OK; +} + +ZXIC_UINT32 dpp_apt_get_lag_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4]) +{ + ZXDH_LAG_T *lag_entry = (ZXDH_LAG_T *)pData; + + ZXIC_COMM_UINT32_GET_BITS(lag_entry->hit_flag, buff[0], 31, 1); + ZXIC_COMM_UINT32_GET_BITS(lag_entry->rsv1, buff[0], 27, 4); + ZXIC_COMM_UINT32_GET_BITS(lag_entry->member_num, buff[0], 24, 3); + ZXIC_COMM_UINT32_GET_BITS(lag_entry->bond_mode, buff[0], 16, 8); + ZXIC_COMM_UINT32_GET_BITS(lag_entry->hash_factor, buff[0], 8, 8); + ZXIC_COMM_UINT32_GET_BITS(lag_entry->rsv2, buff[0], 0, 8); + + ZXIC_COMM_UINT32_GET_BITS(lag_entry->rsv2, buff[1], 16, 16); + ZXIC_COMM_UINT32_GET_BITS(lag_entry->member_bitmap, buff[1], 0, 16); + + return DPP_OK; +} + +ZXIC_UINT32 dpp_apt_set_bc_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4]) +{ + ZXIC_UINT32 bc_bitmap = 0; + ZXDH_BC_T *bc_entry = (ZXDH_BC_T *)pData; + + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], bc_entry->hit_flag, 31, 1); + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], bc_entry->rsv1, 0, 31); + + ZXIC_COMM_UINT32_WRITE_BITS(buff[1], bc_entry->rsv2, 0, 32); + + bc_bitmap = bc_entry->bc_bitmap >> 32; + ZXIC_COMM_UINT32_WRITE_BITS(buff[2], bc_bitmap, 0, 32); + + bc_bitmap = bc_entry->bc_bitmap; + ZXIC_COMM_UINT32_WRITE_BITS(buff[3], bc_bitmap, 0, 32); + + return DPP_OK; +} + +ZXIC_UINT32 dpp_apt_get_bc_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4]) +{ + ZXIC_UINT32 bc_bitmap = 0; + ZXDH_BC_T *bc_entry = (ZXDH_BC_T *)pData; + + ZXIC_COMM_UINT32_GET_BITS(bc_entry->hit_flag, buff[0], 31, 1); + ZXIC_COMM_UINT32_GET_BITS(bc_entry->rsv1, buff[0], 0, 31); + + ZXIC_COMM_UINT32_GET_BITS(bc_entry->rsv2, buff[1], 0, 32); + + ZXIC_COMM_UINT32_GET_BITS(bc_bitmap, buff[2], 0, 32); + bc_entry->bc_bitmap = (((ZXIC_UINT64)bc_bitmap) << 32); + + ZXIC_COMM_UINT32_GET_BITS(bc_bitmap, buff[3], 0, 32); + bc_entry->bc_bitmap |= bc_bitmap; + + return DPP_OK; +} + +ZXIC_UINT32 dpp_apt_set_promisc_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4]) +{ + ZXIC_UINT32 bitmap = 0; + ZXDH_PROMISC_T *promisc_entry = (ZXDH_PROMISC_T *)pData; + + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], promisc_entry->hit_flag, 31, 1); + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], promisc_entry->pf_enable, 30, 1); + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], promisc_entry->rsv1, 0, 30); + + ZXIC_COMM_UINT32_WRITE_BITS(buff[1], promisc_entry->rsv2, 0, 32); + + bitmap = promisc_entry->bitmap >> 32; + ZXIC_COMM_UINT32_WRITE_BITS(buff[2], bitmap, 0, 32); + + bitmap = promisc_entry->bitmap; + ZXIC_COMM_UINT32_WRITE_BITS(buff[3], bitmap, 0, 32); + + return DPP_OK; +} + +ZXIC_UINT32 dpp_apt_get_promisc_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4]) +{ + ZXIC_UINT32 bitmap = 0; + ZXDH_PROMISC_T *promisc_entry = (ZXDH_PROMISC_T *)pData; + + ZXIC_COMM_UINT32_GET_BITS(promisc_entry->hit_flag, buff[0], 31, 1); + ZXIC_COMM_UINT32_GET_BITS(promisc_entry->pf_enable, buff[0], 30, 1); + ZXIC_COMM_UINT32_GET_BITS(promisc_entry->rsv1, buff[0], 0, 30); + + ZXIC_COMM_UINT32_GET_BITS(promisc_entry->rsv2, buff[1], 0, 32); + + ZXIC_COMM_UINT32_GET_BITS(bitmap, buff[2], 0, 32); + promisc_entry->bitmap = (((ZXIC_UINT64)bitmap) << 32); + + ZXIC_COMM_UINT32_GET_BITS(bitmap, buff[3], 0, 32); + promisc_entry->bitmap |= bitmap; + + return DPP_OK; +} + +ZXIC_UINT32 dpp_apt_set_vhca_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4]) +{ + ZXDH_VHCA_T *vhca_entry = (ZXDH_VHCA_T *)pData; + + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], vhca_entry->valid, 31, 1); + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], vhca_entry->rsv1, 11, 20); + ZXIC_COMM_UINT32_WRITE_BITS(buff[0], vhca_entry->vqm_vfid, 0, 11); + + ZXIC_COMM_UINT32_WRITE_BITS(buff[1], vhca_entry->rsv2, 0, 32); + return DPP_OK; +} + +ZXIC_UINT32 dpp_apt_get_vhca_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4]) +{ + ZXDH_VHCA_T *vhca_entry = (ZXDH_VHCA_T *)pData; + + ZXIC_COMM_UINT32_GET_BITS(vhca_entry->valid, buff[0], 31, 1); + ZXIC_COMM_UINT32_GET_BITS(vhca_entry->rsv1, buff[0], 11, 20); + ZXIC_COMM_UINT32_GET_BITS(vhca_entry->vqm_vfid, buff[0], 0, 11); + + ZXIC_COMM_UINT32_GET_BITS(vhca_entry->rsv2, buff[1], 0, 32); + + return DPP_OK; +} \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/driver/source/dpp_drv_hash.c b/src/net/drivers/net/ethernet/dinghai/en_np/driver/source/dpp_drv_hash.c new file mode 100644 index 0000000..84d7319 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/driver/source/dpp_drv_hash.c @@ -0,0 +1,588 @@ +#include "dpp_apt_se_api.h" +#include "dpp_se_api.h" +#include "dpp_apt_se.h" +#include "dpp_sdt.h" +#include "dpp_hash.h" +#include "dpp_dtb_table.h" +#include "dpp_drv_sdt.h" +#include "dpp_drv_hash.h" +#include "dpp_kernel_init.h" + +static DPP_APT_HASH_TABLE_T g_hashSdtTable[] = +{ + { + ZXDH_SDT_L2_ENTRY_TABLE_PHYPORT0, + { + DPP_SDT_TBLT_HASH, + ZXDH_HASH_FUNC0, + HASH_KEY_128b, + 8, // rsv(16) + mac(48) + 0, + 0, + 0, + ZXDH_L2ENTRY_KEEPALIVE_ERAM_BAADDR, + DPP_SDT_RSP_32b, // hit-flag(1) + rsv(20) + VQM_VFID(11) + ZXDH_SDT_CLUTH_DISABLE + }, + 0, + dpp_apt_set_l2entry_data, + dpp_apt_get_l2entry_data + }, + { + ZXDH_SDT_L2_ENTRY_TABLE_PHYPORT1, + { + DPP_SDT_TBLT_HASH, + ZXDH_HASH_FUNC0, + HASH_KEY_128b, + 8, // rsv(16) + mac(48) + 1, + 0, + 0, + ZXDH_L2ENTRY_KEEPALIVE_ERAM_BAADDR, + DPP_SDT_RSP_32b, // hit-flag(1) + rsv(20) + VQM_VFID(11) + ZXDH_SDT_CLUTH_DISABLE + }, + 0, + dpp_apt_set_l2entry_data, + dpp_apt_get_l2entry_data + }, + { + ZXDH_SDT_L2_ENTRY_TABLE_PHYPORT2, + { + DPP_SDT_TBLT_HASH, + ZXDH_HASH_FUNC0, + HASH_KEY_128b, + 8, // rsv(16) + mac(48) + 2, + 0, + 0, + ZXDH_L2ENTRY_KEEPALIVE_ERAM_BAADDR, + DPP_SDT_RSP_32b, // hit-flag(1) + rsv(20) + VQM_VFID(11) + ZXDH_SDT_CLUTH_DISABLE + }, + 0, + dpp_apt_set_l2entry_data, + dpp_apt_get_l2entry_data + }, + { + ZXDH_SDT_L2_ENTRY_TABLE_PHYPORT3, + { + DPP_SDT_TBLT_HASH, + ZXDH_HASH_FUNC0, + HASH_KEY_128b, + 8, // rsv(16) + mac(48) + 3, + 0, + 0, + ZXDH_L2ENTRY_KEEPALIVE_ERAM_BAADDR, + DPP_SDT_RSP_32b, // hit-flag(1) + rsv(20) + VQM_VFID(11) + ZXDH_SDT_CLUTH_DISABLE + }, + 0, + dpp_apt_set_l2entry_data, + dpp_apt_get_l2entry_data + }, + { + ZXDH_SDT_L2_ENTRY_TABLE_PHYPORT4, + { + DPP_SDT_TBLT_HASH, + ZXDH_HASH_FUNC0, + HASH_KEY_128b, + 8, // rsv(16) + mac(48) + 4, + 0, + 0, + ZXDH_L2ENTRY_KEEPALIVE_ERAM_BAADDR, + DPP_SDT_RSP_32b, // hit-flag(1) + rsv(20) + VQM_VFID(11) + ZXDH_SDT_CLUTH_DISABLE + }, + 0, + dpp_apt_set_l2entry_data, + dpp_apt_get_l2entry_data + }, + { + ZXDH_SDT_L2_ENTRY_TABLE_PHYPORT5, + { + DPP_SDT_TBLT_HASH, + ZXDH_HASH_FUNC0, + HASH_KEY_128b, + 8, // rsv(16) + mac(48) + 5, + 0, + 0, + ZXDH_L2ENTRY_KEEPALIVE_ERAM_BAADDR, + DPP_SDT_RSP_32b, // hit-flag(1) + rsv(20) + VQM_VFID(11) + ZXDH_SDT_CLUTH_DISABLE + }, + 0, + dpp_apt_set_l2entry_data, + dpp_apt_get_l2entry_data + }, + { + ZXDH_SDT_MC_TABLE_PHYPORT0, + { + DPP_SDT_TBLT_HASH, + ZXDH_HASH_FUNC0, + HASH_KEY_256b, + 8, // rsv(14) + vf_group_id(2) + MC_MAC(48) + 12, + 0, + 0, + 0, + DPP_SDT_RSP_128b, // hit_flag(1) + rsv(63) + MC_BITMAP(64) + ZXDH_SDT_CLUTH_DISABLE + }, + 0, + dpp_apt_set_mc_data, + dpp_apt_get_mc_data + }, + { + ZXDH_SDT_MC_TABLE_PHYPORT1, + { + DPP_SDT_TBLT_HASH, + ZXDH_HASH_FUNC0, + HASH_KEY_256b, + 8, // rsv(14) + vf_group_id(2) + MC_MAC(48) + 13, + 0, + 0, + 0, + DPP_SDT_RSP_128b, // hit_flag(1) + rsv(63) + MC_BITMAP(64) + ZXDH_SDT_CLUTH_DISABLE + }, + 0, + dpp_apt_set_mc_data, + dpp_apt_get_mc_data + }, + { + ZXDH_SDT_MC_TABLE_PHYPORT2, + { + DPP_SDT_TBLT_HASH, + ZXDH_HASH_FUNC0, + HASH_KEY_256b, + 8, // rsv(14) + vf_group_id(2) + MC_MAC(48) + 14, + 0, + 0, + 0, + DPP_SDT_RSP_128b, // hit_flag(1) + rsv(63) + MC_BITMAP(64) + ZXDH_SDT_CLUTH_DISABLE + }, + 0, + dpp_apt_set_mc_data, + dpp_apt_get_mc_data + }, + { + ZXDH_SDT_MC_TABLE_PHYPORT3, + { + DPP_SDT_TBLT_HASH, + ZXDH_HASH_FUNC0, + HASH_KEY_256b, + 8, // rsv(14) + vf_group_id(2) + MC_MAC(48) + 15, + 0, + 0, + 0, + DPP_SDT_RSP_128b, // hit_flag(1) + rsv(63) + MC_BITMAP(64) + ZXDH_SDT_CLUTH_DISABLE + }, + 0, + dpp_apt_set_mc_data, + dpp_apt_get_mc_data + }, + { + ZXDH_SDT_MC_TABLE_PHYPORT4, + { + DPP_SDT_TBLT_HASH, + ZXDH_HASH_FUNC0, + HASH_KEY_256b, + 8, // rsv(14) + vf_group_id(2) + MC_MAC(48) + 16, + 0, + 0, + 0, + DPP_SDT_RSP_128b, // hit_flag(1) + rsv(63) + MC_BITMAP(64) + ZXDH_SDT_CLUTH_DISABLE + }, + 0, + dpp_apt_set_mc_data, + dpp_apt_get_mc_data + }, + { + ZXDH_SDT_MC_TABLE_PHYPORT5, + { + DPP_SDT_TBLT_HASH, + ZXDH_HASH_FUNC0, + HASH_KEY_256b, + 8, // rsv(14) + vf_group_id(2) + MC_MAC(48) + 17, + 0, + 0, + 0, + DPP_SDT_RSP_128b, // hit_flag(1) + rsv(63) + MC_BITMAP(64) + ZXDH_SDT_CLUTH_DISABLE + }, + 0, + dpp_apt_set_mc_data, + dpp_apt_get_mc_data + } +}; + +DPP_APT_HASH_FUNC_RES_T func_res[] = { + /*func_id | zblk_num | zblk_bitmap | ddr_dis*/ + {0, 10, 0x000003FF, 1}, /*混合，zblock0~zblock9*/ +}; + +DPP_APT_HASH_BULK_RES_T bulk_res[] = { + /*funcid, bulkid, zcell_num, zreg_num, ddr_baddr, ddr_item_num, ddr_width_mode, ddr_crc_sel, ddr_ecc_en*/ + {0, 0, 19, 19, 0, 0, DDR_WIDTH_512b, 0, 0}, + {0, 1, 10, 10, 0, 0, DDR_WIDTH_512b, 0, 0}, + {0, 2, 0, 0, 0, 0, DDR_WIDTH_512b, 0, 0}, + {0, 3, 2, 2, 0, 0, DDR_WIDTH_512b, 0, 0}, + {0, 4, 2, 2, 0, 0, DDR_WIDTH_512b, 0, 0}, + {0, 5, 3, 3, 0, 0, DDR_WIDTH_512b, 0, 0}, + {0, 6, 2, 2, 0, 0, DDR_WIDTH_512b, 0, 0}, + {0, 7, 2, 2, 0, 0, DDR_WIDTH_512b, 0, 0}, +}; + +DPP_HASH_INIT_T g_hashTable = { + .func_num = sizeof(func_res) / sizeof(DPP_APT_HASH_FUNC_RES_T), + .func = func_res, + .bulk_num = sizeof(bulk_res) / sizeof(DPP_APT_HASH_BULK_RES_T), + .bulk = bulk_res, + .ser_num = sizeof(g_hashSdtTable) / sizeof(DPP_APT_HASH_TABLE_T), + .ser = g_hashSdtTable, +}; + +ZXIC_UINT32 dpp_apt_set_l2entry_data(ZXIC_VOID *pData, DPP_HASH_ENTRY *pEntry) +{ + ZXIC_UINT32 key = 0; + ZXIC_UINT32 rst = 0; + ZXDH_L2_ENTRY_T *pL2Entry = NULL; + + ZXIC_COMM_CHECK_POINT(pData); + ZXIC_COMM_CHECK_POINT(pEntry); + ZXIC_COMM_CHECK_POINT(pEntry->p_key); + ZXIC_COMM_CHECK_POINT(pEntry->p_rst); + + pL2Entry = (ZXDH_L2_ENTRY_T *)pData; + ZXIC_COMM_UINT32_WRITE_BITS(key, pL2Entry->key.rsv, 16, 16); + + zxic_comm_swap((ZXIC_UINT8 *)&key,sizeof(ZXIC_UINT32)); + ZXIC_COMM_MEMCPY(pEntry->p_key+1,&key,sizeof(ZXIC_UINT32)); + + ZXIC_COMM_MEMCPY(pEntry->p_key + 3, pL2Entry->key.dmac_addr, 6); + + ZXIC_COMM_UINT32_WRITE_BITS(rst, pL2Entry->entry.hit_flag, 31, 1); + ZXIC_COMM_UINT32_WRITE_BITS(rst, pL2Entry->entry.rsv, 11, 20); + ZXIC_COMM_UINT32_WRITE_BITS(rst, pL2Entry->entry.vqm_vfid, 0, 11); + + zxic_comm_swap((ZXIC_UINT8 *)&rst,sizeof(ZXIC_UINT32)); + ZXIC_COMM_MEMCPY(pEntry->p_rst,&rst,sizeof(ZXIC_UINT32)); + + return DPP_OK; +} + +ZXIC_UINT32 dpp_apt_get_l2entry_data(ZXIC_VOID *pData, DPP_HASH_ENTRY *pEntry) +{ + ZXDH_L2_ENTRY_T *pL2Entry = NULL; + + ZXIC_UINT32 key = 0; + + ZXIC_COMM_CHECK_POINT(pData); + ZXIC_COMM_CHECK_POINT(pEntry); + ZXIC_COMM_CHECK_POINT(pEntry->p_rst); + + pL2Entry = (ZXDH_L2_ENTRY_T *)pData; + + key = *(ZXIC_UINT32 *)(pEntry->p_key + 1); + zxic_comm_swap((ZXIC_UINT8 *)&key,sizeof(ZXIC_UINT32)); + ZXIC_COMM_UINT32_GET_BITS(pL2Entry->key.rsv, key, 16, 16); + + ZXIC_COMM_MEMCPY(pL2Entry->key.dmac_addr, pEntry->p_key + 3, 6); + + zxic_comm_swap(pEntry->p_rst, sizeof(ZXIC_UINT32)); + ZXIC_COMM_UINT32_GET_BITS(pL2Entry->entry.hit_flag, *(ZXIC_UINT32 *)pEntry->p_rst, 31, 1); + ZXIC_COMM_UINT32_GET_BITS(pL2Entry->entry.rsv, *(ZXIC_UINT32 *)pEntry->p_rst, 11, 20); + ZXIC_COMM_UINT32_GET_BITS(pL2Entry->entry.vqm_vfid, *(ZXIC_UINT32 *)pEntry->p_rst, 0, 11); + + return DPP_OK; +} + +ZXIC_UINT32 dpp_apt_set_mc_data(ZXIC_VOID *pData, DPP_HASH_ENTRY *pEntry) +{ + ZXIC_UINT32 key = 0; + ZXIC_UINT32 rst = 0; + + ZXDH_MC_T *mc_table = NULL; + + ZXIC_COMM_CHECK_POINT(pData); + ZXIC_COMM_CHECK_POINT(pEntry); + ZXIC_COMM_CHECK_POINT(pEntry->p_key); + ZXIC_COMM_CHECK_POINT(pEntry->p_rst); + + mc_table = (ZXDH_MC_T *)pData; + + ZXIC_COMM_UINT32_WRITE_BITS(key, mc_table->key.rsv, 18, 14); + ZXIC_COMM_UINT32_WRITE_BITS(key, mc_table->key.group_id, 16, 2); + + zxic_comm_swap((ZXIC_UINT8 *)&key, sizeof(ZXIC_UINT32)); + ZXIC_COMM_MEMCPY(pEntry->p_key + 1, &key, sizeof(ZXIC_UINT32)); + + ZXIC_COMM_MEMCPY(pEntry->p_key + 3, mc_table->key.mc_mac, 6); + + ZXIC_COMM_UINT32_WRITE_BITS(rst, mc_table->entry.hit_flag, 31, 1); + ZXIC_COMM_UINT32_WRITE_BITS(rst, mc_table->entry.mc_pf_enable, 30, 1); + ZXIC_COMM_UINT32_WRITE_BITS(rst, mc_table->entry.rsv1, 0, 30); + zxic_comm_swap((ZXIC_UINT8 *)&rst, sizeof(ZXIC_UINT32)); + ZXIC_COMM_MEMCPY(pEntry->p_rst, &rst, sizeof(ZXIC_UINT32)); + + ZXIC_COMM_UINT32_WRITE_BITS(rst, mc_table->entry.rsv2, 0, 32); + zxic_comm_swap((ZXIC_UINT8 *)&rst, sizeof(ZXIC_UINT32)); + ZXIC_COMM_MEMCPY(pEntry->p_rst + 4, &rst, sizeof(ZXIC_UINT32)); + + rst = mc_table->entry.mc_bitmap >> 32; + zxic_comm_swap((ZXIC_UINT8 *)&rst, sizeof(ZXIC_UINT32)); + ZXIC_COMM_MEMCPY(pEntry->p_rst + 8, &rst, sizeof(ZXIC_UINT32)); + + rst = mc_table->entry.mc_bitmap; + zxic_comm_swap((ZXIC_UINT8 *)&rst, sizeof(ZXIC_UINT32)); + ZXIC_COMM_MEMCPY(pEntry->p_rst + 12, &rst, sizeof(ZXIC_UINT32)); + + return DPP_OK; +} + +ZXIC_UINT32 dpp_apt_get_mc_data(ZXIC_VOID *pData, DPP_HASH_ENTRY *pEntry) +{ + ZXIC_UINT32 key = 0; + ZXIC_UINT32 rst = 0; + + ZXDH_MC_T *mc_table = NULL; + + ZXIC_COMM_CHECK_POINT(pData); + ZXIC_COMM_CHECK_POINT(pEntry); + ZXIC_COMM_CHECK_POINT(pEntry->p_key); + ZXIC_COMM_CHECK_POINT(pEntry->p_rst); + + mc_table = (ZXDH_MC_T *)pData; + + key = *(ZXIC_UINT32 *)(pEntry->p_key + 1); + zxic_comm_swap((ZXIC_UINT8 *)&key, sizeof(ZXIC_UINT32)); + ZXIC_COMM_UINT32_GET_BITS(mc_table->key.rsv, key, 18, 14); + ZXIC_COMM_UINT32_GET_BITS(mc_table->key.group_id, key, 16, 2); + + ZXIC_COMM_MEMCPY(mc_table->key.mc_mac, pEntry->p_key + 3, 6); + + zxic_comm_swap(pEntry->p_rst, sizeof(ZXIC_UINT32)); + ZXIC_COMM_UINT32_GET_BITS(mc_table->entry.hit_flag, *(ZXIC_UINT32 *)pEntry->p_rst, 31, 1); + ZXIC_COMM_UINT32_GET_BITS(mc_table->entry.mc_pf_enable, *(ZXIC_UINT32 *)pEntry->p_rst, 30, 1); + ZXIC_COMM_UINT32_GET_BITS(mc_table->entry.rsv1, *(ZXIC_UINT32 *)pEntry->p_rst, 0, 30); + + zxic_comm_swap(pEntry->p_rst + 4, sizeof(ZXIC_UINT32)); + ZXIC_COMM_UINT32_GET_BITS(mc_table->entry.rsv2, *(ZXIC_UINT32 *)(pEntry->p_rst + 4), 0, 32); + + zxic_comm_swap(pEntry->p_rst + 8, sizeof(ZXIC_UINT32)); + ZXIC_COMM_UINT32_GET_BITS(rst, *(ZXIC_UINT32 *)(pEntry->p_rst + 8), 0, 32); + mc_table->entry.mc_bitmap = (((ZXIC_UINT64)rst) << 32); + + zxic_comm_swap(pEntry->p_rst + 12, sizeof(ZXIC_UINT32)); + ZXIC_COMM_UINT32_GET_BITS(rst, *(ZXIC_UINT32 *)(pEntry->p_rst + 12), 24, 8); + mc_table->entry.mc_bitmap |= rst; + + return DPP_OK; +} + +DPP_STATUS dpp_apt_dtb_hash_table_unicast_mac_dump(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 sdt_no, + ZXDH_L2_ENTRY_T *pHashDataArr, + ZXIC_UINT32 *p_entry_num) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 max_item_num = DTB_DUMP_UNICAST_MAC_DUMP_NUM; + ZXIC_UINT32 index = 0; + ZXIC_UINT32 entryNum = 0; + ZXIC_UINT8* pDumpData = NULL; + ZXIC_UINT8 *pKey = NULL; + ZXIC_UINT8 *pRst = NULL; + + ZXIC_UINT32 dma_size = 0; + ZXIC_UINT64 dma_phy_addr = 0; + ZXIC_UINT64 dma_vir_addr = 0; + + DPP_HASH_ENTRY *p_dump_hash_entry = NULL; + DPP_HASH_ENTRY *p_temp_entry = NULL; + DPP_SDTTBL_HASH_T sdt_hash_info = {0}; /*SDT内容*/ + SE_APT_CALLBACK_T *pAptCallback = NULL; + ZXDH_L2_ENTRY_T *p_l2_mac_entry = NULL; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_POINT(pHashDataArr); + ZXIC_COMM_CHECK_POINT(p_entry_num); + + //从sdt_no中获取SDT配置 + rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_hash_info); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_soft_sdt_tbl_get"); + + pAptCallback = dpp_apt_get_func(DEV_ID(dev), sdt_no); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), pAptCallback); + + //分配空间 + pDumpData = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(max_item_num * sizeof(DPP_HASH_ENTRY)); + ZXIC_COMM_CHECK_POINT_NO_ASSERT(pDumpData); + pKey = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(max_item_num * HASH_KEY_MAX); + ZXIC_COMM_CHECK_POINT_MEMORY_FREE_NO_ASSERT(pKey, pDumpData); + pRst = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(max_item_num * HASH_RST_MAX); + ZXIC_COMM_CHECK_POINT_MEMORY_FREE2PTR_NO_ASSERT(pRst, pKey, pDumpData); + + ZXIC_COMM_MEMSET(pDumpData, 0x0, max_item_num * sizeof(DPP_HASH_ENTRY)); + ZXIC_COMM_MEMSET(pKey, 0x0, max_item_num * HASH_KEY_MAX); + ZXIC_COMM_MEMSET(pRst, 0x0, max_item_num * HASH_RST_MAX); + + p_dump_hash_entry = (DPP_HASH_ENTRY *)pDumpData; + for(index = 0; index < max_item_num; index++) + { + p_temp_entry = p_dump_hash_entry + index; + p_temp_entry->p_key = pKey + index * HASH_KEY_MAX; + p_temp_entry->p_rst = pRst + index * HASH_RST_MAX; + } + + rc = dtb_sdt_dump_dma_alloc(dev, DTB_SDT_DUMP_SIZE, &dma_phy_addr, &dma_vir_addr); + ZXIC_COMM_CHECK_RC_MEMORY_FREE3PTR_NO_ASSERT(rc, "dtb_sdt_dump_dma_alloc", pRst, pKey, pDumpData); + + rc = dpp_dtb_dump_sdt_addr_set(dev, queue_id, sdt_no, dma_phy_addr, dma_vir_addr, DTB_SDT_DUMP_SIZE); + ZXIC_COMM_CHECK_RC_MEMORY_FREE3PTR_NO_ASSERT(rc, "dpp_dtb_dump_sdt_addr_set", pRst, pKey, pDumpData); + + rc = dpp_dtb_hash_table_only_zcam_dump(dev, queue_id, sdt_no, pDumpData, &entryNum); + + dpp_dtb_dump_sdt_addr_get(dev, queue_id, sdt_no, &dma_phy_addr, &dma_vir_addr, &dma_size); + dtb_sdt_dump_dma_release(dev, dma_size, dma_phy_addr, dma_vir_addr); + dpp_dtb_dump_sdt_addr_clear(dev, queue_id, sdt_no); + + if(rc != DPP_OK) + { + ZXIC_COMM_FREE(pKey); + ZXIC_COMM_FREE(pRst); + ZXIC_COMM_FREE(pDumpData); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_hash_table_only_zcam_dump"); + } + + ZXIC_COMM_TRACE_INFO("dpp_dtb_hash_table_only_zcam_dump unicast entry_num: %d\n", entryNum); + + for(index = 0; index < entryNum; index++) + { + p_temp_entry = p_dump_hash_entry + index; + p_l2_mac_entry = pHashDataArr + index; + // //打印数据 + dpp_dtb_data_print(p_temp_entry->p_key, DPP_GET_ACTU_KEY_BY_SIZE(sdt_hash_info.key_size) + 1); + dpp_dtb_data_print(p_temp_entry->p_rst, 4 * (0x1 << sdt_hash_info.rsp_mode)); + + rc = pAptCallback->se_func_info.hashFunc.hash_get_func(p_l2_mac_entry, p_temp_entry); + ZXIC_COMM_CHECK_DEV_RC_MEMORY_FREE3PTR_NO_ASSERT(DEV_ID(dev), rc, "hash_set_func", pRst, pKey, pDumpData); + } + + *p_entry_num = entryNum; + + ZXIC_COMM_FREE(pKey); + ZXIC_COMM_FREE(pRst); + ZXIC_COMM_FREE(pDumpData); + + return DPP_OK; +} + +DPP_STATUS dpp_apt_dtb_hash_table_multicast_mac_dump(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 sdt_no, + ZXDH_MC_T *pHashDataArr, + ZXIC_UINT32 *p_entry_num) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 max_item_num = DTB_DUMP_MULTICAST_MAC_DUMP_NUM; + ZXIC_UINT32 index = 0; + ZXIC_UINT32 entryNum = 0; + ZXIC_UINT8* pDumpData = NULL; + ZXIC_UINT8 *pKey = NULL; + ZXIC_UINT8 *pRst = NULL; + + ZXIC_UINT32 dma_size = 0; + ZXIC_UINT64 dma_phy_addr = 0; + ZXIC_UINT64 dma_vir_addr = 0; + + DPP_HASH_ENTRY *p_dump_hash_entry = NULL; + DPP_HASH_ENTRY *p_temp_entry = NULL; + DPP_SDTTBL_HASH_T sdt_hash_info = {0}; /*SDT内容*/ + SE_APT_CALLBACK_T *pAptCallback = NULL; + ZXDH_MC_T *p_multicast_mac_data = NULL; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_POINT(pHashDataArr); + ZXIC_COMM_CHECK_POINT(p_entry_num); + + //从sdt_no中获取SDT配置 + rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_hash_info); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_soft_sdt_tbl_get"); + + pAptCallback = dpp_apt_get_func(DEV_ID(dev), sdt_no); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), pAptCallback); + + //分配空间 + pDumpData = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(max_item_num * sizeof(DPP_HASH_ENTRY)); + ZXIC_COMM_CHECK_POINT_NO_ASSERT(pDumpData); + pKey = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(max_item_num * HASH_KEY_MAX); + ZXIC_COMM_CHECK_POINT_MEMORY_FREE_NO_ASSERT(pKey, pDumpData); + pRst = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(max_item_num * HASH_RST_MAX); + ZXIC_COMM_CHECK_POINT_MEMORY_FREE2PTR_NO_ASSERT(pRst, pKey, pDumpData); + + ZXIC_COMM_MEMSET(pDumpData, 0x0, max_item_num * sizeof(DPP_HASH_ENTRY)); + ZXIC_COMM_MEMSET(pKey, 0x0, max_item_num * HASH_KEY_MAX); + ZXIC_COMM_MEMSET(pRst, 0x0, max_item_num * HASH_RST_MAX); + + p_dump_hash_entry = (DPP_HASH_ENTRY *)pDumpData; + for(index = 0; index < max_item_num; index++) + { + p_temp_entry = p_dump_hash_entry + index; + p_temp_entry->p_key = pKey + index * HASH_KEY_MAX; + p_temp_entry->p_rst = pRst + index * HASH_RST_MAX; + } + + rc = dtb_sdt_dump_dma_alloc(dev, DTB_SDT_DUMP_SIZE, &dma_phy_addr, &dma_vir_addr); + ZXIC_COMM_CHECK_RC_MEMORY_FREE3PTR_NO_ASSERT(rc, "dtb_sdt_dump_dma_alloc", pRst, pKey, pDumpData); + + rc = dpp_dtb_dump_sdt_addr_set(dev, queue_id, sdt_no, dma_phy_addr, dma_vir_addr, DTB_SDT_DUMP_SIZE); + ZXIC_COMM_CHECK_RC_MEMORY_FREE3PTR_NO_ASSERT(rc, "dpp_dtb_dump_sdt_addr_set", pRst, pKey, pDumpData); + + rc = dpp_dtb_hash_table_only_zcam_dump(dev, queue_id, sdt_no, pDumpData, &entryNum); + + dpp_dtb_dump_sdt_addr_get(dev, queue_id, sdt_no, &dma_phy_addr, &dma_vir_addr, &dma_size); + dtb_sdt_dump_dma_release(dev, dma_size, dma_phy_addr, dma_vir_addr); + dpp_dtb_dump_sdt_addr_clear(dev, queue_id, sdt_no); + + if(rc != DPP_OK) + { + ZXIC_COMM_FREE(pKey); + ZXIC_COMM_FREE(pRst); + ZXIC_COMM_FREE(pDumpData); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_hash_table_only_zcam_dump"); + } + ZXIC_COMM_TRACE_INFO("dpp_dtb_hash_table_only_zcam_dump multicast entry_num: %d\n", entryNum); + + for(index = 0; index < entryNum; index++) + { + p_temp_entry = p_dump_hash_entry + index; + p_multicast_mac_data = pHashDataArr + index; + // //打印数据 + dpp_dtb_data_print(p_temp_entry->p_key, DPP_GET_ACTU_KEY_BY_SIZE(sdt_hash_info.key_size) + 1); + dpp_dtb_data_print(p_temp_entry->p_rst, 4 * (0x1 << sdt_hash_info.rsp_mode)); + + rc = pAptCallback->se_func_info.hashFunc.hash_get_func(p_multicast_mac_data, p_temp_entry); + ZXIC_COMM_CHECK_DEV_RC_MEMORY_FREE3PTR_NO_ASSERT(DEV_ID(dev), rc, "hash_get_func", pRst, pKey, pDumpData); + } + + *p_entry_num = entryNum; + + ZXIC_COMM_FREE(pKey); + ZXIC_COMM_FREE(pRst); + ZXIC_COMM_FREE(pDumpData); + + return DPP_OK; +} diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/driver/source/dpp_drv_init.c b/src/net/drivers/net/ethernet/dinghai/en_np/driver/source/dpp_drv_init.c new file mode 100644 index 0000000..af3057d --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/driver/source/dpp_drv_init.c @@ -0,0 +1,115 @@ +#include "dpp_apt_se_api.h" +#include "dpp_stat_api.h" +#include "dpp_drv_init.h" +#include "dpp_drv_acl.h" +#include "dpp_drv_hash.h" +#include "dpp_drv_eram.h" +#include "dpp_hash.h" +#include "dpp_apt_se.h" + +#define DPP_FLOW_INIT_START ((ZXIC_UINT32)(0)) +#define DPP_FLOW_INIT_SUCCESS ((ZXIC_UINT32)(1)) + +#define DPP_FLOW_INIT_STATUS_CHECK()\ + do{\ + if(DPP_FLOW_INIT_SUCCESS != dpp_flow_init_status)\ + {\ + return DPP_OK;\ + }\ + }while(0) + +#define DPP_FLOW_INIT_SUCCESS_STATUS_CHECK()\ + do{\ + if(DPP_FLOW_INIT_SUCCESS == dpp_flow_init_status)\ + {\ + return DPP_OK;\ + }\ + }while(0) + +ZXIC_UINT32 dpp_flow_init_status = DPP_FLOW_INIT_START; + +DPP_STATUS dpp_flow_init_status_set(ZXIC_UINT32 status) +{ + ZXIC_COMM_CHECK_INDEX(status, DPP_FLOW_INIT_START, DPP_FLOW_INIT_SUCCESS); + + dpp_flow_init_status = status; + + return DPP_OK; +} + +DPP_STATUS dpp_flow_init(DPP_DEV_T *dev) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_COMM_CHECK_POINT(dev); + DPP_FLOW_INIT_SUCCESS_STATUS_CHECK(); + + ZXIC_COMM_PRINT("[%s] start.\n", __FUNCTION__); + + // hash init + rc = dpp_apt_hash_global_res_init(dev); + ZXIC_COMM_CHECK_RC(rc, "dpp_apt_hash_global_res_init"); + + rc = dpp_apt_hash_func_res_init(DEV_ID(dev), g_hashTable.func_num, g_hashTable.func); + ZXIC_COMM_CHECK_RC(rc, "dpp_apt_hash_func_res_init"); + + rc = dpp_apt_hash_bulk_res_init(DEV_ID(dev), g_hashTable.bulk_num, g_hashTable.bulk); + ZXIC_COMM_CHECK_RC(rc, "dpp_apt_hash_bulk_res_init"); + + // tbl-res must be initialized after fun-res and buld-res + rc = dpp_apt_hash_tbl_res_init(dev, g_hashTable.ser_num, g_hashTable.ser); + ZXIC_COMM_CHECK_RC(rc, "dpp_apt_hash_tbl_res_init"); + + // eram init + rc = dpp_apt_eram_res_init(dev, g_eRamTable.tbl_num, g_eRamTable.eram); + ZXIC_COMM_CHECK_RC(rc, "dpp_apt_eram_res_init"); + + // init acl + rc = dpp_apt_acl_res_init(dev, g_aclTable.tbl_num, g_aclTable.acl); + ZXIC_COMM_CHECK_RC(rc, "dpp_apt_acl_res_init"); + +#ifdef DPP_FLOW_HW_INIT + rc = dpp_stat_ppu_eram_baddr_set(dev, ZXDH_STAT_PPU_ERAM_BAADDR); + ZXIC_COMM_CHECK_RC(rc, "dpp_stat_ppu_eram_baddr_set"); + + rc = dpp_stat_ppu_eram_depth_set(dev, (ZXDH_STAT_PPU_ERAM_DEPTH / 2)); //表项深度以128bit为单位 + ZXIC_COMM_CHECK_RC(rc, "dpp_stat_ppu_eram_depth_set"); +#endif + + rc = dpp_flow_init_status_set(DPP_FLOW_INIT_SUCCESS); + ZXIC_COMM_CHECK_RC(rc, "dpp_flow_init_status_set"); + + ZXIC_COMM_PRINT("[%s] success.\n", __FUNCTION__); + + return DPP_OK; +} + +DPP_STATUS dpp_flow_uninit(ZXIC_UINT32 dev_id) +{ + DPP_STATUS rc = DPP_OK; + + DPP_FLOW_INIT_STATUS_CHECK(); + + ZXIC_COMM_PRINT("[%s] start.\n", __FUNCTION__); + + rc = dpp_hash_soft_uninstall(dev_id); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_hash_soft_uninstall"); + + rc = dpp_acl_res_destroy(dev_id); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_acl_res_destroy"); + + ZXIC_COMM_PRINT("[%s] success.\n", __FUNCTION__); + + return DPP_OK; +} + +DPP_STATUS dpp_flow_data_all_flush(DPP_DEV_T *dev, ZXIC_UINT32 queue_id) +{ + DPP_STATUS rc = DPP_OK; + + rc = dpp_apt_hash_func_flush_hardware_all(dev, g_hashTable.func_num, g_hashTable.func, queue_id); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_apt_hash_func_flush_hardware"); + + return rc; +} + diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/fc/Kbuild.include b/src/net/drivers/net/ethernet/dinghai/en_np/fc/Kbuild.include new file mode 100644 index 0000000..e1fac1d --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/fc/Kbuild.include @@ -0,0 +1,4 @@ +cur_dir := en_np/fc/ +subdirs := source/ +src_files += +include $(foreach subdir, $(subdirs), $(dinghai_root)/$(cur_dir)$(subdir)/Kbuild.include) \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/fc/include/dpp_drv_fc.h b/src/net/drivers/net/ethernet/dinghai/en_np/fc/include/dpp_drv_fc.h new file mode 100644 index 0000000..fd15607 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/fc/include/dpp_drv_fc.h @@ -0,0 +1,65 @@ +#ifndef _DPP_DRV_FC_H_ +#define _DPP_DRV_FC_H_ + +#include "zxic_common.h" +#include "dpp_pbu.h" +#include "dpp_pbu_api.h" +#include "dpp_drv_qos.h" + +/***********************************************************/ +/**对外接口 配置基于vport的端口指针阈值 +* @param vport_id--vport号 +* @param port_id 端口号 +* @param p_para 端口阈值 +* @return +* @remark 无 +* @see +* @author sun @date 2023/11/17 +************************************************************/ +DPP_STATUS dpp_port_th_set(DPP_PF_INFO_T* pf_info, + ZXIC_UINT32 port_id, + DPP_PBU_PORT_TH_PARA_T *p_para); + +/***********************************************************/ +/** 读取端口的阈值 +* @param vport_id--vport号 +* @param port_id 端口号 +* @param p_para 端口阈值 +* @return +* @remark 无 +* @see +* @author sun @date 2023/11/17 +************************************************************/ +DPP_STATUS dpp_port_th_get(DPP_PF_INFO_T* pf_info, + ZXIC_UINT32 port_id, + DPP_PBU_PORT_TH_PARA_T *p_para); + +/***********************************************************/ +/**对外接口 配置基于vport的端口指定端口按cos优先级起pfc流控的优先级流控指针阈值 +* @param vport_id--vport号 +* @param port_id 端口号 +* @param p_para cos阈值，要求高优先级的阈值不小于低优先级的阈值 +* @return +* @remark 无 +* @see +* @author sun @date 2023/11/17 +************************************************************/ +DPP_STATUS dpp_port_cos_th_set(DPP_PF_INFO_T* pf_info, + ZXIC_UINT32 port_id, + DPP_PBU_PORT_COS_TH_PARA_T *p_para); + +/***********************************************************/ +/** 读取指定端口中各cos的优先级流控指针阈值，仅对lif0的48个通道有效 +* @param vport_id--vport号 +* @param port_id 端口号 +* @param p_para cos阈值，要求高优先级的阈值不小于低优先级的阈值 +* @return +* @remark 无 +* @see +* @author sun @date 2023/11/17 +************************************************************/ +DPP_STATUS dpp_port_cos_th_get(DPP_PF_INFO_T* pf_info, + ZXIC_UINT32 port_id, + DPP_PBU_PORT_COS_TH_PARA_T *p_para); + +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/fc/source/Kbuild.include b/src/net/drivers/net/ethernet/dinghai/en_np/fc/source/Kbuild.include new file mode 100644 index 0000000..c97776c --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/fc/source/Kbuild.include @@ -0,0 +1,2 @@ +cur_dir := en_np/fc/source/ +src_files += $(addprefix $(cur_dir),$(notdir $(wildcard $(dinghai_root)/$(cur_dir)*.c))) \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/fc/source/dpp_drv_fc.c b/src/net/drivers/net/ethernet/dinghai/en_np/fc/source/dpp_drv_fc.c new file mode 100755 index 0000000..31b10b3 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/fc/source/dpp_drv_fc.c @@ -0,0 +1,138 @@ +#include "dpp_drv_fc.h" + +/***********************************************************/ +/**对外接口 配置基于vport的端口指针阈值 +* @param vport_id--vport号 +* @param port_id 端口号 +* @param p_para 端口阈值 +* @return +* @remark 无 +* @see +* @author sun @date 2023/11/17 +************************************************************/ +DPP_STATUS dpp_port_th_set(DPP_PF_INFO_T* pf_info, + ZXIC_UINT32 port_id, + DPP_PBU_PORT_TH_PARA_T *p_para) +{ + DPP_STATUS ret = DPP_OK; + DPP_DEV_T dev = {0}; + ZXIC_UINT32 dev_id = 0; + + ZXIC_COMM_CHECK_POINT(pf_info); + + ret = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get"); + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, port_id, 0, DPP_TM_PP_NUM - 1); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_para); + + ret = dpp_pbu_port_th_set(&dev, port_id, p_para); + ZXIC_COMM_CHECK_RC(ret, "dpp_pbu_port_th_set"); + + return ret; +} +EXPORT_SYMBOL(dpp_port_th_set); + +/***********************************************************/ +/** 读取端口的阈值 +* @param vport_id--vport号 +* @param port_id 端口号 +* @param p_para 端口阈值 +* @return +* @remark 无 +* @see +* @author sun @date 2023/11/17 +************************************************************/ +DPP_STATUS dpp_port_th_get(DPP_PF_INFO_T* pf_info, + ZXIC_UINT32 port_id, + DPP_PBU_PORT_TH_PARA_T *p_para) +{ + DPP_STATUS ret = DPP_OK; + DPP_DEV_T dev = {0}; + ZXIC_UINT32 dev_id = 0; + + ZXIC_COMM_CHECK_POINT(pf_info); + + ret = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get"); + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, port_id, 0, DPP_TM_PP_NUM - 1); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_para); + + ret = dpp_pbu_port_th_get(&dev, port_id, p_para); + ZXIC_COMM_CHECK_RC(ret, "dpp_pbu_port_th_get"); + + return ret; +} +EXPORT_SYMBOL(dpp_port_th_get); + +/***********************************************************/ +/**对外接口 配置基于vport的端口指定端口按cos优先级起pfc流控的优先级流控指针阈值 +* @param vport_id--vport号 +* @param port_id 端口号 +* @param p_para cos阈值，要求高优先级的阈值不小于低优先级的阈值 +* @return +* @remark 无 +* @see +* @author sun @date 2023/11/17 +************************************************************/ +DPP_STATUS dpp_port_cos_th_set(DPP_PF_INFO_T* pf_info, + ZXIC_UINT32 port_id, + DPP_PBU_PORT_COS_TH_PARA_T *p_para) +{ + DPP_STATUS ret = DPP_OK; + DPP_DEV_T dev = {0}; + ZXIC_UINT32 dev_id = 0; + + ZXIC_COMM_CHECK_POINT(pf_info); + + ret = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get"); + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, port_id, 0, DPP_TM_PP_NUM - 1); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_para); + + ret = dpp_pbu_port_cos_th_set(&dev, port_id, p_para); + ZXIC_COMM_CHECK_RC(ret, "dpp_pbu_port_cos_th_set"); + + return ret; +} +EXPORT_SYMBOL(dpp_port_cos_th_set); + +/***********************************************************/ +/** 读取指定端口中各cos的优先级流控指针阈值，仅对lif0的48个通道有效 +* @param vport_id--vport号 +* @param port_id 端口号 +* @param p_para cos阈值，要求高优先级的阈值不小于低优先级的阈值 +* @return +* @remark 无 +* @see +* @author sun @date 2023/11/17 +************************************************************/ +DPP_STATUS dpp_port_cos_th_get(DPP_PF_INFO_T* pf_info, + ZXIC_UINT32 port_id, + DPP_PBU_PORT_COS_TH_PARA_T *p_para) +{ + DPP_STATUS ret = DPP_OK; + DPP_DEV_T dev = {0}; + ZXIC_UINT32 dev_id = 0; + + ZXIC_COMM_CHECK_POINT(pf_info); + + ret = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get"); + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, port_id, 0, DPP_TM_PP_NUM - 1); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_para); + + ret = dpp_pbu_port_cos_th_get(&dev, port_id, p_para); + ZXIC_COMM_CHECK_RC(ret, "dpp_pbu_port_cos_th_get"); + + return ret; +} +EXPORT_SYMBOL(dpp_port_cos_th_get); + diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/init/Kbuild.include b/src/net/drivers/net/ethernet/dinghai/en_np/init/Kbuild.include new file mode 100644 index 0000000..09f56ad --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/init/Kbuild.include @@ -0,0 +1,4 @@ +cur_dir := en_np/init/ +subdirs := source/ +src_files += +include $(foreach subdir, $(subdirs), $(dinghai_root)/$(cur_dir)$(subdir)/Kbuild.include) \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/init/include/dpp_np_init.h b/src/net/drivers/net/ethernet/dinghai/en_np/init/include/dpp_np_init.h new file mode 100644 index 0000000..25f7eec --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/init/include/dpp_np_init.h @@ -0,0 +1,11 @@ +#ifndef _DPP_NP_INIT_H_ +#define _DPP_NP_INIT_H_ + +#include +#include "zxic_common.h" +#include "dpp_dev.h" + +ZXIC_UINT32 dpp_vport_register(DPP_PF_INFO_T* pf_info, struct pci_dev *p_dev); +ZXIC_UINT32 dpp_vport_unregister(DPP_PF_INFO_T* pf_info); + +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/init/source/Kbuild.include b/src/net/drivers/net/ethernet/dinghai/en_np/init/source/Kbuild.include new file mode 100644 index 0000000..7515849 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/init/source/Kbuild.include @@ -0,0 +1,2 @@ +cur_dir := en_np/init/source/ +src_files += $(addprefix $(cur_dir),$(notdir $(wildcard $(dinghai_root)/$(cur_dir)*.c))) \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/init/source/dpp_np_init.c b/src/net/drivers/net/ethernet/dinghai/en_np/init/source/dpp_np_init.c new file mode 100644 index 0000000..4c47e5f --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/init/source/dpp_np_init.c @@ -0,0 +1,169 @@ +#include "zxic_common.h" +#include "dpp_np_init.h" +#include "dpp_dev.h" +#include "dpp_dtb.h" +#include "dpp_init.h" +#include "dpp_kernel_init.h" +#include "dpp_netlink.h" +#include "dpp_dtb_table_api.h" +#include "dpp_drv_init.h" +#include "dpp_tbl_comm.h" +#include "dpp_apt_se.h" +#include "dpp_cmd_init.h" +#include "dpp_agent_channel.h" +#include "dpp_hash.h" +#include "dpp_sdt_mgr.h" + +ZXIC_UINT32 dpp_vport_register(DPP_PF_INFO_T* pf_info, struct pci_dev *p_dev) +{ + DPP_DEV_T dev = {0}; + + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 rc = DPP_OK; + + ZXIC_COMM_CHECK_POINT(pf_info); + ZXIC_COMM_CHECK_POINT(p_dev); + ZXIC_COMM_CHECK_INDEX_EQUAL_RETURN_OK(IS_PF(pf_info->vport), 0); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x register start.\n", __FUNCTION__, + pf_info->slot, pf_info->vport); + + rc = dpp_dev_pcie_channel_add(dev_id, pf_info, p_dev); + ZXIC_COMM_CHECK_RC(rc, "dpp_dev_pcie_channel_add"); + + rc = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get"); + + rc = dpp_dtb_init(&dev); + ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_init"); + +#ifdef DPP_FLOW_HW_INIT + rc = dpp_flow_init(&dev); + ZXIC_COMM_CHECK_RC(rc, "dpp_flow_init"); +#endif + + rc = dpp_apt_dtb_res_init(&dev); + ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_res_init"); + + rc = dpp_vport_mgr_init(pf_info); + ZXIC_COMM_CHECK_RC(rc, "dpp_vport_mgr_init"); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x register success.\n", __FUNCTION__, + pf_info->slot, pf_info->vport); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_vport_register); + +ZXIC_UINT32 dpp_vport_unregister(DPP_PF_INFO_T* pf_info) +{ + DPP_DEV_T dev = {0}; + + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 queue = 0; + ZXIC_UINT32 rc = DPP_OK; + + ZXIC_COMM_CHECK_POINT(pf_info); + ZXIC_COMM_CHECK_INDEX_EQUAL_RETURN_OK(IS_PF(pf_info->vport), 0); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x unregister start.\n", __FUNCTION__, + pf_info->slot, pf_info->vport); + + rc = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get"); + + rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue); + ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get"); + + rc = dpp_dtb_queue_release(&dev, "pf", queue); + ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_release"); + + rc = dpp_dtb_queue_dma_mem_release(&dev, queue); + ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_dma_mem_release"); + + rc = dpp_dev_pcie_channel_del(dev_id, pf_info); + ZXIC_COMM_CHECK_RC(rc, "dpp_dev_pcie_channel_del"); + + rc = dpp_vport_mgr_release(pf_info); + ZXIC_COMM_CHECK_RC(rc, "dpp_vport_mgr_release"); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x unregister success.\n", __FUNCTION__, + pf_info->slot, pf_info->vport); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_vport_unregister); + +static DPP_SYS_INIT_CTRL_T g_np_sys_init = { + .device_type = DPP_DEV_TYPE_CHIP, + .flags = DPP_DEV_ACCESS_TYPE_PCIE << 0, +}; + +static int __init dpp_np_init(void) +{ + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 rc = DPP_OK; + +#ifndef DPP_FLOW_HW_INIT + DPP_DEV_T dev = {dev_id, {0, 0, 0, 0, 0}}; +#endif + + ZXIC_COMM_PRINT("[%s] start.\n", __FUNCTION__); + + rc = dpp_init(dev_id, &g_np_sys_init); + ZXIC_COMM_CHECK_RC(rc, "dpp_init"); + +#ifndef DPP_FLOW_HW_INIT + rc = dpp_flow_init(&dev); + ZXIC_COMM_CHECK_RC(rc, "dpp_flow_init"); +#endif + + rc = dpp_agent_channel_init(); + ZXIC_COMM_CHECK_RC(rc, "dpp_agent_channel_init"); + + rc = dpp_netlink_init(); + ZXIC_COMM_CHECK_RC(rc, "dpp_netlink_init"); + + rc = dpp_cmd_init(); + ZXIC_COMM_CHECK_RC(rc, "dpp_cmd_init"); + + ZXIC_COMM_PRINT("[%s] success.\n", __FUNCTION__); + + return DPP_OK; +} + +ZXIC_UINT32 dpp_np_online_uninstall(void) +{ + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 rc = DPP_OK; + + rc = dpp_flow_uninit(dev_id); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_flow_uninit"); + + rc = dpp_dtb_mgr_destory_all(); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_mgr_destory"); + + rc = dpp_sdt_mgr_destroy(dev_id); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_sdt_mgr_destroy"); + + rc = dpp_dev_del(dev_id); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dev_del"); + + return DPP_OK; +} + +static void __exit dpp_np_exit(void) +{ + ZXIC_COMM_PRINT("[%s] start.\n", __FUNCTION__); + + dpp_netlink_exit(); + dpp_agent_channel_exit(); + dpp_np_online_uninstall(); + + ZXIC_COMM_PRINT("[%s] success.\n", __FUNCTION__); +} + +module_init(dpp_np_init); +module_exit(dpp_np_exit); + +MODULE_LICENSE("GPL"); diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/netlink/Kbuild.include b/src/net/drivers/net/ethernet/dinghai/en_np/netlink/Kbuild.include new file mode 100644 index 0000000..70b1d52 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/netlink/Kbuild.include @@ -0,0 +1,4 @@ +cur_dir := en_np/netlink/ +subdirs := source/ +src_files += +include $(foreach subdir, $(subdirs), $(dinghai_root)/$(cur_dir)$(subdir)/Kbuild.include) \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/netlink/include/dpp_netlink.h b/src/net/drivers/net/ethernet/dinghai/en_np/netlink/include/dpp_netlink.h new file mode 100644 index 0000000..8989efe --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/netlink/include/dpp_netlink.h @@ -0,0 +1,30 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_netlink.h +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : +* 完成日期 : 2014/01/27 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ + +#ifndef DPP_NETLINK_H +#define DPP_NETLINK_H + +#include "zxic_common.h" +#include "dpp_type_api.h" + +ZXIC_SINT32 dpp_netlink_init(ZXIC_VOID); +ZXIC_VOID dpp_netlink_exit(ZXIC_VOID); +DPP_STATUS dpp_netlink_regist_msg_proc_fun(ZXIC_UINT32 id, ZXIC_VOID *ptr); + +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/netlink/source/Kbuild.include b/src/net/drivers/net/ethernet/dinghai/en_np/netlink/source/Kbuild.include new file mode 100644 index 0000000..2405820 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/netlink/source/Kbuild.include @@ -0,0 +1,2 @@ +cur_dir := en_np/netlink/source/ +src_files += $(addprefix $(cur_dir),$(notdir $(wildcard $(dinghai_root)/$(cur_dir)*.c))) \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/netlink/source/dpp_netlink.c b/src/net/drivers/net/ethernet/dinghai/en_np/netlink/source/dpp_netlink.c new file mode 100644 index 0000000..78f77e4 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/netlink/source/dpp_netlink.c @@ -0,0 +1,205 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "dpp_netlink.h" + +#define DPP_NETLINK_PROTOCOL ((ZXIC_UINT32)(29)) +#define DPP_NETLINK_GROUP_ID ((ZXIC_UINT32)(1)) +#define DPP_NETLINK_MAX_PROC ((ZXIC_UINT32)(2048)) + +typedef DPP_STATUS (*DPP_NETLINK_PROC_PTR)(ZXIC_VOID *msg_body, ZXIC_UINT32 msg_len, ZXIC_VOID **resp, ZXIC_UINT32 *reps_len); + +static struct sock *dpp_netlink_sk; +static DPP_NETLINK_PROC_PTR dpp_netlink_proc_ptr[DPP_NETLINK_MAX_PROC] = {0}; + +static DPP_STATUS dpp_netlink_send_ack_msg(ZXIC_VOID *data, ZXIC_UINT32 len) +{ + struct sk_buff *skb = NULL; + struct nlmsghdr *nlh = NULL; + ZXIC_SINT32 rtn = DPP_OK; + + if (data == NULL) + { + ZXIC_COMM_PRINT("%s: data invalid.\n", __FUNCTION__); + return DPP_ERR; + } + + skb = alloc_skb(NLMSG_SPACE(len), GFP_KERNEL); + if (skb == NULL) + { + ZXIC_COMM_PRINT("%s: alloc_skb failed.\n", __FUNCTION__); + return DPP_ERR; + } + + nlh = nlmsg_put(skb, 0, 0, 0, len, 0); + if (nlh == NULL) + { + ZXIC_COMM_PRINT("%s: nlmsg_put failed.\n", __FUNCTION__); + return DPP_ERR; + } + + nlh->nlmsg_flags = NLM_F_ACK; + memcpy(NLMSG_DATA(nlh), data, len); + + rtn = nlmsg_multicast(dpp_netlink_sk, skb, 0, DPP_NETLINK_GROUP_ID, 0); + if (rtn < 0) + { + ZXIC_COMM_PRINT("%s: nlmsg_multicast failed, rtn %d.\n", __FUNCTION__, rtn); + return DPP_ERR; + } + return DPP_OK; +} + +static DPP_STATUS dpp_netlink_dispach_msg(struct nlmsghdr *nlh) +{ + ZXIC_UINT8 *data = NULL; + ZXIC_UINT32 id = 0; + ZXIC_UINT32 len = 0; + ZXIC_UINT8 *req = NULL; + ZXIC_VOID *resp = NULL; + ZXIC_UINT32 resp_len = 0; + ZXIC_UINT32 rtn = DPP_OK; + + DPP_NETLINK_PROC_PTR ptr = NULL; + + if (nlh == NULL) + { + ZXIC_COMM_PRINT("%s: nlh invalid.\n", __FUNCTION__); + return DPP_ERR; + } + + id = *(ZXIC_UINT32 *)NLMSG_DATA(nlh); + len = nlh->nlmsg_len - NLMSG_HDRLEN; + req = (ZXIC_UINT8 *)NLMSG_DATA(nlh); + if (id > (DPP_NETLINK_MAX_PROC - 1)) + { + ZXIC_COMM_PRINT("%s: id %u invalid.\n", __FUNCTION__, id); + return DPP_ERR; + } + + ptr = dpp_netlink_proc_ptr[id]; + if (ptr == NULL) + { + ZXIC_COMM_PRINT("%s: ptr invalid.\n", __FUNCTION__); + return DPP_ERR; + } + + rtn = ptr(req, len, &resp, &resp_len); + if (rtn != DPP_OK) + { + kfree(resp); + ZXIC_COMM_PRINT("%s: proc id %u failed.\n", __FUNCTION__, id); + return rtn; + } + + data = (ZXIC_UINT8 *)kmalloc(NLMSG_ALIGN(resp_len) + sizeof(ZXIC_UINT32), GFP_KERNEL); + if (data == NULL) + { + kfree(resp); + ZXIC_COMM_PRINT("%s: kmalloc failed.\n", __FUNCTION__); + return DPP_ERR; + } + memcpy(data, &rtn, sizeof(ZXIC_UINT32)); + + if (resp != NULL) + { + memcpy(data + sizeof(ZXIC_UINT32), resp, resp_len); + } + + dpp_netlink_send_ack_msg(data, NLMSG_ALIGN(resp_len) + sizeof(ZXIC_UINT32)); + + kfree(data); + kfree(resp); + + return DPP_OK; +} + +static ZXIC_VOID dpp_netlink_recv_msg(struct sk_buff *__skb) +{ + struct sk_buff *skb; + struct nlmsghdr *nlh; + ZXIC_UINT32 rtn = DPP_ERR; + + skb = skb_get(__skb); + if (skb == NULL) + { + ZXIC_COMM_PRINT("%s: get skb failed.\n", __FUNCTION__); + return; + } + + nlh = nlmsg_hdr(skb); + if ((nlh == NULL) || !NLMSG_OK(nlh, skb->len)) + { + kfree_skb(skb); + ZXIC_COMM_PRINT("%s: skb format invalid.\n", __FUNCTION__); + return; + } + + if ((nlh->nlmsg_flags & NLM_F_REQUEST) != 0) + { + if (dpp_netlink_dispach_msg(nlh) != DPP_OK) + { + dpp_netlink_send_ack_msg((ZXIC_UINT8 *)&rtn, sizeof(ZXIC_UINT32)); + ZXIC_COMM_PRINT("%s: dpp_netlink_dispach_msg failed.\n", __FUNCTION__); + } + kfree_skb(skb); + return; + } + + kfree_skb(skb); + ZXIC_COMM_PRINT("%s: nlmsg_flags 0x%04x invalid.\n", __FUNCTION__, nlh->nlmsg_flags); + return; +} + +DPP_STATUS dpp_netlink_regist_msg_proc_fun(ZXIC_UINT32 id, ZXIC_VOID *ptr) +{ + if (ptr == NULL) + { + ZXIC_COMM_PRINT("%s: ptr invalid.\n", __FUNCTION__); + return DPP_ERR; + } + if (id > (DPP_NETLINK_MAX_PROC - 1)) + { + ZXIC_COMM_PRINT("%s: id %u invalid.\n", __FUNCTION__, id); + return DPP_ERR; + } + dpp_netlink_proc_ptr[id] = ptr; + return DPP_OK; +} + +ZXIC_SINT32 dpp_netlink_init(ZXIC_VOID) +{ + struct netlink_kernel_cfg cfg = { + .input = dpp_netlink_recv_msg, + }; + + ZXIC_COMM_PRINT("[%s] start.\n", __FUNCTION__); + + // dpp_netlink_sk = netlink_kernel_create(get_net_ns_by_pid(1), DPP_NETLINK_PROTOCOL, &cfg); + dpp_netlink_sk = netlink_kernel_create(&init_net, DPP_NETLINK_PROTOCOL, &cfg); + if (!dpp_netlink_sk) + { + ZXIC_COMM_PRINT("%s: create socket failed.\n", __FUNCTION__); + return DPP_ERR; + } + + ZXIC_COMM_PRINT("[%s] success.\n", __FUNCTION__); + + return DPP_OK; +} + +ZXIC_VOID dpp_netlink_exit(ZXIC_VOID) +{ + ZXIC_COMM_PRINT("[%s] start.\n", __FUNCTION__); + netlink_kernel_release(dpp_netlink_sk); + ZXIC_COMM_PRINT("[%s] success.\n", __FUNCTION__); +} diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/qos/Kbuild.include b/src/net/drivers/net/ethernet/dinghai/en_np/qos/Kbuild.include new file mode 100644 index 0000000..2e54261 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/qos/Kbuild.include @@ -0,0 +1,4 @@ +cur_dir := en_np/qos/ +subdirs := source/ +src_files += +include $(foreach subdir, $(subdirs), $(dinghai_root)/$(cur_dir)$(subdir)/Kbuild.include) \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/qos/include/dpp_drv_qos.h b/src/net/drivers/net/ethernet/dinghai/en_np/qos/include/dpp_drv_qos.h new file mode 100644 index 0000000..8916bb0 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/qos/include/dpp_drv_qos.h @@ -0,0 +1,568 @@ +/************************************************************** +* TM调度器资源分配如下 +* FQ +*fq_num: 1280 : 0, 1, 2 ... 0x4ff +*fq2_num: 1024 : 0x500, 0x502, 0x504 ... 0xcfe +*fq4_num: 1024 : 0xd00, 0xd04, 0xd08 ... 0x1cfc +*fq8_num: 1120 : 0x1d00, 0x1d08, 0x1d10 ... 0x3ff8 +* SP-WFQ +*sp_num: 128 : 0x4000, 0x4001, 0x4002 ... 0x407f +*wfq_num: 2048 : 0x4080, 0x4081, 0x4082 ... 0x487f +*wfq2_num: 256 : 0x4880, 0x4882, 0x4884 ... 0x4a7e +*wfq4_num: 256 : 0x4a80, 0x4a84, 0x4a88 ... 0x4e7c +*wfq8_num: 688 : 0x4e80, 0x4e88, 0x4e90 ... 0x63f8 +* +*队列资源分配如下 +*flow id 0~0xf 预留 0队列用于MR复制队列， 0x10~0xfff 通用队列 + +* PLCR profileid资源分配如下 +* 一级CAR +* flowid:32K, profileid:512 +* 一级CAR +* flowid:4K, profileid:128 +* 一级CAR +* flowid:1K, profileid:32 +***************************************************************/ +#ifndef _DPP_DRV_QOS_H_ +#define _DPP_DRV_QOS_H_ + +#include "zxic_common.h" +#include "dpp_tm.h" +#include "dpp_tm_api.h" +#include "dpp_stat_car.h" +#include "dpp_stat_api.h" +#include "dpp_agent_channel.h" + +/****************************************************************************** + * 宏定义 * + *****************************************************************************/ +#define DPP_VPORT_NUM_MAX (0x7fff) +#define DPP_CRDT_LEVEL_MAX (7) +#define DPP_SCHE_TYPE_MAX (10) + +#define DPP_TM_PORT_WIDTH (56) +#define DPP_TM_VPORT_WIDTH (32) +#define DPP_TM_LEVEL_WIDTH (28) +#define DPP_TM_TYPE_WIDTH (24) + +#define G_SCH_ID_LEN (8) + +#define CAR_TYPE_MAX (4) + +#define G_PROFILE_ID_LEN (8) + +/* Get Real port */ +#define DPP_TM_CRDT_PP_PORT_GET(_gsch_id, _pp_port) \ + ((_pp_port) = ((_gsch_id >> DPP_TM_PORT_WIDTH) & 0xffff)) + +/* Get Real vport */ +#define DPP_TM_CRDT_VPORT_GET(_gsch_id, _vport) \ + ((_vport) = ((_gsch_id >> DPP_TM_VPORT_WIDTH) & 0xffff)) + +/* Get Real level */ +#define DPP_TM_CRDT_LEVEL_GET(_gsch_id,_sche_level) \ + ((_sche_level) = ((_gsch_id >> DPP_TM_LEVEL_WIDTH) & 0xf)) + +/* Get Real type */ +#define DPP_TM_CRDT_TYPE_GET(_gsch_id,_sche_type) \ + ((_sche_type) = ((_gsch_id >> DPP_TM_TYPE_WIDTH) & 0xf)) + +/* Get Real se_id */ +#define DPP_TM_CRDT_SE_ID_GET(_gsch_id,_se_id) \ + ((_se_id) = ((_gsch_id & 0xffff))) + +/* Get Real profile */ +#define DPP_CAR_PROFILE_ID_GET(_profile_id,_profileid) \ + ((_profileid) = ((_profile_id & 0xffff))) + +/****************************************************************************** + * 类型定义 * + *****************************************************************************/ + +/****************************************************************************** + * 接口定义 * + *****************************************************************************/ +/***********************************************************/ +/**对外接口 TM资源申请 +* @param vport_id--vport号 +* @param pp_port--端口0~9 +* @param numq--申请id个数 1 +* @param level--挂接层级 +* @param flags--se_id类型 +* @param gsch_id--调度单元号 +* @return +* @remark 无 +* @see +* @author sun @date 2023/11/17 +************************************************************/ +DPP_STATUS dpp_cosq_gsch_id_add(DPP_PF_INFO_T* pf_info, + ZXIC_UINT32 pp_port, + ZXIC_UINT32 numq, + ZXIC_UINT32 level, + ZXIC_UINT32 flags, + ZXIC_UINT64 *p_gsch_id); + +/***********************************************************/ +/**对外接口 TM资源释放 +* @param vport_id--vport号 +* @param pp_port--端口0~9 +* @param gsch_id--调度单元号 +* @return +* @remark 无 +* @see +* @author sun @date 2023/11/17 +************************************************************/ +DPP_STATUS dpp_cosq_gsch_id_delete(DPP_PF_INFO_T* pf_info, + ZXIC_UINT32 pp_port, + ZXIC_UINT64 gsch_id); + +/***********************************************************/ +/**对外接口 读取TM根节点 +* @param vport_id--vport号 +* @param pp_port--端口0~9 +* @param gsch_id--调度单元号 +* @return +* @remark 无 +* @see +* @author sun @date 2023/11/17 +************************************************************/ +DPP_STATUS dpp_sch_base_node_get(DPP_PF_INFO_T* pf_info, + ZXIC_UINT32 pp_port, + ZXIC_UINT64 *gsch_id); + +/***********************************************************/ +/**对外接口 配置se->pp->dev挂接关系 +* @param vport_id--vport号 +* @param se_id--调度器号 +* @param pp_id-端口号 +* @param weight-权重1 +* @param sp_mapping-优先级0-7 +* @return +* @remark 无 +* @see +* @author sun @date 2023/11/17 +************************************************************/ +DPP_STATUS dpp_crdt_se_pp_link_set(DPP_PF_INFO_T* pf_info, + ZXIC_UINT32 se_id, + ZXIC_UINT32 pp_id, + ZXIC_UINT32 weight, + ZXIC_UINT32 sp_mapping); + +/***********************************************************/ +/**对外接口 配置se->se层次化挂接关系 +* @param vport_id--vport号 +* @param se_id--调度器号 +* @param se_linkid--上级调度器号 +* @param se_weight -权重 +* @param se_sp-优先级0-7 +* @return +* @remark 无 +* @see +* @author sun @date 2023/11/17 +************************************************************/ +DPP_STATUS dpp_crdt_se_link_set(DPP_PF_INFO_T* pf_info, + ZXIC_UINT32 se_id, + ZXIC_UINT32 se_linkid, + ZXIC_UINT32 se_weight, + ZXIC_UINT32 se_sp); + +/***********************************************************/ +/**对外接口 配置flow级流队列挂接关系 +* @param vport_id--vport号 +* @param flow_id--0~4095 +* @param c_linkid--c桶se_id +* @param c_weight--c桶权重 +* @param c_sp--c桶优先级 +* @param mode--0-单桶 1-双桶 +* @param e_linkid--e桶se_id +* @param e_weight--e桶权重 +* @param e_sp--e桶优先级 +* @return +* @remark 无 +* @see +* @author sun @date 2023/11/17 +************************************************************/ +DPP_STATUS dpp_crdt_flow_link_set(DPP_PF_INFO_T* pf_info, + ZXIC_UINT32 flow_id, + ZXIC_UINT32 c_linkid, + ZXIC_UINT32 c_weight, + ZXIC_UINT32 c_sp, + ZXIC_UINT32 mode, + ZXIC_UINT32 e_linkid, + ZXIC_UINT32 e_weight, + ZXIC_UINT32 e_sp); + +/***********************************************************/ +/**对外接口 删除flow级流队列挂接关系 +* @param vport_id--vport号 +* @param id_s--起始flowid +* @param id_e--终止flowid +* @return +* @remark 无 +* @see +* @author sun @date 2023/11/17 +************************************************************/ +DPP_STATUS dpp_crdt_del_flow_link_set(DPP_PF_INFO_T* pf_info, + ZXIC_UINT32 id_s, + ZXIC_UINT32 id_e); + +/***********************************************************/ +/**对外接口 删除调度器挂接关系 +* @param vport_id--vport号 +* @param id_s--起始seid +* @param id_e--终止seid +* @return +* @remark 无 +* @see +* @author sun @date 2023/11/17 +************************************************************/ +DPP_STATUS dpp_crdt_del_se_link_set(DPP_PF_INFO_T* pf_info, + ZXIC_UINT32 id_s, + ZXIC_UINT32 id_e); + +/***********************************************************/ +/**对外接口 配置端口级整形 +* @param vport_id--vport号 +* @param pp_port--端口0~9 +* @param cir 单位Kb +* @param cbs 单位KB +* @param c_en c桶使能 +* @return +* @remark 无 +* @see +* @author sun @date 2023/11/17 +************************************************************/ +DPP_STATUS dpp_port_shape_set(DPP_PF_INFO_T* pf_info, + ZXIC_UINT32 pp_port, + ZXIC_UINT32 cir, + ZXIC_UINT32 cbs, + ZXIC_UINT32 c_en); + +/***********************************************************/ +/**对外接口 读取端口级整形 +* @param vport_id--vport号 +* @param pp_port--端口0~9 +* @param p_para 整形信息:cir/cbs/en +* @return +* @remark 无 +* @see +* @author sun @date 2023/11/17 +************************************************************/ +DPP_STATUS dpp_port_shape_get(DPP_PF_INFO_T* pf_info, + ZXIC_UINT32 pp_port, + DPP_TM_SHAPE_PP_PARA_T *p_para); + +/***********************************************************/ +/**对外接口 配置调度器整形 +* @param vport_id vport号 +* @param se_id 调度器编号号 +* @param pir pir总速率，单位Kb，范围同cir +* @param pbs pbs总桶深，单位KB，范围同cbs +* @param db_en 整形模式，0-单桶，1-双桶，仅FQ8/WFQ8有效 +* @param cir 调度器cir速率，单位Kb +* @param cbs 调度器cbs桶深，单位KB +* 注：cbs=0 表示关闭整形,即不限速 +* @return +* @remark 无 +* @see +* @author sun @date 2023/11/17 +************************************************************/ +DPP_STATUS dpp_se_shape_set(DPP_PF_INFO_T* pf_info, + ZXIC_UINT32 se_id, + ZXIC_UINT32 pir, + ZXIC_UINT32 pbs, + ZXIC_UINT32 db_en, + ZXIC_UINT32 cir, + ZXIC_UINT32 cbs); + +/***********************************************************/ +/**对外接口 配置flow整形 +* @param vport_id vport号 +* @param flow_id 流队列号 +* @param cir cir速率，单位Kb +* @param cbs cbs桶深，单位KB +* 注：cbs=0 表示关闭整形,即不限速 +* @param db_en 双桶整形使能，0-单桶，1-双桶 +* @param eir eir速率，单位Kb +* @param ebs ebs桶深，单位KB +* @return +* @remark 无 +* @see +* @author sun @date 2023/11/17 +************************************************************/ +DPP_STATUS dpp_flow_shape_set(DPP_PF_INFO_T* pf_info, + ZXIC_UINT32 flow_id, + ZXIC_UINT32 cir, + ZXIC_UINT32 cbs, + ZXIC_UINT32 db_en, + ZXIC_UINT32 eir, + ZXIC_UINT32 ebs); + +/***********************************************************/ +/**对外接口 配置流队列挂接到端口号 +* @param vport_id vport号 +* @param flow_id 流队列号 +* @param port 端口0~9 +* @return +* @remark 无 +* @see +* @author sun @date 2023/11/17 +************************************************************/ +DPP_STATUS dpp_flow_map_port_set(DPP_PF_INFO_T* pf_info, + ZXIC_UINT32 flow_id, + ZXIC_UINT32 port); + +/***********************************************************/ +/**对外接口 读取流队列挂接的端口号 +* @param vport_id vport号 +* @param flowid 流队列号 +* @param port 端口0~9 +* @return +* @remark 无 +* @see +* @author sun @date 2023/11/17 +************************************************************/ +DPP_STATUS dpp_flow_map_port_get(DPP_PF_INFO_T* pf_info, + ZXIC_UINT32 flow_id, + ZXIC_UINT32 *p_port); + +/***********************************************************/ +/**对外接口 配置TD门限值 +* @param vport_id vport号 +* @param flow_id 流队列号 +* @param td_th 配置的丢弃门限值 +* @return +* @remark 无 +* @see +* @author sun @date 2023/11/17 +************************************************************/ +DPP_STATUS dpp_flow_td_th_set(DPP_PF_INFO_T* pf_info, + ZXIC_UINT32 flow_id, + ZXIC_UINT32 td_th); + +/***********************************************************/ +/**对外接口 读取TD门限值 +* @param vport_id vport号 +* @param flow_id 流队列号 +* @param p_td_th 配置的丢弃门限值 +* @return +* @remark 无 +* @see +* @author sun @date 2023/11/17 +************************************************************/ +DPP_STATUS dpp_flow_td_th_get(DPP_PF_INFO_T* pf_info, + ZXIC_UINT32 flow_id, + ZXIC_UINT32 *p_td_th); + +/***********************************************************/ +/**对外接口 设置block值 +* @param vport_id vport号 +* @param size 配置block值 +* @return +* @remark 无 +* @see +* @author sun @date 2023/11/17 +************************************************************/ +DPP_STATUS dpp_blk_size_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 size); + +/***********************************************************/ +/**对外接口 配置全局pfc使能状态 +* @param vport_id vport号 +* @param pfc_en 使能开关 +* @return +* @remark 无 +* @see +* @author sun @date 2023/11/17 +************************************************************/ +DPP_STATUS dpp_qmu_pfc_en_set(DPP_PF_INFO_T* pf_info, + ZXIC_UINT32 pfc_en); + +/***********************************************************/ +/**对外接口 读取全局pfc使能状态 +* @param vport_id vport号 +* @param p_pfc_en 使能开关 +* @return +* @remark 无 +* @see +* @author sun @date 2023/11/17 +************************************************************/ +DPP_STATUS dpp_qmu_pfc_en_get(DPP_PF_INFO_T* pf_info, + ZXIC_UINT32 *p_pfc_en); + +/***********************************************************/ +/**对外接口 配置物理端口pfc使能状态 +* @param vport_id vport号 +* @param port_id 端口0~9 +* @param port_en 使能开关 +* @return +* @remark 无 +* @see +* @author sun @date 2023/11/17 +************************************************************/ +DPP_STATUS dpp_qmu_port_pfc_set(DPP_PF_INFO_T* pf_info, + ZXIC_UINT32 port_id, + ZXIC_UINT32 port_en); + +/***********************************************************/ +/**对外接口 读取物理端口pfc使能状态 +* @param vport_id vport号 +* @param port_id 端口0~9 +* @param p_port_en 使能开关 +* @return +* @remark 无 +* @see +* @author sun @date 2023/11/17 +************************************************************/ +DPP_STATUS dpp_qmu_port_pfc_get(DPP_PF_INFO_T* pf_info, + ZXIC_UINT32 port_id, + ZXIC_UINT32 *p_port_en); + + +/***********************************************************/ +/**对外接口 申请profile_id资源 +* @param vport_id vport号 +* @param numq 申请id个数 1 +* @param flags car类型 +* @param profile_id 限速模版号 +* @return +* @remark 无 +* @see +* @author sun @date 2023/11/17 +************************************************************/ +DPP_STATUS dpp_car_profile_id_add(DPP_PF_INFO_T* pf_info, + ZXIC_UINT32 flags, + ZXIC_UINT64 *profile_id); + +/***********************************************************/ +/**对外接口 释放profile_id资源 +* @param vport_id vport号 +* @param flags car类型 +* @param profile_id 限速模版号 +* @return +* @remark 无 +* @see +* @author sun @date 2023/11/17 +************************************************************/ +DPP_STATUS dpp_car_profile_id_delete(DPP_PF_INFO_T* pf_info, + ZXIC_UINT32 flags, + ZXIC_UINT64 profile_id); + +/***********************************************************/ +/**对外接口 配置flow_id和profile_id的绑定关系，并配置限速模板使能 +* @param vport_id vport号 +* @param car_type car模式 +* @param flow_id 队列号 +* @param drop_flag 丢弃标志 +* @param plcr_en 限速使能 +* @param profile_id 模板编号 +* +* @return +* @remark 无 +* @see +* @author sun @date 2023/11/17 +************************************************************/ +DPP_STATUS dpp_car_queue_cfg_set(DPP_PF_INFO_T* pf_info, + ZXIC_UINT32 car_type, + ZXIC_UINT32 flow_id, + ZXIC_UINT32 drop_flag, + ZXIC_UINT32 plcr_en, + ZXIC_UINT32 profile_id); + +/***********************************************************/ +/**对外接口 查询flow_id和profile_id的绑定关系 +* @param vport_id vport号 +* @param car_type car模式 +* @param flow_id 队列号 +* @param p_drop_flag 丢弃标志 +* @param p_plcr_en 限速使能 +* @param p_profile_id 模板编号 +* +* @return +* @remark 无 +* @see +* @author sun @date 2023/11/17 +************************************************************/ +DPP_STATUS dpp_car_queue_cfg_get(DPP_PF_INFO_T* pf_info, + ZXIC_UINT32 car_type, + ZXIC_UINT32 flow_id, + ZXIC_UINT32 *p_drop_flag, + ZXIC_UINT32 *p_plcr_en, + ZXIC_UINT32 *p_profile_id); + +/***********************************************************/ +/**对外接口 配置profile_id限速模版 +* @param vport_id vport号 +* @param car_type car模式 +* @param pkt_sign 限速模式0-字节;1-包 +* @param profile_id 模板编号 +* @param p_car_profile_cfg 限速参数 +* +* @return +* @remark 无 +* @see +* @author sun @date 2023/11/17 +************************************************************/ +DPP_STATUS dpp_car_profile_cfg_set(DPP_PF_INFO_T* pf_info, + ZXIC_UINT32 car_type, + ZXIC_UINT32 pkt_sign, + ZXIC_UINT32 profile_id, + ZXIC_VOID* p_car_profile_cfg); + +/***********************************************************/ +/**对外接口 查询profile_id限速模版参数 +* @param vport_id vport号 +* @param car_type car模式 +* @param pkt_sign 限速模式0-字节;1-包 +* @param profile_id 模板编号 +* @param p_car_profile_cfg 限速参数 +* +* @return +* @remark 无 +* @see +* @author sun @date 2023/11/17 +************************************************************/ +DPP_STATUS dpp_car_profile_cfg_get(DPP_PF_INFO_T* pf_info, + ZXIC_UINT32 car_type, + ZXIC_UINT32 pkt_sign, + ZXIC_UINT32 profile_id, + ZXIC_VOID* p_car_profile_cfg); + +/***********************************************************/ +/**对外接口 配置队列映射关系 +* @param dev_id 设备号 +* @param car_type car模式类型，参见STAT_CAR_TYPE_E +* @param flow_id 队列号 +* @param map_flow_id 映射队列号 +* @param map_sp 映射sp +* +* @return +* @remark 无 +* @see +* @author sun @date 2023/11/17 +************************************************************/ +DPP_STATUS dpp_car_queue_map_set(DPP_PF_INFO_T* pf_info, + ZXIC_UINT32 car_type, + ZXIC_UINT32 flow_id, + ZXIC_UINT32 map_flow_id, + ZXIC_UINT32 map_sp); + +/***********************************************************/ +/**对外接口 配置队列映射关系 +* @param dev_id 设备号 +* @param car_type car模式类型，参见STAT_CAR_TYPE_E +* @param flow_id 队列号 +* @param map_flow_id 映射队列号 +* @param map_sp 映射sp +* +* @return +* @remark 无 +* @see +* @author sun @date 2023/11/17 +************************************************************/ +DPP_STATUS dpp_car_queue_map_get(DPP_PF_INFO_T* pf_info, + ZXIC_UINT32 car_type, + ZXIC_UINT32 flow_id, + ZXIC_UINT32 *p_map_flow_id, + ZXIC_UINT32 *p_map_sp); + +#endif \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/qos/source/Kbuild.include b/src/net/drivers/net/ethernet/dinghai/en_np/qos/source/Kbuild.include new file mode 100644 index 0000000..80d2a08 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/qos/source/Kbuild.include @@ -0,0 +1,2 @@ +cur_dir := en_np/qos/source/ +src_files += $(addprefix $(cur_dir),$(notdir $(wildcard $(dinghai_root)/$(cur_dir)*.c))) \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/qos/source/dpp_drv_qos.c b/src/net/drivers/net/ethernet/dinghai/en_np/qos/source/dpp_drv_qos.c new file mode 100644 index 0000000..3ee97d6 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/qos/source/dpp_drv_qos.c @@ -0,0 +1,1100 @@ +/************************************************************** + * 文件名称 : dpp_drv_qos.c + * 文件标识 : + * 内容摘要 : QOS出口调度树资源维护 + * 其它说明 : + * 当前版本 : 1.0 + * 作 者 : sun + * 完成日期 : + ***************************************************************/ + +/****************************************************************************** + * 头文件 * + *****************************************************************************/ +#include "dpp_drv_qos.h" + +/***********************************************************/ +/**对外接口 TM资源申请 + * @param vport_id--vport号 + * @param pp_port--端口0~9 + * @param numq--申请id个数 1 + * @param level--挂接层级 + * @param flags--se_id类型 + * @param gsch_id--调度单元号 + * @return + * @remark 无 + * @see + * @author sun @date 2023/11/17 + ************************************************************/ +DPP_STATUS dpp_cosq_gsch_id_add(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 pp_port, ZXIC_UINT32 numq, ZXIC_UINT32 level, + ZXIC_UINT32 flags, ZXIC_UINT64 *p_gsch_id) +{ + DPP_STATUS ret = DPP_OK; + DPP_DEV_T dev = {0}; + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 num = 0; + ZXIC_UINT32 *gsch_id = ZXIC_NULL; + ZXIC_UINT32 gsch_id_h = 0; + ZXIC_UINT32 gsch_id_l = 0; + ZXIC_UINT64 temp_id = 0; + + ZXIC_COMM_CHECK_POINT(pf_info); + + gsch_id = (ZXIC_UINT32 *)kmalloc(G_SCH_ID_LEN, GFP_KERNEL); + ZXIC_COMM_CHECK_POINT(gsch_id); + + ret = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC_MEMORY_FREE(ret, "dpp_dev_get", gsch_id); + + ZXIC_COMM_CHECK_DEV_INDEX_MEMORY_FREE_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX, gsch_id); + ZXIC_COMM_CHECK_DEV_INDEX_MEMORY_FREE_NO_ASSERT(dev_id, pp_port, 0, DPP_TM_PP_NUM - 1, gsch_id); + ZXIC_COMM_CHECK_DEV_INDEX_MEMORY_FREE_NO_ASSERT(dev_id, level, 0, DPP_CRDT_LEVEL_MAX, gsch_id); + ZXIC_COMM_CHECK_DEV_INDEX_MEMORY_FREE_NO_ASSERT(dev_id, flags, 0, DPP_SCHE_TYPE_MAX, gsch_id); + num = ((flags == FLOW_SCHE) ? numq : 1); + + ret = dpp_agent_channel_tm_seid_request(&dev, pp_port, pf_info->vport, level, flags, num, gsch_id); + ZXIC_COMM_CHECK_RC_MEMORY_FREE(ret, "dpp_agent_channel_tm_seid_request", gsch_id); + + gsch_id_h = *(gsch_id + 1); + gsch_id_l = *gsch_id; + + temp_id = ((ZXIC_UINT64)gsch_id_h) << 32 | ((ZXIC_UINT64)gsch_id_l); + + if (DPP_OK != (ZXIC_UINT32)(temp_id >> 56)) + { + kfree(gsch_id); + return DPP_ERR; + } + + *p_gsch_id = temp_id; + kfree(gsch_id); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_cosq_gsch_id_add); + +/***********************************************************/ +/**对外接口 TM资源释放 + * @param vport_id--vport号 + * @param pp_port--端口0~9 + * @param gsch_id--调度单元号 + * @return + * @remark 无 + * @see + * @author sun @date 2023/11/17 + ************************************************************/ +DPP_STATUS dpp_cosq_gsch_id_delete(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 pp_port, ZXIC_UINT64 gsch_id) +{ + DPP_STATUS ret = DPP_OK; + DPP_DEV_T dev = {0}; + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 sche_level = 0; + ZXIC_UINT32 sche_type = 0; + ZXIC_UINT32 num = 1; + ZXIC_UINT32 se_id = 0; + + ZXIC_COMM_CHECK_POINT(pf_info); + + ret = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get"); + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pp_port, 0, DPP_TM_PP_NUM - 1); + + DPP_TM_CRDT_LEVEL_GET(gsch_id, sche_level); + DPP_TM_CRDT_TYPE_GET(gsch_id, sche_type); + DPP_TM_CRDT_SE_ID_GET(gsch_id, se_id); + + ret = dpp_agent_channel_tm_seid_release(&dev, pp_port, pf_info->vport, sche_level, sche_type, num, se_id); + ZXIC_COMM_CHECK_RC(ret, "dpp_agent_channel_tm_seid_release"); + + // if (DPP_OK != ret) + // { + // return DPP_ERR; + // } + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_cosq_gsch_id_delete); + +/***********************************************************/ +/**对外接口 读取TM根节点 + * @param vport_id--vport号 + * @param pp_port--端口0~9 + * @param gsch_id--调度单元号 + * @return + * @remark 无 + * @see + * @author sun @date 2023/11/17 + ************************************************************/ +DPP_STATUS dpp_sch_base_node_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 pp_port, ZXIC_UINT64 *p_gsch_id) +{ + DPP_STATUS ret = DPP_OK; + DPP_DEV_T dev = {0}; + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 *gsch_id = ZXIC_NULL; + ZXIC_UINT32 gsch_id_h = 0; + ZXIC_UINT32 gsch_id_l = 0; + ZXIC_UINT64 temp_id = 0; + + ZXIC_COMM_CHECK_POINT(pf_info); + + gsch_id = (ZXIC_UINT32 *)kmalloc(G_SCH_ID_LEN, GFP_KERNEL); + ZXIC_COMM_CHECK_POINT(gsch_id); + + ret = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC_MEMORY_FREE(ret, "dpp_dev_get", gsch_id); + + ZXIC_COMM_CHECK_DEV_INDEX_MEMORY_FREE_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX, gsch_id); + ZXIC_COMM_CHECK_DEV_INDEX_MEMORY_FREE_NO_ASSERT(dev_id, pp_port, 0, DPP_TM_PP_NUM - 1, gsch_id); + + ret = dpp_agent_channel_tm_base_node_get(&dev, pp_port, pf_info->vport, gsch_id); + ZXIC_COMM_CHECK_RC_MEMORY_FREE(ret, "dpp_agent_channel_tm_base_node_get", gsch_id); + + gsch_id_h = *(gsch_id + 1); + gsch_id_l = *gsch_id; + + temp_id = ((ZXIC_UINT64)gsch_id_h) << 32 | ((ZXIC_UINT64)gsch_id_l); + if (DPP_OK != (ZXIC_UINT32)(temp_id >> 56)) + { + kfree(gsch_id); + return DPP_ERR; + } + + *p_gsch_id = temp_id; + kfree(gsch_id); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_sch_base_node_get); + +/***********************************************************/ +/**对外接口 配置se->pp->dev挂接关系 + * @param vport_id--vport号 + * @param se_id--调度器号 + * @param pp_id-端口号 + * @param weight-权重1 + * @param sp_mapping-优先级0-7 + * @return + * @remark 无 + * @see + * @author sun @date 2023/11/17 + ************************************************************/ +DPP_STATUS dpp_crdt_se_pp_link_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 se_id, ZXIC_UINT32 pp_id, ZXIC_UINT32 weight, + ZXIC_UINT32 sp_mapping) +{ + DPP_STATUS ret = DPP_OK; + DPP_DEV_T dev = {0}; + ZXIC_UINT32 dev_id = 0; + + ZXIC_COMM_CHECK_POINT(pf_info); + + ret = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get"); + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, se_id, 0, DPP_ETM_FQSPWFQ_NUM - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pp_id, 0, DPP_TM_PP_NUM - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, weight, 0, DPP_TM_SCH_WEIGHT_MAX); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, sp_mapping, DPP_TM_SCH_SP_0, DPP_TM_SCH_SP_8); + + ret = dpp_tm_crdt_se_pp_link_set(&dev, se_id, pp_id, weight, sp_mapping); + ZXIC_COMM_CHECK_RC(ret, "dpp_tm_crdt_se_pp_link_set"); + + return ret; +} +EXPORT_SYMBOL(dpp_crdt_se_pp_link_set); + +/***********************************************************/ +/**对外接口 配置se->se层次化挂接关系 + * @param vport_id--vport号 + * @param se_id--调度器号 + * @param se_linkid--上级调度器号 + * @param se_weight -权重 + * @param se_sp-优先级0-7 + * @return + * @remark 无 + * @see + * @author sun @date 2023/11/17 + ************************************************************/ +DPP_STATUS dpp_crdt_se_link_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 se_id, ZXIC_UINT32 se_linkid, ZXIC_UINT32 se_weight, + ZXIC_UINT32 se_sp) +{ + DPP_STATUS ret = DPP_OK; + DPP_DEV_T dev = {0}; + ZXIC_UINT32 dev_id = 0; + + ZXIC_COMM_CHECK_POINT(pf_info); + + ret = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get"); + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, se_id, 0, DPP_ETM_FQSPWFQ_NUM - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, se_linkid, 0, DPP_ETM_FQSPWFQ_NUM - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, se_weight, 0, DPP_TM_SCH_WEIGHT_MAX); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, se_sp, DPP_TM_SCH_SP_0, DPP_TM_SCH_SP_8); + + ret = dpp_tm_crdt_se_link_set(&dev, se_id, se_linkid, se_weight, se_sp); + ZXIC_COMM_CHECK_RC(ret, "dpp_tm_crdt_se_link_set"); + + return ret; +} +EXPORT_SYMBOL(dpp_crdt_se_link_set); + +/***********************************************************/ +/**对外接口 配置flow级流队列挂接关系 + * @param vport_id--vport号 + * @param flow_id--0~4095 + * @param c_linkid--c桶se_id + * @param c_weight--c桶权重 + * @param c_sp--c桶优先级 + * @param mode--0-单桶 1-双桶 + * @param e_linkid--e桶se_id + * @param e_weight--e桶权重 + * @param e_sp--e桶优先级 + * @return + * @remark 无 + * @see + * @author sun @date 2023/11/17 + ************************************************************/ +DPP_STATUS dpp_crdt_flow_link_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 flow_id, ZXIC_UINT32 c_linkid, ZXIC_UINT32 c_weight, + ZXIC_UINT32 c_sp, ZXIC_UINT32 mode, ZXIC_UINT32 e_linkid, ZXIC_UINT32 e_weight, + ZXIC_UINT32 e_sp) +{ + DPP_STATUS ret = DPP_OK; + DPP_DEV_T dev = {0}; + ZXIC_UINT32 dev_id = 0; + + ZXIC_COMM_CHECK_POINT(pf_info); + + ret = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get"); + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX); + + ret = dpp_tm_crdt_flow_link_set(&dev, flow_id, c_linkid, c_weight, c_sp, mode, e_linkid, e_weight, e_sp); + ZXIC_COMM_CHECK_RC(ret, "dpp_tm_crdt_flow_link_set"); + + return ret; +} +EXPORT_SYMBOL(dpp_crdt_flow_link_set); + +/***********************************************************/ +/**对外接口 删除flow级流队列挂接关系 + * @param vport_id--vport号 + * @param id_s--起始flowid + * @param id_e--终止flowid + * @return + * @remark 无 + * @see + * @author sun @date 2023/11/17 + ************************************************************/ +DPP_STATUS dpp_crdt_del_flow_link_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 id_s, ZXIC_UINT32 id_e) +{ + DPP_STATUS ret = DPP_OK; + DPP_DEV_T dev = {0}; + ZXIC_UINT32 dev_id = 0; + + ZXIC_COMM_CHECK_POINT(pf_info); + + ret = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get"); + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, id_s, 0, DPP_ETM_CRDT_NUM); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, id_e, 0, DPP_ETM_CRDT_NUM); + + ret = dpp_tm_crdt_del_flow_link_set(&dev, id_s, id_e); + ZXIC_COMM_CHECK_RC(ret, "dpp_tm_crdt_del_flow_link_set"); + + return ret; +} +EXPORT_SYMBOL(dpp_crdt_del_flow_link_set); + +/***********************************************************/ +/**对外接口 删除调度器挂接关系 + * @param vport_id--vport号 + * @param id_s--起始seid + * @param id_e--终止seid + * @return + * @remark 无 + * @see + * @author sun @date 2023/11/17 + ************************************************************/ +DPP_STATUS dpp_crdt_del_se_link_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 id_s, ZXIC_UINT32 id_e) +{ + DPP_STATUS ret = DPP_OK; + DPP_DEV_T dev = {0}; + ZXIC_UINT32 dev_id = 0; + + ZXIC_COMM_CHECK_POINT(pf_info); + + ret = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get"); + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, id_s, 0, DPP_ETM_FQSPWFQ_NUM); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, id_e, 0, DPP_ETM_FQSPWFQ_NUM); + + ret = dpp_tm_crdt_del_se_link_set(&dev, id_s, id_e); + ZXIC_COMM_CHECK_RC(ret, "dpp_tm_crdt_del_se_link_set"); + + return ret; +} +EXPORT_SYMBOL(dpp_crdt_del_se_link_set); + +/***********************************************************/ +/**对外接口 配置端口级整形 + * @param vport_id--vport号 + * @param pp_port--端口0~9 + * @param cir 单位Kb + * @param cbs 单位KB + * @param c_en c桶使能 + * @return + * @remark 无 + * @see + * @author sun @date 2023/11/17 + ************************************************************/ +DPP_STATUS dpp_port_shape_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 pp_port, ZXIC_UINT32 cir, ZXIC_UINT32 cbs, + ZXIC_UINT32 c_en) +{ + DPP_STATUS ret = DPP_OK; + DPP_DEV_T dev = {0}; + ZXIC_UINT32 dev_id = 0; + + ZXIC_COMM_CHECK_POINT(pf_info); + + ret = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get"); + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pp_port, 0, DPP_TM_PP_NUM - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, c_en, 0, 1); + + ret = dpp_tm_shape_pp_para_wr(&dev, pp_port, cir, cbs, c_en); + ZXIC_COMM_CHECK_RC(ret, "dpp_tm_shape_pp_para_wr"); + + return ret; +} +EXPORT_SYMBOL(dpp_port_shape_set); + +/***********************************************************/ +/**对外接口 读取端口级整形 + * @param vport_id--vport号 + * @param pp_port--端口0~9 + * @param p_para 整形信息:cir/cbs/en + * @return + * @remark 无 + * @see + * @author sun @date 2023/11/17 + ************************************************************/ +DPP_STATUS dpp_port_shape_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 pp_port, DPP_TM_SHAPE_PP_PARA_T *p_para) +{ + DPP_STATUS ret = DPP_OK; + DPP_DEV_T dev = {0}; + ZXIC_UINT32 dev_id = 0; + DPP_TM_SHAPE_PP_PARA_T pp_shap_para = {0}; + + ZXIC_COMM_CHECK_POINT(pf_info); + + ret = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get"); + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pp_port, 0, DPP_TM_PP_NUM - 1); + + ret = dpp_tm_shape_pp_para_get(&dev, pp_port, &pp_shap_para); + ZXIC_COMM_CHECK_RC(ret, "dpp_tm_shape_pp_para_get"); + + p_para->c_en = pp_shap_para.c_en; + p_para->cir = pp_shap_para.cir; + p_para->cbs = pp_shap_para.cbs; + + return ret; +} +EXPORT_SYMBOL(dpp_port_shape_get); + +/***********************************************************/ +/**对外接口 配置调度器整形 + * @param vport_id vport号 + * @param se_id 调度器编号号 + * @param pir pir总速率，单位Kb，范围同cir + * @param pbs pbs总桶深，单位KB，范围同cbs + * @param db_en 整形模式，0-单桶，1-双桶，仅FQ8/WFQ8有效 + * @param cir 调度器cir速率，单位Kb + * @param cbs 调度器cbs桶深，单位KB + * 注：cbs=0 表示关闭整形,即不限速 + * @return + * @remark 无 + * @see + * @author sun @date 2023/11/17 + ************************************************************/ +DPP_STATUS dpp_se_shape_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 se_id, ZXIC_UINT32 pir, ZXIC_UINT32 pbs, + ZXIC_UINT32 db_en, ZXIC_UINT32 cir, ZXIC_UINT32 cbs) +{ + DPP_STATUS ret = DPP_OK; + DPP_DEV_T dev = {0}; + ZXIC_UINT32 dev_id = 0; + + ZXIC_COMM_CHECK_POINT(pf_info); + + ret = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get"); + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX); + + ret = dpp_tm_shape_se_para_set(&dev, se_id, pir, pbs, db_en, cir, cbs); + ZXIC_COMM_CHECK_RC(ret, "dpp_tm_shape_se_para_set"); + + return ret; +} +EXPORT_SYMBOL(dpp_se_shape_set); + +/***********************************************************/ +/**对外接口 配置flow整形 + * @param vport_id vport号 + * @param flow_id 流队列号 + * @param cir cir速率，单位Kb + * @param cbs cbs桶深，单位KB + * 注：cbs=0 表示关闭整形,即不限速 + * @param db_en 双桶整形使能，0-单桶，1-双桶 + * @param eir eir速率，单位Kb + * @param ebs ebs桶深，单位KB + * @return + * @remark 无 + * @see + * @author sun @date 2023/11/17 + ************************************************************/ +DPP_STATUS dpp_flow_shape_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 flow_id, ZXIC_UINT32 cir, ZXIC_UINT32 cbs, + ZXIC_UINT32 db_en, ZXIC_UINT32 eir, ZXIC_UINT32 ebs) +{ + DPP_STATUS ret = DPP_OK; + DPP_DEV_T dev = {0}; + ZXIC_UINT32 dev_id = 0; + + ZXIC_COMM_CHECK_POINT(pf_info); + + ret = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get"); + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX); + + ret = dpp_tm_shape_flow_para_set(&dev, flow_id, cir, cbs, db_en, eir, ebs); + ZXIC_COMM_CHECK_RC(ret, "dpp_tm_shape_flow_para_set"); + + return ret; +} +EXPORT_SYMBOL(dpp_flow_shape_set); + +/***********************************************************/ +/**对外接口 配置流队列挂接到端口号 + * @param vport_id vport号 + * @param flow_id 流队列号 + * @param port 端口0~9 + * @return + * @remark 无 + * @see + * @author sun @date 2023/11/17 + ************************************************************/ +DPP_STATUS dpp_flow_map_port_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 flow_id, ZXIC_UINT32 port) +{ + DPP_STATUS ret = DPP_OK; + DPP_DEV_T dev = {0}; + ZXIC_UINT32 dev_id = 0; + + ZXIC_COMM_CHECK_POINT(pf_info); + + ret = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get"); + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX); + + ret = dpp_tm_cgavd_q_map_pp_set(&dev, flow_id, port); + ZXIC_COMM_CHECK_RC(ret, "dpp_tm_cgavd_q_map_pp_set"); + + return ret; +} +EXPORT_SYMBOL(dpp_flow_map_port_set); + +/***********************************************************/ +/**对外接口 读取流队列挂接的端口号 + * @param vport_id vport号 + * @param flowid 流队列号 + * @param port 端口0~9 + * @return + * @remark 无 + * @see + * @author sun @date 2023/11/17 + ************************************************************/ +DPP_STATUS dpp_flow_map_port_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 flow_id, ZXIC_UINT32 *p_port) +{ + DPP_STATUS ret = DPP_OK; + DPP_DEV_T dev = {0}; + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 pp_id = 0; + + ZXIC_COMM_CHECK_POINT(pf_info); + + ret = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get"); + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX); + + ret = dpp_tm_cgavd_q_map_pp_get(&dev, flow_id, &pp_id); + ZXIC_COMM_CHECK_RC(ret, "dpp_tm_cgavd_q_map_pp_get"); + + *p_port = pp_id; + + return ret; +} +EXPORT_SYMBOL(dpp_flow_map_port_get); + +/***********************************************************/ +/**对外接口 配置TD门限值 + * @param vport_id vport号 + * @param flow_id 流队列号 + * @param td_th 配置的丢弃门限值 + * @return + * @remark 无 + * @see + * @author sun @date 2023/11/17 + ************************************************************/ +DPP_STATUS dpp_flow_td_th_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 flow_id, ZXIC_UINT32 td_th) +{ + DPP_STATUS ret = DPP_OK; + DPP_DEV_T dev = {0}; + ZXIC_UINT32 dev_id = 0; + + ZXIC_COMM_CHECK_POINT(pf_info); + + ret = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get"); + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX); + + ret = dpp_tm_cgavd_td_th_set(&dev, QUEUE_LEVEL, flow_id, td_th); + ZXIC_COMM_CHECK_RC(ret, "dpp_tm_cgavd_td_th_set"); + + return ret; +} +EXPORT_SYMBOL(dpp_flow_td_th_set); + +/***********************************************************/ +/**对外接口 读取TD门限值 + * @param vport_id vport号 + * @param flow_id 流队列号 + * @param p_td_th 配置的丢弃门限值 + * @return + * @remark 无 + * @see + * @author sun @date 2023/11/17 + ************************************************************/ +DPP_STATUS dpp_flow_td_th_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 flow_id, ZXIC_UINT32 *p_td_th) +{ + DPP_STATUS ret = DPP_OK; + DPP_DEV_T dev = {0}; + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 td_th = 0; + + ZXIC_COMM_CHECK_POINT(pf_info); + + ret = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get"); + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX); + + ret = dpp_tm_cgavd_td_th_get(&dev, QUEUE_LEVEL, flow_id, &td_th); + ZXIC_COMM_CHECK_RC(ret, "dpp_tm_cgavd_td_th_get"); + + *p_td_th = td_th; + + return ret; +} +EXPORT_SYMBOL(dpp_flow_td_th_get); + +/***********************************************************/ +/**对外接口 设置block值 +* @param vport_id vport号 +* @param size 配置block值 +* @return +* @remark 无 +* @see +* @author sun @date 2023/11/17 +************************************************************/ +DPP_STATUS dpp_blk_size_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 size) +{ + DPP_STATUS ret = DPP_OK; + DPP_DEV_T dev = {0}; + ZXIC_UINT32 dev_id = 0; + + ZXIC_COMM_CHECK_POINT(pf_info); + + ret = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get"); + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX); + ret = dpp_tm_cfgmt_blk_size_set(&dev, size); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, ret, "dpp_tm_cfgmt_blk_size_set"); + + return ret; +} +EXPORT_SYMBOL(dpp_blk_size_set); + +/***********************************************************/ +/**对外接口 配置全局pfc使能状态 + * @param vport_id vport号 + * @param pfc_en 使能开关 + * @return + * @remark 无 + * @see + * @author sun @date 2023/11/17 + ************************************************************/ +DPP_STATUS dpp_qmu_pfc_en_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 pfc_en) +{ + DPP_STATUS ret = DPP_OK; + DPP_DEV_T dev = {0}; + ZXIC_UINT32 dev_id = 0; + + ZXIC_COMM_CHECK_POINT(pf_info); + + ret = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get"); + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pfc_en, 0, 1); + + ret = dpp_tm_qmu_pfc_en_set(&dev, pfc_en); + ZXIC_COMM_CHECK_RC(ret, "dpp_tm_qmu_pfc_en_set"); + + return ret; +} +EXPORT_SYMBOL(dpp_qmu_pfc_en_set); + +/***********************************************************/ +/**对外接口 读取全局pfc使能状态 + * @param vport_id vport号 + * @param p_pfc_en 使能开关 + * @return + * @remark 无 + * @see + * @author sun @date 2023/11/17 + ************************************************************/ +DPP_STATUS dpp_qmu_pfc_en_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 *p_pfc_en) +{ + DPP_STATUS ret = DPP_OK; + DPP_DEV_T dev = {0}; + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 pfc_en = 0; + + ZXIC_COMM_CHECK_POINT(pf_info); + + ret = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get"); + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pfc_en, 0, 1); + + ret = dpp_tm_qmu_pfc_en_get(&dev, &pfc_en); + ZXIC_COMM_CHECK_RC(ret, "dpp_tm_qmu_pfc_en_set"); + + *p_pfc_en = pfc_en; + + return ret; +} +EXPORT_SYMBOL(dpp_qmu_pfc_en_get); + +/***********************************************************/ +/**对外接口 配置物理端口pfc使能状态 + * @param vport_id vport号 + * @param port_id 端口0~9 + * @param port_en 使能开关 + * @return + * @remark 无 + * @see + * @author sun @date 2023/11/17 + ************************************************************/ +DPP_STATUS dpp_qmu_port_pfc_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 port_id, ZXIC_UINT32 port_en) +{ + DPP_STATUS ret = DPP_OK; + DPP_DEV_T dev = {0}; + ZXIC_UINT32 dev_id = 0; + + ZXIC_COMM_CHECK_POINT(pf_info); + + ret = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get"); + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, port_id, 0, DPP_TM_PP_NUM - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, port_en, 0, 1); + + ret = dpp_tm_qmu_port_pfc_make_set(&dev, port_id, port_en); + ZXIC_COMM_CHECK_RC(ret, "dpp_tm_qmu_port_pfc_make_set"); + + return ret; +} +EXPORT_SYMBOL(dpp_qmu_port_pfc_set); + +/***********************************************************/ +/**对外接口 读取物理端口pfc使能状态 + * @param vport_id vport号 + * @param port_id 端口0~9 + * @param p_port_en 使能开关 + * @return + * @remark 无 + * @see + * @author sun @date 2023/11/17 + ************************************************************/ +DPP_STATUS dpp_qmu_port_pfc_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 port_id, ZXIC_UINT32 *p_port_en) +{ + DPP_STATUS ret = DPP_OK; + DPP_DEV_T dev = {0}; + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 port_en = 0; + + ZXIC_COMM_CHECK_POINT(pf_info); + + ret = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get"); + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, port_id, 0, DPP_TM_PP_NUM - 1); + + ret = dpp_tm_qmu_port_pfc_make_get(&dev, port_id, &port_en); + ZXIC_COMM_CHECK_RC(ret, "dpp_tm_qmu_port_pfc_make_get"); + + *p_port_en = port_en; + + return ret; +} +EXPORT_SYMBOL(dpp_qmu_port_pfc_get); + + +/***********************************************************/ +/**对外接口 申请profile_id资源 +* @param vport_id vport号 +* @param flags car类型 +* @param p_profile_id 限速模版号 +* @return +* @remark 无 +* @see +* @author sun @date 2023/11/17 +************************************************************/ +DPP_STATUS dpp_car_profile_id_add(DPP_PF_INFO_T* pf_info, + ZXIC_UINT32 flags, + ZXIC_UINT64 *p_profile_id) +{ + DPP_STATUS ret = DPP_OK; + DPP_DEV_T dev = {0}; + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 *profile_id = ZXIC_NULL; + ZXIC_UINT32 profile_id_h = 0; + ZXIC_UINT32 profile_id_l = 0; + ZXIC_UINT64 temp_profile_id = 0; + + ZXIC_COMM_CHECK_POINT(pf_info); + + profile_id = (ZXIC_UINT32 *)kmalloc(G_PROFILE_ID_LEN, GFP_KERNEL); + ZXIC_COMM_CHECK_POINT(profile_id); + + ret = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC_MEMORY_FREE(ret, "dpp_dev_get", profile_id); + + ZXIC_COMM_CHECK_DEV_INDEX_MEMORY_FREE_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX, profile_id); + ZXIC_COMM_CHECK_DEV_INDEX_MEMORY_FREE_NO_ASSERT(dev_id, flags, 0, CAR_TYPE_MAX, profile_id); + + ret = dpp_agent_channel_plcr_profileid_request(&dev, pf_info->vport, flags, profile_id); + ZXIC_COMM_CHECK_RC_MEMORY_FREE(ret, "dpp_agent_channel_plcr_profileid_request", profile_id); + + profile_id_h = *(profile_id + 1); + profile_id_l = *profile_id; + + temp_profile_id = ((ZXIC_UINT64)profile_id_l) << 32 | ((ZXIC_UINT64)profile_id_h); + + if (DPP_OK != (ZXIC_UINT32)(temp_profile_id >> 56)) + { + kfree(profile_id); + return DPP_ERR; + } + + *p_profile_id = temp_profile_id; + kfree(profile_id); + + return ret; +} +EXPORT_SYMBOL(dpp_car_profile_id_add); + +/***********************************************************/ +/**对外接口 释放profile_id资源 +* @param vport_id vport号 +* @param flags car类型 +* @param profile_id 限速模版号 + * @return + * @remark 无 + * @see + * @author sun @date 2023/11/17 + ************************************************************/ +DPP_STATUS dpp_car_profile_id_delete(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 flags, ZXIC_UINT64 profile_id) +{ + DPP_STATUS ret = DPP_OK; + DPP_DEV_T dev = {0}; + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 profileid = 0; + + ZXIC_COMM_CHECK_POINT(pf_info); + + ret = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get"); + + DPP_CAR_PROFILE_ID_GET(profile_id, profileid); + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, flags, 0, CAR_TYPE_MAX); + + ret = dpp_agent_channel_plcr_profileid_release(&dev, pf_info->vport, flags, profileid); + ZXIC_COMM_CHECK_RC(ret, "dpp_agent_channel_plcr_profileid_release"); + + // if (DPP_OK != ret) + // { + // return DPP_ERR; + // } + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_car_profile_id_delete); + +/***********************************************************/ +/**对外接口 配置flow_id和profile_id的绑定关系，并配置限速模板使能 +* @param vport_id vport号 +* @param car_type car模式 +* @param flow_id 队列号 +* @param drop_flag 丢弃标志 +* @param plcr_en 限速使能 +* @param profile_id 模板编号 +* +* @return +* @remark 无 +* @see +* @author sun @date 2023/11/17 +************************************************************/ +DPP_STATUS dpp_car_queue_cfg_set(DPP_PF_INFO_T* pf_info, + ZXIC_UINT32 car_type, + ZXIC_UINT32 flow_id, + ZXIC_UINT32 drop_flag, + ZXIC_UINT32 plcr_en, + ZXIC_UINT32 profile_id) +{ + DPP_STATUS ret = DPP_OK; + DPP_DEV_T dev = {0}; + ZXIC_UINT32 dev_id = 0; + + ZXIC_COMM_CHECK_POINT(pf_info); + + ret = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get"); + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX); + + ret = dpp_stat_car_queue_cfg_set(&dev, car_type, flow_id, drop_flag, plcr_en, profile_id); + ZXIC_COMM_CHECK_RC(ret, "dpp_stat_car_queue_cfg_set"); + + return ret; + +} +EXPORT_SYMBOL(dpp_car_queue_cfg_set); + +/***********************************************************/ +/**对外接口 查询flow_id和profile_id的绑定关系 +* @param vport_id vport号 +* @param car_type car模式 +* @param flow_id 队列号 +* @param p_drop_flag 丢弃标志 +* @param p_plcr_en 限速使能 +* @param p_profile_id 模板编号 +* +* @return +* @remark 无 +* @see +* @author sun @date 2023/11/17 +************************************************************/ +DPP_STATUS dpp_car_queue_cfg_get(DPP_PF_INFO_T* pf_info, + ZXIC_UINT32 car_type, + ZXIC_UINT32 flow_id, + ZXIC_UINT32 *p_drop_flag, + ZXIC_UINT32 *p_plcr_en, + ZXIC_UINT32 *p_profile_id) +{ + DPP_STATUS ret = DPP_OK; + DPP_DEV_T dev = {0}; + ZXIC_UINT32 dev_id = 0; + + ZXIC_COMM_CHECK_POINT(pf_info); + + ZXIC_COMM_CHECK_DEV_POINT(0, p_drop_flag); + ZXIC_COMM_CHECK_DEV_POINT(0, p_plcr_en); + ZXIC_COMM_CHECK_DEV_POINT(0, p_profile_id); + + ret = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get"); + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX); + + ret = dpp_stat_car_queue_cfg_get(&dev, car_type, flow_id, p_drop_flag, p_plcr_en, p_profile_id); + ZXIC_COMM_CHECK_RC(ret, "dpp_stat_car_queue_cfg_get"); + + return ret; +} +EXPORT_SYMBOL(dpp_car_queue_cfg_get); + +/***********************************************************/ +/**对外接口 配置profile_id限速模版 +* @param dev_id +* @param car_type +* @param pkt_sign +* @param profile_id +* @param p_car_profile_cfg +* +* @return +* @remark 无 +* @see +* @author sun @date 2023/11/17 +************************************************************/ +DPP_STATUS dpp_car_profile_cfg_set(DPP_PF_INFO_T* pf_info, + ZXIC_UINT32 car_type, + ZXIC_UINT32 pkt_sign, + ZXIC_UINT32 profile_id, + ZXIC_VOID* p_car_profile_cfg) +{ + DPP_STATUS ret = DPP_OK; + DPP_DEV_T dev = {0}; + ZXIC_UINT32 dev_id = 0; + + ZXIC_COMM_CHECK_POINT(pf_info); + + ret = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get"); + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_car_profile_cfg); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX); + + ret = dpp_stat_car_profile_cfg_set(&dev, car_type, pkt_sign, profile_id, p_car_profile_cfg); + ZXIC_COMM_CHECK_RC(ret, "dpp_stat_car_queue_cfg_set"); + + return ret; +} +EXPORT_SYMBOL(dpp_car_profile_cfg_set); + +/***********************************************************/ +/**对外接口 查询profile_id限速模版参数 +* @param vport_id vport号 +* @param car_type car模式 +* @param pkt_sign 限速模式0-字节;1-包 +* @param profile_id 模板编号 +* @param p_car_profile_cfg 限速参数 +* +* @return +* @remark 无 +* @see +* @author sun @date 2023/11/17 +************************************************************/ +DPP_STATUS dpp_car_profile_cfg_get(DPP_PF_INFO_T* pf_info, + ZXIC_UINT32 car_type, + ZXIC_UINT32 pkt_sign, + ZXIC_UINT32 profile_id, + ZXIC_VOID* p_car_profile_cfg) +{ + DPP_STATUS ret = DPP_OK; + DPP_DEV_T dev = {0}; + ZXIC_UINT32 dev_id = 0; + + ZXIC_COMM_CHECK_POINT(pf_info); + + ret = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get"); + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_car_profile_cfg); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX); + + ret = dpp_stat_car_profile_cfg_get(&dev, car_type, pkt_sign, profile_id, p_car_profile_cfg); + ZXIC_COMM_CHECK_RC(ret, "dpp_stat_car_profile_cfg_get"); + + return ret; +} +EXPORT_SYMBOL(dpp_car_profile_cfg_get); + +/***********************************************************/ +/**对外接口 配置队列映射关系 +* @param dev_id 设备号 +* @param car_type car模式类型，参见STAT_CAR_TYPE_E +* @param flow_id 队列号 +* @param map_flow_id 映射队列号 +* @param map_sp 映射sp +* +* @return +* @remark 无 +* @see +* @author sun @date 2023/11/17 +************************************************************/ +DPP_STATUS dpp_car_queue_map_set(DPP_PF_INFO_T* pf_info, + ZXIC_UINT32 car_type, + ZXIC_UINT32 flow_id, + ZXIC_UINT32 map_flow_id, + ZXIC_UINT32 map_sp) +{ + DPP_STATUS ret = DPP_OK; + DPP_DEV_T dev = {0}; + ZXIC_UINT32 dev_id = 0; + + ZXIC_COMM_CHECK_POINT(pf_info); + + ret = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get"); + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX); + + ret = dpp_stat_car_queue_map_set(&dev, car_type, flow_id, map_flow_id, map_sp); + ZXIC_COMM_CHECK_RC(ret, "dpp_stat_car_queue_map_set"); + + return ret; +} +EXPORT_SYMBOL(dpp_car_queue_map_set); + +/***********************************************************/ +/**对外接口 配置队列映射关系 +* @param dev_id 设备号 +* @param car_type car模式类型，参见STAT_CAR_TYPE_E +* @param flow_id 队列号 +* @param map_flow_id 映射队列号 +* @param map_sp 映射sp +* +* @return +* @remark 无 +* @see +* @author sun @date 2023/11/17 +************************************************************/ +DPP_STATUS dpp_car_queue_map_get(DPP_PF_INFO_T* pf_info, + ZXIC_UINT32 car_type, + ZXIC_UINT32 flow_id, + ZXIC_UINT32 *p_map_flow_id, + ZXIC_UINT32 *p_map_sp) +{ + DPP_STATUS ret = DPP_OK; + DPP_DEV_T dev = {0}; + ZXIC_UINT32 dev_id = 0; + + ZXIC_COMM_CHECK_POINT(pf_info); + + ret = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get"); + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_map_flow_id); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_map_sp); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX); + + ret = dpp_stat_car_queue_map_get(&dev, car_type, flow_id, p_map_flow_id, p_map_sp); + ZXIC_COMM_CHECK_RC(ret, "dpp_stat_car_queue_map_get"); + + return ret; +} +EXPORT_SYMBOL(dpp_car_queue_map_get); diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/Kbuild.include b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/Kbuild.include new file mode 100644 index 0000000..71babb3 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/Kbuild.include @@ -0,0 +1,4 @@ +cur_dir := en_np/sdk/ +subdirs := source/ +src_files += +include $(foreach subdir, $(subdirs), $(dinghai_root)/$(cur_dir)$(subdir)/Kbuild.include) \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_apt_se_api.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_apt_se_api.h new file mode 100644 index 0000000..8094f4a --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_apt_se_api.h @@ -0,0 +1,303 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_apt_se_api.h +* 文件标识 : +* 内容摘要 : SE适配业务接口数据结构和函数声明 +* 其它说明 : +* 当前版本 : +* 作 者 : chenqin00181032 +* 完成日期 : 2022/02/22 +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ + +#ifndef _DPP_APT_SE_API_H_ +#define _DPP_APT_SE_API_H_ + +#include "zxic_common.h" + +#if ZXIC_REAL("header file") +#include "dpp_dev.h" +#include "dpp_se_api.h" +#include "dpp_etcam.h" +#include "dpp_se.h" +#endif + + +#if ZXIC_REAL("data struct define") +typedef ZXIC_UINT32 (*DPP_APT_ACL_ENTRY_SET_FUNC)(ZXIC_VOID *pData,DPP_ACL_ENTRY_EX_T *aclEntry); +typedef ZXIC_UINT32 (*DPP_APT_ACL_ENTRY_GET_FUNC)(ZXIC_VOID *pData,DPP_ACL_ENTRY_EX_T *aclEntry); + +typedef ZXIC_UINT32 (*DPP_APT_ERAM_SET_FUNC)(ZXIC_VOID *pData,ZXIC_UINT32 buf[4]); +typedef ZXIC_UINT32 (*DPP_APT_ERAM_GET_FUNC)(ZXIC_VOID *pData,ZXIC_UINT32 buf[4]); + +typedef ZXIC_UINT32 (*DPP_APT_HASH_ENTRY_SET_FUNC)(ZXIC_VOID *pData,DPP_HASH_ENTRY *pEntry); +typedef ZXIC_UINT32 (*DPP_APT_HASH_ENTRY_GET_FUNC)(ZXIC_VOID *pData,DPP_HASH_ENTRY *pEntry); + +typedef ZXIC_UINT32 (*DPP_APT_LPM_ENTRY_SET_FUNC)(ZXIC_VOID *pData,ZXIC_VOID *pEntry); +typedef ZXIC_UINT32 (*DPP_APT_LPM_ENTRY_GET_FUNC)(ZXIC_VOID *pData,ZXIC_VOID *pEntry); + +typedef ZXIC_UINT32 (*DPP_APT_DDR_SET_FUNC)(ZXIC_VOID *pData,ZXIC_UINT32 buf[DPP_DIR_TBL_BUF_MAX_NUM]); +typedef ZXIC_UINT32 (*DPP_APT_DDR_GET_FUNC)(ZXIC_VOID *pData,ZXIC_UINT32 buf[DPP_DIR_TBL_BUF_MAX_NUM]); + +typedef struct dpp_apt_eram_table_t +{ + ZXIC_UINT32 sdtNo; /** <@brief sdt no 0~255 */ + DPP_SDTTBL_ERAM_T eRamSdt; /** <@brief eRam属性*/ + ZXIC_UINT32 opr_mode; /**cpu读写位宽模式DPP_ERAM128_OPR_MODE_E 0:128b 1:64b 2:1b 3:32b <@*/ + ZXIC_UINT32 rd_mode; /*读清模式DPP_ERAM128_RD_CLR_MODE_E，0:正常读 1:读清模式*/ + DPP_APT_ERAM_SET_FUNC eram_set_func; /** <@brief 结构体转换为码流 */ + DPP_APT_ERAM_GET_FUNC eram_get_func; /** <@brief 码流转换为结构体 */ +} DPP_APT_ERAM_TABLE_T; + +typedef struct dpp_apt_ddr_table_t +{ + ZXIC_UINT32 sdtNo; /** <@brief sdt no 0~255 */ + DPP_SDTTBL_DDR3_T eDdrSdt; /** <@brief DDR属性*/ + ZXIC_UINT32 ddr_table_depth;/** <@brief DDR表项深度，单位与读写模式一致*/ + DPP_APT_DDR_SET_FUNC ddr_set_func; /** <@brief 结构体转换为码流 */ + DPP_APT_DDR_GET_FUNC ddr_get_func; /** <@brief 码流转换为结构体 */ +} DPP_APT_DDR_TABLE_T; + +typedef struct dpp_apt_acl_res_t +{ + ZXIC_UINT32 pri_mode; /** <@brief1：显式优先级，2：隐式优先级，以条目下发顺序作为优先级，3：用户指定每个条目在tcam中的存放索引*/ + ZXIC_UINT32 entry_num; /** <@brief 可配置的条目数*/ + ZXIC_UINT32 block_num; /** <@brief 最大8个 */ + ZXIC_UINT32 block_index[DPP_ETCAM_BLOCK_NUM]; /** <@brief 0~7 */ +} DPP_APT_ACL_RES_T; + +typedef struct dpp_apt_acl_table_t +{ + ZXIC_UINT32 sdtNo; /** <@brief sdt no 0~255 */ + DPP_SDTTBL_ETCAM_T aclSdt; /** <@brief acl属性*/ + DPP_APT_ACL_RES_T aclRes; /** <@brief acl资源*/ + DPP_APT_ACL_ENTRY_SET_FUNC acl_set_func; /** <@brief 结构体转换为码流 */ + DPP_APT_ACL_ENTRY_GET_FUNC acl_get_func; /** <@brief 码流转换为结构体 */ +} DPP_APT_ACL_TABLE_T; + +typedef struct dpp_apt_hash_table_t +{ + ZXIC_UINT32 sdtNo; /** <@brief sdt no 0~255 */ + DPP_SDTTBL_HASH_T hashSdt; /** <@brief hash sdt属性*/ + ZXIC_UINT32 tbl_flag; /**< @brief 业务表初始化标记（bit0：老化保活置位使能，bit1：硬件学习使能，bit2：微码写表使能）*/ + DPP_APT_HASH_ENTRY_SET_FUNC hash_set_func; /** <@brief 结构体转换为码流,转换时预留一个字节，从第1字节开始填充 */ + DPP_APT_HASH_ENTRY_GET_FUNC hash_get_func; /** <@brief 码流转换为结构体 */ +} DPP_APT_HASH_TABLE_T; + +typedef struct dpp_apt_hash_func_res_t +{ + ZXIC_UINT32 func_id; /**< @brief hash引擎id 0~3*/ + ZXIC_UINT32 zblk_num; /**< @brief 0~32*/ + ZXIC_UINT32 zblk_bitmap; /**< @brief 置1的bit位表示分配的block编号 */ + ZXIC_UINT32 ddr_dis; /** <@brief 0:混合模式，1：纯片内模式*/ +} DPP_APT_HASH_FUNC_RES_T; + +typedef struct dpp_apt_hash_bulk_res_t +{ + ZXIC_UINT32 func_id; /**< @brief 0~3*/ + ZXIC_UINT32 bulk_id; /**< @brief 0~7*/ + ZXIC_UINT32 zcell_num; /**< @brief 0~128*/ + ZXIC_UINT32 zreg_num; /**< @brief 0~128*/ + ZXIC_UINT32 ddr_baddr; /**< @brief 分配给hash的DDR空间的硬件基地址,单位2k*256bit*/ + ZXIC_UINT32 ddr_item_num; /**< @brief 分配给hash的DDR空间单元数目，以256bit为一个单元（根据分配的基地址和单元数目确定分配的DDR空间大小）*/ + DPP_HASH_DDR_WIDTH_MODE ddr_width_mode; /**< @brief 分配给hash的DDR空间物理存储位宽模式，0:无效值，1:256bit 2:512bit*/ + ZXIC_UINT32 ddr_crc_sel; /**< @brief 选择一个DDR CRC多项式，取值范围0~3,0~3分别对应一个CRC多项式*/ + ZXIC_UINT32 ddr_ecc_en; /**< @brief DDR ECC使能: 0-不使能，1-使能*/ +} DPP_APT_HASH_BULK_RES_T; + +#define DTB_DUMP_UNICAST_MAC_DUMP_NUM (32 * 257) +#define DTB_DUMP_MULTICAST_MAC_DUMP_NUM (32 * 257) +#endif + +#if ZXIC_REAL("SE APT FUNCTION") + +/***********************************************************/ +/** eram表资源初始化 +* @param dev_id 设备号 +* @param tbl_num 需初始化的eram表个数 +* @param pEramTbl eram资源信息，包括SDT配置信息，直接表读取位宽和结构体码流转换回调函数 +* @return +* @remark 无 +* @see +* @author chenqin00181032 @date 2023/02/22 +************************************************************/ +DPP_STATUS dpp_apt_eram_res_init(DPP_DEV_T *dev,ZXIC_UINT32 tbl_num,DPP_APT_ERAM_TABLE_T *pEramTbl); + +/***********************************************************/ +/** DDR表资源初始化 +* @param dev_id 设备号 +* @param tbl_num 需初始化的DDR表个数 +* @param pDdrTbl ddr资源信息，包括SDT配置信息，直接表读取位宽和结构体码流转换回调函数 +* @return +* @remark 无 +* @see +* @author chenqin00181032 @date 2023/07/26 +************************************************************/ +DPP_STATUS dpp_apt_ddr_res_init(DPP_DEV_T *dev,ZXIC_UINT32 tbl_num,DPP_APT_DDR_TABLE_T *pDdrTbl); + +/***********************************************************/ +/** acl资源初始化 +* @param dev_id 设备号 +* @param tbl_num etcam对应的sdt表个数 +* @param pAclTblRes acl表资源信息，包括SDT配置信息，acl资源(条目数，存放方式和占用的block)和结构体码流转换回调函数 +* @return +* @remark 无 +* @see +* @author chenqin00181032 @date 2023/02/22 +************************************************************/ +DPP_STATUS dpp_apt_acl_res_init(DPP_DEV_T *dev,ZXIC_UINT32 tbl_num,DPP_APT_ACL_TABLE_T *pAclTblRes); + +/***********************************************************/ +/** hash表全局资源初始化 +* @param dev_id 设备号 +* @return +* @remark 无 +* @see +* @author chenqin00181032 @date 2023/02/22 +************************************************************/ +DPP_STATUS dpp_apt_hash_global_res_init(DPP_DEV_T *dev); + +/***********************************************************/ +/** hash引擎初始化 +* @param dev_id 设备号 +* @param func_num 需初始化的hash引擎个数 1~4 +* @param pHashFuncRes 每个hash引擎分配的zblock个数和编号，以及分配模式(混合模式或者纯片内模式) +* @return +* @remark 无 +* @see +* @author chenqin00181032 @date 2023/02/22 +************************************************************/ +DPP_STATUS dpp_apt_hash_func_res_init(ZXIC_UINT32 dev_id,ZXIC_UINT32 func_num,DPP_APT_HASH_FUNC_RES_T *pHashFuncRes); + +/***********************************************************/ +/** hash引擎初始化(删除硬件数据) +* @param dev_id 设备号 +* @param func_num 需初始化的hash引擎个数 1~4 +* @param pHashFuncRes 每个hash引擎分配的zblock个数和编号，以及分配模式(混合模式或者纯片内模式) +* @return +* @remark 无 +* @see +* @author chenqin00181032 @date 2023/02/22 +************************************************************/ +DPP_STATUS dpp_apt_hash_func_flush_hardware_all(DPP_DEV_T *dev, + ZXIC_UINT32 func_num, + DPP_APT_HASH_FUNC_RES_T *pHashFuncRes, + ZXIC_UINT32 queue_id); + +/***********************************************************/ +/** hash引擎bulk空间初始化 +* @param dev_id 设备号 +* @param bulk_num 需初始化的bulk表个数 1~32 +* @param pBulkRes zcell和zreg资源占用信息，如果是混合模式，需进行DDR资源分配 +* @return +* @remark 无 +* @see +* @author chenqin00181032 @date 2023/02/22 +************************************************************/ +DPP_STATUS dpp_apt_hash_bulk_res_init(ZXIC_UINT32 dev_id,ZXIC_UINT32 bulk_num,DPP_APT_HASH_BULK_RES_T *pBulkRes); + +/***********************************************************/ +/** hash业务表属性初始化 +* @param dev_id 设备号 +* @param tbl_num 需初始化的业务表表个数 1~128 +* @param pHashTbl sdt配置信息，初始化标记和业务结构体码流转换函数 +* @return +* @remark 无 +* @see +* @author chenqin00181032 @date 2023/02/22 +************************************************************/ +DPP_STATUS dpp_apt_hash_tbl_res_init(DPP_DEV_T *dev,ZXIC_UINT32 tbl_num,DPP_APT_HASH_TABLE_T *pHashTbl); + +/***********************************************************/ +/** dtb eram表项插入/更新 +* @param dev_id 设备号 +* @param sdt_no SDT号 0~255 +* @param index 条目index，索引范围随wrt_mode模式不同 +* @param pData 插入表项内容，由业务确定 +* @return +* @remark 无 +* @see +* @author chenqin00181032 @date 2023/02/22 +************************************************************/ +DPP_STATUS dpp_apt_dtb_eram_insert(DPP_DEV_T *dev,ZXIC_UINT32 queue_id,ZXIC_UINT32 sdt_no,ZXIC_UINT32 index,void *pData); + +/***********************************************************/ +/** eram表项数据获取,从软件缓存中获取 +* @param dev_id 设备号 +* @param sdt_no SDT号 0~255 +* @param index 条目index，索引范围随wrt_mode模式不同 +* @param pData 出参，返回业务表项内容 +* @return +* @remark 无 +* @see +* @author chenqin00181032 @date 2023/02/22 +************************************************************/ +DPP_STATUS dpp_apt_dtb_eram_get(DPP_DEV_T *dev, ZXIC_UINT32 queue_id, ZXIC_UINT32 sdt_no, ZXIC_UINT32 index, void *pData); + +/***********************************************************/ +/** eram表项删除,软件维护删除 +* @param dev_id 设备号 +* @param sdt_no SDT号 0~255 +* @param index 条目index，索引范围随wrt_mode模式不同 +* @return +* @remark 无 +* @see +* @author chenqin00181032 @date 2023/02/22 +************************************************************/ +DPP_STATUS dpp_apt_dtb_eram_clear(DPP_DEV_T *dev,ZXIC_UINT32 queue_id,ZXIC_UINT32 sdt_no,ZXIC_UINT32 index); + +/***********************************************************/ +/** dtb hash表项插入/更新 +* @param dev_id 设备号 +* @param sdt_no sdt号 0~255 +* @param pData 插入hash表项信息,由业务确定 +* @return +* @remark 无 +* @see +* @author chenqin00181032 @date 2023/02/22 +************************************************************/ +DPP_STATUS dpp_apt_dtb_hash_insert(DPP_DEV_T *dev,ZXIC_UINT32 queue_id,ZXIC_UINT32 sdt_no,void *pData); + +/***********************************************************/ +/** dtb hash表项删除 +* @param dev_id 设备号 +* @param sdt_no sdt号 0~255 +* @param pData 删除hash表项信息,由业务传入 +* @return +* @remark 无 +* @see +* @author chenqin00181032 @date 2023/02/22 +************************************************************/ +DPP_STATUS dpp_apt_dtb_hash_delete(DPP_DEV_T *dev,ZXIC_UINT32 queue_id,ZXIC_UINT32 sdt_no,void *pData); + +/***********************************************************/ +/** acl表项插入/更新 +* @param dev_id 设备号 +* @param sdt_no sdt号 0~255 +* @param pData 业务插入表项内容，具体结构体由业务确定(结构体的第一个字段必须为index)，SDK不感知 +* @return +* @remark 无 +* @see +* @author chenqin00181032 @date 2023/02/22 +************************************************************/ +DPP_STATUS dpp_apt_dtb_acl_entry_insert(DPP_DEV_T *dev,ZXIC_UINT32 queue_id, ZXIC_UINT32 sdt_no, void *pData); + +/***********************************************************/ +/** 释放sdt资源以及适配资源 +* @param dev_id 设备号 +* @param sdt_no sdt号 +* @return +* @remark 无 +* @see +* @author cq @date 2023/11/09 +************************************************************/ +DPP_STATUS dpp_apt_sdt_res_deinit(DPP_DEV_T *dev, ZXIC_UINT32 sdt_no); +#endif + +#endif \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_dtb_table_api.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_dtb_table_api.h new file mode 100644 index 0000000..3bcc5c4 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_dtb_table_api.h @@ -0,0 +1,213 @@ +#ifndef _DPP_DTB_TABLE_API_H_ +#define _DPP_DTB_TABLE_API_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "dpp_dev.h" +#include "zxic_common.h" + +#define DPP_DTB_DUMP_ZCAM_TYPE (ZXIC_UINT32)(0) +#define DPP_DTB_DUMP_DDR_TYPE (ZXIC_UINT32)(1) + +typedef struct dpp_dtb_user_entry_t +{ + ZXIC_UINT32 sdt_no; /*流表sdt号*/ + ZXIC_VOID* p_entry_data; /*该流表的数据，数据结构见各表的结构体定义*/ +}DPP_DTB_USER_ENTRY_T; + +typedef struct dpp_dtb_eram_entry_info_t +{ + ZXIC_UINT32 index; /*条目index，根据wrt_mode模式为单位的的index，支持1/64/128bit */ + ZXIC_UINT32 *p_data; /*写入的表项信息 */ +}DPP_DTB_ERAM_ENTRY_INFO_T; + +typedef struct dpp_dtb_ddr_entry_info_t +{ + ZXIC_UINT32 index; /*条目index，根据wrt_mode模式定义的index，支持128/256/384/512bit*/ + ZXIC_UINT32 *p_data; /*写入的表项信息*/ +}DPP_DTB_DDR_ENTRY_INFO_T; + +typedef struct dpp_dtb_hash_entry_info_t +{ + ZXIC_UINT8 *p_actu_key; /*实际的键值，对于一种表来说键值长度是固定的，在初始化时，会通过dpp_hash_tbl_id_info_init进行配置*/ + ZXIC_UINT8 *p_rst; /*hash表结果 result的长度由当前业务结果位宽决定*/ +}DPP_DTB_HASH_ENTRY_INFO_T; + +typedef struct dpp_dtb_acl_entry_info_t +{ + ZXIC_UINT32 handle; /*条目索引*/ + ZXIC_UINT8 *key_data; /*键值data部分 按mode的长度，支持640bit/320bit/160bit/80bit*/ + ZXIC_UINT8 *key_mask; /*键值mask部分 长度与data相同*/ + ZXIC_UINT8 *p_as_rslt; /*关联结果，仅使能关联查找情况有效 支持1/64/128bit*/ +}DPP_DTB_ACL_ENTRY_INFO_T; + +typedef struct dpp_dtb_dump_index_t +{ + ZXIC_UINT32 index; /*index*/ + ZXIC_UINT32 index_type; /*index类型 */ +}DPP_DTB_DUMP_INDEX_T; + +typedef struct dtb_queue_dma_addr_info +{ + ZXIC_UINT32 slot_id; /*np所在的槽位号*/ + ZXIC_UINT32 queue_id; /*队列号*/ + ZXIC_UINT32 dma_size; /*该队列申请的dma大小*/ + ZXIC_UINT64 dma_phy_addr; /* dma 物理地址*/ + ZXIC_UINT64 dma_vir_addr; /* dma 内核虚拟地址*/ +}DTB_QUEUE_DMA_ADDR_INFO; + +/*dump地址信息获取*/ +ZXIC_UINT32 dpp_dtb_dump_sdt_addr_get(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 sdt_no, + ZXIC_UINT64 *phy_addr, + ZXIC_UINT64 *vir_addr, + ZXIC_UINT32 *size); + +/***********************************************************/ +/** DTB通道申请 +* @param devId NP设备号 +* @param pName 申请DTB通道的唯一设备名(最大32字符) +* @param pQueueId 申请到的DTB通道编号 +* @return +* @remark 无 +* @see +* @author cbb @date 2023/07/03 +************************************************************/ +ZXIC_UINT32 dpp_dtb_queue_requst(DPP_DEV_T *dev, ZXIC_CONST ZXIC_UINT8* pName, + ZXIC_UINT16 vPort, + ZXIC_UINT32 *pQueueId); + +/***********************************************************/ +/** DTB通道释放 +* @param devId NP设备号 +* @param pName 要释放DTB通道的唯一设备名(最大32字符) +* @param pQueueId 要释放的DTB通道编号 +* @return +* @remark 无 +* @see +* @author cbb @date 2023/07/03 +************************************************************/ +ZXIC_UINT32 dpp_dtb_queue_release(DPP_DEV_T *dev, ZXIC_CONST ZXIC_UINT8* pName, + ZXIC_UINT32 queueId); + +/***********************************************************/ +/** DTB通道用户信息配置 +* @param devId NP设备号 +* @param queueId DTB通道编号 +* @param vPort vport信息 +* @param vector 中断号 +* @return +* @remark 无 +* @see +* @author cbb @date 2023/07/03 +************************************************************/ +ZXIC_UINT32 dpp_dtb_user_info_set(DPP_DEV_T *dev, + ZXIC_UINT32 queueId, + ZXIC_UINT16 vPort, + ZXIC_UINT32 vector); + +/***********************************************************/ +/** DTB通道下表空间地址设置,空间大小[32*(16+16*1024)B] +* @param devId NP设备号 +* @param queueId DTB通道编号 +* @param phyAddr 物理地址 +* @param virAddr 虚拟地址 +* @return +* @remark 无 +* @see +* @author cbb @date 2023/07/03 +************************************************************/ +ZXIC_UINT32 dpp_dtb_queue_down_table_addr_set(DPP_DEV_T *dev, + ZXIC_UINT32 queueId, + ZXIC_UINT64 phyAddr, + ZXIC_UINT64 virAddr); + +/***********************************************************/ +/** DTB通道dump空间地址设置,空间大小[32*(16+16*1024)B] +* @param devId NP设备号 +* @param pName 要释放DTB通道的设备名 +* @param phyAddr 物理地址 +* @param virAddr 虚拟地址 +* @return +* @remark 无 +* @see +* @author cbb @date 2023/07/03 +************************************************************/ +ZXIC_UINT32 dpp_dtb_queue_dump_table_addr_set(DPP_DEV_T *dev, + ZXIC_UINT32 queueId, + ZXIC_UINT64 phyAddr, + ZXIC_UINT64 virAddr); + +/***********************************************************/ +/** 大批量dump一个流表使用的地址空间配置 +* @param devId NP设备号 +* @param queueId DTB队列编号 +* @param sdtNo 流表std号 +* @param phyAddr 物理地址 +* @param virAddr 虚拟地址 +* @param size (最大64MB) +* @return +* @remark 无 +* @see +* @author cbb @date 2023/07/03 +************************************************************/ +ZXIC_UINT32 dpp_dtb_dump_sdt_addr_set(DPP_DEV_T *dev, + ZXIC_UINT32 queueId, + ZXIC_UINT32 sdtNo, + ZXIC_UINT64 phyAddr, + ZXIC_UINT64 virAddr, + ZXIC_UINT32 size); + +/***********************************************************/ +/** 清除大批量dump一个流表使用的地址空间配置 +* @param devId NP设备号 +* @param queueId DTB队列编号 +* @param sdtNo 流表std号 +* @return +* @remark 无 +* @see +* @author cbb @date 2023/07/03 +************************************************************/ +ZXIC_UINT32 dpp_dtb_dump_sdt_addr_clear(DPP_DEV_T *dev, + ZXIC_UINT32 queueId, + ZXIC_UINT32 sdtNo); + +/***********************************************************/ +/** 释放当前sdt下的所有流表(硬件方式) +* (适用于进程启动后，仅配置流表资源，软件未配置流表，但需要删除硬件上已配置流表的场景) +* @param dev_id 设备号 +* @param queue_id 队列号 +* @param sdt_no sdt号 +* @return +* @remark 无 +* @see +* @author cq @date 2023/12/04 +************************************************************/ +DPP_STATUS dpp_dtb_hash_offline_delete(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 sdt_no); + + +/***********************************************************/ +/** 释放当前sdt下的所有流表(硬件方式) +* (适用于进程正常退出前删除表项，软件上有存储表项) +* @param dev_id 设备号 +* @param queue_id 队列号 +* @param sdt_no sdt号 +* @return +* @remark 无 +* @see +* @author cq @date 2023/12/04 +************************************************************/ +DPP_STATUS dpp_dtb_hash_online_delete(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 sdt_no); + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_pbu_api.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_pbu_api.h new file mode 100644 index 0000000..f558605 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_pbu_api.h @@ -0,0 +1,145 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_pbu_api.h +* 文件标识 : pbu模块对外数据类型定义和接口函数声明 +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : djf +* 完成日期 : 2015/02/04 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ + +#ifndef _DPP_PBU_API_H_ +#define _DPP_PBU_API_H_ + +#include "dpp_module.h" + +#if ZXIC_REAL("data struct define") +typedef struct dpp_pbu_mc_cos_para_t +{ + ZXIC_UINT32 mc_cos_th[8]; /**< @brief cos0~7的mc指针阈值*/ + ZXIC_UINT32 mc_cos_mode[8]; /**< @brief cos0~7的mc指针溢出处理模式*/ +} DPP_PBU_MC_COS_PARA_T; + + +typedef struct dpp_pbu_port_th_para_t +{ + ZXIC_UINT32 lif_th; /**< @brief lif阈值*/ + ZXIC_UINT32 lif_prv; /**< @brief lif私有阈值*/ + ZXIC_UINT32 idma_prv; /**< @brief idma私有阈值*/ + ZXIC_UINT32 idma_th_cos0; /**< @brief idma cos0指针阈值*/ + ZXIC_UINT32 idma_th_cos1; /**< @brief idma cos1指针阈值*/ + ZXIC_UINT32 idma_th_cos2; /**< @brief idma cos2指针阈值*/ + ZXIC_UINT32 idma_th_cos3; /**< @brief idma cos3指针阈值*/ + ZXIC_UINT32 idma_th_cos4; /**< @brief idma cos4指针阈值*/ + ZXIC_UINT32 idma_th_cos5; /**< @brief idma cos5指针阈值*/ + ZXIC_UINT32 idma_th_cos6; /**< @brief idma cos6指针阈值*/ + ZXIC_UINT32 idma_th_cos7; /**< @brief idma cos7指针阈值*/ +} DPP_PBU_PORT_TH_PARA_T; + +typedef struct dpp_pbu_port_cos_th_para_t +{ + ZXIC_UINT32 cos_th[8]; /**< @brief 各cos对应的阈值，要求高优先级的阈值不小于低优先级的阈值 */ +} DPP_PBU_PORT_COS_TH_PARA_T; + + +typedef struct dpp_pbu_global_th_t +{ + ZXIC_UINT32 idma_public_th;/**< @brief idma总的共有指针*/ + ZXIC_UINT32 lif_public_th;/**< @brief lif总的共有指针*/ + ZXIC_UINT32 idma_total_th;/**< @brief idma总的指针阈值，最大支持16384*/ + ZXIC_UINT32 lif_total_th;/**< @brief lif总的指针阈值，最大支持16384*/ + ZXIC_UINT32 mc_total_th;/**< @brief 组播总的指针阈值*/ +} DPP_PBU_GLOBAL_TH_T; + + + + + + +#endif//struct + + +#if ZXIC_REAL("function declaration") +#if 0 +/***********************************************************/ +/** 全局公共使用指针阈值总体配置 +* @param dev_id 芯片ID 0~3 +* @param p_global_th 参见DPP_PBU_GLOBAL_TH_T详细定义 +* +* @return +* @remark 无 +* @see +* @author pj @date 2019/12/04 +************************************************************/ +DPP_STATUS dpp_pbu_global_th_set(ZXIC_UINT32 dev_id, + DPP_PBU_GLOBAL_TH_T *p_global_th); + +#endif +/***********************************************************/ +/** 配置基于端口的指针阈值 +* @param dev_id 设备编号 +* @param port_id 端口号 +* @param p_para 端口阈值 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/07/09 +************************************************************/ +DPP_STATUS dpp_pbu_port_th_set(DPP_DEV_T *dev, + ZXIC_UINT32 port_id, + DPP_PBU_PORT_TH_PARA_T *p_para); + +/***********************************************************/ +/** 配置指定端口按cos优先级起pfc流控的优先级流控指针阈值，仅对lif0的48个通道有效 +* @param dev_id 设备编号 +* @param port_id 端口号 +* @param p_para cos阈值，要求高优先级的阈值不小于低优先级的阈值 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/07/09 +************************************************************/ +DPP_STATUS dpp_pbu_port_cos_th_set(DPP_DEV_T *dev, + ZXIC_UINT32 port_id, + DPP_PBU_PORT_COS_TH_PARA_T *p_para); + +#if 0 +/***********************************************************/ +/** pbu初始化函数 +* @param dev_id 设备编号 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/07/09 +************************************************************/ +DPP_STATUS dpp_pbu_init(ZXIC_UINT32 dev_id); + +/***********************************************************/ +/** 配置基于cos的mc复制指针阈值和mc指针溢出处理模式 +* @param dev_id 设备编号 +* @param p_para cos0~7的mc指针阈值和mc指针溢出处理模式 0-wait 1-disc +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/04/14 +************************************************************/ +DPP_STATUS dpp_pbu_mc_cos_para_set(ZXIC_UINT32 dev_id, + DPP_PBU_MC_COS_PARA_T *p_para); +#endif +#endif//function +#endif + + diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_ppu_api.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_ppu_api.h new file mode 100755 index 0000000..45f5875 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_ppu_api.h @@ -0,0 +1,393 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_ppu_api.h +* 文件标识 : +* 内容摘要 : PPU模块对外数据结构和函数声明 +* 其它说明 : +* 当前版本 : +* 作 者 : wcl +* 完成日期 : 2015/02/13 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ + +#ifndef _DPP_PPU_API_H_ +#define _DPP_PPU_API_H_ + + +#if ZXIC_REAL("header file") +#include "dpp_module.h" + +#endif + +#if ZXIC_REAL("data struct define") + +/** mcode version time */ +typedef struct dpp_version_t +{ + /*对应微码伪指令 version = expr_a.expr_b.expr_c*/ + ZXIC_UINT32 version_a; /**< @brief expr_a*/ + ZXIC_UINT32 version_b; /**< @brief expr_b*/ + ZXIC_UINT32 version_c; /**< @brief xpr_c*/ + + /*对应微码编译版本的时间 年/月/日/小时*/ + ZXIC_UINT32 year; + ZXIC_UINT32 month; + ZXIC_UINT32 day; + ZXIC_UINT32 hour; +}DPP_VERSION_T; + +/** SDT表数据*/ +typedef struct dpp_sdt_tbl_data_t +{ + ZXIC_UINT32 data_high32; /**< @brief SDT表数据高32bit*/ + ZXIC_UINT32 data_low32; /**< @brief SDT表数据低32bit*/ +}DPP_SDT_TBL_DATA_T; + +#endif + +#if ZXIC_REAL("interrupt data struct define") +/** PPU 指令RAM ECC错误中断原因*/ +typedef struct dpp_ppu_ram_parity_err_t +{ + ZXIC_UINT32 instrmem2_bank3_parity_err; /**< @brief 指令RAM instrmem2 BANK3 parity 错误*/ + ZXIC_UINT32 instrmem2_bank2_parity_err; /**< @brief 指令RAM instrmem2 BANK2 parity 错误*/ + ZXIC_UINT32 instrmem2_bank1_parity_err; /**< @brief 指令RAM instrmem2 BANK1 parity 错误*/ + ZXIC_UINT32 instrmem2_bank0_parity_err; /**< @brief 指令RAM instrmem2 BANK0 parity 错误*/ + ZXIC_UINT32 instrmem1_bank3_parity_err; /**< @brief 指令RAM instrmem1 BANK3 parity 错误*/ + ZXIC_UINT32 instrmem1_bank2_parity_err; /**< @brief 指令RAM instrmem1 BANK2 parity 错误*/ + ZXIC_UINT32 instrmem1_bank1_parity_err; /**< @brief 指令RAM instrmem1 BANK1 parity 错误*/ + ZXIC_UINT32 instrmem1_bank0_parity_err; /**< @brief 指令RAM instrmem1 BANK0 parity 错误*/ + ZXIC_UINT32 instrmem0_bank3_parity_err; /**< @brief 指令RAM instrmem0 BANK3 parity 错误*/ + ZXIC_UINT32 instrmem0_bank2_parity_err; /**< @brief 指令RAM instrmem0 BANK2 parity 错误*/ + ZXIC_UINT32 instrmem0_bank1_parity_err; /**< @brief 指令RAM instrmem0 BANK1 parity 错误*/ + ZXIC_UINT32 instrmem0_bank0_parity_err; /**< @brief 指令RAM instrmem0 BANK0 parity 错误*/ +}DPP_PPU_RAM_PARITY_ERR_T; + +/** PPU ME指令RAM ECC错误中断原因*/ +typedef struct dpp_ppu_me_interrupt_t +{ + ZXIC_UINT32 me7_interrupt_mask ; /**< @brief me7core的中断掩码*/ + ZXIC_UINT32 me6_interrupt_mask ; /**< @brief me6core的中断掩码*/ + ZXIC_UINT32 me5_interrupt_mask ; /**< @brief me5core的中断掩码*/ + ZXIC_UINT32 me4_interrupt_mask ; /**< @brief me4core的中断掩码*/ + ZXIC_UINT32 me3_interrupt_mask ; /**< @brief me3core的中断掩码*/ + ZXIC_UINT32 me2_interrupt_mask ; /**< @brief me2core的中断掩码*/ + ZXIC_UINT32 me1_interrupt_mask ; /**< @brief me1core的中断掩码*/ + ZXIC_UINT32 me0_interrupt_mask ; /**< @brief me0core的中断掩码*/ + +}DPP_PPU_ME_INTERRUPT_T; + +/** cluster mex的错误中断原因*/ +typedef struct dpp_ppu_cluster_600m_mex_fifo_int_t +{ + ZXIC_UINT32 ppu_se_ikey_afifo_underflow; /**< @brief se片内表key fifo读空中断*/ + ZXIC_UINT32 ppu_se_ekey_afifo_underflow; /**< @brief se片外表key fifo读空中断*/ + ZXIC_UINT32 ppu_sta_key_afifo_underflow; /**< @brief 统计计数key fifo读空中断*/ + ZXIC_UINT32 ppu_cluster_mf_in_overflow; /**< @brief metafram接收 fifo满写中断*/ + ZXIC_UINT32 ppu_ese_rsp_afifo_overflow; /**< @brief se片外表 rsp fifo满写中断*/ + ZXIC_UINT32 ppu_ise_rsp_afifo_overflow; /**< @brief se片内表 rsp fifo满写中断*/ + ZXIC_UINT32 ppu_sta_rsp_afifo_overflow; /**< @brief 统计计数 rsp fifo满写中断*/ +}DPP_PPU_CLUSTER_600M_MEX_FIFO_INT_T; + +/** cluster mex的错误中断原因*/ +typedef struct dpp_ppu_cluster_1200m_mex_fifo_int_t +{ + ZXIC_UINT32 ppu_se_key_afifo_32x54_wrapper_overflow_flag; /**< @brief ppu_se_key_afifo_32x54_wrapper满写中断掩码*/ + ZXIC_UINT32 ppu_se_key_afifo_32x665_wrapper_overflow_flag; /**< @brief ppu_se_key_afifo_32x665_wrapper满写中断掩码*/ + ZXIC_UINT32 ppu_sta_key_afifo_32x110_wrapper_overflow_flag; /**< @brief ppu_sta_key_afifo_32x110_wrapper满写中断掩码*/ + ZXIC_UINT32 ppu_cluster_mf_in_afifo_16x2048_wrapper_underflow_flag; /**< @brief ppu_cluster_mf_in_afifo_32x2048_wrapper读空中断掩码*/ + ZXIC_UINT32 ppu_pbu_mcode_pf_rsp_fifo_32x13_wrapper_overflow_flag; /**< @brief ppu_pbu_mcode_pf_rsp_fifo满写中断掩码*/ + ZXIC_UINT32 ppu_pbu_mcode_pf_rsp_fifo_32x13_wrapper_underflow_flag; /**< @brief ppu_pbu_mcode_pf_rsp_fifo_32x13_wrapper读空中断掩码*/ + ZXIC_UINT32 ppu_coprocess_rsp_fifo_32x77_wrapper_overflow_flag; /**< @brief ppu_coprocess_rsp_fifo_32x77_wrapper满写中断掩码*/ + ZXIC_UINT32 ppu_coprocess_rsp_fifo_32x77_wrapper_underflow_flag; /**< @brief ppu_coprocess_rsp_fifo_32x77_wrapper读空中断掩码*/ + ZXIC_UINT32 ppu_coprocess_rsp_fwft_fifo_128x78_wrapper_overflow_flag; /**< @brief ppu_coprocess_rsp_fwft_fifo_128x78_wrapper满写中断掩码*/ + ZXIC_UINT32 ppu_coprocess_rsp_fwft_fifo_128x78_wrapper_underflow_flag; /**< @brief ppu_coprocess_rsp_fwft_fifo_128x78_wrapper读空中断掩码*/ + ZXIC_UINT32 ppu_ese_rsp_afifo_64x271_wrapper_u0_underflow_flag; /**< @brief ppu_ese_rsp_afifo_64x271_wrapper_u0满写中断掩码*/ + + ZXIC_UINT32 ese_rsp_ram_free_ptr_u0_overflow_flag; /**< @brief ese_rsp_ram_free_ptr_u0满写中断掩码*/ + ZXIC_UINT32 ese_rsp_ram_free_ptr_u0_underflow_flag; /**< @brief ese_rsp_ram_free_ptr_u0读空中断掩码*/ + ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u0_overflow_flag; /**< @brief ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u0满写中断掩码*/ + ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u0_underflow_flag; /**< @brief ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u0读空中断掩码*/ + ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u1_overflow_flag; /**< @brief ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u1满写中断掩码*/ + ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u1_underflow_flag; /**< @brief ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u1读空中断掩码*/ + ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u2_overflow_flag; /**< @brief ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u2满写中断掩码*/ + ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u2_underflow_flag; /**< @brief ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u2读空中断掩码*/ + ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u3_overflow_flag; /**< @brief ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u3满写中断标记*/ + ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u3_underflow_flag; /**< @brief ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u3读空中断标记*/ + ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u4_overflow_flag; /**< @brief ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u4满写中断标记*/ + ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u4_underflow_flag; /**< @brief ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u4读空中断标记*/ + ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u5_overflow_flag; /**< @brief ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u5满写中断标记*/ + ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u5_underflow_flag; /**< @brief ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u5读空中断标记*/ + ZXIC_UINT32 ppu_ise_rsp_afifo_64x143_wrapper_u0_underflow_flag; /**< @brief ppu_ise_rsp_afifo_64x143_wrapper_u0读空中断标记*/ + ZXIC_UINT32 ise_rsp_ram_free_ptr_u0_overflow_flag; /**< @brief ise_rsp_ram_free_ptr_u0满写中断标记 */ + ZXIC_UINT32 ise_rsp_ram_free_ptr_u0_underflow_flag; /**< @brief ise_rsp_ram_free_ptr_u0读空中断标记*/ + ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u0_overflow_flag; /**< @brief ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u0满写中断标记*/ + ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u0_underflow_flag; /**< @brief ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u0读空中断标记*/ + ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u1_overflow_flag; /**< @brief ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u1满写中断标记*/ + ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u1_underflow_flag; /**< @brief ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u1读空中断标记*/ + ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u2_overflow_flag; /**< @brief ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u2满写中断标记*/ + ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u2_underflow_flag; /**< @brief ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u2读空中断标记*/ + ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u3_overflow_flag; /**< @brief ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u3满写中断标记*/ + ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u3_underflow_flag; /**< @brief ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u3读空中断标记*/ + ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u4_overflow_flag; /**< @brief ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u4满写中断标记*/ + ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u4_underflow_flag; /**< @brief ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u4读空中断标记*/ + ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u5_overflow_flag; /**< @brief ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u5满写中断标记*/ + ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u5_underflow_flag; /**< @brief ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u5读空中断标记*/ + ZXIC_UINT32 ppu_sta_rsp_afifo_64x79_wrapper_underflow_flag; /**< @brief ppu_sta_rsp_afifo_64x79_wrapper读空中断标记*/ + ZXIC_UINT32 ppu_sta_rsp_fwft_fifo_128x79_wrapper_overflow_flag; /**< @brief ppu_sta_rsp_fwft_fifo_128x79_wrapper满写中断标记*/ + ZXIC_UINT32 ppu_sta_rsp_fwft_fifo_128x79_wrapper_underflow_flag; /**< @brief ppu_sta_rsp_fwft_fifo_128x79_wrapper读空中断标记*/ +}DPP_PPU_CLUSTER_1200M_MEX_FIFO_INT_T; + +typedef struct dpp_ppu_ppu_ram_err_t +{ + ZXIC_UINT32 dup_freeptr_fwft_fifo_128x7_wrapper_u0_parity_err_flag; /**< @brief dup_freeptr_fwft_fifo_128x7_wrapper_u0_parity_err中断标记*/ + ZXIC_UINT32 free_global_num_fwft_fifo_8192x13_wrapper_u0_parity_err_flag; /**< @brief free_global_num_fwft_fifo_8192x13_wrapper_u0_parity_err中断标记*/ + ZXIC_UINT32 ppu_mccnt_fifo_32x15_wrapper_u0_parity_err_flag; /**< @brief ppu_mccnt_fifo_32x15_wrapper_u0_parity_err中断标记*/ + ZXIC_UINT32 ppu_reorder_link_table_ram_1r1w_8192x13_wrapper_u1_parity_err_flag; /**< @brief ppu_reorder_link_table_ram_1r1w_8192x13_wrapper_u1_parity_err中断标记*/ + ZXIC_UINT32 ppu_reorder_link_table_ram_1r1w_8192x13_wrapper_u0_parity_err_flag; /**< @brief ppu_reorder_link_table_ram_1r1w_8192x13_wrapper_u0_parity_err中断标记*/ +}DPP_PPU_PPU_RAM_ERR_T; + +typedef struct dpp_ppu_cls_ram_err_600m_t +{ + ZXIC_UINT32 ppu_sdt_table_ram_2rw_256x64_wrapper_parity_errb_flag; /**< @brief ppu_sdt_table_ram_2rw_256x64_wrapper_parity_errb中断标记*/ + ZXIC_UINT32 ppu_sdt_table_ram_2rw_256x64_wrapper_parity_erra_flag; /**< @brief ppu_sdt_table_ram_2rw_256x64_wrapper_parity_errba中断标记*/ +}DPP_PPU_CLS_RAM_ERR_600M_T; + +/** cluster mex的错误中断原因*/ +typedef struct dpp_ppu_cluster_me_fifo_int_t +{ + ZXIC_UINT32 me_except_refetch_pc_overflow_flag; /**< @brief me_except_refetch_pc满写中断标记*/ + ZXIC_UINT32 me_except_refetch_pc_underflow_flag; /**< @brief me_except_refetch_pc读空中断标记*/ + + ZXIC_UINT32 me_free_pkt_q_overflow_flag; /**< @brief me_free_pkt_q满写中断状态*/ + ZXIC_UINT32 me_free_pkt_q_underflow_flag; /**< @brief me_free_pkt_q读空中断状态*/ + ZXIC_UINT32 me_free_thread_q_overflow_flag; /**< @brief me_free_thread_q满写中断状态*/ + ZXIC_UINT32 me_free_thread_q_underflow_flag; /**< @brief me_free_thread_q读空中断状态*/ + ZXIC_UINT32 me_pkt_in_overflow_flag; /**< @brief me_pkt_in_满写中断状态*/ + ZXIC_UINT32 me_pkt_in_underflow_flag; /**< @brief me_pkt_in_读空中断状态*/ + ZXIC_UINT32 me_rdy_q_overflow_flag; /**< @brief me_rdy_q满写中断状态*/ + ZXIC_UINT32 me_rdy_q_underflow_flag; /**< @brief me_rdy_q读空中断状态*/ + ZXIC_UINT32 me_pkt_out_q_overflow_flag; /**< @brief me_pkt_out_q满写中断状态*/ + ZXIC_UINT32 me_pkt_out_q_underflow_flag; /**< @brief me_pkt_out_q读空中断状态*/ + ZXIC_UINT32 me_continue_q_overflow_flag; /**< @brief me_continue_q满写中断状态*/ + ZXIC_UINT32 me_continue_q_underflow_flag; /**< @brief me_continue_q读空中断状态*/ + ZXIC_UINT32 me_esrh_q_overflow_flag; /**< @brief me_esrh_q满写中断状态*/ + ZXIC_UINT32 me_esrh_q_underflow_flag; /**< @brief me_esrh_q读空中断状态*/ + ZXIC_UINT32 me_isrh_q_overflow_flag; /**< @brief me_isrh_q满写中断状态*/ + ZXIC_UINT32 me_isrh_q_underflow_flag; /**< @brief me_isrh_q读空中断状态*/ + ZXIC_UINT32 me_cache_miss_q_overflow_flag; /**< @brief me_cache_miss_q满写中断状态*/ + ZXIC_UINT32 me_cache_miss_q_underflow_flag; /**< @brief me_cache_miss_q读空中断状态*/ + ZXIC_UINT32 me_base_q_u0_overflow_flag; /**< @brief me_base_q_u0满写中断状态*/ + ZXIC_UINT32 me_base_q_u0_underflow_flag; /**< @brief me_base_q_u0读空中断状态*/ + ZXIC_UINT32 me_base_q_u1_overflow_flag; /**< @brief me_base_q_u1满写中断状态*/ + ZXIC_UINT32 me_base_q_u1_underflow_flag; /**< @brief me_base_q_u1读空中断状态*/ + ZXIC_UINT32 me_base_q_u2_overflow_flag; /**< @brief me_base_q_u2满写中断状态*/ + ZXIC_UINT32 me_base_q_u2_underflow_flag; /**< @brief me_base_q_u2读空中断状态*/ + ZXIC_UINT32 me_base_q_u3_overflow_flag; /**< @brief me_base_q_u3满写中断状态*/ + ZXIC_UINT32 me_base_q_u3_underflow_flag; /**< @brief me_base_q_u3读空中断状态*/ + ZXIC_UINT32 me_reg_pc_q_overflow_flag; /**< @brief me_reg_pc_q满写中断状态*/ + ZXIC_UINT32 me_reg_pc_q_underflow_flag; /**< @brief me_reg_pc_q读空中断状态*/ + ZXIC_UINT32 me_branch_q_overflow_flag; /**< @brief me_branch_q满写中断状态*/ + ZXIC_UINT32 me_branch_q_underflow_flag; /**< @brief me_branch_q读空中断状态*/ + ZXIC_UINT32 me_pkt_base_q_overflow_flag; /**< @brief me_pkt_base_q满写中断状态*/ + ZXIC_UINT32 me_pkt_base_q_underflow_flag; /**< @brief me_pkt_base_q读空中断状态*/ +}DPP_PPU_CLUSTER_ME_FIFO_INT_T; + + +typedef struct dpp_ppu_ppu_isu_ppu_demux_fifo_int_t +{ + ZXIC_UINT32 isu_in_para_fwft_fifo_32x81_wrapper_u0_overflow_flag; /**< @brief isu_in_para_fwft_fifo_32x81_wrapper_u0_overflow中断标记*/ + ZXIC_UINT32 isu_in_para_fwft_fifo_32x81_wrapper_u0_underflow_flag; /**< @brief isu_in_para_fwft_fifo_32x81_wrapper_u0_underflow中断标记*/ + ZXIC_UINT32 isu_in_fifo_64x81_wrapper_u0_overflow_flag; /**< @brief isu_in_fifo_64x81_wrapper_u0_overflow中断标记*/ + ZXIC_UINT32 isu_in_fifo_64x81_wrapper_u0_underflow_flag; /**< @brief isu_in_fifo_64x81_wrapper_u0_underflow中断标记*/ +}DPP_PPU_PPU_ISU_PPU_DEMUX_FIFO_INT_T; + +typedef struct dpp_ppu_ppu_ppu_multicast_fifo_int_t +{ + ZXIC_UINT32 pf_req_fwft_fifo_16x36_wrapper_u0_overflow_flag; /**< @brief pf_req_fwft_fifo_16x36_wrapper_u0_overflow中断标记*/ + ZXIC_UINT32 pf_req_fwft_fifo_16x36_wrapper_u0_underflow_flag; /**< @brief pf_req_fwft_fifo_16x36_wrapper_u0_underflow中断标记*/ + ZXIC_UINT32 pf_rsp_fwft_fifo_32x34_wrapper_u0_overflow_flag; /**< @brief pf_rsp_fwft_fifo_32x34_wrapper_u0_overflow中断标记*/ + ZXIC_UINT32 pf_rsp_fwft_fifo_32x34_wrapper_u0_underflow_flag; /**< @brief pf_rsp_fwft_fifo_32x34_wrapper_u0_underflow中断标记*/ + ZXIC_UINT32 dup_para_fwft_fifo_16x35_wrapper_u0_overflow_flag; /**< @brief dup_para_fwft_fifo_16x35_wrapper_u0_overflow中断标记*/ + ZXIC_UINT32 dup_para_fwft_fifo_16x35_wrapper_u0_underflow_flag; /**< @brief dup_para_fwft_fifo_16x35_wrapper_u0_underflow中断标记*/ + ZXIC_UINT32 se_mc_rsp_fwft_fifo_32x17_wrapper_u0_overflow_flag; /**< @brief se_mc_rsp_fwft_fifo_32x17_wrapper_u0_overflow中断标记*/ + ZXIC_UINT32 se_mc_rsp_fwft_fifo_32x17_wrapper_u0_underflow_flag; /**< @brief se_mc_rsp_fwft_fifo_32x17_wrapper_u0_underflow中断标记*/ + ZXIC_UINT32 sa_para_fwft_fifo_64x17_wrapper_u0_overflow_flag; /**< @brief sa_para_fwft_fifo_64x17_wrapper_u0_overflow中断标记*/ + ZXIC_UINT32 sa_para_fwft_fifo_64x17_wrapper_u0_underflow_flag; /**< @brief sa_para_fwft_fifo_64x17_wrapper_u0_underflow中断标记*/ + ZXIC_UINT32 group_id_fifo_64x16_wrapper_u0_overflow_flag; /**< @brief group_id_fifo_64x16_wrapper_u0_overflow中断标记*/ + ZXIC_UINT32 group_id_fifo_64x16_wrapper_u0_underflow_flag; /**< @brief group_id_fifo_64x16_wrapper_u0_underflow中断标记*/ + ZXIC_UINT32 isu_mc_para_fwft_fifo_128x34_wrapper_u0_overflow_flag; /**< @brief isu_mc_para_fwft_fifo_128x34_wrapper_u0_overflow中断标记*/ + ZXIC_UINT32 isu_mc_para_fwft_fifo_128x34_wrapper_u0_underflow_flag; /**< @brief isu_mc_para_fwft_fifo_128x34_wrapper_u0_underflow中断标记*/ + ZXIC_UINT32 dup_freeptr_fwft_fifo_128x7_wrapper_u0_overflow_flag; /**< @brief dup_freeptr_fwft_fifo_128x7_wrapper_u0_overflow中断标记*/ + ZXIC_UINT32 dup_freeptr_fwft_fifo_128x7_wrapper_u0_underflow_flag; /**< @brief dup_freeptr_fwft_fifo_128x7_wrapper_u0_underflow中断标记*/ + ZXIC_UINT32 car_flag_fifo_32x1_wrapper_overflow_flag; /**< @brief car_flag_fifo_32x1_wrapper_overflow中断标记*/ + ZXIC_UINT32 car_flag_fifo_32x1_wrapper_underflow_flag; /**< @brief car_flag_fifo_32x1_wrapper_underflow中断标记*/ +}DPP_PPU_PPU_PPU_MULTICAST_FIFO_INT_T; + +typedef struct dpp_ppu_ppu_ppu_in_schedule_fifo_int_t +{ + ZXIC_UINT32 free_global_num_fwft_fifo_8192x13_wrapper_u0_overflow_flag; /**< @brief free_global_num_fwft_fifo_8192x13_满写中断标记*/ + ZXIC_UINT32 free_global_num_fwft_fifo_8192x13_wrapper_u0_underflow_flag; /**< @brief free_global_num_fwft_fifo_8192x13_空读中断标记*/ + ZXIC_UINT32 mc_mf_fifo_16x2048_wrapper_u0_overflow_flag; /**< @brief mc_mf_fifo_16x2048_满写中断标记*/ + ZXIC_UINT32 mc_mf_fifo_16x2048_wrapper_u0_underflow_flag; /**< @brief mc_mf_fifo_16x2048_空读中断标记*/ + ZXIC_UINT32 uc_mf_fifo_96x2048_wrapper_u0_overflow_flag; /**< @brief uc_mf_fifo_96x2048_满写中断标记*/ + ZXIC_UINT32 uc_mf_fifo_96x2048_wrapper_u0_underflow_flag; /**< @brief uc_mf_fifo_96x2048_空读中断标记*/ +}DPP_PPU_PPU_PPU_IN_SCHEDULE_FIFO_INT_T; + +typedef struct dpp_ppu_ppu_ppu_mf_out_fifo_int_t +{ + ZXIC_UINT32 ppu_cluster5_mf_out_afifo_16x2048_wrapper_overflow_flag; /**< @brief cluster5发送描述符fifo满写中断标记*/ + ZXIC_UINT32 ppu_cluster5_mf_out_afifo_16x2048_wrapper_underflow_flag; /**< @brief cluster5发送描述符fifo空读中断标记*/ + ZXIC_UINT32 ppu_cluster4_mf_out_afifo_16x2048_wrapper_overflow_flag; /**< @brief cluster4发送描述符fifo满写中断标记*/ + ZXIC_UINT32 ppu_cluster4_mf_out_afifo_16x2048_wrapper_underflow_flag; /**< @brief cluster4发送描述符fifo空读中断标记*/ + ZXIC_UINT32 ppu_cluster3_mf_out_afifo_16x2048_wrapper_overflow_flag; /**< @brief cluster3发送描述符fifo满写中断标记*/ + ZXIC_UINT32 ppu_cluster3_mf_out_afifo_16x2048_wrapper_underflow_flag; /**< @brief cluster3发送描述符fifo空读中断标记*/ + ZXIC_UINT32 ppu_cluster2_mf_out_afifo_16x2048_wrapper_overflow_flag; /**< @brief cluster2发送描述符fifo满写中断标记*/ + ZXIC_UINT32 ppu_cluster2_mf_out_afifo_16x2048_wrapper_underflow_flag; /**< @brief cluster2发送描述符fifo空读中断标记*/ + ZXIC_UINT32 ppu_cluster1_mf_out_afifo_16x2048_wrapper_overflow_flag; /**< @brief cluster1发送描述符fifo满写中断标记*/ + ZXIC_UINT32 ppu_cluster1_mf_out_afifo_16x2048_wrapper_underflow_flag; /**< @brief cluster1发送描述符fifo空读中断标记*/ + ZXIC_UINT32 ppu_cluster0_mf_out_afifo_16x2048_wrapper_overflow_flag; /**< @brief cluster0发送描述符fifo满写中断标记*/ + ZXIC_UINT32 ppu_cluster0_mf_out_afifo_16x2048_wrapper_underflow_flag; /**< @brief cluster0发送描述符fifo空读中断标记*/ +}DPP_PPU_PPU_PPU_MF_OUT_FIFO_INT_T; + +typedef struct dpp_ppu_ppu_pbu_mcode_pf_req_schedule_fifo_int_t +{ + ZXIC_UINT32 ppu_cluster5_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_flag; /**< @brief cluster5指针预取fifo满写中断标记*/ + ZXIC_UINT32 ppu_cluster4_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_flag; /**< @brief cluster4指针预取fifo满写中断标记*/ + ZXIC_UINT32 ppu_cluster3_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_flag; /**< @brief cluster3指针预取fifo满写中断标记*/ + ZXIC_UINT32 ppu_cluster2_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_flag; /**< @brief cluster2指针预取fifo满写中断标记*/ + ZXIC_UINT32 ppu_cluster1_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_flag; /**< @brief cluster1指针预取fifo满写中断标记*/ + ZXIC_UINT32 ppu_cluster0_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_flag; /**< @brief cluster0指针预取fifo满写中断标记*/ + ZXIC_UINT32 ppu_cluster5_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_flag; /**< @brief cluster5指针预取fifo空读中断标记*/ + ZXIC_UINT32 ppu_cluster4_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_flag; /**< @brief cluster4指针预取fifo空读中断标记*/ + ZXIC_UINT32 ppu_cluster3_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_flag; /**< @brief cluster3指针预取fifo空读中断标记*/ + ZXIC_UINT32 ppu_cluster2_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_flag; /**< @brief cluster2指针预取fifo空读中断标记*/ + ZXIC_UINT32 ppu_cluster1_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_flag; /**< @brief cluster1指针预取fifo空读中断标记*/ + ZXIC_UINT32 ppu_cluster0_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_flag; /**< @brief cluster0指针预取fifo空读中断标记*/ +}DPP_PPU_PPU_PBU_MCODE_PF_REQ_SCHEDULE_FIFO_INT_T; + +typedef struct dpp_ppu_ppu_pbu_mcode_pf_rsp_schedule_fifo_int_t +{ + ZXIC_UINT32 ppu_pbu_mcode_pf_rsp_afifo_64x16_wrapper_u0r_underflow_flag; /**< @brief ppu微码申请指针返回fifo空读中断标记*/ + ZXIC_UINT32 ppu_pbu_mcode_pf_rsp_afifo_64x16_wrapper_u0_overflow_flag; /**< @brief ppu微码申请指针返回fifo满写中断标记*/ +}DPP_PPU_PPU_PBU_MCODE_PF_RSP_SCHEDULE_FIFO_INT_T; + +typedef struct dpp_ppu_ppu_ppu_mccnt_fifo_int_t +{ + ZXIC_UINT32 ppu_mccnt_fifo_32x15_wrapper_u0_overflow_flag; /**< @brief ppu_mccnt_fifo_32x15_wrapper_u0_overflow中断标记*/ + ZXIC_UINT32 ppu_mccnt_fifo_32x15_wrapper_u0_underflow_flag; /**< @brief ppu_mccnt_fifo_32x15_wrapper_u0_underflow中断标记*/ + ZXIC_UINT32 ppu_wb_data_fifo_32x2048_wrapper_u0_overflow_flag; /**< @brief ppu_wb_data_fifo_32x2048_wrapper_u0_overflow中断标记*/ + ZXIC_UINT32 ppu_wb_data_fifo_32x2048_wrapper_u0_underflow_flag; /**< @brief ppu_wb_data_fifo_32x2048_wrapper_u0_underflow中断标记*/ + ZXIC_UINT32 mccnt_rsp_fifo_32x1_wrapper_u0_overflow_flag; /**< @brief mccnt_rsp_fifo_32x1_wrapper_u0_overflow中断标记*/ + ZXIC_UINT32 mccnt_rsp_fifo_32x1_wrapper_u0_underflow_flag; /**< @brief mccnt_rsp_fifo_32x1_wrapper_u0_underflow中断标记*/ +}DPP_PPU_PPU_PPU_MCCNT_FIFO_INT_T; + +typedef struct dpp_ppu_ppu_coprocessor_fifo_int_t +{ + ZXIC_UINT32 ppu_cop_random_mod_para_delay_fifo_48x16_wrapper_overflow_flag; /**< @brief 协处理random_mod参数fifo错误满写中断标记*/ + ZXIC_UINT32 ppu_cop_random_mod_para_delay_fifo_48x16_wrapper_underflow_flag; /**< @brief 协处理random_mod参数fifo错误空读中断标记*/ + + ZXIC_UINT32 ppu_cop_result_fwft_fifo_80x80_wrapper_overflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 ppu_cop_result_fwft_fifo_80x80_wrapper_underflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 ppu_cop_delay_fifo_48x16_wrapper_overflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 ppu_cop_delay_fifo_48x16_wrapper_underflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 ppu_cop_delay_fifo_16x48_wrapper_overflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 ppu_cop_delay_fifo_16x48_wrapper_underflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 ppu_cop_delay_fifo_16x32_wrapper_overflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 ppu_cop_delay_fifo_16x32_wrapper_underflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 ppu_cop_result_fwft_fifo_96x80_wrapper_overflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 ppu_cop_result_fwft_fifo_96x80_wrapper_underflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 ppu_cop_delay_fifo_16x16_wrapper_overflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 ppu_cop_delay_fifo_16x16_wrapper_underflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 ppu_cop_result_fwft_fifo_32x80_wrapper_overflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 ppu_cop_result_fwft_fifo_32x80_wrapper_underflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 ppu_cop_result_fwft_fifo_16x80_wrapper_overflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 ppu_cop_result_fwft_fifo_16x80_wrapper_underflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 mec5_cop_key_crc_fifo_32x625_wrapper_overflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 mec5_cop_key_crc_fifo_32x625_wrapper_underflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 mec5_cop_key_checksum_fifo_32x180_wrapper_overflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 mec5_cop_key_checksum_fifo_32x180_wrapper_underflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 mec5_cop_key_mul_fifo_32x52_wrapper_overflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 mec5_cop_key_mul_fifo_32x52_wrapper_underflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 mec5_cop_key_random_mod_fifo_32x44_wrapper_overflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 mec5_cop_key_random_mod_fifo_32x44_wrapper_underflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 mec4_cop_key_crc_fifo_32x625_wrapper_overflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 mec4_cop_key_crc_fifo_32x625_wrapper_underflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 mec4_cop_key_checksum_fifo_32x180_wrapper_overflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 mec4_cop_key_checksum_fifo_32x180_wrapper_underflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 mec4_cop_key_mul_fifo_32x52_wrapper_overflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 mec4_cop_key_mul_fifo_32x52_wrapper_underflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 mec4_cop_key_random_mod_fifo_32x44_wrapper_overflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 mec4_cop_key_random_mod_fifo_32x44_wrapper_underflow_flag; /**< @brief fifo错误中断标记*/ + + ZXIC_UINT32 mec3_cop_key_crc_fifo_32x625_wrapper_overflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 mec3_cop_key_crc_fifo_32x625_wrapper_underflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 mec3_cop_key_checksum_fifo_32x180_wrapper_overflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 mec3_cop_key_checksum_fifo_32x180_wrapper_underflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 mec3_cop_key_mul_fifo_32x52_wrapper_overflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 mec3_cop_key_mul_fifo_32x52_wrapper_underflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 mec3_cop_key_random_mod_fifo_32x44_wrapper_overflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 mec3_cop_key_random_mod_fifo_32x44_wrapper_underflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 mec2_cop_key_crc_fifo_32x625_wrapper_overflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 mec2_cop_key_crc_fifo_32x625_wrapper_underflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 mec2_cop_key_checksum_fifo_32x180_wrapper_overflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 mec2_cop_key_checksum_fifo_32x180_wrapper_underflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 mec2_cop_key_mul_fifo_32x52_wrapper_overflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 mec2_cop_key_mul_fifo_32x52_wrapper_underflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 mec2_cop_key_random_mod_fifo_32x44_wrapper_overflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 mec2_cop_key_random_mod_fifo_32x44_wrapper_underflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 mec1_cop_key_crc_fifo_32x625_wrapper_overflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 mec1_cop_key_crc_fifo_32x625_wrapper_underflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 mec1_cop_key_checksum_fifo_32x180_wrapper_overflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 mec1_cop_key_checksum_fifo_32x180_wrapper_underflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 mec1_cop_key_mul_fifo_32x52_wrapper_overflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 mec1_cop_key_mul_fifo_32x52_wrapper_underflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 mec1_cop_key_random_mod_fifo_32x44_wrapper_overflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 mec1_cop_key_random_mod_fifo_32x44_wrapper_underflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 mec0_cop_key_crc_fifo_32x625_wrapper_overflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 mec0_cop_key_crc_fifo_32x625_wrapper_underflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 mec0_cop_key_checksum_fifo_32x180_wrapper_overflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 mec0_cop_key_checksum_fifo_32x180_wrapper_underflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 mec0_cop_key_mul_fifo_32x52_wrapper_overflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 mec0_cop_key_mul_fifo_32x52_wrapper_underflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 mec0_cop_key_random_mod_fifo_32x44_wrapper_overflow_flag; /**< @brief fifo错误中断标记*/ + ZXIC_UINT32 mec0_cop_key_random_mod_fifo_32x44_wrapper_underflow_flag; /**< @brief fifo错误中断标记*/ +}DPP_PPU_PPU_COPROCESSOR_FIFO_INT_T; + + +typedef struct dpp_ppu_ppu_cos_meter_cfg_t +{ + ZXIC_UINT32 cbs; /**< @brief 0~7队列CBS配置*/ + ZXIC_UINT32 pbs; /**< @brief 0~7队列PBS配置*/ + ZXIC_UINT32 green_action; /**< @brief 0~7队列绿色报文动作配置，关闭CAR使能的时候，需要同时将该动作置为1*/ + ZXIC_UINT32 yellow_action; /**< @brief 0~7队列黄色报文动作配置*/ + ZXIC_UINT32 red_action; /**< @brief 0~7队列红色报文动作配置*/ + ZXIC_UINT32 cir; /**< @brief 0~7队列CIR配置，单位Mpps，0x24a对应600Mpps，按照线性变化*/ + ZXIC_UINT32 pir; /**< @brief 0~7队列PIR配置，单位Mpps，0x24a对应600Mpps，按照线性变化*/ + ZXIC_UINT32 car_en; /**< @brief 0~7队列CAR使能配置*/ +}DPP_PPU_PPU_COS_METER_CFG_T; + +#endif + +/***********************************************************/ +/** 配置SDT表 +* @param dev_id 设备号，范围0~3 +* @param cluster_id me cluster编号，范围0~7 +* @param index 地址，即sdt表号，范围0~255 +* @param p_sdt_data sdt表数据 +* +* @return +* @remark 无 +* @see +* @author 王春雷 @date 2014/03/18 +************************************************************/ +DPP_STATUS dpp_ppu_sdt_tbl_write(DPP_DEV_T *dev, ZXIC_UINT32 cluster_id, ZXIC_UINT32 index, DPP_SDT_TBL_DATA_T *p_sdt_data); + +#endif /* dpp_ppu_api.h */ diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_reg_api.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_reg_api.h new file mode 100755 index 0000000..b87c69e --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_reg_api.h @@ -0,0 +1,183 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_reg.h +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : wcl +* 完成日期 : 2014/02/12 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ + +#ifndef _DPP_REG_API_H_ +#define _DPP_REG_API_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "dpp_dev.h" +#include "dpp_reg_struct.h" + +/** 所有上层模块不需要直接使用该全局变量*/ +extern DPP_REG_T g_dpp_reg_info[]; + +/** public*/ +#define DPP_REG(no) (g_dpp_reg_info[no]) +#define DPP_REG_NAME(no) ((DPP_REG(no)).reg_name) +#define DPP_REG_NO(no) ((DPP_REG(no)).reg_no) +#define DPP_REG_MODULE_NO(no) ((DPP_REG(no)).module_no) +#define DPP_REG_FLAGS(no) ((DPP_REG(no)).flags) +#define DPP_REG_TYPE(no) ((DPP_REG(no)).array_type) +#define DPP_REG_ADDR(no) ((DPP_REG(no)).addr) +#define DPP_REG_WIDTH(no) ((DPP_REG(no)).width) +#define DPP_REG_M_SIZE(no) ((DPP_REG(no)).m_size) +#define DPP_REG_N_SIZE(no) ((DPP_REG(no)).n_size) +#define DPP_REG_M_STEP(no) ((DPP_REG(no)).m_step) +#define DPP_REG_N_STEP(no) ((DPP_REG(no)).n_step) +#define DPP_REG_FIELD_NUM(no) ((DPP_REG(no)).field_num) +#define DPP_REG_FIELD_NAME(no, field_no) (((DPP_REG(no)).p_fields+field_no)->p_name) + +typedef enum dpp_bar_4k_e +{ + BAR_4K_DTB = 0, /**< @brief 0*/ + BAR_4K_ETCAM, /**< @brief 1*/ + BAR_4K_CLS0, /**< @brief 2*/ + BAR_4K_CLS1, /**< @brief 3*/ + BAR_4K_CLS2, /**< @brief 4*/ + BAR_4K_CLS3, /**< @brief 5*/ + BAR_4K_CLS4, /**< @brief 6*/ + BAR_4K_CLS5, /**< @brief 7*/ + BAR_4K_SE, /**< @brief 8*/ + BAR_4K_SMMU1, /**< @brief 9*/ + BAR_4K_MAX +} DPP_BAR_4K_E; + +typedef struct +{ + ZXIC_UINT32 reg_module; /*DPP_MODULE_E*/ + ZXIC_UINT32 index_4k; /*BAR NP空间映射4K相对索引*/ + ZXIC_UINT32 addr_offset; /*寄存器偏移，用于计算BAR映射空间位置*/ +}DPP_REG_OFFSET_ADDR; + +/***********************************************************/ +/** 获取寄存器属性 +* @param reg_no 寄存器编号 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author 王春雷 @date 2014/04/17 +************************************************************/ +DPP_REG_T* dpp_reg_info_get(ZXIC_UINT32 reg_no); + +/***********************************************************/ +/** 通用寄存器写函数 +* @param dev_id 设备号，支持多芯片 +* @param reg_no 寄存器编号 +* @param m_offset 二元寄存器的m偏移 +* @param n_offset 一元寄存器或二元寄存器的n偏移 +* @param p_data 数据指针 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author 王春雷 @date 2014/02/12 +************************************************************/ +DPP_STATUS dpp_reg_write(DPP_DEV_T *dev, ZXIC_UINT32 reg_no, ZXIC_UINT32 m_offset, ZXIC_UINT32 n_offset, ZXIC_VOID *p_data); + +/***********************************************************/ +/** 通用寄存器读函数 +* @param dev_id 设备号，支持多芯片 +* @param reg_no 寄存器编号 +* @param m_offset 二元寄存器的m偏移 +* @param n_offset 一元寄存器或二元寄存器的n偏移 +* @param p_data 数据指针 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author 王春雷 @date 2014/02/12 +************************************************************/ +DPP_STATUS dpp_reg_read(DPP_DEV_T *dev, ZXIC_UINT32 reg_no, ZXIC_UINT32 m_offset, ZXIC_UINT32 n_offset, ZXIC_VOID *p_data); + +/***********************************************************/ +/** 根据寄存器编号获得寄存器芯片内绝对地址 +* @param reg_no +* @param m_offset +* @param n_offset +* +* @return +* @remark 无 +* @see +* @author 王春雷 @date 2014/03/19 +************************************************************/ +ZXIC_UINT32 dpp_reg_get_reg_addr(ZXIC_UINT32 reg_no, ZXIC_UINT32 m_offset, ZXIC_UINT32 n_offset); + +/***********************************************************/ +/** 通过寄存器编号配置寄存器，仅适用于32bit位宽 + 的常规寄存器 +* @param dev_id 设备号 +* @param reg_no 寄存器编号 +* @param m_offset 二元寄存器的m偏移 +* @param n_offset 一元寄存器或二元寄存器的n偏移 +* @param data 数据，32bit +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author 王春雷 @date 2015/01/21 +************************************************************/ +DPP_STATUS dpp_reg_write32(DPP_DEV_T *dev, ZXIC_UINT32 reg_no, ZXIC_UINT32 data); + +/***********************************************************/ +/** 通过寄存器编号读取寄存器的值，仅适用于32bit位宽的常规寄存器 +* @param dev_id 设备号 +* @param reg_no 寄存器编号 +* @param m_offset 二元寄存器的m偏移 +* @param n_offset 一元寄存器或二元寄存器的n偏移 +* @param p_data 出参，返回读取寄存器数值 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author 石金锋 @date 2015/03/09 +************************************************************/ +DPP_STATUS dpp_reg_read32(DPP_DEV_T *dev, ZXIC_UINT32 reg_no, ZXIC_UINT32 m_offset, ZXIC_UINT32 n_offset, ZXIC_UINT32 *p_data); +/***********************************************************/ +/** 判断是否为4K寄存器 +* @param reg_module +* +* @return +* @remark 无 +* @see +* @author cq @date 2023/11/29 +************************************************************/ +BOOLEAN dpp_4k_reg(ZXIC_UINT32 reg_module); +/***********************************************************/ +/** 获取NP对应模块的映射地址偏移(riscv或者非4K寄存器不做转换，host根据映射情况做转换) +* @param dev_id +* @param reg_module +* @param flags 标志位，DPP_REG_FLAG_INDIRECT DPP_REG_FLAG_DIRECT +* @param addr +* +* @return 映射地址 +* @remark 无 +* @see +* @author cq @date 2023/11/29 +************************************************************/ +ZXIC_UINT32 dpp_reg_addr_convert(ZXIC_UINT32 dev_id, ZXIC_UINT32 reg_module,ZXIC_UINT32 flags, ZXIC_UINT32 addr); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_se_api.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_se_api.h new file mode 100755 index 0000000..db5715c --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_se_api.h @@ -0,0 +1,1386 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_se_api.h +* 文件标识 : se模块对外数据类型定义和接口函数声明 +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : wcl +* 完成日期 : 2015/01/30 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ +#ifndef _DPP_SE_API_H_ +#define _DPP_SE_API_H_ + +#if ZXIC_REAL("header file") + #include "dpp_type_api.h" /* xcx_0619 */ +#endif + +#if ZXIC_REAL("data struct define") + +/** DPP+ 所有eram block 大小都变为2M ~深度是16K */ +#define SE_SMMU0_ERAM_BLOCK_NUM (32) +#define SE_SMMU0_ERAM_ADDR_NUM_PER_BLOCK (0x4000) +#define SE_SMMU0_ERAM_ADDR_NUM_TOTAL (SE_SMMU0_ERAM_BLOCK_NUM * SE_SMMU0_ERAM_ADDR_NUM_PER_BLOCK) + +#define DPP_DDR4_PER_BANK_BADDR_SETP (0x800)/* 8G X16 */ +#define DPP_DDR4_BANK_NUM (64) +#define DPP_DDR4_PER_BANK_BADDR_CONV(ddr4_phy_type) \ + (DPP_DDR4_PER_BANK_BADDR_SETP*(4U>>ddr4_phy_type)) + +/*普通上送上送类型*/ +typedef enum dpp_dma_ecc_en_e +{ + DMA_ECC_DISABLE = 0, + DMA_ECC_ENABLE = 1, +} DPP_DMA_ECC_EN_E; + +/** eRam表读请模式 */ +typedef enum dpp_eram128_rd_clr_mode_e +{ + RD_MODE_HOLD = 0, /**< @brief 正常读，读完数据不清空 */ + RD_MODE_CLEAR = 1, /**< @brief 读清模式，返回eram中的值 */ +} DPP_ERAM128_RD_CLR_MODE_E; + +/** eRam表cpu读写位宽模式*/ +typedef enum dpp_eram128_opr_mode_e +{ + ERAM128_OPR_128b = 0, /**< @brief 128bit模式读写eRam, 支持128bit读清模式*/ + ERAM128_OPR_64b = 1, /**< @brief 64bit模式读写eRam, 支持64bit 读清模式*/ + ERAM128_OPR_1b = 2, /**< @brief 1bit模式读写eRam, 不支持1bit 读清模式*/ + ERAM128_OPR_32b = 3 /**< @brief 32bit模式读eRam, 不能用于写，支持32bit 读清模式*/ +} DPP_ERAM128_OPR_MODE_E; + +/** eRam直接表位宽模式,也可用于eRam做结果表时的位宽 */ +typedef enum dpp_eram128_tbl_mode_e +{ + ERAM128_TBL_1b = 0, /**< @brief 1bit eRam片内直接表 */ + ERAM128_TBL_32b = 1, /**< @brief 32bit eRam片内直接表 */ + ERAM128_TBL_64b = 2, /**< @brief 64bit eRam片内直接表 */ + ERAM128_TBL_128b = 3, /**< @brief 128bit eRam片内直接表 */ + ERAM128_TBL_2b = 4, /**< @brief 2bit eRam片内直接表 */ + ERAM128_TBL_4b = 5, /**< @brief 4bit eRam片内直接表 */ + ERAM128_TBL_8b = 6, /**< @brief 8bit eRam片内直接表 */ + ERAM128_TBL_16b = 7 /**< @brief 16bit eRam片内直接表 */ +} DPP_ERAM128_TBL_MODE_E; + +/** eRam查表通道*/ +typedef enum smmu0_empty_type_e +{ + SMMU0_EMPTY_CLS0 = 0, /**< @brief PPU cluster0通道*/ + SMMU0_EMPTY_CLS1 = 1, /**< @brief PPU cluster1通道*/ + SMMU0_EMPTY_CLS2 = 2, /**< @brief PPU cluster2通道*/ + SMMU0_EMPTY_CLS3 = 3, /**< @brief PPU cluster3通道*/ + SMMU0_EMPTY_CLS4 = 4, /**< @brief PPU cluster4通道*/ + SMMU0_EMPTY_CLS5 = 5, /**< @brief PPU cluster5通道*/ + SMMU0_EMPTY_CLS6 = 6, /**< @brief PPU cluster6通道*/ + SMMU0_EMPTY_CLS7 = 7, /**< @brief PPU cluster7通道*/ + SMMU0_EMPTY_MCAST = 8, /**< @brief 组播复制表通道*/ + SMMU0_EMPTY_ODMA = 9, /**< @brief ODMA保序计数通道*/ +} SMMU0_EMPTY_TYPE_E; + +/** 组播报文类型*/ +typedef enum smmu0_mcast_tbl_type_e +{ + MCAST_TDM = 0, /**< @brief TDM组播报文*/ + MCAST_DATA = 1, /**< @brief 数据组播报文*/ + + MCAST_INVALID, /**< @brief 无效值 */ +} SMMU0_MCAST_TBL_TYPE_E; + +/** 调试计数读清模式 */ +typedef enum se_dbg_cnt_read_mode_e +{ + SE_DBG_CNT_READ_UNCLR = 0, /**< @brief 非读清模式 */ + SE_DBG_CNT_READ_CLR, /**< @brief 读清模式 */ +} SE_DBG_CNT_READ_MODE_E; + +/** 调试计数溢出模式 */ +typedef enum se_dbg_cnt_overflow_mode_e +{ + SE_DBG_CNT_OVERFLOW_UNREVERSE = 0, /**< @brief 溢出保持 */ + SE_DBG_CNT_OVERFLOW_REVERSE, /**< @brief 溢出翻转 */ +} SE_DBG_CNT_OVERFLOW_MODE_E; + +/** DDR颗粒类型*/ +typedef enum se_ddr_phy_cfg_type_e +{ + DPP_SE_DDR_PHY_32G_16 = 0, /**< @brief DDR颗粒每组32G容量,x16颗粒*/ + DPP_SE_DDR_PHY_16G_16, /**< @brief DDR颗粒每组16G容量,x16颗粒*/ + DPP_SE_DDR_PHY_8G_16, /**< @brief DDR颗粒每组8G容量,x16颗粒*/ + DPP_SE_DDR_PHY_4G_16, /**< @brief DDR颗粒每组4G容量,x16颗粒*/ + DPP_SE_DDR_PHY_32G_8, /**< @brief DDR颗粒每组32G容量,x8颗粒*/ + DPP_SE_DDR_PHY_16G_8, /**< @brief DDR颗粒每组16G容量,x8颗粒*/ + DPP_SE_DDR_PHY_8G_8, /**< @brief DDR颗粒每组8G容量,x8颗粒*/ + DPP_SE_DDR_PHY_4G_8, /**< @brief DDR颗粒每组4G容量,x8颗粒*/ + DPP_SE_DDR_PHY_MAX, +} SE_DDR_PHY_CFG_TYPE_E; + +/** DDR表写数据位宽模式*/ +typedef enum smmu1_ddr_wrt_mode_e +{ + SMMU1_DDR_WRT_128b = 0, /**< @brief 128bit模式写DDR*/ + SMMU1_DDR_WRT_256b = 1, /**< @brief 256bit模式写DDR*/ + SMMU1_DDR_WRT_384b = 2, /**< @brief 384bit模式写DDR*/ + SMMU1_DDR_WRT_512b = 3, /**< @brief 512bit模式写DDR*/ +} SMMU1_DDR_WRT_MODE_E; + +/** DDR表的共享模式 */ +typedef enum smmu1_ddr_share_mode_e +{ + SMMU1_DDR_SHARE_NO_SHARE = 0, /**< @brief SE 占用整个DDR*/ + SMMU1_DDR_SHARE_1_2 = 1, /**< @brief SE 占用1/2 DDR*/ + SMMU1_DDR_SHARE_1_4 = 2, /**< @brief SE 占用1/4 DDR*/ + SMMU1_DDR_SHARE_1_8 = 3, /**< @brief SE 占用1/8 DDR*/ + SMMU1_DDR_SHARE_MAX +} SMMU1_DDR_SHARE_MODE_E; + +/** 占用smmu1的表类型 */ +typedef enum smmu1_ddr_tbl_type_e +{ + SMMU1_DDR_TBL_TYPE_DIR_TBL = 0, /**< @brief 片外直接表 */ + SMMU1_DDR_TBL_TYPE_HASH_TBL = 1, /**< @brief HASH占用表 */ + SMMU1_DDR_TBL_TYPE_LPM_TBL = 2, /**< @brief LPM 占用表 */ + SMMU1_DDR_TBL_TYPE_OAM_TBL = 3, /**< @brief OAM 占用表 */ + SMMU1_DDR_TBL_TYPE_FTM_TBL = 4, /**< @brief FTM 占用表 */ + SMMU1_DDR_TBL_TYPE_ETM_TBL = 5, /**< @brief ETM 占用表 */ + SMMU1_DDR_TBL_TYPE_MAX +} SMMU1_DDR_TBL_TYPE_E; + +typedef enum cmmu_rd_mode_e +{ + CMMU_RD_MODE_29_35 = 0, + CMMU_RD_MODE_32 = 1, + CMMU_RD_MODE_64 = 2, + CMMU_RD_MODE_128 = 3, + CMMU_RD_MODE_MAX, +} CMMU_RD_OPR_MODE_E; + +/** CMMU读请模式 */ +typedef enum cmmu_rd_clr_mode_e +{ + CMMU_RD_CLR_MODE_UNCLR = 0, /**< @brief 正常读，读完数据不清空 */ + CMMU_RD_CLR_MODE_CLR = 1, /**< @brief 读清模式*/ + CMMU_RD_CLR_MODE_MAX, +} CMMU_RD_CLR_MODE_E; + +/** DDR表读数据位宽模式*/ +typedef enum smmu1_ddr_srh_mode_e +{ + SMMU1_DDR_SRH_128b = 0, /**< @brief 访问DDR，以128bit模式返回数据*/ + SMMU1_DDR_SRH_256b, /**< @brief 访问DDR，以256bit模式返回数据*/ + SMMU1_DDR_SRH_512b, /**< @brief 访问DDR，以512bit模式返回数据*/ + SMMU1_DDR_SRH_MAX +} SMMU1_DDR_SRH_MODE_E; + +/** DDR地址映射参数*/ +typedef struct se_ddr_addr_map_info_t +{ + ZXIC_UINT32 is_inited; /**< @brief 用于检测此结构体是否已经经过初始化 0xAA-已经初始化 其他值-未初始化 */ + ZXIC_UINT32 ddr_phy_type; /**< @brief DDR颗粒类型 0-32G,x16颗粒,1-16G,x16颗粒,2-8G,x16颗粒 */ + ZXIC_UINT32 se_use_bank_num; /**< @brief SE使用的bank数目 */ + ZXIC_UINT32 bank_used_sate[64]; /**< @brief 表示64个bank的使用状态 0-不存在 1-SE使用 2-PUB使用 3-FTM使用 4-ETM使用 */ +} SE_DDR_ADDR_MAP_INFO_T; + +/** se从ppu接收的查表请求排空状态*/ +typedef struct dpp_se_ept_flag_t +{ + ZXIC_UINT32 ppu5_ept_flag; /**< @brief se从ppu通道5接收的查表请求排空状态*/ + ZXIC_UINT32 ppu4_ept_flag; /**< @brief se从ppu通道4接收的查表请求排空状态*/ + ZXIC_UINT32 ppu3_ept_flag; /**< @brief se从ppu通道3接收的查表请求排空状态*/ + ZXIC_UINT32 ppu2_ept_flag; /**< @brief se从ppu通道2接收的查表请求排空状态*/ + ZXIC_UINT32 ppu1_ept_flag; /**< @brief se从ppu通道1接收的查表请求排空状态*/ + ZXIC_UINT32 ppu0_ept_flag; /**< @brief se从ppu通道0接收的查表请求排空状态*/ +} DPP_SE_EPT_FLAG_T; + +/** smmu0(eRam)各通道查表请求排空状态*/ +typedef struct dpp_smmu0_ept_flag_t +{ + ZXIC_UINT32 ept_flag8; /**< @brief odam请求排空状态*/ + ZXIC_UINT32 ept_flag7; /**< @brief odam tdm请求排空状态*/ + ZXIC_UINT32 ept_flag6; /**< @brief sa组播份数表请求排空状态*/ + ZXIC_UINT32 ept_flag5; /**< @brief ppu通道5查表请求排空状态*/ + ZXIC_UINT32 ept_flag4; /**< @brief ppu通道4查表请求排空状态*/ + ZXIC_UINT32 ept_flag3; /**< @brief ppu通道3查表请求排空状态*/ + ZXIC_UINT32 ept_flag2; /**< @brief ppu通道2查表请求排空状态*/ + ZXIC_UINT32 ept_flag1; /**< @brief ppu通道1查表请求排空状态*/ + ZXIC_UINT32 ept_flag0; /**< @brief ppu通道0查表请求排空状态*/ +} DPP_SMMU0_EPT_FLAG_T; + +/** SMMU0保序FIFO写满读空中断原因*/ +typedef struct dpp_se_smmu0_int0_t +{ + ZXIC_UINT32 dma_ordfifo; /**< @brief DMA保序fifo 写满读空标志*/ + ZXIC_UINT32 odma_ordfifo; /**< @brief ODMA保序fifo 写满读空标志*/ + ZXIC_UINT32 mcast_ordfifo; /**< @brief MCAST保序fifo 写满读空标志*/ +} DPP_SE_SMMU0_INT0_T; + +/* 数据组播报文类型 */ +typedef struct data_mcast_t_ +{ + ZXIC_UINT8 valid; /**< @brief valid 表示是否可用 */ + ZXIC_UINT8 rsv; /**< @brief rsv 保留位，字节对齐使用,勿需关心 */ + ZXIC_UINT16 mc_cnt; /**< @brief mc_cnt 16bit */ +} DATA_MCAST_T; + +/* TDM 组播报文类型 */ +typedef struct tdm_mcast_t_ +{ + ZXIC_UINT8 valid; /**< @brief valid 表示是否可用 */ + ZXIC_UINT8 rsv; /**< @brief rsv 保留位，字节对齐使用，勿需关心 */ + ZXIC_UINT8 bitmap[6]; /**< @brief bitmap[0]是最高位，bitmap[2]是最低位 */ +} TDM_MCAST_T; + +#endif + +#if ZXIC_REAL("eTcam data struct define") + +#endif + +#if ZXIC_REAL("interrupt data struct define") +/** SMMU0 中断状态 */ +typedef struct dpp_se_smmu0_int_t +{ + ZXIC_UINT32 smmu0_int0; + ZXIC_UINT32 smmu0_int1; + ZXIC_UINT32 smmu0_int2; + ZXIC_UINT32 smmu0_int3; + ZXIC_UINT32 smmu0_int4; + ZXIC_UINT32 smmu0_int5; + ZXIC_UINT32 smmu0_int6; + ZXIC_UINT32 smmu0_int7; + ZXIC_UINT32 smmu0_int8; + ZXIC_UINT32 smmu0_int9; + ZXIC_UINT32 smmu0_int10; + ZXIC_UINT32 smmu0_int11; + ZXIC_UINT32 smmu0_int12; + ZXIC_UINT32 smmu0_int13; + ZXIC_UINT32 smmu0_int14; + ZXIC_UINT32 smmu0_int15; + ZXIC_UINT32 smmu0_int16; + ZXIC_UINT32 smmu0_int17; + ZXIC_UINT32 smmu0_int18; + ZXIC_UINT32 smmu0_int19; + ZXIC_UINT32 smmu0_int20; + ZXIC_UINT32 smmu0_int21; + ZXIC_UINT32 smmu0_int22; + ZXIC_UINT32 smmu0_int23; + ZXIC_UINT32 smmu0_int24; + ZXIC_UINT32 smmu0_int25; + ZXIC_UINT32 smmu0_int26; + ZXIC_UINT32 smmu0_int27; + ZXIC_UINT32 smmu0_int28; + ZXIC_UINT32 smmu0_int29; + ZXIC_UINT32 smmu0_int30; + ZXIC_UINT32 smmu0_int31; + ZXIC_UINT32 smmu0_int32; + ZXIC_UINT32 smmu0_int33; + ZXIC_UINT32 smmu0_int34; + ZXIC_UINT32 smmu0_int35; + ZXIC_UINT32 smmu0_int36; + ZXIC_UINT32 smmu0_int37; + ZXIC_UINT32 smmu0_int38; + +}DPP_SE_SMMU0_INT_T; + +/** SMMU0 模块总的中断状态 */ +typedef struct dpp_smmu0_brief_int_t +{ + ZXIC_UINT32 smmu0_int14_unmask_flag; + ZXIC_UINT32 smmu0_int13_unmask_flag; + ZXIC_UINT32 smmu0_int12_unmask_flag; + ZXIC_UINT32 smmu0_int11_unmask_flag; + ZXIC_UINT32 smmu0_int10_unmask_flag; + ZXIC_UINT32 smmu0_int9_unmask_flag; + ZXIC_UINT32 smmu0_int8_unmask_flag; + ZXIC_UINT32 smmu0_int7_unmask_flag; + ZXIC_UINT32 smmu0_int6_unmask_flag; + ZXIC_UINT32 smmu0_int5_unmask_flag; + ZXIC_UINT32 smmu0_int4_unmask_flag; + ZXIC_UINT32 smmu0_int3_unmask_flag; + ZXIC_UINT32 smmu0_int2_unmask_flag; + ZXIC_UINT32 smmu0_int1_unmask_flag; + ZXIC_UINT32 smmu0_int0_unmask_flag; +} DPP_SMMU0_BRIEF_INT_T; + +/** SE 模块总的中断状态 */ +typedef struct dpp_se_int_status_t +{ + ZXIC_UINT32 as_int_unmask_flag; /**< @brief 级联查找模块（AS）总中断状态 */ + ZXIC_UINT32 kschd_int_unmask_flag; /**< @brief 键值调度模块（KSCHD）总中断状态 */ + ZXIC_UINT32 rschd_int_unmask_flag; /**< @brief 返回调度模块（RSCHD）总中断状态 */ + ZXIC_UINT32 smmu1_int_unmask_flag; /**< @brief SMMU1 中断总中断状态 */ + ZXIC_UINT32 cmmu_int_unmask_flag; /**< @brief CMMU 总中断状态 */ + ZXIC_UINT32 parser_int_unmask_flag; /**< @brief 解析模块（parse）总中断状态 */ +} DPP_SE_INT_STATUS_T; + +/** se解析模块中断状态 */ +typedef struct dpp_se_parser_int_t +{ + ZXIC_UINT32 parser_int_en; + ZXIC_UINT32 parser_int_mask; + ZXIC_UINT32 parser_int_status; +} DPP_SE_PARSER_INT_T; + +/** key调度模块(KSCHD)中断状态 */ +typedef struct dpp_se_kschd_int_t +{ + ZXIC_UINT32 kschd_int_0; + ZXIC_UINT32 kschd_int_1; + ZXIC_UINT32 kschd_int_2; + ZXIC_UINT32 kschd_int_3; + ZXIC_UINT32 kschd_int_4; +} DPP_SE_KSCHD_INT_T; + +/** rsp调度模块(RSCHD)中断状态 */ +typedef struct dpp_se_rschd_int_t +{ + ZXIC_UINT32 port0_int; + ZXIC_UINT32 port1_int; +} DPP_SE_RSCHD_INT_T; + +/** 关联查找(AS)模块的中断原因*/ +typedef struct dpp_se_as_int_t +{ + ZXIC_UINT32 as_int_0; + ZXIC_UINT32 as_int_1; + ZXIC_UINT32 as_int_2; +} DPP_SE_AS_INT_T; + +/** cmmu 模块中断*/ +typedef struct dpp_se_cmmu_int_t +{ + ZXIC_UINT32 cmmu_int12; + ZXIC_UINT32 cmmu_int11; + ZXIC_UINT32 cmmu_int10; + ZXIC_UINT32 cmmu_int9; + ZXIC_UINT32 cmmu_int8; + ZXIC_UINT32 cmmu_int7; + ZXIC_UINT32 cmmu_int6; + ZXIC_UINT32 cmmu_int5; + ZXIC_UINT32 cmmu_int4; + ZXIC_UINT32 cmmu_int3; + ZXIC_UINT32 cmmu_int2; + ZXIC_UINT32 cmmu_int1; + ZXIC_UINT32 cmmu_int0; +} DPP_SE_CMMU_INT_T; + +/** ALG 模块中断*/ +typedef struct dpp_se_alg_int_t +{ + ZXIC_UINT32 wr_rsp_fifo_ovfl_int; /**< @brief 写返回缓存ptr fifo 溢出中断上报 */ + ZXIC_UINT32 init_rd_cft_int; /**< @brief 初始化过程中出现读命令，冲突中断 */ + ZXIC_UINT32 schd_lpm_fifo_parity_err_int; /**< @brief 调度lpm缓存FIFO奇偶校验错误上报 */ + ZXIC_UINT32 schd_hash3_fifo_parity_err_int; /**< @brief 调度hash3缓存FIFO奇偶校验错误上报 */ + ZXIC_UINT32 schd_hash2_fifo_parity_err_int; /**< @brief 调度hash2缓存FIFO奇偶校验错误上报 */ + ZXIC_UINT32 schd_hash1_fifo_parity_err_int; /**< @brief 调度hash1缓存FIFO奇偶校验错误上报 */ + ZXIC_UINT32 schd_hash0_fifo_parity_err_int; /**< @brief 调度hash0缓存FIFO奇偶校验错误上报 */ + ZXIC_UINT32 schd_learn_fifo_parity_err_int; /**< @brief 调度学习缓存FIFO奇偶校验错误上报 */ + ZXIC_UINT32 schd_lpm_fifo_ovfl_int; /**< @brief 调度lpm键值缓存FIFO溢出中断上报 */ + ZXIC_UINT32 schd_hash3_fifo_ovfl_int; /**< @brief 调度hash3键值缓存FIFO溢出中断上报 */ + ZXIC_UINT32 schd_hash2_fifo_unfl_int; /**< @brief 调度hash2键值缓存FIFO溢出中断上报 */ + ZXIC_UINT32 schd_hash1_fifo_ovfl_int; /**< @brief 调度hash1键值缓存FIFO溢出中断上报 */ + ZXIC_UINT32 schd_hash0_fifo_ovfl_int; /**< @brief 调度hash0键值缓存FIFO溢出中断上报 */ + ZXIC_UINT32 schd_learn_fifo_ovfl_int; /**< @brief 调度学习命令缓存FIFO溢出中断上报 */ + + ZXIC_UINT32 zblk31_parity_int; /**< @brief zblock31 parity 中断 */ + ZXIC_UINT32 zblk30_parity_int; /**< @brief zblock30 parity 中断 */ + ZXIC_UINT32 zblk29_parity_int; /**< @brief zblock29 parity 中断 */ + ZXIC_UINT32 zblk28_parity_int; /**< @brief zblock28 parity 中断 */ + ZXIC_UINT32 zblk27_parity_int; /**< @brief zblock27 parity 中断 */ + ZXIC_UINT32 zblk26_parity_int; /**< @brief zblock26 parity 中断 */ + ZXIC_UINT32 zblk25_parity_int; /**< @brief zblock25 parity 中断 */ + ZXIC_UINT32 zblk24_parity_int; /**< @brief zblock24 parity 中断 */ + ZXIC_UINT32 zblk23_parity_int; /**< @brief zblock23 parity 中断 */ + ZXIC_UINT32 zblk22_parity_int; /**< @brief zblock22 parity 中断 */ + ZXIC_UINT32 zblk21_parity_int; /**< @brief zblock21 parity 中断 */ + ZXIC_UINT32 zblk20_parity_int; /**< @brief zblock20 parity 中断 */ + ZXIC_UINT32 zblk19_parity_int; /**< @brief zblock19 parity 中断 */ + ZXIC_UINT32 zblk18_parity_int; /**< @brief zblock18 parity 中断 */ + ZXIC_UINT32 zblk17_parity_int; /**< @brief zblock17 parity 中断 */ + ZXIC_UINT32 zblk16_parity_int; /**< @brief zblock16 parity 中断 */ + ZXIC_UINT32 zblk15_parity_int; /**< @brief zblock15 parity 中断 */ + ZXIC_UINT32 zblk14_parity_int; /**< @brief zblock14 parity 中断 */ + ZXIC_UINT32 zblk13_parity_int; /**< @brief zblock13 parity 中断 */ + ZXIC_UINT32 zblk12_parity_int; /**< @brief zblock12 parity 中断 */ + ZXIC_UINT32 zblk11_parity_int; /**< @brief zblock11 parity 中断 */ + ZXIC_UINT32 zblk10_parity_int; /**< @brief zblock10 parity 中断 */ + ZXIC_UINT32 zblk9_parity_int; /**< @brief zblock9 parity 中断 */ + ZXIC_UINT32 zblk8_parity_int; /**< @brief zblock8 parity 中断 */ + ZXIC_UINT32 zblk7_parity_int; /**< @brief zblock7 parity 中断 */ + ZXIC_UINT32 zblk6_parity_int; /**< @brief zblock6 parity 中断 */ + ZXIC_UINT32 zblk5_parity_int; /**< @brief zblock5 parity 中断 */ + ZXIC_UINT32 zblk4_parity_int; /**< @brief zblock4 parity 中断 */ + ZXIC_UINT32 zblk3_parity_int; /**< @brief zblock3 parity 中断 */ + ZXIC_UINT32 zblk2_parity_int; /**< @brief zblock2 parity 中断 */ + ZXIC_UINT32 zblk1_parity_int; /**< @brief zblock1 parity 中断 */ + ZXIC_UINT32 zblk0_parity_int; /**< @brief zblock0 parity 中断 */ + + ZXIC_UINT32 zcam_hash_p0_err_int; /**< @brief hash0 ZCAM查找出错中断 */ + ZXIC_UINT32 hash0_agree_int_fifo_ovf_int; /**< @brief hash0 汇聚fifo 片内通道溢出中断 */ + ZXIC_UINT32 hash0_agree_ext_fifo_ovf_int; /**< @brief hash0 汇聚fifo 片外通道parity中断 */ + ZXIC_UINT32 hash0_agree_ext_fifo_parity_err_int; /**< @brief hash0 汇聚fifo 片外通道溢出中断*/ + ZXIC_UINT32 hash0_agree_int_fifo_parity_err_int; /**< @brief hash0 汇聚fifo 片内通道parity中断 */ + ZXIC_UINT32 hash0_key_fifo_ovfl_int; /**< @brief hash0 片外键值缓存FIFO 溢出中断 */ + ZXIC_UINT32 hash0_sreq_fifo_ovfl_int; /**< @brief hash0 片外读地址缓存FIFO溢出中断 */ + ZXIC_UINT32 hash0_key_fifo_parity_err_int; /**< @brief hash0 片外键值缓存FIFO parity err中断 */ + + ZXIC_UINT32 zcam_hash_p1_err_int; /**< @brief hash1 ZCAM查找出错中断 */ + ZXIC_UINT32 hash1_agree_int_fifo_ovf_int; /**< @brief hash1 汇聚fifo 片内通道溢出中断 */ + ZXIC_UINT32 hash1_agree_ext_fifo_ovf_int; /**< @brief hash1 汇聚fifo 片外通道parity中断 */ + ZXIC_UINT32 hash1_agree_ext_fifo_parity_err_int; /**< @brief hash1 汇聚fifo 片外通道溢出中断*/ + ZXIC_UINT32 hash1_agree_int_fifo_parity_err_int; /**< @brief hash1 汇聚fifo 片内通道parity中断 */ + ZXIC_UINT32 hash1_key_fifo_ovfl_int; /**< @brief hash1 片外键值缓存FIFO 溢出中断 */ + ZXIC_UINT32 hash1_sreq_fifo_ovfl_int; /**< @brief hash1 片外读地址缓存FIFO溢出中断 */ + ZXIC_UINT32 hash1_key_fifo_parity_err_int; /**< @brief hash1 片外键值缓存FIFO parity err中断 */ + + ZXIC_UINT32 zcam_hash_p2_err_int; /**< @brief hash2 ZCAM查找出错中断 */ + ZXIC_UINT32 hash2_agree_int_fifo_ovf_int; /**< @brief hash2 汇聚fifo 片内通道溢出中断 */ + ZXIC_UINT32 hash2_agree_ext_fifo_ovf_int; /**< @brief hash2 汇聚fifo 片外通道parity中断 */ + ZXIC_UINT32 hash2_agree_ext_fifo_parity_err_int; /**< @brief hash2 汇聚fifo 片外通道溢出中断*/ + ZXIC_UINT32 hash2_agree_int_fifo_parity_err_int; /**< @brief hash2 汇聚fifo 片内通道parity中断 */ + ZXIC_UINT32 hash2_key_fifo_ovfl_int; /**< @brief hash2 片外键值缓存FIFO 溢出中断 */ + ZXIC_UINT32 hash2_sreq_fifo_ovfl_int; /**< @brief hash2 片外读地址缓存FIFO溢出中断 */ + ZXIC_UINT32 hash2_key_fifo_parity_err_int; /**< @brief hash2 片外键值缓存FIFO parity err中断 */ + + ZXIC_UINT32 zcam_hash_p3_err_int; /**< @brief hash3 ZCAM查找出错中断 */ + ZXIC_UINT32 hash3_agree_int_fifo_ovf_int; /**< @brief hash3 汇聚fifo 片内通道溢出中断 */ + ZXIC_UINT32 hash3_agree_ext_fifo_ovf_int; /**< @brief hash3 汇聚fifo 片外通道parity中断 */ + ZXIC_UINT32 hash3_agree_ext_fifo_parity_err_int; /**< @brief hash3 汇聚fifo 片外通道溢出中断*/ + ZXIC_UINT32 hash3_agree_int_fifo_parity_err_int; /**< @brief hash3 汇聚fifo 片内通道parity中断 */ + ZXIC_UINT32 hash3_key_fifo_ovfl_int; /**< @brief hash3 片外键值缓存FIFO 溢出中断 */ + ZXIC_UINT32 hash3_sreq_fifo_ovfl_int; /**< @brief hash3 片外读地址缓存FIFO溢出中断 */ + ZXIC_UINT32 hash3_key_fifo_parity_err_int; /**< @brief hash3 片外键值缓存FIFO parity err中断 */ + + ZXIC_UINT32 zcam_lpm_err_int; /**< @brief lpm ZCAM查找出错中断 */ + ZXIC_UINT32 lpm_as_int_rsp_fifo_ovfl_int; /**< @brief lpm as 片内查找结果缓存FIFO溢出中断 */ + ZXIC_UINT32 lpm_as_req_fifo_ovfl_int; /**< @brief lpm as 查找ddr 地址 FIFO溢出中断 */ + ZXIC_UINT32 lpm_ext_ddr_rsp_fifo_parity_int; /**< @brief lpm ext ddr rsp FIFO parity中断 */ + ZXIC_UINT32 lpm_ext_v6_key_parity_int; /**< @brief lpm ext v6 key FIFO parity中断 */ + ZXIC_UINT32 lpm_ext_v4_key_parity_int; /**< @brief lpm ext v4 key FIFO parity中断 */ + ZXIC_UINT32 lpm_ext_addr_fifo_ovfl_int; /**< @brief lpm ext ddr3 地址溢出中断 */ + ZXIC_UINT32 lpm_ext_v4_fifo_ovfl_int; /**< @brief lpm ext v4 key溢出中断 */ + ZXIC_UINT32 lpm_ext_v6_fifo_ovfl_int; /**< @brief lpm ext v6 key溢出中断 */ + ZXIC_UINT32 lpm_ext_ddr_rsp_ovf_int; /**< @brief lpm ext ddr返回缓存fifo溢出中断 */ +} DPP_SE_ALG_INT_T; + +/** ALG 模块对外总中断*/ +typedef struct dpp_se_alg_brief_int_t +{ + ZXIC_UINT32 schd_int_unmask_flag; /**<@brief alg模块调度状态 */ + ZXIC_UINT32 zblk_parity_int_unmask_flag; /**<@brief alg模块zblock奇偶校验中断 */ + ZXIC_UINT32 hash0_int_unmask_flag; /**<@brief alg模块hash0中断状态 */ + ZXIC_UINT32 hash1_int_unmask_flag; /**<@brief alg模块hash1中断状态 */ + ZXIC_UINT32 hash2_int_unmask_flag; /**<@brief alg模块hash2中断状态 */ + ZXIC_UINT32 hash3_int_unmask_flag; /**<@brief alg模块hash3中断状态 */ + ZXIC_UINT32 lpm_int_unmask_flag; /**<@brief alg模块lpm中断状态 */ +} DPP_SE_ALG_BRIEF_INT_T; + +/** SMMU1 中断 */ +typedef struct dpp_se_smmu1_int_t +{ + ZXIC_UINT32 smmu1_int0; + ZXIC_UINT32 smmu1_int1; + ZXIC_UINT32 smmu1_int2; + ZXIC_UINT32 smmu1_int3; + ZXIC_UINT32 smmu1_int4; + ZXIC_UINT32 smmu1_int5; + ZXIC_UINT32 smmu1_int6; + ZXIC_UINT32 smmu1_int7; + ZXIC_UINT32 smmu1_int8; + ZXIC_UINT32 smmu1_int9; + ZXIC_UINT32 smmu1_int10; + ZXIC_UINT32 smmu1_int11; + ZXIC_UINT32 smmu1_int12; + ZXIC_UINT32 smmu1_int13; + ZXIC_UINT32 smmu1_int14; + ZXIC_UINT32 smmu1_int15; + ZXIC_UINT32 smmu1_int16; + ZXIC_UINT32 smmu1_int17; +} DPP_SE_SMMU1_INT_T; + +typedef struct dpp_etcam_intr_t +{ + ZXIC_UINT32 etcam_int_33; + ZXIC_UINT32 etcam_int_32; + ZXIC_UINT32 etcam_int_31; + ZXIC_UINT32 etcam_int_30; + ZXIC_UINT32 etcam_int_29; + ZXIC_UINT32 etcam_int_28; + ZXIC_UINT32 etcam_int_27; + ZXIC_UINT32 etcam_int_26; + ZXIC_UINT32 etcam_int_25; + ZXIC_UINT32 etcam_int_24; + ZXIC_UINT32 etcam_int_23; + ZXIC_UINT32 etcam_int_22; + ZXIC_UINT32 etcam_int_21; + ZXIC_UINT32 etcam_int_20; + ZXIC_UINT32 etcam_int_19; + ZXIC_UINT32 etcam_int_18; + ZXIC_UINT32 etcam_int_17; + ZXIC_UINT32 etcam_int_16; + ZXIC_UINT32 etcam_int_15; + ZXIC_UINT32 etcam_int_14; + ZXIC_UINT32 etcam_int_13; + ZXIC_UINT32 etcam_int_12; + ZXIC_UINT32 etcam_int_11; + ZXIC_UINT32 etcam_int_10; + ZXIC_UINT32 etcam_int_9; + ZXIC_UINT32 etcam_int_8; + ZXIC_UINT32 etcam_int_7; + ZXIC_UINT32 etcam_int_6; + ZXIC_UINT32 etcam_int_5; + ZXIC_UINT32 etcam_int_4; + ZXIC_UINT32 etcam_int_3; + ZXIC_UINT32 etcam_int_2; + ZXIC_UINT32 etcam_int_1; + ZXIC_UINT32 etcam_int_0; +} DPP_ETCAM_INTR_T; + +typedef struct dpp_se_stat_int_t +{ + ZXIC_UINT32 stat_int0; + ZXIC_UINT32 stat_int1; + ZXIC_UINT32 stat_int2; + ZXIC_UINT32 stat_int3; + ZXIC_UINT32 stat_int4; + ZXIC_UINT32 stat_int5; +} DPP_SE_STAT_INT_T; + +#endif + +#if ZXIC_REAL("macro function define") + +#endif + +#if ZXIC_REAL("function declaration") +/***********************************************************/ +/** 读eRam +* @param dev_id 设备号 +* @param base_addr 基地址，以128bit为单位 +* @param index 条目索引,支持128、64、32和1bit的索引值 +* @param rd_mode 读eRam模式, 取值参照ERAM128_OPR_MODE_E定义，读清模式下不支持1bit模式 +* @param rd_clr_mode eRam读清模式, 取值参照ERAM128_RD_CLR_MODE_E定义 +* @param p_data 返回数据缓存的指针 +* +* @return +* @remark 无 +* @see +* @author wcl @date 2015/01/30 +************************************************************/ +DPP_STATUS dpp_se_smmu0_ind_read(DPP_DEV_T *dev, ZXIC_UINT32 base_addr, ZXIC_UINT32 index, ZXIC_UINT32 rd_mode, ZXIC_UINT32 rd_clr_mode, ZXIC_UINT32 *p_data); + +#endif + +#if ZXIC_REAL("Hash & LPM data struct and function") + +/** lpm&hash算法模块硬件读写函数指针类型 */ +typedef DPP_STATUS (*WRITE32_FUN)(ZXIC_UINT32 dev_id, ZXIC_UINT32 addr, ZXIC_UINT32 write_data); +typedef DPP_STATUS (*READ32_FUN) (ZXIC_UINT32 dev_id, ZXIC_UINT32 addr, ZXIC_UINT32 *read_data); + +/** 前缀匹配路由关联结果表写硬件函数指针类型*/ +typedef DPP_STATUS (*LPM_AS_RSLT_WRT_FUNCTION)(ZXIC_UINT32 dev_id, ZXIC_UINT32 as_type, ZXIC_UINT32 tbl_id, ZXIC_UINT32 index, ZXIC_UINT8 *p_data); + +#define SE_ZGRP_NUM (4) +#define SE_ZBLK_NUM (32) +#define SE_ZCELL_NUM (4) +#define SE_ZCELL_TOTAL_NUM (SE_ZBLK_NUM * SE_ZCELL_NUM) +#define SE_ZREG_NUM (4) +#define SE_RAM_DEPTH (512) +#define MAX_FUN_NUM (8) +#define SE_ALG_BANK_NUM (29) + +#define LPM_THREAD_HW_WRITE_EN (0) /* ??????????????? */ +#if LPM_THREAD_HW_WRITE_EN +#define ROUTE_DEV_CHANNEL_MAX (4) /* ?????? NPE_DEV_CHANNEL_MAX ??????? */ +#define MAX_ITEM_INFO_BAK_NUM (0x100) +#endif +/* +* zcell/zreg 基本存储单元的配置信息,512bit为单位， +* zcell包含512个基本存储单元，zreg包含4个基本存储单元， +* 每个单元可以存储1个512bit条目、2个256bit条目或4个128bit条目， +* 本结构体不感知内部存储条目的位宽，hash中键值中的key_type可以 +* 可以获取表项的位宽信息 +*/ +typedef struct se_item_cfg +{ + D_HEAD item_list; /** 基本存储单元双链表头节点，可以存放放在本单元内的具体表项条目*/ + ZXIC_UINT32 item_index; /** 基本存储单元所处的索引值 */ + ZXIC_UINT32 hw_addr; /** 基本存储单元物理的地址 */ + ZXIC_UINT32 bulk_id; + ZXIC_UINT32 item_type; /** 基本存储单元的存储类型，包括片外或片内，参见SE_ITEM_TYPE */ + ZXIC_UINT8 wrt_mask; /** 基本存储单元写入的掩码，4bit，每bit表示待写入的128bit位置 */ + ZXIC_UINT8 valid; /** 基本存储单元是否被占用，0-未被占用，1-被占用 */ + ZXIC_UINT8 pad[2]; +} SE_ITEM_CFG; + +/** zcell属性标志*/ +#define DPP_ZCELL_FLAG_IS_MONO (1) /**< @brief ZCELL是否被独占: 0-未被独占，1-已经被独占*/ + +/** zcell属性标志*/ +#define DPP_ZREG_FLAG_IS_MONO (1) /**< @brief ZREG是否被独占: 0-未被独占，1-已经被独占*/ + +/* zcell 的配置信息*/ +typedef struct se_zcell_cfg +{ + ZXIC_UINT8 flag; /* zcell属性标志，各比特的含义见上面DPP_ZCELL_FLAG_MODE等的定义 */ + ZXIC_UINT32 bulk_id; /* zcell所属空间ID */ + ZXIC_UINT32 zcell_idx; /* zcell 的索引值, 高6bit为zblock的索引 */ + ZXIC_UINT16 mask_len; /* 掩码长度 */ + ZXIC_UINT8 is_used; /* 本zcell是否被占用*/ + ZXIC_UINT8 is_share; /* 是否共享block中的zcell*/ + ZXIC_UINT32 item_used; + SE_ITEM_CFG item_info[SE_RAM_DEPTH]; /* 本zcell的基本存储单元配置*/ + + D_NODE zcell_dn; /* 双链表节点，初始化其data指针指向SE_ZCELL_CFG实例自身，然后插入双链表中*/ + ZXIC_AVL_NODE zcell_avl; /* 本hash程序未使用， 平衡二叉树节点*/ +} SE_ZCELL_CFG; +/* zreg 的配置信息*/ +typedef struct se_zreg_cfg +{ + ZXIC_UINT8 flag; /* z属性标志，各比特的含义见上面DPP_ZCELL_FLAG_MODE等的定义 */ + ZXIC_UINT8 pad[3]; + ZXIC_UINT32 bulk_id; /* zcell所属空间ID */ + SE_ITEM_CFG item_info; /* zreg 存储的表条目配置*/ +} SE_ZREG_CFG; +/* zblock 的配置信息*/ +typedef struct se_zblk_cfg +{ + ZXIC_UINT32 zblk_idx; /* 统一编址，范围0~31 */ + ZXIC_UINT16 is_used; /* 本zblock 是否被占用 */ + ZXIC_UINT16 zcell_bm; /* 本hash程序未使用 */ + ZXIC_UINT16 hash_arg; /* hash crc算法的因子 */ + ZXIC_UINT16 pad; + + SE_ZCELL_CFG zcell_info[SE_ZCELL_NUM]; /* 本block的4个zcell配置 */ + SE_ZREG_CFG zreg_info[SE_ZREG_NUM]; /* 本block的4个zreg配置*/ + + D_NODE zblk_dn; /* 指向本实例的双链表节点 */ + +} SE_ZBLK_CFG; +/* alg表类型配置，包括4路hash引擎和v4 和 v6 lpm表项*/ +typedef struct func_id_info +{ + ZXIC_VOID *fun_ptr; + ZXIC_UINT8 fun_type; /* 业务类型 参见 SE_FUN_TYPE */ + ZXIC_UINT8 fun_id; + ZXIC_UINT8 is_used; + ZXIC_UINT8 pad; +} FUNC_ID_INFO; + +typedef struct ddr_mem +{ + ZXIC_UINT32 total_num; + ZXIC_UINT32 base_addr; + ZXIC_UINT32 base_addr_offset; + ZXIC_UINT32 ecc_en; + ZXIC_UINT32 bank_num; + ZXIC_UINT32 bank_info[SE_ALG_BANK_NUM]; + ZXIC_UINT32 share_type; /* DDR bank共享模式 */ + ZXIC_UINT32 item_used; + ZXIC_LISTSTACK_MANGER *p_ddr_mng; +} DDR_MEM; + +typedef struct share_ram +{ + ZXIC_UINT32 zblk_array[SE_ZBLK_NUM]; + D_HEAD zblk_list; + D_HEAD zcell_free_list; + ZXIC_UINT32 def_route_num; + + ZXIC_RB_CFG def_rb; + struct def_route_info *p_dr_info; + + DDR_MEM ddr4_info; + DDR_MEM ddr6_info; +} SHARE_RAM; + +/** 算法模块管理数据结构，用户仅需创建实例变量，然后将指针传给初始化函数dpp_se_init()和dpp_se_client_init()即可，不需要单独赋值成员变量*/ +typedef struct dpp_se_cfg +{ + SE_ZBLK_CFG zblk_info[SE_ZBLK_NUM]; + + FUNC_ID_INFO fun_info[MAX_FUN_NUM]; + + SHARE_RAM route_shareram; + ZXIC_UINT32 reg_base; + + WRITE32_FUN p_write32_fun; + READ32_FUN p_read32_fun; + + ZXIC_UINT32 lpm_flags; + + ZXIC_VOID *p_client; + + DPP_DEV_T *dev; + ZXIC_UINT32 dev_id; + + LPM_AS_RSLT_WRT_FUNCTION p_as_rslt_wrt_fun; /* dpp_se_lpm_as_rslt_write */ + +#if LPM_THREAD_HW_WRITE_EN + // ZXIC_UINT32 mutex_location; /* dpp_route_cfg ?? cache mutex???????????route mode */ + ZXIC_MUTEX_T cache_index_mutex[MAX_ITEM_INFO_BAK_NUM]; /* cache每个节点锁 */ + ZXIC_UINT32 thread_hw_write_is_create; /* ??????????????? ???????? add by lining for thread_hw_write */ + ZXIC_LISTSTACK_MANGER *p_thread_liststack_mng; +#endif + +} DPP_SE_CFG; + +/** hash物理存储位宽类型*/ +typedef enum dpp_hash_ddr_width_mode +{ + DDR_WIDTH_INVALID = 0, + DDR_WIDTH_256b, /**< @brief 256bit位宽模式*/ + DDR_WIDTH_512b, /**< @brief 512bit位宽模式*/ +} DPP_HASH_DDR_WIDTH_MODE; + +/** hash条目类型*/ +typedef enum dpp_hash_key_type +{ + HASH_KEY_INVALID = 0, /**< @brief 无效类型*/ + HASH_KEY_128b, /**< @brief 128bit位宽类型*/ + HASH_KEY_256b, /**< @brief 256bit位宽类型*/ + HASH_KEY_512b, /**< @brief 512bit位宽类型*/ +} DPP_HASH_KEY_TYPE; + +/** hash ddr resource cfg info*/ +typedef struct dpp_hash_ddr_resc_cfg_t +{ + ZXIC_UINT32 ddr_width_mode; /**< @brief 分配给hash的DDR空间物理存储位宽模式，取值参考DPP_HASH_DDR_WIDTH_MODE的定义*/ + ZXIC_UINT32 ddr_crc_sel; /**< @brief 选择一个DDR CRC多项式，取值范围0~3,0~3分别对应一个CRC多项式*/ + ZXIC_UINT32 ddr_item_num; /**< @brief 分配给hash的DDR空间单元数目，以256bit为一个单元*/ + ZXIC_UINT32 ddr_baddr; /**< @brief 分配给hash的DDR空间的硬件基地址,以2k*256bit为单位*/ + ZXIC_UINT32 ddr_ecc_en; /**< @brief DDR ECC使能: 0-不使能，1-使能*/ +} DPP_HASH_DDR_RESC_CFG_T; + +/** hash search mode */ +typedef enum dpp_hash_srh_mode +{ + HASH_SRH_MODE_SOFT = 1, /**< @brief 查软件 */ + HASH_SRH_MODE_HDW = 2, /**< @brief 查硬件 */ +} DPP_HASH_SRH_MODE; + +/** hash tbl_flag */ +#define HASH_TBL_FLAG_AGE (1<<0) /**< @brief 老化保活置位使能: 0-不使能；1-使能*/ +#define HASH_TBL_FLAG_LEARN (1<<1) /**< @brief 硬件学习使能: 0-不使能；1-使能*/ +#define HASH_TBL_FLAG_MC_WRT (1<<2) /**< @brief 微码写表使能: 0-不使能，1-使能 */ + +/** hash条目*/ +typedef struct dpp_hash_entry +{ + ZXIC_UINT8 *p_key; /**< @brief 键值，格式详见各操作函数的说明*/ + ZXIC_UINT8 *p_rst; /**< @brief 结果*/ +} DPP_HASH_ENTRY; + + +/** 前缀路由业务初始化标志*/ +#define LPM_FLAG_RT_HANDLE_START (0) /**< @brief 是否使能级联结果表查找: 0-不使能，1-使能*/ +#define LPM_FLAG_RT_HANDLE_WIDTH (1) +#define LPM4_FLAG_DDR_EN_START (1) /**< @brief 是否使能ipv4片外查找模式: 0-不使能，1-使能 */ +#define LPM4_FLAG_DDR_EN_WIDTH (1) +#define LPM6_FLAG_DDR_EN_START (2) /**< @brief 是否使能ipv6片外查找模式: 0-不使能，1-使能 */ +#define LPM6_FLAG_DDR_EN_WIDTH (1) +#define LPM4_FLAG_DDR_SEL_START (3) /**< @brief 是否为ipv4非线速模式: 0-线速，1-非线速 */ +#define LPM4_FLAG_DDR_SEL_WIDTH (1) +#define LPM6_FLAG_DDR_SEL_START (4) /**< @brief 是否为ipv6非线速模式: 0-线速，1-非线速 */ +#define LPM6_FLAG_DDR_SEL_WIDTH (1) +#define LPM_FLAG_AS_MODE_START (5) /**< @brief 级联结果表模式: 1-级联DDR，0-级联eRam */ +#define LPM_FLAG_AS_MODE_WIDTH (1) + +/** 前缀匹配路由级联DDR结果表返回位宽模式*/ +typedef enum dpp_route_as_rsp_len_e +{ + DPP_ROUTE_AS_128b = 0, /**< @brief 返回128bit模式*/ + DPP_ROUTE_AS_256b = 1, /**< @brief 返回256bit模式*/ + DPP_ROUTE_AS_384b = 2, /**< @brief 返回384bit模式*/ + DPP_ROUTE_AS_512b = 3 /**< @brief 返回512bit模式*/ +} DPP_ROUTE_AS_RSP_LEN_E; + +/** 前缀匹配路由业务ID*/ +typedef enum dpp_route_id_e +{ + DPP_ROUTE_V4_ID = 4, /**< @brief route ipv4 ID*/ + DPP_ROUTE_V6_ID = 5, /**< @brief route ipv6 ID*/ +} DPP_ROUTE_ID_E; + +/** 前缀匹配路由业务模式*/ +typedef enum dpp_route_mode_e +{ + DPP_ROUTE_MODE_IPV4 = 1UL, /**< @brief ipv4路由模式*/ + DPP_ROUTE_MODE_IPV6 /**< @brief ipv6路由模式*/ +} DPP_ROUTE_MODE_E; + +/** 前缀匹配路由DDR空间占用模式*/ +typedef enum dpp_route_ddr_use_mode_e +{ + DPP_ROUTE_DDR_USE_MINOR = 1, /**< @brief DDR使用量较少*/ + DPP_ROUTE_DDR_USE_MIDDLE = 2, /**< @brief DDR使用量中等*/ + DPP_ROUTE_DDR_USE_MAJOR = 3, /**< @brief DDR使用量较多*/ +} DPP_ROUTE_DDR_USE_MODE_E; + +/** 前缀匹配路由调试查找模式*/ +typedef enum dpp_route_srh_mode_e +{ + DPP_ROUTE_SRH_MODE_LP = 1, /**< @brief 前缀匹配查找模式*/ + DPP_ROUTE_SRH_MODE_EQUAL = 2, /**< @brief 精确匹配查找模式*/ +} DPP_ROUTE_SRH_MODE_E; + +/** 前缀匹配路由硬件资源 */ +typedef struct dpp_route_resource_t +{ + ZXIC_UINT32 zblk_num; /**< @brief LPM ipv4和ipv6共享的zblock数目*/ + ZXIC_UINT32 *zblk_idx; /**< @brief LPM ipv4和ipv6共享的zblock编号数组*/ + ZXIC_UINT32 ddr4_item_num; /**< @brief 分配给ipv4前缀查找的ddr存储条目数，以256bit为单位*/ + ZXIC_UINT32 ddr4_baddr; /**< @brief 分配给ipv4前缀查找的ddr存储空间的基地址，以4K*128bit为单位*/ + ZXIC_UINT32 ddr4_base_offset; /**< @brief ipv4前缀查找相对于片外ddr存储空间基地址的偏移量，以256bit为单位*/ + ZXIC_UINT32 ddr4_ecc_en; /**< @brief 固定配为1，分配给ipv4前缀查找的ddr存储空间的ECC校验使能标志*/ + ZXIC_UINT32 ddr4_bank_num; /**< @brief ipv4前缀查找的ddr存储空间bank复制份数 */ + ZXIC_UINT32 *ddr4_bank_info; /**< @brief ipv4前缀查找的ddr存储空间bank号，数组传入，支持离散分配*/ + ZXIC_UINT32 ddr4_share_type; /**< @brief ipv4前缀查找的ddr存储空间bank共享模式，参见SMMU1_DDR_SHARE_MODE_E*/ + ZXIC_UINT32 ddr6_item_num; /**< @brief 分配给ipv6前缀查找的ddr存储条目数，以256bit为单位*/ + ZXIC_UINT32 ddr6_baddr; /**< @brief 分配给ipv6前缀查找的ddr存储空间的基地址，以4K*128bit为单位*/ + ZXIC_UINT32 ddr6_base_offset; /**< @brief ipv6前缀查找相对于片外ddr存储空间基地址的偏移量，以256bit为单位*/ + ZXIC_UINT32 ddr6_ecc_en; /**< @brief 固定配为1，分配给ipv4前缀查找的ddr存储空间的ECC校验使能标志*/ + ZXIC_UINT32 ddr6_bank_num; /**< @brief ipv6前缀查找的ddr存储空间bank复制份数 */ + ZXIC_UINT32 *ddr6_bank_info; /**< @brief ipv6前缀查找的ddr存储空间bank号，数组传入，支持离散分配*/ + ZXIC_UINT32 ddr6_share_type; /**< @brief ipv6前缀查找的ddr存储空间bank共享模式，参见SMMU1_DDR_SHARE_MODE_E*/ +} DPP_ROUTE_RESOURCE_T; + +/** 前缀匹配路由级联片内eRam结果表属性 */ +typedef struct dpp_route_as_eram_t +{ + ZXIC_UINT32 baddr; /**< @brief LPM级联eRam结果基地址*/ + ZXIC_UINT32 rsp_mode; /**< @brief LPM级联eRam结果位宽模式，取值参照ERAM128_TBL_MODE_E的定义*/ +} DPP_ROUTE_AS_ERAM_T; + +/** 前缀匹配路由级联片外DDR结果表属性 */ +typedef struct dpp_route_as_ddr_t +{ + ZXIC_UINT32 baddr; /**< @brief 分配给级联ddr结果表空间的基地址，以4K*128bit为单位*/ + ZXIC_UINT32 rsp_len; /**< @brief LPM级联DDR结果位宽模式，取值参照DPP_ROUTE_AS_RSP_LEN_E的定义*/ + ZXIC_UINT32 ecc_en; /**< @brief 级联结果表DDR空间ECC校验使能标志: 0-不使能，1-使能*/ +} DPP_ROUTE_AS_DDR_T; + +typedef union dpp_route_as_rslttbl_u +{ + DPP_ROUTE_AS_ERAM_T as_eram_cfg; /**< @brief LPM级联eRam结果表空间属性*/ + DPP_ROUTE_AS_DDR_T as_ddr_cfg; /**< @brief LPM级联DDR结果表空间属性*/ +} DPP_ROUTE_AS_RSLTTBL_U; + +/** 前缀匹配IPv4键值*/ +typedef struct dpp_route_ipv4_key_t +{ + ZXIC_UINT32 vpnid; /**< @brief vpnid，16bit*/ + ZXIC_UINT32 mask_len; /**< @brief IP地址的掩码长度，最小为0(表示默认路由)，最大为32*/ + ZXIC_UINT32 ipv4_addr; /**< @brief IP地址，32bit*/ +} DPP_ROUTE_IPV4_KEY_T; + +/** 前缀匹配IPv4单个路由条目*/ +typedef struct dpp_route_entry_ipv4_t +{ + DPP_ROUTE_IPV4_KEY_T route_key; /**< @brief 键值*/ + ZXIC_UINT32 route_handle; /**< @brief 键值匹配后，继续查转发结果表的索引*/ + ZXIC_UINT8 *p_as_rslt; /**< @brief 转发结果，仅在使能lpm关联结果查找的情况下有效 */ +} DPP_ROUTE_ENTRY_IPV4_T; + +/** 前缀匹配IPv6键值*/ +typedef struct dpp_route_ipv6_key_t +{ + ZXIC_UINT32 vpnid; /**< @brief vpnid，16bit*/ + ZXIC_UINT32 mask_len; /**< @brief IP地址的掩码长度，最小为0(表示默认路由)，最大为128*/ + ZXIC_UINT32 ipaddr[4]; /**< @brief IP地址，128bit*/ +} DPP_ROUTE_IPV6_KEY_T; + +/** 前缀匹配IPv6单个路由条目*/ +typedef struct dpp_route_entry_ipv6_t +{ + DPP_ROUTE_IPV6_KEY_T route_key; /**< @brief 键值*/ + ZXIC_UINT32 route_handle; /**< @brief 键值匹配后，继续查转发结果表的索引*/ + ZXIC_UINT8 *p_as_rslt; /**< @brief 转发结果，仅在使能lpm关联结果查找的情况下有效 */ +} DPP_ROUTE_ENTRY_IPV6_T; + +/* 在HASH进行初始化的时候，需要存储的参数 */ +typedef struct dpp_hash_soft_reset_stor_dat +{ + /* 参照dpp_hash_init()的参数 */ + ZXIC_UINT32 ddr_dis_flag[4]; /**< @brief 4个HASH引擎是否DISABLE DDR标志 */ + ZXIC_UINT32 zblk_num[4]; /**< @brief 4个HASH引擎使用的zblk数量 */ + ZXIC_UINT32 *zblk_idx_start[4]; /**< @brief 4个HASH引擎使用的起始zblk index */ + + /* 参照dpp_hash_bulk_init()的参数 */ + ZXIC_UINT32 ddr_item_num[4][8]; /**< @brief 每个bulk空间存放的ddr item数 */ + ZXIC_UINT32 ddr_base_addr[4]; /**< @brief 每个hash引擎基地址 */ + ZXIC_UINT32 ddr_bank_cp[4]; /**< @brief 每个hash引擎bank copy数量 */ + ZXIC_UINT32 ddr_ecc_en[4]; /**< @brief ddr是否开启ecc使能 */ + + /* ZXIC_UINT32 ddr_width_mode[4]; */ /**< @brief ddr存储位宽 */ + /* ZXIC_UINT32 ddr_crc_sel[4]; */ /**< @brief ddr多项式选择 */ + /* ZXIC_UINT32 ddr_share_type[4]; */ /**< @brief ddr 共享类型 */ + + ZXIC_UINT32 hash_id_valid; /** HASH引擎是否已经初始化标志 */ +} DPP_HASH_SOFT_RESET_STOR_DAT; + + + +/***********************************************************/ +/** 初始化算法管理数据结构，不包含用户自定义的数据指针 +* @param p_se_cfg 算法管理数据结构指针 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author wcl @date 2015/05/20 +************************************************************/ +DPP_STATUS dpp_se_init(DPP_DEV_T *dev, DPP_SE_CFG *p_se_cfg); + +/***********************************************************/ +/** 初始化算法管理数据结构用户自定义的数据指针，当前仅用于传入设备号的值 +* @param p_se_cfg 算法管理数据结构指针 +* @param p_client 用户自定义的数据指针 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author wcl @date 2015/05/20 +************************************************************/ +DPP_STATUS dpp_se_client_init(DPP_SE_CFG *p_se_cfg, ZXIC_VOID *p_client); + +/***********************************************************/ +/** 单个hash引擎初始化 +* @param p_se_cfg 算法模块公共管理数据结构指针 +* @param fun_id hash引擎号 +* @param zblk_num 分配给此hash引擎的zblock数目 +* @param zblk_idx 分配给此hash引擎的zblock编号 +* @param ddr_dis DDR关闭位，0-不关闭片外DDR, 1-关闭片外DDR +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author wcl @date 2015/05/15 +************************************************************/ +DPP_STATUS dpp_hash_init(DPP_SE_CFG *p_se_cfg, + ZXIC_UINT32 fun_id, + ZXIC_UINT32 zblk_num, + ZXIC_UINT32 *zblk_idx, + ZXIC_UINT32 ddr_dis); + +/***********************************************************/ +/** 初始化单个hash引擎内的某个业务表，此接口支持为该业务表分配独占的zcell。 +* 必须先初始化hash引擎，再初始化业务表。 +* @param p_se_cfg 算法模块公共管理数据结构指针 +* @param fun_id hash引擎号 +* @param bulk_id 每个Hash引擎资源划分的空间ID号 +* @param p_ddr_resc_cfg 分配给hash引擎此资源空间的ddr资源属性 +* @param zcell_num 分配给hash引擎此资源空间的zcell数量 +* @param zreg_num 分配给hash引擎此资源空间的zreg数量 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author wcl @date 2015/05/15 +************************************************************/ +DPP_STATUS dpp_hash_bulk_init(DPP_SE_CFG *p_se_cfg, + ZXIC_UINT32 fun_id, + ZXIC_UINT32 bulk_id, + DPP_HASH_DDR_RESC_CFG_T *p_ddr_resc_cfg, + ZXIC_UINT32 zcell_num, + ZXIC_UINT32 zreg_num); + +/***********************************************************/ +/** 初始化单个hash引擎内的某个业务表，此接口支持为该业务表分配独占的zcell。 +* 必须先初始化hash引擎，如果是片内+片外模式还必须先初始化dpp_hash_ddr_bulk_init， +* 再初始化业务表。 +* @param p_se_cfg 算法模块公共管理数据结构指针 +* @param fun_id hash引擎号 +* @param tbl_id 业务表 +* @param tbl_flag 初始化标记, bitmap的形式使用，如:HASH_TBL_FLAG_AGE等 +* @param key_type hash条目类型，取值参照DPP_HASH_KEY_TYPE的定义 +* @param actu_key_size 业务键值有效长度: 8bit*N，N=1~48 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author wcl @date 2015/05/15 +************************************************************/ +DPP_STATUS dpp_hash_tbl_id_info_init(DPP_SE_CFG *p_se_cfg, + ZXIC_UINT32 fun_id, + ZXIC_UINT32 tbl_id, + ZXIC_UINT32 tbl_flag, + ZXIC_UINT32 key_type, + ZXIC_UINT32 actu_key_size); + +#endif + +#if ZXIC_REAL("eTcam data struct and function") +typedef DPP_STATUS (*ACL_AS_RSLT_WRT_FUNCTION)(ZXIC_UINT32 dev_id, ZXIC_UINT32 base_addr, ZXIC_UINT32 index, ZXIC_UINT32 as_mode, ZXIC_UINT8 *p_data); +#define DPP_ACL_TBL_ID_NUM (8U) +#define DPP_ACL_ETCAM_ID_NUM (1U) +#define DPP_ACL_BLOCK_NUM (8U) + +/** eTcam条目位宽模式*/ +typedef enum dpp_etcam_entry_mode_e +{ + DPP_ETCAM_KEY_640b = 0, + DPP_ETCAM_KEY_320b = 1, + DPP_ETCAM_KEY_160b = 2, + DPP_ETCAM_KEY_80b = 3, + DPP_ETCAM_KEY_INVALID, +} DPP_ETCAM_ENTRY_MODE_E; + +/** eTcam操作类型*/ +typedef enum dpp_etcam_opr_type_e +{ + DPP_ETCAM_OPR_DM = 0, /**< @brief data & mask类型*/ + DPP_ETCAM_OPR_XY = 1, /**< @brief X & Y类型*/ +} DPP_ETCAM_OPR_TYPE_E; + +/** eTcam条目格式*/ +typedef struct dpp_etcam_entry_t +{ + ZXIC_UINT32 mode; /**< @brief 条目位宽模式: 2'b00-640bit,2'b01-320bit,2'b10-160bit,2'b11-80bit*/ + ZXIC_UINT8 *p_data; /**< @brief 键值*/ + ZXIC_UINT8 *p_mask; /**< @brief 掩码*/ +} DPP_ETCAM_ENTRY_T; + +/** ACL键值位宽模式*/ +typedef enum dpp_acl_key_mode_e +{ + DPP_ACL_KEY_640b = 0, /**< @brief 640bit键值位宽*/ + DPP_ACL_KEY_320b, /**< @brief 320bit键值位宽*/ + DPP_ACL_KEY_160b, /**< @brief 160bit键值位宽*/ + DPP_ACL_KEY_80b, /**< @brief 80bit键值位宽*/ + DPP_ACL_KEY_INVALID, +} DPP_ACL_KEY_MODE_E; + +/** ACL关联查找结果表位宽模式*/ +typedef enum dpp_acl_as_mode_e +{ + DPP_ACL_AS_MODE_16b = 0, + DPP_ACL_AS_MODE_32b = 1, + DPP_ACL_AS_MODE_64b = 2, /**< @brief 64bit结果位宽*/ + DPP_ACL_AS_MODE_128b = 3, /**< @brief 128bit结果位宽*/ + DPP_ACL_AS_MODE_INVALID, +} DPP_ACL_AS_MODE_E; + +/** ACL调试查找模式*/ +typedef enum dpp_acl_srh_mode_e +{ + DPP_ACL_SRH_SOFT = 0, /**< @brief 查软件*/ + DPP_ACL_SRH_HARDWARE = 1, /**< @brief 查硬件*/ +} DPP_ACL_SRH_MODE_E; + +/** ACL条目*/ +typedef struct dpp_acl_entry_t +{ + ZXIC_UINT32 handle; /**< @brief 条目索引*/ + ZXIC_UINT8 *key_data; /**< @brief 键值data部分*/ + ZXIC_UINT8 *key_mask; /**< @brief 键值mask部分: 0为关心，1为不关心*/ + ZXIC_UINT8 *p_as_rslt; /**< @brief 关联结果，仅使能关联查找情况有效*/ +} DPP_ACL_ENTRY_T; + +typedef struct dpp_acl_block_info_t +{ + ZXIC_UINT32 is_used; + ZXIC_UINT32 tbl_id; + ZXIC_UINT32 idx_base; +} DPP_ACL_BLOCK_INFO_T; + +typedef struct dpp_acl_etcamid_cfg_t +{ + ZXIC_UINT32 is_valid; + ZXIC_UINT32 as_enable; /* eTcam自动关联eRam结果表使能: 0-不使能，1-使能 */ + ZXIC_UINT32 as_idx_offset; /* 关联结果表基地址偏移，以128bit为单位 */ + ZXIC_UINT32 as_eRam_base; /* eTcam自动关联的eRam block的基地址，以128bit为单位 */ + D_HEAD tbl_list; +} DPP_ACL_ETCAMID_CFG_T; + +typedef struct dpp_acl_key_info_t +{ + ZXIC_UINT32 handle; + ZXIC_UINT32 pri; + ZXIC_UINT8 key[0]; /* data+mask */ +} DPP_ACL_KEY_INFO_T; + +/** ACL初始化使能标志*/ +#define DPP_ACL_FLAG_ETCAM0_EN (1<<0) /**< @brief 开启eTcam端口0: 0-不开启，1-开启.*/ +#define DPP_ACL_FLAG_ETCAM0_AS (1<<2) /**< @brief 开启eTcam端口0的关联结果查找: 0-不开启，1-开启.*/ +//#define DPP_ACL_FLAG_ETCAM1_AS (1<<3) /**< @brief 开启eTcam端口1的关联结果查找: 0-不开启，1-开启.*/ + +typedef DPP_STATUS (*ACL_TBL_AS_DDR_WR_FUN)(ZXIC_UINT32 dev_id, ZXIC_UINT32 tbl_type, ZXIC_UINT32 tbl_id, ZXIC_UINT32 dir_tbl_share_type, ZXIC_UINT32 dir_tbl_base_addr, ZXIC_UINT32 ecc_en, ZXIC_UINT32 index, ZXIC_UINT32 as_mode, ZXIC_UINT8 *p_data); +typedef DPP_STATUS (*ACL_TBL_AS_DDR_RD_FUN)(ZXIC_UINT32 dev_id, ZXIC_UINT32 base_addr, ZXIC_UINT32 index, ZXIC_UINT32 as_mode, ZXIC_UINT8 *p_data); + +/** */ +typedef struct dpp_acl_tbl_cfg_t +{ + ZXIC_UINT32 tbl_type; + ZXIC_UINT32 table_id; + ZXIC_UINT8 is_as_ddr; + ZXIC_UINT8 ddr_bankcp_info; + ZXIC_UINT32 dir_tbl_share_type; + ZXIC_UINT8 ddr_ecc_en; + ZXIC_UINT32 pri_mode; + ZXIC_UINT32 key_mode; + ZXIC_UINT32 entry_num; + ZXIC_UINT32 block_num; + ZXIC_UINT32 *block_array; + ZXIC_UINT32 is_used; + ZXIC_UINT32 as_mode; + ZXIC_UINT32 as_idx_base; + ZXIC_UINT32 as_enable; /* eTcam自动关联eRam结果表使能: 0-不使能，1-使能 */ + ZXIC_UINT32 as_eRam_base; /* eTcam自动关联的eRam block的基地址，以128bit为单位 */ + ZXIC_UINT32 ddr_baddr; + ZXIC_UINT32 idx_offset; /* 相对于ddr_baddr的基地址的索引偏移，以as_mode对应的数据位宽为单位 */ + ACL_TBL_AS_DDR_WR_FUN p_as_ddr_wr_fun; + ACL_TBL_AS_DDR_RD_FUN p_as_ddr_rd_fun; + D_NODE entry_dn; + INDEX_FILL_CFG index_mng; + ZXIC_RB_CFG acl_rb; + DPP_ACL_KEY_INFO_T **acl_key_buff; + ZXIC_UINT8 *as_rslt_buff; +} DPP_ACL_TBL_CFG_T; + +/** ACL公共管理数据结构*/ +typedef struct dpp_acl_cfg_t +{ + ZXIC_VOID *p_client; + DPP_DEV_T *dev; + ZXIC_UINT32 dev_id; + ZXIC_UINT32 flags; + ACL_AS_RSLT_WRT_FUNCTION p_as_rslt_write_fun; + ACL_AS_RSLT_WRT_FUNCTION p_as_rslt_read_fun; + DPP_ACL_BLOCK_INFO_T acl_blocks[DPP_ACL_BLOCK_NUM]; + DPP_ACL_ETCAMID_CFG_T acl_etcamids; + DPP_ACL_TBL_CFG_T acl_tbls[DPP_ACL_TBL_ID_NUM]; +} DPP_ACL_CFG_T; + +/**< @brief ACL公共管理数据结构*/ +typedef struct dpp_acl_cfg_ex_t +{ + ZXIC_VOID *p_client; + DPP_DEV_T *dev; + ZXIC_UINT32 dev_id; + ZXIC_UINT32 flags; + ACL_AS_RSLT_WRT_FUNCTION p_as_rslt_write_fun; + ACL_AS_RSLT_WRT_FUNCTION p_as_rslt_read_fun; + DPP_ACL_BLOCK_INFO_T acl_blocks[DPP_ACL_BLOCK_NUM]; + DPP_ACL_ETCAMID_CFG_T acl_etcamids; + DPP_ACL_TBL_CFG_T acl_tbls[DPP_ACL_TBL_ID_NUM]; +}DPP_ACL_CFG_EX_T; + +/** acl优先级模式*/ +typedef enum dpp_acl_pri_mode_e +{ + DPP_ACL_PRI_EXPLICIT = 1, /**< @brief 显示优先级*/ + DPP_ACL_PRI_IMPLICIT, /**< @brief 隐式优先级，以条目下发顺序作为优先级*/ + DPP_ACL_PRI_SPECIFY, /**< @brief 用户指定每个条目的在tcam中的存放索引*/ + DPP_ACL_PRI_INVALID, +} DPP_ACL_PRI_MODE_E; + +/** */ +typedef struct dpp_acl_entry_ex_t +{ + ZXIC_UINT32 idx_val; /**< @brief 一次插入单个acl条目时有效，返回单个索引*/ + D_HEAD idx_list; /**< @brief 一次插入多个acl条目时有效，返回多个索引*/ + ZXIC_UINT32 pri; /* PRI_EXPLICIT: pri is priority, PRI_IMPLICIT: pri is invalid, PRI_SPECIFY: pri is handle */ + ZXIC_UINT8 *key_data; + ZXIC_UINT8 *key_mask; + ZXIC_UINT8 *p_as_rslt; +} DPP_ACL_ENTRY_EX_T; + +/***********************************************************/ +/** eTcam模块初始化 +* @param dev_id 设备号 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author wcl @date 2015/07/24 +************************************************************/ +DPP_STATUS dpp_etcam_init(ZXIC_UINT32 dev_id); + +/***********************************************************/ +/** +* @param p_acl_cfg ACL公共管理数据结构指针 +* @param p_client 用户自定义的数据指针 +* @param flags +* @param p_as_wrt_fun 关联结果写硬件表回调函数指针 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author yxh @date 2017/12/15 +************************************************************/ +DPP_STATUS dpp_acl_cfg_init_ex(DPP_DEV_T *dev, + DPP_ACL_CFG_EX_T *p_acl_cfg, + ZXIC_VOID *p_client, + ZXIC_UINT32 flags, + ACL_AS_RSLT_WRT_FUNCTION p_as_wrt_fun); + +/***********************************************************/ +/** acl业务表初始化，注意分配给一个table的多个block_idx + 必须按从小到大的顺序给定。支持多个优先级模式，暂不对外开放。 +* @param p_acl_cfg ACL公共管理数据结构指针 +* @param table_id 业务表号 +* @param as_enable 是否使能关联结果查找，0-不使能，1-使能 +* @param entry_num 最大条目数 +* @param pri_mode ACL优先级模式 +* @param key_mode ACL键值位宽模式, 取值参照DPP_ACL_KEY_MODE_E的定义 +* @param as_mode ACL关联查找结果表位宽模式 +* @param as_baddr 基地址 +* @param block_num 分配给当前业务表号的block数目 +* @param p_block_idx 分配给当前业务表号的block编号数组 +* +* @return +* @remark 无 +* @see +* @author wcl @date 2014/12/23 +************************************************************/ +DPP_STATUS dpp_acl_tbl_init_ex(DPP_ACL_CFG_EX_T *p_acl_cfg, + ZXIC_UINT32 table_id, + ZXIC_UINT32 as_enable, + ZXIC_UINT32 entry_num, + DPP_ACL_PRI_MODE_E pri_mode, + ZXIC_UINT32 key_mode, + DPP_ACL_AS_MODE_E as_mode, + ZXIC_UINT32 as_baddr, + ZXIC_UINT32 block_num, + ZXIC_UINT32 *p_block_idx); +DPP_STATUS dpp_acl_res_destroy(ZXIC_UINT32 dev_id); + +#endif + +#if ZXIC_REAL("SDT data struct and function") +/** SDT属性中的表类型 */ +typedef enum dpp_sdt_table_type_e +{ + DPP_SDT_TBLT_INVALID = 0, /**< @brief 无效类型*/ + DPP_SDT_TBLT_eRAM = 1, /**< @brief eRAM直接表类型*/ + DPP_SDT_TBLT_DDR3 = 2, /**< @brief DDR3直接表类型*/ + DPP_SDT_TBLT_HASH = 3, /**< @brief Hash表类型*/ + DPP_SDT_TBLT_LPM = 4, /**< @brief LPM表类型*/ + DPP_SDT_TBLT_eTCAM = 5, /**< @brief 片内Tcam表类型*/ + DPP_SDT_TBLT_PORTTBL = 6, /**< @brief 物理端口属性表*/ + DPP_SDT_TBLT_MAX = 7, +} DPP_SDT_TABLE_TYPE_E; + +/** 返回位宽模式*/ +typedef enum dpp_sdt_rsp_mode_e +{ + DPP_SDT_RSP_32b = 0, /** 返回32bit位宽表结果*/ + DPP_SDT_RSP_64b = 1, /** 返回64bit位宽表结果*/ + DPP_SDT_RSP_128b = 2, /** 返回128bit位宽表结果*/ + DPP_SDT_RSP_256b = 3, /** 返回256bit位宽表结果*/ +} DPP_SDT_RSP_MODE_E; + +/** eRam直接表SDT属性*/ +typedef struct dpp_sdt_tbl_eram_t +{ + ZXIC_UINT32 table_type; /** <@brief 查找表项类型 */ + ZXIC_UINT32 eram_mode; /** <@brief eRam返回位宽 */ + ZXIC_UINT32 eram_base_addr; /** <@brief eRam表项基地址，128bit为单位 */ + ZXIC_UINT32 eram_table_depth; /** <@brief 表项深度，作为越界检查使用 */ + ZXIC_UINT32 eram_clutch_en; /** <@brief 抓包使能 */ +} DPP_SDTTBL_ERAM_T; + +/** DDR3直接表SDT属性*/ +typedef struct dpp_sdt_tbl_ddr3_t +{ + ZXIC_UINT32 table_type; /** <@brief 查找表项类型 */ + ZXIC_UINT32 ddr3_base_addr; /** <@brief ddr 基地址 */ + ZXIC_UINT32 ddr3_share_type; /** <@brief ddr 共享类型 */ + ZXIC_UINT32 ddr3_rw_len; /** <@brief 表项返回/写入位宽 */ + ZXIC_UINT32 ddr3_sdt_num; /** <@brief SDT表号/复制信息ram的表号 */ + ZXIC_UINT32 ddr3_ecc_en; /** <@brief ecc使能 */ + ZXIC_UINT32 ddr3_clutch_en; /** <@brief 抓包使能 */ +} DPP_SDTTBL_DDR3_T; + +/** HASH表SDT属性*/ +typedef struct dpp_sdt_tbl_hash_t +{ + ZXIC_UINT32 table_type; /** <@brief 查找表项类型 */ + ZXIC_UINT32 hash_id; /** <@brief 访问hash的引擎 */ + ZXIC_UINT32 hash_table_width; /** <@brief hash 表项存储位宽 */ + ZXIC_UINT32 key_size; /** <@brief hash 键值长度 */ + ZXIC_UINT32 hash_table_id; /** <@brief hash 逻辑表号 */ + ZXIC_UINT32 learn_en; /** <@brief 硬件学习使能 */ + ZXIC_UINT32 keep_alive; /** <@brief 保活标志使能 */ + ZXIC_UINT32 keep_alive_baddr; /** <@brief 保活标志基地址 */ + ZXIC_UINT32 rsp_mode; /** <@brief 表项返回数据位宽 */ + ZXIC_UINT32 hash_clutch_en; /** <@brief 抓包使能 */ +} DPP_SDTTBL_HASH_T; + +/** LPM表SDT属性*/ +typedef struct dpp_sdt_tbl_lpm_t +{ + ZXIC_UINT32 table_type; /** <@brief 查找表项类型 */ + ZXIC_UINT32 lpm_v46_id; /** <@brief ipv4/ipv6标志 */ + ZXIC_UINT32 rsp_mode; /** <@brief 表项返回数据位宽 */ + ZXIC_UINT32 lpm_table_depth; /** <@brief 表项深度，越界检查 */ + ZXIC_UINT32 lpm_clutch_en; /** <@brief 抓包使能 */ +} DPP_SDTTBL_LPM_T; + +/** eTCAM表SDT属性*/ +typedef struct dpp_sdt_tbl_etcam_t +{ + ZXIC_UINT32 table_type; /** <@brief 查找表项类型 */ + ZXIC_UINT32 etcam_id; /** <@brief etcam通道 */ + ZXIC_UINT32 etcam_key_mode; /** <@brief etcam键值长度 */ + ZXIC_UINT32 etcam_table_id; /** <@brief etcam表项号 */ + ZXIC_UINT32 no_as_rsp_mode; /** <@brief handle模式返回位宽 */ + ZXIC_UINT32 as_en; /** <@brief 级联eram使能 */ + ZXIC_UINT32 as_eram_baddr; /** <@brief 级联eram基地址 */ + ZXIC_UINT32 as_rsp_mode; /** <@brief 级联返回位宽 */ + ZXIC_UINT32 etcam_table_depth; /** <@brief 表项深度，越界检查 */ + ZXIC_UINT32 etcam_clutch_en; /** <@brief 抓包使能 */ +} DPP_SDTTBL_ETCAM_T; + +/** 物理端口属性表SDT属性*/ +typedef struct dpp_sdt_tbl_porttbl_t +{ + ZXIC_UINT32 table_type; /** <@brief 查找表项类型 */ + ZXIC_UINT32 porttbl_clutch_en; /** <@brief 抓包使能 */ +} DPP_SDTTBL_PORTTBL_T; + +/***********************************************************/ +/** 初始化SDT表配置管理 +* @param dev_num 设备数目 +* @param dev_id_array 设备dev_id数组 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author wcl @date 2015/07/13 +************************************************************/ +DPP_STATUS dpp_sdt_init(ZXIC_UINT32 dev_num, ZXIC_UINT32 *dev_id_array); + +/***********************************************************/ +/** 写SDT属性表条目到硬件表，同时向8个cluster写入 +* @param dev_id 设备号 +* @param sdt_no 业务表对应的sdt号 +* @param table_type SDT属性中的表类型，取值参考DPP_SDT_TABLE_TYPE_E的定义(仅添加操作时有效) +* @param p_sdt_info 写入的SDT属性(仅添加操作时有效)。由table_type确定此ZXIC_VOID型指针对应的数据结构, 包括: \n +* DPP_SDTTBL_ERAM_T、DPP_SDTTBL_DDR3_T、DPP_SDTTBL_HASH_T、DPP_SDTTBL_LPM_T、\n +* DPP_SDTTBL_ETCAM_T、DPP_SDTTBL_XTCAM_T、DPP_SDTTBL_PORTTBL_T。 +* @param opr_type 操作类型: 0-添加条目，1-删除条目. +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author wcl @date 2015/07/11 +************************************************************/ +DPP_STATUS dpp_sdt_tbl_write(DPP_DEV_T *dev, + ZXIC_UINT32 sdt_no, + ZXIC_UINT32 table_type, + ZXIC_VOID *p_sdt_info, + ZXIC_UINT32 opr_type); + +#endif + +#endif /*dpp_se_api.h*/ diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_stat_api.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_stat_api.h new file mode 100755 index 0000000..5737757 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_stat_api.h @@ -0,0 +1,533 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_stat_api.h +* 文件标识 : stat计数模块对外数据类型定义和接口函数声明 +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : xjw +* 完成日期 : 2015/02/09 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ + +#ifndef _DPP_STAT_API_H_ +#define _DPP_STAT_API_H_ + + +#if ZXIC_REAL("header file") + +#include "dpp_dev.h" + +#endif + +#if ZXIC_REAL("data struct define") +/** STAT模块TM模式*/ +typedef enum stat_tm_mode_e +{ + STAT_TM_MODE_ETM = 0, /**< @brief 上行TM */ + STAT_TM_MODE_FTM = 1, /**< @brief 下行TM */ + STAT_TM_MODE_MAX +}STAT_TM_MODE_E; + +/** TM统计端口选择 */ +typedef enum stat_tm_port_mode_e +{ + STAT_TM_PORT_MODE_0_1 = 0, /**< @brief 端口0~1 */ + STAT_TM_PORT_MODE_2_3 = 1, /**< @brief 端口2~3 */ + STAT_TM_PORT_MODE_MAX, +}STAT_TM_PORT_MODE_E; + +/**TM统计计数模式选择 */ +typedef enum stat_tm_cnt_mode_e +{ + STAT_TM_CNT_MODE_MIX = 0, /**< @brief 混合模式 */ + STAT_TM_CNT_MODE_INNER = 1, /**< @brief 内部模式 */ + STAT_TM_CNT_MODE_MAX +}STAT_TM_CNT_MODE_E; + +/* TM计数器类型，共支持20种 */ +typedef enum tm_stat_type_e { + + TM_STAT_ENQUE_PKT = 0, /**< @brief 入队包计数*/ + TM_STAT_ENQUE_VALID_PKT = 1, /**< @brief 入队VALID包计数*/ + TM_STAT_ENQUE_DROP_PKT = 2, /**< @brief 入队丢弃包计数*/ + TM_STAT_ENQUE_TD_PKT = 3, /**< @brief 入队TD包计数*/ + TM_STAT_ENQUE_WRED_PKT = 4, /**< @brief 入队WRED包计数*/ + TM_STAT_ENQUE_DP0_PKT = 5, /**< @brief 入队DP0包计数*/ + TM_STAT_ENQUE_DP1_PKT = 6, /**< @brief 入队DP1包计数*/ + TM_STAT_ENQUE_DP2_PKT = 7, /**< @brief 入队DP2包计数*/ + TM_STAT_ENQUE_DP3_PKT = 8, /**< @brief 入队DP3包计数*/ + TM_STAT_ENQUE_DP4_PKT = 9, /**< @brief 入队DP4包计数*/ + TM_STAT_ENQUE_DP5_PKT = 10, /**< @brief 入队DP5包计数*/ + TM_STAT_ENQUE_DP6_PKT = 11, /**< @brief 入队DP6包计数*/ + TM_STAT_ENQUE_DP7_PKT = 12, /**< @brief 入队DP7包计数*/ + TM_STAT_ENQUE_BLOCK_PKT = 13, /**< @brief 入队BLOCK包计数*/ + TM_STAT_ENQUE_DISABLE_PKT = 14, /**< @brief 入队DISABLE包计数*/ + TM_STAT_DEQUE_PKT = 15, /**< @brief 出队包计数*/ + TM_STAT_DEQUE_VALID_PKT = 16, /**< @brief 出队VALID包计数*/ + TM_STAT_DEQUE_DISCARD_PKT = 17, /**< @brief 出队DISCARD包计数*/ + TM_STAT_DEQUE_CLEAR_PKT = 18, /**< @brief 出队CLEAR包计数*/ + TM_STAT_DEQUE_AGE_PKT = 19, /**< @brief 出队AGE包计数*/ + TM_STAT_TYPE_UNEN = 20, /**< @brief 不使能的时候，需配置成这个*/ + TM_STAT_TYPE_MAX +} TM_STAT_TYPE_E; + +/** car的监管类型 */ +typedef enum stat_car_type_e +{ + STAT_CAR_A_TYPE = 0, /**< @brief A级CAR*/ + STAT_CAR_B_TYPE, /**< @brief B级CAR*/ + STAT_CAR_C_TYPE, /**< @brief C级CAR*/ + STAT_CAR_MAX_TYPE +}STAT_CAR_TYPE_E; + +/** car监管队列配置*/ +typedef struct stat_car_queue_cfg_t +{ + ZXIC_UINT32 queue_id; /**< @brief 队列号*/ + ZXIC_UINT32 plcr_en; /**< @brief CAR使能*/ + ZXIC_UINT32 drop_flag; /**< @brief 丢弃标记*/ + ZXIC_VOID * profile_cfg; /**< @brief carA的包模式时，结构体类型是DPP_STAT_CAR_PKT_PROFILE_CFG_T，其余模式组合时，结构体类型DPP_STAT_CAR_PROFILE_CFG_T*/ +}STAT_CAR_QUEUE_CFG_T; + +/** stat模块计数模式设置*/ +typedef struct stat_count_cfg_t +{ + ZXIC_UINT32 rd_mode; /**< @brief 0:计数器在CPU读的下一拍自动清理,1:不自动清零*/ + ZXIC_UINT32 overflow_mode; /**< @brief 0:计数器达到最大值后，一直保持最大值,1:计数器累积到最高1bit为1，最高1bit始终为1，而其余为继续计数*/ +}STAT_COUNT_CFG_T; + +/** stat 的smmu1属性 */ +typedef struct dpp_stat_smmu1_cfg_t +{ + ZXIC_UINT32 baddr; /**< @brief 基地址*/ +}DPP_STAT_SMMU1_CFG_T; + +/** stat模块公共配置 */ +typedef struct dpp_stat_comm_cfg_t +{ + DPP_STAT_SMMU1_CFG_T stat_smmu1_cfg[DPP_DEV_CHANNEL_MAX]; /**< @brief stat 的smmu1属性*/ + ZXIC_UINT32 is_init[DPP_DEV_CHANNEL_MAX]; /**< @brief 初始化选择*/ +}DPP_STAT_COMM_CFG_T; + +/** stat模块tm统计配置 */ +typedef struct dpp_stat_tm_cfg_t +{ + ZXIC_UINT32 tm_en; /**< @brief TM统计使能 */ + ZXIC_UINT32 mov_en; /**< @brief 搬移使能*/ + ZXIC_UINT32 eram_en; /**< @brief 片内计数使能*/ + ZXIC_UINT32 ftm_pkt_en; /**< @brief ftm包计数使能*/ + ZXIC_UINT32 etm_pkt_en; /**< @brief etm包计数使能*/ + ZXIC_UINT32 ftm_port_type[4]; /**< @brief ftm包计数端口类型选择 参考 TM_STAT_TYPE_E */ + ZXIC_UINT32 etm_port_type[4]; /**< @brief etm包计数端口类型选择 参考 TM_STAT_TYPE_E */ + ZXIC_UINT32 etm_start_queue_id; /**< @brief etm起始队列号*/ + ZXIC_UINT32 etm_queue_depth_mode; /**< @brief etm队列深度*/ + DPP_STAT_SMMU1_CFG_T ftm_smmu1_cfg; /**< @brief ftm统计的smmu1属性*/ + DPP_STAT_SMMU1_CFG_T etm_smmu1_cfg; /**< @brief etm统计的smmu1属性*/ + ZXIC_UINT32 is_init[DPP_DEV_CHANNEL_MAX]; /**< @brief 初始化选择*/ +}DPP_STAT_TM_CFG_T; + +/** TM 统计计数信息 */ +typedef struct dpp_stat_tm_cnt_t +{ + ZXIC_UINT32 tm_cnt_en; /**< @brief tm计数使能*/ + ZXIC_UINT32 tm_mode; /**< @brief TM统计模式:0-ftm, 1-etm*/ + ZXIC_UINT32 tm_flow_id; /**< @brief TM统计流号*/ + ZXIC_UINT32 tm_stat_type; /**< @brief TM统计端口类型*/ + ZXIC_UINT32 is_tm_byte_en; /**< @brief TM统计字节计数使能*/ + ZXIC_UINT32 is_eram_en; /**< @brief TM统计片内计数使能*/ + ZXIC_UINT64 tm_cnt; /**< @brief TM计数结果*/ +}DPP_STAT_TM_CNT_T; + +/** STAT 中断状态 */ +typedef struct dpp_stat_brief_int_t +{ + ZXIC_UINT32 etcam_int; /**< @brief etcam模块中断 */ + ZXIC_UINT32 stat_sch_int; /**< @brief stat sch剩余部分的中断状态 */ +}DPP_STAT_BRIEF_INT_T; + +/** STAT fifo中断状态选择 */ +typedef struct dpp_stat_sch_intr_t +{ + ZXIC_UINT32 hardware_rsv; /**< @brief 系统保留，用户无需关心*/ + ZXIC_UINT32 oam0_ord_fifo_int; /**< @brief oam0保序模块中断*/ + ZXIC_UINT32 oam2_ord_fifo_int; /**< @brief oam2保序模块中断*/ + ZXIC_UINT32 oam3_ord_fifo_int; /**< @brief oam3保序模块中断*/ + ZXIC_UINT32 ddr_sch_fifo_int; /**< @brief ddr调度中断*/ + ZXIC_UINT32 plcr_sch_fifo_int; /**< @brief plcr调度中断*/ + ZXIC_UINT32 stat_schd_fifo_int; /**< @brief stat模块key调度中断*/ + ZXIC_UINT32 stat_rschd_fifo_int; /**< @brief stat模块rsp调度中断*/ +}DPP_STAT_SCH_INTR_T; + +/*stat 计数类型*/ +typedef enum stat_cnt_mode_e +{ + STAT_64_MODE = 0, /**< @brief 64bit位宽模式*/ + STAT_128_MODE = 1, /**< @brief 128bit位宽模式*/ + STAT_MAX_MODE, +}STAT_CNT_MODE_E; + +/**DPP STAT读清模式选择 */ +typedef enum stat_rd_clr_mode_e +{ + STAT_RD_CLR_MODE_UNCLR = 0, /**< @brief 不读请*/ + STAT_RD_CLR_MODE_CLR = 1, /**< @brief 读清*/ + STAT_RD_CLR_MODE_MAX, +}STAT_RD_CLR_MODE_E; + +/* car 优先级 */ +typedef enum dpp_car_priority_e +{ + DPP_CAR_PRI0 = 0, /**< @brief CAR优先级0配置*/ + DPP_CAR_PRI1 = 1, /**< @brief CAR优先级1配置*/ + DPP_CAR_PRI2 = 2, /**< @brief CAR优先级2配置*/ + DPP_CAR_PRI3 = 3, /**< @brief CAR优先级3配置*/ + DPP_CAR_PRI4 = 4, /**< @brief CAR优先级4配置*/ + DPP_CAR_PRI5 = 5, /**< @brief CAR优先级5配置*/ + DPP_CAR_PRI6 = 6, /**< @brief CAR优先级6配置*/ + DPP_CAR_PRI7 = 7, /**< @brief CAR优先级7配置*/ + DPP_CAR_PRI_MAX +}DPP_CAR_PRIORITY_E; + +/** car 监管模板参数设置的参数 */ +typedef struct dpp_stat_car_profile_cfg_t +{ + ZXIC_UINT32 profile_id; /**< @brief car模板号*/ + ZXIC_UINT32 pkt_sign; /**< @brief 包限速选择标志*/ + ZXIC_UINT32 cd; /**< @brief CD算法标志/令牌桶算法标志 0:srtcm 1:trtcm 2:MEF10.1*/ + ZXIC_UINT32 cf; /**< @brief CF溢出耦合标志，0:不溢出，1:溢出*/ + ZXIC_UINT32 cm; /**< @brief CM色盲/色敏标志，0:色盲模式，1:色敏模式 */ + ZXIC_UINT32 cir; /**< @brief C令牌桶添加速率(0~X, X Gbps/64kbps),最小值为64Kbps，步长为64Kbps*/ + ZXIC_UINT32 cbs; /**< @brief C桶桶深(XM),配置范围为0~XMByte-1，步长为1Byte*/ + ZXIC_UINT32 eir; /**< @brief E令牌桶添加速率(0~X, XGbps/64kbps),最小值为64Kbps，步长为64Kbps*/ + ZXIC_UINT32 ebs; /**< @brief E桶桶深(XM),配置范围为0~XMByte-1，步长为1Byte*/ + ZXIC_UINT32 random_disc_e; /**< @brief 仅carB、carC支持 */ + ZXIC_UINT32 random_disc_c; /**< @brief 仅carB、carC支持 */ + ZXIC_UINT32 c_pri[DPP_CAR_PRI_MAX]; /**< @brief 仅pri 1~7是有效值*/ + ZXIC_UINT32 e_green_pri[DPP_CAR_PRI_MAX]; /**< @brief 仅pri 1~7是有效值*/ + ZXIC_UINT32 e_yellow_pri[DPP_CAR_PRI_MAX]; +}DPP_STAT_CAR_PROFILE_CFG_T; + +/* car 独占smmu0的模式 */ +typedef enum dpp_car_smmu0_mono_mode_e +{ + CAR_SMMU0_MONO_MODE_NONE = 0, /**< @brief CAR不独占smmu0*/ + CAR_SMMU0_MONO_MODE_1 = 1, /**< @brief CAR独占1片smmu0*/ + CAR_SMMU0_MONO_MODE_2 = 2, /**< @brief CAR独占2片smmu0*/ + CAR_SMMU0_MONO_MODE_MAX +}DPP_CAR_SMMU0_MONO_MODE_E; + +/* TM统计的读清模式 */ +typedef enum stat_tm_clr_mode_e +{ + STAT_TM_CLR_MODE_UNCLR = 0, /**< @brief TM统计不读请*/ + STAT_TM_CLR_MODE_CLR = 1, /**< @brief TM统计读请*/ + STAT_TM_CLR_MODE_MAX, +}STAT_TM_CLR_MODE_E; + +/** car A 队列设置的参数 */ +typedef struct dpp_stat_car_a_queue_cfg_t +{ + ZXIC_UINT32 flow_id; + ZXIC_UINT32 drop_flag; + ZXIC_UINT32 plcr_en; + ZXIC_UINT32 profile_id; + ZXIC_UINT64 tq; + ZXIC_UINT32 ted; + ZXIC_UINT32 tcd; + ZXIC_UINT32 tei; + ZXIC_UINT32 tci; +}DPP_STAT_CAR_A_QUEUE_CFG_T; + +#endif + +#if ZXIC_REAL("macro function define") + +#endif + + +#if ZXIC_REAL("function declaration") +/***********************************************************/ +/** stat公共配置初始化 +* @param dev_id +* @param p_dpp_stat_comm_cfg +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/07/14 +************************************************************/ +DPP_STATUS dpp_stat_comm_init(ZXIC_UINT32 dev_id, DPP_STAT_COMM_CFG_T * p_dpp_stat_comm_cfg); + +/***********************************************************/ +/** 设置ppu统计 ERAM基地址 +* @param dev_id 设备号 +* @param ppu_eram_baddr ppu统计eRam基地址,128bit为单位 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/03/31 +************************************************************/ +DPP_STATUS dpp_stat_ppu_eram_baddr_set(DPP_DEV_T *dev, ZXIC_UINT32 ppu_eram_baddr); + +/***********************************************************/ +/** 设置ppu统计片内深度 +* @param dev_id 设备号 +* @param ppu_eram_depth ppu统计片内深度 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/03/31 +************************************************************/ +DPP_STATUS dpp_stat_ppu_eram_depth_set(DPP_DEV_T *dev, ZXIC_UINT32 ppu_eram_depth); + +/***********************************************************/ +/** 设置ppu统计 DDR基地址 +* @param dev_id 设备号 +* @param ppu_ddr_baddr ppu统计DDR基地址 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/03/31 +************************************************************/ +DPP_STATUS dpp_stat_ppu_ddr_baddr_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 ppu_ddr_baddr); + +/***********************************************************/ +/** TM配置初始化 +* @param dev_id +* @param p_stat_tm_cfg +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/08/03 +************************************************************/ +DPP_STATUS dpp_stat_tm_init(ZXIC_UINT32 dev_id, DPP_STAT_TM_CFG_T *p_stat_tm_cfg); + +/***********************************************************/ +/** 配置Etm 统计类型 +* @param dev_id 设备号 +* @param etm_port0_type 统计类型0 +* @param etm_port1_type 统计类型1 +* @param etm_port2_type 统计类型2 +* @param etm_port3_type 统计类型3 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/03/31 +************************************************************/ +DPP_STATUS dpp_stat_etm_port_type_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 etm_port0_type, + ZXIC_UINT32 etm_port1_type, + ZXIC_UINT32 etm_port2_type, + ZXIC_UINT32 etm_port3_type); + +/***********************************************************/ +/** 配置Ftm 统计类型 +* @param dev_id 设备号 +* @param ftm_port0_type 统计类型0 +* @param ftm_port1_type 统计类型1 +* @param ftm_port2_type 统计类型2 +* @param ftm_port3_type 统计类型3 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/03/31 +************************************************************/ +DPP_STATUS dpp_stat_ftm_port_type_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 ftm_port0_type, + ZXIC_UINT32 ftm_port1_type, + ZXIC_UINT32 ftm_port2_type, + ZXIC_UINT32 ftm_port3_type); + + + +/***********************************************************/ +/** car硬件初始化 +* @param dev_id 设备号 +* @param car_type car编号 +* @param car_type car模式，参见STAT_CAR_TYPE_E +* @param car_mono_mode car独占mono模式 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/04/27 +************************************************************/ +DPP_STATUS dpp_stat_car_hardware_init(ZXIC_UINT32 dev_id, + ZXIC_UINT32 car_type, + ZXIC_UINT32 car_mono_mode); + +/***********************************************************/ +/** 配置car的层级模式 +* @param dev_id +* @param mode 2 - 三级car, 第一级支持16K +* 1 - 两级car, 第一级扩展为17K +* 0 - 一级car, 第一级扩展为21K +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/09/28 +************************************************************/ +DPP_STATUS dpp_stat_car_en_mode_set(DPP_DEV_T *dev, ZXIC_UINT32 mode); + +/***********************************************************/ +/** car A 字节限速监管模板设定 +* @param dev_id 设备 car号 +* @param profile_id 监管模板号 +* @param p_cara_profile_cfg 监管模板配置 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/04/05 +************************************************************/ +DPP_STATUS dpp_stat_cara_profile_cfg_set(DPP_DEV_T *dev, + ZXIC_UINT32 profile_id, + DPP_STAT_CAR_PROFILE_CFG_T* p_cara_profile_cfg); + +/***********************************************************/ +/** 获取car A的流设置 +* @param dev_id 设备 car编号 +* @param flow_id 流号 +* @param p_cara_queue_cfg car A流配置信息 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/04/05 +************************************************************/ +DPP_STATUS dpp_stat_cara_queue_cfg_get(DPP_DEV_T *dev, + ZXIC_UINT32 flow_id, + DPP_STAT_CAR_A_QUEUE_CFG_T* p_cara_queue_cfg); + +/***********************************************************/ +/** car A的流设置 +* @param dev_id 设备 car编号 +* @param flow_id 流号 +* @param drop_flag 丢弃标志 +* @param plcr_en 监管使能 +* @param profile_id 监管模板号 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/04/05 +************************************************************/ +DPP_STATUS dpp_stat_cara_queue_cfg_set(DPP_DEV_T *dev, + ZXIC_UINT32 flow_id, + ZXIC_UINT32 drop_flag, + ZXIC_UINT32 plcr_en, + ZXIC_UINT32 profile_id); + +/***********************************************************/ +/** stat模块常用函数列表 +* @param dev_id +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author 刘硕10181552 @date 2016/02/03 +************************************************************/ +DPP_STATUS dpp_stat_help(ZXIC_UINT32 dev_id); + +/***********************************************************/ +/** stat 模块上电初始化 +* @param dev_id +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2017/07/20 +************************************************************/ +DPP_STATUS dpp_stat_module_init(ZXIC_UINT32 dev_id); + +/***********************************************************/ +/** ppu stat读统计结果配置 +* @param dev_id 设备号 +* @param rd_mode 读取位宽模式，参见STAT_CNT_MODE_E，0-64bit，1-128bit +* @param index 索引，具体位宽参见rd_mode +* @param p_data 出参，读取的数据 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author xhj @date 2018/02/01 +************************************************************/ +DPP_STATUS dpp_stat_ppu_cnt_set(ZXIC_UINT32 dev_id, + STAT_CNT_MODE_E rd_mode, + ZXIC_UINT32 index, + ZXIC_UINT32 *p_data); + +/***********************************************************/ +/** ppu计数值获取 +* @param dev_id 设备号 +* @param rd_mode 读取位宽模式，参见STAT_CNT_MODE_E，0-64bit，1-128bit +* @param index 索引，具体位宽参见rd_mode +* @param clr_mode 读清模式，参见STAT_RD_CLR_MODE_E，0-不读清，1-读清 +* @param p_data 出参，读取的数据 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/07/11 +************************************************************/ +DPP_STATUS dpp_stat_ppu_cnt_get(DPP_DEV_T *dev, + STAT_CNT_MODE_E rd_mode, + ZXIC_UINT32 index, + ZXIC_UINT32 clr_mode, + ZXIC_UINT32 *p_data); + +/***********************************************************/ +/** TM计数值获取 +* @param dev_id 设备号 +* @param tm_mode tm模式，0-ftm，1-etm 参见STAT_TM_MODE_E +* @param only_pkt_num_en 全包模式使能 +* @param port_mode 端口位置模式，参见STAT_TM_PORT_MODE_E +* @param cnt_mode 计数模式，0-片内计数，1-混合计数 +* @param clr_mode 读清模式，0-非读清，1-读清 +* @param index 索引值 +* @param p_data 数据 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/07/19 +************************************************************/ +DPP_STATUS dpp_stat_tm_cnt_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 tm_mode, + ZXIC_UINT32 only_pkt_num_en, + ZXIC_UINT32 port_mode, + ZXIC_UINT32 cnt_mode, + ZXIC_UINT32 clr_mode, + ZXIC_UINT32 index, + ZXIC_UINT32 *p_data); + +/***********************************************************/ +/** CMMU配置信息、ppu stat 统计计数配置打印 +* @param dev_id +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author 刘硕10181552 @date 2016/01/20 +************************************************************/ +DPP_STATUS diag_dpp_stat_ppu_cfg_prt(ZXIC_UINT32 dev_id); + +#endif +#endif /*dpp_stat_api.h*/ + + + diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_tm_api.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_tm_api.h new file mode 100755 index 0000000..9da623f --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_tm_api.h @@ -0,0 +1,1209 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_tm_api.h +* 文件标识 : tm模块对外数据类型定义和接口函数声明 +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : djf +* 完成日期 : 2015/02/04 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ +#ifndef _DPP_TM_API_H_ +#define _DPP_TM_API_H_ + + +#if ZXIC_REAL("header file") +#include "dpp_module.h" +#endif + +#if ZXIC_REAL("macro") +#define DPP_TM_SA_NUM (128) +#define DPP_TM_PP_NUM (64)/**< @brief TM内部逻辑端口数 */ +#define DPP_ETM_Q_NUM (9216)/**< @ETM qmu支持9K物理队列 */ +#define DPP_FTM_Q_NUM (2048)/**< @FTM qmu支持2k队列 */ +#define DPP_ETM_CRDT_NUM (0x47FF) /*etm 支持的crdt流队列逻辑编号cir+eir=18K */ +#define DPP_FTM_CRDT_NUM (0xFFF) /*ftm 支持的crdt流队列逻辑编号cir+eir=4K */ +#define DPP_ETM_MID_SE_NUM (6144)/**< @ETM中间级共享0x17FF调度单元 */ +#define DPP_FTM_MID_SE_NUM (512)/**< @FTM 中间级共享0x1FF调度单元 */ +#define DPP_ETM_MID_WFQFQ_NUM (8 * 6144)/**< @brief 中间级共享8 * 6144调度器 */ +#define DPP_FTM_MID_WFQFQ_NUM (8 * 512)/**< @brief 中间级共享8 * 512调度器 */ + + +#define DPP_ETM_WFQSP_OFFSET (0x4000) /*etm sp-wfq调度器相对于fq调度器编号偏移*/ +#define DPP_ETM_FQ_NUM (16*1024) /*etm fq调度器个数*/ +#define DPP_ETM_WFQSP_NUM (9*1024) /*etm sp8和wfq调度器个数*/ +#define DPP_ETM_FQSPWFQ_NUM (25*1024) /*etm fq-sp-wfq调度器总个数*/ +#define DPP_FTM_WFQSP_NUM (1920+64) /*ftm sp8和wfq调度器个数+64个端口*/ +#define DPP_ETM_SCH_DEL_NUM (0xABFF) /*etm-crdt要删除的流和调度器编号*/ +#define DPP_FTM_SCH_DEL_NUM (0x177F) /*ftm-crdt要删除的流和调度器编号*/ + +#define DPP_TM_INVALID_PORT (0xFFFF) /* 定义crdt无效端口号,用于判定crdt挂接状态 */ +#define DPP_FTM_DELETED_LINK_ID (0x7FF) /**定义ftm已被删除的link_id**/ +#define DPP_ETM_DELETED_LINK_ID (0x7FFF) /**定义etm已被删除的link_id**/ + + + +/* ftm/etm调度器往端口级挂接link_id偏移 */ +#define DPP_FTM_PORT_LINKID_BASE (0x780) +#define DPP_ETM_PORT_LINKID_BASE (0x7F80) +/**SHAP模块se_id编号基址(非从0开始)**/ +#define DPP_FTM_SHAP_SEID_BASE (0x1000) +#define DPP_ETM_SHAP_SEID_BASE (0x4800) + + + +/**< @brief TD */ +#define DPP_TM_Q_TD_TH_MAX (8192)/**< @brief Kbyte */ +#define DPP_TM_PP_TD_TH_MAX (8192)/**< @brief Kbyte */ +#define DPP_TM_SYS_TD_TH_MAX (8192)/**< @brief Kbyte */ + +#define DPP_TM_Q_AVG_Q_LEN_MAX (8192)/**< @brief Kbyte */ +#define DPP_TM_PP_AVG_Q_LEN_MAX (8192)/**< @brief Kbyte */ +#define DPP_TM_SYS_AVG_Q_LEN_MAX (8192)/**< @brief Kbyte */ + +/**< @brief WRED */ +#define DPP_TM_Q_WRED_NUM (32)/**< @brief 队列级WRED组数 */ +#define DPP_TM_Q_WRED_TH_MAX (8192)/**< @brief Kbyte */ +#define DPP_TM_Q_WRED_MAX_TH_MAX (8192)/**< @brief Kbyte */ +#define DPP_TM_Q_WRED_MIN_TH_MAX (8192)/**< @brief Kbyte */ +#define DPP_TM_Q_WRED_MAX_CFG_PARA (0xffffffff) + +#define DPP_TM_PP_WRED_NUM (8)/**< @brief 端口级WRED组数 */ +#define DPP_TM_PP_WRED_TH_MAX (8192)/**< @brief Kbyte */ +#define DPP_TM_PP_WRED_MAX_TH_MAX (8192)/**< @brief Kbyte */ +#define DPP_TM_PP_WRED_MIN_TH_MAX (8192)/**< @brief Kbyte */ +#define DPP_TM_PP_WRED_MAX_CFG_PARA (0xffffffff) + +/**< @brief GRED */ +#define DPP_TM_SYS_GRED_TH_MAX (8192)/**< @brief Kbyte */ +#define DPP_TM_SYS_GRED_MAX_TH_MAX (8192)/**< @brief Kbyte */ +#define DPP_TM_SYS_GRED_MIN_TH_MAX (8192)/**< @brief Kbyte */ +#define DPP_TM_SYS_GRED_MID_TH_MAX (8192)/**< @brief Kbyte */ + +#define DPP_TM_DP_NUM (8)/**< @brief DP曲线数 */ +#define DPP_TM_RED_P_MIN (1) +#define DPP_TM_RED_P_MAX (100) +#define DPP_TM_CGAVD_WEIGHT_MAX (15) +#define DPP_TM_CGAVD_MOVE_PROFILE_NUM (16) + + +#define DPP_TM_SCH_WEIGHT_INVALID (0) /**< @brief WFQ权重，FQ时weight是无效的 */ +#define DPP_TM_SCH_WEIGHT_MIN (1) +#define DPP_TM_SCH_WEIGHT_MAX (511) +#define DPP_TM_SCH_SP_NUM (8) + +#define DPP_ETM_MID_SHAPE_PROFILE_NUM (512)/**< ETM中间级整形策略数 */ +#define DPP_FTM_MID_SHAPE_PROFILE_NUM (64)/**< FTM中间级整形策略数 */ +#define DPP_ETM_FLOW_SHAPE_PROFILE_NUM (512)/**< ETM 流级整形策略数 */ +#define DPP_FTM_FLOW_SHAPE_PROFILE_NUM (128)/**< FTM 流级整形策略数 */ + +#define DPP_TM_SHAPE_CIR_MIN (0) /**< @brief kbps */ +#define DPP_TM_SHAPE_CIR_MAX (800 * 1000 * 1000) /**< @brief kbps:用户可配最大整形 */ +#define DPP_TM_SHAPE_CBS_MIN (0) /**< @brief kbyte */ +#define DPP_TM_SHAPE_CBS_MAX (128 * 1024) /**< @brief kbyte:用户可配最大桶深 128M */ + + +/**< CBS写入寄存器最大值为0x7FF */ +#define DPP_TM_SHAPE_CBS_REG_MIN (0) /**< @brief kbyte */ +#define DPP_TM_SHAPE_CBS_REG_MAX (0x7FF) /**< @brief kbyte */ + +#define DPP_TM_SYS_HZ (1000*1000*1000) /* 系统主频1000MHz */ + +#define DPP_TM_TC_NUM (8) + +#endif + + +#if ZXIC_REAL("data struct define") +/**< @brief 内置TM工作模式 */ +typedef enum dpp_tm_work_mode_e +{ + DPP_TM_WORK_MODE_TM = 0, + DPP_TM_WORK_MODE_SA, + DPP_TM_WORK_MODE_INVALID +} DPP_TM_WORK_MODE_E; + +/**< @brief QMU工作模式 */ +typedef enum dpp_tm_qmu_work_mode_e +{ + DPP_TM_QMU_WORK_MODE_2M = 0, /**< @brief 2M节点工作模式 */ + DPP_TM_QMU_WORK_MODE_4M, /**< @brief 4M节点工作模式 */ + DPP_TM_QMU_WORK_MODE_INVALID +} DPP_TM_QMU_WORK_MODE_E; + +/**< @brief QMU DDR随机模式 */ +typedef enum dpp_tm_qmu_ddr_random_mode_e +{ + DPP_TM_QMU_DDR_NOT_RANDOM = 0, /**< @brief DDR不随机模式 */ + DPP_TM_QMU_DDR_RANDOM, /**< @brief DDR随机模式 */ + DPP_TM_QMU_DDR_RANDOM_MODE_INVALID +} DPP_TM_QMU_DDR_RANDOM_MODE_E; + +/**< @brief 计数模式寄存器 */ +typedef struct dpp_tm_cnt_mode_t +{ + + ZXIC_UINT32 fc_count_mode; /**< @brief 计数流控模式 */ + ZXIC_UINT32 count_rd_mode; /**< @brief 计数读模式 */ + ZXIC_UINT32 count_overflow_mode; /**< @brief 计数溢出模式 */ +} DPP_TM_CNT_MODE_T; + +/**< @brief 中断信息 */ +typedef struct dpp_tm_int_t +{ + + ZXIC_UINT32 shap_int; + ZXIC_UINT32 crdt_int; + ZXIC_UINT32 mmu_int; + ZXIC_UINT32 qmu_int; + ZXIC_UINT32 cgavd_int; + ZXIC_UINT32 olif_int; + ZXIC_UINT32 cfgmt_int; +} DPP_TM_INT_T; + + +/**< @brief 拥塞避免层次 */ +typedef enum dpp_tm_cgavd_level_e +{ + QUEUE_LEVEL = 0, /**< @brief 流队列级 */ + PP_LEVEL, /**< @brief 端口级 */ + SYS_LEVEL, /**< @brief 系统级 */ + SA_LEVEL, /**< @brief SA队列不可达拥塞避免 */ + INVALID_LEVEL +} DPP_TM_CGAVD_LEVEL_E; + +/**< @brief dp选取值 */ +typedef enum dpp_tm_cgavd_dp_sel_e +{ + DP_SEL_DP = 0, /**< @brief 选tm头中dp字段作为cgavd的dp */ + DP_SEL_TC, /**< @brief 选tm头中tc字段作为cgavd的dp */ + DP_SEL_PKT_LEN, /**< @brief 选tm头中pkt[2:0]字段作为cgavd的dp */ + INVALID_DP +} DPP_TM_CGAVD_DP_SEL_E; + +/**< @brief 拥塞避免模式 */ +typedef enum dpp_tm_cgavd_method_e +{ + TD_METHOD = 0, /**< @brief TD模式 */ + WRED_GRED_METHOD, /**< @brief 流级和端口级为WRED模式，系统级为GRED模式 */ + INVALID_METHOD +} DPP_TM_CGAVD_METHOD_E; + +/**< @brief WRED DP曲线配置参数 */ +typedef struct dpp_tm_wred_dp_line_para_t +{ + ZXIC_UINT32 max_th; /**< @brief 平均队列深度上限阈值 */ + ZXIC_UINT32 min_th; /**< @brief 平均队列深度下限阈值 */ + ZXIC_UINT32 max_p; /**< @brief 最大丢弃概率 */ + ZXIC_UINT32 weight; /**< @brief 平均队列深度计算权重 */ + ZXIC_UINT32 q_len_th; /**< @brief 队列深度阈值 */ +} DPP_TM_WRED_DP_LINE_PARA_T; + +/**< @brief GRED DP曲线配置参数 */ +typedef struct dpp_tm_gred_dp_line_para_t +{ + ZXIC_UINT32 max_th; /**< @brief 第2段平均队列深度上限阈值 */ + ZXIC_UINT32 mid_th; /**< @brief 第1段平均队列深度上限阈值 */ + ZXIC_UINT32 min_th; /**< @brief 第1段平均队列深度下限阈值 */ + ZXIC_UINT32 max_p; /**< @brief 最大丢弃概率 */ + ZXIC_UINT32 weight; /**< @brief 平均队列深度计算权重 */ + ZXIC_UINT32 q_len_th; /**< @brief 队列深度阈值 */ +} DPP_TM_GRED_DP_LINE_PARA_T; + +/**< @brief CRDT调度层次 */ +typedef enum dpp_tm_sch_level_e +{ + DPP_TM_SCH_LEVEL_Q = 1, + DPP_TM_SCH_LEVEL_VC = 2, + DPP_TM_SCH_LEVEL_VCG = 3, + DPP_TM_SCH_LEVEL_VP = 4, + DPP_TM_SCH_LEVEL_PP = 5, + DPP_TM_SCH_LEVEL_INVALID +} DPP_TM_SCH_LEVEL_E; + +/**< @brief SP_ID */ +typedef enum dpp_tm_sch_sp_e +{ + DPP_TM_SCH_SP_0 = 0, + DPP_TM_SCH_SP_1 = 1, + DPP_TM_SCH_SP_2 = 2, + DPP_TM_SCH_SP_3 = 3, + DPP_TM_SCH_SP_4 = 4, + DPP_TM_SCH_SP_5 = 5, + DPP_TM_SCH_SP_6 = 6, + DPP_TM_SCH_SP_7 = 7, + DPP_TM_SCH_SP_8 = 8, + DPP_TM_SCH_SP_INVALID +} DPP_TM_SCH_SP_E; + +/**< @brief 调度单元挂接参数 */ +typedef struct dpp_tm_sch_para_t +{ + ZXIC_UINT32 level_id; /**< @brief 当前为中间级时，vc:0 vcg:1 vp:2 para_get已加2供调用*/ + DPP_TM_SCH_LEVEL_E se_last_level; /**< @brief 挂接到的上级层次 */ + ZXIC_UINT32 se_id; /**< @brief 挂接到的上级调度单元ID */ + DPP_TM_SCH_SP_E c_sp_id; /**< @brief C桶挂接到的SPID,SP0~SP7 */ + DPP_TM_SCH_SP_E e_sp_id; /**< @brief E桶挂接到的SPID,SP0~SP7 */ + ZXIC_UINT32 sp_relay; /**< @brief 队列优先级传递标志,FLOW级时表示FLOW_WORK_MODE */ + ZXIC_UINT32 c_sp_weight; /**< @brief C桶挂接到的调度器是WFQ的话，WFQ的权重 */ + ZXIC_UINT32 e_sp_weight; /**< @brief E桶挂接到的调度器是WFQ的话，WFQ的权重 */ +} DPP_TM_SCH_PARA_T; + +/**< @brief 调度器参数 */ +typedef struct dpp_tm_wfqfq_t +{ + ZXIC_UINT32 wfqfq_id[8]; /**< @brief 本级调度单元下挂接的8个调度器ID，FQ/WFQ，由ID号区分 */ +} DPP_TM_WFQFQ_T; + +/**< @brief 流队列挂接参数 */ +typedef struct dpp_tm_sch_flow_para_t +{ + ZXIC_UINT32 c_linkid; /**< @brief c桶要挂接到的上级调度器id */ + ZXIC_UINT32 c_weight; /**< @brief c桶挂接到上级调度器的权重[1~511] */ + ZXIC_UINT32 c_sp; /**< @brief c桶挂接到上级调度器的sp优先级,有效值[0-8],共9级，优先级依次降低 */ + ZXIC_UINT32 mode; /**< @brief 挂接模式：0-单桶 1-双桶。配置单桶时无需关注后续参数，配0即可 */ + ZXIC_UINT32 e_linkid; /**< @brief e桶要挂接到的上级调度器id */ + ZXIC_UINT32 e_weight; /**< @brief e桶挂接到上级调度器的权重[1~511] */ + ZXIC_UINT32 e_sp; /**< @brief e桶挂接到上级调度器的sp优先级，有效值[0-8],共9级，优先级依次降低 */ +} DPP_TM_SCH_FLOW_PARA_T; + +/**< @brief 调度单元挂接参数:非优先级传递 */ +typedef struct dpp_tm_sch_se_para_t +{ + ZXIC_UINT32 se_linkid; /**< @brief 要挂接到的上级调度器id */ + ZXIC_UINT32 cp_token_en; /**< @brief 调度器cp双桶使能开关，仅fq8/wfq8支持 */ + ZXIC_UINT32 se_weight; /**< @brief 挂接到上级调度器的权重[1~511] */ + ZXIC_UINT32 se_sp; /**< @brief 挂接到上级调度器的sp优先级,有效值[0-8],共9级，优先级依次降低 */ +} DPP_TM_SCH_SE_PARA_T; + +/**< @brief 调度单元挂接参数:优先级传递开启 */ +typedef struct dpp_tm_sch_se_para_insw_t +{ + ZXIC_UINT32 se_linkid; /**< @brief 要挂接到的上级调度器id */ + ZXIC_UINT32 cp_token_en; /**< @brief 调度器cp双桶使能开关，仅fq8/wfq8支持 */ + ZXIC_UINT32 se_sp; /**< @brief 挂接到上级调度器的sp优先级,有效值[0-8],共9级，优先级依次降低 */ + ZXIC_UINT32 se_weight[8]; /**< @brief WFQ8中各调度器权重值[1~511]，若是WFQ2/4 只取前面对应值，后面无效 */ +} DPP_TM_SCH_SE_PARA_INSW_T; + +typedef enum dpp_tm_sch_port_linkid_t +{ + DPP_TM_PP_LINKID_PORT0 = 0x7F80, + DPP_TM_PP_LINKID_PORT1 = 0x7F81, + DPP_TM_PP_LINKID_PORT2 = 0x7F82, + DPP_TM_PP_LINKID_PORT3 = 0x7F83, + DPP_TM_PP_LINKID_PORT4 = 0x7F84, + DPP_TM_PP_LINKID_PORT5 = 0x7F85, + DPP_TM_PP_LINKID_PORT6 = 0x7F86, + DPP_TM_PP_LINKID_PORT7 = 0x7F87, + DPP_TM_PP_LINKID_PORT8 = 0x7F88, + DPP_TM_PP_LINKID_PORT9 = 0x7F89, + DPP_TM_PP_LINKID_PORT10 = 0x7F8A, + DPP_TM_PP_LINKID_PORT11 = 0x7F8B, + DPP_TM_PP_LINKID_PORT12 = 0x7F8C, + DPP_TM_PP_LINKID_PORT13 = 0x7F8D, + DPP_TM_PP_LINKID_PORT14 = 0x7F8E, + DPP_TM_PP_LINKID_PORT15 = 0x7F8F, + DPP_TM_PP_LINKID_PORT16 = 0x7F90, + DPP_TM_PP_LINKID_PORT17 = 0x7F91, + DPP_TM_PP_LINKID_PORT18 = 0x7F92, + DPP_TM_PP_LINKID_PORT19 = 0x7F93, + DPP_TM_PP_LINKID_PORT20 = 0x7F94, + DPP_TM_PP_LINKID_PORT21 = 0x7F95, + DPP_TM_PP_LINKID_PORT22 = 0x7F96, + DPP_TM_PP_LINKID_PORT23 = 0x7F97, + DPP_TM_PP_LINKID_PORT24 = 0x7F98, + DPP_TM_PP_LINKID_PORT25 = 0x7F99, + DPP_TM_PP_LINKID_PORT26 = 0x7F9A, + DPP_TM_PP_LINKID_PORT27 = 0x7F9B, + DPP_TM_PP_LINKID_PORT28 = 0x7F9C, + DPP_TM_PP_LINKID_PORT29 = 0x7F9D, + DPP_TM_PP_LINKID_PORT30 = 0x7F9E, + DPP_TM_PP_LINKID_PORT31 = 0x7F9F, + DPP_TM_PP_LINKID_PORT32 = 0x7FA0, + DPP_TM_PP_LINKID_PORT33 = 0x7FA1, + DPP_TM_PP_LINKID_PORT34 = 0x7FA2, + DPP_TM_PP_LINKID_PORT35 = 0x7FA3, + DPP_TM_PP_LINKID_PORT36 = 0x7FA4, + DPP_TM_PP_LINKID_PORT37 = 0x7FA5, + DPP_TM_PP_LINKID_PORT38 = 0x7FA6, + DPP_TM_PP_LINKID_PORT39 = 0x7FA7, + DPP_TM_PP_LINKID_PORT40 = 0x7FA8, + DPP_TM_PP_LINKID_PORT41 = 0x7FA9, + DPP_TM_PP_LINKID_PORT42 = 0x7FAA, + DPP_TM_PP_LINKID_PORT43 = 0x7FAB, + DPP_TM_PP_LINKID_PORT44 = 0x7FAC, + DPP_TM_PP_LINKID_PORT45 = 0x7FAD, + DPP_TM_PP_LINKID_PORT46 = 0x7FAE, + DPP_TM_PP_LINKID_PORT47 = 0x7FAF, + DPP_TM_PP_LINKID_PORT48 = 0x7FB0, + DPP_TM_PP_LINKID_PORT49 = 0x7FB1, + DPP_TM_PP_LINKID_PORT50 = 0x7FB2, + DPP_TM_PP_LINKID_PORT51 = 0x7FB3, + DPP_TM_PP_LINKID_PORT52 = 0x7FB4, + DPP_TM_PP_LINKID_PORT53 = 0x7FB5, + DPP_TM_PP_LINKID_PORT54 = 0x7FB6, + DPP_TM_PP_LINKID_PORT55 = 0x7FB7, + DPP_TM_PP_LINKID_PORT56 = 0x7FB8, + DPP_TM_PP_LINKID_PORT57 = 0x7FB9, + DPP_TM_PP_LINKID_PORT58 = 0x7FBA, + DPP_TM_PP_LINKID_PORT59 = 0x7FBB, + DPP_TM_PP_LINKID_PORT60 = 0x7FBC, + DPP_TM_PP_LINKID_PORT61 = 0x7FBD, + DPP_TM_PP_LINKID_PORT62 = 0x7FBE, + DPP_TM_PP_LINKID_PORT63 = 0x7FBF, + DPP_TM_PP_LINKID_INVALID +} DPP_TM_SCH_PORT_LINKID_T; +typedef enum dpp_tm_shape_flag_e +{ + DPP_TM_SHAPE_FLAG_CIR = 0, + DPP_TM_SHAPE_FLAG_EIR = 1, + DPP_TM_SHAPE_FLAG_INVALID +} DPP_TM_SHAPE_FLAG_E; + +/**< @brief 整形令牌桶模式 */ +typedef enum dpp_tm_shape_mode_e +{ + DPP_TM_SINGLE_MIX_BUCKET = 0, /**< @brief 单桶/组合流 */ + DPP_TM_DUAL_BUCKET = 1, /**< @brief 双桶 */ + DPP_TM_DUAL_PIPE = 2, /**< @brief 被双桶 */ + DPP_TM_SHAPE_MODE_INVALID +} DPP_TM_SHAPE_MODE_E; + +/**< @brief 整形profile参数 */ +typedef struct dpp_tm_shape_profile_t +{ + ZXIC_UINT32 cir; + ZXIC_UINT32 cbs; + ZXIC_UINT32 eir; + ZXIC_UINT32 ebs; +} DPP_TM_SHAPE_PROFILE_T; + +/**< @brief 端口级整形参数 */ +typedef struct dpp_tm_shape_pp_para_t +{ + ZXIC_UINT32 cir; + ZXIC_UINT32 cbs; + ZXIC_UINT32 c_en; +} DPP_TM_SHAPE_PP_PARA_T; + +/**< @brief 调度单元整形参数 */ +typedef struct dpp_tm_shape_para_t +{ + ZXIC_UINT32 class_id; /**< @brief 当前中间级所属层次，vc:1 vcg:2 vp:3 */ + ZXIC_UINT32 profile_id; + ZXIC_UINT32 c_en; + ZXIC_UINT32 e_en; + DPP_TM_SHAPE_MODE_E mode; +} DPP_TM_SHAPE_PARA_T; + +/**< @brief 整形参数 */ +typedef struct dpp_tm_shape_t +{ + ZXIC_UINT32 mid_level; /**< @brief 当前中间级所属层次，vc:1 vcg:2 vp:3 */ + ZXIC_UINT32 cir; + ZXIC_UINT32 cbs; + ZXIC_UINT32 eir; + ZXIC_UINT32 ebs; + ZXIC_UINT32 c_en; + ZXIC_UINT32 e_en; + ZXIC_UINT32 mode; +} DPP_TM_SHAPE_T; + +typedef struct dpp_tm_shape_para +{ + ZXIC_UINT32 shape_cir; + ZXIC_UINT32 shape_cbs; + ZXIC_UINT32 shape_num; +} DPP_TM_SHAPE_PARA_TABLE; + + +/**< @brief TM初始化参数 */ +typedef struct dpp_tm_init_para_t +{ + DPP_TM_WORK_MODE_E tm_sa_mode; /**< @brief TM或SA模式 */ + DPP_TM_QMU_WORK_MODE_E qmu_mode; /**< @brief QMU 2M或4M节点模式 */ + ZXIC_UINT32 case_num; /**< @brief 四组QMU初始化场景编号为1-4;ddr*bank:1:4x2;2:4x4;3:8x2;4:4x8.*/ + DPP_TM_QMU_DDR_RANDOM_MODE_E ddr_random_mode; /**< @brief ddr随机模式 */ + ZXIC_UINT32 block_size; /**< @brief block模式，128/256/512/1024 */ + ZXIC_UINT32 local_sa_id; /**< @brief SA模式时，本地sa_id*/ +} DPP_TM_INIT_PARA_T; + + +/* TM ASIC初始化信息配置 */ +typedef struct dpp_tm_asic_init_info_t +{ + ZXIC_UINT32 blk_size; /**< @brief qmu配置的block大小 256B/512B[default]/1024B */ + ZXIC_UINT32 case_num; /**< @brief 四组QMU初始化场景编号为1-4;ddr*bank:1:4x2;2:4x4;3:8x2;4:4x8. */ + ZXIC_UINT32 imem_omem; /**< @brief 0:片内外混合; 1:纯片内;2:纯片外 */ + ZXIC_UINT32 mode; /**< @brief TM工作模式 0:TM模式; 1:SA模式 */ +} DPP_TM_ASIC_INIT_INFO_T; + +#endif + +#if ZXIC_REAL("function declaration") + + + +/***********************************************************/ +/** 读取block长度模式 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_size block长度模式，256/512/1024 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/04/09 +************************************************************/ +DPP_STATUS dpp_tm_cfgmt_blk_size_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_size); + + +/***********************************************************/ +/** 配置内置TM的工作模式 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param mode 配置的值，0-TM模式，1-SA模式 +*ETM仅工作在TM模式，FTM可以工作TM或SA模式 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/25 +************************************************************/ +DPP_STATUS dpp_tm_cfgmt_sa_work_mode_set(DPP_DEV_T *dev, DPP_TM_WORK_MODE_E mode); + + +/***********************************************************/ +/** 配置各级搬移功能使能 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param level 要配置的拥塞避免层次号，0:队列级，1:端口级，2:系统级 +* @param en 使能标记，0-不使能，1-使能 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2016/10/18 +************************************************************/ +#ifdef ETM_REAL +DPP_STATUS dpp_tm_cgavd_move_en_set(ZXIC_UINT32 dev_id, + DPP_TM_CGAVD_LEVEL_E level, + ZXIC_UINT32 en); + +/***********************************************************/ +/** 配置各级搬移门限 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param level 拥塞避免支持层次号，0:队列级，1:端口级，2:系统级 +* @param id 队列号或端口号，系统级时，id参数无效 +* @param value 端口级和系统级时，为搬移门限值，单位为NPPU存包的单位，256B； + 流级时为搬移profile_id,0~15 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2016/10/18 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_move_th_set(ZXIC_UINT32 dev_id, + DPP_TM_CGAVD_LEVEL_E level, + ZXIC_UINT32 id, + ZXIC_UINT32 value); + +/***********************************************************/ +/** 配置flow级的搬移策略 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param move_profile flow级的搬移门限分组索引,0~15 +* @param th flow级的搬移门限，单位为KB； +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2016/10/18 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_flow_move_profile_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 move_profile, + ZXIC_UINT32 th); +#endif + +/***********************************************************/ +/** 配置端口共享的搬移门限 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param th 端口共享的搬移门限，单位为NPPU存包的单位，256B； +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2016/10/18 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_port_share_th_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 th); + +/***********************************************************/ +/** 配置各级拥塞避免功能使能 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param level 要配置的拥塞避免层次号，0:队列级，1:端口级，2:系统级 +* @param en 使能标记，0-不使能，1-使能 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/28 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_en_set(DPP_DEV_T *dev, + DPP_TM_CGAVD_LEVEL_E level, + ZXIC_UINT32 en); + +/***********************************************************/ +/** 配置拥塞避免算法 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param level 拥塞避免支持层次号，0:队列级，1:端口级，2:系统级 +* @param id 队列号或端口号，系统级时，id参数无效 +* @param method 配置的拥塞避免算法，0:TD，1:WRED/GRED +* 配置TD算法时，先配TD阈值，再配置TD算法 +* 配置WRED算法时,先配置流级或端口级的平均队列深度，再配置WRED算法 +* 配置GRED算法时，先配置系统级的平均队列深度，在配置成GRED算法 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark +* @see +* @author taq @date 2015/04/14 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_method_set(DPP_DEV_T *dev, + DPP_TM_CGAVD_LEVEL_E level, + ZXIC_UINT32 id, + DPP_TM_CGAVD_METHOD_E method); + +/***********************************************************/ +/** 配置TD拥塞避免模式下的丢弃门限值 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param level 拥塞避免支持层次号，0:队列级，1:端口级，2:系统级 +* @param id 队列号或端口号，系统级时，id参数无效 +* @param td_th 配置的丢弃门限值，用户配置门限值单位为Kbyte，需要转化为Block单位写入寄存器 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/17 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_td_th_set(DPP_DEV_T *dev, + DPP_TM_CGAVD_LEVEL_E level, + ZXIC_UINT32 id, + ZXIC_UINT32 td_th); + +/***********************************************************/ +/** 配置指定端口或队列绑定的WRED GROUP ID +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param level WRED支持层次号，0:队列级，1:端口级 +* @param id 队列号或端口号 +* @param wred_id 配置的WRED GROUP ID +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/17 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_wred_id_set(ZXIC_UINT32 dev_id, + DPP_TM_CGAVD_LEVEL_E level, + ZXIC_UINT32 id, + ZXIC_UINT32 wred_id); + +/***********************************************************/ +/** 配置TM模式下流队列挂接的端口号；SA模式下流队列映射的目的芯片ID +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param q_id 队列号 +* @param pp_id 配置的端口号 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/18 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_q_map_pp_set(DPP_DEV_T *dev, + ZXIC_UINT32 q_id, + ZXIC_UINT32 pp_id); + +/***********************************************************/ +/** 配置TM模式tc到flow的映射 +* @param dev_id 设备编号 +* @param tc_id itmd tc优先级（0~7） +* @param flow_id 映射的flowid号 （0~4095） +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author sun @date 2023/07/04 +************************************************************/ +DPP_STATUS dpp_tm_tc_map_flow_set(DPP_DEV_T *dev, + ZXIC_UINT32 tc_id, + ZXIC_UINT32 flow_id); + +/***********************************************************/ +/** 配置指定端口或队列是否支持动态门限机制 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param level WRED支持层次号，0:队列级，1:端口级 +* @param id 队列号或端口号 +* @param en 配置的值，0-不支持动态门限机制，1-支持动态门限机制 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/17 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_dyn_th_en_set(DPP_DEV_T *dev, + DPP_TM_CGAVD_LEVEL_E level, + ZXIC_UINT32 id, + ZXIC_UINT32 en); + +/***********************************************************/ +/** 配置强制片内或片外 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param en 1:使能 +* @param mode 1 :omem 强制片外 0:imem 强制片内 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author wush @date 2017/10/14 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_imem_omem_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 en, + ZXIC_UINT32 mode); + + +/***********************************************************/ +/** 读取QMU队列授权价值 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_credit_value 授权价值，默认值是400Byte +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cuiy @date 2016/04/14 +************************************************************/ +DPP_STATUS dpp_tm_qmu_credit_value_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_credit_value); + +/****************************************************************************** +*包老化配置 +* @param: dev_id: 设备索引编号 +* @param tm_type 0-ETM,1-FTM +* aging_en: 包老化使能：1表示包老化功能使能；0表示包老化功能关闭。 +* aging_interval: 普通老化两次的间隔配置 +* aging_step_interval: 普通老化的老化时间的步进配置值 +* aging_start_qnum: 老化起始队列 +* aging_end_qnum: 老化结束队列 +* aging_req_aful_th: 普通老化FIFO的将满阈值 +* aging_pkt_num: 一次老化的包个数 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cuiy @date 2016/05/10 +************************************************************/ +DPP_STATUS dpp_tm_qmu_pkt_aging_set(DPP_DEV_T *dev, + ZXIC_UINT32 aging_en, + ZXIC_UINT32 aging_interval, + ZXIC_UINT32 aging_step_interval, + ZXIC_UINT32 aging_start_qnum, + ZXIC_UINT32 aging_end_qnum, + ZXIC_UINT32 aging_pkt_num, + ZXIC_UINT32 aging_req_aful_th); + +/****************************************************************************** +*配置老化一个包的时间，一次老化一个包，老化队列范围为可配 +* @param: dev_id: 设备索引编号 +* @param tm_type 0: etm; 1: ftm; +* aging_en: 包老化使能：1表示包老化功能使能；0表示包老化功能关闭。 +* aging_time: 老化一个包的时间，单位ms + aging_que_start:老化起始队列 + aging_que_start:老化终止队列 +老化时间=2*aging_interval*step_interval*q_num +aging_interval = (aging_time * 600000) / (2 * 1 * DPP_TM_Q_NUM); +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xuhb @date 2020/12/08 +************************************************************/ +DPP_STATUS dpp_tm_qmu_pkt_age_time_set(DPP_DEV_T *dev, + ZXIC_UINT32 aging_en, + ZXIC_UINT32 aging_time, + ZXIC_UINT32 aging_que_start, + ZXIC_UINT32 aging_que_end); + + +/***********************************************************/ +/** 分配etm调度器资源：fq/fq2/fq4/fq8 个数，(共16K= 16384) +* @param dev_id 设备编号 +* @param fq_num FQ调度器个数，须是8的倍数 +* @param fq2_num FQ2调度器个数，须是4的倍数 +* @param fq4_num FQ4调度器个数，须是2的倍数 +* @param fq8_num FQ8调度器个数 +* 调度器总数不能超过：16K= 16384 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/02/26 +************************************************************/ +DPP_STATUS dpp_etm_crdt_fq_set(DPP_DEV_T *dev, + ZXIC_UINT32 fq_num, + ZXIC_UINT32 fq2_num, + ZXIC_UINT32 fq4_num, + ZXIC_UINT32 fq8_num); + +/***********************************************************/ +/** 分配TM调度器资源：sp/wfq/wfq2/wfq4/wfq8 个数，（etm共9K=9216,ftm共1920个） +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param sp_num SP调度器个数，须是8的倍数 +* @param wfq_num WFQ调度器个数，须是8的倍数 +* @param wfq2_num WFQ2调度器个数，须是4的倍数 +* @param wfq4_num WFQ4调度器个数，须是2的倍数 +* @param wfq8_num WFQ8调度器个数 +* 调度器总数不能超过：ETM= 9216; FTM= 1920 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/02/26 +************************************************************/ +DPP_STATUS dpp_tm_crdt_wfqsp_set(DPP_DEV_T *dev, + ZXIC_UINT32 sp_num, + ZXIC_UINT32 wfq_num, + ZXIC_UINT32 wfq2_num, + ZXIC_UINT32 wfq4_num, + ZXIC_UINT32 wfq8_num); + +/***********************************************************/ +/** 配置flow级流队列的挂接关系(flow到上级调度器的挂接) +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param flow_id 流队列号 +* @param c_linkid c桶要挂接到的上级调度器id +* @param c_weight c桶挂接到上级调度器的权重[1~511] +* @param c_sp c桶挂接到上级调度器的sp优先级,有效值[0-8],共9级，优先级依次降低 +* @param mode 挂接模式：0-单桶 1-双桶。配置单桶时无需关注后续参数，配0即可 +* @param e_linkid e桶要挂接到的上级调度器id +* @param e_weight e桶挂接到上级调度器的权重[1~511] +* @param e_sp e桶挂接到上级调度器的sp优先级，有效值[0-8],共9级，优先级依次降低 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/02/27 +************************************************************/ +DPP_STATUS dpp_tm_crdt_flow_link_set(DPP_DEV_T *dev, + ZXIC_UINT32 flow_id, + ZXIC_UINT32 c_linkid, + ZXIC_UINT32 c_weight, + ZXIC_UINT32 c_sp, + ZXIC_UINT32 mode, + ZXIC_UINT32 e_linkid, + ZXIC_UINT32 e_weight, + ZXIC_UINT32 e_sp); + +/***********************************************************/ +/** 配置调度器层次化QOS的挂接关系:非优先级传递 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param se_id 本级调度器id +* @param se_linkid 要挂接到的上级调度器id +* @param se_weight 挂接到上级调度器的权重[1~511] +* @param se_sp 挂接到上级调度器的sp优先级,有效值[0-8],共9级，优先级依次降低 +* @param se_insw 优先级传递使能：0-关 1-开. 该参数不传递直接配0 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/02/27 +************************************************************/ +DPP_STATUS dpp_tm_crdt_se_link_set(DPP_DEV_T *dev, + ZXIC_UINT32 se_id, + ZXIC_UINT32 se_linkid, + ZXIC_UINT32 se_weight, + ZXIC_UINT32 se_sp); + +/***********************************************************/ +/** 配置调度器层次化QOS的挂接关系:优先级传递 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param se_id 本级调度器id +* @param se_linkid 要挂接到的上级调度器id +* @param se_weight WFQ2/4/8中各调度器权重值[1~511]，取相等的值 +* @param se_sp 挂接到上级调度器的sp优先级,有效值[0-7],共8级，优先级依次降低 +* @param se_insw 优先级传递使能：0-关 1-开. 该参数不传递直接配1 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/02/27 +************************************************************/ +DPP_STATUS dpp_tm_crdt_se_link_insw_set(DPP_DEV_T *dev, + ZXIC_UINT32 se_id, + ZXIC_UINT32 se_linkid, + ZXIC_UINT32 se_weight, + ZXIC_UINT32 se_sp); + +/***********************************************************/ +/** 配置调度器层次化QOS的挂接关系:优先级传递,单个调度器挂接 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param se_id 本级调度器id +* @param se_linkid 要挂接到的上级调度器id +* @param se_weight WFQ8中对应调度器权重值[1~511] +* @param se_sp 挂接到上级调度器的sp优先级,有效值[0-7],共8级，优先级依次降低 +* @param se_insw 优先级传递使能：0-关 1-开. 该参数不传递直接配1 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/02/27 +************************************************************/ +DPP_STATUS dpp_tm_crdt_se_link_insw_single_set(DPP_DEV_T *dev, + ZXIC_UINT32 se_id, + ZXIC_UINT32 se_linkid, + ZXIC_UINT32 se_weight, + ZXIC_UINT32 se_sp); + +/***********************************************************/ +/** 删除流挂接关系 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param id_s 要删除的流号或调度器起始id +* @param id_e 要删除的流号或调度器终止id +* ETM范围:0--0x47FF; FTM范围:0-0xFFF +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/02/27 +************************************************************/ +DPP_STATUS dpp_tm_crdt_del_flow_link_set(DPP_DEV_T *dev, ZXIC_UINT32 id_s, ZXIC_UINT32 id_e); + +/***********************************************************/ +/** 删除调度器挂接关系(调度器编号从0开始) +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param se_id_s 要删除的起始调度器id +* @param se_id_e 要删除的终止调度器id +* ETM范围:0--0x63FF; FTM范围:0-0x77F +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/02/27 +************************************************************/ +DPP_STATUS dpp_tm_crdt_del_se_link_set(DPP_DEV_T *dev, ZXIC_UINT32 id_s, ZXIC_UINT32 id_e); + +/***********************************************************/ +/** 配置se->pp->dev挂接关系 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param se_id 往端口挂接的调度器id +* @param pp_id [0-63] +* @param weight [1-511] +* @param sp_mapping 0~7 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/3/4 +************************************************************/ +DPP_STATUS dpp_tm_crdt_se_pp_link_set(DPP_DEV_T *dev, + ZXIC_UINT32 se_id, + ZXIC_UINT32 pp_id, + ZXIC_UINT32 weight, + ZXIC_UINT32 sp_mapping); + +/***********************************************************/ +/** +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param que_id queue id +* @param en 1:过滤E桶队列CRS状态为SLOW的入链请求；0:E桶队列CRS SLOW正常入链； +* +* @return +* @remark 无 +* @see +* @author XXX @date 2019/05/08 +************************************************************/ +DPP_STATUS dpp_tm_crdt_eir_crs_filter_en_set(DPP_DEV_T *dev, ZXIC_UINT32 que_id, ZXIC_UINT32 en); + + +/***********************************************************/ +/** 清除整形表格里面的值 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author yjd @date 2015/07/16 +************************************************************/ +DPP_STATUS dpp_tm_clr_shape_para(DPP_DEV_T *dev); + +/***********************************************************/ +/** 配置流队列双桶整形使能及模式 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param db_en 双桶整形使能 +* @param mode 0:c+e模式，1:c+p模式 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/03/11 +************************************************************/ +DPP_STATUS dpp_tm_shape_flow_db_en_set(DPP_DEV_T *dev, ZXIC_UINT32 db_en, ZXIC_UINT32 mode); + +/***********************************************************/ +/** 配置流级整形参数 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param flow_id 流队列号 ETM:0-9215,FTM:0-2047 +* @param cir cir速率，单位Kb，范围[64Kb - 160Gb] +* @param cbs cbs桶深，单位KB，范围[1KB - 64M] +* 注：cbs=0 表示关闭整形,即不限速 +* @param db_en 双桶整形使能，0-单桶，1-双桶 +* @param eir eir速率，单位Kb，范围同cir +* @param ebs ebs桶深，单位Kb，范围同cbs +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/03/11 +************************************************************/ +DPP_STATUS dpp_tm_shape_flow_para_set(DPP_DEV_T *dev, + ZXIC_UINT32 flow_id, + ZXIC_UINT32 cir, + ZXIC_UINT32 cbs, + ZXIC_UINT32 db_en, + ZXIC_UINT32 eir, + ZXIC_UINT32 ebs); + + +/***********************************************************/ +/** tm配置调度器整形参数 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param se_id 调度器编号号 ETM:0x4800-0xABFF,FTM:0x1000-0x177F +* @param pir pir总速率，单位Kb，范围同cir +* @param pbs pbs总桶深，单位Kb，范围同cbs +* @param db_en 整形模式，0-单桶，1-双桶，仅FQ8/WFQ8有效 +* @param cir [0-3]调度器cir速率，单位Kb，范围[64Kb - 160Gb] +* @param cbs [0-3]调度器cbs桶深，单位KB，范围[1KB - 64M] +* 注：cbs=0 表示关闭整形,即不限速 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/03/11 +************************************************************/ +DPP_STATUS dpp_tm_shape_se_para_set(DPP_DEV_T *dev, + ZXIC_UINT32 se_id, + ZXIC_UINT32 pir, + ZXIC_UINT32 pbs, + ZXIC_UINT32 db_en, + ZXIC_UINT32 cir, + ZXIC_UINT32 cbs); + + +/***********************************************************/ +/** 写入端口级整形信息 +* @param tm_type 0-ETM,1-FTM +* @param port_id 端口号0-63 +* @param cir +* @param cbs +* @param c_en c桶使能 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/03/03 +************************************************************/ +DPP_STATUS dpp_tm_shape_pp_para_wr(DPP_DEV_T *dev, + ZXIC_UINT32 port_id, + ZXIC_UINT32 cir, + ZXIC_UINT32 cbs, + ZXIC_UINT32 c_en); + +/***********************************************************/ +/** 配置端口级整形参数 更改整形转换公式 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param port_id 端口号 +* @param p_para 整形信息:CIR/CBS/EN +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cuiy @date 2016/04/15 +************************************************************/ +DPP_STATUS dpp_tm_shape_pp_para_set(DPP_DEV_T *dev, + ZXIC_UINT32 port_id, + const DPP_TM_SHAPE_PP_PARA_T *p_para); + +/***********************************************************/ +/** 配置轮转扫描使能和扫描速率 +* @param dev_id 设备索引编号 +* @param tm_type 0-ETM,1-FTM +* @param scan_en 轮转扫描使能。0：关闭，1：开启 +* @param scan_rate 轮转扫描速率，配置扫描周期不得少于256个周期 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/03/10 +************************************************************/ +DPP_STATUS dpp_tm_qmu_scan_rate_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 scan_en, + ZXIC_UINT32 scan_rate); + +/***********************************************************/ +/** 配置CMD_SW分端口(qmu出端口)整形速率和使能 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param shape_cir 整形值，单位Mbps，范围[0-160000] +* @param shape_cbs 桶深， 单位B，范围[0-0x1EE00] +* @param shape_en 整形使能 +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author whuashan 2020-3-17 +************************************************************/ +DPP_STATUS dpp_tm_qmu_egress_shape_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 port_id, + ZXIC_UINT32 shape_cir, + ZXIC_UINT32 shape_cbs, + ZXIC_UINT32 shape_en); + + +/***********************************************************/ +/** 配置WRED丢弃曲线对应的参数 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param level WRED支持层次号，0:队列级，1:端口级 +* @param wred_id 队列级共支持16个WRED组0-15，端口级支持8组0-7 +* @param dp 共支持8个dp，取值0-7 +* @param p_para 配置的WRED组参数值，包含以下五个参数 + max_th 平均队列深度上限阈值 + min_th 平均队列深度下限阈值 + max_p 最大丢弃概率 + weight 平均队列深度计算权重 + q_len_th 队列深度阈值 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author taq @date 2015/04/20 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_wred_dp_line_para_set(ZXIC_UINT32 dev_id, + DPP_TM_CGAVD_LEVEL_E level, + ZXIC_UINT32 wred_id, + ZXIC_UINT32 dp, + DPP_TM_WRED_DP_LINE_PARA_T *p_para); + + +/***********************************************************/ +/** 配置各级WRED丢弃曲线对应的参数 +* @param tm_type 0-ETM,1-FTM +* @param level WRED支持层次号，0:队列级，1:端口级 +* @param wred_id 队列级共支持16个WRED组0-15，端口级支持8组0-7 +* @param dp 共支持8个dp，取值0-7 +* @param max_th 平均队列深度上限阈值 +* @param min_th 平均队列深度下限阈值 +* @param max_p 最大丢弃概率 +* @param weight 平均队列深度计算权重 +* @param q_len_th 队列深度阈值 +* @param flag 忽略乘法里的当前包长和最大包长比标志位:1为忽略 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cy @date 2015/11/9 +************************************************************/ +DPP_STATUS dpp_tm_wred_dp_line_para_flag_wr(ZXIC_UINT32 dev_id, + ZXIC_UINT32 level, + ZXIC_UINT32 wred_id, + ZXIC_UINT32 dp, + ZXIC_UINT32 max_th, + ZXIC_UINT32 min_th, + ZXIC_UINT32 max_p, + ZXIC_UINT32 weight, + ZXIC_UINT32 q_len_th, + ZXIC_UINT32 flag); + +/***********************************************************/ +/** 配置CPU设置的报文长度是否参与计算丢弃概率的使能 +* @param tm_type 0-ETM,1-FTM +* @param flag 忽略乘法里的当前包长和最大包长比标志位:1为忽略 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cy @date 2015/11/9 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_wred_pke_len_calc_sign_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 flag); + + +/***********************************************************/ +/** TMMU TM纯片内模式配置 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param imem_en 1纯片内 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 说明：高有效，表示使能打开，TMMU不会再发起对MMU的读写操作，用户需要保证Cache PD全部命中。 +* @see +* @author wush @date 2017/10/14 +************************************************************/ +DPP_STATUS dpp_tm_tmmu_imem_en_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 imem_en); + +/***********************************************************/ +/** TMMU 强制DDR RDY配置 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param ddr_force_rdy 1、如果bit【0】配置为1，则QMU看到的DDR0 RDY一直为1。 + 2、bit【0】代表DDR0，bit【7】代表DDR7。 + 3、纯片内模式需要配置为8'hff，排除DDR干扰。 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark +* @see +* @author wush @date 2017/10/14 +************************************************************/ +DPP_STATUS dpp_tm_tmmu_ddr_force_rdy_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 ddr_force_rdy); + +/***********************************************************/ +/** 写一片连续的TM寄存器 +* @param module_id 区分TM子模块 +* @param first_addr 起始寄存器的地址 +* @param reg_num 总共读取的寄存器数 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author yjd @date 2015/07/26 +************************************************************/ +DPP_STATUS dpp_tm_wr_more_reg(ZXIC_UINT32 dev_id, ZXIC_UINT32 module_id, ZXIC_UINT32 first_addr, ZXIC_UINT32 first_data, ZXIC_UINT32 data_step, ZXIC_UINT32 reg_num); + +/***********************************************************/ +/** 打印tm诊断常用函数信息 +* +* @return +* @remark 无 +* @see +* @author 张明月 @date 2015/10/21 +************************************************************/ +DPP_STATUS dpp_tm_help(ZXIC_UINT32 dev_id); + +/***********TM CPU软复位接口 End*************/ + + +#endif/***function declaration***/ + +#endif/****_DPP_TM_H_****/ + + + + + diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_type_api.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_type_api.h new file mode 100755 index 0000000..5b988e8 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_type_api.h @@ -0,0 +1,415 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_error.h +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : +* 完成日期 : 2014/01/27 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ + +#ifndef _DPP_TYPE_API_H_ +#define _DPP_TYPE_API_H_ + +#ifdef __cplusplus +extern "C" { +#endif + + +//#define DPP_FOR_IDE /* IDE仿真器Driver编译控制宏，通过VC工具导入，不允许手动更改此行 */ +//#define DPP_FOR_LLT /* DPP 打桩控制宏，通过Makefile编译脚本导入，不允许手动更改此行 "make ssp4_test_64 DPPLLT=1"*/ + + +#ifndef DPP_FOR_LLT +/* write hardware enable */ +#define DPP_HW_OPR_EN (1) +#else +/* write hardware disable */ +#define DPP_HW_OPR_EN (1) +#endif + +#ifndef DPP_FOR_LLT + #ifndef DPP_FOR_RISCV + #ifndef DPP_FOR_PCIE + /* dev VPCI enalbe */ + #define DPP_DEV_VPCI_EN (1) + #else + #define DPP_DEV_VPCI_EN (0) + #endif + #else + #define DPP_DEV_VPCI_EN (0) + #endif +#else + #define DPP_DEV_VPCI_EN (0) +#endif + + +/* CPU软复位调试时开启 */ +#define DPP_CPU_SOFT_RESET (0) + +#if defined(ZXIC_OS_WIN) +#define DPP_OS_WIN32 +#elif defined(ZXIC_OS_LINUX) +#define DPP_OS_LINUX +#endif + + +#ifdef ZXIC_OS_WIN +#define SDT_FILE_PATH "..\\tools\\midware\\table_info.txt" +#else +#define SDT_FILE_PATH "table_info.txt" +#endif + + +#ifndef BOOL +#define BOOL int +#endif + +#ifndef BOOLEAN +#define BOOLEAN unsigned char +#endif + +#ifndef DPP_STATUS +#define DPP_STATUS ZXIC_UINT32 +#endif + +#ifndef DPP_OK +#define DPP_OK (0) +#endif + +#ifndef DPP_ERR +#define DPP_ERR (1) +#endif + + +#define DPP_RD_CNT_MAX (100) /* 最大读完成状态次数 */ + +#define DPP_PRT_BIT_LEN_1 (1) +#define DPP_PRT_BIT_LEN_2 (2) +#define DPP_PRT_BIT_LEN_8 (8) +#define DPP_PRT_BIT_LEN_16 (16) +#define DPP_PRT_BIT_LEN_32 (32) + + +/* agent module error code */ +#define DPP_RC_AGENT_BASE (0x100) +#define DPP_RC_AGENT_INVALID_PARAMS (DPP_RC_AGENT_BASE | 0x0) +#define DPP_RC_AGENT_INVALID_RANGES (DPP_RC_AGENT_BASE | 0x1) +#define DPP_RC_AGENT_CALL_FUN_FAIL (DPP_RC_AGENT_BASE | 0x2) +#define DPP_RC_AGENT_GET_POINTER_FAIL (DPP_RC_AGENT_BASE | 0x3) +#define DPP_RC_AGENT_SEND_MSG_FAIL (DPP_RC_AGENT_BASE | 0x4) +#define DPP_RC_AGENT_MSG_TYPE_INVALID (DPP_RC_AGENT_BASE | 0x5) + +/* common module error code */ +#define DPP_RC_COMMON_BASE (0x200) +#define DPP_RC_COMMON_INVALID_PARAMS (DPP_RC_COMMON_BASE | 0x0) +#define DPP_RC_COMMON_INVALID_RANGES (DPP_RC_COMMON_BASE | 0x1) +#define DPP_RC_COMMON_CALL_FUN_FAIL (DPP_RC_COMMON_BASE | 0x2) +#define DPP_RC_COMMON_GET_POINTER_FAIL (DPP_RC_COMMON_BASE | 0x3) +#define DPP_RC_COMMON_SEND_MSG_FAIL (DPP_RC_COMMON_BASE | 0x4) +#define DPP_RC_COMMON_MSG_TYPE_INVALID (DPP_RC_COMMON_BASE | 0x5) +#define DPP_RC_COMMON_MEMCPY_S_INVALID_PTR (DPP_RC_COMMON_BASE | 0x6) +#define DPP_RC_COMMON_MEMCPY_S_MEM_OVERLAP (DPP_RC_COMMON_BASE | 0x7) +#define DPP_RC_COMMON_CLOSE_FAIL (DPP_RC_COMMON_BASE | 0x8) + +/* config module error code */ +#define DPP_RC_CONFIG_BASE (0x300) +#define DPP_RC_CONFIG_PARA_INVALID (DPP_RC_CONFIG_BASE | 0x0) +#define DPP_RC_CONFIG_MSG_TYPE_INVALID (DPP_RC_CONFIG_BASE | 0x1) +#define DPP_RC_CONFIG_MEM_NO_INVALID (DPP_RC_CONFIG_BASE | 0x2) + +/* debug module error code */ +#define DPP_RC_DBG_BASE (0x400) +#define DPP_RC_DBG_INVALID_PARAMS (DPP_RC_DBG_BASE | 0x0) +#define DPP_RC_DBG_INVALID_RANGES (DPP_RC_DBG_BASE | 0x1) +#define DPP_RC_DBG_CALL_FUN_FAIL (DPP_RC_DBG_BASE | 0x2) +#define DPP_RC_DBG_GET_POINTER_FAIL (DPP_RC_DBG_BASE | 0x3) +#define DPP_RC_DBG_SEND_MSG_FAIL (DPP_RC_DBG_BASE | 0x4) +#define DPP_RC_DBG_MEM_NOT_ALLOC (DPP_RC_DBG_BASE | 0x5) + +/* download module error code */ +#define DPP_RC_LOAD_BASE (0x500) +#define DPP_RC_LOAD_INVALID_PARAMS (DPP_RC_LOAD_BASE | 0x0) +#define DPP_RC_LOAD_INVALID_RANGES (DPP_RC_LOAD_BASE | 0x1) +#define DPP_RC_LOAD_CALL_FUN_FAIL (DPP_RC_LOAD_BASE | 0x2) +#define DPP_RC_LOAD_GET_POINTER_FAIL (DPP_RC_LOAD_BASE | 0x3) +#define DPP_RC_LOAD_MSG_SEND_FAIL (DPP_RC_LOAD_BASE | 0x4) +#define DPP_RC_LOAD_MSG_TYPE_INVALID (DPP_RC_LOAD_BASE | 0x5) +#define DPP_RC_LOAD_DEV_NOT_EXIST (DPP_RC_LOAD_BASE | 0x6) + +/* device module error code */ +#define DPP_RC_DEV_BASE (0x600) +#define DPP_RC_DEV_PARA_INVALID (DPP_RC_DEV_BASE | 0x0) +#define DPP_RC_DEV_RANGE_INVALID (DPP_RC_DEV_BASE | 0x1) +#define DPP_RC_DEV_CALL_FUNC_FAIL (DPP_RC_DEV_BASE | 0x2) +#define DPP_RC_DEV_TYPE_INVALID (DPP_RC_DEV_BASE | 0x3) +#define DPP_RC_DEV_CONNECT_FAIL (DPP_RC_DEV_BASE | 0x4) +#define DPP_RC_DEV_MSG_INVALID (DPP_RC_DEV_BASE | 0x5) +#define DPP_RC_DEV_NOT_EXIST (DPP_RC_DEV_BASE | 0x6) +#define DPP_RC_DEV_MGR_NOT_INIT (DPP_RC_DEV_BASE | 0x7) +#define DPP_RC_DEV_CFG_NOT_INIT (DPP_RC_DEV_BASE | 0x8) + +/* env(xOS) module error code */ +#define DPP_RC_ENV_BASE (0x700) +#define DPP_RC_ENV_PARA_INVALID (DPP_RC_ENV_BASE | 0x0) +#define DPP_RC_ENV_RANGE_INVALID (DPP_RC_ENV_BASE | 0x1) +#define DPP_RC_ENV_CALL_FUNC_FAIL (DPP_RC_ENV_BASE | 0x2) +#define DPP_RC_ENV_SOCKET_FAIL (DPP_RC_ENV_BASE | 0x3) +#define DPP_RC_ENV_SOCKET_FULL (DPP_RC_ENV_BASE | 0x4) +#define DPP_RC_ENV_THREAD_FAIL (DPP_RC_ENV_BASE | 0x5) +#define DPP_RC_ENV_NOT_INIT (DPP_RC_ENV_BASE | 0x6) +#define DPP_RC_ENV_TABLE_FULL (DPP_RC_ENV_BASE | 0x7) +#define DPP_RC_ENV_MUTEX_FAIL (DPP_RC_ENV_BASE | 0x8) +#define DPP_RC_ENV_SOCKET_NOT_EXIST (DPP_RC_ENV_BASE | 0x9) + +/* table module error code */ +#define DPP_RC_TABLE_BASE (0x800) +#define DPP_RC_TABLE_PARA_INVALID (DPP_RC_TABLE_BASE | 0x0) +#define DPP_RC_TABLE_RANGE_INVALID (DPP_RC_TABLE_BASE | 0x1) +#define DPP_RC_TABLE_CALL_FUNC_FAIL (DPP_RC_TABLE_BASE | 0x2) +#define DPP_RC_TABLE_SDT_MSG_INVALID (DPP_RC_TABLE_BASE | 0x3) +#define DPP_RC_TABLE_SDT_MGR_INVALID (DPP_RC_TABLE_BASE | 0x4) +#define DPP_RC_TABLE_IF_VALUE_FAIL (DPP_RC_TABLE_BASE | 0x5) + + +/* stat module error code */ +#define DPP_RC_STAT_BASE (0x900) +#define DPP_RC_STAT_INIT_ERR (DPP_RC_STAT_BASE | 0x1) +#define DPP_RC_STAT_TM_INIT_ERR (DPP_RC_STAT_BASE | 0x2) +#define DPP_RC_STAT_TM_DIS_EN (DPP_RC_STAT_BASE | 0x3) +#define DPP_RC_STAT_TM_TYPE_ERR (DPP_RC_STAT_BASE | 0xe) /* TM 计数类型错误*/ +#define DPP_RC_STAT_TM_DEPTH_ERR (DPP_RC_STAT_BASE | 0xf) /* TM 计数深度错误*/ + +/* appl module error code */ +#define DPP_RC_APPL_BASE (0xa00) +#define DPP_RC_APPL_PARA_INVALID (DPP_RC_APPL_BASE | 0x0) +#define DPP_RC_APPL_RANGE_INVALID (DPP_RC_APPL_BASE | 0x1) +#define DPP_RC_APPL_CALL_FUNC_FAIL (DPP_RC_APPL_BASE | 0x2) + +/* reg module error code */ +#define DPP_RC_MODULE_BASE (0xb00) +#define DPP_RC_MODULE_PARA_INVALID (DPP_RC_MODULE_BASE | 0x0) +#define DPP_RC_MODULE_RANGE_INVALID (DPP_RC_MODULE_BASE | 0x1) +#define DPP_RC_MODULE_CALL_FUNC_FAIL (DPP_RC_MODULE_BASE | 0x2) +#define DPP_RC_MODULE_ENUM_TYPE_FAIL (DPP_RC_MODULE_BASE | 0x3) +#define DPP_RC_MODULE_BCDR_WR_FAIL (DPP_RC_MODULE_BASE | 0x4) + +/* reg module error code */ +#define DPP_RC_REG_BASE (0xc00) +#define DPP_RC_REG_PARA_INVALID (DPP_RC_REG_BASE | 0x0) +#define DPP_RC_REG_RANGE_INVALID (DPP_RC_REG_BASE | 0x1) +#define DPP_RC_REG_CALL_FUNC_FAIL (DPP_RC_REG_BASE | 0x2) +#define DPP_RC_REG_FIELD_OVERFLOW (DPP_RC_REG_BASE | 0x3) + +/* DTB module error code */ +#define DPP_RC_DTB_BASE (0xd00) +#define DPP_RC_DTB_MGR_EXIST (DPP_RC_DTB_BASE | 0x0) +#define DPP_RC_DTB_MGR_NOT_EXIST (DPP_RC_DTB_BASE | 0x1) +#define DPP_RC_DTB_QUEUE_RES_EMPTY (DPP_RC_DTB_BASE | 0x2) +#define DPP_RC_DTB_QUEUE_BUFF_SIZE_ERR (DPP_RC_DTB_BASE | 0x3) +#define DPP_RC_DTB_QUEUE_ITEM_HW_EMPTY (DPP_RC_DTB_BASE | 0x4) +#define DPP_RC_DTB_QUEUE_ITEM_SW_EMPTY (DPP_RC_DTB_BASE | 0x5) +#define DPP_RC_DTB_TAB_UP_BUFF_EMPTY (DPP_RC_DTB_BASE | 0x6) +#define DPP_RC_DTB_TAB_DOWN_BUFF_EMPTY (DPP_RC_DTB_BASE | 0x7) +#define DPP_RC_DTB_TAB_UP_TRANS_ERR (DPP_RC_DTB_BASE | 0x8) +#define DPP_RC_DTB_TAB_DOWN_TRANS_ERR (DPP_RC_DTB_BASE | 0x9) +#define DPP_RC_DTB_QUEUE_IS_WORKING (DPP_RC_DTB_BASE | 0xa) +#define DPP_RC_DTB_QUEUE_IS_NOT_INIT (DPP_RC_DTB_BASE | 0xb) +#define DPP_RC_DTB_MEMORY_ALLOC_ERR (DPP_RC_DTB_BASE | 0xc) +#define DPP_RC_DTB_PARA_INVALID (DPP_RC_DTB_BASE | 0xd) +#define DPP_RC_DMA_RANGE_INVALID (DPP_RC_DTB_BASE | 0xe) +#define DPP_RC_DMA_RCV_DATA_EMPTY (DPP_RC_DTB_BASE | 0xf) +#define DPP_RC_DTB_LPM_INSERT_FAIL (DPP_RC_DTB_BASE | 0x10) +#define DPP_RC_DTB_LPM_DELETE_FAIL (DPP_RC_DTB_BASE | 0x11) +#define DPP_RC_DTB_DOWN_LEN_INVALID (DPP_RC_DTB_BASE | 0x12) +#define DPP_RC_DTB_DOWN_HASH_CONFLICT (DPP_RC_DTB_BASE | 0x13) //3347 +#define DPP_RC_DTB_QUEUE_NOT_ALLOC (DPP_RC_DTB_BASE | 0x14) +#define DPP_RC_DTB_QUEUE_NAME_ERROR (DPP_RC_DTB_BASE | 0x15) +#define DPP_RC_DTB_DUMP_SIZE_SMALL (DPP_RC_DTB_BASE | 0x16) +#define DPP_RC_DTB_SEARCH_VPORT_QUEUE_ZERO (DPP_RC_DTB_BASE | 0x17) +#define DPP_RC_DTB_QUEUE_NOT_ENABLE (DPP_RC_DTB_BASE | 0x18) +#define DPP_RC_DTB_OPEN_DEBUG_MODE (DPP_RC_DTB_BASE | 0x19) +#define DPP_RC_DTB_OVER_TIME (DPP_RC_DTB_BASE | 0x1a) //3354 + +/* lif module error code */ +#define DPP_RC_LIF_BASE (0xe00) +#define DPP_RC_LIF_PARA_INVALID (DPP_RC_LIF_BASE | 0x0) +#define DPP_RC_LIF_RANGE_INVALID (DPP_RC_LIF_BASE | 0x1) +#define DPP_RC_LIF_CALL_FUNC_FAIL (DPP_RC_LIF_BASE | 0x2) +#define DPP_RC_LIF_OPER_MODE_ERR (DPP_RC_LIF_BASE | 0x3) +#define DPP_RC_SERDES_ARRAY_OVERFLOW (DPP_RC_LIF_BASE | 0x4) +#define DPP_RC_RCV_PLL_LOCK_TIMEOUT (DPP_RC_LIF_BASE | 0x5) +#define DPP_RC_LIF_TIMEOUT (DPP_RC_LIF_BASE | 0x7) +#define DPP_RC_LIF_NO_PORT (DPP_RC_LIF_BASE | 0x8) +#define DPP_RC_BCDR_PARA_ERR (DPP_RC_LIF_BASE | 0x9) +#define DPP_RC_LIF_NOT_SUPPORT (DPP_RC_LIF_BASE | 0xa) + +/* ddr module error code */ +#define DPP_RC_DDR_BASE (0x1000) +#define DPP_RC_DDR_TIME_OUT (DPP_RC_DDR_BASE | 0x0) +#define DPP_RC_DDR_TRAIN_FAIL (DPP_RC_DDR_BASE | 0x1) +#define DPP_RC_DDR_TYPE_ERR (DPP_RC_DDR_BASE | 0x2) +#define DPP_RC_DDR_LOGCHK_ERR (DPP_RC_DDR_BASE | 0x3) +#define DPP_RC_DDR_PARA_ERR (DPP_RC_DDR_BASE | 0x4) +#define DPP_RC_DDR_DAMAGED (DPP_RC_DDR_BASE | 0x5) +#define DPP_RC_DDR_DISABLE (DPP_RC_DDR_BASE | 0x6) +#define DPP_RC_DDR_ARRAY_OVERFLOW (DPP_RC_DDR_BASE | 0x7) +#define DPP_RC_DDR_INVAL_TRAIN_MODE (DPP_RC_DDR_BASE | 0x8) +#define DPP_RC_DDR_INVAL_VREF_MODE (DPP_RC_DDR_BASE | 0x9) +#define DPP_RC_DDR_INTR_ERR (DPP_RC_DDR_BASE | 0xa) +#define DPP_RC_DDR_BIST_FAIL (DPP_RC_DDR_BASE | 0xb) +#define DPP_RC_DDR_SOFTCHK_FAIL (DPP_RC_DDR_BASE | 0xb) +#define DPP_RC_DDR_PLL_LOCK_TIMEOUT (DPP_RC_DDR_BASE | 0x0) + +/* tlb module error code */ +#define DPP_RC_TLB_BASE (0x2000) +#define DPP_RC_TLB_MGR_EXIST (DPP_RC_TLB_BASE | 0x0) +#define DPP_RC_TLB_MGR_NOT_EXIST (DPP_RC_TLB_BASE | 0x1) + +/* se alg error code */ +#define DPP_SE_RC_BASE (0x50000) +#define DPP_SE_RC_ZBLK_FULL (DPP_SE_RC_CFG_BASE | 0x1) +#define DPP_SE_RC_FUN_INVALID (DPP_SE_RC_CFG_BASE | 0x2) +#define DPP_SE_RC_PARA_INVALID (DPP_SE_RC_CFG_BASE | 0x3) + +#define DPP_SE_RC_CFG_BASE (DPP_SE_RC_BASE | 0x1000) +#define DPP_SE_RC_ACL_BASE (DPP_SE_RC_BASE | 0x2000) +#define DPP_SE_RC_LPM_BASE (DPP_SE_RC_BASE | 0x3000) +#define DPP_LPM_TBL_INVALID (DPP_SE_RC_LPM_BASE | 0x01) +#define DPP_LPM_MODE_INVALID (DPP_SE_RC_LPM_BASE | 0x02) +#define DPP_LPM_FUNID_INVALID (DPP_SE_RC_LPM_BASE | 0x03) +#define DPP_LPM_RAM_FULL (DPP_SE_RC_LPM_BASE | 0x04) +#define DPP_LPM_UPDATE (DPP_SE_RC_LPM_BASE | 0x05) +#define DPP_LPM_SRHFAIL (DPP_SE_RC_LPM_BASE | 0x06) +#define DPP_LPM_KEY_INVALID (DPP_SE_RC_LPM_BASE | 0x07) +#define DPP_LPM_DEF_REG_FULL (DPP_SE_RC_LPM_BASE | 0x08) /*16组默认路由寄存器插满*/ +#define DPP_LPM_DEF_REG_NO_HIT (DPP_SE_RC_LPM_BASE | 0x09) /*16组默认路由寄存器未匹配删除条目*/ +#define DPP_LPM_DEF_REG_UPDATE (DPP_SE_RC_LPM_BASE | 0x0A) +#define DPP_LPM_DIV_GO_ON (DPP_SE_RC_LPM_BASE | 0x0B) +#define DPP_LPM_DDR_FULL (DPP_SE_RC_LPM_BASE | 0x0C) +#define DPP_LPM_DDR_PARA_INVALID (DPP_SE_RC_LPM_BASE | 0x0D) + +#define DPP_SE_RC_HASH_BASE (DPP_SE_RC_BASE | 0x4000) +#define DPP_HASH_RC_INVALID_FUNCINFO (DPP_SE_RC_HASH_BASE | 0x1) +#define DPP_HASH_RC_INVALID_ZBLCK (DPP_SE_RC_HASH_BASE | 0x2) +#define DPP_HASH_RC_INVALID_ZCELL (DPP_SE_RC_HASH_BASE | 0x3) +#define DPP_HASH_RC_INVALID_KEY (DPP_SE_RC_HASH_BASE | 0x4) +#define DPP_HASH_RC_INVALID_TBL_ID_INFO (DPP_SE_RC_HASH_BASE | 0x5) +#define DPP_HASH_RC_RB_TREE_FULL (DPP_SE_RC_HASH_BASE | 0x6) +#define DPP_HASH_RC_INVALID_KEY_TYPE (DPP_SE_RC_HASH_BASE | 0x7) +#define DPP_HASH_RC_ADD_UPDATE (DPP_SE_RC_HASH_BASE | 0x8) +#define DPP_HASH_RC_DEL_SRHFAIL (DPP_SE_RC_HASH_BASE | 0x9) +#define DPP_HASH_RC_ITEM_FULL (DPP_SE_RC_HASH_BASE | 0xa) +#define DPP_HASH_RC_INVALID_DDR_WIDTH_MODE (DPP_SE_RC_HASH_BASE | 0xb) +#define DPP_HASH_RC_INVALID_PARA (DPP_SE_RC_HASH_BASE | 0xc) +#define DPP_HASH_RC_TBL_FULL (DPP_SE_RC_HASH_BASE | 0xd) +#define DPP_HASH_RC_SRH_FAIL (DPP_SE_RC_HASH_BASE | 0xe) +#define DPP_HASH_RC_MATCH_ITEM_FAIL (DPP_SE_RC_HASH_BASE | 0xf) +#define DPP_HASH_RC_DDR_WIDTH_MODE_ERR (DPP_SE_RC_HASH_BASE | 0x10) +#define DPP_HASH_RC_INVALID_ITEM_TYPE (DPP_SE_RC_HASH_BASE | 0x11) +#define DPP_HASH_RC_REPEAT_INIT (DPP_SE_RC_HASH_BASE | 0x12) + +#define DPP_SE_RC_ETCAM_BASE (DPP_SE_RC_BASE | 0x5000) +#define DPP_ETCAM_RC_TBL_INVALID (DPP_SE_RC_ETCAM_BASE | 0x1) +#define DPP_ETCAM_RC_TBL_OVERFLOW (DPP_SE_RC_ETCAM_BASE | 0x2) + +#define DPP_ACL_RC_BASE (0x60000) +#define DPP_ACL_RC_INVALID_TBLID (DPP_ACL_RC_BASE | 0x0) +#define DPP_ACL_RC_INVALID_BLOCKNUM (DPP_ACL_RC_BASE | 0x1) +#define DPP_ACL_RC_INVALID_BLOCKID (DPP_ACL_RC_BASE | 0x2) +#define DPP_ACL_RC_TBL_NOT_INIT (DPP_ACL_RC_BASE | 0x3) +#define DPP_ACL_RC_ETCAMID_NOT_INIT (DPP_ACL_RC_BASE | 0x4) +#define DPP_ACL_RC_AS_ERAM_NOT_ENOUGH (DPP_ACL_RC_BASE | 0x5) +#define DPP_ACL_RC_RB_TREE_FULL (DPP_ACL_RC_BASE | 0x6) +#define DPP_ACL_RC_TABLE_FULL (DPP_ACL_RC_BASE | 0x7) +#define DPP_ACL_RC_INVALID_PARA (DPP_ACL_RC_BASE | 0x8) +#define DPP_ACL_RC_DEL_SRHFAIL (DPP_ACL_RC_BASE | 0x9) +#define DPP_ACL_RC_TABLE_UPDATE (DPP_ACL_RC_BASE | 0xa) +#define DPP_ACL_RC_SRH_FAIL (DPP_ACL_RC_BASE | 0xb) + +#define DPP_SE_RC_CAR_BASE (0x1100) +#define DPP_RC_CAR_TIME_OUT (DPP_SE_RC_CAR_BASE | 0x1) +#define DPP_RC_CAR_QUEUE_OUTRANGE (DPP_SE_RC_CAR_BASE | 0x2) +#define DPP_RC_CAR_RB_TREE_FULL (DPP_SE_RC_CAR_BASE | 0x3) +#define DPP_RC_CAR_RB_TREE_UPDATE (DPP_SE_RC_CAR_BASE | 0x4) +#define DPP_RC_CAR_RB_TREE_DEL_FAIL (DPP_SE_RC_CAR_BASE | 0x5) +#define DPP_RC_CAR_RB_TREE_SRH_FAIL (DPP_SE_RC_CAR_BASE | 0x6) +#define DPP_RC_CAR_RB_TREE_GET_FAIL (DPP_SE_RC_CAR_BASE | 0x7) +#define DPP_RC_CAR_INIT_FAIL (DPP_SE_RC_CAR_BASE | 0x8) +#define DPP_RC_CAR_UN_INIT (DPP_SE_RC_CAR_BASE | 0x9) +#define DPP_RC_CAR_PROFILE_UNSET (DPP_SE_RC_CAR_BASE | 0xa) +#define DPP_RC_CAR_LISTSTACK_MNG_FULL (DPP_SE_RC_CAR_BASE | 0xb) + + +/*system critical item check error code*/ +#define DPP_SYSTEM_CHECK_RC_BASE (0x70000) +#define DPP_SYSTEM_CHECK_CRM_RC_BASE (DPP_SYSTEM_CHECK_RC_BASE | 0x1000) +#define DPP_SYSTEM_CHECK_LIF0_RC_BASE (DPP_SYSTEM_CHECK_RC_BASE | 0x2000) +#define DPP_SYSTEM_CHECK_PKTRX_RC_BASE (DPP_SYSTEM_CHECK_RC_BASE | 0x3000) +#define DPP_SYSTEM_CHECK_PBU_RC_BASE (DPP_SYSTEM_CHECK_RC_BASE | 0x4000) +#define DPP_SYSTEM_CHECK_PPU_RC_BASE (DPP_SYSTEM_CHECK_RC_BASE | 0x5000) +#define DPP_SYSTEM_CHECK_ODMA_RC_BASE (DPP_SYSTEM_CHECK_RC_BASE | 0x6000) +#define DPP_SYSTEM_CHECK_CFG_RC_BASE (DPP_SYSTEM_CHECK_RC_BASE | 0x7000) +#define DPP_SYSTEM_CHECK_TM_RC_BASE (DPP_SYSTEM_CHECK_RC_BASE | 0x8000) +#define DPP_SYSTEM_CHECK_TM_READY_RC_BASE (DPP_SYSTEM_CHECK_RC_BASE | 0x100) +#define DPP_SYSTEM_CHECK_TM_SAIP_RC_BASE (DPP_SYSTEM_CHECK_RC_BASE | 0x200) +#define DPP_SYSTEM_CHECK_TM_ILIF_RC_BASE (DPP_SYSTEM_CHECK_TM_RC_BASE | 0x300) +#define DPP_SYSTEM_CHECK_TM_OLIF_RC_BASE (DPP_SYSTEM_CHECK_TM_RC_BASE | 0x400) +#define DPP_SYSTEM_CHECK_TM_TMMU_RC_BASE (DPP_SYSTEM_CHECK_TM_RC_BASE | 0x500) +#define DPP_SYSTEM_CHECK_TM_SHAPE_RC_BASE (DPP_SYSTEM_CHECK_TM_RC_BASE | 0x600) +#define DPP_SYSTEM_CHECK_TM_CRDT_RC_BASE (DPP_SYSTEM_CHECK_TM_RC_BASE | 0x700) +#define DPP_SYSTEM_CHECK_TM_CGAVD_RC_BASE (DPP_SYSTEM_CHECK_TM_RC_BASE | 0x800) +#define DPP_SYSTEM_CHECK_TM_QMU_RC_BASE (DPP_SYSTEM_CHECK_TM_RC_BASE | 0x900) + +/*system critical item check error code*/ +#define DPP_SERDES_CHECK_RC_BASE (0x80000) +#define DPP_SERDES_CHECK_PLL_BASE (DPP_SERDES_CHECK_RC_BASE | 0x1000) +#define DPP_SERDES_CHECK_PLL_A_BASE (DPP_SERDES_CHECK_PLL_BASE | 0x100) +#define DPP_SERDES_CHECK_PLL_B_BASE (DPP_SERDES_CHECK_PLL_BASE | 0x200) +#define DPP_SERDES_CHECK_PHYREADY_BASE (DPP_SERDES_CHECK_RC_BASE | 0x2000) +#define DPP_SERDES_CHECK_TX_PHYREADY_BASE (DPP_SERDES_CHECK_PHYREADY_BASE | 0x100) +#define DPP_SERDES_CHECK_RX_PHYREADY_BASE (DPP_SERDES_CHECK_PHYREADY_BASE | 0x200) +#define DPP_SERDES_CHECK_BERTOK_BASE (DPP_SERDES_CHECK_RC_BASE | 0x3000) + +/*TM RAM检测项返回错误码定义*/ +#define DPP_TM_CHECK_RC_BASE (0x100000) +#define DPP_TM_CHECK_RAM_RC_BASE (DPP_TM_CHECK_RC_BASE|0x100000) +#define DPP_RC_TM_CRDT_INS_BUSY (DPP_TM_CHECK_RC_BASE|0x100) + +/*SAIP RAM检测项返回错误码定义*/ +#define DPP_SA_CHECK_RC_BASE (0x110000) +#define DPP_SA_CHECK_RAM_RC_BASE (DPP_SA_CHECK_RC_BASE|0x110000) + +/*soft reset check error code*/ +#define DPP_SOFT_RESET_CHECK_BASE (0x1300) +#define DPP_SOFT_RESET_CHECK_WR_FAIL (DPP_SOFT_RESET_CHECK_BASE | 0x0) +#define DPP_SOFT_RESET_CHECK_RD_FAIL (DPP_SOFT_RESET_CHECK_BASE | 0x1) +#define DPP_SOFT_RESET_CHECK_WR_SIZE_ERR (DPP_SOFT_RESET_CHECK_BASE | 0x2) +#define DPP_SOFT_RESET_CHECK_RD_SIZE_ERR (DPP_SOFT_RESET_CHECK_BASE | 0x3) +#define DPP_SOFT_RESET_CHECK_BACKUP_ERR (DPP_SOFT_RESET_CHECK_BASE | 0x4) + +//add by yinxh at 2018-1-15 +//soft interrupt check error code +#define DPP_SOFT_INT_CHECK_BASE (0x1400) +#define DPP_SOFT_INT_CHECK_INVALID (DPP_SOFT_INT_CHECK_BASE | 0x0) +#define DPP_SOFT_INT_CHECK_NOT_INIT (DPP_SOFT_INT_CHECK_BASE | 0x1) +#define DPP_SOFT_INT_CHECK_SRH_FAIL (DPP_SOFT_INT_CHECK_BASE | 0x2) +#define DPP_SOFT_INT_CHECK_RB_TREE_FULL (DPP_SOFT_INT_CHECK_BASE | 0x3) + + +#ifdef __cplusplus +} +#endif + +#endif + + diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/chip/dpp_dev.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/chip/dpp_dev.h new file mode 100755 index 0000000..7dd9990 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/chip/dpp_dev.h @@ -0,0 +1,223 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_dev.h +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : 王春雷 +* 完成日期 : 2014/02/10 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: 代码规范性修改 +* 修改日期: 2014/02/10 +* 版 本 号: +* 修 改 人: 丁金凤 +* 修改内容: +***************************************************************/ + +#ifndef _DPP_DEV_H_ +#define _DPP_DEV_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include "zxic_common.h" +#include "dpp_type_api.h" + +#define DPP_KEYSIG_DEBUG (1) +#define DPP_DEV_CHANNEL_MAX (2) /* 最多支持6个芯片 */ +#define DPP_DEV_PPU_CLS_MAX (6) /* 芯片支持4级cluster */ +#define DPP_DEV_PPU_INSTR_REG_NUM (3) /* 芯片支持4级cluster 共2个指令空间*/ + +#define DPP_DEV_ME_MAX (8) /* 每级cluster支持8个me */ +#define DPP_DEV_SDT_ID_MAX (256U) +#define DPP_DTB_QUEUE_MAX (128) + +#define DPP_CHIP_DPP (0x279221) + +#define X86_ADDR_2_ARRCH64(X86_ADDR) (((X86_ADDR & (~0xFFFF)) << 4) | (X86_ADDR & 0xFFFF)) + +#define DPP_PCIE_SLOT_MAX (256) +#define DPP_PCIE_CHANNEL_MAX (128) +#define DPP_PCIE_CHANNEL_ID(VPORT) (((VPORT & 0x7000) | (VPORT & 0x0700)) >> 8) + +#define DEV_ID(DEV) (((DPP_DEV_T *)(DEV))->device_id) +#define DEV_PCIE_SLOT(DEV) (((DPP_DEV_T *)(DEV))->pcie_channel.slot) +#define DEV_PCIE_VPORT(DEV) (((DPP_DEV_T *)(DEV))->pcie_channel.vport) +#define DEV_PCIE_DEV(DEV) (((DPP_DEV_T *)(DEV))->pcie_channel.device) +#define DEV_PCIE_ADDR(DEV) (((DPP_DEV_T *)(DEV))->pcie_channel.base_addr) +#define DEV_PCIE_OFFSET_ADDR(DEV) (((DPP_DEV_T *)(DEV))->pcie_channel.offset_addr) +#define DEV_PCIE_ID(DEV) (((DPP_DEV_T *)(DEV))->pcie_channel.pcie_id) +#define DEV_PCIE_MUTEX(DEV) (((DPP_DEV_T *)(DEV))->pcie_channel.oper_mutex) + +#define DEV_PCIE_MSG_OFFSET_ADDR (0x2000) +#define DEV_PCIE_MSG_ADDR(DEV) (DEV_PCIE_ADDR(DEV) + DEV_PCIE_MSG_OFFSET_ADDR) +#define DEV_PCIE_REG_ADDR(DEV) (DEV_PCIE_ADDR(DEV) + DEV_PCIE_OFFSET_ADDR(DEV) - SYS_NP_BASE_ADDR1) + +typedef struct dpp_pf_info_t +{ + ZXIC_UINT16 slot; + ZXIC_UINT16 vport; +} DPP_PF_INFO_T; + +typedef struct dpp_pcie_channel_t +{ + ZXIC_UINT16 slot; + ZXIC_UINT16 vport; + ZXIC_UINT16 pcie_id; + ZXIC_ADDR_T base_addr; + ZXIC_ADDR_T offset_addr; + struct pci_dev* device; + ZXIC_MUTEX_T* oper_mutex; +} DPP_PCIE_CHANNEL_T; + +typedef struct dpp_dev_t +{ + ZXIC_UINT32 device_id; + DPP_PCIE_CHANNEL_T pcie_channel; +} DPP_DEV_T; + +/** 底层设备硬件读写接口指针*/ +typedef DPP_STATUS (*DPP_DEV_WRITE_FUNC)(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 size, ZXIC_UINT32 *p_data); +typedef DPP_STATUS (*DPP_DEV_READ_FUNC)(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 size, ZXIC_UINT32 *p_data); +typedef DPP_STATUS (*DPP_ACCESS_SWITCH_FUNC)(ZXIC_UINT32 dev_id, ZXIC_UINT32 access_type); + +/** 设备访问类型*/ +typedef enum dpp_dev_access_type_e +{ + DPP_DEV_ACCESS_TYPE_PCIE = 0, /**< @brief PCIe访问*/ + DPP_DEV_ACCESS_TYPE_RISCV = 1, /**< @brief RISCV访问*/ +} DPP_DEV_ACCESS_TYPE_E; + +/** 设备类型*/ +typedef enum dpp_dev_type_e +{ + DPP_DEV_TYPE_SIM = 0, /**< @brief 仿真器设备*/ + DPP_DEV_TYPE_VCS = 1, /**< @brief VCS设备*/ + DPP_DEV_TYPE_CHIP = 2, /**< @brief asci芯片设备*/ + DPP_DEV_TYPE_FPGA = 3, /**< @brief fpga设备*/ + DPP_DEV_TYPE_PCIE_ACC = 4, + DPP_DEV_TYPE_INVALID, +} DPP_DEV_TYPE_E; + +/** 设备版本*/ +typedef enum dpp_chip_version_e +{ + DPP_CHIP_VERSION_DPP = 0U, /**< @brief DPP */ + DPP_CHIP_VERSION_DPP_P = 1U, /**< @brief DPP+ */ + DPP_CHIP_VERSION_INVALID, +} DPP_CHIP_VERSION_E; + +/** 互斥锁类型*/ +typedef enum dpp_dev_mutex_type_e +{ + DPP_DEV_MUTEX_T_REG = 0, /**< @brief 寄存器操作互斥锁 */ + DPP_DEV_MUTEX_T_OAM = 1, /**< @brief OAM模块操作互斥锁 */ + DPP_DEV_MUTEX_T_ETM = 2, /**< @brief ETM模块操作互斥锁 */ + DPP_DEV_MUTEX_T_DDR = 4, /**< @brief DDR模块操作互斥锁 */ + DPP_DEV_MUTEX_T_IND = 5, /**< @brief RAM间接读写操作互斥锁 */ + DPP_DEV_MUTEX_T_ETCAM = 6, /**< @brief ETCAM间接读写操作互斥锁*/ + DPP_DEV_MUTEX_T_MMU = 7, /**< @brief MMU间接读写操作互斥锁 */ + DPP_DEV_MUTEX_T_CAR0 = 8, /**< @brief CAR0模块操作互斥锁 */ + DPP_DEV_MUTEX_T_ALG = 9, /**< @brief ALG间接读写操作互斥锁 */ + DPP_DEV_MUTEX_T_NPPU = 10, /**< @brief nppu间接读写操作互斥锁 */ + DPP_DEV_MUTEX_T_SMMU0 = 11, /**< @brief smmu0 模块操作互斥锁 */ + DPP_DEV_MUTEX_T_SMMU1 = 12, /**< @brief smmu1 模块操作互斥锁 */ + DPP_DEV_MUTEX_T_ETM_2ND = 13, /**< @brief ETM模块二层间接表操作互斥锁 */ + DPP_DEV_MUTEX_T_LPM = 14, /**< @brief LPM模块操作互斥锁 */ + DPP_DEV_MUTEX_T_CRM_TEMP = 15, /**< @brief 温度获取操作互斥锁 */ + DPP_DEV_MUTEX_T_SIM = 16, /**< @brief 仿真器socket通信操作互斥锁 */ + DPP_DEV_MUTEX_T_DTB = 17, /**< @brief DTB队列操作互斥锁 */ + DPP_DEV_MUTEX_T_MAX +} DPP_DEV_MUTEX_TYPE_E; + +typedef enum module_init_e +{ + MODULE_INIT_NPPU = 0, /**< @brief 01:pktrx 0x2:pbu 0x4:odma*/ + MODULE_INIT_PPU, + MODULE_INIT_SE, /**< @brief corresponding bits indicacte SE submodule, 0:smmu0 1:smmu1 2:alg 3:as 4:etcam 5:stat 6:reg_fifo 31:SE_init_done*/ + MODULE_INIT_ETM, /**< @brief bit31:tm bit0:olif bit1:cgavd bit2:tmmu bit3:shap bit4:crdt bit5:qmu */ + MODULE_INIT_DLB, + MODULE_INIT_TRPG, + MODULE_INIT_TSN, + MODULE_INIT_MAX +} MODULE_INIT_E; + +typedef struct dpp_dev_cfg_t +{ + ZXIC_UINT32 device_id; /* 设备号 */ + DPP_DEV_TYPE_E dev_type; /* 设备类型: 0-SIM, 1-VCS, 2-CHIP(ASIC), 3-FPGA. */ + ZXIC_UINT32 chip_ver; /* 设备类型: 0-DPP, 1-DPP+ */ + ZXIC_UINT32 access_type; /* 访问类型: 0-PCIe, 1-RISCV. */ + ZXIC_ADDR_T pcie_addr; /* PCIe映射地址 */ + ZXIC_ADDR_T riscv_addr; /* RISCV映射地址 */ + ZXIC_ADDR_T dma_vir_addr; /* DMA空间映射地址 */ + ZXIC_ADDR_T dma_phy_addr; /* 芯片地址相对偏移 */ + ZXIC_UINT32 init_flags[MODULE_INIT_MAX]; + DPP_DEV_WRITE_FUNC p_pcie_write_fun; /** PCIe硬件写回调函数 */ + DPP_DEV_READ_FUNC p_pcie_read_fun; /** PCIe硬件读回调函数 */ + DPP_DEV_WRITE_FUNC p_riscv_write_fun; /** RISCV硬件写回调函数 */ + DPP_DEV_READ_FUNC p_riscv_read_fun; /** RISCV硬件读回调函数 */ + ZXIC_MUTEX_T reg_opr_mutex; /** 寄存器操作互斥量 */ + ZXIC_MUTEX_T oam_mutex; /** OAM硬件操作互斥锁 */ + ZXIC_MUTEX_T etm_mutex; /** ETM硬件操作互斥锁 */ + ZXIC_MUTEX_T ddr_mutex; /** DDR硬件操作互斥锁 */ + ZXIC_MUTEX_T ind_mutex; /** RAM间接操作互斥锁 */ + ZXIC_MUTEX_T etcam_mutex; /** ETCAM硬件操作互斥锁 */ + ZXIC_MUTEX_T car0_mutex; /** CAR0硬件操作互斥锁 */ + ZXIC_MUTEX_T alg_mutex; /** alg硬件操作互斥锁*/ + ZXIC_MUTEX_T nppu_mutex; /** nppu硬件操作互斥锁*/ + ZXIC_MUTEX_T smmu0_mutex; /** smmu0 硬件操作互斥锁*/ + ZXIC_MUTEX_T smmu1_mutex; /** smmu1 硬件操作互斥锁*/ + ZXIC_MUTEX_T etm_2nd_mutex; /** ETM 二层间接表 硬件操作互斥锁*/ + ZXIC_MUTEX_T lpm_mutex; /** lpm配置 操作互斥锁*/ + ZXIC_MUTEX_T crm_temp_mutex; /** 温度获取 操作互斥锁*/ + ZXIC_MUTEX_T sim_mutex; /** 仿真器socket通信 操作互斥锁*/ + ZXIC_MUTEX_T dtb_mutex; /** DTB操作互斥锁*/ + ZXIC_MUTEX_T dtb_queue_mutex[DPP_DTB_QUEUE_MAX]; /* DTB模块队列操作互斥锁 */ + DPP_PCIE_CHANNEL_T pcie_channel[DPP_PCIE_SLOT_MAX][DPP_PCIE_CHANNEL_MAX]; +} DPP_DEV_CFG_T; + +typedef struct dpp_dev_mngr_t +{ + ZXIC_UINT32 device_num; /* 设备数目 */ + ZXIC_UINT32 is_init; + DPP_DEV_CFG_T *p_dev_array[DPP_DEV_CHANNEL_MAX]; +} DPP_DEV_MGR_T; + +DPP_STATUS dpp_dev_init(ZXIC_VOID); +DPP_STATUS dpp_dev_add(ZXIC_UINT32 dev_id, + DPP_DEV_TYPE_E dev_type, + DPP_DEV_ACCESS_TYPE_E access_type, + ZXIC_ADDR_T pcie_addr, + ZXIC_ADDR_T riscv_addr, + ZXIC_ADDR_T dma_vir_addr, + ZXIC_ADDR_T dma_phy_addr, + DPP_DEV_WRITE_FUNC p_pcie_write_fun, + DPP_DEV_READ_FUNC p_pcie_read_fun, + DPP_DEV_WRITE_FUNC p_riscv_write_fun, + DPP_DEV_READ_FUNC p_riscv_read_fun); +DPP_STATUS dpp_dev_del(ZXIC_UINT32 dev_id); +DPP_STATUS dpp_dev_get(ZXIC_UINT32 dev_id, DPP_PF_INFO_T* pf_info, DPP_DEV_T *dev); +DPP_STATUS dpp_dev_pcie_channel_add(ZXIC_UINT32 dev_id, DPP_PF_INFO_T* pf_info, struct pci_dev* p_dev); +DPP_STATUS dpp_dev_pcie_channel_del(ZXIC_UINT32 dev_id, DPP_PF_INFO_T* pf_info); +ZXIC_UINT32 dpp_dev_get_dev_type(ZXIC_UINT32 dev_id); +ZXIC_UINT32 dpp_dev_chip_version_get(ZXIC_UINT32 dev_id); +DPP_STATUS dpp_dev_init_flag_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 module_id, ZXIC_UINT32 flag); +DPP_STATUS dpp_dev_init_flag_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 module_id, ZXIC_UINT32 *p_flag); +DPP_STATUS dpp_dev_opr_mutex_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 type, ZXIC_MUTEX_T **p_mutex_out); +DPP_STATUS dpp_dev_dtb_opr_mutex_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 type, ZXIC_UINT32 index, ZXIC_MUTEX_T **p_mutex_out); +DPP_STATUS dpp_dev_pcie_default_write(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 size, ZXIC_UINT32 *p_data); +DPP_STATUS dpp_dev_pcie_default_read(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 size, ZXIC_UINT32 *p_data); +DPP_STATUS dpp_dev_write_channel(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 size, ZXIC_UINT32 *p_data); +DPP_STATUS dpp_dev_read_channel(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 size, ZXIC_UINT32 *p_data); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/chip/dpp_init.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/chip/dpp_init.h new file mode 100755 index 0000000..c959437 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/chip/dpp_init.h @@ -0,0 +1,66 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_init.h +* 文件标识 : +* 内容摘要 : 芯片初始化头文件 +* 其它说明 : +* 当前版本 : +* 作 者 : wcl +* 完成日期 : 2015/03/17 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ +#ifndef _DPP_INIT_H_ +#define _DPP_INIT_H_ + +/** 系统初始化标志*/ +#define DPP_INIT_FLAG_ACCESS_TYPE (1<<0) /**< @brief 访问模式: 0-PCRISCV1-MDIO*/ +#define DPP_INIT_FLAG_SERDES_DOWN_TP (1<<1) /**< @brief serdes加载方式: 0-组播，1-单播*/ +#define DPP_INIT_FLAG_DDR_BACKDOOR (1<<2) /**< @brief DDR3校准: 0-校准，1-不校准*/ +#define DPP_INIT_FLAG_SA_MODE (1<<3) /**< @brief SA工作模式: 0-内置sa，1-非SA模式*/ +#define DPP_INIT_FLAG_SA_MESH (1<<4) /**< @brief SA mesh模式: 0-非mesh，1-mesh*/ +#define DPP_INIT_FLAG_SA_SERDES_MODE (1<<5) /**< @brief SA serdes编码方式: 0-64B/66B; 1-8B/10B */ +#define DPP_INIT_FLAG_INT_DEST_MODE (1<<6) /**< @brief 中断上报方式: 0-PCIe; 1-LocalBus(管脚)*/ +#define DPP_INIT_FLAG_LIF0_MODE (1<<7) /**< @brief 0: PON模式 1: QSGMII模式*/ +#define DPP_INIT_FLAG_DMA_ENABLE (1<<8) /**< @brief DMA使能: 0-使能，1-不使能*/ +#define DPP_INIT_FLAG_TM_IMEM_FLAG (1<<9) /**< @brief TM片内外模式: 0-片外，1-片内*/ + +/** dpp sdk系统初始化控制结构*/ +typedef struct dpp_sys_init_ctrl_t +{ + DPP_DEV_TYPE_E device_type; /**< @brief 设备类型，取值参考DPP_DEV_TYPE_E的定义*/ + ZXIC_UINT32 flags; /**< @brief 初始化标志，按bitmap使用，*/ + ZXIC_UINT32 sa_id; /**< @brief 内置sa模式下，sa的ID，范围0~127*/ + ZXIC_UINT32 case_num; /**< @brief TM四组QMU初始化场景编号为1-8;ddr*bank:1:4x2;2:4x4;3:8x2;4:4x8.*/ + ZXIC_UINT32 lif0_port_type; /**< @brief LIF0是PON口模式下，lif0的PON端口类型，详见DPP_LIF0_PON_TYPE_E */ + ZXIC_UINT32 lif1_port_type; /**< @brief 非内置SA模式下，lif1的端口类型，详见DPP_LIF1_PORT_MODE_E */ + ZXIC_ADDR_T pcie_vir_baddr; /**< @brief PCIe映射虚拟基地址*/ + ZXIC_ADDR_T riscv_vir_baddr; /**< @brief RISCV映射虚拟基地址 */ + ZXIC_ADDR_T dma_vir_baddr; /**< @brief DMA映射虚拟地址*/ + ZXIC_ADDR_T dma_phy_baddr; /**< @brief DMA内存物理地址*/ + DPP_DEV_WRITE_FUNC pcie_write_fun; /**< @brief PCIe硬件写回调函数 */ + DPP_DEV_READ_FUNC pcie_read_fun; /**< @brief PCIe硬件读回调函数*/ + DPP_DEV_WRITE_FUNC riscv_write_fun; /**< @brief RISCV硬件写回调函数 */ + DPP_DEV_READ_FUNC riscv_read_fun; /**< @brief RISCV硬件读回调函数*/ + DPP_ACCESS_SWITCH_FUNC access_switch_fun; /**< @brief PCIe/RISCV切换回调函数*/ +} DPP_SYS_INIT_CTRL_T; + +/***********************************************************/ +/** 芯片上电初始，完整版本 +* @param dev_id 设备号 +* @param p_init_ctrl 系统初始化控制数据结构，由用户完成实例化和成员赋值 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author wcl @date 2015/03/26 +************************************************************/ +DPP_STATUS dpp_init(ZXIC_UINT32 dev_id, DPP_SYS_INIT_CTRL_T *p_init_ctrl); + +#endif /* dpp_init.h */ diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/init/dpp_kernel_init.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/init/dpp_kernel_init.h new file mode 100644 index 0000000..c989094 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/init/dpp_kernel_init.h @@ -0,0 +1,19 @@ +#ifndef _DPP_KERNEL_INIT_H_ +#define _DPP_KERNEL_INIT_H_ + +#include "zxic_common.h" +#include "dpp_dtb_table_api.h" + +ZXIC_SINT32 dpp_dtb_queue_dma_mem_alloc(DPP_DEV_T *dev, ZXIC_UINT32 queue_id, ZXIC_UINT32 size); +ZXIC_SINT32 dpp_dtb_queue_dma_mem_get(DPP_DEV_T *dev, ZXIC_UINT32 queue_id, DTB_QUEUE_DMA_ADDR_INFO *dmaAddrInfo); +ZXIC_SINT32 dpp_dtb_queue_dma_mem_release(DPP_DEV_T *dev, ZXIC_UINT32 queue_id); +ZXIC_SINT32 dtb_sdt_dump_dma_alloc(DPP_DEV_T *dev, + ZXIC_UINT32 dma_size, + ZXIC_UINT64 * p_dma_phy_addr, + ZXIC_UINT64 * p_dma_vir_addr); + +ZXIC_SINT32 dtb_sdt_dump_dma_release(DPP_DEV_T *dev, + ZXIC_UINT32 dma_size, + ZXIC_UINT64 dma_phy_addr, + ZXIC_UINT64 dma_vir_addr); +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/dma/dpp_dtb.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/dma/dpp_dtb.h new file mode 100755 index 0000000..e40be24 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/dma/dpp_dtb.h @@ -0,0 +1,696 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_dtb.h +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : zab +* 完成日期 : 2022/08/26 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ +#ifndef _DPP_DTB_H_ +#define _DPP_DTB_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "dpp_dtb_cfg.h" + +#define DPP_DTB_QUEUE_ITEM_NUM_MAX (32) + +#define DPP_DTB_ITEM_ACK_SIZE (16) +#define DPP_DTB_ITEM_BUFF_SIZE (16 * 1024) +#define DPP_DTB_ITEM_SIZE (16 + 16 * 1024) +#define DPP_DTB_TAB_UP_SIZE ((16 + 16 * 1024) * 32) +#define DPP_DTB_TAB_DOWN_SIZE ((16 + 16 * 1024) * 32) + +#define DPP_DTB_TAB_UP_ACK_VLD_MASK (0x555555) +#define DPP_DTB_TAB_DOWN_ACK_VLD_MASK (0x5a5a5a) +#define DPP_DTB_TAB_ACK_IS_USING_MASK (0x11111100) +#define DPP_DTB_TAB_ACK_UNUSED_MASK (0x0) +#define DPP_DTB_TAB_ACK_SUCCESS_MASK (0xff) +#define DPP_DTB_TAB_ACK_FAILED_MASK (0x1) +#define DPP_DTB_TAB_ACK_CHECK_VALUE (0x12345678) + +#define DPP_DTB_TAB_ACK_VLD_SHIFT (104) +#define DPP_DTB_TAB_ACK_STATUS_SHIFT (96) + +#define DPP_DTB_TAB_UP_PHY_ADDR_GET(SLOT_ID, DEV_ID, QUEUE_ID, INDEX) \ + (p_dpp_dtb_mgr[SLOT_ID][DEV_ID]->queue_info[QUEUE_ID].tab_up.start_phy_addr + INDEX * p_dpp_dtb_mgr[SLOT_ID][DEV_ID]->queue_info[QUEUE_ID].tab_up.item_size) +#define DPP_DTB_TAB_UP_USER_PHY_ADDR_GET(SLOT_ID, DEV_ID, QUEUE_ID, INDEX) \ + (p_dpp_dtb_mgr[SLOT_ID][DEV_ID]->queue_info[QUEUE_ID].tab_up.user_addr[INDEX].phy_addr) +#define DPP_DTB_TAB_UP_USER_PHY_ADDR_FLAG_GET(SLOT_ID, DEV_ID, QUEUE_ID, INDEX) \ + (p_dpp_dtb_mgr[SLOT_ID][DEV_ID]->queue_info[QUEUE_ID].tab_up.user_addr[INDEX].user_flag) +#define DPP_DTB_TAB_UP_USER_ADDR_FLAG_SET(SLOT_ID, DEV_ID, QUEUE_ID, INDEX, VAL) \ + do {\ + p_dpp_dtb_mgr[SLOT_ID][DEV_ID]->queue_info[QUEUE_ID].tab_up.user_addr[INDEX].user_flag = VAL;\ + }while(0) +#define DPP_DTB_TAB_DOWN_PHY_ADDR_GET(SLOT_ID, DEV_ID, QUEUE_ID, INDEX) \ + (p_dpp_dtb_mgr[SLOT_ID][DEV_ID]->queue_info[QUEUE_ID].tab_down.start_phy_addr + INDEX * p_dpp_dtb_mgr[SLOT_ID][DEV_ID]->queue_info[QUEUE_ID].tab_down.item_size) +#define DPP_DTB_TAB_UP_VIR_ADDR_GET(SLOT_ID, DEV_ID, QUEUE_ID, INDEX) \ + (p_dpp_dtb_mgr[SLOT_ID][DEV_ID]->queue_info[QUEUE_ID].tab_up.start_vir_addr + INDEX * p_dpp_dtb_mgr[SLOT_ID][DEV_ID]->queue_info[QUEUE_ID].tab_up.item_size) +#define DPP_DTB_TAB_UP_USER_VIR_ADDR_GET(SLOT_ID, DEV_ID, QUEUE_ID, INDEX) \ + (p_dpp_dtb_mgr[SLOT_ID][DEV_ID]->queue_info[QUEUE_ID].tab_up.user_addr[INDEX].vir_addr) +#define DPP_DTB_TAB_DOWN_VIR_ADDR_GET(SLOT_ID, DEV_ID, QUEUE_ID, INDEX) \ + (p_dpp_dtb_mgr[SLOT_ID][DEV_ID]->queue_info[QUEUE_ID].tab_down.start_vir_addr + INDEX * p_dpp_dtb_mgr[SLOT_ID][DEV_ID]->queue_info[QUEUE_ID].tab_down.item_size) +#define DPP_DTB_TAB_UP_WR_INDEX_GET(SLOT_ID, DEV_ID, QUEUE_ID) \ + (p_dpp_dtb_mgr[SLOT_ID][DEV_ID]->queue_info[QUEUE_ID].tab_up.wr_index) +#define DPP_DTB_TAB_UP_RD_INDEX_GET(SLOT_ID, DEV_ID, QUEUE_ID) \ + (p_dpp_dtb_mgr[SLOT_ID][DEV_ID]->queue_info[QUEUE_ID].tab_up.rd_index) +#define DPP_DTB_TAB_DOWN_WR_INDEX_GET(SLOT_ID, DEV_ID, QUEUE_ID) \ + (p_dpp_dtb_mgr[SLOT_ID][DEV_ID]->queue_info[QUEUE_ID].tab_down.wr_index) +#define DPP_DTB_TAB_DOWN_RD_INDEX_GET(SLOT_ID, DEV_ID, QUEUE_ID) \ + (p_dpp_dtb_mgr[SLOT_ID][DEV_ID]->queue_info[QUEUE_ID].tab_down.rd_index) +#define DPP_DTB_TAB_UP_DATA_LEN_GET(SLOT_ID, DEV_ID, QUEUE_ID, INDEX) \ + (p_dpp_dtb_mgr[SLOT_ID][DEV_ID]->queue_info[QUEUE_ID].tab_up.data_len[INDEX]) +#define DPP_DTB_QUEUE_INIT_FLAG_GET(SLOT_ID, DEV_ID, QUEUE_ID) \ + (p_dpp_dtb_mgr[SLOT_ID][DEV_ID]->queue_info[QUEUE_ID].init_flag) +#define DPP_DTB_QUEUE_VPORT_GET(SLOT_ID, DEV_ID, QUEUE_ID) \ + (p_dpp_dtb_mgr[SLOT_ID][DEV_ID]->queue_info[QUEUE_ID].vport) + +#define DPP_BDRING_ITEM_SIZE (16) + +#define DPP_UP_MAC_BD_ITEM_NUM (0XFF) + +#define DPP_BD_ITEM_NUM_MAX (0XFF) +#define DPP_UP_BD_BUFF_SIZE_MAX (4 * 1024) + +#define DPP_UP_MAC_BD_ITEM_SIZE ((DPP_UP_MAC_BD_ITEM_NUM + 1) * DPP_BDRING_ITEM_SIZE) +#define DPP_UP_MAC_BUFF_SIZE (16 * 1024) +#define DPP_UP_MAC_BD_BUFF_SIZE (DPP_UP_MAC_BD_ITEM_NUM * DPP_UP_MAC_BUFF_SIZE) +#define DPP_UP_MAC_BD_TOTAL_SIZE (DPP_UP_MAC_BD_ITEM_SIZE + DPP_UP_MAC_BD_BUFF_SIZE) +#define DPP_DMA_BUFF_SIZE (4*1024*1024) + +#define DPP_DMA_BD_VLD_MSK (0x80000000) +#define DPP_DMA_BD_DATA_LEN_MSK (0x7FF) + +#define DPP_EP_ID_MAX (16) + +#define DPP_DTB_LEN_MIN (1) +#define DPP_DTB_DOWN_LEN (0x3FF) + +#define DPP_DMA_HASH_KEY_OFFSET (6) +#define DPP_DMA_HASH_ITEM_MAX (64) +#define DPP_DMA_HASH_KEY_RST (DPP_DMA_HASH_ITEM_MAX-DPP_DMA_HASH_KEY_OFFSET) + +#define DPP_DMA_SENDTYPE_START_BIT (23) +#define DPP_DMA_SENDTYPE_BIT_NUM (2) +#define DPP_DMA_VALID_START_BIT (23) +#define DPP_DMA_VALID_BIT_NUM (1) +#define DPP_DMA_HASHID_START_BIT (21) +#define DPP_DMA_HASHID_BIT_NUM (2) +#define DPP_DMA_TBLID_START_BIT (16) +#define DPP_DMA_TBLID_BIT_NUM (2) + +typedef struct dpp_dtb_queue_cfg_t +{ + ZXIC_ADDR_T up_start_phy_addr; + ZXIC_ADDR_T up_start_vir_addr; + ZXIC_ADDR_T down_start_phy_addr; + ZXIC_ADDR_T down_start_vir_addr; + + ZXIC_UINT32 up_item_size; + ZXIC_UINT32 down_item_size; +}DPP_DTB_QUEUE_CFG_T; + +typedef struct dpp_dtb_tab_up_user_addr_t +{ + ZXIC_UINT32 user_flag; + + ZXIC_ADDR_T phy_addr; + ZXIC_ADDR_T vir_addr; +}DPP_DTB_TAB_UP_USER_ADDR_T; + +typedef struct dpp_dtb_tab_up_info_t +{ + ZXIC_ADDR_T start_phy_addr; + ZXIC_ADDR_T start_vir_addr; + ZXIC_UINT32 item_size; + + ZXIC_UINT32 wr_index; + ZXIC_UINT32 rd_index; + + ZXIC_UINT32 data_len[DPP_DTB_QUEUE_ITEM_NUM_MAX]; + DPP_DTB_TAB_UP_USER_ADDR_T user_addr[DPP_DTB_QUEUE_ITEM_NUM_MAX]; +}DPP_DTB_TAB_UP_INFO_T; + +typedef struct dpp_dtb_tab_down_info_t +{ + ZXIC_ADDR_T start_phy_addr; + ZXIC_ADDR_T start_vir_addr; + ZXIC_UINT32 item_size; + + ZXIC_UINT32 wr_index; + ZXIC_UINT32 rd_index; +}DPP_DTB_TAB_DOWN_INFO_T; + +typedef struct dpp_dtb_queue_info_t +{ + ZXIC_UINT32 init_flag; + ZXIC_UINT32 slot_id; + ZXIC_UINT32 vport; + ZXIC_UINT32 vector; + + DPP_DTB_TAB_UP_INFO_T tab_up; + DPP_DTB_TAB_DOWN_INFO_T tab_down; +}DPP_DTB_QUEUE_INFO_T; + +typedef struct dpp_dtb_mgr_t +{ + DPP_DTB_QUEUE_INFO_T queue_info[DPP_DTB_QUEUE_NUM_MAX]; +} DPP_DTB_MGR_T; + +typedef enum dpp_dtb_dir_type_e +{ + DPP_DTB_DIR_DOWN_TYPE = 0, + DPP_DTB_DIR_UP_TYPE = 1, + DPP_DTB_DIR_TYPE_MAX, +} DPP_DTB_DIR_TYPE_E; + + +typedef enum dpp_dtb_tab_up_user_addr_type_e +{ + DPP_DTB_TAB_UP_NOUSER_ADDR_TYPE = 0, + DPP_DTB_TAB_UP_USER_ADDR_TYPE = 1, + DPP_DTB_TAB_UP_USER_ADDR_TYPE_MAX, +} DPP_DTB_TAB_UP_USER_ADDR_TYPE_E; + +typedef enum dpp_dma_send_type_e +{ + DMA_LEARN_HASH = 0, + DMA_DEL_HASH = 1, + DMA_UPDATE_HASH = 2, + DMA_ADD_HASH = 3, + DMA_SEND_TYPE_MAX +}DPP_DMA_SEND_TYPE_E; + +/* 单个通道BD表管理结构体 */ +typedef struct dpp_dma_bd_t +{ + ZXIC_ADDR_T bd_phy_addr; /* BD表物理地址 */ + ZXIC_ADDR_T bd_vir_addr; /* BD表进程空间虚拟地址 */ + ZXIC_ADDR_T buff_phy_addr; /* BD表指向的BUFF物理地址 */ + ZXIC_ADDR_T buff_vir_addr; /* BD表指向的BUFF进程空间虚拟地址 */ + ZXIC_UINT32 bd_index; /* BD表当前使用index */ +} DPP_DMA_BD_T; + +/* 单个设备BD表管理结构体 */ +typedef struct dpp_dma_mgr_t +{ + ZXIC_UINT32 init; + ZXIC_UINT32 endian_flag; /* DMA数据通道大小端，0-小端，1-大端 */ + DPP_DMA_BD_T up_mac; +} DPP_DMA_MGR_T; + +/**使能dtb调试函数*/ +ZXIC_UINT32 dpp_dtb_debug_fun_enable(ZXIC_VOID); + +/**去使能dtb调试函数*/ +ZXIC_UINT32 dpp_dtb_debug_fun_disable(ZXIC_VOID); + +/**获取dtb调试函数*/ +ZXIC_UINT32 dpp_dtb_debug_fun_get(ZXIC_VOID); + +/**使能dtb打印函数*/ +ZXIC_UINT32 dpp_dtb_prt_enable(ZXIC_VOID); + +/**去使能dtb打印函数*/ +ZXIC_UINT32 dpp_dtb_prt_disable(ZXIC_VOID); + +/**获取dtb打印函数*/ +ZXIC_UINT32 dpp_dtb_prt_get(ZXIC_VOID); + +ZXIC_UINT32 dpp_dtb_soft_perf_test_set(ZXIC_UINT32 value); + +ZXIC_UINT32 dpp_dtb_soft_perf_test_get(ZXIC_VOID); + +ZXIC_UINT32 dpp_dtb_hardware_perf_test_set(ZXIC_UINT32 value); + +ZXIC_UINT32 dpp_dtb_hardware_perf_test_get(ZXIC_VOID); + +ZXIC_UINT32 dpp_dtb_down_table_overtime_set(ZXIC_UINT32 times_s); +ZXIC_UINT32 dpp_dtb_down_table_overtime_get(ZXIC_VOID); + +ZXIC_UINT32 dpp_dtb_dump_table_overtime_set(ZXIC_UINT32 times_s); +ZXIC_UINT32 dpp_dtb_dump_table_overtime_get(ZXIC_VOID); + +#if ZXIC_REAL("MGR") +/***********************************************************/ +/** 创建DTB的管理结构 +* @param dev_id 设备号，支持多芯片 +* +* @return +* @remark 无 +* @see +* @author zab @date 2021/02/23 +************************************************************/ +ZXIC_UINT32 dpp_dtb_mgr_create(ZXIC_UINT32 slot_id, ZXIC_UINT32 dev_id); + +/***********************************************************/ +/** 注销DTB的管理结构 +* @param dev_id 设备号，支持多芯片 +* +* @return +* @remark 无 +* @see +* @author zab @date 2021/02/23 +************************************************************/ +ZXIC_UINT32 dpp_dtb_mgr_destory_all(ZXIC_VOID); +ZXIC_UINT32 dpp_dtb_mgr_destory(ZXIC_UINT32 slot_id, ZXIC_UINT32 dev_id); + +/***********************************************************/ +/** 重置DTB管理结构 +* @param dev_id 设备号，支持多芯片 +* +* @return +* @remark 无 +* @see +* @author zab @date 2021/02/23 +************************************************************/ +ZXIC_UINT32 dpp_dtb_mgr_reset(ZXIC_UINT32 slot_id, ZXIC_UINT32 dev_id); + +/***********************************************************/ +/** 获取DMA管理结构 +* @param dev_id 设备号，支持多芯片 +* +* @return +* @remark 无 +* @see +* @author zab @date 2021/02/23 +************************************************************/ +DPP_DTB_MGR_T *dpp_dtb_mgr_get(ZXIC_UINT32 slot_id, ZXIC_UINT32 dev_id); +#endif + +#if ZXIC_REAL("ACK_RW") +/***********************************************************/ +/** 读取BD表条目信息 +* @param dev_id 芯片的id号 +* @param queue_id 队列号,范围0-127 +* @param dir_flag 方向,1-上送表项,0-下发表项 +* @param index 条目索引,范围0-31 +* @param pos 一个item里面的4个32位，pos对应的是第几个ZXICP_WORD32， +* 取值为0，1，2，3 +* @param p_data 读取的数据,大端格式 +* +* @return +* @remark 无 +* @see +* @author zab @date 2019/11/2 +************************************************************/ +ZXIC_UINT32 dpp_dtb_item_ack_rd(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 dir_flag, + ZXIC_UINT32 index, + ZXIC_UINT32 pos, + ZXIC_UINT32 *p_data); + +/***********************************************************/ +/** 向BD表条目指定位置写入值 +* @param dev_id 芯片的id号 +* @param queue_id 队列号,范围0-127 +* @param dir_flag 方向,1-上送表项,0-下发表项 +* @param index 条目索引,范围0-31 +* @param pos 一个item里面的4个32位，pos对应的是第几个ZXICP_WORD32， +* 取值为0，1，2，3 +* @param data 读取的数据,大端格式 +* +* @return +* @remark 无 +* @see +* @author zab @date 2019/11/2 +************************************************************/ +ZXIC_UINT32 dpp_dtb_item_ack_wr(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 dir_flag, + ZXIC_UINT32 index, + ZXIC_UINT32 pos, + ZXIC_UINT32 data); +#endif + +#if ZXIC_REAL("BUFF_RW") +/***********************************************************/ +/** 读取dtb条目指向BUFF的数据 +* @param dev_id 芯片的id号 +* @param queue_id 队列号,范围0-127 +* @param dir_flag 方向,1-上送表项,0-下发表项 +* @param index 条目索引,范围0-31 +* @param pos 相对BUFF起始地址的偏移,单位32bit; +* @param p_data 读取的数据,大端格式 +* @param len 读取数据长度,单位32bit; +* +* @return +* @remark 无 +* @see +* @author zab @date 2019/11/2 +************************************************************/ +ZXIC_UINT32 dpp_dtb_item_buff_rd(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 dir_flag, + ZXIC_UINT32 index, + ZXIC_UINT32 pos, + ZXIC_UINT32 len, + ZXIC_UINT32 *p_data); + +/***********************************************************/ +/** 向BD表条目指向的BUFF指定位置写入值 +* @param dev_id 芯片的id号 +* @param queue_id 队列号,范围0-127 +* @param dir_flag 方向,1-上送表项,0-下发表项 +* @param index 条目索引,范围0-31 +* @param pos 相对BUFF起始地址的偏移,单位32bit; +* @param p_data 读取的数据,大端格式 +* @param len 写入数据长度,单位32bit; +* +* @return +* @remark 无 +* @see +* @author zab @date 2019/11/2 +************************************************************/ +ZXIC_UINT32 dpp_dtb_item_buff_wr(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 dir_flag, + ZXIC_UINT32 index, + ZXIC_UINT32 pos, + ZXIC_UINT32 len, + ZXIC_UINT32 *p_data); +#endif + +#if ZXIC_REAL("API") +/***********************************************************/ +/** 配置下发配置数据信息 +* @param dev_id 设备号，支持多芯片 +* @param queue_id 队列号，范围0-31 +* @param int_flag 中断标志，0-无，1-有 +* @param data_len 数据长度，单位32bit; +* @param p_data 待下发数据 +* @param p_item_index 返回使用的条目编号 +* +* @return +* @remark 无 +* @see +* @author zab @date 2021/02/23 +************************************************************/ +ZXIC_UINT32 dpp_dtb_tab_down_info_set(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 int_flag, + ZXIC_UINT32 data_len, + ZXIC_UINT32 *p_data, + ZXIC_UINT32 *p_item_index); + +/***********************************************************/ +/** 一个元素down成功状态检查 +* @param dev_id 设备号，支持多芯片 +* @param queue_id 队列号，范围0-31 +* @param element_id 条目编号 +* +* @return +* @remark 无 +* @see +* @author zab @date 2021/02/23 +************************************************************/ +ZXIC_UINT32 dpp_dtb_tab_down_success_status_check(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 element_id); + +/***********************************************************/ +/** dump队列空闲条目获取 +* @param dev_id 设备号，支持多芯片 +* @param queue_id 队列号，范围0-31 +* @param p_item_index 返回使用的条目编号 +* @return +* @remark 无 +* @see +* @author zab @date 2021/02/23 +************************************************************/ +ZXIC_UINT32 dpp_dtb_tab_up_free_item_get(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 *p_item_index); + +/***********************************************************/ +/** 获取dump指定条目物理地址 +* @param dev_id 设备号，支持多芯片 +* @param queue_id 队列编号,范围:0-127 +* @param item_index 条目编号,范围0-31 +* @param p_phy_haddr 物理地址高32bit +* @param p_phy_laddr 物理地址低32bit +* +* @return +* @remark 无 +* @see +* @author zab @date 2021/02/23 +************************************************************/ +ZXIC_UINT32 dpp_dtb_tab_up_item_addr_get(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 item_index, + ZXIC_UINT32 *p_phy_haddr, + ZXIC_UINT32 *p_phy_laddr); + +/***********************************************************/ +/** 获取指定dump条目一定地址偏移的物理地址 +* @param dev_id 设备号，支持多芯片 +* @param queue_id 队列编号,范围:0-127 +* @param item_index 条目编号,范围0-31 +* @param p_phy_haddr 物理地址高32bit +* @param p_phy_laddr 物理地址低32bit +* +* @return +* @remark 无 +* @see +* @author zab @date 2021/02/23 +************************************************************/ +ZXIC_UINT32 dpp_dtb_tab_up_item_offset_addr_get(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 item_index, + ZXIC_UINT32 addr_offset, + ZXIC_UINT32 *p_phy_haddr, + ZXIC_UINT32 *p_phy_laddr); + +/***********************************************************/ +/** 设置dump指定条目空间地址，用于用户自定义空间传输 +* @param dev_id 设备号，支持多芯片 +* @param queue_id 队列编号,范围:0-127 +* @param item_index 条目编号,范围0-31 +* @param phy_haddr 物理地址高 +* @param vir_laddr 虚拟地址低 +* +* @return +* @remark 无 +* @see +* @author zab @date 2021/02/23 +************************************************************/ +ZXIC_UINT32 dpp_dtb_tab_up_item_user_addr_set(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 item_index, + ZXIC_ADDR_T phy_addr, + ZXIC_ADDR_T vir_addr); + +/***********************************************************/ +/** 清除用户dump指定条目空间地址 +* @param dev_id 设备号，支持多芯片 +* @param queue_id 队列编号,范围:0-127 +* @param item_index 条目编号,范围0-31 +* +* @return +* @remark 无 +* @see +* @author zab @date 2021/02/23 +************************************************************/ +ZXIC_UINT32 dpp_dtb_tab_up_item_user_addr_clr(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 item_index); + +/***********************************************************/ +/** dump配置描述符信息设置 +* @param dev_id 设备号，支持多芯片 +* @param queue_id 队列号，范围0-31 +* @param item_index 返回使用的条目编号 +* @param int_flag 中断标志，0-无，1-有 +* @param data_len 数据长度，单位32bit; +* @param desc_len 描述符长度，单位32bit; +* @param p_desc_data 待下发描述符 +* @return +* @remark 无 +* @see +* @author zab @date 2021/02/23 +************************************************************/ +ZXIC_UINT32 dpp_dtb_tab_up_info_set(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 item_index, + ZXIC_UINT32 int_flag, + ZXIC_UINT32 data_len, + ZXIC_UINT32 desc_len, + ZXIC_UINT32 *p_desc_data); + +/***********************************************************/ +/** 一个元素dump成功状态检查 +* @param dev_id 设备号，支持多芯片 +* @param queue_id 队列号，范围0-31 +* @param element_id 条目编号 +* +* @return +* @remark 无 +* @see +* @author zab @date 2021/02/23 +************************************************************/ +ZXIC_UINT32 dpp_dtb_tab_up_success_status_check(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 element_id); + +/***********************************************************/ +/** 获取dump数据 +* @param dev_id 设备号，支持多芯片 +* @param queue_id 队列号，范围0-31 +* @param item_index 数据对应的的条目编号 +* @param data_len 数据长度，单位32bit; +* @param p_data dump数据 +* +* @return +* @remark 无 +* @see +* @author zab @date 2021/02/23 +************************************************************/ +ZXIC_UINT32 dpp_dtb_tab_up_data_get(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 item_index, + ZXIC_UINT32 data_len, + ZXIC_UINT32 *p_data); + +/***********************************************************/ +/** dtb初始化 +* @param dev_id 设备号，支持多芯片 +* +* @return +* @remark 无 +* @see +* @author zab @date 2022/08/30 +************************************************************/ +ZXIC_UINT32 dpp_dtb_init(DPP_DEV_T *dev); + +/***********************************************************/ +/** dtb队列down初始化 +* @param dev_id 设备号，支持多芯片 +* @param queue_id 队列号 +* @param p_queue_cfg 队列配置参数，具体见DPP_DTB_QUEUE_CFG_T结构体类型 +* +* @return +* @remark 无 +* @see +* @author zab @date 2021/02/23 +************************************************************/ +ZXIC_UINT32 dpp_dtb_queue_down_init(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + DPP_DTB_QUEUE_CFG_T *p_queue_cfg); + +/***********************************************************/ +/** dtb队列dump初始化 +* @param dev_id 设备号，支持多芯片 +* @param queue_id 队列号 +* @param p_queue_cfg 队列配置参数，具体见DPP_DTB_QUEUE_CFG_T结构体类型 +* +* @return +* @remark 无 +* @see +* @author zab @date 2021/02/23 +************************************************************/ +ZXIC_UINT32 dpp_dtb_queue_dump_init(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + DPP_DTB_QUEUE_CFG_T *p_queue_cfg); + +/***********************************************************/ +/** dtb队列down 空间地址配置 +* @param channelId dtb通道号 +* @param phyAddr down物理地址 +* @param virAddr down虚拟地址 +* @param size 空间大小 +* +* @return +* @remark 无 +* @see +* @author zab @date 2021/02/23 +************************************************************/ +ZXIC_UINT32 dpp_dtb_down_channel_addr_set(DPP_DEV_T *dev, + ZXIC_UINT32 channelId, + ZXIC_UINT64 phyAddr, + ZXIC_UINT64 virAddr, + ZXIC_UINT32 size); + +/***********************************************************/ +/** dtb队列dump 空间地址配置 +* @param channelId dtb通道号 +* @param phyAddr dump物理地址 +* @param virAddr dump虚拟地址 +* @param size 空间大小 +* +* @return +* @remark 无 +* @see +* @author zab @date 2021/02/23 +************************************************************/ +ZXIC_UINT32 dpp_dtb_dump_channel_addr_set(DPP_DEV_T *dev, + ZXIC_UINT32 channelId, + ZXIC_UINT64 phyAddr, + ZXIC_UINT64 virAddr, + ZXIC_UINT32 size); + +/***********************************************************/ +/** 释放队列资源 +* @param dev_id 设备号，支持多芯片 +* @param queue_id 分配到的队列号; +* +* @return +* @remark 无 +* @see +* @author zab @date 2021/02/23 +************************************************************/ +ZXIC_UINT32 dpp_dtb_queue_id_free(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id); + +/***********************************************************/ +/** 根据vport查找相应的队列号 +* @param dev_id 设备号，支持多芯片 +* @param vport vport信息 +* @param p_queue_arr 找到到队列数组 +* @param p_num 找到的队列个数 +* @return +* @remark 无 +* @see +* @author cbb @date 2023/09/13 +************************************************************/ +ZXIC_UINT32 dpp_dtb_queue_id_search_by_vport(DPP_DEV_T *dev, + ZXIC_UINT32 *p_queue_arr, + ZXIC_UINT32 *p_num); + +/***********************************************************/ +/** 根据vport查找相应的队列号 +* @param dev_id 设备号，支持多芯片 +* @param vport vport信息 +* @param p_queue_arr 找到到队列数组 +* @param p_num 找到的队列个数 +* @return +* @remark 无 +* @see +* @author cbb @date 2023/09/13 +************************************************************/ +ZXIC_UINT32 dpp_dtb_queue_id_get(ZXIC_UINT32 dev_id, DPP_PF_INFO_T* pf_info, ZXIC_UINT32 *queue); + +#endif + +#if ZXIC_REAL("DMA") + +#endif + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/dma/dpp_dtb_cfg.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/dma/dpp_dtb_cfg.h new file mode 100755 index 0000000..08fdd24 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/dma/dpp_dtb_cfg.h @@ -0,0 +1,439 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_dtb_cfg.h +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : zab +* 完成日期 : 2022/08/23 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ +#ifndef _DPP_DTB_CFG_H_ +#define _DPP_DTB_CFG_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "dpp_dev.h" + +#define DPP_DEV_SLOT_MAX (256) +#define DPP_DTB_QUEUE_NUM_MAX (128) +#define DPP_DTB_TRAF_CTRL_RAM_SIZE (256) +#define DPP_DTB_TRAF_CTRL_RAM_5_SIZE (64) +#define DPP_DTB_DUMP_PD_RAM_SIZE (2048) +#define DPP_DTB_RD_CTRL_RAM_SIZE (4096) +#define DPP_DTB_RD_TABLE_RAM_SIZE (8192) +#define DPP_DTB_CMD_MAN_RAM_SIZE (16384) + +/*vport格式 +15 |14 13 12 | 11 |10 9 8|7 6 5 4 3 2 1 0| +rsv| ep_id |func_active|func_num| vfunc_num | +*/ +#define VPORT_EPID_BT_START (12) /*EPID起始位*/ +#define VPORT_EPID_BT_LEN (3) /*EPID长度*/ +#define VPORT_FUNC_ACTIVE_BT_START (11) /*FUNC_ACTIVE起始位*/ +#define VPORT_FUNC_ACTIVE_BT_LEN (1) /*FUNC_ACTIVE长度*/ +#define VPORT_FUNC_NUM_BT_START (8) /*FUNC_NUM起始位*/ +#define VPORT_FUNC_NUM_BT_LEN (3) /*FUNC_NUM长度*/ +#define VPORT_VFUNC_NUM_BT_START (0) /*FUNC_NUM起始位*/ +#define VPORT_VFUNC_NUM_BT_LEN (8) /*FUNC_NUM长度*/ + +typedef struct dpp_dtb_queue_item_info_t +{ + ZXIC_UINT32 cmd_vld; + ZXIC_UINT32 cmd_type; + ZXIC_UINT32 int_en; + ZXIC_UINT32 data_len; + ZXIC_UINT32 data_laddr; + ZXIC_UINT32 data_hddr; +} DPP_DTB_QUEUE_ITEM_INFO_T; + +typedef struct dpp_dtb_queue_vm_info_t +{ + ZXIC_UINT32 dbi_en; + ZXIC_UINT32 queue_en; + ZXIC_UINT32 epid; + ZXIC_UINT32 vfunc_num; + ZXIC_UINT32 vector; + ZXIC_UINT32 func_num; + ZXIC_UINT32 vfunc_active; +} DPP_DTB_QUEUE_VM_INFO_T; + +#if ZXIC_REAL("DTB_CFG") +/***********************************************************/ +/** DTB队列元素信息配置 +* @param dev_id 芯片id +* @param queue_id 队列ID，范围0-127 +* @param p_item_info 队列元素配置信息 +* +* @return +* @remark 无 +* @see +* @author zab @date 2018/08/23 +************************************************************/ +ZXIC_UINT32 dpp_dtb_queue_item_info_set(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + DPP_DTB_QUEUE_ITEM_INFO_T *p_item_info); + +/***********************************************************/ +/** 获取DTB队列中剩余未使用的条目数量 +* @param dev_id 芯片id +* @param queue_id 队列ID，范围0-127 +* @param p_item_num 剩余未使用条目数量 +* +* @return +* @remark 无 +* @see +* @author zab @date 2018/08/23 +************************************************************/ +ZXIC_UINT32 dpp_dtb_queue_unused_item_num_get(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 *p_item_num); + +/***********************************************************/ +/** 配置队列VM相关信息 +* @param dev_id 芯片id +* @param queue_id 队列ID，范围0-127 +* @param p_vm_info VM配置信息 +* +* @return +* @remark 无 +* @see +* @author zab @date 2018/08/23 +************************************************************/ +ZXIC_UINT32 dpp_dtb_queue_vm_info_set(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + DPP_DTB_QUEUE_VM_INFO_T *p_vm_info); + + +/***********************************************************/ +/** 获取队列VM配置信息 +* @param dev_id оƬid +* @param queue_id 队列ID，范围0-127 +* @param p_vm_info VM配置信息 +* +* @return +* @remark 无 +* @see +* @author zab @date 2018/08/23 +************************************************************/ +ZXIC_UINT32 dpp_dtb_queue_vm_info_get(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + DPP_DTB_QUEUE_VM_INFO_T *p_vm_info); + +/***********************************************************/ +/** 配置队列使能 +* @param dev_id 芯片id +* @param queue_id 队列ID，范围0-127 +* @param enable 1:队列使能,0:队列去使能 +* +* @return +* @remark 无 +* @see +* @author cbb @date 2023/09/27 +************************************************************/ +ZXIC_UINT32 dpp_dtb_queue_enable_set(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 enable); + +/***********************************************************/ +/** 获取队列使能状态 +* @param dev_id 芯片id +* @param queue_id 队列ID，范围0-127 +* @param enable 1:队列使能,0:队列去使能 +* +* @return +* @remark 无 +* @see +* @author cbb @date 2023/09/27 +************************************************************/ +ZXIC_UINT32 dpp_dtb_queue_enable_get(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 *enable); + + +/***********************************************************/ +/** 配置 dtb 完成中断事件状态 +* @param dev_id 芯片id +* @param queue_id 队列ID，范围0-127 +* @param state 中断事件状态，1-发生中断，0-无中断发生 +* +* @return +* @remark 无 +* @see +* @author cbb @date 2022/11/12 +************************************************************/ +ZXIC_UINT32 dpp_dtb_finish_interrupt_event_state_set(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 state); + + +/***********************************************************/ +/** 清除 dtb 完成中断事件状态 +* @param dev_id 芯片id +* @param queue_id 队列ID，范围0-127 +* +* @return +* @remark 无 +* @see +* @author cbb @date 2022/11/12 +************************************************************/ +ZXIC_UINT32 dpp_dtb_finish_interrupt_event_state_clr(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id); + +ZXIC_UINT32 dpp_dtb_debug_mode_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_debug_mode); + +ZXIC_UINT32 dpp_dtb_mode_is_debug(DPP_DEV_T *dev); + +/***********************************************************/ +/** 读取axi 最近一次读表相关信息 +* @param dev_id 芯片id +* @param p_last_rd_table_addr_h axim最近一次读表高地址 +* @param p_last_rd_table_addr_l axim最近一次读表低地址 +* @param p_last_rd_table_len axim最近一次读表长度 +* @param p_last_rd_table_user axim最近一次读表USER信号 +* @param p_last_rd_table_onload_cnt axim最近一次读表在线计数 +* +* @return +* @remark 无 +* @see +* @author cbb @date 2022/11/09 +************************************************************/ +ZXIC_UINT32 dpp_dtb_axi_last_rd_table_info_get(DPP_DEV_T *dev, + ZXIC_UINT32 *p_last_rd_table_addr_h, + ZXIC_UINT32 *p_last_rd_table_addr_l, + ZXIC_UINT32 *p_last_rd_table_len, + ZXIC_UINT32 *p_last_rd_table_user, + ZXIC_UINT32 *p_last_rd_table_onload_cnt + ); + +/***********************************************************/ +/** 读表通道错误次数统计 +* @param dev_id 芯片id +* @param p_axi_rd_table_resp_err_cnt 读表通道返回错误次数 +* +* @return +* @remark 无 +* @see +* @author cbb @date 2022/11/09 +************************************************************/ +ZXIC_UINT32 dpp_dtb_axi_rd_table_resp_err_cnt_get(DPP_DEV_T *dev, + ZXIC_UINT32 *p_axi_rd_table_resp_err_cnt + ); + +/***********************************************************/ +/** 读取axi 最近一次读PD相关信息 +* @param dev_id 芯片id +* @param p_last_rd_pd_addr_h axim最近一次读PD高地址 +* @param p_last_rd_pd_addr_l axim最近一次读PD低地址 +* @param p_last_rd_pd_len axim最近一次读PD长度 +* @param p_last_rd_pd_user axim最近一次读PD USER信号 +* @param p_last_rd_pd_onload_cnt axim最近一次读PD在线计数 +* +* @return +* @remark 无 +* @see +* @author cbb @date 2022/11/09 +************************************************************/ +ZXIC_UINT32 dpp_dtb_axi_last_rd_pd_info_get(DPP_DEV_T *dev, + ZXIC_UINT32 *p_last_rd_pd_addr_h, + ZXIC_UINT32 *p_last_rd_pd_addr_l, + ZXIC_UINT32 *p_last_rd_pd_len, + ZXIC_UINT32 *p_last_rd_pd_user, + ZXIC_UINT32 *p_last_rd_pd_onload_cnt + ); + +/***********************************************************/ +/** 读PD通道错误次数统计 +* @param dev_id 芯片id +* @param p_axi_rd_pd_resp_err_cnt 读PD通道返回错误次数 +* +* @return +* @remark 无 +* @see +* @author cbb @date 2022/11/09 +************************************************************/ +ZXIC_UINT32 dpp_dtb_axi_rd_pd_resp_err_cnt_get(DPP_DEV_T *dev, + ZXIC_UINT32 *p_axi_rd_pd_resp_err_cnt + ); + +/***********************************************************/ +/** 读取axim 最近一次写控制相关信息 +* @param dev_id 芯片id +* @param p_last_wr_ctrl_addr_h axim最近一次写控制高地址 +* @param p_last_wr_ctrl_addr_l axim最近一次写控制低地址 +* @param p_last_wr_ctrl_len axim最近一次写控制长度 +* @param p_last_wr_ctrl_user axim最近一次写控制 USER信号 +* @param p_last_wr_ctrl_onload_cnt axim最近一次写控制在线计数 +* +* @return +* @remark 无 +* @see +* @author cbb @date 2022/11/09 +************************************************************/ +ZXIC_UINT32 dpp_dtb_axi_last_wr_ctrl_info_get(DPP_DEV_T *dev, + ZXIC_UINT32 *p_last_wr_ctrl_addr_h, + ZXIC_UINT32 *p_last_wr_ctrl_addr_l, + ZXIC_UINT32 *p_last_wr_ctrl_len, + ZXIC_UINT32 *p_last_wr_ctrl_user, + ZXIC_UINT32 *p_last_wr_ctrl_onload_cnt + ); + +/***********************************************************/ +/** 获取写控制通道错误次数统计 +* @param dev_id 芯片id +* @param p_axi_wr_ctrl_resp_err_cnt 写控制通道返回错误次数 +* +* @return +* @remark 无 +* @see +* @author cbb @date 2022/11/09 +************************************************************/ +ZXIC_UINT32 dpp_dtb_axi_wr_ctrl_resp_err_cnt_get(DPP_DEV_T *dev, + ZXIC_UINT32 *p_axi_wr_ctrl_resp_err_cnt + ); + +/***********************************************************/ +/** 读取axim 最近一次写DDR相关信息 +* @param dev_id 芯片id +* @param p_last_wr_ddr_addr_h axim最近一次写控制高地址 +* @param p_last_wr_ddr_addr_l axim最近一次写控制低地址 +* @param p_last_wr_ddr_len axim最近一次写控制长度 +* @param p_last_wr_ddr_user axim最近一次写控制 USER信号 +* @param p_last_wr_ddr_onload_cnt axim最近一次写控制在线计数 +* +* @return +* @remark 无 +* @see +* @author cbb @date 2022/11/09 +************************************************************/ +ZXIC_UINT32 dpp_dtb_axi_last_wr_ddr_info_get(DPP_DEV_T *dev, + ZXIC_UINT32 *p_last_wr_ddr_addr_h, + ZXIC_UINT32 *p_last_wr_ddr_addr_l, + ZXIC_UINT32 *p_last_wr_ddr_len, + ZXIC_UINT32 *p_last_wr_ddr_user, + ZXIC_UINT32 *p_last_wr_ddr_onload_cnt + ) ; + +/***********************************************************/ +/** 获取写DDR通道错误次数统计 +* @param dev_id 芯片id +* @param p_axi_wr_ddr_resp_err_cnt 写DDR通道返回错误次数 +* +* @return +* @remark 无 +* @see +* @author cbb @date 2022/11/09 +************************************************************/ +ZXIC_UINT32 dpp_dtb_axi_wr_ddr_resp_err_cnt_get(DPP_DEV_T *dev, + ZXIC_UINT32 *p_axi_wr_ddr_resp_err_cnt + ) ; + +/***********************************************************/ +/** 读取axim 最近一次写完成相关信息 +* @param dev_id 芯片id +* @param p_last_wr_fin_addr_h axim最近一次写控制高地址 +* @param p_last_wr_fin_addr_l axim最近一次写控制低地址 +* @param p_last_wr_fin_len axim最近一次写控制长度 +* @param p_last_wr_fin_user axim最近一次写控制 USER信号 +* @param p_last_wr_fin_onload_cnt axim最近一次写控制在线计数 +* +* @return +* @remark 无 +* @see +* @author cbb @date 2022/11/09 +************************************************************/ +ZXIC_UINT32 dpp_dtb_axi_last_wr_fin_info_get(DPP_DEV_T *dev, + ZXIC_UINT32 *p_last_wr_fin_addr_h, + ZXIC_UINT32 *p_last_wr_fin_addr_l, + ZXIC_UINT32 *p_last_wr_fin_len, + ZXIC_UINT32 *p_last_wr_fin_user, + ZXIC_UINT32 *p_last_wr_fin_onload_cnt + ) ; + +/***********************************************************/ +/** 获取写完成通道错误次数统计 +* @param dev_id 芯片id +* @param p_axi_wr_fin_resp_err_cnt 写完成通道返回错误次数 +* +* @return +* @remark 无 +* @see +* @author cbb @date 2022/11/09 +************************************************************/ +ZXIC_UINT32 dpp_dtb_axi_wr_fin_resp_err_cnt_get(DPP_DEV_T *dev, + ZXIC_UINT32 *p_axi_wr_fin_resp_err_cnt + ) ; + +/***********************************************************/ +/** 读取 DTB 各通道状态机 +* @param dev_id 芯片id +* @param p_wr_ctrl_state_info 写控制状态机 +* @param p_rd_table_state_info 读表状态机 +* @param p_rd_pd_state_info 读描述符数据状态机 +* @param p_wr_ddr_state_info 写数据到ddr的状态机 +* @param p_wr_fin_state_info 写结束标志的状态机 +* +* @return +* @remark 无 +* @see +* @author cbb @date 2022/11/09 +************************************************************/ +ZXIC_UINT32 dpp_dtb_state_info_get(DPP_DEV_T *dev, + ZXIC_UINT32 *p_wr_ctrl_state_info, + ZXIC_UINT32 *p_rd_table_state_info, + ZXIC_UINT32 *p_rd_pd_state_info, + ZXIC_UINT32 *p_wr_ddr_state_info, + ZXIC_UINT32 *p_dump_cmd_state_info + ); + +/***********************************************************/ +/** 各通道错误统计打印 +* @param dev_id 芯片的id号 +* +* @return +* @remark 无 +* @see +* @author cbb @date 2022/11/11 +************************************************************/ +ZXIC_UINT32 diag_dpp_dtb_channels_axi_resp_err_cnt_prt(DPP_DEV_T *dev); + +/***********************************************************/ +/** AXIM最近一次操作信息记录打印 +* @param dev_id 芯片的id号 +* +* @return +* @remark 无 +* @see +* @author cbb @date 2022/11/11 +************************************************************/ +ZXIC_UINT32 diag_dpp_dtb_axi_last_operate_info_prt(DPP_DEV_T *dev); + +/***********************************************************/ +/** DTB 各通道状态机信息获取 +* @param dev_id 芯片的id号 +* +* @return +* @remark 无 +* @see +* @author cbb @date 2022/11/11 +************************************************************/ +ZXIC_UINT32 diag_dpp_dtb_channels_state_info_prt(DPP_DEV_T *dev); + +#endif + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/nppu/dpp_pbu.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/nppu/dpp_pbu.h new file mode 100644 index 0000000..e2d3fc0 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/nppu/dpp_pbu.h @@ -0,0 +1,458 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_pbu.h +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : djf +* 完成日期 : 2014/04/14 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ +#ifndef _DPP_PBU_H_ +#define _DPP_PBU_H_ + +#include "dpp_nppu_reg.h" +#include "dpp_pbu_api.h" + +#if ZXIC_REAL("macro") +/****************************************************************************** + * START: 宏定义 * + *****************************************************************************/ +#define DPP_PBU_IND_CMD_WRT_FLAG (0) +#define DPP_PBU_IND_CMD_RD_FLAG (1) + +#define PBU_FILE_PATH ("sa500t_pbu_output.txt") +#define PBU_FILE_PATH_RAM ("sa500t_pbu_output_ram.txt") + +#define DPP_PBU_PORT_NUM (119) /** 物理端口号个数(0-128) */ +#define DPP_PBU_PORT_TH_MAX (16380) /** IDMA指针阈值最大值 */ + +#define DPP_PBU_LIF0_PORT_NUM (48) /** lif0 48个通道对应的物理端口号个数(0-47) */ +#define DPP_PBU_LIF1_PORT_NUM (56) /** lif1 8个通道对应的物理端口号个数(48~55) */ +#define DPP_PBU_TM_LOOP_PORT_NUM (113) /** TM还回通道113 */ + + +#define DPP_PBU_COS_NUM (8) /** COS个数*/ +#define DPP_PBU_ALL_FTM_LINK_TH_NUM (6) /** COS个数*/ +#define DPP_PBU_IDMA_MAX_TH (16380) /** IDMA指针阈值最大值 */ +#define DPP_PBU_LIF_MAX_TH (16384) /** LIF指针阈值最大值 */ +#define DPP_PBU_MC_MAX_TH (16380) /** 组播指针阈值最大值 */ +#define DPP_PBU_PORT_COS_MAX_TH (16380) /** 单个端口指针阈值最大值 */ +#define DPP_PBU_MC_MAX_DIFF_TH (255) /** 组播指针申请逻辑复制和微码复制直接的阈值差最大值 */ +#define DPP_PBU_MC_MIN_DIFF_TH (5) /** 组播指针申请逻辑复制和微码复制直接的阈值差最小值 */ +#define DPP_PBU_CAP_DATA_MODE_MIN (0) /** PBU抓包数据模式最小值 */ +#define DPP_PBU_CAP_DATA_MODE_MAX (12) /** PBU抓包数据模式最大值 */ + +#define DPP_PBU_CAP_FILTER_ADDR (0x185) +#define DPP_PBU_CAP_PKT_NUM (64) /** 抓包的最大分片个数 */ + +/****************************************************************************** + * END: 宏定义 * + *****************************************************************************/ +#endif + + +#if ZXIC_REAL("struct") + + +typedef enum npe_pbu_ptr_rotate_e{ + DPP_PBU_TOTAL_PTR_ROTATE = 0X1, /**< @brief 全局指针翻转*/ + DPP_PBU_MC_PTR_ROTATE = 0X2, /**< @brief 组播指针翻转*/ + DPP_PBU_PORT_PTR_ROTATE = 0X4, /**< @brief 端口指针翻转*/ + +}DPP_PBU_PTR_ROTATE_E; + + +/****************************************************************************** + * START: 类型定义 * + *****************************************************************************/ +typedef struct dpp_pbu_cnt_para_t +{ + ZXIC_UINT32 total_cnt; /* 总指针计数 */ + ZXIC_UINT32 idma_pub_cnt; /* idma共享指针计数 */ + ZXIC_UINT32 lif_pub_cnt; /* lif共享指针计数 */ + ZXIC_UINT32 mc_total_cnt; /* mc总指针计数 */ +} DPP_PBU_CNT_PARA_T; +/* +typedef struct dpp_pbu_module_fc_rdy_t +{ + ZXIC_UINT32 pbu_oam_send_fc_rdy; + ZXIC_UINT32 pbu_lif_ctrl_rdy; + ZXIC_UINT32 pbu_odma_fc_rdy; + ZXIC_UINT32 pbu_tm_fc_rdy; + ZXIC_UINT32 pbu_idma_cos_rdy; +}DPP_PBU_MODULE_FC_RDY_T; +*/ + +typedef struct dpp_mf_info_t +{ + ZXIC_CHAR* name; + ZXIC_UINT32 start_bit; + ZXIC_UINT32 end_bit; +}DPP_MF_INFO_T; + + +typedef enum dpp_pbu_ind_mem_id_e +{ + DPP_PBU_IDMATH_RAM= 0, /**< @brief 端口阈值RAM，可读可写 */ + DPP_PBU_MACTH_RAM = 1, /**< @brief 端口COS阈值RAM，可读可写 */ + DPP_PBU_CFG_IND_MEM_ID_INVALID = 2, /**< @brief PBU CFG模块使用的内部表的个数 */ +} DPP_PBU_CFG_IND_MEM_ID_E; + +typedef enum dpp_pbu_stat_ind_mem_id_e +{ + DPP_PBU_PORT_CNT = 1, /**< @brief 端口的指针计数，只读 */ + DPP_PBU_STAT = 2, /**< @brief PBU调试计数，只读 */ + DPP_PBU_IFB_CFG = 3, /**< @brief IFB中192字节报文，只读 */ + DPP_PBU_CAPTURE_CFG = 4, /**< @brief 报文抓包 可读可写 */ + DPP_PBU_PORT_PUB_CNT = 5, + DPP_PBU_IND_MEM_ID_INVALID = 6, /**< @brief PBU模块使用的内部表的个数*/ +} DPP_PBU_STAT_IND_MEM_ID_E; + +typedef enum dpp_idma_stat_ind_mem_id_e +{ + DPP_IDMA_STAT_RAM = 0, + DPP_IDMA_DEBUG_RAM = 1, + DPP_IDMA_IND_MEM_ID_INVALID = 2, /**< @brief IDMA模块使用的内部表的个数*/ +} DPP_IDMA_STAT_IND_MEM_ID_E; + +typedef enum dpp_pbu_other_cnt_id_e +{ + DPP_PBU_IDMA_PTR_REQ_CNT = 0, /**< @brief idma指针申请计数，含无效申请 */ + DPP_PBU_IDMA_RFD_WR_CNT = 1, /**< @brief idma写RFD计数 */ + DPP_PBU_IDMA_IFB_WR1_CNT = 2, /**< @brief idma写ifb高64字节计数 */ + DPP_PBU_IDMA_IFB_WR2_CNT = 3, /**< @brief idma写ifb低128字节计数 */ + DPP_PBU_PPU_IFB_RD_CNT = 4, /**< @brief ppu读ifb申请计数 */ + DPP_PBU_IFB_PPU_RDRSP_CNT = 5, /**< @brief ifb返回给ppu包头计数 */ + DPP_PBU_ODMA_RECY_PTR_CNT = 6, /**< @brief odma指针回收个数 */ + DPP_PBU_PPU_PF_REQ0_CNT = 7, /**< @brief ppu微码复制申请指针计数 */ + DPP_PBU_PBU_PF_RSP0_CNT = 8, /**< @brief pbu返回微码复制申请指针计数 */ + DPP_PBU_PPU_PF_REQ1_CNT = 9, /**< @brief ppu逻辑复制申请指针计数 */ + DPP_PBU_PBU_PF_RSP1_CNT = 10, /**< @brief pbu返回逻辑复制申请指针计数 */ + DPP_PBU_PPU_USE_PTR_CNT = 11, /**< @brief idma有效申请指针计数 */ + DPP_PBU_PPU_WRBK_CNT = 12, /**< @brief ppu回写计数 */ + DPP_PBU_PPU_REORDER_RSP_CNT = 13, /**< @brief pbu返回ppu回写参数计数 */ + DPP_PBU_SE_PBU_KEY_VLD_CNT = 14, /**< @brief 深度解析请求计数 */ + DPP_PBU_PBU_SE_RSP_VLD_CNT = 15, /**< @brief 深度解析返回计数 */ + DPP_PBU_ODMA_IFB_RD1_CNT = 16, /**< @brief odma读ifb接口1读请求计数 */ + DPP_PBU_ODMA_IFB_RD2_CNT = 17, /**< @brief odma读ifb接口2读请求计数 */ + DPP_PBU_IDMA_O_ISU_PKT_CNT = 18, /**< @brief idma输出报文总计数 */ + DPP_PBU_IDMA_O_ISU_EPKT_CNT = 19, /**< @brief idma输出带error标记的报文总计数 */ + DPP_PBU_IDMA_DISPKT_CNT = 20, /**< @brief idma丢弃报文总数 */ + DPP_PBU_OTHER_CNT_ID_INVALID, /**< @brief PBU模块other计数的个数*/ +} DPP_PBU_OTHER_CNT_ID_E; + + +typedef struct dpp_pbu_port_ptr_cnt_t +{ + ZXIC_UINT32 peak_port_cnt; /**< @brief 端口指针峰值 */ + ZXIC_UINT32 current_port_cnt;/**< @brief 端口指针占用 */ +} DPP_PBU_PORT_PTR_CNT_T; + +typedef struct dpp_pbu_ifb_data_t +{ + ZXIC_UINT32 pbu_ifb_data[64];/**< @brief ifb数据 */ +} DPP_PBU_IFB_DATA_T; + + +typedef struct dpp_pbu_all_ftm_link_th_t +{ + ZXIC_UINT32 total_congest_th[7]; /**< @brief 拥塞阈值*/ +} DPP_PBU_ALL_FTM_LINK_TH_T; + +typedef struct +{ + ZXIC_UINT32 pbu_lif_group0_pfc_rdy[12]; +} DPP_PBU_LIF_GROUP_PFC_RDY; + + + +/****************************************************************************** + * END: 类型定义 * + *****************************************************************************/ +#endif + +#if 1 +/****************************************************************************** + * START: 函数声明 * + *****************************************************************************/ +#if 0 +DPP_STATUS dpp_pbu_idma_public_th_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 th); +DPP_STATUS dpp_pbu_idma_public_th_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *p_th); +DPP_STATUS dpp_pbu_lif_public_th_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 th); +DPP_STATUS dpp_pbu_lif_public_th_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *p_th); +DPP_STATUS dpp_pbu_idma_total_th_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 th); +DPP_STATUS dpp_pbu_idma_total_th_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *p_th); +DPP_STATUS dpp_pbu_lif_total_th_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 th); +DPP_STATUS dpp_pbu_lif_total_th_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *p_th); +DPP_STATUS dpp_pbu_mc_total_th_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 th); +DPP_STATUS dpp_pbu_mc_total_th_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *p_th); + +DPP_STATUS dpp_pbu_mc_cos_para_get(ZXIC_UINT32 dev_id, + DPP_PBU_MC_COS_PARA_T *p_para); +DPP_STATUS dpp_pbu_sa_ip_en_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 en); +DPP_STATUS dpp_pbu_sa_ip_en_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *p_en); +DPP_STATUS dpp_pbu_cnt_ovfl_mode_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 mode); +DPP_STATUS dpp_pbu_cnt_ovfl_mode_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *p_mode); +DPP_STATUS dpp_pbu_cnt_rdclr_mode_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 mode); +DPP_STATUS dpp_pbu_cnt_rdclr_mode_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *p_mode); +DPP_STATUS dpp_pbu_mc_diff_th_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 th); +DPP_STATUS dpp_pbu_mc_diff_th_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *p_th); +DPP_STATUS dpp_pbu_peak_port_cnt_clr_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 port_no, ZXIC_UINT32 peak_port_cnt_clr); +DPP_STATUS dpp_pbu_peak_port_cnt_clr_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 port_no, ZXIC_UINT32* p_peak_port_cnt_clr); +DPP_STATUS dpp_pbu_all_ftm_crdt_th_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 port_no, DPP_NPPU_PBU_CFG_ALL_FTM_CRDT_TH_T* p_all_ftm_crdt_th); +DPP_STATUS dpp_pbu_all_ftm_crdt_th_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 port_no, DPP_NPPU_PBU_CFG_ALL_FTM_CRDT_TH_T* p_all_ftm_crdt_th); +DPP_STATUS dpp_pbu_all_ftm_link_th_set(ZXIC_UINT32 dev_id, + DPP_PBU_ALL_FTM_LINK_TH_T *p_para); +DPP_STATUS dpp_pbu_all_ftm_link_th_get(ZXIC_UINT32 dev_id, + DPP_PBU_ALL_FTM_LINK_TH_T *p_para); +DPP_STATUS dpp_pbu_ftm_total_congest_th_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 total_congest_th); +DPP_STATUS dpp_pbu_ftm_total_congest_th_get(ZXIC_UINT32 dev_id, ZXIC_UINT32* total_congest_th); +DPP_STATUS dpp_pbu_crdt_mode_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 crdt_mode); +DPP_STATUS dpp_pbu_crdt_mode_get(ZXIC_UINT32 dev_id, ZXIC_UINT32* p_crdt_mode); +DPP_STATUS dpp_pbu_ind_reg_mode_status_check(ZXIC_UINT32 dev_id, ZXIC_UINT32 sub_module_ind_status_reg, ZXIC_UINT32 sleep_time); +DPP_STATUS dpp_pbu_ind_cmd_reg_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 mem_addr, + ZXIC_UINT32 mem_id, + ZXIC_UINT32 wrt_rd_flag); +DPP_STATUS dpp_pbu_ind_data_reg_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 len, + ZXIC_UINT32 *p_data, + ZXIC_UINT32 data_reg_base); +DPP_STATUS dpp_pbu_ind_data_reg_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 len, + ZXIC_UINT32 *p_data, + ZXIC_UINT32 data_reg_base); +DPP_STATUS dpp_pbu_cfg_ind_wrt(ZXIC_UINT32 dev_id, + ZXIC_UINT32 mem_addr, + DPP_PBU_CFG_IND_MEM_ID_E mem_id, + ZXIC_UINT32 len, + ZXIC_UINT32 *p_data); +DPP_STATUS dpp_pbu_cfg_ind_rd(ZXIC_UINT32 dev_id, + ZXIC_UINT32 mem_addr, + DPP_PBU_CFG_IND_MEM_ID_E mem_id, + ZXIC_UINT32 len, + ZXIC_UINT32 *p_data); +#endif +DPP_STATUS dpp_pbu_port_th_get(DPP_DEV_T *dev, + ZXIC_UINT32 port_id, + DPP_PBU_PORT_TH_PARA_T *p_para); +DPP_STATUS dpp_pbu_port_cos_th_get(DPP_DEV_T *dev, + ZXIC_UINT32 port_id, + DPP_PBU_PORT_COS_TH_PARA_T *p_para); +#if 0 +DPP_STATUS dpp_pbu_cnt_clr_all(ZXIC_UINT32 dev_id); +DPP_STATUS dpp_pbu_int_flag_prt(ZXIC_UINT32 dev_id); +DPP_STATUS dpp_pbu_stat_cnt_para_get(ZXIC_UINT32 dev_id, + DPP_PBU_CNT_PARA_T *p_para); +DPP_STATUS dpp_pbu_stat_thram_init_done_check(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *p_rdy); +DPP_STATUS dpp_pbu_stat_fptr_init_done_check(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *p_rdy); +DPP_STATUS dpp_pbu_fc_rdy_get(ZXIC_UINT32 dev_id, + DPP_NPPU_PBU_STAT_PBU_FC_RDY_T* p_pbu_module_fc); +DPP_STATUS dpp_pbu_lif_fc_rdy_get(ZXIC_UINT32 dev_id, + DPP_NPPU_PBU_STAT_PBU_LIF_GROUP0_RDY0_T* p_pbu_group0_rdy0); +DPP_STATUS dpp_pbu_lif_pfc_rdy_get(ZXIC_UINT32 dev_id, DPP_PBU_LIF_GROUP_PFC_RDY *p_lif_group0_pfc_rdy); +DPP_STATUS dpp_pbu_pktrx_mr_pfc_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_pbu_pktrx_mr_pfc); +DPP_STATUS dpp_pbu_stat_reg_mode_status_check(ZXIC_UINT32 dev_id, ZXIC_UINT32 sub_module_ind_status_reg, ZXIC_UINT32 sleep_time); +DPP_STATUS dpp_pbu_stat_ind_cmd_reg_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 mem_addr, + ZXIC_UINT32 mem_id, + ZXIC_UINT32 wrt_rd_flag); +DPP_STATUS dpp_pbu_stat_ind_data_reg_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 len, + ZXIC_UINT32 *p_data); +DPP_STATUS dpp_pbu_stat_ind_data_reg_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 len, + ZXIC_UINT32 *p_data); +DPP_STATUS dpp_pbu_stat_ind_wrt(ZXIC_UINT32 dev_id, + ZXIC_UINT32 mem_addr, + DPP_PBU_STAT_IND_MEM_ID_E mem_id, + ZXIC_UINT32 len, + ZXIC_UINT32 *p_data); +DPP_STATUS dpp_pbu_stat_ind_rd(ZXIC_UINT32 dev_id, + ZXIC_UINT32 mem_addr, + DPP_PBU_STAT_IND_MEM_ID_E mem_id, + ZXIC_UINT32 len, + ZXIC_UINT32 *p_data); +DPP_STATUS dpp_pbu_stat_port_ptr_cnt_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 port_id, + DPP_PBU_PORT_PTR_CNT_T *p_port_ptr_cnt); +DPP_STATUS dpp_pbu_stat_ifb_req_vld_cnt_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *p_cnt); +DPP_STATUS dpp_pbu_stat_ifb_rsp_vld_cnt_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *p_cnt); +DPP_STATUS dpp_pbu_stat_odma_recy_ptr_cnt_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *p_cnt); +DPP_STATUS dpp_pbu_stat_mcode_pf_req_cnt_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *p_cnt); +DPP_STATUS dpp_pbu_stat_mcode_pf_rsp_cnt_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *p_cnt); +DPP_STATUS dpp_pbu_stat_logic_pf_req_cnt_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *p_cnt); +DPP_STATUS dpp_pbu_stat_logic_pf_rsp_cnt_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *p_cnt); +DPP_STATUS dpp_pbu_stat_ppu_use_ptr_pulse_cnt_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *p_cnt); +DPP_STATUS dpp_pbu_stat_ppu_wb_vld_cnt_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *p_cnt); +DPP_STATUS dpp_pbu_stat_ppu_reorder_para_cnt_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *p_cnt); +DPP_STATUS dpp_pbu_stat_se_dpi_key_vld_cnt_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *p_cnt); +DPP_STATUS dpp_pbu_stat_se_dpi_rsp_vld_cnt_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *p_cnt); +DPP_STATUS dpp_pbu_stat_odma_ifb_rd1_cnt_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *p_cnt); +DPP_STATUS dpp_pbu_stat_odma_ifb_rd2_cnt_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *p_cnt); +DPP_STATUS dpp_pbu_stat_mcode_pf_no_rsp_cnt_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *p_cnt); +DPP_STATUS dpp_pbu_stat_logic_pf_no_rsp_cnt_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *p_cnt); +DPP_STATUS dpp_pbu_stat_ifb_data_get(ZXIC_UINT32 dev_id, + DPP_PBU_IFB_DATA_T *p_data); +DPP_STATUS dpp_pbu_stat_port_public_ptr_cnt_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 port_no, + ZXIC_UINT32 *p_cnt); +DPP_STATUS dpp_idma_cfg_cnt_ovfl_mode_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 mode); +DPP_STATUS dpp_idma_cfg_cnt_ovfl_mode_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *p_mode); +DPP_STATUS dpp_idma_cfg_cnt_rdclr_mode_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 mode); +DPP_STATUS dpp_idma_cfg_cnt_rdclr_mode_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *p_mode); +DPP_STATUS dpp_idma_stat_ind_reg_mode_status_check(ZXIC_UINT32 dev_id, ZXIC_UINT32 sub_module_ind_status_reg, ZXIC_UINT32 sleep_time); +DPP_STATUS dpp_idma_stat_ind_cmd_reg_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 mem_addr, + ZXIC_UINT32 mem_id, + ZXIC_UINT32 wrt_rd_flag); +DPP_STATUS dpp_idma_stat_ind_data_reg_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *p_data); +DPP_STATUS dpp_idma_stat_ind_data_reg_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *p_data); +DPP_STATUS dpp_idma_stat_ind_wrt(ZXIC_UINT32 dev_id, + ZXIC_UINT32 mem_addr, + DPP_IDMA_STAT_IND_MEM_ID_E mem_id, + ZXIC_UINT32 *p_data); +DPP_STATUS dpp_idma_stat_ind_rd(ZXIC_UINT32 dev_id, + ZXIC_UINT32 mem_addr, + DPP_IDMA_STAT_IND_MEM_ID_E mem_id, + ZXIC_UINT32 *p_data); +DPP_STATUS dpp_idma_stat_to_isu_total_cnt_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *p_cnt); +DPP_STATUS dpp_idma_stat_to_isu_err_total_cnt_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *p_cnt); +DPP_STATUS dpp_idma_stat_disc_total_cnt_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *p_cnt); +DPP_STATUS dpp_idma_stat_port_to_isu_cnt_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 port_no, + ZXIC_UINT32 *p_cnt); +DPP_STATUS dpp_idma_stat_port_to_isu_err_cnt_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 port_no, + ZXIC_UINT32 *p_cnt); +DPP_STATUS dpp_idma_stat_port_disc_cnt_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 port_no, + ZXIC_UINT32 *p_cnt); +DPP_STATUS dpp_pbu_cap_data_mode_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 mod_data); +DPP_STATUS dpp_pbu_pkt_capture_start(ZXIC_UINT32 dev_id, ZXIC_UINT32 pkt_num); +DPP_STATUS dpp_pbu_pkt_capture_stop(ZXIC_UINT32 dev_id); +DPP_STATUS dpp_pbu_pkt_capture_mode_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 mode); +DPP_STATUS dpp_pbu_pkt_capture_cnt(ZXIC_UINT32 dev_id, ZXIC_UINT32* pkt_num); +DPP_STATUS dpp_pbu_pkt_capture_dbg_print(ZXIC_UINT32 dev_id); +DPP_STATUS dpp_pbu_pkt_capture_cnt_print(ZXIC_UINT32 dev_id); +DPP_STATUS dpp_pbu_pkt_capture_print_one(ZXIC_UINT32 dev_id, ZXIC_UINT32 pkt_no); +DPP_STATUS dpp_pbu_pkt_capture_print(ZXIC_UINT32 dev_id, + ZXIC_UINT32 pkt_start_no, + ZXIC_UINT32 pkt_end_no); +DPP_STATUS dpp_pbu_pkt_capture_print_all(ZXIC_UINT32 dev_id); +DPP_STATUS dpp_pbu_pkt_capture_filter_set_bit(ZXIC_UINT32 dev_id, + ZXIC_UINT32 bit_no, + ZXIC_UINT32 filter_mode + ); +DPP_STATUS dpp_pbu_pkt_capture_filter_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 bit_start_no, + ZXIC_UINT32 bit_end_no, + ZXIC_UINT32 filter_mode); +DPP_STATUS dpp_pbu_pkt_capture_filter_mask_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 start, ZXIC_UINT32 end, ZXIC_UINT32 mask, ZXIC_UINT32 data); +DPP_STATUS dpp_pbu_pkt_capture_filter_pkt_mask_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 start, ZXIC_UINT32 end, ZXIC_UINT32 mask, ZXIC_UINT32 data); +DPP_STATUS dpp_pbu_pkt_capture_filter_sport_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 port); +DPP_STATUS dpp_pbu_pkt_capture_filter_dport_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 port); +DPP_STATUS dpp_pbu_pkt_capture_filter_clr_bit(ZXIC_UINT32 dev_id, + ZXIC_UINT32 bit_no); +DPP_STATUS dpp_pbu_pkt_capture_filter_clr(ZXIC_UINT32 dev_id, + ZXIC_UINT32 bit_start_no, + ZXIC_UINT32 bit_end_no); +DPP_STATUS dpp_pbu_pkt_capture_filter_clr_all(ZXIC_UINT32 dev_id); +/***********************************************************/ +/** 抓包报文分片打印by mf bit +* @param dev_id 芯片ID +* @param pkt_no 要打印的分片号 +* +* @return +* @remark 无 +* @see +* @author czd @date 2015/04/29 +************************************************************/ +DPP_STATUS dpp_pbu_pkt_capture_print_one_mf_by_bit(ZXIC_UINT32 dev_id, ZXIC_UINT32 pkt_no); + +DPP_STATUS dpp_pbu_glb_mgr_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *p_flag, + ZXIC_UINT32 *p_size, + ZXIC_UINT8 **pp_data_buff); +DPP_STATUS dpp_pbu_glb_mgr_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 size, + ZXIC_UINT8 *p_data_buff); +DPP_STATUS dpp_pbu_glb_size_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *p_size); + +ZXIC_UINT32 sim_soc_mf_field_print(ZXIC_UINT8 *pkt_buff); + + +DPP_STATUS dpp_pbu_pkt_capture_print_mf_by_bit(ZXIC_UINT32 dev_id, + ZXIC_UINT32 pkt_start_no, + ZXIC_UINT32 pkt_end_no); +DPP_STATUS dpp_pbu_pkt_capture_print_one_simple_mf_by_bit(ZXIC_UINT32 dev_id, ZXIC_UINT32 pkt_no); + +DPP_STATUS dpp_pbu_pkt_capture_print_all_mf_by_bit(ZXIC_UINT32 dev_id); + +#endif + +/****************************************************************************** + * END: 函数声明 * + *****************************************************************************/ +#endif + +#endif /* _DPP_PBU_H_ */ +/* 必须有个空行，否则可能编不过 */ + + + diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/ppu/dpp_ppu.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/ppu/dpp_ppu.h new file mode 100755 index 0000000..3a07989 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/ppu/dpp_ppu.h @@ -0,0 +1,104 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_ppu.h +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : 王春雷 +* 完成日期 : 2014/03/18 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ + +#ifndef _DPP_PPU_H_ +#define _DPP_PPU_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "dpp_module.h" +#include "dpp_ppu_api.h" +#include "dpp_ppu_reg.h" +#include "zxic_comm_thread.h" + +#define PPU_CLS_ME_NUM (8) +#define PPU_INSTR_MEM_NUM (3) /*ppu中的微码指令空间数量 2个cluster 共用一个指令空间*/ +#define PPU_INSTR_REG_NUM (4) /*ppu中指令空间中的数据寄存器数目*/ +#define PPU_INSTR_NUM_MAX (32*1024) /* xjw mod at 18.6.2 from 16k to 32k */ +#define PPU_SDT_IDX_MIN (0) +#define PPU_SDT_IDX_MAX (255) +#define PPU_DUP_IDX_MIN (0) +#define PPU_DUP_IDX_MAX (63) +#define PPU_INSTR_COL_MAX (4) + +/** ME指令调试中断*/ +#define PPU_ME0_INT_BT_START (0) +#define PPU_ME0_INT_BT_LEN (1) +#define PPU_ME1_INT_BT_START (1) +#define PPU_ME1_INT_BT_LEN (1) +#define PPU_ME2_INT_BT_START (2) +#define PPU_ME2_INT_BT_LEN (1) +#define PPU_ME3_INT_BT_START (3) +#define PPU_ME3_INT_BT_LEN (1) +#define PPU_ME4_INT_BT_START (4) +#define PPU_ME4_INT_BT_LEN (1) +#define PPU_ME5_INT_BT_START (5) +#define PPU_ME5_INT_BT_LEN (1) +#define PPU_ME6_INT_BT_START (6) +#define PPU_ME6_INT_BT_LEN (1) +#define PPU_ME7_INT_BT_START (7) +#define PPU_ME7_INT_BT_LEN (1) + +#define DPP_FPGA_MAX_FLOWTCAM_NUM (32) +#define DPP_PPU_CLS_0_BIT_MAP (1<<0) /*bit0 = 1 代表cluster0 启动*/ +#define DPP_PPU_CLS_1_BIT_MAP (1<<1) /*bit1 = 1 代表cluster1 启动*/ +#define DPP_PPU_CLS_2_BIT_MAP (1<<2) /*bit2 = 1 代表cluster2 启动*/ +#define DPP_PPU_CLS_3_BIT_MAP (1<<3) /*bit3 = 1 代表cluster3 启动*/ +#define DPP_PPU_CLS_4_BIT_MAP (1<<4) /*bit4 = 1 代表cluster4 启动*/ +#define DPP_PPU_CLS_5_BIT_MAP (1<<5) /*bit5 = 1 代表cluster5 启动*/ + +#define DPP_PPU_CLS_ALL_START (0x3F) /*打开所有cluster*/ + +/*该结构在ppu初始化的时候生成 全局不可修改*/ +typedef struct dpp_ppu_cls_bitmap_t +{ + ZXIC_UINT32 cls_use[DPP_PPU_CLUSTER_NUM]; /*记录配置生效的 cluster 由bitmap解析获得*/ + ZXIC_UINT32 instr_mem[PPU_INSTR_MEM_NUM]; /*记录配置生效的 指令空间索引号, 每两个cluster 共享一个指令空间*/ +} DPP_PPU_CLS_BITMAP_T; + +typedef struct dpp_ppu_ppu_cop_thash_rsk_t +{ + ZXIC_UINT32 rsk_319_288; + ZXIC_UINT32 rsk_287_256; + ZXIC_UINT32 rsk_255_224; + ZXIC_UINT32 rsk_223_192; + ZXIC_UINT32 rsk_191_160; + ZXIC_UINT32 rsk_159_128; + ZXIC_UINT32 rsk_127_096; + ZXIC_UINT32 rsk_095_064; + ZXIC_UINT32 rsk_063_032; + ZXIC_UINT32 rsk_031_000; + +} DPP_PPU_PPU_COP_THASH_RSK_T; + +ZXIC_UINT32 dpp_ppu_cls_use_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 cluster_id, ZXIC_UINT32 flag); +ZXIC_UINT32 dpp_ppu_cls_use_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 cluster_id); +ZXIC_UINT32 dpp_ppu_instr_mem_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 mem_id, ZXIC_UINT32 flag); +ZXIC_UINT32 dpp_ppu_parse_cls_bitmap(ZXIC_UINT32 dev_id, ZXIC_UINT32 bitmap); + +DPP_STATUS dpp_ppu_ppu_cop_thash_rsk_set(DPP_DEV_T *dev, DPP_PPU_PPU_COP_THASH_RSK_T *p_para); +DPP_STATUS dpp_ppu_ppu_cop_thash_rsk_get(DPP_DEV_T *dev, DPP_PPU_PPU_COP_THASH_RSK_T *p_ppu_cop_thash_rsk); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/se/dpp_apt_se.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/se/dpp_apt_se.h new file mode 100755 index 0000000..cf59470 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/se/dpp_apt_se.h @@ -0,0 +1,111 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_apt_se.h +* 文件标识 : +* 内容摘要 : SE适配业务接口数据结构和函数声明 +* 其它说明 : +* 当前版本 : +* 作 者 : chenqin00181032 +* 完成日期 : 2022/02/22 +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ + +#ifndef _DPP_APT_SE_H_ +#define _DPP_APT_SE_H_ + +#include "dpp_apt_se_api.h" + +#define SDT_OPER_ADD (ZXIC_UINT32)(0) +#define SDT_OPER_DEL (ZXIC_UINT32)(1) + +#define SDT_DDR_RW_128BIT (ZXIC_UINT32)(0) +#define SDT_DDR_RW_256BIT (ZXIC_UINT32)(1) +#define SDT_DDR_RW_512BIT (ZXIC_UINT32)(2) + +#define DDR_128BIT_BYTE (ZXIC_UINT32)(16) + +#define ERAM_ENTRY_SOFT_MAX (ZXIC_UINT32)(16) /*eram最大位宽128bit*/ +#define HASH_ENTRY_SOFT_MAX (ZXIC_UINT32)(64) /*hash最大位宽512bit*/ +#define ACL_ENTRY_SOFT_MAX (ZXIC_UINT32)(160) /*acl最大位宽640bit key+640bit mask*/ + +typedef struct se_apt_eram_func_t +{ + ZXIC_UINT32 opr_mode; /**cpu读写位宽模式DPP_ERAM128_OPR_MODE_E 0:128b 1:64b 2:1b 3:32b <@*/ + ZXIC_UINT32 rd_mode; /*读清模式DPP_ERAM128_RD_CLR_MODE_E，0:正常读 1:读清模式*/ + DPP_APT_ERAM_SET_FUNC eram_set_func; + DPP_APT_ERAM_GET_FUNC eram_get_func; +}SE_APT_ERAM_FUNC_T; + +typedef struct se_apt_ddr_func_t +{ + ZXIC_UINT32 ddr_tbl_depth; /*ddr表项深度，单位与ddr读写模式一致*/ + DPP_APT_DDR_SET_FUNC ddr_set_func; + DPP_APT_DDR_GET_FUNC ddr_get_func; +}SE_APT_DDR_FUNC_T; + +typedef struct se_apt_acl_func_t +{ + DPP_APT_ACL_ENTRY_SET_FUNC acl_set_func; + DPP_APT_ACL_ENTRY_GET_FUNC acl_get_func; +}SE_APT_ACL_FUNC_T; + +typedef struct se_apt_hash_func_t +{ + DPP_APT_HASH_ENTRY_SET_FUNC hash_set_func; + DPP_APT_HASH_ENTRY_GET_FUNC hash_get_func; +}SE_APT_HASH_FUNC_T; + +typedef struct se_apt_lpm_func_t +{ + DPP_APT_LPM_ENTRY_SET_FUNC lpm_set_func; + DPP_APT_LPM_ENTRY_GET_FUNC lpm_get_func; +}SE_APT_LPM_FUNC_T; +typedef struct se_apt_callback_t +{ + ZXIC_UINT32 sdtNo; /** <@brief sdt no 0~255 */ + ZXIC_UINT32 table_type; /** <@brief 查找表项类型 */ + + union + { + SE_APT_ERAM_FUNC_T eramFunc; + SE_APT_DDR_FUNC_T ddrFunc; + SE_APT_ACL_FUNC_T aclFunc; + SE_APT_HASH_FUNC_T hashFunc; + SE_APT_LPM_FUNC_T lpmFunc; + }se_func_info; +}SE_APT_CALLBACK_T; + +typedef struct se_apt_eram_soft_t +{ + ZXIC_UINT32 index; + ZXIC_UINT32 buff[ERAM_ENTRY_SOFT_MAX/4]; +}SE_APT_ERAM_SOFT_T; + +typedef struct se_apt_eram_hash_t +{ + ZXIC_UINT32 index; + ZXIC_UINT8 aucData[HASH_ENTRY_SOFT_MAX]; +}SE_APT_HASH_SOFT_T; + +typedef struct se_apt_eram_acl_t +{ + ZXIC_UINT32 index; + ZXIC_UINT8 aucData[ACL_ENTRY_SOFT_MAX]; +}SE_APT_ACL_SOFT_T; + +ZXIC_SINT32 dpp_apt_table_key_cmp(void *p_new_key, void *p_old_key, ZXIC_UINT32 key_len); +SE_APT_CALLBACK_T *dpp_apt_get_func(ZXIC_UINT32 dev_id,ZXIC_UINT32 sdt_no); +DPP_STATUS dpp_apt_set_callback(ZXIC_UINT32 dev_id, ZXIC_UINT32 sdt_no, ZXIC_UINT32 table_type,ZXIC_VOID *pData); +DPP_STATUS dpp_apt_sw_list_insert(ZXIC_RB_CFG *rb_cfg,void *pData,ZXIC_UINT32 len); +DPP_STATUS dpp_apt_sw_list_search(ZXIC_RB_CFG *rb_cfg,void *pData,ZXIC_UINT32 len); +DPP_STATUS dpp_apt_sw_list_delete(ZXIC_RB_CFG *rb_cfg,void *pData,ZXIC_UINT32 len); +DPP_STATUS dpp_apt_get_zblock_index(ZXIC_UINT32 zblock_bitmap,ZXIC_UINT32 *zblk_idx); +DPP_STATUS dpp_apt_dtb_res_init(DPP_DEV_T *dev); +DPP_STATUS dpp_apt_se_callback_init(ZXIC_UINT32 dev_id); +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/se/dpp_etcam.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/se/dpp_etcam.h new file mode 100755 index 0000000..588b815 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/se/dpp_etcam.h @@ -0,0 +1,157 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_etcam.h +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : 王春雷 +* 完成日期 : 2014/04/03 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ + +#ifndef _DPP_ETCAM_H_ +#define _DPP_ETCAM_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#define DPP_ETCAM_BLOCK_NUM (8) /* eTcam中Block的数目 16:dpp+的etcam block 数目 */ +#define DPP_ETCAM_TBLID_NUM (8) /* eTcam支持的业务表号 */ +#define DPP_ETCAM_RAM_NUM (8) /* Block内部RAM的个数 */ +#define DPP_ETCAM_RAM_WIDTH (80U) /* Block内部单个RAM的宽度，比特为单位 */ + +#ifdef DPP_FPGA_TEST_BAORD_SA500FT +#define DPP_ETCAM_RAM_DEPTH (16U) /* Block内部单个RAM的深度 */ +#else +#define DPP_ETCAM_RAM_DEPTH (512U) /* Block内部单个RAM的深度 */ +#endif + +#define DPP_ETCAM_WR_MASK_MAX (((ZXIC_UINT32)1<> 12) +#define DPP_SMMU1_TOTAL_BANK_NUM (8) +#define DPP_SMMU1_TOTAL_MAX_ADDR (0xffffffff) +#define DPP_SMMU1_TOTAL_MAX_BADDR (DPP_SMMU1_TOTAL_MAX_ADDR >> 12) +#define DPP_SMMU1_BADDR_MASK (0x7ffff800) +#define DPP_SMMU1_DDR_GROUP_NUM (1) +#define DPP_SMMU1_BANK_COPY_MAX_NUM (16) +#define DPP_SMMU1_READ_REG_MAX_NUM (16) +#define DPP_DIR_TBL_BUF_MAX_NUM (DPP_SMMU1_READ_REG_MAX_NUM) + +/*hash ext crc cfg*/ +#define HASH_ECC_EN_BT_START (2) +#define HASH_ECC_EN_BT_WIDTH (1) +#define HASH_BANK_COPY_BT_START (3) +#define HASH_BANK_COPY_BT_WIDTH (3) +#define HASH_BASE_ADDR_BT_START (6) +#define HASH_BASE_ADDR_BT_WIDTH (15) +/*hash learn tbl cfg*/ +#define LEARN_HASH_TBL_BT_START (0) +#define LEARN_HASH_TBL_BT_WIDTH (19) + +#define DPP_SMMU0_MCAST_TBL_MAX_GROUP (0xffff) + +#define DPP_SMMU0_CAR0_MONO_POS (0) +#define DPP_SMMU0_CAR0_MONO_LEN (1) +#define DPP_SMMU0_CAR0_EN_POS (1) +#define DPP_SMMU0_CAR0_EN_LEN (1) +#define DPP_SMMU0_CAR1_MONO_POS (2) +#define DPP_SMMU0_CAR1_MONO_LEN (1) +#define DPP_SMMU0_CAR1_EN_POS (3) +#define DPP_SMMU0_CAR1_EN_LEN (1) + +#define DPP_SMMU0_LPM_AS_TBL_ID_MAX (7) +#define DPP_SMMU0_LPM_AS_TBL_ID_NUM (8) + +#define DPP_SMMU0_MCAST_DATA_VLD_POS (16) +#define DPP_SMMU0_MCAST_DATA_VLD_LEN (1) +#define DPP_SMMU0_MCAST_CNT_POS (0) +#define DPP_SMMU0_MCAST_CNT_LEN (16) + +#define DPP_SMMU0_INDIER_RDWR_OFFSET_NUM (4) +#define DPP_SMMU0_READ_REG_MAX_NUM (4) + +/** SMMU0 调度 fifo ecc 使能标志 */ +#define DPP_SMMU0_PPU_FIFO_POS (12) +#define DPP_SMMU0_PPU_FIFO_LEN (8) +#define DPP_SMMU0_STAT_FIFO_POS (11) +#define DPP_SMMU0_STAT_FIFO_LEN (1) +#define DPP_SMMU0_DMA_FIFO_POS (10) +#define DPP_SMMU0_DMA_FIFO_LEN (1) +#define DPP_SMMU0_ODMA_FIFO_POS (6) +#define DPP_SMMU0_ODMA_FIFO_LEN (4) +#define DPP_SMMU0_MCAST_FIFO_POS (5) +#define DPP_SMMU0_MCAST_FIFO_LEN (1) +#define DPP_SMMU0_ETCAM_FIFO_POS (1) +#define DPP_SMMU0_ETCAM_FIFO_LEN (4) +#define DPP_SMMU0_LPM_FIFO_POS (0) +#define DPP_SMMU0_LPM_FIFO_LEN (1) + +#define DPP_SMMU0_CTRL_ECC_CFG_POS (0) +#define DPP_SMMU0_CTRL_ECC_CFG_LEN (3) + +#define DPP_SMMU0_RSCHD_RAM_POS (0) +#define DPP_SMMU0_RSCHD_RAM_LEN (1) + +#define DPP_SMMU0_ERAM_ECC_CFG_POS (0) +#define DPP_SMMU0_ERAM_ECC_CFG_LEN (24) + +#define DPP_SMMU0_WR_ARB_ECC_CFG_POS (0) +#define DPP_SMMU0_WR_ARB_ECC_CFG_LEN (1) + +/* smmu0 int0 reg bit define */ +#define SMMU0_INT0_DMA_ORDFIFO_START (0) +#define SMMU0_INT0_DMA_ORDFIFO_LEN (1) +#define SMMU0_INT0_ODMA_ORDFIFO_START (1) +#define SMMU0_INT0_ODMA_ORDFIFO_LEN (1) +#define SMMU0_INT0_MCAST_ORDFIFO_START (2) +#define SMMU0_INT0_MCAST_ORDFIFO_LEN (1) + +#define DPP_ERAM128_BADDR_MASK (0x3FFFF80)/* modified for dpp+ 25bit 2018-09-27*/ + +#define DPP_SE_SMMU1_MAX_BADDR_NO_SHARE ((1<<20)-1) +#define DPP_SE_SMMU1_MAX_BADDR_SHARE ((1<<13)-1) +#define DPP_SE_SMMU1_MAX_ADDR ((1<<30)-1) + +#define DPP_SE_SMMU1_BANK_NUM_POS (16) +#define DPP_SE_SMMU1_BANK_NUM_LEN (5) + +#define DPP_SE_SMMU1_SHARE_TYPE_POS (21) +#define DPP_SE_SMMU1_SHARE_TYPE_LEN (2) + +#define DPP_SE_SMMU1_RR_STATE_POS (0) +#define DPP_SE_SMMU1_RR_STATE_LEN (15) + +#define DPP_SE_CFG_PPU_INFO_POS (0) +#define DPP_SE_CFG_PPU_INFO_LEN (12) + +#define DPP_SE_CFG_DPI_FLAG_POS (12) +#define DPP_SE_CFG_DPI_FLAG_LEN (1) + +#define DPP_SE_CFG_WR_FLAG_POS (13) +#define DPP_SE_CFG_WR_FLAG_LEN (1) + + +/** 中断相关 */ +#define DPP_SE_ALG_SCHD_INT_NUM (14) +#define DPP_SE_ALG_ZBLK_ECC_INT_NUM (32) +#define DPP_SE_ALG_HASH0_INT_NUM (8) +#define DPP_SE_ALG_HASH1_INT_NUM (8) +#define DPP_SE_ALG_HASH2_INT_NUM (8) +#define DPP_SE_ALG_HASH3_INT_NUM (8) +#define DPP_SE_ALG_LPM_INT_NUM (10) + +#define DPP_SMMU0_CLS_NUM (6) +#define DPP_SMMU0_STAT_NUM (10) +#define DPP_SMMU0_AS_ETCAM_NUM (DPP_ETCAM_ID_NUM) +#define DPP_SMMU0_PLCR_NUM (1) +#define DPP_SMMU0_ERAM_BLOCK_NUM (32) + +#define DPP_SMMU1_SCH_CNT (4)/*sch 调度次数 完成6->4调度*/ +//#define DPP_SMMU1_GRP_CNT (DPP_SMMU1_DDR_GRP_NUM) +#define DPP_SMMU1_GRP_CNT (8) /*与reg n_size保持一�?*/ +#define DPP_SMMU1_DIR_CHANNEL_CNT (4) + +#define DPP_PARSE_MEX_CHANNEL_NUM (6) +#define DPP_PARSE_KSCHD_CHANNEL_NUM (6) +#define DPP_RSCHD_PPU_CHANNEL_NUM (6) + +typedef enum smmu1_stat_type_e +{ + STAT_TYPE_PPU = 0, + STAT_TYPE_OAM = 1, + STAT_TYPE_MAX, +}SMMU1_STAT_TYPE_E; + +typedef enum alg_lpm_type_e +{ + ALG_LPM_V4 = 1, + ALG_LPM_V6 = 2, + ALG_LPM_V4_AS = 3, + ALG_LPM_V6_AS = 4, + ALG_LPM_MAX +}ALG_LPM_TYPE_E; + +typedef enum se_ddr_bank_info_e +{ + SE_DDR_BKINFO_LPM4 = 0, + SE_DDR_BKINFO_LPM6 = 1, + SE_DDR_BKINFO_LPM4_AS = 2, + SE_DDR_BKINFO_LPM6_AS = 3, +}SE_DDR_BANK_INFO_E; + +typedef enum alg_zblk_serv_type_e +{ + ALG_ZBLK_SERV_LPM = 0, + ALG_ZBLK_SERV_HASH, +}ALG_ZBLK_SERV_TYPE_E; + +typedef enum cmmu_ddr3_bank_enable_e +{ + CMMU_DDR3_BANK_DISABLE = 0, + CMMU_DDR3_BANK_ENABLE, +}CMMU_DDR3_BANK_ENABLE_E; + +/** TM统计读片外位�? */ +typedef enum stat_tm_rd_ddr_mode_e +{ + STAT_TM_RD_DDR_MODE_128 = 0, + STAT_TM_RD_DDR_MODE_256 = 1, + STAT_TM_RD_DDR_MODE_512 = 2, + STAT_TM_RD_DDR_MODE_MAX, +}STAT_TM_RD_DDR_MODE_E; + +typedef enum stat_tm_rd_clr_mode_e +{ + STAT_TM_RD_CLR_MODE_UNCLR = 0, /**< @brief 正常读，读完数据不清�? */ + STAT_TM_RD_CLR_MODE_CLR = 1, /**< @brief 读清模式*/ + STAT_TM_RD_CLR_MODE_MAX, +}STAT_TM_RD_CLR_MODE_E; + +typedef enum se_ddr_map_flag_e +{ + VIR_TO_PHY_FLAG = 0, /**< @brief 虚拟地址/bank到物理地址/bank的映�? */ + PHY_TO_VIR_FLAG = 1, /**< @brief 物理地址/bank到虚拟地址/bank的映�? */ +}SE_DDR_MAP_FLAG_E; + +/** module se*/ +typedef enum module_init_se_e +{ + MODULE_INIT_SE_SMMU0 = 0, + MODULE_INIT_SE_SMMU1, + MODULE_INIT_SE_ALG, + MODULE_INIT_SE_AS, + MODULE_INIT_SE_ETCAM, + MODULE_INIT_SE_STAT, + MODULE_INIT_SE_FIFO, + MODULE_INIT_SE_MAX +} MODULE_INIT_SE_E; + +typedef struct smmu1_kschd_hash_ddr_cfg_t +{ + ZXIC_UINT32 baddr; + ZXIC_UINT32 crcen; + ZXIC_UINT32 mode; +}SMMU1_KSCHD_HASH_DDR_CFG_T; + +typedef struct smmu1_kschd_lpm_ddr_cfg_t +{ + ZXIC_UINT32 baddr; + ZXIC_UINT32 bankcopy; + ZXIC_UINT32 crcen; + ZXIC_UINT32 flag; /* 0-256, 1-384 */ + ZXIC_UINT32 as_baddr; + ZXIC_UINT32 as_bankcopy; + ZXIC_UINT32 as_crcen; + ZXIC_UINT32 as_mode; +}SMMU1_KSCHD_LPM_DDR_CFG_T; + +typedef struct dpp_lpm_as_eram_info_t +{ + ZXIC_UINT32 as_baddr; + ZXIC_UINT32 as_mode; +}DPP_LPM_AS_ERAM_INFO_T; + +typedef struct dpp_lpm_res_info_t +{ + DPP_LPM_AS_ERAM_INFO_T as_eram_info[DPP_SMMU0_LPM_AS_TBL_ID_NUM]; + ZXIC_UINT32 v4_ddr_baddr; + ZXIC_UINT32 v4_as_ddr_baddr; + ZXIC_UINT32 v4_as_rsp_len; + ZXIC_UINT32 v6_ddr_baddr; + ZXIC_UINT32 v6_as_ddr_baddr; + ZXIC_UINT32 v6_as_rsp_len; +}DPP_LPM_RES_INFO_T; + +/*--------------------------------------------------------调试打印计数--------------------------------------------------------*/ + +/*smmu0 调试打印计数 开�?*/ +typedef struct dpp_smmu0_dbg_cnt_t +{ + ZXIC_UINT32 smmu0_rcv_as_age_req_cnt; + ZXIC_UINT32 smmu0_rcv_parse_req_cnt; + ZXIC_UINT32 smmu0_cpu_ind_rd_rsp_cnt; + ZXIC_UINT32 smmu0_cpu_ind_rd_req_cnt; + ZXIC_UINT32 smmu0_cpu_ind_wr_req_cnt; + + ZXIC_UINT32 smmu0_to_plcr_rsp_cnt[DPP_SMMU0_PLCR_NUM]; + ZXIC_UINT32 smmu0_rcv_plcr_req_cnt[DPP_SMMU0_PLCR_NUM]; + + ZXIC_UINT32 smmu0_to_lpm_as_rsp_cnt; + ZXIC_UINT32 smmu0_rcv_lpm_as_req_cnt; + + ZXIC_UINT32 smmu0_to_as_etacm_rsp_cnt[DPP_SMMU0_AS_ETCAM_NUM];/* 与fc是反�? */ + ZXIC_UINT32 smmu0_rcv_as_etacm_req_cnt[DPP_SMMU0_AS_ETCAM_NUM]; + + ZXIC_UINT32 smmu0_to_ppu_mc_rsp_cnt; + ZXIC_UINT32 smmu0_rcv_ppu_mc_req_cnt; + ZXIC_UINT32 smmu0_to_odma_tdm_mc_rsp_cnt; + ZXIC_UINT32 smmu0_rcv_odma_tdm_mc_req_cnt; + ZXIC_UINT32 smmu0_to_odma_rsp_cnt; + ZXIC_UINT32 smmu0_rcv_odma_req_cnt; + ZXIC_UINT32 smmu0_to_dma_rsp_cnt; + ZXIC_UINT32 smmu0_rcv_dma_req_cnt; + + ZXIC_UINT32 smmu0_to_stat_rsp_cnt[DPP_SMMU0_STAT_NUM]; + ZXIC_UINT32 smmu0_rcv_stat_req_cnt[DPP_SMMU0_STAT_NUM]; + ZXIC_UINT32 smmu0_to_ppu_rsp_cnt[DPP_SMMU0_CLS_NUM]; + ZXIC_UINT32 smmu0_rcv_ppu_req_cnt[DPP_SMMU0_CLS_NUM]; + + ZXIC_UINT32 smmu0_rcv_ftm_stat_req0_cnt; + ZXIC_UINT32 smmu0_rcv_ftm_stat_req1_cnt; + ZXIC_UINT32 smmu0_rcv_etm_stat_req0_cnt; + ZXIC_UINT32 smmu0_rcv_etm_stat_req1_cnt; + + ZXIC_UINT32 smmu0_block_rd_cnt[DPP_SMMU0_ERAM_BLOCK_NUM]; + ZXIC_UINT32 smmu0_block_wr_cnt[DPP_SMMU0_ERAM_BLOCK_NUM]; + +}DPP_SMMU0_DBG_CNT_T; + +typedef struct dpp_smmu0_dbg_fc_cnt_t +{ + ZXIC_UINT32 smmu0_to_as_age_req_fc_cnt; + ZXIC_UINT32 smmu0_to_parse_req_fc_cnt; + ZXIC_UINT32 smmu0_rcv_wr_arb_cpu_fc_cnt; + ZXIC_UINT32 smmu0_to_as_lpm_req_fc_cnt; + ZXIC_UINT32 smmu0_rcv_as_lpm_rsp_fc_cnt; + ZXIC_UINT32 smmu0_to_as_etacm_req_fc_cnt[DPP_SMMU0_AS_ETCAM_NUM]; + ZXIC_UINT32 smmu0_rcv_as_etacm_rsp_fc_cnt[DPP_SMMU0_AS_ETCAM_NUM]; + ZXIC_UINT32 smmu0_to_ppu_mc_req_fc_cnt; + ZXIC_UINT32 smmu0_rcv_ppu_mc_rsp_fc_cnt; + ZXIC_UINT32 smmu0_rcv_odma_tdm_mc_rsp_fc_cnt; + ZXIC_UINT32 smmu0_to_odma_tdm_mc_req_fc_cnt; + ZXIC_UINT32 smmu0_to_odma_req_fc_cnt; + ZXIC_UINT32 smmu0_to_dma_req_fc_cnt; + ZXIC_UINT32 smmu0_to_stat_req_fc_cnt[DPP_SMMU0_STAT_NUM]; + ZXIC_UINT32 smmu0_rcv_stat_rsp_fc_cnt[DPP_SMMU0_STAT_NUM]; + ZXIC_UINT32 smmu0_to_ppu_req_fc_cnt[DPP_SMMU0_CLS_NUM]; + ZXIC_UINT32 smmu0_rcv_ppu_rsp_fc_cnt[DPP_SMMU0_CLS_NUM]; +}DPP_SMMU0_DBG_FC_CNT_T; +/*smmu0 调试打印计数 结束*/ + +/*smmu1 计数�?*/ +typedef struct dpp_smmu1_dbg_cnt_t +{ + ZXIC_UINT32 ctrl_to_cash_fc_cnt[DPP_SMMU1_GRP_CNT]; + ZXIC_UINT32 cash_to_ctrl_req_cnt[DPP_SMMU1_GRP_CNT]; + ZXIC_UINT32 rschd_to_cache_fc_cnt[DPP_SMMU1_GRP_CNT]; + ZXIC_UINT32 cash_to_cache_rsp_cnt[DPP_SMMU1_GRP_CNT]; + ZXIC_UINT32 cash_to_ctrl_fc_cnt[DPP_SMMU1_GRP_CNT]; + ZXIC_UINT32 ctrl_to_cash_rsp_cnt[DPP_SMMU1_GRP_CNT]; + ZXIC_UINT32 kschd_to_cache_req_cnt[DPP_SMMU1_GRP_CNT]; + ZXIC_UINT32 cache_to_kschd_fc_cnt[DPP_SMMU1_GRP_CNT]; + ZXIC_UINT32 dma_to_smmu1_rd_req_cnt; + ZXIC_UINT32 oam_to_kschd_req_cnt; + ZXIC_UINT32 oam_rr_state_rsp_cnt; + ZXIC_UINT32 oam_clash_info_cnt; + ZXIC_UINT32 oam_to_rr_req_cnt; + ZXIC_UINT32 lpm_as_to_kschd_req_cnt; + ZXIC_UINT32 lpm_as_rr_state_rsp_cnt; + ZXIC_UINT32 lpm_as_clash_info_cnt; + ZXIC_UINT32 lpm_as_to_rr_req_cnt; + ZXIC_UINT32 lpm_to_kschd_req_cnt; + ZXIC_UINT32 lpm_rr_state_rsp_cnt; + ZXIC_UINT32 lpm_clash_info_cnt; + ZXIC_UINT32 lpm_to_rr_req_cnt; + ZXIC_UINT32 hash_to_kschd_req_cnt[DPP_HASH_ID_NUM]; + ZXIC_UINT32 hash_rr_state_rsp_cnt[DPP_HASH_ID_NUM]; + ZXIC_UINT32 hash_clash_info_cnt[DPP_HASH_ID_NUM]; + ZXIC_UINT32 hash_to_rr_req_cnt[DPP_HASH_ID_NUM]; + ZXIC_UINT32 dir_to_kschd_req_cnt[DPP_SMMU1_DIR_CHANNEL_CNT]; + ZXIC_UINT32 dir_clash_info_cnt[DPP_SMMU1_DIR_CHANNEL_CNT]; + ZXIC_UINT32 dir_tbl_wr_req_cnt; + ZXIC_UINT32 warbi_to_dir_tbl_warbi_fc_cnt; + ZXIC_UINT32 dir_to_bank_rr_req_cnt[DPP_SMMU1_DIR_CHANNEL_CNT]; + ZXIC_UINT32 kschd_to_dir_fc_cnt[DPP_SMMU1_DIR_CHANNEL_CNT]; + ZXIC_UINT32 dir_rr_state_rsp_cnt[DPP_SMMU1_DIR_CHANNEL_CNT]; + ZXIC_UINT32 wr_done_to_warbi_fc_cnt; + ZXIC_UINT32 wr_done_ptr_req_cnt; + ZXIC_UINT32 ctrl_to_warbi_fc_cnt[DPP_SMMU1_GRP_CNT]; + ZXIC_UINT32 warbi_to_ctrl_wr_req_cnt[DPP_SMMU1_GRP_CNT]; + ZXIC_UINT32 warbi_to_cash_wr_req_cnt[DPP_SMMU1_GRP_CNT]; + ZXIC_UINT32 warbi_to_cpu_wr_fc_cnt; + ZXIC_UINT32 cpu_wr_req_cnt; + ZXIC_UINT32 ctrl_to_cpu_rd_rsp_cnt[DPP_SMMU1_GRP_CNT]; + ZXIC_UINT32 cpu_to_ctrl_rd_req_cnt[DPP_SMMU1_GRP_CNT]; + ZXIC_UINT32 cpu_rd_dir_tbl_rsp_cnt; + ZXIC_UINT32 cpu_to_dir_tbl_rd_wr_req_cnt; + ZXIC_UINT32 smmu1_to_mmu_rsp_fc_cnt[DPP_SMMU1_GRP_CNT]; + ZXIC_UINT32 mmu_to_smmu1_rd_rsp_cnt[DPP_SMMU1_GRP_CNT]; + ZXIC_UINT32 mmu_to_smmu1_rd_fc_cnt[DPP_SMMU1_GRP_CNT]; + ZXIC_UINT32 smmu1_to_mmu_rd_req_cnt[DPP_SMMU1_GRP_CNT]; + ZXIC_UINT32 mmu_to_smmu1_wr_fc_cnt[DPP_SMMU1_GRP_CNT]; + ZXIC_UINT32 smmu1_to_mmu_wr_req_cnt[DPP_SMMU1_GRP_CNT]; + ZXIC_UINT32 se_to_smmu1_wr_rsp_fc_cnt; + ZXIC_UINT32 smmu1_to_se_wr_rsp_cnt; + ZXIC_UINT32 ddr_wr_rsp_cnt[DPP_SMMU1_GRP_CNT]; + ZXIC_UINT32 smmu1_to_as_fc_cnt; + ZXIC_UINT32 as_to_smmu1_wr_req_cnt; + ZXIC_UINT32 smmu1_to_se_parser_fc_cnt; + ZXIC_UINT32 se_parser_to_smmu1_req_cnt;/* 微码写ddr直接�? */ + ZXIC_UINT32 smmu1_to_etm_wr_fc_cnt; + ZXIC_UINT32 etm_wr_req_cnt; + ZXIC_UINT32 smmu1_to_ftm_wr_fc_cnt; + ZXIC_UINT32 ftm_wr_req_cnt; + ZXIC_UINT32 smmu1_to_state_wr_fc_cnt; + ZXIC_UINT32 state_wr_req_cnt; + ZXIC_UINT32 se_to_dma_rsp_cnt; + ZXIC_UINT32 se_to_dma_fc_cnt; + ZXIC_UINT32 oam_to_smmu1_fc_cnt; + ZXIC_UINT32 smmu1_to_oam_rsp_cnt; + ZXIC_UINT32 smmu1_to_oam_fc_cnt; + ZXIC_UINT32 oam_to_smmu1_req_cnt; + ZXIC_UINT32 smmu1_to_etm_rsp_cnt; + ZXIC_UINT32 smmu1_to_ftm_rsp_cnt; + ZXIC_UINT32 smmu1_to_etm_fc_cnt; + ZXIC_UINT32 etm_to_smmu1_req_cnt; + ZXIC_UINT32 smmu1_to_ftm_fc_cnt; + ZXIC_UINT32 ftm_to_smmu1_req_cnt; + ZXIC_UINT32 smmu1_to_stat_rsp_cnt; + ZXIC_UINT32 smmu1_to_stat_fc_cnt; + ZXIC_UINT32 stat_to_smmu1_req_cnt; /* cmmu */ + ZXIC_UINT32 lpm_as_to_smmu1_fc_cnt; + ZXIC_UINT32 lpm_to_smmu1_fc_cnt; + ZXIC_UINT32 smmu1_to_lpm_as_rsp_cnt; + ZXIC_UINT32 smmu1_to_lpm_rsp_cnt; + ZXIC_UINT32 smmu1_to_lpm_as_fc_cnt; + ZXIC_UINT32 smmu1_to_lpm_fc_cnt; + ZXIC_UINT32 lpm_as_to_smmu1_req_cnt; + ZXIC_UINT32 lpm_to_smmu1_req_cnt; + ZXIC_UINT32 hash_to_smmu1_fc_cnt[DPP_HASH_ID_NUM]; + ZXIC_UINT32 smmu1_to_hash_rsp_cnt[DPP_HASH_ID_NUM]; + ZXIC_UINT32 smmu1_to_hash_fc_cnt[DPP_HASH_ID_NUM]; + ZXIC_UINT32 hash_to_smmu1_cnt[DPP_HASH_ID_NUM]; + ZXIC_UINT32 se_to_smmu1_dir_rsp_fc_cnt[DPP_SMMU1_DIR_CHANNEL_CNT]; + ZXIC_UINT32 smmu1_to_se_dir_rsp_cnt[DPP_SMMU1_DIR_CHANNEL_CNT]; + ZXIC_UINT32 smmu1_to_se_dir_fc_cnt[DPP_SMMU1_DIR_CHANNEL_CNT]; + ZXIC_UINT32 se_to_smmu1_dir_cnt[DPP_SMMU1_DIR_CHANNEL_CNT]; + ZXIC_UINT32 cache_to_rschd_rsp_cnt[DPP_SMMU1_GRP_CNT]; +}DPP_SMMU1_DBG_CNT_T; + +/*parser 计数�?*/ +typedef struct se_parser_dbg_cnt_t +{ + ZXIC_UINT32 mex_req_cnt[DPP_PARSE_MEX_CHANNEL_NUM]; + ZXIC_UINT32 kschd_req_cnt[DPP_PARSE_KSCHD_CHANNEL_NUM]; + ZXIC_UINT32 kschd_parser_fc_cnt[DPP_PARSE_KSCHD_CHANNEL_NUM]; + ZXIC_UINT32 se_ppu_mex_fc_cnt[DPP_PARSE_MEX_CHANNEL_NUM]; + ZXIC_UINT32 smmu0_marc_fc_cnt; + ZXIC_UINT32 smmu0_marc_key_cnt; + ZXIC_UINT32 smmu1_key_cnt; + ZXIC_UINT32 smmu1_parser_fc_cnt; + ZXIC_UINT32 marc_tab_type_err_mex_cnt[DPP_PARSE_MEX_CHANNEL_NUM]; + ZXIC_UINT32 eram_fulladdr_drop_cnt; +}SE_PARSER_DBG_CNT_T; + +/*kschd 计数�?*/ +typedef struct se_kschd_dbg_cnt_t +{ + ZXIC_UINT32 parser_kschd_key_cnt[DPP_PARSE_KSCHD_CHANNEL_NUM]; + ZXIC_UINT32 kschd_smmu1_key_cnt[DPP_SMMU1_SCH_CNT]; + ZXIC_UINT32 kschd_to_as_hash0_key_cnt; + ZXIC_UINT32 kschd_to_as_hash1_key_cnt; + ZXIC_UINT32 kschd_to_as_hash2_key_cnt; + ZXIC_UINT32 kschd_to_as_hash3_key_cnt; + ZXIC_UINT32 kschd_to_as_lpm_key_cnt; + ZXIC_UINT32 kschd_to_as_etacm0_key_cnt; + ZXIC_UINT32 kschd_to_as_etacm1_key_cnt; + ZXIC_UINT32 kschd_to_as_pbu_key_cnt; + ZXIC_UINT32 kschd_to_parser_fc_cnt[DPP_PARSE_KSCHD_CHANNEL_NUM]; + ZXIC_UINT32 smmu1_kschd_fc_cnt[DPP_SMMU1_SCH_CNT]; + ZXIC_UINT32 kschd_rcv_as_hash0_fc_cnt; + ZXIC_UINT32 kschd_rcv_as_hash1_fc_cnt; + ZXIC_UINT32 kschd_rcv_as_hash2_fc_cnt; + ZXIC_UINT32 kschd_rcv_as_hash3_fc_cnt; + ZXIC_UINT32 kschd_rcv_as_lpm_fc_cnt; + ZXIC_UINT32 kschd_rcv_as_etacm0_fc_cnt; + ZXIC_UINT32 kschd_rcv_as_etacm1_fc_cnt; + ZXIC_UINT32 kschd_rcv_as_pbu_fc_cnt; +}SE_KSCHD_DBG_CNT_T; + +/*rschd 计数�?*/ +typedef struct se_rschd_dbg_cnt_t +{ + ZXIC_UINT32 se_ppu_mex_rsp_cnt[DPP_RSCHD_PPU_CHANNEL_NUM]; + ZXIC_UINT32 rschd_rcv_as_hash0_rsp_cnt; + ZXIC_UINT32 rschd_rcv_as_hash1_rsp_cnt; + ZXIC_UINT32 rschd_rcv_as_hash2_rsp_cnt; + ZXIC_UINT32 rschd_rcv_as_hash3_rsp_cnt; + ZXIC_UINT32 rschd_rcv_as_lpm_rsp_cnt; + ZXIC_UINT32 rschd_rcv_as_etacm0_rsp_cnt; + ZXIC_UINT32 rschd_rcv_as_etacm1_rsp_cnt; + ZXIC_UINT32 rschd_rcv_as_pbu_rsp_cnt; + ZXIC_UINT32 smmu1_rschd_rsp_cnt[DPP_SMMU1_SCH_CNT]; + ZXIC_UINT32 ppu_se_mex_fc_cnt[DPP_RSCHD_PPU_CHANNEL_NUM]; + ZXIC_UINT32 rschd_to_as_hash0_fc_cnt; + ZXIC_UINT32 rschd_to_as_hash1_fc_cnt; + ZXIC_UINT32 rschd_to_as_hash2_fc_cnt; + ZXIC_UINT32 rschd_to_as_hash3_fc_cnt; + ZXIC_UINT32 rschd_to_as_lpm_fc_cnt; + ZXIC_UINT32 rschd_to_as_etacm0_fc_cnt; + ZXIC_UINT32 rschd_to_as_etacm1_fc_cnt; + ZXIC_UINT32 rschd_to_as_pbu_fc_cnt; + ZXIC_UINT32 rschd_smmu1_rdy_cnt[DPP_SMMU1_SCH_CNT]; + ZXIC_UINT32 rschd_rcv_smmu0_wr_done_cnt; + ZXIC_UINT32 rschd_to_smmu0_wr_done_fc_cnt; + ZXIC_UINT32 rschd_rcv_smmu1_wr_done_cnt; + ZXIC_UINT32 rschd_to_smmu1_wr_done_fc_cnt; + ZXIC_UINT32 rschd_rcv_alg_wr_done_cnt; + ZXIC_UINT32 rschd_to_alg_wr_done_fc_cnt; +}SE_RSCHD_DBG_CNT_T; + +/*cmmu 计数�?*/ +typedef struct se_cmmu_dbg_cnt_t +{ + ZXIC_UINT32 stat_cmmu_req_cnt; + ZXIC_UINT32 cmmu_stat_fc_cnt; + ZXIC_UINT32 smmu1_cmmu_wr_fc_cnt; + ZXIC_UINT32 smmu1_cmmu_rd_fc_cnt; +}SE_CMMU_DBG_CNT_T; +/*cmmu req计数�? 结束*/ + +/*se_as模块 计数�?*/ +typedef struct se_as_dbg_cnt_t +{ + ZXIC_UINT32 hash_wr_req_cnt[DPP_HASH_ID_NUM]; + ZXIC_UINT32 smmu0_etcam_fc_cnt[DPP_ETCAM_ID_NUM]; + ZXIC_UINT32 etcam_smmu0_req_cnt[DPP_ETCAM_ID_NUM]; + ZXIC_UINT32 smmu0_etcam_rsp_cnt[DPP_ETCAM_ID_NUM]; + ZXIC_UINT32 as_hla_hash_key_cnt[DPP_HASH_ID_NUM]; + ZXIC_UINT32 as_hla_lpm_key_cnt; + ZXIC_UINT32 alg_as_hash_rsp_cnt[DPP_HASH_ID_NUM]; + ZXIC_UINT32 alg_as_hash_smf_rsp_cnt[DPP_HASH_ID_NUM];/* 命中计数 */ + ZXIC_UINT32 alg_as_lpm_rsp_cnt; + ZXIC_UINT32 alg_as_lpm_smf_rsp_cnt;/* 命中计数 */ + ZXIC_UINT32 as_pbu_key_cnt; + ZXIC_UINT32 pbu_se_dpi_rsp_dat_cnt; + ZXIC_UINT32 as_etcam_ctrl_req_cnt[DPP_ETCAM_ID_NUM]; + ZXIC_UINT32 etcam_ctrl_as_index_cnt[DPP_ETCAM_ID_NUM];/* 有效返回计数 */ + ZXIC_UINT32 etcam_ctrl_as_hit_cnt[DPP_ETCAM_ID_NUM]; + ZXIC_UINT32 as_smmu0_req_cnt; + ZXIC_UINT32 learn_hla_wr_cnt;/* 硬件学习 */ + ZXIC_UINT32 as_smmu1_req_cnt; + ZXIC_UINT32 se_cfg_mac_dat_cnt;/* 到DMA计数 */ + ZXIC_UINT32 alg_as_hash_fc_cnt[DPP_HASH_ID_NUM]; + ZXIC_UINT32 alg_as_lpm_fc_cnt; + ZXIC_UINT32 as_alg_hash_fc_cnt[DPP_HASH_ID_NUM]; + ZXIC_UINT32 as_alg_lpm_fc_cnt; + ZXIC_UINT32 as_pbu_fc_cnt; + ZXIC_UINT32 pbu_se_dpi_key_fc_cnt; + ZXIC_UINT32 as_etcam_ctrl_fc_cnt[DPP_ETCAM_ID_NUM]; + ZXIC_UINT32 etcam_ctrl_as_fc_cnt[DPP_ETCAM_ID_NUM]; + ZXIC_UINT32 smmu0_as_mac_age_fc_cnt; + ZXIC_UINT32 alg_learn_fc_cnt; + ZXIC_UINT32 smmu1_as_fc_cnt; + ZXIC_UINT32 cfg_se_mac_fc_cnt; +}SE_AS_DBG_CNT_T; + + +/* hash 是否响应dma流控使能*/ +typedef enum se_as_hash_dma_fc_en_e +{ + HASH_EN_DMA_FC = 0, + HASH_UN_EN_DMA_FC = 1, +}SE_AS_HASH_DMA_FC_EN_E; +/*se_as模块 计数�? 结束*/ + +/** alg模块调试计数*/ +typedef struct se_alg_dbg_cnt_t +{ + ZXIC_UINT32 hash_key_cnt[4]; + ZXIC_UINT32 hash_rsp_cnt[4]; + ZXIC_UINT32 hash_hit_cnt[4]; + ZXIC_UINT32 hash_space_vld_cnt[4]; + ZXIC_UINT32 hash_ddr3_req_vld_cnt[4]; + ZXIC_UINT32 hash_ddr3_rsp_vld_cnt[4]; + + ZXIC_UINT32 lpm_key_cnt; + ZXIC_UINT32 lpm_rsp_cnt; + ZXIC_UINT32 lpm_hit_cnt; + ZXIC_UINT32 lpm_key_ddr3_req_vld_cnt; /**< @brief LPM_SMMU1_P4口用于键�?*/ + ZXIC_UINT32 lpm_key_ddr3_rsp_vld_cnt; /**< @brief LPM_SMMU1_P4口用于键�?*/ + ZXIC_UINT32 lpm_as_ddr3_req_vld_cnt; /**< @brief LPM_SMMU1_P5口用于关联结�?*/ + ZXIC_UINT32 lpm_as_ddr3_rsp_vld_cnt; /**< @brief LPM_SMMU1_P5口用于关联结�?*/ +}SE_ALG_DBG_CNT_T; + +typedef struct se_alg_dbg_excp_cnt_t +{ + ZXIC_UINT32 schd_learn_fifo_int_cnt; + ZXIC_UINT32 schd_hash_fifo_int_cnt[4]; + ZXIC_UINT32 schd_lpm_fifo_int_cnt; + ZXIC_UINT32 schd_learn_fifo_parity_err_cnt; + ZXIC_UINT32 schd_hash_fifo_parity_err_cnt[4]; + ZXIC_UINT32 schd_lpm_fifo_parity_err_cnt; + ZXIC_UINT32 rd_init_cft_cnt; /**< @brief 初始化过程中出现的CPU读命令冲突计�?*/ + ZXIC_UINT32 zblk_ecc_err_cnt[32]; /**< @brief 32个zblock的ecc错误计数*/ + ZXIC_UINT32 zcam_hash_parity_err_cnt[4]; /**< @brief 4个hash业务口的parity错误计数*/ + ZXIC_UINT32 zcam_lpm_err_cnt; /**< @brief LPM业务口错误计�?*/ + + ZXIC_UINT32 hash_sreq_fifo_parity_err_cnt[4]; + ZXIC_UINT32 hash_sreq_fifo_int_cnt[4]; + ZXIC_UINT32 hash_key_fifo_int_cnt[4]; + ZXIC_UINT32 hash_int_rsp_fifo_parity_err_cnt[4]; + ZXIC_UINT32 hash_ext_rsp_fifo_parity_err_cnt[4]; + ZXIC_UINT32 hash_ext_rsp_fifo_int_cnt[4]; + ZXIC_UINT32 hash_int_rsp_fifo_int_cnt[4]; + + ZXIC_UINT32 lpm_ext_rsp_fifo_int_cnt; + ZXIC_UINT32 lpm_ext_v6_fifo_int_cnt; + ZXIC_UINT32 lpm_ext_v4_fifo_int_cnt; + ZXIC_UINT32 lpm_ext_addr_fifo_int_cnt; + ZXIC_UINT32 lpm_ext_v4_fifo_parity_err_cnt; + ZXIC_UINT32 lpm_ext_v6_fifo_parity_err_cnt; + ZXIC_UINT32 lpm_ext_rsp_fifo_parity_err_cnt; + ZXIC_UINT32 lpm_as_req_fifo_int_cnt; + ZXIC_UINT32 lpm_as_int_rsp_fifo_int_cnt; +}SE_ALG_DBG_EXCP_CNT_T; + + +#define LPM_HW_DAT_BUFF_SIZE_MAX (16 * 1024) +typedef enum { + LPM_DAT_WR_TYPE_DMA = 1UL, + LPM_DAT_WR_TYPE_REG = 2UL, +}LPM_DAT_WR_TYPE; + +typedef enum { + LPM_DAT_ZECLL = 1UL, + LPM_DAT_ZREG = 2UL, + LPM_DAT_DDR = 3UL, + LPM_DAT_DDR_RST = 4UL, + LPM_DAT_ERAM_RST = 5UL, + LPM_DAT_TYPE_MAX, +}ROUTE_DAT_TYPE; + +typedef struct _lpm_hw_dat_ddr +{ + ZXIC_UINT32 dat_type; /* ROUTE_DAT_TYPE :LPM_DAT_DDR/LPM_DAT_DDR_RST */ + ZXIC_UINT32 v4v6_flag; /* ALG_LPM_TYPE_E */ + ZXIC_UINT32 lpm_wr_vld; /* 0-WR 1-RD */ + ZXIC_UINT32 tbl_id; /* 对应复制通道 */ + ZXIC_UINT32 base_addr; /* 19b */ + ZXIC_UINT32 index; /* by rw_len */ + ZXIC_UINT32 ecc_en; + ZXIC_UINT32 rw_len; /* SMMU1_DDR_WRT_MODE_E */ + ZXIC_UINT8 data[512/8]; /* 左对�? */ +}ROUTE_HW_DAT_DDR; + +typedef struct _lpm_hw_dat_zcam +{ + ZXIC_UINT32 dat_type; /* ROUTE_DAT_TYPE :LPM_DAT_ZREG/LPM_DAT_ZECLL */ + ZXIC_UINT32 ram_reg_flag; /* 0-reg 1-cell */ + ZXIC_UINT32 rw_addr; /* by 512b */ + ZXIC_UINT8 data[512/8]; /* 左对�? */ +}ROUTE_HW_DAT_ZCAM; + +typedef struct _lpm_hw_dat_eram +{ + ZXIC_UINT32 dat_type; /* ROUTE_DAT_TYPE :LPM_DAT_ERAM_RST */ + ZXIC_UINT32 base_addr; /* by 128b */ + ZXIC_UINT32 index; /* by rw_len*/ + ZXIC_UINT32 rw_len; /* DPP_ERAM128_TBL_MODE_E */ + ZXIC_UINT8 data[128/8];/* 左对�? */ +}ROUTE_HW_DAT_ERAM; + +typedef struct ppu_stat_cfg_t +{ + ZXIC_UINT32 eram_baddr; /*片内统计基地址，单位128bit*/ + ZXIC_UINT32 eram_depth; /*片内深度，单位128bit*/ + ZXIC_UINT32 ddr_base_addr; /*片外统计基地址(PPU和OAM的片外计数共用此基地址)，单位2k*256bit*/ + ZXIC_UINT32 ppu_addr_offset; /*PPU统计偏移地址,单位128bit*/ +}PPU_STAT_CFG_T; + +/***********************************************************/ +/** dpp hash的smmu1属性设�? +* @param dev_id 设备�? +* @param hash_id hash引擎�? +* @param tbl_id hash表号 +* @param ecc_en ecc使能 +* @param baddr ddr基地址 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark �? +* @see +* @author ls @date 2016/04/12 +************************************************************/ +DPP_STATUS dpp_se_smmu1_hash_tbl_cfg_set(DPP_DEV_T *dev, + ZXIC_UINT32 hash_id, + ZXIC_UINT32 tbl_id, + ZXIC_UINT32 ecc_en, + ZXIC_UINT32 baddr); + +/** 获取hash算法访问DDR空间的属性，从软件获取(待优化) +* @param dev_id 设备号 +* @param hash_id hash引擎号 +* @param bulk_id Hash引擎存储资源划分块数的ID号 +* @param p_ecc_en 使能ECC校验 +* @param p_base_addr DDR空间基地址 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author tf @date 2016/06/15 +************************************************************/ +DPP_STATUS dpp_se_smmu1_hash_tbl_soft_cfg_get(DPP_DEV_T *dev, + ZXIC_UINT32 hash_id, + ZXIC_UINT32 bulk_id, + ZXIC_UINT32 *p_ecc_en, + ZXIC_UINT32 *p_base_addr); + +DPP_STATUS dpp_se_zblk_serv_cfg_set(DPP_DEV_T *dev, ZXIC_UINT32 zblk_idx, ZXIC_UINT32 serv_sel, ZXIC_UINT32 hash_id, ZXIC_UINT32 enable); + +DPP_STATUS dpp_se_zcell_mono_cfg_set(DPP_DEV_T *dev, + ZXIC_UINT32 zblk_idx, + ZXIC_UINT32 zcell0_tbl_id, + ZXIC_UINT32 zcell0_mono_flag, + ZXIC_UINT32 zcell1_tbl_id, + ZXIC_UINT32 zcell1_mono_flag, + ZXIC_UINT32 zcell2_tbl_id, + ZXIC_UINT32 zcell2_mono_flag, + ZXIC_UINT32 zcell3_tbl_id, + ZXIC_UINT32 zcell3_mono_flag); + +DPP_STATUS dpp_se_zcell_mono_cfg_get(DPP_DEV_T *dev, + ZXIC_UINT32 zblk_idx, + ZXIC_UINT32 *zcell0_tbl_id, + ZXIC_UINT32 *zcell0_mono_flag, + ZXIC_UINT32 *zcell1_tbl_id, + ZXIC_UINT32 *zcell1_mono_flag, + ZXIC_UINT32 *zcell2_tbl_id, + ZXIC_UINT32 *zcell2_mono_flag, + ZXIC_UINT32 *zcell3_tbl_id, + ZXIC_UINT32 *zcell3_mono_flag); + +DPP_STATUS dpp_se_zreg_mono_cfg_set(DPP_DEV_T *dev, + ZXIC_UINT32 zblk_idx, + ZXIC_UINT32 zreg0_tbl_id, + ZXIC_UINT32 zreg0_mono_flag, + ZXIC_UINT32 zreg1_tbl_id, + ZXIC_UINT32 zreg1_mono_flag, + ZXIC_UINT32 zreg2_tbl_id, + ZXIC_UINT32 zreg2_mono_flag, + ZXIC_UINT32 zreg3_tbl_id, + ZXIC_UINT32 zreg3_mono_flag); + +DPP_STATUS dpp_se_zreg_mono_cfg_get(DPP_DEV_T *dev, + ZXIC_UINT32 zblk_idx, + ZXIC_UINT32 *zreg0_tbl_id, + ZXIC_UINT32 *zreg0_mono_flag, + ZXIC_UINT32 *zreg1_tbl_id, + ZXIC_UINT32 *zreg1_mono_flag, + ZXIC_UINT32 *zreg2_tbl_id, + ZXIC_UINT32 *zreg2_mono_flag, + ZXIC_UINT32 *zreg3_tbl_id, + ZXIC_UINT32 *zreg3_mono_flag); +DPP_STATUS dpp_se_hash_zcam_mono_flags_set(DPP_DEV_T *dev, + ZXIC_UINT32 hash0_mono_flag, + ZXIC_UINT32 hash1_mono_flag, + ZXIC_UINT32 hash2_mono_flag, + ZXIC_UINT32 hash3_mono_flag); + +DPP_STATUS dpp_se_hash_zcam_mono_flags_get(DPP_DEV_T *dev, + ZXIC_UINT32 *hash0_mono_flag, + ZXIC_UINT32 *hash1_mono_flag, + ZXIC_UINT32 *hash2_mono_flag, + ZXIC_UINT32 *hash3_mono_flag); + +DPP_STATUS dpp_se_hash_ext_cfg_set(DPP_DEV_T *dev, ZXIC_UINT32 hash_id, ZXIC_UINT32 ext_mode, ZXIC_UINT32 flag); +DPP_STATUS dpp_se_hash_ext_cfg_get(DPP_DEV_T *dev, ZXIC_UINT32 hash_id, ZXIC_UINT32 *p_content_type, ZXIC_UINT32 *p_flag); +DPP_STATUS dpp_se_hash_tbl_depth_set(DPP_DEV_T *dev, + ZXIC_UINT32 hash_id, + ZXIC_UINT32 hash_tbl0_depth, + ZXIC_UINT32 hash_tbl1_depth, + ZXIC_UINT32 hash_tbl2_depth, + ZXIC_UINT32 hash_tbl3_depth, + ZXIC_UINT32 hash_tbl4_depth, + ZXIC_UINT32 hash_tbl5_depth, + ZXIC_UINT32 hash_tbl6_depth, + ZXIC_UINT32 hash_tbl7_depth); +DPP_STATUS dpp_se_hash_tbl_depth_get(DPP_DEV_T *dev, + ZXIC_UINT32 hash_id, + ZXIC_UINT32 *hash_tbl0_depth, + ZXIC_UINT32 *hash_tbl1_depth, + ZXIC_UINT32 *hash_tbl2_depth, + ZXIC_UINT32 *hash_tbl3_depth, + ZXIC_UINT32 *hash_tbl4_depth, + ZXIC_UINT32 *hash_tbl5_depth, + ZXIC_UINT32 *hash_tbl6_depth, + ZXIC_UINT32 *hash_tbl7_depth); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/se/dpp_stat_car.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/se/dpp_stat_car.h new file mode 100755 index 0000000..afa4ca5 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/se/dpp_stat_car.h @@ -0,0 +1,1047 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_stat_car.h +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : ls +* 完成日期 : 2016/04/05 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ +#ifndef _DPP_STAT_CAR_H_ +#define _DPP_STAT_CAR_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "dpp_dev.h" +#include "dpp_stat_api.h" + + +#define DPP_CAR_ID_MAX (1) + +#define DPP_CAR_DEBUG_SWITCH (0) + +#define DPP_CAR_A_FLOW_ID_MAX (0x7fff) /*car A支持动态配置暂取32K, 后续待修改*/ +#define DPP_CAR_B_FLOW_ID_MAX (0xfff) +#define DPP_CAR_C_FLOW_ID_MAX (0x3ff) +#define DPP_CAR_A_FLOW_ID_NUM (0x8000) /*car A支持动态配置暂取32K, 后续待修改*/ +#define DPP_CAR_B_FLOW_ID_NUM (0x1000) +#define DPP_CAR_C_FLOW_ID_NUM (0x400) + +#define DPP_CAR_PROFILE_ID_TOTAL ((0x200 + 0x80 + 0x20) * DPP_CAR_ID_MAX) + +#define DPP_CAR_PKT_PROFILE_ID_MAX (0x200) /* 512 */ +#define DPP_CAR_A_PROFILE_ID_MAX (0x1ff) +#define DPP_CAR_B_PROFILE_ID_MAX (0x7f) +#define DPP_CAR_C_PROFILE_ID_MAX (0x1f) + +#define DPP_CAR_B_PROFILE_ID_RANDOM_MAX (0x1f) +#define DPP_CAR_C_PROFILE_ID_RANDOM_MAX (0x7) +#define DPP_CAR_RANDOM_OFFSET_VAL (7) + +#define DPP_CAR_MAX_CBS_VALUE ((1<<27) - 1) +#define DPP_CAR_MAX_EBS_VALUE ((1<<27) - 1) +#define DPP_CAR_MAX_CIR_VALUE ((1<<23) - 1) +#define DPP_CAR_MAX_EIR_VALUE ((1<<23) - 1) +#define DPP_CAR_MAX_PRI_VALUE ((1<<5) - 1) + +#define DPP_CAR_QUEUQ_CFG_TQ_LEN (64) +#define DPP_CAR_QUEUQ_CFG_TQ_HIGH_13BIT_POS (44) +#define DPP_CAR_QUEUQ_CFG_TQ_HIGH_13BIT_LEN (13) +#define DPP_CAR_QUEUQ_CFG_TQ_LOW_32BIT_POS (31) +#define DPP_CAR_QUEUQ_CFG_TQ_LOW_32BIT_LEN (32) + +#define DPP_CAR_PROFILE_CFG_ZXIC_UINT8 (28) +#define DPP_CAR_PROFILE_CFG_ZXIC_UINT32 (DPP_CAR_PROFILE_CFG_ZXIC_UINT8>>2) +#define DPP_CAR_PROFILE_CFG_WIDTH (DPP_CAR_PROFILE_CFG_ZXIC_UINT8<<3) + +#define DPP_CAR_QUEUE_CFG_ZXIC_UINT8 (4) +#define DPP_CAR_QUEUE_CFG_WIDTH (DPP_CAR_QUEUE_CFG_ZXIC_UINT8<<3) + +#define DPP_CAR_PROFILE_CFG_CAR_TYPE_POS (1) +#define DPP_CAR_PROFILE_CFG_CAR_TYPE_LEN (2) +#define DPP_CAR_PROFILE_CFG_PKT_SIGN_POS (2) +#define DPP_CAR_PROFILE_CFG_PKT_SIGN_LEN (1) +#define DPP_CAR_PROFILE_CFG_CD_POS (4) +#define DPP_CAR_PROFILE_CFG_CD_LEN (2) +#define DPP_CAR_PROFILE_CFG_CF_POS (5) +#define DPP_CAR_PROFILE_CFG_CF_LEN (1) +#define DPP_CAR_PROFILE_CFG_CM_POS (6) +#define DPP_CAR_PROFILE_CFG_CM_LEN (1) +#define DPP_CAR_PROFILE_CFG_EIR_POS (28) +#define DPP_CAR_PROFILE_CFG_EIR_LEN (22) +#define DPP_CAR_PROFILE_CFG_CIR_POS (50) +#define DPP_CAR_PROFILE_CFG_CIR_LEN (22) +#define DPP_CAR_PROFILE_CFG_EBS_POS (77) +#define DPP_CAR_PROFILE_CFG_EBS_LEN (27) +#define DPP_CAR_PROFILE_CFG_CBS_POS (104) +#define DPP_CAR_PROFILE_CFG_CBS_LEN (27) +#define DPP_CAR_PROFILE_CFG_C_PRI1_POS (139) +#define DPP_CAR_PROFILE_CFG_C_PRI1_LEN (5) +#define DPP_CAR_PROFILE_CFG_E_G_PRI1_POS (174) +#define DPP_CAR_PROFILE_CFG_E_G_PRI1_LEN (5) +#define DPP_CAR_PROFILE_CFG_E_Y_PRI0_POS (214) +#define DPP_CAR_PROFILE_CFG_E_Y_PRI0_LEN (5) + +#define DPP_CAR_PKT_PROFILE_CFG_CAR_TYPE_POS (1) +#define DPP_CAR_PKT_PROFILE_CFG_CAR_TYPE_LEN (2) +#define DPP_CAR_PKT_PROFILE_CFG_PKT_SIGN_POS (2) +#define DPP_CAR_PKT_PROFILE_CFG_PKT_SIGN_LEN (1) +#define DPP_CAR_PKT_PROFILE_CFG_CIR_POS (32) +#define DPP_CAR_PKT_PROFILE_CFG_CIR_LEN (30) +#define DPP_CAR_PKT_PROFILE_CFG_CBS_POS (46) +#define DPP_CAR_PKT_PROFILE_CFG_CBS_LEN (14) +#define DPP_CAR_PKT_PROFILE_CFG_C_PRI0_POS (86) +#define DPP_CAR_PKT_PROFILE_CFG_C_PRI0_LEN (5) + +#define DPP_CAR_QUEUE_CFG_CAR_TYPE_POS (1) +#define DPP_CAR_QUEUE_CFG_CAR_TYPE_LEN (2) +#define DPP_CAR_QUEUE_CFG_PKT_SIGN_POS (2) +#define DPP_CAR_QUEUE_CFG_PKT_SIGN_LEN (1) +#define DPP_CAR_QUEUE_CFG_QUEUE_ID_POS (16) +#define DPP_CAR_QUEUE_CFG_QUEUE_ID_LEN (14) + +/* car 算法模式 */ +typedef enum dpp_car_cd_mode_e +{ + CAR_CD_MODE_SRTCM = 0, + CAR_CD_MODE_TRTCM, + CAR_CD_MODE_MEF10_1, + CAR_CD_MODE_INVALID +}DPP_CAR_CD_MODE_E; + +/* car 读清模式*/ +typedef enum dpp_car_rd_mode_e +{ + CAR_READ_NOT_CLEAR = 0, + CAR_READ_AND_CLEAR = 1, +}DPP_CAR_RD_MODE_E; + +/* car 翻转模式 */ +typedef enum dpp_car_overflow_mode_e +{ + CAR_KEEP_COUNT = 0, + CAR_RE_COUNT = 1, +}DPP_CAR_OVERFLOW_MODE_E; + +/** QVOS翻转模式 */ +typedef enum dpp_car_qvos_mode_e +{ + CAR_QVOS_MODE_OVERFLOW_0 = 0, + CAR_QVOS_MODE_OVERFLOW_1 = 1, + CAR_QVOS_MODE_OVERFLOW_2 = 2, + CAR_QVOS_MODE_OVERFLOW_MAX +}DPP_CAR_QVOS_MODE_E; + +typedef enum dpp_car_en_mode_e +{ + DPP_CAR_EN_MODE_BOTH_EN = 0, + DPP_CAR_EN_MODE_A_EN = 1, + DPP_CAR_EN_MODE_A_B_EN = 2, + DPP_CAR_EN_MODE_INVALID +}DPP_CAR_EN_MODE_E; + +typedef enum dpp_car_cfg_operate_mode_e +{ + CAR_OPERATE_MODE_ADD = 0, + CAR_OPERATE_MODE_DEL = 1, + CAR_OPERATE_MODE_SRH = 2, + CAR_OPERATE_MODE_GET = 3, + CAR_OPERATE_MODE_MAX, +}DPP_CAR_CFG_OPERATE_MODE_E; + +typedef struct dpp_stat_car_dbg_cnt_t +{ + ZXIC_UINT32 pkt_input_total_cnt; + ZXIC_UINT32 pkt_input_green_cnt; + ZXIC_UINT32 pkt_input_yellow_cnt; + ZXIC_UINT32 pkt_input_red_cnt; + ZXIC_UINT32 pkt_output_total_cnt; + ZXIC_UINT32 pkt_output_green_cnt; + ZXIC_UINT32 pkt_output_yellow_cnt; + ZXIC_UINT32 pkt_output_red_cnt; + ZXIC_UINT32 pkt_fc_dbg_cnt; + ZXIC_UINT32 pkt_size_cnt; +}DPP_STAT_CAR_DBG_CNT_T; + +/** car 包监管模板参数设置的参数 */ +typedef struct dpp_stat_car_pkt_profile_cfg_t +{ + ZXIC_UINT32 profile_id; + ZXIC_UINT32 pkt_sign; + ZXIC_UINT32 cir; + ZXIC_UINT32 cbs; + ZXIC_UINT32 pri[DPP_CAR_PRI_MAX]; /**< @brief pri 0~7是有效值*/ +}DPP_STAT_CAR_PKT_PROFILE_CFG_T; + +/** car A包队列设置的参数 */ +typedef struct dpp_stat_car_a_pkt_queue_cfg_t +{ + ZXIC_UINT32 flow_id; + ZXIC_UINT32 drop_flag; + ZXIC_UINT32 plcr_en; + ZXIC_UINT32 profile_id; + ZXIC_UINT64 tq; + ZXIC_UINT64 dc; + ZXIC_UINT32 tc; +}DPP_STAT_CAR_A_PKT_QUEUE_CFG_T; + +/** car B 队列设置的参数 */ +typedef struct dpp_stat_car_b_queue_cfg_t +{ + ZXIC_UINT32 flow_id; + ZXIC_UINT32 drop_flag; + ZXIC_UINT32 plcr_en; + ZXIC_UINT32 profile_id; + ZXIC_UINT64 tq; + ZXIC_UINT32 tce_flag; + ZXIC_UINT32 tce; + ZXIC_UINT32 tc; + ZXIC_UINT32 te; +}DPP_STAT_CAR_B_QUEUE_CFG_T; + +/** car C 队列设置的参数 */ +typedef struct dpp_stat_car_c_queue_cfg_t +{ + ZXIC_UINT32 flow_id; + ZXIC_UINT32 drop_flag; + ZXIC_UINT32 plcr_en; + ZXIC_UINT32 profile_id; + ZXIC_UINT64 tq; + ZXIC_UINT32 tce_flag; + ZXIC_UINT32 tce; + ZXIC_UINT32 tc; + ZXIC_UINT32 te; +}DPP_STAT_CAR_C_QUEUE_CFG_T; + +/* profile配置键值 */ +typedef struct dpp_car_profile_rb_key_t +{ + /**carprofile: + car_type[2]+pkt_sign[1]+cd[2]+cf[1]+cm[1]+eir[22]+cir[22]+ebs[27]+cbs[27]+cpri[35]+e_g_pri[35]+e_y_pri[40]+0[9]*/ + /**carpktprofile: + car_type[2]+pkt_sign[1]+cir[30]+cbs[14]+c_pri[32]+0[115]*/ + ZXIC_UINT32 profile_cfg[DPP_CAR_PROFILE_CFG_ZXIC_UINT32]; + ZXIC_UINT32 is_static; /* 是否静态，静态的profile必须由用户手动删除,待实现 */ + ZXIC_UINT32 use_count; +}DPP_CAR_PROFILE_RB_KEY_T; + +/* profile id与profile 配置节点关系键值 */ +typedef struct dpp_car_profile_id_rb_key_t +{ + ZXIC_UINT32 profile_id; + void * p_car_node; + ZXIC_UINT32 is_used; +}DPP_CAR_PROFILE_ID_RB_KEY_T; + +/* 队列和profile id绑定关系键值 */ +typedef struct dpp_car_queue_rb_key_t +{ /** carqueue + car_type[2]+pkt_sign[1]+queue_id[14]+15[0]*/ + ZXIC_UINT8 profile_cfg[DPP_CAR_QUEUE_CFG_ZXIC_UINT8]; + ZXIC_UINT32 is_used; + ZXIC_UINT32 profile_id; +}DPP_CAR_QUEUE_RB_KEY_T; + +/* 红黑树管理 */ +typedef struct dpp_car_rb_mng_t +{ + ZXIC_UINT32 init_en; + ZXIC_UINT32 total_num; + ZXIC_UINT32 key_size; /** 单个红黑树节点空间的大小 */ + ZXIC_RB_CMPFUN p_cmpfun; + ZXIC_RB_CMPFUN p_id_cmpfun; + ZXIC_RB_CFG * p_plcr_rb; + ZXIC_RB_CFG * p_plcr_id_rb; /** 由id反查car的配置 的红黑树结构 */ + ZXIC_LISTSTACK_MANGER *p_liststack_mng; /** 索引分配 */ +}DPP_CAR_RB_MNG_T; + +/* profile管理 */ +typedef struct dpp_car_profile_mng_t +{ + ZXIC_UINT32 is_init; + DPP_CAR_RB_MNG_T *p_car_a_rb_profile_mng; + DPP_CAR_RB_MNG_T *p_car_b_rb_profile_mng; + DPP_CAR_RB_MNG_T *p_car_c_rb_profile_mng; +}DPP_CAR_PROFILE_MNG_T; + +/* 队列管理 */ +typedef struct dpp_car_queue_mng_t +{ + ZXIC_UINT32 is_init; + DPP_CAR_RB_MNG_T *p_car_rb_queue_mng; /** 不同的car*/ +}DPP_CAR_QUEUE_MNG_T; + +/* car配置信息 */ +typedef struct dpp_car_cfg_t +{ + ZXIC_UINT32 is_init[DPP_DEV_CHANNEL_MAX]; + ZXIC_UINT32 car0_mono_mode[DPP_DEV_CHANNEL_MAX]; + DPP_CAR_QUEUE_MNG_T * p_car_queue_mng[DPP_DEV_CHANNEL_MAX]; + DPP_CAR_PROFILE_MNG_T * p_car_profile_mng[DPP_DEV_CHANNEL_MAX]; +}DPP_CAR_CFG_T; + +/* car软复位需要存储的参数 */ +typedef struct dpp_car_soft_reset_item_t +{ + ZXIC_UINT32 flow_id; + ZXIC_UINT32 profile_id; +}DPP_CAR_SOFT_RESET_ITEM_T; + +typedef struct dpp_car_soft_reset_data_t +{ + ZXIC_UINT8 car_pkt_sign[DPP_CAR_PKT_PROFILE_ID_MAX]; /* */ + + ZXIC_UINT32 is_init; /* car是否初始化标志位 */ + ZXIC_UINT32 car0_pkt_num; /* */ + + ZXIC_UINT32 cara_flow_num; /* car0已配置过的流ID数目 */ + ZXIC_UINT32 carb_flow_num; /* car0已配置过的流ID数目 */ + ZXIC_UINT32 carc_flow_num; /* car0已配置过的流ID数目 */ + + DPP_CAR_SOFT_RESET_ITEM_T cara_item[DPP_CAR_A_FLOW_ID_NUM]; + DPP_CAR_SOFT_RESET_ITEM_T carb_item[DPP_CAR_B_FLOW_ID_NUM]; + DPP_CAR_SOFT_RESET_ITEM_T carc_item[DPP_CAR_C_FLOW_ID_NUM]; + +}DPP_CAR_SOFT_RESET_DATA_T; + +typedef struct dpp_car_random_ram_t +{ + ZXIC_UINT32 p1; /* 第一档丢弃概率(百分比)，取值0-100，推荐为1(百分比) */ + ZXIC_UINT32 p2; /* 第二档丢弃概率(百分比)，取值0-100，推荐为10(百分比) */ + ZXIC_UINT32 p3; /* 第三档丢弃概率(百分比)，取值0-100，推荐为50(百分比) */ + ZXIC_UINT32 tc; /* 桶深，即CBS或EBS */ + ZXIC_UINT32 t1; /* 桶深的低水线，取值0-CBS/EBS，推荐是70%的桶深 */ + ZXIC_UINT32 t2; /* 桶深的中水线，取值0-CBS/EBS，推荐是85%的桶深 */ + ZXIC_UINT32 t3; /* 桶深的高水线，取值0-CBS/EBS，推荐是95%的桶深 */ +}DPP_CAR_RANDOM_RAM_T; + +typedef struct dpp_car_soft_reset_queue_t +{ + ZXIC_UINT32 car_type; + ZXIC_UINT32 flow_id; + ZXIC_UINT32 drop_flag; + ZXIC_UINT32 plcr_en; + ZXIC_UINT32 profile_id; + +}DPP_CAR_SOFT_RESET_QUEUE_T; + +/***********************************************************/ +/** car A包限速监管模板设定 +* @param dev_id 设备号 car号 +* @param profile_id 监管模板号 +* @param p_cara_profile_cfg 监管模板配置 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/04/05 +************************************************************/ +DPP_STATUS dpp_stat_cara_pkt_profile_cfg_set(DPP_DEV_T *dev, + ZXIC_UINT32 profile_id, + DPP_STAT_CAR_PKT_PROFILE_CFG_T* p_cara_profile_cfg); + +/***********************************************************/ +/** 获取car A 包长监管流配置 +* @param dev_id 设备号 car号 +* @param flow_id 流号 +* @param p_cara_queue_cfg car A流配置信息 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/04/05 +************************************************************/ +DPP_STATUS dpp_stat_cara_pkt_queue_cfg_get(DPP_DEV_T *dev, + ZXIC_UINT32 flow_id, + DPP_STAT_CAR_A_PKT_QUEUE_CFG_T* p_cara_queue_cfg); + +/***********************************************************/ +/** 配置car B 概率丢弃配置参数 +* @param dev_id +* @param profile_id +* @param p_random_ram +* +* @return +* @remark 无 +* @see +* @author YXH @date 2019/04/01 +************************************************************/ +DPP_STATUS dpp_stat_carb_random_ram_set(DPP_DEV_T *dev, + ZXIC_UINT32 profile_id, + DPP_CAR_RANDOM_RAM_T *p_random_ram_e, + DPP_CAR_RANDOM_RAM_T *p_random_ram_c); + +/***********************************************************/ +/** 获取car B 概率丢弃配置参数 +* @param dev_id +* @param profile_id +* @param p_random_ram +* +* @return +* @remark 无 +* @see +* @author YXH @date 2019/04/01 +************************************************************/ +DPP_STATUS dpp_stat_carb_random_ram_get(DPP_DEV_T *dev, + ZXIC_UINT32 profile_id, + DPP_CAR_RANDOM_RAM_T *p_random_ram_e, + DPP_CAR_RANDOM_RAM_T *p_random_ram_c); + +/***********************************************************/ +/** 配置car C 概率丢弃配置参数 +* @param dev_id +* @param profile_id +* @param p_random_ram +* +* @return +* @remark 无 +* @see +* @author YXH @date 2019/04/01 +************************************************************/ +DPP_STATUS dpp_stat_carc_random_ram_set(DPP_DEV_T *dev, + ZXIC_UINT32 profile_id, + DPP_CAR_RANDOM_RAM_T *p_random_ram_e, + DPP_CAR_RANDOM_RAM_T *p_random_ram_c); + +/***********************************************************/ +/** 获取car B 概率丢弃配置参数 +* @param dev_id +* @param profile_id +* @param p_random_ram +* +* @return +* @remark 无 +* @see +* @author YXH @date 2019/04/01 +************************************************************/ +DPP_STATUS dpp_stat_carc_random_ram_get(DPP_DEV_T *dev, + ZXIC_UINT32 profile_id, + DPP_CAR_RANDOM_RAM_T *p_random_ram_e, + DPP_CAR_RANDOM_RAM_T *p_random_ram_c); + +/***********************************************************/ +/** 获取car的包长偏移 +* @param dev_id +* @param p_pkt_size_off +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author wll @date 2019/06/06 +************************************************************/ +DPP_STATUS dpp_stat_car_pkt_size_offset_get(DPP_DEV_T *dev, + ZXIC_UINT32 *p_pkt_size_off); + +/***********************************************************/ +/** 配置cara的最大包长 +* @param dev_id +* @param max_pkt_size +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author wll @date 2019/06/06 +************************************************************/ +DPP_STATUS dpp_stat_cara_max_pkt_size_set(DPP_DEV_T *dev, + ZXIC_UINT32 max_pkt_size); + +/***********************************************************/ +/** 获取cara的最大包长 +* @param dev_id +* @param p_max_pkt_size +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author wll @date 2019/06/06 +************************************************************/ +DPP_STATUS dpp_stat_cara_max_pkt_size_get(DPP_DEV_T *dev, + ZXIC_UINT32 *p_max_pkt_size); + +/***********************************************************/ +/** 配置carb的最大包长 +* @param dev_id +* @param max_pkt_size +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author wll @date 2019/06/06 +************************************************************/ +DPP_STATUS dpp_stat_carb_max_pkt_size_set(DPP_DEV_T *dev, + ZXIC_UINT32 max_pkt_size); + +/***********************************************************/ +/** 获取carb的最大包长 +* @param dev_id +* @param p_max_pkt_size +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author wll @date 2019/06/06 +************************************************************/ +DPP_STATUS dpp_stat_carb_max_pkt_size_get(DPP_DEV_T *dev, + ZXIC_UINT32 *p_max_pkt_size); + +/***********************************************************/ +/** 配置carc的最大包长 +* @param dev_id +* @param max_pkt_size +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author wll @date 2019/06/06 +************************************************************/ +DPP_STATUS dpp_stat_carc_max_pkt_size_set(DPP_DEV_T *dev, + ZXIC_UINT32 max_pkt_size); + +/***********************************************************/ +/** 获取carc的最大包长 +* @param dev_id +* @param p_max_pkt_size +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author wll @date 2019/06/06 +************************************************************/ +DPP_STATUS dpp_stat_carc_max_pkt_size_get(DPP_DEV_T *dev, + ZXIC_UINT32 *p_max_pkt_size); + +/***********************************************************/ +/** 获取最大包长 +* @param dev_id +* @param car_type +* @param p_max_pkt_len +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author wll @date 2019/06/06 +************************************************************/ +DPP_STATUS dpp_stat_car_max_pkt_size_get(DPP_DEV_T *dev, + ZXIC_UINT32 car_type, + ZXIC_UINT32 *p_max_pkt_len); + +/***********************************************************/ +/** 配置car的包长偏移 +* @param dev_id +* @param pkt_size_off +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author wll @date 2019/06/06 +************************************************************/ +DPP_STATUS dpp_stat_car_pkt_size_offset_set(DPP_DEV_T *dev, + ZXIC_UINT32 pkt_size_off); + +/***********************************************************/ +/** 配置最大包长 +* @param dev_id +* @param car_type +* @param max_pkt_size +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author wll @date 2019/06/06 +************************************************************/ +DPP_STATUS dpp_stat_car_max_pkt_size_set(DPP_DEV_T *dev, + ZXIC_UINT32 car_type, + ZXIC_UINT32 max_pkt_size); + +/***********************************************************/ +/** car 模块流配置 +* @param dev_id +* @param car_type +* @param flow_id +* @param drop_flag +* @param plcr_en +* @param profile_id +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/05/06 +************************************************************/ +DPP_STATUS dpp_stat_car_queue_cfg_set(DPP_DEV_T *dev, + ZXIC_UINT32 car_type, + ZXIC_UINT32 flow_id, + ZXIC_UINT32 drop_flag, + ZXIC_UINT32 plcr_en, + ZXIC_UINT32 profile_id); + +/***********************************************************/ +/** car profile硬件写入 +* @param dev_id +* @param car_type +* @param pkt_sign +* @param profile_id +* @param p_car_profile_cfg +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/05/06 +************************************************************/ +DPP_STATUS dpp_stat_car_profile_cfg_set(DPP_DEV_T *dev, + ZXIC_UINT32 car_type, + ZXIC_UINT32 pkt_sign, + ZXIC_UINT32 profile_id, + ZXIC_VOID* p_car_profile_cfg); + +/***********************************************************/ +/** car 队列映射关系配置 +* @param dev_id 设备号 0:上行CAR限速 1:下行CAR限速 +* @param car_type 0:A级car，1:B级car，2:C级car +* @param flow_id 流号 +* @param map_flow_id 映射后的流号 +* @param map_sp 映射后的优先级 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/09/27 +************************************************************/ +DPP_STATUS dpp_stat_car_queue_map_set(DPP_DEV_T *dev, + ZXIC_UINT32 car_type, + ZXIC_UINT32 flow_id, + ZXIC_UINT32 map_flow_id, + ZXIC_UINT32 map_sp); + +/***********************************************************/ +/** +* @param dev_id +* @param car_type +* @param pkt_sign +* @param flow_id +* @param p_data +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/09/27 +************************************************************/ +DPP_STATUS dpp_stat_car_queue_get(DPP_DEV_T *dev, + ZXIC_UINT32 car_type, + ZXIC_UINT32 pkt_sign, + ZXIC_UINT32 flow_id, + ZXIC_VOID* p_data); +/***********************************************************/ +/** car 模块流配置获取 +* @param dev_id +* @param car_type +* @param flow_id +* @param p_drop_flag +* @param p_plcr_en +* @param p_profile_id +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/08/19 +************************************************************/ +DPP_STATUS dpp_stat_car_queue_cfg_get(DPP_DEV_T *dev, + ZXIC_UINT32 car_type, + ZXIC_UINT32 flow_id, + ZXIC_UINT32 *p_drop_flag, + ZXIC_UINT32 *p_plcr_en, + ZXIC_UINT32 *p_profile_id); + +DPP_STATUS dpp_stat_car_profile_cfg_get(DPP_DEV_T *dev, + ZXIC_UINT32 car_type, + ZXIC_UINT32 pkt_sign, + ZXIC_UINT32 profile_id, + ZXIC_VOID* p_car_profile_cfg); + +/***********************************************************/ +/** +* @param dev_id 设备ID car ID +* @param profile_id 模板ID +* @param p_random_ram_e E桶概率丢弃配置参数 +* @param p_random_ram_c C桶概率丢弃配置参数 +* +* @return +* @remark 无 +* @see +* @author YXH @date 2019/04/01 +************************************************************/ +DPP_STATUS dpp_stat_car_random_ram_set(DPP_DEV_T *dev, + ZXIC_UINT32 car_type, + ZXIC_UINT32 profile_id, + DPP_CAR_RANDOM_RAM_T *p_random_ram_e, + DPP_CAR_RANDOM_RAM_T *p_random_ram_c); + +/***********************************************************/ +/** +* @param dev_id 设备ID car ID +* @param profile_id 模板ID +* @param p_random_ram_e E桶概率丢弃配置参数 +* @param p_random_ram_c C桶概率丢弃配置参数 +* +* @return +* @remark 无 +* @see +* @author YXH @date 2019/04/01 +************************************************************/ +DPP_STATUS dpp_stat_car_random_ram_get(DPP_DEV_T *dev, + ZXIC_UINT32 car_type, + ZXIC_UINT32 profile_id, + DPP_CAR_RANDOM_RAM_T *p_random_ram_e, + DPP_CAR_RANDOM_RAM_T *p_random_ram_c); + +/***********************************************************/ +/** 获取 car 流号的绑定关系 +* @param dev_id +* @param car_type +* @param flow_id +* @param p_map_flow_id +* @param p_map_sp +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/09/27 +************************************************************/ +DPP_STATUS dpp_stat_car_queue_map_get(DPP_DEV_T *dev, + ZXIC_UINT32 car_type, + ZXIC_UINT32 flow_id, + ZXIC_UINT32* p_map_flow_id, + ZXIC_UINT32* p_map_sp); + +/***********************************************************/ +/** car 模块调试计数 获取 +* @param dev_id +* @param car_type +* @param p_car_dbg_cnt +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/09/27 +************************************************************/ +DPP_STATUS dpp_stat_car_dbg_cnt_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 car_type, + DPP_STAT_CAR_DBG_CNT_T *p_car_dbg_cnt); +/***********************************************************/ +/** +* @param dev_id +* @param car_type +* @param overflow_mode +* @param rd_mode +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/09/27 +************************************************************/ +DPP_STATUS dpp_stat_car_dbg_cnt_mode_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 car_type, + ZXIC_UINT32 overflow_mode, + ZXIC_UINT32 rd_mode); +/***********************************************************/ +/** +* @param dev_id +* @param car_type +* @param p_overflow_mode +* @param p_rd_mode +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/09/27 +************************************************************/ +DPP_STATUS dpp_stat_car_dbg_cnt_mode_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 car_type, + ZXIC_UINT32* p_overflow_mode, + ZXIC_UINT32* p_rd_mode); + +/***********************************************************/ +/** car 模块初始化 +* @param dev_id +* @param p_car_cfg +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/05/05 +************************************************************/ +DPP_STATUS dpp_stat_car_init(ZXIC_UINT32 dev_id, + DPP_CAR_CFG_T *p_car_cfg); + + +/***********************************************************/ +/** STAT CAR复位获取全局变量大小函数 +* @param dev_id +* @param p_size +* +* @return +* @remark 无 +* @see +* @author yxh @date 2018/06/26 +************************************************************/ +DPP_STATUS dpp_stat_car_glb_size_get(DPP_DEV_T *dev, ZXIC_UINT32* p_size); + +/***********************************************************/ +/** STAT CAR复位设置全局变量函数 +* @param dev_id 设备号 +* @param size 大小，字节数 +* @param p_data_buff 全局变量数据 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author yxh @date 2018/06/26 +************************************************************/ +DPP_STATUS dpp_stat_car_glb_mgr_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 size, ZXIC_UINT8 *p_data_buff); + +/***********************************************************/ +/** STAT CAR复位获取全局变量函数 +* @param dev_id 设备号 +* @param p_flag 释放使能，1-需要手动free，0-不需要手动free +* @param p_size 数据大小 +* @param pp_data_buff 全局变量数据 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author yxh @date 2018/06/26 +************************************************************/ +DPP_STATUS dpp_stat_car_glb_mgr_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *p_flag, + ZXIC_UINT32 *p_size, + ZXIC_UINT8 **pp_data_buff); + +DPP_STATUS dpp_stat_queue_rb_root_prt(ZXIC_RB_CFG *p_rb_cfg); +DPP_STATUS dpp_stat_car_profile_id_rb_root_prt(ZXIC_UINT32 dev_id, ZXIC_RB_CFG *p_rb_cfg); + +/***********************************************************/ +/** 配置car A的qvos溢出模式 +* @param dev_id 设备号 car编号 +* @param flow_id 流号 +* @param qvos_mode 溢出模式，参见DPP_CAR_QVOS_MODE_E +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/04/06 +************************************************************/ +DPP_STATUS dpp_stat_cara_queue_qvos_set(DPP_DEV_T *dev, + ZXIC_UINT32 flow_id, + ZXIC_UINT32 qvos_mode); + +/***********************************************************/ +/** 获取car A的qvos溢出模式 +* @param dev_id 设备号 car编号 +* @param flow_id 流号 +* @param p_qvos_mode qvos溢出模式 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/04/06 +************************************************************/ +DPP_STATUS dpp_stat_cara_queue_qvos_get(DPP_DEV_T *dev, + ZXIC_UINT32 flow_id, + ZXIC_UINT32 *p_qvos_mode); + +/***********************************************************/ +/** car A指定队列模式配置，仅用于调试 +* @param dev_id 设备号 car编号 +* @param global_en 全局队列使能，0-不使能，1-使能 +* @param sp_en 优先级队列使能，0-不使能，1-使能 +* @param appoint_sp 指定的优先级 +* @param appoint_queue 指定的队列号 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/04/06 +************************************************************/ +DPP_STATUS dpp_stat_cara_queue_appoint_mode_set(DPP_DEV_T *dev, + ZXIC_UINT32 global_en, + ZXIC_UINT32 sp_en, + ZXIC_UINT32 appoint_sp, + ZXIC_UINT32 appoint_queue); + +/***********************************************************/ +/** 获取car A指定队列模式的配置 +* @param dev_id 设备号 car编号 +* @param p_global_en 全局队列使能，0-不使能，1-使能 +* @param p_sp_en 优先级队列使能，0-不使能，1-使能 +* @param p_appoint_sp 指定的优先级 +* @param p_appoint_queue 指定的队列号 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/04/07 +************************************************************/ +DPP_STATUS dpp_stat_cara_queue_appoint_mode_get(DPP_DEV_T *dev, + ZXIC_UINT32 *p_global_en, + ZXIC_UINT32 *p_sp_en, + ZXIC_UINT32 *p_appoint_sp, + ZXIC_UINT32 *p_appoint_queue); + +/***********************************************************/ +/** 配置car B的qvos溢出模式 +* @param dev_id 设备号 car编号 +* @param flow_id 流号 +* @param qvos_mode 溢出模式，参见DPP_CAR_QVOS_MODE_E +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/04/06 +************************************************************/ +DPP_STATUS dpp_stat_carb_queue_qvos_set(DPP_DEV_T *dev, + ZXIC_UINT32 flow_id, + ZXIC_UINT32 qvos_mode); + +/***********************************************************/ +/** 获取car B的qvos溢出模式 +* @param dev_id 设备号 car编号 +* @param flow_id 流号 +* @param p_qvos_mode qvos溢出模式 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/04/06 +************************************************************/ +DPP_STATUS dpp_stat_carb_queue_qvos_get(DPP_DEV_T *dev, + ZXIC_UINT32 flow_id, + ZXIC_UINT32 *p_qvos_mode); + +/***********************************************************/ +/** car B指定队列模式配置，仅用于调试 +* @param dev_id 设备号 car编号 +* @param global_en 全局队列使能，0-不使能，1-使能 +* @param sp_en 优先级队列使能，0-不使能，1-使能 +* @param appoint_sp 指定的优先级 +* @param appoint_queue 指定的队列号 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/04/06 +************************************************************/ +DPP_STATUS dpp_stat_carb_queue_appoint_mode_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 global_en, + ZXIC_UINT32 sp_en, + ZXIC_UINT32 appoint_sp, + ZXIC_UINT32 appoint_queue); +/***********************************************************/ +/** 获取car B指定队列模式的配置 +* @param dev_id 设备号 car编号 +* @param p_global_en 全局队列使能，0-不使能，1-使能 +* @param p_sp_en 优先级队列使能，0-不使能，1-使能 +* @param p_appoint_sp 指定的优先级 +* @param p_appoint_queue 指定的队列号 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/04/07 +************************************************************/ +DPP_STATUS dpp_stat_carb_queue_appoint_mode_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *p_global_en, + ZXIC_UINT32 *p_sp_en, + ZXIC_UINT32 *p_appoint_sp, + ZXIC_UINT32 *p_appoint_queue); + +/***********************************************************/ +/** 配置car C的qvos溢出模式 +* @param dev_id 设备号 car编号 +* @param flow_id 流号 +* @param qvos_mode 溢出模式，参见DPP_CAR_QVOS_MODE_E +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/04/06 +************************************************************/ +DPP_STATUS dpp_stat_carc_queue_qvos_set(DPP_DEV_T *dev, + ZXIC_UINT32 flow_id, + ZXIC_UINT32 qvos_mode); + +/***********************************************************/ +/** 获取car C的qvos溢出模式 +* @param dev_id 设备号 car编号 +* @param flow_id 流号 +* @param p_qvos_mode qvos溢出模式 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/04/06 +************************************************************/ +DPP_STATUS dpp_stat_carc_queue_qvos_get(DPP_DEV_T *dev, + ZXIC_UINT32 flow_id, + ZXIC_UINT32 *p_qvos_mode); + +/***********************************************************/ +/** car C指定队列模式配置，仅用于调试 +* @param dev_id 设备号 car编号 +* @param global_en 全局队列使能，0-不使能，1-使能 +* @param sp_en 优先级队列使能，0-不使能，1-使能 +* @param appoint_sp 指定的优先级 +* @param appoint_queue 指定的队列号 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/04/06 +************************************************************/ +DPP_STATUS dpp_stat_carc_queue_appoint_mode_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 global_en, + ZXIC_UINT32 sp_en, + ZXIC_UINT32 appoint_sp, + ZXIC_UINT32 appoint_queue); + +/***********************************************************/ +/** 获取car C指定队列模式的配置 +* @param dev_id 设备号 car编号 +* @param p_global_en 全局队列使能，0-不使能，1-使能 +* @param p_sp_en 优先级队列使能，0-不使能，1-使能 +* @param p_appoint_sp 指定的优先级 +* @param p_appoint_queue 指定的队列号 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/04/07 +************************************************************/ +DPP_STATUS dpp_stat_carc_queue_appoint_mode_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *p_global_en, + ZXIC_UINT32 *p_sp_en, + ZXIC_UINT32 *p_appoint_sp, + ZXIC_UINT32 *p_appoint_queue); + +/***********************************************************/ +/** +* @param dev_id +* @param p_mode +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/09/28 +************************************************************/ +DPP_STATUS dpp_stat_car_en_mode_get(DPP_DEV_T *dev, + ZXIC_UINT32 *p_mode); + +#ifdef __cplusplus +} +#endif + +#endif + + + diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/se/dpp_stat_cfg.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/se/dpp_stat_cfg.h new file mode 100755 index 0000000..bd4a1cf --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/se/dpp_stat_cfg.h @@ -0,0 +1,196 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_stat_cfg.h +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : ls +* 完成日期 : 2016/03/29 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ +#ifndef _DPP_STAT_CFG_H_ +#define _DPP_STAT_CFG_H_ + +#ifdef __cplusplus +extern "C" { +#endif +#include "dpp_stat_api.h" + +#if ZXIC_REAL("Variable definition") + +#define DPP_STAT_TM_PORT_MAX (4) +#define DPP_STAT_ETM_ADDR_MAX (9*1024) +#define DPP_STAT_FTM_ADDR_MAX (2048) +#define DPP_STAT_IND_WR_MODE (0) +#define DPP_STAT_IND_RD_MODE (1) +#define DPP_STAT_TM_MOV_PERIOD_MAX (0xff) + +#define DPP_STAT_WIDTH_3_MAX_VALUE ((1<<3) - 1) +#define DPP_STAT_WIDTH_4_MAX_VALUE ((1<<4) - 1) +#define DPP_STAT_PPU_ERAM_DEPTH_MAX (0x7ffff) +#define DPP_STAT_PPU_ERAM_BADDR_MAX (0x7ffff) +#define DPP_STAT_PPU_DDR_BADDR_MAX (0x4ffffff) + +#define DPP_STAT_OAM_ERAM_BADDR_MAX (0x7ffff) +#define DPP_STAT_OAM_DDR_BADDR_MAX (0x4ffffff) + +#define DPP_STAT_PLCR_ERAM_BADDR_MAX (0x7ffff) +#define DPP_STAT_PLCR_ID (0) + +#define DPP_STAT_TM_FLAG_FTM_PKT_EN (0) +#define DPP_STAT_TM_FLAG_ETM_PKT_EN (1) +#define DPP_STAT_TM_FLAG_ERAM_EN (2) + +#define DPP_STAT_PPU_STAT_CHANNEL_NUM (16) +#define DPP_STAT_PPU_MEX_NUM (6) +#define CMMU_DDR_DIR_CPY_NUM (15) + + +/** stat TM类型 */ +typedef enum dpp_stat_tm_type_e +{ + DPP_STAT_TM_TYPE_ETM = 0, /*<@brief FTM模式 */ + DPP_STAT_TM_TYPE_FTM = 1, /*<@brief ETM模式 */ + DPP_STAT_TM_TYPE_MAX +}DPP_STAT_TM_TYPE_E; + + +typedef enum dpp_stat_tm_store_mode_e +{ + DPP_STAT_TM_STORE_MODE_ERAM = 0, /* 片内存储模式 */ + DPP_STAT_TM_STORE_MODE_MIX = 1, /* 混合存储模式 */ + DPP_STAT_TM_STORE_MODE_MAX, +}DPP_STAT_TM_STORE_MODE_E; + +typedef enum dpp_stat_etm_depth_mode_e +{ + DPP_STAT_ETM_DEPTH_ERAM_1K = 0, + DPP_STAT_ETM_DEPTH_ERAM_4K = 1, + DPP_STAT_ETM_DEPTH_ERAM_5K = 2, + DPP_STAT_ETM_DEPTH_ERAM_8K = 3, + DPP_STAT_ETM_DEPTH_ERAM_9K = 4, + DPP_STAT_ETM_DEPTH_MIX_2K = 5, + DPP_STAT_ETM_DEPTH_MIX_8K = 6, + DPP_STAT_ETM_DEPTH_MIX_9K = 7, + DPP_STAT_ETM_DEPTH_MAX, +}DPP_STAT_ETM_DEPTH_MODE_E; + +typedef enum stat_store_mode_e +{ + STAT_STORE_MODE_IN_ERAM = 0, + STAT_STORE_MODE_IN_DDR = 1, + STAT_STORE_MODE_MAX, +}STAT_STORE_MODE_E; + +typedef enum stat_oam_type_e +{ + STAT_OAM_TYPE_ERAM = 0, + STAT_OAM_TYPE_LM_ERAM = 1, + STAT_OAM_TYPE_DDR = 2, + STAT_OAM_TYPE_MAX, +}STAT_OAM_TYPE_E; + +typedef struct dpp_stat_dbg_cnt_t +{ + ZXIC_UINT32 stat_to_smmu0_rsp_fc_cnt[DPP_STAT_PPU_STAT_CHANNEL_NUM]; + ZXIC_UINT32 stat_rcv_smmu0_req_fc_cnt[DPP_STAT_PPU_STAT_CHANNEL_NUM]; + ZXIC_UINT32 stat_to_ppu_req_fc_cnt[DPP_STAT_PPU_MEX_NUM]; + ZXIC_UINT32 stat_rcv_ppu_rsp_fc_cnt[DPP_STAT_PPU_MEX_NUM]; + ZXIC_UINT32 stat_rcv_se_etm_wr_fc_cnt; + ZXIC_UINT32 stat_rcv_se_etm_rd_fc_cnt; + ZXIC_UINT32 stat_rcv_se_ftm_wr_fc_cnt; + ZXIC_UINT32 stat_rcv_se_ftm_rd_fc_cnt; + ZXIC_UINT32 stat_to_etm_deq_fc_cnt; + ZXIC_UINT32 stat_to_etm_enq_fc_cnt; + ZXIC_UINT32 stat_to_ftm_deq_fc_cnt; + ZXIC_UINT32 stat_to_ftm_enq_fc_cnt; + ZXIC_UINT32 stat_to_oam_lm_fc_cnt; + ZXIC_UINT32 stat_rcv_oam_lm_fc_cnt; + ZXIC_UINT32 stat_to_oam_fc_cnt; + ZXIC_UINT32 stat_rcv_cmmu_fc_cnt; + ZXIC_UINT32 stat_to_cmmu_req_cnt; + ZXIC_UINT32 stat_rcv_smmu0_rsp_cnt[DPP_STAT_PPU_STAT_CHANNEL_NUM]; + ZXIC_UINT32 stat_to_smmu0_req_cnt[DPP_STAT_PPU_STAT_CHANNEL_NUM]; + ZXIC_UINT32 stat_plcr_rcv_smmu0_rsp1_cnt; + ZXIC_UINT32 stat_plcr_rcv_smmu0_rsp0_cnt; + ZXIC_UINT32 stat_plcr_to_smmu0_req1_cnt; + ZXIC_UINT32 stat_plcr_to_smmu0_req0_cnt; + ZXIC_UINT32 stat_to_ppu_mex_rsp_cnt[DPP_STAT_PPU_MEX_NUM]; + ZXIC_UINT32 stat_oam_lm_rsp_cnt; + ZXIC_UINT32 stat_rcv_oam_lm_req_cnt; + ZXIC_UINT32 stat_rcv_oam_req_cnt; + ZXIC_UINT32 stat_rcv_ppu_mex_key_cnt[DPP_STAT_PPU_MEX_NUM]; + ZXIC_UINT32 stat_rcv_se_etm_rsp_cnt; + ZXIC_UINT32 stat_rcv_etm_se_wr_req_cnt; + ZXIC_UINT32 stat_rcv_etm_se_rd_req_cnt; + ZXIC_UINT32 stat_rcv_se_ftm_rsp_cnt; + ZXIC_UINT32 stat_to_ftm_se_wr_req_cnt; + ZXIC_UINT32 stat_to_ftm_se_rd_req_cnt; + ZXIC_UINT32 stat_rcv_ftm_smmu0_req_cnt0; + ZXIC_UINT32 stat_rcv_ftm_smmu0_req_cnt1; + ZXIC_UINT32 stat_rcv_etm_smmu0_req_cnt0; + ZXIC_UINT32 stat_rcv_etm_smmu0_req_cnt1; + ZXIC_UINT32 ppu_no_exist_opcd_ex_cnt[DPP_STAT_PPU_MEX_NUM]; + ZXIC_UINT32 stat_rcv_tm_eram_cpu_rsp_cnt; + ZXIC_UINT32 cpu_rd_eram_req_cnt; + ZXIC_UINT32 cpu_wr_eram_req_cnt; + ZXIC_UINT32 tm_stat_ddr_cpu_rsp_cnt; + ZXIC_UINT32 cpu_rd_ddr_req_cnt; + ZXIC_UINT32 cpu_wr_ddr_req_cnt; +}DPP_STAT_DBG_CNT_T; + +#endif + +/***********************************************************/ +/** 获取ppu统计片内深度 +* @param dev_id 设备号 +* @param p_ppu_eram_depth ppu统计片内深度 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/03/31 +************************************************************/ +DPP_STATUS dpp_stat_ppu_eram_depth_get(DPP_DEV_T *dev, + ZXIC_UINT32* p_ppu_eram_depth); + + +/***********************************************************/ +/** 获取ppu统计 ERAM基地址 +* @param dev_id 设备号 +* @param p_ppu_eram_baddr ppu统计片内基地址 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/03/31 +************************************************************/ +DPP_STATUS dpp_stat_ppu_eram_baddr_get(DPP_DEV_T *dev, + ZXIC_UINT32* p_ppu_eram_baddr); + +/***********************************************************/ +/** 获取ppu统计 ddr基地址 +* @param dev_id 设备号 +* @param p_ppu_ddr_baddr ppu统计片外基地址 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/03/31 +************************************************************/ +DPP_STATUS dpp_stat_ppu_ddr_baddr_get(DPP_DEV_T *dev, + ZXIC_UINT32* p_ppu_ddr_baddr); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/table/sdt/dpp_sdt.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/table/sdt/dpp_sdt.h new file mode 100755 index 0000000..4bfd745 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/table/sdt/dpp_sdt.h @@ -0,0 +1,164 @@ +/********************************************************************* +* 版权所有 (C)2013, 深圳市中兴通讯股份有限公司。 +* +* 文件名称： +* 文件标识： +* 内容摘要: +* 其它说明: +* +* +* 当前版本： +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT : 100% +* 作 者： 王春雷10111187 +* 完成日期： 2013-9-2 +********************************************************************/ + +#ifndef _DPP_SDT_H_ +#define _DPP_SDT_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "dpp_ppu.h" + +/** SDT属性表高32bit中各比特字段的位宽定义*/ +#define DPP_SDT_H_TBL_TYPE_BT_POS (29) +#define DPP_SDT_H_TBL_TYPE_BT_LEN (3) + +#define DPP_SDT_H_ERAM_MODE_BT_POS (26) +#define DPP_SDT_H_ERAM_MODE_BT_LEN (3) +#define DPP_SDT_H_ERAM_BASE_ADDR_BT_POS (7) +#define DPP_SDT_H_ERAM_BASE_ADDR_BT_LEN (19) +#define DPP_SDT_L_ERAM_TABLE_DEPTH_BT_POS (1) +#define DPP_SDT_L_ERAM_TABLE_DEPTH_BT_LEN (22) + +#define DPP_SDT_H_DDR3_BASE_ADDR_BT_POS (9) +#define DPP_SDT_H_DDR3_BASE_ADDR_BT_LEN (20) +#define DPP_SDT_H_DDR3_SHARE_TYPE_BT_POS (7) +#define DPP_SDT_H_DDR3_SHARE_TYPE_BT_LEN (2) +#define DPP_SDT_H_DDR3_RW_LEN_BT_POS (5) +#define DPP_SDT_H_DDR3_RW_LEN_BT_LEN (2) +#define DPP_SDT_H_DDR3_SDT_NUM_BT_POS (0) +#define DPP_SDT_H_DDR3_SDT_NUM_BT_LEN (5) +#define DPP_SDT_L_DDR3_SDT_NUM_BT_POS (29) +#define DPP_SDT_L_DDR3_SDT_NUM_BT_LEN (3) +#define DPP_SDT_L_DDR3_ECC_EN_BT_POS (28) +#define DPP_SDT_L_DDR3_ECC_EN_BT_LEN (1) + +#define DPP_SDT_H_HASH_ID_BT_POS (27) +#define DPP_SDT_H_HASH_ID_BT_LEN (2) +#define DPP_SDT_H_HASH_TABLE_WIDTH_BT_POS (25) +#define DPP_SDT_H_HASH_TABLE_WIDTH_BT_LEN (2) +#define DPP_SDT_H_HASH_KEY_SIZE_BT_POS (19) +#define DPP_SDT_H_HASH_KEY_SIZE_BT_LEN (6) +#define DPP_SDT_H_HASH_TABLE_ID_BT_POS (14) +#define DPP_SDT_H_HASH_TABLE_ID_BT_LEN (5) +#define DPP_SDT_H_LEARN_EN_BT_POS (13) +#define DPP_SDT_H_LEARN_EN_BT_LEN (1) +#define DPP_SDT_H_KEEP_ALIVE_BT_POS (12) +#define DPP_SDT_H_KEEP_ALIVE_BT_LEN (1) +#define DPP_SDT_H_KEEP_ALIVE_BADDR_BT_POS (0) +#define DPP_SDT_H_KEEP_ALIVE_BADDR_BT_LEN (12) +#define DPP_SDT_L_KEEP_ALIVE_BADDR_BT_POS (25) +#define DPP_SDT_L_KEEP_ALIVE_BADDR_BT_LEN (7) +#define DPP_SDT_L_RSP_MODE_BT_POS (23) +#define DPP_SDT_L_RSP_MODE_BT_LEN (2) + +#define DPP_SDT_H_LPM_V46ID_BT_POS (28) +#define DPP_SDT_H_LPM_V46ID_BT_LEN (1) +#define DPP_SDT_H_LPM_RSP_MODE_BT_POS (0) +#define DPP_SDT_H_LPM_RSP_MODE_BT_LEN (2) +#define DPP_SDT_L_LPM_TABLE_DEPTH_BT_POS (1) +#define DPP_SDT_L_LPM_TABLE_DEPTH_BT_LEN (30) + +#define DPP_SDT_H_ETCAM_ID_BT_POS (27) +#define DPP_SDT_H_ETCAM_ID_BT_LEN (1) +#define DPP_SDT_H_ETCAM_KEY_MODE_BT_POS (25) +#define DPP_SDT_H_ETCAM_KEY_MODE_BT_LEN (2) +#define DPP_SDT_H_ETCAM_TABLE_ID_BT_POS (21) +#define DPP_SDT_H_ETCAM_TABLE_ID_BT_LEN (4) +#define DPP_SDT_H_ETCAM_NOAS_RSP_MODE_BT_POS (19) +#define DPP_SDT_H_ETCAM_NOAS_RSP_MODE_BT_LEN (2) +#define DPP_SDT_H_ETCAM_AS_EN_BT_POS (18) +#define DPP_SDT_H_ETCAM_AS_EN_BT_LEN (1) +#define DPP_SDT_H_ETCAM_AS_ERAM_BADDR_BT_POS (0) +#define DPP_SDT_H_ETCAM_AS_ERAM_BADDR_BT_LEN (18) +#define DPP_SDT_L_ETCAM_AS_ERAM_BADDR_BT_POS (31) +#define DPP_SDT_L_ETCAM_AS_ERAM_BADDR_BT_LEN (1) +#define DPP_SDT_L_ETCAM_AS_RSP_MODE_BT_POS (28) +#define DPP_SDT_L_ETCAM_AS_RSP_MODE_BT_LEN (3) +#define DPP_SDT_L_ETCAM_TABLE_DEPTH_BT_POS (1) +#define DPP_SDT_L_ETCAM_TABLE_DEPTH_BT_LEN (20) + +#define DPP_SDT_L_CLUTCH_EN_BT_POS (0) +#define DPP_SDT_L_CLUTCH_EN_BT_LEN (1) + +#define DPP_SDT_TBL_TYPE_NUM (8) + +/***********************************************************/ +/** 解析从硬件读取的64bit SDT属性 +* @param sdt_hig32 硬件表中存储的SDT属性高32bit +* @param sdt_low32 硬件表中存储的SDT属性低32bit +* @param p_sdt_info 解析之后的SDT属性，根据SDT属性中的table_type确定此ZXIC_VOID型指针对应的数据结构, 包括: \n +* DPP_SDTTBL_ERAM_T、DPP_SDTTBL_DDR3_T、DPP_SDTTBL_HASH_T、DPP_SDTTBL_LPM_T、\n +* DPP_SDTTBL_ETCAM_T、DPP_SDTTBL_PORTTBL_T。 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author 王春雷 @date 2015/07/13 +************************************************************/ +DPP_STATUS dpp_sdt_tbl_data_parser(ZXIC_UINT32 dev_id, ZXIC_UINT32 sdt_hig32, ZXIC_UINT32 sdt_low32, ZXIC_VOID *p_sdt_info); + +/***********************************************************/ +/** 从软件缓存中获取table data信息 +* @param dev_id 设备号 +* @param sdt_no 业务表对应的sdt号,0-255 +* @param p_sdt_data sdt表信息 +* +* @return +* @remark 无 +* @see +* @author lim @date 2020/04/16 +************************************************************/ +DPP_STATUS dpp_sdt_tbl_data_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 sdt_no, DPP_SDT_TBL_DATA_T *p_sdt_data); + +/***********************************************************/ +/** 将sdt信息保存在软件缓存中 +* @param dev_id 设备号 +* @param sdt_no 业务表对应的sdt号 +* @param table_type SDT属性中的表类型，取值参考DPP_SDT_TABLE_TYPE_E的定义 +* @param p_sdt_info 写入的SDT表信息。 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author lim @date 2020/04/16 +************************************************************/ +DPP_STATUS dpp_soft_sdt_tbl_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 sdt_no, + ZXIC_UINT32 table_type, + DPP_SDT_TBL_DATA_T *p_sdt_info); + +/***********************************************************/ +/** 从软件缓存中获取sdt信息 +* @param device_id 设备号 +* @param sdt_no 业务表对应的sdt号 +* @param p_sdt_info 写入的SDT属性。由table_type确定此ZXIC_VOID型指针对应的数据结构, 包括: \n +* DPP_SDTTBL_ERAM_T、DPP_SDTTBL_DDR_T、DPP_SDTTBL_HASH_T、DPP_SDTTBL_LPM_T、 +* DPP_SDTTBL_ETCAM_T。 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author lim @date 2020/04/16 +************************************************************/ +DPP_STATUS dpp_soft_sdt_tbl_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 sdt_no, ZXIC_VOID *p_sdt_info); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/table/sdt/dpp_sdt_def.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/table/sdt/dpp_sdt_def.h new file mode 100755 index 0000000..4b8e895 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/table/sdt/dpp_sdt_def.h @@ -0,0 +1,143 @@ +/********************************************************************* +* 版权所有 (C)2001, 深圳市中兴通讯股份有限公司。 +* +* 文件名称： +* 文件标识： +* 内容摘要: +* 其它说明: +* +* +* 当前版本： +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT : 100% +* 作 者： 石金锋 +* 完成日期：2012-09-21 +********************************************************************/ +#ifndef _DPP_SDT_DEF_H_ +#define _DPP_SDT_DEF_H_ + + +typedef enum dpp_tbl_type_e +{ + TblType_Invalid = 0, + TblType_Eram128 = 1, + TblType_DDR3 = 2, + TblType_HASH = 3, + TblType_LPM = 4, + TblType_eTcam = 5, + TblType_PORTTBL = 6, + TblType_MAX = 7 +} DPP_TBL_TYPE_E; + +typedef enum dpp_eram128_mode_e +{ + Eram128Mode_1BITS = 0, + Eram128Mode_32BITS = 1, + Eram128Mode_64BITS = 2, + Eram128Mode_128BITS = 3, + Eram128Mode_2BITS = 4,/** Add By LiuShuo @ 2016年2月24日15:56:39*/ + Eram128Mode_4BITS = 5, + Eram128Mode_8BITS = 6, + Eram128Mode_16BITS = 7, + Eram128Mode_MAX = 8 +} DPP_ERAM128_MODE_E; + +typedef enum dpp_dde3_mode_e +{ + DDR3Mode_128BITS = 0, + DDR3Mode_256BITS = 1, + DDR3Mode_512BITS = 2, + DDR3Mode_MAX = 3 +} DPP_DDR3_MODE_E; +/** DDR3 共享模式 */ +typedef enum dpp_ddr3_share_mode_e +{ + DDR_SHARE_MODE_NONE = 0, /** <@brief 不共享模式 */ + DDR_SHARE_MODE_1_2 = 1, /** <@brief 1/2共享模式 */ + DDR_SHARE_MODE_1_4 = 2, /** <@brief 1/4共享模式 */ + DDR_SHARE_MODE_1_8 = 3, /** <@brief 1/8共享模式 */ + DDR_SHARE_MODE_MAX = 4, /** <@brief 不可用 */ +} DPP_DDR3_SHARE_MODE_E; + +typedef enum dpp_ddr3_copy_type_e +{ + DDR3_COPY_TYPE_INN_0 = 0, + DDR3_COPY_TYPE_INN_2 = 1, + DDR3_COPY_TYPE_INN_4 = 2, + DDR3_COPY_TYPE_INN_8 = 3, + DDR3_COPY_TYPE_OUT_0 = 4, + DDR3_COPY_TYPE_OUT_1 = 5, + DDR3_COPY_TYPE_OUT_2 = 7, +} DPP_DDR3_COPY_TYPE_E; + +/** 仿真器表项操作特殊定制，仅用于操作仿真器设备*/ +#define HASH_SIM_ADD_ADDR (0xFFFFFFF4) +#define HASH_SIM_DEL_ADDR (0xFFFFFFF8) +#define LPM_SIM_ADD_ADDR (0xFFFFFFE4) +#define LPM_SIM_DEL_ADDR (0xFFFFFFE8) +#define ETCAM_SIM_ADD_ADDR (0xFFFFFFD4) +#define ETCAM_SIM_DEL_ADDR (0xFFFFFFD8) + +typedef struct dpp_sdt_smmu0_t +{ + ZXIC_UINT32 *p_data; /*输入,输出数据地址 */ + ZXIC_UINT32 wr_rd_flag; /*0: Write 1: Read */ + ZXIC_UINT32 tbl_index; /*表项索引 */ + ZXIC_UINT32 tbl_base_addr; /*表项基地址 */ + ZXIC_UINT32 mode; /*参见DPP_ERAM128_MODE_E */ + ZXIC_UINT32 tbl_depth; /*表项的深度，越界检测 */ +} DPP_SDT_SMMU0_T; + +typedef struct dpp_sdt_smmu1_t +{ + ZXIC_UINT32 *p_data; /*输入,输出数据地址 */ + ZXIC_UINT32 crc_chk_en; /*Crc效验使能 */ + ZXIC_UINT32 wr_rd_flag; /*0: Write 1: Read */ + ZXIC_UINT32 ddr_share_type; /*参见DPP_DDR3_SHARE_MODE_E */ + ZXIC_UINT32 tbl_index; /*表项索引 */ + ZXIC_UINT32 tbl_base_addr; /*DDR3片内基地址 */ + ZXIC_UINT32 ddr_mode; /*参见DPP_DDR3_MODE_E */ + ZXIC_UINT32 sdt_no; /*SDT表号 */ +} DPP_SDT_SMMU1_T; + +typedef struct dpp_sdt_hash_t +{ + ZXIC_UINT32 id; /* hash引擎号 */ + ZXIC_UINT32 tbl_id; /* hash业务号 */ + ZXIC_UINT32 *p_data; + ZXIC_UINT32 addr; + ZXIC_UINT32 length; /* 数据长度，以4字节为单位 */ + ZXIC_UINT32 key_size; /* 键值长度，以字节为单位 */ + ZXIC_UINT32 key_type; /* 表项存储位宽 */ + ZXIC_UINT32 rsp_mode; + ZXIC_UINT32 wr_rd_flag; /* 0: Write 1: Read */ +} DPP_SDT_HASH_T; + +typedef struct dpp_sdt_lpm_t +{ + ZXIC_UINT32 *p_data; + ZXIC_UINT32 addr; + ZXIC_UINT32 length; /* 数据长度，以4字节为单位 */ + ZXIC_UINT32 wr_rd_flag; /* 0: Write 1: Read */ + ZXIC_UINT32 v46_flag; /* 1:ipv4, 0:ipv6 */ +} DPP_SDT_LPM_T; + +typedef struct dpp_sdt_etcam_t +{ + ZXIC_UINT32 id; /* etcam号 */ + ZXIC_UINT32 tbl_id; /* 业务号 */ + ZXIC_UINT32 *p_data; + ZXIC_UINT32 length; /* 数据长度，以4字节为单位 */ + ZXIC_UINT32 addr; + ZXIC_UINT32 wr_rd_flag; /* 0: Write 1: Read */ + ZXIC_UINT32 key_mode; + ZXIC_UINT32 rsp_mode; + ZXIC_UINT32 as_en; + ZXIC_UINT32 as_eram_baddr; + ZXIC_UINT32 as_rsp_mode; +} DPP_SDT_ETCAM_T; + +#endif + + + diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/table/sdt/dpp_sdt_mgr.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/table/sdt/dpp_sdt_mgr.h new file mode 100755 index 0000000..fa7f714 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/table/sdt/dpp_sdt_mgr.h @@ -0,0 +1,147 @@ +/********************************************************************* +* 版权所有 (C)2013, 深圳市中兴通讯股份有限公司。 +* +* 文件名称： +* 文件标识： +* 内容摘要: +* 其它说明: +* +* +* 当前版本： +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT : 100% +* 作 者： 王春雷10111187 +* 完成日期： 2013-9-2 +********************************************************************/ + +#ifndef _DPP_SDT_MGR_H_ +#define _DPP_SDT_MGR_H_ + +#include "dpp_sdt_def.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define DPP_SDT_CFG_LEN (2) + +#define DPP_SDT_VALID (1) +#define DPP_SDT_INVALID (0) + +#define DPP_SDT_WRITE (0) +#define DPP_SDT_READ (1) + +#define DPP_SDT_MAX_BUFF (18) + +#define DPP_TBL_DATA_MAX (50) + +typedef enum dpp_opr_type_e +{ + DPP_TABLE_UPDATE = 0, + DPP_TABLE_DELETE = 1, + DPP_TABLE_SEARCH = 2, +} DPP_OPR_TYEP_E; + +/** eRam SDT变量获取中间结构 */ +typedef struct dpp_eram128_params_t +{ + ZXIC_UINT32 tbl_base_addr; /** 表项基地址，128bit为单位 */ + DPP_ERAM128_MODE_E eram128_mode; /** 表项位宽模式 */ + ZXIC_UINT32 tbl_depth; /** 表项深度值。越界检测 */ + ZXIC_UINT32 count; /** 表示写入数据的长度，以32bit为单位*/ +} DPP_ERAM128_PARAMS_T; + +/** DDR3 SDT变量获取中间结构 */ +typedef struct dpp_ddr3_params_t +{ + ZXIC_UINT32 base_addr; /** 表项基地址，以4K*128bit 为单位 */ + ZXIC_UINT32 crc_check; /** ECC校验使能位 */ + DPP_DDR3_MODE_E ddr3_mode; /** DDR位宽模式 */ + ZXIC_UINT32 tbl_share_mode; /** bank 共享模式 */ + ZXIC_UINT32 wr_rd_count; /** 表示写入数据的长度，以32bit为单位 */ +} DPP_DDR3_PARAMS_T; + +typedef enum dpp_hash_key_width_e +{ + HashKey_Invalid = 0, + HashKey_128b, + HashKey_256b, + HashKey_512b, + HashKey_MAX +} DPP_HASH_KEY_WIDTH_E; + +/** HASH SDT变量获取中间结构 */ +typedef struct dpp_hash_params_t +{ + ZXIC_UINT8 hash_id; /** hash引擎号 */ + ZXIC_UINT8 key_tbl_width; /** hash表项存储位宽, */ + ZXIC_UINT8 key_size; /** hash键值长度,以8bit为单位，1~48 */ + ZXIC_UINT8 table_id; /** hash逻辑表号 */ + ZXIC_UINT8 rsp_mode; /** 返回数据宽度 0:32 1:64 2:128 3:256*/ +} DPP_HASH_PARAMS_T; + +typedef struct dpp_lpm_params_t +{ + ZXIC_UINT8 v46_flag; /* 1:Ipv4, 0:Ipv6 */ + ZXIC_UINT8 count; /* 以4字节为单位 */ + ZXIC_UINT8 pad[2]; /* 字节对齐 */ +} DPP_LPM_PARAMS_T; + +typedef struct dpp_etcam_params_t +{ + ZXIC_UINT8 id; + ZXIC_UINT8 table_id; + ZXIC_UINT8 key_mode; + ZXIC_UINT8 rsp_mode; + ZXIC_UINT8 as_en; + ZXIC_UINT32 as_baddr; + ZXIC_UINT8 as_rsp_mode; +} DPP_ETCAM_PARAMS_T; + +typedef ZXIC_UINT32 (*dpp_sdt_mgr_smmu0_mux_fun_ptr)(ZXIC_UINT32 dev_id, DPP_SDT_SMMU0_T *p_sdt_smmu0); +typedef ZXIC_UINT32 (*dpp_sdt_mgr_smmu1_mux_fun_ptr)(ZXIC_UINT32 dev_id, DPP_SDT_SMMU1_T *p_sdt_smmu1); +typedef ZXIC_UINT32 (*dpp_sdt_mgr_hash_mux_fun_ptr)(ZXIC_UINT32 dev_id, DPP_SDT_HASH_T *p_sdt_hash); +typedef ZXIC_UINT32 (*dpp_sdt_mgr_lpm_mux_fun_ptr)(ZXIC_UINT32 dev_id, DPP_SDT_LPM_T *p_sdt_lpm); +typedef ZXIC_UINT32 (*dpp_sdt_mgr_etcam_mux_fun_ptr)(ZXIC_UINT32 dev_id, DPP_SDT_ETCAM_T *p_sdt_etcam); + +typedef struct dpp_sdt_item_t +{ + ZXIC_UINT32 valid; + ZXIC_UINT32 table_cfg[DPP_SDT_CFG_LEN]; +} DPP_SDT_ITEM_T; + +typedef struct dpp_sdt_soft_table_t +{ + ZXIC_UINT32 device_id; + DPP_SDT_ITEM_T sdt_array[DPP_DEV_SDT_ID_MAX]; +} DPP_SDT_SOFT_TABLE_T; + +typedef struct dpp_sdt_mgr_t +{ + ZXIC_UINT32 channel_num; + ZXIC_UINT32 is_init; + DPP_SDT_SOFT_TABLE_T* sdt_tbl_array[DPP_DEV_CHANNEL_MAX]; + dpp_sdt_mgr_smmu0_mux_fun_ptr p_sdt_mgr_smmu0_mux; + dpp_sdt_mgr_smmu1_mux_fun_ptr p_sdt_mgr_smmu1_mux; + dpp_sdt_mgr_hash_mux_fun_ptr p_sdt_mgr_hash_mux; + dpp_sdt_mgr_lpm_mux_fun_ptr p_sdt_mgr_lpm_mux; + dpp_sdt_mgr_etcam_mux_fun_ptr p_sdt_mgr_etcam_mux; +} DPP_SDT_MGR_T; + +ZXIC_UINT32 dpp_sdt_mgr_init(ZXIC_VOID); +ZXIC_UINT32 dpp_sdt_mgr_create(ZXIC_UINT32 dev_id); +ZXIC_UINT32 dpp_sdt_mgr_destroy(ZXIC_UINT32 dev_id); + +DPP_STATUS dpp_sdt_mgr_sdt_item_add(ZXIC_UINT32 dev_id, ZXIC_UINT32 sdt_no, ZXIC_UINT32 sdt_hig32, ZXIC_UINT32 sdt_low32); +DPP_STATUS dpp_sdt_mgr_sdt_item_srh(ZXIC_UINT32 dev_id, ZXIC_UINT32 sdt_no, ZXIC_UINT32 *p_sdt_hig32, ZXIC_UINT32 *p_sdt_low32); +DPP_STATUS dpp_sdt_mgr_sdt_item_del(ZXIC_UINT32 dev_id, ZXIC_UINT32 sdt_no); + +ZXIC_UINT32 dpp_sdt_mgr_get_as_table_en(ZXIC_UINT32 *table_cfg, ZXIC_UINT32 *p_as_en); +ZXIC_UINT32 dpp_sdt_mgr_get_as_table_type(ZXIC_UINT32 *table_cfg, DPP_TBL_TYPE_E *p_as_type); +ZXIC_UINT32 dpp_sdt_mgr_get_ddr3_page(ZXIC_UINT32 copy_type, ZXIC_UINT32 copy_position, ZXIC_UINT32 *p_page); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/table/se/dpp_acl.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/table/se/dpp_acl.h new file mode 100755 index 0000000..b8ae672 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/table/se/dpp_acl.h @@ -0,0 +1,103 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_acl.h +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : 王春雷 +* 完成日期 : 2014/12/17 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ +#ifndef _DPP_ACL_H_ +#define _DPP_ACL_H_ + +#include "dpp_se_api.h" + +#define DPP_ACL_TBL_ID_MIN (0) +#define DPP_ACL_TBL_ID_MAX (7) +#define DPP_ACL_ETCAM_ID_MIN (0) +#define DPP_ACL_ETCAM_ID_MAX (0) + +#define DPP_ACL_ENTRY_MAX_GET(key_mode, block_num) \ + ((block_num) * DPP_ETCAM_RAM_DEPTH * (1U<<(key_mode))) + +#define DPP_ACL_AS_RSLT_SIZE_GET(mode) \ + (((mode)==DPP_ACL_AS_MODE_128b)?(128/8):(((mode)==DPP_ACL_AS_MODE_64b)?(64/8):(((mode)==DPP_ACL_AS_MODE_32b)?\ + (32/8):(((mode)==DPP_ACL_AS_MODE_16b)?(16/8):(0))))) + +/** 仅内部调试接口使用*/ +#define DPP_ACL_AS_RSLT_SIZE_GET_EX(mode) (2U<<(mode)) + + +/** ACL关联查找结果表位宽模式，仅调试用*/ +typedef enum dpp_acl_as_mode_ex_e +{ + DPP_ACL_AS_MODE_EX_64b = 1, /**< @brief 64bit结果位宽*/ + DPP_ACL_AS_MODE_EX_128b = 2, /**< @brief 128bit结果位宽*/ + DPP_ACL_AS_MODE_EX_256b = 3, /**< @brief 256bit结果位宽，仅当关联结果表为DDR时有效*/ + DPP_ACL_AS_MODE_EX_INVALID, +}DPP_ACL_AS_MODE_EX_E; + +/***********************************************************/ +/** 初始化ACL公共管理数据结构 +* @param p_acl_cfg ACL公共管理数据结构指针 +* @param p_client 用户自定义数据指针，目前仅为传入dev_id的值 +* @param flags ACL初始化使能标志，详见DPP_ACL_FLAG_ETCAM0_EN等的定义 +* @param p_as_wrt_fun 关联结果G从布s表回调函数指针 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author wcl @date 2015/05/20 +************************************************************/ +DPP_STATUS dpp_acl_cfg_init(DPP_ACL_CFG_T *p_acl_cfg, + ZXIC_VOID *p_client, + ZXIC_UINT32 flags, + ACL_AS_RSLT_WRT_FUNCTION p_as_wrt_fun); + +/***********************************************************/ +/** 获取ACL公共管理数据结构 +* @param p_acl_cfg ACL公共管理配置结构指针 +* +* @return DPP_OK-成功，DPP_ERR-失败 +************************************************************/ +DPP_STATUS dpp_acl_cfg_get(DPP_ACL_CFG_EX_T **p_acl_cfg); + +/***********************************************************/ +/** 初始化ACL业务表属G? +* @param p_acl_cfg ACL公共管理数据结构指针 +* @param table_id 业务表号，取值范围0~15 +* @param as_enable 是否使能关联结果查找，0-不使能，1-使能 +* @param entry_num 最大条目数 +* @param key_mode 键值位宽模式，取值参照DPP_ACL_KEY_MODE_E的定义 +* @param as_mode 关联结果位宽模式，取值参照DPP_ACL_AS_MODE_E的定义 +* @param block_num 分配给当前业务表号的block数目 +* @param p_block_idx 分配给当前业务表号的block编号数组 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author wcl @date 2015/05/20 +************************************************************/ +DPP_STATUS dpp_acl_tbl_init(DPP_ACL_CFG_T *p_acl_cfg, + ZXIC_UINT32 table_id, + ZXIC_UINT32 as_enable, + ZXIC_UINT32 entry_num, + DPP_ACL_KEY_MODE_E key_mode, + DPP_ACL_AS_MODE_E as_mode, + ZXIC_UINT32 block_num, + ZXIC_UINT32 *p_block_idx); + +DPP_STATUS dpp_acl_hdw_addr_get(DPP_ACL_TBL_CFG_T *p_tbl_cfg, ZXIC_UINT32 handle, ZXIC_UINT32 *p_block_idx, ZXIC_UINT32 *p_addr, ZXIC_UINT32 *p_wr_mask); +#endif + + + diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/table/se/dpp_dtb_table.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/table/se/dpp_dtb_table.h new file mode 100644 index 0000000..e5f4ac1 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/table/se/dpp_dtb_table.h @@ -0,0 +1,720 @@ +#ifndef _DPP_DTB_TABLE_H_ +#define _DPP_DTB_TABLE_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "dpp_dev.h" +#include "dpp_hash.h" +#include "dpp_etcam.h" +#include "dpp_dtb_table_api.h" + +#define DISABLE (0) +#define ENABLE (1) + +#define DTB_DOWN_TABLE_CMD (0) +#define DTB_DUMP_TABLE_CMD (1) + +#define DTB_QUEUE_MAX (128) +#define DTB_QUEUE_ELEMENT_MAX (32) +#define DTB_DATA_SIZE_BIT (16*1024*8) +#define DPP_DTB_TABLE_DATA_BUFF_SIZE (1024*16) +#define DPP_DTB_TABLE_DUMP_INFO_BUFF_SIZE (1024*4) +#define DTB_TABLE_CMD_SIZE_BIT (128) +#define DTB_TABLE_CMD_SIZE_BYTE (16) +#define DTB_ERAM_DATA_SIZE_1b (128) +#define DTB_ERAM_DATA_SIZE_64b (128) +#define DTB_ERAM_DATA_SIZE_128b (256) +#define DTB_ERAM_ENTRY_CNT_MAX_1b (DTB_DATA_SIZE_BIT / DTB_ERAM_DATA_SIZE_1b) +#define DTB_ERAM_ENTRY_CNT_MAX_64b (DTB_DATA_SIZE_BIT / DTB_ERAM_DATA_SIZE_64b) +#define DTB_ERAM_ENTRY_CNT_MAX_128b (DTB_DATA_SIZE_BIT / DTB_ERAM_DATA_SIZE_128b) +#define DTB_ZCAM_LEN_SIZE (5) /*单位16字节*/ +#define DTB_ETCAM_LEN_SIZE (6) /*单位16字节*/ +#define DTB_MC_HASH_LEN_SIZE (5) /*单位16字节*/ +#define DTB_ZCAM_DATA_SIZE (ZXIC_UINT32)(64) +#define DTB_DMUP_DATA_MAX (ZXIC_UINT32)(4*1024*1024) +#define DTB_DUMP_DDR_ITEMS_MAX (0x10000) + +#define DTB_SDT_DUMP_SIZE (0x400000) //4MB + +#define DTB_TABLE_VALID (1) +#define DTB_LEN_POS_SETP (16) /*DTB len 单位16字节 */ + +#define LPM_IPV4 (1) +#define LPM_IPV6 (0) +#define LPM_ENABLE (1) +#define LPM_DISABLE (0) + +#define DTB_TABLE_MODE_ERAM (0) +#define DTB_TABLE_MODE_DDR (1) +#define DTB_TABLE_MODE_ZCAM (2) +#define DTB_TABLE_MODE_ETCAM (3) +#define DTB_TABLE_MODE_MC_HASH (4) + +#define DTB_DUMP_MODE_ERAM (0) +#define DTB_DUMP_MODE_DDR (1) +#define DTB_DUMP_MODE_ZCAM (2) +#define DTB_DUMP_MODE_ETCAM (3) + +#define DTB_ITEM_ADD_OR_UPDATE (0) +#define DTB_ITEM_DELETE (1) + +/* DTB 表信息管理 */ +/*表顺序与g_dpp_dtb_table_info中顺序一致*/ +typedef enum dpp_dtb_table_info_e +{ + DTB_TABLE_DDR = 0, + DTB_TABLE_ERAM_1 = 1, + DTB_TABLE_ERAM_64 = 2, + DTB_TABLE_ERAM_128 = 3, + DTB_TABLE_ZCAM = 4, + DTB_TABLE_ETCAM = 5, + DTB_TABLE_MC_HASH = 6, + DTB_TABLE_ENUM_MAX +}DPP_DTB_TABLE_INFO_E; + +typedef enum dpp_dtb_dump_info_e +{ + DTB_DUMP_ERAM = 0, + DTB_DUMP_DDR = 1, + DTB_DUMP_ZCAM = 2, + DTB_DUMP_ETCAM = 3, + DTB_DUMP_ENUM_MAX +}DPP_DTB_DUMP_INFO_E; + +typedef enum dpp_dtb_dump_zcam_width_e +{ + DTB_DUMP_ZCAM_128b = 0, + DTB_DUMP_ZCAM_256b = 1, + DTB_DUMP_ZCAM_512b = 2, + DTB_DUMP_ZCAM_RSV = 3, +}DPP_DTB_DUMP_ZCAM_WIDTH_E; + +typedef enum dpp_dtb_dump_etcam_width_e +{ + DTB_DUMP_ETCAM_80b = 0, + DTB_DUMP_ETCAM_160b = 1, + DTB_DUMP_ETCAM_320b = 2, + DTB_DUMP_ETCAM_640b = 3, + DTB_DUMP_ETCAM_MAX +}DPP_DTB_DUMP_ETCAM_WIDTH_E; + +/* DTB下表格式字段定义 */ +typedef struct dpp_dtb_ddr_table_form_t +{ + ZXIC_UINT32 valid; /* 有效标识 1有效*/ + ZXIC_UINT32 type_mode; /* DDR：0x1 */ + ZXIC_UINT32 rw_len; /*数据长度 00:128 01:256 10:384 11:512*/ + ZXIC_UINT32 v46_flag; /*1：IPV4 0:IPV6*/ + ZXIC_UINT32 lpm_wr_vld; /*lpm表写有效标识*/ + ZXIC_UINT32 baddr; /*表基地址*/ + ZXIC_UINT32 ecc_en; /* ECC 使能*/ + ZXIC_UINT32 rw_addr; /*以数据宽度为单位的index*/ +}DPP_DTB_DDR_TABLE_FORM_T; + +typedef struct dpp_dtb_eram_table_form_t +{ + ZXIC_UINT32 valid; /* 有效标识 1有效*/ + ZXIC_UINT32 type_mode; /* ERAM：0x0 */ + ZXIC_UINT32 data_mode; /*数据长度 00:128 01:64 10:1*/ + ZXIC_UINT32 cpu_wr; /*CPU写使能*/ + ZXIC_UINT32 cpu_rd; /*CPU读使能*/ + ZXIC_UINT32 cpu_rd_mode; /*CPU读模式 0：读 1：读清*/ + ZXIC_UINT32 addr; /*访问eram 1bit为单位*/ + ZXIC_UINT32 data_h; /*数据高32bit*/ + ZXIC_UINT32 data_l; /*数据低32bit*/ +}DPP_DTB_ERAM_TABLE_FORM_T; + +typedef struct dpp_dtb_zcam_table_form_t +{ + ZXIC_UINT32 valid; /* 有效标识 1有效*/ + ZXIC_UINT32 type_mode; /* zcam：0x2 */ + ZXIC_UINT32 ram_reg_flag; /* ram reg 标识 */ + ZXIC_UINT32 zgroup_id; /* zgroup id */ + ZXIC_UINT32 zblock_id; /* zblock id */ + ZXIC_UINT32 zcell_id; /* zcell id */ + ZXIC_UINT32 mask; /* 掩码 */ + ZXIC_UINT32 sram_addr; /* ram地址 */ + +}DPP_DTB_ZCAM_TABLE_FORM_T; + +typedef struct dpp_dtb_etcam_table_form_t +{ + ZXIC_UINT32 valid; /* 有效标识 1有效*/ + ZXIC_UINT32 type_mode; /* etcam：0x3 */ + ZXIC_UINT32 block_sel; /*block索引 0 - 7*/ + ZXIC_UINT32 init_en; /*初始化使能 高有效*/ + ZXIC_UINT32 row_or_col_msk; /* 1 write row mask reg 0:write col mask reg*/ + ZXIC_UINT32 vben; /* enable the valid bit addressed by addr*/ + ZXIC_UINT32 reg_tcam_flag; /* 1:配置内部row_col_mask寄存器 0：读写tcam*/ + ZXIC_UINT32 uload; /*使能标识删除对应addr的表项条目，（80bit为单位，含义与wr_mode一一对应）*/ + ZXIC_UINT32 rd_wr; /*读写标志 0写 1读*/ + ZXIC_UINT32 wr_mode; /*写入掩码，最高8bit，对应bit为1代表对应的80bit的数据*/ + ZXIC_UINT32 data_or_mask; /*数据或掩码标志 1：写x(data),0:写y(mask)*/ + ZXIC_UINT32 addr; /*etcam地址（0-511）*/ + ZXIC_UINT32 vbit; /*valid bit input*/ + +}DPP_DTB_ETCAM_TABLE_FORM_T; + +typedef struct dpp_dtb_mc_hash_table_form_t +{ + ZXIC_UINT32 valid; /* 有效标识 1有效 */ + ZXIC_UINT32 type_mode; /* 微码写hash 0x4 */ + ZXIC_UINT32 std_h; /* sdt信息高32bit */ + ZXIC_UINT32 std_l; /* sdt信息低32bit */ +}DPP_DTB_MC_HASH_TABLE_FORM_T; + +/* DTB DUMP表格式 */ +typedef struct dpp_dtb_eram_dump_form_t +{ + ZXIC_UINT32 valid; /* 有效标识 1有效 */ + ZXIC_UINT32 up_type; /* 00:eram */ + ZXIC_UINT32 base_addr; /* 128bit为单位 */ + ZXIC_UINT32 tb_depth; /* 表项深度，每条条目位宽128bit */ + ZXIC_UINT32 tb_dst_addr_h; /* 数据目的地址高32bit */ + ZXIC_UINT32 tb_dst_addr_l; /* 数据目的地址低32bit */ + +}DPP_DTB_ERAM_DUMP_FORM_T; + +typedef struct dpp_dtb_ddr_dump_form_t +{ + ZXIC_UINT32 valid; + ZXIC_UINT32 up_type; /* 01:ddr */ + ZXIC_UINT32 base_addr; /* 128bit为单位 */ + ZXIC_UINT32 tb_depth; /* 表项深度，每条条目位宽512bit */ + ZXIC_UINT32 tb_dst_addr_h; + ZXIC_UINT32 tb_dst_addr_l; + +}DPP_DTB_DDR_DUMP_FORM_T; + +typedef struct dpp_dtb_zcam_dump_form_t +{ + ZXIC_UINT32 valid; + ZXIC_UINT32 up_type; /* 10:zcam */ + ZXIC_UINT32 zgroup_id; /* */ + ZXIC_UINT32 zblock_id; /* */ + ZXIC_UINT32 ram_reg_flag; + ZXIC_UINT32 z_reg_cell_id; + ZXIC_UINT32 sram_addr; + ZXIC_UINT32 tb_depth; /* 表项深度 */ + ZXIC_UINT32 tb_width; /* 表项宽度 */ + ZXIC_UINT32 tb_dst_addr_h; + ZXIC_UINT32 tb_dst_addr_l; + + +}DPP_DTB_ZCAM_DUMP_FORM_T; +typedef struct dpp_dtb_etcam_dump_form_t +{ + ZXIC_UINT32 valid; + ZXIC_UINT32 up_type; /* 11:etcam */ + ZXIC_UINT32 block_sel; /* block num */ + ZXIC_UINT32 addr; /* 640bit位单位 */ + ZXIC_UINT32 rd_mode; /* 读模式，共8bit，每bit控制ram中对应位置的80bit数据是否有效*/ + ZXIC_UINT32 data_or_mask; /* data：1 mask：0*/ + ZXIC_UINT32 tb_depth; /* dump出数据深度，以640bit为单位 */ + ZXIC_UINT32 tb_width; /* dump出数据宽度 00:80bit 01:160bit 10:320bit 11:640bit */ + ZXIC_UINT32 tb_dst_addr_h; /* dma地址高32bit */ + ZXIC_UINT32 tb_dst_addr_l; /* dma地址低32bit */ +}DPP_DTB_ETCAM_DUMP_FORM_T; + +typedef struct etcam_dump_info_t +{ + ZXIC_UINT32 block_sel; /* block index 0-7 */ + ZXIC_UINT32 addr; /* 单个block的RAM地址，范围0~511 640bit为单位 */ + ZXIC_UINT32 rd_mode; /* 读模式，共8bit，每bit控制ram中对应位置的80bit数据是否有效 */ + ZXIC_UINT32 data_or_mask; /* data：1 mask：0 参照DPP_ETCAM_DATA_TYPE_E定义*/ + ZXIC_UINT32 tb_depth; /* dump出表深度，以640bit为单位 */ + ZXIC_UINT32 tb_width; /* dump出数据宽度 00:80bit 01:160bit 10:320bit 11:640bit */ +}ETCAM_DUMP_INFO_T; + +/* 表信息结构 */ +typedef struct dpp_dtb_field_t +{ + ZXIC_CHAR *p_name; /* 字段名 */ + ZXIC_UINT16 lsb_pos; /* 最低比特位置，以寄存器列表为准*/ + ZXIC_UINT16 len; /* 字段长度，以比特为单位 */ +}DPP_DTB_FIELD_T; + +typedef struct dpp_dtb_table_t +{ + ZXIC_CHAR *table_type; /* 表类型名称*/ + ZXIC_UINT32 table_no; /* 表编号 */ + ZXIC_UINT32 field_num; /* 包含的字段个数 */ + DPP_DTB_FIELD_T *p_fields; /* 表格式所有字段 */ +}DPP_DTB_TABLE_T; + +typedef struct dpp_dtb_entry_t +{ + ZXIC_UINT8 *cmd; /* 命令 128bit 即 16B*/ + ZXIC_UINT8 *data; /* 数据 */ + ZXIC_UINT32 data_in_cmd_flag; /*eram 1/64 bit模式时使用,1表示data在cmd中*/ + ZXIC_UINT32 data_size; /* 数据长度，以字节为单位 */ +}DPP_DTB_ENTRY_T; + +typedef struct dpp_dtb_cmd_t +{ + ZXIC_UINT32 queue_id; /*队列id*/ + ZXIC_UINT32 dtb_phy_addr_hi32; /*dtb描述符物理地址高32bit*/ + ZXIC_UINT32 dtb_phy_addr_lo32; /*dtb描述符物理地址低32bit*/ + ZXIC_UINT32 cmd_type; /*0为流表下发命令，1为流表dump命令*/ + ZXIC_UINT32 int_enable; /* 中断使能 */ + ZXIC_UINT32 dtb_len; /* 指示配表内容或dump描述符长度，以16字节为单位 */ +}DPP_DTB_CMD_T; + + +typedef struct dpp_dtb_mc_hash_key_t +{ + ZXIC_UINT32 hash_key[16]; +}DPP_DTB_MC_HASH_KEY_T; + +typedef struct dpp_dtb_mixed_table_t +{ + ZXIC_UINT32 down_cmd_len; /**down描述符长度，字节为单位*/ + ZXIC_UINT32 dump_cmd_len; /**dump描述符长度，字节为单位*/ + ZXIC_UINT32 down_buff_offset; /**down buff 偏移，字节为单位*/ + ZXIC_UINT32 dump_buff_offset; /**dump buff 偏移，字节为单位*/ + ZXIC_UINT8 * p_down_cmd_buff; /**指向下表描述符空间，空间为16KB*/ + ZXIC_UINT8 * p_dump_cmd_buff; /**指向dump描述符空间，空间为4KB*/ +}DPP_DTB_MIXED_TABLE_T; + +typedef struct dpp_dtb_mc_hash_entry_info_t +{ + ZXIC_UINT32 delete_en; /* delete 浣胯兘 */ + ZXIC_UINT32 dma_en; /* dma 浣胯兘 */ + ZXIC_UINT32 *p_data; /*hash 鏉＄洰鎸囬拡 闀垮害512bit*/ +}DPP_DTB_MC_HASH_ENTRY_INFO_T; + +/** dtb 中断配置 +* @param int_enable 中断使能 +* +* @return +* @remark 无 +* @see +* @author cbb @date 2022/08/30 +************************************************************/ +DPP_STATUS dpp_dtb_interrupt_status_set(ZXIC_UINT32 int_enable); + +/** dtb 中断获取 +* +* @return +* @remark 无 +* @see +* @author cbb @date 2022/08/30 +************************************************************/ +ZXIC_UINT32 dpp_dtb_interrupt_status_get(ZXIC_VOID); + +/** dtb cmd 大小端设置 +* @param int_enable 中断使能 +* +* @return +* @remark 无 +* @see +* @author cbb @date 2022/08/30 +************************************************************/ +DPP_STATUS dpp_dtb_cmd_endian_status_set(ZXIC_UINT32 endian); + +/** dtb cmd 大小端获取 +* +* @return +* @remark 无 +* @see +* @author cbb @date 2022/08/30 +************************************************************/ +DPP_STATUS dpp_dtb_cmd_endian_status_get(ZXIC_VOID); + +/** dtb写smmu0中的数据，数据长度不限 +* @param dev_id 设备号 +* @param queue_id 队列号 +* @param smmu0_base_addr smmu0基地址，以128bit为单位 +* @param smmu0_wr_mode smmu0写模式，参考DPP_ERAM128_OPR_MODE_E，仅支持128bit、64bit、1bit模式 +* @param entry_num 下发的条目数 +* @param p_entry_arr 待下发表项内容结构体数组指针 +* @param element_id 返回下表使用的元素id +* @return +* @remark 无 +* @see +* @author cbb @date 2024/01/04 +************************************************************/ +DPP_STATUS dpp_dtb_smmu0_data_write(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 smmu0_base_addr, + ZXIC_UINT32 smmu0_wr_mode, + ZXIC_UINT32 entry_num, + DPP_DTB_ERAM_ENTRY_INFO_T *p_entry_arr, + ZXIC_UINT32 *element_id); + +/** dtb flush smmu0中的数据,大数据量 +* @param dev_id 设备号 +* @param queue_id 队列号 +* @param smmu0_base_addr smmu0基地址，以128bit为单位 +* @param smmu0_wr_mode smmu0写模式，参考DPP_ERAM128_OPR_MODE_E，仅支持128bit、64bit、1bit模式 +* @param start_index flush开始的条目 +* @param entry_num 下发的条目数 +* @param element_id 返回下表使用的元素id +* @return +* @remark 无 +* @see +* @author cbb @date 2024/01/04 +************************************************************/ +DPP_STATUS dpp_dtb_smmu0_flush(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 smmu0_base_addr, + ZXIC_UINT32 smmu0_wr_mode, + ZXIC_UINT32 start_index, + ZXIC_UINT32 entry_num, + ZXIC_UINT32 *element_id); + +/** dtb写eRam表 +* @param dev_id 设备号 +* @param queue_id 队列号 +* @param sdt_no eram表sdt表号 +* @param entry_cnt 下发的条目数 +* @param p_entry_arr 待下发表项内容结构体数组指针 +* @param element_id 返回下表使用的元素id +* @return +* @remark 无 +* @see +* @author cbb @date 2022/08/30 +************************************************************/ +DPP_STATUS dpp_dtb_eram_dma_write(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 sdt_no, + ZXIC_UINT32 entry_num, + DPP_DTB_ERAM_ENTRY_INFO_T *p_entry_arr, + ZXIC_UINT32 *element_id); + +/** dtb写HASH表,在插入条目时如果冲突，则对冲突条目进行记录 +* @param dev_id 设备号 +* @param queue_id 队列号 +* @param sdt_no hash表sdt表号 +* @param entry_cnt 下发的条目数 +* @param p_entry_arr 待下发表项内容结构体数组指针 +* @param element_id 返回下表使用的元素id +* @return +* @remark 无 是否是有一个写不成功就返回，还是继续进行下一个条目并记录错误的条目 +* @see +* @author cbb @date 2022/08/30 +************************************************************/ +DPP_STATUS dpp_dtb_hash_dma_insert(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 sdt_no, + ZXIC_UINT32 entry_num, + DPP_DTB_HASH_ENTRY_INFO_T *p_arr_hash_entry, + ZXIC_UINT32 *element_id); + +/** dtb删除HASH表 +* @param dev_id 设备号 +* @param queue_id 队列号 +* @param sdt_no hash表sdt表号 +* @param entry_cnt 删除的条目数 +* @param p_entry_arr 待下发表项内容结构体数组指针 +* @param element_id 返回下表使用的元素id +* @return +* @remark 无 +* @see +* @author @date 2023/03/14 +************************************************************/ +DPP_STATUS dpp_dtb_hash_dma_delete(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 sdt_no, + ZXIC_UINT32 entry_num, + DPP_DTB_HASH_ENTRY_INFO_T *p_arr_hash_entry, + ZXIC_UINT32 *element_id); + +/** dtb写ACL表 （SPECIFY模式，条目中指定handle，支持级联64bit/128bit） +* @param dev_id 设备号 +* @param queue_id 队列号 +* @param sdt_no ACL表sdt表号 +* @param entry_num 下发的条目数 +* @param p_acl_entry_arr 待下发表项内容结构体数组指针 +* @param element_id 返回下表使用的元素id +* @return +* @remark 无 是否是有一个写不成功就返回，还是继续进行下一个条目并记录错误的条目 +* @see +* @author cbb @date 2022/08/30 +************************************************************/ +DPP_STATUS dpp_dtb_acl_dma_insert(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 sdt_no, + ZXIC_UINT32 entry_num, + DPP_DTB_ACL_ENTRY_INFO_T *p_acl_entry_arr, + ZXIC_UINT32 *element_id + ); + + +/** dtb dump eram直接表表项内容 +* @param dev_id 设备号 +* @param queue_id 队列号 +* @param sdt_no eram表sdt表号 +* @param p_dump_eram_entry eram数据结构，数据已分配相应内存 +* @return +* @remark 无 +* @see +* @author cbb @date 2022/08/30 +************************************************************/ +DPP_STATUS dpp_dtb_eram_data_get(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 sdt_no, + DPP_DTB_ERAM_ENTRY_INFO_T *p_dump_eram_entry); + +/** dtb dump eram直接表表项内容 +* @param dev_id 设备号 +* @param queue_id 队列号 +* @param sdt_no eram表sdt表号 +* @param p_dump_eram_entry eram数据结构，数据已分配相应内存 +* @return +* @remark 无 +* @see +* @author cbb @date 2022/08/30 +************************************************************/ +DPP_STATUS dpp_dtb_eram_stat_data_get(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 base_addr, + ZXIC_UINT32 rd_mode, + ZXIC_UINT32 index, + ZXIC_UINT32 *p_data); + +/***********************************************************/ +/** 配置数据获取模式 +* @param srh_mode 0:软件获取 1:硬件获取 +* @return +* @remark 无 +* @see +* @author cq @date 2023/08/02 +************************************************************/ +ZXIC_VOID dpp_dtb_srh_mode_set(ZXIC_UINT32 srh_mode); + +/** 获取查找方式 +* @param +* @return +* @remark 无 +* @see +* @author cq @date 2023/08/02 +************************************************************/ +ZXIC_UINT32 dpp_dtb_srh_mode_get(ZXIC_VOID); + +/** 根据键值查找hash表 +* @param dev_id 设备号，支持多芯片 +* @param queue_id 队列id +* @param sdt_no 0~255 +* @param p_dtb_hash_entry 出参，返回描述符信息 +* @return +* @remark 无 +* @see +* @author cq @date 2023/08/02 +************************************************************/ + +ZXIC_UINT32 dpp_dtb_hash_data_get(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 sdt_no, + DPP_DTB_HASH_ENTRY_INFO_T *p_dtb_hash_entry); + +/** dtb 通过key和mask获取ACL表级联结果 +* @param dev_id 设备号 +* @param queue_id 队列号 +* @param sdt_no eram表sdt表号 +* @param p_dump_acl_entry etcam 数据结构，数据已分配相应内存,需要输入key和mask +* @return +* @remark 无 +* @see +* @author cbb @date 2022/08/30 +************************************************************/ +DPP_STATUS dpp_dtb_acl_data_get(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 sdt_no, + DPP_DTB_ACL_ENTRY_INFO_T *p_dump_acl_entry); + +/** dtb etcam 数据get接口，通过handle值获取etcam数据 +* @param dev_id 设备号 +* @param queue_id 队列号 +* @param sdt_no eram表sdt表号 +* @param p_dump_acl_entry etcam 数据结构，数据已分配相应内存 +* @return +* @remark 无 +* @see +* @author cbb @date 2022/08/30 +************************************************************/ +DPP_STATUS dpp_dtb_etcam_data_get(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 sdt_no, + DPP_DTB_ACL_ENTRY_INFO_T *p_dump_acl_entry); + + +/***********************************************************/ +/** flush当前hash引擎占用的ZCAM空间 +* @param p_se_cfg 全局数据结构 +* @param queue_id 队列id +* @param fun_id hash引擎0~3 +* @return +* @remark 无 +* @see +* @author cq @date 2023/08/02 +************************************************************/ +DPP_STATUS dpp_dtb_zcam_space_clr(DPP_DEV_T *dev, + DPP_SE_CFG *p_se_cfg, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 fun_id); + +/***********************************************************/ +/** flush指定eram空间 +* @param dev_id 设备id +* @param queue_id 队列id +* @param sdt_no sdt号 +* @return +* @remark 无 +* @see +* @author cq @date 2023/08/02 +************************************************************/ +DPP_STATUS dpp_dtb_eram_table_flush(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 sdt_no); + +/***********************************************************/ +/** flush指定hash空间(DDR/ZCAM) +* @param dev_id 设备id +* @param queue_id 队列id +* @param sdt_no sdt号 +* @return +* @remark 无 +* @see +* @author cq @date 2023/08/02 +************************************************************/ +DPP_STATUS dpp_dtb_hash_table_flush(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 sdt_no); + +/***********************************************************/ +/** 清除hash表资源(硬件和软件，硬件通过dtb方式清除) +* @param dev_id 设备id +* @param queue_id 队列id +* @param hash_id hash引擎 0~3 +* @return +* @remark 无 +* @see +* @author cq @date 2023/09/26 +************************************************************/ +DPP_STATUS dpp_dtb_hash_all_entry_delete(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 hash_id); + +/***********************************************************/ +/** DTB etcam 整个流表清空Flush +* @param devId NP设备号 +* @param queueId DTB队列编号 +* @param sdtNo 流表std号 +* @return +* @remark 无 +* @see +* @author cbb @date 2023/07/03 +************************************************************/ +DPP_STATUS dpp_dtb_etcam_table_flush(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 sdt_no); + +/** dtb dump eram直接表表项内容 支持64bit/128bit +* @param dev_id 设备号 +* @param queue_id 队列号 +* @param sdt_no eram表sdt表号 +* @param start_index 要dump的起始index，单位是sdt_no该表的mode +* @param p_dump_data_arr 本次dump出的数据，数据格式与下表格式相同 +* @param entry_num 本次dump实际的条目数 +* @param next_start_index 下次dump是开始的index +* @param finish_flag 整个表dump完成标志，1表示完成，0表示未完成 +* @return +* @remark 无 +* @see +* @author cbb @date 2022/08/30 +************************************************************/ + DPP_STATUS dpp_dtb_eram_table_dump(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 sdt_no, + DPP_DTB_DUMP_INDEX_T start_index, + DPP_DTB_ERAM_ENTRY_INFO_T* p_dump_data_arr, + ZXIC_UINT32 *entry_num, + DPP_DTB_DUMP_INDEX_T *next_start_index, + ZXIC_UINT32 *finish_flag); + +/***********************************************************/ +/** 只dump hash表的zcam内容 +* @param dev_id 设备id +* @param queue_id 队列id 0~127 +* @param sdt_no sdt号 0~255 +* @param pDumpData 出参，dump数据，内存由用户分配，结构体DPP_DTB_HASH_ENTRY_INFO_T +* @param entryNum 出参，dump出的有效hash条目 +* @return +* @remark 无 +* @see +* @author cq @date 2023/08/22 +************************************************************/ +DPP_STATUS dpp_dtb_hash_table_only_zcam_dump(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 sdt_no, + ZXIC_UINT8* pDumpData, + ZXIC_UINT32 *entryNum); + +/** dtb dump etcam直接表表项内容 级联eram支持64bit/128bit +* @param dev_id 设备号 +* @param queue_id 队列号 +* @param sdt_no acl表sdt表号 +* @param start_index 要dump的起始index，单位是sdt_no该表的mode +* @param p_dump_data_arr 本次dump出的数据，数据格式与下表格式相同 +* @param entry_num 本次dump实际的条目数 +* @param next_start_index 下次dump是开始的index +* @param finish_flag 整个表dump完成标志，1表示完成，0表示未完成 +* @return +* @remark 无 +* @see +* @author cbb @date 2022/08/30 +************************************************************/ + DPP_STATUS dpp_dtb_acl_table_dump(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 sdt_no, + DPP_DTB_DUMP_INDEX_T start_index, + DPP_DTB_ACL_ENTRY_INFO_T* p_dump_data_arr, + ZXIC_UINT32 *entry_num, + DPP_DTB_DUMP_INDEX_T *next_start_index, + ZXIC_UINT32 *finish_flag); + +ZXIC_VOID dpp_data_buff_print(ZXIC_UINT8 *buff, ZXIC_UINT32 size); +ZXIC_VOID dpp_acl_data_print(ZXIC_UINT8 *p_data, ZXIC_UINT8 *p_mask, ZXIC_UINT32 etcam_mode); +ZXIC_VOID dpp_dtb_data_print(ZXIC_UINT8 *p_data, ZXIC_UINT32 len); + +ZXIC_UINT32 dpp_ddr_index_calc(ZXIC_UINT32 index, + ZXIC_UINT32 width_mode, + ZXIC_UINT32 key_type, + ZXIC_UINT32 byte_offset); + +DPP_STATUS dpp_dtb_hash_dma_delete_hardware(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 sdt_no, + ZXIC_UINT32 entry_num, + DPP_DTB_HASH_ENTRY_INFO_T *p_arr_hash_entry, + ZXIC_UINT32 *element_id); + +ZXIC_UINT32 dpp_dtb_hash_zcam_delete_hardware(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + HASH_ENTRY_CFG *p_hash_entry_cfg, + DPP_HASH_ENTRY *p_hash_entry, + DPP_DTB_ENTRY_T *p_entry, + ZXIC_UINT8 *p_srh_succ); + +DPP_STATUS dpp_dtb_se_zcam_dma_dump(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 addr, + ZXIC_UINT32 tb_width, + ZXIC_UINT32 depth, + ZXIC_UINT32 *p_data, + ZXIC_UINT32 *element_id); + +ZXIC_UINT32 dpp_dtb_hash_data_parse(ZXIC_UINT32 item_type, + ZXIC_UINT32 key_by_size, + DPP_HASH_ENTRY *p_entry, + ZXIC_UINT8 *p_item_data, + ZXIC_UINT8 *p_data_offset); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/table/se/dpp_hash.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/table/se/dpp_hash.h new file mode 100755 index 0000000..e2a986c --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/table/se/dpp_hash.h @@ -0,0 +1,402 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_hash.h +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : wcl +* 完成日期 : 2014/02/14 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ + +#ifndef _DPP_HASH_H_ +#define _DPP_HASH_H_ + +#include "dpp_se_cfg.h" + +#define HASH_FUNC_ID_MIN (0) +#define HASH_FUNC_ID_NUM (4) + +#define HASH_DDR_CRC_NUM (4) + +#define HASH_KEY_MAX (49) /* 最大键值长度，以字节为单位 */ +#define HASH_RST_MAX (32) /* 最大结果长度，以字节为单位 */ +#define HASH_ENTRY_POS_STEP (16) + +#define HASH_TBL_ID_NUM (32) /* 每个Hash引擎中的最大业务表数目 */ +#define HASH_BULK_NUM (8) /* 每个Hash引擎DDR资源划分的块数 */ + + +#define HASH_ACTU_KEY_MIN (1) /* 业务实际键值长度 */ +#define HASH_ACTU_KEY_MAX (48) +#define HASH_ACTU_KEY_STEP (1) /* actual key的长度单位: 1字节 */ +#define HASH_KEY_CTR_SIZE (1) /* key中控制信息的长度, 1字节 */ +#define ITEM_ENTRY_NUM_2 (2) +#define ITEM_ENTRY_NUM_4 (4) + +#define HASH_DDR_ITEM_MIN (1<<14) +#define HASH_DDR_ITEM_MAX (1<<26) + +#define HASH_ZBLK_ID_MAX (31) + +/* hash ext cfg reg */ +#define HASH_EXT_MODE_BT_START (1) +#define HASH_EXT_MODE_BT_WIDTH (8) +#define HASH_EXT_FLAG_BT_START (0) +#define HASH_EXT_FLAG_BT_WIDTH (1) + +/* hash tbl30 depth reg */ +#define HASH_TBL0_DEPTH_BT_START (0) +#define HASH_TBL0_DEPTH_BT_WIDTH (8) +#define HASH_TBL1_DEPTH_BT_START (8) +#define HASH_TBL1_DEPTH_BT_WIDTH (8) +#define HASH_TBL2_DEPTH_BT_START (16) +#define HASH_TBL2_DEPTH_BT_WIDTH (8) +#define HASH_TBL3_DEPTH_BT_START (24) +#define HASH_TBL3_DEPTH_BT_WIDTH (8) + +/* hash tbl74 depth reg*/ +#define HASH_TBL4_DEPTH_BT_START (0) +#define HASH_TBL4_DEPTH_BT_WIDTH (8) +#define HASH_TBL5_DEPTH_BT_START (8) +#define HASH_TBL5_DEPTH_BT_WIDTH (8) +#define HASH_TBL6_DEPTH_BT_START (16) +#define HASH_TBL6_DEPTH_BT_WIDTH (8) +#define HASH_TBL7_DEPTH_BT_START (24) +#define HASH_TBL7_DEPTH_BT_WIDTH (8) + +/* hash ext crc cfg*/ +#define TBL0_EXT_CRC_CFG_BT_START (0) +#define TBL0_EXT_CRC_CFG_BT_WIDTH (2) +#define TBL1_EXT_CRC_CFG_BT_START (2) +#define TBL1_EXT_CRC_CFG_BT_WIDTH (2) +#define TBL2_EXT_CRC_CFG_BT_START (4) +#define TBL2_EXT_CRC_CFG_BT_WIDTH (2) +#define TBL3_EXT_CRC_CFG_BT_START (6) +#define TBL3_EXT_CRC_CFG_BT_WIDTH (2) +#define TBL4_EXT_CRC_CFG_BT_START (8) +#define TBL4_EXT_CRC_CFG_BT_WIDTH (2) +#define TBL5_EXT_CRC_CFG_BT_START (10) +#define TBL5_EXT_CRC_CFG_BT_WIDTH (2) +#define TBL6_EXT_CRC_CFG_BT_START (12) +#define TBL6_EXT_CRC_CFG_BT_WIDTH (2) +#define TBL7_EXT_CRC_CFG_BT_START (14) +#define TBL7_EXT_CRC_CFG_BT_WIDTH (2) + +/* hash mono flags*/ +#define HASH0_MONO_FLAG_BT_START (0) +#define HASH0_MONO_FLAG_BT_WIDTH (8) +#define HASH1_MONO_FLAG_BT_START (8) +#define HASH1_MONO_FLAG_BT_WIDTH (8) +#define HASH2_MONO_FLAG_BT_START (16) +#define HASH2_MONO_FLAG_BT_WIDTH (8) +#define HASH3_MONO_FLAG_BT_START (24) +#define HASH3_MONO_FLAG_BT_WIDTH (8) + +/* hash zcell mono*/ +#define ZCELL0_BULK_ID_BT_START (2) +#define ZCELL0_BULK_ID_BT_WIDTH (3) +#define ZCELL0_MONO_FLAG_BT_START (3) +#define ZCELL0_MONO_FLAG_BT_WIDTH (1) +#define ZCELL1_BULK_ID_BT_START (10) +#define ZCELL1_BULK_ID_BT_WIDTH (3) +#define ZCELL1_MONO_FLAG_BT_START (11) +#define ZCELL1_MONO_FLAG_BT_WIDTH (1) +#define ZCELL2_BULK_ID_BT_START (18) +#define ZCELL2_BULK_ID_BT_WIDTH (3) +#define ZCELL2_MONO_FLAG_BT_START (19) +#define ZCELL2_MONO_FLAG_BT_WIDTH (1) +#define ZCELL3_BULK_ID_BT_START (26) +#define ZCELL3_BULK_ID_BT_WIDTH (3) +#define ZCELL3_MONO_FLAG_BT_START (27) +#define ZCELL3_MONO_FLAG_BT_WIDTH (1) + +/* hash zreg mono */ +#define ZREG0_BULK_ID_BT_START (2) +#define ZREG0_BULK_ID_BT_WIDTH (3) +#define ZREG0_MONO_FLAG_BT_START (3) +#define ZREG0_MONO_FLAG_BT_WIDTH (1) +#define ZREG1_BULK_ID_BT_START (10) +#define ZREG1_BULK_ID_BT_WIDTH (3) +#define ZREG1_MONO_FLAG_BT_START (11) +#define ZREG1_MONO_FLAG_BT_WIDTH (1) +#define ZREG2_BULK_ID_BT_START (18) +#define ZREG2_BULK_ID_BT_WIDTH (3) +#define ZREG2_MONO_FLAG_BT_START (19) +#define ZREG2_MONO_FLAG_BT_WIDTH (1) +#define ZREG3_BULK_ID_BT_START (26) +#define ZREG3_BULK_ID_BT_WIDTH (3) +#define ZREG3_MONO_FLAG_BT_START (27) +#define ZREG3_MONO_FLAG_BT_WIDTH (1) + +#define OPR_CLR (0) +#define OPR_WR (1) + +#define OBTAIN_CONFLICT_KEY (0) + +/* HASH soft reset*/ +#define HASH_ARG_NUM_PER_BULK (8) /* 每个bulk 需要记录的参数数目 */ +#define HASH_ARG_NUM_PER_TBL (4) /* 每个表 需要记录的参数数目 */ +#define HASH_INIT_NUM (8) /* HASH引擎初始化参数数目 */ +#define HASH_BULK_INIT_NUM (1+HASH_BULK_NUM*HASH_ARG_NUM_PER_BULK+3) /* 1-bulk_valid +3是为了凑够4的倍数 */ +#define HASH_TBL_INIT_NUM (1+HASH_TBL_ID_NUM*HASH_ARG_NUM_PER_TBL+3) /* 1-tbl_valid +3是为了凑够4的整数倍 */ + +typedef struct dpp_hash_table_stat +{ + ZXIC_FLOAT ddr; + ZXIC_FLOAT zcell; + ZXIC_FLOAT zreg; + ZXIC_FLOAT sum; +}DPP_HASH_TABLE_STAT; + +typedef struct dpp_hash_zreg_mono_stat +{ + ZXIC_UINT32 zblk_id; + ZXIC_UINT32 zreg_id; +}DPP_HASH_ZREG_MONO_STAT; + +typedef struct dpp_hash_bulk_zcam_stat +{ + ZXIC_UINT32 zcell_mono_idx[SE_ZBLK_NUM*SE_ZCELL_NUM]; + DPP_HASH_ZREG_MONO_STAT zreg_mono_id[SE_ZBLK_NUM][SE_ZREG_NUM]; +}DPP_HASH_BULK_ZCAM_STAT; + +typedef struct dpp_hash_stat +{ + ZXIC_UINT32 insert_ok; + ZXIC_UINT32 insert_fail; + ZXIC_UINT32 insert_same; + ZXIC_UINT32 insert_ddr; + ZXIC_UINT32 insert_zcell; + ZXIC_UINT32 insert_zreg; + + ZXIC_UINT32 delete_ok; + ZXIC_UINT32 delete_fail; + + ZXIC_UINT32 search_ok; + ZXIC_UINT32 search_fail; + + ZXIC_UINT32 zblock_num; + ZXIC_UINT32 zblock_array[SE_ZBLK_NUM]; + + DPP_HASH_TABLE_STAT insert_table[HASH_TBL_ID_NUM]; + DPP_HASH_BULK_ZCAM_STAT *p_bulk_zcam_mono[HASH_BULK_NUM]; +}DPP_HASH_STAT; + +typedef enum dpp_hash_itme_pos +{ + HASH_ITEM_POS_0 = 0, + HASH_ITEM_POS_1 = 1, + HASH_ITEM_POS_2 = 2, + HASH_ITEM_POS_3 = 3, + HASH_ITEM_POS_MAX = 4, +}DPP_HASH_ITME_POS; + +typedef enum dpp_hash_item_inst_mode +{ + HASH_ITEM_INSERT_LAST = 0, + HASH_ITEM_INSERT_1ST, + HASH_ITEM_INSERT_NULL +}DPP_HASH_ITEM_INST_MODE; + +/* hash 表项信息 */ +typedef struct dpp_hash_tbl_info +{ + ZXIC_UINT32 fun_id; + ZXIC_UINT32 actu_key_size; /**< @brief 实际键值长度，以1字节为单位 */ + ZXIC_UINT32 key_type; /**< @brief 表项长度类型: 1-128bit, 2-256bit, 3-512bit */ + ZXIC_UINT8 is_init; /**< @brief 是否初始化*/ + ZXIC_UINT8 mono_zcell; /**< @brief 是否有独占的zcell*/ + ZXIC_UINT8 zcell_num; /**< @brief 独占的zcell的数目*/ + ZXIC_UINT8 mono_zreg; /**< @brief 是否有独占的zcell*/ + ZXIC_UINT8 zreg_num; /**< @brief 独占的zcell的数目*/ + ZXIC_UINT8 is_age; /* 硬件老化标志，业务表支持硬件老化 */ + ZXIC_UINT8 is_lrn; /* 硬件学习标志，业务表支持硬件学习 */ + ZXIC_UINT8 is_mc_wrt; /* 微码写表标志，业务表支持微码写表 */ + //ZXIC_UINT8 pad[3]; +}DPP_HASH_TBL_ID_INFO; + +typedef struct dpp_hash_rbkey_info +{ + ZXIC_UINT8 key[HASH_KEY_MAX]; + ZXIC_UINT8 rst[HASH_RST_MAX]; + D_NODE entry_dn; + SE_ITEM_CFG *p_item_info; +/* ZXIC_UINT32 rb_idx;*/ + ZXIC_UINT32 entry_size; /* 条目宽度，以字节为单位 */ + ZXIC_UINT32 entry_pos; /* 条目在item中的起始位置，以128bit为偏移单位 */ +}DPP_HASH_RBKEY_INFO; + +/* DDR*/ +typedef struct hash_ddr_cfg +{ + ZXIC_UINT32 bulk_use; /**< @brief 该hash引擎bulk空间是否已经使用*/ + ZXIC_UINT32 ddr_baddr; /**< @brief 分配给hash的DDR空间的硬件基地址*/ + ZXIC_UINT32 ddr_ecc_en; /**< @brief DDR ECC使能: 0-不使能，1-使能*/ + ZXIC_UINT32 item_num; /**< @brief 硬件分配的ddr存储单元数目，以位宽为单位*/ + ZXIC_UINT32 bulk_id; /**< @brief DDR空间编号*/ + ZXIC_UINT32 hash_ddr_arg; /**< @brief hash ddr CRC 计算式*/ + ZXIC_UINT32 width_mode; /**< @brief ddr3 位宽*/ + ZXIC_UINT32 hw_baddr; /**< @brief ddr3 存储单元起始偏移，以256bit为单位*/ + ZXIC_UINT32 zcell_num; /*cpu 软复位 存储记录该参数*/ + ZXIC_UINT32 zreg_num; /*cpu 软复位 存储记录该参数*/ + + SE_ITEM_CFG **p_item_array; /**< @brief 指向数组指针的指针*/ +}HASH_DDR_CFG; + +#define HASH_ADDR_EXT_FLAG_BT_OFF (31) +#define HASH_ADDR_WRT_MASK_BT_OFF (27) +#define HASH_ADDR_BT_OFF (1) +#define HASH_ADDR_DDR_BT_LEN (26) +#define HASH_ADDR_ZCAM_BT_LEN (17) +typedef struct dpp_hash_wrt_lrn_rsp +{ + ZXIC_UINT8 space_vld; /* 仅硬件学习时此标志有效 */ + ZXIC_UINT8 ext_flag; /* 软件模拟硬件学习标志位*/ + ZXIC_UINT8 wrt_mask; + ZXIC_UINT8 width_flag; + ZXIC_UINT32 lrn_addr; +}DPP_HASH_WRT_LRN_RSP; + +typedef struct dpp_hash_cfg +{ + ZXIC_UINT32 fun_id; + ZXIC_UINT8 ddr_valid; /* 是否使用DDR表项 */ + ZXIC_UINT8 pad[3]; + HASH_FUNCTION32 p_hash32_fun; + HASH_FUNCTION p_hash16_fun; + + HASH_DDR_CFG *p_bulk_ddr_info[HASH_BULK_NUM]; /* 每个DDR空间的配置*/ + ZXIC_UINT8 bulk_ram_mono[HASH_BULK_NUM]; /* 每个ZCAM空间独占标志*/ + SHARE_RAM hash_shareram; /* 共享的ZCAM资源 */ + DPP_SE_CFG *p_se_info; + + ZXIC_RB_CFG hash_rb; + ZXIC_RB_CFG ddr_cfg_rb; + DPP_HASH_STAT hash_stat; +}DPP_HASH_CFG; + +typedef struct hash_entry_cfg +{ + ZXIC_UINT32 fun_id; + ZXIC_UINT8 bulk_id; + ZXIC_UINT8 table_id; + ZXIC_UINT8 key_type; + ZXIC_UINT8 rsp_mode; + ZXIC_UINT32 actu_key_size; + ZXIC_UINT32 key_by_size; + ZXIC_UINT32 rst_by_size; + DPP_SE_CFG *p_se_cfg; + DPP_HASH_CFG *p_hash_cfg; + DPP_HASH_RBKEY_INFO *p_rbkey_new; + ZXIC_RB_TN *p_rb_tn_new; +}HASH_ENTRY_CFG; + +#define DPP_GET_HASH_KEY_CTRL(valid, type, tbl_id) (((valid & 0x1) << 7) | ((type & 0x3) << 5) | (tbl_id & 0x1f)) +#define DPP_GET_HASH_TBL_ID(p_key) ((p_key)[0] & 0x1F) +#define DPP_GET_HASH_KEY_TYPE(p_key) (((p_key)[0] >> 5) & 0x3) +#define DPP_GET_HASH_KEY_VALID(p_key) (((p_key)[0] >> 7) & 0x1) + +/** 根据hash的类型获取其字节数，返回值包括16B,32B和64B，或者0*/ +#define DPP_GET_HASH_ENTRY_SIZE(key_type) \ + ((key_type == HASH_KEY_128b)?16U: \ + ((key_type == HASH_KEY_256b)?32U: \ + ((key_type == HASH_KEY_512b)?64U:0))) + +#define DPP_GET_ACTU_KEY_BY_SIZE(actu_key_size) \ + (actu_key_size * HASH_ACTU_KEY_STEP) + +#define DPP_GET_KEY_SIZE(actu_key_size) \ + (DPP_GET_ACTU_KEY_BY_SIZE(actu_key_size) + HASH_KEY_CTR_SIZE) +#define DPP_GET_RST_SIZE(key_type, actu_key_size) \ + ((DPP_GET_HASH_ENTRY_SIZE(key_type) != 0)? \ + (DPP_GET_HASH_ENTRY_SIZE(key_type) - DPP_GET_ACTU_KEY_BY_SIZE(actu_key_size) - HASH_KEY_CTR_SIZE): 0xFF) /* modify coverity kfr 2022.05.31 */ + +#define DPP_GET_HASH_RB_KEY(p_hash_rb, idx) \ + ((p_hash_rb)->p_keybase + ((p_hash_rb)->key_size * (idx))) + +#define DPP_GET_DDR_WR_MODE(key_type) ((key_type == HASH_KEY_512b)?key_type : (key_type - 1)) + +/** 根据条目位宽和起始的位置获取写入掩码 */ +#define DPP_GET_HASH_ENTRY_MASK(entry_size, entry_pos) \ + ((((1U << (entry_size/16U)) - 1U) << (4U - entry_size/16U - entry_pos)) & 0xF) + +DPP_STATUS dpp_hash_zblkcfg_write(DPP_SE_CFG *p_se_cfg, ZXIC_UINT32 fun_id, SE_ZBLK_CFG *p_zblk_cfg); + +DPP_STATUS dpp_hash_bulk_mono_flags_write(DPP_SE_CFG *p_se_cfg, ZXIC_UINT32 hash_id, ZXIC_UINT32 bulk_id); + +DPP_STATUS dpp_hash_zcell_mono_write(DPP_SE_CFG *p_se_cfg, SE_ZCELL_CFG *p_zcell_cfg); + +DPP_STATUS dpp_hash_zreg_mono_write(DPP_SE_CFG *p_se_cfg, + ZXIC_UINT32 tbl_id, + ZXIC_UINT32 zblk_idx, + ZXIC_UINT32 zreg_id); + +DPP_STATUS dpp_hash_ext_cfg_write(DPP_SE_CFG *p_se_cfg, + ZXIC_UINT32 fun_id, + ZXIC_UINT32 bulk_id, + HASH_DDR_CFG *p_ddr_cfg); + +DPP_STATUS dpp_hash_ext_cfg_clr(DPP_SE_CFG *p_se_cfg, ZXIC_UINT32 fun_id); + +DPP_STATUS dpp_hash_tbl_depth_write(DPP_SE_CFG *p_se_cfg, + ZXIC_UINT32 fun_id, + ZXIC_UINT32 bulk_id, + HASH_DDR_CFG *p_ddr_cfg); + +DPP_STATUS dpp_hash_tbl_depth_clr(DPP_SE_CFG *p_se_cfg, ZXIC_UINT32 fun_id); + +DPP_STATUS dpp_hash_tbl_crc_poly_write(DPP_SE_CFG *p_se_cfg, + ZXIC_UINT32 fun_id, + ZXIC_UINT32 bulk_id, + ZXIC_UINT32 crc_sel); + +ZXIC_SINT32 dpp_hash_rb_key_cmp(ZXIC_VOID *p_new, ZXIC_VOID *p_old, ZXIC_UINT32 key_size); + +DPP_STATUS dpp_hash_insrt_to_item(DPP_HASH_CFG *p_hash_cfg, + DPP_HASH_RBKEY_INFO *p_rbkey, + SE_ITEM_CFG *p_item, + ZXIC_UINT32 item_idx, + ZXIC_UINT32 item_type, + ZXIC_UINT32 insrt_key_type); + +DPP_STATUS dpp_hash_red_black_node_alloc(DPP_DEV_T *dev,ZXIC_RB_TN **p_rb_tn_new,DPP_HASH_RBKEY_INFO **p_rbkey_new); + +DPP_STATUS dpp_hash_rb_insert(DPP_DEV_T *dev,HASH_ENTRY_CFG *p_hash_entry_cfg,DPP_HASH_ENTRY *p_entry); + +DPP_STATUS dpp_hash_set_crc_key(DPP_DEV_T *dev,HASH_ENTRY_CFG *p_hash_entry_cfg,DPP_HASH_ENTRY *p_entry,ZXIC_UINT8 *p_temp_key); + +DPP_STATUS dpp_hash_insert_ddr(DPP_DEV_T *dev,HASH_ENTRY_CFG *p_hash_entry_cfg,ZXIC_UINT8 *p_temp_key,ZXIC_UINT8 *p_end_flag); + +DPP_STATUS dpp_hash_insert_zcell(DPP_DEV_T *dev,DPP_SE_CFG *p_se_cfg,HASH_ENTRY_CFG *p_hash_entry_cfg,ZXIC_UINT8 *p_temp_key,ZXIC_UINT8 *p_end_flag); + +DPP_STATUS dpp_hash_insert_zreg(DPP_DEV_T *dev,HASH_ENTRY_CFG *p_hash_entry_cfg,ZXIC_UINT8 *p_temp_key,ZXIC_UINT8 *p_end_flag); + +/***********************************************************/ +/** 清除hash引擎的所有hash表项(清除软件配置) +* @param p_se_cfg +* @param hash_id +* @param bulk_id +* +* @return +* @remark 无 +* @see +* @author cq @date 2023/08/18 +************************************************************/ +DPP_STATUS dpp_hash_soft_all_entry_delete(DPP_SE_CFG *p_se_cfg,ZXIC_UINT32 hash_id); + +DPP_STATUS dpp_hash_get_hash_info_from_sdt(ZXIC_UINT32 dev_id, ZXIC_UINT32 sdt_no, HASH_ENTRY_CFG *p_hash_entry_cfg); + +DPP_STATUS dpp_hash_soft_uninstall(ZXIC_UINT32 dev_id); + +DPP_STATUS dpp_one_hash_soft_uninstall(ZXIC_UINT32 dev_id,ZXIC_UINT32 hash_id); + +#endif /* dpp_hash.h */ diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/table/se/dpp_hash_crc.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/table/se/dpp_hash_crc.h new file mode 100755 index 0000000..33fde70 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/table/se/dpp_hash_crc.h @@ -0,0 +1,16 @@ +#ifndef _DPP_HASH_CRC_H_ +#define _DPP_HASH_CRC_H_ + +#define MAX_CRC_WIDTH (20) + +ZXIC_UINT32 dpp_crc32_calc(ZXIC_UINT8 *pInputKey,ZXIC_UINT32 dwByteNum,ZXIC_UINT32 dwCrcPoly); + +ZXIC_UINT16 dpp_crc16_calc(ZXIC_UINT8 *pInputKey,ZXIC_UINT32 dwByteNum,ZXIC_UINT16 dwCrcPoly); + +ZXIC_UINT16 dpp_crc16_get_idx(ZXIC_UINT16 crc_val); + +ZXIC_UINT16 dpp_crc16_table_lookup(ZXIC_UINT8 *pInputKey, ZXIC_UINT32 dwByteNum, ZXIC_UINT16 dwCrcPoly); + +#endif + + diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/table/se/dpp_se_cfg.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/table/se/dpp_se_cfg.h new file mode 100755 index 0000000..7f66a22 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/table/se/dpp_se_cfg.h @@ -0,0 +1,279 @@ +/***************************************************************************** + * 版权所有 (C)2001-2015, 深圳市中兴通讯股份有限公司。 + * + * 文件名称： dpp_se_cfg.h + * 文件标识： SE配置部分头文件 + * 内容摘要： + * 其它说明： + * 当前版本： + * 作 者： ChenWei10088471 + * 完成日期： + * 当前责任人-1： + * 当前责任人-2： + * + * DEPARTMENT : ASIC_FPGA_R&D_Dept + * MANUAL_PERCENT : 100% + *****************************************************************************/ + +#ifndef _DPP_SE_CFG_H_ +#define _DPP_SE_CFG_H_ + +#include "dpp_se_api.h" + + +#define DPP_WRITE_FILE_EN (0) + +#define LPM_OPTIMIZE_EZXIC_VOLUTION_TIME_SET_EN (0) + +#define SE_ITEM_WIDTH_MAX (64) /* 单条item最大宽度, 以字节为单位 */ +#define SE_ENTRY_WIDTH_MAX (64) /* 单条entry最大宽度, 以字节为单位 */ + +#define SE_RAM_WIDTH (512) + +#define IPV4_DDR_WIDTH (256) +#define IPV6_DDR_WIDTH (512) +#define IPV6_DDR_WIDTH_LR (384) /*线速宽度为384*/ + +#define ROUTE_DEFAULT_REG_NUM (8) +#define ZBLK_LAST_INDREG_ADDR (0x15) +#define ZBLK_ECC_STATU_REG_ADDR (0x11) +#define ZBLK_HASH_LIST_REG0_ADDR (0xd) +#define ZBLK_HASH_LIST_REG3_ADDR (0x10) + +#define ZCELL_ADDR_BT_START (0) +#define ZCELL_ADDR_BT_WIDTH (9) +#define ZCELL_IDX_BT_START (9) +#define ZCELL_IDX_BT_WIDTH (2) +#define ZBLK_IDX_BT_START (11) +#define ZBLK_IDX_BT_WIDTH (3) +#define ZGRP_IDX_BT_START (14) +#define ZGRP_IDX_BT_WIDTH (2) +#define REG_SRAM_FLAG_BT_START (16) +#define REG_SRAM_FLAG_BT_WIDTH (1) +#define ZBLK_WRT_MASK_BT_START (17) +#define ZBLK_WRT_MASK_BT_WIDTH (4) + +#define ZBLK_NUM_PER_ZGRP (8) + +/*片外部分*/ +#define SE_DDR_WIDTH (128) + + +struct def_route_info; + + +/*HASH 函数部分*/ +typedef ZXIC_UINT16 (*HASH_FUNCTION)(ZXIC_UINT8 *pkey,ZXIC_UINT32 width,ZXIC_UINT16 arg); +typedef ZXIC_UINT32 (*HASH_FUNCTION32)(ZXIC_UINT8 *pkey,ZXIC_UINT32 width,ZXIC_UINT32 arg); + +typedef ZXIC_UINT32 (*WR_PROCESS) (ZXIC_UINT8*p_buff, ZXIC_UINT32 size); + + +typedef enum file_type +{ + FILE_TYPE_REG = 0, + FILE_TYPE_RAM, + FILE_TYPE_ZBLK_CFG, + FILE_TYPE_ZCELL_CFG, + FILE_TYPE_DEF_ROUTE, + FILE_TYPE_DDR256, + FILE_TYPE_DDR512, + FILE_TYPE_V6CMP_CFG, + FILE_TYPE_V4CMP_CFG, + FILE_TYPE_DDR128, +}FILE_TYPE; + +typedef enum se_item_type +{ + ITEM_INVALID = 0, + ITEM_RAM, + ITEM_DDR_256, + ITEM_DDR_512, + ITEM_REG, +}SE_ITEM_TYPE; + + +typedef enum se_fun_type +{ + FUN_HASH = 1, + FUN_LPM, + FUN_ACL, + FUN_MAX +}SE_FUN_TYPE; + + +typedef struct file_info +{ + ZXIC_FILE *fp; + ZXIC_UINT32 f_status; /*1 open, 0 close*/ +}FILE_INFO; + +typedef struct file_mng +{ + ZXIC_RB_CFG rb_fn; + FILE_INFO *p_fi; +}SE_FILE_MNG; + + +#define ZBLK_CFG_BASE (0x8000) +#define SERVICE_REG_ADDR (0) +#define MASK_REG_ADDR (1) +#define DEFAULT_REG_ADDR (5) +#define V6CMP_REG_ADDR (0x12) +#define V4CMP_REG_ADDR (0x13) + +#define GET_ZBLK_IDX(zcell_idx) \ + (((zcell_idx) & 0x7F) >> 2) + +#define GET_ZCELL_IDX(zcell_idx) \ + ((zcell_idx) & 0x3) + +#define DPP_SE_GET_ZBLK_CFG(p_se,zblk_idx) \ + (&(((DPP_SE_CFG*)(p_se))->zblk_info[zblk_idx])) + +#define DPP_SE_GET_ZCELL_CFG(p_se,zcell_idx) \ + (&(((DPP_SE_CFG*)(p_se))->zblk_info[GET_ZBLK_IDX(zcell_idx)].zcell_info[GET_ZCELL_IDX(zcell_idx)])) + +#define DPP_GET_FUN_INFO(p_se,fun_id) \ + (&(((DPP_SE_CFG*)(p_se))->fun_info[fun_id])) + + +#define ZBLK_CHECK_FULL(p_zblk_cfg) \ + (((((SE_ZBLK_CFG*)(p_zblk_cfg))->zcell_bm & 0xF )== 0xF ) ? 1 : 0 ) + +#define GET_ZCELL_CRC_VAL(zcell_id, crc16_val) \ + (((crc16_val) >> (zcell_id)) & (SE_RAM_DEPTH - 1)) + +#define ZBLK_ADDR_CONV(zblk_idx) \ + (((zblk_idx) / ZBLK_NUM_PER_ZGRP) * (1 << ZBLK_IDX_BT_WIDTH) + (zblk_idx)%ZBLK_NUM_PER_ZGRP) + +#define ZCELL_ADDR_CONV(zcell_idx) \ + ((ZBLK_ADDR_CONV(((zcell_idx) >> ZCELL_IDX_BT_WIDTH) & ((1<<(ZBLK_IDX_BT_WIDTH+ZGRP_IDX_BT_WIDTH))-1)) << ZCELL_IDX_BT_WIDTH) | ((zcell_idx) & ((1<is_used)\ + {\ + ZXIC_COMM_TRACE_ERROR("\n Error[0x%x],is_used Fun_id is invalid,(p_func_id)->is_used is [%d]",DPP_SE_RC_FUN_INVALID,(p_func_id)->is_used);\ + return DPP_SE_RC_FUN_INVALID;\ + }\ + else if ((p_func_id)->fun_id != (id))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n Error[0x%x],fun_id != (id) Fun_id is invalid;p_func_id->fun_id is [%d]",DPP_SE_RC_FUN_INVALID,(p_func_id)->fun_id);\ + return DPP_SE_RC_FUN_INVALID;\ + }\ + else if (!(p_func_id)->fun_ptr)\ + {\ + ZXIC_COMM_TRACE_ERROR("\n Error[0x%x],fun_ptr Fun_id is invalid",DPP_SE_RC_FUN_INVALID);\ + return DPP_SE_RC_FUN_INVALID;\ + }\ + else if ((p_func_id)->fun_type != (type))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n Error[0x%x],type Fun_id is invalid",DPP_SE_RC_FUN_INVALID);\ + return DPP_SE_RC_FUN_INVALID;\ + }\ + }while (0) + +#define DPP_SE_CHECK_FUN_MEMORY_FREE(p_func_id,id,type,ptr) \ + do{\ + if (!(p_func_id)->is_used)\ + {\ + ZXIC_COMM_TRACE_ERROR("\n Error[0x%x],is_used Fun_id is invalid,(p_func_id)->is_used is [%d]",DPP_SE_RC_FUN_INVALID,(p_func_id)->is_used);\ + ZXIC_COMM_FREE(ptr);\ + return DPP_SE_RC_FUN_INVALID;\ + }\ + else if ((p_func_id)->fun_id != (id))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n Error[0x%x],fun_id != (id) Fun_id is invalid;p_func_id->fun_id is [%d]",DPP_SE_RC_FUN_INVALID,(p_func_id)->fun_id);\ + ZXIC_COMM_FREE(ptr);\ + return DPP_SE_RC_FUN_INVALID;\ + }\ + else if (!(p_func_id)->fun_ptr)\ + {\ + ZXIC_COMM_TRACE_ERROR("\n Error[0x%x],fun_ptr Fun_id is invalid",DPP_SE_RC_FUN_INVALID);\ + ZXIC_COMM_FREE(ptr);\ + return DPP_SE_RC_FUN_INVALID;\ + }\ + else if ((p_func_id)->fun_type != (type))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n Error[0x%x],type Fun_id is invalid",DPP_SE_RC_FUN_INVALID);\ + ZXIC_COMM_FREE(ptr);\ + return DPP_SE_RC_FUN_INVALID;\ + }\ + }while (0) + +#define DPP_SE_CHECK_FUN_MUTEX_UNLOCK(p_func_id, id, type, mutex) \ +do{\ + if (!(p_func_id)->is_used)\ + {\ + ZXIC_COMM_TRACE_ERROR("\n Error[0x%x],is_used Fun_id is invalid,(p_func_id)->is_used is [%d]", DPP_SE_RC_FUN_INVALID,(p_func_id)->is_used);\ + zxic_comm_mutex_unlock(mutex);\ + return DPP_SE_RC_FUN_INVALID;\ + }\ + else if ((p_func_id)->fun_id != (id))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n Error[0x%x],fun_id != (id) Fun_id is invalid;p_func_id->fun_id is [%d]", DPP_SE_RC_FUN_INVALID,(p_func_id)->fun_id);\ + zxic_comm_mutex_unlock(mutex);\ + return DPP_SE_RC_FUN_INVALID;\ + }\ + else if (!(p_func_id)->fun_ptr)\ + {\ + ZXIC_COMM_TRACE_ERROR("\n Error[0x%x],fun_ptr Fun_id is invalid", DPP_SE_RC_FUN_INVALID);\ + zxic_comm_mutex_unlock(mutex);\ + return DPP_SE_RC_FUN_INVALID;\ + }\ + else if ((p_func_id)->fun_type != (type))\ + {\ + ZXIC_COMM_TRACE_ERROR("\n Error[0x%x],type Fun_id is invalid", DPP_SE_RC_FUN_INVALID);\ + zxic_comm_mutex_unlock(mutex);\ + return DPP_SE_RC_FUN_INVALID;\ + }\ + }while (0) + + +#define DPP_SE_HW_POS(x) (SE_RAM_WIDTH - 1 -(x)) + +#define DPP_SE_ZBLK_OUT_DDR_V6_START (0) +#define DPP_SE_ZBLK_OUT_DDR_V6_END (0) + +#define DPP_SE_ZBLK_OUT_DDR_V4_START (0) +#define DPP_SE_ZBLK_OUT_DDR_V4_END (0) + +#define DPP_SE_ZBLK_SERVICE_TYPE_START (3) +#define DPP_SE_ZBLK_SERVICE_TYPE_END (3) + +#define DPP_SE_ZBLK_HASH_CHAN_START (2) +#define DPP_SE_ZBLK_HASH_CHAN_END (1) + +#define DPP_SE_ZBLK_HW_POS_EN_START (0) +#define DPP_SE_ZBLK_HW_POS_EN_END (0) + +#endif + + diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/tm/dpp_tm.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/tm/dpp_tm.h new file mode 100755 index 0000000..35c2a90 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/tm/dpp_tm.h @@ -0,0 +1,4917 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_tm.h +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : djf +* 完成日期 : 2014/02/25 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ +#ifndef _DPP_ETM_H_ +#define _DPP_ETM_H_ + + +#include "dpp_tm_api.h" +#include "dpp_etm_reg.h" +#if ZXIC_REAL("ETM_MACRO") +/****************************************************************************** + * START: 宏定义 * + *****************************************************************************/ +#define ETM_WRITE_CHECK (1) +#define DPP_TM_CGAVD_KILO_UL (1024)/* Kbyte和byte换算 */ +#define DPP_TM_CGAVD_TD_MAX (16*512) +/* CIR颗粒度: bps */ +#define DPP_TM_SHAPE_CIR_STEP ((ZXIC_DOUBLE) 400 * 1000 * 1000 * 1000 / 0x3FFFFFE) +//#define DPP_TM_SHAPE_CIR_STEP (160069565217 / 0x3FFFFFE) +/* EIR颗粒度: bps */ +//define DPP_TM_SHAPE_EIR_STEP ((ZXIC_FLOAT) 160 * 1000 * 1000 * 1000 / 0x3FFFFFE) +#define DPP_TM_SHAPE_EIR_STEP (160 * 1000 * 1000 * 1000 / 0x3FFFFFE) +#define DPP_TM_SHAPE_DEFAULT_CBS (20)/*寄存器写入CBS的最小值，小于该值时，整形不准*/ +#define DPP_TM_KILO_UL (1024) +#define DPP_TM_KILO_ULL (1000) +#define DPP_TM_QMU_PORT_SHAP_MAG (1.03) +#define DPP_ETM_SA_EGRS_MAX_PORTID (66) +/*cfgmt_byte_mode:0:block mode 1:byte mode*/ +#define DPP_TM_CGAVD_BLOCK_MODE (0) +#define DPP_TM_CGAVD_ZXIC_UINT8_MODE (1) + +/*shap整形模板最大值:每2K流或调度器一一映射一块令牌桶资源,每块资源拥有0-127个模板*/ +/*ETM 0xABFF/2K = 21 */ +#define DPP_ETM_SHAP_TABEL_ID_MAX (22) +/*FTM 0x17FF/2K = 2 */ +#define DPP_FTM_SHAP_TABEL_ID_MAX (3) +#define DPP_TM_SHAP_MAP_ID_MAX (128) + +/****************************************************************************** + * END: 宏定义 * + *****************************************************************************/ +#endif /* ETM_MACRO */ + + + +#if ZXIC_REAL("ETM_STRUCT") +/****************************************************************************** + * START: 类型定义 * + *****************************************************************************/ +/* block长度模式 */ +typedef enum dpp_tm_blk_size_e +{ + DPP_ETM_BLK_SIZE_128_B = 0, + DPP_ETM_BLK_SIZE_256_B, + DPP_ETM_BLK_SIZE_512_B, + DPP_ETM_BLK_SIZE_1024_B, + DPP_ETM_BLK_SIZE_INVALID +} DPP_ETM_BLK_SIZE_E; + +/* 动态门限放大因子参数 */ +typedef struct dpp_tm_amplify_gene_para_t +{ + ZXIC_UINT32 amplify_gene[16]; +} DPP_ETM_AMPLIFY_GENE_PARA_T; + +/* 等价包长阈值 */ +typedef struct dpp_tm_equal_pkt_len_th_para_t +{ + ZXIC_UINT32 equal_pkt_len_th[7]; +} DPP_ETM_EQUAL_PKT_LEN_TH_PARA_T; + +/* 等价包长*/ +typedef struct dpp_tm_equal_pkt_len_para_t +{ + ZXIC_UINT32 equal_pkt_len[8]; +} DPP_ETM_EQUAL_PKT_LEN_PARA_T; + +/*ETM_STRUCT_STAT */ +typedef enum dpp_tm_cgavd_stat_qnum_e +{ + DPP_ETM_CGAVD_STAT_QNUM1 = 0, + DPP_ETM_CGAVD_STAT_QNUM2 = 1, + DPP_ETM_CGAVD_STAT_QNUM_INVALID +} DPP_ETM_CGAVD_STAT_QNUM_E; + +typedef enum dpp_tm_cgavd_stat_mode_e +{ + DPP_ETM_CGAVD_STAT_ALL_QUEUE = 0, + DPP_ETM_CGAVD_STAT_ONE_QUEUE = 1, + DPP_ETM_CGAVD_STAT_MODE_INVALID +} DPP_ETM_CGAVD_STAT_MODE_E; + + +typedef struct dpp_tm_cgavd_stat_para_t +{ + DPP_ETM_CGAVD_STAT_MODE_E mode; + ZXIC_UINT32 q_id; +} DPP_ETM_CGAVD_STAT_PARA_T; + +typedef struct dpp_tm_cgavd_stat_info_t +{ + DPP_ETM_CGAVD_STAT_MODE_E mode; + ZXIC_UINT32 q_id; + ZXIC_UINT32 lif_in_pkt_num; + ZXIC_UINT32 enqueue_pkt_num; + ZXIC_UINT32 dequeue_pkt_num; + ZXIC_UINT32 td_drop_pkt_num; + ZXIC_UINT32 wred_drop_pkt_num; + ZXIC_UINT32 wred_dpi_pkt_num[8]; + ZXIC_UINT32 gred_drop_pkt_num; + ZXIC_UINT32 gred_dpi_pkt_num[8]; +} DPP_ETM_CGAVD_STAT_INFO_T; + +typedef struct dpp_tm_qmu_stat_info_t +{ + ZXIC_UINT32 fc_cnt_mode; + ZXIC_UINT32 mmu_qmu_wr_fc_cnt; + ZXIC_UINT32 mmu_qmu_rd_fc_cnt; + ZXIC_UINT32 qmu_cgavd_fc_cnt; + ZXIC_UINT32 cgavd_qmu_pkt_cnt; + ZXIC_UINT32 cgavd_qmu_pktlen_all; + ZXIC_UINT32 cgavd_qmu_drop_tap; + ZXIC_UINT32 last_drop_qnum; + ZXIC_UINT32 crdt_qmu_credit_cnt; + ZXIC_UINT32 qmu_to_qsch_report_cnt; + ZXIC_UINT32 qmu_to_cgavd_report_cnt; + ZXIC_UINT32 qmu_crdt_crs_normal_cnt; + ZXIC_UINT32 qmu_crdt_crs_off_cnt; + ZXIC_UINT32 qsch_qlist_shedule_cnt; + ZXIC_UINT32 qsch_qlist_sch_ept_cnt; + ZXIC_UINT32 qmu_to_mmu_blk_wr_cnt; + ZXIC_UINT32 qmu_to_csw_blk_rd_cnt; + ZXIC_UINT32 qmu_to_mmu_sop_wr_cnt; + ZXIC_UINT32 qmu_to_mmu_eop_wr_cnt; + ZXIC_UINT32 qmu_to_mmu_drop_wr_cnt; + ZXIC_UINT32 qmu_to_csw_sop_rd_cnt; + ZXIC_UINT32 qmu_to_csw_eop_rd_cnt; + ZXIC_UINT32 qmu_to_csw_drop_rd_cnt; + ZXIC_UINT32 mmu_to_qmu_wr_release_cnt; + ZXIC_UINT32 mmu_to_qmu_rd_release_cnt; +} DPP_ETM_QMU_STAT_INFO_T; + +typedef struct dpp_tm_qmu_spec_q_stat_info_t +{ + ZXIC_UINT32 observe_portfc_spec; + ZXIC_UINT32 spec_lif_portfc_count; + ZXIC_UINT32 observe_qnum_set; + ZXIC_UINT32 spec_q_pkt_received; + ZXIC_UINT32 spec_q_pkt_dropped; + ZXIC_UINT32 spec_q_pkt_scheduled; + ZXIC_UINT32 spec_q_wr_cmd_sent; + ZXIC_UINT32 spec_q_rd_cmd_sent; + ZXIC_UINT32 spec_q_pkt_enq; + ZXIC_UINT32 spec_q_pkt_deq; + ZXIC_UINT32 spec_q_crdt_uncon_received; + ZXIC_UINT32 spec_q_crdt_cong_received; + ZXIC_UINT32 spec_q_crs_normal_cnt; + ZXIC_UINT32 spec_q_crs_off_cnt; +} DPP_ETM_QMU_SPEC_Q_STAT_INFO_T; + +typedef struct dpp_tm_qmu_spec_bat_stat_info_t +{ + ZXIC_UINT32 observe_batch_set; + ZXIC_UINT32 spec_bat_pkt_received; + ZXIC_UINT32 spec_bat_pkt_dropped; + ZXIC_UINT32 spec_bat_blk_scheduled; + ZXIC_UINT32 spec_bat_wr_cmd_sent; + ZXIC_UINT32 spec_bat_rd_cmd_sent; + ZXIC_UINT32 spec_bat_pkt_enq; + ZXIC_UINT32 spec_bat_pkt_deq; + ZXIC_UINT32 spec_bat_crdt_uncon_received; + ZXIC_UINT32 spec_bat_crdt_cong_received; + ZXIC_UINT32 spec_bat_crs_normal_cnt; + ZXIC_UINT32 spec_bat_crs_off_cnt; +} DPP_ETM_QMU_SPEC_BAT_STAT_INFO_T; + +typedef struct qmu_port_shape_para +{ + ZXIC_UINT32 shape_value_amplified; + ZXIC_UINT32 token_add_num; + ZXIC_UINT32 token_gap; +} QMU_PORT_SHAPE_PARA; + +/*etm 实际使用的ddr_attach、bank_num、depth(mmu中看到的)*/ +typedef struct dpp_etm_qmu_init_para +{ + ZXIC_UINT32 etm_mmu_ddr_attach; + ZXIC_UINT32 etm_mmu_bank_num; + ZXIC_UINT32 etm_mmu_depth; +} DPP_ETM_QMU_INIT_PARA; + +/*ftm 实际使用的ddr_attach、bank_num、depth(mmu中看到的)*/ +typedef struct dpp_ftm_qmu_init_para +{ + ZXIC_UINT32 ftm_mmu_ddr_attach; + ZXIC_UINT32 ftm_mmu_bank_num; + ZXIC_UINT32 ftm_mmu_depth; +} DPP_FTM_QMU_INIT_PARA; + +typedef struct dpp_tm_crdt_spwfq_start_num_t +{ + ZXIC_UINT32 start_num_fq; + ZXIC_UINT32 start_num_fq2; + ZXIC_UINT32 start_num_fq4; + ZXIC_UINT32 start_num_fq8; + ZXIC_UINT32 start_num_sp; + ZXIC_UINT32 start_num_wfq; + ZXIC_UINT32 start_num_wfq2; + ZXIC_UINT32 start_num_wfq4; + ZXIC_UINT32 start_num_wfq8; +} DPP_TM_CRDT_SPWFQ_START_NUM_T; + + +/****************************************************************************** + * END: 类型定义 * + *****************************************************************************/ +#endif + + + +#if ZXIC_REAL("ETM_FUNCTION") +/****************************************************************************** + * START: 函数声明 * + *****************************************************************************/ +/***********************************************************/ +/** 打印指定的全局数组值以及清空全局数组 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param para_x 数组index_x +* @param para_y 数组index_y +* @param clear_flag 清空shape全局数组 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark +* @see +* @author xuhb @date 2019/06/10 +************************************************************/ +DPP_STATUS dpp_tm_shape_para_array_prt(ZXIC_UINT32 dev_id, + ZXIC_UINT32 para_x, + ZXIC_UINT32 para_y, + ZXIC_UINT32 clear_flag); + +DPP_STATUS dpp_tm_qmu_qlist_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 ddr_num, + ZXIC_UINT32 bank_num_para, + ZXIC_UINT32 bank_vld, + ZXIC_UINT32 gene_para); + +DPP_STATUS dpp_tm_cgavd_td_th_together_wr(DPP_DEV_T *dev, + ZXIC_UINT32 level, + ZXIC_UINT32 id, + ZXIC_UINT32 td_th, + ZXIC_UINT32 num); + + +DPP_STATUS dpp_tm_cgavd_td_th_together_get(DPP_DEV_T *dev, + ZXIC_UINT32 level, + ZXIC_UINT32 id, + ZXIC_UINT32 num); + +DPP_STATUS dpp_tm_cgavd_dyn_th_en_set_more(DPP_DEV_T *dev, + DPP_TM_CGAVD_LEVEL_E level, + ZXIC_UINT32 id, + ZXIC_UINT32 en, + ZXIC_UINT32 num); + +/***********************************************************/ +/** 配置基于优先级的QMU接收NPPU数据的fifo阈值 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param sp 优先级0~7 +* @param th 指定优先级的fifo阈值0~511，单位为fifo条目，fifo深度512 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2016/10/18 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_move_drop_sp_th_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 sp, + ZXIC_UINT32 th); + + +DPP_STATUS dpp_tm_wred_dp_line_para_wr(ZXIC_UINT32 dev_id, + ZXIC_UINT32 level, + ZXIC_UINT32 wred_id, + ZXIC_UINT32 dp, + ZXIC_UINT32 max_th, + ZXIC_UINT32 min_th, + ZXIC_UINT32 max_p, + ZXIC_UINT32 weight, + ZXIC_UINT32 q_len_th); + + +DPP_STATUS dpp_tm_gred_dp_line_para_wr(ZXIC_UINT32 dev_id, + ZXIC_UINT32 dp, + ZXIC_UINT32 max_th, + ZXIC_UINT32 mid_th, + ZXIC_UINT32 min_th, + ZXIC_UINT32 max_p, + ZXIC_UINT32 weight, + ZXIC_UINT32 q_len_th); + +DPP_STATUS dpp_tm_crdt_idle_check(DPP_DEV_T *dev); + +/***********************************************************/ +/** 获取各调度器的起始编号（etm共25K=25600,ftm共1920个） +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_spwfq_start_num 调度器起始编号结构体 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/02/28 +************************************************************/ +DPP_STATUS dpp_tm_crdt_wfqsp_get(DPP_DEV_T *dev, + DPP_TM_CRDT_SPWFQ_START_NUM_T *p_spwfq_start_num); + +/***********************************************************/ +/** 获取调度器挂接配置参数 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param se_id 调度器编号 +* @param p_se_para_tbl 调度器参数 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/02/27 +************************************************************/ +DPP_STATUS dpp_tm_crdt_se_para_get(DPP_DEV_T *dev, ZXIC_UINT32 se_id, DPP_ETM_CRDT_SE_PARA_TBL_T *p_se_para_tbl); + + + +/***********************************************************/ +/** 配置QMU工作模式，2M节点或4M节点 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param mode 0-第一种工作模式2M节点，1-第二种工作模式4M节点 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/25 +************************************************************/ +DPP_STATUS dpp_tm_cfgmt_qmu_work_mode_set(DPP_DEV_T *dev, DPP_TM_QMU_WORK_MODE_E mode); + +/***********************************************************/ +/** 读取QMU工作模式，2M节点或4M节点 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_mode 0-第一种工作模式2M节点，1-第二种工作模式4M节点 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/25 +************************************************************/ +DPP_STATUS dpp_tm_cfgmt_qmu_work_mode_get(DPP_DEV_T *dev, DPP_TM_QMU_WORK_MODE_E *p_mode); + +/***********************************************************/ +/** 配置本地sa_id，SA模式下需要配置 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param sa_id 配置的sa_id值 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/25 ftm模式下使用 +************************************************************/ +DPP_STATUS dpp_tm_cfgmt_local_sa_id_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 sa_id); + +/***********************************************************/ +/** 读取本地sa_id，SA模式下有效 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_sa_id 读取的sa_id值 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/25 +************************************************************/ +DPP_STATUS dpp_tm_cfgmt_local_sa_id_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_sa_id); + +/***********************************************************/ +/** CPU设置的各级队列深度配置 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param level 拥塞避免支持层次号，0:队列级，1:端口级，2:系统级 +* @param q_len_use_cpu_set_en 0：选取RAM中读出的队列深度； +* @param 1：选取q_len_cpu_set值 +* @param q_len_cpu_set CPU设置的各级队列深度,单位为block。 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author yjd @date 2015/06/19 +************************************************************/ +DPP_STATUS dpp_tm_q_len_use_cpu_set(DPP_DEV_T *dev, + DPP_TM_CGAVD_LEVEL_E level, + ZXIC_UINT32 q_len_use_cpu_set_en, + ZXIC_UINT32 q_len_cpu_set); + +/***********************************************************/ +/** CPU设置的各级平均队列深度配置 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param level 拥塞避免支持层次号，0:队列级，1:端口级，2:系统级 +* @param q_avg_len_use_cpu_set_en 0：选取RAM中读出的队列深度； +* @param 1：选取q_avg_len_cpu_set值 +* @param q_avg_len_cpu_set CPU设置的各级平均队列深度。 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author yjd @date 2015/06/19 +************************************************************/ +DPP_STATUS dpp_tm_q_avg_len_use_cpu_set(DPP_DEV_T *dev, + DPP_TM_CGAVD_LEVEL_E level, + ZXIC_UINT32 q_avg_len_use_cpu_set_en, + ZXIC_UINT32 q_avg_len_cpu_set); + +/***********************************************************/ +/** 配置QMU查询队列Qos开关 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param q_id: 队列号 +* @param qos_sign: qos开关 0:关闭 1:开启 +* @param +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author yjd @date 2015/07/03 +************************************************************/ +DPP_STATUS dpp_tm_qmu_qos_sign_set(DPP_DEV_T *dev, + ZXIC_UINT32 q_id, + ZXIC_UINT32 qos_sign); + +/***********************************************************/ +/** 配置授权分发使能或者关闭 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param en 配置的值，0-关闭授权分发，1-使能授权分发 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/25 +************************************************************/ +DPP_STATUS dpp_tm_crdt_credit_en_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 en); + +/***********************************************************/ +/** 读取授权分发使能或者关闭 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_en 读出的值，0-关闭授权分发，1-使能授权分发 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/25 +************************************************************/ +DPP_STATUS dpp_tm_crdt_credit_en_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_en); + +/***********************************************************/ +/** 配置授权产生间隔 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param crdt_space_choose 授权发送间隔 0:固定16个周期 1：查表 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/03/10 +************************************************************/ +DPP_STATUS dpp_tm_crdt_space_choose_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 crdt_space_choose); + +/***********************************************************/ +/** 获得授权产生间隔 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param crdt_space_choose 授权发送间隔 0:固定16个周期 1：查表 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/03/10 +************************************************************/ +DPP_STATUS dpp_tm_crdt_space_choose_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_crdt_space_choose); + +/***********************************************************/ +/** 配置端口拥塞令牌桶使能 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param port_id 端口号：0~63 +* @param port_en 端口拥塞令牌桶使能，1表示不使用拥塞令牌桶的授权，0表示可以使用拥塞令牌桶授权 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/03/11 +************************************************************/ +DPP_STATUS dpp_tm_crdt_port_congest_en_set(DPP_DEV_T *dev, + ZXIC_UINT32 port_id, + ZXIC_UINT32 port_en); + +/***********************************************************/ +/** 获得端口拥塞令牌桶使能 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param port_id 端口号：0~120 +* @param p_port_en 端口拥塞令牌桶使能，1表示不使用拥塞令牌桶的授权，0表示可以使用拥塞令牌桶授权 +* +* @return +* @remark 无 +* @see +* @author djf @date 2015/03/11 +************************************************************/ +DPP_STATUS dpp_tm_crdt_port_congest_en_get(DPP_DEV_T *dev, + ZXIC_UINT32 port_id, + ZXIC_UINT32 *p_port_en); + +/***********************************************************/ +/** 流级中间级补充扫描机制使能配置 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param renew_scan_flow:0为不开启补充扫描 others:开启补充扫描，扫描间隔 +* @param renew_scan_mid:0为不开启补充扫描 others:开启补充扫描，扫描间隔 +* @param +* @return +* @remark 无 +* @see +* @author yjd @date 2015/07/03 +************************************************************/ +DPP_STATUS dpp_tm_crdt_renew_scan_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 renew_scan_flow, + ZXIC_UINT32 renew_scan_mid); + +/***********************************************************/ +/** 获取流级中间级补充扫描机制使能 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param renew_scan_flow:0为不开启补充扫描 others:开启补充扫描，扫描间隔 +* @param renew_scan_mid:0为不开启补充扫描 others:开启补充扫描，扫描间隔 +* @param +* @return +* @remark 无 +* @see +* @author yjd @date 2015/07/03 +************************************************************/ +DPP_STATUS dpp_tm_crdt_renew_scan_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *renew_scan_flow, + ZXIC_UINT32 *renew_scan_mid); + + +/***********************************************************/ +/**cpu配置flow_id的crs强制为normal或者off开关使能，用于检测SA模式下队列到授权流的多对一问题 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param flow_id:流号(和授权流号一一对应) +* en 强制配置crs的使能，0-不使能，1-使能 +* crs_value:强制配置crs的值2'b00:off; 2'b01:low; 2'b10:normal； +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cuiy @date 2016/04/25 +************************************************************/ +DPP_STATUS dpp_tm_crdt_crs_sheild_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 flow_id, ZXIC_UINT32 en, ZXIC_UINT32 crs_value); + + +/***********************************************************/ +/**获取flow_id的crs强制为normal或者off开关使能，用于检测SA模式下队列到授权流的多对一问题 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param flow_id:流号(和授权流号一一对应) +* en 强制配置crs的使能，0-不使能，1-使能 +* crs_value:强制配置crs的值2'b00:off; 2'b01:low; 2'b10:normal； +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cuiy @date 2016/04/25 +************************************************************/ +DPP_STATUS dpp_tm_crdt_crs_sheild_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_flow_id, ZXIC_UINT32 *p_en, ZXIC_UINT32 *p_crs_value); + +/***********************************************************/ +/** 控制授权速率的门限 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param index 0~6 +* @param rci_grade_th_0_data +* +* @return +* @remark 无 +* @see +* @author wush @date 2017/10/17 +************************************************************/ +DPP_STATUS dpp_tm_crdt_rci_grade_th_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 index, ZXIC_UINT32 rci_grade_th_0_data); + +DPP_STATUS dpp_tm_crdt_rci_grade_th_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 index, ZXIC_UINT32 *p_rci_grade_th_0_data); + + +/***********************************************************/ +/** 控制授权间隔的门限，建议大于等于0XF，不可取0； +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param index 0~7 +* @param asm_interval_0_data 控制授权间隔的门限，建议大于等于0XF，不可取0； +* +* @return +* @remark 无 +* @see +* @author wush @date 2017/10/17 +************************************************************/ +DPP_STATUS dpp_tm_crdt_asm_interval_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 index, ZXIC_UINT32 asm_interval_0_data); + +DPP_STATUS dpp_tm_crdt_asm_interval_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 index, ZXIC_UINT32 *p_asm_interval_0_data); + + +/***********************************************************/ +/** rci的级别 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_rci_grade_data +* +* @return +* @remark 无 +* @see +* @author wush @date 2017/10/17 +************************************************************/ +DPP_STATUS dpp_tm_crdt_rci_grade_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_rci_grade_data); + +DPP_STATUS dpp_tm_crdt_rci_value_r_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_crdt_rci_value_r_data); + +DPP_STATUS dpp_tm_crdt_interval_now_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_crdt_interval_now_data); + + +/***********************************************************/ +/** 配置crdt interval使能， +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param crdt_interval_en_cfg_data 授权分发间隔使能，1打开，0关闭 +* +* @return +* @remark 无 +* @see +* @author wush @date 2017/03/27 +************************************************************/ +DPP_STATUS dpp_tm_crdt_interval_en_cfg_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 crdt_interval_en_cfg_data); + +/***********************************************************/ +/**配置拥塞状态(有效链路数+UCN等级)到授权产生间隔的映射表 +* @param dev_id 设备编号 +* @param valid_serdes_num 有效的链路数(0~32) +* @param ucn_level UCN等级(0~7) +* @param cr_clk 授权产生间隔(0~0x3fffff) +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author wush @date 2017/03/28 +************************************************************/ +DPP_STATUS dpp_tm_crdt_cfgmt_interval_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 valid_serdes_num, + ZXIC_UINT32 ucn_level, + ZXIC_UINT32 cr_clk); + +/***********************************************************/ +/** 读取crdt interval使能 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param crdt_interval_en_cfg_data 授权分发间隔使能，1打开，0关闭 +* +* @return +* @remark 无 +* @see +* @author wush @date 2017/03/27 +************************************************************/ +DPP_STATUS dpp_tm_crdt_interval_en_cfg_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_crdt_interval_en_cfg_data); + + +/***********************************************************/ +/** 屏蔽ucn/asm_rdy的时能信号 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param ucn_rdy_shield_en 是否屏蔽ucn_rdy信号，1屏蔽，0不屏蔽 +* @param asm_rdy_shield_en 是否屏蔽asm_rdy信号，1屏蔽，0不屏蔽 +* +* @return +* @remark 无 +* @see +* @author wush @date 2017/10/17 +************************************************************/ +DPP_STATUS dpp_tm_crdt_ucn_asm_rdy_shield_en_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 ucn_rdy_shield_en, ZXIC_UINT32 asm_rdy_shield_en); + +DPP_STATUS dpp_tm_crdt_ucn_asm_rdy_shield_en_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_ucn_rdy_shield_en, ZXIC_UINT32 *p_asm_rdy_shield_en); + + +/***********************************************************/ +/** 配置QMU队列授权价值 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param credit_value 授权价值，默认值是400Byte +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/03/04 +************************************************************/ +DPP_STATUS dpp_tm_qmu_credit_value_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 credit_value); + +/***********************************************************/ +/** QMU DDR随机模式时，DDR随机组配置 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param ddr_num ddr组数，1-6组 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/03/04 +************************************************************/ +DPP_STATUS dpp_tm_qmu_ddr_rand_grp_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 ddr_num); + +/***********************************************************/ +/** 配置QMU DDR BANK随机模式 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param ddr_random 模式:0-轮询模式；1-随机模式 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/03/04 +************************************************************/ +DPP_STATUS dpp_tm_qmu_ddr_random_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 ddr_random); + +/***********************************************************/ +/** QMU配置完成寄存器，在QMU链表和DDR随机模式寄存器写入后，将此寄存器写1，完成QMU配置 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/03/04 +************************************************************/ +DPP_STATUS dpp_tm_qmu_cfg_done_set(ZXIC_UINT32 dev_id); + + +/***********************************************************/ +/** 配置CRS的e桶产生的crbal门限值 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param index crs组数：0~15 +* @param crs_th CRS产生的crbal门限值 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author xuhb @date 2021/02/14 +************************************************************/ +DPP_STATUS dpp_tm_qmu_crs_eir_th_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 index, + ZXIC_UINT32 crs_th); + + +/***********************************************************/ +/** 配置CRS产生的crbal门限值 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param index crs组数：0~15 +* @param crs_th CRS产生的crbal门限值 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/03/11 +************************************************************/ +DPP_STATUS dpp_tm_qmu_crs_th_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 index, + ZXIC_UINT32 crs_th); + +/***********************************************************/ +/** 配置CRS产生的空队列确保门限值 +* @param dev_id 设备索引编号 +* @param tm_type 0-ETM,1-FTM +* @param que_type 队列类型编号(0~15) +* @param empty_que_ack_th 空队列确保授权门限 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/03/09 +************************************************************/ +DPP_STATUS dpp_tm_qmu_crs_th2_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 que_type, + ZXIC_UINT32 empty_que_ack_th); + +/***********************************************************/ +/** 配置QMU端口间交织模式 +* @param dev_id 设备索引编号 +* @param tm_type 0-ETM,1-FTM +* @param pkt_blk_mode 交织模式: 1-按包交织; 0-按block交织SA模式只能配置为1 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author szq @date 2015/03/25 +************************************************************/ +DPP_STATUS dpp_tm_qmu_pkt_blk_mode_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 pkt_blk_mode); + +/***********************************************************/ +/** 获取QMU端口间交织模式 +* @param dev_id 设备索引编号 +* @param tm_type 0-ETM,1-FTM +* @param p_pkt_blk_mode 交织模式: 0-按包交织; 1-按block交织SA模式只能配置为1 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author szq @date 2015/03/25 +************************************************************/ +DPP_STATUS dpp_tm_qmu_pkt_blk_mode_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_pkt_blk_mode); + +/***********************************************************/ +/** 配置读命令老化使能 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param aged_en 读命令老化使能：0：不使能；1：使能 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/03/11 +************************************************************/ +DPP_STATUS dpp_tm_qmu_wr_aged_en_set(DPP_DEV_T *dev, ZXIC_UINT32 aged_en); + +/***********************************************************/ +/** 配置读命令老化速率 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param scan_time 读命令老化速率（扫描间隔时间） +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/03/11 +************************************************************/ +DPP_STATUS dpp_tm_qmu_wr_aged_scan_time_set(DPP_DEV_T *dev, ZXIC_UINT32 scan_time); + +/***********************************************************/ +/** 获得读命令老化速率 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_scan_time 读命令老化速率（扫描间隔时间） +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/03/11 +************************************************************/ +DPP_STATUS dpp_tm_qmu_wr_aged_scan_time_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_scan_time); + + +/***********************************************************/ +/** 配置QMU队列到目的SAId的映射ETM 模式没有， +FTM 模式才有1024个。 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param que_id 队列号 +* @param dest_said 目的said +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author szq @date 2015/04/08 +************************************************************/ +DPP_STATUS dpp_tm_qmu_qcfg_dest_id_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 que_id, ZXIC_UINT32 dest_said); + + +/***********************************************************/ +/** 获取QMU队列到目的SAId的映射ETM 模式没有， +FTM 模式才有1024个。 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param que_id 队列号 +* @param p_dest_said 目的said +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author szq @date 2015/04/08 +************************************************************/ +DPP_STATUS dpp_tm_qmu_qcfg_dest_id_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 que_id, ZXIC_UINT32 *p_dest_said); + +/***********************************************************/ +/** 配置出队暂存使用的进程总数 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param used_inall 出队暂存使用的进程总数=19-N，默认3表示使用16个进程 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/06/18 +************************************************************/ +DPP_STATUS dpp_tm_qmu_pid_use_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 used_inall); + +/***********************************************************/ +/** 获得出队暂存使用的进程总数 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_used_inall 出队暂存使用的进程总数=19-N，默认3表示使用16个进程 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/06/23 +************************************************************/ +DPP_STATUS dpp_tm_qmu_pid_use_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_used_inall); + +/***********************************************************/ +/** 配置出队暂存自回加进程总数阈值 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param round_th 出队暂存自回加进程总数阈值=19-N，默认4表示使用15个进程就自回加 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/06/18 +************************************************************/ +DPP_STATUS dpp_tm_qmu_pid_round_th_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 round_th); + +/***********************************************************/ +/** 获得出队暂存自回加进程总数阈值 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_round_th 出队暂存自回加进程总数阈值=19-N，默认4表示使用15个进程就自回加 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/06/23 +************************************************************/ + +DPP_STATUS dpp_tm_qmu_pid_round_th_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_round_th); + +/***********************************************************/ +/** 配置CRS发送强制使能 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param en 配置的值，0-不使能，1-使能 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/03/04 +************************************************************/ +DPP_STATUS dpp_tm_qmu_crs_force_en_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 en); + +/***********************************************************/ +/** 配置CRS发送强制的队列 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param q_id 队列号 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/03/04 +************************************************************/ +DPP_STATUS dpp_tm_qmu_crs_force_q_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 q_id); + + +/***********************************************************/ +/** 配置CRS发送强置的状态 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param crs_state CRS发送强置的状态 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/06/18 +************************************************************/ +DPP_STATUS dpp_tm_qmu_crs_force_state_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 crs_state); + +/***********************************************************/ +/** 配置特定队列发送特定CRS +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param qnum 队列号 +* qcfg_qsch_crs_force_crs:CRS状态(0：off；1：normal。) + qcfg_qsch_crs_force_en:CRS发送强置使能(0：不使能；1：使能。) +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/03/04 +************************************************************/ +DPP_STATUS dpp_tm_qmu_qnum_crs_force(ZXIC_UINT32 dev_id, + ZXIC_UINT32 qnum, + ZXIC_UINT32 qcfg_qsch_crs_force_crs, + ZXIC_UINT32 qcfg_qsch_crs_force_en); + + +/***********************************************************/ +/** 配置CRS状态 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param qnum 队列号 +* @param state +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/06/19 +************************************************************/ +DPP_STATUS dpp_tm_qmu_crs_state_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 qnum, + ZXIC_UINT32 state); + +/***********************************************************/ +/** 获得CRS状态 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param qnum 队列号 +* @param p_state +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/06/23 +************************************************************/ +DPP_STATUS dpp_tm_qmu_crs_state_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 qnum, + ZXIC_UINT32 *p_state); + +/***********************************************************/ +/** 配置自动授权队列范围 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param first_que 自授权起始队列号 +* @param last_que 自授权终止队列号 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/06/19 +************************************************************/ +DPP_STATUS dpp_tm_qmu_auto_credit_que_set(DPP_DEV_T *dev, + ZXIC_UINT32 first_que, + ZXIC_UINT32 last_que); + +/***********************************************************/ +/** 获得自动授权队列范围 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_first_que 自授权起始队列号 +* @param p_last_que 自授权终止队列号 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/06/23 +************************************************************/ +DPP_STATUS dpp_tm_qmu_auto_credit_que_get(DPP_DEV_T *dev, + ZXIC_UINT32 *p_first_que, + ZXIC_UINT32 *p_last_que); + +/***********************************************************/ +/** 配置自动授权开启使能及扫描速率 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param auto_crdt_en 自动授权开启使能，默认关闭。0：关闭；1：开启 +* @param auto_crdt_rate 自授权速率配置 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/06/19 +************************************************************/ +DPP_STATUS dpp_tm_qmu_auto_credit_rate_set(DPP_DEV_T *dev, + ZXIC_UINT32 auto_crdt_en, + ZXIC_UINT32 auto_crdt_rate); + +/***********************************************************/ +/** 获得自动授权开启使能及扫描速率 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_auto_crdt_en 自动授权开启使能，默认关闭。0：关闭；1：开启 +* @param p_auto_crdt_rate 自授权速率配置 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/06/23 +************************************************************/ +DPP_STATUS dpp_tm_qmu_auto_credit_rate_get(DPP_DEV_T *dev, + ZXIC_UINT32 *p_auto_crdt_en, + ZXIC_UINT32 *p_auto_crdt_rate); + +/***********************************************************/ +/** 配置授权丢弃使能 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param all_drop_en 所有授权丢弃使能：1：允许丢弃所有授权；0：仅允许丢弃拥塞授权 +* @param drop_en 授权丢弃使能：1：允许丢弃授权；0：禁止丢弃授权 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/06/23 +************************************************************/ +DPP_STATUS dpp_tm_qmu_crbal_drop_en_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 all_drop_en, + ZXIC_UINT32 drop_en); + +/***********************************************************/ +/** 获得授权丢弃使能 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_all_drop_en 所有授权丢弃使能：1：允许丢弃所有授权；0：仅允许丢弃拥塞授权 +* @param p_drop_en 授权丢弃使能：1：允许丢弃授权；0：禁止丢弃授权 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/06/23 +************************************************************/ +DPP_STATUS dpp_tm_qmu_crbal_drop_en_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *p_all_drop_en, + ZXIC_UINT32 *p_drop_en); + +/***********************************************************/ +/**设置自然拥塞反压门限值 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param +* @return +* @remark 无 +* @see +* @author yjd @date 2015/07/16 +************************************************************/ +DPP_STATUS dpp_tm_qmu_qcfg_csch_congest_th_set(DPP_DEV_T *dev, ZXIC_UINT32 port_id, ZXIC_UINT32 qmu_congest_th); + +/***********************************************************/ +/**获取自然拥塞反压门限值 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param +* @return +* @remark 无 +* @see +* @author yjd @date 2015/07/16 +************************************************************/ +DPP_STATUS dpp_tm_qmu_qcfg_csch_congest_th_get(DPP_DEV_T *dev, ZXIC_UINT32 port_id, ZXIC_UINT32 *p_qmu_congest_th); + +/***********************************************************/ +/**设置CMD_SCH分优先级反压门限值 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param +* @return +* @remark 无 +* @see +* @author yjd @date 2015/07/16 +************************************************************/ +DPP_STATUS dpp_tm_qmu_qcfg_csch_sp_fc_th_set(DPP_DEV_T *dev, ZXIC_UINT32 port_id, ZXIC_UINT32 q_pri, ZXIC_UINT32 qmu_sp_fc_th); + +/***********************************************************/ +/**获取自然拥塞反压门限值 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param +* @return +* @remark 无 +* @see +* @author yjd @date 2015/07/16 +************************************************************/ +DPP_STATUS dpp_tm_qmu_qcfg_csch_sp_fc_th_get(DPP_DEV_T *dev, ZXIC_UINT32 port_id, ZXIC_UINT32 q_pri, ZXIC_UINT32 *p_qmu_sp_fc_th); + +/***********************************************************/ +/** 配置QMU需要检测流控的端口号 +* @param dev_id 设备号 +* @param tm_type 0-ETM,1-FTM +* @param port_id 端口号 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/05/07 +************************************************************/ +DPP_STATUS dpp_tm_qmu_observe_portfc_set(DPP_DEV_T *dev, ZXIC_UINT32 port_id); + +/***********************************************************/ +/** 配置pfc使能 +* @param dev_id 设备编号 +* @param pfc_en 配置的值，0-不使能pfc，1-使能pfc +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author lsy @date 2022/08/22 +************************************************************/ +DPP_STATUS dpp_tm_qmu_pfc_en_set(DPP_DEV_T *dev, ZXIC_UINT32 pfc_en); + +/***********************************************************/ +/** 读取pfc使能 +* @param dev_id 设备编号 +* @param pfc_en 配置的值，0-不使能pfc，1-使能pfc +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author lsy @date 2022/08/22 +************************************************************/ +DPP_STATUS dpp_tm_qmu_pfc_en_get(DPP_DEV_T *dev, ZXIC_UINT32 *pfc_en); + +/***********************************************************/ +/** 配置端口pfc掩码 +* @param dev_id 设备编号 +* @param port_id 端口号：0~63 +* @param port_en 端口掩码配置，1pfc模式下该端口接收olif的优先级反压， +* 0pfc模式下该端口不接受olif的优先级反压，并将反压信号全部置1 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author lsy @date 2022/08/22 +************************************************************/ +DPP_STATUS dpp_tm_qmu_port_pfc_make_set(DPP_DEV_T *dev, + ZXIC_UINT32 port_id, + ZXIC_UINT32 port_en); + +/***********************************************************/ +/** 获得端口pfc掩码 +* @param dev_id 设备编号 +* @param port_id 端口号：0~63 +* @param port_en 端口掩码配置，1pfc模式下该端口接收olif的优先级反压， +* 0pfc模式下该端口不接受olif的优先级反压，并将反压信号全部置1 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author lsy @date 2022/08/22 +************************************************************/ +DPP_STATUS dpp_tm_qmu_port_pfc_make_get(DPP_DEV_T *dev, + ZXIC_UINT32 port_id, + ZXIC_UINT32 *p_port_en); + + + +/***********************************************************/ +/** QMU初始化配置场景一：4组*2bank，MMU开启rotatjon，MMU实际分配4~7组，每组2~3bank +* @param dev_id 设备编号 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cuiy @date 2016/11/17 +************************************************************/ +DPP_STATUS dpp_etm_qmu_init_set_1(ZXIC_UINT32 dev_id); + + +/***********************************************************/ +/** QMU初始化配置场景一：4组*2bank，MMU开启rotatjon，MMU实际分配0~3组，每组2~3bank +* @param dev_id 设备编号 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cuiy @date 2016/11/17 +************************************************************/ +DPP_STATUS dpp_ftm_qmu_init_set_1(ZXIC_UINT32 dev_id); + + +/***********************************************************/ +/** QMU初始化配置场景一ddr4模式，开启MMU/IP rotatjon，tm看到4组*2bank，对应DDR分配4~7组，每组2~3bank************* +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cuiy @date 2016/11/17 +************************************************************/ +DPP_STATUS dpp_tm_qmu_init_set_1(ZXIC_UINT32 dev_id); + + +/***********************************************************/ +/** QMU初始化配置场景二：ddr3模式，tm看到4组*4bank，对应DDR分配4~7组，每组2~3,6~7bank +* @param dev_id 设备编号 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cuiy @date 2016/11/17 +************************************************************/ +DPP_STATUS dpp_etm_qmu_init_set_2(ZXIC_UINT32 dev_id); + + +/***********************************************************/ +/** QMU初始化配置场景二：ddr3模式，tm看到4组*4bank，对应DDR分配0~3组，每组2~3,6~7bank* +* @param dev_id 设备编号 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cuiy @date 2016/11/17 +************************************************************/ +DPP_STATUS dpp_ftm_qmu_init_set_2(ZXIC_UINT32 dev_id); + + +/***********************************************************/ +/** QMU初始化配置场景二：ddr3模式，tm看到4组*4bank，对应DDR分配4~7组，每组2~3,6~7bank +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cuiy @date 2016/11/17 +************************************************************/ +DPP_STATUS dpp_tm_qmu_init_set_2(ZXIC_UINT32 dev_id); + + +/***********************************************************/ +/** QMU初始化配置场景二：ddr3模式，tm看到4组*4bank，对应DDR分配4~7组，每组2~3,6~7bank +* depth=64,代表16k +* @param dev_id 设备编号 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cuiy @date 2016/11/17 +************************************************************/ +DPP_STATUS dpp_etm_qmu_init_set_pd16k_2(ZXIC_UINT32 dev_id, ZXIC_UINT32 depth); + + +/***********************************************************/ +/** QMU初始化配置场景二：ddr3模式，8组*8bank +* depth=64,代表16k +* @param dev_id 设备编号 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author sun @date 2023/04/12 +************************************************************/ +DPP_STATUS dpp_etm_qmu_init_set_chuk32(ZXIC_UINT32 dev_id, ZXIC_UINT32 depth); + +/***********************************************************/ +/** QMU初始化配置场景二：ddr3模式，tm看到4组*4bank，对应DDR分配0~3组，每组2~3,6~7bank* +* @param dev_id 设备编号 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cuiy @date 2016/11/17 +************************************************************/ +DPP_STATUS dpp_ftm_qmu_init_set_pd16k_2(ZXIC_UINT32 dev_id, ZXIC_UINT32 depth); + + +/***********************************************************/ +/** QMU初始化配置场景二：ddr3模式，tm看到4组*4bank，对应DDR分配4~7组，每组2~3,6~7bank +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cuiy @date 2016/11/17 +************************************************************/ +DPP_STATUS dpp_tm_qmu_init_set_pd16k_2(ZXIC_UINT32 dev_id, ZXIC_UINT32 depth); + +/***********************************************************/ +/** QMU初始化配置场景：ddr3模式，8组ddr*8bank +* @param dev_id 设备编号 +* @param depth bank depth +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author sun @date 2023/04/12 +************************************************************/ +DPP_STATUS dpp_tm_qmu_init_set_chuk32(ZXIC_UINT32 dev_id, ZXIC_UINT32 depth); + + +/***********************************************************/ +/** QMU初始化配置场景三：8组*2bank，MMU开启rotatjon，MMU实际分配0~7组，每组6~7bank +* @param dev_id 设备编号 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cuiy @date 2016/11/17 +************************************************************/ +DPP_STATUS dpp_etm_qmu_init_set_3(ZXIC_UINT32 dev_id); + +/***********************************************************/ +/** QMU初始化配置场景三：8组*2bank，MMU开启rotatjon，MMU实际分配0~3组，每组2~3bank +* @param dev_id 设备编号 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cuiy @date 2016/11/17 +************************************************************/ +DPP_STATUS dpp_ftm_qmu_init_set_3(ZXIC_UINT32 dev_id); + +/***********************************************************/ +/** QMU初始化配置场景三ETM: 8组*2bank，MMU开启rotatjon，MMU实际分配0~7组，每组6~7bank +* FTM: 8组*2bank，MMU开启rotatjon，MMU实际分配0~3组，每组2~3bank +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cuiy @date 2016/11/17 +************************************************************/ +DPP_STATUS dpp_tm_qmu_init_set_3(ZXIC_UINT32 dev_id); + + +/***********************************************************/ +/**场景4：TM共享2组ddr:FTM为2、4组ddr的01bank，ETM为2、4组ddr 23bank +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xuhb @date 2020/06/06 +************************************************************/ +DPP_STATUS dpp_etm_qmu_init_set_4(ZXIC_UINT32 dev_id); + +/***********************************************************/ +/**场景4：TM共享2组ddr:FTM为2、4组ddr的01bank，ETM为2、4组ddr 23bank +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xuhb @date 2020/06/06 +************************************************************/ +DPP_STATUS dpp_ftm_qmu_init_set_4(ZXIC_UINT32 dev_id); + +/***********************************************************/ +/**场景4：TM共享2组ddr:FTM为2、4组ddr的01bank，ETM为2、4组ddr 23bank +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xuhb @date 2020/06/06 +************************************************************/ +DPP_STATUS dpp_tm_qmu_init_set_4(ZXIC_UINT32 dev_id); + + +/***********************************************************/ +/** 场景5：TM共享4组ddr:FTM为1234组ddr的01bank，ETM为1234组ddr 23bank +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xuhb @date 2020/06/06 +************************************************************/ +DPP_STATUS dpp_etm_qmu_init_set_5(ZXIC_UINT32 dev_id); + + +/***********************************************************/ +/** 场景5：TM共享4组ddr:FTM为1234组ddr的01bank，ETM为1234组ddr 23bank +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xuhb @date 2020/06/06 +************************************************************/ +DPP_STATUS dpp_ftm_qmu_init_set_5(ZXIC_UINT32 dev_id); + + +/***********************************************************/ +/** 场景5：TM共享4组ddr:FTM为1234组ddr的01bank，ETM为1234组ddr 23bank +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xuhb @date 2020/06/06 +************************************************************/ +DPP_STATUS dpp_tm_qmu_init_set_5(ZXIC_UINT32 dev_id); + + +/***********************************************************/ +/** QMU初始化配置场景6：4组*2bank，MMU实际分配ftm:4,6,7,9组(01bank); etm:4,6,7,9组(23bank) +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xuhb @date 2020/05/13 +************************************************************/ +DPP_STATUS dpp_tm_qmu_init_set_6(ZXIC_UINT32 dev_id); + +/***********************************************************/ +/** QMU初始化配置场景6：4组*2bank，MMU实际分配ftm:4,6,7,9组(01bank); etm:4,6,7,9组(23bank) +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xuhb @date 2020/05/13 +************************************************************/ +DPP_STATUS dpp_etm_qmu_init_set_6(ZXIC_UINT32 dev_id); + + +/***********************************************************/ +/** QMU初始化配置场景6：4组*2bank，MMU实际分配ftm:4,6,7,9组(01bank); etm:4,6,7,9组(23bank) +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xuhb @date 2020/05/13 +************************************************************/ +DPP_STATUS dpp_ftm_qmu_init_set_6(ZXIC_UINT32 dev_id); + +/***********************************************************/ +/** QMU初始化配置场景6：4组*4bank，MMU实际分配1,2(ftm); 5,6(etm)组，每组2~3 6~7bank +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cuiy @date 2016/11/17 +************************************************************/ +DPP_STATUS dpp_tm_qmu_init_set_7(ZXIC_UINT32 dev_id); + +/***********************************************************/ +/** QMU初始化配置场景6：4组*4bank，MMU实际分配5~6组，每组2~3 6~7bank +* @param dev_id 设备编号 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cuiy @date 2016/11/17 +************************************************************/ +DPP_STATUS dpp_etm_qmu_init_set_7(ZXIC_UINT32 dev_id); + + +/***********************************************************/ +/** QMU初始化配置场景6：4组*4bank，MMU实际分配1~2组，每组2~3 6~7bank +* @param dev_id 设备编号 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cuiy @date 2016/11/17 +************************************************************/ +DPP_STATUS dpp_ftm_qmu_init_set_7(ZXIC_UINT32 dev_id); + + +/***********************************************************/ +/** QMU初始化配置场景6：4组*4bank，MMU实际分配1,2(ftm); 5,6(etm)组，每组2~3 6~7bank +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cuiy @date 2016/11/17 +************************************************************/ +DPP_STATUS dpp_tm_qmu_init_set_8(ZXIC_UINT32 dev_id); + +/***********************************************************/ +/** QMU初始化配置场景6：4组*4bank，MMU实际分配5~6组，每组2~3 6~7bank +* @param dev_id 设备编号 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cuiy @date 2016/11/17 +************************************************************/ +DPP_STATUS dpp_etm_qmu_init_set_8(ZXIC_UINT32 dev_id); + + +/***********************************************************/ +/** QMU初始化配置场景6：4组*4bank，MMU实际分配1~2组，每组2~3 6~7bank +* @param dev_id 设备编号 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cuiy @date 2016/11/17 +************************************************************/ +DPP_STATUS dpp_ftm_qmu_init_set_8(ZXIC_UINT32 dev_id); + + +/***********************************************************/ +/** QMU初始化配置场景9：4组*2bank，MMU实际分配ftm:6,7,8,9组(01bank); etm:6,7,8,9组(23bank) +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xuhb @date 2020/09/28 +************************************************************/ +DPP_STATUS dpp_tm_qmu_init_set_9(ZXIC_UINT32 dev_id); + +/***********************************************************/ +/** QMU初始化配置场景9：4组*2bank，MMU实际分配ftm:6,7,8,9组(01bank); etm:6,7,8,9组(23bank) +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xuhb @date 2020/09/28 +************************************************************/ +DPP_STATUS dpp_etm_qmu_init_set_9(ZXIC_UINT32 dev_id); + + +/***********************************************************/ +/** QMU初始化配置场景9：4组*2bank，MMU实际分配ftm:6,7,8,9组(01bank); etm:6,7,8,9组(23bank) +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xuhb @date 2020/09/28 +************************************************************/ +DPP_STATUS dpp_ftm_qmu_init_set_9(ZXIC_UINT32 dev_id); + +/***********************************************************/ +/** QMU初始化配置场景10：独享2组*8bank，MMU实际分配1,2; etm or ftm使用0-7bank +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xuhb @date 2020/12/16 +************************************************************/ +DPP_STATUS dpp_etm_qmu_init_set_10(ZXIC_UINT32 dev_id); + +/***********************************************************/ +/** QMU初始化配置场景10：独享2组*8bank，MMU实际分配1,2; etm or ftm使用0-7bank +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xuhb @date 2020/12/16 +************************************************************/ +DPP_STATUS dpp_ftm_qmu_init_set_10(ZXIC_UINT32 dev_id); + +/***********************************************************/ +/** QMU初始化配置场景10：独享2组*8bank，MMU实际分配1,2; etm or ftm使用0-7bank +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xuhb @date 2020/12/16 +************************************************************/ +DPP_STATUS dpp_tm_qmu_init_set_10(ZXIC_UINT32 dev_id); + + +/***********************************************************/ +/**场景11：TM共享2组ddr:FTM为ddr_no1、ddr_no2组ddr的01bank，ETM为ddr_no1、ddr_no2组ddr 23bank +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xuhb @date 2020/06/06 +************************************************************/ +DPP_STATUS dpp_etm_qmu_init_set_11(ZXIC_UINT32 dev_id, ZXIC_UINT32 ddr_no1, ZXIC_UINT32 ddr_no2); + +/***********************************************************/ +/**场景11：TM共享2组ddr:FTM为ddr_no1、ddr_no2组ddr的01bank，ETM为ddr_no1、ddr_no2组ddr 23bank +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xuhb @date 2020/06/06 +************************************************************/ +DPP_STATUS dpp_ftm_qmu_init_set_11(ZXIC_UINT32 dev_id, ZXIC_UINT32 ddr_no1, ZXIC_UINT32 ddr_no2); + +/***********************************************************/ +/**场景4：TM共享2组ddr:FTM为ddr_no1,ddr_no2组ddr的01bank，ETM为ddr_no1,ddr_no2组ddr 23bank +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xuhb @date 2020/06/06 +************************************************************/ +DPP_STATUS dpp_tm_qmu_init_set_11(ZXIC_UINT32 dev_id, ZXIC_UINT32 ddr_no1, ZXIC_UINT32 ddr_no2); + + +/***********************************************************/ +/** +QMU/MMU初始化配置场景12：每个tm只用1组*4bank，MMU实际分配ftm:0-9中指定组(4567bank); etm:0-9中指定组(0123bank) +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xuhb @date 2020/4/14 +************************************************************/ +DPP_STATUS dpp_ftm_qmu_init_set_12(ZXIC_UINT32 dev_id, ZXIC_UINT32 ftm_ddr_no); + + +/***********************************************************/ +/** +QMU/MMU初始化配置场景15：每个tm只用1组*4bank，MMU实际分配ftm:0-9中指定组(4567bank); etm:0-9中指定组(0123bank) +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xuhb @date 2020/4/14 +************************************************************/ +DPP_STATUS dpp_tm_qmu_init_set_12(ZXIC_UINT32 dev_id, ZXIC_UINT32 ddr_no); + + + +/***********************************************************/ +/** QMU初始化配置场景13：TM独享4组ddr:FTM为指定4组ddr的0~7bank， + ETM为指定4组ddr 0~7bank +* @param dev_id 设备编号 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xuhb @date 2016/11/17 +************************************************************/ +DPP_STATUS dpp_etm_qmu_init_set_13(ZXIC_UINT32 dev_id, ZXIC_UINT32 ddr_no); + +/***********************************************************/ +/** QMU初始化配置场景13：TM独享4组ddr:FTM为指定4组ddr的0~7bank， + ETM为指定4组ddr 0~7bank +* @param dev_id 设备编号 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xuhb @date 2016/11/17 +************************************************************/ +DPP_STATUS dpp_ftm_qmu_init_set_13(ZXIC_UINT32 dev_id, ZXIC_UINT32 ddr_no); + + +/***********************************************************/ +/** QMU/MMU初始化配置场景13：TM独享4组ddr:FTM为指定4组ddr的0~7bank + ETM为指定4组ddr的0-7bank +* MMU开启rotatjon +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xuhb @date 2016/11/17 +************************************************************/ +DPP_STATUS dpp_tm_qmu_init_set_13(ZXIC_UINT32 dev_id, ZXIC_UINT32 ddr_no); + + +/** QMU/MMU初始化配置场景14：每个tm只用1组*8bank，MMU实际分配ftm:0-9中指定组(0-7bank); etm:0-9中指定组(0-7bank) +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xuhb @date 2020/4/14 +************************************************************/ +DPP_STATUS dpp_tm_qmu_init_set_14(ZXIC_UINT32 dev_id, ZXIC_UINT32 etm_ddr_no, ZXIC_UINT32 ftm_ddr_no); + + +/** QMU/MMU初始化配置场景14：每个tm只用1组*8bank，MMU实际分配ftm:0-9中指定组(0-7bank); etm:0-9中指定组(0-7bank) +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xuhb @date 2020/4/14 +************************************************************/ +DPP_STATUS dpp_etm_qmu_init_set_14(ZXIC_UINT32 dev_id, ZXIC_UINT32 etm_ddr_no); + + +/** QMU/MMU初始化配置场景14：每个tm只用1组*8bank，MMU实际分配ftm:0-9中指定组(0-7bank); etm:0-9中指定组(0-7bank) +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xuhb @date 2020/4/14 +************************************************************/ +DPP_STATUS dpp_ftm_qmu_init_set_14(ZXIC_UINT32 dev_id, ZXIC_UINT32 ftm_ddr_no); + + +/** QMU/MMU初始化配置场景15：每个tm只用1组*4bank，MMU实际分配ftm:0-9中指定组(0123bank); etm:0-9中指定组(0123bank) +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xuhb @date 2020/4/14 +************************************************************/ +DPP_STATUS dpp_tm_qmu_init_set_15(ZXIC_UINT32 dev_id, ZXIC_UINT32 etm_ddr_no, ZXIC_UINT32 ftm_ddr_no); + + +/** QMU/MMU初始化配置场景15：每个tm只用1组*4bank，MMU实际分配ftm:0-9中指定组(0123bank); etm:0-9中指定组(0123bank) +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xuhb @date 2020/4/14 +************************************************************/ +DPP_STATUS dpp_etm_qmu_init_set_15(ZXIC_UINT32 dev_id, ZXIC_UINT32 etm_ddr_no); + + +/** QMU/MMU初始化配置场景15：每个tm只用1组*4bank，MMU实际分配ftm:0-9中指定组(0123bank); etm:0-9中指定组(0123bank) +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xuhb @date 2020/4/14 +************************************************************/ +DPP_STATUS dpp_ftm_qmu_init_set_15(ZXIC_UINT32 dev_id, ZXIC_UINT32 ftm_ddr_no); + + +/***********************************************************/ +/** QMU初始化配置场景16：独享2组*8bank，MMU实际分配1,2; etm or ftm使用0-7bank +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xuhb @date 2020/12/16 +************************************************************/ +DPP_STATUS dpp_tm_qmu_init_set_16(ZXIC_UINT32 dev_id, ZXIC_UINT32 etm_ddr_no, ZXIC_UINT32 ftm_ddr_no); + +/***********************************************************/ +/** QMU初始化配置场景16：独享2组*8bank，MMU实际分配1,2; etm or ftm使用0-7bank +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xuhb @date 2020/12/16 +************************************************************/ +DPP_STATUS dpp_etm_qmu_init_set_16(ZXIC_UINT32 dev_id, ZXIC_UINT32 ftm_ddr_no); + +/***********************************************************/ +/** QMU初始化配置场景16：独享2组*8bank，MMU实际分配1,2; etm or ftm使用0-7bank +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xuhb @date 2020/12/16 +************************************************************/ +DPP_STATUS dpp_ftm_qmu_init_set_16(ZXIC_UINT32 dev_id, ZXIC_UINT32 etm_ddr_no); + +/***********************************************************/ +/** 64k队列的简单挂接函数配置 +*flow0~65535 -> ses0~4095 -> pp0 +:具体为flow0~15挂接到ses0的sp0，flow16~31挂接到ses1的sp0，以此类推 +* ses到PP的挂接都是挂接于pp0的sp0 +*@param dev_id 设备编号 +* port_id端口号 +* @ +* @return +* @remark 无 +* @see +* @author cy @date 2015/06/30 +************************************************************/ +DPP_STATUS dpp_tm_crdt_sch_64k_test(ZXIC_UINT32 dev_id, ZXIC_UINT32 port_id); + + +/***********************************************************/ +/** 把整数分解成(指定位长)最高有效数和(2的)指数位数的形式，data=p_remdata*2^(p_exp) +* @param data 需要转换前的数 +* @param rembitsum 余数的位数 +* @param p_remdata 余数大小 +* @param p_exp 指数大小 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/27 +************************************************************/ +DPP_STATUS dpp_tm_rem_and_exp_translate(ZXIC_UINT32 data, + ZXIC_UINT32 rembitsum, + ZXIC_UINT32 *p_remdata, + ZXIC_UINT32 *p_exp); + +/***********************************************************/ +/** 配置统计计数寄存器的统计方式 +* @param dev_id 设备编号 +* @param qnum 支持2组统计寄存器，0-qnum1，1-qnum2 +* @param mode 统计方式，0-统计全部队列，1-统计指定q_id +* @param q_id mode=1时生效，统计该队列的信息 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/03/04 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_stat_q_set(ZXIC_UINT32 dev_id, + DPP_ETM_CGAVD_STAT_QNUM_E qnum, + DPP_ETM_CGAVD_STAT_MODE_E mode, + ZXIC_UINT32 q_id); + +/***********************************************************/ +/** 读取统计计数寄存器的计数信息 +* @param dev_id 设备编号 +* @param qnum 支持2组统计寄存器，0-qnum1，1-qnum2 +* @param p_para 获得的统计信息 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/03/04 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_stat_q_get(ZXIC_UINT32 dev_id, + DPP_ETM_CGAVD_STAT_QNUM_E qnum, + DPP_ETM_CGAVD_STAT_INFO_T *p_para); + +/***********************************************************/ +/** 配置等价包长 +* @param dev_id +* @param tm_type 0-ETM,1-FTM +* @param p_equal_pkt_len 等价包长 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/28 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_equal_pkt_len_para_set(DPP_DEV_T *dev, + DPP_ETM_EQUAL_PKT_LEN_PARA_T *p_equal_pkt_len); + +/***********************************************************/ +/** 读取等价包长 +* @param dev_id +* @param tm_type 0-ETM,1-FTM +* @param p_equal_pkt_len 等价包长 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/28 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_equal_pkt_len_para_get(DPP_DEV_T *dev, + DPP_ETM_EQUAL_PKT_LEN_PARA_T *p_equal_pkt_len); + +/***********************************************************/ +/** 动态门限放大因子参数配置 +* @param dev_id +* @param tm_type 0-ETM,1-FTM +* @param p_amplify_gene_para 动态门限放大因子参数 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/28 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_amplify_gene_para_set(DPP_DEV_T *dev, + DPP_ETM_AMPLIFY_GENE_PARA_T *p_amplify_gene_para); + + +/***********************************************************/ +/** 动态门限放大因子参数获取 +* @param dev_id +* @param tm_type 0-ETM,1-FTM +* @param p_amplify_gene_para 动态门限放大因子参数 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/28 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_amplify_gene_para_get(DPP_DEV_T *dev, + DPP_ETM_AMPLIFY_GENE_PARA_T *p_amplify_gene_para); + +/***********************************************************/ +/** 配置等价包长阈值 +* @param dev_id +* @param tm_type 0-ETM,1-FTM +* @param p_equal_pkt_len_th 等价包长阈值 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/28 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_equal_pkt_len_th_para_set(DPP_DEV_T *dev, + DPP_ETM_EQUAL_PKT_LEN_TH_PARA_T *p_equal_pkt_len_th); + +/***********************************************************/ +/** 配置QMU DDR BANK随机模式 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_ddr_random 模式:0-轮询模式；1-随机模式 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/03/04 +************************************************************/ +DPP_STATUS dpp_tm_qmu_ddr_random_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_ddr_random); + +/***********************************************************/ +/** 读取等价包长阈值 +* @param dev_id +* @param tm_type 0-ETM,1-FTM +* @param p_equal_pkt_len_th 等价包长阈值 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/28 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_equal_pkt_len_th_para_get(DPP_DEV_T *dev, + DPP_ETM_EQUAL_PKT_LEN_TH_PARA_T *p_equal_pkt_len_th); + + + +/***********************************************************/ +/** 读取全部队列的计数信息 +* @param dev_id 设备编号* +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 使用第2组统计寄存器进行统计 +* @see +* @author yjd @date 2015/07/04 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_stat_q_all_get_diag(ZXIC_UINT32 dev_id); + +/***********************************************************/ +/** 读取某一队列统计计数寄存器的计数信息 +* @param dev_id 设备编号 +* @param q_id 统计该队列的信息 +* 使用第1组统计寄存器进行统计 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author yjd @date 2015/07/04 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_stat_q_single_get_diag(ZXIC_UINT32 dev_id); + + + +/***********************************************************/ +/** 配置默认队列使能 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param en 配置的值，0-不使能默认队列，1-使能默认队列， +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author wush @date 2016/08/16 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_default_queue_en_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 en); + +/***********************************************************/ +/** 读取默认队列使能 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_en 读取的值，0-不使能默认队列，1-使能默认队列， +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author wush @date 2016/08/16 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_default_queue_en_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_en); + + +/***********************************************************/ +/** 配置默认队列起始末尾 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param def_start_que 起始默认队列block/byte单位 +* @param def_finish_que 结束默认队列block/byte单位 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author wush @date 2016/08/16 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_default_queue_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 def_start_queue, ZXIC_UINT32 def_finish_queue); + +/***********************************************************/ +/** 读取默认队列起始末尾值 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_def_start_que 默认队列起始值block/byte单位 +* @param p_def_finish_que 默认队列结束值block/byte单位 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author wush @date 2016/08/16 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_default_queue_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_def_start_queue, ZXIC_UINT32 *p_def_finish_queue); + +/***********************************************************/ +/** 配置协议队列使能 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param en 配置的值，0-不使能默认队列，1-使能默认队列， +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author wush @date 2016/08/16 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_protocol_queue_en_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 en); + +/***********************************************************/ +/** 读取协议队列使能 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_en 读取的值，0-不使能通用门限，1-使能通用门限， +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author wush @date 2016/08/16 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_protocol_queue_en_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_en); + +/***********************************************************/ +/** 配置协议队列起始末尾 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param protocol_start_que 起始协议队列block/byte单位 +*@param protocol_-finish_que 末尾协议队列block/byte单位 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author wush @date 2016/08/16 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_protocol_queue_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 protocol_start_que, ZXIC_UINT32 protocol_finish_que); + +/***********************************************************/ +/** 读取协议队列起始末尾值 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_protocol_start_que 协议认队列起始值block/byte单位 +* @param p_protocol_finish_que 协议认队列末尾值block/byte单位 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author wush @date 2016/08/16 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_protocol_queue_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_protocol_start_que, ZXIC_UINT32 *p_protocol_finish_que); + + +/***********************************************************/ +/** 配置QMU需要统计的队列组 +* @param dev_id 设备号 +* @param tm_type 0-ETM,1-FTM +* @param batch_id 队列组 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/05/07 +************************************************************/ +DPP_STATUS dpp_tm_qmu_observe_batch_set(DPP_DEV_T *dev, ZXIC_UINT32 batch_id); + +/***********************************************************/ +/** 配置QMU需要统计的队列号 +* @param dev_id 设备号 +* @param tm_type 0-ETM,1-FTM +* @param q_id 队列号 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/05/07 +************************************************************/ +DPP_STATUS dpp_tm_qmu_observe_qnum_set(DPP_DEV_T *dev, ZXIC_UINT32 q_id); + +/***********************************************************/ +/** 配置授权盈余初始化值 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param crbal_initial_value 授权盈余初始化值 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/03/04 +************************************************************/ +DPP_STATUS dpp_tm_qmu_crbal_initial_value_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 crbal_initial_value); + +/***********************************************************/ +/** 配置等价包长使能 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param en 使能标记，0-不使能，1-使能 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/28 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_equal_pkt_len_en_set(DPP_DEV_T *dev, ZXIC_UINT32 en); + +/***********************************************************/ +/** 读取等价包长使能 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_en 使能标记，0-不使能，1-使能 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/28 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_equal_pkt_len_en_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_en); + + +/***********************************************************/ +/** 读取指定队列获得授权个数(只打印授权非零的队列号) +* @param dev_id 设备编号 +* @param ackflow_start 授权起始流号 +* @param ackflow_end 授权终止流号 +* @param sleep_time_ms 等待时间 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author wush @date 2017/01/19 +************************************************************/ +DPP_STATUS dpp_etm_crdt_traffic_diag(ZXIC_UINT32 dev_id, + ZXIC_UINT32 ackflow_start, + ZXIC_UINT32 ackflow_end, + ZXIC_UINT32 sleep_time_ms); + +/***********************************************************/ +/** 读取指定队列获得授权个数(只打印授权非零的队列号) +* @param dev_id 设备编号 +* @param ackflow_start 授权起始流号 +* @param ackflow_end 授权终止流号 +* @param sleep_time_ms 等待时间 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author wush @date 2017/01/19 +************************************************************/ +DPP_STATUS dpp_ftm_crdt_traffic_diag(ZXIC_UINT32 dev_id, + ZXIC_UINT32 ackflow_start, + ZXIC_UINT32 ackflow_end, + ZXIC_UINT32 sleep_time_ms); + + +/***********************************************************/ +/** 读取指定队列获得授权个数(只打印授权非零的队列号) +* @param dev_id 设备编号 +* @param tm_type 0-ETM, 1FTM +* @param ackflow_start 授权流起始 +* @param ackflow_end 授权流终止 +* @param sleep_time_ms 等待时间 +* +* @return +* @remark 无 +* @see +* @author wush @date 2017/01/24 +************************************************************/ +DPP_STATUS diag_dpp_tm_crdt_traffic_diag(ZXIC_UINT32 dev_id, + ZXIC_UINT32 ackflow_start, + ZXIC_UINT32 ackflow_end, + ZXIC_UINT32 sleep_time_ms); + +/***********************************************************/ +/** +* @param dev_id +* @param tm_type +* @param i_or_e_sel +* @param port_or_dest_id_sel +* @param start_id +* @param start_port_dest_id +* @param num +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xjw @date 2018/02/01 +************************************************************/ +DPP_STATUS dpp_tm_olif_stat_set_mul(ZXIC_UINT32 dev_id, + ZXIC_UINT32 i_or_e_sel, + ZXIC_UINT32 port_or_dest_id_sel, + ZXIC_UINT32 start_id, + ZXIC_UINT32 start_port_dest_id, + ZXIC_UINT32 num); + + +/****************************************************************************** + * END: 函数声明 * + *****************************************************************************/ +#endif + + +#if ZXIC_REAL("ETM_STAT") + + +/***********************************************************/ +/** 打印dpp tm所有模块中断状态 +* @param tm_type 0-ETM,1-FTM +* @param dev_id 设备编号 +* @param +* @param +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author yjd @date 2015/07/09 +************************************************************/ +DPP_STATUS diag_dpp_tm_int(ZXIC_UINT32 dev_id); + +/***********************************************************/ +/** 获取tm.c中qmu_init_set中配置的case_num +* @param tm_type 0-ETM,1-FTM +* @param dev_id 设备编号 +* @param +* @param +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xuhb @date 2020/04/15 +************************************************************/ +DPP_STATUS dpp_tm_case_no_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *case_no); + +/***********************************************************/ +/** 配置dpp tm所有模块中断屏蔽 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param int_mask_flag 0:不屏蔽 1:屏蔽 +* @param +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author yjd @date 2015/07/09 +************************************************************/ +DPP_STATUS dpp_tm_int_mask_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 int_mask_flag); + +/***********************************************************/ +/** 读取基于优先级的QMU接收NPPU数据的fifo阈值 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param sp 优先级0~7 +* @param p_th 指定优先级的fifo阈值0~511，单位为fifo条目，fifo深度512 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2016/10/18 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_move_drop_sp_th_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 sp, + ZXIC_UINT32 *p_th); + +/***********************************************************/ +/** 打印cgavd模式 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_mode 0:block mode 1:byte mode +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cy @date 2016/07/29 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_cfg_mode_get_diag(ZXIC_UINT32 dev_id); + + +/***********************************************************/ +/** 打印cgavd TD阈值 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param level 拥塞避免支持层次号，0:队列级，1:端口级，2:系统级 +* @param id 队列号或端口号，系统级时，id参数无效 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cy @date 2016/08/01 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_td_byte_block_th_get_diag(ZXIC_UINT32 dev_id, + DPP_TM_CGAVD_LEVEL_E level, + ZXIC_UINT32 id); + +/***********************************************************/ +/** QMU MMU 配置清除 +* @param dev_id +* @param tm_type +* +* @return +* @remark 无 +* @see +* @author XXX @date 2020/04/13 +************************************************************/ +DPP_STATUS dpp_tm_qmu_mmu_cfg_clr(ZXIC_UINT32 dev_id); + +/***********************************************************/ +/** 读取QMU所有队列的统计信息 +* @param dev_id 设备编号 +* @param p_para 获得的统计信息 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/03/04 +************************************************************/ +DPP_STATUS dpp_tm_qmu_stat_get(ZXIC_UINT32 dev_id, DPP_ETM_QMU_STAT_INFO_T *p_para); + +/***********************************************************/ +/** 读取QMU指定队列的计数信息 +* @param dev_id 设备编号 +* @param p_para 获得的统计信息 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/03/04 +************************************************************/ +DPP_STATUS dpp_tm_qmu_spec_q_stat_get(ZXIC_UINT32 dev_id, DPP_ETM_QMU_SPEC_Q_STAT_INFO_T *p_para); + +/***********************************************************/ +/** 读取QMU指定队列组的计数信息 +* @param dev_id 设备编号 +* @param p_para 获得的统计信息 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/03/04 +************************************************************/ +DPP_STATUS dpp_tm_qmu_spec_bat_stat_get(ZXIC_UINT32 dev_id, DPP_ETM_QMU_SPEC_BAT_STAT_INFO_T *p_para); + +/***********************************************************/ +/** 配置QMU流控计数模式 +* @param dev_id 设备号 +* @param tm_type 0-ETM,1-FTM +* @param mode 流控模式，0-电平流控；1-边沿流控 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/05/07 +************************************************************/ +DPP_STATUS dpp_tm_qmu_fc_cnt_mode_set(DPP_DEV_T *dev, ZXIC_UINT32 mode); + +/***********************************************************/ +/** 读取QMU流控计数模式 +* @param dev_id 设备号 +* @param tm_type 0-ETM,1-FTM +* @param p_mode 流控模式，0-电平流控；1-边沿流控 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/05/07 +************************************************************/ +DPP_STATUS dpp_tm_qmu_fc_cnt_mode_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_mode); + +/***********************************************************/ +/** 打印block长度 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author yjd @date 2015/07/20 +************************************************************/ +DPP_STATUS dpp_tm_cfgmt_blk_size_get_diag(ZXIC_UINT32 dev_id); + + +/***********************************************************/ +/** 打印队列空标志查询 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param qnum 配置的队列号 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author cy @date 2016/06/20 +************************************************************/ +DPP_STATUS dpp_tm_qlist_ept_flag_get_diag(ZXIC_UINT32 dev_id, ZXIC_UINT32 qnum); + + +/***********************************************************/ +/** 获得队列空标志查询 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param qnum 配置的队列号 +* @param p_value 队列空标志查询 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author cy @date 2016/06/20 +************************************************************/ +DPP_STATUS dpp_tm_qlist_ept_flag_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 qnum, + ZXIC_UINT32 *p_value); + + +/***********************************************************/ +/** 获得队列深度计数 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param qnum 配置的队列号 +* @param p_value 队列深度计数 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author cy @date 2016/06/20 +************************************************************/ +DPP_STATUS dpp_tm_qlist_r_bcnt_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 qnum, + ZXIC_UINT32 *p_value); + + +/***********************************************************/ +/** 打印队列深度计数 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param qnum 配置的队列号 +* @param p_value 队列深度计数 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author cy @date 2016/06/20 +************************************************************/ +DPP_STATUS dpp_tm_qlist_r_bcnt_get_diag(ZXIC_UINT32 dev_id, ZXIC_UINT32 qnum); + +/***********************************************************/ +/** CMDSCH中分端口分优先级的BLOCK计数 +* @param dev_id 设备编号 +* @param pri +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author sun @date 2023/09/19 +************************************************************/ +DPP_STATUS dpp_tm_csch_r_block_cnt_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 pri, ZXIC_UINT32 *p_value); + +/***********************************************************/ +/** 打印CMDSCH中分端口分优先级的BLOCK计数 +* @param dev_id 设备编号 +* @param port +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author sun @date 2023/09/19 +************************************************************/ +DPP_STATUS dpp_tm_csch_r_block_cnt_diag(ZXIC_UINT32 dev_id, ZXIC_UINT32 port); + +/***********************************************************/ +/** 打印队列入链状态 +* @param dev_id 设备编号 +* @param flow_id +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author sun @date 2023/09/19 +************************************************************/ +DPP_STATUS dpp_tm_crdt_flow_link_state_get_diag(ZXIC_UINT32 dev_id, ZXIC_UINT32 flow_id); + +/***********************************************************/ +/** 打印调度器入链状态 +* @param dev_id 设备编号 +* @param flow_id +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author sun @date 2023/09/19 +************************************************************/ +DPP_STATUS dpp_tm_crdt_se_link_state_get_diag(ZXIC_UINT32 dev_id, ZXIC_UINT32 se_id); + +/***********************************************************/ +/** 打印olif的fifo是否空状态 +* @param dev_id 设备编号 +* @param +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author sun @date 2023/09/19 +************************************************************/ +DPP_STATUS dpp_tm_olif_fifo_empty_state_get_diag(ZXIC_UINT32 dev_id); + +/***********************************************************/ +/** 授权个数统计寄存器清零 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author taq @date 2015/06/19 +************************************************************/ +DPP_STATUS dpp_tm_crdt_clr_diag(ZXIC_UINT32 dev_id); + +/***********************************************************/ +/**cpu配置flow_id的crs强制为normal或者off开关使能，用于检测SA模式下队列到授权流的多对一问题 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param flow_id:流号(和授权流号一一对应) +* en 强制配置crs的使能，0-不使能，1-使能 +* crs_value:强制配置crs的值2'b00:off; 2'b01:low; 2'b10:normal； +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cuiy @date 2016/04/25 +************************************************************/ +DPP_STATUS dpp_tm_crdt_crs_sheild_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 flow_id, ZXIC_UINT32 en, ZXIC_UINT32 crs_value); + + +/***********************************************************/ +/**获取flow_id的crs强制为normal或者off开关使能，用于检测SA模式下队列到授权流的多对一问题 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param flow_id:流号(和授权流号一一对应) +* en 强制配置crs的使能，0-不使能，1-使能 +* crs_value:强制配置crs的值2'b00:off; 2'b01:low; 2'b10:normal； +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cuiy @date 2016/04/25 +************************************************************/ +DPP_STATUS dpp_tm_crdt_crs_sheild_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_flow_id, ZXIC_UINT32 *p_en, ZXIC_UINT32 *p_crs_value); + + +/***********************************************************/ +/** 获得拥塞状态(有效链路数+UCN等级)到授权产生间隔的映射表 +* @param dev_id 设备编号 +* @param valid_serdes_num 有效的链路数(0~32 +* @param ucn_level UCN等级(0~7) +* @param p_cr_clk UCN等级(0~7) +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author wush @date 2017/03/28 +************************************************************/ +DPP_STATUS dpp_tm_crdt_cfgmt_interval_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 valid_serdes_num, + ZXIC_UINT32 ucn_level, + ZXIC_UINT32 *p_cr_clk); + +/***********************************************************/ +/**每隔10s获取crs状态的个数 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param +* @return +* @remark 无 +* @see +* @author zmy @date 2015/08/07 +************************************************************/ +DPP_STATUS dpp_tm_crs_statics(ZXIC_UINT32 dev_id, ZXIC_UINT32 que_id); + + +/***********************************************************/ +/** 统计QMU发送和CRDT模块指定授权流接收的CRS计数(10s内) +* @param dev_id 设备编号 +* @param que_id QMU队列号 +* @param ackflow_id 授权流号 +* @param valid_flag 0:队列发送和授权流接收都统计; 1:只关注队列发送，2:只关注授权流接收。 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author wush @date 2017/05/12 +************************************************************/ +DPP_STATUS dpp_tm_crs_cnt_prt(ZXIC_UINT32 dev_id, ZXIC_UINT32 que_id, ZXIC_UINT32 ackflow_id, ZXIC_UINT32 valid_flag); + + +/***********************************************************/ +/** 带停流的统计QMU发送和CRDT模块指定授权流接收的CRS计数 +* @param dev_id 设备编号 +* @param que_id QMU队列号 +* @param ackflow_id 授权流号 +* @param valid_flag 0:默认队列发送和授权流接收都统计,此时队列授权都在本板; +* 1:只关注队列发送，2:只关注授权流接收，需要与源端队列停流配合使用， + 先停流，运行该函数；或者直接不停流得到的是某段时间的计数。 +* @param sleep_time 统计多长时间内的crs计数 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author wush @date 2017/05/12 +************************************************************/ +DPP_STATUS dpp_tm_crs_cnt_prt_1(ZXIC_UINT32 dev_id, + ZXIC_UINT32 que_id, + ZXIC_UINT32 ackflow_id, + ZXIC_UINT32 valid_flag, + ZXIC_UINT32 sleep_time); + +/***********************************************************/ +/** 读取qlist入队及出队状态监控 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cy @date 2015/08/26 +************************************************************/ +DPP_STATUS dpp_tm_qmu_qlist_state_query(ZXIC_UINT32 dev_id); + + +/***********************************************************/ +/** 打印被指定统计的第0~15个端口消耗的令牌个数 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM + +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 统计时间为2s，其中c桶统计1s，e桶统计1s +* @see +* @author whuashan @date 2019/03/15 +************************************************************/ +DPP_STATUS dpp_tm_shape_token_dec_cnt_diag(ZXIC_UINT32 dev_id); + +/***********************************************************/ +/** 打印被指定统计的第0~15个端口接收的令牌个数 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 统计时间为2s，其中c桶统计1s，e桶统计1s +* @see +* @author whuashan @date 2019/03/15 +************************************************************/ +DPP_STATUS dpp_tm_shape_token_dist_cnt_diag(ZXIC_UINT32 dev_id); + + +/***********************************************************/ +/** 配置olif统计组信息 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param id olif统计组号 +* @param all_or_by_port 0-统计所有，1-统计某一端口或某一dest_id +* @param i_or_e_sel 10-统计片外，01-统计片内，其他值-统计所有 +* @param port_or_dest_id_sel 0-统计port，1-统计dest_id +* @param port_dest_id port号或dest_id号 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cuiy @date 2016/04/21 +************************************************************/ +DPP_STATUS dpp_tm_olif_stat_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 id, + ZXIC_UINT32 all_or_by_port, + ZXIC_UINT32 i_or_e_sel, + ZXIC_UINT32 port_or_dest_id_sel, + ZXIC_UINT32 port_dest_id); + + +/***********************************************************/ +/** 查看CRDT接收到和发送的某端口拥塞授权总数 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param pp_id 0~63 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cy @date 2016/12/08 +************************************************************/ +DPP_STATUS diag_dpp_tm_crdt_port_congest_credit_cnt(ZXIC_UINT32 dev_id, ZXIC_UINT32 pp_id); + +#endif /*ETM_STAT */ + + +#if ZXIC_REAL("TM_REG") +/***********************************************************/ +/** 写TM寄存器 +* @param module_id 区分TM子模块 +* @param addr 基于子模块的地址 +* @param data 写入的数据 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author yjd @date 2015/07/26 +************************************************************/ +DPP_STATUS dpp_tm_wr_reg(ZXIC_UINT32 dev_id, ZXIC_UINT32 module_id, ZXIC_UINT32 addr, ZXIC_UINT32 data); + + +/***********************************************************/ +/** 读TM寄存器 +* @param module_id 区分TM子模块 +* @param addr 基于子模块的地址 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author yjd @date 2015/07/26 +************************************************************/ +DPP_STATUS dpp_tm_rd_reg(ZXIC_UINT32 dev_id, ZXIC_UINT32 module_id, ZXIC_UINT32 addr); + + +/***********************************************************/ +/** 读一片连续的TM寄存器 +* @param module_id 区分TM子模块 +* @param first_addr 起始寄存器的地址 +* @param reg_num 总共读取的寄存器数 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author yjd @date 2017/07/26 +************************************************************/ +DPP_STATUS dpp_tm_rd_more_reg(ZXIC_UINT32 dev_id, ZXIC_UINT32 module_id, ZXIC_UINT32 first_addr, ZXIC_UINT32 reg_num); + +/***********************************************************/ +/** 写tm模块二层间接寄存器(仅crdt/shap模块使用) +* @param module_id 区分TM子模块 +* @param addr 基于子模块的地址 +* @param data 写入的数据 +* +* @return +* @remark 无 +* @see +* @author whuashan @date 2019/02/25 +************************************************************/ +DPP_STATUS dpp_tm_ind_wr_reg(ZXIC_UINT32 dev_id, ZXIC_UINT32 module_id, ZXIC_UINT32 addr, ZXIC_UINT64 data); + +/***********************************************************/ +/** 读tm模块二层间接寄存器(仅crdt/shap模块使用) +* @param module_id 区分TM子模块 +* @param addr 基于子模块的地址 +* +* @return +* @remark 无 +* @see +* @author whuashan @date 2019/02/25 +************************************************************/ +DPP_STATUS dpp_tm_ind_rd_reg(ZXIC_UINT32 dev_id, ZXIC_UINT32 module_id, ZXIC_UINT32 addr); +#endif /*TM_REG */ + +#if ZXIC_REAL("TM_CFGMT") +/***********************************************************/ +/** 校验子系统初始化就绪，所有子系统均初始化就绪，p_rdy值为1 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_rdy 初始化就绪标记，1-就绪，0-未就绪 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/04/09 +************************************************************/ +DPP_STATUS dpp_tm_cfgmt_subsystem_rdy_check(ZXIC_UINT32 dev_id); + + +/***********************************************************/ +/** cpu读写通道验证，其读出值等于写入值。读出值不等于写入值时，返回err +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/04/09 +************************************************************/ +DPP_STATUS dpp_tm_cfgmt_cpu_check(DPP_DEV_T *dev); + + +/***********************************************************/ +/** 读取内置TM的工作模式 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_mode 读取的值，0-TM模式，1-SA模式 +*ETM仅工作在TM模式，FTM可以工作TM或SA模式 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/25 +************************************************************/ +DPP_STATUS dpp_tm_cfgmt_sa_work_mode_get(DPP_DEV_T *dev, DPP_TM_WORK_MODE_E *p_mode); + + +/***********************************************************/ +/** 配置ddr3挂接组数 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param ddr_num ddr组数，1-6组 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/04/09 +************************************************************/ +DPP_STATUS dpp_tm_cfgmt_ddr_attach_set(DPP_DEV_T *dev, ZXIC_UINT32 ddr_num); + + +/***********************************************************/ +/** 读取ddr3挂接组数 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_ddr_num ddr组数,1-6组 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/04/09 +************************************************************/ +DPP_STATUS dpp_tm_cfgmt_ddr_attach_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_ddr_num); + +DPP_STATUS dpp_qmu_init_info(ZXIC_UINT32 dev_id); + +/***********************************************************/ +/** 配置包存储的CRC功能是否使能 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param en 配置的值，0-禁止CRC功能，1-允许CRC功能 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/25 +************************************************************/ +DPP_STATUS dpp_tm_cfgmt_crc_en_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 en); + + +/***********************************************************/ +/** 配置qmu端口转换使能，SA模式下需要配置 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param en 配置的使能值，0-不使能，1-使能 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/25 +************************************************************/ +DPP_STATUS dpp_tm_cfgmt_port_transfer_en_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 en); + + +/***********************************************************/ +/** 读取qmu端口转换使能 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_en 读取的使能值，0-不使能，1-使能 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/25 +************************************************************/ +DPP_STATUS dpp_tm_cfgmt_port_transfer_en_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_en); + + +/***********************************************************/ +/** 读取包存储的CRC功能是否使能 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_en 读取的值，0-禁止CRC功能，1-允许CRC功能 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/25 +************************************************************/ +DPP_STATUS dpp_tm_cfgmt_crc_en_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_en); + + +/***********************************************************/ +/** 配置block长度模式 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param size block长度模式:256/512/1024 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/04/09 +************************************************************/ +DPP_STATUS dpp_tm_cfgmt_blk_size_set(DPP_DEV_T *dev, ZXIC_UINT32 size); + + +/***********************************************************/ +/** 配置计数模式 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_mode 计数模式 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/04/09 +************************************************************/ +DPP_STATUS dpp_tm_cfgmt_cnt_mode_set(ZXIC_UINT32 dev_id, DPP_TM_CNT_MODE_T *p_mode); + + +/***********************************************************/ +/** 读取计数模式 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_mode 计数模式 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/04/09 +************************************************************/ +DPP_STATUS dpp_tm_cfgmt_cnt_mode_get(ZXIC_UINT32 dev_id, DPP_TM_CNT_MODE_T *p_mode); + + +/***********************************************************/ +/** 配置中断屏蔽 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_para 中断屏蔽 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/04/09 +************************************************************/ +DPP_STATUS dpp_tm_cfgmt_int_mask_set(ZXIC_UINT32 dev_id, DPP_TM_INT_T *p_para); + + +/***********************************************************/ +/** 读取中断屏蔽 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_para 中断屏蔽 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/04/09 +************************************************************/ +DPP_STATUS dpp_tm_cfgmt_int_mask_get(ZXIC_UINT32 dev_id, DPP_TM_INT_T *p_para); + + +/***********************************************************/ +/** 读取中断状态 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_para 中断状态 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/04/09 +************************************************************/ +DPP_STATUS dpp_tm_cfgmt_int_state_get(ZXIC_UINT32 dev_id, DPP_TM_INT_T *p_para); + +/***********************************************************/ +/** 配置tm时钟门控是否使能 +* @param dev_id 设备编号 +* @param en 配置的值，0-禁止tm时钟门控，1-使能tm时钟门控 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author lsy @date 2022/08/22 +************************************************************/ +DPP_STATUS dpp_tm_cfgmt_clkgate_en_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 en); + +/***********************************************************/ +/** 读取tm时钟门控是否使能 +* @param dev_id 设备编号 +* @param en 配置的值，0-禁止tm时钟门控，1-使能tm时钟门控 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author lsy @date 2022/08/22 + +************************************************************/ +DPP_STATUS dpp_tm_cfgmt_clkgate_en_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_en); + +/***********************************************************/ +/** 配置tm软复位是否使能 +* @param dev_id 设备编号 +* @param en 配置的值，0-禁止tm软复位，1-使能tm软复位 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author lsy @date 2022/08/22 +************************************************************/ +DPP_STATUS dpp_tm_cfgmt_softrst_en_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 en); + +/***********************************************************/ +/** 读取tm软复位是否使能 +* @param dev_id 设备编号 +* @param en 配置的值，0-禁止tm软复位，1-使能tm软复位 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author lsy @date 2022/08/22 + +************************************************************/ +DPP_STATUS dpp_tm_cfgmt_softrst_en_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_en); + +#endif /*TM_CFGMT */ + +#if ZXIC_REAL("TM_CGAVD") +/***********************************************************/ +/** 读取各级搬移功能使能 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param level 要配置的拥塞避免层次号，0:队列级，1:端口级，2:系统级 +* @param p_en 读出的使能标记，0-不使能，1-使能 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2016/10/18 +************************************************************/ +#ifdef ETM_REAL +DPP_STATUS dpp_tm_cgavd_move_en_get(ZXIC_UINT32 dev_id, + DPP_TM_CGAVD_LEVEL_E level, + ZXIC_UINT32 *p_en); + +/***********************************************************/ +/** 配置各级搬移门限 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param level 拥塞避免支持层次号，0:队列级，1:端口级，2:系统级 +* @param id 队列号或端口号，系统级时，id参数无效 +* @param value 端口级和系统级时，为搬移门限值，单位为NPPU存包的单位，256B； + 流级时为搬移profile_id,0~15 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2016/10/18 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_move_th_set(ZXIC_UINT32 dev_id, + DPP_TM_CGAVD_LEVEL_E level, + ZXIC_UINT32 id, + ZXIC_UINT32 value); + +/***********************************************************/ +/** 读取各级搬移门限 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param level 拥塞避免支持层次号，0:队列级，1:端口级，2:系统级 +* @param id 队列号或端口号，系统级时，id参数无效 +* @param p_value 端口级和系统级时，为搬移门限值，单位为NPPU存包的单位，256B； + 流级时为搬移profile_id,0~15 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2016/10/18 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_move_th_get(ZXIC_UINT32 dev_id, + DPP_TM_CGAVD_LEVEL_E level, + ZXIC_UINT32 id, + ZXIC_UINT32 *p_value); + +/***********************************************************/ +/** 读取flow级的搬移策略 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param move_profile flow级的搬移门限分组索引,0~15 +* @param p_th flow级的搬移门限，单位为KB； +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2016/10/18 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_flow_move_profile_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 move_profile, + ZXIC_UINT32 *p_th); +#endif +/***********************************************************/ +/** 读取端口共享的搬移门限 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_th 端口共享的搬移门限，单位为NPPU存包的单位，256B； +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2016/10/18 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_port_share_th_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *p_th); + +/***********************************************************/ +/** 读取各级拥塞避免功能使能 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param level 要读取的拥塞避免层次号，0:队列级，1:端口级，2:系统级 +* @param p_en 读出的使能标记，0-不使能，1-使能 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/28 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_en_get(DPP_DEV_T *dev, + DPP_TM_CGAVD_LEVEL_E level, + ZXIC_UINT32 *p_en); + +/***********************************************************/ +/** dp选取来源 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param level 要配置的拥塞避免层次号，0:队列级，1:端口级，2:系统级 +* @param dp_sel dp选取来源，0-dp，1-tc，2-pkt_len[2:0] +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2017/03/14 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_dp_sel_set(DPP_DEV_T *dev, + DPP_TM_CGAVD_LEVEL_E level, + DPP_TM_CGAVD_DP_SEL_E dp_sel); + +/***********************************************************/ +/** 读取拥塞避免算法 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param level 拥塞避免支持层次号，0:队列级，1:端口级，2:系统级 +* @param id 队列号或端口号,系统级时,id参数无效 +* @param p_method 配置的拥塞避免算法,0:TD,1:WRED/GRED +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/17 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_method_get(DPP_DEV_T *dev, + DPP_TM_CGAVD_LEVEL_E level, + ZXIC_UINT32 id, + DPP_TM_CGAVD_METHOD_E *p_method); + + +/***********************************************************/ +/** 流队列级队列深度的获取 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param que_id 队列号 +* p_len 队列深度以KB为单位 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author yjd @date 2015/06/19 +************************************************************/ +DPP_STATUS dpp_tm_flow_que_len_get(DPP_DEV_T *dev, + ZXIC_UINT32 que_id, + ZXIC_UINT32 *p_len); + +/***********************************************************/ +/** 端口级队列深度的获取 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param pp_id 队列号 +* pp_len 队列深度以KB为单位 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author yjd @date 2015/06/19 +************************************************************/ +DPP_STATUS dpp_tm_port_que_len_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 pp_id, + ZXIC_UINT32 *pp_len); + +/***********************************************************/ +/** 系统级队列深度的获取 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param sys_len 系统级深度以block为单位 +* sys_protocol_len 系统级包含协议队列深度以KB为单位 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author yjd @date 2015/06/19 +************************************************************/ +DPP_STATUS dpp_tm_sys_que_len_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *sys_len, + ZXIC_UINT32 *sys_protocol_len); + +/***********************************************************/ +/** 读取TD拥塞避免模式下的丢弃门限值 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param level 拥塞避免支持层次号，0:队列级，1:端口级，2:系统级 +* @param id 队列号或端口号，系统级时，id参数无效 +* @param p_td_th 配置的丢弃门限值 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/17 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_td_th_get(DPP_DEV_T *dev, + DPP_TM_CGAVD_LEVEL_E level, + ZXIC_UINT32 id, + ZXIC_UINT32 *p_td_th); + +/***********************************************************/ +/** 读取指定端口或队列绑定的WRED GROUP ID +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param level WRED支持层次号，0:队列级，1:端口级 +* @param id 队列号或端口号 +* @param p_wred_id 配置的WRED GROUP ID +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/17 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_wred_id_get(ZXIC_UINT32 dev_id, + DPP_TM_CGAVD_LEVEL_E level, + ZXIC_UINT32 id, + ZXIC_UINT32 *p_wred_id); + +/***********************************************************/ +/** 读取WRED丢弃曲线对应的参数 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param level WRED支持层次号，0:队列级，1:端口级 +* @param wred_id 队列级共支持16个WRED组0-15，端口级支持8组0-7 +* @param dp 共支持8个dp，取值0-7 +* @param p_para 配置的WRED组参数值，包含以下五个参数 + max_th 平均队列深度上限阈值 + min_th 平均队列深度下限阈值 + max_p 最大丢弃概率 + weight 平均队列深度计算权重 + q_len_th 队列深度阈值 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author taq @date 2015/04/20 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_wred_dp_line_para_get(ZXIC_UINT32 dev_id, + DPP_TM_CGAVD_LEVEL_E level, + ZXIC_UINT32 wred_id, + ZXIC_UINT32 dp, + DPP_TM_WRED_DP_LINE_PARA_T *p_para); + +/***********************************************************/ +/** 配置系统级GRED丢弃曲线对应的参数 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param dp 共支持8个dp，取值0-7 +* @param p_para 配置的GRED丢弃曲线参数值，包含以下六个参数 + max_th 平均队列深度上限阈值 + mid_th 平均队列深度中间阈值 + min_th 平均队列深度下限阈值 + max_p 最大丢弃概率 + weight 平均队列深度计算权重 + q_len_th 队列深度阈值 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author taq @date 2015/04/20 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_gred_dp_line_para_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 dp, + DPP_TM_GRED_DP_LINE_PARA_T *p_para); + +/***********************************************************/ +/** 配置系统级阶梯TD 丢弃曲线对应的参数 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param dp 共支持8个dp，取值0-7 +* @param td_th TD 门限 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cy @date 2016/08/02 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_ladtd_dp_line_para_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 dp, + ZXIC_UINT32 td_th); + + +/***********************************************************/ +/** 读取系统级GRED丢弃曲线对应的参数 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param dp 共支持8个dp，取值0-7 +* @param p_para 配置的GRED丢弃曲线参数值，包含以下六个参数 + max_th 平均队列深度上限阈值 + mid_th 平均队列深度中间阈值 + min_th 平均队列深度下限阈值 + max_p 最大丢弃概率 + weight 平均队列深度计算权重 + q_len_th 队列深度阈值 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author taq @date 2015/04/20 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_gred_dp_line_para_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 dp, + DPP_TM_GRED_DP_LINE_PARA_T *p_para); + +/***********************************************************/ +/** 读取指定端口或队列是否支持动态门限机制 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param level WRED支持层次号，0:队列级，1:端口级 +* @param id 队列号或端口号 +* @param p_en 读取的值，0-不支持动态门限机制，1-支持动态门限机制 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/17 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_dyn_th_en_get(DPP_DEV_T *dev, + DPP_TM_CGAVD_LEVEL_E level, + ZXIC_UINT32 id, + ZXIC_UINT32 *p_en); + +/***********************************************************/ +/** 配置通用门限使能 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param en 配置的值，0-不使能通用门限，1-使能通用门限， +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/17 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_uniform_th_en_set(DPP_DEV_T *dev, ZXIC_UINT32 en); + +/***********************************************************/ +/** 读取通用门限使能 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_en 读取的值，0-不使能通用门限，1-使能通用门限， +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/17 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_uniform_th_en_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_en); + +/***********************************************************/ +/** 配置通用门限 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param th 通用门限值 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/17 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_uniform_th_set(DPP_DEV_T *dev, ZXIC_UINT32 th); + +/***********************************************************/ +/** 读取通用门限 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_th 通用门限值 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/17 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_uniform_th_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_th); + +/***********************************************************/ +/** 配置流队列所属优先级 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param q_id 队列号 +* @param pri 配置的优先级，0~7 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/17 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_q_pri_set(DPP_DEV_T *dev, + ZXIC_UINT32 q_id, + ZXIC_UINT32 pri); + +/***********************************************************/ +/** 读取TM模式下流队列挂接的端口号；SA模式下流队列映射的目的芯片ID +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param q_id 队列号 +* @param p_pp_id 读取的端口号 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/18 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_q_map_pp_get(DPP_DEV_T *dev, + ZXIC_UINT32 q_id, + ZXIC_UINT32 *p_pp_id); + +/***********************************************************/ +/** 读取配置TM模式tc到flow的映射 +* @param dev_id 设备编号 +* @param tc_id itmd tc优先级（0~7） +* @param flow_id 读取映射的flowid号 （0~4095） +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author sun @date 2023/07/04 +************************************************************/ +DPP_STATUS dpp_tm_tc_map_flow_get(DPP_DEV_T *dev, + ZXIC_UINT32 tc_id, + ZXIC_UINT32 *flow_id); + +/***********************************************************/ +/** 获取强制片内或片外 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param en 1:使能 +* @param mode 1 :omem 强制片外 0:imem 强制片内 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author wush @date 2017/10/14 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_imem_omem_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *p_en, + ZXIC_UINT32 *p_mode); + +/***********************************************************/ +/** 连续配置各级搬移门限 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param level 拥塞避免支持层次号，0:队列级，1:端口级，2:系统级 +* @param start_id 为起始 队列号或端口号，系统级时，id参数无效 +* @param value 端口级和系统级时，为搬移门限值，单位为NPPU存包的单位，256B； + 流级时为搬移profile_id,0~15 +* @param num 为队列或端口个数 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author wush @date 2016/11/19 +************************************************************/ +#ifdef ETM_REAL +DPP_STATUS dpp_tm_cgavd_move_th_together_wr(ZXIC_UINT32 dev_id, + DPP_TM_CGAVD_LEVEL_E level, + ZXIC_UINT32 start_id, + ZXIC_UINT32 value, + ZXIC_UINT32 num); +#endif +/***********************************************************/ +/** 系统级缓存使用上下限阈值配置 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param th_h: 系统级缓存使用上限阈值 +* @param th_l: 系统级缓存使用下限阈值 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author yjd @date 2015/07/03 +************************************************************/ +DPP_STATUS dpp_tm_sys_window_th_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 th_h, + ZXIC_UINT32 th_l); + +/***********************************************************/ +/** 配置cgavd强制反压 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param cgavd_fc: 0:不强制反压 1:强制反压 +* @param +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/07/03 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_cfg_fc_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 cgavd_fc); + +/***********************************************************/ +/** 获取cgavd强制反压状态 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param cgavd_fc: 0:不强制反压 1:强制反压 +* @param +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/07/03 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_cfg_fc_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *cgavd_fc); + +/***********************************************************/ +/** 配置cgavd强制不反压 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param cgavd_no_fc: 0:不强制 1:强制不反压 +* @param +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/07/03 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_cfg_no_fc_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 cgavd_no_fc); + +/***********************************************************/ +/** 获取cgavd强制不反压状态 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param cgavd_no_fc: 0:不强制 1:强制不反压 +* @param +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/07/03 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_cfg_no_fc_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *cgavd_no_fc); + + +/***********************************************************/ +/** 配置cgavd平均队列深度归零 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param en: 0:关闭 1:使能 +* @param +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xuhb @date 2020/08/05 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_avg_qlen_return_zero_en_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 en); +#endif /*TM_CGAVD */ + +/** crdt ram初始化 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/03/22 +************************************************************/ +DPP_STATUS dpp_tm_crdt_ram_init(ZXIC_UINT32 dev_id); + +/***********************************************************/ +/** 获取调度器类型 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param se_id 调度器编号 +* @param item_num 调度器中包含的子调度器个数 +* @param sch_type_num 调度器类型编号 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/02/26 +************************************************************/ +DPP_STATUS dpp_tm_crdt_sch_type_get(DPP_DEV_T *dev, ZXIC_UINT32 se_id, ZXIC_UINT32 *item_num, ZXIC_UINT32 *sch_type_num); + +/***********************************************************/ +/** 配置flow级流队列的挂接关系(flow到上级调度器的挂接) +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param flow_id 流队列号 +* @param c_linkid c桶要挂接到的上级调度器id +* @param c_weight c桶挂接到上级调度器的权重[1~511] +* @param c_sp c桶挂接到上级调度器的sp优先级,有效值[0-8],共9级，优先级依次降低 +* @param mode 挂接模式：0-单桶 1-双桶。配置单桶时无需关注后续参数，配0即可 +* @param e_linkid e桶要挂接到的上级调度器id +* @param e_weight e桶挂接到上级调度器的权重[1~511] +* @param e_sp e桶挂接到上级调度器的sp优先级，有效值[0-8],共9级，优先级依次降低 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/02/27 +************************************************************/ +DPP_STATUS dpp_tm_crdt_flow_link_wr(DPP_DEV_T *dev, + ZXIC_UINT32 flow_id, + DPP_TM_SCH_FLOW_PARA_T *p_flow_para); + +/***********************************************************/ +/** 批量配置flow级流队列的挂接关系 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param flow_id_s 起始流队列号 +* @param flow_id_e 终止流队列号 +* @param c_linkid c桶要挂接到的上级调度器id +* @param c_weight c桶挂接到上级调度器的权重[1~511] +* @param c_sp c桶挂接到上级调度器的sp优先级,有效值[0-8],共9级，优先级依次降低 +* @param mode 挂接模式：0-单桶 1-双桶。配置单桶时无需关注后续参数，配0即可 +* @param e_linkid e桶要挂接到的上级调度器id +* @param e_weight e桶挂接到上级调度器的权重[1~511] +* @param e_sp e桶挂接到上级调度器的sp优先级，有效值[0-8],共9级，优先级依次降低 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/02/27 +************************************************************/ +DPP_STATUS dpp_tm_crdt_flow_link_more_set(DPP_DEV_T *dev, + ZXIC_UINT32 flow_id_s, + ZXIC_UINT32 flow_id_e, + ZXIC_UINT32 c_linkid, + ZXIC_UINT32 c_weight, + ZXIC_UINT32 c_sp, + ZXIC_UINT32 mode, + ZXIC_UINT32 e_linkid, + ZXIC_UINT32 e_weight, + ZXIC_UINT32 e_sp); + +/***********************************************************/ +/** 配置调度器层次化QOS的挂接关系:非优先级传递 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param se_id 本级调度器id +* @param se_linkid 要挂接到的上级调度器id +* @param se_weight 挂接到上级调度器的权重[1~511] +* @param se_sp 挂接到上级调度器的sp优先级,有效值[0-8],共9级，优先级依次降低 +* @param se_insw 优先级传递使能：0-关 1-开。该参数不传递直接配0 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/02/27 +************************************************************/ +DPP_STATUS dpp_tm_crdt_se_link_wr(DPP_DEV_T *dev, + ZXIC_UINT32 se_id, + DPP_TM_SCH_SE_PARA_T *p_sch_se_para); + + +/***********************************************************/ +/** 配置调度器层次化QOS的挂接关系:优先级传递 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param se_id 本级调度器id +* @param se_linkid 要挂接到的上级调度器id +* @param se_sp 挂接到上级调度器的sp优先级,有效值[0-3],最多4级，优先级按调度单元分配， +* 每个调度单元内部调度器优先级相同！ +* @param se_weight0-7 WFQ8中各调度器权重值[1~511]，若是WFQ2/4 只取前面对应值，后面无效 +* @param se_insw 优先级传递使能：0-关 1-开. 该参数不传递直接配1 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/02/27 +************************************************************/ +DPP_STATUS dpp_tm_crdt_se_link_insw_wr(DPP_DEV_T *dev, + ZXIC_UINT32 se_id, + DPP_TM_SCH_SE_PARA_INSW_T *p_sch_se_para_insw); + +/***********************************************************/ +/** 获取流队列入链状态 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param flow_id 流队列号 +* @param link_state 0-未入链 1-在调度器链表中 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/02/27 +************************************************************/ +DPP_STATUS dpp_tm_crdt_flow_link_state_get(DPP_DEV_T *dev, ZXIC_UINT32 flow_id, ZXIC_UINT32 *link_state); + +/***********************************************************/ +/** 获取调度器入链状态 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param se_id 调度器编号 +* @param link_state 0-未入链 1-在调度器链表中 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/02/27 +************************************************************/ +DPP_STATUS dpp_tm_crdt_se_link_state_get(DPP_DEV_T *dev, ZXIC_UINT32 se_id, ZXIC_UINT32 *link_state); + +/***********************************************************/ +/** 判断crdt流删除命令是否空闲 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/02/27 +************************************************************/ +DPP_STATUS dpp_tm_crdt_del_cmd_idle(DPP_DEV_T *dev); + +/***********************************************************/ +/** 删除流/调度器挂接关系 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param id 要删除的流号或调度器id +* ETM范围:0--0xABFF; FTM范围:0-0x177F +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/02/27 +************************************************************/ +DPP_STATUS dpp_tm_crdt_del_link_set(DPP_DEV_T *dev, ZXIC_UINT32 id); + + + + +/***********************************************************/ +/** 获取pp->dev挂接关系 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param pp_id 0~63 +* @param p_weight 0~127 +* @param p_sp_mapping 0~7 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cuiy @date 2016/04/20 +************************************************************/ +DPP_STATUS dpp_tm_crdt_pp_para_get(DPP_DEV_T *dev, + ZXIC_UINT32 pp_id, + ZXIC_UINT32 *p_weight, + ZXIC_UINT32 *p_sp_mapping); + +/***********************************************************/ +/** +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param que_id_s 起始队列号 +* @param que_id_e 终止队列号 +* @param en 1:过滤E桶队列CRS状态为SLOW的入链请求；0:E桶队列CRS SLOW正常入链； +* +* @return +* @remark 无 +* @see +* @author XXX @date 2019/05/08 +************************************************************/ +DPP_STATUS dpp_tm_crdt_eir_crs_filter_en_more_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 que_id_s, ZXIC_UINT32 que_id_e, ZXIC_UINT32 en); + + +/***********************************************************/ +/** +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param que_id queue id +* @param p_en +* +* @return +* @remark 无 +* @see +* @author XXX @date 2019/05/08 +************************************************************/ +DPP_STATUS dpp_tm_crdt_eir_crs_filter_en_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 que_id, ZXIC_UINT32 *p_en); + +/***********************************************************/ +/** +* @param dev_id +* @param tm_type +* @param que_id +* +* @return +* @remark 无 +* @see +* @author XXX @date 2019/05/08 +************************************************************/ +DPP_STATUS dpp_tm_crdt_eir_crs_filter_en_get_diag(ZXIC_UINT32 dev_id, ZXIC_UINT32 que_id); + + +/***********************************************************/ +/** 打印指定的全局数组值以及清空全局数组 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param para_x 数组index_x +* @param para_y 数组index_y +* @param clear_flag 清空shape全局数组 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark +* @see +* @author xuhb @date 2019/06/10 +************************************************************/ +DPP_STATUS dpp_tm_shape_para_array_prt(ZXIC_UINT32 dev_id, ZXIC_UINT32 para_x, ZXIC_UINT32 para_y, ZXIC_UINT32 clear_flag); + + +/***********************************************************/ +/** 配置shap模块中 crd_grain授权价值 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param credit_value 授权价值，默认值是0x5feByte +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xuhb @date 2020/08/13 +************************************************************/ +DPP_STATUS dpp_tm_shap_crd_grain_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 credit_value); + + +/***********************************************************/ +/** shap ram初始化 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/03/22 +************************************************************/ +DPP_STATUS dpp_tm_shap_ram_init(ZXIC_UINT32 dev_id); + +/***********************************************************/ +/** 获取流队列双桶整形使能及模式 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param db_en 双桶整形使能 +* @param mode 0:c+e模式，1:c+p模式 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/03/11 +************************************************************/ +DPP_STATUS dpp_tm_shape_flow_db_en_get(DPP_DEV_T *dev, ZXIC_UINT32 *db_en, ZXIC_UINT32 *mode); + +/***********************************************************/ +/** 配置桶深最小单位配置:共8档：0-7 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param token_grain 3’d0：最小单位为128K +* 3’d1：最小单位为64k +* 3’d2：最小单位为32k +* 3’d3：最小单位为16k +* 3’d4：最小单位为8k +* 3’d5：最小单位为4k +* 3’d6：最小单位为2k +* 3’d7：最小单位为1k +* 默认为0，即128K +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/03/11 +************************************************************/ +DPP_STATUS dpp_tm_shape_token_grain_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 token_grain); + +/***********************************************************/ +/** 获取桶深最小单位配置:共8档：0-7 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param token_grain 3’d0：最小单位为128K +* 3’d1：最小单位为64k +* 3’d2：最小单位为32k +* 3’d3：最小单位为16k +* 3’d4：最小单位为8k +* 3’d5：最小单位为4k +* 3’d6：最小单位为2k +* 3’d7：最小单位为1k +* 默认为0，即128K +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/03/11 +************************************************************/ +DPP_STATUS dpp_tm_shape_token_grain_get(DPP_DEV_T *dev, ZXIC_UINT32 *token_grain); + +/***********************************************************/ +/** 配置流或调度器映射到整形参数表的某个ID +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param id 流或调度器编号ETM:0-ABFF,FTM:0-177F +* @param profile_id 整形参数表:[0-127] +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/03/11 +************************************************************/ +DPP_STATUS dpp_tm_shape_map_table_set(DPP_DEV_T *dev, ZXIC_UINT32 id, ZXIC_UINT32 profile_id); + +/***********************************************************/ +/** 获取流或调度器映射到整形参数表的配置ID +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param id 流或调度器编号ETM:0-ABFF,FTM:0-177F +* @param profile_id 整形参数表:[0-127] +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/03/11 +************************************************************/ +DPP_STATUS dpp_tm_shape_map_table_get(DPP_DEV_T *dev, ZXIC_UINT32 id, ZXIC_UINT32 *profile_id); + +/***********************************************************/ +/** 获取流级整形参数 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param flow_id 流队列号 ETM:0-9215,FTM:0-2047 +* @param cir cir速率，单位Kb，范围[64Kb - 160Gb] +* @param cbs cbs桶深，单位KB，范围[1KB - 64M] +* 注：cbs=0 表示关闭整形,即不限速 +* @param mode_e 整形模式，0-获取c桶参数，1-获取对应e桶参数 +* @param p_para_id 整形模板索引：ETM=[0-AFF]，FTM=[0-17F] +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/03/11 +************************************************************/ +DPP_STATUS dpp_tm_shape_flow_para_get(DPP_DEV_T *dev, + ZXIC_UINT32 flow_id, + ZXIC_UINT32 mode, + ZXIC_UINT32 *p_para_id, + DPP_TM_SHAPE_PARA_TABLE *p_flow_para_tbl); + + +/***********************************************************/ +/** etm配置流级整形参数 +* @param dev_id 设备编号 +* @param flow_id 流队列号 ETM:0-9215,FTM:0-2047 +* @param cir cir速率，单位Kb，范围[64Kb - 160Gb] +* @param cbs cbs桶深，单位KB，范围[1KB - 64M] +* @param db_en 双桶整形使能，0-单桶，1-双桶 +* @param eir eir速率，单位Kb，范围同cir +* @param ebs ebs桶深，单位Kb，范围同cbs +* 注：cbs=0 表示关闭整形,即不限速 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/03/11 +************************************************************/ +DPP_STATUS dpp_etm_shape_flow_para_set(DPP_DEV_T *dev, + ZXIC_UINT32 flow_id, + ZXIC_UINT32 cir, + ZXIC_UINT32 cbs, + ZXIC_UINT32 db_en, + ZXIC_UINT32 eir, + ZXIC_UINT32 ebs); + +/***********************************************************/ +/** 获取调度单元整形参数 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param se_id 调度器单元号 ETM:0-63FF,FTM:0-77F +* @param cir cir速率，单位Kb，范围[64Kb - 160Gb] +* @param cbs cbs桶深，单位KB，范围[1KB - 64M] +* @param mode 整形模式，0-获取p桶参数，1-获取对应c桶参数(仅FQ8/WFQ8支持) +* @param p_para_id 整形模板索引：ETM=[0-AFF]，FTM=[0-17F] +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/03/11 +************************************************************/ +DPP_STATUS dpp_tm_shape_se_para_get(DPP_DEV_T *dev, + ZXIC_UINT32 se_id, + ZXIC_UINT32 mode, + ZXIC_UINT32 *p_para_id, + DPP_TM_SHAPE_PARA_TABLE *p_se_para_tbl); + + + +/***********************************************************/ +/** ftm配置调度器整形参数 +* @param dev_id 设备编号 +* @param se_id 调度器编号号 ETM:0x4800-0xABFF,FTM:0x1000-0x177F +* @param pir pir总速率，单位Kb，范围同cir +* @param pbs pbs总桶深，单位Kb，范围同cbs +* @param db_en 整形模式，0-单桶，1-双桶，仅FQ8/WFQ8有效 +* @param cir [0-3]调度器cir速率，单位Kb，范围[64Kb - 160Gb] +* @param cbs [0-3]调度器cbs桶深，单位KB，范围[1KB - 64M] +* 注：cbs=0 表示关闭整形,即不限速 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/03/11 +************************************************************/ +DPP_STATUS dpp_ftm_shape_se_para_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 se_id, + ZXIC_UINT32 pir, + ZXIC_UINT32 pbs, + ZXIC_UINT32 db_en, + ZXIC_UINT32 cir, + ZXIC_UINT32 cbs); + +/***********************************************************/ +/** etm配置调度器整形参数 +* @param dev_id 设备编号 +* @param se_id 调度器编号号 ETM:0x4800-0xABFF,FTM:0x1000-0x177F +* @param pir pir总速率，单位Kb，范围同cir +* @param pbs pbs总桶深，单位Kb，范围同cbs +* @param db_en 整形模式，0-单桶，1-双桶，仅FQ8/WFQ8有效 +* @param cir [0-3]调度器cir速率，单位Kb，范围[64Kb - 160Gb] +* @param cbs [0-3]调度器cbs桶深，单位KB，范围[1KB - 64M] +* 注：cbs=0 表示关闭整形,即不限速 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/03/11 +************************************************************/ +DPP_STATUS dpp_etm_shape_se_para_set(DPP_DEV_T *dev, + ZXIC_UINT32 se_id, + ZXIC_UINT32 pir, + ZXIC_UINT32 pbs, + ZXIC_UINT32 db_en, + ZXIC_UINT32 cir, + ZXIC_UINT32 cbs); + + +/***********************************************************/ +/** 写入流/调度器整形参数配置表 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param map_id 整形参数表中模板索引id ETM:0-AFF,FTM:0-17F +* @param cir 整形速率(c/e桶统一) +* @param cbs 桶深 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/03/11 +************************************************************/ +DPP_STATUS dpp_tm_shape_para_set(DPP_DEV_T *dev, + ZXIC_UINT32 total_para_id, + ZXIC_UINT32 cir, + ZXIC_UINT32 cbs); + +/***********************************************************/ +/** 读取流/调度器整形参数配置表 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param total_para_id 整形参数表中模板索引id ETM:0-AFF,FTM:0-17F +* @param cir 整形速率(c/e桶统一) +* @param cbs 桶深 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/03/11 +************************************************************/ +DPP_STATUS dpp_tm_shape_para_get(DPP_DEV_T *dev, + ZXIC_UINT32 total_para_id, + DPP_TM_SHAPE_PARA_TABLE *p_shap_para_tbl); + +/***********************************************************/ +/** 配置第0~15个被统计得到令牌个数的端口号 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param port_id 被统计得到令牌个数的端口号 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/3/15 STM模式下使用 +************************************************************/ +DPP_STATUS dpp_tm_shape_token_pp_cfg(ZXIC_UINT32 dev_id, + ZXIC_UINT32 port_id); + +/***********************************************************/ +/** 打印各级及指定被统计的第0~15个授权流得到的授权个数 stm模式下使用 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author yjd @date 2015/06/19 +************************************************************/ +DPP_STATUS dpp_tm_crdt_ackcnt_diag(ZXIC_UINT32 dev_id, ZXIC_UINT32 delay_ms); + +/***********************************************************/ +/** 读取端口级整形参数 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param port_id 端口号 +* @param p_para 整形信息:CIR/CBS/EN +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cuiy @date 2016/04/15 +************************************************************/ +DPP_STATUS dpp_tm_shape_pp_para_get(DPP_DEV_T *dev, + ZXIC_UINT32 port_id, + DPP_TM_SHAPE_PP_PARA_T *p_para); + +/***********************************************************/ +/** 配置SA模式下各个版本的授权价值 +* @param dev_id 设备索引编号 +* @param tm_type 0-ETM,1-FTM +* @param sa_ver_id 版本号(0~7) +* @param sa_credit_value 授权价值 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author szq @date 2015/03/25 +************************************************************/ +DPP_STATUS dpp_tm_qmu_sa_credit_value_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 sa_ver_id, + ZXIC_UINT32 sa_credit_value); + +/***********************************************************/ +/** 获取SA模式下各个版本的授权价值 +* @param dev_id 设备索引编号 +* @param tm_type 0-ETM,1-FTM +* @param sa_ver_id 版本号(0~7) +* @param p_sa_credit_value 授权价值 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author szq @date 2015/03/25 +************************************************************/ +DPP_STATUS dpp_tm_qmu_sa_credit_value_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 sa_ver_id, + ZXIC_UINT32 *p_sa_credit_value); + +/***********************************************************/ +/** 配置CRS发送的速率 +* @param dev_id 设备索引编号 +* @param tm_type 0-ETM,1-FTM +* @param sent_cyc CRS发送的间隔(单位:时钟周期) +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author szq @date 2015/03/25 +************************************************************/ +DPP_STATUS dpp_tm_qmu_crs_sent_rate_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 sent_cyc); + +/***********************************************************/ +/** 获取CRS发送的速率 +* @param dev_id 设备索引编号 +* @param tm_type 0-ETM,1-FTM +* @param p_sent_cyc CRS发送的间隔(单位:时钟周期) +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author szq @date 2015/03/25 +************************************************************/ +DPP_STATUS dpp_tm_qmu_crs_sent_rate_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_sent_cyc); + +/***********************************************************/ +/** 配置CRS过滤使能 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param en 配置的值，0-不使能过滤，1-使能过滤 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/03/04 +************************************************************/ +DPP_STATUS dpp_tm_qmu_crs_filter_en_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 en); + + +/***********************************************************/ +/** 配置多播授权令牌添加个数 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param token_add_num 令牌添加时，每次增加的令牌数目，取值范围为1~255，默认为1；禁止配置为0，配置为0时，将不会产生授权。 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/03/09 +************************************************************/ +DPP_STATUS dpp_tm_qmu_mul_token_gen_num_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 token_add_num); + +/***********************************************************/ +/** 配置多播授权整形桶参数和使能参数 +* @param dev_id 设备索引编号 +* @param tm_type 0-ETM,1-FTM +* @param q3_lb_control_en 3号队列整形功能开启使能。0：关闭；1：开启。 +* @param q012_lb_control_en 0～2号队列整形功能开启使能。0：关闭；1：开启。 +* @param q3_lb_max_cnt 3号队列整形桶桶深。 +* @param q012_lb_max_cnt 0～2号队列整形桶桶深。 +* @param q3_lb_add_rate 3号队列令牌添加速率，时钟周期为单位。不可配置为0，配置为0整形使能时，不能产生队列3授权调度信号。 +* @param q012_lb_add_rate 0～2号队列令牌添加速率，以时钟周期单位。不可配置为0，配置为0并整形使能时，不能产生队列0、1、2授权调度信号。 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/03/09 +************************************************************/ +DPP_STATUS dpp_tm_qmu_mul_ack_lb_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 q3_lb_control_en, + ZXIC_UINT32 q012_lb_control_en, + ZXIC_UINT32 q3_lb_max_cnt, + ZXIC_UINT32 q012_lb_max_cnt, + ZXIC_UINT32 q3_lb_add_rate, + ZXIC_UINT32 q012_lb_add_rate); + +/***********************************************************/ +/** 配置0,1号队列挂接1或2号MCN漏桶信息 +* @param tm_type 0-ETM,1-FTM +* @param dev_id 设备索引编号 +* @param mcn_lb_sel 0：0,1号队列挂接1号MCN漏桶 1：0,1号队列挂接2号MCN漏桶 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/03/09 +************************************************************/ +DPP_STATUS dpp_tm_qmu_mcn_lb_sel_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 mcn_lb_sel); + +/***********************************************************/ +/** 配置多播队列0~2的授权输出SP、DWRR +* @param dev_id 设备索引编号 +* @param tm_type 0-ETM,1-FTM +* @param sp_or_dwrr SP、DWRR模式选择。0：SP；1：DWRR。 +* @param dwrr_w0 0号队列DWRR权重(0~127) +* @param dwrr_w1 1号队列DWRR权重(0~127) +* @param dwrr_w2 2号队列DWRR权重(0~127) +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/03/09 +************************************************************/ +DPP_STATUS dpp_tm_qmu_mul_sp_dwrr_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 sp_or_dwrr, + ZXIC_UINT32 dwrr_w0, + ZXIC_UINT32 dwrr_w1, + ZXIC_UINT32 dwrr_w2); + +/***********************************************************/ +/** 配置分目的SA整形打开或关闭 +* @param dev_id 设备索引编号 +* @param tm_type 0-ETM,1-FTM +* @param shap_en 分目的SA整形使能开关 0：表示关闭 1：表示打开 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/03/09 +************************************************************/ +DPP_STATUS dpp_tm_qmu_dest_sa_shap_en_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 shap_en); + +/***********************************************************/ +/** 获得轮转扫描使能和扫描速率 +* @param dev_id 设备索引编号 +* @param tm_type 0-ETM,1-FTM +* @param scan_en 轮转扫描使能。0：关闭，1：开启 +* @param scan_rate 轮转扫描速率，配置扫描周期不得少于256个周期 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/03/10 +************************************************************/ +DPP_STATUS dpp_tm_qmu_scan_rate_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *p_scan_en, + ZXIC_UINT32 *p_scan_rate); + +/***********************************************************/ +/** 配置轮转扫描队列范围 +* @param dev_id 设备索引编号 +* @param tm_type 0-ETM,1-FTM +* @param first_que 起始队列号 +* @param last_que 终止队列号 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author whuashan @date 2019/09/10 +************************************************************/ +DPP_STATUS dpp_tm_qmu_scan_que_range_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 first_que, + ZXIC_UINT32 last_que); + +/***********************************************************/ +/** 获取轮转扫描队列范围 +* @param dev_id 设备索引编号 +* @param tm_type 0-ETM,1-FTM +* @param first_que 起始队列号 +* @param last_que 终止队列号 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author whuashan @date 2019/09/10 +************************************************************/ +DPP_STATUS dpp_tm_qmu_scan_que_range_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *first_que, + ZXIC_UINT32 *last_que); + +/***********************************************************/ +/** 获取QMU清空状态 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_clr_done_flag 队列是否清空完成 +* +* @return +* @remark 无 +* @see +* @author szq @date 2015/05/21 +************************************************************/ +DPP_STATUS dpp_tm_qmu_qlist_qcfg_clr_done_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_clr_done_flag); + + +/***********************************************************/ +/** 配置qsch调度分端口整形速率和使能 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param shape_en 整形使能 +* @param token_add_num [23:12]:添加令牌数目 +* @param token_gap [11:0]:添加令牌间隔，其中实际间隔为配置间隔+1 +* @param token_depth 桶深，单位B,范围[0-0x1EE00] +*公式：（600*8*token_num）/(gap+1) = X Mbps +* 主频= 600 MHz +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author xuhb 2020-5-15 +************************************************************/ +DPP_STATUS dpp_tm_qmu_qsch_port_shape_set(DPP_DEV_T *dev, + ZXIC_UINT32 port_id, + ZXIC_UINT32 token_add_num, + ZXIC_UINT32 token_gap, + ZXIC_UINT32 token_depth, + ZXIC_UINT32 shape_en); + +/***********************************************************/ +/** 配置CMD_SW分端口整形速率和使能 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param shape_en 整形使能 +* @param token_add_num [23:12]:添加令牌数目 +* @param token_gap [11:0]:添加令牌间隔，其中实际间隔为配置间隔+1 +* @param token_depth 桶深，单位B,范围[0-0x1EE00] +*公式：（600*8*token_num）/(gap+1) = X Mbps +* 主频= 600 MHz +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author whuashan 2020-3-17 +************************************************************/ +DPP_STATUS dpp_tm_qmu_port_shape_set(DPP_DEV_T *dev, + ZXIC_UINT32 port_id, + ZXIC_UINT32 token_add_num, + ZXIC_UINT32 token_gap, + ZXIC_UINT32 token_depth, + ZXIC_UINT32 shape_en); + +/***********************************************************/ +/** 获得CMD_SW分端口整形速率和使能 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_shape_en 整形使能 +* @param p_token_add_num [23:12]:添加令牌数目 +* @param p_token_gap [11:0]:添加令牌间隔，其中实际间隔为配置间隔+1 +* @param p_token_depth 桶深，单位B +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author whuashan 2020-3-17 +************************************************************/ +DPP_STATUS dpp_tm_qmu_port_shape_get(DPP_DEV_T *dev, + ZXIC_UINT32 port_id, + ZXIC_UINT32 *p_token_add_num, + ZXIC_UINT32 *p_token_gap, + ZXIC_UINT32 *p_token_depth, + ZXIC_UINT32 *p_shape_en); + +/***********************************************************/ +/** 获取CMD_SW分端口整形速率和使能 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param shape_vlue 整形值，单位Mbps +* @param shape_en 整形使能 +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author zmy @20151217 +************************************************************/ +DPP_STATUS dpp_tm_qmu_egress_shape_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 port_id, + ZXIC_UINT32 *shape_value, + ZXIC_UINT32 *shape_en); + + +/***********************************************************/ +/** 配置需要检测的特定队列号 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param qnum 需要检测统计的特定的队列号 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/06/18 +************************************************************/ +DPP_STATUS dpp_tm_qmu_spec_qnum_set(DPP_DEV_T *dev, ZXIC_UINT32 qnum); + +/***********************************************************/ +/** 获得特定的队列号 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_qnum 需要检测统计的特定的队列号 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/06/23 +************************************************************/ +DPP_STATUS dpp_tm_qmu_spec_qnum_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_qnum); + +/***********************************************************/ +/** 配置需要检测的队列组 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param group_num 需要检测统计的特定的队列组。这里按取q的低3bit +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/06/18 +************************************************************/ +DPP_STATUS dpp_tm_qmu_spec_group_set(DPP_DEV_T *dev, ZXIC_UINT32 group_num); + +/***********************************************************/ +/** 获得需要检测的队列组 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_group_num 需要检测统计的特定的队列组。这里按取q的低3bit +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/06/23 +************************************************************/ +DPP_STATUS dpp_tm_qmu_spec_group_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_group_num); + + +/***********************************************************/ +/** 配置队列授权盈余 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param qnum 配置的队列号 +* @param value 授权盈余 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/06/18 +************************************************************/ +DPP_STATUS dpp_tm_qmu_crbal_value_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 qnum, + ZXIC_UINT32 value); + +/***********************************************************/ +/** 获得队列授权盈余 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param qnum 配置的队列号 +* @param p_value 授权盈余 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/06/23 +************************************************************/ +DPP_STATUS dpp_tm_qmu_crbal_value_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 qnum, + ZXIC_UINT32 *p_value); + +/***********************************************************/ +/** 配置分目的SA整形桶深上、下限参数 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param max_value 分目的SA整形桶深上限，必须配置为正值 +* @param min_value 分目的SA整形桶深下限，必须配置为负值 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/06/18 +************************************************************/ +DPP_STATUS dpp_tm_qmu_dest_sa_shape_para_set(ZXIC_UINT32 dev_id, + ZXIC_SINT32 max_value, + ZXIC_SINT32 min_value); + +/***********************************************************/ +/** 获得分目的SA整形桶深上、下限参数 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_max_value 分目的SA整形桶深上限，必须配置为正值 +* @param p_min_value 分目的SA整形桶深下限，必须配置为负值 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/06/23 +************************************************************/ +DPP_STATUS dpp_tm_qmu_dest_sa_shape_para_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *p_max_value, + ZXIC_UINT32 *p_min_value); + +/***********************************************************/ +/** 获取特定队列发送的crs normal的个数 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param 注 须先设置统计的特定队列 +* @param +* @return +* @remark 无 +* @see +* @author yjd @date 2015/07/09 +************************************************************/ +DPP_STATUS dpp_tm_qmu_spec_q_crs_normal_cnt(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_que_crs_normal_cnt); + +/***********************************************************/ +/** 获取特定队列发送的crs off的个数 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param 注 须先设置统计的特定队列 +* @param +* @return +* @remark 无 +* @see +* @author yjd @date 2015/07/09 +************************************************************/ +DPP_STATUS dpp_tm_qmu_spec_q_crs_off_cnt(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_que_crs_off_cnt); + +/***********************************************************/ +/** QMU初始化配置场景 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param case_no 四组QMU初始化场景编号为1-4;ddr*bank:1:4x2;2:4x4;3:8x2;4:4x8. +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cuiy @date 2016/11/17 +************************************************************/ +DPP_STATUS dpp_tm_qmu_init_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 case_no); + +/***********************************************************/ +/** TMMU TM纯片内模式配置获取 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_imem_en 1纯片内 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author wush @date 2017/10/14 +************************************************************/ +DPP_STATUS dpp_tm_tmmu_imem_en_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_imem_en); + +/***********************************************************/ +/** TMMU 强制DDR RDY配置获取 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_ddr_force_rdy 1、如果bit【0】配置为1，则QMU看到的DDR0 RDY一直为1。 + 2、bit【0】代表DDR0，bit【7】代表DDR7。 + 3、纯片内模式需要配置为8'hff，排除DDR干扰。 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author wush @date 2017/10/14 +************************************************************/ +DPP_STATUS dpp_tm_tmmu_ddr_force_rdy_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_ddr_force_rdy); + +DPP_STATUS dpp_tm_mr_init(ZXIC_UINT32 dev_id); +/***********************************************************/ +/** 配置TM模式下初始化代码 +* @param dev_id +* @param tm_type 0-ETM,1-FTM +* @param p_tm_init_info 配置TM模式下初始化信息包括以下 +* blk_size 配置qmu block大小 +* case_num 四组QMU初始化场景编号为1-4;ddr*bank:1:4x2;2:4x4;3:8x2;4:4x8. +* imem_omem; 0:片内外混合; 1:纯片内;2:纯片外 +* mode 0:TM 1:SA +* +* @return +* @remark 无 +* @see +* @author szq @date 2015/03/26 +************************************************************/ +DPP_STATUS dpp_tm_asic_init(ZXIC_UINT32 dev_id, DPP_TM_ASIC_INIT_INFO_T *p_tm_asic_init_info); + +/***********************************************************/ +/** 配置TM模式下初始化代码 +* @param dev_id +* @param tm_type 0-ETM,1-FTM +* @param p_tm_init_info 配置TM模式下初始化信息包括以下 +* blk_size 配置qmu block大小 +* case_num 四组QMU初始化场景编号为1-4;ddr*bank:1:4x2;2:4x4;3:8x2;4:4x8. +* imem_omem; 0:片内外混合; 1:纯片内;2:纯片外 +* mode 0:TM 1:SA +* +* @return +* @remark 无 +* @see +* @author szq @date 2015/03/26 +************************************************************/ +DPP_STATUS dpp_tm_asic_init_diag(ZXIC_UINT32 dev_id, ZXIC_UINT32 blk_size, ZXIC_UINT32 case_num, ZXIC_UINT32 imem_omem, ZXIC_UINT32 mode); + +/**************************************************************************** +* 函数名称: dpp_tm_avg_que_len_get +* 功能描述: 各级平均队列深度获取 +* 输入参数: dev_id: 设备索引编号 +* @param tm_type 0-ETM,1-FTM +* cgavd_level: 拥塞避免支持层次号，0:队列级，1:端口级，2:系统级 +* que_id: 本级别层次内的队列编号。 +* 输出参数: p_avg_len: 平均队列深度，单位为BLOCK。 +* 返 回 值: DPP_OK-成功，DPP_ERR-失败 +* 其它说明: +* author cy @date 2015/06/29 +*****************************************************************************/ +DPP_STATUS dpp_tm_avg_que_len_get(ZXIC_UINT32 dev_id, + DPP_TM_CGAVD_LEVEL_E cgavd_level, + ZXIC_UINT32 que_id, + ZXIC_UINT32 *p_avg_len); + +/***********************************************************/ +/** 获取配置CPU设置的报文长度是否参与计算丢弃概率的使能 +* @param tm_type 0-ETM,1-FTM +* @param flag 忽略乘法里的当前包长和最大包长比标志位:1为忽略 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cy @date 2015/11/9 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_wred_pke_len_calc_sign_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_flag); + +/***********************************************************/ +/** 配置配置cgavd模式 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param mode 0:block mode 1:byte mode +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cy @date 2016/07/28 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_cfg_mode_set(DPP_DEV_T *dev, + ZXIC_UINT32 mode); + + +/***********************************************************/ +/** 配置配置cgavd模式 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_mode 0:block mode 1:byte mode +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cy @date 2016/07/29 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_cfg_mode_get(DPP_DEV_T *dev, + ZXIC_UINT32 *p_mode); + + +/***********************************************************/ +/** 配置TD拥塞避免模式下的丢弃门限值 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param level 拥塞避免支持层次号，0:队列级，1:端口级，2:系统级 +* @param id 队列号或端口号，系统级时，id参数无效 +* @param byte_block_th 配置的丢弃门限值，ZXIC_UINT8/BLOCK单位写入寄存器 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cy @date 2016/07/29 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_td_byte_block_th_set(DPP_DEV_T *dev, + DPP_TM_CGAVD_LEVEL_E level, + ZXIC_UINT32 id, + ZXIC_UINT32 byte_block_th); + + +/***********************************************************/ +/** 读取TD拥塞避免模式下的丢弃门限值字节模式 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param level 拥塞避免支持层次号，0:队列级，1:端口级，2:系统级 +* @param id 队列号或端口号，系统级时，id参数无效 +* @param p_byte_block_th 配置的丢弃门限值ZXIC_UINT8/BLOCK单位 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cy @date 2016/07/29 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_td_byte_block_th_get(DPP_DEV_T *dev, + DPP_TM_CGAVD_LEVEL_E level, + ZXIC_UINT32 id, + ZXIC_UINT32 *p_byte_block_th); + + +/***********************************************************/ +/** 配置通用门限block模式 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param byte_block_uni_th 通用门限值block/byte单位 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cy @date 2016/08/01 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_uniform_byte_block_th_set(DPP_DEV_T *dev, ZXIC_UINT32 byte_block_uni_th); + +/***********************************************************/ +/** 读取通用门限 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_byte_block_uni_th 通用门限值block/byte单位 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cy @date 2016/08/01 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_uniform_byte_block_th_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_byte_block_uni_th); + + + +/***********TM CPU软复位接口 Begin*************/ +/***********************************************************/ +/** 设置TM的全局变量，shape_para只保存profile被使用的数量，整形相关参数从寄存器中重新读取 +* @param dev_id +* @param size data_buff的长度 +* @param p_data_buff 需要恢复的内容 +* +* @return +* @remark 无 +* @see +* @author XXX @date 2018/06/25 +************************************************************/ +DPP_STATUS dpp_tm_glb_mgr_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 size, ZXIC_UINT8 *p_data_buff); + +/***********************************************************/ +/** 获取TM的全局变量，shape_para只保存profile被使用的数量，整形相关参数从寄存器中重新读取 +* @param dev_id +* @param p_flag 上层释放data_buff的标志，1:需要上层free,0:不需要上层free +* @param p_size data_buff的长度 +* @param pp_data_buff 二级指针(指向函数内部malloc空间的地址) +* +* @return +* @remark 无 +* @see +* @author XXX @date 2018/06/25 +************************************************************/ +DPP_STATUS dpp_tm_glb_mgr_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_flag, ZXIC_UINT32 *p_size, ZXIC_UINT8 **pp_data_buff); + +/***********************************************************/ +/** 获取TM的全局变量，shape_para只保存profile被使用的数量，整形相关参数从寄存器中重新读取 +* @param dev_id +* @param p_size data_buff的长度 +* +* @return +* @remark 无 +* @see +* @author XXX @date 2018/06/25 +************************************************************/ +DPP_STATUS dpp_tm_glb_size_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_size); + + +/***********************************************************/ +/** 配置tm授权价值 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param credit_value 授权价值，默认值是0x5feByte +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xuhb @date 2020/08/13 +************************************************************/ +DPP_STATUS dpp_tm_credit_value_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 credit_value); + +/***********************************************************/ +/** 获取全局数组中用户实际配置的整形值 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param flow_id 流队列号 ETM:0-9215,FTM:0-2047 +* @param cir cir速率，单位Kb，范围[64Kb - 160Gb] +* @param cbs cbs桶深，单位KB，范围[1KB - 64M] +* 注：cbs=0 表示关闭整形,即不限速 +* @param mode_e 整形模式，0-获取c桶参数，1-获取对应e桶参数 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark +* @see +* @author xuhb @date 2019/06/10 +************************************************************/ +DPP_STATUS dpp_tm_shape_flow_para_array_get(DPP_DEV_T *dev, + ZXIC_UINT32 flow_id, + ZXIC_UINT32 mode, + DPP_TM_SHAPE_PARA_TABLE *p_flow_para_tbl); + + +#endif +/* 必须有个空行，否则可能编不过 */ + + + + + + + + + + + + + + diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_axi_reg.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_axi_reg.h new file mode 100644 index 0000000..12bb803 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_axi_reg.h @@ -0,0 +1,50 @@ + +#ifndef _DPP_AXI_REG_H_ +#define _DPP_AXI_REG_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +typedef struct dpp_axi_axi_conv_cfg_epid_v_func_num_t +{ + ZXIC_UINT32 user_en; + ZXIC_UINT32 cfg_epid; + ZXIC_UINT32 cfg_vfunc_num; + ZXIC_UINT32 cfg_func_num; + ZXIC_UINT32 cfg_vfunc_active; +}DPP_AXI_AXI_CONV_CFG_EPID_V_FUNC_NUM_T; + +typedef struct dpp_axi_axi_conv_info_axim_rw_hsk_cnt_t +{ + ZXIC_UINT32 axim_rd_handshake_cnt; + ZXIC_UINT32 axim_wr_handshake_cnt; +}DPP_AXI_AXI_CONV_INFO_AXIM_RW_HSK_CNT_T; + +typedef struct dpp_axi_axi_conv_info_axim_last_wr_id_t +{ + ZXIC_UINT32 axim_rd_id; + ZXIC_UINT32 axim_wr_id; +}DPP_AXI_AXI_CONV_INFO_AXIM_LAST_WR_ID_T; + +typedef struct dpp_axi_axi_conv_info_axim_last_wr_addr_h_t +{ + ZXIC_UINT32 aximlastwraddrhigh; +}DPP_AXI_AXI_CONV_INFO_AXIM_LAST_WR_ADDR_H_T; + +typedef struct dpp_axi_axi_conv_info_axim_last_wr_addr_l_t +{ + ZXIC_UINT32 aximlastrdaddrlow; +}DPP_AXI_AXI_CONV_INFO_AXIM_LAST_WR_ADDR_L_T; + +typedef struct dpp_axi_axi_conv_cfg_debug_info_clr_en_t +{ + ZXIC_UINT32 cfg_global_clr_en; +}DPP_AXI_AXI_CONV_CFG_DEBUG_INFO_CLR_EN_T; + + +#ifdef __cplusplus +} +#endif +#endif + diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_cfg_reg.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_cfg_reg.h new file mode 100644 index 0000000..fa2fd7f --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_cfg_reg.h @@ -0,0 +1,1248 @@ + +#ifndef _DPP_CFG_REG_H_ +#define _DPP_CFG_REG_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +typedef struct dpp_cfg_pcie_int_repeat_t +{ + ZXIC_UINT32 int_repeat; +}DPP_CFG_PCIE_INT_REPEAT_T; + +typedef struct dpp_cfg_dma_dma_up_size_t +{ + ZXIC_UINT32 dma_up_size; +}DPP_CFG_DMA_DMA_UP_SIZE_T; + +typedef struct dpp_cfg_csr_soc_wr_time_out_thresh_t +{ + ZXIC_UINT32 soc_wr_time_out_thresh; +}DPP_CFG_CSR_SOC_WR_TIME_OUT_THRESH_T; + +typedef struct dpp_cfg_pcie_pcie_ddr_switch_t +{ + ZXIC_UINT32 pcie_ddr_switch; +}DPP_CFG_PCIE_PCIE_DDR_SWITCH_T; + +typedef struct dpp_cfg_pcie_user0_int_en_t +{ + ZXIC_UINT32 user_int_en; +}DPP_CFG_PCIE_USER0_INT_EN_T; + +typedef struct dpp_cfg_pcie_user0_int_mask_t +{ + ZXIC_UINT32 user_int_mask; +}DPP_CFG_PCIE_USER0_INT_MASK_T; + +typedef struct dpp_cfg_pcie_user0_int_status_t +{ + ZXIC_UINT32 user_int_status; +}DPP_CFG_PCIE_USER0_INT_STATUS_T; + +typedef struct dpp_cfg_pcie_user1_int_en_t +{ + ZXIC_UINT32 user_int_en; +}DPP_CFG_PCIE_USER1_INT_EN_T; + +typedef struct dpp_cfg_pcie_user1_int_mask_t +{ + ZXIC_UINT32 user_int_mask; +}DPP_CFG_PCIE_USER1_INT_MASK_T; + +typedef struct dpp_cfg_pcie_user1_int_status_t +{ + ZXIC_UINT32 user_int_status; +}DPP_CFG_PCIE_USER1_INT_STATUS_T; + +typedef struct dpp_cfg_pcie_user2_int_en_t +{ + ZXIC_UINT32 user_int_en; +}DPP_CFG_PCIE_USER2_INT_EN_T; + +typedef struct dpp_cfg_pcie_user2_int_mask_t +{ + ZXIC_UINT32 user_int_mask; +}DPP_CFG_PCIE_USER2_INT_MASK_T; + +typedef struct dpp_cfg_pcie_user2_int_status_t +{ + ZXIC_UINT32 user_int_status; +}DPP_CFG_PCIE_USER2_INT_STATUS_T; + +typedef struct dpp_cfg_pcie_ecc_1b_int_en_t +{ + ZXIC_UINT32 ecc_1b_int_en; +}DPP_CFG_PCIE_ECC_1B_INT_EN_T; + +typedef struct dpp_cfg_pcie_ecc_1b_int_mask_t +{ + ZXIC_UINT32 ecc_1b_int_mask; +}DPP_CFG_PCIE_ECC_1B_INT_MASK_T; + +typedef struct dpp_cfg_pcie_ecc_1b_int_status_t +{ + ZXIC_UINT32 ecc_1b_int_status; +}DPP_CFG_PCIE_ECC_1B_INT_STATUS_T; + +typedef struct dpp_cfg_pcie_ecc_2b_int_en_t +{ + ZXIC_UINT32 ecc_2b_int_en; +}DPP_CFG_PCIE_ECC_2B_INT_EN_T; + +typedef struct dpp_cfg_pcie_ecc_2b_int_mask_t +{ + ZXIC_UINT32 ecc_2b_int_mask; +}DPP_CFG_PCIE_ECC_2B_INT_MASK_T; + +typedef struct dpp_cfg_pcie_ecc_2b_int_status_t +{ + ZXIC_UINT32 ecc_2b_int_status; +}DPP_CFG_PCIE_ECC_2B_INT_STATUS_T; + +typedef struct dpp_cfg_pcie_cfg_int_status_t +{ + ZXIC_UINT32 cfg_int_status; +}DPP_CFG_PCIE_CFG_INT_STATUS_T; + +typedef struct dpp_cfg_pcie_i_core_to_cntl_t +{ + ZXIC_UINT32 i_core_to_cntl; +}DPP_CFG_PCIE_I_CORE_TO_CNTL_T; + +typedef struct dpp_cfg_pcie_test_in_low_t +{ + ZXIC_UINT32 test_in_low; +}DPP_CFG_PCIE_TEST_IN_LOW_T; + +typedef struct dpp_cfg_pcie_test_in_high_t +{ + ZXIC_UINT32 test_in_high; +}DPP_CFG_PCIE_TEST_IN_HIGH_T; + +typedef struct dpp_cfg_pcie_local_interrupt_out_t +{ + ZXIC_UINT32 local_interrupt_out; +}DPP_CFG_PCIE_LOCAL_INTERRUPT_OUT_T; + +typedef struct dpp_cfg_pcie_pl_ltssm_t +{ + ZXIC_UINT32 pl_ltssm; +}DPP_CFG_PCIE_PL_LTSSM_T; + +typedef struct dpp_cfg_pcie_test_out0_t +{ + ZXIC_UINT32 test_out0; +}DPP_CFG_PCIE_TEST_OUT0_T; + +typedef struct dpp_cfg_pcie_test_out1_t +{ + ZXIC_UINT32 test_out1; +}DPP_CFG_PCIE_TEST_OUT1_T; + +typedef struct dpp_cfg_pcie_test_out2_t +{ + ZXIC_UINT32 test_out2; +}DPP_CFG_PCIE_TEST_OUT2_T; + +typedef struct dpp_cfg_pcie_test_out3_t +{ + ZXIC_UINT32 test_out3; +}DPP_CFG_PCIE_TEST_OUT3_T; + +typedef struct dpp_cfg_pcie_test_out4_t +{ + ZXIC_UINT32 test_out4; +}DPP_CFG_PCIE_TEST_OUT4_T; + +typedef struct dpp_cfg_pcie_test_out5_t +{ + ZXIC_UINT32 test_out5; +}DPP_CFG_PCIE_TEST_OUT5_T; + +typedef struct dpp_cfg_pcie_test_out6_t +{ + ZXIC_UINT32 test_out6; +}DPP_CFG_PCIE_TEST_OUT6_T; + +typedef struct dpp_cfg_pcie_test_out7_t +{ + ZXIC_UINT32 test_out7; +}DPP_CFG_PCIE_TEST_OUT7_T; + +typedef struct dpp_cfg_pcie_sync_o_core_status_t +{ + ZXIC_UINT32 sync_o_core_status; +}DPP_CFG_PCIE_SYNC_O_CORE_STATUS_T; + +typedef struct dpp_cfg_pcie_sync_o_alert_dbe_t +{ + ZXIC_UINT32 sync_o_alert_dbe; +}DPP_CFG_PCIE_SYNC_O_ALERT_DBE_T; + +typedef struct dpp_cfg_pcie_sync_o_alert_sbe_t +{ + ZXIC_UINT32 sync_o_alert_sbe; +}DPP_CFG_PCIE_SYNC_O_ALERT_SBE_T; + +typedef struct dpp_cfg_pcie_sync_o_link_loopback_en_t +{ + ZXIC_UINT32 sync_o_link_loopback_en; +}DPP_CFG_PCIE_SYNC_O_LINK_LOOPBACK_EN_T; + +typedef struct dpp_cfg_pcie_sync_o_local_fs_lf_valid_t +{ + ZXIC_UINT32 sync_o_local_fs_lf_valid; +}DPP_CFG_PCIE_SYNC_O_LOCAL_FS_LF_VALID_T; + +typedef struct dpp_cfg_pcie_sync_o_rx_idle_detect_t +{ + ZXIC_UINT32 sync_o_rx_idle_detect; +}DPP_CFG_PCIE_SYNC_O_RX_IDLE_DETECT_T; + +typedef struct dpp_cfg_pcie_sync_o_rx_rdy_t +{ + ZXIC_UINT32 sync_o_rx_rdy; +}DPP_CFG_PCIE_SYNC_O_RX_RDY_T; + +typedef struct dpp_cfg_pcie_sync_o_tx_rdy_t +{ + ZXIC_UINT32 sync_o_tx_rdy; +}DPP_CFG_PCIE_SYNC_O_TX_RDY_T; + +typedef struct dpp_cfg_pcie_pcie_link_up_cnt_t +{ + ZXIC_UINT32 pcie_link_up_cnt; +}DPP_CFG_PCIE_PCIE_LINK_UP_CNT_T; + +typedef struct dpp_cfg_pcie_test_out_pcie0_t +{ + ZXIC_UINT32 test_out_pcie0; +}DPP_CFG_PCIE_TEST_OUT_PCIE0_T; + +typedef struct dpp_cfg_pcie_test_out_pcie1_t +{ + ZXIC_UINT32 test_out_pcie1; +}DPP_CFG_PCIE_TEST_OUT_PCIE1_T; + +typedef struct dpp_cfg_pcie_test_out_pcie2_t +{ + ZXIC_UINT32 test_out_pcie2; +}DPP_CFG_PCIE_TEST_OUT_PCIE2_T; + +typedef struct dpp_cfg_pcie_test_out_pcie3_t +{ + ZXIC_UINT32 test_out_pcie3; +}DPP_CFG_PCIE_TEST_OUT_PCIE3_T; + +typedef struct dpp_cfg_pcie_test_out_pcie4_t +{ + ZXIC_UINT32 test_out_pcie4; +}DPP_CFG_PCIE_TEST_OUT_PCIE4_T; + +typedef struct dpp_cfg_pcie_test_out_pcie5_t +{ + ZXIC_UINT32 test_out_pcie5; +}DPP_CFG_PCIE_TEST_OUT_PCIE5_T; + +typedef struct dpp_cfg_pcie_test_out_pcie6_t +{ + ZXIC_UINT32 test_out_pcie6; +}DPP_CFG_PCIE_TEST_OUT_PCIE6_T; + +typedef struct dpp_cfg_pcie_test_out_pcie7_t +{ + ZXIC_UINT32 test_out_pcie7; +}DPP_CFG_PCIE_TEST_OUT_PCIE7_T; + +typedef struct dpp_cfg_pcie_test_out_pcie8_t +{ + ZXIC_UINT32 test_out_pcie8; +}DPP_CFG_PCIE_TEST_OUT_PCIE8_T; + +typedef struct dpp_cfg_pcie_test_out_pcie9_t +{ + ZXIC_UINT32 test_out_pcie9; +}DPP_CFG_PCIE_TEST_OUT_PCIE9_T; + +typedef struct dpp_cfg_pcie_test_out_pcie10_t +{ + ZXIC_UINT32 test_out_pcie10; +}DPP_CFG_PCIE_TEST_OUT_PCIE10_T; + +typedef struct dpp_cfg_pcie_test_out_pcie11_t +{ + ZXIC_UINT32 test_out_pcie11; +}DPP_CFG_PCIE_TEST_OUT_PCIE11_T; + +typedef struct dpp_cfg_pcie_test_out_pcie12_t +{ + ZXIC_UINT32 test_out_pcie12; +}DPP_CFG_PCIE_TEST_OUT_PCIE12_T; + +typedef struct dpp_cfg_pcie_test_out_pcie13_t +{ + ZXIC_UINT32 test_out_pcie13; +}DPP_CFG_PCIE_TEST_OUT_PCIE13_T; + +typedef struct dpp_cfg_pcie_test_out_pcie14_t +{ + ZXIC_UINT32 test_out_pcie14; +}DPP_CFG_PCIE_TEST_OUT_PCIE14_T; + +typedef struct dpp_cfg_pcie_test_out_pcie15_t +{ + ZXIC_UINT32 test_out_pcie15; +}DPP_CFG_PCIE_TEST_OUT_PCIE15_T; + +typedef struct dpp_cfg_pcie_int_repeat_en_t +{ + ZXIC_UINT32 int_repeat_en; +}DPP_CFG_PCIE_INT_REPEAT_EN_T; + +typedef struct dpp_cfg_pcie_dbg_awid_axi_mst_t +{ + ZXIC_UINT32 dbg_awid_axi_mst; +}DPP_CFG_PCIE_DBG_AWID_AXI_MST_T; + +typedef struct dpp_cfg_pcie_dbg_awaddr_axi_mst0_t +{ + ZXIC_UINT32 dbg_awaddr_axi_mst0; +}DPP_CFG_PCIE_DBG_AWADDR_AXI_MST0_T; + +typedef struct dpp_cfg_pcie_dbg_awaddr_axi_mst1_t +{ + ZXIC_UINT32 dbg_awaddr_axi_mst1; +}DPP_CFG_PCIE_DBG_AWADDR_AXI_MST1_T; + +typedef struct dpp_cfg_pcie_dbg_awlen_axi_mst_t +{ + ZXIC_UINT32 dbg_awlen_axi_mst; +}DPP_CFG_PCIE_DBG_AWLEN_AXI_MST_T; + +typedef struct dpp_cfg_pcie_dbg_awsize_axi_mst_t +{ + ZXIC_UINT32 dbg_awid_axi_mst; +}DPP_CFG_PCIE_DBG_AWSIZE_AXI_MST_T; + +typedef struct dpp_cfg_pcie_dbg_awburst_axi_mst_t +{ + ZXIC_UINT32 dbg_awburst_axi_mst; +}DPP_CFG_PCIE_DBG_AWBURST_AXI_MST_T; + +typedef struct dpp_cfg_pcie_dbg_awlock_axi_mst_t +{ + ZXIC_UINT32 dbg_awlock_axi_mst; +}DPP_CFG_PCIE_DBG_AWLOCK_AXI_MST_T; + +typedef struct dpp_cfg_pcie_dbg_awcache_axi_mst_t +{ + ZXIC_UINT32 dbg_awcache_axi_mst; +}DPP_CFG_PCIE_DBG_AWCACHE_AXI_MST_T; + +typedef struct dpp_cfg_pcie_dbg_awprot_axi_mst_t +{ + ZXIC_UINT32 dbg_awprot_axi_mst; +}DPP_CFG_PCIE_DBG_AWPROT_AXI_MST_T; + +typedef struct dpp_cfg_pcie_dbg_wid_axi_mst_t +{ + ZXIC_UINT32 dbg_wid_axi_mst; +}DPP_CFG_PCIE_DBG_WID_AXI_MST_T; + +typedef struct dpp_cfg_pcie_dbg_wdata_axi_mst0_t +{ + ZXIC_UINT32 dbg_wdata_axi_mst0; +}DPP_CFG_PCIE_DBG_WDATA_AXI_MST0_T; + +typedef struct dpp_cfg_pcie_dbg_wdata_axi_mst1_t +{ + ZXIC_UINT32 dbg_wdata_axi_mst1; +}DPP_CFG_PCIE_DBG_WDATA_AXI_MST1_T; + +typedef struct dpp_cfg_pcie_dbg_wdata_axi_mst2_t +{ + ZXIC_UINT32 dbg_wdata_axi_mst2; +}DPP_CFG_PCIE_DBG_WDATA_AXI_MST2_T; + +typedef struct dpp_cfg_pcie_dbg_wdata_axi_mst3_t +{ + ZXIC_UINT32 dbg_wdata_axi_mst3; +}DPP_CFG_PCIE_DBG_WDATA_AXI_MST3_T; + +typedef struct dpp_cfg_pcie_dbg_wstrb_axi_mst_t +{ + ZXIC_UINT32 dbg_wstrb_axi_mst; +}DPP_CFG_PCIE_DBG_WSTRB_AXI_MST_T; + +typedef struct dpp_cfg_pcie_dbg_wlast_axi_mst_t +{ + ZXIC_UINT32 dbg_wlast_axi_mst; +}DPP_CFG_PCIE_DBG_WLAST_AXI_MST_T; + +typedef struct dpp_cfg_pcie_dbg_arid_axi_mst_t +{ + ZXIC_UINT32 dbg_arid_axi_mst; +}DPP_CFG_PCIE_DBG_ARID_AXI_MST_T; + +typedef struct dpp_cfg_pcie_dbg_araddr_axi_mst0_t +{ + ZXIC_UINT32 dbg_araddr_axi_mst0; +}DPP_CFG_PCIE_DBG_ARADDR_AXI_MST0_T; + +typedef struct dpp_cfg_pcie_dbg_araddr_axi_mst1_t +{ + ZXIC_UINT32 dbg_araddr_axi_mst1; +}DPP_CFG_PCIE_DBG_ARADDR_AXI_MST1_T; + +typedef struct dpp_cfg_pcie_dbg_arlen_axi_mst_t +{ + ZXIC_UINT32 dbg_arlen_axi_mst; +}DPP_CFG_PCIE_DBG_ARLEN_AXI_MST_T; + +typedef struct dpp_cfg_pcie_dbg_arsize_axi_mst_t +{ + ZXIC_UINT32 dbg_arsize_axi_mst; +}DPP_CFG_PCIE_DBG_ARSIZE_AXI_MST_T; + +typedef struct dpp_cfg_pcie_dbg_arburst_axi_mst_t +{ + ZXIC_UINT32 dbg_arburst_axi_mst; +}DPP_CFG_PCIE_DBG_ARBURST_AXI_MST_T; + +typedef struct dpp_cfg_pcie_dbg_arlock_axi_mst_t +{ + ZXIC_UINT32 dbg_arlock_axi_mst; +}DPP_CFG_PCIE_DBG_ARLOCK_AXI_MST_T; + +typedef struct dpp_cfg_pcie_dbg_arcache_axi_mst_t +{ + ZXIC_UINT32 dbg_arcache_axi_mst; +}DPP_CFG_PCIE_DBG_ARCACHE_AXI_MST_T; + +typedef struct dpp_cfg_pcie_dbg_arprot_axi_mst_t +{ + ZXIC_UINT32 dbg_arprot_axi_mst; +}DPP_CFG_PCIE_DBG_ARPROT_AXI_MST_T; + +typedef struct dpp_cfg_pcie_dbg_rdata_axi_mst0_t +{ + ZXIC_UINT32 dbg_rdata_axi_mst0; +}DPP_CFG_PCIE_DBG_RDATA_AXI_MST0_T; + +typedef struct dpp_cfg_pcie_dbg_rdata_axi_mst1_t +{ + ZXIC_UINT32 dbg_rdata_axi_mst1; +}DPP_CFG_PCIE_DBG_RDATA_AXI_MST1_T; + +typedef struct dpp_cfg_pcie_dbg_rdata_axi_mst2_t +{ + ZXIC_UINT32 dbg_rdata_axi_mst2; +}DPP_CFG_PCIE_DBG_RDATA_AXI_MST2_T; + +typedef struct dpp_cfg_pcie_dbg_rdata_axi_mst3_t +{ + ZXIC_UINT32 dbg_rdata_axi_mst3; +}DPP_CFG_PCIE_DBG_RDATA_AXI_MST3_T; + +typedef struct dpp_cfg_pcie_axi_mst_state_t +{ + ZXIC_UINT32 axi_mst_state; +}DPP_CFG_PCIE_AXI_MST_STATE_T; + +typedef struct dpp_cfg_pcie_axi_cfg_state_t +{ + ZXIC_UINT32 axi_cfg_state; +}DPP_CFG_PCIE_AXI_CFG_STATE_T; + +typedef struct dpp_cfg_pcie_axi_slv_rd_state_t +{ + ZXIC_UINT32 axi_slv_rd_state; +}DPP_CFG_PCIE_AXI_SLV_RD_STATE_T; + +typedef struct dpp_cfg_pcie_axi_slv_wr_state_t +{ + ZXIC_UINT32 axi_slv_wr_state; +}DPP_CFG_PCIE_AXI_SLV_WR_STATE_T; + +typedef struct dpp_cfg_pcie_axim_delay_en_t +{ + ZXIC_UINT32 axim_delay_en; +}DPP_CFG_PCIE_AXIM_DELAY_EN_T; + +typedef struct dpp_cfg_pcie_axim_delay_t +{ + ZXIC_UINT32 axim_delay; +}DPP_CFG_PCIE_AXIM_DELAY_T; + +typedef struct dpp_cfg_pcie_axim_speed_wr_t +{ + ZXIC_UINT32 axim_speed_wr; +}DPP_CFG_PCIE_AXIM_SPEED_WR_T; + +typedef struct dpp_cfg_pcie_axim_speed_rd_t +{ + ZXIC_UINT32 axim_speed_rd; +}DPP_CFG_PCIE_AXIM_SPEED_RD_T; + +typedef struct dpp_cfg_pcie_dbg_awaddr_axi_slv0_t +{ + ZXIC_UINT32 dbg_awaddr_axi_slv0; +}DPP_CFG_PCIE_DBG_AWADDR_AXI_SLV0_T; + +typedef struct dpp_cfg_pcie_dbg_awaddr_axi_slv1_t +{ + ZXIC_UINT32 dbg_awaddr_axi_slv1; +}DPP_CFG_PCIE_DBG_AWADDR_AXI_SLV1_T; + +typedef struct dpp_cfg_pcie_dbg0_wdata_axi_slv0_t +{ + ZXIC_UINT32 dbg0_wdata_axi_slv0; +}DPP_CFG_PCIE_DBG0_WDATA_AXI_SLV0_T; + +typedef struct dpp_cfg_pcie_dbg0_wdata_axi_slv1_t +{ + ZXIC_UINT32 dbg0_wdata_axi_slv1; +}DPP_CFG_PCIE_DBG0_WDATA_AXI_SLV1_T; + +typedef struct dpp_cfg_pcie_dbg0_wdata_axi_slv2_t +{ + ZXIC_UINT32 dbg0_wdata_axi_slv2; +}DPP_CFG_PCIE_DBG0_WDATA_AXI_SLV2_T; + +typedef struct dpp_cfg_pcie_dbg0_wdata_axi_slv3_t +{ + ZXIC_UINT32 dbg0_wdata_axi_slv3; +}DPP_CFG_PCIE_DBG0_WDATA_AXI_SLV3_T; + +typedef struct dpp_cfg_pcie_dbg1_wdata_axi_slv0_t +{ + ZXIC_UINT32 dbg1_wdata_axi_slv0; +}DPP_CFG_PCIE_DBG1_WDATA_AXI_SLV0_T; + +typedef struct dpp_cfg_pcie_dbg1_wdata_axi_slv1_t +{ + ZXIC_UINT32 dbg1_wdata_axi_slv1; +}DPP_CFG_PCIE_DBG1_WDATA_AXI_SLV1_T; + +typedef struct dpp_cfg_pcie_dbg1_wdata_axi_slv2_t +{ + ZXIC_UINT32 dbg1_wdata_axi_slv2; +}DPP_CFG_PCIE_DBG1_WDATA_AXI_SLV2_T; + +typedef struct dpp_cfg_pcie_dbg1_wdata_axi_slv3_t +{ + ZXIC_UINT32 dbg1_wdata_axi_slv3; +}DPP_CFG_PCIE_DBG1_WDATA_AXI_SLV3_T; + +typedef struct dpp_cfg_pcie_dbg2_wdata_axi_slv0_t +{ + ZXIC_UINT32 dbg2_wdata_axi_slv0; +}DPP_CFG_PCIE_DBG2_WDATA_AXI_SLV0_T; + +typedef struct dpp_cfg_pcie_dbg2_wdata_axi_slv1_t +{ + ZXIC_UINT32 dbg2_wdata_axi_slv1; +}DPP_CFG_PCIE_DBG2_WDATA_AXI_SLV1_T; + +typedef struct dpp_cfg_pcie_dbg2_wdata_axi_slv2_t +{ + ZXIC_UINT32 dbg2_wdata_axi_slv2; +}DPP_CFG_PCIE_DBG2_WDATA_AXI_SLV2_T; + +typedef struct dpp_cfg_pcie_dbg2_wdata_axi_slv3_t +{ + ZXIC_UINT32 dbg2_wdata_axi_slv3; +}DPP_CFG_PCIE_DBG2_WDATA_AXI_SLV3_T; + +typedef struct dpp_cfg_pcie_dbg3_wdata_axi_slv0_t +{ + ZXIC_UINT32 dbg3_wdata_axi_slv0; +}DPP_CFG_PCIE_DBG3_WDATA_AXI_SLV0_T; + +typedef struct dpp_cfg_pcie_dbg3_wdata_axi_slv1_t +{ + ZXIC_UINT32 dbg3_wdata_axi_slv1; +}DPP_CFG_PCIE_DBG3_WDATA_AXI_SLV1_T; + +typedef struct dpp_cfg_pcie_dbg3_wdata_axi_slv2_t +{ + ZXIC_UINT32 dbg3_wdata_axi_slv2; +}DPP_CFG_PCIE_DBG3_WDATA_AXI_SLV2_T; + +typedef struct dpp_cfg_pcie_dbg3_wdata_axi_slv3_t +{ + ZXIC_UINT32 dbg3_wdata_axi_slv3; +}DPP_CFG_PCIE_DBG3_WDATA_AXI_SLV3_T; + +typedef struct dpp_cfg_pcie_dbg4_wdata_axi_slv0_t +{ + ZXIC_UINT32 dbg4_wdata_axi_slv0; +}DPP_CFG_PCIE_DBG4_WDATA_AXI_SLV0_T; + +typedef struct dpp_cfg_pcie_dbg4_wdata_axi_slv1_t +{ + ZXIC_UINT32 dbg4_wdata_axi_slv1; +}DPP_CFG_PCIE_DBG4_WDATA_AXI_SLV1_T; + +typedef struct dpp_cfg_pcie_dbg4_wdata_axi_slv2_t +{ + ZXIC_UINT32 dbg4_wdata_axi_slv2; +}DPP_CFG_PCIE_DBG4_WDATA_AXI_SLV2_T; + +typedef struct dpp_cfg_pcie_dbg4_wdata_axi_slv3_t +{ + ZXIC_UINT32 dbg4_wdata_axi_slv3; +}DPP_CFG_PCIE_DBG4_WDATA_AXI_SLV3_T; + +typedef struct dpp_cfg_pcie_dbg5_wdata_axi_slv0_t +{ + ZXIC_UINT32 dbg5_wdata_axi_slv0; +}DPP_CFG_PCIE_DBG5_WDATA_AXI_SLV0_T; + +typedef struct dpp_cfg_pcie_dbg5_wdata_axi_slv1_t +{ + ZXIC_UINT32 dbg5_wdata_axi_slv1; +}DPP_CFG_PCIE_DBG5_WDATA_AXI_SLV1_T; + +typedef struct dpp_cfg_pcie_dbg5_wdata_axi_slv2_t +{ + ZXIC_UINT32 dbg5_wdata_axi_slv2; +}DPP_CFG_PCIE_DBG5_WDATA_AXI_SLV2_T; + +typedef struct dpp_cfg_pcie_dbg5_wdata_axi_slv3_t +{ + ZXIC_UINT32 dbg5_wdata_axi_slv3; +}DPP_CFG_PCIE_DBG5_WDATA_AXI_SLV3_T; + +typedef struct dpp_cfg_pcie_dbg6_wdata_axi_slv0_t +{ + ZXIC_UINT32 dbg6_wdata_axi_slv0; +}DPP_CFG_PCIE_DBG6_WDATA_AXI_SLV0_T; + +typedef struct dpp_cfg_pcie_dbg6_wdata_axi_slv1_t +{ + ZXIC_UINT32 dbg6_wdata_axi_slv1; +}DPP_CFG_PCIE_DBG6_WDATA_AXI_SLV1_T; + +typedef struct dpp_cfg_pcie_dbg6_wdata_axi_slv2_t +{ + ZXIC_UINT32 dbg6_wdata_axi_slv2; +}DPP_CFG_PCIE_DBG6_WDATA_AXI_SLV2_T; + +typedef struct dpp_cfg_pcie_dbg6_wdata_axi_slv3_t +{ + ZXIC_UINT32 dbg6_wdata_axi_slv3; +}DPP_CFG_PCIE_DBG6_WDATA_AXI_SLV3_T; + +typedef struct dpp_cfg_pcie_dbg7_wdata_axi_slv0_t +{ + ZXIC_UINT32 dbg7_wdata_axi_slv0; +}DPP_CFG_PCIE_DBG7_WDATA_AXI_SLV0_T; + +typedef struct dpp_cfg_pcie_dbg7_wdata_axi_slv1_t +{ + ZXIC_UINT32 dbg7_wdata_axi_slv1; +}DPP_CFG_PCIE_DBG7_WDATA_AXI_SLV1_T; + +typedef struct dpp_cfg_pcie_dbg7_wdata_axi_slv2_t +{ + ZXIC_UINT32 dbg7_wdata_axi_slv2; +}DPP_CFG_PCIE_DBG7_WDATA_AXI_SLV2_T; + +typedef struct dpp_cfg_pcie_dbg7_wdata_axi_slv3_t +{ + ZXIC_UINT32 dbg7_wdata_axi_slv3; +}DPP_CFG_PCIE_DBG7_WDATA_AXI_SLV3_T; + +typedef struct dpp_cfg_pcie_dbg8_wdata_axi_slv0_t +{ + ZXIC_UINT32 dbg8_wdata_axi_slv0; +}DPP_CFG_PCIE_DBG8_WDATA_AXI_SLV0_T; + +typedef struct dpp_cfg_pcie_dbg8_wdata_axi_slv1_t +{ + ZXIC_UINT32 dbg8_wdata_axi_slv1; +}DPP_CFG_PCIE_DBG8_WDATA_AXI_SLV1_T; + +typedef struct dpp_cfg_pcie_dbg8_wdata_axi_slv2_t +{ + ZXIC_UINT32 dbg8_wdata_axi_slv2; +}DPP_CFG_PCIE_DBG8_WDATA_AXI_SLV2_T; + +typedef struct dpp_cfg_pcie_dbg8_wdata_axi_slv3_t +{ + ZXIC_UINT32 dbg8_wdata_axi_slv3; +}DPP_CFG_PCIE_DBG8_WDATA_AXI_SLV3_T; + +typedef struct dpp_cfg_pcie_dbg9_wdata_axi_slv0_t +{ + ZXIC_UINT32 dbg9_wdata_axi_slv0; +}DPP_CFG_PCIE_DBG9_WDATA_AXI_SLV0_T; + +typedef struct dpp_cfg_pcie_dbg9_wdata_axi_slv1_t +{ + ZXIC_UINT32 dbg9_wdata_axi_slv1; +}DPP_CFG_PCIE_DBG9_WDATA_AXI_SLV1_T; + +typedef struct dpp_cfg_pcie_dbg9_wdata_axi_slv2_t +{ + ZXIC_UINT32 dbg9_wdata_axi_slv2; +}DPP_CFG_PCIE_DBG9_WDATA_AXI_SLV2_T; + +typedef struct dpp_cfg_pcie_dbg9_wdata_axi_slv3_t +{ + ZXIC_UINT32 dbg9_wdata_axi_slv3; +}DPP_CFG_PCIE_DBG9_WDATA_AXI_SLV3_T; + +typedef struct dpp_cfg_pcie_dbg_awlen_axi_slv_t +{ + ZXIC_UINT32 dbg_awlen_axi_slv; +}DPP_CFG_PCIE_DBG_AWLEN_AXI_SLV_T; + +typedef struct dpp_cfg_pcie_dbg_wlast_axi_slv_t +{ + ZXIC_UINT32 dbg_wlast_axi_slv; +}DPP_CFG_PCIE_DBG_WLAST_AXI_SLV_T; + +typedef struct dpp_cfg_pcie_dbg_araddr_axi_slv0_t +{ + ZXIC_UINT32 dbg5_wdata_axi_slv1; +}DPP_CFG_PCIE_DBG_ARADDR_AXI_SLV0_T; + +typedef struct dpp_cfg_pcie_dbg_araddr_axi_slv1_t +{ + ZXIC_UINT32 dbg5_wdata_axi_slv2; +}DPP_CFG_PCIE_DBG_ARADDR_AXI_SLV1_T; + +typedef struct dpp_cfg_pcie_dbg0_rdata_axi_slv0_t +{ + ZXIC_UINT32 dbg5_wdata_axi_slv3; +}DPP_CFG_PCIE_DBG0_RDATA_AXI_SLV0_T; + +typedef struct dpp_cfg_pcie_dbg0_rdata_axi_slv1_t +{ + ZXIC_UINT32 dbg6_wdata_axi_slv0; +}DPP_CFG_PCIE_DBG0_RDATA_AXI_SLV1_T; + +typedef struct dpp_cfg_pcie_dbg0_rdata_axi_slv2_t +{ + ZXIC_UINT32 dbg6_wdata_axi_slv1; +}DPP_CFG_PCIE_DBG0_RDATA_AXI_SLV2_T; + +typedef struct dpp_cfg_pcie_dbg0_rdata_axi_slv3_t +{ + ZXIC_UINT32 dbg6_wdata_axi_slv2; +}DPP_CFG_PCIE_DBG0_RDATA_AXI_SLV3_T; + +typedef struct dpp_cfg_pcie_dbg1_rdata_axi_slv0_t +{ + ZXIC_UINT32 dbg6_wdata_axi_slv3; +}DPP_CFG_PCIE_DBG1_RDATA_AXI_SLV0_T; + +typedef struct dpp_cfg_pcie_dbg1_rdata_axi_slv1_t +{ + ZXIC_UINT32 dbg7_wdata_axi_slv0; +}DPP_CFG_PCIE_DBG1_RDATA_AXI_SLV1_T; + +typedef struct dpp_cfg_pcie_dbg1_rdata_axi_slv2_t +{ + ZXIC_UINT32 dbg7_wdata_axi_slv1; +}DPP_CFG_PCIE_DBG1_RDATA_AXI_SLV2_T; + +typedef struct dpp_cfg_pcie_dbg1_rdata_axi_slv3_t +{ + ZXIC_UINT32 dbg7_wdata_axi_slv2; +}DPP_CFG_PCIE_DBG1_RDATA_AXI_SLV3_T; + +typedef struct dpp_cfg_pcie_dbg_rlast_axi_slv_t +{ + ZXIC_UINT32 dbg_rlast_axi_slv; +}DPP_CFG_PCIE_DBG_RLAST_AXI_SLV_T; + +typedef struct dpp_cfg_dma_dma_enable_t +{ + ZXIC_UINT32 dma_enable; +}DPP_CFG_DMA_DMA_ENABLE_T; + +typedef struct dpp_cfg_dma_up_req_t +{ + ZXIC_UINT32 up_req; +}DPP_CFG_DMA_UP_REQ_T; + +typedef struct dpp_cfg_dma_dma_up_current_state_t +{ + ZXIC_UINT32 dma_up_current_state; +}DPP_CFG_DMA_DMA_UP_CURRENT_STATE_T; + +typedef struct dpp_cfg_dma_dma_up_req_ack_t +{ + ZXIC_UINT32 dma_up_req_ack; +}DPP_CFG_DMA_DMA_UP_REQ_ACK_T; + +typedef struct dpp_cfg_dma_dma_done_latch_t +{ + ZXIC_UINT32 done_latch; +}DPP_CFG_DMA_DMA_DONE_LATCH_T; + +typedef struct dpp_cfg_dma_dma_up_cpu_addr_low32_t +{ + ZXIC_UINT32 dma_up_cpu_addr_low; +}DPP_CFG_DMA_DMA_UP_CPU_ADDR_LOW32_T; + +typedef struct dpp_cfg_dma_dma_up_cpu_addr_high32_t +{ + ZXIC_UINT32 dma_up_cpu_addr_high; +}DPP_CFG_DMA_DMA_UP_CPU_ADDR_HIGH32_T; + +typedef struct dpp_cfg_dma_dma_up_se_addr_t +{ + ZXIC_UINT32 dma_up_se_addr; +}DPP_CFG_DMA_DMA_UP_SE_ADDR_T; + +typedef struct dpp_cfg_dma_dma_done_int_t +{ + ZXIC_UINT32 dma_done_int; +}DPP_CFG_DMA_DMA_DONE_INT_T; + +typedef struct dpp_cfg_dma_sp_cfg_t +{ + ZXIC_UINT32 sp_cfg; +}DPP_CFG_DMA_SP_CFG_T; + +typedef struct dpp_cfg_dma_dma_ing_t +{ + ZXIC_UINT32 dma_ing; +}DPP_CFG_DMA_DMA_ING_T; + +typedef struct dpp_cfg_dma_rd_timeout_thresh_t +{ + ZXIC_UINT32 rd_timeout_thresh; +}DPP_CFG_DMA_RD_TIMEOUT_THRESH_T; + +typedef struct dpp_cfg_dma_dma_tab_sta_up_fifo_gap_t +{ + ZXIC_UINT32 dma_tab_sta_up_fifo_gap; +}DPP_CFG_DMA_DMA_TAB_STA_UP_FIFO_GAP_T; + +typedef struct dpp_cfg_dma_cfg_mac_tim_t +{ + ZXIC_UINT32 cfg_mac_tim; +}DPP_CFG_DMA_CFG_MAC_TIM_T; + +typedef struct dpp_cfg_dma_cfg_mac_num_t +{ + ZXIC_UINT32 cfg_mac_num; +}DPP_CFG_DMA_CFG_MAC_NUM_T; + +typedef struct dpp_cfg_dma_init_bd_addr_t +{ + ZXIC_UINT32 init_bd_addr; +}DPP_CFG_DMA_INIT_BD_ADDR_T; + +typedef struct dpp_cfg_dma_mac_up_bd_addr1_low32_t +{ + ZXIC_UINT32 mac_up_bd_addr1_low32; +}DPP_CFG_DMA_MAC_UP_BD_ADDR1_LOW32_T; + +typedef struct dpp_cfg_dma_mac_up_bd_addr1_high32_t +{ + ZXIC_UINT32 mac_up_bd_addr1_high32; +}DPP_CFG_DMA_MAC_UP_BD_ADDR1_HIGH32_T; + +typedef struct dpp_cfg_dma_mac_up_bd_addr2_low32_t +{ + ZXIC_UINT32 mac_up_bd_addr2_low32; +}DPP_CFG_DMA_MAC_UP_BD_ADDR2_LOW32_T; + +typedef struct dpp_cfg_dma_mac_up_bd_addr2_high32_t +{ + ZXIC_UINT32 mac_up_bd_addr2_high32; +}DPP_CFG_DMA_MAC_UP_BD_ADDR2_HIGH32_T; + +typedef struct dpp_cfg_dma_cfg_mac_max_num_t +{ + ZXIC_UINT32 cfg_mac_max_num; +}DPP_CFG_DMA_CFG_MAC_MAX_NUM_T; + +typedef struct dpp_cfg_dma_dma_wbuf_ff_empty_t +{ + ZXIC_UINT32 dma_wbuf_ff_empty; +}DPP_CFG_DMA_DMA_WBUF_FF_EMPTY_T; + +typedef struct dpp_cfg_dma_dma_wbuf_state_t +{ + ZXIC_UINT32 dma_wbuf_state; +}DPP_CFG_DMA_DMA_WBUF_STATE_T; + +typedef struct dpp_cfg_dma_dma_mac_bd_addr_low32_t +{ + ZXIC_UINT32 dma_mac_bd_addr_low32; +}DPP_CFG_DMA_DMA_MAC_BD_ADDR_LOW32_T; + +typedef struct dpp_cfg_dma_dma_mac_bd_addr_high32_t +{ + ZXIC_UINT32 dma_mac_bd_addr_high32; +}DPP_CFG_DMA_DMA_MAC_BD_ADDR_HIGH32_T; + +typedef struct dpp_cfg_dma_mac_up_enable_t +{ + ZXIC_UINT32 mac_up_enable; +}DPP_CFG_DMA_MAC_UP_ENABLE_T; + +typedef struct dpp_cfg_dma_mac_endian_t +{ + ZXIC_UINT32 mac_endian; +}DPP_CFG_DMA_MAC_ENDIAN_T; + +typedef struct dpp_cfg_dma_up_endian_t +{ + ZXIC_UINT32 up_endian; +}DPP_CFG_DMA_UP_ENDIAN_T; + +typedef struct dpp_cfg_dma_dma_up_rd_cnt_latch_t +{ + ZXIC_UINT32 dma_up_rd_cnt_latch; +}DPP_CFG_DMA_DMA_UP_RD_CNT_LATCH_T; + +typedef struct dpp_cfg_dma_dma_up_rcv_cnt_latch_t +{ + ZXIC_UINT32 dma_up_rcv_cnt_latch; +}DPP_CFG_DMA_DMA_UP_RCV_CNT_LATCH_T; + +typedef struct dpp_cfg_dma_dma_up_cnt_latch_t +{ + ZXIC_UINT32 dma_up_cnt_latch; +}DPP_CFG_DMA_DMA_UP_CNT_LATCH_T; + +typedef struct dpp_cfg_dma_cpu_rd_bd_pulse_t +{ + ZXIC_UINT32 cpu_rd_bd_pulse; +}DPP_CFG_DMA_CPU_RD_BD_PULSE_T; + +typedef struct dpp_cfg_dma_cpu_bd_threshold_t +{ + ZXIC_UINT32 cpu_bd_threshold; +}DPP_CFG_DMA_CPU_BD_THRESHOLD_T; + +typedef struct dpp_cfg_dma_cpu_bd_used_cnt_t +{ + ZXIC_UINT32 cpu_bd_used_cnt; +}DPP_CFG_DMA_CPU_BD_USED_CNT_T; + +typedef struct dpp_cfg_dma_dma_up_rcv_status_t +{ + ZXIC_UINT32 dma_up_rcv_status; +}DPP_CFG_DMA_DMA_UP_RCV_STATUS_T; + +typedef struct dpp_cfg_dma_slv_rid_err_en_t +{ + ZXIC_UINT32 slv_rid_err_en; +}DPP_CFG_DMA_SLV_RID_ERR_EN_T; + +typedef struct dpp_cfg_dma_slv_rresp_err_en_t +{ + ZXIC_UINT32 slv_rresp_err_en; +}DPP_CFG_DMA_SLV_RRESP_ERR_EN_T; + +typedef struct dpp_cfg_dma_se_rdbk_ff_full_t +{ + ZXIC_UINT32 se_rdbk_ff_full; +}DPP_CFG_DMA_SE_RDBK_FF_FULL_T; + +typedef struct dpp_cfg_dma_dma_up_data_count_t +{ + ZXIC_UINT32 dma_up_data_count; +}DPP_CFG_DMA_DMA_UP_DATA_COUNT_T; + +typedef struct dpp_cfg_dma_dma_mwr_fifo_afull_gap_t +{ + ZXIC_UINT32 dma_mwr_fifo_afull_gap; +}DPP_CFG_DMA_DMA_MWR_FIFO_AFULL_GAP_T; + +typedef struct dpp_cfg_dma_dma_info_fifo_afull_gap_t +{ + ZXIC_UINT32 dma_mwr_fifo_afull_gap; +}DPP_CFG_DMA_DMA_INFO_FIFO_AFULL_GAP_T; + +typedef struct dpp_cfg_dma_dma_rd_timeout_set_t +{ + ZXIC_UINT32 dma_rd_timeout_set; +}DPP_CFG_DMA_DMA_RD_TIMEOUT_SET_T; + +typedef struct dpp_cfg_dma_dma_bd_dat_err_en_t +{ + ZXIC_UINT32 dma_bd_dat_err_en; +}DPP_CFG_DMA_DMA_BD_DAT_ERR_EN_T; + +typedef struct dpp_cfg_dma_dma_repeat_cnt_t +{ + ZXIC_UINT32 dma_repeat_cnt; +}DPP_CFG_DMA_DMA_REPEAT_CNT_T; + +typedef struct dpp_cfg_dma_dma_rd_timeout_en_t +{ + ZXIC_UINT32 dma_rd_timeout_en; +}DPP_CFG_DMA_DMA_RD_TIMEOUT_EN_T; + +typedef struct dpp_cfg_dma_dma_repeat_read_t +{ + ZXIC_UINT32 dma_repeat_read; +}DPP_CFG_DMA_DMA_REPEAT_READ_T; + +typedef struct dpp_cfg_dma_dma_repeat_read_en_t +{ + ZXIC_UINT32 dma_repeat_read_en; +}DPP_CFG_DMA_DMA_REPEAT_READ_EN_T; + +typedef struct dpp_cfg_dma_bd_ctl_state_t +{ + ZXIC_UINT32 bd_ctl_state; +}DPP_CFG_DMA_BD_CTL_STATE_T; + +typedef struct dpp_cfg_dma_dma_done_int_cnt_wr_t +{ + ZXIC_UINT32 dma_done_int_cnt_wr; +}DPP_CFG_DMA_DMA_DONE_INT_CNT_WR_T; + +typedef struct dpp_cfg_dma_dma_done_int_cnt_mac_t +{ + ZXIC_UINT32 dma_done_int_cnt_mac; +}DPP_CFG_DMA_DMA_DONE_INT_CNT_MAC_T; + +typedef struct dpp_cfg_dma_current_mac_num_t +{ + ZXIC_UINT32 current_mac_num; +}DPP_CFG_DMA_CURRENT_MAC_NUM_T; + +typedef struct dpp_cfg_dma_cfg_mac_afifo_afull_t +{ + ZXIC_UINT32 cfg_mac_afifo_afull; +}DPP_CFG_DMA_CFG_MAC_AFIFO_AFULL_T; + +typedef struct dpp_cfg_dma_dma_mac_ff_full_t +{ + ZXIC_UINT32 dma_mac_ff_full; +}DPP_CFG_DMA_DMA_MAC_FF_FULL_T; + +typedef struct dpp_cfg_dma_user_axi_mst_t +{ + ZXIC_UINT32 user_en; + ZXIC_UINT32 cfg_epid; + ZXIC_UINT32 cfg_vfunc_num; + ZXIC_UINT32 cfg_func_num; + ZXIC_UINT32 cfg_vfunc_active; +}DPP_CFG_DMA_USER_AXI_MST_T; + +typedef struct dpp_cfg_csr_sbus_state_t +{ + ZXIC_UINT32 sbus_state; +}DPP_CFG_CSR_SBUS_STATE_T; + +typedef struct dpp_cfg_csr_mst_debug_en_t +{ + ZXIC_UINT32 mst_debug_en; +}DPP_CFG_CSR_MST_DEBUG_EN_T; + +typedef struct dpp_cfg_csr_sbus_command_sel_t +{ + ZXIC_UINT32 sbus_command_sel; +}DPP_CFG_CSR_SBUS_COMMAND_SEL_T; + +typedef struct dpp_cfg_csr_soc_rd_time_out_thresh_t +{ + ZXIC_UINT32 soc_rd_time_out_thresh; +}DPP_CFG_CSR_SOC_RD_TIME_OUT_THRESH_T; + +typedef struct dpp_cfg_csr_big_little_byte_order_t +{ + ZXIC_UINT32 big_little_byte_order; +}DPP_CFG_CSR_BIG_LITTLE_BYTE_ORDER_T; + +typedef struct dpp_cfg_csr_ecc_bypass_read_t +{ + ZXIC_UINT32 ecc_bypass_read; +}DPP_CFG_CSR_ECC_BYPASS_READ_T; + +typedef struct dpp_cfg_csr_ahb_async_wr_fifo_afull_gap_t +{ + ZXIC_UINT32 ahb_async_wr_fifo_afull_gap; +}DPP_CFG_CSR_AHB_ASYNC_WR_FIFO_AFULL_GAP_T; + +typedef struct dpp_cfg_csr_ahb_async_rd_fifo_afull_gap_t +{ + ZXIC_UINT32 ahb_async_rd_fifo_afull_gap; +}DPP_CFG_CSR_AHB_ASYNC_RD_FIFO_AFULL_GAP_T; + +typedef struct dpp_cfg_csr_ahb_async_cpl_fifo_afull_gap_t +{ + ZXIC_UINT32 ahb_async_cpl_fifo_afull_gap; +}DPP_CFG_CSR_AHB_ASYNC_CPL_FIFO_AFULL_GAP_T; + +typedef struct dpp_cfg_csr_mst_debug_data0_high26_t +{ + ZXIC_UINT32 mst_debug_data0_high26; +}DPP_CFG_CSR_MST_DEBUG_DATA0_HIGH26_T; + +typedef struct dpp_cfg_csr_mst_debug_data0_low32_t +{ + ZXIC_UINT32 mst_debug_data0_low32; +}DPP_CFG_CSR_MST_DEBUG_DATA0_LOW32_T; + +typedef struct dpp_cfg_csr_mst_debug_data1_high26_t +{ + ZXIC_UINT32 mst_debug_data1_high26; +}DPP_CFG_CSR_MST_DEBUG_DATA1_HIGH26_T; + +typedef struct dpp_cfg_csr_mst_debug_data1_low32_t +{ + ZXIC_UINT32 mst_debug_data1_low32; +}DPP_CFG_CSR_MST_DEBUG_DATA1_LOW32_T; + +typedef struct dpp_cfg_csr_mst_debug_data2_high26_t +{ + ZXIC_UINT32 mst_debug_data2_high26; +}DPP_CFG_CSR_MST_DEBUG_DATA2_HIGH26_T; + +typedef struct dpp_cfg_csr_mst_debug_data2_low32_t +{ + ZXIC_UINT32 mst_debug_data2_low32; +}DPP_CFG_CSR_MST_DEBUG_DATA2_LOW32_T; + +typedef struct dpp_cfg_csr_mst_debug_data3_high26_t +{ + ZXIC_UINT32 mst_debug_data3_high26; +}DPP_CFG_CSR_MST_DEBUG_DATA3_HIGH26_T; + +typedef struct dpp_cfg_csr_mst_debug_data3_low32_t +{ + ZXIC_UINT32 mst_debug_data3_low32; +}DPP_CFG_CSR_MST_DEBUG_DATA3_LOW32_T; + +typedef struct dpp_cfg_csr_mst_debug_data4_high26_t +{ + ZXIC_UINT32 mst_debug_data4_high26; +}DPP_CFG_CSR_MST_DEBUG_DATA4_HIGH26_T; + +typedef struct dpp_cfg_csr_mst_debug_data4_low32_t +{ + ZXIC_UINT32 mst_debug_data4_low32; +}DPP_CFG_CSR_MST_DEBUG_DATA4_LOW32_T; + +typedef struct dpp_cfg_csr_mst_debug_data5_high26_t +{ + ZXIC_UINT32 mst_debug_data5_high26; +}DPP_CFG_CSR_MST_DEBUG_DATA5_HIGH26_T; + +typedef struct dpp_cfg_csr_mst_debug_data5_low32_t +{ + ZXIC_UINT32 mst_debug_data5_low32; +}DPP_CFG_CSR_MST_DEBUG_DATA5_LOW32_T; + +typedef struct dpp_cfg_csr_mst_debug_data6_high26_t +{ + ZXIC_UINT32 mst_debug_data6_high26; +}DPP_CFG_CSR_MST_DEBUG_DATA6_HIGH26_T; + +typedef struct dpp_cfg_csr_mst_debug_data6_low32_t +{ + ZXIC_UINT32 mst_debug_data6_low32; +}DPP_CFG_CSR_MST_DEBUG_DATA6_LOW32_T; + +typedef struct dpp_cfg_csr_mst_debug_data7_high26_t +{ + ZXIC_UINT32 mst_debug_data7_high26; +}DPP_CFG_CSR_MST_DEBUG_DATA7_HIGH26_T; + +typedef struct dpp_cfg_csr_mst_debug_data7_low32_t +{ + ZXIC_UINT32 mst_debug_data7_low32; +}DPP_CFG_CSR_MST_DEBUG_DATA7_LOW32_T; + +typedef struct dpp_cfg_csr_mst_debug_data8_high26_t +{ + ZXIC_UINT32 mst_debug_data8_high26; +}DPP_CFG_CSR_MST_DEBUG_DATA8_HIGH26_T; + +typedef struct dpp_cfg_csr_mst_debug_data8_low32_t +{ + ZXIC_UINT32 mst_debug_data8_low32; +}DPP_CFG_CSR_MST_DEBUG_DATA8_LOW32_T; + +typedef struct dpp_cfg_csr_mst_debug_data9_high26_t +{ + ZXIC_UINT32 mst_debug_data9_high26; +}DPP_CFG_CSR_MST_DEBUG_DATA9_HIGH26_T; + +typedef struct dpp_cfg_csr_mst_debug_data9_low32_t +{ + ZXIC_UINT32 mst_debug_data9_low32; +}DPP_CFG_CSR_MST_DEBUG_DATA9_LOW32_T; + +typedef struct dpp_cfg_csr_mst_debug_data10_high26_t +{ + ZXIC_UINT32 mst_debug_data10_high26; +}DPP_CFG_CSR_MST_DEBUG_DATA10_HIGH26_T; + +typedef struct dpp_cfg_csr_mst_debug_data10_low32_t +{ + ZXIC_UINT32 mst_debug_data10_low32; +}DPP_CFG_CSR_MST_DEBUG_DATA10_LOW32_T; + +typedef struct dpp_cfg_csr_mst_debug_data11_high26_t +{ + ZXIC_UINT32 mst_debug_data11_high26; +}DPP_CFG_CSR_MST_DEBUG_DATA11_HIGH26_T; + +typedef struct dpp_cfg_csr_mst_debug_data11_low32_t +{ + ZXIC_UINT32 mst_debug_data11_low32; +}DPP_CFG_CSR_MST_DEBUG_DATA11_LOW32_T; + +typedef struct dpp_cfg_csr_mst_debug_data12_high26_t +{ + ZXIC_UINT32 mst_debug_data12_high26; +}DPP_CFG_CSR_MST_DEBUG_DATA12_HIGH26_T; + +typedef struct dpp_cfg_csr_mst_debug_data12_low32_t +{ + ZXIC_UINT32 mst_debug_data12_low32; +}DPP_CFG_CSR_MST_DEBUG_DATA12_LOW32_T; + +typedef struct dpp_cfg_csr_mst_debug_data13_high26_t +{ + ZXIC_UINT32 mst_debug_data13_high26; +}DPP_CFG_CSR_MST_DEBUG_DATA13_HIGH26_T; + +typedef struct dpp_cfg_csr_mst_debug_data13_low32_t +{ + ZXIC_UINT32 mst_debug_data13_low32; +}DPP_CFG_CSR_MST_DEBUG_DATA13_LOW32_T; + +typedef struct dpp_cfg_csr_mst_debug_data14_high26_t +{ + ZXIC_UINT32 mst_debug_data14_high26; +}DPP_CFG_CSR_MST_DEBUG_DATA14_HIGH26_T; + +typedef struct dpp_cfg_csr_mst_debug_data14_low32_t +{ + ZXIC_UINT32 mst_debug_data14_low32; +}DPP_CFG_CSR_MST_DEBUG_DATA14_LOW32_T; + +typedef struct dpp_cfg_csr_mst_debug_data15_high26_t +{ + ZXIC_UINT32 mst_debug_data15_high26; +}DPP_CFG_CSR_MST_DEBUG_DATA15_HIGH26_T; + +typedef struct dpp_cfg_csr_mst_debug_data15_low32_t +{ + ZXIC_UINT32 mst_debug_data15_low32; +}DPP_CFG_CSR_MST_DEBUG_DATA15_LOW32_T; + + +#ifdef __cplusplus +} +#endif +#endif + diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_dtb4k_reg.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_dtb4k_reg.h new file mode 100644 index 0000000..5ae6c12 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_dtb4k_reg.h @@ -0,0 +1,47 @@ + +#ifndef _DPP_DTB4K_REG_H_ +#define _DPP_DTB4K_REG_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +typedef struct dpp_dtb4k_dtb_enq_cfg_queue_dtb_addr_h_0_127_t +{ + ZXIC_UINT32 cfg_queue_dtb_addr_h; +}DPP_DTB4K_DTB_ENQ_CFG_QUEUE_DTB_ADDR_H_0_127_T; + +typedef struct dpp_dtb4k_dtb_enq_cfg_queue_dtb_addr_l_0_127_t +{ + ZXIC_UINT32 cfg_queue_dtb_addr_l; +}DPP_DTB4K_DTB_ENQ_CFG_QUEUE_DTB_ADDR_L_0_127_T; + +typedef struct dpp_dtb4k_dtb_enq_cfg_queue_dtb_len_0_127_t +{ + ZXIC_UINT32 cfg_dtb_cmd_type; + ZXIC_UINT32 cfg_dtb_cmd_int_en; + ZXIC_UINT32 cfg_queue_dtb_len; +}DPP_DTB4K_DTB_ENQ_CFG_QUEUE_DTB_LEN_0_127_T; + +typedef struct dpp_dtb4k_dtb_enq_info_queue_buf_space_left_0_127_t +{ + ZXIC_UINT32 info_queue_buf_space_left; +}DPP_DTB4K_DTB_ENQ_INFO_QUEUE_BUF_SPACE_LEFT_0_127_T; + +typedef struct dpp_dtb4k_dtb_enq_cfg_epid_v_func_num_0_127_t +{ + ZXIC_UINT32 dbi_en; + ZXIC_UINT32 queue_en; + ZXIC_UINT32 cfg_epid; + ZXIC_UINT32 cfg_vfunc_num; + ZXIC_UINT32 cfg_vector; + ZXIC_UINT32 cfg_func_num; + ZXIC_UINT32 cfg_vfunc_active; +}DPP_DTB4K_DTB_ENQ_CFG_EPID_V_FUNC_NUM_0_127_T; + + +#ifdef __cplusplus +} +#endif +#endif + diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_dtb_reg.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_dtb_reg.h new file mode 100644 index 0000000..b0989ce --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_dtb_reg.h @@ -0,0 +1,599 @@ + +#ifndef _DPP_DTB_REG_H_ +#define _DPP_DTB_REG_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +typedef struct dpp_dtb_dtb_cfg_cfg_eram_wr_interval_cnt_t +{ + ZXIC_UINT32 cfg_eram_wr_interval_cnt; +}DPP_DTB_DTB_CFG_CFG_ERAM_WR_INTERVAL_CNT_T; + +typedef struct dpp_dtb_dtb_cfg_cfg_zcam_wr_interval_cnt_t +{ + ZXIC_UINT32 cfg_zcam_wr_interval_cnt; +}DPP_DTB_DTB_CFG_CFG_ZCAM_WR_INTERVAL_CNT_T; + +typedef struct dpp_dtb_dtb_cfg_cfg_tcam_wr_interval_cnt_t +{ + ZXIC_UINT32 cfg_zcam_wr_interval_cnt; +}DPP_DTB_DTB_CFG_CFG_TCAM_WR_INTERVAL_CNT_T; + +typedef struct dpp_dtb_dtb_cfg_cfg_ddr_wr_interval_cnt_t +{ + ZXIC_UINT32 cfg_ddr_wr_interval_cnt; +}DPP_DTB_DTB_CFG_CFG_DDR_WR_INTERVAL_CNT_T; + +typedef struct dpp_dtb_dtb_cfg_cfg_hash_wr_interval_cnt_t +{ + ZXIC_UINT32 cfg_hash_wr_interval_cnt; +}DPP_DTB_DTB_CFG_CFG_HASH_WR_INTERVAL_CNT_T; + +typedef struct dpp_dtb_dtb_cfg_cfg_eram_rd_interval_cnt_t +{ + ZXIC_UINT32 cfg_eram_rd_interval_cnt; +}DPP_DTB_DTB_CFG_CFG_ERAM_RD_INTERVAL_CNT_T; + +typedef struct dpp_dtb_dtb_cfg_cfg_zcam_rd_interval_cnt_t +{ + ZXIC_UINT32 cfg_zcam_rd_interval_cnt; +}DPP_DTB_DTB_CFG_CFG_ZCAM_RD_INTERVAL_CNT_T; + +typedef struct dpp_dtb_dtb_cfg_cfg_tcam_rd_interval_cnt_t +{ + ZXIC_UINT32 cfg_tcam_rd_interval_cnt; +}DPP_DTB_DTB_CFG_CFG_TCAM_RD_INTERVAL_CNT_T; + +typedef struct dpp_dtb_dtb_cfg_cfg_ddr_rd_interval_cnt_t +{ + ZXIC_UINT32 cfg_ddr_rd_interval_cnt; +}DPP_DTB_DTB_CFG_CFG_DDR_RD_INTERVAL_CNT_T; + +typedef struct dpp_dtb_dtb_cfg_cfg_dtb_queue_lock_state_0_3_t +{ + ZXIC_UINT32 cfg_dtb_queue_lock_state; +}DPP_DTB_DTB_CFG_CFG_DTB_QUEUE_LOCK_STATE_0_3_T; + +typedef struct dpp_dtb_dtb_axim0_w_convert_0_mode_t +{ + ZXIC_UINT32 w_convert_mode; +}DPP_DTB_DTB_AXIM0_W_CONVERT_0_MODE_T; + +typedef struct dpp_dtb_dtb_axim0_r_convert_0_mode_t +{ + ZXIC_UINT32 r_convert_mode; +}DPP_DTB_DTB_AXIM0_R_CONVERT_0_MODE_T; + +typedef struct dpp_dtb_dtb_axim0_aximr_os_t +{ + ZXIC_UINT32 aximr_os; +}DPP_DTB_DTB_AXIM0_AXIMR_OS_T; + +typedef struct dpp_dtb_dtb_axim1_w_convert_1_mode_t +{ + ZXIC_UINT32 w_convert_mode; +}DPP_DTB_DTB_AXIM1_W_CONVERT_1_MODE_T; + +typedef struct dpp_dtb_dtb_axim1_r_convert_1_mode_t +{ + ZXIC_UINT32 r_convert_mode; +}DPP_DTB_DTB_AXIM1_R_CONVERT_1_MODE_T; + +typedef struct dpp_dtb_dtb_axis_axis_convert_mode_t +{ + ZXIC_UINT32 w_r_convert_mode; +}DPP_DTB_DTB_AXIS_AXIS_CONVERT_MODE_T; + +typedef struct dpp_dtb_dtb_cfg_cfg_finish_int_event0_t +{ + ZXIC_UINT32 cfg_finish_int_event0; +}DPP_DTB_DTB_CFG_CFG_FINISH_INT_EVENT0_T; + +typedef struct dpp_dtb_dtb_cfg_cfg_finish_int_event1_t +{ + ZXIC_UINT32 cfg_finish_int_event1; +}DPP_DTB_DTB_CFG_CFG_FINISH_INT_EVENT1_T; + +typedef struct dpp_dtb_dtb_cfg_cfg_finish_int_event2_t +{ + ZXIC_UINT32 cfg_finish_int_event2; +}DPP_DTB_DTB_CFG_CFG_FINISH_INT_EVENT2_T; + +typedef struct dpp_dtb_dtb_cfg_cfg_finish_int_event3_t +{ + ZXIC_UINT32 cfg_finish_int_event3; +}DPP_DTB_DTB_CFG_CFG_FINISH_INT_EVENT3_T; + +typedef struct dpp_dtb_dtb_cfg_cfg_finish_int_maks0_t +{ + ZXIC_UINT32 cfg_finish_int_mask0; +}DPP_DTB_DTB_CFG_CFG_FINISH_INT_MAKS0_T; + +typedef struct dpp_dtb_dtb_cfg_cfg_finish_int_maks1_t +{ + ZXIC_UINT32 cfg_finish_int_mask1; +}DPP_DTB_DTB_CFG_CFG_FINISH_INT_MAKS1_T; + +typedef struct dpp_dtb_dtb_cfg_cfg_finish_int_maks2_t +{ + ZXIC_UINT32 cfg_finish_int_mask2; +}DPP_DTB_DTB_CFG_CFG_FINISH_INT_MAKS2_T; + +typedef struct dpp_dtb_dtb_cfg_cfg_finish_int_maks3_t +{ + ZXIC_UINT32 cfg_finish_int_mask3; +}DPP_DTB_DTB_CFG_CFG_FINISH_INT_MAKS3_T; + +typedef struct dpp_dtb_dtb_cfg_cfg_finish_int_test0_t +{ + ZXIC_UINT32 cfg_finish_int_test0; +}DPP_DTB_DTB_CFG_CFG_FINISH_INT_TEST0_T; + +typedef struct dpp_dtb_dtb_cfg_cfg_finish_int_test1_t +{ + ZXIC_UINT32 cfg_finish_int_test1; +}DPP_DTB_DTB_CFG_CFG_FINISH_INT_TEST1_T; + +typedef struct dpp_dtb_dtb_cfg_cfg_finish_int_test2_t +{ + ZXIC_UINT32 cfg_finish_int_test2; +}DPP_DTB_DTB_CFG_CFG_FINISH_INT_TEST2_T; + +typedef struct dpp_dtb_dtb_cfg_cfg_finish_int_test3_t +{ + ZXIC_UINT32 cfg_finish_int_test3; +}DPP_DTB_DTB_CFG_CFG_FINISH_INT_TEST3_T; + +typedef struct dpp_dtb_dtb_cfg_cfg_dtb_int_to_riscv_sel_t +{ + ZXIC_UINT32 cfg_dtb_int_to_riscv_sel0; +}DPP_DTB_DTB_CFG_CFG_DTB_INT_TO_RISCV_SEL_T; + +typedef struct dpp_dtb_dtb_cfg_cfg_dtb_ep_int_msix_enable_t +{ + ZXIC_UINT32 cfg_dtb_ep_int_msix_enable; +}DPP_DTB_DTB_CFG_CFG_DTB_EP_INT_MSIX_ENABLE_T; + +typedef struct dpp_dtb_dtb_cfg_cfg_dtb_ep_doorbell_addr_h_0_15_t +{ + ZXIC_UINT32 cfg_dtb_ep_doorbell_addr_h_0_15; +}DPP_DTB_DTB_CFG_CFG_DTB_EP_DOORBELL_ADDR_H_0_15_T; + +typedef struct dpp_dtb_dtb_cfg_cfg_dtb_ep_doorbell_addr_l_0_15_t +{ + ZXIC_UINT32 cfg_dtb_ep_doorbell_addr_l_0_15; +}DPP_DTB_DTB_CFG_CFG_DTB_EP_DOORBELL_ADDR_L_0_15_T; + +typedef struct dpp_dtb_dtb_cfg_cfg_dtb_debug_mode_en_t +{ + ZXIC_UINT32 cfg_dtb_debug_mode_en; +}DPP_DTB_DTB_CFG_CFG_DTB_DEBUG_MODE_EN_T; + +typedef struct dpp_dtb_dtb_cfg_info_axi_last_rd_table_addr_high_t +{ + ZXIC_UINT32 info_axi_last_rd_table_addr_high; +}DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_ADDR_HIGH_T; + +typedef struct dpp_dtb_dtb_cfg_info_axi_last_rd_table_addr_low_t +{ + ZXIC_UINT32 info_axi_last_rd_table_addr_low; +}DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_ADDR_LOW_T; + +typedef struct dpp_dtb_dtb_cfg_info_axi_last_rd_table_len_t +{ + ZXIC_UINT32 info_axi_last_rd_table_len; +}DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_LEN_T; + +typedef struct dpp_dtb_dtb_cfg_info_axi_last_rd_table_user_t +{ + ZXIC_UINT32 info_rd_table_user_en; + ZXIC_UINT32 info_rd_table_epid; + ZXIC_UINT32 info_rd_table_vfunc_num; + ZXIC_UINT32 info_rd_table_func_num; + ZXIC_UINT32 info_rd_table_vfunc_active; +}DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_USER_T; + +typedef struct dpp_dtb_dtb_cfg_info_axi_last_rd_table_onload_cnt_t +{ + ZXIC_UINT32 info_axi_last_rd_table_onload_cnt; +}DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_ONLOAD_CNT_T; + +typedef struct dpp_dtb_dtb_cfg_cnt_axi_rd_table_resp_err_t +{ + ZXIC_UINT32 cnt_axi_rd_table_resp_err; +}DPP_DTB_DTB_CFG_CNT_AXI_RD_TABLE_RESP_ERR_T; + +typedef struct dpp_dtb_dtb_cfg_info_axi_last_rd_pd_addr_high_t +{ + ZXIC_UINT32 info_axi_last_rd_pd_addr_high; +}DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_ADDR_HIGH_T; + +typedef struct dpp_dtb_dtb_cfg_info_axi_last_rd_pd_addr_low_t +{ + ZXIC_UINT32 info_axi_last_rd_pd_addr_low; +}DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_ADDR_LOW_T; + +typedef struct dpp_dtb_dtb_cfg_info_axi_last_rd_pd_len_t +{ + ZXIC_UINT32 info_axi_last_rd_pd_len; +}DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_LEN_T; + +typedef struct dpp_dtb_dtb_cfg_info_axi_last_rd_pd_user_t +{ + ZXIC_UINT32 info_rd_pd_user_en; + ZXIC_UINT32 info_rd_pd_epid; + ZXIC_UINT32 info_rd_pd_vfunc_num; + ZXIC_UINT32 info_rd_pd_func_num; + ZXIC_UINT32 info_rd_pd_vfunc_active; +}DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_USER_T; + +typedef struct dpp_dtb_dtb_cfg_info_axi_last_rd_pd_onload_cnt_t +{ + ZXIC_UINT32 info_axi_last_rd_pd_onload_cnt; +}DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_ONLOAD_CNT_T; + +typedef struct dpp_dtb_dtb_cfg_cnt_axi_rd_pd_resp_err_t +{ + ZXIC_UINT32 cnt_axi_rd_pd_resp_err; +}DPP_DTB_DTB_CFG_CNT_AXI_RD_PD_RESP_ERR_T; + +typedef struct dpp_dtb_dtb_cfg_info_axi_last_wr_ctrl_addr_high_t +{ + ZXIC_UINT32 info_axi_last_wr_ctrl_addr_high; +}DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_ADDR_HIGH_T; + +typedef struct dpp_dtb_dtb_cfg_info_axi_last_wr_ctrl_addr_low_t +{ + ZXIC_UINT32 info_axi_last_wr_ctrl_addr_low; +}DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_ADDR_LOW_T; + +typedef struct dpp_dtb_dtb_cfg_info_axi_last_wr_ctrl_len_t +{ + ZXIC_UINT32 info_axi_last_wr_ctrl_len; +}DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_LEN_T; + +typedef struct dpp_dtb_dtb_cfg_info_axi_last_wr_ctrl_user_t +{ + ZXIC_UINT32 info_wr_ctrl_user_en; + ZXIC_UINT32 info_wr_ctrl_epid; + ZXIC_UINT32 info_wr_ctrl_vfunc_num; + ZXIC_UINT32 info_wr_ctrl_func_num; + ZXIC_UINT32 info_wr_ctrl_vfunc_active; +}DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_USER_T; + +typedef struct dpp_dtb_dtb_cfg_info_axi_last_wr_ctrl_onload_cnt_t +{ + ZXIC_UINT32 info_axi_last_wr_ctrl_onload_cnt; +}DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_ONLOAD_CNT_T; + +typedef struct dpp_dtb_dtb_cfg_cnt_axi_wr_ctrl_resp_err_t +{ + ZXIC_UINT32 cnt_axi_wr_ctrl_resp_err; +}DPP_DTB_DTB_CFG_CNT_AXI_WR_CTRL_RESP_ERR_T; + +typedef struct dpp_dtb_dtb_cfg_info_axi_last_wr_ddr_addr_high_t +{ + ZXIC_UINT32 info_axi_last_wr_ddr_addr_high; +}DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_ADDR_HIGH_T; + +typedef struct dpp_dtb_dtb_cfg_info_axi_last_wr_ddr_addr_low_t +{ + ZXIC_UINT32 info_axi_last_wr_ddr_addr_low; +}DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_ADDR_LOW_T; + +typedef struct dpp_dtb_dtb_cfg_info_axi_last_wr_ddr_len_t +{ + ZXIC_UINT32 info_axi_last_wr_ddr_len; +}DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_LEN_T; + +typedef struct dpp_dtb_dtb_cfg_info_axi_last_wr_ddr_user_t +{ + ZXIC_UINT32 info_wr_ddr_user_en; + ZXIC_UINT32 info_wr_ddr_epid; + ZXIC_UINT32 info_wr_ddr_vfunc_num; + ZXIC_UINT32 info_wr_ddr_func_num; + ZXIC_UINT32 info_wr_ddr_vfunc_active; +}DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_USER_T; + +typedef struct dpp_dtb_dtb_cfg_info_axi_last_wr_ddr_onload_cnt_t +{ + ZXIC_UINT32 info_axi_last_wr_ddr_onload_cnt; +}DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_ONLOAD_CNT_T; + +typedef struct dpp_dtb_dtb_cfg_cnt_axi_wr_ddr_resp_err_t +{ + ZXIC_UINT32 cnt_axi_wr_ddr_resp_err; +}DPP_DTB_DTB_CFG_CNT_AXI_WR_DDR_RESP_ERR_T; + +typedef struct dpp_dtb_dtb_cfg_info_axi_last_wr_fin_addr_high_t +{ + ZXIC_UINT32 info_axi_last_wr_fin_addr_high; +}DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_ADDR_HIGH_T; + +typedef struct dpp_dtb_dtb_cfg_info_axi_last_wr_fin_addr_low_t +{ + ZXIC_UINT32 info_axi_last_wr_fin_addr_low; +}DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_ADDR_LOW_T; + +typedef struct dpp_dtb_dtb_cfg_info_axi_last_wr_fin_len_t +{ + ZXIC_UINT32 info_axi_last_wr_fin_len; +}DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_LEN_T; + +typedef struct dpp_dtb_dtb_cfg_info_axi_last_wr_fin_user_t +{ + ZXIC_UINT32 info_wr_fin_user_en; + ZXIC_UINT32 info_wr_fin_epid; + ZXIC_UINT32 info_wr_fin_vfunc_num; + ZXIC_UINT32 info_wr_fin_func_num; + ZXIC_UINT32 info_wr_fin_vfunc_active; +}DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_USER_T; + +typedef struct dpp_dtb_dtb_cfg_info_axi_last_wr_fin_onload_cnt_t +{ + ZXIC_UINT32 info_axi_last_wr_fin_onload_cnt; +}DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_ONLOAD_CNT_T; + +typedef struct dpp_dtb_dtb_cfg_cnt_axi_wr_fin_resp_err_t +{ + ZXIC_UINT32 cnt_axi_wr_fin_resp_err; +}DPP_DTB_DTB_CFG_CNT_AXI_WR_FIN_RESP_ERR_T; + +typedef struct dpp_dtb_dtb_cfg_cnt_dtb_wr_smmu0_table_high_t +{ + ZXIC_UINT32 cnt_dtb_wr_smmu0_table_high; +}DPP_DTB_DTB_CFG_CNT_DTB_WR_SMMU0_TABLE_HIGH_T; + +typedef struct dpp_dtb_dtb_cfg_cnt_dtb_wr_smmu0_table_low_t +{ + ZXIC_UINT32 cnt_dtb_wr_smmu0_table_low; +}DPP_DTB_DTB_CFG_CNT_DTB_WR_SMMU0_TABLE_LOW_T; + +typedef struct dpp_dtb_dtb_cfg_cnt_dtb_wr_smmu1_table_high_t +{ + ZXIC_UINT32 cnt_dtb_wr_smmu1_table_high; +}DPP_DTB_DTB_CFG_CNT_DTB_WR_SMMU1_TABLE_HIGH_T; + +typedef struct dpp_dtb_dtb_cfg_cnt_dtb_wr_smmu1_table_low_t +{ + ZXIC_UINT32 cnt_dtb_wr_smmu1_table_low; +}DPP_DTB_DTB_CFG_CNT_DTB_WR_SMMU1_TABLE_LOW_T; + +typedef struct dpp_dtb_dtb_cfg_cnt_dtb_wr_zcam_table_high_t +{ + ZXIC_UINT32 cnt_dtb_wr_zcam_table_high; +}DPP_DTB_DTB_CFG_CNT_DTB_WR_ZCAM_TABLE_HIGH_T; + +typedef struct dpp_dtb_dtb_cfg_cnt_dtb_wr_zcam_table_low_t +{ + ZXIC_UINT32 cnt_dtb_wr_zcam_table_low; +}DPP_DTB_DTB_CFG_CNT_DTB_WR_ZCAM_TABLE_LOW_T; + +typedef struct dpp_dtb_dtb_cfg_cnt_dtb_wr_etcam_table_high_t +{ + ZXIC_UINT32 cnt_dtb_wr_etcam_table_high; +}DPP_DTB_DTB_CFG_CNT_DTB_WR_ETCAM_TABLE_HIGH_T; + +typedef struct dpp_dtb_dtb_cfg_cnt_dtb_wr_etcam_table_low_t +{ + ZXIC_UINT32 cnt_dtb_wr_etcam_table_low; +}DPP_DTB_DTB_CFG_CNT_DTB_WR_ETCAM_TABLE_LOW_T; + +typedef struct dpp_dtb_dtb_cfg_cnt_dtb_wr_hash_table_high_t +{ + ZXIC_UINT32 cnt_dtb_wr_hash_table_high; +}DPP_DTB_DTB_CFG_CNT_DTB_WR_HASH_TABLE_HIGH_T; + +typedef struct dpp_dtb_dtb_cfg_cnt_dtb_wr_hash_table_low_t +{ + ZXIC_UINT32 cnt_dtb_wr_hash_table_low; +}DPP_DTB_DTB_CFG_CNT_DTB_WR_HASH_TABLE_LOW_T; + +typedef struct dpp_dtb_dtb_cfg_cnt_dtb_rd_smmu0_table_high_t +{ + ZXIC_UINT32 cnt_dtb_rd_smmu0_table_high; +}DPP_DTB_DTB_CFG_CNT_DTB_RD_SMMU0_TABLE_HIGH_T; + +typedef struct dpp_dtb_dtb_cfg_cnt_dtb_rd_smmu0_table_low_t +{ + ZXIC_UINT32 cnt_dtb_rd_smmu0_table_low; +}DPP_DTB_DTB_CFG_CNT_DTB_RD_SMMU0_TABLE_LOW_T; + +typedef struct dpp_dtb_dtb_cfg_cnt_dtb_rd_smmu1_table_high_t +{ + ZXIC_UINT32 cnt_dtb_rd_smmu1_table_high; +}DPP_DTB_DTB_CFG_CNT_DTB_RD_SMMU1_TABLE_HIGH_T; + +typedef struct dpp_dtb_dtb_cfg_cnt_dtb_rd_smmu1_table_low_t +{ + ZXIC_UINT32 cnt_dtb_rd_smmu1_table_low; +}DPP_DTB_DTB_CFG_CNT_DTB_RD_SMMU1_TABLE_LOW_T; + +typedef struct dpp_dtb_dtb_cfg_cnt_dtb_rd_zcam_table_high_t +{ + ZXIC_UINT32 cnt_dtb_rd_zcam_table_high; +}DPP_DTB_DTB_CFG_CNT_DTB_RD_ZCAM_TABLE_HIGH_T; + +typedef struct dpp_dtb_dtb_cfg_cnt_dtb_rd_zcam_table_low_t +{ + ZXIC_UINT32 cnt_dtb_rd_zcam_table_low; +}DPP_DTB_DTB_CFG_CNT_DTB_RD_ZCAM_TABLE_LOW_T; + +typedef struct dpp_dtb_dtb_cfg_cnt_dtb_rd_etcam_table_high_t +{ + ZXIC_UINT32 cnt_dtb_rd_etcam_table_high; +}DPP_DTB_DTB_CFG_CNT_DTB_RD_ETCAM_TABLE_HIGH_T; + +typedef struct dpp_dtb_dtb_cfg_cnt_dtb_rd_etcam_table_low_t +{ + ZXIC_UINT32 cnt_dtb_rd_etcam_table_low; +}DPP_DTB_DTB_CFG_CNT_DTB_RD_ETCAM_TABLE_LOW_T; + +typedef struct dpp_dtb_dtb_cfg_info_wr_ctrl_state_t +{ + ZXIC_UINT32 info_wr_ctrl_state; +}DPP_DTB_DTB_CFG_INFO_WR_CTRL_STATE_T; + +typedef struct dpp_dtb_dtb_cfg_info_rd_table_state_t +{ + ZXIC_UINT32 info_rd_table_state; +}DPP_DTB_DTB_CFG_INFO_RD_TABLE_STATE_T; + +typedef struct dpp_dtb_dtb_cfg_info_rd_pd_state_t +{ + ZXIC_UINT32 info_rd_pd_state; +}DPP_DTB_DTB_CFG_INFO_RD_PD_STATE_T; + +typedef struct dpp_dtb_dtb_cfg_info_dump_cmd_state_t +{ + ZXIC_UINT32 info_dump_cmd_state; +}DPP_DTB_DTB_CFG_INFO_DUMP_CMD_STATE_T; + +typedef struct dpp_dtb_dtb_cfg_info_wr_ddr_state_t +{ + ZXIC_UINT32 info_wr_ddr_state; +}DPP_DTB_DTB_CFG_INFO_WR_DDR_STATE_T; + +typedef struct dpp_dtb_dtb_cfg_cfg_dtb_debug_info_clr_t +{ + ZXIC_UINT32 cfg_dtb_debug_info_clr; +}DPP_DTB_DTB_CFG_CFG_DTB_DEBUG_INFO_CLR_T; + +typedef struct dpp_dtb_ddos_cfg_ddos_stat_dump_thrd_0_15_t +{ + ZXIC_UINT32 cfg_ddos_stat_dump_thrd; +}DPP_DTB_DDOS_CFG_DDOS_STAT_DUMP_THRD_0_15_T; + +typedef struct dpp_dtb_ddos_cfg_ddos_stat_dump_thrd_comp_en_t +{ + ZXIC_UINT32 cfg_ddos_stat_dump_thrd_comp_en; +}DPP_DTB_DDOS_CFG_DDOS_STAT_DUMP_THRD_COMP_EN_T; + +typedef struct dpp_dtb_ddos_cfg_ddos_dump_stat_num_t +{ + ZXIC_UINT32 cfg_ddos_dump_stat_num; +}DPP_DTB_DDOS_CFG_DDOS_DUMP_STAT_NUM_T; + +typedef struct dpp_dtb_ddos_cfg_ddos_even_hash_table_baddr_t +{ + ZXIC_UINT32 cfg_ddos_even_hash_table_baddr; +}DPP_DTB_DDOS_CFG_DDOS_EVEN_HASH_TABLE_BADDR_T; + +typedef struct dpp_dtb_ddos_cfg_ddos_odd_hash_table_baddr_t +{ + ZXIC_UINT32 cfg_ddos_odd_hash_table_baddr; +}DPP_DTB_DDOS_CFG_DDOS_ODD_HASH_TABLE_BADDR_T; + +typedef struct dpp_dtb_ddos_cfg_ddos_stat_index_offset_t +{ + ZXIC_UINT32 cfg_ddos_stat_index_offset; +}DPP_DTB_DDOS_CFG_DDOS_STAT_INDEX_OFFSET_T; + +typedef struct dpp_dtb_ddos_cfg_ddos_ns_flag_cnt_t +{ + ZXIC_UINT32 cfg_ddos_ns_flag_cnt; +}DPP_DTB_DDOS_CFG_DDOS_NS_FLAG_CNT_T; + +typedef struct dpp_dtb_ddos_cfg_ddos_even_stat_table_baddr_t +{ + ZXIC_UINT32 cfg_ddos_even_stat_table_baddr; +}DPP_DTB_DDOS_CFG_DDOS_EVEN_STAT_TABLE_BADDR_T; + +typedef struct dpp_dtb_ddos_cfg_ddos_odd_stat_table_baddr_t +{ + ZXIC_UINT32 cfg_ddos_odd_stat_table_baddr; +}DPP_DTB_DDOS_CFG_DDOS_ODD_STAT_TABLE_BADDR_T; + +typedef struct dpp_dtb_ddos_cfg_ddos_even_stat_dump_daddr_h_t +{ + ZXIC_UINT32 cfg_ddos_even_stat_dump_daddr_h; +}DPP_DTB_DDOS_CFG_DDOS_EVEN_STAT_DUMP_DADDR_H_T; + +typedef struct dpp_dtb_ddos_cfg_ddos_even_stat_dump_daddr_l_t +{ + ZXIC_UINT32 cfg_ddos_even_stat_dump_daddr_l; +}DPP_DTB_DDOS_CFG_DDOS_EVEN_STAT_DUMP_DADDR_L_T; + +typedef struct dpp_dtb_ddos_cfg_ddos_odd_stat_dump_daddr_h_t +{ + ZXIC_UINT32 cfg_ddos_odd_stat_dump_daddr_h; +}DPP_DTB_DDOS_CFG_DDOS_ODD_STAT_DUMP_DADDR_H_T; + +typedef struct dpp_dtb_ddos_cfg_ddos_odd_stat_dump_daddr_l_t +{ + ZXIC_UINT32 cfg_ddos_odd_stat_dump_daddr_l; +}DPP_DTB_DDOS_CFG_DDOS_ODD_STAT_DUMP_DADDR_L_T; + +typedef struct dpp_dtb_ddos_cfg_ddos_work_mode_enable_t +{ + ZXIC_UINT32 cfg_ddos_mode_work_enable; +}DPP_DTB_DDOS_CFG_DDOS_WORK_MODE_ENABLE_T; + +typedef struct dpp_dtb_ddos_cfg_ddos_stat_table_len_t +{ + ZXIC_UINT32 cfg_ddos_stat_table_len; +}DPP_DTB_DDOS_CFG_DDOS_STAT_TABLE_LEN_T; + +typedef struct dpp_dtb_ddos_cfg_ddos_hash_table_len_t +{ + ZXIC_UINT32 cfg_ddos_hash_table_len; +}DPP_DTB_DDOS_CFG_DDOS_HASH_TABLE_LEN_T; + +typedef struct dpp_dtb_dtb_ram_traf_ctrl_ram0_0_255_t +{ + ZXIC_UINT32 traf_ctrl_ram0_0_255; +}DPP_DTB_DTB_RAM_TRAF_CTRL_RAM0_0_255_T; + +typedef struct dpp_dtb_dtb_ram_traf_ctrl_ram1_0_255_t +{ + ZXIC_UINT32 traf_ctrl_ram1_0_255; +}DPP_DTB_DTB_RAM_TRAF_CTRL_RAM1_0_255_T; + +typedef struct dpp_dtb_dtb_ram_traf_ctrl_ram2_0_255_t +{ + ZXIC_UINT32 traf_ctrl_ram2_0_255; +}DPP_DTB_DTB_RAM_TRAF_CTRL_RAM2_0_255_T; + +typedef struct dpp_dtb_dtb_ram_traf_ctrl_ram3_0_255_t +{ + ZXIC_UINT32 traf_ctrl_ram3_0_255; +}DPP_DTB_DTB_RAM_TRAF_CTRL_RAM3_0_255_T; + +typedef struct dpp_dtb_dtb_ram_traf_ctrl_ram4_0_255_t +{ + ZXIC_UINT32 traf_ctrl_ram4_0_255; +}DPP_DTB_DTB_RAM_TRAF_CTRL_RAM4_0_255_T; + +typedef struct dpp_dtb_dtb_ram_traf_ctrl_ram5_0_63_t +{ + ZXIC_UINT32 traf_ctrl_ram5_0_63; +}DPP_DTB_DTB_RAM_TRAF_CTRL_RAM5_0_63_T; + +typedef struct dpp_dtb_dtb_ram_dump_pd_ram_0_2047_t +{ + ZXIC_UINT32 dump_pd_ram_0_2047; +}DPP_DTB_DTB_RAM_DUMP_PD_RAM_0_2047_T; + +typedef struct dpp_dtb_dtb_ram_rd_ctrl_ram_0_4095_t +{ + ZXIC_UINT32 rd_ctrl_ram_0_4095; +}DPP_DTB_DTB_RAM_RD_CTRL_RAM_0_4095_T; + +typedef struct dpp_dtb_dtb_ram_rd_table_ram_0_8191_t +{ + ZXIC_UINT32 rd_table_ram_0_8191; +}DPP_DTB_DTB_RAM_RD_TABLE_RAM_0_8191_T; + +typedef struct dpp_dtb_dtb_ram_dtb_cmd_man_ram_0_16383_t +{ + ZXIC_UINT32 dtb_cmd_man_ram_0_16383; +}DPP_DTB_DTB_RAM_DTB_CMD_MAN_RAM_0_16383_T; + + +#ifdef __cplusplus +} +#endif +#endif + diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_etm_reg.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_etm_reg.h new file mode 100644 index 0000000..60d7491 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_etm_reg.h @@ -0,0 +1,4926 @@ + +#ifndef _DPP_ETM_REG_H_ +#define _DPP_ETM_REG_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +typedef struct dpp_etm_cfgmt_cpu_check_reg_t +{ + ZXIC_UINT32 cpu_check_reg; +}DPP_ETM_CFGMT_CPU_CHECK_REG_T; + +typedef struct dpp_etm_cfgmt_cfgmt_blksize_t +{ + ZXIC_UINT32 cfgmt_blksize; +}DPP_ETM_CFGMT_CFGMT_BLKSIZE_T; + +typedef struct dpp_etm_cfgmt_reg_int_state_reg_t +{ + ZXIC_UINT32 shap_int; + ZXIC_UINT32 crdt_int; + ZXIC_UINT32 mmu_int; + ZXIC_UINT32 qmu_int; + ZXIC_UINT32 cgavd_int; + ZXIC_UINT32 olif_int; + ZXIC_UINT32 cfgmt_int_buf; +}DPP_ETM_CFGMT_REG_INT_STATE_REG_T; + +typedef struct dpp_etm_cfgmt_reg_int_mask_reg_t +{ + ZXIC_UINT32 shap_int_mask; + ZXIC_UINT32 crdt_int_mask; + ZXIC_UINT32 tmmu_int_mask; + ZXIC_UINT32 qmu_int_mask; + ZXIC_UINT32 cgavd_int_mask; + ZXIC_UINT32 olif_int_mask; + ZXIC_UINT32 cfgmt_int_buf_mask; +}DPP_ETM_CFGMT_REG_INT_MASK_REG_T; + +typedef struct dpp_etm_cfgmt_timeout_limit_t +{ + ZXIC_UINT32 timeout_limit; +}DPP_ETM_CFGMT_TIMEOUT_LIMIT_T; + +typedef struct dpp_etm_cfgmt_subsystem_rdy_reg_t +{ + ZXIC_UINT32 olif_rdy; + ZXIC_UINT32 qmu_rdy; + ZXIC_UINT32 cgavd_rdy; + ZXIC_UINT32 tmmu_rdy; + ZXIC_UINT32 shap_rdy; + ZXIC_UINT32 crdt_rdy; +}DPP_ETM_CFGMT_SUBSYSTEM_RDY_REG_T; + +typedef struct dpp_etm_cfgmt_subsystem_en_reg_t +{ + ZXIC_UINT32 subsystem_en_buf_31_28; + ZXIC_UINT32 subsystem_en_buf_25_0; +}DPP_ETM_CFGMT_SUBSYSTEM_EN_REG_T; + +typedef struct dpp_etm_cfgmt_cfgmt_int_reg_t +{ + ZXIC_UINT32 cfgmt_int_buf; +}DPP_ETM_CFGMT_CFGMT_INT_REG_T; + +typedef struct dpp_etm_cfgmt_qmu_work_mode_t +{ + ZXIC_UINT32 qmu_work_mode; +}DPP_ETM_CFGMT_QMU_WORK_MODE_T; + +typedef struct dpp_etm_cfgmt_cfgmt_ddr_attach_t +{ + ZXIC_UINT32 cfgmt_ddr_attach; +}DPP_ETM_CFGMT_CFGMT_DDR_ATTACH_T; + +typedef struct dpp_etm_cfgmt_cnt_mode_reg_t +{ + ZXIC_UINT32 cfgmt_fc_count_mode; + ZXIC_UINT32 cfgmt_count_rd_mode; + ZXIC_UINT32 cfgmt_count_overflow_mode; +}DPP_ETM_CFGMT_CNT_MODE_REG_T; + +typedef struct dpp_etm_cfgmt_clkgate_en_t +{ + ZXIC_UINT32 clkgate_en; +}DPP_ETM_CFGMT_CLKGATE_EN_T; + +typedef struct dpp_etm_cfgmt_softrst_en_t +{ + ZXIC_UINT32 softrst_en; +}DPP_ETM_CFGMT_SOFTRST_EN_T; + +typedef struct dpp_etm_olif_imem_prog_full_t +{ + ZXIC_UINT32 imem_prog_full_assert; + ZXIC_UINT32 imem_prog_full_negate; +}DPP_ETM_OLIF_IMEM_PROG_FULL_T; + +typedef struct dpp_etm_olif_qmu_para_prog_full_t +{ + ZXIC_UINT32 qmu_para_prog_full_assert; + ZXIC_UINT32 qmu_para_prog_full_negate; +}DPP_ETM_OLIF_QMU_PARA_PROG_FULL_T; + +typedef struct dpp_etm_olif_olif_int_mask_t +{ + ZXIC_UINT32 emem_dat_sop_err_mask; + ZXIC_UINT32 emem_dat_eop_err_mask; + ZXIC_UINT32 imem_dat_sop_err_mask; + ZXIC_UINT32 imem_dat_eop_err_mask; + ZXIC_UINT32 crcram_parity_err_mask; + ZXIC_UINT32 emem_fifo_ecc_mask; + ZXIC_UINT32 imem_fifo_ecc_mask; + ZXIC_UINT32 emem_fifo_ovf_mask; + ZXIC_UINT32 emem_fifo_udf_mask; + ZXIC_UINT32 imem_fifo_ovf_mask; + ZXIC_UINT32 imem_fifo_udf_mask; + ZXIC_UINT32 para_fifo_ecc_mask; + ZXIC_UINT32 para_fifo_ovf_mask; + ZXIC_UINT32 para_fifo_udf_mask; + ZXIC_UINT32 itmh_ecc_single_err_mask; + ZXIC_UINT32 itmh_ecc_double_err_mask; + ZXIC_UINT32 order_fifo_parity_err_mask; + ZXIC_UINT32 order_fifo_ovf_mask; + ZXIC_UINT32 order_fifo_udf_mask; +}DPP_ETM_OLIF_OLIF_INT_MASK_T; + +typedef struct dpp_etm_olif_itmhram_parity_err_2_int_t +{ + ZXIC_UINT32 emem_dat_sop_err; + ZXIC_UINT32 emem_dat_eop_err; + ZXIC_UINT32 imem_dat_sop_err; + ZXIC_UINT32 imem_dat_eop_err; + ZXIC_UINT32 crcram_parity_err_1_int; + ZXIC_UINT32 emem_fifo_ecc_single_err_int; + ZXIC_UINT32 emem_fifo_ecc_double_err_int; + ZXIC_UINT32 imem_fifo_ecc_single_err_int; + ZXIC_UINT32 imem_fifo_ecc_double_err_int; + ZXIC_UINT32 emem_fifo_ovf_int; + ZXIC_UINT32 emem_fifo_udf_int; + ZXIC_UINT32 imem_fifo_ovf_int; + ZXIC_UINT32 imem_fifo_udf_int; + ZXIC_UINT32 para_fifo_ecc_single_err_int; + ZXIC_UINT32 para_fifo_ecc_double_err_int; + ZXIC_UINT32 para_fifo_ovf_int; + ZXIC_UINT32 para_fifo_udf_int; + ZXIC_UINT32 itmh_ecc_single_err_int; + ZXIC_UINT32 itmh_ecc_double_err_int; + ZXIC_UINT32 order_fifo_parity_err_int; + ZXIC_UINT32 order_fifo_ovf_int; + ZXIC_UINT32 order_fifo_udf_int; +}DPP_ETM_OLIF_ITMHRAM_PARITY_ERR_2_INT_T; + +typedef struct dpp_etm_olif_lif0_port_rdy_mask_h_t +{ + ZXIC_UINT32 lif0_port_rdy_mask_h; +}DPP_ETM_OLIF_LIF0_PORT_RDY_MASK_H_T; + +typedef struct dpp_etm_olif_lif0_port_rdy_mask_l_t +{ + ZXIC_UINT32 lif0_port_rdy_mask_l; +}DPP_ETM_OLIF_LIF0_PORT_RDY_MASK_L_T; + +typedef struct dpp_etm_olif_lif0_port_rdy_cfg_h_t +{ + ZXIC_UINT32 lif0_port_rdy_cfg_h; +}DPP_ETM_OLIF_LIF0_PORT_RDY_CFG_H_T; + +typedef struct dpp_etm_olif_lif0_port_rdy_cfg_l_t +{ + ZXIC_UINT32 lif0_port_rdy_cfg_l; +}DPP_ETM_OLIF_LIF0_PORT_RDY_CFG_L_T; + +typedef struct dpp_etm_olif_lif0_link_rdy_mask_cfg_t +{ + ZXIC_UINT32 lif0_link_rdy_mask; + ZXIC_UINT32 lif0_link_rdy_cfg; +}DPP_ETM_OLIF_LIF0_LINK_RDY_MASK_CFG_T; + +typedef struct dpp_etm_olif_tm_lif_stat_cfg_t +{ + ZXIC_UINT32 all_or_by_port; + ZXIC_UINT32 i_or_e_sel; + ZXIC_UINT32 port_or_dest_id_sel; + ZXIC_UINT32 port_dest_id; +}DPP_ETM_OLIF_TM_LIF_STAT_CFG_T; + +typedef struct dpp_etm_olif_tm_lif_sop_stat_t +{ + ZXIC_UINT32 tm_lif_sop_stat; +}DPP_ETM_OLIF_TM_LIF_SOP_STAT_T; + +typedef struct dpp_etm_olif_tm_lif_eop_stat_t +{ + ZXIC_UINT32 tm_lif_eop_stat; +}DPP_ETM_OLIF_TM_LIF_EOP_STAT_T; + +typedef struct dpp_etm_olif_tm_lif_vld_stat_t +{ + ZXIC_UINT32 tm_lif_vld_stat; +}DPP_ETM_OLIF_TM_LIF_VLD_STAT_T; + +typedef struct dpp_etm_cgavd_prog_full_assert_cfg_t +{ + ZXIC_UINT32 prog_full_assert_cfg; + ZXIC_UINT32 prog_full_negate_cfg; +}DPP_ETM_CGAVD_PROG_FULL_ASSERT_CFG_T; + +typedef struct dpp_etm_cgavd_cgavd_int_t +{ + ZXIC_UINT32 cgavd_int; +}DPP_ETM_CGAVD_CGAVD_INT_T; + +typedef struct dpp_etm_cgavd_cgavd_ram_err_t +{ + ZXIC_UINT32 flow_qnum_intb; + ZXIC_UINT32 flow_qnum_inta; + ZXIC_UINT32 pp_qlen_inta; + ZXIC_UINT32 pp_qlen_intb; + ZXIC_UINT32 pp_tdth_int; + ZXIC_UINT32 flow_tdth_inta; + ZXIC_UINT32 flow_tdth_intb; + ZXIC_UINT32 flow_qlen_inta; + ZXIC_UINT32 flow_qlen_intb; + ZXIC_UINT32 qmu_cgavd_fifo_uv_int; + ZXIC_UINT32 qmu_cgavd_fifo_ov_int; + ZXIC_UINT32 pds_deal_fifo_ov_int; + ZXIC_UINT32 pds_deal_fifo_uv_int; +}DPP_ETM_CGAVD_CGAVD_RAM_ERR_T; + +typedef struct dpp_etm_cgavd_cgavd_int_mask_t +{ + ZXIC_UINT32 cgavd_int_mask; +}DPP_ETM_CGAVD_CGAVD_INT_MASK_T; + +typedef struct dpp_etm_cgavd_cgavd_ram_err_int_mask_t +{ + ZXIC_UINT32 flow_qnum_inta_mask; + ZXIC_UINT32 flow_qnum_intb_mask; + ZXIC_UINT32 pp_qlen_inta_mask; + ZXIC_UINT32 pp_qlen_intb_mask; + ZXIC_UINT32 pp_tdth_int_mask; + ZXIC_UINT32 flow_tdth_inta_mask; + ZXIC_UINT32 flow_tdth_intb_mask; + ZXIC_UINT32 flow_qlen_inta_mask; + ZXIC_UINT32 flow_qlen_intb_mask; + ZXIC_UINT32 qmu_cgavd_fifo_uv_int_mask; + ZXIC_UINT32 qmu_cgavd_fifo_ov_int_mask; + ZXIC_UINT32 pds_deal_fifo_ov_int_mask; + ZXIC_UINT32 pds_deal_fifo_uv_int_mask; +}DPP_ETM_CGAVD_CGAVD_RAM_ERR_INT_MASK_T; + +typedef struct dpp_etm_cgavd_cfgmt_byte_mode_t +{ + ZXIC_UINT32 cfgmt_byte_mode; +}DPP_ETM_CGAVD_CFGMT_BYTE_MODE_T; + +typedef struct dpp_etm_cgavd_avg_qlen_return_zero_en_t +{ + ZXIC_UINT32 avg_qlen_return_zero_en; +}DPP_ETM_CGAVD_AVG_QLEN_RETURN_ZERO_EN_T; + +typedef struct dpp_etm_cgavd_flow_wred_q_len_th_t +{ + ZXIC_UINT32 flow_wred_q_len_th; +}DPP_ETM_CGAVD_FLOW_WRED_Q_LEN_TH_T; + +typedef struct dpp_etm_cgavd_flow_wq_t +{ + ZXIC_UINT32 wq_flow; +}DPP_ETM_CGAVD_FLOW_WQ_T; + +typedef struct dpp_etm_cgavd_flow_wred_max_th_t +{ + ZXIC_UINT32 flow_wred_max_th; +}DPP_ETM_CGAVD_FLOW_WRED_MAX_TH_T; + +typedef struct dpp_etm_cgavd_flow_wred_min_th_t +{ + ZXIC_UINT32 flow_wred_min_th; +}DPP_ETM_CGAVD_FLOW_WRED_MIN_TH_T; + +typedef struct dpp_etm_cgavd_flow_wred_cfg_para_t +{ + ZXIC_UINT32 flow_wred_cfg_para; +}DPP_ETM_CGAVD_FLOW_WRED_CFG_PARA_T; + +typedef struct dpp_etm_cgavd_pp_avg_q_len_t +{ + ZXIC_UINT32 pp_avg_q_len; +}DPP_ETM_CGAVD_PP_AVG_Q_LEN_T; + +typedef struct dpp_etm_cgavd_pp_td_th_t +{ + ZXIC_UINT32 pp_td_th; +}DPP_ETM_CGAVD_PP_TD_TH_T; + +typedef struct dpp_etm_cgavd_pp_ca_mtd_t +{ + ZXIC_UINT32 pp_ca_mtd; +}DPP_ETM_CGAVD_PP_CA_MTD_T; + +typedef struct dpp_etm_cgavd_pp_wred_grp_th_en_t +{ + ZXIC_UINT32 pp_wred_grp; + ZXIC_UINT32 pp_wred_grp_th_en; +}DPP_ETM_CGAVD_PP_WRED_GRP_TH_EN_T; + +typedef struct dpp_etm_cgavd_pp_wred_q_len_th_t +{ + ZXIC_UINT32 pp_wred_q_len_th; +}DPP_ETM_CGAVD_PP_WRED_Q_LEN_TH_T; + +typedef struct dpp_etm_cgavd_pp_wq_t +{ + ZXIC_UINT32 wq_pp; +}DPP_ETM_CGAVD_PP_WQ_T; + +typedef struct dpp_etm_cgavd_pp_wred_max_th_t +{ + ZXIC_UINT32 pp_wred_max_th; +}DPP_ETM_CGAVD_PP_WRED_MAX_TH_T; + +typedef struct dpp_etm_cgavd_pp_wred_min_th_t +{ + ZXIC_UINT32 pp_wred_min_th; +}DPP_ETM_CGAVD_PP_WRED_MIN_TH_T; + +typedef struct dpp_etm_cgavd_pp_cfg_para_t +{ + ZXIC_UINT32 pp_cfg_para; +}DPP_ETM_CGAVD_PP_CFG_PARA_T; + +typedef struct dpp_etm_cgavd_sys_avg_q_len_t +{ + ZXIC_UINT32 sys_avg_q_len; +}DPP_ETM_CGAVD_SYS_AVG_Q_LEN_T; + +typedef struct dpp_etm_cgavd_sys_td_th_t +{ + ZXIC_UINT32 sys_td_th; +}DPP_ETM_CGAVD_SYS_TD_TH_T; + +typedef struct dpp_etm_cgavd_sys_cgavd_metd_t +{ + ZXIC_UINT32 sys_cgavd_metd; +}DPP_ETM_CGAVD_SYS_CGAVD_METD_T; + +typedef struct dpp_etm_cgavd_sys_cfg_q_grp_para_t +{ + ZXIC_UINT32 gred_q_len_th_sys; +}DPP_ETM_CGAVD_SYS_CFG_Q_GRP_PARA_T; + +typedef struct dpp_etm_cgavd_sys_wq_t +{ + ZXIC_UINT32 wq_sys; +}DPP_ETM_CGAVD_SYS_WQ_T; + +typedef struct dpp_etm_cgavd_gred_max_th_t +{ + ZXIC_UINT32 gred_max_th; +}DPP_ETM_CGAVD_GRED_MAX_TH_T; + +typedef struct dpp_etm_cgavd_gred_mid_th_t +{ + ZXIC_UINT32 gred_mid_th; +}DPP_ETM_CGAVD_GRED_MID_TH_T; + +typedef struct dpp_etm_cgavd_gred_min_th_t +{ + ZXIC_UINT32 gred_min_th; +}DPP_ETM_CGAVD_GRED_MIN_TH_T; + +typedef struct dpp_etm_cgavd_gred_cfg_para0_t +{ + ZXIC_UINT32 gred_cfg_para0; +}DPP_ETM_CGAVD_GRED_CFG_PARA0_T; + +typedef struct dpp_etm_cgavd_gred_cfg_para1_t +{ + ZXIC_UINT32 gred_cfg_para1; +}DPP_ETM_CGAVD_GRED_CFG_PARA1_T; + +typedef struct dpp_etm_cgavd_gred_cfg_para2_t +{ + ZXIC_UINT32 gred_cfg_para2; +}DPP_ETM_CGAVD_GRED_CFG_PARA2_T; + +typedef struct dpp_etm_cgavd_sys_window_th_h_t +{ + ZXIC_UINT32 sys_window_th_h; +}DPP_ETM_CGAVD_SYS_WINDOW_TH_H_T; + +typedef struct dpp_etm_cgavd_sys_window_th_l_t +{ + ZXIC_UINT32 sys_window_th_l; +}DPP_ETM_CGAVD_SYS_WINDOW_TH_L_T; + +typedef struct dpp_etm_cgavd_amplify_gene0_t +{ + ZXIC_UINT32 amplify_gene0; +}DPP_ETM_CGAVD_AMPLIFY_GENE0_T; + +typedef struct dpp_etm_cgavd_amplify_gene1_t +{ + ZXIC_UINT32 amplify_gene1; +}DPP_ETM_CGAVD_AMPLIFY_GENE1_T; + +typedef struct dpp_etm_cgavd_amplify_gene2_t +{ + ZXIC_UINT32 amplify_gene2; +}DPP_ETM_CGAVD_AMPLIFY_GENE2_T; + +typedef struct dpp_etm_cgavd_amplify_gene3_t +{ + ZXIC_UINT32 amplify_gene3; +}DPP_ETM_CGAVD_AMPLIFY_GENE3_T; + +typedef struct dpp_etm_cgavd_amplify_gene4_t +{ + ZXIC_UINT32 amplify_gene4; +}DPP_ETM_CGAVD_AMPLIFY_GENE4_T; + +typedef struct dpp_etm_cgavd_amplify_gene5_t +{ + ZXIC_UINT32 amplify_gene5; +}DPP_ETM_CGAVD_AMPLIFY_GENE5_T; + +typedef struct dpp_etm_cgavd_amplify_gene6_t +{ + ZXIC_UINT32 amplify_gene6; +}DPP_ETM_CGAVD_AMPLIFY_GENE6_T; + +typedef struct dpp_etm_cgavd_amplify_gene7_t +{ + ZXIC_UINT32 amplify_gene7; +}DPP_ETM_CGAVD_AMPLIFY_GENE7_T; + +typedef struct dpp_etm_cgavd_amplify_gene8_t +{ + ZXIC_UINT32 amplify_gene8; +}DPP_ETM_CGAVD_AMPLIFY_GENE8_T; + +typedef struct dpp_etm_cgavd_amplify_gene9_t +{ + ZXIC_UINT32 amplify_gene9; +}DPP_ETM_CGAVD_AMPLIFY_GENE9_T; + +typedef struct dpp_etm_cgavd_amplify_gene10_t +{ + ZXIC_UINT32 amplify_gene10; +}DPP_ETM_CGAVD_AMPLIFY_GENE10_T; + +typedef struct dpp_etm_cgavd_amplify_gene11_t +{ + ZXIC_UINT32 amplify_gene11; +}DPP_ETM_CGAVD_AMPLIFY_GENE11_T; + +typedef struct dpp_etm_cgavd_amplify_gene12_t +{ + ZXIC_UINT32 amplify_gene12; +}DPP_ETM_CGAVD_AMPLIFY_GENE12_T; + +typedef struct dpp_etm_cgavd_amplify_gene13_t +{ + ZXIC_UINT32 amplify_gene13; +}DPP_ETM_CGAVD_AMPLIFY_GENE13_T; + +typedef struct dpp_etm_cgavd_amplify_gene14_t +{ + ZXIC_UINT32 amplify_gene14; +}DPP_ETM_CGAVD_AMPLIFY_GENE14_T; + +typedef struct dpp_etm_cgavd_amplify_gene15_t +{ + ZXIC_UINT32 amplify_gene15; +}DPP_ETM_CGAVD_AMPLIFY_GENE15_T; + +typedef struct dpp_etm_cgavd_equal_pkt_len_en_t +{ + ZXIC_UINT32 equal_pkt_len_en; +}DPP_ETM_CGAVD_EQUAL_PKT_LEN_EN_T; + +typedef struct dpp_etm_cgavd_equal_pkt_len_th0_t +{ + ZXIC_UINT32 equal_pkt_len_th0; +}DPP_ETM_CGAVD_EQUAL_PKT_LEN_TH0_T; + +typedef struct dpp_etm_cgavd_equal_pkt_len_th1_t +{ + ZXIC_UINT32 equal_pkt_len_th1; +}DPP_ETM_CGAVD_EQUAL_PKT_LEN_TH1_T; + +typedef struct dpp_etm_cgavd_equal_pkt_len_th2_t +{ + ZXIC_UINT32 equal_pkt_len_th2; +}DPP_ETM_CGAVD_EQUAL_PKT_LEN_TH2_T; + +typedef struct dpp_etm_cgavd_equal_pkt_len_th3_t +{ + ZXIC_UINT32 equal_pkt_len_th3; +}DPP_ETM_CGAVD_EQUAL_PKT_LEN_TH3_T; + +typedef struct dpp_etm_cgavd_equal_pkt_len_th4_t +{ + ZXIC_UINT32 equal_pkt_len_th4; +}DPP_ETM_CGAVD_EQUAL_PKT_LEN_TH4_T; + +typedef struct dpp_etm_cgavd_equal_pkt_len_th5_t +{ + ZXIC_UINT32 equal_pkt_len_th5; +}DPP_ETM_CGAVD_EQUAL_PKT_LEN_TH5_T; + +typedef struct dpp_etm_cgavd_equal_pkt_len_th6_t +{ + ZXIC_UINT32 equal_pkt_len_th6; +}DPP_ETM_CGAVD_EQUAL_PKT_LEN_TH6_T; + +typedef struct dpp_etm_cgavd_equal_pkt_len0_t +{ + ZXIC_UINT32 equal_pkt_len0; +}DPP_ETM_CGAVD_EQUAL_PKT_LEN0_T; + +typedef struct dpp_etm_cgavd_equal_pkt_len1_t +{ + ZXIC_UINT32 equal_pkt_len1; +}DPP_ETM_CGAVD_EQUAL_PKT_LEN1_T; + +typedef struct dpp_etm_cgavd_equal_pkt_len2_t +{ + ZXIC_UINT32 equal_pkt_len2; +}DPP_ETM_CGAVD_EQUAL_PKT_LEN2_T; + +typedef struct dpp_etm_cgavd_equal_pkt_len3_t +{ + ZXIC_UINT32 equal_pkt_len3; +}DPP_ETM_CGAVD_EQUAL_PKT_LEN3_T; + +typedef struct dpp_etm_cgavd_equal_pkt_len4_t +{ + ZXIC_UINT32 equal_pkt_len4; +}DPP_ETM_CGAVD_EQUAL_PKT_LEN4_T; + +typedef struct dpp_etm_cgavd_equal_pkt_len5_t +{ + ZXIC_UINT32 equal_pkt_len5; +}DPP_ETM_CGAVD_EQUAL_PKT_LEN5_T; + +typedef struct dpp_etm_cgavd_equal_pkt_len6_t +{ + ZXIC_UINT32 equal_pkt_len6; +}DPP_ETM_CGAVD_EQUAL_PKT_LEN6_T; + +typedef struct dpp_etm_cgavd_equal_pkt_len7_t +{ + ZXIC_UINT32 equal_pkt_len7; +}DPP_ETM_CGAVD_EQUAL_PKT_LEN7_T; + +typedef struct dpp_etm_cgavd_flow_cpu_set_avg_len_t +{ + ZXIC_UINT32 flow_cpu_set_avg_len; +}DPP_ETM_CGAVD_FLOW_CPU_SET_AVG_LEN_T; + +typedef struct dpp_etm_cgavd_flow_cpu_set_q_len_t +{ + ZXIC_UINT32 flow_cpu_set_q_len; +}DPP_ETM_CGAVD_FLOW_CPU_SET_Q_LEN_T; + +typedef struct dpp_etm_cgavd_pp_cpu_set_avg_q_len_t +{ + ZXIC_UINT32 pp_cpu_set_avg_q_len; +}DPP_ETM_CGAVD_PP_CPU_SET_AVG_Q_LEN_T; + +typedef struct dpp_etm_cgavd_pp_cpu_set_q_len_t +{ + ZXIC_UINT32 pp_cpu_set_q_len; +}DPP_ETM_CGAVD_PP_CPU_SET_Q_LEN_T; + +typedef struct dpp_etm_cgavd_sys_cpu_set_avg_len_t +{ + ZXIC_UINT32 sys_cpu_set_avg_len; +}DPP_ETM_CGAVD_SYS_CPU_SET_AVG_LEN_T; + +typedef struct dpp_etm_cgavd_sys_cpu_set_q_len_t +{ + ZXIC_UINT32 sys_cpu_set_q_len; +}DPP_ETM_CGAVD_SYS_CPU_SET_Q_LEN_T; + +typedef struct dpp_etm_cgavd_pke_len_calc_sign_t +{ + ZXIC_UINT32 pke_len_calc_sign; +}DPP_ETM_CGAVD_PKE_LEN_CALC_SIGN_T; + +typedef struct dpp_etm_cgavd_rd_cpu_or_ram_t +{ + ZXIC_UINT32 cpu_sel_sys_q_len_en; + ZXIC_UINT32 cpu_sel_sys_avg_q_len_en; + ZXIC_UINT32 cpu_sel_pp_q_len_en; + ZXIC_UINT32 cpu_sel_pp_avg_q_len_en; + ZXIC_UINT32 cpu_sel_flow_q_len_en; + ZXIC_UINT32 cpu_sel_flow_avg_q_len_en; +}DPP_ETM_CGAVD_RD_CPU_OR_RAM_T; + +typedef struct dpp_etm_cgavd_q_len_update_disable_t +{ + ZXIC_UINT32 q_len_sys_update_en; + ZXIC_UINT32 q_len_pp_update_en; + ZXIC_UINT32 q_len_flow_update_en; +}DPP_ETM_CGAVD_Q_LEN_UPDATE_DISABLE_T; + +typedef struct dpp_etm_cgavd_cgavd_dp_sel_t +{ + ZXIC_UINT32 flow_dp_sel_high; + ZXIC_UINT32 flow_dp_sel_mid; + ZXIC_UINT32 flow_dp_sel_low; + ZXIC_UINT32 pp_dp_sel_high; + ZXIC_UINT32 pp_dp_sel_mid; + ZXIC_UINT32 pp_dp_sel_low; + ZXIC_UINT32 sys_dp_sel_high; + ZXIC_UINT32 sys_dp_sel_mid; + ZXIC_UINT32 sys_dp_sel_low; +}DPP_ETM_CGAVD_CGAVD_DP_SEL_T; + +typedef struct dpp_etm_cgavd_cgavd_sub_en_t +{ + ZXIC_UINT32 cgavd_sa_sub_en; + ZXIC_UINT32 cgavd_sys_sub_en; + ZXIC_UINT32 cgavd_pp_sub_en; + ZXIC_UINT32 cgavd_flow_sub_en; +}DPP_ETM_CGAVD_CGAVD_SUB_EN_T; + +typedef struct dpp_etm_cgavd_default_start_queue_t +{ + ZXIC_UINT32 default_start_queue; +}DPP_ETM_CGAVD_DEFAULT_START_QUEUE_T; + +typedef struct dpp_etm_cgavd_default_finish_queue_t +{ + ZXIC_UINT32 default_finish_queue; +}DPP_ETM_CGAVD_DEFAULT_FINISH_QUEUE_T; + +typedef struct dpp_etm_cgavd_protocol_start_queue_t +{ + ZXIC_UINT32 protocol_start_queue; +}DPP_ETM_CGAVD_PROTOCOL_START_QUEUE_T; + +typedef struct dpp_etm_cgavd_protocol_finish_queue_t +{ + ZXIC_UINT32 protocol_finish_queue; +}DPP_ETM_CGAVD_PROTOCOL_FINISH_QUEUE_T; + +typedef struct dpp_etm_cgavd_uniform_td_th_t +{ + ZXIC_UINT32 uniform_td_th; +}DPP_ETM_CGAVD_UNIFORM_TD_TH_T; + +typedef struct dpp_etm_cgavd_uniform_td_th_en_t +{ + ZXIC_UINT32 uniform_td_th_en; +}DPP_ETM_CGAVD_UNIFORM_TD_TH_EN_T; + +typedef struct dpp_etm_cgavd_cgavd_cfg_fc_t +{ + ZXIC_UINT32 cgavd_cfg_fc; +}DPP_ETM_CGAVD_CGAVD_CFG_FC_T; + +typedef struct dpp_etm_cgavd_cgavd_cfg_no_fc_t +{ + ZXIC_UINT32 cgavd_cfg_no_fc; +}DPP_ETM_CGAVD_CGAVD_CFG_NO_FC_T; + +typedef struct dpp_etm_cgavd_cgavd_force_imem_omem_t +{ + ZXIC_UINT32 imem_omem_force_en; + ZXIC_UINT32 choose_imem_omem; +}DPP_ETM_CGAVD_CGAVD_FORCE_IMEM_OMEM_T; + +typedef struct dpp_etm_cgavd_cgavd_sys_q_len_l_t +{ + ZXIC_UINT32 cgavd_sys_q_len_l; +}DPP_ETM_CGAVD_CGAVD_SYS_Q_LEN_L_T; + +typedef struct dpp_etm_cgavd_default_queue_en_t +{ + ZXIC_UINT32 default_queue_en; +}DPP_ETM_CGAVD_DEFAULT_QUEUE_EN_T; + +typedef struct dpp_etm_cgavd_protocol_queue_en_t +{ + ZXIC_UINT32 protocol_queue_en; +}DPP_ETM_CGAVD_PROTOCOL_QUEUE_EN_T; + +typedef struct dpp_etm_cgavd_cfg_tc_flowid_dat_t +{ + ZXIC_UINT32 cfg_tc_flowid_dat; +}DPP_ETM_CGAVD_CFG_TC_FLOWID_DAT_T; + +typedef struct dpp_etm_cgavd_flow_td_th_t +{ + ZXIC_UINT32 flow_td_th; +}DPP_ETM_CGAVD_FLOW_TD_TH_T; + +typedef struct dpp_etm_cgavd_flow_ca_mtd_t +{ + ZXIC_UINT32 flow_ca_mtd; +}DPP_ETM_CGAVD_FLOW_CA_MTD_T; + +typedef struct dpp_etm_cgavd_flow_dynamic_th_en_t +{ + ZXIC_UINT32 flow_dynamic_th_en; +}DPP_ETM_CGAVD_FLOW_DYNAMIC_TH_EN_T; + +typedef struct dpp_etm_cgavd_pp_num_t +{ + ZXIC_UINT32 pp_num; +}DPP_ETM_CGAVD_PP_NUM_T; + +typedef struct dpp_etm_cgavd_flow_q_len_t +{ + ZXIC_UINT32 flow_q_len; +}DPP_ETM_CGAVD_FLOW_Q_LEN_T; + +typedef struct dpp_etm_cgavd_flow_wred_grp_t +{ + ZXIC_UINT32 flow_wred_grp; +}DPP_ETM_CGAVD_FLOW_WRED_GRP_T; + +typedef struct dpp_etm_cgavd_flow_avg_q_len_t +{ + ZXIC_UINT32 flow_avg_q_len; +}DPP_ETM_CGAVD_FLOW_AVG_Q_LEN_T; + +typedef struct dpp_etm_cgavd_qos_sign_t +{ + ZXIC_UINT32 qos_sign_flow_cfg_din; +}DPP_ETM_CGAVD_QOS_SIGN_T; + +typedef struct dpp_etm_cgavd_q_pri_t +{ + ZXIC_UINT32 qpri_flow_cfg_din; +}DPP_ETM_CGAVD_Q_PRI_T; + +typedef struct dpp_etm_cgavd_odma_tm_itmd_rd_low_t +{ + ZXIC_UINT32 odma_tm_itmd_low; +}DPP_ETM_CGAVD_ODMA_TM_ITMD_RD_LOW_T; + +typedef struct dpp_etm_cgavd_odma_tm_itmd_rd_mid_t +{ + ZXIC_UINT32 odma_tm_itmd_mid; +}DPP_ETM_CGAVD_ODMA_TM_ITMD_RD_MID_T; + +typedef struct dpp_etm_cgavd_odma_tm_itmd_rd_high_t +{ + ZXIC_UINT32 odma_tm_itmd_high; +}DPP_ETM_CGAVD_ODMA_TM_ITMD_RD_HIGH_T; + +typedef struct dpp_etm_cgavd_cgavd_stat_pkt_len_t +{ + ZXIC_UINT32 expect_deq_pkt_len; + ZXIC_UINT32 expect_enq_pkt_len; +}DPP_ETM_CGAVD_CGAVD_STAT_PKT_LEN_T; + +typedef struct dpp_etm_cgavd_cgavd_stat_qnum_t +{ + ZXIC_UINT32 cgavd_unexcept_qnum; + ZXIC_UINT32 cgavd_except_qnum; +}DPP_ETM_CGAVD_CGAVD_STAT_QNUM_T; + +typedef struct dpp_etm_cgavd_cgavd_stat_dp_t +{ + ZXIC_UINT32 cgavd_stat_dp; +}DPP_ETM_CGAVD_CGAVD_STAT_DP_T; + +typedef struct dpp_etm_cgavd_flow_num0_t +{ + ZXIC_UINT32 flow_num0; +}DPP_ETM_CGAVD_FLOW_NUM0_T; + +typedef struct dpp_etm_cgavd_flow_num1_t +{ + ZXIC_UINT32 flow_num1; +}DPP_ETM_CGAVD_FLOW_NUM1_T; + +typedef struct dpp_etm_cgavd_flow_num2_t +{ + ZXIC_UINT32 flow_num2; +}DPP_ETM_CGAVD_FLOW_NUM2_T; + +typedef struct dpp_etm_cgavd_flow_num3_t +{ + ZXIC_UINT32 flow_num3; +}DPP_ETM_CGAVD_FLOW_NUM3_T; + +typedef struct dpp_etm_cgavd_flow_num4_t +{ + ZXIC_UINT32 flow_num4; +}DPP_ETM_CGAVD_FLOW_NUM4_T; + +typedef struct dpp_etm_cgavd_flow0_imem_cnt_t +{ + ZXIC_UINT32 flow0_imem_cnt; +}DPP_ETM_CGAVD_FLOW0_IMEM_CNT_T; + +typedef struct dpp_etm_cgavd_flow1_imem_cnt_t +{ + ZXIC_UINT32 flow1_imem_cnt; +}DPP_ETM_CGAVD_FLOW1_IMEM_CNT_T; + +typedef struct dpp_etm_cgavd_flow2_imem_cnt_t +{ + ZXIC_UINT32 flow2_imem_cnt; +}DPP_ETM_CGAVD_FLOW2_IMEM_CNT_T; + +typedef struct dpp_etm_cgavd_flow3_imem_cnt_t +{ + ZXIC_UINT32 flow3_imem_cnt; +}DPP_ETM_CGAVD_FLOW3_IMEM_CNT_T; + +typedef struct dpp_etm_cgavd_flow4_imem_cnt_t +{ + ZXIC_UINT32 flow4_imem_cnt; +}DPP_ETM_CGAVD_FLOW4_IMEM_CNT_T; + +typedef struct dpp_etm_cgavd_flow0_drop_cnt_t +{ + ZXIC_UINT32 flow0_drop_cnt; +}DPP_ETM_CGAVD_FLOW0_DROP_CNT_T; + +typedef struct dpp_etm_cgavd_flow1_drop_cnt_t +{ + ZXIC_UINT32 flow1_drop_cnt; +}DPP_ETM_CGAVD_FLOW1_DROP_CNT_T; + +typedef struct dpp_etm_cgavd_flow2_drop_cnt_t +{ + ZXIC_UINT32 flow2_drop_cnt; +}DPP_ETM_CGAVD_FLOW2_DROP_CNT_T; + +typedef struct dpp_etm_cgavd_flow3_drop_cnt_t +{ + ZXIC_UINT32 flow3_drop_cnt; +}DPP_ETM_CGAVD_FLOW3_DROP_CNT_T; + +typedef struct dpp_etm_cgavd_flow4_drop_cnt_t +{ + ZXIC_UINT32 flow4_drop_cnt; +}DPP_ETM_CGAVD_FLOW4_DROP_CNT_T; + +typedef struct dpp_etm_cgavd_fc_count_mode_t +{ + ZXIC_UINT32 fc_count_mode; +}DPP_ETM_CGAVD_FC_COUNT_MODE_T; + +typedef struct dpp_etm_cgavd_qmu_cgavd_fc_num_t +{ + ZXIC_UINT32 qmu_cgavd_fc_state; + ZXIC_UINT32 qmu_cgavd_fc_num; +}DPP_ETM_CGAVD_QMU_CGAVD_FC_NUM_T; + +typedef struct dpp_etm_cgavd_cgavd_odma_fc_num_t +{ + ZXIC_UINT32 cgavd_lif_fc_state; + ZXIC_UINT32 cgavd_lif_fc_num; +}DPP_ETM_CGAVD_CGAVD_ODMA_FC_NUM_T; + +typedef struct dpp_etm_cgavd_cfg_offset_t +{ + ZXIC_UINT32 cfg_offset; +}DPP_ETM_CGAVD_CFG_OFFSET_T; + +typedef struct dpp_etm_tmmu_tmmu_init_done_t +{ + ZXIC_UINT32 tmmu_init_done; +}DPP_ETM_TMMU_TMMU_INIT_DONE_T; + +typedef struct dpp_etm_tmmu_tmmu_int_mask_1_t +{ + ZXIC_UINT32 imem_enq_rd_fifo_full_mask; + ZXIC_UINT32 imem_enq_rd_fifo_overflow_mask; + ZXIC_UINT32 imem_enq_rd_fifo_underflow_mask; + ZXIC_UINT32 imem_enq_drop_fifo_full_mask; + ZXIC_UINT32 imem_enq_drop_fifo_overflow_mask; + ZXIC_UINT32 imem_enq_drop_fifo_underflow_mask; + ZXIC_UINT32 imem_deq_rd_fifo_full_mask; + ZXIC_UINT32 imem_deq_rd_fifo_overflow_mask; + ZXIC_UINT32 imem_deq_rd_fifo_underflow_mask; + ZXIC_UINT32 imem_deq_drop_fifo_full_mask; + ZXIC_UINT32 imem_deq_drop_fifo_overflow_mask; + ZXIC_UINT32 imem_deq_drop_fifo_underflow_mask; + ZXIC_UINT32 dma_data_fifo_full_mask; + ZXIC_UINT32 dma_data_fifo_overflow_mask; + ZXIC_UINT32 dma_data_fifo_underflow_mask; + ZXIC_UINT32 wr_cmd_fifo_full_mask; + ZXIC_UINT32 wr_cmd_fifo_overflow_mask; + ZXIC_UINT32 wr_cmd_fifo_underflow_mask; + ZXIC_UINT32 cached_pd_fifo_full_mask; + ZXIC_UINT32 cached_pd_fifo_overflow_mask; + ZXIC_UINT32 cached_pd_fifo_underflow_mask; + ZXIC_UINT32 emem_pd_fifo_full_mask; + ZXIC_UINT32 emem_pd_fifo_overflow_mask; + ZXIC_UINT32 emem_pd_fifo_underflow_mask; + ZXIC_UINT32 pd_order_fifo_full_mask; + ZXIC_UINT32 pd_order_fifo_overflow_mask; + ZXIC_UINT32 pd_order_fifo_underflow_mask; +}DPP_ETM_TMMU_TMMU_INT_MASK_1_T; + +typedef struct dpp_etm_tmmu_tmmu_int_mask_2_t +{ + ZXIC_UINT32 dma_data_fifo_parity_err_mask; + ZXIC_UINT32 imem_enq_rd_fifo_ecc_single_err_mask; + ZXIC_UINT32 imem_enq_rd_fifo_ecc_double_err_mask; + ZXIC_UINT32 imem_enq_drop_fifo_ecc_single_err_mask; + ZXIC_UINT32 imem_enq_drop_fifo_ecc_double_err_mask; + ZXIC_UINT32 imem_deq_rd_fifo_ecc_single_err_mask; + ZXIC_UINT32 imem_deq_rd_fifo_ecc_double_err_mask; + ZXIC_UINT32 imem_deq_drop_fifo_ecc_single_err_mask; + ZXIC_UINT32 imem_deq_drop_fifo_ecc_double_err_mask; + ZXIC_UINT32 wr_cmd_fifo_ecc_single_err_mask; + ZXIC_UINT32 wr_cmd_fifo_ecc_double_err_mask; + ZXIC_UINT32 pd_cache_ram_ecc_single_err_mask; + ZXIC_UINT32 pd_cache_ram_ecc_double_err_mask; + ZXIC_UINT32 cached_pd_fifo_ecc_single_err_mask; + ZXIC_UINT32 cached_pd_fifo_ecc_double_err_mask; + ZXIC_UINT32 emem_pd_fifo_ecc_single_err_mask; + ZXIC_UINT32 emem_pd_fifo_ecc_double_err_mask; +}DPP_ETM_TMMU_TMMU_INT_MASK_2_T; + +typedef struct dpp_etm_tmmu_cfgmt_tm_pure_imem_en_t +{ + ZXIC_UINT32 cfgmt_tm_pure_imem_en; +}DPP_ETM_TMMU_CFGMT_TM_PURE_IMEM_EN_T; + +typedef struct dpp_etm_tmmu_cfgmt_force_ddr_rdy_cfg_t +{ + ZXIC_UINT32 cfgmt_force_ddr_rdy_cfg; +}DPP_ETM_TMMU_CFGMT_FORCE_DDR_RDY_CFG_T; + +typedef struct dpp_etm_tmmu_pd_order_fifo_aful_th_t +{ + ZXIC_UINT32 pd_order_fifo_aful_th; +}DPP_ETM_TMMU_PD_ORDER_FIFO_AFUL_TH_T; + +typedef struct dpp_etm_tmmu_cached_pd_fifo_aful_th_t +{ + ZXIC_UINT32 cached_pd_fifo_aful_th; +}DPP_ETM_TMMU_CACHED_PD_FIFO_AFUL_TH_T; + +typedef struct dpp_etm_tmmu_wr_cmd_fifo_aful_th_t +{ + ZXIC_UINT32 wr_cmd_fifo_aful_th; +}DPP_ETM_TMMU_WR_CMD_FIFO_AFUL_TH_T; + +typedef struct dpp_etm_tmmu_imem_enq_rd_fifo_aful_th_t +{ + ZXIC_UINT32 imem_enq_rd_fifo_aful_th; +}DPP_ETM_TMMU_IMEM_ENQ_RD_FIFO_AFUL_TH_T; + +typedef struct dpp_etm_tmmu_imem_enq_drop_fifo_aful_th_t +{ + ZXIC_UINT32 imem_enq_drop_fifo_aful_th; +}DPP_ETM_TMMU_IMEM_ENQ_DROP_FIFO_AFUL_TH_T; + +typedef struct dpp_etm_tmmu_imem_deq_drop_fifo_aful_th_t +{ + ZXIC_UINT32 imem_deq_drop_fifo_aful_th; +}DPP_ETM_TMMU_IMEM_DEQ_DROP_FIFO_AFUL_TH_T; + +typedef struct dpp_etm_tmmu_imem_deq_rd_fifo_aful_th_t +{ + ZXIC_UINT32 imem_deq_rd_fifo_aful_th; +}DPP_ETM_TMMU_IMEM_DEQ_RD_FIFO_AFUL_TH_T; + +typedef struct dpp_etm_tmmu_tmmu_states_1_t +{ + ZXIC_UINT32 imem_enq_rd_fifo_full; + ZXIC_UINT32 imem_enq_rd_fifo_overflow; + ZXIC_UINT32 imem_enq_rd_fifo_underflow; + ZXIC_UINT32 imem_enq_drop_fifo_full; + ZXIC_UINT32 imem_enq_drop_fifo_overflow; + ZXIC_UINT32 imem_enq_drop_fifo_underflow; + ZXIC_UINT32 imem_deq_rd_fifo_full; + ZXIC_UINT32 imem_deq_rd_fifo_overflow; + ZXIC_UINT32 imem_deq_rd_fifo_underflow; + ZXIC_UINT32 imem_deq_drop_fifo_full; + ZXIC_UINT32 imem_deq_drop_fifo_overflow; + ZXIC_UINT32 imem_deq_drop_fifo_underflow; + ZXIC_UINT32 dma_data_fifo_full; + ZXIC_UINT32 dma_data_fifo_overflow; + ZXIC_UINT32 dma_data_fifo_underflow; + ZXIC_UINT32 wr_cmd_fifo_full; + ZXIC_UINT32 wr_cmd_fifo_overflow; + ZXIC_UINT32 wr_cmd_fifo_underflow; + ZXIC_UINT32 cached_pd_fifo_full; + ZXIC_UINT32 cached_pd_fifo_overflow; + ZXIC_UINT32 cached_pd_fifo_underflow; + ZXIC_UINT32 emem_pd_fifo_full; + ZXIC_UINT32 emem_pd_fifo_overflow; + ZXIC_UINT32 emem_pd_fifo_underflow; + ZXIC_UINT32 pd_order_fifo_full; + ZXIC_UINT32 pd_order_fifo_overflow; + ZXIC_UINT32 pd_order_fifo_underflow; +}DPP_ETM_TMMU_TMMU_STATES_1_T; + +typedef struct dpp_etm_tmmu_tmmu_states_2_t +{ + ZXIC_UINT32 dma_data_fifo_parity_err; + ZXIC_UINT32 imem_enq_rd_fifo_ecc_single_err; + ZXIC_UINT32 imem_enq_rd_fifo_ecc_double_err; + ZXIC_UINT32 imem_enq_drop_fifo_ecc_single_err; + ZXIC_UINT32 imem_enq_drop_fifo_ecc_double_err; + ZXIC_UINT32 imem_deq_rd_fifo_ecc_single_err; + ZXIC_UINT32 imem_deq_rd_fifo_ecc_double_err; + ZXIC_UINT32 imem_deq_drop_fifo_ecc_single_err; + ZXIC_UINT32 imem_deq_drop_fifo_ecc_double_err; + ZXIC_UINT32 wr_cmd_fifo_ecc_single_err; + ZXIC_UINT32 wr_cmd_fifo_ecc_double_err; + ZXIC_UINT32 pd_cache_ram_ecc_single_err; + ZXIC_UINT32 pd_cache_ram_ecc_double_err; + ZXIC_UINT32 cached_pd_fifo_ecc_single_err; + ZXIC_UINT32 cached_pd_fifo_ecc_double_err; + ZXIC_UINT32 emem_pd_fifo_ecc_single_err; + ZXIC_UINT32 emem_pd_fifo_ecc_double_err; +}DPP_ETM_TMMU_TMMU_STATES_2_T; + +typedef struct dpp_etm_shap_shap_ind_cmd_t +{ + ZXIC_UINT32 rd; + ZXIC_UINT32 mem_id; + ZXIC_UINT32 addr; +}DPP_ETM_SHAP_SHAP_IND_CMD_T; + +typedef struct dpp_etm_shap_shap_ind_sta_t +{ + ZXIC_UINT32 indirectaccessdone; +}DPP_ETM_SHAP_SHAP_IND_STA_T; + +typedef struct dpp_etm_shap_shap_ind_data0_t +{ + ZXIC_UINT32 indirectdata0; +}DPP_ETM_SHAP_SHAP_IND_DATA0_T; + +typedef struct dpp_etm_shap_shap_ind_data1_t +{ + ZXIC_UINT32 indirectdata1; +}DPP_ETM_SHAP_SHAP_IND_DATA1_T; + +typedef struct dpp_etm_shap_full_threshold_t +{ + ZXIC_UINT32 full_threshold; +}DPP_ETM_SHAP_FULL_THRESHOLD_T; + +typedef struct dpp_etm_shap_empty_threshold_t +{ + ZXIC_UINT32 empty_threshold; +}DPP_ETM_SHAP_EMPTY_THRESHOLD_T; + +typedef struct dpp_etm_shap_shap_sta_init_cfg_t +{ + ZXIC_UINT32 sta_ram_init_done; + ZXIC_UINT32 sta_ram_init_en; +}DPP_ETM_SHAP_SHAP_STA_INIT_CFG_T; + +typedef struct dpp_etm_shap_shap_cfg_init_cfg_t +{ + ZXIC_UINT32 cfg_ram_init_done; + ZXIC_UINT32 cfg_ram_init_en; +}DPP_ETM_SHAP_SHAP_CFG_INIT_CFG_T; + +typedef struct dpp_etm_shap_token_mode_switch_t +{ + ZXIC_UINT32 token_mode_switch; +}DPP_ETM_SHAP_TOKEN_MODE_SWITCH_T; + +typedef struct dpp_etm_shap_token_grain_t +{ + ZXIC_UINT32 token_grain; +}DPP_ETM_SHAP_TOKEN_GRAIN_T; + +typedef struct dpp_etm_shap_crd_grain_t +{ + ZXIC_UINT32 crd_grain; +}DPP_ETM_SHAP_CRD_GRAIN_T; + +typedef struct dpp_etm_shap_shap_stat_ctrl_t +{ + ZXIC_UINT32 shap_stat_ctrl; +}DPP_ETM_SHAP_SHAP_STAT_CTRL_T; + +typedef struct dpp_etm_shap_token_stat_id_t +{ + ZXIC_UINT32 token_stat_id; +}DPP_ETM_SHAP_TOKEN_STAT_ID_T; + +typedef struct dpp_etm_shap_token_stat_t +{ + ZXIC_UINT32 token_stat; +}DPP_ETM_SHAP_TOKEN_STAT_T; + +typedef struct dpp_etm_shap_shap_stat_clk_cnt_t +{ + ZXIC_UINT32 shap_stat_clk_cnt; +}DPP_ETM_SHAP_SHAP_STAT_CLK_CNT_T; + +typedef struct dpp_etm_shap_shap_bucket_map_tbl_t +{ + ZXIC_UINT32 shap_map; +}DPP_ETM_SHAP_SHAP_BUCKET_MAP_TBL_T; + +typedef struct dpp_etm_shap_bkt_para_tbl_t +{ + ZXIC_UINT32 bucket_depth; + ZXIC_UINT32 bucket_rate; +}DPP_ETM_SHAP_BKT_PARA_TBL_T; + +typedef struct dpp_etm_crdt_credit_en_t +{ + ZXIC_UINT32 credit_en; +}DPP_ETM_CRDT_CREDIT_EN_T; + +typedef struct dpp_etm_crdt_crt_inter1_t +{ + ZXIC_UINT32 crd_inter1; +}DPP_ETM_CRDT_CRT_INTER1_T; + +typedef struct dpp_etm_crdt_db_token_t +{ + ZXIC_UINT32 db_token; +}DPP_ETM_CRDT_DB_TOKEN_T; + +typedef struct dpp_etm_crdt_crs_flt_cfg_t +{ + ZXIC_UINT32 crs_flt_cfg; +}DPP_ETM_CRDT_CRS_FLT_CFG_T; + +typedef struct dpp_etm_crdt_th_sp_t +{ + ZXIC_UINT32 th_sp; +}DPP_ETM_CRDT_TH_SP_T; + +typedef struct dpp_etm_crdt_th_wfq_fq_t +{ + ZXIC_UINT32 th_fq; + ZXIC_UINT32 th_wfq; +}DPP_ETM_CRDT_TH_WFQ_FQ_T; + +typedef struct dpp_etm_crdt_th_wfq2_fq2_t +{ + ZXIC_UINT32 th_fq2; + ZXIC_UINT32 th_wfq2; +}DPP_ETM_CRDT_TH_WFQ2_FQ2_T; + +typedef struct dpp_etm_crdt_th_wfq4_fq4_t +{ + ZXIC_UINT32 th_fq4; + ZXIC_UINT32 th_wfq4; +}DPP_ETM_CRDT_TH_WFQ4_FQ4_T; + +typedef struct dpp_etm_crdt_cfg_state_t +{ + ZXIC_UINT32 cfg_state; +}DPP_ETM_CRDT_CFG_STATE_T; + +typedef struct dpp_etm_crdt_crdt_ind_cmd_t +{ + ZXIC_UINT32 rd; + ZXIC_UINT32 mem_id; + ZXIC_UINT32 addr; +}DPP_ETM_CRDT_CRDT_IND_CMD_T; + +typedef struct dpp_etm_crdt_crdt_ind_sta_t +{ + ZXIC_UINT32 indirectaccessdone; +}DPP_ETM_CRDT_CRDT_IND_STA_T; + +typedef struct dpp_etm_crdt_crdt_ind_data0_t +{ + ZXIC_UINT32 indirectdata0; +}DPP_ETM_CRDT_CRDT_IND_DATA0_T; + +typedef struct dpp_etm_crdt_crdt_ind_data1_t +{ + ZXIC_UINT32 indirectdata1; +}DPP_ETM_CRDT_CRDT_IND_DATA1_T; + +typedef struct dpp_etm_crdt_crdt_state_t +{ + ZXIC_UINT32 crdt_int; + ZXIC_UINT32 crdt_rdy; +}DPP_ETM_CRDT_CRDT_STATE_T; + +typedef struct dpp_etm_crdt_stat_que_id_0_t +{ + ZXIC_UINT32 stat_que_id_0; +}DPP_ETM_CRDT_STAT_QUE_ID_0_T; + +typedef struct dpp_etm_crdt_stat_que_id_1_t +{ + ZXIC_UINT32 stat_que_id_1; +}DPP_ETM_CRDT_STAT_QUE_ID_1_T; + +typedef struct dpp_etm_crdt_stat_que_id_2_t +{ + ZXIC_UINT32 stat_que_id_2; +}DPP_ETM_CRDT_STAT_QUE_ID_2_T; + +typedef struct dpp_etm_crdt_stat_que_id_3_t +{ + ZXIC_UINT32 stat_que_id_3; +}DPP_ETM_CRDT_STAT_QUE_ID_3_T; + +typedef struct dpp_etm_crdt_stat_que_id_4_t +{ + ZXIC_UINT32 stat_que_id_4; +}DPP_ETM_CRDT_STAT_QUE_ID_4_T; + +typedef struct dpp_etm_crdt_stat_que_id_5_t +{ + ZXIC_UINT32 stat_que_id_5; +}DPP_ETM_CRDT_STAT_QUE_ID_5_T; + +typedef struct dpp_etm_crdt_stat_que_id_6_t +{ + ZXIC_UINT32 stat_que_id_6; +}DPP_ETM_CRDT_STAT_QUE_ID_6_T; + +typedef struct dpp_etm_crdt_stat_que_id_7_t +{ + ZXIC_UINT32 stat_que_id_7; +}DPP_ETM_CRDT_STAT_QUE_ID_7_T; + +typedef struct dpp_etm_crdt_stat_que_id_8_t +{ + ZXIC_UINT32 stat_que_id_8; +}DPP_ETM_CRDT_STAT_QUE_ID_8_T; + +typedef struct dpp_etm_crdt_stat_que_id_9_t +{ + ZXIC_UINT32 stat_que_id_9; +}DPP_ETM_CRDT_STAT_QUE_ID_9_T; + +typedef struct dpp_etm_crdt_stat_que_id_10_t +{ + ZXIC_UINT32 stat_que_id_10; +}DPP_ETM_CRDT_STAT_QUE_ID_10_T; + +typedef struct dpp_etm_crdt_stat_que_id_11_t +{ + ZXIC_UINT32 stat_que_id_11; +}DPP_ETM_CRDT_STAT_QUE_ID_11_T; + +typedef struct dpp_etm_crdt_stat_que_id_12_t +{ + ZXIC_UINT32 stat_que_id_12; +}DPP_ETM_CRDT_STAT_QUE_ID_12_T; + +typedef struct dpp_etm_crdt_stat_que_id_13_t +{ + ZXIC_UINT32 stat_que_id_13; +}DPP_ETM_CRDT_STAT_QUE_ID_13_T; + +typedef struct dpp_etm_crdt_stat_que_id_14_t +{ + ZXIC_UINT32 stat_que_id_14; +}DPP_ETM_CRDT_STAT_QUE_ID_14_T; + +typedef struct dpp_etm_crdt_stat_que_id_15_t +{ + ZXIC_UINT32 stat_que_id_15; +}DPP_ETM_CRDT_STAT_QUE_ID_15_T; + +typedef struct dpp_etm_crdt_stat_que_credit_t +{ + ZXIC_UINT32 stat_que_credit_cnt; +}DPP_ETM_CRDT_STAT_QUE_CREDIT_T; + +typedef struct dpp_etm_crdt_crdt_cfg_ram_init_t +{ + ZXIC_UINT32 cfg_ram_init_done; + ZXIC_UINT32 cfg_ram_init_en; +}DPP_ETM_CRDT_CRDT_CFG_RAM_INIT_T; + +typedef struct dpp_etm_crdt_crdt_sta_ram_init_t +{ + ZXIC_UINT32 sta_ram_init_done; + ZXIC_UINT32 sta_ram_init_en; +}DPP_ETM_CRDT_CRDT_STA_RAM_INIT_T; + +typedef struct dpp_etm_crdt_crs_que_id_t +{ + ZXIC_UINT32 crs_que_id; +}DPP_ETM_CRDT_CRS_QUE_ID_T; + +typedef struct dpp_etm_crdt_qmu_crs_end_state_t +{ + ZXIC_UINT32 qmu_crs_end_state; +}DPP_ETM_CRDT_QMU_CRS_END_STATE_T; + +typedef struct dpp_etm_crdt_shap_rdy_t +{ + ZXIC_UINT32 shap_rdy; +}DPP_ETM_CRDT_SHAP_RDY_T; + +typedef struct dpp_etm_crdt_shap_int_reg_t +{ + ZXIC_UINT32 pp_c_token_min_int; +}DPP_ETM_CRDT_SHAP_INT_REG_T; + +typedef struct dpp_etm_crdt_shap_int_mask_reg_t +{ + ZXIC_UINT32 pp_c_token_min_int_mask; +}DPP_ETM_CRDT_SHAP_INT_MASK_REG_T; + +typedef struct dpp_etm_crdt_token_state_almost_empty_th_t +{ + ZXIC_UINT32 token_state_almost_empty_th; +}DPP_ETM_CRDT_TOKEN_STATE_ALMOST_EMPTY_TH_T; + +typedef struct dpp_etm_crdt_token_state_empty_th_t +{ + ZXIC_UINT32 token_state_empty_th; +}DPP_ETM_CRDT_TOKEN_STATE_EMPTY_TH_T; + +typedef struct dpp_etm_crdt_full_th_t +{ + ZXIC_UINT32 token_state_full_th; +}DPP_ETM_CRDT_FULL_TH_T; + +typedef struct dpp_etm_crdt_pp_c_level_shap_en_t +{ + ZXIC_UINT32 pp_c_level_shap_en; +}DPP_ETM_CRDT_PP_C_LEVEL_SHAP_EN_T; + +typedef struct dpp_etm_crdt_enq_token_th_t +{ + ZXIC_UINT32 enq_token_th; +}DPP_ETM_CRDT_ENQ_TOKEN_TH_T; + +typedef struct dpp_etm_crdt_pp_tokenq_level1_qstate_weight_cir_t +{ + ZXIC_UINT32 pp_pp_q_state_cir; + ZXIC_UINT32 pp_pp_q_weight_wfq_l1_cir; +}DPP_ETM_CRDT_PP_TOKENQ_LEVEL1_QSTATE_WEIGHT_CIR_T; + +typedef struct dpp_etm_crdt_pp_idle_weight_level1_cir_t +{ + ZXIC_UINT32 pp_idle_q_weight_wfq_l1_cir; +}DPP_ETM_CRDT_PP_IDLE_WEIGHT_LEVEL1_CIR_T; + +typedef struct dpp_etm_crdt_rci_grade_th_0_cfg_t +{ + ZXIC_UINT32 rci_grade_th_0_cfg; +}DPP_ETM_CRDT_RCI_GRADE_TH_0_CFG_T; + +typedef struct dpp_etm_crdt_rci_grade_th_1_cfg_t +{ + ZXIC_UINT32 rci_grade_th_1_cfg; +}DPP_ETM_CRDT_RCI_GRADE_TH_1_CFG_T; + +typedef struct dpp_etm_crdt_rci_grade_th_2_cfg_t +{ + ZXIC_UINT32 rci_grade_th_2_cfg; +}DPP_ETM_CRDT_RCI_GRADE_TH_2_CFG_T; + +typedef struct dpp_etm_crdt_rci_grade_th_3_cfg_t +{ + ZXIC_UINT32 rci_grade_th_3_cfg; +}DPP_ETM_CRDT_RCI_GRADE_TH_3_CFG_T; + +typedef struct dpp_etm_crdt_rci_grade_th_4_cfg_t +{ + ZXIC_UINT32 rci_grade_th_4_cfg; +}DPP_ETM_CRDT_RCI_GRADE_TH_4_CFG_T; + +typedef struct dpp_etm_crdt_rci_grade_th_5_cfg_t +{ + ZXIC_UINT32 rci_grade_th_5_cfg; +}DPP_ETM_CRDT_RCI_GRADE_TH_5_CFG_T; + +typedef struct dpp_etm_crdt_rci_grade_th_6_cfg_t +{ + ZXIC_UINT32 rci_grade_th_6_cfg; +}DPP_ETM_CRDT_RCI_GRADE_TH_6_CFG_T; + +typedef struct dpp_etm_crdt_flow_del_cmd_t +{ + ZXIC_UINT32 flow_del_busy; + ZXIC_UINT32 flow_alt_cmd; + ZXIC_UINT32 flow_alt_ind; +}DPP_ETM_CRDT_FLOW_DEL_CMD_T; + +typedef struct dpp_etm_crdt_cnt_clr_t +{ + ZXIC_UINT32 cnt_clr; +}DPP_ETM_CRDT_CNT_CLR_T; + +typedef struct dpp_etm_crdt_crdt_int_bus_t +{ + ZXIC_UINT32 ldstr_fifo15_ovf_int; + ZXIC_UINT32 ldstr_fifo14_ovf_int; + ZXIC_UINT32 ldstr_fifo13_ovf_int; + ZXIC_UINT32 ldstr_fifo12_ovf_int; + ZXIC_UINT32 ldstr_fifo11_ovf_int; + ZXIC_UINT32 ldstr_fifo10_ovf_int; + ZXIC_UINT32 ldstr_fifo9_ovf_int; + ZXIC_UINT32 ldstr_fifo8_ovf_int; + ZXIC_UINT32 ldstr_fifo7_ovf_int; + ZXIC_UINT32 ldstr_fifo6_ovf_int; + ZXIC_UINT32 ldstr_fifo5_ovf_int; + ZXIC_UINT32 ldstr_fifo4_ovf_int; + ZXIC_UINT32 ldstr_fifo3_ovf_int; + ZXIC_UINT32 ldstr_fifo2_ovf_int; + ZXIC_UINT32 ldstr_fifo1_ovf_int; + ZXIC_UINT32 ldstr_fifo0_ovf_int; + ZXIC_UINT32 cfg_del_err_int; + ZXIC_UINT32 flwin_secrs_fifo_ovf_int; + ZXIC_UINT32 flwin_voqcrs_fifo_ovf_int; +}DPP_ETM_CRDT_CRDT_INT_BUS_T; + +typedef struct dpp_etm_crdt_crdt_int_mask_t +{ + ZXIC_UINT32 crdt_int_mask; +}DPP_ETM_CRDT_CRDT_INT_MASK_T; + +typedef struct dpp_etm_crdt_cfg_weight_together_t +{ + ZXIC_UINT32 cfg_weight_together; +}DPP_ETM_CRDT_CFG_WEIGHT_TOGETHER_T; + +typedef struct dpp_etm_crdt_weight_t +{ + ZXIC_UINT32 c_weight; + ZXIC_UINT32 e_weight; +}DPP_ETM_CRDT_WEIGHT_T; + +typedef struct dpp_etm_crdt_dev_sp_state_t +{ + ZXIC_UINT32 dev_sp_state; +}DPP_ETM_CRDT_DEV_SP_STATE_T; + +typedef struct dpp_etm_crdt_dev_crs_t +{ + ZXIC_UINT32 dev_crs; +}DPP_ETM_CRDT_DEV_CRS_T; + +typedef struct dpp_etm_crdt_congest_token_disable_31_0_t +{ + ZXIC_UINT32 congest_token_disable_31_0; +}DPP_ETM_CRDT_CONGEST_TOKEN_DISABLE_31_0_T; + +typedef struct dpp_etm_crdt_congest_token_disable_63_32_t +{ + ZXIC_UINT32 congest_token_disable_63_32; +}DPP_ETM_CRDT_CONGEST_TOKEN_DISABLE_63_32_T; + +typedef struct dpp_etm_crdt_crdt_interval_en_cfg_t +{ + ZXIC_UINT32 crdt_interval_en; +}DPP_ETM_CRDT_CRDT_INTERVAL_EN_CFG_T; + +typedef struct dpp_etm_crdt_q_token_staue_cfg_t +{ + ZXIC_UINT32 test_token_q_id; +}DPP_ETM_CRDT_Q_TOKEN_STAUE_CFG_T; + +typedef struct dpp_etm_crdt_q_token_dist_cnt_t +{ + ZXIC_UINT32 q_token_dist_counter; +}DPP_ETM_CRDT_Q_TOKEN_DIST_CNT_T; + +typedef struct dpp_etm_crdt_q_token_dec_cnt_t +{ + ZXIC_UINT32 q_token_dec_counter; +}DPP_ETM_CRDT_Q_TOKEN_DEC_CNT_T; + +typedef struct dpp_etm_crdt_pp_weight_ram_t +{ + ZXIC_UINT32 pp_c_weight; +}DPP_ETM_CRDT_PP_WEIGHT_RAM_T; + +typedef struct dpp_etm_crdt_pp_cbs_shape_en_ram_t +{ + ZXIC_UINT32 pp_cbs; + ZXIC_UINT32 pp_c_shap_en; +}DPP_ETM_CRDT_PP_CBS_SHAPE_EN_RAM_T; + +typedef struct dpp_etm_crdt_pp_next_pc_q_state_ram_t +{ + ZXIC_UINT32 pp_next_pc; + ZXIC_UINT32 pp_token_num; + ZXIC_UINT32 pp_q_state; +}DPP_ETM_CRDT_PP_NEXT_PC_Q_STATE_RAM_T; + +typedef struct dpp_etm_crdt_dev_interval_t +{ + ZXIC_UINT32 dev_interval; +}DPP_ETM_CRDT_DEV_INTERVAL_T; + +typedef struct dpp_etm_crdt_dev_wfq_cnt_t +{ + ZXIC_UINT32 dev_wfq_cnt; +}DPP_ETM_CRDT_DEV_WFQ_CNT_T; + +typedef struct dpp_etm_crdt_dev_wfq_state_t +{ + ZXIC_UINT32 dev_wfq_state; +}DPP_ETM_CRDT_DEV_WFQ_STATE_T; + +typedef struct dpp_etm_crdt_dev_active_head_ptr_t +{ + ZXIC_UINT32 dev_active_head_ptr; +}DPP_ETM_CRDT_DEV_ACTIVE_HEAD_PTR_T; + +typedef struct dpp_etm_crdt_dev_active_tail_ptr_t +{ + ZXIC_UINT32 dev_active_tail_ptr; +}DPP_ETM_CRDT_DEV_ACTIVE_TAIL_PTR_T; + +typedef struct dpp_etm_crdt_dev_unactive_head_ptr_t +{ + ZXIC_UINT32 dev_unactive_head_ptr; +}DPP_ETM_CRDT_DEV_UNACTIVE_HEAD_PTR_T; + +typedef struct dpp_etm_crdt_dev_unactive_tail_ptr_t +{ + ZXIC_UINT32 dev_unactive_tail_ptr; +}DPP_ETM_CRDT_DEV_UNACTIVE_TAIL_PTR_T; + +typedef struct dpp_etm_crdt_pp_weight_t +{ + ZXIC_UINT32 pp_weight; +}DPP_ETM_CRDT_PP_WEIGHT_T; + +typedef struct dpp_etm_crdt_pp_que_state_t +{ + ZXIC_UINT32 pp_enque_flag; + ZXIC_UINT32 pp_cir; + ZXIC_UINT32 pp_congest_cir; + ZXIC_UINT32 pp_crs; + ZXIC_UINT32 dev_sp; +}DPP_ETM_CRDT_PP_QUE_STATE_T; + +typedef struct dpp_etm_crdt_pp_next_ptr_t +{ + ZXIC_UINT32 pp_next_ptr; +}DPP_ETM_CRDT_PP_NEXT_PTR_T; + +typedef struct dpp_etm_crdt_pp_cfg_t +{ + ZXIC_UINT32 pp_cfg; +}DPP_ETM_CRDT_PP_CFG_T; + +typedef struct dpp_etm_crdt_pp_up_ptr_t +{ + ZXIC_UINT32 pp_up_ptr; +}DPP_ETM_CRDT_PP_UP_PTR_T; + +typedef struct dpp_etm_crdt_credit_drop_num_t +{ + ZXIC_UINT32 credit_drop_num; +}DPP_ETM_CRDT_CREDIT_DROP_NUM_T; + +typedef struct dpp_etm_crdt_se_id_lv0_t +{ + ZXIC_UINT32 se_id_out_lv0; +}DPP_ETM_CRDT_SE_ID_LV0_T; + +typedef struct dpp_etm_crdt_se_id_lv1_t +{ + ZXIC_UINT32 se_id_out_lv1; +}DPP_ETM_CRDT_SE_ID_LV1_T; + +typedef struct dpp_etm_crdt_se_id_lv2_t +{ + ZXIC_UINT32 se_id_out_lv2; +}DPP_ETM_CRDT_SE_ID_LV2_T; + +typedef struct dpp_etm_crdt_se_id_lv3_t +{ + ZXIC_UINT32 se_id_out_lv3; +}DPP_ETM_CRDT_SE_ID_LV3_T; + +typedef struct dpp_etm_crdt_se_id_lv4_t +{ + ZXIC_UINT32 se_id_out_lv4; +}DPP_ETM_CRDT_SE_ID_LV4_T; + +typedef struct dpp_etm_crdt_que_id_t +{ + ZXIC_UINT32 que_id_out; +}DPP_ETM_CRDT_QUE_ID_T; + +typedef struct dpp_etm_crdt_se_info_lv0_t +{ + ZXIC_UINT32 se_shape_lv0; + ZXIC_UINT32 se_ins_out_lv0; + ZXIC_UINT32 se_state_out_lv0; + ZXIC_UINT32 se_new_state_out_lv0; +}DPP_ETM_CRDT_SE_INFO_LV0_T; + +typedef struct dpp_etm_crdt_se_info_lv1_t +{ + ZXIC_UINT32 se_shape_lv1; + ZXIC_UINT32 se_ins_out_lv1; + ZXIC_UINT32 se_state_out_lv1; + ZXIC_UINT32 se_new_state_out_lv1; +}DPP_ETM_CRDT_SE_INFO_LV1_T; + +typedef struct dpp_etm_crdt_se_info_lv2_t +{ + ZXIC_UINT32 se_shape_lv2; + ZXIC_UINT32 se_ins_out_lv2; + ZXIC_UINT32 se_state_out_lv2; + ZXIC_UINT32 se_new_state_out_lv2; +}DPP_ETM_CRDT_SE_INFO_LV2_T; + +typedef struct dpp_etm_crdt_se_info_lv3_t +{ + ZXIC_UINT32 se_shape_lv3; + ZXIC_UINT32 se_ins_out_lv3; + ZXIC_UINT32 se_state_out_lv3; + ZXIC_UINT32 se_new_state_out_lv3; +}DPP_ETM_CRDT_SE_INFO_LV3_T; + +typedef struct dpp_etm_crdt_se_info_lv4_t +{ + ZXIC_UINT32 se_shape_lv4; + ZXIC_UINT32 se_ins_out_lv4; + ZXIC_UINT32 se_state_out_lv4; + ZXIC_UINT32 se_new_state_out_lv4; +}DPP_ETM_CRDT_SE_INFO_LV4_T; + +typedef struct dpp_etm_crdt_que_state_t +{ + ZXIC_UINT32 que_state_out; +}DPP_ETM_CRDT_QUE_STATE_T; + +typedef struct dpp_etm_crdt_eir_off_in_advance_t +{ + ZXIC_UINT32 eir_crs_filter; +}DPP_ETM_CRDT_EIR_OFF_IN_ADVANCE_T; + +typedef struct dpp_etm_crdt_double_level_shap_prevent_t +{ + ZXIC_UINT32 double_level_shap_prevent; +}DPP_ETM_CRDT_DOUBLE_LEVEL_SHAP_PREVENT_T; + +typedef struct dpp_etm_crdt_add_store_cycle_t +{ + ZXIC_UINT32 add_store_cycle; +}DPP_ETM_CRDT_ADD_STORE_CYCLE_T; + +typedef struct dpp_etm_crdt_tflag2_wr_flag_sum_t +{ + ZXIC_UINT32 tflag2_wr_flag_sum; +}DPP_ETM_CRDT_TFLAG2_WR_FLAG_SUM_T; + +typedef struct dpp_etm_crdt_flowque_para_tbl_t +{ + ZXIC_UINT32 flowque_link; + ZXIC_UINT32 flowque_w; + ZXIC_UINT32 flowque_pri; +}DPP_ETM_CRDT_FLOWQUE_PARA_TBL_T; + +typedef struct dpp_etm_crdt_se_para_tbl_t +{ + ZXIC_UINT32 se_insw; + ZXIC_UINT32 se_link; + ZXIC_UINT32 cp_token_en; + ZXIC_UINT32 se_w; + ZXIC_UINT32 se_pri; +}DPP_ETM_CRDT_SE_PARA_TBL_T; + +typedef struct dpp_etm_crdt_flowque_ins_tbl_t +{ + ZXIC_UINT32 flowque_ins; +}DPP_ETM_CRDT_FLOWQUE_INS_TBL_T; + +typedef struct dpp_etm_crdt_se_ins_tbl_t +{ + ZXIC_UINT32 se_ins_flag; + ZXIC_UINT32 se_ins_priority; +}DPP_ETM_CRDT_SE_INS_TBL_T; + +typedef struct dpp_etm_crdt_eir_crs_filter_tbl_t +{ + ZXIC_UINT32 eir_crs_filter; +}DPP_ETM_CRDT_EIR_CRS_FILTER_TBL_T; + +typedef struct dpp_etm_qmu_qcfg_qlist_cfg_done_t +{ + ZXIC_UINT32 qcfg_qlist_cfg_done; +}DPP_ETM_QMU_QCFG_QLIST_CFG_DONE_T; + +typedef struct dpp_etm_qmu_qcfg_qsch_credit_value_t +{ + ZXIC_UINT32 qcfg_qsch_credit_value; +}DPP_ETM_QMU_QCFG_QSCH_CREDIT_VALUE_T; + +typedef struct dpp_etm_qmu_qcfg_qsch_crbal_init_value_t +{ + ZXIC_UINT32 qcfg_qsch_crbal_init_value; +}DPP_ETM_QMU_QCFG_QSCH_CRBAL_INIT_VALUE_T; + +typedef struct dpp_etm_qmu_qcfg_qsch_crbal_init_mask_t +{ + ZXIC_UINT32 qcfg_qsch_crbal_init_mask; +}DPP_ETM_QMU_QCFG_QSCH_CRBAL_INIT_MASK_T; + +typedef struct dpp_etm_qmu_cmdsch_rd_cmd_aful_th_t +{ + ZXIC_UINT32 cmdsch_rd_cmd_aful_th; +}DPP_ETM_QMU_CMDSCH_RD_CMD_AFUL_TH_T; + +typedef struct dpp_etm_qmu_cfg_port_fc_interval_t +{ + ZXIC_UINT32 cfg_port_fc_interval; +}DPP_ETM_QMU_CFG_PORT_FC_INTERVAL_T; + +typedef struct dpp_etm_qmu_qcfg_csch_aged_cfg_t +{ + ZXIC_UINT32 qcfg_csch_aged_cfg; +}DPP_ETM_QMU_QCFG_CSCH_AGED_CFG_T; + +typedef struct dpp_etm_qmu_qcfg_csch_aged_scan_time_t +{ + ZXIC_UINT32 qcfg_csch_aged_scan_time; +}DPP_ETM_QMU_QCFG_CSCH_AGED_SCAN_TIME_T; + +typedef struct dpp_etm_qmu_qcfg_qmu_qlist_state_query_t +{ + ZXIC_UINT32 pkt_age_req_fifo_afull; + ZXIC_UINT32 rd_release_fwft_afull; + ZXIC_UINT32 drop_imem_fwft_afull; + ZXIC_UINT32 pkt_age_req_fifo_empty; + ZXIC_UINT32 rd_release_fwft_empty; + ZXIC_UINT32 drop_imem_fwft_empty; + ZXIC_UINT32 mmu_qmu_sop_rd_rdy; + ZXIC_UINT32 big_fifo_empty; + ZXIC_UINT32 qmu_mmu_rd_release_rdy; + ZXIC_UINT32 xsw_qmu_crs_rdy; + ZXIC_UINT32 mmu_qmu_rdy; + ZXIC_UINT32 mmu_ql_wr_rdy; + ZXIC_UINT32 mmu_ql_rd_rdy; + ZXIC_UINT32 csw_ql_rdy; + ZXIC_UINT32 ql_init_done; + ZXIC_UINT32 free_addr_ready; + ZXIC_UINT32 bank_group_afull; + ZXIC_UINT32 pds_fwft_empty; + ZXIC_UINT32 enq_rpt_fwft_afull; +}DPP_ETM_QMU_QCFG_QMU_QLIST_STATE_QUERY_T; + +typedef struct dpp_etm_qmu_cfgmt_qsch_crbal_drop_en_t +{ + ZXIC_UINT32 cfgmt_qsch_all_crbal_drop_en; + ZXIC_UINT32 cfgmt_qsch_crbal_drop_en; +}DPP_ETM_QMU_CFGMT_QSCH_CRBAL_DROP_EN_T; + +typedef struct dpp_etm_qmu_cfgmt_wlist_qnum_fifo_aful_th_t +{ + ZXIC_UINT32 cfgmt_wlist_qnum_fifo_aful_th; +}DPP_ETM_QMU_CFGMT_WLIST_QNUM_FIFO_AFUL_TH_T; + +typedef struct dpp_etm_qmu_qcfg_csw_pkt_blk_mode_t +{ + ZXIC_UINT32 qcfg_csw_pkt_blk_mode; +}DPP_ETM_QMU_QCFG_CSW_PKT_BLK_MODE_T; + +typedef struct dpp_etm_qmu_qcfg_qlist_ram_init_cancel_t +{ + ZXIC_UINT32 qcfg_qlist_ram_init_cancel; +}DPP_ETM_QMU_QCFG_QLIST_RAM_INIT_CANCEL_T; + +typedef struct dpp_etm_qmu_qcfg_qsch_crbal_transfer_mode_t +{ + ZXIC_UINT32 qcfg_qsch_crbal_transfer_mode; + ZXIC_UINT32 qcfg_qsch_crbal_transfer_value; +}DPP_ETM_QMU_QCFG_QSCH_CRBAL_TRANSFER_MODE_T; + +typedef struct dpp_etm_qmu_qcfg_qlist_qclr_interval_t +{ + ZXIC_UINT32 qcfg_qlist_qclr_interval; +}DPP_ETM_QMU_QCFG_QLIST_QCLR_INTERVAL_T; + +typedef struct dpp_etm_qmu_qcfg_qsch_qclr_rate_t +{ + ZXIC_UINT32 qcfg_qsch_qclr_rate; +}DPP_ETM_QMU_QCFG_QSCH_QCLR_RATE_T; + +typedef struct dpp_etm_qmu_qcfg_qlist_ddr_random_t +{ + ZXIC_UINT32 qcfg_qlist_ddr_random; +}DPP_ETM_QMU_QCFG_QLIST_DDR_RANDOM_T; + +typedef struct dpp_etm_qmu_cfgmt_qlist_pds_fifo_afull_th_t +{ + ZXIC_UINT32 cfgmt_qlist_pds_fifo_afull_th; +}DPP_ETM_QMU_CFGMT_QLIST_PDS_FIFO_AFULL_TH_T; + +typedef struct dpp_etm_qmu_cfgmt_sop_cmd_fifo_afull_th_t +{ + ZXIC_UINT32 cfgmt_sop_cmd_fifo_afull_th; +}DPP_ETM_QMU_CFGMT_SOP_CMD_FIFO_AFULL_TH_T; + +typedef struct dpp_etm_qmu_cfgmt_non_sop_cmd_fifo_afull_th_t +{ + ZXIC_UINT32 cfgmt_non_sop_cmd_fifo_afull_th; +}DPP_ETM_QMU_CFGMT_NON_SOP_CMD_FIFO_AFULL_TH_T; + +typedef struct dpp_etm_qmu_cfgmt_mmu_data_fifo_afull_th_t +{ + ZXIC_UINT32 cfgmt_mmu_data_fifo_afull_th; +}DPP_ETM_QMU_CFGMT_MMU_DATA_FIFO_AFULL_TH_T; + +typedef struct dpp_etm_qmu_qcfg_qlist_bank_ept_th_t +{ + ZXIC_UINT32 qcfg_qlist_bank_ept_th; +}DPP_ETM_QMU_QCFG_QLIST_BANK_EPT_TH_T; + +typedef struct dpp_etm_qmu_random_bypass_en_t +{ + ZXIC_UINT32 random_bypass_en; +}DPP_ETM_QMU_RANDOM_BYPASS_EN_T; + +typedef struct dpp_etm_qmu_cfgmt_crs_spd_bypass_t +{ + ZXIC_UINT32 cfgmt_crs_spd_bypass; +}DPP_ETM_QMU_CFGMT_CRS_SPD_BYPASS_T; + +typedef struct dpp_etm_qmu_cfgmt_crs_interval_t +{ + ZXIC_UINT32 cfgmt_crs_interval; +}DPP_ETM_QMU_CFGMT_CRS_INTERVAL_T; + +typedef struct dpp_etm_qmu_cfg_qsch_auto_credit_control_en_t +{ + ZXIC_UINT32 cfg_qsch_auto_credit_control_en; +}DPP_ETM_QMU_CFG_QSCH_AUTO_CREDIT_CONTROL_EN_T; + +typedef struct dpp_etm_qmu_cfg_qsch_autocrfrstque_t +{ + ZXIC_UINT32 cfg_qsch_autocrfrstque; +}DPP_ETM_QMU_CFG_QSCH_AUTOCRFRSTQUE_T; + +typedef struct dpp_etm_qmu_cfg_qsch_autocrlastque_t +{ + ZXIC_UINT32 cfg_qsch_autocrlastque; +}DPP_ETM_QMU_CFG_QSCH_AUTOCRLASTQUE_T; + +typedef struct dpp_etm_qmu_cfg_qsch_autocreditrate_t +{ + ZXIC_UINT32 cfg_qsch_autocreditrate; +}DPP_ETM_QMU_CFG_QSCH_AUTOCREDITRATE_T; + +typedef struct dpp_etm_qmu_cfg_qsch_scanfrstque_t +{ + ZXIC_UINT32 cfg_qsch_scanfrstque; +}DPP_ETM_QMU_CFG_QSCH_SCANFRSTQUE_T; + +typedef struct dpp_etm_qmu_cfg_qsch_scanlastque_t +{ + ZXIC_UINT32 cfg_qsch_scanlastque; +}DPP_ETM_QMU_CFG_QSCH_SCANLASTQUE_T; + +typedef struct dpp_etm_qmu_cfg_qsch_scanrate_t +{ + ZXIC_UINT32 cfg_qsch_scanrate; +}DPP_ETM_QMU_CFG_QSCH_SCANRATE_T; + +typedef struct dpp_etm_qmu_cfg_qsch_scan_en_t +{ + ZXIC_UINT32 cfg_qsch_scan_en; +}DPP_ETM_QMU_CFG_QSCH_SCAN_EN_T; + +typedef struct dpp_etm_qmu_cfgmt_qsch_rd_credit_fifo_rate_t +{ + ZXIC_UINT32 cfgmt_qsch_rd_credit_fifo_rate; +}DPP_ETM_QMU_CFGMT_QSCH_RD_CREDIT_FIFO_RATE_T; + +typedef struct dpp_etm_qmu_qcfg_qlist_bdep_t +{ + ZXIC_UINT32 qcfg_qlist_bdep; +}DPP_ETM_QMU_QCFG_QLIST_BDEP_T; + +typedef struct dpp_etm_qmu_qcfg_qlist_bhead_t +{ + ZXIC_UINT32 bank_vld; + ZXIC_UINT32 qcfg_qlist_bhead; +}DPP_ETM_QMU_QCFG_QLIST_BHEAD_T; + +typedef struct dpp_etm_qmu_qcfg_qlist_btail_t +{ + ZXIC_UINT32 qcfg_qlist_btail; +}DPP_ETM_QMU_QCFG_QLIST_BTAIL_T; + +typedef struct dpp_etm_qmu_qcfg_qsch_shap_param_t +{ + ZXIC_UINT32 qcfg_qsch_shap_en; + ZXIC_UINT32 qcfg_qsch_shap_param1; + ZXIC_UINT32 qcfg_qsch_shap_param2; +}DPP_ETM_QMU_QCFG_QSCH_SHAP_PARAM_T; + +typedef struct dpp_etm_qmu_qcfg_qsch_shap_token_t +{ + ZXIC_UINT32 qcfg_qsch_shap_token; +}DPP_ETM_QMU_QCFG_QSCH_SHAP_TOKEN_T; + +typedef struct dpp_etm_qmu_qcfg_qsch_shap_offset_t +{ + ZXIC_UINT32 qcfg_qsch_shap_offset; +}DPP_ETM_QMU_QCFG_QSCH_SHAP_OFFSET_T; + +typedef struct dpp_etm_qmu_qcfg_qsch_crs_eir_th_t +{ + ZXIC_UINT32 qcfg_qsch_crs_eir_th; +}DPP_ETM_QMU_QCFG_QSCH_CRS_EIR_TH_T; + +typedef struct dpp_etm_qmu_qcfg_qsch_crs_th1_t +{ + ZXIC_UINT32 qcfg_qsch_crs_th1; +}DPP_ETM_QMU_QCFG_QSCH_CRS_TH1_T; + +typedef struct dpp_etm_qmu_qcfg_qsch_crs_th2_t +{ + ZXIC_UINT32 qcfg_qsch_crs_th2; +}DPP_ETM_QMU_QCFG_QSCH_CRS_TH2_T; + +typedef struct dpp_etm_qmu_qcfg_csch_congest_th_t +{ + ZXIC_UINT32 qcfg_csch_congest_th; +}DPP_ETM_QMU_QCFG_CSCH_CONGEST_TH_T; + +typedef struct dpp_etm_qmu_qcfg_csch_sp_fc_th_t +{ + ZXIC_UINT32 qcfg_csch_sp_fc_th; +}DPP_ETM_QMU_QCFG_CSCH_SP_FC_TH_T; + +typedef struct dpp_etm_qmu_qcfg_csw_shap_parameter_t +{ + ZXIC_UINT32 qcfg_csw_shap_en; + ZXIC_UINT32 qcfg_csw_shap_parameter; +}DPP_ETM_QMU_QCFG_CSW_SHAP_PARAMETER_T; + +typedef struct dpp_etm_qmu_cfgmt_rd_release_aful_th_t +{ + ZXIC_UINT32 cfgmt_rd_release_aful_th; +}DPP_ETM_QMU_CFGMT_RD_RELEASE_AFUL_TH_T; + +typedef struct dpp_etm_qmu_cfgmt_drop_imem_release_fifo_aful_th_t +{ + ZXIC_UINT32 cfgmt_drop_imem_release_fifo_aful_th; +}DPP_ETM_QMU_CFGMT_DROP_IMEM_RELEASE_FIFO_AFUL_TH_T; + +typedef struct dpp_etm_qmu_cfgmt_nnh_rd_buf_aful_th_t +{ + ZXIC_UINT32 cfgmt_nnh_rd_buf_aful_th; +}DPP_ETM_QMU_CFGMT_NNH_RD_BUF_AFUL_TH_T; + +typedef struct dpp_etm_qmu_cfg_pid_use_inall_t +{ + ZXIC_UINT32 cfgmt_nod_rd_buf_0_aful_th; +}DPP_ETM_QMU_CFG_PID_USE_INALL_T; + +typedef struct dpp_etm_qmu_cfg_pid_round_th_t +{ + ZXIC_UINT32 cfgmt_nod_rd_buf_1_aful_th; +}DPP_ETM_QMU_CFG_PID_ROUND_TH_T; + +typedef struct dpp_etm_qmu_cfgmt_credit_fifo_afull_th_t +{ + ZXIC_UINT32 cfgmt_credit_fifo_afull_th; +}DPP_ETM_QMU_CFGMT_CREDIT_FIFO_AFULL_TH_T; + +typedef struct dpp_etm_qmu_cfgmt_scan_fifo_afull_th_t +{ + ZXIC_UINT32 cfgmt_scan_fifo_afull_th; +}DPP_ETM_QMU_CFGMT_SCAN_FIFO_AFULL_TH_T; + +typedef struct dpp_etm_qmu_cfgmt_small_fifo_aful_th_t +{ + ZXIC_UINT32 cfgmt_small_fifo_aful_th; +}DPP_ETM_QMU_CFGMT_SMALL_FIFO_AFUL_TH_T; + +typedef struct dpp_etm_qmu_cfgmt_free_addr_fifo_aful_th_t +{ + ZXIC_UINT32 cfgmt_free_addr_fifo_aful_th; +}DPP_ETM_QMU_CFGMT_FREE_ADDR_FIFO_AFUL_TH_T; + +typedef struct dpp_etm_qmu_cfgmt_enq_rpt_fifo_aful_th_t +{ + ZXIC_UINT32 cfgmt_enq_rpt_fifo_aful_th; +}DPP_ETM_QMU_CFGMT_ENQ_RPT_FIFO_AFUL_TH_T; + +typedef struct dpp_etm_qmu_qcfg_csw_shap_token_depth_t +{ + ZXIC_UINT32 qcfg_csw_shap_token_depth; +}DPP_ETM_QMU_QCFG_CSW_SHAP_TOKEN_DEPTH_T; + +typedef struct dpp_etm_qmu_qcfg_csw_shap_offset_value_t +{ + ZXIC_UINT32 qcfg_csw_shap_offset_value; +}DPP_ETM_QMU_QCFG_CSW_SHAP_OFFSET_VALUE_T; + +typedef struct dpp_etm_qmu_qcfg_csw_fc_offset_value_t +{ + ZXIC_UINT32 qcfg_csw_fc_offset_value; +}DPP_ETM_QMU_QCFG_CSW_FC_OFFSET_VALUE_T; + +typedef struct dpp_etm_qmu_qmu_init_done_state_t +{ + ZXIC_UINT32 csch_qcfg_init_done; + ZXIC_UINT32 qsch_qcfg_init_done; + ZXIC_UINT32 qlist_qcfg_init_done; + ZXIC_UINT32 qcsr_ram_init_done; +}DPP_ETM_QMU_QMU_INIT_DONE_STATE_T; + +typedef struct dpp_etm_qmu_csw_qcfg_port_shap_rdy_0_t +{ + ZXIC_UINT32 csw_qcfg_port_shap_rdy_0; +}DPP_ETM_QMU_CSW_QCFG_PORT_SHAP_RDY_0_T; + +typedef struct dpp_etm_qmu_csw_qcfg_port_shap_rdy_1_t +{ + ZXIC_UINT32 csw_qcfg_port_shap_rdy_1; +}DPP_ETM_QMU_CSW_QCFG_PORT_SHAP_RDY_1_T; + +typedef struct dpp_etm_qmu_qlist_cfgmt_ram_init_done_t +{ + ZXIC_UINT32 qlist_qcfg_qds_ram_init_done; + ZXIC_UINT32 qlist_qcfg_chk_ram_init_done; + ZXIC_UINT32 qlist_qcfg_ept_ram_init_done; + ZXIC_UINT32 qlist_qcfg_cti_ram_init_done; + ZXIC_UINT32 qlist_qcfg_cto_ram_init_done; + ZXIC_UINT32 qlist_qcfg_bcnt_ram_init_done; + ZXIC_UINT32 qlist_qcfg_biu_ram_init_done; + ZXIC_UINT32 qlist_qcfg_baram_init_done; +}DPP_ETM_QMU_QLIST_CFGMT_RAM_INIT_DONE_T; + +typedef struct dpp_etm_qmu_qlist_cfgmt_ram_ecc_err_t +{ + ZXIC_UINT32 qds_ram_parity_err; + ZXIC_UINT32 qcsr_qnum_fifo_parity_err; + ZXIC_UINT32 sa_id_ram_parity_err; + ZXIC_UINT32 enq_rpt_fifo_parity_err; + ZXIC_UINT32 bcnts_parity_err; + ZXIC_UINT32 baram_parity_err_a; + ZXIC_UINT32 baram_parity_err_b; + ZXIC_UINT32 bcntm_ram_parity_err; + ZXIC_UINT32 biu_ram_single_ecc_err; + ZXIC_UINT32 chk_ram_single_ecc_err; + ZXIC_UINT32 cmd_sch_cmd_ram_single_ecc_err; + ZXIC_UINT32 cmd_sch_list_ram_single_ecc_err; + ZXIC_UINT32 cmd_sch_hp_ram_single_ecc_err; + ZXIC_UINT32 cmd_sch_tp_ram_single_ecc_err; + ZXIC_UINT32 cmd_sch_enq_active_ram_single_ecc_err; + ZXIC_UINT32 cmd_sch_deq_active_ram_single_ecc_err; + ZXIC_UINT32 cmd_sch_empty_ram_single_ecc_err; + ZXIC_UINT32 cmd_sch_eop_ram_single_ecc_err; + ZXIC_UINT32 cmd_sch_blkcnt_ram_single_ecc_err; + ZXIC_UINT32 biu_ram_double_ecc_err; + ZXIC_UINT32 chk_ram_double_ecc_err; + ZXIC_UINT32 cmd_sch_cmd_ram_double_ecc_err; + ZXIC_UINT32 cmd_sch_list_ram_double_ecc_err; + ZXIC_UINT32 cmd_sch_hp_ram_double_ecc_err; + ZXIC_UINT32 cmd_sch_tp_ram_double_ecc_err; + ZXIC_UINT32 cmd_sch_enq_active_ram_double_ecc_err; + ZXIC_UINT32 cmd_sch_deq_active_ram_double_ecc_err; + ZXIC_UINT32 cmd_sch_empty_ram_double_ecc_err; + ZXIC_UINT32 cmd_sch_eop_ram_double_ecc_err; + ZXIC_UINT32 cmd_sch_blkcnt_ram_double_ecc_err; +}DPP_ETM_QMU_QLIST_CFGMT_RAM_ECC_ERR_T; + +typedef struct dpp_etm_qmu_qlist_cfgmt_ram_slot_err_t +{ + ZXIC_UINT32 qds_ram_enq_rd_slot_err; + ZXIC_UINT32 qds_ram_deq_rd_slot_err; + ZXIC_UINT32 qds_ram_enq_wr_slot_err; + ZXIC_UINT32 qds_ram_deq_wr_slot_err; + ZXIC_UINT32 chk_ram_enq_rd_slot_err; + ZXIC_UINT32 chk_ram_deq_rd_slot_err; + ZXIC_UINT32 chk_ram_enq_wr_slot_err; + ZXIC_UINT32 chk_ram_deq_wr_slot_err; + ZXIC_UINT32 ept_ram_enq_rd_slot_err; + ZXIC_UINT32 ept_ram_deq_rd_slot_err; + ZXIC_UINT32 ept_ram_enq_wr_slot_err; + ZXIC_UINT32 ept_ram_deq_wr_slot_err; + ZXIC_UINT32 cti_ram_enq_rd_slot_err; + ZXIC_UINT32 cti_ram_deq_rd_slot_err; + ZXIC_UINT32 cti_ram_enq_wr_slot_err; + ZXIC_UINT32 cti_ram_deq_wr_slot_err; + ZXIC_UINT32 cto_ram_enq_rd_slot_err; + ZXIC_UINT32 cto_ram_deq_rd_slot_err; + ZXIC_UINT32 cto_ram_enq_wr_slot_err; + ZXIC_UINT32 cto_ram_deq_wr_slot_err; +}DPP_ETM_QMU_QLIST_CFGMT_RAM_SLOT_ERR_T; + +typedef struct dpp_etm_qmu_qsch_cfgmt_ram_ecc_t +{ + ZXIC_UINT32 crbal_rama_parity_error; + ZXIC_UINT32 crbal_ramb_parity_error; + ZXIC_UINT32 crs_ram_parity_error; + ZXIC_UINT32 wlist_flag_ram_single_ecc_err; + ZXIC_UINT32 wlist_next_single_ecc_err; + ZXIC_UINT32 wlist_wactive_ram_single_ecc_err; + ZXIC_UINT32 wlist_ractive_ram_single_ecc_err; + ZXIC_UINT32 wlist_tp1_ram_single_ecc_err; + ZXIC_UINT32 wlist_tp2_ram_single_ecc_err; + ZXIC_UINT32 wlist_empty1_ram_single_ecc_err_a; + ZXIC_UINT32 wlist_empty1_ram_single_ecc_err_b; + ZXIC_UINT32 wlist_empty2_ram_single_ecc_err_a; + ZXIC_UINT32 wlist_empty2_ram_single_ecc_err_b; + ZXIC_UINT32 wlist_hp_ram_single_ecc_err_a; + ZXIC_UINT32 wlist_hp_ram_single_ecc_err_b; + ZXIC_UINT32 wlist_flag_ram_double_ecc_err; + ZXIC_UINT32 wlist_next_double_ecc_err; + ZXIC_UINT32 wlist_wactive_ram_double_ecc_err; + ZXIC_UINT32 wlist_ractive_ram_double_ecc_err; + ZXIC_UINT32 wlist_tp1_ram_double_ecc_err; + ZXIC_UINT32 wlist_tp2_ram_double_ecc_err; + ZXIC_UINT32 wlist_empty1_ram_double_ecc_err_a; + ZXIC_UINT32 wlist_empty1_ram_double_ecc_err_b; + ZXIC_UINT32 wlist_empty2_ram_double_ecc_err_a; + ZXIC_UINT32 wlist_empty2_ram_double_ecc_err_b; + ZXIC_UINT32 wlist_hp_ram_double_ecc_err_a; + ZXIC_UINT32 wlist_hp_ram_double_ecc_err_b; +}DPP_ETM_QMU_QSCH_CFGMT_RAM_ECC_T; + +typedef struct dpp_etm_qmu_qlist_cfgmt_fifo_state_t +{ + ZXIC_UINT32 pkt_age_req_fifo_overflow; + ZXIC_UINT32 pkt_age_req_fifo_underflow; + ZXIC_UINT32 qcsr_big_fifo_ovfl; + ZXIC_UINT32 qcsr_small_fifo_overflow; + ZXIC_UINT32 enq_rpt_fifo_overflow; + ZXIC_UINT32 enq_rpt_fifo_underflow; + ZXIC_UINT32 pds_fwft_overflow; + ZXIC_UINT32 pds_fwft_underflow; + ZXIC_UINT32 free_addr_fifo_overflow; + ZXIC_UINT32 free_addr_fifo_underflow; + ZXIC_UINT32 rd_release_fwft_overflow; + ZXIC_UINT32 rd_release_fwft_underflow; + ZXIC_UINT32 pid_free_list_overflow; + ZXIC_UINT32 pid_free_list_underflow; + ZXIC_UINT32 pid_prp_list_overflow; + ZXIC_UINT32 pid_prp_list_underflow; + ZXIC_UINT32 pid_rdy_list_overflow; + ZXIC_UINT32 pid_rdy_list_underflow; + ZXIC_UINT32 drop_imem_release_fwft_overflow; + ZXIC_UINT32 drop_imem_release_fwft_underflow; + ZXIC_UINT32 nnh_rd_buf_fifo_overflow; + ZXIC_UINT32 nnh_rd_buf_fifo_underflow; + ZXIC_UINT32 nod_rd_buf_0_fifo_overflow; + ZXIC_UINT32 nod_rd_buf_0_fifo_underflow; + ZXIC_UINT32 nod_rd_buf_1_fifo_overflow; + ZXIC_UINT32 nod_rd_buf_1_fifo_underflow; +}DPP_ETM_QMU_QLIST_CFGMT_FIFO_STATE_T; + +typedef struct dpp_etm_qmu_qlist_qcfg_clr_done_t +{ + ZXIC_UINT32 qlist_qcfg_clr_done; +}DPP_ETM_QMU_QLIST_QCFG_CLR_DONE_T; + +typedef struct dpp_etm_qmu_qmu_int_mask1_t +{ + ZXIC_UINT32 qmu_int_mask1; +}DPP_ETM_QMU_QMU_INT_MASK1_T; + +typedef struct dpp_etm_qmu_qmu_int_mask2_t +{ + ZXIC_UINT32 qmu_int_mask2; +}DPP_ETM_QMU_QMU_INT_MASK2_T; + +typedef struct dpp_etm_qmu_qmu_int_mask3_t +{ + ZXIC_UINT32 qmu_int_mask3; +}DPP_ETM_QMU_QMU_INT_MASK3_T; + +typedef struct dpp_etm_qmu_qmu_int_mask4_t +{ + ZXIC_UINT32 qmu_int_mask4; +}DPP_ETM_QMU_QMU_INT_MASK4_T; + +typedef struct dpp_etm_qmu_qmu_int_mask5_t +{ + ZXIC_UINT32 qmu_int_mask5; +}DPP_ETM_QMU_QMU_INT_MASK5_T; + +typedef struct dpp_etm_qmu_qmu_int_mask6_t +{ + ZXIC_UINT32 qmu_int_mask6; +}DPP_ETM_QMU_QMU_INT_MASK6_T; + +typedef struct dpp_etm_qmu_cmd_sch_cfgmt_fifo_state_t +{ + ZXIC_UINT32 nsop_fifo_parity_err; + ZXIC_UINT32 cmdsch_rd_cmd_fifo_parity_err; + ZXIC_UINT32 sop_fifo_afull; + ZXIC_UINT32 sop_fifo_empty; + ZXIC_UINT32 sop_fifo_overflow; + ZXIC_UINT32 sop_fifo_underflow; + ZXIC_UINT32 mmu_data_fifo_afull; + ZXIC_UINT32 mmu_data_fifo_empty; + ZXIC_UINT32 mmudat_fifo_overflow; + ZXIC_UINT32 mmudat_fifo_underflow; + ZXIC_UINT32 non_sop_fifo_afull; + ZXIC_UINT32 non_sop_fifo_empty; + ZXIC_UINT32 nsop_fifo_overflow; + ZXIC_UINT32 nsop_fifo_underflow; + ZXIC_UINT32 cmdsch_rd_cmd_fifo_afull; + ZXIC_UINT32 cmdsch_rd_cmd_fifo_empty; + ZXIC_UINT32 cmdsch_rd_cmd_fifo_overflow; + ZXIC_UINT32 cmdsch_rd_cmd_fifo_underflow; + ZXIC_UINT32 wlist_qnum_fifo_overflow; + ZXIC_UINT32 wlist_qnum_fifo_underflow; + ZXIC_UINT32 qsch_scan_fifo_overflow; + ZXIC_UINT32 qsch_scan_fifo_underflow; + ZXIC_UINT32 qsch_credit_fifo_overflow; + ZXIC_UINT32 qsch_credit_fifo_underflow; + ZXIC_UINT32 qsch_credit_fifo2_overflow; + ZXIC_UINT32 qsch_credit_fifo2_underflow; +}DPP_ETM_QMU_CMD_SCH_CFGMT_FIFO_STATE_T; + +typedef struct dpp_etm_qmu_qlist_r_bcnt_t +{ + ZXIC_UINT32 qlist_r_bcnt; +}DPP_ETM_QMU_QLIST_R_BCNT_T; + +typedef struct dpp_etm_qmu_qsch_rw_crbal_t +{ + ZXIC_UINT32 qsch_rw_crbal; +}DPP_ETM_QMU_QSCH_RW_CRBAL_T; + +typedef struct dpp_etm_qmu_qsch_rw_crs_t +{ + ZXIC_UINT32 qsch_rw_crs; +}DPP_ETM_QMU_QSCH_RW_CRS_T; + +typedef struct dpp_etm_qmu_qsch_r_wlist_empty_t +{ + ZXIC_UINT32 qsch_r_wlist_empty; +}DPP_ETM_QMU_QSCH_R_WLIST_EMPTY_T; + +typedef struct dpp_etm_qmu_qcfg_qlist_baram_rd_t +{ + ZXIC_UINT32 qcfg_qlist_baram_rd; +}DPP_ETM_QMU_QCFG_QLIST_BARAM_RD_T; + +typedef struct dpp_etm_qmu_qcfg_qsch_crbal_fb_rw_t +{ + ZXIC_UINT32 qcfg_qlist_crbal_fb_rw; +}DPP_ETM_QMU_QCFG_QSCH_CRBAL_FB_RW_T; + +typedef struct dpp_etm_qmu_qcfg_qlist_grp0_bank_t +{ + ZXIC_UINT32 qcfg_qlist_grp0_bank_wr; +}DPP_ETM_QMU_QCFG_QLIST_GRP0_BANK_T; + +typedef struct dpp_etm_qmu_qcfg_qlist_grp1_bank_t +{ + ZXIC_UINT32 qcfg_qlist_grp1_bank_wr; +}DPP_ETM_QMU_QCFG_QLIST_GRP1_BANK_T; + +typedef struct dpp_etm_qmu_qcfg_qlist_grp2_bank_t +{ + ZXIC_UINT32 qcfg_qlist_grp2_bank_wr; +}DPP_ETM_QMU_QCFG_QLIST_GRP2_BANK_T; + +typedef struct dpp_etm_qmu_qcfg_qlist_grp3_bank_t +{ + ZXIC_UINT32 qcfg_qlist_grp3_bank_wr; +}DPP_ETM_QMU_QCFG_QLIST_GRP3_BANK_T; + +typedef struct dpp_etm_qmu_qcfg_qlist_grp4_bank_t +{ + ZXIC_UINT32 qcfg_qlist_grp4_bank_wr; +}DPP_ETM_QMU_QCFG_QLIST_GRP4_BANK_T; + +typedef struct dpp_etm_qmu_qcfg_qlist_grp5_bank_t +{ + ZXIC_UINT32 qcfg_qlist_grp5_bank_wr; +}DPP_ETM_QMU_QCFG_QLIST_GRP5_BANK_T; + +typedef struct dpp_etm_qmu_qcfg_qlist_grp6_bank_t +{ + ZXIC_UINT32 qcfg_qlist_grp6_bank_wr; +}DPP_ETM_QMU_QCFG_QLIST_GRP6_BANK_T; + +typedef struct dpp_etm_qmu_qcfg_qlist_grp7_bank_t +{ + ZXIC_UINT32 qcfg_qlist_grp7_bank_wr; +}DPP_ETM_QMU_QCFG_QLIST_GRP7_BANK_T; + +typedef struct dpp_etm_qmu_qcfg_qlist_grp_t +{ + ZXIC_UINT32 qcfg_qlist_grp_wr; +}DPP_ETM_QMU_QCFG_QLIST_GRP_T; + +typedef struct dpp_etm_qmu_cfgmt_active_to_bank_cfg_t +{ + ZXIC_UINT32 cfgmt_active_to_bank_cfg; +}DPP_ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFG_T; + +typedef struct dpp_etm_qmu_cfgmt_ddr_in_mmu_cfg_t +{ + ZXIC_UINT32 cfgmt_ddr_in_mmu_cfg; +}DPP_ETM_QMU_CFGMT_DDR_IN_MMU_CFG_T; + +typedef struct dpp_etm_qmu_cfgmt_ddr_in_qmu_cfg_t +{ + ZXIC_UINT32 cfgmt_ddr_in_qmu_cfg; +}DPP_ETM_QMU_CFGMT_DDR_IN_QMU_CFG_T; + +typedef struct dpp_etm_qmu_cfgmt_bank_to_mmu_cfg_t +{ + ZXIC_UINT32 cfgmt_bank_in_mmu_cfg; +}DPP_ETM_QMU_CFGMT_BANK_TO_MMU_CFG_T; + +typedef struct dpp_etm_qmu_cfgmt_bank_to_qmu_cfg_t +{ + ZXIC_UINT32 cfgmt_bank_in_qmu_cfg; +}DPP_ETM_QMU_CFGMT_BANK_TO_QMU_CFG_T; + +typedef struct dpp_etm_qmu_cfgmt_grp_ram_n_clr_thd_t +{ + ZXIC_UINT32 cfgmt_grp_ram_n_clr_thd; +}DPP_ETM_QMU_CFGMT_GRP_RAM_N_CLR_THD_T; + +typedef struct dpp_etm_qmu_cfgmt_age_pkt_num_t +{ + ZXIC_UINT32 cfgmt_age_pkt_num; +}DPP_ETM_QMU_CFGMT_AGE_PKT_NUM_T; + +typedef struct dpp_etm_qmu_cfgmt_age_multi_interval_t +{ + ZXIC_UINT32 cfgmt_age_multi_interval; +}DPP_ETM_QMU_CFGMT_AGE_MULTI_INTERVAL_T; + +typedef struct dpp_etm_qmu_cfgmt_qmu_pkt_age_en_t +{ + ZXIC_UINT32 cfgmt_qmu_pkt_age_en; +}DPP_ETM_QMU_CFGMT_QMU_PKT_AGE_EN_T; + +typedef struct dpp_etm_qmu_cfgmt_qmu_pkt_age_interval_t +{ + ZXIC_UINT32 cfgmt_qmu_pkt_age_interval; +}DPP_ETM_QMU_CFGMT_QMU_PKT_AGE_INTERVAL_T; + +typedef struct dpp_etm_qmu_cfgmt_qmu_pkt_age_start_end_t +{ + ZXIC_UINT32 cfgmt_qmu_pkt_age_end; + ZXIC_UINT32 cfgmt_qmu_pkt_age_start; +}DPP_ETM_QMU_CFGMT_QMU_PKT_AGE_START_END_T; + +typedef struct dpp_etm_qmu_cfgmt_pkt_age_req_aful_th_t +{ + ZXIC_UINT32 cfgmt_pkt_age_req_aful_th; +}DPP_ETM_QMU_CFGMT_PKT_AGE_REQ_AFUL_TH_T; + +typedef struct dpp_etm_qmu_cfgmt_pkt_age_step_interval_t +{ + ZXIC_UINT32 cfgmt_pkt_age_step_interval; +}DPP_ETM_QMU_CFGMT_PKT_AGE_STEP_INTERVAL_T; + +typedef struct dpp_etm_qmu_cfgmt_qmu_imem_age_mode_t +{ + ZXIC_UINT32 cfgmt_qmu_imem_age_en; + ZXIC_UINT32 cfgmt_qmu_imem_age_qlen_en; + ZXIC_UINT32 cfgmt_qmu_imem_age_time_en; +}DPP_ETM_QMU_CFGMT_QMU_IMEM_AGE_MODE_T; + +typedef struct dpp_etm_qmu_cfgmt_qmu_imem_qlen_age_interval_t +{ + ZXIC_UINT32 cfgmt_qmu_imem_qlen_age_interval; +}DPP_ETM_QMU_CFGMT_QMU_IMEM_QLEN_AGE_INTERVAL_T; + +typedef struct dpp_etm_qmu_cfgmt_qmu_imem_time_age_interval_t +{ + ZXIC_UINT32 cfgmt_qmu_imem_time_age_interval; +}DPP_ETM_QMU_CFGMT_QMU_IMEM_TIME_AGE_INTERVAL_T; + +typedef struct dpp_etm_qmu_cfgmt_qmu_imem_qlen_age_thd_t +{ + ZXIC_UINT32 cfgmt_qmu_imem_qlen_age_thd; +}DPP_ETM_QMU_CFGMT_QMU_IMEM_QLEN_AGE_THD_T; + +typedef struct dpp_etm_qmu_cfgmt_imem_age_step_interval_t +{ + ZXIC_UINT32 cfgmt_imem_age_step_interval; +}DPP_ETM_QMU_CFGMT_IMEM_AGE_STEP_INTERVAL_T; + +typedef struct dpp_etm_qmu_cfgmt_qmu_ecc_bypass_read_t +{ + ZXIC_UINT32 cfgmt_qmu_ecc_bypass_read; +}DPP_ETM_QMU_CFGMT_QMU_ECC_BYPASS_READ_T; + +typedef struct dpp_etm_qmu_cfgmt_qmu_resp_stat_fc_en_t +{ + ZXIC_UINT32 cfgmt_qmu_resp_stat_fc_en; +}DPP_ETM_QMU_CFGMT_QMU_RESP_STAT_FC_EN_T; + +typedef struct dpp_etm_qmu_cfgmt_qmu_bank_xoff_pds_mode_t +{ + ZXIC_UINT32 cfgmt_qmu_bank_xoff_pds_mode; +}DPP_ETM_QMU_CFGMT_QMU_BANK_XOFF_PDS_MODE_T; + +typedef struct dpp_etm_qmu_cfgmt_qmu_stat_offset_t +{ + ZXIC_UINT32 cfgmt_qmu_stat_offset; +}DPP_ETM_QMU_CFGMT_QMU_STAT_OFFSET_T; + +typedef struct dpp_etm_qmu_fc_cnt_mode_t +{ + ZXIC_UINT32 fc_cnt_mode; +}DPP_ETM_QMU_FC_CNT_MODE_T; + +typedef struct dpp_etm_qmu_mmu_qmu_wr_fc_cnt_t +{ + ZXIC_UINT32 mmu_qmu_wr_fc_cnt; +}DPP_ETM_QMU_MMU_QMU_WR_FC_CNT_T; + +typedef struct dpp_etm_qmu_mmu_qmu_rd_fc_cnt_t +{ + ZXIC_UINT32 mmu_qmu_rd_fc_cnt; +}DPP_ETM_QMU_MMU_QMU_RD_FC_CNT_T; + +typedef struct dpp_etm_qmu_qmu_cgavd_fc_cnt_t +{ + ZXIC_UINT32 qmu_cgavd_fc_cnt; +}DPP_ETM_QMU_QMU_CGAVD_FC_CNT_T; + +typedef struct dpp_etm_qmu_cgavd_qmu_pkt_cnt_t +{ + ZXIC_UINT32 cgavd_qmu_pkt_cnt; +}DPP_ETM_QMU_CGAVD_QMU_PKT_CNT_T; + +typedef struct dpp_etm_qmu_cgavd_qmu_pktlen_all_t +{ + ZXIC_UINT32 cgavd_qmu_pktlen_all; +}DPP_ETM_QMU_CGAVD_QMU_PKTLEN_ALL_T; + +typedef struct dpp_etm_qmu_observe_portfc_spec_t +{ + ZXIC_UINT32 observe_portfc_spec; +}DPP_ETM_QMU_OBSERVE_PORTFC_SPEC_T; + +typedef struct dpp_etm_qmu_spec_lif_portfc_count_t +{ + ZXIC_UINT32 spec_lif_portfc_count; +}DPP_ETM_QMU_SPEC_LIF_PORTFC_COUNT_T; + +typedef struct dpp_etm_qmu_cfgmt_qmu_pfc_en_t +{ + ZXIC_UINT32 cfgmt_qmu_pfc_en; +}DPP_ETM_QMU_CFGMT_QMU_PFC_EN_T; + +typedef struct dpp_etm_qmu_cfgmt_qmu_pfc_mask_1_t +{ + ZXIC_UINT32 cfgmt_qmu_pfc_mask_1; +}DPP_ETM_QMU_CFGMT_QMU_PFC_MASK_1_T; + +typedef struct dpp_etm_qmu_cfgmt_qmu_pfc_mask_2_t +{ + ZXIC_UINT32 cfgmt_qmu_pfc_mask_2; +}DPP_ETM_QMU_CFGMT_QMU_PFC_MASK_2_T; + +typedef struct dpp_etm_cfgmt_chip_version_reg_t +{ + ZXIC_UINT32 chip_version_reg; + ZXIC_UINT32 chip_sub_reg; + ZXIC_UINT32 chip_type_reg; +}DPP_ETM_CFGMT_CHIP_VERSION_REG_T; + +typedef struct dpp_etm_cfgmt_chip_date_reg_t +{ + ZXIC_UINT32 chip_date_reg; +}DPP_ETM_CFGMT_CHIP_DATE_REG_T; + +typedef struct dpp_etm_cfgmt_cfgmt_crc_en_t +{ + ZXIC_UINT32 cfgmt_crc_en; +}DPP_ETM_CFGMT_CFGMT_CRC_EN_T; + +typedef struct dpp_etm_cfgmt_cfg_port_transfer_en_t +{ + ZXIC_UINT32 cfg_port_transfer_en; +}DPP_ETM_CFGMT_CFG_PORT_TRANSFER_EN_T; + +typedef struct dpp_etm_cfgmt_tm_sa_work_mode_t +{ + ZXIC_UINT32 tm_sa_work_mode; +}DPP_ETM_CFGMT_TM_SA_WORK_MODE_T; + +typedef struct dpp_etm_cfgmt_local_sa_id_t +{ + ZXIC_UINT32 local_sa_id; +}DPP_ETM_CFGMT_LOCAL_SA_ID_T; + +typedef struct dpp_etm_olif_olif_rdy_t +{ + ZXIC_UINT32 cfgmt_block_mode; + ZXIC_UINT32 cfgmt_count_overflow_mode; + ZXIC_UINT32 cfgmt_count_rd_mode; + ZXIC_UINT32 olif_rdy; +}DPP_ETM_OLIF_OLIF_RDY_T; + +typedef struct dpp_etm_olif_emem_prog_full_t +{ + ZXIC_UINT32 emem_prog_full_assert; + ZXIC_UINT32 emem_prog_full_negate; +}DPP_ETM_OLIF_EMEM_PROG_FULL_T; + +typedef struct dpp_etm_olif_port_order_fifo_full_t +{ + ZXIC_UINT32 port_order_fifo_full_assert; + ZXIC_UINT32 port_order_fifo_full_negate; +}DPP_ETM_OLIF_PORT_ORDER_FIFO_FULL_T; + +typedef struct dpp_etm_olif_olif_release_last_t +{ + ZXIC_UINT32 olif_release_last_addr; + ZXIC_UINT32 olif_release_last_bank; +}DPP_ETM_OLIF_OLIF_RELEASE_LAST_T; + +typedef struct dpp_etm_olif_olif_fifo_empty_state_t +{ + ZXIC_UINT32 qmu_para_fifo_empty; + ZXIC_UINT32 emem_empty; + ZXIC_UINT32 imem_empty; +}DPP_ETM_OLIF_OLIF_FIFO_EMPTY_STATE_T; + +typedef struct dpp_etm_olif_qmu_olif_release_fc_cnt_t +{ + ZXIC_UINT32 qmu_olif_release_fc_cnt; +}DPP_ETM_OLIF_QMU_OLIF_RELEASE_FC_CNT_T; + +typedef struct dpp_etm_olif_olif_qmu_link_fc_cnt_t +{ + ZXIC_UINT32 olif_qmu_link_fc_cnt; +}DPP_ETM_OLIF_OLIF_QMU_LINK_FC_CNT_T; + +typedef struct dpp_etm_olif_lif0_link_fc_cnt_t +{ + ZXIC_UINT32 lif0_link_fc_cnt; +}DPP_ETM_OLIF_LIF0_LINK_FC_CNT_T; + +typedef struct dpp_etm_olif_olif_tmmu_fc_cnt_t +{ + ZXIC_UINT32 olif_tmmu_fc_cnt; +}DPP_ETM_OLIF_OLIF_TMMU_FC_CNT_T; + +typedef struct dpp_etm_olif_olif_mmu_fc_cnt_t +{ + ZXIC_UINT32 olif_mmu_fc_cnt; +}DPP_ETM_OLIF_OLIF_MMU_FC_CNT_T; + +typedef struct dpp_etm_olif_olif_qmu_port_rdy_h_t +{ + ZXIC_UINT32 olif_qmu_port_rdy_h; +}DPP_ETM_OLIF_OLIF_QMU_PORT_RDY_H_T; + +typedef struct dpp_etm_olif_olif_qmu_port_rdy_l_t +{ + ZXIC_UINT32 olif_qmu_port_rdy_l; +}DPP_ETM_OLIF_OLIF_QMU_PORT_RDY_L_T; + +typedef struct dpp_etm_olif_lif0_port_rdy_h_t +{ + ZXIC_UINT32 lif0_port_rdy_h; +}DPP_ETM_OLIF_LIF0_PORT_RDY_H_T; + +typedef struct dpp_etm_olif_lif0_port_rdy_l_t +{ + ZXIC_UINT32 lif0_port_rdy_l; +}DPP_ETM_OLIF_LIF0_PORT_RDY_L_T; + +typedef struct dpp_etm_olif_qmu_olif_rd_sop_cnt_t +{ + ZXIC_UINT32 qmu_olif_rd_sop_cnt; +}DPP_ETM_OLIF_QMU_OLIF_RD_SOP_CNT_T; + +typedef struct dpp_etm_olif_qmu_olif_rd_eop_cnt_t +{ + ZXIC_UINT32 qmu_olif_rd_eop_cnt; +}DPP_ETM_OLIF_QMU_OLIF_RD_EOP_CNT_T; + +typedef struct dpp_etm_olif_qmu_olif_rd_vld_cnt_t +{ + ZXIC_UINT32 qmu_olif_rd_vld_cnt; +}DPP_ETM_OLIF_QMU_OLIF_RD_VLD_CNT_T; + +typedef struct dpp_etm_olif_qmu_olif_rd_blk_cnt_t +{ + ZXIC_UINT32 qmu_olif_rd_blk_cnt; +}DPP_ETM_OLIF_QMU_OLIF_RD_BLK_CNT_T; + +typedef struct dpp_etm_olif_mmu_tm_data_sop_cnt_t +{ + ZXIC_UINT32 mmu_tm_data_sop_cnt; +}DPP_ETM_OLIF_MMU_TM_DATA_SOP_CNT_T; + +typedef struct dpp_etm_olif_mmu_tm_data_eop_cnt_t +{ + ZXIC_UINT32 mmu_tm_data_eop_cnt; +}DPP_ETM_OLIF_MMU_TM_DATA_EOP_CNT_T; + +typedef struct dpp_etm_olif_mmu_tm_data_vld_cnt_t +{ + ZXIC_UINT32 mmu_tm_data_vld_cnt; +}DPP_ETM_OLIF_MMU_TM_DATA_VLD_CNT_T; + +typedef struct dpp_etm_olif_odma_tm_data_sop_cnt_t +{ + ZXIC_UINT32 odma_tm_data_sop_cnt; +}DPP_ETM_OLIF_ODMA_TM_DATA_SOP_CNT_T; + +typedef struct dpp_etm_olif_odma_tm_data_eop_cnt_t +{ + ZXIC_UINT32 odma_tm_data_eop_cnt; +}DPP_ETM_OLIF_ODMA_TM_DATA_EOP_CNT_T; + +typedef struct dpp_etm_olif_odma_tm_deq_vld_cnt_t +{ + ZXIC_UINT32 odma_tm_deq_vld_cnt; +}DPP_ETM_OLIF_ODMA_TM_DEQ_VLD_CNT_T; + +typedef struct dpp_etm_olif_olif_qmu_release_vld_cnt_t +{ + ZXIC_UINT32 olif_qmu_release_vld_cnt; +}DPP_ETM_OLIF_OLIF_QMU_RELEASE_VLD_CNT_T; + +typedef struct dpp_etm_olif_emem_dat_vld_cnt_t +{ + ZXIC_UINT32 emem_dat_vld_cnt; +}DPP_ETM_OLIF_EMEM_DAT_VLD_CNT_T; + +typedef struct dpp_etm_olif_imem_dat_vld_cnt_t +{ + ZXIC_UINT32 imem_dat_vld_cnt; +}DPP_ETM_OLIF_IMEM_DAT_VLD_CNT_T; + +typedef struct dpp_etm_olif_emem_dat_rd_cnt_t +{ + ZXIC_UINT32 emem_dat_rd_cnt; +}DPP_ETM_OLIF_EMEM_DAT_RD_CNT_T; + +typedef struct dpp_etm_olif_imem_dat_rd_cnt_t +{ + ZXIC_UINT32 imem_dat_rd_cnt; +}DPP_ETM_OLIF_IMEM_DAT_RD_CNT_T; + +typedef struct dpp_etm_olif_qmu_olif_rd_sop_emem_cnt_t +{ + ZXIC_UINT32 qmu_olif_rd_sop_emem_cnt; +}DPP_ETM_OLIF_QMU_OLIF_RD_SOP_EMEM_CNT_T; + +typedef struct dpp_etm_olif_qmu_olif_rd_vld_emem_cnt_t +{ + ZXIC_UINT32 qmu_olif_rd_vld_emem_cnt; +}DPP_ETM_OLIF_QMU_OLIF_RD_VLD_EMEM_CNT_T; + +typedef struct dpp_etm_olif_cpu_last_wr_addr_t +{ + ZXIC_UINT32 cpu_last_wr_addr; +}DPP_ETM_OLIF_CPU_LAST_WR_ADDR_T; + +typedef struct dpp_etm_olif_cpu_last_wr_data_t +{ + ZXIC_UINT32 cpu_last_wr_data; +}DPP_ETM_OLIF_CPU_LAST_WR_DATA_T; + +typedef struct dpp_etm_olif_cpu_last_rd_addr_t +{ + ZXIC_UINT32 cpu_last_rd_addr; +}DPP_ETM_OLIF_CPU_LAST_RD_ADDR_T; + +typedef struct dpp_etm_olif_qmu_olif_last_port_t +{ + ZXIC_UINT32 qmu_olif_last_port; +}DPP_ETM_OLIF_QMU_OLIF_LAST_PORT_T; + +typedef struct dpp_etm_olif_qmu_olif_last_addr_t +{ + ZXIC_UINT32 qmu_olif_last_addr; +}DPP_ETM_OLIF_QMU_OLIF_LAST_ADDR_T; + +typedef struct dpp_etm_olif_qmu_olif_last_bank_t +{ + ZXIC_UINT32 qmu_olif_last_bank; +}DPP_ETM_OLIF_QMU_OLIF_LAST_BANK_T; + +typedef struct dpp_etm_olif_tm_lif_byte_stat_t +{ + ZXIC_UINT32 tm_lif_byte_stat; +}DPP_ETM_OLIF_TM_LIF_BYTE_STAT_T; + +typedef struct dpp_etm_olif_tm_lif_err_stat_t +{ + ZXIC_UINT32 tm_lif_err_stat; +}DPP_ETM_OLIF_TM_LIF_ERR_STAT_T; + +typedef struct dpp_etm_cgavd_port_share_cnt_t +{ + ZXIC_UINT32 port_share_cnt; +}DPP_ETM_CGAVD_PORT_SHARE_CNT_T; + +typedef struct dpp_etm_cgavd_total_imem_cnt_t +{ + ZXIC_UINT32 total_imem_cnt; +}DPP_ETM_CGAVD_TOTAL_IMEM_CNT_T; + +typedef struct dpp_etm_cgavd_pp_q_len_t +{ + ZXIC_UINT32 pp_q_len; +}DPP_ETM_CGAVD_PP_Q_LEN_T; + +typedef struct dpp_etm_cgavd_sys_q_len_t +{ + ZXIC_UINT32 sys_q_len; +}DPP_ETM_CGAVD_SYS_Q_LEN_T; + +typedef struct dpp_etm_cgavd_cgavd_cfg_error_warning_t +{ + ZXIC_UINT32 error_correction_11; + ZXIC_UINT32 error_correction_10; + ZXIC_UINT32 error_correction_9; + ZXIC_UINT32 error_correction_8; + ZXIC_UINT32 error_correction_7; + ZXIC_UINT32 error_correction_6; + ZXIC_UINT32 error_correction5; + ZXIC_UINT32 error_correction_4; + ZXIC_UINT32 error_correction_3; + ZXIC_UINT32 error_correction_2; + ZXIC_UINT32 error_correction_1; + ZXIC_UINT32 error_correction_0; +}DPP_ETM_CGAVD_CGAVD_CFG_ERROR_WARNING_T; + +typedef struct dpp_etm_cgavd_mult_qlen_th_en_t +{ + ZXIC_UINT32 mult_qlen_th; +}DPP_ETM_CGAVD_MULT_QLEN_TH_EN_T; + +typedef struct dpp_etm_cgavd_mult_qlen_th_t +{ + ZXIC_UINT32 mult_qlen_th; +}DPP_ETM_CGAVD_MULT_QLEN_TH_T; + +typedef struct dpp_etm_cgavd_cgavd_cfg_move_t +{ + ZXIC_UINT32 cfgmt_sys_move_en; + ZXIC_UINT32 cfgmt_port_move_en; + ZXIC_UINT32 cfgmt_flow_move_en; +}DPP_ETM_CGAVD_CGAVD_CFG_MOVE_T; + +typedef struct dpp_etm_cgavd_cfgmt_total_th_t +{ + ZXIC_UINT32 cfgmt_total_th; +}DPP_ETM_CGAVD_CFGMT_TOTAL_TH_T; + +typedef struct dpp_etm_cgavd_cfgmt_port_share_th_t +{ + ZXIC_UINT32 cfgmt_port_share_th; +}DPP_ETM_CGAVD_CFGMT_PORT_SHARE_TH_T; + +typedef struct dpp_etm_cgavd_sa_unreach_state_t +{ + ZXIC_UINT32 sa_unreach_state; +}DPP_ETM_CGAVD_SA_UNREACH_STATE_T; + +typedef struct dpp_etm_cgavd_mv_port_th_t +{ + ZXIC_UINT32 port_th; +}DPP_ETM_CGAVD_MV_PORT_TH_T; + +typedef struct dpp_etm_cgavd_mv_drop_sp_th_t +{ + ZXIC_UINT32 mvdrop_sp_th; +}DPP_ETM_CGAVD_MV_DROP_SP_TH_T; + +typedef struct dpp_etm_cgavd_cgavd_state_warning_t +{ + ZXIC_UINT32 deq_q_num_warning; + ZXIC_UINT32 deq_pkt_len_warning; + ZXIC_UINT32 enq_pkt_dp_warning; + ZXIC_UINT32 unenq_q_num_warning; + ZXIC_UINT32 enq_q_num_warning; + ZXIC_UINT32 enq_pkt_len_warning; +}DPP_ETM_CGAVD_CGAVD_STATE_WARNING_T; + +typedef struct dpp_etm_cgavd_tmmu_cgavd_dma_fifo_cnt_t +{ + ZXIC_UINT32 tmmu_cgavd_dma_fifo_cnt; +}DPP_ETM_CGAVD_TMMU_CGAVD_DMA_FIFO_CNT_T; + +typedef struct dpp_etm_cgavd_tmmu_cgavd_dma_fifo_cnt_max_t +{ + ZXIC_UINT32 tmmu_cgavd_dma_fifo_cnt_max; +}DPP_ETM_CGAVD_TMMU_CGAVD_DMA_FIFO_CNT_MAX_T; + +typedef struct dpp_etm_cgavd_imem_total_cnt_t +{ + ZXIC_UINT32 imem_total_cnt; +}DPP_ETM_CGAVD_IMEM_TOTAL_CNT_T; + +typedef struct dpp_etm_cgavd_imem_total_cnt_max_t +{ + ZXIC_UINT32 imem_total_cnt_max; +}DPP_ETM_CGAVD_IMEM_TOTAL_CNT_MAX_T; + +typedef struct dpp_etm_cgavd_flow0_omem_cnt_t +{ + ZXIC_UINT32 flow0_omem_cnt; +}DPP_ETM_CGAVD_FLOW0_OMEM_CNT_T; + +typedef struct dpp_etm_cgavd_flow1_omem_cnt_t +{ + ZXIC_UINT32 flow1_omem_cnt; +}DPP_ETM_CGAVD_FLOW1_OMEM_CNT_T; + +typedef struct dpp_etm_cgavd_flow2_omem_cnt_t +{ + ZXIC_UINT32 flow2_omem_cnt; +}DPP_ETM_CGAVD_FLOW2_OMEM_CNT_T; + +typedef struct dpp_etm_cgavd_flow3_omem_cnt_t +{ + ZXIC_UINT32 flow3_omem_cnt; +}DPP_ETM_CGAVD_FLOW3_OMEM_CNT_T; + +typedef struct dpp_etm_cgavd_flow4_omem_cnt_t +{ + ZXIC_UINT32 flow4_omem_cnt; +}DPP_ETM_CGAVD_FLOW4_OMEM_CNT_T; + +typedef struct dpp_etm_cgavd_appoint_flow_num_message_1_t +{ + ZXIC_UINT32 appoint_flow_num_en_1; + ZXIC_UINT32 appoint_flow_num_1; +}DPP_ETM_CGAVD_APPOINT_FLOW_NUM_MESSAGE_1_T; + +typedef struct dpp_etm_cgavd_appoint_flow_num_message_2_t +{ + ZXIC_UINT32 appoint_flow_num_en_2; + ZXIC_UINT32 appoint_flow_num_2; +}DPP_ETM_CGAVD_APPOINT_FLOW_NUM_MESSAGE_2_T; + +typedef struct dpp_etm_cgavd_odma_cgavd_pkt_num_1_t +{ + ZXIC_UINT32 odma_cgavd_pkt_num_1; +}DPP_ETM_CGAVD_ODMA_CGAVD_PKT_NUM_1_T; + +typedef struct dpp_etm_cgavd_odma_cgavd_byte_num_1_t +{ + ZXIC_UINT32 odma_cgavd_byte_num_1; +}DPP_ETM_CGAVD_ODMA_CGAVD_BYTE_NUM_1_T; + +typedef struct dpp_etm_cgavd_cgavd_enqueue_pkt_num_1_t +{ + ZXIC_UINT32 cgavd_enqueue_pkt_num_1; +}DPP_ETM_CGAVD_CGAVD_ENQUEUE_PKT_NUM_1_T; + +typedef struct dpp_etm_cgavd_cgavd_dequeue_pkt_num_1_t +{ + ZXIC_UINT32 cgavd_dequeue_pkt_num_1; +}DPP_ETM_CGAVD_CGAVD_DEQUEUE_PKT_NUM_1_T; + +typedef struct dpp_etm_cgavd_cgavd_qmu_pkt_imem_num_1_t +{ + ZXIC_UINT32 cgavd_qmu_pkt_imem_num_1; +}DPP_ETM_CGAVD_CGAVD_QMU_PKT_IMEM_NUM_1_T; + +typedef struct dpp_etm_cgavd_cgavd_qmu_pkt_omem_num_1_t +{ + ZXIC_UINT32 cgavd_qmu_pkt_omem_num_1; +}DPP_ETM_CGAVD_CGAVD_QMU_PKT_OMEM_NUM_1_T; + +typedef struct dpp_etm_cgavd_cgavd_qmu_byte_imem_num_1_t +{ + ZXIC_UINT32 cgavd_qmu_byte_imem_1; +}DPP_ETM_CGAVD_CGAVD_QMU_BYTE_IMEM_NUM_1_T; + +typedef struct dpp_etm_cgavd_cgavd_qmu_byte_omem_num_1_t +{ + ZXIC_UINT32 cgavd_qmu_byte_omem_1; +}DPP_ETM_CGAVD_CGAVD_QMU_BYTE_OMEM_NUM_1_T; + +typedef struct dpp_etm_cgavd_cgavd_qmu_pkt_drop_num_1_t +{ + ZXIC_UINT32 cgavd_qmu_pkt_drop_num_1; +}DPP_ETM_CGAVD_CGAVD_QMU_PKT_DROP_NUM_1_T; + +typedef struct dpp_etm_cgavd_cgavd_qmu_byte_drop_num_1_t +{ + ZXIC_UINT32 cgavd_qmu_byte_drop_num_1; +}DPP_ETM_CGAVD_CGAVD_QMU_BYTE_DROP_NUM_1_T; + +typedef struct dpp_etm_cgavd_cgavd_qmu_forbid_drop_num_1_t +{ + ZXIC_UINT32 cgavd_qmu_forbid_drop_num_1; +}DPP_ETM_CGAVD_CGAVD_QMU_FORBID_DROP_NUM_1_T; + +typedef struct dpp_etm_cgavd_cgavd_qmu_flow_td_drop_num_1_t +{ + ZXIC_UINT32 cgavd_qmu_flow_td_drop_num_1; +}DPP_ETM_CGAVD_CGAVD_QMU_FLOW_TD_DROP_NUM_1_T; + +typedef struct dpp_etm_cgavd_cgavd_qmu_flow_wred_drop_num_1_t +{ + ZXIC_UINT32 cgavd_qmu_flow_wred_drop_num_1; +}DPP_ETM_CGAVD_CGAVD_QMU_FLOW_WRED_DROP_NUM_1_T; + +typedef struct dpp_etm_cgavd_cgavd_qmu_flow_wred_dp_drop_num_1_t +{ + ZXIC_UINT32 cgavd_qmu_flow_wred_dp_drop_num1; +}DPP_ETM_CGAVD_CGAVD_QMU_FLOW_WRED_DP_DROP_NUM_1_T; + +typedef struct dpp_etm_cgavd_cgavd_qmu_pp_td_num_1_t +{ + ZXIC_UINT32 cgavd_qmu_pp_td_num_1; +}DPP_ETM_CGAVD_CGAVD_QMU_PP_TD_NUM_1_T; + +typedef struct dpp_etm_cgavd_cgavd_qmu_pp_wred_drop_num_1_t +{ + ZXIC_UINT32 cgavd_qmu_pp_wred_drop_num_1; +}DPP_ETM_CGAVD_CGAVD_QMU_PP_WRED_DROP_NUM_1_T; + +typedef struct dpp_etm_cgavd_cgavd_qmu_pp_wred_dp_drop_num_1_t +{ + ZXIC_UINT32 cgavd_qmu_pp_wred_dp_drop_num1; +}DPP_ETM_CGAVD_CGAVD_QMU_PP_WRED_DP_DROP_NUM_1_T; + +typedef struct dpp_etm_cgavd_cgavd_qmu_sys_td_drop_num_1_t +{ + ZXIC_UINT32 cgavd_qmu_sys_td_drop_num_1; +}DPP_ETM_CGAVD_CGAVD_QMU_SYS_TD_DROP_NUM_1_T; + +typedef struct dpp_etm_cgavd_cgavd_qmu_sys_gred_drop_num_1_t +{ + ZXIC_UINT32 cgavd_qmu_sys_gred_drop_num_1; +}DPP_ETM_CGAVD_CGAVD_QMU_SYS_GRED_DROP_NUM_1_T; + +typedef struct dpp_etm_cgavd_cgavd_qmu_sys_gred_dp_drop_num1_t +{ + ZXIC_UINT32 cgavd_qmu_sys_gred_dp_drop_num1; +}DPP_ETM_CGAVD_CGAVD_QMU_SYS_GRED_DP_DROP_NUM1_T; + +typedef struct dpp_etm_cgavd_cgavd_qmu_sa_drop_num_1_t +{ + ZXIC_UINT32 cgavd_qmu_sa_drop_num_1; +}DPP_ETM_CGAVD_CGAVD_QMU_SA_DROP_NUM_1_T; + +typedef struct dpp_etm_cgavd_cgavd_qmu_move_drop_num_1_t +{ + ZXIC_UINT32 cgavd_qmu_move_drop_num_1; +}DPP_ETM_CGAVD_CGAVD_QMU_MOVE_DROP_NUM_1_T; + +typedef struct dpp_etm_cgavd_cgavd_qmu_tm_mult_drop_num_1_t +{ + ZXIC_UINT32 cgavd_qmu_tm_mult_drop_num_1; +}DPP_ETM_CGAVD_CGAVD_QMU_TM_MULT_DROP_NUM_1_T; + +typedef struct dpp_etm_cgavd_cgavd_qmu_tm_error_drop_num_1_t +{ + ZXIC_UINT32 cgavd_qmu_tm_error_drop_num_1; +}DPP_ETM_CGAVD_CGAVD_QMU_TM_ERROR_DROP_NUM_1_T; + +typedef struct dpp_etm_cgavd_odma_cgavd_pkt_num_2_t +{ + ZXIC_UINT32 odma_cgavd_pkt_num_2; +}DPP_ETM_CGAVD_ODMA_CGAVD_PKT_NUM_2_T; + +typedef struct dpp_etm_cgavd_odma_cgavd_byte_num_2_t +{ + ZXIC_UINT32 odma_cgavd_byte_num_2; +}DPP_ETM_CGAVD_ODMA_CGAVD_BYTE_NUM_2_T; + +typedef struct dpp_etm_cgavd_cgavd_enqueue_pkt_num_2_t +{ + ZXIC_UINT32 cgavd_enqueue_pkt_num_2; +}DPP_ETM_CGAVD_CGAVD_ENQUEUE_PKT_NUM_2_T; + +typedef struct dpp_etm_cgavd_cgavd_dequeue_pkt_num_2_t +{ + ZXIC_UINT32 cgavd_dequeue_pkt_num_2; +}DPP_ETM_CGAVD_CGAVD_DEQUEUE_PKT_NUM_2_T; + +typedef struct dpp_etm_cgavd_cgavd_qmu_pkt_imem_num_2_t +{ + ZXIC_UINT32 cgavd_qmu_pkt_imem_num_2; +}DPP_ETM_CGAVD_CGAVD_QMU_PKT_IMEM_NUM_2_T; + +typedef struct dpp_etm_cgavd_cgavd_qmu_pkt_omem_num_2_t +{ + ZXIC_UINT32 cgavd_qmu_pkt_omem_num_2; +}DPP_ETM_CGAVD_CGAVD_QMU_PKT_OMEM_NUM_2_T; + +typedef struct dpp_etm_cgavd_cgavd_qmu_byte_imem_num_2_t +{ + ZXIC_UINT32 cgavd_qmu_byte_imem_num_2; +}DPP_ETM_CGAVD_CGAVD_QMU_BYTE_IMEM_NUM_2_T; + +typedef struct dpp_etm_cgavd_cgavd_qmu_byte_omem_num_2_t +{ + ZXIC_UINT32 cgavd_qmu_byte_omem_num_2; +}DPP_ETM_CGAVD_CGAVD_QMU_BYTE_OMEM_NUM_2_T; + +typedef struct dpp_etm_cgavd_cgavd_qmu_pkt_drop_num_2_t +{ + ZXIC_UINT32 cgavd_qmu_pkt_drop_num_2; +}DPP_ETM_CGAVD_CGAVD_QMU_PKT_DROP_NUM_2_T; + +typedef struct dpp_etm_cgavd_cgavd_qmu_byte_drop_num_2_t +{ + ZXIC_UINT32 cgavd_qmu_byte_drop_num_2; +}DPP_ETM_CGAVD_CGAVD_QMU_BYTE_DROP_NUM_2_T; + +typedef struct dpp_etm_cgavd_cgavd_qmu_forbid_drop_num_2_t +{ + ZXIC_UINT32 cgavd_qmu_forbid_drop_num_2; +}DPP_ETM_CGAVD_CGAVD_QMU_FORBID_DROP_NUM_2_T; + +typedef struct dpp_etm_cgavd_cgavd_qmu_flow_td_drop_num_2_t +{ + ZXIC_UINT32 cgavd_qmu_flow_td_drop_num_2; +}DPP_ETM_CGAVD_CGAVD_QMU_FLOW_TD_DROP_NUM_2_T; + +typedef struct dpp_etm_cgavd_cgavd_qmu_flow_wred_drop_num_2_t +{ + ZXIC_UINT32 cgavd_qmu_flow_wred_drop_num_2; +}DPP_ETM_CGAVD_CGAVD_QMU_FLOW_WRED_DROP_NUM_2_T; + +typedef struct dpp_etm_cgavd_cgavd_qmu_flow_wred_dp_drop_num_2_t +{ + ZXIC_UINT32 cgavd_qmu_flow_wred_dp_drop_num_2; +}DPP_ETM_CGAVD_CGAVD_QMU_FLOW_WRED_DP_DROP_NUM_2_T; + +typedef struct dpp_etm_cgavd_cgavd_qmu_pp_td_num_2_t +{ + ZXIC_UINT32 cgavd_qmu_pp_td_num_2; +}DPP_ETM_CGAVD_CGAVD_QMU_PP_TD_NUM_2_T; + +typedef struct dpp_etm_cgavd_cgavd_qmu_pp_wred_drop_num_2_t +{ + ZXIC_UINT32 cgavd_qmu_pp_wred_drop_num_2; +}DPP_ETM_CGAVD_CGAVD_QMU_PP_WRED_DROP_NUM_2_T; + +typedef struct dpp_etm_cgavd_cgavd_qmu_pp_wred_dp_drop_num_2_t +{ + ZXIC_UINT32 cgavd_qmu_pp_wred_dp_drop_num_2; +}DPP_ETM_CGAVD_CGAVD_QMU_PP_WRED_DP_DROP_NUM_2_T; + +typedef struct dpp_etm_cgavd_cgavd_qmu_sys_td_drop_num_2_t +{ + ZXIC_UINT32 cgavd_qmu_sys_td_drop_num_2; +}DPP_ETM_CGAVD_CGAVD_QMU_SYS_TD_DROP_NUM_2_T; + +typedef struct dpp_etm_cgavd_cgavd_qmu_sys_gred_drop_num_2_t +{ + ZXIC_UINT32 cgavd_qmu_sys_gred_drop_num_2; +}DPP_ETM_CGAVD_CGAVD_QMU_SYS_GRED_DROP_NUM_2_T; + +typedef struct dpp_etm_cgavd_cgavd_qmu_sys_gred_dp_drop_num_2_t +{ + ZXIC_UINT32 cgavd_qmu_sys_gred_dp_drop_num_2; +}DPP_ETM_CGAVD_CGAVD_QMU_SYS_GRED_DP_DROP_NUM_2_T; + +typedef struct dpp_etm_cgavd_cgavd_qmu_sa_drop_num_2_t +{ + ZXIC_UINT32 cgavd_qmu_sa_drop_num_2; +}DPP_ETM_CGAVD_CGAVD_QMU_SA_DROP_NUM_2_T; + +typedef struct dpp_etm_cgavd_cgavd_qmu_move_drop_num_2_t +{ + ZXIC_UINT32 cgavd_qmu_move_drop_num_2; +}DPP_ETM_CGAVD_CGAVD_QMU_MOVE_DROP_NUM_2_T; + +typedef struct dpp_etm_cgavd_cgavd_qmu_tm_mult_drop_num_2_t +{ + ZXIC_UINT32 cgavd_qmu_tm_mult_drop_num_2; +}DPP_ETM_CGAVD_CGAVD_QMU_TM_MULT_DROP_NUM_2_T; + +typedef struct dpp_etm_cgavd_cgavd_qmu_tm_error_drop_num_2_t +{ + ZXIC_UINT32 cgavd_qmu_tm_error_drop_num_2; +}DPP_ETM_CGAVD_CGAVD_QMU_TM_ERROR_DROP_NUM_2_T; + +typedef struct dpp_etm_cgavd_move_flow_th_profile_t +{ + ZXIC_UINT32 move_drop_profile; +}DPP_ETM_CGAVD_MOVE_FLOW_TH_PROFILE_T; + +typedef struct dpp_etm_cgavd_move_flow_th_t +{ + ZXIC_UINT32 move_drop_flow_th; +}DPP_ETM_CGAVD_MOVE_FLOW_TH_T; + +typedef struct dpp_etm_tmmu_emem_pd_fifo_aful_th_t +{ + ZXIC_UINT32 emem_pd_fifo_aful_th; +}DPP_ETM_TMMU_EMEM_PD_FIFO_AFUL_TH_T; + +typedef struct dpp_etm_tmmu_dma_data_fifo_aful_th_t +{ + ZXIC_UINT32 dma_data_fifo_aful_th; +}DPP_ETM_TMMU_DMA_DATA_FIFO_AFUL_TH_T; + +typedef struct dpp_etm_tmmu_tmmu_states_0_t +{ + ZXIC_UINT32 tm_odma_pkt_rdy; + ZXIC_UINT32 dma_data_fifo_empty; + ZXIC_UINT32 imem_enq_rd_fifo_empty; + ZXIC_UINT32 imem_enq_drop_fifo_empty; + ZXIC_UINT32 imem_deq_rd_fifo_empty; + ZXIC_UINT32 imem_deq_drop_fifo_empty; + ZXIC_UINT32 wr_cmd_fifo_empty; + ZXIC_UINT32 cached_pd_fifo_empty; + ZXIC_UINT32 emem_pd_fifo_empty; + ZXIC_UINT32 pd_order_fifo_empty; + ZXIC_UINT32 odma_tm_data_rdy; + ZXIC_UINT32 odma_tm_discard_rdy; + ZXIC_UINT32 olif_tmmu_rdy; + ZXIC_UINT32 mmu_tm_cmd_wr_rdy; + ZXIC_UINT32 mmu_tm_data_wr_rdy; + ZXIC_UINT32 mmu_tm_rd_rdy; + ZXIC_UINT32 mmu_tm_sop_rd_rdy; + ZXIC_UINT32 qmu_tmmu_sop_data_rdy; + ZXIC_UINT32 tmmu_cmdsw_imem_release_rdy; + ZXIC_UINT32 imem_age_release_rdy; + ZXIC_UINT32 tmmu_qmu_wr_rdy; + ZXIC_UINT32 tmmu_qmu_rdy_7; + ZXIC_UINT32 tmmu_qmu_rdy_6; + ZXIC_UINT32 tmmu_qmu_rdy_5; + ZXIC_UINT32 tmmu_qmu_rdy_4; + ZXIC_UINT32 tmmu_qmu_rdy_3; + ZXIC_UINT32 tmmu_qmu_rdy_2; + ZXIC_UINT32 tmmu_qmu_rdy_1; + ZXIC_UINT32 tmmu_qmu_rdy_0; + ZXIC_UINT32 tmmu_qmu_rd_rdy; + ZXIC_UINT32 tmmu_qmu_sop_rd_rdy; +}DPP_ETM_TMMU_TMMU_STATES_0_T; + +typedef struct dpp_etm_tmmu_qmu_tmmu_wr_sop_cnt_t +{ + ZXIC_UINT32 qmu_tmmu_wr_sop_cnt; +}DPP_ETM_TMMU_QMU_TMMU_WR_SOP_CNT_T; + +typedef struct dpp_etm_tmmu_qmu_tmmu_wr_eop_cnt_t +{ + ZXIC_UINT32 qmu_tmmu_wr_eop_cnt; +}DPP_ETM_TMMU_QMU_TMMU_WR_EOP_CNT_T; + +typedef struct dpp_etm_tmmu_qmu_tmmu_wr_drop_cnt_t +{ + ZXIC_UINT32 qmu_tmmu_wr_drop_cnt; +}DPP_ETM_TMMU_QMU_TMMU_WR_DROP_CNT_T; + +typedef struct dpp_etm_tmmu_qmu_tmmu_wr_emem_cnt_t +{ + ZXIC_UINT32 qmu_tmmu_wr_emem_cnt; +}DPP_ETM_TMMU_QMU_TMMU_WR_EMEM_CNT_T; + +typedef struct dpp_etm_tmmu_qmu_tmmu_wr_imem_cnt_t +{ + ZXIC_UINT32 qmu_tmmu_wr_imem_cnt; +}DPP_ETM_TMMU_QMU_TMMU_WR_IMEM_CNT_T; + +typedef struct dpp_etm_tmmu_tmmu_mmu_wr_sop_cnt_t +{ + ZXIC_UINT32 tmmu_mmu_wr_sop_cnt; +}DPP_ETM_TMMU_TMMU_MMU_WR_SOP_CNT_T; + +typedef struct dpp_etm_tmmu_tmmu_mmu_wr_eop_cnt_t +{ + ZXIC_UINT32 tmmu_mmu_wr_eop_cnt; +}DPP_ETM_TMMU_TMMU_MMU_WR_EOP_CNT_T; + +typedef struct dpp_etm_tmmu_qmu_tmmu_rd_sop_cnt_t +{ + ZXIC_UINT32 qmu_tmmu_rd_sop_cnt; +}DPP_ETM_TMMU_QMU_TMMU_RD_SOP_CNT_T; + +typedef struct dpp_etm_tmmu_qmu_tmmu_rd_eop_cnt_t +{ + ZXIC_UINT32 qmu_tmmu_rd_eop_cnt; +}DPP_ETM_TMMU_QMU_TMMU_RD_EOP_CNT_T; + +typedef struct dpp_etm_tmmu_qmu_tmmu_rd_drop_cnt_t +{ + ZXIC_UINT32 qmu_tmmu_rd_drop_cnt; +}DPP_ETM_TMMU_QMU_TMMU_RD_DROP_CNT_T; + +typedef struct dpp_etm_tmmu_qmu_tmmu_rd_emem_cnt_t +{ + ZXIC_UINT32 qmu_tmmu_rd_emem_cnt; +}DPP_ETM_TMMU_QMU_TMMU_RD_EMEM_CNT_T; + +typedef struct dpp_etm_tmmu_qmu_tmmu_rd_imem_cnt_t +{ + ZXIC_UINT32 qmu_tmmu_rd_imem_cnt; +}DPP_ETM_TMMU_QMU_TMMU_RD_IMEM_CNT_T; + +typedef struct dpp_etm_tmmu_tmmu_mmu_rd_sop_cnt_t +{ + ZXIC_UINT32 tmmu_mmu_rd_sop_cnt; +}DPP_ETM_TMMU_TMMU_MMU_RD_SOP_CNT_T; + +typedef struct dpp_etm_tmmu_tmmu_mmu_rd_eop_cnt_t +{ + ZXIC_UINT32 tmmu_mmu_rd_eop_cnt; +}DPP_ETM_TMMU_TMMU_MMU_RD_EOP_CNT_T; + +typedef struct dpp_etm_tmmu_tmmu_odma_in_sop_cnt_t +{ + ZXIC_UINT32 tmmu_odma_in_sop_cnt; +}DPP_ETM_TMMU_TMMU_ODMA_IN_SOP_CNT_T; + +typedef struct dpp_etm_tmmu_tmmu_odma_in_eop_cnt_t +{ + ZXIC_UINT32 tmmu_odma_in_eop_cnt; +}DPP_ETM_TMMU_TMMU_ODMA_IN_EOP_CNT_T; + +typedef struct dpp_etm_tmmu_tmmu_odma_vld_cnt_t +{ + ZXIC_UINT32 tmmu_odma_vld_cnt; +}DPP_ETM_TMMU_TMMU_ODMA_VLD_CNT_T; + +typedef struct dpp_etm_tmmu_qmu_pd_in_cnt_t +{ + ZXIC_UINT32 qmu_pd_in_cnt; +}DPP_ETM_TMMU_QMU_PD_IN_CNT_T; + +typedef struct dpp_etm_tmmu_tmmu_pd_hit_cnt_t +{ + ZXIC_UINT32 tmmu_pd_hit_cnt; +}DPP_ETM_TMMU_TMMU_PD_HIT_CNT_T; + +typedef struct dpp_etm_tmmu_tmmu_pd_out_cnt_t +{ + ZXIC_UINT32 tmmu_pd_out_cnt; +}DPP_ETM_TMMU_TMMU_PD_OUT_CNT_T; + +typedef struct dpp_etm_tmmu_tmmu_wr_cmd_fifo_wr_cnt_t +{ + ZXIC_UINT32 tmmu_wr_cmd_fifo_wr_cnt; +}DPP_ETM_TMMU_TMMU_WR_CMD_FIFO_WR_CNT_T; + +typedef struct dpp_etm_tmmu_tmmu_imem_age_cnt_t +{ + ZXIC_UINT32 tmmu_imem_age_cnt; +}DPP_ETM_TMMU_TMMU_IMEM_AGE_CNT_T; + +typedef struct dpp_etm_tmmu_tmmu_cmdsch_rd_cnt_t +{ + ZXIC_UINT32 tmmu_cmdsch_rd_cnt; +}DPP_ETM_TMMU_TMMU_CMDSCH_RD_CNT_T; + +typedef struct dpp_etm_tmmu_tmmu_cmdsch_drop_cnt_t +{ + ZXIC_UINT32 tmmu_cmdsch_drop_cnt; +}DPP_ETM_TMMU_TMMU_CMDSCH_DROP_CNT_T; + +typedef struct dpp_etm_tmmu_tmmu_cmdsw_drop_cnt_t +{ + ZXIC_UINT32 tmmu_cmdsw_drop_cnt; +}DPP_ETM_TMMU_TMMU_CMDSW_DROP_CNT_T; + +typedef struct dpp_etm_tmmu_tmmu_odma_enq_rd_cnt_t +{ + ZXIC_UINT32 tmmu_odma_enq_rd_cnt; +}DPP_ETM_TMMU_TMMU_ODMA_ENQ_RD_CNT_T; + +typedef struct dpp_etm_tmmu_tmmu_odma_enq_drop_cnt_t +{ + ZXIC_UINT32 tmmu_odma_enq_drop_cnt; +}DPP_ETM_TMMU_TMMU_ODMA_ENQ_DROP_CNT_T; + +typedef struct dpp_etm_tmmu_tmmu_odma_imem_age_cnt_t +{ + ZXIC_UINT32 tmmu_odma_imem_age_cnt; +}DPP_ETM_TMMU_TMMU_ODMA_IMEM_AGE_CNT_T; + +typedef struct dpp_etm_tmmu_tmmu_odma_deq_rd_cnt_t +{ + ZXIC_UINT32 tmmu_odma_deq_rd_cnt; +}DPP_ETM_TMMU_TMMU_ODMA_DEQ_RD_CNT_T; + +typedef struct dpp_etm_tmmu_tmmu_odma_deq_drop_cnt_t +{ + ZXIC_UINT32 tmmu_odma_deq_drop_cnt; +}DPP_ETM_TMMU_TMMU_ODMA_DEQ_DROP_CNT_T; + +typedef struct dpp_etm_tmmu_olif_tmmu_xoff_cnt_t +{ + ZXIC_UINT32 olif_tmmu_xoff_cnt; +}DPP_ETM_TMMU_OLIF_TMMU_XOFF_CNT_T; + +typedef struct dpp_etm_tmmu_odma_tm_data_xoff_cnt_t +{ + ZXIC_UINT32 odma_tm_data_xoff_cnt; +}DPP_ETM_TMMU_ODMA_TM_DATA_XOFF_CNT_T; + +typedef struct dpp_etm_tmmu_tm_odma_pkt_xoff_cnt_t +{ + ZXIC_UINT32 tm_odma_pkt_xoff_cnt; +}DPP_ETM_TMMU_TM_ODMA_PKT_XOFF_CNT_T; + +typedef struct dpp_etm_tmmu_tm_state_3_t +{ + ZXIC_UINT32 tmmu_qmu_rdy_9; + ZXIC_UINT32 tmmu_qmu_rdy_8; +}DPP_ETM_TMMU_TM_STATE_3_T; + +typedef struct dpp_etm_tmmu_cfgmt_pd_cache_cmd_t +{ + ZXIC_UINT32 cfgmt_pd_cache_addr; +}DPP_ETM_TMMU_CFGMT_PD_CACHE_CMD_T; + +typedef struct dpp_etm_tmmu_cfgmt_pd_cache_rd_done_t +{ + ZXIC_UINT32 cfgmt_pd_cache_rd_done; +}DPP_ETM_TMMU_CFGMT_PD_CACHE_RD_DONE_T; + +typedef struct dpp_etm_tmmu_cfgmt_pd_cache_rd_data_0_t +{ + ZXIC_UINT32 cfgmt_pd_cache_rd_data_0; +}DPP_ETM_TMMU_CFGMT_PD_CACHE_RD_DATA_0_T; + +typedef struct dpp_etm_tmmu_cfgmt_pd_cache_rd_data_1_t +{ + ZXIC_UINT32 cfgmt_pd_cache_rd_data_1; +}DPP_ETM_TMMU_CFGMT_PD_CACHE_RD_DATA_1_T; + +typedef struct dpp_etm_tmmu_cfgmt_pd_cache_rd_data_2_t +{ + ZXIC_UINT32 cfgmt_pd_cache_rd_data_2; +}DPP_ETM_TMMU_CFGMT_PD_CACHE_RD_DATA_2_T; + +typedef struct dpp_etm_tmmu_cfgmt_pd_cache_rd_data_3_t +{ + ZXIC_UINT32 cfgmt_pd_cache_rd_data_3; +}DPP_ETM_TMMU_CFGMT_PD_CACHE_RD_DATA_3_T; + +typedef struct dpp_etm_tmmu_cfgmt_tmmu_to_odma_para_t +{ + ZXIC_UINT32 cfgmt_tmmu_to_odma_para; +}DPP_ETM_TMMU_CFGMT_TMMU_TO_ODMA_PARA_T; + +typedef struct dpp_etm_tmmu_cfgmt_dma_data_fifo_cnt_t +{ + ZXIC_UINT32 cfgmt_dma_data_fifo_cnt; +}DPP_ETM_TMMU_CFGMT_DMA_DATA_FIFO_CNT_T; + +typedef struct dpp_etm_tmmu_cfgmt_cache_tag_bit0_offset_t +{ + ZXIC_UINT32 cfgmt_cache_tag_bit0_offset; +}DPP_ETM_TMMU_CFGMT_CACHE_TAG_BIT0_OFFSET_T; + +typedef struct dpp_etm_tmmu_cfgmt_cache_tag_bit1_offset_t +{ + ZXIC_UINT32 cfgmt_cache_tag_bit1_offset; +}DPP_ETM_TMMU_CFGMT_CACHE_TAG_BIT1_OFFSET_T; + +typedef struct dpp_etm_tmmu_cfgmt_cache_tag_bit2_offset_t +{ + ZXIC_UINT32 cfgmt_cache_tag_bit2_offset; +}DPP_ETM_TMMU_CFGMT_CACHE_TAG_BIT2_OFFSET_T; + +typedef struct dpp_etm_tmmu_cfgmt_cache_tag_bit3_offset_t +{ + ZXIC_UINT32 cfgmt_cache_tag_bit3_offset; +}DPP_ETM_TMMU_CFGMT_CACHE_TAG_BIT3_OFFSET_T; + +typedef struct dpp_etm_tmmu_cfgmt_cache_tag_bit4_offset_t +{ + ZXIC_UINT32 cfgmt_cache_tag_bit4_offset; +}DPP_ETM_TMMU_CFGMT_CACHE_TAG_BIT4_OFFSET_T; + +typedef struct dpp_etm_tmmu_cfgmt_cache_tag_bit5_offset_t +{ + ZXIC_UINT32 cfgmt_cache_tag_bit5_offset; +}DPP_ETM_TMMU_CFGMT_CACHE_TAG_BIT5_OFFSET_T; + +typedef struct dpp_etm_tmmu_cfgmt_cache_index_bit0_offset_t +{ + ZXIC_UINT32 cfgmt_cache_index_bit0_offset; +}DPP_ETM_TMMU_CFGMT_CACHE_INDEX_BIT0_OFFSET_T; + +typedef struct dpp_etm_tmmu_cfgmt_cache_index_bit1_offset_t +{ + ZXIC_UINT32 cfgmt_cache_index_bit1_offset; +}DPP_ETM_TMMU_CFGMT_CACHE_INDEX_BIT1_OFFSET_T; + +typedef struct dpp_etm_tmmu_cfgmt_cache_index_bit2_offset_t +{ + ZXIC_UINT32 cfgmt_cache_index_bit2_offset; +}DPP_ETM_TMMU_CFGMT_CACHE_INDEX_BIT2_OFFSET_T; + +typedef struct dpp_etm_tmmu_cfgmt_cache_index_bit3_offset_t +{ + ZXIC_UINT32 cfgmt_cache_index_bit3_offset; +}DPP_ETM_TMMU_CFGMT_CACHE_INDEX_BIT3_OFFSET_T; + +typedef struct dpp_etm_tmmu_cfgmt_cache_index_bit4_offset_t +{ + ZXIC_UINT32 cfgmt_cache_index_bit4_offset; +}DPP_ETM_TMMU_CFGMT_CACHE_INDEX_BIT4_OFFSET_T; + +typedef struct dpp_etm_tmmu_cfgmt_cache_index_bit5_offset_t +{ + ZXIC_UINT32 cfgmt_cache_index_bit5_offset; +}DPP_ETM_TMMU_CFGMT_CACHE_INDEX_BIT5_OFFSET_T; + +typedef struct dpp_etm_tmmu_cfgmt_cache_index_bit6_offset_t +{ + ZXIC_UINT32 cfgmt_cache_index_bit6_offset; +}DPP_ETM_TMMU_CFGMT_CACHE_INDEX_BIT6_OFFSET_T; + +typedef struct dpp_etm_tmmu_cfgmt_cache_index_bit7_offset_t +{ + ZXIC_UINT32 cfgmt_cache_index_bit7_offset; +}DPP_ETM_TMMU_CFGMT_CACHE_INDEX_BIT7_OFFSET_T; + +typedef struct dpp_etm_tmmu_cfgmt_cache_index_bit8_offset_t +{ + ZXIC_UINT32 cfgmt_cache_index_bit8_offset; +}DPP_ETM_TMMU_CFGMT_CACHE_INDEX_BIT8_OFFSET_T; + +typedef struct dpp_etm_tmmu_cfgmt_cache_index_bit9_offset_t +{ + ZXIC_UINT32 cfgmt_cache_index_bit9_offset; +}DPP_ETM_TMMU_CFGMT_CACHE_INDEX_BIT9_OFFSET_T; + +typedef struct dpp_etm_tmmu_cfgmt_cache_index_bit10_offset_t +{ + ZXIC_UINT32 cfgmt_cache_index_bit10_offset; +}DPP_ETM_TMMU_CFGMT_CACHE_INDEX_BIT10_OFFSET_T; + +typedef struct dpp_etm_tmmu_cfgmt_cache_index_bit11_offset_t +{ + ZXIC_UINT32 cfgmt_cache_index_bit11_offset; +}DPP_ETM_TMMU_CFGMT_CACHE_INDEX_BIT11_OFFSET_T; + +typedef struct dpp_etm_tmmu_cfgmt_cache_index_bit12_offset_t +{ + ZXIC_UINT32 cfgmt_cache_index_bit12_offset; +}DPP_ETM_TMMU_CFGMT_CACHE_INDEX_BIT12_OFFSET_T; + +typedef struct dpp_etm_shap_bktfull_fifo_full_flagregister_t +{ + ZXIC_UINT32 bktfull_fifo_full_flag_core; +}DPP_ETM_SHAP_BKTFULL_FIFO_FULL_FLAGREGISTER_T; + +typedef struct dpp_etm_shap_fifo_full_regregister_t +{ + ZXIC_UINT32 fifo_full_reg; +}DPP_ETM_SHAP_FIFO_FULL_REGREGISTER_T; + +typedef struct dpp_etm_shap_fifo_empty_regregister_t +{ + ZXIC_UINT32 fifo_empty_reg; +}DPP_ETM_SHAP_FIFO_EMPTY_REGREGISTER_T; + +typedef struct dpp_etm_shap_fifo_almost_full_regregister_t +{ + ZXIC_UINT32 fifo_almost_full_reg; +}DPP_ETM_SHAP_FIFO_ALMOST_FULL_REGREGISTER_T; + +typedef struct dpp_etm_shap_fifo_almost_empty_regregister_t +{ + ZXIC_UINT32 fifo_almost_empty_reg; +}DPP_ETM_SHAP_FIFO_ALMOST_EMPTY_REGREGISTER_T; + +typedef struct dpp_etm_crdt_credit_space_select_t +{ + ZXIC_UINT32 credit_space_select; +}DPP_ETM_CRDT_CREDIT_SPACE_SELECT_T; + +typedef struct dpp_etm_crdt_stat_space_max_t +{ + ZXIC_UINT32 stat_space_max; +}DPP_ETM_CRDT_STAT_SPACE_MAX_T; + +typedef struct dpp_etm_crdt_stat_space_min_t +{ + ZXIC_UINT32 stat_space_min; +}DPP_ETM_CRDT_STAT_SPACE_MIN_T; + +typedef struct dpp_etm_crdt_stat_space_credit_t +{ + ZXIC_UINT32 stat_space_credit; +}DPP_ETM_CRDT_STAT_SPACE_CREDIT_T; + +typedef struct dpp_etm_crdt_stat_que_step8_credit_t +{ + ZXIC_UINT32 stat_que_step8_credit; +}DPP_ETM_CRDT_STAT_QUE_STEP8_CREDIT_T; + +typedef struct dpp_etm_crdt_special_que_t +{ + ZXIC_UINT32 special_que_id; +}DPP_ETM_CRDT_SPECIAL_QUE_T; + +typedef struct dpp_etm_crdt_special_que_credit_t +{ + ZXIC_UINT32 special_que_credit; +}DPP_ETM_CRDT_SPECIAL_QUE_CREDIT_T; + +typedef struct dpp_etm_crdt_lif_congest_credit_cnt_t +{ + ZXIC_UINT32 lif_congest_credit_cnt; +}DPP_ETM_CRDT_LIF_CONGEST_CREDIT_CNT_T; + +typedef struct dpp_etm_crdt_lif_port_congest_credit_cnt_t +{ + ZXIC_UINT32 lif_port_congest_credit_cnt; +}DPP_ETM_CRDT_LIF_PORT_CONGEST_CREDIT_CNT_T; + +typedef struct dpp_etm_crdt_crdt_congest_credit_cnt_t +{ + ZXIC_UINT32 crdt_congest_credit_cnt; +}DPP_ETM_CRDT_CRDT_CONGEST_CREDIT_CNT_T; + +typedef struct dpp_etm_crdt_crdt_port_congest_credit_cnt_t +{ + ZXIC_UINT32 crdt_port_congest_credit_cnt; +}DPP_ETM_CRDT_CRDT_PORT_CONGEST_CREDIT_CNT_T; + +typedef struct dpp_etm_crdt_congest_port_id_t +{ + ZXIC_UINT32 congest_port_id; +}DPP_ETM_CRDT_CONGEST_PORT_ID_T; + +typedef struct dpp_etm_crdt_dev_link_control_t +{ + ZXIC_UINT32 dev_link_control; +}DPP_ETM_CRDT_DEV_LINK_CONTROL_T; + +typedef struct dpp_etm_crdt_crdt_sa_port_rdy_t +{ + ZXIC_UINT32 crdt_sa_port_rdy; +}DPP_ETM_CRDT_CRDT_SA_PORT_RDY_T; + +typedef struct dpp_etm_crdt_crdt_congest_mode_select_t +{ + ZXIC_UINT32 crdt_congest_mode_selectr; +}DPP_ETM_CRDT_CRDT_CONGEST_MODE_SELECT_T; + +typedef struct dpp_etm_crdt_fifo_out_all_crs_normal_cnt_t +{ + ZXIC_UINT32 fifo_out_all_crs_normal_cnt; +}DPP_ETM_CRDT_FIFO_OUT_ALL_CRS_NORMAL_CNT_T; + +typedef struct dpp_etm_crdt_fifo_out_all_crs_off_cnt_t +{ + ZXIC_UINT32 fifo_out_all_crs_off_cnt; +}DPP_ETM_CRDT_FIFO_OUT_ALL_CRS_OFF_CNT_T; + +typedef struct dpp_etm_crdt_fifo_out_que_crs_normal_cnt_t +{ + ZXIC_UINT32 fifo_out_que_crs_normal_cnt; +}DPP_ETM_CRDT_FIFO_OUT_QUE_CRS_NORMAL_CNT_T; + +typedef struct dpp_etm_crdt_fifo_out_que_crs_off_cnt_t +{ + ZXIC_UINT32 fifo_out_que_crs_off_cnt; +}DPP_ETM_CRDT_FIFO_OUT_QUE_CRS_OFF_CNT_T; + +typedef struct dpp_etm_crdt_mode_add_60g_t +{ + ZXIC_UINT32 mode_add_60g; +}DPP_ETM_CRDT_MODE_ADD_60G_T; + +typedef struct dpp_etm_crdt_pp_token_add_t +{ + ZXIC_UINT32 pp_token_add_cir; +}DPP_ETM_CRDT_PP_TOKEN_ADD_T; + +typedef struct dpp_etm_crdt_pp_cir_token_total_dist_cnt_t +{ + ZXIC_UINT32 pp_cir_token_total_dist_counter; +}DPP_ETM_CRDT_PP_CIR_TOKEN_TOTAL_DIST_CNT_T; + +typedef struct dpp_etm_crdt_pp_cir_token_total_dec_cnt_t +{ + ZXIC_UINT32 pp_cir_token_total_dec_counter; +}DPP_ETM_CRDT_PP_CIR_TOKEN_TOTAL_DEC_CNT_T; + +typedef struct dpp_etm_crdt_dev_credit_cnt_t +{ + ZXIC_UINT32 dev_credit_cnt; +}DPP_ETM_CRDT_DEV_CREDIT_CNT_T; + +typedef struct dpp_etm_crdt_no_credit_cnt1_t +{ + ZXIC_UINT32 no_credit_cnt1; +}DPP_ETM_CRDT_NO_CREDIT_CNT1_T; + +typedef struct dpp_etm_crdt_no_credit_cnt2_t +{ + ZXIC_UINT32 no_credit_cnt2; +}DPP_ETM_CRDT_NO_CREDIT_CNT2_T; + +typedef struct dpp_etm_crdt_asm_interval_0_cfg_t +{ + ZXIC_UINT32 asm_interval_0_cfg; +}DPP_ETM_CRDT_ASM_INTERVAL_0_CFG_T; + +typedef struct dpp_etm_crdt_asm_interval_1_cfg_t +{ + ZXIC_UINT32 asm_interval_1_cfg; +}DPP_ETM_CRDT_ASM_INTERVAL_1_CFG_T; + +typedef struct dpp_etm_crdt_asm_interval_2_cfg_t +{ + ZXIC_UINT32 asm_interval_2_cfg; +}DPP_ETM_CRDT_ASM_INTERVAL_2_CFG_T; + +typedef struct dpp_etm_crdt_asm_interval_3_cfg_t +{ + ZXIC_UINT32 asm_interval_3_cfg; +}DPP_ETM_CRDT_ASM_INTERVAL_3_CFG_T; + +typedef struct dpp_etm_crdt_asm_interval_4_cfg_t +{ + ZXIC_UINT32 asm_interval_4_cfg; +}DPP_ETM_CRDT_ASM_INTERVAL_4_CFG_T; + +typedef struct dpp_etm_crdt_asm_interval_5cfg_t +{ + ZXIC_UINT32 asm_interval_5_cfg; +}DPP_ETM_CRDT_ASM_INTERVAL_5CFG_T; + +typedef struct dpp_etm_crdt_asm_interval_6_cfg_t +{ + ZXIC_UINT32 asm_interval_6_cfg; +}DPP_ETM_CRDT_ASM_INTERVAL_6_CFG_T; + +typedef struct dpp_etm_crdt_asm_interval_7_cfg_t +{ + ZXIC_UINT32 asm_interval_7_cfg; +}DPP_ETM_CRDT_ASM_INTERVAL_7_CFG_T; + +typedef struct dpp_etm_crdt_crdt_total_congest_mode_cfg_t +{ + ZXIC_UINT32 crdt_total_congest_mode_cfg; +}DPP_ETM_CRDT_CRDT_TOTAL_CONGEST_MODE_CFG_T; + +typedef struct dpp_etm_crdt_rci_fifo_ini_deep_cfg_t +{ + ZXIC_UINT32 rci_fifo_ini_deep_cfg; +}DPP_ETM_CRDT_RCI_FIFO_INI_DEEP_CFG_T; + +typedef struct dpp_etm_crdt_crdt_ecc_t +{ + ZXIC_UINT32 seinfo_wfq_single_ecc_err; + ZXIC_UINT32 seinfo_wfq_double_ecc_err; + ZXIC_UINT32 seinfo_fq_single_ecc_err; + ZXIC_UINT32 seinfo_fq_double_ecc_err; + ZXIC_UINT32 ecc_bypass; +}DPP_ETM_CRDT_CRDT_ECC_T; + +typedef struct dpp_etm_crdt_ucn_asm_rdy_shield_en_t +{ + ZXIC_UINT32 ucn_rdy_shield_en; + ZXIC_UINT32 asm_rdy_shield_en; +}DPP_ETM_CRDT_UCN_ASM_RDY_SHIELD_EN_T; + +typedef struct dpp_etm_crdt_ucn_asm_rdy_t +{ + ZXIC_UINT32 ucn_rdy; + ZXIC_UINT32 asm_rdy; +}DPP_ETM_CRDT_UCN_ASM_RDY_T; + +typedef struct dpp_etm_crdt_rci_grade_t +{ + ZXIC_UINT32 rci_grade; +}DPP_ETM_CRDT_RCI_GRADE_T; + +typedef struct dpp_etm_crdt_crdt_rci_value_r_t +{ + ZXIC_UINT32 crdt_rci_value_r; +}DPP_ETM_CRDT_CRDT_RCI_VALUE_R_T; + +typedef struct dpp_etm_crdt_crdt_interval_now_t +{ + ZXIC_UINT32 crdt_interval_now; +}DPP_ETM_CRDT_CRDT_INTERVAL_NOW_T; + +typedef struct dpp_etm_crdt_crs_sheild_flow_id_cfg_t +{ + ZXIC_UINT32 crs_sheild_flow_id_cfg; +}DPP_ETM_CRDT_CRS_SHEILD_FLOW_ID_CFG_T; + +typedef struct dpp_etm_crdt_crs_sheild_en_cfg_t +{ + ZXIC_UINT32 crs_sheild_en_cfg; +}DPP_ETM_CRDT_CRS_SHEILD_EN_CFG_T; + +typedef struct dpp_etm_crdt_crs_sheild_value_cfg_t +{ + ZXIC_UINT32 crs_sheild_value_cfg; +}DPP_ETM_CRDT_CRS_SHEILD_VALUE_CFG_T; + +typedef struct dpp_etm_crdt_test_token_calc_ctrl_t +{ + ZXIC_UINT32 test_token_calc_state; + ZXIC_UINT32 test_token_calc_trigger; +}DPP_ETM_CRDT_TEST_TOKEN_CALC_CTRL_T; + +typedef struct dpp_etm_crdt_test_token_sample_cycle_num_t +{ + ZXIC_UINT32 sample_cycle_num; +}DPP_ETM_CRDT_TEST_TOKEN_SAMPLE_CYCLE_NUM_T; + +typedef struct dpp_etm_crdt_q_state_0_7_t +{ + ZXIC_UINT32 q_token_state_7; + ZXIC_UINT32 q_token_state_6; + ZXIC_UINT32 q_token_state_5; + ZXIC_UINT32 q_token_state_4; + ZXIC_UINT32 q_token_state_3; + ZXIC_UINT32 q_token_state_2; + ZXIC_UINT32 q_token_state_1; + ZXIC_UINT32 q_token_state_0; +}DPP_ETM_CRDT_Q_STATE_0_7_T; + +typedef struct dpp_etm_crdt_q_state_8_15_t +{ + ZXIC_UINT32 q_token_state_15; + ZXIC_UINT32 q_token_state_14; + ZXIC_UINT32 q_token_state_13; + ZXIC_UINT32 q_token_state_12; + ZXIC_UINT32 q_token_state_11; + ZXIC_UINT32 q_token_state_10; + ZXIC_UINT32 q_token_state_9; + ZXIC_UINT32 q_token_state_8; +}DPP_ETM_CRDT_Q_STATE_8_15_T; + +typedef struct dpp_etm_qmu_csw_csch_rd_cmd_cnt_t +{ + ZXIC_UINT32 csw_csch_rd_cmd_cnt; +}DPP_ETM_QMU_CSW_CSCH_RD_CMD_CNT_T; + +typedef struct dpp_etm_qmu_csw_csch_rd_sop_cnt_t +{ + ZXIC_UINT32 csw_csch_rd_sop_cnt; +}DPP_ETM_QMU_CSW_CSCH_RD_SOP_CNT_T; + +typedef struct dpp_etm_qmu_csw_csch_rd_eop_cnt_t +{ + ZXIC_UINT32 csw_csch_rd_eop_cnt; +}DPP_ETM_QMU_CSW_CSCH_RD_EOP_CNT_T; + +typedef struct dpp_etm_qmu_csw_csch_rd_drop_cnt_t +{ + ZXIC_UINT32 csw_csch_rd_drop_cnt; +}DPP_ETM_QMU_CSW_CSCH_RD_DROP_CNT_T; + +typedef struct dpp_etm_qmu_csch_mmu_rd_cmd_cnt_t +{ + ZXIC_UINT32 csch_mmu_rd_cmd_cnt; +}DPP_ETM_QMU_CSCH_MMU_RD_CMD_CNT_T; + +typedef struct dpp_etm_qmu_csch_mmu_rd_sop_cnt_t +{ + ZXIC_UINT32 csch_mmu_rd_sop_cnt; +}DPP_ETM_QMU_CSCH_MMU_RD_SOP_CNT_T; + +typedef struct dpp_etm_qmu_csch_mmu_rd_eop_cnt_t +{ + ZXIC_UINT32 csch_mmu_rd_eop_cnt; +}DPP_ETM_QMU_CSCH_MMU_RD_EOP_CNT_T; + +typedef struct dpp_etm_qmu_csch_mmu_rd_drop_cnt_t +{ + ZXIC_UINT32 csch_mmu_rd_drop_cnt; +}DPP_ETM_QMU_CSCH_MMU_RD_DROP_CNT_T; + +typedef struct dpp_etm_qmu_qcfg_qsch_crs_filter_t +{ + ZXIC_UINT32 qcfg_qsch_crs_filter; +}DPP_ETM_QMU_QCFG_QSCH_CRS_FILTER_T; + +typedef struct dpp_etm_qmu_qcfg_qsch_crs_force_en_t +{ + ZXIC_UINT32 qcfg_qsch_crs_force_en; +}DPP_ETM_QMU_QCFG_QSCH_CRS_FORCE_EN_T; + +typedef struct dpp_etm_qmu_qcfg_qsch_crs_force_qnum_t +{ + ZXIC_UINT32 qcfg_qsch_crs_force_qnum; +}DPP_ETM_QMU_QCFG_QSCH_CRS_FORCE_QNUM_T; + +typedef struct dpp_etm_qmu_qcfg_qsch_crs_force_crs_t +{ + ZXIC_UINT32 qcfg_qsch_crs_force_crs; +}DPP_ETM_QMU_QCFG_QSCH_CRS_FORCE_CRS_T; + +typedef struct dpp_etm_qmu_cfgmt_oshp_sgmii_shap_mode_t +{ + ZXIC_UINT32 cfgmt_oshp_sgmii_shap_mode; +}DPP_ETM_QMU_CFGMT_OSHP_SGMII_SHAP_MODE_T; + +typedef struct dpp_etm_qmu_cfgmt_qmu_sashap_en_t +{ + ZXIC_UINT32 cfgmt_qmu_sashap_en; +}DPP_ETM_QMU_CFGMT_QMU_SASHAP_EN_T; + +typedef struct dpp_etm_qmu_cfgmt_sashap_token_max_t +{ + ZXIC_UINT32 cfgmt_sashap_token_max; +}DPP_ETM_QMU_CFGMT_SASHAP_TOKEN_MAX_T; + +typedef struct dpp_etm_qmu_cfgmt_sashap_token_min_t +{ + ZXIC_UINT32 cfgmt_sashap_token_min; +}DPP_ETM_QMU_CFGMT_SASHAP_TOKEN_MIN_T; + +typedef struct dpp_etm_qmu_cfg_qsch_q3lbaddrate_t +{ + ZXIC_UINT32 cfg_qsch_q3lbaddrate; +}DPP_ETM_QMU_CFG_QSCH_Q3LBADDRATE_T; + +typedef struct dpp_etm_qmu_cfg_qsch_q012lbaddrate_t +{ + ZXIC_UINT32 cfg_qsch_q012lbaddrate; +}DPP_ETM_QMU_CFG_QSCH_Q012LBADDRATE_T; + +typedef struct dpp_etm_qmu_cfg_qsch_q3creditlbmaxcnt_t +{ + ZXIC_UINT32 cfg_qsch_q3creditlbmaxcnt; +}DPP_ETM_QMU_CFG_QSCH_Q3CREDITLBMAXCNT_T; + +typedef struct dpp_etm_qmu_cfg_qsch_q012creditlbmaxcnt_t +{ + ZXIC_UINT32 cfg_qsch_q012creditlbmaxcnt; +}DPP_ETM_QMU_CFG_QSCH_Q012CREDITLBMAXCNT_T; + +typedef struct dpp_etm_qmu_cfg_qsch_mul_token_gen_num_t +{ + ZXIC_UINT32 cfg_qsch_mul_token_gen_num; +}DPP_ETM_QMU_CFG_QSCH_MUL_TOKEN_GEN_NUM_T; + +typedef struct dpp_etm_qmu_cfg_qsch_q3_credit_lb_control_en_t +{ + ZXIC_UINT32 cfg_qsch_q3_credit_lb_control_en; +}DPP_ETM_QMU_CFG_QSCH_Q3_CREDIT_LB_CONTROL_EN_T; + +typedef struct dpp_etm_qmu_cfg_qsch_q012_credit_lb_control_en_t +{ + ZXIC_UINT32 cfg_qsch_q012_credit_lb_control_en; +}DPP_ETM_QMU_CFG_QSCH_Q012_CREDIT_LB_CONTROL_EN_T; + +typedef struct dpp_etm_qmu_cfg_qsch_sp_dwrr_en_t +{ + ZXIC_UINT32 cfg_qsch_sp_dwrr_en; +}DPP_ETM_QMU_CFG_QSCH_SP_DWRR_EN_T; + +typedef struct dpp_etm_qmu_cfg_qsch_q01_attach_en_t +{ + ZXIC_UINT32 cfg_qsch_q01_attach_en; +}DPP_ETM_QMU_CFG_QSCH_Q01_ATTACH_EN_T; + +typedef struct dpp_etm_qmu_cfg_qsch_w0_t +{ + ZXIC_UINT32 cfg_qsch_w0; +}DPP_ETM_QMU_CFG_QSCH_W0_T; + +typedef struct dpp_etm_qmu_cfg_qsch_w1_t +{ + ZXIC_UINT32 cfg_qsch_w1; +}DPP_ETM_QMU_CFG_QSCH_W1_T; + +typedef struct dpp_etm_qmu_cfg_qsch_w2_t +{ + ZXIC_UINT32 cfg_qsch_w2; +}DPP_ETM_QMU_CFG_QSCH_W2_T; + +typedef struct dpp_etm_qmu_cfg_qsch_lkybktmaxcnt1_t +{ + ZXIC_UINT32 cfg_qsch_lkybktmaxcnt1; +}DPP_ETM_QMU_CFG_QSCH_LKYBKTMAXCNT1_T; + +typedef struct dpp_etm_qmu_cfg_qsch_lkybktmaxcnt2_t +{ + ZXIC_UINT32 cfg_qsch_lkybktmaxcnt2; +}DPP_ETM_QMU_CFG_QSCH_LKYBKTMAXCNT2_T; + +typedef struct dpp_etm_qmu_cfg_qsch_lkybktdcrrate1_t +{ + ZXIC_UINT32 cfg_qsch_lkybktdcrrate1; +}DPP_ETM_QMU_CFG_QSCH_LKYBKTDCRRATE1_T; + +typedef struct dpp_etm_qmu_cfg_qsch_lkybktdcrrate2_t +{ + ZXIC_UINT32 cfg_qsch_lkybktdcrrate2; +}DPP_ETM_QMU_CFG_QSCH_LKYBKTDCRRATE2_T; + +typedef struct dpp_etm_qmu_cfg_qsch_lkybktdcrrate3_t +{ + ZXIC_UINT32 cfg_qsch_lkybktdcrrate3; +}DPP_ETM_QMU_CFG_QSCH_LKYBKTDCRRATE3_T; + +typedef struct dpp_etm_qmu_cfg_qsch_lkybktmaxcnt3_t +{ + ZXIC_UINT32 cfg_qsch_lkybktmaxcnt3; +}DPP_ETM_QMU_CFG_QSCH_LKYBKTMAXCNT3_T; + +typedef struct dpp_etm_qmu_cfg_qsch_qmu_mul_auto_sa_version_t +{ + ZXIC_UINT32 cfg_qsch_qmu_mul_auto_sa_version; +}DPP_ETM_QMU_CFG_QSCH_QMU_MUL_AUTO_SA_VERSION_T; + +typedef struct dpp_etm_qmu_cfg_qsch_sa_credit_value_0_t +{ + ZXIC_UINT32 cfg_qsch_sa_credit_value_0; +}DPP_ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_0_T; + +typedef struct dpp_etm_qmu_cfg_qsch_sa_credit_value_1_t +{ + ZXIC_UINT32 cfg_qsch_sa_credit_value_1; +}DPP_ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_1_T; + +typedef struct dpp_etm_qmu_cfg_qsch_sa_credit_value_2_t +{ + ZXIC_UINT32 cfg_qsch_sa_credit_value_2; +}DPP_ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_2_T; + +typedef struct dpp_etm_qmu_cfg_qsch_sa_credit_value_3_t +{ + ZXIC_UINT32 cfg_qsch_sa_credit_value_3; +}DPP_ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_3_T; + +typedef struct dpp_etm_qmu_cfg_qsch_sa_credit_value_4_t +{ + ZXIC_UINT32 cfg_qsch_sa_credit_value_4; +}DPP_ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_4_T; + +typedef struct dpp_etm_qmu_cfg_qsch_sa_credit_value_5_t +{ + ZXIC_UINT32 cfg_qsch_sa_credit_value_5; +}DPP_ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_5_T; + +typedef struct dpp_etm_qmu_cfg_qsch_sa_credit_value_6_t +{ + ZXIC_UINT32 cfg_qsch_sa_credit_value_6; +}DPP_ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_6_T; + +typedef struct dpp_etm_qmu_cfg_qsch_sa_credit_value_7_t +{ + ZXIC_UINT32 cfg_qsch_sa_credit_value_7; +}DPP_ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_7_T; + +typedef struct dpp_etm_qmu_cfg_qsch_remote_credit_fifo_almost_full_th_t +{ + ZXIC_UINT32 cfg_qsch_remote_credit_fifo_almost_full_th; +}DPP_ETM_QMU_CFG_QSCH_REMOTE_CREDIT_FIFO_ALMOST_FULL_TH_T; + +typedef struct dpp_etm_qmu_cfg_qsch_auto_credit_fifo_almost_full_th_t +{ + ZXIC_UINT32 cfg_qsch_auto_credit_fifo_almost_full_th; +}DPP_ETM_QMU_CFG_QSCH_AUTO_CREDIT_FIFO_ALMOST_FULL_TH_T; + +typedef struct dpp_etm_qmu_cfg_qsch_q3_credit_fifo_almost_full_th_t +{ + ZXIC_UINT32 cfg_qsch_q3_credit_fifo_almost_full_th; +}DPP_ETM_QMU_CFG_QSCH_Q3_CREDIT_FIFO_ALMOST_FULL_TH_T; + +typedef struct dpp_etm_qmu_cfg_qsch_q012_credit_fifo_almost_full_th_t +{ + ZXIC_UINT32 cfg_qsch_q012_credit_fifo_almost_full_th; +}DPP_ETM_QMU_CFG_QSCH_Q012_CREDIT_FIFO_ALMOST_FULL_TH_T; + +typedef struct dpp_etm_qmu_cfg_qsch_mul_fc_res_en_t +{ + ZXIC_UINT32 cfg_qsch_mul_fc_res_en; +}DPP_ETM_QMU_CFG_QSCH_MUL_FC_RES_EN_T; + +typedef struct dpp_etm_qmu_cfgmt_mul_ovf_udf_flg_query_t +{ + ZXIC_UINT32 qsch_cfg_remote_credit_fifo_full; + ZXIC_UINT32 qsch_cfg_remote_credit_fifo_empty; + ZXIC_UINT32 qsch_cfg_remote_credit_fifo_overflow; + ZXIC_UINT32 qsch_cfg_remote_credit_fifo_underflow; + ZXIC_UINT32 qsch_cfg_auto_credit_fifo_full; + ZXIC_UINT32 qsch_cfg_auto_credit_fifo_empty; + ZXIC_UINT32 qsch_cfg_auto_credit_fifo_overflow; + ZXIC_UINT32 qsch_cfg_auto_credit_fifo_underflow; + ZXIC_UINT32 qsch_cfg_q3_credit_fifo_full; + ZXIC_UINT32 qsch_cfg_q3_credit_fifo_empty; + ZXIC_UINT32 qsch_cfg_q3_credit_fifo_overflow; + ZXIC_UINT32 qsch_cfg_q3_credit_fifo_underflow; + ZXIC_UINT32 qsch_cfg_q012_credit_fifo_full; + ZXIC_UINT32 qsch_cfg_q012_credit_fifo_empty; + ZXIC_UINT32 qsch_cfg_q012_credit_fifo_overflow; + ZXIC_UINT32 qsch_cfg_q012_credit_fifo_underflow; + ZXIC_UINT32 qsch_cfg_lkybktoverflow1; + ZXIC_UINT32 qsch_cfg_lkybktoverflow2; + ZXIC_UINT32 qsch_cfg_lkybktoverflow3; +}DPP_ETM_QMU_CFGMT_MUL_OVF_UDF_FLG_QUERY_T; + +typedef struct dpp_etm_qmu_cfgmt_mul_cng_flg_query_t +{ + ZXIC_UINT32 qsch_cfg_q3cngflag; + ZXIC_UINT32 qsch_cfg_q012cngflag; + ZXIC_UINT32 qsch_cfg_cngflag1; + ZXIC_UINT32 qsch_cfg_cngflag2; + ZXIC_UINT32 qsch_cfg_cngflag3; +}DPP_ETM_QMU_CFGMT_MUL_CNG_FLG_QUERY_T; + +typedef struct dpp_etm_qmu_qsch_cfg_lkybktval1_t +{ + ZXIC_UINT32 qsch_cfg_lkybktval1; +}DPP_ETM_QMU_QSCH_CFG_LKYBKTVAL1_T; + +typedef struct dpp_etm_qmu_qsch_cfg_lkybktval2_t +{ + ZXIC_UINT32 qsch_cfg_lkybktval2; +}DPP_ETM_QMU_QSCH_CFG_LKYBKTVAL2_T; + +typedef struct dpp_etm_qmu_qsch_cfg_lkybktval3_t +{ + ZXIC_UINT32 qsch_cfg_lkybktval3; +}DPP_ETM_QMU_QSCH_CFG_LKYBKTVAL3_T; + +typedef struct dpp_etm_qmu_qsch_cfg_q3lbval_t +{ + ZXIC_UINT32 qsch_cfg_q3lbval; +}DPP_ETM_QMU_QSCH_CFG_Q3LBVAL_T; + +typedef struct dpp_etm_qmu_qsch_cfg_q012lbval_t +{ + ZXIC_UINT32 qsch_cfg_q012lbval; +}DPP_ETM_QMU_QSCH_CFG_Q012LBVAL_T; + +typedef struct dpp_etm_qmu_qlist_cfgmt_ram_ecc_err2_t +{ + ZXIC_UINT32 qlist_imem_pd_ram_single_ecc_err; + ZXIC_UINT32 qlist_imem_pd_ram_double_ecc_err; + ZXIC_UINT32 qlist_imem_up_ptr_ram_single_ecc_err; + ZXIC_UINT32 qlist_imem_up_ptr_ram_double_ecc_err; + ZXIC_UINT32 qlist_imem_down_ptr_ram_single_ecc_err; + ZXIC_UINT32 qlist_imem_down_ptr_ram_double_ecc_err; + ZXIC_UINT32 cmdsw_sop_fifo_single_ecc_err; + ZXIC_UINT32 cmdsw_sop_fifo_double_ecc_err; + ZXIC_UINT32 cmdsw_nsop_fifo_single_ecc_err; + ZXIC_UINT32 cmdsw_nsop_fifo_double_ecc_err; + ZXIC_UINT32 cmdsw_mmudat_fifo_single_ecc_err; + ZXIC_UINT32 cmdsw_mmudat_fifo_double_ecc_err; + ZXIC_UINT32 qlist_rd_release_fwft_single_ecc_err; + ZXIC_UINT32 qlist_rd_release_fwft_double_ecc_err; + ZXIC_UINT32 qlist_drop_imem_fwft_single_ecc_err; + ZXIC_UINT32 qlist_drop_imem_fwft_double_ecc_err; +}DPP_ETM_QMU_QLIST_CFGMT_RAM_ECC_ERR2_T; + +typedef struct dpp_etm_qmu_csch_aged_cmd_cnt_t +{ + ZXIC_UINT32 csch_aged_cmd_cnt; +}DPP_ETM_QMU_CSCH_AGED_CMD_CNT_T; + +typedef struct dpp_etm_qmu_csch_qcfg_csch_congest_cnt_t +{ + ZXIC_UINT32 csch_qcfg_csch_congest_cnt; +}DPP_ETM_QMU_CSCH_QCFG_CSCH_CONGEST_CNT_T; + +typedef struct dpp_etm_qmu_csch_qcfg_qlist_csch_sop_cnt_t +{ + ZXIC_UINT32 csch_qcfg_qlist_csch_sop_cnt; +}DPP_ETM_QMU_CSCH_QCFG_QLIST_CSCH_SOP_CNT_T; + +typedef struct dpp_etm_qmu_csch_qcfg_qlist_csch_eop_cnt_t +{ + ZXIC_UINT32 csch_qcfg_qlist_csch_eop_cnt; +}DPP_ETM_QMU_CSCH_QCFG_QLIST_CSCH_EOP_CNT_T; + +typedef struct dpp_etm_qmu_csch_qcfg_csch_csw_sop_cnt_t +{ + ZXIC_UINT32 csch_qcfg_csch_csw_sop_cnt; +}DPP_ETM_QMU_CSCH_QCFG_CSCH_CSW_SOP_CNT_T; + +typedef struct dpp_etm_qmu_csch_qcfg_csch_csw_eop_cnt_t +{ + ZXIC_UINT32 csch_qcfg_csch_csw_eop_cnt; +}DPP_ETM_QMU_CSCH_QCFG_CSCH_CSW_EOP_CNT_T; + +typedef struct dpp_etm_qmu_csch_qcfg_qlist_csch_drop_cnt_t +{ + ZXIC_UINT32 csch_qcfg_qlist_csch_drop_cnt; +}DPP_ETM_QMU_CSCH_QCFG_QLIST_CSCH_DROP_CNT_T; + +typedef struct dpp_etm_qmu_csch_qcfg_csch_csw_drop_cnt_t +{ + ZXIC_UINT32 csch_qcfg_csch_csw_drop_cnt; +}DPP_ETM_QMU_CSCH_QCFG_CSCH_CSW_DROP_CNT_T; + +typedef struct dpp_etm_qmu_csw_mmu_sop_cmd_cnt_t +{ + ZXIC_UINT32 csw_mmu_sop_cmd_cnt; +}DPP_ETM_QMU_CSW_MMU_SOP_CMD_CNT_T; + +typedef struct dpp_etm_qmu_mmu_csw_sop_data_cnt_t +{ + ZXIC_UINT32 mmu_csw_sop_data_cnt; +}DPP_ETM_QMU_MMU_CSW_SOP_DATA_CNT_T; + +typedef struct dpp_etm_qmu_csw_qsch_feedb_cnt_t +{ + ZXIC_UINT32 csw_qsch_feedb_cnt; +}DPP_ETM_QMU_CSW_QSCH_FEEDB_CNT_T; + +typedef struct dpp_etm_qmu_qmu_crdt_port_fc_cnt_t +{ + ZXIC_UINT32 qmu_crdt_port_fc_cnt; +}DPP_ETM_QMU_QMU_CRDT_PORT_FC_CNT_T; + +typedef struct dpp_etm_qmu_csch_r_block_cnt_t +{ + ZXIC_UINT32 csch_r_block_cnt; +}DPP_ETM_QMU_CSCH_R_BLOCK_CNT_T; + +typedef struct dpp_etm_qmu_qcfg_qlist_qds_head_rd_t +{ + ZXIC_UINT32 qcfg_qlist_qds_head_rd; +}DPP_ETM_QMU_QCFG_QLIST_QDS_HEAD_RD_T; + +typedef struct dpp_etm_qmu_qcfg_qlist_qds_tail_rd_t +{ + ZXIC_UINT32 qcfg_qlist_qds_tail_rd; +}DPP_ETM_QMU_QCFG_QLIST_QDS_TAIL_RD_T; + +typedef struct dpp_etm_qmu_qcfg_qlist_ept_rd_t +{ + ZXIC_UINT32 qcfg_qlist_ept_rd; +}DPP_ETM_QMU_QCFG_QLIST_EPT_RD_T; + +typedef struct dpp_etm_qmu_qcfg_qlist_age_flag_rd_t +{ + ZXIC_UINT32 qcfg_qlist_age_flag_rd; +}DPP_ETM_QMU_QCFG_QLIST_AGE_FLAG_RD_T; + +typedef struct dpp_etm_qmu_qcfg_qlist_cti_rd_t +{ + ZXIC_UINT32 qcfg_qlist_cti_rd; +}DPP_ETM_QMU_QCFG_QLIST_CTI_RD_T; + +typedef struct dpp_etm_qmu_qcfg_qlist_cto_rd_t +{ + ZXIC_UINT32 qcfg_qlist_cto_rd; +}DPP_ETM_QMU_QCFG_QLIST_CTO_RD_T; + +typedef struct dpp_etm_qmu_qcfg_qlist_chk_rd_t +{ + ZXIC_UINT32 qcfg_qlist_chk_rd; +}DPP_ETM_QMU_QCFG_QLIST_CHK_RD_T; + +typedef struct dpp_etm_qmu_qcfg_qlist_nod_rd_t +{ + ZXIC_UINT32 qcfg_qlist_nod_rd; +}DPP_ETM_QMU_QCFG_QLIST_NOD_RD_T; + +typedef struct dpp_etm_qmu_qcfg_qlist_biu_rd_t +{ + ZXIC_UINT32 qcfg_qlist_biu_rd; +}DPP_ETM_QMU_QCFG_QLIST_BIU_RD_T; + +typedef struct dpp_etm_qmu_qsch_r_wlist_flag_t +{ + ZXIC_UINT32 qsch_r_wlist_flag; +}DPP_ETM_QMU_QSCH_R_WLIST_FLAG_T; + +typedef struct dpp_etm_qmu_qcfg_crs_flg_rd_t +{ + ZXIC_UINT32 qcfg_crs_flg_rd; +}DPP_ETM_QMU_QCFG_CRS_FLG_RD_T; + +typedef struct dpp_etm_qmu_cfgmt_qmu_imem_age_qds_t +{ + ZXIC_UINT32 cfgmt_qmu_imem_tp; + ZXIC_UINT32 cfgmt_qmu_imem_hp; +}DPP_ETM_QMU_CFGMT_QMU_IMEM_AGE_QDS_T; + +typedef struct dpp_etm_qmu_cfgmt_qmu_imem_age_qlen_t +{ + ZXIC_UINT32 cfgmt_qmu_imem_no_empty; + ZXIC_UINT32 cfgmt_qmu_imem_qlen; +}DPP_ETM_QMU_CFGMT_QMU_IMEM_AGE_QLEN_T; + +typedef struct dpp_etm_qmu_cfgmt_qmu_imem_pd_ram_low_t +{ + ZXIC_UINT32 cfgmt_qmu_imem_pd_ram_low; +}DPP_ETM_QMU_CFGMT_QMU_IMEM_PD_RAM_LOW_T; + +typedef struct dpp_etm_qmu_cfgmt_qmu_imem_pd_ram_high_t +{ + ZXIC_UINT32 cfgmt_qmu_imem_pd_ram_high; +}DPP_ETM_QMU_CFGMT_QMU_IMEM_PD_RAM_HIGH_T; + +typedef struct dpp_etm_qmu_cfgmt_qmu_imem_up_ptr_t +{ + ZXIC_UINT32 cfgmt_qmu_imem_up_ptr; +}DPP_ETM_QMU_CFGMT_QMU_IMEM_UP_PTR_T; + +typedef struct dpp_etm_qmu_cfgmt_qmu_imem_down_ptr_t +{ + ZXIC_UINT32 cfgmt_qmu_imem_down_ptr; +}DPP_ETM_QMU_CFGMT_QMU_IMEM_DOWN_PTR_T; + +typedef struct dpp_etm_qmu_cfgmt_qmu_imem_age_flag_t +{ + ZXIC_UINT32 cfgmt_qmu_imem_age_flag; +}DPP_ETM_QMU_CFGMT_QMU_IMEM_AGE_FLAG_T; + +typedef struct dpp_etm_qmu_cfg_qsch_lkybkt2cngth_t +{ + ZXIC_UINT32 cfg_qsch_lkybkt2cngth; +}DPP_ETM_QMU_CFG_QSCH_LKYBKT2CNGTH_T; + +typedef struct dpp_etm_qmu_cfg_qsch_lkybkt1cngth_t +{ + ZXIC_UINT32 cfg_qsch_lkybkt1cngth; +}DPP_ETM_QMU_CFG_QSCH_LKYBKT1CNGTH_T; + +typedef struct dpp_etm_qmu_cfg_qsch_lkybkt3cngth_t +{ + ZXIC_UINT32 cfg_qsch_lkybkt3cngth; +}DPP_ETM_QMU_CFG_QSCH_LKYBKT3CNGTH_T; + +typedef struct dpp_etm_qmu_cfg_qsch_rm_mul_mcn1_credit_value_t +{ + ZXIC_UINT32 cfg_qsch_rm_mul_mcn1_credit_value; +}DPP_ETM_QMU_CFG_QSCH_RM_MUL_MCN1_CREDIT_VALUE_T; + +typedef struct dpp_etm_qmu_cfg_qsch_rm_mul_mcn2_credit_value_t +{ + ZXIC_UINT32 cfg_qsch_rm_mul_mcn2_credit_value; +}DPP_ETM_QMU_CFG_QSCH_RM_MUL_MCN2_CREDIT_VALUE_T; + +typedef struct dpp_etm_qmu_cfg_qsch_rm_mul_mcn3_credit_value_t +{ + ZXIC_UINT32 cfg_qsch_rm_mul_mcn3_credit_value; +}DPP_ETM_QMU_CFG_QSCH_RM_MUL_MCN3_CREDIT_VALUE_T; + +typedef struct dpp_etm_qmu_rm_mul_mcn1_rand_ansr_seed_t +{ + ZXIC_UINT32 cfg_qsch_rm_mul_mcn1_rand_mchsm_en; + ZXIC_UINT32 cfg_qsch_rm_mul_mcn1_rand_ansr_seed; +}DPP_ETM_QMU_RM_MUL_MCN1_RAND_ANSR_SEED_T; + +typedef struct dpp_etm_qmu_rm_mul_mcn2_rand_ansr_seed_t +{ + ZXIC_UINT32 cfg_qsch_rm_mul_mcn2_rand_mchsm_en; + ZXIC_UINT32 cfg_qsch_rm_mul_mcn2_rand_ansr_seed; +}DPP_ETM_QMU_RM_MUL_MCN2_RAND_ANSR_SEED_T; + +typedef struct dpp_etm_qmu_rm_mul_mcn3_rand_ansr_seed_t +{ + ZXIC_UINT32 cfg_qsch_rm_mul_mcn3_rand_mchsm_en; + ZXIC_UINT32 cfg_qsch_rm_mul_mcn3_rand_ansr_seed; +}DPP_ETM_QMU_RM_MUL_MCN3_RAND_ANSR_SEED_T; + +typedef struct dpp_etm_qmu_rm_mul_mcn1_rand_ansr_th_t +{ + ZXIC_UINT32 cfg_qsch_rm_mul_mcn1_rand_ansr_th; +}DPP_ETM_QMU_RM_MUL_MCN1_RAND_ANSR_TH_T; + +typedef struct dpp_etm_qmu_rm_mul_mcn2_rand_ansr_th_t +{ + ZXIC_UINT32 cfg_qsch_rm_mul_mcn2_rand_ansr_th; +}DPP_ETM_QMU_RM_MUL_MCN2_RAND_ANSR_TH_T; + +typedef struct dpp_etm_qmu_rm_mul_mcn3_rand_ansr_th_t +{ + ZXIC_UINT32 cfg_qsch_rm_mul_mcn3_rand_ansr_th; +}DPP_ETM_QMU_RM_MUL_MCN3_RAND_ANSR_TH_T; + +typedef struct dpp_etm_qmu_rm_mul_mcn1_rand_hold_base_t +{ + ZXIC_UINT32 cfg_qsch_rm_mul_mcn1_rand_mchsm_en; + ZXIC_UINT32 cfg_qsch_rm_mul_mcn1_rand_hold_base; +}DPP_ETM_QMU_RM_MUL_MCN1_RAND_HOLD_BASE_T; + +typedef struct dpp_etm_qmu_rm_mul_mcn2_rand_hold_base_t +{ + ZXIC_UINT32 cfg_qsch_rm_mul_mcn2_rand_mchsm_en; + ZXIC_UINT32 cfg_qsch_rm_mul_mcn2_rand_hold_base; +}DPP_ETM_QMU_RM_MUL_MCN2_RAND_HOLD_BASE_T; + +typedef struct dpp_etm_qmu_rm_mul_mcn3_rand_hold_base_t +{ + ZXIC_UINT32 cfg_qsch_rm_mul_mcn3_rand_mchsm_en; + ZXIC_UINT32 cfg_qsch_rm_mul_mcn3_rand_hold_base; +}DPP_ETM_QMU_RM_MUL_MCN3_RAND_HOLD_BASE_T; + +typedef struct dpp_etm_qmu_rm_mul_mcn1_rand_sel_mask_t +{ + ZXIC_UINT32 cfg_qsch_rm_mul_mcn1_rand_sel_mask; +}DPP_ETM_QMU_RM_MUL_MCN1_RAND_SEL_MASK_T; + +typedef struct dpp_etm_qmu_rm_mul_mcn2_rand_sel_mask_t +{ + ZXIC_UINT32 cfg_qsch_rm_mul_mcn2_rand_sel_mask; +}DPP_ETM_QMU_RM_MUL_MCN2_RAND_SEL_MASK_T; + +typedef struct dpp_etm_qmu_rm_mul_mcn3_rand_sel_mask_t +{ + ZXIC_UINT32 cfg_qsch_rm_mul_mcn3_rand_sel_mask; +}DPP_ETM_QMU_RM_MUL_MCN3_RAND_SEL_MASK_T; + +typedef struct dpp_etm_qmu_rm_mul_mcn1_rand_sel_seed_reg0_t +{ + ZXIC_UINT32 rm_mul_mcn1_rand_sel_seed7; + ZXIC_UINT32 rm_mul_mcn1_rand_sel_seed6; + ZXIC_UINT32 rm_mul_mcn1_rand_sel_seed5; + ZXIC_UINT32 rm_mul_mcn1_rand_sel_seed4; + ZXIC_UINT32 rm_mul_mcn1_rand_sel_seed3; + ZXIC_UINT32 rm_mul_mcn1_rand_sel_seed2; + ZXIC_UINT32 rm_mul_mcn1_rand_sel_seed1; + ZXIC_UINT32 rm_mul_mcn1_rand_sel_seed0; +}DPP_ETM_QMU_RM_MUL_MCN1_RAND_SEL_SEED_REG0_T; + +typedef struct dpp_etm_qmu_rm_mul_mcn1_rand_sel_seed_reg1_t +{ + ZXIC_UINT32 rm_mul_mcn1_rand_sel_seed8; +}DPP_ETM_QMU_RM_MUL_MCN1_RAND_SEL_SEED_REG1_T; + +typedef struct dpp_etm_qmu_rm_mul_mcn2_rand_sel_seed_reg0_t +{ + ZXIC_UINT32 rm_mul_mcn2_rand_sel_seed7; + ZXIC_UINT32 rm_mul_mcn2_rand_sel_seed6; + ZXIC_UINT32 rm_mul_mcn2_rand_sel_seed5; + ZXIC_UINT32 rm_mul_mcn2_rand_sel_seed4; + ZXIC_UINT32 rm_mul_mcn2_rand_sel_seed3; + ZXIC_UINT32 rm_mul_mcn2_rand_sel_seed2; + ZXIC_UINT32 rm_mul_mcn2_rand_sel_seed1; + ZXIC_UINT32 rm_mul_mcn2_rand_sel_seed0; +}DPP_ETM_QMU_RM_MUL_MCN2_RAND_SEL_SEED_REG0_T; + +typedef struct dpp_etm_qmu_rm_mul_mcn2_rand_sel_seed_reg1_t +{ + ZXIC_UINT32 rm_mul_mcn2_rand_sel_seed8; +}DPP_ETM_QMU_RM_MUL_MCN2_RAND_SEL_SEED_REG1_T; + +typedef struct dpp_etm_qmu_rm_mul_mcn3_rand_sel_seed_reg0_t +{ + ZXIC_UINT32 rm_mul_mcn3_rand_sel_seed7; + ZXIC_UINT32 rm_mul_mcn3_rand_sel_seed6; + ZXIC_UINT32 rm_mul_mcn3_rand_sel_seed5; + ZXIC_UINT32 rm_mul_mcn3_rand_sel_seed4; + ZXIC_UINT32 rm_mul_mcn3_rand_sel_seed3; + ZXIC_UINT32 rm_mul_mcn3_rand_sel_seed2; + ZXIC_UINT32 rm_mul_mcn3_rand_sel_seed1; + ZXIC_UINT32 rm_mul_mcn3_rand_sel_seed0; +}DPP_ETM_QMU_RM_MUL_MCN3_RAND_SEL_SEED_REG0_T; + +typedef struct dpp_etm_qmu_rm_mul_mcn3_rand_sel_seed_reg1_t +{ + ZXIC_UINT32 rm_mul_mcn3_rand_sel_seed8; +}DPP_ETM_QMU_RM_MUL_MCN3_RAND_SEL_SEED_REG1_T; + +typedef struct dpp_etm_qmu_rm_mul_mcn1_step_wait_th1_t +{ + ZXIC_UINT32 cfg_qsch_rm_mul_mcn1_step_wait_th1; +}DPP_ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH1_T; + +typedef struct dpp_etm_qmu_rm_mul_mcn1_step_wait_th2_t +{ + ZXIC_UINT32 cfg_qsch_rm_mul_mcn1_step_wait_th2; +}DPP_ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH2_T; + +typedef struct dpp_etm_qmu_rm_mul_mcn1_step_wait_th3_t +{ + ZXIC_UINT32 cfg_qsch_rm_mul_mcn1_step_wait_th3; +}DPP_ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH3_T; + +typedef struct dpp_etm_qmu_rm_mul_mcn1_step_wait_th4_t +{ + ZXIC_UINT32 cfg_qsch_rm_mul_mcn1_step_wait_th4; +}DPP_ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH4_T; + +typedef struct dpp_etm_qmu_rm_mul_mcn1_step_wait_th5_t +{ + ZXIC_UINT32 cfg_qsch_rm_mul_mcn1_step_wait_th5; +}DPP_ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH5_T; + +typedef struct dpp_etm_qmu_rm_mul_mcn1_step_wait_th6_t +{ + ZXIC_UINT32 cfg_qsch_rm_mul_mcn1_step_wait_th6; +}DPP_ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH6_T; + +typedef struct dpp_etm_qmu_rm_mul_mcn1_step_wait_th7_t +{ + ZXIC_UINT32 cfg_qsch_rm_mul_mcn1_step_wait_th7; +}DPP_ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH7_T; + +typedef struct dpp_etm_qmu_rm_mul_mcn2_step_wait_th1_t +{ + ZXIC_UINT32 cfg_qsch_rm_mul_mcn2_step_wait_th1; +}DPP_ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH1_T; + +typedef struct dpp_etm_qmu_rm_mul_mcn2_step_wait_th2_t +{ + ZXIC_UINT32 cfg_qsch_rm_mul_mcn2_step_wait_th2; +}DPP_ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH2_T; + +typedef struct dpp_etm_qmu_rm_mul_mcn2_step_wait_th3_t +{ + ZXIC_UINT32 cfg_qsch_rm_mul_mcn2_step_wait_th3; +}DPP_ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH3_T; + +typedef struct dpp_etm_qmu_rm_mul_mcn2_step_wait_th4_t +{ + ZXIC_UINT32 cfg_qsch_rm_mul_mcn2_step_wait_th4; +}DPP_ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH4_T; + +typedef struct dpp_etm_qmu_rm_mul_mcn2_step_wait_th5_t +{ + ZXIC_UINT32 cfg_qsch_rm_mul_mcn2_step_wait_th5; +}DPP_ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH5_T; + +typedef struct dpp_etm_qmu_rm_mul_mcn2_step_wait_th6_t +{ + ZXIC_UINT32 cfg_qsch_rm_mul_mcn2_step_wait_th6; +}DPP_ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH6_T; + +typedef struct dpp_etm_qmu_rm_mul_mcn2_step_wait_th7_t +{ + ZXIC_UINT32 cfg_qsch_rm_mul_mcn2_step_wait_th7; +}DPP_ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH7_T; + +typedef struct dpp_etm_qmu_rm_mul_mcn3_step_wait_th1_t +{ + ZXIC_UINT32 cfg_qsch_rm_mul_mcn3_step_wait_th1; +}DPP_ETM_QMU_RM_MUL_MCN3_STEP_WAIT_TH1_T; + +typedef struct dpp_etm_qmu_rm_mul_mcn3_step_wait_th2_t +{ + ZXIC_UINT32 cfg_qsch_rm_mul_mcn3_step_wait_th2; +}DPP_ETM_QMU_RM_MUL_MCN3_STEP_WAIT_TH2_T; + +typedef struct dpp_etm_qmu_rm_mul_mcn3_step_wait_th3_t +{ + ZXIC_UINT32 cfg_qsch_rm_mul_mcn3_step_wait_th3; +}DPP_ETM_QMU_RM_MUL_MCN3_STEP_WAIT_TH3_T; + +typedef struct dpp_etm_qmu_rm_mul_mcn3_step_wait_th4_t +{ + ZXIC_UINT32 cfg_qsch_rm_mul_mcn3_step_wait_th4; +}DPP_ETM_QMU_RM_MUL_MCN3_STEP_WAIT_TH4_T; + +typedef struct dpp_etm_qmu_rm_mul_mcn3_step_wait_th5_t +{ + ZXIC_UINT32 cfg_qsch_rm_mul_mcn3_step_wait_th5; +}DPP_ETM_QMU_RM_MUL_MCN3_STEP_WAIT_TH5_T; + +typedef struct dpp_etm_qmu_rm_mul_mcn3_step_wait_th6_t +{ + ZXIC_UINT32 cfg_qsch_rm_mul_mcn3_step_wait_th6; +}DPP_ETM_QMU_RM_MUL_MCN3_STEP_WAIT_TH6_T; + +typedef struct dpp_etm_qmu_rm_mul_mcn3step_wait_th7_t +{ + ZXIC_UINT32 cfg_qsch_rm_mul_mcn3_step_wait_th7; +}DPP_ETM_QMU_RM_MUL_MCN3STEP_WAIT_TH7_T; + +typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate0_t +{ + ZXIC_UINT32 cfg_qsch_mulcrdcntrate0; +}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE0_T; + +typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate1_t +{ + ZXIC_UINT32 cfg_qsch_mulcrdcntrate1; +}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE1_T; + +typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate2_t +{ + ZXIC_UINT32 cfg_qsch_mulcrdcntrate2; +}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE2_T; + +typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate3_t +{ + ZXIC_UINT32 cfg_qsch_mulcrdcntrate3; +}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE3_T; + +typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate4_t +{ + ZXIC_UINT32 cfg_qsch_mulcrdcntrate4; +}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE4_T; + +typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate5_t +{ + ZXIC_UINT32 cfg_qsch_mulcrdcntrate5; +}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE5_T; + +typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate6_t +{ + ZXIC_UINT32 cfg_qsch_mulcrdcntrate6; +}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE6_T; + +typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate7_t +{ + ZXIC_UINT32 cfg_qsch_mulcrdcntrate7; +}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE7_T; + +typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate8_t +{ + ZXIC_UINT32 cfg_qsch_mulcrdcntrate8; +}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE8_T; + +typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate9_t +{ + ZXIC_UINT32 cfg_qsch_mulcrdcntrate9; +}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE9_T; + +typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate10_t +{ + ZXIC_UINT32 cfg_qsch_mulcrdcntrate10; +}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE10_T; + +typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate11_t +{ + ZXIC_UINT32 cfg_qsch_mulcrdcntrate11; +}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE11_T; + +typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate12_t +{ + ZXIC_UINT32 cfg_qsch_mulcrdcntrate12; +}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE12_T; + +typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate13_t +{ + ZXIC_UINT32 cfg_qsch_mulcrdcntrate13; +}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE13_T; + +typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate14_t +{ + ZXIC_UINT32 cfg_qsch_mulcrdcntrate14; +}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE14_T; + +typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate15_t +{ + ZXIC_UINT32 cfg_qsch_mulcrdcntrate15; +}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE15_T; + +typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate16_t +{ + ZXIC_UINT32 cfg_qsch_mulcrdcntrate16; +}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE16_T; + +typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate17_t +{ + ZXIC_UINT32 cfg_qsch_mulcrdcntrate17; +}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE17_T; + +typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate18_t +{ + ZXIC_UINT32 cfg_qsch_mulcrdcntrate18; +}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE18_T; + +typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate19_t +{ + ZXIC_UINT32 cfg_qsch_mulcrdcntrate19; +}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE19_T; + +typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate20_t +{ + ZXIC_UINT32 cfg_qsch_mulcrdcntrate20; +}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE20_T; + +typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate21_t +{ + ZXIC_UINT32 cfg_qsch_mulcrdcntrate21; +}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE21_T; + +typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate22_t +{ + ZXIC_UINT32 cfg_qsch_mulcrdcntrate22; +}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE22_T; + +typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate23_t +{ + ZXIC_UINT32 cfg_qsch_mulcrdcntrate23; +}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE23_T; + +typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate24_t +{ + ZXIC_UINT32 cfg_qsch_mulcrdcntrate24; +}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE24_T; + +typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate25_t +{ + ZXIC_UINT32 cfg_qsch_mulcrdcntrate25; +}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE25_T; + +typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate26_t +{ + ZXIC_UINT32 cfg_qsch_mulcrdcntrate26; +}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE26_T; + +typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate27_t +{ + ZXIC_UINT32 cfg_qsch_mulcrdcntrate27; +}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE27_T; + +typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate28_t +{ + ZXIC_UINT32 cfg_qsch_mulcrdcntrate28; +}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE28_T; + +typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate29_t +{ + ZXIC_UINT32 cfg_qsch_mulcrdcntrate29; +}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE29_T; + +typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate30_t +{ + ZXIC_UINT32 cfg_qsch_mulcrdcntrate30; +}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE30_T; + +typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate31_t +{ + ZXIC_UINT32 cfg_qsch_mulcrdcntrate31; +}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE31_T; + +typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate32_t +{ + ZXIC_UINT32 cfg_qsch_mulcrdcntrate32; +}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE32_T; + +typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate33_t +{ + ZXIC_UINT32 cfg_qsch_mulcrdcntrate33; +}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE33_T; + +typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate34_t +{ + ZXIC_UINT32 cfg_qsch_mulcrdcntrate34; +}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE34_T; + +typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate35_t +{ + ZXIC_UINT32 cfg_qsch_mulcrdcntrate35; +}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE35_T; + +typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate36_t +{ + ZXIC_UINT32 cfg_qsch_mulcrdcntrate36; +}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE36_T; + +typedef struct dpp_etm_qmu_cfg_qsch_rm_mul_mcn1_rand_hold_shift_t +{ + ZXIC_UINT32 cfg_qsch_rm_mul_mcn1_rand_hold_shift; +}DPP_ETM_QMU_CFG_QSCH_RM_MUL_MCN1_RAND_HOLD_SHIFT_T; + +typedef struct dpp_etm_qmu_cfg_qsch_rm_mul_mcn2_rand_hold_shift_t +{ + ZXIC_UINT32 cfg_qsch_rm_mul_mcn2_rand_hold_shift; +}DPP_ETM_QMU_CFG_QSCH_RM_MUL_MCN2_RAND_HOLD_SHIFT_T; + +typedef struct dpp_etm_qmu_cfg_qsch_rm_mul_mcn3_rand_hold_shift_t +{ + ZXIC_UINT32 cfg_qsch_rm_mul_mcn3_rand_hold_shift; +}DPP_ETM_QMU_CFG_QSCH_RM_MUL_MCN3_RAND_HOLD_SHIFT_T; + +typedef struct dpp_etm_qmu_last_drop_qnum_get_t +{ + ZXIC_UINT32 cgavd_qmu_drop_tap; + ZXIC_UINT32 last_drop_qnum; +}DPP_ETM_QMU_LAST_DROP_QNUM_GET_T; + +typedef struct dpp_etm_qmu_crdt_qmu_credit_cnt_t +{ + ZXIC_UINT32 crdt_qmu_credit_cnt; +}DPP_ETM_QMU_CRDT_QMU_CREDIT_CNT_T; + +typedef struct dpp_etm_qmu_qmu_to_qsch_report_cnt_t +{ + ZXIC_UINT32 qmu_to_qsch_report_cnt; +}DPP_ETM_QMU_QMU_TO_QSCH_REPORT_CNT_T; + +typedef struct dpp_etm_qmu_qmu_to_cgavd_report_cnt_t +{ + ZXIC_UINT32 qmu_to_cgavd_report_cnt; +}DPP_ETM_QMU_QMU_TO_CGAVD_REPORT_CNT_T; + +typedef struct dpp_etm_qmu_qmu_crdt_crs_normal_cnt_t +{ + ZXIC_UINT32 qmu_crdt_crs_normal_cnt; +}DPP_ETM_QMU_QMU_CRDT_CRS_NORMAL_CNT_T; + +typedef struct dpp_etm_qmu_qmu_crdt_crs_off_cnt_t +{ + ZXIC_UINT32 qmu_crdt_crs_off_cnt; +}DPP_ETM_QMU_QMU_CRDT_CRS_OFF_CNT_T; + +typedef struct dpp_etm_qmu_qsch_qlist_shedule_cnt_t +{ + ZXIC_UINT32 qsch_qlist_shedule_cnt; +}DPP_ETM_QMU_QSCH_QLIST_SHEDULE_CNT_T; + +typedef struct dpp_etm_qmu_qsch_qlist_sch_ept_cnt_t +{ + ZXIC_UINT32 qsch_qlist_sch_ept_cnt; +}DPP_ETM_QMU_QSCH_QLIST_SCH_EPT_CNT_T; + +typedef struct dpp_etm_qmu_qmu_to_mmu_blk_wr_cnt_t +{ + ZXIC_UINT32 qmu_to_mmu_blk_wr_cnt; +}DPP_ETM_QMU_QMU_TO_MMU_BLK_WR_CNT_T; + +typedef struct dpp_etm_qmu_qmu_to_csw_blk_rd_cnt_t +{ + ZXIC_UINT32 qmu_to_csw_blk_rd_cnt; +}DPP_ETM_QMU_QMU_TO_CSW_BLK_RD_CNT_T; + +typedef struct dpp_etm_qmu_qmu_to_mmu_sop_wr_cnt_t +{ + ZXIC_UINT32 qmu_to_mmu_sop_wr_cnt; +}DPP_ETM_QMU_QMU_TO_MMU_SOP_WR_CNT_T; + +typedef struct dpp_etm_qmu_qmu_to_mmu_eop_wr_cnt_t +{ + ZXIC_UINT32 qmu_to_mmu_eop_wr_cnt; +}DPP_ETM_QMU_QMU_TO_MMU_EOP_WR_CNT_T; + +typedef struct dpp_etm_qmu_qmu_to_mmu_drop_wr_cnt_t +{ + ZXIC_UINT32 qmu_to_mmu_drop_wr_cnt; +}DPP_ETM_QMU_QMU_TO_MMU_DROP_WR_CNT_T; + +typedef struct dpp_etm_qmu_qmu_to_csw_sop_rd_cnt_t +{ + ZXIC_UINT32 qmu_to_csw_sop_rd_cnt; +}DPP_ETM_QMU_QMU_TO_CSW_SOP_RD_CNT_T; + +typedef struct dpp_etm_qmu_qmu_to_csw_eop_rd_cnt_t +{ + ZXIC_UINT32 qmu_to_csw_eop_rd_cnt; +}DPP_ETM_QMU_QMU_TO_CSW_EOP_RD_CNT_T; + +typedef struct dpp_etm_qmu_qmu_to_csw_drop_rd_cnt_t +{ + ZXIC_UINT32 qmu_to_csw_drop_rd_cnt; +}DPP_ETM_QMU_QMU_TO_CSW_DROP_RD_CNT_T; + +typedef struct dpp_etm_qmu_mmu_to_qmu_wr_release_cnt_t +{ + ZXIC_UINT32 mmu_to_qmu_wr_release_cnt; +}DPP_ETM_QMU_MMU_TO_QMU_WR_RELEASE_CNT_T; + +typedef struct dpp_etm_qmu_mmu_to_qmu_rd_release_cnt_t +{ + ZXIC_UINT32 mmu_to_qmu_rd_release_cnt; +}DPP_ETM_QMU_MMU_TO_QMU_RD_RELEASE_CNT_T; + +typedef struct dpp_etm_qmu_observe_qnum_set_t +{ + ZXIC_UINT32 observe_qnum_set; +}DPP_ETM_QMU_OBSERVE_QNUM_SET_T; + +typedef struct dpp_etm_qmu_spec_q_pkt_received_t +{ + ZXIC_UINT32 spec_q_pkt_received; +}DPP_ETM_QMU_SPEC_Q_PKT_RECEIVED_T; + +typedef struct dpp_etm_qmu_spec_q_pkt_dropped_t +{ + ZXIC_UINT32 spec_q_pkt_dropped; +}DPP_ETM_QMU_SPEC_Q_PKT_DROPPED_T; + +typedef struct dpp_etm_qmu_spec_q_pkt_scheduled_t +{ + ZXIC_UINT32 spec_q_pkt_scheduled; +}DPP_ETM_QMU_SPEC_Q_PKT_SCHEDULED_T; + +typedef struct dpp_etm_qmu_spec_q_wr_cmd_sent_t +{ + ZXIC_UINT32 spec_q_wr_cmd_sent; +}DPP_ETM_QMU_SPEC_Q_WR_CMD_SENT_T; + +typedef struct dpp_etm_qmu_spec_q_rd_cmd_sent_t +{ + ZXIC_UINT32 spec_q_rd_cmd_sent; +}DPP_ETM_QMU_SPEC_Q_RD_CMD_SENT_T; + +typedef struct dpp_etm_qmu_spec_q_pkt_enq_t +{ + ZXIC_UINT32 spec_q_pkt_enq; +}DPP_ETM_QMU_SPEC_Q_PKT_ENQ_T; + +typedef struct dpp_etm_qmu_spec_q_pkt_deq_t +{ + ZXIC_UINT32 spec_q_pkt_deq; +}DPP_ETM_QMU_SPEC_Q_PKT_DEQ_T; + +typedef struct dpp_etm_qmu_spec_q_crdt_uncon_received_t +{ + ZXIC_UINT32 spec_q_crdt_uncon_received; +}DPP_ETM_QMU_SPEC_Q_CRDT_UNCON_RECEIVED_T; + +typedef struct dpp_etm_qmu_spec_q_crdt_cong_received_t +{ + ZXIC_UINT32 spec_q_crdt_cong_received; +}DPP_ETM_QMU_SPEC_Q_CRDT_CONG_RECEIVED_T; + +typedef struct dpp_etm_qmu_spec_q_crs_normal_cnt_t +{ + ZXIC_UINT32 spec_q_crs_normal_cnt; +}DPP_ETM_QMU_SPEC_Q_CRS_NORMAL_CNT_T; + +typedef struct dpp_etm_qmu_spec_q_crs_off_cnt_t +{ + ZXIC_UINT32 spec_q_crs_off_cnt; +}DPP_ETM_QMU_SPEC_Q_CRS_OFF_CNT_T; + +typedef struct dpp_etm_qmu_observe_batch_set_t +{ + ZXIC_UINT32 observe_batch_set; +}DPP_ETM_QMU_OBSERVE_BATCH_SET_T; + +typedef struct dpp_etm_qmu_spec_bat_pkt_received_t +{ + ZXIC_UINT32 spec_bat_pkt_received; +}DPP_ETM_QMU_SPEC_BAT_PKT_RECEIVED_T; + +typedef struct dpp_etm_qmu_spec_bat_pkt_dropped_t +{ + ZXIC_UINT32 spec_bat_pkt_dropped; +}DPP_ETM_QMU_SPEC_BAT_PKT_DROPPED_T; + +typedef struct dpp_etm_qmu_spec_bat_blk_scheduled_t +{ + ZXIC_UINT32 spec_bat_blk_scheduled; +}DPP_ETM_QMU_SPEC_BAT_BLK_SCHEDULED_T; + +typedef struct dpp_etm_qmu_spec_bat_wr_cmd_sent_t +{ + ZXIC_UINT32 spec_bat_wr_cmd_sent; +}DPP_ETM_QMU_SPEC_BAT_WR_CMD_SENT_T; + +typedef struct dpp_etm_qmu_spec_bat_rd_cmd_sent_t +{ + ZXIC_UINT32 spec_bat_rd_cmd_sent; +}DPP_ETM_QMU_SPEC_BAT_RD_CMD_SENT_T; + +typedef struct dpp_etm_qmu_spec_bat_pkt_enq_t +{ + ZXIC_UINT32 spec_bat_pkt_enq; +}DPP_ETM_QMU_SPEC_BAT_PKT_ENQ_T; + +typedef struct dpp_etm_qmu_spec_bat_pkt_deq_t +{ + ZXIC_UINT32 spec_bat_pkt_deq; +}DPP_ETM_QMU_SPEC_BAT_PKT_DEQ_T; + +typedef struct dpp_etm_qmu_spec_bat_crdt_uncon_received_t +{ + ZXIC_UINT32 spec_bat_crdt_uncon_received; +}DPP_ETM_QMU_SPEC_BAT_CRDT_UNCON_RECEIVED_T; + +typedef struct dpp_etm_qmu_spec_bat_crdt_cong_received_t +{ + ZXIC_UINT32 spec_bat_crdt_cong_received; +}DPP_ETM_QMU_SPEC_BAT_CRDT_CONG_RECEIVED_T; + +typedef struct dpp_etm_qmu_spec_bat_crs_normal_cnt_t +{ + ZXIC_UINT32 spec_bat_crs_normal_cnt; +}DPP_ETM_QMU_SPEC_BAT_CRS_NORMAL_CNT_T; + +typedef struct dpp_etm_qmu_spec_bat_crs_off_cnt_t +{ + ZXIC_UINT32 spec_bat_crs_off_cnt; +}DPP_ETM_QMU_SPEC_BAT_CRS_OFF_CNT_T; + +typedef struct dpp_etm_qmu_bcntm_ovfl_qnum_get_t +{ + ZXIC_UINT32 bcntm_ovfl_qnum_get; +}DPP_ETM_QMU_BCNTM_OVFL_QNUM_GET_T; + +typedef struct dpp_etm_qmu_crbal_a_ovf_qnum_get_t +{ + ZXIC_UINT32 crbal_a_ovf_qnum_get; +}DPP_ETM_QMU_CRBAL_A_OVF_QNUM_GET_T; + +typedef struct dpp_etm_qmu_crbal_b_ovf_qnum_get_t +{ + ZXIC_UINT32 crbal_b_ovf_qnum_get; +}DPP_ETM_QMU_CRBAL_B_OVF_QNUM_GET_T; + +typedef struct dpp_etm_qmu_crbal_drop_qnum_get_t +{ + ZXIC_UINT32 crbal_drop_qnum_get; +}DPP_ETM_QMU_CRBAL_DROP_QNUM_GET_T; + +typedef struct dpp_etm_qmu_deq_flg_report_cnt_t +{ + ZXIC_UINT32 deq_flg_report_cnt; +}DPP_ETM_QMU_DEQ_FLG_REPORT_CNT_T; + +typedef struct dpp_etm_qmu_spec_q_crs_get_t +{ + ZXIC_UINT32 spec_q_crs_get; +}DPP_ETM_QMU_SPEC_Q_CRS_GET_T; + +typedef struct dpp_etm_qmu_spec_q_crs_in_get_t +{ + ZXIC_UINT32 spec_q_crs_in_get; +}DPP_ETM_QMU_SPEC_Q_CRS_IN_GET_T; + +typedef struct dpp_etm_qmu_spec_q_crs_flg_csol_get_t +{ + ZXIC_UINT32 spec_q_crs_flg_csol_get; +}DPP_ETM_QMU_SPEC_Q_CRS_FLG_CSOL_GET_T; + +typedef struct dpp_etm_qmu_ept_sch_qnum_get_t +{ + ZXIC_UINT32 ept_sch_qnum_get; +}DPP_ETM_QMU_EPT_SCH_QNUM_GET_T; + + +#ifdef __cplusplus +} +#endif +#endif + diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_mem_info.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_mem_info.h new file mode 100755 index 0000000..ddf091f --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_mem_info.h @@ -0,0 +1,66 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_mem.h +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : 王春雷 +* 完成日期 : 2014/03/20 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ + +#ifndef _DPP_MEM_H_ +#define _DPP_MEM_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +typedef enum dpp_mem_no_e +{ + PKTRX_PHYPORT_UDF_ATTRIm = 0, + PKTRX_PHYPORT_HDW_ATTRIm = 1, + PKTRX_PHYPORT_FLOW_PCm = 2, + PKTRX_ICU_TCAMm = 3, + PKTRX_FLOWNUM_TCAMm = 4, +}DPP_MEM_NO_E; + +typedef struct dpp_mem_field_t +{ + ZXIC_SINT8 *p_name; /* 字段名 */ + ZXIC_UINT32 flags; /* 标志位 */ + ZXIC_UINT16 msb_pos; /* 最高比特位置，以寄存器列表为准*/ + ZXIC_UINT16 len; /* 字段长度，以比特为单位 */ +}DPP_MEM_FIELD_T; + + +#define DPP_MEM_FLAG_TCAM (1<<0) /* Tcam类型的表 */ +typedef struct dpp_mem_info_t +{ + ZXIC_UINT32 mem_no; + ZXIC_UINT32 module_no; + ZXIC_UINT32 flags; + ZXIC_UINT32 mem_id; /* 模块内部的mem标识 */ + ZXIC_UINT32 index_min; /* 最小索引值 */ + ZXIC_UINT32 index_max; /* 最大索引值 */ + ZXIC_UINT32 width; /* 表项宽度，以字节为单位 */ + + DPP_MEM_FIELD_T *p_fileds; /* 表项所有字段 */ + +}DPP_MEM_INFO_T; + +#ifdef __cplusplus +} +#endif + +#endif + + diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_module.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_module.h new file mode 100755 index 0000000..7c48381 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_module.h @@ -0,0 +1,214 @@ +#ifndef _DPP_MODULE_H_ +#define _DPP_MODULE_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "zxic_common.h" +#include "dpp_dev.h" +#include "dpp_type_api.h" + +/** for PPU*/ +#ifdef DPP_TEST_BAORD_SSP2T +#define DPP_PPU_CLUSTER_NUM (1) +#else +#define DPP_PPU_CLUSTER_NUM (6) +#endif + +#define DPP_PPU_ME_EXCEPTION_MAX (8) +#define DPP_PPU_CLUSTER_MEPERCLS_NUM (8) +#define DPP_PPU_CLUSTER_SPACE_SIZE (0x00008000) +#define DPP_MAX_CHCHK_NUM (50) + +#define DPP_TRPG_PORT_NUM (32) +#define DPP_TRPG_PORT_SPACE_SIZE (0x10000) + +#define DPP_TRPG_RAM_NUM (16) +#define DPP_TRPG_RAM_SPACE_SIZE (0x10000) + +#define DPP_TSN_PORT_NUM (4) +#define DPP_TSN_PORT_SPACE_SIZE (0x4000) + +typedef enum dpp_module_e +{ + CFG = 1, /**< @brief 1*/ + NPPU, /**< @brief 2*/ + PPU, /**< @brief 3*/ + ETM, /**< @brief 4*/ + STAT, /**< @brief 5*/ + CAR, /**< @brief 6*/ + SE, /**< @brief 7*/ + SMMU0 = SE, /**< @brief 7*/ + SMMU1 = SE, /**< @brief 7*/ + DTB, /**< @brief 8*/ + TRPG , /**< @brief 9*/ + TSN , /**< @brief 10*/ + AXI , /**< @brief 11*/ + PTPTM , /**< @brief 12*/ + DTB4K, /**< @brief 13*/ + STAT4K, /**< @brief 14*/ + PPU4K, /**< @brief 15*/ + SE4K, /**< @brief 16*/ + SMMU14K, /**< @brief 17*/ + MODULE_MAX +} DPP_MODULE_E; + +typedef enum module_tm_e +{ + MODULE_TM_CFGMT = 0, + MODULE_TM_OLIF = 1, + MODULE_TM_CGAVD = 2, + MODULE_TM_TMMU = 3, + MODULE_TM_SHAP = 4, + MODULE_TM_CRDT = 5, + MODULE_TM_QMU = 6, + MODULE_TM_MAX +} MODULE_TM_E; + +/*NP 在PICE中的偏移地址*/ +#define SYS_VF_NP_BASE_OFFSET 0X0000000000 +/*NP 在DPU中的基地址*/ + +#if DPP_DEV_VPCI_EN +#define SYS_NP_BASE_ADDR 0x6300000000 +#define SYS_NP_BASE_ADDR0 0x14000000 +#define SYS_NP_BASE_ADDR1 0x16000000 +#else +#define SYS_NP_BASE_ADDR 0x6218000000 +#define SYS_NP_BASE_ADDR0 0x00000000 +#define SYS_NP_BASE_ADDR1 0x02000000 +#endif + +/** sub system base address*/ +typedef enum sys_base_addr_e +{ + SYS_NPPU_BASE_ADDR = (SYS_NP_BASE_ADDR0 + 0x00000000), + SYS_PPU_BASE_ADDR = (SYS_NP_BASE_ADDR0 + 0x00080000), + SYS_ETM_BASE_ADDR = (SYS_NP_BASE_ADDR0 + 0x00180000), + SYS_STAT_BASE_ADDR = (SYS_NP_BASE_ADDR0 + 0x00200000), + SYS_SE_BASE_ADDR = (SYS_NP_BASE_ADDR0 + 0x00280000), + SYS_SE_SMMU0_BASE_ADDR = (SYS_NP_BASE_ADDR0 + 0x00300000), + SYS_SE_SMMU1_BASE_ADDR = (SYS_NP_BASE_ADDR0 + 0x00310000), +// SYS_TRPG_BASE_ADDR = (SYS_NP_BASE_ADDR0 + 0x00320000), + SYS_CFG_BASE_ADDR = (SYS_NP_BASE_ADDR0 + 0x00330000), + SYS_PTP0_BASE_ADDR = (SYS_NP_BASE_ADDR0 + 0x00340000), + SYS_PTP1_BASE_ADDR = (SYS_NP_BASE_ADDR0 + 0x00344000), + SYS_TSN_BASE_ADDR = (SYS_NP_BASE_ADDR0 + 0x00350000), + SYS_TRPG_BASE_ADDR = (SYS_NP_BASE_ADDR0 + 0x00400000), + + SYS_DTB_BASE_ADDR = (SYS_NP_BASE_ADDR1 + 0x00000000), + SYS_AXIM0_BASE_ADDR = (SYS_NP_BASE_ADDR1 + 0x01400000), + SYS_AXIM1_BASE_ADDR = (SYS_NP_BASE_ADDR1 + 0x01408000), + SYS_AXI_CONV_BASE_ADDR = (SYS_NP_BASE_ADDR1 + 0x01410000), + SYS_AXIS_BASE_ADDR = (SYS_NP_BASE_ADDR1 + 0x01418000), + SYS_TLB_BASE_ADDR = (SYS_NP_BASE_ADDR1 + 0x01420000), + + SYS_MAX_BASE_ADDR = 0x20000000, +} SYS_BASE_ADDR_E; + +/** module base address*/ +typedef enum module_base_addr_e +{ + /* CFG */ + MODULE_CFG_PCIE_BASE_ADDR = 0x00000000, + MODULE_CFG_DMA_BASE_ADDR = 0x00001000, + MODULE_CFG_CSR_BASE_ADDR = 0x00003000, + + /* NPPU */ + MODULE_NPPU_MR_CFG_BASE_ADDR = 0x00000000, + MODULE_NPPU_PKTRX_CFG_BASE_ADDR = 0x00000800, + MODULE_NPPU_PKTRX_STAT_BASE_ADDR = 0x00001000, + MODULE_NPPU_IDMA_CFG_BASE_ADDR = 0x00001800, + MODULE_NPPU_IDMA_STAT_BASE_ADDR = 0x00002000, + MODULE_NPPU_PBU_CFG_BASE_ADDR = 0x00002800, + MODULE_NPPU_PBU_STAT_BASE_ADDR = 0x00003000, + MODULE_NPPU_ISU_CFG_BASE_ADDR = 0x00003800, + MODULE_NPPU_ISU_STAT_BASE_ADDR = 0x00004000, + MODULE_NPPU_ODMA_CFG_BASE_ADDR = 0x00004800, + MODULE_NPPU_ODMA_STAT_BASE_ADDR = 0x00005000, + MODULE_NPPU_OAM_CFG_BASE_ADDR = 0x00005800, + MODULE_NPPU_OAM_STAT_BASE_ADDR = 0x00006000, + MODULE_NPPU_OAM_INT_IDX0_BASE_ADDR = 0x00006800, + MODULE_NPPU_OAM_INT_IDX1_BASE_ADDR = 0x00007000, + + /* PPU */ + MODULE_PPU_CSR_BASE_ADDR = 0x00000000, + MODULE_PPU_DBG_BASE_ADDR = 0x00000800, + MODULE_CLUSTER0_BASE_ADDR = 0x00008000, + MODULE_CLUSTER1_BASE_ADDR = 0x00010000, + MODULE_CLUSTER2_BASE_ADDR = 0x00018000, + MODULE_CLUSTER3_BASE_ADDR = 0x00020000, + + /* TM */ + MODULE_TM_CFGMT_BASE_ADDR = 0x00000000, + MODULE_TM_OLIF_BASE_ADDR = 0x00020000, + MODULE_TM_CGAVD_BASE_ADDR = 0x00030000, + MODULE_TM_TMMU_BASE_ADDR = 0x00040000, + MODULE_TM_SHAP_BASE_ADDR = 0x00050000, + MODULE_TM_CRDT_BASE_ADDR = 0x00060000, + MODULE_TM_QMU_BASE_ADDR = 0x00070000, + + /* STAT */ + MODULE_STAT_CAR0_BASE_ADDR = 0x00000000, + MODULE_STAT_ETCAM_BASE_ADDR = 0x00002000, + MODULE_STAT_GLBL_BASE_ADDR = 0x00003000, + + /* SE */ + MODULE_SE_ALG_BASE_ADDR = 0x00000000, + MODULE_SE_KSCHD_BASE_ADDR = 0x00004000, + MODULE_SE_RSCHD_BASE_ADDR = 0x00008000, + MODULE_SE_PARSER_BASE_ADDR = 0x0000c000, + MODULE_SE_AS_BASE_ADDR = 0x00010000, + MODULE_SE_CFG_BASE_ADDR = 0x00014000, + + /* SMMU0 */ + MODULE_SE_SMMU0_BASE_ADDR = 0x00000000, + + /* SMMU1 */ + MODULE_SE_SMMU1_BASE_ADDR = 0x00000000, + MODULE_SE_CMMU_BASE_ADDR = 0x00004000, + + /* DTB */ + MODULE_DTB_ENQ_BASE_ADDR = 0x00000000, + MODULE_DTB_CFG_BASE_ADDR = 0x01000000, + MODULE_DTB_DDOS_BASE_ADDR = 0x01010000, + MODULE_DTB_RAM_BASE_ADDR = 0x01100000, + + /* TRPG */ + MODULE_TRPG_RX_BASE_ADDR = 0x00000000, + MODULE_TRPG_TX_BASE_ADDR = 0x00400000, + MODULE_TRPG_TX_GLB_BASE_ADDR = 0x00600000, + MODULE_TRPG_TX_ETM_PORT_BASE_ADDR = 0x00610000, + MODULE_TRPG_RX_RAM_BASE_ADDR = 0x00200000, + MODULE_TRPG_TX_RAM_BASE_ADDR = 0x00620000, + MODULE_TRPG_TX_ETM_RAM_BASE_ADDR = 0x00710000, + MODULE_TRPG_TX_TODTIME_RAM_BASE_ADDR = 0x00720000, + + + + /* TSN */ + MODULE_TSN_PORT0_BASE_ADDR = 0x00000000, + MODULE_TSN_PORT1_BASE_ADDR = 0x00004000, + MODULE_TSN_PORT2_BASE_ADDR = 0x00008000, + MODULE_TSN_PORT3_BASE_ADDR = 0x0000C000, + +} MODULE_BASE_ADDR_E; + +DPP_STATUS dpp_read(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 *p_data); +DPP_STATUS dpp_write(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 *p_data); + +DPP_STATUS dpp_se_read(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 *p_data); +DPP_STATUS dpp_se_write(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 *p_data); + +DPP_STATUS dpp_se_alg_read(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 *p_data); +DPP_STATUS dpp_se_alg_write(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 *p_data); + +DPP_STATUS dpp_ppu_read(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 *p_data); +DPP_STATUS dpp_ppu_write(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 *p_data); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_nppu_reg.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_nppu_reg.h new file mode 100644 index 0000000..38d6667 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_nppu_reg.h @@ -0,0 +1,3850 @@ + +#ifndef _DPP_NPPU_REG_H_ +#define _DPP_NPPU_REG_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +typedef struct dpp_nppu_mr_cfg_cfg_shap_param_t +{ + ZXIC_UINT32 shap_en; + ZXIC_UINT32 shap_rate; +}DPP_NPPU_MR_CFG_CFG_SHAP_PARAM_T; + +typedef struct dpp_nppu_mr_cfg_cfg_shap_token_t +{ + ZXIC_UINT32 cfg_shap_plen_offset; + ZXIC_UINT32 cfg_shap_token; +}DPP_NPPU_MR_CFG_CFG_SHAP_TOKEN_T; + +typedef struct dpp_nppu_mr_cfg_idle_ptr_fifo_aful_th_t +{ + ZXIC_UINT32 idle_ptr3_fifo_aful_th; + ZXIC_UINT32 idle_ptr2_fifo_aful_th; + ZXIC_UINT32 idle_ptr1_fifo_aful_th; + ZXIC_UINT32 idle_ptr0_fifo_aful_th; +}DPP_NPPU_MR_CFG_IDLE_PTR_FIFO_AFUL_TH_T; + +typedef struct dpp_nppu_mr_cfg_mr_cos_port_cfg_t +{ + ZXIC_UINT32 cos3_port_cfg; + ZXIC_UINT32 cos2_port_cfg; + ZXIC_UINT32 cos1_port_cfg; + ZXIC_UINT32 cos0_port_cfg; +}DPP_NPPU_MR_CFG_MR_COS_PORT_CFG_T; + +typedef struct dpp_nppu_pktrx_cfg_ind_status_t +{ + ZXIC_UINT32 ind_access_done; +}DPP_NPPU_PKTRX_CFG_IND_STATUS_T; + +typedef struct dpp_nppu_pktrx_cfg_ind_cmd_t +{ + ZXIC_UINT32 ind_rd_or_wr; + ZXIC_UINT32 ind_mem_id; + ZXIC_UINT32 ind_mem_addr; +}DPP_NPPU_PKTRX_CFG_IND_CMD_T; + +typedef struct dpp_nppu_pktrx_cfg_ind_data0_t +{ + ZXIC_UINT32 ind_dat0; +}DPP_NPPU_PKTRX_CFG_IND_DATA0_T; + +typedef struct dpp_nppu_pktrx_cfg_ind_data1_t +{ + ZXIC_UINT32 ind_dat1; +}DPP_NPPU_PKTRX_CFG_IND_DATA1_T; + +typedef struct dpp_nppu_pktrx_cfg_ind_data2_t +{ + ZXIC_UINT32 ind_dat2; +}DPP_NPPU_PKTRX_CFG_IND_DATA2_T; + +typedef struct dpp_nppu_pktrx_cfg_ind_data3_t +{ + ZXIC_UINT32 ind_dat3; +}DPP_NPPU_PKTRX_CFG_IND_DATA3_T; + +typedef struct dpp_nppu_pktrx_cfg_ind_data4_t +{ + ZXIC_UINT32 ind_dat4; +}DPP_NPPU_PKTRX_CFG_IND_DATA4_T; + +typedef struct dpp_nppu_pktrx_cfg_ind_data5_t +{ + ZXIC_UINT32 ind_dat5; +}DPP_NPPU_PKTRX_CFG_IND_DATA5_T; + +typedef struct dpp_nppu_pktrx_cfg_ind_data6_t +{ + ZXIC_UINT32 ind_dat6; +}DPP_NPPU_PKTRX_CFG_IND_DATA6_T; + +typedef struct dpp_nppu_pktrx_cfg_ind_data7_t +{ + ZXIC_UINT32 ind_dat7; +}DPP_NPPU_PKTRX_CFG_IND_DATA7_T; + +typedef struct dpp_nppu_pktrx_cfg_tcam_0_cmd_t +{ + ZXIC_UINT32 cfg_vben; + ZXIC_UINT32 cfg_vbi; + ZXIC_UINT32 cfg_t_strwc; + ZXIC_UINT32 tcam0_sm; + ZXIC_UINT32 tcam0_smen; + ZXIC_UINT32 tcam0_rm; + ZXIC_UINT32 tcam0_rmen; + ZXIC_UINT32 tcam0_enable; + ZXIC_UINT32 tcam0_flush; + ZXIC_UINT32 tcam0_unload; + ZXIC_UINT32 tcam0_unload_addr; +}DPP_NPPU_PKTRX_CFG_TCAM_0_CMD_T; + +typedef struct dpp_nppu_pktrx_cfg_tcam_1_cmd_t +{ + ZXIC_UINT32 tcam1_sm; + ZXIC_UINT32 tcam1_smen; + ZXIC_UINT32 tcam1_rm; + ZXIC_UINT32 tcam1_rmen; + ZXIC_UINT32 tcam1_enable; + ZXIC_UINT32 tcam1_flush; + ZXIC_UINT32 tcam1_unload; + ZXIC_UINT32 tcam1_unload_addr; +}DPP_NPPU_PKTRX_CFG_TCAM_1_CMD_T; + +typedef struct dpp_nppu_pktrx_cfg_port_en_0_t +{ + ZXIC_UINT32 cfg_isch_port_en_0; +}DPP_NPPU_PKTRX_CFG_PORT_EN_0_T; + +typedef struct dpp_nppu_pktrx_cfg_port_en_1_t +{ + ZXIC_UINT32 cfg_isch_port_en_1; +}DPP_NPPU_PKTRX_CFG_PORT_EN_1_T; + +typedef struct dpp_nppu_pktrx_cfg_port_en_2_t +{ + ZXIC_UINT32 cfg_isch_port_en_2; +}DPP_NPPU_PKTRX_CFG_PORT_EN_2_T; + +typedef struct dpp_nppu_pktrx_cfg_port_en_3_t +{ + ZXIC_UINT32 cfg_port_change_en_0; + ZXIC_UINT32 cfg_port_change_en_1; + ZXIC_UINT32 cfg_isch_port_en_3; +}DPP_NPPU_PKTRX_CFG_PORT_EN_3_T; + +typedef struct dpp_nppu_pktrx_cfg_cfg_port_l2_offset_mode_0_t +{ + ZXIC_UINT32 cfg_port_l2_offset_mode_0; +}DPP_NPPU_PKTRX_CFG_CFG_PORT_L2_OFFSET_MODE_0_T; + +typedef struct dpp_nppu_pktrx_cfg_cfg_port_l2_offset_mode_1_t +{ + ZXIC_UINT32 cfg_port_l2_offset_mode_1; +}DPP_NPPU_PKTRX_CFG_CFG_PORT_L2_OFFSET_MODE_1_T; + +typedef struct dpp_nppu_pktrx_cfg_cfg_port_l2_offset_mode_2_t +{ + ZXIC_UINT32 cfg_port_l2_offset_mode_2; +}DPP_NPPU_PKTRX_CFG_CFG_PORT_L2_OFFSET_MODE_2_T; + +typedef struct dpp_nppu_pktrx_cfg_cfg_port_l2_offset_mode_3_t +{ + ZXIC_UINT32 cfg_port_l2_offset_mode_3; +}DPP_NPPU_PKTRX_CFG_CFG_PORT_L2_OFFSET_MODE_3_T; + +typedef struct dpp_nppu_pktrx_cfg_port_fc_mode_0_t +{ + ZXIC_UINT32 cfg_isch_fc_mode_0; +}DPP_NPPU_PKTRX_CFG_PORT_FC_MODE_0_T; + +typedef struct dpp_nppu_pktrx_cfg_port_fc_mode_1_t +{ + ZXIC_UINT32 cfg_isch_fc_mode_1; +}DPP_NPPU_PKTRX_CFG_PORT_FC_MODE_1_T; + +typedef struct dpp_nppu_pktrx_cfg_port_fc_mode_2_t +{ + ZXIC_UINT32 cfg_isch_fc_mode_2; +}DPP_NPPU_PKTRX_CFG_PORT_FC_MODE_2_T; + +typedef struct dpp_nppu_pktrx_cfg_port_fc_mode_3_t +{ + ZXIC_UINT32 cfg_isch_fc_mode_3; +}DPP_NPPU_PKTRX_CFG_PORT_FC_MODE_3_T; + +typedef struct dpp_nppu_pktrx_cfg_port_fc_mode_4_t +{ + ZXIC_UINT32 cfg_isch_fc_mode_4; +}DPP_NPPU_PKTRX_CFG_PORT_FC_MODE_4_T; + +typedef struct dpp_nppu_pktrx_cfg_port_fc_mode_5_t +{ + ZXIC_UINT32 cfg_isch_fc_mode_5; +}DPP_NPPU_PKTRX_CFG_PORT_FC_MODE_5_T; + +typedef struct dpp_nppu_pktrx_cfg_port_fc_mode_6_t +{ + ZXIC_UINT32 cfg_isch_fc_mode_6; +}DPP_NPPU_PKTRX_CFG_PORT_FC_MODE_6_T; + +typedef struct dpp_nppu_pktrx_cfg_port_fc_mode_7_t +{ + ZXIC_UINT32 cfg_pfu_aging_en; + ZXIC_UINT32 cfg_isch_aging_en; + ZXIC_UINT32 cfg_isch_fc_mode_7; +}DPP_NPPU_PKTRX_CFG_PORT_FC_MODE_7_T; + +typedef struct dpp_nppu_pktrx_cfg_cfg_isch_aging_th_t +{ + ZXIC_UINT32 cfg_pfu_delay_cycle; + ZXIC_UINT32 cfg_isch_aging_th; +}DPP_NPPU_PKTRX_CFG_CFG_ISCH_AGING_TH_T; + +typedef struct dpp_nppu_pktrx_cfg_isch_fifo_th_0_t +{ + ZXIC_UINT32 cfg_sch_fifo3_fc_th; + ZXIC_UINT32 cfg_sch_fifo2_fc_th; + ZXIC_UINT32 cfg_sch_fifo1_fc_th; + ZXIC_UINT32 cfg_sch_fifo0_fc_th; +}DPP_NPPU_PKTRX_CFG_ISCH_FIFO_TH_0_T; + +typedef struct dpp_nppu_pktrx_cfg_isch_cfg_1_t +{ + ZXIC_UINT32 cfg_parser_max_len_en; + ZXIC_UINT32 cfg_parser_max_len; + ZXIC_UINT32 cfg_parser_min_len_en; + ZXIC_UINT32 cfg_parser_min_len; + ZXIC_UINT32 sp_sch_sel; +}DPP_NPPU_PKTRX_CFG_ISCH_CFG_1_T; + +typedef struct dpp_nppu_pktrx_cfg_tcam_0_vld_t +{ + ZXIC_UINT32 cfg_tcam0_vld; +}DPP_NPPU_PKTRX_CFG_TCAM_0_VLD_T; + +typedef struct dpp_nppu_pktrx_cfg_tcam_1_vld_t +{ + ZXIC_UINT32 cfg_tcam1_vld; +}DPP_NPPU_PKTRX_CFG_TCAM_1_VLD_T; + +typedef struct dpp_nppu_pktrx_cfg_cpu_port_en_mask_t +{ + ZXIC_UINT32 cpu_port_en_mask; +}DPP_NPPU_PKTRX_CFG_CPU_PORT_EN_MASK_T; + +typedef struct dpp_nppu_pktrx_cfg_pktrx_glbal_cfg_0_t +{ + ZXIC_UINT32 pktrx_glbal_cfg_0; +}DPP_NPPU_PKTRX_CFG_PKTRX_GLBAL_CFG_0_T; + +typedef struct dpp_nppu_pktrx_cfg_pktrx_glbal_cfg_1_t +{ + ZXIC_UINT32 pktrx_glbal_cfg_1; +}DPP_NPPU_PKTRX_CFG_PKTRX_GLBAL_CFG_1_T; + +typedef struct dpp_nppu_pktrx_cfg_pktrx_glbal_cfg_2_t +{ + ZXIC_UINT32 pktrx_glbal_cfg_2; +}DPP_NPPU_PKTRX_CFG_PKTRX_GLBAL_CFG_2_T; + +typedef struct dpp_nppu_pktrx_cfg_pktrx_glbal_cfg_3_t +{ + ZXIC_UINT32 pktrx_glbal_cfg_3; +}DPP_NPPU_PKTRX_CFG_PKTRX_GLBAL_CFG_3_T; + +typedef struct dpp_nppu_pktrx_cfg_nppu_start_t +{ + ZXIC_UINT32 nppu_start; +}DPP_NPPU_PKTRX_CFG_NPPU_START_T; + +typedef struct dpp_nppu_pktrx_stat_ind_status_t +{ + ZXIC_UINT32 ind_access_done; +}DPP_NPPU_PKTRX_STAT_IND_STATUS_T; + +typedef struct dpp_nppu_pktrx_stat_ind_cmd_t +{ + ZXIC_UINT32 ind_rd_or_wr; + ZXIC_UINT32 ind_mem_id; + ZXIC_UINT32 ind_mem_addr; +}DPP_NPPU_PKTRX_STAT_IND_CMD_T; + +typedef struct dpp_nppu_pktrx_stat_ind_data0_t +{ + ZXIC_UINT32 ind_dat0; +}DPP_NPPU_PKTRX_STAT_IND_DATA0_T; + +typedef struct dpp_nppu_idma_cfg_debug_cnt_ovfl_mode_t +{ + ZXIC_UINT32 debug_cnt_ovfl_mode; +}DPP_NPPU_IDMA_CFG_DEBUG_CNT_OVFL_MODE_T; + +typedef struct dpp_nppu_idma_stat_ind_status_t +{ + ZXIC_UINT32 ind_access_done; +}DPP_NPPU_IDMA_STAT_IND_STATUS_T; + +typedef struct dpp_nppu_idma_stat_ind_cmd_t +{ + ZXIC_UINT32 ind_rd_or_wr; + ZXIC_UINT32 ind_mem_id; + ZXIC_UINT32 ind_mem_addr; +}DPP_NPPU_IDMA_STAT_IND_CMD_T; + +typedef struct dpp_nppu_idma_stat_ind_data0_t +{ + ZXIC_UINT32 ind_data0; +}DPP_NPPU_IDMA_STAT_IND_DATA0_T; + +typedef struct dpp_nppu_pbu_cfg_ind_status_t +{ + ZXIC_UINT32 ind_access_done; +}DPP_NPPU_PBU_CFG_IND_STATUS_T; + +typedef struct dpp_nppu_pbu_cfg_ind_cmd_t +{ + ZXIC_UINT32 ind_rd_or_wr; + ZXIC_UINT32 ind_mem_id; + ZXIC_UINT32 ind_mem_addr; +}DPP_NPPU_PBU_CFG_IND_CMD_T; + +typedef struct dpp_nppu_pbu_cfg_ind_data0_t +{ + ZXIC_UINT32 ind_data0; +}DPP_NPPU_PBU_CFG_IND_DATA0_T; + +typedef struct dpp_nppu_pbu_cfg_ind_data1_t +{ + ZXIC_UINT32 ind_data1; +}DPP_NPPU_PBU_CFG_IND_DATA1_T; + +typedef struct dpp_nppu_pbu_cfg_ind_data2_t +{ + ZXIC_UINT32 ind_data2; +}DPP_NPPU_PBU_CFG_IND_DATA2_T; + +typedef struct dpp_nppu_pbu_cfg_ind_data3_t +{ + ZXIC_UINT32 ind_data3; +}DPP_NPPU_PBU_CFG_IND_DATA3_T; + +typedef struct dpp_nppu_pbu_cfg_ind_data4_t +{ + ZXIC_UINT32 ind_data4; +}DPP_NPPU_PBU_CFG_IND_DATA4_T; + +typedef struct dpp_nppu_pbu_cfg_ind_data5_t +{ + ZXIC_UINT32 ind_data5; +}DPP_NPPU_PBU_CFG_IND_DATA5_T; + +typedef struct dpp_nppu_pbu_cfg_ind_data6_t +{ + ZXIC_UINT32 ind_data6; +}DPP_NPPU_PBU_CFG_IND_DATA6_T; + +typedef struct dpp_nppu_pbu_cfg_ind_data7_t +{ + ZXIC_UINT32 ind_data7; +}DPP_NPPU_PBU_CFG_IND_DATA7_T; + +typedef struct dpp_nppu_pbu_cfg_idma_public_th_t +{ + ZXIC_UINT32 idma_public_th; +}DPP_NPPU_PBU_CFG_IDMA_PUBLIC_TH_T; + +typedef struct dpp_nppu_pbu_cfg_lif_public_th_t +{ + ZXIC_UINT32 lif_public_th; +}DPP_NPPU_PBU_CFG_LIF_PUBLIC_TH_T; + +typedef struct dpp_nppu_pbu_cfg_idma_total_th_t +{ + ZXIC_UINT32 idma_total_th; +}DPP_NPPU_PBU_CFG_IDMA_TOTAL_TH_T; + +typedef struct dpp_nppu_pbu_cfg_lif_total_th_t +{ + ZXIC_UINT32 lif_total_th; +}DPP_NPPU_PBU_CFG_LIF_TOTAL_TH_T; + +typedef struct dpp_nppu_pbu_cfg_mc_total_th_t +{ + ZXIC_UINT32 mc_total_th; +}DPP_NPPU_PBU_CFG_MC_TOTAL_TH_T; + +typedef struct dpp_nppu_pbu_cfg_mc_cos10_th_t +{ + ZXIC_UINT32 mc_cos1_mode; + ZXIC_UINT32 mc_cos0_mode; + ZXIC_UINT32 mc_cos1_th; + ZXIC_UINT32 mc_cos0_th; +}DPP_NPPU_PBU_CFG_MC_COS10_TH_T; + +typedef struct dpp_nppu_pbu_cfg_mc_cos32_th_t +{ + ZXIC_UINT32 mc_cos3_mode; + ZXIC_UINT32 mc_cos2_mode; + ZXIC_UINT32 mc_cos3_th; + ZXIC_UINT32 mc_cos2_th; +}DPP_NPPU_PBU_CFG_MC_COS32_TH_T; + +typedef struct dpp_nppu_pbu_cfg_mc_cos54_th_t +{ + ZXIC_UINT32 mc_cos5_mode; + ZXIC_UINT32 mc_cos4_mode; + ZXIC_UINT32 mc_cos5_th; + ZXIC_UINT32 mc_cos4_th; +}DPP_NPPU_PBU_CFG_MC_COS54_TH_T; + +typedef struct dpp_nppu_pbu_cfg_mc_cos76_th_t +{ + ZXIC_UINT32 mc_cos7_mode; + ZXIC_UINT32 mc_cos6_mode; + ZXIC_UINT32 mc_cos7_th; + ZXIC_UINT32 mc_cos6_th; +}DPP_NPPU_PBU_CFG_MC_COS76_TH_T; + +typedef struct dpp_nppu_pbu_cfg_debug_cnt_ovfl_mode_t +{ + ZXIC_UINT32 debug_cnt_ovfl_mode; +}DPP_NPPU_PBU_CFG_DEBUG_CNT_OVFL_MODE_T; + +typedef struct dpp_nppu_pbu_cfg_se_key_aful_negate_cfg_t +{ + ZXIC_UINT32 se_key_aful_negate_cfg; +}DPP_NPPU_PBU_CFG_SE_KEY_AFUL_NEGATE_CFG_T; + +typedef struct dpp_nppu_pbu_cfg_sa_flag_t +{ + ZXIC_UINT32 sa_flag; +}DPP_NPPU_PBU_CFG_SA_FLAG_T; + +typedef struct dpp_nppu_pbu_stat_ind_data_t +{ + ZXIC_UINT32 ind_data; +}DPP_NPPU_PBU_STAT_IND_DATA_T; + +typedef struct dpp_nppu_pbu_stat_ind_status_t +{ + ZXIC_UINT32 ind_access_done; +}DPP_NPPU_PBU_STAT_IND_STATUS_T; + +typedef struct dpp_nppu_pbu_stat_ind_cmd_t +{ + ZXIC_UINT32 ind_rd_or_wr; + ZXIC_UINT32 ind_mem_id; + ZXIC_UINT32 ind_mem_addr; +}DPP_NPPU_PBU_STAT_IND_CMD_T; + +typedef struct dpp_nppu_pbu_stat_total_cnt_t +{ + ZXIC_UINT32 total_cnt; +}DPP_NPPU_PBU_STAT_TOTAL_CNT_T; + +typedef struct dpp_nppu_pbu_stat_idma_pub_cnt_t +{ + ZXIC_UINT32 idma_pub_cnt; +}DPP_NPPU_PBU_STAT_IDMA_PUB_CNT_T; + +typedef struct dpp_nppu_pbu_stat_lif_pub_cnt_t +{ + ZXIC_UINT32 lif_pub_cnt; +}DPP_NPPU_PBU_STAT_LIF_PUB_CNT_T; + +typedef struct dpp_nppu_pbu_stat_mc_total_cnt_t +{ + ZXIC_UINT32 mc_total_cnt; +}DPP_NPPU_PBU_STAT_MC_TOTAL_CNT_T; + +typedef struct dpp_nppu_pbu_stat_pbu_thram_init_done_t +{ + ZXIC_UINT32 pbu_thram_init_done; +}DPP_NPPU_PBU_STAT_PBU_THRAM_INIT_DONE_T; + +typedef struct dpp_nppu_pbu_stat_ifb_fptr_init_done_t +{ + ZXIC_UINT32 ifb_fptr_init_done; +}DPP_NPPU_PBU_STAT_IFB_FPTR_INIT_DONE_T; + +typedef struct dpp_nppu_isu_cfg_weight_normal_uc_t +{ + ZXIC_UINT32 weight_normal_uc; +}DPP_NPPU_ISU_CFG_WEIGHT_NORMAL_UC_T; + +typedef struct dpp_nppu_isu_cfg_fabric_or_saip_t +{ + ZXIC_UINT32 fabric_or_saip; +}DPP_NPPU_ISU_CFG_FABRIC_OR_SAIP_T; + +typedef struct dpp_nppu_isu_stat_ind_status_t +{ + ZXIC_UINT32 ind_access_done; +}DPP_NPPU_ISU_STAT_IND_STATUS_T; + +typedef struct dpp_nppu_isu_stat_ind_cmd_t +{ + ZXIC_UINT32 ind_rd_or_wr; + ZXIC_UINT32 ind_mem_id; + ZXIC_UINT32 ind_mem_addr; +}DPP_NPPU_ISU_STAT_IND_CMD_T; + +typedef struct dpp_nppu_isu_stat_ind_dat0_t +{ + ZXIC_UINT32 ind_dat0; +}DPP_NPPU_ISU_STAT_IND_DAT0_T; + +typedef struct dpp_nppu_odma_cfg_ind_access_done_t +{ + ZXIC_UINT32 ind_access_done; +}DPP_NPPU_ODMA_CFG_IND_ACCESS_DONE_T; + +typedef struct dpp_nppu_odma_cfg_ind_command_t +{ + ZXIC_UINT32 ind_rd_or_wr; + ZXIC_UINT32 ind_mem_id; + ZXIC_UINT32 ind_mem_addr; +}DPP_NPPU_ODMA_CFG_IND_COMMAND_T; + +typedef struct dpp_nppu_odma_cfg_ind_dat0_t +{ + ZXIC_UINT32 ind_dat0; +}DPP_NPPU_ODMA_CFG_IND_DAT0_T; + +typedef struct dpp_nppu_odma_cfg_ind_dat1_t +{ + ZXIC_UINT32 ind_dat1; +}DPP_NPPU_ODMA_CFG_IND_DAT1_T; + +typedef struct dpp_nppu_odma_cfg_fabric_or_saip_t +{ + ZXIC_UINT32 fabric_or_saip; +}DPP_NPPU_ODMA_CFG_FABRIC_OR_SAIP_T; + +typedef struct dpp_nppu_odma_cfg_max_pkt_len_t +{ + ZXIC_UINT32 max_pkt_len; +}DPP_NPPU_ODMA_CFG_MAX_PKT_LEN_T; + +typedef struct dpp_nppu_odma_cfg_age_en_t +{ + ZXIC_UINT32 age_en; +}DPP_NPPU_ODMA_CFG_AGE_EN_T; + +typedef struct dpp_nppu_odma_cfg_age_mode_t +{ + ZXIC_UINT32 age_mode; +}DPP_NPPU_ODMA_CFG_AGE_MODE_T; + +typedef struct dpp_nppu_odma_cfg_age_value_time_t +{ + ZXIC_UINT32 age_value_time; +}DPP_NPPU_ODMA_CFG_AGE_VALUE_TIME_T; + +typedef struct dpp_nppu_odma_cfg_age_value_room_t +{ + ZXIC_UINT32 age_value_room; +}DPP_NPPU_ODMA_CFG_AGE_VALUE_ROOM_T; + +typedef struct dpp_nppu_odma_cfg_age_out_cnt_t +{ + ZXIC_UINT32 age_out_cnt; +}DPP_NPPU_ODMA_CFG_AGE_OUT_CNT_T; + +typedef struct dpp_nppu_odma_cfg_token_value_a_t +{ + ZXIC_UINT32 token_value_a; +}DPP_NPPU_ODMA_CFG_TOKEN_VALUE_A_T; + +typedef struct dpp_nppu_odma_cfg_token_value_b_t +{ + ZXIC_UINT32 token_value_b; +}DPP_NPPU_ODMA_CFG_TOKEN_VALUE_B_T; + +typedef struct dpp_nppu_odma_cfg_cfg_shap_en_p0_t +{ + ZXIC_UINT32 cfg_shap_en_p0; +}DPP_NPPU_ODMA_CFG_CFG_SHAP_EN_P0_T; + +typedef struct dpp_nppu_odma_cfg_cfg_shap_en_p1_t +{ + ZXIC_UINT32 cfg_shap_en_p1; +}DPP_NPPU_ODMA_CFG_CFG_SHAP_EN_P1_T; + +typedef struct dpp_nppu_odma_cfg_cfg_shap_en_tm_t +{ + ZXIC_UINT32 cfg_shap_en_tm; +}DPP_NPPU_ODMA_CFG_CFG_SHAP_EN_TM_T; + +typedef struct dpp_nppu_odma_stat_ind_status_t +{ + ZXIC_UINT32 ind_access_done; +}DPP_NPPU_ODMA_STAT_IND_STATUS_T; + +typedef struct dpp_nppu_odma_stat_ind_cmd_t +{ + ZXIC_UINT32 ind_rd_or_wr; + ZXIC_UINT32 ind_mem_id; + ZXIC_UINT32 ind_mem_addr; +}DPP_NPPU_ODMA_STAT_IND_CMD_T; + +typedef struct dpp_nppu_odma_stat_ind_data0_t +{ + ZXIC_UINT32 ind_dat0; +}DPP_NPPU_ODMA_STAT_IND_DATA0_T; + +typedef struct dpp_nppu_odma_stat_debug_cnt_cfg_t +{ + ZXIC_UINT32 debug_cnt_ovf_mode; + ZXIC_UINT32 debug_cnt_rdclr_mode; + ZXIC_UINT32 user_cnt_value; +}DPP_NPPU_ODMA_STAT_DEBUG_CNT_CFG_T; + +typedef struct dpp_nppu_oam_cfg_bfd_firstchk_th_t +{ + ZXIC_UINT32 bfd_firstchk_th; +}DPP_NPPU_OAM_CFG_BFD_FIRSTCHK_TH_T; + +typedef struct dpp_nppu_pbu_cfg_memid_0_pbu_fc_idmath_ram_t +{ + ZXIC_UINT32 lif_th_15; + ZXIC_UINT32 lif_prv_15; + ZXIC_UINT32 idma_prv_15; + ZXIC_UINT32 idma_th_cos0_15; + ZXIC_UINT32 idma_th_cos1_15; + ZXIC_UINT32 idma_th_cos2_15; + ZXIC_UINT32 idma_th_cos3_15; + ZXIC_UINT32 idma_th_cos4_15; + ZXIC_UINT32 idma_th_cos5_15; + ZXIC_UINT32 idma_th_cos6_15; + ZXIC_UINT32 idma_th_cos7_15; +}DPP_NPPU_PBU_CFG_MEMID_0_PBU_FC_IDMATH_RAM_T; + +typedef struct dpp_nppu_pbu_cfg_memid_1_pbu_fc_macth_ram_t +{ + ZXIC_UINT32 cos7_th; + ZXIC_UINT32 cos6_th; + ZXIC_UINT32 cos5_th; + ZXIC_UINT32 cos4_th; + ZXIC_UINT32 cos3_th; + ZXIC_UINT32 cos2_th; + ZXIC_UINT32 cos1_th; + ZXIC_UINT32 cos0_th; +}DPP_NPPU_PBU_CFG_MEMID_1_PBU_FC_MACTH_RAM_T; + +typedef struct dpp_nppu_pbu_stat_memid_1_all_kind_port_cnt_t +{ + ZXIC_UINT32 peak_port_cnt; + ZXIC_UINT32 current_port_cnt; +}DPP_NPPU_PBU_STAT_MEMID_1_ALL_KIND_PORT_CNT_T; + +typedef struct dpp_nppu_pbu_stat_memid_2_ppu_pbu_ifb_req_vld_cnt_t +{ + ZXIC_UINT32 ppu_pbu_ifb_req_vld_cnt; +}DPP_NPPU_PBU_STAT_MEMID_2_PPU_PBU_IFB_REQ_VLD_CNT_T; + +typedef struct dpp_nppu_pbu_stat_memid_2_pbu_ppu_ifb_rsp_vld_cnt_t +{ + ZXIC_UINT32 pbu_ppu_ifb_rsp_vld_cnt; +}DPP_NPPU_PBU_STAT_MEMID_2_PBU_PPU_IFB_RSP_VLD_CNT_T; + +typedef struct dpp_nppu_pbu_stat_memid_2_odma_pbu_recy_ptr_vld_cnt_t +{ + ZXIC_UINT32 odma_pbu_recy_ptr_vld_cnt; +}DPP_NPPU_PBU_STAT_MEMID_2_ODMA_PBU_RECY_PTR_VLD_CNT_T; + +typedef struct dpp_nppu_pbu_stat_memid_2_ppu_pbu_mcode_pf_req_cnt_t +{ + ZXIC_UINT32 ppu_pbu_mcode_pf_req_cnt; +}DPP_NPPU_PBU_STAT_MEMID_2_PPU_PBU_MCODE_PF_REQ_CNT_T; + +typedef struct dpp_nppu_pbu_stat_memid_2_pbu_ppu_mcode_pf_rsp_cnt_t +{ + ZXIC_UINT32 pbu_ppu_mcode_pf_rsp_cnt; +}DPP_NPPU_PBU_STAT_MEMID_2_PBU_PPU_MCODE_PF_RSP_CNT_T; + +typedef struct dpp_nppu_pbu_stat_memid_2_ppu_pbu_logic_pf_req_cnt_t +{ + ZXIC_UINT32 ppu_pbu_logic_pf_req_cnt; +}DPP_NPPU_PBU_STAT_MEMID_2_PPU_PBU_LOGIC_PF_REQ_CNT_T; + +typedef struct dpp_nppu_pbu_stat_memid_2_pbu_ppu_logic_pf_rsp_cnt_t +{ + ZXIC_UINT32 pbu_ppu_logic_pf_rsp_cnt; +}DPP_NPPU_PBU_STAT_MEMID_2_PBU_PPU_LOGIC_PF_RSP_CNT_T; + +typedef struct dpp_nppu_pbu_stat_memid_2_ppu_use_ptr_pulse_cnt_t +{ + ZXIC_UINT32 ppu_use_ptr_pulse_cnt; +}DPP_NPPU_PBU_STAT_MEMID_2_PPU_USE_PTR_PULSE_CNT_T; + +typedef struct dpp_nppu_pbu_stat_memid_2_ppu_pbu_wb_vld_cnt_t +{ + ZXIC_UINT32 ppu_pbu_wb_vld_cnt; +}DPP_NPPU_PBU_STAT_MEMID_2_PPU_PBU_WB_VLD_CNT_T; + +typedef struct dpp_nppu_pbu_stat_memid_2_pbu_ppu_reorder_para_vld_cnt_t +{ + ZXIC_UINT32 pbu_ppu_reorder_para_vld_cnt; +}DPP_NPPU_PBU_STAT_MEMID_2_PBU_PPU_REORDER_PARA_VLD_CNT_T; + +typedef struct dpp_nppu_pbu_stat_memid_2_se_pbu_dpi_key_vld_cnt_t +{ + ZXIC_UINT32 se_pbu_dpi_key_vld_cnt; +}DPP_NPPU_PBU_STAT_MEMID_2_SE_PBU_DPI_KEY_VLD_CNT_T; + +typedef struct dpp_nppu_pbu_stat_memid_2_pbu_se_dpi_rsp_datvld_cnt_t +{ + ZXIC_UINT32 pbu_se_dpi_rsp_datvld_cnt; +}DPP_NPPU_PBU_STAT_MEMID_2_PBU_SE_DPI_RSP_DATVLD_CNT_T; + +typedef struct dpp_nppu_pbu_stat_memid_2_odma_pbu_ifb_rd1_cnt_t +{ + ZXIC_UINT32 odma_pbu_ifb_rd1_cnt; +}DPP_NPPU_PBU_STAT_MEMID_2_ODMA_PBU_IFB_RD1_CNT_T; + +typedef struct dpp_nppu_pbu_stat_memid_2_odma_pbu_ifb_rd2_cnt_t +{ + ZXIC_UINT32 odma_pbu_ifb_rd2_cnt; +}DPP_NPPU_PBU_STAT_MEMID_2_ODMA_PBU_IFB_RD2_CNT_T; + +typedef struct dpp_nppu_pbu_stat_memid_2_pbu_ppu_mcode_pf_no_rsp_cnt_t +{ + ZXIC_UINT32 pbu_ppu_mcode_pf_no_rsp_cnt; +}DPP_NPPU_PBU_STAT_MEMID_2_PBU_PPU_MCODE_PF_NO_RSP_CNT_T; + +typedef struct dpp_nppu_pbu_stat_memid_2_pbu_ppu_logic_pf_no_rsp_cnt_t +{ + ZXIC_UINT32 pbu_ppu_logic_pf_no_rsp_cnt; +}DPP_NPPU_PBU_STAT_MEMID_2_PBU_PPU_LOGIC_PF_NO_RSP_CNT_T; + +typedef struct dpp_nppu_pbu_stat_memid_3_cpu_rd_ifb_data_t +{ + ZXIC_UINT32 cpu_rd_ifb_data; +}DPP_NPPU_PBU_STAT_MEMID_3_CPU_RD_IFB_DATA_T; + +typedef struct dpp_nppu_pbu_stat_memid_4_mux_sel_rgt_t +{ + ZXIC_UINT32 current_port_cnt; +}DPP_NPPU_PBU_STAT_MEMID_4_MUX_SEL_RGT_T; + +typedef struct dpp_nppu_pbu_stat_memid_5_port_pub_cnt_t +{ + ZXIC_UINT32 port_pub_cnt; +}DPP_NPPU_PBU_STAT_MEMID_5_PORT_PUB_CNT_T; + +typedef struct dpp_nppu_idma_stat_memid_1_idma_o_isu_pkt_pulse_total_cnt_t +{ + ZXIC_UINT32 idma_o_isu_pkt_pulse_total_cnt; +}DPP_NPPU_IDMA_STAT_MEMID_1_IDMA_O_ISU_PKT_PULSE_TOTAL_CNT_T; + +typedef struct dpp_nppu_idma_stat_memid_1_idma_o_isu_epkt_pulse_total_cnt_t +{ + ZXIC_UINT32 idma_o_isu_epkt_pulse_total_cnt; +}DPP_NPPU_IDMA_STAT_MEMID_1_IDMA_O_ISU_EPKT_PULSE_TOTAL_CNT_T; + +typedef struct dpp_nppu_idma_stat_memid_1_idma_dispkt_pulse_total_cnt_t +{ + ZXIC_UINT32 idma_dispkt_pulse_total_cnt; +}DPP_NPPU_IDMA_STAT_MEMID_1_IDMA_DISPKT_PULSE_TOTAL_CNT_T; + +typedef struct dpp_nppu_idma_stat_memid_0_idma_o_isu_pkt_pulse_cnt_t +{ + ZXIC_UINT32 idma_o_isu_pkt_pulse_cnt; +}DPP_NPPU_IDMA_STAT_MEMID_0_IDMA_O_ISU_PKT_PULSE_CNT_T; + +typedef struct dpp_nppu_idma_stat_memid_0_idma_o_isu_epkt_pulse_cnt_t +{ + ZXIC_UINT32 idma_o_isu_epkt_pulse_cnt; +}DPP_NPPU_IDMA_STAT_MEMID_0_IDMA_O_ISU_EPKT_PULSE_CNT_T; + +typedef struct dpp_nppu_idma_stat_memid_0_idma_dispkt_pulse_cnt_t +{ + ZXIC_UINT32 idma_dispkt_pulse_cnt; +}DPP_NPPU_IDMA_STAT_MEMID_0_IDMA_DISPKT_PULSE_CNT_T; + +typedef struct dpp_nppu_mr_cfg_ind_access_states_t +{ + ZXIC_UINT32 ind_access_done; +}DPP_NPPU_MR_CFG_IND_ACCESS_STATES_T; + +typedef struct dpp_nppu_mr_cfg_ind_access_cmd0_t +{ + ZXIC_UINT32 wr_mode; + ZXIC_UINT32 rd_or_wr; + ZXIC_UINT32 ind_access_addr0; +}DPP_NPPU_MR_CFG_IND_ACCESS_CMD0_T; + +typedef struct dpp_nppu_mr_cfg_ind_access_data0_t +{ + ZXIC_UINT32 ind_access_data0; +}DPP_NPPU_MR_CFG_IND_ACCESS_DATA0_T; + +typedef struct dpp_nppu_mr_cfg_ind_access_data1_t +{ + ZXIC_UINT32 ind_access_data1; +}DPP_NPPU_MR_CFG_IND_ACCESS_DATA1_T; + +typedef struct dpp_nppu_mr_cfg_ind_access_cmd1_t +{ + ZXIC_UINT32 ind_access_addr1; +}DPP_NPPU_MR_CFG_IND_ACCESS_CMD1_T; + +typedef struct dpp_nppu_mr_cfg_mr_init_done_t +{ + ZXIC_UINT32 mr_init_done; +}DPP_NPPU_MR_CFG_MR_INIT_DONE_T; + +typedef struct dpp_nppu_mr_cfg_cnt_mode_reg_t +{ + ZXIC_UINT32 cfgmt_count_rd_mode; + ZXIC_UINT32 cfgmt_count_overflow_mode; +}DPP_NPPU_MR_CFG_CNT_MODE_REG_T; + +typedef struct dpp_nppu_mr_cfg_cfg_ecc_bypass_read_t +{ + ZXIC_UINT32 cfg_ecc_bypass_read; +}DPP_NPPU_MR_CFG_CFG_ECC_BYPASS_READ_T; + +typedef struct dpp_nppu_mr_cfg_cfg_rep_mod_t +{ + ZXIC_UINT32 cfg_rep_mod; +}DPP_NPPU_MR_CFG_CFG_REP_MOD_T; + +typedef struct dpp_nppu_mr_cfg_block_ptr_fifo_aful_th_t +{ + ZXIC_UINT32 block_ptr3_fifo_aful_th; + ZXIC_UINT32 block_ptr2_fifo_aful_th; + ZXIC_UINT32 block_ptr1_fifo_aful_th; + ZXIC_UINT32 block_ptr0_fifo_aful_th; +}DPP_NPPU_MR_CFG_BLOCK_PTR_FIFO_AFUL_TH_T; + +typedef struct dpp_nppu_mr_cfg_pre_rcv_ptr_fifo_aful_th_t +{ + ZXIC_UINT32 pre_rcv_ptr3_fifo_aful_th; + ZXIC_UINT32 pre_rcv_ptr2_fifo_aful_th; + ZXIC_UINT32 pre_rcv_ptr1_fifo_aful_th; + ZXIC_UINT32 pre_rcv_ptr0_fifo_aful_th; +}DPP_NPPU_MR_CFG_PRE_RCV_PTR_FIFO_AFUL_TH_T; + +typedef struct dpp_nppu_mr_cfg_mgid_fifo_aful_th_t +{ + ZXIC_UINT32 mgid3_fifo_aful_th; + ZXIC_UINT32 mgid2_fifo_aful_th; + ZXIC_UINT32 mgid1_fifo_aful_th; + ZXIC_UINT32 mgid0_fifo_aful_th; +}DPP_NPPU_MR_CFG_MGID_FIFO_AFUL_TH_T; + +typedef struct dpp_nppu_mr_cfg_rep_cmd_fifo_aful_th_t +{ + ZXIC_UINT32 rep_cmd3_fifo_aful_th; + ZXIC_UINT32 rep_cmd2_fifo_aful_th; + ZXIC_UINT32 rep_cmd1_fifo_aful_th; + ZXIC_UINT32 rep_cmd0_fifo_aful_th; +}DPP_NPPU_MR_CFG_REP_CMD_FIFO_AFUL_TH_T; + +typedef struct dpp_nppu_mr_cfg_mr_int_mask_1_t +{ + ZXIC_UINT32 free_ptr0_fifo_full_mask; + ZXIC_UINT32 free_ptr1_fifo_full_mask; + ZXIC_UINT32 free_ptr2_fifo_full_mask; + ZXIC_UINT32 free_ptr3_fifo_full_mask; + ZXIC_UINT32 block_ptr0_fifo_full_mask; + ZXIC_UINT32 block_ptr1_fifo_full_mask; + ZXIC_UINT32 block_ptr2_fifo_full_mask; + ZXIC_UINT32 block_ptr3_fifo_full_mask; + ZXIC_UINT32 mgid0_fifo_full_mask; + ZXIC_UINT32 mgid1_fifo_full_mask; + ZXIC_UINT32 mgid2_fifo_full_mask; + ZXIC_UINT32 mgid3_fifo_full_mask; + ZXIC_UINT32 pre_rcv_ptr0_fifo_full_mask; + ZXIC_UINT32 pre_rcv_ptr1_fifo_full_mask; + ZXIC_UINT32 pre_rcv_ptr2_fifo_full_mask; + ZXIC_UINT32 pre_rcv_ptr3_fifo_full_mask; + ZXIC_UINT32 rep_cmd0_fifo_full_mask; + ZXIC_UINT32 rep_cmd1_fifo_full_mask; + ZXIC_UINT32 rep_cmd2_fifo_full_mask; + ZXIC_UINT32 rep_cmd3_fifo_full_mask; +}DPP_NPPU_MR_CFG_MR_INT_MASK_1_T; + +typedef struct dpp_nppu_mr_cfg_mr_int_mask_2_t +{ + ZXIC_UINT32 free_ptr0_fifo_udf_mask; + ZXIC_UINT32 free_ptr1_fifo_udf_mask; + ZXIC_UINT32 free_ptr2_fifo_udf_mask; + ZXIC_UINT32 free_ptr3_fifo_udf_mask; + ZXIC_UINT32 block_ptr0_fifo_udf_mask; + ZXIC_UINT32 block_ptr1_fifo_udf_mask; + ZXIC_UINT32 block_ptr2_fifo_udf_mask; + ZXIC_UINT32 block_ptr3_fifo_udf_mask; + ZXIC_UINT32 mgid0_fifo_udf_mask; + ZXIC_UINT32 mgid1_fifo_udf_mask; + ZXIC_UINT32 mgid2_fifo_udf_mask; + ZXIC_UINT32 mgid3_fifo_udf_mask; + ZXIC_UINT32 pre_rcv_ptr0_fifo_udf_mask; + ZXIC_UINT32 pre_rcv_ptr1_fifo_udf_mask; + ZXIC_UINT32 pre_rcv_ptr2_fifo_udf_mask; + ZXIC_UINT32 pre_rcv_ptr3_fifo_udf_mask; + ZXIC_UINT32 rep_cmd0_fifo_udf_mask; + ZXIC_UINT32 rep_cmd1_fifo_udf_mask; + ZXIC_UINT32 rep_cmd2_fifo_udf_mask; + ZXIC_UINT32 rep_cmd3_fifo_udf_mask; +}DPP_NPPU_MR_CFG_MR_INT_MASK_2_T; + +typedef struct dpp_nppu_mr_cfg_mr_int_mask_3_t +{ + ZXIC_UINT32 free_ptr0_fifo_ovf_mask; + ZXIC_UINT32 free_ptr1_fifo_ovf_mask; + ZXIC_UINT32 free_ptr2_fifo_ovf_mask; + ZXIC_UINT32 free_ptr3_fifo_ovf_mask; + ZXIC_UINT32 block_ptr0_fifo_ovf_mask; + ZXIC_UINT32 block_ptr1_fifo_ovf_mask; + ZXIC_UINT32 block_ptr2_fifo_ovf_mask; + ZXIC_UINT32 block_ptr3_fifo_ovf_mask; + ZXIC_UINT32 mgid0_fifo_ovf_mask; + ZXIC_UINT32 mgid1_fifo_ovf_mask; + ZXIC_UINT32 mgid2_fifo_ovf_mask; + ZXIC_UINT32 mgid3_fifo_ovf_mask; + ZXIC_UINT32 pre_rcv_ptr0_fifo_ovf_mask; + ZXIC_UINT32 pre_rcv_ptr1_fifo_ovf_mask; + ZXIC_UINT32 pre_rcv_ptr2_fifo_ovf_mask; + ZXIC_UINT32 pre_rcv_ptr3_fifo_ovf_mask; + ZXIC_UINT32 rep_cmd0_fifo_ovf_mask; + ZXIC_UINT32 rep_cmd1_fifo_ovf_mask; + ZXIC_UINT32 rep_cmd2_fifo_ovf_mask; + ZXIC_UINT32 rep_cmd3_fifo_ovf_mask; +}DPP_NPPU_MR_CFG_MR_INT_MASK_3_T; + +typedef struct dpp_nppu_mr_cfg_mr_int_mask_4_t +{ + ZXIC_UINT32 data_buf0_ram_parity_err_mask; + ZXIC_UINT32 data_buf1_ram_parity_err_mask; + ZXIC_UINT32 data_buf2_ram_parity_err_mask; + ZXIC_UINT32 data_buf3_ram_parity_err_mask; + ZXIC_UINT32 mlt_ecc_single_err_mask; + ZXIC_UINT32 free_ptr0_fifo_ecc_single_err_mask; + ZXIC_UINT32 free_ptr1_fifo_ecc_single_err_mask; + ZXIC_UINT32 free_ptr2_fifo_ecc_single_err_mask; + ZXIC_UINT32 free_ptr3_fifo_ecc_single_err_mask; + ZXIC_UINT32 block_ptr0_fifo_ecc_single_err_mask; + ZXIC_UINT32 block_ptr1_fifo_ecc_single_err_mask; + ZXIC_UINT32 block_ptr2_fifo_ecc_single_err_mask; + ZXIC_UINT32 block_ptr3_fifo_ecc_single_err_mask; + ZXIC_UINT32 mgid0_fifo_ecc_single_err_mask; + ZXIC_UINT32 mgid1_fifo_ecc_single_err_mask; + ZXIC_UINT32 mgid2_fifo_ecc_single_err_mask; + ZXIC_UINT32 mgid3_fifo_ecc_single_err_mask; + ZXIC_UINT32 pre_rcv_ptr0_fifo_ecc_single_err_mask; + ZXIC_UINT32 pre_rcv_ptr1_fifo_ecc_single_err_mask; + ZXIC_UINT32 pre_rcv_ptr2_fifo_ecc_single_err_mask; + ZXIC_UINT32 pre_rcv_ptr3_fifo_ecc_single_err_mask; + ZXIC_UINT32 rep_cmd0_fifo_ecc_single_err_mask; + ZXIC_UINT32 rep_cmd1_fifo_ecc_single_err_mask; + ZXIC_UINT32 rep_cmd2_fifo_ecc_single_err_mask; + ZXIC_UINT32 rep_cmd3_fifo_ecc_single_err_mask; +}DPP_NPPU_MR_CFG_MR_INT_MASK_4_T; + +typedef struct dpp_nppu_mr_cfg_mr_states_1_t +{ + ZXIC_UINT32 free_ptr0_fifo_full; + ZXIC_UINT32 free_ptr1_fifo_full; + ZXIC_UINT32 free_ptr2_fifo_full; + ZXIC_UINT32 free_ptr3_fifo_full; + ZXIC_UINT32 block_ptr0_fifo_full; + ZXIC_UINT32 block_ptr1_fifo_full; + ZXIC_UINT32 block_ptr2_fifo_full; + ZXIC_UINT32 block_ptr3_fifo_full; + ZXIC_UINT32 mgid0_fifo_full; + ZXIC_UINT32 mgid1_fifo_full; + ZXIC_UINT32 mgid2_fifo_full; + ZXIC_UINT32 mgid3_fifo_full; + ZXIC_UINT32 pre_rcv_ptr0_fifo_full; + ZXIC_UINT32 pre_rcv_ptr1_fifo_full; + ZXIC_UINT32 pre_rcv_ptr2_fifo_full; + ZXIC_UINT32 pre_rcv_ptr3_fifo_full; + ZXIC_UINT32 rep_cmd0_fifo_full; + ZXIC_UINT32 rep_cmd1_fifo_full; + ZXIC_UINT32 rep_cmd2_fifo_full; + ZXIC_UINT32 rep_cmd3_fifo_full; +}DPP_NPPU_MR_CFG_MR_STATES_1_T; + +typedef struct dpp_nppu_mr_cfg_mr_states_2_t +{ + ZXIC_UINT32 free_ptr0_fifo_udf; + ZXIC_UINT32 free_ptr1_fifo_udf; + ZXIC_UINT32 free_ptr2_fifo_udf; + ZXIC_UINT32 free_ptr3_fifo_udf; + ZXIC_UINT32 block_ptr0_fifo_udf; + ZXIC_UINT32 block_ptr1_fifo_udf; + ZXIC_UINT32 block_ptr2_fifo_udf; + ZXIC_UINT32 block_ptr3_fifo_udf; + ZXIC_UINT32 mgid0_fifo_udf; + ZXIC_UINT32 mgid1_fifo_udf; + ZXIC_UINT32 mgid2_fifo_udf; + ZXIC_UINT32 mgid3_fifo_udf; + ZXIC_UINT32 pre_rcv_ptr0_fifo_udf; + ZXIC_UINT32 pre_rcv_ptr1_fifo_udf; + ZXIC_UINT32 pre_rcv_ptr2_fifo_udf; + ZXIC_UINT32 pre_rcv_ptr3_fifo_udf; + ZXIC_UINT32 rep_cmd0_fifo_udf; + ZXIC_UINT32 rep_cmd1_fifo_udf; + ZXIC_UINT32 rep_cmd2_fifo_udf; + ZXIC_UINT32 rep_cmd3_fifo_udf; +}DPP_NPPU_MR_CFG_MR_STATES_2_T; + +typedef struct dpp_nppu_mr_cfg_mr_states_3_t +{ + ZXIC_UINT32 free_ptr0_fifo_ovf; + ZXIC_UINT32 free_ptr1_fifo_ovf; + ZXIC_UINT32 free_ptr2_fifo_ovf; + ZXIC_UINT32 free_ptr3_fifo_ovf; + ZXIC_UINT32 block_ptr0_fifo_ovf; + ZXIC_UINT32 block_ptr1_fifo_ovf; + ZXIC_UINT32 block_ptr2_fifo_ovf; + ZXIC_UINT32 block_ptr3_fifo_ovf; + ZXIC_UINT32 mgid0_fifo_ovf; + ZXIC_UINT32 mgid1_fifo_ovf; + ZXIC_UINT32 mgid2_fifo_ovf; + ZXIC_UINT32 mgid3_fifo_ovf; + ZXIC_UINT32 pre_rcv_ptr0_fifo_ovf; + ZXIC_UINT32 pre_rcv_ptr1_fifo_ovf; + ZXIC_UINT32 pre_rcv_ptr2_fifo_ovf; + ZXIC_UINT32 pre_rcv_ptr3_fifo_ovf; + ZXIC_UINT32 rep_cmd0_fifo_ovf; + ZXIC_UINT32 rep_cmd1_fifo_ovf; + ZXIC_UINT32 rep_cmd2_fifo_ovf; + ZXIC_UINT32 rep_cmd3_fifo_ovf; +}DPP_NPPU_MR_CFG_MR_STATES_3_T; + +typedef struct dpp_nppu_mr_cfg_mr_states_4_t +{ + ZXIC_UINT32 data_buf0_ram_parity_err; + ZXIC_UINT32 data_buf1_ram_parity_err; + ZXIC_UINT32 data_buf2_ram_parity_err; + ZXIC_UINT32 data_buf3_ram_parity_err; + ZXIC_UINT32 mlt_ecc_single_err; + ZXIC_UINT32 free_ptr0_fifo_ecc_single_err; + ZXIC_UINT32 free_ptr1_fifo_ecc_single_err; + ZXIC_UINT32 free_ptr2_fifo_ecc_single_err; + ZXIC_UINT32 free_ptr3_fifo_ecc_single_err; + ZXIC_UINT32 block_ptr0_fifo_ecc_single_err; + ZXIC_UINT32 block_ptr1_fifo_ecc_single_err; + ZXIC_UINT32 block_ptr2_fifo_ecc_single_err; + ZXIC_UINT32 block_ptr3_fifo_ecc_single_err; + ZXIC_UINT32 mgid0_fifo_ecc_single_err; + ZXIC_UINT32 mgid1_fifo_ecc_single_err; + ZXIC_UINT32 mgid2_fifo_ecc_single_err; + ZXIC_UINT32 mgid3_fifo_ecc_single_err; + ZXIC_UINT32 pre_rcv_ptr0_fifo_ecc_single_err; + ZXIC_UINT32 pre_rcv_ptr1_fifo_ecc_single_err; + ZXIC_UINT32 pre_rcv_ptr2_fifo_ecc_single_err; + ZXIC_UINT32 pre_rcv_ptr3_fifo_ecc_single_err; + ZXIC_UINT32 rep_cmd0_fifo_ecc_single_err; + ZXIC_UINT32 rep_cmd1_fifo_ecc_single_err; + ZXIC_UINT32 rep_cmd2_fifo_ecc_single_err; + ZXIC_UINT32 rep_cmd3_fifo_ecc_single_err; +}DPP_NPPU_MR_CFG_MR_STATES_4_T; + +typedef struct dpp_nppu_mr_cfg_mr_states_5_t +{ + ZXIC_UINT32 mlt_ecc_double_err; + ZXIC_UINT32 free_ptr0_fifo_ecc_double_err; + ZXIC_UINT32 free_ptr1_fifo_ecc_double_err; + ZXIC_UINT32 free_ptr2_fifo_ecc_double_err; + ZXIC_UINT32 free_ptr3_fifo_ecc_double_err; + ZXIC_UINT32 block_ptr0_fifo_ecc_double_err; + ZXIC_UINT32 block_ptr1_fifo_ecc_double_err; + ZXIC_UINT32 block_ptr2_fifo_ecc_double_err; + ZXIC_UINT32 block_ptr3_fifo_ecc_double_err; + ZXIC_UINT32 mgid0_fifo_ecc_double_err; + ZXIC_UINT32 mgid1_fifo_ecc_double_err; + ZXIC_UINT32 mgid2_fifo_ecc_double_err; + ZXIC_UINT32 mgid3_fifo_ecc_double_err; + ZXIC_UINT32 pre_rcv_ptr0_fifo_ecc_double_err; + ZXIC_UINT32 pre_rcv_ptr1_fifo_ecc_double_err; + ZXIC_UINT32 pre_rcv_ptr2_fifo_ecc_double_err; + ZXIC_UINT32 pre_rcv_ptr3_fifo_ecc_double_err; + ZXIC_UINT32 rep_cmd0_fifo_ecc_double_err; + ZXIC_UINT32 rep_cmd1_fifo_ecc_double_err; + ZXIC_UINT32 rep_cmd2_fifo_ecc_double_err; + ZXIC_UINT32 rep_cmd3_fifo_ecc_double_err; +}DPP_NPPU_MR_CFG_MR_STATES_5_T; + +typedef struct dpp_nppu_mr_cfg_mr_states_6_t +{ + ZXIC_UINT32 free_ptr0_fifo_empty; + ZXIC_UINT32 free_ptr1_fifo_empty; + ZXIC_UINT32 free_ptr2_fifo_empty; + ZXIC_UINT32 free_ptr3_fifo_empty; + ZXIC_UINT32 block_ptr0_fifo_empty; + ZXIC_UINT32 block_ptr1_fifo_empty; + ZXIC_UINT32 block_ptr2_fifo_empty; + ZXIC_UINT32 block_ptr3_fifo_empty; + ZXIC_UINT32 mgid0_fifo_empty; + ZXIC_UINT32 mgid1_fifo_empty; + ZXIC_UINT32 mgid2_fifo_empty; + ZXIC_UINT32 mgid3_fifo_empty; + ZXIC_UINT32 pre_rcv_ptr0_fifo_empty; + ZXIC_UINT32 pre_rcv_ptr1_fifo_empty; + ZXIC_UINT32 pre_rcv_ptr2_fifo_empty; + ZXIC_UINT32 pre_rcv_ptr3_fifo_empty; + ZXIC_UINT32 rep_cmd0_fifo_empty; + ZXIC_UINT32 rep_cmd1_fifo_empty; + ZXIC_UINT32 rep_cmd2_fifo_empty; + ZXIC_UINT32 rep_cmd3_fifo_empty; +}DPP_NPPU_MR_CFG_MR_STATES_6_T; + +typedef struct dpp_nppu_mr_cfg_mr_states_7_t +{ + ZXIC_UINT32 cos0_is_rep_busy; + ZXIC_UINT32 cos1_is_rep_busy; + ZXIC_UINT32 cos2_is_rep_busy; + ZXIC_UINT32 cos3_is_rep_busy; + ZXIC_UINT32 block_ptr0_fifo_non_sop_ren_rdy; + ZXIC_UINT32 block_ptr1_fifo_non_sop_ren_rdy; + ZXIC_UINT32 block_ptr2_fifo_non_sop_ren_rdy; + ZXIC_UINT32 block_ptr3_fifo_non_sop_ren_rdy; + ZXIC_UINT32 pre_rcv_ptr0_fifo_non_sop_ren_rdy; + ZXIC_UINT32 pre_rcv_ptr1_fifo_non_sop_ren_rdy; + ZXIC_UINT32 pre_rcv_ptr2_fifo_non_sop_ren_rdy; + ZXIC_UINT32 pre_rcv_ptr3_fifo_non_sop_ren_rdy; + ZXIC_UINT32 port_shap_rdy; + ZXIC_UINT32 mr_lif_group0_rdy_3; + ZXIC_UINT32 mr_lif_group0_rdy_2; + ZXIC_UINT32 mr_lif_group0_rdy_1; + ZXIC_UINT32 mr_lif_group0_rdy_0; + ZXIC_UINT32 pktrx_pfc_rdy_3; + ZXIC_UINT32 pktrx_pfc_rdy_2; + ZXIC_UINT32 pktrx_pfc_rdy_1; + ZXIC_UINT32 pktrx_pfc_rdy_0; + ZXIC_UINT32 pktrx_link_rdy; +}DPP_NPPU_MR_CFG_MR_STATES_7_T; + +typedef struct dpp_nppu_mr_cfg_mr_states_8_t +{ + ZXIC_UINT32 mr_head; +}DPP_NPPU_MR_CFG_MR_STATES_8_T; + +typedef struct dpp_nppu_mr_cfg_mr_sop_in_cnt_t +{ + ZXIC_UINT32 mr_sop_in_cnt; +}DPP_NPPU_MR_CFG_MR_SOP_IN_CNT_T; + +typedef struct dpp_nppu_mr_cfg_mr_eop_in_cnt_t +{ + ZXIC_UINT32 mr_eop_in_cnt; +}DPP_NPPU_MR_CFG_MR_EOP_IN_CNT_T; + +typedef struct dpp_nppu_mr_cfg_mr_sop_out_cnt_t +{ + ZXIC_UINT32 mr_sop_out_cnt; +}DPP_NPPU_MR_CFG_MR_SOP_OUT_CNT_T; + +typedef struct dpp_nppu_mr_cfg_mr_eop_out_cnt_t +{ + ZXIC_UINT32 mr_eop_out_cnt; +}DPP_NPPU_MR_CFG_MR_EOP_OUT_CNT_T; + +typedef struct dpp_nppu_mr_cfg_mr_cos0_in_cnt_t +{ + ZXIC_UINT32 mr_cos0_in_cnt; +}DPP_NPPU_MR_CFG_MR_COS0_IN_CNT_T; + +typedef struct dpp_nppu_mr_cfg_mr_cos1_in_cnt_t +{ + ZXIC_UINT32 mr_cos1_in_cnt; +}DPP_NPPU_MR_CFG_MR_COS1_IN_CNT_T; + +typedef struct dpp_nppu_mr_cfg_mr_cos2_in_cnt_t +{ + ZXIC_UINT32 mr_cos2_in_cnt; +}DPP_NPPU_MR_CFG_MR_COS2_IN_CNT_T; + +typedef struct dpp_nppu_mr_cfg_mr_cos3_in_cnt_t +{ + ZXIC_UINT32 mr_cos3_in_cnt; +}DPP_NPPU_MR_CFG_MR_COS3_IN_CNT_T; + +typedef struct dpp_nppu_mr_cfg_mr_cos0_out_cnt_t +{ + ZXIC_UINT32 mr_cos0_out_cnt; +}DPP_NPPU_MR_CFG_MR_COS0_OUT_CNT_T; + +typedef struct dpp_nppu_mr_cfg_mr_cos1_out_cnt_t +{ + ZXIC_UINT32 mr_cos1_out_cnt; +}DPP_NPPU_MR_CFG_MR_COS1_OUT_CNT_T; + +typedef struct dpp_nppu_mr_cfg_mr_cos2_out_cnt_t +{ + ZXIC_UINT32 mr_cos2_out_cnt; +}DPP_NPPU_MR_CFG_MR_COS2_OUT_CNT_T; + +typedef struct dpp_nppu_mr_cfg_mr_cos3_out_cnt_t +{ + ZXIC_UINT32 mr_cos3_out_cnt; +}DPP_NPPU_MR_CFG_MR_COS3_OUT_CNT_T; + +typedef struct dpp_nppu_mr_cfg_mr_err_in_cnt_t +{ + ZXIC_UINT32 mr_err_in_cnt; +}DPP_NPPU_MR_CFG_MR_ERR_IN_CNT_T; + +typedef struct dpp_nppu_mr_cfg_mr_cos0_sop_in_cnt_t +{ + ZXIC_UINT32 mr_cos0_sop_in_cnt; +}DPP_NPPU_MR_CFG_MR_COS0_SOP_IN_CNT_T; + +typedef struct dpp_nppu_mr_cfg_mr_cos0_eop_in_cnt_t +{ + ZXIC_UINT32 mr_cos0_eop_in_cnt; +}DPP_NPPU_MR_CFG_MR_COS0_EOP_IN_CNT_T; + +typedef struct dpp_nppu_mr_cfg_mr_cos1_sop_in_cnt_t +{ + ZXIC_UINT32 mr_cos1_sop_in_cnt; +}DPP_NPPU_MR_CFG_MR_COS1_SOP_IN_CNT_T; + +typedef struct dpp_nppu_mr_cfg_mr_cos1_eop_in_cnt_t +{ + ZXIC_UINT32 mr_cos1_eop_in_cnt; +}DPP_NPPU_MR_CFG_MR_COS1_EOP_IN_CNT_T; + +typedef struct dpp_nppu_mr_cfg_mr_cos2_sop_in_cnt_t +{ + ZXIC_UINT32 mr_cos2_sop_in_cnt; +}DPP_NPPU_MR_CFG_MR_COS2_SOP_IN_CNT_T; + +typedef struct dpp_nppu_mr_cfg_mr_cos2_eop_in_cnt_t +{ + ZXIC_UINT32 mr_cos2_eop_in_cnt; +}DPP_NPPU_MR_CFG_MR_COS2_EOP_IN_CNT_T; + +typedef struct dpp_nppu_mr_cfg_mr_cos3_sop_in_cnt_t +{ + ZXIC_UINT32 mr_cos3_sop_in_cnt; +}DPP_NPPU_MR_CFG_MR_COS3_SOP_IN_CNT_T; + +typedef struct dpp_nppu_mr_cfg_mr_cos3_eop_in_cnt_t +{ + ZXIC_UINT32 mr_cos3_eop_in_cnt; +}DPP_NPPU_MR_CFG_MR_COS3_EOP_IN_CNT_T; + +typedef struct dpp_nppu_mr_cfg_mr_cos0_in_err_cnt_t +{ + ZXIC_UINT32 mr_cos0_in_err_cnt; +}DPP_NPPU_MR_CFG_MR_COS0_IN_ERR_CNT_T; + +typedef struct dpp_nppu_mr_cfg_mr_cos1_in_err_cnt_t +{ + ZXIC_UINT32 mr_cos1_in_err_cnt; +}DPP_NPPU_MR_CFG_MR_COS1_IN_ERR_CNT_T; + +typedef struct dpp_nppu_mr_cfg_mr_cos2_in_err_cnt_t +{ + ZXIC_UINT32 mr_cos2_in_err_cnt; +}DPP_NPPU_MR_CFG_MR_COS2_IN_ERR_CNT_T; + +typedef struct dpp_nppu_mr_cfg_mr_cos3_in_err_cnt_t +{ + ZXIC_UINT32 mr_cos3_in_err_cnt; +}DPP_NPPU_MR_CFG_MR_COS3_IN_ERR_CNT_T; + +typedef struct dpp_nppu_mr_cfg_mr_cos0_sop_out_cnt_t +{ + ZXIC_UINT32 mr_cos0_sop_out_cnt; +}DPP_NPPU_MR_CFG_MR_COS0_SOP_OUT_CNT_T; + +typedef struct dpp_nppu_mr_cfg_mr_cos0_eop_out_cnt_t +{ + ZXIC_UINT32 mr_cos0_eop_out_cnt; +}DPP_NPPU_MR_CFG_MR_COS0_EOP_OUT_CNT_T; + +typedef struct dpp_nppu_mr_cfg_mr_cos1_sop_out_cnt_t +{ + ZXIC_UINT32 mr_cos1_sop_out_cnt; +}DPP_NPPU_MR_CFG_MR_COS1_SOP_OUT_CNT_T; + +typedef struct dpp_nppu_mr_cfg_mr_cos1_eop_out_cnt_t +{ + ZXIC_UINT32 mr_cos1_eop_out_cnt; +}DPP_NPPU_MR_CFG_MR_COS1_EOP_OUT_CNT_T; + +typedef struct dpp_nppu_mr_cfg_mr_cos2_sop_out_cnt_t +{ + ZXIC_UINT32 mr_cos2_sop_out_cnt; +}DPP_NPPU_MR_CFG_MR_COS2_SOP_OUT_CNT_T; + +typedef struct dpp_nppu_mr_cfg_mr_cos2_eop_out_cnt_t +{ + ZXIC_UINT32 mr_cos2_eop_out_cnt; +}DPP_NPPU_MR_CFG_MR_COS2_EOP_OUT_CNT_T; + +typedef struct dpp_nppu_mr_cfg_mr_cos3_sop_out_cnt_t +{ + ZXIC_UINT32 mr_cos3_sop_out_cnt; +}DPP_NPPU_MR_CFG_MR_COS3_SOP_OUT_CNT_T; + +typedef struct dpp_nppu_mr_cfg_mr_cos3_eop_out_cnt_t +{ + ZXIC_UINT32 mr_cos3_eop_out_cnt; +}DPP_NPPU_MR_CFG_MR_COS3_EOP_OUT_CNT_T; + +typedef struct dpp_nppu_mr_cfg_mr_mlt_unvld_cnt_t +{ + ZXIC_UINT32 mr_mlt_unvld_cnt; +}DPP_NPPU_MR_CFG_MR_MLT_UNVLD_CNT_T; + +typedef struct dpp_nppu_mr_cfg_mr_sop_eop_match_cfg_t +{ + ZXIC_UINT32 mr_sop_eop_macth_en; + ZXIC_UINT32 mr_sop_eop_macth_dicard_th; +}DPP_NPPU_MR_CFG_MR_SOP_EOP_MATCH_CFG_T; + +typedef struct dpp_nppu_mr_cfg_mr_mlt_unvld_mgid_t +{ + ZXIC_UINT32 mr_mlt_unvld_mgid; +}DPP_NPPU_MR_CFG_MR_MLT_UNVLD_MGID_T; + +typedef struct dpp_nppu_pktrx_cfg_isch_fifo_th_1_t +{ + ZXIC_UINT32 cfg_sch_fifo7_fc_th; + ZXIC_UINT32 cfg_sch_fifo6_fc_th; + ZXIC_UINT32 cfg_sch_fifo5_fc_th; + ZXIC_UINT32 cfg_sch_fifo4_fc_th; +}DPP_NPPU_PKTRX_CFG_ISCH_FIFO_TH_1_T; + +typedef struct dpp_nppu_pktrx_cfg_isch_fifo_th_2_t +{ + ZXIC_UINT32 cfg_sch_fifo3_drop_th; + ZXIC_UINT32 cfg_sch_fifo1_drop_th; + ZXIC_UINT32 cfg_sch_fifo0_drop_th; + ZXIC_UINT32 cfg_sch_fifo8_fc_th; +}DPP_NPPU_PKTRX_CFG_ISCH_FIFO_TH_2_T; + +typedef struct dpp_nppu_pktrx_cfg_isch_fifo_th_3_t +{ + ZXIC_UINT32 cfg_sch_fifo6_drop_th; + ZXIC_UINT32 cfg_sch_fifo5_drop_th; + ZXIC_UINT32 cfg_sch_fifo4_drop_th; + ZXIC_UINT32 cfg_sch_fifo2_drop_th; +}DPP_NPPU_PKTRX_CFG_ISCH_FIFO_TH_3_T; + +typedef struct dpp_nppu_pktrx_cfg_isch_fifo_th_4_t +{ + ZXIC_UINT32 cfg_sch_fifo9_fc_th; + ZXIC_UINT32 cfg_sch_fifo9_drop_th; + ZXIC_UINT32 cfg_sch_fifo8_drop_th; + ZXIC_UINT32 cfg_sch_fifo7_drop_th; +}DPP_NPPU_PKTRX_CFG_ISCH_FIFO_TH_4_T; + +typedef struct dpp_nppu_pktrx_cfg_isch_cfg_0_t +{ + ZXIC_UINT32 cfg_sch_wrr1_weight1; +}DPP_NPPU_PKTRX_CFG_ISCH_CFG_0_T; + +typedef struct dpp_nppu_pktrx_cfg_hdu_ex_tpid_0_t +{ + ZXIC_UINT32 cfg_type0; + ZXIC_UINT32 cfg_type1; +}DPP_NPPU_PKTRX_CFG_HDU_EX_TPID_0_T; + +typedef struct dpp_nppu_pktrx_cfg_hdu_ex_tpid_1_t +{ + ZXIC_UINT32 cfg_type2; + ZXIC_UINT32 cfg_type3; +}DPP_NPPU_PKTRX_CFG_HDU_EX_TPID_1_T; + +typedef struct dpp_nppu_pktrx_cfg_hdu_int_tpid_0_t +{ + ZXIC_UINT32 cfg_inner_type0; + ZXIC_UINT32 cfg_inner_type1; +}DPP_NPPU_PKTRX_CFG_HDU_INT_TPID_0_T; + +typedef struct dpp_nppu_pktrx_cfg_hdu_int_tpid_1_t +{ + ZXIC_UINT32 cfg_inner_type2; + ZXIC_UINT32 cfg_inner_type3; +}DPP_NPPU_PKTRX_CFG_HDU_INT_TPID_1_T; + +typedef struct dpp_nppu_pktrx_cfg_hdu_hdlc_0_t +{ + ZXIC_UINT32 hdlc_cfg0_type; + ZXIC_UINT32 hdlc_cfg1_type; +}DPP_NPPU_PKTRX_CFG_HDU_HDLC_0_T; + +typedef struct dpp_nppu_pktrx_cfg_hdu_hdlc_1_t +{ + ZXIC_UINT32 hdlc_cfg2_type; + ZXIC_UINT32 hdlc_cfg3_type; +}DPP_NPPU_PKTRX_CFG_HDU_HDLC_1_T; + +typedef struct dpp_nppu_pktrx_cfg_hdu_udf_l3type_0_t +{ + ZXIC_UINT32 cfg_l3_type0; + ZXIC_UINT32 cfg_l3_type1; +}DPP_NPPU_PKTRX_CFG_HDU_UDF_L3TYPE_0_T; + +typedef struct dpp_nppu_pktrx_cfg_hdu_udf_l3type_1_t +{ + ZXIC_UINT32 cfg_l3_type2; + ZXIC_UINT32 cfg_l3_type3; +}DPP_NPPU_PKTRX_CFG_HDU_UDF_L3TYPE_1_T; + +typedef struct dpp_nppu_pktrx_cfg_hdu_udf_l3type_2_t +{ + ZXIC_UINT32 cfg_l3_type4; + ZXIC_UINT32 cfg_l3_type5; +}DPP_NPPU_PKTRX_CFG_HDU_UDF_L3TYPE_2_T; + +typedef struct dpp_nppu_pktrx_cfg_hdu_udf_l3type_3_t +{ + ZXIC_UINT32 cfg_l3_type6; + ZXIC_UINT32 cfg_l3_type7; +}DPP_NPPU_PKTRX_CFG_HDU_UDF_L3TYPE_3_T; + +typedef struct dpp_nppu_pktrx_cfg_hdu_udf_l4type_0_t +{ + ZXIC_UINT32 cfg_l4_type0; + ZXIC_UINT32 cfg_l4_type1; + ZXIC_UINT32 cfg_l4_type2; + ZXIC_UINT32 cfg_l4_type3; +}DPP_NPPU_PKTRX_CFG_HDU_UDF_L4TYPE_0_T; + +typedef struct dpp_nppu_pktrx_cfg_hdu_udf_l4type_1_t +{ + ZXIC_UINT32 cfg_l4_type4; + ZXIC_UINT32 cfg_l4_type5; + ZXIC_UINT32 cfg_l4_type6; + ZXIC_UINT32 cfg_l4_type7; +}DPP_NPPU_PKTRX_CFG_HDU_UDF_L4TYPE_1_T; + +typedef struct dpp_nppu_pktrx_cfg_hdu_udf_l4type_2_t +{ + ZXIC_UINT32 cfg_l4_type8; + ZXIC_UINT32 cfg_l4_type9; + ZXIC_UINT32 cfg_l4_type10; +}DPP_NPPU_PKTRX_CFG_HDU_UDF_L4TYPE_2_T; + +typedef struct dpp_nppu_pktrx_cfg_slot_no_cfg_t +{ + ZXIC_UINT32 cfg_parser_slot_no; +}DPP_NPPU_PKTRX_CFG_SLOT_NO_CFG_T; + +typedef struct dpp_nppu_pktrx_cfg_pktrx_int_en_0_t +{ + ZXIC_UINT32 pktrx_int_en_31; + ZXIC_UINT32 pktrx_int_en_30; + ZXIC_UINT32 pktrx_int_en_29; + ZXIC_UINT32 pktrx_int_en_28; + ZXIC_UINT32 pktrx_int_en_27; + ZXIC_UINT32 pktrx_int_en_26; + ZXIC_UINT32 pktrx_int_en_25; + ZXIC_UINT32 pktrx_int_en_24; + ZXIC_UINT32 pktrx_int_en_23; + ZXIC_UINT32 pktrx_int_en_22; + ZXIC_UINT32 pktrx_int_en_21; + ZXIC_UINT32 pktrx_int_en_20; + ZXIC_UINT32 pktrx_int_en_19; + ZXIC_UINT32 pktrx_int_en_18; + ZXIC_UINT32 pktrx_int_en_17; + ZXIC_UINT32 pktrx_int_en_16; + ZXIC_UINT32 pktrx_int_en_15; + ZXIC_UINT32 pktrx_int_en_14; + ZXIC_UINT32 pktrx_int_en_13; + ZXIC_UINT32 pktrx_int_en_12; + ZXIC_UINT32 pktrx_int_en_11; + ZXIC_UINT32 pktrx_int_en_10; + ZXIC_UINT32 pktrx_int_en_9; + ZXIC_UINT32 pktrx_int_en_8; + ZXIC_UINT32 pktrx_int_en_7; + ZXIC_UINT32 pktrx_int_en_6; + ZXIC_UINT32 pktrx_int_en_5; + ZXIC_UINT32 pktrx_int_en_4; + ZXIC_UINT32 pktrx_int_en_3; + ZXIC_UINT32 pktrx_int_en_2; + ZXIC_UINT32 pktrx_int_en_1; + ZXIC_UINT32 pktrx_int_en_0; +}DPP_NPPU_PKTRX_CFG_PKTRX_INT_EN_0_T; + +typedef struct dpp_nppu_pktrx_cfg_pktrx_int_en_1_t +{ + ZXIC_UINT32 pktrx_int_en_35; + ZXIC_UINT32 pktrx_int_en_34; + ZXIC_UINT32 pktrx_int_en_33; + ZXIC_UINT32 pktrx_int_en_32; +}DPP_NPPU_PKTRX_CFG_PKTRX_INT_EN_1_T; + +typedef struct dpp_nppu_pktrx_cfg_pktrx_int_mask_0_t +{ + ZXIC_UINT32 pktrx_int_mask_31; + ZXIC_UINT32 pktrx_int_mask_30; + ZXIC_UINT32 pktrx_int_mask_29; + ZXIC_UINT32 pktrx_int_mask_28; + ZXIC_UINT32 pktrx_int_mask_27; + ZXIC_UINT32 pktrx_int_mask_26; + ZXIC_UINT32 pktrx_int_mask_25; + ZXIC_UINT32 pktrx_int_mask_24; + ZXIC_UINT32 pktrx_int_mask_23; + ZXIC_UINT32 pktrx_int_mask_22; + ZXIC_UINT32 pktrx_int_mask_21; + ZXIC_UINT32 pktrx_int_mask_20; + ZXIC_UINT32 pktrx_int_mask_19; + ZXIC_UINT32 pktrx_int_mask_18; + ZXIC_UINT32 pktrx_int_mask_17; + ZXIC_UINT32 pktrx_int_mask_16; + ZXIC_UINT32 pktrx_int_mask_15; + ZXIC_UINT32 pktrx_int_mask_14; + ZXIC_UINT32 pktrx_int_mask_13; + ZXIC_UINT32 pktrx_int_mask_12; + ZXIC_UINT32 pktrx_int_mask_11; + ZXIC_UINT32 pktrx_int_mask_10; + ZXIC_UINT32 pktrx_int_mask_9; + ZXIC_UINT32 pktrx_int_mask_8; + ZXIC_UINT32 pktrx_int_mask_7; + ZXIC_UINT32 pktrx_int_mask_6; + ZXIC_UINT32 pktrx_int_mask_5; + ZXIC_UINT32 pktrx_int_mask_4; + ZXIC_UINT32 pktrx_int_mask_3; + ZXIC_UINT32 pktrx_int_mask_2; + ZXIC_UINT32 pktrx_int_mask_1; + ZXIC_UINT32 pktrx_int_mask_0; +}DPP_NPPU_PKTRX_CFG_PKTRX_INT_MASK_0_T; + +typedef struct dpp_nppu_pktrx_cfg_pktrx_int_mask_1_t +{ + ZXIC_UINT32 pktrx_int_mask_35; + ZXIC_UINT32 pktrx_int_mask_34; + ZXIC_UINT32 pktrx_int_mask_33; + ZXIC_UINT32 pktrx_int_mask_32; +}DPP_NPPU_PKTRX_CFG_PKTRX_INT_MASK_1_T; + +typedef struct dpp_nppu_pktrx_cfg_pktrx_int_status_t +{ + ZXIC_UINT32 int_status; +}DPP_NPPU_PKTRX_CFG_PKTRX_INT_STATUS_T; + +typedef struct dpp_nppu_pktrx_cfg_pktrx_port_rdy0_t +{ + ZXIC_UINT32 pktrx_trpgrx_r1_rdy; + ZXIC_UINT32 pktrx_trpgrx_r2_rdy; +}DPP_NPPU_PKTRX_CFG_PKTRX_PORT_RDY0_T; + +typedef struct dpp_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy0_t +{ + ZXIC_UINT32 pktrx_trpgrx_r1_pfc_rdy_0; +}DPP_NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY0_T; + +typedef struct dpp_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy1_t +{ + ZXIC_UINT32 pktrx_trpgrx_r1_pfc_rdy_1; +}DPP_NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY1_T; + +typedef struct dpp_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy2_t +{ + ZXIC_UINT32 pktrx_trpgrx_r1_pfc_rdy_2; +}DPP_NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY2_T; + +typedef struct dpp_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy3_t +{ + ZXIC_UINT32 pktrx_trpgrx_r2_pfc_rdy_3; +}DPP_NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY3_T; + +typedef struct dpp_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy4_t +{ + ZXIC_UINT32 pktrx_trpgrx_r2_pfc_rdy_4; +}DPP_NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY4_T; + +typedef struct dpp_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy5_t +{ + ZXIC_UINT32 pktrx_trpgrx_r2_pfc_rdy_5; +}DPP_NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY5_T; + +typedef struct dpp_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy6_t +{ + ZXIC_UINT32 pktrx_trpgrx_r2_pfc_rdy_6; +}DPP_NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY6_T; + +typedef struct dpp_nppu_pktrx_cfg_cfg_port_l2_offset_mode_t +{ + ZXIC_UINT32 cfg_port_l2_offset_mode; +}DPP_NPPU_PKTRX_CFG_CFG_PORT_L2_OFFSET_MODE_T; + +typedef struct dpp_nppu_idma_cfg_int_ram_en_t +{ + ZXIC_UINT32 phy_sts_parity_err; + ZXIC_UINT32 ptr_buf_parity_err; +}DPP_NPPU_IDMA_CFG_INT_RAM_EN_T; + +typedef struct dpp_nppu_idma_cfg_int_ram_mask_t +{ + ZXIC_UINT32 phy_sts_parity_err; + ZXIC_UINT32 ptr_buf_parity_err; +}DPP_NPPU_IDMA_CFG_INT_RAM_MASK_T; + +typedef struct dpp_nppu_idma_cfg_int_ram_status_t +{ + ZXIC_UINT32 phy_sts_parity_err; + ZXIC_UINT32 ptr_buf_parity_err; +}DPP_NPPU_IDMA_CFG_INT_RAM_STATUS_T; + +typedef struct dpp_nppu_idma_cfg_subsys_int_mask_flag_t +{ + ZXIC_UINT32 subsys_int_mask_flag; +}DPP_NPPU_IDMA_CFG_SUBSYS_INT_MASK_FLAG_T; + +typedef struct dpp_nppu_idma_cfg_subsys_int_unmask_flag_t +{ + ZXIC_UINT32 subsys_int_unmask_flag; +}DPP_NPPU_IDMA_CFG_SUBSYS_INT_UNMASK_FLAG_T; + +typedef struct dpp_nppu_idma_cfg_debug_cnt_rdclr_mode_t +{ + ZXIC_UINT32 debug_cnt_rdclr_mode; +}DPP_NPPU_IDMA_CFG_DEBUG_CNT_RDCLR_MODE_T; + +typedef struct dpp_nppu_pbu_cfg_int_ram_en0_t +{ + ZXIC_UINT32 int_ram_en_31; + ZXIC_UINT32 int_ram_en_30; + ZXIC_UINT32 int_ram_en_29; + ZXIC_UINT32 int_ram_en_28; + ZXIC_UINT32 int_ram_en_27; + ZXIC_UINT32 int_ram_en_26; + ZXIC_UINT32 int_ram_en_25; + ZXIC_UINT32 int_ram_en_24; + ZXIC_UINT32 int_ram_en_23; + ZXIC_UINT32 int_ram_en_22; + ZXIC_UINT32 int_ram_en_21; + ZXIC_UINT32 int_ram_en_20; + ZXIC_UINT32 int_ram_en_19; + ZXIC_UINT32 int_ram_en_18; + ZXIC_UINT32 int_ram_en_17; + ZXIC_UINT32 int_ram_en_16; + ZXIC_UINT32 int_ram_en_15; + ZXIC_UINT32 int_ram_en_14; + ZXIC_UINT32 int_ram_en_13; + ZXIC_UINT32 int_ram_en_12; + ZXIC_UINT32 int_ram_en_11; + ZXIC_UINT32 int_ram_en_10; + ZXIC_UINT32 int_ram_en_9; + ZXIC_UINT32 int_ram_en_8; + ZXIC_UINT32 int_ram_en_7; + ZXIC_UINT32 int_ram_en_6; + ZXIC_UINT32 int_ram_en_5; + ZXIC_UINT32 int_ram_en_4; + ZXIC_UINT32 int_ram_en_3; + ZXIC_UINT32 int_ram_en_2; + ZXIC_UINT32 int_ram_en_1; + ZXIC_UINT32 int_ram_en_0; +}DPP_NPPU_PBU_CFG_INT_RAM_EN0_T; + +typedef struct dpp_nppu_pbu_cfg_int_ram_mask0_t +{ + ZXIC_UINT32 int_ram_mask_31; + ZXIC_UINT32 int_ram_mask_30; + ZXIC_UINT32 int_ram_mask_29; + ZXIC_UINT32 int_ram_mask_28; + ZXIC_UINT32 int_ram_mask_27; + ZXIC_UINT32 int_ram_mask_26; + ZXIC_UINT32 int_ram_mask_25; + ZXIC_UINT32 int_ram_mask_24; + ZXIC_UINT32 int_ram_mask_23; + ZXIC_UINT32 int_ram_mask_22; + ZXIC_UINT32 int_ram_mask_21; + ZXIC_UINT32 int_ram_mask_20; + ZXIC_UINT32 int_ram_mask_19; + ZXIC_UINT32 int_ram_mask_18; + ZXIC_UINT32 int_ram_mask_17; + ZXIC_UINT32 int_ram_mask_16; + ZXIC_UINT32 int_ram_mask_15; + ZXIC_UINT32 int_ram_mask_14; + ZXIC_UINT32 int_ram_mask_13; + ZXIC_UINT32 int_ram_mask_12; + ZXIC_UINT32 int_ram_mask_11; + ZXIC_UINT32 int_ram_mask_10; + ZXIC_UINT32 int_ram_mask_9; + ZXIC_UINT32 int_ram_mask_8; + ZXIC_UINT32 int_ram_mask_7; + ZXIC_UINT32 int_ram_mask_6; + ZXIC_UINT32 int_ram_mask_5; + ZXIC_UINT32 int_ram_mask_4; + ZXIC_UINT32 int_ram_mask_3; + ZXIC_UINT32 int_ram_mask_2; + ZXIC_UINT32 int_ram_mask_1; + ZXIC_UINT32 int_ram_mask_0; +}DPP_NPPU_PBU_CFG_INT_RAM_MASK0_T; + +typedef struct dpp_nppu_pbu_cfg_int_ram_status0_t +{ + ZXIC_UINT32 int_ram_status_31; + ZXIC_UINT32 int_ram_status_30; + ZXIC_UINT32 int_ram_status_29; + ZXIC_UINT32 int_ram_status_28; + ZXIC_UINT32 int_ram_status_27; + ZXIC_UINT32 int_ram_status_26; + ZXIC_UINT32 int_ram_status_25; + ZXIC_UINT32 int_ram_status_24; + ZXIC_UINT32 int_ram_status_23; + ZXIC_UINT32 int_ram_status_22; + ZXIC_UINT32 int_ram_status_21; + ZXIC_UINT32 int_ram_status_20; + ZXIC_UINT32 int_ram_status_19; + ZXIC_UINT32 int_ram_status_18; + ZXIC_UINT32 int_ram_status_17; + ZXIC_UINT32 int_ram_status_16; + ZXIC_UINT32 int_ram_status_15; + ZXIC_UINT32 int_ram_status_14; + ZXIC_UINT32 int_ram_status_13; + ZXIC_UINT32 int_ram_status_12; + ZXIC_UINT32 int_ram_status_11; + ZXIC_UINT32 int_ram_status_10; + ZXIC_UINT32 int_ram_status_9; + ZXIC_UINT32 int_ram_status_8; + ZXIC_UINT32 int_ram_status_7; + ZXIC_UINT32 int_ram_status_6; + ZXIC_UINT32 int_ram_status_5; + ZXIC_UINT32 int_ram_status_4; + ZXIC_UINT32 int_ram_status_3; + ZXIC_UINT32 int_ram_status_2; + ZXIC_UINT32 int_ram_status_1; + ZXIC_UINT32 int_ram_status_0; +}DPP_NPPU_PBU_CFG_INT_RAM_STATUS0_T; + +typedef struct dpp_nppu_pbu_cfg_int_fifo_en0_t +{ + ZXIC_UINT32 int_fifo_en_31; + ZXIC_UINT32 int_fifo_en_30; + ZXIC_UINT32 int_fifo_en_29; + ZXIC_UINT32 int_fifo_en_28; + ZXIC_UINT32 int_fifo_en_27; + ZXIC_UINT32 int_fifo_en_26; + ZXIC_UINT32 int_fifo_en_25; + ZXIC_UINT32 int_fifo_en_24; + ZXIC_UINT32 int_fifo_en_23; + ZXIC_UINT32 int_fifo_en_22; + ZXIC_UINT32 int_fifo_en_21; + ZXIC_UINT32 int_fifo_en_20; + ZXIC_UINT32 int_fifo_en_19; + ZXIC_UINT32 int_fifo_en_18; + ZXIC_UINT32 int_fifo_en_17; + ZXIC_UINT32 int_fifo_en_16; + ZXIC_UINT32 int_fifo_en_15; + ZXIC_UINT32 int_fifo_en_14; + ZXIC_UINT32 int_fifo_en_13; + ZXIC_UINT32 int_fifo_en_12; + ZXIC_UINT32 int_fifo_en_11; + ZXIC_UINT32 int_fifo_en_10; + ZXIC_UINT32 int_fifo_en_9; + ZXIC_UINT32 int_fifo_en_8; + ZXIC_UINT32 int_fifo_en_7; + ZXIC_UINT32 int_fifo_en_6; + ZXIC_UINT32 int_fifo_en_5; + ZXIC_UINT32 int_fifo_en_4; + ZXIC_UINT32 int_fifo_en_3; + ZXIC_UINT32 int_fifo_en_2; + ZXIC_UINT32 int_fifo_en_1; + ZXIC_UINT32 int_fifo_en_0; +}DPP_NPPU_PBU_CFG_INT_FIFO_EN0_T; + +typedef struct dpp_nppu_pbu_cfg_int_fifo_en1_t +{ + ZXIC_UINT32 int_fifo_en_35; + ZXIC_UINT32 int_fifo_en_34; + ZXIC_UINT32 int_fifo_en_33; + ZXIC_UINT32 int_fifo_en_32; +}DPP_NPPU_PBU_CFG_INT_FIFO_EN1_T; + +typedef struct dpp_nppu_pbu_cfg_int_fifo_mask0_t +{ + ZXIC_UINT32 int_fifo_mask_31; + ZXIC_UINT32 int_fifo_mask_30; + ZXIC_UINT32 int_fifo_mask_29; + ZXIC_UINT32 int_fifo_mask_28; + ZXIC_UINT32 int_fifo_mask_27; + ZXIC_UINT32 int_fifo_mask_26; + ZXIC_UINT32 int_fifo_mask_25; + ZXIC_UINT32 int_fifo_mask_24; + ZXIC_UINT32 int_fifo_mask_23; + ZXIC_UINT32 int_fifo_mask_22; + ZXIC_UINT32 int_fifo_mask_21; + ZXIC_UINT32 int_fifo_mask_20; + ZXIC_UINT32 int_fifo_mask_19; + ZXIC_UINT32 int_fifo_mask_18; + ZXIC_UINT32 int_fifo_mask_17; + ZXIC_UINT32 int_fifo_mask_16; + ZXIC_UINT32 int_fifo_mask_15; + ZXIC_UINT32 int_fifo_mask_14; + ZXIC_UINT32 int_fifo_mask_13; + ZXIC_UINT32 int_fifo_mask_12; + ZXIC_UINT32 int_fifo_mask_11; + ZXIC_UINT32 int_fifo_mask_10; + ZXIC_UINT32 int_fifo_mask_9; + ZXIC_UINT32 int_fifo_mask_8; + ZXIC_UINT32 int_fifo_mask_7; + ZXIC_UINT32 int_fifo_mask_6; + ZXIC_UINT32 int_fifo_mask_5; + ZXIC_UINT32 int_fifo_mask_4; + ZXIC_UINT32 int_fifo_mask_3; + ZXIC_UINT32 int_fifo_mask_2; + ZXIC_UINT32 int_fifo_mask_1; + ZXIC_UINT32 int_fifo_mask_0; +}DPP_NPPU_PBU_CFG_INT_FIFO_MASK0_T; + +typedef struct dpp_nppu_pbu_cfg_int_fifo_mask1_t +{ + ZXIC_UINT32 int_fifo_mask_35; + ZXIC_UINT32 int_fifo_mask_34; + ZXIC_UINT32 int_fifo_mask_33; + ZXIC_UINT32 int_fifo_mask_32; +}DPP_NPPU_PBU_CFG_INT_FIFO_MASK1_T; + +typedef struct dpp_nppu_pbu_cfg_int_fifo_status0_t +{ + ZXIC_UINT32 int_fifo_status_31; + ZXIC_UINT32 int_fifo_status_30; + ZXIC_UINT32 int_fifo_status_29; + ZXIC_UINT32 int_fifo_status_28; + ZXIC_UINT32 int_fifo_status_27; + ZXIC_UINT32 int_fifo_status_26; + ZXIC_UINT32 int_fifo_status_25; + ZXIC_UINT32 int_fifo_status_24; + ZXIC_UINT32 int_fifo_status_23; + ZXIC_UINT32 int_fifo_status_22; + ZXIC_UINT32 int_fifo_status_21; + ZXIC_UINT32 int_fifo_status_20; + ZXIC_UINT32 int_fifo_status_19; + ZXIC_UINT32 int_fifo_status_18; + ZXIC_UINT32 int_fifo_status_17; + ZXIC_UINT32 int_fifo_status_16; + ZXIC_UINT32 int_fifo_status_15; + ZXIC_UINT32 int_fifo_status_14; + ZXIC_UINT32 int_fifo_status_13; + ZXIC_UINT32 int_fifo_status_12; + ZXIC_UINT32 int_fifo_status_11; + ZXIC_UINT32 int_fifo_status_10; + ZXIC_UINT32 int_fifo_status_9; + ZXIC_UINT32 int_fifo_status_8; + ZXIC_UINT32 int_fifo_status_7; + ZXIC_UINT32 int_fifo_status_6; + ZXIC_UINT32 int_fifo_status_5; + ZXIC_UINT32 int_fifo_status_4; + ZXIC_UINT32 int_fifo_status_3; + ZXIC_UINT32 int_fifo_status_2; + ZXIC_UINT32 int_fifo_status_1; + ZXIC_UINT32 int_fifo_status_0; +}DPP_NPPU_PBU_CFG_INT_FIFO_STATUS0_T; + +typedef struct dpp_nppu_pbu_cfg_int_fifo_status1_t +{ + ZXIC_UINT32 int_fifo_status_35; + ZXIC_UINT32 int_fifo_status_34; + ZXIC_UINT32 int_fifo_status_33; + ZXIC_UINT32 int_fifo_status_32; +}DPP_NPPU_PBU_CFG_INT_FIFO_STATUS1_T; + +typedef struct dpp_nppu_pbu_cfg_subsys_int_mask_flag_t +{ + ZXIC_UINT32 subsys_int_mask_flag; +}DPP_NPPU_PBU_CFG_SUBSYS_INT_MASK_FLAG_T; + +typedef struct dpp_nppu_pbu_cfg_subsys_int_unmask_flag_t +{ + ZXIC_UINT32 subsys_int_unmask_flag; +}DPP_NPPU_PBU_CFG_SUBSYS_INT_UNMASK_FLAG_T; + +typedef struct dpp_nppu_pbu_cfg_sa_ip_en_t +{ + ZXIC_UINT32 sa_ip_en; +}DPP_NPPU_PBU_CFG_SA_IP_EN_T; + +typedef struct dpp_nppu_pbu_cfg_debug_cnt_rdclr_mode_t +{ + ZXIC_UINT32 debug_cnt_rdclr_mode; +}DPP_NPPU_PBU_CFG_DEBUG_CNT_RDCLR_MODE_T; + +typedef struct dpp_nppu_pbu_cfg_fptr_fifo_aful_assert_cfg_t +{ + ZXIC_UINT32 fptr_fifo_aful_assert_cfg; +}DPP_NPPU_PBU_CFG_FPTR_FIFO_AFUL_ASSERT_CFG_T; + +typedef struct dpp_nppu_pbu_cfg_fptr_fifo_aful_negate_cfg_t +{ + ZXIC_UINT32 fptr_fifo_aful_negate_cfg; +}DPP_NPPU_PBU_CFG_FPTR_FIFO_AFUL_NEGATE_CFG_T; + +typedef struct dpp_nppu_pbu_cfg_pf_fifo_aful_assert_cfg_t +{ + ZXIC_UINT32 pf_fifo_aful_assert_cfg; +}DPP_NPPU_PBU_CFG_PF_FIFO_AFUL_ASSERT_CFG_T; + +typedef struct dpp_nppu_pbu_cfg_pf_fifo_aful_negate_cfg_t +{ + ZXIC_UINT32 pf_fifo_aful_negate_cfg; +}DPP_NPPU_PBU_CFG_PF_FIFO_AFUL_NEGATE_CFG_T; + +typedef struct dpp_nppu_pbu_cfg_pf_fifo_aept_assert_cfg_t +{ + ZXIC_UINT32 pf_fifo_aept_assert_cfg; +}DPP_NPPU_PBU_CFG_PF_FIFO_AEPT_ASSERT_CFG_T; + +typedef struct dpp_nppu_pbu_cfg_pf_fifo_aept_negate_cfg_t +{ + ZXIC_UINT32 pf_fifo_aept_negate_cfg; +}DPP_NPPU_PBU_CFG_PF_FIFO_AEPT_NEGATE_CFG_T; + +typedef struct dpp_nppu_pbu_cfg_wb_aful_assert_cfg_t +{ + ZXIC_UINT32 wb_aful_assert_cfg; +}DPP_NPPU_PBU_CFG_WB_AFUL_ASSERT_CFG_T; + +typedef struct dpp_nppu_pbu_cfg_wb_aful_negate_cfg_t +{ + ZXIC_UINT32 wb_aful_negate_cfg; +}DPP_NPPU_PBU_CFG_WB_AFUL_NEGATE_CFG_T; + +typedef struct dpp_nppu_pbu_cfg_se_key_aful_assert_cfg_t +{ + ZXIC_UINT32 se_key_aful_assert_cfg; +}DPP_NPPU_PBU_CFG_SE_KEY_AFUL_ASSERT_CFG_T; + +typedef struct dpp_nppu_pbu_cfg_ifbrd_se_aful_assert_cfg_t +{ + ZXIC_UINT32 ifbrd_se_aful_assert_cfg; +}DPP_NPPU_PBU_CFG_IFBRD_SE_AFUL_ASSERT_CFG_T; + +typedef struct dpp_nppu_pbu_cfg_ifbrd_se_aful_negate_cfg_t +{ + ZXIC_UINT32 ifbrd_se_aful_negate_cfg; +}DPP_NPPU_PBU_CFG_IFBRD_SE_AFUL_NEGATE_CFG_T; + +typedef struct dpp_nppu_pbu_cfg_ifbrd_odma_aful_assert_cfg_t +{ + ZXIC_UINT32 ifbrd_odma_aful_assert_cfg; +}DPP_NPPU_PBU_CFG_IFBRD_ODMA_AFUL_ASSERT_CFG_T; + +typedef struct dpp_nppu_pbu_cfg_ifbrd_odma_aful_negate_cfg_t +{ + ZXIC_UINT32 ifbrd_odma_aful_negate_cfg; +}DPP_NPPU_PBU_CFG_IFBRD_ODMA_AFUL_NEGATE_CFG_T; + +typedef struct dpp_nppu_pbu_cfg_ifbrd_ppu_aful_assert_cfg_t +{ + ZXIC_UINT32 ifbrd_ppu_aful_assert_cfg; +}DPP_NPPU_PBU_CFG_IFBRD_PPU_AFUL_ASSERT_CFG_T; + +typedef struct dpp_nppu_pbu_cfg_ifbrd_ppu_aful_negate_cfg_t +{ + ZXIC_UINT32 ifbrd_ppu_aful_negate_cfg; +}DPP_NPPU_PBU_CFG_IFBRD_PPU_AFUL_NEGATE_CFG_T; + +typedef struct dpp_nppu_pbu_cfg_mc_logic_aful_assert_cfg_t +{ + ZXIC_UINT32 mc_logic_aful_assert_cfg; +}DPP_NPPU_PBU_CFG_MC_LOGIC_AFUL_ASSERT_CFG_T; + +typedef struct dpp_nppu_pbu_cfg_mc_logic_aful_negate_cfg_t +{ + ZXIC_UINT32 mc_logic_aful_negate_cfg; +}DPP_NPPU_PBU_CFG_MC_LOGIC_AFUL_NEGATE_CFG_T; + +typedef struct dpp_nppu_pbu_cfg_mc_logic_diff_t +{ + ZXIC_UINT32 mc_logic_diff; +}DPP_NPPU_PBU_CFG_MC_LOGIC_DIFF_T; + +typedef struct dpp_nppu_pbu_cfg_cfg_peak_port_cnt_clr_t +{ + ZXIC_UINT32 cfg_peak_port_cnt_clr; +}DPP_NPPU_PBU_CFG_CFG_PEAK_PORT_CNT_CLR_T; + +typedef struct dpp_nppu_pbu_cfg_all_ftm_crdt_th_t +{ + ZXIC_UINT32 ftm_crdt_port_cng_th; + ZXIC_UINT32 ftm_crdt_port_th; +}DPP_NPPU_PBU_CFG_ALL_FTM_CRDT_TH_T; + +typedef struct dpp_nppu_pbu_cfg_all_ftm_link_th_01_t +{ + ZXIC_UINT32 total_congest_th1; + ZXIC_UINT32 total_congest_th0; +}DPP_NPPU_PBU_CFG_ALL_FTM_LINK_TH_01_T; + +typedef struct dpp_nppu_pbu_cfg_all_ftm_link_th_23_t +{ + ZXIC_UINT32 total_congest_th3; + ZXIC_UINT32 total_congest_th2; +}DPP_NPPU_PBU_CFG_ALL_FTM_LINK_TH_23_T; + +typedef struct dpp_nppu_pbu_cfg_all_ftm_link_th_45_t +{ + ZXIC_UINT32 total_congest_th5; + ZXIC_UINT32 total_congest_th4; +}DPP_NPPU_PBU_CFG_ALL_FTM_LINK_TH_45_T; + +typedef struct dpp_nppu_pbu_cfg_all_ftm_link_th_6_t +{ + ZXIC_UINT32 total_congest_th6; +}DPP_NPPU_PBU_CFG_ALL_FTM_LINK_TH_6_T; + +typedef struct dpp_nppu_pbu_cfg_all_ftm_total_congest_th_t +{ + ZXIC_UINT32 all_ftm_total_congest_th; +}DPP_NPPU_PBU_CFG_ALL_FTM_TOTAL_CONGEST_TH_T; + +typedef struct dpp_nppu_pbu_cfg_cfg_crdt_mode_t +{ + ZXIC_UINT32 cfg_crdt_mode; +}DPP_NPPU_PBU_CFG_CFG_CRDT_MODE_T; + +typedef struct dpp_nppu_pbu_cfg_cfg_pfc_rdy_high_time_t +{ + ZXIC_UINT32 cfg_pfc_rdy_high_time; +}DPP_NPPU_PBU_CFG_CFG_PFC_RDY_HIGH_TIME_T; + +typedef struct dpp_nppu_pbu_cfg_cfg_pfc_rdy_low_time_t +{ + ZXIC_UINT32 cfg_pfc_rdy_low_time; +}DPP_NPPU_PBU_CFG_CFG_PFC_RDY_LOW_TIME_T; + +typedef struct dpp_nppu_pbu_stat_pbu_fc_rdy_t +{ + ZXIC_UINT32 pbu_oam_send_fc_rdy; + ZXIC_UINT32 pbu_odma_fc_rdy; + ZXIC_UINT32 pbu_tm_fc_rdy; + ZXIC_UINT32 pbu_idma_cos_rdy; +}DPP_NPPU_PBU_STAT_PBU_FC_RDY_T; + +typedef struct dpp_nppu_pbu_stat_pbu_lif_group0_rdy0_t +{ + ZXIC_UINT32 pbu_ipg1_rdy; + ZXIC_UINT32 pbu_ipg0_rdy; + ZXIC_UINT32 pbu_trpgrx_xge_rdy; + ZXIC_UINT32 pbu_trpgrx_cge1_rdy; + ZXIC_UINT32 pbu_trpgrx_cge0_rdy; +}DPP_NPPU_PBU_STAT_PBU_LIF_GROUP0_RDY0_T; + +typedef struct dpp_nppu_pbu_stat_pbu_lif_group0_rdy1_t +{ + ZXIC_UINT32 pbu_lif_group0_rdy1; +}DPP_NPPU_PBU_STAT_PBU_LIF_GROUP0_RDY1_T; + +typedef struct dpp_nppu_pbu_stat_pbu_lif_group1_rdy_t +{ + ZXIC_UINT32 pbu_lif_group1_rdy1; +}DPP_NPPU_PBU_STAT_PBU_LIF_GROUP1_RDY_T; + +typedef struct dpp_nppu_pbu_stat_pbu_lif_group0_pfc_rdy_t +{ + ZXIC_UINT32 pbu_lif_group0_pfc_rdy; +}DPP_NPPU_PBU_STAT_PBU_LIF_GROUP0_PFC_RDY_T; + +typedef struct dpp_nppu_pbu_stat_pbu_lif_group1_pfc_rdy_t +{ + ZXIC_UINT32 pbu_lif_group1_pfc_rdy; +}DPP_NPPU_PBU_STAT_PBU_LIF_GROUP1_PFC_RDY_T; + +typedef struct dpp_nppu_pbu_stat_pbu_sa_port_rdy_0_31_t +{ + ZXIC_UINT32 pbu_sa_port_rdy_0_31; +}DPP_NPPU_PBU_STAT_PBU_SA_PORT_RDY_0_31_T; + +typedef struct dpp_nppu_pbu_stat_pbu_sa_port_rdy_32_50_t +{ + ZXIC_UINT32 pbu_sa_port_rdy_32_50; +}DPP_NPPU_PBU_STAT_PBU_SA_PORT_RDY_32_50_T; + +typedef struct dpp_nppu_pbu_stat_pbu_pktrx_mr_pfc_rdy_t +{ + ZXIC_UINT32 pbu_pktrx_mr_pfc_rdy; +}DPP_NPPU_PBU_STAT_PBU_PKTRX_MR_PFC_RDY_T; + +typedef struct dpp_nppu_pbu_stat_pbu_ftm_crdt_port_rdy_0_31_t +{ + ZXIC_UINT32 pbu_ftm_crdt_port_rdy_0_31; +}DPP_NPPU_PBU_STAT_PBU_FTM_CRDT_PORT_RDY_0_31_T; + +typedef struct dpp_nppu_pbu_stat_pbu_ftm_crdt_port_rdy_32_47_t +{ + ZXIC_UINT32 pbu_ftm_crdt_port_rdy_32_47; +}DPP_NPPU_PBU_STAT_PBU_FTM_CRDT_PORT_RDY_32_47_T; + +typedef struct dpp_nppu_pbu_stat_pbu_ftm_crdt_port_cng_rdy_0_31_t +{ + ZXIC_UINT32 pbu_ftm_crdt_port_cng_rdy_0_31; +}DPP_NPPU_PBU_STAT_PBU_FTM_CRDT_PORT_CNG_RDY_0_31_T; + +typedef struct dpp_nppu_pbu_stat_pbu_ftm_crdt_port_cng_rdy_32_47_t +{ + ZXIC_UINT32 pbu_ftm_crdt_port_cng_rdy_32_47; +}DPP_NPPU_PBU_STAT_PBU_FTM_CRDT_PORT_CNG_RDY_32_47_T; + +typedef struct dpp_nppu_pbu_stat_pbu_ftm_crdt_sys_info_t +{ + ZXIC_UINT32 pbu_ftm_crdt_sys_info; +}DPP_NPPU_PBU_STAT_PBU_FTM_CRDT_SYS_INFO_T; + +typedef struct dpp_nppu_isu_cfg_weight_normal_mc_t +{ + ZXIC_UINT32 weight_normal_mc; +}DPP_NPPU_ISU_CFG_WEIGHT_NORMAL_MC_T; + +typedef struct dpp_nppu_isu_cfg_weight_sa_mc_t +{ + ZXIC_UINT32 weight_sa_mc; +}DPP_NPPU_ISU_CFG_WEIGHT_SA_MC_T; + +typedef struct dpp_nppu_isu_cfg_weight_etm_t +{ + ZXIC_UINT32 weight_etm; +}DPP_NPPU_ISU_CFG_WEIGHT_ETM_T; + +typedef struct dpp_nppu_isu_cfg_weight_lp_mc_t +{ + ZXIC_UINT32 weight_lp_mc; +}DPP_NPPU_ISU_CFG_WEIGHT_LP_MC_T; + +typedef struct dpp_nppu_isu_cfg_weight_oam_t +{ + ZXIC_UINT32 weight_oam; +}DPP_NPPU_ISU_CFG_WEIGHT_OAM_T; + +typedef struct dpp_nppu_isu_cfg_weight_lif_ctrl1_t +{ + ZXIC_UINT32 weight_lif_ctrl1; +}DPP_NPPU_ISU_CFG_WEIGHT_LIF_CTRL1_T; + +typedef struct dpp_nppu_isu_cfg_weight_lif_ctrl2_t +{ + ZXIC_UINT32 weight_lif_ctrl2; +}DPP_NPPU_ISU_CFG_WEIGHT_LIF_CTRL2_T; + +typedef struct dpp_nppu_isu_cfg_ecc_bypass_read_t +{ + ZXIC_UINT32 eccbypass; +}DPP_NPPU_ISU_CFG_ECC_BYPASS_READ_T; + +typedef struct dpp_nppu_isu_cfg_isu_int_mask_t +{ + ZXIC_UINT32 isu_int_mask; +}DPP_NPPU_ISU_CFG_ISU_INT_MASK_T; + +typedef struct dpp_nppu_isu_cfg_cfg_crdt_cycle_t +{ + ZXIC_UINT32 cfg_cycle; +}DPP_NPPU_ISU_CFG_CFG_CRDT_CYCLE_T; + +typedef struct dpp_nppu_isu_cfg_cfg_crdt_value_t +{ + ZXIC_UINT32 cfg_value; +}DPP_NPPU_ISU_CFG_CFG_CRDT_VALUE_T; + +typedef struct dpp_nppu_isu_cfg_isu_int_en_t +{ + ZXIC_UINT32 isu_int_en; +}DPP_NPPU_ISU_CFG_ISU_INT_EN_T; + +typedef struct dpp_nppu_isu_cfg_isu_ppu_fifo_fc_t +{ + ZXIC_UINT32 isu_ppu_fifo_fc; +}DPP_NPPU_ISU_CFG_ISU_PPU_FIFO_FC_T; + +typedef struct dpp_nppu_isu_cfg_isu_int_status_t +{ + ZXIC_UINT32 isu_int_status_26; + ZXIC_UINT32 isu_int_status_25; + ZXIC_UINT32 isu_int_status_24; + ZXIC_UINT32 isu_int_status_23; + ZXIC_UINT32 isu_int_status_22; + ZXIC_UINT32 isu_int_status_21; + ZXIC_UINT32 isu_int_status_20; + ZXIC_UINT32 isu_int_status_19; + ZXIC_UINT32 isu_int_status_18; + ZXIC_UINT32 isu_int_status_17; + ZXIC_UINT32 isu_int_status_16; + ZXIC_UINT32 isu_int_status_15; + ZXIC_UINT32 isu_int_status_14; + ZXIC_UINT32 isu_int_status_13; + ZXIC_UINT32 isu_int_status_12; + ZXIC_UINT32 isu_int_status_11; + ZXIC_UINT32 isu_int_status_10; + ZXIC_UINT32 isu_int_status_9; + ZXIC_UINT32 isu_int_status_8; + ZXIC_UINT32 isu_int_status_7; + ZXIC_UINT32 isu_int_status_6; + ZXIC_UINT32 isu_int_status_5; + ZXIC_UINT32 isu_int_status_4; + ZXIC_UINT32 isu_int_status_3; + ZXIC_UINT32 isu_int_status_2; + ZXIC_UINT32 isu_int_status_1; + ZXIC_UINT32 isu_int_status_0; +}DPP_NPPU_ISU_CFG_ISU_INT_STATUS_T; + +typedef struct dpp_nppu_isu_cfg_fd_prog_full_assert_cfg_t +{ + ZXIC_UINT32 fd_prog_full_assert_cfg; +}DPP_NPPU_ISU_CFG_FD_PROG_FULL_ASSERT_CFG_T; + +typedef struct dpp_nppu_isu_cfg_fd_prog_full_negate_cfg_t +{ + ZXIC_UINT32 fd_prog_full_negate_cfg; +}DPP_NPPU_ISU_CFG_FD_PROG_FULL_NEGATE_CFG_T; + +typedef struct dpp_nppu_isu_cfg_lp_prog_full_assert_cfg_t +{ + ZXIC_UINT32 lp_prog_ept_assert_cfg; +}DPP_NPPU_ISU_CFG_LP_PROG_FULL_ASSERT_CFG_T; + +typedef struct dpp_nppu_isu_cfg_lp_prog_full_negate_cfg_t +{ + ZXIC_UINT32 lp_prog_ept_negate_cfg; +}DPP_NPPU_ISU_CFG_LP_PROG_FULL_NEGATE_CFG_T; + +typedef struct dpp_nppu_isu_stat_debug_cnt_dat0_t +{ + ZXIC_UINT32 debug_cnt_dat0; +}DPP_NPPU_ISU_STAT_DEBUG_CNT_DAT0_T; + +typedef struct dpp_nppu_isu_stat_debug_cnt_dat1_t +{ + ZXIC_UINT32 debug_cnt_dat1; +}DPP_NPPU_ISU_STAT_DEBUG_CNT_DAT1_T; + +typedef struct dpp_nppu_isu_stat_debug_cnt_dat2_t +{ + ZXIC_UINT32 debug_cnt_dat2; +}DPP_NPPU_ISU_STAT_DEBUG_CNT_DAT2_T; + +typedef struct dpp_nppu_isu_stat_debug_cnt_dat3_t +{ + ZXIC_UINT32 debug_cnt_dat3; +}DPP_NPPU_ISU_STAT_DEBUG_CNT_DAT3_T; + +typedef struct dpp_nppu_isu_stat_debug_cnt_dat4_t +{ + ZXIC_UINT32 debug_cnt_dat4; +}DPP_NPPU_ISU_STAT_DEBUG_CNT_DAT4_T; + +typedef struct dpp_nppu_isu_stat_debug_cnt_dat5_t +{ + ZXIC_UINT32 debug_cnt_dat5; +}DPP_NPPU_ISU_STAT_DEBUG_CNT_DAT5_T; + +typedef struct dpp_nppu_isu_stat_debug_cnt_dat6_t +{ + ZXIC_UINT32 debug_cnt_dat6; +}DPP_NPPU_ISU_STAT_DEBUG_CNT_DAT6_T; + +typedef struct dpp_nppu_isu_stat_debug_cnt_dat7_t +{ + ZXIC_UINT32 debug_cnt_dat7; +}DPP_NPPU_ISU_STAT_DEBUG_CNT_DAT7_T; + +typedef struct dpp_nppu_isu_stat_debug_cnt_dat8_t +{ + ZXIC_UINT32 debug_cnt_dat8; +}DPP_NPPU_ISU_STAT_DEBUG_CNT_DAT8_T; + +typedef struct dpp_nppu_isu_stat_debug_cnt_dat9_t +{ + ZXIC_UINT32 debug_cnt_dat9; +}DPP_NPPU_ISU_STAT_DEBUG_CNT_DAT9_T; + +typedef struct dpp_nppu_isu_stat_debug_cnt_dat10_t +{ + ZXIC_UINT32 debug_cnt_dat10; +}DPP_NPPU_ISU_STAT_DEBUG_CNT_DAT10_T; + +typedef struct dpp_nppu_isu_stat_debug_cnt_dat11_t +{ + ZXIC_UINT32 debug_cnt_dat11; +}DPP_NPPU_ISU_STAT_DEBUG_CNT_DAT11_T; + +typedef struct dpp_nppu_isu_stat_debug_cnt_dat12_t +{ + ZXIC_UINT32 debug_cnt_dat12; +}DPP_NPPU_ISU_STAT_DEBUG_CNT_DAT12_T; + +typedef struct dpp_nppu_isu_stat_debug_cnt_dat13_t +{ + ZXIC_UINT32 debug_cnt_dat13; +}DPP_NPPU_ISU_STAT_DEBUG_CNT_DAT13_T; + +typedef struct dpp_nppu_isu_stat_debug_cnt_dat14_t +{ + ZXIC_UINT32 debug_cnt_dat14; +}DPP_NPPU_ISU_STAT_DEBUG_CNT_DAT14_T; + +typedef struct dpp_nppu_isu_stat_debug_cnt_dat15_t +{ + ZXIC_UINT32 debug_cnt_dat15; +}DPP_NPPU_ISU_STAT_DEBUG_CNT_DAT15_T; + +typedef struct dpp_nppu_isu_stat_debug_cnt_dat16_t +{ + ZXIC_UINT32 debug_cnt_dat16; +}DPP_NPPU_ISU_STAT_DEBUG_CNT_DAT16_T; + +typedef struct dpp_nppu_isu_stat_debug_cnt_dat17_t +{ + ZXIC_UINT32 debug_cnt_dat17; +}DPP_NPPU_ISU_STAT_DEBUG_CNT_DAT17_T; + +typedef struct dpp_nppu_isu_stat_debug_cnt_dat18_t +{ + ZXIC_UINT32 debug_cnt_dat18; +}DPP_NPPU_ISU_STAT_DEBUG_CNT_DAT18_T; + +typedef struct dpp_nppu_isu_stat_debug_cnt_dat19_t +{ + ZXIC_UINT32 debug_cnt_dat18; +}DPP_NPPU_ISU_STAT_DEBUG_CNT_DAT19_T; + +typedef struct dpp_nppu_isu_stat_debug_cnt_cfg_t +{ + ZXIC_UINT32 debug_cnt_ovf_mode; + ZXIC_UINT32 debug_cnt_rdclr_mode; + ZXIC_UINT32 user_cnt_value; +}DPP_NPPU_ISU_STAT_DEBUG_CNT_CFG_T; + +typedef struct dpp_nppu_odma_cfg_exsa_tdm_offset_t +{ + ZXIC_UINT32 exsa_tdm_offset; +}DPP_NPPU_ODMA_CFG_EXSA_TDM_OFFSET_T; + +typedef struct dpp_nppu_odma_cfg_ecc_bypass_readt_t +{ + ZXIC_UINT32 ecc_bypass_read; +}DPP_NPPU_ODMA_CFG_ECC_BYPASS_READT_T; + +typedef struct dpp_nppu_odma_cfg_odma_int_en_0_t +{ + ZXIC_UINT32 odma_int_en_31; + ZXIC_UINT32 odma_int_en_30; + ZXIC_UINT32 odma_int_en_29; + ZXIC_UINT32 odma_int_en_28; + ZXIC_UINT32 odma_int_en_27; + ZXIC_UINT32 odma_int_en_26; + ZXIC_UINT32 odma_int_en_25; + ZXIC_UINT32 odma_int_en_24; + ZXIC_UINT32 odma_int_en_22; + ZXIC_UINT32 odma_int_en_21; + ZXIC_UINT32 odma_int_en_18; +}DPP_NPPU_ODMA_CFG_ODMA_INT_EN_0_T; + +typedef struct dpp_nppu_odma_cfg_odma_int_en_1_t +{ + ZXIC_UINT32 odma_int_en_63; + ZXIC_UINT32 odma_int_en_62; + ZXIC_UINT32 odma_int_en_61; + ZXIC_UINT32 odma_int_en_59; + ZXIC_UINT32 odma_int_en_58; + ZXIC_UINT32 odma_int_en_57; + ZXIC_UINT32 odma_int_en_56; + ZXIC_UINT32 odma_int_en_55; + ZXIC_UINT32 odma_int_en_54; + ZXIC_UINT32 odma_int_en_53; + ZXIC_UINT32 odma_int_en_52; + ZXIC_UINT32 odma_int_en_51; + ZXIC_UINT32 odma_int_en_49; + ZXIC_UINT32 odma_int_en_47; + ZXIC_UINT32 odma_int_en_45; + ZXIC_UINT32 odma_int_en_39; + ZXIC_UINT32 odma_int_en_38; + ZXIC_UINT32 odma_int_en_37; + ZXIC_UINT32 odma_int_en_36; + ZXIC_UINT32 odma_int_en_35; + ZXIC_UINT32 odma_int_en_34; + ZXIC_UINT32 odma_int_en_33; + ZXIC_UINT32 odma_int_en_32; +}DPP_NPPU_ODMA_CFG_ODMA_INT_EN_1_T; + +typedef struct dpp_nppu_odma_cfg_odma_int_en_2_t +{ + ZXIC_UINT32 odma_int_en_91; + ZXIC_UINT32 odma_int_en_88; + ZXIC_UINT32 odma_int_en_85; + ZXIC_UINT32 odma_int_en_82; + ZXIC_UINT32 odma_int_en_79; + ZXIC_UINT32 odma_int_en_75; + ZXIC_UINT32 odma_int_en_74; + ZXIC_UINT32 odma_int_en_71; + ZXIC_UINT32 odma_int_en_65; + ZXIC_UINT32 odma_int_en_64; +}DPP_NPPU_ODMA_CFG_ODMA_INT_EN_2_T; + +typedef struct dpp_nppu_odma_cfg_odma_int_en_3_t +{ + ZXIC_UINT32 odma_int_en_115; + ZXIC_UINT32 odma_int_en_114; + ZXIC_UINT32 odma_int_en_112; + ZXIC_UINT32 odma_int_en_110; + ZXIC_UINT32 odma_int_en_109; + ZXIC_UINT32 odma_int_en_108; + ZXIC_UINT32 odma_int_en_107; + ZXIC_UINT32 odma_int_en_106; + ZXIC_UINT32 odma_int_en_102; + ZXIC_UINT32 odma_int_en_101; + ZXIC_UINT32 odma_int_en_100; + ZXIC_UINT32 odma_int_en_98; + ZXIC_UINT32 odma_int_en_96; +}DPP_NPPU_ODMA_CFG_ODMA_INT_EN_3_T; + +typedef struct dpp_nppu_odma_cfg_odma_int_mask_0_t +{ + ZXIC_UINT32 odma_int_mask_31; + ZXIC_UINT32 odma_int_mask_30; + ZXIC_UINT32 odma_int_mask_29; + ZXIC_UINT32 odma_int_mask_28; + ZXIC_UINT32 odma_int_mask_27; + ZXIC_UINT32 odma_int_mask_26; + ZXIC_UINT32 odma_int_mask_25; + ZXIC_UINT32 odma_int_mask_24; + ZXIC_UINT32 odma_int_mask_22; + ZXIC_UINT32 odma_int_mask_21; + ZXIC_UINT32 odma_int_mask_18; +}DPP_NPPU_ODMA_CFG_ODMA_INT_MASK_0_T; + +typedef struct dpp_nppu_odma_cfg_odma_int_mask_1_t +{ + ZXIC_UINT32 odma_int_mask_63; + ZXIC_UINT32 odma_int_mask_62; + ZXIC_UINT32 odma_int_mask_61; + ZXIC_UINT32 odma_int_mask_59; + ZXIC_UINT32 odma_int_mask_58; + ZXIC_UINT32 odma_int_mask_57; + ZXIC_UINT32 odma_int_mask_56; + ZXIC_UINT32 odma_int_mask_55; + ZXIC_UINT32 odma_int_mask_54; + ZXIC_UINT32 odma_int_mask_53; + ZXIC_UINT32 odma_int_mask_52; + ZXIC_UINT32 odma_int_mask_51; + ZXIC_UINT32 odma_int_mask_50; + ZXIC_UINT32 odma_int_mask_49; + ZXIC_UINT32 odma_int_mask_47; + ZXIC_UINT32 odma_int_mask_45; + ZXIC_UINT32 odma_int_mask_39; + ZXIC_UINT32 odma_int_mask_38; + ZXIC_UINT32 odma_int_mask_37; + ZXIC_UINT32 odma_int_mask_36; + ZXIC_UINT32 odma_int_mask_35; + ZXIC_UINT32 odma_int_mask_34; + ZXIC_UINT32 odma_int_mask_33; + ZXIC_UINT32 odma_int_mask_32; +}DPP_NPPU_ODMA_CFG_ODMA_INT_MASK_1_T; + +typedef struct dpp_nppu_odma_cfg_odma_int_mask_2_t +{ + ZXIC_UINT32 odma_int_mask_91; + ZXIC_UINT32 odma_int_mask_88; + ZXIC_UINT32 odma_int_mask_85; + ZXIC_UINT32 odma_int_mask_82; + ZXIC_UINT32 odma_int_mask_79; + ZXIC_UINT32 odma_int_mask_75; + ZXIC_UINT32 odma_int_mask_74; + ZXIC_UINT32 odma_int_mask_71; + ZXIC_UINT32 odma_int_mask_65; + ZXIC_UINT32 odma_int_mask_64; +}DPP_NPPU_ODMA_CFG_ODMA_INT_MASK_2_T; + +typedef struct dpp_nppu_odma_cfg_odma_int_mask_3_t +{ + ZXIC_UINT32 odma_int_mask_115; + ZXIC_UINT32 odma_int_mask_114; + ZXIC_UINT32 odma_int_mask_112; + ZXIC_UINT32 odma_int_mask_110; + ZXIC_UINT32 odma_int_mask_109; + ZXIC_UINT32 odma_int_mask_108; + ZXIC_UINT32 odma_int_mask_107; + ZXIC_UINT32 odma_int_mask_106; + ZXIC_UINT32 odma_int_mask_102; + ZXIC_UINT32 odma_int_mask_101; + ZXIC_UINT32 odma_int_mask_100; + ZXIC_UINT32 odma_int_mask_98; + ZXIC_UINT32 odma_int_mask_96; +}DPP_NPPU_ODMA_CFG_ODMA_INT_MASK_3_T; + +typedef struct dpp_nppu_odma_cfg_odma_int_status_0_t +{ + ZXIC_UINT32 odma_int_status_31; + ZXIC_UINT32 odma_int_status_30; + ZXIC_UINT32 odma_int_status_29; + ZXIC_UINT32 odma_int_status_28; + ZXIC_UINT32 odma_int_status_27; + ZXIC_UINT32 odma_int_status_26; + ZXIC_UINT32 odma_int_status_25; + ZXIC_UINT32 odma_int_status_24; + ZXIC_UINT32 odma_int_status_22; + ZXIC_UINT32 odma_int_status_21; + ZXIC_UINT32 odma_int_status_18; +}DPP_NPPU_ODMA_CFG_ODMA_INT_STATUS_0_T; + +typedef struct dpp_nppu_odma_cfg_odma_int_status_1_t +{ + ZXIC_UINT32 odma_int_status_63; + ZXIC_UINT32 odma_int_status_62; + ZXIC_UINT32 odma_int_status_61; + ZXIC_UINT32 odma_int_status_59; + ZXIC_UINT32 odma_int_status_58; + ZXIC_UINT32 odma_int_status_57; + ZXIC_UINT32 odma_int_status_56; + ZXIC_UINT32 odma_int_status_55; + ZXIC_UINT32 odma_int_status_54; + ZXIC_UINT32 odma_int_status_53; + ZXIC_UINT32 odma_int_status_52; + ZXIC_UINT32 odma_int_status_51; + ZXIC_UINT32 odma_int_status_49; + ZXIC_UINT32 odma_int_status_47; + ZXIC_UINT32 odma_int_status_45; + ZXIC_UINT32 odma_int_status_39; + ZXIC_UINT32 odma_int_status_38; + ZXIC_UINT32 odma_int_status_37; + ZXIC_UINT32 odma_int_status_36; + ZXIC_UINT32 odma_int_status_35; + ZXIC_UINT32 odma_int_status_34; + ZXIC_UINT32 odma_int_status_33; + ZXIC_UINT32 odma_int_status_32; +}DPP_NPPU_ODMA_CFG_ODMA_INT_STATUS_1_T; + +typedef struct dpp_nppu_odma_cfg_odma_int_status_2_t +{ + ZXIC_UINT32 odma_int_status_91; + ZXIC_UINT32 odma_int_status_88; + ZXIC_UINT32 odma_int_status_85; + ZXIC_UINT32 odma_int_status_82; + ZXIC_UINT32 odma_int_status_79; + ZXIC_UINT32 odma_int_status_75; + ZXIC_UINT32 odma_int_status_74; + ZXIC_UINT32 odma_int_status_71; + ZXIC_UINT32 odma_int_status_65; + ZXIC_UINT32 odma_int_status_64; +}DPP_NPPU_ODMA_CFG_ODMA_INT_STATUS_2_T; + +typedef struct dpp_nppu_odma_cfg_odma_int_status_3_t +{ + ZXIC_UINT32 odma_int_status_117; + ZXIC_UINT32 odma_int_status_116; + ZXIC_UINT32 odma_int_status_115; + ZXIC_UINT32 odma_int_status_114; + ZXIC_UINT32 odma_int_status_112; + ZXIC_UINT32 odma_int_status_110; + ZXIC_UINT32 odma_int_status_109; + ZXIC_UINT32 odma_int_status_108; + ZXIC_UINT32 odma_int_status_107; + ZXIC_UINT32 odma_int_status_106; + ZXIC_UINT32 odma_int_status_102; + ZXIC_UINT32 odma_int_status_101; + ZXIC_UINT32 odma_int_status_100; + ZXIC_UINT32 odma_int_status_98; + ZXIC_UINT32 odma_int_status_96; +}DPP_NPPU_ODMA_CFG_ODMA_INT_STATUS_3_T; + +typedef struct dpp_nppu_odma_cfg_sp_tdm_err_nor_cfg_t +{ + ZXIC_UINT32 sp_tdm_err_nor_cfg; +}DPP_NPPU_ODMA_CFG_SP_TDM_ERR_NOR_CFG_T; + +typedef struct dpp_nppu_odma_cfg_etm_dis_ptr_prog_full_cfg_a_t +{ + ZXIC_UINT32 etm_dis_ptr_prog_full_cfg_a; +}DPP_NPPU_ODMA_CFG_ETM_DIS_PTR_PROG_FULL_CFG_A_T; + +typedef struct dpp_nppu_odma_cfg_etm_dis_ptr_prog_full_cfg_n_t +{ + ZXIC_UINT32 etm_dis_ptr_prog_full_cfg_n; +}DPP_NPPU_ODMA_CFG_ETM_DIS_PTR_PROG_FULL_CFG_N_T; + +typedef struct dpp_nppu_odma_cfg_ftm_dis_ptr_prog_full_cfg_a_t +{ + ZXIC_UINT32 ftm_dis_ptr_prog_full_cfg_a; +}DPP_NPPU_ODMA_CFG_FTM_DIS_PTR_PROG_FULL_CFG_A_T; + +typedef struct dpp_nppu_odma_cfg_ftm_dis_ptr_prog_full_cfg_n_t +{ + ZXIC_UINT32 ftm_dis_ptr_prog_full_cfg_n; +}DPP_NPPU_ODMA_CFG_FTM_DIS_PTR_PROG_FULL_CFG_N_T; + +typedef struct dpp_nppu_odma_cfg_tm_dis_fifo_prog_full_cfg_a_t +{ + ZXIC_UINT32 tm_dis_fifo_prog_full_cfg_a; +}DPP_NPPU_ODMA_CFG_TM_DIS_FIFO_PROG_FULL_CFG_A_T; + +typedef struct dpp_nppu_odma_cfg_tm_dis_fifo_prog_full_cfg_n_t +{ + ZXIC_UINT32 tm_dis_fifo_prog_full_cfg_n; +}DPP_NPPU_ODMA_CFG_TM_DIS_FIFO_PROG_FULL_CFG_N_T; + +typedef struct dpp_nppu_odma_cfg_err_prog_full_cfg_a_t +{ + ZXIC_UINT32 err_prog_full_cfg_a; +}DPP_NPPU_ODMA_CFG_ERR_PROG_FULL_CFG_A_T; + +typedef struct dpp_nppu_odma_cfg_err_prog_full_cfg_n_t +{ + ZXIC_UINT32 err_prog_full_cfg_n; +}DPP_NPPU_ODMA_CFG_ERR_PROG_FULL_CFG_N_T; + +typedef struct dpp_nppu_odma_cfg_tdmuc_prog_full_cfg_a_t +{ + ZXIC_UINT32 tdmuc_prog_full_cfg_a; +}DPP_NPPU_ODMA_CFG_TDMUC_PROG_FULL_CFG_A_T; + +typedef struct dpp_nppu_odma_cfg_tdmuc_prog_full_cfg_n_t +{ + ZXIC_UINT32 tdmuc_prog_full_cfg_n; +}DPP_NPPU_ODMA_CFG_TDMUC_PROG_FULL_CFG_N_T; + +typedef struct dpp_nppu_odma_cfg_tdmmc_groupid_prog_full_cfg_a_t +{ + ZXIC_UINT32 tdmmc_groupid_prog_full_cfg_a; +}DPP_NPPU_ODMA_CFG_TDMMC_GROUPID_PROG_FULL_CFG_A_T; + +typedef struct dpp_nppu_odma_cfg_tdmmc_groupid_prog_full_cfg_n_t +{ + ZXIC_UINT32 tdmmc_groupid_prog_full_cfg_n; +}DPP_NPPU_ODMA_CFG_TDMMC_GROUPID_PROG_FULL_CFG_N_T; + +typedef struct dpp_nppu_odma_cfg_tdmmc_no_bitmap_prog_full_cfg_a_t +{ + ZXIC_UINT32 tdmmc_no_bitmap_prog_full_cfg_a; +}DPP_NPPU_ODMA_CFG_TDMMC_NO_BITMAP_PROG_FULL_CFG_A_T; + +typedef struct dpp_nppu_odma_cfg_tdmmc_no_bitmap_prog_full_cfg_n_t +{ + ZXIC_UINT32 tdmmc_no_bitmap_prog_full_cfg_n; +}DPP_NPPU_ODMA_CFG_TDMMC_NO_BITMAP_PROG_FULL_CFG_N_T; + +typedef struct dpp_nppu_odma_cfg_tdmmc_prog_full_cfg_a_t +{ + ZXIC_UINT32 tdmmc_prog_full_cfg_a; +}DPP_NPPU_ODMA_CFG_TDMMC_PROG_FULL_CFG_A_T; + +typedef struct dpp_nppu_odma_cfg_tdmmc_prog_full_cfg_n_t +{ + ZXIC_UINT32 tdmmc_prog_full_cfg_n; +}DPP_NPPU_ODMA_CFG_TDMMC_PROG_FULL_CFG_N_T; + +typedef struct dpp_nppu_odma_cfg_desc_prog_full_cfg_a_t +{ + ZXIC_UINT32 desc_prog_full_cfg_a; +}DPP_NPPU_ODMA_CFG_DESC_PROG_FULL_CFG_A_T; + +typedef struct dpp_nppu_odma_cfg_desc_prog_full_cfg_n_t +{ + ZXIC_UINT32 desc_prog_full_cfg_n; +}DPP_NPPU_ODMA_CFG_DESC_PROG_FULL_CFG_N_T; + +typedef struct dpp_nppu_odma_cfg_dly_prog_full_cfg_a_t +{ + ZXIC_UINT32 dly_prog_full_cfg_a; +}DPP_NPPU_ODMA_CFG_DLY_PROG_FULL_CFG_A_T; + +typedef struct dpp_nppu_odma_cfg_dly_prog_full_cfg_n_t +{ + ZXIC_UINT32 dly_prog_full_cfg_n; +}DPP_NPPU_ODMA_CFG_DLY_PROG_FULL_CFG_N_T; + +typedef struct dpp_nppu_odma_cfg_rsp_prog_full_cfg_a_t +{ + ZXIC_UINT32 rsp_prog_full_cfg_a; +}DPP_NPPU_ODMA_CFG_RSP_PROG_FULL_CFG_A_T; + +typedef struct dpp_nppu_odma_cfg_rsp_prog_full_cfg_n_t +{ + ZXIC_UINT32 rsp_prog_full_cfg_n; +}DPP_NPPU_ODMA_CFG_RSP_PROG_FULL_CFG_N_T; + +typedef struct dpp_nppu_odma_cfg_nor_prog_full_cfg_a_t +{ + ZXIC_UINT32 nor_prog_full_cfg_a; +}DPP_NPPU_ODMA_CFG_NOR_PROG_FULL_CFG_A_T; + +typedef struct dpp_nppu_odma_cfg_nor_prog_full_cfg_n_t +{ + ZXIC_UINT32 nor_prog_full_cfg_n; +}DPP_NPPU_ODMA_CFG_NOR_PROG_FULL_CFG_N_T; + +typedef struct dpp_nppu_odma_cfg_etm_nor_prog_full_cfg_a_t +{ + ZXIC_UINT32 etm_nor_prog_full_cfg_a; +}DPP_NPPU_ODMA_CFG_ETM_NOR_PROG_FULL_CFG_A_T; + +typedef struct dpp_nppu_odma_cfg_etm_nor_prog_full_cfg_n_t +{ + ZXIC_UINT32 etm_nor_prog_full_cfg_n; +}DPP_NPPU_ODMA_CFG_ETM_NOR_PROG_FULL_CFG_N_T; + +typedef struct dpp_nppu_odma_cfg_ftm_nor_prog_full_cfg_a_t +{ + ZXIC_UINT32 ftm_nor_prog_full_cfg_a; +}DPP_NPPU_ODMA_CFG_FTM_NOR_PROG_FULL_CFG_A_T; + +typedef struct dpp_nppu_odma_cfg_ftm_nor_prog_full_cfg_n_t +{ + ZXIC_UINT32 ftm_nor_prog_full_cfg_n; +}DPP_NPPU_ODMA_CFG_FTM_NOR_PROG_FULL_CFG_N_T; + +typedef struct dpp_nppu_odma_cfg_etm_prog_full_cfg_a_t +{ + ZXIC_UINT32 etm_prog_full_cfg_a; +}DPP_NPPU_ODMA_CFG_ETM_PROG_FULL_CFG_A_T; + +typedef struct dpp_nppu_odma_cfg_etm_prog_full_cfg_n_t +{ + ZXIC_UINT32 etm_prog_full_cfg_n; +}DPP_NPPU_ODMA_CFG_ETM_PROG_FULL_CFG_N_T; + +typedef struct dpp_nppu_odma_cfg_ftm_prog_full_cfg_a_t +{ + ZXIC_UINT32 ftm_prog_full_cfg_a; +}DPP_NPPU_ODMA_CFG_FTM_PROG_FULL_CFG_A_T; + +typedef struct dpp_nppu_odma_cfg_ftm_prog_full_cfg_n_t +{ + ZXIC_UINT32 ftm_prog_full_cfg_n; +}DPP_NPPU_ODMA_CFG_FTM_PROG_FULL_CFG_N_T; + +typedef struct dpp_nppu_odma_cfg_etm_nrdcnt_prog_full_cfg_a_t +{ + ZXIC_UINT32 etm_nrdcnt_prog_full_cfg_a; +}DPP_NPPU_ODMA_CFG_ETM_NRDCNT_PROG_FULL_CFG_A_T; + +typedef struct dpp_nppu_odma_cfg_etm_nrdcnt_prog_full_cfg_n_t +{ + ZXIC_UINT32 etm_nrdcnt_prog_full_cfg_n; +}DPP_NPPU_ODMA_CFG_ETM_NRDCNT_PROG_FULL_CFG_N_T; + +typedef struct dpp_nppu_odma_cfg_ftm_nrdcnt_prog_full_cfg_a_t +{ + ZXIC_UINT32 ftm_nrdcnt_prog_full_cfg_a; +}DPP_NPPU_ODMA_CFG_FTM_NRDCNT_PROG_FULL_CFG_A_T; + +typedef struct dpp_nppu_odma_cfg_ftm_nrdcnt_prog_full_cfg_n_t +{ + ZXIC_UINT32 ftm_nrdcnt_prog_full_cfg_n; +}DPP_NPPU_ODMA_CFG_FTM_NRDCNT_PROG_FULL_CFG_N_T; + +typedef struct dpp_nppu_odma_cfg_pp_prog_full_cfg_a_t +{ + ZXIC_UINT32 pp_prog_full_cfg_a; +}DPP_NPPU_ODMA_CFG_PP_PROG_FULL_CFG_A_T; + +typedef struct dpp_nppu_odma_cfg_pp_prog_full_cfg_n_t +{ + ZXIC_UINT32 pp_prog_full_cfg_n; +}DPP_NPPU_ODMA_CFG_PP_PROG_FULL_CFG_N_T; + +typedef struct dpp_nppu_odma_cfg_tm_weight_t +{ + ZXIC_UINT32 tm_weight; +}DPP_NPPU_ODMA_CFG_TM_WEIGHT_T; + +typedef struct dpp_nppu_odma_cfg_pp_weight_t +{ + ZXIC_UINT32 pp_weight; +}DPP_NPPU_ODMA_CFG_PP_WEIGHT_T; + +typedef struct dpp_nppu_odma_cfg_ifbcmd_prog_full_cfg_a_t +{ + ZXIC_UINT32 ifbcmd_prog_full_cfg_a; +}DPP_NPPU_ODMA_CFG_IFBCMD_PROG_FULL_CFG_A_T; + +typedef struct dpp_nppu_odma_cfg_ifbcmd_prog_full_cfg_n_t +{ + ZXIC_UINT32 ifbcmd_prog_full_cfg_n; +}DPP_NPPU_ODMA_CFG_IFBCMD_PROG_FULL_CFG_N_T; + +typedef struct dpp_nppu_odma_cfg_mccnt_prog_full_cfg_a_t +{ + ZXIC_UINT32 mccnt_prog_full_cfg_a; +}DPP_NPPU_ODMA_CFG_MCCNT_PROG_FULL_CFG_A_T; + +typedef struct dpp_nppu_odma_cfg_mccnt_prog_full_cfg_n_t +{ + ZXIC_UINT32 mccnt_prog_full_cfg_n; +}DPP_NPPU_ODMA_CFG_MCCNT_PROG_FULL_CFG_N_T; + +typedef struct dpp_nppu_odma_cfg_int_or_pon_t +{ + ZXIC_UINT32 int_or_pon; +}DPP_NPPU_ODMA_CFG_INT_OR_PON_T; + +typedef struct dpp_nppu_odma_cfg_quemng_cnt_in_err_cnt_t +{ + ZXIC_UINT32 quemng_cnt_in_err_cnt; +}DPP_NPPU_ODMA_CFG_QUEMNG_CNT_IN_ERR_CNT_T; + +typedef struct dpp_nppu_odma_cfg_lif0_port_eop_cnt_t +{ + ZXIC_UINT32 lif0_port_eop_cnt; +}DPP_NPPU_ODMA_CFG_LIF0_PORT_EOP_CNT_T; + +typedef struct dpp_nppu_odma_cfg_lif1_port_eop_cnt_t +{ + ZXIC_UINT32 lif1_port_eop_cnt; +}DPP_NPPU_ODMA_CFG_LIF1_PORT_EOP_CNT_T; + +typedef struct dpp_nppu_odma_cfg_lifc_port0_eop_cnt_t +{ + ZXIC_UINT32 lifc_port0_eop_cnt; +}DPP_NPPU_ODMA_CFG_LIFC_PORT0_EOP_CNT_T; + +typedef struct dpp_nppu_odma_cfg_lifc_port1_eop_cnt_t +{ + ZXIC_UINT32 lifc_port1_eop_cnt; +}DPP_NPPU_ODMA_CFG_LIFC_PORT1_EOP_CNT_T; + +typedef struct dpp_nppu_odma_cfg_fptr_fifo_prog_ept_cfg_n_t +{ + ZXIC_UINT32 fptr_fifo_prog_ept_cfg_n; +}DPP_NPPU_ODMA_CFG_FPTR_FIFO_PROG_EPT_CFG_N_T; + +typedef struct dpp_nppu_odma_cfg_isu_fifo_prog_full_cfg_a_t +{ + ZXIC_UINT32 isu_fifo_prog_full_cfg_a; +}DPP_NPPU_ODMA_CFG_ISU_FIFO_PROG_FULL_CFG_A_T; + +typedef struct dpp_nppu_odma_cfg_isu_fifo_prog_full_cfg_n_t +{ + ZXIC_UINT32 isu_fifo_prog_full_cfg_n; +}DPP_NPPU_ODMA_CFG_ISU_FIFO_PROG_FULL_CFG_N_T; + +typedef struct dpp_nppu_oam_cfg_ind_access_done_t +{ + ZXIC_UINT32 ind_access_done; +}DPP_NPPU_OAM_CFG_IND_ACCESS_DONE_T; + +typedef struct dpp_nppu_oam_cfg_ind_access_command_t +{ + ZXIC_UINT32 ind_rd_or_wr; + ZXIC_UINT32 ind_mem_mask; + ZXIC_UINT32 ind_mem_id; + ZXIC_UINT32 ind_mem_addr; +}DPP_NPPU_OAM_CFG_IND_ACCESS_COMMAND_T; + +typedef struct dpp_nppu_oam_cfg_ind_dat0_t +{ + ZXIC_UINT32 ind_dat0; +}DPP_NPPU_OAM_CFG_IND_DAT0_T; + +typedef struct dpp_nppu_oam_cfg_ind_dat1_t +{ + ZXIC_UINT32 ind_dat1; +}DPP_NPPU_OAM_CFG_IND_DAT1_T; + +typedef struct dpp_nppu_oam_cfg_ind_dat2_t +{ + ZXIC_UINT32 ind_dat2; +}DPP_NPPU_OAM_CFG_IND_DAT2_T; + +typedef struct dpp_nppu_oam_cfg_ind_dat3_t +{ + ZXIC_UINT32 ind_dat3; +}DPP_NPPU_OAM_CFG_IND_DAT3_T; + +typedef struct dpp_nppu_oam_cfg_oam_tx_main_en_t +{ + ZXIC_UINT32 oam_tx_main_en; +}DPP_NPPU_OAM_CFG_OAM_TX_MAIN_EN_T; + +typedef struct dpp_nppu_oam_cfg_tx_total_num_t +{ + ZXIC_UINT32 tx_total_num; +}DPP_NPPU_OAM_CFG_TX_TOTAL_NUM_T; + +typedef struct dpp_nppu_oam_cfg_oam_chk_main_en_t +{ + ZXIC_UINT32 oam_chk_main_en; +}DPP_NPPU_OAM_CFG_OAM_CHK_MAIN_EN_T; + +typedef struct dpp_nppu_oam_cfg_chk_total_num0_t +{ + ZXIC_UINT32 chk_total_num0; +}DPP_NPPU_OAM_CFG_CHK_TOTAL_NUM0_T; + +typedef struct dpp_nppu_oam_cfg_ma_chk_main_en_t +{ + ZXIC_UINT32 oam_chk_main_en; +}DPP_NPPU_OAM_CFG_MA_CHK_MAIN_EN_T; + +typedef struct dpp_nppu_oam_cfg_chk_total_num1_t +{ + ZXIC_UINT32 chk_total_num0; +}DPP_NPPU_OAM_CFG_CHK_TOTAL_NUM1_T; + +typedef struct dpp_nppu_oam_cfg_tx_stat_en_t +{ + ZXIC_UINT32 tx_stat_en; +}DPP_NPPU_OAM_CFG_TX_STAT_EN_T; + +typedef struct dpp_nppu_oam_cfg_rec_stat_en_t +{ + ZXIC_UINT32 rec_stat_en; +}DPP_NPPU_OAM_CFG_REC_STAT_EN_T; + +typedef struct dpp_nppu_oam_cfg_stat_oam_rdy_mask_t +{ + ZXIC_UINT32 stat_oam_rdy_mask; +}DPP_NPPU_OAM_CFG_STAT_OAM_RDY_MASK_T; + +typedef struct dpp_nppu_oam_cfg_session_grading0_t +{ + ZXIC_UINT32 session_grading0; +}DPP_NPPU_OAM_CFG_SESSION_GRADING0_T; + +typedef struct dpp_nppu_oam_cfg_session_grading1_t +{ + ZXIC_UINT32 session_grading1; +}DPP_NPPU_OAM_CFG_SESSION_GRADING1_T; + +typedef struct dpp_nppu_oam_cfg_session_grading2_t +{ + ZXIC_UINT32 session_grading2; +}DPP_NPPU_OAM_CFG_SESSION_GRADING2_T; + +typedef struct dpp_nppu_oam_cfg_session_grading3_t +{ + ZXIC_UINT32 session_grading3; +}DPP_NPPU_OAM_CFG_SESSION_GRADING3_T; + +typedef struct dpp_nppu_oam_cfg_bfd_chk_haddr_t +{ + ZXIC_UINT32 bfd_chk_haddr; +}DPP_NPPU_OAM_CFG_BFD_CHK_HADDR_T; + +typedef struct dpp_nppu_oam_cfg_ethccm_chk_haddr_t +{ + ZXIC_UINT32 ethccm_chk_haddr; +}DPP_NPPU_OAM_CFG_ETHCCM_CHK_HADDR_T; + +typedef struct dpp_nppu_oam_cfg_tpbfd_chk_haddr_t +{ + ZXIC_UINT32 tpbfd_chk_haddr; +}DPP_NPPU_OAM_CFG_TPBFD_CHK_HADDR_T; + +typedef struct dpp_nppu_oam_cfg_tpoam_ccm_chk_haddr_t +{ + ZXIC_UINT32 tpoam_ccm_chk_haddr; +}DPP_NPPU_OAM_CFG_TPOAM_CCM_CHK_HADDR_T; + +typedef struct dpp_nppu_oam_cfg_bfd_tx_haddr_t +{ + ZXIC_UINT32 bfd_tx_haddr; +}DPP_NPPU_OAM_CFG_BFD_TX_HADDR_T; + +typedef struct dpp_nppu_oam_cfg_ethccm_tx_haddr_t +{ + ZXIC_UINT32 ethccm_tx_haddr; +}DPP_NPPU_OAM_CFG_ETHCCM_TX_HADDR_T; + +typedef struct dpp_nppu_oam_cfg_tpbfd_tx_haddr_t +{ + ZXIC_UINT32 tpbfd_tx_haddr; +}DPP_NPPU_OAM_CFG_TPBFD_TX_HADDR_T; + +typedef struct dpp_nppu_oam_cfg_tpoam_ccm_tx_haddr_t +{ + ZXIC_UINT32 tpoam_ccm_tx_haddr; +}DPP_NPPU_OAM_CFG_TPOAM_CCM_TX_HADDR_T; + +typedef struct dpp_nppu_oam_cfg_ethccm_ma_chk_haddr_t +{ + ZXIC_UINT32 ethccm_ma_chk_haddr; +}DPP_NPPU_OAM_CFG_ETHCCM_MA_CHK_HADDR_T; + +typedef struct dpp_nppu_oam_cfg_tpccm_ma_chk_haddr_t +{ + ZXIC_UINT32 tpccm_ma_chk_haddr; +}DPP_NPPU_OAM_CFG_TPCCM_MA_CHK_HADDR_T; + +typedef struct dpp_nppu_oam_cfg_groupnum_ram_clr_t +{ + ZXIC_UINT32 groupnum_ram_clr; +}DPP_NPPU_OAM_CFG_GROUPNUM_RAM_CLR_T; + +typedef struct dpp_nppu_oam_cfg_index_ram0_clr_t +{ + ZXIC_UINT32 index_ram0_clr; +}DPP_NPPU_OAM_CFG_INDEX_RAM0_CLR_T; + +typedef struct dpp_nppu_oam_cfg_index_ram1_clr_t +{ + ZXIC_UINT32 index_ram1_clr; +}DPP_NPPU_OAM_CFG_INDEX_RAM1_CLR_T; + +typedef struct dpp_nppu_oam_cfg_rmep_ram_clr_t +{ + ZXIC_UINT32 rmep_ram_clr; +}DPP_NPPU_OAM_CFG_RMEP_RAM_CLR_T; + +typedef struct dpp_nppu_oam_cfg_ma_ram_clr_t +{ + ZXIC_UINT32 ma_ram_clr; +}DPP_NPPU_OAM_CFG_MA_RAM_CLR_T; + +typedef struct dpp_nppu_oam_cfg_ram_init_done_t +{ + ZXIC_UINT32 ram_init_done; +}DPP_NPPU_OAM_CFG_RAM_INIT_DONE_T; + +typedef struct dpp_nppu_oam_cfg_rec_bfd_debug_en_t +{ + ZXIC_UINT32 rec_bfd_debug_en; +}DPP_NPPU_OAM_CFG_REC_BFD_DEBUG_EN_T; + +typedef struct dpp_nppu_oam_cfg_oam_session_int_t +{ + ZXIC_UINT32 tpma_int; + ZXIC_UINT32 ethma_int; + ZXIC_UINT32 bfd_int; + ZXIC_UINT32 ethoam_int; + ZXIC_UINT32 tpbfd_int; + ZXIC_UINT32 tpoam_int; +}DPP_NPPU_OAM_CFG_OAM_SESSION_INT_T; + +typedef struct dpp_nppu_oam_cfg_pon_int_t +{ + ZXIC_UINT32 fifo_int; + ZXIC_UINT32 pon_protect_int; +}DPP_NPPU_OAM_CFG_PON_INT_T; + +typedef struct dpp_nppu_oam_cfg_oam_int_clr_t +{ + ZXIC_UINT32 oam_int_clr; +}DPP_NPPU_OAM_CFG_OAM_INT_CLR_T; + +typedef struct dpp_nppu_oam_cfg_type_int_clr0_t +{ + ZXIC_UINT32 tpma_int_clr; + ZXIC_UINT32 ethma_int_clr; + ZXIC_UINT32 bfd_int_clr; + ZXIC_UINT32 ethoam_int_clr; + ZXIC_UINT32 tpbfd_int_clr; + ZXIC_UINT32 tpoam_int_clr; +}DPP_NPPU_OAM_CFG_TYPE_INT_CLR0_T; + +typedef struct dpp_nppu_oam_cfg_type_int_clr1_t +{ + ZXIC_UINT32 fifo_int_clr; + ZXIC_UINT32 pon_protect_int_clr; +}DPP_NPPU_OAM_CFG_TYPE_INT_CLR1_T; + +typedef struct dpp_nppu_oam_cfg_interrupt_mask_t +{ + ZXIC_UINT32 fifo_interrupt_mask; + ZXIC_UINT32 pon_protect_interruptmask; + ZXIC_UINT32 tpma_interrupt_mask; + ZXIC_UINT32 ethma_interrupt_mask; + ZXIC_UINT32 bfd_interrupt_mask; + ZXIC_UINT32 ethoam_interrupt_mask; + ZXIC_UINT32 tpbfd_interrupt_mask; + ZXIC_UINT32 tpoam_interrupt_mask; +}DPP_NPPU_OAM_CFG_INTERRUPT_MASK_T; + +typedef struct dpp_nppu_oam_cfg_int0_index_t +{ + ZXIC_UINT32 int0_index0; +}DPP_NPPU_OAM_CFG_INT0_INDEX_T; + +typedef struct dpp_nppu_oam_cfg_int1_index_t +{ + ZXIC_UINT32 int1_index0; +}DPP_NPPU_OAM_CFG_INT1_INDEX_T; + +typedef struct dpp_nppu_oam_cfg_int0_index_region_t +{ + ZXIC_UINT32 int0_index_region; +}DPP_NPPU_OAM_CFG_INT0_INDEX_REGION_T; + +typedef struct dpp_nppu_oam_cfg_int1_index_region_t +{ + ZXIC_UINT32 int1_index_region; +}DPP_NPPU_OAM_CFG_INT1_INDEX_REGION_T; + +typedef struct dpp_nppu_oam_cfg_bdiinfo_fwft_fifo_th_t +{ + ZXIC_UINT32 bdiinfo_fwft_fifo_th; +}DPP_NPPU_OAM_CFG_BDIINFO_FWFT_FIFO_TH_T; + +typedef struct dpp_nppu_oam_cfg_recsec_fwft_fifo_th_t +{ + ZXIC_UINT32 recsec_fwft_fifo_th; +}DPP_NPPU_OAM_CFG_RECSEC_FWFT_FIFO_TH_T; + +typedef struct dpp_nppu_oam_cfg_timing_chk_info0_fwft_fifo_th_t +{ + ZXIC_UINT32 timing_chk_info0_fwft_fifo_th; +}DPP_NPPU_OAM_CFG_TIMING_CHK_INFO0_FWFT_FIFO_TH_T; + +typedef struct dpp_nppu_oam_cfg_recma_fwft_fifo_th_t +{ + ZXIC_UINT32 recma_fwft_fifo_th; +}DPP_NPPU_OAM_CFG_RECMA_FWFT_FIFO_TH_T; + +typedef struct dpp_nppu_oam_cfg_timing_chk_info1_fwft_fifo_th_t +{ + ZXIC_UINT32 timing_chk_info1_fwft_fifo_th; +}DPP_NPPU_OAM_CFG_TIMING_CHK_INFO1_FWFT_FIFO_TH_T; + +typedef struct dpp_nppu_oam_cfg_oam_txinst_fifo_th_t +{ + ZXIC_UINT32 oam_txinst_fifo_th; +}DPP_NPPU_OAM_CFG_OAM_TXINST_FIFO_TH_T; + +typedef struct dpp_nppu_oam_cfg_oam_rdinfo_fwft_fifo_th_t +{ + ZXIC_UINT32 oam_rdinfo_fwft_fifo_th; +}DPP_NPPU_OAM_CFG_OAM_RDINFO_FWFT_FIFO_TH_T; + +typedef struct dpp_nppu_oam_cfg_lm_cnt_fwft_fifo_th_t +{ + ZXIC_UINT32 lm_cnt_fwft_fifo_th; +}DPP_NPPU_OAM_CFG_LM_CNT_FWFT_FIFO_TH_T; + +typedef struct dpp_nppu_oam_cfg_oam_pkt_fifo_th_t +{ + ZXIC_UINT32 oam_pkt_fifo_th; +}DPP_NPPU_OAM_CFG_OAM_PKT_FIFO_TH_T; + +typedef struct dpp_nppu_oam_cfg_reclm_stat_fifo_th_t +{ + ZXIC_UINT32 reclm_stat_fifo_th; +}DPP_NPPU_OAM_CFG_RECLM_STAT_FIFO_TH_T; + +typedef struct dpp_nppu_oam_cfg_txlm_stat_fifo_th_t +{ + ZXIC_UINT32 txlm_stat_fifo_th; +}DPP_NPPU_OAM_CFG_TXLM_STAT_FIFO_TH_T; + +typedef struct dpp_nppu_oam_cfg_oam_chk_fwft_fifo_th_t +{ + ZXIC_UINT32 oam_chk_fwft_fifo_th; +}DPP_NPPU_OAM_CFG_OAM_CHK_FWFT_FIFO_TH_T; + +typedef struct dpp_nppu_oam_cfg_txoam_stat_fifo_th_t +{ + ZXIC_UINT32 txoam_stat_fifo_th; +}DPP_NPPU_OAM_CFG_TXOAM_STAT_FIFO_TH_T; + +typedef struct dpp_nppu_oam_cfg_recoam_stat_fifo_th_t +{ + ZXIC_UINT32 recoam_stat_fifo_th; +}DPP_NPPU_OAM_CFG_RECOAM_STAT_FIFO_TH_T; + +typedef struct dpp_nppu_oam_cfg_txpkt_data_fwft_fifo_th_t +{ + ZXIC_UINT32 txpkt_data_fwft_fifo_th; +}DPP_NPPU_OAM_CFG_TXPKT_DATA_FWFT_FIFO_TH_T; + +typedef struct dpp_nppu_oam_cfg_tstpkt_fwft_fifo_th_t +{ + ZXIC_UINT32 tstpkt_fwft_fifo_th; +}DPP_NPPU_OAM_CFG_TSTPKT_FWFT_FIFO_TH_T; + +typedef struct dpp_nppu_oam_cfg_tst_txinst_fwft_fifo_th_t +{ + ZXIC_UINT32 tst_txinst_fwft_fifo_th; +}DPP_NPPU_OAM_CFG_TST_TXINST_FWFT_FIFO_TH_T; + +typedef struct dpp_nppu_oam_cfg_tstrx_main_en_t +{ + ZXIC_UINT32 tstrx_main_en; +}DPP_NPPU_OAM_CFG_TSTRX_MAIN_EN_T; + +typedef struct dpp_nppu_oam_cfg_tsttx_cfg_para_tbl2_t +{ + ZXIC_UINT32 ddr_self_test_tx_en; + ZXIC_UINT32 tm_self_test_tx_en; + ZXIC_UINT32 fast_aging_tx_en; + ZXIC_UINT32 timing_aging_tx_en; + ZXIC_UINT32 backgroud_flow_tx_en; + ZXIC_UINT32 tsttx_tx_en; + ZXIC_UINT32 tx_freq; + ZXIC_UINT32 tx_offset; +}DPP_NPPU_OAM_CFG_TSTTX_CFG_PARA_TBL2_T; + +typedef struct dpp_nppu_oam_cfg_tsttx_cfg_para_tbl1_t +{ + ZXIC_UINT32 tx_count; +}DPP_NPPU_OAM_CFG_TSTTX_CFG_PARA_TBL1_T; + +typedef struct dpp_nppu_oam_cfg_tsttx_cfg_para_tbl0_t +{ + ZXIC_UINT32 fast_tx_mode_en; + ZXIC_UINT32 tsttx_tx_head_len; + ZXIC_UINT32 tsttx_tx_interval; +}DPP_NPPU_OAM_CFG_TSTTX_CFG_PARA_TBL0_T; + +typedef struct dpp_nppu_oam_cfg_tstrx_cfg_para_t +{ + ZXIC_UINT32 tstrx_session_num; + ZXIC_UINT32 tstrx_session_en; +}DPP_NPPU_OAM_CFG_TSTRX_CFG_PARA_T; + +typedef struct dpp_nppu_oam_cfg_fifo_status_int_en_0_t +{ + ZXIC_UINT32 fifo_status_int_en_31; + ZXIC_UINT32 fifo_status_int_en_30; + ZXIC_UINT32 fifo_status_int_en_29; + ZXIC_UINT32 fifo_status_int_en_28; + ZXIC_UINT32 fifo_status_int_en_27; + ZXIC_UINT32 fifo_status_int_en_26; + ZXIC_UINT32 fifo_status_int_en_25; + ZXIC_UINT32 fifo_status_int_en_24; + ZXIC_UINT32 fifo_status_int_en_23; + ZXIC_UINT32 fifo_status_int_en_22; + ZXIC_UINT32 fifo_status_int_en_21; + ZXIC_UINT32 fifo_status_int_en_20; + ZXIC_UINT32 fifo_status_int_en_19; + ZXIC_UINT32 fifo_status_int_en_18; + ZXIC_UINT32 fifo_status_int_en_17; + ZXIC_UINT32 fifo_status_int_en_16; + ZXIC_UINT32 fifo_status_int_en_15; + ZXIC_UINT32 fifo_status_int_en_14; + ZXIC_UINT32 fifo_status_int_en_13; + ZXIC_UINT32 fifo_status_int_en_12; + ZXIC_UINT32 fifo_status_int_en_11; + ZXIC_UINT32 fifo_status_int_en_10; + ZXIC_UINT32 fifo_status_int_en_9; + ZXIC_UINT32 fifo_status_int_en_8; + ZXIC_UINT32 fifo_status_int_en_7; + ZXIC_UINT32 fifo_status_int_en_6; + ZXIC_UINT32 fifo_status_int_en_5; + ZXIC_UINT32 fifo_status_int_en_4; + ZXIC_UINT32 fifo_status_int_en_3; + ZXIC_UINT32 fifo_status_int_en_2; + ZXIC_UINT32 fifo_status_int_en_1; + ZXIC_UINT32 fifo_status_int_en_0; +}DPP_NPPU_OAM_CFG_FIFO_STATUS_INT_EN_0_T; + +typedef struct dpp_nppu_oam_cfg_fifo_status_int_en_1_t +{ + ZXIC_UINT32 fifo_status_int_en_41; + ZXIC_UINT32 fifo_status_int_en_40; + ZXIC_UINT32 fifo_status_int_en_39; + ZXIC_UINT32 fifo_status_int_en_38; + ZXIC_UINT32 fifo_status_int_en_37; + ZXIC_UINT32 fifo_status_int_en_36; + ZXIC_UINT32 fifo_status_int_en_35; + ZXIC_UINT32 fifo_status_int_en_34; + ZXIC_UINT32 fifo_status_int_en_33; + ZXIC_UINT32 fifo_status_int_en_32; +}DPP_NPPU_OAM_CFG_FIFO_STATUS_INT_EN_1_T; + +typedef struct dpp_nppu_oam_cfg_fifo_status_int_mask_0_t +{ + ZXIC_UINT32 fifo_status_int_mask_31; + ZXIC_UINT32 fifo_status_int_mask_30; + ZXIC_UINT32 fifo_status_int_mask_29; + ZXIC_UINT32 fifo_status_int_mask_28; + ZXIC_UINT32 fifo_status_int_mask_27; + ZXIC_UINT32 fifo_status_int_mask_26; + ZXIC_UINT32 fifo_status_int_mask_25; + ZXIC_UINT32 fifo_status_int_mask_24; + ZXIC_UINT32 fifo_status_int_mask_23; + ZXIC_UINT32 fifo_status_int_mask_22; + ZXIC_UINT32 fifo_status_int_mask_21; + ZXIC_UINT32 fifo_status_int_mask_20; + ZXIC_UINT32 fifo_status_int_mask_19; + ZXIC_UINT32 fifo_status_int_mask_18; + ZXIC_UINT32 fifo_status_int_mask_17; + ZXIC_UINT32 fifo_status_int_mask_16; + ZXIC_UINT32 fifo_status_int_mask_15; + ZXIC_UINT32 fifo_status_int_mask_14; + ZXIC_UINT32 fifo_status_int_mask_13; + ZXIC_UINT32 fifo_status_int_mask_12; + ZXIC_UINT32 fifo_status_int_mask_11; + ZXIC_UINT32 fifo_status_int_mask_10; + ZXIC_UINT32 fifo_status_int_mask_9; + ZXIC_UINT32 fifo_status_int_mask_8; + ZXIC_UINT32 fifo_status_int_mask_7; + ZXIC_UINT32 fifo_status_int_mask_6; + ZXIC_UINT32 fifo_status_int_mask_5; + ZXIC_UINT32 fifo_status_int_mask_4; + ZXIC_UINT32 fifo_status_int_mask_3; + ZXIC_UINT32 fifo_status_int_mask_2; + ZXIC_UINT32 fifo_status_int_mask_1; + ZXIC_UINT32 fifo_status_int_mask_0; +}DPP_NPPU_OAM_CFG_FIFO_STATUS_INT_MASK_0_T; + +typedef struct dpp_nppu_oam_cfg_fifo_status_int_mask_1_t +{ + ZXIC_UINT32 fifo_status_int_mask_41; + ZXIC_UINT32 fifo_status_int_mask_40; + ZXIC_UINT32 fifo_status_int_mask_39; + ZXIC_UINT32 fifo_status_int_mask_38; + ZXIC_UINT32 fifo_status_int_mask_37; + ZXIC_UINT32 fifo_status_int_mask_36; + ZXIC_UINT32 fifo_status_int_mask_35; + ZXIC_UINT32 fifo_status_int_mask_34; + ZXIC_UINT32 fifo_status_int_mask_33; + ZXIC_UINT32 fifo_status_int_mask_32; +}DPP_NPPU_OAM_CFG_FIFO_STATUS_INT_MASK_1_T; + +typedef struct dpp_nppu_oam_cfg_fifo_status_int_status_t +{ + ZXIC_UINT32 fifo_status_int_status; +}DPP_NPPU_OAM_CFG_FIFO_STATUS_INT_STATUS_T; + +typedef struct dpp_nppu_oam_cfg_main_frequency_t +{ + ZXIC_UINT32 main_frequency; +}DPP_NPPU_OAM_CFG_MAIN_FREQUENCY_T; + +typedef struct dpp_nppu_oam_cfg_oam_cfg_type_t +{ + ZXIC_UINT32 oam_cfg_type; +}DPP_NPPU_OAM_CFG_OAM_CFG_TYPE_T; + +typedef struct dpp_nppu_oam_cfg_fst_swch_eth_head0_t +{ + ZXIC_UINT32 fst_swch_eth_head; +}DPP_NPPU_OAM_CFG_FST_SWCH_ETH_HEAD0_T; + +typedef struct dpp_nppu_oam_cfg_fst_swch_eth_head1_t +{ + ZXIC_UINT32 fst_swch_eth_head1; +}DPP_NPPU_OAM_CFG_FST_SWCH_ETH_HEAD1_T; + +typedef struct dpp_nppu_oam_cfg_fst_swch_eth_head2_t +{ + ZXIC_UINT32 fst_swch_eth_head2; +}DPP_NPPU_OAM_CFG_FST_SWCH_ETH_HEAD2_T; + +typedef struct dpp_nppu_oam_cfg_fst_swch_eth_head3_t +{ + ZXIC_UINT32 fst_swch_eth_head3; +}DPP_NPPU_OAM_CFG_FST_SWCH_ETH_HEAD3_T; + +typedef struct dpp_nppu_oam_cfg_oam_fs_txinst_fifo_th_t +{ + ZXIC_UINT32 oam_fs_txinst_fifo_th; +}DPP_NPPU_OAM_CFG_OAM_FS_TXINST_FIFO_TH_T; + +typedef struct dpp_nppu_oam_cfg_oam_ma_fs_txinst_fifo_th_t +{ + ZXIC_UINT32 oam_ma_fs_txinst_fifo_th; +}DPP_NPPU_OAM_CFG_OAM_MA_FS_TXINST_FIFO_TH_T; + +typedef struct dpp_nppu_oam_cfg_pon_int_ram_clr_t +{ + ZXIC_UINT32 pon_int_ram_clr; +}DPP_NPPU_OAM_CFG_PON_INT_RAM_CLR_T; + +typedef struct dpp_nppu_oam_cfg_pon_p_int_index_t +{ + ZXIC_UINT32 pon_p_int_index; +}DPP_NPPU_OAM_CFG_PON_P_INT_INDEX_T; + +typedef struct dpp_nppu_oam_cfg_pon_protect_pkt_fifo_th_t +{ + ZXIC_UINT32 pon_protect_pkt_fifo_th; +}DPP_NPPU_OAM_CFG_PON_PROTECT_PKT_FIFO_TH_T; + +typedef struct dpp_nppu_oam_cfg_pon_laser_off_en_t +{ + ZXIC_UINT32 pon_laser_off_en; +}DPP_NPPU_OAM_CFG_PON_LASER_OFF_EN_T; + +typedef struct dpp_nppu_oam_cfg_pon_prtct_pkt_tx_en_t +{ + ZXIC_UINT32 pon_prtct_pkt_tx_en; +}DPP_NPPU_OAM_CFG_PON_PRTCT_PKT_TX_EN_T; + +typedef struct dpp_nppu_oam_cfg_cfg_pon_master_t +{ + ZXIC_UINT32 cfg_pon_master; +}DPP_NPPU_OAM_CFG_CFG_PON_MASTER_T; + +typedef struct dpp_nppu_oam_cfg_level_mode_t +{ + ZXIC_UINT32 level_mode; +}DPP_NPPU_OAM_CFG_LEVEL_MODE_T; + +typedef struct dpp_nppu_oam_cfg_interrupt_en_t +{ + ZXIC_UINT32 interrupt_en; +}DPP_NPPU_OAM_CFG_INTERRUPT_EN_T; + +typedef struct dpp_nppu_oam_cfg_pon_laser_on_en_t +{ + ZXIC_UINT32 pon_laser_on_en; +}DPP_NPPU_OAM_CFG_PON_LASER_ON_EN_T; + +typedef struct dpp_nppu_oam_cfg_ti_pon_sd_t +{ + ZXIC_UINT32 ti_pon_sd; +}DPP_NPPU_OAM_CFG_TI_PON_SD_T; + +typedef struct dpp_nppu_oam_cfg_ti_pon_los_t +{ + ZXIC_UINT32 ti_pon_los; +}DPP_NPPU_OAM_CFG_TI_PON_LOS_T; + +typedef struct dpp_nppu_oam_cfg_ind_dat4_t +{ + ZXIC_UINT32 ind_dat4; +}DPP_NPPU_OAM_CFG_IND_DAT4_T; + +typedef struct dpp_nppu_oam_cfg_ind_dat5_t +{ + ZXIC_UINT32 ind_dat5; +}DPP_NPPU_OAM_CFG_IND_DAT5_T; + +typedef struct dpp_nppu_oam_cfg_ind_dat6_t +{ + ZXIC_UINT32 ind_dat6; +}DPP_NPPU_OAM_CFG_IND_DAT6_T; + +typedef struct dpp_nppu_oam_cfg_ind_dat7_t +{ + ZXIC_UINT32 ind_dat7; +}DPP_NPPU_OAM_CFG_IND_DAT7_T; + +typedef struct dpp_nppu_oam_cfg_ind_dat8_t +{ + ZXIC_UINT32 ind_dat8; +}DPP_NPPU_OAM_CFG_IND_DAT8_T; + +typedef struct dpp_nppu_oam_cfg_ind_dat9_t +{ + ZXIC_UINT32 ind_dat9; +}DPP_NPPU_OAM_CFG_IND_DAT9_T; + +typedef struct dpp_nppu_oam_cfg_ind_dat10_t +{ + ZXIC_UINT32 ind_dat10; +}DPP_NPPU_OAM_CFG_IND_DAT10_T; + +typedef struct dpp_nppu_oam_cfg_ind_dat11_t +{ + ZXIC_UINT32 ind_dat11; +}DPP_NPPU_OAM_CFG_IND_DAT11_T; + +typedef struct dpp_nppu_oam_cfg_ind_dat12_t +{ + ZXIC_UINT32 ind_dat12; +}DPP_NPPU_OAM_CFG_IND_DAT12_T; + +typedef struct dpp_nppu_oam_cfg_ind_dat13_t +{ + ZXIC_UINT32 ind_dat13; +}DPP_NPPU_OAM_CFG_IND_DAT13_T; + +typedef struct dpp_nppu_oam_cfg_ind_dat14_t +{ + ZXIC_UINT32 ind_dat14; +}DPP_NPPU_OAM_CFG_IND_DAT14_T; + +typedef struct dpp_nppu_oam_cfg_ind_dat15_t +{ + ZXIC_UINT32 ind_dat15; +}DPP_NPPU_OAM_CFG_IND_DAT15_T; + +typedef struct dpp_nppu_oam_cfg_oam_2544_pkt_fifo_th_t +{ + ZXIC_UINT32 oam_2544_pkt_fifo_th; +}DPP_NPPU_OAM_CFG_OAM_2544_PKT_FIFO_TH_T; + +typedef struct dpp_nppu_oam_cfg_txinfo_ram_clr_t +{ + ZXIC_UINT32 txinfo_ram_clr; +}DPP_NPPU_OAM_CFG_TXINFO_RAM_CLR_T; + +typedef struct dpp_nppu_oam_cfg_txinfo_ram_init_done_t +{ + ZXIC_UINT32 txinfo_ram_init_done; +}DPP_NPPU_OAM_CFG_TXINFO_RAM_INIT_DONE_T; + +typedef struct dpp_nppu_oam_cfg_fifo_status_int_status40_t +{ + ZXIC_UINT32 fifo_status_int_status40; +}DPP_NPPU_OAM_CFG_FIFO_STATUS_INT_STATUS40_T; + +typedef struct dpp_nppu_oam_cfg_fifo_status_int_status41_t +{ + ZXIC_UINT32 fifo_status_int_status41; +}DPP_NPPU_OAM_CFG_FIFO_STATUS_INT_STATUS41_T; + +typedef struct dpp_nppu_oam_cfg_oam_2544_fun_en_t +{ + ZXIC_UINT32 oam_2544_fun_en; +}DPP_NPPU_OAM_CFG_OAM_2544_FUN_EN_T; + +typedef struct dpp_nppu_oam_cfg_oam_2544_stat_clr_t +{ + ZXIC_UINT32 oam_2544_stat_clr; +}DPP_NPPU_OAM_CFG_OAM_2544_STAT_CLR_T; + +typedef struct dpp_nppu_oam_cfg_txdis_default_t +{ + ZXIC_UINT32 txdis_default; +}DPP_NPPU_OAM_CFG_TXDIS_DEFAULT_T; + +typedef struct dpp_nppu_oam_cfg_txdis_default_en_t +{ + ZXIC_UINT32 txdis_default_en; +}DPP_NPPU_OAM_CFG_TXDIS_DEFAULT_EN_T; + +typedef struct dpp_nppu_oam_cfg_tpbfd_firstchk_th_t +{ + ZXIC_UINT32 tpbfd_firstchk_th; +}DPP_NPPU_OAM_CFG_TPBFD_FIRSTCHK_TH_T; + +typedef struct dpp_nppu_oam_cfg_ethccm_firstchk_th_t +{ + ZXIC_UINT32 ethccm_firstchk_th; +}DPP_NPPU_OAM_CFG_ETHCCM_FIRSTCHK_TH_T; + +typedef struct dpp_nppu_oam_cfg_tpccm_firstchk_th_t +{ + ZXIC_UINT32 tpccm_firstchk_th; +}DPP_NPPU_OAM_CFG_TPCCM_FIRSTCHK_TH_T; + +typedef struct dpp_nppu_oam_stat_txstat_req_cnt_t +{ + ZXIC_UINT32 txstat_req_cnt; +}DPP_NPPU_OAM_STAT_TXSTAT_REQ_CNT_T; + +typedef struct dpp_nppu_oam_stat_chkstat_req_cnt_t +{ + ZXIC_UINT32 chkstat_req_cnt; +}DPP_NPPU_OAM_STAT_CHKSTAT_REQ_CNT_T; + +typedef struct dpp_nppu_oam_stat_stat_oam_fc_cnt_t +{ + ZXIC_UINT32 stat1_oam_fc_cnt; +}DPP_NPPU_OAM_STAT_STAT_OAM_FC_CNT_T; + +typedef struct dpp_nppu_oam_stat_bfdseq_req_cnt_t +{ + ZXIC_UINT32 bfdseq_req_cnt; +}DPP_NPPU_OAM_STAT_BFDSEQ_REQ_CNT_T; + +typedef struct dpp_nppu_oam_stat_lmcnt_req_cnt_t +{ + ZXIC_UINT32 lmcnt_req_cnt; +}DPP_NPPU_OAM_STAT_LMCNT_REQ_CNT_T; + +typedef struct dpp_nppu_oam_stat_stat_oam_lm_rsp_cnt_t +{ + ZXIC_UINT32 stat2_rsp_cnt; +}DPP_NPPU_OAM_STAT_STAT_OAM_LM_RSP_CNT_T; + +typedef struct dpp_nppu_oam_stat_stat_oam_lm_fc_cnt_t +{ + ZXIC_UINT32 stat2_oam_fc_cnt; +}DPP_NPPU_OAM_STAT_STAT_OAM_LM_FC_CNT_T; + +typedef struct dpp_nppu_oam_stat_se_req_cnt_t +{ + ZXIC_UINT32 se_req_cnt; +}DPP_NPPU_OAM_STAT_SE_REQ_CNT_T; + +typedef struct dpp_nppu_oam_stat_se_rsp_cnt_t +{ + ZXIC_UINT32 se_rsp_cnt; +}DPP_NPPU_OAM_STAT_SE_RSP_CNT_T; + +typedef struct dpp_nppu_oam_stat_se_oam_fc_cnt_t +{ + ZXIC_UINT32 se_oam_fc_cnt; +}DPP_NPPU_OAM_STAT_SE_OAM_FC_CNT_T; + +typedef struct dpp_nppu_oam_stat_oam_se_fc_cnt_t +{ + ZXIC_UINT32 oam_se_fc_cnt; +}DPP_NPPU_OAM_STAT_OAM_SE_FC_CNT_T; + +typedef struct dpp_nppu_oam_stat_oam_pktrx_sop_cnt_t +{ + ZXIC_UINT32 oam_pktrx_sop_cnt; +}DPP_NPPU_OAM_STAT_OAM_PKTRX_SOP_CNT_T; + +typedef struct dpp_nppu_oam_stat_oam_pktrx_eop_cnt_t +{ + ZXIC_UINT32 oam_pktrx_eop_cnt; +}DPP_NPPU_OAM_STAT_OAM_PKTRX_EOP_CNT_T; + +typedef struct dpp_nppu_oam_stat_pktrx_oam_fc_cnt_t +{ + ZXIC_UINT32 pktrx_oam_fc_cnt; +}DPP_NPPU_OAM_STAT_PKTRX_OAM_FC_CNT_T; + +typedef struct dpp_nppu_oam_stat_pktrx_oam_tst_fc_cnt_t +{ + ZXIC_UINT32 pktrx_oam_tst_fc_cnt; +}DPP_NPPU_OAM_STAT_PKTRX_OAM_TST_FC_CNT_T; + +typedef struct dpp_nppu_oam_stat_odma_oam_sop_cnt_t +{ + ZXIC_UINT32 odma_oam_sop_cnt; +}DPP_NPPU_OAM_STAT_ODMA_OAM_SOP_CNT_T; + +typedef struct dpp_nppu_oam_stat_odma_oam_eop_cnt_t +{ + ZXIC_UINT32 odma_oam_eop_cnt; +}DPP_NPPU_OAM_STAT_ODMA_OAM_EOP_CNT_T; + +typedef struct dpp_nppu_oam_stat_oam_odma_fc_cnt_t +{ + ZXIC_UINT32 oam_odma_fc_cnt; +}DPP_NPPU_OAM_STAT_OAM_ODMA_FC_CNT_T; + +typedef struct dpp_nppu_oam_stat_rec_ma_pkt_illegal_cnt_t +{ + ZXIC_UINT32 rec_ma_pkt_illegal_cnt; +}DPP_NPPU_OAM_STAT_REC_MA_PKT_ILLEGAL_CNT_T; + +typedef struct dpp_nppu_oam_stat_rec_rmep_pkt_illegal_cnt_t +{ + ZXIC_UINT32 rec_rmep_pkt_illegal_cnt; +}DPP_NPPU_OAM_STAT_REC_RMEP_PKT_ILLEGAL_CNT_T; + +typedef struct dpp_nppu_oam_stat_rec_eth_ais_pkt_cnt_t +{ + ZXIC_UINT32 rec_eth_ais_pkt_cnt; +}DPP_NPPU_OAM_STAT_REC_ETH_AIS_PKT_CNT_T; + +typedef struct dpp_nppu_oam_stat_rec_tp_ais_pkt_cnt_t +{ + ZXIC_UINT32 rec_tp_ais_pkt_cnt; +}DPP_NPPU_OAM_STAT_REC_TP_AIS_PKT_CNT_T; + +typedef struct dpp_nppu_oam_stat_rec_tp_csf_pkt_cnt_t +{ + ZXIC_UINT32 rec_tp_csf_pkt_cnt; +}DPP_NPPU_OAM_STAT_REC_TP_CSF_PKT_CNT_T; + +typedef struct dpp_nppu_oam_stat_rec_eth_level_defect_cnt_t +{ + ZXIC_UINT32 rec_eth_level_defect_cnt; +}DPP_NPPU_OAM_STAT_REC_ETH_LEVEL_DEFECT_CNT_T; + +typedef struct dpp_nppu_oam_stat_rec_eth_megid_defect_cnt_t +{ + ZXIC_UINT32 rec_eth_megid_defect_cnt; +}DPP_NPPU_OAM_STAT_REC_ETH_MEGID_DEFECT_CNT_T; + +typedef struct dpp_nppu_oam_stat_rec_eth_mepid_defect_cnt_t +{ + ZXIC_UINT32 rec_eth_mepid_defect_cnt; +}DPP_NPPU_OAM_STAT_REC_ETH_MEPID_DEFECT_CNT_T; + +typedef struct dpp_nppu_oam_stat_rec_eth_interval_defect_cnt_t +{ + ZXIC_UINT32 rec_eth_interval_defect_cnt; +}DPP_NPPU_OAM_STAT_REC_ETH_INTERVAL_DEFECT_CNT_T; + +typedef struct dpp_nppu_oam_stat_rec_sess_unenable_cnt_t +{ + ZXIC_UINT32 rec_sess_unenable_cnt; +}DPP_NPPU_OAM_STAT_REC_SESS_UNENABLE_CNT_T; + +typedef struct dpp_nppu_oam_stat_oam_2544_rd_pkt_cnt_t +{ + ZXIC_UINT32 oam_2544_rd_pkt_cnt; +}DPP_NPPU_OAM_STAT_OAM_2544_RD_PKT_CNT_T; + +typedef struct dpp_nppu_oam_stat_debug_cnt_clr_t +{ + ZXIC_UINT32 debug_cnt_clr; +}DPP_NPPU_OAM_STAT_DEBUG_CNT_CLR_T; + +typedef struct dpp_nppu_oam_stat_oam_pktrx_catch_data_t +{ + ZXIC_UINT32 oam_pktrx_catch_data; +}DPP_NPPU_OAM_STAT_OAM_PKTRX_CATCH_DATA_T; + +typedef struct dpp_nppu_oam_stat_odma_oam_catch_data_t +{ + ZXIC_UINT32 odma_oam_catch_data; +}DPP_NPPU_OAM_STAT_ODMA_OAM_CATCH_DATA_T; + +typedef struct dpp_nppu_oam_stat_tst_session_tx_cnt_t +{ + ZXIC_UINT32 tst_session_tx_cnt; +}DPP_NPPU_OAM_STAT_TST_SESSION_TX_CNT_T; + +typedef struct dpp_nppu_oam_stat_tst_session_rx_cnt_t +{ + ZXIC_UINT32 tst_session_rx_cnt; +}DPP_NPPU_OAM_STAT_TST_SESSION_RX_CNT_T; + +typedef struct dpp_nppu_oam_stat_tstrx_lost_cnt_t +{ + ZXIC_UINT32 tstrx_lost_cnt; +}DPP_NPPU_OAM_STAT_TSTRX_LOST_CNT_T; + +typedef struct dpp_nppu_oam_stat_bfdseq_wr_cnt_t +{ + ZXIC_UINT32 bfdseq_wr_cnt; +}DPP_NPPU_OAM_STAT_BFDSEQ_WR_CNT_T; + +typedef struct dpp_nppu_oam_stat_bfdtime_wr_cnt_t +{ + ZXIC_UINT32 bfdtime_wr_cnt; +}DPP_NPPU_OAM_STAT_BFDTIME_WR_CNT_T; + +typedef struct dpp_nppu_oam_stat_lmcnt_wr_cnt_t +{ + ZXIC_UINT32 lmcnt_wr_cnt; +}DPP_NPPU_OAM_STAT_LMCNT_WR_CNT_T; + +typedef struct dpp_nppu_oam_stat_oam_fs_pkt_cnt_t +{ + ZXIC_UINT32 oam_fs_pkt_cnt; +}DPP_NPPU_OAM_STAT_OAM_FS_PKT_CNT_T; + +typedef struct dpp_nppu_oam_stat_oam_ma_fs_pkt_cnt_t +{ + ZXIC_UINT32 lmcnt_wr_cnt; +}DPP_NPPU_OAM_STAT_OAM_MA_FS_PKT_CNT_T; + +typedef struct dpp_nppu_oam_stat_rec_tp_level_defect_cnt_t +{ + ZXIC_UINT32 rec_tp_level_defect_cnt; +}DPP_NPPU_OAM_STAT_REC_TP_LEVEL_DEFECT_CNT_T; + +typedef struct dpp_nppu_oam_stat_rec_tp_megid_defect_cnt_t +{ + ZXIC_UINT32 rec_tp_megid_defect_cnt; +}DPP_NPPU_OAM_STAT_REC_TP_MEGID_DEFECT_CNT_T; + +typedef struct dpp_nppu_oam_stat_rec_tp_mepid_defect_cnt_t +{ + ZXIC_UINT32 rec_tp_mepid_defect_cnt; +}DPP_NPPU_OAM_STAT_REC_TP_MEPID_DEFECT_CNT_T; + +typedef struct dpp_nppu_oam_stat_rec_tp_interval_defect_cnt_t +{ + ZXIC_UINT32 rec_tp_interval_defect_cnt; +}DPP_NPPU_OAM_STAT_REC_TP_INTERVAL_DEFECT_CNT_T; + +typedef struct dpp_nppu_oam_stat_rd_reg_clear_mode_t +{ + ZXIC_UINT32 rd_clear_mode_cfg; +}DPP_NPPU_OAM_STAT_RD_REG_CLEAR_MODE_T; + +typedef struct dpp_nppu_oam_stat_rd_data_reg_clear_mode_t +{ + ZXIC_UINT32 rd_data_reg_clear_mode_cfg; +}DPP_NPPU_OAM_STAT_RD_DATA_REG_CLEAR_MODE_T; + +typedef struct dpp_nppu_oam_cfg_indir_oam_int_status_ram_0_t +{ + ZXIC_UINT32 bfd_diag_value_bit4; + ZXIC_UINT32 bfd_diag_value_bit3; + ZXIC_UINT32 bfd_diag_value_bit2; + ZXIC_UINT32 bfd_diag_value_bit1; + ZXIC_UINT32 bfd_diag_value_bit0; + ZXIC_UINT32 dloc_int; + ZXIC_UINT32 drdi_int; +}DPP_NPPU_OAM_CFG_INDIR_OAM_INT_STATUS_RAM_0_T; + +typedef struct dpp_nppu_oam_cfg_indir_oam_int_status_ram1_t +{ + ZXIC_UINT32 sticky_error_level_defect; + ZXIC_UINT32 sticky_error_megid_defect; + ZXIC_UINT32 sticky_error_mepid_defect; + ZXIC_UINT32 sticky_error_inter_defect; + ZXIC_UINT32 sticky_ais_defect; + ZXIC_UINT32 sticky_csf_defect; + ZXIC_UINT32 current_error_level_defect; + ZXIC_UINT32 current_error_megid_defect; + ZXIC_UINT32 current_error_mepid_defect; + ZXIC_UINT32 current_error_inter_defect; + ZXIC_UINT32 current_ais_defect; + ZXIC_UINT32 current_csf_defect; +}DPP_NPPU_OAM_CFG_INDIR_OAM_INT_STATUS_RAM1_T; + +typedef struct dpp_nppu_oam_cfg_indir_tst_pkt_tx_para_ram_t +{ + ZXIC_UINT32 ddr_self_test_tx_en; + ZXIC_UINT32 tm_self_test_tx_en; + ZXIC_UINT32 fast_aging_tx_en; + ZXIC_UINT32 timing_aging_tx_en; + ZXIC_UINT32 backgroud_flow_tx_en; + ZXIC_UINT32 tsttx_session_en; + ZXIC_UINT32 tx_freq; + ZXIC_UINT32 tx_offset; + ZXIC_UINT32 tx_count; + ZXIC_UINT32 fast_tx_mode_en; + ZXIC_UINT32 tsttx_pkthead_len; + ZXIC_UINT32 tsttx_interval; +}DPP_NPPU_OAM_CFG_INDIR_TST_PKT_TX_PARA_RAM_T; + +typedef struct dpp_nppu_oam_cfg_indir_groupnumram_t +{ + ZXIC_UINT32 mep_down_num; +}DPP_NPPU_OAM_CFG_INDIR_GROUPNUMRAM_T; + +typedef struct dpp_nppu_oam_cfg_indir_oam_tx_tbl_ram_t +{ + ZXIC_UINT32 oam_tx_en; + ZXIC_UINT32 oam_tx_type; + ZXIC_UINT32 oam_fetch_len; + ZXIC_UINT32 bfd_seq_tx_en; + ZXIC_UINT32 tx_para; + ZXIC_UINT32 oam_tx_interval; + ZXIC_UINT32 hd_ena_flag; + ZXIC_UINT32 last_tx_time; +}DPP_NPPU_OAM_CFG_INDIR_OAM_TX_TBL_RAM_T; + +typedef struct dpp_nppu_oam_cfg_indir_oam_chk_tbl_ram_t +{ + ZXIC_UINT32 fast_switch_en; + ZXIC_UINT32 oam_chk_en; + ZXIC_UINT32 oam_chk_type; + ZXIC_UINT32 ccm_predel_flag; + ZXIC_UINT32 lm_chk_en; + ZXIC_UINT32 ccm_group_id; + ZXIC_UINT32 oam_chk_internal; + ZXIC_UINT32 fist_chk_flag; + ZXIC_UINT32 last_chk_time; +}DPP_NPPU_OAM_CFG_INDIR_OAM_CHK_TBL_RAM_T; + +typedef struct dpp_nppu_oam_cfg_indir_oam_ma_chk_tbl_ram_t +{ + ZXIC_UINT32 ma_fast_switch_en; + ZXIC_UINT32 ma_chk_en; + ZXIC_UINT32 ma_type; + ZXIC_UINT32 error_level_defect_en; + ZXIC_UINT32 error_megid_defect_en; + ZXIC_UINT32 error_mepid_defect_en; + ZXIC_UINT32 error_inter_defect_en; + ZXIC_UINT32 ais_defect_en; + ZXIC_UINT32 csf_defect_en; + ZXIC_UINT32 error_level_defect_ccm; + ZXIC_UINT32 error_megid_defect_ccm; + ZXIC_UINT32 error_mepid_defect_ccm; + ZXIC_UINT32 error_inter_defect_ccm; + ZXIC_UINT32 ais_defect_ccm; + ZXIC_UINT32 csf_defect_ccm; + ZXIC_UINT32 ma_predel_en; + ZXIC_UINT32 error_level_defect_ts; + ZXIC_UINT32 error_megid_defect_ts; + ZXIC_UINT32 error_mepid_defect_ts; + ZXIC_UINT32 error_inter_defect_ts; + ZXIC_UINT32 ais_defect_ts; + ZXIC_UINT32 csf_defect_ts; +}DPP_NPPU_OAM_CFG_INDIR_OAM_MA_CHK_TBL_RAM_T; + +typedef struct dpp_nppu_oam_cfg_indir_oam_2544_tx_ram_t +{ + ZXIC_UINT32 tx_en_2544; + ZXIC_UINT32 tx_cfg_times_2544; + ZXIC_UINT32 current_times; + ZXIC_UINT32 slice_num; + ZXIC_UINT32 pkt_mty; +}DPP_NPPU_OAM_CFG_INDIR_OAM_2544_TX_RAM_T; + + +#ifdef __cplusplus +} +#endif +#endif + diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_pci.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_pci.h new file mode 100755 index 0000000..7d8a027 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_pci.h @@ -0,0 +1,37 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_pci.h +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : 石金锋 +* 完成日期 : 2014/02/10 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: 代码规范性修改 +* 修改日期: 2014/02/10 +* 版 本 号: +* 修 改 人: 丁金凤 +* 修改内容: +***************************************************************/ + +#ifndef _DPP_PCI_H_ +#define _DPP_PCI_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "dpp_dev.h" +#include "dpp_module.h" + +ZXIC_UINT32 dpp_pci_write32(DPP_DEV_T *dev, ZXIC_ADDR_T abs_addr, ZXIC_UINT32 *p_data); +ZXIC_UINT32 dpp_pci_read32(DPP_DEV_T *dev, ZXIC_ADDR_T abs_addr, ZXIC_UINT32 *p_data); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_ppu4k_reg.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_ppu4k_reg.h new file mode 100644 index 0000000..468a042 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_ppu4k_reg.h @@ -0,0 +1,45 @@ + +#ifndef _DPP_PPU4K_REG_H_ +#define _DPP_PPU4K_REG_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +typedef struct dpp_ppu4k_cluster_wr_high_data_r_mex_t +{ + ZXIC_UINT32 wr_high_data_r_mex; +}DPP_PPU4K_CLUSTER_WR_HIGH_DATA_R_MEX_T; + +typedef struct dpp_ppu4k_cluster_wr_low_data_r_mex_t +{ + ZXIC_UINT32 wr_low_data_r_mex; +}DPP_PPU4K_CLUSTER_WR_LOW_DATA_R_MEX_T; + +typedef struct dpp_ppu4k_cluster_addr_r_mex_t +{ + ZXIC_UINT32 operate_type; + ZXIC_UINT32 addr_r_mex; +}DPP_PPU4K_CLUSTER_ADDR_R_MEX_T; + +typedef struct dpp_ppu4k_cluster_sdt_tbl_ind_access_done_t +{ + ZXIC_UINT32 rd_addr_r_mex; +}DPP_PPU4K_CLUSTER_SDT_TBL_IND_ACCESS_DONE_T; + +typedef struct dpp_ppu4k_cluster_rd_high_data_r_mex_t +{ + ZXIC_UINT32 rd_high_data_r_mex; +}DPP_PPU4K_CLUSTER_RD_HIGH_DATA_R_MEX_T; + +typedef struct dpp_ppu4k_cluster_rd_low_data_r_mex_t +{ + ZXIC_UINT32 rd_low_data_r_mex; +}DPP_PPU4K_CLUSTER_RD_LOW_DATA_R_MEX_T; + + +#ifdef __cplusplus +} +#endif +#endif + diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_ppu_reg.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_ppu_reg.h new file mode 100644 index 0000000..c604dc8 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_ppu_reg.h @@ -0,0 +1,4308 @@ + +#ifndef _DPP_PPU_REG_H_ +#define _DPP_PPU_REG_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +typedef struct dpp_ppu_ppu_test_r_t +{ + ZXIC_UINT32 test_r; +}DPP_PPU_PPU_TEST_R_T; + +typedef struct dpp_ppu_ppu_ppu_debug_en_r_t +{ + ZXIC_UINT32 debug_en_r; +}DPP_PPU_PPU_PPU_DEBUG_EN_R_T; + +typedef struct dpp_ppu_ppu_csr_dup_table_wr_data_t +{ + ZXIC_UINT32 item_vld; + ZXIC_UINT32 flownum_vld; + ZXIC_UINT32 start_pc; + ZXIC_UINT32 flownum; +}DPP_PPU_PPU_CSR_DUP_TABLE_WR_DATA_T; + +typedef struct dpp_ppu_ppu_csr_dup_table_rd_data_t +{ + ZXIC_UINT32 item_vld; + ZXIC_UINT32 flownum_vld; + ZXIC_UINT32 start_pc; + ZXIC_UINT32 flownum; +}DPP_PPU_PPU_CSR_DUP_TABLE_RD_DATA_T; + +typedef struct dpp_ppu_ppu_csr_dup_table_addr_t +{ + ZXIC_UINT32 csr_dup_table_operation; + ZXIC_UINT32 csr_dup_table_addr; +}DPP_PPU_PPU_CSR_DUP_TABLE_ADDR_T; + +typedef struct dpp_ppu_ppu_ppu_debug_vld_t +{ + ZXIC_UINT32 ppu_debug_vld; +}DPP_PPU_PPU_PPU_DEBUG_VLD_T; + +typedef struct dpp_ppu_ppu_cop_thash_rsk_319_288_t +{ + ZXIC_UINT32 rsk_319_288; +}DPP_PPU_PPU_COP_THASH_RSK_319_288_T; + +typedef struct dpp_ppu_ppu_cop_thash_rsk_287_256_t +{ + ZXIC_UINT32 rsk_287_256; +}DPP_PPU_PPU_COP_THASH_RSK_287_256_T; + +typedef struct dpp_ppu_ppu_cop_thash_rsk_255_224_t +{ + ZXIC_UINT32 rsk_255_224; +}DPP_PPU_PPU_COP_THASH_RSK_255_224_T; + +typedef struct dpp_ppu_ppu_cop_thash_rsk_223_192_t +{ + ZXIC_UINT32 rsk_223_192; +}DPP_PPU_PPU_COP_THASH_RSK_223_192_T; + +typedef struct dpp_ppu_ppu_cop_thash_rsk_191_160_t +{ + ZXIC_UINT32 rsk_191_160; +}DPP_PPU_PPU_COP_THASH_RSK_191_160_T; + +typedef struct dpp_ppu_ppu_cop_thash_rsk_159_128_t +{ + ZXIC_UINT32 rsk_159_128; +}DPP_PPU_PPU_COP_THASH_RSK_159_128_T; + +typedef struct dpp_ppu_ppu_cop_thash_rsk_127_096_t +{ + ZXIC_UINT32 rsk_127_096; +}DPP_PPU_PPU_COP_THASH_RSK_127_096_T; + +typedef struct dpp_ppu_ppu_cop_thash_rsk_095_064_t +{ + ZXIC_UINT32 rsk_095_064; +}DPP_PPU_PPU_COP_THASH_RSK_095_064_T; + +typedef struct dpp_ppu_ppu_cop_thash_rsk_063_032_t +{ + ZXIC_UINT32 rsk_063_032; +}DPP_PPU_PPU_COP_THASH_RSK_063_032_T; + +typedef struct dpp_ppu_ppu_cop_thash_rsk_031_000_t +{ + ZXIC_UINT32 rsk_031_000; +}DPP_PPU_PPU_COP_THASH_RSK_031_000_T; + +typedef struct dpp_ppu_ppu_cfg_ipv4_ipid_start_value_t +{ + ZXIC_UINT32 cfg_ipv4_ipid_start_value; +}DPP_PPU_PPU_CFG_IPV4_IPID_START_VALUE_T; + +typedef struct dpp_ppu_ppu_cfg_ipv4_ipid_end_value_t +{ + ZXIC_UINT32 cfg_ipv4_ipid_end_value; +}DPP_PPU_PPU_CFG_IPV4_IPID_END_VALUE_T; + +typedef struct dpp_ppu_ppu_cluster_mf_in_en_t +{ + ZXIC_UINT32 cluster_mf_in_en; +}DPP_PPU_PPU_CLUSTER_MF_IN_EN_T; + +typedef struct dpp_ppu_ppu_ppu_empty_t +{ + ZXIC_UINT32 ppu_empty; +}DPP_PPU_PPU_PPU_EMPTY_T; + +typedef struct dpp_ppu_ppu_instrmem_w_addr_t +{ + ZXIC_UINT32 instrmem_w_addr; +}DPP_PPU_PPU_INSTRMEM_W_ADDR_T; + +typedef struct dpp_ppu_ppu_instrmem_w_data_191_160_t +{ + ZXIC_UINT32 instrmem_w_data_191_160; +}DPP_PPU_PPU_INSTRMEM_W_DATA_191_160_T; + +typedef struct dpp_ppu_ppu_instrmem_w_data_159_128_t +{ + ZXIC_UINT32 instrmem_w_data_159_128; +}DPP_PPU_PPU_INSTRMEM_W_DATA_159_128_T; + +typedef struct dpp_ppu_ppu_instrmem_w_data_127_96_t +{ + ZXIC_UINT32 instrmem_w_data_127_96; +}DPP_PPU_PPU_INSTRMEM_W_DATA_127_96_T; + +typedef struct dpp_ppu_ppu_instrmem_w_data_95_64_t +{ + ZXIC_UINT32 instrmem_w_data_95_64; +}DPP_PPU_PPU_INSTRMEM_W_DATA_95_64_T; + +typedef struct dpp_ppu_ppu_instrmem_w_data_63_32_t +{ + ZXIC_UINT32 instrmem_w_data_63_32; +}DPP_PPU_PPU_INSTRMEM_W_DATA_63_32_T; + +typedef struct dpp_ppu_ppu_instrmem_w_data_31_0_t +{ + ZXIC_UINT32 instrmem_w_data_31_0; +}DPP_PPU_PPU_INSTRMEM_W_DATA_31_0_T; + +typedef struct dpp_ppu_ppu_isu_fwft_mf_fifo_prog_full_assert_cfg_t +{ + ZXIC_UINT32 isu_fwft_mf_fifo_prog_full_assert_cfg; +}DPP_PPU_PPU_ISU_FWFT_MF_FIFO_PROG_FULL_ASSERT_CFG_T; + +typedef struct dpp_ppu_ppu_isu_fwft_mf_fifo_prog_full_negate_cfg_t +{ + ZXIC_UINT32 isu_fwft_mf_fifo_prog_full_negate_cfg; +}DPP_PPU_PPU_ISU_FWFT_MF_FIFO_PROG_FULL_NEGATE_CFG_T; + +typedef struct dpp_ppu_cluster_int_1200m_mask_t +{ + ZXIC_UINT32 me7_interrupt_mask; + ZXIC_UINT32 me6_interrupt_mask; + ZXIC_UINT32 me5_interrupt_mask; + ZXIC_UINT32 me4_interrupt_mask; + ZXIC_UINT32 me3_interrupt_mask; + ZXIC_UINT32 me2_interrupt_mask; + ZXIC_UINT32 me1_interrupt_mask; + ZXIC_UINT32 me0_interrupt_mask; +}DPP_PPU_CLUSTER_INT_1200M_MASK_T; + +typedef struct dpp_ppu_ppu_interrupt_en_r_t +{ + ZXIC_UINT32 interrupt_en_r; +}DPP_PPU_PPU_INTERRUPT_EN_R_T; + +typedef struct dpp_ppu_ppu_mec_host_interrupt_t +{ + ZXIC_UINT32 mec_host_interrupt; +}DPP_PPU_PPU_MEC_HOST_INTERRUPT_T; + +typedef struct dpp_ppu_ppu_dbg_rtl_date_t +{ + ZXIC_UINT32 dbg_rtl_date; +}DPP_PPU_PPU_DBG_RTL_DATE_T; + +typedef struct dpp_ppu_ppu_dup_start_num_cfg_t +{ + ZXIC_UINT32 dup_start_num_cfg; +}DPP_PPU_PPU_DUP_START_NUM_CFG_T; + +typedef struct dpp_ppu_ppu_debug_data_write_complete_t +{ + ZXIC_UINT32 debug_data_write_complete; +}DPP_PPU_PPU_DEBUG_DATA_WRITE_COMPLETE_T; + +typedef struct dpp_ppu_ppu_uc_mc_wrr_cfg_t +{ + ZXIC_UINT32 uc_mc_wrr_cfg; +}DPP_PPU_PPU_UC_MC_WRR_CFG_T; + +typedef struct dpp_ppu_ppu_debug_pkt_send_en_t +{ + ZXIC_UINT32 debug_pkt_send_en; +}DPP_PPU_PPU_DEBUG_PKT_SEND_EN_T; + +typedef struct dpp_ppu_ppu_dup_tbl_ind_access_done_t +{ + ZXIC_UINT32 dup_tbl_ind_access_done; +}DPP_PPU_PPU_DUP_TBL_IND_ACCESS_DONE_T; + +typedef struct dpp_ppu_ppu_isu_ppu_demux_fifo_interrupt_mask_t +{ + ZXIC_UINT32 isu_in_para_fwft_fifo_32x81_wrapper_u0_overflow_mask; + ZXIC_UINT32 isu_in_para_fwft_fifo_32x81_wrapper_u0_underflow_mask; + ZXIC_UINT32 isu_in_fifo_64x81_wrapper_u0_overflow_mask; + ZXIC_UINT32 isu_in_fifo_64x81_wrapper_u0_underflow_mask; +}DPP_PPU_PPU_ISU_PPU_DEMUX_FIFO_INTERRUPT_MASK_T; + +typedef struct dpp_ppu_ppu_ppu_multicast_fifo_interrupt_mask_t +{ + ZXIC_UINT32 ppu_pktrx_mc_ptr_fifo_16384x17_wrapper_u0_underflow_mask; + ZXIC_UINT32 ppu_pktrx_mc_ptr_fifo_16384x17_wrapper_u0_overflow_mask; + ZXIC_UINT32 pf_req_fwft_fifo_16x36_wrapper_u0_overflow_mask; + ZXIC_UINT32 pf_req_fwft_fifo_16x36_wrapper_u0_underflow_mask; + ZXIC_UINT32 pf_rsp_fwft_fifo_32x34_wrapper_u0_overflow_mask; + ZXIC_UINT32 pf_rsp_fwft_fifo_32x34_wrapper_u0_underflow_mask; + ZXIC_UINT32 dup_para_fwft_fifo_16x35_wrapper_u0_overflow_mask; + ZXIC_UINT32 dup_para_fwft_fifo_16x35_wrapper_u0_underflow_mask; + ZXIC_UINT32 se_mc_rsp_fwft_fifo_32x17_wrapper_u0_overflow_mask; + ZXIC_UINT32 se_mc_rsp_fwft_fifo_32x17_wrapper_u0_underflow_mask; + ZXIC_UINT32 sa_para_fwft_fifo_64x17_wrapper_u0_overflow_mask; + ZXIC_UINT32 sa_para_fwft_fifo_64x17_wrapper_u0_underflow_mask; + ZXIC_UINT32 group_id_fifo_64x16_wrapper_u0_overflow_mask; + ZXIC_UINT32 group_id_fifo_64x16_wrapper_u0_underflow_mask; + ZXIC_UINT32 isu_mc_para_fwft_fifo_128x34_wrapper_u0_overflow_mask; + ZXIC_UINT32 isu_mc_para_fwft_fifo_128x34_wrapper_u0_underflow_mask; + ZXIC_UINT32 dup_freeptr_fwft_fifo_128x7_wrapper_u0_overflow_mask; + ZXIC_UINT32 dup_freeptr_fwft_fifo_128x7_wrapper_u0_underflow_mask; + ZXIC_UINT32 car_flag_fifo_32x1_wrapper_overflow_mask; + ZXIC_UINT32 car_flag_fifo_32x1_wrapper_underflow_mask; +}DPP_PPU_PPU_PPU_MULTICAST_FIFO_INTERRUPT_MASK_T; + +typedef struct dpp_ppu_ppu_ppu_in_schedule_fifo_interrupt_mask_t +{ + ZXIC_UINT32 free_global_num_fwft_fifo_8192x13_wrapper_u0_overflow_mask; + ZXIC_UINT32 free_global_num_fwft_fifo_8192x13_wrapper_u0_underflow_mask; + ZXIC_UINT32 mc_mf_fifo_16x2048_wrapper_u0_overflow_mask; + ZXIC_UINT32 mc_mf_fifo_16x2048_wrapper_u0_underflow_mask; + ZXIC_UINT32 uc_mf_fifo_96x2048_wrapper_u0_overflow_mask; + ZXIC_UINT32 uc_mf_fifo_96x2048_wrapper_u0_underflow_mask; +}DPP_PPU_PPU_PPU_IN_SCHEDULE_FIFO_INTERRUPT_MASK_T; + +typedef struct dpp_ppu_ppu_ppu_mf_out_fifo_interrupt_mask_t +{ + ZXIC_UINT32 ppu_cluster5_mf_out_afifo_32x2048_wrapper_overflow_mask; + ZXIC_UINT32 ppu_cluster5_mf_out_afifo_32x2048_wrapper_underflow_mask; + ZXIC_UINT32 ppu_cluster4_mf_out_afifo_32x2048_wrapper_overflow_mask; + ZXIC_UINT32 ppu_cluster4_mf_out_afifo_32x2048_wrapper_underflow_mask; + ZXIC_UINT32 ppu_cluster3_mf_out_afifo_32x2048_wrapper_overflow_mask; + ZXIC_UINT32 ppu_cluster3_mf_out_afifo_32x2048_wrapper_underflow_mask; + ZXIC_UINT32 ppu_cluster2_mf_out_afifo_32x2048_wrapper_overflow_mask; + ZXIC_UINT32 ppu_cluster2_mf_out_afifo_32x2048_wrapper_underflow_mask; + ZXIC_UINT32 ppu_cluster1_mf_out_afifo_32x2048_wrapper_overflow_mask; + ZXIC_UINT32 ppu_cluster1_mf_out_afifo_32x2048_wrapper_underflow_mask; + ZXIC_UINT32 ppu_cluster0_mf_out_afifo_32x2048_wrapper_overflow_mask; + ZXIC_UINT32 ppu_cluster0_mf_out_afifo_32x2048_wrapper_underflow_mask; +}DPP_PPU_PPU_PPU_MF_OUT_FIFO_INTERRUPT_MASK_T; + +typedef struct dpp_ppu_ppu_pbu_mcode_pf_req_schedule_fifo_interrupt_mask_t +{ + ZXIC_UINT32 ppu_cluster5_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_mask; + ZXIC_UINT32 ppu_cluster4_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_mask; + ZXIC_UINT32 ppu_cluster3_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_mask; + ZXIC_UINT32 ppu_cluster2_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_mask; + ZXIC_UINT32 ppu_cluster1_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_mask; + ZXIC_UINT32 ppu_cluster0_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_mask; + ZXIC_UINT32 ppu_cluster5_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_mask; + ZXIC_UINT32 ppu_cluster4_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_mask; + ZXIC_UINT32 ppu_cluster3_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_mask; + ZXIC_UINT32 ppu_cluster2_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_mask; + ZXIC_UINT32 ppu_cluster1_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_mask; + ZXIC_UINT32 ppu_cluster0_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_mask; +}DPP_PPU_PPU_PBU_MCODE_PF_REQ_SCHEDULE_FIFO_INTERRUPT_MASK_T; + +typedef struct dpp_ppu_ppu_pbu_mcode_pf_rsp_schedule_fifo_interrupt_mask_t +{ + ZXIC_UINT32 ppu_pbu_mcode_pf_rsp_afifo_64x16_wrapper_u0r_underflow_mask; + ZXIC_UINT32 ppu_pbu_mcode_pf_rsp_afifo_64x16_wrapper_u0_overflow_mask; +}DPP_PPU_PPU_PBU_MCODE_PF_RSP_SCHEDULE_FIFO_INTERRUPT_MASK_T; + +typedef struct dpp_ppu_ppu_ppu_mccnt_fifo_interrupt_mask_t +{ + ZXIC_UINT32 ppu_mccnt_fifo_32x15_wrapper_u0_overflow_mask; + ZXIC_UINT32 ppu_mccnt_fifo_32x15_wrapper_u0_underflow_mask; + ZXIC_UINT32 ppu_wb_data_fifo_32x2048_wrapper_u0_overflow_mask; + ZXIC_UINT32 ppu_wb_data_fifo_32x2048_wrapper_u0_underflow_mask; + ZXIC_UINT32 mccnt_rsp_fifo_32x1_wrapper_u0_overflow_mask; + ZXIC_UINT32 mccnt_rsp_fifo_32x1_wrapper_u0_underflow_mask; +}DPP_PPU_PPU_PPU_MCCNT_FIFO_INTERRUPT_MASK_T; + +typedef struct dpp_ppu_ppu_coprocessor_fifo_interrupt_mask_l_t +{ + ZXIC_UINT32 mec3_cop_key_crc_fifo_32x625_wrapper_overflow_flg_mask; + ZXIC_UINT32 mec3_cop_key_crc_fifo_32x625_wrapper_underflow_flg_mask; + ZXIC_UINT32 mec3_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_mask; + ZXIC_UINT32 mec3_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_mask; + ZXIC_UINT32 mec3_cop_key_mul_fifo_32x52_wrapper_overflow_flg_mask; + ZXIC_UINT32 mec3_cop_key_mul_fifo_32x52_wrapper_underflow_flg_mask; + ZXIC_UINT32 mec3_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_mask; + ZXIC_UINT32 mec3_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_mask; + ZXIC_UINT32 mec2_cop_key_crc_fifo_32x625_wrapper_overflow_flg_mask; + ZXIC_UINT32 mec2_cop_key_crc_fifo_32x625_wrapper_underflow_flg_mask; + ZXIC_UINT32 mec2_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_mask; + ZXIC_UINT32 mec2_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_mask; + ZXIC_UINT32 mec2_cop_key_mul_fifo_32x52_wrapper_overflow_flg_mask; + ZXIC_UINT32 mec2_cop_key_mul_fifo_32x52_wrapper_underflow_flg_mask; + ZXIC_UINT32 mec2_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_mask; + ZXIC_UINT32 mec2_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_mask; + ZXIC_UINT32 mec1_cop_key_crc_fifo_32x625_wrapper_overflow_flg_mask; + ZXIC_UINT32 mec1_cop_key_crc_fifo_32x625_wrapper_underflow_flg_mask; + ZXIC_UINT32 mec1_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_mask; + ZXIC_UINT32 mec1_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_mask; + ZXIC_UINT32 mec1_cop_key_mul_fifo_32x52_wrapper_overflow_flg_mask; + ZXIC_UINT32 mec1_cop_key_mul_fifo_32x52_wrapper_underflow_flg_mask; + ZXIC_UINT32 mec1_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_mask; + ZXIC_UINT32 mec1_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_mask; + ZXIC_UINT32 mec0_cop_key_crc_fifo_32x625_wrapper_overflow_flg_mask; + ZXIC_UINT32 mec0_cop_key_crc_fifo_32x625_wrapper_underflow_flg_mask; + ZXIC_UINT32 mec0_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_mask; + ZXIC_UINT32 mec0_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_mask; + ZXIC_UINT32 mec0_cop_key_mul_fifo_32x52_wrapper_overflow_flg_mask; + ZXIC_UINT32 mec0_cop_key_mul_fifo_32x52_wrapper_underflow_flg_mask; + ZXIC_UINT32 mec0_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_mask; + ZXIC_UINT32 mec0_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_mask; +}DPP_PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_MASK_L_T; + +typedef struct dpp_ppu_ppu_coprocessor_fifo_interrupt_mask_m_t +{ + ZXIC_UINT32 ppu_cop_result_fwft_fifo_80x80_wrapper_overflow_mask; + ZXIC_UINT32 ppu_cop_result_fwft_fifo_80x80_wrapper_underflow_mask; + ZXIC_UINT32 ppu_cop_delay_fifo_48x16_wrapper_overflow_mask; + ZXIC_UINT32 ppu_cop_delay_fifo_48x16_wrapper_underflow_mask; + ZXIC_UINT32 ppu_cop_delay_fifo_16x48_wrapper_overflow_mask; + ZXIC_UINT32 ppu_cop_delay_fifo_16x48_wrapper_underflow_mask; + ZXIC_UINT32 ppu_cop_delay_fifo_16x32_wrapper_overflow_mask; + ZXIC_UINT32 ppu_cop_delay_fifo_16x32_wrapper_underflow_mask; + ZXIC_UINT32 ppu_cop_result_fwft_fifo_96x80_wrapper_overflow_mask; + ZXIC_UINT32 ppu_cop_result_fwft_fifo_96x80_wrapper_underflow_mask; + ZXIC_UINT32 ppu_cop_delay_fifo_16x16_wrapper_overflow_mask; + ZXIC_UINT32 ppu_cop_delay_fifo_16x16_wrapper_underflow_mask; + ZXIC_UINT32 ppu_cop_result_fwft_fifo_32x80_wrapper_overflow_mask; + ZXIC_UINT32 ppu_cop_result_fwft_fifo_32x80_wrapper_underflow_mask; + ZXIC_UINT32 ppu_cop_result_fwft_fifo_16x80_wrapper_overflow_mask; + ZXIC_UINT32 ppu_cop_result_fwft_fifo_16x80_wrapper_underflow_mask; + ZXIC_UINT32 mec5_cop_key_crc_fifo_32x625_wrapper_overflow_flg_mask; + ZXIC_UINT32 mec5_cop_key_crc_fifo_32x625_wrapper_underflow_flg_mask; + ZXIC_UINT32 mec5_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_mask; + ZXIC_UINT32 mec5_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_mask; + ZXIC_UINT32 mec5_cop_key_mul_fifo_32x52_wrapper_overflow_flg_mask; + ZXIC_UINT32 mec5_cop_key_mul_fifo_32x52_wrapper_underflow_flg_mask; + ZXIC_UINT32 mec5_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_mask; + ZXIC_UINT32 mec5_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_mask; + ZXIC_UINT32 mec4_cop_key_crc_fifo_32x625_wrapper_overflow_flg_mask; + ZXIC_UINT32 mec4_cop_key_crc_fifo_32x625_wrapper_underflow_flg_mask; + ZXIC_UINT32 mec4_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_mask; + ZXIC_UINT32 mec4_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_mask; + ZXIC_UINT32 mec4_cop_key_mul_fifo_32x52_wrapper_overflow_flg_mask; + ZXIC_UINT32 mec4_cop_key_mul_fifo_32x52_wrapper_underflow_flg_mask; + ZXIC_UINT32 mec4_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_mask; + ZXIC_UINT32 mec4_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_mask; +}DPP_PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_MASK_M_T; + +typedef struct dpp_ppu_ppu_coprocessor_fifo_interrupt_mask_h_t +{ + ZXIC_UINT32 coprocessor_fwft_fifo_16x80_wrapper_overflow_mask; + ZXIC_UINT32 coprocessor_fwft_fifo_16x80_wrapper_underflow_mask; + ZXIC_UINT32 ppu_cop_random_mod_para_delay_fifo_48x16_wrapper_overflow_mask; + ZXIC_UINT32 ppu_cop_random_mod_para_delay_fifo_48x16_wrapper_underflow_mask; +}DPP_PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_MASK_H_T; + +typedef struct dpp_ppu_ppu_ppu_ram_check_err_mask_t +{ + ZXIC_UINT32 parity_err_mask; +}DPP_PPU_PPU_PPU_RAM_CHECK_ERR_MASK_T; + +typedef struct dpp_ppu_ppu_instrmem_fifo_interrupt_mask_t +{ + ZXIC_UINT32 instrmem2_wr_fifo_ovf_mask; + ZXIC_UINT32 instrmem2_wr_fifo_udf_mask; + ZXIC_UINT32 instrmem2_rd_fifo_ovf_mask; + ZXIC_UINT32 instrmem2_rd_fifo_udf_mask; + ZXIC_UINT32 instrmem1_wr_fifo_ovf_mask; + ZXIC_UINT32 instrmem1_wr_fifo_udf_mask; + ZXIC_UINT32 instrmem1_rd_fifo_ovf_mask; + ZXIC_UINT32 instrmem1_rd_fifo_udf_mask; + ZXIC_UINT32 instrmem0_wr_fifo_ovf_mask; + ZXIC_UINT32 instrmem0_wr_fifo_udf_mask; + ZXIC_UINT32 instrmem0_rd_fifo_ovf_mask; + ZXIC_UINT32 instrmem0_rd_fifo_udf_mask; +}DPP_PPU_PPU_INSTRMEM_FIFO_INTERRUPT_MASK_T; + +typedef struct dpp_ppu_ppu_isu_ppu_demux_fifo_interrupt_sta_t +{ + ZXIC_UINT32 isu_in_para_fwft_fifo_32x81_wrapper_u0_overflow_sta; + ZXIC_UINT32 isu_in_para_fwft_fifo_32x81_wrapper_u0_underflow_sta; + ZXIC_UINT32 isu_in_fifo_64x81_wrapper_u0_overflow_sta; + ZXIC_UINT32 isu_in_fifo_64x81_wrapper_u0_underflow_sta; +}DPP_PPU_PPU_ISU_PPU_DEMUX_FIFO_INTERRUPT_STA_T; + +typedef struct dpp_ppu_ppu_ppu_multicast_fifo_interrupt_sta_t +{ + ZXIC_UINT32 ppu_pktrx_mc_ptr_fifo_16384x17_wrapper_u0_overflow_sta; + ZXIC_UINT32 ppu_pktrx_mc_ptr_fifo_16384x17_wrapper_u0_underflow_sta; + ZXIC_UINT32 pf_req_fwft_fifo_16x36_wrapper_u0_overflow_sta; + ZXIC_UINT32 pf_req_fwft_fifo_16x36_wrapper_u0_underflow_sta; + ZXIC_UINT32 pf_rsp_fwft_fifo_32x34_wrapper_u0_overflow_sta; + ZXIC_UINT32 pf_rsp_fwft_fifo_32x34_wrapper_u0_underflow_sta; + ZXIC_UINT32 dup_para_fwft_fifo_16x35_wrapper_u0_overflow_sta; + ZXIC_UINT32 dup_para_fwft_fifo_16x35_wrapper_u0_underflow_sta; + ZXIC_UINT32 se_mc_rsp_fwft_fifo_32x17_wrapper_u0_overflow_sta; + ZXIC_UINT32 se_mc_rsp_fwft_fifo_32x17_wrapper_u0_underflow_sta; + ZXIC_UINT32 sa_para_fwft_fifo_64x17_wrapper_u0_overflow_sta; + ZXIC_UINT32 sa_para_fwft_fifo_64x17_wrapper_u0_underflow_sta; + ZXIC_UINT32 group_id_fifo_64x16_wrapper_u0_overflow_sta; + ZXIC_UINT32 group_id_fifo_64x16_wrapper_u0_underflow_sta; + ZXIC_UINT32 isu_mc_para_fwft_fifo_128x34_wrapper_u0_overflow_sta; + ZXIC_UINT32 isu_mc_para_fwft_fifo_128x34_wrapper_u0_underflow_sta; + ZXIC_UINT32 dup_freeptr_fwft_fifo_128x7_wrapper_u0_overflow_sta; + ZXIC_UINT32 dup_freeptr_fwft_fifo_128x7_wrapper_u0_underflow_sta; + ZXIC_UINT32 car_flag_fifo_32x1_wrapper_overflow_sta; + ZXIC_UINT32 car_flag_fifo_32x1_wrapper_underflow_sta; +}DPP_PPU_PPU_PPU_MULTICAST_FIFO_INTERRUPT_STA_T; + +typedef struct dpp_ppu_ppu_ppu_in_schedule_fifo_interrupt_sta_t +{ + ZXIC_UINT32 free_global_num_fwft_fifo_8192x13_wrapper_u0_overflow_sta; + ZXIC_UINT32 free_global_num_fwft_fifo_8192x13_wrapper_u0_underflow_sta; + ZXIC_UINT32 mc_mf_fifo_16x2048_wrapper_u0_overflow_sta; + ZXIC_UINT32 mc_mf_fifo_16x2048_wrapper_u0_underflow_sta; + ZXIC_UINT32 uc_mf_fifo_96x2048_wrapper_u0_overflow_sta; + ZXIC_UINT32 uc_mf_fifo_96x2048_wrapper_u0_underflow_sta; +}DPP_PPU_PPU_PPU_IN_SCHEDULE_FIFO_INTERRUPT_STA_T; + +typedef struct dpp_ppu_ppu_ppu_mf_out_fifo_interrupt_sta_t +{ + ZXIC_UINT32 ppu_cluster5_mf_out_afifo_32x2048_wrapper_overflow_sta; + ZXIC_UINT32 ppu_cluster5_mf_out_afifo_32x2048_wrapper_underflow_sta; + ZXIC_UINT32 ppu_cluster4_mf_out_afifo_32x2048_wrapper_overflow_sta; + ZXIC_UINT32 ppu_cluster4_mf_out_afifo_32x2048_wrapper_underflow_sta; + ZXIC_UINT32 ppu_cluster3_mf_out_afifo_32x2048_wrapper_overflow_sta; + ZXIC_UINT32 ppu_cluster3_mf_out_afifo_32x2048_wrapper_underflow_sta; + ZXIC_UINT32 ppu_cluster2_mf_out_afifo_32x2048_wrapper_overflow_sta; + ZXIC_UINT32 ppu_cluster2_mf_out_afifo_32x2048_wrapper_underflow_sta; + ZXIC_UINT32 ppu_cluster1_mf_out_afifo_32x2048_wrapper_overflow_sta; + ZXIC_UINT32 ppu_cluster1_mf_out_afifo_32x2048_wrapper_underflow_sta; + ZXIC_UINT32 ppu_cluster0_mf_out_afifo_32x2048_wrapper_overflow_sta; + ZXIC_UINT32 ppu_cluster0_mf_out_afifo_32x2048_wrapper_underflow_sta; +}DPP_PPU_PPU_PPU_MF_OUT_FIFO_INTERRUPT_STA_T; + +typedef struct dpp_ppu_ppu_pbu_mcode_pf_req_schedule_fifo_interrupt_sta_t +{ + ZXIC_UINT32 ppu_cluster5_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_sta; + ZXIC_UINT32 ppu_cluster4_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_sta; + ZXIC_UINT32 ppu_cluster3_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_sta; + ZXIC_UINT32 ppu_cluster2_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_sta; + ZXIC_UINT32 ppu_cluster1_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_sta; + ZXIC_UINT32 ppu_cluster0_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_sta; + ZXIC_UINT32 ppu_cluster5_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_sta; + ZXIC_UINT32 ppu_cluster4_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_sta; + ZXIC_UINT32 ppu_cluster3_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_sta; + ZXIC_UINT32 ppu_cluster2_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_sta; + ZXIC_UINT32 ppu_cluster1_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_sta; + ZXIC_UINT32 ppu_cluster0_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_sta; +}DPP_PPU_PPU_PBU_MCODE_PF_REQ_SCHEDULE_FIFO_INTERRUPT_STA_T; + +typedef struct dpp_ppu_ppu_pbu_mcode_pf_rsp_schedule_fifo_interrupt_sta_t +{ + ZXIC_UINT32 ppu_pbu_mcode_pf_rsp_afifo_64x16_wrapper_u0r_underflow_sta; + ZXIC_UINT32 ppu_pbu_mcode_pf_rsp_afifo_64x16_wrapper_u0_overflow_sta; +}DPP_PPU_PPU_PBU_MCODE_PF_RSP_SCHEDULE_FIFO_INTERRUPT_STA_T; + +typedef struct dpp_ppu_ppu_ppu_mccnt_fifo_interrupt_sta_t +{ + ZXIC_UINT32 ppu_mccnt_fifo_32x15_wrapper_u0_overflow_sta; + ZXIC_UINT32 ppu_mccnt_fifo_32x15_wrapper_u0_underflow_sta; + ZXIC_UINT32 ppu_wb_data_fifo_32x2048_wrapper_u0_overflow_sta; + ZXIC_UINT32 ppu_wb_data_fifo_32x2048_wrapper_u0_underflow_sta; + ZXIC_UINT32 mccnt_rsp_fifo_32x1_wrapper_u0_overflow_sta; + ZXIC_UINT32 mccnt_rsp_fifo_32x1_wrapper_u0_underflow_sta; +}DPP_PPU_PPU_PPU_MCCNT_FIFO_INTERRUPT_STA_T; + +typedef struct dpp_ppu_ppu_coprocessor_fifo_interrupt_sta_l_t +{ + ZXIC_UINT32 mec3_cop_key_crc_fifo_32x625_wrapper_overflow_flg_sta; + ZXIC_UINT32 mec3_cop_key_crc_fifo_32x625_wrapper_underflow_flg_sta; + ZXIC_UINT32 mec3_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_sta; + ZXIC_UINT32 mec3_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_sta; + ZXIC_UINT32 mec3_cop_key_mul_fifo_32x52_wrapper_overflow_flg_sta; + ZXIC_UINT32 mec3_cop_key_mul_fifo_32x52_wrapper_underflow_flg_sta; + ZXIC_UINT32 mec3_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_sta; + ZXIC_UINT32 mec3_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_sta; + ZXIC_UINT32 mec2_cop_key_crc_fifo_32x625_wrapper_overflow_flg_sta; + ZXIC_UINT32 mec2_cop_key_crc_fifo_32x625_wrapper_underflow_flg_sta; + ZXIC_UINT32 mec2_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_sta; + ZXIC_UINT32 mec2_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_sta; + ZXIC_UINT32 mec2_cop_key_mul_fifo_32x52_wrapper_overflow_flg_sta; + ZXIC_UINT32 mec2_cop_key_mul_fifo_32x52_wrapper_underflow_flg_sta; + ZXIC_UINT32 mec2_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_sta; + ZXIC_UINT32 mec2_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_sta; + ZXIC_UINT32 mec1_cop_key_crc_fifo_32x625_wrapper_overflow_flg_sta; + ZXIC_UINT32 mec1_cop_key_crc_fifo_32x625_wrapper_underflow_flg_sta; + ZXIC_UINT32 mec1_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_sta; + ZXIC_UINT32 mec1_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_sta; + ZXIC_UINT32 mec1_cop_key_mul_fifo_32x52_wrapper_overflow_flg_sta; + ZXIC_UINT32 mec1_cop_key_mul_fifo_32x52_wrapper_underflow_flg_sta; + ZXIC_UINT32 mec1_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_sta; + ZXIC_UINT32 mec1_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_sta; + ZXIC_UINT32 mec0_cop_key_crc_fifo_32x625_wrapper_overflow_flg_sta; + ZXIC_UINT32 mec0_cop_key_crc_fifo_32x625_wrapper_underflow_flg_sta; + ZXIC_UINT32 mec0_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_sta; + ZXIC_UINT32 mec0_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_sta; + ZXIC_UINT32 mec0_cop_key_mul_fifo_32x52_wrapper_overflow_flg_sta; + ZXIC_UINT32 mec0_cop_key_mul_fifo_32x52_wrapper_underflow_flg_sta; + ZXIC_UINT32 mec0_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_sta; + ZXIC_UINT32 mec0_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_sta; +}DPP_PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_STA_L_T; + +typedef struct dpp_ppu_ppu_coprocessor_fifo_interrupt_sta_m_t +{ + ZXIC_UINT32 ppu_cop_result_fwft_fifo_80x80_wrapper_overflow_sta; + ZXIC_UINT32 ppu_cop_result_fwft_fifo_80x80_wrapper_underflow_sta; + ZXIC_UINT32 ppu_cop_delay_fifo_48x16_wrapper_overflow_sta; + ZXIC_UINT32 ppu_cop_delay_fifo_48x16_wrapper_underflow_sta; + ZXIC_UINT32 ppu_cop_delay_fifo_16x48_wrapper_overflow_sta; + ZXIC_UINT32 ppu_cop_delay_fifo_16x48_wrapper_underflow_sta; + ZXIC_UINT32 ppu_cop_delay_fifo_16x32_wrapper_overflow_sta; + ZXIC_UINT32 ppu_cop_delay_fifo_16x32_wrapper_underflow_sta; + ZXIC_UINT32 ppu_cop_result_fwft_fifo_96x80_wrapper_overflow_sta; + ZXIC_UINT32 ppu_cop_result_fwft_fifo_96x80_wrapper_underflow_sta; + ZXIC_UINT32 ppu_cop_delay_fifo_16x16_wrapper_overflow_sta; + ZXIC_UINT32 ppu_cop_delay_fifo_16x16_wrapper_underflow_sta; + ZXIC_UINT32 ppu_cop_result_fwft_fifo_32x80_wrapper_overflow_sta; + ZXIC_UINT32 ppu_cop_result_fwft_fifo_32x80_wrapper_underflow_sta; + ZXIC_UINT32 ppu_cop_result_fwft_fifo_16x80_wrapper_overflow_sta; + ZXIC_UINT32 ppu_cop_result_fwft_fifo_16x80_wrapper_underflow_sta; + ZXIC_UINT32 mec5_cop_key_crc_fifo_32x625_wrapper_overflow_flg_sta; + ZXIC_UINT32 mec5_cop_key_crc_fifo_32x625_wrapper_underflow_flg_sta; + ZXIC_UINT32 mec5_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_sta; + ZXIC_UINT32 mec5_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_sta; + ZXIC_UINT32 mec5_cop_key_mul_fifo_32x52_wrapper_overflow_flg_sta; + ZXIC_UINT32 mec5_cop_key_mul_fifo_32x52_wrapper_underflow_flg_sta; + ZXIC_UINT32 mec5_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_sta; + ZXIC_UINT32 mec5_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_sta; + ZXIC_UINT32 mec4_cop_key_crc_fifo_32x625_wrapper_overflow_flg_sta; + ZXIC_UINT32 mec4_cop_key_crc_fifo_32x625_wrapper_underflow_flg_sta; + ZXIC_UINT32 mec4_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_sta; + ZXIC_UINT32 mec4_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_sta; + ZXIC_UINT32 mec4_cop_key_mul_fifo_32x52_wrapper_overflow_flg_sta; + ZXIC_UINT32 mec4_cop_key_mul_fifo_32x52_wrapper_underflow_flg_sta; + ZXIC_UINT32 mec4_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_sta; + ZXIC_UINT32 mec4_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_sta; +}DPP_PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_STA_M_T; + +typedef struct dpp_ppu_ppu_coprocessor_fifo_interrupt_sta_h_t +{ + ZXIC_UINT32 ppu_cop_random_mod_para_delay_fifo_48x16_wrapper_overflow_sta; + ZXIC_UINT32 ppu_cop_random_mod_para_delay_fifo_48x16_wrapper_underflow_sta; +}DPP_PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_STA_H_T; + +typedef struct dpp_ppu_ppu_instrmem_fifo_interrupt_sta_t +{ + ZXIC_UINT32 instrmem1_wr_fifo_ovf_sta; + ZXIC_UINT32 instrmem1_wr_fifo_udf_sta; + ZXIC_UINT32 instrmem1_rd_fifo_ovf_sta; + ZXIC_UINT32 instrmem1_rd_fifo_udf_sta; + ZXIC_UINT32 instrmem0_wr_fifo_ovf_sta; + ZXIC_UINT32 instrmem0_wr_fifo_udf_sta; + ZXIC_UINT32 instrmem0_rd_fifo_ovf_sta; + ZXIC_UINT32 instrmem0_rd_fifo_udf_sta; +}DPP_PPU_PPU_INSTRMEM_FIFO_INTERRUPT_STA_T; + +typedef struct dpp_ppu_ppu_ppu_ram_check_ecc_err_flag_1_t +{ + ZXIC_UINT32 ecc_single_err_sa_para_fifo_int_flag; + ZXIC_UINT32 ecc_double_err_sa_para_fifo_int_flag; + ZXIC_UINT32 ecc_single_err_dup_para_fifo_int_flag; + ZXIC_UINT32 ecc_double_err_dup_para_fifo_int_flag; + ZXIC_UINT32 ecc_single_err_pf_rsp_fifo_int_flag; + ZXIC_UINT32 ecc_double_err_pf_rsp_fifo_int_flag; + ZXIC_UINT32 ecc_single_err_pf_req_fifo_int_flag; + ZXIC_UINT32 ecc_double_err_pf_req_fifo_int_flag; + ZXIC_UINT32 ecc_single_err_ppu_reorder_link_ram0_int_flag; + ZXIC_UINT32 ecc_double_err_ppu_reorder_link_ram0_int_flag; + ZXIC_UINT32 ecc_single_err_ppu_reorder_link_ram1_int_flag; + ZXIC_UINT32 ecc_double_err_ppu_reorder_link_ram1_int_flag; + ZXIC_UINT32 ecc_single_err_ppu_reorder_link_flag_array_ram0_int_flag; + ZXIC_UINT32 ecc_single_err_ppu_reorder_link_flag_array_ram1_int_flag; + ZXIC_UINT32 ecc_single_err_ppu_reorder_ifb_ram_int_flag; + ZXIC_UINT32 ecc_double_err_ppu_reorder_ifb_ram_int_flag; + ZXIC_UINT32 ecc_single_err_ppu_reorder_flag_array_ram0_int_flag; + ZXIC_UINT32 ecc_single_err_ppu_reorder_flag_array_ram1_int_flag; + ZXIC_UINT32 ecc_single_err_ppu_reorder_flag_ram0_int_flag; + ZXIC_UINT32 ecc_single_err_ppu_reorder_flag_ram1_int_flag; + ZXIC_UINT32 ecc_single_err_uc_mf_fifo_int_flag; + ZXIC_UINT32 ecc_double_err_uc_mf_fifo_int_flag; + ZXIC_UINT32 ecc_single_err_mc_mf_fifo_int_flag; + ZXIC_UINT32 ecc_double_err_mc_mf_fifo_int_flag; + ZXIC_UINT32 ecc_single_err_free_global_num_fifo_int_flag; + ZXIC_UINT32 ecc_double_err_free_global_num_fifo_int_flag; +}DPP_PPU_PPU_PPU_RAM_CHECK_ECC_ERR_FLAG_1_T; + +typedef struct dpp_ppu_ppu_isu_ppu_demux_fifo_interrupt_flag_t +{ + ZXIC_UINT32 isu_in_para_fwft_fifo_32x81_wrapper_u0_overflow_flag; + ZXIC_UINT32 isu_in_para_fwft_fifo_32x81_wrapper_u0_underflow_flag; + ZXIC_UINT32 isu_in_fifo_64x81_wrapper_u0_overflow_flag; + ZXIC_UINT32 isu_in_fifo_64x81_wrapper_u0_underflow_flag; +}DPP_PPU_PPU_ISU_PPU_DEMUX_FIFO_INTERRUPT_FLAG_T; + +typedef struct dpp_ppu_ppu_ppu_multicast_fifo_interrupt_flag_t +{ + ZXIC_UINT32 ppu_pktrx_mc_ptr_fifo_16384x17_wrapper_u0_overflow_flag; + ZXIC_UINT32 ppu_pktrx_mc_ptr_fifo_16384x17_wrapper_u0_underflow_flag; + ZXIC_UINT32 pf_req_fwft_fifo_16x36_wrapper_u0_overflow_flag; + ZXIC_UINT32 pf_req_fwft_fifo_16x36_wrapper_u0_underflow_flag; + ZXIC_UINT32 pf_rsp_fwft_fifo_32x34_wrapper_u0_overflow_flag; + ZXIC_UINT32 pf_rsp_fwft_fifo_32x34_wrapper_u0_underflow_flag; + ZXIC_UINT32 dup_para_fwft_fifo_16x35_wrapper_u0_overflow_flag; + ZXIC_UINT32 dup_para_fwft_fifo_16x35_wrapper_u0_underflow_flag; + ZXIC_UINT32 se_mc_rsp_fwft_fifo_32x17_wrapper_u0_overflow_flag; + ZXIC_UINT32 se_mc_rsp_fwft_fifo_32x17_wrapper_u0_underflow_flag; + ZXIC_UINT32 sa_para_fwft_fifo_64x17_wrapper_u0_overflow_flag; + ZXIC_UINT32 sa_para_fwft_fifo_64x17_wrapper_u0_underflow_flag; + ZXIC_UINT32 group_id_fifo_64x16_wrapper_u0_overflow_flag; + ZXIC_UINT32 group_id_fifo_64x16_wrapper_u0_underflow_flag; + ZXIC_UINT32 isu_mc_para_fwft_fifo_128x34_wrapper_u0_overflow_flag; + ZXIC_UINT32 isu_mc_para_fwft_fifo_128x34_wrapper_u0_underflow_flag; + ZXIC_UINT32 dup_freeptr_fwft_fifo_128x7_wrapper_u0_overflow_flag; + ZXIC_UINT32 dup_freeptr_fwft_fifo_128x7_wrapper_u0_underflow_flag; + ZXIC_UINT32 car_flag_fifo_32x1_wrapper_overflow_flag; + ZXIC_UINT32 car_flag_fifo_32x1_wrapper_underflow_flag; +}DPP_PPU_PPU_PPU_MULTICAST_FIFO_INTERRUPT_FLAG_T; + +typedef struct dpp_ppu_ppu_ppu_in_schedule_fifo_interrupt_flag_t +{ + ZXIC_UINT32 free_global_num_fwft_fifo_8192x13_wrapper_u0_overflow_flag; + ZXIC_UINT32 free_global_num_fwft_fifo_8192x13_wrapper_u0_underflow_flag; + ZXIC_UINT32 mc_mf_fifo_16x2048_wrapper_u0_overflow_flag; + ZXIC_UINT32 mc_mf_fifo_16x2048_wrapper_u0_underflow_flag; + ZXIC_UINT32 uc_mf_fifo_96x2048_wrapper_u0_overflow_flag; + ZXIC_UINT32 uc_mf_fifo_96x2048_wrapper_u0_underflow_flag; +}DPP_PPU_PPU_PPU_IN_SCHEDULE_FIFO_INTERRUPT_FLAG_T; + +typedef struct dpp_ppu_ppu_ppu_mf_out_fifo_interrupt_flag_t +{ + ZXIC_UINT32 ppu_cluster5_mf_out_afifo_32x2048_wrapper_overflow_flag; + ZXIC_UINT32 ppu_cluster5_mf_out_afifo_32x2048_wrapper_underflow_flag; + ZXIC_UINT32 ppu_cluster4_mf_out_afifo_32x2048_wrapper_overflow_flag; + ZXIC_UINT32 ppu_cluster4_mf_out_afifo_32x2048_wrapper_underflow_flag; + ZXIC_UINT32 ppu_cluster3_mf_out_afifo_32x2048_wrapper_overflow_flag; + ZXIC_UINT32 ppu_cluster3_mf_out_afifo_32x2048_wrapper_underflow_flag; + ZXIC_UINT32 ppu_cluster2_mf_out_afifo_32x2048_wrapper_overflow_flag; + ZXIC_UINT32 ppu_cluster2_mf_out_afifo_32x2048_wrapper_underflow_flag; + ZXIC_UINT32 ppu_cluster1_mf_out_afifo_32x2048_wrapper_overflow_flag; + ZXIC_UINT32 ppu_cluster1_mf_out_afifo_32x2048_wrapper_underflow_flag; + ZXIC_UINT32 ppu_cluster0_mf_out_afifo_32x2048_wrapper_overflow_flag; + ZXIC_UINT32 ppu_cluster0_mf_out_afifo_32x2048_wrapper_underflow_flag; +}DPP_PPU_PPU_PPU_MF_OUT_FIFO_INTERRUPT_FLAG_T; + +typedef struct dpp_ppu_ppu_pbu_mcode_pf_req_schedule_fifo_interrupt_flag_t +{ + ZXIC_UINT32 ppu_cluster5_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_flag; + ZXIC_UINT32 ppu_cluster4_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_flag; + ZXIC_UINT32 ppu_cluster3_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_flag; + ZXIC_UINT32 ppu_cluster2_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_flag; + ZXIC_UINT32 ppu_cluster1_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_flag; + ZXIC_UINT32 ppu_cluster0_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_flag; + ZXIC_UINT32 ppu_cluster5_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_flag; + ZXIC_UINT32 ppu_cluster4_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_flag; + ZXIC_UINT32 ppu_cluster3_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_flag; + ZXIC_UINT32 ppu_cluster2_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_flag; + ZXIC_UINT32 ppu_cluster1_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_flag; + ZXIC_UINT32 ppu_cluster0_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_flag; +}DPP_PPU_PPU_PBU_MCODE_PF_REQ_SCHEDULE_FIFO_INTERRUPT_FLAG_T; + +typedef struct dpp_ppu_ppu_pbu_mcode_pf_rsp_schedule_fifo_interrupt_flag_t +{ + ZXIC_UINT32 ppu_pbu_mcode_pf_rsp_afifo_64x16_wrapper_u0r_underflow_flag; + ZXIC_UINT32 ppu_pbu_mcode_pf_rsp_afifo_64x16_wrapper_u0_overflow_flag; +}DPP_PPU_PPU_PBU_MCODE_PF_RSP_SCHEDULE_FIFO_INTERRUPT_FLAG_T; + +typedef struct dpp_ppu_ppu_ppu_mccnt_fifo_interrupt_flag_t +{ + ZXIC_UINT32 ppu_mccnt_fifo_32x15_wrapper_u0_overflow_flag; + ZXIC_UINT32 ppu_mccnt_fifo_32x15_wrapper_u0_underflow_flag; + ZXIC_UINT32 ppu_wb_data_fifo_32x2048_wrapper_u0_overflow_flag; + ZXIC_UINT32 ppu_wb_data_fifo_32x2048_wrapper_u0_underflow_flag; + ZXIC_UINT32 mccnt_rsp_fifo_32x1_wrapper_u0_overflow_flag; + ZXIC_UINT32 mccnt_rsp_fifo_32x1_wrapper_u0_underflow_flag; +}DPP_PPU_PPU_PPU_MCCNT_FIFO_INTERRUPT_FLAG_T; + +typedef struct dpp_ppu_ppu_coprocessor_fifo_interrupt_flag_l_t +{ + ZXIC_UINT32 mec3_cop_key_crc_fifo_32x625_wrapper_overflow_flag; + ZXIC_UINT32 mec3_cop_key_crc_fifo_32x625_wrapper_underflow_flag; + ZXIC_UINT32 mec3_cop_key_checksum_fifo_32x180_wrapper_overflow_flag; + ZXIC_UINT32 mec3_cop_key_checksum_fifo_32x180_wrapper_underflow_flag; + ZXIC_UINT32 mec3_cop_key_mul_fifo_32x52_wrapper_overflow_flag; + ZXIC_UINT32 mec3_cop_key_mul_fifo_32x52_wrapper_underflow_flag; + ZXIC_UINT32 mec3_cop_key_random_mod_fifo_32x44_wrapper_overflow_flag; + ZXIC_UINT32 mec3_cop_key_random_mod_fifo_32x44_wrapper_underflow_flag; + ZXIC_UINT32 mec2_cop_key_crc_fifo_32x625_wrapper_overflow_flag; + ZXIC_UINT32 mec2_cop_key_crc_fifo_32x625_wrapper_underflow_flag; + ZXIC_UINT32 mec2_cop_key_checksum_fifo_32x180_wrapper_overflow_flag; + ZXIC_UINT32 mec2_cop_key_checksum_fifo_32x180_wrapper_underflow_flag; + ZXIC_UINT32 mec2_cop_key_mul_fifo_32x52_wrapper_overflow_flag; + ZXIC_UINT32 mec2_cop_key_mul_fifo_32x52_wrapper_underflow_flag; + ZXIC_UINT32 mec2_cop_key_random_mod_fifo_32x44_wrapper_overflow_flag; + ZXIC_UINT32 mec2_cop_key_random_mod_fifo_32x44_wrapper_underflow_flag; + ZXIC_UINT32 mec1_cop_key_crc_fifo_32x625_wrapper_overflow_flag; + ZXIC_UINT32 mec1_cop_key_crc_fifo_32x625_wrapper_underflow_flag; + ZXIC_UINT32 mec1_cop_key_checksum_fifo_32x180_wrapper_overflow_flag; + ZXIC_UINT32 mec1_cop_key_checksum_fifo_32x180_wrapper_underflow_flag; + ZXIC_UINT32 mec1_cop_key_mul_fifo_32x52_wrapper_overflow_flag; + ZXIC_UINT32 mec1_cop_key_mul_fifo_32x52_wrapper_underflow_flag; + ZXIC_UINT32 mec1_cop_key_random_mod_fifo_32x44_wrapper_overflow_flag; + ZXIC_UINT32 mec1_cop_key_random_mod_fifo_32x44_wrapper_underflow_flag; + ZXIC_UINT32 mec0_cop_key_crc_fifo_32x625_wrapper_overflow_flag; + ZXIC_UINT32 mec0_cop_key_crc_fifo_32x625_wrapper_underflow_flag; + ZXIC_UINT32 mec0_cop_key_checksum_fifo_32x180_wrapper_overflow_flag; + ZXIC_UINT32 mec0_cop_key_checksum_fifo_32x180_wrapper_underflow_flag; + ZXIC_UINT32 mec0_cop_key_mul_fifo_32x52_wrapper_overflow_flag; + ZXIC_UINT32 mec0_cop_key_mul_fifo_32x52_wrapper_underflow_flag; + ZXIC_UINT32 mec0_cop_key_random_mod_fifo_32x44_wrapper_overflow_flag; + ZXIC_UINT32 mec0_cop_key_random_mod_fifo_32x44_wrapper_underflow_flag; +}DPP_PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_FLAG_L_T; + +typedef struct dpp_ppu_ppu_coprocessor_fifo_interrupt_flag_m_t +{ + ZXIC_UINT32 ppu_cop_result_fwft_fifo_80x80_wrapper_overflow_flag; + ZXIC_UINT32 ppu_cop_result_fwft_fifo_80x80_wrapper_underflow_flag; + ZXIC_UINT32 ppu_cop_delay_fifo_48x16_wrapper_overflow_flag; + ZXIC_UINT32 ppu_cop_delay_fifo_48x16_wrapper_underflow_flag; + ZXIC_UINT32 ppu_cop_delay_fifo_16x48_wrapper_overflow_flag; + ZXIC_UINT32 ppu_cop_delay_fifo_16x48_wrapper_underflow_flag; + ZXIC_UINT32 ppu_cop_delay_fifo_16x32_wrapper_overflow_flag; + ZXIC_UINT32 ppu_cop_delay_fifo_16x32_wrapper_underflow_flag; + ZXIC_UINT32 ppu_cop_result_fwft_fifo_96x80_wrapper_overflow_flag; + ZXIC_UINT32 ppu_cop_result_fwft_fifo_96x80_wrapper_underflow_flag; + ZXIC_UINT32 ppu_cop_delay_fifo_16x16_wrapper_overflow_flag; + ZXIC_UINT32 ppu_cop_delay_fifo_16x16_wrapper_underflow_flag; + ZXIC_UINT32 ppu_cop_result_fwft_fifo_32x80_wrapper_overflow_flag; + ZXIC_UINT32 ppu_cop_result_fwft_fifo_32x80_wrapper_underflow_flag; + ZXIC_UINT32 ppu_cop_result_fwft_fifo_16x80_wrapper_overflow_flag; + ZXIC_UINT32 ppu_cop_result_fwft_fifo_16x80_wrapper_underflow_flag; + ZXIC_UINT32 mec5_cop_key_crc_fifo_32x625_wrapper_overflow_flag; + ZXIC_UINT32 mec5_cop_key_crc_fifo_32x625_wrapper_underflow_flag; + ZXIC_UINT32 mec5_cop_key_checksum_fifo_32x180_wrapper_overflow_flag; + ZXIC_UINT32 mec5_cop_key_checksum_fifo_32x180_wrapper_underflow_flag; + ZXIC_UINT32 mec5_cop_key_mul_fifo_32x52_wrapper_overflow_flag; + ZXIC_UINT32 mec5_cop_key_mul_fifo_32x52_wrapper_underflow_flag; + ZXIC_UINT32 mec5_cop_key_random_mod_fifo_32x44_wrapper_overflow_flag; + ZXIC_UINT32 mec5_cop_key_random_mod_fifo_32x44_wrapper_underflow_flag; + ZXIC_UINT32 mec4_cop_key_crc_fifo_32x625_wrapper_overflow_flag; + ZXIC_UINT32 mec4_cop_key_crc_fifo_32x625_wrapper_underflow_flag; + ZXIC_UINT32 mec4_cop_key_checksum_fifo_32x180_wrapper_overflow_flag; + ZXIC_UINT32 mec4_cop_key_checksum_fifo_32x180_wrapper_underflow_flag; + ZXIC_UINT32 mec4_cop_key_mul_fifo_32x52_wrapper_overflow_flag; + ZXIC_UINT32 mec4_cop_key_mul_fifo_32x52_wrapper_underflow_flag; + ZXIC_UINT32 mec4_cop_key_random_mod_fifo_32x44_wrapper_overflow_flag; + ZXIC_UINT32 mec4_cop_key_random_mod_fifo_32x44_wrapper_underflow_flag; +}DPP_PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_FLAG_M_T; + +typedef struct dpp_ppu_ppu_coprocessor_fifo_interrupt_flag_h_t +{ + ZXIC_UINT32 ppu_cop_random_mod_para_delay_fifo_48x16_wrapper_overflow_flag; + ZXIC_UINT32 ppu_cop_random_mod_para_delay_fifo_48x16_wrapper_underflow_flag; +}DPP_PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_FLAG_H_T; + +typedef struct dpp_ppu_ppu_instrmem_fifo_interrupt_flag_t +{ + ZXIC_UINT32 instrmem2_wr_fifo_ovf_flag; + ZXIC_UINT32 instrmem2_wr_fifo_udf_flag; + ZXIC_UINT32 instrmem2_rd_fifo_ovf_flag; + ZXIC_UINT32 instrmem2_rd_fifo_udf_flag; + ZXIC_UINT32 instrmem1_wr_fifo_ovf_flag; + ZXIC_UINT32 instrmem1_wr_fifo_udf_flag; + ZXIC_UINT32 instrmem1_rd_fifo_ovf_flag; + ZXIC_UINT32 instrmem1_rd_fifo_udf_flag; + ZXIC_UINT32 instrmem0_wr_fifo_ovf_flag; + ZXIC_UINT32 instrmem0_wr_fifo_udf_flag; + ZXIC_UINT32 instrmem0_rd_fifo_ovf_flag; + ZXIC_UINT32 instrmem0_rd_fifo_udf_flag; +}DPP_PPU_PPU_INSTRMEM_FIFO_INTERRUPT_FLAG_T; + +typedef struct dpp_ppu_ppu_instrmem_ram_int_out_t +{ + ZXIC_UINT32 instrmem2_bank3_ram_parity_err_int_out; + ZXIC_UINT32 instrmem2_bank2_ram_parity_err_int_out; + ZXIC_UINT32 instrmem2_bank1_ram_parity_err_int_out; + ZXIC_UINT32 instrmem2_bank0_ram_parity_err_int_out; + ZXIC_UINT32 instrmem1_bank3_ram_parity_err_int_out; + ZXIC_UINT32 instrmem1_bank2_ram_parity_err_int_out; + ZXIC_UINT32 instrmem1_bank1_ram_parity_err_int_out; + ZXIC_UINT32 instrmem1_bank0_ram_parity_err_int_out; + ZXIC_UINT32 instrmem0_bank3_ram_parity_err_int_out; + ZXIC_UINT32 instrmem0_bank2_ram_parity_err_int_out; + ZXIC_UINT32 instrmem0_bank1_ram_parity_err_int_out; + ZXIC_UINT32 instrmem0_bank0_ram_parity_err_int_out; +}DPP_PPU_PPU_INSTRMEM_RAM_INT_OUT_T; + +typedef struct dpp_ppu_ppu_instrmem_ram_int_mask_t +{ + ZXIC_UINT32 instrmem2_bank3_ram_parity_err_mask; + ZXIC_UINT32 instrmem2_bank2_ram_parity_err_mask; + ZXIC_UINT32 instrmem2_bank1_ram_parity_err_mask; + ZXIC_UINT32 instrmem2_bank0_ram_parity_err_mask; + ZXIC_UINT32 instrmem1_bank3_ram_parity_err_mask; + ZXIC_UINT32 instrmem1_bank2_ram_parity_err_mask; + ZXIC_UINT32 instrmem1_bank1_ram_parity_err_mask; + ZXIC_UINT32 instrmem1_bank0_ram_parity_err_mask; + ZXIC_UINT32 instrmem0_bank3_ram_parity_err_mask; + ZXIC_UINT32 instrmem0_bank2_ram_parity_err_mask; + ZXIC_UINT32 instrmem0_bank1_ram_parity_err_mask; + ZXIC_UINT32 instrmem0_bank0_ram_parity_err_mask; +}DPP_PPU_PPU_INSTRMEM_RAM_INT_MASK_T; + +typedef struct dpp_ppu_ppu_instrmem_ram_int_stat_t +{ + ZXIC_UINT32 instrmem2_bank3_ram_parity_errstat; + ZXIC_UINT32 instrmem2_bank2_ram_parity_errstat; + ZXIC_UINT32 instrmem2_bank1_ram_parity_errstat; + ZXIC_UINT32 instrmem2_bank0_ram_parity_errstat; + ZXIC_UINT32 instrmem1_bank3_ram_parity_errstat; + ZXIC_UINT32 instrmem1_bank2_ram_parity_errstat; + ZXIC_UINT32 instrmem1_bank1_ram_parity_errstat; + ZXIC_UINT32 instrmem1_bank0_ram_parity_errstat; + ZXIC_UINT32 instrmem0_bank3_ram_parity_errstat; + ZXIC_UINT32 instrmem0_bank2_ram_parity_errstat; + ZXIC_UINT32 instrmem0_bank1_ram_parity_errstat; + ZXIC_UINT32 instrmem0_bank0_ram_parity_errstat; +}DPP_PPU_PPU_INSTRMEM_RAM_INT_STAT_T; + +typedef struct dpp_ppu_ppu_instrmem_ram_int_flag_t +{ + ZXIC_UINT32 instrmem2_bank3_ram_parity_err_flag; + ZXIC_UINT32 instrmem2_bank2_ram_parity_err_flag; + ZXIC_UINT32 instrmem2_bank1_ram_parity_err_flag; + ZXIC_UINT32 instrmem2_bank0_ram_parity_err_flag; + ZXIC_UINT32 instrmem1_bank3_ram_parity_err_flag; + ZXIC_UINT32 instrmem1_bank2_ram_parity_err_flag; + ZXIC_UINT32 instrmem1_bank1_ram_parity_err_flag; + ZXIC_UINT32 instrmem1_bank0_ram_parity_err_flag; + ZXIC_UINT32 instrmem0_bank3_ram_parity_err_flag; + ZXIC_UINT32 instrmem0_bank2_ram_parity_err_flag; + ZXIC_UINT32 instrmem0_bank1_ram_parity_err_flag; + ZXIC_UINT32 instrmem0_bank0_ram_parity_err_flag; +}DPP_PPU_PPU_INSTRMEM_RAM_INT_FLAG_T; + +typedef struct dpp_ppu_ppu_ppu_count_cfg_t +{ + ZXIC_UINT32 ppu_count_overflow_mode; + ZXIC_UINT32 ppu_count_rd_mode; +}DPP_PPU_PPU_PPU_COUNT_CFG_T; + +typedef struct dpp_ppu_ppu_ppu_statics_cfg_t +{ + ZXIC_UINT32 csr_statics_mc_type; + ZXIC_UINT32 csr_statics_bufnum; + ZXIC_UINT32 csr_statics_portnum1; + ZXIC_UINT32 csr_statics_portnum0; +}DPP_PPU_PPU_PPU_STATICS_CFG_T; + +typedef struct dpp_ppu_ppu_ppu_statics_wb_cfg_t +{ + ZXIC_UINT32 csr_statics_wb_halt_send_type; + ZXIC_UINT32 csr_statics_wb_mf_type; + ZXIC_UINT32 csr_statics_wb_halt_continue_end; + ZXIC_UINT32 csr_statics_wb_dup_flag; + ZXIC_UINT32 csr_statics_wb_last_flag; + ZXIC_UINT32 csr_statics_wb_dis_flag; +}DPP_PPU_PPU_PPU_STATICS_WB_CFG_T; + +typedef struct dpp_ppu_ppu_wr_table_self_rsp_en_cfg_t +{ + ZXIC_UINT32 wr_table_self_rsp_en_cfg; +}DPP_PPU_PPU_WR_TABLE_SELF_RSP_EN_CFG_T; + +typedef struct dpp_ppu_ppu_ppu_random_arbiter_8to1_cfg_t +{ + ZXIC_UINT32 ppu_random_arbiter_8to1_cfg; +}DPP_PPU_PPU_PPU_RANDOM_ARBITER_8TO1_CFG_T; + +typedef struct dpp_ppu_ppu_ppu_reorder_bypass_flow_num_cfg_t +{ + ZXIC_UINT32 ppu_reorder_bypass_flow_num_cfg; +}DPP_PPU_PPU_PPU_REORDER_BYPASS_FLOW_NUM_CFG_T; + +typedef struct dpp_ppu_ppu_cos_meter_cfg_h_t +{ + ZXIC_UINT32 cbs; + ZXIC_UINT32 pbs; + ZXIC_UINT32 green_action; + ZXIC_UINT32 yellow_action; + ZXIC_UINT32 red_action; +}DPP_PPU_PPU_COS_METER_CFG_H_T; + +typedef struct dpp_ppu_ppu_cos_meter_cfg_l_t +{ + ZXIC_UINT32 cir; + ZXIC_UINT32 pir; + ZXIC_UINT32 car_en; +}DPP_PPU_PPU_COS_METER_CFG_L_T; + +typedef struct dpp_ppu_ppu_instrmem_rdy_t +{ + ZXIC_UINT32 instrmem_rdy; +}DPP_PPU_PPU_INSTRMEM_RDY_T; + +typedef struct dpp_ppu_ppu_instrmem_addr_t +{ + ZXIC_UINT32 instrmem_operate; + ZXIC_UINT32 instrmem_addr; +}DPP_PPU_PPU_INSTRMEM_ADDR_T; + +typedef struct dpp_ppu_ppu_instrmem_ind_access_done_t +{ + ZXIC_UINT32 instrmem_ind_access_done; +}DPP_PPU_PPU_INSTRMEM_IND_ACCESS_DONE_T; + +typedef struct dpp_ppu_ppu_instrmem_instr0_data_l_t +{ + ZXIC_UINT32 instrmem_instr0_data_l; +}DPP_PPU_PPU_INSTRMEM_INSTR0_DATA_L_T; + +typedef struct dpp_ppu_ppu_instrmem_instr0_data_h_t +{ + ZXIC_UINT32 instrmem_instr0_data_h; +}DPP_PPU_PPU_INSTRMEM_INSTR0_DATA_H_T; + +typedef struct dpp_ppu_ppu_instrmem_instr1_data_l_t +{ + ZXIC_UINT32 instrmem_instr1_data_l; +}DPP_PPU_PPU_INSTRMEM_INSTR1_DATA_L_T; + +typedef struct dpp_ppu_ppu_instrmem_instr1_data_h_t +{ + ZXIC_UINT32 instrmem_instr1_data_h; +}DPP_PPU_PPU_INSTRMEM_INSTR1_DATA_H_T; + +typedef struct dpp_ppu_ppu_instrmem_instr2_data_l_t +{ + ZXIC_UINT32 instrmem_instr2_data_l; +}DPP_PPU_PPU_INSTRMEM_INSTR2_DATA_L_T; + +typedef struct dpp_ppu_ppu_instrmem_instr2_data_h_t +{ + ZXIC_UINT32 instrmem_instr2_data_h; +}DPP_PPU_PPU_INSTRMEM_INSTR2_DATA_H_T; + +typedef struct dpp_ppu_ppu_instrmem_instr3_data_l_t +{ + ZXIC_UINT32 instrmem_instr3_data_l; +}DPP_PPU_PPU_INSTRMEM_INSTR3_DATA_L_T; + +typedef struct dpp_ppu_ppu_instrmem_instr3_data_h_t +{ + ZXIC_UINT32 instrmem_instr3_data_h; +}DPP_PPU_PPU_INSTRMEM_INSTR3_DATA_H_T; + +typedef struct dpp_ppu_ppu_instrmem_read_instr0_data_l_t +{ + ZXIC_UINT32 instrmem_read_instr0_data_l; +}DPP_PPU_PPU_INSTRMEM_READ_INSTR0_DATA_L_T; + +typedef struct dpp_ppu_ppu_instrmem_read_instr0_data_h_t +{ + ZXIC_UINT32 instrmem_read_instr0_data_h; +}DPP_PPU_PPU_INSTRMEM_READ_INSTR0_DATA_H_T; + +typedef struct dpp_ppu_ppu_instrmem_read_instr1_data_l_t +{ + ZXIC_UINT32 instrmem_read_instr1_data_l; +}DPP_PPU_PPU_INSTRMEM_READ_INSTR1_DATA_L_T; + +typedef struct dpp_ppu_ppu_instrmem_read_instr1_data_h_t +{ + ZXIC_UINT32 instrmem_read_instr1_data_h; +}DPP_PPU_PPU_INSTRMEM_READ_INSTR1_DATA_H_T; + +typedef struct dpp_ppu_ppu_instrmem_read_instr2_data_l_t +{ + ZXIC_UINT32 instrmem_read_instr2_data_l; +}DPP_PPU_PPU_INSTRMEM_READ_INSTR2_DATA_L_T; + +typedef struct dpp_ppu_ppu_instrmem_read_instr2_data_h_t +{ + ZXIC_UINT32 instrmem_read_instr2_data_h; +}DPP_PPU_PPU_INSTRMEM_READ_INSTR2_DATA_H_T; + +typedef struct dpp_ppu_ppu_instrmem_read_instr3_data_l_t +{ + ZXIC_UINT32 instrmem_read_instr3_data_l; +}DPP_PPU_PPU_INSTRMEM_READ_INSTR3_DATA_L_T; + +typedef struct dpp_ppu_ppu_instrmem_read_instr3_data_h_t +{ + ZXIC_UINT32 instrmem_read_instr3_data_h; +}DPP_PPU_PPU_INSTRMEM_READ_INSTR3_DATA_H_T; + +typedef struct dpp_ppu_ppu_se_ppu_mc_srh_fc_cnt_h_t +{ + ZXIC_UINT32 se_ppu_mc_srh_fc_cnt_h; +}DPP_PPU_PPU_SE_PPU_MC_SRH_FC_CNT_H_T; + +typedef struct dpp_ppu_ppu_se_ppu_mc_srh_fc_cnt_l_t +{ + ZXIC_UINT32 se_ppu_mc_srh_fc_cnt_l; +}DPP_PPU_PPU_SE_PPU_MC_SRH_FC_CNT_L_T; + +typedef struct dpp_ppu_ppu_ppu_se_mc_srh_fc_cnt_h_t +{ + ZXIC_UINT32 ppu_se_mc_srh_fc_cnt_h; +}DPP_PPU_PPU_PPU_SE_MC_SRH_FC_CNT_H_T; + +typedef struct dpp_ppu_ppu_ppu_se_mc_srh_fc_cnt_l_t +{ + ZXIC_UINT32 ppu_se_mc_srh_fc_cnt_l; +}DPP_PPU_PPU_PPU_SE_MC_SRH_FC_CNT_L_T; + +typedef struct dpp_ppu_ppu_ppu_se_mc_srh_vld_cnt_h_t +{ + ZXIC_UINT32 ppu_se_mc_srh_vld_cnt_h; +}DPP_PPU_PPU_PPU_SE_MC_SRH_VLD_CNT_H_T; + +typedef struct dpp_ppu_ppu_ppu_se_mc_srh_vld_cnt_l_t +{ + ZXIC_UINT32 ppu_se_mc_srh_vld_cnt_l; +}DPP_PPU_PPU_PPU_SE_MC_SRH_VLD_CNT_L_T; + +typedef struct dpp_ppu_ppu_se_ppu_mc_srh_vld_cnt_h_t +{ + ZXIC_UINT32 se_ppu_mc_srh_vld_cnt_h; +}DPP_PPU_PPU_SE_PPU_MC_SRH_VLD_CNT_H_T; + +typedef struct dpp_ppu_ppu_se_ppu_mc_srh_vld_cnt_l_t +{ + ZXIC_UINT32 se_ppu_mc_srh_vld_cnt_l; +}DPP_PPU_PPU_SE_PPU_MC_SRH_VLD_CNT_L_T; + +typedef struct dpp_ppu_ppu_pbu_ppu_logic_pf_fc_cnt_h_t +{ + ZXIC_UINT32 pbu_ppu_logic_pf_fc_cnt_h; +}DPP_PPU_PPU_PBU_PPU_LOGIC_PF_FC_CNT_H_T; + +typedef struct dpp_ppu_ppu_pbu_ppu_logic_pf_fc_cnt_l_t +{ + ZXIC_UINT32 pbu_ppu_logic_pf_fc_cnt_l; +}DPP_PPU_PPU_PBU_PPU_LOGIC_PF_FC_CNT_L_T; + +typedef struct dpp_ppu_ppu_ppu_pbu_logic_rsp_fc_cnt_h_t +{ + ZXIC_UINT32 ppu_pbu_logic_rsp_fc_cnt_h; +}DPP_PPU_PPU_PPU_PBU_LOGIC_RSP_FC_CNT_H_T; + +typedef struct dpp_ppu_ppu_ppu_pbu_logic_rsp_fc_cnt_l_t +{ + ZXIC_UINT32 ppu_pbu_logic_rsp_fc_cnt_l; +}DPP_PPU_PPU_PPU_PBU_LOGIC_RSP_FC_CNT_L_T; + +typedef struct dpp_ppu_ppu_ppu_pbu_logic_pf_req_vld_cnt_h_t +{ + ZXIC_UINT32 ppu_pbu_logic_pf_req_vld_cnt_h; +}DPP_PPU_PPU_PPU_PBU_LOGIC_PF_REQ_VLD_CNT_H_T; + +typedef struct dpp_ppu_ppu_ppu_pbu_logic_pf_req_vld_cnt_l_t +{ + ZXIC_UINT32 ppu_pbu_logic_pf_req_vld_cnt_l; +}DPP_PPU_PPU_PPU_PBU_LOGIC_PF_REQ_VLD_CNT_L_T; + +typedef struct dpp_ppu_ppu_pbu_ppu_logic_pf_rsp_vld_cnt_h_t +{ + ZXIC_UINT32 pbu_ppu_logic_pf_rsp_vld_cnt_h; +}DPP_PPU_PPU_PBU_PPU_LOGIC_PF_RSP_VLD_CNT_H_T; + +typedef struct dpp_ppu_ppu_pbu_ppu_logic_pf_rsp_vld_cnt_l_t +{ + ZXIC_UINT32 pbu_ppu_logic_pf_rsp_vld_cnt_l; +}DPP_PPU_PPU_PBU_PPU_LOGIC_PF_RSP_VLD_CNT_L_T; + +typedef struct dpp_ppu_ppu_pbu_ppu_ifb_rd_fc_cnt_h_t +{ + ZXIC_UINT32 pbu_ppu_ifb_rd_fc_cnt_h; +}DPP_PPU_PPU_PBU_PPU_IFB_RD_FC_CNT_H_T; + +typedef struct dpp_ppu_ppu_pbu_ppu_ifb_rd_fc_cnt_l_t +{ + ZXIC_UINT32 pbu_ppu_ifb_rd_fc_cnt_l; +}DPP_PPU_PPU_PBU_PPU_IFB_RD_FC_CNT_L_T; + +typedef struct dpp_ppu_ppu_pbu_ppu_wb_fc_cnt_h_t +{ + ZXIC_UINT32 pbu_ppu_wb_fc_cnt_h; +}DPP_PPU_PPU_PBU_PPU_WB_FC_CNT_H_T; + +typedef struct dpp_ppu_ppu_pbu_ppu_wb_fc_cnt_l_t +{ + ZXIC_UINT32 pbu_ppu_wb_fc_cnt_l; +}DPP_PPU_PPU_PBU_PPU_WB_FC_CNT_L_T; + +typedef struct dpp_ppu_ppu_ppu_pbu_mcode_pf_req_vld_cnt_h_t +{ + ZXIC_UINT32 ppu_pbu_mcode_pf_req_vld_cnt_h; +}DPP_PPU_PPU_PPU_PBU_MCODE_PF_REQ_VLD_CNT_H_T; + +typedef struct dpp_ppu_ppu_ppu_pbu_mcode_pf_req_vld_cnt_l_t +{ + ZXIC_UINT32 ppu_pbu_mcode_pf_req_vld_cnt_l; +}DPP_PPU_PPU_PPU_PBU_MCODE_PF_REQ_VLD_CNT_L_T; + +typedef struct dpp_ppu_ppu_pbu_ppu_mcode_pf_rsp_vld_cnt_h_t +{ + ZXIC_UINT32 pbu_ppu_mcode_pf_rsp_vld_cnt_h; +}DPP_PPU_PPU_PBU_PPU_MCODE_PF_RSP_VLD_CNT_H_T; + +typedef struct dpp_ppu_ppu_pbu_ppu_mcode_pf_rsp_vld_cnt_l_t +{ + ZXIC_UINT32 pbu_ppu_mcode_pf_rsp_vld_cnt_l; +}DPP_PPU_PPU_PBU_PPU_MCODE_PF_RSP_VLD_CNT_L_T; + +typedef struct dpp_ppu_ppu_odma_ppu_para_fc_cnt_h_t +{ + ZXIC_UINT32 odma_ppu_para_fc_cnt_h; +}DPP_PPU_PPU_ODMA_PPU_PARA_FC_CNT_H_T; + +typedef struct dpp_ppu_ppu_odma_ppu_para_fc_cnt_l_t +{ + ZXIC_UINT32 odma_ppu_para_fc_cnt_l; +}DPP_PPU_PPU_ODMA_PPU_PARA_FC_CNT_L_T; + +typedef struct dpp_ppu_ppu_odma_ppu_mccnt_wr_fc_cnt_h_t +{ + ZXIC_UINT32 odma_ppu_mccnt_wr_fc_cnt_h; +}DPP_PPU_PPU_ODMA_PPU_MCCNT_WR_FC_CNT_H_T; + +typedef struct dpp_ppu_ppu_odma_ppu_mccnt_wr_fc_cnt_l_t +{ + ZXIC_UINT32 odma_ppu_mccnt_wr_fc_cnt_l; +}DPP_PPU_PPU_ODMA_PPU_MCCNT_WR_FC_CNT_L_T; + +typedef struct dpp_ppu_ppu_ppu_odma_mccnt_wr_vld_cnt_h_t +{ + ZXIC_UINT32 ppu_odma_mccnt_wr_vld_cnt_h; +}DPP_PPU_PPU_PPU_ODMA_MCCNT_WR_VLD_CNT_H_T; + +typedef struct dpp_ppu_ppu_ppu_odma_mccnt_wr_vld_cnt_l_t +{ + ZXIC_UINT32 ppu_odma_mccnt_wr_vld_cnt_l; +}DPP_PPU_PPU_PPU_ODMA_MCCNT_WR_VLD_CNT_L_T; + +typedef struct dpp_ppu_ppu_odma_ppu_mccnt_rsp_vld_cnt_h_t +{ + ZXIC_UINT32 odma_ppu_mccnt_rsp_vld_cnt_h; +}DPP_PPU_PPU_ODMA_PPU_MCCNT_RSP_VLD_CNT_H_T; + +typedef struct dpp_ppu_ppu_odma_ppu_mccnt_rsp_vld_cnt_l_t +{ + ZXIC_UINT32 odma_ppu_mccnt_rsp_vld_cnt_l; +}DPP_PPU_PPU_ODMA_PPU_MCCNT_RSP_VLD_CNT_L_T; + +typedef struct dpp_ppu_ppu_ppu_pktrx_uc_fc_cnt_h_t +{ + ZXIC_UINT32 ppu_pktrx_uc_fc_cnt_h; +}DPP_PPU_PPU_PPU_PKTRX_UC_FC_CNT_H_T; + +typedef struct dpp_ppu_ppu_ppu_pktrx_uc_fc_cnt_l_t +{ + ZXIC_UINT32 ppu_pktrx_uc_fc_cnt_l; +}DPP_PPU_PPU_PPU_PKTRX_UC_FC_CNT_L_T; + +typedef struct dpp_ppu_ppu_ppu_pktrx_mc_fc_cnt_h_t +{ + ZXIC_UINT32 ppu_pktrx_mc_fc_cnt_h; +}DPP_PPU_PPU_PPU_PKTRX_MC_FC_CNT_H_T; + +typedef struct dpp_ppu_ppu_ppu_pktrx_mc_fc_cnt_l_t +{ + ZXIC_UINT32 ppu_pktrx_mc_fc_cnt_l; +}DPP_PPU_PPU_PPU_PKTRX_MC_FC_CNT_L_T; + +typedef struct dpp_ppu_ppu_pktrx_ppu_desc_vld_cnt_h_t +{ + ZXIC_UINT32 pktrx_ppu_desc_vld_cnt_h; +}DPP_PPU_PPU_PKTRX_PPU_DESC_VLD_CNT_H_T; + +typedef struct dpp_ppu_ppu_pktrx_ppu_desc_vld_cnt_l_t +{ + ZXIC_UINT32 pktrx_ppu_desc_vld_cnt_l; +}DPP_PPU_PPU_PKTRX_PPU_DESC_VLD_CNT_L_T; + +typedef struct dpp_ppu_ppu_ppu_pbu_ifb_req_vld_cnt_h_t +{ + ZXIC_UINT32 ppu_pbu_ifb_req_vld_cnt_h; +}DPP_PPU_PPU_PPU_PBU_IFB_REQ_VLD_CNT_H_T; + +typedef struct dpp_ppu_ppu_ppu_pbu_ifb_req_vld_cnt_l_t +{ + ZXIC_UINT32 ppu_pbu_ifb_req_vld_cnt_l; +}DPP_PPU_PPU_PPU_PBU_IFB_REQ_VLD_CNT_L_T; + +typedef struct dpp_ppu_ppu_pbu_ppu_ifb_rsp_vld_cnt_h_t +{ + ZXIC_UINT32 pbu_ppu_ifb_rsp_vld_cnt_h; +}DPP_PPU_PPU_PBU_PPU_IFB_RSP_VLD_CNT_H_T; + +typedef struct dpp_ppu_ppu_pbu_ppu_ifb_rsp_vld_cnt_l_t +{ + ZXIC_UINT32 pbu_ppu_ifb_rsp_vld_cnt_l; +}DPP_PPU_PPU_PBU_PPU_IFB_RSP_VLD_CNT_L_T; + +typedef struct dpp_ppu_ppu_ppu_pbu_wb_vld_cnt_h_t +{ + ZXIC_UINT32 ppu_pbu_wb_vld_cnt_h; +}DPP_PPU_PPU_PPU_PBU_WB_VLD_CNT_H_T; + +typedef struct dpp_ppu_ppu_ppu_pbu_wb_vld_cnt_l_t +{ + ZXIC_UINT32 ppu_pbu_wb_vld_cnt_l; +}DPP_PPU_PPU_PPU_PBU_WB_VLD_CNT_L_T; + +typedef struct dpp_ppu_ppu_pbu_ppu_reorder_para_vld_cnt_h_t +{ + ZXIC_UINT32 pbu_ppu_reorder_para_vld_cnt_h; +}DPP_PPU_PPU_PBU_PPU_REORDER_PARA_VLD_CNT_H_T; + +typedef struct dpp_ppu_ppu_pbu_ppu_reorder_para_vld_cnt_l_t +{ + ZXIC_UINT32 pbu_ppu_reorder_para_vld_cnt_l; +}DPP_PPU_PPU_PBU_PPU_REORDER_PARA_VLD_CNT_L_T; + +typedef struct dpp_ppu_ppu_ppu_odma_para_vld_cnt_h_t +{ + ZXIC_UINT32 ppu_odma_para_vld_cnt_h; +}DPP_PPU_PPU_PPU_ODMA_PARA_VLD_CNT_H_T; + +typedef struct dpp_ppu_ppu_ppu_odma_para_vld_cnt_l_t +{ + ZXIC_UINT32 ppu_odma_para_vld_cnt_l; +}DPP_PPU_PPU_PPU_ODMA_PARA_VLD_CNT_L_T; + +typedef struct dpp_ppu_ppu_statics_isu_ppu_mc_vld_cnt_h_t +{ + ZXIC_UINT32 statics_isu_ppu_mc_vld_cnt_h; +}DPP_PPU_PPU_STATICS_ISU_PPU_MC_VLD_CNT_H_T; + +typedef struct dpp_ppu_ppu_statics_isu_ppu_mc_vld_cnt_l_t +{ + ZXIC_UINT32 statics_isu_ppu_mc_vld_cnt_l; +}DPP_PPU_PPU_STATICS_ISU_PPU_MC_VLD_CNT_L_T; + +typedef struct dpp_ppu_ppu_statics_isu_ppu_mc_loop_vld_cnt_h_t +{ + ZXIC_UINT32 statics_isu_ppu_mc_loop_vld_cnt_h; +}DPP_PPU_PPU_STATICS_ISU_PPU_MC_LOOP_VLD_CNT_H_T; + +typedef struct dpp_ppu_ppu_statics_isu_ppu_mc_loop_vld_cnt_l_t +{ + ZXIC_UINT32 statics_isu_ppu_mc_loop_vld_cnt_l; +}DPP_PPU_PPU_STATICS_ISU_PPU_MC_LOOP_VLD_CNT_L_T; + +typedef struct dpp_ppu_ppu_statics_isu_ppu_uc_vld_cnt_h_t +{ + ZXIC_UINT32 statics_isu_ppu_uc_vld_cnt_h; +}DPP_PPU_PPU_STATICS_ISU_PPU_UC_VLD_CNT_H_T; + +typedef struct dpp_ppu_ppu_statics_isu_ppu_uc_vld_cnt_l_t +{ + ZXIC_UINT32 statics_isu_ppu_uc_vld_cnt_l; +}DPP_PPU_PPU_STATICS_ISU_PPU_UC_VLD_CNT_L_T; + +typedef struct dpp_ppu_ppu_statics_isu_ppu_uc_bufnumis0_vld_cnt_h_t +{ + ZXIC_UINT32 statics_isu_ppu_uc_bufnumis0_vld_cnt_h; +}DPP_PPU_PPU_STATICS_ISU_PPU_UC_BUFNUMIS0_VLD_CNT_H_T; + +typedef struct dpp_ppu_ppu_statics_isu_ppu_uc_bufnumis0_vld_cnt_l_t +{ + ZXIC_UINT32 statics_isu_ppu_uc_bufnumis0_vld_cnt_l; +}DPP_PPU_PPU_STATICS_ISU_PPU_UC_BUFNUMIS0_VLD_CNT_L_T; + +typedef struct dpp_ppu_ppu_statics_demux_schedule_mc_vld_cnt_h_t +{ + ZXIC_UINT32 statics_demux_schedule_mc_vld_cnt_h; +}DPP_PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_VLD_CNT_H_T; + +typedef struct dpp_ppu_ppu_statics_demux_schedule_mc_vld_cnt_l_t +{ + ZXIC_UINT32 statics_demux_schedule_mc_vld_cnt_l; +}DPP_PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_VLD_CNT_L_T; + +typedef struct dpp_ppu_ppu_statics_demux_schedule_mc_bufnumis0_vld_cnt_h_t +{ + ZXIC_UINT32 statics_demux_schedule_mc_bufnumis0_vld_cnt_h; +}DPP_PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_BUFNUMIS0_VLD_CNT_H_T; + +typedef struct dpp_ppu_ppu_statics_demux_schedule_mc_bufnumis0_vld_cnt_l_t +{ + ZXIC_UINT32 statics_demux_schedule_mc_bufnumis0_vld_cnt_l; +}DPP_PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_BUFNUMIS0_VLD_CNT_L_T; + +typedef struct dpp_ppu_ppu_statics_demux_schedule_mc_srcportis0_vld_cnt_h_t +{ + ZXIC_UINT32 statics_demux_schedule_mc_srcportis0_vld_cnt_h; +}DPP_PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_SRCPORTIS0_VLD_CNT_H_T; + +typedef struct dpp_ppu_ppu_statics_demux_schedule_mc_srcportis0_vld_cnt_l_t +{ + ZXIC_UINT32 statics_demux_schedule_mc_srcportis0_vld_cnt_l; +}DPP_PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_SRCPORTIS0_VLD_CNT_L_T; + +typedef struct dpp_ppu_ppu_statics_demux_schedule_mc_srcportis1_vld_cnt_h_t +{ + ZXIC_UINT32 statics_demux_schedule_mc_srcportis1_vld_cnt_h; +}DPP_PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_SRCPORTIS1_VLD_CNT_H_T; + +typedef struct dpp_ppu_ppu_statics_demux_schedule_mc_srcportis1_vld_cnt_l_t +{ + ZXIC_UINT32 statics_demux_schedule_mc_srcportis1_vld_cnt_l; +}DPP_PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_SRCPORTIS1_VLD_CNT_L_T; + +typedef struct dpp_ppu_ppu_statics_demux_schedule_uc_vld_cnt_h_t +{ + ZXIC_UINT32 statics_demux_schedule_uc_vld_cnt_h; +}DPP_PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_VLD_CNT_H_T; + +typedef struct dpp_ppu_ppu_statics_demux_schedule_uc_vld_cnt_l_t +{ + ZXIC_UINT32 statics_demux_schedule_uc_vld_cnt_l; +}DPP_PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_VLD_CNT_L_T; + +typedef struct dpp_ppu_ppu_statics_demux_schedule_uc_bufnumis0_vld_cnt_h_t +{ + ZXIC_UINT32 statics_demux_schedule_uc_bufnumis0_vld_cnt_h; +}DPP_PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_BUFNUMIS0_VLD_CNT_H_T; + +typedef struct dpp_ppu_ppu_statics_demux_schedule_uc_bufnumis0_vld_cnt_l_t +{ + ZXIC_UINT32 statics_demux_schedule_uc_bufnumis0_vld_cnt_l; +}DPP_PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_BUFNUMIS0_VLD_CNT_L_T; + +typedef struct dpp_ppu_ppu_statics_demux_schedule_uc_srcportis0_vld_cnt_h_t +{ + ZXIC_UINT32 statics_demux_schedule_uc_srcportis0_vld_cnt_h; +}DPP_PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_SRCPORTIS0_VLD_CNT_H_T; + +typedef struct dpp_ppu_ppu_statics_demux_schedule_uc_srcportis0_vld_cnt_l_t +{ + ZXIC_UINT32 statics_demux_schedule_uc_srcportis0_vld_cnt_l; +}DPP_PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_SRCPORTIS0_VLD_CNT_L_T; + +typedef struct dpp_ppu_ppu_statics_demux_schedule_uc_srcportis1_vld_cnt_h_t +{ + ZXIC_UINT32 statics_demux_schedule_uc_srcportis1_vld_cnt_h; +}DPP_PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_SRCPORTIS1_VLD_CNT_H_T; + +typedef struct dpp_ppu_ppu_statics_demux_schedule_uc_srcportis1_vld_cnt_l_t +{ + ZXIC_UINT32 statics_demux_schedule_uc_srcportis1_vld_cnt_l; +}DPP_PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_SRCPORTIS1_VLD_CNT_L_T; + +typedef struct dpp_ppu_ppu_statics_ppu_wb_vld_cnt_h_t +{ + ZXIC_UINT32 statics_ppu_wb_vld_cnt_h; +}DPP_PPU_PPU_STATICS_PPU_WB_VLD_CNT_H_T; + +typedef struct dpp_ppu_ppu_statics_ppu_wb_vld_cnt_l_t +{ + ZXIC_UINT32 statics_ppu_wb_vld_cnt_l; +}DPP_PPU_PPU_STATICS_PPU_WB_VLD_CNT_L_T; + +typedef struct dpp_ppu_ppu_statics_ppu_wb_bufnumis0_vld_cnt_h_t +{ + ZXIC_UINT32 statics_ppu_wb_bufnumis0_vld_cnt_h; +}DPP_PPU_PPU_STATICS_PPU_WB_BUFNUMIS0_VLD_CNT_H_T; + +typedef struct dpp_ppu_ppu_statics_ppu_wb_bufnumis0_vld_cnt_l_t +{ + ZXIC_UINT32 statics_ppu_wb_bufnumis0_vld_cnt_l; +}DPP_PPU_PPU_STATICS_PPU_WB_BUFNUMIS0_VLD_CNT_L_T; + +typedef struct dpp_ppu_ppu_statics_ppu_wb_srcportis0_vld_cnt_h_t +{ + ZXIC_UINT32 statics_ppu_wb_srcportis0_vld_cnt_h; +}DPP_PPU_PPU_STATICS_PPU_WB_SRCPORTIS0_VLD_CNT_H_T; + +typedef struct dpp_ppu_ppu_statics_ppu_wb_srcportis0_vld_cnt_l_t +{ + ZXIC_UINT32 statics_ppu_wb_srcportis0_vld_cnt_l; +}DPP_PPU_PPU_STATICS_PPU_WB_SRCPORTIS0_VLD_CNT_L_T; + +typedef struct dpp_ppu_ppu_statics_ppu_wb_srcportis1_vld_cnt_h_t +{ + ZXIC_UINT32 statics_ppu_wb_srcportis1_vld_cnt_h; +}DPP_PPU_PPU_STATICS_PPU_WB_SRCPORTIS1_VLD_CNT_H_T; + +typedef struct dpp_ppu_ppu_statics_ppu_wb_srcportis1_vld_cnt_l_t +{ + ZXIC_UINT32 statics_ppu_wb_srcportis1_vld_cnt_l; +}DPP_PPU_PPU_STATICS_PPU_WB_SRCPORTIS1_VLD_CNT_L_T; + +typedef struct dpp_ppu_ppu_statics_ppu_wb_halt_send_type_vld_cnt_h_t +{ + ZXIC_UINT32 statics_ppu_wb_halt_send_type_vld_cnt_h; +}DPP_PPU_PPU_STATICS_PPU_WB_HALT_SEND_TYPE_VLD_CNT_H_T; + +typedef struct dpp_ppu_ppu_statics_ppu_wb_halt_send_type_vld_cnt_l_t +{ + ZXIC_UINT32 statics_ppu_wb_halt_send_type_vld_cnt_l; +}DPP_PPU_PPU_STATICS_PPU_WB_HALT_SEND_TYPE_VLD_CNT_L_T; + +typedef struct dpp_ppu_ppu_statics_ppu_wb_mf_type_vld_cnt_h_t +{ + ZXIC_UINT32 statics_ppu_wb_mf_type_vld_cnt_h; +}DPP_PPU_PPU_STATICS_PPU_WB_MF_TYPE_VLD_CNT_H_T; + +typedef struct dpp_ppu_ppu_statics_ppu_wb_mf_type_vld_cnt_l_t +{ + ZXIC_UINT32 statics_ppu_wb_mf_type_vld_cnt_l; +}DPP_PPU_PPU_STATICS_PPU_WB_MF_TYPE_VLD_CNT_L_T; + +typedef struct dpp_ppu_ppu_statics_ppu_wb_halt_continue_end_vld_cnt_h_t +{ + ZXIC_UINT32 statics_ppu_wb_halt_continue_end_vld_cnt_h; +}DPP_PPU_PPU_STATICS_PPU_WB_HALT_CONTINUE_END_VLD_CNT_H_T; + +typedef struct dpp_ppu_ppu_statics_ppu_wb_halt_continue_end_vld_cnt_l_t +{ + ZXIC_UINT32 statics_ppu_wb_halt_continue_end_vld_cnt_l; +}DPP_PPU_PPU_STATICS_PPU_WB_HALT_CONTINUE_END_VLD_CNT_L_T; + +typedef struct dpp_ppu_ppu_statics_ppu_wb_dup_flag_vld_cnt_h_t +{ + ZXIC_UINT32 statics_ppu_wb_dup_flag_vld_cnt_h; +}DPP_PPU_PPU_STATICS_PPU_WB_DUP_FLAG_VLD_CNT_H_T; + +typedef struct dpp_ppu_ppu_statics_ppu_wb_dup_flag_vld_cnt_l_t +{ + ZXIC_UINT32 statics_ppu_wb_dup_flag_vld_cnt_l; +}DPP_PPU_PPU_STATICS_PPU_WB_DUP_FLAG_VLD_CNT_L_T; + +typedef struct dpp_ppu_ppu_statics_ppu_wb_last_flag_vld_cnt_h_t +{ + ZXIC_UINT32 statics_ppu_wb_last_flag_vld_cnt_h; +}DPP_PPU_PPU_STATICS_PPU_WB_LAST_FLAG_VLD_CNT_H_T; + +typedef struct dpp_ppu_ppu_statics_ppu_wb_last_flag_vld_cnt_l_t +{ + ZXIC_UINT32 statics_ppu_wb_last_flag_vld_cnt_l; +}DPP_PPU_PPU_STATICS_PPU_WB_LAST_FLAG_VLD_CNT_L_T; + +typedef struct dpp_ppu_ppu_statics_ppu_wb_dis_flag_vld_cnt_h_t +{ + ZXIC_UINT32 statics_ppu_wb_dis_flag_vld_cnt_h; +}DPP_PPU_PPU_STATICS_PPU_WB_DIS_FLAG_VLD_CNT_H_T; + +typedef struct dpp_ppu_ppu_statics_ppu_wb_dis_flag_vld_cnt_l_t +{ + ZXIC_UINT32 statics_ppu_wb_dis_flag_vld_cnt_l; +}DPP_PPU_PPU_STATICS_PPU_WB_DIS_FLAG_VLD_CNT_L_T; + +typedef struct dpp_ppu_ppu_statics_pbu_ppu_reorder_halt_send_type_vld_cnt_h_t +{ + ZXIC_UINT32 statics_pbu_ppu_reorder_halt_send_type_vld_cnt_h; +}DPP_PPU_PPU_STATICS_PBU_PPU_REORDER_HALT_SEND_TYPE_VLD_CNT_H_T; + +typedef struct dpp_ppu_ppu_statics_pbu_ppu_reorder_halt_send_type_vld_cnt_l_t +{ + ZXIC_UINT32 statics_pbu_ppu_reorder_halt_send_type_vld_cnt_l; +}DPP_PPU_PPU_STATICS_PBU_PPU_REORDER_HALT_SEND_TYPE_VLD_CNT_L_T; + +typedef struct dpp_ppu_ppu_statics_pbu_ppu_reorder_mf_type_vld_cnt_h_t +{ + ZXIC_UINT32 statics_pbu_ppu_reorder_mf_type_vld_cnt_h; +}DPP_PPU_PPU_STATICS_PBU_PPU_REORDER_MF_TYPE_VLD_CNT_H_T; + +typedef struct dpp_ppu_ppu_statics_pbu_ppu_reorder_mf_type_vld_cnt_l_t +{ + ZXIC_UINT32 statics_pbu_ppu_reorder_mf_type_vld_cnt_l; +}DPP_PPU_PPU_STATICS_PBU_PPU_REORDER_MF_TYPE_VLD_CNT_L_T; + +typedef struct dpp_ppu_ppu_statics_pbu_ppu_reorder_halt_continue_end_vld_cnt_h_t +{ + ZXIC_UINT32 statics_pbu_ppu_reorder_halt_continue_end_vld_cnt_h; +}DPP_PPU_PPU_STATICS_PBU_PPU_REORDER_HALT_CONTINUE_END_VLD_CNT_H_T; + +typedef struct dpp_ppu_ppu_statics_pbu_ppu_reorder_halt_continue_end_vld_cnt_l_t +{ + ZXIC_UINT32 statics_pbu_ppu_reorder_halt_continue_end_vld_cnt_l; +}DPP_PPU_PPU_STATICS_PBU_PPU_REORDER_HALT_CONTINUE_END_VLD_CNT_L_T; + +typedef struct dpp_ppu_ppu_car_green_pkt_vld_cnt_h_t +{ + ZXIC_UINT32 car_green_pkt_vld_cnt_h; +}DPP_PPU_PPU_CAR_GREEN_PKT_VLD_CNT_H_T; + +typedef struct dpp_ppu_ppu_car_green_pkt_vld_cnt_l_t +{ + ZXIC_UINT32 car_green_pkt_vld_cnt_l; +}DPP_PPU_PPU_CAR_GREEN_PKT_VLD_CNT_L_T; + +typedef struct dpp_ppu_ppu_car_yellow_pkt_vld_cnt_h_t +{ + ZXIC_UINT32 car_yellow_pkt_vld_cnt_h; +}DPP_PPU_PPU_CAR_YELLOW_PKT_VLD_CNT_H_T; + +typedef struct dpp_ppu_ppu_car_yellow_pkt_vld_cnt_l_t +{ + ZXIC_UINT32 car_yellow_pkt_vld_cnt_l; +}DPP_PPU_PPU_CAR_YELLOW_PKT_VLD_CNT_L_T; + +typedef struct dpp_ppu_ppu_car_red_pkt_vld_cnt_h_t +{ + ZXIC_UINT32 car_red_pkt_vld_cnt_h; +}DPP_PPU_PPU_CAR_RED_PKT_VLD_CNT_H_T; + +typedef struct dpp_ppu_ppu_car_red_pkt_vld_cnt_l_t +{ + ZXIC_UINT32 car_red_pkt_vld_cnt_l; +}DPP_PPU_PPU_CAR_RED_PKT_VLD_CNT_L_T; + +typedef struct dpp_ppu_ppu_car_drop_pkt_vld_cnt_h_t +{ + ZXIC_UINT32 car_drop_pkt_vld_cnt_h; +}DPP_PPU_PPU_CAR_DROP_PKT_VLD_CNT_H_T; + +typedef struct dpp_ppu_ppu_car_drop_pkt_vld_cnt_l_t +{ + ZXIC_UINT32 car_drop_pkt_vld_cnt_l; +}DPP_PPU_PPU_CAR_DROP_PKT_VLD_CNT_L_T; + +typedef struct dpp_ppu_ppu_ppu_pktrx_mc_ptr_vld_cnt_h_t +{ + ZXIC_UINT32 ppu_pktrx_mc_ptr_vld_cnt_h; +}DPP_PPU_PPU_PPU_PKTRX_MC_PTR_VLD_CNT_H_T; + +typedef struct dpp_ppu_ppu_ppu_pktrx_mc_ptr_vld_cnt_l_t +{ + ZXIC_UINT32 ppu_pktrx_mc_ptr_vld_cnt_l; +}DPP_PPU_PPU_PPU_PKTRX_MC_PTR_VLD_CNT_L_T; + +typedef struct dpp_ppu_ppu_isu_ppu_loopback_fc_cnt_h_t +{ + ZXIC_UINT32 ppu_pktrx_mc_ptr_vld_cnt_h; +}DPP_PPU_PPU_ISU_PPU_LOOPBACK_FC_CNT_H_T; + +typedef struct dpp_ppu_ppu_isu_ppu_loopback_fc_cnt_l_t +{ + ZXIC_UINT32 ppu_pktrx_mc_ptr_vld_cnt_l; +}DPP_PPU_PPU_ISU_PPU_LOOPBACK_FC_CNT_L_T; + +typedef struct dpp_ppu_ppu_ppu_culster_pbu_mcode_pf_req_prog_full_assert_cfg_t +{ + ZXIC_UINT32 ppu_culster_pbu_mcode_pf_req_prog_full_assert_cfg; +}DPP_PPU_PPU_PPU_CULSTER_PBU_MCODE_PF_REQ_PROG_FULL_ASSERT_CFG_T; + +typedef struct dpp_ppu_ppu_ppu_culster_pbu_mcode_pf_req_prog_full_negate_cfg_t +{ + ZXIC_UINT32 ppu_culster_pbu_mcode_pf_req_prog_full_negate_cfg; +}DPP_PPU_PPU_PPU_CULSTER_PBU_MCODE_PF_REQ_PROG_FULL_NEGATE_CFG_T; + +typedef struct dpp_ppu_ppu_ppu_culster_pbu_mcode_pf_req_prog_empty_assert_cfg_t +{ + ZXIC_UINT32 ppu_culster_pbu_mcode_pf_req_prog_empty_assert_cfg; +}DPP_PPU_PPU_PPU_CULSTER_PBU_MCODE_PF_REQ_PROG_EMPTY_ASSERT_CFG_T; + +typedef struct dpp_ppu_ppu_ppu_culster_pbu_mcode_pf_req_prog_empty_negate_cfg_t +{ + ZXIC_UINT32 ppu_culster_pbu_mcode_pf_req_prog_empty_negate_cfg; +}DPP_PPU_PPU_PPU_CULSTER_PBU_MCODE_PF_REQ_PROG_EMPTY_NEGATE_CFG_T; + +typedef struct dpp_ppu_ppu_ppu_pbu_mcode_pf_rsp_prog_full_assert_cfg_t +{ + ZXIC_UINT32 ppu_pbu_mcode_pf_rsp_prog_full_assert_cfg; +}DPP_PPU_PPU_PPU_PBU_MCODE_PF_RSP_PROG_FULL_ASSERT_CFG_T; + +typedef struct dpp_ppu_ppu_ppu_pbu_mcode_pf_rsp_prog_full_negate_cfg_t +{ + ZXIC_UINT32 ppu_pbu_mcode_pf_rsp_prog_full_negate_cfg; +}DPP_PPU_PPU_PPU_PBU_MCODE_PF_RSP_PROG_FULL_NEGATE_CFG_T; + +typedef struct dpp_ppu_ppu_ppu_pbu_mcode_pf_rsp_prog_empty_assert_cfg_t +{ + ZXIC_UINT32 ppu_pbu_mcode_pf_rsp_prog_empty_assert_cfg; +}DPP_PPU_PPU_PPU_PBU_MCODE_PF_RSP_PROG_EMPTY_ASSERT_CFG_T; + +typedef struct dpp_ppu_ppu_ppu_pbu_mcode_pf_rsp_prog_empty_negate_cfg_t +{ + ZXIC_UINT32 ppu_pbu_mcode_pf_rsp_prog_empty_negate_cfg; +}DPP_PPU_PPU_PPU_PBU_MCODE_PF_RSP_PROG_EMPTY_NEGATE_CFG_T; + +typedef struct dpp_ppu_ppu_mccnt_fifo_prog_full_assert_cfg_t +{ + ZXIC_UINT32 mccnt_fifo_prog_full_assert_cfg; +}DPP_PPU_PPU_MCCNT_FIFO_PROG_FULL_ASSERT_CFG_T; + +typedef struct dpp_ppu_ppu_mccnt_fifo_prog_full_negate_cfg_t +{ + ZXIC_UINT32 mccnt_fifo_prog_full_negate_cfg; +}DPP_PPU_PPU_MCCNT_FIFO_PROG_FULL_NEGATE_CFG_T; + +typedef struct dpp_ppu_ppu_mccnt_fifo_prog_empty_assert_cfg_t +{ + ZXIC_UINT32 mccnt_fifo_prog_empty_assert_cfg; +}DPP_PPU_PPU_MCCNT_FIFO_PROG_EMPTY_ASSERT_CFG_T; + +typedef struct dpp_ppu_ppu_mccnt_fifo_prog_empty_negate_cfg_t +{ + ZXIC_UINT32 mccnt_fifo_prog_empty_negate_cfg; +}DPP_PPU_PPU_MCCNT_FIFO_PROG_EMPTY_NEGATE_CFG_T; + +typedef struct dpp_ppu_ppu_uc_mf_fifo_prog_full_assert_cfg_t +{ + ZXIC_UINT32 uc_mf_fifo_prog_full_assert_cfg; +}DPP_PPU_PPU_UC_MF_FIFO_PROG_FULL_ASSERT_CFG_T; + +typedef struct dpp_ppu_ppu_uc_mf_fifo_prog_full_negate_cfg_t +{ + ZXIC_UINT32 uc_mf_fifo_prog_full_negate_cfg; +}DPP_PPU_PPU_UC_MF_FIFO_PROG_FULL_NEGATE_CFG_T; + +typedef struct dpp_ppu_ppu_uc_mf_fifo_prog_empty_assert_cfg_t +{ + ZXIC_UINT32 uc_mf_fifo_prog_empty_assert_cfg; +}DPP_PPU_PPU_UC_MF_FIFO_PROG_EMPTY_ASSERT_CFG_T; + +typedef struct dpp_ppu_ppu_uc_mf_fifo_prog_empty_negate_cfg_t +{ + ZXIC_UINT32 uc_mf_fifo_prog_empty_negate_cfg; +}DPP_PPU_PPU_UC_MF_FIFO_PROG_EMPTY_NEGATE_CFG_T; + +typedef struct dpp_ppu_ppu_mc_mf_fifo_prog_full_assert_cfg_t +{ + ZXIC_UINT32 mc_mf_fifo_prog_full_assert_cfg; +}DPP_PPU_PPU_MC_MF_FIFO_PROG_FULL_ASSERT_CFG_T; + +typedef struct dpp_ppu_ppu_mc_mf_fifo_prog_full_negate_cfg_t +{ + ZXIC_UINT32 mc_mf_fifo_prog_full_negate_cfg; +}DPP_PPU_PPU_MC_MF_FIFO_PROG_FULL_NEGATE_CFG_T; + +typedef struct dpp_ppu_ppu_mc_mf_fifo_prog_empty_assert_cfg_t +{ + ZXIC_UINT32 mc_mf_fifo_prog_empty_assert_cfg; +}DPP_PPU_PPU_MC_MF_FIFO_PROG_EMPTY_ASSERT_CFG_T; + +typedef struct dpp_ppu_ppu_mc_mf_fifo_prog_empty_negate_cfg_t +{ + ZXIC_UINT32 mc_mf_fifo_prog_empty_negate_cfg; +}DPP_PPU_PPU_MC_MF_FIFO_PROG_EMPTY_NEGATE_CFG_T; + +typedef struct dpp_ppu_ppu_isu_mf_fifo_prog_full_assert_cfg_t +{ + ZXIC_UINT32 isu_mf_fifo_prog_full_assert_cfg; +}DPP_PPU_PPU_ISU_MF_FIFO_PROG_FULL_ASSERT_CFG_T; + +typedef struct dpp_ppu_ppu_isu_mf_fifo_prog_full_negate_cfg_t +{ + ZXIC_UINT32 isu_mf_fifo_prog_full_negate_cfg; +}DPP_PPU_PPU_ISU_MF_FIFO_PROG_FULL_NEGATE_CFG_T; + +typedef struct dpp_ppu_ppu_isu_mf_fifo_prog_empty_assert_cfg_t +{ + ZXIC_UINT32 isu_mf_fifo_prog_empty_assert_cfg; +}DPP_PPU_PPU_ISU_MF_FIFO_PROG_EMPTY_ASSERT_CFG_T; + +typedef struct dpp_ppu_ppu_isu_mf_fifo_prog_empty_negate_cfg_t +{ + ZXIC_UINT32 isu_mf_fifo_prog_empty_negate_cfg; +}DPP_PPU_PPU_ISU_MF_FIFO_PROG_EMPTY_NEGATE_CFG_T; + +typedef struct dpp_ppu_ppu_isu_fwft_mf_fifo_prog_empty_assert_cfg_t +{ + ZXIC_UINT32 isu_fwft_mf_fifo_prog_empty_assert_cfg; +}DPP_PPU_PPU_ISU_FWFT_MF_FIFO_PROG_EMPTY_ASSERT_CFG_T; + +typedef struct dpp_ppu_ppu_isu_fwft_mf_fifo_prog_empty_negate_cfg_t +{ + ZXIC_UINT32 isu_fwft_mf_fifo_prog_empty_negate_cfg; +}DPP_PPU_PPU_ISU_FWFT_MF_FIFO_PROG_EMPTY_NEGATE_CFG_T; + +typedef struct dpp_ppu_ppu_isu_mc_para_mf_fifo_prog_full_assert_cfg_t +{ + ZXIC_UINT32 isu_mc_para_mf_fifo_prog_full_assert_cfg; +}DPP_PPU_PPU_ISU_MC_PARA_MF_FIFO_PROG_FULL_ASSERT_CFG_T; + +typedef struct dpp_ppu_ppu_isu_mc_para_mf_fifo_prog_full_negate_cfg_t +{ + ZXIC_UINT32 isu_mc_para_mf_fifo_prog_full_negate_cfg; +}DPP_PPU_PPU_ISU_MC_PARA_MF_FIFO_PROG_FULL_NEGATE_CFG_T; + +typedef struct dpp_ppu_ppu_isu_mc_para_mf_fifo_prog_empty_assert_cfg_t +{ + ZXIC_UINT32 isu_mc_para_mf_fifo_prog_empty_assert_cfg; +}DPP_PPU_PPU_ISU_MC_PARA_MF_FIFO_PROG_EMPTY_ASSERT_CFG_T; + +typedef struct dpp_ppu_ppu_isu_mc_para_mf_fifo_prog_empty_negate_cfg_t +{ + ZXIC_UINT32 isu_mc_para_mf_fifo_prog_empty_negate_cfg; +}DPP_PPU_PPU_ISU_MC_PARA_MF_FIFO_PROG_EMPTY_NEGATE_CFG_T; + +typedef struct dpp_ppu_ppu_group_id_fifo_prog_full_assert_cfg_t +{ + ZXIC_UINT32 group_id_fifo_prog_full_assert_cfg; +}DPP_PPU_PPU_GROUP_ID_FIFO_PROG_FULL_ASSERT_CFG_T; + +typedef struct dpp_ppu_ppu_group_id_fifo_prog_full_negate_cfg_t +{ + ZXIC_UINT32 group_id_fifo_prog_full_negate_cfg; +}DPP_PPU_PPU_GROUP_ID_FIFO_PROG_FULL_NEGATE_CFG_T; + +typedef struct dpp_ppu_ppu_group_id_fifo_prog_empty_assert_cfg_t +{ + ZXIC_UINT32 group_id_fifo_prog_empty_assert_cfg; +}DPP_PPU_PPU_GROUP_ID_FIFO_PROG_EMPTY_ASSERT_CFG_T; + +typedef struct dpp_ppu_ppu_group_id_fifo_prog_empty_negate_cfg_t +{ + ZXIC_UINT32 group_id_fifo_prog_empty_negate_cfg; +}DPP_PPU_PPU_GROUP_ID_FIFO_PROG_EMPTY_NEGATE_CFG_T; + +typedef struct dpp_ppu_ppu_sa_para_fifo_prog_full_assert_cfg_t +{ + ZXIC_UINT32 sa_para_fifo_prog_full_assert_cfg; +}DPP_PPU_PPU_SA_PARA_FIFO_PROG_FULL_ASSERT_CFG_T; + +typedef struct dpp_ppu_ppu_sa_para_fifo_prog_full_negate_cfg_t +{ + ZXIC_UINT32 sa_para_fifo_prog_full_negate_cfg; +}DPP_PPU_PPU_SA_PARA_FIFO_PROG_FULL_NEGATE_CFG_T; + +typedef struct dpp_ppu_ppu_sa_para_fifo_prog_empty_assert_cfg_t +{ + ZXIC_UINT32 sa_para_fifo_prog_empty_assert_cfg; +}DPP_PPU_PPU_SA_PARA_FIFO_PROG_EMPTY_ASSERT_CFG_T; + +typedef struct dpp_ppu_ppu_sa_para_fifo_prog_empty_negate_cfg_t +{ + ZXIC_UINT32 sa_para_fifo_prog_empty_negate_cfg; +}DPP_PPU_PPU_SA_PARA_FIFO_PROG_EMPTY_NEGATE_CFG_T; + +typedef struct dpp_ppu_ppu_se_mc_rsp_fifo_prog_full_assert_cfg_t +{ + ZXIC_UINT32 se_mc_rsp_fifo_prog_full_assert_cfg; +}DPP_PPU_PPU_SE_MC_RSP_FIFO_PROG_FULL_ASSERT_CFG_T; + +typedef struct dpp_ppu_ppu_se_mc_rsp_fifo_prog_full_negate_cfg_t +{ + ZXIC_UINT32 se_mc_rsp_fifo_prog_full_negate_cfg; +}DPP_PPU_PPU_SE_MC_RSP_FIFO_PROG_FULL_NEGATE_CFG_T; + +typedef struct dpp_ppu_ppu_se_mc_rsp_fifo_prog_empty_assert_cfg_t +{ + ZXIC_UINT32 se_mc_rsp_fifo_prog_empty_assert_cfg; +}DPP_PPU_PPU_SE_MC_RSP_FIFO_PROG_EMPTY_ASSERT_CFG_T; + +typedef struct dpp_ppu_ppu_se_mc_rsp_fifo_prog_empty_negate_cfg_t +{ + ZXIC_UINT32 se_mc_rsp_fifo_prog_empty_negate_cfg; +}DPP_PPU_PPU_SE_MC_RSP_FIFO_PROG_EMPTY_NEGATE_CFG_T; + +typedef struct dpp_ppu_ppu_dup_para_fifo_prog_full_assert_cfg_t +{ + ZXIC_UINT32 dup_para_fifo_prog_full_assert_cfg; +}DPP_PPU_PPU_DUP_PARA_FIFO_PROG_FULL_ASSERT_CFG_T; + +typedef struct dpp_ppu_ppu_dup_para_fifo_prog_full_negate_cfg_t +{ + ZXIC_UINT32 dup_para_fifo_prog_full_negate_cfg; +}DPP_PPU_PPU_DUP_PARA_FIFO_PROG_FULL_NEGATE_CFG_T; + +typedef struct dpp_ppu_ppu_dup_para_fifo_prog_empty_assert_cfg_t +{ + ZXIC_UINT32 dup_para_fifo_prog_empty_assert_cfg; +}DPP_PPU_PPU_DUP_PARA_FIFO_PROG_EMPTY_ASSERT_CFG_T; + +typedef struct dpp_ppu_ppu_dup_para_fifo_prog_empty_negate_cfg_t +{ + ZXIC_UINT32 dup_para_fifo_prog_empty_negate_cfg; +}DPP_PPU_PPU_DUP_PARA_FIFO_PROG_EMPTY_NEGATE_CFG_T; + +typedef struct dpp_ppu_ppu_pf_rsp_fifo_prog_full_assert_cfg_t +{ + ZXIC_UINT32 pf_rsp_fifo_prog_full_assert_cfg; +}DPP_PPU_PPU_PF_RSP_FIFO_PROG_FULL_ASSERT_CFG_T; + +typedef struct dpp_ppu_ppu_pf_rsp_fifo_prog_full_negate_cfg_t +{ + ZXIC_UINT32 pf_rsp_fifo_prog_full_negate_cfg; +}DPP_PPU_PPU_PF_RSP_FIFO_PROG_FULL_NEGATE_CFG_T; + +typedef struct dpp_ppu_ppu_pf_rsp_fifo_prog_empty_assert_cfg_t +{ + ZXIC_UINT32 pf_rsp_fifo_prog_empty_assert_cfg; +}DPP_PPU_PPU_PF_RSP_FIFO_PROG_EMPTY_ASSERT_CFG_T; + +typedef struct dpp_ppu_ppu_pf_rsp_fifo_prog_empty_negate_cfg_t +{ + ZXIC_UINT32 pf_rsp_fifo_prog_empty_negate_cfg; +}DPP_PPU_PPU_PF_RSP_FIFO_PROG_EMPTY_NEGATE_CFG_T; + +typedef struct dpp_ppu_ppu_dup_freeptr_fifo_prog_full_assert_cfg_t +{ + ZXIC_UINT32 dup_freeptr_fifo_prog_full_assert_cfg; +}DPP_PPU_PPU_DUP_FREEPTR_FIFO_PROG_FULL_ASSERT_CFG_T; + +typedef struct dpp_ppu_ppu_dup_freeptr_fifo_prog_full_negate_cfg_t +{ + ZXIC_UINT32 dup_freeptr_fifo_prog_full_negate_cfg; +}DPP_PPU_PPU_DUP_FREEPTR_FIFO_PROG_FULL_NEGATE_CFG_T; + +typedef struct dpp_ppu_ppu_dup_freeptr_fifo_prog_empty_assert_cfg_t +{ + ZXIC_UINT32 dup_freeptr_fifo_prog_empty_assert_cfg; +}DPP_PPU_PPU_DUP_FREEPTR_FIFO_PROG_EMPTY_ASSERT_CFG_T; + +typedef struct dpp_ppu_ppu_dup_freeptr_fifo_prog_empty_negate_cfg_t +{ + ZXIC_UINT32 dup_freeptr_fifo_prog_empty_negate_cfg; +}DPP_PPU_PPU_DUP_FREEPTR_FIFO_PROG_EMPTY_NEGATE_CFG_T; + +typedef struct dpp_ppu_ppu_pf_req_fifo_prog_full_assert_cfg_t +{ + ZXIC_UINT32 pf_req_fifo_prog_full_assert_cfg; +}DPP_PPU_PPU_PF_REQ_FIFO_PROG_FULL_ASSERT_CFG_T; + +typedef struct dpp_ppu_ppu_pf_req_fifo_prog_full_negate_cfg_t +{ + ZXIC_UINT32 pf_req_fifo_prog_full_negate_cfg; +}DPP_PPU_PPU_PF_REQ_FIFO_PROG_FULL_NEGATE_CFG_T; + +typedef struct dpp_ppu_ppu_pf_req_fifo_prog_empty_assert_cfg_t +{ + ZXIC_UINT32 pf_req_fifo_prog_empty_assert_cfg; +}DPP_PPU_PPU_PF_REQ_FIFO_PROG_EMPTY_ASSERT_CFG_T; + +typedef struct dpp_ppu_ppu_pf_req_fifo_prog_empty_negate_cfg_t +{ + ZXIC_UINT32 pf_req_fifo_prog_empty_negate_cfg; +}DPP_PPU_PPU_PF_REQ_FIFO_PROG_EMPTY_NEGATE_CFG_T; + +typedef struct dpp_ppu_ppu_car_flag_fifo_prog_full_assert_cfg_t +{ + ZXIC_UINT32 car_flag_fifo_prog_full_assert_cfg; +}DPP_PPU_PPU_CAR_FLAG_FIFO_PROG_FULL_ASSERT_CFG_T; + +typedef struct dpp_ppu_ppu_car_flag_fifo_prog_full_negate_cfg_t +{ + ZXIC_UINT32 car_flag_fifo_prog_full_negate_cfg; +}DPP_PPU_PPU_CAR_FLAG_FIFO_PROG_FULL_NEGATE_CFG_T; + +typedef struct dpp_ppu_ppu_car_flag_fifo_prog_empty_assert_cfg_t +{ + ZXIC_UINT32 car_flag_fifo_prog_empty_assert_cfg; +}DPP_PPU_PPU_CAR_FLAG_FIFO_PROG_EMPTY_ASSERT_CFG_T; + +typedef struct dpp_ppu_ppu_car_flag_fifo_prog_empty_negate_cfg_t +{ + ZXIC_UINT32 car_flag_fifo_prog_empty_negate_cfg; +}DPP_PPU_PPU_CAR_FLAG_FIFO_PROG_EMPTY_NEGATE_CFG_T; + +typedef struct dpp_ppu_ppu_ppu_cluster_mf_out_afifo_prog_full_assert_cfg_t +{ + ZXIC_UINT32 ppu_cluster_mf_out_afifo_prog_full_assert_cfg; +}DPP_PPU_PPU_PPU_CLUSTER_MF_OUT_AFIFO_PROG_FULL_ASSERT_CFG_T; + +typedef struct dpp_ppu_ppu_ppu_cluster_mf_out_afifo_prog_full_negate_cfg_t +{ + ZXIC_UINT32 ppu_cluster_mf_out_afifo_prog_full_negate_cfg; +}DPP_PPU_PPU_PPU_CLUSTER_MF_OUT_AFIFO_PROG_FULL_NEGATE_CFG_T; + +typedef struct dpp_ppu_ppu_ppu_cluster_mf_out_afifo_prog_empty_assert_cfg_t +{ + ZXIC_UINT32 ppu_cluster_mf_out_afifo_prog_empty_assert_cfg; +}DPP_PPU_PPU_PPU_CLUSTER_MF_OUT_AFIFO_PROG_EMPTY_ASSERT_CFG_T; + +typedef struct dpp_ppu_ppu_ppu_cluster_mf_out_afifo_prog_empty_negate_cfg_t +{ + ZXIC_UINT32 ppu_cluster_mf_out_afifo_prog_empty_negate_cfg; +}DPP_PPU_PPU_PPU_CLUSTER_MF_OUT_AFIFO_PROG_EMPTY_NEGATE_CFG_T; + +typedef struct dpp_ppu_ppu_ppu_cop_key_fifo_prog_full_assert_cfg_t +{ + ZXIC_UINT32 ppu_cop_key_fifo_prog_full_assert_cfg; +}DPP_PPU_PPU_PPU_COP_KEY_FIFO_PROG_FULL_ASSERT_CFG_T; + +typedef struct dpp_ppu_ppu_ppu_cop_key_fifo_prog_full_negate_cfg_t +{ + ZXIC_UINT32 ppu_cop_key_fifo_prog_full_negate_cfg; +}DPP_PPU_PPU_PPU_COP_KEY_FIFO_PROG_FULL_NEGATE_CFG_T; + +typedef struct dpp_ppu_ppu_ppu_cop_key_fifo_prog_empty_assert_cfg_t +{ + ZXIC_UINT32 ppu_cop_key_fifo_prog_empty_assert_cfg; +}DPP_PPU_PPU_PPU_COP_KEY_FIFO_PROG_EMPTY_ASSERT_CFG_T; + +typedef struct dpp_ppu_ppu_ppu_cop_key_fifo_prog_empty_negate_cfg_t +{ + ZXIC_UINT32 ppu_cop_key_fifo_prog_empty_negate_cfg; +}DPP_PPU_PPU_PPU_COP_KEY_FIFO_PROG_EMPTY_NEGATE_CFG_T; + +typedef struct dpp_ppu_ppu_ppu_cop_random_mod_para_fifo_prog_full_assert_cfg_t +{ + ZXIC_UINT32 ppu_cop_random_mod_para_fifo_prog_full_assert_cfg; +}DPP_PPU_PPU_PPU_COP_RANDOM_MOD_PARA_FIFO_PROG_FULL_ASSERT_CFG_T; + +typedef struct dpp_ppu_ppu_ppu_cop_random_mod_para_fifo_prog_full_negate_cfg_t +{ + ZXIC_UINT32 ppu_cop_random_mod_para_fifo_prog_full_negate_cfg; +}DPP_PPU_PPU_PPU_COP_RANDOM_MOD_PARA_FIFO_PROG_FULL_NEGATE_CFG_T; + +typedef struct dpp_ppu_ppu_ppu_cop_random_mod_para_fifo_prog_empty_assert_cfg_t +{ + ZXIC_UINT32 ppu_cop_random_mod_para_fifo_prog_empty_assert_cfg; +}DPP_PPU_PPU_PPU_COP_RANDOM_MOD_PARA_FIFO_PROG_EMPTY_ASSERT_CFG_T; + +typedef struct dpp_ppu_ppu_ppu_cop_random_mod_para_fifo_prog_empty_negate_cfg_t +{ + ZXIC_UINT32 ppu_cop_random_mod_para_fifo_prog_empty_negate_cfg; +}DPP_PPU_PPU_PPU_COP_RANDOM_MOD_PARA_FIFO_PROG_EMPTY_NEGATE_CFG_T; + +typedef struct dpp_ppu_ppu_ppu_cop_random_mod_result_fifo_prog_full_assert_cfg_t +{ + ZXIC_UINT32 ppu_cop_random_mod_result_fifo_prog_full_assert_cfg; +}DPP_PPU_PPU_PPU_COP_RANDOM_MOD_RESULT_FIFO_PROG_FULL_ASSERT_CFG_T; + +typedef struct dpp_ppu_ppu_ppu_cop_random_mod_result_fifo_prog_full_negate_cfg_t +{ + ZXIC_UINT32 ppu_cop_random_mod_result_fifo_prog_full_negate_cfg; +}DPP_PPU_PPU_PPU_COP_RANDOM_MOD_RESULT_FIFO_PROG_FULL_NEGATE_CFG_T; + +typedef struct dpp_ppu_ppu_ppu_cop_random_mod_result_fifo_prog_empty_assert_cfg_t +{ + ZXIC_UINT32 ppu_cop_random_mod_result_fifo_prog_empty_assert_cfg; +}DPP_PPU_PPU_PPU_COP_RANDOM_MOD_RESULT_FIFO_PROG_EMPTY_ASSERT_CFG_T; + +typedef struct dpp_ppu_ppu_ppu_cop_random_mod_result_fifo_prog_empty_negate_cfg_t +{ + ZXIC_UINT32 ppu_cop_random_mod_result_fifo_prog_empty_negate_cfg; +}DPP_PPU_PPU_PPU_COP_RANDOM_MOD_RESULT_FIFO_PROG_EMPTY_NEGATE_CFG_T; + +typedef struct dpp_ppu_ppu_ppu_cop_checksum_result_fifo_prog_full_assert_cfg_t +{ + ZXIC_UINT32 ppu_cop_checksum_result_fifo_prog_full_assert_cfg; +}DPP_PPU_PPU_PPU_COP_CHECKSUM_RESULT_FIFO_PROG_FULL_ASSERT_CFG_T; + +typedef struct dpp_ppu_ppu_ppu_cop_checksum_result_fifo_prog_full_negate_cfg_t +{ + ZXIC_UINT32 ppu_cop_checksum_result_fifo_prog_full_negate_cfg; +}DPP_PPU_PPU_PPU_COP_CHECKSUM_RESULT_FIFO_PROG_FULL_NEGATE_CFG_T; + +typedef struct dpp_ppu_ppu_ppu_cop_checksum_result_fifo_prog_empty_assert_cfg_t +{ + ZXIC_UINT32 ppu_cop_checksum_result_fifo_prog_empty_assert_cfg; +}DPP_PPU_PPU_PPU_COP_CHECKSUM_RESULT_FIFO_PROG_EMPTY_ASSERT_CFG_T; + +typedef struct dpp_ppu_ppu_ppu_cop_checksum_result_fifo_prog_empty_negate_cfg_t +{ + ZXIC_UINT32 ppu_cop_checksum_result_fifo_prog_empty_negate_cfg; +}DPP_PPU_PPU_PPU_COP_CHECKSUM_RESULT_FIFO_PROG_EMPTY_NEGATE_CFG_T; + +typedef struct dpp_ppu_ppu_ppu_cop_crc_first_para_fifo_prog_full_assert_cfg_t +{ + ZXIC_UINT32 ppu_cop_crc_first_para_fifo_prog_full_assert_cfg; +}DPP_PPU_PPU_PPU_COP_CRC_FIRST_PARA_FIFO_PROG_FULL_ASSERT_CFG_T; + +typedef struct dpp_ppu_ppu_ppu_cop_crc_first_para_fifo_prog_full_negate_cfg_t +{ + ZXIC_UINT32 ppu_cop_crc_first_para_fifo_prog_full_negate_cfg; +}DPP_PPU_PPU_PPU_COP_CRC_FIRST_PARA_FIFO_PROG_FULL_NEGATE_CFG_T; + +typedef struct dpp_ppu_ppu_ppu_cop_crc_first_para_fifo_prog_empty_assert_cfg_t +{ + ZXIC_UINT32 ppu_cop_crc_first_para_fifo_prog_empty_assert_cfg; +}DPP_PPU_PPU_PPU_COP_CRC_FIRST_PARA_FIFO_PROG_EMPTY_ASSERT_CFG_T; + +typedef struct dpp_ppu_ppu_ppu_cop_crc_first_para_fifo_prog_empty_negate_cfg_t +{ + ZXIC_UINT32 ppu_cop_crc_first_para_fifo_prog_empty_negate_cfg; +}DPP_PPU_PPU_PPU_COP_CRC_FIRST_PARA_FIFO_PROG_EMPTY_NEGATE_CFG_T; + +typedef struct dpp_ppu_ppu_ppu_cop_crc_bypass_delay_prog_full_assert_cfg_t +{ + ZXIC_UINT32 ppu_cop_crc_bypass_delay_prog_full_assert_cfg; +}DPP_PPU_PPU_PPU_COP_CRC_BYPASS_DELAY_PROG_FULL_ASSERT_CFG_T; + +typedef struct dpp_ppu_ppu_ppu_cop_crc_bypass_delay_prog_full_negate_cfg_t +{ + ZXIC_UINT32 ppu_cop_crc_bypass_delay_prog_full_negate_cfg; +}DPP_PPU_PPU_PPU_COP_CRC_BYPASS_DELAY_PROG_FULL_NEGATE_CFG_T; + +typedef struct dpp_ppu_ppu_ppu_cop_crc_bypass_delay_prog_empty_assert_cfg_t +{ + ZXIC_UINT32 ppu_cop_crc_bypass_delay_prog_empty_assert_cfg; +}DPP_PPU_PPU_PPU_COP_CRC_BYPASS_DELAY_PROG_EMPTY_ASSERT_CFG_T; + +typedef struct dpp_ppu_ppu_ppu_cop_crc_bypass_delay_prog_empty_negate_cfg_t +{ + ZXIC_UINT32 ppu_cop_crc_bypass_delay_prog_empty_negate_cfg; +}DPP_PPU_PPU_PPU_COP_CRC_BYPASS_DELAY_PROG_EMPTY_NEGATE_CFG_T; + +typedef struct dpp_ppu_ppu_ppu_cop_crc_second_para_fifo_prog_full_assert_cfg_t +{ + ZXIC_UINT32 ppu_cop_crc_second_para_fifo_prog_full_assert_cfg; +}DPP_PPU_PPU_PPU_COP_CRC_SECOND_PARA_FIFO_PROG_FULL_ASSERT_CFG_T; + +typedef struct dpp_ppu_ppu_ppu_cop_crc_second_para_fifo_prog_full_negate_cfg_t +{ + ZXIC_UINT32 ppu_cop_crc_second_para_fifo_prog_full_negate_cfg; +}DPP_PPU_PPU_PPU_COP_CRC_SECOND_PARA_FIFO_PROG_FULL_NEGATE_CFG_T; + +typedef struct dpp_ppu_ppu_ppu_cop_crc_second_para_fifo_prog_empty_assert_cfg_t +{ + ZXIC_UINT32 ppu_cop_crc_second_para_fifo_prog_empty_assert_cfg; +}DPP_PPU_PPU_PPU_COP_CRC_SECOND_PARA_FIFO_PROG_EMPTY_ASSERT_CFG_T; + +typedef struct dpp_ppu_ppu_ppu_cop_crc_second_para_fifo_prog_empty_negate_cfg_t +{ + ZXIC_UINT32 ppu_cop_crc_second_para_fifo_prog_empty_negate_cfg; +}DPP_PPU_PPU_PPU_COP_CRC_SECOND_PARA_FIFO_PROG_EMPTY_NEGATE_CFG_T; + +typedef struct dpp_ppu_ppu_ppu_cop_crc_result_fwft_fifo_prog_full_assert_cfg_t +{ + ZXIC_UINT32 ppu_cop_crc_result_fwft_fifo_prog_full_assert_cfg; +}DPP_PPU_PPU_PPU_COP_CRC_RESULT_FWFT_FIFO_PROG_FULL_ASSERT_CFG_T; + +typedef struct dpp_ppu_ppu_ppu_cop_crc_result_fwft_fifo_prog_full_negate_cfg_t +{ + ZXIC_UINT32 ppu_cop_crc_result_fwft_fifo_prog_full_negate_cfg; +}DPP_PPU_PPU_PPU_COP_CRC_RESULT_FWFT_FIFO_PROG_FULL_NEGATE_CFG_T; + +typedef struct dpp_ppu_ppu_ppu_cop_crc_result_fwft_fifo_prog_empty_assert_cfg_t +{ + ZXIC_UINT32 ppu_cop_crc_result_fwft_fifo_prog_empty_assert_cfg; +}DPP_PPU_PPU_PPU_COP_CRC_RESULT_FWFT_FIFO_PROG_EMPTY_ASSERT_CFG_T; + +typedef struct dpp_ppu_ppu_ppu_cop_crc_result_fwft_fifo_prog_empty_negate_cfg_t +{ + ZXIC_UINT32 ppu_cop_crc_result_fwft_fifo_prog_empty_negate_cfg; +}DPP_PPU_PPU_PPU_COP_CRC_RESULT_FWFT_FIFO_PROG_EMPTY_NEGATE_CFG_T; + +typedef struct dpp_ppu_ppu_ppu_cop_multiply_para_fifo_prog_full_assert_cfg_t +{ + ZXIC_UINT32 ppu_cop_multiply_para_fifo_prog_full_assert_cfg; +}DPP_PPU_PPU_PPU_COP_MULTIPLY_PARA_FIFO_PROG_FULL_ASSERT_CFG_T; + +typedef struct dpp_ppu_ppu_ppu_cop_multiply_para_fifo_prog_full_negate_cfg_t +{ + ZXIC_UINT32 ppu_cop_multiply_para_fifo_prog_full_negate_cfg; +}DPP_PPU_PPU_PPU_COP_MULTIPLY_PARA_FIFO_PROG_FULL_NEGATE_CFG_T; + +typedef struct dpp_ppu_ppu_ppu_cop_multiply_para_fifo_prog_empty_assert_cfg_t +{ + ZXIC_UINT32 ppu_cop_multiply_para_fifo_prog_empty_assert_cfg; +}DPP_PPU_PPU_PPU_COP_MULTIPLY_PARA_FIFO_PROG_EMPTY_ASSERT_CFG_T; + +typedef struct dpp_ppu_ppu_ppu_cop_multiply_para_fifo_prog_empty_negate_cfg_t +{ + ZXIC_UINT32 ppu_cop_multiply_para_fifo_prog_empty_negate_cfg; +}DPP_PPU_PPU_PPU_COP_MULTIPLY_PARA_FIFO_PROG_EMPTY_NEGATE_CFG_T; + +typedef struct dpp_ppu_ppu_ppu_cop_multiply_para_result_fifo_prog_full_assert_cfg_t +{ + ZXIC_UINT32 ppu_cop_multiply_para_result_fifo_prog_full_assert_cfg; +}DPP_PPU_PPU_PPU_COP_MULTIPLY_PARA_RESULT_FIFO_PROG_FULL_ASSERT_CFG_T; + +typedef struct dpp_ppu_ppu_ppu_cop_multiply_para_result_fifo_prog_full_negate_cfg_t +{ + ZXIC_UINT32 ppu_cop_multiply_para_result_fifo_prog_full_negate_cfg; +}DPP_PPU_PPU_PPU_COP_MULTIPLY_PARA_RESULT_FIFO_PROG_FULL_NEGATE_CFG_T; + +typedef struct dpp_ppu_ppu_ppu_cop_multiply_para_result_fifo_prog_empty_assert_cfg_t +{ + ZXIC_UINT32 ppu_cop_multiply_para_result_fifo_prog_empty_assert_cfg; +}DPP_PPU_PPU_PPU_COP_MULTIPLY_PARA_RESULT_FIFO_PROG_EMPTY_ASSERT_CFG_T; + +typedef struct dpp_ppu_ppu_ppu_cop_multiply_para_result_fifo_prog_empty_negate_cfg_t +{ + ZXIC_UINT32 ppu_cop_multiply_para_result_fifo_prog_empty_negate_cfg; +}DPP_PPU_PPU_PPU_COP_MULTIPLY_PARA_RESULT_FIFO_PROG_EMPTY_NEGATE_CFG_T; + +typedef struct dpp_ppu_ppu_free_global_num_fwft_fifo_prog_full_assert_cfg_t +{ + ZXIC_UINT32 free_global_num_fwft_fifo_prog_full_assert_cfg; +}DPP_PPU_PPU_FREE_GLOBAL_NUM_FWFT_FIFO_PROG_FULL_ASSERT_CFG_T; + +typedef struct dpp_ppu_ppu_free_global_num_fwft_fifo_prog_full_negate_cfg_t +{ + ZXIC_UINT32 free_global_num_fwft_fifo_prog_full_negate_cfg; +}DPP_PPU_PPU_FREE_GLOBAL_NUM_FWFT_FIFO_PROG_FULL_NEGATE_CFG_T; + +typedef struct dpp_ppu_ppu_free_global_num_fwft_fifo_prog_empty_assert_cfg_t +{ + ZXIC_UINT32 free_global_num_fwft_fifo_prog_empty_assert_cfg; +}DPP_PPU_PPU_FREE_GLOBAL_NUM_FWFT_FIFO_PROG_EMPTY_ASSERT_CFG_T; + +typedef struct dpp_ppu_ppu_free_global_num_fwft_fifo_prog_empty_negate_cfg_t +{ + ZXIC_UINT32 free_global_num_fwft_fifo_prog_empty_negate_cfg; +}DPP_PPU_PPU_FREE_GLOBAL_NUM_FWFT_FIFO_PROG_EMPTY_NEGATE_CFG_T; + +typedef struct dpp_ppu_ppu_ppu_pktrx_mc_ptr_fifo_prog_full_assert_cfg_t +{ + ZXIC_UINT32 ppu_pktrx_mc_ptr_fifo_prog_full_assert_cfg; +}DPP_PPU_PPU_PPU_PKTRX_MC_PTR_FIFO_PROG_FULL_ASSERT_CFG_T; + +typedef struct dpp_ppu_ppu_ppu_pktrx_mc_ptr_fifo_prog_full_negate_cfg_t +{ + ZXIC_UINT32 ppu_pktrx_mc_ptr_fifo_prog_full_negate_cfg; +}DPP_PPU_PPU_PPU_PKTRX_MC_PTR_FIFO_PROG_FULL_NEGATE_CFG_T; + +typedef struct dpp_ppu_ppu_ppu_pktrx_mc_ptr_fifo_prog_empty_assert_cfg_t +{ + ZXIC_UINT32 ppu_pktrx_mc_ptr_fifo_prog_empty_assert_cfg; +}DPP_PPU_PPU_PPU_PKTRX_MC_PTR_FIFO_PROG_EMPTY_ASSERT_CFG_T; + +typedef struct dpp_ppu_ppu_ppu_pktrx_mc_ptr_fifo_prog_empty_negate_cfg_t +{ + ZXIC_UINT32 ppu_pktrx_mc_ptr_fifo_prog_empty_negate_cfg; +}DPP_PPU_PPU_PPU_PKTRX_MC_PTR_FIFO_PROG_EMPTY_NEGATE_CFG_T; + +typedef struct dpp_ppu_ppu_pkt_data0_t +{ + ZXIC_UINT32 pkt_data0; +}DPP_PPU_PPU_PKT_DATA0_T; + +typedef struct dpp_ppu_ppu_pkt_data1_t +{ + ZXIC_UINT32 pkt_data1; +}DPP_PPU_PPU_PKT_DATA1_T; + +typedef struct dpp_ppu_ppu_pkt_data2_t +{ + ZXIC_UINT32 pkt_data2; +}DPP_PPU_PPU_PKT_DATA2_T; + +typedef struct dpp_ppu_ppu_pkt_data3_t +{ + ZXIC_UINT32 pkt_data3; +}DPP_PPU_PPU_PKT_DATA3_T; + +typedef struct dpp_ppu_ppu_pkt_data4_t +{ + ZXIC_UINT32 pkt_data4; +}DPP_PPU_PPU_PKT_DATA4_T; + +typedef struct dpp_ppu_ppu_pkt_data5_t +{ + ZXIC_UINT32 pkt_data5; +}DPP_PPU_PPU_PKT_DATA5_T; + +typedef struct dpp_ppu_ppu_pkt_data6_t +{ + ZXIC_UINT32 pkt_data6; +}DPP_PPU_PPU_PKT_DATA6_T; + +typedef struct dpp_ppu_ppu_pkt_data7_t +{ + ZXIC_UINT32 pkt_data7; +}DPP_PPU_PPU_PKT_DATA7_T; + +typedef struct dpp_ppu_ppu_pkt_data8_t +{ + ZXIC_UINT32 pkt_data8; +}DPP_PPU_PPU_PKT_DATA8_T; + +typedef struct dpp_ppu_ppu_pkt_data9_t +{ + ZXIC_UINT32 pkt_data9; +}DPP_PPU_PPU_PKT_DATA9_T; + +typedef struct dpp_ppu_ppu_pkt_data10_t +{ + ZXIC_UINT32 pkt_data10; +}DPP_PPU_PPU_PKT_DATA10_T; + +typedef struct dpp_ppu_ppu_pkt_data11_t +{ + ZXIC_UINT32 pkt_data11; +}DPP_PPU_PPU_PKT_DATA11_T; + +typedef struct dpp_ppu_ppu_pkt_data12_t +{ + ZXIC_UINT32 pkt_data12; +}DPP_PPU_PPU_PKT_DATA12_T; + +typedef struct dpp_ppu_ppu_pkt_data13_t +{ + ZXIC_UINT32 pkt_data13; +}DPP_PPU_PPU_PKT_DATA13_T; + +typedef struct dpp_ppu_ppu_pkt_data14_t +{ + ZXIC_UINT32 pkt_data14; +}DPP_PPU_PPU_PKT_DATA14_T; + +typedef struct dpp_ppu_ppu_pkt_data15_t +{ + ZXIC_UINT32 pkt_data15; +}DPP_PPU_PPU_PKT_DATA15_T; + +typedef struct dpp_ppu_ppu_pkt_data16_t +{ + ZXIC_UINT32 pkt_data16; +}DPP_PPU_PPU_PKT_DATA16_T; + +typedef struct dpp_ppu_ppu_pkt_data17_t +{ + ZXIC_UINT32 pkt_data17; +}DPP_PPU_PPU_PKT_DATA17_T; + +typedef struct dpp_ppu_ppu_pkt_data18_t +{ + ZXIC_UINT32 pkt_data18; +}DPP_PPU_PPU_PKT_DATA18_T; + +typedef struct dpp_ppu_ppu_pkt_data19_t +{ + ZXIC_UINT32 pkt_data19; +}DPP_PPU_PPU_PKT_DATA19_T; + +typedef struct dpp_ppu_ppu_pkt_data20_t +{ + ZXIC_UINT32 pkt_data20; +}DPP_PPU_PPU_PKT_DATA20_T; + +typedef struct dpp_ppu_ppu_pkt_data21_t +{ + ZXIC_UINT32 pkt_data21; +}DPP_PPU_PPU_PKT_DATA21_T; + +typedef struct dpp_ppu_ppu_pkt_data22_t +{ + ZXIC_UINT32 pkt_data22; +}DPP_PPU_PPU_PKT_DATA22_T; + +typedef struct dpp_ppu_ppu_pkt_data23_t +{ + ZXIC_UINT32 pkt_data23; +}DPP_PPU_PPU_PKT_DATA23_T; + +typedef struct dpp_ppu_ppu_pkt_data24_t +{ + ZXIC_UINT32 pkt_data24; +}DPP_PPU_PPU_PKT_DATA24_T; + +typedef struct dpp_ppu_ppu_pkt_data25_t +{ + ZXIC_UINT32 pkt_data25; +}DPP_PPU_PPU_PKT_DATA25_T; + +typedef struct dpp_ppu_ppu_pkt_data26_t +{ + ZXIC_UINT32 pkt_data26; +}DPP_PPU_PPU_PKT_DATA26_T; + +typedef struct dpp_ppu_ppu_pkt_data27_t +{ + ZXIC_UINT32 pkt_data27; +}DPP_PPU_PPU_PKT_DATA27_T; + +typedef struct dpp_ppu_ppu_pkt_data28_t +{ + ZXIC_UINT32 pkt_data28; +}DPP_PPU_PPU_PKT_DATA28_T; + +typedef struct dpp_ppu_ppu_pkt_data29_t +{ + ZXIC_UINT32 pkt_data29; +}DPP_PPU_PPU_PKT_DATA29_T; + +typedef struct dpp_ppu_ppu_pkt_data30_t +{ + ZXIC_UINT32 pkt_data30; +}DPP_PPU_PPU_PKT_DATA30_T; + +typedef struct dpp_ppu_ppu_pkt_data31_t +{ + ZXIC_UINT32 pkt_data31; +}DPP_PPU_PPU_PKT_DATA31_T; + +typedef struct dpp_ppu_ppu_pkt_data32_t +{ + ZXIC_UINT32 pkt_data32; +}DPP_PPU_PPU_PKT_DATA32_T; + +typedef struct dpp_ppu_ppu_pkt_data33_t +{ + ZXIC_UINT32 pkt_data33; +}DPP_PPU_PPU_PKT_DATA33_T; + +typedef struct dpp_ppu_ppu_pkt_data34_t +{ + ZXIC_UINT32 pkt_data34; +}DPP_PPU_PPU_PKT_DATA34_T; + +typedef struct dpp_ppu_ppu_pkt_data35_t +{ + ZXIC_UINT32 pkt_data35; +}DPP_PPU_PPU_PKT_DATA35_T; + +typedef struct dpp_ppu_ppu_pkt_data36_t +{ + ZXIC_UINT32 pkt_data36; +}DPP_PPU_PPU_PKT_DATA36_T; + +typedef struct dpp_ppu_ppu_pkt_data37_t +{ + ZXIC_UINT32 pkt_data37; +}DPP_PPU_PPU_PKT_DATA37_T; + +typedef struct dpp_ppu_ppu_pkt_data38_t +{ + ZXIC_UINT32 pkt_data38; +}DPP_PPU_PPU_PKT_DATA38_T; + +typedef struct dpp_ppu_ppu_pkt_data39_t +{ + ZXIC_UINT32 pkt_data39; +}DPP_PPU_PPU_PKT_DATA39_T; + +typedef struct dpp_ppu_ppu_pkt_data40_t +{ + ZXIC_UINT32 pkt_data40; +}DPP_PPU_PPU_PKT_DATA40_T; + +typedef struct dpp_ppu_ppu_pkt_data41_t +{ + ZXIC_UINT32 pkt_data41; +}DPP_PPU_PPU_PKT_DATA41_T; + +typedef struct dpp_ppu_ppu_pkt_data42_t +{ + ZXIC_UINT32 pkt_data42; +}DPP_PPU_PPU_PKT_DATA42_T; + +typedef struct dpp_ppu_ppu_pkt_data43_t +{ + ZXIC_UINT32 pkt_data43; +}DPP_PPU_PPU_PKT_DATA43_T; + +typedef struct dpp_ppu_ppu_pkt_data44_t +{ + ZXIC_UINT32 pkt_data44; +}DPP_PPU_PPU_PKT_DATA44_T; + +typedef struct dpp_ppu_ppu_pkt_data45_t +{ + ZXIC_UINT32 pkt_data45; +}DPP_PPU_PPU_PKT_DATA45_T; + +typedef struct dpp_ppu_ppu_pkt_data46_t +{ + ZXIC_UINT32 pkt_data46; +}DPP_PPU_PPU_PKT_DATA46_T; + +typedef struct dpp_ppu_ppu_pkt_data47_t +{ + ZXIC_UINT32 pkt_data47; +}DPP_PPU_PPU_PKT_DATA47_T; + +typedef struct dpp_ppu_ppu_pkt_data48_t +{ + ZXIC_UINT32 pkt_data48; +}DPP_PPU_PPU_PKT_DATA48_T; + +typedef struct dpp_ppu_ppu_pkt_data49_t +{ + ZXIC_UINT32 pkt_data49; +}DPP_PPU_PPU_PKT_DATA49_T; + +typedef struct dpp_ppu_ppu_pkt_data50_t +{ + ZXIC_UINT32 pkt_data50; +}DPP_PPU_PPU_PKT_DATA50_T; + +typedef struct dpp_ppu_ppu_pkt_data51_t +{ + ZXIC_UINT32 pkt_data51; +}DPP_PPU_PPU_PKT_DATA51_T; + +typedef struct dpp_ppu_ppu_pkt_data52_t +{ + ZXIC_UINT32 pkt_data52; +}DPP_PPU_PPU_PKT_DATA52_T; + +typedef struct dpp_ppu_ppu_pkt_data53_t +{ + ZXIC_UINT32 pkt_data53; +}DPP_PPU_PPU_PKT_DATA53_T; + +typedef struct dpp_ppu_ppu_pkt_data54_t +{ + ZXIC_UINT32 pkt_data54; +}DPP_PPU_PPU_PKT_DATA54_T; + +typedef struct dpp_ppu_ppu_pkt_data55_t +{ + ZXIC_UINT32 pkt_data55; +}DPP_PPU_PPU_PKT_DATA55_T; + +typedef struct dpp_ppu_ppu_pkt_data56_t +{ + ZXIC_UINT32 pkt_data56; +}DPP_PPU_PPU_PKT_DATA56_T; + +typedef struct dpp_ppu_ppu_pkt_data57_t +{ + ZXIC_UINT32 pkt_data57; +}DPP_PPU_PPU_PKT_DATA57_T; + +typedef struct dpp_ppu_ppu_pkt_data58_t +{ + ZXIC_UINT32 pkt_data58; +}DPP_PPU_PPU_PKT_DATA58_T; + +typedef struct dpp_ppu_ppu_pkt_data59_t +{ + ZXIC_UINT32 pkt_data59; +}DPP_PPU_PPU_PKT_DATA59_T; + +typedef struct dpp_ppu_ppu_pkt_data60_t +{ + ZXIC_UINT32 pkt_data60; +}DPP_PPU_PPU_PKT_DATA60_T; + +typedef struct dpp_ppu_ppu_pkt_data61_t +{ + ZXIC_UINT32 pkt_data61; +}DPP_PPU_PPU_PKT_DATA61_T; + +typedef struct dpp_ppu_ppu_pkt_data62_t +{ + ZXIC_UINT32 pkt_data62; +}DPP_PPU_PPU_PKT_DATA62_T; + +typedef struct dpp_ppu_ppu_pkt_data63_t +{ + ZXIC_UINT32 pkt_data63; +}DPP_PPU_PPU_PKT_DATA63_T; + +typedef struct dpp_ppu_ppu_pkt_data64_t +{ + ZXIC_UINT32 pkt_data64; +}DPP_PPU_PPU_PKT_DATA64_T; + +typedef struct dpp_ppu_ppu_pkt_data65_t +{ + ZXIC_UINT32 pkt_data65; +}DPP_PPU_PPU_PKT_DATA65_T; + +typedef struct dpp_ppu_ppu_pkt_data66_t +{ + ZXIC_UINT32 pkt_data66; +}DPP_PPU_PPU_PKT_DATA66_T; + +typedef struct dpp_ppu_ppu_pkt_data67_t +{ + ZXIC_UINT32 pkt_data67; +}DPP_PPU_PPU_PKT_DATA67_T; + +typedef struct dpp_ppu_ppu_pkt_data68_t +{ + ZXIC_UINT32 pkt_data68; +}DPP_PPU_PPU_PKT_DATA68_T; + +typedef struct dpp_ppu_ppu_pkt_data69_t +{ + ZXIC_UINT32 pkt_data69; +}DPP_PPU_PPU_PKT_DATA69_T; + +typedef struct dpp_ppu_ppu_pkt_data70_t +{ + ZXIC_UINT32 pkt_data70; +}DPP_PPU_PPU_PKT_DATA70_T; + +typedef struct dpp_ppu_ppu_pkt_data71_t +{ + ZXIC_UINT32 pkt_data71; +}DPP_PPU_PPU_PKT_DATA71_T; + +typedef struct dpp_ppu_ppu_pkt_data72_t +{ + ZXIC_UINT32 pkt_data72; +}DPP_PPU_PPU_PKT_DATA72_T; + +typedef struct dpp_ppu_ppu_pkt_data73_t +{ + ZXIC_UINT32 pkt_data73; +}DPP_PPU_PPU_PKT_DATA73_T; + +typedef struct dpp_ppu_ppu_pkt_data74_t +{ + ZXIC_UINT32 pkt_data74; +}DPP_PPU_PPU_PKT_DATA74_T; + +typedef struct dpp_ppu_ppu_pkt_data75_t +{ + ZXIC_UINT32 pkt_data75; +}DPP_PPU_PPU_PKT_DATA75_T; + +typedef struct dpp_ppu_ppu_pkt_data76_t +{ + ZXIC_UINT32 pkt_data76; +}DPP_PPU_PPU_PKT_DATA76_T; + +typedef struct dpp_ppu_ppu_pkt_data77_t +{ + ZXIC_UINT32 pkt_data77; +}DPP_PPU_PPU_PKT_DATA77_T; + +typedef struct dpp_ppu_ppu_pkt_data78_t +{ + ZXIC_UINT32 pkt_data78; +}DPP_PPU_PPU_PKT_DATA78_T; + +typedef struct dpp_ppu_ppu_pkt_data79_t +{ + ZXIC_UINT32 pkt_data79; +}DPP_PPU_PPU_PKT_DATA79_T; + +typedef struct dpp_ppu_ppu_pkt_data80_t +{ + ZXIC_UINT32 pkt_data80; +}DPP_PPU_PPU_PKT_DATA80_T; + +typedef struct dpp_ppu_ppu_pkt_data81_t +{ + ZXIC_UINT32 pkt_data81; +}DPP_PPU_PPU_PKT_DATA81_T; + +typedef struct dpp_ppu_ppu_pkt_data82_t +{ + ZXIC_UINT32 pkt_data82; +}DPP_PPU_PPU_PKT_DATA82_T; + +typedef struct dpp_ppu_ppu_pkt_data83_t +{ + ZXIC_UINT32 pkt_data83; +}DPP_PPU_PPU_PKT_DATA83_T; + +typedef struct dpp_ppu_ppu_pkt_data84_t +{ + ZXIC_UINT32 pkt_data84; +}DPP_PPU_PPU_PKT_DATA84_T; + +typedef struct dpp_ppu_ppu_pkt_data85_t +{ + ZXIC_UINT32 pkt_data85; +}DPP_PPU_PPU_PKT_DATA85_T; + +typedef struct dpp_ppu_ppu_pkt_data86_t +{ + ZXIC_UINT32 pkt_data86; +}DPP_PPU_PPU_PKT_DATA86_T; + +typedef struct dpp_ppu_ppu_pkt_data87_t +{ + ZXIC_UINT32 pkt_data87; +}DPP_PPU_PPU_PKT_DATA87_T; + +typedef struct dpp_ppu_ppu_pkt_data88_t +{ + ZXIC_UINT32 pkt_data88; +}DPP_PPU_PPU_PKT_DATA88_T; + +typedef struct dpp_ppu_ppu_pkt_data89_t +{ + ZXIC_UINT32 pkt_data89; +}DPP_PPU_PPU_PKT_DATA89_T; + +typedef struct dpp_ppu_ppu_pkt_data90_t +{ + ZXIC_UINT32 pkt_data90; +}DPP_PPU_PPU_PKT_DATA90_T; + +typedef struct dpp_ppu_ppu_pkt_data91_t +{ + ZXIC_UINT32 pkt_data91; +}DPP_PPU_PPU_PKT_DATA91_T; + +typedef struct dpp_ppu_ppu_pkt_data92_t +{ + ZXIC_UINT32 pkt_data92; +}DPP_PPU_PPU_PKT_DATA92_T; + +typedef struct dpp_ppu_ppu_pkt_data93_t +{ + ZXIC_UINT32 pkt_data93; +}DPP_PPU_PPU_PKT_DATA93_T; + +typedef struct dpp_ppu_ppu_pkt_data94_t +{ + ZXIC_UINT32 pkt_data94; +}DPP_PPU_PPU_PKT_DATA94_T; + +typedef struct dpp_ppu_ppu_pkt_data95_t +{ + ZXIC_UINT32 pkt_data95; +}DPP_PPU_PPU_PKT_DATA95_T; + +typedef struct dpp_ppu_ppu_pkt_data96_t +{ + ZXIC_UINT32 pkt_data96; +}DPP_PPU_PPU_PKT_DATA96_T; + +typedef struct dpp_ppu_ppu_pkt_data97_t +{ + ZXIC_UINT32 pkt_data97; +}DPP_PPU_PPU_PKT_DATA97_T; + +typedef struct dpp_ppu_ppu_pkt_data98_t +{ + ZXIC_UINT32 pkt_data98; +}DPP_PPU_PPU_PKT_DATA98_T; + +typedef struct dpp_ppu_ppu_pkt_data99_t +{ + ZXIC_UINT32 pkt_data99; +}DPP_PPU_PPU_PKT_DATA99_T; + +typedef struct dpp_ppu_ppu_pkt_data100_t +{ + ZXIC_UINT32 pkt_data100; +}DPP_PPU_PPU_PKT_DATA100_T; + +typedef struct dpp_ppu_ppu_pkt_data101_t +{ + ZXIC_UINT32 pkt_data101; +}DPP_PPU_PPU_PKT_DATA101_T; + +typedef struct dpp_ppu_ppu_pkt_data102_t +{ + ZXIC_UINT32 pkt_data102; +}DPP_PPU_PPU_PKT_DATA102_T; + +typedef struct dpp_ppu_ppu_pkt_data103_t +{ + ZXIC_UINT32 pkt_data103; +}DPP_PPU_PPU_PKT_DATA103_T; + +typedef struct dpp_ppu_ppu_pkt_data104_t +{ + ZXIC_UINT32 pkt_data104; +}DPP_PPU_PPU_PKT_DATA104_T; + +typedef struct dpp_ppu_ppu_pkt_data105_t +{ + ZXIC_UINT32 pkt_data105; +}DPP_PPU_PPU_PKT_DATA105_T; + +typedef struct dpp_ppu_ppu_pkt_data106_t +{ + ZXIC_UINT32 pkt_data106; +}DPP_PPU_PPU_PKT_DATA106_T; + +typedef struct dpp_ppu_ppu_pkt_data107_t +{ + ZXIC_UINT32 pkt_data107; +}DPP_PPU_PPU_PKT_DATA107_T; + +typedef struct dpp_ppu_ppu_pkt_data108_t +{ + ZXIC_UINT32 pkt_data108; +}DPP_PPU_PPU_PKT_DATA108_T; + +typedef struct dpp_ppu_ppu_pkt_data109_t +{ + ZXIC_UINT32 pkt_data109; +}DPP_PPU_PPU_PKT_DATA109_T; + +typedef struct dpp_ppu_ppu_pkt_data110_t +{ + ZXIC_UINT32 pkt_data110; +}DPP_PPU_PPU_PKT_DATA110_T; + +typedef struct dpp_ppu_ppu_pkt_data111_t +{ + ZXIC_UINT32 pkt_data111; +}DPP_PPU_PPU_PKT_DATA111_T; + +typedef struct dpp_ppu_ppu_pkt_data112_t +{ + ZXIC_UINT32 pkt_data112; +}DPP_PPU_PPU_PKT_DATA112_T; + +typedef struct dpp_ppu_ppu_pkt_data113_t +{ + ZXIC_UINT32 pkt_data113; +}DPP_PPU_PPU_PKT_DATA113_T; + +typedef struct dpp_ppu_ppu_pkt_data114_t +{ + ZXIC_UINT32 pkt_data114; +}DPP_PPU_PPU_PKT_DATA114_T; + +typedef struct dpp_ppu_ppu_pkt_data115_t +{ + ZXIC_UINT32 pkt_data115; +}DPP_PPU_PPU_PKT_DATA115_T; + +typedef struct dpp_ppu_ppu_pkt_data116_t +{ + ZXIC_UINT32 pkt_data116; +}DPP_PPU_PPU_PKT_DATA116_T; + +typedef struct dpp_ppu_ppu_pkt_data117_t +{ + ZXIC_UINT32 pkt_data117; +}DPP_PPU_PPU_PKT_DATA117_T; + +typedef struct dpp_ppu_ppu_pkt_data118_t +{ + ZXIC_UINT32 pkt_data118; +}DPP_PPU_PPU_PKT_DATA118_T; + +typedef struct dpp_ppu_ppu_pkt_data119_t +{ + ZXIC_UINT32 pkt_data119; +}DPP_PPU_PPU_PKT_DATA119_T; + +typedef struct dpp_ppu_ppu_pkt_data120_t +{ + ZXIC_UINT32 pkt_data120; +}DPP_PPU_PPU_PKT_DATA120_T; + +typedef struct dpp_ppu_ppu_pkt_data121_t +{ + ZXIC_UINT32 pkt_data121; +}DPP_PPU_PPU_PKT_DATA121_T; + +typedef struct dpp_ppu_ppu_pkt_data122_t +{ + ZXIC_UINT32 pkt_data122; +}DPP_PPU_PPU_PKT_DATA122_T; + +typedef struct dpp_ppu_ppu_pkt_data123_t +{ + ZXIC_UINT32 pkt_data123; +}DPP_PPU_PPU_PKT_DATA123_T; + +typedef struct dpp_ppu_ppu_pkt_data124_t +{ + ZXIC_UINT32 pkt_data124; +}DPP_PPU_PPU_PKT_DATA124_T; + +typedef struct dpp_ppu_ppu_pkt_data125_t +{ + ZXIC_UINT32 pkt_data125; +}DPP_PPU_PPU_PKT_DATA125_T; + +typedef struct dpp_ppu_ppu_pkt_data126_t +{ + ZXIC_UINT32 pkt_data126; +}DPP_PPU_PPU_PKT_DATA126_T; + +typedef struct dpp_ppu_ppu_pkt_data127_t +{ + ZXIC_UINT32 pkt_data127; +}DPP_PPU_PPU_PKT_DATA127_T; + +typedef struct dpp_ppu_ppu_spr0_t +{ + ZXIC_UINT32 spr0; +}DPP_PPU_PPU_SPR0_T; + +typedef struct dpp_ppu_ppu_spr1_t +{ + ZXIC_UINT32 spr1; +}DPP_PPU_PPU_SPR1_T; + +typedef struct dpp_ppu_ppu_spr2_t +{ + ZXIC_UINT32 spr2; +}DPP_PPU_PPU_SPR2_T; + +typedef struct dpp_ppu_ppu_spr3_t +{ + ZXIC_UINT32 spr3; +}DPP_PPU_PPU_SPR3_T; + +typedef struct dpp_ppu_ppu_spr4_t +{ + ZXIC_UINT32 spr4; +}DPP_PPU_PPU_SPR4_T; + +typedef struct dpp_ppu_ppu_spr5_t +{ + ZXIC_UINT32 spr5; +}DPP_PPU_PPU_SPR5_T; + +typedef struct dpp_ppu_ppu_spr6_t +{ + ZXIC_UINT32 spr6; +}DPP_PPU_PPU_SPR6_T; + +typedef struct dpp_ppu_ppu_spr7_t +{ + ZXIC_UINT32 spr7; +}DPP_PPU_PPU_SPR7_T; + +typedef struct dpp_ppu_ppu_spr8_t +{ + ZXIC_UINT32 spr8; +}DPP_PPU_PPU_SPR8_T; + +typedef struct dpp_ppu_ppu_spr9_t +{ + ZXIC_UINT32 spr9; +}DPP_PPU_PPU_SPR9_T; + +typedef struct dpp_ppu_ppu_spr10_t +{ + ZXIC_UINT32 spr10; +}DPP_PPU_PPU_SPR10_T; + +typedef struct dpp_ppu_ppu_spr11_t +{ + ZXIC_UINT32 spr11; +}DPP_PPU_PPU_SPR11_T; + +typedef struct dpp_ppu_ppu_spr12_t +{ + ZXIC_UINT32 spr12; +}DPP_PPU_PPU_SPR12_T; + +typedef struct dpp_ppu_ppu_spr13_t +{ + ZXIC_UINT32 spr13; +}DPP_PPU_PPU_SPR13_T; + +typedef struct dpp_ppu_ppu_spr14_t +{ + ZXIC_UINT32 spr14; +}DPP_PPU_PPU_SPR14_T; + +typedef struct dpp_ppu_ppu_spr15_t +{ + ZXIC_UINT32 spr15; +}DPP_PPU_PPU_SPR15_T; + +typedef struct dpp_ppu_ppu_spr16_t +{ + ZXIC_UINT32 spr16; +}DPP_PPU_PPU_SPR16_T; + +typedef struct dpp_ppu_ppu_spr17_t +{ + ZXIC_UINT32 spr17; +}DPP_PPU_PPU_SPR17_T; + +typedef struct dpp_ppu_ppu_spr18_t +{ + ZXIC_UINT32 spr18; +}DPP_PPU_PPU_SPR18_T; + +typedef struct dpp_ppu_ppu_spr19_t +{ + ZXIC_UINT32 spr19; +}DPP_PPU_PPU_SPR19_T; + +typedef struct dpp_ppu_ppu_spr20_t +{ + ZXIC_UINT32 spr20; +}DPP_PPU_PPU_SPR20_T; + +typedef struct dpp_ppu_ppu_spr21_t +{ + ZXIC_UINT32 spr21; +}DPP_PPU_PPU_SPR21_T; + +typedef struct dpp_ppu_ppu_spr22_t +{ + ZXIC_UINT32 spr22; +}DPP_PPU_PPU_SPR22_T; + +typedef struct dpp_ppu_ppu_spr23_t +{ + ZXIC_UINT32 spr23; +}DPP_PPU_PPU_SPR23_T; + +typedef struct dpp_ppu_ppu_spr24_t +{ + ZXIC_UINT32 spr24; +}DPP_PPU_PPU_SPR24_T; + +typedef struct dpp_ppu_ppu_spr25_t +{ + ZXIC_UINT32 spr25; +}DPP_PPU_PPU_SPR25_T; + +typedef struct dpp_ppu_ppu_spr26_t +{ + ZXIC_UINT32 spr26; +}DPP_PPU_PPU_SPR26_T; + +typedef struct dpp_ppu_ppu_spr27_t +{ + ZXIC_UINT32 spr27; +}DPP_PPU_PPU_SPR27_T; + +typedef struct dpp_ppu_ppu_spr28_t +{ + ZXIC_UINT32 spr28; +}DPP_PPU_PPU_SPR28_T; + +typedef struct dpp_ppu_ppu_spr29_t +{ + ZXIC_UINT32 spr29; +}DPP_PPU_PPU_SPR29_T; + +typedef struct dpp_ppu_ppu_spr30_t +{ + ZXIC_UINT32 spr30; +}DPP_PPU_PPU_SPR30_T; + +typedef struct dpp_ppu_ppu_spr31_t +{ + ZXIC_UINT32 spr31; +}DPP_PPU_PPU_SPR31_T; + +typedef struct dpp_ppu_ppu_rsp0_t +{ + ZXIC_UINT32 rsp0; +}DPP_PPU_PPU_RSP0_T; + +typedef struct dpp_ppu_ppu_rsp1_t +{ + ZXIC_UINT32 rsp1; +}DPP_PPU_PPU_RSP1_T; + +typedef struct dpp_ppu_ppu_rsp2_t +{ + ZXIC_UINT32 rsp2; +}DPP_PPU_PPU_RSP2_T; + +typedef struct dpp_ppu_ppu_rsp3_t +{ + ZXIC_UINT32 rsp3; +}DPP_PPU_PPU_RSP3_T; + +typedef struct dpp_ppu_ppu_rsp4_t +{ + ZXIC_UINT32 rsp4; +}DPP_PPU_PPU_RSP4_T; + +typedef struct dpp_ppu_ppu_rsp5_t +{ + ZXIC_UINT32 rsp5; +}DPP_PPU_PPU_RSP5_T; + +typedef struct dpp_ppu_ppu_rsp6_t +{ + ZXIC_UINT32 rsp6; +}DPP_PPU_PPU_RSP6_T; + +typedef struct dpp_ppu_ppu_rsp7_t +{ + ZXIC_UINT32 rsp7; +}DPP_PPU_PPU_RSP7_T; + +typedef struct dpp_ppu_ppu_rsp8_t +{ + ZXIC_UINT32 rsp8; +}DPP_PPU_PPU_RSP8_T; + +typedef struct dpp_ppu_ppu_rsp9_t +{ + ZXIC_UINT32 rsp9; +}DPP_PPU_PPU_RSP9_T; + +typedef struct dpp_ppu_ppu_rsp10_t +{ + ZXIC_UINT32 rsp10; +}DPP_PPU_PPU_RSP10_T; + +typedef struct dpp_ppu_ppu_rsp11_t +{ + ZXIC_UINT32 rsp11; +}DPP_PPU_PPU_RSP11_T; + +typedef struct dpp_ppu_ppu_rsp12_t +{ + ZXIC_UINT32 rsp12; +}DPP_PPU_PPU_RSP12_T; + +typedef struct dpp_ppu_ppu_rsp13_t +{ + ZXIC_UINT32 rsp13; +}DPP_PPU_PPU_RSP13_T; + +typedef struct dpp_ppu_ppu_rsp14_t +{ + ZXIC_UINT32 rsp14; +}DPP_PPU_PPU_RSP14_T; + +typedef struct dpp_ppu_ppu_rsp15_t +{ + ZXIC_UINT32 rsp15; +}DPP_PPU_PPU_RSP15_T; + +typedef struct dpp_ppu_ppu_rsp16_t +{ + ZXIC_UINT32 rsp16; +}DPP_PPU_PPU_RSP16_T; + +typedef struct dpp_ppu_ppu_rsp17_t +{ + ZXIC_UINT32 rsp17; +}DPP_PPU_PPU_RSP17_T; + +typedef struct dpp_ppu_ppu_rsp18_t +{ + ZXIC_UINT32 rsp18; +}DPP_PPU_PPU_RSP18_T; + +typedef struct dpp_ppu_ppu_rsp19_t +{ + ZXIC_UINT32 rsp19; +}DPP_PPU_PPU_RSP19_T; + +typedef struct dpp_ppu_ppu_rsp20_t +{ + ZXIC_UINT32 rsp20; +}DPP_PPU_PPU_RSP20_T; + +typedef struct dpp_ppu_ppu_rsp21_t +{ + ZXIC_UINT32 rsp21; +}DPP_PPU_PPU_RSP21_T; + +typedef struct dpp_ppu_ppu_rsp22_t +{ + ZXIC_UINT32 rsp22; +}DPP_PPU_PPU_RSP22_T; + +typedef struct dpp_ppu_ppu_rsp23_t +{ + ZXIC_UINT32 rsp23; +}DPP_PPU_PPU_RSP23_T; + +typedef struct dpp_ppu_ppu_rsp24_t +{ + ZXIC_UINT32 rsp24; +}DPP_PPU_PPU_RSP24_T; + +typedef struct dpp_ppu_ppu_rsp25_t +{ + ZXIC_UINT32 rsp25; +}DPP_PPU_PPU_RSP25_T; + +typedef struct dpp_ppu_ppu_rsp26_t +{ + ZXIC_UINT32 rsp26; +}DPP_PPU_PPU_RSP26_T; + +typedef struct dpp_ppu_ppu_rsp27_t +{ + ZXIC_UINT32 rsp27; +}DPP_PPU_PPU_RSP27_T; + +typedef struct dpp_ppu_ppu_rsp28_t +{ + ZXIC_UINT32 rsp28; +}DPP_PPU_PPU_RSP28_T; + +typedef struct dpp_ppu_ppu_rsp29_t +{ + ZXIC_UINT32 rsp29; +}DPP_PPU_PPU_RSP29_T; + +typedef struct dpp_ppu_ppu_rsp30_t +{ + ZXIC_UINT32 rsp30; +}DPP_PPU_PPU_RSP30_T; + +typedef struct dpp_ppu_ppu_rsp31_t +{ + ZXIC_UINT32 rsp31; +}DPP_PPU_PPU_RSP31_T; + +typedef struct dpp_ppu_ppu_key0_t +{ + ZXIC_UINT32 key0; +}DPP_PPU_PPU_KEY0_T; + +typedef struct dpp_ppu_ppu_key1_t +{ + ZXIC_UINT32 key1; +}DPP_PPU_PPU_KEY1_T; + +typedef struct dpp_ppu_ppu_key2_t +{ + ZXIC_UINT32 key2; +}DPP_PPU_PPU_KEY2_T; + +typedef struct dpp_ppu_ppu_key3_t +{ + ZXIC_UINT32 key3; +}DPP_PPU_PPU_KEY3_T; + +typedef struct dpp_ppu_ppu_key4_t +{ + ZXIC_UINT32 key4; +}DPP_PPU_PPU_KEY4_T; + +typedef struct dpp_ppu_ppu_key5_t +{ + ZXIC_UINT32 key5; +}DPP_PPU_PPU_KEY5_T; + +typedef struct dpp_ppu_ppu_key6_t +{ + ZXIC_UINT32 key6; +}DPP_PPU_PPU_KEY6_T; + +typedef struct dpp_ppu_ppu_key7_t +{ + ZXIC_UINT32 key7; +}DPP_PPU_PPU_KEY7_T; + +typedef struct dpp_ppu_ppu_key8_t +{ + ZXIC_UINT32 key8; +}DPP_PPU_PPU_KEY8_T; + +typedef struct dpp_ppu_ppu_key9_t +{ + ZXIC_UINT32 key9; +}DPP_PPU_PPU_KEY9_T; + +typedef struct dpp_ppu_ppu_key10_t +{ + ZXIC_UINT32 key10; +}DPP_PPU_PPU_KEY10_T; + +typedef struct dpp_ppu_ppu_key11_t +{ + ZXIC_UINT32 key11; +}DPP_PPU_PPU_KEY11_T; + +typedef struct dpp_ppu_ppu_key12_t +{ + ZXIC_UINT32 key12; +}DPP_PPU_PPU_KEY12_T; + +typedef struct dpp_ppu_ppu_key13_t +{ + ZXIC_UINT32 key13; +}DPP_PPU_PPU_KEY13_T; + +typedef struct dpp_ppu_ppu_key14_t +{ + ZXIC_UINT32 key14; +}DPP_PPU_PPU_KEY14_T; + +typedef struct dpp_ppu_ppu_key15_t +{ + ZXIC_UINT32 key15; +}DPP_PPU_PPU_KEY15_T; + +typedef struct dpp_ppu_ppu_key16_t +{ + ZXIC_UINT32 key16; +}DPP_PPU_PPU_KEY16_T; + +typedef struct dpp_ppu_ppu_key17_t +{ + ZXIC_UINT32 key17; +}DPP_PPU_PPU_KEY17_T; + +typedef struct dpp_ppu_ppu_key18_t +{ + ZXIC_UINT32 key18; +}DPP_PPU_PPU_KEY18_T; + +typedef struct dpp_ppu_ppu_key19_t +{ + ZXIC_UINT32 key19; +}DPP_PPU_PPU_KEY19_T; + +typedef struct dpp_ppu_ppu_flag_t +{ + ZXIC_UINT32 me_num; + ZXIC_UINT32 thread_num; + ZXIC_UINT32 flag; +}DPP_PPU_PPU_FLAG_T; + +typedef struct dpp_ppu_cluster_int_1200m_flag_t +{ + ZXIC_UINT32 me7_interrupt_flag; + ZXIC_UINT32 me6_interrupt_flag; + ZXIC_UINT32 me5_interrupt_flag; + ZXIC_UINT32 me4_interrupt_flag; + ZXIC_UINT32 me3_interrupt_flag; + ZXIC_UINT32 me2_interrupt_flag; + ZXIC_UINT32 me1_interrupt_flag; + ZXIC_UINT32 me0_interrupt_flag; +}DPP_PPU_CLUSTER_INT_1200M_FLAG_T; + +typedef struct dpp_ppu_cluster_bp_instr_l_t +{ + ZXIC_UINT32 bp_instr_l; +}DPP_PPU_CLUSTER_BP_INSTR_L_T; + +typedef struct dpp_ppu_cluster_bp_instr_h_t +{ + ZXIC_UINT32 bp_instr_h; +}DPP_PPU_CLUSTER_BP_INSTR_H_T; + +typedef struct dpp_ppu_cluster_bp_addr_t +{ + ZXIC_UINT32 bp_addr; +}DPP_PPU_CLUSTER_BP_ADDR_T; + +typedef struct dpp_ppu_cluster_drr_t +{ + ZXIC_UINT32 drr; +}DPP_PPU_CLUSTER_DRR_T; + +typedef struct dpp_ppu_cluster_dsr_t +{ + ZXIC_UINT32 dsr; +}DPP_PPU_CLUSTER_DSR_T; + +typedef struct dpp_ppu_cluster_dbg_rtl_date_t +{ + ZXIC_UINT32 dbg_rtl_date; +}DPP_PPU_CLUSTER_DBG_RTL_DATE_T; + +typedef struct dpp_ppu_cluster_me_continue_t +{ + ZXIC_UINT32 me_continue; +}DPP_PPU_CLUSTER_ME_CONTINUE_T; + +typedef struct dpp_ppu_cluster_me_step_t +{ + ZXIC_UINT32 me_step; +}DPP_PPU_CLUSTER_ME_STEP_T; + +typedef struct dpp_ppu_cluster_me_refresh_t +{ + ZXIC_UINT32 me_refresh; +}DPP_PPU_CLUSTER_ME_REFRESH_T; + +typedef struct dpp_ppu_cluster_drr_clr_t +{ + ZXIC_UINT32 drr_clr; +}DPP_PPU_CLUSTER_DRR_CLR_T; + +typedef struct dpp_ppu_cluster_me_busy_thresold_t +{ + ZXIC_UINT32 me_busy_thresold; +}DPP_PPU_CLUSTER_ME_BUSY_THRESOLD_T; + +typedef struct dpp_ppu_cluster_int_1200m_sta_t +{ + ZXIC_UINT32 me7_interrupt_sta; + ZXIC_UINT32 me6_interrupt_sta; + ZXIC_UINT32 me5_interrupt_sta; + ZXIC_UINT32 me4_interrupt_sta; + ZXIC_UINT32 me3_interrupt_sta; + ZXIC_UINT32 me2_interrupt_sta; + ZXIC_UINT32 me1_interrupt_sta; + ZXIC_UINT32 me0_interrupt_sta; +}DPP_PPU_CLUSTER_INT_1200M_STA_T; + +typedef struct dpp_ppu_cluster_int_1200m_me_fifo_mask_l_t +{ + ZXIC_UINT32 me_free_pkt_q_overflow_mask; + ZXIC_UINT32 me_free_pkt_q_underflow_mask; + ZXIC_UINT32 me_free_thread_q_overflow_mask; + ZXIC_UINT32 me_free_thread_q_underflow_mask; + ZXIC_UINT32 me_pkt_in_overflow_mask; + ZXIC_UINT32 me_pkt_in_underflow_mask; + ZXIC_UINT32 me_rdy_q_overflow_mask; + ZXIC_UINT32 me_rdy_q_underflow_mask; + ZXIC_UINT32 me_pkt_out_q_overflow_mask; + ZXIC_UINT32 me_pkt_out_q_underflow_mask; + ZXIC_UINT32 me_continue_q_overflow_mask; + ZXIC_UINT32 me_continue_q_underflow_mask; + ZXIC_UINT32 me_esrh_q_overflow_mask; + ZXIC_UINT32 me_esrh_q_underflow_mask; + ZXIC_UINT32 me_isrh_q_overflow_mask; + ZXIC_UINT32 me_isrh_q_underflow_mask; + ZXIC_UINT32 me_cache_miss_q_overflow_mask; + ZXIC_UINT32 me_cache_miss_q_underflow_mask; + ZXIC_UINT32 me_base_q_u0_overflow_mask; + ZXIC_UINT32 me_base_q_u0_underflow_mask; + ZXIC_UINT32 me_base_q_u1_overflow_mask; + ZXIC_UINT32 me_base_q_u1_underflow_mask; + ZXIC_UINT32 me_base_q_u2_overflow_mask; + ZXIC_UINT32 me_base_q_u2_underflow_mask; + ZXIC_UINT32 me_base_q_u3_overflow_mask; + ZXIC_UINT32 me_base_q_u3_underflow_mask; + ZXIC_UINT32 me_reg_pc_q_overflow_mask; + ZXIC_UINT32 me_reg_pc_q_underflow_mask; + ZXIC_UINT32 me_branch_q_overflow_mask; + ZXIC_UINT32 me_branch_q_underflow_mask; + ZXIC_UINT32 me_pkt_base_q_overflow_mask; + ZXIC_UINT32 me_pkt_base_q_underflow_mask; +}DPP_PPU_CLUSTER_INT_1200M_ME_FIFO_MASK_L_T; + +typedef struct dpp_ppu_cluster_int_1200m_me_fifo_mask_h_t +{ + ZXIC_UINT32 me_except_refetch_pc_overflow_mask; + ZXIC_UINT32 me_except_refetch_pc_underflow_mask; +}DPP_PPU_CLUSTER_INT_1200M_ME_FIFO_MASK_H_T; + +typedef struct dpp_ppu_cluster_me_fifo_interrupt_flag_l_t +{ + ZXIC_UINT32 me_free_pkt_q_overflow_flag; + ZXIC_UINT32 me_free_pkt_q_underflow_flag; + ZXIC_UINT32 me_free_thread_q_overflow_flag; + ZXIC_UINT32 me_free_thread_q_underflow_flag; + ZXIC_UINT32 me_pkt_in_overflow_flag; + ZXIC_UINT32 me_pkt_in_underflow_flag; + ZXIC_UINT32 me_rdy_q_overflow_flag; + ZXIC_UINT32 me_rdy_q_underflow_flag; + ZXIC_UINT32 me_pkt_out_q_overflow_flag; + ZXIC_UINT32 me_pkt_out_q_underflow_flag; + ZXIC_UINT32 me_continue_q_overflow_flag; + ZXIC_UINT32 me_continue_q_underflow_flag; + ZXIC_UINT32 me_esrh_q_overflow_flag; + ZXIC_UINT32 me_esrh_q_underflow_flag; + ZXIC_UINT32 me_isrh_q_overflow_flag; + ZXIC_UINT32 me_isrh_q_underflow_flag; + ZXIC_UINT32 me_cache_miss_q_overflow_flag; + ZXIC_UINT32 me_cache_miss_q_underflow_flag; + ZXIC_UINT32 me_base_q_u0_overflow_flag; + ZXIC_UINT32 me_base_q_u0_underflow_flag; + ZXIC_UINT32 me_base_q_u1_overflow_flag; + ZXIC_UINT32 me_base_q_u1_underflow_flag; + ZXIC_UINT32 me_base_q_u2_overflow_flag; + ZXIC_UINT32 me_base_q_u2_underflow_flag; + ZXIC_UINT32 me_base_q_u3_overflow_flag; + ZXIC_UINT32 me_base_q_u3_underflow_flag; + ZXIC_UINT32 me_reg_pc_q_overflow_flag; + ZXIC_UINT32 me_reg_pc_q_underflow_flag; + ZXIC_UINT32 me_branch_q_overflow_flag; + ZXIC_UINT32 me_branch_q_underflow_flag; + ZXIC_UINT32 me_pkt_base_q_overflow_flag; + ZXIC_UINT32 me_pkt_base_q_underflow_flag; +}DPP_PPU_CLUSTER_ME_FIFO_INTERRUPT_FLAG_L_T; + +typedef struct dpp_ppu_cluster_me_fifo_interrupt_flag_h_t +{ + ZXIC_UINT32 me_except_refetch_pc_overflow_flag; + ZXIC_UINT32 me_except_refetch_pc_underflow_flag; +}DPP_PPU_CLUSTER_ME_FIFO_INTERRUPT_FLAG_H_T; + +typedef struct dpp_ppu_cluster_me_fifo_interrupt_sta_l_t +{ + ZXIC_UINT32 me_free_pkt_q_overflow_sta; + ZXIC_UINT32 me_free_pkt_q_underflow_sta; + ZXIC_UINT32 me_free_thread_q_overflow_sta; + ZXIC_UINT32 me_free_thread_q_underflow_sta; + ZXIC_UINT32 me_pkt_in_overflow_sta; + ZXIC_UINT32 me_pkt_in_underflow_sta; + ZXIC_UINT32 me_rdy_q_overflow_sta; + ZXIC_UINT32 me_rdy_q_underflow_sta; + ZXIC_UINT32 me_pkt_out_q_overflow_sta; + ZXIC_UINT32 me_pkt_out_q_underflow_sta; + ZXIC_UINT32 me_continue_q_overflow_sta; + ZXIC_UINT32 me_continue_q_underflow_sta; + ZXIC_UINT32 me_esrh_q_overflow_sta; + ZXIC_UINT32 me_esrh_q_underflow_sta; + ZXIC_UINT32 me_isrh_q_overflow_sta; + ZXIC_UINT32 me_isrh_q_underflow_sta; + ZXIC_UINT32 me_cache_miss_q_overflow_sta; + ZXIC_UINT32 me_cache_miss_q_underflow_sta; + ZXIC_UINT32 me_base_q_u0_overflow_sta; + ZXIC_UINT32 me_base_q_u0_underflow_sta; + ZXIC_UINT32 me_base_q_u1_overflow_sta; + ZXIC_UINT32 me_base_q_u1_underflow_sta; + ZXIC_UINT32 me_base_q_u2_overflow_sta; + ZXIC_UINT32 me_base_q_u2_underflow_sta; + ZXIC_UINT32 me_base_q_u3_overflow_sta; + ZXIC_UINT32 me_base_q_u3_underflow_sta; + ZXIC_UINT32 me_reg_pc_q_overflow_sta; + ZXIC_UINT32 me_reg_pc_q_underflow_sta; + ZXIC_UINT32 me_branch_q_overflow_sta; + ZXIC_UINT32 me_branch_q_underflow_sta; + ZXIC_UINT32 me_pkt_base_q_overflow_sta; + ZXIC_UINT32 me_pkt_base_q_underflow_sta; +}DPP_PPU_CLUSTER_ME_FIFO_INTERRUPT_STA_L_T; + +typedef struct dpp_ppu_cluster_me_fifo_interrupt_sta_h_t +{ + ZXIC_UINT32 me_except_refetch_pc_overflow_sta; + ZXIC_UINT32 me_except_refetch_pc_underflow_sta; +}DPP_PPU_CLUSTER_ME_FIFO_INTERRUPT_STA_H_T; + +typedef struct dpp_ppu_cluster_int_1200m_cluster_mex_fifo_mask_l_t +{ + ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u3_overflow_mask; + ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u3_underflow_mask; + ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u4_overflow_mask; + ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u4_underflow_mask; + ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u5_overflow_mask; + ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u5_underflow_mask; + ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u6_overflow_mask; + ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u6_underflow_mask; + ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u7_overflow_mask; + ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u7_underflow_mask; + ZXIC_UINT32 ppu_ise_rsp_afifo_64x143_wrapper_u0_underflow_mask; + ZXIC_UINT32 ise_rsp_ram_free_ptr_u0_overflow_mask; + ZXIC_UINT32 ise_rsp_ram_free_ptr_u0_underflow_mask; + ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u0_overflow_mask; + ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u0_underflow_mask; + ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u1_overflow_mask; + ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u1_underflow_mask; + ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u2_overflow_mask; + ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u2_underflow_mask; + ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u3_overflow_mask; + ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u3_underflow_mask; + ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u4_overflow_mask; + ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u4_underflow_mask; + ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u5_overflow_mask; + ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u5_underflow_mask; + ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u6_overflow_mask; + ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u6_underflow_mask; + ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u7_overflow_mask; + ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u7_underflow_mask; + ZXIC_UINT32 ppu_sta_rsp_afifo_64x79_wrapper_underflow_mask; + ZXIC_UINT32 ppu_sta_rsp_fwft_fifo_128x79_wrapper_overflow_mask; + ZXIC_UINT32 ppu_sta_rsp_fwft_fifo_128x79_wrapper_underflow_mask; +}DPP_PPU_CLUSTER_INT_1200M_CLUSTER_MEX_FIFO_MASK_L_T; + +typedef struct dpp_ppu_cluster_int_1200m_cluster_mex_fifo_mask_h_t +{ + ZXIC_UINT32 ppu_se_key_afifo_32x54_wrapper_overflow_mask; + ZXIC_UINT32 ppu_se_key_afifo_32x665_wrapper_overflow_mask; + ZXIC_UINT32 ppu_sta_key_afifo_32x110_wrapper_overflow_mask; + ZXIC_UINT32 ppu_cluster_mf_in_afifo_32x2048_wrapper_underflow_mask; + ZXIC_UINT32 ppu_pbu_mcode_pf_rsp_fifo_32x13_wrapper_overflow_mask; + ZXIC_UINT32 ppu_pbu_mcode_pf_rsp_fifo_32x13_wrapper_underflow_mask; + ZXIC_UINT32 ppu_coprocess_rsp_fifo_32x77_wrapper_overflow_mask; + ZXIC_UINT32 ppu_coprocess_rsp_fifo_32x77_wrapper_underflow_mask; + ZXIC_UINT32 ppu_coprocess_rsp_fwft_fifo_128x78_wrapper_overflow_mask; + ZXIC_UINT32 ppu_coprocess_rsp_fwft_fifo_128x78_wrapper_underflow_mask; + ZXIC_UINT32 ppu_ese_rsp_afifo_64x271_wrapper_u0_underflow_mask; + ZXIC_UINT32 ese_rsp_ram_free_ptr_u0_overflow_mask; + ZXIC_UINT32 ese_rsp_ram_free_ptr_u0_underflow_mask; + ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u0_overflow_mask; + ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u0_underflow_mask; + ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u1_overflow_mask; + ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u1_underflow_mask; + ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u2_overflow_mask; + ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u2_underflow_mask; +}DPP_PPU_CLUSTER_INT_1200M_CLUSTER_MEX_FIFO_MASK_H_T; + +typedef struct dpp_ppu_cluster_int_1200m_cluster_mex_fifo_flag_l_t +{ + ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u3_overflow_flag; + ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u3_underflow_flag; + ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u4_overflow_flag; + ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u4_underflow_flag; + ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u5_overflow_flag; + ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u5_underflow_flag; + ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u6_overflow_flag; + ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u6_underflow_flag; + ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u7_overflow_flag; + ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u7_underflow_flag; + ZXIC_UINT32 ppu_ise_rsp_afifo_64x143_wrapper_u0_underflow_flag; + ZXIC_UINT32 ise_rsp_ram_free_ptr_u0_overflow_flag; + ZXIC_UINT32 ise_rsp_ram_free_ptr_u0_underflow_flag; + ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u0_overflow_flag; + ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u0_underflow_flag; + ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u1_overflow_flag; + ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u1_underflow_flag; + ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u2_overflow_flag; + ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u2_underflow_flag; + ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u3_overflow_flag; + ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u3_underflow_flag; + ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u4_overflow_flag; + ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u4_underflow_flag; + ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u5_overflow_flag; + ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u5_underflow_flag; + ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u6_overflow_flag; + ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u6_underflow_flag; + ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u7_overflow_flag; + ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u7_underflow_flag; + ZXIC_UINT32 ppu_sta_rsp_afifo_64x79_wrapper_underflow_flag; + ZXIC_UINT32 ppu_sta_rsp_fwft_fifo_128x79_wrapper_overflow_flag; + ZXIC_UINT32 ppu_sta_rsp_fwft_fifo_128x79_wrapper_underflow_flag; +}DPP_PPU_CLUSTER_INT_1200M_CLUSTER_MEX_FIFO_FLAG_L_T; + +typedef struct dpp_ppu_cluster_int_1200m_cluster_mex_fifo_flag_h_t +{ + ZXIC_UINT32 ppu_se_key_afifo_32x54_wrapper_overflow_flag; + ZXIC_UINT32 ppu_se_key_afifo_32x665_wrapper_overflow_flag; + ZXIC_UINT32 ppu_sta_key_afifo_32x110_wrapper_overflow_flag; + ZXIC_UINT32 ppu_cluster_mf_in_afifo_32x2048_wrapper_underflow_flag; + ZXIC_UINT32 ppu_pbu_mcode_pf_rsp_fifo_32x13_wrapper_overflow_flag; + ZXIC_UINT32 ppu_pbu_mcode_pf_rsp_fifo_32x13_wrapper_underflow_flag; + ZXIC_UINT32 ppu_coprocess_rsp_fifo_32x77_wrapper_overflow_flag; + ZXIC_UINT32 ppu_coprocess_rsp_fifo_32x77_wrapper_underflow_flag; + ZXIC_UINT32 ppu_coprocess_rsp_fwft_fifo_128x78_wrapper_overflow_flag; + ZXIC_UINT32 ppu_coprocess_rsp_fwft_fifo_128x78_wrapper_underflow_flag; + ZXIC_UINT32 ppu_ese_rsp_afifo_64x271_wrapper_u0_underflow_flag; + ZXIC_UINT32 ese_rsp_ram_free_ptr_u0_overflow_flag; + ZXIC_UINT32 ese_rsp_ram_free_ptr_u0_underflow_flag; + ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u0_overflow_flag; + ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u0_underflow_flag; + ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u1_overflow_flag; + ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u1_underflow_flag; + ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u2_overflow_flag; + ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u2_underflow_flag; +}DPP_PPU_CLUSTER_INT_1200M_CLUSTER_MEX_FIFO_FLAG_H_T; + +typedef struct dpp_ppu_cluster_int_1200m_cluster_mex_fifo_stat_l_t +{ + ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u3_overflow_stat; + ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u3_underflow_stat; + ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u4_overflow_stat; + ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u4_underflow_stat; + ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u5_overflow_stat; + ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u5_underflow_stat; + ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u6_overflow_stat; + ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u6_underflow_stat; + ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u7_overflow_stat; + ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u7_underflow_stat; + ZXIC_UINT32 ppu_ise_rsp_afifo_64x143_wrapper_u0_underflow_stat; + ZXIC_UINT32 ise_rsp_ram_free_ptr_u0_overflow_stat; + ZXIC_UINT32 ise_rsp_ram_free_ptr_u0_underflow_stat; + ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u0_overflow_stat; + ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u0_underflow_stat; + ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u1_overflow_stat; + ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u1_underflow_stat; + ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u2_overflow_stat; + ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u2_underflow_stat; + ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u3_overflow_stat; + ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u3_underflow_stat; + ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u4_overflow_stat; + ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u4_underflow_stat; + ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u5_overflow_stat; + ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u5_underflow_stat; + ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u6_overflow_stat; + ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u6_underflow_stat; + ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u7_overflow_stat; + ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u7_underflow_stat; + ZXIC_UINT32 ppu_sta_rsp_afifo_64x79_wrapper_underflow_stat; + ZXIC_UINT32 ppu_sta_rsp_fwft_fifo_128x79_wrapper_overflow_stat; + ZXIC_UINT32 ppu_sta_rsp_fwft_fifo_128x79_wrapper_underflow_stat; +}DPP_PPU_CLUSTER_INT_1200M_CLUSTER_MEX_FIFO_STAT_L_T; + +typedef struct dpp_ppu_cluster_int_1200m_cluster_mex_fifo_stat_h_t +{ + ZXIC_UINT32 ppu_se_key_afifo_32x54_wrapper_overflow_stat; + ZXIC_UINT32 ppu_se_key_afifo_32x665_wrapper_overflow_stat; + ZXIC_UINT32 ppu_sta_key_afifo_32x110_wrapper_overflow_stat; + ZXIC_UINT32 ppu_cluster_mf_in_afifo_32x2048_wrapper_underflow_stat; + ZXIC_UINT32 ppu_pbu_mcode_pf_rsp_fifo_32x13_wrapper_overflow_stat; + ZXIC_UINT32 ppu_pbu_mcode_pf_rsp_fifo_32x13_wrapper_underflow_stat; + ZXIC_UINT32 ppu_coprocess_rsp_fifo_32x77_wrapper_overflow_stat; + ZXIC_UINT32 ppu_coprocess_rsp_fifo_32x77_wrapper_underflow_stat; + ZXIC_UINT32 ppu_coprocess_rsp_fwft_fifo_128x78_wrapper_overflow_stat; + ZXIC_UINT32 ppu_coprocess_rsp_fwft_fifo_128x78_wrapper_underflow_stat; + ZXIC_UINT32 ppu_ese_rsp_afifo_64x271_wrapper_u0_underflow_stat; + ZXIC_UINT32 ese_rsp_ram_free_ptr_u0_overflow_stat; + ZXIC_UINT32 ese_rsp_ram_free_ptr_u0_underflow_stat; + ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u0_overflow_stat; + ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u0_underflow_stat; + ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u1_overflow_stat; + ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u1_underflow_stat; + ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u2_overflow_stat; + ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u2_underflow_stat; +}DPP_PPU_CLUSTER_INT_1200M_CLUSTER_MEX_FIFO_STAT_H_T; + +typedef struct dpp_ppu_cluster_ppu_statics_wb_exception_cfg_t +{ + ZXIC_UINT32 csr_statics_wb_exception_code5; + ZXIC_UINT32 csr_statics_wb_exception_code4; + ZXIC_UINT32 csr_statics_wb_exception_code3; + ZXIC_UINT32 csr_statics_wb_exception_code2; + ZXIC_UINT32 csr_statics_wb_exception_code1; + ZXIC_UINT32 csr_statics_wb_exception_code0; +}DPP_PPU_CLUSTER_PPU_STATICS_WB_EXCEPTION_CFG_T; + +typedef struct dpp_ppu_cluster_thread_switch_en_t +{ + ZXIC_UINT32 thread_switch_en; +}DPP_PPU_CLUSTER_THREAD_SWITCH_EN_T; + +typedef struct dpp_ppu_cluster_is_me_not_idle_t +{ + ZXIC_UINT32 me7_is_not_idle; + ZXIC_UINT32 me6_is_not_idle; + ZXIC_UINT32 me5_is_not_idle; + ZXIC_UINT32 me4_is_not_idle; + ZXIC_UINT32 me3_is_not_idle; + ZXIC_UINT32 me2_is_not_idle; + ZXIC_UINT32 me1_is_not_idle; + ZXIC_UINT32 me0_is_not_idle; +}DPP_PPU_CLUSTER_IS_ME_NOT_IDLE_T; + +typedef struct dpp_ppu_cluster_ppu_cluster_mf_in_afifo_prog_empty_assert_cfg_t +{ + ZXIC_UINT32 ppu_cluster_mf_in_afifo_prog_empty_assert_cfg; +}DPP_PPU_CLUSTER_PPU_CLUSTER_MF_IN_AFIFO_PROG_EMPTY_ASSERT_CFG_T; + +typedef struct dpp_ppu_cluster_ppu_cluster_mf_in_afifo_prog_empty_negate_cfg_t +{ + ZXIC_UINT32 ppu_cluster_mf_in_afifo_prog_empty_negate_cfg; +}DPP_PPU_CLUSTER_PPU_CLUSTER_MF_IN_AFIFO_PROG_EMPTY_NEGATE_CFG_T; + +typedef struct dpp_ppu_cluster_ese_rsp_afifo_prog_empty_assert_cfg_t +{ + ZXIC_UINT32 ese_rsp_afifo_prog_empty_assert_cfg; +}DPP_PPU_CLUSTER_ESE_RSP_AFIFO_PROG_EMPTY_ASSERT_CFG_T; + +typedef struct dpp_ppu_cluster_ese_rsp_afifo_prog_empty_negate_cfg_t +{ + ZXIC_UINT32 ese_rsp_afifo_prog_empty_negate_cfg; +}DPP_PPU_CLUSTER_ESE_RSP_AFIFO_PROG_EMPTY_NEGATE_CFG_T; + +typedef struct dpp_ppu_cluster_ise_rsp_afifo_prog_empty_assert_cfg_t +{ + ZXIC_UINT32 ise_rsp_afifo_prog_empty_assert_cfg; +}DPP_PPU_CLUSTER_ISE_RSP_AFIFO_PROG_EMPTY_ASSERT_CFG_T; + +typedef struct dpp_ppu_cluster_ise_rsp_afifo_prog_empty_negate_cfg_t +{ + ZXIC_UINT32 ise_rsp_afifo_prog_empty_negate_cfg; +}DPP_PPU_CLUSTER_ISE_RSP_AFIFO_PROG_EMPTY_NEGATE_CFG_T; + +typedef struct dpp_ppu_cluster_ppu_rsp_ptr_fwft_fifo0_prog_full_assert_cfg_t +{ + ZXIC_UINT32 ppu_rsp_ptr_fwft_fifo0_prog_full_assert_cfg; +}DPP_PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO0_PROG_FULL_ASSERT_CFG_T; + +typedef struct dpp_ppu_cluster_ppu_rsp_ptr_fwft_fifo0_prog_full_negate_cfg_t +{ + ZXIC_UINT32 ppu_rsp_ptr_fwft_fifo0_prog_full_negate_cfg; +}DPP_PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO0_PROG_FULL_NEGATE_CFG_T; + +typedef struct dpp_ppu_cluster_ppu_rsp_ptr_fwft_fifo0_prog_empty_assert_cfg_t +{ + ZXIC_UINT32 ppu_rsp_ptr_fwft_fifo0_prog_empty_assert_cfg; +}DPP_PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO0_PROG_EMPTY_ASSERT_CFG_T; + +typedef struct dpp_ppu_cluster_ppu_rsp_ptr_fwft_fifo0_prog_empty_negate_cfg_t +{ + ZXIC_UINT32 ppu_rsp_ptr_fwft_fifo0_prog_empty_negate_cfg; +}DPP_PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO0_PROG_EMPTY_NEGATE_CFG_T; + +typedef struct dpp_ppu_cluster_ppu_rsp_ptr_fwft_fifo1_prog_full_assert_cfg_t +{ + ZXIC_UINT32 ppu_rsp_ptr_fwft_fifo1_prog_full_assert_cfg; +}DPP_PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO1_PROG_FULL_ASSERT_CFG_T; + +typedef struct dpp_ppu_cluster_ppu_rsp_ptr_fwft_fifo1_prog_full_negate_cfg_t +{ + ZXIC_UINT32 ppu_rsp_ptr_fwft_fifo1_prog_full_negate_cfg; +}DPP_PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO1_PROG_FULL_NEGATE_CFG_T; + +typedef struct dpp_ppu_cluster_ppu_rsp_ptr_fwft_fifo1_prog_empty_assert_cfg_t +{ + ZXIC_UINT32 ppu_rsp_ptr_fwft_fifo1_prog_empty_assert_cfg; +}DPP_PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO1_PROG_EMPTY_ASSERT_CFG_T; + +typedef struct dpp_ppu_cluster_ppu_rsp_ptr_fwft_fifo1_prog_empty_negate_cfg_t +{ + ZXIC_UINT32 ppu_rsp_ptr_fwft_fifo1_prog_empty_negate_cfg; +}DPP_PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO1_PROG_EMPTY_NEGATE_CFG_T; + +typedef struct dpp_ppu_cluster_sta_rsp_afifo_prog_empty_assert_cfg_t +{ + ZXIC_UINT32 sta_rsp_afifo_prog_empty_assert_cfg; +}DPP_PPU_CLUSTER_STA_RSP_AFIFO_PROG_EMPTY_ASSERT_CFG_T; + +typedef struct dpp_ppu_cluster_sta_rsp_afifo_prog_empty_negate_cfg_t +{ + ZXIC_UINT32 sta_rsp_afifo_prog_empty_negate_cfg; +}DPP_PPU_CLUSTER_STA_RSP_AFIFO_PROG_EMPTY_NEGATE_CFG_T; + +typedef struct dpp_ppu_cluster_ppu_sta_rsp_fwft_fifo_prog_full_assert_cfg_t +{ + ZXIC_UINT32 ppu_sta_rsp_fwft_fifo_prog_full_assert_cfg; +}DPP_PPU_CLUSTER_PPU_STA_RSP_FWFT_FIFO_PROG_FULL_ASSERT_CFG_T; + +typedef struct dpp_ppu_cluster_ppu_sta_rsp_fwft_fifo_prog_full_negate_cfg_t +{ + ZXIC_UINT32 ppu_sta_rsp_fwft_fifo_prog_full_negate_cfg; +}DPP_PPU_CLUSTER_PPU_STA_RSP_FWFT_FIFO_PROG_FULL_NEGATE_CFG_T; + +typedef struct dpp_ppu_cluster_ppu_sta_rsp_fwft_fifo_prog_empty_assert_cfg_t +{ + ZXIC_UINT32 ppu_sta_rsp_fwft_fifo_prog_empty_assert_cfg; +}DPP_PPU_CLUSTER_PPU_STA_RSP_FWFT_FIFO_PROG_EMPTY_ASSERT_CFG_T; + +typedef struct dpp_ppu_cluster_ppu_sta_rsp_fwft_fifo_prog_empty_negate_cfg_t +{ + ZXIC_UINT32 ppu_sta_rsp_fwft_fifo_prog_empty_negate_cfg; +}DPP_PPU_CLUSTER_PPU_STA_RSP_FWFT_FIFO_PROG_EMPTY_NEGATE_CFG_T; + +typedef struct dpp_ppu_cluster_cop_rsp_fifo_prog_full_assert_cfg_t +{ + ZXIC_UINT32 cop_rsp_fifo_prog_full_assert_cfg; +}DPP_PPU_CLUSTER_COP_RSP_FIFO_PROG_FULL_ASSERT_CFG_T; + +typedef struct dpp_ppu_cluster_cop_rsp_fifo_prog_full_negate_cfg_t +{ + ZXIC_UINT32 cop_rsp_fifo_prog_full_negate_cfg; +}DPP_PPU_CLUSTER_COP_RSP_FIFO_PROG_FULL_NEGATE_CFG_T; + +typedef struct dpp_ppu_cluster_cop_rsp_fifo_prog_empty_assert_cfg_t +{ + ZXIC_UINT32 cop_rsp_fifo_prog_empty_assert_cfg; +}DPP_PPU_CLUSTER_COP_RSP_FIFO_PROG_EMPTY_ASSERT_CFG_T; + +typedef struct dpp_ppu_cluster_cop_rsp_fifo_prog_empty_negate_cfg_t +{ + ZXIC_UINT32 cop_rsp_fifo_prog_empty_negate_cfg; +}DPP_PPU_CLUSTER_COP_RSP_FIFO_PROG_EMPTY_NEGATE_CFG_T; + +typedef struct dpp_ppu_cluster_mcode_pf_rsp_fifo_prog_full_assert_cfg_t +{ + ZXIC_UINT32 mcode_pf_rsp_fifo_prog_full_assert_cfg; +}DPP_PPU_CLUSTER_MCODE_PF_RSP_FIFO_PROG_FULL_ASSERT_CFG_T; + +typedef struct dpp_ppu_cluster_mcode_pf_rsp_fifo_prog_full_negate_cfg_t +{ + ZXIC_UINT32 mcode_pf_rsp_fifo_prog_full_negate_cfg; +}DPP_PPU_CLUSTER_MCODE_PF_RSP_FIFO_PROG_FULL_NEGATE_CFG_T; + +typedef struct dpp_ppu_cluster_mcode_pf_rsp_fifo_prog_empty_assert_cfg_t +{ + ZXIC_UINT32 mcode_pf_rsp_fifo_prog_empty_assert_cfg; +}DPP_PPU_CLUSTER_MCODE_PF_RSP_FIFO_PROG_EMPTY_ASSERT_CFG_T; + +typedef struct dpp_ppu_cluster_mcode_pf_rsp_fifo_prog_empty_negate_cfg_t +{ + ZXIC_UINT32 mcode_pf_rsp_fifo_prog_empty_negate_cfg; +}DPP_PPU_CLUSTER_MCODE_PF_RSP_FIFO_PROG_EMPTY_NEGATE_CFG_T; + +typedef struct dpp_ppu_cluster_ppu_cop_rsp_fwft_fifo_prog_full_assert_cfg_t +{ + ZXIC_UINT32 ppu_cop_rsp_fwft_fifo_prog_full_assert_cfg; +}DPP_PPU_CLUSTER_PPU_COP_RSP_FWFT_FIFO_PROG_FULL_ASSERT_CFG_T; + +typedef struct dpp_ppu_cluster_ppu_cop_rsp_fwft_fifo_prog_full_negate_cfg_t +{ + ZXIC_UINT32 ppu_cop_rsp_fwft_fifo_prog_full_negate_cfg; +}DPP_PPU_CLUSTER_PPU_COP_RSP_FWFT_FIFO_PROG_FULL_NEGATE_CFG_T; + +typedef struct dpp_ppu_cluster_ppu_cop_rsp_fwft_fifo_prog_empty_assert_cfg_t +{ + ZXIC_UINT32 ppu_cop_rsp_fwft_fifo_prog_empty_assert_cfg; +}DPP_PPU_CLUSTER_PPU_COP_RSP_FWFT_FIFO_PROG_EMPTY_ASSERT_CFG_T; + +typedef struct dpp_ppu_cluster_ppu_cop_rsp_fwft_fifo_prog_empty_negate_cfg_t +{ + ZXIC_UINT32 ppu_cop_rsp_fwft_fifo_prog_empty_negate_cfg; +}DPP_PPU_CLUSTER_PPU_COP_RSP_FWFT_FIFO_PROG_EMPTY_NEGATE_CFG_T; + +typedef struct dpp_ppu_cluster_ppu_ise_key_afifo_prog_full_assert_cfg_t +{ + ZXIC_UINT32 ppu_ise_key_afifo_prog_full_assert_cfg; +}DPP_PPU_CLUSTER_PPU_ISE_KEY_AFIFO_PROG_FULL_ASSERT_CFG_T; + +typedef struct dpp_ppu_cluster_ppu_ise_key_afifo_prog_full_negate_cfg_t +{ + ZXIC_UINT32 ppu_ise_key_afifo_prog_full_negate_cfg; +}DPP_PPU_CLUSTER_PPU_ISE_KEY_AFIFO_PROG_FULL_NEGATE_CFG_T; + +typedef struct dpp_ppu_cluster_ppu_ese_key_afifo_prog_full_assert_cfg_t +{ + ZXIC_UINT32 ppu_ese_key_afifo_prog_full_assert_cfg; +}DPP_PPU_CLUSTER_PPU_ESE_KEY_AFIFO_PROG_FULL_ASSERT_CFG_T; + +typedef struct dpp_ppu_cluster_ppu_ese_key_afifo_prog_full_negate_cfg_t +{ + ZXIC_UINT32 ppu_ese_key_afifo_prog_full_negate_cfg; +}DPP_PPU_CLUSTER_PPU_ESE_KEY_AFIFO_PROG_FULL_NEGATE_CFG_T; + +typedef struct dpp_ppu_cluster_ppu_sta_key_afifo_prog_full_assert_cfg_t +{ + ZXIC_UINT32 ppu_sta_key_afifo_prog_full_assert_cfg; +}DPP_PPU_CLUSTER_PPU_STA_KEY_AFIFO_PROG_FULL_ASSERT_CFG_T; + +typedef struct dpp_ppu_cluster_ppu_sta_key_afifo_prog_full_negate_cfg_t +{ + ZXIC_UINT32 ppu_sta_key_afifo_prog_full_negate_cfg; +}DPP_PPU_CLUSTER_PPU_STA_KEY_AFIFO_PROG_FULL_NEGATE_CFG_T; + +typedef struct dpp_ppu_cluster_int_600m_cluster_mex_fifo_mask_t +{ + ZXIC_UINT32 ppu_se_key_afifo_32x54_wrapper_underflow_mask; + ZXIC_UINT32 ppu_se_key_afifo_32x665_wrapper_underflow_mask; + ZXIC_UINT32 ppu_sta_key_afifo_32x110_wrapper_underflow_mask; + ZXIC_UINT32 ppu_cluster_mf_in_afifo_32x2048_wrapper_overflow_mask; + ZXIC_UINT32 ppu_ese_rsp_afifo_64x271_wrapper_u0_overflow_mask; + ZXIC_UINT32 ppu_ise_rsp_afifo_64x143_wrapper_u0_overflow_mask; + ZXIC_UINT32 ppu_sta_rsp_afifo_64x79_wrapper_overflow_mask; +}DPP_PPU_CLUSTER_INT_600M_CLUSTER_MEX_FIFO_MASK_T; + +typedef struct dpp_ppu_cluster_cluster_mex_fifo_600m_interrupt_flag_t +{ + ZXIC_UINT32 ppu_se_key_afifo_32x54_wrapper_underflow_flag; + ZXIC_UINT32 ppu_se_key_afifo_32x665_wrapper_underflow_flag; + ZXIC_UINT32 ppu_sta_key_afifo_32x110_wrapper_underflow_flag; + ZXIC_UINT32 ppu_cluster_mf_in_afifo_32x2048_wrapper_overflow_flag; + ZXIC_UINT32 ppu_ese_rsp_afifo_64x271_wrapper_u0_overflow_flag; + ZXIC_UINT32 ppu_ise_rsp_afifo_64x143_wrapper_u0_overflow_flag; + ZXIC_UINT32 ppu_sta_rsp_afifo_64x79_wrapper_overflow_flag; +}DPP_PPU_CLUSTER_CLUSTER_MEX_FIFO_600M_INTERRUPT_FLAG_T; + +typedef struct dpp_ppu_cluster_cluster_mex_fifo_600m_interrupt_sta_t +{ + ZXIC_UINT32 ppu_se_key_afifo_32x54_wrapper_underflow_sta; + ZXIC_UINT32 ppu_se_key_afifo_32x665_wrapper_underflow_sta; + ZXIC_UINT32 ppu_sta_key_afifo_32x110_wrapper_underflow_sta; + ZXIC_UINT32 ppu_cluster_mf_in_afifo_32x2048_wrapper_overflow_sta; + ZXIC_UINT32 ppu_ese_rsp_afifo_64x271_wrapper_u0_overflow_sta; + ZXIC_UINT32 ppu_ise_rsp_afifo_64x143_wrapper_u0_overflow_sta; + ZXIC_UINT32 ppu_sta_rsp_afifo_64x79_wrapper_overflow_sta; +}DPP_PPU_CLUSTER_CLUSTER_MEX_FIFO_600M_INTERRUPT_STA_T; + +typedef struct dpp_ppu_cluster_mex_cnt_cfg_t +{ + ZXIC_UINT32 csr_count_overflow_mode; + ZXIC_UINT32 csr_count_rd_mode; +}DPP_PPU_CLUSTER_MEX_CNT_CFG_T; + +typedef struct dpp_ppu_cluster_int_600m_cluster_mex_ram_ecc_error_interrupt_mask_t +{ + ZXIC_UINT32 ppu_sta_key_ram_1r1w_32x110_ecc_double_err_mask; + ZXIC_UINT32 ppu_se_key_afifo_32x665_ecc_double_err_mask; + ZXIC_UINT32 ppu_se_key_afifo_32x54_ecc_double_err_mask; + ZXIC_UINT32 ppu_sta_key_ram_1r1w_32x110_ecc_single_err_flag; + ZXIC_UINT32 ppu_se_key_afifo_32x665_ecc_single_err_mask; + ZXIC_UINT32 ppu_se_key_afifo_32x54_ecc_single_err_mask; +}DPP_PPU_CLUSTER_INT_600M_CLUSTER_MEX_RAM_ECC_ERROR_INTERRUPT_MASK_T; + +typedef struct dpp_ppu_cluster_cluster_mex_ram_600m_ecc_error_interrupt_flag_t +{ + ZXIC_UINT32 ppu_sta_key_ram_1r1w_32x110_ecc_double_err_flag; + ZXIC_UINT32 ppu_se_key_afifo_32x665_ecc_double_err_flag; + ZXIC_UINT32 ppu_se_key_afifo_32x54_ecc_double_err_flag; + ZXIC_UINT32 ppu_sta_key_ram_1r1w_32x110_ecc_single_err_flag; + ZXIC_UINT32 ppu_se_key_afifo_32x665_ecc_single_err_flag; + ZXIC_UINT32 ppu_se_key_afifo_32x54_ecc_single_err_flag; +}DPP_PPU_CLUSTER_CLUSTER_MEX_RAM_600M_ECC_ERROR_INTERRUPT_FLAG_T; + +typedef struct dpp_ppu_cluster_cluster_mex_ram_600m_ecc_error_interrupt_sta_t +{ + ZXIC_UINT32 ppu_sta_key_ram_1r1w_32x110_ecc_double_err_stat; + ZXIC_UINT32 ppu_se_key_afifo_32x665_ecc_double_err_stat; + ZXIC_UINT32 ppu_se_key_afifo_32x54_ecc_double_err_stat; + ZXIC_UINT32 ppu_sta_key_ram_1r1w_32x110_ecc_single_err_stat; + ZXIC_UINT32 ppu_se_key_afifo_32x665_ecc_single_err_stat; + ZXIC_UINT32 ppu_se_key_afifo_32x54_ecc_single_err_stat; +}DPP_PPU_CLUSTER_CLUSTER_MEX_RAM_600M_ECC_ERROR_INTERRUPT_STA_T; + +typedef struct dpp_ppu_cluster_ppu_cluster_mf_in_afifo_prog_full_assert_cfg_t +{ + ZXIC_UINT32 ppu_cluster_mf_in_afifo_prog_full_assert_cfg; +}DPP_PPU_CLUSTER_PPU_CLUSTER_MF_IN_AFIFO_PROG_FULL_ASSERT_CFG_T; + +typedef struct dpp_ppu_cluster_ppu_cluster_mf_in_afifo_prog_full_negate_cfg_t +{ + ZXIC_UINT32 ppu_cluster_mf_in_afifo_prog_full_negate_cfg; +}DPP_PPU_CLUSTER_PPU_CLUSTER_MF_IN_AFIFO_PROG_FULL_NEGATE_CFG_T; + +typedef struct dpp_ppu_cluster_ese_rsp_afifo_prog_full_assert_cfg_t +{ + ZXIC_UINT32 ese_rsp_afifo_prog_full_assert_cfg; +}DPP_PPU_CLUSTER_ESE_RSP_AFIFO_PROG_FULL_ASSERT_CFG_T; + +typedef struct dpp_ppu_cluster_ese_rsp_afifo_prog_full_negate_cfg_t +{ + ZXIC_UINT32 ese_rsp_afifo_prog_full_negate_cfg; +}DPP_PPU_CLUSTER_ESE_RSP_AFIFO_PROG_FULL_NEGATE_CFG_T; + +typedef struct dpp_ppu_cluster_ise_rsp_afifo_prog_full_assert_cfg_t +{ + ZXIC_UINT32 ise_rsp_afifo_prog_full_assert_cfg; +}DPP_PPU_CLUSTER_ISE_RSP_AFIFO_PROG_FULL_ASSERT_CFG_T; + +typedef struct dpp_ppu_cluster_ise_rsp_afifo_prog_full_negate_cfg_t +{ + ZXIC_UINT32 ise_rsp_afifo_prog_full_negate_cfg; +}DPP_PPU_CLUSTER_ISE_RSP_AFIFO_PROG_FULL_NEGATE_CFG_T; + +typedef struct dpp_ppu_cluster_sta_rsp_afifo_prog_full_assert_cfg_t +{ + ZXIC_UINT32 sta_rsp_afifo_prog_full_assert_cfg; +}DPP_PPU_CLUSTER_STA_RSP_AFIFO_PROG_FULL_ASSERT_CFG_T; + +typedef struct dpp_ppu_cluster_sta_rsp_afifo_prog_full_negate_cfg_t +{ + ZXIC_UINT32 sta_rsp_afifo_prog_full_negate_cfg; +}DPP_PPU_CLUSTER_STA_RSP_AFIFO_PROG_FULL_NEGATE_CFG_T; + +typedef struct dpp_ppu_cluster_ppu_ise_key_afifo_prog_empty_assert_cfg_t +{ + ZXIC_UINT32 ppu_ise_key_afifo_prog_empty_assert_cfg; +}DPP_PPU_CLUSTER_PPU_ISE_KEY_AFIFO_PROG_EMPTY_ASSERT_CFG_T; + +typedef struct dpp_ppu_cluster_ppu_ise_key_afifo_prog_empty_negate_cfg_t +{ + ZXIC_UINT32 ppu_ise_key_afifo_prog_empty_negate_cfg; +}DPP_PPU_CLUSTER_PPU_ISE_KEY_AFIFO_PROG_EMPTY_NEGATE_CFG_T; + +typedef struct dpp_ppu_cluster_ppu_ese_key_afifo_prog_empty_assert_cfg_t +{ + ZXIC_UINT32 ppu_ese_key_afifo_prog_empty_assert_cfg; +}DPP_PPU_CLUSTER_PPU_ESE_KEY_AFIFO_PROG_EMPTY_ASSERT_CFG_T; + +typedef struct dpp_ppu_cluster_ppu_ese_key_afifo_prog_empty_negate_cfg_t +{ + ZXIC_UINT32 ppu_ese_key_afifo_prog_empty_negate_cfg; +}DPP_PPU_CLUSTER_PPU_ESE_KEY_AFIFO_PROG_EMPTY_NEGATE_CFG_T; + +typedef struct dpp_ppu_cluster_ppu_sta_key_afifo_prog_empty_assert_cfg_t +{ + ZXIC_UINT32 ppu_sta_key_afifo_prog_empty_assert_cfg; +}DPP_PPU_CLUSTER_PPU_STA_KEY_AFIFO_PROG_EMPTY_ASSERT_CFG_T; + +typedef struct dpp_ppu_cluster_ppu_sta_key_afifo_prog_empty_negate_cfg_t +{ + ZXIC_UINT32 ppu_sta_key_afifo_prog_empty_negate_cfg; +}DPP_PPU_CLUSTER_PPU_STA_KEY_AFIFO_PROG_EMPTY_NEGATE_CFG_T; + +typedef struct dpp_ppu_cluster_ppu_cluster_mf_vld_cnt_h_t +{ + ZXIC_UINT32 ppu_cluster_mf_vld_cnt_h; +}DPP_PPU_CLUSTER_PPU_CLUSTER_MF_VLD_CNT_H_T; + +typedef struct dpp_ppu_cluster_ppu_cluster_mf_vld_cnt_l_t +{ + ZXIC_UINT32 ppu_cluster_mf_vld_cnt_l; +}DPP_PPU_CLUSTER_PPU_CLUSTER_MF_VLD_CNT_L_T; + +typedef struct dpp_ppu_cluster_cluster_ise_key_out_vld_cnt_t +{ + ZXIC_UINT32 cluster_ise_key_out_vld_cnt; +}DPP_PPU_CLUSTER_CLUSTER_ISE_KEY_OUT_VLD_CNT_T; + +typedef struct dpp_ppu_cluster_ise_cluster_rsp_in_vld_cnt_t +{ + ZXIC_UINT32 ise_cluster_rsp_in_vld_cnt; +}DPP_PPU_CLUSTER_ISE_CLUSTER_RSP_IN_VLD_CNT_T; + +typedef struct dpp_ppu_cluster_cluster_ese_key_out_vld_cnt_t +{ + ZXIC_UINT32 cluster_ese_key_out_vld_cnt; +}DPP_PPU_CLUSTER_CLUSTER_ESE_KEY_OUT_VLD_CNT_T; + +typedef struct dpp_ppu_cluster_ese_cluster_rsp_in_vld_cnt_t +{ + ZXIC_UINT32 ese_cluster_rsp_in_vld_cnt; +}DPP_PPU_CLUSTER_ESE_CLUSTER_RSP_IN_VLD_CNT_T; + +typedef struct dpp_ppu_cluster_cluster_stat_cmd_vld_cnt_t +{ + ZXIC_UINT32 cluster_stat_cmd_vld_cnt; +}DPP_PPU_CLUSTER_CLUSTER_STAT_CMD_VLD_CNT_T; + +typedef struct dpp_ppu_cluster_stat_cluster_rsp_vld_cnt_t +{ + ZXIC_UINT32 stat_cluster_rsp_vld_cnt; +}DPP_PPU_CLUSTER_STAT_CLUSTER_RSP_VLD_CNT_T; + +typedef struct dpp_ppu_cluster_mex_debug_key_vld_cnt_t +{ + ZXIC_UINT32 mex_debug_key_vld_cnt; +}DPP_PPU_CLUSTER_MEX_DEBUG_KEY_VLD_CNT_T; + +typedef struct dpp_ppu_cluster_ise_cluster_key_fc_cnt_t +{ + ZXIC_UINT32 ise_cluster_key_fc_cnt; +}DPP_PPU_CLUSTER_ISE_CLUSTER_KEY_FC_CNT_T; + +typedef struct dpp_ppu_cluster_ese_cluster_key_fc_cnt_t +{ + ZXIC_UINT32 ese_cluster_key_fc_cnt; +}DPP_PPU_CLUSTER_ESE_CLUSTER_KEY_FC_CNT_T; + +typedef struct dpp_ppu_cluster_cluster_ise_rsp_fc_cnt_t +{ + ZXIC_UINT32 cluster_ise_rsp_fc_cnt; +}DPP_PPU_CLUSTER_CLUSTER_ISE_RSP_FC_CNT_T; + +typedef struct dpp_ppu_cluster_cluster_ese_rsp_fc_cnt_t +{ + ZXIC_UINT32 cluster_ese_rsp_fc_cnt; +}DPP_PPU_CLUSTER_CLUSTER_ESE_RSP_FC_CNT_T; + +typedef struct dpp_ppu_cluster_stat_cluster_cmd_fc_cnt_t +{ + ZXIC_UINT32 stat_cluster_cmd_fc_cnt; +}DPP_PPU_CLUSTER_STAT_CLUSTER_CMD_FC_CNT_T; + +typedef struct dpp_ppu_cluster_cluster_stat_rsp_fc_cnt_t +{ + ZXIC_UINT32 cluster_stat_rsp_fc_cnt; +}DPP_PPU_CLUSTER_CLUSTER_STAT_RSP_FC_CNT_T; + +typedef struct dpp_ppu_cluster_cluster_ppu_mf_vld_cnt_l_t +{ + ZXIC_UINT32 cluster_ppu_mf_vld_cnt_l; +}DPP_PPU_CLUSTER_CLUSTER_PPU_MF_VLD_CNT_L_T; + +typedef struct dpp_ppu_cluster_cluster_ppu_mf_vld_cnt_h_t +{ + ZXIC_UINT32 cluster_ppu_mf_vld_cnt_h; +}DPP_PPU_CLUSTER_CLUSTER_PPU_MF_VLD_CNT_H_T; + +typedef struct dpp_ppu_cluster_cluster_cop_key_vld_cnt_l_t +{ + ZXIC_UINT32 cluster_cop_key_vld_cnt_l; +}DPP_PPU_CLUSTER_CLUSTER_COP_KEY_VLD_CNT_L_T; + +typedef struct dpp_ppu_cluster_cluster_cop_key_vld_cnt_h_t +{ + ZXIC_UINT32 cluster_cop_key_vld_cnt_h; +}DPP_PPU_CLUSTER_CLUSTER_COP_KEY_VLD_CNT_H_T; + +typedef struct dpp_ppu_cluster_cop_cluster_rsp_vld_cnt_l_t +{ + ZXIC_UINT32 cop_cluster_rsp_vld_cnt_l; +}DPP_PPU_CLUSTER_COP_CLUSTER_RSP_VLD_CNT_L_T; + +typedef struct dpp_ppu_cluster_cop_cluster_rsp_vld_cnt_h_t +{ + ZXIC_UINT32 cop_cluster_rsp_vld_cnt_h; +}DPP_PPU_CLUSTER_COP_CLUSTER_RSP_VLD_CNT_H_T; + +typedef struct dpp_ppu_cluster_mex_me_pkt_in_sop_cnt_l_t +{ + ZXIC_UINT32 mex_me_pkt_in_sop_cnt_l; +}DPP_PPU_CLUSTER_MEX_ME_PKT_IN_SOP_CNT_L_T; + +typedef struct dpp_ppu_cluster_mex_me_pkt_in_sop_cnt_h_t +{ + ZXIC_UINT32 mex_me_pkt_in_sop_cnt_h; +}DPP_PPU_CLUSTER_MEX_ME_PKT_IN_SOP_CNT_H_T; + +typedef struct dpp_ppu_cluster_mex_me_pkt_in_eop_cnt_l_t +{ + ZXIC_UINT32 mex_me_pkt_in_eop_cnt_l; +}DPP_PPU_CLUSTER_MEX_ME_PKT_IN_EOP_CNT_L_T; + +typedef struct dpp_ppu_cluster_mex_me_pkt_in_eop_cnt_h_t +{ + ZXIC_UINT32 mex_me_pkt_in_eop_cnt_h; +}DPP_PPU_CLUSTER_MEX_ME_PKT_IN_EOP_CNT_H_T; + +typedef struct dpp_ppu_cluster_mex_me_pkt_in_vld_cnt_l_t +{ + ZXIC_UINT32 mex_me_pkt_in_vld_cnt_l; +}DPP_PPU_CLUSTER_MEX_ME_PKT_IN_VLD_CNT_L_T; + +typedef struct dpp_ppu_cluster_mex_me_pkt_in_vld_cnt_h_t +{ + ZXIC_UINT32 mex_me_pkt_in_vld_cnt_h; +}DPP_PPU_CLUSTER_MEX_ME_PKT_IN_VLD_CNT_H_T; + +typedef struct dpp_ppu_cluster_me_mex_pkt_out_sop_cnt_l_t +{ + ZXIC_UINT32 me_mex_pkt_out_sop_cnt_l; +}DPP_PPU_CLUSTER_ME_MEX_PKT_OUT_SOP_CNT_L_T; + +typedef struct dpp_ppu_cluster_me_mex_pkt_out_sop_cnt_h_t +{ + ZXIC_UINT32 me_mex_pkt_out_sop_cnt_h; +}DPP_PPU_CLUSTER_ME_MEX_PKT_OUT_SOP_CNT_H_T; + +typedef struct dpp_ppu_cluster_me_mex_pkt_out_eop_cnt_l_t +{ + ZXIC_UINT32 me_mex_pkt_out_eop_cnt_l; +}DPP_PPU_CLUSTER_ME_MEX_PKT_OUT_EOP_CNT_L_T; + +typedef struct dpp_ppu_cluster_me_mex_pkt_out_eop_cnt_h_t +{ + ZXIC_UINT32 me_mex_pkt_out_eop_cnt_h; +}DPP_PPU_CLUSTER_ME_MEX_PKT_OUT_EOP_CNT_H_T; + +typedef struct dpp_ppu_cluster_me_mex_pkt_out_vld_cnt_l_t +{ + ZXIC_UINT32 me_mex_pkt_out_vld_cnt_l; +}DPP_PPU_CLUSTER_ME_MEX_PKT_OUT_VLD_CNT_L_T; + +typedef struct dpp_ppu_cluster_me_mex_pkt_out_vld_cnt_h_t +{ + ZXIC_UINT32 me_mex_pkt_out_vld_cnt_h; +}DPP_PPU_CLUSTER_ME_MEX_PKT_OUT_VLD_CNT_H_T; + +typedef struct dpp_ppu_cluster_me_mex_i_key_out_sop_cnt_l_t +{ + ZXIC_UINT32 me_mex_i_key_out_sop_cnt_l; +}DPP_PPU_CLUSTER_ME_MEX_I_KEY_OUT_SOP_CNT_L_T; + +typedef struct dpp_ppu_cluster_me_mex_i_key_out_sop_cnt_h_t +{ + ZXIC_UINT32 me_mex_i_key_out_sop_cnt_h; +}DPP_PPU_CLUSTER_ME_MEX_I_KEY_OUT_SOP_CNT_H_T; + +typedef struct dpp_ppu_cluster_me_mex_i_key_out_eop_cnt_l_t +{ + ZXIC_UINT32 me_mex_i_key_out_eop_cnt_l; +}DPP_PPU_CLUSTER_ME_MEX_I_KEY_OUT_EOP_CNT_L_T; + +typedef struct dpp_ppu_cluster_me_mex_i_key_out_eop_cnt_h_t +{ + ZXIC_UINT32 me_mex_i_key_out_eop_cnt_h; +}DPP_PPU_CLUSTER_ME_MEX_I_KEY_OUT_EOP_CNT_H_T; + +typedef struct dpp_ppu_cluster_me_mex_i_key_out_vld_cnt_l_t +{ + ZXIC_UINT32 me_mex_i_key_out_vld_cnt_l; +}DPP_PPU_CLUSTER_ME_MEX_I_KEY_OUT_VLD_CNT_L_T; + +typedef struct dpp_ppu_cluster_me_mex_i_key_out_vld_cnt_h_t +{ + ZXIC_UINT32 me_mex_i_key_out_vld_cnt_h; +}DPP_PPU_CLUSTER_ME_MEX_I_KEY_OUT_VLD_CNT_H_T; + +typedef struct dpp_ppu_cluster_me_mex_e_key_out_sop_cnt_l_t +{ + ZXIC_UINT32 me_mex_e_key_out_sop_cnt_l; +}DPP_PPU_CLUSTER_ME_MEX_E_KEY_OUT_SOP_CNT_L_T; + +typedef struct dpp_ppu_cluster_me_mex_e_key_out_sop_cnt_h_t +{ + ZXIC_UINT32 me_mex_e_key_out_sop_cnt_h; +}DPP_PPU_CLUSTER_ME_MEX_E_KEY_OUT_SOP_CNT_H_T; + +typedef struct dpp_ppu_cluster_me_mex_e_key_out_eop_cnt_l_t +{ + ZXIC_UINT32 me_mex_e_key_out_eop_cnt_l; +}DPP_PPU_CLUSTER_ME_MEX_E_KEY_OUT_EOP_CNT_L_T; + +typedef struct dpp_ppu_cluster_me_mex_e_key_out_eop_cnt_h_t +{ + ZXIC_UINT32 me_mex_e_key_out_eop_cnt_h; +}DPP_PPU_CLUSTER_ME_MEX_E_KEY_OUT_EOP_CNT_H_T; + +typedef struct dpp_ppu_cluster_me_mex_e_key_out_vld_cnt_l_t +{ + ZXIC_UINT32 me_mex_e_key_out_vld_cnt_l; +}DPP_PPU_CLUSTER_ME_MEX_E_KEY_OUT_VLD_CNT_L_T; + +typedef struct dpp_ppu_cluster_me_mex_e_key_out_vld_cnt_h_t +{ + ZXIC_UINT32 me_mex_e_key_out_vld_cnt_h; +}DPP_PPU_CLUSTER_ME_MEX_E_KEY_OUT_VLD_CNT_H_T; + +typedef struct dpp_ppu_cluster_me_mex_demux_ise_key_vld_cnt_l_t +{ + ZXIC_UINT32 me_mex_demux_ise_key_vld_cnt_l; +}DPP_PPU_CLUSTER_ME_MEX_DEMUX_ISE_KEY_VLD_CNT_L_T; + +typedef struct dpp_ppu_cluster_me_mex_demux_ise_key_vld_cnt_h_t +{ + ZXIC_UINT32 me_mex_demux_ise_key_vld_cnt_h; +}DPP_PPU_CLUSTER_ME_MEX_DEMUX_ISE_KEY_VLD_CNT_H_T; + +typedef struct dpp_ppu_cluster_me_mex_demux_ese_key_vld_cnt_l_t +{ + ZXIC_UINT32 me_mex_demux_ese_key_vld_cnt_l; +}DPP_PPU_CLUSTER_ME_MEX_DEMUX_ESE_KEY_VLD_CNT_L_T; + +typedef struct dpp_ppu_cluster_me_mex_demux_ese_key_vld_cnt_h_t +{ + ZXIC_UINT32 me_mex_demux_ese_key_vld_cnt_h; +}DPP_PPU_CLUSTER_ME_MEX_DEMUX_ESE_KEY_VLD_CNT_H_T; + +typedef struct dpp_ppu_cluster_me_mex_demux_sta_key_vld_cnt_l_t +{ + ZXIC_UINT32 me_mex_demux_sta_key_vld_cnt_l; +}DPP_PPU_CLUSTER_ME_MEX_DEMUX_STA_KEY_VLD_CNT_L_T; + +typedef struct dpp_ppu_cluster_me_mex_demux_sta_key_vld_cnt_h_t +{ + ZXIC_UINT32 me_mex_demux_sta_key_vld_cnt_h; +}DPP_PPU_CLUSTER_ME_MEX_DEMUX_STA_KEY_VLD_CNT_H_T; + +typedef struct dpp_ppu_cluster_me_mex_demux_cop_key_vld_cnt_l_t +{ + ZXIC_UINT32 me_mex_demux_cop_key_vld_cnt_l; +}DPP_PPU_CLUSTER_ME_MEX_DEMUX_COP_KEY_VLD_CNT_L_T; + +typedef struct dpp_ppu_cluster_me_mex_demux_cop_key_vld_cnt_h_t +{ + ZXIC_UINT32 me_mex_demux_cop_key_vld_cnt_h; +}DPP_PPU_CLUSTER_ME_MEX_DEMUX_COP_KEY_VLD_CNT_H_T; + +typedef struct dpp_ppu_cluster_mex_me_demux_ise_rsp_vld_cnt_l_t +{ + ZXIC_UINT32 mex_me_demux_ise_rsp_vld_cnt_l; +}DPP_PPU_CLUSTER_MEX_ME_DEMUX_ISE_RSP_VLD_CNT_L_T; + +typedef struct dpp_ppu_cluster_mex_me_demux_ise_rsp_vld_cnt_h_t +{ + ZXIC_UINT32 mex_me_demux_ise_rsp_vld_cnt_h; +}DPP_PPU_CLUSTER_MEX_ME_DEMUX_ISE_RSP_VLD_CNT_H_T; + +typedef struct dpp_ppu_cluster_mex_me_demux_ese_rsp_vld_cnt_l_t +{ + ZXIC_UINT32 mex_me_demux_ese_rsp_vld_cnt_l; +}DPP_PPU_CLUSTER_MEX_ME_DEMUX_ESE_RSP_VLD_CNT_L_T; + +typedef struct dpp_ppu_cluster_mex_me_demux_ese_rsp_vld_cnt_h_t +{ + ZXIC_UINT32 mex_me_demux_ese_rsp_vld_cnt_h; +}DPP_PPU_CLUSTER_MEX_ME_DEMUX_ESE_RSP_VLD_CNT_H_T; + +typedef struct dpp_ppu_cluster_mex_me_demux_sta_rsp_vld_cnt_l_t +{ + ZXIC_UINT32 mex_me_demux_sta_rsp_vld_cnt_l; +}DPP_PPU_CLUSTER_MEX_ME_DEMUX_STA_RSP_VLD_CNT_L_T; + +typedef struct dpp_ppu_cluster_mex_me_demux_sta_rsp_vld_cnt_h_t +{ + ZXIC_UINT32 mex_me_demux_sta_rsp_vld_cnt_h; +}DPP_PPU_CLUSTER_MEX_ME_DEMUX_STA_RSP_VLD_CNT_H_T; + +typedef struct dpp_ppu_cluster_mex_me_demux_cop_rsp_vld_cnt_l_t +{ + ZXIC_UINT32 mex_me_demux_cop_rsp_vld_cnt_l; +}DPP_PPU_CLUSTER_MEX_ME_DEMUX_COP_RSP_VLD_CNT_L_T; + +typedef struct dpp_ppu_cluster_mex_me_demux_cop_rsp_vld_cnt_h_t +{ + ZXIC_UINT32 mex_me_demux_cop_rsp_vld_cnt_h; +}DPP_PPU_CLUSTER_MEX_ME_DEMUX_COP_RSP_VLD_CNT_H_T; + +typedef struct dpp_ppu_cluster_me_exception_code0_cnt_l_t +{ + ZXIC_UINT32 me_exception_code0_cnt_l; +}DPP_PPU_CLUSTER_ME_EXCEPTION_CODE0_CNT_L_T; + +typedef struct dpp_ppu_cluster_me_exception_code0_cnt_h_t +{ + ZXIC_UINT32 me_exception_code0_cnt_h; +}DPP_PPU_CLUSTER_ME_EXCEPTION_CODE0_CNT_H_T; + +typedef struct dpp_ppu_cluster_me_exception_code1_cnt_l_t +{ + ZXIC_UINT32 me_exception_code1_cnt_l; +}DPP_PPU_CLUSTER_ME_EXCEPTION_CODE1_CNT_L_T; + +typedef struct dpp_ppu_cluster_me_exception_code1_cnt_h_t +{ + ZXIC_UINT32 me_exception_code1_cnt_h; +}DPP_PPU_CLUSTER_ME_EXCEPTION_CODE1_CNT_H_T; + +typedef struct dpp_ppu_cluster_me_exception_code2_cnt_l_t +{ + ZXIC_UINT32 me_exception_code2_cnt_l; +}DPP_PPU_CLUSTER_ME_EXCEPTION_CODE2_CNT_L_T; + +typedef struct dpp_ppu_cluster_me_exception_code2_cnt_h_t +{ + ZXIC_UINT32 me_exception_code2_cnt_h; +}DPP_PPU_CLUSTER_ME_EXCEPTION_CODE2_CNT_H_T; + +typedef struct dpp_ppu_cluster_me_exception_code3_cnt_l_t +{ + ZXIC_UINT32 me_exception_code3_cnt_l; +}DPP_PPU_CLUSTER_ME_EXCEPTION_CODE3_CNT_L_T; + +typedef struct dpp_ppu_cluster_me_exception_code3_cnt_h_t +{ + ZXIC_UINT32 me_exception_code3_cnt_h; +}DPP_PPU_CLUSTER_ME_EXCEPTION_CODE3_CNT_H_T; + +typedef struct dpp_ppu_cluster_me_exception_code4_cnt_l_t +{ + ZXIC_UINT32 me_exception_code4_cnt_l; +}DPP_PPU_CLUSTER_ME_EXCEPTION_CODE4_CNT_L_T; + +typedef struct dpp_ppu_cluster_me_exception_code4_cnt_h_t +{ + ZXIC_UINT32 me_exception_code4_cnt_h; +}DPP_PPU_CLUSTER_ME_EXCEPTION_CODE4_CNT_H_T; + +typedef struct dpp_ppu_cluster_me_exception_code5_cnt_l_t +{ + ZXIC_UINT32 me_exception_code5_cnt_l; +}DPP_PPU_CLUSTER_ME_EXCEPTION_CODE5_CNT_L_T; + +typedef struct dpp_ppu_cluster_me_exception_code5_cnt_h_t +{ + ZXIC_UINT32 me_exception_code5_cnt_h; +}DPP_PPU_CLUSTER_ME_EXCEPTION_CODE5_CNT_H_T; + + +#ifdef __cplusplus +} +#endif +#endif + diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_ptptm_reg.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_ptptm_reg.h new file mode 100644 index 0000000..db871f4 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_ptptm_reg.h @@ -0,0 +1,895 @@ + +#ifndef _DPP_PTPTM_REG_H_ +#define _DPP_PTPTM_REG_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +typedef struct dpp_ptptm_ptp_top_pp1s_interrupt_t +{ + ZXIC_UINT32 int_state; + ZXIC_UINT32 int_test; + ZXIC_UINT32 int_clr; + ZXIC_UINT32 int_en; +}DPP_PTPTM_PTP_TOP_PP1S_INTERRUPT_T; + +typedef struct dpp_ptptm_ptp_top_pp1s_external_select_t +{ + ZXIC_UINT32 pp1s_external_select; +}DPP_PTPTM_PTP_TOP_PP1S_EXTERNAL_SELECT_T; + +typedef struct dpp_ptptm_ptp_top_pp1s_out_select_t +{ + ZXIC_UINT32 pp1s_out_sel; +}DPP_PTPTM_PTP_TOP_PP1S_OUT_SELECT_T; + +typedef struct dpp_ptptm_ptp_top_test_pp1s_select_t +{ + ZXIC_UINT32 test_pp1s_sel; +}DPP_PTPTM_PTP_TOP_TEST_PP1S_SELECT_T; + +typedef struct dpp_ptptm_ptp_top_local_pp1s_en_t +{ + ZXIC_UINT32 local_pp1s_en; +}DPP_PTPTM_PTP_TOP_LOCAL_PP1S_EN_T; + +typedef struct dpp_ptptm_ptp_top_local_pp1s_adjust_t +{ + ZXIC_UINT32 local_pp1s_adjust_sel; + ZXIC_UINT32 local_pp1s_adjust_en; +}DPP_PTPTM_PTP_TOP_LOCAL_PP1S_ADJUST_T; + +typedef struct dpp_ptptm_ptp_top_local_pp1s_adjust_value_t +{ + ZXIC_UINT32 local_pp1s_adjust_value; +}DPP_PTPTM_PTP_TOP_LOCAL_PP1S_ADJUST_VALUE_T; + +typedef struct dpp_ptptm_ptp_top_pp1s_to_np_select_t +{ + ZXIC_UINT32 pp1s_to_np_sel; +}DPP_PTPTM_PTP_TOP_PP1S_TO_NP_SELECT_T; + +typedef struct dpp_ptptm_ptp_top_pd_u1_sel_t +{ + ZXIC_UINT32 pd_u1_sel1; + ZXIC_UINT32 pd_u1_sel0; +}DPP_PTPTM_PTP_TOP_PD_U1_SEL_T; + +typedef struct dpp_ptptm_ptp_top_pd_u1_pd0_shift_t +{ + ZXIC_UINT32 pd_u1_pd0_shift; +}DPP_PTPTM_PTP_TOP_PD_U1_PD0_SHIFT_T; + +typedef struct dpp_ptptm_ptp_top_pd_u1_pd1_shift_t +{ + ZXIC_UINT32 pd_u1_pd1_shift; +}DPP_PTPTM_PTP_TOP_PD_U1_PD1_SHIFT_T; + +typedef struct dpp_ptptm_ptp_top_pd_u1_result_t +{ + ZXIC_UINT32 pd_u1_result_sign; + ZXIC_UINT32 pd_u1_overflow; + ZXIC_UINT32 pd_u1_result; +}DPP_PTPTM_PTP_TOP_PD_U1_RESULT_T; + +typedef struct dpp_ptptm_ptp_top_pd_u2_sel_t +{ + ZXIC_UINT32 pd_u2_sel1; + ZXIC_UINT32 pd_u2_sel0; +}DPP_PTPTM_PTP_TOP_PD_U2_SEL_T; + +typedef struct dpp_ptptm_ptp_top_pd_u2_pd0_shift_t +{ + ZXIC_UINT32 pd_u2_pd0_shift; +}DPP_PTPTM_PTP_TOP_PD_U2_PD0_SHIFT_T; + +typedef struct dpp_ptptm_ptp_top_pd_u2_pd1_shift_t +{ + ZXIC_UINT32 pd_u2_pd1_shift; +}DPP_PTPTM_PTP_TOP_PD_U2_PD1_SHIFT_T; + +typedef struct dpp_ptptm_ptp_top_pd_u2_result_t +{ + ZXIC_UINT32 pd_u2_result_sign; + ZXIC_UINT32 pd_u2_overflow; + ZXIC_UINT32 pd_u2_result; +}DPP_PTPTM_PTP_TOP_PD_U2_RESULT_T; + +typedef struct dpp_ptptm_ptp_top_tsn_group_nanosecond_delay0_t +{ + ZXIC_UINT32 tsn_group_nanosecond_delay0; +}DPP_PTPTM_PTP_TOP_TSN_GROUP_NANOSECOND_DELAY0_T; + +typedef struct dpp_ptptm_ptp_top_tsn_group_fracnanosecond_delay0_t +{ + ZXIC_UINT32 tsn_group_fracnanosecond_delay0; +}DPP_PTPTM_PTP_TOP_TSN_GROUP_FRACNANOSECOND_DELAY0_T; + +typedef struct dpp_ptptm_ptp_top_tsn_group_nanosecond_delay1_t +{ + ZXIC_UINT32 tsn_group_nanosecond_delay1; +}DPP_PTPTM_PTP_TOP_TSN_GROUP_NANOSECOND_DELAY1_T; + +typedef struct dpp_ptptm_ptp_top_tsn_group_fracnanosecond_delay1_t +{ + ZXIC_UINT32 tsn_group_fracnanosecond_delay1; +}DPP_PTPTM_PTP_TOP_TSN_GROUP_FRACNANOSECOND_DELAY1_T; + +typedef struct dpp_ptptm_ptp_top_tsn_group_nanosecond_delay2_t +{ + ZXIC_UINT32 tsn_group_nanosecond_delay2; +}DPP_PTPTM_PTP_TOP_TSN_GROUP_NANOSECOND_DELAY2_T; + +typedef struct dpp_ptptm_ptp_top_tsn_group_fracnanosecond_delay2_t +{ + ZXIC_UINT32 tsn_group_fracnanosecond_delay2; +}DPP_PTPTM_PTP_TOP_TSN_GROUP_FRACNANOSECOND_DELAY2_T; + +typedef struct dpp_ptptm_ptp_top_tsn_group_nanosecond_delay3_t +{ + ZXIC_UINT32 tsn_group_nanosecond_delay3; +}DPP_PTPTM_PTP_TOP_TSN_GROUP_NANOSECOND_DELAY3_T; + +typedef struct dpp_ptptm_ptp_top_tsn_group_fracnanosecond_delay3_t +{ + ZXIC_UINT32 tsn_group_fracnanosecond_delay3; +}DPP_PTPTM_PTP_TOP_TSN_GROUP_FRACNANOSECOND_DELAY3_T; + +typedef struct dpp_ptptm_ptp_top_tsn_ptp1588_rdma_nanosecond_delay_t +{ + ZXIC_UINT32 ptp1588_rdma_nanosecond_delay; +}DPP_PTPTM_PTP_TOP_TSN_PTP1588_RDMA_NANOSECOND_DELAY_T; + +typedef struct dpp_ptptm_ptp_top_ptp1588_rdma_fracnanosecond_delay_t +{ + ZXIC_UINT32 ptp1588_rdma_fracnanosecond_delay; +}DPP_PTPTM_PTP_TOP_PTP1588_RDMA_FRACNANOSECOND_DELAY_T; + +typedef struct dpp_ptptm_ptp_top_ptp1588_np_nanosecond_delay_t +{ + ZXIC_UINT32 ptp1588_np_nanosecond_delay; +}DPP_PTPTM_PTP_TOP_PTP1588_NP_NANOSECOND_DELAY_T; + +typedef struct dpp_ptptm_ptp_top_ptp1588_np_fracnanosecond_delay_t +{ + ZXIC_UINT32 ptp1588_np_fracnanosecond_delay; +}DPP_PTPTM_PTP_TOP_PTP1588_NP_FRACNANOSECOND_DELAY_T; + +typedef struct dpp_ptptm_ptp_top_time_sync_period_t +{ + ZXIC_UINT32 time_sync_period; +}DPP_PTPTM_PTP_TOP_TIME_SYNC_PERIOD_T; + +typedef struct dpp_ptptm_ptptm_module_id_t +{ + ZXIC_UINT32 module_id; +}DPP_PTPTM_PTPTM_MODULE_ID_T; + +typedef struct dpp_ptptm_ptptm_module_version_t +{ + ZXIC_UINT32 module_major_version; + ZXIC_UINT32 module_minor_version; +}DPP_PTPTM_PTPTM_MODULE_VERSION_T; + +typedef struct dpp_ptptm_ptptm_module_date_t +{ + ZXIC_UINT32 year; + ZXIC_UINT32 month; + ZXIC_UINT32 date; +}DPP_PTPTM_PTPTM_MODULE_DATE_T; + +typedef struct dpp_ptptm_ptptm_interrupt_status_t +{ + ZXIC_UINT32 pps_in_status; + ZXIC_UINT32 fifo_almost_full_status; + ZXIC_UINT32 fifo_no_empty_status; + ZXIC_UINT32 trigger_output_status; + ZXIC_UINT32 trigger_input_status; +}DPP_PTPTM_PTPTM_INTERRUPT_STATUS_T; + +typedef struct dpp_ptptm_ptptm_interrupt_event_t +{ + ZXIC_UINT32 pps_in_event; + ZXIC_UINT32 fifo_almost_full_event; + ZXIC_UINT32 fifo_no_empty_event; + ZXIC_UINT32 trigger_output_event; + ZXIC_UINT32 trigger_input_event; +}DPP_PTPTM_PTPTM_INTERRUPT_EVENT_T; + +typedef struct dpp_ptptm_ptptm_interrupt_mask_t +{ + ZXIC_UINT32 pps_in_event_mask; + ZXIC_UINT32 fifo_almost_full_event_mask; + ZXIC_UINT32 fifo_no_empty_event_mask; + ZXIC_UINT32 trigger_output_event_mask; + ZXIC_UINT32 trigger_input_eventt_mask; +}DPP_PTPTM_PTPTM_INTERRUPT_MASK_T; + +typedef struct dpp_ptptm_ptptm_interrupt_test_t +{ + ZXIC_UINT32 trigger_pps_in_event_test; + ZXIC_UINT32 trigger_fifo_almost_full_event_test; + ZXIC_UINT32 trigger_fifo_no_empty_event_test; + ZXIC_UINT32 trigger_output_event_test; + ZXIC_UINT32 trigger_input_event_test; +}DPP_PTPTM_PTPTM_INTERRUPT_TEST_T; + +typedef struct dpp_ptptm_ptptm_hw_clock_cycle_integer_t +{ + ZXIC_UINT32 integeral_nanosecond_of_hw_clock_cycle; +}DPP_PTPTM_PTPTM_HW_CLOCK_CYCLE_INTEGER_T; + +typedef struct dpp_ptptm_ptptm_hw_clock_cycle_fraction_t +{ + ZXIC_UINT32 fractional_nanosecond_of_hw_clock_cycle; +}DPP_PTPTM_PTPTM_HW_CLOCK_CYCLE_FRACTION_T; + +typedef struct dpp_ptptm_ptptm_ptp_clock_cycle_integer_t +{ + ZXIC_UINT32 integeral_nanosecond_of_ptp_clock_cycle; +}DPP_PTPTM_PTPTM_PTP_CLOCK_CYCLE_INTEGER_T; + +typedef struct dpp_ptptm_ptptm_ptp_clock_cycle_fraction_t +{ + ZXIC_UINT32 fractional_nanosecond_of_ptp_clock_cycle; +}DPP_PTPTM_PTPTM_PTP_CLOCK_CYCLE_FRACTION_T; + +typedef struct dpp_ptptm_ptptm_ptp_configuration_t +{ + ZXIC_UINT32 trig_oe; + ZXIC_UINT32 hw_time_update_en; + ZXIC_UINT32 ptp1588_tod_time_update_en; + ZXIC_UINT32 timer_enable; + ZXIC_UINT32 pps_output_enable; + ZXIC_UINT32 pp1_output_enable; + ZXIC_UINT32 pp2_output_enable; + ZXIC_UINT32 enable_writing_timestamps_to_the_fifo; + ZXIC_UINT32 l2s_time_output_select; + ZXIC_UINT32 reserved_9; + ZXIC_UINT32 pps_input_select; + ZXIC_UINT32 pp_output_select; + ZXIC_UINT32 reserved_6; + ZXIC_UINT32 timer_run_mode; + ZXIC_UINT32 update_command_select; + ZXIC_UINT32 trigger_out_enable; + ZXIC_UINT32 trigger_in_enable; + ZXIC_UINT32 timer_capture_slave_mode; +}DPP_PTPTM_PTPTM_PTP_CONFIGURATION_T; + +typedef struct dpp_ptptm_ptptm_timer_control_t +{ + ZXIC_UINT32 ptpmoutputsynchroningstate; + ZXIC_UINT32 ptp1588_fifo_read_command; + ZXIC_UINT32 adjust_the_timer; +}DPP_PTPTM_PTPTM_TIMER_CONTROL_T; + +typedef struct dpp_ptptm_ptptm_pps_income_delay_t +{ + ZXIC_UINT32 pps_income_delay_nanosecond; + ZXIC_UINT32 pps_income_delay_frac_nanosecond; +}DPP_PTPTM_PTPTM_PPS_INCOME_DELAY_T; + +typedef struct dpp_ptptm_ptptm_clock_cycle_update_t +{ + ZXIC_UINT32 tsn3_clock_cycle_update_enable; + ZXIC_UINT32 tsn2_clock_cycle_update_enable; + ZXIC_UINT32 tsn1_clock_cycle_update_enable; + ZXIC_UINT32 tsn0_clock_cycle_update_enable; + ZXIC_UINT32 ptp1588_clock_cycle_update_enable; +}DPP_PTPTM_PTPTM_CLOCK_CYCLE_UPDATE_T; + +typedef struct dpp_ptptm_ptptm_cycle_time_of_output_period_pulse_1_t +{ + ZXIC_UINT32 clock_number_of_output_period_pulse_1; +}DPP_PTPTM_PTPTM_CYCLE_TIME_OF_OUTPUT_PERIOD_PULSE_1_T; + +typedef struct dpp_ptptm_ptptm_cycle_time_of_output_period_pulse_2_t +{ + ZXIC_UINT32 clock_number_of_output_period_pulse_2; +}DPP_PTPTM_PTPTM_CYCLE_TIME_OF_OUTPUT_PERIOD_PULSE_2_T; + +typedef struct dpp_ptptm_ptptm_timer_latch_en_t +{ + ZXIC_UINT32 latch_the_timer_en; +}DPP_PTPTM_PTPTM_TIMER_LATCH_EN_T; + +typedef struct dpp_ptptm_ptptm_timer_latch_sel_t +{ + ZXIC_UINT32 timer_latch_sel; +}DPP_PTPTM_PTPTM_TIMER_LATCH_SEL_T; + +typedef struct dpp_ptptm_ptptm_trigger_in_tod_nanosecond_t +{ + ZXIC_UINT32 trigger_in_tod_nanosecond; +}DPP_PTPTM_PTPTM_TRIGGER_IN_TOD_NANOSECOND_T; + +typedef struct dpp_ptptm_ptptm_trigger_in_lower_tod_second_t +{ + ZXIC_UINT32 trigger_in_lower_tod_second; +}DPP_PTPTM_PTPTM_TRIGGER_IN_LOWER_TOD_SECOND_T; + +typedef struct dpp_ptptm_ptptm_trigger_in_high_tod_second_t +{ + ZXIC_UINT32 trigger_in_high_tod_second; +}DPP_PTPTM_PTPTM_TRIGGER_IN_HIGH_TOD_SECOND_T; + +typedef struct dpp_ptptm_ptptm_trigger_in_fracnanosecond_t +{ + ZXIC_UINT32 trigger_in_fracnanosecond; +}DPP_PTPTM_PTPTM_TRIGGER_IN_FRACNANOSECOND_T; + +typedef struct dpp_ptptm_ptptm_trigger_in_hardware_time_low_t +{ + ZXIC_UINT32 trigger_in_hardware_time_low; +}DPP_PTPTM_PTPTM_TRIGGER_IN_HARDWARE_TIME_LOW_T; + +typedef struct dpp_ptptm_ptptm_trigger_in_hardware_time_high_t +{ + ZXIC_UINT32 trigger_in_hardware_time_high; +}DPP_PTPTM_PTPTM_TRIGGER_IN_HARDWARE_TIME_HIGH_T; + +typedef struct dpp_ptptm_ptptm_trigger_out_tod_nanosecond_t +{ + ZXIC_UINT32 trigger_out_tod_nanosecond; +}DPP_PTPTM_PTPTM_TRIGGER_OUT_TOD_NANOSECOND_T; + +typedef struct dpp_ptptm_ptptm_trigger_out_lower_tod_second_t +{ + ZXIC_UINT32 trigger_out_lower_tod_second; +}DPP_PTPTM_PTPTM_TRIGGER_OUT_LOWER_TOD_SECOND_T; + +typedef struct dpp_ptptm_ptptm_trigger_out_high_tod_second_t +{ + ZXIC_UINT32 trigger_out_high_tod_second; +}DPP_PTPTM_PTPTM_TRIGGER_OUT_HIGH_TOD_SECOND_T; + +typedef struct dpp_ptptm_ptptm_trigger_out_hardware_time_low_t +{ + ZXIC_UINT32 trigger_out_hardware_time_low; +}DPP_PTPTM_PTPTM_TRIGGER_OUT_HARDWARE_TIME_LOW_T; + +typedef struct dpp_ptptm_ptptm_trigger_out_hardware_time_high_t +{ + ZXIC_UINT32 trigger_out_hardware_time_high; +}DPP_PTPTM_PTPTM_TRIGGER_OUT_HARDWARE_TIME_HIGH_T; + +typedef struct dpp_ptptm_ptptm_adjust_tod_nanosecond_t +{ + ZXIC_UINT32 adjust_tod_nanosecond; +}DPP_PTPTM_PTPTM_ADJUST_TOD_NANOSECOND_T; + +typedef struct dpp_ptptm_ptptm_adjust_lower_tod_second_t +{ + ZXIC_UINT32 adjust_lower_tod_second; +}DPP_PTPTM_PTPTM_ADJUST_LOWER_TOD_SECOND_T; + +typedef struct dpp_ptptm_ptptm_adjust_high_tod_second_t +{ + ZXIC_UINT32 adjust_high_tod_second; +}DPP_PTPTM_PTPTM_ADJUST_HIGH_TOD_SECOND_T; + +typedef struct dpp_ptptm_ptptm_adjust_fracnanosecond_t +{ + ZXIC_UINT32 adjust_fracnanosecond; +}DPP_PTPTM_PTPTM_ADJUST_FRACNANOSECOND_T; + +typedef struct dpp_ptptm_ptptm_adjust_hardware_time_low_t +{ + ZXIC_UINT32 adjust_hardware_time_low; +}DPP_PTPTM_PTPTM_ADJUST_HARDWARE_TIME_LOW_T; + +typedef struct dpp_ptptm_ptptm_adjust_hardware_time_high_t +{ + ZXIC_UINT32 adjust_hardware_time_high; +}DPP_PTPTM_PTPTM_ADJUST_HARDWARE_TIME_HIGH_T; + +typedef struct dpp_ptptm_ptptm_latch_tod_nanosecond_t +{ + ZXIC_UINT32 latch_tod_nanosecond; +}DPP_PTPTM_PTPTM_LATCH_TOD_NANOSECOND_T; + +typedef struct dpp_ptptm_ptptm_latch_lower_tod_second_t +{ + ZXIC_UINT32 latch_lower_tod_second; +}DPP_PTPTM_PTPTM_LATCH_LOWER_TOD_SECOND_T; + +typedef struct dpp_ptptm_ptptm_latch_high_tod_second_t +{ + ZXIC_UINT32 latch_high_tod_second; +}DPP_PTPTM_PTPTM_LATCH_HIGH_TOD_SECOND_T; + +typedef struct dpp_ptptm_ptptm_latch_fracnanosecond_t +{ + ZXIC_UINT32 latch_fracnanosecond; +}DPP_PTPTM_PTPTM_LATCH_FRACNANOSECOND_T; + +typedef struct dpp_ptptm_ptptm_latch_hardware_time_low_t +{ + ZXIC_UINT32 latch_hardware_time_low; +}DPP_PTPTM_PTPTM_LATCH_HARDWARE_TIME_LOW_T; + +typedef struct dpp_ptptm_ptptm_latch_hardware_time_high_t +{ + ZXIC_UINT32 latch_hardware_time_high; +}DPP_PTPTM_PTPTM_LATCH_HARDWARE_TIME_HIGH_T; + +typedef struct dpp_ptptm_ptptm_real_tod_nanosecond_t +{ + ZXIC_UINT32 real_tod_nanosecond; +}DPP_PTPTM_PTPTM_REAL_TOD_NANOSECOND_T; + +typedef struct dpp_ptptm_ptptm_real_lower_tod_second_t +{ + ZXIC_UINT32 real_lower_tod_second; +}DPP_PTPTM_PTPTM_REAL_LOWER_TOD_SECOND_T; + +typedef struct dpp_ptptm_ptptm_real_high_tod_second_t +{ + ZXIC_UINT32 real_high_tod_second; +}DPP_PTPTM_PTPTM_REAL_HIGH_TOD_SECOND_T; + +typedef struct dpp_ptptm_ptptm_real_hardware_time_low_t +{ + ZXIC_UINT32 real_hardware_time_low; +}DPP_PTPTM_PTPTM_REAL_HARDWARE_TIME_LOW_T; + +typedef struct dpp_ptptm_ptptm_real_hardware_time_high_t +{ + ZXIC_UINT32 real_hardware_time_high; +}DPP_PTPTM_PTPTM_REAL_HARDWARE_TIME_HIGH_T; + +typedef struct dpp_ptptm_ptptm_ptp1588_event_message_port_t +{ + ZXIC_UINT32 ptp1588_event_message_port; +}DPP_PTPTM_PTPTM_PTP1588_EVENT_MESSAGE_PORT_T; + +typedef struct dpp_ptptm_ptptm_ptp1588_event_message_timestamp_low_t +{ + ZXIC_UINT32 ptp1588_event_message_timestamp_low; +}DPP_PTPTM_PTPTM_PTP1588_EVENT_MESSAGE_TIMESTAMP_LOW_T; + +typedef struct dpp_ptptm_ptptm_ptp1588_event_message_timestamp_high_t +{ + ZXIC_UINT32 ptp1588_event_message_timestamp_high; +}DPP_PTPTM_PTPTM_PTP1588_EVENT_MESSAGE_TIMESTAMP_HIGH_T; + +typedef struct dpp_ptptm_ptptm_ptp1588_event_message_fifo_status_t +{ + ZXIC_UINT32 fifo_full; + ZXIC_UINT32 fifo_empty; + ZXIC_UINT32 timestamps_count; +}DPP_PTPTM_PTPTM_PTP1588_EVENT_MESSAGE_FIFO_STATUS_T; + +typedef struct dpp_ptptm_ptptm_pp1s_latch_tod_nanosecond_t +{ + ZXIC_UINT32 latch_1588tod_nanosecond; +}DPP_PTPTM_PTPTM_PP1S_LATCH_TOD_NANOSECOND_T; + +typedef struct dpp_ptptm_ptptm_pp1s_latch_lower_tod_second_t +{ + ZXIC_UINT32 latch_lower_1588tod_second; +}DPP_PTPTM_PTPTM_PP1S_LATCH_LOWER_TOD_SECOND_T; + +typedef struct dpp_ptptm_ptptm_pp1s_latch_high_tod_second_t +{ + ZXIC_UINT32 latch_high_1588tod_second; +}DPP_PTPTM_PTPTM_PP1S_LATCH_HIGH_TOD_SECOND_T; + +typedef struct dpp_ptptm_ptptm_pp1s_latch_fracnanosecond_t +{ + ZXIC_UINT32 latch_1588fracnanosecond; +}DPP_PTPTM_PTPTM_PP1S_LATCH_FRACNANOSECOND_T; + +typedef struct dpp_ptptm_ptptm_tsn_time_configuration_t +{ + ZXIC_UINT32 tsn_pps_enable; + ZXIC_UINT32 tsn_timer_enable; + ZXIC_UINT32 tsn_timer_run_mode; + ZXIC_UINT32 timer_capture_slave_mode; +}DPP_PTPTM_PTPTM_TSN_TIME_CONFIGURATION_T; + +typedef struct dpp_ptptm_ptptm_tsn_timer_control_t +{ + ZXIC_UINT32 adjust_the_tsn3_timer; + ZXIC_UINT32 adjust_the_tsn2_timer; + ZXIC_UINT32 adjust_the_tsn1_timer; + ZXIC_UINT32 adjust_the_tsn0_timer; +}DPP_PTPTM_PTPTM_TSN_TIMER_CONTROL_T; + +typedef struct dpp_ptptm_ptptm_tsn0_clock_cycle_integer_t +{ + ZXIC_UINT32 integeral_nanosecond_of_tsn0_clock_cycle; +}DPP_PTPTM_PTPTM_TSN0_CLOCK_CYCLE_INTEGER_T; + +typedef struct dpp_ptptm_ptptm_tsn0_clock_cycle_fraction_t +{ + ZXIC_UINT32 fractional_nanosecond_of_tsn0_clock_cycle; +}DPP_PTPTM_PTPTM_TSN0_CLOCK_CYCLE_FRACTION_T; + +typedef struct dpp_ptptm_ptptm_tsn1_clock_cycle_integer_t +{ + ZXIC_UINT32 integeral_nanosecond_of_tsn1_clock_cycle; +}DPP_PTPTM_PTPTM_TSN1_CLOCK_CYCLE_INTEGER_T; + +typedef struct dpp_ptptm_ptptm_tsn1_clock_cycle_fraction_t +{ + ZXIC_UINT32 fractional_nanosecond_of_tsn1_clock_cycle; +}DPP_PTPTM_PTPTM_TSN1_CLOCK_CYCLE_FRACTION_T; + +typedef struct dpp_ptptm_ptptm_tsn2_clock_cycle_integer_t +{ + ZXIC_UINT32 integeral_nanosecond_of_tsn2_clock_cycle; +}DPP_PTPTM_PTPTM_TSN2_CLOCK_CYCLE_INTEGER_T; + +typedef struct dpp_ptptm_ptptm_tsn2_clock_cycle_fraction_t +{ + ZXIC_UINT32 fractional_nanosecond_of_tsn2_clock_cycle; +}DPP_PTPTM_PTPTM_TSN2_CLOCK_CYCLE_FRACTION_T; + +typedef struct dpp_ptptm_ptptm_tsn3_clock_cycle_integer_t +{ + ZXIC_UINT32 integeral_nanosecond_of_tsn3_clock_cycle; +}DPP_PTPTM_PTPTM_TSN3_CLOCK_CYCLE_INTEGER_T; + +typedef struct dpp_ptptm_ptptm_tsn3_clock_cycle_fraction_t +{ + ZXIC_UINT32 fractional_nanosecond_of_tsn3_clock_cycle; +}DPP_PTPTM_PTPTM_TSN3_CLOCK_CYCLE_FRACTION_T; + +typedef struct dpp_ptptm_ptptm_tsn0_adjust_tod_nanosecond_t +{ + ZXIC_UINT32 tsn0_adjust_tod_nanosecond; +}DPP_PTPTM_PTPTM_TSN0_ADJUST_TOD_NANOSECOND_T; + +typedef struct dpp_ptptm_ptptm_tsn0_adjust_lower_tod_second_t +{ + ZXIC_UINT32 tsn0_adjust_lower_tod_second; +}DPP_PTPTM_PTPTM_TSN0_ADJUST_LOWER_TOD_SECOND_T; + +typedef struct dpp_ptptm_ptptm_tsn0_adjust_high_tod_second_t +{ + ZXIC_UINT32 tsn0_adjust_high_tod_second; +}DPP_PTPTM_PTPTM_TSN0_ADJUST_HIGH_TOD_SECOND_T; + +typedef struct dpp_ptptm_ptptm_tsn0_adjust_fracnanosecond_t +{ + ZXIC_UINT32 tsn0_adjust_fracnanosecond; +}DPP_PTPTM_PTPTM_TSN0_ADJUST_FRACNANOSECOND_T; + +typedef struct dpp_ptptm_ptptm_tsn1_adjust_tod_nanosecond_t +{ + ZXIC_UINT32 tsn1_adjust_tod_nanosecond; +}DPP_PTPTM_PTPTM_TSN1_ADJUST_TOD_NANOSECOND_T; + +typedef struct dpp_ptptm_ptptm_tsn1_adjust_lower_tod_second_t +{ + ZXIC_UINT32 tsn1_adjust_lower_tod_second; +}DPP_PTPTM_PTPTM_TSN1_ADJUST_LOWER_TOD_SECOND_T; + +typedef struct dpp_ptptm_ptptm_tsn1_adjust_high_tod_second_t +{ + ZXIC_UINT32 tsn1_adjust_high_tod_second; +}DPP_PTPTM_PTPTM_TSN1_ADJUST_HIGH_TOD_SECOND_T; + +typedef struct dpp_ptptm_ptptm_tsn1_adjust_fracnanosecond_t +{ + ZXIC_UINT32 tsn1_adjust_fracnanosecond; +}DPP_PTPTM_PTPTM_TSN1_ADJUST_FRACNANOSECOND_T; + +typedef struct dpp_ptptm_ptptm_tsn2_adjust_tod_nanosecond_t +{ + ZXIC_UINT32 tsn2_adjust_tod_nanosecond; +}DPP_PTPTM_PTPTM_TSN2_ADJUST_TOD_NANOSECOND_T; + +typedef struct dpp_ptptm_ptptm_tsn2_adjust_lower_tod_second_t +{ + ZXIC_UINT32 tsn2_adjust_lower_tod_second; +}DPP_PTPTM_PTPTM_TSN2_ADJUST_LOWER_TOD_SECOND_T; + +typedef struct dpp_ptptm_ptptm_tsn2_adjust_high_tod_second_t +{ + ZXIC_UINT32 tsn2_adjust_high_tod_second; +}DPP_PTPTM_PTPTM_TSN2_ADJUST_HIGH_TOD_SECOND_T; + +typedef struct dpp_ptptm_ptptm_tsn2_adjust_fracnanosecond_t +{ + ZXIC_UINT32 tsn2_adjust_fracnanosecond; +}DPP_PTPTM_PTPTM_TSN2_ADJUST_FRACNANOSECOND_T; + +typedef struct dpp_ptptm_ptptm_tsn3_adjust_tod_nanosecond_t +{ + ZXIC_UINT32 tsn3_adjust_tod_nanosecond; +}DPP_PTPTM_PTPTM_TSN3_ADJUST_TOD_NANOSECOND_T; + +typedef struct dpp_ptptm_ptptm_tsn3_adjust_lower_tod_second_t +{ + ZXIC_UINT32 tsn3_adjust_lower_tod_second; +}DPP_PTPTM_PTPTM_TSN3_ADJUST_LOWER_TOD_SECOND_T; + +typedef struct dpp_ptptm_ptptm_tsn3_adjust_high_tod_second_t +{ + ZXIC_UINT32 tsn3_adjust_high_tod_second; +}DPP_PTPTM_PTPTM_TSN3_ADJUST_HIGH_TOD_SECOND_T; + +typedef struct dpp_ptptm_ptptm_tsn3_adjust_fracnanosecond_t +{ + ZXIC_UINT32 tsn3_adjust_fracnanosecond; +}DPP_PTPTM_PTPTM_TSN3_ADJUST_FRACNANOSECOND_T; + +typedef struct dpp_ptptm_ptptm_tsn0_latch_tod_nanosecond_t +{ + ZXIC_UINT32 tsn0_latch_tod_nanosecond; +}DPP_PTPTM_PTPTM_TSN0_LATCH_TOD_NANOSECOND_T; + +typedef struct dpp_ptptm_ptptm_tsn0_latch_lower_tod_second_t +{ + ZXIC_UINT32 tsn0_latch_lower_tod_second; +}DPP_PTPTM_PTPTM_TSN0_LATCH_LOWER_TOD_SECOND_T; + +typedef struct dpp_ptptm_ptptm_tsn0_latch_high_tod_second_t +{ + ZXIC_UINT32 tsn0_latch_high_tod_second; +}DPP_PTPTM_PTPTM_TSN0_LATCH_HIGH_TOD_SECOND_T; + +typedef struct dpp_ptptm_ptptm_tsn0_latch_fracnanosecond_t +{ + ZXIC_UINT32 tsn0_latch_fracnanosecond; +}DPP_PTPTM_PTPTM_TSN0_LATCH_FRACNANOSECOND_T; + +typedef struct dpp_ptptm_ptptm_tsn1_latch_tod_nanosecond_t +{ + ZXIC_UINT32 tsn1_latch_tod_nanosecond; +}DPP_PTPTM_PTPTM_TSN1_LATCH_TOD_NANOSECOND_T; + +typedef struct dpp_ptptm_ptptm_tsn1_latch_lower_tod_second_t +{ + ZXIC_UINT32 tsn1_latch_lower_tod_second; +}DPP_PTPTM_PTPTM_TSN1_LATCH_LOWER_TOD_SECOND_T; + +typedef struct dpp_ptptm_ptptm_tsn1_latch_high_tod_second_t +{ + ZXIC_UINT32 tsn1_latch_high_tod_second; +}DPP_PTPTM_PTPTM_TSN1_LATCH_HIGH_TOD_SECOND_T; + +typedef struct dpp_ptptm_ptptm_tsn1_latch_fracnanosecond_t +{ + ZXIC_UINT32 tsn1_latch_fracnanosecond; +}DPP_PTPTM_PTPTM_TSN1_LATCH_FRACNANOSECOND_T; + +typedef struct dpp_ptptm_ptptm_tsn2_latch_tod_nanosecond_t +{ + ZXIC_UINT32 tsn2_latch_tod_nanosecond; +}DPP_PTPTM_PTPTM_TSN2_LATCH_TOD_NANOSECOND_T; + +typedef struct dpp_ptptm_ptptm_tsn2_latch_lower_tod_second_t +{ + ZXIC_UINT32 tsn2_latch_lower_tod_second; +}DPP_PTPTM_PTPTM_TSN2_LATCH_LOWER_TOD_SECOND_T; + +typedef struct dpp_ptptm_ptptm_tsn2_latch_high_tod_second_t +{ + ZXIC_UINT32 tsn2_latch_high_tod_second; +}DPP_PTPTM_PTPTM_TSN2_LATCH_HIGH_TOD_SECOND_T; + +typedef struct dpp_ptptm_ptptm_tsn2_latch_fracnanosecond_t +{ + ZXIC_UINT32 tsn2_latch_fracnanosecond; +}DPP_PTPTM_PTPTM_TSN2_LATCH_FRACNANOSECOND_T; + +typedef struct dpp_ptptm_ptptm_tsn3_latch_tod_nanosecond_t +{ + ZXIC_UINT32 tsn3_latch_tod_nanosecond; +}DPP_PTPTM_PTPTM_TSN3_LATCH_TOD_NANOSECOND_T; + +typedef struct dpp_ptptm_ptptm_tsn3_latch_lower_tod_second_t +{ + ZXIC_UINT32 tsn3_latch_lower_tod_second; +}DPP_PTPTM_PTPTM_TSN3_LATCH_LOWER_TOD_SECOND_T; + +typedef struct dpp_ptptm_ptptm_tsn3_latch_high_tod_second_t +{ + ZXIC_UINT32 tsn3_latch_high_tod_second; +}DPP_PTPTM_PTPTM_TSN3_LATCH_HIGH_TOD_SECOND_T; + +typedef struct dpp_ptptm_ptptm_tsn3_latch_fracnanosecond_t +{ + ZXIC_UINT32 tsn3_latch_fracnanosecond; +}DPP_PTPTM_PTPTM_TSN3_LATCH_FRACNANOSECOND_T; + +typedef struct dpp_ptptm_ptptm_pp1s_latch_tsn0_tod_nanosecond_t +{ + ZXIC_UINT32 latch_tsn0_tod_nanosecond; +}DPP_PTPTM_PTPTM_PP1S_LATCH_TSN0_TOD_NANOSECOND_T; + +typedef struct dpp_ptptm_ptptm_pp1s_latch_tsn0_lower_tod_second_t +{ + ZXIC_UINT32 latch_lower_tsn0_tod_second; +}DPP_PTPTM_PTPTM_PP1S_LATCH_TSN0_LOWER_TOD_SECOND_T; + +typedef struct dpp_ptptm_ptptm_pp1s_latch_tsn0_high_tod_second_t +{ + ZXIC_UINT32 latch_high_tsn0_tod_second; +}DPP_PTPTM_PTPTM_PP1S_LATCH_TSN0_HIGH_TOD_SECOND_T; + +typedef struct dpp_ptptm_ptptm_pp1s_latch_tsn0_fracnanosecond_t +{ + ZXIC_UINT32 latch_tsn0_fracnanosecond; +}DPP_PTPTM_PTPTM_PP1S_LATCH_TSN0_FRACNANOSECOND_T; + +typedef struct dpp_ptptm_ptptm_pp1s_latch_tsn1_tod_nanosecond_t +{ + ZXIC_UINT32 latch_tsn1_tod_nanosecond; +}DPP_PTPTM_PTPTM_PP1S_LATCH_TSN1_TOD_NANOSECOND_T; + +typedef struct dpp_ptptm_ptptm_pp1s_latch_tsn1_lower_tod_second_t +{ + ZXIC_UINT32 latch_lower_tsn1_tod_second; +}DPP_PTPTM_PTPTM_PP1S_LATCH_TSN1_LOWER_TOD_SECOND_T; + +typedef struct dpp_ptptm_ptptm_pp1s_latch_tsn1_high_tod_second_t +{ + ZXIC_UINT32 latch_high_tsn1_tod_second; +}DPP_PTPTM_PTPTM_PP1S_LATCH_TSN1_HIGH_TOD_SECOND_T; + +typedef struct dpp_ptptm_ptptm_pp1s_latch_tsn1_fracnanosecond_t +{ + ZXIC_UINT32 latch_tsn1_fracnanosecond; +}DPP_PTPTM_PTPTM_PP1S_LATCH_TSN1_FRACNANOSECOND_T; + +typedef struct dpp_ptptm_ptptm_pp1s_latch_tsn2_tod_nanosecond_t +{ + ZXIC_UINT32 latch_tsn2_tod_nanosecond; +}DPP_PTPTM_PTPTM_PP1S_LATCH_TSN2_TOD_NANOSECOND_T; + +typedef struct dpp_ptptm_ptptm_pp1s_latch_tsn2_lower_tod_second_t +{ + ZXIC_UINT32 latch_lower_tsn2_tod_second; +}DPP_PTPTM_PTPTM_PP1S_LATCH_TSN2_LOWER_TOD_SECOND_T; + +typedef struct dpp_ptptm_ptptm_pp1s_latch_tsn2_high_tod_second_t +{ + ZXIC_UINT32 latch_high_tsn2_tod_second; +}DPP_PTPTM_PTPTM_PP1S_LATCH_TSN2_HIGH_TOD_SECOND_T; + +typedef struct dpp_ptptm_ptptm_pp1s_latch_tsn2_fracnanosecond_t +{ + ZXIC_UINT32 latch_tsn2_fracnanosecond; +}DPP_PTPTM_PTPTM_PP1S_LATCH_TSN2_FRACNANOSECOND_T; + +typedef struct dpp_ptptm_ptptm_pp1s_latch_tsn3_tod_nanosecond_t +{ + ZXIC_UINT32 latch_tsn3_tod_nanosecond; +}DPP_PTPTM_PTPTM_PP1S_LATCH_TSN3_TOD_NANOSECOND_T; + +typedef struct dpp_ptptm_ptptm_pp1s_latch_tsn3_lower_tod_second_t +{ + ZXIC_UINT32 latch_lower_tsn3_tod_second; +}DPP_PTPTM_PTPTM_PP1S_LATCH_TSN3_LOWER_TOD_SECOND_T; + +typedef struct dpp_ptptm_ptptm_pp1s_latch_tsn3_high_tod_second_t +{ + ZXIC_UINT32 latch_high_tsn3_tod_second; +}DPP_PTPTM_PTPTM_PP1S_LATCH_TSN3_HIGH_TOD_SECOND_T; + +typedef struct dpp_ptptm_ptptm_pp1s_latch_tsn3_fracnanosecond_t +{ + ZXIC_UINT32 latch_tsn3_fracnanosecond; +}DPP_PTPTM_PTPTM_PP1S_LATCH_TSN3_FRACNANOSECOND_T; + +typedef struct dpp_ptptm_ptptm_tsn0_real_tod_nanosecond_t +{ + ZXIC_UINT32 tsn0_real_tod_nanosecond; +}DPP_PTPTM_PTPTM_TSN0_REAL_TOD_NANOSECOND_T; + +typedef struct dpp_ptptm_ptptm_tsn0_real_lower_tod_second_t +{ + ZXIC_UINT32 tsn0_real_lower_tod_second; +}DPP_PTPTM_PTPTM_TSN0_REAL_LOWER_TOD_SECOND_T; + +typedef struct dpp_ptptm_ptptm_tsn0_real_high_tod_second_t +{ + ZXIC_UINT32 tsn0_real_high_tod_second; +}DPP_PTPTM_PTPTM_TSN0_REAL_HIGH_TOD_SECOND_T; + +typedef struct dpp_ptptm_ptptm_tsn1_real_tod_nanosecond_t +{ + ZXIC_UINT32 tsn1_real_tod_nanosecond; +}DPP_PTPTM_PTPTM_TSN1_REAL_TOD_NANOSECOND_T; + +typedef struct dpp_ptptm_ptptm_tsn1_real_lower_tod_second_t +{ + ZXIC_UINT32 tsn1_real_lower_tod_second; +}DPP_PTPTM_PTPTM_TSN1_REAL_LOWER_TOD_SECOND_T; + +typedef struct dpp_ptptm_ptptm_tsn1_real_high_tod_second_t +{ + ZXIC_UINT32 tsn1_real_high_tod_second; +}DPP_PTPTM_PTPTM_TSN1_REAL_HIGH_TOD_SECOND_T; + +typedef struct dpp_ptptm_ptptm_tsn2_real_tod_nanosecond_t +{ + ZXIC_UINT32 tsn2_real_tod_nanosecond; +}DPP_PTPTM_PTPTM_TSN2_REAL_TOD_NANOSECOND_T; + +typedef struct dpp_ptptm_ptptm_tsn2_real_lower_tod_second_t +{ + ZXIC_UINT32 tsn2_real_lower_tod_second; +}DPP_PTPTM_PTPTM_TSN2_REAL_LOWER_TOD_SECOND_T; + +typedef struct dpp_ptptm_ptptm_tsn2_real_high_tod_second_t +{ + ZXIC_UINT32 tsn2_real_high_tod_second; +}DPP_PTPTM_PTPTM_TSN2_REAL_HIGH_TOD_SECOND_T; + +typedef struct dpp_ptptm_ptptm_tsn3_real_tod_nanosecond_t +{ + ZXIC_UINT32 tsn3_real_tod_nanosecond; +}DPP_PTPTM_PTPTM_TSN3_REAL_TOD_NANOSECOND_T; + +typedef struct dpp_ptptm_ptptm_tsn3_real_lower_tod_second_t +{ + ZXIC_UINT32 tsn3_real_lower_tod_second; +}DPP_PTPTM_PTPTM_TSN3_REAL_LOWER_TOD_SECOND_T; + +typedef struct dpp_ptptm_ptptm_tsn3_real_high_tod_second_t +{ + ZXIC_UINT32 tsn3_real_high_tod_second; +}DPP_PTPTM_PTPTM_TSN3_REAL_HIGH_TOD_SECOND_T; + +typedef struct dpp_ptptm_ptptm_real_ptp_clock_cycle_integer_t +{ + ZXIC_UINT32 integeral_nanosecond_of_real_ptp_clock_cycle; +}DPP_PTPTM_PTPTM_REAL_PTP_CLOCK_CYCLE_INTEGER_T; + +typedef struct dpp_ptptm_ptptm_real_ptp_clock_cycle_fraction_t +{ + ZXIC_UINT32 fractional_nanosecond_of_real_ptp_clock_cycle; +}DPP_PTPTM_PTPTM_REAL_PTP_CLOCK_CYCLE_FRACTION_T; + +typedef struct dpp_ptptm_ptptm_real_tsn0_clock_cycle_integer_t +{ + ZXIC_UINT32 integeral_nanosecond_of_real_tsn0_clock_cycle; +}DPP_PTPTM_PTPTM_REAL_TSN0_CLOCK_CYCLE_INTEGER_T; + +typedef struct dpp_ptptm_ptptm_real_tsn0_clock_cycle_fraction_t +{ + ZXIC_UINT32 fractional_nanosecond_of_real_tsn0_clock_cycle; +}DPP_PTPTM_PTPTM_REAL_TSN0_CLOCK_CYCLE_FRACTION_T; + +typedef struct dpp_ptptm_ptptm_real_tsn1_clock_cycle_integer_t +{ + ZXIC_UINT32 integeral_nanosecond_of_real_tsn1_clock_cycle; +}DPP_PTPTM_PTPTM_REAL_TSN1_CLOCK_CYCLE_INTEGER_T; + +typedef struct dpp_ptptm_ptptm_real_tsn1_clock_cycle_fraction_t +{ + ZXIC_UINT32 fractional_nanosecond_of_real_tsn1_clock_cycle; +}DPP_PTPTM_PTPTM_REAL_TSN1_CLOCK_CYCLE_FRACTION_T; + +typedef struct dpp_ptptm_ptptm_real_tsn2_clock_cycle_integer_t +{ + ZXIC_UINT32 integeral_nanosecond_of_real_tsn2_clock_cycle; +}DPP_PTPTM_PTPTM_REAL_TSN2_CLOCK_CYCLE_INTEGER_T; + +typedef struct dpp_ptptm_ptptm_real_tsn2_clock_cycle_fraction_t +{ + ZXIC_UINT32 fractional_nanosecond_of_real_tsn2_clock_cycle; +}DPP_PTPTM_PTPTM_REAL_TSN2_CLOCK_CYCLE_FRACTION_T; + +typedef struct dpp_ptptm_ptptm_real_tsn3_clock_cycle_integer_t +{ + ZXIC_UINT32 integeral_nanosecond_of_real_tsn3_clock_cycle; +}DPP_PTPTM_PTPTM_REAL_TSN3_CLOCK_CYCLE_INTEGER_T; + +typedef struct dpp_ptptm_ptptm_real_tsn3_clock_cycle_fraction_t +{ + ZXIC_UINT32 fractional_nanosecond_of_real_tsn3_clock_cycle; +}DPP_PTPTM_PTPTM_REAL_TSN3_CLOCK_CYCLE_FRACTION_T; + + +#ifdef __cplusplus +} +#endif +#endif + diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_reg.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_reg.h new file mode 100755 index 0000000..19d4591 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_reg.h @@ -0,0 +1,62 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_reg.h +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : 王春雷 +* 完成日期 : 2014/03/18 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ + +#ifndef _DPP_REG_H_ +#define _DPP_REG_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "dpp_reg_struct.h" +#include "dpp_reg_info.h" +#include "dpp_reg_api.h" +#include "dpp_module.h" + + +#include "dpp_cfg_reg.h" +#include "dpp_etm_reg.h" +#include "dpp_nppu_reg.h" +#include "dpp_ppu_reg.h" +#include "dpp_smmu0_reg.h" +#include "dpp_smmu1_reg.h" +#include "dpp_se_reg.h" +#include "dpp_stat_reg.h" +#include "dpp_axi_reg.h" +#include "dpp_dtb_reg.h" +#include "dpp_trpg_reg.h" +#include "dpp_tsn_reg.h" +#include "dpp_ptptm_reg.h" + + +#include "zxic_comm_socket.h" +#include "zxic_comm_thread.h" + + + +#ifdef __cplusplus +} +#endif + +#endif + + + + + diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_reg_info.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_reg_info.h new file mode 100644 index 0000000..6a46639 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_reg_info.h @@ -0,0 +1,4458 @@ + +#ifndef _DPP_REG_INFO_H_ +#define _DPP_REG_INFO_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +typedef enum dpp_reg_info_e +{ + ETM_CFGMT_CPU_CHECK_REGr = 0, + ETM_CFGMT_CFGMT_BLKSIZEr = 1, + ETM_CFGMT_REG_INT_STATE_REGr = 2, + ETM_CFGMT_REG_INT_MASK_REGr = 3, + ETM_CFGMT_TIMEOUT_LIMITr = 4, + ETM_CFGMT_SUBSYSTEM_RDY_REGr = 5, + ETM_CFGMT_SUBSYSTEM_EN_REGr = 6, + ETM_CFGMT_CFGMT_INT_REGr = 7, + ETM_CFGMT_QMU_WORK_MODEr = 8, + ETM_CFGMT_CFGMT_DDR_ATTACHr = 9, + ETM_CFGMT_CNT_MODE_REGr = 10, + ETM_CFGMT_CLKGATE_ENr = 11, + ETM_CFGMT_SOFTRST_ENr = 12, + ETM_OLIF_IMEM_PROG_FULLr = 13, + ETM_OLIF_QMU_PARA_PROG_FULLr = 14, + ETM_OLIF_OLIF_INT_MASKr = 15, + ETM_OLIF_ITMHRAM_PARITY_ERR_2_INTr = 16, + ETM_OLIF_LIF0_PORT_RDY_MASK_Hr = 17, + ETM_OLIF_LIF0_PORT_RDY_MASK_Lr = 18, + ETM_OLIF_LIF0_PORT_RDY_CFG_Hr = 19, + ETM_OLIF_LIF0_PORT_RDY_CFG_Lr = 20, + ETM_OLIF_LIF0_LINK_RDY_MASK_CFGr = 21, + ETM_OLIF_TM_LIF_STAT_CFGr = 22, + ETM_OLIF_TM_LIF_SOP_STATr = 23, + ETM_OLIF_TM_LIF_EOP_STATr = 24, + ETM_OLIF_TM_LIF_VLD_STATr = 25, + ETM_CGAVD_PROG_FULL_ASSERT_CFGr = 26, + ETM_CGAVD_CGAVD_INTr = 27, + ETM_CGAVD_CGAVD_RAM_ERRr = 28, + ETM_CGAVD_CGAVD_INT_MASKr = 29, + ETM_CGAVD_CGAVD_RAM_ERR_INT_MASKr = 30, + ETM_CGAVD_CFGMT_BYTE_MODEr = 31, + ETM_CGAVD_AVG_QLEN_RETURN_ZERO_ENr = 32, + ETM_CGAVD_FLOW_WRED_Q_LEN_THr = 33, + ETM_CGAVD_FLOW_WQr = 34, + ETM_CGAVD_FLOW_WRED_MAX_THr = 35, + ETM_CGAVD_FLOW_WRED_MIN_THr = 36, + ETM_CGAVD_FLOW_WRED_CFG_PARAr = 37, + ETM_CGAVD_PP_AVG_Q_LENr = 38, + ETM_CGAVD_PP_TD_THr = 39, + ETM_CGAVD_PP_CA_MTDr = 40, + ETM_CGAVD_PP_WRED_GRP_TH_ENr = 41, + ETM_CGAVD_PP_WRED_Q_LEN_THr = 42, + ETM_CGAVD_PP_WQr = 43, + ETM_CGAVD_PP_WRED_MAX_THr = 44, + ETM_CGAVD_PP_WRED_MIN_THr = 45, + ETM_CGAVD_PP_CFG_PARAr = 46, + ETM_CGAVD_SYS_AVG_Q_LENr = 47, + ETM_CGAVD_SYS_TD_THr = 48, + ETM_CGAVD_SYS_CGAVD_METDr = 49, + ETM_CGAVD_SYS_CFG_Q_GRP_PARAr = 50, + ETM_CGAVD_SYS_WQr = 51, + ETM_CGAVD_GRED_MAX_THr = 52, + ETM_CGAVD_GRED_MID_THr = 53, + ETM_CGAVD_GRED_MIN_THr = 54, + ETM_CGAVD_GRED_CFG_PARA0r = 55, + ETM_CGAVD_GRED_CFG_PARA1r = 56, + ETM_CGAVD_GRED_CFG_PARA2r = 57, + ETM_CGAVD_SYS_WINDOW_TH_Hr = 58, + ETM_CGAVD_SYS_WINDOW_TH_Lr = 59, + ETM_CGAVD_AMPLIFY_GENE0r = 60, + ETM_CGAVD_AMPLIFY_GENE1r = 61, + ETM_CGAVD_AMPLIFY_GENE2r = 62, + ETM_CGAVD_AMPLIFY_GENE3r = 63, + ETM_CGAVD_AMPLIFY_GENE4r = 64, + ETM_CGAVD_AMPLIFY_GENE5r = 65, + ETM_CGAVD_AMPLIFY_GENE6r = 66, + ETM_CGAVD_AMPLIFY_GENE7r = 67, + ETM_CGAVD_AMPLIFY_GENE8r = 68, + ETM_CGAVD_AMPLIFY_GENE9r = 69, + ETM_CGAVD_AMPLIFY_GENE10r = 70, + ETM_CGAVD_AMPLIFY_GENE11r = 71, + ETM_CGAVD_AMPLIFY_GENE12r = 72, + ETM_CGAVD_AMPLIFY_GENE13r = 73, + ETM_CGAVD_AMPLIFY_GENE14r = 74, + ETM_CGAVD_AMPLIFY_GENE15r = 75, + ETM_CGAVD_EQUAL_PKT_LEN_ENr = 76, + ETM_CGAVD_EQUAL_PKT_LEN_TH0r = 77, + ETM_CGAVD_EQUAL_PKT_LEN_TH1r = 78, + ETM_CGAVD_EQUAL_PKT_LEN_TH2r = 79, + ETM_CGAVD_EQUAL_PKT_LEN_TH3r = 80, + ETM_CGAVD_EQUAL_PKT_LEN_TH4r = 81, + ETM_CGAVD_EQUAL_PKT_LEN_TH5r = 82, + ETM_CGAVD_EQUAL_PKT_LEN_TH6r = 83, + ETM_CGAVD_EQUAL_PKT_LEN0r = 84, + ETM_CGAVD_EQUAL_PKT_LEN1r = 85, + ETM_CGAVD_EQUAL_PKT_LEN2r = 86, + ETM_CGAVD_EQUAL_PKT_LEN3r = 87, + ETM_CGAVD_EQUAL_PKT_LEN4r = 88, + ETM_CGAVD_EQUAL_PKT_LEN5r = 89, + ETM_CGAVD_EQUAL_PKT_LEN6r = 90, + ETM_CGAVD_EQUAL_PKT_LEN7r = 91, + ETM_CGAVD_FLOW_CPU_SET_AVG_LENr = 92, + ETM_CGAVD_FLOW_CPU_SET_Q_LENr = 93, + ETM_CGAVD_PP_CPU_SET_AVG_Q_LENr = 94, + ETM_CGAVD_PP_CPU_SET_Q_LENr = 95, + ETM_CGAVD_SYS_CPU_SET_AVG_LENr = 96, + ETM_CGAVD_SYS_CPU_SET_Q_LENr = 97, + ETM_CGAVD_PKE_LEN_CALC_SIGNr = 98, + ETM_CGAVD_RD_CPU_OR_RAMr = 99, + ETM_CGAVD_Q_LEN_UPDATE_DISABLEr = 100, + ETM_CGAVD_CGAVD_DP_SELr = 101, + ETM_CGAVD_CGAVD_SUB_ENr = 102, + ETM_CGAVD_DEFAULT_START_QUEUEr = 103, + ETM_CGAVD_DEFAULT_FINISH_QUEUEr = 104, + ETM_CGAVD_PROTOCOL_START_QUEUEr = 105, + ETM_CGAVD_PROTOCOL_FINISH_QUEUEr = 106, + ETM_CGAVD_UNIFORM_TD_THr = 107, + ETM_CGAVD_UNIFORM_TD_TH_ENr = 108, + ETM_CGAVD_CGAVD_CFG_FCr = 109, + ETM_CGAVD_CGAVD_CFG_NO_FCr = 110, + ETM_CGAVD_CGAVD_FORCE_IMEM_OMEMr = 111, + ETM_CGAVD_CGAVD_SYS_Q_LEN_Lr = 112, + ETM_CGAVD_DEFAULT_QUEUE_ENr = 113, + ETM_CGAVD_PROTOCOL_QUEUE_ENr = 114, + ETM_CGAVD_CFG_TC_FLOWID_DATr = 115, + ETM_CGAVD_FLOW_TD_THr = 116, + ETM_CGAVD_FLOW_CA_MTDr = 117, + ETM_CGAVD_FLOW_DYNAMIC_TH_ENr = 118, + ETM_CGAVD_PP_NUMr = 119, + ETM_CGAVD_FLOW_Q_LENr = 120, + ETM_CGAVD_FLOW_WRED_GRPr = 121, + ETM_CGAVD_FLOW_AVG_Q_LENr = 122, + ETM_CGAVD_QOS_SIGNr = 123, + ETM_CGAVD_Q_PRIr = 124, + ETM_CGAVD_ODMA_TM_ITMD_RD_LOWr = 125, + ETM_CGAVD_ODMA_TM_ITMD_RD_MIDr = 126, + ETM_CGAVD_ODMA_TM_ITMD_RD_HIGHr = 127, + ETM_CGAVD_CGAVD_STAT_PKT_LENr = 128, + ETM_CGAVD_CGAVD_STAT_QNUMr = 129, + ETM_CGAVD_CGAVD_STAT_DPr = 130, + ETM_CGAVD_FLOW_NUM0r = 131, + ETM_CGAVD_FLOW_NUM1r = 132, + ETM_CGAVD_FLOW_NUM2r = 133, + ETM_CGAVD_FLOW_NUM3r = 134, + ETM_CGAVD_FLOW_NUM4r = 135, + ETM_CGAVD_FLOW0_IMEM_CNTr = 136, + ETM_CGAVD_FLOW1_IMEM_CNTr = 137, + ETM_CGAVD_FLOW2_IMEM_CNTr = 138, + ETM_CGAVD_FLOW3_IMEM_CNTr = 139, + ETM_CGAVD_FLOW4_IMEM_CNTr = 140, + ETM_CGAVD_FLOW0_DROP_CNTr = 141, + ETM_CGAVD_FLOW1_DROP_CNTr = 142, + ETM_CGAVD_FLOW2_DROP_CNTr = 143, + ETM_CGAVD_FLOW3_DROP_CNTr = 144, + ETM_CGAVD_FLOW4_DROP_CNTr = 145, + ETM_CGAVD_FC_COUNT_MODEr = 146, + ETM_CGAVD_QMU_CGAVD_FC_NUMr = 147, + ETM_CGAVD_CGAVD_ODMA_FC_NUMr = 148, + ETM_CGAVD_CFG_OFFSETr = 149, + ETM_TMMU_TMMU_INIT_DONEr = 150, + ETM_TMMU_TMMU_INT_MASK_1r = 151, + ETM_TMMU_TMMU_INT_MASK_2r = 152, + ETM_TMMU_CFGMT_TM_PURE_IMEM_ENr = 153, + ETM_TMMU_CFGMT_FORCE_DDR_RDY_CFGr = 154, + ETM_TMMU_PD_ORDER_FIFO_AFUL_THr = 155, + ETM_TMMU_CACHED_PD_FIFO_AFUL_THr = 156, + ETM_TMMU_WR_CMD_FIFO_AFUL_THr = 157, + ETM_TMMU_IMEM_ENQ_RD_FIFO_AFUL_THr = 158, + ETM_TMMU_IMEM_ENQ_DROP_FIFO_AFUL_THr = 159, + ETM_TMMU_IMEM_DEQ_DROP_FIFO_AFUL_THr = 160, + ETM_TMMU_IMEM_DEQ_RD_FIFO_AFUL_THr = 161, + ETM_TMMU_TMMU_STATES_1r = 162, + ETM_TMMU_TMMU_STATES_2r = 163, + ETM_SHAP_SHAP_IND_CMDr = 164, + ETM_SHAP_SHAP_IND_STAr = 165, + ETM_SHAP_SHAP_IND_DATA0r = 166, + ETM_SHAP_SHAP_IND_DATA1r = 167, + ETM_SHAP_FULL_THRESHOLDr = 168, + ETM_SHAP_EMPTY_THRESHOLDr = 169, + ETM_SHAP_SHAP_STA_INIT_CFGr = 170, + ETM_SHAP_SHAP_CFG_INIT_CFGr = 171, + ETM_SHAP_TOKEN_MODE_SWITCHr = 172, + ETM_SHAP_TOKEN_GRAINr = 173, + ETM_SHAP_CRD_GRAINr = 174, + ETM_SHAP_SHAP_STAT_CTRLr = 175, + ETM_SHAP_TOKEN_STAT_IDr = 176, + ETM_SHAP_TOKEN_STATr = 177, + ETM_SHAP_SHAP_STAT_CLK_CNTr = 178, + ETM_SHAP_SHAP_BUCKET_MAP_TBLr = 179, + ETM_SHAP_BKT_PARA_TBLr = 180, + ETM_CRDT_CREDIT_ENr = 181, + ETM_CRDT_CRT_INTER1r = 182, + ETM_CRDT_DB_TOKENr = 183, + ETM_CRDT_CRS_FLT_CFGr = 184, + ETM_CRDT_TH_SPr = 185, + ETM_CRDT_TH_WFQ_FQr = 186, + ETM_CRDT_TH_WFQ2_FQ2r = 187, + ETM_CRDT_TH_WFQ4_FQ4r = 188, + ETM_CRDT_CFG_STATEr = 189, + ETM_CRDT_CRDT_IND_CMDr = 190, + ETM_CRDT_CRDT_IND_STAr = 191, + ETM_CRDT_CRDT_IND_DATA0r = 192, + ETM_CRDT_CRDT_IND_DATA1r = 193, + ETM_CRDT_CRDT_STATEr = 194, + ETM_CRDT_STAT_QUE_ID_0r = 195, + ETM_CRDT_STAT_QUE_ID_1r = 196, + ETM_CRDT_STAT_QUE_ID_2r = 197, + ETM_CRDT_STAT_QUE_ID_3r = 198, + ETM_CRDT_STAT_QUE_ID_4r = 199, + ETM_CRDT_STAT_QUE_ID_5r = 200, + ETM_CRDT_STAT_QUE_ID_6r = 201, + ETM_CRDT_STAT_QUE_ID_7r = 202, + ETM_CRDT_STAT_QUE_ID_8r = 203, + ETM_CRDT_STAT_QUE_ID_9r = 204, + ETM_CRDT_STAT_QUE_ID_10r = 205, + ETM_CRDT_STAT_QUE_ID_11r = 206, + ETM_CRDT_STAT_QUE_ID_12r = 207, + ETM_CRDT_STAT_QUE_ID_13r = 208, + ETM_CRDT_STAT_QUE_ID_14r = 209, + ETM_CRDT_STAT_QUE_ID_15r = 210, + ETM_CRDT_STAT_QUE_CREDITr = 211, + ETM_CRDT_CRDT_CFG_RAM_INITr = 212, + ETM_CRDT_CRDT_STA_RAM_INITr = 213, + ETM_CRDT_CRS_QUE_IDr = 214, + ETM_CRDT_QMU_CRS_END_STATEr = 215, + ETM_CRDT_SHAP_RDYr = 216, + ETM_CRDT_SHAP_INT_REGr = 217, + ETM_CRDT_SHAP_INT_MASK_REGr = 218, + ETM_CRDT_TOKEN_STATE_ALMOST_EMPTY_THr = 219, + ETM_CRDT_TOKEN_STATE_EMPTY_THr = 220, + ETM_CRDT_FULL_THr = 221, + ETM_CRDT_PP_C_LEVEL_SHAP_ENr = 222, + ETM_CRDT_ENQ_TOKEN_THr = 223, + ETM_CRDT_PP_TOKENQ_LEVEL1_QSTATE_WEIGHT_CIRr = 224, + ETM_CRDT_PP_IDLE_WEIGHT_LEVEL1_CIRr = 225, + ETM_CRDT_RCI_GRADE_TH_0_CFGr = 226, + ETM_CRDT_RCI_GRADE_TH_1_CFGr = 227, + ETM_CRDT_RCI_GRADE_TH_2_CFGr = 228, + ETM_CRDT_RCI_GRADE_TH_3_CFGr = 229, + ETM_CRDT_RCI_GRADE_TH_4_CFGr = 230, + ETM_CRDT_RCI_GRADE_TH_5_CFGr = 231, + ETM_CRDT_RCI_GRADE_TH_6_CFGr = 232, + ETM_CRDT_FLOW_DEL_CMDr = 233, + ETM_CRDT_CNT_CLRr = 234, + ETM_CRDT_CRDT_INT_BUSr = 235, + ETM_CRDT_CRDT_INT_MASKr = 236, + ETM_CRDT_CFG_WEIGHT_TOGETHERr = 237, + ETM_CRDT_WEIGHTr = 238, + ETM_CRDT_DEV_SP_STATEr = 239, + ETM_CRDT_DEV_CRSr = 240, + ETM_CRDT_CONGEST_TOKEN_DISABLE_31_0r = 241, + ETM_CRDT_CONGEST_TOKEN_DISABLE_63_32r = 242, + ETM_CRDT_CRDT_INTERVAL_EN_CFGr = 243, + ETM_CRDT_Q_TOKEN_STAUE_CFGr = 244, + ETM_CRDT_Q_TOKEN_DIST_CNTr = 245, + ETM_CRDT_Q_TOKEN_DEC_CNTr = 246, + ETM_CRDT_PP_WEIGHT_RAMr = 247, + ETM_CRDT_PP_CBS_SHAPE_EN_RAMr = 248, + ETM_CRDT_PP_NEXT_PC_Q_STATE_RAMr = 249, + ETM_CRDT_DEV_INTERVALr = 250, + ETM_CRDT_DEV_WFQ_CNTr = 251, + ETM_CRDT_DEV_WFQ_STATEr = 252, + ETM_CRDT_DEV_ACTIVE_HEAD_PTRr = 253, + ETM_CRDT_DEV_ACTIVE_TAIL_PTRr = 254, + ETM_CRDT_DEV_UNACTIVE_HEAD_PTRr = 255, + ETM_CRDT_DEV_UNACTIVE_TAIL_PTRr = 256, + ETM_CRDT_PP_WEIGHTr = 257, + ETM_CRDT_PP_QUE_STATEr = 258, + ETM_CRDT_PP_NEXT_PTRr = 259, + ETM_CRDT_PP_CFGr = 260, + ETM_CRDT_PP_UP_PTRr = 261, + ETM_CRDT_CREDIT_DROP_NUMr = 262, + ETM_CRDT_SE_ID_LV0r = 263, + ETM_CRDT_SE_ID_LV1r = 264, + ETM_CRDT_SE_ID_LV2r = 265, + ETM_CRDT_SE_ID_LV3r = 266, + ETM_CRDT_SE_ID_LV4r = 267, + ETM_CRDT_QUE_IDr = 268, + ETM_CRDT_SE_INFO_LV0r = 269, + ETM_CRDT_SE_INFO_LV1r = 270, + ETM_CRDT_SE_INFO_LV2r = 271, + ETM_CRDT_SE_INFO_LV3r = 272, + ETM_CRDT_SE_INFO_LV4r = 273, + ETM_CRDT_QUE_STATEr = 274, + ETM_CRDT_EIR_OFF_IN_ADVANCEr = 275, + ETM_CRDT_DOUBLE_LEVEL_SHAP_PREVENTr = 276, + ETM_CRDT_ADD_STORE_CYCLEr = 277, + ETM_CRDT_TFLAG2_WR_FLAG_SUMr = 278, + ETM_CRDT_FLOWQUE_PARA_TBLr = 279, + ETM_CRDT_SE_PARA_TBLr = 280, + ETM_CRDT_FLOWQUE_INS_TBLr = 281, + ETM_CRDT_SE_INS_TBLr = 282, + ETM_CRDT_EIR_CRS_FILTER_TBLr = 283, + ETM_QMU_QCFG_QLIST_CFG_DONEr = 284, + ETM_QMU_QCFG_QSCH_CREDIT_VALUEr = 285, + ETM_QMU_QCFG_QSCH_CRBAL_INIT_VALUEr = 286, + ETM_QMU_QCFG_QSCH_CRBAL_INIT_MASKr = 287, + ETM_QMU_CMDSCH_RD_CMD_AFUL_THr = 288, + ETM_QMU_CFG_PORT_FC_INTERVALr = 289, + ETM_QMU_QCFG_CSCH_AGED_CFGr = 290, + ETM_QMU_QCFG_CSCH_AGED_SCAN_TIMEr = 291, + ETM_QMU_QCFG_QMU_QLIST_STATE_QUERYr = 292, + ETM_QMU_CFGMT_QSCH_CRBAL_DROP_ENr = 293, + ETM_QMU_CFGMT_WLIST_QNUM_FIFO_AFUL_THr = 294, + ETM_QMU_QCFG_CSW_PKT_BLK_MODEr = 295, + ETM_QMU_QCFG_QLIST_RAM_INIT_CANCELr = 296, + ETM_QMU_QCFG_QSCH_CRBAL_TRANSFER_MODEr = 297, + ETM_QMU_QCFG_QLIST_QCLR_INTERVALr = 298, + ETM_QMU_QCFG_QSCH_QCLR_RATEr = 299, + ETM_QMU_QCFG_QLIST_DDR_RANDOMr = 300, + ETM_QMU_CFGMT_QLIST_PDS_FIFO_AFULL_THr = 301, + ETM_QMU_CFGMT_SOP_CMD_FIFO_AFULL_THr = 302, + ETM_QMU_CFGMT_NON_SOP_CMD_FIFO_AFULL_THr = 303, + ETM_QMU_CFGMT_MMU_DATA_FIFO_AFULL_THr = 304, + ETM_QMU_QCFG_QLIST_BANK_EPT_THr = 305, + ETM_QMU_RANDOM_BYPASS_ENr = 306, + ETM_QMU_CFGMT_CRS_SPD_BYPASSr = 307, + ETM_QMU_CFGMT_CRS_INTERVALr = 308, + ETM_QMU_CFG_QSCH_AUTO_CREDIT_CONTROL_ENr = 309, + ETM_QMU_CFG_QSCH_AUTOCRFRSTQUEr = 310, + ETM_QMU_CFG_QSCH_AUTOCRLASTQUEr = 311, + ETM_QMU_CFG_QSCH_AUTOCREDITRATEr = 312, + ETM_QMU_CFG_QSCH_SCANFRSTQUEr = 313, + ETM_QMU_CFG_QSCH_SCANLASTQUEr = 314, + ETM_QMU_CFG_QSCH_SCANRATEr = 315, + ETM_QMU_CFG_QSCH_SCAN_ENr = 316, + ETM_QMU_CFGMT_QSCH_RD_CREDIT_FIFO_RATEr = 317, + ETM_QMU_QCFG_QLIST_BDEPr = 318, + ETM_QMU_QCFG_QLIST_BHEADr = 319, + ETM_QMU_QCFG_QLIST_BTAILr = 320, + ETM_QMU_QCFG_QSCH_SHAP_PARAMr = 321, + ETM_QMU_QCFG_QSCH_SHAP_TOKENr = 322, + ETM_QMU_QCFG_QSCH_SHAP_OFFSETr = 323, + ETM_QMU_QCFG_QSCH_CRS_EIR_THr = 324, + ETM_QMU_QCFG_QSCH_CRS_TH1r = 325, + ETM_QMU_QCFG_QSCH_CRS_TH2r = 326, + ETM_QMU_QCFG_CSCH_CONGEST_THr = 327, + ETM_QMU_QCFG_CSCH_SP_FC_THr = 328, + ETM_QMU_QCFG_CSW_SHAP_PARAMETERr = 329, + ETM_QMU_CFGMT_RD_RELEASE_AFUL_THr = 330, + ETM_QMU_CFGMT_DROP_IMEM_RELEASE_FIFO_AFUL_THr = 331, + ETM_QMU_CFGMT_NNH_RD_BUF_AFUL_THr = 332, + ETM_QMU_CFG_PID_USE_INALLr = 333, + ETM_QMU_CFG_PID_ROUND_THr = 334, + ETM_QMU_CFGMT_CREDIT_FIFO_AFULL_THr = 335, + ETM_QMU_CFGMT_SCAN_FIFO_AFULL_THr = 336, + ETM_QMU_CFGMT_SMALL_FIFO_AFUL_THr = 337, + ETM_QMU_CFGMT_FREE_ADDR_FIFO_AFUL_THr = 338, + ETM_QMU_CFGMT_ENQ_RPT_FIFO_AFUL_THr = 339, + ETM_QMU_QCFG_CSW_SHAP_TOKEN_DEPTHr = 340, + ETM_QMU_QCFG_CSW_SHAP_OFFSET_VALUEr = 341, + ETM_QMU_QCFG_CSW_FC_OFFSET_VALUEr = 342, + ETM_QMU_QMU_INIT_DONE_STATEr = 343, + ETM_QMU_CSW_QCFG_PORT_SHAP_RDY_0r = 344, + ETM_QMU_CSW_QCFG_PORT_SHAP_RDY_1r = 345, + ETM_QMU_QLIST_CFGMT_RAM_INIT_DONEr = 346, + ETM_QMU_QLIST_CFGMT_RAM_ECC_ERRr = 347, + ETM_QMU_QLIST_CFGMT_RAM_SLOT_ERRr = 348, + ETM_QMU_QSCH_CFGMT_RAM_ECCr = 349, + ETM_QMU_QLIST_CFGMT_FIFO_STATEr = 350, + ETM_QMU_QLIST_QCFG_CLR_DONEr = 351, + ETM_QMU_QMU_INT_MASK1r = 352, + ETM_QMU_QMU_INT_MASK2r = 353, + ETM_QMU_QMU_INT_MASK3r = 354, + ETM_QMU_QMU_INT_MASK4r = 355, + ETM_QMU_QMU_INT_MASK5r = 356, + ETM_QMU_QMU_INT_MASK6r = 357, + ETM_QMU_CMD_SCH_CFGMT_FIFO_STATEr = 358, + ETM_QMU_QLIST_R_BCNTr = 359, + ETM_QMU_QSCH_RW_CRBALr = 360, + ETM_QMU_QSCH_RW_CRSr = 361, + ETM_QMU_QSCH_R_WLIST_EMPTYr = 362, + ETM_QMU_QCFG_QLIST_BARAM_RDr = 363, + ETM_QMU_QCFG_QSCH_CRBAL_FB_RWr = 364, + ETM_QMU_QCFG_QLIST_GRP0_BANKr = 365, + ETM_QMU_QCFG_QLIST_GRP1_BANKr = 366, + ETM_QMU_QCFG_QLIST_GRP2_BANKr = 367, + ETM_QMU_QCFG_QLIST_GRP3_BANKr = 368, + ETM_QMU_QCFG_QLIST_GRP4_BANKr = 369, + ETM_QMU_QCFG_QLIST_GRP5_BANKr = 370, + ETM_QMU_QCFG_QLIST_GRP6_BANKr = 371, + ETM_QMU_QCFG_QLIST_GRP7_BANKr = 372, + ETM_QMU_QCFG_QLIST_GRPr = 373, + ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFGr = 374, + ETM_QMU_CFGMT_DDR_IN_MMU_CFGr = 375, + ETM_QMU_CFGMT_DDR_IN_QMU_CFGr = 376, + ETM_QMU_CFGMT_BANK_TO_MMU_CFGr = 377, + ETM_QMU_CFGMT_BANK_TO_QMU_CFGr = 378, + ETM_QMU_CFGMT_GRP_RAM_N_CLR_THDr = 379, + ETM_QMU_CFGMT_AGE_PKT_NUMr = 380, + ETM_QMU_CFGMT_AGE_MULTI_INTERVALr = 381, + ETM_QMU_CFGMT_QMU_PKT_AGE_ENr = 382, + ETM_QMU_CFGMT_QMU_PKT_AGE_INTERVALr = 383, + ETM_QMU_CFGMT_QMU_PKT_AGE_START_ENDr = 384, + ETM_QMU_CFGMT_PKT_AGE_REQ_AFUL_THr = 385, + ETM_QMU_CFGMT_PKT_AGE_STEP_INTERVALr = 386, + ETM_QMU_CFGMT_QMU_IMEM_AGE_MODEr = 387, + ETM_QMU_CFGMT_QMU_IMEM_QLEN_AGE_INTERVALr = 388, + ETM_QMU_CFGMT_QMU_IMEM_TIME_AGE_INTERVALr = 389, + ETM_QMU_CFGMT_QMU_IMEM_QLEN_AGE_THDr = 390, + ETM_QMU_CFGMT_IMEM_AGE_STEP_INTERVALr = 391, + ETM_QMU_CFGMT_QMU_ECC_BYPASS_READr = 392, + ETM_QMU_CFGMT_QMU_RESP_STAT_FC_ENr = 393, + ETM_QMU_CFGMT_QMU_BANK_XOFF_PDS_MODEr = 394, + ETM_QMU_CFGMT_QMU_STAT_OFFSETr = 395, + ETM_QMU_FC_CNT_MODEr = 396, + ETM_QMU_MMU_QMU_WR_FC_CNTr = 397, + ETM_QMU_MMU_QMU_RD_FC_CNTr = 398, + ETM_QMU_QMU_CGAVD_FC_CNTr = 399, + ETM_QMU_CGAVD_QMU_PKT_CNTr = 400, + ETM_QMU_CGAVD_QMU_PKTLEN_ALLr = 401, + ETM_QMU_OBSERVE_PORTFC_SPECr = 402, + ETM_QMU_SPEC_LIF_PORTFC_COUNTr = 403, + ETM_QMU_CFGMT_QMU_PFC_ENr = 404, + ETM_QMU_CFGMT_QMU_PFC_MASK_1r = 405, + ETM_QMU_CFGMT_QMU_PFC_MASK_2r = 406, + CFG_PCIE_INT_REPEATr = 407, + CFG_DMA_DMA_UP_SIZEr = 408, + CFG_CSR_SOC_WR_TIME_OUT_THRESHr = 409, + NPPU_MR_CFG_CFG_SHAP_PARAMr = 410, + NPPU_MR_CFG_CFG_SHAP_TOKENr = 411, + NPPU_MR_CFG_IDLE_PTR_FIFO_AFUL_THr = 412, + NPPU_MR_CFG_MR_COS_PORT_CFGr = 413, + NPPU_PKTRX_CFG_IND_STATUSr = 414, + NPPU_PKTRX_CFG_IND_CMDr = 415, + NPPU_PKTRX_CFG_IND_DATA0r = 416, + NPPU_PKTRX_CFG_IND_DATA1r = 417, + NPPU_PKTRX_CFG_IND_DATA2r = 418, + NPPU_PKTRX_CFG_IND_DATA3r = 419, + NPPU_PKTRX_CFG_IND_DATA4r = 420, + NPPU_PKTRX_CFG_IND_DATA5r = 421, + NPPU_PKTRX_CFG_IND_DATA6r = 422, + NPPU_PKTRX_CFG_IND_DATA7r = 423, + NPPU_PKTRX_CFG_TCAM_0_CMDr = 424, + NPPU_PKTRX_CFG_TCAM_1_CMDr = 425, + NPPU_PKTRX_CFG_PORT_EN_0r = 426, + NPPU_PKTRX_CFG_PORT_EN_1r = 427, + NPPU_PKTRX_CFG_PORT_EN_2r = 428, + NPPU_PKTRX_CFG_PORT_EN_3r = 429, + NPPU_PKTRX_CFG_CFG_PORT_L2_OFFSET_MODE_0r = 430, + NPPU_PKTRX_CFG_CFG_PORT_L2_OFFSET_MODE_1r = 431, + NPPU_PKTRX_CFG_CFG_PORT_L2_OFFSET_MODE_2r = 432, + NPPU_PKTRX_CFG_CFG_PORT_L2_OFFSET_MODE_3r = 433, + NPPU_PKTRX_CFG_PORT_FC_MODE_0r = 434, + NPPU_PKTRX_CFG_PORT_FC_MODE_1r = 435, + NPPU_PKTRX_CFG_PORT_FC_MODE_2r = 436, + NPPU_PKTRX_CFG_PORT_FC_MODE_3r = 437, + NPPU_PKTRX_CFG_PORT_FC_MODE_4r = 438, + NPPU_PKTRX_CFG_PORT_FC_MODE_5r = 439, + NPPU_PKTRX_CFG_PORT_FC_MODE_6r = 440, + NPPU_PKTRX_CFG_PORT_FC_MODE_7r = 441, + NPPU_PKTRX_CFG_CFG_ISCH_AGING_THr = 442, + NPPU_PKTRX_CFG_ISCH_FIFO_TH_0r = 443, + NPPU_PKTRX_CFG_ISCH_CFG_1r = 444, + NPPU_PKTRX_CFG_TCAM_0_VLDr = 445, + NPPU_PKTRX_CFG_TCAM_1_VLDr = 446, + NPPU_PKTRX_CFG_CPU_PORT_EN_MASKr = 447, + NPPU_PKTRX_CFG_PKTRX_GLBAL_CFG_0r = 448, + NPPU_PKTRX_CFG_PKTRX_GLBAL_CFG_1r = 449, + NPPU_PKTRX_CFG_PKTRX_GLBAL_CFG_2r = 450, + NPPU_PKTRX_CFG_PKTRX_GLBAL_CFG_3r = 451, + NPPU_PKTRX_CFG_NPPU_STARTr = 452, + NPPU_PKTRX_STAT_IND_STATUSr = 453, + NPPU_PKTRX_STAT_IND_CMDr = 454, + NPPU_PKTRX_STAT_IND_DATA0r = 455, + NPPU_IDMA_CFG_DEBUG_CNT_OVFL_MODEr = 456, + NPPU_IDMA_STAT_IND_STATUSr = 457, + NPPU_IDMA_STAT_IND_CMDr = 458, + NPPU_IDMA_STAT_IND_DATA0r = 459, + NPPU_PBU_CFG_IND_STATUSr = 460, + NPPU_PBU_CFG_IND_CMDr = 461, + NPPU_PBU_CFG_IND_DATA0r = 462, + NPPU_PBU_CFG_IND_DATA1r = 463, + NPPU_PBU_CFG_IND_DATA2r = 464, + NPPU_PBU_CFG_IND_DATA3r = 465, + NPPU_PBU_CFG_IND_DATA4r = 466, + NPPU_PBU_CFG_IND_DATA5r = 467, + NPPU_PBU_CFG_IND_DATA6r = 468, + NPPU_PBU_CFG_IND_DATA7r = 469, + NPPU_PBU_CFG_IDMA_PUBLIC_THr = 470, + NPPU_PBU_CFG_LIF_PUBLIC_THr = 471, + NPPU_PBU_CFG_IDMA_TOTAL_THr = 472, + NPPU_PBU_CFG_LIF_TOTAL_THr = 473, + NPPU_PBU_CFG_MC_TOTAL_THr = 474, + NPPU_PBU_CFG_MC_COS10_THr = 475, + NPPU_PBU_CFG_MC_COS32_THr = 476, + NPPU_PBU_CFG_MC_COS54_THr = 477, + NPPU_PBU_CFG_MC_COS76_THr = 478, + NPPU_PBU_CFG_DEBUG_CNT_OVFL_MODEr = 479, + NPPU_PBU_CFG_SE_KEY_AFUL_NEGATE_CFGr = 480, + NPPU_PBU_CFG_SA_FLAGr = 481, + NPPU_PBU_STAT_IND_DATAr = 482, + NPPU_PBU_STAT_IND_STATUSr = 483, + NPPU_PBU_STAT_IND_CMDr = 484, + NPPU_PBU_STAT_TOTAL_CNTr = 485, + NPPU_PBU_STAT_IDMA_PUB_CNTr = 486, + NPPU_PBU_STAT_LIF_PUB_CNTr = 487, + NPPU_PBU_STAT_MC_TOTAL_CNTr = 488, + NPPU_PBU_STAT_PBU_THRAM_INIT_DONEr = 489, + NPPU_PBU_STAT_IFB_FPTR_INIT_DONEr = 490, + NPPU_ISU_CFG_WEIGHT_NORMAL_UCr = 491, + NPPU_ISU_CFG_FABRIC_OR_SAIPr = 492, + NPPU_ISU_STAT_IND_STATUSr = 493, + NPPU_ISU_STAT_IND_CMDr = 494, + NPPU_ISU_STAT_IND_DAT0r = 495, + NPPU_ODMA_CFG_IND_ACCESS_DONEr = 496, + NPPU_ODMA_CFG_IND_COMMANDr = 497, + NPPU_ODMA_CFG_IND_DAT0r = 498, + NPPU_ODMA_CFG_IND_DAT1r = 499, + NPPU_ODMA_CFG_FABRIC_OR_SAIPr = 500, + NPPU_ODMA_CFG_MAX_PKT_LENr = 501, + NPPU_ODMA_CFG_AGE_ENr = 502, + NPPU_ODMA_CFG_AGE_MODEr = 503, + NPPU_ODMA_CFG_AGE_VALUE_TIMEr = 504, + NPPU_ODMA_CFG_AGE_VALUE_ROOMr = 505, + NPPU_ODMA_CFG_AGE_OUT_CNTr = 506, + NPPU_ODMA_CFG_TOKEN_VALUE_Ar = 507, + NPPU_ODMA_CFG_TOKEN_VALUE_Br = 508, + NPPU_ODMA_CFG_CFG_SHAP_EN_P0r = 509, + NPPU_ODMA_CFG_CFG_SHAP_EN_P1r = 510, + NPPU_ODMA_CFG_CFG_SHAP_EN_TMr = 511, + NPPU_ODMA_STAT_IND_STATUSr = 512, + NPPU_ODMA_STAT_IND_CMDr = 513, + NPPU_ODMA_STAT_IND_DATA0r = 514, + NPPU_ODMA_STAT_DEBUG_CNT_CFGr = 515, + NPPU_OAM_CFG_BFD_FIRSTCHK_THr = 516, + NPPU_PBU_CFG_MEMID_0_PBU_FC_IDMATH_RAMr = 517, + NPPU_PBU_CFG_MEMID_1_PBU_FC_MACTH_RAMr = 518, + NPPU_PBU_STAT_MEMID_1_ALL_KIND_PORT_CNTr = 519, + NPPU_PBU_STAT_MEMID_2_PPU_PBU_IFB_REQ_VLD_CNTr = 520, + NPPU_PBU_STAT_MEMID_2_PBU_PPU_IFB_RSP_VLD_CNTr = 521, + NPPU_PBU_STAT_MEMID_2_ODMA_PBU_RECY_PTR_VLD_CNTr = 522, + NPPU_PBU_STAT_MEMID_2_PPU_PBU_MCODE_PF_REQ_CNTr = 523, + NPPU_PBU_STAT_MEMID_2_PBU_PPU_MCODE_PF_RSP_CNTr = 524, + NPPU_PBU_STAT_MEMID_2_PPU_PBU_LOGIC_PF_REQ_CNTr = 525, + NPPU_PBU_STAT_MEMID_2_PBU_PPU_LOGIC_PF_RSP_CNTr = 526, + NPPU_PBU_STAT_MEMID_2_PPU_USE_PTR_PULSE_CNTr = 527, + NPPU_PBU_STAT_MEMID_2_PPU_PBU_WB_VLD_CNTr = 528, + NPPU_PBU_STAT_MEMID_2_PBU_PPU_REORDER_PARA_VLD_CNTr = 529, + NPPU_PBU_STAT_MEMID_2_SE_PBU_DPI_KEY_VLD_CNTr = 530, + NPPU_PBU_STAT_MEMID_2_PBU_SE_DPI_RSP_DATVLD_CNTr = 531, + NPPU_PBU_STAT_MEMID_2_ODMA_PBU_IFB_RD1_CNTr = 532, + NPPU_PBU_STAT_MEMID_2_ODMA_PBU_IFB_RD2_CNTr = 533, + NPPU_PBU_STAT_MEMID_2_PBU_PPU_MCODE_PF_NO_RSP_CNTr = 534, + NPPU_PBU_STAT_MEMID_2_PBU_PPU_LOGIC_PF_NO_RSP_CNTr = 535, + NPPU_PBU_STAT_MEMID_3_CPU_RD_IFB_DATAr = 536, + NPPU_PBU_STAT_MEMID_4_MUX_SEL_RGTr = 537, + NPPU_PBU_STAT_MEMID_5_PORT_PUB_CNTr = 538, + NPPU_IDMA_STAT_MEMID_1_IDMA_O_ISU_PKT_PULSE_TOTAL_CNTr = 539, + NPPU_IDMA_STAT_MEMID_1_IDMA_O_ISU_EPKT_PULSE_TOTAL_CNTr = 540, + NPPU_IDMA_STAT_MEMID_1_IDMA_DISPKT_PULSE_TOTAL_CNTr = 541, + NPPU_IDMA_STAT_MEMID_0_IDMA_O_ISU_PKT_PULSE_CNTr = 542, + NPPU_IDMA_STAT_MEMID_0_IDMA_O_ISU_EPKT_PULSE_CNTr = 543, + NPPU_IDMA_STAT_MEMID_0_IDMA_DISPKT_PULSE_CNTr = 544, + PPU_PPU_TEST_Rr = 545, + PPU_PPU_PPU_DEBUG_EN_Rr = 546, + PPU_PPU_CSR_DUP_TABLE_WR_DATAr = 547, + PPU_PPU_CSR_DUP_TABLE_RD_DATAr = 548, + PPU_PPU_CSR_DUP_TABLE_ADDRr = 549, + PPU_PPU_PPU_DEBUG_VLDr = 550, + PPU_PPU_COP_THASH_RSK_319_288r = 551, + PPU_PPU_COP_THASH_RSK_287_256r = 552, + PPU_PPU_COP_THASH_RSK_255_224r = 553, + PPU_PPU_COP_THASH_RSK_223_192r = 554, + PPU_PPU_COP_THASH_RSK_191_160r = 555, + PPU_PPU_COP_THASH_RSK_159_128r = 556, + PPU_PPU_COP_THASH_RSK_127_096r = 557, + PPU_PPU_COP_THASH_RSK_095_064r = 558, + PPU_PPU_COP_THASH_RSK_063_032r = 559, + PPU_PPU_COP_THASH_RSK_031_000r = 560, + PPU_PPU_CFG_IPV4_IPID_START_VALUEr = 561, + PPU_PPU_CFG_IPV4_IPID_END_VALUEr = 562, + PPU_PPU_CLUSTER_MF_IN_ENr = 563, + PPU_PPU_PPU_EMPTYr = 564, + PPU_PPU_INSTRMEM_W_ADDRr = 565, + PPU_PPU_INSTRMEM_W_DATA_191_160r = 566, + PPU_PPU_INSTRMEM_W_DATA_159_128r = 567, + PPU_PPU_INSTRMEM_W_DATA_127_96r = 568, + PPU_PPU_INSTRMEM_W_DATA_95_64r = 569, + PPU_PPU_INSTRMEM_W_DATA_63_32r = 570, + PPU_PPU_INSTRMEM_W_DATA_31_0r = 571, + PPU_PPU_ISU_FWFT_MF_FIFO_PROG_FULL_ASSERT_CFGr = 572, + PPU_PPU_ISU_FWFT_MF_FIFO_PROG_FULL_NEGATE_CFGr = 573, + PPU_CLUSTER_INT_1200M_MASKr = 574, + PPU4K_CLUSTER_WR_HIGH_DATA_R_MEXr = 575, + PPU4K_CLUSTER_WR_LOW_DATA_R_MEXr = 576, + PPU4K_CLUSTER_ADDR_R_MEXr = 577, + PPU4K_CLUSTER_SDT_TBL_IND_ACCESS_DONEr = 578, + PPU4K_CLUSTER_RD_HIGH_DATA_R_MEXr = 579, + PPU4K_CLUSTER_RD_LOW_DATA_R_MEXr = 580, + SE_ALG_INIT_OKr = 581, + SE_ALG_CPU_RD_RDYr = 582, + SE_ALG_CPU_RD_DATA_TMP0r = 583, + SE_ALG_CPU_RD_DATA_TMP1r = 584, + SE_ALG_CPU_RD_DATA_TMP2r = 585, + SE_ALG_CPU_RD_DATA_TMP3r = 586, + SE_ALG_CPU_RD_DATA_TMP4r = 587, + SE_ALG_CPU_RD_DATA_TMP5r = 588, + SE_ALG_CPU_RD_DATA_TMP6r = 589, + SE_ALG_CPU_RD_DATA_TMP7r = 590, + SE_ALG_CPU_RD_DATA_TMP8r = 591, + SE_ALG_CPU_RD_DATA_TMP9r = 592, + SE_ALG_CPU_RD_DATA_TMP10r = 593, + SE_ALG_CPU_RD_DATA_TMP11r = 594, + SE_ALG_CPU_RD_DATA_TMP12r = 595, + SE_ALG_CPU_RD_DATA_TMP13r = 596, + SE_ALG_CPU_RD_DATA_TMP14r = 597, + SE_ALG_CPU_RD_DATA_TMP15r = 598, + SE_ALG_LPM_V4_CONFIG_RGTr = 599, + SE_ALG_LPM_V6_CONFIG_RGTr = 600, + SE_ALG_LPM_EXT_RSP_FIFO_U0_PFULL_ASTr = 601, + SE_AS_HASH_AGE_PAT_CFGr = 602, + SE_AS_LEARN_RDY_CFGr = 603, + SE_KSCHD_KSCHD_AS_PFUL_CFGr = 604, + SE_KSCHD_KSCHD_DIR_PFUL_CFGr = 605, + SE_KSCHD_KSCHD_AS_EPT_CFGr = 606, + SE_KSCHD_CPU_ARBI_PFUL_CFGr = 607, + SE_KSCHD_KSCHD_PBU_PFUL_CFGr = 608, + SE_RSCHD_RSCHD_DIR_PFUL_CFGr = 609, + SE_RSCHD_RSCHD_DIR_EPT_CFGr = 610, + SE4K_SE_ALG_CPU_CMD_RGTr = 611, + SE4K_SE_ALG_CPU_WR_DATA_TMP0r = 612, + SE4K_SE_ALG_CPU_WR_DATA_TMP1r = 613, + SE4K_SE_ALG_CPU_WR_DATA_TMP2r = 614, + SE4K_SE_ALG_CPU_WR_DATA_TMP3r = 615, + SE4K_SE_ALG_CPU_WR_DATA_TMP4r = 616, + SE4K_SE_ALG_CPU_WR_DATA_TMP5r = 617, + SE4K_SE_ALG_CPU_WR_DATA_TMP6r = 618, + SE4K_SE_ALG_CPU_WR_DATA_TMP7r = 619, + SE4K_SE_ALG_CPU_WR_DATA_TMP8r = 620, + SE4K_SE_ALG_CPU_WR_DATA_TMP9r = 621, + SE4K_SE_ALG_CPU_WR_DATA_TMP10r = 622, + SE4K_SE_ALG_CPU_WR_DATA_TMP11r = 623, + SE4K_SE_ALG_CPU_WR_DATA_TMP12r = 624, + SE4K_SE_ALG_CPU_WR_DATA_TMP13r = 625, + SE4K_SE_ALG_CPU_WR_DATA_TMP14r = 626, + SE4K_SE_ALG_CPU_WR_DATA_TMP15r = 627, + SE4K_SE_ALG_CPU_RD_RDYr = 628, + SE4K_SE_ALG_CPU_RD_DATA_TMP0r = 629, + SE4K_SE_ALG_CPU_RD_DATA_TMP1r = 630, + SE4K_SE_ALG_CPU_RD_DATA_TMP2r = 631, + SE4K_SE_ALG_CPU_RD_DATA_TMP3r = 632, + SE4K_SE_ALG_CPU_RD_DATA_TMP4r = 633, + SE4K_SE_ALG_CPU_RD_DATA_TMP5r = 634, + SE4K_SE_ALG_CPU_RD_DATA_TMP6r = 635, + SE4K_SE_ALG_CPU_RD_DATA_TMP7r = 636, + SE4K_SE_ALG_CPU_RD_DATA_TMP8r = 637, + SE4K_SE_ALG_CPU_RD_DATA_TMP9r = 638, + SE4K_SE_ALG_CPU_RD_DATA_TMP10r = 639, + SE4K_SE_ALG_CPU_RD_DATA_TMP11r = 640, + SE4K_SE_ALG_CPU_RD_DATA_TMP12r = 641, + SE4K_SE_ALG_CPU_RD_DATA_TMP13r = 642, + SE4K_SE_ALG_CPU_RD_DATA_TMP14r = 643, + SE4K_SE_ALG_CPU_RD_DATA_TMP15r = 644, + SE4K_SE_ALG_HASH0_EXT_CFG_RGTr = 645, + SE4K_SE_ALG_HASH1_EXT_CFG_RGTr = 646, + SE4K_SE_ALG_HASH2_EXT_CFG_RGTr = 647, + SE4K_SE_ALG_HASH3_EXT_CFG_RGTr = 648, + SE4K_SE_ALG_HASH0_TBL30_DEPTHr = 649, + SE4K_SE_ALG_HASH0_TBL74_DEPTHr = 650, + SE4K_SE_ALG_HASH1_TBL30_DEPTHr = 651, + SE4K_SE_ALG_HASH1_TBL74_DEPTHr = 652, + SE4K_SE_ALG_HASH2_TBL30_DEPTHr = 653, + SE4K_SE_ALG_HASH2_TBL74_DEPTHr = 654, + SE4K_SE_ALG_HASH3_TBL30_DEPTHr = 655, + SE4K_SE_ALG_HASH3_TBL74_DEPTHr = 656, + SE4K_SE_ALG_WR_RSP_CFGr = 657, + SE4K_SE_ALG_HASH_MONO_FLAGr = 658, + SE4K_SE_ALG_HASH10_EXT_CRC_CFGr = 659, + SE4K_SE_ALG_HASH32_EXT_CRC_CFGr = 660, + SE4K_SE_ALG_ZBLOCK_SERVICE_CONFIGUREr = 661, + SE4K_SE_ALG_ZBLOCK_HASH_ZCELL_MONOr = 662, + SE4K_SE_ALG_ZLOCK_HASH_ZREG_MONOr = 663, + SMMU0_SMMU0_INIT_DONEr = 664, + SMMU0_SMMU0_CPU_IND_WDAT0r = 665, + SMMU0_SMMU0_CPU_IND_WDAT1r = 666, + SMMU0_SMMU0_CPU_IND_WDAT2r = 667, + SMMU0_SMMU0_CPU_IND_WDAT3r = 668, + SMMU0_SMMU0_CPU_IND_CMDr = 669, + SMMU0_SMMU0_CPU_IND_RD_DONEr = 670, + SMMU0_SMMU0_CPU_IND_RDAT0r = 671, + SMMU0_SMMU0_CPU_IND_RDAT1r = 672, + SMMU0_SMMU0_CPU_IND_RDAT2r = 673, + SMMU0_SMMU0_CPU_IND_RDAT3r = 674, + SMMU0_SMMU0_CFG_PLCR_MONOr = 675, + SMMU0_SMMU0_WR_ARB_CPU_RDYr = 676, + SMMU0_SMMU0_TM_STAT_EN_CFGr = 677, + SE_SMMU1_DDR_WDAT0r = 678, + SE_SMMU1_DIR_ARBI_SER_RPFULr = 679, + SE_SMMU1_CFG_WR_ARBI_PFUL2r = 680, + SE_SMMU1_ETM_TBL_CFGr = 681, + SE_SMMU1_CFG_CASH_ADDR_PFULr = 682, + SE_SMMU1_CTRL_RFIFO_CFGr = 683, + SE_SMMU1_CACHE_REQ_FIFO_CFGr = 684, + STAT_STAT_CFG_CPU_IND_ERAM_WDAT0r = 685, + STAT_STAT_CFG_ETM_PORT_SEL_CFGr = 686, + STAT_STAT_CFG_TM_STAT_CFGr = 687, + STAT_STAT_CFG_PPU_ERAM_DEPTHr = 688, + STAT_STAT_CFG_PPU_ERAM_BASE_ADDRr = 689, + STAT_STAT_CFG_PPU_DDR_BASE_ADDRr = 690, + STAT_STAT_CFG_PLCR0_BASE_ADDRr = 691, + STAT_STAT_CFG_ETM_STAT_START_ADDR_CFGr = 692, + STAT_STAT_CFG_ETM_STAT_DEPTH_CFGr = 693, + STAT_STAT_CFG_CYCLE_MOV_EN_CFGr = 694, + STAT_ETCAM_CPU_IND_WDAT0r = 695, + STAT_ETCAM_CPU_IND_CTRL_TMP0r = 696, + STAT_ETCAM_CPU_IND_CTRL_TMP1r = 697, + STAT_ETCAM_CPU_IND_RD_DONEr = 698, + STAT_ETCAM_CPU_RDAT0r = 699, + STAT_ETCAM_CPU_RDAT1r = 700, + STAT_ETCAM_CPU_RDAT2r = 701, + STAT_ETCAM_CPU_RDAT3r = 702, + STAT_ETCAM_CPU_RDAT4r = 703, + STAT_ETCAM_CPU_RDAT5r = 704, + STAT_ETCAM_CPU_RDAT6r = 705, + STAT_ETCAM_CPU_RDAT7r = 706, + STAT_ETCAM_CPU_RDAT8r = 707, + STAT_ETCAM_CPU_RDAT9r = 708, + STAT_ETCAM_CPU_RDAT10r = 709, + STAT_ETCAM_CPU_RDAT11r = 710, + STAT_ETCAM_CPU_RDAT12r = 711, + STAT_ETCAM_CPU_RDAT13r = 712, + STAT_ETCAM_CPU_RDAT14r = 713, + STAT_ETCAM_CPU_RDAT15r = 714, + STAT_ETCAM_CPU_RDAT16r = 715, + STAT_ETCAM_CPU_RDAT17r = 716, + STAT_ETCAM_CPU_RDAT18r = 717, + STAT_ETCAM_CPU_RDAT19r = 718, + STAT_ETCAM_QVBOr = 719, + STAT_ETCAM_CNT_OVERFLOW_MODEr = 720, + STAT_CAR0_CARA_QUEUE_RAM0_159_0r = 721, + STAT_CAR0_CARA_PROFILE_RAM1_255_0r = 722, + STAT_CAR0_CARA_QOVS_RAM_RAM2r = 723, + STAT_CAR0_LOOK_UP_TABLE1r = 724, + STAT_CAR0_CARA_PKT_DES_I_CNTr = 725, + STAT_CAR0_CARA_GREEN_PKT_I_CNTr = 726, + STAT_CAR0_CARA_YELLOW_PKT_I_CNTr = 727, + STAT_CAR0_CARA_RED_PKT_I_CNTr = 728, + STAT_CAR0_CARA_PKT_DES_O_CNTr = 729, + STAT_CAR0_CARA_GREEN_PKT_O_CNTr = 730, + STAT_CAR0_CARA_YELLOW_PKT_O_CNTr = 731, + STAT_CAR0_CARA_RED_PKT_O_CNTr = 732, + STAT_CAR0_CARA_PKT_DES_FC_FOR_CFG_CNTr = 733, + STAT_CAR0_CARA_APPOINT_QNUM_OR_SPr = 734, + STAT_CAR0_CARA_CFGMT_COUNT_MODEr = 735, + STAT_CAR0_CARA_PKT_SIZE_CNTr = 736, + STAT_CAR0_CARA_PLCR_INIT_DONTr = 737, + STAT_CAR0_CARB_QUEUE_RAM0_159_0r = 738, + STAT_CAR0_CARB_PROFILE_RAM1_255_0r = 739, + STAT_CAR0_CARB_QOVS_RAM_RAM2r = 740, + STAT_CAR0_LOOK_UP_TABLE2r = 741, + STAT_CAR0_CARB_PKT_DES_I_CNTr = 742, + STAT_CAR0_CARB_GREEN_PKT_I_CNTr = 743, + STAT_CAR0_CARB_YELLOW_PKT_I_CNTr = 744, + STAT_CAR0_CARB_RED_PKT_I_CNTr = 745, + STAT_CAR0_CARB_PKT_DES_O_CNTr = 746, + STAT_CAR0_CARB_GREEN_PKT_O_CNTr = 747, + STAT_CAR0_CARB_YELLOW_PKT_O_CNTr = 748, + STAT_CAR0_CARB_RED_PKT_O_CNTr = 749, + STAT_CAR0_CARB_PKT_DES_FC_FOR_CFG_CNTr = 750, + STAT_CAR0_CARB_APPOINT_QNUM_OR_SPr = 751, + STAT_CAR0_CARB_CFGMT_COUNT_MODEr = 752, + STAT_CAR0_CARB_PKT_SIZE_CNTr = 753, + STAT_CAR0_CARB_PLCR_INIT_DONTr = 754, + STAT_CAR0_CARC_QUEUE_RAM0_159_0r = 755, + STAT_CAR0_CARC_PROFILE_RAM1_255_0r = 756, + STAT_CAR0_CARC_QOVS_RAM_RAM2r = 757, + STAT_CAR0_CARC_PKT_DES_I_CNTr = 758, + STAT_CAR0_CARC_GREEN_PKT_I_CNTr = 759, + STAT_CAR0_CARC_YELLOW_PKT_I_CNTr = 760, + STAT_CAR0_CARC_RED_PKT_I_CNTr = 761, + STAT_CAR0_CARC_PKT_DES_O_CNTr = 762, + STAT_CAR0_CARC_GREEN_PKT_O_CNTr = 763, + STAT_CAR0_CARC_YELLOW_PKT_O_CNTr = 764, + STAT_CAR0_CARC_RED_PKT_O_CNTr = 765, + STAT_CAR0_CARC_PKT_DES_FC_FOR_CFG_CNTr = 766, + STAT_CAR0_CARC_APPOINT_QNUM_OR_SPr = 767, + STAT_CAR0_CARC_CFGMT_COUNT_MODEr = 768, + STAT_CAR0_CARC_PKT_SIZE_CNTr = 769, + STAT_CAR0_CARC_PLCR_INIT_DONTr = 770, + STAT_CAR0_CARB_RANDOM_RAMr = 771, + STAT_CAR0_CARC_RANDOM_RAMr = 772, + STAT_CAR0_CARA_BEGIN_FLOW_IDr = 773, + STAT_CAR0_CARB_BEGIN_FLOW_IDr = 774, + STAT_CAR0_CARC_BEGIN_FLOW_IDr = 775, + STAT_CAR0_PROG_FULL_ASSERT_CFG_Wr = 776, + STAT_CAR0_PROG_FULL_NEGATE_CFG_Wr = 777, + STAT_CAR0_TIMEOUT_LIMITr = 778, + STAT_CAR0_PKT_DES_FIFO_OVERFLOWr = 779, + STAT_CAR0_PKT_DES_FIFO_UNDERFLOWr = 780, + STAT_CAR0_PKT_DES_FIFO_PROG_FULLr = 781, + STAT_CAR0_PKT_DES_FIFO_PROG_EMPTYr = 782, + STAT_CAR0_PKT_DES_FIFO_FULLr = 783, + STAT_CAR0_PKT_DES_FIFO_EMPTYr = 784, + STAT_CAR0_PKT_SIZE_OFFSETr = 785, + STAT_CAR0_CAR_PLCR_INIT_DONTr = 786, + STAT_CAR0_MAX_PKT_SIZE_Ar = 787, + STAT_CAR0_MAX_PKT_SIZE_Br = 788, + STAT_CAR0_MAX_PKT_SIZE_Cr = 789, + STAT_CAR0_CAR_HIERARCHY_MODEr = 790, + STAT_CAR0_PROG_EMPTY_ASSERT_CFG_Wr = 791, + STAT_CAR0_PROG_EMPTY_NEGATE_CFG_Wr = 792, + STAT_CAR0_PKT_DES_FIFO_OVF_INTr = 793, + STAT_CAR0_PKT_DES_FIFO_DATA_COUNTr = 794, + STAT_CAR0_PKT_DES_FIFO_UDF_INTr = 795, + STAT_CAR0_CARA_QUEUE_RAM0_159_0_PKTr = 796, + STAT_CAR0_CARA_PROFILE_RAM1_255_0_PKTr = 797, + STAT4K_ETCAM_BLOCK0_7_PORT_ID_CFGr = 798, + STAT4K_ETCAM_BLOCK0_3_BASE_ADDR_CFGr = 799, + STAT4K_ETCAM_BLOCK4_7_BASE_ADDR_CFGr = 800, + DTB_DTB_CFG_CFG_ERAM_WR_INTERVAL_CNTr = 801, + DTB_DTB_CFG_CFG_ZCAM_WR_INTERVAL_CNTr = 802, + DTB_DTB_CFG_CFG_TCAM_WR_INTERVAL_CNTr = 803, + DTB_DTB_CFG_CFG_DDR_WR_INTERVAL_CNTr = 804, + DTB_DTB_CFG_CFG_HASH_WR_INTERVAL_CNTr = 805, + DTB_DTB_CFG_CFG_ERAM_RD_INTERVAL_CNTr = 806, + DTB_DTB_CFG_CFG_ZCAM_RD_INTERVAL_CNTr = 807, + DTB_DTB_CFG_CFG_TCAM_RD_INTERVAL_CNTr = 808, + DTB_DTB_CFG_CFG_DDR_RD_INTERVAL_CNTr = 809, + DTB_DTB_CFG_CFG_DTB_QUEUE_LOCK_STATE_0_3r = 810, + DTB_DTB_AXIM0_W_CONVERT_0_MODEr = 811, + DTB_DTB_AXIM0_R_CONVERT_0_MODEr = 812, + DTB_DTB_AXIM0_AXIMR_OSr = 813, + DTB_DTB_AXIM1_W_CONVERT_1_MODEr = 814, + DTB_DTB_AXIM1_R_CONVERT_1_MODEr = 815, + DTB_DTB_AXIS_AXIS_CONVERT_MODEr = 816, + DTB4K_DTB_ENQ_CFG_QUEUE_DTB_ADDR_H_0_127r = 817, + DTB4K_DTB_ENQ_CFG_QUEUE_DTB_ADDR_L_0_127r = 818, + DTB4K_DTB_ENQ_CFG_QUEUE_DTB_LEN_0_127r = 819, + DTB4K_DTB_ENQ_INFO_QUEUE_BUF_SPACE_LEFT_0_127r = 820, + DTB4K_DTB_ENQ_CFG_EPID_V_FUNC_NUM_0_127r = 821, + TRPG_TRPG_RX_PORT_CPU_TRPG_MS_ENr = 822, + TRPG_TRPG_RX_PORT_CPU_TRPG_PORT_ENr = 823, + TRPG_TRPG_RX_PORT_CPU_TRPG_LOOK_ENr = 824, + TRPG_TRPG_RX_PORT_CPU_TRPGRX_RAM_ALMOST_FULLr = 825, + TRPG_TRPG_RX_PORT_CPU_TRPGRX_RAM_TEST_ENr = 826, + TRPG_TRPG_RX_PORT_CPU_TRPGRX_INMOD_PFC_RDY_ENr = 827, + TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_NUM_Hr = 828, + TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_NUM_Lr = 829, + TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_BYTE_NUM_Hr = 830, + TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_BYTE_NUM_Lr = 831, + TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_CNT_CLRr = 832, + TRPG_TRPG_RX_PORT_CPU_TRPGRX_FC_CLK_FREQr = 833, + TRPG_TRPG_RX_PORT_CPU_TRPGRX_FC_ENr = 834, + TRPG_TRPG_RX_PORT_CPU_TRPGRX_FC_TOKEN_ADD_NUMr = 835, + TRPG_TRPG_RX_PORT_CPU_TRPGRX_FC_TOKEN_MAX_NUMr = 836, + TRPG_TRPG_RX_PORT_CPU_TRPGRX_PORT_STATE_INFOr = 837, + TRPG_TRPG_RX_PORT_CPU_TRPGRX_RAM_PAST_MAX_DEPr = 838, + TRPG_TRPG_RX_PORT_CPU_TRPGRX_RAM_PAST_MAX_DEP_CLRr = 839, + TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_PAST_MAX_LENr = 840, + TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_PAST_MAX_LEN_CLRr = 841, + TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_PAST_MIN_LENr = 842, + TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_PAST_MIN_LEN_CLRr = 843, + TRPG_TRPG_RX_RAM_TRPG_RX_DATA_RAMr = 844, + TRPG_TRPG_RX_RAM_TRPG_RX_INFO_RAMr = 845, + TRPG_TRPG_TX_PORT_CPU_TRPG_MS_ENr = 846, + TRPG_TRPG_TX_PORT_CPU_TRPG_PORT_ENr = 847, + TRPG_TRPG_TX_PORT_CPU_TRPG_LOOK_ENr = 848, + TRPG_TRPG_TX_PORT_CPU_TRPGTX_RAM_ALMOST_FULLr = 849, + TRPG_TRPG_TX_PORT_CPU_TRPGTX_RAM_TEST_ENr = 850, + TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_NUM_Hr = 851, + TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_NUM_Lr = 852, + TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_BYTE_NUM_Hr = 853, + TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_BYTE_NUM_Lr = 854, + TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_CNT_CLRr = 855, + TRPG_TRPG_TX_PORT_CPU_TRPGTX_FC_CLK_FREQr = 856, + TRPG_TRPG_TX_PORT_CPU_TRPGTX_FC_ENr = 857, + TRPG_TRPG_TX_PORT_CPU_TRPGTX_FC_TOKEN_ADD_NUMr = 858, + TRPG_TRPG_TX_PORT_CPU_TRPGTX_FC_TOKEN_MAX_NUMr = 859, + TRPG_TRPG_TX_PORT_CPU_TRPGTX_PORT_STATE_INFOr = 860, + TRPG_TRPG_TX_PORT_CPU_TRPGTX_RAM_PAST_MAX_DEPr = 861, + TRPG_TRPG_TX_PORT_CPU_TRPGTX_RAM_PAST_MAX_DEP_CLRr = 862, + TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_PAST_MAX_LENr = 863, + TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_PAST_MAX_LEN_CLRr = 864, + TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_PAST_MIN_LENr = 865, + TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_PAST_MIN_LEN_CLRr = 866, + TRPG_TRPG_TX_ETM_PORT_CPU_TRPGTX_ETM_RAM_ALMOST_FULLr = 867, + TRPG_TRPG_TX_ETM_PORT_CPU_TRPGTX_ETM_RAM_TEST_ENr = 868, + TRPG_TRPG_TX_GLB_CPU_TODTIME_UPDATE_INT_MASKr = 869, + TRPG_TRPG_TX_GLB_CPU_TODTIME_UPDATE_INT_CLRr = 870, + TRPG_TRPG_TX_GLB_CPU_TODTIME_RAM_TEST_ENr = 871, + TRPG_TRPG_TX_RAM_TRPG_TX_DATA_RAMr = 872, + TRPG_TRPG_TX_RAM_TRPG_TX_INFO_RAMr = 873, + TRPG_TRPG_TX_ETM_RAM_TRPG_TX_ETM_DATA_RAMr = 874, + TRPG_TRPG_TX_ETM_RAM_TRPG_TX_ETM_INFO_RAMr = 875, + ETM_CFGMT_CHIP_VERSION_REGr = 876, + ETM_CFGMT_CHIP_DATE_REGr = 877, + ETM_CFGMT_CFGMT_CRC_ENr = 878, + ETM_CFGMT_CFG_PORT_TRANSFER_ENr = 879, + ETM_CFGMT_TM_SA_WORK_MODEr = 880, + ETM_CFGMT_LOCAL_SA_IDr = 881, + ETM_OLIF_OLIF_RDYr = 882, + ETM_OLIF_EMEM_PROG_FULLr = 883, + ETM_OLIF_PORT_ORDER_FIFO_FULLr = 884, + ETM_OLIF_OLIF_RELEASE_LASTr = 885, + ETM_OLIF_OLIF_FIFO_EMPTY_STATEr = 886, + ETM_OLIF_QMU_OLIF_RELEASE_FC_CNTr = 887, + ETM_OLIF_OLIF_QMU_LINK_FC_CNTr = 888, + ETM_OLIF_LIF0_LINK_FC_CNTr = 889, + ETM_OLIF_OLIF_TMMU_FC_CNTr = 890, + ETM_OLIF_OLIF_MMU_FC_CNTr = 891, + ETM_OLIF_OLIF_QMU_PORT_RDY_Hr = 892, + ETM_OLIF_OLIF_QMU_PORT_RDY_Lr = 893, + ETM_OLIF_LIF0_PORT_RDY_Hr = 894, + ETM_OLIF_LIF0_PORT_RDY_Lr = 895, + ETM_OLIF_QMU_OLIF_RD_SOP_CNTr = 896, + ETM_OLIF_QMU_OLIF_RD_EOP_CNTr = 897, + ETM_OLIF_QMU_OLIF_RD_VLD_CNTr = 898, + ETM_OLIF_QMU_OLIF_RD_BLK_CNTr = 899, + ETM_OLIF_MMU_TM_DATA_SOP_CNTr = 900, + ETM_OLIF_MMU_TM_DATA_EOP_CNTr = 901, + ETM_OLIF_MMU_TM_DATA_VLD_CNTr = 902, + ETM_OLIF_ODMA_TM_DATA_SOP_CNTr = 903, + ETM_OLIF_ODMA_TM_DATA_EOP_CNTr = 904, + ETM_OLIF_ODMA_TM_DEQ_VLD_CNTr = 905, + ETM_OLIF_OLIF_QMU_RELEASE_VLD_CNTr = 906, + ETM_OLIF_EMEM_DAT_VLD_CNTr = 907, + ETM_OLIF_IMEM_DAT_VLD_CNTr = 908, + ETM_OLIF_EMEM_DAT_RD_CNTr = 909, + ETM_OLIF_IMEM_DAT_RD_CNTr = 910, + ETM_OLIF_QMU_OLIF_RD_SOP_EMEM_CNTr = 911, + ETM_OLIF_QMU_OLIF_RD_VLD_EMEM_CNTr = 912, + ETM_OLIF_CPU_LAST_WR_ADDRr = 913, + ETM_OLIF_CPU_LAST_WR_DATAr = 914, + ETM_OLIF_CPU_LAST_RD_ADDRr = 915, + ETM_OLIF_QMU_OLIF_LAST_PORTr = 916, + ETM_OLIF_QMU_OLIF_LAST_ADDRr = 917, + ETM_OLIF_QMU_OLIF_LAST_BANKr = 918, + ETM_OLIF_TM_LIF_BYTE_STATr = 919, + ETM_OLIF_TM_LIF_ERR_STATr = 920, + ETM_CGAVD_PORT_SHARE_CNTr = 921, + ETM_CGAVD_TOTAL_IMEM_CNTr = 922, + ETM_CGAVD_PP_Q_LENr = 923, + ETM_CGAVD_SYS_Q_LENr = 924, + ETM_CGAVD_CGAVD_CFG_ERROR_WARNINGr = 925, + ETM_CGAVD_MULT_QLEN_TH_ENr = 926, + ETM_CGAVD_MULT_QLEN_THr = 927, + ETM_CGAVD_CGAVD_CFG_MOVEr = 928, + ETM_CGAVD_CFGMT_TOTAL_THr = 929, + ETM_CGAVD_CFGMT_PORT_SHARE_THr = 930, + ETM_CGAVD_SA_UNREACH_STATEr = 931, + ETM_CGAVD_MV_PORT_THr = 932, + ETM_CGAVD_MV_DROP_SP_THr = 933, + ETM_CGAVD_CGAVD_STATE_WARNINGr = 934, + ETM_CGAVD_TMMU_CGAVD_DMA_FIFO_CNTr = 935, + ETM_CGAVD_TMMU_CGAVD_DMA_FIFO_CNT_MAXr = 936, + ETM_CGAVD_IMEM_TOTAL_CNTr = 937, + ETM_CGAVD_IMEM_TOTAL_CNT_MAXr = 938, + ETM_CGAVD_FLOW0_OMEM_CNTr = 939, + ETM_CGAVD_FLOW1_OMEM_CNTr = 940, + ETM_CGAVD_FLOW2_OMEM_CNTr = 941, + ETM_CGAVD_FLOW3_OMEM_CNTr = 942, + ETM_CGAVD_FLOW4_OMEM_CNTr = 943, + ETM_CGAVD_APPOINT_FLOW_NUM_MESSAGE_1r = 944, + ETM_CGAVD_APPOINT_FLOW_NUM_MESSAGE_2r = 945, + ETM_CGAVD_ODMA_CGAVD_PKT_NUM_1r = 946, + ETM_CGAVD_ODMA_CGAVD_BYTE_NUM_1r = 947, + ETM_CGAVD_CGAVD_ENQUEUE_PKT_NUM_1r = 948, + ETM_CGAVD_CGAVD_DEQUEUE_PKT_NUM_1r = 949, + ETM_CGAVD_CGAVD_QMU_PKT_IMEM_NUM_1r = 950, + ETM_CGAVD_CGAVD_QMU_PKT_OMEM_NUM_1r = 951, + ETM_CGAVD_CGAVD_QMU_BYTE_IMEM_NUM_1r = 952, + ETM_CGAVD_CGAVD_QMU_BYTE_OMEM_NUM_1r = 953, + ETM_CGAVD_CGAVD_QMU_PKT_DROP_NUM_1r = 954, + ETM_CGAVD_CGAVD_QMU_BYTE_DROP_NUM_1r = 955, + ETM_CGAVD_CGAVD_QMU_FORBID_DROP_NUM_1r = 956, + ETM_CGAVD_CGAVD_QMU_FLOW_TD_DROP_NUM_1r = 957, + ETM_CGAVD_CGAVD_QMU_FLOW_WRED_DROP_NUM_1r = 958, + ETM_CGAVD_CGAVD_QMU_FLOW_WRED_DP_DROP_NUM_1r = 959, + ETM_CGAVD_CGAVD_QMU_PP_TD_NUM_1r = 960, + ETM_CGAVD_CGAVD_QMU_PP_WRED_DROP_NUM_1r = 961, + ETM_CGAVD_CGAVD_QMU_PP_WRED_DP_DROP_NUM_1r = 962, + ETM_CGAVD_CGAVD_QMU_SYS_TD_DROP_NUM_1r = 963, + ETM_CGAVD_CGAVD_QMU_SYS_GRED_DROP_NUM_1r = 964, + ETM_CGAVD_CGAVD_QMU_SYS_GRED_DP_DROP_NUM1r = 965, + ETM_CGAVD_CGAVD_QMU_SA_DROP_NUM_1r = 966, + ETM_CGAVD_CGAVD_QMU_MOVE_DROP_NUM_1r = 967, + ETM_CGAVD_CGAVD_QMU_TM_MULT_DROP_NUM_1r = 968, + ETM_CGAVD_CGAVD_QMU_TM_ERROR_DROP_NUM_1r = 969, + ETM_CGAVD_ODMA_CGAVD_PKT_NUM_2r = 970, + ETM_CGAVD_ODMA_CGAVD_BYTE_NUM_2r = 971, + ETM_CGAVD_CGAVD_ENQUEUE_PKT_NUM_2r = 972, + ETM_CGAVD_CGAVD_DEQUEUE_PKT_NUM_2r = 973, + ETM_CGAVD_CGAVD_QMU_PKT_IMEM_NUM_2r = 974, + ETM_CGAVD_CGAVD_QMU_PKT_OMEM_NUM_2r = 975, + ETM_CGAVD_CGAVD_QMU_BYTE_IMEM_NUM_2r = 976, + ETM_CGAVD_CGAVD_QMU_BYTE_OMEM_NUM_2r = 977, + ETM_CGAVD_CGAVD_QMU_PKT_DROP_NUM_2r = 978, + ETM_CGAVD_CGAVD_QMU_BYTE_DROP_NUM_2r = 979, + ETM_CGAVD_CGAVD_QMU_FORBID_DROP_NUM_2r = 980, + ETM_CGAVD_CGAVD_QMU_FLOW_TD_DROP_NUM_2r = 981, + ETM_CGAVD_CGAVD_QMU_FLOW_WRED_DROP_NUM_2r = 982, + ETM_CGAVD_CGAVD_QMU_FLOW_WRED_DP_DROP_NUM_2r = 983, + ETM_CGAVD_CGAVD_QMU_PP_TD_NUM_2r = 984, + ETM_CGAVD_CGAVD_QMU_PP_WRED_DROP_NUM_2r = 985, + ETM_CGAVD_CGAVD_QMU_PP_WRED_DP_DROP_NUM_2r = 986, + ETM_CGAVD_CGAVD_QMU_SYS_TD_DROP_NUM_2r = 987, + ETM_CGAVD_CGAVD_QMU_SYS_GRED_DROP_NUM_2r = 988, + ETM_CGAVD_CGAVD_QMU_SYS_GRED_DP_DROP_NUM_2r = 989, + ETM_CGAVD_CGAVD_QMU_SA_DROP_NUM_2r = 990, + ETM_CGAVD_CGAVD_QMU_MOVE_DROP_NUM_2r = 991, + ETM_CGAVD_CGAVD_QMU_TM_MULT_DROP_NUM_2r = 992, + ETM_CGAVD_CGAVD_QMU_TM_ERROR_DROP_NUM_2r = 993, + ETM_CGAVD_MOVE_FLOW_TH_PROFILEr = 994, + ETM_CGAVD_MOVE_FLOW_THr = 995, + ETM_TMMU_EMEM_PD_FIFO_AFUL_THr = 996, + ETM_TMMU_DMA_DATA_FIFO_AFUL_THr = 997, + ETM_TMMU_TMMU_STATES_0r = 998, + ETM_TMMU_QMU_TMMU_WR_SOP_CNTr = 999, + ETM_TMMU_QMU_TMMU_WR_EOP_CNTr = 1000, + ETM_TMMU_QMU_TMMU_WR_DROP_CNTr = 1001, + ETM_TMMU_QMU_TMMU_WR_EMEM_CNTr = 1002, + ETM_TMMU_QMU_TMMU_WR_IMEM_CNTr = 1003, + ETM_TMMU_TMMU_MMU_WR_SOP_CNTr = 1004, + ETM_TMMU_TMMU_MMU_WR_EOP_CNTr = 1005, + ETM_TMMU_QMU_TMMU_RD_SOP_CNTr = 1006, + ETM_TMMU_QMU_TMMU_RD_EOP_CNTr = 1007, + ETM_TMMU_QMU_TMMU_RD_DROP_CNTr = 1008, + ETM_TMMU_QMU_TMMU_RD_EMEM_CNTr = 1009, + ETM_TMMU_QMU_TMMU_RD_IMEM_CNTr = 1010, + ETM_TMMU_TMMU_MMU_RD_SOP_CNTr = 1011, + ETM_TMMU_TMMU_MMU_RD_EOP_CNTr = 1012, + ETM_TMMU_TMMU_ODMA_IN_SOP_CNTr = 1013, + ETM_TMMU_TMMU_ODMA_IN_EOP_CNTr = 1014, + ETM_TMMU_TMMU_ODMA_VLD_CNTr = 1015, + ETM_TMMU_QMU_PD_IN_CNTr = 1016, + ETM_TMMU_TMMU_PD_HIT_CNTr = 1017, + ETM_TMMU_TMMU_PD_OUT_CNTr = 1018, + ETM_TMMU_TMMU_WR_CMD_FIFO_WR_CNTr = 1019, + ETM_TMMU_TMMU_IMEM_AGE_CNTr = 1020, + ETM_TMMU_TMMU_CMDSCH_RD_CNTr = 1021, + ETM_TMMU_TMMU_CMDSCH_DROP_CNTr = 1022, + ETM_TMMU_TMMU_CMDSW_DROP_CNTr = 1023, + ETM_TMMU_TMMU_ODMA_ENQ_RD_CNTr = 1024, + ETM_TMMU_TMMU_ODMA_ENQ_DROP_CNTr = 1025, + ETM_TMMU_TMMU_ODMA_IMEM_AGE_CNTr = 1026, + ETM_TMMU_TMMU_ODMA_DEQ_RD_CNTr = 1027, + ETM_TMMU_TMMU_ODMA_DEQ_DROP_CNTr = 1028, + ETM_TMMU_OLIF_TMMU_XOFF_CNTr = 1029, + ETM_TMMU_ODMA_TM_DATA_XOFF_CNTr = 1030, + ETM_TMMU_TM_ODMA_PKT_XOFF_CNTr = 1031, + ETM_TMMU_TM_STATE_3r = 1032, + ETM_TMMU_CFGMT_PD_CACHE_CMDr = 1033, + ETM_TMMU_CFGMT_PD_CACHE_RD_DONEr = 1034, + ETM_TMMU_CFGMT_PD_CACHE_RD_DATA_0r = 1035, + ETM_TMMU_CFGMT_PD_CACHE_RD_DATA_1r = 1036, + ETM_TMMU_CFGMT_PD_CACHE_RD_DATA_2r = 1037, + ETM_TMMU_CFGMT_PD_CACHE_RD_DATA_3r = 1038, + ETM_TMMU_CFGMT_TMMU_TO_ODMA_PARAr = 1039, + ETM_TMMU_CFGMT_DMA_DATA_FIFO_CNTr = 1040, + ETM_TMMU_CFGMT_CACHE_TAG_BIT0_OFFSETr = 1041, + ETM_TMMU_CFGMT_CACHE_TAG_BIT1_OFFSETr = 1042, + ETM_TMMU_CFGMT_CACHE_TAG_BIT2_OFFSETr = 1043, + ETM_TMMU_CFGMT_CACHE_TAG_BIT3_OFFSETr = 1044, + ETM_TMMU_CFGMT_CACHE_TAG_BIT4_OFFSETr = 1045, + ETM_TMMU_CFGMT_CACHE_TAG_BIT5_OFFSETr = 1046, + ETM_TMMU_CFGMT_CACHE_INDEX_BIT0_OFFSETr = 1047, + ETM_TMMU_CFGMT_CACHE_INDEX_BIT1_OFFSETr = 1048, + ETM_TMMU_CFGMT_CACHE_INDEX_BIT2_OFFSETr = 1049, + ETM_TMMU_CFGMT_CACHE_INDEX_BIT3_OFFSETr = 1050, + ETM_TMMU_CFGMT_CACHE_INDEX_BIT4_OFFSETr = 1051, + ETM_TMMU_CFGMT_CACHE_INDEX_BIT5_OFFSETr = 1052, + ETM_TMMU_CFGMT_CACHE_INDEX_BIT6_OFFSETr = 1053, + ETM_TMMU_CFGMT_CACHE_INDEX_BIT7_OFFSETr = 1054, + ETM_TMMU_CFGMT_CACHE_INDEX_BIT8_OFFSETr = 1055, + ETM_TMMU_CFGMT_CACHE_INDEX_BIT9_OFFSETr = 1056, + ETM_TMMU_CFGMT_CACHE_INDEX_BIT10_OFFSETr = 1057, + ETM_TMMU_CFGMT_CACHE_INDEX_BIT11_OFFSETr = 1058, + ETM_TMMU_CFGMT_CACHE_INDEX_BIT12_OFFSETr = 1059, + ETM_SHAP_BKTFULL_FIFO_FULL_FLAGREGISTERr = 1060, + ETM_SHAP_FIFO_FULL_REGREGISTERr = 1061, + ETM_SHAP_FIFO_EMPTY_REGREGISTERr = 1062, + ETM_SHAP_FIFO_ALMOST_FULL_REGREGISTERr = 1063, + ETM_SHAP_FIFO_ALMOST_EMPTY_REGREGISTERr = 1064, + ETM_CRDT_CREDIT_SPACE_SELECTr = 1065, + ETM_CRDT_STAT_SPACE_MAXr = 1066, + ETM_CRDT_STAT_SPACE_MINr = 1067, + ETM_CRDT_STAT_SPACE_CREDITr = 1068, + ETM_CRDT_STAT_QUE_STEP8_CREDITr = 1069, + ETM_CRDT_SPECIAL_QUEr = 1070, + ETM_CRDT_SPECIAL_QUE_CREDITr = 1071, + ETM_CRDT_LIF_CONGEST_CREDIT_CNTr = 1072, + ETM_CRDT_LIF_PORT_CONGEST_CREDIT_CNTr = 1073, + ETM_CRDT_CRDT_CONGEST_CREDIT_CNTr = 1074, + ETM_CRDT_CRDT_PORT_CONGEST_CREDIT_CNTr = 1075, + ETM_CRDT_CONGEST_PORT_IDr = 1076, + ETM_CRDT_DEV_LINK_CONTROLr = 1077, + ETM_CRDT_CRDT_SA_PORT_RDYr = 1078, + ETM_CRDT_CRDT_CONGEST_MODE_SELECTr = 1079, + ETM_CRDT_FIFO_OUT_ALL_CRS_NORMAL_CNTr = 1080, + ETM_CRDT_FIFO_OUT_ALL_CRS_OFF_CNTr = 1081, + ETM_CRDT_FIFO_OUT_QUE_CRS_NORMAL_CNTr = 1082, + ETM_CRDT_FIFO_OUT_QUE_CRS_OFF_CNTr = 1083, + ETM_CRDT_MODE_ADD_60Gr = 1084, + ETM_CRDT_PP_TOKEN_ADDr = 1085, + ETM_CRDT_PP_CIR_TOKEN_TOTAL_DIST_CNTr = 1086, + ETM_CRDT_PP_CIR_TOKEN_TOTAL_DEC_CNTr = 1087, + ETM_CRDT_DEV_CREDIT_CNTr = 1088, + ETM_CRDT_NO_CREDIT_CNT1r = 1089, + ETM_CRDT_NO_CREDIT_CNT2r = 1090, + ETM_CRDT_ASM_INTERVAL_0_CFGr = 1091, + ETM_CRDT_ASM_INTERVAL_1_CFGr = 1092, + ETM_CRDT_ASM_INTERVAL_2_CFGr = 1093, + ETM_CRDT_ASM_INTERVAL_3_CFGr = 1094, + ETM_CRDT_ASM_INTERVAL_4_CFGr = 1095, + ETM_CRDT_ASM_INTERVAL_5CFGr = 1096, + ETM_CRDT_ASM_INTERVAL_6_CFGr = 1097, + ETM_CRDT_ASM_INTERVAL_7_CFGr = 1098, + ETM_CRDT_CRDT_TOTAL_CONGEST_MODE_CFGr = 1099, + ETM_CRDT_RCI_FIFO_INI_DEEP_CFGr = 1100, + ETM_CRDT_CRDT_ECCr = 1101, + ETM_CRDT_UCN_ASM_RDY_SHIELD_ENr = 1102, + ETM_CRDT_UCN_ASM_RDYr = 1103, + ETM_CRDT_RCI_GRADEr = 1104, + ETM_CRDT_CRDT_RCI_VALUE_Rr = 1105, + ETM_CRDT_CRDT_INTERVAL_NOWr = 1106, + ETM_CRDT_CRS_SHEILD_FLOW_ID_CFGr = 1107, + ETM_CRDT_CRS_SHEILD_EN_CFGr = 1108, + ETM_CRDT_CRS_SHEILD_VALUE_CFGr = 1109, + ETM_CRDT_TEST_TOKEN_CALC_CTRLr = 1110, + ETM_CRDT_TEST_TOKEN_SAMPLE_CYCLE_NUMr = 1111, + ETM_CRDT_Q_STATE_0_7r = 1112, + ETM_CRDT_Q_STATE_8_15r = 1113, + ETM_QMU_CSW_CSCH_RD_CMD_CNTr = 1114, + ETM_QMU_CSW_CSCH_RD_SOP_CNTr = 1115, + ETM_QMU_CSW_CSCH_RD_EOP_CNTr = 1116, + ETM_QMU_CSW_CSCH_RD_DROP_CNTr = 1117, + ETM_QMU_CSCH_MMU_RD_CMD_CNTr = 1118, + ETM_QMU_CSCH_MMU_RD_SOP_CNTr = 1119, + ETM_QMU_CSCH_MMU_RD_EOP_CNTr = 1120, + ETM_QMU_CSCH_MMU_RD_DROP_CNTr = 1121, + ETM_QMU_QCFG_QSCH_CRS_FILTERr = 1122, + ETM_QMU_QCFG_QSCH_CRS_FORCE_ENr = 1123, + ETM_QMU_QCFG_QSCH_CRS_FORCE_QNUMr = 1124, + ETM_QMU_QCFG_QSCH_CRS_FORCE_CRSr = 1125, + ETM_QMU_CFGMT_OSHP_SGMII_SHAP_MODEr = 1126, + ETM_QMU_CFGMT_QMU_SASHAP_ENr = 1127, + ETM_QMU_CFGMT_SASHAP_TOKEN_MAXr = 1128, + ETM_QMU_CFGMT_SASHAP_TOKEN_MINr = 1129, + ETM_QMU_CFG_QSCH_Q3LBADDRATEr = 1130, + ETM_QMU_CFG_QSCH_Q012LBADDRATEr = 1131, + ETM_QMU_CFG_QSCH_Q3CREDITLBMAXCNTr = 1132, + ETM_QMU_CFG_QSCH_Q012CREDITLBMAXCNTr = 1133, + ETM_QMU_CFG_QSCH_MUL_TOKEN_GEN_NUMr = 1134, + ETM_QMU_CFG_QSCH_Q3_CREDIT_LB_CONTROL_ENr = 1135, + ETM_QMU_CFG_QSCH_Q012_CREDIT_LB_CONTROL_ENr = 1136, + ETM_QMU_CFG_QSCH_SP_DWRR_ENr = 1137, + ETM_QMU_CFG_QSCH_Q01_ATTACH_ENr = 1138, + ETM_QMU_CFG_QSCH_W0r = 1139, + ETM_QMU_CFG_QSCH_W1r = 1140, + ETM_QMU_CFG_QSCH_W2r = 1141, + ETM_QMU_CFG_QSCH_LKYBKTMAXCNT1r = 1142, + ETM_QMU_CFG_QSCH_LKYBKTMAXCNT2r = 1143, + ETM_QMU_CFG_QSCH_LKYBKTDCRRATE1r = 1144, + ETM_QMU_CFG_QSCH_LKYBKTDCRRATE2r = 1145, + ETM_QMU_CFG_QSCH_LKYBKTDCRRATE3r = 1146, + ETM_QMU_CFG_QSCH_LKYBKTMAXCNT3r = 1147, + ETM_QMU_CFG_QSCH_QMU_MUL_AUTO_SA_VERSIONr = 1148, + ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_0r = 1149, + ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_1r = 1150, + ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_2r = 1151, + ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_3r = 1152, + ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_4r = 1153, + ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_5r = 1154, + ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_6r = 1155, + ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_7r = 1156, + ETM_QMU_CFG_QSCH_REMOTE_CREDIT_FIFO_ALMOST_FULL_THr = 1157, + ETM_QMU_CFG_QSCH_AUTO_CREDIT_FIFO_ALMOST_FULL_THr = 1158, + ETM_QMU_CFG_QSCH_Q3_CREDIT_FIFO_ALMOST_FULL_THr = 1159, + ETM_QMU_CFG_QSCH_Q012_CREDIT_FIFO_ALMOST_FULL_THr = 1160, + ETM_QMU_CFG_QSCH_MUL_FC_RES_ENr = 1161, + ETM_QMU_CFGMT_MUL_OVF_UDF_FLG_QUERYr = 1162, + ETM_QMU_CFGMT_MUL_CNG_FLG_QUERYr = 1163, + ETM_QMU_QSCH_CFG_LKYBKTVAL1r = 1164, + ETM_QMU_QSCH_CFG_LKYBKTVAL2r = 1165, + ETM_QMU_QSCH_CFG_LKYBKTVAL3r = 1166, + ETM_QMU_QSCH_CFG_Q3LBVALr = 1167, + ETM_QMU_QSCH_CFG_Q012LBVALr = 1168, + ETM_QMU_QLIST_CFGMT_RAM_ECC_ERR2r = 1169, + ETM_QMU_CSCH_AGED_CMD_CNTr = 1170, + ETM_QMU_CSCH_QCFG_CSCH_CONGEST_CNTr = 1171, + ETM_QMU_CSCH_QCFG_QLIST_CSCH_SOP_CNTr = 1172, + ETM_QMU_CSCH_QCFG_QLIST_CSCH_EOP_CNTr = 1173, + ETM_QMU_CSCH_QCFG_CSCH_CSW_SOP_CNTr = 1174, + ETM_QMU_CSCH_QCFG_CSCH_CSW_EOP_CNTr = 1175, + ETM_QMU_CSCH_QCFG_QLIST_CSCH_DROP_CNTr = 1176, + ETM_QMU_CSCH_QCFG_CSCH_CSW_DROP_CNTr = 1177, + ETM_QMU_CSW_MMU_SOP_CMD_CNTr = 1178, + ETM_QMU_MMU_CSW_SOP_DATA_CNTr = 1179, + ETM_QMU_CSW_QSCH_FEEDB_CNTr = 1180, + ETM_QMU_QMU_CRDT_PORT_FC_CNTr = 1181, + ETM_QMU_CSCH_R_BLOCK_CNTr = 1182, + ETM_QMU_QCFG_QLIST_QDS_HEAD_RDr = 1183, + ETM_QMU_QCFG_QLIST_QDS_TAIL_RDr = 1184, + ETM_QMU_QCFG_QLIST_EPT_RDr = 1185, + ETM_QMU_QCFG_QLIST_AGE_FLAG_RDr = 1186, + ETM_QMU_QCFG_QLIST_CTI_RDr = 1187, + ETM_QMU_QCFG_QLIST_CTO_RDr = 1188, + ETM_QMU_QCFG_QLIST_CHK_RDr = 1189, + ETM_QMU_QCFG_QLIST_NOD_RDr = 1190, + ETM_QMU_QCFG_QLIST_BIU_RDr = 1191, + ETM_QMU_QSCH_R_WLIST_FLAGr = 1192, + ETM_QMU_QCFG_CRS_FLG_RDr = 1193, + ETM_QMU_CFGMT_QMU_IMEM_AGE_QDSr = 1194, + ETM_QMU_CFGMT_QMU_IMEM_AGE_QLENr = 1195, + ETM_QMU_CFGMT_QMU_IMEM_PD_RAM_LOWr = 1196, + ETM_QMU_CFGMT_QMU_IMEM_PD_RAM_HIGHr = 1197, + ETM_QMU_CFGMT_QMU_IMEM_UP_PTRr = 1198, + ETM_QMU_CFGMT_QMU_IMEM_DOWN_PTRr = 1199, + ETM_QMU_CFGMT_QMU_IMEM_AGE_FLAGr = 1200, + ETM_QMU_CFG_QSCH_LKYBKT2CNGTHr = 1201, + ETM_QMU_CFG_QSCH_LKYBKT1CNGTHr = 1202, + ETM_QMU_CFG_QSCH_LKYBKT3CNGTHr = 1203, + ETM_QMU_CFG_QSCH_RM_MUL_MCN1_CREDIT_VALUEr = 1204, + ETM_QMU_CFG_QSCH_RM_MUL_MCN2_CREDIT_VALUEr = 1205, + ETM_QMU_CFG_QSCH_RM_MUL_MCN3_CREDIT_VALUEr = 1206, + ETM_QMU_RM_MUL_MCN1_RAND_ANSR_SEEDr = 1207, + ETM_QMU_RM_MUL_MCN2_RAND_ANSR_SEEDr = 1208, + ETM_QMU_RM_MUL_MCN3_RAND_ANSR_SEEDr = 1209, + ETM_QMU_RM_MUL_MCN1_RAND_ANSR_THr = 1210, + ETM_QMU_RM_MUL_MCN2_RAND_ANSR_THr = 1211, + ETM_QMU_RM_MUL_MCN3_RAND_ANSR_THr = 1212, + ETM_QMU_RM_MUL_MCN1_RAND_HOLD_BASEr = 1213, + ETM_QMU_RM_MUL_MCN2_RAND_HOLD_BASEr = 1214, + ETM_QMU_RM_MUL_MCN3_RAND_HOLD_BASEr = 1215, + ETM_QMU_RM_MUL_MCN1_RAND_SEL_MASKr = 1216, + ETM_QMU_RM_MUL_MCN2_RAND_SEL_MASKr = 1217, + ETM_QMU_RM_MUL_MCN3_RAND_SEL_MASKr = 1218, + ETM_QMU_RM_MUL_MCN1_RAND_SEL_SEED_REG0r = 1219, + ETM_QMU_RM_MUL_MCN1_RAND_SEL_SEED_REG1r = 1220, + ETM_QMU_RM_MUL_MCN2_RAND_SEL_SEED_REG0r = 1221, + ETM_QMU_RM_MUL_MCN2_RAND_SEL_SEED_REG1r = 1222, + ETM_QMU_RM_MUL_MCN3_RAND_SEL_SEED_REG0r = 1223, + ETM_QMU_RM_MUL_MCN3_RAND_SEL_SEED_REG1r = 1224, + ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH1r = 1225, + ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH2r = 1226, + ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH3r = 1227, + ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH4r = 1228, + ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH5r = 1229, + ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH6r = 1230, + ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH7r = 1231, + ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH1r = 1232, + ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH2r = 1233, + ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH3r = 1234, + ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH4r = 1235, + ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH5r = 1236, + ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH6r = 1237, + ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH7r = 1238, + ETM_QMU_RM_MUL_MCN3_STEP_WAIT_TH1r = 1239, + ETM_QMU_RM_MUL_MCN3_STEP_WAIT_TH2r = 1240, + ETM_QMU_RM_MUL_MCN3_STEP_WAIT_TH3r = 1241, + ETM_QMU_RM_MUL_MCN3_STEP_WAIT_TH4r = 1242, + ETM_QMU_RM_MUL_MCN3_STEP_WAIT_TH5r = 1243, + ETM_QMU_RM_MUL_MCN3_STEP_WAIT_TH6r = 1244, + ETM_QMU_RM_MUL_MCN3STEP_WAIT_TH7r = 1245, + ETM_QMU_CFG_QSCH_MULCRDCNTRATE0r = 1246, + ETM_QMU_CFG_QSCH_MULCRDCNTRATE1r = 1247, + ETM_QMU_CFG_QSCH_MULCRDCNTRATE2r = 1248, + ETM_QMU_CFG_QSCH_MULCRDCNTRATE3r = 1249, + ETM_QMU_CFG_QSCH_MULCRDCNTRATE4r = 1250, + ETM_QMU_CFG_QSCH_MULCRDCNTRATE5r = 1251, + ETM_QMU_CFG_QSCH_MULCRDCNTRATE6r = 1252, + ETM_QMU_CFG_QSCH_MULCRDCNTRATE7r = 1253, + ETM_QMU_CFG_QSCH_MULCRDCNTRATE8r = 1254, + ETM_QMU_CFG_QSCH_MULCRDCNTRATE9r = 1255, + ETM_QMU_CFG_QSCH_MULCRDCNTRATE10r = 1256, + ETM_QMU_CFG_QSCH_MULCRDCNTRATE11r = 1257, + ETM_QMU_CFG_QSCH_MULCRDCNTRATE12r = 1258, + ETM_QMU_CFG_QSCH_MULCRDCNTRATE13r = 1259, + ETM_QMU_CFG_QSCH_MULCRDCNTRATE14r = 1260, + ETM_QMU_CFG_QSCH_MULCRDCNTRATE15r = 1261, + ETM_QMU_CFG_QSCH_MULCRDCNTRATE16r = 1262, + ETM_QMU_CFG_QSCH_MULCRDCNTRATE17r = 1263, + ETM_QMU_CFG_QSCH_MULCRDCNTRATE18r = 1264, + ETM_QMU_CFG_QSCH_MULCRDCNTRATE19r = 1265, + ETM_QMU_CFG_QSCH_MULCRDCNTRATE20r = 1266, + ETM_QMU_CFG_QSCH_MULCRDCNTRATE21r = 1267, + ETM_QMU_CFG_QSCH_MULCRDCNTRATE22r = 1268, + ETM_QMU_CFG_QSCH_MULCRDCNTRATE23r = 1269, + ETM_QMU_CFG_QSCH_MULCRDCNTRATE24r = 1270, + ETM_QMU_CFG_QSCH_MULCRDCNTRATE25r = 1271, + ETM_QMU_CFG_QSCH_MULCRDCNTRATE26r = 1272, + ETM_QMU_CFG_QSCH_MULCRDCNTRATE27r = 1273, + ETM_QMU_CFG_QSCH_MULCRDCNTRATE28r = 1274, + ETM_QMU_CFG_QSCH_MULCRDCNTRATE29r = 1275, + ETM_QMU_CFG_QSCH_MULCRDCNTRATE30r = 1276, + ETM_QMU_CFG_QSCH_MULCRDCNTRATE31r = 1277, + ETM_QMU_CFG_QSCH_MULCRDCNTRATE32r = 1278, + ETM_QMU_CFG_QSCH_MULCRDCNTRATE33r = 1279, + ETM_QMU_CFG_QSCH_MULCRDCNTRATE34r = 1280, + ETM_QMU_CFG_QSCH_MULCRDCNTRATE35r = 1281, + ETM_QMU_CFG_QSCH_MULCRDCNTRATE36r = 1282, + ETM_QMU_CFG_QSCH_RM_MUL_MCN1_RAND_HOLD_SHIFTr = 1283, + ETM_QMU_CFG_QSCH_RM_MUL_MCN2_RAND_HOLD_SHIFTr = 1284, + ETM_QMU_CFG_QSCH_RM_MUL_MCN3_RAND_HOLD_SHIFTr = 1285, + ETM_QMU_LAST_DROP_QNUM_GETr = 1286, + ETM_QMU_CRDT_QMU_CREDIT_CNTr = 1287, + ETM_QMU_QMU_TO_QSCH_REPORT_CNTr = 1288, + ETM_QMU_QMU_TO_CGAVD_REPORT_CNTr = 1289, + ETM_QMU_QMU_CRDT_CRS_NORMAL_CNTr = 1290, + ETM_QMU_QMU_CRDT_CRS_OFF_CNTr = 1291, + ETM_QMU_QSCH_QLIST_SHEDULE_CNTr = 1292, + ETM_QMU_QSCH_QLIST_SCH_EPT_CNTr = 1293, + ETM_QMU_QMU_TO_MMU_BLK_WR_CNTr = 1294, + ETM_QMU_QMU_TO_CSW_BLK_RD_CNTr = 1295, + ETM_QMU_QMU_TO_MMU_SOP_WR_CNTr = 1296, + ETM_QMU_QMU_TO_MMU_EOP_WR_CNTr = 1297, + ETM_QMU_QMU_TO_MMU_DROP_WR_CNTr = 1298, + ETM_QMU_QMU_TO_CSW_SOP_RD_CNTr = 1299, + ETM_QMU_QMU_TO_CSW_EOP_RD_CNTr = 1300, + ETM_QMU_QMU_TO_CSW_DROP_RD_CNTr = 1301, + ETM_QMU_MMU_TO_QMU_WR_RELEASE_CNTr = 1302, + ETM_QMU_MMU_TO_QMU_RD_RELEASE_CNTr = 1303, + ETM_QMU_OBSERVE_QNUM_SETr = 1304, + ETM_QMU_SPEC_Q_PKT_RECEIVEDr = 1305, + ETM_QMU_SPEC_Q_PKT_DROPPEDr = 1306, + ETM_QMU_SPEC_Q_PKT_SCHEDULEDr = 1307, + ETM_QMU_SPEC_Q_WR_CMD_SENTr = 1308, + ETM_QMU_SPEC_Q_RD_CMD_SENTr = 1309, + ETM_QMU_SPEC_Q_PKT_ENQr = 1310, + ETM_QMU_SPEC_Q_PKT_DEQr = 1311, + ETM_QMU_SPEC_Q_CRDT_UNCON_RECEIVEDr = 1312, + ETM_QMU_SPEC_Q_CRDT_CONG_RECEIVEDr = 1313, + ETM_QMU_SPEC_Q_CRS_NORMAL_CNTr = 1314, + ETM_QMU_SPEC_Q_CRS_OFF_CNTr = 1315, + ETM_QMU_OBSERVE_BATCH_SETr = 1316, + ETM_QMU_SPEC_BAT_PKT_RECEIVEDr = 1317, + ETM_QMU_SPEC_BAT_PKT_DROPPEDr = 1318, + ETM_QMU_SPEC_BAT_BLK_SCHEDULEDr = 1319, + ETM_QMU_SPEC_BAT_WR_CMD_SENTr = 1320, + ETM_QMU_SPEC_BAT_RD_CMD_SENTr = 1321, + ETM_QMU_SPEC_BAT_PKT_ENQr = 1322, + ETM_QMU_SPEC_BAT_PKT_DEQr = 1323, + ETM_QMU_SPEC_BAT_CRDT_UNCON_RECEIVEDr = 1324, + ETM_QMU_SPEC_BAT_CRDT_CONG_RECEIVEDr = 1325, + ETM_QMU_SPEC_BAT_CRS_NORMAL_CNTr = 1326, + ETM_QMU_SPEC_BAT_CRS_OFF_CNTr = 1327, + ETM_QMU_BCNTM_OVFL_QNUM_GETr = 1328, + ETM_QMU_CRBAL_A_OVF_QNUM_GETr = 1329, + ETM_QMU_CRBAL_B_OVF_QNUM_GETr = 1330, + ETM_QMU_CRBAL_DROP_QNUM_GETr = 1331, + ETM_QMU_DEQ_FLG_REPORT_CNTr = 1332, + ETM_QMU_SPEC_Q_CRS_GETr = 1333, + ETM_QMU_SPEC_Q_CRS_IN_GETr = 1334, + ETM_QMU_SPEC_Q_CRS_FLG_CSOL_GETr = 1335, + ETM_QMU_EPT_SCH_QNUM_GETr = 1336, + CFG_PCIE_PCIE_DDR_SWITCHr = 1337, + CFG_PCIE_USER0_INT_ENr = 1338, + CFG_PCIE_USER0_INT_MASKr = 1339, + CFG_PCIE_USER0_INT_STATUSr = 1340, + CFG_PCIE_USER1_INT_ENr = 1341, + CFG_PCIE_USER1_INT_MASKr = 1342, + CFG_PCIE_USER1_INT_STATUSr = 1343, + CFG_PCIE_USER2_INT_ENr = 1344, + CFG_PCIE_USER2_INT_MASKr = 1345, + CFG_PCIE_USER2_INT_STATUSr = 1346, + CFG_PCIE_ECC_1B_INT_ENr = 1347, + CFG_PCIE_ECC_1B_INT_MASKr = 1348, + CFG_PCIE_ECC_1B_INT_STATUSr = 1349, + CFG_PCIE_ECC_2B_INT_ENr = 1350, + CFG_PCIE_ECC_2B_INT_MASKr = 1351, + CFG_PCIE_ECC_2B_INT_STATUSr = 1352, + CFG_PCIE_CFG_INT_STATUSr = 1353, + CFG_PCIE_I_CORE_TO_CNTLr = 1354, + CFG_PCIE_TEST_IN_LOWr = 1355, + CFG_PCIE_TEST_IN_HIGHr = 1356, + CFG_PCIE_LOCAL_INTERRUPT_OUTr = 1357, + CFG_PCIE_PL_LTSSMr = 1358, + CFG_PCIE_TEST_OUT0r = 1359, + CFG_PCIE_TEST_OUT1r = 1360, + CFG_PCIE_TEST_OUT2r = 1361, + CFG_PCIE_TEST_OUT3r = 1362, + CFG_PCIE_TEST_OUT4r = 1363, + CFG_PCIE_TEST_OUT5r = 1364, + CFG_PCIE_TEST_OUT6r = 1365, + CFG_PCIE_TEST_OUT7r = 1366, + CFG_PCIE_SYNC_O_CORE_STATUSr = 1367, + CFG_PCIE_SYNC_O_ALERT_DBEr = 1368, + CFG_PCIE_SYNC_O_ALERT_SBEr = 1369, + CFG_PCIE_SYNC_O_LINK_LOOPBACK_ENr = 1370, + CFG_PCIE_SYNC_O_LOCAL_FS_LF_VALIDr = 1371, + CFG_PCIE_SYNC_O_RX_IDLE_DETECTr = 1372, + CFG_PCIE_SYNC_O_RX_RDYr = 1373, + CFG_PCIE_SYNC_O_TX_RDYr = 1374, + CFG_PCIE_PCIE_LINK_UP_CNTr = 1375, + CFG_PCIE_TEST_OUT_PCIE0r = 1376, + CFG_PCIE_TEST_OUT_PCIE1r = 1377, + CFG_PCIE_TEST_OUT_PCIE2r = 1378, + CFG_PCIE_TEST_OUT_PCIE3r = 1379, + CFG_PCIE_TEST_OUT_PCIE4r = 1380, + CFG_PCIE_TEST_OUT_PCIE5r = 1381, + CFG_PCIE_TEST_OUT_PCIE6r = 1382, + CFG_PCIE_TEST_OUT_PCIE7r = 1383, + CFG_PCIE_TEST_OUT_PCIE8r = 1384, + CFG_PCIE_TEST_OUT_PCIE9r = 1385, + CFG_PCIE_TEST_OUT_PCIE10r = 1386, + CFG_PCIE_TEST_OUT_PCIE11r = 1387, + CFG_PCIE_TEST_OUT_PCIE12r = 1388, + CFG_PCIE_TEST_OUT_PCIE13r = 1389, + CFG_PCIE_TEST_OUT_PCIE14r = 1390, + CFG_PCIE_TEST_OUT_PCIE15r = 1391, + CFG_PCIE_INT_REPEAT_ENr = 1392, + CFG_PCIE_DBG_AWID_AXI_MSTr = 1393, + CFG_PCIE_DBG_AWADDR_AXI_MST0r = 1394, + CFG_PCIE_DBG_AWADDR_AXI_MST1r = 1395, + CFG_PCIE_DBG_AWLEN_AXI_MSTr = 1396, + CFG_PCIE_DBG_AWSIZE_AXI_MSTr = 1397, + CFG_PCIE_DBG_AWBURST_AXI_MSTr = 1398, + CFG_PCIE_DBG_AWLOCK_AXI_MSTr = 1399, + CFG_PCIE_DBG_AWCACHE_AXI_MSTr = 1400, + CFG_PCIE_DBG_AWPROT_AXI_MSTr = 1401, + CFG_PCIE_DBG_WID_AXI_MSTr = 1402, + CFG_PCIE_DBG_WDATA_AXI_MST0r = 1403, + CFG_PCIE_DBG_WDATA_AXI_MST1r = 1404, + CFG_PCIE_DBG_WDATA_AXI_MST2r = 1405, + CFG_PCIE_DBG_WDATA_AXI_MST3r = 1406, + CFG_PCIE_DBG_WSTRB_AXI_MSTr = 1407, + CFG_PCIE_DBG_WLAST_AXI_MSTr = 1408, + CFG_PCIE_DBG_ARID_AXI_MSTr = 1409, + CFG_PCIE_DBG_ARADDR_AXI_MST0r = 1410, + CFG_PCIE_DBG_ARADDR_AXI_MST1r = 1411, + CFG_PCIE_DBG_ARLEN_AXI_MSTr = 1412, + CFG_PCIE_DBG_ARSIZE_AXI_MSTr = 1413, + CFG_PCIE_DBG_ARBURST_AXI_MSTr = 1414, + CFG_PCIE_DBG_ARLOCK_AXI_MSTr = 1415, + CFG_PCIE_DBG_ARCACHE_AXI_MSTr = 1416, + CFG_PCIE_DBG_ARPROT_AXI_MSTr = 1417, + CFG_PCIE_DBG_RDATA_AXI_MST0r = 1418, + CFG_PCIE_DBG_RDATA_AXI_MST1r = 1419, + CFG_PCIE_DBG_RDATA_AXI_MST2r = 1420, + CFG_PCIE_DBG_RDATA_AXI_MST3r = 1421, + CFG_PCIE_AXI_MST_STATEr = 1422, + CFG_PCIE_AXI_CFG_STATEr = 1423, + CFG_PCIE_AXI_SLV_RD_STATEr = 1424, + CFG_PCIE_AXI_SLV_WR_STATEr = 1425, + CFG_PCIE_AXIM_DELAY_ENr = 1426, + CFG_PCIE_AXIM_DELAYr = 1427, + CFG_PCIE_AXIM_SPEED_WRr = 1428, + CFG_PCIE_AXIM_SPEED_RDr = 1429, + CFG_PCIE_DBG_AWADDR_AXI_SLV0r = 1430, + CFG_PCIE_DBG_AWADDR_AXI_SLV1r = 1431, + CFG_PCIE_DBG0_WDATA_AXI_SLV0r = 1432, + CFG_PCIE_DBG0_WDATA_AXI_SLV1r = 1433, + CFG_PCIE_DBG0_WDATA_AXI_SLV2r = 1434, + CFG_PCIE_DBG0_WDATA_AXI_SLV3r = 1435, + CFG_PCIE_DBG1_WDATA_AXI_SLV0r = 1436, + CFG_PCIE_DBG1_WDATA_AXI_SLV1r = 1437, + CFG_PCIE_DBG1_WDATA_AXI_SLV2r = 1438, + CFG_PCIE_DBG1_WDATA_AXI_SLV3r = 1439, + CFG_PCIE_DBG2_WDATA_AXI_SLV0r = 1440, + CFG_PCIE_DBG2_WDATA_AXI_SLV1r = 1441, + CFG_PCIE_DBG2_WDATA_AXI_SLV2r = 1442, + CFG_PCIE_DBG2_WDATA_AXI_SLV3r = 1443, + CFG_PCIE_DBG3_WDATA_AXI_SLV0r = 1444, + CFG_PCIE_DBG3_WDATA_AXI_SLV1r = 1445, + CFG_PCIE_DBG3_WDATA_AXI_SLV2r = 1446, + CFG_PCIE_DBG3_WDATA_AXI_SLV3r = 1447, + CFG_PCIE_DBG4_WDATA_AXI_SLV0r = 1448, + CFG_PCIE_DBG4_WDATA_AXI_SLV1r = 1449, + CFG_PCIE_DBG4_WDATA_AXI_SLV2r = 1450, + CFG_PCIE_DBG4_WDATA_AXI_SLV3r = 1451, + CFG_PCIE_DBG5_WDATA_AXI_SLV0r = 1452, + CFG_PCIE_DBG5_WDATA_AXI_SLV1r = 1453, + CFG_PCIE_DBG5_WDATA_AXI_SLV2r = 1454, + CFG_PCIE_DBG5_WDATA_AXI_SLV3r = 1455, + CFG_PCIE_DBG6_WDATA_AXI_SLV0r = 1456, + CFG_PCIE_DBG6_WDATA_AXI_SLV1r = 1457, + CFG_PCIE_DBG6_WDATA_AXI_SLV2r = 1458, + CFG_PCIE_DBG6_WDATA_AXI_SLV3r = 1459, + CFG_PCIE_DBG7_WDATA_AXI_SLV0r = 1460, + CFG_PCIE_DBG7_WDATA_AXI_SLV1r = 1461, + CFG_PCIE_DBG7_WDATA_AXI_SLV2r = 1462, + CFG_PCIE_DBG7_WDATA_AXI_SLV3r = 1463, + CFG_PCIE_DBG8_WDATA_AXI_SLV0r = 1464, + CFG_PCIE_DBG8_WDATA_AXI_SLV1r = 1465, + CFG_PCIE_DBG8_WDATA_AXI_SLV2r = 1466, + CFG_PCIE_DBG8_WDATA_AXI_SLV3r = 1467, + CFG_PCIE_DBG9_WDATA_AXI_SLV0r = 1468, + CFG_PCIE_DBG9_WDATA_AXI_SLV1r = 1469, + CFG_PCIE_DBG9_WDATA_AXI_SLV2r = 1470, + CFG_PCIE_DBG9_WDATA_AXI_SLV3r = 1471, + CFG_PCIE_DBG_AWLEN_AXI_SLVr = 1472, + CFG_PCIE_DBG_WLAST_AXI_SLVr = 1473, + CFG_PCIE_DBG_ARADDR_AXI_SLV0r = 1474, + CFG_PCIE_DBG_ARADDR_AXI_SLV1r = 1475, + CFG_PCIE_DBG0_RDATA_AXI_SLV0r = 1476, + CFG_PCIE_DBG0_RDATA_AXI_SLV1r = 1477, + CFG_PCIE_DBG0_RDATA_AXI_SLV2r = 1478, + CFG_PCIE_DBG0_RDATA_AXI_SLV3r = 1479, + CFG_PCIE_DBG1_RDATA_AXI_SLV0r = 1480, + CFG_PCIE_DBG1_RDATA_AXI_SLV1r = 1481, + CFG_PCIE_DBG1_RDATA_AXI_SLV2r = 1482, + CFG_PCIE_DBG1_RDATA_AXI_SLV3r = 1483, + CFG_PCIE_DBG_RLAST_AXI_SLVr = 1484, + CFG_DMA_DMA_ENABLEr = 1485, + CFG_DMA_UP_REQr = 1486, + CFG_DMA_DMA_UP_CURRENT_STATEr = 1487, + CFG_DMA_DMA_UP_REQ_ACKr = 1488, + CFG_DMA_DMA_DONE_LATCHr = 1489, + CFG_DMA_DMA_UP_CPU_ADDR_LOW32r = 1490, + CFG_DMA_DMA_UP_CPU_ADDR_HIGH32r = 1491, + CFG_DMA_DMA_UP_SE_ADDRr = 1492, + CFG_DMA_DMA_DONE_INTr = 1493, + CFG_DMA_SP_CFGr = 1494, + CFG_DMA_DMA_INGr = 1495, + CFG_DMA_RD_TIMEOUT_THRESHr = 1496, + CFG_DMA_DMA_TAB_STA_UP_FIFO_GAPr = 1497, + CFG_DMA_CFG_MAC_TIMr = 1498, + CFG_DMA_CFG_MAC_NUMr = 1499, + CFG_DMA_INIT_BD_ADDRr = 1500, + CFG_DMA_MAC_UP_BD_ADDR1_LOW32r = 1501, + CFG_DMA_MAC_UP_BD_ADDR1_HIGH32r = 1502, + CFG_DMA_MAC_UP_BD_ADDR2_LOW32r = 1503, + CFG_DMA_MAC_UP_BD_ADDR2_HIGH32r = 1504, + CFG_DMA_CFG_MAC_MAX_NUMr = 1505, + CFG_DMA_DMA_WBUF_FF_EMPTYr = 1506, + CFG_DMA_DMA_WBUF_STATEr = 1507, + CFG_DMA_DMA_MAC_BD_ADDR_LOW32r = 1508, + CFG_DMA_DMA_MAC_BD_ADDR_HIGH32r = 1509, + CFG_DMA_MAC_UP_ENABLEr = 1510, + CFG_DMA_MAC_ENDIANr = 1511, + CFG_DMA_UP_ENDIANr = 1512, + CFG_DMA_DMA_UP_RD_CNT_LATCHr = 1513, + CFG_DMA_DMA_UP_RCV_CNT_LATCHr = 1514, + CFG_DMA_DMA_UP_CNT_LATCHr = 1515, + CFG_DMA_CPU_RD_BD_PULSEr = 1516, + CFG_DMA_CPU_BD_THRESHOLDr = 1517, + CFG_DMA_CPU_BD_USED_CNTr = 1518, + CFG_DMA_DMA_UP_RCV_STATUSr = 1519, + CFG_DMA_SLV_RID_ERR_ENr = 1520, + CFG_DMA_SLV_RRESP_ERR_ENr = 1521, + CFG_DMA_SE_RDBK_FF_FULLr = 1522, + CFG_DMA_DMA_UP_DATA_COUNTr = 1523, + CFG_DMA_DMA_MWR_FIFO_AFULL_GAPr = 1524, + CFG_DMA_DMA_INFO_FIFO_AFULL_GAPr = 1525, + CFG_DMA_DMA_RD_TIMEOUT_SETr = 1526, + CFG_DMA_DMA_BD_DAT_ERR_ENr = 1527, + CFG_DMA_DMA_REPEAT_CNTr = 1528, + CFG_DMA_DMA_RD_TIMEOUT_ENr = 1529, + CFG_DMA_DMA_REPEAT_READr = 1530, + CFG_DMA_DMA_REPEAT_READ_ENr = 1531, + CFG_DMA_BD_CTL_STATEr = 1532, + CFG_DMA_DMA_DONE_INT_CNT_WRr = 1533, + CFG_DMA_DMA_DONE_INT_CNT_MACr = 1534, + CFG_DMA_CURRENT_MAC_NUMr = 1535, + CFG_DMA_CFG_MAC_AFIFO_AFULLr = 1536, + CFG_DMA_DMA_MAC_FF_FULLr = 1537, + CFG_DMA_USER_AXI_MSTr = 1538, + CFG_CSR_SBUS_STATEr = 1539, + CFG_CSR_MST_DEBUG_ENr = 1540, + CFG_CSR_SBUS_COMMAND_SELr = 1541, + CFG_CSR_SOC_RD_TIME_OUT_THRESHr = 1542, + CFG_CSR_BIG_LITTLE_BYTE_ORDERr = 1543, + CFG_CSR_ECC_BYPASS_READr = 1544, + CFG_CSR_AHB_ASYNC_WR_FIFO_AFULL_GAPr = 1545, + CFG_CSR_AHB_ASYNC_RD_FIFO_AFULL_GAPr = 1546, + CFG_CSR_AHB_ASYNC_CPL_FIFO_AFULL_GAPr = 1547, + CFG_CSR_MST_DEBUG_DATA0_HIGH26r = 1548, + CFG_CSR_MST_DEBUG_DATA0_LOW32r = 1549, + CFG_CSR_MST_DEBUG_DATA1_HIGH26r = 1550, + CFG_CSR_MST_DEBUG_DATA1_LOW32r = 1551, + CFG_CSR_MST_DEBUG_DATA2_HIGH26r = 1552, + CFG_CSR_MST_DEBUG_DATA2_LOW32r = 1553, + CFG_CSR_MST_DEBUG_DATA3_HIGH26r = 1554, + CFG_CSR_MST_DEBUG_DATA3_LOW32r = 1555, + CFG_CSR_MST_DEBUG_DATA4_HIGH26r = 1556, + CFG_CSR_MST_DEBUG_DATA4_LOW32r = 1557, + CFG_CSR_MST_DEBUG_DATA5_HIGH26r = 1558, + CFG_CSR_MST_DEBUG_DATA5_LOW32r = 1559, + CFG_CSR_MST_DEBUG_DATA6_HIGH26r = 1560, + CFG_CSR_MST_DEBUG_DATA6_LOW32r = 1561, + CFG_CSR_MST_DEBUG_DATA7_HIGH26r = 1562, + CFG_CSR_MST_DEBUG_DATA7_LOW32r = 1563, + CFG_CSR_MST_DEBUG_DATA8_HIGH26r = 1564, + CFG_CSR_MST_DEBUG_DATA8_LOW32r = 1565, + CFG_CSR_MST_DEBUG_DATA9_HIGH26r = 1566, + CFG_CSR_MST_DEBUG_DATA9_LOW32r = 1567, + CFG_CSR_MST_DEBUG_DATA10_HIGH26r = 1568, + CFG_CSR_MST_DEBUG_DATA10_LOW32r = 1569, + CFG_CSR_MST_DEBUG_DATA11_HIGH26r = 1570, + CFG_CSR_MST_DEBUG_DATA11_LOW32r = 1571, + CFG_CSR_MST_DEBUG_DATA12_HIGH26r = 1572, + CFG_CSR_MST_DEBUG_DATA12_LOW32r = 1573, + CFG_CSR_MST_DEBUG_DATA13_HIGH26r = 1574, + CFG_CSR_MST_DEBUG_DATA13_LOW32r = 1575, + CFG_CSR_MST_DEBUG_DATA14_HIGH26r = 1576, + CFG_CSR_MST_DEBUG_DATA14_LOW32r = 1577, + CFG_CSR_MST_DEBUG_DATA15_HIGH26r = 1578, + CFG_CSR_MST_DEBUG_DATA15_LOW32r = 1579, + NPPU_MR_CFG_IND_ACCESS_STATESr = 1580, + NPPU_MR_CFG_IND_ACCESS_CMD0r = 1581, + NPPU_MR_CFG_IND_ACCESS_DATA0r = 1582, + NPPU_MR_CFG_IND_ACCESS_DATA1r = 1583, + NPPU_MR_CFG_IND_ACCESS_CMD1r = 1584, + NPPU_MR_CFG_MR_INIT_DONEr = 1585, + NPPU_MR_CFG_CNT_MODE_REGr = 1586, + NPPU_MR_CFG_CFG_ECC_BYPASS_READr = 1587, + NPPU_MR_CFG_CFG_REP_MODr = 1588, + NPPU_MR_CFG_BLOCK_PTR_FIFO_AFUL_THr = 1589, + NPPU_MR_CFG_PRE_RCV_PTR_FIFO_AFUL_THr = 1590, + NPPU_MR_CFG_MGID_FIFO_AFUL_THr = 1591, + NPPU_MR_CFG_REP_CMD_FIFO_AFUL_THr = 1592, + NPPU_MR_CFG_MR_INT_MASK_1r = 1593, + NPPU_MR_CFG_MR_INT_MASK_2r = 1594, + NPPU_MR_CFG_MR_INT_MASK_3r = 1595, + NPPU_MR_CFG_MR_INT_MASK_4r = 1596, + NPPU_MR_CFG_MR_STATES_1r = 1597, + NPPU_MR_CFG_MR_STATES_2r = 1598, + NPPU_MR_CFG_MR_STATES_3r = 1599, + NPPU_MR_CFG_MR_STATES_4r = 1600, + NPPU_MR_CFG_MR_STATES_5r = 1601, + NPPU_MR_CFG_MR_STATES_6r = 1602, + NPPU_MR_CFG_MR_STATES_7r = 1603, + NPPU_MR_CFG_MR_STATES_8r = 1604, + NPPU_MR_CFG_MR_SOP_IN_CNTr = 1605, + NPPU_MR_CFG_MR_EOP_IN_CNTr = 1606, + NPPU_MR_CFG_MR_SOP_OUT_CNTr = 1607, + NPPU_MR_CFG_MR_EOP_OUT_CNTr = 1608, + NPPU_MR_CFG_MR_COS0_IN_CNTr = 1609, + NPPU_MR_CFG_MR_COS1_IN_CNTr = 1610, + NPPU_MR_CFG_MR_COS2_IN_CNTr = 1611, + NPPU_MR_CFG_MR_COS3_IN_CNTr = 1612, + NPPU_MR_CFG_MR_COS0_OUT_CNTr = 1613, + NPPU_MR_CFG_MR_COS1_OUT_CNTr = 1614, + NPPU_MR_CFG_MR_COS2_OUT_CNTr = 1615, + NPPU_MR_CFG_MR_COS3_OUT_CNTr = 1616, + NPPU_MR_CFG_MR_ERR_IN_CNTr = 1617, + NPPU_MR_CFG_MR_COS0_SOP_IN_CNTr = 1618, + NPPU_MR_CFG_MR_COS0_EOP_IN_CNTr = 1619, + NPPU_MR_CFG_MR_COS1_SOP_IN_CNTr = 1620, + NPPU_MR_CFG_MR_COS1_EOP_IN_CNTr = 1621, + NPPU_MR_CFG_MR_COS2_SOP_IN_CNTr = 1622, + NPPU_MR_CFG_MR_COS2_EOP_IN_CNTr = 1623, + NPPU_MR_CFG_MR_COS3_SOP_IN_CNTr = 1624, + NPPU_MR_CFG_MR_COS3_EOP_IN_CNTr = 1625, + NPPU_MR_CFG_MR_COS0_IN_ERR_CNTr = 1626, + NPPU_MR_CFG_MR_COS1_IN_ERR_CNTr = 1627, + NPPU_MR_CFG_MR_COS2_IN_ERR_CNTr = 1628, + NPPU_MR_CFG_MR_COS3_IN_ERR_CNTr = 1629, + NPPU_MR_CFG_MR_COS0_SOP_OUT_CNTr = 1630, + NPPU_MR_CFG_MR_COS0_EOP_OUT_CNTr = 1631, + NPPU_MR_CFG_MR_COS1_SOP_OUT_CNTr = 1632, + NPPU_MR_CFG_MR_COS1_EOP_OUT_CNTr = 1633, + NPPU_MR_CFG_MR_COS2_SOP_OUT_CNTr = 1634, + NPPU_MR_CFG_MR_COS2_EOP_OUT_CNTr = 1635, + NPPU_MR_CFG_MR_COS3_SOP_OUT_CNTr = 1636, + NPPU_MR_CFG_MR_COS3_EOP_OUT_CNTr = 1637, + NPPU_MR_CFG_MR_MLT_UNVLD_CNTr = 1638, + NPPU_MR_CFG_MR_SOP_EOP_MATCH_CFGr = 1639, + NPPU_MR_CFG_MR_MLT_UNVLD_MGIDr = 1640, + NPPU_PKTRX_CFG_ISCH_FIFO_TH_1r = 1641, + NPPU_PKTRX_CFG_ISCH_FIFO_TH_2r = 1642, + NPPU_PKTRX_CFG_ISCH_FIFO_TH_3r = 1643, + NPPU_PKTRX_CFG_ISCH_FIFO_TH_4r = 1644, + NPPU_PKTRX_CFG_ISCH_CFG_0r = 1645, + NPPU_PKTRX_CFG_HDU_EX_TPID_0r = 1646, + NPPU_PKTRX_CFG_HDU_EX_TPID_1r = 1647, + NPPU_PKTRX_CFG_HDU_INT_TPID_0r = 1648, + NPPU_PKTRX_CFG_HDU_INT_TPID_1r = 1649, + NPPU_PKTRX_CFG_HDU_HDLC_0r = 1650, + NPPU_PKTRX_CFG_HDU_HDLC_1r = 1651, + NPPU_PKTRX_CFG_HDU_UDF_L3TYPE_0r = 1652, + NPPU_PKTRX_CFG_HDU_UDF_L3TYPE_1r = 1653, + NPPU_PKTRX_CFG_HDU_UDF_L3TYPE_2r = 1654, + NPPU_PKTRX_CFG_HDU_UDF_L3TYPE_3r = 1655, + NPPU_PKTRX_CFG_HDU_UDF_L4TYPE_0r = 1656, + NPPU_PKTRX_CFG_HDU_UDF_L4TYPE_1r = 1657, + NPPU_PKTRX_CFG_HDU_UDF_L4TYPE_2r = 1658, + NPPU_PKTRX_CFG_SLOT_NO_CFGr = 1659, + NPPU_PKTRX_CFG_PKTRX_INT_EN_0r = 1660, + NPPU_PKTRX_CFG_PKTRX_INT_EN_1r = 1661, + NPPU_PKTRX_CFG_PKTRX_INT_MASK_0r = 1662, + NPPU_PKTRX_CFG_PKTRX_INT_MASK_1r = 1663, + NPPU_PKTRX_CFG_PKTRX_INT_STATUSr = 1664, + NPPU_PKTRX_CFG_PKTRX_PORT_RDY0r = 1665, + NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY0r = 1666, + NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY1r = 1667, + NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY2r = 1668, + NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY3r = 1669, + NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY4r = 1670, + NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY5r = 1671, + NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY6r = 1672, + NPPU_PKTRX_CFG_CFG_PORT_L2_OFFSET_MODEr = 1673, + NPPU_IDMA_CFG_INT_RAM_ENr = 1674, + NPPU_IDMA_CFG_INT_RAM_MASKr = 1675, + NPPU_IDMA_CFG_INT_RAM_STATUSr = 1676, + NPPU_IDMA_CFG_SUBSYS_INT_MASK_FLAGr = 1677, + NPPU_IDMA_CFG_SUBSYS_INT_UNMASK_FLAGr = 1678, + NPPU_IDMA_CFG_DEBUG_CNT_RDCLR_MODEr = 1679, + NPPU_PBU_CFG_INT_RAM_EN0r = 1680, + NPPU_PBU_CFG_INT_RAM_MASK0r = 1681, + NPPU_PBU_CFG_INT_RAM_STATUS0r = 1682, + NPPU_PBU_CFG_INT_FIFO_EN0r = 1683, + NPPU_PBU_CFG_INT_FIFO_EN1r = 1684, + NPPU_PBU_CFG_INT_FIFO_MASK0r = 1685, + NPPU_PBU_CFG_INT_FIFO_MASK1r = 1686, + NPPU_PBU_CFG_INT_FIFO_STATUS0r = 1687, + NPPU_PBU_CFG_INT_FIFO_STATUS1r = 1688, + NPPU_PBU_CFG_SUBSYS_INT_MASK_FLAGr = 1689, + NPPU_PBU_CFG_SUBSYS_INT_UNMASK_FLAGr = 1690, + NPPU_PBU_CFG_SA_IP_ENr = 1691, + NPPU_PBU_CFG_DEBUG_CNT_RDCLR_MODEr = 1692, + NPPU_PBU_CFG_FPTR_FIFO_AFUL_ASSERT_CFGr = 1693, + NPPU_PBU_CFG_FPTR_FIFO_AFUL_NEGATE_CFGr = 1694, + NPPU_PBU_CFG_PF_FIFO_AFUL_ASSERT_CFGr = 1695, + NPPU_PBU_CFG_PF_FIFO_AFUL_NEGATE_CFGr = 1696, + NPPU_PBU_CFG_PF_FIFO_AEPT_ASSERT_CFGr = 1697, + NPPU_PBU_CFG_PF_FIFO_AEPT_NEGATE_CFGr = 1698, + NPPU_PBU_CFG_WB_AFUL_ASSERT_CFGr = 1699, + NPPU_PBU_CFG_WB_AFUL_NEGATE_CFGr = 1700, + NPPU_PBU_CFG_SE_KEY_AFUL_ASSERT_CFGr = 1701, + NPPU_PBU_CFG_IFBRD_SE_AFUL_ASSERT_CFGr = 1702, + NPPU_PBU_CFG_IFBRD_SE_AFUL_NEGATE_CFGr = 1703, + NPPU_PBU_CFG_IFBRD_ODMA_AFUL_ASSERT_CFGr = 1704, + NPPU_PBU_CFG_IFBRD_ODMA_AFUL_NEGATE_CFGr = 1705, + NPPU_PBU_CFG_IFBRD_PPU_AFUL_ASSERT_CFGr = 1706, + NPPU_PBU_CFG_IFBRD_PPU_AFUL_NEGATE_CFGr = 1707, + NPPU_PBU_CFG_MC_LOGIC_AFUL_ASSERT_CFGr = 1708, + NPPU_PBU_CFG_MC_LOGIC_AFUL_NEGATE_CFGr = 1709, + NPPU_PBU_CFG_MC_LOGIC_DIFFr = 1710, + NPPU_PBU_CFG_CFG_PEAK_PORT_CNT_CLRr = 1711, + NPPU_PBU_CFG_ALL_FTM_CRDT_THr = 1712, + NPPU_PBU_CFG_ALL_FTM_LINK_TH_01r = 1713, + NPPU_PBU_CFG_ALL_FTM_LINK_TH_23r = 1714, + NPPU_PBU_CFG_ALL_FTM_LINK_TH_45r = 1715, + NPPU_PBU_CFG_ALL_FTM_LINK_TH_6r = 1716, + NPPU_PBU_CFG_ALL_FTM_TOTAL_CONGEST_THr = 1717, + NPPU_PBU_CFG_CFG_CRDT_MODEr = 1718, + NPPU_PBU_CFG_CFG_PFC_RDY_HIGH_TIMEr = 1719, + NPPU_PBU_CFG_CFG_PFC_RDY_LOW_TIMEr = 1720, + NPPU_PBU_STAT_PBU_FC_RDYr = 1721, + NPPU_PBU_STAT_PBU_LIF_GROUP0_RDY0r = 1722, + NPPU_PBU_STAT_PBU_LIF_GROUP0_RDY1r = 1723, + NPPU_PBU_STAT_PBU_LIF_GROUP1_RDYr = 1724, + NPPU_PBU_STAT_PBU_LIF_GROUP0_PFC_RDYr = 1725, + NPPU_PBU_STAT_PBU_LIF_GROUP1_PFC_RDYr = 1726, + NPPU_PBU_STAT_PBU_SA_PORT_RDY_0_31r = 1727, + NPPU_PBU_STAT_PBU_SA_PORT_RDY_32_50r = 1728, + NPPU_PBU_STAT_PBU_PKTRX_MR_PFC_RDYr = 1729, + NPPU_PBU_STAT_PBU_FTM_CRDT_PORT_RDY_0_31r = 1730, + NPPU_PBU_STAT_PBU_FTM_CRDT_PORT_RDY_32_47r = 1731, + NPPU_PBU_STAT_PBU_FTM_CRDT_PORT_CNG_RDY_0_31r = 1732, + NPPU_PBU_STAT_PBU_FTM_CRDT_PORT_CNG_RDY_32_47r = 1733, + NPPU_PBU_STAT_PBU_FTM_CRDT_SYS_INFOr = 1734, + NPPU_ISU_CFG_WEIGHT_NORMAL_MCr = 1735, + NPPU_ISU_CFG_WEIGHT_SA_MCr = 1736, + NPPU_ISU_CFG_WEIGHT_ETMr = 1737, + NPPU_ISU_CFG_WEIGHT_LP_MCr = 1738, + NPPU_ISU_CFG_WEIGHT_OAMr = 1739, + NPPU_ISU_CFG_WEIGHT_LIF_CTRL1r = 1740, + NPPU_ISU_CFG_WEIGHT_LIF_CTRL2r = 1741, + NPPU_ISU_CFG_ECC_BYPASS_READr = 1742, + NPPU_ISU_CFG_ISU_INT_MASKr = 1743, + NPPU_ISU_CFG_CFG_CRDT_CYCLEr = 1744, + NPPU_ISU_CFG_CFG_CRDT_VALUEr = 1745, + NPPU_ISU_CFG_ISU_INT_ENr = 1746, + NPPU_ISU_CFG_ISU_PPU_FIFO_FCr = 1747, + NPPU_ISU_CFG_ISU_INT_STATUSr = 1748, + NPPU_ISU_CFG_FD_PROG_FULL_ASSERT_CFGr = 1749, + NPPU_ISU_CFG_FD_PROG_FULL_NEGATE_CFGr = 1750, + NPPU_ISU_CFG_LP_PROG_FULL_ASSERT_CFGr = 1751, + NPPU_ISU_CFG_LP_PROG_FULL_NEGATE_CFGr = 1752, + NPPU_ISU_STAT_DEBUG_CNT_DAT0r = 1753, + NPPU_ISU_STAT_DEBUG_CNT_DAT1r = 1754, + NPPU_ISU_STAT_DEBUG_CNT_DAT2r = 1755, + NPPU_ISU_STAT_DEBUG_CNT_DAT3r = 1756, + NPPU_ISU_STAT_DEBUG_CNT_DAT4r = 1757, + NPPU_ISU_STAT_DEBUG_CNT_DAT5r = 1758, + NPPU_ISU_STAT_DEBUG_CNT_DAT6r = 1759, + NPPU_ISU_STAT_DEBUG_CNT_DAT7r = 1760, + NPPU_ISU_STAT_DEBUG_CNT_DAT8r = 1761, + NPPU_ISU_STAT_DEBUG_CNT_DAT9r = 1762, + NPPU_ISU_STAT_DEBUG_CNT_DAT10r = 1763, + NPPU_ISU_STAT_DEBUG_CNT_DAT11r = 1764, + NPPU_ISU_STAT_DEBUG_CNT_DAT12r = 1765, + NPPU_ISU_STAT_DEBUG_CNT_DAT13r = 1766, + NPPU_ISU_STAT_DEBUG_CNT_DAT14r = 1767, + NPPU_ISU_STAT_DEBUG_CNT_DAT15r = 1768, + NPPU_ISU_STAT_DEBUG_CNT_DAT16r = 1769, + NPPU_ISU_STAT_DEBUG_CNT_DAT17r = 1770, + NPPU_ISU_STAT_DEBUG_CNT_DAT18r = 1771, + NPPU_ISU_STAT_DEBUG_CNT_DAT19r = 1772, + NPPU_ISU_STAT_DEBUG_CNT_CFGr = 1773, + NPPU_ODMA_CFG_EXSA_TDM_OFFSETr = 1774, + NPPU_ODMA_CFG_ECC_BYPASS_READTr = 1775, + NPPU_ODMA_CFG_ODMA_INT_EN_0r = 1776, + NPPU_ODMA_CFG_ODMA_INT_EN_1r = 1777, + NPPU_ODMA_CFG_ODMA_INT_EN_2r = 1778, + NPPU_ODMA_CFG_ODMA_INT_EN_3r = 1779, + NPPU_ODMA_CFG_ODMA_INT_MASK_0r = 1780, + NPPU_ODMA_CFG_ODMA_INT_MASK_1r = 1781, + NPPU_ODMA_CFG_ODMA_INT_MASK_2r = 1782, + NPPU_ODMA_CFG_ODMA_INT_MASK_3r = 1783, + NPPU_ODMA_CFG_ODMA_INT_STATUS_0r = 1784, + NPPU_ODMA_CFG_ODMA_INT_STATUS_1r = 1785, + NPPU_ODMA_CFG_ODMA_INT_STATUS_2r = 1786, + NPPU_ODMA_CFG_ODMA_INT_STATUS_3r = 1787, + NPPU_ODMA_CFG_SP_TDM_ERR_NOR_CFGr = 1788, + NPPU_ODMA_CFG_ETM_DIS_PTR_PROG_FULL_CFG_Ar = 1789, + NPPU_ODMA_CFG_ETM_DIS_PTR_PROG_FULL_CFG_Nr = 1790, + NPPU_ODMA_CFG_FTM_DIS_PTR_PROG_FULL_CFG_Ar = 1791, + NPPU_ODMA_CFG_FTM_DIS_PTR_PROG_FULL_CFG_Nr = 1792, + NPPU_ODMA_CFG_TM_DIS_FIFO_PROG_FULL_CFG_Ar = 1793, + NPPU_ODMA_CFG_TM_DIS_FIFO_PROG_FULL_CFG_Nr = 1794, + NPPU_ODMA_CFG_ERR_PROG_FULL_CFG_Ar = 1795, + NPPU_ODMA_CFG_ERR_PROG_FULL_CFG_Nr = 1796, + NPPU_ODMA_CFG_TDMUC_PROG_FULL_CFG_Ar = 1797, + NPPU_ODMA_CFG_TDMUC_PROG_FULL_CFG_Nr = 1798, + NPPU_ODMA_CFG_TDMMC_GROUPID_PROG_FULL_CFG_Ar = 1799, + NPPU_ODMA_CFG_TDMMC_GROUPID_PROG_FULL_CFG_Nr = 1800, + NPPU_ODMA_CFG_TDMMC_NO_BITMAP_PROG_FULL_CFG_Ar = 1801, + NPPU_ODMA_CFG_TDMMC_NO_BITMAP_PROG_FULL_CFG_Nr = 1802, + NPPU_ODMA_CFG_TDMMC_PROG_FULL_CFG_Ar = 1803, + NPPU_ODMA_CFG_TDMMC_PROG_FULL_CFG_Nr = 1804, + NPPU_ODMA_CFG_DESC_PROG_FULL_CFG_Ar = 1805, + NPPU_ODMA_CFG_DESC_PROG_FULL_CFG_Nr = 1806, + NPPU_ODMA_CFG_DLY_PROG_FULL_CFG_Ar = 1807, + NPPU_ODMA_CFG_DLY_PROG_FULL_CFG_Nr = 1808, + NPPU_ODMA_CFG_RSP_PROG_FULL_CFG_Ar = 1809, + NPPU_ODMA_CFG_RSP_PROG_FULL_CFG_Nr = 1810, + NPPU_ODMA_CFG_NOR_PROG_FULL_CFG_Ar = 1811, + NPPU_ODMA_CFG_NOR_PROG_FULL_CFG_Nr = 1812, + NPPU_ODMA_CFG_ETM_NOR_PROG_FULL_CFG_Ar = 1813, + NPPU_ODMA_CFG_ETM_NOR_PROG_FULL_CFG_Nr = 1814, + NPPU_ODMA_CFG_FTM_NOR_PROG_FULL_CFG_Ar = 1815, + NPPU_ODMA_CFG_FTM_NOR_PROG_FULL_CFG_Nr = 1816, + NPPU_ODMA_CFG_ETM_PROG_FULL_CFG_Ar = 1817, + NPPU_ODMA_CFG_ETM_PROG_FULL_CFG_Nr = 1818, + NPPU_ODMA_CFG_FTM_PROG_FULL_CFG_Ar = 1819, + NPPU_ODMA_CFG_FTM_PROG_FULL_CFG_Nr = 1820, + NPPU_ODMA_CFG_ETM_NRDCNT_PROG_FULL_CFG_Ar = 1821, + NPPU_ODMA_CFG_ETM_NRDCNT_PROG_FULL_CFG_Nr = 1822, + NPPU_ODMA_CFG_FTM_NRDCNT_PROG_FULL_CFG_Ar = 1823, + NPPU_ODMA_CFG_FTM_NRDCNT_PROG_FULL_CFG_Nr = 1824, + NPPU_ODMA_CFG_PP_PROG_FULL_CFG_Ar = 1825, + NPPU_ODMA_CFG_PP_PROG_FULL_CFG_Nr = 1826, + NPPU_ODMA_CFG_TM_WEIGHTr = 1827, + NPPU_ODMA_CFG_PP_WEIGHTr = 1828, + NPPU_ODMA_CFG_IFBCMD_PROG_FULL_CFG_Ar = 1829, + NPPU_ODMA_CFG_IFBCMD_PROG_FULL_CFG_Nr = 1830, + NPPU_ODMA_CFG_MCCNT_PROG_FULL_CFG_Ar = 1831, + NPPU_ODMA_CFG_MCCNT_PROG_FULL_CFG_Nr = 1832, + NPPU_ODMA_CFG_INT_OR_PONr = 1833, + NPPU_ODMA_CFG_QUEMNG_CNT_IN_ERR_CNTr = 1834, + NPPU_ODMA_CFG_LIF0_PORT_EOP_CNTr = 1835, + NPPU_ODMA_CFG_LIF1_PORT_EOP_CNTr = 1836, + NPPU_ODMA_CFG_LIFC_PORT0_EOP_CNTr = 1837, + NPPU_ODMA_CFG_LIFC_PORT1_EOP_CNTr = 1838, + NPPU_ODMA_CFG_FPTR_FIFO_PROG_EPT_CFG_Nr = 1839, + NPPU_ODMA_CFG_ISU_FIFO_PROG_FULL_CFG_Ar = 1840, + NPPU_ODMA_CFG_ISU_FIFO_PROG_FULL_CFG_Nr = 1841, + NPPU_OAM_CFG_IND_ACCESS_DONEr = 1842, + NPPU_OAM_CFG_IND_ACCESS_COMMANDr = 1843, + NPPU_OAM_CFG_IND_DAT0r = 1844, + NPPU_OAM_CFG_IND_DAT1r = 1845, + NPPU_OAM_CFG_IND_DAT2r = 1846, + NPPU_OAM_CFG_IND_DAT3r = 1847, + NPPU_OAM_CFG_OAM_TX_MAIN_ENr = 1848, + NPPU_OAM_CFG_TX_TOTAL_NUMr = 1849, + NPPU_OAM_CFG_OAM_CHK_MAIN_ENr = 1850, + NPPU_OAM_CFG_CHK_TOTAL_NUM0r = 1851, + NPPU_OAM_CFG_MA_CHK_MAIN_ENr = 1852, + NPPU_OAM_CFG_CHK_TOTAL_NUM1r = 1853, + NPPU_OAM_CFG_TX_STAT_ENr = 1854, + NPPU_OAM_CFG_REC_STAT_ENr = 1855, + NPPU_OAM_CFG_STAT_OAM_RDY_MASKr = 1856, + NPPU_OAM_CFG_SESSION_GRADING0r = 1857, + NPPU_OAM_CFG_SESSION_GRADING1r = 1858, + NPPU_OAM_CFG_SESSION_GRADING2r = 1859, + NPPU_OAM_CFG_SESSION_GRADING3r = 1860, + NPPU_OAM_CFG_BFD_CHK_HADDRr = 1861, + NPPU_OAM_CFG_ETHCCM_CHK_HADDRr = 1862, + NPPU_OAM_CFG_TPBFD_CHK_HADDRr = 1863, + NPPU_OAM_CFG_TPOAM_CCM_CHK_HADDRr = 1864, + NPPU_OAM_CFG_BFD_TX_HADDRr = 1865, + NPPU_OAM_CFG_ETHCCM_TX_HADDRr = 1866, + NPPU_OAM_CFG_TPBFD_TX_HADDRr = 1867, + NPPU_OAM_CFG_TPOAM_CCM_TX_HADDRr = 1868, + NPPU_OAM_CFG_ETHCCM_MA_CHK_HADDRr = 1869, + NPPU_OAM_CFG_TPCCM_MA_CHK_HADDRr = 1870, + NPPU_OAM_CFG_GROUPNUM_RAM_CLRr = 1871, + NPPU_OAM_CFG_INDEX_RAM0_CLRr = 1872, + NPPU_OAM_CFG_INDEX_RAM1_CLRr = 1873, + NPPU_OAM_CFG_RMEP_RAM_CLRr = 1874, + NPPU_OAM_CFG_MA_RAM_CLRr = 1875, + NPPU_OAM_CFG_RAM_INIT_DONEr = 1876, + NPPU_OAM_CFG_REC_BFD_DEBUG_ENr = 1877, + NPPU_OAM_CFG_OAM_SESSION_INTr = 1878, + NPPU_OAM_CFG_PON_INTr = 1879, + NPPU_OAM_CFG_OAM_INT_CLRr = 1880, + NPPU_OAM_CFG_TYPE_INT_CLR0r = 1881, + NPPU_OAM_CFG_TYPE_INT_CLR1r = 1882, + NPPU_OAM_CFG_INTERRUPT_MASKr = 1883, + NPPU_OAM_CFG_INT0_INDEXr = 1884, + NPPU_OAM_CFG_INT1_INDEXr = 1885, + NPPU_OAM_CFG_INT0_INDEX_REGIONr = 1886, + NPPU_OAM_CFG_INT1_INDEX_REGIONr = 1887, + NPPU_OAM_CFG_BDIINFO_FWFT_FIFO_THr = 1888, + NPPU_OAM_CFG_RECSEC_FWFT_FIFO_THr = 1889, + NPPU_OAM_CFG_TIMING_CHK_INFO0_FWFT_FIFO_THr = 1890, + NPPU_OAM_CFG_RECMA_FWFT_FIFO_THr = 1891, + NPPU_OAM_CFG_TIMING_CHK_INFO1_FWFT_FIFO_THr = 1892, + NPPU_OAM_CFG_OAM_TXINST_FIFO_THr = 1893, + NPPU_OAM_CFG_OAM_RDINFO_FWFT_FIFO_THr = 1894, + NPPU_OAM_CFG_LM_CNT_FWFT_FIFO_THr = 1895, + NPPU_OAM_CFG_OAM_PKT_FIFO_THr = 1896, + NPPU_OAM_CFG_RECLM_STAT_FIFO_THr = 1897, + NPPU_OAM_CFG_TXLM_STAT_FIFO_THr = 1898, + NPPU_OAM_CFG_OAM_CHK_FWFT_FIFO_THr = 1899, + NPPU_OAM_CFG_TXOAM_STAT_FIFO_THr = 1900, + NPPU_OAM_CFG_RECOAM_STAT_FIFO_THr = 1901, + NPPU_OAM_CFG_TXPKT_DATA_FWFT_FIFO_THr = 1902, + NPPU_OAM_CFG_TSTPKT_FWFT_FIFO_THr = 1903, + NPPU_OAM_CFG_TST_TXINST_FWFT_FIFO_THr = 1904, + NPPU_OAM_CFG_TSTRX_MAIN_ENr = 1905, + NPPU_OAM_CFG_TSTTX_CFG_PARA_TBL2r = 1906, + NPPU_OAM_CFG_TSTTX_CFG_PARA_TBL1r = 1907, + NPPU_OAM_CFG_TSTTX_CFG_PARA_TBL0r = 1908, + NPPU_OAM_CFG_TSTRX_CFG_PARAr = 1909, + NPPU_OAM_CFG_FIFO_STATUS_INT_EN_0r = 1910, + NPPU_OAM_CFG_FIFO_STATUS_INT_EN_1r = 1911, + NPPU_OAM_CFG_FIFO_STATUS_INT_MASK_0r = 1912, + NPPU_OAM_CFG_FIFO_STATUS_INT_MASK_1r = 1913, + NPPU_OAM_CFG_FIFO_STATUS_INT_STATUSr = 1914, + NPPU_OAM_CFG_MAIN_FREQUENCYr = 1915, + NPPU_OAM_CFG_OAM_CFG_TYPEr = 1916, + NPPU_OAM_CFG_FST_SWCH_ETH_HEAD0r = 1917, + NPPU_OAM_CFG_FST_SWCH_ETH_HEAD1r = 1918, + NPPU_OAM_CFG_FST_SWCH_ETH_HEAD2r = 1919, + NPPU_OAM_CFG_FST_SWCH_ETH_HEAD3r = 1920, + NPPU_OAM_CFG_OAM_FS_TXINST_FIFO_THr = 1921, + NPPU_OAM_CFG_OAM_MA_FS_TXINST_FIFO_THr = 1922, + NPPU_OAM_CFG_PON_INT_RAM_CLRr = 1923, + NPPU_OAM_CFG_PON_P_INT_INDEXr = 1924, + NPPU_OAM_CFG_PON_PROTECT_PKT_FIFO_THr = 1925, + NPPU_OAM_CFG_PON_LASER_OFF_ENr = 1926, + NPPU_OAM_CFG_PON_PRTCT_PKT_TX_ENr = 1927, + NPPU_OAM_CFG_CFG_PON_MASTERr = 1928, + NPPU_OAM_CFG_LEVEL_MODEr = 1929, + NPPU_OAM_CFG_INTERRUPT_ENr = 1930, + NPPU_OAM_CFG_PON_LASER_ON_ENr = 1931, + NPPU_OAM_CFG_TI_PON_SDr = 1932, + NPPU_OAM_CFG_TI_PON_LOSr = 1933, + NPPU_OAM_CFG_IND_DAT4r = 1934, + NPPU_OAM_CFG_IND_DAT5r = 1935, + NPPU_OAM_CFG_IND_DAT6r = 1936, + NPPU_OAM_CFG_IND_DAT7r = 1937, + NPPU_OAM_CFG_IND_DAT8r = 1938, + NPPU_OAM_CFG_IND_DAT9r = 1939, + NPPU_OAM_CFG_IND_DAT10r = 1940, + NPPU_OAM_CFG_IND_DAT11r = 1941, + NPPU_OAM_CFG_IND_DAT12r = 1942, + NPPU_OAM_CFG_IND_DAT13r = 1943, + NPPU_OAM_CFG_IND_DAT14r = 1944, + NPPU_OAM_CFG_IND_DAT15r = 1945, + NPPU_OAM_CFG_OAM_2544_PKT_FIFO_THr = 1946, + NPPU_OAM_CFG_TXINFO_RAM_CLRr = 1947, + NPPU_OAM_CFG_TXINFO_RAM_INIT_DONEr = 1948, + NPPU_OAM_CFG_FIFO_STATUS_INT_STATUS40r = 1949, + NPPU_OAM_CFG_FIFO_STATUS_INT_STATUS41r = 1950, + NPPU_OAM_CFG_OAM_2544_FUN_ENr = 1951, + NPPU_OAM_CFG_OAM_2544_STAT_CLRr = 1952, + NPPU_OAM_CFG_TXDIS_DEFAULTr = 1953, + NPPU_OAM_CFG_TXDIS_DEFAULT_ENr = 1954, + NPPU_OAM_CFG_TPBFD_FIRSTCHK_THr = 1955, + NPPU_OAM_CFG_ETHCCM_FIRSTCHK_THr = 1956, + NPPU_OAM_CFG_TPCCM_FIRSTCHK_THr = 1957, + NPPU_OAM_STAT_TXSTAT_REQ_CNTr = 1958, + NPPU_OAM_STAT_CHKSTAT_REQ_CNTr = 1959, + NPPU_OAM_STAT_STAT_OAM_FC_CNTr = 1960, + NPPU_OAM_STAT_BFDSEQ_REQ_CNTr = 1961, + NPPU_OAM_STAT_LMCNT_REQ_CNTr = 1962, + NPPU_OAM_STAT_STAT_OAM_LM_RSP_CNTr = 1963, + NPPU_OAM_STAT_STAT_OAM_LM_FC_CNTr = 1964, + NPPU_OAM_STAT_SE_REQ_CNTr = 1965, + NPPU_OAM_STAT_SE_RSP_CNTr = 1966, + NPPU_OAM_STAT_SE_OAM_FC_CNTr = 1967, + NPPU_OAM_STAT_OAM_SE_FC_CNTr = 1968, + NPPU_OAM_STAT_OAM_PKTRX_SOP_CNTr = 1969, + NPPU_OAM_STAT_OAM_PKTRX_EOP_CNTr = 1970, + NPPU_OAM_STAT_PKTRX_OAM_FC_CNTr = 1971, + NPPU_OAM_STAT_PKTRX_OAM_TST_FC_CNTr = 1972, + NPPU_OAM_STAT_ODMA_OAM_SOP_CNTr = 1973, + NPPU_OAM_STAT_ODMA_OAM_EOP_CNTr = 1974, + NPPU_OAM_STAT_OAM_ODMA_FC_CNTr = 1975, + NPPU_OAM_STAT_REC_MA_PKT_ILLEGAL_CNTr = 1976, + NPPU_OAM_STAT_REC_RMEP_PKT_ILLEGAL_CNTr = 1977, + NPPU_OAM_STAT_REC_ETH_AIS_PKT_CNTr = 1978, + NPPU_OAM_STAT_REC_TP_AIS_PKT_CNTr = 1979, + NPPU_OAM_STAT_REC_TP_CSF_PKT_CNTr = 1980, + NPPU_OAM_STAT_REC_ETH_LEVEL_DEFECT_CNTr = 1981, + NPPU_OAM_STAT_REC_ETH_MEGID_DEFECT_CNTr = 1982, + NPPU_OAM_STAT_REC_ETH_MEPID_DEFECT_CNTr = 1983, + NPPU_OAM_STAT_REC_ETH_INTERVAL_DEFECT_CNTr = 1984, + NPPU_OAM_STAT_REC_SESS_UNENABLE_CNTr = 1985, + NPPU_OAM_STAT_OAM_2544_RD_PKT_CNTr = 1986, + NPPU_OAM_STAT_DEBUG_CNT_CLRr = 1987, + NPPU_OAM_STAT_OAM_PKTRX_CATCH_DATAr = 1988, + NPPU_OAM_STAT_ODMA_OAM_CATCH_DATAr = 1989, + NPPU_OAM_STAT_TST_SESSION_TX_CNTr = 1990, + NPPU_OAM_STAT_TST_SESSION_RX_CNTr = 1991, + NPPU_OAM_STAT_TSTRX_LOST_CNTr = 1992, + NPPU_OAM_STAT_BFDSEQ_WR_CNTr = 1993, + NPPU_OAM_STAT_BFDTIME_WR_CNTr = 1994, + NPPU_OAM_STAT_LMCNT_WR_CNTr = 1995, + NPPU_OAM_STAT_OAM_FS_PKT_CNTr = 1996, + NPPU_OAM_STAT_OAM_MA_FS_PKT_CNTr = 1997, + NPPU_OAM_STAT_REC_TP_LEVEL_DEFECT_CNTr = 1998, + NPPU_OAM_STAT_REC_TP_MEGID_DEFECT_CNTr = 1999, + NPPU_OAM_STAT_REC_TP_MEPID_DEFECT_CNTr = 2000, + NPPU_OAM_STAT_REC_TP_INTERVAL_DEFECT_CNTr = 2001, + NPPU_OAM_STAT_RD_REG_CLEAR_MODEr = 2002, + NPPU_OAM_STAT_RD_DATA_REG_CLEAR_MODEr = 2003, + NPPU_OAM_CFG_INDIR_OAM_INT_STATUS_RAM_0r = 2004, + NPPU_OAM_CFG_INDIR_OAM_INT_STATUS_RAM1r = 2005, + NPPU_OAM_CFG_INDIR_TST_PKT_TX_PARA_RAMr = 2006, + NPPU_OAM_CFG_INDIR_GROUPNUMRAMr = 2007, + NPPU_OAM_CFG_INDIR_OAM_TX_TBL_RAMr = 2008, + NPPU_OAM_CFG_INDIR_OAM_CHK_TBL_RAMr = 2009, + NPPU_OAM_CFG_INDIR_OAM_MA_CHK_TBL_RAMr = 2010, + NPPU_OAM_CFG_INDIR_OAM_2544_TX_RAMr = 2011, + PPU_PPU_INTERRUPT_EN_Rr = 2012, + PPU_PPU_MEC_HOST_INTERRUPTr = 2013, + PPU_PPU_DBG_RTL_DATEr = 2014, + PPU_PPU_DUP_START_NUM_CFGr = 2015, + PPU_PPU_DEBUG_DATA_WRITE_COMPLETEr = 2016, + PPU_PPU_UC_MC_WRR_CFGr = 2017, + PPU_PPU_DEBUG_PKT_SEND_ENr = 2018, + PPU_PPU_DUP_TBL_IND_ACCESS_DONEr = 2019, + PPU_PPU_ISU_PPU_DEMUX_FIFO_INTERRUPT_MASKr = 2020, + PPU_PPU_PPU_MULTICAST_FIFO_INTERRUPT_MASKr = 2021, + PPU_PPU_PPU_IN_SCHEDULE_FIFO_INTERRUPT_MASKr = 2022, + PPU_PPU_PPU_MF_OUT_FIFO_INTERRUPT_MASKr = 2023, + PPU_PPU_PBU_MCODE_PF_REQ_SCHEDULE_FIFO_INTERRUPT_MASKr = 2024, + PPU_PPU_PBU_MCODE_PF_RSP_SCHEDULE_FIFO_INTERRUPT_MASKr = 2025, + PPU_PPU_PPU_MCCNT_FIFO_INTERRUPT_MASKr = 2026, + PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_MASK_Lr = 2027, + PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_MASK_Mr = 2028, + PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_MASK_Hr = 2029, + PPU_PPU_PPU_RAM_CHECK_ERR_MASKr = 2030, + PPU_PPU_INSTRMEM_FIFO_INTERRUPT_MASKr = 2031, + PPU_PPU_ISU_PPU_DEMUX_FIFO_INTERRUPT_STAr = 2032, + PPU_PPU_PPU_MULTICAST_FIFO_INTERRUPT_STAr = 2033, + PPU_PPU_PPU_IN_SCHEDULE_FIFO_INTERRUPT_STAr = 2034, + PPU_PPU_PPU_MF_OUT_FIFO_INTERRUPT_STAr = 2035, + PPU_PPU_PBU_MCODE_PF_REQ_SCHEDULE_FIFO_INTERRUPT_STAr = 2036, + PPU_PPU_PBU_MCODE_PF_RSP_SCHEDULE_FIFO_INTERRUPT_STAr = 2037, + PPU_PPU_PPU_MCCNT_FIFO_INTERRUPT_STAr = 2038, + PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_STA_Lr = 2039, + PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_STA_Mr = 2040, + PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_STA_Hr = 2041, + PPU_PPU_INSTRMEM_FIFO_INTERRUPT_STAr = 2042, + PPU_PPU_PPU_RAM_CHECK_ECC_ERR_FLAG_1r = 2043, + PPU_PPU_ISU_PPU_DEMUX_FIFO_INTERRUPT_FLAGr = 2044, + PPU_PPU_PPU_MULTICAST_FIFO_INTERRUPT_FLAGr = 2045, + PPU_PPU_PPU_IN_SCHEDULE_FIFO_INTERRUPT_FLAGr = 2046, + PPU_PPU_PPU_MF_OUT_FIFO_INTERRUPT_FLAGr = 2047, + PPU_PPU_PBU_MCODE_PF_REQ_SCHEDULE_FIFO_INTERRUPT_FLAGr = 2048, + PPU_PPU_PBU_MCODE_PF_RSP_SCHEDULE_FIFO_INTERRUPT_FLAGr = 2049, + PPU_PPU_PPU_MCCNT_FIFO_INTERRUPT_FLAGr = 2050, + PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_FLAG_Lr = 2051, + PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_FLAG_Mr = 2052, + PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_FLAG_Hr = 2053, + PPU_PPU_INSTRMEM_FIFO_INTERRUPT_FLAGr = 2054, + PPU_PPU_INSTRMEM_RAM_INT_OUTr = 2055, + PPU_PPU_INSTRMEM_RAM_INT_MASKr = 2056, + PPU_PPU_INSTRMEM_RAM_INT_STATr = 2057, + PPU_PPU_INSTRMEM_RAM_INT_FLAGr = 2058, + PPU_PPU_PPU_COUNT_CFGr = 2059, + PPU_PPU_PPU_STATICS_CFGr = 2060, + PPU_PPU_PPU_STATICS_WB_CFGr = 2061, + PPU_PPU_WR_TABLE_SELF_RSP_EN_CFGr = 2062, + PPU_PPU_PPU_RANDOM_ARBITER_8TO1_CFGr = 2063, + PPU_PPU_PPU_REORDER_BYPASS_FLOW_NUM_CFGr = 2064, + PPU_PPU_COS_METER_CFG_Hr = 2065, + PPU_PPU_COS_METER_CFG_Lr = 2066, + PPU_PPU_INSTRMEM_RDYr = 2067, + PPU_PPU_INSTRMEM_ADDRr = 2068, + PPU_PPU_INSTRMEM_IND_ACCESS_DONEr = 2069, + PPU_PPU_INSTRMEM_INSTR0_DATA_Lr = 2070, + PPU_PPU_INSTRMEM_INSTR0_DATA_Hr = 2071, + PPU_PPU_INSTRMEM_INSTR1_DATA_Lr = 2072, + PPU_PPU_INSTRMEM_INSTR1_DATA_Hr = 2073, + PPU_PPU_INSTRMEM_INSTR2_DATA_Lr = 2074, + PPU_PPU_INSTRMEM_INSTR2_DATA_Hr = 2075, + PPU_PPU_INSTRMEM_INSTR3_DATA_Lr = 2076, + PPU_PPU_INSTRMEM_INSTR3_DATA_Hr = 2077, + PPU_PPU_INSTRMEM_READ_INSTR0_DATA_Lr = 2078, + PPU_PPU_INSTRMEM_READ_INSTR0_DATA_Hr = 2079, + PPU_PPU_INSTRMEM_READ_INSTR1_DATA_Lr = 2080, + PPU_PPU_INSTRMEM_READ_INSTR1_DATA_Hr = 2081, + PPU_PPU_INSTRMEM_READ_INSTR2_DATA_Lr = 2082, + PPU_PPU_INSTRMEM_READ_INSTR2_DATA_Hr = 2083, + PPU_PPU_INSTRMEM_READ_INSTR3_DATA_Lr = 2084, + PPU_PPU_INSTRMEM_READ_INSTR3_DATA_Hr = 2085, + PPU_PPU_SE_PPU_MC_SRH_FC_CNT_Hr = 2086, + PPU_PPU_SE_PPU_MC_SRH_FC_CNT_Lr = 2087, + PPU_PPU_PPU_SE_MC_SRH_FC_CNT_Hr = 2088, + PPU_PPU_PPU_SE_MC_SRH_FC_CNT_Lr = 2089, + PPU_PPU_PPU_SE_MC_SRH_VLD_CNT_Hr = 2090, + PPU_PPU_PPU_SE_MC_SRH_VLD_CNT_Lr = 2091, + PPU_PPU_SE_PPU_MC_SRH_VLD_CNT_Hr = 2092, + PPU_PPU_SE_PPU_MC_SRH_VLD_CNT_Lr = 2093, + PPU_PPU_PBU_PPU_LOGIC_PF_FC_CNT_Hr = 2094, + PPU_PPU_PBU_PPU_LOGIC_PF_FC_CNT_Lr = 2095, + PPU_PPU_PPU_PBU_LOGIC_RSP_FC_CNT_Hr = 2096, + PPU_PPU_PPU_PBU_LOGIC_RSP_FC_CNT_Lr = 2097, + PPU_PPU_PPU_PBU_LOGIC_PF_REQ_VLD_CNT_Hr = 2098, + PPU_PPU_PPU_PBU_LOGIC_PF_REQ_VLD_CNT_Lr = 2099, + PPU_PPU_PBU_PPU_LOGIC_PF_RSP_VLD_CNT_Hr = 2100, + PPU_PPU_PBU_PPU_LOGIC_PF_RSP_VLD_CNT_Lr = 2101, + PPU_PPU_PBU_PPU_IFB_RD_FC_CNT_Hr = 2102, + PPU_PPU_PBU_PPU_IFB_RD_FC_CNT_Lr = 2103, + PPU_PPU_PBU_PPU_WB_FC_CNT_Hr = 2104, + PPU_PPU_PBU_PPU_WB_FC_CNT_Lr = 2105, + PPU_PPU_PPU_PBU_MCODE_PF_REQ_VLD_CNT_Hr = 2106, + PPU_PPU_PPU_PBU_MCODE_PF_REQ_VLD_CNT_Lr = 2107, + PPU_PPU_PBU_PPU_MCODE_PF_RSP_VLD_CNT_Hr = 2108, + PPU_PPU_PBU_PPU_MCODE_PF_RSP_VLD_CNT_Lr = 2109, + PPU_PPU_ODMA_PPU_PARA_FC_CNT_Hr = 2110, + PPU_PPU_ODMA_PPU_PARA_FC_CNT_Lr = 2111, + PPU_PPU_ODMA_PPU_MCCNT_WR_FC_CNT_Hr = 2112, + PPU_PPU_ODMA_PPU_MCCNT_WR_FC_CNT_Lr = 2113, + PPU_PPU_PPU_ODMA_MCCNT_WR_VLD_CNT_Hr = 2114, + PPU_PPU_PPU_ODMA_MCCNT_WR_VLD_CNT_Lr = 2115, + PPU_PPU_ODMA_PPU_MCCNT_RSP_VLD_CNT_Hr = 2116, + PPU_PPU_ODMA_PPU_MCCNT_RSP_VLD_CNT_Lr = 2117, + PPU_PPU_PPU_PKTRX_UC_FC_CNT_Hr = 2118, + PPU_PPU_PPU_PKTRX_UC_FC_CNT_Lr = 2119, + PPU_PPU_PPU_PKTRX_MC_FC_CNT_Hr = 2120, + PPU_PPU_PPU_PKTRX_MC_FC_CNT_Lr = 2121, + PPU_PPU_PKTRX_PPU_DESC_VLD_CNT_Hr = 2122, + PPU_PPU_PKTRX_PPU_DESC_VLD_CNT_Lr = 2123, + PPU_PPU_PPU_PBU_IFB_REQ_VLD_CNT_Hr = 2124, + PPU_PPU_PPU_PBU_IFB_REQ_VLD_CNT_Lr = 2125, + PPU_PPU_PBU_PPU_IFB_RSP_VLD_CNT_Hr = 2126, + PPU_PPU_PBU_PPU_IFB_RSP_VLD_CNT_Lr = 2127, + PPU_PPU_PPU_PBU_WB_VLD_CNT_Hr = 2128, + PPU_PPU_PPU_PBU_WB_VLD_CNT_Lr = 2129, + PPU_PPU_PBU_PPU_REORDER_PARA_VLD_CNT_Hr = 2130, + PPU_PPU_PBU_PPU_REORDER_PARA_VLD_CNT_Lr = 2131, + PPU_PPU_PPU_ODMA_PARA_VLD_CNT_Hr = 2132, + PPU_PPU_PPU_ODMA_PARA_VLD_CNT_Lr = 2133, + PPU_PPU_STATICS_ISU_PPU_MC_VLD_CNT_Hr = 2134, + PPU_PPU_STATICS_ISU_PPU_MC_VLD_CNT_Lr = 2135, + PPU_PPU_STATICS_ISU_PPU_MC_LOOP_VLD_CNT_Hr = 2136, + PPU_PPU_STATICS_ISU_PPU_MC_LOOP_VLD_CNT_Lr = 2137, + PPU_PPU_STATICS_ISU_PPU_UC_VLD_CNT_Hr = 2138, + PPU_PPU_STATICS_ISU_PPU_UC_VLD_CNT_Lr = 2139, + PPU_PPU_STATICS_ISU_PPU_UC_BUFNUMIS0_VLD_CNT_Hr = 2140, + PPU_PPU_STATICS_ISU_PPU_UC_BUFNUMIS0_VLD_CNT_Lr = 2141, + PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_VLD_CNT_Hr = 2142, + PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_VLD_CNT_Lr = 2143, + PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_BUFNUMIS0_VLD_CNT_Hr = 2144, + PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_BUFNUMIS0_VLD_CNT_Lr = 2145, + PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_SRCPORTIS0_VLD_CNT_Hr = 2146, + PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_SRCPORTIS0_VLD_CNT_Lr = 2147, + PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_SRCPORTIS1_VLD_CNT_Hr = 2148, + PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_SRCPORTIS1_VLD_CNT_Lr = 2149, + PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_VLD_CNT_Hr = 2150, + PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_VLD_CNT_Lr = 2151, + PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_BUFNUMIS0_VLD_CNT_Hr = 2152, + PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_BUFNUMIS0_VLD_CNT_Lr = 2153, + PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_SRCPORTIS0_VLD_CNT_Hr = 2154, + PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_SRCPORTIS0_VLD_CNT_Lr = 2155, + PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_SRCPORTIS1_VLD_CNT_Hr = 2156, + PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_SRCPORTIS1_VLD_CNT_Lr = 2157, + PPU_PPU_STATICS_PPU_WB_VLD_CNT_Hr = 2158, + PPU_PPU_STATICS_PPU_WB_VLD_CNT_Lr = 2159, + PPU_PPU_STATICS_PPU_WB_BUFNUMIS0_VLD_CNT_Hr = 2160, + PPU_PPU_STATICS_PPU_WB_BUFNUMIS0_VLD_CNT_Lr = 2161, + PPU_PPU_STATICS_PPU_WB_SRCPORTIS0_VLD_CNT_Hr = 2162, + PPU_PPU_STATICS_PPU_WB_SRCPORTIS0_VLD_CNT_Lr = 2163, + PPU_PPU_STATICS_PPU_WB_SRCPORTIS1_VLD_CNT_Hr = 2164, + PPU_PPU_STATICS_PPU_WB_SRCPORTIS1_VLD_CNT_Lr = 2165, + PPU_PPU_STATICS_PPU_WB_HALT_SEND_TYPE_VLD_CNT_Hr = 2166, + PPU_PPU_STATICS_PPU_WB_HALT_SEND_TYPE_VLD_CNT_Lr = 2167, + PPU_PPU_STATICS_PPU_WB_MF_TYPE_VLD_CNT_Hr = 2168, + PPU_PPU_STATICS_PPU_WB_MF_TYPE_VLD_CNT_Lr = 2169, + PPU_PPU_STATICS_PPU_WB_HALT_CONTINUE_END_VLD_CNT_Hr = 2170, + PPU_PPU_STATICS_PPU_WB_HALT_CONTINUE_END_VLD_CNT_Lr = 2171, + PPU_PPU_STATICS_PPU_WB_DUP_FLAG_VLD_CNT_Hr = 2172, + PPU_PPU_STATICS_PPU_WB_DUP_FLAG_VLD_CNT_Lr = 2173, + PPU_PPU_STATICS_PPU_WB_LAST_FLAG_VLD_CNT_Hr = 2174, + PPU_PPU_STATICS_PPU_WB_LAST_FLAG_VLD_CNT_Lr = 2175, + PPU_PPU_STATICS_PPU_WB_DIS_FLAG_VLD_CNT_Hr = 2176, + PPU_PPU_STATICS_PPU_WB_DIS_FLAG_VLD_CNT_Lr = 2177, + PPU_PPU_STATICS_PBU_PPU_REORDER_HALT_SEND_TYPE_VLD_CNT_Hr = 2178, + PPU_PPU_STATICS_PBU_PPU_REORDER_HALT_SEND_TYPE_VLD_CNT_Lr = 2179, + PPU_PPU_STATICS_PBU_PPU_REORDER_MF_TYPE_VLD_CNT_Hr = 2180, + PPU_PPU_STATICS_PBU_PPU_REORDER_MF_TYPE_VLD_CNT_Lr = 2181, + PPU_PPU_STATICS_PBU_PPU_REORDER_HALT_CONTINUE_END_VLD_CNT_Hr = 2182, + PPU_PPU_STATICS_PBU_PPU_REORDER_HALT_CONTINUE_END_VLD_CNT_Lr = 2183, + PPU_PPU_CAR_GREEN_PKT_VLD_CNT_Hr = 2184, + PPU_PPU_CAR_GREEN_PKT_VLD_CNT_Lr = 2185, + PPU_PPU_CAR_YELLOW_PKT_VLD_CNT_Hr = 2186, + PPU_PPU_CAR_YELLOW_PKT_VLD_CNT_Lr = 2187, + PPU_PPU_CAR_RED_PKT_VLD_CNT_Hr = 2188, + PPU_PPU_CAR_RED_PKT_VLD_CNT_Lr = 2189, + PPU_PPU_CAR_DROP_PKT_VLD_CNT_Hr = 2190, + PPU_PPU_CAR_DROP_PKT_VLD_CNT_Lr = 2191, + PPU_PPU_PPU_PKTRX_MC_PTR_VLD_CNT_Hr = 2192, + PPU_PPU_PPU_PKTRX_MC_PTR_VLD_CNT_Lr = 2193, + PPU_PPU_ISU_PPU_LOOPBACK_FC_CNT_Hr = 2194, + PPU_PPU_ISU_PPU_LOOPBACK_FC_CNT_Lr = 2195, + PPU_PPU_PPU_CULSTER_PBU_MCODE_PF_REQ_PROG_FULL_ASSERT_CFGr = 2196, + PPU_PPU_PPU_CULSTER_PBU_MCODE_PF_REQ_PROG_FULL_NEGATE_CFGr = 2197, + PPU_PPU_PPU_CULSTER_PBU_MCODE_PF_REQ_PROG_EMPTY_ASSERT_CFGr = 2198, + PPU_PPU_PPU_CULSTER_PBU_MCODE_PF_REQ_PROG_EMPTY_NEGATE_CFGr = 2199, + PPU_PPU_PPU_PBU_MCODE_PF_RSP_PROG_FULL_ASSERT_CFGr = 2200, + PPU_PPU_PPU_PBU_MCODE_PF_RSP_PROG_FULL_NEGATE_CFGr = 2201, + PPU_PPU_PPU_PBU_MCODE_PF_RSP_PROG_EMPTY_ASSERT_CFGr = 2202, + PPU_PPU_PPU_PBU_MCODE_PF_RSP_PROG_EMPTY_NEGATE_CFGr = 2203, + PPU_PPU_MCCNT_FIFO_PROG_FULL_ASSERT_CFGr = 2204, + PPU_PPU_MCCNT_FIFO_PROG_FULL_NEGATE_CFGr = 2205, + PPU_PPU_MCCNT_FIFO_PROG_EMPTY_ASSERT_CFGr = 2206, + PPU_PPU_MCCNT_FIFO_PROG_EMPTY_NEGATE_CFGr = 2207, + PPU_PPU_UC_MF_FIFO_PROG_FULL_ASSERT_CFGr = 2208, + PPU_PPU_UC_MF_FIFO_PROG_FULL_NEGATE_CFGr = 2209, + PPU_PPU_UC_MF_FIFO_PROG_EMPTY_ASSERT_CFGr = 2210, + PPU_PPU_UC_MF_FIFO_PROG_EMPTY_NEGATE_CFGr = 2211, + PPU_PPU_MC_MF_FIFO_PROG_FULL_ASSERT_CFGr = 2212, + PPU_PPU_MC_MF_FIFO_PROG_FULL_NEGATE_CFGr = 2213, + PPU_PPU_MC_MF_FIFO_PROG_EMPTY_ASSERT_CFGr = 2214, + PPU_PPU_MC_MF_FIFO_PROG_EMPTY_NEGATE_CFGr = 2215, + PPU_PPU_ISU_MF_FIFO_PROG_FULL_ASSERT_CFGr = 2216, + PPU_PPU_ISU_MF_FIFO_PROG_FULL_NEGATE_CFGr = 2217, + PPU_PPU_ISU_MF_FIFO_PROG_EMPTY_ASSERT_CFGr = 2218, + PPU_PPU_ISU_MF_FIFO_PROG_EMPTY_NEGATE_CFGr = 2219, + PPU_PPU_ISU_FWFT_MF_FIFO_PROG_EMPTY_ASSERT_CFGr = 2220, + PPU_PPU_ISU_FWFT_MF_FIFO_PROG_EMPTY_NEGATE_CFGr = 2221, + PPU_PPU_ISU_MC_PARA_MF_FIFO_PROG_FULL_ASSERT_CFGr = 2222, + PPU_PPU_ISU_MC_PARA_MF_FIFO_PROG_FULL_NEGATE_CFGr = 2223, + PPU_PPU_ISU_MC_PARA_MF_FIFO_PROG_EMPTY_ASSERT_CFGr = 2224, + PPU_PPU_ISU_MC_PARA_MF_FIFO_PROG_EMPTY_NEGATE_CFGr = 2225, + PPU_PPU_GROUP_ID_FIFO_PROG_FULL_ASSERT_CFGr = 2226, + PPU_PPU_GROUP_ID_FIFO_PROG_FULL_NEGATE_CFGr = 2227, + PPU_PPU_GROUP_ID_FIFO_PROG_EMPTY_ASSERT_CFGr = 2228, + PPU_PPU_GROUP_ID_FIFO_PROG_EMPTY_NEGATE_CFGr = 2229, + PPU_PPU_SA_PARA_FIFO_PROG_FULL_ASSERT_CFGr = 2230, + PPU_PPU_SA_PARA_FIFO_PROG_FULL_NEGATE_CFGr = 2231, + PPU_PPU_SA_PARA_FIFO_PROG_EMPTY_ASSERT_CFGr = 2232, + PPU_PPU_SA_PARA_FIFO_PROG_EMPTY_NEGATE_CFGr = 2233, + PPU_PPU_SE_MC_RSP_FIFO_PROG_FULL_ASSERT_CFGr = 2234, + PPU_PPU_SE_MC_RSP_FIFO_PROG_FULL_NEGATE_CFGr = 2235, + PPU_PPU_SE_MC_RSP_FIFO_PROG_EMPTY_ASSERT_CFGr = 2236, + PPU_PPU_SE_MC_RSP_FIFO_PROG_EMPTY_NEGATE_CFGr = 2237, + PPU_PPU_DUP_PARA_FIFO_PROG_FULL_ASSERT_CFGr = 2238, + PPU_PPU_DUP_PARA_FIFO_PROG_FULL_NEGATE_CFGr = 2239, + PPU_PPU_DUP_PARA_FIFO_PROG_EMPTY_ASSERT_CFGr = 2240, + PPU_PPU_DUP_PARA_FIFO_PROG_EMPTY_NEGATE_CFGr = 2241, + PPU_PPU_PF_RSP_FIFO_PROG_FULL_ASSERT_CFGr = 2242, + PPU_PPU_PF_RSP_FIFO_PROG_FULL_NEGATE_CFGr = 2243, + PPU_PPU_PF_RSP_FIFO_PROG_EMPTY_ASSERT_CFGr = 2244, + PPU_PPU_PF_RSP_FIFO_PROG_EMPTY_NEGATE_CFGr = 2245, + PPU_PPU_DUP_FREEPTR_FIFO_PROG_FULL_ASSERT_CFGr = 2246, + PPU_PPU_DUP_FREEPTR_FIFO_PROG_FULL_NEGATE_CFGr = 2247, + PPU_PPU_DUP_FREEPTR_FIFO_PROG_EMPTY_ASSERT_CFGr = 2248, + PPU_PPU_DUP_FREEPTR_FIFO_PROG_EMPTY_NEGATE_CFGr = 2249, + PPU_PPU_PF_REQ_FIFO_PROG_FULL_ASSERT_CFGr = 2250, + PPU_PPU_PF_REQ_FIFO_PROG_FULL_NEGATE_CFGr = 2251, + PPU_PPU_PF_REQ_FIFO_PROG_EMPTY_ASSERT_CFGr = 2252, + PPU_PPU_PF_REQ_FIFO_PROG_EMPTY_NEGATE_CFGr = 2253, + PPU_PPU_CAR_FLAG_FIFO_PROG_FULL_ASSERT_CFGr = 2254, + PPU_PPU_CAR_FLAG_FIFO_PROG_FULL_NEGATE_CFGr = 2255, + PPU_PPU_CAR_FLAG_FIFO_PROG_EMPTY_ASSERT_CFGr = 2256, + PPU_PPU_CAR_FLAG_FIFO_PROG_EMPTY_NEGATE_CFGr = 2257, + PPU_PPU_PPU_CLUSTER_MF_OUT_AFIFO_PROG_FULL_ASSERT_CFGr = 2258, + PPU_PPU_PPU_CLUSTER_MF_OUT_AFIFO_PROG_FULL_NEGATE_CFGr = 2259, + PPU_PPU_PPU_CLUSTER_MF_OUT_AFIFO_PROG_EMPTY_ASSERT_CFGr = 2260, + PPU_PPU_PPU_CLUSTER_MF_OUT_AFIFO_PROG_EMPTY_NEGATE_CFGr = 2261, + PPU_PPU_PPU_COP_KEY_FIFO_PROG_FULL_ASSERT_CFGr = 2262, + PPU_PPU_PPU_COP_KEY_FIFO_PROG_FULL_NEGATE_CFGr = 2263, + PPU_PPU_PPU_COP_KEY_FIFO_PROG_EMPTY_ASSERT_CFGr = 2264, + PPU_PPU_PPU_COP_KEY_FIFO_PROG_EMPTY_NEGATE_CFGr = 2265, + PPU_PPU_PPU_COP_RANDOM_MOD_PARA_FIFO_PROG_FULL_ASSERT_CFGr = 2266, + PPU_PPU_PPU_COP_RANDOM_MOD_PARA_FIFO_PROG_FULL_NEGATE_CFGr = 2267, + PPU_PPU_PPU_COP_RANDOM_MOD_PARA_FIFO_PROG_EMPTY_ASSERT_CFGr = 2268, + PPU_PPU_PPU_COP_RANDOM_MOD_PARA_FIFO_PROG_EMPTY_NEGATE_CFGr = 2269, + PPU_PPU_PPU_COP_RANDOM_MOD_RESULT_FIFO_PROG_FULL_ASSERT_CFGr = 2270, + PPU_PPU_PPU_COP_RANDOM_MOD_RESULT_FIFO_PROG_FULL_NEGATE_CFGr = 2271, + PPU_PPU_PPU_COP_RANDOM_MOD_RESULT_FIFO_PROG_EMPTY_ASSERT_CFGr = 2272, + PPU_PPU_PPU_COP_RANDOM_MOD_RESULT_FIFO_PROG_EMPTY_NEGATE_CFGr = 2273, + PPU_PPU_PPU_COP_CHECKSUM_RESULT_FIFO_PROG_FULL_ASSERT_CFGr = 2274, + PPU_PPU_PPU_COP_CHECKSUM_RESULT_FIFO_PROG_FULL_NEGATE_CFGr = 2275, + PPU_PPU_PPU_COP_CHECKSUM_RESULT_FIFO_PROG_EMPTY_ASSERT_CFGr = 2276, + PPU_PPU_PPU_COP_CHECKSUM_RESULT_FIFO_PROG_EMPTY_NEGATE_CFGr = 2277, + PPU_PPU_PPU_COP_CRC_FIRST_PARA_FIFO_PROG_FULL_ASSERT_CFGr = 2278, + PPU_PPU_PPU_COP_CRC_FIRST_PARA_FIFO_PROG_FULL_NEGATE_CFGr = 2279, + PPU_PPU_PPU_COP_CRC_FIRST_PARA_FIFO_PROG_EMPTY_ASSERT_CFGr = 2280, + PPU_PPU_PPU_COP_CRC_FIRST_PARA_FIFO_PROG_EMPTY_NEGATE_CFGr = 2281, + PPU_PPU_PPU_COP_CRC_BYPASS_DELAY_PROG_FULL_ASSERT_CFGr = 2282, + PPU_PPU_PPU_COP_CRC_BYPASS_DELAY_PROG_FULL_NEGATE_CFGr = 2283, + PPU_PPU_PPU_COP_CRC_BYPASS_DELAY_PROG_EMPTY_ASSERT_CFGr = 2284, + PPU_PPU_PPU_COP_CRC_BYPASS_DELAY_PROG_EMPTY_NEGATE_CFGr = 2285, + PPU_PPU_PPU_COP_CRC_SECOND_PARA_FIFO_PROG_FULL_ASSERT_CFGr = 2286, + PPU_PPU_PPU_COP_CRC_SECOND_PARA_FIFO_PROG_FULL_NEGATE_CFGr = 2287, + PPU_PPU_PPU_COP_CRC_SECOND_PARA_FIFO_PROG_EMPTY_ASSERT_CFGr = 2288, + PPU_PPU_PPU_COP_CRC_SECOND_PARA_FIFO_PROG_EMPTY_NEGATE_CFGr = 2289, + PPU_PPU_PPU_COP_CRC_RESULT_FWFT_FIFO_PROG_FULL_ASSERT_CFGr = 2290, + PPU_PPU_PPU_COP_CRC_RESULT_FWFT_FIFO_PROG_FULL_NEGATE_CFGr = 2291, + PPU_PPU_PPU_COP_CRC_RESULT_FWFT_FIFO_PROG_EMPTY_ASSERT_CFGr = 2292, + PPU_PPU_PPU_COP_CRC_RESULT_FWFT_FIFO_PROG_EMPTY_NEGATE_CFGr = 2293, + PPU_PPU_PPU_COP_MULTIPLY_PARA_FIFO_PROG_FULL_ASSERT_CFGr = 2294, + PPU_PPU_PPU_COP_MULTIPLY_PARA_FIFO_PROG_FULL_NEGATE_CFGr = 2295, + PPU_PPU_PPU_COP_MULTIPLY_PARA_FIFO_PROG_EMPTY_ASSERT_CFGr = 2296, + PPU_PPU_PPU_COP_MULTIPLY_PARA_FIFO_PROG_EMPTY_NEGATE_CFGr = 2297, + PPU_PPU_PPU_COP_MULTIPLY_PARA_RESULT_FIFO_PROG_FULL_ASSERT_CFGr = 2298, + PPU_PPU_PPU_COP_MULTIPLY_PARA_RESULT_FIFO_PROG_FULL_NEGATE_CFGr = 2299, + PPU_PPU_PPU_COP_MULTIPLY_PARA_RESULT_FIFO_PROG_EMPTY_ASSERT_CFGr = 2300, + PPU_PPU_PPU_COP_MULTIPLY_PARA_RESULT_FIFO_PROG_EMPTY_NEGATE_CFGr = 2301, + PPU_PPU_FREE_GLOBAL_NUM_FWFT_FIFO_PROG_FULL_ASSERT_CFGr = 2302, + PPU_PPU_FREE_GLOBAL_NUM_FWFT_FIFO_PROG_FULL_NEGATE_CFGr = 2303, + PPU_PPU_FREE_GLOBAL_NUM_FWFT_FIFO_PROG_EMPTY_ASSERT_CFGr = 2304, + PPU_PPU_FREE_GLOBAL_NUM_FWFT_FIFO_PROG_EMPTY_NEGATE_CFGr = 2305, + PPU_PPU_PPU_PKTRX_MC_PTR_FIFO_PROG_FULL_ASSERT_CFGr = 2306, + PPU_PPU_PPU_PKTRX_MC_PTR_FIFO_PROG_FULL_NEGATE_CFGr = 2307, + PPU_PPU_PPU_PKTRX_MC_PTR_FIFO_PROG_EMPTY_ASSERT_CFGr = 2308, + PPU_PPU_PPU_PKTRX_MC_PTR_FIFO_PROG_EMPTY_NEGATE_CFGr = 2309, + PPU_PPU_PKT_DATA0r = 2310, + PPU_PPU_PKT_DATA1r = 2311, + PPU_PPU_PKT_DATA2r = 2312, + PPU_PPU_PKT_DATA3r = 2313, + PPU_PPU_PKT_DATA4r = 2314, + PPU_PPU_PKT_DATA5r = 2315, + PPU_PPU_PKT_DATA6r = 2316, + PPU_PPU_PKT_DATA7r = 2317, + PPU_PPU_PKT_DATA8r = 2318, + PPU_PPU_PKT_DATA9r = 2319, + PPU_PPU_PKT_DATA10r = 2320, + PPU_PPU_PKT_DATA11r = 2321, + PPU_PPU_PKT_DATA12r = 2322, + PPU_PPU_PKT_DATA13r = 2323, + PPU_PPU_PKT_DATA14r = 2324, + PPU_PPU_PKT_DATA15r = 2325, + PPU_PPU_PKT_DATA16r = 2326, + PPU_PPU_PKT_DATA17r = 2327, + PPU_PPU_PKT_DATA18r = 2328, + PPU_PPU_PKT_DATA19r = 2329, + PPU_PPU_PKT_DATA20r = 2330, + PPU_PPU_PKT_DATA21r = 2331, + PPU_PPU_PKT_DATA22r = 2332, + PPU_PPU_PKT_DATA23r = 2333, + PPU_PPU_PKT_DATA24r = 2334, + PPU_PPU_PKT_DATA25r = 2335, + PPU_PPU_PKT_DATA26r = 2336, + PPU_PPU_PKT_DATA27r = 2337, + PPU_PPU_PKT_DATA28r = 2338, + PPU_PPU_PKT_DATA29r = 2339, + PPU_PPU_PKT_DATA30r = 2340, + PPU_PPU_PKT_DATA31r = 2341, + PPU_PPU_PKT_DATA32r = 2342, + PPU_PPU_PKT_DATA33r = 2343, + PPU_PPU_PKT_DATA34r = 2344, + PPU_PPU_PKT_DATA35r = 2345, + PPU_PPU_PKT_DATA36r = 2346, + PPU_PPU_PKT_DATA37r = 2347, + PPU_PPU_PKT_DATA38r = 2348, + PPU_PPU_PKT_DATA39r = 2349, + PPU_PPU_PKT_DATA40r = 2350, + PPU_PPU_PKT_DATA41r = 2351, + PPU_PPU_PKT_DATA42r = 2352, + PPU_PPU_PKT_DATA43r = 2353, + PPU_PPU_PKT_DATA44r = 2354, + PPU_PPU_PKT_DATA45r = 2355, + PPU_PPU_PKT_DATA46r = 2356, + PPU_PPU_PKT_DATA47r = 2357, + PPU_PPU_PKT_DATA48r = 2358, + PPU_PPU_PKT_DATA49r = 2359, + PPU_PPU_PKT_DATA50r = 2360, + PPU_PPU_PKT_DATA51r = 2361, + PPU_PPU_PKT_DATA52r = 2362, + PPU_PPU_PKT_DATA53r = 2363, + PPU_PPU_PKT_DATA54r = 2364, + PPU_PPU_PKT_DATA55r = 2365, + PPU_PPU_PKT_DATA56r = 2366, + PPU_PPU_PKT_DATA57r = 2367, + PPU_PPU_PKT_DATA58r = 2368, + PPU_PPU_PKT_DATA59r = 2369, + PPU_PPU_PKT_DATA60r = 2370, + PPU_PPU_PKT_DATA61r = 2371, + PPU_PPU_PKT_DATA62r = 2372, + PPU_PPU_PKT_DATA63r = 2373, + PPU_PPU_PKT_DATA64r = 2374, + PPU_PPU_PKT_DATA65r = 2375, + PPU_PPU_PKT_DATA66r = 2376, + PPU_PPU_PKT_DATA67r = 2377, + PPU_PPU_PKT_DATA68r = 2378, + PPU_PPU_PKT_DATA69r = 2379, + PPU_PPU_PKT_DATA70r = 2380, + PPU_PPU_PKT_DATA71r = 2381, + PPU_PPU_PKT_DATA72r = 2382, + PPU_PPU_PKT_DATA73r = 2383, + PPU_PPU_PKT_DATA74r = 2384, + PPU_PPU_PKT_DATA75r = 2385, + PPU_PPU_PKT_DATA76r = 2386, + PPU_PPU_PKT_DATA77r = 2387, + PPU_PPU_PKT_DATA78r = 2388, + PPU_PPU_PKT_DATA79r = 2389, + PPU_PPU_PKT_DATA80r = 2390, + PPU_PPU_PKT_DATA81r = 2391, + PPU_PPU_PKT_DATA82r = 2392, + PPU_PPU_PKT_DATA83r = 2393, + PPU_PPU_PKT_DATA84r = 2394, + PPU_PPU_PKT_DATA85r = 2395, + PPU_PPU_PKT_DATA86r = 2396, + PPU_PPU_PKT_DATA87r = 2397, + PPU_PPU_PKT_DATA88r = 2398, + PPU_PPU_PKT_DATA89r = 2399, + PPU_PPU_PKT_DATA90r = 2400, + PPU_PPU_PKT_DATA91r = 2401, + PPU_PPU_PKT_DATA92r = 2402, + PPU_PPU_PKT_DATA93r = 2403, + PPU_PPU_PKT_DATA94r = 2404, + PPU_PPU_PKT_DATA95r = 2405, + PPU_PPU_PKT_DATA96r = 2406, + PPU_PPU_PKT_DATA97r = 2407, + PPU_PPU_PKT_DATA98r = 2408, + PPU_PPU_PKT_DATA99r = 2409, + PPU_PPU_PKT_DATA100r = 2410, + PPU_PPU_PKT_DATA101r = 2411, + PPU_PPU_PKT_DATA102r = 2412, + PPU_PPU_PKT_DATA103r = 2413, + PPU_PPU_PKT_DATA104r = 2414, + PPU_PPU_PKT_DATA105r = 2415, + PPU_PPU_PKT_DATA106r = 2416, + PPU_PPU_PKT_DATA107r = 2417, + PPU_PPU_PKT_DATA108r = 2418, + PPU_PPU_PKT_DATA109r = 2419, + PPU_PPU_PKT_DATA110r = 2420, + PPU_PPU_PKT_DATA111r = 2421, + PPU_PPU_PKT_DATA112r = 2422, + PPU_PPU_PKT_DATA113r = 2423, + PPU_PPU_PKT_DATA114r = 2424, + PPU_PPU_PKT_DATA115r = 2425, + PPU_PPU_PKT_DATA116r = 2426, + PPU_PPU_PKT_DATA117r = 2427, + PPU_PPU_PKT_DATA118r = 2428, + PPU_PPU_PKT_DATA119r = 2429, + PPU_PPU_PKT_DATA120r = 2430, + PPU_PPU_PKT_DATA121r = 2431, + PPU_PPU_PKT_DATA122r = 2432, + PPU_PPU_PKT_DATA123r = 2433, + PPU_PPU_PKT_DATA124r = 2434, + PPU_PPU_PKT_DATA125r = 2435, + PPU_PPU_PKT_DATA126r = 2436, + PPU_PPU_PKT_DATA127r = 2437, + PPU_PPU_SPR0r = 2438, + PPU_PPU_SPR1r = 2439, + PPU_PPU_SPR2r = 2440, + PPU_PPU_SPR3r = 2441, + PPU_PPU_SPR4r = 2442, + PPU_PPU_SPR5r = 2443, + PPU_PPU_SPR6r = 2444, + PPU_PPU_SPR7r = 2445, + PPU_PPU_SPR8r = 2446, + PPU_PPU_SPR9r = 2447, + PPU_PPU_SPR10r = 2448, + PPU_PPU_SPR11r = 2449, + PPU_PPU_SPR12r = 2450, + PPU_PPU_SPR13r = 2451, + PPU_PPU_SPR14r = 2452, + PPU_PPU_SPR15r = 2453, + PPU_PPU_SPR16r = 2454, + PPU_PPU_SPR17r = 2455, + PPU_PPU_SPR18r = 2456, + PPU_PPU_SPR19r = 2457, + PPU_PPU_SPR20r = 2458, + PPU_PPU_SPR21r = 2459, + PPU_PPU_SPR22r = 2460, + PPU_PPU_SPR23r = 2461, + PPU_PPU_SPR24r = 2462, + PPU_PPU_SPR25r = 2463, + PPU_PPU_SPR26r = 2464, + PPU_PPU_SPR27r = 2465, + PPU_PPU_SPR28r = 2466, + PPU_PPU_SPR29r = 2467, + PPU_PPU_SPR30r = 2468, + PPU_PPU_SPR31r = 2469, + PPU_PPU_RSP0r = 2470, + PPU_PPU_RSP1r = 2471, + PPU_PPU_RSP2r = 2472, + PPU_PPU_RSP3r = 2473, + PPU_PPU_RSP4r = 2474, + PPU_PPU_RSP5r = 2475, + PPU_PPU_RSP6r = 2476, + PPU_PPU_RSP7r = 2477, + PPU_PPU_RSP8r = 2478, + PPU_PPU_RSP9r = 2479, + PPU_PPU_RSP10r = 2480, + PPU_PPU_RSP11r = 2481, + PPU_PPU_RSP12r = 2482, + PPU_PPU_RSP13r = 2483, + PPU_PPU_RSP14r = 2484, + PPU_PPU_RSP15r = 2485, + PPU_PPU_RSP16r = 2486, + PPU_PPU_RSP17r = 2487, + PPU_PPU_RSP18r = 2488, + PPU_PPU_RSP19r = 2489, + PPU_PPU_RSP20r = 2490, + PPU_PPU_RSP21r = 2491, + PPU_PPU_RSP22r = 2492, + PPU_PPU_RSP23r = 2493, + PPU_PPU_RSP24r = 2494, + PPU_PPU_RSP25r = 2495, + PPU_PPU_RSP26r = 2496, + PPU_PPU_RSP27r = 2497, + PPU_PPU_RSP28r = 2498, + PPU_PPU_RSP29r = 2499, + PPU_PPU_RSP30r = 2500, + PPU_PPU_RSP31r = 2501, + PPU_PPU_KEY0r = 2502, + PPU_PPU_KEY1r = 2503, + PPU_PPU_KEY2r = 2504, + PPU_PPU_KEY3r = 2505, + PPU_PPU_KEY4r = 2506, + PPU_PPU_KEY5r = 2507, + PPU_PPU_KEY6r = 2508, + PPU_PPU_KEY7r = 2509, + PPU_PPU_KEY8r = 2510, + PPU_PPU_KEY9r = 2511, + PPU_PPU_KEY10r = 2512, + PPU_PPU_KEY11r = 2513, + PPU_PPU_KEY12r = 2514, + PPU_PPU_KEY13r = 2515, + PPU_PPU_KEY14r = 2516, + PPU_PPU_KEY15r = 2517, + PPU_PPU_KEY16r = 2518, + PPU_PPU_KEY17r = 2519, + PPU_PPU_KEY18r = 2520, + PPU_PPU_KEY19r = 2521, + PPU_PPU_FLAGr = 2522, + PPU_CLUSTER_INT_1200M_FLAGr = 2523, + PPU_CLUSTER_BP_INSTR_Lr = 2524, + PPU_CLUSTER_BP_INSTR_Hr = 2525, + PPU_CLUSTER_BP_ADDRr = 2526, + PPU_CLUSTER_DRRr = 2527, + PPU_CLUSTER_DSRr = 2528, + PPU_CLUSTER_DBG_RTL_DATEr = 2529, + PPU_CLUSTER_ME_CONTINUEr = 2530, + PPU_CLUSTER_ME_STEPr = 2531, + PPU_CLUSTER_ME_REFRESHr = 2532, + PPU_CLUSTER_DRR_CLRr = 2533, + PPU_CLUSTER_ME_BUSY_THRESOLDr = 2534, + PPU_CLUSTER_INT_1200M_STAr = 2535, + PPU_CLUSTER_INT_1200M_ME_FIFO_MASK_Lr = 2536, + PPU_CLUSTER_INT_1200M_ME_FIFO_MASK_Hr = 2537, + PPU_CLUSTER_ME_FIFO_INTERRUPT_FLAG_Lr = 2538, + PPU_CLUSTER_ME_FIFO_INTERRUPT_FLAG_Hr = 2539, + PPU_CLUSTER_ME_FIFO_INTERRUPT_STA_Lr = 2540, + PPU_CLUSTER_ME_FIFO_INTERRUPT_STA_Hr = 2541, + PPU_CLUSTER_INT_1200M_CLUSTER_MEX_FIFO_MASK_Lr = 2542, + PPU_CLUSTER_INT_1200M_CLUSTER_MEX_FIFO_MASK_Hr = 2543, + PPU_CLUSTER_INT_1200M_CLUSTER_MEX_FIFO_FLAG_Lr = 2544, + PPU_CLUSTER_INT_1200M_CLUSTER_MEX_FIFO_FLAG_Hr = 2545, + PPU_CLUSTER_INT_1200M_CLUSTER_MEX_FIFO_STAT_Lr = 2546, + PPU_CLUSTER_INT_1200M_CLUSTER_MEX_FIFO_STAT_Hr = 2547, + PPU_CLUSTER_PPU_STATICS_WB_EXCEPTION_CFGr = 2548, + PPU_CLUSTER_THREAD_SWITCH_ENr = 2549, + PPU_CLUSTER_IS_ME_NOT_IDLEr = 2550, + PPU_CLUSTER_PPU_CLUSTER_MF_IN_AFIFO_PROG_EMPTY_ASSERT_CFGr = 2551, + PPU_CLUSTER_PPU_CLUSTER_MF_IN_AFIFO_PROG_EMPTY_NEGATE_CFGr = 2552, + PPU_CLUSTER_ESE_RSP_AFIFO_PROG_EMPTY_ASSERT_CFGr = 2553, + PPU_CLUSTER_ESE_RSP_AFIFO_PROG_EMPTY_NEGATE_CFGr = 2554, + PPU_CLUSTER_ISE_RSP_AFIFO_PROG_EMPTY_ASSERT_CFGr = 2555, + PPU_CLUSTER_ISE_RSP_AFIFO_PROG_EMPTY_NEGATE_CFGr = 2556, + PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO0_PROG_FULL_ASSERT_CFGr = 2557, + PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO0_PROG_FULL_NEGATE_CFGr = 2558, + PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO0_PROG_EMPTY_ASSERT_CFGr = 2559, + PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO0_PROG_EMPTY_NEGATE_CFGr = 2560, + PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO1_PROG_FULL_ASSERT_CFGr = 2561, + PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO1_PROG_FULL_NEGATE_CFGr = 2562, + PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO1_PROG_EMPTY_ASSERT_CFGr = 2563, + PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO1_PROG_EMPTY_NEGATE_CFGr = 2564, + PPU_CLUSTER_STA_RSP_AFIFO_PROG_EMPTY_ASSERT_CFGr = 2565, + PPU_CLUSTER_STA_RSP_AFIFO_PROG_EMPTY_NEGATE_CFGr = 2566, + PPU_CLUSTER_PPU_STA_RSP_FWFT_FIFO_PROG_FULL_ASSERT_CFGr = 2567, + PPU_CLUSTER_PPU_STA_RSP_FWFT_FIFO_PROG_FULL_NEGATE_CFGr = 2568, + PPU_CLUSTER_PPU_STA_RSP_FWFT_FIFO_PROG_EMPTY_ASSERT_CFGr = 2569, + PPU_CLUSTER_PPU_STA_RSP_FWFT_FIFO_PROG_EMPTY_NEGATE_CFGr = 2570, + PPU_CLUSTER_COP_RSP_FIFO_PROG_FULL_ASSERT_CFGr = 2571, + PPU_CLUSTER_COP_RSP_FIFO_PROG_FULL_NEGATE_CFGr = 2572, + PPU_CLUSTER_COP_RSP_FIFO_PROG_EMPTY_ASSERT_CFGr = 2573, + PPU_CLUSTER_COP_RSP_FIFO_PROG_EMPTY_NEGATE_CFGr = 2574, + PPU_CLUSTER_MCODE_PF_RSP_FIFO_PROG_FULL_ASSERT_CFGr = 2575, + PPU_CLUSTER_MCODE_PF_RSP_FIFO_PROG_FULL_NEGATE_CFGr = 2576, + PPU_CLUSTER_MCODE_PF_RSP_FIFO_PROG_EMPTY_ASSERT_CFGr = 2577, + PPU_CLUSTER_MCODE_PF_RSP_FIFO_PROG_EMPTY_NEGATE_CFGr = 2578, + PPU_CLUSTER_PPU_COP_RSP_FWFT_FIFO_PROG_FULL_ASSERT_CFGr = 2579, + PPU_CLUSTER_PPU_COP_RSP_FWFT_FIFO_PROG_FULL_NEGATE_CFGr = 2580, + PPU_CLUSTER_PPU_COP_RSP_FWFT_FIFO_PROG_EMPTY_ASSERT_CFGr = 2581, + PPU_CLUSTER_PPU_COP_RSP_FWFT_FIFO_PROG_EMPTY_NEGATE_CFGr = 2582, + PPU_CLUSTER_PPU_ISE_KEY_AFIFO_PROG_FULL_ASSERT_CFGr = 2583, + PPU_CLUSTER_PPU_ISE_KEY_AFIFO_PROG_FULL_NEGATE_CFGr = 2584, + PPU_CLUSTER_PPU_ESE_KEY_AFIFO_PROG_FULL_ASSERT_CFGr = 2585, + PPU_CLUSTER_PPU_ESE_KEY_AFIFO_PROG_FULL_NEGATE_CFGr = 2586, + PPU_CLUSTER_PPU_STA_KEY_AFIFO_PROG_FULL_ASSERT_CFGr = 2587, + PPU_CLUSTER_PPU_STA_KEY_AFIFO_PROG_FULL_NEGATE_CFGr = 2588, + PPU_CLUSTER_INT_600M_CLUSTER_MEX_FIFO_MASKr = 2589, + PPU_CLUSTER_CLUSTER_MEX_FIFO_600M_INTERRUPT_FLAGr = 2590, + PPU_CLUSTER_CLUSTER_MEX_FIFO_600M_INTERRUPT_STAr = 2591, + PPU_CLUSTER_MEX_CNT_CFGr = 2592, + PPU_CLUSTER_INT_600M_CLUSTER_MEX_RAM_ECC_ERROR_INTERRUPT_MASKr = 2593, + PPU_CLUSTER_CLUSTER_MEX_RAM_600M_ECC_ERROR_INTERRUPT_FLAGr = 2594, + PPU_CLUSTER_CLUSTER_MEX_RAM_600M_ECC_ERROR_INTERRUPT_STAr = 2595, + PPU_CLUSTER_PPU_CLUSTER_MF_IN_AFIFO_PROG_FULL_ASSERT_CFGr = 2596, + PPU_CLUSTER_PPU_CLUSTER_MF_IN_AFIFO_PROG_FULL_NEGATE_CFGr = 2597, + PPU_CLUSTER_ESE_RSP_AFIFO_PROG_FULL_ASSERT_CFGr = 2598, + PPU_CLUSTER_ESE_RSP_AFIFO_PROG_FULL_NEGATE_CFGr = 2599, + PPU_CLUSTER_ISE_RSP_AFIFO_PROG_FULL_ASSERT_CFGr = 2600, + PPU_CLUSTER_ISE_RSP_AFIFO_PROG_FULL_NEGATE_CFGr = 2601, + PPU_CLUSTER_STA_RSP_AFIFO_PROG_FULL_ASSERT_CFGr = 2602, + PPU_CLUSTER_STA_RSP_AFIFO_PROG_FULL_NEGATE_CFGr = 2603, + PPU_CLUSTER_PPU_ISE_KEY_AFIFO_PROG_EMPTY_ASSERT_CFGr = 2604, + PPU_CLUSTER_PPU_ISE_KEY_AFIFO_PROG_EMPTY_NEGATE_CFGr = 2605, + PPU_CLUSTER_PPU_ESE_KEY_AFIFO_PROG_EMPTY_ASSERT_CFGr = 2606, + PPU_CLUSTER_PPU_ESE_KEY_AFIFO_PROG_EMPTY_NEGATE_CFGr = 2607, + PPU_CLUSTER_PPU_STA_KEY_AFIFO_PROG_EMPTY_ASSERT_CFGr = 2608, + PPU_CLUSTER_PPU_STA_KEY_AFIFO_PROG_EMPTY_NEGATE_CFGr = 2609, + PPU_CLUSTER_PPU_CLUSTER_MF_VLD_CNT_Hr = 2610, + PPU_CLUSTER_PPU_CLUSTER_MF_VLD_CNT_Lr = 2611, + PPU_CLUSTER_CLUSTER_ISE_KEY_OUT_VLD_CNTr = 2612, + PPU_CLUSTER_ISE_CLUSTER_RSP_IN_VLD_CNTr = 2613, + PPU_CLUSTER_CLUSTER_ESE_KEY_OUT_VLD_CNTr = 2614, + PPU_CLUSTER_ESE_CLUSTER_RSP_IN_VLD_CNTr = 2615, + PPU_CLUSTER_CLUSTER_STAT_CMD_VLD_CNTr = 2616, + PPU_CLUSTER_STAT_CLUSTER_RSP_VLD_CNTr = 2617, + PPU_CLUSTER_MEX_DEBUG_KEY_VLD_CNTr = 2618, + PPU_CLUSTER_ISE_CLUSTER_KEY_FC_CNTr = 2619, + PPU_CLUSTER_ESE_CLUSTER_KEY_FC_CNTr = 2620, + PPU_CLUSTER_CLUSTER_ISE_RSP_FC_CNTr = 2621, + PPU_CLUSTER_CLUSTER_ESE_RSP_FC_CNTr = 2622, + PPU_CLUSTER_STAT_CLUSTER_CMD_FC_CNTr = 2623, + PPU_CLUSTER_CLUSTER_STAT_RSP_FC_CNTr = 2624, + PPU_CLUSTER_CLUSTER_PPU_MF_VLD_CNT_Lr = 2625, + PPU_CLUSTER_CLUSTER_PPU_MF_VLD_CNT_Hr = 2626, + PPU_CLUSTER_CLUSTER_COP_KEY_VLD_CNT_Lr = 2627, + PPU_CLUSTER_CLUSTER_COP_KEY_VLD_CNT_Hr = 2628, + PPU_CLUSTER_COP_CLUSTER_RSP_VLD_CNT_Lr = 2629, + PPU_CLUSTER_COP_CLUSTER_RSP_VLD_CNT_Hr = 2630, + PPU_CLUSTER_MEX_ME_PKT_IN_SOP_CNT_Lr = 2631, + PPU_CLUSTER_MEX_ME_PKT_IN_SOP_CNT_Hr = 2632, + PPU_CLUSTER_MEX_ME_PKT_IN_EOP_CNT_Lr = 2633, + PPU_CLUSTER_MEX_ME_PKT_IN_EOP_CNT_Hr = 2634, + PPU_CLUSTER_MEX_ME_PKT_IN_VLD_CNT_Lr = 2635, + PPU_CLUSTER_MEX_ME_PKT_IN_VLD_CNT_Hr = 2636, + PPU_CLUSTER_ME_MEX_PKT_OUT_SOP_CNT_Lr = 2637, + PPU_CLUSTER_ME_MEX_PKT_OUT_SOP_CNT_Hr = 2638, + PPU_CLUSTER_ME_MEX_PKT_OUT_EOP_CNT_Lr = 2639, + PPU_CLUSTER_ME_MEX_PKT_OUT_EOP_CNT_Hr = 2640, + PPU_CLUSTER_ME_MEX_PKT_OUT_VLD_CNT_Lr = 2641, + PPU_CLUSTER_ME_MEX_PKT_OUT_VLD_CNT_Hr = 2642, + PPU_CLUSTER_ME_MEX_I_KEY_OUT_SOP_CNT_Lr = 2643, + PPU_CLUSTER_ME_MEX_I_KEY_OUT_SOP_CNT_Hr = 2644, + PPU_CLUSTER_ME_MEX_I_KEY_OUT_EOP_CNT_Lr = 2645, + PPU_CLUSTER_ME_MEX_I_KEY_OUT_EOP_CNT_Hr = 2646, + PPU_CLUSTER_ME_MEX_I_KEY_OUT_VLD_CNT_Lr = 2647, + PPU_CLUSTER_ME_MEX_I_KEY_OUT_VLD_CNT_Hr = 2648, + PPU_CLUSTER_ME_MEX_E_KEY_OUT_SOP_CNT_Lr = 2649, + PPU_CLUSTER_ME_MEX_E_KEY_OUT_SOP_CNT_Hr = 2650, + PPU_CLUSTER_ME_MEX_E_KEY_OUT_EOP_CNT_Lr = 2651, + PPU_CLUSTER_ME_MEX_E_KEY_OUT_EOP_CNT_Hr = 2652, + PPU_CLUSTER_ME_MEX_E_KEY_OUT_VLD_CNT_Lr = 2653, + PPU_CLUSTER_ME_MEX_E_KEY_OUT_VLD_CNT_Hr = 2654, + PPU_CLUSTER_ME_MEX_DEMUX_ISE_KEY_VLD_CNT_Lr = 2655, + PPU_CLUSTER_ME_MEX_DEMUX_ISE_KEY_VLD_CNT_Hr = 2656, + PPU_CLUSTER_ME_MEX_DEMUX_ESE_KEY_VLD_CNT_Lr = 2657, + PPU_CLUSTER_ME_MEX_DEMUX_ESE_KEY_VLD_CNT_Hr = 2658, + PPU_CLUSTER_ME_MEX_DEMUX_STA_KEY_VLD_CNT_Lr = 2659, + PPU_CLUSTER_ME_MEX_DEMUX_STA_KEY_VLD_CNT_Hr = 2660, + PPU_CLUSTER_ME_MEX_DEMUX_COP_KEY_VLD_CNT_Lr = 2661, + PPU_CLUSTER_ME_MEX_DEMUX_COP_KEY_VLD_CNT_Hr = 2662, + PPU_CLUSTER_MEX_ME_DEMUX_ISE_RSP_VLD_CNT_Lr = 2663, + PPU_CLUSTER_MEX_ME_DEMUX_ISE_RSP_VLD_CNT_Hr = 2664, + PPU_CLUSTER_MEX_ME_DEMUX_ESE_RSP_VLD_CNT_Lr = 2665, + PPU_CLUSTER_MEX_ME_DEMUX_ESE_RSP_VLD_CNT_Hr = 2666, + PPU_CLUSTER_MEX_ME_DEMUX_STA_RSP_VLD_CNT_Lr = 2667, + PPU_CLUSTER_MEX_ME_DEMUX_STA_RSP_VLD_CNT_Hr = 2668, + PPU_CLUSTER_MEX_ME_DEMUX_COP_RSP_VLD_CNT_Lr = 2669, + PPU_CLUSTER_MEX_ME_DEMUX_COP_RSP_VLD_CNT_Hr = 2670, + PPU_CLUSTER_ME_EXCEPTION_CODE0_CNT_Lr = 2671, + PPU_CLUSTER_ME_EXCEPTION_CODE0_CNT_Hr = 2672, + PPU_CLUSTER_ME_EXCEPTION_CODE1_CNT_Lr = 2673, + PPU_CLUSTER_ME_EXCEPTION_CODE1_CNT_Hr = 2674, + PPU_CLUSTER_ME_EXCEPTION_CODE2_CNT_Lr = 2675, + PPU_CLUSTER_ME_EXCEPTION_CODE2_CNT_Hr = 2676, + PPU_CLUSTER_ME_EXCEPTION_CODE3_CNT_Lr = 2677, + PPU_CLUSTER_ME_EXCEPTION_CODE3_CNT_Hr = 2678, + PPU_CLUSTER_ME_EXCEPTION_CODE4_CNT_Lr = 2679, + PPU_CLUSTER_ME_EXCEPTION_CODE4_CNT_Hr = 2680, + PPU_CLUSTER_ME_EXCEPTION_CODE5_CNT_Lr = 2681, + PPU_CLUSTER_ME_EXCEPTION_CODE5_CNT_Hr = 2682, + SE_CFG_PPU_SOFT_RSTr = 2683, + SE_CFG_EPT_FLAGr = 2684, + SE_CFG_DDR_KEY_LK0_3r = 2685, + SE_CFG_DDR_KEY_LK0_2r = 2686, + SE_CFG_DDR_KEY_LK0_1r = 2687, + SE_CFG_DDR_KEY_LK0_0r = 2688, + SE_CFG_DDR_KEY_LK1_3r = 2689, + SE_CFG_DDR_KEY_LK1_2r = 2690, + SE_CFG_DDR_KEY_LK1_1r = 2691, + SE_CFG_DDR_KEY_LK1_0r = 2692, + SE_CFG_HASH_KEY_LK0_18r = 2693, + SE_CFG_HASH_KEY_LK0_17r = 2694, + SE_CFG_HASH_KEY_LK0_16r = 2695, + SE_CFG_HASH_KEY_LK0_15r = 2696, + SE_CFG_HASH_KEY_LK0_14r = 2697, + SE_CFG_HASH_KEY_LK0_13r = 2698, + SE_CFG_HASH_KEY_LK0_12r = 2699, + SE_CFG_HASH_KEY_LK0_11r = 2700, + SE_CFG_HASH_KEY_LK0_10r = 2701, + SE_CFG_HASH_KEY_LK0_9r = 2702, + SE_CFG_HASH_KEY_LK0_8r = 2703, + SE_CFG_HASH_KEY_LK0_7r = 2704, + SE_CFG_HASH_KEY_LK0_6r = 2705, + SE_CFG_HASH_KEY_LK0_5r = 2706, + SE_CFG_HASH_KEY_LK0_4r = 2707, + SE_CFG_HASH_KEY_LK0_3r = 2708, + SE_CFG_HASH_KEY_LK0_2r = 2709, + SE_CFG_HASH_KEY_LK0_1r = 2710, + SE_CFG_HASH_KEY_LK0_0r = 2711, + SE_CFG_HASH_KEY_LK1_18r = 2712, + SE_CFG_HASH_KEY_LK1_17r = 2713, + SE_CFG_HASH_KEY_LK1_16r = 2714, + SE_CFG_HASH_KEY_LK1_15r = 2715, + SE_CFG_HASH_KEY_LK1_14r = 2716, + SE_CFG_HASH_KEY_LK1_13r = 2717, + SE_CFG_HASH_KEY_LK1_12r = 2718, + SE_CFG_HASH_KEY_LK1_11r = 2719, + SE_CFG_HASH_KEY_LK1_10r = 2720, + SE_CFG_HASH_KEY_LK1_9r = 2721, + SE_CFG_HASH_KEY_LK1_8r = 2722, + SE_CFG_HASH_KEY_LK1_7r = 2723, + SE_CFG_HASH_KEY_LK1_6r = 2724, + SE_CFG_HASH_KEY_LK1_5r = 2725, + SE_CFG_HASH_KEY_LK1_4r = 2726, + SE_CFG_HASH_KEY_LK1_3r = 2727, + SE_CFG_HASH_KEY_LK1_2r = 2728, + SE_CFG_HASH_KEY_LK1_1r = 2729, + SE_CFG_HASH_KEY_LK1_0r = 2730, + SE_CFG_HASH_KEY_LK2_18r = 2731, + SE_CFG_HASH_KEY_LK2_17r = 2732, + SE_CFG_HASH_KEY_LK2_16r = 2733, + SE_CFG_HASH_KEY_LK2_15r = 2734, + SE_CFG_HASH_KEY_LK2_14r = 2735, + SE_CFG_HASH_KEY_LK2_13r = 2736, + SE_CFG_HASH_KEY_LK2_12r = 2737, + SE_CFG_HASH_KEY_LK2_11r = 2738, + SE_CFG_HASH_KEY_LK2_10r = 2739, + SE_CFG_HASH_KEY_LK2_9r = 2740, + SE_CFG_HASH_KEY_LK2_8r = 2741, + SE_CFG_HASH_KEY_LK2_7r = 2742, + SE_CFG_HASH_KEY_LK2_6r = 2743, + SE_CFG_HASH_KEY_LK2_5r = 2744, + SE_CFG_HASH_KEY_LK2_4r = 2745, + SE_CFG_HASH_KEY_LK2_3r = 2746, + SE_CFG_HASH_KEY_LK2_2r = 2747, + SE_CFG_HASH_KEY_LK2_1r = 2748, + SE_CFG_HASH_KEY_LK2_0r = 2749, + SE_CFG_HASH_KEY_LK3_18r = 2750, + SE_CFG_HASH_KEY_LK3_17r = 2751, + SE_CFG_HASH_KEY_LK3_16r = 2752, + SE_CFG_HASH_KEY_LK3_15r = 2753, + SE_CFG_HASH_KEY_LK3_14r = 2754, + SE_CFG_HASH_KEY_LK3_13r = 2755, + SE_CFG_HASH_KEY_LK3_12r = 2756, + SE_CFG_HASH_KEY_LK3_11r = 2757, + SE_CFG_HASH_KEY_LK3_10r = 2758, + SE_CFG_HASH_KEY_LK3_9r = 2759, + SE_CFG_HASH_KEY_LK3_8r = 2760, + SE_CFG_HASH_KEY_LK3_7r = 2761, + SE_CFG_HASH_KEY_LK3_6r = 2762, + SE_CFG_HASH_KEY_LK3_5r = 2763, + SE_CFG_HASH_KEY_LK3_4r = 2764, + SE_CFG_HASH_KEY_LK3_3r = 2765, + SE_CFG_HASH_KEY_LK3_2r = 2766, + SE_CFG_HASH_KEY_LK3_1r = 2767, + SE_CFG_HASH_KEY_LK3_0r = 2768, + SE_CFG_LPM_KEY_LK0_6r = 2769, + SE_CFG_LPM_KEY_LK0_5r = 2770, + SE_CFG_LPM_KEY_LK0_4r = 2771, + SE_CFG_LPM_KEY_LK0_3r = 2772, + SE_CFG_LPM_KEY_LK0_2r = 2773, + SE_CFG_LPM_KEY_LK0_1r = 2774, + SE_CFG_LPM_KEY_LK0_0r = 2775, + SE_CFG_LPM_KEY_LK1_6r = 2776, + SE_CFG_LPM_KEY_LK1_5r = 2777, + SE_CFG_LPM_KEY_LK1_4r = 2778, + SE_CFG_LPM_KEY_LK1_3r = 2779, + SE_CFG_LPM_KEY_LK1_2r = 2780, + SE_CFG_LPM_KEY_LK1_1r = 2781, + SE_CFG_LPM_KEY_LK1_0r = 2782, + SE_CFG_LPM_KEY_LK2_6r = 2783, + SE_CFG_LPM_KEY_LK2_5r = 2784, + SE_CFG_LPM_KEY_LK2_4r = 2785, + SE_CFG_LPM_KEY_LK2_3r = 2786, + SE_CFG_LPM_KEY_LK2_2r = 2787, + SE_CFG_LPM_KEY_LK2_1r = 2788, + SE_CFG_LPM_KEY_LK2_0r = 2789, + SE_CFG_LPM_KEY_LK3_6r = 2790, + SE_CFG_LPM_KEY_LK3_5r = 2791, + SE_CFG_LPM_KEY_LK3_4r = 2792, + SE_CFG_LPM_KEY_LK3_3r = 2793, + SE_CFG_LPM_KEY_LK3_2r = 2794, + SE_CFG_LPM_KEY_LK3_1r = 2795, + SE_CFG_LPM_KEY_LK3_0r = 2796, + SE_CFG_ETCAM_KEY_LK0_22r = 2797, + SE_CFG_ETCAM_KEY_LK0_21r = 2798, + SE_CFG_ETCAM_KEY_LK0_20r = 2799, + SE_CFG_ETCAM_KEY_LK0_19r = 2800, + SE_CFG_ETCAM_KEY_LK0_18r = 2801, + SE_CFG_ETCAM_KEY_LK0_17r = 2802, + SE_CFG_ETCAM_KEY_LK0_16r = 2803, + SE_CFG_ETCAM_KEY_LK0_15r = 2804, + SE_CFG_ETCAM_KEY_LK0_14r = 2805, + SE_CFG_ETCAM_KEY_LK0_13r = 2806, + SE_CFG_ETCAM_KEY_LK0_12r = 2807, + SE_CFG_ETCAM_KEY_LK0_11r = 2808, + SE_CFG_ETCAM_KEY_LK0_10r = 2809, + SE_CFG_ETCAM_KEY_LK0_9r = 2810, + SE_CFG_ETCAM_KEY_LK0_8r = 2811, + SE_CFG_ETCAM_KEY_LK0_7r = 2812, + SE_CFG_ETCAM_KEY_LK0_6r = 2813, + SE_CFG_ETCAM_KEY_LK0_5r = 2814, + SE_CFG_ETCAM_KEY_LK0_4r = 2815, + SE_CFG_ETCAM_KEY_LK0_3r = 2816, + SE_CFG_ETCAM_KEY_LK0_2r = 2817, + SE_CFG_ETCAM_KEY_LK0_1r = 2818, + SE_CFG_ETCAM_KEY_LK0_0r = 2819, + SE_CFG_ETCAM_KEY_LK1_22r = 2820, + SE_CFG_ETCAM_KEY_LK1_21r = 2821, + SE_CFG_ETCAM_KEY_LK1_20r = 2822, + SE_CFG_ETCAM_KEY_LK1_19r = 2823, + SE_CFG_ETCAM_KEY_LK1_18r = 2824, + SE_CFG_ETCAM_KEY_LK1_17r = 2825, + SE_CFG_ETCAM_KEY_LK1_16r = 2826, + SE_CFG_ETCAM_KEY_LK1_15r = 2827, + SE_CFG_ETCAM_KEY_LK1_14r = 2828, + SE_CFG_ETCAM_KEY_LK1_13r = 2829, + SE_CFG_ETCAM_KEY_LK1_12r = 2830, + SE_CFG_ETCAM_KEY_LK1_11r = 2831, + SE_CFG_ETCAM_KEY_LK1_10r = 2832, + SE_CFG_ETCAM_KEY_LK1_9r = 2833, + SE_CFG_ETCAM_KEY_LK1_8r = 2834, + SE_CFG_ETCAM_KEY_LK1_7r = 2835, + SE_CFG_ETCAM_KEY_LK1_6r = 2836, + SE_CFG_ETCAM_KEY_LK1_5r = 2837, + SE_CFG_ETCAM_KEY_LK1_4r = 2838, + SE_CFG_ETCAM_KEY_LK1_3r = 2839, + SE_CFG_ETCAM_KEY_LK1_2r = 2840, + SE_CFG_ETCAM_KEY_LK1_1r = 2841, + SE_CFG_ETCAM_KEY_LK1_0r = 2842, + SE_CFG_ETCAM_KEY_LK2_22r = 2843, + SE_CFG_ETCAM_KEY_LK2_21r = 2844, + SE_CFG_ETCAM_KEY_LK2_20r = 2845, + SE_CFG_ETCAM_KEY_LK2_19r = 2846, + SE_CFG_ETCAM_KEY_LK2_18r = 2847, + SE_CFG_ETCAM_KEY_LK2_17r = 2848, + SE_CFG_ETCAM_KEY_LK2_16r = 2849, + SE_CFG_ETCAM_KEY_LK2_15r = 2850, + SE_CFG_ETCAM_KEY_LK2_14r = 2851, + SE_CFG_ETCAM_KEY_LK2_13r = 2852, + SE_CFG_ETCAM_KEY_LK2_12r = 2853, + SE_CFG_ETCAM_KEY_LK2_11r = 2854, + SE_CFG_ETCAM_KEY_LK2_10r = 2855, + SE_CFG_ETCAM_KEY_LK2_9r = 2856, + SE_CFG_ETCAM_KEY_LK2_8r = 2857, + SE_CFG_ETCAM_KEY_LK2_7r = 2858, + SE_CFG_ETCAM_KEY_LK2_6r = 2859, + SE_CFG_ETCAM_KEY_LK2_5r = 2860, + SE_CFG_ETCAM_KEY_LK2_4r = 2861, + SE_CFG_ETCAM_KEY_LK2_3r = 2862, + SE_CFG_ETCAM_KEY_LK2_2r = 2863, + SE_CFG_ETCAM_KEY_LK2_1r = 2864, + SE_CFG_ETCAM_KEY_LK2_0r = 2865, + SE_CFG_ETCAM_KEY_LK3_22r = 2866, + SE_CFG_ETCAM_KEY_LK3_21r = 2867, + SE_CFG_ETCAM_KEY_LK3_20r = 2868, + SE_CFG_ETCAM_KEY_LK3_19r = 2869, + SE_CFG_ETCAM_KEY_LK3_18r = 2870, + SE_CFG_ETCAM_KEY_LK3_17r = 2871, + SE_CFG_ETCAM_KEY_LK3_16r = 2872, + SE_CFG_ETCAM_KEY_LK3_15r = 2873, + SE_CFG_ETCAM_KEY_LK3_14r = 2874, + SE_CFG_ETCAM_KEY_LK3_13r = 2875, + SE_CFG_ETCAM_KEY_LK3_12r = 2876, + SE_CFG_ETCAM_KEY_LK3_11r = 2877, + SE_CFG_ETCAM_KEY_LK3_10r = 2878, + SE_CFG_ETCAM_KEY_LK3_9r = 2879, + SE_CFG_ETCAM_KEY_LK3_8r = 2880, + SE_CFG_ETCAM_KEY_LK3_7r = 2881, + SE_CFG_ETCAM_KEY_LK3_6r = 2882, + SE_CFG_ETCAM_KEY_LK3_5r = 2883, + SE_CFG_ETCAM_KEY_LK3_4r = 2884, + SE_CFG_ETCAM_KEY_LK3_3r = 2885, + SE_CFG_ETCAM_KEY_LK3_2r = 2886, + SE_CFG_ETCAM_KEY_LK3_1r = 2887, + SE_CFG_ETCAM_KEY_LK3_0r = 2888, + SE_CFG_PBU_KEY_LK0_3r = 2889, + SE_CFG_PBU_KEY_LK0_2r = 2890, + SE_CFG_PBU_KEY_LK0_1r = 2891, + SE_CFG_PBU_KEY_LK0_0r = 2892, + SE_CFG_PBU_KEY_LK1_3r = 2893, + SE_CFG_PBU_KEY_LK1_2r = 2894, + SE_CFG_PBU_KEY_LK1_1r = 2895, + SE_CFG_PBU_KEY_LK1_0r = 2896, + SE_CFG_PBU_KEY_LK2_3r = 2897, + SE_CFG_PBU_KEY_LK2_2r = 2898, + SE_CFG_PBU_KEY_LK2_1r = 2899, + SE_CFG_PBU_KEY_LK2_0r = 2900, + SE_CFG_PBU_KEY_LK3_3r = 2901, + SE_CFG_PBU_KEY_LK3_2r = 2902, + SE_CFG_PBU_KEY_LK3_1r = 2903, + SE_CFG_PBU_KEY_LK3_0r = 2904, + SE_ALG_SCHD_LEARN_FIFO_PFULL_ASTr = 2905, + SE_ALG_SCHD_LEARN_FIFO_PFULL_NEGr = 2906, + SE_ALG_SCHD_HASH0_FIFO_PFULL_ASTr = 2907, + SE_ALG_SCHD_HASH0_FIFO_PFULL_NEGr = 2908, + SE_ALG_SCHD_HASH1_FIFO_PFULL_ASTr = 2909, + SE_ALG_SCHD_HASH1_FIFO_PFULL_NEGr = 2910, + SE_ALG_SCHD_HASH2_FIFO_PFULL_ASTr = 2911, + SE_ALG_SCHD_HASH2_FIFO_PFULL_NEGr = 2912, + SE_ALG_SCHD_HASH3_FIFO_PFULL_ASTr = 2913, + SE_ALG_SCHD_HASH3_FIFO_PFULL_NEGr = 2914, + SE_ALG_SCHD_LPM_FIFO_PFULL_ASTr = 2915, + SE_ALG_SCHD_LPM_FIFO_PFULL_NEGr = 2916, + SE_ALG_HASH0_KEY_FIFO_PFULL_ASTr = 2917, + SE_ALG_HASH0_KEY_FIFO_PFULL_NEGr = 2918, + SE_ALG_HASH0_SREQ_FIFO_PFULL_ASTr = 2919, + SE_ALG_HASH0_SREQ_FIFO_PFULL_NEGr = 2920, + SE_ALG_HASH0_INT_RSP_FIFO_PFULL_ASTr = 2921, + SE_ALG_HASH0_INT_RSP_FIFO_PFULL_NEGr = 2922, + SE_ALG_HASH0_EXT_RSP_FIFO_PFULL_ASTr = 2923, + SE_ALG_HASH0_EXT_RSP_FIFO_PFULL_NEGr = 2924, + SE_ALG_HASH1_KEY_FIFO_PFULL_ASTr = 2925, + SE_ALG_HASH1_KEY_FIFO_PFULL_NEGr = 2926, + SE_ALG_HASH1_SREQ_FIFO_PFULL_ASTr = 2927, + SE_ALG_HASH1_SREQ_FIFO_PFULL_NEGr = 2928, + SE_ALG_HASH1_INT_RSP_FIFO_PFULL_ASTr = 2929, + SE_ALG_HASH1_INT_RSP_FIFO_PFULL_NEGr = 2930, + SE_ALG_HASH1_EXT_RSP_FIFO_PFULL_ASTr = 2931, + SE_ALG_HASH1_EXT_RSP_FIFO_PFULL_NEGr = 2932, + SE_ALG_HASH2_KEY_FIFO_PFULL_ASTr = 2933, + SE_ALG_HASH2_KEY_FIFO_PFULL_NEGr = 2934, + SE_ALG_HASH2_SREQ_FIFO_PFULL_ASTr = 2935, + SE_ALG_HASH2_SREQ_FIFO_PFULL_NEGr = 2936, + SE_ALG_HASH2_INT_RSP_FIFO_PFULL_ASTr = 2937, + SE_ALG_HASH2_INT_RSP_FIFO_PFULL_NEGr = 2938, + SE_ALG_HASH2_EXT_RSP_FIFO_PFULL_ASTr = 2939, + SE_ALG_HASH2_EXT_RSP_FIFO_PFULL_NEGr = 2940, + SE_ALG_HASH3_KEY_FIFO_PFULL_ASTr = 2941, + SE_ALG_HASH3_KEY_FIFO_PFULL_NEGr = 2942, + SE_ALG_HASH3_SREQ_FIFO_PFULL_ASTr = 2943, + SE_ALG_HASH3_SREQ_FIFO_PFULL_NEGr = 2944, + SE_ALG_HASH3_INT_RSP_FIFO_PFULL_ASTr = 2945, + SE_ALG_HASH3_INT_RSP_FIFO_PFULL_NEGr = 2946, + SE_ALG_HASH3_EXT_RSP_FIFO_PFULL_ASTr = 2947, + SE_ALG_HASH3_EXT_RSP_FIFO_PFULL_NEGr = 2948, + SE_ALG_LPM_AS_INFOr = 2949, + SE_ALG_LPM_EXT_RSP_FIFO_U0_PFULL_NEGr = 2950, + SE_ALG_LPM_EXT_RSP_FIFO_U2_PFULL_ASTr = 2951, + SE_ALG_LPM_EXT_RSP_FIFO_U2_PFULL_NEGr = 2952, + SE_ALG_LPM_EXT_RSP_FIFO_U3_PFULL_ASTr = 2953, + SE_ALG_LPM_EXT_RSP_FIFO_U3_PFULL_NEGr = 2954, + SE_ALG_LPM_EXT_RSP_FIFO_U4_PFULL_ASTr = 2955, + SE_ALG_LPM_EXT_RSP_FIFO_U4_PFULL_NEGr = 2956, + SE_ALG_LPM_AS_RSP_FIFO_U0_PFULL_ASTr = 2957, + SE_ALG_LPM_AS_RSP_FIFO_U0_PFULL_NEGr = 2958, + SE_ALG_LPM_AS_RSP_FIFO_U1_PFULL_ASTr = 2959, + SE_ALG_LPM_AS_RSP_FIFO_U1_PFULL_NEGr = 2960, + SE_ALG_LPM_V4_DDR3_BASE_ADDRr = 2961, + SE_ALG_LPM_V6_DDR3_BASE_ADDRr = 2962, + SE_ALG_DEBUG_CNT_MODEr = 2963, + SE_ALG_HASH_P0_KEY_VLD_CNTr = 2964, + SE_ALG_HASH_P1_KEY_VLD_CNTr = 2965, + SE_ALG_HASH_P2_KEY_VLD_CNTr = 2966, + SE_ALG_HASH_P3_KEY_VLD_CNTr = 2967, + SE_ALG_LPM_P0_KEY_VLD_CNTr = 2968, + SE_ALG_HASH_P0_RSP_VLD_CNTr = 2969, + SE_ALG_HASH_P1_RSP_VLD_CNTr = 2970, + SE_ALG_HASH_P2_RSP_VLD_CNTr = 2971, + SE_ALG_HASH_P3_RSP_VLD_CNTr = 2972, + SE_ALG_LPM_P0_RSP_VLD_CNTr = 2973, + SE_ALG_HASH_P0_SMF_CNTr = 2974, + SE_ALG_HASH_P1_SMF_CNTr = 2975, + SE_ALG_HASH_P2_SMF_CNTr = 2976, + SE_ALG_HASH_P3_SMF_CNTr = 2977, + SE_ALG_LPM_P0_SMF_CNTr = 2978, + SE_ALG_HASH_P0_SPACEVLD_CNTr = 2979, + SE_ALG_HASH_P1_SPACEVLD_CNTr = 2980, + SE_ALG_HASH_P2_SPACEVLD_CNTr = 2981, + SE_ALG_HASH_P3_SPACEVLD_CNTr = 2982, + SE_ALG_SMMU1_P0_REQ_VLD_CNTr = 2983, + SE_ALG_SMMU1_P1_REQ_VLD_CNTr = 2984, + SE_ALG_SMMU1_P2_REQ_VLD_CNTr = 2985, + SE_ALG_SMMU1_P3_REQ_VLD_CNTr = 2986, + SE_ALG_SMMU1_P4_REQ_VLD_CNTr = 2987, + SE_ALG_SMMU1_P5_REQ_VLD_CNTr = 2988, + SE_ALG_SMMU1_P0_RSP_VLD_CNTr = 2989, + SE_ALG_SMMU1_P1_RSP_VLD_CNTr = 2990, + SE_ALG_SMMU1_P2_RSP_VLD_CNTr = 2991, + SE_ALG_SMMU1_P3_RSP_VLD_CNTr = 2992, + SE_ALG_SMMU1_P4_RSP_VLD_CNTr = 2993, + SE_ALG_SMMU1_P5_RSP_VLD_CNTr = 2994, + SE_ALG_SCHD_LEARN_FIFO_INT_CNTr = 2995, + SE_ALG_SCHD_HASH0_FIFO_INT_CNTr = 2996, + SE_ALG_SCHD_HASH1_FIFO_INT_CNTr = 2997, + SE_ALG_SCHD_HASH2_FIFO_INT_CNTr = 2998, + SE_ALG_SCHD_HASH3_FIFO_INT_CNTr = 2999, + SE_ALG_SCHD_LPM_FIFO_INT_CNTr = 3000, + SE_ALG_SCHD_LEARN_FIFO_PARITY_ERR_CNTr = 3001, + SE_ALG_SCHD_HASH0_FIFO_PARITY_ERR_CNTr = 3002, + SE_ALG_SCHD_HASH1_FIFO_PARITY_ERR_CNTr = 3003, + SE_ALG_SCHD_HASH2_FIFO_PARITY_ERR_CNTr = 3004, + SE_ALG_SCHD_HASH3_FIFO_PARITY_ERR_CNTr = 3005, + SE_ALG_SCHD_LPM_FIFO_PARITY_ERR_CNTr = 3006, + SE_ALG_RD_INIT_CFT_CNTr = 3007, + SE_ALG_ZGP0_ZBLK0_ECC_ERR_CNTr = 3008, + SE_ALG_ZGP0_ZBLK1_ECC_ERR_CNTr = 3009, + SE_ALG_ZGP0_ZBLK2_ECC_ERR_CNTr = 3010, + SE_ALG_ZGP0_ZBLK3_ECC_ERR_CNTr = 3011, + SE_ALG_ZGP0_ZBLK4_ECC_ERR_CNTr = 3012, + SE_ALG_ZGP0_ZBLK5_ECC_ERR_CNTr = 3013, + SE_ALG_ZGP0_ZBLK6_ECC_ERR_CNTr = 3014, + SE_ALG_ZGP0_ZBLK7_ECC_ERR_CNTr = 3015, + SE_ALG_ZGP1_ZBLK0_ECC_ERR_CNTr = 3016, + SE_ALG_ZGP1_ZBLK1_ECC_ERR_CNTr = 3017, + SE_ALG_ZGP1_ZBLK2_ECC_ERR_CNTr = 3018, + SE_ALG_ZGP1_ZBLK3_ECC_ERR_CNTr = 3019, + SE_ALG_ZGP1_ZBLK4_ECC_ERR_CNTr = 3020, + SE_ALG_ZGP1_ZBLK5_ECC_ERR_CNTr = 3021, + SE_ALG_ZGP1_ZBLK6_ECC_ERR_CNTr = 3022, + SE_ALG_ZGP1_ZBLK7_ECC_ERR_CNTr = 3023, + SE_ALG_ZGP2_ZBLK0_ECC_ERR_CNTr = 3024, + SE_ALG_ZGP2_ZBLK1_ECC_ERR_CNTr = 3025, + SE_ALG_ZGP2_ZBLK2_ECC_ERR_CNTr = 3026, + SE_ALG_ZGP2_ZBLK3_ECC_ERR_CNTr = 3027, + SE_ALG_ZGP2_ZBLK4_ECC_ERR_CNTr = 3028, + SE_ALG_ZGP2_ZBLK5_ECC_ERR_CNTr = 3029, + SE_ALG_ZGP2_ZBLK6_ECC_ERR_CNTr = 3030, + SE_ALG_ZGP2_ZBLK7_ECC_ERR_CNTr = 3031, + SE_ALG_ZGP3_ZBLK0_ECC_ERR_CNTr = 3032, + SE_ALG_ZGP3_ZBLK1_ECC_ERR_CNTr = 3033, + SE_ALG_ZGP3_ZBLK2_ECC_ERR_CNTr = 3034, + SE_ALG_ZGP3_ZBLK3_ECC_ERR_CNTr = 3035, + SE_ALG_ZGP3_ZBLK4_ECC_ERR_CNTr = 3036, + SE_ALG_ZGP3_ZBLK5_ECC_ERR_CNTr = 3037, + SE_ALG_ZGP3_ZBLK6_ECC_ERR_CNTr = 3038, + SE_ALG_ZGP3_ZBLK7_ECC_ERR_CNTr = 3039, + SE_ALG_ZCAM_HASH_P0_ERR_CNTr = 3040, + SE_ALG_ZCAM_HASH_P1_ERR_CNTr = 3041, + SE_ALG_ZCAM_HASH_P2_ERR_CNTr = 3042, + SE_ALG_ZCAM_HASH_P3_ERR_CNTr = 3043, + SE_ALG_ZCAM_LPM_ERR_CNTr = 3044, + SE_ALG_HASH0_SREQ_FIFO_PARITY_ERR_CNTr = 3045, + SE_ALG_HASH0_SREQ_FIFO_INT_CNTr = 3046, + SE_ALG_HASH0_KEY_FIFO_INT_CNTr = 3047, + SE_ALG_HASH0_INT_RSP_FIFO_PARITY_ERR_CNTr = 3048, + SE_ALG_HASH0_EXT_RSP_FIFO_PARITY_ERR_CNTr = 3049, + SE_ALG_HASH0_EXT_RSP_FIFO_INT_CNTr = 3050, + SE_ALG_HASH0_INT_RSP_FIFO_INT_CNTr = 3051, + SE_ALG_HASH1_SREQ_FIFO_PARITY_ERR_CNTr = 3052, + SE_ALG_HASH1_SREQ_FIFO_INT_CNTr = 3053, + SE_ALG_HASH1_KEY_FIFO_INT_CNTr = 3054, + SE_ALG_HASH1_INT_RSP_FIFO_PARITY_ERR_CNTr = 3055, + SE_ALG_HASH1_EXT_RSP_FIFO_PARITY_ERR_CNTr = 3056, + SE_ALG_HASH1_EXT_RSP_FIFO_INT_CNTr = 3057, + SE_ALG_HASH1_INT_RSP_FIFO_INT_CNTr = 3058, + SE_ALG_HASH2_SREQ_FIFO_PARITY_ERR_CNTr = 3059, + SE_ALG_HASH2_SREQ_FIFO_INT_CNTr = 3060, + SE_ALG_HASH2_KEY_FIFO_INT_CNTr = 3061, + SE_ALG_HASH2_INT_RSP_FIFO_PARITY_ERR_CNTr = 3062, + SE_ALG_HASH2_EXT_RSP_FIFO_PARITY_ERR_CNTr = 3063, + SE_ALG_HASH2_EXT_RSP_FIFO_INT_CNTr = 3064, + SE_ALG_HASH2_INT_RSP_FIFO_INT_CNTr = 3065, + SE_ALG_HASH3_SREQ_FIFO_PARITY_ERR_CNTr = 3066, + SE_ALG_HASH3_SREQ_FIFO_INT_CNTr = 3067, + SE_ALG_HASH3_KEY_FIFO_INT_CNTr = 3068, + SE_ALG_HASH3_INT_RSP_FIFO_PARITY_ERR_CNTr = 3069, + SE_ALG_HASH3_EXT_RSP_FIFO_PARITY_ERR_CNTr = 3070, + SE_ALG_HASH3_EXT_RSP_FIFO_INT_CNTr = 3071, + SE_ALG_HASH3_INT_RSP_FIFO_INT_CNTr = 3072, + SE_ALG_LPM_EXT_RSP_FIFO_INT_CNTr = 3073, + SE_ALG_LPM_EXT_V6_FIFO_INT_CNTr = 3074, + SE_ALG_LPM_EXT_V4_FIFO_INT_CNTr = 3075, + SE_ALG_LPM_EXT_ADDR_FIFO_INT_CNTr = 3076, + SE_ALG_LPM_EXT_V4_FIFO_PARITY_ERR_CNTr = 3077, + SE_ALG_LPM_EXT_V6_FIFO_PARITY_ERR_CNTr = 3078, + SE_ALG_LPM_EXT_RSP_FIFO_PARITY_ERR_CNTr = 3079, + SE_ALG_LPM_AS_REQ_FIFO_INT_CNTr = 3080, + SE_ALG_LPM_AS_INT_RSP_FIFO_INT_CNTr = 3081, + SE_ALG_SE_ALG_INT_STATUSr = 3082, + SE_ALG_SCHD_INT_ENr = 3083, + SE_ALG_SCHD_INT_MASKr = 3084, + SE_ALG_SCHD_INT_STATUSr = 3085, + SE_ALG_ZBLK_ECC_INT_ENr = 3086, + SE_ALG_ZBLK_ECC_INT_MASKr = 3087, + SE_ALG_ZBLK_ECC_INT_STATUSr = 3088, + SE_ALG_HASH0_INT_ENr = 3089, + SE_ALG_HASH0_INT_MASKr = 3090, + SE_ALG_HASH0_INT_STATUSr = 3091, + SE_ALG_HASH1_INT_ENr = 3092, + SE_ALG_HASH1_INT_MASKr = 3093, + SE_ALG_HASH1_INT_STATUSr = 3094, + SE_ALG_HASH2_INT_ENr = 3095, + SE_ALG_HASH2_INT_MASKr = 3096, + SE_ALG_HASH2_INT_STATUSr = 3097, + SE_ALG_HASH3_INT_ENr = 3098, + SE_ALG_HASH3_INT_MASKr = 3099, + SE_ALG_HASH3_INT_STATUSr = 3100, + SE_ALG_LPM_INT_ENr = 3101, + SE_ALG_LPM_INT_MASKr = 3102, + SE_ALG_LPM_INT_STATUSr = 3103, + SE_ALG_ZBLOCK_LPM_MASK0r = 3104, + SE_ALG_ZBLOCK_LPM_MASK1r = 3105, + SE_ALG_ZBLOCK_LPM_MASK2r = 3106, + SE_ALG_ZBLOCK_LPM_MASK3r = 3107, + SE_ALG_ZBLOCK_DEFAULT_ROUTE0r = 3108, + SE_ALG_ZBLOCK_DEFAULT_ROUTE1r = 3109, + SE_ALG_ZBLOCK_DEFAULT_ROUTE2r = 3110, + SE_ALG_ZBLOCK_DEFAULT_ROUTE3r = 3111, + SE_ALG_ZBLOCK_DEFAULT_ROUTE4r = 3112, + SE_ALG_ZBLOCK_DEFAULT_ROUTE5r = 3113, + SE_ALG_ZBLOCK_DEFAULT_ROUTE6r = 3114, + SE_ALG_ZBLOCK_DEFAULT_ROUTE7r = 3115, + SE_ALG_ZBLOCK_HASH_LISTTABLE_ITEM0r = 3116, + SE_ALG_ZBLOCK_HASH_LISTTABLE_ITEM1r = 3117, + SE_ALG_ZBLOCK_HASH_LISTTABLE_ITEM2r = 3118, + SE_ALG_ZBLOCK_HASH_LISTTABLE_ITEM3r = 3119, + SE_ALG_ZBLOCK_ECC_ERR_STATUSr = 3120, + SE_ALG_ZBLOCK_LPM_V6_SRAM_CMPr = 3121, + SE_ALG_ZBLOCK_LPM_V4_SRAM_CMPr = 3122, + SE_PARSER_KSCHD_PFUL_CFGr = 3123, + SE_PARSER_DEBUG_CNT_MODEr = 3124, + SE_PARSER_PARSER_INT_ENr = 3125, + SE_PARSER_PARSER_INT_MASKr = 3126, + SE_PARSER_PARSER_INT_STATUSr = 3127, + SE_PARSER_PARSER_INT_UNMASK_FLAGr = 3128, + SE_PARSER_ECC_BYPASS_READr = 3129, + SE_PARSER_MEX0_5_REQ_CNTr = 3130, + SE_PARSER_KSCHD_REQ0_5_CNTr = 3131, + SE_PARSER_KSCHD_PARSER_FC0_5_CNTr = 3132, + SE_PARSER_SE_PPU_MEX0_5_FC_CNTr = 3133, + SE_PARSER_SMMU0_MARC_FC_CNTr = 3134, + SE_PARSER_SMMU0_MARC_KEY_CNTr = 3135, + SE_PARSER_CMMU_KEY_CNTr = 3136, + SE_PARSER_CMMU_PARSER_FC_CNTr = 3137, + SE_PARSER_MARC_TAB_TYPE_ERR_MEX0_5_CNTr = 3138, + SE_PARSER_ERAM_FULLADDR_DROP_CNTr = 3139, + SE_AS_HASH0_PFUL_CFGr = 3140, + SE_AS_HASH1_PFUL_CFGr = 3141, + SE_AS_HASH2_PFUL_CFGr = 3142, + SE_AS_HASH3_PFUL_CFGr = 3143, + SE_AS_PBU_PFUL_CFGr = 3144, + SE_AS_LPM_PFUL_CFGr = 3145, + SE_AS_ETCAM_PFUL_CFGr = 3146, + SE_AS_AS_LEARN0_FIFO_CFGr = 3147, + SE_AS_AS_LEARN1_FIFO_CFGr = 3148, + SE_AS_AS_DMA_FIFO_CFGr = 3149, + SE_AS_AGE_PFUL_CFGr = 3150, + SE_AS_ETCAM_RSP_CFGr = 3151, + SE_AS_PBU_ECC_BYPASS_READr = 3152, + SE_AS_ETCAM0_ECC_BYPASS_READr = 3153, + SE_AS_ETCAM1_ECC_BYPASS_READr = 3154, + SE_AS_LPM_ECC_BYPASS_READr = 3155, + SE_AS_HASH_ECC_BYPASS_READr = 3156, + SE_AS_HASH_LEARN_ECC_BYPASS_READr = 3157, + SE_AS_DEBUG_CNT_MODEr = 3158, + SE_AS_AS_INT_0_ENr = 3159, + SE_AS_AS_INT_0_MASKr = 3160, + SE_AS_AS_INT_1_ENr = 3161, + SE_AS_AS_INT_1_MASKr = 3162, + SE_AS_AS_INT_2_ENr = 3163, + SE_AS_AS_INT_2_MASKr = 3164, + SE_AS_AS_INT_0_STATUSr = 3165, + SE_AS_AS_INT_1_STATUSr = 3166, + SE_AS_AS_INT_2_STATUSr = 3167, + SE_AS_SE_AS_INT_STATUSr = 3168, + SE_AS_HASH0_3_WR_REQ_CNTr = 3169, + SE_AS_SMMU0_ETCAM0_1_FC_CNTr = 3170, + SE_AS_ETCAM0_1_SMMU0_REQ_CNTr = 3171, + SE_AS_SMMU0_ETCAM0_1_RSP_CNTr = 3172, + SE_AS_AS_HLA_HASH_P0_3_KEY_CNTr = 3173, + SE_AS_AS_HLA_LPM_P0_KEY_CNTr = 3174, + SE_AS_ALG_AS_HASH_P0_3_RSP_CNTr = 3175, + SE_AS_ALG_AS_HASH_P0_3_SMF_RSP_CNTr = 3176, + SE_AS_ALG_AS_LPM_P0_RSP_CNTr = 3177, + SE_AS_ALG_AS_LPM_P0_3_SMF_RSP_CNTr = 3178, + SE_AS_AS_PBU_KEY_CNTr = 3179, + SE_AS_PBU_SE_DPI_RSP_DAT_CNTr = 3180, + SE_AS_AS_ETCAM_CTRL_REQ0_CNTr = 3181, + SE_AS_ETCAM_CTRL_AS_INDEX0_1_CNTr = 3182, + SE_AS_ETCAM_CTRL_AS_HIT0_1_CNTr = 3183, + SE_AS_AS_SMMU0_REQ_CNTr = 3184, + SE_AS_LEARN_HLA_WR_CNTr = 3185, + SE_AS_AS_SMMU1_REQ_CNTr = 3186, + SE_AS_SE_CFG_MAC_DAT_CNTr = 3187, + SE_AS_ALG_AS_HASH_P0_3_FC_CNTr = 3188, + SE_AS_ALG_AS_LPM_P0_FC_CNTr = 3189, + SE_AS_AS_ALG_HASH_P0_3_FC_CNTr = 3190, + SE_AS_AS_ALG_LPM_P0_FC_CNTr = 3191, + SE_AS_AS_PBU_FC_CNTr = 3192, + SE_AS_PBU_SE_DPI_KEY_FC_CNTr = 3193, + SE_AS_AS_ETCAM_CTRL_FC0_1_CNTr = 3194, + SE_AS_ETCAM_CTRL_AS_FC0_1_CNTr = 3195, + SE_AS_SMMU0_AS_MAC_AGE_FC_CNTr = 3196, + SE_AS_ALG_LEARN_FC_CNTr = 3197, + SE_AS_SMMU1_AS_FC_CNTr = 3198, + SE_AS_CFG_SE_MAC_FC_CNTr = 3199, + SE_KSCHD_KSCHD_CPU_RDYr = 3200, + SE_KSCHD_PPU0_ECC_BYPASS_READr = 3201, + SE_KSCHD_PBU_ECC_BYPASS_READr = 3202, + SE_KSCHD_SMMU1_ECC_BYPASS_READr = 3203, + SE_KSCHD_ASS_ECC_BYPASS_READr = 3204, + SE_KSCHD_SDT_Hr = 3205, + SE_KSCHD_SDT_Lr = 3206, + SE_KSCHD_HASH_KEY15r = 3207, + SE_KSCHD_HASH_KEY14r = 3208, + SE_KSCHD_HASH_KEY13r = 3209, + SE_KSCHD_HASH_KEY12r = 3210, + SE_KSCHD_HASH_KEY11r = 3211, + SE_KSCHD_HASH_KEY10r = 3212, + SE_KSCHD_HASH_KEY9r = 3213, + SE_KSCHD_HASH_KEY8r = 3214, + SE_KSCHD_HASH_KEY7r = 3215, + SE_KSCHD_HASH_KEY6r = 3216, + SE_KSCHD_HASH_KEY5r = 3217, + SE_KSCHD_HASH_KEY4r = 3218, + SE_KSCHD_HASH_KEY3r = 3219, + SE_KSCHD_HASH_KEY2r = 3220, + SE_KSCHD_HASH_KEY1r = 3221, + SE_KSCHD_HASH_KEY0r = 3222, + SE_KSCHD_SCHD_INT_0_ENr = 3223, + SE_KSCHD_SCHD_INT_0_MASKr = 3224, + SE_KSCHD_SCHD_INT_1_ENr = 3225, + SE_KSCHD_SCHD_INT_1_MASKr = 3226, + SE_KSCHD_SCHD_INT_2_ENr = 3227, + SE_KSCHD_SCHD_INT_2_MASKr = 3228, + SE_KSCHD_SCHD_INT_3_ENr = 3229, + SE_KSCHD_SCHD_INT_3_MASKr = 3230, + SE_KSCHD_SCHD_INT_4_ENr = 3231, + SE_KSCHD_SCHD_INT_4_MASKr = 3232, + SE_KSCHD_SCHD_INT_0_STATUSr = 3233, + SE_KSCHD_SCHD_INT_1_STATUSr = 3234, + SE_KSCHD_SCHD_INT_2_STATUSr = 3235, + SE_KSCHD_SCHD_INT_3_STATUSr = 3236, + SE_KSCHD_SCHD_INT_4_STATUSr = 3237, + SE_KSCHD_SE_KSCHD_INT_STATUSr = 3238, + SE_KSCHD_DEBUG_CNT_MODEr = 3239, + SE_KSCHD_SE_PARSER_KSCHD_KEY0_3_CNTr = 3240, + SE_KSCHD_SE_SMMU1_KEY0_3_CNTr = 3241, + SE_KSCHD_KSCHD_AS_KEY0_CNTr = 3242, + SE_KSCHD_KSCHD_AS_KEY1_CNTr = 3243, + SE_KSCHD_KSCHD_AS_KEY2_CNTr = 3244, + SE_KSCHD_KSCHD_AS_KEY3_CNTr = 3245, + SE_KSCHD_KSCHD_AS_KEY4_CNTr = 3246, + SE_KSCHD_KSCHD_AS_KEY5_CNTr = 3247, + SE_KSCHD_KSCHD_AS_KEY6_CNTr = 3248, + SE_KSCHD_KSCHD_AS_KEY9_CNTr = 3249, + SE_KSCHD_KSCHD_SE_PARSER_FC0_3_CNTr = 3250, + SE_KSCHD_SMMU1_SE_FC0_3_CNTr = 3251, + SE_KSCHD_AS_KSCHD_FC_CNT0r = 3252, + SE_KSCHD_AS_KSCHD_FC_CNT1r = 3253, + SE_KSCHD_AS_KSCHD_FC_CNT2r = 3254, + SE_KSCHD_AS_KSCHD_FC_CNT3r = 3255, + SE_KSCHD_AS_KSCHD_FC_CNT4r = 3256, + SE_KSCHD_AS_KSCHD_FC_CNT5r = 3257, + SE_KSCHD_AS_KSCHD_FC_CNT6r = 3258, + SE_KSCHD_AS_KSCHD_FC_CNT9r = 3259, + SE_RSCHD_RSCHD_HASH_PFUL_CFGr = 3260, + SE_RSCHD_RSCHD_HASH_EPT_CFGr = 3261, + SE_RSCHD_RSCHD_PBU_PFUL_CFGr = 3262, + SE_RSCHD_RSCHD_PBU_EPT_CFGr = 3263, + SE_RSCHD_RSCHD_LPM_PFUL_CFGr = 3264, + SE_RSCHD_RSCHD_LPM_EPT_CFGr = 3265, + SE_RSCHD_RSCHD_ETCAM_PFUL_CFGr = 3266, + SE_RSCHD_RSCHD_ETCAM_EPT_CFGr = 3267, + SE_RSCHD_SMMU0_WB_PFUL_CFGr = 3268, + SE_RSCHD_SMMU0_WB_EPT_CFGr = 3269, + SE_RSCHD_SMMU1_WB_PFUL_CFGr = 3270, + SE_RSCHD_SMMU1_WB_EPT_CFGr = 3271, + SE_RSCHD_ALG_WB_PFUL_CFGr = 3272, + SE_RSCHD_ALG_WB_EPT_CFGr = 3273, + SE_RSCHD_WR_RSP_VLD_ENr = 3274, + SE_RSCHD_NPPU_WB_PFUL_CFGr = 3275, + SE_RSCHD_NPPU_WB_EPT_CFGr = 3276, + SE_RSCHD_PORT0_INT_ENr = 3277, + SE_RSCHD_PORT0_INT_MASKr = 3278, + SE_RSCHD_PORT1_INT_ENr = 3279, + SE_RSCHD_PORT1_INT_MASKr = 3280, + SE_RSCHD_PORT0_INT_STATUSr = 3281, + SE_RSCHD_PORT1_INT_STATUSr = 3282, + SE_RSCHD_SE_RSCHD_INT_STATUSr = 3283, + SE_RSCHD_DEBUG_CNT_MODEr = 3284, + SE_RSCHD_SE_PPU_MEX0_5_RSP1_CNTr = 3285, + SE_RSCHD_AS_RSCHD_RSP0_CNTr = 3286, + SE_RSCHD_AS_RSCHD_RSP1_CNTr = 3287, + SE_RSCHD_AS_RSCHD_RSP2_CNTr = 3288, + SE_RSCHD_AS_RSCHD_RSP3_CNTr = 3289, + SE_RSCHD_AS_RSCHD_RSP4_CNTr = 3290, + SE_RSCHD_AS_RSCHD_RSP5_CNTr = 3291, + SE_RSCHD_AS_RSCHD_RSP6_CNTr = 3292, + SE_RSCHD_AS_RSCHD_RSP9_CNTr = 3293, + SE_RSCHD_SMMU1_SE_RSP0_3_CNTr = 3294, + SE_RSCHD_PPU_SE_MEX0_3_FC_CNTr = 3295, + SE_RSCHD_RSCHD_AS_FC_CNT0r = 3296, + SE_RSCHD_RSCHD_AS_FC_CNT1r = 3297, + SE_RSCHD_RSCHD_AS_FC_CNT2r = 3298, + SE_RSCHD_RSCHD_AS_FC_CNT3r = 3299, + SE_RSCHD_RSCHD_AS_FC_CNT4r = 3300, + SE_RSCHD_RSCHD_AS_FC_CNT5r = 3301, + SE_RSCHD_RSCHD_AS_FC_CNT6r = 3302, + SE_RSCHD_RSCHD_AS_FC_CNT9r = 3303, + SE_RSCHD_SE_SMMU1_FC0_3_CNTr = 3304, + SE_RSCHD_SMMU0_SE_WR_DONE_CNTr = 3305, + SE_RSCHD_SE_SMMU0_WR_DONE_FC_CNTr = 3306, + SE_RSCHD_SMMU1_SE_WR_RSP_CNTr = 3307, + SE_RSCHD_SE_SMMU1_WR_RSP_FC_CNTr = 3308, + SE_RSCHD_ALG_SE_WR_RSP_CNTr = 3309, + SE_RSCHD_SE_ALG_WR_RSP_FC_CNTr = 3310, + SMMU0_SMMU0_KSCHD_PFUL_CFG0r = 3311, + SMMU0_SMMU0_KSCHD_PFUL_CFG1r = 3312, + SMMU0_SMMU0_CTRL_PFUL1_CFGr = 3313, + SMMU0_SMMU0_CTRL_PFUL2_CFGr = 3314, + SMMU0_SMMU0_CTRL_PFUL3_CFGr = 3315, + SMMU0_SMMU0_RSCHD_PFUL_CFGr = 3316, + SMMU0_SMMU0_RSCHD_EPT_CFGr = 3317, + SMMU0_SMMU0_ALUCMD_PFUL_CFGr = 3318, + SMMU0_SMMU0_ALUWR_PFUL_CFGr = 3319, + SMMU0_SMMU0_WR_ARB_PFUL_CFG0r = 3320, + SMMU0_SMMU0_WR_ARB_PFUL_CFG1r = 3321, + SMMU0_SMMU0_ORD_PFUL_CFGr = 3322, + SMMU0_SMMU0_CFG_DMA_BADDRr = 3323, + SMMU0_SMMU0_CFG_ODMA0_BADDRr = 3324, + SMMU0_SMMU0_CFG_ODMA1_BADDRr = 3325, + SMMU0_SMMU0_CFG_ODMA2_BADDRr = 3326, + SMMU0_SMMU0_CFG_ODMA_TDM_BADDRr = 3327, + SMMU0_SMMU0_CFG_MCAST_BADDRr = 3328, + SMMU0_SMMU0_CFG_LPM0r = 3329, + SMMU0_SMMU0_CFG_LPM1r = 3330, + SMMU0_SMMU0_CFG_LPM2r = 3331, + SMMU0_SMMU0_CFG_LPM3r = 3332, + SMMU0_SMMU0_CFG_LPM4r = 3333, + SMMU0_SMMU0_CFG_LPM5r = 3334, + SMMU0_SMMU0_CFG_LPM6r = 3335, + SMMU0_SMMU0_CFG_LPM7r = 3336, + SMMU0_SMMU0_DEBUG_CNT_MODEr = 3337, + SMMU0_SMMU0_STAT_OVERFLOW_MODEr = 3338, + SMMU0_SMMU0_INIT_EN_CFG_TMPr = 3339, + SMMU0_SMMU0_SMMU0_INT_UNMASK_FLAGr = 3340, + SMMU0_SMMU0_SMMU0_INT0_ENr = 3341, + SMMU0_SMMU0_SMMU0_INT0_MASKr = 3342, + SMMU0_SMMU0_SMMU0_INT0_STATUSr = 3343, + SMMU0_SMMU0_SMMU0_INT1_ENr = 3344, + SMMU0_SMMU0_SMMU0_INT1_MASKr = 3345, + SMMU0_SMMU0_SMMU0_INT1_STATUSr = 3346, + SMMU0_SMMU0_SMMU0_INT2_ENr = 3347, + SMMU0_SMMU0_SMMU0_INT2_MASKr = 3348, + SMMU0_SMMU0_SMMU0_INT2_STATUSr = 3349, + SMMU0_SMMU0_SMMU0_INT3_ENr = 3350, + SMMU0_SMMU0_SMMU0_INT3_MASKr = 3351, + SMMU0_SMMU0_SMMU0_INT3_STATUSr = 3352, + SMMU0_SMMU0_SMMU0_INT4_ENr = 3353, + SMMU0_SMMU0_SMMU0_INT4_MASKr = 3354, + SMMU0_SMMU0_SMMU0_INT4_STATUSr = 3355, + SMMU0_SMMU0_SMMU0_INT5_ENr = 3356, + SMMU0_SMMU0_SMMU0_INT5_MASKr = 3357, + SMMU0_SMMU0_SMMU0_INT5_STATUSr = 3358, + SMMU0_SMMU0_SMMU0_INT6_ENr = 3359, + SMMU0_SMMU0_SMMU0_INT6_MASKr = 3360, + SMMU0_SMMU0_SMMU0_INT6_STATUSr = 3361, + SMMU0_SMMU0_SMMU0_INT7_ENr = 3362, + SMMU0_SMMU0_SMMU0_INT7_MASKr = 3363, + SMMU0_SMMU0_SMMU0_INT7_STATUSr = 3364, + SMMU0_SMMU0_SMMU0_INT8_ENr = 3365, + SMMU0_SMMU0_SMMU0_INT8_MASKr = 3366, + SMMU0_SMMU0_SMMU0_INT8_STATUSr = 3367, + SMMU0_SMMU0_SMMU0_INT9_ENr = 3368, + SMMU0_SMMU0_SMMU0_INT9_MASKr = 3369, + SMMU0_SMMU0_SMMU0_INT9_STATUSr = 3370, + SMMU0_SMMU0_SMMU0_INT10_ENr = 3371, + SMMU0_SMMU0_SMMU0_INT10_MASKr = 3372, + SMMU0_SMMU0_SMMU0_INT10_STATUSr = 3373, + SMMU0_SMMU0_SMMU0_INT11_ENr = 3374, + SMMU0_SMMU0_SMMU0_INT11_MASKr = 3375, + SMMU0_SMMU0_SMMU0_INT11_STATUSr = 3376, + SMMU0_SMMU0_SMMU0_INT12_ENr = 3377, + SMMU0_SMMU0_SMMU0_INT12_MASKr = 3378, + SMMU0_SMMU0_SMMU0_INT12_STATUSr = 3379, + SMMU0_SMMU0_SMMU0_INT13_ENr = 3380, + SMMU0_SMMU0_SMMU0_INT13_MASKr = 3381, + SMMU0_SMMU0_SMMU0_INT13_STATUSr = 3382, + SMMU0_SMMU0_SMMU0_INT14_ENr = 3383, + SMMU0_SMMU0_SMMU0_INT14_MASKr = 3384, + SMMU0_SMMU0_SMMU0_INT14_STATUSr = 3385, + SMMU0_SMMU0_SMMU0_ECC_UNMASK_FLAGr = 3386, + SMMU0_SMMU0_SMMU0_INT15_ENr = 3387, + SMMU0_SMMU0_SMMU0_INT15_MASKr = 3388, + SMMU0_SMMU0_SMMU0_INT15_STATUSr = 3389, + SMMU0_SMMU0_SMMU0_INT16_ENr = 3390, + SMMU0_SMMU0_SMMU0_INT16_MASKr = 3391, + SMMU0_SMMU0_SMMU0_INT16_STATUSr = 3392, + SMMU0_SMMU0_SMMU0_INT17_ENr = 3393, + SMMU0_SMMU0_SMMU0_INT17_MASKr = 3394, + SMMU0_SMMU0_SMMU0_INT17_STATUSr = 3395, + SMMU0_SMMU0_SMMU0_INT18_ENr = 3396, + SMMU0_SMMU0_SMMU0_INT18_MASKr = 3397, + SMMU0_SMMU0_SMMU0_INT18_STATUSr = 3398, + SMMU0_SMMU0_SMMU0_INT19_ENr = 3399, + SMMU0_SMMU0_SMMU0_INT19_MASKr = 3400, + SMMU0_SMMU0_SMMU0_INT19_STATUSr = 3401, + SMMU0_SMMU0_SMMU0_INT20_ENr = 3402, + SMMU0_SMMU0_SMMU0_INT20_MASKr = 3403, + SMMU0_SMMU0_SMMU0_INT20_STATUSr = 3404, + SMMU0_SMMU0_SMMU0_INT21_ENr = 3405, + SMMU0_SMMU0_SMMU0_INT21_MASKr = 3406, + SMMU0_SMMU0_SMMU0_INT21_STATUSr = 3407, + SMMU0_SMMU0_SMMU0_INT22_ENr = 3408, + SMMU0_SMMU0_SMMU0_INT22_MASKr = 3409, + SMMU0_SMMU0_SMMU0_INT22_STATUSr = 3410, + SMMU0_SMMU0_SMMU0_INT23_ENr = 3411, + SMMU0_SMMU0_SMMU0_INT23_MASKr = 3412, + SMMU0_SMMU0_SMMU0_INT23_STATUSr = 3413, + SMMU0_SMMU0_SMMU0_INT24_ENr = 3414, + SMMU0_SMMU0_SMMU0_INT24_MASKr = 3415, + SMMU0_SMMU0_SMMU0_INT24_STATUSr = 3416, + SMMU0_SMMU0_SMMU0_INT25_ENr = 3417, + SMMU0_SMMU0_SMMU0_INT25_MASKr = 3418, + SMMU0_SMMU0_SMMU0_INT25_STATUSr = 3419, + SMMU0_SMMU0_SMMU0_INT26_ENr = 3420, + SMMU0_SMMU0_SMMU0_INT26_MASKr = 3421, + SMMU0_SMMU0_SMMU0_INT26_STATUSr = 3422, + SMMU0_SMMU0_SMMU0_INT27_ENr = 3423, + SMMU0_SMMU0_SMMU0_INT27_MASKr = 3424, + SMMU0_SMMU0_SMMU0_INT27_STATUSr = 3425, + SMMU0_SMMU0_SMMU0_INT28_ENr = 3426, + SMMU0_SMMU0_SMMU0_INT28_MASKr = 3427, + SMMU0_SMMU0_SMMU0_INT28_STATUSr = 3428, + SMMU0_SMMU0_SMMU0_INT29_ENr = 3429, + SMMU0_SMMU0_SMMU0_INT29_MASKr = 3430, + SMMU0_SMMU0_SMMU0_INT29_STATUSr = 3431, + SMMU0_SMMU0_SMMU0_INT30_ENr = 3432, + SMMU0_SMMU0_SMMU0_INT30_MASKr = 3433, + SMMU0_SMMU0_SMMU0_INT30_STATUSr = 3434, + SMMU0_SMMU0_SMMU0_INT31_ENr = 3435, + SMMU0_SMMU0_SMMU0_INT31_MASKr = 3436, + SMMU0_SMMU0_SMMU0_INT31_STATUSr = 3437, + SMMU0_SMMU0_SMMU0_INT32_ENr = 3438, + SMMU0_SMMU0_SMMU0_INT32_MASKr = 3439, + SMMU0_SMMU0_SMMU0_INT32_STATUSr = 3440, + SMMU0_SMMU0_SMMU0_INT33_ENr = 3441, + SMMU0_SMMU0_SMMU0_INT33_MASKr = 3442, + SMMU0_SMMU0_SMMU0_INT33_STATUSr = 3443, + SMMU0_SMMU0_SMMU0_INT34_ENr = 3444, + SMMU0_SMMU0_SMMU0_INT34_MASKr = 3445, + SMMU0_SMMU0_SMMU0_INT34_STATUSr = 3446, + SMMU0_SMMU0_SMMU0_INT35_ENr = 3447, + SMMU0_SMMU0_SMMU0_INT35_MASKr = 3448, + SMMU0_SMMU0_SMMU0_INT35_STATUSr = 3449, + SMMU0_SMMU0_SMMU0_INT36_ENr = 3450, + SMMU0_SMMU0_SMMU0_INT36_MASKr = 3451, + SMMU0_SMMU0_SMMU0_INT36_STATUSr = 3452, + SMMU0_SMMU0_SMMU0_INT37_ENr = 3453, + SMMU0_SMMU0_SMMU0_INT37_MASKr = 3454, + SMMU0_SMMU0_SMMU0_INT37_STATUSr = 3455, + SMMU0_SMMU0_SMMU0_INT38_ENr = 3456, + SMMU0_SMMU0_SMMU0_INT38_MASKr = 3457, + SMMU0_SMMU0_SMMU0_INT38_STATUSr = 3458, + SMMU0_SMMU0_SMMU0_INT39_ENr = 3459, + SMMU0_SMMU0_SMMU0_INT39_MASKr = 3460, + SMMU0_SMMU0_SMMU0_INT39_STATUSr = 3461, + SMMU0_SMMU0_SMMU0_INT40_ENr = 3462, + SMMU0_SMMU0_SMMU0_INT40_MASKr = 3463, + SMMU0_SMMU0_SMMU0_INT40_STATUSr = 3464, + SMMU0_SMMU0_SMMU0_INT41_ENr = 3465, + SMMU0_SMMU0_SMMU0_INT41_MASKr = 3466, + SMMU0_SMMU0_SMMU0_INT41_STATUSr = 3467, + SMMU0_SMMU0_SMMU0_INT42_ENr = 3468, + SMMU0_SMMU0_SMMU0_INT42_MASKr = 3469, + SMMU0_SMMU0_SMMU0_INT42_STATUSr = 3470, + SMMU0_SMMU0_SMMU0_INT43_ENr = 3471, + SMMU0_SMMU0_SMMU0_INT43_MASKr = 3472, + SMMU0_SMMU0_SMMU0_INT43_STATUSr = 3473, + SMMU0_SMMU0_SMMU0_INT44_ENr = 3474, + SMMU0_SMMU0_SMMU0_INT44_MASKr = 3475, + SMMU0_SMMU0_SMMU0_INT44_STATUSr = 3476, + SMMU0_SMMU0_SMMU0_INT45_ENr = 3477, + SMMU0_SMMU0_SMMU0_INT45_MASKr = 3478, + SMMU0_SMMU0_SMMU0_INT45_STATUSr = 3479, + SMMU0_SMMU0_SMMU0_INT46_ENr = 3480, + SMMU0_SMMU0_SMMU0_INT46_MASKr = 3481, + SMMU0_SMMU0_SMMU0_INT46_STATUSr = 3482, + SMMU0_SMMU0_SMMU0_INT47_ENr = 3483, + SMMU0_SMMU0_SMMU0_INT47_MASKr = 3484, + SMMU0_SMMU0_SMMU0_INT47_STATUSr = 3485, + SMMU0_SMMU0_SMMU0_INT48_ENr = 3486, + SMMU0_SMMU0_SMMU0_INT48_MASKr = 3487, + SMMU0_SMMU0_SMMU0_INT48_STATUSr = 3488, + SMMU0_SMMU0_SMMU0_INT49_ENr = 3489, + SMMU0_SMMU0_SMMU0_INT49_MASKr = 3490, + SMMU0_SMMU0_SMMU0_INT49_STATUSr = 3491, + SMMU0_SMMU0_SMMU0_INT50_ENr = 3492, + SMMU0_SMMU0_SMMU0_INT50_MASKr = 3493, + SMMU0_SMMU0_SMMU0_INT50_STATUSr = 3494, + SMMU0_SMMU0_SMMU0_INT51_ENr = 3495, + SMMU0_SMMU0_SMMU0_INT51_MASKr = 3496, + SMMU0_SMMU0_SMMU0_INT51_STATUSr = 3497, + SMMU0_SMMU0_SMMU0_INT52_ENr = 3498, + SMMU0_SMMU0_SMMU0_INT52_MASKr = 3499, + SMMU0_SMMU0_SMMU0_INT52_STATUSr = 3500, + SMMU0_SMMU0_SMMU0_INT53_ENr = 3501, + SMMU0_SMMU0_SMMU0_INT53_MASKr = 3502, + SMMU0_SMMU0_SMMU0_INT53_STATUSr = 3503, + SMMU0_SMMU0_CTRL0_ARBITER_ECC_BYPASSr = 3504, + SMMU0_SMMU0_CTRL2_ARBITER_ECC_BYPASSr = 3505, + SMMU0_SMMU0_CTRL4_ARBITER_ECC_BYPASSr = 3506, + SMMU0_SMMU0_CTRL6_ARBITER_ECC_BYPASSr = 3507, + SMMU0_SMMU0_CTRL8_ARBITER_ECC_BYPASSr = 3508, + SMMU0_SMMU0_CTRL10_ARBITER_ECC_BYPASSr = 3509, + SMMU0_SMMU0_CTRL12_ARBITER_ECC_BYPASSr = 3510, + SMMU0_SMMU0_CTRL14_ARBITER_ECC_BYPASSr = 3511, + SMMU0_SMMU0_CTRL16_ARBITER_ECC_BYPASSr = 3512, + SMMU0_SMMU0_CTRL18_ARBITER_ECC_BYPASSr = 3513, + SMMU0_SMMU0_CTRL20_ARBITER_ECC_BYPASSr = 3514, + SMMU0_SMMU0_CTRL22_ARBITER_ECC_BYPASSr = 3515, + SMMU0_SMMU0_CTRL24_ARBITER_ECC_BYPASSr = 3516, + SMMU0_SMMU0_CTRL26_ARBITER_ECC_BYPASSr = 3517, + SMMU0_SMMU0_CTRL28_ARBITER_ECC_BYPASSr = 3518, + SMMU0_SMMU0_CTRL30_ARBITER_ECC_BYPASSr = 3519, + SMMU0_SMMU0_CTRL_REQ_ECC_BYPASSr = 3520, + SMMU0_SMMU0_CTRL_INFO_ECC_BYPASSr = 3521, + SMMU0_SMMU0_SMMU0_RSCHD_ECC_BYPASSr = 3522, + SMMU0_SMMU0_SMMU0_WR_ECC_BYPASSr = 3523, + SMMU0_SMMU0_CTRL0_ARBITER_ECC_ERRr = 3524, + SMMU0_SMMU0_CTRL1_ARBITER_ECC_ERRr = 3525, + SMMU0_SMMU0_CTRL2_ARBITER_ECC_ERRr = 3526, + SMMU0_SMMU0_CTRL3_ARBITER_ECC_ERRr = 3527, + SMMU0_SMMU0_CTRL4_ARBITER_ECC_ERRr = 3528, + SMMU0_SMMU0_CTRL5_ARBITER_ECC_ERRr = 3529, + SMMU0_SMMU0_CTRL6_ARBITER_ECC_ERRr = 3530, + SMMU0_SMMU0_CTRL7_ARBITER_ECC_ERRr = 3531, + SMMU0_SMMU0_CTRL8_ARBITER_ECC_ERRr = 3532, + SMMU0_SMMU0_CTRL9_ARBITER_ECC_ERRr = 3533, + SMMU0_SMMU0_CTRL10_ARBITER_ECC_ERRr = 3534, + SMMU0_SMMU0_CTRL11_ARBITER_ECC_ERRr = 3535, + SMMU0_SMMU0_CTRL12_ARBITER_ECC_ERRr = 3536, + SMMU0_SMMU0_CTRL13_ARBITER_ECC_ERRr = 3537, + SMMU0_SMMU0_CTRL14_ARBITER_ECC_ERRr = 3538, + SMMU0_SMMU0_CTRL15_ARBITER_ECC_ERRr = 3539, + SMMU0_SMMU0_CTRL16_ARBITER_ECC_ERRr = 3540, + SMMU0_SMMU0_CTRL17_ARBITER_ECC_ERRr = 3541, + SMMU0_SMMU0_CTRL18_ARBITER_ECC_ERRr = 3542, + SMMU0_SMMU0_CTRL19_ARBITER_ECC_ERRr = 3543, + SMMU0_SMMU0_CTRL20_ARBITER_ECC_ERRr = 3544, + SMMU0_SMMU0_CTRL21_ARBITER_ECC_ERRr = 3545, + SMMU0_SMMU0_CTRL22_ARBITER_ECC_ERRr = 3546, + SMMU0_SMMU0_CTRL23_ARBITER_ECC_ERRr = 3547, + SMMU0_SMMU0_CTRL24_ARBITER_ECC_ERRr = 3548, + SMMU0_SMMU0_CTRL25_ARBITER_ECC_ERRr = 3549, + SMMU0_SMMU0_CTRL26_ARBITER_ECC_ERRr = 3550, + SMMU0_SMMU0_CTRL27_ARBITER_ECC_ERRr = 3551, + SMMU0_SMMU0_CTRL28_ARBITER_ECC_ERRr = 3552, + SMMU0_SMMU0_CTRL29_ARBITER_ECC_ERRr = 3553, + SMMU0_SMMU0_CTRL30_ARBITER_ECC_ERRr = 3554, + SMMU0_SMMU0_CTRL31_ARBITER_ECC_ERRr = 3555, + SMMU0_SMMU0_CTRL_REQ_ECC_SINGLE_ERRr = 3556, + SMMU0_SMMU0_CTRL_REQ_ECC_DOUBLE_ERRr = 3557, + SMMU0_SMMU0_CTRL_INFO_ECC_SINGLE_ERRr = 3558, + SMMU0_SMMU0_CTRL_INFO_ECC_DOUBLE_ERRr = 3559, + SMMU0_SMMU0_SMMU0_WR_ECC_ERRr = 3560, + SMMU0_SMMU0_SMMU0_RSCHD_ECC_SINGLE_ERRr = 3561, + SMMU0_SMMU0_SMMU0_RSCHD_ECC_DOUBLE_ERRr = 3562, + SMMU0_SMMU0_ORD_FIFO_EMPTYr = 3563, + SMMU0_SMMU0_WR_ARB_FIFO_EMPTYr = 3564, + SMMU0_SMMU0_CTRL_FIFO_EMPTY0r = 3565, + SMMU0_SMMU0_CTRL_FIFO_EMPTY1r = 3566, + SMMU0_SMMU0_CTRL_FIFO_EMPTY2r = 3567, + SMMU0_SMMU0_CTRL_FIFO_EMPTY3r = 3568, + SMMU0_SMMU0_CTRL_FIFO_EMPTY4r = 3569, + SMMU0_SMMU0_CTRL_FIFO_EMPTY5r = 3570, + SMMU0_SMMU0_KSCHD_FIFO_EMPTY0r = 3571, + SMMU0_SMMU0_KSCHD_FIFO_EMPTY1r = 3572, + SMMU0_SMMU0_KSCHD_FIFO_EMPTY2r = 3573, + SMMU0_SMMU0_KSCHD_FIFO_EMPTY3r = 3574, + SMMU0_SMMU0_KSCHD_FIFO_EMPTY4r = 3575, + SMMU0_SMMU0_KSCHD_FIFO_EMPTY5r = 3576, + SMMU0_SMMU0_KSCHD_FIFO_EMPTY6r = 3577, + SMMU0_SMMU0_KSCHD_FIFO_EMPTY7r = 3578, + SMMU0_SMMU0_KSCHD_FIFO_EMPTY8r = 3579, + SMMU0_SMMU0_KSCHD_FIFO_EMPTY9r = 3580, + SMMU0_SMMU0_KSCHD_FIFO_EMPTY10r = 3581, + SMMU0_SMMU0_KSCHD_FIFO_EMPTY11r = 3582, + SMMU0_SMMU0_KSCHD_FIFO_EMPTY12r = 3583, + SMMU0_SMMU0_KSCHD_FIFO_EMPTY13r = 3584, + SMMU0_SMMU0_KSCHD_FIFO_EMPTY14r = 3585, + SMMU0_SMMU0_KSCHD_FIFO_EMPTY15r = 3586, + SMMU0_SMMU0_KSCHD_FIFO_EMPTY16r = 3587, + SMMU0_SMMU0_KSCHD_FIFO_EMPTY17r = 3588, + SMMU0_SMMU0_KSCHD_FIFO_EMPTY18r = 3589, + SMMU0_SMMU0_KSCHD_FIFO_EMPTY19r = 3590, + SMMU0_SMMU0_KSCHD_FIFO_EMPTY20r = 3591, + SMMU0_SMMU0_KSCHD_FIFO_EMPTY21r = 3592, + SMMU0_SMMU0_KSCHD_FIFO_EMPTY22r = 3593, + SMMU0_SMMU0_KSCHD_FIFO_EMPTY23r = 3594, + SMMU0_SMMU0_KSCHD_FIFO_EMPTY24r = 3595, + SMMU0_SMMU0_KSCHD_FIFO_EMPTY25r = 3596, + SMMU0_SMMU0_KSCHD_FIFO_EMPTY26r = 3597, + SMMU0_SMMU0_KSCHD_FIFO_EMPTY27r = 3598, + SMMU0_SMMU0_KSCHD_FIFO_EMPTY28r = 3599, + SMMU0_SMMU0_KSCHD_FIFO_EMPTY29r = 3600, + SMMU0_SMMU0_KSCHD_FIFO_EMPTY30r = 3601, + SMMU0_SMMU0_KSCHD_FIFO_EMPTY31r = 3602, + SMMU0_SMMU0_RSCHD_FIFO_EMPTY0r = 3603, + SMMU0_SMMU0_RSCHD_FIFO_EMPTY1r = 3604, + SMMU0_SMMU0_RSCHD_FIFO_EMPTY2r = 3605, + SMMU0_SMMU0_RSCHD_FIFO_EMPTY3r = 3606, + SMMU0_SMMU0_RSCHD_FIFO_EMPTY4r = 3607, + SMMU0_SMMU0_RSCHD_FIFO_EMPTY5r = 3608, + SMMU0_SMMU0_RSCHD_FIFO_EMPTY6r = 3609, + SMMU0_SMMU0_RSCHD_FIFO_EMPTY7r = 3610, + SMMU0_SMMU0_RSCHD_FIFO_EMPTY8r = 3611, + SMMU0_SMMU0_RSCHD_FIFO_EMPTY9r = 3612, + SMMU0_SMMU0_RSCHD_FIFO_EMPTY10r = 3613, + SMMU0_SMMU0_RSCHD_FIFO_EMPTY11r = 3614, + SMMU0_SMMU0_RSCHD_FIFO_EMPTY12r = 3615, + SMMU0_SMMU0_RSCHD_FIFO_EMPTY13r = 3616, + SMMU0_SMMU0_RSCHD_FIFO_EMPTY14r = 3617, + SMMU0_SMMU0_RSCHD_FIFO_EMPTY15r = 3618, + SMMU0_SMMU0_RSCHD_FIFO_EMPTY16r = 3619, + SMMU0_SMMU0_RSCHD_FIFO_EMPTY17r = 3620, + SMMU0_SMMU0_RSCHD_FIFO_EMPTY18r = 3621, + SMMU0_SMMU0_RSCHD_FIFO_EMPTY19r = 3622, + SMMU0_SMMU0_RSCHD_FIFO_EMPTY20r = 3623, + SMMU0_SMMU0_RSCHD_FIFO_EMPTY21r = 3624, + SMMU0_SMMU0_RSCHD_FIFO_EMPTY22r = 3625, + SMMU0_SMMU0_RSCHD_FIFO_EMPTY23r = 3626, + SMMU0_SMMU0_RSCHD_FIFO_EMPTY24r = 3627, + SMMU0_SMMU0_RSCHD_FIFO_EMPTY25r = 3628, + SMMU0_SMMU0_RSCHD_FIFO_EMPTY26r = 3629, + SMMU0_SMMU0_RSCHD_FIFO_EMPTY27r = 3630, + SMMU0_SMMU0_RSCHD_FIFO_EMPTY28r = 3631, + SMMU0_SMMU0_RSCHD_FIFO_EMPTY29r = 3632, + SMMU0_SMMU0_RSCHD_FIFO_EMPTY30r = 3633, + SMMU0_SMMU0_RSCHD_FIFO_EMPTY31r = 3634, + SMMU0_SMMU0_EPT_FLAGr = 3635, + SMMU0_SMMU0_PPU_SOFT_RSTr = 3636, + SMMU0_SMMU0_SMMU0_AS_MAC_AGE_FC_CNTr = 3637, + SMMU0_SMMU0_SMMU0_MARC_SE_PARSER_FC_CNTr = 3638, + SMMU0_SMMU0_WR_ARB_CPU_FC_CNTr = 3639, + SMMU0_SMMU0_SMMU0_LPM_AS_FC_CNTr = 3640, + SMMU0_SMMU0_LPM_AS_SMMU0_FC_CNTr = 3641, + SMMU0_SMMU0_SMMU0_ETCAM1_0_AS_FC_CNTr = 3642, + SMMU0_SMMU0_AS_ETCAM1_0_SMMU0_FC_CNTr = 3643, + SMMU0_SMMU0_SMMU0_PPU_MCAST_FC_CNTr = 3644, + SMMU0_SMMU0_PPU_SMMU0_MCAST_FC_CNTr = 3645, + SMMU0_SMMU0_ODMA_SMMU0_TDM_FC_RSP_FC_CNTr = 3646, + SMMU0_SMMU0_SMMU0_ODMA_TDM_FC_KEY_FC_CNTr = 3647, + SMMU0_SMMU0_SMMU0_ODMA_FC_CNTr = 3648, + SMMU0_SMMU0_SMMU0_CFG_TAB_RD_FC_CNTr = 3649, + SMMU0_SMMU0_SMMU0_STAT_FC15_0_CNTr = 3650, + SMMU0_SMMU0_STAT_SMMU0_FC15_0_CNTr = 3651, + SMMU0_SMMU0_SMMU0_PPU_MEX5_0_FC_CNTr = 3652, + SMMU0_SMMU0_PPU_SMMU0_MEX5_0_FC_CNTr = 3653, + SMMU0_SMMU0_AS_SMMU0_MAC_AGE_REQ_CNTr = 3654, + SMMU0_SMMU0_SE_PARSER_SMMU0_MARC_KEY_CNTr = 3655, + SMMU0_SMMU0_CPU_IND_RDAT_CNTr = 3656, + SMMU0_SMMU0_CPU_IND_RD_REQ_CNTr = 3657, + SMMU0_SMMU0_CPU_IND_WR_REQ_CNTr = 3658, + SMMU0_SMMU0_SMMU0_PLCR_RSP0_CNTr = 3659, + SMMU0_SMMU0_PLCR_SMMU0_REQ0_CNTr = 3660, + SMMU0_SMMU0_SMMU0_LPM_AS_RSP_CNTr = 3661, + SMMU0_SMMU0_LPM_AS_SMMU0_REQ_CNTr = 3662, + SMMU0_SMMU0_SMMU0_ETCAM1_0_AS_RSP_CNTr = 3663, + SMMU0_SMMU0_ETCAM1_0_AS_SMMU0_REQ_CNTr = 3664, + SMMU0_SMMU0_SMMU0_PPU_MCAST_RSP_CNTr = 3665, + SMMU0_SMMU0_PPU_SMMU0_MCAST_KEY_CNTr = 3666, + SMMU0_SMMU0_SMMU0_ODMA_TDM_MC_RSP_CNTr = 3667, + SMMU0_SMMU0_ODMA_SMMU0_TDM_MC_KEY_CNTr = 3668, + SMMU0_SMMU0_SMMU0_ODMA_RSP_CNTr = 3669, + SMMU0_SMMU0_ODMA_SMMU0_CMD_CNTr = 3670, + SMMU0_SMMU0_SMMU0_CFG_TAB_RDAT_CNTr = 3671, + SMMU0_SMMU0_CFG_SMMU0_TAB_RD_CNTr = 3672, + SMMU0_SMMU0_SMMU0_STAT_RSP15_0_CNTr = 3673, + SMMU0_SMMU0_STAT_SMMU0_REQ15_0_CNTr = 3674, + SMMU0_SMMU0_SMMU0_PPU_MEX5_0_RSP_CNTr = 3675, + SMMU0_SMMU0_PPU_SMMU0_MEX5_0_KEY_CNTr = 3676, + SMMU0_SMMU0_FTM_STAT_SMMU0_REQ0_CNTr = 3677, + SMMU0_SMMU0_FTM_STAT_SMMU0_REQ1_CNTr = 3678, + SMMU0_SMMU0_ETM_STAT_SMMU0_REQ0_CNTr = 3679, + SMMU0_SMMU0_ETM_STAT_SMMU0_REQ1_CNTr = 3680, + SMMU0_SMMU0_REQ_ERAM0_31_RD_CNTr = 3681, + SMMU0_SMMU0_REQ_ERAM0_31_WR_CNTr = 3682, + SE_SMMU1_DDR_WDAT1r = 3683, + SE_SMMU1_DDR_WDAT2r = 3684, + SE_SMMU1_DDR_WDAT3r = 3685, + SE_SMMU1_DDR_WDAT4r = 3686, + SE_SMMU1_DDR_WDAT5r = 3687, + SE_SMMU1_DDR_WDAT6r = 3688, + SE_SMMU1_DDR_WDAT7r = 3689, + SE_SMMU1_DDR_WDAT8r = 3690, + SE_SMMU1_DDR_WDAT9r = 3691, + SE_SMMU1_DDR_WDAT10r = 3692, + SE_SMMU1_DDR_WDAT11r = 3693, + SE_SMMU1_DDR_WDAT12r = 3694, + SE_SMMU1_DDR_WDAT13r = 3695, + SE_SMMU1_DDR_WDAT14r = 3696, + SE_SMMU1_DDR_WDAT15r = 3697, + SE_SMMU1_CNT_STAT_CACHE_ENr = 3698, + SE_SMMU1_CNT_STAT_CACHE_CLRr = 3699, + SE_SMMU1_CNT_STAT_CACHE_REQ_63_32r = 3700, + SE_SMMU1_CNT_STAT_CACHE_REQ_31_0r = 3701, + SE_SMMU1_CNT_STAT_CACHE_HIT_63_32r = 3702, + SE_SMMU1_CNT_STAT_CACHE_HIT_31_0r = 3703, + SE_SMMU1_DDR_CMD0r = 3704, + SE_SMMU1_INFO_ADDRr = 3705, + SE_SMMU1_DDR_CMD1r = 3706, + SE_SMMU1_CLR_START_ADDRr = 3707, + SE_SMMU1_CLR_END_ADDRr = 3708, + SE_SMMU1_CLR_TBL_ENr = 3709, + SE_SMMU1_DEBUG_CNT_MODEr = 3710, + SE_SMMU1_INIT_DONEr = 3711, + SE_SMMU1_CPU_RSP_RD_DONEr = 3712, + SE_SMMU1_KSCH_OAM_SP_ENr = 3713, + SE_SMMU1_CFG_CACHE_ENr = 3714, + SE_SMMU1_CACHE_AGE_ENr = 3715, + SE_SMMU1_CPU_RDAT0r = 3716, + SE_SMMU1_CPU_RDAT1r = 3717, + SE_SMMU1_CPU_RDAT2r = 3718, + SE_SMMU1_CPU_RDAT3r = 3719, + SE_SMMU1_CPU_RDAT4r = 3720, + SE_SMMU1_CPU_RDAT5r = 3721, + SE_SMMU1_CPU_RDAT6r = 3722, + SE_SMMU1_CPU_RDAT7r = 3723, + SE_SMMU1_CPU_RDAT8r = 3724, + SE_SMMU1_CPU_RDAT9r = 3725, + SE_SMMU1_CPU_RDAT10r = 3726, + SE_SMMU1_CPU_RDAT11r = 3727, + SE_SMMU1_CPU_RDAT12r = 3728, + SE_SMMU1_CPU_RDAT13r = 3729, + SE_SMMU1_CPU_RDAT14r = 3730, + SE_SMMU1_CPU_RDAT15r = 3731, + SE_SMMU1_CTRL_CPU_RD_RDYr = 3732, + SE_SMMU1_CPU_WARBI_RDY_CFGr = 3733, + SE_SMMU1_DIR_ARBI_CPU_RPFULr = 3734, + SE_SMMU1_DIR_ARBI_WPFULr = 3735, + SE_SMMU1_CFG_WR_ARBI_PFUL0r = 3736, + SE_SMMU1_CFG_WR_ARBI_PFUL1r = 3737, + SE_SMMU1_SMMU1_WDONE_PFUL_CFGr = 3738, + SE_SMMU1_STAT_RATE_CFG_CNTr = 3739, + SE_SMMU1_FTM_RATE_CFG_CNTr = 3740, + SE_SMMU1_ETM_RATE_CFG_CNTr = 3741, + SE_SMMU1_DIR_RATE_CFG_CNTr = 3742, + SE_SMMU1_HASH_RATE_CFG_CNTr = 3743, + SE_SMMU1_FTM_TBL_CFGr = 3744, + SE_SMMU1_LPM_V4_AS_TBL_CFGr = 3745, + SE_SMMU1_LPM_V4_TBL_CFGr = 3746, + SE_SMMU1_LPM_V6_TBL_CFGr = 3747, + SE_SMMU1_LPM_V6_AS_TBL_CFGr = 3748, + SE_SMMU1_DMA_TBL_CFGr = 3749, + SE_SMMU1_OAM_TBL_CFGr = 3750, + SE_SMMU1_CTRL_RPAR_CPU_PFULr = 3751, + SE_SMMU1_CFG_KSCH_DIR_PFULr = 3752, + SE_SMMU1_CFG_KSCH_HASH_PFULr = 3753, + SE_SMMU1_CFG_KSCH_LPM_PFULr = 3754, + SE_SMMU1_CFG_KSCH_LPM_AS_PFULr = 3755, + SE_SMMU1_CFG_KSCH_STAT_PFULr = 3756, + SE_SMMU1_CFG_KSCH_TM_PFULr = 3757, + SE_SMMU1_CFG_KSCH_OAM_PFULr = 3758, + SE_SMMU1_CFG_KSCH_DMA_PFULr = 3759, + SE_SMMU1_CTRL_WFIFO_CFGr = 3760, + SE_SMMU1_RSCH_HASH_PTR_CFGr = 3761, + SE_SMMU1_RSCH_LPM_PTR_CFGr = 3762, + SE_SMMU1_RSCH_LPM_AS_PTR_CFGr = 3763, + SE_SMMU1_RSCH_STAT_PTR_CFGr = 3764, + SE_SMMU1_RSCH_OAM_PTR_CFGr = 3765, + SE_SMMU1_RSCHD_FIFO_PEPT_CFGr = 3766, + SE_SMMU1_DIR_FIFO_PFUL_CFGr = 3767, + SE_SMMU1_HASH_FIFO_PFUL_CFGr = 3768, + SE_SMMU1_LPM_FIFO_PFUL_CFGr = 3769, + SE_SMMU1_LPM_AS_FIFO_PFUL_CFGr = 3770, + SE_SMMU1_STAT_FIFO_PFUL_CFGr = 3771, + SE_SMMU1_FTM_FIFO_PFUL_CFGr = 3772, + SE_SMMU1_ETM_FIFO_PFUL_CFGr = 3773, + SE_SMMU1_OAM_FIFO_PFUL_CFGr = 3774, + SE_SMMU1_DMA_FIFO_PFUL_CFGr = 3775, + SE_SMMU1_CACHE_RSP_RR_FIFO_CFGr = 3776, + SE_SMMU1_DDR_RSP_RR_FIFO_CFGr = 3777, + SE_SMMU1_CPU_CAHCE_FIFO_CFGr = 3778, + SE_SMMU1_CACHE_RSP_FIFO_CFGr = 3779, + SE_SMMU1_TEST_STATEr = 3780, + SE_SMMU1_CACHE_FIFO_EPTr = 3781, + SE_SMMU1_RR_FIFO_EPTr = 3782, + SE_SMMU1_WR_FIFO_EPTr = 3783, + SE_SMMU1_WDONE_FIFO_EPTr = 3784, + SE_SMMU1_KSCHD_FIFO_EPT0r = 3785, + SE_SMMU1_CASH_FIFO_EPTr = 3786, + SE_SMMU1_CTRL_FIFO_EPTr = 3787, + SE_SMMU1_SMMU1_RSCHD_EPT3r = 3788, + SE_SMMU1_SMMU1_RSCHD_EPT2r = 3789, + SE_SMMU1_SMMU1_RSCHD_EPT1r = 3790, + SE_SMMU1_SMMU1_RSCHD_EPT0r = 3791, + SE_SMMU1_CASH0_ECC_ERR_ADDRr = 3792, + SE_SMMU1_ARBI_CPU_WR_RDYr = 3793, + SE_SMMU1_SMMU1_INT_0_ENr = 3794, + SE_SMMU1_SMMU1_INT_0_MASKr = 3795, + SE_SMMU1_SMMU1_INT_1_ENr = 3796, + SE_SMMU1_SMMU1_INT_1_MASKr = 3797, + SE_SMMU1_SMMU1_INT_2_ENr = 3798, + SE_SMMU1_SMMU1_INT_2_MASKr = 3799, + SE_SMMU1_SMMU1_INT_3_ENr = 3800, + SE_SMMU1_SMMU1_INT_3_MASKr = 3801, + SE_SMMU1_SMMU1_INT_0_STATUSr = 3802, + SE_SMMU1_SMMU1_INT_1_STATUSr = 3803, + SE_SMMU1_SMMU1_INT_2_STATUSr = 3804, + SE_SMMU1_SMMU1_INT_3_STATUSr = 3805, + SE_SMMU1_SMMU1_INT_STATUSr = 3806, + SE_SMMU1_CTRL_TO_CASH7_0_FC_CNTr = 3807, + SE_SMMU1_CASH7_0_TO_CTRL_REQ_CNTr = 3808, + SE_SMMU1_RSCHD_TO_CACHE7_FC_CNTr = 3809, + SE_SMMU1_CASH7_TO_CACHE_RSP_CNTr = 3810, + SE_SMMU1_CASH7_TO_CTRL_FC_CNTr = 3811, + SE_SMMU1_CTRL_TO_CASH7_0_RSP_CNTr = 3812, + SE_SMMU1_KSCHD_TO_CACHE7_0_REQ_CNTr = 3813, + SE_SMMU1_CACHE7_0_TO_KSCHD_FC_CNTr = 3814, + SE_SMMU1_DMA_TO_SMMU1_RD_REQ_CNTr = 3815, + SE_SMMU1_OAM_TO_KSCHD_REQ_CNTr = 3816, + SE_SMMU1_OAM_RR_STATE_RSP_CNTr = 3817, + SE_SMMU1_OAM_CLASH_INFO_CNTr = 3818, + SE_SMMU1_OAM_TO_RR_REQ_CNTr = 3819, + SE_SMMU1_LPM_AS_TO_KSCHD_REQ_CNTr = 3820, + SE_SMMU1_LPM_AS_RR_STATE_RSP_CNTr = 3821, + SE_SMMU1_LPM_AS_CLASH_INFO_CNTr = 3822, + SE_SMMU1_LPM_AS_TO_RR_REQ_CNTr = 3823, + SE_SMMU1_LPM_TO_KSCHD_REQ_CNTr = 3824, + SE_SMMU1_LPM_RR_STATE_RSP_CNTr = 3825, + SE_SMMU1_LPM_CLASH_INFO_CNTr = 3826, + SE_SMMU1_LPM_TO_RR_REQ_CNTr = 3827, + SE_SMMU1_HASH3_0_TO_KSCHD_REQ_CNTr = 3828, + SE_SMMU1_HASH3_0_RR_STATE_RSP_CNTr = 3829, + SE_SMMU1_HASH3_0_CLASH_INFO_CNTr = 3830, + SE_SMMU1_HASH3_0_TO_RR_REQ_CNTr = 3831, + SE_SMMU1_DIR3_0_TO_KSCHD_REQ_CNTr = 3832, + SE_SMMU1_DIR3_0_CLASH_INFO_CNTr = 3833, + SE_SMMU1_DIR_TBL_WR_REQ_CNTr = 3834, + SE_SMMU1_WARBI_TO_DIR_TBL_WARBI_FC_CNTr = 3835, + SE_SMMU1_DIR3_0_TO_BANK_RR_REQ_CNTr = 3836, + SE_SMMU1_KSCHD_TO_DIR3_0_FC_CNTr = 3837, + SE_SMMU1_DIR3_0_RR_STATE_RSP_CNTr = 3838, + SE_SMMU1_WR_DONE_TO_WARBI_FC_CNTr = 3839, + SE_SMMU1_WR_DONE_PTR_REQ_CNTr = 3840, + SE_SMMU1_CTRL7_0_TO_WARBI_FC_CNTr = 3841, + SE_SMMU1_WARBI_TO_CTRL7_0_WR_REQ_CNTr = 3842, + SE_SMMU1_WARBI_TO_CASH7_0_WR_REQ_CNTr = 3843, + SE_SMMU1_WARBI_TO_CPU_WR_FC_CNTr = 3844, + SE_SMMU1_CPU_WR_REQ_CNTr = 3845, + SE_SMMU1_CTRL7_0_TO_CPU_RD_RSP_CNTr = 3846, + SE_SMMU1_CPU_TO_CTRL7_0_RD_REQ_CNTr = 3847, + SE_SMMU1_CPU_RD_DIR_TBL_RSP_CNTr = 3848, + SE_SMMU1_CPU_TO_DIR_TBL_RD_WR_REQ_CNTr = 3849, + SE_SMMU1_SMMU1_TO_MMU_7_0_RSP_FC_CNTr = 3850, + SE_SMMU1_MMU_7_0_TO_SMMU1_RD_RSP_CNTr = 3851, + SE_SMMU1_MMU_7_0_TO_SMMU1_RD_FC_CNTr = 3852, + SE_SMMU1_SMMU1_TO_MMU_7_RD_REQ_CNTr = 3853, + SE_SMMU1_MMU_7_TO_SMMU1_WR_FC_CNTr = 3854, + SE_SMMU1_SMMU1_TO_MMU_7_0_WR_REQ_CNTr = 3855, + SE_SMMU1_SE_TO_SMMU1_WR_RSP_FC_CNTr = 3856, + SE_SMMU1_SMMU1_TO_SE_WR_RSP_CNTr = 3857, + SE_SMMU1_DDR7_0_WR_RSP_CNTr = 3858, + SE_SMMU1_SMMU1_TO_AS_FC_CNTr = 3859, + SE_SMMU1_AS_TO_SMMU1_WR_REQ_CNTr = 3860, + SE_SMMU1_SMMU1_TO_SE_PARSER_FC_CNTr = 3861, + SE_SMMU1_SE_PARSER_TO_SMMU1_REQ_CNTr = 3862, + SE_SMMU1_SMMU1_TO_ETM_WR_FC_CNTr = 3863, + SE_SMMU1_ETM_WR_REQ_CNTr = 3864, + SE_SMMU1_SMMU1_TO_FTM_WR_FC_CNTr = 3865, + SE_SMMU1_FTM_WR_REQ_CNTr = 3866, + SE_SMMU1_SMMU1_TO_STATE_WR_FC_CNTr = 3867, + SE_SMMU1_STATE_WR_REQ_CNTr = 3868, + SE_SMMU1_SE_TO_DMA_RSP_CNTr = 3869, + SE_SMMU1_SE_TO_DMA_FC_CNTr = 3870, + SE_SMMU1_OAM_TO_SMMU1_FC_CNTr = 3871, + SE_SMMU1_SMMU1_TO_OAM_RSP_CNTr = 3872, + SE_SMMU1_SMMU1_TO_OAM_FC_CNTr = 3873, + SE_SMMU1_OAM_TO_SMMU1_REQ_CNTr = 3874, + SE_SMMU1_SMMU1_TO_ETM_RSP_CNTr = 3875, + SE_SMMU1_SMMU1_TO_FTM_RSP_CNTr = 3876, + SE_SMMU1_SMMU1_TO_ETM_FC_CNTr = 3877, + SE_SMMU1_ETM_TO_SMMU1_REQ_CNTr = 3878, + SE_SMMU1_SMMU1_TO_FTM_FC_CNTr = 3879, + SE_SMMU1_FTM_TO_SMMU1_REQ_CNTr = 3880, + SE_SMMU1_SMMU1_TO_STAT_RSP_CNTr = 3881, + SE_SMMU1_SMMU1_TO_STAT_FC_CNTr = 3882, + SE_SMMU1_STAT_TO_SMMU1_REQ_CNTr = 3883, + SE_SMMU1_LPM_AS_TO_SMMU1_FC_CNTr = 3884, + SE_SMMU1_LPM_TO_SMMU1_FC_CNTr = 3885, + SE_SMMU1_SMMU1_TO_LPM_AS_RSP_CNTr = 3886, + SE_SMMU1_SMMU1_TO_LPM_RSP_CNTr = 3887, + SE_SMMU1_SMMU1_TO_LPM_AS_FC_CNTr = 3888, + SE_SMMU1_SMMU1_TO_LPM_FC_CNTr = 3889, + SE_SMMU1_LPM_AS_TO_SMMU1_REQ_CNTr = 3890, + SE_SMMU1_LPM_TO_SMMU1_REQ_CNTr = 3891, + SE_SMMU1_HASH3_0_TO_SMMU1_FC_CNTr = 3892, + SE_SMMU1_SMMU1_TO_HASH3_0_RSP_CNTr = 3893, + SE_SMMU1_SMMU1_TO_HASH3_0_FC_CNTr = 3894, + SE_SMMU1_HASH3_0_TO_SMMU1_CNTr = 3895, + SE_SMMU1_SE_TO_SMMU1_DIR3_0_RSP_FC_CNTr = 3896, + SE_SMMU1_SMMU1_TO_SE_DIR3_0_RSP_CNTr = 3897, + SE_SMMU1_SMMU1_TO_SE_DIR3_0_FC_CNTr = 3898, + SE_SMMU1_SE_TO_SMMU1_DIR3_0_CNTr = 3899, + SE_SMMU1_CACHE7_0_TO_RSCHD_RSP_CNTr = 3900, + SE_CMMU_DDR_RW_ADDRr = 3901, + SE_CMMU_DDR_RW_MODEr = 3902, + SE_CMMU_CP_CMDr = 3903, + SE_CMMU_CPU_IND_RD_DONEr = 3904, + SE_CMMU_CPU_IND_RDAT0r = 3905, + SE_CMMU_CPU_IND_RDAT1r = 3906, + SE_CMMU_CPU_IND_RDAT2r = 3907, + SE_CMMU_CPU_IND_RDAT3r = 3908, + SE_CMMU_CPU_DDR_FIFO_ALMFULr = 3909, + SE_CMMU_DEBUG_CNT_MODEr = 3910, + SE_CMMU_CMMU_PFUL_CFGr = 3911, + SE_CMMU_CMMU_STAT_PFUL_CFGr = 3912, + SE_CMMU_STAT_OVERFLOW_MODEr = 3913, + SE_CMMU_CMMU_CP_FIFO_PFULr = 3914, + SE_CMMU_DDR_WR_DAT0r = 3915, + SE_CMMU_DDR_WR_DAT1r = 3916, + SE_CMMU_CMMU_INT_UNMASK_FLAGr = 3917, + SE_CMMU_CMMU_INT_ENr = 3918, + SE_CMMU_CMMU_INT_MASKr = 3919, + SE_CMMU_CMMU_INT_STATUSr = 3920, + SE_CMMU_STAT_CMMU_REQ_CNTr = 3921, + SE_CMMU_CMMU_FC0_CNTr = 3922, + SE_CMMU_CMMU_FC1_CNTr = 3923, + SE_CMMU_CMMU_FC2_CNTr = 3924, + SMMU14K_SE_SMMU1_HASH0_TBL0_CFGr = 3925, + SMMU14K_SE_SMMU1_HASH0_TBL1_CFGr = 3926, + SMMU14K_SE_SMMU1_HASH0_TBL2_CFGr = 3927, + SMMU14K_SE_SMMU1_HASH0_TBL3_CFGr = 3928, + SMMU14K_SE_SMMU1_HASH0_TBL4_CFGr = 3929, + SMMU14K_SE_SMMU1_HASH0_TBL5_CFGr = 3930, + SMMU14K_SE_SMMU1_HASH0_TBL6_CFGr = 3931, + SMMU14K_SE_SMMU1_HASH0_TBL7_CFGr = 3932, + SMMU14K_SE_SMMU1_HASH1_TBL0_CFGr = 3933, + SMMU14K_SE_SMMU1_HASH1_TBL1_CFGr = 3934, + SMMU14K_SE_SMMU1_HASH1_TBL2_CFGr = 3935, + SMMU14K_SE_SMMU1_HASH1_TBL3_CFGr = 3936, + SMMU14K_SE_SMMU1_HASH1_TBL4_CFGr = 3937, + SMMU14K_SE_SMMU1_HASH1_TBL5_CFGr = 3938, + SMMU14K_SE_SMMU1_HASH1_TBL6_CFGr = 3939, + SMMU14K_SE_SMMU1_HASH1_TBL7_CFGr = 3940, + SMMU14K_SE_SMMU1_HASH2_TBL0_CFGr = 3941, + SMMU14K_SE_SMMU1_HASH2_TBL1_CFGr = 3942, + SMMU14K_SE_SMMU1_HASH2_TBL2_CFGr = 3943, + SMMU14K_SE_SMMU1_HASH2_TBL3_CFGr = 3944, + SMMU14K_SE_SMMU1_HASH2_TBL4_CFGr = 3945, + SMMU14K_SE_SMMU1_HASH2_TBL5_CFGr = 3946, + SMMU14K_SE_SMMU1_HASH2_TBL6_CFGr = 3947, + SMMU14K_SE_SMMU1_HASH2_TBL7_CFGr = 3948, + SMMU14K_SE_SMMU1_HASH3_TBL0_CFGr = 3949, + SMMU14K_SE_SMMU1_HASH3_TBL1_CFGr = 3950, + SMMU14K_SE_SMMU1_HASH3_TBL2_CFGr = 3951, + SMMU14K_SE_SMMU1_HASH3_TBL3_CFGr = 3952, + SMMU14K_SE_SMMU1_HASH3_TBL4_CFGr = 3953, + SMMU14K_SE_SMMU1_HASH3_TBL5_CFGr = 3954, + SMMU14K_SE_SMMU1_HASH3_TBL6_CFGr = 3955, + SMMU14K_SE_SMMU1_HASH3_TBL7_CFGr = 3956, + STAT_STAT_CFG_CPU_IND_ERAM_WDAT1r = 3957, + STAT_STAT_CFG_CPU_IND_ERAM_WDAT2r = 3958, + STAT_STAT_CFG_CPU_IND_ERAM_WDAT3r = 3959, + STAT_STAT_CFG_CPU_IND_ERAM_REQ_INFOr = 3960, + STAT_STAT_CFG_CPU_IND_ERAM_RD_DONEr = 3961, + STAT_STAT_CFG_CPU_IND_ERAM_RDAT0r = 3962, + STAT_STAT_CFG_CPU_IND_ERAM_RDAT1r = 3963, + STAT_STAT_CFG_CPU_IND_ERAM_RDAT2r = 3964, + STAT_STAT_CFG_CPU_IND_ERAM_RDAT3r = 3965, + STAT_STAT_CFG_TM_ALU_ERAM_CPU_RDYr = 3966, + STAT_STAT_CFG_OAM_STAT_CFGr = 3967, + STAT_STAT_CFG_FTM_PORT_SEL_CFGr = 3968, + STAT_STAT_CFG_OAM_ERAM_BASE_ADDRr = 3969, + STAT_STAT_CFG_OAM_LM_ERAM_BASE_ADDRr = 3970, + STAT_STAT_CFG_OAM_DDR_BASE_ADDRr = 3971, + STAT_STAT_CFG_PLCR0_SCHD_PFUL_CFGr = 3972, + STAT_STAT_CFG_OAM_LM_ORD_PFUL_CFGr = 3973, + STAT_STAT_CFG_DDR_SCHD_PFUL_CFGr = 3974, + STAT_STAT_CFG_ERAM_SCHD_PFUL_CFGr = 3975, + STAT_STAT_CFG_ERAM_SCHD_PEPT_CFGr = 3976, + STAT_STAT_CFG_ERAM_SCHD_OAM_PFUL_CFGr = 3977, + STAT_STAT_CFG_ERAM_SCHD_OAM_PEPT_CFGr = 3978, + STAT_STAT_CFG_ERAM_SCHD_OAM_LM_PFUL_CFGr = 3979, + STAT_STAT_CFG_ERAM_SCHD_OAM_LM_PEPT_CFGr = 3980, + STAT_STAT_CFG_RSCHD_PFUL_CFGr = 3981, + STAT_STAT_CFG_RSCHD_PEPT_CFGr = 3982, + STAT_STAT_CFG_RSCHD_PLCR_PFUL_CFGr = 3983, + STAT_STAT_CFG_RSCHD_PLCR_PEPT_CFGr = 3984, + STAT_STAT_CFG_RSCHD_PLCR_INFO_PFUL_CFGr = 3985, + STAT_STAT_CFG_ALU_ARB_CPU_PFUL_CFGr = 3986, + STAT_STAT_CFG_ALU_ARB_USER_PFUL_CFGr = 3987, + STAT_STAT_CFG_ALU_ARB_STAT_PFUL_CFGr = 3988, + STAT_STAT_CFG_CYCMOV_DAT_PFUL_CFGr = 3989, + STAT_STAT_CFG_DDR_OPR_PFUL_CFGr = 3990, + STAT_STAT_CFG_CYCLE_MOV_PFUL_CFGr = 3991, + STAT_STAT_CFG_CNTOVF_PFUL_CFGr = 3992, + STAT_STAT_CFG_ERAM_SCHD_PLCR_PFUL_CFGr = 3993, + STAT_STAT_CFG_ERAM_SCHD_PLCR_PEPT_CFGr = 3994, + STAT_STAT_CFG_DEBUG_CNT_MODEr = 3995, + STAT_STAT_CFG_TM_MOV_PERIOD_CFGr = 3996, + STAT_STAT_CFG_ALU_DDR_CPU_REQ_PFUL_CFGr = 3997, + STAT_STAT_CFG_CYCMOV_ADDR_PFUL_CFGr = 3998, + STAT_STAT_CFG_ORD_DDR_PLCR_FIFO_EMPTYr = 3999, + STAT_STAT_CFG_TM_STAT_FIFO_EMPTYr = 4000, + STAT_STAT_CFG_ERAM_SCHD_FIFO_EMPTY_0_1r = 4001, + STAT_STAT_CFG_ERAM_SCHD_FIFO_EMPTY_2_3r = 4002, + STAT_STAT_CFG_ERAM_SCHD_FIFO_EMPTY_4_5r = 4003, + STAT_STAT_CFG_ERAM_SCHD_FIFO_EMPTY_6_7r = 4004, + STAT_STAT_CFG_ERAM_SCHD_FIFO_EMPTY_FREE_8r = 4005, + STAT_STAT_CFG_RSCHD_FIFO_EMPTY_0_3r = 4006, + STAT_STAT_CFG_RSCHD_FIFO_EMPTY_4_7r = 4007, + STAT_STAT_CFG_RSCHD_FIFO_EMPTY_8_11r = 4008, + STAT_STAT_CFG_RSCHD_FIFO_EMPTY_12_15r = 4009, + STAT_STAT_CFG_RSCHD_FIFO_EMPTY_PLCR_16_17r = 4010, + STAT_STAT_CFG_STAT_INT_UNMASK_FLAGr = 4011, + STAT_STAT_CFG_STAT_INT0_ENr = 4012, + STAT_STAT_CFG_STAT_INT0_MASKr = 4013, + STAT_STAT_CFG_STAT_INT0_STATUSr = 4014, + STAT_STAT_CFG_STAT_INT1_ENr = 4015, + STAT_STAT_CFG_STAT_INT1_MASKr = 4016, + STAT_STAT_CFG_STAT_INT1_STATUSr = 4017, + STAT_STAT_CFG_STAT_INT2_ENr = 4018, + STAT_STAT_CFG_STAT_INT2_MASKr = 4019, + STAT_STAT_CFG_STAT_INT2_STATUSr = 4020, + STAT_STAT_CFG_STAT_INT3_ENr = 4021, + STAT_STAT_CFG_STAT_INT3_MASKr = 4022, + STAT_STAT_CFG_STAT_INT3_STATUSr = 4023, + STAT_STAT_CFG_STAT_INT4_ENr = 4024, + STAT_STAT_CFG_STAT_INT4_MASKr = 4025, + STAT_STAT_CFG_STAT_INT4_STATUSr = 4026, + STAT_STAT_CFG_STAT_INT5_ENr = 4027, + STAT_STAT_CFG_STAT_INT5_MASKr = 4028, + STAT_STAT_CFG_STAT_INT5_STATUSr = 4029, + STAT_STAT_CFG_RSCHD_ECC_BYPASSr = 4030, + STAT_STAT_CFG_RSCHD_ECC_SINGLE_ERRr = 4031, + STAT_STAT_CFG_RSCHD_ECC_DOUBLE_ERRr = 4032, + STAT_STAT_CFG_CPU_IND_DDR_WDAT0r = 4033, + STAT_STAT_CFG_CPU_IND_DDR_WDAT1r = 4034, + STAT_STAT_CFG_CPU_IND_DDR_WDAT2r = 4035, + STAT_STAT_CFG_CPU_IND_DDR_WDAT3r = 4036, + STAT_STAT_CFG_CPU_IND_DDR_WDAT4r = 4037, + STAT_STAT_CFG_CPU_IND_DDR_WDAT5r = 4038, + STAT_STAT_CFG_CPU_IND_DDR_WDAT6r = 4039, + STAT_STAT_CFG_CPU_IND_DDR_WDAT7r = 4040, + STAT_STAT_CFG_CPU_IND_DDR_WDAT8r = 4041, + STAT_STAT_CFG_CPU_IND_DDR_WDAT9r = 4042, + STAT_STAT_CFG_CPU_IND_DDR_WDAT10r = 4043, + STAT_STAT_CFG_CPU_IND_DDR_WDAT11r = 4044, + STAT_STAT_CFG_CPU_IND_DDR_WDAT12r = 4045, + STAT_STAT_CFG_CPU_IND_DDR_WDAT13r = 4046, + STAT_STAT_CFG_CPU_IND_DDR_WDAT14r = 4047, + STAT_STAT_CFG_CPU_IND_DDR_WDAT15r = 4048, + STAT_STAT_CFG_CPU_IND_DDR_REQ_INFOr = 4049, + STAT_STAT_CFG_CPU_IND_DDR_RD_DONEr = 4050, + STAT_STAT_CFG_CPU_IND_DDR_RDAT0r = 4051, + STAT_STAT_CFG_CPU_IND_DDR_RDAT1r = 4052, + STAT_STAT_CFG_CPU_IND_DDR_RDAT2r = 4053, + STAT_STAT_CFG_CPU_IND_DDR_RDAT3r = 4054, + STAT_STAT_CFG_CPU_IND_DDR_RDAT4r = 4055, + STAT_STAT_CFG_CPU_IND_DDR_RDAT5r = 4056, + STAT_STAT_CFG_CPU_IND_DDR_RDAT6r = 4057, + STAT_STAT_CFG_CPU_IND_DDR_RDAT7r = 4058, + STAT_STAT_CFG_CPU_IND_DDR_RDAT8r = 4059, + STAT_STAT_CFG_CPU_IND_DDR_RDAT9r = 4060, + STAT_STAT_CFG_CPU_IND_DDR_RDAT10r = 4061, + STAT_STAT_CFG_CPU_IND_DDR_RDAT11r = 4062, + STAT_STAT_CFG_CPU_IND_DDR_RDAT12r = 4063, + STAT_STAT_CFG_CPU_IND_DDR_RDAT13r = 4064, + STAT_STAT_CFG_CPU_IND_DDR_RDAT14r = 4065, + STAT_STAT_CFG_CPU_IND_DDR_RDAT15r = 4066, + STAT_STAT_CFG_TM_ALU_DDR_CPU_RDYr = 4067, + STAT_STAT_CFG_EPT_FLAGr = 4068, + STAT_STAT_CFG_PPU_SOFT_RSTr = 4069, + STAT_STAT_CFG_STAT_SMMU0_FC15_0_CNTr = 4070, + STAT_STAT_CFG_SMMU0_STAT_FC15_0_CNTr = 4071, + STAT_STAT_CFG_SMMU0_STAT_RSP15_0_CNTr = 4072, + STAT_STAT_CFG_STAT_SMMU0_REQ15_0_CNTr = 4073, + STAT_STAT_CFG_PPU_STAT_MEC5_0_RSP_FC_CNTr = 4074, + STAT_STAT_CFG_STAT_PPU_MEC5_0_KEY_FC_CNTr = 4075, + STAT_STAT_CFG_STAT_PPU_MEC5_0_RSP_CNTr = 4076, + STAT_STAT_CFG_PPU_STAT_MEC5_0_KEY_CNTr = 4077, + STAT_STAT_CFG_PPU5_0_NO_EXIST_OPCD_EX_CNTr = 4078, + STAT_STAT_CFG_SE_ETM_STAT_WR_FC_CNTr = 4079, + STAT_STAT_CFG_SE_ETM_STAT_RD_FC_CNTr = 4080, + STAT_STAT_CFG_STAT_ETM_DEQ_FC_CNTr = 4081, + STAT_STAT_CFG_STAT_ETM_ENQ_FC_CNTr = 4082, + STAT_STAT_CFG_STAT_OAM_LM_FC_CNTr = 4083, + STAT_STAT_CFG_OAM_STAT_LM_FC_CNTr = 4084, + STAT_STAT_CFG_STAT_OAM_FC_CNTr = 4085, + STAT_STAT_CFG_CMMU_STAT_FC_CNTr = 4086, + STAT_STAT_CFG_STAT_CMMU_REQ_CNTr = 4087, + STAT_STAT_CFG_SMMU0_PLCR_RSP0_CNTr = 4088, + STAT_STAT_CFG_PLCR_SMMU0_REQ0_CNTr = 4089, + STAT_STAT_CFG_STAT_OAM_LM_RSP_CNTr = 4090, + STAT_STAT_CFG_OAM_STAT_LM_REQ_CNTr = 4091, + STAT_STAT_CFG_OAM_STAT_REQ_CNTr = 4092, + STAT_STAT_CFG_SE_ETM_STAT_RSP_CNTr = 4093, + STAT_STAT_CFG_ETM_STAT_SE_WR_REQ_CNTr = 4094, + STAT_STAT_CFG_ETM_STAT_SE_RD_REQ_CNTr = 4095, + STAT_STAT_CFG_ETM_STAT_SMMU0_REQ_CNT0r = 4096, + STAT_STAT_CFG_ETM_STAT_SMMU0_REQ_CNT1r = 4097, + STAT_STAT_CFG_TM_STAT_ERAM_CPU_RSP_CNTr = 4098, + STAT_STAT_CFG_CPU_RD_ERAM_REQ_CNTr = 4099, + STAT_STAT_CFG_CPU_WR_ERAM_REQ_CNTr = 4100, + STAT_STAT_CFG_TM_STAT_DDR_CPU_RSP_CNTr = 4101, + STAT_STAT_CFG_CPU_RD_DDR_REQ_CNTr = 4102, + STAT_STAT_CFG_CPU_WR_DDR_REQ_CNTr = 4103, + STAT_ETCAM_CPU_IND_WDAT1r = 4104, + STAT_ETCAM_CPU_IND_WDAT2r = 4105, + STAT_ETCAM_CPU_IND_WDAT3r = 4106, + STAT_ETCAM_CPU_IND_WDAT4r = 4107, + STAT_ETCAM_CPU_IND_WDAT5r = 4108, + STAT_ETCAM_CPU_IND_WDAT6r = 4109, + STAT_ETCAM_CPU_IND_WDAT7r = 4110, + STAT_ETCAM_CPU_IND_WDAT8r = 4111, + STAT_ETCAM_CPU_IND_WDAT9r = 4112, + STAT_ETCAM_CPU_IND_WDAT10r = 4113, + STAT_ETCAM_CPU_IND_WDAT11r = 4114, + STAT_ETCAM_CPU_IND_WDAT12r = 4115, + STAT_ETCAM_CPU_IND_WDAT13r = 4116, + STAT_ETCAM_CPU_IND_WDAT14r = 4117, + STAT_ETCAM_CPU_IND_WDAT15r = 4118, + STAT_ETCAM_CPU_IND_WDAT16r = 4119, + STAT_ETCAM_CPU_IND_WDAT17r = 4120, + STAT_ETCAM_CPU_IND_WDAT18r = 4121, + STAT_ETCAM_CPU_IND_WDAT19r = 4122, + STAT_ETCAM_T_STRWC_CFGr = 4123, + STAT_ETCAM_ETCAM_INT_UNMASK_FLAGr = 4124, + STAT_ETCAM_ETCAM_INT_EN0r = 4125, + STAT_ETCAM_ETCAM_INT_MASK0r = 4126, + STAT_ETCAM_ETCAM_INT_STATUSr = 4127, + STAT_ETCAM_INT_TB_INI_OKr = 4128, + STAT_ETCAM_ETCAM_CLK_ENr = 4129, + STAT_ETCAM_AS_ETCAM_REQ0_CNTr = 4130, + STAT_ETCAM_AS_ETCAM_REQ1_CNTr = 4131, + STAT_ETCAM_ETCAM_AS_INDEX0_CNTr = 4132, + STAT_ETCAM_ETCAM_AS_INDEX1_CNTr = 4133, + STAT_ETCAM_ETCAM_NOT_HIT0_CNTr = 4134, + STAT_ETCAM_ETCAM_NOT_HIT1_CNTr = 4135, + STAT_ETCAM_TABLE_ID_NOT_MATCH_CNTr = 4136, + STAT_ETCAM_TABLE_ID_CLASH01_CNTr = 4137, + STAT_ETCAM_ETCAM_CPU_FLr = 4138, + STAT_ETCAM_ETCAM_ARB_EMPTYr = 4139, + DTB_DTB_CFG_CFG_FINISH_INT_EVENT0r = 4140, + DTB_DTB_CFG_CFG_FINISH_INT_EVENT1r = 4141, + DTB_DTB_CFG_CFG_FINISH_INT_EVENT2r = 4142, + DTB_DTB_CFG_CFG_FINISH_INT_EVENT3r = 4143, + DTB_DTB_CFG_CFG_FINISH_INT_MAKS0r = 4144, + DTB_DTB_CFG_CFG_FINISH_INT_MAKS1r = 4145, + DTB_DTB_CFG_CFG_FINISH_INT_MAKS2r = 4146, + DTB_DTB_CFG_CFG_FINISH_INT_MAKS3r = 4147, + DTB_DTB_CFG_CFG_FINISH_INT_TEST0r = 4148, + DTB_DTB_CFG_CFG_FINISH_INT_TEST1r = 4149, + DTB_DTB_CFG_CFG_FINISH_INT_TEST2r = 4150, + DTB_DTB_CFG_CFG_FINISH_INT_TEST3r = 4151, + DTB_DTB_CFG_CFG_DTB_INT_TO_RISCV_SELr = 4152, + DTB_DTB_CFG_CFG_DTB_EP_INT_MSIX_ENABLEr = 4153, + DTB_DTB_CFG_CFG_DTB_EP_DOORBELL_ADDR_H_0_15r = 4154, + DTB_DTB_CFG_CFG_DTB_EP_DOORBELL_ADDR_L_0_15r = 4155, + DTB_DTB_CFG_CFG_DTB_DEBUG_MODE_ENr = 4156, + DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_ADDR_HIGHr = 4157, + DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_ADDR_LOWr = 4158, + DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_LENr = 4159, + DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_USERr = 4160, + DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_ONLOAD_CNTr = 4161, + DTB_DTB_CFG_CNT_AXI_RD_TABLE_RESP_ERRr = 4162, + DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_ADDR_HIGHr = 4163, + DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_ADDR_LOWr = 4164, + DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_LENr = 4165, + DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_USERr = 4166, + DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_ONLOAD_CNTr = 4167, + DTB_DTB_CFG_CNT_AXI_RD_PD_RESP_ERRr = 4168, + DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_ADDR_HIGHr = 4169, + DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_ADDR_LOWr = 4170, + DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_LENr = 4171, + DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_USERr = 4172, + DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_ONLOAD_CNTr = 4173, + DTB_DTB_CFG_CNT_AXI_WR_CTRL_RESP_ERRr = 4174, + DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_ADDR_HIGHr = 4175, + DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_ADDR_LOWr = 4176, + DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_LENr = 4177, + DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_USERr = 4178, + DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_ONLOAD_CNTr = 4179, + DTB_DTB_CFG_CNT_AXI_WR_DDR_RESP_ERRr = 4180, + DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_ADDR_HIGHr = 4181, + DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_ADDR_LOWr = 4182, + DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_LENr = 4183, + DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_USERr = 4184, + DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_ONLOAD_CNTr = 4185, + DTB_DTB_CFG_CNT_AXI_WR_FIN_RESP_ERRr = 4186, + DTB_DTB_CFG_CNT_DTB_WR_SMMU0_TABLE_HIGHr = 4187, + DTB_DTB_CFG_CNT_DTB_WR_SMMU0_TABLE_LOWr = 4188, + DTB_DTB_CFG_CNT_DTB_WR_SMMU1_TABLE_HIGHr = 4189, + DTB_DTB_CFG_CNT_DTB_WR_SMMU1_TABLE_LOWr = 4190, + DTB_DTB_CFG_CNT_DTB_WR_ZCAM_TABLE_HIGHr = 4191, + DTB_DTB_CFG_CNT_DTB_WR_ZCAM_TABLE_LOWr = 4192, + DTB_DTB_CFG_CNT_DTB_WR_ETCAM_TABLE_HIGHr = 4193, + DTB_DTB_CFG_CNT_DTB_WR_ETCAM_TABLE_LOWr = 4194, + DTB_DTB_CFG_CNT_DTB_WR_HASH_TABLE_HIGHr = 4195, + DTB_DTB_CFG_CNT_DTB_WR_HASH_TABLE_LOWr = 4196, + DTB_DTB_CFG_CNT_DTB_RD_SMMU0_TABLE_HIGHr = 4197, + DTB_DTB_CFG_CNT_DTB_RD_SMMU0_TABLE_LOWr = 4198, + DTB_DTB_CFG_CNT_DTB_RD_SMMU1_TABLE_HIGHr = 4199, + DTB_DTB_CFG_CNT_DTB_RD_SMMU1_TABLE_LOWr = 4200, + DTB_DTB_CFG_CNT_DTB_RD_ZCAM_TABLE_HIGHr = 4201, + DTB_DTB_CFG_CNT_DTB_RD_ZCAM_TABLE_LOWr = 4202, + DTB_DTB_CFG_CNT_DTB_RD_ETCAM_TABLE_HIGHr = 4203, + DTB_DTB_CFG_CNT_DTB_RD_ETCAM_TABLE_LOWr = 4204, + DTB_DTB_CFG_INFO_WR_CTRL_STATEr = 4205, + DTB_DTB_CFG_INFO_RD_TABLE_STATEr = 4206, + DTB_DTB_CFG_INFO_RD_PD_STATEr = 4207, + DTB_DTB_CFG_INFO_DUMP_CMD_STATEr = 4208, + DTB_DTB_CFG_INFO_WR_DDR_STATEr = 4209, + DTB_DTB_CFG_CFG_DTB_DEBUG_INFO_CLRr = 4210, + DTB_DDOS_CFG_DDOS_STAT_DUMP_THRD_0_15r = 4211, + DTB_DDOS_CFG_DDOS_STAT_DUMP_THRD_COMP_ENr = 4212, + DTB_DDOS_CFG_DDOS_DUMP_STAT_NUMr = 4213, + DTB_DDOS_CFG_DDOS_EVEN_HASH_TABLE_BADDRr = 4214, + DTB_DDOS_CFG_DDOS_ODD_HASH_TABLE_BADDRr = 4215, + DTB_DDOS_CFG_DDOS_STAT_INDEX_OFFSETr = 4216, + DTB_DDOS_CFG_DDOS_NS_FLAG_CNTr = 4217, + DTB_DDOS_CFG_DDOS_EVEN_STAT_TABLE_BADDRr = 4218, + DTB_DDOS_CFG_DDOS_ODD_STAT_TABLE_BADDRr = 4219, + DTB_DDOS_CFG_DDOS_EVEN_STAT_DUMP_DADDR_Hr = 4220, + DTB_DDOS_CFG_DDOS_EVEN_STAT_DUMP_DADDR_Lr = 4221, + DTB_DDOS_CFG_DDOS_ODD_STAT_DUMP_DADDR_Hr = 4222, + DTB_DDOS_CFG_DDOS_ODD_STAT_DUMP_DADDR_Lr = 4223, + DTB_DDOS_CFG_DDOS_WORK_MODE_ENABLEr = 4224, + DTB_DDOS_CFG_DDOS_STAT_TABLE_LENr = 4225, + DTB_DDOS_CFG_DDOS_HASH_TABLE_LENr = 4226, + DTB_DTB_RAM_TRAF_CTRL_RAM0_0_255r = 4227, + DTB_DTB_RAM_TRAF_CTRL_RAM1_0_255r = 4228, + DTB_DTB_RAM_TRAF_CTRL_RAM2_0_255r = 4229, + DTB_DTB_RAM_TRAF_CTRL_RAM3_0_255r = 4230, + DTB_DTB_RAM_TRAF_CTRL_RAM4_0_255r = 4231, + DTB_DTB_RAM_TRAF_CTRL_RAM5_0_63r = 4232, + DTB_DTB_RAM_DUMP_PD_RAM_0_2047r = 4233, + DTB_DTB_RAM_RD_CTRL_RAM_0_4095r = 4234, + DTB_DTB_RAM_RD_TABLE_RAM_0_8191r = 4235, + DTB_DTB_RAM_DTB_CMD_MAN_RAM_0_16383r = 4236, + TRPG_TRPG_RX_PORT_CPU_TRPG_MS_STr = 4237, + TRPG_TRPG_RX_PORT_CPU_TRPG_MS_INDr = 4238, + TRPG_TRPG_RX_PORT_CPU_TRPG_MS_SLAVE_INDr = 4239, + TRPG_TRPG_RX_PORT_CPU_TRPGRX_UP_WATER_LEVELr = 4240, + TRPG_TRPG_RX_PORT_CPU_TRPGRX_LOW_WATER_LEVELr = 4241, + TRPG_TRPG_TX_PORT_CPU_TRPG_MS_STr = 4242, + TRPG_TRPG_TX_PORT_CPU_TRPG_MS_INDr = 4243, + TRPG_TRPG_TX_PORT_CPU_TRPG_MS_SLAVE_INDr = 4244, + TRPG_TRPG_TX_GLB_CPU_TODTIME_UPDATE_INT_EVENTr = 4245, + TRPG_TRPG_TX_GLB_CPU_TODTIME_UPDATE_INT_TESTr = 4246, + TRPG_TRPG_TX_GLB_CPU_TODTIME_UPDATE_INT_ADDRr = 4247, + TRPG_TRPG_TX_TODTIME_RAM_TRPG_TX_TODTIME_RAMr = 4248, + TSN_TSN_PORT_CFG_TSN_TEST_REGr = 4249, + TSN_TSN_PORT_CFG_TSN_PORT_QBV_ENABLEr = 4250, + TSN_TSN_PORT_CFG_TSN_PHY_PORT_SELr = 4251, + TSN_TSN_PORT_CFG_TSN_PORT_TIME_SELr = 4252, + TSN_TSN_PORT_CFG_TSN_CLK_FREQr = 4253, + TSN_TSN_PORT_CFG_TSN_READ_RAM_Nr = 4254, + TSN_TSN_PORT_CFG_TSN_EXE_TIMEr = 4255, + TSN_TSN_PORT_CFG_TSN_PORT_ITR_SHIFTr = 4256, + TSN_TSN_PORT_CFG_TSN_PORT_BASE_TIME_Hr = 4257, + TSN_TSN_PORT_CFG_TSN_PORT_BASE_TIME_Lr = 4258, + TSN_TSN_PORT_CFG_TSN_PORT_CYCLE_TIME_Hr = 4259, + TSN_TSN_PORT_CFG_TSN_PORT_CYCLE_TIME_Lr = 4260, + TSN_TSN_PORT_CFG_TSN_PORT_GUARD_BAND_TIMEr = 4261, + TSN_TSN_PORT_CFG_TSN_PORT_DEFAULT_GATE_ENr = 4262, + TSN_TSN_PORT_CFG_TSN_PORT_CHANGE_GATE_ENr = 4263, + TSN_TSN_PORT_CFG_TSN_PORT_INIT_FINISHr = 4264, + TSN_TSN_PORT_CFG_TSN_PORT_CHANGE_ENr = 4265, + TSN_TSN_PORT_CFG_TSN_PORT_GCL_NUM0r = 4266, + TSN_TSN_PORT_CFG_TSN_PORT_GCL_NUM1r = 4267, + TSN_TSN_PORT_CFG_TSN_PORT_GCL_VALUE0r = 4268, + TSN_TSN_PORT_CFG_TSN_PORT_GCL_VALUE1r = 4269, + AXI_AXI_CONV_CFG_EPID_V_FUNC_NUMr = 4270, + AXI_AXI_CONV_INFO_AXIM_RW_HSK_CNTr = 4271, + AXI_AXI_CONV_INFO_AXIM_LAST_WR_IDr = 4272, + AXI_AXI_CONV_INFO_AXIM_LAST_WR_ADDR_Hr = 4273, + AXI_AXI_CONV_INFO_AXIM_LAST_WR_ADDR_Lr = 4274, + AXI_AXI_CONV_CFG_DEBUG_INFO_CLR_ENr = 4275, + PTPTM_PTP_TOP_PP1S_INTERRUPTr = 4276, + PTPTM_PTP_TOP_PP1S_EXTERNAL_SELECTr = 4277, + PTPTM_PTP_TOP_PP1S_OUT_SELECTr = 4278, + PTPTM_PTP_TOP_TEST_PP1S_SELECTr = 4279, + PTPTM_PTP_TOP_LOCAL_PP1S_ENr = 4280, + PTPTM_PTP_TOP_LOCAL_PP1S_ADJUSTr = 4281, + PTPTM_PTP_TOP_LOCAL_PP1S_ADJUST_VALUEr = 4282, + PTPTM_PTP_TOP_PP1S_TO_NP_SELECTr = 4283, + PTPTM_PTP_TOP_PD_U1_SELr = 4284, + PTPTM_PTP_TOP_PD_U1_PD0_SHIFTr = 4285, + PTPTM_PTP_TOP_PD_U1_PD1_SHIFTr = 4286, + PTPTM_PTP_TOP_PD_U1_RESULTr = 4287, + PTPTM_PTP_TOP_PD_U2_SELr = 4288, + PTPTM_PTP_TOP_PD_U2_PD0_SHIFTr = 4289, + PTPTM_PTP_TOP_PD_U2_PD1_SHIFTr = 4290, + PTPTM_PTP_TOP_PD_U2_RESULTr = 4291, + PTPTM_PTP_TOP_TSN_GROUP_NANOSECOND_DELAY0r = 4292, + PTPTM_PTP_TOP_TSN_GROUP_FRACNANOSECOND_DELAY0r = 4293, + PTPTM_PTP_TOP_TSN_GROUP_NANOSECOND_DELAY1r = 4294, + PTPTM_PTP_TOP_TSN_GROUP_FRACNANOSECOND_DELAY1r = 4295, + PTPTM_PTP_TOP_TSN_GROUP_NANOSECOND_DELAY2r = 4296, + PTPTM_PTP_TOP_TSN_GROUP_FRACNANOSECOND_DELAY2r = 4297, + PTPTM_PTP_TOP_TSN_GROUP_NANOSECOND_DELAY3r = 4298, + PTPTM_PTP_TOP_TSN_GROUP_FRACNANOSECOND_DELAY3r = 4299, + PTPTM_PTP_TOP_TSN_PTP1588_RDMA_NANOSECOND_DELAYr = 4300, + PTPTM_PTP_TOP_PTP1588_RDMA_FRACNANOSECOND_DELAYr = 4301, + PTPTM_PTP_TOP_PTP1588_NP_NANOSECOND_DELAYr = 4302, + PTPTM_PTP_TOP_PTP1588_NP_FRACNANOSECOND_DELAYr = 4303, + PTPTM_PTP_TOP_TIME_SYNC_PERIODr = 4304, + PTPTM_PTPTM_MODULE_IDr = 4305, + PTPTM_PTPTM_MODULE_VERSIONr = 4306, + PTPTM_PTPTM_MODULE_DATEr = 4307, + PTPTM_PTPTM_INTERRUPT_STATUSr = 4308, + PTPTM_PTPTM_INTERRUPT_EVENTr = 4309, + PTPTM_PTPTM_INTERRUPT_MASKr = 4310, + PTPTM_PTPTM_INTERRUPT_TESTr = 4311, + PTPTM_PTPTM_HW_CLOCK_CYCLE_INTEGERr = 4312, + PTPTM_PTPTM_HW_CLOCK_CYCLE_FRACTIONr = 4313, + PTPTM_PTPTM_PTP_CLOCK_CYCLE_INTEGERr = 4314, + PTPTM_PTPTM_PTP_CLOCK_CYCLE_FRACTIONr = 4315, + PTPTM_PTPTM_PTP_CONFIGURATIONr = 4316, + PTPTM_PTPTM_TIMER_CONTROLr = 4317, + PTPTM_PTPTM_PPS_INCOME_DELAYr = 4318, + PTPTM_PTPTM_CLOCK_CYCLE_UPDATEr = 4319, + PTPTM_PTPTM_CYCLE_TIME_OF_OUTPUT_PERIOD_PULSE_1r = 4320, + PTPTM_PTPTM_CYCLE_TIME_OF_OUTPUT_PERIOD_PULSE_2r = 4321, + PTPTM_PTPTM_TIMER_LATCH_ENr = 4322, + PTPTM_PTPTM_TIMER_LATCH_SELr = 4323, + PTPTM_PTPTM_TRIGGER_IN_TOD_NANOSECONDr = 4324, + PTPTM_PTPTM_TRIGGER_IN_LOWER_TOD_SECONDr = 4325, + PTPTM_PTPTM_TRIGGER_IN_HIGH_TOD_SECONDr = 4326, + PTPTM_PTPTM_TRIGGER_IN_FRACNANOSECONDr = 4327, + PTPTM_PTPTM_TRIGGER_IN_HARDWARE_TIME_LOWr = 4328, + PTPTM_PTPTM_TRIGGER_IN_HARDWARE_TIME_HIGHr = 4329, + PTPTM_PTPTM_TRIGGER_OUT_TOD_NANOSECONDr = 4330, + PTPTM_PTPTM_TRIGGER_OUT_LOWER_TOD_SECONDr = 4331, + PTPTM_PTPTM_TRIGGER_OUT_HIGH_TOD_SECONDr = 4332, + PTPTM_PTPTM_TRIGGER_OUT_HARDWARE_TIME_LOWr = 4333, + PTPTM_PTPTM_TRIGGER_OUT_HARDWARE_TIME_HIGHr = 4334, + PTPTM_PTPTM_ADJUST_TOD_NANOSECONDr = 4335, + PTPTM_PTPTM_ADJUST_LOWER_TOD_SECONDr = 4336, + PTPTM_PTPTM_ADJUST_HIGH_TOD_SECONDr = 4337, + PTPTM_PTPTM_ADJUST_FRACNANOSECONDr = 4338, + PTPTM_PTPTM_ADJUST_HARDWARE_TIME_LOWr = 4339, + PTPTM_PTPTM_ADJUST_HARDWARE_TIME_HIGHr = 4340, + PTPTM_PTPTM_LATCH_TOD_NANOSECONDr = 4341, + PTPTM_PTPTM_LATCH_LOWER_TOD_SECONDr = 4342, + PTPTM_PTPTM_LATCH_HIGH_TOD_SECONDr = 4343, + PTPTM_PTPTM_LATCH_FRACNANOSECONDr = 4344, + PTPTM_PTPTM_LATCH_HARDWARE_TIME_LOWr = 4345, + PTPTM_PTPTM_LATCH_HARDWARE_TIME_HIGHr = 4346, + PTPTM_PTPTM_REAL_TOD_NANOSECONDr = 4347, + PTPTM_PTPTM_REAL_LOWER_TOD_SECONDr = 4348, + PTPTM_PTPTM_REAL_HIGH_TOD_SECONDr = 4349, + PTPTM_PTPTM_REAL_HARDWARE_TIME_LOWr = 4350, + PTPTM_PTPTM_REAL_HARDWARE_TIME_HIGHr = 4351, + PTPTM_PTPTM_PTP1588_EVENT_MESSAGE_PORTr = 4352, + PTPTM_PTPTM_PTP1588_EVENT_MESSAGE_TIMESTAMP_LOWr = 4353, + PTPTM_PTPTM_PTP1588_EVENT_MESSAGE_TIMESTAMP_HIGHr = 4354, + PTPTM_PTPTM_PTP1588_EVENT_MESSAGE_FIFO_STATUSr = 4355, + PTPTM_PTPTM_PP1S_LATCH_TOD_NANOSECONDr = 4356, + PTPTM_PTPTM_PP1S_LATCH_LOWER_TOD_SECONDr = 4357, + PTPTM_PTPTM_PP1S_LATCH_HIGH_TOD_SECONDr = 4358, + PTPTM_PTPTM_PP1S_LATCH_FRACNANOSECONDr = 4359, + PTPTM_PTPTM_TSN_TIME_CONFIGURATIONr = 4360, + PTPTM_PTPTM_TSN_TIMER_CONTROLr = 4361, + PTPTM_PTPTM_TSN0_CLOCK_CYCLE_INTEGERr = 4362, + PTPTM_PTPTM_TSN0_CLOCK_CYCLE_FRACTIONr = 4363, + PTPTM_PTPTM_TSN1_CLOCK_CYCLE_INTEGERr = 4364, + PTPTM_PTPTM_TSN1_CLOCK_CYCLE_FRACTIONr = 4365, + PTPTM_PTPTM_TSN2_CLOCK_CYCLE_INTEGERr = 4366, + PTPTM_PTPTM_TSN2_CLOCK_CYCLE_FRACTIONr = 4367, + PTPTM_PTPTM_TSN3_CLOCK_CYCLE_INTEGERr = 4368, + PTPTM_PTPTM_TSN3_CLOCK_CYCLE_FRACTIONr = 4369, + PTPTM_PTPTM_TSN0_ADJUST_TOD_NANOSECONDr = 4370, + PTPTM_PTPTM_TSN0_ADJUST_LOWER_TOD_SECONDr = 4371, + PTPTM_PTPTM_TSN0_ADJUST_HIGH_TOD_SECONDr = 4372, + PTPTM_PTPTM_TSN0_ADJUST_FRACNANOSECONDr = 4373, + PTPTM_PTPTM_TSN1_ADJUST_TOD_NANOSECONDr = 4374, + PTPTM_PTPTM_TSN1_ADJUST_LOWER_TOD_SECONDr = 4375, + PTPTM_PTPTM_TSN1_ADJUST_HIGH_TOD_SECONDr = 4376, + PTPTM_PTPTM_TSN1_ADJUST_FRACNANOSECONDr = 4377, + PTPTM_PTPTM_TSN2_ADJUST_TOD_NANOSECONDr = 4378, + PTPTM_PTPTM_TSN2_ADJUST_LOWER_TOD_SECONDr = 4379, + PTPTM_PTPTM_TSN2_ADJUST_HIGH_TOD_SECONDr = 4380, + PTPTM_PTPTM_TSN2_ADJUST_FRACNANOSECONDr = 4381, + PTPTM_PTPTM_TSN3_ADJUST_TOD_NANOSECONDr = 4382, + PTPTM_PTPTM_TSN3_ADJUST_LOWER_TOD_SECONDr = 4383, + PTPTM_PTPTM_TSN3_ADJUST_HIGH_TOD_SECONDr = 4384, + PTPTM_PTPTM_TSN3_ADJUST_FRACNANOSECONDr = 4385, + PTPTM_PTPTM_TSN0_LATCH_TOD_NANOSECONDr = 4386, + PTPTM_PTPTM_TSN0_LATCH_LOWER_TOD_SECONDr = 4387, + PTPTM_PTPTM_TSN0_LATCH_HIGH_TOD_SECONDr = 4388, + PTPTM_PTPTM_TSN0_LATCH_FRACNANOSECONDr = 4389, + PTPTM_PTPTM_TSN1_LATCH_TOD_NANOSECONDr = 4390, + PTPTM_PTPTM_TSN1_LATCH_LOWER_TOD_SECONDr = 4391, + PTPTM_PTPTM_TSN1_LATCH_HIGH_TOD_SECONDr = 4392, + PTPTM_PTPTM_TSN1_LATCH_FRACNANOSECONDr = 4393, + PTPTM_PTPTM_TSN2_LATCH_TOD_NANOSECONDr = 4394, + PTPTM_PTPTM_TSN2_LATCH_LOWER_TOD_SECONDr = 4395, + PTPTM_PTPTM_TSN2_LATCH_HIGH_TOD_SECONDr = 4396, + PTPTM_PTPTM_TSN2_LATCH_FRACNANOSECONDr = 4397, + PTPTM_PTPTM_TSN3_LATCH_TOD_NANOSECONDr = 4398, + PTPTM_PTPTM_TSN3_LATCH_LOWER_TOD_SECONDr = 4399, + PTPTM_PTPTM_TSN3_LATCH_HIGH_TOD_SECONDr = 4400, + PTPTM_PTPTM_TSN3_LATCH_FRACNANOSECONDr = 4401, + PTPTM_PTPTM_PP1S_LATCH_TSN0_TOD_NANOSECONDr = 4402, + PTPTM_PTPTM_PP1S_LATCH_TSN0_LOWER_TOD_SECONDr = 4403, + PTPTM_PTPTM_PP1S_LATCH_TSN0_HIGH_TOD_SECONDr = 4404, + PTPTM_PTPTM_PP1S_LATCH_TSN0_FRACNANOSECONDr = 4405, + PTPTM_PTPTM_PP1S_LATCH_TSN1_TOD_NANOSECONDr = 4406, + PTPTM_PTPTM_PP1S_LATCH_TSN1_LOWER_TOD_SECONDr = 4407, + PTPTM_PTPTM_PP1S_LATCH_TSN1_HIGH_TOD_SECONDr = 4408, + PTPTM_PTPTM_PP1S_LATCH_TSN1_FRACNANOSECONDr = 4409, + PTPTM_PTPTM_PP1S_LATCH_TSN2_TOD_NANOSECONDr = 4410, + PTPTM_PTPTM_PP1S_LATCH_TSN2_LOWER_TOD_SECONDr = 4411, + PTPTM_PTPTM_PP1S_LATCH_TSN2_HIGH_TOD_SECONDr = 4412, + PTPTM_PTPTM_PP1S_LATCH_TSN2_FRACNANOSECONDr = 4413, + PTPTM_PTPTM_PP1S_LATCH_TSN3_TOD_NANOSECONDr = 4414, + PTPTM_PTPTM_PP1S_LATCH_TSN3_LOWER_TOD_SECONDr = 4415, + PTPTM_PTPTM_PP1S_LATCH_TSN3_HIGH_TOD_SECONDr = 4416, + PTPTM_PTPTM_PP1S_LATCH_TSN3_FRACNANOSECONDr = 4417, + PTPTM_PTPTM_TSN0_REAL_TOD_NANOSECONDr = 4418, + PTPTM_PTPTM_TSN0_REAL_LOWER_TOD_SECONDr = 4419, + PTPTM_PTPTM_TSN0_REAL_HIGH_TOD_SECONDr = 4420, + PTPTM_PTPTM_TSN1_REAL_TOD_NANOSECONDr = 4421, + PTPTM_PTPTM_TSN1_REAL_LOWER_TOD_SECONDr = 4422, + PTPTM_PTPTM_TSN1_REAL_HIGH_TOD_SECONDr = 4423, + PTPTM_PTPTM_TSN2_REAL_TOD_NANOSECONDr = 4424, + PTPTM_PTPTM_TSN2_REAL_LOWER_TOD_SECONDr = 4425, + PTPTM_PTPTM_TSN2_REAL_HIGH_TOD_SECONDr = 4426, + PTPTM_PTPTM_TSN3_REAL_TOD_NANOSECONDr = 4427, + PTPTM_PTPTM_TSN3_REAL_LOWER_TOD_SECONDr = 4428, + PTPTM_PTPTM_TSN3_REAL_HIGH_TOD_SECONDr = 4429, + PTPTM_PTPTM_REAL_PTP_CLOCK_CYCLE_INTEGERr = 4430, + PTPTM_PTPTM_REAL_PTP_CLOCK_CYCLE_FRACTIONr = 4431, + PTPTM_PTPTM_REAL_TSN0_CLOCK_CYCLE_INTEGERr = 4432, + PTPTM_PTPTM_REAL_TSN0_CLOCK_CYCLE_FRACTIONr = 4433, + PTPTM_PTPTM_REAL_TSN1_CLOCK_CYCLE_INTEGERr = 4434, + PTPTM_PTPTM_REAL_TSN1_CLOCK_CYCLE_FRACTIONr = 4435, + PTPTM_PTPTM_REAL_TSN2_CLOCK_CYCLE_INTEGERr = 4436, + PTPTM_PTPTM_REAL_TSN2_CLOCK_CYCLE_FRACTIONr = 4437, + PTPTM_PTPTM_REAL_TSN3_CLOCK_CYCLE_INTEGERr = 4438, + PTPTM_PTPTM_REAL_TSN3_CLOCK_CYCLE_FRACTIONr = 4439, + REG_ENUM_MAX_VALUE +}DPP_REG_INFO_E; + +#ifdef __cplusplus +} +#endif +#endif + diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_reg_struct.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_reg_struct.h new file mode 100755 index 0000000..a91092c --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_reg_struct.h @@ -0,0 +1,88 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_reg_struct.h +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : 石金锋 +* 完成日期 : 2014/02/10 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ +#ifndef _DPP_REG_STRUCT_H_ +#define _DPP_REG_STRUCT_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "zxic_common.h" +#include "dpp_dev.h" +#include "dpp_type_api.h" + + +typedef ZXIC_UINT32 (*DPP_REG_WRITE)(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 *p_data); +typedef ZXIC_UINT32 (*DPP_REG_READ)(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 *p_data); + + +#define DPP_FIELD_FLAG_RO (1<<0) /* 只读标志 */ +#define DPP_FIELD_FLAG_RW (1<<1) /* 读写标志 */ +#define DPP_FIELD_FLAG_RC (1<<2) /* 读清标志 */ +#define DPP_FIELD_FLAG_WO (1<<3) /* 只写标志 */ +#define DPP_FIELD_FLAG_WC (1<<4) /* 写清标志 */ + +typedef struct dpp_field_t +{ + ZXIC_CHAR *p_name; /* 字段名 */ + ZXIC_UINT32 flags; /* 标志位 */ + ZXIC_UINT16 msb_pos; /* 最高比特位置，以寄存器列表为准*/ + ZXIC_UINT16 len; /* 字段长度，以比特为单位 */ + ZXIC_UINT32 default_value; /* 缺省值 */ + ZXIC_UINT32 default_step; /* 缺省值步长*/ +}DPP_FIELD_T; + + +#define DPP_REG_FLAG_DIRECT (0<<0) /* 直接读写寄存器 */ +#define DPP_REG_FLAG_INDIRECT (1<<0) /* 间接读写寄存器 */ +#define DPP_REG_FLAG_WO (1<<1) /* 只写寄存器 */ + +#define DPP_REG_NUL_ARRAY (0<<0) /*零元寄存器序列 */ +#define DPP_REG_UNI_ARRAY (1<<0) /*一元寄存器序列 */ +#define DPP_REG_BIN_ARRAY (1<<1) /*二元寄存器序列 */ + +typedef struct dpp_reg_t +{ + ZXIC_CHAR *reg_name; /* 寄存器名称*/ + ZXIC_UINT32 reg_no; /* 寄存器的编号 */ + ZXIC_UINT32 module_no; /* 寄存器归属的模块的编号 */ + ZXIC_UINT32 flags; /* 标志位 */ + ZXIC_UINT32 array_type; /* 寄存器偏移类型*/ + ZXIC_UINT32 addr; /* 寄存器的芯片地址*/ + ZXIC_UINT32 width; /* 寄存器位宽，以字节为单位 */ + ZXIC_UINT32 m_size; /* 寄存器序列参数1的个数 */ + ZXIC_UINT32 n_size; /* 寄存器序列参数2的个数*/ + ZXIC_UINT32 m_step; /* 寄存器序列参数1的偏移步长 */ + ZXIC_UINT32 n_step; /* 寄存器序列参数2的偏移步长 */ + ZXIC_UINT32 field_num; /* 包含的字段个数 */ + DPP_FIELD_T *p_fields; /* 寄存器所有字段 */ + + DPP_REG_WRITE p_write_fun; /* 寄存器写函数 */ + DPP_REG_READ p_read_fun; /* 寄存器读函数 */ +}DPP_REG_T; + + +#ifdef __cplusplus +} +#endif + +#endif + + + diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_se4k_reg.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_se4k_reg.h new file mode 100644 index 0000000..4ab258c --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_se4k_reg.h @@ -0,0 +1,334 @@ + +#ifndef _DPP_SE4K_REG_H_ +#define _DPP_SE4K_REG_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +typedef struct dpp_se4k_se_alg_cpu_cmd_rgt_t +{ + ZXIC_UINT32 rd_flag; + ZXIC_UINT32 mask; + ZXIC_UINT32 reg_sram_flag; + ZXIC_UINT32 zgroup_id; + ZXIC_UINT32 zblock_id; + ZXIC_UINT32 zcell_id; + ZXIC_UINT32 addr; +}DPP_SE4K_SE_ALG_CPU_CMD_RGT_T; + +typedef struct dpp_se4k_se_alg_cpu_wr_data_tmp0_t +{ + ZXIC_UINT32 cpu_wr_data_tmp0; +}DPP_SE4K_SE_ALG_CPU_WR_DATA_TMP0_T; + +typedef struct dpp_se4k_se_alg_cpu_wr_data_tmp1_t +{ + ZXIC_UINT32 cpu_wr_data_tmp1; +}DPP_SE4K_SE_ALG_CPU_WR_DATA_TMP1_T; + +typedef struct dpp_se4k_se_alg_cpu_wr_data_tmp2_t +{ + ZXIC_UINT32 cpu_wr_data_tmp2; +}DPP_SE4K_SE_ALG_CPU_WR_DATA_TMP2_T; + +typedef struct dpp_se4k_se_alg_cpu_wr_data_tmp3_t +{ + ZXIC_UINT32 cpu_wr_data_tmp3; +}DPP_SE4K_SE_ALG_CPU_WR_DATA_TMP3_T; + +typedef struct dpp_se4k_se_alg_cpu_wr_data_tmp4_t +{ + ZXIC_UINT32 cpu_wr_data_tmp4; +}DPP_SE4K_SE_ALG_CPU_WR_DATA_TMP4_T; + +typedef struct dpp_se4k_se_alg_cpu_wr_data_tmp5_t +{ + ZXIC_UINT32 cpu_wr_data_tmp5; +}DPP_SE4K_SE_ALG_CPU_WR_DATA_TMP5_T; + +typedef struct dpp_se4k_se_alg_cpu_wr_data_tmp6_t +{ + ZXIC_UINT32 cpu_wr_data_tmp6; +}DPP_SE4K_SE_ALG_CPU_WR_DATA_TMP6_T; + +typedef struct dpp_se4k_se_alg_cpu_wr_data_tmp7_t +{ + ZXIC_UINT32 cpu_wr_data_tmp7; +}DPP_SE4K_SE_ALG_CPU_WR_DATA_TMP7_T; + +typedef struct dpp_se4k_se_alg_cpu_wr_data_tmp8_t +{ + ZXIC_UINT32 cpu_wr_data_tmp8; +}DPP_SE4K_SE_ALG_CPU_WR_DATA_TMP8_T; + +typedef struct dpp_se4k_se_alg_cpu_wr_data_tmp9_t +{ + ZXIC_UINT32 cpu_wr_data_tmp9; +}DPP_SE4K_SE_ALG_CPU_WR_DATA_TMP9_T; + +typedef struct dpp_se4k_se_alg_cpu_wr_data_tmp10_t +{ + ZXIC_UINT32 cpu_wr_data_tmp10; +}DPP_SE4K_SE_ALG_CPU_WR_DATA_TMP10_T; + +typedef struct dpp_se4k_se_alg_cpu_wr_data_tmp11_t +{ + ZXIC_UINT32 cpu_wr_data_tmp11; +}DPP_SE4K_SE_ALG_CPU_WR_DATA_TMP11_T; + +typedef struct dpp_se4k_se_alg_cpu_wr_data_tmp12_t +{ + ZXIC_UINT32 cpu_wr_data_tmp12; +}DPP_SE4K_SE_ALG_CPU_WR_DATA_TMP12_T; + +typedef struct dpp_se4k_se_alg_cpu_wr_data_tmp13_t +{ + ZXIC_UINT32 cpu_wr_data_tmp13; +}DPP_SE4K_SE_ALG_CPU_WR_DATA_TMP13_T; + +typedef struct dpp_se4k_se_alg_cpu_wr_data_tmp14_t +{ + ZXIC_UINT32 cpu_wr_data_tmp14; +}DPP_SE4K_SE_ALG_CPU_WR_DATA_TMP14_T; + +typedef struct dpp_se4k_se_alg_cpu_wr_data_tmp15_t +{ + ZXIC_UINT32 cpu_wr_data_tmp15; +}DPP_SE4K_SE_ALG_CPU_WR_DATA_TMP15_T; + +typedef struct dpp_se4k_se_alg_cpu_rd_rdy_t +{ + ZXIC_UINT32 cpu_rd_rdy; +}DPP_SE4K_SE_ALG_CPU_RD_RDY_T; + +typedef struct dpp_se4k_se_alg_cpu_rd_data_tmp0_t +{ + ZXIC_UINT32 cpu_rd_data_tmp0; +}DPP_SE4K_SE_ALG_CPU_RD_DATA_TMP0_T; + +typedef struct dpp_se4k_se_alg_cpu_rd_data_tmp1_t +{ + ZXIC_UINT32 cpu_rd_data_tmp1; +}DPP_SE4K_SE_ALG_CPU_RD_DATA_TMP1_T; + +typedef struct dpp_se4k_se_alg_cpu_rd_data_tmp2_t +{ + ZXIC_UINT32 cpu_rd_data_tmp2; +}DPP_SE4K_SE_ALG_CPU_RD_DATA_TMP2_T; + +typedef struct dpp_se4k_se_alg_cpu_rd_data_tmp3_t +{ + ZXIC_UINT32 cpu_rd_data_tmp3; +}DPP_SE4K_SE_ALG_CPU_RD_DATA_TMP3_T; + +typedef struct dpp_se4k_se_alg_cpu_rd_data_tmp4_t +{ + ZXIC_UINT32 cpu_rd_data_tmp4; +}DPP_SE4K_SE_ALG_CPU_RD_DATA_TMP4_T; + +typedef struct dpp_se4k_se_alg_cpu_rd_data_tmp5_t +{ + ZXIC_UINT32 cpu_rd_data_tmp5; +}DPP_SE4K_SE_ALG_CPU_RD_DATA_TMP5_T; + +typedef struct dpp_se4k_se_alg_cpu_rd_data_tmp6_t +{ + ZXIC_UINT32 cpu_rd_data_tmp6; +}DPP_SE4K_SE_ALG_CPU_RD_DATA_TMP6_T; + +typedef struct dpp_se4k_se_alg_cpu_rd_data_tmp7_t +{ + ZXIC_UINT32 cpu_rd_data_tmp7; +}DPP_SE4K_SE_ALG_CPU_RD_DATA_TMP7_T; + +typedef struct dpp_se4k_se_alg_cpu_rd_data_tmp8_t +{ + ZXIC_UINT32 cpu_rd_data_tmp8; +}DPP_SE4K_SE_ALG_CPU_RD_DATA_TMP8_T; + +typedef struct dpp_se4k_se_alg_cpu_rd_data_tmp9_t +{ + ZXIC_UINT32 cpu_rd_data_tmp9; +}DPP_SE4K_SE_ALG_CPU_RD_DATA_TMP9_T; + +typedef struct dpp_se4k_se_alg_cpu_rd_data_tmp10_t +{ + ZXIC_UINT32 cpu_rd_data_tmp10; +}DPP_SE4K_SE_ALG_CPU_RD_DATA_TMP10_T; + +typedef struct dpp_se4k_se_alg_cpu_rd_data_tmp11_t +{ + ZXIC_UINT32 cpu_rd_data_tmp11; +}DPP_SE4K_SE_ALG_CPU_RD_DATA_TMP11_T; + +typedef struct dpp_se4k_se_alg_cpu_rd_data_tmp12_t +{ + ZXIC_UINT32 cpu_rd_data_tmp12; +}DPP_SE4K_SE_ALG_CPU_RD_DATA_TMP12_T; + +typedef struct dpp_se4k_se_alg_cpu_rd_data_tmp13_t +{ + ZXIC_UINT32 cpu_rd_data_tmp13; +}DPP_SE4K_SE_ALG_CPU_RD_DATA_TMP13_T; + +typedef struct dpp_se4k_se_alg_cpu_rd_data_tmp14_t +{ + ZXIC_UINT32 cpu_rd_data_tmp14; +}DPP_SE4K_SE_ALG_CPU_RD_DATA_TMP14_T; + +typedef struct dpp_se4k_se_alg_cpu_rd_data_tmp15_t +{ + ZXIC_UINT32 cpu_rd_data_tmp15; +}DPP_SE4K_SE_ALG_CPU_RD_DATA_TMP15_T; + +typedef struct dpp_se4k_se_alg_hash0_ext_cfg_rgt_t +{ + ZXIC_UINT32 hash0_ext_mode; + ZXIC_UINT32 hash0_ext_flag; +}DPP_SE4K_SE_ALG_HASH0_EXT_CFG_RGT_T; + +typedef struct dpp_se4k_se_alg_hash1_ext_cfg_rgt_t +{ + ZXIC_UINT32 hash1_ext_mode; + ZXIC_UINT32 hash1_ext_flag; +}DPP_SE4K_SE_ALG_HASH1_EXT_CFG_RGT_T; + +typedef struct dpp_se4k_se_alg_hash2_ext_cfg_rgt_t +{ + ZXIC_UINT32 hash2_ext_mode; + ZXIC_UINT32 hash2_ext_flag; +}DPP_SE4K_SE_ALG_HASH2_EXT_CFG_RGT_T; + +typedef struct dpp_se4k_se_alg_hash3_ext_cfg_rgt_t +{ + ZXIC_UINT32 hash3_ext_mode; + ZXIC_UINT32 hash3_ext_flag; +}DPP_SE4K_SE_ALG_HASH3_EXT_CFG_RGT_T; + +typedef struct dpp_se4k_se_alg_hash0_tbl30_depth_t +{ + ZXIC_UINT32 hash0_tbl3_depth; + ZXIC_UINT32 hash0_tbl2_depth; + ZXIC_UINT32 hash0_tbl1_depth; + ZXIC_UINT32 hash0_tbl0_depth; +}DPP_SE4K_SE_ALG_HASH0_TBL30_DEPTH_T; + +typedef struct dpp_se4k_se_alg_hash0_tbl74_depth_t +{ + ZXIC_UINT32 hash0_tbl7_depth; + ZXIC_UINT32 hash0_tbl6_depth; + ZXIC_UINT32 hash0_tbl5_depth; + ZXIC_UINT32 hash0_tbl4_depth; +}DPP_SE4K_SE_ALG_HASH0_TBL74_DEPTH_T; + +typedef struct dpp_se4k_se_alg_hash1_tbl30_depth_t +{ + ZXIC_UINT32 hash1_tbl3_depth; + ZXIC_UINT32 hash1_tbl2_depth; + ZXIC_UINT32 hash1_tbl1_depth; + ZXIC_UINT32 hash1_tbl0_depth; +}DPP_SE4K_SE_ALG_HASH1_TBL30_DEPTH_T; + +typedef struct dpp_se4k_se_alg_hash1_tbl74_depth_t +{ + ZXIC_UINT32 hash1_tbl7_depth; + ZXIC_UINT32 hash1_tbl6_depth; + ZXIC_UINT32 hash1_tbl5_depth; + ZXIC_UINT32 hash1_tbl4_depth; +}DPP_SE4K_SE_ALG_HASH1_TBL74_DEPTH_T; + +typedef struct dpp_se4k_se_alg_hash2_tbl30_depth_t +{ + ZXIC_UINT32 hash2_tbl3_depth; + ZXIC_UINT32 hash2_tbl2_depth; + ZXIC_UINT32 hash2_tbl1_depth; + ZXIC_UINT32 hash2_tbl0_depth; +}DPP_SE4K_SE_ALG_HASH2_TBL30_DEPTH_T; + +typedef struct dpp_se4k_se_alg_hash2_tbl74_depth_t +{ + ZXIC_UINT32 hash2_tbl7_depth; + ZXIC_UINT32 hash2_tbl6_depth; + ZXIC_UINT32 hash2_tbl5_depth; + ZXIC_UINT32 hash2_tbl4_depth; +}DPP_SE4K_SE_ALG_HASH2_TBL74_DEPTH_T; + +typedef struct dpp_se4k_se_alg_hash3_tbl30_depth_t +{ + ZXIC_UINT32 hash3_tbl3_depth; + ZXIC_UINT32 hash3_tbl2_depth; + ZXIC_UINT32 hash3_tbl1_depth; + ZXIC_UINT32 hash3_tbl0_depth; +}DPP_SE4K_SE_ALG_HASH3_TBL30_DEPTH_T; + +typedef struct dpp_se4k_se_alg_hash3_tbl74_depth_t +{ + ZXIC_UINT32 hash3_tbl7_depth; + ZXIC_UINT32 hash3_tbl6_depth; + ZXIC_UINT32 hash3_tbl5_depth; + ZXIC_UINT32 hash3_tbl4_depth; +}DPP_SE4K_SE_ALG_HASH3_TBL74_DEPTH_T; + +typedef struct dpp_se4k_se_alg_wr_rsp_cfg_t +{ + ZXIC_UINT32 wr_rsp_fifo_cfg; +}DPP_SE4K_SE_ALG_WR_RSP_CFG_T; + +typedef struct dpp_se4k_se_alg_hash_mono_flag_t +{ + ZXIC_UINT32 hash3_mono_flag; + ZXIC_UINT32 hash2_mono_flag; + ZXIC_UINT32 hash1_mono_flag; + ZXIC_UINT32 hash0_mono_flag; +}DPP_SE4K_SE_ALG_HASH_MONO_FLAG_T; + +typedef struct dpp_se4k_se_alg_hash10_ext_crc_cfg_t +{ + ZXIC_UINT32 hash1_crc_cfg; + ZXIC_UINT32 hash0_crc_cfg; +}DPP_SE4K_SE_ALG_HASH10_EXT_CRC_CFG_T; + +typedef struct dpp_se4k_se_alg_hash32_ext_crc_cfg_t +{ + ZXIC_UINT32 hash3_crc_cfg; + ZXIC_UINT32 hash2_crc_cfg; +}DPP_SE4K_SE_ALG_HASH32_EXT_CRC_CFG_T; + +typedef struct dpp_se4k_se_alg_zblock_service_configure_t +{ + ZXIC_UINT32 service_sel; + ZXIC_UINT32 hash_channel_sel; + ZXIC_UINT32 st_en; +}DPP_SE4K_SE_ALG_ZBLOCK_SERVICE_CONFIGURE_T; + +typedef struct dpp_se4k_se_alg_zblock_hash_zcell_mono_t +{ + ZXIC_UINT32 ha_zcell3_mono_flag; + ZXIC_UINT32 ha_zcell3_tbl_id; + ZXIC_UINT32 ha_zcell2_mono_flag; + ZXIC_UINT32 ha_zcell2_tbl_id; + ZXIC_UINT32 ha_zcell1_mono_flag; + ZXIC_UINT32 ha_zcell1_tbl_id; + ZXIC_UINT32 ha_zcell0_mono_flag; + ZXIC_UINT32 ha_zcell0_tbl_id; +}DPP_SE4K_SE_ALG_ZBLOCK_HASH_ZCELL_MONO_T; + +typedef struct dpp_se4k_se_alg_zlock_hash_zreg_mono_t +{ + ZXIC_UINT32 ha_zreg3_mono_flag; + ZXIC_UINT32 ha_zreg3_tbl_id; + ZXIC_UINT32 ha_zreg2_mono_flag; + ZXIC_UINT32 ha_zreg2_tbl_id; + ZXIC_UINT32 ha_zreg1_mono_flag; + ZXIC_UINT32 ha_zreg1_tbl_id; + ZXIC_UINT32 ha_zreg0_mono_flag; + ZXIC_UINT32 ha_zreg0_tbl_id; +}DPP_SE4K_SE_ALG_ZLOCK_HASH_ZREG_MONO_T; + + +#ifdef __cplusplus +} +#endif +#endif + diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_se_reg.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_se_reg.h new file mode 100644 index 0000000..2328ea6 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_se_reg.h @@ -0,0 +1,3438 @@ + +#ifndef _DPP_SE_REG_H_ +#define _DPP_SE_REG_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +typedef struct dpp_se_alg_init_ok_t +{ + ZXIC_UINT32 init_ok; +}DPP_SE_ALG_INIT_OK_T; + +typedef struct dpp_se_alg_cpu_rd_rdy_t +{ + ZXIC_UINT32 cpu_rd_rdy; +}DPP_SE_ALG_CPU_RD_RDY_T; + +typedef struct dpp_se_alg_cpu_rd_data_tmp0_t +{ + ZXIC_UINT32 cpu_rd_data_tmp0; +}DPP_SE_ALG_CPU_RD_DATA_TMP0_T; + +typedef struct dpp_se_alg_cpu_rd_data_tmp1_t +{ + ZXIC_UINT32 cpu_rd_data_tmp1; +}DPP_SE_ALG_CPU_RD_DATA_TMP1_T; + +typedef struct dpp_se_alg_cpu_rd_data_tmp2_t +{ + ZXIC_UINT32 cpu_rd_data_tmp2; +}DPP_SE_ALG_CPU_RD_DATA_TMP2_T; + +typedef struct dpp_se_alg_cpu_rd_data_tmp3_t +{ + ZXIC_UINT32 cpu_rd_data_tmp3; +}DPP_SE_ALG_CPU_RD_DATA_TMP3_T; + +typedef struct dpp_se_alg_cpu_rd_data_tmp4_t +{ + ZXIC_UINT32 cpu_rd_data_tmp4; +}DPP_SE_ALG_CPU_RD_DATA_TMP4_T; + +typedef struct dpp_se_alg_cpu_rd_data_tmp5_t +{ + ZXIC_UINT32 cpu_rd_data_tmp5; +}DPP_SE_ALG_CPU_RD_DATA_TMP5_T; + +typedef struct dpp_se_alg_cpu_rd_data_tmp6_t +{ + ZXIC_UINT32 cpu_rd_data_tmp6; +}DPP_SE_ALG_CPU_RD_DATA_TMP6_T; + +typedef struct dpp_se_alg_cpu_rd_data_tmp7_t +{ + ZXIC_UINT32 cpu_rd_data_tmp7; +}DPP_SE_ALG_CPU_RD_DATA_TMP7_T; + +typedef struct dpp_se_alg_cpu_rd_data_tmp8_t +{ + ZXIC_UINT32 cpu_rd_data_tmp8; +}DPP_SE_ALG_CPU_RD_DATA_TMP8_T; + +typedef struct dpp_se_alg_cpu_rd_data_tmp9_t +{ + ZXIC_UINT32 cpu_rd_data_tmp9; +}DPP_SE_ALG_CPU_RD_DATA_TMP9_T; + +typedef struct dpp_se_alg_cpu_rd_data_tmp10_t +{ + ZXIC_UINT32 cpu_rd_data_tmp10; +}DPP_SE_ALG_CPU_RD_DATA_TMP10_T; + +typedef struct dpp_se_alg_cpu_rd_data_tmp11_t +{ + ZXIC_UINT32 cpu_rd_data_tmp11; +}DPP_SE_ALG_CPU_RD_DATA_TMP11_T; + +typedef struct dpp_se_alg_cpu_rd_data_tmp12_t +{ + ZXIC_UINT32 cpu_rd_data_tmp12; +}DPP_SE_ALG_CPU_RD_DATA_TMP12_T; + +typedef struct dpp_se_alg_cpu_rd_data_tmp13_t +{ + ZXIC_UINT32 cpu_rd_data_tmp13; +}DPP_SE_ALG_CPU_RD_DATA_TMP13_T; + +typedef struct dpp_se_alg_cpu_rd_data_tmp14_t +{ + ZXIC_UINT32 cpu_rd_data_tmp14; +}DPP_SE_ALG_CPU_RD_DATA_TMP14_T; + +typedef struct dpp_se_alg_cpu_rd_data_tmp15_t +{ + ZXIC_UINT32 cpu_rd_data_tmp15; +}DPP_SE_ALG_CPU_RD_DATA_TMP15_T; + +typedef struct dpp_se_alg_lpm_v4_config_rgt_t +{ + ZXIC_UINT32 lpm_v4_shift_sel; + ZXIC_UINT32 lpm_v4_sram_cmp_flag; + ZXIC_UINT32 lpm_v4_ddr3_addr_sel; +}DPP_SE_ALG_LPM_V4_CONFIG_RGT_T; + +typedef struct dpp_se_alg_lpm_v6_config_rgt_t +{ + ZXIC_UINT32 lpm_v6_shift_sel; + ZXIC_UINT32 lpm_v6_sram_cmp_flag; + ZXIC_UINT32 lpm_v6_ddr3_addr_sel; +}DPP_SE_ALG_LPM_V6_CONFIG_RGT_T; + +typedef struct dpp_se_alg_lpm_ext_rsp_fifo_u0_pfull_ast_t +{ + ZXIC_UINT32 lpm_ext_rsp_fifo_u0_pfull_ast; +}DPP_SE_ALG_LPM_EXT_RSP_FIFO_U0_PFULL_AST_T; + +typedef struct dpp_se_as_hash_age_pat_cfg_t +{ + ZXIC_UINT32 hash_age_pat_cfg; +}DPP_SE_AS_HASH_AGE_PAT_CFG_T; + +typedef struct dpp_se_as_learn_rdy_cfg_t +{ + ZXIC_UINT32 learn_rdy_cfg; +}DPP_SE_AS_LEARN_RDY_CFG_T; + +typedef struct dpp_se_kschd_kschd_as_pful_cfg_t +{ + ZXIC_UINT32 kschd_as_pful_cfg; +}DPP_SE_KSCHD_KSCHD_AS_PFUL_CFG_T; + +typedef struct dpp_se_kschd_kschd_dir_pful_cfg_t +{ + ZXIC_UINT32 kschd_dir_pful_cfg; +}DPP_SE_KSCHD_KSCHD_DIR_PFUL_CFG_T; + +typedef struct dpp_se_kschd_kschd_as_ept_cfg_t +{ + ZXIC_UINT32 kschd_as_ept_cfg; +}DPP_SE_KSCHD_KSCHD_AS_EPT_CFG_T; + +typedef struct dpp_se_kschd_cpu_arbi_pful_cfg_t +{ + ZXIC_UINT32 cpu_arbi_pful_cfg; +}DPP_SE_KSCHD_CPU_ARBI_PFUL_CFG_T; + +typedef struct dpp_se_kschd_kschd_pbu_pful_cfg_t +{ + ZXIC_UINT32 kschd_pbu_pful_cfg; +}DPP_SE_KSCHD_KSCHD_PBU_PFUL_CFG_T; + +typedef struct dpp_se_rschd_rschd_dir_pful_cfg_t +{ + ZXIC_UINT32 rschd_dir_pful_cfg; +}DPP_SE_RSCHD_RSCHD_DIR_PFUL_CFG_T; + +typedef struct dpp_se_rschd_rschd_dir_ept_cfg_t +{ + ZXIC_UINT32 rschd_dir_ept_cfg; +}DPP_SE_RSCHD_RSCHD_DIR_EPT_CFG_T; + +typedef struct dpp_se_cfg_ppu_soft_rst_t +{ + ZXIC_UINT32 ppu_soft_rst; +}DPP_SE_CFG_PPU_SOFT_RST_T; + +typedef struct dpp_se_cfg_ept_flag_t +{ + ZXIC_UINT32 ept_flag; +}DPP_SE_CFG_EPT_FLAG_T; + +typedef struct dpp_se_cfg_ddr_key_lk0_3_t +{ + ZXIC_UINT32 ddr_key_lk0_3; +}DPP_SE_CFG_DDR_KEY_LK0_3_T; + +typedef struct dpp_se_cfg_ddr_key_lk0_2_t +{ + ZXIC_UINT32 ddr_key_lk0_2; +}DPP_SE_CFG_DDR_KEY_LK0_2_T; + +typedef struct dpp_se_cfg_ddr_key_lk0_1_t +{ + ZXIC_UINT32 ddr_key_lk0_1; +}DPP_SE_CFG_DDR_KEY_LK0_1_T; + +typedef struct dpp_se_cfg_ddr_key_lk0_0_t +{ + ZXIC_UINT32 ddr_key_lk0_0; +}DPP_SE_CFG_DDR_KEY_LK0_0_T; + +typedef struct dpp_se_cfg_ddr_key_lk1_3_t +{ + ZXIC_UINT32 ddr_key_lk1_3; +}DPP_SE_CFG_DDR_KEY_LK1_3_T; + +typedef struct dpp_se_cfg_ddr_key_lk1_2_t +{ + ZXIC_UINT32 ddr_key_lk1_2; +}DPP_SE_CFG_DDR_KEY_LK1_2_T; + +typedef struct dpp_se_cfg_ddr_key_lk1_1_t +{ + ZXIC_UINT32 ddr_key_lk1_1; +}DPP_SE_CFG_DDR_KEY_LK1_1_T; + +typedef struct dpp_se_cfg_ddr_key_lk1_0_t +{ + ZXIC_UINT32 ddr_key_lk1_0; +}DPP_SE_CFG_DDR_KEY_LK1_0_T; + +typedef struct dpp_se_cfg_hash_key_lk0_18_t +{ + ZXIC_UINT32 hash_key_lk0_18; +}DPP_SE_CFG_HASH_KEY_LK0_18_T; + +typedef struct dpp_se_cfg_hash_key_lk0_17_t +{ + ZXIC_UINT32 hash_key_lk0_17; +}DPP_SE_CFG_HASH_KEY_LK0_17_T; + +typedef struct dpp_se_cfg_hash_key_lk0_16_t +{ + ZXIC_UINT32 hash_key_lk0_16; +}DPP_SE_CFG_HASH_KEY_LK0_16_T; + +typedef struct dpp_se_cfg_hash_key_lk0_15_t +{ + ZXIC_UINT32 hash_key_lk0_15; +}DPP_SE_CFG_HASH_KEY_LK0_15_T; + +typedef struct dpp_se_cfg_hash_key_lk0_14_t +{ + ZXIC_UINT32 hash_key_lk0_14; +}DPP_SE_CFG_HASH_KEY_LK0_14_T; + +typedef struct dpp_se_cfg_hash_key_lk0_13_t +{ + ZXIC_UINT32 hash_key_lk0_13; +}DPP_SE_CFG_HASH_KEY_LK0_13_T; + +typedef struct dpp_se_cfg_hash_key_lk0_12_t +{ + ZXIC_UINT32 hash_key_lk0_12; +}DPP_SE_CFG_HASH_KEY_LK0_12_T; + +typedef struct dpp_se_cfg_hash_key_lk0_11_t +{ + ZXIC_UINT32 hash_key_lk0_11; +}DPP_SE_CFG_HASH_KEY_LK0_11_T; + +typedef struct dpp_se_cfg_hash_key_lk0_10_t +{ + ZXIC_UINT32 hash_key_lk0_10; +}DPP_SE_CFG_HASH_KEY_LK0_10_T; + +typedef struct dpp_se_cfg_hash_key_lk0_9_t +{ + ZXIC_UINT32 hash_key_lk0_9; +}DPP_SE_CFG_HASH_KEY_LK0_9_T; + +typedef struct dpp_se_cfg_hash_key_lk0_8_t +{ + ZXIC_UINT32 hash_key_lk0_8; +}DPP_SE_CFG_HASH_KEY_LK0_8_T; + +typedef struct dpp_se_cfg_hash_key_lk0_7_t +{ + ZXIC_UINT32 hash_key_lk0_7; +}DPP_SE_CFG_HASH_KEY_LK0_7_T; + +typedef struct dpp_se_cfg_hash_key_lk0_6_t +{ + ZXIC_UINT32 hash_key_lk0_6; +}DPP_SE_CFG_HASH_KEY_LK0_6_T; + +typedef struct dpp_se_cfg_hash_key_lk0_5_t +{ + ZXIC_UINT32 hash_key_lk0_5; +}DPP_SE_CFG_HASH_KEY_LK0_5_T; + +typedef struct dpp_se_cfg_hash_key_lk0_4_t +{ + ZXIC_UINT32 hash_key_lk0_4; +}DPP_SE_CFG_HASH_KEY_LK0_4_T; + +typedef struct dpp_se_cfg_hash_key_lk0_3_t +{ + ZXIC_UINT32 hash_key_lk0_3; +}DPP_SE_CFG_HASH_KEY_LK0_3_T; + +typedef struct dpp_se_cfg_hash_key_lk0_2_t +{ + ZXIC_UINT32 hash_key_lk0_2; +}DPP_SE_CFG_HASH_KEY_LK0_2_T; + +typedef struct dpp_se_cfg_hash_key_lk0_1_t +{ + ZXIC_UINT32 hash_key_lk0_1; +}DPP_SE_CFG_HASH_KEY_LK0_1_T; + +typedef struct dpp_se_cfg_hash_key_lk0_0_t +{ + ZXIC_UINT32 hash_key_lk0_0; +}DPP_SE_CFG_HASH_KEY_LK0_0_T; + +typedef struct dpp_se_cfg_hash_key_lk1_18_t +{ + ZXIC_UINT32 hash_key_lk1_18; +}DPP_SE_CFG_HASH_KEY_LK1_18_T; + +typedef struct dpp_se_cfg_hash_key_lk1_17_t +{ + ZXIC_UINT32 hash_key_lk1_17; +}DPP_SE_CFG_HASH_KEY_LK1_17_T; + +typedef struct dpp_se_cfg_hash_key_lk1_16_t +{ + ZXIC_UINT32 hash_key_lk1_16; +}DPP_SE_CFG_HASH_KEY_LK1_16_T; + +typedef struct dpp_se_cfg_hash_key_lk1_15_t +{ + ZXIC_UINT32 hash_key_lk1_15; +}DPP_SE_CFG_HASH_KEY_LK1_15_T; + +typedef struct dpp_se_cfg_hash_key_lk1_14_t +{ + ZXIC_UINT32 hash_key_lk1_14; +}DPP_SE_CFG_HASH_KEY_LK1_14_T; + +typedef struct dpp_se_cfg_hash_key_lk1_13_t +{ + ZXIC_UINT32 hash_key_lk1_13; +}DPP_SE_CFG_HASH_KEY_LK1_13_T; + +typedef struct dpp_se_cfg_hash_key_lk1_12_t +{ + ZXIC_UINT32 hash_key_lk1_12; +}DPP_SE_CFG_HASH_KEY_LK1_12_T; + +typedef struct dpp_se_cfg_hash_key_lk1_11_t +{ + ZXIC_UINT32 hash_key_lk1_11; +}DPP_SE_CFG_HASH_KEY_LK1_11_T; + +typedef struct dpp_se_cfg_hash_key_lk1_10_t +{ + ZXIC_UINT32 hash_key_lk1_10; +}DPP_SE_CFG_HASH_KEY_LK1_10_T; + +typedef struct dpp_se_cfg_hash_key_lk1_9_t +{ + ZXIC_UINT32 hash_key_lk1_9; +}DPP_SE_CFG_HASH_KEY_LK1_9_T; + +typedef struct dpp_se_cfg_hash_key_lk1_8_t +{ + ZXIC_UINT32 hash_key_lk1_8; +}DPP_SE_CFG_HASH_KEY_LK1_8_T; + +typedef struct dpp_se_cfg_hash_key_lk1_7_t +{ + ZXIC_UINT32 hash_key_lk1_7; +}DPP_SE_CFG_HASH_KEY_LK1_7_T; + +typedef struct dpp_se_cfg_hash_key_lk1_6_t +{ + ZXIC_UINT32 hash_key_lk1_6; +}DPP_SE_CFG_HASH_KEY_LK1_6_T; + +typedef struct dpp_se_cfg_hash_key_lk1_5_t +{ + ZXIC_UINT32 hash_key_lk1_5; +}DPP_SE_CFG_HASH_KEY_LK1_5_T; + +typedef struct dpp_se_cfg_hash_key_lk1_4_t +{ + ZXIC_UINT32 hash_key_lk1_4; +}DPP_SE_CFG_HASH_KEY_LK1_4_T; + +typedef struct dpp_se_cfg_hash_key_lk1_3_t +{ + ZXIC_UINT32 hash_key_lk1_3; +}DPP_SE_CFG_HASH_KEY_LK1_3_T; + +typedef struct dpp_se_cfg_hash_key_lk1_2_t +{ + ZXIC_UINT32 hash_key_lk1_2; +}DPP_SE_CFG_HASH_KEY_LK1_2_T; + +typedef struct dpp_se_cfg_hash_key_lk1_1_t +{ + ZXIC_UINT32 hash_key_lk1_1; +}DPP_SE_CFG_HASH_KEY_LK1_1_T; + +typedef struct dpp_se_cfg_hash_key_lk1_0_t +{ + ZXIC_UINT32 hash_key_lk1_0; +}DPP_SE_CFG_HASH_KEY_LK1_0_T; + +typedef struct dpp_se_cfg_hash_key_lk2_18_t +{ + ZXIC_UINT32 hash_key_lk2_18; +}DPP_SE_CFG_HASH_KEY_LK2_18_T; + +typedef struct dpp_se_cfg_hash_key_lk2_17_t +{ + ZXIC_UINT32 hash_key_lk2_17; +}DPP_SE_CFG_HASH_KEY_LK2_17_T; + +typedef struct dpp_se_cfg_hash_key_lk2_16_t +{ + ZXIC_UINT32 hash_key_lk2_16; +}DPP_SE_CFG_HASH_KEY_LK2_16_T; + +typedef struct dpp_se_cfg_hash_key_lk2_15_t +{ + ZXIC_UINT32 hash_key_lk2_15; +}DPP_SE_CFG_HASH_KEY_LK2_15_T; + +typedef struct dpp_se_cfg_hash_key_lk2_14_t +{ + ZXIC_UINT32 hash_key_lk2_14; +}DPP_SE_CFG_HASH_KEY_LK2_14_T; + +typedef struct dpp_se_cfg_hash_key_lk2_13_t +{ + ZXIC_UINT32 hash_key_lk2_13; +}DPP_SE_CFG_HASH_KEY_LK2_13_T; + +typedef struct dpp_se_cfg_hash_key_lk2_12_t +{ + ZXIC_UINT32 hash_key_lk2_12; +}DPP_SE_CFG_HASH_KEY_LK2_12_T; + +typedef struct dpp_se_cfg_hash_key_lk2_11_t +{ + ZXIC_UINT32 hash_key_lk2_11; +}DPP_SE_CFG_HASH_KEY_LK2_11_T; + +typedef struct dpp_se_cfg_hash_key_lk2_10_t +{ + ZXIC_UINT32 hash_key_lk2_10; +}DPP_SE_CFG_HASH_KEY_LK2_10_T; + +typedef struct dpp_se_cfg_hash_key_lk2_9_t +{ + ZXIC_UINT32 hash_key_lk2_9; +}DPP_SE_CFG_HASH_KEY_LK2_9_T; + +typedef struct dpp_se_cfg_hash_key_lk2_8_t +{ + ZXIC_UINT32 hash_key_lk2_8; +}DPP_SE_CFG_HASH_KEY_LK2_8_T; + +typedef struct dpp_se_cfg_hash_key_lk2_7_t +{ + ZXIC_UINT32 hash_key_lk2_7; +}DPP_SE_CFG_HASH_KEY_LK2_7_T; + +typedef struct dpp_se_cfg_hash_key_lk2_6_t +{ + ZXIC_UINT32 hash_key_lk2_6; +}DPP_SE_CFG_HASH_KEY_LK2_6_T; + +typedef struct dpp_se_cfg_hash_key_lk2_5_t +{ + ZXIC_UINT32 hash_key_lk2_5; +}DPP_SE_CFG_HASH_KEY_LK2_5_T; + +typedef struct dpp_se_cfg_hash_key_lk2_4_t +{ + ZXIC_UINT32 hash_key_lk2_4; +}DPP_SE_CFG_HASH_KEY_LK2_4_T; + +typedef struct dpp_se_cfg_hash_key_lk2_3_t +{ + ZXIC_UINT32 hash_key_lk2_3; +}DPP_SE_CFG_HASH_KEY_LK2_3_T; + +typedef struct dpp_se_cfg_hash_key_lk2_2_t +{ + ZXIC_UINT32 hash_key_lk2_2; +}DPP_SE_CFG_HASH_KEY_LK2_2_T; + +typedef struct dpp_se_cfg_hash_key_lk2_1_t +{ + ZXIC_UINT32 hash_key_lk2_1; +}DPP_SE_CFG_HASH_KEY_LK2_1_T; + +typedef struct dpp_se_cfg_hash_key_lk2_0_t +{ + ZXIC_UINT32 hash_key_lk2_0; +}DPP_SE_CFG_HASH_KEY_LK2_0_T; + +typedef struct dpp_se_cfg_hash_key_lk3_18_t +{ + ZXIC_UINT32 hash_key_lk3_18; +}DPP_SE_CFG_HASH_KEY_LK3_18_T; + +typedef struct dpp_se_cfg_hash_key_lk3_17_t +{ + ZXIC_UINT32 hash_key_lk3_17; +}DPP_SE_CFG_HASH_KEY_LK3_17_T; + +typedef struct dpp_se_cfg_hash_key_lk3_16_t +{ + ZXIC_UINT32 hash_key_lk3_16; +}DPP_SE_CFG_HASH_KEY_LK3_16_T; + +typedef struct dpp_se_cfg_hash_key_lk3_15_t +{ + ZXIC_UINT32 hash_key_lk3_15; +}DPP_SE_CFG_HASH_KEY_LK3_15_T; + +typedef struct dpp_se_cfg_hash_key_lk3_14_t +{ + ZXIC_UINT32 hash_key_lk3_14; +}DPP_SE_CFG_HASH_KEY_LK3_14_T; + +typedef struct dpp_se_cfg_hash_key_lk3_13_t +{ + ZXIC_UINT32 hash_key_lk3_13; +}DPP_SE_CFG_HASH_KEY_LK3_13_T; + +typedef struct dpp_se_cfg_hash_key_lk3_12_t +{ + ZXIC_UINT32 hash_key_lk3_12; +}DPP_SE_CFG_HASH_KEY_LK3_12_T; + +typedef struct dpp_se_cfg_hash_key_lk3_11_t +{ + ZXIC_UINT32 hash_key_lk3_11; +}DPP_SE_CFG_HASH_KEY_LK3_11_T; + +typedef struct dpp_se_cfg_hash_key_lk3_10_t +{ + ZXIC_UINT32 hash_key_lk3_10; +}DPP_SE_CFG_HASH_KEY_LK3_10_T; + +typedef struct dpp_se_cfg_hash_key_lk3_9_t +{ + ZXIC_UINT32 hash_key_lk3_9; +}DPP_SE_CFG_HASH_KEY_LK3_9_T; + +typedef struct dpp_se_cfg_hash_key_lk3_8_t +{ + ZXIC_UINT32 hash_key_lk3_8; +}DPP_SE_CFG_HASH_KEY_LK3_8_T; + +typedef struct dpp_se_cfg_hash_key_lk3_7_t +{ + ZXIC_UINT32 hash_key_lk3_7; +}DPP_SE_CFG_HASH_KEY_LK3_7_T; + +typedef struct dpp_se_cfg_hash_key_lk3_6_t +{ + ZXIC_UINT32 hash_key_lk3_6; +}DPP_SE_CFG_HASH_KEY_LK3_6_T; + +typedef struct dpp_se_cfg_hash_key_lk3_5_t +{ + ZXIC_UINT32 hash_key_lk3_5; +}DPP_SE_CFG_HASH_KEY_LK3_5_T; + +typedef struct dpp_se_cfg_hash_key_lk3_4_t +{ + ZXIC_UINT32 hash_key_lk3_4; +}DPP_SE_CFG_HASH_KEY_LK3_4_T; + +typedef struct dpp_se_cfg_hash_key_lk3_3_t +{ + ZXIC_UINT32 hash_key_lk3_3; +}DPP_SE_CFG_HASH_KEY_LK3_3_T; + +typedef struct dpp_se_cfg_hash_key_lk3_2_t +{ + ZXIC_UINT32 hash_key_lk3_2; +}DPP_SE_CFG_HASH_KEY_LK3_2_T; + +typedef struct dpp_se_cfg_hash_key_lk3_1_t +{ + ZXIC_UINT32 hash_key_lk3_1; +}DPP_SE_CFG_HASH_KEY_LK3_1_T; + +typedef struct dpp_se_cfg_hash_key_lk3_0_t +{ + ZXIC_UINT32 hash_key_lk3_0; +}DPP_SE_CFG_HASH_KEY_LK3_0_T; + +typedef struct dpp_se_cfg_lpm_key_lk0_6_t +{ + ZXIC_UINT32 lpm_key_lk0_6; +}DPP_SE_CFG_LPM_KEY_LK0_6_T; + +typedef struct dpp_se_cfg_lpm_key_lk0_5_t +{ + ZXIC_UINT32 lpm_key_lk0_5; +}DPP_SE_CFG_LPM_KEY_LK0_5_T; + +typedef struct dpp_se_cfg_lpm_key_lk0_4_t +{ + ZXIC_UINT32 lpm_key_lk0_4; +}DPP_SE_CFG_LPM_KEY_LK0_4_T; + +typedef struct dpp_se_cfg_lpm_key_lk0_3_t +{ + ZXIC_UINT32 lpm_key_lk0_3; +}DPP_SE_CFG_LPM_KEY_LK0_3_T; + +typedef struct dpp_se_cfg_lpm_key_lk0_2_t +{ + ZXIC_UINT32 lpm_key_lk0_2; +}DPP_SE_CFG_LPM_KEY_LK0_2_T; + +typedef struct dpp_se_cfg_lpm_key_lk0_1_t +{ + ZXIC_UINT32 lpm_key_lk0_1; +}DPP_SE_CFG_LPM_KEY_LK0_1_T; + +typedef struct dpp_se_cfg_lpm_key_lk0_0_t +{ + ZXIC_UINT32 lpm_key_lk0_0; +}DPP_SE_CFG_LPM_KEY_LK0_0_T; + +typedef struct dpp_se_cfg_lpm_key_lk1_6_t +{ + ZXIC_UINT32 lpm_key_lk1_6; +}DPP_SE_CFG_LPM_KEY_LK1_6_T; + +typedef struct dpp_se_cfg_lpm_key_lk1_5_t +{ + ZXIC_UINT32 lpm_key_lk1_5; +}DPP_SE_CFG_LPM_KEY_LK1_5_T; + +typedef struct dpp_se_cfg_lpm_key_lk1_4_t +{ + ZXIC_UINT32 lpm_key_lk1_4; +}DPP_SE_CFG_LPM_KEY_LK1_4_T; + +typedef struct dpp_se_cfg_lpm_key_lk1_3_t +{ + ZXIC_UINT32 lpm_key_lk1_3; +}DPP_SE_CFG_LPM_KEY_LK1_3_T; + +typedef struct dpp_se_cfg_lpm_key_lk1_2_t +{ + ZXIC_UINT32 lpm_key_lk1_2; +}DPP_SE_CFG_LPM_KEY_LK1_2_T; + +typedef struct dpp_se_cfg_lpm_key_lk1_1_t +{ + ZXIC_UINT32 lpm_key_lk1_1; +}DPP_SE_CFG_LPM_KEY_LK1_1_T; + +typedef struct dpp_se_cfg_lpm_key_lk1_0_t +{ + ZXIC_UINT32 lpm_key_lk1_0; +}DPP_SE_CFG_LPM_KEY_LK1_0_T; + +typedef struct dpp_se_cfg_lpm_key_lk2_6_t +{ + ZXIC_UINT32 lpm_key_lk2_6; +}DPP_SE_CFG_LPM_KEY_LK2_6_T; + +typedef struct dpp_se_cfg_lpm_key_lk2_5_t +{ + ZXIC_UINT32 lpm_key_lk2_5; +}DPP_SE_CFG_LPM_KEY_LK2_5_T; + +typedef struct dpp_se_cfg_lpm_key_lk2_4_t +{ + ZXIC_UINT32 lpm_key_lk2_4; +}DPP_SE_CFG_LPM_KEY_LK2_4_T; + +typedef struct dpp_se_cfg_lpm_key_lk2_3_t +{ + ZXIC_UINT32 lpm_key_lk2_3; +}DPP_SE_CFG_LPM_KEY_LK2_3_T; + +typedef struct dpp_se_cfg_lpm_key_lk2_2_t +{ + ZXIC_UINT32 lpm_key_lk2_2; +}DPP_SE_CFG_LPM_KEY_LK2_2_T; + +typedef struct dpp_se_cfg_lpm_key_lk2_1_t +{ + ZXIC_UINT32 lpm_key_lk2_1; +}DPP_SE_CFG_LPM_KEY_LK2_1_T; + +typedef struct dpp_se_cfg_lpm_key_lk2_0_t +{ + ZXIC_UINT32 lpm_key_lk2_0; +}DPP_SE_CFG_LPM_KEY_LK2_0_T; + +typedef struct dpp_se_cfg_lpm_key_lk3_6_t +{ + ZXIC_UINT32 lpm_key_lk3_6; +}DPP_SE_CFG_LPM_KEY_LK3_6_T; + +typedef struct dpp_se_cfg_lpm_key_lk3_5_t +{ + ZXIC_UINT32 lpm_key_lk3_5; +}DPP_SE_CFG_LPM_KEY_LK3_5_T; + +typedef struct dpp_se_cfg_lpm_key_lk3_4_t +{ + ZXIC_UINT32 lpm_key_lk3_4; +}DPP_SE_CFG_LPM_KEY_LK3_4_T; + +typedef struct dpp_se_cfg_lpm_key_lk3_3_t +{ + ZXIC_UINT32 lpm_key_lk3_3; +}DPP_SE_CFG_LPM_KEY_LK3_3_T; + +typedef struct dpp_se_cfg_lpm_key_lk3_2_t +{ + ZXIC_UINT32 lpm_key_lk3_2; +}DPP_SE_CFG_LPM_KEY_LK3_2_T; + +typedef struct dpp_se_cfg_lpm_key_lk3_1_t +{ + ZXIC_UINT32 lpm_key_lk3_1; +}DPP_SE_CFG_LPM_KEY_LK3_1_T; + +typedef struct dpp_se_cfg_lpm_key_lk3_0_t +{ + ZXIC_UINT32 lpm_key_lk3_0; +}DPP_SE_CFG_LPM_KEY_LK3_0_T; + +typedef struct dpp_se_cfg_etcam_key_lk0_22_t +{ + ZXIC_UINT32 etcam_key_lk0_22; +}DPP_SE_CFG_ETCAM_KEY_LK0_22_T; + +typedef struct dpp_se_cfg_etcam_key_lk0_21_t +{ + ZXIC_UINT32 etcam_key_lk0_21; +}DPP_SE_CFG_ETCAM_KEY_LK0_21_T; + +typedef struct dpp_se_cfg_etcam_key_lk0_20_t +{ + ZXIC_UINT32 etcam_key_lk0_20; +}DPP_SE_CFG_ETCAM_KEY_LK0_20_T; + +typedef struct dpp_se_cfg_etcam_key_lk0_19_t +{ + ZXIC_UINT32 etcam_key_lk0_19; +}DPP_SE_CFG_ETCAM_KEY_LK0_19_T; + +typedef struct dpp_se_cfg_etcam_key_lk0_18_t +{ + ZXIC_UINT32 etcam_key_lk0_18; +}DPP_SE_CFG_ETCAM_KEY_LK0_18_T; + +typedef struct dpp_se_cfg_etcam_key_lk0_17_t +{ + ZXIC_UINT32 etcam_key_lk0_17; +}DPP_SE_CFG_ETCAM_KEY_LK0_17_T; + +typedef struct dpp_se_cfg_etcam_key_lk0_16_t +{ + ZXIC_UINT32 etcam_key_lk0_16; +}DPP_SE_CFG_ETCAM_KEY_LK0_16_T; + +typedef struct dpp_se_cfg_etcam_key_lk0_15_t +{ + ZXIC_UINT32 etcam_key_lk0_15; +}DPP_SE_CFG_ETCAM_KEY_LK0_15_T; + +typedef struct dpp_se_cfg_etcam_key_lk0_14_t +{ + ZXIC_UINT32 etcam_key_lk0_14; +}DPP_SE_CFG_ETCAM_KEY_LK0_14_T; + +typedef struct dpp_se_cfg_etcam_key_lk0_13_t +{ + ZXIC_UINT32 etcam_key_lk0_13; +}DPP_SE_CFG_ETCAM_KEY_LK0_13_T; + +typedef struct dpp_se_cfg_etcam_key_lk0_12_t +{ + ZXIC_UINT32 etcam_key_lk0_12; +}DPP_SE_CFG_ETCAM_KEY_LK0_12_T; + +typedef struct dpp_se_cfg_etcam_key_lk0_11_t +{ + ZXIC_UINT32 etcam_key_lk0_11; +}DPP_SE_CFG_ETCAM_KEY_LK0_11_T; + +typedef struct dpp_se_cfg_etcam_key_lk0_10_t +{ + ZXIC_UINT32 etcam_key_lk0_10; +}DPP_SE_CFG_ETCAM_KEY_LK0_10_T; + +typedef struct dpp_se_cfg_etcam_key_lk0_9_t +{ + ZXIC_UINT32 etcam_key_lk0_9; +}DPP_SE_CFG_ETCAM_KEY_LK0_9_T; + +typedef struct dpp_se_cfg_etcam_key_lk0_8_t +{ + ZXIC_UINT32 etcam_key_lk0_8; +}DPP_SE_CFG_ETCAM_KEY_LK0_8_T; + +typedef struct dpp_se_cfg_etcam_key_lk0_7_t +{ + ZXIC_UINT32 etcam_key_lk0_7; +}DPP_SE_CFG_ETCAM_KEY_LK0_7_T; + +typedef struct dpp_se_cfg_etcam_key_lk0_6_t +{ + ZXIC_UINT32 etcam_key_lk0_6; +}DPP_SE_CFG_ETCAM_KEY_LK0_6_T; + +typedef struct dpp_se_cfg_etcam_key_lk0_5_t +{ + ZXIC_UINT32 etcam_key_lk0_5; +}DPP_SE_CFG_ETCAM_KEY_LK0_5_T; + +typedef struct dpp_se_cfg_etcam_key_lk0_4_t +{ + ZXIC_UINT32 etcam_key_lk0_4; +}DPP_SE_CFG_ETCAM_KEY_LK0_4_T; + +typedef struct dpp_se_cfg_etcam_key_lk0_3_t +{ + ZXIC_UINT32 etcam_key_lk0_3; +}DPP_SE_CFG_ETCAM_KEY_LK0_3_T; + +typedef struct dpp_se_cfg_etcam_key_lk0_2_t +{ + ZXIC_UINT32 etcam_key_lk0_2; +}DPP_SE_CFG_ETCAM_KEY_LK0_2_T; + +typedef struct dpp_se_cfg_etcam_key_lk0_1_t +{ + ZXIC_UINT32 etcam_key_lk0_1; +}DPP_SE_CFG_ETCAM_KEY_LK0_1_T; + +typedef struct dpp_se_cfg_etcam_key_lk0_0_t +{ + ZXIC_UINT32 etcam_key_lk0_0; +}DPP_SE_CFG_ETCAM_KEY_LK0_0_T; + +typedef struct dpp_se_cfg_etcam_key_lk1_22_t +{ + ZXIC_UINT32 etcam_key_lk1_22; +}DPP_SE_CFG_ETCAM_KEY_LK1_22_T; + +typedef struct dpp_se_cfg_etcam_key_lk1_21_t +{ + ZXIC_UINT32 etcam_key_lk1_21; +}DPP_SE_CFG_ETCAM_KEY_LK1_21_T; + +typedef struct dpp_se_cfg_etcam_key_lk1_20_t +{ + ZXIC_UINT32 etcam_key_lk1_20; +}DPP_SE_CFG_ETCAM_KEY_LK1_20_T; + +typedef struct dpp_se_cfg_etcam_key_lk1_19_t +{ + ZXIC_UINT32 etcam_key_lk1_19; +}DPP_SE_CFG_ETCAM_KEY_LK1_19_T; + +typedef struct dpp_se_cfg_etcam_key_lk1_18_t +{ + ZXIC_UINT32 etcam_key_lk1_18; +}DPP_SE_CFG_ETCAM_KEY_LK1_18_T; + +typedef struct dpp_se_cfg_etcam_key_lk1_17_t +{ + ZXIC_UINT32 etcam_key_lk1_17; +}DPP_SE_CFG_ETCAM_KEY_LK1_17_T; + +typedef struct dpp_se_cfg_etcam_key_lk1_16_t +{ + ZXIC_UINT32 etcam_key_lk1_16; +}DPP_SE_CFG_ETCAM_KEY_LK1_16_T; + +typedef struct dpp_se_cfg_etcam_key_lk1_15_t +{ + ZXIC_UINT32 etcam_key_lk1_15; +}DPP_SE_CFG_ETCAM_KEY_LK1_15_T; + +typedef struct dpp_se_cfg_etcam_key_lk1_14_t +{ + ZXIC_UINT32 etcam_key_lk1_14; +}DPP_SE_CFG_ETCAM_KEY_LK1_14_T; + +typedef struct dpp_se_cfg_etcam_key_lk1_13_t +{ + ZXIC_UINT32 etcam_key_lk1_13; +}DPP_SE_CFG_ETCAM_KEY_LK1_13_T; + +typedef struct dpp_se_cfg_etcam_key_lk1_12_t +{ + ZXIC_UINT32 etcam_key_lk1_12; +}DPP_SE_CFG_ETCAM_KEY_LK1_12_T; + +typedef struct dpp_se_cfg_etcam_key_lk1_11_t +{ + ZXIC_UINT32 etcam_key_lk1_11; +}DPP_SE_CFG_ETCAM_KEY_LK1_11_T; + +typedef struct dpp_se_cfg_etcam_key_lk1_10_t +{ + ZXIC_UINT32 etcam_key_lk1_10; +}DPP_SE_CFG_ETCAM_KEY_LK1_10_T; + +typedef struct dpp_se_cfg_etcam_key_lk1_9_t +{ + ZXIC_UINT32 etcam_key_lk1_9; +}DPP_SE_CFG_ETCAM_KEY_LK1_9_T; + +typedef struct dpp_se_cfg_etcam_key_lk1_8_t +{ + ZXIC_UINT32 etcam_key_lk1_8; +}DPP_SE_CFG_ETCAM_KEY_LK1_8_T; + +typedef struct dpp_se_cfg_etcam_key_lk1_7_t +{ + ZXIC_UINT32 etcam_key_lk1_7; +}DPP_SE_CFG_ETCAM_KEY_LK1_7_T; + +typedef struct dpp_se_cfg_etcam_key_lk1_6_t +{ + ZXIC_UINT32 etcam_key_lk1_6; +}DPP_SE_CFG_ETCAM_KEY_LK1_6_T; + +typedef struct dpp_se_cfg_etcam_key_lk1_5_t +{ + ZXIC_UINT32 etcam_key_lk1_5; +}DPP_SE_CFG_ETCAM_KEY_LK1_5_T; + +typedef struct dpp_se_cfg_etcam_key_lk1_4_t +{ + ZXIC_UINT32 etcam_key_lk1_4; +}DPP_SE_CFG_ETCAM_KEY_LK1_4_T; + +typedef struct dpp_se_cfg_etcam_key_lk1_3_t +{ + ZXIC_UINT32 etcam_key_lk1_3; +}DPP_SE_CFG_ETCAM_KEY_LK1_3_T; + +typedef struct dpp_se_cfg_etcam_key_lk1_2_t +{ + ZXIC_UINT32 etcam_key_lk1_2; +}DPP_SE_CFG_ETCAM_KEY_LK1_2_T; + +typedef struct dpp_se_cfg_etcam_key_lk1_1_t +{ + ZXIC_UINT32 etcam_key_lk1_1; +}DPP_SE_CFG_ETCAM_KEY_LK1_1_T; + +typedef struct dpp_se_cfg_etcam_key_lk1_0_t +{ + ZXIC_UINT32 etcam_key_lk1_0; +}DPP_SE_CFG_ETCAM_KEY_LK1_0_T; + +typedef struct dpp_se_cfg_etcam_key_lk2_22_t +{ + ZXIC_UINT32 etcam_key_lk2_22; +}DPP_SE_CFG_ETCAM_KEY_LK2_22_T; + +typedef struct dpp_se_cfg_etcam_key_lk2_21_t +{ + ZXIC_UINT32 etcam_key_lk2_21; +}DPP_SE_CFG_ETCAM_KEY_LK2_21_T; + +typedef struct dpp_se_cfg_etcam_key_lk2_20_t +{ + ZXIC_UINT32 etcam_key_lk2_20; +}DPP_SE_CFG_ETCAM_KEY_LK2_20_T; + +typedef struct dpp_se_cfg_etcam_key_lk2_19_t +{ + ZXIC_UINT32 etcam_key_lk2_19; +}DPP_SE_CFG_ETCAM_KEY_LK2_19_T; + +typedef struct dpp_se_cfg_etcam_key_lk2_18_t +{ + ZXIC_UINT32 etcam_key_lk2_18; +}DPP_SE_CFG_ETCAM_KEY_LK2_18_T; + +typedef struct dpp_se_cfg_etcam_key_lk2_17_t +{ + ZXIC_UINT32 etcam_key_lk2_17; +}DPP_SE_CFG_ETCAM_KEY_LK2_17_T; + +typedef struct dpp_se_cfg_etcam_key_lk2_16_t +{ + ZXIC_UINT32 etcam_key_lk2_16; +}DPP_SE_CFG_ETCAM_KEY_LK2_16_T; + +typedef struct dpp_se_cfg_etcam_key_lk2_15_t +{ + ZXIC_UINT32 etcam_key_lk2_15; +}DPP_SE_CFG_ETCAM_KEY_LK2_15_T; + +typedef struct dpp_se_cfg_etcam_key_lk2_14_t +{ + ZXIC_UINT32 etcam_key_lk2_14; +}DPP_SE_CFG_ETCAM_KEY_LK2_14_T; + +typedef struct dpp_se_cfg_etcam_key_lk2_13_t +{ + ZXIC_UINT32 etcam_key_lk2_13; +}DPP_SE_CFG_ETCAM_KEY_LK2_13_T; + +typedef struct dpp_se_cfg_etcam_key_lk2_12_t +{ + ZXIC_UINT32 etcam_key_lk2_12; +}DPP_SE_CFG_ETCAM_KEY_LK2_12_T; + +typedef struct dpp_se_cfg_etcam_key_lk2_11_t +{ + ZXIC_UINT32 etcam_key_lk2_11; +}DPP_SE_CFG_ETCAM_KEY_LK2_11_T; + +typedef struct dpp_se_cfg_etcam_key_lk2_10_t +{ + ZXIC_UINT32 etcam_key_lk2_10; +}DPP_SE_CFG_ETCAM_KEY_LK2_10_T; + +typedef struct dpp_se_cfg_etcam_key_lk2_9_t +{ + ZXIC_UINT32 etcam_key_lk2_9; +}DPP_SE_CFG_ETCAM_KEY_LK2_9_T; + +typedef struct dpp_se_cfg_etcam_key_lk2_8_t +{ + ZXIC_UINT32 etcam_key_lk2_8; +}DPP_SE_CFG_ETCAM_KEY_LK2_8_T; + +typedef struct dpp_se_cfg_etcam_key_lk2_7_t +{ + ZXIC_UINT32 etcam_key_lk2_7; +}DPP_SE_CFG_ETCAM_KEY_LK2_7_T; + +typedef struct dpp_se_cfg_etcam_key_lk2_6_t +{ + ZXIC_UINT32 etcam_key_lk2_6; +}DPP_SE_CFG_ETCAM_KEY_LK2_6_T; + +typedef struct dpp_se_cfg_etcam_key_lk2_5_t +{ + ZXIC_UINT32 etcam_key_lk2_5; +}DPP_SE_CFG_ETCAM_KEY_LK2_5_T; + +typedef struct dpp_se_cfg_etcam_key_lk2_4_t +{ + ZXIC_UINT32 etcam_key_lk2_4; +}DPP_SE_CFG_ETCAM_KEY_LK2_4_T; + +typedef struct dpp_se_cfg_etcam_key_lk2_3_t +{ + ZXIC_UINT32 etcam_key_lk2_3; +}DPP_SE_CFG_ETCAM_KEY_LK2_3_T; + +typedef struct dpp_se_cfg_etcam_key_lk2_2_t +{ + ZXIC_UINT32 etcam_key_lk2_2; +}DPP_SE_CFG_ETCAM_KEY_LK2_2_T; + +typedef struct dpp_se_cfg_etcam_key_lk2_1_t +{ + ZXIC_UINT32 etcam_key_lk2_1; +}DPP_SE_CFG_ETCAM_KEY_LK2_1_T; + +typedef struct dpp_se_cfg_etcam_key_lk2_0_t +{ + ZXIC_UINT32 etcam_key_lk2_0; +}DPP_SE_CFG_ETCAM_KEY_LK2_0_T; + +typedef struct dpp_se_cfg_etcam_key_lk3_22_t +{ + ZXIC_UINT32 etcam_key_lk3_22; +}DPP_SE_CFG_ETCAM_KEY_LK3_22_T; + +typedef struct dpp_se_cfg_etcam_key_lk3_21_t +{ + ZXIC_UINT32 etcam_key_lk3_21; +}DPP_SE_CFG_ETCAM_KEY_LK3_21_T; + +typedef struct dpp_se_cfg_etcam_key_lk3_20_t +{ + ZXIC_UINT32 etcam_key_lk3_20; +}DPP_SE_CFG_ETCAM_KEY_LK3_20_T; + +typedef struct dpp_se_cfg_etcam_key_lk3_19_t +{ + ZXIC_UINT32 etcam_key_lk3_19; +}DPP_SE_CFG_ETCAM_KEY_LK3_19_T; + +typedef struct dpp_se_cfg_etcam_key_lk3_18_t +{ + ZXIC_UINT32 etcam_key_lk3_18; +}DPP_SE_CFG_ETCAM_KEY_LK3_18_T; + +typedef struct dpp_se_cfg_etcam_key_lk3_17_t +{ + ZXIC_UINT32 etcam_key_lk3_17; +}DPP_SE_CFG_ETCAM_KEY_LK3_17_T; + +typedef struct dpp_se_cfg_etcam_key_lk3_16_t +{ + ZXIC_UINT32 etcam_key_lk3_16; +}DPP_SE_CFG_ETCAM_KEY_LK3_16_T; + +typedef struct dpp_se_cfg_etcam_key_lk3_15_t +{ + ZXIC_UINT32 etcam_key_lk3_15; +}DPP_SE_CFG_ETCAM_KEY_LK3_15_T; + +typedef struct dpp_se_cfg_etcam_key_lk3_14_t +{ + ZXIC_UINT32 etcam_key_lk3_14; +}DPP_SE_CFG_ETCAM_KEY_LK3_14_T; + +typedef struct dpp_se_cfg_etcam_key_lk3_13_t +{ + ZXIC_UINT32 etcam_key_lk3_13; +}DPP_SE_CFG_ETCAM_KEY_LK3_13_T; + +typedef struct dpp_se_cfg_etcam_key_lk3_12_t +{ + ZXIC_UINT32 etcam_key_lk3_12; +}DPP_SE_CFG_ETCAM_KEY_LK3_12_T; + +typedef struct dpp_se_cfg_etcam_key_lk3_11_t +{ + ZXIC_UINT32 etcam_key_lk3_11; +}DPP_SE_CFG_ETCAM_KEY_LK3_11_T; + +typedef struct dpp_se_cfg_etcam_key_lk3_10_t +{ + ZXIC_UINT32 etcam_key_lk3_10; +}DPP_SE_CFG_ETCAM_KEY_LK3_10_T; + +typedef struct dpp_se_cfg_etcam_key_lk3_9_t +{ + ZXIC_UINT32 etcam_key_lk3_9; +}DPP_SE_CFG_ETCAM_KEY_LK3_9_T; + +typedef struct dpp_se_cfg_etcam_key_lk3_8_t +{ + ZXIC_UINT32 etcam_key_lk3_8; +}DPP_SE_CFG_ETCAM_KEY_LK3_8_T; + +typedef struct dpp_se_cfg_etcam_key_lk3_7_t +{ + ZXIC_UINT32 etcam_key_lk3_7; +}DPP_SE_CFG_ETCAM_KEY_LK3_7_T; + +typedef struct dpp_se_cfg_etcam_key_lk3_6_t +{ + ZXIC_UINT32 etcam_key_lk3_6; +}DPP_SE_CFG_ETCAM_KEY_LK3_6_T; + +typedef struct dpp_se_cfg_etcam_key_lk3_5_t +{ + ZXIC_UINT32 etcam_key_lk3_5; +}DPP_SE_CFG_ETCAM_KEY_LK3_5_T; + +typedef struct dpp_se_cfg_etcam_key_lk3_4_t +{ + ZXIC_UINT32 etcam_key_lk3_4; +}DPP_SE_CFG_ETCAM_KEY_LK3_4_T; + +typedef struct dpp_se_cfg_etcam_key_lk3_3_t +{ + ZXIC_UINT32 etcam_key_lk3_3; +}DPP_SE_CFG_ETCAM_KEY_LK3_3_T; + +typedef struct dpp_se_cfg_etcam_key_lk3_2_t +{ + ZXIC_UINT32 etcam_key_lk3_2; +}DPP_SE_CFG_ETCAM_KEY_LK3_2_T; + +typedef struct dpp_se_cfg_etcam_key_lk3_1_t +{ + ZXIC_UINT32 etcam_key_lk3_1; +}DPP_SE_CFG_ETCAM_KEY_LK3_1_T; + +typedef struct dpp_se_cfg_etcam_key_lk3_0_t +{ + ZXIC_UINT32 etcam_key_lk3_0; +}DPP_SE_CFG_ETCAM_KEY_LK3_0_T; + +typedef struct dpp_se_cfg_pbu_key_lk0_3_t +{ + ZXIC_UINT32 pbu_key_lk0_3; +}DPP_SE_CFG_PBU_KEY_LK0_3_T; + +typedef struct dpp_se_cfg_pbu_key_lk0_2_t +{ + ZXIC_UINT32 pbu_key_lk0_2; +}DPP_SE_CFG_PBU_KEY_LK0_2_T; + +typedef struct dpp_se_cfg_pbu_key_lk0_1_t +{ + ZXIC_UINT32 pbu_key_lk0_1; +}DPP_SE_CFG_PBU_KEY_LK0_1_T; + +typedef struct dpp_se_cfg_pbu_key_lk0_0_t +{ + ZXIC_UINT32 pbu_key_lk0_0; +}DPP_SE_CFG_PBU_KEY_LK0_0_T; + +typedef struct dpp_se_cfg_pbu_key_lk1_3_t +{ + ZXIC_UINT32 pbu_key_lk1_3; +}DPP_SE_CFG_PBU_KEY_LK1_3_T; + +typedef struct dpp_se_cfg_pbu_key_lk1_2_t +{ + ZXIC_UINT32 pbu_key_lk1_2; +}DPP_SE_CFG_PBU_KEY_LK1_2_T; + +typedef struct dpp_se_cfg_pbu_key_lk1_1_t +{ + ZXIC_UINT32 pbu_key_lk1_1; +}DPP_SE_CFG_PBU_KEY_LK1_1_T; + +typedef struct dpp_se_cfg_pbu_key_lk1_0_t +{ + ZXIC_UINT32 pbu_key_lk1_0; +}DPP_SE_CFG_PBU_KEY_LK1_0_T; + +typedef struct dpp_se_cfg_pbu_key_lk2_3_t +{ + ZXIC_UINT32 pbu_key_lk2_3; +}DPP_SE_CFG_PBU_KEY_LK2_3_T; + +typedef struct dpp_se_cfg_pbu_key_lk2_2_t +{ + ZXIC_UINT32 pbu_key_lk2_2; +}DPP_SE_CFG_PBU_KEY_LK2_2_T; + +typedef struct dpp_se_cfg_pbu_key_lk2_1_t +{ + ZXIC_UINT32 pbu_key_lk2_1; +}DPP_SE_CFG_PBU_KEY_LK2_1_T; + +typedef struct dpp_se_cfg_pbu_key_lk2_0_t +{ + ZXIC_UINT32 pbu_key_lk2_0; +}DPP_SE_CFG_PBU_KEY_LK2_0_T; + +typedef struct dpp_se_cfg_pbu_key_lk3_3_t +{ + ZXIC_UINT32 pbu_key_lk3_3; +}DPP_SE_CFG_PBU_KEY_LK3_3_T; + +typedef struct dpp_se_cfg_pbu_key_lk3_2_t +{ + ZXIC_UINT32 pbu_key_lk3_2; +}DPP_SE_CFG_PBU_KEY_LK3_2_T; + +typedef struct dpp_se_cfg_pbu_key_lk3_1_t +{ + ZXIC_UINT32 pbu_key_lk3_1; +}DPP_SE_CFG_PBU_KEY_LK3_1_T; + +typedef struct dpp_se_cfg_pbu_key_lk3_0_t +{ + ZXIC_UINT32 pbu_key_lk3_0; +}DPP_SE_CFG_PBU_KEY_LK3_0_T; + +typedef struct dpp_se_alg_schd_learn_fifo_pfull_ast_t +{ + ZXIC_UINT32 schd_learn_fifo_pfull_ast; +}DPP_SE_ALG_SCHD_LEARN_FIFO_PFULL_AST_T; + +typedef struct dpp_se_alg_schd_learn_fifo_pfull_neg_t +{ + ZXIC_UINT32 schd_learn_fifo_pfull_neg; +}DPP_SE_ALG_SCHD_LEARN_FIFO_PFULL_NEG_T; + +typedef struct dpp_se_alg_schd_hash0_fifo_pfull_ast_t +{ + ZXIC_UINT32 schd_hash0_fifo_pfull_ast; +}DPP_SE_ALG_SCHD_HASH0_FIFO_PFULL_AST_T; + +typedef struct dpp_se_alg_schd_hash0_fifo_pfull_neg_t +{ + ZXIC_UINT32 schd_hash0_fifo_pfull_neg; +}DPP_SE_ALG_SCHD_HASH0_FIFO_PFULL_NEG_T; + +typedef struct dpp_se_alg_schd_hash1_fifo_pfull_ast_t +{ + ZXIC_UINT32 schd_hash1_fifo_pfull_ast; +}DPP_SE_ALG_SCHD_HASH1_FIFO_PFULL_AST_T; + +typedef struct dpp_se_alg_schd_hash1_fifo_pfull_neg_t +{ + ZXIC_UINT32 schd_hash1_fifo_pfull_neg; +}DPP_SE_ALG_SCHD_HASH1_FIFO_PFULL_NEG_T; + +typedef struct dpp_se_alg_schd_hash2_fifo_pfull_ast_t +{ + ZXIC_UINT32 schd_hash2_fifo_pfull_ast; +}DPP_SE_ALG_SCHD_HASH2_FIFO_PFULL_AST_T; + +typedef struct dpp_se_alg_schd_hash2_fifo_pfull_neg_t +{ + ZXIC_UINT32 schd_hash2_fifo_pfull_neg; +}DPP_SE_ALG_SCHD_HASH2_FIFO_PFULL_NEG_T; + +typedef struct dpp_se_alg_schd_hash3_fifo_pfull_ast_t +{ + ZXIC_UINT32 schd_hash3_fifo_pfull_ast; +}DPP_SE_ALG_SCHD_HASH3_FIFO_PFULL_AST_T; + +typedef struct dpp_se_alg_schd_hash3_fifo_pfull_neg_t +{ + ZXIC_UINT32 schd_hash3_fifo_pfull_neg; +}DPP_SE_ALG_SCHD_HASH3_FIFO_PFULL_NEG_T; + +typedef struct dpp_se_alg_schd_lpm_fifo_pfull_ast_t +{ + ZXIC_UINT32 schd_lpm_fifo_pfull_ast; +}DPP_SE_ALG_SCHD_LPM_FIFO_PFULL_AST_T; + +typedef struct dpp_se_alg_schd_lpm_fifo_pfull_neg_t +{ + ZXIC_UINT32 schd_lpm_fifo_pfull_neg; +}DPP_SE_ALG_SCHD_LPM_FIFO_PFULL_NEG_T; + +typedef struct dpp_se_alg_hash0_key_fifo_pfull_ast_t +{ + ZXIC_UINT32 hash0_key_fifo_pfull_ast; +}DPP_SE_ALG_HASH0_KEY_FIFO_PFULL_AST_T; + +typedef struct dpp_se_alg_hash0_key_fifo_pfull_neg_t +{ + ZXIC_UINT32 hash0_key_fifo_pfull_ast; +}DPP_SE_ALG_HASH0_KEY_FIFO_PFULL_NEG_T; + +typedef struct dpp_se_alg_hash0_sreq_fifo_pfull_ast_t +{ + ZXIC_UINT32 hash0_sreq_fifo_pfull_ast; +}DPP_SE_ALG_HASH0_SREQ_FIFO_PFULL_AST_T; + +typedef struct dpp_se_alg_hash0_sreq_fifo_pfull_neg_t +{ + ZXIC_UINT32 hash0_sreq_fifo_pfull_neg; +}DPP_SE_ALG_HASH0_SREQ_FIFO_PFULL_NEG_T; + +typedef struct dpp_se_alg_hash0_int_rsp_fifo_pfull_ast_t +{ + ZXIC_UINT32 hash0_int_rsp_fifo_pfull_ast; +}DPP_SE_ALG_HASH0_INT_RSP_FIFO_PFULL_AST_T; + +typedef struct dpp_se_alg_hash0_int_rsp_fifo_pfull_neg_t +{ + ZXIC_UINT32 hash0_int_rsp_fifo_pfull_neg; +}DPP_SE_ALG_HASH0_INT_RSP_FIFO_PFULL_NEG_T; + +typedef struct dpp_se_alg_hash0_ext_rsp_fifo_pfull_ast_t +{ + ZXIC_UINT32 hash0_ext_rsp_fifo_pfull_ast; +}DPP_SE_ALG_HASH0_EXT_RSP_FIFO_PFULL_AST_T; + +typedef struct dpp_se_alg_hash0_ext_rsp_fifo_pfull_neg_t +{ + ZXIC_UINT32 hash0_ext_rsp_fifo_pfull_neg; +}DPP_SE_ALG_HASH0_EXT_RSP_FIFO_PFULL_NEG_T; + +typedef struct dpp_se_alg_hash1_key_fifo_pfull_ast_t +{ + ZXIC_UINT32 hash1_key_fifo_pfull_ast; +}DPP_SE_ALG_HASH1_KEY_FIFO_PFULL_AST_T; + +typedef struct dpp_se_alg_hash1_key_fifo_pfull_neg_t +{ + ZXIC_UINT32 hash1_key_fifo_pfull_ast; +}DPP_SE_ALG_HASH1_KEY_FIFO_PFULL_NEG_T; + +typedef struct dpp_se_alg_hash1_sreq_fifo_pfull_ast_t +{ + ZXIC_UINT32 hash1_sreq_fifo_pfull_ast; +}DPP_SE_ALG_HASH1_SREQ_FIFO_PFULL_AST_T; + +typedef struct dpp_se_alg_hash1_sreq_fifo_pfull_neg_t +{ + ZXIC_UINT32 hash1_sreq_fifo_pfull_neg; +}DPP_SE_ALG_HASH1_SREQ_FIFO_PFULL_NEG_T; + +typedef struct dpp_se_alg_hash1_int_rsp_fifo_pfull_ast_t +{ + ZXIC_UINT32 hash1_int_rsp_fifo_pfull_ast; +}DPP_SE_ALG_HASH1_INT_RSP_FIFO_PFULL_AST_T; + +typedef struct dpp_se_alg_hash1_int_rsp_fifo_pfull_neg_t +{ + ZXIC_UINT32 hash1_int_rsp_fifo_pfull_neg; +}DPP_SE_ALG_HASH1_INT_RSP_FIFO_PFULL_NEG_T; + +typedef struct dpp_se_alg_hash1_ext_rsp_fifo_pfull_ast_t +{ + ZXIC_UINT32 hash1_ext_rsp_fifo_pfull_ast; +}DPP_SE_ALG_HASH1_EXT_RSP_FIFO_PFULL_AST_T; + +typedef struct dpp_se_alg_hash1_ext_rsp_fifo_pfull_neg_t +{ + ZXIC_UINT32 hash1_ext_rsp_fifo_pfull_neg; +}DPP_SE_ALG_HASH1_EXT_RSP_FIFO_PFULL_NEG_T; + +typedef struct dpp_se_alg_hash2_key_fifo_pfull_ast_t +{ + ZXIC_UINT32 hash2_key_fifo_pfull_ast; +}DPP_SE_ALG_HASH2_KEY_FIFO_PFULL_AST_T; + +typedef struct dpp_se_alg_hash2_key_fifo_pfull_neg_t +{ + ZXIC_UINT32 hash2_key_fifo_pfull_ast; +}DPP_SE_ALG_HASH2_KEY_FIFO_PFULL_NEG_T; + +typedef struct dpp_se_alg_hash2_sreq_fifo_pfull_ast_t +{ + ZXIC_UINT32 hash2_sreq_fifo_pfull_ast; +}DPP_SE_ALG_HASH2_SREQ_FIFO_PFULL_AST_T; + +typedef struct dpp_se_alg_hash2_sreq_fifo_pfull_neg_t +{ + ZXIC_UINT32 hash2_sreq_fifo_pfull_neg; +}DPP_SE_ALG_HASH2_SREQ_FIFO_PFULL_NEG_T; + +typedef struct dpp_se_alg_hash2_int_rsp_fifo_pfull_ast_t +{ + ZXIC_UINT32 hash2_int_rsp_fifo_pfull_ast; +}DPP_SE_ALG_HASH2_INT_RSP_FIFO_PFULL_AST_T; + +typedef struct dpp_se_alg_hash2_int_rsp_fifo_pfull_neg_t +{ + ZXIC_UINT32 hash2_int_rsp_fifo_pfull_neg; +}DPP_SE_ALG_HASH2_INT_RSP_FIFO_PFULL_NEG_T; + +typedef struct dpp_se_alg_hash2_ext_rsp_fifo_pfull_ast_t +{ + ZXIC_UINT32 hash2_ext_rsp_fifo_pfull_ast; +}DPP_SE_ALG_HASH2_EXT_RSP_FIFO_PFULL_AST_T; + +typedef struct dpp_se_alg_hash2_ext_rsp_fifo_pfull_neg_t +{ + ZXIC_UINT32 hash2_ext_rsp_fifo_pfull_neg; +}DPP_SE_ALG_HASH2_EXT_RSP_FIFO_PFULL_NEG_T; + +typedef struct dpp_se_alg_hash3_key_fifo_pfull_ast_t +{ + ZXIC_UINT32 hash3_key_fifo_pfull_ast; +}DPP_SE_ALG_HASH3_KEY_FIFO_PFULL_AST_T; + +typedef struct dpp_se_alg_hash3_key_fifo_pfull_neg_t +{ + ZXIC_UINT32 hash3_key_fifo_pfull_ast; +}DPP_SE_ALG_HASH3_KEY_FIFO_PFULL_NEG_T; + +typedef struct dpp_se_alg_hash3_sreq_fifo_pfull_ast_t +{ + ZXIC_UINT32 hash3_sreq_fifo_pfull_ast; +}DPP_SE_ALG_HASH3_SREQ_FIFO_PFULL_AST_T; + +typedef struct dpp_se_alg_hash3_sreq_fifo_pfull_neg_t +{ + ZXIC_UINT32 hash3_sreq_fifo_pfull_neg; +}DPP_SE_ALG_HASH3_SREQ_FIFO_PFULL_NEG_T; + +typedef struct dpp_se_alg_hash3_int_rsp_fifo_pfull_ast_t +{ + ZXIC_UINT32 hash3_int_rsp_fifo_pfull_ast; +}DPP_SE_ALG_HASH3_INT_RSP_FIFO_PFULL_AST_T; + +typedef struct dpp_se_alg_hash3_int_rsp_fifo_pfull_neg_t +{ + ZXIC_UINT32 hash3_int_rsp_fifo_pfull_neg; +}DPP_SE_ALG_HASH3_INT_RSP_FIFO_PFULL_NEG_T; + +typedef struct dpp_se_alg_hash3_ext_rsp_fifo_pfull_ast_t +{ + ZXIC_UINT32 hash3_ext_rsp_fifo_pfull_ast; +}DPP_SE_ALG_HASH3_EXT_RSP_FIFO_PFULL_AST_T; + +typedef struct dpp_se_alg_hash3_ext_rsp_fifo_pfull_neg_t +{ + ZXIC_UINT32 hash3_ext_rsp_fifo_pfull_neg; +}DPP_SE_ALG_HASH3_EXT_RSP_FIFO_PFULL_NEG_T; + +typedef struct dpp_se_alg_lpm_as_info_t +{ + ZXIC_UINT32 lpm_as_type; + ZXIC_UINT32 lpm_as_en; +}DPP_SE_ALG_LPM_AS_INFO_T; + +typedef struct dpp_se_alg_lpm_ext_rsp_fifo_u0_pfull_neg_t +{ + ZXIC_UINT32 lpm_ext_rsp_fifo_u0_pfull_neg; +}DPP_SE_ALG_LPM_EXT_RSP_FIFO_U0_PFULL_NEG_T; + +typedef struct dpp_se_alg_lpm_ext_rsp_fifo_u2_pfull_ast_t +{ + ZXIC_UINT32 lpm_ext_rsp_fifo_u2_pfull_ast; +}DPP_SE_ALG_LPM_EXT_RSP_FIFO_U2_PFULL_AST_T; + +typedef struct dpp_se_alg_lpm_ext_rsp_fifo_u2_pfull_neg_t +{ + ZXIC_UINT32 lpm_ext_rsp_fifo_u2_pfull_neg; +}DPP_SE_ALG_LPM_EXT_RSP_FIFO_U2_PFULL_NEG_T; + +typedef struct dpp_se_alg_lpm_ext_rsp_fifo_u3_pfull_ast_t +{ + ZXIC_UINT32 lpm_ext_rsp_fifo_u3_pfull_ast; +}DPP_SE_ALG_LPM_EXT_RSP_FIFO_U3_PFULL_AST_T; + +typedef struct dpp_se_alg_lpm_ext_rsp_fifo_u3_pfull_neg_t +{ + ZXIC_UINT32 lpm_ext_rsp_fifo_u3_pfull_neg; +}DPP_SE_ALG_LPM_EXT_RSP_FIFO_U3_PFULL_NEG_T; + +typedef struct dpp_se_alg_lpm_ext_rsp_fifo_u4_pfull_ast_t +{ + ZXIC_UINT32 lpm_ext_rsp_fifo_u4_pfull_ast; +}DPP_SE_ALG_LPM_EXT_RSP_FIFO_U4_PFULL_AST_T; + +typedef struct dpp_se_alg_lpm_ext_rsp_fifo_u4_pfull_neg_t +{ + ZXIC_UINT32 lpm_ext_rsp_fifo_u4_pfull_neg; +}DPP_SE_ALG_LPM_EXT_RSP_FIFO_U4_PFULL_NEG_T; + +typedef struct dpp_se_alg_lpm_as_rsp_fifo_u0_pfull_ast_t +{ + ZXIC_UINT32 lpm_as_rsp_fifo_u0_pfull_ast; +}DPP_SE_ALG_LPM_AS_RSP_FIFO_U0_PFULL_AST_T; + +typedef struct dpp_se_alg_lpm_as_rsp_fifo_u0_pfull_neg_t +{ + ZXIC_UINT32 lpm_as_rsp_fifo_u0_pfull_neg; +}DPP_SE_ALG_LPM_AS_RSP_FIFO_U0_PFULL_NEG_T; + +typedef struct dpp_se_alg_lpm_as_rsp_fifo_u1_pfull_ast_t +{ + ZXIC_UINT32 lpm_as_rsp_fifo_u1_pfull_ast; +}DPP_SE_ALG_LPM_AS_RSP_FIFO_U1_PFULL_AST_T; + +typedef struct dpp_se_alg_lpm_as_rsp_fifo_u1_pfull_neg_t +{ + ZXIC_UINT32 lpm_as_rsp_fifo_u1_pfull_neg; +}DPP_SE_ALG_LPM_AS_RSP_FIFO_U1_PFULL_NEG_T; + +typedef struct dpp_se_alg_lpm_v4_ddr3_base_addr_t +{ + ZXIC_UINT32 lpm_v4_ddr3_base_addr; +}DPP_SE_ALG_LPM_V4_DDR3_BASE_ADDR_T; + +typedef struct dpp_se_alg_lpm_v6_ddr3_base_addr_t +{ + ZXIC_UINT32 lpm_v6_ddr3_base_addr; +}DPP_SE_ALG_LPM_V6_DDR3_BASE_ADDR_T; + +typedef struct dpp_se_alg_debug_cnt_mode_t +{ + ZXIC_UINT32 cnt_rd_mode; + ZXIC_UINT32 cnt_overflow_mode; +}DPP_SE_ALG_DEBUG_CNT_MODE_T; + +typedef struct dpp_se_alg_hash_p0_key_vld_cnt_t +{ + ZXIC_UINT32 hash_p0_key_vld_cnt; +}DPP_SE_ALG_HASH_P0_KEY_VLD_CNT_T; + +typedef struct dpp_se_alg_hash_p1_key_vld_cnt_t +{ + ZXIC_UINT32 hash_p1_key_vld_cnt; +}DPP_SE_ALG_HASH_P1_KEY_VLD_CNT_T; + +typedef struct dpp_se_alg_hash_p2_key_vld_cnt_t +{ + ZXIC_UINT32 hash_p2_key_vld_cnt; +}DPP_SE_ALG_HASH_P2_KEY_VLD_CNT_T; + +typedef struct dpp_se_alg_hash_p3_key_vld_cnt_t +{ + ZXIC_UINT32 hash_p3_key_vld_cnt; +}DPP_SE_ALG_HASH_P3_KEY_VLD_CNT_T; + +typedef struct dpp_se_alg_lpm_p0_key_vld_cnt_t +{ + ZXIC_UINT32 lpm_p0_key_vld_cnt; +}DPP_SE_ALG_LPM_P0_KEY_VLD_CNT_T; + +typedef struct dpp_se_alg_hash_p0_rsp_vld_cnt_t +{ + ZXIC_UINT32 hash_p0_rsp_vld_cnt; +}DPP_SE_ALG_HASH_P0_RSP_VLD_CNT_T; + +typedef struct dpp_se_alg_hash_p1_rsp_vld_cnt_t +{ + ZXIC_UINT32 hash_p1_rsp_vld_cnt; +}DPP_SE_ALG_HASH_P1_RSP_VLD_CNT_T; + +typedef struct dpp_se_alg_hash_p2_rsp_vld_cnt_t +{ + ZXIC_UINT32 hash_p2_rsp_vld_cnt; +}DPP_SE_ALG_HASH_P2_RSP_VLD_CNT_T; + +typedef struct dpp_se_alg_hash_p3_rsp_vld_cnt_t +{ + ZXIC_UINT32 hash_p3_rsp_vld_cnt; +}DPP_SE_ALG_HASH_P3_RSP_VLD_CNT_T; + +typedef struct dpp_se_alg_lpm_p0_rsp_vld_cnt_t +{ + ZXIC_UINT32 lpm_p0_rsp_vld_cnt; +}DPP_SE_ALG_LPM_P0_RSP_VLD_CNT_T; + +typedef struct dpp_se_alg_hash_p0_smf_cnt_t +{ + ZXIC_UINT32 hash_p0_smf_cnt; +}DPP_SE_ALG_HASH_P0_SMF_CNT_T; + +typedef struct dpp_se_alg_hash_p1_smf_cnt_t +{ + ZXIC_UINT32 hash_p1_smf_cnt; +}DPP_SE_ALG_HASH_P1_SMF_CNT_T; + +typedef struct dpp_se_alg_hash_p2_smf_cnt_t +{ + ZXIC_UINT32 hash_p2_smf_cnt; +}DPP_SE_ALG_HASH_P2_SMF_CNT_T; + +typedef struct dpp_se_alg_hash_p3_smf_cnt_t +{ + ZXIC_UINT32 hash_p3_smf_cnt; +}DPP_SE_ALG_HASH_P3_SMF_CNT_T; + +typedef struct dpp_se_alg_lpm_p0_smf_cnt_t +{ + ZXIC_UINT32 lpm_p0_smf_cnt; +}DPP_SE_ALG_LPM_P0_SMF_CNT_T; + +typedef struct dpp_se_alg_hash_p0_spacevld_cnt_t +{ + ZXIC_UINT32 hash_p0_spacevld_cnt; +}DPP_SE_ALG_HASH_P0_SPACEVLD_CNT_T; + +typedef struct dpp_se_alg_hash_p1_spacevld_cnt_t +{ + ZXIC_UINT32 hash_p1_spacevld_cnt; +}DPP_SE_ALG_HASH_P1_SPACEVLD_CNT_T; + +typedef struct dpp_se_alg_hash_p2_spacevld_cnt_t +{ + ZXIC_UINT32 hash_p2_spacevld_cnt; +}DPP_SE_ALG_HASH_P2_SPACEVLD_CNT_T; + +typedef struct dpp_se_alg_hash_p3_spacevld_cnt_t +{ + ZXIC_UINT32 hash_p3_spacevld_cnt; +}DPP_SE_ALG_HASH_P3_SPACEVLD_CNT_T; + +typedef struct dpp_se_alg_smmu1_p0_req_vld_cnt_t +{ + ZXIC_UINT32 smmu1_p0_req_vld_cnt; +}DPP_SE_ALG_SMMU1_P0_REQ_VLD_CNT_T; + +typedef struct dpp_se_alg_smmu1_p1_req_vld_cnt_t +{ + ZXIC_UINT32 smmu1_p1_req_vld_cnt; +}DPP_SE_ALG_SMMU1_P1_REQ_VLD_CNT_T; + +typedef struct dpp_se_alg_smmu1_p2_req_vld_cnt_t +{ + ZXIC_UINT32 smmu1_p2_req_vld_cnt; +}DPP_SE_ALG_SMMU1_P2_REQ_VLD_CNT_T; + +typedef struct dpp_se_alg_smmu1_p3_req_vld_cnt_t +{ + ZXIC_UINT32 smmu1_p3_req_vld_cnt; +}DPP_SE_ALG_SMMU1_P3_REQ_VLD_CNT_T; + +typedef struct dpp_se_alg_smmu1_p4_req_vld_cnt_t +{ + ZXIC_UINT32 smmu1_p4_req_vld_cnt; +}DPP_SE_ALG_SMMU1_P4_REQ_VLD_CNT_T; + +typedef struct dpp_se_alg_smmu1_p5_req_vld_cnt_t +{ + ZXIC_UINT32 smmu1_p5_req_vld_cnt; +}DPP_SE_ALG_SMMU1_P5_REQ_VLD_CNT_T; + +typedef struct dpp_se_alg_smmu1_p0_rsp_vld_cnt_t +{ + ZXIC_UINT32 smmu1_p0_rsp_vld_cnt; +}DPP_SE_ALG_SMMU1_P0_RSP_VLD_CNT_T; + +typedef struct dpp_se_alg_smmu1_p1_rsp_vld_cnt_t +{ + ZXIC_UINT32 smmu1_p1_rsp_vld_cnt; +}DPP_SE_ALG_SMMU1_P1_RSP_VLD_CNT_T; + +typedef struct dpp_se_alg_smmu1_p2_rsp_vld_cnt_t +{ + ZXIC_UINT32 smmu1_p2_rsp_vld_cnt; +}DPP_SE_ALG_SMMU1_P2_RSP_VLD_CNT_T; + +typedef struct dpp_se_alg_smmu1_p3_rsp_vld_cnt_t +{ + ZXIC_UINT32 smmu1_p3_rsp_vld_cnt; +}DPP_SE_ALG_SMMU1_P3_RSP_VLD_CNT_T; + +typedef struct dpp_se_alg_smmu1_p4_rsp_vld_cnt_t +{ + ZXIC_UINT32 smmu1_p4_rsp_vld_cnt; +}DPP_SE_ALG_SMMU1_P4_RSP_VLD_CNT_T; + +typedef struct dpp_se_alg_smmu1_p5_rsp_vld_cnt_t +{ + ZXIC_UINT32 smmu1_p5_rsp_vld_cnt; +}DPP_SE_ALG_SMMU1_P5_RSP_VLD_CNT_T; + +typedef struct dpp_se_alg_schd_learn_fifo_int_cnt_t +{ + ZXIC_UINT32 schd_learn_fifo_int_cnt; +}DPP_SE_ALG_SCHD_LEARN_FIFO_INT_CNT_T; + +typedef struct dpp_se_alg_schd_hash0_fifo_int_cnt_t +{ + ZXIC_UINT32 schd_hash0_fifo_int_cnt; +}DPP_SE_ALG_SCHD_HASH0_FIFO_INT_CNT_T; + +typedef struct dpp_se_alg_schd_hash1_fifo_int_cnt_t +{ + ZXIC_UINT32 schd_hash1_fifo_int_cnt; +}DPP_SE_ALG_SCHD_HASH1_FIFO_INT_CNT_T; + +typedef struct dpp_se_alg_schd_hash2_fifo_int_cnt_t +{ + ZXIC_UINT32 schd_hash2_fifo_int_cnt; +}DPP_SE_ALG_SCHD_HASH2_FIFO_INT_CNT_T; + +typedef struct dpp_se_alg_schd_hash3_fifo_int_cnt_t +{ + ZXIC_UINT32 schd_hash3_fifo_int_cnt; +}DPP_SE_ALG_SCHD_HASH3_FIFO_INT_CNT_T; + +typedef struct dpp_se_alg_schd_lpm_fifo_int_cnt_t +{ + ZXIC_UINT32 schd_lpm_fifo_int_cnt; +}DPP_SE_ALG_SCHD_LPM_FIFO_INT_CNT_T; + +typedef struct dpp_se_alg_schd_learn_fifo_parity_err_cnt_t +{ + ZXIC_UINT32 schd_learn_fifo_parity_err_cnt; +}DPP_SE_ALG_SCHD_LEARN_FIFO_PARITY_ERR_CNT_T; + +typedef struct dpp_se_alg_schd_hash0_fifo_parity_err_cnt_t +{ + ZXIC_UINT32 schd_hash0_fifo_parity_err_cnt; +}DPP_SE_ALG_SCHD_HASH0_FIFO_PARITY_ERR_CNT_T; + +typedef struct dpp_se_alg_schd_hash1_fifo_parity_err_cnt_t +{ + ZXIC_UINT32 schd_hash1_fifo_parity_err_cnt; +}DPP_SE_ALG_SCHD_HASH1_FIFO_PARITY_ERR_CNT_T; + +typedef struct dpp_se_alg_schd_hash2_fifo_parity_err_cnt_t +{ + ZXIC_UINT32 schd_hash2_fifo_parity_err_cnt; +}DPP_SE_ALG_SCHD_HASH2_FIFO_PARITY_ERR_CNT_T; + +typedef struct dpp_se_alg_schd_hash3_fifo_parity_err_cnt_t +{ + ZXIC_UINT32 schd_hash3_fifo_parity_err_cnt; +}DPP_SE_ALG_SCHD_HASH3_FIFO_PARITY_ERR_CNT_T; + +typedef struct dpp_se_alg_schd_lpm_fifo_parity_err_cnt_t +{ + ZXIC_UINT32 schd_lpm_fifo_parity_err_cnt; +}DPP_SE_ALG_SCHD_LPM_FIFO_PARITY_ERR_CNT_T; + +typedef struct dpp_se_alg_rd_init_cft_cnt_t +{ + ZXIC_UINT32 rd_init_cft_cnt; +}DPP_SE_ALG_RD_INIT_CFT_CNT_T; + +typedef struct dpp_se_alg_zgp0_zblk0_ecc_err_cnt_t +{ + ZXIC_UINT32 zgp0_zblk0_ecc_err_cnt; +}DPP_SE_ALG_ZGP0_ZBLK0_ECC_ERR_CNT_T; + +typedef struct dpp_se_alg_zgp0_zblk1_ecc_err_cnt_t +{ + ZXIC_UINT32 zgp0_zblk1_ecc_err_cnt; +}DPP_SE_ALG_ZGP0_ZBLK1_ECC_ERR_CNT_T; + +typedef struct dpp_se_alg_zgp0_zblk2_ecc_err_cnt_t +{ + ZXIC_UINT32 zgp0_zblk2_ecc_err_cnt; +}DPP_SE_ALG_ZGP0_ZBLK2_ECC_ERR_CNT_T; + +typedef struct dpp_se_alg_zgp0_zblk3_ecc_err_cnt_t +{ + ZXIC_UINT32 zgp0_zblk3_ecc_err_cnt; +}DPP_SE_ALG_ZGP0_ZBLK3_ECC_ERR_CNT_T; + +typedef struct dpp_se_alg_zgp0_zblk4_ecc_err_cnt_t +{ + ZXIC_UINT32 zgp0_zblk4_ecc_err_cnt; +}DPP_SE_ALG_ZGP0_ZBLK4_ECC_ERR_CNT_T; + +typedef struct dpp_se_alg_zgp0_zblk5_ecc_err_cnt_t +{ + ZXIC_UINT32 zgp0_zblk5_ecc_err_cnt; +}DPP_SE_ALG_ZGP0_ZBLK5_ECC_ERR_CNT_T; + +typedef struct dpp_se_alg_zgp0_zblk6_ecc_err_cnt_t +{ + ZXIC_UINT32 zgp0_zblk6_ecc_err_cnt; +}DPP_SE_ALG_ZGP0_ZBLK6_ECC_ERR_CNT_T; + +typedef struct dpp_se_alg_zgp0_zblk7_ecc_err_cnt_t +{ + ZXIC_UINT32 zgp0_zblk7_ecc_err_cnt; +}DPP_SE_ALG_ZGP0_ZBLK7_ECC_ERR_CNT_T; + +typedef struct dpp_se_alg_zgp1_zblk0_ecc_err_cnt_t +{ + ZXIC_UINT32 zgp1_zblk0_ecc_err_cnt; +}DPP_SE_ALG_ZGP1_ZBLK0_ECC_ERR_CNT_T; + +typedef struct dpp_se_alg_zgp1_zblk1_ecc_err_cnt_t +{ + ZXIC_UINT32 zgp1_zblk1_ecc_err_cnt; +}DPP_SE_ALG_ZGP1_ZBLK1_ECC_ERR_CNT_T; + +typedef struct dpp_se_alg_zgp1_zblk2_ecc_err_cnt_t +{ + ZXIC_UINT32 zgp1_zblk2_ecc_err_cnt; +}DPP_SE_ALG_ZGP1_ZBLK2_ECC_ERR_CNT_T; + +typedef struct dpp_se_alg_zgp1_zblk3_ecc_err_cnt_t +{ + ZXIC_UINT32 zgp1_zblk3_ecc_err_cnt; +}DPP_SE_ALG_ZGP1_ZBLK3_ECC_ERR_CNT_T; + +typedef struct dpp_se_alg_zgp1_zblk4_ecc_err_cnt_t +{ + ZXIC_UINT32 zgp1_zblk4_ecc_err_cnt; +}DPP_SE_ALG_ZGP1_ZBLK4_ECC_ERR_CNT_T; + +typedef struct dpp_se_alg_zgp1_zblk5_ecc_err_cnt_t +{ + ZXIC_UINT32 zgp1_zblk5_ecc_err_cnt; +}DPP_SE_ALG_ZGP1_ZBLK5_ECC_ERR_CNT_T; + +typedef struct dpp_se_alg_zgp1_zblk6_ecc_err_cnt_t +{ + ZXIC_UINT32 zgp1_zblk6_ecc_err_cnt; +}DPP_SE_ALG_ZGP1_ZBLK6_ECC_ERR_CNT_T; + +typedef struct dpp_se_alg_zgp1_zblk7_ecc_err_cnt_t +{ + ZXIC_UINT32 zgp1_zblk7_ecc_err_cnt; +}DPP_SE_ALG_ZGP1_ZBLK7_ECC_ERR_CNT_T; + +typedef struct dpp_se_alg_zgp2_zblk0_ecc_err_cnt_t +{ + ZXIC_UINT32 zgp2_zblk0_ecc_err_cnt; +}DPP_SE_ALG_ZGP2_ZBLK0_ECC_ERR_CNT_T; + +typedef struct dpp_se_alg_zgp2_zblk1_ecc_err_cnt_t +{ + ZXIC_UINT32 zgp2_zblk1_ecc_err_cnt; +}DPP_SE_ALG_ZGP2_ZBLK1_ECC_ERR_CNT_T; + +typedef struct dpp_se_alg_zgp2_zblk2_ecc_err_cnt_t +{ + ZXIC_UINT32 zgp2_zblk2_ecc_err_cnt; +}DPP_SE_ALG_ZGP2_ZBLK2_ECC_ERR_CNT_T; + +typedef struct dpp_se_alg_zgp2_zblk3_ecc_err_cnt_t +{ + ZXIC_UINT32 zgp2_zblk3_ecc_err_cnt; +}DPP_SE_ALG_ZGP2_ZBLK3_ECC_ERR_CNT_T; + +typedef struct dpp_se_alg_zgp2_zblk4_ecc_err_cnt_t +{ + ZXIC_UINT32 zgp2_zblk4_ecc_err_cnt; +}DPP_SE_ALG_ZGP2_ZBLK4_ECC_ERR_CNT_T; + +typedef struct dpp_se_alg_zgp2_zblk5_ecc_err_cnt_t +{ + ZXIC_UINT32 zgp2_zblk5_ecc_err_cnt; +}DPP_SE_ALG_ZGP2_ZBLK5_ECC_ERR_CNT_T; + +typedef struct dpp_se_alg_zgp2_zblk6_ecc_err_cnt_t +{ + ZXIC_UINT32 zgp2_zblk6_ecc_err_cnt; +}DPP_SE_ALG_ZGP2_ZBLK6_ECC_ERR_CNT_T; + +typedef struct dpp_se_alg_zgp2_zblk7_ecc_err_cnt_t +{ + ZXIC_UINT32 zgp2_zblk7_ecc_err_cnt; +}DPP_SE_ALG_ZGP2_ZBLK7_ECC_ERR_CNT_T; + +typedef struct dpp_se_alg_zgp3_zblk0_ecc_err_cnt_t +{ + ZXIC_UINT32 zgp3_zblk0_ecc_err_cnt; +}DPP_SE_ALG_ZGP3_ZBLK0_ECC_ERR_CNT_T; + +typedef struct dpp_se_alg_zgp3_zblk1_ecc_err_cnt_t +{ + ZXIC_UINT32 zgp3_zblk1_ecc_err_cnt; +}DPP_SE_ALG_ZGP3_ZBLK1_ECC_ERR_CNT_T; + +typedef struct dpp_se_alg_zgp3_zblk2_ecc_err_cnt_t +{ + ZXIC_UINT32 zgp3_zblk2_ecc_err_cnt; +}DPP_SE_ALG_ZGP3_ZBLK2_ECC_ERR_CNT_T; + +typedef struct dpp_se_alg_zgp3_zblk3_ecc_err_cnt_t +{ + ZXIC_UINT32 zgp3_zblk3_ecc_err_cnt; +}DPP_SE_ALG_ZGP3_ZBLK3_ECC_ERR_CNT_T; + +typedef struct dpp_se_alg_zgp3_zblk4_ecc_err_cnt_t +{ + ZXIC_UINT32 zgp3_zblk4_ecc_err_cnt; +}DPP_SE_ALG_ZGP3_ZBLK4_ECC_ERR_CNT_T; + +typedef struct dpp_se_alg_zgp3_zblk5_ecc_err_cnt_t +{ + ZXIC_UINT32 zgp3_zblk5_ecc_err_cnt; +}DPP_SE_ALG_ZGP3_ZBLK5_ECC_ERR_CNT_T; + +typedef struct dpp_se_alg_zgp3_zblk6_ecc_err_cnt_t +{ + ZXIC_UINT32 zgp3_zblk6_ecc_err_cnt; +}DPP_SE_ALG_ZGP3_ZBLK6_ECC_ERR_CNT_T; + +typedef struct dpp_se_alg_zgp3_zblk7_ecc_err_cnt_t +{ + ZXIC_UINT32 zgp3_zblk7_ecc_err_cnt; +}DPP_SE_ALG_ZGP3_ZBLK7_ECC_ERR_CNT_T; + +typedef struct dpp_se_alg_zcam_hash_p0_err_cnt_t +{ + ZXIC_UINT32 zcam_hash_p0_err_cnt; +}DPP_SE_ALG_ZCAM_HASH_P0_ERR_CNT_T; + +typedef struct dpp_se_alg_zcam_hash_p1_err_cnt_t +{ + ZXIC_UINT32 zcam_hash_p1_err_cnt; +}DPP_SE_ALG_ZCAM_HASH_P1_ERR_CNT_T; + +typedef struct dpp_se_alg_zcam_hash_p2_err_cnt_t +{ + ZXIC_UINT32 zcam_hash_p2_err_cnt; +}DPP_SE_ALG_ZCAM_HASH_P2_ERR_CNT_T; + +typedef struct dpp_se_alg_zcam_hash_p3_err_cnt_t +{ + ZXIC_UINT32 zcam_hash_p3_err_cnt; +}DPP_SE_ALG_ZCAM_HASH_P3_ERR_CNT_T; + +typedef struct dpp_se_alg_zcam_lpm_err_cnt_t +{ + ZXIC_UINT32 zcam_lpm_err_cnt; +}DPP_SE_ALG_ZCAM_LPM_ERR_CNT_T; + +typedef struct dpp_se_alg_hash0_sreq_fifo_parity_err_cnt_t +{ + ZXIC_UINT32 hash0_sreq_fifo_parity_err_cnt; +}DPP_SE_ALG_HASH0_SREQ_FIFO_PARITY_ERR_CNT_T; + +typedef struct dpp_se_alg_hash0_sreq_fifo_int_cnt_t +{ + ZXIC_UINT32 hash0_sreq_fifo_int_cnt; +}DPP_SE_ALG_HASH0_SREQ_FIFO_INT_CNT_T; + +typedef struct dpp_se_alg_hash0_key_fifo_int_cnt_t +{ + ZXIC_UINT32 hash0_key_fifo_int_cnt; +}DPP_SE_ALG_HASH0_KEY_FIFO_INT_CNT_T; + +typedef struct dpp_se_alg_hash0_int_rsp_fifo_parity_err_cnt_t +{ + ZXIC_UINT32 hash0_int_rsp_fifo_parity_err_cnt; +}DPP_SE_ALG_HASH0_INT_RSP_FIFO_PARITY_ERR_CNT_T; + +typedef struct dpp_se_alg_hash0_ext_rsp_fifo_parity_err_cnt_t +{ + ZXIC_UINT32 hash0_ext_rsp_fifo_parity_err_cnt; +}DPP_SE_ALG_HASH0_EXT_RSP_FIFO_PARITY_ERR_CNT_T; + +typedef struct dpp_se_alg_hash0_ext_rsp_fifo_int_cnt_t +{ + ZXIC_UINT32 hash0_ext_rsp_fifo_int_cnt; +}DPP_SE_ALG_HASH0_EXT_RSP_FIFO_INT_CNT_T; + +typedef struct dpp_se_alg_hash0_int_rsp_fifo_int_cnt_t +{ + ZXIC_UINT32 hash0_int_rsp_fifo_int_cnt; +}DPP_SE_ALG_HASH0_INT_RSP_FIFO_INT_CNT_T; + +typedef struct dpp_se_alg_hash1_sreq_fifo_parity_err_cnt_t +{ + ZXIC_UINT32 hash1_sreq_fifo_parity_err_cnt; +}DPP_SE_ALG_HASH1_SREQ_FIFO_PARITY_ERR_CNT_T; + +typedef struct dpp_se_alg_hash1_sreq_fifo_int_cnt_t +{ + ZXIC_UINT32 hash1_sreq_fifo_int_cnt; +}DPP_SE_ALG_HASH1_SREQ_FIFO_INT_CNT_T; + +typedef struct dpp_se_alg_hash1_key_fifo_int_cnt_t +{ + ZXIC_UINT32 hash1_key_fifo_int_cnt; +}DPP_SE_ALG_HASH1_KEY_FIFO_INT_CNT_T; + +typedef struct dpp_se_alg_hash1_int_rsp_fifo_parity_err_cnt_t +{ + ZXIC_UINT32 hash1_int_rsp_fifo_parity_err_cnt; +}DPP_SE_ALG_HASH1_INT_RSP_FIFO_PARITY_ERR_CNT_T; + +typedef struct dpp_se_alg_hash1_ext_rsp_fifo_parity_err_cnt_t +{ + ZXIC_UINT32 hash1_ext_rsp_fifo_parity_err_cnt; +}DPP_SE_ALG_HASH1_EXT_RSP_FIFO_PARITY_ERR_CNT_T; + +typedef struct dpp_se_alg_hash1_ext_rsp_fifo_int_cnt_t +{ + ZXIC_UINT32 hash1_ext_rsp_fifo_int_cnt; +}DPP_SE_ALG_HASH1_EXT_RSP_FIFO_INT_CNT_T; + +typedef struct dpp_se_alg_hash1_int_rsp_fifo_int_cnt_t +{ + ZXIC_UINT32 hash1_int_rsp_fifo_int_cnt; +}DPP_SE_ALG_HASH1_INT_RSP_FIFO_INT_CNT_T; + +typedef struct dpp_se_alg_hash2_sreq_fifo_parity_err_cnt_t +{ + ZXIC_UINT32 hash2_sreq_fifo_parity_err_cnt; +}DPP_SE_ALG_HASH2_SREQ_FIFO_PARITY_ERR_CNT_T; + +typedef struct dpp_se_alg_hash2_sreq_fifo_int_cnt_t +{ + ZXIC_UINT32 hash2_sreq_fifo_int_cnt; +}DPP_SE_ALG_HASH2_SREQ_FIFO_INT_CNT_T; + +typedef struct dpp_se_alg_hash2_key_fifo_int_cnt_t +{ + ZXIC_UINT32 hash2_key_fifo_int_cnt; +}DPP_SE_ALG_HASH2_KEY_FIFO_INT_CNT_T; + +typedef struct dpp_se_alg_hash2_int_rsp_fifo_parity_err_cnt_t +{ + ZXIC_UINT32 hash2_int_rsp_fifo_parity_err_cnt; +}DPP_SE_ALG_HASH2_INT_RSP_FIFO_PARITY_ERR_CNT_T; + +typedef struct dpp_se_alg_hash2_ext_rsp_fifo_parity_err_cnt_t +{ + ZXIC_UINT32 hash2_ext_rsp_fifo_parity_err_cnt; +}DPP_SE_ALG_HASH2_EXT_RSP_FIFO_PARITY_ERR_CNT_T; + +typedef struct dpp_se_alg_hash2_ext_rsp_fifo_int_cnt_t +{ + ZXIC_UINT32 hash2_ext_rsp_fifo_int_cnt; +}DPP_SE_ALG_HASH2_EXT_RSP_FIFO_INT_CNT_T; + +typedef struct dpp_se_alg_hash2_int_rsp_fifo_int_cnt_t +{ + ZXIC_UINT32 hash2_int_rsp_fifo_int_cnt; +}DPP_SE_ALG_HASH2_INT_RSP_FIFO_INT_CNT_T; + +typedef struct dpp_se_alg_hash3_sreq_fifo_parity_err_cnt_t +{ + ZXIC_UINT32 hash3_sreq_fifo_parity_err_cnt; +}DPP_SE_ALG_HASH3_SREQ_FIFO_PARITY_ERR_CNT_T; + +typedef struct dpp_se_alg_hash3_sreq_fifo_int_cnt_t +{ + ZXIC_UINT32 hash3_sreq_fifo_int_cnt; +}DPP_SE_ALG_HASH3_SREQ_FIFO_INT_CNT_T; + +typedef struct dpp_se_alg_hash3_key_fifo_int_cnt_t +{ + ZXIC_UINT32 hash3_key_fifo_int_cnt; +}DPP_SE_ALG_HASH3_KEY_FIFO_INT_CNT_T; + +typedef struct dpp_se_alg_hash3_int_rsp_fifo_parity_err_cnt_t +{ + ZXIC_UINT32 hash3_int_rsp_fifo_parity_err_cnt; +}DPP_SE_ALG_HASH3_INT_RSP_FIFO_PARITY_ERR_CNT_T; + +typedef struct dpp_se_alg_hash3_ext_rsp_fifo_parity_err_cnt_t +{ + ZXIC_UINT32 hash3_ext_rsp_fifo_parity_err_cnt; +}DPP_SE_ALG_HASH3_EXT_RSP_FIFO_PARITY_ERR_CNT_T; + +typedef struct dpp_se_alg_hash3_ext_rsp_fifo_int_cnt_t +{ + ZXIC_UINT32 hash3_ext_rsp_fifo_int_cnt; +}DPP_SE_ALG_HASH3_EXT_RSP_FIFO_INT_CNT_T; + +typedef struct dpp_se_alg_hash3_int_rsp_fifo_int_cnt_t +{ + ZXIC_UINT32 hash3_int_rsp_fifo_int_cnt; +}DPP_SE_ALG_HASH3_INT_RSP_FIFO_INT_CNT_T; + +typedef struct dpp_se_alg_lpm_ext_rsp_fifo_int_cnt_t +{ + ZXIC_UINT32 lpm_ext_rsp_fifo_int_cnt; +}DPP_SE_ALG_LPM_EXT_RSP_FIFO_INT_CNT_T; + +typedef struct dpp_se_alg_lpm_ext_v6_fifo_int_cnt_t +{ + ZXIC_UINT32 lpm_ext_v6_fifo_int_cnt; +}DPP_SE_ALG_LPM_EXT_V6_FIFO_INT_CNT_T; + +typedef struct dpp_se_alg_lpm_ext_v4_fifo_int_cnt_t +{ + ZXIC_UINT32 lpm_ext_v4_fifo_int_cnt; +}DPP_SE_ALG_LPM_EXT_V4_FIFO_INT_CNT_T; + +typedef struct dpp_se_alg_lpm_ext_addr_fifo_int_cnt_t +{ + ZXIC_UINT32 lpm_ext_addr_fifo_int_cnt; +}DPP_SE_ALG_LPM_EXT_ADDR_FIFO_INT_CNT_T; + +typedef struct dpp_se_alg_lpm_ext_v4_fifo_parity_err_cnt_t +{ + ZXIC_UINT32 lpm_ext_v4_fifo_parity_err_cnt; +}DPP_SE_ALG_LPM_EXT_V4_FIFO_PARITY_ERR_CNT_T; + +typedef struct dpp_se_alg_lpm_ext_v6_fifo_parity_err_cnt_t +{ + ZXIC_UINT32 lpm_ext_v6_fifo_parity_err_cnt; +}DPP_SE_ALG_LPM_EXT_V6_FIFO_PARITY_ERR_CNT_T; + +typedef struct dpp_se_alg_lpm_ext_rsp_fifo_parity_err_cnt_t +{ + ZXIC_UINT32 lpm_ext_rsp_fifo_parity_err_cnt; +}DPP_SE_ALG_LPM_EXT_RSP_FIFO_PARITY_ERR_CNT_T; + +typedef struct dpp_se_alg_lpm_as_req_fifo_int_cnt_t +{ + ZXIC_UINT32 lpm_as_req_fifo_int_cnt; +}DPP_SE_ALG_LPM_AS_REQ_FIFO_INT_CNT_T; + +typedef struct dpp_se_alg_lpm_as_int_rsp_fifo_int_cnt_t +{ + ZXIC_UINT32 lpm_as_int_rsp_fifo_int_cnt; +}DPP_SE_ALG_LPM_AS_INT_RSP_FIFO_INT_CNT_T; + +typedef struct dpp_se_alg_se_alg_int_status_t +{ + ZXIC_UINT32 schd_int_unmask_flag; + ZXIC_UINT32 zblk_ecc_int_unmask_flag; + ZXIC_UINT32 hash0_int_unmask_flag; + ZXIC_UINT32 hash1_int_unmask_flag; + ZXIC_UINT32 hash2_int_unmask_flag; + ZXIC_UINT32 hash3_int_unmask_flag; + ZXIC_UINT32 lpm_int_unmask_flag; +}DPP_SE_ALG_SE_ALG_INT_STATUS_T; + +typedef struct dpp_se_alg_schd_int_en_t +{ + ZXIC_UINT32 wr_rsp_fifo_ovfl; + ZXIC_UINT32 init_rd_cft_en; + ZXIC_UINT32 schd_lpm_fifo_parity_errl; + ZXIC_UINT32 schd_hash3_fifo_parity_err; + ZXIC_UINT32 schd_hash2_fifo_parity_err; + ZXIC_UINT32 schd_hash1_fifo_parity_err; + ZXIC_UINT32 schd_hash0_fifo_parity_err; + ZXIC_UINT32 schd_learn_fifo_parity_err; + ZXIC_UINT32 schd_lpm_fifo_ovfl; + ZXIC_UINT32 schd_hash3_fifo_ovfl; + ZXIC_UINT32 schd_hash2_fifo_unfl; + ZXIC_UINT32 schd_hash1_fifo_ovfl; + ZXIC_UINT32 schd_hash0_fifo_ovfl; + ZXIC_UINT32 schd_learn_fifo_ovfl; +}DPP_SE_ALG_SCHD_INT_EN_T; + +typedef struct dpp_se_alg_schd_int_mask_t +{ + ZXIC_UINT32 schd_int_mask; +}DPP_SE_ALG_SCHD_INT_MASK_T; + +typedef struct dpp_se_alg_schd_int_status_t +{ + ZXIC_UINT32 schd_int_status; +}DPP_SE_ALG_SCHD_INT_STATUS_T; + +typedef struct dpp_se_alg_zblk_ecc_int_en_t +{ + ZXIC_UINT32 zblk_ecc_int_en; +}DPP_SE_ALG_ZBLK_ECC_INT_EN_T; + +typedef struct dpp_se_alg_zblk_ecc_int_mask_t +{ + ZXIC_UINT32 zblk_ecc_int_mask; +}DPP_SE_ALG_ZBLK_ECC_INT_MASK_T; + +typedef struct dpp_se_alg_zblk_ecc_int_status_t +{ + ZXIC_UINT32 zblk_ecc_int_status; +}DPP_SE_ALG_ZBLK_ECC_INT_STATUS_T; + +typedef struct dpp_se_alg_hash0_int_en_t +{ + ZXIC_UINT32 zcam_hash_p0_err_en; + ZXIC_UINT32 hash0_agree_int_fifo_ovf_en; + ZXIC_UINT32 hash0_agree_ext_fifo_ovf_en; + ZXIC_UINT32 hash0_agree_ext_fifo_parity_err_en; + ZXIC_UINT32 hash0_agree_int_fifo_parity_err_en; + ZXIC_UINT32 hash0_key_fifo_ovfl_en; + ZXIC_UINT32 hash0_sreq_fifo_ovfl_en; + ZXIC_UINT32 hash0_key_fifo_parity_err_en; +}DPP_SE_ALG_HASH0_INT_EN_T; + +typedef struct dpp_se_alg_hash0_int_mask_t +{ + ZXIC_UINT32 hash0_int_mask; +}DPP_SE_ALG_HASH0_INT_MASK_T; + +typedef struct dpp_se_alg_hash0_int_status_t +{ + ZXIC_UINT32 hash0_int_status; +}DPP_SE_ALG_HASH0_INT_STATUS_T; + +typedef struct dpp_se_alg_hash1_int_en_t +{ + ZXIC_UINT32 zcam_hash_p1_err_en; + ZXIC_UINT32 hash1_agree_int_fifo_ovf_en; + ZXIC_UINT32 hash1_agree_ext_fifo_ovf_en; + ZXIC_UINT32 hash1_agree_ext_fifo_parity_err_en; + ZXIC_UINT32 hash1_agree_int_fifo_parity_err_en; + ZXIC_UINT32 hash1_key_fifo_ovfl_en; + ZXIC_UINT32 hash1_sreq_fifo_ovfl_en; + ZXIC_UINT32 hash1_key_fifo_parity_err_en; +}DPP_SE_ALG_HASH1_INT_EN_T; + +typedef struct dpp_se_alg_hash1_int_mask_t +{ + ZXIC_UINT32 hash1_int_mask; +}DPP_SE_ALG_HASH1_INT_MASK_T; + +typedef struct dpp_se_alg_hash1_int_status_t +{ + ZXIC_UINT32 hash1_int_status; +}DPP_SE_ALG_HASH1_INT_STATUS_T; + +typedef struct dpp_se_alg_hash2_int_en_t +{ + ZXIC_UINT32 zcam_hash_p2_err_en; + ZXIC_UINT32 hash2_agree_int_fifo_ovf_en; + ZXIC_UINT32 hash2_agree_ext_fifo_ovf_en; + ZXIC_UINT32 hash2_agree_ext_fifo_parity_err_en; + ZXIC_UINT32 hash2_agree_int_fifo_parity_err_en; + ZXIC_UINT32 hash2_key_fifo_ovfl_en; + ZXIC_UINT32 hash2_sreq_fifo_ovfl_en; + ZXIC_UINT32 hash2_key_fifo_parity_err_en; +}DPP_SE_ALG_HASH2_INT_EN_T; + +typedef struct dpp_se_alg_hash2_int_mask_t +{ + ZXIC_UINT32 hash2_int_mask; +}DPP_SE_ALG_HASH2_INT_MASK_T; + +typedef struct dpp_se_alg_hash2_int_status_t +{ + ZXIC_UINT32 hash2_int_status; +}DPP_SE_ALG_HASH2_INT_STATUS_T; + +typedef struct dpp_se_alg_hash3_int_en_t +{ + ZXIC_UINT32 zcam_hash_p3_err_en; + ZXIC_UINT32 hash3_agree_int_fifo_ovf_en; + ZXIC_UINT32 hash3_agree_ext_fifo_ovf_en; + ZXIC_UINT32 hash3_agree_ext_fifo_parity_err_en; + ZXIC_UINT32 hash3_agree_int_fifo_parity_err_en; + ZXIC_UINT32 hash3_key_fifo_ovfl_en; + ZXIC_UINT32 hash3_sreq_fifo_ovfl_en; + ZXIC_UINT32 hash3_key_fifo_parity_err_en; +}DPP_SE_ALG_HASH3_INT_EN_T; + +typedef struct dpp_se_alg_hash3_int_mask_t +{ + ZXIC_UINT32 hash3_int_mask; +}DPP_SE_ALG_HASH3_INT_MASK_T; + +typedef struct dpp_se_alg_hash3_int_status_t +{ + ZXIC_UINT32 hash3_int_status; +}DPP_SE_ALG_HASH3_INT_STATUS_T; + +typedef struct dpp_se_alg_lpm_int_en_t +{ + ZXIC_UINT32 zcam_lpm_err_en; + ZXIC_UINT32 lpm_as_int_rsp_fifo_ovfl_en; + ZXIC_UINT32 lpm_as_req_fifo_ovfl_en; + ZXIC_UINT32 lpm_ext_ddr_rsp_fifo_parity_en; + ZXIC_UINT32 lpm_ext_v6_key_parity_en; + ZXIC_UINT32 lpm_ext_v4_key_parity_en; + ZXIC_UINT32 lpm_ext_addr_fifo_ovfl_en; + ZXIC_UINT32 lpm_ext_v4_fifo_ovfl_en; + ZXIC_UINT32 lpm_ext_v6_fifo_ovfl_en; + ZXIC_UINT32 lpm_ext_ddr_rsp_ovf_en; +}DPP_SE_ALG_LPM_INT_EN_T; + +typedef struct dpp_se_alg_lpm_int_mask_t +{ + ZXIC_UINT32 lpm_int_mask; +}DPP_SE_ALG_LPM_INT_MASK_T; + +typedef struct dpp_se_alg_lpm_int_status_t +{ + ZXIC_UINT32 lpm_int_status; +}DPP_SE_ALG_LPM_INT_STATUS_T; + +typedef struct dpp_se_alg_zblock_lpm_mask0_t +{ + ZXIC_UINT32 vpn_id_mask; + ZXIC_UINT32 prefix0_mask; + ZXIC_UINT32 prefix1_mask; + ZXIC_UINT32 prefix2_mask; + ZXIC_UINT32 prefix3_mask; +}DPP_SE_ALG_ZBLOCK_LPM_MASK0_T; + +typedef struct dpp_se_alg_zblock_lpm_mask1_t +{ + ZXIC_UINT32 vpn_id_mask; + ZXIC_UINT32 prefix0_mask; + ZXIC_UINT32 prefix1_mask; + ZXIC_UINT32 prefix2_mask; + ZXIC_UINT32 prefix3_mask; +}DPP_SE_ALG_ZBLOCK_LPM_MASK1_T; + +typedef struct dpp_se_alg_zblock_lpm_mask2_t +{ + ZXIC_UINT32 vpn_id_mask; + ZXIC_UINT32 prefix0_mask; + ZXIC_UINT32 prefix1_mask; + ZXIC_UINT32 prefix2_mask; + ZXIC_UINT32 prefix3_mask; +}DPP_SE_ALG_ZBLOCK_LPM_MASK2_T; + +typedef struct dpp_se_alg_zblock_lpm_mask3_t +{ + ZXIC_UINT32 vpn_id_mask; + ZXIC_UINT32 prefix0_mask; + ZXIC_UINT32 prefix1_mask; + ZXIC_UINT32 prefix2_mask; + ZXIC_UINT32 prefix3_mask; +}DPP_SE_ALG_ZBLOCK_LPM_MASK3_T; + +typedef struct dpp_se_alg_zblock_default_route0_t +{ + ZXIC_UINT32 vpn_id; + ZXIC_UINT32 vpn_dresult; + ZXIC_UINT32 vpn_flag; + ZXIC_UINT32 vpn_vld; +}DPP_SE_ALG_ZBLOCK_DEFAULT_ROUTE0_T; + +typedef struct dpp_se_alg_zblock_default_route1_t +{ + ZXIC_UINT32 vpn_id; + ZXIC_UINT32 vpn_dresult; + ZXIC_UINT32 vpn_flag; + ZXIC_UINT32 vpn_vld; +}DPP_SE_ALG_ZBLOCK_DEFAULT_ROUTE1_T; + +typedef struct dpp_se_alg_zblock_default_route2_t +{ + ZXIC_UINT32 vpn_id; + ZXIC_UINT32 vpn_dresult; + ZXIC_UINT32 vpn_flag; + ZXIC_UINT32 vpn_vld; +}DPP_SE_ALG_ZBLOCK_DEFAULT_ROUTE2_T; + +typedef struct dpp_se_alg_zblock_default_route3_t +{ + ZXIC_UINT32 vpn_id; + ZXIC_UINT32 vpn_dresult; + ZXIC_UINT32 vpn_flag; + ZXIC_UINT32 vpn_vld; +}DPP_SE_ALG_ZBLOCK_DEFAULT_ROUTE3_T; + +typedef struct dpp_se_alg_zblock_default_route4_t +{ + ZXIC_UINT32 vpn_id; + ZXIC_UINT32 vpn_dresult; + ZXIC_UINT32 vpn_flag; + ZXIC_UINT32 vpn_vld; +}DPP_SE_ALG_ZBLOCK_DEFAULT_ROUTE4_T; + +typedef struct dpp_se_alg_zblock_default_route5_t +{ + ZXIC_UINT32 vpn_id; + ZXIC_UINT32 vpn_dresult; + ZXIC_UINT32 vpn_flag; + ZXIC_UINT32 vpn_vld; +}DPP_SE_ALG_ZBLOCK_DEFAULT_ROUTE5_T; + +typedef struct dpp_se_alg_zblock_default_route6_t +{ + ZXIC_UINT32 vpn_id; + ZXIC_UINT32 vpn_dresult; + ZXIC_UINT32 vpn_flag; + ZXIC_UINT32 vpn_vld; +}DPP_SE_ALG_ZBLOCK_DEFAULT_ROUTE6_T; + +typedef struct dpp_se_alg_zblock_default_route7_t +{ + ZXIC_UINT32 vpn_id; + ZXIC_UINT32 vpn_dresult; + ZXIC_UINT32 vpn_flag; + ZXIC_UINT32 vpn_vld; +}DPP_SE_ALG_ZBLOCK_DEFAULT_ROUTE7_T; + +typedef struct dpp_se_alg_zblock_hash_listtable_item0_t +{ + ZXIC_UINT32 hash_item; +}DPP_SE_ALG_ZBLOCK_HASH_LISTTABLE_ITEM0_T; + +typedef struct dpp_se_alg_zblock_hash_listtable_item1_t +{ + ZXIC_UINT32 hash_item; +}DPP_SE_ALG_ZBLOCK_HASH_LISTTABLE_ITEM1_T; + +typedef struct dpp_se_alg_zblock_hash_listtable_item2_t +{ + ZXIC_UINT32 hash_item; +}DPP_SE_ALG_ZBLOCK_HASH_LISTTABLE_ITEM2_T; + +typedef struct dpp_se_alg_zblock_hash_listtable_item3_t +{ + ZXIC_UINT32 hash_item; +}DPP_SE_ALG_ZBLOCK_HASH_LISTTABLE_ITEM3_T; + +typedef struct dpp_se_alg_zblock_ecc_err_status_t +{ + ZXIC_UINT32 sram3_ecc_err; + ZXIC_UINT32 sram2_ecc_err; + ZXIC_UINT32 sram1_ecc_err; + ZXIC_UINT32 sram0_ecc_err; +}DPP_SE_ALG_ZBLOCK_ECC_ERR_STATUS_T; + +typedef struct dpp_se_alg_zblock_lpm_v6_sram_cmp_t +{ + ZXIC_UINT32 sram_cmp_flag; +}DPP_SE_ALG_ZBLOCK_LPM_V6_SRAM_CMP_T; + +typedef struct dpp_se_alg_zblock_lpm_v4_sram_cmp_t +{ + ZXIC_UINT32 sram_cmp_flag; +}DPP_SE_ALG_ZBLOCK_LPM_V4_SRAM_CMP_T; + +typedef struct dpp_se_parser_kschd_pful_cfg_t +{ + ZXIC_UINT32 kschd_pful_assert; + ZXIC_UINT32 kschd_pful_negate; +}DPP_SE_PARSER_KSCHD_PFUL_CFG_T; + +typedef struct dpp_se_parser_debug_cnt_mode_t +{ + ZXIC_UINT32 cnt_rd_mode; + ZXIC_UINT32 cnt_overflow_mode; +}DPP_SE_PARSER_DEBUG_CNT_MODE_T; + +typedef struct dpp_se_parser_parser_int_en_t +{ + ZXIC_UINT32 parser_int_en; +}DPP_SE_PARSER_PARSER_INT_EN_T; + +typedef struct dpp_se_parser_parser_int_mask_t +{ + ZXIC_UINT32 parser_int_mask; +}DPP_SE_PARSER_PARSER_INT_MASK_T; + +typedef struct dpp_se_parser_parser_int_status_t +{ + ZXIC_UINT32 parser_int_status; +}DPP_SE_PARSER_PARSER_INT_STATUS_T; + +typedef struct dpp_se_parser_parser_int_unmask_flag_t +{ + ZXIC_UINT32 parser_int_unmask_flag; +}DPP_SE_PARSER_PARSER_INT_UNMASK_FLAG_T; + +typedef struct dpp_se_parser_ecc_bypass_read_t +{ + ZXIC_UINT32 ecc_bypass_read; +}DPP_SE_PARSER_ECC_BYPASS_READ_T; + +typedef struct dpp_se_parser_mex0_5_req_cnt_t +{ + ZXIC_UINT32 mex0_5_req_cnt; +}DPP_SE_PARSER_MEX0_5_REQ_CNT_T; + +typedef struct dpp_se_parser_kschd_req0_5_cnt_t +{ + ZXIC_UINT32 kschd_req0_5_cnt; +}DPP_SE_PARSER_KSCHD_REQ0_5_CNT_T; + +typedef struct dpp_se_parser_kschd_parser_fc0_5_cnt_t +{ + ZXIC_UINT32 kschd_parser_fc0_5_cnt; +}DPP_SE_PARSER_KSCHD_PARSER_FC0_5_CNT_T; + +typedef struct dpp_se_parser_se_ppu_mex0_5_fc_cnt_t +{ + ZXIC_UINT32 se_ppu_mex0_5_fc_cnt; +}DPP_SE_PARSER_SE_PPU_MEX0_5_FC_CNT_T; + +typedef struct dpp_se_parser_smmu0_marc_fc_cnt_t +{ + ZXIC_UINT32 smmu0_marc_fc_cnt; +}DPP_SE_PARSER_SMMU0_MARC_FC_CNT_T; + +typedef struct dpp_se_parser_smmu0_marc_key_cnt_t +{ + ZXIC_UINT32 smmu0_marc_key_cnt; +}DPP_SE_PARSER_SMMU0_MARC_KEY_CNT_T; + +typedef struct dpp_se_parser_cmmu_key_cnt_t +{ + ZXIC_UINT32 cmmu_key_cnt; +}DPP_SE_PARSER_CMMU_KEY_CNT_T; + +typedef struct dpp_se_parser_cmmu_parser_fc_cnt_t +{ + ZXIC_UINT32 cmmu_parser_fc_cnt; +}DPP_SE_PARSER_CMMU_PARSER_FC_CNT_T; + +typedef struct dpp_se_parser_marc_tab_type_err_mex0_5_cnt_t +{ + ZXIC_UINT32 marc_tab_type_err_mex0_5_cnt; +}DPP_SE_PARSER_MARC_TAB_TYPE_ERR_MEX0_5_CNT_T; + +typedef struct dpp_se_parser_eram_fulladdr_drop_cnt_t +{ + ZXIC_UINT32 eram_fulladdr_drop_cnt; +}DPP_SE_PARSER_ERAM_FULLADDR_DROP_CNT_T; + +typedef struct dpp_se_as_hash0_pful_cfg_t +{ + ZXIC_UINT32 hash0_pful_cfg; +}DPP_SE_AS_HASH0_PFUL_CFG_T; + +typedef struct dpp_se_as_hash1_pful_cfg_t +{ + ZXIC_UINT32 hash1_pful_cfg; +}DPP_SE_AS_HASH1_PFUL_CFG_T; + +typedef struct dpp_se_as_hash2_pful_cfg_t +{ + ZXIC_UINT32 hash2_pful_cfg; +}DPP_SE_AS_HASH2_PFUL_CFG_T; + +typedef struct dpp_se_as_hash3_pful_cfg_t +{ + ZXIC_UINT32 hash3_pful_cfg; +}DPP_SE_AS_HASH3_PFUL_CFG_T; + +typedef struct dpp_se_as_pbu_pful_cfg_t +{ + ZXIC_UINT32 pbu_pful_cfg; +}DPP_SE_AS_PBU_PFUL_CFG_T; + +typedef struct dpp_se_as_lpm_pful_cfg_t +{ + ZXIC_UINT32 lpm_pful_cfg; +}DPP_SE_AS_LPM_PFUL_CFG_T; + +typedef struct dpp_se_as_etcam_pful_cfg_t +{ + ZXIC_UINT32 etcam_pful_cfg; +}DPP_SE_AS_ETCAM_PFUL_CFG_T; + +typedef struct dpp_se_as_as_learn0_fifo_cfg_t +{ + ZXIC_UINT32 as_learn1_pful_negate; + ZXIC_UINT32 as_learn1_pful_asert; + ZXIC_UINT32 as_learn0_pful_negate; + ZXIC_UINT32 as_learn0_pful_asert; +}DPP_SE_AS_AS_LEARN0_FIFO_CFG_T; + +typedef struct dpp_se_as_as_learn1_fifo_cfg_t +{ + ZXIC_UINT32 as_learn3_pful_negate; + ZXIC_UINT32 as_learn3_pful_asert; + ZXIC_UINT32 as_learn2_pful_negate; + ZXIC_UINT32 as_learn2_pful_asert; +}DPP_SE_AS_AS_LEARN1_FIFO_CFG_T; + +typedef struct dpp_se_as_as_dma_fifo_cfg_t +{ + ZXIC_UINT32 as_dma_fifo_cfg; +}DPP_SE_AS_AS_DMA_FIFO_CFG_T; + +typedef struct dpp_se_as_age_pful_cfg_t +{ + ZXIC_UINT32 age_pful_cfg; +}DPP_SE_AS_AGE_PFUL_CFG_T; + +typedef struct dpp_se_as_etcam_rsp_cfg_t +{ + ZXIC_UINT32 eram_rsp_pful_negate; + ZXIC_UINT32 eram_rsp_pful_assert; + ZXIC_UINT32 etcam_rsp_pful_negate; + ZXIC_UINT32 etcam_rsp_pful_assert; +}DPP_SE_AS_ETCAM_RSP_CFG_T; + +typedef struct dpp_se_as_pbu_ecc_bypass_read_t +{ + ZXIC_UINT32 pbu_ecc_bypass_read; +}DPP_SE_AS_PBU_ECC_BYPASS_READ_T; + +typedef struct dpp_se_as_etcam0_ecc_bypass_read_t +{ + ZXIC_UINT32 etcam0_ecc_bypass_read; +}DPP_SE_AS_ETCAM0_ECC_BYPASS_READ_T; + +typedef struct dpp_se_as_etcam1_ecc_bypass_read_t +{ + ZXIC_UINT32 etcam1_ecc_bypass_read; +}DPP_SE_AS_ETCAM1_ECC_BYPASS_READ_T; + +typedef struct dpp_se_as_lpm_ecc_bypass_read_t +{ + ZXIC_UINT32 lpm_ecc_bypass_read; +}DPP_SE_AS_LPM_ECC_BYPASS_READ_T; + +typedef struct dpp_se_as_hash_ecc_bypass_read_t +{ + ZXIC_UINT32 hash3_ecc_bypass_read; + ZXIC_UINT32 hash2_ecc_bypass_read; + ZXIC_UINT32 hash1_ecc_bypass_read; + ZXIC_UINT32 hash0_ecc_bypass_read; +}DPP_SE_AS_HASH_ECC_BYPASS_READ_T; + +typedef struct dpp_se_as_hash_learn_ecc_bypass_read_t +{ + ZXIC_UINT32 hash_learn_ecc_bypass_read; +}DPP_SE_AS_HASH_LEARN_ECC_BYPASS_READ_T; + +typedef struct dpp_se_as_debug_cnt_mode_t +{ + ZXIC_UINT32 cnt_rd_mode; + ZXIC_UINT32 cnt_overflow_mode; +}DPP_SE_AS_DEBUG_CNT_MODE_T; + +typedef struct dpp_se_as_as_int_0_en_t +{ + ZXIC_UINT32 as_int_0_en; +}DPP_SE_AS_AS_INT_0_EN_T; + +typedef struct dpp_se_as_as_int_0_mask_t +{ + ZXIC_UINT32 as_int_0_mask; +}DPP_SE_AS_AS_INT_0_MASK_T; + +typedef struct dpp_se_as_as_int_1_en_t +{ + ZXIC_UINT32 as_int_1_en; +}DPP_SE_AS_AS_INT_1_EN_T; + +typedef struct dpp_se_as_as_int_1_mask_t +{ + ZXIC_UINT32 as_int_1_mask; +}DPP_SE_AS_AS_INT_1_MASK_T; + +typedef struct dpp_se_as_as_int_2_en_t +{ + ZXIC_UINT32 as_int_2_en; +}DPP_SE_AS_AS_INT_2_EN_T; + +typedef struct dpp_se_as_as_int_2_mask_t +{ + ZXIC_UINT32 as_int_2_mask; +}DPP_SE_AS_AS_INT_2_MASK_T; + +typedef struct dpp_se_as_as_int_0_status_t +{ + ZXIC_UINT32 port0_int_status; +}DPP_SE_AS_AS_INT_0_STATUS_T; + +typedef struct dpp_se_as_as_int_1_status_t +{ + ZXIC_UINT32 port1_int_status; +}DPP_SE_AS_AS_INT_1_STATUS_T; + +typedef struct dpp_se_as_as_int_2_status_t +{ + ZXIC_UINT32 port2_int_status; +}DPP_SE_AS_AS_INT_2_STATUS_T; + +typedef struct dpp_se_as_se_as_int_status_t +{ + ZXIC_UINT32 as_int_2_unmask_flag; + ZXIC_UINT32 as_int_1_unmask_flag; + ZXIC_UINT32 as_int_0_unmask_flag; +}DPP_SE_AS_SE_AS_INT_STATUS_T; + +typedef struct dpp_se_as_hash0_3_wr_req_cnt_t +{ + ZXIC_UINT32 hash0_3_wr_req_cnt; +}DPP_SE_AS_HASH0_3_WR_REQ_CNT_T; + +typedef struct dpp_se_as_smmu0_etcam0_1_fc_cnt_t +{ + ZXIC_UINT32 smmu0_etcam0_1_fc_cnt; +}DPP_SE_AS_SMMU0_ETCAM0_1_FC_CNT_T; + +typedef struct dpp_se_as_etcam0_1_smmu0_req_cnt_t +{ + ZXIC_UINT32 etcam0_1_smmu0_req_cnt; +}DPP_SE_AS_ETCAM0_1_SMMU0_REQ_CNT_T; + +typedef struct dpp_se_as_smmu0_etcam0_1_rsp_cnt_t +{ + ZXIC_UINT32 smmu0_etcam0_1_rsp_cnt; +}DPP_SE_AS_SMMU0_ETCAM0_1_RSP_CNT_T; + +typedef struct dpp_se_as_as_hla_hash_p0_3_key_cnt_t +{ + ZXIC_UINT32 as_hla_hash_p0_3_key_cnt; +}DPP_SE_AS_AS_HLA_HASH_P0_3_KEY_CNT_T; + +typedef struct dpp_se_as_as_hla_lpm_p0_key_cnt_t +{ + ZXIC_UINT32 as_hla_lpm_p0_key_cnt; +}DPP_SE_AS_AS_HLA_LPM_P0_KEY_CNT_T; + +typedef struct dpp_se_as_alg_as_hash_p0_3_rsp_cnt_t +{ + ZXIC_UINT32 alg_as_hash_p0_3_rsp_cnt; +}DPP_SE_AS_ALG_AS_HASH_P0_3_RSP_CNT_T; + +typedef struct dpp_se_as_alg_as_hash_p0_3_smf_rsp_cnt_t +{ + ZXIC_UINT32 alg_as_hash_p0_3_smf_rsp_cnt; +}DPP_SE_AS_ALG_AS_HASH_P0_3_SMF_RSP_CNT_T; + +typedef struct dpp_se_as_alg_as_lpm_p0_rsp_cnt_t +{ + ZXIC_UINT32 alg_as_lpm_p0_rsp_cnt; +}DPP_SE_AS_ALG_AS_LPM_P0_RSP_CNT_T; + +typedef struct dpp_se_as_alg_as_lpm_p0_3_smf_rsp_cnt_t +{ + ZXIC_UINT32 alg_as_lpm_p0_3_smf_rsp_cnt; +}DPP_SE_AS_ALG_AS_LPM_P0_3_SMF_RSP_CNT_T; + +typedef struct dpp_se_as_as_pbu_key_cnt_t +{ + ZXIC_UINT32 as_pbu_key_cnt; +}DPP_SE_AS_AS_PBU_KEY_CNT_T; + +typedef struct dpp_se_as_pbu_se_dpi_rsp_dat_cnt_t +{ + ZXIC_UINT32 pbu_se_dpi_rsp_dat_cnt; +}DPP_SE_AS_PBU_SE_DPI_RSP_DAT_CNT_T; + +typedef struct dpp_se_as_as_etcam_ctrl_req0_cnt_t +{ + ZXIC_UINT32 as_etcam_ctrl_req0_cnt; +}DPP_SE_AS_AS_ETCAM_CTRL_REQ0_CNT_T; + +typedef struct dpp_se_as_etcam_ctrl_as_index0_1_cnt_t +{ + ZXIC_UINT32 etcam_ctrl_as_index0_1_cnt; +}DPP_SE_AS_ETCAM_CTRL_AS_INDEX0_1_CNT_T; + +typedef struct dpp_se_as_etcam_ctrl_as_hit0_1_cnt_t +{ + ZXIC_UINT32 etcam_ctrl_as_hit0_1_cnt; +}DPP_SE_AS_ETCAM_CTRL_AS_HIT0_1_CNT_T; + +typedef struct dpp_se_as_as_smmu0_req_cnt_t +{ + ZXIC_UINT32 as_smmu0_req_cnt; +}DPP_SE_AS_AS_SMMU0_REQ_CNT_T; + +typedef struct dpp_se_as_learn_hla_wr_cnt_t +{ + ZXIC_UINT32 learn_hla_wr_cnt; +}DPP_SE_AS_LEARN_HLA_WR_CNT_T; + +typedef struct dpp_se_as_as_smmu1_req_cnt_t +{ + ZXIC_UINT32 as_smmu1_req_cnt; +}DPP_SE_AS_AS_SMMU1_REQ_CNT_T; + +typedef struct dpp_se_as_se_cfg_mac_dat_cnt_t +{ + ZXIC_UINT32 se_cfg_mac_dat_cnt; +}DPP_SE_AS_SE_CFG_MAC_DAT_CNT_T; + +typedef struct dpp_se_as_alg_as_hash_p0_3_fc_cnt_t +{ + ZXIC_UINT32 alg_as_hash_p0_3_fc_cnt; +}DPP_SE_AS_ALG_AS_HASH_P0_3_FC_CNT_T; + +typedef struct dpp_se_as_alg_as_lpm_p0_fc_cnt_t +{ + ZXIC_UINT32 alg_as_lpm_p0_fc_cnt; +}DPP_SE_AS_ALG_AS_LPM_P0_FC_CNT_T; + +typedef struct dpp_se_as_as_alg_hash_p0_3_fc_cnt_t +{ + ZXIC_UINT32 as_alg_hash_p0_3_fc_cnt; +}DPP_SE_AS_AS_ALG_HASH_P0_3_FC_CNT_T; + +typedef struct dpp_se_as_as_alg_lpm_p0_fc_cnt_t +{ + ZXIC_UINT32 as_alg_lpm_p0_fc_cnt; +}DPP_SE_AS_AS_ALG_LPM_P0_FC_CNT_T; + +typedef struct dpp_se_as_as_pbu_fc_cnt_t +{ + ZXIC_UINT32 as_pbu_fc_cnt; +}DPP_SE_AS_AS_PBU_FC_CNT_T; + +typedef struct dpp_se_as_pbu_se_dpi_key_fc_cnt_t +{ + ZXIC_UINT32 pbu_se_dpi_key_fc_cnt; +}DPP_SE_AS_PBU_SE_DPI_KEY_FC_CNT_T; + +typedef struct dpp_se_as_as_etcam_ctrl_fc0_1_cnt_t +{ + ZXIC_UINT32 as_etcam_ctrl_fc0_1_cnt; +}DPP_SE_AS_AS_ETCAM_CTRL_FC0_1_CNT_T; + +typedef struct dpp_se_as_etcam_ctrl_as_fc0_1_cnt_t +{ + ZXIC_UINT32 etcam_ctrl_as_fc0_1_cnt; +}DPP_SE_AS_ETCAM_CTRL_AS_FC0_1_CNT_T; + +typedef struct dpp_se_as_smmu0_as_mac_age_fc_cnt_t +{ + ZXIC_UINT32 smmu0_as_mac_age_fc_cnt; +}DPP_SE_AS_SMMU0_AS_MAC_AGE_FC_CNT_T; + +typedef struct dpp_se_as_alg_learn_fc_cnt_t +{ + ZXIC_UINT32 alg_learn_fc_cnt; +}DPP_SE_AS_ALG_LEARN_FC_CNT_T; + +typedef struct dpp_se_as_smmu1_as_fc_cnt_t +{ + ZXIC_UINT32 smmu1_as_fc_cnt; +}DPP_SE_AS_SMMU1_AS_FC_CNT_T; + +typedef struct dpp_se_as_cfg_se_mac_fc_cnt_t +{ + ZXIC_UINT32 cfg_se_mac_fc_cnt; +}DPP_SE_AS_CFG_SE_MAC_FC_CNT_T; + +typedef struct dpp_se_kschd_kschd_cpu_rdy_t +{ + ZXIC_UINT32 kschd_cpu_rdy; +}DPP_SE_KSCHD_KSCHD_CPU_RDY_T; + +typedef struct dpp_se_kschd_ppu0_ecc_bypass_read_t +{ + ZXIC_UINT32 ppu0_ecc_bypass_read; +}DPP_SE_KSCHD_PPU0_ECC_BYPASS_READ_T; + +typedef struct dpp_se_kschd_pbu_ecc_bypass_read_t +{ + ZXIC_UINT32 pbu_ecc_bypass_read; +}DPP_SE_KSCHD_PBU_ECC_BYPASS_READ_T; + +typedef struct dpp_se_kschd_smmu1_ecc_bypass_read_t +{ + ZXIC_UINT32 u3_smmu1_ecc_bypass_read; + ZXIC_UINT32 u2_smmu1_ecc_bypass_read; + ZXIC_UINT32 u1_smmu1_ecc_bypass_read; + ZXIC_UINT32 u0_smmu1_ecc_bypass_read; +}DPP_SE_KSCHD_SMMU1_ECC_BYPASS_READ_T; + +typedef struct dpp_se_kschd_ass_ecc_bypass_read_t +{ + ZXIC_UINT32 ass_ecc_bypass_read; +}DPP_SE_KSCHD_ASS_ECC_BYPASS_READ_T; + +typedef struct dpp_se_kschd_sdt_h_t +{ + ZXIC_UINT32 sdt_h; +}DPP_SE_KSCHD_SDT_H_T; + +typedef struct dpp_se_kschd_sdt_l_t +{ + ZXIC_UINT32 sdt_l; +}DPP_SE_KSCHD_SDT_L_T; + +typedef struct dpp_se_kschd_hash_key15_t +{ + ZXIC_UINT32 dma_en; + ZXIC_UINT32 delete_en; + ZXIC_UINT32 hash_key15; +}DPP_SE_KSCHD_HASH_KEY15_T; + +typedef struct dpp_se_kschd_hash_key14_t +{ + ZXIC_UINT32 hash_key14; +}DPP_SE_KSCHD_HASH_KEY14_T; + +typedef struct dpp_se_kschd_hash_key13_t +{ + ZXIC_UINT32 hash_key13; +}DPP_SE_KSCHD_HASH_KEY13_T; + +typedef struct dpp_se_kschd_hash_key12_t +{ + ZXIC_UINT32 hash_key12; +}DPP_SE_KSCHD_HASH_KEY12_T; + +typedef struct dpp_se_kschd_hash_key11_t +{ + ZXIC_UINT32 hash_key11; +}DPP_SE_KSCHD_HASH_KEY11_T; + +typedef struct dpp_se_kschd_hash_key10_t +{ + ZXIC_UINT32 hash_key10; +}DPP_SE_KSCHD_HASH_KEY10_T; + +typedef struct dpp_se_kschd_hash_key9_t +{ + ZXIC_UINT32 hash_key9; +}DPP_SE_KSCHD_HASH_KEY9_T; + +typedef struct dpp_se_kschd_hash_key8_t +{ + ZXIC_UINT32 hash_key8; +}DPP_SE_KSCHD_HASH_KEY8_T; + +typedef struct dpp_se_kschd_hash_key7_t +{ + ZXIC_UINT32 hash_key7; +}DPP_SE_KSCHD_HASH_KEY7_T; + +typedef struct dpp_se_kschd_hash_key6_t +{ + ZXIC_UINT32 hash_key6; +}DPP_SE_KSCHD_HASH_KEY6_T; + +typedef struct dpp_se_kschd_hash_key5_t +{ + ZXIC_UINT32 hash_key5; +}DPP_SE_KSCHD_HASH_KEY5_T; + +typedef struct dpp_se_kschd_hash_key4_t +{ + ZXIC_UINT32 hash_key4; +}DPP_SE_KSCHD_HASH_KEY4_T; + +typedef struct dpp_se_kschd_hash_key3_t +{ + ZXIC_UINT32 hash_key3; +}DPP_SE_KSCHD_HASH_KEY3_T; + +typedef struct dpp_se_kschd_hash_key2_t +{ + ZXIC_UINT32 hash_key2; +}DPP_SE_KSCHD_HASH_KEY2_T; + +typedef struct dpp_se_kschd_hash_key1_t +{ + ZXIC_UINT32 hash_key1; +}DPP_SE_KSCHD_HASH_KEY1_T; + +typedef struct dpp_se_kschd_hash_key0_t +{ + ZXIC_UINT32 hash_key0; +}DPP_SE_KSCHD_HASH_KEY0_T; + +typedef struct dpp_se_kschd_schd_int_0_en_t +{ + ZXIC_UINT32 port0_int_en; +}DPP_SE_KSCHD_SCHD_INT_0_EN_T; + +typedef struct dpp_se_kschd_schd_int_0_mask_t +{ + ZXIC_UINT32 port0_int_mask; +}DPP_SE_KSCHD_SCHD_INT_0_MASK_T; + +typedef struct dpp_se_kschd_schd_int_1_en_t +{ + ZXIC_UINT32 port1_int_en; +}DPP_SE_KSCHD_SCHD_INT_1_EN_T; + +typedef struct dpp_se_kschd_schd_int_1_mask_t +{ + ZXIC_UINT32 port1_int_mask; +}DPP_SE_KSCHD_SCHD_INT_1_MASK_T; + +typedef struct dpp_se_kschd_schd_int_2_en_t +{ + ZXIC_UINT32 port2_int_en; +}DPP_SE_KSCHD_SCHD_INT_2_EN_T; + +typedef struct dpp_se_kschd_schd_int_2_mask_t +{ + ZXIC_UINT32 port2_int_mask; +}DPP_SE_KSCHD_SCHD_INT_2_MASK_T; + +typedef struct dpp_se_kschd_schd_int_3_en_t +{ + ZXIC_UINT32 port3_int_en; +}DPP_SE_KSCHD_SCHD_INT_3_EN_T; + +typedef struct dpp_se_kschd_schd_int_3_mask_t +{ + ZXIC_UINT32 port3_int_mask; +}DPP_SE_KSCHD_SCHD_INT_3_MASK_T; + +typedef struct dpp_se_kschd_schd_int_4_en_t +{ + ZXIC_UINT32 port4_int_en; +}DPP_SE_KSCHD_SCHD_INT_4_EN_T; + +typedef struct dpp_se_kschd_schd_int_4_mask_t +{ + ZXIC_UINT32 port4_int_mask; +}DPP_SE_KSCHD_SCHD_INT_4_MASK_T; + +typedef struct dpp_se_kschd_schd_int_0_status_t +{ + ZXIC_UINT32 port0_int_status; +}DPP_SE_KSCHD_SCHD_INT_0_STATUS_T; + +typedef struct dpp_se_kschd_schd_int_1_status_t +{ + ZXIC_UINT32 port1_int_status; +}DPP_SE_KSCHD_SCHD_INT_1_STATUS_T; + +typedef struct dpp_se_kschd_schd_int_2_status_t +{ + ZXIC_UINT32 port2_int_status; +}DPP_SE_KSCHD_SCHD_INT_2_STATUS_T; + +typedef struct dpp_se_kschd_schd_int_3_status_t +{ + ZXIC_UINT32 port3_int_status; +}DPP_SE_KSCHD_SCHD_INT_3_STATUS_T; + +typedef struct dpp_se_kschd_schd_int_4_status_t +{ + ZXIC_UINT32 port4_int_status; +}DPP_SE_KSCHD_SCHD_INT_4_STATUS_T; + +typedef struct dpp_se_kschd_se_kschd_int_status_t +{ + ZXIC_UINT32 schd_int4_unmask_flag; + ZXIC_UINT32 schd_int3_unmask_flag; + ZXIC_UINT32 schd_int2_unmask_flag; + ZXIC_UINT32 schd_int1_unmask_flag; + ZXIC_UINT32 schd_int0_unmask_flag; +}DPP_SE_KSCHD_SE_KSCHD_INT_STATUS_T; + +typedef struct dpp_se_kschd_debug_cnt_mode_t +{ + ZXIC_UINT32 cnt_rd_mode; + ZXIC_UINT32 cnt_overflow_mode; +}DPP_SE_KSCHD_DEBUG_CNT_MODE_T; + +typedef struct dpp_se_kschd_se_parser_kschd_key0_3_cnt_t +{ + ZXIC_UINT32 se_parser_kschd_key0_3_cnt; +}DPP_SE_KSCHD_SE_PARSER_KSCHD_KEY0_3_CNT_T; + +typedef struct dpp_se_kschd_se_smmu1_key0_3_cnt_t +{ + ZXIC_UINT32 se_smmu1_key0_3_cnt; +}DPP_SE_KSCHD_SE_SMMU1_KEY0_3_CNT_T; + +typedef struct dpp_se_kschd_kschd_as_key0_cnt_t +{ + ZXIC_UINT32 kschd_as_key0_cnt; +}DPP_SE_KSCHD_KSCHD_AS_KEY0_CNT_T; + +typedef struct dpp_se_kschd_kschd_as_key1_cnt_t +{ + ZXIC_UINT32 kschd_as_key1_cnt; +}DPP_SE_KSCHD_KSCHD_AS_KEY1_CNT_T; + +typedef struct dpp_se_kschd_kschd_as_key2_cnt_t +{ + ZXIC_UINT32 kschd_as_key2_cnt; +}DPP_SE_KSCHD_KSCHD_AS_KEY2_CNT_T; + +typedef struct dpp_se_kschd_kschd_as_key3_cnt_t +{ + ZXIC_UINT32 kschd_as_key3_cnt; +}DPP_SE_KSCHD_KSCHD_AS_KEY3_CNT_T; + +typedef struct dpp_se_kschd_kschd_as_key4_cnt_t +{ + ZXIC_UINT32 kschd_as_key4_cnt; +}DPP_SE_KSCHD_KSCHD_AS_KEY4_CNT_T; + +typedef struct dpp_se_kschd_kschd_as_key5_cnt_t +{ + ZXIC_UINT32 kschd_as_key5_cnt; +}DPP_SE_KSCHD_KSCHD_AS_KEY5_CNT_T; + +typedef struct dpp_se_kschd_kschd_as_key6_cnt_t +{ + ZXIC_UINT32 kschd_as_key6_cnt; +}DPP_SE_KSCHD_KSCHD_AS_KEY6_CNT_T; + +typedef struct dpp_se_kschd_kschd_as_key9_cnt_t +{ + ZXIC_UINT32 kschd_as_key9_cnt; +}DPP_SE_KSCHD_KSCHD_AS_KEY9_CNT_T; + +typedef struct dpp_se_kschd_kschd_se_parser_fc0_3_cnt_t +{ + ZXIC_UINT32 kschd_se_parser_fc0_3_cnt; +}DPP_SE_KSCHD_KSCHD_SE_PARSER_FC0_3_CNT_T; + +typedef struct dpp_se_kschd_smmu1_se_fc0_3_cnt_t +{ + ZXIC_UINT32 smmu1_se_fc0_3_cnt; +}DPP_SE_KSCHD_SMMU1_SE_FC0_3_CNT_T; + +typedef struct dpp_se_kschd_as_kschd_fc_cnt0_t +{ + ZXIC_UINT32 as_kschd_fc_cnt0; +}DPP_SE_KSCHD_AS_KSCHD_FC_CNT0_T; + +typedef struct dpp_se_kschd_as_kschd_fc_cnt1_t +{ + ZXIC_UINT32 as_kschd_fc_cnt1; +}DPP_SE_KSCHD_AS_KSCHD_FC_CNT1_T; + +typedef struct dpp_se_kschd_as_kschd_fc_cnt2_t +{ + ZXIC_UINT32 as_kschd_fc_cnt2; +}DPP_SE_KSCHD_AS_KSCHD_FC_CNT2_T; + +typedef struct dpp_se_kschd_as_kschd_fc_cnt3_t +{ + ZXIC_UINT32 as_kschd_fc_cnt3; +}DPP_SE_KSCHD_AS_KSCHD_FC_CNT3_T; + +typedef struct dpp_se_kschd_as_kschd_fc_cnt4_t +{ + ZXIC_UINT32 as_kschd_fc_cnt4; +}DPP_SE_KSCHD_AS_KSCHD_FC_CNT4_T; + +typedef struct dpp_se_kschd_as_kschd_fc_cnt5_t +{ + ZXIC_UINT32 as_kschd_fc_cnt5; +}DPP_SE_KSCHD_AS_KSCHD_FC_CNT5_T; + +typedef struct dpp_se_kschd_as_kschd_fc_cnt6_t +{ + ZXIC_UINT32 as_kschd_fc_cnt6; +}DPP_SE_KSCHD_AS_KSCHD_FC_CNT6_T; + +typedef struct dpp_se_kschd_as_kschd_fc_cnt9_t +{ + ZXIC_UINT32 as_kschd_fc_cnt9; +}DPP_SE_KSCHD_AS_KSCHD_FC_CNT9_T; + +typedef struct dpp_se_rschd_rschd_hash_pful_cfg_t +{ + ZXIC_UINT32 rschd_hash_pful_cfg; +}DPP_SE_RSCHD_RSCHD_HASH_PFUL_CFG_T; + +typedef struct dpp_se_rschd_rschd_hash_ept_cfg_t +{ + ZXIC_UINT32 rschd_hash_ept_cfg; +}DPP_SE_RSCHD_RSCHD_HASH_EPT_CFG_T; + +typedef struct dpp_se_rschd_rschd_pbu_pful_cfg_t +{ + ZXIC_UINT32 rschd_pbu_pful_cfg; +}DPP_SE_RSCHD_RSCHD_PBU_PFUL_CFG_T; + +typedef struct dpp_se_rschd_rschd_pbu_ept_cfg_t +{ + ZXIC_UINT32 rschd_pbu_ept_cfg; +}DPP_SE_RSCHD_RSCHD_PBU_EPT_CFG_T; + +typedef struct dpp_se_rschd_rschd_lpm_pful_cfg_t +{ + ZXIC_UINT32 rschd_lpm_pful_cfg; +}DPP_SE_RSCHD_RSCHD_LPM_PFUL_CFG_T; + +typedef struct dpp_se_rschd_rschd_lpm_ept_cfg_t +{ + ZXIC_UINT32 rschd_lpm_ept_cfg; +}DPP_SE_RSCHD_RSCHD_LPM_EPT_CFG_T; + +typedef struct dpp_se_rschd_rschd_etcam_pful_cfg_t +{ + ZXIC_UINT32 rschd_etcam_pful_cfg; +}DPP_SE_RSCHD_RSCHD_ETCAM_PFUL_CFG_T; + +typedef struct dpp_se_rschd_rschd_etcam_ept_cfg_t +{ + ZXIC_UINT32 rschd_etcam_ept_cfg; +}DPP_SE_RSCHD_RSCHD_ETCAM_EPT_CFG_T; + +typedef struct dpp_se_rschd_smmu0_wb_pful_cfg_t +{ + ZXIC_UINT32 smmu0_wb_pful_cfg; +}DPP_SE_RSCHD_SMMU0_WB_PFUL_CFG_T; + +typedef struct dpp_se_rschd_smmu0_wb_ept_cfg_t +{ + ZXIC_UINT32 smmu0_wb_ept_cfg; +}DPP_SE_RSCHD_SMMU0_WB_EPT_CFG_T; + +typedef struct dpp_se_rschd_smmu1_wb_pful_cfg_t +{ + ZXIC_UINT32 smmu1_wb_pful_cfg; +}DPP_SE_RSCHD_SMMU1_WB_PFUL_CFG_T; + +typedef struct dpp_se_rschd_smmu1_wb_ept_cfg_t +{ + ZXIC_UINT32 smmu1_wb_ept_cfg; +}DPP_SE_RSCHD_SMMU1_WB_EPT_CFG_T; + +typedef struct dpp_se_rschd_alg_wb_pful_cfg_t +{ + ZXIC_UINT32 alg_wb_pful_cfg; +}DPP_SE_RSCHD_ALG_WB_PFUL_CFG_T; + +typedef struct dpp_se_rschd_alg_wb_ept_cfg_t +{ + ZXIC_UINT32 alg_wb_ept_cfg; +}DPP_SE_RSCHD_ALG_WB_EPT_CFG_T; + +typedef struct dpp_se_rschd_wr_rsp_vld_en_t +{ + ZXIC_UINT32 wr_rsp_vld_en; +}DPP_SE_RSCHD_WR_RSP_VLD_EN_T; + +typedef struct dpp_se_rschd_nppu_wb_pful_cfg_t +{ + ZXIC_UINT32 nppu_wb_pful_cfg; +}DPP_SE_RSCHD_NPPU_WB_PFUL_CFG_T; + +typedef struct dpp_se_rschd_nppu_wb_ept_cfg_t +{ + ZXIC_UINT32 nppu_wb_ept_cfg; +}DPP_SE_RSCHD_NPPU_WB_EPT_CFG_T; + +typedef struct dpp_se_rschd_port0_int_en_t +{ + ZXIC_UINT32 port0_int_en; +}DPP_SE_RSCHD_PORT0_INT_EN_T; + +typedef struct dpp_se_rschd_port0_int_mask_t +{ + ZXIC_UINT32 port0_int_mask; +}DPP_SE_RSCHD_PORT0_INT_MASK_T; + +typedef struct dpp_se_rschd_port1_int_en_t +{ + ZXIC_UINT32 port1_int_en; +}DPP_SE_RSCHD_PORT1_INT_EN_T; + +typedef struct dpp_se_rschd_port1_int_mask_t +{ + ZXIC_UINT32 port1_int_mask; +}DPP_SE_RSCHD_PORT1_INT_MASK_T; + +typedef struct dpp_se_rschd_port0_int_status_t +{ + ZXIC_UINT32 port0_int_status; +}DPP_SE_RSCHD_PORT0_INT_STATUS_T; + +typedef struct dpp_se_rschd_port1_int_status_t +{ + ZXIC_UINT32 port1_int_status; +}DPP_SE_RSCHD_PORT1_INT_STATUS_T; + +typedef struct dpp_se_rschd_se_rschd_int_status_t +{ + ZXIC_UINT32 port1_int_unmask_flag; + ZXIC_UINT32 port0_int_unmask_flag; +}DPP_SE_RSCHD_SE_RSCHD_INT_STATUS_T; + +typedef struct dpp_se_rschd_debug_cnt_mode_t +{ + ZXIC_UINT32 cnt_rd_mode; + ZXIC_UINT32 cnt_overflow_mode; +}DPP_SE_RSCHD_DEBUG_CNT_MODE_T; + +typedef struct dpp_se_rschd_se_ppu_mex0_5_rsp1_cnt_t +{ + ZXIC_UINT32 se_ppu_mex0_5_rsp1_cnt; +}DPP_SE_RSCHD_SE_PPU_MEX0_5_RSP1_CNT_T; + +typedef struct dpp_se_rschd_as_rschd_rsp0_cnt_t +{ + ZXIC_UINT32 as_rschd_rsp0_cnt; +}DPP_SE_RSCHD_AS_RSCHD_RSP0_CNT_T; + +typedef struct dpp_se_rschd_as_rschd_rsp1_cnt_t +{ + ZXIC_UINT32 as_rschd_rsp1_cnt; +}DPP_SE_RSCHD_AS_RSCHD_RSP1_CNT_T; + +typedef struct dpp_se_rschd_as_rschd_rsp2_cnt_t +{ + ZXIC_UINT32 as_rschd_rsp2_cnt; +}DPP_SE_RSCHD_AS_RSCHD_RSP2_CNT_T; + +typedef struct dpp_se_rschd_as_rschd_rsp3_cnt_t +{ + ZXIC_UINT32 as_rschd_rsp3_cnt; +}DPP_SE_RSCHD_AS_RSCHD_RSP3_CNT_T; + +typedef struct dpp_se_rschd_as_rschd_rsp4_cnt_t +{ + ZXIC_UINT32 as_rschd_rsp4_cnt; +}DPP_SE_RSCHD_AS_RSCHD_RSP4_CNT_T; + +typedef struct dpp_se_rschd_as_rschd_rsp5_cnt_t +{ + ZXIC_UINT32 as_rschd_rsp5_cnt; +}DPP_SE_RSCHD_AS_RSCHD_RSP5_CNT_T; + +typedef struct dpp_se_rschd_as_rschd_rsp6_cnt_t +{ + ZXIC_UINT32 as_rschd_rsp6_cnt; +}DPP_SE_RSCHD_AS_RSCHD_RSP6_CNT_T; + +typedef struct dpp_se_rschd_as_rschd_rsp9_cnt_t +{ + ZXIC_UINT32 as_rschd_rsp9_cnt; +}DPP_SE_RSCHD_AS_RSCHD_RSP9_CNT_T; + +typedef struct dpp_se_rschd_smmu1_se_rsp0_3_cnt_t +{ + ZXIC_UINT32 smmu1_se_rsp0_3_cnt; +}DPP_SE_RSCHD_SMMU1_SE_RSP0_3_CNT_T; + +typedef struct dpp_se_rschd_ppu_se_mex0_3_fc_cnt_t +{ + ZXIC_UINT32 ppu_se_mex0_3_fc_cnt; +}DPP_SE_RSCHD_PPU_SE_MEX0_3_FC_CNT_T; + +typedef struct dpp_se_rschd_rschd_as_fc_cnt0_t +{ + ZXIC_UINT32 rschd_as_fc_cnt0; +}DPP_SE_RSCHD_RSCHD_AS_FC_CNT0_T; + +typedef struct dpp_se_rschd_rschd_as_fc_cnt1_t +{ + ZXIC_UINT32 rschd_as_fc_cnt1; +}DPP_SE_RSCHD_RSCHD_AS_FC_CNT1_T; + +typedef struct dpp_se_rschd_rschd_as_fc_cnt2_t +{ + ZXIC_UINT32 rschd_as_fc_cnt2; +}DPP_SE_RSCHD_RSCHD_AS_FC_CNT2_T; + +typedef struct dpp_se_rschd_rschd_as_fc_cnt3_t +{ + ZXIC_UINT32 rschd_as_fc_cnt3; +}DPP_SE_RSCHD_RSCHD_AS_FC_CNT3_T; + +typedef struct dpp_se_rschd_rschd_as_fc_cnt4_t +{ + ZXIC_UINT32 rschd_as_fc_cnt4; +}DPP_SE_RSCHD_RSCHD_AS_FC_CNT4_T; + +typedef struct dpp_se_rschd_rschd_as_fc_cnt5_t +{ + ZXIC_UINT32 rschd_as_fc_cnt5; +}DPP_SE_RSCHD_RSCHD_AS_FC_CNT5_T; + +typedef struct dpp_se_rschd_rschd_as_fc_cnt6_t +{ + ZXIC_UINT32 rschd_as_fc_cnt6; +}DPP_SE_RSCHD_RSCHD_AS_FC_CNT6_T; + +typedef struct dpp_se_rschd_rschd_as_fc_cnt9_t +{ + ZXIC_UINT32 rschd_as_fc_cnt9; +}DPP_SE_RSCHD_RSCHD_AS_FC_CNT9_T; + +typedef struct dpp_se_rschd_se_smmu1_fc0_3_cnt_t +{ + ZXIC_UINT32 se_smmu1_fc0_3_cnt; +}DPP_SE_RSCHD_SE_SMMU1_FC0_3_CNT_T; + +typedef struct dpp_se_rschd_smmu0_se_wr_done_cnt_t +{ + ZXIC_UINT32 smmu0_se_wr_done_cnt; +}DPP_SE_RSCHD_SMMU0_SE_WR_DONE_CNT_T; + +typedef struct dpp_se_rschd_se_smmu0_wr_done_fc_cnt_t +{ + ZXIC_UINT32 se_smmu0_wr_done_fc_cnt; +}DPP_SE_RSCHD_SE_SMMU0_WR_DONE_FC_CNT_T; + +typedef struct dpp_se_rschd_smmu1_se_wr_rsp_cnt_t +{ + ZXIC_UINT32 smmu1_se_wr_rsp_cnt; +}DPP_SE_RSCHD_SMMU1_SE_WR_RSP_CNT_T; + +typedef struct dpp_se_rschd_se_smmu1_wr_rsp_fc_cnt_t +{ + ZXIC_UINT32 se_smmu1_wr_rsp_fc_cnt; +}DPP_SE_RSCHD_SE_SMMU1_WR_RSP_FC_CNT_T; + +typedef struct dpp_se_rschd_alg_se_wr_rsp_cnt_t +{ + ZXIC_UINT32 alg_se_wr_rsp_cnt; +}DPP_SE_RSCHD_ALG_SE_WR_RSP_CNT_T; + +typedef struct dpp_se_rschd_se_alg_wr_rsp_fc_cnt_t +{ + ZXIC_UINT32 se_alg_wr_rsp_fc_cnt; +}DPP_SE_RSCHD_SE_ALG_WR_RSP_FC_CNT_T; + + +#ifdef __cplusplus +} +#endif +#endif + diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_smmu0_reg.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_smmu0_reg.h new file mode 100644 index 0000000..08b7a46 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_smmu0_reg.h @@ -0,0 +1,6423 @@ + +#ifndef _DPP_SMMU0_REG_H_ +#define _DPP_SMMU0_REG_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +typedef struct dpp_smmu0_smmu0_init_done_t +{ + ZXIC_UINT32 init_done; +}DPP_SMMU0_SMMU0_INIT_DONE_T; + +typedef struct dpp_smmu0_smmu0_cpu_ind_wdat0_t +{ + ZXIC_UINT32 cpu_ind_wdat0; +}DPP_SMMU0_SMMU0_CPU_IND_WDAT0_T; + +typedef struct dpp_smmu0_smmu0_cpu_ind_wdat1_t +{ + ZXIC_UINT32 cpu_ind_wdat1; +}DPP_SMMU0_SMMU0_CPU_IND_WDAT1_T; + +typedef struct dpp_smmu0_smmu0_cpu_ind_wdat2_t +{ + ZXIC_UINT32 cpu_ind_wdat2; +}DPP_SMMU0_SMMU0_CPU_IND_WDAT2_T; + +typedef struct dpp_smmu0_smmu0_cpu_ind_wdat3_t +{ + ZXIC_UINT32 cpu_ind_wdat3; +}DPP_SMMU0_SMMU0_CPU_IND_WDAT3_T; + +typedef struct dpp_smmu0_smmu0_cpu_ind_cmd_t +{ + ZXIC_UINT32 cpu_ind_rw; + ZXIC_UINT32 cpu_ind_rd_mode; + ZXIC_UINT32 cpu_req_mode; + ZXIC_UINT32 cpu_ind_addr; +}DPP_SMMU0_SMMU0_CPU_IND_CMD_T; + +typedef struct dpp_smmu0_smmu0_cpu_ind_rd_done_t +{ + ZXIC_UINT32 cpu_ind_rd_done; +}DPP_SMMU0_SMMU0_CPU_IND_RD_DONE_T; + +typedef struct dpp_smmu0_smmu0_cpu_ind_rdat0_t +{ + ZXIC_UINT32 cpu_ind_rdat0; +}DPP_SMMU0_SMMU0_CPU_IND_RDAT0_T; + +typedef struct dpp_smmu0_smmu0_cpu_ind_rdat1_t +{ + ZXIC_UINT32 cpu_ind_rdat1; +}DPP_SMMU0_SMMU0_CPU_IND_RDAT1_T; + +typedef struct dpp_smmu0_smmu0_cpu_ind_rdat2_t +{ + ZXIC_UINT32 cpu_ind_rdat2; +}DPP_SMMU0_SMMU0_CPU_IND_RDAT2_T; + +typedef struct dpp_smmu0_smmu0_cpu_ind_rdat3_t +{ + ZXIC_UINT32 cpu_ind_rdat3; +}DPP_SMMU0_SMMU0_CPU_IND_RDAT3_T; + +typedef struct dpp_smmu0_smmu0_cfg_plcr_mono_t +{ + ZXIC_UINT32 cfg_plcr_mono; +}DPP_SMMU0_SMMU0_CFG_PLCR_MONO_T; + +typedef struct dpp_smmu0_smmu0_wr_arb_cpu_rdy_t +{ + ZXIC_UINT32 wr_arb_cpu_rdy; +}DPP_SMMU0_SMMU0_WR_ARB_CPU_RDY_T; + +typedef struct dpp_smmu0_smmu0_tm_stat_en_cfg_t +{ + ZXIC_UINT32 tm_stat_en_cfg; +}DPP_SMMU0_SMMU0_TM_STAT_EN_CFG_T; + +typedef struct dpp_smmu0_smmu0_kschd_pful_cfg0_t +{ + ZXIC_UINT32 kschd_pful_assert0_1; + ZXIC_UINT32 kschd_pful_negate0_1; + ZXIC_UINT32 kschd_pful_assert0_0; + ZXIC_UINT32 kschd_pful_negate0_0; +}DPP_SMMU0_SMMU0_KSCHD_PFUL_CFG0_T; + +typedef struct dpp_smmu0_smmu0_kschd_pful_cfg1_t +{ + ZXIC_UINT32 kschd_pful_assert1_1; + ZXIC_UINT32 kschd_pful_negate1_1; + ZXIC_UINT32 kschd_pful_assert1_0; + ZXIC_UINT32 kschd_pful_negate1_0; +}DPP_SMMU0_SMMU0_KSCHD_PFUL_CFG1_T; + +typedef struct dpp_smmu0_smmu0_ctrl_pful1_cfg_t +{ + ZXIC_UINT32 ctrl_pful1_assert; + ZXIC_UINT32 ctrl_pful1_negate; +}DPP_SMMU0_SMMU0_CTRL_PFUL1_CFG_T; + +typedef struct dpp_smmu0_smmu0_ctrl_pful2_cfg_t +{ + ZXIC_UINT32 ctrl_pful2_assert; + ZXIC_UINT32 ctrl_pful2_negate; +}DPP_SMMU0_SMMU0_CTRL_PFUL2_CFG_T; + +typedef struct dpp_smmu0_smmu0_ctrl_pful3_cfg_t +{ + ZXIC_UINT32 ctrl_pful3_assert; + ZXIC_UINT32 ctrl_pful3_negate; +}DPP_SMMU0_SMMU0_CTRL_PFUL3_CFG_T; + +typedef struct dpp_smmu0_smmu0_rschd_pful_cfg_t +{ + ZXIC_UINT32 rschd_pful_assert; + ZXIC_UINT32 rschd_pful_negate; +}DPP_SMMU0_SMMU0_RSCHD_PFUL_CFG_T; + +typedef struct dpp_smmu0_smmu0_rschd_ept_cfg_t +{ + ZXIC_UINT32 rschd_ept_assert; + ZXIC_UINT32 rschd_ept_negate; +}DPP_SMMU0_SMMU0_RSCHD_EPT_CFG_T; + +typedef struct dpp_smmu0_smmu0_alucmd_pful_cfg_t +{ + ZXIC_UINT32 alucmd_pful_assert; + ZXIC_UINT32 alucmd_pful_negate; +}DPP_SMMU0_SMMU0_ALUCMD_PFUL_CFG_T; + +typedef struct dpp_smmu0_smmu0_aluwr_pful_cfg_t +{ + ZXIC_UINT32 aluwr_pful_assert; + ZXIC_UINT32 aluwr_pful_negate; +}DPP_SMMU0_SMMU0_ALUWR_PFUL_CFG_T; + +typedef struct dpp_smmu0_smmu0_wr_arb_pful_cfg0_t +{ + ZXIC_UINT32 wr_arb_pful0_assert; + ZXIC_UINT32 wr_arb_pful0_negate; +}DPP_SMMU0_SMMU0_WR_ARB_PFUL_CFG0_T; + +typedef struct dpp_smmu0_smmu0_wr_arb_pful_cfg1_t +{ + ZXIC_UINT32 wr_arb_pful1_assert; + ZXIC_UINT32 wr_arb_pful1_negate; +}DPP_SMMU0_SMMU0_WR_ARB_PFUL_CFG1_T; + +typedef struct dpp_smmu0_smmu0_ord_pful_cfg_t +{ + ZXIC_UINT32 ord_pful_assert; + ZXIC_UINT32 ord_pful_negate; +}DPP_SMMU0_SMMU0_ORD_PFUL_CFG_T; + +typedef struct dpp_smmu0_smmu0_cfg_dma_baddr_t +{ + ZXIC_UINT32 cfg_dma_baddr; +}DPP_SMMU0_SMMU0_CFG_DMA_BADDR_T; + +typedef struct dpp_smmu0_smmu0_cfg_odma0_baddr_t +{ + ZXIC_UINT32 cfg_odma0_baddr; +}DPP_SMMU0_SMMU0_CFG_ODMA0_BADDR_T; + +typedef struct dpp_smmu0_smmu0_cfg_odma1_baddr_t +{ + ZXIC_UINT32 cfg_odma1_baddr; +}DPP_SMMU0_SMMU0_CFG_ODMA1_BADDR_T; + +typedef struct dpp_smmu0_smmu0_cfg_odma2_baddr_t +{ + ZXIC_UINT32 cfg_odma2_baddr; +}DPP_SMMU0_SMMU0_CFG_ODMA2_BADDR_T; + +typedef struct dpp_smmu0_smmu0_cfg_odma_tdm_baddr_t +{ + ZXIC_UINT32 cfg_odma_tdm_baddr; +}DPP_SMMU0_SMMU0_CFG_ODMA_TDM_BADDR_T; + +typedef struct dpp_smmu0_smmu0_cfg_mcast_baddr_t +{ + ZXIC_UINT32 cfg_mcast_baddr; +}DPP_SMMU0_SMMU0_CFG_MCAST_BADDR_T; + +typedef struct dpp_smmu0_smmu0_cfg_lpm0_t +{ + ZXIC_UINT32 lpm0_rsp_mode; + ZXIC_UINT32 lpm0_baddr; +}DPP_SMMU0_SMMU0_CFG_LPM0_T; + +typedef struct dpp_smmu0_smmu0_cfg_lpm1_t +{ + ZXIC_UINT32 lpm1_rsp_mode; + ZXIC_UINT32 lpm1_baddr; +}DPP_SMMU0_SMMU0_CFG_LPM1_T; + +typedef struct dpp_smmu0_smmu0_cfg_lpm2_t +{ + ZXIC_UINT32 lpm2_rsp_mode; + ZXIC_UINT32 lpm2_baddr; +}DPP_SMMU0_SMMU0_CFG_LPM2_T; + +typedef struct dpp_smmu0_smmu0_cfg_lpm3_t +{ + ZXIC_UINT32 lpm3_rsp_mode; + ZXIC_UINT32 lpm3_baddr; +}DPP_SMMU0_SMMU0_CFG_LPM3_T; + +typedef struct dpp_smmu0_smmu0_cfg_lpm4_t +{ + ZXIC_UINT32 lpm4_rsp_mode; + ZXIC_UINT32 lpm4_baddr; +}DPP_SMMU0_SMMU0_CFG_LPM4_T; + +typedef struct dpp_smmu0_smmu0_cfg_lpm5_t +{ + ZXIC_UINT32 lpm5_rsp_mode; + ZXIC_UINT32 lpm5_baddr; +}DPP_SMMU0_SMMU0_CFG_LPM5_T; + +typedef struct dpp_smmu0_smmu0_cfg_lpm6_t +{ + ZXIC_UINT32 lpm6_rsp_mode; + ZXIC_UINT32 lpm6_baddr; +}DPP_SMMU0_SMMU0_CFG_LPM6_T; + +typedef struct dpp_smmu0_smmu0_cfg_lpm7_t +{ + ZXIC_UINT32 lpm7_rsp_mode; + ZXIC_UINT32 lpm7_baddr; +}DPP_SMMU0_SMMU0_CFG_LPM7_T; + +typedef struct dpp_smmu0_smmu0_debug_cnt_mode_t +{ + ZXIC_UINT32 cnt_rd_mode; + ZXIC_UINT32 cnt_overflow_mode; +}DPP_SMMU0_SMMU0_DEBUG_CNT_MODE_T; + +typedef struct dpp_smmu0_smmu0_stat_overflow_mode_t +{ + ZXIC_UINT32 stat_overflow_mode; +}DPP_SMMU0_SMMU0_STAT_OVERFLOW_MODE_T; + +typedef struct dpp_smmu0_smmu0_init_en_cfg_tmp_t +{ + ZXIC_UINT32 init_en_cfg_tmp31; + ZXIC_UINT32 init_en_cfg_tmp30; + ZXIC_UINT32 init_en_cfg_tmp29; + ZXIC_UINT32 init_en_cfg_tmp28; + ZXIC_UINT32 init_en_cfg_tmp27; + ZXIC_UINT32 init_en_cfg_tmp26; + ZXIC_UINT32 init_en_cfg_tmp25; + ZXIC_UINT32 init_en_cfg_tmp24; + ZXIC_UINT32 init_en_cfg_tmp23; + ZXIC_UINT32 init_en_cfg_tmp22; + ZXIC_UINT32 init_en_cfg_tmp21; + ZXIC_UINT32 init_en_cfg_tmp20; + ZXIC_UINT32 init_en_cfg_tmp19; + ZXIC_UINT32 init_en_cfg_tmp18; + ZXIC_UINT32 init_en_cfg_tmp17; + ZXIC_UINT32 init_en_cfg_tmp16; + ZXIC_UINT32 init_en_cfg_tmp15; + ZXIC_UINT32 init_en_cfg_tmp14; + ZXIC_UINT32 init_en_cfg_tmp13; + ZXIC_UINT32 init_en_cfg_tmp12; + ZXIC_UINT32 init_en_cfg_tmp11; + ZXIC_UINT32 init_en_cfg_tmp10; + ZXIC_UINT32 init_en_cfg_tmp9; + ZXIC_UINT32 init_en_cfg_tmp8; + ZXIC_UINT32 init_en_cfg_tmp7; + ZXIC_UINT32 init_en_cfg_tmp6; + ZXIC_UINT32 init_en_cfg_tmp5; + ZXIC_UINT32 init_en_cfg_tmp4; + ZXIC_UINT32 init_en_cfg_tmp3; + ZXIC_UINT32 init_en_cfg_tmp2; + ZXIC_UINT32 init_en_cfg_tmp1; + ZXIC_UINT32 init_en_cfg_tmp0; +}DPP_SMMU0_SMMU0_INIT_EN_CFG_TMP_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int_unmask_flag_t +{ + ZXIC_UINT32 smmu0_int0_31_unmask_flag; +}DPP_SMMU0_SMMU0_SMMU0_INT_UNMASK_FLAG_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int0_en_t +{ + ZXIC_UINT32 smmu0_int0_en31; + ZXIC_UINT32 smmu0_int0_en30; + ZXIC_UINT32 smmu0_int0_en29; + ZXIC_UINT32 smmu0_int0_en28; + ZXIC_UINT32 smmu0_int0_en27; + ZXIC_UINT32 smmu0_int0_en26; + ZXIC_UINT32 smmu0_int0_en25; + ZXIC_UINT32 smmu0_int0_en24; + ZXIC_UINT32 smmu0_int0_en23; + ZXIC_UINT32 smmu0_int0_en22; + ZXIC_UINT32 smmu0_int0_en21; + ZXIC_UINT32 smmu0_int0_en20; + ZXIC_UINT32 smmu0_int0_en19; + ZXIC_UINT32 smmu0_int0_en18; + ZXIC_UINT32 smmu0_int0_en17; + ZXIC_UINT32 smmu0_int0_en16; + ZXIC_UINT32 smmu0_int0_en15; + ZXIC_UINT32 smmu0_int0_en14; + ZXIC_UINT32 smmu0_int0_en13; + ZXIC_UINT32 smmu0_int0_en12; + ZXIC_UINT32 smmu0_int0_en11; + ZXIC_UINT32 smmu0_int0_en10; + ZXIC_UINT32 smmu0_int0_en9; + ZXIC_UINT32 smmu0_int0_en8; + ZXIC_UINT32 smmu0_int0_en7; + ZXIC_UINT32 smmu0_int0_en6; + ZXIC_UINT32 smmu0_int0_en5; + ZXIC_UINT32 smmu0_int0_en4; + ZXIC_UINT32 smmu0_int0_en3; + ZXIC_UINT32 smmu0_int0_en2; + ZXIC_UINT32 smmu0_int0_en1; + ZXIC_UINT32 smmu0_int0_en0; +}DPP_SMMU0_SMMU0_SMMU0_INT0_EN_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int0_mask_t +{ + ZXIC_UINT32 smmu0_int0_mask31; + ZXIC_UINT32 smmu0_int0_mask30; + ZXIC_UINT32 smmu0_int0_mask29; + ZXIC_UINT32 smmu0_int0_mask28; + ZXIC_UINT32 smmu0_int0_mask27; + ZXIC_UINT32 smmu0_int0_mask26; + ZXIC_UINT32 smmu0_int0_mask25; + ZXIC_UINT32 smmu0_int0_mask24; + ZXIC_UINT32 smmu0_int0_mask23; + ZXIC_UINT32 smmu0_int0_mask22; + ZXIC_UINT32 smmu0_int0_mask21; + ZXIC_UINT32 smmu0_int0_mask20; + ZXIC_UINT32 smmu0_int0_mask19; + ZXIC_UINT32 smmu0_int0_mask18; + ZXIC_UINT32 smmu0_int0_mask17; + ZXIC_UINT32 smmu0_int0_mask16; + ZXIC_UINT32 smmu0_int0_mask15; + ZXIC_UINT32 smmu0_int0_mask14; + ZXIC_UINT32 smmu0_int0_mask13; + ZXIC_UINT32 smmu0_int0_mask12; + ZXIC_UINT32 smmu0_int0_mask11; + ZXIC_UINT32 smmu0_int0_mask10; + ZXIC_UINT32 smmu0_int0_mask9; + ZXIC_UINT32 smmu0_int0_mask8; + ZXIC_UINT32 smmu0_int0_mask7; + ZXIC_UINT32 smmu0_int0_mask6; + ZXIC_UINT32 smmu0_int0_mask5; + ZXIC_UINT32 smmu0_int0_mask4; + ZXIC_UINT32 smmu0_int0_mask3; + ZXIC_UINT32 smmu0_int0_mask2; + ZXIC_UINT32 smmu0_int0_mask1; + ZXIC_UINT32 smmu0_int0_mask0; +}DPP_SMMU0_SMMU0_SMMU0_INT0_MASK_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int0_status_t +{ + ZXIC_UINT32 smmu0_int0_status31; + ZXIC_UINT32 smmu0_int0_status30; + ZXIC_UINT32 smmu0_int0_status29; + ZXIC_UINT32 smmu0_int0_status28; + ZXIC_UINT32 smmu0_int0_status27; + ZXIC_UINT32 smmu0_int0_status26; + ZXIC_UINT32 smmu0_int0_status25; + ZXIC_UINT32 smmu0_int0_status24; + ZXIC_UINT32 smmu0_int0_status23; + ZXIC_UINT32 smmu0_int0_status22; + ZXIC_UINT32 smmu0_int0_status21; + ZXIC_UINT32 smmu0_int0_status20; + ZXIC_UINT32 smmu0_int0_status19; + ZXIC_UINT32 smmu0_int0_status18; + ZXIC_UINT32 smmu0_int0_status17; + ZXIC_UINT32 smmu0_int0_status16; + ZXIC_UINT32 smmu0_int0_status15; + ZXIC_UINT32 smmu0_int0_status14; + ZXIC_UINT32 smmu0_int0_status13; + ZXIC_UINT32 smmu0_int0_status12; + ZXIC_UINT32 smmu0_int0_status11; + ZXIC_UINT32 smmu0_int0_status10; + ZXIC_UINT32 smmu0_int0_status9; + ZXIC_UINT32 smmu0_int0_status8; + ZXIC_UINT32 smmu0_int0_status7; + ZXIC_UINT32 smmu0_int0_status6; + ZXIC_UINT32 smmu0_int0_status5; + ZXIC_UINT32 smmu0_int0_status4; + ZXIC_UINT32 smmu0_int0_status3; + ZXIC_UINT32 smmu0_int0_status2; + ZXIC_UINT32 smmu0_int0_status1; + ZXIC_UINT32 smmu0_int0_status0; +}DPP_SMMU0_SMMU0_SMMU0_INT0_STATUS_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int1_en_t +{ + ZXIC_UINT32 smmu0_int1_en31; + ZXIC_UINT32 smmu0_int1_en30; + ZXIC_UINT32 smmu0_int1_en29; + ZXIC_UINT32 smmu0_int1_en28; + ZXIC_UINT32 smmu0_int1_en27; + ZXIC_UINT32 smmu0_int1_en26; + ZXIC_UINT32 smmu0_int1_en25; + ZXIC_UINT32 smmu0_int1_en24; + ZXIC_UINT32 smmu0_int1_en23; + ZXIC_UINT32 smmu0_int1_en22; + ZXIC_UINT32 smmu0_int1_en21; + ZXIC_UINT32 smmu0_int1_en20; + ZXIC_UINT32 smmu0_int1_en19; + ZXIC_UINT32 smmu0_int1_en18; + ZXIC_UINT32 smmu0_int1_en17; + ZXIC_UINT32 smmu0_int1_en16; + ZXIC_UINT32 smmu0_int1_en15; + ZXIC_UINT32 smmu0_int1_en14; + ZXIC_UINT32 smmu0_int1_en13; + ZXIC_UINT32 smmu0_int1_en12; + ZXIC_UINT32 smmu0_int1_en11; + ZXIC_UINT32 smmu0_int1_en10; + ZXIC_UINT32 smmu0_int1_en9; + ZXIC_UINT32 smmu0_int1_en8; + ZXIC_UINT32 smmu0_int1_en7; + ZXIC_UINT32 smmu0_int1_en6; + ZXIC_UINT32 smmu0_int1_en5; + ZXIC_UINT32 smmu0_int1_en4; + ZXIC_UINT32 smmu0_int1_en3; + ZXIC_UINT32 smmu0_int1_en2; + ZXIC_UINT32 smmu0_int1_en1; + ZXIC_UINT32 smmu0_int1_en0; +}DPP_SMMU0_SMMU0_SMMU0_INT1_EN_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int1_mask_t +{ + ZXIC_UINT32 smmu0_int1_mask31; + ZXIC_UINT32 smmu0_int1_mask30; + ZXIC_UINT32 smmu0_int1_mask29; + ZXIC_UINT32 smmu0_int1_mask28; + ZXIC_UINT32 smmu0_int1_mask27; + ZXIC_UINT32 smmu0_int1_mask26; + ZXIC_UINT32 smmu0_int1_mask25; + ZXIC_UINT32 smmu0_int1_mask24; + ZXIC_UINT32 smmu0_int1_mask23; + ZXIC_UINT32 smmu0_int1_mask22; + ZXIC_UINT32 smmu0_int1_mask21; + ZXIC_UINT32 smmu0_int1_mask20; + ZXIC_UINT32 smmu0_int1_mask19; + ZXIC_UINT32 smmu0_int1_mask18; + ZXIC_UINT32 smmu0_int1_mask17; + ZXIC_UINT32 smmu0_int1_mask16; + ZXIC_UINT32 smmu0_int1_mask15; + ZXIC_UINT32 smmu0_int1_mask14; + ZXIC_UINT32 smmu0_int1_mask13; + ZXIC_UINT32 smmu0_int1_mask12; + ZXIC_UINT32 smmu0_int1_mask11; + ZXIC_UINT32 smmu0_int1_mask10; + ZXIC_UINT32 smmu0_int1_mask9; + ZXIC_UINT32 smmu0_int1_mask8; + ZXIC_UINT32 smmu0_int1_mask7; + ZXIC_UINT32 smmu0_int1_mask6; + ZXIC_UINT32 smmu0_int1_mask5; + ZXIC_UINT32 smmu0_int1_mask4; + ZXIC_UINT32 smmu0_int1_mask3; + ZXIC_UINT32 smmu0_int1_mask2; + ZXIC_UINT32 smmu0_int1_mask1; + ZXIC_UINT32 smmu0_int1_mask0; +}DPP_SMMU0_SMMU0_SMMU0_INT1_MASK_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int1_status_t +{ + ZXIC_UINT32 smmu0_int1_status31; + ZXIC_UINT32 smmu0_int1_status30; + ZXIC_UINT32 smmu0_int1_status29; + ZXIC_UINT32 smmu0_int1_status28; + ZXIC_UINT32 smmu0_int1_status27; + ZXIC_UINT32 smmu0_int1_status26; + ZXIC_UINT32 smmu0_int1_status25; + ZXIC_UINT32 smmu0_int1_status24; + ZXIC_UINT32 smmu0_int1_status23; + ZXIC_UINT32 smmu0_int1_status22; + ZXIC_UINT32 smmu0_int1_status21; + ZXIC_UINT32 smmu0_int1_status20; + ZXIC_UINT32 smmu0_int1_status19; + ZXIC_UINT32 smmu0_int1_status18; + ZXIC_UINT32 smmu0_int1_status17; + ZXIC_UINT32 smmu0_int1_status16; + ZXIC_UINT32 smmu0_int1_status15; + ZXIC_UINT32 smmu0_int1_status14; + ZXIC_UINT32 smmu0_int1_status13; + ZXIC_UINT32 smmu0_int1_status12; + ZXIC_UINT32 smmu0_int1_status11; + ZXIC_UINT32 smmu0_int1_status10; + ZXIC_UINT32 smmu0_int1_status9; + ZXIC_UINT32 smmu0_int1_status8; + ZXIC_UINT32 smmu0_int1_status7; + ZXIC_UINT32 smmu0_int1_status6; + ZXIC_UINT32 smmu0_int1_status5; + ZXIC_UINT32 smmu0_int1_status4; + ZXIC_UINT32 smmu0_int1_status3; + ZXIC_UINT32 smmu0_int1_status2; + ZXIC_UINT32 smmu0_int1_status1; + ZXIC_UINT32 smmu0_int1_status0; +}DPP_SMMU0_SMMU0_SMMU0_INT1_STATUS_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int2_en_t +{ + ZXIC_UINT32 smmu0_int2_en31; + ZXIC_UINT32 smmu0_int2_en30; + ZXIC_UINT32 smmu0_int2_en29; + ZXIC_UINT32 smmu0_int2_en28; + ZXIC_UINT32 smmu0_int2_en27; + ZXIC_UINT32 smmu0_int2_en26; + ZXIC_UINT32 smmu0_int2_en25; + ZXIC_UINT32 smmu0_int2_en24; + ZXIC_UINT32 smmu0_int2_en23; + ZXIC_UINT32 smmu0_int2_en22; + ZXIC_UINT32 smmu0_int2_en21; + ZXIC_UINT32 smmu0_int2_en20; + ZXIC_UINT32 smmu0_int2_en19; + ZXIC_UINT32 smmu0_int2_en18; + ZXIC_UINT32 smmu0_int2_en17; + ZXIC_UINT32 smmu0_int2_en16; + ZXIC_UINT32 smmu0_int2_en15; + ZXIC_UINT32 smmu0_int2_en14; + ZXIC_UINT32 smmu0_int2_en13; + ZXIC_UINT32 smmu0_int2_en12; + ZXIC_UINT32 smmu0_int2_en11; + ZXIC_UINT32 smmu0_int2_en10; + ZXIC_UINT32 smmu0_int2_en9; + ZXIC_UINT32 smmu0_int2_en8; + ZXIC_UINT32 smmu0_int2_en7; + ZXIC_UINT32 smmu0_int2_en6; + ZXIC_UINT32 smmu0_int2_en5; + ZXIC_UINT32 smmu0_int2_en4; + ZXIC_UINT32 smmu0_int2_en3; + ZXIC_UINT32 smmu0_int2_en2; + ZXIC_UINT32 smmu0_int2_en1; + ZXIC_UINT32 smmu0_int2_en0; +}DPP_SMMU0_SMMU0_SMMU0_INT2_EN_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int2_mask_t +{ + ZXIC_UINT32 smmu0_int2_mask31; + ZXIC_UINT32 smmu0_int2_mask30; + ZXIC_UINT32 smmu0_int2_mask29; + ZXIC_UINT32 smmu0_int2_mask28; + ZXIC_UINT32 smmu0_int2_mask27; + ZXIC_UINT32 smmu0_int2_mask26; + ZXIC_UINT32 smmu0_int2_mask25; + ZXIC_UINT32 smmu0_int2_mask24; + ZXIC_UINT32 smmu0_int2_mask23; + ZXIC_UINT32 smmu0_int2_mask22; + ZXIC_UINT32 smmu0_int2_mask21; + ZXIC_UINT32 smmu0_int2_mask20; + ZXIC_UINT32 smmu0_int2_mask19; + ZXIC_UINT32 smmu0_int2_mask18; + ZXIC_UINT32 smmu0_int2_mask17; + ZXIC_UINT32 smmu0_int2_mask16; + ZXIC_UINT32 smmu0_int2_mask15; + ZXIC_UINT32 smmu0_int2_mask14; + ZXIC_UINT32 smmu0_int2_mask13; + ZXIC_UINT32 smmu0_int2_mask12; + ZXIC_UINT32 smmu0_int2_mask11; + ZXIC_UINT32 smmu0_int2_mask10; + ZXIC_UINT32 smmu0_int2_mask9; + ZXIC_UINT32 smmu0_int2_mask8; + ZXIC_UINT32 smmu0_int2_mask7; + ZXIC_UINT32 smmu0_int2_mask6; + ZXIC_UINT32 smmu0_int2_mask5; + ZXIC_UINT32 smmu0_int2_mask4; + ZXIC_UINT32 smmu0_int2_mask3; + ZXIC_UINT32 smmu0_int2_mask2; + ZXIC_UINT32 smmu0_int2_mask1; + ZXIC_UINT32 smmu0_int2_mask0; +}DPP_SMMU0_SMMU0_SMMU0_INT2_MASK_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int2_status_t +{ + ZXIC_UINT32 smmu0_int2_status31; + ZXIC_UINT32 smmu0_int2_status30; + ZXIC_UINT32 smmu0_int2_status29; + ZXIC_UINT32 smmu0_int2_status28; + ZXIC_UINT32 smmu0_int2_status27; + ZXIC_UINT32 smmu0_int2_status26; + ZXIC_UINT32 smmu0_int2_status25; + ZXIC_UINT32 smmu0_int2_status24; + ZXIC_UINT32 smmu0_int2_status23; + ZXIC_UINT32 smmu0_int2_status22; + ZXIC_UINT32 smmu0_int2_status21; + ZXIC_UINT32 smmu0_int2_status20; + ZXIC_UINT32 smmu0_int2_status19; + ZXIC_UINT32 smmu0_int2_status18; + ZXIC_UINT32 smmu0_int2_status17; + ZXIC_UINT32 smmu0_int2_status16; + ZXIC_UINT32 smmu0_int2_status15; + ZXIC_UINT32 smmu0_int2_status14; + ZXIC_UINT32 smmu0_int2_status13; + ZXIC_UINT32 smmu0_int2_status12; + ZXIC_UINT32 smmu0_int2_status11; + ZXIC_UINT32 smmu0_int2_status10; + ZXIC_UINT32 smmu0_int2_status9; + ZXIC_UINT32 smmu0_int2_status8; + ZXIC_UINT32 smmu0_int2_status7; + ZXIC_UINT32 smmu0_int2_status6; + ZXIC_UINT32 smmu0_int2_status5; + ZXIC_UINT32 smmu0_int2_status4; + ZXIC_UINT32 smmu0_int2_status3; + ZXIC_UINT32 smmu0_int2_status2; + ZXIC_UINT32 smmu0_int2_status1; + ZXIC_UINT32 smmu0_int2_status0; +}DPP_SMMU0_SMMU0_SMMU0_INT2_STATUS_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int3_en_t +{ + ZXIC_UINT32 smmu0_int3_en31; + ZXIC_UINT32 smmu0_int3_en30; + ZXIC_UINT32 smmu0_int3_en29; + ZXIC_UINT32 smmu0_int3_en28; + ZXIC_UINT32 smmu0_int3_en27; + ZXIC_UINT32 smmu0_int3_en26; + ZXIC_UINT32 smmu0_int3_en25; + ZXIC_UINT32 smmu0_int3_en24; + ZXIC_UINT32 smmu0_int3_en23; + ZXIC_UINT32 smmu0_int3_en22; + ZXIC_UINT32 smmu0_int3_en21; + ZXIC_UINT32 smmu0_int3_en20; + ZXIC_UINT32 smmu0_int3_en19; + ZXIC_UINT32 smmu0_int3_en18; + ZXIC_UINT32 smmu0_int3_en17; + ZXIC_UINT32 smmu0_int3_en16; + ZXIC_UINT32 smmu0_int3_en15; + ZXIC_UINT32 smmu0_int3_en14; + ZXIC_UINT32 smmu0_int3_en13; + ZXIC_UINT32 smmu0_int3_en12; + ZXIC_UINT32 smmu0_int3_en11; + ZXIC_UINT32 smmu0_int3_en10; + ZXIC_UINT32 smmu0_int3_en9; + ZXIC_UINT32 smmu0_int3_en8; + ZXIC_UINT32 smmu0_int3_en7; + ZXIC_UINT32 smmu0_int3_en6; + ZXIC_UINT32 smmu0_int3_en5; + ZXIC_UINT32 smmu0_int3_en4; + ZXIC_UINT32 smmu0_int3_en3; + ZXIC_UINT32 smmu0_int3_en2; + ZXIC_UINT32 smmu0_int3_en1; + ZXIC_UINT32 smmu0_int3_en0; +}DPP_SMMU0_SMMU0_SMMU0_INT3_EN_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int3_mask_t +{ + ZXIC_UINT32 smmu0_int3_mask31; + ZXIC_UINT32 smmu0_int3_mask30; + ZXIC_UINT32 smmu0_int3_mask29; + ZXIC_UINT32 smmu0_int3_mask28; + ZXIC_UINT32 smmu0_int3_mask27; + ZXIC_UINT32 smmu0_int3_mask26; + ZXIC_UINT32 smmu0_int3_mask25; + ZXIC_UINT32 smmu0_int3_mask24; + ZXIC_UINT32 smmu0_int3_mask23; + ZXIC_UINT32 smmu0_int3_mask22; + ZXIC_UINT32 smmu0_int3_mask21; + ZXIC_UINT32 smmu0_int3_mask20; + ZXIC_UINT32 smmu0_int3_mask19; + ZXIC_UINT32 smmu0_int3_mask18; + ZXIC_UINT32 smmu0_int3_mask17; + ZXIC_UINT32 smmu0_int3_mask16; + ZXIC_UINT32 smmu0_int3_mask15; + ZXIC_UINT32 smmu0_int3_mask14; + ZXIC_UINT32 smmu0_int3_mask13; + ZXIC_UINT32 smmu0_int3_mask12; + ZXIC_UINT32 smmu0_int3_mask11; + ZXIC_UINT32 smmu0_int3_mask10; + ZXIC_UINT32 smmu0_int3_mask9; + ZXIC_UINT32 smmu0_int3_mask8; + ZXIC_UINT32 smmu0_int3_mask7; + ZXIC_UINT32 smmu0_int3_mask6; + ZXIC_UINT32 smmu0_int3_mask5; + ZXIC_UINT32 smmu0_int3_mask4; + ZXIC_UINT32 smmu0_int3_mask3; + ZXIC_UINT32 smmu0_int3_mask2; + ZXIC_UINT32 smmu0_int3_mask1; + ZXIC_UINT32 smmu0_int3_mask0; +}DPP_SMMU0_SMMU0_SMMU0_INT3_MASK_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int3_status_t +{ + ZXIC_UINT32 smmu0_int3_status31; + ZXIC_UINT32 smmu0_int3_status30; + ZXIC_UINT32 smmu0_int3_status29; + ZXIC_UINT32 smmu0_int3_status28; + ZXIC_UINT32 smmu0_int3_status27; + ZXIC_UINT32 smmu0_int3_status26; + ZXIC_UINT32 smmu0_int3_status25; + ZXIC_UINT32 smmu0_int3_status24; + ZXIC_UINT32 smmu0_int3_status23; + ZXIC_UINT32 smmu0_int3_status22; + ZXIC_UINT32 smmu0_int3_status21; + ZXIC_UINT32 smmu0_int3_status20; + ZXIC_UINT32 smmu0_int3_status19; + ZXIC_UINT32 smmu0_int3_status18; + ZXIC_UINT32 smmu0_int3_status17; + ZXIC_UINT32 smmu0_int3_status16; + ZXIC_UINT32 smmu0_int3_status15; + ZXIC_UINT32 smmu0_int3_status14; + ZXIC_UINT32 smmu0_int3_status13; + ZXIC_UINT32 smmu0_int3_status12; + ZXIC_UINT32 smmu0_int3_status11; + ZXIC_UINT32 smmu0_int3_status10; + ZXIC_UINT32 smmu0_int3_status9; + ZXIC_UINT32 smmu0_int3_status8; + ZXIC_UINT32 smmu0_int3_status7; + ZXIC_UINT32 smmu0_int3_status6; + ZXIC_UINT32 smmu0_int3_status5; + ZXIC_UINT32 smmu0_int3_status4; + ZXIC_UINT32 smmu0_int3_status3; + ZXIC_UINT32 smmu0_int3_status2; + ZXIC_UINT32 smmu0_int3_status1; + ZXIC_UINT32 smmu0_int3_status0; +}DPP_SMMU0_SMMU0_SMMU0_INT3_STATUS_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int4_en_t +{ + ZXIC_UINT32 smmu0_int4_en31; + ZXIC_UINT32 smmu0_int4_en30; + ZXIC_UINT32 smmu0_int4_en29; + ZXIC_UINT32 smmu0_int4_en28; + ZXIC_UINT32 smmu0_int4_en27; + ZXIC_UINT32 smmu0_int4_en26; + ZXIC_UINT32 smmu0_int4_en25; + ZXIC_UINT32 smmu0_int4_en24; + ZXIC_UINT32 smmu0_int4_en23; + ZXIC_UINT32 smmu0_int4_en22; + ZXIC_UINT32 smmu0_int4_en21; + ZXIC_UINT32 smmu0_int4_en20; + ZXIC_UINT32 smmu0_int4_en19; + ZXIC_UINT32 smmu0_int4_en18; + ZXIC_UINT32 smmu0_int4_en17; + ZXIC_UINT32 smmu0_int4_en16; + ZXIC_UINT32 smmu0_int4_en15; + ZXIC_UINT32 smmu0_int4_en14; + ZXIC_UINT32 smmu0_int4_en13; + ZXIC_UINT32 smmu0_int4_en12; + ZXIC_UINT32 smmu0_int4_en11; + ZXIC_UINT32 smmu0_int4_en10; + ZXIC_UINT32 smmu0_int4_en9; + ZXIC_UINT32 smmu0_int4_en8; + ZXIC_UINT32 smmu0_int4_en7; + ZXIC_UINT32 smmu0_int4_en6; + ZXIC_UINT32 smmu0_int4_en5; + ZXIC_UINT32 smmu0_int4_en4; + ZXIC_UINT32 smmu0_int4_en3; + ZXIC_UINT32 smmu0_int4_en2; + ZXIC_UINT32 smmu0_int4_en1; + ZXIC_UINT32 smmu0_int4_en0; +}DPP_SMMU0_SMMU0_SMMU0_INT4_EN_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int4_mask_t +{ + ZXIC_UINT32 smmu0_int4_mask31; + ZXIC_UINT32 smmu0_int4_mask30; + ZXIC_UINT32 smmu0_int4_mask29; + ZXIC_UINT32 smmu0_int4_mask28; + ZXIC_UINT32 smmu0_int4_mask27; + ZXIC_UINT32 smmu0_int4_mask26; + ZXIC_UINT32 smmu0_int4_mask25; + ZXIC_UINT32 smmu0_int4_mask24; + ZXIC_UINT32 smmu0_int4_mask23; + ZXIC_UINT32 smmu0_int4_mask22; + ZXIC_UINT32 smmu0_int4_mask21; + ZXIC_UINT32 smmu0_int4_mask20; + ZXIC_UINT32 smmu0_int4_mask19; + ZXIC_UINT32 smmu0_int4_mask18; + ZXIC_UINT32 smmu0_int4_mask17; + ZXIC_UINT32 smmu0_int4_mask16; + ZXIC_UINT32 smmu0_int4_mask15; + ZXIC_UINT32 smmu0_int4_mask14; + ZXIC_UINT32 smmu0_int4_mask13; + ZXIC_UINT32 smmu0_int4_mask12; + ZXIC_UINT32 smmu0_int4_mask11; + ZXIC_UINT32 smmu0_int4_mask10; + ZXIC_UINT32 smmu0_int4_mask9; + ZXIC_UINT32 smmu0_int4_mask8; + ZXIC_UINT32 smmu0_int4_mask7; + ZXIC_UINT32 smmu0_int4_mask6; + ZXIC_UINT32 smmu0_int4_mask5; + ZXIC_UINT32 smmu0_int4_mask4; + ZXIC_UINT32 smmu0_int4_mask3; + ZXIC_UINT32 smmu0_int4_mask2; + ZXIC_UINT32 smmu0_int4_mask1; + ZXIC_UINT32 smmu0_int4_mask0; +}DPP_SMMU0_SMMU0_SMMU0_INT4_MASK_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int4_status_t +{ + ZXIC_UINT32 smmu0_int4_status31; + ZXIC_UINT32 smmu0_int4_status30; + ZXIC_UINT32 smmu0_int4_status29; + ZXIC_UINT32 smmu0_int4_status28; + ZXIC_UINT32 smmu0_int4_status27; + ZXIC_UINT32 smmu0_int4_status26; + ZXIC_UINT32 smmu0_int4_status25; + ZXIC_UINT32 smmu0_int4_status24; + ZXIC_UINT32 smmu0_int4_status23; + ZXIC_UINT32 smmu0_int4_status22; + ZXIC_UINT32 smmu0_int4_status21; + ZXIC_UINT32 smmu0_int4_status20; + ZXIC_UINT32 smmu0_int4_status19; + ZXIC_UINT32 smmu0_int4_status18; + ZXIC_UINT32 smmu0_int4_status17; + ZXIC_UINT32 smmu0_int4_status16; + ZXIC_UINT32 smmu0_int4_status15; + ZXIC_UINT32 smmu0_int4_status14; + ZXIC_UINT32 smmu0_int4_status13; + ZXIC_UINT32 smmu0_int4_status12; + ZXIC_UINT32 smmu0_int4_status11; + ZXIC_UINT32 smmu0_int4_status10; + ZXIC_UINT32 smmu0_int4_status9; + ZXIC_UINT32 smmu0_int4_status8; + ZXIC_UINT32 smmu0_int4_status7; + ZXIC_UINT32 smmu0_int4_status6; + ZXIC_UINT32 smmu0_int4_status5; + ZXIC_UINT32 smmu0_int4_status4; + ZXIC_UINT32 smmu0_int4_status3; + ZXIC_UINT32 smmu0_int4_status2; + ZXIC_UINT32 smmu0_int4_status1; + ZXIC_UINT32 smmu0_int4_status0; +}DPP_SMMU0_SMMU0_SMMU0_INT4_STATUS_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int5_en_t +{ + ZXIC_UINT32 smmu0_int5_en31; + ZXIC_UINT32 smmu0_int5_en30; + ZXIC_UINT32 smmu0_int5_en29; + ZXIC_UINT32 smmu0_int5_en28; + ZXIC_UINT32 smmu0_int5_en27; + ZXIC_UINT32 smmu0_int5_en26; + ZXIC_UINT32 smmu0_int5_en25; + ZXIC_UINT32 smmu0_int5_en24; + ZXIC_UINT32 smmu0_int5_en23; + ZXIC_UINT32 smmu0_int5_en22; + ZXIC_UINT32 smmu0_int5_en21; + ZXIC_UINT32 smmu0_int5_en20; + ZXIC_UINT32 smmu0_int5_en19; + ZXIC_UINT32 smmu0_int5_en18; + ZXIC_UINT32 smmu0_int5_en17; + ZXIC_UINT32 smmu0_int5_en16; + ZXIC_UINT32 smmu0_int5_en15; + ZXIC_UINT32 smmu0_int5_en14; + ZXIC_UINT32 smmu0_int5_en13; + ZXIC_UINT32 smmu0_int5_en12; + ZXIC_UINT32 smmu0_int5_en11; + ZXIC_UINT32 smmu0_int5_en10; + ZXIC_UINT32 smmu0_int5_en9; + ZXIC_UINT32 smmu0_int5_en8; + ZXIC_UINT32 smmu0_int5_en7; + ZXIC_UINT32 smmu0_int5_en6; + ZXIC_UINT32 smmu0_int5_en5; + ZXIC_UINT32 smmu0_int5_en4; + ZXIC_UINT32 smmu0_int5_en3; + ZXIC_UINT32 smmu0_int5_en2; + ZXIC_UINT32 smmu0_int5_en1; + ZXIC_UINT32 smmu0_int5_en0; +}DPP_SMMU0_SMMU0_SMMU0_INT5_EN_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int5_mask_t +{ + ZXIC_UINT32 smmu0_int5_mask31; + ZXIC_UINT32 smmu0_int5_mask30; + ZXIC_UINT32 smmu0_int5_mask29; + ZXIC_UINT32 smmu0_int5_mask28; + ZXIC_UINT32 smmu0_int5_mask27; + ZXIC_UINT32 smmu0_int5_mask26; + ZXIC_UINT32 smmu0_int5_mask25; + ZXIC_UINT32 smmu0_int5_mask24; + ZXIC_UINT32 smmu0_int5_mask23; + ZXIC_UINT32 smmu0_int5_mask22; + ZXIC_UINT32 smmu0_int5_mask21; + ZXIC_UINT32 smmu0_int5_mask20; + ZXIC_UINT32 smmu0_int5_mask19; + ZXIC_UINT32 smmu0_int5_mask18; + ZXIC_UINT32 smmu0_int5_mask17; + ZXIC_UINT32 smmu0_int5_mask16; + ZXIC_UINT32 smmu0_int5_mask15; + ZXIC_UINT32 smmu0_int5_mask14; + ZXIC_UINT32 smmu0_int5_mask13; + ZXIC_UINT32 smmu0_int5_mask12; + ZXIC_UINT32 smmu0_int5_mask11; + ZXIC_UINT32 smmu0_int5_mask10; + ZXIC_UINT32 smmu0_int5_mask9; + ZXIC_UINT32 smmu0_int5_mask8; + ZXIC_UINT32 smmu0_int5_mask7; + ZXIC_UINT32 smmu0_int5_mask6; + ZXIC_UINT32 smmu0_int5_mask5; + ZXIC_UINT32 smmu0_int5_mask4; + ZXIC_UINT32 smmu0_int5_mask3; + ZXIC_UINT32 smmu0_int5_mask2; + ZXIC_UINT32 smmu0_int5_mask1; + ZXIC_UINT32 smmu0_int5_mask0; +}DPP_SMMU0_SMMU0_SMMU0_INT5_MASK_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int5_status_t +{ + ZXIC_UINT32 smmu0_int5_status31; + ZXIC_UINT32 smmu0_int5_status30; + ZXIC_UINT32 smmu0_int5_status29; + ZXIC_UINT32 smmu0_int5_status28; + ZXIC_UINT32 smmu0_int5_status27; + ZXIC_UINT32 smmu0_int5_status26; + ZXIC_UINT32 smmu0_int5_status25; + ZXIC_UINT32 smmu0_int5_status24; + ZXIC_UINT32 smmu0_int5_status23; + ZXIC_UINT32 smmu0_int5_status22; + ZXIC_UINT32 smmu0_int5_status21; + ZXIC_UINT32 smmu0_int5_status20; + ZXIC_UINT32 smmu0_int5_status19; + ZXIC_UINT32 smmu0_int5_status18; + ZXIC_UINT32 smmu0_int5_status17; + ZXIC_UINT32 smmu0_int5_status16; + ZXIC_UINT32 smmu0_int5_status15; + ZXIC_UINT32 smmu0_int5_status14; + ZXIC_UINT32 smmu0_int5_status13; + ZXIC_UINT32 smmu0_int5_status12; + ZXIC_UINT32 smmu0_int5_status11; + ZXIC_UINT32 smmu0_int5_status10; + ZXIC_UINT32 smmu0_int5_status9; + ZXIC_UINT32 smmu0_int5_status8; + ZXIC_UINT32 smmu0_int5_status7; + ZXIC_UINT32 smmu0_int5_status6; + ZXIC_UINT32 smmu0_int5_status5; + ZXIC_UINT32 smmu0_int5_status4; + ZXIC_UINT32 smmu0_int5_status3; + ZXIC_UINT32 smmu0_int5_status2; + ZXIC_UINT32 smmu0_int5_status1; + ZXIC_UINT32 smmu0_int5_status0; +}DPP_SMMU0_SMMU0_SMMU0_INT5_STATUS_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int6_en_t +{ + ZXIC_UINT32 smmu0_int6_en31; + ZXIC_UINT32 smmu0_int6_en30; + ZXIC_UINT32 smmu0_int6_en29; + ZXIC_UINT32 smmu0_int6_en28; + ZXIC_UINT32 smmu0_int6_en27; + ZXIC_UINT32 smmu0_int6_en26; + ZXIC_UINT32 smmu0_int6_en25; + ZXIC_UINT32 smmu0_int6_en24; + ZXIC_UINT32 smmu0_int6_en23; + ZXIC_UINT32 smmu0_int6_en22; + ZXIC_UINT32 smmu0_int6_en21; + ZXIC_UINT32 smmu0_int6_en20; + ZXIC_UINT32 smmu0_int6_en19; + ZXIC_UINT32 smmu0_int6_en18; + ZXIC_UINT32 smmu0_int6_en17; + ZXIC_UINT32 smmu0_int6_en16; + ZXIC_UINT32 smmu0_int6_en15; + ZXIC_UINT32 smmu0_int6_en14; + ZXIC_UINT32 smmu0_int6_en13; + ZXIC_UINT32 smmu0_int6_en12; + ZXIC_UINT32 smmu0_int6_en11; + ZXIC_UINT32 smmu0_int6_en10; + ZXIC_UINT32 smmu0_int6_en9; + ZXIC_UINT32 smmu0_int6_en8; + ZXIC_UINT32 smmu0_int6_en7; + ZXIC_UINT32 smmu0_int6_en6; + ZXIC_UINT32 smmu0_int6_en5; + ZXIC_UINT32 smmu0_int6_en4; + ZXIC_UINT32 smmu0_int6_en3; + ZXIC_UINT32 smmu0_int6_en2; + ZXIC_UINT32 smmu0_int6_en1; + ZXIC_UINT32 smmu0_int6_en0; +}DPP_SMMU0_SMMU0_SMMU0_INT6_EN_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int6_mask_t +{ + ZXIC_UINT32 smmu0_int6_mask31; + ZXIC_UINT32 smmu0_int6_mask30; + ZXIC_UINT32 smmu0_int6_mask29; + ZXIC_UINT32 smmu0_int6_mask28; + ZXIC_UINT32 smmu0_int6_mask27; + ZXIC_UINT32 smmu0_int6_mask26; + ZXIC_UINT32 smmu0_int6_mask25; + ZXIC_UINT32 smmu0_int6_mask24; + ZXIC_UINT32 smmu0_int6_mask23; + ZXIC_UINT32 smmu0_int6_mask22; + ZXIC_UINT32 smmu0_int6_mask21; + ZXIC_UINT32 smmu0_int6_mask20; + ZXIC_UINT32 smmu0_int6_mask19; + ZXIC_UINT32 smmu0_int6_mask18; + ZXIC_UINT32 smmu0_int6_mask17; + ZXIC_UINT32 smmu0_int6_mask16; + ZXIC_UINT32 smmu0_int6_mask15; + ZXIC_UINT32 smmu0_int6_mask14; + ZXIC_UINT32 smmu0_int6_mask13; + ZXIC_UINT32 smmu0_int6_mask12; + ZXIC_UINT32 smmu0_int6_mask11; + ZXIC_UINT32 smmu0_int6_mask10; + ZXIC_UINT32 smmu0_int6_mask9; + ZXIC_UINT32 smmu0_int6_mask8; + ZXIC_UINT32 smmu0_int6_mask7; + ZXIC_UINT32 smmu0_int6_mask6; + ZXIC_UINT32 smmu0_int6_mask5; + ZXIC_UINT32 smmu0_int6_mask4; + ZXIC_UINT32 smmu0_int6_mask3; + ZXIC_UINT32 smmu0_int6_mask2; + ZXIC_UINT32 smmu0_int6_mask1; + ZXIC_UINT32 smmu0_int6_mask0; +}DPP_SMMU0_SMMU0_SMMU0_INT6_MASK_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int6_status_t +{ + ZXIC_UINT32 smmu0_int6_status31; + ZXIC_UINT32 smmu0_int6_status30; + ZXIC_UINT32 smmu0_int6_status29; + ZXIC_UINT32 smmu0_int6_status28; + ZXIC_UINT32 smmu0_int6_status27; + ZXIC_UINT32 smmu0_int6_status26; + ZXIC_UINT32 smmu0_int6_status25; + ZXIC_UINT32 smmu0_int6_status24; + ZXIC_UINT32 smmu0_int6_status23; + ZXIC_UINT32 smmu0_int6_status22; + ZXIC_UINT32 smmu0_int6_status21; + ZXIC_UINT32 smmu0_int6_status20; + ZXIC_UINT32 smmu0_int6_status19; + ZXIC_UINT32 smmu0_int6_status18; + ZXIC_UINT32 smmu0_int6_status17; + ZXIC_UINT32 smmu0_int6_status16; + ZXIC_UINT32 smmu0_int6_status15; + ZXIC_UINT32 smmu0_int6_status14; + ZXIC_UINT32 smmu0_int6_status13; + ZXIC_UINT32 smmu0_int6_status12; + ZXIC_UINT32 smmu0_int6_status11; + ZXIC_UINT32 smmu0_int6_status10; + ZXIC_UINT32 smmu0_int6_status9; + ZXIC_UINT32 smmu0_int6_status8; + ZXIC_UINT32 smmu0_int6_status7; + ZXIC_UINT32 smmu0_int6_status6; + ZXIC_UINT32 smmu0_int6_status5; + ZXIC_UINT32 smmu0_int6_status4; + ZXIC_UINT32 smmu0_int6_status3; + ZXIC_UINT32 smmu0_int6_status2; + ZXIC_UINT32 smmu0_int6_status1; + ZXIC_UINT32 smmu0_int6_status0; +}DPP_SMMU0_SMMU0_SMMU0_INT6_STATUS_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int7_en_t +{ + ZXIC_UINT32 smmu0_int7_en31; + ZXIC_UINT32 smmu0_int7_en30; + ZXIC_UINT32 smmu0_int7_en29; + ZXIC_UINT32 smmu0_int7_en28; + ZXIC_UINT32 smmu0_int7_en27; + ZXIC_UINT32 smmu0_int7_en26; + ZXIC_UINT32 smmu0_int7_en25; + ZXIC_UINT32 smmu0_int7_en24; + ZXIC_UINT32 smmu0_int7_en23; + ZXIC_UINT32 smmu0_int7_en22; + ZXIC_UINT32 smmu0_int7_en21; + ZXIC_UINT32 smmu0_int7_en20; + ZXIC_UINT32 smmu0_int7_en19; + ZXIC_UINT32 smmu0_int7_en18; + ZXIC_UINT32 smmu0_int7_en17; + ZXIC_UINT32 smmu0_int7_en16; + ZXIC_UINT32 smmu0_int7_en15; + ZXIC_UINT32 smmu0_int7_en14; + ZXIC_UINT32 smmu0_int7_en13; + ZXIC_UINT32 smmu0_int7_en12; + ZXIC_UINT32 smmu0_int7_en11; + ZXIC_UINT32 smmu0_int7_en10; + ZXIC_UINT32 smmu0_int7_en9; + ZXIC_UINT32 smmu0_int7_en8; + ZXIC_UINT32 smmu0_int7_en7; + ZXIC_UINT32 smmu0_int7_en6; + ZXIC_UINT32 smmu0_int7_en5; + ZXIC_UINT32 smmu0_int7_en4; + ZXIC_UINT32 smmu0_int7_en3; + ZXIC_UINT32 smmu0_int7_en2; + ZXIC_UINT32 smmu0_int7_en1; + ZXIC_UINT32 smmu0_int7_en0; +}DPP_SMMU0_SMMU0_SMMU0_INT7_EN_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int7_mask_t +{ + ZXIC_UINT32 smmu0_int7_mask31; + ZXIC_UINT32 smmu0_int7_mask30; + ZXIC_UINT32 smmu0_int7_mask29; + ZXIC_UINT32 smmu0_int7_mask28; + ZXIC_UINT32 smmu0_int7_mask27; + ZXIC_UINT32 smmu0_int7_mask26; + ZXIC_UINT32 smmu0_int7_mask25; + ZXIC_UINT32 smmu0_int7_mask24; + ZXIC_UINT32 smmu0_int7_mask23; + ZXIC_UINT32 smmu0_int7_mask22; + ZXIC_UINT32 smmu0_int7_mask21; + ZXIC_UINT32 smmu0_int7_mask20; + ZXIC_UINT32 smmu0_int7_mask19; + ZXIC_UINT32 smmu0_int7_mask18; + ZXIC_UINT32 smmu0_int7_mask17; + ZXIC_UINT32 smmu0_int7_mask16; + ZXIC_UINT32 smmu0_int7_mask15; + ZXIC_UINT32 smmu0_int7_mask14; + ZXIC_UINT32 smmu0_int7_mask13; + ZXIC_UINT32 smmu0_int7_mask12; + ZXIC_UINT32 smmu0_int7_mask11; + ZXIC_UINT32 smmu0_int7_mask10; + ZXIC_UINT32 smmu0_int7_mask9; + ZXIC_UINT32 smmu0_int7_mask8; + ZXIC_UINT32 smmu0_int7_mask7; + ZXIC_UINT32 smmu0_int7_mask6; + ZXIC_UINT32 smmu0_int7_mask5; + ZXIC_UINT32 smmu0_int7_mask4; + ZXIC_UINT32 smmu0_int7_mask3; + ZXIC_UINT32 smmu0_int7_mask2; + ZXIC_UINT32 smmu0_int7_mask1; + ZXIC_UINT32 smmu0_int7_mask0; +}DPP_SMMU0_SMMU0_SMMU0_INT7_MASK_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int7_status_t +{ + ZXIC_UINT32 smmu0_int7_status31; + ZXIC_UINT32 smmu0_int7_status30; + ZXIC_UINT32 smmu0_int7_status29; + ZXIC_UINT32 smmu0_int7_status28; + ZXIC_UINT32 smmu0_int7_status27; + ZXIC_UINT32 smmu0_int7_status26; + ZXIC_UINT32 smmu0_int7_status25; + ZXIC_UINT32 smmu0_int7_status24; + ZXIC_UINT32 smmu0_int7_status23; + ZXIC_UINT32 smmu0_int7_status22; + ZXIC_UINT32 smmu0_int7_status21; + ZXIC_UINT32 smmu0_int7_status20; + ZXIC_UINT32 smmu0_int7_status19; + ZXIC_UINT32 smmu0_int7_status18; + ZXIC_UINT32 smmu0_int7_status17; + ZXIC_UINT32 smmu0_int7_status16; + ZXIC_UINT32 smmu0_int7_status15; + ZXIC_UINT32 smmu0_int7_status14; + ZXIC_UINT32 smmu0_int7_status13; + ZXIC_UINT32 smmu0_int7_status12; + ZXIC_UINT32 smmu0_int7_status11; + ZXIC_UINT32 smmu0_int7_status10; + ZXIC_UINT32 smmu0_int7_status9; + ZXIC_UINT32 smmu0_int7_status8; + ZXIC_UINT32 smmu0_int7_status7; + ZXIC_UINT32 smmu0_int7_status6; + ZXIC_UINT32 smmu0_int7_status5; + ZXIC_UINT32 smmu0_int7_status4; + ZXIC_UINT32 smmu0_int7_status3; + ZXIC_UINT32 smmu0_int7_status2; + ZXIC_UINT32 smmu0_int7_status1; + ZXIC_UINT32 smmu0_int7_status0; +}DPP_SMMU0_SMMU0_SMMU0_INT7_STATUS_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int8_en_t +{ + ZXIC_UINT32 smmu0_int8_en31; + ZXIC_UINT32 smmu0_int8_en30; + ZXIC_UINT32 smmu0_int8_en29; + ZXIC_UINT32 smmu0_int8_en28; + ZXIC_UINT32 smmu0_int8_en27; + ZXIC_UINT32 smmu0_int8_en26; + ZXIC_UINT32 smmu0_int8_en25; + ZXIC_UINT32 smmu0_int8_en24; + ZXIC_UINT32 smmu0_int8_en23; + ZXIC_UINT32 smmu0_int8_en22; + ZXIC_UINT32 smmu0_int8_en21; + ZXIC_UINT32 smmu0_int8_en20; + ZXIC_UINT32 smmu0_int8_en19; + ZXIC_UINT32 smmu0_int8_en18; + ZXIC_UINT32 smmu0_int8_en17; + ZXIC_UINT32 smmu0_int8_en16; + ZXIC_UINT32 smmu0_int8_en15; + ZXIC_UINT32 smmu0_int8_en14; + ZXIC_UINT32 smmu0_int8_en13; + ZXIC_UINT32 smmu0_int8_en12; + ZXIC_UINT32 smmu0_int8_en11; + ZXIC_UINT32 smmu0_int8_en10; + ZXIC_UINT32 smmu0_int8_en9; + ZXIC_UINT32 smmu0_int8_en8; + ZXIC_UINT32 smmu0_int8_en7; + ZXIC_UINT32 smmu0_int8_en6; + ZXIC_UINT32 smmu0_int8_en5; + ZXIC_UINT32 smmu0_int8_en4; + ZXIC_UINT32 smmu0_int8_en3; + ZXIC_UINT32 smmu0_int8_en2; + ZXIC_UINT32 smmu0_int8_en1; + ZXIC_UINT32 smmu0_int8_en0; +}DPP_SMMU0_SMMU0_SMMU0_INT8_EN_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int8_mask_t +{ + ZXIC_UINT32 smmu0_int8_mask31; + ZXIC_UINT32 smmu0_int8_mask30; + ZXIC_UINT32 smmu0_int8_mask29; + ZXIC_UINT32 smmu0_int8_mask28; + ZXIC_UINT32 smmu0_int8_mask27; + ZXIC_UINT32 smmu0_int8_mask26; + ZXIC_UINT32 smmu0_int8_mask25; + ZXIC_UINT32 smmu0_int8_mask24; + ZXIC_UINT32 smmu0_int8_mask23; + ZXIC_UINT32 smmu0_int8_mask22; + ZXIC_UINT32 smmu0_int8_mask21; + ZXIC_UINT32 smmu0_int8_mask20; + ZXIC_UINT32 smmu0_int8_mask19; + ZXIC_UINT32 smmu0_int8_mask18; + ZXIC_UINT32 smmu0_int8_mask17; + ZXIC_UINT32 smmu0_int8_mask16; + ZXIC_UINT32 smmu0_int8_mask15; + ZXIC_UINT32 smmu0_int8_mask14; + ZXIC_UINT32 smmu0_int8_mask13; + ZXIC_UINT32 smmu0_int8_mask12; + ZXIC_UINT32 smmu0_int8_mask11; + ZXIC_UINT32 smmu0_int8_mask10; + ZXIC_UINT32 smmu0_int8_mask9; + ZXIC_UINT32 smmu0_int8_mask8; + ZXIC_UINT32 smmu0_int8_mask7; + ZXIC_UINT32 smmu0_int8_mask6; + ZXIC_UINT32 smmu0_int8_mask5; + ZXIC_UINT32 smmu0_int8_mask4; + ZXIC_UINT32 smmu0_int8_mask3; + ZXIC_UINT32 smmu0_int8_mask2; + ZXIC_UINT32 smmu0_int8_mask1; + ZXIC_UINT32 smmu0_int8_mask0; +}DPP_SMMU0_SMMU0_SMMU0_INT8_MASK_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int8_status_t +{ + ZXIC_UINT32 smmu0_int8_status31; + ZXIC_UINT32 smmu0_int8_status30; + ZXIC_UINT32 smmu0_int8_status29; + ZXIC_UINT32 smmu0_int8_status28; + ZXIC_UINT32 smmu0_int8_status27; + ZXIC_UINT32 smmu0_int8_status26; + ZXIC_UINT32 smmu0_int8_status25; + ZXIC_UINT32 smmu0_int8_status24; + ZXIC_UINT32 smmu0_int8_status23; + ZXIC_UINT32 smmu0_int8_status22; + ZXIC_UINT32 smmu0_int8_status21; + ZXIC_UINT32 smmu0_int8_status20; + ZXIC_UINT32 smmu0_int8_status19; + ZXIC_UINT32 smmu0_int8_status18; + ZXIC_UINT32 smmu0_int8_status17; + ZXIC_UINT32 smmu0_int8_status16; + ZXIC_UINT32 smmu0_int8_status15; + ZXIC_UINT32 smmu0_int8_status14; + ZXIC_UINT32 smmu0_int8_status13; + ZXIC_UINT32 smmu0_int8_status12; + ZXIC_UINT32 smmu0_int8_status11; + ZXIC_UINT32 smmu0_int8_status10; + ZXIC_UINT32 smmu0_int8_status9; + ZXIC_UINT32 smmu0_int8_status8; + ZXIC_UINT32 smmu0_int8_status7; + ZXIC_UINT32 smmu0_int8_status6; + ZXIC_UINT32 smmu0_int8_status5; + ZXIC_UINT32 smmu0_int8_status4; + ZXIC_UINT32 smmu0_int8_status3; + ZXIC_UINT32 smmu0_int8_status2; + ZXIC_UINT32 smmu0_int8_status1; + ZXIC_UINT32 smmu0_int8_status0; +}DPP_SMMU0_SMMU0_SMMU0_INT8_STATUS_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int9_en_t +{ + ZXIC_UINT32 smmu0_int8_en31; + ZXIC_UINT32 smmu0_int8_en30; + ZXIC_UINT32 smmu0_int8_en29; + ZXIC_UINT32 smmu0_int8_en28; + ZXIC_UINT32 smmu0_int8_en27; + ZXIC_UINT32 smmu0_int8_en26; + ZXIC_UINT32 smmu0_int8_en25; + ZXIC_UINT32 smmu0_int8_en24; + ZXIC_UINT32 smmu0_int8_en23; + ZXIC_UINT32 smmu0_int8_en22; + ZXIC_UINT32 smmu0_int8_en21; + ZXIC_UINT32 smmu0_int8_en20; + ZXIC_UINT32 smmu0_int9_en19; + ZXIC_UINT32 smmu0_int9_en18; + ZXIC_UINT32 smmu0_int9_en17; + ZXIC_UINT32 smmu0_int9_en16; + ZXIC_UINT32 smmu0_int9_en15; + ZXIC_UINT32 smmu0_int9_en14; + ZXIC_UINT32 smmu0_int9_en13; + ZXIC_UINT32 smmu0_int9_en12; + ZXIC_UINT32 smmu0_int9_en11; + ZXIC_UINT32 smmu0_int9_en10; + ZXIC_UINT32 smmu0_int9_en9; + ZXIC_UINT32 smmu0_int9_en8; + ZXIC_UINT32 smmu0_int9_en7; + ZXIC_UINT32 smmu0_int9_en6; + ZXIC_UINT32 smmu0_int9_en5; + ZXIC_UINT32 smmu0_int9_en4; + ZXIC_UINT32 smmu0_int9_en3; + ZXIC_UINT32 smmu0_int9_en2; + ZXIC_UINT32 smmu0_int9_en1; + ZXIC_UINT32 smmu0_int9_en0; +}DPP_SMMU0_SMMU0_SMMU0_INT9_EN_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int9_mask_t +{ + ZXIC_UINT32 smmu0_int9_mask0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT9_MASK_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int9_status_t +{ + ZXIC_UINT32 smmu0_int9_status0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT9_STATUS_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int10_en_t +{ + ZXIC_UINT32 smmu0_int10_en31; + ZXIC_UINT32 smmu0_int10_en30; + ZXIC_UINT32 smmu0_int10_en29; + ZXIC_UINT32 smmu0_int10_en28; + ZXIC_UINT32 smmu0_int10_en27; + ZXIC_UINT32 smmu0_int10_en26; + ZXIC_UINT32 smmu0_int10_en25; + ZXIC_UINT32 smmu0_int10_en24; + ZXIC_UINT32 smmu0_int10_en23; + ZXIC_UINT32 smmu0_int10_en22; + ZXIC_UINT32 smmu0_int10_en21; + ZXIC_UINT32 smmu0_int10_en20; + ZXIC_UINT32 smmu0_int10_en19; + ZXIC_UINT32 smmu0_int10_en18; + ZXIC_UINT32 smmu0_int10_en17; + ZXIC_UINT32 smmu0_int10_en16; + ZXIC_UINT32 smmu0_int10_en15; + ZXIC_UINT32 smmu0_int10_en14; + ZXIC_UINT32 smmu0_int10_en13; + ZXIC_UINT32 smmu0_int10_en12; + ZXIC_UINT32 smmu0_int10_en11; + ZXIC_UINT32 smmu0_int10_en10; + ZXIC_UINT32 smmu0_int10_en9; + ZXIC_UINT32 smmu0_int10_en8; + ZXIC_UINT32 smmu0_int10_en7; + ZXIC_UINT32 smmu0_int10_en6; + ZXIC_UINT32 smmu0_int10_en5; + ZXIC_UINT32 smmu0_int10_en4; + ZXIC_UINT32 smmu0_int10_en3; + ZXIC_UINT32 smmu0_int10_en2; + ZXIC_UINT32 smmu0_int10_en1; + ZXIC_UINT32 smmu0_int10_en0; +}DPP_SMMU0_SMMU0_SMMU0_INT10_EN_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int10_mask_t +{ + ZXIC_UINT32 smmu0_int10_mask0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT10_MASK_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int10_status_t +{ + ZXIC_UINT32 smmu0_int10_status0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT10_STATUS_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int11_en_t +{ + ZXIC_UINT32 smmu0_int11_en0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT11_EN_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int11_mask_t +{ + ZXIC_UINT32 smmu0_int11_mask0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT11_MASK_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int11_status_t +{ + ZXIC_UINT32 smmu0_int11_status0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT11_STATUS_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int12_en_t +{ + ZXIC_UINT32 smmu0_int12_en0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT12_EN_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int12_mask_t +{ + ZXIC_UINT32 smmu0_int12_mask0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT12_MASK_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int12_status_t +{ + ZXIC_UINT32 smmu0_int12_status0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT12_STATUS_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int13_en_t +{ + ZXIC_UINT32 smmu0_int13_en19; + ZXIC_UINT32 smmu0_int13_en18; + ZXIC_UINT32 smmu0_int13_en17; + ZXIC_UINT32 smmu0_int13_en16; + ZXIC_UINT32 smmu0_int13_en15; + ZXIC_UINT32 smmu0_int13_en14; + ZXIC_UINT32 smmu0_int13_en13; + ZXIC_UINT32 smmu0_int13_en12; + ZXIC_UINT32 smmu0_int13_en11; + ZXIC_UINT32 smmu0_int13_en10; + ZXIC_UINT32 smmu0_int13_en9; + ZXIC_UINT32 smmu0_int13_en8; + ZXIC_UINT32 smmu0_int13_en7; + ZXIC_UINT32 smmu0_int13_en6; + ZXIC_UINT32 smmu0_int13_en5; + ZXIC_UINT32 smmu0_int13_en4; + ZXIC_UINT32 smmu0_int13_en3; + ZXIC_UINT32 smmu0_int13_en2; + ZXIC_UINT32 smmu0_int13_en1; + ZXIC_UINT32 smmu0_int13_en0; +}DPP_SMMU0_SMMU0_SMMU0_INT13_EN_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int13_mask_t +{ + ZXIC_UINT32 smmu0_int13_mask19; + ZXIC_UINT32 smmu0_int13_mask18; + ZXIC_UINT32 smmu0_int13_mask17; + ZXIC_UINT32 smmu0_int13_mask16; + ZXIC_UINT32 smmu0_int13_mask15; + ZXIC_UINT32 smmu0_int13_mask14; + ZXIC_UINT32 smmu0_int13_mask13; + ZXIC_UINT32 smmu0_int13_mask12; + ZXIC_UINT32 smmu0_int13_mask11; + ZXIC_UINT32 smmu0_int13_mask10; + ZXIC_UINT32 smmu0_int13_mask9; + ZXIC_UINT32 smmu0_int13_mask8; + ZXIC_UINT32 smmu0_int13_mask7; + ZXIC_UINT32 smmu0_int13_mask6; + ZXIC_UINT32 smmu0_int13_mask5; + ZXIC_UINT32 smmu0_int13_mask4; + ZXIC_UINT32 smmu0_int13_mask3; + ZXIC_UINT32 smmu0_int13_mask2; + ZXIC_UINT32 smmu0_int13_mask1; + ZXIC_UINT32 smmu0_int13_mask0; +}DPP_SMMU0_SMMU0_SMMU0_INT13_MASK_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int13_status_t +{ + ZXIC_UINT32 smmu0_int13_status19; + ZXIC_UINT32 smmu0_int13_status18; + ZXIC_UINT32 smmu0_int13_status17; + ZXIC_UINT32 smmu0_int13_status16; + ZXIC_UINT32 smmu0_int13_status15; + ZXIC_UINT32 smmu0_int13_status14; + ZXIC_UINT32 smmu0_int13_status13; + ZXIC_UINT32 smmu0_int13_status12; + ZXIC_UINT32 smmu0_int13_status11; + ZXIC_UINT32 smmu0_int13_status10; + ZXIC_UINT32 smmu0_int13_status9; + ZXIC_UINT32 smmu0_int13_status8; + ZXIC_UINT32 smmu0_int13_status7; + ZXIC_UINT32 smmu0_int13_status6; + ZXIC_UINT32 smmu0_int13_status5; + ZXIC_UINT32 smmu0_int13_status4; + ZXIC_UINT32 smmu0_int13_status3; + ZXIC_UINT32 smmu0_int13_status2; + ZXIC_UINT32 smmu0_int13_status1; + ZXIC_UINT32 smmu0_int13_status0; +}DPP_SMMU0_SMMU0_SMMU0_INT13_STATUS_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int14_en_t +{ + ZXIC_UINT32 smmu0_int14_en16; + ZXIC_UINT32 smmu0_int14_en15; + ZXIC_UINT32 smmu0_int14_en14; + ZXIC_UINT32 smmu0_int14_en13; + ZXIC_UINT32 smmu0_int14_en12; + ZXIC_UINT32 smmu0_int14_en11; + ZXIC_UINT32 smmu0_int14_en10; + ZXIC_UINT32 smmu0_int14_en9; + ZXIC_UINT32 smmu0_int14_en8; + ZXIC_UINT32 smmu0_int14_en7; + ZXIC_UINT32 smmu0_int14_en6; + ZXIC_UINT32 smmu0_int14_en5; + ZXIC_UINT32 smmu0_int14_en4; + ZXIC_UINT32 smmu0_int14_en3; + ZXIC_UINT32 smmu0_int14_en2; + ZXIC_UINT32 smmu0_int14_en1; + ZXIC_UINT32 smmu0_int14_en0; +}DPP_SMMU0_SMMU0_SMMU0_INT14_EN_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int14_mask_t +{ + ZXIC_UINT32 smmu0_int14_mask16; + ZXIC_UINT32 smmu0_int14_mask15; + ZXIC_UINT32 smmu0_int14_mask14; + ZXIC_UINT32 smmu0_int14_mask13; + ZXIC_UINT32 smmu0_int14_mask12; + ZXIC_UINT32 smmu0_int14_mask11; + ZXIC_UINT32 smmu0_int14_mask10; + ZXIC_UINT32 smmu0_int14_mask9; + ZXIC_UINT32 smmu0_int14_mask8; + ZXIC_UINT32 smmu0_int14_mask7; + ZXIC_UINT32 smmu0_int14_mask6; + ZXIC_UINT32 smmu0_int14_mask5; + ZXIC_UINT32 smmu0_int14_mask4; + ZXIC_UINT32 smmu0_int14_mask3; + ZXIC_UINT32 smmu0_int14_mask2; + ZXIC_UINT32 smmu0_int14_mask1; + ZXIC_UINT32 smmu0_int14_mask0; +}DPP_SMMU0_SMMU0_SMMU0_INT14_MASK_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int14_status_t +{ + ZXIC_UINT32 smmu0_int14_status16; + ZXIC_UINT32 smmu0_int14_status15; + ZXIC_UINT32 smmu0_int14_status14; + ZXIC_UINT32 smmu0_int14_status13; + ZXIC_UINT32 smmu0_int14_status12; + ZXIC_UINT32 smmu0_int14_status11; + ZXIC_UINT32 smmu0_int14_status10; + ZXIC_UINT32 smmu0_int14_status9; + ZXIC_UINT32 smmu0_int14_status8; + ZXIC_UINT32 smmu0_int14_status7; + ZXIC_UINT32 smmu0_int14_status6; + ZXIC_UINT32 smmu0_int14_status5; + ZXIC_UINT32 smmu0_int14_status4; + ZXIC_UINT32 smmu0_int14_status3; + ZXIC_UINT32 smmu0_int14_status2; + ZXIC_UINT32 smmu0_int14_status1; + ZXIC_UINT32 smmu0_int14_status0; +}DPP_SMMU0_SMMU0_SMMU0_INT14_STATUS_T; + +typedef struct dpp_smmu0_smmu0_smmu0_ecc_unmask_flag_t +{ + ZXIC_UINT32 smmu0_int53_unmask_flag; + ZXIC_UINT32 smmu0_int52_unmask_flag; + ZXIC_UINT32 smmu0_int51_unmask_flag; + ZXIC_UINT32 smmu0_int50_unmask_flag; + ZXIC_UINT32 smmu0_int49_unmask_flag; + ZXIC_UINT32 smmu0_int48_unmask_flag; + ZXIC_UINT32 smmu0_int47_unmask_flag; + ZXIC_UINT32 smmu0_int46_unmask_flag; + ZXIC_UINT32 smmu0_int45_unmask_flag; + ZXIC_UINT32 smmu0_int44_unmask_flag; + ZXIC_UINT32 smmu0_int43_unmask_flag; + ZXIC_UINT32 smmu0_int42_unmask_flag; + ZXIC_UINT32 smmu0_int41_unmask_flag; + ZXIC_UINT32 smmu0_int40_unmask_flag; + ZXIC_UINT32 smmu0_int39_unmask_flag; + ZXIC_UINT32 smmu0_int38_unmask_flag; + ZXIC_UINT32 smmu0_int37_unmask_flag; + ZXIC_UINT32 smmu0_int36_unmask_flag; + ZXIC_UINT32 smmu0_int35_unmask_flag; + ZXIC_UINT32 smmu0_int34_unmask_flag; + ZXIC_UINT32 smmu0_int33_unmask_flag; + ZXIC_UINT32 smmu0_int32_unmask_flag; +}DPP_SMMU0_SMMU0_SMMU0_ECC_UNMASK_FLAG_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int15_en_t +{ + ZXIC_UINT32 smmu0_int15_en31; + ZXIC_UINT32 smmu0_int15_en30; + ZXIC_UINT32 smmu0_int15_en29; + ZXIC_UINT32 smmu0_int15_en28; + ZXIC_UINT32 smmu0_int15_en27; + ZXIC_UINT32 smmu0_int15_en26; + ZXIC_UINT32 smmu0_int15_en25; + ZXIC_UINT32 smmu0_int15_en24; + ZXIC_UINT32 smmu0_int15_en23; + ZXIC_UINT32 smmu0_int15_en22; + ZXIC_UINT32 smmu0_int15_en21; + ZXIC_UINT32 smmu0_int15_en20; + ZXIC_UINT32 smmu0_int15_en19; + ZXIC_UINT32 smmu0_int15_en18; + ZXIC_UINT32 smmu0_int15_en17; + ZXIC_UINT32 smmu0_int15_en16; + ZXIC_UINT32 smmu0_int15_en15; + ZXIC_UINT32 smmu0_int15_en14; + ZXIC_UINT32 smmu0_int15_en13; + ZXIC_UINT32 smmu0_int15_en12; + ZXIC_UINT32 smmu0_int15_en11; + ZXIC_UINT32 smmu0_int15_en10; + ZXIC_UINT32 smmu0_int15_en9; + ZXIC_UINT32 smmu0_int15_en8; + ZXIC_UINT32 smmu0_int15_en7; + ZXIC_UINT32 smmu0_int15_en6; + ZXIC_UINT32 smmu0_int15_en5; + ZXIC_UINT32 smmu0_int15_en4; + ZXIC_UINT32 smmu0_int15_en3; + ZXIC_UINT32 smmu0_int15_en2; + ZXIC_UINT32 smmu0_int15_en1; + ZXIC_UINT32 smmu0_int15_en0; +}DPP_SMMU0_SMMU0_SMMU0_INT15_EN_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int15_mask_t +{ + ZXIC_UINT32 smmu0_int15_mask31; + ZXIC_UINT32 smmu0_int15_mask30; + ZXIC_UINT32 smmu0_int15_mask29; + ZXIC_UINT32 smmu0_int15_mask28; + ZXIC_UINT32 smmu0_int15_mask27; + ZXIC_UINT32 smmu0_int15_mask26; + ZXIC_UINT32 smmu0_int15_mask25; + ZXIC_UINT32 smmu0_int15_mask24; + ZXIC_UINT32 smmu0_int15_mask23; + ZXIC_UINT32 smmu0_int15_mask22; + ZXIC_UINT32 smmu0_int15_mask21; + ZXIC_UINT32 smmu0_int15_mask20; + ZXIC_UINT32 smmu0_int15_mask19; + ZXIC_UINT32 smmu0_int15_mask18; + ZXIC_UINT32 smmu0_int15_mask17; + ZXIC_UINT32 smmu0_int15_mask16; + ZXIC_UINT32 smmu0_int15_mask15; + ZXIC_UINT32 smmu0_int15_mask14; + ZXIC_UINT32 smmu0_int15_mask13; + ZXIC_UINT32 smmu0_int15_mask12; + ZXIC_UINT32 smmu0_int15_mask11; + ZXIC_UINT32 smmu0_int15_mask10; + ZXIC_UINT32 smmu0_int15_mask9; + ZXIC_UINT32 smmu0_int15_mask8; + ZXIC_UINT32 smmu0_int15_mask7; + ZXIC_UINT32 smmu0_int15_mask6; + ZXIC_UINT32 smmu0_int15_mask5; + ZXIC_UINT32 smmu0_int15_mask4; + ZXIC_UINT32 smmu0_int15_mask3; + ZXIC_UINT32 smmu0_int15_mask2; + ZXIC_UINT32 smmu0_int15_mask1; + ZXIC_UINT32 smmu0_int15_mask0; +}DPP_SMMU0_SMMU0_SMMU0_INT15_MASK_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int15_status_t +{ + ZXIC_UINT32 smmu0_int15_status31; + ZXIC_UINT32 smmu0_int15_status30; + ZXIC_UINT32 smmu0_int15_status29; + ZXIC_UINT32 smmu0_int15_status28; + ZXIC_UINT32 smmu0_int15_status27; + ZXIC_UINT32 smmu0_int15_status26; + ZXIC_UINT32 smmu0_int15_status25; + ZXIC_UINT32 smmu0_int15_status24; + ZXIC_UINT32 smmu0_int15_status23; + ZXIC_UINT32 smmu0_int15_status22; + ZXIC_UINT32 smmu0_int15_status21; + ZXIC_UINT32 smmu0_int15_status20; + ZXIC_UINT32 smmu0_int15_status19; + ZXIC_UINT32 smmu0_int15_status18; + ZXIC_UINT32 smmu0_int15_status17; + ZXIC_UINT32 smmu0_int15_status16; + ZXIC_UINT32 smmu0_int15_status15; + ZXIC_UINT32 smmu0_int15_status14; + ZXIC_UINT32 smmu0_int15_status13; + ZXIC_UINT32 smmu0_int15_status12; + ZXIC_UINT32 smmu0_int15_status11; + ZXIC_UINT32 smmu0_int15_status10; + ZXIC_UINT32 smmu0_int15_status9; + ZXIC_UINT32 smmu0_int15_status8; + ZXIC_UINT32 smmu0_int15_status7; + ZXIC_UINT32 smmu0_int15_status6; + ZXIC_UINT32 smmu0_int15_status5; + ZXIC_UINT32 smmu0_int15_status4; + ZXIC_UINT32 smmu0_int15_status3; + ZXIC_UINT32 smmu0_int15_status2; + ZXIC_UINT32 smmu0_int15_status1; + ZXIC_UINT32 smmu0_int15_status0; +}DPP_SMMU0_SMMU0_SMMU0_INT15_STATUS_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int16_en_t +{ + ZXIC_UINT32 smmu0_int16_en31; + ZXIC_UINT32 smmu0_int16_en30; + ZXIC_UINT32 smmu0_int16_en29; + ZXIC_UINT32 smmu0_int16_en28; + ZXIC_UINT32 smmu0_int16_en27; + ZXIC_UINT32 smmu0_int16_en26; + ZXIC_UINT32 smmu0_int16_en25; + ZXIC_UINT32 smmu0_int16_en24; + ZXIC_UINT32 smmu0_int16_en23; + ZXIC_UINT32 smmu0_int16_en22; + ZXIC_UINT32 smmu0_int16_en21; + ZXIC_UINT32 smmu0_int16_en20; + ZXIC_UINT32 smmu0_int16_en19; + ZXIC_UINT32 smmu0_int16_en18; + ZXIC_UINT32 smmu0_int16_en17; + ZXIC_UINT32 smmu0_int16_en16; + ZXIC_UINT32 smmu0_int16_en15; + ZXIC_UINT32 smmu0_int16_en14; + ZXIC_UINT32 smmu0_int16_en13; + ZXIC_UINT32 smmu0_int16_en12; + ZXIC_UINT32 smmu0_int16_en11; + ZXIC_UINT32 smmu0_int16_en10; + ZXIC_UINT32 smmu0_int16_en9; + ZXIC_UINT32 smmu0_int16_en8; + ZXIC_UINT32 smmu0_int16_en7; + ZXIC_UINT32 smmu0_int16_en6; + ZXIC_UINT32 smmu0_int16_en5; + ZXIC_UINT32 smmu0_int16_en4; + ZXIC_UINT32 smmu0_int16_en3; + ZXIC_UINT32 smmu0_int16_en2; + ZXIC_UINT32 smmu0_int16_en1; + ZXIC_UINT32 smmu0_int16_en0; +}DPP_SMMU0_SMMU0_SMMU0_INT16_EN_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int16_mask_t +{ + ZXIC_UINT32 smmu0_int16_mask31; + ZXIC_UINT32 smmu0_int16_mask30; + ZXIC_UINT32 smmu0_int16_mask29; + ZXIC_UINT32 smmu0_int16_mask28; + ZXIC_UINT32 smmu0_int16_mask27; + ZXIC_UINT32 smmu0_int16_mask26; + ZXIC_UINT32 smmu0_int16_mask25; + ZXIC_UINT32 smmu0_int16_mask24; + ZXIC_UINT32 smmu0_int16_mask23; + ZXIC_UINT32 smmu0_int16_mask22; + ZXIC_UINT32 smmu0_int16_mask21; + ZXIC_UINT32 smmu0_int16_mask20; + ZXIC_UINT32 smmu0_int16_mask19; + ZXIC_UINT32 smmu0_int16_mask18; + ZXIC_UINT32 smmu0_int16_mask17; + ZXIC_UINT32 smmu0_int16_mask16; + ZXIC_UINT32 smmu0_int16_mask15; + ZXIC_UINT32 smmu0_int16_mask14; + ZXIC_UINT32 smmu0_int16_mask13; + ZXIC_UINT32 smmu0_int16_mask12; + ZXIC_UINT32 smmu0_int16_mask11; + ZXIC_UINT32 smmu0_int16_mask10; + ZXIC_UINT32 smmu0_int16_mask9; + ZXIC_UINT32 smmu0_int16_mask8; + ZXIC_UINT32 smmu0_int16_mask7; + ZXIC_UINT32 smmu0_int16_mask6; + ZXIC_UINT32 smmu0_int16_mask5; + ZXIC_UINT32 smmu0_int16_mask4; + ZXIC_UINT32 smmu0_int16_mask3; + ZXIC_UINT32 smmu0_int16_mask2; + ZXIC_UINT32 smmu0_int16_mask1; + ZXIC_UINT32 smmu0_int16_mask0; +}DPP_SMMU0_SMMU0_SMMU0_INT16_MASK_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int16_status_t +{ + ZXIC_UINT32 smmu0_int16_status31; + ZXIC_UINT32 smmu0_int16_status30; + ZXIC_UINT32 smmu0_int16_status29; + ZXIC_UINT32 smmu0_int16_status28; + ZXIC_UINT32 smmu0_int16_status27; + ZXIC_UINT32 smmu0_int16_status26; + ZXIC_UINT32 smmu0_int16_status25; + ZXIC_UINT32 smmu0_int16_status24; + ZXIC_UINT32 smmu0_int16_status23; + ZXIC_UINT32 smmu0_int16_status22; + ZXIC_UINT32 smmu0_int16_status21; + ZXIC_UINT32 smmu0_int16_status20; + ZXIC_UINT32 smmu0_int16_status19; + ZXIC_UINT32 smmu0_int16_status18; + ZXIC_UINT32 smmu0_int16_status17; + ZXIC_UINT32 smmu0_int16_status16; + ZXIC_UINT32 smmu0_int16_status15; + ZXIC_UINT32 smmu0_int16_status14; + ZXIC_UINT32 smmu0_int16_status13; + ZXIC_UINT32 smmu0_int16_status12; + ZXIC_UINT32 smmu0_int16_status11; + ZXIC_UINT32 smmu0_int16_status10; + ZXIC_UINT32 smmu0_int16_status9; + ZXIC_UINT32 smmu0_int16_status8; + ZXIC_UINT32 smmu0_int16_status7; + ZXIC_UINT32 smmu0_int16_status6; + ZXIC_UINT32 smmu0_int16_status5; + ZXIC_UINT32 smmu0_int16_status4; + ZXIC_UINT32 smmu0_int16_status3; + ZXIC_UINT32 smmu0_int16_status2; + ZXIC_UINT32 smmu0_int16_status1; + ZXIC_UINT32 smmu0_int16_status0; +}DPP_SMMU0_SMMU0_SMMU0_INT16_STATUS_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int17_en_t +{ + ZXIC_UINT32 smmu0_int17_en31; + ZXIC_UINT32 smmu0_int17_en30; + ZXIC_UINT32 smmu0_int17_en29; + ZXIC_UINT32 smmu0_int17_en28; + ZXIC_UINT32 smmu0_int17_en27; + ZXIC_UINT32 smmu0_int17_en26; + ZXIC_UINT32 smmu0_int17_en25; + ZXIC_UINT32 smmu0_int17_en24; + ZXIC_UINT32 smmu0_int17_en23; + ZXIC_UINT32 smmu0_int17_en22; + ZXIC_UINT32 smmu0_int17_en21; + ZXIC_UINT32 smmu0_int17_en20; + ZXIC_UINT32 smmu0_int17_en19; + ZXIC_UINT32 smmu0_int17_en18; + ZXIC_UINT32 smmu0_int17_en17; + ZXIC_UINT32 smmu0_int17_en16; + ZXIC_UINT32 smmu0_int17_en15; + ZXIC_UINT32 smmu0_int17_en14; + ZXIC_UINT32 smmu0_int17_en13; + ZXIC_UINT32 smmu0_int17_en12; + ZXIC_UINT32 smmu0_int17_en11; + ZXIC_UINT32 smmu0_int17_en10; + ZXIC_UINT32 smmu0_int17_en9; + ZXIC_UINT32 smmu0_int17_en8; + ZXIC_UINT32 smmu0_int17_en7; + ZXIC_UINT32 smmu0_int17_en6; + ZXIC_UINT32 smmu0_int17_en5; + ZXIC_UINT32 smmu0_int17_en4; + ZXIC_UINT32 smmu0_int17_en3; + ZXIC_UINT32 smmu0_int17_en2; + ZXIC_UINT32 smmu0_int17_en1; + ZXIC_UINT32 smmu0_int17_en0; +}DPP_SMMU0_SMMU0_SMMU0_INT17_EN_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int17_mask_t +{ + ZXIC_UINT32 smmu0_int17_mask31; + ZXIC_UINT32 smmu0_int17_mask30; + ZXIC_UINT32 smmu0_int17_mask29; + ZXIC_UINT32 smmu0_int17_mask28; + ZXIC_UINT32 smmu0_int17_mask27; + ZXIC_UINT32 smmu0_int17_mask26; + ZXIC_UINT32 smmu0_int17_mask25; + ZXIC_UINT32 smmu0_int17_mask24; + ZXIC_UINT32 smmu0_int17_mask23; + ZXIC_UINT32 smmu0_int17_mask22; + ZXIC_UINT32 smmu0_int17_mask21; + ZXIC_UINT32 smmu0_int17_mask20; + ZXIC_UINT32 smmu0_int17_mask19; + ZXIC_UINT32 smmu0_int17_mask18; + ZXIC_UINT32 smmu0_int17_mask17; + ZXIC_UINT32 smmu0_int17_mask16; + ZXIC_UINT32 smmu0_int17_mask15; + ZXIC_UINT32 smmu0_int17_mask14; + ZXIC_UINT32 smmu0_int17_mask13; + ZXIC_UINT32 smmu0_int17_mask12; + ZXIC_UINT32 smmu0_int17_mask11; + ZXIC_UINT32 smmu0_int17_mask10; + ZXIC_UINT32 smmu0_int17_mask9; + ZXIC_UINT32 smmu0_int17_mask8; + ZXIC_UINT32 smmu0_int17_mask7; + ZXIC_UINT32 smmu0_int17_mask6; + ZXIC_UINT32 smmu0_int17_mask5; + ZXIC_UINT32 smmu0_int17_mask4; + ZXIC_UINT32 smmu0_int17_mask3; + ZXIC_UINT32 smmu0_int17_mask2; + ZXIC_UINT32 smmu0_int17_mask1; + ZXIC_UINT32 smmu0_int17_mask0; +}DPP_SMMU0_SMMU0_SMMU0_INT17_MASK_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int17_status_t +{ + ZXIC_UINT32 smmu0_int17_status31; + ZXIC_UINT32 smmu0_int17_status30; + ZXIC_UINT32 smmu0_int17_status29; + ZXIC_UINT32 smmu0_int17_status28; + ZXIC_UINT32 smmu0_int17_status27; + ZXIC_UINT32 smmu0_int17_status26; + ZXIC_UINT32 smmu0_int17_status25; + ZXIC_UINT32 smmu0_int17_status24; + ZXIC_UINT32 smmu0_int17_status23; + ZXIC_UINT32 smmu0_int17_status22; + ZXIC_UINT32 smmu0_int17_status21; + ZXIC_UINT32 smmu0_int17_status20; + ZXIC_UINT32 smmu0_int17_status19; + ZXIC_UINT32 smmu0_int17_status18; + ZXIC_UINT32 smmu0_int17_status17; + ZXIC_UINT32 smmu0_int17_status16; + ZXIC_UINT32 smmu0_int17_status15; + ZXIC_UINT32 smmu0_int17_status14; + ZXIC_UINT32 smmu0_int17_status13; + ZXIC_UINT32 smmu0_int17_status12; + ZXIC_UINT32 smmu0_int17_status11; + ZXIC_UINT32 smmu0_int17_status10; + ZXIC_UINT32 smmu0_int17_status9; + ZXIC_UINT32 smmu0_int17_status8; + ZXIC_UINT32 smmu0_int17_status7; + ZXIC_UINT32 smmu0_int17_status6; + ZXIC_UINT32 smmu0_int17_status5; + ZXIC_UINT32 smmu0_int17_status4; + ZXIC_UINT32 smmu0_int17_status3; + ZXIC_UINT32 smmu0_int17_status2; + ZXIC_UINT32 smmu0_int17_status1; + ZXIC_UINT32 smmu0_int17_status0; +}DPP_SMMU0_SMMU0_SMMU0_INT17_STATUS_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int18_en_t +{ + ZXIC_UINT32 smmu0_int18_en31; + ZXIC_UINT32 smmu0_int18_en30; + ZXIC_UINT32 smmu0_int18_en29; + ZXIC_UINT32 smmu0_int18_en28; + ZXIC_UINT32 smmu0_int18_en27; + ZXIC_UINT32 smmu0_int18_en26; + ZXIC_UINT32 smmu0_int18_en25; + ZXIC_UINT32 smmu0_int18_en24; + ZXIC_UINT32 smmu0_int18_en23; + ZXIC_UINT32 smmu0_int18_en22; + ZXIC_UINT32 smmu0_int18_en21; + ZXIC_UINT32 smmu0_int18_en20; + ZXIC_UINT32 smmu0_int18_en19; + ZXIC_UINT32 smmu0_int18_en18; + ZXIC_UINT32 smmu0_int18_en17; + ZXIC_UINT32 smmu0_int18_en16; + ZXIC_UINT32 smmu0_int18_en15; + ZXIC_UINT32 smmu0_int18_en14; + ZXIC_UINT32 smmu0_int18_en13; + ZXIC_UINT32 smmu0_int18_en12; + ZXIC_UINT32 smmu0_int18_en11; + ZXIC_UINT32 smmu0_int18_en10; + ZXIC_UINT32 smmu0_int18_en9; + ZXIC_UINT32 smmu0_int18_en8; + ZXIC_UINT32 smmu0_int18_en7; + ZXIC_UINT32 smmu0_int18_en6; + ZXIC_UINT32 smmu0_int18_en5; + ZXIC_UINT32 smmu0_int18_en4; + ZXIC_UINT32 smmu0_int18_en3; + ZXIC_UINT32 smmu0_int18_en2; + ZXIC_UINT32 smmu0_int18_en1; + ZXIC_UINT32 smmu0_int18_en0; +}DPP_SMMU0_SMMU0_SMMU0_INT18_EN_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int18_mask_t +{ + ZXIC_UINT32 smmu0_int18_mask31; + ZXIC_UINT32 smmu0_int18_mask30; + ZXIC_UINT32 smmu0_int18_mask29; + ZXIC_UINT32 smmu0_int18_mask28; + ZXIC_UINT32 smmu0_int18_mask27; + ZXIC_UINT32 smmu0_int18_mask26; + ZXIC_UINT32 smmu0_int18_mask25; + ZXIC_UINT32 smmu0_int18_mask24; + ZXIC_UINT32 smmu0_int18_mask23; + ZXIC_UINT32 smmu0_int18_mask22; + ZXIC_UINT32 smmu0_int18_mask21; + ZXIC_UINT32 smmu0_int18_mask20; + ZXIC_UINT32 smmu0_int18_mask19; + ZXIC_UINT32 smmu0_int18_mask18; + ZXIC_UINT32 smmu0_int18_mask17; + ZXIC_UINT32 smmu0_int18_mask16; + ZXIC_UINT32 smmu0_int18_mask15; + ZXIC_UINT32 smmu0_int18_mask14; + ZXIC_UINT32 smmu0_int18_mask13; + ZXIC_UINT32 smmu0_int18_mask12; + ZXIC_UINT32 smmu0_int18_mask11; + ZXIC_UINT32 smmu0_int18_mask10; + ZXIC_UINT32 smmu0_int18_mask9; + ZXIC_UINT32 smmu0_int18_mask8; + ZXIC_UINT32 smmu0_int18_mask7; + ZXIC_UINT32 smmu0_int18_mask6; + ZXIC_UINT32 smmu0_int18_mask5; + ZXIC_UINT32 smmu0_int18_mask4; + ZXIC_UINT32 smmu0_int18_mask3; + ZXIC_UINT32 smmu0_int18_mask2; + ZXIC_UINT32 smmu0_int18_mask1; + ZXIC_UINT32 smmu0_int18_mask0; +}DPP_SMMU0_SMMU0_SMMU0_INT18_MASK_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int18_status_t +{ + ZXIC_UINT32 smmu0_int18_status31; + ZXIC_UINT32 smmu0_int18_status30; + ZXIC_UINT32 smmu0_int18_status29; + ZXIC_UINT32 smmu0_int18_status28; + ZXIC_UINT32 smmu0_int18_status27; + ZXIC_UINT32 smmu0_int18_status26; + ZXIC_UINT32 smmu0_int18_status25; + ZXIC_UINT32 smmu0_int18_status24; + ZXIC_UINT32 smmu0_int18_status23; + ZXIC_UINT32 smmu0_int18_status22; + ZXIC_UINT32 smmu0_int18_status21; + ZXIC_UINT32 smmu0_int18_status20; + ZXIC_UINT32 smmu0_int18_status19; + ZXIC_UINT32 smmu0_int18_status18; + ZXIC_UINT32 smmu0_int18_status17; + ZXIC_UINT32 smmu0_int18_status16; + ZXIC_UINT32 smmu0_int18_status15; + ZXIC_UINT32 smmu0_int18_status14; + ZXIC_UINT32 smmu0_int18_status13; + ZXIC_UINT32 smmu0_int18_status12; + ZXIC_UINT32 smmu0_int18_status11; + ZXIC_UINT32 smmu0_int18_status10; + ZXIC_UINT32 smmu0_int18_status9; + ZXIC_UINT32 smmu0_int18_status8; + ZXIC_UINT32 smmu0_int18_status7; + ZXIC_UINT32 smmu0_int18_status6; + ZXIC_UINT32 smmu0_int18_status5; + ZXIC_UINT32 smmu0_int18_status4; + ZXIC_UINT32 smmu0_int18_status3; + ZXIC_UINT32 smmu0_int18_status2; + ZXIC_UINT32 smmu0_int18_status1; + ZXIC_UINT32 smmu0_int18_status0; +}DPP_SMMU0_SMMU0_SMMU0_INT18_STATUS_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int19_en_t +{ + ZXIC_UINT32 smmu0_int19_en31; + ZXIC_UINT32 smmu0_int19_en30; + ZXIC_UINT32 smmu0_int19_en29; + ZXIC_UINT32 smmu0_int19_en28; + ZXIC_UINT32 smmu0_int19_en27; + ZXIC_UINT32 smmu0_int19_en26; + ZXIC_UINT32 smmu0_int19_en25; + ZXIC_UINT32 smmu0_int19_en24; + ZXIC_UINT32 smmu0_int19_en23; + ZXIC_UINT32 smmu0_int19_en22; + ZXIC_UINT32 smmu0_int19_en21; + ZXIC_UINT32 smmu0_int19_en20; + ZXIC_UINT32 smmu0_int19_en19; + ZXIC_UINT32 smmu0_int19_en18; + ZXIC_UINT32 smmu0_int19_en17; + ZXIC_UINT32 smmu0_int19_en16; + ZXIC_UINT32 smmu0_int19_en15; + ZXIC_UINT32 smmu0_int19_en14; + ZXIC_UINT32 smmu0_int19_en13; + ZXIC_UINT32 smmu0_int19_en12; + ZXIC_UINT32 smmu0_int19_en11; + ZXIC_UINT32 smmu0_int19_en10; + ZXIC_UINT32 smmu0_int19_en9; + ZXIC_UINT32 smmu0_int19_en8; + ZXIC_UINT32 smmu0_int19_en7; + ZXIC_UINT32 smmu0_int19_en6; + ZXIC_UINT32 smmu0_int19_en5; + ZXIC_UINT32 smmu0_int19_en4; + ZXIC_UINT32 smmu0_int19_en3; + ZXIC_UINT32 smmu0_int19_en2; + ZXIC_UINT32 smmu0_int19_en1; + ZXIC_UINT32 smmu0_int19_en0; +}DPP_SMMU0_SMMU0_SMMU0_INT19_EN_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int19_mask_t +{ + ZXIC_UINT32 smmu0_int19_mask31; + ZXIC_UINT32 smmu0_int19_mask30; + ZXIC_UINT32 smmu0_int19_mask29; + ZXIC_UINT32 smmu0_int19_mask28; + ZXIC_UINT32 smmu0_int19_mask27; + ZXIC_UINT32 smmu0_int19_mask26; + ZXIC_UINT32 smmu0_int19_mask25; + ZXIC_UINT32 smmu0_int19_mask24; + ZXIC_UINT32 smmu0_int19_mask23; + ZXIC_UINT32 smmu0_int19_mask22; + ZXIC_UINT32 smmu0_int19_mask21; + ZXIC_UINT32 smmu0_int19_mask20; + ZXIC_UINT32 smmu0_int19_mask19; + ZXIC_UINT32 smmu0_int19_mask18; + ZXIC_UINT32 smmu0_int19_mask17; + ZXIC_UINT32 smmu0_int19_mask16; + ZXIC_UINT32 smmu0_int19_mask15; + ZXIC_UINT32 smmu0_int19_mask14; + ZXIC_UINT32 smmu0_int19_mask13; + ZXIC_UINT32 smmu0_int19_mask12; + ZXIC_UINT32 smmu0_int19_mask11; + ZXIC_UINT32 smmu0_int19_mask10; + ZXIC_UINT32 smmu0_int19_mask9; + ZXIC_UINT32 smmu0_int19_mask8; + ZXIC_UINT32 smmu0_int19_mask7; + ZXIC_UINT32 smmu0_int19_mask6; + ZXIC_UINT32 smmu0_int19_mask5; + ZXIC_UINT32 smmu0_int19_mask4; + ZXIC_UINT32 smmu0_int19_mask3; + ZXIC_UINT32 smmu0_int19_mask2; + ZXIC_UINT32 smmu0_int19_mask1; + ZXIC_UINT32 smmu0_int19_mask0; +}DPP_SMMU0_SMMU0_SMMU0_INT19_MASK_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int19_status_t +{ + ZXIC_UINT32 smmu0_int19_status31; + ZXIC_UINT32 smmu0_int19_status30; + ZXIC_UINT32 smmu0_int19_status29; + ZXIC_UINT32 smmu0_int19_status28; + ZXIC_UINT32 smmu0_int19_status27; + ZXIC_UINT32 smmu0_int19_status26; + ZXIC_UINT32 smmu0_int19_status25; + ZXIC_UINT32 smmu0_int19_status24; + ZXIC_UINT32 smmu0_int19_status23; + ZXIC_UINT32 smmu0_int19_status22; + ZXIC_UINT32 smmu0_int19_status21; + ZXIC_UINT32 smmu0_int19_status20; + ZXIC_UINT32 smmu0_int19_status19; + ZXIC_UINT32 smmu0_int19_status18; + ZXIC_UINT32 smmu0_int19_status17; + ZXIC_UINT32 smmu0_int19_status16; + ZXIC_UINT32 smmu0_int19_status15; + ZXIC_UINT32 smmu0_int19_status14; + ZXIC_UINT32 smmu0_int19_status13; + ZXIC_UINT32 smmu0_int19_status12; + ZXIC_UINT32 smmu0_int19_status11; + ZXIC_UINT32 smmu0_int19_status10; + ZXIC_UINT32 smmu0_int19_status9; + ZXIC_UINT32 smmu0_int19_status8; + ZXIC_UINT32 smmu0_int19_status7; + ZXIC_UINT32 smmu0_int19_status6; + ZXIC_UINT32 smmu0_int19_status5; + ZXIC_UINT32 smmu0_int19_status4; + ZXIC_UINT32 smmu0_int19_status3; + ZXIC_UINT32 smmu0_int19_status2; + ZXIC_UINT32 smmu0_int19_status1; + ZXIC_UINT32 smmu0_int19_status0; +}DPP_SMMU0_SMMU0_SMMU0_INT19_STATUS_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int20_en_t +{ + ZXIC_UINT32 smmu0_int20_en31; + ZXIC_UINT32 smmu0_int20_en30; + ZXIC_UINT32 smmu0_int20_en29; + ZXIC_UINT32 smmu0_int20_en28; + ZXIC_UINT32 smmu0_int20_en27; + ZXIC_UINT32 smmu0_int20_en26; + ZXIC_UINT32 smmu0_int20_en25; + ZXIC_UINT32 smmu0_int20_en24; + ZXIC_UINT32 smmu0_int20_en23; + ZXIC_UINT32 smmu0_int20_en22; + ZXIC_UINT32 smmu0_int20_en21; + ZXIC_UINT32 smmu0_int20_en20; + ZXIC_UINT32 smmu0_int20_en19; + ZXIC_UINT32 smmu0_int20_en18; + ZXIC_UINT32 smmu0_int20_en17; + ZXIC_UINT32 smmu0_int20_en16; + ZXIC_UINT32 smmu0_int20_en15; + ZXIC_UINT32 smmu0_int20_en14; + ZXIC_UINT32 smmu0_int20_en13; + ZXIC_UINT32 smmu0_int20_en12; + ZXIC_UINT32 smmu0_int20_en11; + ZXIC_UINT32 smmu0_int20_en10; + ZXIC_UINT32 smmu0_int20_en9; + ZXIC_UINT32 smmu0_int20_en8; + ZXIC_UINT32 smmu0_int20_en7; + ZXIC_UINT32 smmu0_int20_en6; + ZXIC_UINT32 smmu0_int20_en5; + ZXIC_UINT32 smmu0_int20_en4; + ZXIC_UINT32 smmu0_int20_en3; + ZXIC_UINT32 smmu0_int20_en2; + ZXIC_UINT32 smmu0_int20_en1; + ZXIC_UINT32 smmu0_int20_en0; +}DPP_SMMU0_SMMU0_SMMU0_INT20_EN_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int20_mask_t +{ + ZXIC_UINT32 smmu0_int20_mask31; + ZXIC_UINT32 smmu0_int20_mask30; + ZXIC_UINT32 smmu0_int20_mask29; + ZXIC_UINT32 smmu0_int20_mask28; + ZXIC_UINT32 smmu0_int20_mask27; + ZXIC_UINT32 smmu0_int20_mask26; + ZXIC_UINT32 smmu0_int20_mask25; + ZXIC_UINT32 smmu0_int20_mask24; + ZXIC_UINT32 smmu0_int20_mask23; + ZXIC_UINT32 smmu0_int20_mask22; + ZXIC_UINT32 smmu0_int20_mask21; + ZXIC_UINT32 smmu0_int20_mask20; + ZXIC_UINT32 smmu0_int20_mask19; + ZXIC_UINT32 smmu0_int20_mask18; + ZXIC_UINT32 smmu0_int20_mask17; + ZXIC_UINT32 smmu0_int20_mask16; + ZXIC_UINT32 smmu0_int20_mask15; + ZXIC_UINT32 smmu0_int20_mask14; + ZXIC_UINT32 smmu0_int20_mask13; + ZXIC_UINT32 smmu0_int20_mask12; + ZXIC_UINT32 smmu0_int20_mask11; + ZXIC_UINT32 smmu0_int20_mask10; + ZXIC_UINT32 smmu0_int20_mask9; + ZXIC_UINT32 smmu0_int20_mask8; + ZXIC_UINT32 smmu0_int20_mask7; + ZXIC_UINT32 smmu0_int20_mask6; + ZXIC_UINT32 smmu0_int20_mask5; + ZXIC_UINT32 smmu0_int20_mask4; + ZXIC_UINT32 smmu0_int20_mask3; + ZXIC_UINT32 smmu0_int20_mask2; + ZXIC_UINT32 smmu0_int20_mask1; + ZXIC_UINT32 smmu0_int20_mask0; +}DPP_SMMU0_SMMU0_SMMU0_INT20_MASK_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int20_status_t +{ + ZXIC_UINT32 smmu0_int20_status31; + ZXIC_UINT32 smmu0_int20_status30; + ZXIC_UINT32 smmu0_int20_status29; + ZXIC_UINT32 smmu0_int20_status28; + ZXIC_UINT32 smmu0_int20_status27; + ZXIC_UINT32 smmu0_int20_status26; + ZXIC_UINT32 smmu0_int20_status25; + ZXIC_UINT32 smmu0_int20_status24; + ZXIC_UINT32 smmu0_int20_status23; + ZXIC_UINT32 smmu0_int20_status22; + ZXIC_UINT32 smmu0_int20_status21; + ZXIC_UINT32 smmu0_int20_status20; + ZXIC_UINT32 smmu0_int20_status19; + ZXIC_UINT32 smmu0_int20_status18; + ZXIC_UINT32 smmu0_int20_status17; + ZXIC_UINT32 smmu0_int20_status16; + ZXIC_UINT32 smmu0_int20_status15; + ZXIC_UINT32 smmu0_int20_status14; + ZXIC_UINT32 smmu0_int20_status13; + ZXIC_UINT32 smmu0_int20_status12; + ZXIC_UINT32 smmu0_int20_status11; + ZXIC_UINT32 smmu0_int20_status10; + ZXIC_UINT32 smmu0_int20_status9; + ZXIC_UINT32 smmu0_int20_status8; + ZXIC_UINT32 smmu0_int20_status7; + ZXIC_UINT32 smmu0_int20_status6; + ZXIC_UINT32 smmu0_int20_status5; + ZXIC_UINT32 smmu0_int20_status4; + ZXIC_UINT32 smmu0_int20_status3; + ZXIC_UINT32 smmu0_int20_status2; + ZXIC_UINT32 smmu0_int20_status1; + ZXIC_UINT32 smmu0_int20_status0; +}DPP_SMMU0_SMMU0_SMMU0_INT20_STATUS_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int21_en_t +{ + ZXIC_UINT32 smmu0_int21_en31; + ZXIC_UINT32 smmu0_int21_en30; + ZXIC_UINT32 smmu0_int21_en29; + ZXIC_UINT32 smmu0_int21_en28; + ZXIC_UINT32 smmu0_int21_en27; + ZXIC_UINT32 smmu0_int21_en26; + ZXIC_UINT32 smmu0_int21_en25; + ZXIC_UINT32 smmu0_int21_en24; + ZXIC_UINT32 smmu0_int21_en23; + ZXIC_UINT32 smmu0_int21_en22; + ZXIC_UINT32 smmu0_int21_en21; + ZXIC_UINT32 smmu0_int21_en20; + ZXIC_UINT32 smmu0_int21_en19; + ZXIC_UINT32 smmu0_int21_en18; + ZXIC_UINT32 smmu0_int21_en17; + ZXIC_UINT32 smmu0_int21_en16; + ZXIC_UINT32 smmu0_int21_en15; + ZXIC_UINT32 smmu0_int21_en14; + ZXIC_UINT32 smmu0_int21_en13; + ZXIC_UINT32 smmu0_int21_en12; + ZXIC_UINT32 smmu0_int21_en11; + ZXIC_UINT32 smmu0_int21_en10; + ZXIC_UINT32 smmu0_int21_en9; + ZXIC_UINT32 smmu0_int21_en8; + ZXIC_UINT32 smmu0_int21_en7; + ZXIC_UINT32 smmu0_int21_en6; + ZXIC_UINT32 smmu0_int21_en5; + ZXIC_UINT32 smmu0_int21_en4; + ZXIC_UINT32 smmu0_int21_en3; + ZXIC_UINT32 smmu0_int21_en2; + ZXIC_UINT32 smmu0_int21_en1; + ZXIC_UINT32 smmu0_int21_en0; +}DPP_SMMU0_SMMU0_SMMU0_INT21_EN_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int21_mask_t +{ + ZXIC_UINT32 smmu0_int21_mask31; + ZXIC_UINT32 smmu0_int21_mask30; + ZXIC_UINT32 smmu0_int21_mask29; + ZXIC_UINT32 smmu0_int21_mask28; + ZXIC_UINT32 smmu0_int21_mask27; + ZXIC_UINT32 smmu0_int21_mask26; + ZXIC_UINT32 smmu0_int21_mask25; + ZXIC_UINT32 smmu0_int21_mask24; + ZXIC_UINT32 smmu0_int21_mask23; + ZXIC_UINT32 smmu0_int21_mask22; + ZXIC_UINT32 smmu0_int21_mask21; + ZXIC_UINT32 smmu0_int21_mask20; + ZXIC_UINT32 smmu0_int21_mask19; + ZXIC_UINT32 smmu0_int21_mask18; + ZXIC_UINT32 smmu0_int21_mask17; + ZXIC_UINT32 smmu0_int21_mask16; + ZXIC_UINT32 smmu0_int21_mask15; + ZXIC_UINT32 smmu0_int21_mask14; + ZXIC_UINT32 smmu0_int21_mask13; + ZXIC_UINT32 smmu0_int21_mask12; + ZXIC_UINT32 smmu0_int21_mask11; + ZXIC_UINT32 smmu0_int21_mask10; + ZXIC_UINT32 smmu0_int21_mask9; + ZXIC_UINT32 smmu0_int21_mask8; + ZXIC_UINT32 smmu0_int21_mask7; + ZXIC_UINT32 smmu0_int21_mask6; + ZXIC_UINT32 smmu0_int21_mask5; + ZXIC_UINT32 smmu0_int21_mask4; + ZXIC_UINT32 smmu0_int21_mask3; + ZXIC_UINT32 smmu0_int21_mask2; + ZXIC_UINT32 smmu0_int21_mask1; + ZXIC_UINT32 smmu0_int21_mask0; +}DPP_SMMU0_SMMU0_SMMU0_INT21_MASK_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int21_status_t +{ + ZXIC_UINT32 smmu0_int21_status31; + ZXIC_UINT32 smmu0_int21_status30; + ZXIC_UINT32 smmu0_int21_status29; + ZXIC_UINT32 smmu0_int21_status28; + ZXIC_UINT32 smmu0_int21_status27; + ZXIC_UINT32 smmu0_int21_status26; + ZXIC_UINT32 smmu0_int21_status25; + ZXIC_UINT32 smmu0_int21_status24; + ZXIC_UINT32 smmu0_int21_status23; + ZXIC_UINT32 smmu0_int21_status22; + ZXIC_UINT32 smmu0_int21_status21; + ZXIC_UINT32 smmu0_int21_status20; + ZXIC_UINT32 smmu0_int21_status19; + ZXIC_UINT32 smmu0_int21_status18; + ZXIC_UINT32 smmu0_int21_status17; + ZXIC_UINT32 smmu0_int21_status16; + ZXIC_UINT32 smmu0_int21_status15; + ZXIC_UINT32 smmu0_int21_status14; + ZXIC_UINT32 smmu0_int21_status13; + ZXIC_UINT32 smmu0_int21_status12; + ZXIC_UINT32 smmu0_int21_status11; + ZXIC_UINT32 smmu0_int21_status10; + ZXIC_UINT32 smmu0_int21_status9; + ZXIC_UINT32 smmu0_int21_status8; + ZXIC_UINT32 smmu0_int21_status7; + ZXIC_UINT32 smmu0_int21_status6; + ZXIC_UINT32 smmu0_int21_status5; + ZXIC_UINT32 smmu0_int21_status4; + ZXIC_UINT32 smmu0_int21_status3; + ZXIC_UINT32 smmu0_int21_status2; + ZXIC_UINT32 smmu0_int21_status1; + ZXIC_UINT32 smmu0_int21_status0; +}DPP_SMMU0_SMMU0_SMMU0_INT21_STATUS_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int22_en_t +{ + ZXIC_UINT32 smmu0_int22_en31; + ZXIC_UINT32 smmu0_int22_en30; + ZXIC_UINT32 smmu0_int22_en29; + ZXIC_UINT32 smmu0_int22_en28; + ZXIC_UINT32 smmu0_int22_en27; + ZXIC_UINT32 smmu0_int22_en26; + ZXIC_UINT32 smmu0_int22_en25; + ZXIC_UINT32 smmu0_int22_en24; + ZXIC_UINT32 smmu0_int22_en23; + ZXIC_UINT32 smmu0_int22_en22; + ZXIC_UINT32 smmu0_int22_en21; + ZXIC_UINT32 smmu0_int22_en20; + ZXIC_UINT32 smmu0_int22_en19; + ZXIC_UINT32 smmu0_int22_en18; + ZXIC_UINT32 smmu0_int22_en17; + ZXIC_UINT32 smmu0_int22_en16; + ZXIC_UINT32 smmu0_int22_en15; + ZXIC_UINT32 smmu0_int22_en14; + ZXIC_UINT32 smmu0_int22_en13; + ZXIC_UINT32 smmu0_int22_en12; + ZXIC_UINT32 smmu0_int22_en11; + ZXIC_UINT32 smmu0_int22_en10; + ZXIC_UINT32 smmu0_int22_en9; + ZXIC_UINT32 smmu0_int22_en8; + ZXIC_UINT32 smmu0_int22_en7; + ZXIC_UINT32 smmu0_int22_en6; + ZXIC_UINT32 smmu0_int22_en5; + ZXIC_UINT32 smmu0_int22_en4; + ZXIC_UINT32 smmu0_int22_en3; + ZXIC_UINT32 smmu0_int22_en2; + ZXIC_UINT32 smmu0_int22_en1; + ZXIC_UINT32 smmu0_int22_en0; +}DPP_SMMU0_SMMU0_SMMU0_INT22_EN_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int22_mask_t +{ + ZXIC_UINT32 smmu0_int22_mask31; + ZXIC_UINT32 smmu0_int22_mask30; + ZXIC_UINT32 smmu0_int22_mask29; + ZXIC_UINT32 smmu0_int22_mask28; + ZXIC_UINT32 smmu0_int22_mask27; + ZXIC_UINT32 smmu0_int22_mask26; + ZXIC_UINT32 smmu0_int22_mask25; + ZXIC_UINT32 smmu0_int22_mask24; + ZXIC_UINT32 smmu0_int22_mask23; + ZXIC_UINT32 smmu0_int22_mask22; + ZXIC_UINT32 smmu0_int22_mask21; + ZXIC_UINT32 smmu0_int22_mask20; + ZXIC_UINT32 smmu0_int22_mask19; + ZXIC_UINT32 smmu0_int22_mask18; + ZXIC_UINT32 smmu0_int22_mask17; + ZXIC_UINT32 smmu0_int22_mask16; + ZXIC_UINT32 smmu0_int22_mask15; + ZXIC_UINT32 smmu0_int22_mask14; + ZXIC_UINT32 smmu0_int22_mask13; + ZXIC_UINT32 smmu0_int22_mask12; + ZXIC_UINT32 smmu0_int22_mask11; + ZXIC_UINT32 smmu0_int22_mask10; + ZXIC_UINT32 smmu0_int22_mask9; + ZXIC_UINT32 smmu0_int22_mask8; + ZXIC_UINT32 smmu0_int22_mask7; + ZXIC_UINT32 smmu0_int22_mask6; + ZXIC_UINT32 smmu0_int22_mask5; + ZXIC_UINT32 smmu0_int22_mask4; + ZXIC_UINT32 smmu0_int22_mask3; + ZXIC_UINT32 smmu0_int22_mask2; + ZXIC_UINT32 smmu0_int22_mask1; + ZXIC_UINT32 smmu0_int22_mask0; +}DPP_SMMU0_SMMU0_SMMU0_INT22_MASK_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int22_status_t +{ + ZXIC_UINT32 smmu0_int22_status31; + ZXIC_UINT32 smmu0_int22_status30; + ZXIC_UINT32 smmu0_int22_status29; + ZXIC_UINT32 smmu0_int22_status28; + ZXIC_UINT32 smmu0_int22_status27; + ZXIC_UINT32 smmu0_int22_status26; + ZXIC_UINT32 smmu0_int22_status25; + ZXIC_UINT32 smmu0_int22_status24; + ZXIC_UINT32 smmu0_int22_status23; + ZXIC_UINT32 smmu0_int22_status22; + ZXIC_UINT32 smmu0_int22_status21; + ZXIC_UINT32 smmu0_int22_status20; + ZXIC_UINT32 smmu0_int22_status19; + ZXIC_UINT32 smmu0_int22_status18; + ZXIC_UINT32 smmu0_int22_status17; + ZXIC_UINT32 smmu0_int22_status16; + ZXIC_UINT32 smmu0_int22_status15; + ZXIC_UINT32 smmu0_int22_status14; + ZXIC_UINT32 smmu0_int22_status13; + ZXIC_UINT32 smmu0_int22_status12; + ZXIC_UINT32 smmu0_int22_status11; + ZXIC_UINT32 smmu0_int22_status10; + ZXIC_UINT32 smmu0_int22_status9; + ZXIC_UINT32 smmu0_int22_status8; + ZXIC_UINT32 smmu0_int22_status7; + ZXIC_UINT32 smmu0_int22_status6; + ZXIC_UINT32 smmu0_int22_status5; + ZXIC_UINT32 smmu0_int22_status4; + ZXIC_UINT32 smmu0_int22_status3; + ZXIC_UINT32 smmu0_int22_status2; + ZXIC_UINT32 smmu0_int22_status1; + ZXIC_UINT32 smmu0_int22_status0; +}DPP_SMMU0_SMMU0_SMMU0_INT22_STATUS_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int23_en_t +{ + ZXIC_UINT32 smmu0_int23_en31; + ZXIC_UINT32 smmu0_int23_en30; + ZXIC_UINT32 smmu0_int23_en29; + ZXIC_UINT32 smmu0_int23_en28; + ZXIC_UINT32 smmu0_int23_en27; + ZXIC_UINT32 smmu0_int23_en26; + ZXIC_UINT32 smmu0_int23_en25; + ZXIC_UINT32 smmu0_int23_en24; + ZXIC_UINT32 smmu0_int23_en23; + ZXIC_UINT32 smmu0_int23_en22; + ZXIC_UINT32 smmu0_int23_en21; + ZXIC_UINT32 smmu0_int23_en20; + ZXIC_UINT32 smmu0_int23_en19; + ZXIC_UINT32 smmu0_int23_en18; + ZXIC_UINT32 smmu0_int23_en17; + ZXIC_UINT32 smmu0_int23_en16; + ZXIC_UINT32 smmu0_int23_en15; + ZXIC_UINT32 smmu0_int23_en14; + ZXIC_UINT32 smmu0_int23_en13; + ZXIC_UINT32 smmu0_int23_en12; + ZXIC_UINT32 smmu0_int23_en11; + ZXIC_UINT32 smmu0_int23_en10; + ZXIC_UINT32 smmu0_int23_en9; + ZXIC_UINT32 smmu0_int23_en8; + ZXIC_UINT32 smmu0_int23_en7; + ZXIC_UINT32 smmu0_int23_en6; + ZXIC_UINT32 smmu0_int23_en5; + ZXIC_UINT32 smmu0_int23_en4; + ZXIC_UINT32 smmu0_int23_en3; + ZXIC_UINT32 smmu0_int23_en2; + ZXIC_UINT32 smmu0_int23_en1; + ZXIC_UINT32 smmu0_int23_en0; +}DPP_SMMU0_SMMU0_SMMU0_INT23_EN_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int23_mask_t +{ + ZXIC_UINT32 smmu0_int23_mask31; + ZXIC_UINT32 smmu0_int23_mask30; + ZXIC_UINT32 smmu0_int23_mask29; + ZXIC_UINT32 smmu0_int23_mask28; + ZXIC_UINT32 smmu0_int23_mask27; + ZXIC_UINT32 smmu0_int23_mask26; + ZXIC_UINT32 smmu0_int23_mask25; + ZXIC_UINT32 smmu0_int23_mask24; + ZXIC_UINT32 smmu0_int23_mask23; + ZXIC_UINT32 smmu0_int23_mask22; + ZXIC_UINT32 smmu0_int23_mask21; + ZXIC_UINT32 smmu0_int23_mask20; + ZXIC_UINT32 smmu0_int23_mask19; + ZXIC_UINT32 smmu0_int23_mask18; + ZXIC_UINT32 smmu0_int23_mask17; + ZXIC_UINT32 smmu0_int23_mask16; + ZXIC_UINT32 smmu0_int23_mask15; + ZXIC_UINT32 smmu0_int23_mask14; + ZXIC_UINT32 smmu0_int23_mask13; + ZXIC_UINT32 smmu0_int23_mask12; + ZXIC_UINT32 smmu0_int23_mask11; + ZXIC_UINT32 smmu0_int23_mask10; + ZXIC_UINT32 smmu0_int23_mask9; + ZXIC_UINT32 smmu0_int23_mask8; + ZXIC_UINT32 smmu0_int23_mask7; + ZXIC_UINT32 smmu0_int23_mask6; + ZXIC_UINT32 smmu0_int23_mask5; + ZXIC_UINT32 smmu0_int23_mask4; + ZXIC_UINT32 smmu0_int23_mask3; + ZXIC_UINT32 smmu0_int23_mask2; + ZXIC_UINT32 smmu0_int23_mask1; + ZXIC_UINT32 smmu0_int23_mask0; +}DPP_SMMU0_SMMU0_SMMU0_INT23_MASK_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int23_status_t +{ + ZXIC_UINT32 smmu0_int23_status31; + ZXIC_UINT32 smmu0_int23_status30; + ZXIC_UINT32 smmu0_int23_status29; + ZXIC_UINT32 smmu0_int23_status28; + ZXIC_UINT32 smmu0_int23_status27; + ZXIC_UINT32 smmu0_int23_status26; + ZXIC_UINT32 smmu0_int23_status25; + ZXIC_UINT32 smmu0_int23_status24; + ZXIC_UINT32 smmu0_int23_status23; + ZXIC_UINT32 smmu0_int23_status22; + ZXIC_UINT32 smmu0_int23_status21; + ZXIC_UINT32 smmu0_int23_status20; + ZXIC_UINT32 smmu0_int23_status19; + ZXIC_UINT32 smmu0_int23_status18; + ZXIC_UINT32 smmu0_int23_status17; + ZXIC_UINT32 smmu0_int23_status16; + ZXIC_UINT32 smmu0_int23_status15; + ZXIC_UINT32 smmu0_int23_status14; + ZXIC_UINT32 smmu0_int23_status13; + ZXIC_UINT32 smmu0_int23_status12; + ZXIC_UINT32 smmu0_int23_status11; + ZXIC_UINT32 smmu0_int23_status10; + ZXIC_UINT32 smmu0_int23_status9; + ZXIC_UINT32 smmu0_int23_status8; + ZXIC_UINT32 smmu0_int23_status7; + ZXIC_UINT32 smmu0_int23_status6; + ZXIC_UINT32 smmu0_int23_status5; + ZXIC_UINT32 smmu0_int23_status4; + ZXIC_UINT32 smmu0_int23_status3; + ZXIC_UINT32 smmu0_int23_status2; + ZXIC_UINT32 smmu0_int23_status1; + ZXIC_UINT32 smmu0_int23_status0; +}DPP_SMMU0_SMMU0_SMMU0_INT23_STATUS_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int24_en_t +{ + ZXIC_UINT32 smmu0_int24_en31; + ZXIC_UINT32 smmu0_int24_en30; + ZXIC_UINT32 smmu0_int24_en29; + ZXIC_UINT32 smmu0_int24_en28; + ZXIC_UINT32 smmu0_int24_en27; + ZXIC_UINT32 smmu0_int24_en26; + ZXIC_UINT32 smmu0_int24_en25; + ZXIC_UINT32 smmu0_int24_en24; + ZXIC_UINT32 smmu0_int24_en23; + ZXIC_UINT32 smmu0_int24_en22; + ZXIC_UINT32 smmu0_int24_en21; + ZXIC_UINT32 smmu0_int24_en20; + ZXIC_UINT32 smmu0_int24_en19; + ZXIC_UINT32 smmu0_int24_en18; + ZXIC_UINT32 smmu0_int24_en17; + ZXIC_UINT32 smmu0_int24_en16; + ZXIC_UINT32 smmu0_int24_en15; + ZXIC_UINT32 smmu0_int24_en14; + ZXIC_UINT32 smmu0_int24_en13; + ZXIC_UINT32 smmu0_int24_en12; + ZXIC_UINT32 smmu0_int24_en11; + ZXIC_UINT32 smmu0_int24_en10; + ZXIC_UINT32 smmu0_int24_en9; + ZXIC_UINT32 smmu0_int24_en8; + ZXIC_UINT32 smmu0_int24_en7; + ZXIC_UINT32 smmu0_int24_en6; + ZXIC_UINT32 smmu0_int24_en5; + ZXIC_UINT32 smmu0_int24_en4; + ZXIC_UINT32 smmu0_int24_en3; + ZXIC_UINT32 smmu0_int24_en2; + ZXIC_UINT32 smmu0_int24_en1; + ZXIC_UINT32 smmu0_int24_en0; +}DPP_SMMU0_SMMU0_SMMU0_INT24_EN_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int24_mask_t +{ + ZXIC_UINT32 smmu0_int24_mask31; + ZXIC_UINT32 smmu0_int24_mask30; + ZXIC_UINT32 smmu0_int24_mask29; + ZXIC_UINT32 smmu0_int24_mask28; + ZXIC_UINT32 smmu0_int24_mask27; + ZXIC_UINT32 smmu0_int24_mask26; + ZXIC_UINT32 smmu0_int24_mask25; + ZXIC_UINT32 smmu0_int24_mask24; + ZXIC_UINT32 smmu0_int24_mask23; + ZXIC_UINT32 smmu0_int24_mask22; + ZXIC_UINT32 smmu0_int24_mask21; + ZXIC_UINT32 smmu0_int24_mask20; + ZXIC_UINT32 smmu0_int24_mask19; + ZXIC_UINT32 smmu0_int24_mask18; + ZXIC_UINT32 smmu0_int24_mask17; + ZXIC_UINT32 smmu0_int24_mask16; + ZXIC_UINT32 smmu0_int24_mask15; + ZXIC_UINT32 smmu0_int24_mask14; + ZXIC_UINT32 smmu0_int24_mask13; + ZXIC_UINT32 smmu0_int24_mask12; + ZXIC_UINT32 smmu0_int24_mask11; + ZXIC_UINT32 smmu0_int24_mask10; + ZXIC_UINT32 smmu0_int24_mask9; + ZXIC_UINT32 smmu0_int24_mask8; + ZXIC_UINT32 smmu0_int24_mask7; + ZXIC_UINT32 smmu0_int24_mask6; + ZXIC_UINT32 smmu0_int24_mask5; + ZXIC_UINT32 smmu0_int24_mask4; + ZXIC_UINT32 smmu0_int24_mask3; + ZXIC_UINT32 smmu0_int24_mask2; + ZXIC_UINT32 smmu0_int24_mask1; + ZXIC_UINT32 smmu0_int24_mask0; +}DPP_SMMU0_SMMU0_SMMU0_INT24_MASK_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int24_status_t +{ + ZXIC_UINT32 smmu0_int24_status31; + ZXIC_UINT32 smmu0_int24_status30; + ZXIC_UINT32 smmu0_int24_status29; + ZXIC_UINT32 smmu0_int24_status28; + ZXIC_UINT32 smmu0_int24_status27; + ZXIC_UINT32 smmu0_int24_status26; + ZXIC_UINT32 smmu0_int24_status25; + ZXIC_UINT32 smmu0_int24_status24; + ZXIC_UINT32 smmu0_int24_status23; + ZXIC_UINT32 smmu0_int24_status22; + ZXIC_UINT32 smmu0_int24_status21; + ZXIC_UINT32 smmu0_int24_status20; + ZXIC_UINT32 smmu0_int24_status19; + ZXIC_UINT32 smmu0_int24_status18; + ZXIC_UINT32 smmu0_int24_status17; + ZXIC_UINT32 smmu0_int24_status16; + ZXIC_UINT32 smmu0_int24_status15; + ZXIC_UINT32 smmu0_int24_status14; + ZXIC_UINT32 smmu0_int24_status13; + ZXIC_UINT32 smmu0_int24_status12; + ZXIC_UINT32 smmu0_int24_status11; + ZXIC_UINT32 smmu0_int24_status10; + ZXIC_UINT32 smmu0_int24_status9; + ZXIC_UINT32 smmu0_int24_status8; + ZXIC_UINT32 smmu0_int24_status7; + ZXIC_UINT32 smmu0_int24_status6; + ZXIC_UINT32 smmu0_int24_status5; + ZXIC_UINT32 smmu0_int24_status4; + ZXIC_UINT32 smmu0_int24_status3; + ZXIC_UINT32 smmu0_int24_status2; + ZXIC_UINT32 smmu0_int24_status1; + ZXIC_UINT32 smmu0_int24_status0; +}DPP_SMMU0_SMMU0_SMMU0_INT24_STATUS_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int25_en_t +{ + ZXIC_UINT32 smmu0_int25_en31; + ZXIC_UINT32 smmu0_int25_en30; + ZXIC_UINT32 smmu0_int25_en29; + ZXIC_UINT32 smmu0_int25_en28; + ZXIC_UINT32 smmu0_int25_en27; + ZXIC_UINT32 smmu0_int25_en26; + ZXIC_UINT32 smmu0_int25_en25; + ZXIC_UINT32 smmu0_int25_en24; + ZXIC_UINT32 smmu0_int25_en23; + ZXIC_UINT32 smmu0_int25_en22; + ZXIC_UINT32 smmu0_int25_en21; + ZXIC_UINT32 smmu0_int25_en20; + ZXIC_UINT32 smmu0_int25_en19; + ZXIC_UINT32 smmu0_int25_en18; + ZXIC_UINT32 smmu0_int25_en17; + ZXIC_UINT32 smmu0_int25_en16; + ZXIC_UINT32 smmu0_int25_en15; + ZXIC_UINT32 smmu0_int25_en14; + ZXIC_UINT32 smmu0_int25_en13; + ZXIC_UINT32 smmu0_int25_en12; + ZXIC_UINT32 smmu0_int25_en11; + ZXIC_UINT32 smmu0_int25_en10; + ZXIC_UINT32 smmu0_int25_en9; + ZXIC_UINT32 smmu0_int25_en8; + ZXIC_UINT32 smmu0_int25_en7; + ZXIC_UINT32 smmu0_int25_en6; + ZXIC_UINT32 smmu0_int25_en5; + ZXIC_UINT32 smmu0_int25_en4; + ZXIC_UINT32 smmu0_int25_en3; + ZXIC_UINT32 smmu0_int25_en2; + ZXIC_UINT32 smmu0_int25_en1; + ZXIC_UINT32 smmu0_int25_en0; +}DPP_SMMU0_SMMU0_SMMU0_INT25_EN_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int25_mask_t +{ + ZXIC_UINT32 smmu0_int25_mask31; + ZXIC_UINT32 smmu0_int25_mask30; + ZXIC_UINT32 smmu0_int25_mask29; + ZXIC_UINT32 smmu0_int25_mask28; + ZXIC_UINT32 smmu0_int25_mask27; + ZXIC_UINT32 smmu0_int25_mask26; + ZXIC_UINT32 smmu0_int25_mask25; + ZXIC_UINT32 smmu0_int25_mask24; + ZXIC_UINT32 smmu0_int25_mask23; + ZXIC_UINT32 smmu0_int25_mask22; + ZXIC_UINT32 smmu0_int25_mask21; + ZXIC_UINT32 smmu0_int25_mask20; + ZXIC_UINT32 smmu0_int25_mask19; + ZXIC_UINT32 smmu0_int25_mask18; + ZXIC_UINT32 smmu0_int25_mask17; + ZXIC_UINT32 smmu0_int25_mask16; + ZXIC_UINT32 smmu0_int25_mask15; + ZXIC_UINT32 smmu0_int25_mask14; + ZXIC_UINT32 smmu0_int25_mask13; + ZXIC_UINT32 smmu0_int25_mask12; + ZXIC_UINT32 smmu0_int25_mask11; + ZXIC_UINT32 smmu0_int25_mask10; + ZXIC_UINT32 smmu0_int25_mask9; + ZXIC_UINT32 smmu0_int25_mask8; + ZXIC_UINT32 smmu0_int25_mask7; + ZXIC_UINT32 smmu0_int25_mask6; + ZXIC_UINT32 smmu0_int25_mask5; + ZXIC_UINT32 smmu0_int25_mask4; + ZXIC_UINT32 smmu0_int25_mask3; + ZXIC_UINT32 smmu0_int25_mask2; + ZXIC_UINT32 smmu0_int25_mask1; + ZXIC_UINT32 smmu0_int25_mask0; +}DPP_SMMU0_SMMU0_SMMU0_INT25_MASK_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int25_status_t +{ + ZXIC_UINT32 smmu0_int25_status31; + ZXIC_UINT32 smmu0_int25_status30; + ZXIC_UINT32 smmu0_int25_status29; + ZXIC_UINT32 smmu0_int25_status28; + ZXIC_UINT32 smmu0_int25_status27; + ZXIC_UINT32 smmu0_int25_status26; + ZXIC_UINT32 smmu0_int25_status25; + ZXIC_UINT32 smmu0_int25_status24; + ZXIC_UINT32 smmu0_int25_status23; + ZXIC_UINT32 smmu0_int25_status22; + ZXIC_UINT32 smmu0_int25_status21; + ZXIC_UINT32 smmu0_int25_status20; + ZXIC_UINT32 smmu0_int25_status19; + ZXIC_UINT32 smmu0_int25_status18; + ZXIC_UINT32 smmu0_int25_status17; + ZXIC_UINT32 smmu0_int25_status16; + ZXIC_UINT32 smmu0_int25_status15; + ZXIC_UINT32 smmu0_int25_status14; + ZXIC_UINT32 smmu0_int25_status13; + ZXIC_UINT32 smmu0_int25_status12; + ZXIC_UINT32 smmu0_int25_status11; + ZXIC_UINT32 smmu0_int25_status10; + ZXIC_UINT32 smmu0_int25_status9; + ZXIC_UINT32 smmu0_int25_status8; + ZXIC_UINT32 smmu0_int25_status7; + ZXIC_UINT32 smmu0_int25_status6; + ZXIC_UINT32 smmu0_int25_status5; + ZXIC_UINT32 smmu0_int25_status4; + ZXIC_UINT32 smmu0_int25_status3; + ZXIC_UINT32 smmu0_int25_status2; + ZXIC_UINT32 smmu0_int25_status1; + ZXIC_UINT32 smmu0_int25_status0; +}DPP_SMMU0_SMMU0_SMMU0_INT25_STATUS_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int26_en_t +{ + ZXIC_UINT32 smmu0_int26_en31; + ZXIC_UINT32 smmu0_int26_en30; + ZXIC_UINT32 smmu0_int26_en29; + ZXIC_UINT32 smmu0_int26_en28; + ZXIC_UINT32 smmu0_int26_en27; + ZXIC_UINT32 smmu0_int26_en26; + ZXIC_UINT32 smmu0_int26_en25; + ZXIC_UINT32 smmu0_int26_en24; + ZXIC_UINT32 smmu0_int26_en23; + ZXIC_UINT32 smmu0_int26_en22; + ZXIC_UINT32 smmu0_int26_en21; + ZXIC_UINT32 smmu0_int26_en20; + ZXIC_UINT32 smmu0_int26_en19; + ZXIC_UINT32 smmu0_int26_en18; + ZXIC_UINT32 smmu0_int26_en17; + ZXIC_UINT32 smmu0_int26_en16; + ZXIC_UINT32 smmu0_int26_en15; + ZXIC_UINT32 smmu0_int26_en14; + ZXIC_UINT32 smmu0_int26_en13; + ZXIC_UINT32 smmu0_int26_en12; + ZXIC_UINT32 smmu0_int26_en11; + ZXIC_UINT32 smmu0_int26_en10; + ZXIC_UINT32 smmu0_int26_en9; + ZXIC_UINT32 smmu0_int26_en8; + ZXIC_UINT32 smmu0_int26_en7; + ZXIC_UINT32 smmu0_int26_en6; + ZXIC_UINT32 smmu0_int26_en5; + ZXIC_UINT32 smmu0_int26_en4; + ZXIC_UINT32 smmu0_int26_en3; + ZXIC_UINT32 smmu0_int26_en2; + ZXIC_UINT32 smmu0_int26_en1; + ZXIC_UINT32 smmu0_int26_en0; +}DPP_SMMU0_SMMU0_SMMU0_INT26_EN_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int26_mask_t +{ + ZXIC_UINT32 smmu0_int26_mask31; + ZXIC_UINT32 smmu0_int26_mask30; + ZXIC_UINT32 smmu0_int26_mask29; + ZXIC_UINT32 smmu0_int26_mask28; + ZXIC_UINT32 smmu0_int26_mask27; + ZXIC_UINT32 smmu0_int26_mask26; + ZXIC_UINT32 smmu0_int26_mask25; + ZXIC_UINT32 smmu0_int26_mask24; + ZXIC_UINT32 smmu0_int26_mask23; + ZXIC_UINT32 smmu0_int26_mask22; + ZXIC_UINT32 smmu0_int26_mask21; + ZXIC_UINT32 smmu0_int26_mask20; + ZXIC_UINT32 smmu0_int26_mask19; + ZXIC_UINT32 smmu0_int26_mask18; + ZXIC_UINT32 smmu0_int26_mask17; + ZXIC_UINT32 smmu0_int26_mask16; + ZXIC_UINT32 smmu0_int26_mask15; + ZXIC_UINT32 smmu0_int26_mask14; + ZXIC_UINT32 smmu0_int26_mask13; + ZXIC_UINT32 smmu0_int26_mask12; + ZXIC_UINT32 smmu0_int26_mask11; + ZXIC_UINT32 smmu0_int26_mask10; + ZXIC_UINT32 smmu0_int26_mask9; + ZXIC_UINT32 smmu0_int26_mask8; + ZXIC_UINT32 smmu0_int26_mask7; + ZXIC_UINT32 smmu0_int26_mask6; + ZXIC_UINT32 smmu0_int26_mask5; + ZXIC_UINT32 smmu0_int26_mask4; + ZXIC_UINT32 smmu0_int26_mask3; + ZXIC_UINT32 smmu0_int26_mask2; + ZXIC_UINT32 smmu0_int26_mask1; + ZXIC_UINT32 smmu0_int26_mask0; +}DPP_SMMU0_SMMU0_SMMU0_INT26_MASK_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int26_status_t +{ + ZXIC_UINT32 smmu0_int26_status31; + ZXIC_UINT32 smmu0_int26_status30; + ZXIC_UINT32 smmu0_int26_status29; + ZXIC_UINT32 smmu0_int26_status28; + ZXIC_UINT32 smmu0_int26_status27; + ZXIC_UINT32 smmu0_int26_status26; + ZXIC_UINT32 smmu0_int26_status25; + ZXIC_UINT32 smmu0_int26_status24; + ZXIC_UINT32 smmu0_int26_status23; + ZXIC_UINT32 smmu0_int26_status22; + ZXIC_UINT32 smmu0_int26_status21; + ZXIC_UINT32 smmu0_int26_status20; + ZXIC_UINT32 smmu0_int26_status19; + ZXIC_UINT32 smmu0_int26_status18; + ZXIC_UINT32 smmu0_int26_status17; + ZXIC_UINT32 smmu0_int26_status16; + ZXIC_UINT32 smmu0_int26_status15; + ZXIC_UINT32 smmu0_int26_status14; + ZXIC_UINT32 smmu0_int26_status13; + ZXIC_UINT32 smmu0_int26_status12; + ZXIC_UINT32 smmu0_int26_status11; + ZXIC_UINT32 smmu0_int26_status10; + ZXIC_UINT32 smmu0_int26_status9; + ZXIC_UINT32 smmu0_int26_status8; + ZXIC_UINT32 smmu0_int26_status7; + ZXIC_UINT32 smmu0_int26_status6; + ZXIC_UINT32 smmu0_int26_status5; + ZXIC_UINT32 smmu0_int26_status4; + ZXIC_UINT32 smmu0_int26_status3; + ZXIC_UINT32 smmu0_int26_status2; + ZXIC_UINT32 smmu0_int26_status1; + ZXIC_UINT32 smmu0_int26_status0; +}DPP_SMMU0_SMMU0_SMMU0_INT26_STATUS_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int27_en_t +{ + ZXIC_UINT32 smmu0_int27_en31; + ZXIC_UINT32 smmu0_int27_en30; + ZXIC_UINT32 smmu0_int27_en29; + ZXIC_UINT32 smmu0_int27_en28; + ZXIC_UINT32 smmu0_int27_en27; + ZXIC_UINT32 smmu0_int27_en26; + ZXIC_UINT32 smmu0_int27_en25; + ZXIC_UINT32 smmu0_int27_en24; + ZXIC_UINT32 smmu0_int27_en23; + ZXIC_UINT32 smmu0_int27_en22; + ZXIC_UINT32 smmu0_int27_en21; + ZXIC_UINT32 smmu0_int27_en20; + ZXIC_UINT32 smmu0_int27_en19; + ZXIC_UINT32 smmu0_int27_en18; + ZXIC_UINT32 smmu0_int27_en17; + ZXIC_UINT32 smmu0_int27_en16; + ZXIC_UINT32 smmu0_int27_en15; + ZXIC_UINT32 smmu0_int27_en14; + ZXIC_UINT32 smmu0_int27_en13; + ZXIC_UINT32 smmu0_int27_en12; + ZXIC_UINT32 smmu0_int27_en11; + ZXIC_UINT32 smmu0_int27_en10; + ZXIC_UINT32 smmu0_int27_en9; + ZXIC_UINT32 smmu0_int27_en8; + ZXIC_UINT32 smmu0_int27_en7; + ZXIC_UINT32 smmu0_int27_en6; + ZXIC_UINT32 smmu0_int27_en5; + ZXIC_UINT32 smmu0_int27_en4; + ZXIC_UINT32 smmu0_int27_en3; + ZXIC_UINT32 smmu0_int27_en2; + ZXIC_UINT32 smmu0_int27_en1; + ZXIC_UINT32 smmu0_int27_en0; +}DPP_SMMU0_SMMU0_SMMU0_INT27_EN_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int27_mask_t +{ + ZXIC_UINT32 smmu0_int27_mask31; + ZXIC_UINT32 smmu0_int27_mask30; + ZXIC_UINT32 smmu0_int27_mask29; + ZXIC_UINT32 smmu0_int27_mask28; + ZXIC_UINT32 smmu0_int27_mask27; + ZXIC_UINT32 smmu0_int27_mask26; + ZXIC_UINT32 smmu0_int27_mask25; + ZXIC_UINT32 smmu0_int27_mask24; + ZXIC_UINT32 smmu0_int27_mask23; + ZXIC_UINT32 smmu0_int27_mask22; + ZXIC_UINT32 smmu0_int27_mask21; + ZXIC_UINT32 smmu0_int27_mask20; + ZXIC_UINT32 smmu0_int27_mask19; + ZXIC_UINT32 smmu0_int27_mask18; + ZXIC_UINT32 smmu0_int27_mask17; + ZXIC_UINT32 smmu0_int27_mask16; + ZXIC_UINT32 smmu0_int27_mask15; + ZXIC_UINT32 smmu0_int27_mask14; + ZXIC_UINT32 smmu0_int27_mask13; + ZXIC_UINT32 smmu0_int27_mask12; + ZXIC_UINT32 smmu0_int27_mask11; + ZXIC_UINT32 smmu0_int27_mask10; + ZXIC_UINT32 smmu0_int27_mask9; + ZXIC_UINT32 smmu0_int27_mask8; + ZXIC_UINT32 smmu0_int27_mask7; + ZXIC_UINT32 smmu0_int27_mask6; + ZXIC_UINT32 smmu0_int27_mask5; + ZXIC_UINT32 smmu0_int27_mask4; + ZXIC_UINT32 smmu0_int27_mask3; + ZXIC_UINT32 smmu0_int27_mask2; + ZXIC_UINT32 smmu0_int27_mask1; + ZXIC_UINT32 smmu0_int27_mask0; +}DPP_SMMU0_SMMU0_SMMU0_INT27_MASK_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int27_status_t +{ + ZXIC_UINT32 smmu0_int27_status31; + ZXIC_UINT32 smmu0_int27_status30; + ZXIC_UINT32 smmu0_int27_status29; + ZXIC_UINT32 smmu0_int27_status28; + ZXIC_UINT32 smmu0_int27_status27; + ZXIC_UINT32 smmu0_int27_status26; + ZXIC_UINT32 smmu0_int27_status25; + ZXIC_UINT32 smmu0_int27_status24; + ZXIC_UINT32 smmu0_int27_status23; + ZXIC_UINT32 smmu0_int27_status22; + ZXIC_UINT32 smmu0_int27_status21; + ZXIC_UINT32 smmu0_int27_status20; + ZXIC_UINT32 smmu0_int27_status19; + ZXIC_UINT32 smmu0_int27_status18; + ZXIC_UINT32 smmu0_int27_status17; + ZXIC_UINT32 smmu0_int27_status16; + ZXIC_UINT32 smmu0_int27_status15; + ZXIC_UINT32 smmu0_int27_status14; + ZXIC_UINT32 smmu0_int27_status13; + ZXIC_UINT32 smmu0_int27_status12; + ZXIC_UINT32 smmu0_int27_status11; + ZXIC_UINT32 smmu0_int27_status10; + ZXIC_UINT32 smmu0_int27_status9; + ZXIC_UINT32 smmu0_int27_status8; + ZXIC_UINT32 smmu0_int27_status7; + ZXIC_UINT32 smmu0_int27_status6; + ZXIC_UINT32 smmu0_int27_status5; + ZXIC_UINT32 smmu0_int27_status4; + ZXIC_UINT32 smmu0_int27_status3; + ZXIC_UINT32 smmu0_int27_status2; + ZXIC_UINT32 smmu0_int27_status1; + ZXIC_UINT32 smmu0_int27_status0; +}DPP_SMMU0_SMMU0_SMMU0_INT27_STATUS_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int28_en_t +{ + ZXIC_UINT32 smmu0_int28_en31; + ZXIC_UINT32 smmu0_int28_en30; + ZXIC_UINT32 smmu0_int28_en29; + ZXIC_UINT32 smmu0_int28_en28; + ZXIC_UINT32 smmu0_int28_en27; + ZXIC_UINT32 smmu0_int28_en26; + ZXIC_UINT32 smmu0_int28_en25; + ZXIC_UINT32 smmu0_int28_en24; + ZXIC_UINT32 smmu0_int28_en23; + ZXIC_UINT32 smmu0_int28_en22; + ZXIC_UINT32 smmu0_int28_en21; + ZXIC_UINT32 smmu0_int28_en20; + ZXIC_UINT32 smmu0_int28_en19; + ZXIC_UINT32 smmu0_int28_en18; + ZXIC_UINT32 smmu0_int28_en17; + ZXIC_UINT32 smmu0_int28_en16; + ZXIC_UINT32 smmu0_int28_en15; + ZXIC_UINT32 smmu0_int28_en14; + ZXIC_UINT32 smmu0_int28_en13; + ZXIC_UINT32 smmu0_int28_en12; + ZXIC_UINT32 smmu0_int28_en11; + ZXIC_UINT32 smmu0_int28_en10; + ZXIC_UINT32 smmu0_int28_en9; + ZXIC_UINT32 smmu0_int28_en8; + ZXIC_UINT32 smmu0_int28_en7; + ZXIC_UINT32 smmu0_int28_en6; + ZXIC_UINT32 smmu0_int28_en5; + ZXIC_UINT32 smmu0_int28_en4; + ZXIC_UINT32 smmu0_int28_en3; + ZXIC_UINT32 smmu0_int28_en2; + ZXIC_UINT32 smmu0_int28_en1; + ZXIC_UINT32 smmu0_int28_en0; +}DPP_SMMU0_SMMU0_SMMU0_INT28_EN_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int28_mask_t +{ + ZXIC_UINT32 smmu0_int28_mask31; + ZXIC_UINT32 smmu0_int28_mask30; + ZXIC_UINT32 smmu0_int28_mask29; + ZXIC_UINT32 smmu0_int28_mask28; + ZXIC_UINT32 smmu0_int28_mask27; + ZXIC_UINT32 smmu0_int28_mask26; + ZXIC_UINT32 smmu0_int28_mask25; + ZXIC_UINT32 smmu0_int28_mask24; + ZXIC_UINT32 smmu0_int28_mask23; + ZXIC_UINT32 smmu0_int28_mask22; + ZXIC_UINT32 smmu0_int28_mask21; + ZXIC_UINT32 smmu0_int28_mask20; + ZXIC_UINT32 smmu0_int28_mask19; + ZXIC_UINT32 smmu0_int28_mask18; + ZXIC_UINT32 smmu0_int28_mask17; + ZXIC_UINT32 smmu0_int28_mask16; + ZXIC_UINT32 smmu0_int28_mask15; + ZXIC_UINT32 smmu0_int28_mask14; + ZXIC_UINT32 smmu0_int28_mask13; + ZXIC_UINT32 smmu0_int28_mask12; + ZXIC_UINT32 smmu0_int28_mask11; + ZXIC_UINT32 smmu0_int28_mask10; + ZXIC_UINT32 smmu0_int28_mask9; + ZXIC_UINT32 smmu0_int28_mask8; + ZXIC_UINT32 smmu0_int28_mask7; + ZXIC_UINT32 smmu0_int28_mask6; + ZXIC_UINT32 smmu0_int28_mask5; + ZXIC_UINT32 smmu0_int28_mask4; + ZXIC_UINT32 smmu0_int28_mask3; + ZXIC_UINT32 smmu0_int28_mask2; + ZXIC_UINT32 smmu0_int28_mask1; + ZXIC_UINT32 smmu0_int28_mask0; +}DPP_SMMU0_SMMU0_SMMU0_INT28_MASK_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int28_status_t +{ + ZXIC_UINT32 smmu0_int28_status31; + ZXIC_UINT32 smmu0_int28_status30; + ZXIC_UINT32 smmu0_int28_status29; + ZXIC_UINT32 smmu0_int28_status28; + ZXIC_UINT32 smmu0_int28_status27; + ZXIC_UINT32 smmu0_int28_status26; + ZXIC_UINT32 smmu0_int28_status25; + ZXIC_UINT32 smmu0_int28_status24; + ZXIC_UINT32 smmu0_int28_status23; + ZXIC_UINT32 smmu0_int28_status22; + ZXIC_UINT32 smmu0_int28_status21; + ZXIC_UINT32 smmu0_int28_status20; + ZXIC_UINT32 smmu0_int28_status19; + ZXIC_UINT32 smmu0_int28_status18; + ZXIC_UINT32 smmu0_int28_status17; + ZXIC_UINT32 smmu0_int28_status16; + ZXIC_UINT32 smmu0_int28_status15; + ZXIC_UINT32 smmu0_int28_status14; + ZXIC_UINT32 smmu0_int28_status13; + ZXIC_UINT32 smmu0_int28_status12; + ZXIC_UINT32 smmu0_int28_status11; + ZXIC_UINT32 smmu0_int28_status10; + ZXIC_UINT32 smmu0_int28_status9; + ZXIC_UINT32 smmu0_int28_status8; + ZXIC_UINT32 smmu0_int28_status7; + ZXIC_UINT32 smmu0_int28_status6; + ZXIC_UINT32 smmu0_int28_status5; + ZXIC_UINT32 smmu0_int28_status4; + ZXIC_UINT32 smmu0_int28_status3; + ZXIC_UINT32 smmu0_int28_status2; + ZXIC_UINT32 smmu0_int28_status1; + ZXIC_UINT32 smmu0_int28_status0; +}DPP_SMMU0_SMMU0_SMMU0_INT28_STATUS_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int29_en_t +{ + ZXIC_UINT32 smmu0_int29_en31; + ZXIC_UINT32 smmu0_int29_en30; + ZXIC_UINT32 smmu0_int29_en29; + ZXIC_UINT32 smmu0_int29_en28; + ZXIC_UINT32 smmu0_int29_en27; + ZXIC_UINT32 smmu0_int29_en26; + ZXIC_UINT32 smmu0_int29_en25; + ZXIC_UINT32 smmu0_int29_en24; + ZXIC_UINT32 smmu0_int29_en23; + ZXIC_UINT32 smmu0_int29_en22; + ZXIC_UINT32 smmu0_int29_en21; + ZXIC_UINT32 smmu0_int29_en20; + ZXIC_UINT32 smmu0_int29_en19; + ZXIC_UINT32 smmu0_int29_en18; + ZXIC_UINT32 smmu0_int29_en17; + ZXIC_UINT32 smmu0_int29_en16; + ZXIC_UINT32 smmu0_int29_en15; + ZXIC_UINT32 smmu0_int29_en14; + ZXIC_UINT32 smmu0_int29_en13; + ZXIC_UINT32 smmu0_int29_en12; + ZXIC_UINT32 smmu0_int29_en11; + ZXIC_UINT32 smmu0_int29_en10; + ZXIC_UINT32 smmu0_int29_en9; + ZXIC_UINT32 smmu0_int29_en8; + ZXIC_UINT32 smmu0_int29_en7; + ZXIC_UINT32 smmu0_int29_en6; + ZXIC_UINT32 smmu0_int29_en5; + ZXIC_UINT32 smmu0_int29_en4; + ZXIC_UINT32 smmu0_int29_en3; + ZXIC_UINT32 smmu0_int29_en2; + ZXIC_UINT32 smmu0_int29_en1; + ZXIC_UINT32 smmu0_int29_en0; +}DPP_SMMU0_SMMU0_SMMU0_INT29_EN_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int29_mask_t +{ + ZXIC_UINT32 smmu0_int29_mask31; + ZXIC_UINT32 smmu0_int29_mask30; + ZXIC_UINT32 smmu0_int29_mask29; + ZXIC_UINT32 smmu0_int29_mask28; + ZXIC_UINT32 smmu0_int29_mask27; + ZXIC_UINT32 smmu0_int29_mask26; + ZXIC_UINT32 smmu0_int29_mask25; + ZXIC_UINT32 smmu0_int29_mask24; + ZXIC_UINT32 smmu0_int29_mask23; + ZXIC_UINT32 smmu0_int29_mask22; + ZXIC_UINT32 smmu0_int29_mask21; + ZXIC_UINT32 smmu0_int29_mask20; + ZXIC_UINT32 smmu0_int29_mask19; + ZXIC_UINT32 smmu0_int29_mask18; + ZXIC_UINT32 smmu0_int29_mask17; + ZXIC_UINT32 smmu0_int29_mask16; + ZXIC_UINT32 smmu0_int29_mask15; + ZXIC_UINT32 smmu0_int29_mask14; + ZXIC_UINT32 smmu0_int29_mask13; + ZXIC_UINT32 smmu0_int29_mask12; + ZXIC_UINT32 smmu0_int29_mask11; + ZXIC_UINT32 smmu0_int29_mask10; + ZXIC_UINT32 smmu0_int29_mask9; + ZXIC_UINT32 smmu0_int29_mask8; + ZXIC_UINT32 smmu0_int29_mask7; + ZXIC_UINT32 smmu0_int29_mask6; + ZXIC_UINT32 smmu0_int29_mask5; + ZXIC_UINT32 smmu0_int29_mask4; + ZXIC_UINT32 smmu0_int29_mask3; + ZXIC_UINT32 smmu0_int29_mask2; + ZXIC_UINT32 smmu0_int29_mask1; + ZXIC_UINT32 smmu0_int29_mask0; +}DPP_SMMU0_SMMU0_SMMU0_INT29_MASK_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int29_status_t +{ + ZXIC_UINT32 smmu0_int29_status31; + ZXIC_UINT32 smmu0_int29_status30; + ZXIC_UINT32 smmu0_int29_status29; + ZXIC_UINT32 smmu0_int29_status28; + ZXIC_UINT32 smmu0_int29_status27; + ZXIC_UINT32 smmu0_int29_status26; + ZXIC_UINT32 smmu0_int29_status25; + ZXIC_UINT32 smmu0_int29_status24; + ZXIC_UINT32 smmu0_int29_status23; + ZXIC_UINT32 smmu0_int29_status22; + ZXIC_UINT32 smmu0_int29_status21; + ZXIC_UINT32 smmu0_int29_status20; + ZXIC_UINT32 smmu0_int29_status19; + ZXIC_UINT32 smmu0_int29_status18; + ZXIC_UINT32 smmu0_int29_status17; + ZXIC_UINT32 smmu0_int29_status16; + ZXIC_UINT32 smmu0_int29_status15; + ZXIC_UINT32 smmu0_int29_status14; + ZXIC_UINT32 smmu0_int29_status13; + ZXIC_UINT32 smmu0_int29_status12; + ZXIC_UINT32 smmu0_int29_status11; + ZXIC_UINT32 smmu0_int29_status10; + ZXIC_UINT32 smmu0_int29_status9; + ZXIC_UINT32 smmu0_int29_status8; + ZXIC_UINT32 smmu0_int29_status7; + ZXIC_UINT32 smmu0_int29_status6; + ZXIC_UINT32 smmu0_int29_status5; + ZXIC_UINT32 smmu0_int29_status4; + ZXIC_UINT32 smmu0_int29_status3; + ZXIC_UINT32 smmu0_int29_status2; + ZXIC_UINT32 smmu0_int29_status1; + ZXIC_UINT32 smmu0_int29_status0; +}DPP_SMMU0_SMMU0_SMMU0_INT29_STATUS_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int30_en_t +{ + ZXIC_UINT32 smmu0_int30_en31; + ZXIC_UINT32 smmu0_int30_en30; + ZXIC_UINT32 smmu0_int30_en29; + ZXIC_UINT32 smmu0_int30_en28; + ZXIC_UINT32 smmu0_int30_en27; + ZXIC_UINT32 smmu0_int30_en26; + ZXIC_UINT32 smmu0_int30_en25; + ZXIC_UINT32 smmu0_int30_en24; + ZXIC_UINT32 smmu0_int30_en23; + ZXIC_UINT32 smmu0_int30_en22; + ZXIC_UINT32 smmu0_int30_en21; + ZXIC_UINT32 smmu0_int30_en20; + ZXIC_UINT32 smmu0_int30_en19; + ZXIC_UINT32 smmu0_int30_en18; + ZXIC_UINT32 smmu0_int30_en17; + ZXIC_UINT32 smmu0_int30_en16; + ZXIC_UINT32 smmu0_int30_en15; + ZXIC_UINT32 smmu0_int30_en14; + ZXIC_UINT32 smmu0_int30_en13; + ZXIC_UINT32 smmu0_int30_en12; + ZXIC_UINT32 smmu0_int30_en11; + ZXIC_UINT32 smmu0_int30_en10; + ZXIC_UINT32 smmu0_int30_en9; + ZXIC_UINT32 smmu0_int30_en8; + ZXIC_UINT32 smmu0_int30_en7; + ZXIC_UINT32 smmu0_int30_en6; + ZXIC_UINT32 smmu0_int30_en5; + ZXIC_UINT32 smmu0_int30_en4; + ZXIC_UINT32 smmu0_int30_en3; + ZXIC_UINT32 smmu0_int30_en2; + ZXIC_UINT32 smmu0_int30_en1; + ZXIC_UINT32 smmu0_int30_en0; +}DPP_SMMU0_SMMU0_SMMU0_INT30_EN_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int30_mask_t +{ + ZXIC_UINT32 smmu0_int30_mask31; + ZXIC_UINT32 smmu0_int30_mask30; + ZXIC_UINT32 smmu0_int30_mask29; + ZXIC_UINT32 smmu0_int30_mask28; + ZXIC_UINT32 smmu0_int30_mask27; + ZXIC_UINT32 smmu0_int30_mask26; + ZXIC_UINT32 smmu0_int30_mask25; + ZXIC_UINT32 smmu0_int30_mask24; + ZXIC_UINT32 smmu0_int30_mask23; + ZXIC_UINT32 smmu0_int30_mask22; + ZXIC_UINT32 smmu0_int30_mask21; + ZXIC_UINT32 smmu0_int30_mask20; + ZXIC_UINT32 smmu0_int30_mask19; + ZXIC_UINT32 smmu0_int30_mask18; + ZXIC_UINT32 smmu0_int30_mask17; + ZXIC_UINT32 smmu0_int30_mask16; + ZXIC_UINT32 smmu0_int30_mask15; + ZXIC_UINT32 smmu0_int30_mask14; + ZXIC_UINT32 smmu0_int30_mask13; + ZXIC_UINT32 smmu0_int30_mask12; + ZXIC_UINT32 smmu0_int30_mask11; + ZXIC_UINT32 smmu0_int30_mask10; + ZXIC_UINT32 smmu0_int30_mask9; + ZXIC_UINT32 smmu0_int30_mask8; + ZXIC_UINT32 smmu0_int30_mask7; + ZXIC_UINT32 smmu0_int30_mask6; + ZXIC_UINT32 smmu0_int30_mask5; + ZXIC_UINT32 smmu0_int30_mask4; + ZXIC_UINT32 smmu0_int30_mask3; + ZXIC_UINT32 smmu0_int30_mask2; + ZXIC_UINT32 smmu0_int30_mask1; + ZXIC_UINT32 smmu0_int30_mask0; +}DPP_SMMU0_SMMU0_SMMU0_INT30_MASK_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int30_status_t +{ + ZXIC_UINT32 smmu0_int30_status31; + ZXIC_UINT32 smmu0_int30_status30; + ZXIC_UINT32 smmu0_int30_status29; + ZXIC_UINT32 smmu0_int30_status28; + ZXIC_UINT32 smmu0_int30_status27; + ZXIC_UINT32 smmu0_int30_status26; + ZXIC_UINT32 smmu0_int30_status25; + ZXIC_UINT32 smmu0_int30_status24; + ZXIC_UINT32 smmu0_int30_status23; + ZXIC_UINT32 smmu0_int30_status22; + ZXIC_UINT32 smmu0_int30_status21; + ZXIC_UINT32 smmu0_int30_status20; + ZXIC_UINT32 smmu0_int30_status19; + ZXIC_UINT32 smmu0_int30_status18; + ZXIC_UINT32 smmu0_int30_status17; + ZXIC_UINT32 smmu0_int30_status16; + ZXIC_UINT32 smmu0_int30_status15; + ZXIC_UINT32 smmu0_int30_status14; + ZXIC_UINT32 smmu0_int30_status13; + ZXIC_UINT32 smmu0_int30_status12; + ZXIC_UINT32 smmu0_int30_status11; + ZXIC_UINT32 smmu0_int30_status10; + ZXIC_UINT32 smmu0_int30_status9; + ZXIC_UINT32 smmu0_int30_status8; + ZXIC_UINT32 smmu0_int30_status7; + ZXIC_UINT32 smmu0_int30_status6; + ZXIC_UINT32 smmu0_int30_status5; + ZXIC_UINT32 smmu0_int30_status4; + ZXIC_UINT32 smmu0_int30_status3; + ZXIC_UINT32 smmu0_int30_status2; + ZXIC_UINT32 smmu0_int30_status1; + ZXIC_UINT32 smmu0_int30_status0; +}DPP_SMMU0_SMMU0_SMMU0_INT30_STATUS_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int31_en_t +{ + ZXIC_UINT32 smmu0_int31_en31; + ZXIC_UINT32 smmu0_int31_en30; + ZXIC_UINT32 smmu0_int31_en29; + ZXIC_UINT32 smmu0_int31_en28; + ZXIC_UINT32 smmu0_int31_en27; + ZXIC_UINT32 smmu0_int31_en26; + ZXIC_UINT32 smmu0_int31_en25; + ZXIC_UINT32 smmu0_int31_en24; + ZXIC_UINT32 smmu0_int31_en23; + ZXIC_UINT32 smmu0_int31_en22; + ZXIC_UINT32 smmu0_int31_en21; + ZXIC_UINT32 smmu0_int31_en20; + ZXIC_UINT32 smmu0_int31_en19; + ZXIC_UINT32 smmu0_int31_en18; + ZXIC_UINT32 smmu0_int31_en17; + ZXIC_UINT32 smmu0_int31_en16; + ZXIC_UINT32 smmu0_int31_en15; + ZXIC_UINT32 smmu0_int31_en14; + ZXIC_UINT32 smmu0_int31_en13; + ZXIC_UINT32 smmu0_int31_en12; + ZXIC_UINT32 smmu0_int31_en11; + ZXIC_UINT32 smmu0_int31_en10; + ZXIC_UINT32 smmu0_int31_en9; + ZXIC_UINT32 smmu0_int31_en8; + ZXIC_UINT32 smmu0_int31_en7; + ZXIC_UINT32 smmu0_int31_en6; + ZXIC_UINT32 smmu0_int31_en5; + ZXIC_UINT32 smmu0_int31_en4; + ZXIC_UINT32 smmu0_int31_en3; + ZXIC_UINT32 smmu0_int31_en2; + ZXIC_UINT32 smmu0_int31_en1; + ZXIC_UINT32 smmu0_int31_en0; +}DPP_SMMU0_SMMU0_SMMU0_INT31_EN_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int31_mask_t +{ + ZXIC_UINT32 smmu0_int31_mask31; + ZXIC_UINT32 smmu0_int31_mask30; + ZXIC_UINT32 smmu0_int31_mask29; + ZXIC_UINT32 smmu0_int31_mask28; + ZXIC_UINT32 smmu0_int31_mask27; + ZXIC_UINT32 smmu0_int31_mask26; + ZXIC_UINT32 smmu0_int31_mask25; + ZXIC_UINT32 smmu0_int31_mask24; + ZXIC_UINT32 smmu0_int31_mask23; + ZXIC_UINT32 smmu0_int31_mask22; + ZXIC_UINT32 smmu0_int31_mask21; + ZXIC_UINT32 smmu0_int31_mask20; + ZXIC_UINT32 smmu0_int31_mask19; + ZXIC_UINT32 smmu0_int31_mask18; + ZXIC_UINT32 smmu0_int31_mask17; + ZXIC_UINT32 smmu0_int31_mask16; + ZXIC_UINT32 smmu0_int31_mask15; + ZXIC_UINT32 smmu0_int31_mask14; + ZXIC_UINT32 smmu0_int31_mask13; + ZXIC_UINT32 smmu0_int31_mask12; + ZXIC_UINT32 smmu0_int31_mask11; + ZXIC_UINT32 smmu0_int31_mask10; + ZXIC_UINT32 smmu0_int31_mask9; + ZXIC_UINT32 smmu0_int31_mask8; + ZXIC_UINT32 smmu0_int31_mask7; + ZXIC_UINT32 smmu0_int31_mask6; + ZXIC_UINT32 smmu0_int31_mask5; + ZXIC_UINT32 smmu0_int31_mask4; + ZXIC_UINT32 smmu0_int31_mask3; + ZXIC_UINT32 smmu0_int31_mask2; + ZXIC_UINT32 smmu0_int31_mask1; + ZXIC_UINT32 smmu0_int31_mask0; +}DPP_SMMU0_SMMU0_SMMU0_INT31_MASK_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int31_status_t +{ + ZXIC_UINT32 smmu0_int31_status31; + ZXIC_UINT32 smmu0_int31_status30; + ZXIC_UINT32 smmu0_int31_status29; + ZXIC_UINT32 smmu0_int31_status28; + ZXIC_UINT32 smmu0_int31_status27; + ZXIC_UINT32 smmu0_int31_status26; + ZXIC_UINT32 smmu0_int31_status25; + ZXIC_UINT32 smmu0_int31_status24; + ZXIC_UINT32 smmu0_int31_status23; + ZXIC_UINT32 smmu0_int31_status22; + ZXIC_UINT32 smmu0_int31_status21; + ZXIC_UINT32 smmu0_int31_status20; + ZXIC_UINT32 smmu0_int31_status19; + ZXIC_UINT32 smmu0_int31_status18; + ZXIC_UINT32 smmu0_int31_status17; + ZXIC_UINT32 smmu0_int31_status16; + ZXIC_UINT32 smmu0_int31_status15; + ZXIC_UINT32 smmu0_int31_status14; + ZXIC_UINT32 smmu0_int31_status13; + ZXIC_UINT32 smmu0_int31_status12; + ZXIC_UINT32 smmu0_int31_status11; + ZXIC_UINT32 smmu0_int31_status10; + ZXIC_UINT32 smmu0_int31_status9; + ZXIC_UINT32 smmu0_int31_status8; + ZXIC_UINT32 smmu0_int31_status7; + ZXIC_UINT32 smmu0_int31_status6; + ZXIC_UINT32 smmu0_int31_status5; + ZXIC_UINT32 smmu0_int31_status4; + ZXIC_UINT32 smmu0_int31_status3; + ZXIC_UINT32 smmu0_int31_status2; + ZXIC_UINT32 smmu0_int31_status1; + ZXIC_UINT32 smmu0_int31_status0; +}DPP_SMMU0_SMMU0_SMMU0_INT31_STATUS_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int32_en_t +{ + ZXIC_UINT32 smmu0_int32_en31; + ZXIC_UINT32 smmu0_int32_en30; + ZXIC_UINT32 smmu0_int32_en29; + ZXIC_UINT32 smmu0_int32_en28; + ZXIC_UINT32 smmu0_int32_en27; + ZXIC_UINT32 smmu0_int32_en26; + ZXIC_UINT32 smmu0_int32_en25; + ZXIC_UINT32 smmu0_int32_en24; + ZXIC_UINT32 smmu0_int32_en23; + ZXIC_UINT32 smmu0_int32_en22; + ZXIC_UINT32 smmu0_int32_en21; + ZXIC_UINT32 smmu0_int32_en20; + ZXIC_UINT32 smmu0_int32_en19; + ZXIC_UINT32 smmu0_int32_en18; + ZXIC_UINT32 smmu0_int32_en17; + ZXIC_UINT32 smmu0_int32_en16; + ZXIC_UINT32 smmu0_int32_en15; + ZXIC_UINT32 smmu0_int32_en14; + ZXIC_UINT32 smmu0_int32_en13; + ZXIC_UINT32 smmu0_int32_en12; + ZXIC_UINT32 smmu0_int32_en11; + ZXIC_UINT32 smmu0_int32_en10; + ZXIC_UINT32 smmu0_int32_en9; + ZXIC_UINT32 smmu0_int32_en8; + ZXIC_UINT32 smmu0_int32_en7; + ZXIC_UINT32 smmu0_int32_en6; + ZXIC_UINT32 smmu0_int32_en5; + ZXIC_UINT32 smmu0_int32_en4; + ZXIC_UINT32 smmu0_int32_en3; + ZXIC_UINT32 smmu0_int32_en2; + ZXIC_UINT32 smmu0_int32_en1; + ZXIC_UINT32 smmu0_int32_en0; +}DPP_SMMU0_SMMU0_SMMU0_INT32_EN_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int32_mask_t +{ + ZXIC_UINT32 smmu0_int32_mask31; + ZXIC_UINT32 smmu0_int32_mask30; + ZXIC_UINT32 smmu0_int32_mask29; + ZXIC_UINT32 smmu0_int32_mask28; + ZXIC_UINT32 smmu0_int32_mask27; + ZXIC_UINT32 smmu0_int32_mask26; + ZXIC_UINT32 smmu0_int32_mask25; + ZXIC_UINT32 smmu0_int32_mask24; + ZXIC_UINT32 smmu0_int32_mask23; + ZXIC_UINT32 smmu0_int32_mask22; + ZXIC_UINT32 smmu0_int32_mask21; + ZXIC_UINT32 smmu0_int32_mask20; + ZXIC_UINT32 smmu0_int32_mask19; + ZXIC_UINT32 smmu0_int32_mask18; + ZXIC_UINT32 smmu0_int32_mask17; + ZXIC_UINT32 smmu0_int32_mask16; + ZXIC_UINT32 smmu0_int32_mask15; + ZXIC_UINT32 smmu0_int32_mask14; + ZXIC_UINT32 smmu0_int32_mask13; + ZXIC_UINT32 smmu0_int32_mask12; + ZXIC_UINT32 smmu0_int32_mask11; + ZXIC_UINT32 smmu0_int32_mask10; + ZXIC_UINT32 smmu0_int32_mask9; + ZXIC_UINT32 smmu0_int32_mask8; + ZXIC_UINT32 smmu0_int32_mask7; + ZXIC_UINT32 smmu0_int32_mask6; + ZXIC_UINT32 smmu0_int32_mask5; + ZXIC_UINT32 smmu0_int32_mask4; + ZXIC_UINT32 smmu0_int32_mask3; + ZXIC_UINT32 smmu0_int32_mask2; + ZXIC_UINT32 smmu0_int32_mask1; + ZXIC_UINT32 smmu0_int32_mask0; +}DPP_SMMU0_SMMU0_SMMU0_INT32_MASK_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int32_status_t +{ + ZXIC_UINT32 smmu0_int32_status31; + ZXIC_UINT32 smmu0_int32_status30; + ZXIC_UINT32 smmu0_int32_status29; + ZXIC_UINT32 smmu0_int32_status28; + ZXIC_UINT32 smmu0_int32_status27; + ZXIC_UINT32 smmu0_int32_status26; + ZXIC_UINT32 smmu0_int32_status25; + ZXIC_UINT32 smmu0_int32_status24; + ZXIC_UINT32 smmu0_int32_status23; + ZXIC_UINT32 smmu0_int32_status22; + ZXIC_UINT32 smmu0_int32_status21; + ZXIC_UINT32 smmu0_int32_status20; + ZXIC_UINT32 smmu0_int32_status19; + ZXIC_UINT32 smmu0_int32_status18; + ZXIC_UINT32 smmu0_int32_status17; + ZXIC_UINT32 smmu0_int32_status16; + ZXIC_UINT32 smmu0_int32_status15; + ZXIC_UINT32 smmu0_int32_status14; + ZXIC_UINT32 smmu0_int32_status13; + ZXIC_UINT32 smmu0_int32_status12; + ZXIC_UINT32 smmu0_int32_status11; + ZXIC_UINT32 smmu0_int32_status10; + ZXIC_UINT32 smmu0_int32_status9; + ZXIC_UINT32 smmu0_int32_status8; + ZXIC_UINT32 smmu0_int32_status7; + ZXIC_UINT32 smmu0_int32_status6; + ZXIC_UINT32 smmu0_int32_status5; + ZXIC_UINT32 smmu0_int32_status4; + ZXIC_UINT32 smmu0_int32_status3; + ZXIC_UINT32 smmu0_int32_status2; + ZXIC_UINT32 smmu0_int32_status1; + ZXIC_UINT32 smmu0_int32_status0; +}DPP_SMMU0_SMMU0_SMMU0_INT32_STATUS_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int33_en_t +{ + ZXIC_UINT32 smmu0_int33_en31; + ZXIC_UINT32 smmu0_int33_en30; + ZXIC_UINT32 smmu0_int33_en29; + ZXIC_UINT32 smmu0_int33_en28; + ZXIC_UINT32 smmu0_int33_en27; + ZXIC_UINT32 smmu0_int33_en26; + ZXIC_UINT32 smmu0_int33_en25; + ZXIC_UINT32 smmu0_int33_en24; + ZXIC_UINT32 smmu0_int33_en23; + ZXIC_UINT32 smmu0_int33_en22; + ZXIC_UINT32 smmu0_int33_en21; + ZXIC_UINT32 smmu0_int33_en20; + ZXIC_UINT32 smmu0_int33_en19; + ZXIC_UINT32 smmu0_int33_en18; + ZXIC_UINT32 smmu0_int33_en17; + ZXIC_UINT32 smmu0_int33_en16; + ZXIC_UINT32 smmu0_int33_en15; + ZXIC_UINT32 smmu0_int33_en14; + ZXIC_UINT32 smmu0_int33_en13; + ZXIC_UINT32 smmu0_int33_en12; + ZXIC_UINT32 smmu0_int33_en11; + ZXIC_UINT32 smmu0_int33_en10; + ZXIC_UINT32 smmu0_int33_en9; + ZXIC_UINT32 smmu0_int33_en8; + ZXIC_UINT32 smmu0_int33_en7; + ZXIC_UINT32 smmu0_int33_en6; + ZXIC_UINT32 smmu0_int33_en5; + ZXIC_UINT32 smmu0_int33_en4; + ZXIC_UINT32 smmu0_int33_en3; + ZXIC_UINT32 smmu0_int33_en2; + ZXIC_UINT32 smmu0_int33_en1; + ZXIC_UINT32 smmu0_int33_en0; +}DPP_SMMU0_SMMU0_SMMU0_INT33_EN_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int33_mask_t +{ + ZXIC_UINT32 smmu0_int33_mask31; + ZXIC_UINT32 smmu0_int33_mask30; + ZXIC_UINT32 smmu0_int33_mask29; + ZXIC_UINT32 smmu0_int33_mask28; + ZXIC_UINT32 smmu0_int33_mask27; + ZXIC_UINT32 smmu0_int33_mask26; + ZXIC_UINT32 smmu0_int33_mask25; + ZXIC_UINT32 smmu0_int33_mask24; + ZXIC_UINT32 smmu0_int33_mask23; + ZXIC_UINT32 smmu0_int33_mask22; + ZXIC_UINT32 smmu0_int33_mask21; + ZXIC_UINT32 smmu0_int33_mask20; + ZXIC_UINT32 smmu0_int33_mask19; + ZXIC_UINT32 smmu0_int33_mask18; + ZXIC_UINT32 smmu0_int33_mask17; + ZXIC_UINT32 smmu0_int33_mask16; + ZXIC_UINT32 smmu0_int33_mask15; + ZXIC_UINT32 smmu0_int33_mask14; + ZXIC_UINT32 smmu0_int33_mask13; + ZXIC_UINT32 smmu0_int33_mask12; + ZXIC_UINT32 smmu0_int33_mask11; + ZXIC_UINT32 smmu0_int33_mask10; + ZXIC_UINT32 smmu0_int33_mask9; + ZXIC_UINT32 smmu0_int33_mask8; + ZXIC_UINT32 smmu0_int33_mask7; + ZXIC_UINT32 smmu0_int33_mask6; + ZXIC_UINT32 smmu0_int33_mask5; + ZXIC_UINT32 smmu0_int33_mask4; + ZXIC_UINT32 smmu0_int33_mask3; + ZXIC_UINT32 smmu0_int33_mask2; + ZXIC_UINT32 smmu0_int33_mask1; + ZXIC_UINT32 smmu0_int33_mask0; +}DPP_SMMU0_SMMU0_SMMU0_INT33_MASK_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int33_status_t +{ + ZXIC_UINT32 smmu0_int33_status31; + ZXIC_UINT32 smmu0_int33_status30; + ZXIC_UINT32 smmu0_int33_status29; + ZXIC_UINT32 smmu0_int33_status28; + ZXIC_UINT32 smmu0_int33_status27; + ZXIC_UINT32 smmu0_int33_status26; + ZXIC_UINT32 smmu0_int33_status25; + ZXIC_UINT32 smmu0_int33_status24; + ZXIC_UINT32 smmu0_int33_status23; + ZXIC_UINT32 smmu0_int33_status22; + ZXIC_UINT32 smmu0_int33_status21; + ZXIC_UINT32 smmu0_int33_status20; + ZXIC_UINT32 smmu0_int33_status19; + ZXIC_UINT32 smmu0_int33_status18; + ZXIC_UINT32 smmu0_int33_status17; + ZXIC_UINT32 smmu0_int33_status16; + ZXIC_UINT32 smmu0_int33_status15; + ZXIC_UINT32 smmu0_int33_status14; + ZXIC_UINT32 smmu0_int33_status13; + ZXIC_UINT32 smmu0_int33_status12; + ZXIC_UINT32 smmu0_int33_status11; + ZXIC_UINT32 smmu0_int33_status10; + ZXIC_UINT32 smmu0_int33_status9; + ZXIC_UINT32 smmu0_int33_status8; + ZXIC_UINT32 smmu0_int33_status7; + ZXIC_UINT32 smmu0_int33_status6; + ZXIC_UINT32 smmu0_int33_status5; + ZXIC_UINT32 smmu0_int33_status4; + ZXIC_UINT32 smmu0_int33_status3; + ZXIC_UINT32 smmu0_int33_status2; + ZXIC_UINT32 smmu0_int33_status1; + ZXIC_UINT32 smmu0_int33_status0; +}DPP_SMMU0_SMMU0_SMMU0_INT33_STATUS_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int34_en_t +{ + ZXIC_UINT32 smmu0_int34_en31; + ZXIC_UINT32 smmu0_int34_en30; + ZXIC_UINT32 smmu0_int34_en29; + ZXIC_UINT32 smmu0_int34_en28; + ZXIC_UINT32 smmu0_int34_en27; + ZXIC_UINT32 smmu0_int34_en26; + ZXIC_UINT32 smmu0_int34_en25; + ZXIC_UINT32 smmu0_int34_en24; + ZXIC_UINT32 smmu0_int34_en23; + ZXIC_UINT32 smmu0_int34_en22; + ZXIC_UINT32 smmu0_int34_en21; + ZXIC_UINT32 smmu0_int34_en20; + ZXIC_UINT32 smmu0_int34_en19; + ZXIC_UINT32 smmu0_int34_en18; + ZXIC_UINT32 smmu0_int34_en17; + ZXIC_UINT32 smmu0_int34_en16; + ZXIC_UINT32 smmu0_int34_en15; + ZXIC_UINT32 smmu0_int34_en14; + ZXIC_UINT32 smmu0_int34_en13; + ZXIC_UINT32 smmu0_int34_en12; + ZXIC_UINT32 smmu0_int34_en11; + ZXIC_UINT32 smmu0_int34_en10; + ZXIC_UINT32 smmu0_int34_en9; + ZXIC_UINT32 smmu0_int34_en8; + ZXIC_UINT32 smmu0_int34_en7; + ZXIC_UINT32 smmu0_int34_en6; + ZXIC_UINT32 smmu0_int34_en5; + ZXIC_UINT32 smmu0_int34_en4; + ZXIC_UINT32 smmu0_int34_en3; + ZXIC_UINT32 smmu0_int34_en2; + ZXIC_UINT32 smmu0_int34_en1; + ZXIC_UINT32 smmu0_int34_en0; +}DPP_SMMU0_SMMU0_SMMU0_INT34_EN_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int34_mask_t +{ + ZXIC_UINT32 smmu0_int34_mask31; + ZXIC_UINT32 smmu0_int34_mask30; + ZXIC_UINT32 smmu0_int34_mask29; + ZXIC_UINT32 smmu0_int34_mask28; + ZXIC_UINT32 smmu0_int34_mask27; + ZXIC_UINT32 smmu0_int34_mask26; + ZXIC_UINT32 smmu0_int34_mask25; + ZXIC_UINT32 smmu0_int34_mask24; + ZXIC_UINT32 smmu0_int34_mask23; + ZXIC_UINT32 smmu0_int34_mask22; + ZXIC_UINT32 smmu0_int34_mask21; + ZXIC_UINT32 smmu0_int34_mask20; + ZXIC_UINT32 smmu0_int34_mask19; + ZXIC_UINT32 smmu0_int34_mask18; + ZXIC_UINT32 smmu0_int34_mask17; + ZXIC_UINT32 smmu0_int34_mask16; + ZXIC_UINT32 smmu0_int34_mask15; + ZXIC_UINT32 smmu0_int34_mask14; + ZXIC_UINT32 smmu0_int34_mask13; + ZXIC_UINT32 smmu0_int34_mask12; + ZXIC_UINT32 smmu0_int34_mask11; + ZXIC_UINT32 smmu0_int34_mask10; + ZXIC_UINT32 smmu0_int34_mask9; + ZXIC_UINT32 smmu0_int34_mask8; + ZXIC_UINT32 smmu0_int34_mask7; + ZXIC_UINT32 smmu0_int34_mask6; + ZXIC_UINT32 smmu0_int34_mask5; + ZXIC_UINT32 smmu0_int34_mask4; + ZXIC_UINT32 smmu0_int34_mask3; + ZXIC_UINT32 smmu0_int34_mask2; + ZXIC_UINT32 smmu0_int34_mask1; + ZXIC_UINT32 smmu0_int34_mask0; +}DPP_SMMU0_SMMU0_SMMU0_INT34_MASK_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int34_status_t +{ + ZXIC_UINT32 smmu0_int34_status31; + ZXIC_UINT32 smmu0_int34_status30; + ZXIC_UINT32 smmu0_int34_status29; + ZXIC_UINT32 smmu0_int34_status28; + ZXIC_UINT32 smmu0_int34_status27; + ZXIC_UINT32 smmu0_int34_status26; + ZXIC_UINT32 smmu0_int34_status25; + ZXIC_UINT32 smmu0_int34_status24; + ZXIC_UINT32 smmu0_int34_status23; + ZXIC_UINT32 smmu0_int34_status22; + ZXIC_UINT32 smmu0_int34_status21; + ZXIC_UINT32 smmu0_int34_status20; + ZXIC_UINT32 smmu0_int34_status19; + ZXIC_UINT32 smmu0_int34_status18; + ZXIC_UINT32 smmu0_int34_status17; + ZXIC_UINT32 smmu0_int34_status16; + ZXIC_UINT32 smmu0_int34_status15; + ZXIC_UINT32 smmu0_int34_status14; + ZXIC_UINT32 smmu0_int34_status13; + ZXIC_UINT32 smmu0_int34_status12; + ZXIC_UINT32 smmu0_int34_status11; + ZXIC_UINT32 smmu0_int34_status10; + ZXIC_UINT32 smmu0_int34_status9; + ZXIC_UINT32 smmu0_int34_status8; + ZXIC_UINT32 smmu0_int34_status7; + ZXIC_UINT32 smmu0_int34_status6; + ZXIC_UINT32 smmu0_int34_status5; + ZXIC_UINT32 smmu0_int34_status4; + ZXIC_UINT32 smmu0_int34_status3; + ZXIC_UINT32 smmu0_int34_status2; + ZXIC_UINT32 smmu0_int34_status1; + ZXIC_UINT32 smmu0_int34_status0; +}DPP_SMMU0_SMMU0_SMMU0_INT34_STATUS_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int35_en_t +{ + ZXIC_UINT32 smmu0_int35_en0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT35_EN_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int35_mask_t +{ + ZXIC_UINT32 smmu0_int35_mask0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT35_MASK_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int35_status_t +{ + ZXIC_UINT32 smmu0_int35_status0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT35_STATUS_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int36_en_t +{ + ZXIC_UINT32 smmu0_int36_en0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT36_EN_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int36_mask_t +{ + ZXIC_UINT32 smmu0_int36_mask0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT36_MASK_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int36_status_t +{ + ZXIC_UINT32 smmu0_int36_status0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT36_STATUS_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int37_en_t +{ + ZXIC_UINT32 smmu0_int37_en0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT37_EN_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int37_mask_t +{ + ZXIC_UINT32 smmu0_int37_mask0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT37_MASK_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int37_status_t +{ + ZXIC_UINT32 smmu0_int37_status0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT37_STATUS_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int38_en_t +{ + ZXIC_UINT32 smmu0_int38_en0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT38_EN_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int38_mask_t +{ + ZXIC_UINT32 smmu0_int38_mask0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT38_MASK_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int38_status_t +{ + ZXIC_UINT32 smmu0_int38_status0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT38_STATUS_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int39_en_t +{ + ZXIC_UINT32 smmu0_int39_en0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT39_EN_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int39_mask_t +{ + ZXIC_UINT32 smmu0_int39_mask0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT39_MASK_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int39_status_t +{ + ZXIC_UINT32 smmu0_int39_status0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT39_STATUS_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int40_en_t +{ + ZXIC_UINT32 smmu0_int40_en0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT40_EN_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int40_mask_t +{ + ZXIC_UINT32 smmu0_int40_mask0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT40_MASK_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int40_status_t +{ + ZXIC_UINT32 smmu0_int40_status0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT40_STATUS_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int41_en_t +{ + ZXIC_UINT32 smmu0_int41_en0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT41_EN_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int41_mask_t +{ + ZXIC_UINT32 smmu0_int41_mask0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT41_MASK_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int41_status_t +{ + ZXIC_UINT32 smmu0_int41_status0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT41_STATUS_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int42_en_t +{ + ZXIC_UINT32 smmu0_int42_en0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT42_EN_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int42_mask_t +{ + ZXIC_UINT32 smmu0_int42_mask0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT42_MASK_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int42_status_t +{ + ZXIC_UINT32 smmu0_int42_status0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT42_STATUS_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int43_en_t +{ + ZXIC_UINT32 smmu0_int43_en0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT43_EN_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int43_mask_t +{ + ZXIC_UINT32 smmu0_int43_mask0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT43_MASK_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int43_status_t +{ + ZXIC_UINT32 smmu0_int43_status0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT43_STATUS_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int44_en_t +{ + ZXIC_UINT32 smmu0_int44_en0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT44_EN_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int44_mask_t +{ + ZXIC_UINT32 smmu0_int44_mask0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT44_MASK_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int44_status_t +{ + ZXIC_UINT32 smmu0_int44_status0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT44_STATUS_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int45_en_t +{ + ZXIC_UINT32 smmu0_int45_en0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT45_EN_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int45_mask_t +{ + ZXIC_UINT32 smmu0_int45_mask0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT45_MASK_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int45_status_t +{ + ZXIC_UINT32 smmu0_int45_status0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT45_STATUS_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int46_en_t +{ + ZXIC_UINT32 smmu0_int46_en0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT46_EN_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int46_mask_t +{ + ZXIC_UINT32 smmu0_int46_mask0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT46_MASK_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int46_status_t +{ + ZXIC_UINT32 smmu0_int46_status0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT46_STATUS_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int47_en_t +{ + ZXIC_UINT32 smmu0_int47_en0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT47_EN_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int47_mask_t +{ + ZXIC_UINT32 smmu0_int47_mask0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT47_MASK_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int47_status_t +{ + ZXIC_UINT32 smmu0_int47_status0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT47_STATUS_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int48_en_t +{ + ZXIC_UINT32 smmu0_int48_en0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT48_EN_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int48_mask_t +{ + ZXIC_UINT32 smmu0_int48_mask0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT48_MASK_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int48_status_t +{ + ZXIC_UINT32 smmu0_int48_status0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT48_STATUS_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int49_en_t +{ + ZXIC_UINT32 smmu0_int49_en0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT49_EN_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int49_mask_t +{ + ZXIC_UINT32 smmu0_int49_mask0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT49_MASK_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int49_status_t +{ + ZXIC_UINT32 smmu0_int49_status0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT49_STATUS_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int50_en_t +{ + ZXIC_UINT32 smmu0_int50_en0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT50_EN_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int50_mask_t +{ + ZXIC_UINT32 smmu0_int50_mask0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT50_MASK_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int50_status_t +{ + ZXIC_UINT32 smmu0_int50_status0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT50_STATUS_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int51_en_t +{ + ZXIC_UINT32 smmu0_int51_en0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT51_EN_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int51_mask_t +{ + ZXIC_UINT32 smmu0_int51_mask0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT51_MASK_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int51_status_t +{ + ZXIC_UINT32 smmu0_int51_status0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT51_STATUS_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int52_en_t +{ + ZXIC_UINT32 smmu0_int52_en0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT52_EN_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int52_mask_t +{ + ZXIC_UINT32 smmu0_int52_mask0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT52_MASK_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int52_status_t +{ + ZXIC_UINT32 smmu0_int52_status0_31; +}DPP_SMMU0_SMMU0_SMMU0_INT52_STATUS_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int53_en_t +{ + ZXIC_UINT32 smmu0_int53_en3; + ZXIC_UINT32 smmu0_int53_en2; + ZXIC_UINT32 smmu0_int53_en1; + ZXIC_UINT32 smmu0_int53_en0; +}DPP_SMMU0_SMMU0_SMMU0_INT53_EN_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int53_mask_t +{ + ZXIC_UINT32 smmu0_int53_mask3; + ZXIC_UINT32 smmu0_int53_mask2; + ZXIC_UINT32 smmu0_int53_mask1; + ZXIC_UINT32 smmu0_int53_mask0; +}DPP_SMMU0_SMMU0_SMMU0_INT53_MASK_T; + +typedef struct dpp_smmu0_smmu0_smmu0_int53_status_t +{ + ZXIC_UINT32 smmu0_int53_status15; + ZXIC_UINT32 smmu0_int53_status14; + ZXIC_UINT32 smmu0_int53_status13; + ZXIC_UINT32 smmu0_int53_status12; +}DPP_SMMU0_SMMU0_SMMU0_INT53_STATUS_T; + +typedef struct dpp_smmu0_smmu0_ctrl0_arbiter_ecc_bypass_t +{ + ZXIC_UINT32 ctrl1_arbiter_ecc_bypass_15; + ZXIC_UINT32 ctrl1_arbiter_ecc_bypass_14; + ZXIC_UINT32 ctrl1_arbiter_ecc_bypass_13; + ZXIC_UINT32 ctrl1_arbiter_ecc_bypass_12; + ZXIC_UINT32 ctrl1_arbiter_ecc_bypass_11; + ZXIC_UINT32 ctrl1_arbiter_ecc_bypass_10; + ZXIC_UINT32 ctrl1_arbiter_ecc_bypass_9; + ZXIC_UINT32 ctrl1_arbiter_ecc_bypass_8; + ZXIC_UINT32 ctrl1_arbiter_ecc_bypass_7; + ZXIC_UINT32 ctrl1_arbiter_ecc_bypass_6; + ZXIC_UINT32 ctrl1_arbiter_ecc_bypass_5; + ZXIC_UINT32 ctrl1_arbiter_ecc_bypass_4; + ZXIC_UINT32 ctrl1_arbiter_ecc_bypass_3; + ZXIC_UINT32 ctrl1_arbiter_ecc_bypass_2; + ZXIC_UINT32 ctrl1_arbiter_ecc_bypass_1; + ZXIC_UINT32 ctrl1_arbiter_ecc_bypass_0; + ZXIC_UINT32 ctrl0_arbiter_ecc_bypass_15; + ZXIC_UINT32 ctrl0_arbiter_ecc_bypass_14; + ZXIC_UINT32 ctrl0_arbiter_ecc_bypass_13; + ZXIC_UINT32 ctrl0_arbiter_ecc_bypass_12; + ZXIC_UINT32 ctrl0_arbiter_ecc_bypass_11; + ZXIC_UINT32 ctrl0_arbiter_ecc_bypass_10; + ZXIC_UINT32 ctrl0_arbiter_ecc_bypass_9; + ZXIC_UINT32 ctrl0_arbiter_ecc_bypass_8; + ZXIC_UINT32 ctrl0_arbiter_ecc_bypass_7; + ZXIC_UINT32 ctrl0_arbiter_ecc_bypass_6; + ZXIC_UINT32 ctrl0_arbiter_ecc_bypass_5; + ZXIC_UINT32 ctrl0_arbiter_ecc_bypass_4; + ZXIC_UINT32 ctrl0_arbiter_ecc_bypass_3; + ZXIC_UINT32 ctrl0_arbiter_ecc_bypass_2; + ZXIC_UINT32 ctrl0_arbiter_ecc_bypass_1; + ZXIC_UINT32 ctrl0_arbiter_ecc_bypass_0; +}DPP_SMMU0_SMMU0_CTRL0_ARBITER_ECC_BYPASS_T; + +typedef struct dpp_smmu0_smmu0_ctrl2_arbiter_ecc_bypass_t +{ + ZXIC_UINT32 ctrl3_arbiter_ecc_bypass_15; + ZXIC_UINT32 ctrl3_arbiter_ecc_bypass_14; + ZXIC_UINT32 ctrl3_arbiter_ecc_bypass_13; + ZXIC_UINT32 ctrl3_arbiter_ecc_bypass_12; + ZXIC_UINT32 ctrl3_arbiter_ecc_bypass_11; + ZXIC_UINT32 ctrl3_arbiter_ecc_bypass_10; + ZXIC_UINT32 ctrl3_arbiter_ecc_bypass_9; + ZXIC_UINT32 ctrl3_arbiter_ecc_bypass_8; + ZXIC_UINT32 ctrl3_arbiter_ecc_bypass_7; + ZXIC_UINT32 ctrl3_arbiter_ecc_bypass_6; + ZXIC_UINT32 ctrl3_arbiter_ecc_bypass_5; + ZXIC_UINT32 ctrl3_arbiter_ecc_bypass_4; + ZXIC_UINT32 ctrl3_arbiter_ecc_bypass_3; + ZXIC_UINT32 ctrl3_arbiter_ecc_bypass_2; + ZXIC_UINT32 ctrl3_arbiter_ecc_bypass_1; + ZXIC_UINT32 ctrl3_arbiter_ecc_bypass_0; + ZXIC_UINT32 ctrl2_arbiter_ecc_bypass_15; + ZXIC_UINT32 ctrl2_arbiter_ecc_bypass_14; + ZXIC_UINT32 ctrl2_arbiter_ecc_bypass_13; + ZXIC_UINT32 ctrl2_arbiter_ecc_bypass_12; + ZXIC_UINT32 ctrl2_arbiter_ecc_bypass_11; + ZXIC_UINT32 ctrl2_arbiter_ecc_bypass_10; + ZXIC_UINT32 ctrl2_arbiter_ecc_bypass_9; + ZXIC_UINT32 ctrl2_arbiter_ecc_bypass_8; + ZXIC_UINT32 ctrl2_arbiter_ecc_bypass_7; + ZXIC_UINT32 ctrl2_arbiter_ecc_bypass_6; + ZXIC_UINT32 ctrl2_arbiter_ecc_bypass_5; + ZXIC_UINT32 ctrl2_arbiter_ecc_bypass_4; + ZXIC_UINT32 ctrl2_arbiter_ecc_bypass_3; + ZXIC_UINT32 ctrl2_arbiter_ecc_bypass_2; + ZXIC_UINT32 ctrl2_arbiter_ecc_bypass_1; + ZXIC_UINT32 ctrl2_arbiter_ecc_bypass_0; +}DPP_SMMU0_SMMU0_CTRL2_ARBITER_ECC_BYPASS_T; + +typedef struct dpp_smmu0_smmu0_ctrl4_arbiter_ecc_bypass_t +{ + ZXIC_UINT32 ctrl5_arbiter_ecc_bypass_15; + ZXIC_UINT32 ctrl5_arbiter_ecc_bypass_14; + ZXIC_UINT32 ctrl5_arbiter_ecc_bypass_13; + ZXIC_UINT32 ctrl5_arbiter_ecc_bypass_12; + ZXIC_UINT32 ctrl5_arbiter_ecc_bypass_11; + ZXIC_UINT32 ctrl5_arbiter_ecc_bypass_10; + ZXIC_UINT32 ctrl5_arbiter_ecc_bypass_9; + ZXIC_UINT32 ctrl5_arbiter_ecc_bypass_8; + ZXIC_UINT32 ctrl5_arbiter_ecc_bypass_7; + ZXIC_UINT32 ctrl5_arbiter_ecc_bypass_6; + ZXIC_UINT32 ctrl5_arbiter_ecc_bypass_5; + ZXIC_UINT32 ctrl5_arbiter_ecc_bypass_4; + ZXIC_UINT32 ctrl5_arbiter_ecc_bypass_3; + ZXIC_UINT32 ctrl5_arbiter_ecc_bypass_2; + ZXIC_UINT32 ctrl5_arbiter_ecc_bypass_1; + ZXIC_UINT32 ctrl5_arbiter_ecc_bypass_0; + ZXIC_UINT32 ctrl4_arbiter_ecc_bypass_15; + ZXIC_UINT32 ctrl4_arbiter_ecc_bypass_14; + ZXIC_UINT32 ctrl4_arbiter_ecc_bypass_13; + ZXIC_UINT32 ctrl4_arbiter_ecc_bypass_12; + ZXIC_UINT32 ctrl4_arbiter_ecc_bypass_11; + ZXIC_UINT32 ctrl4_arbiter_ecc_bypass_10; + ZXIC_UINT32 ctrl4_arbiter_ecc_bypass_9; + ZXIC_UINT32 ctrl4_arbiter_ecc_bypass_8; + ZXIC_UINT32 ctrl4_arbiter_ecc_bypass_7; + ZXIC_UINT32 ctrl4_arbiter_ecc_bypass_6; + ZXIC_UINT32 ctrl4_arbiter_ecc_bypass_5; + ZXIC_UINT32 ctrl4_arbiter_ecc_bypass_4; + ZXIC_UINT32 ctrl4_arbiter_ecc_bypass_3; + ZXIC_UINT32 ctrl4_arbiter_ecc_bypass_2; + ZXIC_UINT32 ctrl4_arbiter_ecc_bypass_1; + ZXIC_UINT32 ctrl4_arbiter_ecc_bypass_0; +}DPP_SMMU0_SMMU0_CTRL4_ARBITER_ECC_BYPASS_T; + +typedef struct dpp_smmu0_smmu0_ctrl6_arbiter_ecc_bypass_t +{ + ZXIC_UINT32 ctrl7_arbiter_ecc_bypass_15; + ZXIC_UINT32 ctrl7_arbiter_ecc_bypass_14; + ZXIC_UINT32 ctrl7_arbiter_ecc_bypass_13; + ZXIC_UINT32 ctrl7_arbiter_ecc_bypass_12; + ZXIC_UINT32 ctrl7_arbiter_ecc_bypass_11; + ZXIC_UINT32 ctrl7_arbiter_ecc_bypass_10; + ZXIC_UINT32 ctrl7_arbiter_ecc_bypass_9; + ZXIC_UINT32 ctrl7_arbiter_ecc_bypass_8; + ZXIC_UINT32 ctrl7_arbiter_ecc_bypass_7; + ZXIC_UINT32 ctrl7_arbiter_ecc_bypass_6; + ZXIC_UINT32 ctrl7_arbiter_ecc_bypass_5; + ZXIC_UINT32 ctrl7_arbiter_ecc_bypass_4; + ZXIC_UINT32 ctrl7_arbiter_ecc_bypass_3; + ZXIC_UINT32 ctrl7_arbiter_ecc_bypass_2; + ZXIC_UINT32 ctrl7_arbiter_ecc_bypass_1; + ZXIC_UINT32 ctrl7_arbiter_ecc_bypass_0; + ZXIC_UINT32 ctrl6_arbiter_ecc_bypass_15; + ZXIC_UINT32 ctrl6_arbiter_ecc_bypass_14; + ZXIC_UINT32 ctrl6_arbiter_ecc_bypass_13; + ZXIC_UINT32 ctrl6_arbiter_ecc_bypass_12; + ZXIC_UINT32 ctrl6_arbiter_ecc_bypass_11; + ZXIC_UINT32 ctrl6_arbiter_ecc_bypass_10; + ZXIC_UINT32 ctrl6_arbiter_ecc_bypass_9; + ZXIC_UINT32 ctrl6_arbiter_ecc_bypass_8; + ZXIC_UINT32 ctrl6_arbiter_ecc_bypass_7; + ZXIC_UINT32 ctrl6_arbiter_ecc_bypass_6; + ZXIC_UINT32 ctrl6_arbiter_ecc_bypass_5; + ZXIC_UINT32 ctrl6_arbiter_ecc_bypass_4; + ZXIC_UINT32 ctrl6_arbiter_ecc_bypass_3; + ZXIC_UINT32 ctrl6_arbiter_ecc_bypass_2; + ZXIC_UINT32 ctrl6_arbiter_ecc_bypass_1; + ZXIC_UINT32 ctrl6_arbiter_ecc_bypass_0; +}DPP_SMMU0_SMMU0_CTRL6_ARBITER_ECC_BYPASS_T; + +typedef struct dpp_smmu0_smmu0_ctrl8_arbiter_ecc_bypass_t +{ + ZXIC_UINT32 ctrl9_arbiter_ecc_bypass_15; + ZXIC_UINT32 ctrl9_arbiter_ecc_bypass_14; + ZXIC_UINT32 ctrl9_arbiter_ecc_bypass_13; + ZXIC_UINT32 ctrl9_arbiter_ecc_bypass_12; + ZXIC_UINT32 ctrl9_arbiter_ecc_bypass_11; + ZXIC_UINT32 ctrl9_arbiter_ecc_bypass_10; + ZXIC_UINT32 ctrl9_arbiter_ecc_bypass_9; + ZXIC_UINT32 ctrl9_arbiter_ecc_bypass_8; + ZXIC_UINT32 ctrl9_arbiter_ecc_bypass_7; + ZXIC_UINT32 ctrl9_arbiter_ecc_bypass_6; + ZXIC_UINT32 ctrl9_arbiter_ecc_bypass_5; + ZXIC_UINT32 ctrl9_arbiter_ecc_bypass_4; + ZXIC_UINT32 ctrl9_arbiter_ecc_bypass_3; + ZXIC_UINT32 ctrl9_arbiter_ecc_bypass_2; + ZXIC_UINT32 ctrl9_arbiter_ecc_bypass_1; + ZXIC_UINT32 ctrl9_arbiter_ecc_bypass_0; + ZXIC_UINT32 ctrl8_arbiter_ecc_bypass_15; + ZXIC_UINT32 ctrl8_arbiter_ecc_bypass_14; + ZXIC_UINT32 ctrl8_arbiter_ecc_bypass_13; + ZXIC_UINT32 ctrl8_arbiter_ecc_bypass_12; + ZXIC_UINT32 ctrl8_arbiter_ecc_bypass_11; + ZXIC_UINT32 ctrl8_arbiter_ecc_bypass_10; + ZXIC_UINT32 ctrl8_arbiter_ecc_bypass_9; + ZXIC_UINT32 ctrl8_arbiter_ecc_bypass_8; + ZXIC_UINT32 ctrl8_arbiter_ecc_bypass_7; + ZXIC_UINT32 ctrl8_arbiter_ecc_bypass_6; + ZXIC_UINT32 ctrl8_arbiter_ecc_bypass_5; + ZXIC_UINT32 ctrl8_arbiter_ecc_bypass_4; + ZXIC_UINT32 ctrl8_arbiter_ecc_bypass_3; + ZXIC_UINT32 ctrl8_arbiter_ecc_bypass_2; + ZXIC_UINT32 ctrl8_arbiter_ecc_bypass_1; + ZXIC_UINT32 ctrl8_arbiter_ecc_bypass_0; +}DPP_SMMU0_SMMU0_CTRL8_ARBITER_ECC_BYPASS_T; + +typedef struct dpp_smmu0_smmu0_ctrl10_arbiter_ecc_bypass_t +{ + ZXIC_UINT32 ctrl11_arbiter_ecc_bypass_15; + ZXIC_UINT32 ctrl11_arbiter_ecc_bypass_14; + ZXIC_UINT32 ctrl11_arbiter_ecc_bypass_13; + ZXIC_UINT32 ctrl11_arbiter_ecc_bypass_12; + ZXIC_UINT32 ctrl11_arbiter_ecc_bypass_11; + ZXIC_UINT32 ctrl11_arbiter_ecc_bypass_10; + ZXIC_UINT32 ctrl11_arbiter_ecc_bypass_9; + ZXIC_UINT32 ctrl11_arbiter_ecc_bypass_8; + ZXIC_UINT32 ctrl11_arbiter_ecc_bypass_7; + ZXIC_UINT32 ctrl11_arbiter_ecc_bypass_6; + ZXIC_UINT32 ctrl11_arbiter_ecc_bypass_5; + ZXIC_UINT32 ctrl11_arbiter_ecc_bypass_4; + ZXIC_UINT32 ctrl11_arbiter_ecc_bypass_3; + ZXIC_UINT32 ctrl11_arbiter_ecc_bypass_2; + ZXIC_UINT32 ctrl11_arbiter_ecc_bypass_1; + ZXIC_UINT32 ctrl11_arbiter_ecc_bypass_0; + ZXIC_UINT32 ctrl10_arbiter_ecc_bypass_15; + ZXIC_UINT32 ctrl10_arbiter_ecc_bypass_14; + ZXIC_UINT32 ctrl10_arbiter_ecc_bypass_13; + ZXIC_UINT32 ctrl10_arbiter_ecc_bypass_12; + ZXIC_UINT32 ctrl10_arbiter_ecc_bypass_11; + ZXIC_UINT32 ctrl10_arbiter_ecc_bypass_10; + ZXIC_UINT32 ctrl10_arbiter_ecc_bypass_9; + ZXIC_UINT32 ctrl10_arbiter_ecc_bypass_8; + ZXIC_UINT32 ctrl10_arbiter_ecc_bypass_7; + ZXIC_UINT32 ctrl10_arbiter_ecc_bypass_6; + ZXIC_UINT32 ctrl10_arbiter_ecc_bypass_5; + ZXIC_UINT32 ctrl10_arbiter_ecc_bypass_4; + ZXIC_UINT32 ctrl10_arbiter_ecc_bypass_3; + ZXIC_UINT32 ctrl10_arbiter_ecc_bypass_2; + ZXIC_UINT32 ctrl10_arbiter_ecc_bypass_1; + ZXIC_UINT32 ctrl10_arbiter_ecc_bypass_0; +}DPP_SMMU0_SMMU0_CTRL10_ARBITER_ECC_BYPASS_T; + +typedef struct dpp_smmu0_smmu0_ctrl12_arbiter_ecc_bypass_t +{ + ZXIC_UINT32 ctrl13_arbiter_ecc_bypass_15; + ZXIC_UINT32 ctrl13_arbiter_ecc_bypass_14; + ZXIC_UINT32 ctrl13_arbiter_ecc_bypass_13; + ZXIC_UINT32 ctrl13_arbiter_ecc_bypass_12; + ZXIC_UINT32 ctrl13_arbiter_ecc_bypass_11; + ZXIC_UINT32 ctrl13_arbiter_ecc_bypass_10; + ZXIC_UINT32 ctrl13_arbiter_ecc_bypass_9; + ZXIC_UINT32 ctrl13_arbiter_ecc_bypass_8; + ZXIC_UINT32 ctrl13_arbiter_ecc_bypass_7; + ZXIC_UINT32 ctrl13_arbiter_ecc_bypass_6; + ZXIC_UINT32 ctrl13_arbiter_ecc_bypass_5; + ZXIC_UINT32 ctrl13_arbiter_ecc_bypass_4; + ZXIC_UINT32 ctrl13_arbiter_ecc_bypass_3; + ZXIC_UINT32 ctrl13_arbiter_ecc_bypass_2; + ZXIC_UINT32 ctrl13_arbiter_ecc_bypass_1; + ZXIC_UINT32 ctrl13_arbiter_ecc_bypass_0; + ZXIC_UINT32 ctrl12_arbiter_ecc_bypass_15; + ZXIC_UINT32 ctrl12_arbiter_ecc_bypass_14; + ZXIC_UINT32 ctrl12_arbiter_ecc_bypass_13; + ZXIC_UINT32 ctrl12_arbiter_ecc_bypass_12; + ZXIC_UINT32 ctrl12_arbiter_ecc_bypass_11; + ZXIC_UINT32 ctrl12_arbiter_ecc_bypass_10; + ZXIC_UINT32 ctrl12_arbiter_ecc_bypass_9; + ZXIC_UINT32 ctrl12_arbiter_ecc_bypass_8; + ZXIC_UINT32 ctrl12_arbiter_ecc_bypass_7; + ZXIC_UINT32 ctrl12_arbiter_ecc_bypass_6; + ZXIC_UINT32 ctrl12_arbiter_ecc_bypass_5; + ZXIC_UINT32 ctrl12_arbiter_ecc_bypass_4; + ZXIC_UINT32 ctrl12_arbiter_ecc_bypass_3; + ZXIC_UINT32 ctrl12_arbiter_ecc_bypass_2; + ZXIC_UINT32 ctrl12_arbiter_ecc_bypass_1; + ZXIC_UINT32 ctrl12_arbiter_ecc_bypass_0; +}DPP_SMMU0_SMMU0_CTRL12_ARBITER_ECC_BYPASS_T; + +typedef struct dpp_smmu0_smmu0_ctrl14_arbiter_ecc_bypass_t +{ + ZXIC_UINT32 ctrl15_arbiter_ecc_bypass_15; + ZXIC_UINT32 ctrl15_arbiter_ecc_bypass_14; + ZXIC_UINT32 ctrl15_arbiter_ecc_bypass_13; + ZXIC_UINT32 ctrl15_arbiter_ecc_bypass_12; + ZXIC_UINT32 ctrl15_arbiter_ecc_bypass_11; + ZXIC_UINT32 ctrl15_arbiter_ecc_bypass_10; + ZXIC_UINT32 ctrl15_arbiter_ecc_bypass_9; + ZXIC_UINT32 ctrl15_arbiter_ecc_bypass_8; + ZXIC_UINT32 ctrl15_arbiter_ecc_bypass_7; + ZXIC_UINT32 ctrl15_arbiter_ecc_bypass_6; + ZXIC_UINT32 ctrl15_arbiter_ecc_bypass_5; + ZXIC_UINT32 ctrl15_arbiter_ecc_bypass_4; + ZXIC_UINT32 ctrl15_arbiter_ecc_bypass_3; + ZXIC_UINT32 ctrl15_arbiter_ecc_bypass_2; + ZXIC_UINT32 ctrl15_arbiter_ecc_bypass_1; + ZXIC_UINT32 ctrl15_arbiter_ecc_bypass_0; + ZXIC_UINT32 ctrl14_arbiter_ecc_bypass_15; + ZXIC_UINT32 ctrl14_arbiter_ecc_bypass_14; + ZXIC_UINT32 ctrl14_arbiter_ecc_bypass_13; + ZXIC_UINT32 ctrl14_arbiter_ecc_bypass_12; + ZXIC_UINT32 ctrl14_arbiter_ecc_bypass_11; + ZXIC_UINT32 ctrl14_arbiter_ecc_bypass_10; + ZXIC_UINT32 ctrl14_arbiter_ecc_bypass_9; + ZXIC_UINT32 ctrl14_arbiter_ecc_bypass_8; + ZXIC_UINT32 ctrl14_arbiter_ecc_bypass_7; + ZXIC_UINT32 ctrl14_arbiter_ecc_bypass_6; + ZXIC_UINT32 ctrl14_arbiter_ecc_bypass_5; + ZXIC_UINT32 ctrl14_arbiter_ecc_bypass_4; + ZXIC_UINT32 ctrl14_arbiter_ecc_bypass_3; + ZXIC_UINT32 ctrl14_arbiter_ecc_bypass_2; + ZXIC_UINT32 ctrl14_arbiter_ecc_bypass_1; + ZXIC_UINT32 ctrl14_arbiter_ecc_bypass_0; +}DPP_SMMU0_SMMU0_CTRL14_ARBITER_ECC_BYPASS_T; + +typedef struct dpp_smmu0_smmu0_ctrl16_arbiter_ecc_bypass_t +{ + ZXIC_UINT32 ctrl17_arbiter_ecc_bypass_15; + ZXIC_UINT32 ctrl17_arbiter_ecc_bypass_14; + ZXIC_UINT32 ctrl17_arbiter_ecc_bypass_13; + ZXIC_UINT32 ctrl17_arbiter_ecc_bypass_12; + ZXIC_UINT32 ctrl17_arbiter_ecc_bypass_11; + ZXIC_UINT32 ctrl17_arbiter_ecc_bypass_10; + ZXIC_UINT32 ctrl17_arbiter_ecc_bypass_9; + ZXIC_UINT32 ctrl17_arbiter_ecc_bypass_8; + ZXIC_UINT32 ctrl17_arbiter_ecc_bypass_7; + ZXIC_UINT32 ctrl17_arbiter_ecc_bypass_6; + ZXIC_UINT32 ctrl17_arbiter_ecc_bypass_5; + ZXIC_UINT32 ctrl17_arbiter_ecc_bypass_4; + ZXIC_UINT32 ctrl17_arbiter_ecc_bypass_3; + ZXIC_UINT32 ctrl17_arbiter_ecc_bypass_2; + ZXIC_UINT32 ctrl17_arbiter_ecc_bypass_1; + ZXIC_UINT32 ctrl17_arbiter_ecc_bypass_0; + ZXIC_UINT32 ctrl16_arbiter_ecc_bypass_15; + ZXIC_UINT32 ctrl16_arbiter_ecc_bypass_14; + ZXIC_UINT32 ctrl16_arbiter_ecc_bypass_13; + ZXIC_UINT32 ctrl16_arbiter_ecc_bypass_12; + ZXIC_UINT32 ctrl16_arbiter_ecc_bypass_11; + ZXIC_UINT32 ctrl16_arbiter_ecc_bypass_10; + ZXIC_UINT32 ctrl16_arbiter_ecc_bypass_9; + ZXIC_UINT32 ctrl16_arbiter_ecc_bypass_8; + ZXIC_UINT32 ctrl16_arbiter_ecc_bypass_7; + ZXIC_UINT32 ctrl16_arbiter_ecc_bypass_6; + ZXIC_UINT32 ctrl16_arbiter_ecc_bypass_5; + ZXIC_UINT32 ctrl16_arbiter_ecc_bypass_4; + ZXIC_UINT32 ctrl16_arbiter_ecc_bypass_3; + ZXIC_UINT32 ctrl16_arbiter_ecc_bypass_2; + ZXIC_UINT32 ctrl16_arbiter_ecc_bypass_1; + ZXIC_UINT32 ctrl16_arbiter_ecc_bypass_0; +}DPP_SMMU0_SMMU0_CTRL16_ARBITER_ECC_BYPASS_T; + +typedef struct dpp_smmu0_smmu0_ctrl18_arbiter_ecc_bypass_t +{ + ZXIC_UINT32 ctrl19_arbiter_ecc_bypass_15; + ZXIC_UINT32 ctrl19_arbiter_ecc_bypass_14; + ZXIC_UINT32 ctrl19_arbiter_ecc_bypass_13; + ZXIC_UINT32 ctrl19_arbiter_ecc_bypass_12; + ZXIC_UINT32 ctrl19_arbiter_ecc_bypass_11; + ZXIC_UINT32 ctrl19_arbiter_ecc_bypass_10; + ZXIC_UINT32 ctrl19_arbiter_ecc_bypass_9; + ZXIC_UINT32 ctrl19_arbiter_ecc_bypass_8; + ZXIC_UINT32 ctrl19_arbiter_ecc_bypass_7; + ZXIC_UINT32 ctrl19_arbiter_ecc_bypass_6; + ZXIC_UINT32 ctrl19_arbiter_ecc_bypass_5; + ZXIC_UINT32 ctrl19_arbiter_ecc_bypass_4; + ZXIC_UINT32 ctrl19_arbiter_ecc_bypass_3; + ZXIC_UINT32 ctrl19_arbiter_ecc_bypass_2; + ZXIC_UINT32 ctrl19_arbiter_ecc_bypass_1; + ZXIC_UINT32 ctrl19_arbiter_ecc_bypass_0; + ZXIC_UINT32 ctrl18_arbiter_ecc_bypass_15; + ZXIC_UINT32 ctrl18_arbiter_ecc_bypass_14; + ZXIC_UINT32 ctrl18_arbiter_ecc_bypass_13; + ZXIC_UINT32 ctrl18_arbiter_ecc_bypass_12; + ZXIC_UINT32 ctrl18_arbiter_ecc_bypass_11; + ZXIC_UINT32 ctrl18_arbiter_ecc_bypass_10; + ZXIC_UINT32 ctrl18_arbiter_ecc_bypass_9; + ZXIC_UINT32 ctrl18_arbiter_ecc_bypass_8; + ZXIC_UINT32 ctrl18_arbiter_ecc_bypass_7; + ZXIC_UINT32 ctrl18_arbiter_ecc_bypass_6; + ZXIC_UINT32 ctrl18_arbiter_ecc_bypass_5; + ZXIC_UINT32 ctrl18_arbiter_ecc_bypass_4; + ZXIC_UINT32 ctrl18_arbiter_ecc_bypass_3; + ZXIC_UINT32 ctrl18_arbiter_ecc_bypass_2; + ZXIC_UINT32 ctrl18_arbiter_ecc_bypass_1; + ZXIC_UINT32 ctrl18_arbiter_ecc_bypass_0; +}DPP_SMMU0_SMMU0_CTRL18_ARBITER_ECC_BYPASS_T; + +typedef struct dpp_smmu0_smmu0_ctrl20_arbiter_ecc_bypass_t +{ + ZXIC_UINT32 ctrl21_arbiter_ecc_bypass_15; + ZXIC_UINT32 ctrl21_arbiter_ecc_bypass_14; + ZXIC_UINT32 ctrl21_arbiter_ecc_bypass_13; + ZXIC_UINT32 ctrl21_arbiter_ecc_bypass_12; + ZXIC_UINT32 ctrl21_arbiter_ecc_bypass_11; + ZXIC_UINT32 ctrl21_arbiter_ecc_bypass_10; + ZXIC_UINT32 ctrl21_arbiter_ecc_bypass_9; + ZXIC_UINT32 ctrl21_arbiter_ecc_bypass_8; + ZXIC_UINT32 ctrl21_arbiter_ecc_bypass_7; + ZXIC_UINT32 ctrl21_arbiter_ecc_bypass_6; + ZXIC_UINT32 ctrl21_arbiter_ecc_bypass_5; + ZXIC_UINT32 ctrl21_arbiter_ecc_bypass_4; + ZXIC_UINT32 ctrl21_arbiter_ecc_bypass_3; + ZXIC_UINT32 ctrl21_arbiter_ecc_bypass_2; + ZXIC_UINT32 ctrl21_arbiter_ecc_bypass_1; + ZXIC_UINT32 ctrl21_arbiter_ecc_bypass_0; + ZXIC_UINT32 ctrl20_arbiter_ecc_bypass_15; + ZXIC_UINT32 ctrl20_arbiter_ecc_bypass_14; + ZXIC_UINT32 ctrl20_arbiter_ecc_bypass_13; + ZXIC_UINT32 ctrl20_arbiter_ecc_bypass_12; + ZXIC_UINT32 ctrl20_arbiter_ecc_bypass_11; + ZXIC_UINT32 ctrl20_arbiter_ecc_bypass_10; + ZXIC_UINT32 ctrl20_arbiter_ecc_bypass_9; + ZXIC_UINT32 ctrl20_arbiter_ecc_bypass_8; + ZXIC_UINT32 ctrl20_arbiter_ecc_bypass_7; + ZXIC_UINT32 ctrl20_arbiter_ecc_bypass_6; + ZXIC_UINT32 ctrl20_arbiter_ecc_bypass_5; + ZXIC_UINT32 ctrl20_arbiter_ecc_bypass_4; + ZXIC_UINT32 ctrl20_arbiter_ecc_bypass_3; + ZXIC_UINT32 ctrl20_arbiter_ecc_bypass_2; + ZXIC_UINT32 ctrl20_arbiter_ecc_bypass_1; + ZXIC_UINT32 ctrl20_arbiter_ecc_bypass_0; +}DPP_SMMU0_SMMU0_CTRL20_ARBITER_ECC_BYPASS_T; + +typedef struct dpp_smmu0_smmu0_ctrl22_arbiter_ecc_bypass_t +{ + ZXIC_UINT32 ctrl23_arbiter_ecc_bypass_15; + ZXIC_UINT32 ctrl23_arbiter_ecc_bypass_14; + ZXIC_UINT32 ctrl23_arbiter_ecc_bypass_13; + ZXIC_UINT32 ctrl23_arbiter_ecc_bypass_12; + ZXIC_UINT32 ctrl23_arbiter_ecc_bypass_11; + ZXIC_UINT32 ctrl23_arbiter_ecc_bypass_10; + ZXIC_UINT32 ctrl23_arbiter_ecc_bypass_9; + ZXIC_UINT32 ctrl23_arbiter_ecc_bypass_8; + ZXIC_UINT32 ctrl23_arbiter_ecc_bypass_7; + ZXIC_UINT32 ctrl23_arbiter_ecc_bypass_6; + ZXIC_UINT32 ctrl23_arbiter_ecc_bypass_5; + ZXIC_UINT32 ctrl23_arbiter_ecc_bypass_4; + ZXIC_UINT32 ctrl23_arbiter_ecc_bypass_3; + ZXIC_UINT32 ctrl23_arbiter_ecc_bypass_2; + ZXIC_UINT32 ctrl23_arbiter_ecc_bypass_1; + ZXIC_UINT32 ctrl23_arbiter_ecc_bypass_0; + ZXIC_UINT32 ctrl22_arbiter_ecc_bypass_15; + ZXIC_UINT32 ctrl22_arbiter_ecc_bypass_14; + ZXIC_UINT32 ctrl22_arbiter_ecc_bypass_13; + ZXIC_UINT32 ctrl22_arbiter_ecc_bypass_12; + ZXIC_UINT32 ctrl22_arbiter_ecc_bypass_11; + ZXIC_UINT32 ctrl22_arbiter_ecc_bypass_10; + ZXIC_UINT32 ctrl22_arbiter_ecc_bypass_9; + ZXIC_UINT32 ctrl22_arbiter_ecc_bypass_8; + ZXIC_UINT32 ctrl22_arbiter_ecc_bypass_7; + ZXIC_UINT32 ctrl22_arbiter_ecc_bypass_6; + ZXIC_UINT32 ctrl22_arbiter_ecc_bypass_5; + ZXIC_UINT32 ctrl22_arbiter_ecc_bypass_4; + ZXIC_UINT32 ctrl22_arbiter_ecc_bypass_3; + ZXIC_UINT32 ctrl22_arbiter_ecc_bypass_2; + ZXIC_UINT32 ctrl22_arbiter_ecc_bypass_1; + ZXIC_UINT32 ctrl22_arbiter_ecc_bypass_0; +}DPP_SMMU0_SMMU0_CTRL22_ARBITER_ECC_BYPASS_T; + +typedef struct dpp_smmu0_smmu0_ctrl24_arbiter_ecc_bypass_t +{ + ZXIC_UINT32 ctrl25_arbiter_ecc_bypass_15; + ZXIC_UINT32 ctrl25_arbiter_ecc_bypass_14; + ZXIC_UINT32 ctrl25_arbiter_ecc_bypass_13; + ZXIC_UINT32 ctrl25_arbiter_ecc_bypass_12; + ZXIC_UINT32 ctrl25_arbiter_ecc_bypass_11; + ZXIC_UINT32 ctrl25_arbiter_ecc_bypass_10; + ZXIC_UINT32 ctrl25_arbiter_ecc_bypass_9; + ZXIC_UINT32 ctrl25_arbiter_ecc_bypass_8; + ZXIC_UINT32 ctrl25_arbiter_ecc_bypass_7; + ZXIC_UINT32 ctrl25_arbiter_ecc_bypass_6; + ZXIC_UINT32 ctrl25_arbiter_ecc_bypass_5; + ZXIC_UINT32 ctrl25_arbiter_ecc_bypass_4; + ZXIC_UINT32 ctrl25_arbiter_ecc_bypass_3; + ZXIC_UINT32 ctrl25_arbiter_ecc_bypass_2; + ZXIC_UINT32 ctrl25_arbiter_ecc_bypass_1; + ZXIC_UINT32 ctrl25_arbiter_ecc_bypass_0; + ZXIC_UINT32 ctrl24_arbiter_ecc_bypass_15; + ZXIC_UINT32 ctrl24_arbiter_ecc_bypass_14; + ZXIC_UINT32 ctrl24_arbiter_ecc_bypass_13; + ZXIC_UINT32 ctrl24_arbiter_ecc_bypass_12; + ZXIC_UINT32 ctrl24_arbiter_ecc_bypass_11; + ZXIC_UINT32 ctrl24_arbiter_ecc_bypass_10; + ZXIC_UINT32 ctrl24_arbiter_ecc_bypass_9; + ZXIC_UINT32 ctrl24_arbiter_ecc_bypass_8; + ZXIC_UINT32 ctrl24_arbiter_ecc_bypass_7; + ZXIC_UINT32 ctrl24_arbiter_ecc_bypass_6; + ZXIC_UINT32 ctrl24_arbiter_ecc_bypass_5; + ZXIC_UINT32 ctrl24_arbiter_ecc_bypass_4; + ZXIC_UINT32 ctrl24_arbiter_ecc_bypass_3; + ZXIC_UINT32 ctrl24_arbiter_ecc_bypass_2; + ZXIC_UINT32 ctrl24_arbiter_ecc_bypass_1; + ZXIC_UINT32 ctrl24_arbiter_ecc_bypass_0; +}DPP_SMMU0_SMMU0_CTRL24_ARBITER_ECC_BYPASS_T; + +typedef struct dpp_smmu0_smmu0_ctrl26_arbiter_ecc_bypass_t +{ + ZXIC_UINT32 ctrl27_arbiter_ecc_bypass_15; + ZXIC_UINT32 ctrl27_arbiter_ecc_bypass_14; + ZXIC_UINT32 ctrl27_arbiter_ecc_bypass_13; + ZXIC_UINT32 ctrl27_arbiter_ecc_bypass_12; + ZXIC_UINT32 ctrl27_arbiter_ecc_bypass_11; + ZXIC_UINT32 ctrl27_arbiter_ecc_bypass_10; + ZXIC_UINT32 ctrl27_arbiter_ecc_bypass_9; + ZXIC_UINT32 ctrl27_arbiter_ecc_bypass_8; + ZXIC_UINT32 ctrl27_arbiter_ecc_bypass_7; + ZXIC_UINT32 ctrl27_arbiter_ecc_bypass_6; + ZXIC_UINT32 ctrl27_arbiter_ecc_bypass_5; + ZXIC_UINT32 ctrl27_arbiter_ecc_bypass_4; + ZXIC_UINT32 ctrl27_arbiter_ecc_bypass_3; + ZXIC_UINT32 ctrl27_arbiter_ecc_bypass_2; + ZXIC_UINT32 ctrl27_arbiter_ecc_bypass_1; + ZXIC_UINT32 ctrl27_arbiter_ecc_bypass_0; + ZXIC_UINT32 ctrl26_arbiter_ecc_bypass_15; + ZXIC_UINT32 ctrl26_arbiter_ecc_bypass_14; + ZXIC_UINT32 ctrl26_arbiter_ecc_bypass_13; + ZXIC_UINT32 ctrl26_arbiter_ecc_bypass_12; + ZXIC_UINT32 ctrl26_arbiter_ecc_bypass_11; + ZXIC_UINT32 ctrl26_arbiter_ecc_bypass_10; + ZXIC_UINT32 ctrl26_arbiter_ecc_bypass_9; + ZXIC_UINT32 ctrl26_arbiter_ecc_bypass_8; + ZXIC_UINT32 ctrl26_arbiter_ecc_bypass_7; + ZXIC_UINT32 ctrl26_arbiter_ecc_bypass_6; + ZXIC_UINT32 ctrl26_arbiter_ecc_bypass_5; + ZXIC_UINT32 ctrl26_arbiter_ecc_bypass_4; + ZXIC_UINT32 ctrl26_arbiter_ecc_bypass_3; + ZXIC_UINT32 ctrl26_arbiter_ecc_bypass_2; + ZXIC_UINT32 ctrl26_arbiter_ecc_bypass_1; + ZXIC_UINT32 ctrl26_arbiter_ecc_bypass_0; +}DPP_SMMU0_SMMU0_CTRL26_ARBITER_ECC_BYPASS_T; + +typedef struct dpp_smmu0_smmu0_ctrl28_arbiter_ecc_bypass_t +{ + ZXIC_UINT32 ctrl29_arbiter_ecc_bypass_15; + ZXIC_UINT32 ctrl29_arbiter_ecc_bypass_14; + ZXIC_UINT32 ctrl29_arbiter_ecc_bypass_13; + ZXIC_UINT32 ctrl29_arbiter_ecc_bypass_12; + ZXIC_UINT32 ctrl29_arbiter_ecc_bypass_11; + ZXIC_UINT32 ctrl29_arbiter_ecc_bypass_10; + ZXIC_UINT32 ctrl29_arbiter_ecc_bypass_9; + ZXIC_UINT32 ctrl29_arbiter_ecc_bypass_8; + ZXIC_UINT32 ctrl29_arbiter_ecc_bypass_7; + ZXIC_UINT32 ctrl29_arbiter_ecc_bypass_6; + ZXIC_UINT32 ctrl29_arbiter_ecc_bypass_5; + ZXIC_UINT32 ctrl29_arbiter_ecc_bypass_4; + ZXIC_UINT32 ctrl29_arbiter_ecc_bypass_3; + ZXIC_UINT32 ctrl29_arbiter_ecc_bypass_2; + ZXIC_UINT32 ctrl29_arbiter_ecc_bypass_1; + ZXIC_UINT32 ctrl29_arbiter_ecc_bypass_0; + ZXIC_UINT32 ctrl28_arbiter_ecc_bypass_15; + ZXIC_UINT32 ctrl28_arbiter_ecc_bypass_14; + ZXIC_UINT32 ctrl28_arbiter_ecc_bypass_13; + ZXIC_UINT32 ctrl28_arbiter_ecc_bypass_12; + ZXIC_UINT32 ctrl28_arbiter_ecc_bypass_11; + ZXIC_UINT32 ctrl28_arbiter_ecc_bypass_10; + ZXIC_UINT32 ctrl28_arbiter_ecc_bypass_9; + ZXIC_UINT32 ctrl28_arbiter_ecc_bypass_8; + ZXIC_UINT32 ctrl28_arbiter_ecc_bypass_7; + ZXIC_UINT32 ctrl28_arbiter_ecc_bypass_6; + ZXIC_UINT32 ctrl28_arbiter_ecc_bypass_5; + ZXIC_UINT32 ctrl28_arbiter_ecc_bypass_4; + ZXIC_UINT32 ctrl28_arbiter_ecc_bypass_3; + ZXIC_UINT32 ctrl28_arbiter_ecc_bypass_2; + ZXIC_UINT32 ctrl28_arbiter_ecc_bypass_1; + ZXIC_UINT32 ctrl28_arbiter_ecc_bypass_0; +}DPP_SMMU0_SMMU0_CTRL28_ARBITER_ECC_BYPASS_T; + +typedef struct dpp_smmu0_smmu0_ctrl30_arbiter_ecc_bypass_t +{ + ZXIC_UINT32 ctrl31_arbiter_ecc_bypass_15; + ZXIC_UINT32 ctrl31_arbiter_ecc_bypass_14; + ZXIC_UINT32 ctrl31_arbiter_ecc_bypass_13; + ZXIC_UINT32 ctrl31_arbiter_ecc_bypass_12; + ZXIC_UINT32 ctrl31_arbiter_ecc_bypass_11; + ZXIC_UINT32 ctrl31_arbiter_ecc_bypass_10; + ZXIC_UINT32 ctrl31_arbiter_ecc_bypass_9; + ZXIC_UINT32 ctrl31_arbiter_ecc_bypass_8; + ZXIC_UINT32 ctrl31_arbiter_ecc_bypass_7; + ZXIC_UINT32 ctrl31_arbiter_ecc_bypass_6; + ZXIC_UINT32 ctrl31_arbiter_ecc_bypass_5; + ZXIC_UINT32 ctrl31_arbiter_ecc_bypass_4; + ZXIC_UINT32 ctrl31_arbiter_ecc_bypass_3; + ZXIC_UINT32 ctrl31_arbiter_ecc_bypass_2; + ZXIC_UINT32 ctrl31_arbiter_ecc_bypass_1; + ZXIC_UINT32 ctrl31_arbiter_ecc_bypass_0; + ZXIC_UINT32 ctrl30_arbiter_ecc_bypass_15; + ZXIC_UINT32 ctrl30_arbiter_ecc_bypass_14; + ZXIC_UINT32 ctrl30_arbiter_ecc_bypass_13; + ZXIC_UINT32 ctrl30_arbiter_ecc_bypass_12; + ZXIC_UINT32 ctrl30_arbiter_ecc_bypass_11; + ZXIC_UINT32 ctrl30_arbiter_ecc_bypass_10; + ZXIC_UINT32 ctrl30_arbiter_ecc_bypass_9; + ZXIC_UINT32 ctrl30_arbiter_ecc_bypass_8; + ZXIC_UINT32 ctrl30_arbiter_ecc_bypass_7; + ZXIC_UINT32 ctrl30_arbiter_ecc_bypass_6; + ZXIC_UINT32 ctrl30_arbiter_ecc_bypass_5; + ZXIC_UINT32 ctrl30_arbiter_ecc_bypass_4; + ZXIC_UINT32 ctrl30_arbiter_ecc_bypass_3; + ZXIC_UINT32 ctrl30_arbiter_ecc_bypass_2; + ZXIC_UINT32 ctrl30_arbiter_ecc_bypass_1; + ZXIC_UINT32 ctrl30_arbiter_ecc_bypass_0; +}DPP_SMMU0_SMMU0_CTRL30_ARBITER_ECC_BYPASS_T; + +typedef struct dpp_smmu0_smmu0_ctrl_req_ecc_bypass_t +{ + ZXIC_UINT32 ctrl_req_ecc_bypass_0_31; +}DPP_SMMU0_SMMU0_CTRL_REQ_ECC_BYPASS_T; + +typedef struct dpp_smmu0_smmu0_ctrl_info_ecc_bypass_t +{ + ZXIC_UINT32 ctrl_info_ecc_bypass_0_31; +}DPP_SMMU0_SMMU0_CTRL_INFO_ECC_BYPASS_T; + +typedef struct dpp_smmu0_smmu0_smmu0_rschd_ecc_bypass_t +{ + ZXIC_UINT32 smmu0_rschd_ecc_bypass_0_31; +}DPP_SMMU0_SMMU0_SMMU0_RSCHD_ECC_BYPASS_T; + +typedef struct dpp_smmu0_smmu0_smmu0_wr_ecc_bypass_t +{ + ZXIC_UINT32 smmu0_wr_ecc_bypass1; + ZXIC_UINT32 smmu0_wr_ecc_bypass0; +}DPP_SMMU0_SMMU0_SMMU0_WR_ECC_BYPASS_T; + +typedef struct dpp_smmu0_smmu0_ctrl0_arbiter_ecc_err_t +{ + ZXIC_UINT32 ctrl0_arbiter_ecc_err_31; + ZXIC_UINT32 ctrl0_arbiter_ecc_err_30; + ZXIC_UINT32 ctrl0_arbiter_ecc_err_29; + ZXIC_UINT32 ctrl0_arbiter_ecc_err_28; + ZXIC_UINT32 ctrl0_arbiter_ecc_err_27; + ZXIC_UINT32 ctrl0_arbiter_ecc_err_26; + ZXIC_UINT32 ctrl0_arbiter_ecc_err_25; + ZXIC_UINT32 ctrl0_arbiter_ecc_err_24; + ZXIC_UINT32 ctrl0_arbiter_ecc_err_23; + ZXIC_UINT32 ctrl0_arbiter_ecc_err_22; + ZXIC_UINT32 ctrl0_arbiter_ecc_err_21; + ZXIC_UINT32 ctrl0_arbiter_ecc_err_20; + ZXIC_UINT32 ctrl0_arbiter_ecc_err_19; + ZXIC_UINT32 ctrl0_arbiter_ecc_err_18; + ZXIC_UINT32 ctrl0_arbiter_ecc_err_17; + ZXIC_UINT32 ctrl0_arbiter_ecc_err_16; + ZXIC_UINT32 ctrl0_arbiter_ecc_err_15; + ZXIC_UINT32 ctrl0_arbiter_ecc_err_14; + ZXIC_UINT32 ctrl0_arbiter_ecc_err_13; + ZXIC_UINT32 ctrl0_arbiter_ecc_err_12; + ZXIC_UINT32 ctrl0_arbiter_ecc_err_11; + ZXIC_UINT32 ctrl0_arbiter_ecc_err_10; + ZXIC_UINT32 ctrl0_arbiter_ecc_err_9; + ZXIC_UINT32 ctrl0_arbiter_ecc_err_8; + ZXIC_UINT32 ctrl0_arbiter_ecc_err_7; + ZXIC_UINT32 ctrl0_arbiter_ecc_err_6; + ZXIC_UINT32 ctrl0_arbiter_ecc_err_5; + ZXIC_UINT32 ctrl0_arbiter_ecc_err_4; + ZXIC_UINT32 ctrl0_arbiter_ecc_err_3; + ZXIC_UINT32 ctrl0_arbiter_ecc_err_2; + ZXIC_UINT32 ctrl0_arbiter_ecc_err_1; + ZXIC_UINT32 ctrl0_arbiter_ecc_err_0; +}DPP_SMMU0_SMMU0_CTRL0_ARBITER_ECC_ERR_T; + +typedef struct dpp_smmu0_smmu0_ctrl1_arbiter_ecc_err_t +{ + ZXIC_UINT32 ctrl1_arbiter_ecc_err_31; + ZXIC_UINT32 ctrl1_arbiter_ecc_err_30; + ZXIC_UINT32 ctrl1_arbiter_ecc_err_29; + ZXIC_UINT32 ctrl1_arbiter_ecc_err_28; + ZXIC_UINT32 ctrl1_arbiter_ecc_err_27; + ZXIC_UINT32 ctrl1_arbiter_ecc_err_26; + ZXIC_UINT32 ctrl1_arbiter_ecc_err_25; + ZXIC_UINT32 ctrl1_arbiter_ecc_err_24; + ZXIC_UINT32 ctrl1_arbiter_ecc_err_23; + ZXIC_UINT32 ctrl1_arbiter_ecc_err_22; + ZXIC_UINT32 ctrl1_arbiter_ecc_err_21; + ZXIC_UINT32 ctrl1_arbiter_ecc_err_20; + ZXIC_UINT32 ctrl1_arbiter_ecc_err_19; + ZXIC_UINT32 ctrl1_arbiter_ecc_err_18; + ZXIC_UINT32 ctrl1_arbiter_ecc_err_17; + ZXIC_UINT32 ctrl1_arbiter_ecc_err_16; + ZXIC_UINT32 ctrl1_arbiter_ecc_err_15; + ZXIC_UINT32 ctrl1_arbiter_ecc_err_14; + ZXIC_UINT32 ctrl1_arbiter_ecc_err_13; + ZXIC_UINT32 ctrl1_arbiter_ecc_err_12; + ZXIC_UINT32 ctrl1_arbiter_ecc_err_11; + ZXIC_UINT32 ctrl1_arbiter_ecc_err_10; + ZXIC_UINT32 ctrl1_arbiter_ecc_err_9; + ZXIC_UINT32 ctrl1_arbiter_ecc_err_8; + ZXIC_UINT32 ctrl1_arbiter_ecc_err_7; + ZXIC_UINT32 ctrl1_arbiter_ecc_err_6; + ZXIC_UINT32 ctrl1_arbiter_ecc_err_5; + ZXIC_UINT32 ctrl1_arbiter_ecc_err_4; + ZXIC_UINT32 ctrl1_arbiter_ecc_err_3; + ZXIC_UINT32 ctrl1_arbiter_ecc_err_2; + ZXIC_UINT32 ctrl1_arbiter_ecc_err_1; + ZXIC_UINT32 ctrl1_arbiter_ecc_err_0; +}DPP_SMMU0_SMMU0_CTRL1_ARBITER_ECC_ERR_T; + +typedef struct dpp_smmu0_smmu0_ctrl2_arbiter_ecc_err_t +{ + ZXIC_UINT32 ctrl2_arbiter_ecc_err_31; + ZXIC_UINT32 ctrl2_arbiter_ecc_err_30; + ZXIC_UINT32 ctrl2_arbiter_ecc_err_29; + ZXIC_UINT32 ctrl2_arbiter_ecc_err_28; + ZXIC_UINT32 ctrl2_arbiter_ecc_err_27; + ZXIC_UINT32 ctrl2_arbiter_ecc_err_26; + ZXIC_UINT32 ctrl2_arbiter_ecc_err_25; + ZXIC_UINT32 ctrl2_arbiter_ecc_err_24; + ZXIC_UINT32 ctrl2_arbiter_ecc_err_23; + ZXIC_UINT32 ctrl2_arbiter_ecc_err_22; + ZXIC_UINT32 ctrl2_arbiter_ecc_err_21; + ZXIC_UINT32 ctrl2_arbiter_ecc_err_20; + ZXIC_UINT32 ctrl2_arbiter_ecc_err_19; + ZXIC_UINT32 ctrl2_arbiter_ecc_err_18; + ZXIC_UINT32 ctrl2_arbiter_ecc_err_17; + ZXIC_UINT32 ctrl2_arbiter_ecc_err_16; + ZXIC_UINT32 ctrl2_arbiter_ecc_err_15; + ZXIC_UINT32 ctrl2_arbiter_ecc_err_14; + ZXIC_UINT32 ctrl2_arbiter_ecc_err_13; + ZXIC_UINT32 ctrl2_arbiter_ecc_err_12; + ZXIC_UINT32 ctrl2_arbiter_ecc_err_11; + ZXIC_UINT32 ctrl2_arbiter_ecc_err_10; + ZXIC_UINT32 ctrl2_arbiter_ecc_err_9; + ZXIC_UINT32 ctrl2_arbiter_ecc_err_8; + ZXIC_UINT32 ctrl2_arbiter_ecc_err_7; + ZXIC_UINT32 ctrl2_arbiter_ecc_err_6; + ZXIC_UINT32 ctrl2_arbiter_ecc_err_5; + ZXIC_UINT32 ctrl2_arbiter_ecc_err_4; + ZXIC_UINT32 ctrl2_arbiter_ecc_err_3; + ZXIC_UINT32 ctrl2_arbiter_ecc_err_2; + ZXIC_UINT32 ctrl2_arbiter_ecc_err_1; + ZXIC_UINT32 ctrl2_arbiter_ecc_err_0; +}DPP_SMMU0_SMMU0_CTRL2_ARBITER_ECC_ERR_T; + +typedef struct dpp_smmu0_smmu0_ctrl3_arbiter_ecc_err_t +{ + ZXIC_UINT32 ctrl3_arbiter_ecc_err_31; + ZXIC_UINT32 ctrl3_arbiter_ecc_err_30; + ZXIC_UINT32 ctrl3_arbiter_ecc_err_29; + ZXIC_UINT32 ctrl3_arbiter_ecc_err_28; + ZXIC_UINT32 ctrl3_arbiter_ecc_err_27; + ZXIC_UINT32 ctrl3_arbiter_ecc_err_26; + ZXIC_UINT32 ctrl3_arbiter_ecc_err_25; + ZXIC_UINT32 ctrl3_arbiter_ecc_err_24; + ZXIC_UINT32 ctrl3_arbiter_ecc_err_23; + ZXIC_UINT32 ctrl3_arbiter_ecc_err_22; + ZXIC_UINT32 ctrl3_arbiter_ecc_err_21; + ZXIC_UINT32 ctrl3_arbiter_ecc_err_20; + ZXIC_UINT32 ctrl3_arbiter_ecc_err_19; + ZXIC_UINT32 ctrl3_arbiter_ecc_err_18; + ZXIC_UINT32 ctrl3_arbiter_ecc_err_17; + ZXIC_UINT32 ctrl3_arbiter_ecc_err_16; + ZXIC_UINT32 ctrl3_arbiter_ecc_err_15; + ZXIC_UINT32 ctrl3_arbiter_ecc_err_14; + ZXIC_UINT32 ctrl3_arbiter_ecc_err_13; + ZXIC_UINT32 ctrl3_arbiter_ecc_err_12; + ZXIC_UINT32 ctrl3_arbiter_ecc_err_11; + ZXIC_UINT32 ctrl3_arbiter_ecc_err_10; + ZXIC_UINT32 ctrl3_arbiter_ecc_err_9; + ZXIC_UINT32 ctrl3_arbiter_ecc_err_8; + ZXIC_UINT32 ctrl3_arbiter_ecc_err_7; + ZXIC_UINT32 ctrl3_arbiter_ecc_err_6; + ZXIC_UINT32 ctrl3_arbiter_ecc_err_5; + ZXIC_UINT32 ctrl3_arbiter_ecc_err_4; + ZXIC_UINT32 ctrl3_arbiter_ecc_err_3; + ZXIC_UINT32 ctrl3_arbiter_ecc_err_2; + ZXIC_UINT32 ctrl3_arbiter_ecc_err_1; + ZXIC_UINT32 ctrl3_arbiter_ecc_err_0; +}DPP_SMMU0_SMMU0_CTRL3_ARBITER_ECC_ERR_T; + +typedef struct dpp_smmu0_smmu0_ctrl4_arbiter_ecc_err_t +{ + ZXIC_UINT32 ctrl4_arbiter_ecc_err_31; + ZXIC_UINT32 ctrl4_arbiter_ecc_err_30; + ZXIC_UINT32 ctrl4_arbiter_ecc_err_29; + ZXIC_UINT32 ctrl4_arbiter_ecc_err_28; + ZXIC_UINT32 ctrl4_arbiter_ecc_err_27; + ZXIC_UINT32 ctrl4_arbiter_ecc_err_26; + ZXIC_UINT32 ctrl4_arbiter_ecc_err_25; + ZXIC_UINT32 ctrl4_arbiter_ecc_err_24; + ZXIC_UINT32 ctrl4_arbiter_ecc_err_23; + ZXIC_UINT32 ctrl4_arbiter_ecc_err_22; + ZXIC_UINT32 ctrl4_arbiter_ecc_err_21; + ZXIC_UINT32 ctrl4_arbiter_ecc_err_20; + ZXIC_UINT32 ctrl4_arbiter_ecc_err_19; + ZXIC_UINT32 ctrl4_arbiter_ecc_err_18; + ZXIC_UINT32 ctrl4_arbiter_ecc_err_17; + ZXIC_UINT32 ctrl4_arbiter_ecc_err_16; + ZXIC_UINT32 ctrl4_arbiter_ecc_err_15; + ZXIC_UINT32 ctrl4_arbiter_ecc_err_14; + ZXIC_UINT32 ctrl4_arbiter_ecc_err_13; + ZXIC_UINT32 ctrl4_arbiter_ecc_err_12; + ZXIC_UINT32 ctrl4_arbiter_ecc_err_11; + ZXIC_UINT32 ctrl4_arbiter_ecc_err_10; + ZXIC_UINT32 ctrl4_arbiter_ecc_err_9; + ZXIC_UINT32 ctrl4_arbiter_ecc_err_8; + ZXIC_UINT32 ctrl4_arbiter_ecc_err_7; + ZXIC_UINT32 ctrl4_arbiter_ecc_err_6; + ZXIC_UINT32 ctrl4_arbiter_ecc_err_5; + ZXIC_UINT32 ctrl4_arbiter_ecc_err_4; + ZXIC_UINT32 ctrl4_arbiter_ecc_err_3; + ZXIC_UINT32 ctrl4_arbiter_ecc_err_2; + ZXIC_UINT32 ctrl4_arbiter_ecc_err_1; + ZXIC_UINT32 ctrl4_arbiter_ecc_err_0; +}DPP_SMMU0_SMMU0_CTRL4_ARBITER_ECC_ERR_T; + +typedef struct dpp_smmu0_smmu0_ctrl5_arbiter_ecc_err_t +{ + ZXIC_UINT32 ctrl5_arbiter_ecc_err_31; + ZXIC_UINT32 ctrl5_arbiter_ecc_err_30; + ZXIC_UINT32 ctrl5_arbiter_ecc_err_29; + ZXIC_UINT32 ctrl5_arbiter_ecc_err_28; + ZXIC_UINT32 ctrl5_arbiter_ecc_err_27; + ZXIC_UINT32 ctrl5_arbiter_ecc_err_26; + ZXIC_UINT32 ctrl5_arbiter_ecc_err_25; + ZXIC_UINT32 ctrl5_arbiter_ecc_err_24; + ZXIC_UINT32 ctrl5_arbiter_ecc_err_23; + ZXIC_UINT32 ctrl5_arbiter_ecc_err_22; + ZXIC_UINT32 ctrl5_arbiter_ecc_err_21; + ZXIC_UINT32 ctrl5_arbiter_ecc_err_20; + ZXIC_UINT32 ctrl5_arbiter_ecc_err_19; + ZXIC_UINT32 ctrl5_arbiter_ecc_err_18; + ZXIC_UINT32 ctrl5_arbiter_ecc_err_17; + ZXIC_UINT32 ctrl5_arbiter_ecc_err_16; + ZXIC_UINT32 ctrl5_arbiter_ecc_err_15; + ZXIC_UINT32 ctrl5_arbiter_ecc_err_14; + ZXIC_UINT32 ctrl5_arbiter_ecc_err_13; + ZXIC_UINT32 ctrl5_arbiter_ecc_err_12; + ZXIC_UINT32 ctrl5_arbiter_ecc_err_11; + ZXIC_UINT32 ctrl5_arbiter_ecc_err_10; + ZXIC_UINT32 ctrl5_arbiter_ecc_err_9; + ZXIC_UINT32 ctrl5_arbiter_ecc_err_8; + ZXIC_UINT32 ctrl5_arbiter_ecc_err_7; + ZXIC_UINT32 ctrl5_arbiter_ecc_err_6; + ZXIC_UINT32 ctrl5_arbiter_ecc_err_5; + ZXIC_UINT32 ctrl5_arbiter_ecc_err_4; + ZXIC_UINT32 ctrl5_arbiter_ecc_err_3; + ZXIC_UINT32 ctrl5_arbiter_ecc_err_2; + ZXIC_UINT32 ctrl5_arbiter_ecc_err_1; + ZXIC_UINT32 ctrl5_arbiter_ecc_err_0; +}DPP_SMMU0_SMMU0_CTRL5_ARBITER_ECC_ERR_T; + +typedef struct dpp_smmu0_smmu0_ctrl6_arbiter_ecc_err_t +{ + ZXIC_UINT32 ctrl6_arbiter_ecc_err_31; + ZXIC_UINT32 ctrl6_arbiter_ecc_err_30; + ZXIC_UINT32 ctrl6_arbiter_ecc_err_29; + ZXIC_UINT32 ctrl6_arbiter_ecc_err_28; + ZXIC_UINT32 ctrl6_arbiter_ecc_err_27; + ZXIC_UINT32 ctrl6_arbiter_ecc_err_26; + ZXIC_UINT32 ctrl6_arbiter_ecc_err_25; + ZXIC_UINT32 ctrl6_arbiter_ecc_err_24; + ZXIC_UINT32 ctrl6_arbiter_ecc_err_23; + ZXIC_UINT32 ctrl6_arbiter_ecc_err_22; + ZXIC_UINT32 ctrl6_arbiter_ecc_err_21; + ZXIC_UINT32 ctrl6_arbiter_ecc_err_20; + ZXIC_UINT32 ctrl6_arbiter_ecc_err_19; + ZXIC_UINT32 ctrl6_arbiter_ecc_err_18; + ZXIC_UINT32 ctrl6_arbiter_ecc_err_17; + ZXIC_UINT32 ctrl6_arbiter_ecc_err_16; + ZXIC_UINT32 ctrl6_arbiter_ecc_err_15; + ZXIC_UINT32 ctrl6_arbiter_ecc_err_14; + ZXIC_UINT32 ctrl6_arbiter_ecc_err_13; + ZXIC_UINT32 ctrl6_arbiter_ecc_err_12; + ZXIC_UINT32 ctrl6_arbiter_ecc_err_11; + ZXIC_UINT32 ctrl6_arbiter_ecc_err_10; + ZXIC_UINT32 ctrl6_arbiter_ecc_err_9; + ZXIC_UINT32 ctrl6_arbiter_ecc_err_8; + ZXIC_UINT32 ctrl6_arbiter_ecc_err_7; + ZXIC_UINT32 ctrl6_arbiter_ecc_err_6; + ZXIC_UINT32 ctrl6_arbiter_ecc_err_5; + ZXIC_UINT32 ctrl6_arbiter_ecc_err_4; + ZXIC_UINT32 ctrl6_arbiter_ecc_err_3; + ZXIC_UINT32 ctrl6_arbiter_ecc_err_2; + ZXIC_UINT32 ctrl6_arbiter_ecc_err_1; + ZXIC_UINT32 ctrl6_arbiter_ecc_err_0; +}DPP_SMMU0_SMMU0_CTRL6_ARBITER_ECC_ERR_T; + +typedef struct dpp_smmu0_smmu0_ctrl7_arbiter_ecc_err_t +{ + ZXIC_UINT32 ctrl7_arbiter_ecc_err_31; + ZXIC_UINT32 ctrl7_arbiter_ecc_err_30; + ZXIC_UINT32 ctrl7_arbiter_ecc_err_29; + ZXIC_UINT32 ctrl7_arbiter_ecc_err_28; + ZXIC_UINT32 ctrl7_arbiter_ecc_err_27; + ZXIC_UINT32 ctrl7_arbiter_ecc_err_26; + ZXIC_UINT32 ctrl7_arbiter_ecc_err_25; + ZXIC_UINT32 ctrl7_arbiter_ecc_err_24; + ZXIC_UINT32 ctrl7_arbiter_ecc_err_23; + ZXIC_UINT32 ctrl7_arbiter_ecc_err_22; + ZXIC_UINT32 ctrl7_arbiter_ecc_err_21; + ZXIC_UINT32 ctrl7_arbiter_ecc_err_20; + ZXIC_UINT32 ctrl7_arbiter_ecc_err_19; + ZXIC_UINT32 ctrl7_arbiter_ecc_err_18; + ZXIC_UINT32 ctrl7_arbiter_ecc_err_17; + ZXIC_UINT32 ctrl7_arbiter_ecc_err_16; + ZXIC_UINT32 ctrl7_arbiter_ecc_err_15; + ZXIC_UINT32 ctrl7_arbiter_ecc_err_14; + ZXIC_UINT32 ctrl7_arbiter_ecc_err_13; + ZXIC_UINT32 ctrl7_arbiter_ecc_err_12; + ZXIC_UINT32 ctrl7_arbiter_ecc_err_11; + ZXIC_UINT32 ctrl7_arbiter_ecc_err_10; + ZXIC_UINT32 ctrl7_arbiter_ecc_err_9; + ZXIC_UINT32 ctrl7_arbiter_ecc_err_8; + ZXIC_UINT32 ctrl7_arbiter_ecc_err_7; + ZXIC_UINT32 ctrl7_arbiter_ecc_err_6; + ZXIC_UINT32 ctrl7_arbiter_ecc_err_5; + ZXIC_UINT32 ctrl7_arbiter_ecc_err_4; + ZXIC_UINT32 ctrl7_arbiter_ecc_err_3; + ZXIC_UINT32 ctrl7_arbiter_ecc_err_2; + ZXIC_UINT32 ctrl7_arbiter_ecc_err_1; + ZXIC_UINT32 ctrl7_arbiter_ecc_err_0; +}DPP_SMMU0_SMMU0_CTRL7_ARBITER_ECC_ERR_T; + +typedef struct dpp_smmu0_smmu0_ctrl8_arbiter_ecc_err_t +{ + ZXIC_UINT32 ctrl8_arbiter_ecc_err_31; + ZXIC_UINT32 ctrl8_arbiter_ecc_err_30; + ZXIC_UINT32 ctrl8_arbiter_ecc_err_29; + ZXIC_UINT32 ctrl8_arbiter_ecc_err_28; + ZXIC_UINT32 ctrl8_arbiter_ecc_err_27; + ZXIC_UINT32 ctrl8_arbiter_ecc_err_26; + ZXIC_UINT32 ctrl8_arbiter_ecc_err_25; + ZXIC_UINT32 ctrl8_arbiter_ecc_err_24; + ZXIC_UINT32 ctrl8_arbiter_ecc_err_23; + ZXIC_UINT32 ctrl8_arbiter_ecc_err_22; + ZXIC_UINT32 ctrl8_arbiter_ecc_err_21; + ZXIC_UINT32 ctrl8_arbiter_ecc_err_20; + ZXIC_UINT32 ctrl8_arbiter_ecc_err_19; + ZXIC_UINT32 ctrl8_arbiter_ecc_err_18; + ZXIC_UINT32 ctrl8_arbiter_ecc_err_17; + ZXIC_UINT32 ctrl8_arbiter_ecc_err_16; + ZXIC_UINT32 ctrl8_arbiter_ecc_err_15; + ZXIC_UINT32 ctrl8_arbiter_ecc_err_14; + ZXIC_UINT32 ctrl8_arbiter_ecc_err_13; + ZXIC_UINT32 ctrl8_arbiter_ecc_err_12; + ZXIC_UINT32 ctrl8_arbiter_ecc_err_11; + ZXIC_UINT32 ctrl8_arbiter_ecc_err_10; + ZXIC_UINT32 ctrl8_arbiter_ecc_err_9; + ZXIC_UINT32 ctrl8_arbiter_ecc_err_8; + ZXIC_UINT32 ctrl8_arbiter_ecc_err_7; + ZXIC_UINT32 ctrl8_arbiter_ecc_err_6; + ZXIC_UINT32 ctrl8_arbiter_ecc_err_5; + ZXIC_UINT32 ctrl8_arbiter_ecc_err_4; + ZXIC_UINT32 ctrl8_arbiter_ecc_err_3; + ZXIC_UINT32 ctrl8_arbiter_ecc_err_2; + ZXIC_UINT32 ctrl8_arbiter_ecc_err_1; + ZXIC_UINT32 ctrl8_arbiter_ecc_err_0; +}DPP_SMMU0_SMMU0_CTRL8_ARBITER_ECC_ERR_T; + +typedef struct dpp_smmu0_smmu0_ctrl9_arbiter_ecc_err_t +{ + ZXIC_UINT32 ctrl9_arbiter_ecc_err_31; + ZXIC_UINT32 ctrl9_arbiter_ecc_err_30; + ZXIC_UINT32 ctrl9_arbiter_ecc_err_29; + ZXIC_UINT32 ctrl9_arbiter_ecc_err_28; + ZXIC_UINT32 ctrl9_arbiter_ecc_err_27; + ZXIC_UINT32 ctrl9_arbiter_ecc_err_26; + ZXIC_UINT32 ctrl9_arbiter_ecc_err_25; + ZXIC_UINT32 ctrl9_arbiter_ecc_err_24; + ZXIC_UINT32 ctrl9_arbiter_ecc_err_23; + ZXIC_UINT32 ctrl9_arbiter_ecc_err_22; + ZXIC_UINT32 ctrl9_arbiter_ecc_err_21; + ZXIC_UINT32 ctrl9_arbiter_ecc_err_20; + ZXIC_UINT32 ctrl9_arbiter_ecc_err_19; + ZXIC_UINT32 ctrl9_arbiter_ecc_err_18; + ZXIC_UINT32 ctrl9_arbiter_ecc_err_17; + ZXIC_UINT32 ctrl9_arbiter_ecc_err_16; + ZXIC_UINT32 ctrl9_arbiter_ecc_err_15; + ZXIC_UINT32 ctrl9_arbiter_ecc_err_14; + ZXIC_UINT32 ctrl9_arbiter_ecc_err_13; + ZXIC_UINT32 ctrl9_arbiter_ecc_err_12; + ZXIC_UINT32 ctrl9_arbiter_ecc_err_11; + ZXIC_UINT32 ctrl9_arbiter_ecc_err_10; + ZXIC_UINT32 ctrl9_arbiter_ecc_err_9; + ZXIC_UINT32 ctrl9_arbiter_ecc_err_8; + ZXIC_UINT32 ctrl9_arbiter_ecc_err_7; + ZXIC_UINT32 ctrl9_arbiter_ecc_err_6; + ZXIC_UINT32 ctrl9_arbiter_ecc_err_5; + ZXIC_UINT32 ctrl9_arbiter_ecc_err_4; + ZXIC_UINT32 ctrl9_arbiter_ecc_err_3; + ZXIC_UINT32 ctrl9_arbiter_ecc_err_2; + ZXIC_UINT32 ctrl9_arbiter_ecc_err_1; + ZXIC_UINT32 ctrl9_arbiter_ecc_err_0; +}DPP_SMMU0_SMMU0_CTRL9_ARBITER_ECC_ERR_T; + +typedef struct dpp_smmu0_smmu0_ctrl10_arbiter_ecc_err_t +{ + ZXIC_UINT32 ctrl10_arbiter_ecc_err_31; + ZXIC_UINT32 ctrl10_arbiter_ecc_err_30; + ZXIC_UINT32 ctrl10_arbiter_ecc_err_29; + ZXIC_UINT32 ctrl10_arbiter_ecc_err_28; + ZXIC_UINT32 ctrl10_arbiter_ecc_err_27; + ZXIC_UINT32 ctrl10_arbiter_ecc_err_26; + ZXIC_UINT32 ctrl10_arbiter_ecc_err_25; + ZXIC_UINT32 ctrl10_arbiter_ecc_err_24; + ZXIC_UINT32 ctrl10_arbiter_ecc_err_23; + ZXIC_UINT32 ctrl10_arbiter_ecc_err_22; + ZXIC_UINT32 ctrl10_arbiter_ecc_err_21; + ZXIC_UINT32 ctrl10_arbiter_ecc_err_20; + ZXIC_UINT32 ctrl10_arbiter_ecc_err_19; + ZXIC_UINT32 ctrl10_arbiter_ecc_err_18; + ZXIC_UINT32 ctrl10_arbiter_ecc_err_17; + ZXIC_UINT32 ctrl10_arbiter_ecc_err_16; + ZXIC_UINT32 ctrl10_arbiter_ecc_err_15; + ZXIC_UINT32 ctrl10_arbiter_ecc_err_14; + ZXIC_UINT32 ctrl10_arbiter_ecc_err_13; + ZXIC_UINT32 ctrl10_arbiter_ecc_err_12; + ZXIC_UINT32 ctrl10_arbiter_ecc_err_11; + ZXIC_UINT32 ctrl10_arbiter_ecc_err_10; + ZXIC_UINT32 ctrl10_arbiter_ecc_err_9; + ZXIC_UINT32 ctrl10_arbiter_ecc_err_8; + ZXIC_UINT32 ctrl10_arbiter_ecc_err_7; + ZXIC_UINT32 ctrl10_arbiter_ecc_err_6; + ZXIC_UINT32 ctrl10_arbiter_ecc_err_5; + ZXIC_UINT32 ctrl10_arbiter_ecc_err_4; + ZXIC_UINT32 ctrl10_arbiter_ecc_err_3; + ZXIC_UINT32 ctrl10_arbiter_ecc_err_2; + ZXIC_UINT32 ctrl10_arbiter_ecc_err_1; + ZXIC_UINT32 ctrl10_arbiter_ecc_err_0; +}DPP_SMMU0_SMMU0_CTRL10_ARBITER_ECC_ERR_T; + +typedef struct dpp_smmu0_smmu0_ctrl11_arbiter_ecc_err_t +{ + ZXIC_UINT32 ctrl11_arbiter_ecc_err_31; + ZXIC_UINT32 ctrl11_arbiter_ecc_err_30; + ZXIC_UINT32 ctrl11_arbiter_ecc_err_29; + ZXIC_UINT32 ctrl11_arbiter_ecc_err_28; + ZXIC_UINT32 ctrl11_arbiter_ecc_err_27; + ZXIC_UINT32 ctrl11_arbiter_ecc_err_26; + ZXIC_UINT32 ctrl11_arbiter_ecc_err_25; + ZXIC_UINT32 ctrl11_arbiter_ecc_err_24; + ZXIC_UINT32 ctrl11_arbiter_ecc_err_23; + ZXIC_UINT32 ctrl11_arbiter_ecc_err_22; + ZXIC_UINT32 ctrl11_arbiter_ecc_err_21; + ZXIC_UINT32 ctrl11_arbiter_ecc_err_20; + ZXIC_UINT32 ctrl11_arbiter_ecc_err_19; + ZXIC_UINT32 ctrl11_arbiter_ecc_err_18; + ZXIC_UINT32 ctrl11_arbiter_ecc_err_17; + ZXIC_UINT32 ctrl11_arbiter_ecc_err_16; + ZXIC_UINT32 ctrl11_arbiter_ecc_err_15; + ZXIC_UINT32 ctrl11_arbiter_ecc_err_14; + ZXIC_UINT32 ctrl11_arbiter_ecc_err_13; + ZXIC_UINT32 ctrl11_arbiter_ecc_err_12; + ZXIC_UINT32 ctrl11_arbiter_ecc_err_11; + ZXIC_UINT32 ctrl11_arbiter_ecc_err_10; + ZXIC_UINT32 ctrl11_arbiter_ecc_err_9; + ZXIC_UINT32 ctrl11_arbiter_ecc_err_8; + ZXIC_UINT32 ctrl11_arbiter_ecc_err_7; + ZXIC_UINT32 ctrl11_arbiter_ecc_err_6; + ZXIC_UINT32 ctrl11_arbiter_ecc_err_5; + ZXIC_UINT32 ctrl11_arbiter_ecc_err_4; + ZXIC_UINT32 ctrl11_arbiter_ecc_err_3; + ZXIC_UINT32 ctrl11_arbiter_ecc_err_2; + ZXIC_UINT32 ctrl11_arbiter_ecc_err_1; + ZXIC_UINT32 ctrl11_arbiter_ecc_err_0; +}DPP_SMMU0_SMMU0_CTRL11_ARBITER_ECC_ERR_T; + +typedef struct dpp_smmu0_smmu0_ctrl12_arbiter_ecc_err_t +{ + ZXIC_UINT32 ctrl12_arbiter_ecc_err_31; + ZXIC_UINT32 ctrl12_arbiter_ecc_err_30; + ZXIC_UINT32 ctrl12_arbiter_ecc_err_29; + ZXIC_UINT32 ctrl12_arbiter_ecc_err_28; + ZXIC_UINT32 ctrl12_arbiter_ecc_err_27; + ZXIC_UINT32 ctrl12_arbiter_ecc_err_26; + ZXIC_UINT32 ctrl12_arbiter_ecc_err_25; + ZXIC_UINT32 ctrl12_arbiter_ecc_err_24; + ZXIC_UINT32 ctrl12_arbiter_ecc_err_23; + ZXIC_UINT32 ctrl12_arbiter_ecc_err_22; + ZXIC_UINT32 ctrl12_arbiter_ecc_err_21; + ZXIC_UINT32 ctrl12_arbiter_ecc_err_20; + ZXIC_UINT32 ctrl12_arbiter_ecc_err_19; + ZXIC_UINT32 ctrl12_arbiter_ecc_err_18; + ZXIC_UINT32 ctrl12_arbiter_ecc_err_17; + ZXIC_UINT32 ctrl12_arbiter_ecc_err_16; + ZXIC_UINT32 ctrl12_arbiter_ecc_err_15; + ZXIC_UINT32 ctrl12_arbiter_ecc_err_14; + ZXIC_UINT32 ctrl12_arbiter_ecc_err_13; + ZXIC_UINT32 ctrl12_arbiter_ecc_err_12; + ZXIC_UINT32 ctrl12_arbiter_ecc_err_11; + ZXIC_UINT32 ctrl12_arbiter_ecc_err_10; + ZXIC_UINT32 ctrl12_arbiter_ecc_err_9; + ZXIC_UINT32 ctrl12_arbiter_ecc_err_8; + ZXIC_UINT32 ctrl12_arbiter_ecc_err_7; + ZXIC_UINT32 ctrl12_arbiter_ecc_err_6; + ZXIC_UINT32 ctrl12_arbiter_ecc_err_5; + ZXIC_UINT32 ctrl12_arbiter_ecc_err_4; + ZXIC_UINT32 ctrl12_arbiter_ecc_err_3; + ZXIC_UINT32 ctrl12_arbiter_ecc_err_2; + ZXIC_UINT32 ctrl12_arbiter_ecc_err_1; + ZXIC_UINT32 ctrl12_arbiter_ecc_err_0; +}DPP_SMMU0_SMMU0_CTRL12_ARBITER_ECC_ERR_T; + +typedef struct dpp_smmu0_smmu0_ctrl13_arbiter_ecc_err_t +{ + ZXIC_UINT32 ctrl13_arbiter_ecc_err_31; + ZXIC_UINT32 ctrl13_arbiter_ecc_err_30; + ZXIC_UINT32 ctrl13_arbiter_ecc_err_29; + ZXIC_UINT32 ctrl13_arbiter_ecc_err_28; + ZXIC_UINT32 ctrl13_arbiter_ecc_err_27; + ZXIC_UINT32 ctrl13_arbiter_ecc_err_26; + ZXIC_UINT32 ctrl13_arbiter_ecc_err_25; + ZXIC_UINT32 ctrl13_arbiter_ecc_err_24; + ZXIC_UINT32 ctrl13_arbiter_ecc_err_23; + ZXIC_UINT32 ctrl13_arbiter_ecc_err_22; + ZXIC_UINT32 ctrl13_arbiter_ecc_err_21; + ZXIC_UINT32 ctrl13_arbiter_ecc_err_20; + ZXIC_UINT32 ctrl13_arbiter_ecc_err_19; + ZXIC_UINT32 ctrl13_arbiter_ecc_err_18; + ZXIC_UINT32 ctrl13_arbiter_ecc_err_17; + ZXIC_UINT32 ctrl13_arbiter_ecc_err_16; + ZXIC_UINT32 ctrl13_arbiter_ecc_err_15; + ZXIC_UINT32 ctrl13_arbiter_ecc_err_14; + ZXIC_UINT32 ctrl13_arbiter_ecc_err_13; + ZXIC_UINT32 ctrl13_arbiter_ecc_err_12; + ZXIC_UINT32 ctrl13_arbiter_ecc_err_11; + ZXIC_UINT32 ctrl13_arbiter_ecc_err_10; + ZXIC_UINT32 ctrl13_arbiter_ecc_err_9; + ZXIC_UINT32 ctrl13_arbiter_ecc_err_8; + ZXIC_UINT32 ctrl13_arbiter_ecc_err_7; + ZXIC_UINT32 ctrl13_arbiter_ecc_err_6; + ZXIC_UINT32 ctrl13_arbiter_ecc_err_5; + ZXIC_UINT32 ctrl13_arbiter_ecc_err_4; + ZXIC_UINT32 ctrl13_arbiter_ecc_err_3; + ZXIC_UINT32 ctrl13_arbiter_ecc_err_2; + ZXIC_UINT32 ctrl13_arbiter_ecc_err_1; + ZXIC_UINT32 ctrl13_arbiter_ecc_err_0; +}DPP_SMMU0_SMMU0_CTRL13_ARBITER_ECC_ERR_T; + +typedef struct dpp_smmu0_smmu0_ctrl14_arbiter_ecc_err_t +{ + ZXIC_UINT32 ctrl14_arbiter_ecc_err_31; + ZXIC_UINT32 ctrl14_arbiter_ecc_err_30; + ZXIC_UINT32 ctrl14_arbiter_ecc_err_29; + ZXIC_UINT32 ctrl14_arbiter_ecc_err_28; + ZXIC_UINT32 ctrl14_arbiter_ecc_err_27; + ZXIC_UINT32 ctrl14_arbiter_ecc_err_26; + ZXIC_UINT32 ctrl14_arbiter_ecc_err_25; + ZXIC_UINT32 ctrl14_arbiter_ecc_err_24; + ZXIC_UINT32 ctrl14_arbiter_ecc_err_23; + ZXIC_UINT32 ctrl14_arbiter_ecc_err_22; + ZXIC_UINT32 ctrl14_arbiter_ecc_err_21; + ZXIC_UINT32 ctrl14_arbiter_ecc_err_20; + ZXIC_UINT32 ctrl14_arbiter_ecc_err_19; + ZXIC_UINT32 ctrl14_arbiter_ecc_err_18; + ZXIC_UINT32 ctrl14_arbiter_ecc_err_17; + ZXIC_UINT32 ctrl14_arbiter_ecc_err_16; + ZXIC_UINT32 ctrl14_arbiter_ecc_err_15; + ZXIC_UINT32 ctrl14_arbiter_ecc_err_14; + ZXIC_UINT32 ctrl14_arbiter_ecc_err_13; + ZXIC_UINT32 ctrl14_arbiter_ecc_err_12; + ZXIC_UINT32 ctrl14_arbiter_ecc_err_11; + ZXIC_UINT32 ctrl14_arbiter_ecc_err_10; + ZXIC_UINT32 ctrl14_arbiter_ecc_err_9; + ZXIC_UINT32 ctrl14_arbiter_ecc_err_8; + ZXIC_UINT32 ctrl14_arbiter_ecc_err_7; + ZXIC_UINT32 ctrl14_arbiter_ecc_err_6; + ZXIC_UINT32 ctrl14_arbiter_ecc_err_5; + ZXIC_UINT32 ctrl14_arbiter_ecc_err_4; + ZXIC_UINT32 ctrl14_arbiter_ecc_err_3; + ZXIC_UINT32 ctrl14_arbiter_ecc_err_2; + ZXIC_UINT32 ctrl14_arbiter_ecc_err_1; + ZXIC_UINT32 ctrl14_arbiter_ecc_err_0; +}DPP_SMMU0_SMMU0_CTRL14_ARBITER_ECC_ERR_T; + +typedef struct dpp_smmu0_smmu0_ctrl15_arbiter_ecc_err_t +{ + ZXIC_UINT32 ctrl15_arbiter_ecc_err_31; + ZXIC_UINT32 ctrl15_arbiter_ecc_err_30; + ZXIC_UINT32 ctrl15_arbiter_ecc_err_29; + ZXIC_UINT32 ctrl15_arbiter_ecc_err_28; + ZXIC_UINT32 ctrl15_arbiter_ecc_err_27; + ZXIC_UINT32 ctrl15_arbiter_ecc_err_26; + ZXIC_UINT32 ctrl15_arbiter_ecc_err_25; + ZXIC_UINT32 ctrl15_arbiter_ecc_err_24; + ZXIC_UINT32 ctrl15_arbiter_ecc_err_23; + ZXIC_UINT32 ctrl15_arbiter_ecc_err_22; + ZXIC_UINT32 ctrl15_arbiter_ecc_err_21; + ZXIC_UINT32 ctrl15_arbiter_ecc_err_20; + ZXIC_UINT32 ctrl15_arbiter_ecc_err_19; + ZXIC_UINT32 ctrl15_arbiter_ecc_err_18; + ZXIC_UINT32 ctrl15_arbiter_ecc_err_17; + ZXIC_UINT32 ctrl15_arbiter_ecc_err_16; + ZXIC_UINT32 ctrl15_arbiter_ecc_err_15; + ZXIC_UINT32 ctrl15_arbiter_ecc_err_14; + ZXIC_UINT32 ctrl15_arbiter_ecc_err_13; + ZXIC_UINT32 ctrl15_arbiter_ecc_err_12; + ZXIC_UINT32 ctrl15_arbiter_ecc_err_11; + ZXIC_UINT32 ctrl15_arbiter_ecc_err_10; + ZXIC_UINT32 ctrl15_arbiter_ecc_err_9; + ZXIC_UINT32 ctrl15_arbiter_ecc_err_8; + ZXIC_UINT32 ctrl15_arbiter_ecc_err_7; + ZXIC_UINT32 ctrl15_arbiter_ecc_err_6; + ZXIC_UINT32 ctrl15_arbiter_ecc_err_5; + ZXIC_UINT32 ctrl15_arbiter_ecc_err_4; + ZXIC_UINT32 ctrl15_arbiter_ecc_err_3; + ZXIC_UINT32 ctrl15_arbiter_ecc_err_2; + ZXIC_UINT32 ctrl15_arbiter_ecc_err_1; + ZXIC_UINT32 ctrl15_arbiter_ecc_err_0; +}DPP_SMMU0_SMMU0_CTRL15_ARBITER_ECC_ERR_T; + +typedef struct dpp_smmu0_smmu0_ctrl16_arbiter_ecc_err_t +{ + ZXIC_UINT32 ctrl16_arbiter_ecc_err_31; + ZXIC_UINT32 ctrl16_arbiter_ecc_err_30; + ZXIC_UINT32 ctrl16_arbiter_ecc_err_29; + ZXIC_UINT32 ctrl16_arbiter_ecc_err_28; + ZXIC_UINT32 ctrl16_arbiter_ecc_err_27; + ZXIC_UINT32 ctrl16_arbiter_ecc_err_26; + ZXIC_UINT32 ctrl16_arbiter_ecc_err_25; + ZXIC_UINT32 ctrl16_arbiter_ecc_err_24; + ZXIC_UINT32 ctrl16_arbiter_ecc_err_23; + ZXIC_UINT32 ctrl16_arbiter_ecc_err_22; + ZXIC_UINT32 ctrl16_arbiter_ecc_err_21; + ZXIC_UINT32 ctrl16_arbiter_ecc_err_20; + ZXIC_UINT32 ctrl16_arbiter_ecc_err_19; + ZXIC_UINT32 ctrl16_arbiter_ecc_err_18; + ZXIC_UINT32 ctrl16_arbiter_ecc_err_17; + ZXIC_UINT32 ctrl16_arbiter_ecc_err_16; + ZXIC_UINT32 ctrl16_arbiter_ecc_err_15; + ZXIC_UINT32 ctrl16_arbiter_ecc_err_14; + ZXIC_UINT32 ctrl16_arbiter_ecc_err_13; + ZXIC_UINT32 ctrl16_arbiter_ecc_err_12; + ZXIC_UINT32 ctrl16_arbiter_ecc_err_11; + ZXIC_UINT32 ctrl16_arbiter_ecc_err_10; + ZXIC_UINT32 ctrl16_arbiter_ecc_err_9; + ZXIC_UINT32 ctrl16_arbiter_ecc_err_8; + ZXIC_UINT32 ctrl16_arbiter_ecc_err_7; + ZXIC_UINT32 ctrl16_arbiter_ecc_err_6; + ZXIC_UINT32 ctrl16_arbiter_ecc_err_5; + ZXIC_UINT32 ctrl16_arbiter_ecc_err_4; + ZXIC_UINT32 ctrl16_arbiter_ecc_err_3; + ZXIC_UINT32 ctrl16_arbiter_ecc_err_2; + ZXIC_UINT32 ctrl16_arbiter_ecc_err_1; + ZXIC_UINT32 ctrl16_arbiter_ecc_err_0; +}DPP_SMMU0_SMMU0_CTRL16_ARBITER_ECC_ERR_T; + +typedef struct dpp_smmu0_smmu0_ctrl17_arbiter_ecc_err_t +{ + ZXIC_UINT32 ctrl17_arbiter_ecc_err_31; + ZXIC_UINT32 ctrl17_arbiter_ecc_err_30; + ZXIC_UINT32 ctrl17_arbiter_ecc_err_29; + ZXIC_UINT32 ctrl17_arbiter_ecc_err_28; + ZXIC_UINT32 ctrl17_arbiter_ecc_err_27; + ZXIC_UINT32 ctrl17_arbiter_ecc_err_26; + ZXIC_UINT32 ctrl17_arbiter_ecc_err_25; + ZXIC_UINT32 ctrl17_arbiter_ecc_err_24; + ZXIC_UINT32 ctrl17_arbiter_ecc_err_23; + ZXIC_UINT32 ctrl17_arbiter_ecc_err_22; + ZXIC_UINT32 ctrl17_arbiter_ecc_err_21; + ZXIC_UINT32 ctrl17_arbiter_ecc_err_20; + ZXIC_UINT32 ctrl17_arbiter_ecc_err_19; + ZXIC_UINT32 ctrl17_arbiter_ecc_err_18; + ZXIC_UINT32 ctrl17_arbiter_ecc_err_17; + ZXIC_UINT32 ctrl17_arbiter_ecc_err_16; + ZXIC_UINT32 ctrl17_arbiter_ecc_err_15; + ZXIC_UINT32 ctrl17_arbiter_ecc_err_14; + ZXIC_UINT32 ctrl17_arbiter_ecc_err_13; + ZXIC_UINT32 ctrl17_arbiter_ecc_err_12; + ZXIC_UINT32 ctrl17_arbiter_ecc_err_11; + ZXIC_UINT32 ctrl17_arbiter_ecc_err_10; + ZXIC_UINT32 ctrl17_arbiter_ecc_err_9; + ZXIC_UINT32 ctrl17_arbiter_ecc_err_8; + ZXIC_UINT32 ctrl17_arbiter_ecc_err_7; + ZXIC_UINT32 ctrl17_arbiter_ecc_err_6; + ZXIC_UINT32 ctrl17_arbiter_ecc_err_5; + ZXIC_UINT32 ctrl17_arbiter_ecc_err_4; + ZXIC_UINT32 ctrl17_arbiter_ecc_err_3; + ZXIC_UINT32 ctrl17_arbiter_ecc_err_2; + ZXIC_UINT32 ctrl17_arbiter_ecc_err_1; + ZXIC_UINT32 ctrl17_arbiter_ecc_err_0; +}DPP_SMMU0_SMMU0_CTRL17_ARBITER_ECC_ERR_T; + +typedef struct dpp_smmu0_smmu0_ctrl18_arbiter_ecc_err_t +{ + ZXIC_UINT32 ctrl18_arbiter_ecc_err_31; + ZXIC_UINT32 ctrl18_arbiter_ecc_err_30; + ZXIC_UINT32 ctrl18_arbiter_ecc_err_29; + ZXIC_UINT32 ctrl18_arbiter_ecc_err_28; + ZXIC_UINT32 ctrl18_arbiter_ecc_err_27; + ZXIC_UINT32 ctrl18_arbiter_ecc_err_26; + ZXIC_UINT32 ctrl18_arbiter_ecc_err_25; + ZXIC_UINT32 ctrl18_arbiter_ecc_err_24; + ZXIC_UINT32 ctrl18_arbiter_ecc_err_23; + ZXIC_UINT32 ctrl18_arbiter_ecc_err_22; + ZXIC_UINT32 ctrl18_arbiter_ecc_err_21; + ZXIC_UINT32 ctrl18_arbiter_ecc_err_20; + ZXIC_UINT32 ctrl18_arbiter_ecc_err_19; + ZXIC_UINT32 ctrl18_arbiter_ecc_err_18; + ZXIC_UINT32 ctrl18_arbiter_ecc_err_17; + ZXIC_UINT32 ctrl18_arbiter_ecc_err_16; + ZXIC_UINT32 ctrl18_arbiter_ecc_err_15; + ZXIC_UINT32 ctrl18_arbiter_ecc_err_14; + ZXIC_UINT32 ctrl18_arbiter_ecc_err_13; + ZXIC_UINT32 ctrl18_arbiter_ecc_err_12; + ZXIC_UINT32 ctrl18_arbiter_ecc_err_11; + ZXIC_UINT32 ctrl18_arbiter_ecc_err_10; + ZXIC_UINT32 ctrl18_arbiter_ecc_err_9; + ZXIC_UINT32 ctrl18_arbiter_ecc_err_8; + ZXIC_UINT32 ctrl18_arbiter_ecc_err_7; + ZXIC_UINT32 ctrl18_arbiter_ecc_err_6; + ZXIC_UINT32 ctrl18_arbiter_ecc_err_5; + ZXIC_UINT32 ctrl18_arbiter_ecc_err_4; + ZXIC_UINT32 ctrl18_arbiter_ecc_err_3; + ZXIC_UINT32 ctrl18_arbiter_ecc_err_2; + ZXIC_UINT32 ctrl18_arbiter_ecc_err_1; + ZXIC_UINT32 ctrl18_arbiter_ecc_err_0; +}DPP_SMMU0_SMMU0_CTRL18_ARBITER_ECC_ERR_T; + +typedef struct dpp_smmu0_smmu0_ctrl19_arbiter_ecc_err_t +{ + ZXIC_UINT32 ctrl19_arbiter_ecc_err_31; + ZXIC_UINT32 ctrl19_arbiter_ecc_err_30; + ZXIC_UINT32 ctrl19_arbiter_ecc_err_29; + ZXIC_UINT32 ctrl19_arbiter_ecc_err_28; + ZXIC_UINT32 ctrl19_arbiter_ecc_err_27; + ZXIC_UINT32 ctrl19_arbiter_ecc_err_26; + ZXIC_UINT32 ctrl19_arbiter_ecc_err_25; + ZXIC_UINT32 ctrl19_arbiter_ecc_err_24; + ZXIC_UINT32 ctrl19_arbiter_ecc_err_23; + ZXIC_UINT32 ctrl19_arbiter_ecc_err_22; + ZXIC_UINT32 ctrl19_arbiter_ecc_err_21; + ZXIC_UINT32 ctrl19_arbiter_ecc_err_20; + ZXIC_UINT32 ctrl19_arbiter_ecc_err_19; + ZXIC_UINT32 ctrl19_arbiter_ecc_err_18; + ZXIC_UINT32 ctrl19_arbiter_ecc_err_17; + ZXIC_UINT32 ctrl19_arbiter_ecc_err_16; + ZXIC_UINT32 ctrl19_arbiter_ecc_err_15; + ZXIC_UINT32 ctrl19_arbiter_ecc_err_14; + ZXIC_UINT32 ctrl19_arbiter_ecc_err_13; + ZXIC_UINT32 ctrl19_arbiter_ecc_err_12; + ZXIC_UINT32 ctrl19_arbiter_ecc_err_11; + ZXIC_UINT32 ctrl19_arbiter_ecc_err_10; + ZXIC_UINT32 ctrl19_arbiter_ecc_err_9; + ZXIC_UINT32 ctrl19_arbiter_ecc_err_8; + ZXIC_UINT32 ctrl19_arbiter_ecc_err_7; + ZXIC_UINT32 ctrl19_arbiter_ecc_err_6; + ZXIC_UINT32 ctrl19_arbiter_ecc_err_5; + ZXIC_UINT32 ctrl19_arbiter_ecc_err_4; + ZXIC_UINT32 ctrl19_arbiter_ecc_err_3; + ZXIC_UINT32 ctrl19_arbiter_ecc_err_2; + ZXIC_UINT32 ctrl19_arbiter_ecc_err_1; + ZXIC_UINT32 ctrl19_arbiter_ecc_err_0; +}DPP_SMMU0_SMMU0_CTRL19_ARBITER_ECC_ERR_T; + +typedef struct dpp_smmu0_smmu0_ctrl20_arbiter_ecc_err_t +{ + ZXIC_UINT32 ctrl20_arbiter_ecc_err_31; + ZXIC_UINT32 ctrl20_arbiter_ecc_err_30; + ZXIC_UINT32 ctrl20_arbiter_ecc_err_29; + ZXIC_UINT32 ctrl20_arbiter_ecc_err_28; + ZXIC_UINT32 ctrl20_arbiter_ecc_err_27; + ZXIC_UINT32 ctrl20_arbiter_ecc_err_26; + ZXIC_UINT32 ctrl20_arbiter_ecc_err_25; + ZXIC_UINT32 ctrl20_arbiter_ecc_err_24; + ZXIC_UINT32 ctrl20_arbiter_ecc_err_23; + ZXIC_UINT32 ctrl20_arbiter_ecc_err_22; + ZXIC_UINT32 ctrl20_arbiter_ecc_err_21; + ZXIC_UINT32 ctrl20_arbiter_ecc_err_20; + ZXIC_UINT32 ctrl20_arbiter_ecc_err_19; + ZXIC_UINT32 ctrl20_arbiter_ecc_err_18; + ZXIC_UINT32 ctrl20_arbiter_ecc_err_17; + ZXIC_UINT32 ctrl20_arbiter_ecc_err_16; + ZXIC_UINT32 ctrl20_arbiter_ecc_err_15; + ZXIC_UINT32 ctrl20_arbiter_ecc_err_14; + ZXIC_UINT32 ctrl20_arbiter_ecc_err_13; + ZXIC_UINT32 ctrl20_arbiter_ecc_err_12; + ZXIC_UINT32 ctrl20_arbiter_ecc_err_11; + ZXIC_UINT32 ctrl20_arbiter_ecc_err_10; + ZXIC_UINT32 ctrl20_arbiter_ecc_err_9; + ZXIC_UINT32 ctrl20_arbiter_ecc_err_8; + ZXIC_UINT32 ctrl20_arbiter_ecc_err_7; + ZXIC_UINT32 ctrl20_arbiter_ecc_err_6; + ZXIC_UINT32 ctrl20_arbiter_ecc_err_5; + ZXIC_UINT32 ctrl20_arbiter_ecc_err_4; + ZXIC_UINT32 ctrl20_arbiter_ecc_err_3; + ZXIC_UINT32 ctrl20_arbiter_ecc_err_2; + ZXIC_UINT32 ctrl20_arbiter_ecc_err_1; + ZXIC_UINT32 ctrl20_arbiter_ecc_err_0; +}DPP_SMMU0_SMMU0_CTRL20_ARBITER_ECC_ERR_T; + +typedef struct dpp_smmu0_smmu0_ctrl21_arbiter_ecc_err_t +{ + ZXIC_UINT32 ctrl21_arbiter_ecc_err_31; + ZXIC_UINT32 ctrl21_arbiter_ecc_err_30; + ZXIC_UINT32 ctrl21_arbiter_ecc_err_29; + ZXIC_UINT32 ctrl21_arbiter_ecc_err_28; + ZXIC_UINT32 ctrl21_arbiter_ecc_err_27; + ZXIC_UINT32 ctrl21_arbiter_ecc_err_26; + ZXIC_UINT32 ctrl21_arbiter_ecc_err_25; + ZXIC_UINT32 ctrl21_arbiter_ecc_err_24; + ZXIC_UINT32 ctrl21_arbiter_ecc_err_23; + ZXIC_UINT32 ctrl21_arbiter_ecc_err_22; + ZXIC_UINT32 ctrl21_arbiter_ecc_err_21; + ZXIC_UINT32 ctrl21_arbiter_ecc_err_20; + ZXIC_UINT32 ctrl21_arbiter_ecc_err_19; + ZXIC_UINT32 ctrl21_arbiter_ecc_err_18; + ZXIC_UINT32 ctrl21_arbiter_ecc_err_17; + ZXIC_UINT32 ctrl21_arbiter_ecc_err_16; + ZXIC_UINT32 ctrl21_arbiter_ecc_err_15; + ZXIC_UINT32 ctrl21_arbiter_ecc_err_14; + ZXIC_UINT32 ctrl21_arbiter_ecc_err_13; + ZXIC_UINT32 ctrl21_arbiter_ecc_err_12; + ZXIC_UINT32 ctrl21_arbiter_ecc_err_11; + ZXIC_UINT32 ctrl21_arbiter_ecc_err_10; + ZXIC_UINT32 ctrl21_arbiter_ecc_err_9; + ZXIC_UINT32 ctrl21_arbiter_ecc_err_8; + ZXIC_UINT32 ctrl21_arbiter_ecc_err_7; + ZXIC_UINT32 ctrl21_arbiter_ecc_err_6; + ZXIC_UINT32 ctrl21_arbiter_ecc_err_5; + ZXIC_UINT32 ctrl21_arbiter_ecc_err_4; + ZXIC_UINT32 ctrl21_arbiter_ecc_err_3; + ZXIC_UINT32 ctrl21_arbiter_ecc_err_2; + ZXIC_UINT32 ctrl21_arbiter_ecc_err_1; + ZXIC_UINT32 ctrl21_arbiter_ecc_err_0; +}DPP_SMMU0_SMMU0_CTRL21_ARBITER_ECC_ERR_T; + +typedef struct dpp_smmu0_smmu0_ctrl22_arbiter_ecc_err_t +{ + ZXIC_UINT32 ctrl22_arbiter_ecc_err_31; + ZXIC_UINT32 ctrl22_arbiter_ecc_err_30; + ZXIC_UINT32 ctrl22_arbiter_ecc_err_29; + ZXIC_UINT32 ctrl22_arbiter_ecc_err_28; + ZXIC_UINT32 ctrl22_arbiter_ecc_err_27; + ZXIC_UINT32 ctrl22_arbiter_ecc_err_26; + ZXIC_UINT32 ctrl22_arbiter_ecc_err_25; + ZXIC_UINT32 ctrl22_arbiter_ecc_err_24; + ZXIC_UINT32 ctrl22_arbiter_ecc_err_23; + ZXIC_UINT32 ctrl22_arbiter_ecc_err_22; + ZXIC_UINT32 ctrl22_arbiter_ecc_err_21; + ZXIC_UINT32 ctrl22_arbiter_ecc_err_20; + ZXIC_UINT32 ctrl22_arbiter_ecc_err_19; + ZXIC_UINT32 ctrl22_arbiter_ecc_err_18; + ZXIC_UINT32 ctrl22_arbiter_ecc_err_17; + ZXIC_UINT32 ctrl22_arbiter_ecc_err_16; + ZXIC_UINT32 ctrl22_arbiter_ecc_err_15; + ZXIC_UINT32 ctrl22_arbiter_ecc_err_14; + ZXIC_UINT32 ctrl22_arbiter_ecc_err_13; + ZXIC_UINT32 ctrl22_arbiter_ecc_err_12; + ZXIC_UINT32 ctrl22_arbiter_ecc_err_11; + ZXIC_UINT32 ctrl22_arbiter_ecc_err_10; + ZXIC_UINT32 ctrl22_arbiter_ecc_err_9; + ZXIC_UINT32 ctrl22_arbiter_ecc_err_8; + ZXIC_UINT32 ctrl22_arbiter_ecc_err_7; + ZXIC_UINT32 ctrl22_arbiter_ecc_err_6; + ZXIC_UINT32 ctrl22_arbiter_ecc_err_5; + ZXIC_UINT32 ctrl22_arbiter_ecc_err_4; + ZXIC_UINT32 ctrl22_arbiter_ecc_err_3; + ZXIC_UINT32 ctrl22_arbiter_ecc_err_2; + ZXIC_UINT32 ctrl22_arbiter_ecc_err_1; + ZXIC_UINT32 ctrl22_arbiter_ecc_err_0; +}DPP_SMMU0_SMMU0_CTRL22_ARBITER_ECC_ERR_T; + +typedef struct dpp_smmu0_smmu0_ctrl23_arbiter_ecc_err_t +{ + ZXIC_UINT32 ctrl23_arbiter_ecc_err_31; + ZXIC_UINT32 ctrl23_arbiter_ecc_err_30; + ZXIC_UINT32 ctrl23_arbiter_ecc_err_29; + ZXIC_UINT32 ctrl23_arbiter_ecc_err_28; + ZXIC_UINT32 ctrl23_arbiter_ecc_err_27; + ZXIC_UINT32 ctrl23_arbiter_ecc_err_26; + ZXIC_UINT32 ctrl23_arbiter_ecc_err_25; + ZXIC_UINT32 ctrl23_arbiter_ecc_err_24; + ZXIC_UINT32 ctrl23_arbiter_ecc_err_23; + ZXIC_UINT32 ctrl23_arbiter_ecc_err_22; + ZXIC_UINT32 ctrl23_arbiter_ecc_err_21; + ZXIC_UINT32 ctrl23_arbiter_ecc_err_20; + ZXIC_UINT32 ctrl23_arbiter_ecc_err_19; + ZXIC_UINT32 ctrl23_arbiter_ecc_err_18; + ZXIC_UINT32 ctrl23_arbiter_ecc_err_17; + ZXIC_UINT32 ctrl23_arbiter_ecc_err_16; + ZXIC_UINT32 ctrl23_arbiter_ecc_err_15; + ZXIC_UINT32 ctrl23_arbiter_ecc_err_14; + ZXIC_UINT32 ctrl23_arbiter_ecc_err_13; + ZXIC_UINT32 ctrl23_arbiter_ecc_err_12; + ZXIC_UINT32 ctrl23_arbiter_ecc_err_11; + ZXIC_UINT32 ctrl23_arbiter_ecc_err_10; + ZXIC_UINT32 ctrl23_arbiter_ecc_err_9; + ZXIC_UINT32 ctrl23_arbiter_ecc_err_8; + ZXIC_UINT32 ctrl23_arbiter_ecc_err_7; + ZXIC_UINT32 ctrl23_arbiter_ecc_err_6; + ZXIC_UINT32 ctrl23_arbiter_ecc_err_5; + ZXIC_UINT32 ctrl23_arbiter_ecc_err_4; + ZXIC_UINT32 ctrl23_arbiter_ecc_err_3; + ZXIC_UINT32 ctrl23_arbiter_ecc_err_2; + ZXIC_UINT32 ctrl23_arbiter_ecc_err_1; + ZXIC_UINT32 ctrl23_arbiter_ecc_err_0; +}DPP_SMMU0_SMMU0_CTRL23_ARBITER_ECC_ERR_T; + +typedef struct dpp_smmu0_smmu0_ctrl24_arbiter_ecc_err_t +{ + ZXIC_UINT32 ctrl24_arbiter_ecc_err_31; + ZXIC_UINT32 ctrl24_arbiter_ecc_err_30; + ZXIC_UINT32 ctrl24_arbiter_ecc_err_29; + ZXIC_UINT32 ctrl24_arbiter_ecc_err_28; + ZXIC_UINT32 ctrl24_arbiter_ecc_err_27; + ZXIC_UINT32 ctrl24_arbiter_ecc_err_26; + ZXIC_UINT32 ctrl24_arbiter_ecc_err_25; + ZXIC_UINT32 ctrl24_arbiter_ecc_err_24; + ZXIC_UINT32 ctrl24_arbiter_ecc_err_23; + ZXIC_UINT32 ctrl24_arbiter_ecc_err_22; + ZXIC_UINT32 ctrl24_arbiter_ecc_err_21; + ZXIC_UINT32 ctrl24_arbiter_ecc_err_20; + ZXIC_UINT32 ctrl24_arbiter_ecc_err_19; + ZXIC_UINT32 ctrl24_arbiter_ecc_err_18; + ZXIC_UINT32 ctrl24_arbiter_ecc_err_17; + ZXIC_UINT32 ctrl24_arbiter_ecc_err_16; + ZXIC_UINT32 ctrl24_arbiter_ecc_err_15; + ZXIC_UINT32 ctrl24_arbiter_ecc_err_14; + ZXIC_UINT32 ctrl24_arbiter_ecc_err_13; + ZXIC_UINT32 ctrl24_arbiter_ecc_err_12; + ZXIC_UINT32 ctrl24_arbiter_ecc_err_11; + ZXIC_UINT32 ctrl24_arbiter_ecc_err_10; + ZXIC_UINT32 ctrl24_arbiter_ecc_err_9; + ZXIC_UINT32 ctrl24_arbiter_ecc_err_8; + ZXIC_UINT32 ctrl24_arbiter_ecc_err_7; + ZXIC_UINT32 ctrl24_arbiter_ecc_err_6; + ZXIC_UINT32 ctrl24_arbiter_ecc_err_5; + ZXIC_UINT32 ctrl24_arbiter_ecc_err_4; + ZXIC_UINT32 ctrl24_arbiter_ecc_err_3; + ZXIC_UINT32 ctrl24_arbiter_ecc_err_2; + ZXIC_UINT32 ctrl24_arbiter_ecc_err_1; + ZXIC_UINT32 ctrl24_arbiter_ecc_err_0; +}DPP_SMMU0_SMMU0_CTRL24_ARBITER_ECC_ERR_T; + +typedef struct dpp_smmu0_smmu0_ctrl25_arbiter_ecc_err_t +{ + ZXIC_UINT32 ctrl25_arbiter_ecc_err_31; + ZXIC_UINT32 ctrl25_arbiter_ecc_err_30; + ZXIC_UINT32 ctrl25_arbiter_ecc_err_29; + ZXIC_UINT32 ctrl25_arbiter_ecc_err_28; + ZXIC_UINT32 ctrl25_arbiter_ecc_err_27; + ZXIC_UINT32 ctrl25_arbiter_ecc_err_26; + ZXIC_UINT32 ctrl25_arbiter_ecc_err_25; + ZXIC_UINT32 ctrl25_arbiter_ecc_err_24; + ZXIC_UINT32 ctrl25_arbiter_ecc_err_23; + ZXIC_UINT32 ctrl25_arbiter_ecc_err_22; + ZXIC_UINT32 ctrl25_arbiter_ecc_err_21; + ZXIC_UINT32 ctrl25_arbiter_ecc_err_20; + ZXIC_UINT32 ctrl25_arbiter_ecc_err_19; + ZXIC_UINT32 ctrl25_arbiter_ecc_err_18; + ZXIC_UINT32 ctrl25_arbiter_ecc_err_17; + ZXIC_UINT32 ctrl25_arbiter_ecc_err_16; + ZXIC_UINT32 ctrl25_arbiter_ecc_err_15; + ZXIC_UINT32 ctrl25_arbiter_ecc_err_14; + ZXIC_UINT32 ctrl25_arbiter_ecc_err_13; + ZXIC_UINT32 ctrl25_arbiter_ecc_err_12; + ZXIC_UINT32 ctrl25_arbiter_ecc_err_11; + ZXIC_UINT32 ctrl25_arbiter_ecc_err_10; + ZXIC_UINT32 ctrl25_arbiter_ecc_err_9; + ZXIC_UINT32 ctrl25_arbiter_ecc_err_8; + ZXIC_UINT32 ctrl25_arbiter_ecc_err_7; + ZXIC_UINT32 ctrl25_arbiter_ecc_err_6; + ZXIC_UINT32 ctrl25_arbiter_ecc_err_5; + ZXIC_UINT32 ctrl25_arbiter_ecc_err_4; + ZXIC_UINT32 ctrl25_arbiter_ecc_err_3; + ZXIC_UINT32 ctrl25_arbiter_ecc_err_2; + ZXIC_UINT32 ctrl25_arbiter_ecc_err_1; + ZXIC_UINT32 ctrl25_arbiter_ecc_err_0; +}DPP_SMMU0_SMMU0_CTRL25_ARBITER_ECC_ERR_T; + +typedef struct dpp_smmu0_smmu0_ctrl26_arbiter_ecc_err_t +{ + ZXIC_UINT32 ctrl26_arbiter_ecc_err_31; + ZXIC_UINT32 ctrl26_arbiter_ecc_err_30; + ZXIC_UINT32 ctrl26_arbiter_ecc_err_29; + ZXIC_UINT32 ctrl26_arbiter_ecc_err_28; + ZXIC_UINT32 ctrl26_arbiter_ecc_err_27; + ZXIC_UINT32 ctrl26_arbiter_ecc_err_26; + ZXIC_UINT32 ctrl26_arbiter_ecc_err_25; + ZXIC_UINT32 ctrl26_arbiter_ecc_err_24; + ZXIC_UINT32 ctrl26_arbiter_ecc_err_23; + ZXIC_UINT32 ctrl26_arbiter_ecc_err_22; + ZXIC_UINT32 ctrl26_arbiter_ecc_err_21; + ZXIC_UINT32 ctrl26_arbiter_ecc_err_20; + ZXIC_UINT32 ctrl26_arbiter_ecc_err_19; + ZXIC_UINT32 ctrl26_arbiter_ecc_err_18; + ZXIC_UINT32 ctrl26_arbiter_ecc_err_17; + ZXIC_UINT32 ctrl26_arbiter_ecc_err_16; + ZXIC_UINT32 ctrl26_arbiter_ecc_err_15; + ZXIC_UINT32 ctrl26_arbiter_ecc_err_14; + ZXIC_UINT32 ctrl26_arbiter_ecc_err_13; + ZXIC_UINT32 ctrl26_arbiter_ecc_err_12; + ZXIC_UINT32 ctrl26_arbiter_ecc_err_11; + ZXIC_UINT32 ctrl26_arbiter_ecc_err_10; + ZXIC_UINT32 ctrl26_arbiter_ecc_err_9; + ZXIC_UINT32 ctrl26_arbiter_ecc_err_8; + ZXIC_UINT32 ctrl26_arbiter_ecc_err_7; + ZXIC_UINT32 ctrl26_arbiter_ecc_err_6; + ZXIC_UINT32 ctrl26_arbiter_ecc_err_5; + ZXIC_UINT32 ctrl26_arbiter_ecc_err_4; + ZXIC_UINT32 ctrl26_arbiter_ecc_err_3; + ZXIC_UINT32 ctrl26_arbiter_ecc_err_2; + ZXIC_UINT32 ctrl26_arbiter_ecc_err_1; + ZXIC_UINT32 ctrl26_arbiter_ecc_err_0; +}DPP_SMMU0_SMMU0_CTRL26_ARBITER_ECC_ERR_T; + +typedef struct dpp_smmu0_smmu0_ctrl27_arbiter_ecc_err_t +{ + ZXIC_UINT32 ctrl27_arbiter_ecc_err_31; + ZXIC_UINT32 ctrl27_arbiter_ecc_err_30; + ZXIC_UINT32 ctrl27_arbiter_ecc_err_29; + ZXIC_UINT32 ctrl27_arbiter_ecc_err_28; + ZXIC_UINT32 ctrl27_arbiter_ecc_err_27; + ZXIC_UINT32 ctrl27_arbiter_ecc_err_26; + ZXIC_UINT32 ctrl27_arbiter_ecc_err_25; + ZXIC_UINT32 ctrl27_arbiter_ecc_err_24; + ZXIC_UINT32 ctrl27_arbiter_ecc_err_23; + ZXIC_UINT32 ctrl27_arbiter_ecc_err_22; + ZXIC_UINT32 ctrl27_arbiter_ecc_err_21; + ZXIC_UINT32 ctrl27_arbiter_ecc_err_20; + ZXIC_UINT32 ctrl27_arbiter_ecc_err_19; + ZXIC_UINT32 ctrl27_arbiter_ecc_err_18; + ZXIC_UINT32 ctrl27_arbiter_ecc_err_17; + ZXIC_UINT32 ctrl27_arbiter_ecc_err_16; + ZXIC_UINT32 ctrl27_arbiter_ecc_err_15; + ZXIC_UINT32 ctrl27_arbiter_ecc_err_14; + ZXIC_UINT32 ctrl27_arbiter_ecc_err_13; + ZXIC_UINT32 ctrl27_arbiter_ecc_err_12; + ZXIC_UINT32 ctrl27_arbiter_ecc_err_11; + ZXIC_UINT32 ctrl27_arbiter_ecc_err_10; + ZXIC_UINT32 ctrl27_arbiter_ecc_err_9; + ZXIC_UINT32 ctrl27_arbiter_ecc_err_8; + ZXIC_UINT32 ctrl27_arbiter_ecc_err_7; + ZXIC_UINT32 ctrl27_arbiter_ecc_err_6; + ZXIC_UINT32 ctrl27_arbiter_ecc_err_5; + ZXIC_UINT32 ctrl27_arbiter_ecc_err_4; + ZXIC_UINT32 ctrl27_arbiter_ecc_err_3; + ZXIC_UINT32 ctrl27_arbiter_ecc_err_2; + ZXIC_UINT32 ctrl27_arbiter_ecc_err_1; + ZXIC_UINT32 ctrl27_arbiter_ecc_err_0; +}DPP_SMMU0_SMMU0_CTRL27_ARBITER_ECC_ERR_T; + +typedef struct dpp_smmu0_smmu0_ctrl28_arbiter_ecc_err_t +{ + ZXIC_UINT32 ctrl28_arbiter_ecc_err_31; + ZXIC_UINT32 ctrl28_arbiter_ecc_err_30; + ZXIC_UINT32 ctrl28_arbiter_ecc_err_29; + ZXIC_UINT32 ctrl28_arbiter_ecc_err_28; + ZXIC_UINT32 ctrl28_arbiter_ecc_err_27; + ZXIC_UINT32 ctrl28_arbiter_ecc_err_26; + ZXIC_UINT32 ctrl28_arbiter_ecc_err_25; + ZXIC_UINT32 ctrl28_arbiter_ecc_err_24; + ZXIC_UINT32 ctrl28_arbiter_ecc_err_23; + ZXIC_UINT32 ctrl28_arbiter_ecc_err_22; + ZXIC_UINT32 ctrl28_arbiter_ecc_err_21; + ZXIC_UINT32 ctrl28_arbiter_ecc_err_20; + ZXIC_UINT32 ctrl28_arbiter_ecc_err_19; + ZXIC_UINT32 ctrl28_arbiter_ecc_err_18; + ZXIC_UINT32 ctrl28_arbiter_ecc_err_17; + ZXIC_UINT32 ctrl28_arbiter_ecc_err_16; + ZXIC_UINT32 ctrl28_arbiter_ecc_err_15; + ZXIC_UINT32 ctrl28_arbiter_ecc_err_14; + ZXIC_UINT32 ctrl28_arbiter_ecc_err_13; + ZXIC_UINT32 ctrl28_arbiter_ecc_err_12; + ZXIC_UINT32 ctrl28_arbiter_ecc_err_11; + ZXIC_UINT32 ctrl28_arbiter_ecc_err_10; + ZXIC_UINT32 ctrl28_arbiter_ecc_err_9; + ZXIC_UINT32 ctrl28_arbiter_ecc_err_8; + ZXIC_UINT32 ctrl28_arbiter_ecc_err_7; + ZXIC_UINT32 ctrl28_arbiter_ecc_err_6; + ZXIC_UINT32 ctrl28_arbiter_ecc_err_5; + ZXIC_UINT32 ctrl28_arbiter_ecc_err_4; + ZXIC_UINT32 ctrl28_arbiter_ecc_err_3; + ZXIC_UINT32 ctrl28_arbiter_ecc_err_2; + ZXIC_UINT32 ctrl28_arbiter_ecc_err_1; + ZXIC_UINT32 ctrl28_arbiter_ecc_err_0; +}DPP_SMMU0_SMMU0_CTRL28_ARBITER_ECC_ERR_T; + +typedef struct dpp_smmu0_smmu0_ctrl29_arbiter_ecc_err_t +{ + ZXIC_UINT32 ctrl29_arbiter_ecc_err_31; + ZXIC_UINT32 ctrl29_arbiter_ecc_err_30; + ZXIC_UINT32 ctrl29_arbiter_ecc_err_29; + ZXIC_UINT32 ctrl29_arbiter_ecc_err_28; + ZXIC_UINT32 ctrl29_arbiter_ecc_err_27; + ZXIC_UINT32 ctrl29_arbiter_ecc_err_26; + ZXIC_UINT32 ctrl29_arbiter_ecc_err_25; + ZXIC_UINT32 ctrl29_arbiter_ecc_err_24; + ZXIC_UINT32 ctrl29_arbiter_ecc_err_23; + ZXIC_UINT32 ctrl29_arbiter_ecc_err_22; + ZXIC_UINT32 ctrl29_arbiter_ecc_err_21; + ZXIC_UINT32 ctrl29_arbiter_ecc_err_20; + ZXIC_UINT32 ctrl29_arbiter_ecc_err_19; + ZXIC_UINT32 ctrl29_arbiter_ecc_err_18; + ZXIC_UINT32 ctrl29_arbiter_ecc_err_17; + ZXIC_UINT32 ctrl29_arbiter_ecc_err_16; + ZXIC_UINT32 ctrl29_arbiter_ecc_err_15; + ZXIC_UINT32 ctrl29_arbiter_ecc_err_14; + ZXIC_UINT32 ctrl29_arbiter_ecc_err_13; + ZXIC_UINT32 ctrl29_arbiter_ecc_err_12; + ZXIC_UINT32 ctrl29_arbiter_ecc_err_11; + ZXIC_UINT32 ctrl29_arbiter_ecc_err_10; + ZXIC_UINT32 ctrl29_arbiter_ecc_err_9; + ZXIC_UINT32 ctrl29_arbiter_ecc_err_8; + ZXIC_UINT32 ctrl29_arbiter_ecc_err_7; + ZXIC_UINT32 ctrl29_arbiter_ecc_err_6; + ZXIC_UINT32 ctrl29_arbiter_ecc_err_5; + ZXIC_UINT32 ctrl29_arbiter_ecc_err_4; + ZXIC_UINT32 ctrl29_arbiter_ecc_err_3; + ZXIC_UINT32 ctrl29_arbiter_ecc_err_2; + ZXIC_UINT32 ctrl29_arbiter_ecc_err_1; + ZXIC_UINT32 ctrl29_arbiter_ecc_err_0; +}DPP_SMMU0_SMMU0_CTRL29_ARBITER_ECC_ERR_T; + +typedef struct dpp_smmu0_smmu0_ctrl30_arbiter_ecc_err_t +{ + ZXIC_UINT32 ctrl30_arbiter_ecc_err_31; + ZXIC_UINT32 ctrl30_arbiter_ecc_err_30; + ZXIC_UINT32 ctrl30_arbiter_ecc_err_29; + ZXIC_UINT32 ctrl30_arbiter_ecc_err_28; + ZXIC_UINT32 ctrl30_arbiter_ecc_err_27; + ZXIC_UINT32 ctrl30_arbiter_ecc_err_26; + ZXIC_UINT32 ctrl30_arbiter_ecc_err_25; + ZXIC_UINT32 ctrl30_arbiter_ecc_err_24; + ZXIC_UINT32 ctrl30_arbiter_ecc_err_23; + ZXIC_UINT32 ctrl30_arbiter_ecc_err_22; + ZXIC_UINT32 ctrl30_arbiter_ecc_err_21; + ZXIC_UINT32 ctrl30_arbiter_ecc_err_20; + ZXIC_UINT32 ctrl30_arbiter_ecc_err_19; + ZXIC_UINT32 ctrl30_arbiter_ecc_err_18; + ZXIC_UINT32 ctrl30_arbiter_ecc_err_17; + ZXIC_UINT32 ctrl30_arbiter_ecc_err_16; + ZXIC_UINT32 ctrl30_arbiter_ecc_err_15; + ZXIC_UINT32 ctrl30_arbiter_ecc_err_14; + ZXIC_UINT32 ctrl30_arbiter_ecc_err_13; + ZXIC_UINT32 ctrl30_arbiter_ecc_err_12; + ZXIC_UINT32 ctrl30_arbiter_ecc_err_11; + ZXIC_UINT32 ctrl30_arbiter_ecc_err_10; + ZXIC_UINT32 ctrl30_arbiter_ecc_err_9; + ZXIC_UINT32 ctrl30_arbiter_ecc_err_8; + ZXIC_UINT32 ctrl30_arbiter_ecc_err_7; + ZXIC_UINT32 ctrl30_arbiter_ecc_err_6; + ZXIC_UINT32 ctrl30_arbiter_ecc_err_5; + ZXIC_UINT32 ctrl30_arbiter_ecc_err_4; + ZXIC_UINT32 ctrl30_arbiter_ecc_err_3; + ZXIC_UINT32 ctrl30_arbiter_ecc_err_2; + ZXIC_UINT32 ctrl30_arbiter_ecc_err_1; + ZXIC_UINT32 ctrl30_arbiter_ecc_err_0; +}DPP_SMMU0_SMMU0_CTRL30_ARBITER_ECC_ERR_T; + +typedef struct dpp_smmu0_smmu0_ctrl31_arbiter_ecc_err_t +{ + ZXIC_UINT32 ctrl31_arbiter_ecc_err_31; + ZXIC_UINT32 ctrl31_arbiter_ecc_err_30; + ZXIC_UINT32 ctrl31_arbiter_ecc_err_29; + ZXIC_UINT32 ctrl31_arbiter_ecc_err_28; + ZXIC_UINT32 ctrl31_arbiter_ecc_err_27; + ZXIC_UINT32 ctrl31_arbiter_ecc_err_26; + ZXIC_UINT32 ctrl31_arbiter_ecc_err_25; + ZXIC_UINT32 ctrl31_arbiter_ecc_err_24; + ZXIC_UINT32 ctrl31_arbiter_ecc_err_23; + ZXIC_UINT32 ctrl31_arbiter_ecc_err_22; + ZXIC_UINT32 ctrl31_arbiter_ecc_err_21; + ZXIC_UINT32 ctrl31_arbiter_ecc_err_20; + ZXIC_UINT32 ctrl31_arbiter_ecc_err_19; + ZXIC_UINT32 ctrl31_arbiter_ecc_err_18; + ZXIC_UINT32 ctrl31_arbiter_ecc_err_17; + ZXIC_UINT32 ctrl31_arbiter_ecc_err_16; + ZXIC_UINT32 ctrl31_arbiter_ecc_err_15; + ZXIC_UINT32 ctrl31_arbiter_ecc_err_14; + ZXIC_UINT32 ctrl31_arbiter_ecc_err_13; + ZXIC_UINT32 ctrl31_arbiter_ecc_err_12; + ZXIC_UINT32 ctrl31_arbiter_ecc_err_11; + ZXIC_UINT32 ctrl31_arbiter_ecc_err_10; + ZXIC_UINT32 ctrl31_arbiter_ecc_err_9; + ZXIC_UINT32 ctrl31_arbiter_ecc_err_8; + ZXIC_UINT32 ctrl31_arbiter_ecc_err_7; + ZXIC_UINT32 ctrl31_arbiter_ecc_err_6; + ZXIC_UINT32 ctrl31_arbiter_ecc_err_5; + ZXIC_UINT32 ctrl31_arbiter_ecc_err_4; + ZXIC_UINT32 ctrl31_arbiter_ecc_err_3; + ZXIC_UINT32 ctrl31_arbiter_ecc_err_2; + ZXIC_UINT32 ctrl31_arbiter_ecc_err_1; + ZXIC_UINT32 ctrl31_arbiter_ecc_err_0; +}DPP_SMMU0_SMMU0_CTRL31_ARBITER_ECC_ERR_T; + +typedef struct dpp_smmu0_smmu0_ctrl_req_ecc_single_err_t +{ + ZXIC_UINT32 ctrl_req_ecc_single_err_0_31; +}DPP_SMMU0_SMMU0_CTRL_REQ_ECC_SINGLE_ERR_T; + +typedef struct dpp_smmu0_smmu0_ctrl_req_ecc_double_err_t +{ + ZXIC_UINT32 ctrl_req_ecc_double_err_0_31; +}DPP_SMMU0_SMMU0_CTRL_REQ_ECC_DOUBLE_ERR_T; + +typedef struct dpp_smmu0_smmu0_ctrl_info_ecc_single_err_t +{ + ZXIC_UINT32 ctrl_info_ecc_single_err_0_31; +}DPP_SMMU0_SMMU0_CTRL_INFO_ECC_SINGLE_ERR_T; + +typedef struct dpp_smmu0_smmu0_ctrl_info_ecc_double_err_t +{ + ZXIC_UINT32 ctrl_info_ecc_double_err_0_31; +}DPP_SMMU0_SMMU0_CTRL_INFO_ECC_DOUBLE_ERR_T; + +typedef struct dpp_smmu0_smmu0_smmu0_wr_ecc_err_t +{ + ZXIC_UINT32 smmu0_wr_ecc_err_3; + ZXIC_UINT32 smmu0_wr_ecc_err_2; + ZXIC_UINT32 smmu0_wr_ecc_err_1; + ZXIC_UINT32 smmu0_wr_ecc_err_0; +}DPP_SMMU0_SMMU0_SMMU0_WR_ECC_ERR_T; + +typedef struct dpp_smmu0_smmu0_smmu0_rschd_ecc_single_err_t +{ + ZXIC_UINT32 smmu0_rschd_ecc_single_err_0_31; +}DPP_SMMU0_SMMU0_SMMU0_RSCHD_ECC_SINGLE_ERR_T; + +typedef struct dpp_smmu0_smmu0_smmu0_rschd_ecc_double_err_t +{ + ZXIC_UINT32 smmu0_rschd_ecc_double_err_0_31; +}DPP_SMMU0_SMMU0_SMMU0_RSCHD_ECC_DOUBLE_ERR_T; + +typedef struct dpp_smmu0_smmu0_ord_fifo_empty_t +{ + ZXIC_UINT32 ord_fifo_empty; +}DPP_SMMU0_SMMU0_ORD_FIFO_EMPTY_T; + +typedef struct dpp_smmu0_smmu0_wr_arb_fifo_empty_t +{ + ZXIC_UINT32 wr_arb_fifo_empty; +}DPP_SMMU0_SMMU0_WR_ARB_FIFO_EMPTY_T; + +typedef struct dpp_smmu0_smmu0_ctrl_fifo_empty0_t +{ + ZXIC_UINT32 ctrl_fifo_empty0_5; + ZXIC_UINT32 ctrl_fifo_empty0_4; + ZXIC_UINT32 ctrl_fifo_empty0_3; + ZXIC_UINT32 ctrl_fifo_empty0_2; + ZXIC_UINT32 ctrl_fifo_empty0_1; + ZXIC_UINT32 ctrl_fifo_empty0_0; +}DPP_SMMU0_SMMU0_CTRL_FIFO_EMPTY0_T; + +typedef struct dpp_smmu0_smmu0_ctrl_fifo_empty1_t +{ + ZXIC_UINT32 ctrl_fifo_empty1_5; + ZXIC_UINT32 ctrl_fifo_empty1_4; + ZXIC_UINT32 ctrl_fifo_empty1_3; + ZXIC_UINT32 ctrl_fifo_empty1_2; + ZXIC_UINT32 ctrl_fifo_empty1_1; + ZXIC_UINT32 ctrl_fifo_empty1_0; +}DPP_SMMU0_SMMU0_CTRL_FIFO_EMPTY1_T; + +typedef struct dpp_smmu0_smmu0_ctrl_fifo_empty2_t +{ + ZXIC_UINT32 ctrl_fifo_empty2_5; + ZXIC_UINT32 ctrl_fifo_empty2_4; + ZXIC_UINT32 ctrl_fifo_empty2_3; + ZXIC_UINT32 ctrl_fifo_empty2_2; + ZXIC_UINT32 ctrl_fifo_empty2_1; + ZXIC_UINT32 ctrl_fifo_empty2_0; +}DPP_SMMU0_SMMU0_CTRL_FIFO_EMPTY2_T; + +typedef struct dpp_smmu0_smmu0_ctrl_fifo_empty3_t +{ + ZXIC_UINT32 ctrl_fifo_empty3_5; + ZXIC_UINT32 ctrl_fifo_empty3_4; + ZXIC_UINT32 ctrl_fifo_empty3_3; + ZXIC_UINT32 ctrl_fifo_empty3_2; + ZXIC_UINT32 ctrl_fifo_empty3_1; + ZXIC_UINT32 ctrl_fifo_empty3_0; +}DPP_SMMU0_SMMU0_CTRL_FIFO_EMPTY3_T; + +typedef struct dpp_smmu0_smmu0_ctrl_fifo_empty4_t +{ + ZXIC_UINT32 ctrl_fifo_empty4_5; + ZXIC_UINT32 ctrl_fifo_empty4_4; + ZXIC_UINT32 ctrl_fifo_empty4_3; + ZXIC_UINT32 ctrl_fifo_empty4_2; + ZXIC_UINT32 ctrl_fifo_empty4_1; + ZXIC_UINT32 ctrl_fifo_empty4_0; +}DPP_SMMU0_SMMU0_CTRL_FIFO_EMPTY4_T; + +typedef struct dpp_smmu0_smmu0_ctrl_fifo_empty5_t +{ + ZXIC_UINT32 ctrl_fifo_empty5_1; + ZXIC_UINT32 ctrl_fifo_empty5_0; +}DPP_SMMU0_SMMU0_CTRL_FIFO_EMPTY5_T; + +typedef struct dpp_smmu0_smmu0_kschd_fifo_empty0_t +{ + ZXIC_UINT32 kschd_fifo_empty0; +}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY0_T; + +typedef struct dpp_smmu0_smmu0_kschd_fifo_empty1_t +{ + ZXIC_UINT32 kschd_fifo_empty1; +}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY1_T; + +typedef struct dpp_smmu0_smmu0_kschd_fifo_empty2_t +{ + ZXIC_UINT32 kschd_fifo_empty2; +}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY2_T; + +typedef struct dpp_smmu0_smmu0_kschd_fifo_empty3_t +{ + ZXIC_UINT32 kschd_fifo_empty3; +}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY3_T; + +typedef struct dpp_smmu0_smmu0_kschd_fifo_empty4_t +{ + ZXIC_UINT32 kschd_fifo_empty4; +}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY4_T; + +typedef struct dpp_smmu0_smmu0_kschd_fifo_empty5_t +{ + ZXIC_UINT32 kschd_fifo_empty5; +}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY5_T; + +typedef struct dpp_smmu0_smmu0_kschd_fifo_empty6_t +{ + ZXIC_UINT32 kschd_fifo_empty6; +}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY6_T; + +typedef struct dpp_smmu0_smmu0_kschd_fifo_empty7_t +{ + ZXIC_UINT32 kschd_fifo_empty7; +}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY7_T; + +typedef struct dpp_smmu0_smmu0_kschd_fifo_empty8_t +{ + ZXIC_UINT32 kschd_fifo_empty8; +}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY8_T; + +typedef struct dpp_smmu0_smmu0_kschd_fifo_empty9_t +{ + ZXIC_UINT32 kschd_fifo_empty9; +}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY9_T; + +typedef struct dpp_smmu0_smmu0_kschd_fifo_empty10_t +{ + ZXIC_UINT32 kschd_fifo_empty10; +}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY10_T; + +typedef struct dpp_smmu0_smmu0_kschd_fifo_empty11_t +{ + ZXIC_UINT32 kschd_fifo_empty11; +}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY11_T; + +typedef struct dpp_smmu0_smmu0_kschd_fifo_empty12_t +{ + ZXIC_UINT32 kschd_fifo_empty12; +}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY12_T; + +typedef struct dpp_smmu0_smmu0_kschd_fifo_empty13_t +{ + ZXIC_UINT32 kschd_fifo_empty13; +}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY13_T; + +typedef struct dpp_smmu0_smmu0_kschd_fifo_empty14_t +{ + ZXIC_UINT32 kschd_fifo_empty14; +}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY14_T; + +typedef struct dpp_smmu0_smmu0_kschd_fifo_empty15_t +{ + ZXIC_UINT32 kschd_fifo_empty15; +}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY15_T; + +typedef struct dpp_smmu0_smmu0_kschd_fifo_empty16_t +{ + ZXIC_UINT32 kschd_fifo_empty16; +}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY16_T; + +typedef struct dpp_smmu0_smmu0_kschd_fifo_empty17_t +{ + ZXIC_UINT32 kschd_fifo_empty17; +}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY17_T; + +typedef struct dpp_smmu0_smmu0_kschd_fifo_empty18_t +{ + ZXIC_UINT32 kschd_fifo_empty18; +}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY18_T; + +typedef struct dpp_smmu0_smmu0_kschd_fifo_empty19_t +{ + ZXIC_UINT32 kschd_fifo_empty19; +}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY19_T; + +typedef struct dpp_smmu0_smmu0_kschd_fifo_empty20_t +{ + ZXIC_UINT32 kschd_fifo_empty20; +}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY20_T; + +typedef struct dpp_smmu0_smmu0_kschd_fifo_empty21_t +{ + ZXIC_UINT32 kschd_fifo_empty21; +}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY21_T; + +typedef struct dpp_smmu0_smmu0_kschd_fifo_empty22_t +{ + ZXIC_UINT32 kschd_fifo_empty22; +}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY22_T; + +typedef struct dpp_smmu0_smmu0_kschd_fifo_empty23_t +{ + ZXIC_UINT32 kschd_fifo_empty23; +}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY23_T; + +typedef struct dpp_smmu0_smmu0_kschd_fifo_empty24_t +{ + ZXIC_UINT32 kschd_fifo_empty24; +}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY24_T; + +typedef struct dpp_smmu0_smmu0_kschd_fifo_empty25_t +{ + ZXIC_UINT32 kschd_fifo_empty25; +}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY25_T; + +typedef struct dpp_smmu0_smmu0_kschd_fifo_empty26_t +{ + ZXIC_UINT32 kschd_fifo_empty26; +}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY26_T; + +typedef struct dpp_smmu0_smmu0_kschd_fifo_empty27_t +{ + ZXIC_UINT32 kschd_fifo_empty27; +}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY27_T; + +typedef struct dpp_smmu0_smmu0_kschd_fifo_empty28_t +{ + ZXIC_UINT32 kschd_fifo_empty28; +}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY28_T; + +typedef struct dpp_smmu0_smmu0_kschd_fifo_empty29_t +{ + ZXIC_UINT32 kschd_fifo_empty29; +}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY29_T; + +typedef struct dpp_smmu0_smmu0_kschd_fifo_empty30_t +{ + ZXIC_UINT32 kschd_fifo_empty30; +}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY30_T; + +typedef struct dpp_smmu0_smmu0_kschd_fifo_empty31_t +{ + ZXIC_UINT32 kschd_fifo_empty31; +}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY31_T; + +typedef struct dpp_smmu0_smmu0_rschd_fifo_empty0_t +{ + ZXIC_UINT32 rschd_fifo_empty0; +}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY0_T; + +typedef struct dpp_smmu0_smmu0_rschd_fifo_empty1_t +{ + ZXIC_UINT32 rschd_fifo_empty1; +}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY1_T; + +typedef struct dpp_smmu0_smmu0_rschd_fifo_empty2_t +{ + ZXIC_UINT32 rschd_fifo_empty2; +}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY2_T; + +typedef struct dpp_smmu0_smmu0_rschd_fifo_empty3_t +{ + ZXIC_UINT32 rschd_fifo_empty3; +}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY3_T; + +typedef struct dpp_smmu0_smmu0_rschd_fifo_empty4_t +{ + ZXIC_UINT32 rschd_fifo_empty4; +}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY4_T; + +typedef struct dpp_smmu0_smmu0_rschd_fifo_empty5_t +{ + ZXIC_UINT32 rschd_fifo_empty5; +}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY5_T; + +typedef struct dpp_smmu0_smmu0_rschd_fifo_empty6_t +{ + ZXIC_UINT32 rschd_fifo_empty6; +}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY6_T; + +typedef struct dpp_smmu0_smmu0_rschd_fifo_empty7_t +{ + ZXIC_UINT32 rschd_fifo_empty7; +}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY7_T; + +typedef struct dpp_smmu0_smmu0_rschd_fifo_empty8_t +{ + ZXIC_UINT32 rschd_fifo_empty8; +}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY8_T; + +typedef struct dpp_smmu0_smmu0_rschd_fifo_empty9_t +{ + ZXIC_UINT32 rschd_fifo_empty9; +}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY9_T; + +typedef struct dpp_smmu0_smmu0_rschd_fifo_empty10_t +{ + ZXIC_UINT32 rschd_fifo_empty10; +}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY10_T; + +typedef struct dpp_smmu0_smmu0_rschd_fifo_empty11_t +{ + ZXIC_UINT32 rschd_fifo_empty11; +}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY11_T; + +typedef struct dpp_smmu0_smmu0_rschd_fifo_empty12_t +{ + ZXIC_UINT32 rschd_fifo_empty12; +}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY12_T; + +typedef struct dpp_smmu0_smmu0_rschd_fifo_empty13_t +{ + ZXIC_UINT32 rschd_fifo_empty13; +}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY13_T; + +typedef struct dpp_smmu0_smmu0_rschd_fifo_empty14_t +{ + ZXIC_UINT32 rschd_fifo_empty14; +}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY14_T; + +typedef struct dpp_smmu0_smmu0_rschd_fifo_empty15_t +{ + ZXIC_UINT32 rschd_fifo_empty15; +}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY15_T; + +typedef struct dpp_smmu0_smmu0_rschd_fifo_empty16_t +{ + ZXIC_UINT32 rschd_fifo_empty16; +}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY16_T; + +typedef struct dpp_smmu0_smmu0_rschd_fifo_empty17_t +{ + ZXIC_UINT32 rschd_fifo_empty17; +}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY17_T; + +typedef struct dpp_smmu0_smmu0_rschd_fifo_empty18_t +{ + ZXIC_UINT32 rschd_fifo_empty18; +}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY18_T; + +typedef struct dpp_smmu0_smmu0_rschd_fifo_empty19_t +{ + ZXIC_UINT32 rschd_fifo_empty19; +}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY19_T; + +typedef struct dpp_smmu0_smmu0_rschd_fifo_empty20_t +{ + ZXIC_UINT32 rschd_fifo_empty20; +}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY20_T; + +typedef struct dpp_smmu0_smmu0_rschd_fifo_empty21_t +{ + ZXIC_UINT32 rschd_fifo_empty21; +}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY21_T; + +typedef struct dpp_smmu0_smmu0_rschd_fifo_empty22_t +{ + ZXIC_UINT32 rschd_fifo_empty22; +}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY22_T; + +typedef struct dpp_smmu0_smmu0_rschd_fifo_empty23_t +{ + ZXIC_UINT32 rschd_fifo_empty23; +}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY23_T; + +typedef struct dpp_smmu0_smmu0_rschd_fifo_empty24_t +{ + ZXIC_UINT32 rschd_fifo_empty24; +}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY24_T; + +typedef struct dpp_smmu0_smmu0_rschd_fifo_empty25_t +{ + ZXIC_UINT32 rschd_fifo_empty25; +}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY25_T; + +typedef struct dpp_smmu0_smmu0_rschd_fifo_empty26_t +{ + ZXIC_UINT32 rschd_fifo_empty26; +}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY26_T; + +typedef struct dpp_smmu0_smmu0_rschd_fifo_empty27_t +{ + ZXIC_UINT32 rschd_fifo_empty27; +}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY27_T; + +typedef struct dpp_smmu0_smmu0_rschd_fifo_empty28_t +{ + ZXIC_UINT32 rschd_fifo_empty28; +}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY28_T; + +typedef struct dpp_smmu0_smmu0_rschd_fifo_empty29_t +{ + ZXIC_UINT32 rschd_fifo_empty29; +}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY29_T; + +typedef struct dpp_smmu0_smmu0_rschd_fifo_empty30_t +{ + ZXIC_UINT32 rschd_fifo_empty30; +}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY30_T; + +typedef struct dpp_smmu0_smmu0_rschd_fifo_empty31_t +{ + ZXIC_UINT32 rschd_fifo_empty31; +}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY31_T; + +typedef struct dpp_smmu0_smmu0_ept_flag_t +{ + ZXIC_UINT32 ept_flag8; + ZXIC_UINT32 ept_flag7; + ZXIC_UINT32 ept_flag6; + ZXIC_UINT32 ept_flag5; + ZXIC_UINT32 ept_flag4; + ZXIC_UINT32 ept_flag3; + ZXIC_UINT32 ept_flag2; + ZXIC_UINT32 ept_flag1; + ZXIC_UINT32 ept_flag0; +}DPP_SMMU0_SMMU0_EPT_FLAG_T; + +typedef struct dpp_smmu0_smmu0_ppu_soft_rst_t +{ + ZXIC_UINT32 ppu_soft_rst; +}DPP_SMMU0_SMMU0_PPU_SOFT_RST_T; + +typedef struct dpp_smmu0_smmu0_smmu0_as_mac_age_fc_cnt_t +{ + ZXIC_UINT32 smmu0_as_mac_age_fc_cnt; +}DPP_SMMU0_SMMU0_SMMU0_AS_MAC_AGE_FC_CNT_T; + +typedef struct dpp_smmu0_smmu0_smmu0_marc_se_parser_fc_cnt_t +{ + ZXIC_UINT32 smmu0_marc_se_parser_fc_cnt; +}DPP_SMMU0_SMMU0_SMMU0_MARC_SE_PARSER_FC_CNT_T; + +typedef struct dpp_smmu0_smmu0_wr_arb_cpu_fc_cnt_t +{ + ZXIC_UINT32 wr_arb_cpu_fc_cnt; +}DPP_SMMU0_SMMU0_WR_ARB_CPU_FC_CNT_T; + +typedef struct dpp_smmu0_smmu0_smmu0_lpm_as_fc_cnt_t +{ + ZXIC_UINT32 smmu0_lpm_as_fc_cnt; +}DPP_SMMU0_SMMU0_SMMU0_LPM_AS_FC_CNT_T; + +typedef struct dpp_smmu0_smmu0_lpm_as_smmu0_fc_cnt_t +{ + ZXIC_UINT32 lpm_as_smmu0_fc_cnt; +}DPP_SMMU0_SMMU0_LPM_AS_SMMU0_FC_CNT_T; + +typedef struct dpp_smmu0_smmu0_smmu0_etcam1_0_as_fc_cnt_t +{ + ZXIC_UINT32 smmu0_etcam1_0_as_fc_cnt; +}DPP_SMMU0_SMMU0_SMMU0_ETCAM1_0_AS_FC_CNT_T; + +typedef struct dpp_smmu0_smmu0_as_etcam1_0_smmu0_fc_cnt_t +{ + ZXIC_UINT32 as_etcam1_0_smmu0_fc_cnt; +}DPP_SMMU0_SMMU0_AS_ETCAM1_0_SMMU0_FC_CNT_T; + +typedef struct dpp_smmu0_smmu0_smmu0_ppu_mcast_fc_cnt_t +{ + ZXIC_UINT32 smmu0_ppu_mcast_fc_cnt; +}DPP_SMMU0_SMMU0_SMMU0_PPU_MCAST_FC_CNT_T; + +typedef struct dpp_smmu0_smmu0_ppu_smmu0_mcast_fc_cnt_t +{ + ZXIC_UINT32 ppu_smmu0_mcast_fc_cnt; +}DPP_SMMU0_SMMU0_PPU_SMMU0_MCAST_FC_CNT_T; + +typedef struct dpp_smmu0_smmu0_odma_smmu0_tdm_fc_rsp_fc_cnt_t +{ + ZXIC_UINT32 odma_smmu0_tdm_fc_rsp_fc_cnt; +}DPP_SMMU0_SMMU0_ODMA_SMMU0_TDM_FC_RSP_FC_CNT_T; + +typedef struct dpp_smmu0_smmu0_smmu0_odma_tdm_fc_key_fc_cnt_t +{ + ZXIC_UINT32 smmu0_odma_tdm_fc_key_fc_cnt; +}DPP_SMMU0_SMMU0_SMMU0_ODMA_TDM_FC_KEY_FC_CNT_T; + +typedef struct dpp_smmu0_smmu0_smmu0_odma_fc_cnt_t +{ + ZXIC_UINT32 smmu0_odma_fc_cnt; +}DPP_SMMU0_SMMU0_SMMU0_ODMA_FC_CNT_T; + +typedef struct dpp_smmu0_smmu0_smmu0_cfg_tab_rd_fc_cnt_t +{ + ZXIC_UINT32 smmu0_cfg_tab_rd_fc_cnt; +}DPP_SMMU0_SMMU0_SMMU0_CFG_TAB_RD_FC_CNT_T; + +typedef struct dpp_smmu0_smmu0_smmu0_stat_fc15_0_cnt_t +{ + ZXIC_UINT32 smmu0_stat_fc15_0_cnt; +}DPP_SMMU0_SMMU0_SMMU0_STAT_FC15_0_CNT_T; + +typedef struct dpp_smmu0_smmu0_stat_smmu0_fc15_0_cnt_t +{ + ZXIC_UINT32 stat_smmu0_fc15_0_cnt; +}DPP_SMMU0_SMMU0_STAT_SMMU0_FC15_0_CNT_T; + +typedef struct dpp_smmu0_smmu0_smmu0_ppu_mex5_0_fc_cnt_t +{ + ZXIC_UINT32 smmu0_ppu_mex5_0_fc_cnt; +}DPP_SMMU0_SMMU0_SMMU0_PPU_MEX5_0_FC_CNT_T; + +typedef struct dpp_smmu0_smmu0_ppu_smmu0_mex5_0_fc_cnt_t +{ + ZXIC_UINT32 ppu_smmu0_mex5_0_fc_cnt; +}DPP_SMMU0_SMMU0_PPU_SMMU0_MEX5_0_FC_CNT_T; + +typedef struct dpp_smmu0_smmu0_as_smmu0_mac_age_req_cnt_t +{ + ZXIC_UINT32 as_smmu0_mac_age_req_cnt; +}DPP_SMMU0_SMMU0_AS_SMMU0_MAC_AGE_REQ_CNT_T; + +typedef struct dpp_smmu0_smmu0_se_parser_smmu0_marc_key_cnt_t +{ + ZXIC_UINT32 se_parser_smmu0_marc_key_cnt; +}DPP_SMMU0_SMMU0_SE_PARSER_SMMU0_MARC_KEY_CNT_T; + +typedef struct dpp_smmu0_smmu0_cpu_ind_rdat_cnt_t +{ + ZXIC_UINT32 cpu_ind_rdat_cnt; +}DPP_SMMU0_SMMU0_CPU_IND_RDAT_CNT_T; + +typedef struct dpp_smmu0_smmu0_cpu_ind_rd_req_cnt_t +{ + ZXIC_UINT32 cpu_ind_rd_req_cnt; +}DPP_SMMU0_SMMU0_CPU_IND_RD_REQ_CNT_T; + +typedef struct dpp_smmu0_smmu0_cpu_ind_wr_req_cnt_t +{ + ZXIC_UINT32 cpu_ind_wr_req_cnt; +}DPP_SMMU0_SMMU0_CPU_IND_WR_REQ_CNT_T; + +typedef struct dpp_smmu0_smmu0_smmu0_plcr_rsp0_cnt_t +{ + ZXIC_UINT32 smmu0_plcr_rsp0_cnt; +}DPP_SMMU0_SMMU0_SMMU0_PLCR_RSP0_CNT_T; + +typedef struct dpp_smmu0_smmu0_plcr_smmu0_req0_cnt_t +{ + ZXIC_UINT32 plcr_smmu0_req0_cnt; +}DPP_SMMU0_SMMU0_PLCR_SMMU0_REQ0_CNT_T; + +typedef struct dpp_smmu0_smmu0_smmu0_lpm_as_rsp_cnt_t +{ + ZXIC_UINT32 smmu0_lpm_as_rsp_cnt; +}DPP_SMMU0_SMMU0_SMMU0_LPM_AS_RSP_CNT_T; + +typedef struct dpp_smmu0_smmu0_lpm_as_smmu0_req_cnt_t +{ + ZXIC_UINT32 lpm_as_smmu0_req_cnt; +}DPP_SMMU0_SMMU0_LPM_AS_SMMU0_REQ_CNT_T; + +typedef struct dpp_smmu0_smmu0_smmu0_etcam1_0_as_rsp_cnt_t +{ + ZXIC_UINT32 smmu0_etcam1_0_as_rsp_cnt; +}DPP_SMMU0_SMMU0_SMMU0_ETCAM1_0_AS_RSP_CNT_T; + +typedef struct dpp_smmu0_smmu0_etcam1_0_as_smmu0_req_cnt_t +{ + ZXIC_UINT32 etcam1_0_as_smmu0_req_cnt; +}DPP_SMMU0_SMMU0_ETCAM1_0_AS_SMMU0_REQ_CNT_T; + +typedef struct dpp_smmu0_smmu0_smmu0_ppu_mcast_rsp_cnt_t +{ + ZXIC_UINT32 smmu0_ppu_mcast_rsp_cnt; +}DPP_SMMU0_SMMU0_SMMU0_PPU_MCAST_RSP_CNT_T; + +typedef struct dpp_smmu0_smmu0_ppu_smmu0_mcast_key_cnt_t +{ + ZXIC_UINT32 ppu_smmu0_mcast_key_cnt; +}DPP_SMMU0_SMMU0_PPU_SMMU0_MCAST_KEY_CNT_T; + +typedef struct dpp_smmu0_smmu0_smmu0_odma_tdm_mc_rsp_cnt_t +{ + ZXIC_UINT32 smmu0_odma_tdm_mc_rsp_cnt; +}DPP_SMMU0_SMMU0_SMMU0_ODMA_TDM_MC_RSP_CNT_T; + +typedef struct dpp_smmu0_smmu0_odma_smmu0_tdm_mc_key_cnt_t +{ + ZXIC_UINT32 odma_smmu0_tdm_mc_key_cnt; +}DPP_SMMU0_SMMU0_ODMA_SMMU0_TDM_MC_KEY_CNT_T; + +typedef struct dpp_smmu0_smmu0_smmu0_odma_rsp_cnt_t +{ + ZXIC_UINT32 smmu0_odma_rsp_cnt; +}DPP_SMMU0_SMMU0_SMMU0_ODMA_RSP_CNT_T; + +typedef struct dpp_smmu0_smmu0_odma_smmu0_cmd_cnt_t +{ + ZXIC_UINT32 odma_smmu0_cmd_cnt; +}DPP_SMMU0_SMMU0_ODMA_SMMU0_CMD_CNT_T; + +typedef struct dpp_smmu0_smmu0_smmu0_cfg_tab_rdat_cnt_t +{ + ZXIC_UINT32 smmu0_cfg_tab_rdat_cnt; +}DPP_SMMU0_SMMU0_SMMU0_CFG_TAB_RDAT_CNT_T; + +typedef struct dpp_smmu0_smmu0_cfg_smmu0_tab_rd_cnt_t +{ + ZXIC_UINT32 cfg_smmu0_tab_rd_cnt; +}DPP_SMMU0_SMMU0_CFG_SMMU0_TAB_RD_CNT_T; + +typedef struct dpp_smmu0_smmu0_smmu0_stat_rsp15_0_cnt_t +{ + ZXIC_UINT32 smmu0_stat_rsp15_0_cnt; +}DPP_SMMU0_SMMU0_SMMU0_STAT_RSP15_0_CNT_T; + +typedef struct dpp_smmu0_smmu0_stat_smmu0_req15_0_cnt_t +{ + ZXIC_UINT32 stat_smmu0_req15_0_cnt; +}DPP_SMMU0_SMMU0_STAT_SMMU0_REQ15_0_CNT_T; + +typedef struct dpp_smmu0_smmu0_smmu0_ppu_mex5_0_rsp_cnt_t +{ + ZXIC_UINT32 smmu0_ppu_mex5_0_rsp_cnt; +}DPP_SMMU0_SMMU0_SMMU0_PPU_MEX5_0_RSP_CNT_T; + +typedef struct dpp_smmu0_smmu0_ppu_smmu0_mex5_0_key_cnt_t +{ + ZXIC_UINT32 ppu_smmu0_mex5_0_key_cnt; +}DPP_SMMU0_SMMU0_PPU_SMMU0_MEX5_0_KEY_CNT_T; + +typedef struct dpp_smmu0_smmu0_ftm_stat_smmu0_req0_cnt_t +{ + ZXIC_UINT32 ftm_stat_smmu0_req0_cnt; +}DPP_SMMU0_SMMU0_FTM_STAT_SMMU0_REQ0_CNT_T; + +typedef struct dpp_smmu0_smmu0_ftm_stat_smmu0_req1_cnt_t +{ + ZXIC_UINT32 ftm_stat_smmu0_req1_cnt; +}DPP_SMMU0_SMMU0_FTM_STAT_SMMU0_REQ1_CNT_T; + +typedef struct dpp_smmu0_smmu0_etm_stat_smmu0_req0_cnt_t +{ + ZXIC_UINT32 etm_stat_smmu0_req0_cnt; +}DPP_SMMU0_SMMU0_ETM_STAT_SMMU0_REQ0_CNT_T; + +typedef struct dpp_smmu0_smmu0_etm_stat_smmu0_req1_cnt_t +{ + ZXIC_UINT32 etm_stat_smmu0_req1_cnt; +}DPP_SMMU0_SMMU0_ETM_STAT_SMMU0_REQ1_CNT_T; + +typedef struct dpp_smmu0_smmu0_req_eram0_31_rd_cnt_t +{ + ZXIC_UINT32 req_eram0_31_rd_cnt; +}DPP_SMMU0_SMMU0_REQ_ERAM0_31_RD_CNT_T; + +typedef struct dpp_smmu0_smmu0_req_eram0_31_wr_cnt_t +{ + ZXIC_UINT32 req_eram0_31_wr_cnt; +}DPP_SMMU0_SMMU0_REQ_ERAM0_31_WR_CNT_T; + + +#ifdef __cplusplus +} +#endif +#endif + diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_smmu14k_reg.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_smmu14k_reg.h new file mode 100644 index 0000000..734cbfb --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_smmu14k_reg.h @@ -0,0 +1,238 @@ + +#ifndef _DPP_SMMU14K_REG_H_ +#define _DPP_SMMU14K_REG_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +typedef struct dpp_smmu14k_se_smmu1_hash0_tbl0_cfg_t +{ + ZXIC_UINT32 hash0_tbl0_len; + ZXIC_UINT32 hash0_tbl0_ecc_en; + ZXIC_UINT32 hash0_tbl0_baddr; +}DPP_SMMU14K_SE_SMMU1_HASH0_TBL0_CFG_T; + +typedef struct dpp_smmu14k_se_smmu1_hash0_tbl1_cfg_t +{ + ZXIC_UINT32 hash0_tbl1_len; + ZXIC_UINT32 hash0_tbl1_ecc_en; + ZXIC_UINT32 hash0_tbl1_baddr; +}DPP_SMMU14K_SE_SMMU1_HASH0_TBL1_CFG_T; + +typedef struct dpp_smmu14k_se_smmu1_hash0_tbl2_cfg_t +{ + ZXIC_UINT32 hash0_tbl2_len; + ZXIC_UINT32 hash0_tbl2_ecc_en; + ZXIC_UINT32 hash0_tbl2_baddr; +}DPP_SMMU14K_SE_SMMU1_HASH0_TBL2_CFG_T; + +typedef struct dpp_smmu14k_se_smmu1_hash0_tbl3_cfg_t +{ + ZXIC_UINT32 hash0_tbl3_len; + ZXIC_UINT32 hash0_tbl3_ecc_en; + ZXIC_UINT32 hash0_tbl3_baddr; +}DPP_SMMU14K_SE_SMMU1_HASH0_TBL3_CFG_T; + +typedef struct dpp_smmu14k_se_smmu1_hash0_tbl4_cfg_t +{ + ZXIC_UINT32 hash0_tbl4_len; + ZXIC_UINT32 hash0_tbl4_ecc_en; + ZXIC_UINT32 hash0_tbl4_baddr; +}DPP_SMMU14K_SE_SMMU1_HASH0_TBL4_CFG_T; + +typedef struct dpp_smmu14k_se_smmu1_hash0_tbl5_cfg_t +{ + ZXIC_UINT32 hash0_tbl5_len; + ZXIC_UINT32 hash0_tbl5_ecc_en; + ZXIC_UINT32 hash0_tbl5_baddr; +}DPP_SMMU14K_SE_SMMU1_HASH0_TBL5_CFG_T; + +typedef struct dpp_smmu14k_se_smmu1_hash0_tbl6_cfg_t +{ + ZXIC_UINT32 hash0_tbl6_len; + ZXIC_UINT32 hash0_tbl6_ecc_en; + ZXIC_UINT32 hash0_tbl6_baddr; +}DPP_SMMU14K_SE_SMMU1_HASH0_TBL6_CFG_T; + +typedef struct dpp_smmu14k_se_smmu1_hash0_tbl7_cfg_t +{ + ZXIC_UINT32 hash0_tbl7_len; + ZXIC_UINT32 hash0_tbl7_ecc_en; + ZXIC_UINT32 hash0_tbl7_baddr; +}DPP_SMMU14K_SE_SMMU1_HASH0_TBL7_CFG_T; + +typedef struct dpp_smmu14k_se_smmu1_hash1_tbl0_cfg_t +{ + ZXIC_UINT32 hash1_tbl0_len; + ZXIC_UINT32 hash1_tbl0_ecc_en; + ZXIC_UINT32 hash1_tbl0_baddr; +}DPP_SMMU14K_SE_SMMU1_HASH1_TBL0_CFG_T; + +typedef struct dpp_smmu14k_se_smmu1_hash1_tbl1_cfg_t +{ + ZXIC_UINT32 hash1_tbl1_len; + ZXIC_UINT32 hash1_tbl1_ecc_en; + ZXIC_UINT32 hash1_tbl1_baddr; +}DPP_SMMU14K_SE_SMMU1_HASH1_TBL1_CFG_T; + +typedef struct dpp_smmu14k_se_smmu1_hash1_tbl2_cfg_t +{ + ZXIC_UINT32 hash1_tbl2_len; + ZXIC_UINT32 hash1_tbl2_ecc_en; + ZXIC_UINT32 hash1_tbl2_baddr; +}DPP_SMMU14K_SE_SMMU1_HASH1_TBL2_CFG_T; + +typedef struct dpp_smmu14k_se_smmu1_hash1_tbl3_cfg_t +{ + ZXIC_UINT32 hash1_tbl3_len; + ZXIC_UINT32 hash1_tbl3_ecc_en; + ZXIC_UINT32 hash1_tbl3_baddr; +}DPP_SMMU14K_SE_SMMU1_HASH1_TBL3_CFG_T; + +typedef struct dpp_smmu14k_se_smmu1_hash1_tbl4_cfg_t +{ + ZXIC_UINT32 hash1_tbl4_len; + ZXIC_UINT32 hash1_tbl4_ecc_en; + ZXIC_UINT32 hash1_tbl4_baddr; +}DPP_SMMU14K_SE_SMMU1_HASH1_TBL4_CFG_T; + +typedef struct dpp_smmu14k_se_smmu1_hash1_tbl5_cfg_t +{ + ZXIC_UINT32 hash1_tbl5_len; + ZXIC_UINT32 hash1_tbl5_ecc_en; + ZXIC_UINT32 hash1_tbl5_baddr; +}DPP_SMMU14K_SE_SMMU1_HASH1_TBL5_CFG_T; + +typedef struct dpp_smmu14k_se_smmu1_hash1_tbl6_cfg_t +{ + ZXIC_UINT32 hash1_tbl6_len; + ZXIC_UINT32 hash1_tbl6_ecc_en; + ZXIC_UINT32 hash1_tbl6_baddr; +}DPP_SMMU14K_SE_SMMU1_HASH1_TBL6_CFG_T; + +typedef struct dpp_smmu14k_se_smmu1_hash1_tbl7_cfg_t +{ + ZXIC_UINT32 hash1_tbl7_len; + ZXIC_UINT32 hash1_tbl7_ecc_en; + ZXIC_UINT32 hash1_tbl7_baddr; +}DPP_SMMU14K_SE_SMMU1_HASH1_TBL7_CFG_T; + +typedef struct dpp_smmu14k_se_smmu1_hash2_tbl0_cfg_t +{ + ZXIC_UINT32 hash2_tbl0_len; + ZXIC_UINT32 hash2_tbl0_ecc_en; + ZXIC_UINT32 hash2_tbl0_baddr; +}DPP_SMMU14K_SE_SMMU1_HASH2_TBL0_CFG_T; + +typedef struct dpp_smmu14k_se_smmu1_hash2_tbl1_cfg_t +{ + ZXIC_UINT32 hash2_tbl1_len; + ZXIC_UINT32 hash2_tbl1_ecc_en; + ZXIC_UINT32 hash2_tbl1_baddr; +}DPP_SMMU14K_SE_SMMU1_HASH2_TBL1_CFG_T; + +typedef struct dpp_smmu14k_se_smmu1_hash2_tbl2_cfg_t +{ + ZXIC_UINT32 hash2_tbl2_len; + ZXIC_UINT32 hash2_tbl2_ecc_en; + ZXIC_UINT32 hash2_tbl2_baddr; +}DPP_SMMU14K_SE_SMMU1_HASH2_TBL2_CFG_T; + +typedef struct dpp_smmu14k_se_smmu1_hash2_tbl3_cfg_t +{ + ZXIC_UINT32 hash2_tbl3_len; + ZXIC_UINT32 hash2_tbl3_ecc_en; + ZXIC_UINT32 hash2_tbl3_baddr; +}DPP_SMMU14K_SE_SMMU1_HASH2_TBL3_CFG_T; + +typedef struct dpp_smmu14k_se_smmu1_hash2_tbl4_cfg_t +{ + ZXIC_UINT32 hash2_tbl4_len; + ZXIC_UINT32 hash2_tbl4_ecc_en; + ZXIC_UINT32 hash2_tbl4_baddr; +}DPP_SMMU14K_SE_SMMU1_HASH2_TBL4_CFG_T; + +typedef struct dpp_smmu14k_se_smmu1_hash2_tbl5_cfg_t +{ + ZXIC_UINT32 hash2_tbl5_len; + ZXIC_UINT32 hash2_tbl5_ecc_en; + ZXIC_UINT32 hash2_tbl5_baddr; +}DPP_SMMU14K_SE_SMMU1_HASH2_TBL5_CFG_T; + +typedef struct dpp_smmu14k_se_smmu1_hash2_tbl6_cfg_t +{ + ZXIC_UINT32 hash2_tbl6_len; + ZXIC_UINT32 hash2_tbl6_ecc_en; + ZXIC_UINT32 hash2_tbl6_baddr; +}DPP_SMMU14K_SE_SMMU1_HASH2_TBL6_CFG_T; + +typedef struct dpp_smmu14k_se_smmu1_hash2_tbl7_cfg_t +{ + ZXIC_UINT32 hash2_tbl7_len; + ZXIC_UINT32 hash2_tbl7_ecc_en; + ZXIC_UINT32 hash2_tbl7_baddr; +}DPP_SMMU14K_SE_SMMU1_HASH2_TBL7_CFG_T; + +typedef struct dpp_smmu14k_se_smmu1_hash3_tbl0_cfg_t +{ + ZXIC_UINT32 hash3_tbl0_len; + ZXIC_UINT32 hash3_tbl0_ecc_en; + ZXIC_UINT32 hash3_tbl0_baddr; +}DPP_SMMU14K_SE_SMMU1_HASH3_TBL0_CFG_T; + +typedef struct dpp_smmu14k_se_smmu1_hash3_tbl1_cfg_t +{ + ZXIC_UINT32 hash3_tbl1_len; + ZXIC_UINT32 hash3_tbl1_ecc_en; + ZXIC_UINT32 hash3_tbl1_baddr; +}DPP_SMMU14K_SE_SMMU1_HASH3_TBL1_CFG_T; + +typedef struct dpp_smmu14k_se_smmu1_hash3_tbl2_cfg_t +{ + ZXIC_UINT32 hash3_tbl2_len; + ZXIC_UINT32 hash3_tbl2_ecc_en; + ZXIC_UINT32 hash3_tbl2_baddr; +}DPP_SMMU14K_SE_SMMU1_HASH3_TBL2_CFG_T; + +typedef struct dpp_smmu14k_se_smmu1_hash3_tbl3_cfg_t +{ + ZXIC_UINT32 hash3_tbl3_len; + ZXIC_UINT32 hash3_tbl3_ecc_en; + ZXIC_UINT32 hash3_tbl3_baddr; +}DPP_SMMU14K_SE_SMMU1_HASH3_TBL3_CFG_T; + +typedef struct dpp_smmu14k_se_smmu1_hash3_tbl4_cfg_t +{ + ZXIC_UINT32 hash3_tbl4_len; + ZXIC_UINT32 hash3_tbl4_ecc_en; + ZXIC_UINT32 hash3_tbl4_baddr; +}DPP_SMMU14K_SE_SMMU1_HASH3_TBL4_CFG_T; + +typedef struct dpp_smmu14k_se_smmu1_hash3_tbl5_cfg_t +{ + ZXIC_UINT32 hash3_tbl5_len; + ZXIC_UINT32 hash3_tbl5_ecc_en; + ZXIC_UINT32 hash3_tbl5_baddr; +}DPP_SMMU14K_SE_SMMU1_HASH3_TBL5_CFG_T; + +typedef struct dpp_smmu14k_se_smmu1_hash3_tbl6_cfg_t +{ + ZXIC_UINT32 hash3_tbl6_len; + ZXIC_UINT32 hash3_tbl6_ecc_en; + ZXIC_UINT32 hash3_tbl6_baddr; +}DPP_SMMU14K_SE_SMMU1_HASH3_TBL6_CFG_T; + +typedef struct dpp_smmu14k_se_smmu1_hash3_tbl7_cfg_t +{ + ZXIC_UINT32 hash3_tbl7_len; + ZXIC_UINT32 hash3_tbl7_ecc_en; + ZXIC_UINT32 hash3_tbl7_baddr; +}DPP_SMMU14K_SE_SMMU1_HASH3_TBL7_CFG_T; + + +#ifdef __cplusplus +} +#endif +#endif + diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_smmu1_reg.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_smmu1_reg.h new file mode 100644 index 0000000..72ddae5 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_smmu1_reg.h @@ -0,0 +1,1327 @@ + +#ifndef _DPP_SMMU1_REG_H_ +#define _DPP_SMMU1_REG_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +typedef struct dpp_se_smmu1_ddr_wdat0_t +{ + ZXIC_UINT32 ddr_wdat0; +}DPP_SE_SMMU1_DDR_WDAT0_T; + +typedef struct dpp_se_smmu1_dir_arbi_ser_rpful_t +{ + ZXIC_UINT32 dir_arbi_ser_rpful; +}DPP_SE_SMMU1_DIR_ARBI_SER_RPFUL_T; + +typedef struct dpp_se_smmu1_cfg_wr_arbi_pful2_t +{ + ZXIC_UINT32 hash_wr_pful; + ZXIC_UINT32 dir_wr_pful; +}DPP_SE_SMMU1_CFG_WR_ARBI_PFUL2_T; + +typedef struct dpp_se_smmu1_etm_tbl_cfg_t +{ + ZXIC_UINT32 etm_baddr; +}DPP_SE_SMMU1_ETM_TBL_CFG_T; + +typedef struct dpp_se_smmu1_cfg_cash_addr_pful_t +{ + ZXIC_UINT32 cfg_cash_addr_pful; +}DPP_SE_SMMU1_CFG_CASH_ADDR_PFUL_T; + +typedef struct dpp_se_smmu1_ctrl_rfifo_cfg_t +{ + ZXIC_UINT32 brst_fwft_fifo_prog_empty_assert; + ZXIC_UINT32 brst_fwft_fifo_prog_empty_negate; + ZXIC_UINT32 brst_fwft_fifo_prog_full_assert; + ZXIC_UINT32 brst_fwft_fifo_prog_full_negate; +}DPP_SE_SMMU1_CTRL_RFIFO_CFG_T; + +typedef struct dpp_se_smmu1_cache_req_fifo_cfg_t +{ + ZXIC_UINT32 srch_fifo_pfull_assert; + ZXIC_UINT32 srch_fifo_pfull_negate; +}DPP_SE_SMMU1_CACHE_REQ_FIFO_CFG_T; + +typedef struct dpp_se_smmu1_ddr_wdat1_t +{ + ZXIC_UINT32 ddr_wdat1; +}DPP_SE_SMMU1_DDR_WDAT1_T; + +typedef struct dpp_se_smmu1_ddr_wdat2_t +{ + ZXIC_UINT32 ddr_wdat2; +}DPP_SE_SMMU1_DDR_WDAT2_T; + +typedef struct dpp_se_smmu1_ddr_wdat3_t +{ + ZXIC_UINT32 ddr_wdat3; +}DPP_SE_SMMU1_DDR_WDAT3_T; + +typedef struct dpp_se_smmu1_ddr_wdat4_t +{ + ZXIC_UINT32 ddr_wdat4; +}DPP_SE_SMMU1_DDR_WDAT4_T; + +typedef struct dpp_se_smmu1_ddr_wdat5_t +{ + ZXIC_UINT32 ddr_wdat5; +}DPP_SE_SMMU1_DDR_WDAT5_T; + +typedef struct dpp_se_smmu1_ddr_wdat6_t +{ + ZXIC_UINT32 ddr_wdat6; +}DPP_SE_SMMU1_DDR_WDAT6_T; + +typedef struct dpp_se_smmu1_ddr_wdat7_t +{ + ZXIC_UINT32 ddr_wdat7; +}DPP_SE_SMMU1_DDR_WDAT7_T; + +typedef struct dpp_se_smmu1_ddr_wdat8_t +{ + ZXIC_UINT32 ddr_wdat8; +}DPP_SE_SMMU1_DDR_WDAT8_T; + +typedef struct dpp_se_smmu1_ddr_wdat9_t +{ + ZXIC_UINT32 ddr_wdat9; +}DPP_SE_SMMU1_DDR_WDAT9_T; + +typedef struct dpp_se_smmu1_ddr_wdat10_t +{ + ZXIC_UINT32 ddr_wdat10; +}DPP_SE_SMMU1_DDR_WDAT10_T; + +typedef struct dpp_se_smmu1_ddr_wdat11_t +{ + ZXIC_UINT32 ddr_wdat11; +}DPP_SE_SMMU1_DDR_WDAT11_T; + +typedef struct dpp_se_smmu1_ddr_wdat12_t +{ + ZXIC_UINT32 ddr_wdat12; +}DPP_SE_SMMU1_DDR_WDAT12_T; + +typedef struct dpp_se_smmu1_ddr_wdat13_t +{ + ZXIC_UINT32 ddr_wdat13; +}DPP_SE_SMMU1_DDR_WDAT13_T; + +typedef struct dpp_se_smmu1_ddr_wdat14_t +{ + ZXIC_UINT32 ddr_wdat14; +}DPP_SE_SMMU1_DDR_WDAT14_T; + +typedef struct dpp_se_smmu1_ddr_wdat15_t +{ + ZXIC_UINT32 ddr_wdat15; +}DPP_SE_SMMU1_DDR_WDAT15_T; + +typedef struct dpp_se_smmu1_cnt_stat_cache_en_t +{ + ZXIC_UINT32 cnt_stat_cache_en; +}DPP_SE_SMMU1_CNT_STAT_CACHE_EN_T; + +typedef struct dpp_se_smmu1_cnt_stat_cache_clr_t +{ + ZXIC_UINT32 cnt_stat_cache_clr; +}DPP_SE_SMMU1_CNT_STAT_CACHE_CLR_T; + +typedef struct dpp_se_smmu1_cnt_stat_cache_req_63_32_t +{ + ZXIC_UINT32 cnt_stat_cache_req_63_32; +}DPP_SE_SMMU1_CNT_STAT_CACHE_REQ_63_32_T; + +typedef struct dpp_se_smmu1_cnt_stat_cache_req_31_0_t +{ + ZXIC_UINT32 cnt_stat_cache_req_31_0; +}DPP_SE_SMMU1_CNT_STAT_CACHE_REQ_31_0_T; + +typedef struct dpp_se_smmu1_cnt_stat_cache_hit_63_32_t +{ + ZXIC_UINT32 cnt_stat_cache_hit_63_32; +}DPP_SE_SMMU1_CNT_STAT_CACHE_HIT_63_32_T; + +typedef struct dpp_se_smmu1_cnt_stat_cache_hit_31_0_t +{ + ZXIC_UINT32 cnt_stat_cache_hit_31_0; +}DPP_SE_SMMU1_CNT_STAT_CACHE_HIT_31_0_T; + +typedef struct dpp_se_smmu1_ddr_cmd0_t +{ + ZXIC_UINT32 ecc_en; + ZXIC_UINT32 rw_len; + ZXIC_UINT32 baddr; +}DPP_SE_SMMU1_DDR_CMD0_T; + +typedef struct dpp_se_smmu1_info_addr_t +{ + ZXIC_UINT32 info_addr; +}DPP_SE_SMMU1_INFO_ADDR_T; + +typedef struct dpp_se_smmu1_ddr_cmd1_t +{ + ZXIC_UINT32 rw_flag; + ZXIC_UINT32 rw_addr; +}DPP_SE_SMMU1_DDR_CMD1_T; + +typedef struct dpp_se_smmu1_clr_start_addr_t +{ + ZXIC_UINT32 clr_start_addr; +}DPP_SE_SMMU1_CLR_START_ADDR_T; + +typedef struct dpp_se_smmu1_clr_end_addr_t +{ + ZXIC_UINT32 clr_end_addr; +}DPP_SE_SMMU1_CLR_END_ADDR_T; + +typedef struct dpp_se_smmu1_clr_tbl_en_t +{ + ZXIC_UINT32 cfg_init_en; + ZXIC_UINT32 clr_tbl_en; +}DPP_SE_SMMU1_CLR_TBL_EN_T; + +typedef struct dpp_se_smmu1_debug_cnt_mode_t +{ + ZXIC_UINT32 cnt_rd_mode; + ZXIC_UINT32 cnt_overflow_mode; +}DPP_SE_SMMU1_DEBUG_CNT_MODE_T; + +typedef struct dpp_se_smmu1_init_done_t +{ + ZXIC_UINT32 cache_init_done; + ZXIC_UINT32 clr_done; + ZXIC_UINT32 init_ok; +}DPP_SE_SMMU1_INIT_DONE_T; + +typedef struct dpp_se_smmu1_cpu_rsp_rd_done_t +{ + ZXIC_UINT32 cpu_rsp_rd_done; +}DPP_SE_SMMU1_CPU_RSP_RD_DONE_T; + +typedef struct dpp_se_smmu1_ksch_oam_sp_en_t +{ + ZXIC_UINT32 ksch_oam_sp_en; +}DPP_SE_SMMU1_KSCH_OAM_SP_EN_T; + +typedef struct dpp_se_smmu1_cfg_cache_en_t +{ + ZXIC_UINT32 cfg_cache_en; +}DPP_SE_SMMU1_CFG_CACHE_EN_T; + +typedef struct dpp_se_smmu1_cache_age_en_t +{ + ZXIC_UINT32 cache_age_en; +}DPP_SE_SMMU1_CACHE_AGE_EN_T; + +typedef struct dpp_se_smmu1_cpu_rdat0_t +{ + ZXIC_UINT32 cpu_rdat0; +}DPP_SE_SMMU1_CPU_RDAT0_T; + +typedef struct dpp_se_smmu1_cpu_rdat1_t +{ + ZXIC_UINT32 cpu_rdat1; +}DPP_SE_SMMU1_CPU_RDAT1_T; + +typedef struct dpp_se_smmu1_cpu_rdat2_t +{ + ZXIC_UINT32 cpu_rdat2; +}DPP_SE_SMMU1_CPU_RDAT2_T; + +typedef struct dpp_se_smmu1_cpu_rdat3_t +{ + ZXIC_UINT32 cpu_rdat3; +}DPP_SE_SMMU1_CPU_RDAT3_T; + +typedef struct dpp_se_smmu1_cpu_rdat4_t +{ + ZXIC_UINT32 cpu_rdat4; +}DPP_SE_SMMU1_CPU_RDAT4_T; + +typedef struct dpp_se_smmu1_cpu_rdat5_t +{ + ZXIC_UINT32 cpu_rdat5; +}DPP_SE_SMMU1_CPU_RDAT5_T; + +typedef struct dpp_se_smmu1_cpu_rdat6_t +{ + ZXIC_UINT32 cpu_rdat6; +}DPP_SE_SMMU1_CPU_RDAT6_T; + +typedef struct dpp_se_smmu1_cpu_rdat7_t +{ + ZXIC_UINT32 cpu_rdat7; +}DPP_SE_SMMU1_CPU_RDAT7_T; + +typedef struct dpp_se_smmu1_cpu_rdat8_t +{ + ZXIC_UINT32 cpu_rdat8; +}DPP_SE_SMMU1_CPU_RDAT8_T; + +typedef struct dpp_se_smmu1_cpu_rdat9_t +{ + ZXIC_UINT32 cpu_rdat9; +}DPP_SE_SMMU1_CPU_RDAT9_T; + +typedef struct dpp_se_smmu1_cpu_rdat10_t +{ + ZXIC_UINT32 cpu_rdat10; +}DPP_SE_SMMU1_CPU_RDAT10_T; + +typedef struct dpp_se_smmu1_cpu_rdat11_t +{ + ZXIC_UINT32 cpu_rdat11; +}DPP_SE_SMMU1_CPU_RDAT11_T; + +typedef struct dpp_se_smmu1_cpu_rdat12_t +{ + ZXIC_UINT32 cpu_rdat12; +}DPP_SE_SMMU1_CPU_RDAT12_T; + +typedef struct dpp_se_smmu1_cpu_rdat13_t +{ + ZXIC_UINT32 cpu_rdat13; +}DPP_SE_SMMU1_CPU_RDAT13_T; + +typedef struct dpp_se_smmu1_cpu_rdat14_t +{ + ZXIC_UINT32 cpu_rdat14; +}DPP_SE_SMMU1_CPU_RDAT14_T; + +typedef struct dpp_se_smmu1_cpu_rdat15_t +{ + ZXIC_UINT32 cpu_rdat15; +}DPP_SE_SMMU1_CPU_RDAT15_T; + +typedef struct dpp_se_smmu1_ctrl_cpu_rd_rdy_t +{ + ZXIC_UINT32 ctrl_cpu_rd_rdy; +}DPP_SE_SMMU1_CTRL_CPU_RD_RDY_T; + +typedef struct dpp_se_smmu1_cpu_warbi_rdy_cfg_t +{ + ZXIC_UINT32 cpu_warbi_rdy_cfg; +}DPP_SE_SMMU1_CPU_WARBI_RDY_CFG_T; + +typedef struct dpp_se_smmu1_dir_arbi_cpu_rpful_t +{ + ZXIC_UINT32 smmu1_cfg_rpful; + ZXIC_UINT32 smmu1_cfg_wpful; +}DPP_SE_SMMU1_DIR_ARBI_CPU_RPFUL_T; + +typedef struct dpp_se_smmu1_dir_arbi_wpful_t +{ + ZXIC_UINT32 smmu1_ser_wdir_pful; + ZXIC_UINT32 smmu1_cfg_wdir_pful; +}DPP_SE_SMMU1_DIR_ARBI_WPFUL_T; + +typedef struct dpp_se_smmu1_cfg_wr_arbi_pful0_t +{ + ZXIC_UINT32 arbi_out_pful; + ZXIC_UINT32 cpu_wr_pful; +}DPP_SE_SMMU1_CFG_WR_ARBI_PFUL0_T; + +typedef struct dpp_se_smmu1_cfg_wr_arbi_pful1_t +{ + ZXIC_UINT32 tm_wr_pful; + ZXIC_UINT32 stat_wr_pful; +}DPP_SE_SMMU1_CFG_WR_ARBI_PFUL1_T; + +typedef struct dpp_se_smmu1_smmu1_wdone_pful_cfg_t +{ + ZXIC_UINT32 smmu1_wdone_pful_cfg; +}DPP_SE_SMMU1_SMMU1_WDONE_PFUL_CFG_T; + +typedef struct dpp_se_smmu1_stat_rate_cfg_cnt_t +{ + ZXIC_UINT32 stat_rate_cfg_cnt; +}DPP_SE_SMMU1_STAT_RATE_CFG_CNT_T; + +typedef struct dpp_se_smmu1_ftm_rate_cfg_cnt_t +{ + ZXIC_UINT32 ftm_rate_cfg_cnt; +}DPP_SE_SMMU1_FTM_RATE_CFG_CNT_T; + +typedef struct dpp_se_smmu1_etm_rate_cfg_cnt_t +{ + ZXIC_UINT32 etm_rate_cfg_cnt; +}DPP_SE_SMMU1_ETM_RATE_CFG_CNT_T; + +typedef struct dpp_se_smmu1_dir_rate_cfg_cnt_t +{ + ZXIC_UINT32 dir_rate_cfg_cnt; +}DPP_SE_SMMU1_DIR_RATE_CFG_CNT_T; + +typedef struct dpp_se_smmu1_hash_rate_cfg_cnt_t +{ + ZXIC_UINT32 hash_rate_cfg_cnt; +}DPP_SE_SMMU1_HASH_RATE_CFG_CNT_T; + +typedef struct dpp_se_smmu1_ftm_tbl_cfg_t +{ + ZXIC_UINT32 ftm_baddr; +}DPP_SE_SMMU1_FTM_TBL_CFG_T; + +typedef struct dpp_se_smmu1_lpm_v4_as_tbl_cfg_t +{ + ZXIC_UINT32 lpm_v4_as_rsp_len; + ZXIC_UINT32 lpm_v4_as_ecc_en; + ZXIC_UINT32 lpm_v4_as_baddr; +}DPP_SE_SMMU1_LPM_V4_AS_TBL_CFG_T; + +typedef struct dpp_se_smmu1_lpm_v4_tbl_cfg_t +{ + ZXIC_UINT32 lpm_v4_len; + ZXIC_UINT32 lpm_v4_ecc_en; + ZXIC_UINT32 lpm_v4_baddr; +}DPP_SE_SMMU1_LPM_V4_TBL_CFG_T; + +typedef struct dpp_se_smmu1_lpm_v6_tbl_cfg_t +{ + ZXIC_UINT32 lpm_v6_len; + ZXIC_UINT32 lpm_v6_ecc_en; + ZXIC_UINT32 lpm_v6_baddr; +}DPP_SE_SMMU1_LPM_V6_TBL_CFG_T; + +typedef struct dpp_se_smmu1_lpm_v6_as_tbl_cfg_t +{ + ZXIC_UINT32 lpm_v6_as_rsp_len; + ZXIC_UINT32 lpm_v6_as_ecc_en; + ZXIC_UINT32 lpm_v6_as_baddr; +}DPP_SE_SMMU1_LPM_V6_AS_TBL_CFG_T; + +typedef struct dpp_se_smmu1_dma_tbl_cfg_t +{ + ZXIC_UINT32 dma_baddr; +}DPP_SE_SMMU1_DMA_TBL_CFG_T; + +typedef struct dpp_se_smmu1_oam_tbl_cfg_t +{ + ZXIC_UINT32 oam_baddr; +}DPP_SE_SMMU1_OAM_TBL_CFG_T; + +typedef struct dpp_se_smmu1_ctrl_rpar_cpu_pful_t +{ + ZXIC_UINT32 ctrl_rpar_cpu_pful; +}DPP_SE_SMMU1_CTRL_RPAR_CPU_PFUL_T; + +typedef struct dpp_se_smmu1_cfg_ksch_dir_pful_t +{ + ZXIC_UINT32 cfg_ksch_dir_pful; +}DPP_SE_SMMU1_CFG_KSCH_DIR_PFUL_T; + +typedef struct dpp_se_smmu1_cfg_ksch_hash_pful_t +{ + ZXIC_UINT32 cfg_ksch_hash_pful; +}DPP_SE_SMMU1_CFG_KSCH_HASH_PFUL_T; + +typedef struct dpp_se_smmu1_cfg_ksch_lpm_pful_t +{ + ZXIC_UINT32 cfg_ksch_lpm_pful; +}DPP_SE_SMMU1_CFG_KSCH_LPM_PFUL_T; + +typedef struct dpp_se_smmu1_cfg_ksch_lpm_as_pful_t +{ + ZXIC_UINT32 cfg_ksch_lpm_as_pful; +}DPP_SE_SMMU1_CFG_KSCH_LPM_AS_PFUL_T; + +typedef struct dpp_se_smmu1_cfg_ksch_stat_pful_t +{ + ZXIC_UINT32 cfg_ksch_stat_pful; +}DPP_SE_SMMU1_CFG_KSCH_STAT_PFUL_T; + +typedef struct dpp_se_smmu1_cfg_ksch_tm_pful_t +{ + ZXIC_UINT32 cfg_ksch_tm_pful; +}DPP_SE_SMMU1_CFG_KSCH_TM_PFUL_T; + +typedef struct dpp_se_smmu1_cfg_ksch_oam_pful_t +{ + ZXIC_UINT32 cfg_ksch_oam_pful; +}DPP_SE_SMMU1_CFG_KSCH_OAM_PFUL_T; + +typedef struct dpp_se_smmu1_cfg_ksch_dma_pful_t +{ + ZXIC_UINT32 cfg_ksch_dma_pful; +}DPP_SE_SMMU1_CFG_KSCH_DMA_PFUL_T; + +typedef struct dpp_se_smmu1_ctrl_wfifo_cfg_t +{ + ZXIC_UINT32 ctrl_wfifo_cfg; +}DPP_SE_SMMU1_CTRL_WFIFO_CFG_T; + +typedef struct dpp_se_smmu1_rsch_hash_ptr_cfg_t +{ + ZXIC_UINT32 rsch_hash_ptr_cfg; +}DPP_SE_SMMU1_RSCH_HASH_PTR_CFG_T; + +typedef struct dpp_se_smmu1_rsch_lpm_ptr_cfg_t +{ + ZXIC_UINT32 rsch_lpm_ptr_cfg; +}DPP_SE_SMMU1_RSCH_LPM_PTR_CFG_T; + +typedef struct dpp_se_smmu1_rsch_lpm_as_ptr_cfg_t +{ + ZXIC_UINT32 rsch_lpm_as_ptr_cfg; +}DPP_SE_SMMU1_RSCH_LPM_AS_PTR_CFG_T; + +typedef struct dpp_se_smmu1_rsch_stat_ptr_cfg_t +{ + ZXIC_UINT32 rsch_stat_ptr_cfg; +}DPP_SE_SMMU1_RSCH_STAT_PTR_CFG_T; + +typedef struct dpp_se_smmu1_rsch_oam_ptr_cfg_t +{ + ZXIC_UINT32 rsch_oam_ptr_cfg; +}DPP_SE_SMMU1_RSCH_OAM_PTR_CFG_T; + +typedef struct dpp_se_smmu1_rschd_fifo_pept_cfg_t +{ + ZXIC_UINT32 rschd_fifo_pept_cfg; +}DPP_SE_SMMU1_RSCHD_FIFO_PEPT_CFG_T; + +typedef struct dpp_se_smmu1_dir_fifo_pful_cfg_t +{ + ZXIC_UINT32 dir_fifo_pful_cfg; +}DPP_SE_SMMU1_DIR_FIFO_PFUL_CFG_T; + +typedef struct dpp_se_smmu1_hash_fifo_pful_cfg_t +{ + ZXIC_UINT32 hash_fifo_pful_cfg; +}DPP_SE_SMMU1_HASH_FIFO_PFUL_CFG_T; + +typedef struct dpp_se_smmu1_lpm_fifo_pful_cfg_t +{ + ZXIC_UINT32 lpm_fifo_pful_cfg; +}DPP_SE_SMMU1_LPM_FIFO_PFUL_CFG_T; + +typedef struct dpp_se_smmu1_lpm_as_fifo_pful_cfg_t +{ + ZXIC_UINT32 lpm_as_fifo_pful_cfg; +}DPP_SE_SMMU1_LPM_AS_FIFO_PFUL_CFG_T; + +typedef struct dpp_se_smmu1_stat_fifo_pful_cfg_t +{ + ZXIC_UINT32 stat_fifo_pful_cfg; +}DPP_SE_SMMU1_STAT_FIFO_PFUL_CFG_T; + +typedef struct dpp_se_smmu1_ftm_fifo_pful_cfg_t +{ + ZXIC_UINT32 ftm_fifo_pful_cfg; +}DPP_SE_SMMU1_FTM_FIFO_PFUL_CFG_T; + +typedef struct dpp_se_smmu1_etm_fifo_pful_cfg_t +{ + ZXIC_UINT32 etm_fifo_pful_cfg; +}DPP_SE_SMMU1_ETM_FIFO_PFUL_CFG_T; + +typedef struct dpp_se_smmu1_oam_fifo_pful_cfg_t +{ + ZXIC_UINT32 oam_fifo_pful_cfg; +}DPP_SE_SMMU1_OAM_FIFO_PFUL_CFG_T; + +typedef struct dpp_se_smmu1_dma_fifo_pful_cfg_t +{ + ZXIC_UINT32 dma_fifo_pful_cfg; +}DPP_SE_SMMU1_DMA_FIFO_PFUL_CFG_T; + +typedef struct dpp_se_smmu1_cache_rsp_rr_fifo_cfg_t +{ + ZXIC_UINT32 rr_pfull_assert0; + ZXIC_UINT32 rr_pfull_negate0; +}DPP_SE_SMMU1_CACHE_RSP_RR_FIFO_CFG_T; + +typedef struct dpp_se_smmu1_ddr_rsp_rr_fifo_cfg_t +{ + ZXIC_UINT32 rr_pfull_assert1; + ZXIC_UINT32 rr_pfull_negate1; +}DPP_SE_SMMU1_DDR_RSP_RR_FIFO_CFG_T; + +typedef struct dpp_se_smmu1_cpu_cahce_fifo_cfg_t +{ + ZXIC_UINT32 smmu1_cahce_fwft_fifo_pfull_assert; + ZXIC_UINT32 smmu1_cahce_fwft_fifo_pfull_negate; +}DPP_SE_SMMU1_CPU_CAHCE_FIFO_CFG_T; + +typedef struct dpp_se_smmu1_cache_rsp_fifo_cfg_t +{ + ZXIC_UINT32 rschd_fifo_pfull_assert; + ZXIC_UINT32 rschd_fifo_pfull_negate; +}DPP_SE_SMMU1_CACHE_RSP_FIFO_CFG_T; + +typedef struct dpp_se_smmu1_test_state_t +{ + ZXIC_UINT32 test_state; +}DPP_SE_SMMU1_TEST_STATE_T; + +typedef struct dpp_se_smmu1_cache_fifo_ept_t +{ + ZXIC_UINT32 cache_fifo_ept; +}DPP_SE_SMMU1_CACHE_FIFO_EPT_T; + +typedef struct dpp_se_smmu1_rr_fifo_ept_t +{ + ZXIC_UINT32 rr_fifo_ept; +}DPP_SE_SMMU1_RR_FIFO_EPT_T; + +typedef struct dpp_se_smmu1_wr_fifo_ept_t +{ + ZXIC_UINT32 dir_arbi_ept; +}DPP_SE_SMMU1_WR_FIFO_EPT_T; + +typedef struct dpp_se_smmu1_wdone_fifo_ept_t +{ + ZXIC_UINT32 wdone_fifo_ept; +}DPP_SE_SMMU1_WDONE_FIFO_EPT_T; + +typedef struct dpp_se_smmu1_kschd_fifo_ept0_t +{ + ZXIC_UINT32 kschd_fifo_ept0; +}DPP_SE_SMMU1_KSCHD_FIFO_EPT0_T; + +typedef struct dpp_se_smmu1_cash_fifo_ept_t +{ + ZXIC_UINT32 cash_fifo_ept; +}DPP_SE_SMMU1_CASH_FIFO_EPT_T; + +typedef struct dpp_se_smmu1_ctrl_fifo_ept_t +{ + ZXIC_UINT32 ctrl_fifo_ept; +}DPP_SE_SMMU1_CTRL_FIFO_EPT_T; + +typedef struct dpp_se_smmu1_smmu1_rschd_ept3_t +{ + ZXIC_UINT32 rschd_fifo_ept3; +}DPP_SE_SMMU1_SMMU1_RSCHD_EPT3_T; + +typedef struct dpp_se_smmu1_smmu1_rschd_ept2_t +{ + ZXIC_UINT32 rschd_fifo_ept2; +}DPP_SE_SMMU1_SMMU1_RSCHD_EPT2_T; + +typedef struct dpp_se_smmu1_smmu1_rschd_ept1_t +{ + ZXIC_UINT32 rschd_fifo_ept1; +}DPP_SE_SMMU1_SMMU1_RSCHD_EPT1_T; + +typedef struct dpp_se_smmu1_smmu1_rschd_ept0_t +{ + ZXIC_UINT32 rschd_fifo_ept0; +}DPP_SE_SMMU1_SMMU1_RSCHD_EPT0_T; + +typedef struct dpp_se_smmu1_cash0_ecc_err_addr_t +{ + ZXIC_UINT32 cash0_ecc_err_addr; +}DPP_SE_SMMU1_CASH0_ECC_ERR_ADDR_T; + +typedef struct dpp_se_smmu1_arbi_cpu_wr_rdy_t +{ + ZXIC_UINT32 arbi_cpu_wr_rdy; +}DPP_SE_SMMU1_ARBI_CPU_WR_RDY_T; + +typedef struct dpp_se_smmu1_smmu1_int_0_en_t +{ + ZXIC_UINT32 smmu1_int_0_en; +}DPP_SE_SMMU1_SMMU1_INT_0_EN_T; + +typedef struct dpp_se_smmu1_smmu1_int_0_mask_t +{ + ZXIC_UINT32 smmu1_int_0_mask; +}DPP_SE_SMMU1_SMMU1_INT_0_MASK_T; + +typedef struct dpp_se_smmu1_smmu1_int_1_en_t +{ + ZXIC_UINT32 smmu1_int_1_en; +}DPP_SE_SMMU1_SMMU1_INT_1_EN_T; + +typedef struct dpp_se_smmu1_smmu1_int_1_mask_t +{ + ZXIC_UINT32 smmu1_int_1_mask; +}DPP_SE_SMMU1_SMMU1_INT_1_MASK_T; + +typedef struct dpp_se_smmu1_smmu1_int_2_en_t +{ + ZXIC_UINT32 smmu1_int_2_en; +}DPP_SE_SMMU1_SMMU1_INT_2_EN_T; + +typedef struct dpp_se_smmu1_smmu1_int_2_mask_t +{ + ZXIC_UINT32 smmu1_int_2_mask; +}DPP_SE_SMMU1_SMMU1_INT_2_MASK_T; + +typedef struct dpp_se_smmu1_smmu1_int_3_en_t +{ + ZXIC_UINT32 smmu1_int_3_en; +}DPP_SE_SMMU1_SMMU1_INT_3_EN_T; + +typedef struct dpp_se_smmu1_smmu1_int_3_mask_t +{ + ZXIC_UINT32 smmu1_int_3_mask; +}DPP_SE_SMMU1_SMMU1_INT_3_MASK_T; + +typedef struct dpp_se_smmu1_smmu1_int_0_status_t +{ + ZXIC_UINT32 smmu1_int_0_status; +}DPP_SE_SMMU1_SMMU1_INT_0_STATUS_T; + +typedef struct dpp_se_smmu1_smmu1_int_1_status_t +{ + ZXIC_UINT32 smmu1_int_1_status; +}DPP_SE_SMMU1_SMMU1_INT_1_STATUS_T; + +typedef struct dpp_se_smmu1_smmu1_int_2_status_t +{ + ZXIC_UINT32 smmu1_int_2_status; +}DPP_SE_SMMU1_SMMU1_INT_2_STATUS_T; + +typedef struct dpp_se_smmu1_smmu1_int_3_status_t +{ + ZXIC_UINT32 smmu1_int_3_status; +}DPP_SE_SMMU1_SMMU1_INT_3_STATUS_T; + +typedef struct dpp_se_smmu1_smmu1_int_status_t +{ + ZXIC_UINT32 smmu1_int_status; +}DPP_SE_SMMU1_SMMU1_INT_STATUS_T; + +typedef struct dpp_se_smmu1_ctrl_to_cash7_0_fc_cnt_t +{ + ZXIC_UINT32 ctrl_to_cash7_0_fc_cnt; +}DPP_SE_SMMU1_CTRL_TO_CASH7_0_FC_CNT_T; + +typedef struct dpp_se_smmu1_cash7_0_to_ctrl_req_cnt_t +{ + ZXIC_UINT32 cash7_0_to_ctrl_req_cnt; +}DPP_SE_SMMU1_CASH7_0_TO_CTRL_REQ_CNT_T; + +typedef struct dpp_se_smmu1_rschd_to_cache7_fc_cnt_t +{ + ZXIC_UINT32 rschd_to_cache7_fc_cnt; +}DPP_SE_SMMU1_RSCHD_TO_CACHE7_FC_CNT_T; + +typedef struct dpp_se_smmu1_cash7_to_cache_rsp_cnt_t +{ + ZXIC_UINT32 cash7_to_cache_rsp_cnt; +}DPP_SE_SMMU1_CASH7_TO_CACHE_RSP_CNT_T; + +typedef struct dpp_se_smmu1_cash7_to_ctrl_fc_cnt_t +{ + ZXIC_UINT32 cash7_to_ctrl_fc_cnt; +}DPP_SE_SMMU1_CASH7_TO_CTRL_FC_CNT_T; + +typedef struct dpp_se_smmu1_ctrl_to_cash7_0_rsp_cnt_t +{ + ZXIC_UINT32 ctrl_to_cash7_0_rsp_cnt; +}DPP_SE_SMMU1_CTRL_TO_CASH7_0_RSP_CNT_T; + +typedef struct dpp_se_smmu1_kschd_to_cache7_0_req_cnt_t +{ + ZXIC_UINT32 kschd_to_cache7_0_req_cnt; +}DPP_SE_SMMU1_KSCHD_TO_CACHE7_0_REQ_CNT_T; + +typedef struct dpp_se_smmu1_cache7_0_to_kschd_fc_cnt_t +{ + ZXIC_UINT32 cache7_0_to_kschd_fc_cnt; +}DPP_SE_SMMU1_CACHE7_0_TO_KSCHD_FC_CNT_T; + +typedef struct dpp_se_smmu1_dma_to_smmu1_rd_req_cnt_t +{ + ZXIC_UINT32 dma_to_smmu1_rd_req_cnt; +}DPP_SE_SMMU1_DMA_TO_SMMU1_RD_REQ_CNT_T; + +typedef struct dpp_se_smmu1_oam_to_kschd_req_cnt_t +{ + ZXIC_UINT32 oam_to_kschd_req_cnt; +}DPP_SE_SMMU1_OAM_TO_KSCHD_REQ_CNT_T; + +typedef struct dpp_se_smmu1_oam_rr_state_rsp_cnt_t +{ + ZXIC_UINT32 oam_rr_state_rsp_cnt; +}DPP_SE_SMMU1_OAM_RR_STATE_RSP_CNT_T; + +typedef struct dpp_se_smmu1_oam_clash_info_cnt_t +{ + ZXIC_UINT32 oam_clash_info_cnt; +}DPP_SE_SMMU1_OAM_CLASH_INFO_CNT_T; + +typedef struct dpp_se_smmu1_oam_to_rr_req_cnt_t +{ + ZXIC_UINT32 oam_to_rr_req_cnt; +}DPP_SE_SMMU1_OAM_TO_RR_REQ_CNT_T; + +typedef struct dpp_se_smmu1_lpm_as_to_kschd_req_cnt_t +{ + ZXIC_UINT32 lpm_as_to_kschd_req_cnt; +}DPP_SE_SMMU1_LPM_AS_TO_KSCHD_REQ_CNT_T; + +typedef struct dpp_se_smmu1_lpm_as_rr_state_rsp_cnt_t +{ + ZXIC_UINT32 lpm_as_rr_state_rsp_cnt; +}DPP_SE_SMMU1_LPM_AS_RR_STATE_RSP_CNT_T; + +typedef struct dpp_se_smmu1_lpm_as_clash_info_cnt_t +{ + ZXIC_UINT32 lpm_as_clash_info_cnt; +}DPP_SE_SMMU1_LPM_AS_CLASH_INFO_CNT_T; + +typedef struct dpp_se_smmu1_lpm_as_to_rr_req_cnt_t +{ + ZXIC_UINT32 lpm_as_to_rr_req_cnt; +}DPP_SE_SMMU1_LPM_AS_TO_RR_REQ_CNT_T; + +typedef struct dpp_se_smmu1_lpm_to_kschd_req_cnt_t +{ + ZXIC_UINT32 lpm_to_kschd_req_cnt; +}DPP_SE_SMMU1_LPM_TO_KSCHD_REQ_CNT_T; + +typedef struct dpp_se_smmu1_lpm_rr_state_rsp_cnt_t +{ + ZXIC_UINT32 lpm_rr_state_rsp_cnt; +}DPP_SE_SMMU1_LPM_RR_STATE_RSP_CNT_T; + +typedef struct dpp_se_smmu1_lpm_clash_info_cnt_t +{ + ZXIC_UINT32 lpm_clash_info_cnt; +}DPP_SE_SMMU1_LPM_CLASH_INFO_CNT_T; + +typedef struct dpp_se_smmu1_lpm_to_rr_req_cnt_t +{ + ZXIC_UINT32 lpm_to_rr_req_cnt; +}DPP_SE_SMMU1_LPM_TO_RR_REQ_CNT_T; + +typedef struct dpp_se_smmu1_hash3_0_to_kschd_req_cnt_t +{ + ZXIC_UINT32 hash3_0_to_kschd_req_cnt; +}DPP_SE_SMMU1_HASH3_0_TO_KSCHD_REQ_CNT_T; + +typedef struct dpp_se_smmu1_hash3_0_rr_state_rsp_cnt_t +{ + ZXIC_UINT32 hash3_0_rr_state_rsp_cnt; +}DPP_SE_SMMU1_HASH3_0_RR_STATE_RSP_CNT_T; + +typedef struct dpp_se_smmu1_hash3_0_clash_info_cnt_t +{ + ZXIC_UINT32 hash3_0_clash_info_cnt; +}DPP_SE_SMMU1_HASH3_0_CLASH_INFO_CNT_T; + +typedef struct dpp_se_smmu1_hash3_0_to_rr_req_cnt_t +{ + ZXIC_UINT32 hash3_0_to_rr_req_cnt; +}DPP_SE_SMMU1_HASH3_0_TO_RR_REQ_CNT_T; + +typedef struct dpp_se_smmu1_dir3_0_to_kschd_req_cnt_t +{ + ZXIC_UINT32 dir3_0_to_kschd_req_cnt; +}DPP_SE_SMMU1_DIR3_0_TO_KSCHD_REQ_CNT_T; + +typedef struct dpp_se_smmu1_dir3_0_clash_info_cnt_t +{ + ZXIC_UINT32 dir3_0_clash_info_cnt; +}DPP_SE_SMMU1_DIR3_0_CLASH_INFO_CNT_T; + +typedef struct dpp_se_smmu1_dir_tbl_wr_req_cnt_t +{ + ZXIC_UINT32 dir_tbl_wr_req_cnt; +}DPP_SE_SMMU1_DIR_TBL_WR_REQ_CNT_T; + +typedef struct dpp_se_smmu1_warbi_to_dir_tbl_warbi_fc_cnt_t +{ + ZXIC_UINT32 warbi_to_dir_tbl_warbi_fc_cnt; +}DPP_SE_SMMU1_WARBI_TO_DIR_TBL_WARBI_FC_CNT_T; + +typedef struct dpp_se_smmu1_dir3_0_to_bank_rr_req_cnt_t +{ + ZXIC_UINT32 dir3_0_to_bank_rr_req_cnt; +}DPP_SE_SMMU1_DIR3_0_TO_BANK_RR_REQ_CNT_T; + +typedef struct dpp_se_smmu1_kschd_to_dir3_0_fc_cnt_t +{ + ZXIC_UINT32 kschd_to_dir3_0_fc_cnt; +}DPP_SE_SMMU1_KSCHD_TO_DIR3_0_FC_CNT_T; + +typedef struct dpp_se_smmu1_dir3_0_rr_state_rsp_cnt_t +{ + ZXIC_UINT32 dir3_0_rr_state_rsp_cnt; +}DPP_SE_SMMU1_DIR3_0_RR_STATE_RSP_CNT_T; + +typedef struct dpp_se_smmu1_wr_done_to_warbi_fc_cnt_t +{ + ZXIC_UINT32 wr_done_to_warbi_fc_cnt; +}DPP_SE_SMMU1_WR_DONE_TO_WARBI_FC_CNT_T; + +typedef struct dpp_se_smmu1_wr_done_ptr_req_cnt_t +{ + ZXIC_UINT32 wr_done_ptr_req_cnt; +}DPP_SE_SMMU1_WR_DONE_PTR_REQ_CNT_T; + +typedef struct dpp_se_smmu1_ctrl7_0_to_warbi_fc_cnt_t +{ + ZXIC_UINT32 ctrl7_0_to_warbi_fc_cnt; +}DPP_SE_SMMU1_CTRL7_0_TO_WARBI_FC_CNT_T; + +typedef struct dpp_se_smmu1_warbi_to_ctrl7_0_wr_req_cnt_t +{ + ZXIC_UINT32 warbi_to_ctrl7_0_wr_req_cnt; +}DPP_SE_SMMU1_WARBI_TO_CTRL7_0_WR_REQ_CNT_T; + +typedef struct dpp_se_smmu1_warbi_to_cash7_0_wr_req_cnt_t +{ + ZXIC_UINT32 warbi_to_cash7_0_wr_req_cnt; +}DPP_SE_SMMU1_WARBI_TO_CASH7_0_WR_REQ_CNT_T; + +typedef struct dpp_se_smmu1_warbi_to_cpu_wr_fc_cnt_t +{ + ZXIC_UINT32 warbi_to_cpu_wr_fc_cnt; +}DPP_SE_SMMU1_WARBI_TO_CPU_WR_FC_CNT_T; + +typedef struct dpp_se_smmu1_cpu_wr_req_cnt_t +{ + ZXIC_UINT32 cpu_wr_req_cnt; +}DPP_SE_SMMU1_CPU_WR_REQ_CNT_T; + +typedef struct dpp_se_smmu1_ctrl7_0_to_cpu_rd_rsp_cnt_t +{ + ZXIC_UINT32 ctrl7_0_to_cpu_rd_rsp_cnt; +}DPP_SE_SMMU1_CTRL7_0_TO_CPU_RD_RSP_CNT_T; + +typedef struct dpp_se_smmu1_cpu_to_ctrl7_0_rd_req_cnt_t +{ + ZXIC_UINT32 cpu_to_ctrl7_0_rd_req_cnt; +}DPP_SE_SMMU1_CPU_TO_CTRL7_0_RD_REQ_CNT_T; + +typedef struct dpp_se_smmu1_cpu_rd_dir_tbl_rsp_cnt_t +{ + ZXIC_UINT32 cpu_rd_dir_tbl_rsp_cnt; +}DPP_SE_SMMU1_CPU_RD_DIR_TBL_RSP_CNT_T; + +typedef struct dpp_se_smmu1_cpu_to_dir_tbl_rd_wr_req_cnt_t +{ + ZXIC_UINT32 cpu_to_dir_tbl_rd_wr_req_cnt; +}DPP_SE_SMMU1_CPU_TO_DIR_TBL_RD_WR_REQ_CNT_T; + +typedef struct dpp_se_smmu1_smmu1_to_mmu_7_0_rsp_fc_cnt_t +{ + ZXIC_UINT32 smmu1_to_mmu_7_0_rsp_fc_cnt; +}DPP_SE_SMMU1_SMMU1_TO_MMU_7_0_RSP_FC_CNT_T; + +typedef struct dpp_se_smmu1_mmu_7_0_to_smmu1_rd_rsp_cnt_t +{ + ZXIC_UINT32 mmu_7_0_to_smmu1_rd_rsp_cnt; +}DPP_SE_SMMU1_MMU_7_0_TO_SMMU1_RD_RSP_CNT_T; + +typedef struct dpp_se_smmu1_mmu_7_0_to_smmu1_rd_fc_cnt_t +{ + ZXIC_UINT32 mmu_7_0_to_smmu1_rd_fc_cnt; +}DPP_SE_SMMU1_MMU_7_0_TO_SMMU1_RD_FC_CNT_T; + +typedef struct dpp_se_smmu1_smmu1_to_mmu_7_rd_req_cnt_t +{ + ZXIC_UINT32 smmu1_to_mmu_7_rd_req_cnt; +}DPP_SE_SMMU1_SMMU1_TO_MMU_7_RD_REQ_CNT_T; + +typedef struct dpp_se_smmu1_mmu_7_to_smmu1_wr_fc_cnt_t +{ + ZXIC_UINT32 mmu_7_to_smmu1_wr_fc_cnt; +}DPP_SE_SMMU1_MMU_7_TO_SMMU1_WR_FC_CNT_T; + +typedef struct dpp_se_smmu1_smmu1_to_mmu_7_0_wr_req_cnt_t +{ + ZXIC_UINT32 smmu1_to_mmu_7_0_wr_req_cnt; +}DPP_SE_SMMU1_SMMU1_TO_MMU_7_0_WR_REQ_CNT_T; + +typedef struct dpp_se_smmu1_se_to_smmu1_wr_rsp_fc_cnt_t +{ + ZXIC_UINT32 se_to_smmu1_wr_rsp_fc_cnt; +}DPP_SE_SMMU1_SE_TO_SMMU1_WR_RSP_FC_CNT_T; + +typedef struct dpp_se_smmu1_smmu1_to_se_wr_rsp_cnt_t +{ + ZXIC_UINT32 smmu1_to_se_wr_rsp_cnt; +}DPP_SE_SMMU1_SMMU1_TO_SE_WR_RSP_CNT_T; + +typedef struct dpp_se_smmu1_ddr7_0_wr_rsp_cnt_t +{ + ZXIC_UINT32 ddr7_0_wr_rsp_cnt; +}DPP_SE_SMMU1_DDR7_0_WR_RSP_CNT_T; + +typedef struct dpp_se_smmu1_smmu1_to_as_fc_cnt_t +{ + ZXIC_UINT32 smmu1_to_as_fc_cnt; +}DPP_SE_SMMU1_SMMU1_TO_AS_FC_CNT_T; + +typedef struct dpp_se_smmu1_as_to_smmu1_wr_req_cnt_t +{ + ZXIC_UINT32 as_to_smmu1_wr_req_cnt; +}DPP_SE_SMMU1_AS_TO_SMMU1_WR_REQ_CNT_T; + +typedef struct dpp_se_smmu1_smmu1_to_se_parser_fc_cnt_t +{ + ZXIC_UINT32 smmu1_to_se_parser_fc_cnt; +}DPP_SE_SMMU1_SMMU1_TO_SE_PARSER_FC_CNT_T; + +typedef struct dpp_se_smmu1_se_parser_to_smmu1_req_cnt_t +{ + ZXIC_UINT32 se_parser_to_smmu1_req_cnt; +}DPP_SE_SMMU1_SE_PARSER_TO_SMMU1_REQ_CNT_T; + +typedef struct dpp_se_smmu1_smmu1_to_etm_wr_fc_cnt_t +{ + ZXIC_UINT32 smmu1_to_etm_wr_fc_cnt; +}DPP_SE_SMMU1_SMMU1_TO_ETM_WR_FC_CNT_T; + +typedef struct dpp_se_smmu1_etm_wr_req_cnt_t +{ + ZXIC_UINT32 etm_wr_req_cnt; +}DPP_SE_SMMU1_ETM_WR_REQ_CNT_T; + +typedef struct dpp_se_smmu1_smmu1_to_ftm_wr_fc_cnt_t +{ + ZXIC_UINT32 smmu1_to_ftm_wr_fc_cnt; +}DPP_SE_SMMU1_SMMU1_TO_FTM_WR_FC_CNT_T; + +typedef struct dpp_se_smmu1_ftm_wr_req_cnt_t +{ + ZXIC_UINT32 ftm_wr_req_cnt; +}DPP_SE_SMMU1_FTM_WR_REQ_CNT_T; + +typedef struct dpp_se_smmu1_smmu1_to_state_wr_fc_cnt_t +{ + ZXIC_UINT32 smmu1_to_state_wr_fc_cnt; +}DPP_SE_SMMU1_SMMU1_TO_STATE_WR_FC_CNT_T; + +typedef struct dpp_se_smmu1_state_wr_req_cnt_t +{ + ZXIC_UINT32 state_wr_req_cnt; +}DPP_SE_SMMU1_STATE_WR_REQ_CNT_T; + +typedef struct dpp_se_smmu1_se_to_dma_rsp_cnt_t +{ + ZXIC_UINT32 se_to_dma_rsp_cnt; +}DPP_SE_SMMU1_SE_TO_DMA_RSP_CNT_T; + +typedef struct dpp_se_smmu1_se_to_dma_fc_cnt_t +{ + ZXIC_UINT32 se_to_dma_fc_cnt; +}DPP_SE_SMMU1_SE_TO_DMA_FC_CNT_T; + +typedef struct dpp_se_smmu1_oam_to_smmu1_fc_cnt_t +{ + ZXIC_UINT32 oam_to_smmu1_fc_cnt; +}DPP_SE_SMMU1_OAM_TO_SMMU1_FC_CNT_T; + +typedef struct dpp_se_smmu1_smmu1_to_oam_rsp_cnt_t +{ + ZXIC_UINT32 smmu1_to_oam_rsp_cnt; +}DPP_SE_SMMU1_SMMU1_TO_OAM_RSP_CNT_T; + +typedef struct dpp_se_smmu1_smmu1_to_oam_fc_cnt_t +{ + ZXIC_UINT32 smmu1_to_oam_fc_cnt; +}DPP_SE_SMMU1_SMMU1_TO_OAM_FC_CNT_T; + +typedef struct dpp_se_smmu1_oam_to_smmu1_req_cnt_t +{ + ZXIC_UINT32 oam_to_smmu1_req_cnt; +}DPP_SE_SMMU1_OAM_TO_SMMU1_REQ_CNT_T; + +typedef struct dpp_se_smmu1_smmu1_to_etm_rsp_cnt_t +{ + ZXIC_UINT32 smmu1_to_etm_rsp_cnt; +}DPP_SE_SMMU1_SMMU1_TO_ETM_RSP_CNT_T; + +typedef struct dpp_se_smmu1_smmu1_to_ftm_rsp_cnt_t +{ + ZXIC_UINT32 smmu1_to_ftm_rsp_cnt; +}DPP_SE_SMMU1_SMMU1_TO_FTM_RSP_CNT_T; + +typedef struct dpp_se_smmu1_smmu1_to_etm_fc_cnt_t +{ + ZXIC_UINT32 smmu1_to_etm_fc_cnt; +}DPP_SE_SMMU1_SMMU1_TO_ETM_FC_CNT_T; + +typedef struct dpp_se_smmu1_etm_to_smmu1_req_cnt_t +{ + ZXIC_UINT32 etm_to_smmu1_req_cnt; +}DPP_SE_SMMU1_ETM_TO_SMMU1_REQ_CNT_T; + +typedef struct dpp_se_smmu1_smmu1_to_ftm_fc_cnt_t +{ + ZXIC_UINT32 smmu1_to_ftm_fc_cnt; +}DPP_SE_SMMU1_SMMU1_TO_FTM_FC_CNT_T; + +typedef struct dpp_se_smmu1_ftm_to_smmu1_req_cnt_t +{ + ZXIC_UINT32 ftm_to_smmu1_req_cnt; +}DPP_SE_SMMU1_FTM_TO_SMMU1_REQ_CNT_T; + +typedef struct dpp_se_smmu1_smmu1_to_stat_rsp_cnt_t +{ + ZXIC_UINT32 smmu1_to_stat_rsp_cnt; +}DPP_SE_SMMU1_SMMU1_TO_STAT_RSP_CNT_T; + +typedef struct dpp_se_smmu1_smmu1_to_stat_fc_cnt_t +{ + ZXIC_UINT32 smmu1_to_stat_fc_cnt; +}DPP_SE_SMMU1_SMMU1_TO_STAT_FC_CNT_T; + +typedef struct dpp_se_smmu1_stat_to_smmu1_req_cnt_t +{ + ZXIC_UINT32 stat_to_smmu1_req_cnt; +}DPP_SE_SMMU1_STAT_TO_SMMU1_REQ_CNT_T; + +typedef struct dpp_se_smmu1_lpm_as_to_smmu1_fc_cnt_t +{ + ZXIC_UINT32 lpm_as_to_smmu1_fc_cnt; +}DPP_SE_SMMU1_LPM_AS_TO_SMMU1_FC_CNT_T; + +typedef struct dpp_se_smmu1_lpm_to_smmu1_fc_cnt_t +{ + ZXIC_UINT32 lpm_to_smmu1_fc_cnt; +}DPP_SE_SMMU1_LPM_TO_SMMU1_FC_CNT_T; + +typedef struct dpp_se_smmu1_smmu1_to_lpm_as_rsp_cnt_t +{ + ZXIC_UINT32 smmu1_to_lpm_as_rsp_cnt; +}DPP_SE_SMMU1_SMMU1_TO_LPM_AS_RSP_CNT_T; + +typedef struct dpp_se_smmu1_smmu1_to_lpm_rsp_cnt_t +{ + ZXIC_UINT32 smmu1_to_lpm_rsp_cnt; +}DPP_SE_SMMU1_SMMU1_TO_LPM_RSP_CNT_T; + +typedef struct dpp_se_smmu1_smmu1_to_lpm_as_fc_cnt_t +{ + ZXIC_UINT32 smmu1_to_lpm_as_fc_cnt; +}DPP_SE_SMMU1_SMMU1_TO_LPM_AS_FC_CNT_T; + +typedef struct dpp_se_smmu1_smmu1_to_lpm_fc_cnt_t +{ + ZXIC_UINT32 smmu1_to_lpm_fc_cnt; +}DPP_SE_SMMU1_SMMU1_TO_LPM_FC_CNT_T; + +typedef struct dpp_se_smmu1_lpm_as_to_smmu1_req_cnt_t +{ + ZXIC_UINT32 lpm_as_to_smmu1_req_cnt; +}DPP_SE_SMMU1_LPM_AS_TO_SMMU1_REQ_CNT_T; + +typedef struct dpp_se_smmu1_lpm_to_smmu1_req_cnt_t +{ + ZXIC_UINT32 lpm_to_smmu1_req_cnt; +}DPP_SE_SMMU1_LPM_TO_SMMU1_REQ_CNT_T; + +typedef struct dpp_se_smmu1_hash3_0_to_smmu1_fc_cnt_t +{ + ZXIC_UINT32 hash3_0_to_smmu1_fc_cnt; +}DPP_SE_SMMU1_HASH3_0_TO_SMMU1_FC_CNT_T; + +typedef struct dpp_se_smmu1_smmu1_to_hash3_0_rsp_cnt_t +{ + ZXIC_UINT32 smmu1_to_hash3_0_rsp_cnt; +}DPP_SE_SMMU1_SMMU1_TO_HASH3_0_RSP_CNT_T; + +typedef struct dpp_se_smmu1_smmu1_to_hash3_0_fc_cnt_t +{ + ZXIC_UINT32 smmu1_to_hash3_0_fc_cnt; +}DPP_SE_SMMU1_SMMU1_TO_HASH3_0_FC_CNT_T; + +typedef struct dpp_se_smmu1_hash3_0_to_smmu1_cnt_t +{ + ZXIC_UINT32 hash3_0_to_smmu1_cnt; +}DPP_SE_SMMU1_HASH3_0_TO_SMMU1_CNT_T; + +typedef struct dpp_se_smmu1_se_to_smmu1_dir3_0_rsp_fc_cnt_t +{ + ZXIC_UINT32 se_to_smmu1_dir3_0_rsp_fc_cnt; +}DPP_SE_SMMU1_SE_TO_SMMU1_DIR3_0_RSP_FC_CNT_T; + +typedef struct dpp_se_smmu1_smmu1_to_se_dir3_0_rsp_cnt_t +{ + ZXIC_UINT32 smmu1_to_se_dir3_0_rsp_cnt; +}DPP_SE_SMMU1_SMMU1_TO_SE_DIR3_0_RSP_CNT_T; + +typedef struct dpp_se_smmu1_smmu1_to_se_dir3_0_fc_cnt_t +{ + ZXIC_UINT32 smmu1_to_se_dir3_0_fc_cnt; +}DPP_SE_SMMU1_SMMU1_TO_SE_DIR3_0_FC_CNT_T; + +typedef struct dpp_se_smmu1_se_to_smmu1_dir3_0_cnt_t +{ + ZXIC_UINT32 se_to_smmu1_dir3_0_cnt; +}DPP_SE_SMMU1_SE_TO_SMMU1_DIR3_0_CNT_T; + +typedef struct dpp_se_smmu1_cache7_0_to_rschd_rsp_cnt_t +{ + ZXIC_UINT32 cache7_0_to_rschd_rsp_cnt; +}DPP_SE_SMMU1_CACHE7_0_TO_RSCHD_RSP_CNT_T; + +typedef struct dpp_se_cmmu_ddr_rw_addr_t +{ + ZXIC_UINT32 ddr_wr; +}DPP_SE_CMMU_DDR_RW_ADDR_T; + +typedef struct dpp_se_cmmu_ddr_rw_mode_t +{ + ZXIC_UINT32 ddr_rw_flag; + ZXIC_UINT32 ddr_rw_mode; +}DPP_SE_CMMU_DDR_RW_MODE_T; + +typedef struct dpp_se_cmmu_cp_cmd_t +{ + ZXIC_UINT32 stat_tbl_baddr; +}DPP_SE_CMMU_CP_CMD_T; + +typedef struct dpp_se_cmmu_cpu_ind_rd_done_t +{ + ZXIC_UINT32 cpu_ind_rd_done; +}DPP_SE_CMMU_CPU_IND_RD_DONE_T; + +typedef struct dpp_se_cmmu_cpu_ind_rdat0_t +{ + ZXIC_UINT32 cpu_ind_rdat0; +}DPP_SE_CMMU_CPU_IND_RDAT0_T; + +typedef struct dpp_se_cmmu_cpu_ind_rdat1_t +{ + ZXIC_UINT32 cpu_ind_rdat1; +}DPP_SE_CMMU_CPU_IND_RDAT1_T; + +typedef struct dpp_se_cmmu_cpu_ind_rdat2_t +{ + ZXIC_UINT32 cpu_ind_rdat2; +}DPP_SE_CMMU_CPU_IND_RDAT2_T; + +typedef struct dpp_se_cmmu_cpu_ind_rdat3_t +{ + ZXIC_UINT32 cpu_ind_rdat3; +}DPP_SE_CMMU_CPU_IND_RDAT3_T; + +typedef struct dpp_se_cmmu_cpu_ddr_fifo_almful_t +{ + ZXIC_UINT32 cpu_ddr_fifo_almful; +}DPP_SE_CMMU_CPU_DDR_FIFO_ALMFUL_T; + +typedef struct dpp_se_cmmu_debug_cnt_mode_t +{ + ZXIC_UINT32 cnt_rd_mode; + ZXIC_UINT32 cnt_overflow_mode; +}DPP_SE_CMMU_DEBUG_CNT_MODE_T; + +typedef struct dpp_se_cmmu_cmmu_pful_cfg_t +{ + ZXIC_UINT32 alu_cmd_pful_negate; + ZXIC_UINT32 alu_cmd_pful_assert; +}DPP_SE_CMMU_CMMU_PFUL_CFG_T; + +typedef struct dpp_se_cmmu_cmmu_stat_pful_cfg_t +{ + ZXIC_UINT32 cmmu_stat_pful_negate; + ZXIC_UINT32 cmmu_stat_pful_assert; +}DPP_SE_CMMU_CMMU_STAT_PFUL_CFG_T; + +typedef struct dpp_se_cmmu_stat_overflow_mode_t +{ + ZXIC_UINT32 stat_overflow_mode; +}DPP_SE_CMMU_STAT_OVERFLOW_MODE_T; + +typedef struct dpp_se_cmmu_cmmu_cp_fifo_pful_t +{ + ZXIC_UINT32 cmmu_cp_fifo_pful; +}DPP_SE_CMMU_CMMU_CP_FIFO_PFUL_T; + +typedef struct dpp_se_cmmu_ddr_wr_dat0_t +{ + ZXIC_UINT32 ddr_wr_dat0; +}DPP_SE_CMMU_DDR_WR_DAT0_T; + +typedef struct dpp_se_cmmu_ddr_wr_dat1_t +{ + ZXIC_UINT32 ddr_wr_dat1; +}DPP_SE_CMMU_DDR_WR_DAT1_T; + +typedef struct dpp_se_cmmu_cmmu_int_unmask_flag_t +{ + ZXIC_UINT32 cmmu_int_unmask_flag; +}DPP_SE_CMMU_CMMU_INT_UNMASK_FLAG_T; + +typedef struct dpp_se_cmmu_cmmu_int_en_t +{ + ZXIC_UINT32 cmmu_int_en12; + ZXIC_UINT32 cmmu_int_en11; + ZXIC_UINT32 cmmu_int_en10; + ZXIC_UINT32 cmmu_int_en9; + ZXIC_UINT32 cmmu_int_en8; + ZXIC_UINT32 cmmu_int_en7; + ZXIC_UINT32 cmmu_int_en6; + ZXIC_UINT32 cmmu_int_en5; + ZXIC_UINT32 cmmu_int_en4; + ZXIC_UINT32 cmmu_int_en3; + ZXIC_UINT32 cmmu_int_en2; + ZXIC_UINT32 cmmu_int_en1; + ZXIC_UINT32 cmmu_int_en0; +}DPP_SE_CMMU_CMMU_INT_EN_T; + +typedef struct dpp_se_cmmu_cmmu_int_mask_t +{ + ZXIC_UINT32 cmmu_int_mask12; + ZXIC_UINT32 cmmu_int_mask11; + ZXIC_UINT32 cmmu_int_mask10; + ZXIC_UINT32 cmmu_int_mask9; + ZXIC_UINT32 cmmu_int_mask8; + ZXIC_UINT32 cmmu_int_mask7; + ZXIC_UINT32 cmmu_int_mask6; + ZXIC_UINT32 cmmu_int_mask5; + ZXIC_UINT32 cmmu_int_mask4; + ZXIC_UINT32 cmmu_int_mask3; + ZXIC_UINT32 cmmu_int_mask2; + ZXIC_UINT32 cmmu_int_mask1; + ZXIC_UINT32 cmmu_int_mask0; +}DPP_SE_CMMU_CMMU_INT_MASK_T; + +typedef struct dpp_se_cmmu_cmmu_int_status_t +{ + ZXIC_UINT32 cmmu_int_status12; + ZXIC_UINT32 cmmu_int_status11; + ZXIC_UINT32 cmmu_int_status10; + ZXIC_UINT32 cmmu_int_status9; + ZXIC_UINT32 cmmu_int_status8; + ZXIC_UINT32 cmmu_int_status7; + ZXIC_UINT32 cmmu_int_status6; + ZXIC_UINT32 cmmu_int_status5; + ZXIC_UINT32 cmmu_int_status4; + ZXIC_UINT32 cmmu_int_status3; + ZXIC_UINT32 cmmu_int_status2; + ZXIC_UINT32 cmmu_int_status1; + ZXIC_UINT32 cmmu_int_status0; +}DPP_SE_CMMU_CMMU_INT_STATUS_T; + +typedef struct dpp_se_cmmu_stat_cmmu_req_cnt_t +{ + ZXIC_UINT32 stat_cmmu_req_cnt; +}DPP_SE_CMMU_STAT_CMMU_REQ_CNT_T; + +typedef struct dpp_se_cmmu_cmmu_fc0_cnt_t +{ + ZXIC_UINT32 cmmu_stat_rdy; +}DPP_SE_CMMU_CMMU_FC0_CNT_T; + +typedef struct dpp_se_cmmu_cmmu_fc1_cnt_t +{ + ZXIC_UINT32 smmu1_cmmu_wr_rdy; +}DPP_SE_CMMU_CMMU_FC1_CNT_T; + +typedef struct dpp_se_cmmu_cmmu_fc2_cnt_t +{ + ZXIC_UINT32 smmu1_cmmu_rd_rdy; +}DPP_SE_CMMU_CMMU_FC2_CNT_T; + + +#ifdef __cplusplus +} +#endif +#endif + diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_stat4k_reg.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_stat4k_reg.h new file mode 100644 index 0000000..f55a9cb --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_stat4k_reg.h @@ -0,0 +1,42 @@ + +#ifndef _DPP_STAT4K_REG_H_ +#define _DPP_STAT4K_REG_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +typedef struct dpp_stat4k_etcam_block0_7_port_id_cfg_t +{ + ZXIC_UINT32 block7_port_id; + ZXIC_UINT32 block6_port_id; + ZXIC_UINT32 block5_port_id; + ZXIC_UINT32 block4_port_id; + ZXIC_UINT32 block3_port_id; + ZXIC_UINT32 block2_port_id; + ZXIC_UINT32 block1_port_id; + ZXIC_UINT32 block0_port_id; +}DPP_STAT4K_ETCAM_BLOCK0_7_PORT_ID_CFG_T; + +typedef struct dpp_stat4k_etcam_block0_3_base_addr_cfg_t +{ + ZXIC_UINT32 block3_base_addr_cfg; + ZXIC_UINT32 block2_base_addr_cfg; + ZXIC_UINT32 block1_base_addr_cfg; + ZXIC_UINT32 block0_base_addr_cfg; +}DPP_STAT4K_ETCAM_BLOCK0_3_BASE_ADDR_CFG_T; + +typedef struct dpp_stat4k_etcam_block4_7_base_addr_cfg_t +{ + ZXIC_UINT32 block7_base_addr_cfg; + ZXIC_UINT32 block6_base_addr_cfg; + ZXIC_UINT32 block5_base_addr_cfg; + ZXIC_UINT32 block4_base_addr_cfg; +}DPP_STAT4K_ETCAM_BLOCK4_7_BASE_ADDR_CFG_T; + + +#ifdef __cplusplus +} +#endif +#endif + diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_stat_reg.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_stat_reg.h new file mode 100644 index 0000000..1ccb40b --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_stat_reg.h @@ -0,0 +1,2362 @@ + +#ifndef _DPP_STAT_REG_H_ +#define _DPP_STAT_REG_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +typedef struct dpp_stat_stat_cfg_cpu_ind_eram_wdat0_t +{ + ZXIC_UINT32 cpu_ind_eram_wdat0; +}DPP_STAT_STAT_CFG_CPU_IND_ERAM_WDAT0_T; + +typedef struct dpp_stat_stat_cfg_etm_port_sel_cfg_t +{ + ZXIC_UINT32 etm_port0_sel_cfg; + ZXIC_UINT32 etm_port1_sel_cfg; + ZXIC_UINT32 etm_port2_sel_cfg; + ZXIC_UINT32 etm_port3_sel_cfg; +}DPP_STAT_STAT_CFG_ETM_PORT_SEL_CFG_T; + +typedef struct dpp_stat_stat_cfg_tm_stat_cfg_t +{ + ZXIC_UINT32 stat_overflow_mode; + ZXIC_UINT32 tm_stat_mode_cfg; + ZXIC_UINT32 tm_flow_control_cfg; +}DPP_STAT_STAT_CFG_TM_STAT_CFG_T; + +typedef struct dpp_stat_stat_cfg_ppu_eram_depth_t +{ + ZXIC_UINT32 ppu_eram_depth; +}DPP_STAT_STAT_CFG_PPU_ERAM_DEPTH_T; + +typedef struct dpp_stat_stat_cfg_ppu_eram_base_addr_t +{ + ZXIC_UINT32 ppu_eram_base_addr; +}DPP_STAT_STAT_CFG_PPU_ERAM_BASE_ADDR_T; + +typedef struct dpp_stat_stat_cfg_ppu_ddr_base_addr_t +{ + ZXIC_UINT32 ppu_ddr_base_addr; +}DPP_STAT_STAT_CFG_PPU_DDR_BASE_ADDR_T; + +typedef struct dpp_stat_stat_cfg_plcr0_base_addr_t +{ + ZXIC_UINT32 plcr0_base_addr; +}DPP_STAT_STAT_CFG_PLCR0_BASE_ADDR_T; + +typedef struct dpp_stat_stat_cfg_etm_stat_start_addr_cfg_t +{ + ZXIC_UINT32 etm_stat_start_addr_cfg; +}DPP_STAT_STAT_CFG_ETM_STAT_START_ADDR_CFG_T; + +typedef struct dpp_stat_stat_cfg_etm_stat_depth_cfg_t +{ + ZXIC_UINT32 etm_stat_depth_cfg; +}DPP_STAT_STAT_CFG_ETM_STAT_DEPTH_CFG_T; + +typedef struct dpp_stat_stat_cfg_cycle_mov_en_cfg_t +{ + ZXIC_UINT32 cycle_mov_en_cfg; +}DPP_STAT_STAT_CFG_CYCLE_MOV_EN_CFG_T; + +typedef struct dpp_stat_etcam_cpu_ind_wdat0_t +{ + ZXIC_UINT32 wdat0; +}DPP_STAT_ETCAM_CPU_IND_WDAT0_T; + +typedef struct dpp_stat_etcam_cpu_ind_ctrl_tmp0_t +{ + ZXIC_UINT32 reg_tcam_flag; + ZXIC_UINT32 flush; + ZXIC_UINT32 rd_wr; + ZXIC_UINT32 wr_mode; + ZXIC_UINT32 dat_or_mask; + ZXIC_UINT32 ram_sel; + ZXIC_UINT32 addr; +}DPP_STAT_ETCAM_CPU_IND_CTRL_TMP0_T; + +typedef struct dpp_stat_etcam_cpu_ind_ctrl_tmp1_t +{ + ZXIC_UINT32 row_or_col_msk; + ZXIC_UINT32 vben; + ZXIC_UINT32 vbit; +}DPP_STAT_ETCAM_CPU_IND_CTRL_TMP1_T; + +typedef struct dpp_stat_etcam_cpu_ind_rd_done_t +{ + ZXIC_UINT32 cpu_ind_rd_done; +}DPP_STAT_ETCAM_CPU_IND_RD_DONE_T; + +typedef struct dpp_stat_etcam_cpu_rdat0_t +{ + ZXIC_UINT32 cpu_rdat0; +}DPP_STAT_ETCAM_CPU_RDAT0_T; + +typedef struct dpp_stat_etcam_cpu_rdat1_t +{ + ZXIC_UINT32 cpu_rdat1; +}DPP_STAT_ETCAM_CPU_RDAT1_T; + +typedef struct dpp_stat_etcam_cpu_rdat2_t +{ + ZXIC_UINT32 cpu_rdat2; +}DPP_STAT_ETCAM_CPU_RDAT2_T; + +typedef struct dpp_stat_etcam_cpu_rdat3_t +{ + ZXIC_UINT32 cpu_rdat3; +}DPP_STAT_ETCAM_CPU_RDAT3_T; + +typedef struct dpp_stat_etcam_cpu_rdat4_t +{ + ZXIC_UINT32 cpu_rdat4; +}DPP_STAT_ETCAM_CPU_RDAT4_T; + +typedef struct dpp_stat_etcam_cpu_rdat5_t +{ + ZXIC_UINT32 cpu_rdat5; +}DPP_STAT_ETCAM_CPU_RDAT5_T; + +typedef struct dpp_stat_etcam_cpu_rdat6_t +{ + ZXIC_UINT32 cpu_rdat6; +}DPP_STAT_ETCAM_CPU_RDAT6_T; + +typedef struct dpp_stat_etcam_cpu_rdat7_t +{ + ZXIC_UINT32 cpu_rdat7; +}DPP_STAT_ETCAM_CPU_RDAT7_T; + +typedef struct dpp_stat_etcam_cpu_rdat8_t +{ + ZXIC_UINT32 cpu_rdat8; +}DPP_STAT_ETCAM_CPU_RDAT8_T; + +typedef struct dpp_stat_etcam_cpu_rdat9_t +{ + ZXIC_UINT32 cpu_rdat9; +}DPP_STAT_ETCAM_CPU_RDAT9_T; + +typedef struct dpp_stat_etcam_cpu_rdat10_t +{ + ZXIC_UINT32 cpu_rdat10; +}DPP_STAT_ETCAM_CPU_RDAT10_T; + +typedef struct dpp_stat_etcam_cpu_rdat11_t +{ + ZXIC_UINT32 cpu_rdat11; +}DPP_STAT_ETCAM_CPU_RDAT11_T; + +typedef struct dpp_stat_etcam_cpu_rdat12_t +{ + ZXIC_UINT32 cpu_rdat12; +}DPP_STAT_ETCAM_CPU_RDAT12_T; + +typedef struct dpp_stat_etcam_cpu_rdat13_t +{ + ZXIC_UINT32 cpu_rdat13; +}DPP_STAT_ETCAM_CPU_RDAT13_T; + +typedef struct dpp_stat_etcam_cpu_rdat14_t +{ + ZXIC_UINT32 cpu_rdat14; +}DPP_STAT_ETCAM_CPU_RDAT14_T; + +typedef struct dpp_stat_etcam_cpu_rdat15_t +{ + ZXIC_UINT32 cpu_rdat15; +}DPP_STAT_ETCAM_CPU_RDAT15_T; + +typedef struct dpp_stat_etcam_cpu_rdat16_t +{ + ZXIC_UINT32 cpu_rdat16; +}DPP_STAT_ETCAM_CPU_RDAT16_T; + +typedef struct dpp_stat_etcam_cpu_rdat17_t +{ + ZXIC_UINT32 cpu_rdat17; +}DPP_STAT_ETCAM_CPU_RDAT17_T; + +typedef struct dpp_stat_etcam_cpu_rdat18_t +{ + ZXIC_UINT32 cpu_rdat18; +}DPP_STAT_ETCAM_CPU_RDAT18_T; + +typedef struct dpp_stat_etcam_cpu_rdat19_t +{ + ZXIC_UINT32 cpu_rdat19; +}DPP_STAT_ETCAM_CPU_RDAT19_T; + +typedef struct dpp_stat_etcam_qvbo_t +{ + ZXIC_UINT32 qvbo; +}DPP_STAT_ETCAM_QVBO_T; + +typedef struct dpp_stat_etcam_cnt_overflow_mode_t +{ + ZXIC_UINT32 cnt_rd_mode; + ZXIC_UINT32 cnt_overflow_mode; +}DPP_STAT_ETCAM_CNT_OVERFLOW_MODE_T; + +typedef struct dpp_stat_car0_cara_queue_ram0_159_0_t +{ + ZXIC_UINT32 cara_drop; + ZXIC_UINT32 cara_plcr_en; + ZXIC_UINT32 cara_profile_id; + ZXIC_UINT32 cara_tq_h; + ZXIC_UINT32 cara_tq_l; + ZXIC_UINT32 cara_ted; + ZXIC_UINT32 cara_tcd; + ZXIC_UINT32 cara_tei; + ZXIC_UINT32 cara_tci; +}DPP_STAT_CAR0_CARA_QUEUE_RAM0_159_0_T; + +typedef struct dpp_stat_car0_cara_profile_ram1_255_0_t +{ + ZXIC_UINT32 cara_profile_wr; + ZXIC_UINT32 cara_pkt_sign; + ZXIC_UINT32 cara_cd; + ZXIC_UINT32 cara_cf; + ZXIC_UINT32 cara_cm; + ZXIC_UINT32 cara_eir; + ZXIC_UINT32 cara_cir; + ZXIC_UINT32 cara_ebs_pbs; + ZXIC_UINT32 cara_cbs; + ZXIC_UINT32 cara_c_pri1; + ZXIC_UINT32 cara_c_pri2; + ZXIC_UINT32 cara_c_pri3; + ZXIC_UINT32 cara_c_pri4; + ZXIC_UINT32 cara_c_pri5; + ZXIC_UINT32 cara_c_pri6; + ZXIC_UINT32 cara_c_pri7; + ZXIC_UINT32 cara_e_g_pri1; + ZXIC_UINT32 cara_e_g_pri2; + ZXIC_UINT32 cara_e_g_pri3; + ZXIC_UINT32 cara_e_g_pri4; + ZXIC_UINT32 cara_e_g_pri5; + ZXIC_UINT32 cara_e_g_pri6; + ZXIC_UINT32 cara_e_g_pri7; + ZXIC_UINT32 cara_e_y_pri0; + ZXIC_UINT32 cara_e_y_pri1; + ZXIC_UINT32 cara_e_y_pri2; + ZXIC_UINT32 cara_e_y_pri3; + ZXIC_UINT32 cara_e_y_pri4; + ZXIC_UINT32 cara_e_y_pri5; + ZXIC_UINT32 cara_e_y_pri6; + ZXIC_UINT32 cara_e_y_pri7; +}DPP_STAT_CAR0_CARA_PROFILE_RAM1_255_0_T; + +typedef struct dpp_stat_car0_cara_qovs_ram_ram2_t +{ + ZXIC_UINT32 cara_qovs; +}DPP_STAT_CAR0_CARA_QOVS_RAM_RAM2_T; + +typedef struct dpp_stat_car0_look_up_table1_t +{ + ZXIC_UINT32 cara_flow_id; + ZXIC_UINT32 cara_sp; +}DPP_STAT_CAR0_LOOK_UP_TABLE1_T; + +typedef struct dpp_stat_car0_cara_pkt_des_i_cnt_t +{ + ZXIC_UINT32 cara_pkt_des_i_cnt; +}DPP_STAT_CAR0_CARA_PKT_DES_I_CNT_T; + +typedef struct dpp_stat_car0_cara_green_pkt_i_cnt_t +{ + ZXIC_UINT32 cara_green_pkt_i_cnt; +}DPP_STAT_CAR0_CARA_GREEN_PKT_I_CNT_T; + +typedef struct dpp_stat_car0_cara_yellow_pkt_i_cnt_t +{ + ZXIC_UINT32 cara_yellow_pkt_i_cnt; +}DPP_STAT_CAR0_CARA_YELLOW_PKT_I_CNT_T; + +typedef struct dpp_stat_car0_cara_red_pkt_i_cnt_t +{ + ZXIC_UINT32 cara_red_pkt_i_cnt; +}DPP_STAT_CAR0_CARA_RED_PKT_I_CNT_T; + +typedef struct dpp_stat_car0_cara_pkt_des_o_cnt_t +{ + ZXIC_UINT32 cara_pkt_des_o_cnt; +}DPP_STAT_CAR0_CARA_PKT_DES_O_CNT_T; + +typedef struct dpp_stat_car0_cara_green_pkt_o_cnt_t +{ + ZXIC_UINT32 cara_green_pkt_o_cnt; +}DPP_STAT_CAR0_CARA_GREEN_PKT_O_CNT_T; + +typedef struct dpp_stat_car0_cara_yellow_pkt_o_cnt_t +{ + ZXIC_UINT32 cara_yellow_pkt_o_cnt; +}DPP_STAT_CAR0_CARA_YELLOW_PKT_O_CNT_T; + +typedef struct dpp_stat_car0_cara_red_pkt_o_cnt_t +{ + ZXIC_UINT32 cara_red_pkt_o_cnt; +}DPP_STAT_CAR0_CARA_RED_PKT_O_CNT_T; + +typedef struct dpp_stat_car0_cara_pkt_des_fc_for_cfg_cnt_t +{ + ZXIC_UINT32 cara_pkt_des_fc_for_cfg_cnt; +}DPP_STAT_CAR0_CARA_PKT_DES_FC_FOR_CFG_CNT_T; + +typedef struct dpp_stat_car0_cara_appoint_qnum_or_sp_t +{ + ZXIC_UINT32 cara_appoint_qnum_or_not; + ZXIC_UINT32 cara_appoint_sp_or_not; + ZXIC_UINT32 cara_plcr_stat_sp; + ZXIC_UINT32 cara_plcr_stat_qnum; +}DPP_STAT_CAR0_CARA_APPOINT_QNUM_OR_SP_T; + +typedef struct dpp_stat_car0_cara_cfgmt_count_mode_t +{ + ZXIC_UINT32 cara_cfgmt_count_overflow_mode; + ZXIC_UINT32 cara_cfgmt_count_rd_mode; +}DPP_STAT_CAR0_CARA_CFGMT_COUNT_MODE_T; + +typedef struct dpp_stat_car0_cara_pkt_size_cnt_t +{ + ZXIC_UINT32 cara_pkt_size_cnt; +}DPP_STAT_CAR0_CARA_PKT_SIZE_CNT_T; + +typedef struct dpp_stat_car0_cara_plcr_init_dont_t +{ + ZXIC_UINT32 cara_plcr_init_done; +}DPP_STAT_CAR0_CARA_PLCR_INIT_DONT_T; + +typedef struct dpp_stat_car0_carb_queue_ram0_159_0_t +{ + ZXIC_UINT32 carb_drop; + ZXIC_UINT32 carb_plcr_en; + ZXIC_UINT32 carb_profile_id; + ZXIC_UINT32 carb_tq_h; + ZXIC_UINT32 carb_tq_l; + ZXIC_UINT32 carb_ted; + ZXIC_UINT32 carb_tcd; + ZXIC_UINT32 carb_tei; + ZXIC_UINT32 carb_tci; +}DPP_STAT_CAR0_CARB_QUEUE_RAM0_159_0_T; + +typedef struct dpp_stat_car0_carb_profile_ram1_255_0_t +{ + ZXIC_UINT32 carb_profile_wr; + ZXIC_UINT32 carb_random_discard_en_e; + ZXIC_UINT32 carb_random_discard_en_c; + ZXIC_UINT32 carb_pkt_sign; + ZXIC_UINT32 carb_cd; + ZXIC_UINT32 carb_cf; + ZXIC_UINT32 carb_cm; + ZXIC_UINT32 carb_eir; + ZXIC_UINT32 carb_cir; + ZXIC_UINT32 carb_ebs_pbs; + ZXIC_UINT32 carb_cbs; + ZXIC_UINT32 carb_c_pri1; + ZXIC_UINT32 carb_c_pri2; + ZXIC_UINT32 carb_c_pri3; + ZXIC_UINT32 carb_c_pri4; + ZXIC_UINT32 carb_c_pri5; + ZXIC_UINT32 carb_c_pri6; + ZXIC_UINT32 carb_c_pri7; + ZXIC_UINT32 carb_e_g_pri1; + ZXIC_UINT32 carb_e_g_pri2; + ZXIC_UINT32 carb_e_g_pri3; + ZXIC_UINT32 carb_e_g_pri4; + ZXIC_UINT32 carb_e_g_pri5; + ZXIC_UINT32 carb_e_g_pri6; + ZXIC_UINT32 carb_e_g_pri7; + ZXIC_UINT32 carb_e_y_pri0; + ZXIC_UINT32 carb_e_y_pri1; + ZXIC_UINT32 carb_e_y_pri2; + ZXIC_UINT32 carb_e_y_pri3; + ZXIC_UINT32 carb_e_y_pri4; + ZXIC_UINT32 carb_e_y_pri5; + ZXIC_UINT32 carb_e_y_pri6; + ZXIC_UINT32 carb_e_y_pri7; +}DPP_STAT_CAR0_CARB_PROFILE_RAM1_255_0_T; + +typedef struct dpp_stat_car0_carb_qovs_ram_ram2_t +{ + ZXIC_UINT32 carb_qovs; +}DPP_STAT_CAR0_CARB_QOVS_RAM_RAM2_T; + +typedef struct dpp_stat_car0_look_up_table2_t +{ + ZXIC_UINT32 carb_flow_id; + ZXIC_UINT32 carb_sp; +}DPP_STAT_CAR0_LOOK_UP_TABLE2_T; + +typedef struct dpp_stat_car0_carb_pkt_des_i_cnt_t +{ + ZXIC_UINT32 carb_pkt_des_i_cnt; +}DPP_STAT_CAR0_CARB_PKT_DES_I_CNT_T; + +typedef struct dpp_stat_car0_carb_green_pkt_i_cnt_t +{ + ZXIC_UINT32 carb_green_pkt_i_cnt; +}DPP_STAT_CAR0_CARB_GREEN_PKT_I_CNT_T; + +typedef struct dpp_stat_car0_carb_yellow_pkt_i_cnt_t +{ + ZXIC_UINT32 carb_yellow_pkt_i_cnt; +}DPP_STAT_CAR0_CARB_YELLOW_PKT_I_CNT_T; + +typedef struct dpp_stat_car0_carb_red_pkt_i_cnt_t +{ + ZXIC_UINT32 carb_red_pkt_i_cnt; +}DPP_STAT_CAR0_CARB_RED_PKT_I_CNT_T; + +typedef struct dpp_stat_car0_carb_pkt_des_o_cnt_t +{ + ZXIC_UINT32 carb_pkt_des_o_cnt; +}DPP_STAT_CAR0_CARB_PKT_DES_O_CNT_T; + +typedef struct dpp_stat_car0_carb_green_pkt_o_cnt_t +{ + ZXIC_UINT32 carb_green_pkt_o_cnt; +}DPP_STAT_CAR0_CARB_GREEN_PKT_O_CNT_T; + +typedef struct dpp_stat_car0_carb_yellow_pkt_o_cnt_t +{ + ZXIC_UINT32 carb_yellow_pkt_o_cnt; +}DPP_STAT_CAR0_CARB_YELLOW_PKT_O_CNT_T; + +typedef struct dpp_stat_car0_carb_red_pkt_o_cnt_t +{ + ZXIC_UINT32 carb_red_pkt_o_cnt; +}DPP_STAT_CAR0_CARB_RED_PKT_O_CNT_T; + +typedef struct dpp_stat_car0_carb_pkt_des_fc_for_cfg_cnt_t +{ + ZXIC_UINT32 carb_pkt_des_fc_for_cfg_cnt; +}DPP_STAT_CAR0_CARB_PKT_DES_FC_FOR_CFG_CNT_T; + +typedef struct dpp_stat_car0_carb_appoint_qnum_or_sp_t +{ + ZXIC_UINT32 carb_appoint_qnum_or_not; + ZXIC_UINT32 carb_appoint_sp_or_not; + ZXIC_UINT32 carb_plcr_stat_sp; + ZXIC_UINT32 carb_plcr_stat_qnum; +}DPP_STAT_CAR0_CARB_APPOINT_QNUM_OR_SP_T; + +typedef struct dpp_stat_car0_carb_cfgmt_count_mode_t +{ + ZXIC_UINT32 carb_cfgmt_count_overflow_mode; + ZXIC_UINT32 carb_cfgmt_count_rd_mode; +}DPP_STAT_CAR0_CARB_CFGMT_COUNT_MODE_T; + +typedef struct dpp_stat_car0_carb_pkt_size_cnt_t +{ + ZXIC_UINT32 carb_pkt_size_cnt; +}DPP_STAT_CAR0_CARB_PKT_SIZE_CNT_T; + +typedef struct dpp_stat_car0_carb_plcr_init_dont_t +{ + ZXIC_UINT32 carb_plcr_init_done; +}DPP_STAT_CAR0_CARB_PLCR_INIT_DONT_T; + +typedef struct dpp_stat_car0_carc_queue_ram0_159_0_t +{ + ZXIC_UINT32 carc_drop; + ZXIC_UINT32 carc_plcr_en; + ZXIC_UINT32 carc_profile_id; + ZXIC_UINT32 carc_tq_h; + ZXIC_UINT32 carc_tq_l; + ZXIC_UINT32 carc_ted; + ZXIC_UINT32 carc_tcd; + ZXIC_UINT32 carc_tei; + ZXIC_UINT32 carc_tci; +}DPP_STAT_CAR0_CARC_QUEUE_RAM0_159_0_T; + +typedef struct dpp_stat_car0_carc_profile_ram1_255_0_t +{ + ZXIC_UINT32 carc_profile_wr; + ZXIC_UINT32 carc_random_discard_en_e; + ZXIC_UINT32 carc_random_discard_en_c; + ZXIC_UINT32 carc_pkt_sign; + ZXIC_UINT32 carc_cd; + ZXIC_UINT32 carc_cf; + ZXIC_UINT32 carc_cm; + ZXIC_UINT32 carc_eir; + ZXIC_UINT32 carc_cir; + ZXIC_UINT32 carc_ebs_pbs; + ZXIC_UINT32 carc_cbs; + ZXIC_UINT32 carc_c_pri1; + ZXIC_UINT32 carc_c_pri2; + ZXIC_UINT32 carc_c_pri3; + ZXIC_UINT32 carc_c_pri4; + ZXIC_UINT32 carc_c_pri5; + ZXIC_UINT32 carc_c_pri6; + ZXIC_UINT32 carc_c_pri7; + ZXIC_UINT32 carc_e_g_pri1; + ZXIC_UINT32 carc_e_g_pri2; + ZXIC_UINT32 carc_e_g_pri3; + ZXIC_UINT32 carc_e_g_pri4; + ZXIC_UINT32 carc_e_g_pri5; + ZXIC_UINT32 carc_e_g_pri6; + ZXIC_UINT32 carc_e_g_pri7; + ZXIC_UINT32 carc_e_y_pri0; + ZXIC_UINT32 carc_e_y_pri1; + ZXIC_UINT32 carc_e_y_pri2; + ZXIC_UINT32 carc_e_y_pri3; + ZXIC_UINT32 carc_e_y_pri4; + ZXIC_UINT32 carc_e_y_pri5; + ZXIC_UINT32 carc_e_y_pri6; + ZXIC_UINT32 carc_e_y_pri7; +}DPP_STAT_CAR0_CARC_PROFILE_RAM1_255_0_T; + +typedef struct dpp_stat_car0_carc_qovs_ram_ram2_t +{ + ZXIC_UINT32 carc_qovs; +}DPP_STAT_CAR0_CARC_QOVS_RAM_RAM2_T; + +typedef struct dpp_stat_car0_carc_pkt_des_i_cnt_t +{ + ZXIC_UINT32 carc_pkt_des_i_cnt; +}DPP_STAT_CAR0_CARC_PKT_DES_I_CNT_T; + +typedef struct dpp_stat_car0_carc_green_pkt_i_cnt_t +{ + ZXIC_UINT32 carc_green_pkt_i_cnt; +}DPP_STAT_CAR0_CARC_GREEN_PKT_I_CNT_T; + +typedef struct dpp_stat_car0_carc_yellow_pkt_i_cnt_t +{ + ZXIC_UINT32 carc_yellow_pkt_i_cnt; +}DPP_STAT_CAR0_CARC_YELLOW_PKT_I_CNT_T; + +typedef struct dpp_stat_car0_carc_red_pkt_i_cnt_t +{ + ZXIC_UINT32 carc_red_pkt_i_cnt; +}DPP_STAT_CAR0_CARC_RED_PKT_I_CNT_T; + +typedef struct dpp_stat_car0_carc_pkt_des_o_cnt_t +{ + ZXIC_UINT32 carc_pkt_des_o_cnt; +}DPP_STAT_CAR0_CARC_PKT_DES_O_CNT_T; + +typedef struct dpp_stat_car0_carc_green_pkt_o_cnt_t +{ + ZXIC_UINT32 carc_green_pkt_o_cnt; +}DPP_STAT_CAR0_CARC_GREEN_PKT_O_CNT_T; + +typedef struct dpp_stat_car0_carc_yellow_pkt_o_cnt_t +{ + ZXIC_UINT32 carc_yellow_pkt_o_cnt; +}DPP_STAT_CAR0_CARC_YELLOW_PKT_O_CNT_T; + +typedef struct dpp_stat_car0_carc_red_pkt_o_cnt_t +{ + ZXIC_UINT32 carc_red_pkt_o_cnt; +}DPP_STAT_CAR0_CARC_RED_PKT_O_CNT_T; + +typedef struct dpp_stat_car0_carc_pkt_des_fc_for_cfg_cnt_t +{ + ZXIC_UINT32 carc_pkt_des_fc_for_cfg_cnt; +}DPP_STAT_CAR0_CARC_PKT_DES_FC_FOR_CFG_CNT_T; + +typedef struct dpp_stat_car0_carc_appoint_qnum_or_sp_t +{ + ZXIC_UINT32 carc_appoint_qnum_or_not; + ZXIC_UINT32 carc_appoint_sp_or_not; + ZXIC_UINT32 carc_plcr_stat_sp; + ZXIC_UINT32 carc_plcr_stat_qnum; +}DPP_STAT_CAR0_CARC_APPOINT_QNUM_OR_SP_T; + +typedef struct dpp_stat_car0_carc_cfgmt_count_mode_t +{ + ZXIC_UINT32 carc_cfgmt_count_overflow_mode; + ZXIC_UINT32 carc_cfgmt_count_rd_mode; +}DPP_STAT_CAR0_CARC_CFGMT_COUNT_MODE_T; + +typedef struct dpp_stat_car0_carc_pkt_size_cnt_t +{ + ZXIC_UINT32 carc_pkt_size_cnt; +}DPP_STAT_CAR0_CARC_PKT_SIZE_CNT_T; + +typedef struct dpp_stat_car0_carc_plcr_init_dont_t +{ + ZXIC_UINT32 carc_plcr_init_done; +}DPP_STAT_CAR0_CARC_PLCR_INIT_DONT_T; + +typedef struct dpp_stat_car0_carb_random_ram_t +{ + ZXIC_UINT32 para8_e; + ZXIC_UINT32 para7_e; + ZXIC_UINT32 para6_e; + ZXIC_UINT32 para5_e; + ZXIC_UINT32 para4_h_e; + ZXIC_UINT32 para4_l_e; + ZXIC_UINT32 para3_e; + ZXIC_UINT32 para2_h_e; + ZXIC_UINT32 para2_l_e; + ZXIC_UINT32 para1_e; + ZXIC_UINT32 para0_h_e; + ZXIC_UINT32 para0_l_e; + ZXIC_UINT32 para8_c; + ZXIC_UINT32 para7_c; + ZXIC_UINT32 para6_c; + ZXIC_UINT32 para5_c; + ZXIC_UINT32 para4_h_c; + ZXIC_UINT32 para4_l_c; + ZXIC_UINT32 para3_c; + ZXIC_UINT32 para2_h_c; + ZXIC_UINT32 para2_l_c; + ZXIC_UINT32 para1_c; + ZXIC_UINT32 para0_h_c; + ZXIC_UINT32 para0_l_c; +}DPP_STAT_CAR0_CARB_RANDOM_RAM_T; + +typedef struct dpp_stat_car0_carc_random_ram_t +{ + ZXIC_UINT32 para8_e; + ZXIC_UINT32 para7_e; + ZXIC_UINT32 para6_e; + ZXIC_UINT32 para5_e; + ZXIC_UINT32 para4_h_e; + ZXIC_UINT32 para4_l_e; + ZXIC_UINT32 para3_e; + ZXIC_UINT32 para2_h_e; + ZXIC_UINT32 para2_l_e; + ZXIC_UINT32 para1_e; + ZXIC_UINT32 para0_h_e; + ZXIC_UINT32 para0_l_e; + ZXIC_UINT32 para8_c; + ZXIC_UINT32 para7_c; + ZXIC_UINT32 para6_c; + ZXIC_UINT32 para5_c; + ZXIC_UINT32 para4_h_c; + ZXIC_UINT32 para4_l_c; + ZXIC_UINT32 para3_c; + ZXIC_UINT32 para2_h_c; + ZXIC_UINT32 para2_l_c; + ZXIC_UINT32 para1_c; + ZXIC_UINT32 para0_h_c; + ZXIC_UINT32 para0_l_c; +}DPP_STAT_CAR0_CARC_RANDOM_RAM_T; + +typedef struct dpp_stat_car0_cara_begin_flow_id_t +{ + ZXIC_UINT32 cara_begin_flow_id; +}DPP_STAT_CAR0_CARA_BEGIN_FLOW_ID_T; + +typedef struct dpp_stat_car0_carb_begin_flow_id_t +{ + ZXIC_UINT32 carb_begin_flow_id; +}DPP_STAT_CAR0_CARB_BEGIN_FLOW_ID_T; + +typedef struct dpp_stat_car0_carc_begin_flow_id_t +{ + ZXIC_UINT32 carc_begin_flow_id; +}DPP_STAT_CAR0_CARC_BEGIN_FLOW_ID_T; + +typedef struct dpp_stat_car0_prog_full_assert_cfg_w_t +{ + ZXIC_UINT32 prog_full_assert_cfg_w; +}DPP_STAT_CAR0_PROG_FULL_ASSERT_CFG_W_T; + +typedef struct dpp_stat_car0_prog_full_negate_cfg_w_t +{ + ZXIC_UINT32 prog_full_negate_cfg_w; +}DPP_STAT_CAR0_PROG_FULL_NEGATE_CFG_W_T; + +typedef struct dpp_stat_car0_timeout_limit_t +{ + ZXIC_UINT32 timeout_limit; +}DPP_STAT_CAR0_TIMEOUT_LIMIT_T; + +typedef struct dpp_stat_car0_pkt_des_fifo_overflow_t +{ + ZXIC_UINT32 pkt_des_fifo_overflow; +}DPP_STAT_CAR0_PKT_DES_FIFO_OVERFLOW_T; + +typedef struct dpp_stat_car0_pkt_des_fifo_underflow_t +{ + ZXIC_UINT32 pkt_des_fifo_underflow; +}DPP_STAT_CAR0_PKT_DES_FIFO_UNDERFLOW_T; + +typedef struct dpp_stat_car0_pkt_des_fifo_prog_full_t +{ + ZXIC_UINT32 pkt_des_fifo_prog_full; +}DPP_STAT_CAR0_PKT_DES_FIFO_PROG_FULL_T; + +typedef struct dpp_stat_car0_pkt_des_fifo_prog_empty_t +{ + ZXIC_UINT32 pkt_des_fifo_prog_empty; +}DPP_STAT_CAR0_PKT_DES_FIFO_PROG_EMPTY_T; + +typedef struct dpp_stat_car0_pkt_des_fifo_full_t +{ + ZXIC_UINT32 pkt_des_fifo_full; +}DPP_STAT_CAR0_PKT_DES_FIFO_FULL_T; + +typedef struct dpp_stat_car0_pkt_des_fifo_empty_t +{ + ZXIC_UINT32 pkt_des_fifo_empty; +}DPP_STAT_CAR0_PKT_DES_FIFO_EMPTY_T; + +typedef struct dpp_stat_car0_pkt_size_offset_t +{ + ZXIC_UINT32 pkt_size_offset; +}DPP_STAT_CAR0_PKT_SIZE_OFFSET_T; + +typedef struct dpp_stat_car0_car_plcr_init_dont_t +{ + ZXIC_UINT32 plcr_init_done; +}DPP_STAT_CAR0_CAR_PLCR_INIT_DONT_T; + +typedef struct dpp_stat_car0_max_pkt_size_a_t +{ + ZXIC_UINT32 max_pkt_size_a; +}DPP_STAT_CAR0_MAX_PKT_SIZE_A_T; + +typedef struct dpp_stat_car0_max_pkt_size_b_t +{ + ZXIC_UINT32 max_pkt_size_b; +}DPP_STAT_CAR0_MAX_PKT_SIZE_B_T; + +typedef struct dpp_stat_car0_max_pkt_size_c_t +{ + ZXIC_UINT32 max_pkt_size_c; +}DPP_STAT_CAR0_MAX_PKT_SIZE_C_T; + +typedef struct dpp_stat_car0_car_hierarchy_mode_t +{ + ZXIC_UINT32 car_hierarchy_mode; +}DPP_STAT_CAR0_CAR_HIERARCHY_MODE_T; + +typedef struct dpp_stat_car0_prog_empty_assert_cfg_w_t +{ + ZXIC_UINT32 prog_empty_assert_cfg_w; +}DPP_STAT_CAR0_PROG_EMPTY_ASSERT_CFG_W_T; + +typedef struct dpp_stat_car0_prog_empty_negate_cfg_w_t +{ + ZXIC_UINT32 prog_empty_negate_cfg_w; +}DPP_STAT_CAR0_PROG_EMPTY_NEGATE_CFG_W_T; + +typedef struct dpp_stat_car0_pkt_des_fifo_ovf_int_t +{ + ZXIC_UINT32 pkt_des_fifo_ovf_int; +}DPP_STAT_CAR0_PKT_DES_FIFO_OVF_INT_T; + +typedef struct dpp_stat_car0_pkt_des_fifo_data_count_t +{ + ZXIC_UINT32 pkt_des_fifo_data_count; +}DPP_STAT_CAR0_PKT_DES_FIFO_DATA_COUNT_T; + +typedef struct dpp_stat_car0_pkt_des_fifo_udf_int_t +{ + ZXIC_UINT32 pkt_des_fifo_udf_int; +}DPP_STAT_CAR0_PKT_DES_FIFO_UDF_INT_T; + +typedef struct dpp_stat_car0_cara_queue_ram0_159_0_pkt_t +{ + ZXIC_UINT32 cara_drop; + ZXIC_UINT32 cara_plcr_en; + ZXIC_UINT32 cara_profile_id; + ZXIC_UINT32 cara_tq_h; + ZXIC_UINT32 cara_tq_l; + ZXIC_UINT32 cara_dc_high; + ZXIC_UINT32 cara_dc_low; + ZXIC_UINT32 cara_tc; +}DPP_STAT_CAR0_CARA_QUEUE_RAM0_159_0_PKT_T; + +typedef struct dpp_stat_car0_cara_profile_ram1_255_0_pkt_t +{ + ZXIC_UINT32 cara_profile_wr; + ZXIC_UINT32 cara_pkt_sign; + ZXIC_UINT32 cara_pkt_cir; + ZXIC_UINT32 cara_pkt_cbs; + ZXIC_UINT32 cara_pri0; + ZXIC_UINT32 cara_pri1; + ZXIC_UINT32 cara_pri2; + ZXIC_UINT32 cara_pri3; + ZXIC_UINT32 cara_pri4; + ZXIC_UINT32 cara_pri5; + ZXIC_UINT32 cara_pri6; + ZXIC_UINT32 cara_pri7; +}DPP_STAT_CAR0_CARA_PROFILE_RAM1_255_0_PKT_T; + +typedef struct dpp_stat_stat_cfg_cpu_ind_eram_wdat1_t +{ + ZXIC_UINT32 cpu_ind_eram_wdat1; +}DPP_STAT_STAT_CFG_CPU_IND_ERAM_WDAT1_T; + +typedef struct dpp_stat_stat_cfg_cpu_ind_eram_wdat2_t +{ + ZXIC_UINT32 cpu_ind_eram_wdat2; +}DPP_STAT_STAT_CFG_CPU_IND_ERAM_WDAT2_T; + +typedef struct dpp_stat_stat_cfg_cpu_ind_eram_wdat3_t +{ + ZXIC_UINT32 cpu_ind_eram_wdat3; +}DPP_STAT_STAT_CFG_CPU_IND_ERAM_WDAT3_T; + +typedef struct dpp_stat_stat_cfg_cpu_ind_eram_req_info_t +{ + ZXIC_UINT32 rw_mode; + ZXIC_UINT32 read_mode; + ZXIC_UINT32 tm_cs; + ZXIC_UINT32 queue_cs; + ZXIC_UINT32 rw_addr; +}DPP_STAT_STAT_CFG_CPU_IND_ERAM_REQ_INFO_T; + +typedef struct dpp_stat_stat_cfg_cpu_ind_eram_rd_done_t +{ + ZXIC_UINT32 cpu_ind_eram_rd_done; +}DPP_STAT_STAT_CFG_CPU_IND_ERAM_RD_DONE_T; + +typedef struct dpp_stat_stat_cfg_cpu_ind_eram_rdat0_t +{ + ZXIC_UINT32 cpu_ind_eram_rdat0; +}DPP_STAT_STAT_CFG_CPU_IND_ERAM_RDAT0_T; + +typedef struct dpp_stat_stat_cfg_cpu_ind_eram_rdat1_t +{ + ZXIC_UINT32 cpu_ind_eram_rdat1; +}DPP_STAT_STAT_CFG_CPU_IND_ERAM_RDAT1_T; + +typedef struct dpp_stat_stat_cfg_cpu_ind_eram_rdat2_t +{ + ZXIC_UINT32 cpu_ind_eram_rdat2; +}DPP_STAT_STAT_CFG_CPU_IND_ERAM_RDAT2_T; + +typedef struct dpp_stat_stat_cfg_cpu_ind_eram_rdat3_t +{ + ZXIC_UINT32 cpu_ind_eram_rdat3; +}DPP_STAT_STAT_CFG_CPU_IND_ERAM_RDAT3_T; + +typedef struct dpp_stat_stat_cfg_tm_alu_eram_cpu_rdy_t +{ + ZXIC_UINT32 tm_alu_eram_cpu_rdy; +}DPP_STAT_STAT_CFG_TM_ALU_ERAM_CPU_RDY_T; + +typedef struct dpp_stat_stat_cfg_oam_stat_cfg_t +{ + ZXIC_UINT32 oam_flow_control_cfg; + ZXIC_UINT32 oam_lm_flow_control_cfg; + ZXIC_UINT32 oam_in_eram_cfg; +}DPP_STAT_STAT_CFG_OAM_STAT_CFG_T; + +typedef struct dpp_stat_stat_cfg_ftm_port_sel_cfg_t +{ + ZXIC_UINT32 ftm_port0_sel_cfg; + ZXIC_UINT32 ftm_port1_sel_cfg; + ZXIC_UINT32 ftm_port2_sel_cfg; + ZXIC_UINT32 ftm_port3_sel_cfg; +}DPP_STAT_STAT_CFG_FTM_PORT_SEL_CFG_T; + +typedef struct dpp_stat_stat_cfg_oam_eram_base_addr_t +{ + ZXIC_UINT32 oam_eram_base_addr; +}DPP_STAT_STAT_CFG_OAM_ERAM_BASE_ADDR_T; + +typedef struct dpp_stat_stat_cfg_oam_lm_eram_base_addr_t +{ + ZXIC_UINT32 oam_lm_eram_base_addr; +}DPP_STAT_STAT_CFG_OAM_LM_ERAM_BASE_ADDR_T; + +typedef struct dpp_stat_stat_cfg_oam_ddr_base_addr_t +{ + ZXIC_UINT32 oam_ddr_base_addr; +}DPP_STAT_STAT_CFG_OAM_DDR_BASE_ADDR_T; + +typedef struct dpp_stat_stat_cfg_plcr0_schd_pful_cfg_t +{ + ZXIC_UINT32 plcr0_schd_pful_assert; + ZXIC_UINT32 plcr0_schd_pful_negate; +}DPP_STAT_STAT_CFG_PLCR0_SCHD_PFUL_CFG_T; + +typedef struct dpp_stat_stat_cfg_oam_lm_ord_pful_cfg_t +{ + ZXIC_UINT32 oam_lm_ord_pful_assert; + ZXIC_UINT32 oam_lm_ord_pful_negate; +}DPP_STAT_STAT_CFG_OAM_LM_ORD_PFUL_CFG_T; + +typedef struct dpp_stat_stat_cfg_ddr_schd_pful_cfg_t +{ + ZXIC_UINT32 ddr_schd_pful_assert; + ZXIC_UINT32 ddr_schd_pful_negate; +}DPP_STAT_STAT_CFG_DDR_SCHD_PFUL_CFG_T; + +typedef struct dpp_stat_stat_cfg_eram_schd_pful_cfg_t +{ + ZXIC_UINT32 eram_schd_pful_assert; + ZXIC_UINT32 eram_schd_pful_negate; +}DPP_STAT_STAT_CFG_ERAM_SCHD_PFUL_CFG_T; + +typedef struct dpp_stat_stat_cfg_eram_schd_pept_cfg_t +{ + ZXIC_UINT32 eram_schd_pept_assert; + ZXIC_UINT32 eram_schd_pept_negate; +}DPP_STAT_STAT_CFG_ERAM_SCHD_PEPT_CFG_T; + +typedef struct dpp_stat_stat_cfg_eram_schd_oam_pful_cfg_t +{ + ZXIC_UINT32 eram_schd_oam_pful_assert; + ZXIC_UINT32 eram_schd_oam_pful_negate; +}DPP_STAT_STAT_CFG_ERAM_SCHD_OAM_PFUL_CFG_T; + +typedef struct dpp_stat_stat_cfg_eram_schd_oam_pept_cfg_t +{ + ZXIC_UINT32 eram_schd_oam_pept_assert; + ZXIC_UINT32 eram_schd_oam_pept_negate; +}DPP_STAT_STAT_CFG_ERAM_SCHD_OAM_PEPT_CFG_T; + +typedef struct dpp_stat_stat_cfg_eram_schd_oam_lm_pful_cfg_t +{ + ZXIC_UINT32 eram_schd_oam_lm_pful_assert; + ZXIC_UINT32 eram_schd_oam_lm_pful_negate; +}DPP_STAT_STAT_CFG_ERAM_SCHD_OAM_LM_PFUL_CFG_T; + +typedef struct dpp_stat_stat_cfg_eram_schd_oam_lm_pept_cfg_t +{ + ZXIC_UINT32 eram_schd_oam_lm_pept_assert; + ZXIC_UINT32 eram_schd_oam_lm_pept_negate; +}DPP_STAT_STAT_CFG_ERAM_SCHD_OAM_LM_PEPT_CFG_T; + +typedef struct dpp_stat_stat_cfg_rschd_pful_cfg_t +{ + ZXIC_UINT32 rschd_pful_assert; + ZXIC_UINT32 rschd_pful_negate; +}DPP_STAT_STAT_CFG_RSCHD_PFUL_CFG_T; + +typedef struct dpp_stat_stat_cfg_rschd_pept_cfg_t +{ + ZXIC_UINT32 rschd_pept_assert; + ZXIC_UINT32 rschd_pept_negate; +}DPP_STAT_STAT_CFG_RSCHD_PEPT_CFG_T; + +typedef struct dpp_stat_stat_cfg_rschd_plcr_pful_cfg_t +{ + ZXIC_UINT32 rschd_plcr_pful_assert; + ZXIC_UINT32 rschd_plcr_pful_negate; +}DPP_STAT_STAT_CFG_RSCHD_PLCR_PFUL_CFG_T; + +typedef struct dpp_stat_stat_cfg_rschd_plcr_pept_cfg_t +{ + ZXIC_UINT32 rschd_plcr_pept_assert; + ZXIC_UINT32 rschd_plcr_pept_negate; +}DPP_STAT_STAT_CFG_RSCHD_PLCR_PEPT_CFG_T; + +typedef struct dpp_stat_stat_cfg_rschd_plcr_info_pful_cfg_t +{ + ZXIC_UINT32 rschd_plcr_info_pful_assert; + ZXIC_UINT32 rschd_plcr_info_pful_negate; +}DPP_STAT_STAT_CFG_RSCHD_PLCR_INFO_PFUL_CFG_T; + +typedef struct dpp_stat_stat_cfg_alu_arb_cpu_pful_cfg_t +{ + ZXIC_UINT32 alu_arb_cpu_pful_assert; + ZXIC_UINT32 alu_arb_cpu_pful_negate; +}DPP_STAT_STAT_CFG_ALU_ARB_CPU_PFUL_CFG_T; + +typedef struct dpp_stat_stat_cfg_alu_arb_user_pful_cfg_t +{ + ZXIC_UINT32 alu_arb_user_pful_assert; + ZXIC_UINT32 alu_arb_user_pful_negate; +}DPP_STAT_STAT_CFG_ALU_ARB_USER_PFUL_CFG_T; + +typedef struct dpp_stat_stat_cfg_alu_arb_stat_pful_cfg_t +{ + ZXIC_UINT32 alu_arb_stat_pful_assert; + ZXIC_UINT32 alu_arb_stat_pful_negate; +}DPP_STAT_STAT_CFG_ALU_ARB_STAT_PFUL_CFG_T; + +typedef struct dpp_stat_stat_cfg_cycmov_dat_pful_cfg_t +{ + ZXIC_UINT32 cycmov_dat_pful_assert; + ZXIC_UINT32 cycmov_dat_pful_negate; +}DPP_STAT_STAT_CFG_CYCMOV_DAT_PFUL_CFG_T; + +typedef struct dpp_stat_stat_cfg_ddr_opr_pful_cfg_t +{ + ZXIC_UINT32 ddr_opr_pful_assert; + ZXIC_UINT32 ddr_opr_pful_negate; +}DPP_STAT_STAT_CFG_DDR_OPR_PFUL_CFG_T; + +typedef struct dpp_stat_stat_cfg_cycle_mov_pful_cfg_t +{ + ZXIC_UINT32 cycle_mov_pful_assert; + ZXIC_UINT32 cycle_mov_pful_negate; +}DPP_STAT_STAT_CFG_CYCLE_MOV_PFUL_CFG_T; + +typedef struct dpp_stat_stat_cfg_cntovf_pful_cfg_t +{ + ZXIC_UINT32 cntovf_pful_assert; + ZXIC_UINT32 cntovf_pful_negate; +}DPP_STAT_STAT_CFG_CNTOVF_PFUL_CFG_T; + +typedef struct dpp_stat_stat_cfg_eram_schd_plcr_pful_cfg_t +{ + ZXIC_UINT32 eram_schd_plcr_pful_assert; + ZXIC_UINT32 eram_schd_plcr_pful_negate; +}DPP_STAT_STAT_CFG_ERAM_SCHD_PLCR_PFUL_CFG_T; + +typedef struct dpp_stat_stat_cfg_eram_schd_plcr_pept_cfg_t +{ + ZXIC_UINT32 eram_schd_plcr_pept_assert; + ZXIC_UINT32 eram_schd_plcr_pept_negate; +}DPP_STAT_STAT_CFG_ERAM_SCHD_PLCR_PEPT_CFG_T; + +typedef struct dpp_stat_stat_cfg_debug_cnt_mode_t +{ + ZXIC_UINT32 cnt_rd_mode; + ZXIC_UINT32 cnt_overflow_mode; +}DPP_STAT_STAT_CFG_DEBUG_CNT_MODE_T; + +typedef struct dpp_stat_stat_cfg_tm_mov_period_cfg_t +{ + ZXIC_UINT32 etm_mov_period_cfg; + ZXIC_UINT32 ftm_mov_period_cfg; +}DPP_STAT_STAT_CFG_TM_MOV_PERIOD_CFG_T; + +typedef struct dpp_stat_stat_cfg_alu_ddr_cpu_req_pful_cfg_t +{ + ZXIC_UINT32 alu_ddr_cpu_req_pful_assert; + ZXIC_UINT32 alu_ddr_cpu_req_pful_negate; +}DPP_STAT_STAT_CFG_ALU_DDR_CPU_REQ_PFUL_CFG_T; + +typedef struct dpp_stat_stat_cfg_cycmov_addr_pful_cfg_t +{ + ZXIC_UINT32 cycmov_addr_pful_assert; + ZXIC_UINT32 cycmov_addr_pful_negate; +}DPP_STAT_STAT_CFG_CYCMOV_ADDR_PFUL_CFG_T; + +typedef struct dpp_stat_stat_cfg_ord_ddr_plcr_fifo_empty_t +{ + ZXIC_UINT32 ord_oam_lm_empty; + ZXIC_UINT32 ddr_schd_fifo_empty; + ZXIC_UINT32 plcr0_schd_fifo_empty; +}DPP_STAT_STAT_CFG_ORD_DDR_PLCR_FIFO_EMPTY_T; + +typedef struct dpp_stat_stat_cfg_tm_stat_fifo_empty_t +{ + ZXIC_UINT32 tm_stat_fifo_empty; +}DPP_STAT_STAT_CFG_TM_STAT_FIFO_EMPTY_T; + +typedef struct dpp_stat_stat_cfg_eram_schd_fifo_empty_0_1_t +{ + ZXIC_UINT32 eram_schd_fifo_empty1; + ZXIC_UINT32 eram_schd_fifo_empty0; +}DPP_STAT_STAT_CFG_ERAM_SCHD_FIFO_EMPTY_0_1_T; + +typedef struct dpp_stat_stat_cfg_eram_schd_fifo_empty_2_3_t +{ + ZXIC_UINT32 eram_schd_fifo_empty3; + ZXIC_UINT32 eram_schd_fifo_empty2; +}DPP_STAT_STAT_CFG_ERAM_SCHD_FIFO_EMPTY_2_3_T; + +typedef struct dpp_stat_stat_cfg_eram_schd_fifo_empty_4_5_t +{ + ZXIC_UINT32 eram_schd_fifo_empty5; + ZXIC_UINT32 eram_schd_fifo_empty4; +}DPP_STAT_STAT_CFG_ERAM_SCHD_FIFO_EMPTY_4_5_T; + +typedef struct dpp_stat_stat_cfg_eram_schd_fifo_empty_6_7_t +{ + ZXIC_UINT32 eram_schd_fifo_empty7; + ZXIC_UINT32 eram_schd_fifo_empty6; +}DPP_STAT_STAT_CFG_ERAM_SCHD_FIFO_EMPTY_6_7_T; + +typedef struct dpp_stat_stat_cfg_eram_schd_fifo_empty_free_8_t +{ + ZXIC_UINT32 eram_schd_free_fifo_empty8; + ZXIC_UINT32 eram_schd_free_fifo_empty7; + ZXIC_UINT32 eram_schd_free_fifo_empty6; + ZXIC_UINT32 eram_schd_free_fifo_empty5; + ZXIC_UINT32 eram_schd_free_fifo_empty4; + ZXIC_UINT32 eram_schd_free_fifo_empty3; + ZXIC_UINT32 eram_schd_free_fifo_empty2; + ZXIC_UINT32 eram_schd_free_fifo_empty1; + ZXIC_UINT32 eram_schd_free_fifo_empty0; + ZXIC_UINT32 eram_schd_fifo_empty8; +}DPP_STAT_STAT_CFG_ERAM_SCHD_FIFO_EMPTY_FREE_8_T; + +typedef struct dpp_stat_stat_cfg_rschd_fifo_empty_0_3_t +{ + ZXIC_UINT32 rschd_fifo_empty3; + ZXIC_UINT32 rschd_fifo_empty2; + ZXIC_UINT32 rschd_fifo_empty1; + ZXIC_UINT32 rschd_fifo_empty0; +}DPP_STAT_STAT_CFG_RSCHD_FIFO_EMPTY_0_3_T; + +typedef struct dpp_stat_stat_cfg_rschd_fifo_empty_4_7_t +{ + ZXIC_UINT32 rschd_fifo_empty7; + ZXIC_UINT32 rschd_fifo_empty6; + ZXIC_UINT32 rschd_fifo_empty5; + ZXIC_UINT32 rschd_fifo_empty4; +}DPP_STAT_STAT_CFG_RSCHD_FIFO_EMPTY_4_7_T; + +typedef struct dpp_stat_stat_cfg_rschd_fifo_empty_8_11_t +{ + ZXIC_UINT32 rschd_fifo_empty11; + ZXIC_UINT32 rschd_fifo_empty10; + ZXIC_UINT32 rschd_fifo_empty9; + ZXIC_UINT32 rschd_fifo_empty8; +}DPP_STAT_STAT_CFG_RSCHD_FIFO_EMPTY_8_11_T; + +typedef struct dpp_stat_stat_cfg_rschd_fifo_empty_12_15_t +{ + ZXIC_UINT32 rschd_fifo_empty15; + ZXIC_UINT32 rschd_fifo_empty14; + ZXIC_UINT32 rschd_fifo_empty13; + ZXIC_UINT32 rschd_fifo_empty12; +}DPP_STAT_STAT_CFG_RSCHD_FIFO_EMPTY_12_15_T; + +typedef struct dpp_stat_stat_cfg_rschd_fifo_empty_plcr_16_17_t +{ + ZXIC_UINT32 rschd_fifo_empty_plcr; + ZXIC_UINT32 rschd_fifo_empty17; + ZXIC_UINT32 rschd_fifo_empty16; +}DPP_STAT_STAT_CFG_RSCHD_FIFO_EMPTY_PLCR_16_17_T; + +typedef struct dpp_stat_stat_cfg_stat_int_unmask_flag_t +{ + ZXIC_UINT32 stat_int5_unmask_flag; + ZXIC_UINT32 stat_int4_unmask_flag; + ZXIC_UINT32 stat_int3_unmask_flag; + ZXIC_UINT32 stat_int2_unmask_flag; + ZXIC_UINT32 stat_int1_unmask_flag; + ZXIC_UINT32 stat_int0_unmask_flag; +}DPP_STAT_STAT_CFG_STAT_INT_UNMASK_FLAG_T; + +typedef struct dpp_stat_stat_cfg_stat_int0_en_t +{ + ZXIC_UINT32 stat_int0_en31; + ZXIC_UINT32 stat_int0_en30; + ZXIC_UINT32 stat_int0_en29; + ZXIC_UINT32 stat_int0_en28; + ZXIC_UINT32 stat_int0_en27; + ZXIC_UINT32 stat_int0_en26; + ZXIC_UINT32 stat_int0_en25; + ZXIC_UINT32 stat_int0_en24; + ZXIC_UINT32 stat_int0_en23; + ZXIC_UINT32 stat_int0_en22; + ZXIC_UINT32 stat_int0_en21; + ZXIC_UINT32 stat_int0_en20; + ZXIC_UINT32 stat_int0_en19; + ZXIC_UINT32 stat_int0_en18; + ZXIC_UINT32 stat_int0_en17; + ZXIC_UINT32 stat_int0_en16; + ZXIC_UINT32 stat_int0_en15; + ZXIC_UINT32 stat_int0_en14; + ZXIC_UINT32 stat_int0_en13; + ZXIC_UINT32 stat_int0_en12; + ZXIC_UINT32 stat_int0_en11; + ZXIC_UINT32 stat_int0_en10; + ZXIC_UINT32 stat_int0_en9; + ZXIC_UINT32 stat_int0_en8; + ZXIC_UINT32 stat_int0_en7; + ZXIC_UINT32 stat_int0_en6; + ZXIC_UINT32 stat_int0_en5; + ZXIC_UINT32 stat_int0_en4; + ZXIC_UINT32 stat_int0_en3; + ZXIC_UINT32 stat_int0_en2; + ZXIC_UINT32 stat_int0_en1; + ZXIC_UINT32 stat_int0_en0; +}DPP_STAT_STAT_CFG_STAT_INT0_EN_T; + +typedef struct dpp_stat_stat_cfg_stat_int0_mask_t +{ + ZXIC_UINT32 stat_int0_mask31; + ZXIC_UINT32 stat_int0_mask30; + ZXIC_UINT32 stat_int0_mask29; + ZXIC_UINT32 stat_int0_mask28; + ZXIC_UINT32 stat_int0_mask27; + ZXIC_UINT32 stat_int0_mask26; + ZXIC_UINT32 stat_int0_mask25; + ZXIC_UINT32 stat_int0_mask24; + ZXIC_UINT32 stat_int0_mask23; + ZXIC_UINT32 stat_int0_mask22; + ZXIC_UINT32 stat_int0_mask21; + ZXIC_UINT32 stat_int0_mask20; + ZXIC_UINT32 stat_int0_mask19; + ZXIC_UINT32 stat_int0_mask18; + ZXIC_UINT32 stat_int0_mask17; + ZXIC_UINT32 stat_int0_mask16; + ZXIC_UINT32 stat_int0_mask15; + ZXIC_UINT32 stat_int0_mask14; + ZXIC_UINT32 stat_int0_mask13; + ZXIC_UINT32 stat_int0_mask12; + ZXIC_UINT32 stat_int0_mask11; + ZXIC_UINT32 stat_int0_mask10; + ZXIC_UINT32 stat_int0_mask9; + ZXIC_UINT32 stat_int0_mask8; + ZXIC_UINT32 stat_int0_mask7; + ZXIC_UINT32 stat_int0_mask6; + ZXIC_UINT32 stat_int0_mask5; + ZXIC_UINT32 stat_int0_mask4; + ZXIC_UINT32 stat_int0_mask3; + ZXIC_UINT32 stat_int0_mask2; + ZXIC_UINT32 stat_int0_mask1; + ZXIC_UINT32 stat_int0_mask0; +}DPP_STAT_STAT_CFG_STAT_INT0_MASK_T; + +typedef struct dpp_stat_stat_cfg_stat_int0_status_t +{ + ZXIC_UINT32 stat_int0_status31; + ZXIC_UINT32 stat_int0_status30; + ZXIC_UINT32 stat_int0_status29; + ZXIC_UINT32 stat_int0_status28; + ZXIC_UINT32 stat_int0_status27; + ZXIC_UINT32 stat_int0_status26; + ZXIC_UINT32 stat_int0_status25; + ZXIC_UINT32 stat_int0_status24; + ZXIC_UINT32 stat_int0_status23; + ZXIC_UINT32 stat_int0_status22; + ZXIC_UINT32 stat_int0_status21; + ZXIC_UINT32 stat_int0_status20; + ZXIC_UINT32 stat_int0_status19; + ZXIC_UINT32 stat_int0_status18; + ZXIC_UINT32 stat_int0_status17; + ZXIC_UINT32 stat_int0_status16; + ZXIC_UINT32 stat_int0_status15; + ZXIC_UINT32 stat_int0_status14; + ZXIC_UINT32 stat_int0_status13; + ZXIC_UINT32 stat_int0_status12; + ZXIC_UINT32 stat_int0_status11; + ZXIC_UINT32 stat_int0_status10; + ZXIC_UINT32 stat_int0_status9; + ZXIC_UINT32 stat_int0_status8; + ZXIC_UINT32 stat_int0_status7; + ZXIC_UINT32 stat_int0_status6; + ZXIC_UINT32 stat_int0_status5; + ZXIC_UINT32 stat_int0_status4; + ZXIC_UINT32 stat_int0_status3; + ZXIC_UINT32 stat_int0_status2; + ZXIC_UINT32 stat_int0_status1; + ZXIC_UINT32 stat_int0_status0; +}DPP_STAT_STAT_CFG_STAT_INT0_STATUS_T; + +typedef struct dpp_stat_stat_cfg_stat_int1_en_t +{ + ZXIC_UINT32 stat_int1_en31; + ZXIC_UINT32 stat_int1_en30; + ZXIC_UINT32 stat_int1_en29; + ZXIC_UINT32 stat_int1_en28; + ZXIC_UINT32 stat_int1_en27; + ZXIC_UINT32 stat_int1_en26; + ZXIC_UINT32 stat_int1_en25; + ZXIC_UINT32 stat_int1_en24; + ZXIC_UINT32 stat_int1_en23; + ZXIC_UINT32 stat_int1_en22; + ZXIC_UINT32 stat_int1_en21; + ZXIC_UINT32 stat_int1_en20; + ZXIC_UINT32 stat_int1_en19; + ZXIC_UINT32 stat_int1_en18; + ZXIC_UINT32 stat_int1_en17; + ZXIC_UINT32 stat_int1_en16; + ZXIC_UINT32 stat_int1_en15; + ZXIC_UINT32 stat_int1_en14; + ZXIC_UINT32 stat_int1_en13; + ZXIC_UINT32 stat_int1_en12; + ZXIC_UINT32 stat_int1_en11; + ZXIC_UINT32 stat_int1_en10; + ZXIC_UINT32 stat_int1_en9; + ZXIC_UINT32 stat_int1_en8; + ZXIC_UINT32 stat_int1_en7; + ZXIC_UINT32 stat_int1_en6; + ZXIC_UINT32 stat_int1_en5; + ZXIC_UINT32 stat_int1_en4; + ZXIC_UINT32 stat_int1_en3; + ZXIC_UINT32 stat_int1_en2; + ZXIC_UINT32 stat_int1_en1; + ZXIC_UINT32 stat_int1_en0; +}DPP_STAT_STAT_CFG_STAT_INT1_EN_T; + +typedef struct dpp_stat_stat_cfg_stat_int1_mask_t +{ + ZXIC_UINT32 stat_int1_mask31; + ZXIC_UINT32 stat_int1_mask30; + ZXIC_UINT32 stat_int1_mask29; + ZXIC_UINT32 stat_int1_mask28; + ZXIC_UINT32 stat_int1_mask27; + ZXIC_UINT32 stat_int1_mask26; + ZXIC_UINT32 stat_int1_mask25; + ZXIC_UINT32 stat_int1_mask24; + ZXIC_UINT32 stat_int1_mask23; + ZXIC_UINT32 stat_int1_mask22; + ZXIC_UINT32 stat_int1_mask21; + ZXIC_UINT32 stat_int1_mask20; + ZXIC_UINT32 stat_int1_mask19; + ZXIC_UINT32 stat_int1_mask18; + ZXIC_UINT32 stat_int1_mask17; + ZXIC_UINT32 stat_int1_mask16; + ZXIC_UINT32 stat_int1_mask15; + ZXIC_UINT32 stat_int1_mask14; + ZXIC_UINT32 stat_int1_mask13; + ZXIC_UINT32 stat_int1_mask12; + ZXIC_UINT32 stat_int1_mask11; + ZXIC_UINT32 stat_int1_mask10; + ZXIC_UINT32 stat_int1_mask9; + ZXIC_UINT32 stat_int1_mask8; + ZXIC_UINT32 stat_int1_mask7; + ZXIC_UINT32 stat_int1_mask6; + ZXIC_UINT32 stat_int1_mask5; + ZXIC_UINT32 stat_int1_mask4; + ZXIC_UINT32 stat_int1_mask3; + ZXIC_UINT32 stat_int1_mask2; + ZXIC_UINT32 stat_int1_mask1; + ZXIC_UINT32 stat_int1_mask0; +}DPP_STAT_STAT_CFG_STAT_INT1_MASK_T; + +typedef struct dpp_stat_stat_cfg_stat_int1_status_t +{ + ZXIC_UINT32 stat_int1_status31; + ZXIC_UINT32 stat_int1_status30; + ZXIC_UINT32 stat_int1_status29; + ZXIC_UINT32 stat_int1_status28; + ZXIC_UINT32 stat_int1_status27; + ZXIC_UINT32 stat_int1_status26; + ZXIC_UINT32 stat_int1_status25; + ZXIC_UINT32 stat_int1_status24; + ZXIC_UINT32 stat_int1_status23; + ZXIC_UINT32 stat_int1_status22; + ZXIC_UINT32 stat_int1_status21; + ZXIC_UINT32 stat_int1_status20; + ZXIC_UINT32 stat_int1_status19; + ZXIC_UINT32 stat_int1_status18; + ZXIC_UINT32 stat_int1_status17; + ZXIC_UINT32 stat_int1_status16; + ZXIC_UINT32 stat_int1_status15; + ZXIC_UINT32 stat_int1_status14; + ZXIC_UINT32 stat_int1_status13; + ZXIC_UINT32 stat_int1_status12; + ZXIC_UINT32 stat_int1_status11; + ZXIC_UINT32 stat_int1_status10; + ZXIC_UINT32 stat_int1_status9; + ZXIC_UINT32 stat_int1_status8; + ZXIC_UINT32 stat_int1_status7; + ZXIC_UINT32 stat_int1_status6; + ZXIC_UINT32 stat_int1_status5; + ZXIC_UINT32 stat_int1_status4; + ZXIC_UINT32 stat_int1_status3; + ZXIC_UINT32 stat_int1_status2; + ZXIC_UINT32 stat_int1_status1; + ZXIC_UINT32 stat_int1_status0; +}DPP_STAT_STAT_CFG_STAT_INT1_STATUS_T; + +typedef struct dpp_stat_stat_cfg_stat_int2_en_t +{ + ZXIC_UINT32 stat_int2_en31; + ZXIC_UINT32 stat_int2_en30; + ZXIC_UINT32 stat_int2_en29; + ZXIC_UINT32 stat_int2_en28; + ZXIC_UINT32 stat_int2_en27; + ZXIC_UINT32 stat_int2_en26; + ZXIC_UINT32 stat_int2_en25; + ZXIC_UINT32 stat_int2_en24; + ZXIC_UINT32 stat_int2_en23; + ZXIC_UINT32 stat_int2_en22; + ZXIC_UINT32 stat_int2_en21; + ZXIC_UINT32 stat_int2_en20; + ZXIC_UINT32 stat_int2_en19; + ZXIC_UINT32 stat_int2_en18; + ZXIC_UINT32 stat_int2_en17; + ZXIC_UINT32 stat_int2_en16; + ZXIC_UINT32 stat_int2_en15; + ZXIC_UINT32 stat_int2_en14; + ZXIC_UINT32 stat_int2_en13; + ZXIC_UINT32 stat_int2_en12; + ZXIC_UINT32 stat_int2_en11; + ZXIC_UINT32 stat_int2_en10; + ZXIC_UINT32 stat_int2_en9; + ZXIC_UINT32 stat_int2_en8; + ZXIC_UINT32 stat_int2_en7; + ZXIC_UINT32 stat_int2_en6; + ZXIC_UINT32 stat_int2_en5; + ZXIC_UINT32 stat_int2_en4; + ZXIC_UINT32 stat_int2_en3; + ZXIC_UINT32 stat_int2_en2; + ZXIC_UINT32 stat_int2_en1; + ZXIC_UINT32 stat_int2_en0; +}DPP_STAT_STAT_CFG_STAT_INT2_EN_T; + +typedef struct dpp_stat_stat_cfg_stat_int2_mask_t +{ + ZXIC_UINT32 stat_int2_mask31; + ZXIC_UINT32 stat_int2_mask30; + ZXIC_UINT32 stat_int2_mask29; + ZXIC_UINT32 stat_int2_mask28; + ZXIC_UINT32 stat_int2_mask27; + ZXIC_UINT32 stat_int2_mask26; + ZXIC_UINT32 stat_int2_mask25; + ZXIC_UINT32 stat_int2_mask24; + ZXIC_UINT32 stat_int2_mask23; + ZXIC_UINT32 stat_int2_mask22; + ZXIC_UINT32 stat_int2_mask21; + ZXIC_UINT32 stat_int2_mask20; + ZXIC_UINT32 stat_int2_mask19; + ZXIC_UINT32 stat_int2_mask18; + ZXIC_UINT32 stat_int2_mask17; + ZXIC_UINT32 stat_int2_mask16; + ZXIC_UINT32 stat_int2_mask15; + ZXIC_UINT32 stat_int2_mask14; + ZXIC_UINT32 stat_int2_mask13; + ZXIC_UINT32 stat_int2_mask12; + ZXIC_UINT32 stat_int2_mask11; + ZXIC_UINT32 stat_int2_mask10; + ZXIC_UINT32 stat_int2_mask9; + ZXIC_UINT32 stat_int2_mask8; + ZXIC_UINT32 stat_int2_mask7; + ZXIC_UINT32 stat_int2_mask6; + ZXIC_UINT32 stat_int2_mask5; + ZXIC_UINT32 stat_int2_mask4; + ZXIC_UINT32 stat_int2_mask3; + ZXIC_UINT32 stat_int2_mask2; + ZXIC_UINT32 stat_int2_mask1; + ZXIC_UINT32 stat_int2_mask0; +}DPP_STAT_STAT_CFG_STAT_INT2_MASK_T; + +typedef struct dpp_stat_stat_cfg_stat_int2_status_t +{ + ZXIC_UINT32 stat_int2_status31; + ZXIC_UINT32 stat_int2_status30; + ZXIC_UINT32 stat_int2_status29; + ZXIC_UINT32 stat_int2_status28; + ZXIC_UINT32 stat_int2_status27; + ZXIC_UINT32 stat_int2_status26; + ZXIC_UINT32 stat_int2_status25; + ZXIC_UINT32 stat_int2_status24; + ZXIC_UINT32 stat_int2_status23; + ZXIC_UINT32 stat_int2_status22; + ZXIC_UINT32 stat_int2_status21; + ZXIC_UINT32 stat_int2_status20; + ZXIC_UINT32 stat_int2_status19; + ZXIC_UINT32 stat_int2_status18; + ZXIC_UINT32 stat_int2_status17; + ZXIC_UINT32 stat_int2_status16; + ZXIC_UINT32 stat_int2_status15; + ZXIC_UINT32 stat_int2_status14; + ZXIC_UINT32 stat_int2_status13; + ZXIC_UINT32 stat_int2_status12; + ZXIC_UINT32 stat_int2_status11; + ZXIC_UINT32 stat_int2_status10; + ZXIC_UINT32 stat_int2_status9; + ZXIC_UINT32 stat_int2_status8; + ZXIC_UINT32 stat_int2_status7; + ZXIC_UINT32 stat_int2_status6; + ZXIC_UINT32 stat_int2_status5; + ZXIC_UINT32 stat_int2_status4; + ZXIC_UINT32 stat_int2_status3; + ZXIC_UINT32 stat_int2_status2; + ZXIC_UINT32 stat_int2_status1; + ZXIC_UINT32 stat_int2_status0; +}DPP_STAT_STAT_CFG_STAT_INT2_STATUS_T; + +typedef struct dpp_stat_stat_cfg_stat_int3_en_t +{ + ZXIC_UINT32 stat_int3_en31; + ZXIC_UINT32 stat_int3_en30; + ZXIC_UINT32 stat_int3_en29; + ZXIC_UINT32 stat_int3_en28; + ZXIC_UINT32 stat_int3_en27; + ZXIC_UINT32 stat_int3_en26; + ZXIC_UINT32 stat_int3_en25; + ZXIC_UINT32 stat_int3_en24; + ZXIC_UINT32 stat_int3_en23; + ZXIC_UINT32 stat_int3_en22; + ZXIC_UINT32 stat_int3_en21; + ZXIC_UINT32 stat_int3_en20; + ZXIC_UINT32 stat_int3_en19; + ZXIC_UINT32 stat_int3_en18; + ZXIC_UINT32 stat_int3_en17; + ZXIC_UINT32 stat_int3_en16; + ZXIC_UINT32 stat_int3_en15; + ZXIC_UINT32 stat_int3_en14; + ZXIC_UINT32 stat_int3_en13; + ZXIC_UINT32 stat_int3_en12; + ZXIC_UINT32 stat_int3_en11; + ZXIC_UINT32 stat_int3_en10; + ZXIC_UINT32 stat_int3_en9; + ZXIC_UINT32 stat_int3_en8; + ZXIC_UINT32 stat_int3_en7; + ZXIC_UINT32 stat_int3_en6; + ZXIC_UINT32 stat_int3_en5; + ZXIC_UINT32 stat_int3_en4; + ZXIC_UINT32 stat_int3_en3; + ZXIC_UINT32 stat_int3_en2; + ZXIC_UINT32 stat_int3_en1; + ZXIC_UINT32 stat_int3_en0; +}DPP_STAT_STAT_CFG_STAT_INT3_EN_T; + +typedef struct dpp_stat_stat_cfg_stat_int3_mask_t +{ + ZXIC_UINT32 stat_int3_mask31; + ZXIC_UINT32 stat_int3_mask30; + ZXIC_UINT32 stat_int3_mask29; + ZXIC_UINT32 stat_int3_mask28; + ZXIC_UINT32 stat_int3_mask27; + ZXIC_UINT32 stat_int3_mask26; + ZXIC_UINT32 stat_int3_mask25; + ZXIC_UINT32 stat_int3_mask24; + ZXIC_UINT32 stat_int3_mask23; + ZXIC_UINT32 stat_int3_mask22; + ZXIC_UINT32 stat_int3_mask21; + ZXIC_UINT32 stat_int3_mask20; + ZXIC_UINT32 stat_int3_mask19; + ZXIC_UINT32 stat_int3_mask18; + ZXIC_UINT32 stat_int3_mask17; + ZXIC_UINT32 stat_int3_mask16; + ZXIC_UINT32 stat_int3_mask15; + ZXIC_UINT32 stat_int3_mask14; + ZXIC_UINT32 stat_int3_mask13; + ZXIC_UINT32 stat_int3_mask12; + ZXIC_UINT32 stat_int3_mask11; + ZXIC_UINT32 stat_int3_mask10; + ZXIC_UINT32 stat_int3_mask9; + ZXIC_UINT32 stat_int3_mask8; + ZXIC_UINT32 stat_int3_mask7; + ZXIC_UINT32 stat_int3_mask6; + ZXIC_UINT32 stat_int3_mask5; + ZXIC_UINT32 stat_int3_mask4; + ZXIC_UINT32 stat_int3_mask3; + ZXIC_UINT32 stat_int3_mask2; + ZXIC_UINT32 stat_int3_mask1; + ZXIC_UINT32 stat_int3_mask0; +}DPP_STAT_STAT_CFG_STAT_INT3_MASK_T; + +typedef struct dpp_stat_stat_cfg_stat_int3_status_t +{ + ZXIC_UINT32 stat_int3_status31; + ZXIC_UINT32 stat_int3_status30; + ZXIC_UINT32 stat_int3_status29; + ZXIC_UINT32 stat_int3_status28; + ZXIC_UINT32 stat_int3_status27; + ZXIC_UINT32 stat_int3_status26; + ZXIC_UINT32 stat_int3_status25; + ZXIC_UINT32 stat_int3_status24; + ZXIC_UINT32 stat_int3_status23; + ZXIC_UINT32 stat_int3_status22; + ZXIC_UINT32 stat_int3_status21; + ZXIC_UINT32 stat_int3_status20; + ZXIC_UINT32 stat_int3_status19; + ZXIC_UINT32 stat_int3_status18; + ZXIC_UINT32 stat_int3_status17; + ZXIC_UINT32 stat_int3_status16; + ZXIC_UINT32 stat_int3_status15; + ZXIC_UINT32 stat_int3_status14; + ZXIC_UINT32 stat_int3_status13; + ZXIC_UINT32 stat_int3_status12; + ZXIC_UINT32 stat_int3_status11; + ZXIC_UINT32 stat_int3_status10; + ZXIC_UINT32 stat_int3_status9; + ZXIC_UINT32 stat_int3_status8; + ZXIC_UINT32 stat_int3_status7; + ZXIC_UINT32 stat_int3_status6; + ZXIC_UINT32 stat_int3_status5; + ZXIC_UINT32 stat_int3_status4; + ZXIC_UINT32 stat_int3_status3; + ZXIC_UINT32 stat_int3_status2; + ZXIC_UINT32 stat_int3_status1; + ZXIC_UINT32 stat_int3_status0; +}DPP_STAT_STAT_CFG_STAT_INT3_STATUS_T; + +typedef struct dpp_stat_stat_cfg_stat_int4_en_t +{ + ZXIC_UINT32 stat_int4_en_18; + ZXIC_UINT32 stat_int4_en_17; + ZXIC_UINT32 stat_int4_en_16; + ZXIC_UINT32 stat_int4_en_15; + ZXIC_UINT32 stat_int4_en_14; + ZXIC_UINT32 stat_int4_en_13; + ZXIC_UINT32 stat_int4_en_12; + ZXIC_UINT32 stat_int4_en_11; + ZXIC_UINT32 stat_int4_en_10; + ZXIC_UINT32 stat_int4_en_9; + ZXIC_UINT32 stat_int4_en_8; + ZXIC_UINT32 stat_int4_en_7; + ZXIC_UINT32 stat_int4_en_6; + ZXIC_UINT32 stat_int4_en_5; + ZXIC_UINT32 stat_int4_en_4; + ZXIC_UINT32 stat_int4_en_3; + ZXIC_UINT32 stat_int4_en_2; + ZXIC_UINT32 stat_int4_en_1; + ZXIC_UINT32 stat_int4_en_0; +}DPP_STAT_STAT_CFG_STAT_INT4_EN_T; + +typedef struct dpp_stat_stat_cfg_stat_int4_mask_t +{ + ZXIC_UINT32 stat_int4_mask_18; + ZXIC_UINT32 stat_int4_mask_17; + ZXIC_UINT32 stat_int4_mask_16; + ZXIC_UINT32 stat_int4_mask_15; + ZXIC_UINT32 stat_int4_mask_14; + ZXIC_UINT32 stat_int4_mask_13; + ZXIC_UINT32 stat_int4_mask_12; + ZXIC_UINT32 stat_int4_mask_11; + ZXIC_UINT32 stat_int4_mask_10; + ZXIC_UINT32 stat_int4_mask_9; + ZXIC_UINT32 stat_int4_mask_8; + ZXIC_UINT32 stat_int4_mask_7; + ZXIC_UINT32 stat_int4_mask_6; + ZXIC_UINT32 stat_int4_mask_5; + ZXIC_UINT32 stat_int4_mask_4; + ZXIC_UINT32 stat_int4_mask_3; + ZXIC_UINT32 stat_int4_mask_2; + ZXIC_UINT32 stat_int4_mask_1; + ZXIC_UINT32 stat_int4_mask_0; +}DPP_STAT_STAT_CFG_STAT_INT4_MASK_T; + +typedef struct dpp_stat_stat_cfg_stat_int4_status_t +{ + ZXIC_UINT32 stat_int4_mask_18; + ZXIC_UINT32 stat_int4_mask_17; + ZXIC_UINT32 stat_int4_mask_16; + ZXIC_UINT32 stat_int4_mask_15; + ZXIC_UINT32 stat_int4_mask_14; + ZXIC_UINT32 stat_int4_mask_13; + ZXIC_UINT32 stat_int4_mask_12; + ZXIC_UINT32 stat_int4_mask_11; + ZXIC_UINT32 stat_int4_mask_10; + ZXIC_UINT32 stat_int4_mask_9; + ZXIC_UINT32 stat_int4_mask_8; + ZXIC_UINT32 stat_int4_mask_7; + ZXIC_UINT32 stat_int4_mask_6; + ZXIC_UINT32 stat_int4_mask_5; + ZXIC_UINT32 stat_int4_mask_4; + ZXIC_UINT32 stat_int4_mask_3; + ZXIC_UINT32 stat_int4_mask_2; + ZXIC_UINT32 stat_int4_mask_1; + ZXIC_UINT32 stat_int4_mask_0; +}DPP_STAT_STAT_CFG_STAT_INT4_STATUS_T; + +typedef struct dpp_stat_stat_cfg_stat_int5_en_t +{ + ZXIC_UINT32 stat_int5_en_18; + ZXIC_UINT32 stat_int5_en_17; + ZXIC_UINT32 stat_int5_en_16; + ZXIC_UINT32 stat_int5_en_15; + ZXIC_UINT32 stat_int5_en_14; + ZXIC_UINT32 stat_int5_en_13; + ZXIC_UINT32 stat_int5_en_12; + ZXIC_UINT32 stat_int5_en_11; + ZXIC_UINT32 stat_int5_en_10; + ZXIC_UINT32 stat_int5_en_9; + ZXIC_UINT32 stat_int5_en_8; + ZXIC_UINT32 stat_int5_en_7; + ZXIC_UINT32 stat_int5_en_6; + ZXIC_UINT32 stat_int5_en_5; + ZXIC_UINT32 stat_int5_en_4; + ZXIC_UINT32 stat_int5_en_3; + ZXIC_UINT32 stat_int5_en_2; + ZXIC_UINT32 stat_int5_en_1; + ZXIC_UINT32 stat_int5_en_0; +}DPP_STAT_STAT_CFG_STAT_INT5_EN_T; + +typedef struct dpp_stat_stat_cfg_stat_int5_mask_t +{ + ZXIC_UINT32 stat_int5_mask_18; + ZXIC_UINT32 stat_int5_mask_17; + ZXIC_UINT32 stat_int5_mask_16; + ZXIC_UINT32 stat_int5_mask_15; + ZXIC_UINT32 stat_int5_mask_14; + ZXIC_UINT32 stat_int5_mask_13; + ZXIC_UINT32 stat_int5_mask_12; + ZXIC_UINT32 stat_int5_mask_11; + ZXIC_UINT32 stat_int5_mask_10; + ZXIC_UINT32 stat_int5_mask_9; + ZXIC_UINT32 stat_int5_mask_8; + ZXIC_UINT32 stat_int5_mask_7; + ZXIC_UINT32 stat_int5_mask_6; + ZXIC_UINT32 stat_int5_mask_5; + ZXIC_UINT32 stat_int5_mask_4; + ZXIC_UINT32 stat_int5_mask_3; + ZXIC_UINT32 stat_int5_mask_2; + ZXIC_UINT32 stat_int5_mask_1; + ZXIC_UINT32 stat_int5_mask_0; +}DPP_STAT_STAT_CFG_STAT_INT5_MASK_T; + +typedef struct dpp_stat_stat_cfg_stat_int5_status_t +{ + ZXIC_UINT32 stat_int5_mask_18; + ZXIC_UINT32 stat_int5_mask_17; + ZXIC_UINT32 stat_int5_mask_16; + ZXIC_UINT32 stat_int5_mask_15; + ZXIC_UINT32 stat_int5_mask_14; + ZXIC_UINT32 stat_int5_mask_13; + ZXIC_UINT32 stat_int5_mask_12; + ZXIC_UINT32 stat_int5_mask_11; + ZXIC_UINT32 stat_int5_mask_10; + ZXIC_UINT32 stat_int5_mask_9; + ZXIC_UINT32 stat_int5_mask_8; + ZXIC_UINT32 stat_int5_mask_7; + ZXIC_UINT32 stat_int5_mask_6; + ZXIC_UINT32 stat_int5_mask_5; + ZXIC_UINT32 stat_int5_mask_4; + ZXIC_UINT32 stat_int5_mask_3; + ZXIC_UINT32 stat_int5_mask_2; + ZXIC_UINT32 stat_int5_mask_1; + ZXIC_UINT32 stat_int5_mask_0; +}DPP_STAT_STAT_CFG_STAT_INT5_STATUS_T; + +typedef struct dpp_stat_stat_cfg_rschd_ecc_bypass_t +{ + ZXIC_UINT32 rschd_ecc_bypass_18; + ZXIC_UINT32 rschd_ecc_bypass_17; + ZXIC_UINT32 rschd_ecc_bypass_16; + ZXIC_UINT32 rschd_ecc_bypass_15; + ZXIC_UINT32 rschd_ecc_bypass_14; + ZXIC_UINT32 rschd_ecc_bypass_13; + ZXIC_UINT32 rschd_ecc_bypass_12; + ZXIC_UINT32 rschd_ecc_bypass_11; + ZXIC_UINT32 rschd_ecc_bypass_10; + ZXIC_UINT32 rschd_ecc_bypass_9; + ZXIC_UINT32 rschd_ecc_bypass_8; + ZXIC_UINT32 rschd_ecc_bypass_7; + ZXIC_UINT32 rschd_ecc_bypass_6; + ZXIC_UINT32 rschd_ecc_bypass_5; + ZXIC_UINT32 rschd_ecc_bypass_4; + ZXIC_UINT32 rschd_ecc_bypass_3; + ZXIC_UINT32 rschd_ecc_bypass_2; + ZXIC_UINT32 rschd_ecc_bypass_1; + ZXIC_UINT32 rschd_ecc_bypass_0; +}DPP_STAT_STAT_CFG_RSCHD_ECC_BYPASS_T; + +typedef struct dpp_stat_stat_cfg_rschd_ecc_single_err_t +{ + ZXIC_UINT32 rschd_ecc_single_err_18; + ZXIC_UINT32 rschd_ecc_single_err_17; + ZXIC_UINT32 rschd_ecc_single_err_16; + ZXIC_UINT32 rschd_ecc_single_err_15; + ZXIC_UINT32 rschd_ecc_single_err_14; + ZXIC_UINT32 rschd_ecc_single_err_13; + ZXIC_UINT32 rschd_ecc_single_err_12; + ZXIC_UINT32 rschd_ecc_single_err_11; + ZXIC_UINT32 rschd_ecc_single_err_10; + ZXIC_UINT32 rschd_ecc_single_err_9; + ZXIC_UINT32 rschd_ecc_single_err_8; + ZXIC_UINT32 rschd_ecc_single_err_7; + ZXIC_UINT32 rschd_ecc_single_err_6; + ZXIC_UINT32 rschd_ecc_single_err_5; + ZXIC_UINT32 rschd_ecc_single_err_4; + ZXIC_UINT32 rschd_ecc_single_err_3; + ZXIC_UINT32 rschd_ecc_single_err_2; + ZXIC_UINT32 rschd_ecc_single_err_1; + ZXIC_UINT32 rschd_ecc_single_err_0; +}DPP_STAT_STAT_CFG_RSCHD_ECC_SINGLE_ERR_T; + +typedef struct dpp_stat_stat_cfg_rschd_ecc_double_err_t +{ + ZXIC_UINT32 rschd_ecc_double_err_18; + ZXIC_UINT32 rschd_ecc_double_err_17; + ZXIC_UINT32 rschd_ecc_double_err_16; + ZXIC_UINT32 rschd_ecc_double_err_15; + ZXIC_UINT32 rschd_ecc_double_err_14; + ZXIC_UINT32 rschd_ecc_double_err_13; + ZXIC_UINT32 rschd_ecc_double_err_12; + ZXIC_UINT32 rschd_ecc_double_err_11; + ZXIC_UINT32 rschd_ecc_double_err_10; + ZXIC_UINT32 rschd_ecc_double_err_9; + ZXIC_UINT32 rschd_ecc_double_err_8; + ZXIC_UINT32 rschd_ecc_double_err_7; + ZXIC_UINT32 rschd_ecc_double_err_6; + ZXIC_UINT32 rschd_ecc_double_err_5; + ZXIC_UINT32 rschd_ecc_double_err_4; + ZXIC_UINT32 rschd_ecc_double_err_3; + ZXIC_UINT32 rschd_ecc_double_err_2; + ZXIC_UINT32 rschd_ecc_double_err_1; + ZXIC_UINT32 rschd_ecc_double_err_0; +}DPP_STAT_STAT_CFG_RSCHD_ECC_DOUBLE_ERR_T; + +typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_wdat0_t +{ + ZXIC_UINT32 cpu_ind_ddr_wdat0; +}DPP_STAT_STAT_CFG_CPU_IND_DDR_WDAT0_T; + +typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_wdat1_t +{ + ZXIC_UINT32 cpu_ind_ddr_wdat1; +}DPP_STAT_STAT_CFG_CPU_IND_DDR_WDAT1_T; + +typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_wdat2_t +{ + ZXIC_UINT32 cpu_ind_ddr_wdat2; +}DPP_STAT_STAT_CFG_CPU_IND_DDR_WDAT2_T; + +typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_wdat3_t +{ + ZXIC_UINT32 cpu_ind_ddr_wdat3; +}DPP_STAT_STAT_CFG_CPU_IND_DDR_WDAT3_T; + +typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_wdat4_t +{ + ZXIC_UINT32 cpu_ind_ddr_wdat4; +}DPP_STAT_STAT_CFG_CPU_IND_DDR_WDAT4_T; + +typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_wdat5_t +{ + ZXIC_UINT32 cpu_ind_ddr_wdat5; +}DPP_STAT_STAT_CFG_CPU_IND_DDR_WDAT5_T; + +typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_wdat6_t +{ + ZXIC_UINT32 cpu_ind_ddr_wdat6; +}DPP_STAT_STAT_CFG_CPU_IND_DDR_WDAT6_T; + +typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_wdat7_t +{ + ZXIC_UINT32 cpu_ind_ddr_wdat7; +}DPP_STAT_STAT_CFG_CPU_IND_DDR_WDAT7_T; + +typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_wdat8_t +{ + ZXIC_UINT32 cpu_ind_ddr_wdat8; +}DPP_STAT_STAT_CFG_CPU_IND_DDR_WDAT8_T; + +typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_wdat9_t +{ + ZXIC_UINT32 cpu_ind_ddr_wdat9; +}DPP_STAT_STAT_CFG_CPU_IND_DDR_WDAT9_T; + +typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_wdat10_t +{ + ZXIC_UINT32 cpu_ind_ddr_wdat10; +}DPP_STAT_STAT_CFG_CPU_IND_DDR_WDAT10_T; + +typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_wdat11_t +{ + ZXIC_UINT32 cpu_ind_ddr_wdat11; +}DPP_STAT_STAT_CFG_CPU_IND_DDR_WDAT11_T; + +typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_wdat12_t +{ + ZXIC_UINT32 cpu_ind_ddr_wdat12; +}DPP_STAT_STAT_CFG_CPU_IND_DDR_WDAT12_T; + +typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_wdat13_t +{ + ZXIC_UINT32 cpu_ind_ddr_wdat13; +}DPP_STAT_STAT_CFG_CPU_IND_DDR_WDAT13_T; + +typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_wdat14_t +{ + ZXIC_UINT32 cpu_ind_ddr_wdat14; +}DPP_STAT_STAT_CFG_CPU_IND_DDR_WDAT14_T; + +typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_wdat15_t +{ + ZXIC_UINT32 cpu_ind_ddr_wdat15; +}DPP_STAT_STAT_CFG_CPU_IND_DDR_WDAT15_T; + +typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_req_info_t +{ + ZXIC_UINT32 rw_mode; + ZXIC_UINT32 read_mode; + ZXIC_UINT32 tm_cs; + ZXIC_UINT32 rw_addr; +}DPP_STAT_STAT_CFG_CPU_IND_DDR_REQ_INFO_T; + +typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_rd_done_t +{ + ZXIC_UINT32 cpu_ind_ddr_rd_done; +}DPP_STAT_STAT_CFG_CPU_IND_DDR_RD_DONE_T; + +typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_rdat0_t +{ + ZXIC_UINT32 cpu_ind_ddr_rdat0; +}DPP_STAT_STAT_CFG_CPU_IND_DDR_RDAT0_T; + +typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_rdat1_t +{ + ZXIC_UINT32 cpu_ind_ddr_rdat1; +}DPP_STAT_STAT_CFG_CPU_IND_DDR_RDAT1_T; + +typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_rdat2_t +{ + ZXIC_UINT32 cpu_ind_ddr_rdat2; +}DPP_STAT_STAT_CFG_CPU_IND_DDR_RDAT2_T; + +typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_rdat3_t +{ + ZXIC_UINT32 cpu_ind_ddr_rdat3; +}DPP_STAT_STAT_CFG_CPU_IND_DDR_RDAT3_T; + +typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_rdat4_t +{ + ZXIC_UINT32 cpu_ind_ddr_rdat4; +}DPP_STAT_STAT_CFG_CPU_IND_DDR_RDAT4_T; + +typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_rdat5_t +{ + ZXIC_UINT32 cpu_ind_ddr_rdat5; +}DPP_STAT_STAT_CFG_CPU_IND_DDR_RDAT5_T; + +typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_rdat6_t +{ + ZXIC_UINT32 cpu_ind_ddr_rdat6; +}DPP_STAT_STAT_CFG_CPU_IND_DDR_RDAT6_T; + +typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_rdat7_t +{ + ZXIC_UINT32 cpu_ind_ddr_rdat7; +}DPP_STAT_STAT_CFG_CPU_IND_DDR_RDAT7_T; + +typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_rdat8_t +{ + ZXIC_UINT32 cpu_ind_ddr_rdat8; +}DPP_STAT_STAT_CFG_CPU_IND_DDR_RDAT8_T; + +typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_rdat9_t +{ + ZXIC_UINT32 cpu_ind_ddr_rdat9; +}DPP_STAT_STAT_CFG_CPU_IND_DDR_RDAT9_T; + +typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_rdat10_t +{ + ZXIC_UINT32 cpu_ind_ddr_rdat10; +}DPP_STAT_STAT_CFG_CPU_IND_DDR_RDAT10_T; + +typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_rdat11_t +{ + ZXIC_UINT32 cpu_ind_ddr_rdat11; +}DPP_STAT_STAT_CFG_CPU_IND_DDR_RDAT11_T; + +typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_rdat12_t +{ + ZXIC_UINT32 cpu_ind_ddr_rdat12; +}DPP_STAT_STAT_CFG_CPU_IND_DDR_RDAT12_T; + +typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_rdat13_t +{ + ZXIC_UINT32 cpu_ind_ddr_rdat13; +}DPP_STAT_STAT_CFG_CPU_IND_DDR_RDAT13_T; + +typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_rdat14_t +{ + ZXIC_UINT32 cpu_ind_ddr_rdat14; +}DPP_STAT_STAT_CFG_CPU_IND_DDR_RDAT14_T; + +typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_rdat15_t +{ + ZXIC_UINT32 cpu_ind_ddr_rdat15; +}DPP_STAT_STAT_CFG_CPU_IND_DDR_RDAT15_T; + +typedef struct dpp_stat_stat_cfg_tm_alu_ddr_cpu_rdy_t +{ + ZXIC_UINT32 tm_alu_ddr_cpu_rdy; +}DPP_STAT_STAT_CFG_TM_ALU_DDR_CPU_RDY_T; + +typedef struct dpp_stat_stat_cfg_ept_flag_t +{ + ZXIC_UINT32 ept_flag; +}DPP_STAT_STAT_CFG_EPT_FLAG_T; + +typedef struct dpp_stat_stat_cfg_ppu_soft_rst_t +{ + ZXIC_UINT32 ppu_soft_rst; +}DPP_STAT_STAT_CFG_PPU_SOFT_RST_T; + +typedef struct dpp_stat_stat_cfg_stat_smmu0_fc15_0_cnt_t +{ + ZXIC_UINT32 stat_smmu0_fc15_0_cnt; +}DPP_STAT_STAT_CFG_STAT_SMMU0_FC15_0_CNT_T; + +typedef struct dpp_stat_stat_cfg_smmu0_stat_fc15_0_cnt_t +{ + ZXIC_UINT32 smmu0_stat_fc15_0_cnt; +}DPP_STAT_STAT_CFG_SMMU0_STAT_FC15_0_CNT_T; + +typedef struct dpp_stat_stat_cfg_smmu0_stat_rsp15_0_cnt_t +{ + ZXIC_UINT32 smmu0_stat_rsp15_0_cnt; +}DPP_STAT_STAT_CFG_SMMU0_STAT_RSP15_0_CNT_T; + +typedef struct dpp_stat_stat_cfg_stat_smmu0_req15_0_cnt_t +{ + ZXIC_UINT32 stat_smmu0_req15_0_cnt; +}DPP_STAT_STAT_CFG_STAT_SMMU0_REQ15_0_CNT_T; + +typedef struct dpp_stat_stat_cfg_ppu_stat_mec5_0_rsp_fc_cnt_t +{ + ZXIC_UINT32 ppu_stat_mec5_0_rsp_fc_cnt; +}DPP_STAT_STAT_CFG_PPU_STAT_MEC5_0_RSP_FC_CNT_T; + +typedef struct dpp_stat_stat_cfg_stat_ppu_mec5_0_key_fc_cnt_t +{ + ZXIC_UINT32 stat_ppu_mec5_0_key_fc_cnt; +}DPP_STAT_STAT_CFG_STAT_PPU_MEC5_0_KEY_FC_CNT_T; + +typedef struct dpp_stat_stat_cfg_stat_ppu_mec5_0_rsp_cnt_t +{ + ZXIC_UINT32 stat_ppu_mec5_0_rsp_cnt; +}DPP_STAT_STAT_CFG_STAT_PPU_MEC5_0_RSP_CNT_T; + +typedef struct dpp_stat_stat_cfg_ppu_stat_mec5_0_key_cnt_t +{ + ZXIC_UINT32 ppu_stat_mec5_0_key_cnt; +}DPP_STAT_STAT_CFG_PPU_STAT_MEC5_0_KEY_CNT_T; + +typedef struct dpp_stat_stat_cfg_ppu5_0_no_exist_opcd_ex_cnt_t +{ + ZXIC_UINT32 ppu5_0_no_exist_opcd_ex_cnt; +}DPP_STAT_STAT_CFG_PPU5_0_NO_EXIST_OPCD_EX_CNT_T; + +typedef struct dpp_stat_stat_cfg_se_etm_stat_wr_fc_cnt_t +{ + ZXIC_UINT32 se_etm_stat_wr_fc_cnt; +}DPP_STAT_STAT_CFG_SE_ETM_STAT_WR_FC_CNT_T; + +typedef struct dpp_stat_stat_cfg_se_etm_stat_rd_fc_cnt_t +{ + ZXIC_UINT32 se_etm_stat_rd_fc_cnt; +}DPP_STAT_STAT_CFG_SE_ETM_STAT_RD_FC_CNT_T; + +typedef struct dpp_stat_stat_cfg_stat_etm_deq_fc_cnt_t +{ + ZXIC_UINT32 stat_etm_deq_fc_cnt; +}DPP_STAT_STAT_CFG_STAT_ETM_DEQ_FC_CNT_T; + +typedef struct dpp_stat_stat_cfg_stat_etm_enq_fc_cnt_t +{ + ZXIC_UINT32 stat_etm_enq_fc_cnt; +}DPP_STAT_STAT_CFG_STAT_ETM_ENQ_FC_CNT_T; + +typedef struct dpp_stat_stat_cfg_stat_oam_lm_fc_cnt_t +{ + ZXIC_UINT32 stat_oam_lm_fc_cnt; +}DPP_STAT_STAT_CFG_STAT_OAM_LM_FC_CNT_T; + +typedef struct dpp_stat_stat_cfg_oam_stat_lm_fc_cnt_t +{ + ZXIC_UINT32 oam_stat_lm_fc_cnt; +}DPP_STAT_STAT_CFG_OAM_STAT_LM_FC_CNT_T; + +typedef struct dpp_stat_stat_cfg_stat_oam_fc_cnt_t +{ + ZXIC_UINT32 stat_oam_fc_cnt; +}DPP_STAT_STAT_CFG_STAT_OAM_FC_CNT_T; + +typedef struct dpp_stat_stat_cfg_cmmu_stat_fc_cnt_t +{ + ZXIC_UINT32 cmmu_stat_fc_cnt; +}DPP_STAT_STAT_CFG_CMMU_STAT_FC_CNT_T; + +typedef struct dpp_stat_stat_cfg_stat_cmmu_req_cnt_t +{ + ZXIC_UINT32 stat_cmmu_req_cnt; +}DPP_STAT_STAT_CFG_STAT_CMMU_REQ_CNT_T; + +typedef struct dpp_stat_stat_cfg_smmu0_plcr_rsp0_cnt_t +{ + ZXIC_UINT32 smmu0_plcr_rsp0_cnt; +}DPP_STAT_STAT_CFG_SMMU0_PLCR_RSP0_CNT_T; + +typedef struct dpp_stat_stat_cfg_plcr_smmu0_req0_cnt_t +{ + ZXIC_UINT32 plcr_smmu0_req0_cnt; +}DPP_STAT_STAT_CFG_PLCR_SMMU0_REQ0_CNT_T; + +typedef struct dpp_stat_stat_cfg_stat_oam_lm_rsp_cnt_t +{ + ZXIC_UINT32 stat_oam_lm_rsp_cnt; +}DPP_STAT_STAT_CFG_STAT_OAM_LM_RSP_CNT_T; + +typedef struct dpp_stat_stat_cfg_oam_stat_lm_req_cnt_t +{ + ZXIC_UINT32 oam_stat_lm_req_cnt; +}DPP_STAT_STAT_CFG_OAM_STAT_LM_REQ_CNT_T; + +typedef struct dpp_stat_stat_cfg_oam_stat_req_cnt_t +{ + ZXIC_UINT32 oam_stat_req_cnt; +}DPP_STAT_STAT_CFG_OAM_STAT_REQ_CNT_T; + +typedef struct dpp_stat_stat_cfg_se_etm_stat_rsp_cnt_t +{ + ZXIC_UINT32 se_etm_stat_rsp_cnt; +}DPP_STAT_STAT_CFG_SE_ETM_STAT_RSP_CNT_T; + +typedef struct dpp_stat_stat_cfg_etm_stat_se_wr_req_cnt_t +{ + ZXIC_UINT32 etm_stat_se_wr_req_cnt; +}DPP_STAT_STAT_CFG_ETM_STAT_SE_WR_REQ_CNT_T; + +typedef struct dpp_stat_stat_cfg_etm_stat_se_rd_req_cnt_t +{ + ZXIC_UINT32 etm_stat_se_rd_req_cnt; +}DPP_STAT_STAT_CFG_ETM_STAT_SE_RD_REQ_CNT_T; + +typedef struct dpp_stat_stat_cfg_etm_stat_smmu0_req_cnt0_t +{ + ZXIC_UINT32 etm_stat_smmu0_req_cnt0; +}DPP_STAT_STAT_CFG_ETM_STAT_SMMU0_REQ_CNT0_T; + +typedef struct dpp_stat_stat_cfg_etm_stat_smmu0_req_cnt1_t +{ + ZXIC_UINT32 etm_stat_smmu0_req_cnt1; +}DPP_STAT_STAT_CFG_ETM_STAT_SMMU0_REQ_CNT1_T; + +typedef struct dpp_stat_stat_cfg_tm_stat_eram_cpu_rsp_cnt_t +{ + ZXIC_UINT32 tm_stat_eram_cpu_rsp_cnt; +}DPP_STAT_STAT_CFG_TM_STAT_ERAM_CPU_RSP_CNT_T; + +typedef struct dpp_stat_stat_cfg_cpu_rd_eram_req_cnt_t +{ + ZXIC_UINT32 cpu_rd_eram_req_cnt; +}DPP_STAT_STAT_CFG_CPU_RD_ERAM_REQ_CNT_T; + +typedef struct dpp_stat_stat_cfg_cpu_wr_eram_req_cnt_t +{ + ZXIC_UINT32 cpu_wr_eram_req_cnt; +}DPP_STAT_STAT_CFG_CPU_WR_ERAM_REQ_CNT_T; + +typedef struct dpp_stat_stat_cfg_tm_stat_ddr_cpu_rsp_cnt_t +{ + ZXIC_UINT32 tm_stat_ddr_cpu_rsp_cnt; +}DPP_STAT_STAT_CFG_TM_STAT_DDR_CPU_RSP_CNT_T; + +typedef struct dpp_stat_stat_cfg_cpu_rd_ddr_req_cnt_t +{ + ZXIC_UINT32 cpu_rd_ddr_req_cnt; +}DPP_STAT_STAT_CFG_CPU_RD_DDR_REQ_CNT_T; + +typedef struct dpp_stat_stat_cfg_cpu_wr_ddr_req_cnt_t +{ + ZXIC_UINT32 cpu_wr_ddr_req_cnt; +}DPP_STAT_STAT_CFG_CPU_WR_DDR_REQ_CNT_T; + +typedef struct dpp_stat_etcam_cpu_ind_wdat1_t +{ + ZXIC_UINT32 wdat1; +}DPP_STAT_ETCAM_CPU_IND_WDAT1_T; + +typedef struct dpp_stat_etcam_cpu_ind_wdat2_t +{ + ZXIC_UINT32 wdat2; +}DPP_STAT_ETCAM_CPU_IND_WDAT2_T; + +typedef struct dpp_stat_etcam_cpu_ind_wdat3_t +{ + ZXIC_UINT32 wdat3; +}DPP_STAT_ETCAM_CPU_IND_WDAT3_T; + +typedef struct dpp_stat_etcam_cpu_ind_wdat4_t +{ + ZXIC_UINT32 wdat4; +}DPP_STAT_ETCAM_CPU_IND_WDAT4_T; + +typedef struct dpp_stat_etcam_cpu_ind_wdat5_t +{ + ZXIC_UINT32 wdat5; +}DPP_STAT_ETCAM_CPU_IND_WDAT5_T; + +typedef struct dpp_stat_etcam_cpu_ind_wdat6_t +{ + ZXIC_UINT32 wdat6; +}DPP_STAT_ETCAM_CPU_IND_WDAT6_T; + +typedef struct dpp_stat_etcam_cpu_ind_wdat7_t +{ + ZXIC_UINT32 wdat7; +}DPP_STAT_ETCAM_CPU_IND_WDAT7_T; + +typedef struct dpp_stat_etcam_cpu_ind_wdat8_t +{ + ZXIC_UINT32 wdat8; +}DPP_STAT_ETCAM_CPU_IND_WDAT8_T; + +typedef struct dpp_stat_etcam_cpu_ind_wdat9_t +{ + ZXIC_UINT32 wdat9; +}DPP_STAT_ETCAM_CPU_IND_WDAT9_T; + +typedef struct dpp_stat_etcam_cpu_ind_wdat10_t +{ + ZXIC_UINT32 wdat10; +}DPP_STAT_ETCAM_CPU_IND_WDAT10_T; + +typedef struct dpp_stat_etcam_cpu_ind_wdat11_t +{ + ZXIC_UINT32 wdat11; +}DPP_STAT_ETCAM_CPU_IND_WDAT11_T; + +typedef struct dpp_stat_etcam_cpu_ind_wdat12_t +{ + ZXIC_UINT32 wdat12; +}DPP_STAT_ETCAM_CPU_IND_WDAT12_T; + +typedef struct dpp_stat_etcam_cpu_ind_wdat13_t +{ + ZXIC_UINT32 wdat13; +}DPP_STAT_ETCAM_CPU_IND_WDAT13_T; + +typedef struct dpp_stat_etcam_cpu_ind_wdat14_t +{ + ZXIC_UINT32 wdat14; +}DPP_STAT_ETCAM_CPU_IND_WDAT14_T; + +typedef struct dpp_stat_etcam_cpu_ind_wdat15_t +{ + ZXIC_UINT32 wdat15; +}DPP_STAT_ETCAM_CPU_IND_WDAT15_T; + +typedef struct dpp_stat_etcam_cpu_ind_wdat16_t +{ + ZXIC_UINT32 wdat16; +}DPP_STAT_ETCAM_CPU_IND_WDAT16_T; + +typedef struct dpp_stat_etcam_cpu_ind_wdat17_t +{ + ZXIC_UINT32 wdat17; +}DPP_STAT_ETCAM_CPU_IND_WDAT17_T; + +typedef struct dpp_stat_etcam_cpu_ind_wdat18_t +{ + ZXIC_UINT32 wdat18; +}DPP_STAT_ETCAM_CPU_IND_WDAT18_T; + +typedef struct dpp_stat_etcam_cpu_ind_wdat19_t +{ + ZXIC_UINT32 wdat19; +}DPP_STAT_ETCAM_CPU_IND_WDAT19_T; + +typedef struct dpp_stat_etcam_t_strwc_cfg_t +{ + ZXIC_UINT32 t_strwc_cfg; +}DPP_STAT_ETCAM_T_STRWC_CFG_T; + +typedef struct dpp_stat_etcam_etcam_int_unmask_flag_t +{ + ZXIC_UINT32 etcam_int_unmask_flag; +}DPP_STAT_ETCAM_ETCAM_INT_UNMASK_FLAG_T; + +typedef struct dpp_stat_etcam_etcam_int_en0_t +{ + ZXIC_UINT32 etcam_int_en17; + ZXIC_UINT32 etcam_int_en16; + ZXIC_UINT32 etcam_int_en15; + ZXIC_UINT32 etcam_int_en14; + ZXIC_UINT32 etcam_int_en13; + ZXIC_UINT32 etcam_int_en12; + ZXIC_UINT32 etcam_int_en11; + ZXIC_UINT32 etcam_int_en10; + ZXIC_UINT32 etcam_int_en9; + ZXIC_UINT32 etcam_int_en8; + ZXIC_UINT32 etcam_int_en7; + ZXIC_UINT32 etcam_int_en6; + ZXIC_UINT32 etcam_int_en5; + ZXIC_UINT32 etcam_int_en4; + ZXIC_UINT32 etcam_int_en3; + ZXIC_UINT32 etcam_int_en2; + ZXIC_UINT32 etcam_int_en1; + ZXIC_UINT32 etcam_int_en0; +}DPP_STAT_ETCAM_ETCAM_INT_EN0_T; + +typedef struct dpp_stat_etcam_etcam_int_mask0_t +{ + ZXIC_UINT32 etcam_int_mask17; + ZXIC_UINT32 etcam_int_mask16; + ZXIC_UINT32 etcam_int_mask15; + ZXIC_UINT32 etcam_int_mask14; + ZXIC_UINT32 etcam_int_mask13; + ZXIC_UINT32 etcam_int_mask12; + ZXIC_UINT32 etcam_int_mask11; + ZXIC_UINT32 etcam_int_mask10; + ZXIC_UINT32 etcam_int_mask9; + ZXIC_UINT32 etcam_int_mask8; + ZXIC_UINT32 etcam_int_mask7; + ZXIC_UINT32 etcam_int_mask6; + ZXIC_UINT32 etcam_int_mask5; + ZXIC_UINT32 etcam_int_mask4; + ZXIC_UINT32 etcam_int_mask3; + ZXIC_UINT32 etcam_int_mask2; + ZXIC_UINT32 etcam_int_mask1; + ZXIC_UINT32 etcam_int_mask0; +}DPP_STAT_ETCAM_ETCAM_INT_MASK0_T; + +typedef struct dpp_stat_etcam_etcam_int_status_t +{ + ZXIC_UINT32 etcam_int_status17; + ZXIC_UINT32 etcam_int_status16; + ZXIC_UINT32 etcam_int_status15; + ZXIC_UINT32 etcam_int_status14; + ZXIC_UINT32 etcam_int_status13; + ZXIC_UINT32 etcam_int_status12; + ZXIC_UINT32 etcam_int_status11; + ZXIC_UINT32 etcam_int_status10; + ZXIC_UINT32 etcam_int_status9; + ZXIC_UINT32 etcam_int_status8; + ZXIC_UINT32 etcam_int_status7; + ZXIC_UINT32 etcam_int_status6; + ZXIC_UINT32 etcam_int_status5; + ZXIC_UINT32 etcam_int_status4; + ZXIC_UINT32 etcam_int_status3; + ZXIC_UINT32 etcam_int_status2; + ZXIC_UINT32 etcam_int_status1; + ZXIC_UINT32 etcam_int_status0; +}DPP_STAT_ETCAM_ETCAM_INT_STATUS_T; + +typedef struct dpp_stat_etcam_int_tb_ini_ok_t +{ + ZXIC_UINT32 int_tb_ini_ok; +}DPP_STAT_ETCAM_INT_TB_INI_OK_T; + +typedef struct dpp_stat_etcam_etcam_clk_en_t +{ + ZXIC_UINT32 etcam_clk_en; +}DPP_STAT_ETCAM_ETCAM_CLK_EN_T; + +typedef struct dpp_stat_etcam_as_etcam_req0_cnt_t +{ + ZXIC_UINT32 as_etcam_req0_cnt; +}DPP_STAT_ETCAM_AS_ETCAM_REQ0_CNT_T; + +typedef struct dpp_stat_etcam_as_etcam_req1_cnt_t +{ + ZXIC_UINT32 as_etcam_req1_cnt; +}DPP_STAT_ETCAM_AS_ETCAM_REQ1_CNT_T; + +typedef struct dpp_stat_etcam_etcam_as_index0_cnt_t +{ + ZXIC_UINT32 etcam_as_index0_cnt; +}DPP_STAT_ETCAM_ETCAM_AS_INDEX0_CNT_T; + +typedef struct dpp_stat_etcam_etcam_as_index1_cnt_t +{ + ZXIC_UINT32 etcam_as_index1_cnt; +}DPP_STAT_ETCAM_ETCAM_AS_INDEX1_CNT_T; + +typedef struct dpp_stat_etcam_etcam_not_hit0_cnt_t +{ + ZXIC_UINT32 etcam_not_hit0_cnt; +}DPP_STAT_ETCAM_ETCAM_NOT_HIT0_CNT_T; + +typedef struct dpp_stat_etcam_etcam_not_hit1_cnt_t +{ + ZXIC_UINT32 etcam_not_hit1_cnt; +}DPP_STAT_ETCAM_ETCAM_NOT_HIT1_CNT_T; + +typedef struct dpp_stat_etcam_table_id_not_match_cnt_t +{ + ZXIC_UINT32 table_id_not_match_cnt; +}DPP_STAT_ETCAM_TABLE_ID_NOT_MATCH_CNT_T; + +typedef struct dpp_stat_etcam_table_id_clash01_cnt_t +{ + ZXIC_UINT32 table_id_clash01_cnt; +}DPP_STAT_ETCAM_TABLE_ID_CLASH01_CNT_T; + +typedef struct dpp_stat_etcam_etcam_cpu_fl_t +{ + ZXIC_UINT32 etcam_cpu_fl; +}DPP_STAT_ETCAM_ETCAM_CPU_FL_T; + +typedef struct dpp_stat_etcam_etcam_arb_empty_t +{ + ZXIC_UINT32 etcam_arb_empty; +}DPP_STAT_ETCAM_ETCAM_ARB_EMPTY_T; + + +#ifdef __cplusplus +} +#endif +#endif + diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_trpg_reg.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_trpg_reg.h new file mode 100644 index 0000000..aaed025 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_trpg_reg.h @@ -0,0 +1,344 @@ + +#ifndef _DPP_TRPG_REG_H_ +#define _DPP_TRPG_REG_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +typedef struct dpp_trpg_trpg_rx_port_cpu_trpg_ms_en_t +{ + ZXIC_UINT32 cpu_trpgrx_ms_en; +}DPP_TRPG_TRPG_RX_PORT_CPU_TRPG_MS_EN_T; + +typedef struct dpp_trpg_trpg_rx_port_cpu_trpg_port_en_t +{ + ZXIC_UINT32 cpu_trpgrx_port_en; +}DPP_TRPG_TRPG_RX_PORT_CPU_TRPG_PORT_EN_T; + +typedef struct dpp_trpg_trpg_rx_port_cpu_trpg_look_en_t +{ + ZXIC_UINT32 cpu_trpgrx_look_en; +}DPP_TRPG_TRPG_RX_PORT_CPU_TRPG_LOOK_EN_T; + +typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_ram_almost_full_t +{ + ZXIC_UINT32 cpu_trpgrx_ram_almost_full; +}DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_RAM_ALMOST_FULL_T; + +typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_ram_test_en_t +{ + ZXIC_UINT32 cpu_trpgrx_ram_test_en; +}DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_RAM_TEST_EN_T; + +typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_inmod_pfc_rdy_en_t +{ + ZXIC_UINT32 cpu_trpgrx_inmod_pfc_rdy_en; +}DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_INMOD_PFC_RDY_EN_T; + +typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_pkt_num_h_t +{ + ZXIC_UINT32 cpu_trpgrx_pkt_num_h; +}DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_NUM_H_T; + +typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_pkt_num_l_t +{ + ZXIC_UINT32 cpu_trpgrx_pkt_num_l; +}DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_NUM_L_T; + +typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_pkt_byte_num_h_t +{ + ZXIC_UINT32 cpu_trpgrx_pkt_byte_num_h; +}DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_BYTE_NUM_H_T; + +typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_pkt_byte_num_l_t +{ + ZXIC_UINT32 cpu_trpgrx_pkt_byte_num_l; +}DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_BYTE_NUM_L_T; + +typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_pkt_cnt_clr_t +{ + ZXIC_UINT32 cpu_trpgrx_pkt_cnt_clr; +}DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_CNT_CLR_T; + +typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_fc_clk_freq_t +{ + ZXIC_UINT32 cpu_trpgrx_fc_clk_freq; +}DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_FC_CLK_FREQ_T; + +typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_fc_en_t +{ + ZXIC_UINT32 cpu_trpgrx_fc_en; +}DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_FC_EN_T; + +typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_fc_token_add_num_t +{ + ZXIC_UINT32 cpu_trpgrx_fc_token_add_num; +}DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_FC_TOKEN_ADD_NUM_T; + +typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_fc_token_max_num_t +{ + ZXIC_UINT32 cpu_trpgrx_fc_token_max_num; +}DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_FC_TOKEN_MAX_NUM_T; + +typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_port_state_info_t +{ + ZXIC_UINT32 cpu_trpgrx_port_state_info; +}DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_PORT_STATE_INFO_T; + +typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_ram_past_max_dep_t +{ + ZXIC_UINT32 cpu_trpgrx_ram_past_max_dep; +}DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_RAM_PAST_MAX_DEP_T; + +typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_ram_past_max_dep_clr_t +{ + ZXIC_UINT32 cpu_trpgrx_ram_past_max_dep_clr; +}DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_RAM_PAST_MAX_DEP_CLR_T; + +typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_pkt_past_max_len_t +{ + ZXIC_UINT32 cpu_trpgrx_pkt_past_max_len; +}DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_PAST_MAX_LEN_T; + +typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_pkt_past_max_len_clr_t +{ + ZXIC_UINT32 cpu_trpgrx_pkt_past_max_len_clr; +}DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_PAST_MAX_LEN_CLR_T; + +typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_pkt_past_min_len_t +{ + ZXIC_UINT32 cpu_trpgrx_pkt_past_min_len; +}DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_PAST_MIN_LEN_T; + +typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_pkt_past_min_len_clr_t +{ + ZXIC_UINT32 cpu_trpgrx_pkt_past_min_len_clr; +}DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_PAST_MIN_LEN_CLR_T; + +typedef struct dpp_trpg_trpg_rx_ram_trpg_rx_data_ram_t +{ + ZXIC_UINT32 trpg_rx_data_ram; +}DPP_TRPG_TRPG_RX_RAM_TRPG_RX_DATA_RAM_T; + +typedef struct dpp_trpg_trpg_rx_ram_trpg_rx_info_ram_t +{ + ZXIC_UINT32 trpg_rx_info_ram; +}DPP_TRPG_TRPG_RX_RAM_TRPG_RX_INFO_RAM_T; + +typedef struct dpp_trpg_trpg_tx_port_cpu_trpg_ms_en_t +{ + ZXIC_UINT32 cpu_trpgtx_ms_en; +}DPP_TRPG_TRPG_TX_PORT_CPU_TRPG_MS_EN_T; + +typedef struct dpp_trpg_trpg_tx_port_cpu_trpg_port_en_t +{ + ZXIC_UINT32 cpu_trpgtx_port_en; +}DPP_TRPG_TRPG_TX_PORT_CPU_TRPG_PORT_EN_T; + +typedef struct dpp_trpg_trpg_tx_port_cpu_trpg_look_en_t +{ + ZXIC_UINT32 cpu_trpgtx_look_en; +}DPP_TRPG_TRPG_TX_PORT_CPU_TRPG_LOOK_EN_T; + +typedef struct dpp_trpg_trpg_tx_port_cpu_trpgtx_ram_almost_full_t +{ + ZXIC_UINT32 cpu_trpgtx_ram_almost_full; +}DPP_TRPG_TRPG_TX_PORT_CPU_TRPGTX_RAM_ALMOST_FULL_T; + +typedef struct dpp_trpg_trpg_tx_port_cpu_trpgtx_ram_test_en_t +{ + ZXIC_UINT32 cpu_trpgtx_ram_test_en; +}DPP_TRPG_TRPG_TX_PORT_CPU_TRPGTX_RAM_TEST_EN_T; + +typedef struct dpp_trpg_trpg_tx_port_cpu_trpgtx_pkt_num_h_t +{ + ZXIC_UINT32 cpu_trpgtx_pkt_num_h; +}DPP_TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_NUM_H_T; + +typedef struct dpp_trpg_trpg_tx_port_cpu_trpgtx_pkt_num_l_t +{ + ZXIC_UINT32 cpu_trpgtx_pkt_num_l; +}DPP_TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_NUM_L_T; + +typedef struct dpp_trpg_trpg_tx_port_cpu_trpgtx_pkt_byte_num_h_t +{ + ZXIC_UINT32 cpu_trpgtx_pkt_byte_num_h; +}DPP_TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_BYTE_NUM_H_T; + +typedef struct dpp_trpg_trpg_tx_port_cpu_trpgtx_pkt_byte_num_l_t +{ + ZXIC_UINT32 cpu_trpgtx_pkt_byte_num_l; +}DPP_TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_BYTE_NUM_L_T; + +typedef struct dpp_trpg_trpg_tx_port_cpu_trpgtx_pkt_cnt_clr_t +{ + ZXIC_UINT32 cpu_trpgtx_pkt_cnt_clr; +}DPP_TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_CNT_CLR_T; + +typedef struct dpp_trpg_trpg_tx_port_cpu_trpgtx_fc_clk_freq_t +{ + ZXIC_UINT32 cpu_trpgtx_fc_clk_freq; +}DPP_TRPG_TRPG_TX_PORT_CPU_TRPGTX_FC_CLK_FREQ_T; + +typedef struct dpp_trpg_trpg_tx_port_cpu_trpgtx_fc_en_t +{ + ZXIC_UINT32 cpu_trpgtx_fc_en; +}DPP_TRPG_TRPG_TX_PORT_CPU_TRPGTX_FC_EN_T; + +typedef struct dpp_trpg_trpg_tx_port_cpu_trpgtx_fc_token_add_num_t +{ + ZXIC_UINT32 cpu_trpgtx_fc_token_add_num; +}DPP_TRPG_TRPG_TX_PORT_CPU_TRPGTX_FC_TOKEN_ADD_NUM_T; + +typedef struct dpp_trpg_trpg_tx_port_cpu_trpgtx_fc_token_max_num_t +{ + ZXIC_UINT32 cpu_trpgtx_fc_token_max_num; +}DPP_TRPG_TRPG_TX_PORT_CPU_TRPGTX_FC_TOKEN_MAX_NUM_T; + +typedef struct dpp_trpg_trpg_tx_port_cpu_trpgtx_port_state_info_t +{ + ZXIC_UINT32 cpu_trpgtx_port_state_info; +}DPP_TRPG_TRPG_TX_PORT_CPU_TRPGTX_PORT_STATE_INFO_T; + +typedef struct dpp_trpg_trpg_tx_port_cpu_trpgtx_ram_past_max_dep_t +{ + ZXIC_UINT32 cpu_trpgtx_ram_past_max_dep; +}DPP_TRPG_TRPG_TX_PORT_CPU_TRPGTX_RAM_PAST_MAX_DEP_T; + +typedef struct dpp_trpg_trpg_tx_port_cpu_trpgtx_ram_past_max_dep_clr_t +{ + ZXIC_UINT32 cpu_trpgtx_ram_past_max_dep_clr; +}DPP_TRPG_TRPG_TX_PORT_CPU_TRPGTX_RAM_PAST_MAX_DEP_CLR_T; + +typedef struct dpp_trpg_trpg_tx_port_cpu_trpgtx_pkt_past_max_len_t +{ + ZXIC_UINT32 cpu_trpgtx_pkt_past_max_len; +}DPP_TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_PAST_MAX_LEN_T; + +typedef struct dpp_trpg_trpg_tx_port_cpu_trpgtx_pkt_past_max_len_clr_t +{ + ZXIC_UINT32 cpu_trpgtx_pkt_past_max_len_clr; +}DPP_TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_PAST_MAX_LEN_CLR_T; + +typedef struct dpp_trpg_trpg_tx_port_cpu_trpgtx_pkt_past_min_len_t +{ + ZXIC_UINT32 cpu_trpgtx_pkt_past_min_len; +}DPP_TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_PAST_MIN_LEN_T; + +typedef struct dpp_trpg_trpg_tx_port_cpu_trpgtx_pkt_past_min_len_clr_t +{ + ZXIC_UINT32 cpu_trpgtx_pkt_past_min_len_clr; +}DPP_TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_PAST_MIN_LEN_CLR_T; + +typedef struct dpp_trpg_trpg_tx_etm_port_cpu_trpgtx_etm_ram_almost_full_t +{ + ZXIC_UINT32 cpu_trpgtx_etm_ram_almost_full; +}DPP_TRPG_TRPG_TX_ETM_PORT_CPU_TRPGTX_ETM_RAM_ALMOST_FULL_T; + +typedef struct dpp_trpg_trpg_tx_etm_port_cpu_trpgtx_etm_ram_test_en_t +{ + ZXIC_UINT32 cpu_trpgtx_etm_ram_test_en; +}DPP_TRPG_TRPG_TX_ETM_PORT_CPU_TRPGTX_ETM_RAM_TEST_EN_T; + +typedef struct dpp_trpg_trpg_tx_glb_cpu_todtime_update_int_mask_t +{ + ZXIC_UINT32 cpu_todtime_update_int_mask; +}DPP_TRPG_TRPG_TX_GLB_CPU_TODTIME_UPDATE_INT_MASK_T; + +typedef struct dpp_trpg_trpg_tx_glb_cpu_todtime_update_int_clr_t +{ + ZXIC_UINT32 cpu_todtime_update_int_clr; +}DPP_TRPG_TRPG_TX_GLB_CPU_TODTIME_UPDATE_INT_CLR_T; + +typedef struct dpp_trpg_trpg_tx_glb_cpu_todtime_ram_test_en_t +{ + ZXIC_UINT32 cpu_todtime_ram_test_en; +}DPP_TRPG_TRPG_TX_GLB_CPU_TODTIME_RAM_TEST_EN_T; + +typedef struct dpp_trpg_trpg_tx_ram_trpg_tx_data_ram_t +{ + ZXIC_UINT32 trpg_tx_data_ram; +}DPP_TRPG_TRPG_TX_RAM_TRPG_TX_DATA_RAM_T; + +typedef struct dpp_trpg_trpg_tx_ram_trpg_tx_info_ram_t +{ + ZXIC_UINT32 trpg_tx_info_ram; +}DPP_TRPG_TRPG_TX_RAM_TRPG_TX_INFO_RAM_T; + +typedef struct dpp_trpg_trpg_tx_etm_ram_trpg_tx_etm_data_ram_t +{ + ZXIC_UINT32 trpg_tx_etm_data_ram; +}DPP_TRPG_TRPG_TX_ETM_RAM_TRPG_TX_ETM_DATA_RAM_T; + +typedef struct dpp_trpg_trpg_tx_etm_ram_trpg_tx_etm_info_ram_t +{ + ZXIC_UINT32 trpg_tx_etm_info_ram; +}DPP_TRPG_TRPG_TX_ETM_RAM_TRPG_TX_ETM_INFO_RAM_T; + +typedef struct dpp_trpg_trpg_rx_port_cpu_trpg_ms_st_t +{ + ZXIC_UINT32 cpu_trpgrx_ms_st; +}DPP_TRPG_TRPG_RX_PORT_CPU_TRPG_MS_ST_T; + +typedef struct dpp_trpg_trpg_rx_port_cpu_trpg_ms_ind_t +{ + ZXIC_UINT32 cpu_trpgrx_ms_ind; +}DPP_TRPG_TRPG_RX_PORT_CPU_TRPG_MS_IND_T; + +typedef struct dpp_trpg_trpg_rx_port_cpu_trpg_ms_slave_ind_t +{ + ZXIC_UINT32 cpu_trpgrx_ms_slave_ind; +}DPP_TRPG_TRPG_RX_PORT_CPU_TRPG_MS_SLAVE_IND_T; + +typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_up_water_level_t +{ + ZXIC_UINT32 cpu_trpgrx_up_water_level; +}DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_UP_WATER_LEVEL_T; + +typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_low_water_level_t +{ + ZXIC_UINT32 cpu_trpgrx_low_water_level; +}DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_LOW_WATER_LEVEL_T; + +typedef struct dpp_trpg_trpg_tx_port_cpu_trpg_ms_st_t +{ + ZXIC_UINT32 cpu_trpgtx_ms_st; +}DPP_TRPG_TRPG_TX_PORT_CPU_TRPG_MS_ST_T; + +typedef struct dpp_trpg_trpg_tx_port_cpu_trpg_ms_ind_t +{ + ZXIC_UINT32 cpu_trpgtx_ms_ind; +}DPP_TRPG_TRPG_TX_PORT_CPU_TRPG_MS_IND_T; + +typedef struct dpp_trpg_trpg_tx_port_cpu_trpg_ms_slave_ind_t +{ + ZXIC_UINT32 cpu_trpgtx_ms_slave_ind; +}DPP_TRPG_TRPG_TX_PORT_CPU_TRPG_MS_SLAVE_IND_T; + +typedef struct dpp_trpg_trpg_tx_glb_cpu_todtime_update_int_event_t +{ + ZXIC_UINT32 cpu_todtime_update_int_event; +}DPP_TRPG_TRPG_TX_GLB_CPU_TODTIME_UPDATE_INT_EVENT_T; + +typedef struct dpp_trpg_trpg_tx_glb_cpu_todtime_update_int_test_t +{ + ZXIC_UINT32 cpu_todtime_update_int_test; +}DPP_TRPG_TRPG_TX_GLB_CPU_TODTIME_UPDATE_INT_TEST_T; + +typedef struct dpp_trpg_trpg_tx_glb_cpu_todtime_update_int_addr_t +{ + ZXIC_UINT32 cpu_todtime_update_int_addr; +}DPP_TRPG_TRPG_TX_GLB_CPU_TODTIME_UPDATE_INT_ADDR_T; + +typedef struct dpp_trpg_trpg_tx_todtime_ram_trpg_tx_todtime_ram_t +{ + ZXIC_UINT32 trpg_tx_todtime_ram; +}DPP_TRPG_TRPG_TX_TODTIME_RAM_TRPG_TX_TODTIME_RAM_T; + + +#ifdef __cplusplus +} +#endif +#endif + diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_tsn_reg.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_tsn_reg.h new file mode 100644 index 0000000..2fc6542 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_tsn_reg.h @@ -0,0 +1,124 @@ + +#ifndef _DPP_TSN_REG_H_ +#define _DPP_TSN_REG_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +typedef struct dpp_tsn_tsn_port_cfg_tsn_test_reg_t +{ + ZXIC_UINT32 cfg_tsn_test_reg; +}DPP_TSN_TSN_PORT_CFG_TSN_TEST_REG_T; + +typedef struct dpp_tsn_tsn_port_cfg_tsn_port_qbv_enable_t +{ + ZXIC_UINT32 cfg_tsn_port_qbv_enable; +}DPP_TSN_TSN_PORT_CFG_TSN_PORT_QBV_ENABLE_T; + +typedef struct dpp_tsn_tsn_port_cfg_tsn_phy_port_sel_t +{ + ZXIC_UINT32 cfg_tsn_phy_port_sel; +}DPP_TSN_TSN_PORT_CFG_TSN_PHY_PORT_SEL_T; + +typedef struct dpp_tsn_tsn_port_cfg_tsn_port_time_sel_t +{ + ZXIC_UINT32 cfg_tsn_port_time_sel; +}DPP_TSN_TSN_PORT_CFG_TSN_PORT_TIME_SEL_T; + +typedef struct dpp_tsn_tsn_port_cfg_tsn_clk_freq_t +{ + ZXIC_UINT32 en; + ZXIC_UINT32 cfg_tsn_clk_freq; +}DPP_TSN_TSN_PORT_CFG_TSN_CLK_FREQ_T; + +typedef struct dpp_tsn_tsn_port_cfg_tsn_read_ram_n_t +{ + ZXIC_UINT32 cfg_tsn_data; + ZXIC_UINT32 cfg_tsn_read_status; + ZXIC_UINT32 cfg_tsn_read_ram_n; +}DPP_TSN_TSN_PORT_CFG_TSN_READ_RAM_N_T; + +typedef struct dpp_tsn_tsn_port_cfg_tsn_exe_time_t +{ + ZXIC_UINT32 cfg_tsn_exe_time; +}DPP_TSN_TSN_PORT_CFG_TSN_EXE_TIME_T; + +typedef struct dpp_tsn_tsn_port_cfg_tsn_port_itr_shift_t +{ + ZXIC_UINT32 cfg_tsn_port_itr_shift; +}DPP_TSN_TSN_PORT_CFG_TSN_PORT_ITR_SHIFT_T; + +typedef struct dpp_tsn_tsn_port_cfg_tsn_port_base_time_h_t +{ + ZXIC_UINT32 cfg_tsn_port_base_time_h; +}DPP_TSN_TSN_PORT_CFG_TSN_PORT_BASE_TIME_H_T; + +typedef struct dpp_tsn_tsn_port_cfg_tsn_port_base_time_l_t +{ + ZXIC_UINT32 cfg_tsn_port_base_time_l; +}DPP_TSN_TSN_PORT_CFG_TSN_PORT_BASE_TIME_L_T; + +typedef struct dpp_tsn_tsn_port_cfg_tsn_port_cycle_time_h_t +{ + ZXIC_UINT32 cfg_tsn_port_cycle_time_h; +}DPP_TSN_TSN_PORT_CFG_TSN_PORT_CYCLE_TIME_H_T; + +typedef struct dpp_tsn_tsn_port_cfg_tsn_port_cycle_time_l_t +{ + ZXIC_UINT32 cfg_tsn_port_cycle_time_l; +}DPP_TSN_TSN_PORT_CFG_TSN_PORT_CYCLE_TIME_L_T; + +typedef struct dpp_tsn_tsn_port_cfg_tsn_port_guard_band_time_t +{ + ZXIC_UINT32 cfg_tsn_port_guard_band_time; +}DPP_TSN_TSN_PORT_CFG_TSN_PORT_GUARD_BAND_TIME_T; + +typedef struct dpp_tsn_tsn_port_cfg_tsn_port_default_gate_en_t +{ + ZXIC_UINT32 cfg_tsn_port_default_gate_en; +}DPP_TSN_TSN_PORT_CFG_TSN_PORT_DEFAULT_GATE_EN_T; + +typedef struct dpp_tsn_tsn_port_cfg_tsn_port_change_gate_en_t +{ + ZXIC_UINT32 cfg_tsn_port_change_gate_en; +}DPP_TSN_TSN_PORT_CFG_TSN_PORT_CHANGE_GATE_EN_T; + +typedef struct dpp_tsn_tsn_port_cfg_tsn_port_init_finish_t +{ + ZXIC_UINT32 cfg_tsn_port_init_finish; +}DPP_TSN_TSN_PORT_CFG_TSN_PORT_INIT_FINISH_T; + +typedef struct dpp_tsn_tsn_port_cfg_tsn_port_change_en_t +{ + ZXIC_UINT32 cfg_tsn_port_change_en; +}DPP_TSN_TSN_PORT_CFG_TSN_PORT_CHANGE_EN_T; + +typedef struct dpp_tsn_tsn_port_cfg_tsn_port_gcl_num0_t +{ + ZXIC_UINT32 cfg_tsn_port_gcl_num0; +}DPP_TSN_TSN_PORT_CFG_TSN_PORT_GCL_NUM0_T; + +typedef struct dpp_tsn_tsn_port_cfg_tsn_port_gcl_num1_t +{ + ZXIC_UINT32 cfg_tsn_port_gcl_num1; +}DPP_TSN_TSN_PORT_CFG_TSN_PORT_GCL_NUM1_T; + +typedef struct dpp_tsn_tsn_port_cfg_tsn_port_gcl_value0_t +{ + ZXIC_UINT32 cfg_tsn_port_gcl_gate_control0; + ZXIC_UINT32 cfg_tsn_port_gcl_interval_time0; +}DPP_TSN_TSN_PORT_CFG_TSN_PORT_GCL_VALUE0_T; + +typedef struct dpp_tsn_tsn_port_cfg_tsn_port_gcl_value1_t +{ + ZXIC_UINT32 cfg_tsn_port_gcl_gate_control1; + ZXIC_UINT32 cfg_tsn_port_gcl_interval_time1; +}DPP_TSN_TSN_PORT_CFG_TSN_PORT_GCL_VALUE1_T; + + +#ifdef __cplusplus +} +#endif +#endif + diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/diag/dpp_se_diag.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/diag/dpp_se_diag.h new file mode 100755 index 0000000..b6dd469 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/diag/dpp_se_diag.h @@ -0,0 +1,37 @@ +/************************************************************** +* Ȩ (C)2013-2015, ͨѶɷ޹˾ +* ļ : dpp_se_diag.h +* ļʶ : +* ժҪ : +* ˵ : +* ǰ汾 : +* : XXX +* : 2016/01/14 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* ޸ļ¼1: +* ޸: +* : +* : +* ޸: +***************************************************************/ +#ifndef _DPP_SE_DIAG_H_ +#define _DPP_SE_DIAG_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum diag_dpp_etcam_no_as_rsp_mode_e +{ + DPP_ETCAM_NO_AS_RSP_MODE_32 = 0, + DPP_ETCAM_NO_AS_RSP_MODE_64 = 1, + DPP_ETCAM_NO_AS_RSP_MODE_128 = 2, +} DPP_DIAG_ETCAM_NO_AS_RSP_MODE_E; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/Kbuild.include b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/Kbuild.include new file mode 100644 index 0000000..dd81488 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/Kbuild.include @@ -0,0 +1,4 @@ +cur_dir := en_np/sdk/source/ +subdirs := dev/ +src_files += +include $(foreach subdir, $(subdirs), $(dinghai_root)/$(cur_dir)$(subdir)/Kbuild.include) \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/Kbuild.include b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/Kbuild.include new file mode 100644 index 0000000..dac9db1 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/Kbuild.include @@ -0,0 +1,4 @@ +cur_dir := en_np/sdk/source/dev/ +subdirs := reg/ module/ chip/ init/ +src_files += +include $(foreach subdir, $(subdirs), $(dinghai_root)/$(cur_dir)$(subdir)/Kbuild.include) \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/chip/Kbuild.include b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/chip/Kbuild.include new file mode 100644 index 0000000..2025bb7 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/chip/Kbuild.include @@ -0,0 +1,2 @@ +cur_dir := en_np/sdk/source/dev/chip/ +src_files += $(addprefix $(cur_dir),$(notdir $(wildcard $(dinghai_root)/$(cur_dir)*.c))) \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/chip/dpp_dev.c b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/chip/dpp_dev.c new file mode 100755 index 0000000..95155dc --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/chip/dpp_dev.c @@ -0,0 +1,1083 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_dev.c +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : 王春雷 +* 完成日期 : 2014/02/10 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: 代码规范性修改 +* 修改日期: 2014/02/10 +* 版 本 号: +* 修 改 人: 丁金凤 +* 修改内容: +***************************************************************/ + +#include "zxic_common.h" +#include "dpp_module.h" +#include "dpp_pci.h" +#include "dpp_dev.h" +#include "dpp_type_api.h" +#include "dh_cmd.h" + +static DPP_DEV_MGR_T g_dev_mgr = {0}; + +#define DPP_DEV_INFO_GET(id) (g_dev_mgr.p_dev_array[id]) + +/***********************************************************/ +/** 初始化设备管理模块 +* @param ZXIC_VOID +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author 王春雷 @date 2015/03/06 +************************************************************/ +DPP_STATUS dpp_dev_init(ZXIC_VOID) +{ + if (g_dev_mgr.is_init) + { + ZXIC_COMM_TRACE_ERROR("Dev is already initialized.\n"); + return DPP_OK; + } + + g_dev_mgr.device_num = 0; + g_dev_mgr.is_init = 1; + + return DPP_OK; +} + +/***********************************************************/ +/** +* @return +* @remark 无 +* @see +* @author XXX @date 2014/02/14 +************************************************************/ +DPP_DEV_MGR_T *dpp_dev_mgr_get(ZXIC_VOID) +{ + if (!g_dev_mgr.is_init) + { + ZXIC_COMM_TRACE_ERROR("Error: dev_mgr is not init.\n"); + ZXIC_COMM_ASSERT(0); + return NULL; + } + + return &g_dev_mgr; +} + +/***********************************************************/ +/** 添加新设备实例，并初始化 +* @param dev_id 新增设备的设备号 +* @param dev_type 设备类型，取值参照DPP_DEV_TYPE_E的定义 +* @param access_type 设备访问类型，取值参照DPP_DEV_ACCESS_TYPE_E的定义 +* @param pcie_addr PCIe映射地址 +* @param riscv_addr RISCV映射地址 +* @param dma_vir_addr DMA映射地址 +* @param dma_phy_addr DMA内存物理地址 +* @param p_pcie_write_fun PCIe硬件写回调函数 +* @param p_pcie_read_fun PCIe硬件读回调函数 +* @param p_riscv_write_fun RISCV硬件写回调函数 +* @param p_riscv_read_fun RISCV硬件读回调函数 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author 王春雷 @date 2015/03/06 +************************************************************/ +DPP_STATUS dpp_dev_add(ZXIC_UINT32 dev_id, + DPP_DEV_TYPE_E dev_type, + DPP_DEV_ACCESS_TYPE_E access_type, + ZXIC_ADDR_T pcie_addr, + ZXIC_ADDR_T riscv_addr, + ZXIC_ADDR_T dma_vir_addr, + ZXIC_ADDR_T dma_phy_addr, + DPP_DEV_WRITE_FUNC p_pcie_write_fun, + DPP_DEV_READ_FUNC p_pcie_read_fun, + DPP_DEV_WRITE_FUNC p_riscv_write_fun, + DPP_DEV_READ_FUNC p_riscv_read_fun) +{ + DPP_STATUS rtn = DPP_OK; + DPP_DEV_CFG_T *p_dev_info = NULL; + DPP_DEV_MGR_T *p_dev_mgr = NULL; + ZXIC_UINT32 i = 0; + + ZXIC_COMM_CHECK_INDEX_UPPER(dev_id,DPP_DEV_CHANNEL_MAX - 1); + + p_dev_mgr = dpp_dev_mgr_get(); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_dev_mgr); + if (!p_dev_mgr->is_init) + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "ErrorCode[ 0x%x]: Device Manager is not init!!!\n", + DPP_RC_DEV_MGR_NOT_INIT); + return DPP_RC_DEV_MGR_NOT_INIT; + } + + if (p_dev_mgr->p_dev_array[dev_id] != NULL) + { + /* device is already exist. */ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "Device is added again!!!\n"); + p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + } + else + { + /* device is new. */ + p_dev_info = (DPP_DEV_CFG_T *)ZXIC_COMM_MALLOC(sizeof(DPP_DEV_CFG_T)); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_dev_info); + p_dev_mgr->p_dev_array[dev_id] = p_dev_info; + p_dev_mgr->device_num++; + } + + p_dev_info->device_id = dev_id; + p_dev_info->dev_type = dev_type; + p_dev_info->access_type = access_type; + p_dev_info->pcie_addr = pcie_addr; + p_dev_info->riscv_addr = riscv_addr; + p_dev_info->dma_vir_addr = dma_vir_addr; + p_dev_info->dma_phy_addr = dma_phy_addr; + p_dev_info->p_riscv_write_fun = NULL; + p_dev_info->p_riscv_read_fun = NULL; + p_dev_info->p_pcie_write_fun = dpp_dev_pcie_default_write; + p_dev_info->p_pcie_read_fun = dpp_dev_pcie_default_read; + + if(p_riscv_write_fun) + { + p_dev_info->p_riscv_write_fun = p_riscv_write_fun; + } + + if(p_riscv_read_fun) + { + p_dev_info->p_riscv_read_fun = p_riscv_read_fun; + } + + if (p_pcie_write_fun) + { + p_dev_info->p_pcie_write_fun = p_pcie_write_fun; + } + + if (p_pcie_read_fun) + { + p_dev_info->p_pcie_read_fun = p_pcie_read_fun; + } + + if (dev_type == DPP_DEV_TYPE_CHIP) + { + p_dev_info->chip_ver = dpp_dev_chip_version_get(dev_id); + } + else if ((dev_type == DPP_DEV_TYPE_SIM) || (dev_type == DPP_DEV_TYPE_VCS)) + { + //p_dev_info->chip_ver = dpp_vpci_get_chip_version(); + } + + ZXIC_COMM_MEMSET(p_dev_info->pcie_channel, 0x00, sizeof(p_dev_info->pcie_channel)); + + rtn = zxic_comm_mutex_create(&p_dev_info->reg_opr_mutex); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_create"); + + rtn = zxic_comm_mutex_create(&p_dev_info->oam_mutex); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_create"); + + rtn = zxic_comm_mutex_create(&p_dev_info->etm_mutex); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_create"); + + rtn = zxic_comm_mutex_create(&p_dev_info->ddr_mutex); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_create"); + + rtn = zxic_comm_mutex_create(&p_dev_info->ind_mutex); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_create"); + + rtn = zxic_comm_mutex_create(&p_dev_info->etcam_mutex); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_create"); + + rtn = zxic_comm_mutex_create(&p_dev_info->car0_mutex); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_create"); + + rtn = zxic_comm_mutex_create(&p_dev_info->alg_mutex); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_create"); + + rtn = zxic_comm_mutex_create(&p_dev_info->nppu_mutex); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_create"); + + rtn = zxic_comm_mutex_create(&p_dev_info->smmu0_mutex); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_create"); + + rtn = zxic_comm_mutex_create(&p_dev_info->smmu1_mutex); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_create"); + + rtn = zxic_comm_mutex_create(&p_dev_info->etm_2nd_mutex); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_create"); + + rtn = zxic_comm_mutex_create(&p_dev_info->lpm_mutex); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_create"); + + rtn = zxic_comm_mutex_create(&p_dev_info->crm_temp_mutex); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_create"); + + rtn = zxic_comm_mutex_create(&p_dev_info->sim_mutex); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_create"); + + rtn = zxic_comm_mutex_create(&p_dev_info->dtb_mutex); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_create"); + + for (i = 0; i < DPP_DTB_QUEUE_MAX; i++) + { + rtn = zxic_comm_mutex_create(&p_dev_info->dtb_queue_mutex[i]); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_create"); + } + + return DPP_OK; +} + +/***********************************************************/ +/** 删除设备实例 +* @param dev_id 设备号 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author 王春雷 @date 2015/05/20 +************************************************************/ +DPP_STATUS dpp_dev_del(ZXIC_UINT32 dev_id) +{ + DPP_STATUS rtn = DPP_OK; + DPP_DEV_CFG_T *p_dev_info = NULL; + DPP_DEV_MGR_T *p_dev_mgr = NULL; + + ZXIC_COMM_CHECK_INDEX_UPPER(dev_id,DPP_DEV_CHANNEL_MAX - 1); + + p_dev_mgr = dpp_dev_mgr_get(); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_dev_mgr); + p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + + if (p_dev_info != NULL) + { + rtn = zxic_comm_mutex_destroy(&p_dev_info->reg_opr_mutex); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_destroy"); + + rtn = zxic_comm_mutex_destroy(&p_dev_info->oam_mutex); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_destroy"); + + rtn = zxic_comm_mutex_destroy(&p_dev_info->etm_mutex); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_destroy"); + + rtn = zxic_comm_mutex_destroy(&p_dev_info->ddr_mutex); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_destroy"); + + rtn = zxic_comm_mutex_destroy(&p_dev_info->ind_mutex); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_destroy"); + + rtn = zxic_comm_mutex_destroy(&p_dev_info->etcam_mutex); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_destroy"); + + rtn = zxic_comm_mutex_destroy(&p_dev_info->car0_mutex); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_destroy"); + + rtn = zxic_comm_mutex_destroy(&p_dev_info->alg_mutex); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_destroy"); + + rtn = zxic_comm_mutex_destroy(&p_dev_info->nppu_mutex); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_destroy"); + + rtn = zxic_comm_mutex_destroy(&p_dev_info->smmu0_mutex); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_destroy"); + + rtn = zxic_comm_mutex_destroy(&p_dev_info->smmu1_mutex); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_destroy"); + + rtn = zxic_comm_mutex_destroy(&p_dev_info->etm_2nd_mutex); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_destroy"); + + rtn = zxic_comm_mutex_destroy(&p_dev_info->lpm_mutex); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_destroy"); + + rtn = zxic_comm_mutex_destroy(&p_dev_info->crm_temp_mutex); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_destroy"); + + + ZXIC_COMM_FREE(p_dev_info); + p_dev_mgr->p_dev_array[dev_id] = NULL; + ZXIC_COMM_CHECK_DEV_INDEX_SUB_OVERFLOW_NO_ASSERT(dev_id, p_dev_mgr->device_num, 1); + p_dev_mgr->device_num--; + } + + return DPP_OK; +} + +/***********************************************************/ +/** 获取 DPP_DEV_T +* @param dev_id +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author 王春雷 @date 2015/05/20 +************************************************************/ +DPP_STATUS dpp_dev_get(ZXIC_UINT32 dev_id, DPP_PF_INFO_T* pf_info, DPP_DEV_T *dev) +{ + ZXIC_UINT16 slot = 0; + ZXIC_UINT16 channel_id = 0; + + DPP_DEV_CFG_T *p_dev_info = NULL; + DPP_DEV_MGR_T *p_dev_mgr = NULL; + + ZXIC_COMM_CHECK_INDEX_UPPER(dev_id, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, pf_info); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, dev); + + slot = pf_info->slot; + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, slot, 0, DPP_PCIE_SLOT_MAX - 1); + + channel_id = DPP_PCIE_CHANNEL_ID(pf_info->vport); + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, channel_id, 0, DPP_PCIE_CHANNEL_MAX - 1); + + p_dev_mgr = dpp_dev_mgr_get(); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_dev_mgr); + if (!p_dev_mgr->is_init) + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "ErrorCode[ 0x%x]: Device Manager is not init!!!\n", + DPP_RC_DEV_MGR_NOT_INIT); + return DPP_RC_DEV_MGR_NOT_INIT; + } + p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_dev_info); + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_dev_info->pcie_channel[slot][channel_id].device); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_dev_info->pcie_channel[slot][channel_id].oper_mutex); + + dev->device_id = p_dev_info->device_id; + dev->pcie_channel.slot = p_dev_info->pcie_channel[slot][channel_id].slot; + dev->pcie_channel.vport = p_dev_info->pcie_channel[slot][channel_id].vport; + dev->pcie_channel.pcie_id = p_dev_info->pcie_channel[slot][channel_id].pcie_id; + dev->pcie_channel.device = p_dev_info->pcie_channel[slot][channel_id].device; + dev->pcie_channel.base_addr = p_dev_info->pcie_channel[slot][channel_id].base_addr; + dev->pcie_channel.offset_addr = p_dev_info->pcie_channel[slot][channel_id].offset_addr; + dev->pcie_channel.oper_mutex = p_dev_info->pcie_channel[slot][channel_id].oper_mutex; + + return DPP_OK; +} + +/***********************************************************/ +/** +* @param dev_id 设备的设备号 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author 王春雷 @date 2015/03/06 +************************************************************/ +DPP_STATUS dpp_dev_pcie_channel_add(ZXIC_UINT32 dev_id, DPP_PF_INFO_T* pf_info, struct pci_dev* p_dev) +{ + DPP_STATUS rc = 0; + ZXIC_VOID* base_addr = 0; + ZXIC_UINT8 type = 0; + ZXIC_UINT32 post = 0; + ZXIC_UINT16 pcie_id = 0; + ZXIC_UINT16 slot = 0; + ZXIC_UINT16 channel_id = 0; + DPP_DEV_CFG_T *p_dev_info = NULL; + DPP_DEV_MGR_T *p_dev_mgr = NULL; + +#ifdef DPP_FLOW_HW_INIT + struct bar_offset_res res; + struct bar_offset_params paras; +#endif + + ZXIC_COMM_CHECK_INDEX_UPPER(dev_id, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, pf_info); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_dev); + + slot = pf_info->slot; + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, slot, 0, DPP_PCIE_SLOT_MAX - 1); + + channel_id = DPP_PCIE_CHANNEL_ID(pf_info->vport); + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, channel_id, 0, DPP_PCIE_CHANNEL_MAX - 1); + + p_dev_mgr = dpp_dev_mgr_get(); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_dev_mgr); + if (!p_dev_mgr->is_init) + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "ErrorCode[ 0x%x]: Device Manager is not init!!!\n", + DPP_RC_DEV_MGR_NOT_INIT); + return DPP_RC_DEV_MGR_NOT_INIT; + } + p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_dev_info); + + if (p_dev_info->pcie_channel[slot][channel_id].device != NULL) + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "ErrorCode[ 0x%x]: pcie slot %u vport 0x%04x already init.\n", + DPP_RC_DEV_PARA_INVALID, slot, pf_info->vport); + return DPP_RC_DEV_PARA_INVALID; + } + + base_addr = ioremap(pci_resource_start(p_dev, 0), pci_resource_len(p_dev, 0)); + if (IS_ERR_OR_NULL(base_addr)) + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "ErrorCode[ 0x%x]: pcie slot %u vport 0x%04x ioremap failed.\n", + DPP_RC_DEV_PARA_INVALID, slot, pf_info->vport); + return DPP_RC_DEV_PARA_INVALID; + } + + for (post = pci_find_capability(p_dev, PCI_CAP_ID_VNDR); + post > 0; post = pci_find_next_capability(p_dev, post, PCI_CAP_ID_VNDR)) + { + pci_read_config_byte(p_dev, post + 3, &type); + + if (type == 5) + { + pci_read_config_word(p_dev, post + 6, &pcie_id); + } + } + + if (pcie_id == 0) + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "ErrorCode[ 0x%x]: pcie slot %u vport 0x%04x get pcieid failed.\n", + DPP_RC_DEV_PARA_INVALID, slot, pf_info->vport); + return DPP_RC_DEV_PARA_INVALID; + } + +#ifdef DPP_FLOW_HW_INIT + paras.type = URI_NP; + paras.pcie_id = pcie_id; + paras.virt_addr = ZXIC_COMM_PTR_TO_VAL(base_addr) + DEV_PCIE_MSG_OFFSET_ADDR; + if (zxdh_get_bar_offset(¶s, &res) != BAR_MSG_OK) + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "ErrorCode[ 0x%x]: pcie slot %u vport 0x%04x get bar offset failed.\n", + DPP_RC_DEV_PARA_INVALID, slot, pf_info->vport); + return DPP_RC_DEV_PARA_INVALID; + } +#endif + p_dev_info->pcie_channel[slot][channel_id].slot = slot; + p_dev_info->pcie_channel[slot][channel_id].vport = pf_info->vport; + p_dev_info->pcie_channel[slot][channel_id].pcie_id = pcie_id; + p_dev_info->pcie_channel[slot][channel_id].device = p_dev; + p_dev_info->pcie_channel[slot][channel_id].base_addr = ZXIC_COMM_PTR_TO_VAL(base_addr); + +#ifdef DPP_FLOW_HW_INIT + p_dev_info->pcie_channel[slot][channel_id].offset_addr = res.bar_offset; +#else + p_dev_info->pcie_channel[slot][channel_id].offset_addr = 0x6000; +#endif + + p_dev_info->pcie_channel[slot][channel_id].oper_mutex = ZXIC_COMM_MALLOC(sizeof(ZXIC_MUTEX_T)); + rc = zxic_comm_mutex_create(p_dev_info->pcie_channel[slot][channel_id].oper_mutex); + ZXIC_COMM_CHECK_DEV_RC_MEMORY_FREE(dev_id, rc, "zxic_comm_mutex_create", + p_dev_info->pcie_channel[slot][channel_id].oper_mutex); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x base_addr: 0x%llx success.\n", + __FUNCTION__, slot, pf_info->vport, ZXIC_COMM_PTR_TO_VAL(base_addr)); + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x pcie_id: 0x%04x offset_addr: 0x%llx success.\n", + __FUNCTION__, slot, pf_info->vport, pcie_id, + p_dev_info->pcie_channel[slot][channel_id].offset_addr); + + return DPP_OK; +} + +/***********************************************************/ +/** +* @param dev_id 设备的设备号 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author 王春雷 @date 2015/03/06 +************************************************************/ +DPP_STATUS dpp_dev_pcie_channel_del(ZXIC_UINT32 dev_id, DPP_PF_INFO_T* pf_info) +{ + DPP_STATUS rc = 0; + ZXIC_UINT16 slot = 0; + ZXIC_UINT16 channel_id = 0; + DPP_DEV_CFG_T *p_dev_info = NULL; + DPP_DEV_MGR_T *p_dev_mgr = NULL; + + ZXIC_COMM_CHECK_INDEX_UPPER(dev_id, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, pf_info); + + slot = pf_info->slot; + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, slot, 0, DPP_PCIE_SLOT_MAX - 1); + + channel_id = DPP_PCIE_CHANNEL_ID(pf_info->vport); + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, channel_id, 0, DPP_PCIE_CHANNEL_MAX - 1); + + p_dev_mgr = dpp_dev_mgr_get(); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_dev_mgr); + if (!p_dev_mgr->is_init) + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "ErrorCode[ 0x%x]: Device Manager is not init!!!\n", + DPP_RC_DEV_MGR_NOT_INIT); + return DPP_RC_DEV_MGR_NOT_INIT; + } + p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_dev_info); + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_dev_info->pcie_channel[slot][channel_id].device); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_dev_info->pcie_channel[slot][channel_id].oper_mutex); + + rc = zxic_comm_mutex_destroy(p_dev_info->pcie_channel[slot][channel_id].oper_mutex); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "zxic_comm_mutex_destroy"); + ZXIC_COMM_FREE(p_dev_info->pcie_channel[slot][channel_id].oper_mutex); + + iounmap((ZXIC_VOID*)p_dev_info->pcie_channel[slot][channel_id].base_addr); + + p_dev_info->pcie_channel[slot][channel_id].device = NULL; + p_dev_info->pcie_channel[slot][channel_id].slot = 0; + p_dev_info->pcie_channel[slot][channel_id].vport = 0; + p_dev_info->pcie_channel[slot][channel_id].pcie_id = 0; + p_dev_info->pcie_channel[slot][channel_id].base_addr = 0; + p_dev_info->pcie_channel[slot][channel_id].offset_addr = 0; + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x success.\n", __FUNCTION__, slot, pf_info->vport); + + return DPP_OK; +} + +/***********************************************************/ +/** 获取设备类型 +* @param dev_id 设备号 +* +* @return 设备类型，参考DPP_DEV_TYPE_E的定义 +* @remark 无 +* @see +* @author 王春雷 @date 2015/03/06 +************************************************************/ +ZXIC_UINT32 dpp_dev_get_dev_type(ZXIC_UINT32 dev_id) +{ + DPP_DEV_MGR_T *p_dev_mgr = NULL; + DPP_DEV_CFG_T *p_dev_info = NULL; + + ZXIC_COMM_CHECK_INDEX_UPPER(dev_id, DPP_DEV_CHANNEL_MAX - 1); + + p_dev_mgr = dpp_dev_mgr_get(); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_dev_mgr); + + p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + + if (NULL == p_dev_info) + { + return DPP_DEV_TYPE_INVALID; + } + + return (p_dev_info->dev_type); +} + +/***********************************************************/ +/** 获取芯片类型 +* @param dev_id +* +* @return +* @remark 无 +* @see +* @author lfq @date 2014/03/05 +************************************************************/ +ZXIC_UINT32 dpp_dev_chip_version_get(ZXIC_UINT32 dev_id) +{ + // ZXIC_UINT32 device_no = 0; + ZXIC_UINT32 chip_ver = 0; + + // ZXIC_COMM_CHECK_INDEX_UPPER(dev_id,DPP_DEV_CHANNEL_MAX - 1); + + // if (device_no == DPP_CHIP_DPP) + // { + // chip_ver = DPP_CHIP_VERSION_DPP_P; + // } + // else + // { + // ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "Device id [0x%08x] is wrong\n", device_no); + // } + + return chip_ver; +} + +/***********************************************************/ +/** 每个模块的初始化标记设置接口 +* @param dev_id 设备号 +* @param module_id 模块ID, 见MODULE_INIT_E +* @param flag 31bit代表整体初始化状态(1:完成 0:未完成或未开始)，其余31bit自由利用，可以按子模块的初始化状态赋值 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 初始化标记主要用于记录本模块的初始化状态 +* @see +* @author xjw @date 2019/10/30 +************************************************************/ +DPP_STATUS dpp_dev_init_flag_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 module_id, ZXIC_UINT32 flag) +{ + DPP_DEV_CFG_T *p_dev_info = NULL; + DPP_DEV_MGR_T *p_dev_mgr = NULL; + + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, module_id, MODULE_INIT_NPPU, MODULE_INIT_MAX - 1); + + p_dev_mgr = dpp_dev_mgr_get(); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_dev_mgr); + p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + + if (NULL == p_dev_info) + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "ErrorCode[ 0x%x]: Device CFG is not init!!!\n", + DPP_RC_DEV_CFG_NOT_INIT); + return DPP_RC_DEV_CFG_NOT_INIT; + } + + p_dev_info->init_flags[module_id] = flag; + + return DPP_OK; +} + +/***********************************************************/ +/** 每个模块的初始化标记获取接口 +* @param dev_id 设备号 +* @param module_id 模块ID, 见MODULE_INIT_E +* @param p_flag 按ZXIC_UINT32返回，bit处理各模块自行完成 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 初始化标记主要用于记录本模块的初始化状态 +* @see +* @author xjw @date 2019/10/30 +************************************************************/ +DPP_STATUS dpp_dev_init_flag_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 module_id, ZXIC_UINT32 *p_flag) +{ + DPP_DEV_CFG_T *p_dev_info = NULL; + DPP_DEV_MGR_T *p_dev_mgr = NULL; + + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, module_id, MODULE_INIT_NPPU, MODULE_INIT_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_flag); + + p_dev_mgr = dpp_dev_mgr_get(); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_dev_mgr); + p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + + if (NULL == p_dev_info) + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "ErrorCode[ 0x%x]: Device CFG is not init!!!\n", + DPP_RC_DEV_CFG_NOT_INIT); + return DPP_RC_DEV_CFG_NOT_INIT; + } + + *p_flag = p_dev_info->init_flags[module_id]; + + return DPP_OK; +} + +/***********************************************************/ +/** 根据类型获取互斥锁 +* @param dev_id 设备号 +* @param type 互斥锁类型，取值参照DPP_DEV_MUTEX_TYPE_E的定义 +* @param p_mutex_out 返回的互斥锁指针地址 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author 王春雷 @date 2015/10/10 +************************************************************/ +DPP_STATUS dpp_dev_opr_mutex_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 type, ZXIC_MUTEX_T **p_mutex_out) +{ + //DPP_STATUS rc = 0; + DPP_DEV_MGR_T *p_dev_mgr = NULL; + DPP_DEV_CFG_T *p_dev_info = NULL; + + ZXIC_COMM_CHECK_INDEX_UPPER(dev_id, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_INDEX_UPPER(type, DPP_DEV_MUTEX_T_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_mutex_out); + + p_dev_mgr = dpp_dev_mgr_get(); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_dev_mgr); + p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + + if (NULL == p_dev_info) + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "Get dev_info[ %d ] fail!\n", dev_id); + return DPP_DEV_TYPE_INVALID; + } + + switch (type) + { + case DPP_DEV_MUTEX_T_REG: + { + *p_mutex_out = &(p_dev_info->reg_opr_mutex); + } + break; + + case DPP_DEV_MUTEX_T_OAM: + { + *p_mutex_out = &(p_dev_info->oam_mutex); + } + break; + + case DPP_DEV_MUTEX_T_ETM: + { + *p_mutex_out = &(p_dev_info->etm_mutex); + } + break; + + case DPP_DEV_MUTEX_T_DDR: + { + *p_mutex_out = &(p_dev_info->ddr_mutex); + } + break; + + case DPP_DEV_MUTEX_T_IND: + { + *p_mutex_out = &(p_dev_info->ind_mutex); + } + break; + + case DPP_DEV_MUTEX_T_ETCAM: + { + *p_mutex_out = &(p_dev_info->etcam_mutex); + } + break; + + case DPP_DEV_MUTEX_T_CAR0: + { + *p_mutex_out = &(p_dev_info->car0_mutex); + } + break; + + case DPP_DEV_MUTEX_T_ALG: + { + *p_mutex_out = &(p_dev_info->alg_mutex); + } + break; + + case DPP_DEV_MUTEX_T_NPPU: + { + *p_mutex_out = &(p_dev_info->nppu_mutex); + } + break; + + case DPP_DEV_MUTEX_T_SMMU0: + { + *p_mutex_out = &(p_dev_info->smmu0_mutex); + } + break; + + case DPP_DEV_MUTEX_T_SMMU1: + { + *p_mutex_out = &(p_dev_info->smmu1_mutex); + } + break; + + case DPP_DEV_MUTEX_T_ETM_2ND: + { + *p_mutex_out = &(p_dev_info->etm_2nd_mutex); + } + break; + + case DPP_DEV_MUTEX_T_LPM: + { + *p_mutex_out = &(p_dev_info->lpm_mutex); + } + break; + + case DPP_DEV_MUTEX_T_CRM_TEMP: + { + *p_mutex_out = &(p_dev_info->crm_temp_mutex); + } + break; + + case DPP_DEV_MUTEX_T_SIM: + { + *p_mutex_out = &(p_dev_info->sim_mutex); + } + break; + + case DPP_DEV_MUTEX_T_DTB: + { + *p_mutex_out = &(p_dev_info->dtb_mutex); + } + break; + + default: + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "mutex type is invalid!\n"); + return DPP_ERR; + } + } + + return DPP_OK; +} + +/***********************************************************/ +/** 根据index获取dtb对应队列的互斥锁 +* @param dev_id 设备号 +* @param type 互斥锁类型，取值参照DPP_DEV_MUTEX_TYPE_E的定义 +* @param p_mutex_out 返回的互斥锁指针地址 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author 王春雷 @date 2015/10/10 +************************************************************/ +DPP_STATUS dpp_dev_dtb_opr_mutex_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 type, ZXIC_UINT32 index, ZXIC_MUTEX_T **p_mutex_out) +{ + //DPP_STATUS rc = 0; + DPP_DEV_MGR_T *p_dev_mgr = NULL; + DPP_DEV_CFG_T *p_dev_info = NULL; + + ZXIC_COMM_CHECK_INDEX_UPPER(dev_id, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_INDEX_UPPER(type, DPP_DEV_MUTEX_T_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_mutex_out); + + p_dev_mgr = dpp_dev_mgr_get(); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_dev_mgr); + p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + + if (NULL == p_dev_info) + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "Get dev_info[ %d ] fail!\n", dev_id); + return DPP_DEV_TYPE_INVALID; + } + + switch (type) + { + case DPP_DEV_MUTEX_T_DTB: + { + *p_mutex_out = &(p_dev_info->dtb_queue_mutex[index]); + } + break; + + default: + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "mutex type is invalid!\n"); + return DPP_ERR; + } + } + + return DPP_OK; +} + +/***********************************************************/ +/** PCIE 默认读接口 +* @param dev_id +* @param addr +* @param size +* @param p_data +* +* @return +* @remark 无 +* @see +* @author XXX @date 2018/05/02 +************************************************************/ +DPP_STATUS dpp_dev_pcie_default_write(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 size, ZXIC_UINT32 *p_data) +{ + DPP_STATUS rc = 0; + ZXIC_UINT32 i; + ZXIC_ADDR_T abs_addr = 0; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data); + + abs_addr = DEV_PCIE_REG_ADDR(dev); + +#ifdef MACRO_CPU64 + ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_64_NO_ASSERT(DEV_ID(dev), abs_addr, (ZXIC_ADDR_T)addr); +#else + ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(DEV_ID(dev), abs_addr, (ZXIC_ADDR_T)addr); +#endif + +#ifdef DPP_FOR_AARCH64 + addr = addr - (SYS_NP_BASE_ADDR1 - DEV_PCIE_OFFSET_ADDR(dev)); + addr = X86_ADDR_2_ARRCH64(addr); + addr = addr + (SYS_NP_BASE_ADDR1 - DEV_PCIE_OFFSET_ADDR(dev)); +#endif + + abs_addr += addr; + ZXIC_COMM_TRACE_DEBUG("dpp_dev_pcie_default_write: write abs_addr:0x%llx\n", abs_addr); + + for (i = 0; i < size; i++) + { + +#ifdef MACRO_CPU64 + ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_64_NO_ASSERT(DEV_ID(dev), abs_addr, (ZXIC_ADDR_T)(4 * ((ZXIC_ADDR_T)(i)))); +#else + ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(DEV_ID(dev), abs_addr, (ZXIC_ADDR_T)(4 * ((ZXIC_ADDR_T)(i)))); +#endif + + rc = dpp_pci_write32(dev, abs_addr + (ZXIC_ADDR_T)(4 * ((ZXIC_ADDR_T)(i))), p_data + i); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_pci_write32"); + ZXIC_COMM_TRACE_DEBUG("dpp_dev_pcie_default_write: write Addr:0x%llx ,Value 0x%x\n", (abs_addr + (ZXIC_ADDR_T)(4 * ((ZXIC_ADDR_T)(i)))), *(p_data + i)); + } + + return DPP_OK; +} + +/***********************************************************/ +/** PCIE 默认写接口 +* @param dev_id +* @param addr +* @param size +* @param p_data +* +* @return +* @remark 无 +* @see +* @author XXX @date 2018/05/02 +************************************************************/ +DPP_STATUS dpp_dev_pcie_default_read(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 size, ZXIC_UINT32 *p_data) +{ + DPP_STATUS rc = 0; + ZXIC_UINT32 i; + ZXIC_ADDR_T abs_addr = 0; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data); + + abs_addr = DEV_PCIE_REG_ADDR(dev); + +#ifdef MACRO_CPU64 + ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_64_NO_ASSERT(DEV_ID(dev), abs_addr, (ZXIC_ADDR_T)(addr)); +#else + ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(DEV_ID(dev), abs_addr, (ZXIC_ADDR_T)(addr)); +#endif + +#ifdef DPP_FOR_AARCH64 + addr = addr - (SYS_NP_BASE_ADDR1 - DEV_PCIE_OFFSET_ADDR(dev)); + addr = X86_ADDR_2_ARRCH64(addr); + addr = addr + (SYS_NP_BASE_ADDR1 - DEV_PCIE_OFFSET_ADDR(dev)); +#endif + + abs_addr += addr; + + for (i = 0; i < size; i++) + { + rc = dpp_pci_read32(dev, abs_addr + (ZXIC_ADDR_T)(4 * ((ZXIC_ADDR_T)(i))), p_data + i); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_pci_read32"); + + ZXIC_COMM_TRACE_DEBUG("dpp_dev_pcie_default_read: Read Addr:0x%llx ,Value 0x%x\n", (abs_addr + (ZXIC_ADDR_T)(4 * ((ZXIC_ADDR_T)(i)))), *(p_data + i)); + } + + return DPP_OK; +} + +#ifndef ES_FOR_LLT +/***********************************************************/ +/** 写设备底层接口 +* @param dev_id 设备号 +* @param addr 单个设备内部的相对地址 +* @param size 数据的长度，以32bit为单位 +* @param p_data 数据 +* +* @return +* @remark 无 +* @see +* @author 王春雷 @date 2014/05/15 +************************************************************/ +DPP_STATUS dpp_dev_write_channel(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 size, ZXIC_UINT32 *p_data) +{ + /*ZXIC_UINT32 i = 0;*/ + DPP_STATUS rtn = 0; +#if DPP_HW_OPR_EN + DPP_DEV_CFG_T *p_dev_info = NULL; +#endif + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev), DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data); + +#ifdef DPP_FOR_LLT + rtn = dpp_stump_reg_rb_debug_wr(DEV_ID(dev), + addr, + size, + p_data); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_stump_reg_rb_debug_wr"); + return DPP_OK; +#endif + +#if DPP_HW_OPR_EN + p_dev_info = DPP_DEV_INFO_GET(DEV_ID(dev)); + + if (p_dev_info == NULL) + { + ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "Error: Channel[%d] dev is not exist!\n ", DEV_ID(dev)); + return DPP_ERR; + } + else + { + if (p_dev_info->access_type == DPP_DEV_ACCESS_TYPE_PCIE) + { + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_dev_info->p_pcie_write_fun); + rtn = p_dev_info->p_pcie_write_fun(dev, addr, size, p_data); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "p_dev_info->p_pcie_write_fun"); + } + else + { + ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "Dev access type[ %d ] is invalid!\n", p_dev_info->access_type); + return DPP_ERR; + } + } + +#endif + + return DPP_OK; +} + +/***********************************************************/ +/** 读设备底层接口 +* @param dev_id 设备号 +* @param addr 单个设备内部的相对地址 +* @param size 数据的长度，以32bit为单位 +* @param p_data 数据 +* +* @return +* @remark 无 +* @see +* @author 王春雷 @date 2014/05/15 +************************************************************/ +DPP_STATUS dpp_dev_read_channel(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 size, ZXIC_UINT32 *p_data) +{ + DPP_STATUS rtn = 0; +#if DPP_HW_OPR_EN + DPP_DEV_CFG_T *p_dev_info = NULL; +#endif + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev), DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data); + +#ifdef DPP_FOR_LLT + rtn = dpp_stump_reg_rb_debug_rd(DEV_ID(dev), + addr, + size, + p_data); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_stump_reg_rb_debug_rd"); + return DPP_OK; +#endif + +#if DPP_HW_OPR_EN + p_dev_info = DPP_DEV_INFO_GET(DEV_ID(dev)); + + if (p_dev_info == NULL) + { + ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "Error: Channel[%d] dev is not exist!\n ", DEV_ID(dev)); + return DPP_ERR; + } + else + { + if (p_dev_info->access_type == DPP_DEV_ACCESS_TYPE_PCIE) + { + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_dev_info->p_pcie_read_fun); + rtn = p_dev_info->p_pcie_read_fun(dev, addr, size, p_data); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "p_dev_info->p_pcie_read_fun"); + } + else + { + ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "Dev access type[ %d ] is invalid!\n", p_dev_info->access_type); + return DPP_ERR; + } + } + +#else + + for (ZXIC_UINT32 i = 0; i < size; i++) + { + p_data[i] = 0xffffffff; + } + +#endif + + return DPP_OK; +} +#endif /* ES_FOR_LLT */ diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/chip/dpp_init.c b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/chip/dpp_init.c new file mode 100755 index 0000000..918d463 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/chip/dpp_init.c @@ -0,0 +1,73 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_init.c +* 文件标识 : +* 内容摘要 : 芯片初始化源文件 +* 其它说明 : +* 当前版本 : +* 作 者 : 王春雷 +* 完成日期 : 2015/03/17 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ + +#include "zxic_common.h" +#include "dpp_module.h" +#include "dpp_dev.h" +#include "dpp_ppu.h" +#include "dpp_se.h" +#include "dpp_dtb.h" +#include "dpp_init.h" + +/***********************************************************/ +/** 芯片上电初始，完整版本 +* @param dev_id 设备号 +* @param p_init_ctrl 系统初始化控制数据结构，由用户完成实例化和成员赋值 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author 王春雷 @date 2015/03/26 +************************************************************/ +DPP_STATUS dpp_init(ZXIC_UINT32 dev_id, DPP_SYS_INIT_CTRL_T *p_init_ctrl) +{ + DPP_STATUS rt = 0; + ZXIC_UINT32 access_type = 0; + ZXIC_UINT32 dev_id_array[DPP_DEV_CHANNEL_MAX] = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_init_ctrl); + + /* 初始化设备管理模块 */ + rt = dpp_dev_init(); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rt, "dpp_dev_init"); + + rt = dpp_dev_add(dev_id, + p_init_ctrl->device_type, + access_type, + p_init_ctrl->pcie_vir_baddr, + p_init_ctrl->riscv_vir_baddr, + p_init_ctrl->dma_vir_baddr, + p_init_ctrl->dma_phy_baddr, + p_init_ctrl->pcie_write_fun, + p_init_ctrl->pcie_read_fun, + p_init_ctrl->riscv_write_fun, + p_init_ctrl->riscv_read_fun); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rt, "dpp_dev_add"); + + /* 初始化table模块软件部分 */ + dev_id_array[0] = dev_id; + rt = dpp_sdt_init(1, dev_id_array); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rt, "dpp_sdt_init"); + + rt = dpp_ppu_parse_cls_bitmap(dev_id, DPP_PPU_CLS_ALL_START); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rt, "dpp_ppu_parse_cls_bitmap"); + + return DPP_OK; +} diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/init/Kbuild.include b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/init/Kbuild.include new file mode 100644 index 0000000..3c13531 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/init/Kbuild.include @@ -0,0 +1,2 @@ +cur_dir := en_np/sdk/source/dev/init/ +src_files += $(addprefix $(cur_dir),$(notdir $(wildcard $(dinghai_root)/$(cur_dir)*.c))) \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/init/dpp_kernel_init.c b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/init/dpp_kernel_init.c new file mode 100644 index 0000000..0e8b05b --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/init/dpp_kernel_init.c @@ -0,0 +1,233 @@ +#include +#include +#include +#include +#include +#include "zxic_common.h" +#include "dpp_dtb_cfg.h" +#include "dpp_kernel_init.h" +#include "dpp_dtb_table_api.h" + +/*hash dma地址信息*/ +typedef struct hash_dma_addr_info +{ + ZXIC_UINT32 slot_id; /*np所在的槽位号*/ + ZXIC_UINT32 dma_size; /*hash申请的dma大小*/ + dma_addr_t dma_phy_addr; /* dma 物理地址*/ + ZXIC_VOID *dma_vir_addr; /* dma 内核虚拟地址*/ +}HASH_DMA_ADDR_INFO; + +/*DMA空间信息*/ +typedef struct dpp_dma_info +{ + DTB_QUEUE_DMA_ADDR_INFO dtb_queue_info[DPP_DTB_QUEUE_NUM_MAX]; /*dtb队列*/ + HASH_DMA_ADDR_INFO hash_dma_info; /*hash上送*/ +}DPP_KERNEL_DMA_INFO; + +static DPP_KERNEL_DMA_INFO g_dpp_dma_info[DPP_PCIE_SLOT_MAX] = {0}; +static ZXIC_UINT32 queue_used_flag[DPP_PCIE_SLOT_MAX][4] = {0}; + +static ZXIC_VOID dpp_dtb_queue_dma_flag_set(ZXIC_UINT32 slot_id, ZXIC_UINT32 queue_id) +{ + ZXIC_UINT32 bit_shift = 0; + ZXIC_UINT32 reg_shift = 0; + + reg_shift = queue_id / 32; + bit_shift = queue_id % 32; + + queue_used_flag[slot_id][reg_shift] = queue_used_flag[slot_id][reg_shift] | (0x1 << bit_shift); +} + +static ZXIC_VOID dpp_dtb_queue_dma_flag_clear(ZXIC_UINT32 slot_id, ZXIC_UINT32 queue_id) +{ + ZXIC_UINT32 bit_shift = 0; + ZXIC_UINT32 reg_shift = 0; + + reg_shift = queue_id / 32; + bit_shift = queue_id % 32; + + queue_used_flag[slot_id][reg_shift] = queue_used_flag[slot_id][reg_shift] & ~(0x1 << bit_shift); +} + +static ZXIC_UINT32 dpp_dtb_queue_dma_flag_get(ZXIC_UINT32 slot_id, ZXIC_UINT32 queue_id) +{ + ZXIC_UINT32 bit_shift = 0; + ZXIC_UINT32 reg_shift = 0; + + ZXIC_UINT32 flag = 0; + + reg_shift = queue_id / 32; + bit_shift = queue_id % 32; + + flag = (queue_used_flag[slot_id][reg_shift] >> bit_shift) & 0x1; + + ZXIC_COMM_PRINT("[dpp_dtb_queue_dma_flag_get]:slot %d queue %d flag %d!\n", slot_id, queue_id, flag); + + return flag; +} + +//申请队列DMA空间，通过传入DMA队列号，返回申请到DMA内存的物理地址 +ZXIC_SINT32 dpp_dtb_queue_dma_mem_alloc(DPP_DEV_T *dev, ZXIC_UINT32 queue_id, ZXIC_UINT32 size) +{ + dma_addr_t dma_handle; + ZXIC_VOID* cpu_addr = NULL; + ZXIC_UINT32 slot_id = 0; + + ZXIC_COMM_CHECK_POINT(dev); + + slot_id = (ZXIC_UINT32)DEV_PCIE_SLOT(dev); + ZXIC_COMM_CHECK_INDEX(slot_id, 0, DPP_DEV_SLOT_MAX - 1); + + if (queue_id > (DPP_DTB_QUEUE_NUM_MAX - 1)) + { + return -ENOMEM; + } + + cpu_addr = dma_alloc_coherent(&(DEV_PCIE_DEV(dev)->dev), size, &dma_handle, GFP_KERNEL); + + if(!cpu_addr) + { + dev_err(&(DEV_PCIE_DEV(dev)->dev),"dpp_dtb_queue_dma_mem_alloc buff allocation failed\n"); + return -ENOMEM; + } + + g_dpp_dma_info[slot_id].dtb_queue_info[queue_id].slot_id = slot_id; + g_dpp_dma_info[slot_id].dtb_queue_info[queue_id].queue_id = queue_id; + g_dpp_dma_info[slot_id].dtb_queue_info[queue_id].dma_vir_addr = ZXIC_COMM_PTR_TO_VAL(cpu_addr); + g_dpp_dma_info[slot_id].dtb_queue_info[queue_id].dma_phy_addr = dma_handle; + g_dpp_dma_info[slot_id].dtb_queue_info[queue_id].dma_size = size; + + ZXIC_COMM_PRINT("[dpp_dtb_queue_dma_mem_alloc]:slot %d queue %d kernel phy addr :0x%016llx !\n", + slot_id, queue_id, dma_handle); + ZXIC_COMM_PRINT("[dpp_dtb_queue_dma_mem_alloc]:slot %d queue %d kernel vir addr :0x%016llx !\n", + slot_id, queue_id, ZXIC_COMM_PTR_TO_VAL(cpu_addr)); + + dpp_dtb_queue_dma_flag_set(slot_id, queue_id); + dpp_dtb_queue_dma_flag_get(slot_id, queue_id); + + return DPP_OK; +} + +ZXIC_SINT32 dpp_dtb_queue_dma_mem_get(DPP_DEV_T *dev, ZXIC_UINT32 queue_id, DTB_QUEUE_DMA_ADDR_INFO *dmaAddrInfo) +{ + ZXIC_UINT32 slot_id = 0; + + ZXIC_COMM_CHECK_POINT(dev); + + slot_id = (ZXIC_UINT32)DEV_PCIE_SLOT(dev); + ZXIC_COMM_CHECK_INDEX(slot_id, 0, DPP_DEV_SLOT_MAX - 1); + + if(queue_id > (DPP_DTB_QUEUE_NUM_MAX - 1)) + { + ZXIC_COMM_PRINT("[dpp_dtb_queue_dma_mem_get]:queue id max.\n"); + return -1; + } + + if (g_dpp_dma_info[slot_id].dtb_queue_info[queue_id].queue_id != queue_id) + { + ZXIC_COMM_PRINT("[dpp_dtb_queue_dma_mem_get]:slot %d queue %d error !\n", slot_id, queue_id); + return -1; + } + dmaAddrInfo->dma_phy_addr = g_dpp_dma_info[slot_id].dtb_queue_info[queue_id].dma_phy_addr; + dmaAddrInfo->dma_vir_addr = g_dpp_dma_info[slot_id].dtb_queue_info[queue_id].dma_vir_addr; + dmaAddrInfo->dma_size = g_dpp_dma_info[slot_id].dtb_queue_info[queue_id].dma_size; + dmaAddrInfo->queue_id = queue_id; + dmaAddrInfo->slot_id = slot_id; + + return DPP_OK; +} + +/*dtb队列dma内存释放，通过传入dtb队列号，在维护的队列地址中找到对应的虚拟地址和物理地址，进行释放*/ +ZXIC_SINT32 dpp_dtb_queue_dma_mem_release(DPP_DEV_T *dev, ZXIC_UINT32 queue_id) +{ + dma_addr_t dma_handle = 0; + ZXIC_VOID* cpu_addr = NULL; + ZXIC_UINT32 dma_size = 0; + ZXIC_UINT32 slot_id = 0; + + ZXIC_COMM_CHECK_POINT(dev); + + slot_id = (ZXIC_UINT32)DEV_PCIE_SLOT(dev); + ZXIC_COMM_CHECK_INDEX(slot_id, 0, DPP_DEV_SLOT_MAX - 1); + + if(queue_id > (DPP_DTB_QUEUE_NUM_MAX - 1)) + { + ZXIC_COMM_PRINT("[dpp_dtb_dma_mem_release]:queue id max.\n"); + return -1; + } + + if (g_dpp_dma_info[slot_id].dtb_queue_info[queue_id].queue_id != queue_id) + { + ZXIC_COMM_PRINT("[dpp_dtb_dma_mem_release]:slot %d queue %d error !\n", slot_id, queue_id); + return -1; + } + + dma_handle = g_dpp_dma_info[slot_id].dtb_queue_info[queue_id].dma_phy_addr; + cpu_addr = ZXIC_COMM_VAL_TO_PTR(g_dpp_dma_info[slot_id].dtb_queue_info[queue_id].dma_vir_addr); + dma_size = g_dpp_dma_info[slot_id].dtb_queue_info[queue_id].dma_size; + + if (!dma_handle) + { + return -EFAULT; + } + + dma_free_coherent(&(DEV_PCIE_DEV(dev)->dev), dma_size, cpu_addr, dma_handle); + + ZXIC_COMM_PRINT("[dpp_dtb_dma_mem_release]:slot %d queue %d release success!\n", slot_id, queue_id); + + g_dpp_dma_info[slot_id].dtb_queue_info[queue_id].slot_id = 0; + g_dpp_dma_info[slot_id].dtb_queue_info[queue_id].queue_id = 0; + g_dpp_dma_info[slot_id].dtb_queue_info[queue_id].dma_phy_addr = 0; + g_dpp_dma_info[slot_id].dtb_queue_info[queue_id].dma_vir_addr = 0; + g_dpp_dma_info[slot_id].dtb_queue_info[queue_id].dma_size = 0; + + dpp_dtb_queue_dma_flag_clear(slot_id, queue_id); + dpp_dtb_queue_dma_flag_get(slot_id, queue_id); + + return 0; +} + +ZXIC_SINT32 dtb_sdt_dump_dma_alloc(DPP_DEV_T *dev, + ZXIC_UINT32 dma_size, + ZXIC_UINT64 * p_dma_phy_addr, + ZXIC_UINT64 * p_dma_vir_addr) +{ + int rc = 0; + + dma_addr_t dma_handle; + ZXIC_VOID* cpu_addr = NULL; + + cpu_addr = dma_alloc_coherent(&(DEV_PCIE_DEV(dev)->dev), dma_size, &dma_handle, GFP_KERNEL); + + if(!cpu_addr) + { + dev_err(&(DEV_PCIE_DEV(dev)->dev),"dtb_sdt_dump_dma_alloc buff allocation failed\n"); + return -ENOMEM; + } + + *p_dma_phy_addr = (ZXIC_UINT64)dma_handle; + *p_dma_vir_addr = (ZXIC_UINT64)(ZXIC_COMM_PTR_TO_VAL(cpu_addr)); + + return rc; +} + +ZXIC_SINT32 dtb_sdt_dump_dma_release(DPP_DEV_T *dev, + ZXIC_UINT32 dma_size, + ZXIC_UINT64 dma_phy_addr, + ZXIC_UINT64 dma_vir_addr) +{ + dma_addr_t dma_handle = 0; + ZXIC_VOID* cpu_addr = NULL; + + dma_handle = (dma_addr_t)dma_phy_addr; + cpu_addr = ZXIC_COMM_VAL_TO_PTR(dma_vir_addr); + + if (!dma_handle) + { + return -EFAULT; + } + + dma_free_coherent(&(DEV_PCIE_DEV(dev)->dev), dma_size, cpu_addr, dma_handle); + + return 0; +} diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/Kbuild.include b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/Kbuild.include new file mode 100644 index 0000000..9b841e1 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/Kbuild.include @@ -0,0 +1,4 @@ +cur_dir := en_np/sdk/source/dev/module/ +subdirs := se/ table/ dma/ se_apt/ ppu/ tm/ nppu/ +src_files += +include $(foreach subdir, $(subdirs), $(dinghai_root)/$(cur_dir)$(subdir)/Kbuild.include) \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/dma/Kbuild.include b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/dma/Kbuild.include new file mode 100644 index 0000000..632e1f9 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/dma/Kbuild.include @@ -0,0 +1,2 @@ +cur_dir := en_np/sdk/source/dev/module/dma/ +src_files += $(addprefix $(cur_dir),$(notdir $(wildcard $(dinghai_root)/$(cur_dir)*.c))) diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/dma/dpp_dtb.c b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/dma/dpp_dtb.c new file mode 100755 index 0000000..9d64e63 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/dma/dpp_dtb.c @@ -0,0 +1,2183 @@ +/************************************************************** +* 版权所有(C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_dtb.c +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : zab +* 完成日期 : 2022/08/26 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ +#include "zxic_common.h" +#include "dpp_dev.h" +#include "dpp_type_api.h" +#include "dpp_dtb_cfg.h" +#include "dpp_dtb.h" +#include "dpp_dtb_table.h" +#include "dpp_hash.h" +#include "dpp_dtb_reg.h" +#include "dpp_reg_api.h" +#include "dpp_reg_info.h" +#include "dpp_se_api.h" + +#if ZXIC_REAL("DTB") + +ZXIC_CHAR *g_dpp_dtb_name[] = +{ + "DOWN TAB", + "UP TAB", +}; + +DPP_DTB_MGR_T *p_dpp_dtb_mgr[DPP_PCIE_SLOT_MAX][DPP_DEV_CHANNEL_MAX] = {{NULL}}; + +/**dtb超时时间 单位us*/ +static ZXIC_UINT32 g_dtb_down_overtime = 2*1000; +static ZXIC_UINT32 g_dtb_dump_overtime = 5*1000*1000; + +/*配置dtb调试函数*/ +static ZXIC_UINT32 g_dtb_debug_fun_en = 0; +static ZXIC_UINT32 g_dtb_print_en = 0; +static ZXIC_UINT32 g_dtb_soft_perf_test = 0; +static ZXIC_UINT32 g_dtb_hardware_perf_test = 0; + +/**使能dtb调试函数*/ +ZXIC_UINT32 dpp_dtb_debug_fun_enable(ZXIC_VOID) +{ + g_dtb_debug_fun_en = 1; + return 0; +} + +/**去使能dtb调试函数*/ +ZXIC_UINT32 dpp_dtb_debug_fun_disable(ZXIC_VOID) +{ + g_dtb_debug_fun_en = 0; + return 0; +} + +/**获取dtb调试函数*/ +ZXIC_UINT32 dpp_dtb_debug_fun_get(ZXIC_VOID) +{ + return g_dtb_debug_fun_en; +} + +/**使能dtb打印函数*/ +ZXIC_UINT32 dpp_dtb_prt_enable(ZXIC_VOID) +{ + g_dtb_print_en = 1; + return 0; +} + +/**去使能dtb打印函数*/ +ZXIC_UINT32 dpp_dtb_prt_disable(ZXIC_VOID) +{ + g_dtb_print_en = 0; + return 0; +} + +/**获取dtb打印函数*/ +ZXIC_UINT32 dpp_dtb_prt_get(ZXIC_VOID) +{ + return g_dtb_print_en; +} + +ZXIC_UINT32 dpp_dtb_soft_perf_test_set(ZXIC_UINT32 value) +{ + g_dtb_soft_perf_test = value; + return 0; +} + +ZXIC_UINT32 dpp_dtb_soft_perf_test_get(ZXIC_VOID) +{ + return g_dtb_soft_perf_test; +} + +ZXIC_UINT32 dpp_dtb_hardware_perf_test_set(ZXIC_UINT32 value) +{ + g_dtb_hardware_perf_test = value; + return 0; +} + +ZXIC_UINT32 dpp_dtb_hardware_perf_test_get(ZXIC_VOID) +{ + return g_dtb_hardware_perf_test; +} + +ZXIC_UINT32 dpp_dtb_down_table_overtime_set(ZXIC_UINT32 times_s) +{ + g_dtb_down_overtime = times_s; + return 0; +} + +ZXIC_UINT32 dpp_dtb_down_table_overtime_get(ZXIC_VOID) +{ + return g_dtb_down_overtime; +} + +ZXIC_UINT32 dpp_dtb_dump_table_overtime_set(ZXIC_UINT32 times_s) +{ + g_dtb_dump_overtime = times_s; + return 0; +} + +ZXIC_UINT32 dpp_dtb_dump_table_overtime_get(ZXIC_VOID) +{ + return g_dtb_dump_overtime; +} + +#if ZXIC_REAL("MGR") +/***********************************************************/ +/** 创建DTB的管理结构 +* @param dev_id 设备号，支持多芯片 +* +* @return +* @remark 无 +* @see +* @author zab @date 2021/02/23 +************************************************************/ +ZXIC_UINT32 dpp_dtb_mgr_create(ZXIC_UINT32 slot_id, ZXIC_UINT32 dev_id) +{ + ZXIC_COMM_CHECK_INDEX(slot_id, 0, DPP_PCIE_SLOT_MAX - 1); + ZXIC_COMM_CHECK_INDEX(dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + + if (p_dpp_dtb_mgr[slot_id][dev_id] != ZXIC_NULL) + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "slot %d ErrorCode[0x%x]: DTB Manager is not exist!!!\n", slot_id, DPP_RC_DTB_MGR_NOT_EXIST); + return DPP_RC_DTB_MGR_EXIST; + } + + p_dpp_dtb_mgr[slot_id][dev_id] = (DPP_DTB_MGR_T *)ZXIC_COMM_MALLOC(sizeof(DPP_DTB_MGR_T)); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_dpp_dtb_mgr[slot_id][dev_id]); + + ZXIC_COMM_MEMSET(p_dpp_dtb_mgr[slot_id][dev_id], 0, sizeof(DPP_DTB_MGR_T)); + + ZXIC_COMM_PRINT("dpp_dtb_mgr_create:slot %d dev %d done!!!", slot_id, dev_id); + + return DPP_OK; +} + +/***********************************************************/ +/** 注销DTB的管理结构 +* @param dev_id 设备号，支持多芯片 +* +* @return +* @remark 无 +* @see +* @author zab @date 2021/02/23 +************************************************************/ +ZXIC_UINT32 dpp_dtb_mgr_destory_all(ZXIC_VOID) +{ + ZXIC_UINT32 slot_id = 0; + ZXIC_UINT32 dev_id = 0; + + for(slot_id = 0; slot_id < DPP_DEV_SLOT_MAX; slot_id++) + { + for(dev_id = 0; dev_id < DPP_DEV_CHANNEL_MAX; dev_id++) + { + dpp_dtb_mgr_destory(slot_id, dev_id); + } + } + + return DPP_OK; +} + +ZXIC_UINT32 dpp_dtb_mgr_destory(ZXIC_UINT32 slot_id, ZXIC_UINT32 dev_id) +{ + ZXIC_COMM_CHECK_INDEX(slot_id, 0, DPP_PCIE_SLOT_MAX - 1); + ZXIC_COMM_CHECK_INDEX(dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + + if (p_dpp_dtb_mgr[slot_id][dev_id] != ZXIC_NULL) + { + ZXIC_COMM_FREE(p_dpp_dtb_mgr[slot_id][dev_id]); + p_dpp_dtb_mgr[slot_id][dev_id] = ZXIC_NULL; + ZXIC_COMM_PRINT("dpp_dtb_mgr_destory:slot %d dev %d done!!!", slot_id, dev_id); + } + + return DPP_OK; +} + +/***********************************************************/ +/** 重置DTB管理结构 +* @param dev_id 设备号，支持多芯片 +* +* @return +* @remark 无 +* @see +* @author zab @date 2021/02/23 +************************************************************/ +ZXIC_UINT32 dpp_dtb_mgr_reset(ZXIC_UINT32 slot_id, ZXIC_UINT32 dev_id) +{ + ZXIC_COMM_CHECK_INDEX(slot_id, 0, DPP_PCIE_SLOT_MAX - 1); + ZXIC_COMM_CHECK_INDEX(dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + + if (p_dpp_dtb_mgr[slot_id][dev_id] == ZXIC_NULL) + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "slot %d ErrorCode[0x%x]: dtb manager is not exist!!!\n", slot_id, DPP_RC_DTB_MGR_NOT_EXIST); + return DPP_RC_DTB_MGR_NOT_EXIST; + } + + ZXIC_COMM_MEMSET(p_dpp_dtb_mgr[slot_id][dev_id], 0, sizeof(DPP_DTB_MGR_T)); + + return DPP_OK; +} + +/***********************************************************/ +/** 获取DMA管理结构 +* @param dev_id 设备号，支持多芯片 +* +* @return +* @remark 无 +* @see +* @author zab @date 2021/02/23 +************************************************************/ +DPP_DTB_MGR_T *dpp_dtb_mgr_get(ZXIC_UINT32 slot_id, ZXIC_UINT32 dev_id) +{ + if ((slot_id >= DPP_PCIE_SLOT_MAX) || (dev_id >= DPP_DEV_CHANNEL_MAX)) + { + return ZXIC_NULL; + } + else + { + return p_dpp_dtb_mgr[slot_id][dev_id]; + } +} +#endif + +#if ZXIC_REAL("QUEUE_ADDR") +/***********************************************************/ +/** 获得下表队列中某元素的物理地址 +* @param dev_id 设备号，支持多芯片 +* @param queue_id 队列号0-127 +* @param element_id 队列中元素号0-31 +* @param p_element_start_addr_h 元素起始高32位地址 +* @param p_element_start_addr_l 元素起始低32位地址 +* @param p_element_table_addr_h 下表内容开始高32位地址 +* @param p_element_table_addr_l 下表内容开始低32位地址 +* +* @return +* @remark 无 +* @see +* @author zab @date 2021/02/23 +************************************************************/ +ZXIC_UINT32 dpp_dtb_down_table_elemet_addr_get(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 element_id, + ZXIC_UINT32 *p_element_start_addr_h, + ZXIC_UINT32 *p_element_start_addr_l, + ZXIC_UINT32 *p_element_table_addr_h, + ZXIC_UINT32 *p_element_table_addr_l) +{ + ZXIC_UINT32 addr_h = 0; + ZXIC_UINT32 addr_l = 0; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), element_id, 0, DPP_DTB_QUEUE_ITEM_NUM_MAX - 1); + + addr_h = (DPP_DTB_TAB_DOWN_PHY_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, element_id) >> 32) & 0xffffffff; + addr_l = DPP_DTB_TAB_DOWN_PHY_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, element_id) & 0xffffffff; + + *p_element_start_addr_h = addr_h; + *p_element_start_addr_l = addr_l; + + addr_h = ((DPP_DTB_TAB_DOWN_PHY_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, element_id) + DPP_DTB_ITEM_ACK_SIZE) >> 32) & 0xffffffff; + addr_l = (DPP_DTB_TAB_DOWN_PHY_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, element_id) + DPP_DTB_ITEM_ACK_SIZE) & 0xffffffff; + + *p_element_table_addr_h = addr_h; + *p_element_table_addr_l = addr_l; + + return DPP_OK; +} + +/***********************************************************/ +/** 获得队列中某元素dump的物理地址 +* @param dev_id 设备号，支持多芯片 +* @param queue_id 队列号0-127 +* @param element_id 队列中元素号0-31 +* @param p_element_start_addr_h 元素起始高32位地址 +* @param p_element_start_addr_l 元素起始低32位地址 +* @param p_element_dump_addr_h dump描述符开始高32位地址 +* @param p_element_dump_addr_l dump描述符开始低32位地址 +* @param p_element_table_info_addr_h 表内容开始高32位地址 +* @param p_element_table_info_addr_l 表内容开始低32位地址 +* +* @return +* @remark 无 +* @see +* @author zab @date 2021/02/23 +************************************************************/ +ZXIC_UINT32 dpp_dtb_dump_table_elemet_addr_get(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 element_id, + ZXIC_UINT32 *p_element_start_addr_h, + ZXIC_UINT32 *p_element_start_addr_l, + ZXIC_UINT32 *p_element_dump_addr_h, + ZXIC_UINT32 *p_element_dump_addr_l, + ZXIC_UINT32 *p_element_table_info_addr_h, + ZXIC_UINT32 *p_element_table_info_addr_l) +{ + ZXIC_UINT32 rc = 0; + ZXIC_UINT32 addr_h = 0; + ZXIC_UINT32 addr_l = 0; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), element_id, 0, DPP_DTB_QUEUE_ITEM_NUM_MAX - 1); + + addr_h = ((DPP_DTB_TAB_UP_PHY_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, element_id)) >> 32) & 0xffffffff; + addr_l = (DPP_DTB_TAB_UP_PHY_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, element_id)) & 0xffffffff; + + *p_element_start_addr_h = addr_h; + *p_element_start_addr_l = addr_l; + + addr_h = ((DPP_DTB_TAB_UP_PHY_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, element_id)+ DPP_DTB_ITEM_ACK_SIZE) >> 32) & 0xffffffff; + addr_l = (DPP_DTB_TAB_UP_PHY_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, element_id)+ DPP_DTB_ITEM_ACK_SIZE) & 0xffffffff; + + *p_element_dump_addr_h = addr_h; + *p_element_dump_addr_l = addr_l; + + rc = dpp_dtb_tab_up_item_addr_get(dev, queue_id, element_id, p_element_table_info_addr_h, p_element_table_info_addr_l); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_tab_up_item_addr_get"); + + return DPP_OK; +} + +#endif + +#if ZXIC_REAL("MEM_RW") +/***********************************************************/ +/** 内存32bits写入函数 +* @param dev_id 设备号，支持多芯片 +* @param addr 地址偏移 +* @param data 写入数据 +* +* @return +* @remark 无 +* @see +* @author zab @date 2021/02/23 +************************************************************/ +ZXIC_UINT32 dpp_dtb_wr32(DPP_DEV_T *dev, + ZXIC_ADDR_T addr, + ZXIC_UINT32 data) +{ + ZXIC_UINT32 value = data; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), data, 0, ZXIC_UINT32_MAX); + + if (!zxic_comm_is_big_endian()) + { + value = ZXIC_COMM_CONVERT32(value); + } + + *((ZXIC_VOL ZXIC_UINT32 *)(addr)) = value; + + return DPP_OK; +} + +/***********************************************************/ +/** 内存32bits读取函数 +* @param dev_id 设备号，支持多芯片 +* @param addr 读取地址 +* @param p_data 读取数据 +* +* @return +* @remark 无 +* @see +* @author zab @date 2021/02/23 +************************************************************/ +ZXIC_UINT32 dpp_dtb_rd32(DPP_DEV_T *dev, + ZXIC_ADDR_T addr, + ZXIC_UINT32 *p_data) +{ + ZXIC_UINT32 value = 0; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data); + + // dpp_flush_cache();//片内DDR使用 + + value = *((ZXIC_VOL ZXIC_UINT32 *)(addr)); + + if (!zxic_comm_is_big_endian()) + { + value = ZXIC_COMM_CONVERT32(value); + } + + *p_data = value; + + return DPP_OK; +} +#endif + +#if ZXIC_REAL("ACK_RW") +/***********************************************************/ +/** 读取BD表条目信息 +* @param dev_id 芯片的id号 +* @param queue_id 队列号,范围0-127 +* @param dir_flag 方向,1-上送表项,0-下发表项 +* @param index 条目索引,范围0-31 +* @param pos 一个item里面的4个32位，pos对应的是第几个ZXICP_WORD32， +* 取值为0，1，2，3 +* @param p_data 读取的数据,大端格式 +* +* @return +* @remark 无 +* @see +* @author zab @date 2019/11/2 +************************************************************/ +ZXIC_UINT32 dpp_dtb_item_ack_rd(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 dir_flag, + ZXIC_UINT32 index, + ZXIC_UINT32 pos, + ZXIC_UINT32 *p_data) +{ + ZXIC_UINT32 rc = 0; + ZXIC_ADDR_T addr = 0; + ZXIC_UINT32 val = 0; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), dir_flag, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), index, 0, DPP_DTB_QUEUE_ITEM_NUM_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), pos, 0, 3); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data); + + if(DPP_DTB_QUEUE_INIT_FLAG_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id) == 0) + { + ZXIC_COMM_TRACE_ERROR("dtb slot %d queue %d is not init.\n", DEV_PCIE_SLOT(dev), queue_id); + return DPP_RC_DTB_QUEUE_IS_NOT_INIT; + } + + if (dir_flag == DPP_DTB_DIR_UP_TYPE) + { + addr = DPP_DTB_TAB_UP_VIR_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, index) + pos * 4; + } + else + { + addr = DPP_DTB_TAB_DOWN_VIR_ADDR_GET(DEV_PCIE_SLOT(dev),DEV_ID(dev), queue_id, index) + pos * 4; + } + + rc = dpp_dtb_rd32(dev, addr, &val); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_rd32"); + + *p_data = val; + + return DPP_OK; +} + +/***********************************************************/ +/** 向BD表条目指定位置写入值 +* @param dev_id 芯片的id号 +* @param queue_id 队列号,范围0-127 +* @param dir_flag 方向,1-上送表项,0-下发表项 +* @param index 条目索引,范围0-31 +* @param pos 一个item里面的4个32位，pos对应的是第几个ZXICP_WORD32， +* 取值为0，1，2，3 +* @param data 读取的数据,大端格式 +* +* @return +* @remark 无 +* @see +* @author zab @date 2019/11/2 +************************************************************/ +ZXIC_UINT32 dpp_dtb_item_ack_wr(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 dir_flag, + ZXIC_UINT32 index, + ZXIC_UINT32 pos, + ZXIC_UINT32 data) +{ + ZXIC_UINT32 rc = 0; + ZXIC_ADDR_T addr = 0; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), dir_flag, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), index, 0, DPP_DTB_QUEUE_ITEM_NUM_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), pos, 0, 3); + + if(DPP_DTB_QUEUE_INIT_FLAG_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id) == 0) + { + ZXIC_COMM_TRACE_ERROR("dtb slot %d queue %d is not init.\n", DEV_PCIE_SLOT(dev), queue_id); + return DPP_RC_DTB_QUEUE_IS_NOT_INIT; + } + + if (dir_flag == DPP_DTB_DIR_UP_TYPE) + { + addr = DPP_DTB_TAB_UP_VIR_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, index) + pos * 4; + } + else + { + addr = DPP_DTB_TAB_DOWN_VIR_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, index) + pos * 4; + } + + rc = dpp_dtb_wr32(dev, addr, data); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_wr32"); + + return DPP_OK; +} + +/***********************************************************/ +/** 打印队列指定条目ACK信息 +* @param dev_id 芯片的id号 +* @param queue_id 队列号，范围0-127 +* @param dir_flag 方向,0-down,1-up +* @param index 条目索引 +* +* @return +* @remark 无 +* @see +* @author zab @date 2022/08/30 +************************************************************/ +ZXIC_UINT32 dpp_dtb_item_ack_prt(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 dir_flag, + ZXIC_UINT32 index) +{ + ZXIC_UINT32 rc = 0; + ZXIC_UINT32 i = 0; + ZXIC_UINT32 ack_data[4] = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX_NO_ASSERT(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), dir_flag, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), index, 0, DPP_DTB_QUEUE_ITEM_NUM_MAX -1); + + for (i = 0; i < DPP_DTB_ITEM_ACK_SIZE / 4; i++) + { + rc = dpp_dtb_item_ack_rd(dev, queue_id, dir_flag, index, i, ack_data + i); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_dtb_item_ack_rd"); + } + + ZXIC_COMM_PRINT("\n=====> [%s] BD INFO:", g_dpp_dtb_name[dir_flag]); + ZXIC_COMM_PRINT("\n[ index : %u] : 0x%08x 0x%08x 0x%08x 0x%08x \n", index, ack_data[0], ack_data[1], ack_data[2], ack_data[3]); + + return DPP_OK; +} + +/***********************************************************/ +/** 打印队列指定条目BUFF的数据 +* @param dev_id 芯片的id号 +* @param queue_id 队列号，范围0-127 +* @param dir_flag 方向,0-down,1-up +* @param index 条目索引 +* @param len 读取数据长度 4字节为单位 +* +* @return +* @remark 无 +* @see +* @author zab @date 2022/08/30 +************************************************************/ +ZXIC_UINT32 dpp_dtb_item_buff_prt(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 dir_flag, + ZXIC_UINT32 index, + ZXIC_UINT32 len) +{ + ZXIC_UINT32 rc = 0; + ZXIC_UINT32 i = 0; + ZXIC_UINT32 j = 0; + ZXIC_UINT32 *p_item_buff = ZXIC_NULL; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX_NO_ASSERT(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), dir_flag, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), index, 0, DPP_DTB_QUEUE_ITEM_NUM_MAX -1); + + p_item_buff = ZXIC_COMM_MALLOC((len * sizeof(ZXIC_UINT32)) % ZXIC_COMM_WORD32_MASK); + if (p_item_buff == ZXIC_NULL) + { + ZXIC_COMM_PRINT("Alloc dtb item buffer faild!!!\n"); + return DPP_RC_DTB_MEMORY_ALLOC_ERR; + } + + ZXIC_COMM_MEMSET(p_item_buff, 0, len * sizeof(ZXIC_UINT32)); + + rc = dpp_dtb_item_buff_rd(dev, queue_id, dir_flag, index, 0, len, p_item_buff); + ZXIC_COMM_CHECK_DEV_RC_MEMORY_FREE(DEV_ID(dev), rc, "dpp_dtb_item_buff_rd", p_item_buff); + + ZXIC_COMM_PRINT("\n=====> [%s] BUFF INFO:", g_dpp_dtb_name[dir_flag]); + for(i = 0, j = 0; i < len; i++, j++) + { + if(j % 4 == 0) + { + ZXIC_COMM_PRINT("\n0x%08x ", (*(p_item_buff + i))); + } + else + { + ZXIC_COMM_PRINT("0x%08x ", (*(p_item_buff + i))); + } + } + ZXIC_COMM_PRINT("\n"); + + ZXIC_COMM_FREE(p_item_buff); + + return DPP_OK; +} + +#endif + + +#if ZXIC_REAL("BUFF_RW") + +/***********************************************************/ +/** 读取dtb条目指向BUFF的数据 +* @param dev_id 芯片的id号 +* @param queue_id 队列号,范围0-127 +* @param dir_flag 方向,1-上送表项,0-下发表项 +* @param index 条目索引,范围0-31 +* @param pos 相对BUFF起始地址的偏移,单位32bit; +* @param p_data 读取的数据,大端格式 +* @param len 读取数据长度,单位32bit; +* +* @return +* @remark 无 +* @see +* @author zab @date 2019/11/2 +************************************************************/ +ZXIC_UINT32 dpp_dtb_item_buff_rd(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 dir_flag, + ZXIC_UINT32 index, + ZXIC_UINT32 pos, + ZXIC_UINT32 len, + ZXIC_UINT32 *p_data) +{ + ZXIC_ADDR_T addr = 0; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), dir_flag, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), index, 0, DPP_DTB_QUEUE_ITEM_NUM_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), pos, 0, 3); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data); + + if(DPP_DTB_QUEUE_INIT_FLAG_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id) == 0) + { + ZXIC_COMM_TRACE_ERROR("dtb slot %d queue %d is not init.\n", DEV_PCIE_SLOT(dev), queue_id); + return DPP_RC_DTB_QUEUE_IS_NOT_INIT; + } + + if (dir_flag == DPP_DTB_DIR_UP_TYPE) + { + if (DPP_DTB_TAB_UP_USER_PHY_ADDR_FLAG_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, index) == DPP_DTB_TAB_UP_USER_ADDR_TYPE) + { + addr = DPP_DTB_TAB_UP_USER_VIR_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, index) + pos * 4; + DPP_DTB_TAB_UP_USER_ADDR_FLAG_SET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, index, 0);//为什么设置为0？ + } + else + { + addr = DPP_DTB_TAB_UP_VIR_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, index) + DPP_DTB_ITEM_ACK_SIZE + pos * 4; + } + } + else + { + addr = DPP_DTB_TAB_DOWN_VIR_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, index) + DPP_DTB_ITEM_ACK_SIZE + pos * 4; + } + + ZXIC_COMM_MEMCPY_S(p_data, len * 4, (ZXIC_UINT8 *)(addr), len * 4); + + zxic_comm_swap((ZXIC_UINT8*)p_data, len * 4); + + return DPP_OK; +} + +/***********************************************************/ +/** 向BD表条目指向的BUFF指定位置写入值 +* @param dev_id 芯片的id号 +* @param queue_id 队列号,范围0-127 +* @param dir_flag 方向,1-上送表项,0-下发表项 +* @param index 条目索引,范围0-31 +* @param pos 相对BUFF起始地址的偏移,单位32bit; +* @param p_data 读取的数据,大端格式 +* @param len 写入数据长度,单位32bit; +* +* @return +* @remark 无 +* @see +* @author zab @date 2019/11/2 +************************************************************/ +ZXIC_UINT32 dpp_dtb_item_buff_wr(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 dir_flag, + ZXIC_UINT32 index, + ZXIC_UINT32 pos, + ZXIC_UINT32 len, + ZXIC_UINT32 *p_data) +{ + ZXIC_ADDR_T addr = 0; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), dir_flag, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), index, 0, DPP_DTB_QUEUE_ITEM_NUM_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), pos, 0, 3); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data); + + if(DPP_DTB_QUEUE_INIT_FLAG_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id) == 0) + { + ZXIC_COMM_TRACE_ERROR("dtb slot %d queue %d is not init.\n", DEV_PCIE_SLOT(dev), queue_id); + return DPP_RC_DTB_QUEUE_IS_NOT_INIT; + } + + if (dir_flag == DPP_DTB_DIR_UP_TYPE) + { + addr = DPP_DTB_TAB_UP_VIR_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, index) + DPP_DTB_ITEM_ACK_SIZE + pos * 4; + } + else + { + addr = DPP_DTB_TAB_DOWN_VIR_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, index) + DPP_DTB_ITEM_ACK_SIZE + pos * 4; + } + + ZXIC_COMM_MEMCPY_S((ZXIC_UINT8 *)(addr), len * 4, p_data, len * 4); + + // dpp_flush_cache();//片内ddr使用 + + return DPP_OK; +} +#endif + +#if ZXIC_REAL("API") +#if ZXIC_REAL("TAB_DOWN") + +/** dtb info print*/ +ZXIC_UINT32 dpp_dtb_info_print(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 item_index, + DPP_DTB_QUEUE_ITEM_INFO_T *item_info) +{ + ZXIC_ADDR_T element_start_addr = 0; + ZXIC_ADDR_T ack_start_addr = 0; + ZXIC_ADDR_T data_addr = 0; + ZXIC_UINT32 data = 0; + ZXIC_UINT32 i = 0; + ZXIC_UINT32 j = 0; + + ZXIC_COMM_CHECK_POINT(dev); + + ZXIC_COMM_PRINT("dpp_dtb_info_print: slot %d queue: %d, element:%d, %s table info is:\n", DEV_PCIE_SLOT(dev), queue_id, item_index, + (item_info->cmd_type) ? "up" : "down"); + ZXIC_COMM_PRINT("cmd_vld : %d\n", item_info->cmd_vld); + ZXIC_COMM_PRINT("cmd_type : %s\n", (item_info->cmd_type) ? "up" : "down"); + ZXIC_COMM_PRINT("int_en : %d\n", item_info->int_en); + ZXIC_COMM_PRINT("data_len : %d\n", item_info->data_len); + ZXIC_COMM_PRINT("data_hddr : 0x%08x\n", item_info->data_hddr); + ZXIC_COMM_PRINT("data_laddr : 0x%08x\n", item_info->data_laddr); + + if (item_info->cmd_type == DPP_DTB_DIR_UP_TYPE) + { + if (DPP_DTB_TAB_UP_USER_PHY_ADDR_FLAG_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, item_index) == DPP_DTB_TAB_UP_USER_ADDR_TYPE) + { + ack_start_addr = DPP_DTB_TAB_UP_USER_VIR_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, item_index); + } + ack_start_addr = DPP_DTB_TAB_UP_VIR_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, item_index); + element_start_addr = DPP_DTB_TAB_UP_VIR_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, item_index) + DPP_DTB_ITEM_ACK_SIZE; + } + else + { + ack_start_addr = DPP_DTB_TAB_DOWN_VIR_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, item_index); + element_start_addr = DPP_DTB_TAB_DOWN_VIR_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, item_index) + DPP_DTB_ITEM_ACK_SIZE; + } + ZXIC_COMM_PRINT("dtb data:\n"); + + ZXIC_COMM_PRINT("ack info:\n"); + for(j = 0; j < 4; j++) + { + data = ZXIC_COMM_CONVERT32(*((ZXIC_UINT32 *)(ack_start_addr + 4 * j))); + + ZXIC_COMM_PRINT("0x%08x ",data); + } + ZXIC_COMM_PRINT("\n"); + + for (i = 0; i < item_info->data_len; i++) + { + data_addr = element_start_addr + 16 * i;//16字节为一行 + + ZXIC_COMM_PRINT("row_%d:", i); + + for(j = 0; j < 4; j++) + { + data = ZXIC_COMM_CONVERT32(*((ZXIC_UINT32 *)(data_addr + 4 * j))); + + ZXIC_COMM_PRINT("0x%08x ",data); + } + + ZXIC_COMM_PRINT("\n"); + } + + ZXIC_COMM_PRINT("dpp dtb info print end.\n"); + return DPP_OK; +} + +/***********************************************************/ +/** 配置下发配置数据信息 +* @param dev_id 设备号，支持多芯片 +* @param queue_id 队列号，范围0-31 +* @param int_flag 中断标志，0-无，1-有 +* @param data_len 数据长度，单位32bit; +* @param p_data 待下发数据 +* @param p_item_index 返回使用的条目编号 +* +* @return +* @remark 无 +* @see +* @author zab @date 2021/02/23 +************************************************************/ +ZXIC_UINT32 dpp_dtb_tab_down_info_set(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 int_flag, + ZXIC_UINT32 data_len, + ZXIC_UINT32 *p_data, + ZXIC_UINT32 *p_item_index) +{ + ZXIC_UINT32 rc = 0; + ZXIC_UINT32 i = 0; + ZXIC_UINT32 queue_en = 0; + ZXIC_UINT32 ack_vale = 0; + ZXIC_UINT32 item_index = 0; + ZXIC_UINT32 unused_item_num = 0; + DPP_DTB_QUEUE_ITEM_INFO_T item_info = {0}; + ZXIC_MUTEX_T *p_mutex = NULL; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), int_flag, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), data_len, 4, 0xffc); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_item_index); + + rc = dpp_dev_dtb_opr_mutex_get(DEV_ID(dev), DPP_DEV_MUTEX_T_DTB, queue_id, &p_mutex); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dev_dtb_opr_mutex_get"); + + rc = zxic_comm_mutex_lock(p_mutex); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev),rc,"zxic_comm_mutex_lock"); + + /* + * 流程 + * 0.检测队列是否使能 + * 1.检测当前队列是否已初始化; + * 2.获取硬件队列剩余情况，大于0正常下发，等于0返回失败； + * 3.获取软件缓存空闲情况； + * 4.将下表配置数据填入buff中； + * 5.将ack字段填入0x11111100; + * 6.将数据信息填入硬件触发寄存器中; + * + */ +#if 0 + if(dpp_dtb_mode_is_debug(dev)) + { + ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "the queue %d is open debug mode!", queue_id); + rc = zxic_comm_mutex_unlock(p_mutex); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "zxic_comm_mutex_unlock"); + return DPP_RC_DTB_OPEN_DEBUG_MODE; + } +#endif + + rc = dpp_dtb_queue_enable_get(dev, queue_id, &queue_en); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_dtb_queue_enable_get", p_mutex); + if(!queue_en) + { + ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "the slot %d queue %d is not enable!", DEV_PCIE_SLOT(dev), queue_id); + rc = zxic_comm_mutex_unlock(p_mutex); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev),rc,"zxic_comm_mutex_unlock"); + return DPP_RC_DTB_QUEUE_NOT_ENABLE; + } + + if(DPP_DTB_QUEUE_INIT_FLAG_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id) == 0) + { + ZXIC_COMM_TRACE_ERROR("dtb slot %d queue %d is not init.\n", DEV_PCIE_SLOT(dev), queue_id); + rc = zxic_comm_mutex_unlock(p_mutex); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev),rc,"zxic_comm_mutex_unlock"); + return DPP_RC_DTB_QUEUE_IS_NOT_INIT; + } + + if (data_len % 4 != 0) + { + rc = zxic_comm_mutex_unlock(p_mutex); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev),rc,"zxic_comm_mutex_unlock"); + /* 硬件规定数据必须是16字节为单位 */ + return DPP_RC_DTB_PARA_INVALID; + } + + rc = dpp_dtb_queue_unused_item_num_get(dev, queue_id, &unused_item_num); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_dtb_queue_unused_item_num_get", p_mutex); + + if (unused_item_num == 0) + { + rc = zxic_comm_mutex_unlock(p_mutex); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev),rc,"zxic_comm_mutex_unlock"); + return DPP_RC_DTB_QUEUE_ITEM_HW_EMPTY; + } + + for (i = 0; i < DPP_DTB_QUEUE_ITEM_NUM_MAX; i++) + { + item_index = DPP_DTB_TAB_DOWN_WR_INDEX_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id) % DPP_DTB_QUEUE_ITEM_NUM_MAX; + + rc = dpp_dtb_item_ack_rd(dev, queue_id, DPP_DTB_DIR_DOWN_TYPE, item_index, 0, &ack_vale); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_dtb_item_ack_rd", p_mutex); + + DPP_DTB_TAB_DOWN_WR_INDEX_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id)++; + + if ((ack_vale >> 8) == DPP_DTB_TAB_ACK_UNUSED_MASK) + { + break; + } + } + + if (i == DPP_DTB_QUEUE_ITEM_NUM_MAX) + { + rc = zxic_comm_mutex_unlock(p_mutex); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev),rc,"zxic_comm_mutex_unlock"); + return DPP_RC_DTB_QUEUE_ITEM_SW_EMPTY; + } + + rc = dpp_dtb_item_buff_wr(dev, queue_id, DPP_DTB_DIR_DOWN_TYPE, item_index, 0, data_len, p_data); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_dtb_item_buff_wr", p_mutex); + + rc = dpp_dtb_item_ack_wr(dev, queue_id, DPP_DTB_DIR_DOWN_TYPE, item_index, 0, DPP_DTB_TAB_ACK_IS_USING_MASK); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_dtb_item_ack_wr", p_mutex); + + item_info.cmd_vld = 1; + item_info.cmd_type = DPP_DTB_DIR_DOWN_TYPE; + item_info.int_en = int_flag; + item_info.data_len = data_len / 4; + item_info.data_hddr = ((DPP_DTB_TAB_DOWN_PHY_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, item_index)>>4)>>32) & 0xffffffff; + item_info.data_laddr = (DPP_DTB_TAB_DOWN_PHY_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, item_index)>>4) & 0xffffffff; + + if(item_info.data_len < DPP_DTB_LEN_MIN || item_info.data_len > DPP_DTB_DOWN_LEN) + { + ZXIC_COMM_PRINT("DTB DATA_LEN :0x%08x.\n",item_info.data_len); + rc = dpp_dtb_item_ack_wr(dev, queue_id, DPP_DTB_DIR_DOWN_TYPE, item_index, 0, DPP_DTB_TAB_ACK_UNUSED_MASK); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_item_ack_wr"); + rc = zxic_comm_mutex_unlock(p_mutex); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev),rc,"zxic_comm_mutex_unlock"); + return DPP_RC_DTB_PARA_INVALID; + } + + if(dpp_dtb_prt_get()) + { + dpp_dtb_info_print(dev, queue_id, item_index, &item_info); + } + + if(DPP_DEV_TYPE_SIM == dpp_dev_get_dev_type(DEV_ID(dev))) + { + *p_item_index = item_index; + rc = zxic_comm_mutex_unlock(p_mutex); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev),rc,"zxic_comm_mutex_unlock"); + return DPP_OK; + } + + if(dpp_dtb_soft_perf_test_get()) + { + *p_item_index = item_index; + rc = zxic_comm_mutex_unlock(p_mutex); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev),rc,"zxic_comm_mutex_unlock"); + return DPP_OK; + } + + rc = dpp_dtb_queue_item_info_set(dev, queue_id, &item_info); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_dtb_queue_item_info_set", p_mutex); + *p_item_index = item_index; + + rc = zxic_comm_mutex_unlock(p_mutex); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev),rc,"zxic_comm_mutex_unlock"); + + return DPP_OK; +} + +/***********************************************************/ +/** 打印下表队列中指定元素的地址、ACK及下表中前768bit的数据 +* @param dev_id 芯片的id号 +* @param queue_id 队列号，范围0-127 +* @param element_id 元素号，范围0-31 +* +* @return +* @remark 无 +* @see +* @author zab @date 2022/08/30 +************************************************************/ +ZXIC_UINT32 dpp_dtb_down_table_element_info_prt(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 element_id) +{ + ZXIC_UINT32 rc = 0; + + ZXIC_UINT32 element_start_addr_h = 0; + ZXIC_UINT32 element_start_addr_l = 0; + ZXIC_UINT32 element_table_addr_h = 0; + ZXIC_UINT32 element_table_addr_l = 0; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), element_id, 0, DPP_DTB_QUEUE_ITEM_NUM_MAX - 1); + + rc = dpp_dtb_down_table_elemet_addr_get(dev, + queue_id, + element_id, + &element_start_addr_h, + &element_start_addr_l, + &element_table_addr_h, + &element_table_addr_l); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_dtb_elemet_addr_get"); + + ZXIC_COMM_DBGCNT32_PRINT("slot_id", DEV_PCIE_SLOT(dev)); + ZXIC_COMM_DBGCNT32_PRINT("queue_id", queue_id); + ZXIC_COMM_DBGCNT32_PRINT("element_id", element_id); + ZXIC_COMM_DBGCNT32_PRINT("element_start_addr_h", element_start_addr_h); + ZXIC_COMM_DBGCNT32_PRINT("element_start_addr_l", element_start_addr_l); + ZXIC_COMM_DBGCNT32_PRINT("element_table_addr_h", element_table_addr_h); + ZXIC_COMM_DBGCNT32_PRINT("element_table_addr_l", element_table_addr_l); + + /*打印element ack*/ + rc = dpp_dtb_item_ack_prt(dev, queue_id, DPP_DTB_DIR_DOWN_TYPE, element_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_dtb_item_ack_prt"); + + rc = dpp_dtb_item_buff_prt(dev, queue_id, DPP_DTB_DIR_DOWN_TYPE, element_id, 24); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_dtb_item_buff_prt"); + + return DPP_OK; +} + +/***********************************************************/ +/** 一个元素down成功状态检查 +* @param dev_id 设备号，支持多芯片 +* @param queue_id 队列号，范围0-31 +* @param element_id 条目编号 +* +* @return +* @remark 无 +* @see +* @author zab @date 2021/02/23 +************************************************************/ +ZXIC_UINT32 dpp_dtb_tab_down_success_status_check(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 element_id) +{ + ZXIC_UINT32 rc = 0; + ZXIC_UINT32 rd_cnt = 0; + ZXIC_UINT32 ack_value = 0; + ZXIC_UINT32 success_flag = 0; + ZXIC_UINT32 dtb_interrupt_status = 0; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), element_id, 0, DPP_DTB_QUEUE_ITEM_NUM_MAX - 1); + + dtb_interrupt_status = dpp_dtb_interrupt_status_get(); + + if(DPP_DEV_TYPE_SIM == dpp_dev_get_dev_type(DEV_ID(dev))) + { + rc = dpp_dtb_item_ack_wr(dev, queue_id, DPP_DTB_DIR_DOWN_TYPE, element_id, 0, DPP_DTB_TAB_ACK_UNUSED_MASK); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_item_ack_wr"); + return rc; + } + + if(dpp_dtb_soft_perf_test_get() || dpp_dtb_hardware_perf_test_get()) + { + rc = dpp_dtb_item_ack_wr(dev, queue_id, DPP_DTB_DIR_DOWN_TYPE, element_id, 0, DPP_DTB_TAB_ACK_UNUSED_MASK); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_item_ack_wr"); + return rc; + } + + if(dpp_dtb_debug_fun_get()) + { + return DPP_OK; + } + + while(!success_flag) + { + rc = dpp_dtb_item_ack_rd(dev, queue_id, DPP_DTB_DIR_DOWN_TYPE, element_id, 0, &ack_value); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_item_ack_rd"); + + ZXIC_COMM_TRACE_DEBUG("dpp_dtb_item_ack_rd ack_value:0x%08x\n", ack_value); + + if (((ack_value >> 8) & 0xffffff) == DPP_DTB_TAB_DOWN_ACK_VLD_MASK) + { + success_flag = 1; + break; + } + + if (rd_cnt > dpp_dtb_down_table_overtime_get()) + { + ZXIC_COMM_TRACE_ERROR("Error!!! dpp dtb down slot [%d] vport [0x%x] queue [%d] item [%d] ack success is overtime!\n", DEV_PCIE_SLOT(dev), DEV_PCIE_VPORT(dev), queue_id, element_id); + + ZXIC_COMM_PRINT("-------------------------------------------------------------------\n"); + ZXIC_COMM_PRINT(" dtb down table info \n"); + ZXIC_COMM_PRINT("-------------------------------------------------------------------\n"); + rc = dpp_dtb_down_table_element_info_prt(dev, queue_id, element_id); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_down_table_element_info_prt"); + + rc = dpp_dtb_item_ack_wr(dev, queue_id, DPP_DTB_DIR_DOWN_TYPE, element_id, 0, DPP_DTB_TAB_ACK_UNUSED_MASK); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_item_ack_wr"); + + ZXIC_COMM_PRINT("-------------------------------------------------------------------\n"); + ZXIC_COMM_PRINT(" dtb reg info \n"); + ZXIC_COMM_PRINT("-------------------------------------------------------------------\n"); + + rc = diag_dpp_dtb_axi_last_operate_info_prt(dev); + ZXIC_COMM_CHECK_DEV_RC(0, rc, "diag_dpp_dtb_axi_last_operate_info_prt"); + + rc = diag_dpp_dtb_channels_state_info_prt(dev); + ZXIC_COMM_CHECK_DEV_RC(0, rc, "diag_dpp_dtb_channels_state_info_prt"); + + rc = diag_dpp_dtb_channels_axi_resp_err_cnt_prt(dev); + ZXIC_COMM_CHECK_DEV_RC(0, rc, "diag_dpp_dtb_channels_axi_resp_err_cnt_prt"); + + return DPP_RC_DTB_OVER_TIME; + } + + rd_cnt++; + zxic_comm_udelay(1); + } + + if (dtb_interrupt_status) + { + /*清中断*/ + rc = dpp_dtb_finish_interrupt_event_state_clr(dev, queue_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_dtb_finish_interrupt_event_state_clr"); + } + + if ((ack_value & 0xff) != DPP_DTB_TAB_ACK_SUCCESS_MASK) + { + rc = dpp_dtb_item_ack_wr(dev, queue_id, DPP_DTB_DIR_DOWN_TYPE, element_id, 0, DPP_DTB_TAB_ACK_UNUSED_MASK); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_item_ack_wr"); + return ack_value & 0xff; + } + + rc = dpp_dtb_item_ack_wr(dev, queue_id, DPP_DTB_DIR_DOWN_TYPE, element_id, 0, DPP_DTB_TAB_ACK_UNUSED_MASK); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_item_ack_wr"); + + return rc; +} + +#endif +#if ZXIC_REAL("TAB_UP") +/***********************************************************/ +/** dump队列空闲条目获取 +* @param dev_id 设备号，支持多芯片 +* @param queue_id 队列号，范围0-31 +* @param p_item_index 返回使用的条目编号 +* @return +* @remark 无 +* @see +* @author zab @date 2021/02/23 +************************************************************/ +ZXIC_UINT32 dpp_dtb_tab_up_free_item_get(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 *p_item_index) +{ + ZXIC_UINT32 rc = 0; + ZXIC_UINT32 i = 0; + ZXIC_UINT32 ack_vale = 0; + ZXIC_UINT32 item_index = 0; + ZXIC_UINT32 unused_item_num = 0; + ZXIC_MUTEX_T *p_mutex = NULL; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_item_index); + + rc = dpp_dev_dtb_opr_mutex_get(DEV_ID(dev), DPP_DEV_MUTEX_T_DTB, queue_id, &p_mutex); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dev_dtb_opr_mutex_get"); + + rc = zxic_comm_mutex_lock(p_mutex); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev),rc,"zxic_comm_mutex_lock"); + + /* + * 流程 + * 1.获取硬件队列剩余情况，大于0正常上送，等于0返回失败； + * 2.获取软件缓存空闲情况； + * + */ + if(DPP_DTB_QUEUE_INIT_FLAG_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id) == 0) + { + ZXIC_COMM_TRACE_ERROR("dtb slot %d queue %d is not init.\n", DEV_PCIE_SLOT(dev), queue_id); + rc = zxic_comm_mutex_unlock(p_mutex); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev),rc,"zxic_comm_mutex_unlock"); + return DPP_RC_DTB_QUEUE_IS_NOT_INIT; + } + + rc = dpp_dtb_queue_unused_item_num_get(dev, queue_id, &unused_item_num); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_dtb_queue_unused_item_num_get", p_mutex); + + if (unused_item_num == 0) + { + rc = zxic_comm_mutex_unlock(p_mutex); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev),rc,"zxic_comm_mutex_unlock"); + return DPP_RC_DTB_QUEUE_ITEM_HW_EMPTY; + } + + for (i = 0; i < DPP_DTB_QUEUE_ITEM_NUM_MAX; i++) + { + item_index = DPP_DTB_TAB_UP_WR_INDEX_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id) % DPP_DTB_QUEUE_ITEM_NUM_MAX; + + rc = dpp_dtb_item_ack_rd(dev, queue_id, DPP_DTB_DIR_UP_TYPE, item_index, 0, &ack_vale); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_dtb_item_ack_rd", p_mutex); + + DPP_DTB_TAB_UP_WR_INDEX_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id)++; + + if ((ack_vale >> 8) == DPP_DTB_TAB_ACK_UNUSED_MASK) + { + break; + } + } + + if (i == DPP_DTB_QUEUE_ITEM_NUM_MAX) + { + rc = zxic_comm_mutex_unlock(p_mutex); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev),rc,"zxic_comm_mutex_unlock"); + return DPP_RC_DTB_QUEUE_ITEM_SW_EMPTY; + } + + rc = dpp_dtb_item_ack_wr(dev, queue_id, DPP_DTB_DIR_UP_TYPE, item_index, 0, DPP_DTB_TAB_ACK_IS_USING_MASK); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_dtb_item_buff_wr", p_mutex); + + *p_item_index = item_index; + + rc = zxic_comm_mutex_unlock(p_mutex); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev),rc,"zxic_comm_mutex_unlock"); + + return DPP_OK; +} + +/***********************************************************/ +/** 获取dump指定条目物理地址 +* @param dev_id 设备号，支持多芯片 +* @param queue_id 队列编号,范围:0-127 +* @param item_index 条目编号,范围0-31 +* @param p_phy_haddr 物理地址高32bit +* @param p_phy_laddr 物理地址低32bit +* +* @return +* @remark 无 +* @see +* @author zab @date 2021/02/23 +************************************************************/ +ZXIC_UINT32 dpp_dtb_tab_up_item_addr_get(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 item_index, + ZXIC_UINT32 *p_phy_haddr, + ZXIC_UINT32 *p_phy_laddr) +{ + ZXIC_ADDR_T addr = 0; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), item_index, 0, DPP_DTB_QUEUE_ITEM_NUM_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_phy_haddr); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_phy_laddr); + + if(DPP_DTB_QUEUE_INIT_FLAG_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id) == 0) + { + ZXIC_COMM_TRACE_ERROR("dtb slot %d queue %d is not init.\n", DEV_PCIE_SLOT(dev), queue_id); + return DPP_RC_DTB_QUEUE_IS_NOT_INIT; + } + + if (DPP_DTB_TAB_UP_USER_PHY_ADDR_FLAG_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, item_index) == DPP_DTB_TAB_UP_USER_ADDR_TYPE) + { + addr = DPP_DTB_TAB_UP_USER_PHY_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, item_index); + } + else + { + addr = DPP_DTB_TAB_UP_PHY_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, item_index) + DPP_DTB_ITEM_ACK_SIZE; + } + + + /*将地址转换成16字节为单位*/ + // addr = addr >> 4; + + *p_phy_haddr = (addr >> 32) & 0xffffffff; + *p_phy_laddr = addr & 0xffffffff; + + return DPP_OK; +} + +/***********************************************************/ +/** 获取指定dump条目一定地址偏移的物理地址 +* @param dev_id 设备号，支持多芯片 +* @param queue_id 队列编号,范围:0-127 +* @param item_index 条目编号,范围0-31 +* @param p_phy_haddr 物理地址高32bit +* @param p_phy_laddr 物理地址低32bit +* +* @return +* @remark 无 +* @see +* @author zab @date 2021/02/23 +************************************************************/ +ZXIC_UINT32 dpp_dtb_tab_up_item_offset_addr_get(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 item_index, + ZXIC_UINT32 addr_offset, + ZXIC_UINT32 *p_phy_haddr, + ZXIC_UINT32 *p_phy_laddr) +{ + ZXIC_ADDR_T addr = 0; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), item_index, 0, DPP_DTB_QUEUE_ITEM_NUM_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_phy_haddr); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_phy_laddr); + + if(DPP_DTB_QUEUE_INIT_FLAG_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id) == 0) + { + ZXIC_COMM_TRACE_ERROR("dtb slot %d queue %d is not init.\n", DEV_PCIE_SLOT(dev), queue_id); + return DPP_RC_DTB_QUEUE_IS_NOT_INIT; + } + + if (DPP_DTB_TAB_UP_USER_PHY_ADDR_FLAG_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, item_index) == DPP_DTB_TAB_UP_USER_ADDR_TYPE) + { + addr = DPP_DTB_TAB_UP_USER_PHY_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, item_index); + } + else + { + addr = DPP_DTB_TAB_UP_PHY_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, item_index) + DPP_DTB_ITEM_ACK_SIZE; + } + + addr = addr + addr_offset; + + *p_phy_haddr = (addr >> 32) & 0xffffffff; + *p_phy_laddr = addr & 0xffffffff; + + return DPP_OK; +} + +/***********************************************************/ +/** 设置dump指定条目空间地址，用于用户自定义空间传输 +* @param dev_id 设备号，支持多芯片 +* @param queue_id 队列编号,范围:0-127 +* @param item_index 条目编号,范围0-31 +* @param phy_haddr 物理地址高 +* @param vir_laddr 虚拟地址低 +* +* @return +* @remark 无 +* @see +* @author zab @date 2021/02/23 +************************************************************/ +ZXIC_UINT32 dpp_dtb_tab_up_item_user_addr_set(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 item_index, + ZXIC_ADDR_T phy_addr, + ZXIC_ADDR_T vir_addr) +{ + DPP_DTB_MGR_T *p_dtb_mgr = ZXIC_NULL; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), item_index, 0, DPP_DTB_QUEUE_ITEM_NUM_MAX - 1); + + p_dtb_mgr = dpp_dtb_mgr_get(DEV_PCIE_SLOT(dev), DEV_ID(dev)); + if (p_dtb_mgr == ZXIC_NULL) + { + ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "slot %d ErrorCode[0x%x]: DTB Manager is not exist!!!\n", DEV_PCIE_SLOT(dev), DPP_RC_DTB_MGR_NOT_EXIST); + return DPP_RC_DTB_MGR_NOT_EXIST; + } + + if(DPP_DTB_QUEUE_INIT_FLAG_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id) == 0) + { + ZXIC_COMM_TRACE_ERROR("dtb slot %d queue %d is not init.\n", DEV_PCIE_SLOT(dev), queue_id); + return DPP_RC_DTB_QUEUE_IS_NOT_INIT; + } + + p_dtb_mgr->queue_info[queue_id].tab_up.user_addr[item_index].phy_addr = phy_addr; + p_dtb_mgr->queue_info[queue_id].tab_up.user_addr[item_index].vir_addr = vir_addr; + p_dtb_mgr->queue_info[queue_id].tab_up.user_addr[item_index].user_flag = DPP_DTB_TAB_UP_USER_ADDR_TYPE; + + return DPP_OK; +} + +/***********************************************************/ +/** 清除用户dump指定条目空间地址 +* @param dev_id 设备号，支持多芯片 +* @param queue_id 队列编号,范围:0-127 +* @param item_index 条目编号,范围0-31 +* +* @return +* @remark 无 +* @see +* @author zab @date 2021/02/23 +************************************************************/ +ZXIC_UINT32 dpp_dtb_tab_up_item_user_addr_clr(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 item_index) +{ + DPP_DTB_MGR_T *p_dtb_mgr = ZXIC_NULL; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), item_index, 0, DPP_DTB_QUEUE_ITEM_NUM_MAX - 1); + + p_dtb_mgr = dpp_dtb_mgr_get(DEV_PCIE_SLOT(dev), DEV_ID(dev)); + if (p_dtb_mgr == ZXIC_NULL) + { + ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "slot %d ErrorCode[0x%x]: DTB Manager is not exist!!!\n", DEV_PCIE_SLOT(dev), DPP_RC_DTB_MGR_NOT_EXIST); + return DPP_RC_DTB_MGR_NOT_EXIST; + } + + if(DPP_DTB_QUEUE_INIT_FLAG_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id) == 0) + { + ZXIC_COMM_TRACE_ERROR("dtb slot %d queue %d is not init.\n", DEV_PCIE_SLOT(dev), queue_id); + return DPP_RC_DTB_QUEUE_IS_NOT_INIT; + } + + p_dtb_mgr->queue_info[queue_id].tab_up.user_addr[item_index].phy_addr = 0; + p_dtb_mgr->queue_info[queue_id].tab_up.user_addr[item_index].vir_addr = 0; + p_dtb_mgr->queue_info[queue_id].tab_up.user_addr[item_index].user_flag = DPP_DTB_TAB_UP_NOUSER_ADDR_TYPE; + + return DPP_OK; +} + + +/***********************************************************/ +/** dump配置描述符信息设置 +* @param dev_id 设备号，支持多芯片 +* @param queue_id 队列号，范围0-31 +* @param item_index 返回使用的条目编号 +* @param int_flag 中断标志，0-无，1-有 +* @param data_len 数据长度，单位32bit; +* @param desc_len 描述符长度，单位32bit; +* @param p_desc_data 待下发描述符 +* @return +* @remark 无 +* @see +* @author zab @date 2021/02/23 +************************************************************/ +ZXIC_UINT32 dpp_dtb_tab_up_info_set(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 item_index, + ZXIC_UINT32 int_flag, + ZXIC_UINT32 data_len, + ZXIC_UINT32 desc_len, + ZXIC_UINT32 *p_desc_data) +{ + ZXIC_UINT32 rc = 0; + ZXIC_UINT32 queue_en = 0; + DPP_DTB_QUEUE_ITEM_INFO_T item_info = {0}; + ZXIC_MUTEX_T *p_mutex = NULL; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), item_index, 0, DPP_DTB_QUEUE_ITEM_NUM_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), desc_len, 0, 0x400); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), int_flag, 0, 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_desc_data); + + rc = dpp_dev_dtb_opr_mutex_get(DEV_ID(dev), DPP_DEV_MUTEX_T_DTB, queue_id, &p_mutex); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dev_dtb_opr_mutex_get"); + + rc = zxic_comm_mutex_lock(p_mutex); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev),rc,"zxic_comm_mutex_lock"); + + /* + * 流程 + * 0.检测队列是否使能 + * 1.获取硬件队列剩余情况，大于0正常下发，等于0返回失败； + * 2.获取软件缓存空闲情况； + * 3.将dump描述符写入buff中; + * 4.将ack字段填入0x11111100; + * 5.将数据信息填入硬件触发寄存器中; + * + */ +#if 0 + if(dpp_dtb_mode_is_debug(dev)) + { + ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "the queue %d is open debug mode!", queue_id); + rc = zxic_comm_mutex_unlock(p_mutex); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "zxic_comm_mutex_unlock"); + return DPP_RC_DTB_OPEN_DEBUG_MODE; + } +#endif + + rc = dpp_dtb_queue_enable_get(dev, queue_id, &queue_en); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_dtb_queue_enable_get", p_mutex); + if(!queue_en) + { + ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "the slot %d queue %d is not enable!", DEV_PCIE_SLOT(dev), queue_id); + rc = zxic_comm_mutex_unlock(p_mutex); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev),rc,"zxic_comm_mutex_unlock"); + ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "the queue %d is not enable!", queue_id); + return DPP_RC_DTB_QUEUE_NOT_ENABLE; + } + + if(DPP_DTB_QUEUE_INIT_FLAG_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id) == 0) + { + ZXIC_COMM_TRACE_ERROR("dtb slot %d queue %d is not init.\n", DEV_PCIE_SLOT(dev), queue_id); + rc = zxic_comm_mutex_unlock(p_mutex); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev),rc,"zxic_comm_mutex_unlock"); + return DPP_RC_DTB_QUEUE_IS_NOT_INIT; + } + + if (desc_len % 4 != 0) + { + rc = zxic_comm_mutex_unlock(p_mutex); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev),rc,"zxic_comm_mutex_unlock"); + /* 硬件规定数据必须是16字节为单位 */ + return DPP_RC_DTB_PARA_INVALID; + } + + rc = dpp_dtb_item_buff_wr(dev, queue_id, DPP_DTB_DIR_UP_TYPE, item_index, 0, desc_len, p_desc_data); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_dtb_item_buff_wr", p_mutex); + + + rc = dpp_dtb_item_ack_wr(dev, queue_id, DPP_DTB_DIR_UP_TYPE, item_index, 0, DPP_DTB_TAB_ACK_IS_USING_MASK); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_dtb_item_ack_wr", p_mutex); + + + DPP_DTB_TAB_UP_DATA_LEN_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, item_index) = data_len; + + item_info.cmd_vld = 1; + item_info.cmd_type = DPP_DTB_DIR_UP_TYPE; + item_info.int_en = int_flag; + item_info.data_len = desc_len / 4; + item_info.data_hddr = ((DPP_DTB_TAB_UP_PHY_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, item_index)>>4) >> 32) & 0xffffffff; + item_info.data_laddr = (DPP_DTB_TAB_UP_PHY_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, item_index)>>4) & 0xffffffff; + + if(dpp_dtb_prt_get()) + { + dpp_dtb_info_print(dev, queue_id, item_index, &item_info); + } + + if(DPP_DEV_TYPE_SIM == dpp_dev_get_dev_type(DEV_ID(dev))) + { + rc = zxic_comm_mutex_unlock(p_mutex); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev),rc,"zxic_comm_mutex_unlock"); + return DPP_OK; + } + + rc = dpp_dtb_queue_item_info_set(dev, queue_id, &item_info); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_dtb_queue_item_info_set", p_mutex); + + rc = zxic_comm_mutex_unlock(p_mutex); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev),rc,"zxic_comm_mutex_unlock"); + + return DPP_OK; +} + +/***********************************************************/ +/** 打印队列中指定元素的dump地址、ACK及下表中前768bit的数据 +* @param dev_id 芯片的id号 +* @param queue_id 队列号，范围0-127 +* @param element_id 元素号，范围0-31 +* +* @return +* @remark 无 +* @see +* @author zab @date 2022/08/30 +************************************************************/ +ZXIC_UINT32 dpp_dtb_dump_table_element_info_prt(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 element_id) +{ + ZXIC_UINT32 rc = 0; + + ZXIC_UINT32 element_start_addr_h = 0; + ZXIC_UINT32 element_start_addr_l = 0; + ZXIC_UINT32 element_dump_addr_h = 0; + ZXIC_UINT32 element_dump_addr_l = 0; + ZXIC_UINT32 element_table_info_addr_h = 0; + ZXIC_UINT32 element_table_info_addr_l = 0; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), element_id, 0, DPP_DTB_QUEUE_ITEM_NUM_MAX - 1); + + rc = dpp_dtb_dump_table_elemet_addr_get(dev, + queue_id, + element_id, + &element_start_addr_h, + &element_start_addr_l, + &element_dump_addr_h, + &element_dump_addr_l, + &element_table_info_addr_h, + &element_table_info_addr_l); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_dtb_dump_table_elemet_addr_get"); + + ZXIC_COMM_DBGCNT32_PRINT("slot_id", DEV_PCIE_SLOT(dev)); + ZXIC_COMM_DBGCNT32_PRINT("queue_id", queue_id); + ZXIC_COMM_DBGCNT32_PRINT("element_id", element_id); + ZXIC_COMM_DBGCNT32_PRINT("element_start_addr_h", element_start_addr_h); + ZXIC_COMM_DBGCNT32_PRINT("element_start_addr_l", element_start_addr_l); + ZXIC_COMM_DBGCNT32_PRINT("element_dump_addr_h", element_dump_addr_h); + ZXIC_COMM_DBGCNT32_PRINT("element_dump_addr_l", element_dump_addr_l); + ZXIC_COMM_DBGCNT32_PRINT("element_table_info_addr_h", element_table_info_addr_h); + ZXIC_COMM_DBGCNT32_PRINT("element_table_info_addr_l", element_table_info_addr_l); + + /*打印element ack*/ + rc = dpp_dtb_item_ack_prt(dev, queue_id, DPP_DTB_DIR_UP_TYPE, element_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_dtb_item_ack_prt"); + + rc = dpp_dtb_item_buff_prt(dev, queue_id, DPP_DTB_DIR_UP_TYPE, element_id, 32); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_dtb_item_buff_prt"); + + return DPP_OK; +} + +/***********************************************************/ +/** 一个元素dump成功状态检查 +* @param dev_id 设备号，支持多芯片 +* @param queue_id 队列号，范围0-31 +* @param element_id 条目编号 +* +* @return +* @remark 无 +* @see +* @author zab @date 2021/02/23 +************************************************************/ +ZXIC_UINT32 dpp_dtb_tab_up_success_status_check(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 element_id) +{ + ZXIC_UINT32 rc = 0; + ZXIC_UINT32 rd_cnt = 0; + ZXIC_UINT32 ack_value = 0; + ZXIC_UINT32 success_flag = 0; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), element_id, 0, DPP_DTB_QUEUE_ITEM_NUM_MAX - 1); + + if(DPP_DEV_TYPE_SIM == dpp_dev_get_dev_type(DEV_ID(dev))) + { + return rc; + } + + if(dpp_dtb_soft_perf_test_get() || dpp_dtb_hardware_perf_test_get()) + { + return rc; + } + + while(!success_flag) + { + rc = dpp_dtb_item_ack_rd(dev, queue_id, DPP_DTB_DIR_UP_TYPE, element_id, 0, &ack_value); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_item_ack_rd"); + + if ((((ack_value >> 8) & 0xffffff) == DPP_DTB_TAB_UP_ACK_VLD_MASK) && + ((ack_value & 0xff) == DPP_DTB_TAB_ACK_SUCCESS_MASK)) + { + success_flag = 1; + break; + } + + if (rd_cnt > dpp_dtb_dump_table_overtime_get()) + { + ZXIC_COMM_TRACE_ERROR("Error!!! dpp dtb dump slot [%d] vport [0x%x] queue [%d] item [%d] ack success is overtime!\n", DEV_PCIE_SLOT(dev), DEV_PCIE_VPORT(dev), queue_id, element_id); + + ZXIC_COMM_PRINT("-------------------------------------------------------------------\n"); + ZXIC_COMM_PRINT(" dtb dump table info \n"); + ZXIC_COMM_PRINT("-------------------------------------------------------------------\n"); + rc = dpp_dtb_dump_table_element_info_prt(dev, queue_id, element_id); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_dump_table_element_info_prt"); + + rc = dpp_dtb_item_ack_wr(dev, queue_id, DPP_DTB_DIR_UP_TYPE, element_id, 0, DPP_DTB_TAB_ACK_UNUSED_MASK); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_item_ack_wr"); + + ZXIC_COMM_PRINT("-------------------------------------------------------------------\n"); + ZXIC_COMM_PRINT(" dtb reg info \n"); + ZXIC_COMM_PRINT("-------------------------------------------------------------------\n"); + + rc = diag_dpp_dtb_axi_last_operate_info_prt(dev); + ZXIC_COMM_CHECK_DEV_RC(0, rc, "diag_dpp_dtb_axi_last_operate_info_prt"); + + rc = diag_dpp_dtb_channels_state_info_prt(dev); + ZXIC_COMM_CHECK_DEV_RC(0, rc, "diag_dpp_dtb_channels_state_info_prt"); + + rc = diag_dpp_dtb_channels_axi_resp_err_cnt_prt(dev); + ZXIC_COMM_CHECK_DEV_RC(0, rc, "diag_dpp_dtb_channels_axi_resp_err_cnt_prt"); + + return DPP_ERR; + } + + rd_cnt++; + zxic_comm_udelay(1); + } + + return rc; +} + +/***********************************************************/ +/** 获取dump数据 +* @param dev_id 设备号，支持多芯片 +* @param queue_id 队列号，范围0-31 +* @param item_index 数据对应的的条目编号 +* @param data_len 数据长度，单位32bit; +* @param p_data dump数据 +* +* @return +* @remark 无 +* @see +* @author zab @date 2021/02/23 +************************************************************/ +ZXIC_UINT32 dpp_dtb_tab_up_data_get(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 item_index, + ZXIC_UINT32 data_len, + ZXIC_UINT32 *p_data) +{ + ZXIC_UINT32 rc = 0; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), item_index, 0, DPP_DTB_QUEUE_ITEM_NUM_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data); + + if(DPP_DTB_QUEUE_INIT_FLAG_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id) == 0) + { + ZXIC_COMM_TRACE_ERROR("dtb slot %d queue %d is not init.\n", DEV_PCIE_SLOT(dev), queue_id); + return DPP_RC_DTB_QUEUE_IS_NOT_INIT; + } + + if(dpp_dtb_hardware_perf_test_get()) + { + return rc; + } + + rc = dpp_dtb_item_buff_rd(dev, + queue_id, + DPP_DTB_DIR_UP_TYPE, + item_index, + 0, + data_len, + p_data); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_item_buff_rd"); + + if(dpp_dtb_debug_fun_get()) + { + return DPP_OK; + } + + rc = dpp_dtb_item_ack_wr(dev, queue_id, DPP_DTB_DIR_UP_TYPE, item_index, 0, DPP_DTB_TAB_ACK_UNUSED_MASK); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_item_ack_wr"); + + return DPP_OK; +} + +#endif +/***********************************************************/ +/** dtb队列down初始化 +* @param dev_id 设备号，支持多芯片 +* @param queue_id 队列号 +* @param p_queue_cfg 队列配置参数，具体见DPP_DTB_QUEUE_CFG_T结构体类型 +* +* @return +* @remark 无 +* @see +* @author zab @date 2021/02/23 +************************************************************/ +ZXIC_UINT32 dpp_dtb_queue_down_init(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + DPP_DTB_QUEUE_CFG_T *p_queue_cfg) +{ + ZXIC_UINT32 rc = 0; + ZXIC_UINT32 i = 0; + ZXIC_UINT32 ack_vale = 0; + ZXIC_UINT32 tab_down_item_size = 0; + DPP_DTB_MGR_T *p_dtb_mgr = ZXIC_NULL; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_queue_cfg); + + p_dtb_mgr = dpp_dtb_mgr_get(DEV_PCIE_SLOT(dev), DEV_ID(dev)); + if (p_dtb_mgr == ZXIC_NULL) + { + ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "slot %d ErrorCode[0x%x]: DTB Manager is not exist!!!\n", DEV_PCIE_SLOT(dev), DPP_RC_DTB_MGR_NOT_EXIST); + return DPP_RC_DTB_MGR_NOT_EXIST; + } + + /* + * 流程： + * 1.寻找空闲队列； + * 2.若找到： + * 1）配置硬件信息； + * 2）配置软件缓存信息； + * 3）初始化条目ack缓存信息,空闲约定:up-0x000000XX,down-0x000000XX； + * 忙约定:up-0x111111XX,down-0x111111XX; + * 完成约定:up-0x555555XX,down-0x5a5a5aXX; + * 3.若未找到：返回错误信息； + */ + + p_dtb_mgr->queue_info[queue_id].init_flag = 1; + p_dtb_mgr->queue_info[queue_id].slot_id = DEV_PCIE_SLOT(dev); + p_dtb_mgr->queue_info[queue_id].vport = DEV_PCIE_VPORT(dev); + + tab_down_item_size = (p_queue_cfg->down_item_size == 0) ? DPP_DTB_ITEM_SIZE : p_queue_cfg->down_item_size; + + p_dtb_mgr->queue_info[queue_id].tab_down.item_size = tab_down_item_size; + p_dtb_mgr->queue_info[queue_id].tab_down.start_phy_addr = p_queue_cfg->down_start_phy_addr; + p_dtb_mgr->queue_info[queue_id].tab_down.start_vir_addr = p_queue_cfg->down_start_vir_addr; + p_dtb_mgr->queue_info[queue_id].tab_down.wr_index = 0; + p_dtb_mgr->queue_info[queue_id].tab_down.rd_index = 0; + + for (i = 0; i < DPP_DTB_QUEUE_ITEM_NUM_MAX; i++) + { + rc = dpp_dtb_item_ack_wr(dev, queue_id, DPP_DTB_DIR_DOWN_TYPE, i, 0, DPP_DTB_TAB_ACK_CHECK_VALUE); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_item_ack_wr"); + } + + for(i = 0; i < DPP_DTB_QUEUE_ITEM_NUM_MAX; i++) + { + rc = dpp_dtb_item_ack_rd(dev, queue_id, DPP_DTB_DIR_DOWN_TYPE, i, 0, &ack_vale); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_item_ack_rd"); + if(ack_vale != DPP_DTB_TAB_ACK_CHECK_VALUE) + { + ZXIC_COMM_PRINT("dtb slot [%d] queue [%d] down init faild, mem err!!!\n", DEV_PCIE_SLOT(dev), queue_id); + return DPP_RC_DTB_MEMORY_ALLOC_ERR; + } + } + + ZXIC_COMM_PRINT("dtb slot [%d] queue [%d] down init success!!!\n", DEV_PCIE_SLOT(dev), queue_id); + + ZXIC_COMM_MEMSET((ZXIC_UINT8 *)(p_queue_cfg->down_start_vir_addr), 0, tab_down_item_size * DPP_DTB_QUEUE_ITEM_NUM_MAX); + + return DPP_OK; +} + +/***********************************************************/ +/** dtb队列dump初始化 +* @param dev_id 设备号，支持多芯片 +* @param queue_id 队列号 +* @param p_queue_cfg 队列配置参数，具体见DPP_DTB_QUEUE_CFG_T结构体类型 +* +* @return +* @remark 无 +* @see +* @author zab @date 2021/02/23 +************************************************************/ +ZXIC_UINT32 dpp_dtb_queue_dump_init(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + DPP_DTB_QUEUE_CFG_T *p_queue_cfg) +{ + ZXIC_UINT32 rc = 0; + ZXIC_UINT32 i = 0; + ZXIC_UINT32 ack_vale = 0; + ZXIC_UINT32 tab_up_item_size = 0; + DPP_DTB_MGR_T *p_dtb_mgr = ZXIC_NULL; + ZXIC_UINT32 slot_id = 0; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_queue_cfg); + + slot_id = (ZXIC_UINT32)DEV_PCIE_SLOT(dev); + ZXIC_COMM_CHECK_INDEX(slot_id, 0, DPP_DEV_SLOT_MAX - 1); + + p_dtb_mgr = dpp_dtb_mgr_get(slot_id, DEV_ID(dev)); + if (p_dtb_mgr == ZXIC_NULL) + { + ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "slot %d ErrorCode[0x%x]: DTB Manager is not exist!!!\n", DEV_PCIE_SLOT(dev), DPP_RC_DTB_MGR_NOT_EXIST); + return DPP_RC_DTB_MGR_NOT_EXIST; + } + + /* + * 流程： + * 1.寻找空闲队列； + * 2.若找到： + * 1）配置硬件信息； + * 2）配置软件缓存信息； + * 3）初始化条目ack缓存信息,空闲约定:up-0x000000XX,down-0x000000XX； + * 忙约定:up-0x111111XX,down-0x111111XX; + * 完成约定:up-0x555555XX,down-0x5a5a5aXX; + * 3.若未找到：返回错误信息； + */ + + p_dtb_mgr->queue_info[queue_id].init_flag = 1; + p_dtb_mgr->queue_info[queue_id].slot_id = DEV_PCIE_SLOT(dev); + p_dtb_mgr->queue_info[queue_id].vport = DEV_PCIE_VPORT(dev); + + tab_up_item_size = (p_queue_cfg->up_item_size == 0) ? DPP_DTB_ITEM_SIZE : p_queue_cfg->up_item_size; + + p_dtb_mgr->queue_info[queue_id].tab_up.item_size = tab_up_item_size; + p_dtb_mgr->queue_info[queue_id].tab_up.start_phy_addr = p_queue_cfg->up_start_phy_addr; + p_dtb_mgr->queue_info[queue_id].tab_up.start_vir_addr = p_queue_cfg->up_start_vir_addr; + p_dtb_mgr->queue_info[queue_id].tab_up.wr_index = 0; + p_dtb_mgr->queue_info[queue_id].tab_up.rd_index = 0; + + for (i = 0; i < DPP_DTB_QUEUE_ITEM_NUM_MAX; i++) + { + rc = dpp_dtb_item_ack_wr(dev, queue_id, DPP_DTB_DIR_UP_TYPE, i, 0, DPP_DTB_TAB_ACK_CHECK_VALUE); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_item_ack_wr"); + } + + for(i = 0; i < DPP_DTB_QUEUE_ITEM_NUM_MAX; i++) + { + rc = dpp_dtb_item_ack_rd(dev, queue_id, DPP_DTB_DIR_UP_TYPE, i, 0, &ack_vale); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_item_ack_rd"); + if(ack_vale != DPP_DTB_TAB_ACK_CHECK_VALUE) + { + ZXIC_COMM_PRINT("dtb slot [%d] queue [%d] init faild, mem err!!!\n", DEV_PCIE_SLOT(dev), queue_id); + return DPP_RC_DTB_MEMORY_ALLOC_ERR; + } + } + + ZXIC_COMM_PRINT("dtb slot [%d] queue [%d] up init success!!!\n", DEV_PCIE_SLOT(dev), queue_id); + + ZXIC_COMM_MEMSET((ZXIC_UINT8 *)(p_queue_cfg->up_start_vir_addr), 0, tab_up_item_size * DPP_DTB_QUEUE_ITEM_NUM_MAX); + + return DPP_OK; +} + +/***********************************************************/ +/** dtb队列down 空间地址配置 +* @param channelId dtb通道号 +* @param phyAddr down物理地址 +* @param virAddr down虚拟地址 +* @param size 空间大小 0:使用系统默认值16K+16 +* +* @return +* @remark 无 +* @see +* @author zab @date 2021/02/23 +************************************************************/ +ZXIC_UINT32 dpp_dtb_down_channel_addr_set(DPP_DEV_T *dev, + ZXIC_UINT32 channelId, + ZXIC_UINT64 phyAddr, + ZXIC_UINT64 virAddr, + ZXIC_UINT32 size) +{ + ZXIC_UINT32 rc = 0; + + DPP_DTB_QUEUE_CFG_T down_queue_cfg = {0}; + + ZXIC_COMM_CHECK_POINT_NO_ASSERT(dev); + + down_queue_cfg.down_start_phy_addr = phyAddr; + down_queue_cfg.down_start_vir_addr = virAddr; + down_queue_cfg.down_item_size = size; + + rc = dpp_dtb_queue_down_init(dev, + channelId, + &down_queue_cfg); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_queue_down_init"); + + return rc; +} + +/***********************************************************/ +/** dtb队列dump 空间地址配置 +* @param channelId dtb通道号 +* @param phyAddr dump物理地址 +* @param virAddr dump虚拟地址 +* @param size 空间大小 +* +* @return +* @remark 无 +* @see +* @author zab @date 2021/02/23 +************************************************************/ +ZXIC_UINT32 dpp_dtb_dump_channel_addr_set(DPP_DEV_T *dev, + ZXIC_UINT32 channelId, + ZXIC_UINT64 phyAddr, + ZXIC_UINT64 virAddr, + ZXIC_UINT32 size) +{ + ZXIC_UINT32 rc = 0; + + DPP_DTB_QUEUE_CFG_T dump_queue_cfg = {0}; + + ZXIC_COMM_CHECK_POINT_NO_ASSERT(dev); + + dump_queue_cfg.up_start_phy_addr = phyAddr; + dump_queue_cfg.up_start_vir_addr = virAddr; + dump_queue_cfg.up_item_size = size; + + rc = dpp_dtb_queue_dump_init(dev, + channelId, + &dump_queue_cfg); + + return rc; +} + +/***********************************************************/ +/** 释放队列资源 +* @param dev_id 设备号，支持多芯片 +* @param queue_id 分配到的队列号; +* +* @return +* @remark 无 +* @see +* @author zab @date 2021/02/23 +************************************************************/ +ZXIC_UINT32 dpp_dtb_queue_id_free(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id) +{ + ZXIC_UINT32 rc = 0; + ZXIC_UINT32 item_num = 0; + DPP_DTB_MGR_T *p_dtb_mgr = ZXIC_NULL; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev),queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1); + + p_dtb_mgr = dpp_dtb_mgr_get(DEV_PCIE_SLOT(dev), DEV_ID(dev)); + if (p_dtb_mgr == ZXIC_NULL) + { + ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "slot %d ErrorCode[0x%x]: DTB Manager is not exist!!!\n", DEV_PCIE_SLOT(dev), DPP_RC_DTB_MGR_NOT_EXIST); + return DPP_RC_DTB_MGR_NOT_EXIST; + } + + rc = dpp_dtb_queue_unused_item_num_get(dev, queue_id, &item_num); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_queue_unused_item_num_get"); + + if (item_num != DPP_DTB_QUEUE_ITEM_NUM_MAX) + { + return DPP_RC_DTB_QUEUE_IS_WORKING; + } + + p_dtb_mgr->queue_info[queue_id].init_flag = 0; + + ZXIC_COMM_MEMSET(&(p_dtb_mgr->queue_info[queue_id].tab_up), 0, sizeof(DPP_DTB_TAB_UP_INFO_T)); + ZXIC_COMM_MEMSET(&(p_dtb_mgr->queue_info[queue_id].tab_down), 0, sizeof(DPP_DTB_TAB_DOWN_INFO_T)); + + return DPP_OK; +} + +/***********************************************************/ +/** dtb初始化 +* @param dev_id 设备号，支持多芯片 +* +* @return +* @remark 无 +* @see +* @author zab @date 2022/08/30 +************************************************************/ +ZXIC_UINT32 dpp_dtb_init(DPP_DEV_T *dev) +{ + ZXIC_UINT32 rc = 0; + DPP_DTB_MGR_T *p_dtb_mgr = ZXIC_NULL; + + ZXIC_COMM_CHECK_POINT(dev); + + p_dtb_mgr = dpp_dtb_mgr_get(DEV_PCIE_SLOT(dev), DEV_ID(dev)); + if (p_dtb_mgr == ZXIC_NULL) + { + rc = dpp_dtb_mgr_create(DEV_PCIE_SLOT(dev), DEV_ID(dev)); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_mgr_create"); + + p_dtb_mgr = dpp_dtb_mgr_get(DEV_PCIE_SLOT(dev), DEV_ID(dev)); + if (p_dtb_mgr == ZXIC_NULL) + { + ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "slot %d ErrorCode[0x%x]: DTB Manager is not exist!!!\n", DEV_PCIE_SLOT(dev), DPP_RC_DTB_MGR_NOT_EXIST); + return DPP_RC_DTB_MGR_NOT_EXIST; + } + } + + return DPP_OK; +} + +/***********************************************************/ +/** 根据vport查找相应的队列号 +* @param dev_id 设备号，支持多芯片 +* @param vport vport信息 +* @param p_queue_arr 找到到队列数组 +* @param p_num 找到的队列个数 +* @return +* @remark 无 +* @see +* @author cbb @date 2023/09/13 +************************************************************/ +ZXIC_UINT32 dpp_dtb_queue_id_search_by_vport(DPP_DEV_T *dev, + ZXIC_UINT32 *p_queue_arr, + ZXIC_UINT32 *p_num) +{ + ZXIC_UINT32 queue_id = 0; + ZXIC_UINT32 count = 0; + + DPP_DTB_MGR_T *p_dtb_mgr = ZXIC_NULL; + + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_queue_arr); + + p_dtb_mgr = dpp_dtb_mgr_get(DEV_PCIE_SLOT(dev), DEV_ID(dev)); + if (p_dtb_mgr == ZXIC_NULL) + { + ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "slot %d ErrorCode[0x%x]: DTB Manager is not exist!!!\n", DEV_PCIE_SLOT(dev), DPP_RC_DTB_MGR_NOT_EXIST); + return DPP_RC_DTB_MGR_NOT_EXIST; + } + + for(queue_id = 0; queue_id < DPP_DTB_QUEUE_NUM_MAX; queue_id++) + { + if(DPP_DTB_QUEUE_INIT_FLAG_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id) != 0) + { + if(DEV_PCIE_VPORT(dev) == DPP_DTB_QUEUE_VPORT_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id)) + { + p_queue_arr[count] = queue_id; + count++; + } + } + } + + if (count == 0) + { + ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "slot %d ErrorCode[0x%x]: vport 0x%04x no queue not found!!!\n", + DEV_PCIE_SLOT(dev), DPP_RC_DTB_QUEUE_NOT_ALLOC, DEV_PCIE_VPORT(dev)); + return DPP_RC_DTB_QUEUE_NOT_ALLOC; + } + + *p_num = count; + + return DPP_OK; +} + +/***********************************************************/ +/** 根据vport查找相应的队列号 +* @param dev_id 设备号，支持多芯片 +* @param vport vport信息 +* @param p_queue_arr 找到到队列数组 +* @param p_num 找到的队列个数 +* @return +* @remark 无 +* @see +* @author cbb @date 2023/09/13 +************************************************************/ +ZXIC_UINT32 dpp_dtb_queue_id_get(ZXIC_UINT32 dev_id, DPP_PF_INFO_T* pf_info, ZXIC_UINT32 *queue) +{ + DPP_DEV_T dev = {0}; + + ZXIC_UINT32 num = 0; + ZXIC_UINT32 rc = DPP_OK; + + ZXIC_UINT32 queue_arr[DPP_DTB_QUEUE_NUM_MAX] = {0}; + + ZXIC_COMM_CHECK_POINT_NO_ASSERT(pf_info); + + rc = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get"); + + rc = dpp_dtb_queue_id_search_by_vport(&dev, queue_arr, &num); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_queue_id_search_by_vport"); + + *queue = queue_arr[0]; + + return DPP_OK; +} + +#endif +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/dma/dpp_dtb_cfg.c b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/dma/dpp_dtb_cfg.c new file mode 100755 index 0000000..f49b81c --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/dma/dpp_dtb_cfg.c @@ -0,0 +1,1079 @@ +/************************************************************** +* 版权所有(C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_dtb_cfg.c +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : zab +* 完成日期 : 2022/08/23 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ + +#include "zxic_common.h" +#include "dpp_type_api.h" +#include "dpp_cfg_reg.h" +#include "dpp_dev.h" +#include "dpp_dtb.h" +#include "dpp_reg.h" +#include "dpp_reg_info.h" +#include "dpp_dtb_cfg.h" +#include "dpp_dtb4k_reg.h" +#include "dpp_dtb_reg.h" + +#define DTB_DEBUG_VALUE (0x5A) + +#if ZXIC_REAL("DTB_CFG") +/***********************************************************/ +/** DTB队列元素信息配置 +* @param dev_id 芯片id +* @param queue_id 队列ID，范围0-127 +* @param p_item_info 队列元素配置信息 +* +* @return +* @remark 无 +* @see +* @author zab @date 2018/08/23 +************************************************************/ +ZXIC_UINT32 dpp_dtb_queue_item_info_set(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + DPP_DTB_QUEUE_ITEM_INFO_T *p_item_info) +{ + ZXIC_UINT32 rc = 0; + DPP_DTB4K_DTB_ENQ_CFG_QUEUE_DTB_LEN_0_127_T dtb_len = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_item_info); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_item_info->cmd_vld, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_item_info->cmd_type, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_item_info->int_en, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_item_info->data_len, DPP_DTB_LEN_MIN, DPP_DTB_DOWN_LEN); + + rc = dpp_reg_write(dev, DTB4K_DTB_ENQ_CFG_QUEUE_DTB_ADDR_H_0_127r, 0, queue_id, &(p_item_info->data_hddr)); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write"); + + rc = dpp_reg_write(dev, DTB4K_DTB_ENQ_CFG_QUEUE_DTB_ADDR_L_0_127r, 0, queue_id, &(p_item_info->data_laddr)); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write"); + + dtb_len.cfg_dtb_cmd_type = p_item_info->cmd_type; + dtb_len.cfg_dtb_cmd_int_en = p_item_info->int_en; + dtb_len.cfg_queue_dtb_len = p_item_info->data_len; + + rc = dpp_reg_write(dev, DTB4K_DTB_ENQ_CFG_QUEUE_DTB_LEN_0_127r, 0, queue_id, &dtb_len); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write"); + + return DPP_OK; +} + +/***********************************************************/ +/** 获取DTB队列中剩余未使用的条目数量 +* @param dev_id 芯片id +* @param queue_id 队列ID，范围0-127 +* @param p_item_num 剩余未使用条目数量 +* +* @return +* @remark 无 +* @see +* @author zab @date 2018/08/23 +************************************************************/ +ZXIC_UINT32 dpp_dtb_queue_unused_item_num_get(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 *p_item_num) +{ + ZXIC_UINT32 rc = 0; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_item_num); + + if(DPP_DEV_TYPE_SIM == dpp_dev_get_dev_type(DEV_ID(dev))) + { + *p_item_num = 32; + return DPP_OK; + } + + rc = dpp_reg_read(dev, DTB4K_DTB_ENQ_INFO_QUEUE_BUF_SPACE_LEFT_0_127r, 0, queue_id, p_item_num); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + + return DPP_OK; +} + +/***********************************************************/ +/** 配置队列VM相关信息 +* @param dev_id 芯片id +* @param queue_id 队列ID，范围0-127 +* @param p_vm_info VM配置信息 +* +* @return +* @remark 无 +* @see +* @author zab @date 2018/08/23 +************************************************************/ +ZXIC_UINT32 dpp_dtb_queue_vm_info_set(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + DPP_DTB_QUEUE_VM_INFO_T *p_vm_info) +{ + ZXIC_UINT32 rc = 0; + DPP_DTB4K_DTB_ENQ_CFG_EPID_V_FUNC_NUM_0_127_T vm_info = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_vm_info); + + vm_info.dbi_en = p_vm_info->dbi_en; + vm_info.queue_en = p_vm_info->queue_en; + vm_info.cfg_epid = p_vm_info->epid; + vm_info.cfg_vector = p_vm_info->vector; + vm_info.cfg_vfunc_num = p_vm_info->vfunc_num; + vm_info.cfg_func_num = p_vm_info->func_num; + vm_info.cfg_vfunc_active = p_vm_info->vfunc_active; + + rc = dpp_reg_write(dev, DTB4K_DTB_ENQ_CFG_EPID_V_FUNC_NUM_0_127r, 0, queue_id, &vm_info); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write"); + + return DPP_OK; +} + +/***********************************************************/ +/** 获取队列VM配置信息 +* @param dev_id оƬid +* @param queue_id 队列ID，范围0-127 +* @param p_vm_info VM配置信息 +* +* @return +* @remark 无 +* @see +* @author zab @date 2018/08/23 +************************************************************/ +ZXIC_UINT32 dpp_dtb_queue_vm_info_get(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + DPP_DTB_QUEUE_VM_INFO_T *p_vm_info) +{ + ZXIC_UINT32 rc = 0; + DPP_DTB4K_DTB_ENQ_CFG_EPID_V_FUNC_NUM_0_127_T vm_info = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_vm_info); + + rc = dpp_reg_read(dev, DTB4K_DTB_ENQ_CFG_EPID_V_FUNC_NUM_0_127r, 0, queue_id, &vm_info); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + + p_vm_info->dbi_en = vm_info.dbi_en; + p_vm_info->queue_en = vm_info.queue_en; + p_vm_info->epid = vm_info.cfg_epid; + p_vm_info->vector = vm_info.cfg_vector; + p_vm_info->vfunc_num = vm_info.cfg_vfunc_num; + p_vm_info->func_num = vm_info.cfg_func_num; + p_vm_info->vfunc_active = vm_info.cfg_vfunc_active; + + return DPP_OK; +} + +/***********************************************************/ +/** 配置队列使能 +* @param dev_id 芯片id +* @param queue_id 队列ID，范围0-127 +* @param enable 1:队列使能,0:队列去使能 +* +* @return +* @remark 无 +* @see +* @author cbb @date 2023/09/27 +************************************************************/ +ZXIC_UINT32 dpp_dtb_queue_enable_set(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 enable) +{ + ZXIC_UINT32 rc = DPP_OK; + DPP_DTB_QUEUE_VM_INFO_T vm_info = {0}; + + rc = dpp_dtb_queue_vm_info_get(dev, queue_id, &vm_info); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_queue_vm_info_get"); + + vm_info.queue_en = enable; + rc = dpp_dtb_queue_vm_info_set(dev, queue_id, &vm_info); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_queue_vm_info_set"); + + ZXIC_COMM_TRACE_INFO("dtb queue [%d] enable_set [%d] success.\n", queue_id, enable); + + return rc; +} + +/***********************************************************/ +/** 获取队列使能状态 +* @param dev_id 芯片id +* @param queue_id 队列ID，范围0-127 +* @param enable 1:队列使能,0:队列去使能 +* +* @return +* @remark 无 +* @see +* @author cbb @date 2023/09/27 +************************************************************/ +ZXIC_UINT32 dpp_dtb_queue_enable_get(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 *enable) +{ + ZXIC_UINT32 rc = DPP_OK; + DPP_DTB_QUEUE_VM_INFO_T vm_info = {0}; + + rc = dpp_dtb_queue_vm_info_get(dev, queue_id, &vm_info); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_queue_vm_info_get"); + + *enable = vm_info.queue_en; + + ZXIC_COMM_TRACE_INFO("dpp_dtb_queue_enable_get queue %d enable: %d success.\n", queue_id, *enable); + + return rc; +} + +/***********************************************************/ +/** 配置 dtb 完成中断事件状态 +* @param dev_id 芯片id +* @param queue_id 队列ID，范围0-127 +* @param state 中断事件状态，1-发生中断，0-无中断发生 +* +* @return +* @remark 无 +* @see +* @author cbb @date 2022/11/12 +************************************************************/ +ZXIC_UINT32 dpp_dtb_finish_interrupt_event_state_set(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 state) +{ + ZXIC_UINT32 rc = 0; + ZXIC_UINT32 bit_shift = 0; + ZXIC_UINT32 reg_shift = 0; + ZXIC_UINT32 rd_value = 0; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), state, 0, 1); + + reg_shift = queue_id / 32; + bit_shift = queue_id % 32; + + rc = dpp_reg_read(dev, DTB_DTB_CFG_CFG_FINISH_INT_EVENT0r + reg_shift, 0, 0, &rd_value); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + + ZXIC_COMM_UINT32_WRITE_BITS(rd_value, state, bit_shift, 1); + + rc = dpp_reg_write(dev, DTB_DTB_CFG_CFG_FINISH_INT_EVENT0r + reg_shift, 0, 0, &rd_value); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write"); + + return DPP_OK; +} + +/***********************************************************/ +/** 清除 dtb 完成中断事件状态 +* @param dev_id 芯片id +* @param queue_id 队列ID，范围0-127 +* +* @return +* @remark 无 +* @see +* @author cbb @date 2022/11/12 +************************************************************/ +ZXIC_UINT32 dpp_dtb_finish_interrupt_event_state_clr(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id) +{ + ZXIC_UINT32 rc = 0; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1); + + rc = dpp_dtb_finish_interrupt_event_state_set(dev, queue_id, 1); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_finish_interrupt_event_state_set"); + + return rc; +} + +/***********************************************************/ +/** 获取DTB debug模式配置 +* @param dev_id 芯片id +* @param p_debug_mode 调试模式 当为0x5a时，dtb的ram均可读写 +* +* @return +* @remark 无 +* @see +* @author cbb @date 2022/11/09 +************************************************************/ +ZXIC_UINT32 dpp_dtb_debug_mode_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_debug_mode) +{ + ZXIC_UINT32 rc = 0; + DPP_DTB_DTB_CFG_CFG_DTB_DEBUG_MODE_EN_T dtb_debug_mode = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_debug_mode); + + rc = dpp_reg_read(dev, DTB_DTB_CFG_CFG_DTB_DEBUG_MODE_ENr, 0, 0, &dtb_debug_mode); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + + *p_debug_mode = dtb_debug_mode.cfg_dtb_debug_mode_en; + + return DPP_OK; +} + +/***********************************************************/ +/** 判断dtb是否在debug模式 +* @param dev_id 芯片的id号 +* +* @return 1:DTB为debug模式; 0:非debug模式 +* @remark 无 +* @see +* @author cbb @date 2023/6/10 +************************************************************/ +ZXIC_UINT32 dpp_dtb_mode_is_debug(DPP_DEV_T *dev) +{ + ZXIC_UINT32 rc = 0; + ZXIC_UINT32 dtb_mode = 0; + + ZXIC_COMM_CHECK_POINT(dev); + rc = dpp_dtb_debug_mode_get(dev, &dtb_mode); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_dtb_debug_mode_get"); + + if(DTB_DEBUG_VALUE == dtb_mode) + { + return 1; + } + + return 0; +} + +#if ZXIC_REAL("AXIM_READ_TABLE_DEBUG") + +/***********************************************************/ +/** 读取axi 最近一次读表相关信息 +* @param dev_id 芯片id +* @param p_last_rd_table_addr_h axim最近一次读表高地址 +* @param p_last_rd_table_addr_l axim最近一次读表低地址 +* @param p_last_rd_table_len axim最近一次读表长度 +* @param p_last_rd_table_user axim最近一次读表USER信号 +* @param p_last_rd_table_onload_cnt axim最近一次读表在线计数 +* +* @return +* @remark 无 +* @see +* @author cbb @date 2022/11/09 +************************************************************/ +ZXIC_UINT32 dpp_dtb_axi_last_rd_table_info_get(DPP_DEV_T *dev, + ZXIC_UINT32 *p_last_rd_table_addr_h, + ZXIC_UINT32 *p_last_rd_table_addr_l, + ZXIC_UINT32 *p_last_rd_table_len, + ZXIC_UINT32 *p_last_rd_table_user, + ZXIC_UINT32 *p_last_rd_table_onload_cnt + ) +{ + ZXIC_UINT32 rc = 0; + + DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_ADDR_HIGH_T rd_table_addr_high = {0}; + DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_ADDR_LOW_T rd_table_addr_low = {0}; + DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_LEN_T rd_table_len = {0}; + DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_USER_T rd_table_user = {0}; + DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_ONLOAD_CNT_T rd_table_onload_cnt = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_last_rd_table_addr_h); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_last_rd_table_addr_l); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_last_rd_table_len); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_last_rd_table_user); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_last_rd_table_onload_cnt); + + rc = dpp_reg_read(dev, DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_ADDR_HIGHr, 0, 0, &rd_table_addr_high); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + rc = dpp_reg_read(dev, DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_ADDR_LOWr, 0, 0, &rd_table_addr_low); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + rc = dpp_reg_read(dev, DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_LENr, 0, 0, &rd_table_len); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + rc = dpp_reg_read(dev, DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_USERr, 0, 0, &rd_table_user); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + rc = dpp_reg_read(dev, DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_ONLOAD_CNTr, 0, 0, &rd_table_onload_cnt); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + + *p_last_rd_table_addr_h = rd_table_addr_high.info_axi_last_rd_table_addr_high; + *p_last_rd_table_addr_l = rd_table_addr_low.info_axi_last_rd_table_addr_low; + *p_last_rd_table_len = rd_table_len.info_axi_last_rd_table_len; + (*((DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_USER_T*)p_last_rd_table_user)).info_rd_table_user_en = rd_table_user.info_rd_table_user_en; + (*((DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_USER_T*)p_last_rd_table_user)).info_rd_table_epid = rd_table_user.info_rd_table_epid; + (*((DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_USER_T*)p_last_rd_table_user)).info_rd_table_vfunc_num = rd_table_user.info_rd_table_vfunc_num; + (*((DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_USER_T*)p_last_rd_table_user)).info_rd_table_func_num = rd_table_user.info_rd_table_func_num; + (*((DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_USER_T*)p_last_rd_table_user)).info_rd_table_vfunc_active = rd_table_user.info_rd_table_vfunc_active; + *p_last_rd_table_onload_cnt = rd_table_onload_cnt.info_axi_last_rd_table_onload_cnt; + + return DPP_OK; +} + +/***********************************************************/ +/** 读表通道错误次数统计 +* @param dev_id 芯片id +* @param p_axi_rd_table_resp_err_cnt 读表通道返回错误次数 +* +* @return +* @remark 无 +* @see +* @author cbb @date 2022/11/09 +************************************************************/ +ZXIC_UINT32 dpp_dtb_axi_rd_table_resp_err_cnt_get(DPP_DEV_T *dev, + ZXIC_UINT32 *p_axi_rd_table_resp_err_cnt + ) +{ + ZXIC_UINT32 rc = 0; + + DPP_DTB_DTB_CFG_CNT_AXI_RD_TABLE_RESP_ERR_T rd_table_resp_err_cnt= {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_axi_rd_table_resp_err_cnt); + + rc = dpp_reg_read(dev, DTB_DTB_CFG_CNT_AXI_RD_TABLE_RESP_ERRr, 0, 0, &rd_table_resp_err_cnt); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + + *p_axi_rd_table_resp_err_cnt = rd_table_resp_err_cnt.cnt_axi_rd_table_resp_err; + + return DPP_OK; +} +#endif + +#if ZXIC_REAL("AXIM_READ_PD_DEBUG") +/***********************************************************/ +/** 读取axi 最近一次读PD相关信息 +* @param dev_id 芯片id +* @param p_last_rd_pd_addr_h axim最近一次读PD高地址 +* @param p_last_rd_pd_addr_l axim最近一次读PD低地址 +* @param p_last_rd_pd_len axim最近一次读PD长度 +* @param p_last_rd_pd_user axim最近一次读PD USER信号 +* @param p_last_rd_pd_onload_cnt axim最近一次读PD在线计数 +* +* @return +* @remark 无 +* @see +* @author cbb @date 2022/11/09 +************************************************************/ +ZXIC_UINT32 dpp_dtb_axi_last_rd_pd_info_get(DPP_DEV_T *dev, + ZXIC_UINT32 *p_last_rd_pd_addr_h, + ZXIC_UINT32 *p_last_rd_pd_addr_l, + ZXIC_UINT32 *p_last_rd_pd_len, + ZXIC_UINT32 *p_last_rd_pd_user, + ZXIC_UINT32 *p_last_rd_pd_onload_cnt + ) +{ + ZXIC_UINT32 rc = 0; + + DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_ADDR_HIGH_T rd_pd_addr_high = {0}; + DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_ADDR_LOW_T rd_pd_addr_low = {0}; + DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_LEN_T rd_pd_len = {0}; + DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_USER_T rd_pd_user = {0}; + DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_ONLOAD_CNT_T rd_pd_onload_cnt = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_last_rd_pd_addr_h); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_last_rd_pd_addr_l); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_last_rd_pd_len); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_last_rd_pd_user); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_last_rd_pd_onload_cnt); + + rc = dpp_reg_read(dev, DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_ADDR_HIGHr, 0, 0, &rd_pd_addr_high); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + rc = dpp_reg_read(dev, DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_ADDR_LOWr, 0, 0, &rd_pd_addr_low); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + rc = dpp_reg_read(dev, DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_LENr, 0, 0, &rd_pd_len); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + rc = dpp_reg_read(dev, DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_USERr, 0, 0, &rd_pd_user); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + rc = dpp_reg_read(dev, DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_ONLOAD_CNTr, 0, 0, &rd_pd_onload_cnt); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + + *p_last_rd_pd_addr_h = rd_pd_addr_high.info_axi_last_rd_pd_addr_high; + *p_last_rd_pd_addr_l = rd_pd_addr_low.info_axi_last_rd_pd_addr_low; + *p_last_rd_pd_len = rd_pd_len.info_axi_last_rd_pd_len; + (*((DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_USER_T*)p_last_rd_pd_user)).info_rd_pd_user_en = rd_pd_user.info_rd_pd_user_en; + (*((DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_USER_T*)p_last_rd_pd_user)).info_rd_pd_epid = rd_pd_user.info_rd_pd_epid; + (*((DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_USER_T*)p_last_rd_pd_user)).info_rd_pd_vfunc_num = rd_pd_user.info_rd_pd_vfunc_num; + (*((DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_USER_T*)p_last_rd_pd_user)).info_rd_pd_func_num = rd_pd_user.info_rd_pd_func_num; + (*((DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_USER_T*)p_last_rd_pd_user)).info_rd_pd_vfunc_active = rd_pd_user.info_rd_pd_vfunc_active; + *p_last_rd_pd_onload_cnt = rd_pd_onload_cnt.info_axi_last_rd_pd_onload_cnt; + + return DPP_OK; +} + +/***********************************************************/ +/** 读PD通道错误次数统计 +* @param dev_id 芯片id +* @param p_axi_rd_pd_resp_err_cnt 读PD通道返回错误次数 +* +* @return +* @remark 无 +* @see +* @author cbb @date 2022/11/09 +************************************************************/ +ZXIC_UINT32 dpp_dtb_axi_rd_pd_resp_err_cnt_get(DPP_DEV_T *dev, + ZXIC_UINT32 *p_axi_rd_pd_resp_err_cnt + ) +{ + ZXIC_UINT32 rc = 0; + + DPP_DTB_DTB_CFG_CNT_AXI_RD_PD_RESP_ERR_T rd_pd_resp_err_cnt= {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_axi_rd_pd_resp_err_cnt); + + rc = dpp_reg_read(dev, DTB_DTB_CFG_CNT_AXI_RD_PD_RESP_ERRr, 0, 0, &rd_pd_resp_err_cnt); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + + *p_axi_rd_pd_resp_err_cnt = rd_pd_resp_err_cnt.cnt_axi_rd_pd_resp_err; + + return DPP_OK; +} + +#endif + +#if ZXIC_REAL("AXI_WRITE_CTRL_DEBUG") + +/***********************************************************/ +/** 读取axim 最近一次写控制相关信息 +* @param dev_id 芯片id +* @param p_last_wr_ctrl_addr_h axim最近一次写控制高地址 +* @param p_last_wr_ctrl_addr_l axim最近一次写控制低地址 +* @param p_last_wr_ctrl_len axim最近一次写控制长度 +* @param p_last_wr_ctrl_user axim最近一次写控制 USER信号 +* @param p_last_wr_ctrl_onload_cnt axim最近一次写控制在线计数 +* +* @return +* @remark 无 +* @see +* @author cbb @date 2022/11/09 +************************************************************/ +ZXIC_UINT32 dpp_dtb_axi_last_wr_ctrl_info_get(DPP_DEV_T *dev, + ZXIC_UINT32 *p_last_wr_ctrl_addr_h, + ZXIC_UINT32 *p_last_wr_ctrl_addr_l, + ZXIC_UINT32 *p_last_wr_ctrl_len, + ZXIC_UINT32 *p_last_wr_ctrl_user, + ZXIC_UINT32 *p_last_wr_ctrl_onload_cnt + ) +{ + ZXIC_UINT32 rc = 0; + + DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_ADDR_HIGH_T wr_ctrl_addr_high = {0}; + DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_ADDR_LOW_T wr_ctrl_addr_low = {0}; + DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_LEN_T wr_ctrl_len = {0}; + DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_USER_T wr_ctrl_user = {0}; + DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_ONLOAD_CNT_T wr_ctrl_onload_cnt = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_last_wr_ctrl_addr_h); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_last_wr_ctrl_addr_l); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_last_wr_ctrl_len); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_last_wr_ctrl_user); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_last_wr_ctrl_onload_cnt); + + rc = dpp_reg_read(dev, DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_ADDR_HIGHr, 0, 0, &wr_ctrl_addr_high); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + rc = dpp_reg_read(dev, DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_ADDR_LOWr, 0, 0, &wr_ctrl_addr_low); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + rc = dpp_reg_read(dev, DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_LENr, 0, 0, &wr_ctrl_len); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + rc = dpp_reg_read(dev, DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_USERr, 0, 0, &wr_ctrl_user); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + rc = dpp_reg_read(dev, DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_ONLOAD_CNTr, 0, 0, &wr_ctrl_onload_cnt); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + + *p_last_wr_ctrl_addr_h = wr_ctrl_addr_high.info_axi_last_wr_ctrl_addr_high; + *p_last_wr_ctrl_addr_l = wr_ctrl_addr_low.info_axi_last_wr_ctrl_addr_low; + *p_last_wr_ctrl_len = wr_ctrl_len.info_axi_last_wr_ctrl_len; + (*((DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_USER_T*)p_last_wr_ctrl_user)).info_wr_ctrl_user_en = wr_ctrl_user.info_wr_ctrl_user_en; + (*((DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_USER_T*)p_last_wr_ctrl_user)).info_wr_ctrl_epid = wr_ctrl_user.info_wr_ctrl_epid; + (*((DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_USER_T*)p_last_wr_ctrl_user)).info_wr_ctrl_vfunc_num = wr_ctrl_user.info_wr_ctrl_vfunc_num; + (*((DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_USER_T*)p_last_wr_ctrl_user)).info_wr_ctrl_func_num = wr_ctrl_user.info_wr_ctrl_func_num; + (*((DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_USER_T*)p_last_wr_ctrl_user)).info_wr_ctrl_vfunc_active = wr_ctrl_user.info_wr_ctrl_vfunc_active; + *p_last_wr_ctrl_onload_cnt = wr_ctrl_onload_cnt.info_axi_last_wr_ctrl_onload_cnt; + + return DPP_OK; +} + +/***********************************************************/ +/** 获取写控制通道错误次数统计 +* @param dev_id 芯片id +* @param p_axi_wr_ctrl_resp_err_cnt 写控制通道返回错误次数 +* +* @return +* @remark 无 +* @see +* @author cbb @date 2022/11/09 +************************************************************/ +ZXIC_UINT32 dpp_dtb_axi_wr_ctrl_resp_err_cnt_get(DPP_DEV_T *dev, + ZXIC_UINT32 *p_axi_wr_ctrl_resp_err_cnt + ) +{ + ZXIC_UINT32 rc = 0; + + DPP_DTB_DTB_CFG_CNT_AXI_WR_CTRL_RESP_ERR_T wr_ctrl_resp_err_cnt= {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_axi_wr_ctrl_resp_err_cnt); + + rc = dpp_reg_read(dev, DTB_DTB_CFG_CNT_AXI_WR_CTRL_RESP_ERRr, 0, 0, &wr_ctrl_resp_err_cnt); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + + *p_axi_wr_ctrl_resp_err_cnt = wr_ctrl_resp_err_cnt.cnt_axi_wr_ctrl_resp_err; + + return DPP_OK; +} + +#endif + +#if ZXIC_REAL("AXI_WRITE_DDR_DEBUG") +/***********************************************************/ +/** 读取axim 最近一次写DDR相关信息 +* @param dev_id 芯片id +* @param p_last_wr_ddr_addr_h axim最近一次写控制高地址 +* @param p_last_wr_ddr_addr_l axim最近一次写控制低地址 +* @param p_last_wr_ddr_len axim最近一次写控制长度 +* @param p_last_wr_ddr_user axim最近一次写控制 USER信号 +* @param p_last_wr_ddr_onload_cnt axim最近一次写控制在线计数 +* +* @return +* @remark 无 +* @see +* @author cbb @date 2022/11/09 +************************************************************/ +ZXIC_UINT32 dpp_dtb_axi_last_wr_ddr_info_get(DPP_DEV_T *dev, + ZXIC_UINT32 *p_last_wr_ddr_addr_h, + ZXIC_UINT32 *p_last_wr_ddr_addr_l, + ZXIC_UINT32 *p_last_wr_ddr_len, + ZXIC_UINT32 *p_last_wr_ddr_user, + ZXIC_UINT32 *p_last_wr_ddr_onload_cnt + ) +{ + ZXIC_UINT32 rc = 0; + + DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_ADDR_HIGH_T wr_ddr_addr_high = {0}; + DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_ADDR_LOW_T wr_ddr_addr_low = {0}; + DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_LEN_T wr_ddr_len = {0}; + DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_USER_T wr_ddr_user = {0}; + DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_ONLOAD_CNT_T wr_ddr_onload_cnt = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_last_wr_ddr_addr_h); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_last_wr_ddr_addr_l); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_last_wr_ddr_len); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_last_wr_ddr_user); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_last_wr_ddr_onload_cnt); + + rc = dpp_reg_read(dev, DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_ADDR_HIGHr, 0, 0, &wr_ddr_addr_high); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + rc = dpp_reg_read(dev, DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_ADDR_LOWr, 0, 0, &wr_ddr_addr_low); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + rc = dpp_reg_read(dev, DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_LENr, 0, 0, &wr_ddr_len); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + rc = dpp_reg_read(dev, DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_USERr, 0, 0, &wr_ddr_user); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + rc = dpp_reg_read(dev, DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_ONLOAD_CNTr, 0, 0, &wr_ddr_onload_cnt); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + + *p_last_wr_ddr_addr_h = wr_ddr_addr_high.info_axi_last_wr_ddr_addr_high; + *p_last_wr_ddr_addr_l = wr_ddr_addr_low.info_axi_last_wr_ddr_addr_low; + *p_last_wr_ddr_len = wr_ddr_len.info_axi_last_wr_ddr_len; + (*((DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_USER_T*)p_last_wr_ddr_user)).info_wr_ddr_user_en = wr_ddr_user.info_wr_ddr_user_en; + (*((DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_USER_T*)p_last_wr_ddr_user)).info_wr_ddr_epid = wr_ddr_user.info_wr_ddr_epid; + (*((DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_USER_T*)p_last_wr_ddr_user)).info_wr_ddr_vfunc_num = wr_ddr_user.info_wr_ddr_vfunc_num; + (*((DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_USER_T*)p_last_wr_ddr_user)).info_wr_ddr_func_num = wr_ddr_user.info_wr_ddr_func_num; + (*((DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_USER_T*)p_last_wr_ddr_user)).info_wr_ddr_vfunc_active = wr_ddr_user.info_wr_ddr_vfunc_active; + *p_last_wr_ddr_onload_cnt = wr_ddr_onload_cnt.info_axi_last_wr_ddr_onload_cnt; + + return DPP_OK; +} + +/***********************************************************/ +/** 获取写DDR通道错误次数统计 +* @param dev_id 芯片id +* @param p_axi_wr_ddr_resp_err_cnt 写DDR通道返回错误次数 +* +* @return +* @remark 无 +* @see +* @author cbb @date 2022/11/09 +************************************************************/ +ZXIC_UINT32 dpp_dtb_axi_wr_ddr_resp_err_cnt_get(DPP_DEV_T *dev, + ZXIC_UINT32 *p_axi_wr_ddr_resp_err_cnt + ) +{ + ZXIC_UINT32 rc = 0; + + DPP_DTB_DTB_CFG_CNT_AXI_WR_DDR_RESP_ERR_T wr_ddr_resp_err_cnt= {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_axi_wr_ddr_resp_err_cnt); + + rc = dpp_reg_read(dev, DTB_DTB_CFG_CNT_AXI_WR_DDR_RESP_ERRr, 0, 0, &wr_ddr_resp_err_cnt); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + + *p_axi_wr_ddr_resp_err_cnt = wr_ddr_resp_err_cnt.cnt_axi_wr_ddr_resp_err; + + return DPP_OK; +} + +#endif + +#if ZXIC_REAL("AXIM_WRITE_FINISH_DEBUG") + +/***********************************************************/ +/** 读取axim 最近一次写完成相关信息 +* @param dev_id 芯片id +* @param p_last_wr_fin_addr_h axim最近一次写控制高地址 +* @param p_last_wr_fin_addr_l axim最近一次写控制低地址 +* @param p_last_wr_fin_len axim最近一次写控制长度 +* @param p_last_wr_fin_user axim最近一次写控制 USER信号 +* @param p_last_wr_fin_onload_cnt axim最近一次写控制在线计数 +* +* @return +* @remark 无 +* @see +* @author cbb @date 2022/11/09 +************************************************************/ +ZXIC_UINT32 dpp_dtb_axi_last_wr_fin_info_get(DPP_DEV_T *dev, + ZXIC_UINT32 *p_last_wr_fin_addr_h, + ZXIC_UINT32 *p_last_wr_fin_addr_l, + ZXIC_UINT32 *p_last_wr_fin_len, + ZXIC_UINT32 *p_last_wr_fin_user, + ZXIC_UINT32 *p_last_wr_fin_onload_cnt + ) +{ + ZXIC_UINT32 rc = 0; + + DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_ADDR_HIGH_T wr_fin_addr_high = {0}; + DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_ADDR_LOW_T wr_fin_addr_low = {0}; + DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_LEN_T wr_fin_len = {0}; + DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_USER_T wr_fin_user = {0}; + DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_ONLOAD_CNT_T wr_fin_onload_cnt = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_last_wr_fin_addr_h); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_last_wr_fin_addr_l); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_last_wr_fin_len); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_last_wr_fin_user); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_last_wr_fin_onload_cnt); + + rc = dpp_reg_read(dev, DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_ADDR_HIGHr, 0, 0, &wr_fin_addr_high); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + rc = dpp_reg_read(dev, DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_ADDR_LOWr, 0, 0, &wr_fin_addr_low); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + rc = dpp_reg_read(dev, DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_LENr, 0, 0, &wr_fin_len); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + rc = dpp_reg_read(dev, DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_USERr, 0, 0, &wr_fin_user); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + rc = dpp_reg_read(dev, DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_ONLOAD_CNTr, 0, 0, &wr_fin_onload_cnt); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + + *p_last_wr_fin_addr_h = wr_fin_addr_high.info_axi_last_wr_fin_addr_high; + *p_last_wr_fin_addr_l = wr_fin_addr_low.info_axi_last_wr_fin_addr_low; + *p_last_wr_fin_len = wr_fin_len.info_axi_last_wr_fin_len; + + (*((DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_USER_T*)p_last_wr_fin_user)).info_wr_fin_user_en = wr_fin_user.info_wr_fin_user_en; + (*((DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_USER_T*)p_last_wr_fin_user)).info_wr_fin_epid = wr_fin_user.info_wr_fin_epid; + (*((DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_USER_T*)p_last_wr_fin_user)).info_wr_fin_vfunc_num = wr_fin_user.info_wr_fin_vfunc_num; + (*((DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_USER_T*)p_last_wr_fin_user)).info_wr_fin_func_num = wr_fin_user.info_wr_fin_func_num; + (*((DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_USER_T*)p_last_wr_fin_user)).info_wr_fin_vfunc_active = wr_fin_user.info_wr_fin_vfunc_active; + *p_last_wr_fin_onload_cnt = wr_fin_onload_cnt.info_axi_last_wr_fin_onload_cnt; + + return DPP_OK; +} + +/***********************************************************/ +/** 获取写完成通道错误次数统计 +* @param dev_id 芯片id +* @param p_axi_wr_fin_resp_err_cnt 写完成通道返回错误次数 +* +* @return +* @remark 无 +* @see +* @author cbb @date 2022/11/09 +************************************************************/ +ZXIC_UINT32 dpp_dtb_axi_wr_fin_resp_err_cnt_get(DPP_DEV_T *dev, + ZXIC_UINT32 *p_axi_wr_fin_resp_err_cnt + ) +{ + ZXIC_UINT32 rc = 0; + + DPP_DTB_DTB_CFG_CNT_AXI_WR_FIN_RESP_ERR_T wr_fin_resp_err_cnt= {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_axi_wr_fin_resp_err_cnt); + + rc = dpp_reg_read(dev, DTB_DTB_CFG_CNT_AXI_WR_FIN_RESP_ERRr, 0, 0, &wr_fin_resp_err_cnt); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + + *p_axi_wr_fin_resp_err_cnt = wr_fin_resp_err_cnt.cnt_axi_wr_fin_resp_err; + + return DPP_OK; +} + +#endif + +#if ZXIC_REAL("DTB_STATE") + +/***********************************************************/ +/** 读取 DTB 各通道状态机 +* @param dev_id 芯片id +* @param p_wr_ctrl_state_info 写控制状态机 +* @param p_rd_table_state_info 读表状态机 +* @param p_rd_pd_state_info 读描述符数据状态机 +* @param p_wr_ddr_state_info 写数据到ddr的状态机 +* @param p_wr_fin_state_info 写结束标志的状态机 +* +* @return +* @remark 无 +* @see +* @author cbb @date 2022/11/09 +************************************************************/ +ZXIC_UINT32 dpp_dtb_state_info_get(DPP_DEV_T *dev, + ZXIC_UINT32 *p_wr_ctrl_state_info, + ZXIC_UINT32 *p_rd_table_state_info, + ZXIC_UINT32 *p_rd_pd_state_info, + ZXIC_UINT32 *p_wr_ddr_state_info, + ZXIC_UINT32 *p_dump_cmd_state_info + ) +{ + + ZXIC_UINT32 rc = 0; + + DPP_DTB_DTB_CFG_INFO_WR_CTRL_STATE_T wr_ctrl_state = {0}; + DPP_DTB_DTB_CFG_INFO_RD_TABLE_STATE_T rd_table_state = {0}; + DPP_DTB_DTB_CFG_INFO_RD_PD_STATE_T rd_pd_state = {0}; + DPP_DTB_DTB_CFG_INFO_WR_DDR_STATE_T wr_ddr_state = {0}; + DPP_DTB_DTB_CFG_INFO_DUMP_CMD_STATE_T dump_cmd_state = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_wr_ctrl_state_info); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_rd_table_state_info); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_rd_pd_state_info); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_wr_ddr_state_info); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_dump_cmd_state_info); + + rc = dpp_reg_read(dev, DTB_DTB_CFG_INFO_WR_CTRL_STATEr, 0, 0, &wr_ctrl_state); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + rc = dpp_reg_read(dev, DTB_DTB_CFG_INFO_RD_TABLE_STATEr, 0, 0, &rd_table_state); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + rc = dpp_reg_read(dev, DTB_DTB_CFG_INFO_RD_PD_STATEr, 0, 0, &rd_pd_state); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + rc = dpp_reg_read(dev, DTB_DTB_CFG_INFO_WR_DDR_STATEr, 0, 0, &wr_ddr_state); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + rc = dpp_reg_read(dev, DTB_DTB_CFG_INFO_DUMP_CMD_STATEr, 0, 0, &dump_cmd_state); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + + *p_wr_ctrl_state_info = wr_ctrl_state.info_wr_ctrl_state; + *p_rd_table_state_info = rd_table_state.info_rd_table_state; + *p_rd_pd_state_info = rd_pd_state.info_rd_pd_state; + *p_wr_ddr_state_info = wr_ddr_state.info_wr_ddr_state; + *p_dump_cmd_state_info = dump_cmd_state.info_dump_cmd_state; + + return DPP_OK; +} + +#endif + +/***********************************************************/ +/** 各通道错误统计打印 +* @param dev_id 芯片的id号 +* +* @return +* @remark 无 +* @see +* @author cbb @date 2022/11/11 +************************************************************/ +ZXIC_UINT32 diag_dpp_dtb_channels_axi_resp_err_cnt_prt(DPP_DEV_T *dev) +{ + ZXIC_UINT32 rc = 0; + ZXIC_UINT32 rd_value = 0; + + ZXIC_COMM_PRINT("\n --------------- DTB CHANNEL ERR STAT INFO --------------- \n"); + + ZXIC_COMM_PRINT("********** dtb down table err cnt **********\n"); + + rc = dpp_dtb_axi_rd_table_resp_err_cnt_get(dev, &rd_value); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_dtb_axi_rd_table_resp_err_cnt_get"); + + ZXIC_COMM_DBGCNT32_PRINT("cnt_axi_rd_table_resp_err", rd_value); + + rc = dpp_dtb_axi_wr_ctrl_resp_err_cnt_get(dev, &rd_value); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_dtb_axi_wr_ctrl_resp_err_cnt_get"); + + ZXIC_COMM_DBGCNT32_PRINT("cnt_axi_wr_ctrl_resp_err", rd_value); + + ZXIC_COMM_PRINT("********** dtb dump table err cnt **********\n"); + + rc = dpp_dtb_axi_rd_pd_resp_err_cnt_get(dev, &rd_value); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_dtb_axi_rd_pd_resp_err_cnt_get"); + + ZXIC_COMM_DBGCNT32_PRINT("cnt_axi_rd_pd_resp_err", rd_value); + + rc = dpp_dtb_axi_wr_ddr_resp_err_cnt_get(dev, &rd_value); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_dtb_axi_wr_ddr_resp_err_cnt_get"); + + ZXIC_COMM_DBGCNT32_PRINT("cnt_axi_wr_ddr_resp_err", rd_value); + + rc = dpp_dtb_axi_wr_fin_resp_err_cnt_get(dev, &rd_value); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_dtb_axi_wr_fin_resp_err_cnt_get"); + + ZXIC_COMM_DBGCNT32_PRINT("cnt_axi_wr_fin_resp_err", rd_value); + + return DPP_OK; +} + +/***********************************************************/ +/** AXIM最近一次操作信息记录打印 +* @param dev_id 芯片的id号 +* +* @return +* @remark 无 +* @see +* @author cbb @date 2022/11/11 +************************************************************/ +ZXIC_UINT32 diag_dpp_dtb_axi_last_operate_info_prt(DPP_DEV_T *dev) +{ + ZXIC_UINT32 rc = 0; + ZXIC_UINT32 addr_high = 0; + ZXIC_UINT32 addr_low = 0; + ZXIC_UINT32 len = 0; + ZXIC_UINT32 onload_cnt = 0; + + DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_USER_T rd_table_user = {0}; + DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_USER_T rd_pd_user = {0}; + DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_USER_T wr_ctrl_user = {0}; + DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_USER_T wr_ddr_user = {0}; + DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_USER_T wr_fin_user = {0}; + ZXIC_COMM_PRINT("\n------------------ DTB DOWN TABLE LAST INFO ------------------\n"); + rc = dpp_dtb_axi_last_rd_table_info_get( dev, &addr_high, &addr_low, &len, (ZXIC_UINT32 *)&rd_table_user, &onload_cnt); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_dtb_axi_last_rd_table_info_get"); + ZXIC_COMM_PRINT("**********axim last read table info***********\n"); + ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_rd_table_addr_high", addr_high); + ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_rd_table_addr_low", addr_low); + ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_rd_table_len", len); + ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_rd_table_user_en", rd_table_user.info_rd_table_user_en); + ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_rd_table_epid", rd_table_user.info_rd_table_epid); + ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_rd_table_vfunc_num", rd_table_user.info_rd_table_vfunc_num); + ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_rd_table_func_num", rd_table_user.info_rd_table_func_num); + ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_rd_table_vfunc_active", rd_table_user.info_rd_table_vfunc_active); + ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_rd_table_onload_cnt", onload_cnt); + + rc = dpp_dtb_axi_last_wr_ctrl_info_get( dev, &addr_high, &addr_low, &len, (ZXIC_UINT32 *)&wr_ctrl_user, &onload_cnt); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_dtb_axi_last_wr_ctrl_info_get"); + ZXIC_COMM_PRINT("**********axim last write ctrl info***********\n"); + ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_wr_ctrl_addr_high", addr_high); + ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_wr_ctrl_addr_low", addr_low); + ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_wr_ctrl_len", len); + ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_wr_ctrl_user_en", wr_ctrl_user.info_wr_ctrl_user_en); + ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_wr_ctrl_epid", wr_ctrl_user.info_wr_ctrl_epid); + ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_wr_ctrl_vfunc_num", wr_ctrl_user.info_wr_ctrl_vfunc_num); + ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_wr_ctrl_func_num", wr_ctrl_user.info_wr_ctrl_func_num); + ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_wr_ctrl_vfunc_active", wr_ctrl_user.info_wr_ctrl_vfunc_active); + ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_wr_ctrl_onload_cnt", onload_cnt); + + ZXIC_COMM_PRINT("\n------------------ DTB DUMP TABLE LAST INFO ------------------\n"); + rc = dpp_dtb_axi_last_rd_pd_info_get( dev, &addr_high, &addr_low, &len, (ZXIC_UINT32*)&rd_pd_user, &onload_cnt); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_dtb_axi_last_rd_pd_info_get"); + ZXIC_COMM_PRINT("**********axim last read pd info***********\n"); + ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_rd_pd_addr_high", addr_high); + ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_rd_pd_addr_low", addr_low); + ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_rd_pd_len", len); + ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_rd_pd_user_en", rd_pd_user.info_rd_pd_user_en); + ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_rd_pd_epid", rd_pd_user.info_rd_pd_epid); + ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_rd_pd_vfunc_num", rd_pd_user.info_rd_pd_vfunc_num); + ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_rd_pd_func_num", rd_pd_user.info_rd_pd_func_num); + ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_rd_pd_vfunc_active", rd_pd_user.info_rd_pd_vfunc_active); + ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_rd_pd_onload_cnt", onload_cnt); + + rc = dpp_dtb_axi_last_wr_ddr_info_get( dev, &addr_high, &addr_low, &len, (ZXIC_UINT32 *)&wr_ddr_user, &onload_cnt); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_dtb_axi_last_wr_ddr_info_get"); + ZXIC_COMM_PRINT("**********axim last write ddr info***********\n"); + ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_wr_ddr_addr_high", addr_high); + ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_wr_ddr_addr_low", addr_low); + ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_wr_ddr_len", len); + ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_wr_ddr_user_en", wr_ddr_user.info_wr_ddr_user_en); + ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_wr_ddr_epid", wr_ddr_user.info_wr_ddr_epid); + ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_wr_ddr_vfunc_num", wr_ddr_user.info_wr_ddr_vfunc_num); + ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_wr_ddr_func_num", wr_ddr_user.info_wr_ddr_func_num); + ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_wr_ddr_vfunc_active", wr_ddr_user.info_wr_ddr_vfunc_active); + ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_wr_ddr_onload_cnt", onload_cnt); + + rc = dpp_dtb_axi_last_wr_fin_info_get( dev, &addr_high, &addr_low, &len, (ZXIC_UINT32 *)&wr_fin_user, &onload_cnt); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_dtb_axi_wr_fin_resp_err_cnt_get"); + ZXIC_COMM_PRINT("**********axim last write final info***********\n"); + ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_wr_fin_addr_high", addr_high); + ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_wr_fin_addr_low", addr_low); + ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_wr_fin_len", len); + ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_wr_fin_user_en", wr_fin_user.info_wr_fin_user_en); + ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_wr_fin_epid", wr_fin_user.info_wr_fin_epid); + ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_wr_fin_vfunc_num", wr_fin_user.info_wr_fin_vfunc_num); + ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_wr_fin_func_num", wr_fin_user.info_wr_fin_func_num); + ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_wr_fin_vfunc_active", wr_fin_user.info_wr_fin_vfunc_active); + ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_wr_fin_onload_cnt", onload_cnt); + + return DPP_OK; +} + +/***********************************************************/ +/** DTB 各通道状态机信息获取 +* @param dev_id 芯片的id号 +* +* @return +* @remark 无 +* @see +* @author cbb @date 2022/11/11 +************************************************************/ +ZXIC_UINT32 diag_dpp_dtb_channels_state_info_prt(DPP_DEV_T *dev) +{ + ZXIC_UINT32 rc = 0; + + ZXIC_UINT32 wr_ctrl_state = 0; + ZXIC_UINT32 rd_table_state = 0; + ZXIC_UINT32 rd_pd_state = 0; + ZXIC_UINT32 wr_ddr_state = 0; + ZXIC_UINT32 dump_cmd_state = 0; + + rc = dpp_dtb_state_info_get(dev, + &wr_ctrl_state, + &rd_table_state, + &rd_pd_state, + &wr_ddr_state, + &dump_cmd_state); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_dtb_stat_info_get"); + + ZXIC_COMM_PRINT("\n-------------- DTB CHANNEL STATE INFO ----------------- \n"); + ZXIC_COMM_PRINT("----- REG ------------------- CURRENT ------- CORRECT ----- \n"); + ZXIC_COMM_PRINT("info_wr_ctrl_state 0x%08x 0x00000005 \n", wr_ctrl_state); + ZXIC_COMM_PRINT("info_rd_table_state 0x%08x 0x00080004 \n", rd_table_state); + ZXIC_COMM_PRINT("info_rd_pd_state 0x%08x 0x00020020 \n", rd_pd_state); + ZXIC_COMM_PRINT("info_wr_ddr_state 0x%08x 0x00000001 \n", wr_ddr_state); + ZXIC_COMM_PRINT("info_dump_cmd_state 0x%08x 0x0000002a \n", dump_cmd_state); + + return DPP_OK; +} + +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/nppu/Kbuild.include b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/nppu/Kbuild.include new file mode 100644 index 0000000..b1f4bca --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/nppu/Kbuild.include @@ -0,0 +1,2 @@ +cur_dir := en_np/sdk/source/dev/module/nppu/ +src_files += $(addprefix $(cur_dir),$(notdir $(wildcard $(dinghai_root)/$(cur_dir)*.c))) diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/nppu/dpp_pbu.c b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/nppu/dpp_pbu.c new file mode 100755 index 0000000..962c73d --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/nppu/dpp_pbu.c @@ -0,0 +1,225 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_pbu.c +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : djf +* 完成日期 : 2014/04/14 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ + +/****************************************************************************** + * START: 头文件 * + *****************************************************************************/ +#include "zxic_common.h" +#include "dpp_type_api.h" +#include "dpp_reg.h" +#include "dpp_pbu_api.h" +#include "dpp_pbu.h" +#include "dpp_dev.h" +/****************************************************************************** + * END: 头文件 * + *****************************************************************************/ + + +/****************************************************************************** + * START: 常量定义 * + *****************************************************************************/ + +/****************************************************************************** + * END: 常量定义 * + *****************************************************************************/ +#define MF_MAX_BIT (4095) +#define MF_START_BIT (2047) +#define PKT_MAX_BIT (2047) +#define CAP_MAX_NUM (64) +#define PKT_BUFF_NUM (128) +#define PKT_BUF_SIZE (32) + + +/***********************************************************/ +/** 配置端口的阈值 +* @param dev_id 设备编号 +* @param port_id 端口号 +* @param p_para 端口阈值 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/07/09 +************************************************************/ +DPP_STATUS dpp_pbu_port_th_set(DPP_DEV_T *dev, + ZXIC_UINT32 port_id, + DPP_PBU_PORT_TH_PARA_T *p_para) +{ + DPP_STATUS rc = 0; + ZXIC_UINT32 *p_data = NULL; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), port_id, 0, DPP_PBU_PORT_NUM - 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_para); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_para->lif_th, 0, DPP_PBU_PORT_TH_MAX); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_para->lif_prv, 0, DPP_PBU_PORT_TH_MAX); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_para->idma_prv, 0, DPP_PBU_PORT_TH_MAX); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_para->idma_th_cos7, 0, DPP_PBU_PORT_TH_MAX); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_para->idma_th_cos6, 0, p_para->idma_th_cos7); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_para->idma_th_cos5, 0, p_para->idma_th_cos6); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_para->idma_th_cos4, 0, p_para->idma_th_cos5); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_para->idma_th_cos3, 0, p_para->idma_th_cos4); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_para->idma_th_cos2, 0, p_para->idma_th_cos3); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_para->idma_th_cos1, 0, p_para->idma_th_cos2); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_para->idma_th_cos0, 0, p_para->idma_th_cos1); + + + p_data = (ZXIC_UINT32*)p_para; + + rc = dpp_reg_write(dev, + NPPU_PBU_CFG_MEMID_0_PBU_FC_IDMATH_RAMr, + 0, + port_id, + p_data); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write"); + + return DPP_OK; +} + +/***********************************************************/ +/** 读取端口的阈值 +* @param dev_id 设备编号 +* @param port_id 端口号 +* @param p_para 端口阈值 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/07/09 +************************************************************/ +DPP_STATUS dpp_pbu_port_th_get(DPP_DEV_T *dev, + ZXIC_UINT32 port_id, + DPP_PBU_PORT_TH_PARA_T *p_para) +{ + DPP_STATUS rc = 0; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), port_id, 0, DPP_PBU_PORT_NUM - 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_para); + + rc = dpp_reg_read(dev, NPPU_PBU_CFG_MEMID_0_PBU_FC_IDMATH_RAMr, 0, port_id, (ZXIC_UINT32*)p_para); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + + + return DPP_OK; +} + +/***********************************************************/ +/** 配置指定端口按cos优先级起pfc流控的优先级流控指针阈值，仅对lif0的48个通道有效 +* @param dev_id 设备编号 +* @param port_id 端口号 +* @param p_para cos阈值，要求高优先级的阈值不小于低优先级的阈值 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/07/09 +************************************************************/ +DPP_STATUS dpp_pbu_port_cos_th_set(DPP_DEV_T *dev, + ZXIC_UINT32 port_id, + DPP_PBU_PORT_COS_TH_PARA_T *p_para) +{ + DPP_STATUS rc = 0; + ZXIC_UINT32 i = 0; + ZXIC_UINT32 tmp_index = 0; + ZXIC_UINT32 *p_data = NULL; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), port_id, 0, DPP_PBU_PORT_NUM - 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_para); + + if (port_id < DPP_PBU_LIF1_PORT_NUM) + { + tmp_index = port_id; + + } + else if (port_id == DPP_PBU_TM_LOOP_PORT_NUM) + { + tmp_index = 56; + + } + else + { + ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "dpp_pbu_port_cos_th_set: please check input port:%d !!!!!!\n", port_id); + return DPP_OK; + } + + for (i = 0; i < DPP_PBU_COS_NUM; i++) + { + if (0 == i) + { + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_para->cos_th[i], 0, DPP_PBU_PORT_COS_MAX_TH ); + } + else + { + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_para->cos_th[i], p_para->cos_th[i - 1], DPP_PBU_PORT_COS_MAX_TH); + } + } + + p_data = (ZXIC_UINT32*)p_para; + + rc = dpp_reg_write(dev, NPPU_PBU_CFG_MEMID_1_PBU_FC_MACTH_RAMr, 0, tmp_index, p_data ); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write"); + + return DPP_OK; +} + + +/***********************************************************/ +/** 读取指定端口中各cos的优先级流控指针阈值，仅对lif0的48个通道有效 +* @param dev_id 设备编号 +* @param port_id 端口号 +* @param p_para cos阈值，要求高优先级的阈值不小于低优先级的阈值 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/07/09 +************************************************************/ +DPP_STATUS dpp_pbu_port_cos_th_get(DPP_DEV_T *dev, + ZXIC_UINT32 port_id, + DPP_PBU_PORT_COS_TH_PARA_T *p_para) +{ + DPP_STATUS rc = 0; + ZXIC_UINT32 tmp_index = 0; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), port_id, 0, DPP_PBU_PORT_NUM - 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_para); + + if (port_id < DPP_PBU_LIF1_PORT_NUM) + { + tmp_index = port_id; + + } + else if (port_id == DPP_PBU_TM_LOOP_PORT_NUM) + { + tmp_index = 56; + + } + else + { + return DPP_OK; + } + + rc = dpp_reg_read(dev, NPPU_PBU_CFG_MEMID_1_PBU_FC_MACTH_RAMr, 0, tmp_index, (ZXIC_UINT32*)p_para); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + + return DPP_OK; +} diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/ppu/Kbuild.include b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/ppu/Kbuild.include new file mode 100644 index 0000000..9fcf516 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/ppu/Kbuild.include @@ -0,0 +1,2 @@ +cur_dir := en_np/sdk/source/dev/module/ppu/ +src_files += $(addprefix $(cur_dir),$(notdir $(wildcard $(dinghai_root)/$(cur_dir)*.c))) \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/ppu/dpp_ppu.c b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/ppu/dpp_ppu.c new file mode 100755 index 0000000..699b8ea --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/ppu/dpp_ppu.c @@ -0,0 +1,339 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_ppu.c +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : 王春雷 +* 完成日期 : 2014/03/18 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ + +#include "zxic_common.h" +#include "dpp_reg.h" +#include "dpp_dev.h" +#include "dpp_ppu_api.h" +#include "dpp_ppu.h" +#include "dpp_ppu4k_reg.h" + +#define OPR_WRITE (0) +#define OPR_READ (1) + +DPP_PPU_CLS_BITMAP_T g_ppu_cls_bit_map[DPP_DEV_CHANNEL_MAX]; + +#if ZXIC_REAL("INIT") + +ZXIC_UINT32 dpp_ppu_cls_use_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 cluster_id, + ZXIC_UINT32 flag) +{ + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, cluster_id, 0, DPP_PPU_CLUSTER_NUM - 1); + g_ppu_cls_bit_map[dev_id].cls_use[cluster_id] = flag; + + return DPP_OK; +} + +ZXIC_UINT32 dpp_ppu_cls_use_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 cluster_id) +{ + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, cluster_id, 0, DPP_PPU_CLUSTER_NUM - 1); + + return g_ppu_cls_bit_map[dev_id].cls_use[cluster_id]; +} + +ZXIC_UINT32 dpp_ppu_instr_mem_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 mem_id, + ZXIC_UINT32 flag) +{ + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, mem_id, 0, PPU_INSTR_MEM_NUM - 1); + g_ppu_cls_bit_map[dev_id].instr_mem[mem_id] = flag; + + return DPP_OK; +} + +#define DPP_PPU_CLS_USE_CHECK(dev_id,cls_id) \ + do{ \ + if (!dpp_ppu_cls_use_get(dev_id, cls_id))\ + {\ + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:cluster %d stop] ! FUNCTION : %s!\n",__FILE__,__LINE__,cls_id,__FUNCTION__);\ + ZXIC_COMM_ASSERT(0);\ + return DPP_ERR;\ + }\ + }while (0) + +ZXIC_UINT32 dpp_ppu_parse_cls_bitmap(ZXIC_UINT32 dev_id, + ZXIC_UINT32 bitmap) +{ + ZXIC_UINT32 cls_id = 0; + ZXIC_UINT32 mem_id = 0; + + ZXIC_UINT32 cls_use = 0; + ZXIC_UINT32 instr_mem = 0; + + /*cluster 使用标记必须保证至少有一个cluster是打开的使用的*/ + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, bitmap, 0, DPP_PPU_CLS_ALL_START); + + for (cls_id = 0; cls_id < DPP_PPU_CLUSTER_NUM; cls_id++) + { + cls_use = (bitmap >> cls_id) & 0x1; + + dpp_ppu_cls_use_set(dev_id, cls_id, cls_use); + } + + for (mem_id = 0; mem_id < PPU_INSTR_MEM_NUM; mem_id++) + { + instr_mem = (bitmap >> (mem_id * 2)) & 0x3; + + dpp_ppu_instr_mem_set(dev_id, mem_id, ((instr_mem > 0) ? 1 : 0)); + } + + return DPP_OK; +} + +#endif + +#if ZXIC_REAL("TABEL_CFG") +/***********************************************************/ +/** 配置SDT表 +* @param dev_id 设备号，范围0~3 +* @param cluster_id me cluster编号，范围0~7 +* @param index 地址，即sdt表号，范围0~255 +* @param p_sdt_data sdt表数据 +* +* @return +* @remark 无 +* @see +* @author 王春雷 @date 2014/03/18 +************************************************************/ +DPP_STATUS dpp_ppu_sdt_tbl_write(DPP_DEV_T *dev, ZXIC_UINT32 cluster_id, ZXIC_UINT32 index, DPP_SDT_TBL_DATA_T *p_sdt_data) +{ + DPP_STATUS rtn = DPP_OK; + DPP_PPU4K_CLUSTER_WR_HIGH_DATA_R_MEX_T high_data = {0}; + DPP_PPU4K_CLUSTER_WR_LOW_DATA_R_MEX_T low_data = {0}; + DPP_PPU4K_CLUSTER_ADDR_R_MEX_T sdt_cmd = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), index, PPU_SDT_IDX_MIN, PPU_SDT_IDX_MAX); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_sdt_data); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), cluster_id, 0, DPP_PPU_CLUSTER_NUM - 1); + DPP_PPU_CLS_USE_CHECK(DEV_ID(dev), cluster_id); + + /* write data reg*/ + high_data.wr_high_data_r_mex = p_sdt_data->data_high32; + low_data.wr_low_data_r_mex = p_sdt_data->data_low32; + rtn = dpp_reg_write(dev, + PPU4K_CLUSTER_WR_HIGH_DATA_R_MEXr, + cluster_id, + 0, + &high_data); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_write"); + + rtn = dpp_reg_write(dev, + PPU4K_CLUSTER_WR_LOW_DATA_R_MEXr, + cluster_id, + 0, + &low_data); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_write"); + + /* write cmd reg*/ + sdt_cmd.operate_type = OPR_WRITE; + sdt_cmd.addr_r_mex = index; + + rtn = dpp_reg_write(dev, + PPU4K_CLUSTER_ADDR_R_MEXr, + cluster_id, + 0, + &sdt_cmd); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_write"); + + return DPP_OK; +} +#endif + +#if ZXIC_REAL("PPU_STATICS") + +/***********************************************************/ +/**配置协处理器哈希计算密钥 +* @param dev_id 设备号 +* @param DPP_PPU_PPU_COP_THASH_RSK_T +* +* @return +* @remark 无 +* @see +* @author yangmy @date 2022/09/09 +************************************************************/ +DPP_STATUS dpp_ppu_ppu_cop_thash_rsk_set(DPP_DEV_T *dev, DPP_PPU_PPU_COP_THASH_RSK_T *p_para) +{ + DPP_STATUS rc = DPP_OK; + + DPP_PPU_PPU_COP_THASH_RSK_031_000_T rsk_031_000 = {0}; + DPP_PPU_PPU_COP_THASH_RSK_063_032_T rsk_063_032 = {0}; + DPP_PPU_PPU_COP_THASH_RSK_095_064_T rsk_095_064 = {0}; + DPP_PPU_PPU_COP_THASH_RSK_127_096_T rsk_127_096 = {0}; + DPP_PPU_PPU_COP_THASH_RSK_159_128_T rsk_159_128 = {0}; + DPP_PPU_PPU_COP_THASH_RSK_191_160_T rsk_191_160 = {0}; + DPP_PPU_PPU_COP_THASH_RSK_223_192_T rsk_223_192 = {0}; + DPP_PPU_PPU_COP_THASH_RSK_255_224_T rsk_255_224 = {0}; + DPP_PPU_PPU_COP_THASH_RSK_287_256_T rsk_287_256 = {0}; + DPP_PPU_PPU_COP_THASH_RSK_319_288_T rsk_319_288 = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_para); + + + + rsk_031_000.rsk_031_000 = p_para->rsk_031_000; + rsk_063_032.rsk_063_032 = p_para->rsk_063_032; + rsk_095_064.rsk_095_064 = p_para->rsk_095_064; + rsk_127_096.rsk_127_096 = p_para->rsk_127_096; + rsk_159_128.rsk_159_128 = p_para->rsk_159_128; + rsk_191_160.rsk_191_160 = p_para->rsk_191_160; + rsk_223_192.rsk_223_192 = p_para->rsk_223_192; + rsk_255_224.rsk_255_224 = p_para->rsk_255_224; + rsk_287_256.rsk_287_256 = p_para->rsk_287_256; + rsk_319_288.rsk_319_288 = p_para->rsk_319_288; + + + rc = dpp_reg_write(dev, + PPU_PPU_COP_THASH_RSK_031_000r, + 0, + 0, + &rsk_031_000); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write"); + + rc = dpp_reg_write(dev, + PPU_PPU_COP_THASH_RSK_063_032r, + 0, + 0, + &rsk_063_032); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write"); + + rc = dpp_reg_write(dev, + PPU_PPU_COP_THASH_RSK_095_064r, + 0, + 0, + &rsk_095_064); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write"); + + rc = dpp_reg_write(dev, + PPU_PPU_COP_THASH_RSK_127_096r, + 0, + 0, + &rsk_127_096); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write"); + + rc = dpp_reg_write(dev, + PPU_PPU_COP_THASH_RSK_159_128r, + 0, + 0, + &rsk_159_128); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write"); + + rc = dpp_reg_write(dev, + PPU_PPU_COP_THASH_RSK_191_160r, + 0, + 0, + &rsk_191_160); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write"); + + rc = dpp_reg_write(dev, + PPU_PPU_COP_THASH_RSK_223_192r, + 0, + 0, + &rsk_223_192); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write"); + + + rc = dpp_reg_write(dev, + PPU_PPU_COP_THASH_RSK_255_224r, + 0, + 0, + &rsk_255_224); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write"); + + + rc = dpp_reg_write(dev, + PPU_PPU_COP_THASH_RSK_287_256r, + 0, + 0, + &rsk_287_256); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write"); + + + rc = dpp_reg_write(dev, + PPU_PPU_COP_THASH_RSK_319_288r, + 0, + 0, + &rsk_319_288); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write"); + return DPP_OK; +} + +DPP_STATUS dpp_ppu_ppu_cop_thash_rsk_get(DPP_DEV_T *dev, DPP_PPU_PPU_COP_THASH_RSK_T *p_ppu_cop_thash_rsk) +{ + DPP_STATUS rtn = DPP_OK; + + DPP_PPU_PPU_COP_THASH_RSK_031_000_T rsk_031_000 = {0}; + DPP_PPU_PPU_COP_THASH_RSK_063_032_T rsk_063_032 = {0}; + DPP_PPU_PPU_COP_THASH_RSK_095_064_T rsk_095_064 = {0}; + DPP_PPU_PPU_COP_THASH_RSK_127_096_T rsk_127_096 = {0}; + DPP_PPU_PPU_COP_THASH_RSK_159_128_T rsk_159_128 = {0}; + DPP_PPU_PPU_COP_THASH_RSK_191_160_T rsk_191_160 = {0}; + DPP_PPU_PPU_COP_THASH_RSK_223_192_T rsk_223_192 = {0}; + DPP_PPU_PPU_COP_THASH_RSK_255_224_T rsk_255_224 = {0}; + DPP_PPU_PPU_COP_THASH_RSK_287_256_T rsk_287_256 = {0}; + DPP_PPU_PPU_COP_THASH_RSK_319_288_T rsk_319_288 = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_ppu_cop_thash_rsk); + + rtn = dpp_reg_read(dev, PPU_PPU_COP_THASH_RSK_031_000r, 0, 0, &rsk_031_000); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_read"); + rtn = dpp_reg_read(dev, PPU_PPU_COP_THASH_RSK_063_032r, 0, 0, &rsk_063_032); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_read"); + rtn = dpp_reg_read(dev, PPU_PPU_COP_THASH_RSK_095_064r, 0, 0, &rsk_095_064); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_read"); + rtn = dpp_reg_read(dev, PPU_PPU_COP_THASH_RSK_127_096r, 0, 0, &rsk_127_096); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_read"); + rtn = dpp_reg_read(dev, PPU_PPU_COP_THASH_RSK_159_128r, 0, 0, &rsk_159_128); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_read"); + rtn = dpp_reg_read(dev, PPU_PPU_COP_THASH_RSK_191_160r, 0, 0, &rsk_191_160); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_read"); + rtn = dpp_reg_read(dev, PPU_PPU_COP_THASH_RSK_223_192r, 0, 0, &rsk_223_192); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_read"); + rtn = dpp_reg_read(dev, PPU_PPU_COP_THASH_RSK_255_224r, 0, 0, &rsk_255_224); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_read"); + rtn = dpp_reg_read(dev, PPU_PPU_COP_THASH_RSK_287_256r, 0, 0, &rsk_287_256); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_read"); + rtn = dpp_reg_read(dev, PPU_PPU_COP_THASH_RSK_319_288r, 0, 0, &rsk_319_288); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_read"); + + + p_ppu_cop_thash_rsk->rsk_031_000 = rsk_031_000.rsk_031_000; + p_ppu_cop_thash_rsk->rsk_063_032 = rsk_063_032.rsk_063_032; + p_ppu_cop_thash_rsk->rsk_095_064 = rsk_095_064.rsk_095_064; + p_ppu_cop_thash_rsk->rsk_127_096 = rsk_127_096.rsk_127_096; + p_ppu_cop_thash_rsk->rsk_159_128 = rsk_159_128.rsk_159_128; + p_ppu_cop_thash_rsk->rsk_191_160 = rsk_191_160.rsk_191_160; + p_ppu_cop_thash_rsk->rsk_223_192 = rsk_223_192.rsk_223_192; + p_ppu_cop_thash_rsk->rsk_255_224 = rsk_255_224.rsk_255_224; + p_ppu_cop_thash_rsk->rsk_287_256 = rsk_287_256.rsk_287_256; + p_ppu_cop_thash_rsk->rsk_319_288 = rsk_319_288.rsk_319_288; + + + return DPP_OK; + +} + +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se/Kbuild.include b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se/Kbuild.include new file mode 100644 index 0000000..bda349a --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se/Kbuild.include @@ -0,0 +1,2 @@ +cur_dir := en_np/sdk/source/dev/module/se/ +src_files += $(addprefix $(cur_dir),$(notdir $(wildcard $(dinghai_root)/$(cur_dir)*.c))) \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se/dpp_etcam.c b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se/dpp_etcam.c new file mode 100644 index 0000000..f92a6fe --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se/dpp_etcam.c @@ -0,0 +1,814 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_etcam.c +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : 王春雷 +* 完成日期 : 2014/04/03 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ + +#include "zxic_common.h" + +#include "dpp_reg.h" +#include "dpp_se_api.h" +#include "dpp_etcam.h" +#include "dpp_dev.h" +#include "dpp_stat4k_reg.h" + +#define DPP_ETCAM_OPR_WR (1) +#define DPP_ETCAM_OPR_RD (2) +#define DPP_ETCAM_OPR_UNLOAD (3) +#define DPP_ETCAM_OPR_VBIT (4) + +#define TBLID_CFG_SETP (8) +#define BADDR_CFG_SETP (4) + +/** 当前etcam 条目vld信息 */ +DPP_ETCAM_ENTRY_VLD_T g_etcam_vld_info[DPP_DEV_CHANNEL_MAX][DPP_ETCAM_BLOCK_NUM][DPP_ETCAM_RAM_DEPTH] = {{{{0}}}}; +#define GET_ETCAM_VLD_INFO(dev_id,block_id,block_index) (g_etcam_vld_info[dev_id][block_id] + block_index) + +#if ZXIC_REAL("IN_FUNC") +/***********************************************************/ +/** 将用户输入的D/M格式的数据转换为写硬件需要的X/Y数据 +* @param p_dm +* @param p_xy +* @param len +* +* @return +* @remark 无 +* @see +* @author 王春雷 @date 2014/04/03 +************************************************************/ +DPP_STATUS dpp_etcam_dm_to_xy(DPP_ETCAM_ENTRY_T *p_dm, + DPP_ETCAM_ENTRY_T *p_xy, + ZXIC_UINT32 len) +{ + ZXIC_UINT32 i = 0; + + ZXIC_COMM_CHECK_POINT(p_dm); + ZXIC_COMM_CHECK_POINT(p_xy); + ZXIC_COMM_CHECK_INDEX(len, 0, DPP_ETCAM_WIDTH_MAX / 8); + ZXIC_COMM_ASSERT(p_dm->p_data && p_dm->p_mask && p_xy->p_data && p_xy->p_mask); + + for (i = 0; i < len; i++) + { + p_xy->p_data[i] = ZXIC_COMM_DM_TO_X(p_dm->p_data[i], p_dm->p_mask[i]); + p_xy->p_mask[i] = ZXIC_COMM_DM_TO_Y(p_dm->p_data[i], p_dm->p_mask[i]); + } + + return DPP_OK; +} + +/***********************************************************/ +/** 将从硬件读到的X/Y格式的数据转换为用户需要的D/M数据 +* @param p_xy +* @param p_dm +* @param len +* +* @return +* @remark 无 +* @see +* @author 王春雷 @date 2014/04/03 +************************************************************/ +DPP_STATUS dpp_etcam_xy_to_dm(DPP_ETCAM_ENTRY_T *p_dm, + DPP_ETCAM_ENTRY_T *p_xy, + ZXIC_UINT32 len) +{ + ZXIC_UINT32 i = 0; + + ZXIC_COMM_CHECK_POINT(p_dm); + ZXIC_COMM_CHECK_POINT(p_xy); + ZXIC_COMM_CHECK_INDEX(len, 0, DPP_ETCAM_WIDTH_MAX / 8); + ZXIC_COMM_ASSERT(p_dm->p_data && p_dm->p_mask && p_xy->p_data && p_xy->p_mask); + + for (i = 0; i < len; i++) + { + p_dm->p_data[i] = ZXIC_COMM_XY_TO_DATA(p_xy->p_data[i], p_xy->p_mask[i]); /* valid only when mask is 0 */ + p_dm->p_mask[i] = ZXIC_COMM_XY_TO_MASK(p_xy->p_data[i], p_xy->p_mask[i]); + } + + return DPP_OK; +} + +/***********************************************************/ +/** 根据读写模式，获取需要操作的间接寄存器掩码 +* @param mask block RAM操作位图，共8比特，每比特对应一个block RAM行的80bit +* +* @return +* @remark 无 +* @see +* @author 王春雷 @date 2014/03/31 +************************************************************/ +ZXIC_UINT32 dpp_etcam_ind_data_reg_opr_mask_get(ZXIC_UINT32 mask) +{ + ZXIC_UINT32 i = 0; + ZXIC_UINT32 reg_mask = 0; + + ZXIC_COMM_CHECK_INDEX(mask, 0, 0xff); + + for (i = 0; i < DPP_ETCAM_RAM_NUM; i++) + { + if ((mask >> i) & 0x1) + { + reg_mask |= ((ZXIC_UINT32)0x7 << ((i / 2) * 5 + (i % 2) * 2)); + } + } + + return reg_mask; +} + +/***********************************************************/ +/** 写eTcam表项数据 +* @param dev_id +* @param wr_mask +* @param p_data +* +* @return +* @remark 无 +* @see +* @author 王春雷 @date 2014/03/31 +************************************************************/ +DPP_STATUS dpp_etcam_ind_data_set(DPP_DEV_T *dev, ZXIC_UINT32 wr_mask, ZXIC_UINT8 *p_data) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 i = 0; + ZXIC_UINT32 offset = 0; + ZXIC_UINT32 reg_mask = 0; + ZXIC_UINT8 *p_temp = NULL; + ZXIC_UINT8 buff[DPP_ETCAM_WIDTH_MAX / 8] = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), wr_mask, 0, DPP_ETCAM_WR_MASK_MAX); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data); + + p_temp = p_data; + + /* 160bit key: high 80bit in tcam_ram1, low 80bit in tcam_ram0, and so on. */ + for (i = 0; i < DPP_ETCAM_RAM_NUM; i++) + { + offset = i * ((ZXIC_UINT32)DPP_ETCAM_WIDTH_MIN / 8); + + if ((wr_mask >> (DPP_ETCAM_RAM_NUM - 1 - i)) & 0x1) + { + ZXIC_COMM_MEMCPY(buff + offset, p_temp, DPP_ETCAM_WIDTH_MIN / 8); + p_temp += DPP_ETCAM_WIDTH_MIN / 8; + } + } + + zxic_comm_swap(buff, DPP_ETCAM_WIDTH_MAX / 8); + + /* get ind data reg operate mask, 20bit */ + reg_mask = dpp_etcam_ind_data_reg_opr_mask_get(wr_mask); + + /* cpu_ind_wdat0 reg is for lowest 32bit data. */ + for (i = 0; i < (DPP_ETCAM_WIDTH_MAX / 32); i++) + { + if ((reg_mask >> (DPP_ETCAM_WIDTH_MAX / 32 - 1 - i)) & 0x1) + { + rc = dpp_reg_write(dev, + STAT_ETCAM_CPU_IND_WDAT19r - i, + 0, + 0, + (buff + i * sizeof(ZXIC_UINT32))); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write"); + } + } + + return DPP_OK; +} + +/***********************************************************/ +/** 写eTcam间接命令寄存器 +* @param dev_id +* @param addr etcam地址(0-511) +* @param block_idx block索引(0-15) +* @param data_or_mask 1：写X(data), 0:写Y(mask) +* @param wr_mask 写入掩码, 最高8bit, 对应bit为1代表对应的80bit数据 +* @param opr_type 1-write, 2-read, 3-unload +* @param tacm_reg_flag 1：配置内部row_col_mask寄存器 还是0：读写tcam +* @param row_mask_flag 1: write row_mask reg, 0: write col_mask reg +* @param vben enable the valid bit addressed by addr +* @param vbit valid bit input +* +* @return +* @remark 无 +* @see +* @author 王春雷 @date 2014/03/29 +* @modify YXH @date 2018/11/29 +************************************************************/ +DPP_STATUS dpp_etcam_ind_cmd_set(DPP_DEV_T *dev, + ZXIC_UINT32 addr, + ZXIC_UINT32 block_idx, + ZXIC_UINT32 data_or_mask, + ZXIC_UINT32 wr_mask, + ZXIC_UINT32 opr_type, + ZXIC_UINT32 tacm_reg_flag, + ZXIC_UINT32 row_mask_flag, + ZXIC_UINT32 vben, + ZXIC_UINT32 vbit) +{ + DPP_STATUS rc = DPP_OK; + DPP_STAT_ETCAM_CPU_IND_CTRL_TMP0_T ind_cmd = {0}; + DPP_STAT_ETCAM_CPU_IND_CTRL_TMP1_T ind_cmd_1 = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), addr, 0, DPP_ETCAM_RAM_DEPTH - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), block_idx, 0, DPP_ETCAM_BLOCK_NUM - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), data_or_mask, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), wr_mask, 0, DPP_ETCAM_WR_MASK_MAX); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), opr_type, 1, 4); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), tacm_reg_flag, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), row_mask_flag, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), vben, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), vbit, 0, 0xff); + + /* 一定要先配置 配置寄存器1,再配置 配置寄存器0 */ + ind_cmd_1.row_or_col_msk = row_mask_flag; + ind_cmd_1.vben = vben; + ind_cmd_1.vbit = vbit; + + rc = dpp_reg_write(dev, + STAT_ETCAM_CPU_IND_CTRL_TMP1r, + 0, + 0, + &ind_cmd_1); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write"); + + /* opr_type: 1-write, 2-read, 3-unload */ + switch (opr_type) + { + case DPP_ETCAM_OPR_RD: + { + ind_cmd.rd_wr = 1; + } + break; + + case DPP_ETCAM_OPR_WR: + { + ind_cmd.rd_wr = 0; + ind_cmd.wr_mode = wr_mask; + } + break; + + case DPP_ETCAM_OPR_UNLOAD: + { + /* 掩码表，决定哪些条目删除,8bit */ + ind_cmd.flush = wr_mask; + } + break; + + case DPP_ETCAM_OPR_VBIT: + { + /* 获取该地址的vbit valid位状态 */ + ind_cmd.rd_wr = 1; + ind_cmd.wr_mode = wr_mask; + } + break; + + default: + { + ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "Invalid opr_type!\n"); + ZXIC_COMM_ASSERT(0); + return DPP_ERR; + } + } + + ind_cmd.dat_or_mask = data_or_mask; + ind_cmd.ram_sel = block_idx; + ind_cmd.addr = addr; + + ZXIC_COMM_TRACE_DEBUG("data_or_mask:%d\n", ind_cmd.dat_or_mask); + ZXIC_COMM_TRACE_DEBUG("block_idx:%d\n", ind_cmd.ram_sel); + ZXIC_COMM_TRACE_DEBUG("addr:0x%08x\n", ind_cmd.addr); + + rc = dpp_reg_write(dev, + STAT_ETCAM_CPU_IND_CTRL_TMP0r, + 0, + 0, + &ind_cmd); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write"); + + return DPP_OK; +} + +#endif + +#if ZXIC_REAL("EX_FUNC") +/***********************************************************/ +/** 获取etcam中每个block的cpu操作fifo将满信号，若将满则cpu不能再操作当前block +* @param dev_id 设备号 +* @param block_idx etcam中的block编号，范围0~15 +* @param p_cpu_afull +* +* @return +* @remark 无 +* @see +* @author 王春雷 @date 2015/02/07 +************************************************************/ +DPP_STATUS dpp_etcam_cpu_afull_get(DPP_DEV_T *dev, ZXIC_UINT32 block_idx, ZXIC_UINT32 *p_cpu_afull) +{ + DPP_STATUS rc = DPP_OK; + DPP_STAT_ETCAM_ETCAM_CPU_FL_T cpu_fl = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), block_idx, 0, DPP_ETCAM_BLOCK_NUM - 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_cpu_afull); + + rc = dpp_reg_read(dev, STAT_ETCAM_ETCAM_CPU_FLr, 0, 0, &cpu_fl); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + + *p_cpu_afull = (cpu_fl.etcam_cpu_fl >> block_idx) & 0x1; + + return DPP_OK; +} + +/***********************************************************/ +/** 校验etcam中每个block的cpu操作fifo将满信号，若将满则cpu不能再操作当前block +* @param dev_id 设备号 +* @param block_idx etcam中的block编号，范围0~7 +* +* @return +* @remark 无 +* @see +* @author wll @date 2019/04/15 +************************************************************/ +DPP_STATUS dpp_etcam_cpu_afull_check(DPP_DEV_T *dev, ZXIC_UINT32 block_idx) +{ + ZXIC_UINT32 read_cnt = 0; + ZXIC_UINT32 cpu_afull = 1; + DPP_STATUS rc = DPP_OK; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), block_idx, 0, DPP_ETCAM_BLOCK_NUM - 1); + + while (cpu_afull) + { + rc = dpp_etcam_cpu_afull_get(dev, block_idx, &cpu_afull); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_etcam_cpu_afull_get"); + + if (!cpu_afull) + { + break; + } + + read_cnt++; + + if (read_cnt > DPP_RD_CNT_MAX * DPP_RD_CNT_MAX) + { + ZXIC_COMM_TRACE_ERROR("Error!!! dpp_etcam_cpu_afull_check is overtime!\n"); + return DPP_ERR; + } + + /* zxic_comm_usleep(100); */ + } + + return DPP_OK; +} + +/***********************************************************/ +/** 添加eTcam表条目 +* @param dev_id 设备号 +* @param addr 每个block中的ram地址，位宽为8*80bit +* @param block_idx block编号，范围0~7 +* @param wr_mask 写表掩码，共8bit，每bit控制ram中对应位置的80bit数据是否有效 +* @param opr_type etcam操作类型，详见 DPP_ETCAM_OPR_TYPE_E +* @param p_entry 条目数据，data和mask +* +* @return +* @remark 无 +* @see +* @author 王春雷 @date 2014/04/03 +************************************************************/ +DPP_STATUS dpp_etcam_entry_add(DPP_DEV_T *dev, + ZXIC_UINT32 addr, + ZXIC_UINT32 block_idx, + ZXIC_UINT32 wr_mask, + ZXIC_UINT32 opr_type, + DPP_ETCAM_ENTRY_T *p_entry) +{ + DPP_STATUS rc = DPP_OK; + // ZXIC_UINT32 i = 0; + // ZXIC_UINT32 tbl_id = 0; + // ZXIC_UINT32 handle_row = 0; + // ZXIC_UINT32 handle = 0; + // ZXIC_UINT32 basea_addr = 0; + ZXIC_UINT8 temp_data[DPP_ETCAM_WIDTH_MAX / 8] = {0}; + ZXIC_UINT8 temp_mask[DPP_ETCAM_WIDTH_MAX / 8] = {0}; + ZXIC_MUTEX_T *p_etcam_mutex = NULL; + DPP_ETCAM_ENTRY_T entry_xy = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), addr, 0, DPP_ETCAM_RAM_DEPTH - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), block_idx, 0, DPP_ETCAM_BLOCK_NUM - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), wr_mask, 0, DPP_ETCAM_WR_MASK_MAX); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), opr_type, DPP_ETCAM_OPR_DM, DPP_ETCAM_OPR_XY); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_entry); + + rc = dpp_dev_opr_mutex_get(DEV_ID(dev), DPP_DEV_MUTEX_T_ETCAM, &p_etcam_mutex); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dev_opr_mutex_get"); + + rc = zxic_comm_mutex_lock(p_etcam_mutex); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "zxic_comm_mutex_lock"); + + /* check cpu fifo is afull */ + rc = dpp_etcam_cpu_afull_check(dev, block_idx); + ZXIC_COMM_CHECK_DEV_RC_UNLOCK(DEV_ID(dev), rc, "dpp_etcam_cpu_afull_check", p_etcam_mutex); + + ZXIC_COMM_ASSERT(p_entry->p_data && p_entry->p_mask); + + entry_xy.p_data = temp_data; + entry_xy.p_mask = temp_mask; + + if (opr_type == DPP_ETCAM_OPR_DM) + { + /* convert user D/M data to X/Y */ + rc = dpp_etcam_dm_to_xy(p_entry, &entry_xy, DPP_ETCAM_ENTRY_SIZE_GET(p_entry->mode)); + ZXIC_COMM_CHECK_DEV_RC_UNLOCK(DEV_ID(dev), rc, "dpp_etcam_dm_to_xy", p_etcam_mutex); + } + else + { + ZXIC_COMM_MEMCPY(entry_xy.p_data, p_entry->p_data, DPP_ETCAM_ENTRY_SIZE_GET(p_entry->mode)); + ZXIC_COMM_MEMCPY(entry_xy.p_mask, p_entry->p_mask, DPP_ETCAM_ENTRY_SIZE_GET(p_entry->mode)); + } + + /* write data X */ + rc = dpp_etcam_ind_data_set(dev, wr_mask, entry_xy.p_data); + ZXIC_COMM_CHECK_DEV_RC_UNLOCK(DEV_ID(dev), rc, "dpp_etcam_ind_data_set", p_etcam_mutex); + + rc = dpp_etcam_ind_cmd_set(dev, + addr, + block_idx, + DPP_ETCAM_DTYPE_DATA, + wr_mask, + DPP_ETCAM_OPR_WR, + 0, + 0, + 1, + 0); + ZXIC_COMM_CHECK_DEV_RC_UNLOCK(DEV_ID(dev), rc, "dpp_etcam_ind_cmd_set", p_etcam_mutex); + + /* write mask Y */ + rc = dpp_etcam_ind_data_set(dev, wr_mask, entry_xy.p_mask); + ZXIC_COMM_CHECK_DEV_RC_UNLOCK(DEV_ID(dev), rc, "dpp_etcam_ind_data_set", p_etcam_mutex); + + rc = dpp_etcam_ind_cmd_set(dev, + addr, + block_idx, + DPP_ETCAM_DTYPE_MASK, + wr_mask, + DPP_ETCAM_OPR_WR, + 0, + 0, + 1, + 0xFF); + ZXIC_COMM_CHECK_DEV_RC_UNLOCK(DEV_ID(dev), rc, "dpp_etcam_ind_cmd_set", p_etcam_mutex); + + rc = zxic_comm_mutex_unlock(p_etcam_mutex); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "zxic_comm_mutex_unlock"); + + return DPP_OK; +} + +/***********************************************************/ +/** 删除eTcam表项条目 +* @param dev_id 设备号 +* @param addr 每个block中的ram地址，位宽为8*80bit +* @param block_idx block的编号，范围0~7 +* @param wr_mask 写表掩码，共8bit，每bit控制ram中对应位置的80bit数据是否有效 +* +* @return +* @remark 无 +* @see +* @author 王春雷 @date 2014/04/03 +************************************************************/ +DPP_STATUS dpp_etcam_entry_del(DPP_DEV_T *dev, + ZXIC_UINT32 addr, + ZXIC_UINT32 block_idx, + ZXIC_UINT32 wr_mask) +{ + DPP_STATUS rc = DPP_OK; + // ZXIC_UINT32 i = 0; + // ZXIC_UINT32 tbl_id = 0; + // ZXIC_UINT32 handle_row = 0; + // ZXIC_UINT32 handle = 0; + // ZXIC_UINT32 basea_addr = 0; + + ZXIC_UINT8 temp_data[DPP_ETCAM_WIDTH_MAX / 8] = {0xff,}; + ZXIC_UINT8 temp_mask[DPP_ETCAM_WIDTH_MAX / 8] = {0,}; + ZXIC_MUTEX_T *p_etcam_mutex = NULL; + DPP_ETCAM_ENTRY_T entry_xy = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), addr, 0, DPP_ETCAM_RAM_DEPTH - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), block_idx, 0, DPP_ETCAM_BLOCK_NUM - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), wr_mask, 0, DPP_ETCAM_WR_MASK_MAX); + + ZXIC_COMM_MEMSET(temp_data, 0xff, DPP_ETCAM_WIDTH_MAX / 8); + ZXIC_COMM_MEMSET(temp_mask, 0, DPP_ETCAM_WIDTH_MAX / 8); + + entry_xy.p_data = temp_data; + entry_xy.p_mask = temp_mask; + + rc = dpp_dev_opr_mutex_get(DEV_ID(dev), DPP_DEV_MUTEX_T_ETCAM, &p_etcam_mutex); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dev_opr_mutex_get"); + + rc = zxic_comm_mutex_lock(p_etcam_mutex); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "zxic_comm_mutex_lock"); + + /* check cpu fifo is afull */ + rc = dpp_etcam_cpu_afull_check(dev, block_idx); + ZXIC_COMM_CHECK_DEV_RC_UNLOCK(DEV_ID(dev), rc, "dpp_etcam_cpu_afull_check", p_etcam_mutex); + + /* write data X */ + rc = dpp_etcam_ind_data_set(dev, wr_mask, entry_xy.p_data); + ZXIC_COMM_CHECK_DEV_RC_UNLOCK(DEV_ID(dev), rc, "dpp_etcam_ind_data_set", p_etcam_mutex); + + rc = dpp_etcam_ind_cmd_set(dev, + addr, + block_idx, + DPP_ETCAM_DTYPE_DATA, + wr_mask, + DPP_ETCAM_OPR_WR, + 0, + 0, + 1, + 0xFF); + ZXIC_COMM_CHECK_DEV_RC_UNLOCK(DEV_ID(dev), rc, "dpp_etcam_ind_cmd_set", p_etcam_mutex); + + /* write mask Y */ + rc = dpp_etcam_ind_data_set(dev, wr_mask, entry_xy.p_mask); + ZXIC_COMM_CHECK_DEV_RC_UNLOCK(DEV_ID(dev), rc, "dpp_etcam_ind_data_set", p_etcam_mutex); + + rc = dpp_etcam_ind_cmd_set(dev, + addr, + block_idx, + DPP_ETCAM_DTYPE_MASK, + wr_mask, + DPP_ETCAM_OPR_WR, + 0, + 0, + 1, + 0xFF); + ZXIC_COMM_CHECK_DEV_RC_UNLOCK(DEV_ID(dev), rc, "dpp_etcam_ind_cmd_set", p_etcam_mutex); + + rc = zxic_comm_mutex_unlock(p_etcam_mutex); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "zxic_comm_mutex_unlock"); + + return DPP_OK; +} + +/***********************************************************/ +/** 比较一组data/mask和一组X/Y数据内容是否相异 +* @param p_entry_dm 待比较的data/mask数据 +* @param p_entry_xy 待比较的一组X/Y组合数据 +* +* @return 1-不同，0-相同 +* @remark 无 +* @see +* @author 王春雷 @date 2015/04/23 +************************************************************/ +ZXIC_UINT32 dpp_etcam_entry_cmp(DPP_ETCAM_ENTRY_T *p_entry_dm, DPP_ETCAM_ENTRY_T *p_entry_xy) +{ + DPP_STATUS rc = 0; + ZXIC_UINT32 data_len = 0; + ZXIC_UINT8 temp_data[DPP_ETCAM_WIDTH_MAX / 8] = {0}; + ZXIC_UINT8 temp_mask[DPP_ETCAM_WIDTH_MAX / 8] = {0}; + DPP_ETCAM_ENTRY_T entry_xy_temp = {0}; + + ZXIC_COMM_CHECK_POINT(p_entry_dm); + ZXIC_COMM_CHECK_POINT(p_entry_xy); + + entry_xy_temp.mode = p_entry_dm->mode; + entry_xy_temp.p_data = temp_data; + entry_xy_temp.p_mask = temp_mask; + data_len = DPP_ETCAM_ENTRY_SIZE_GET(entry_xy_temp.mode); + + if(data_len > 80) + { + return 1; + } + + ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW_NO_ASSERT(3U, entry_xy_temp.mode); + rc = dpp_etcam_dm_to_xy(p_entry_dm, &entry_xy_temp, data_len); + ZXIC_COMM_CHECK_RC(rc, "dpp_etcam_dm_to_xy"); + + if ((ZXIC_COMM_MEMCMP(entry_xy_temp.p_data, p_entry_xy->p_data, data_len) != 0) || + (ZXIC_COMM_MEMCMP(entry_xy_temp.p_mask, p_entry_xy->p_mask, data_len) != 0)) + { + return 1; + } + + return 0; +} + +/***********************************************************/ +/** 配置block的业务号，table_id +* @param dev_id 设备号 +* @param block_idx block的索引值。范围[0~7] +* @param tbl_id 表号，范围[0~7] +* +* @return +* @remark 无 +* @see +* @author 王春雷 @date 2014/04/08 +************************************************************/ +DPP_STATUS dpp_etcam_block_tbl_id_set(DPP_DEV_T *dev, + ZXIC_UINT32 block_idx, + ZXIC_UINT32 tbl_id) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 reg_offset = 0; + ZXIC_UINT32 bit_offset = 0; + ZXIC_UINT32 *p_temp = 0; + DPP_STAT4K_ETCAM_BLOCK0_7_PORT_ID_CFG_T block_tbl_id = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), block_idx, 0, DPP_ETCAM_BLOCK_NUM - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), tbl_id, 0, DPP_ETCAM_TBLID_NUM - 1); + + /*reg_offset 表示第几个寄存器进行配置，共四组配置寄存器*/ + reg_offset = block_idx / TBLID_CFG_SETP; + /*bit_offset 一个寄存器可以配置四组port_id,本位表示寄存器内配置的偏移*/ + bit_offset = block_idx % TBLID_CFG_SETP; + + /*取出当前的配置*/ + rc = dpp_reg_read(dev, + STAT4K_ETCAM_BLOCK0_7_PORT_ID_CFGr + reg_offset, + 0, + 0, + &block_tbl_id); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + /*计算出来配置当前的port_id所处的地址*/ + p_temp = (ZXIC_UINT32 *)(&block_tbl_id) + 7 - bit_offset; + + *p_temp = tbl_id; + + rc = dpp_reg_write(dev, + STAT4K_ETCAM_BLOCK0_7_PORT_ID_CFGr + reg_offset, + 0, + 0, + &block_tbl_id); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write"); + + return DPP_OK; +} + +/***********************************************************/ +/** 获取block的业务号，table_id +* @param dev_id +* @param block_idx +* @param p_tbl_id +* +* @return +* @remark 无 +* @see +* @author 王春雷 @date 2014/04/08 +************************************************************/ +DPP_STATUS dpp_etcam_block_tbl_id_get(DPP_DEV_T *dev, + ZXIC_UINT32 block_idx, + ZXIC_UINT32 *p_tbl_id) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 reg_offset = 0; + ZXIC_UINT32 bit_offset = 0; + ZXIC_UINT32 *p_temp = 0; + DPP_STAT4K_ETCAM_BLOCK0_7_PORT_ID_CFG_T block_tbl_id = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), block_idx, 0, DPP_ETCAM_BLOCK_NUM - 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_tbl_id); + + reg_offset = block_idx / TBLID_CFG_SETP; + bit_offset = block_idx % TBLID_CFG_SETP; + + rc = dpp_reg_read(dev, + STAT4K_ETCAM_BLOCK0_7_PORT_ID_CFGr + reg_offset, + 0, + 0, + &block_tbl_id); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + + p_temp = (ZXIC_UINT32 *)(&block_tbl_id) + TBLID_CFG_SETP - 1 - bit_offset; + + *p_tbl_id = *p_temp; + + return DPP_OK; +} + + +/***********************************************************/ +/** 配置block的基地址。 +* @param dev_id 设备号 +* @param block_idx block编号 +* @param base_addr 基地址。 +* 配置规则:每个寄存器寄存器位宽是7bit，逻辑实现为{base_addr[6:0],9'b0}, +* 80 bit键值模式下，base_addr格式遵循{base_addr[6,3],3'0} +* 160bit键值模式下，base_addr格式遵循{1'b0,base_addr[5,2],2'0} +* 320bit键值模式下，base_addr格式遵循{2'b0,base_addr[4,1],1'0} +* 640bit键值模式下，base_addr格式遵循{3'b0,base_addr[3,0]} +* @return +* @remark 无 +* @see 共有8组配置寄存器，每组寄存器支持两组block基地址的配置 +* 其中第0组支持0和1号block基地址配置，第1组支持1和2号block基地址配置 ，依次类推 +* @author 王春雷 @date 2014/04/08 +************************************************************/ +DPP_STATUS dpp_etcam_block_baddr_set(DPP_DEV_T *dev, + ZXIC_UINT32 block_idx, + ZXIC_UINT32 base_addr) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 reg_offset = 0; + ZXIC_UINT32 bit_offset = 0; + ZXIC_UINT32 *p_temp = 0; + DPP_STAT4K_ETCAM_BLOCK0_3_BASE_ADDR_CFG_T block_baddr = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), block_idx, 0, DPP_ETCAM_BLOCK_NUM - 1); + + reg_offset = block_idx / BADDR_CFG_SETP; + bit_offset = block_idx % BADDR_CFG_SETP; + + rc = dpp_reg_read(dev, + STAT4K_ETCAM_BLOCK0_3_BASE_ADDR_CFGr + reg_offset, + 0, + 0, + &block_baddr); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + + p_temp = (ZXIC_UINT32 *)(&block_baddr) + 3 - bit_offset; + + *p_temp = base_addr; + + rc = dpp_reg_write(dev, + STAT4K_ETCAM_BLOCK0_3_BASE_ADDR_CFGr + reg_offset, + 0, + 0, + &block_baddr); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write"); + + return DPP_OK; +} + +/***********************************************************/ +/** 获取block的基地址 +* @param dev_id +* @param block_idx +* @param p_base_addr +* +* @return +* @remark 无 +* @see +* @author 王春雷 @date 2014/04/08 +************************************************************/ +DPP_STATUS dpp_etcam_block_baddr_get(DPP_DEV_T *dev, + ZXIC_UINT32 block_idx, + ZXIC_UINT32 *p_base_addr) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 reg_offset = 0; + ZXIC_UINT32 bit_offset = 0; + ZXIC_UINT32 *p_temp = 0; + DPP_STAT4K_ETCAM_BLOCK0_3_BASE_ADDR_CFG_T block_baddr = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), block_idx, 0, DPP_ETCAM_BLOCK_NUM - 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_base_addr); + + reg_offset = block_idx / BADDR_CFG_SETP; + bit_offset = block_idx % BADDR_CFG_SETP; + + rc = dpp_reg_read(dev, + STAT4K_ETCAM_BLOCK0_3_BASE_ADDR_CFGr + reg_offset, + 0, + 0, + &block_baddr); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + + p_temp = (ZXIC_UINT32 *)&block_baddr + BADDR_CFG_SETP - 1 - bit_offset; + + *p_base_addr = *p_temp; + + return DPP_OK; +} + +#endif \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se/dpp_se.c b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se/dpp_se.c new file mode 100755 index 0000000..2dc9dd6 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se/dpp_se.c @@ -0,0 +1,1084 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_se.c +* 文件标识 : +* 内容摘要 : 芯片se模块基本接口函数实现 +* 其它说明 : +* 当前版本 : +* 作 者 : 王春雷 +* 完成日期 : 2014/03/11 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ + +#include "zxic_common.h" +#include "dpp_type_api.h" +#include "dpp_reg.h" +#include "dpp_se_api.h" +#include "dpp_etcam.h" +#include "dpp_se.h" +#include "dpp_dev.h" +#include "dpp_se_cfg.h" +#include "dpp_sdt.h" +#include "dpp_smmu14k_reg.h" +#include "dpp_se4k_reg.h" + +#define SE_OPR_WR (0) +#define SE_OPR_RD (1) +#define SE_CLS_MAX (8) +#define SE_SMMU1_PAGE_MAX (5) +#define SE_LPMID_OFF (4) + +static SMMU1_KSCHD_HASH_DDR_CFG_T g_smmu1_kschd_hash[DPP_DEV_CHANNEL_MAX][DPP_HASH_ID_NUM][HASH_BULK_NUM] = {{{{0}}}}; + +ZXIC_UINT32 g_lpm_dat_wr_type_flag = 2; /* 1:开启DMA 2:REG mode */ +ZXIC_UINT8 g_lpm_hw_dat_buf[LPM_HW_DAT_BUFF_SIZE_MAX] = {0}; +ZXIC_UINT32 g_lpm_hw_dat_offset = 0; + +#define GET_SMMU1_KSCHD_HASH_CFG(dev_id,hash_id,bulk_id) (&g_smmu1_kschd_hash[dev_id][hash_id][bulk_id]) + +#define SMMU1_WDAT0_R (SYS_SE_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0) +#define SMMU1_CMD0_R (SYS_SE_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x40) +#define SMMU1_CMD1_R (SYS_SE_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x44) +#define SMMU1_CMD0_F_ADDR_START (30) +#define SMMU1_CMD0_F_ADDR_WIDTH (2) +#define SMMU1_CMD0_F_ECC_EN_START (5) +#define SMMU1_CMD0_F_ECC_EN_WIDTH (1) +#define SMMU1_CMD0_F_DDR_MODE_START (3) +#define SMMU1_CMD0_F_DDR_MODE_WIDTH (2) +#define SMMU1_CMD0_F_BK_INFO_START (0) +#define SMMU1_CMD0_F_BK_INFO_WIDTH (3) + +#define SMMU1_CMD1_F_DDR_WR_START (30) +#define SMMU1_CMD1_F_DDR_WR_WIDTH (1) +#define SMMU1_CMD1_F_ADDR_START (0) +#define SMMU1_CMD1_F_ADDR_WIDTH (30) + + +#if ZXIC_REAL("SMMU0") +/***********************************************************/ +/** SE通用完成状态检查 +* @param dev_id 设备号 +* @param reg_no 寄存器编号 +* @param pos 所要读的寄存器的done_flag的位置(只支持1bit) +* +* @return +* @remark 无 +* @see +* @author wyt @date 2018/07/09 +************************************************************/ +DPP_STATUS dpp_se_done_status_check(DPP_DEV_T *dev, ZXIC_UINT32 reg_no, ZXIC_UINT32 pos) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_UINT32 data = 0; + ZXIC_UINT32 rd_cnt = 0; + ZXIC_UINT32 done_flag = 0; + + /* 打桩使用 */ +#ifdef DPP_FOR_LLT + ZXIC_UINT32 done_sig = 0xffffffff; + + rc = dpp_reg_write32(dev_id, reg_no, done_sig); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_reg_write32"); +#endif + + ZXIC_COMM_CHECK_POINT(dev); + + ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev), DPP_DEV_CHANNEL_MAX - 1); + + while (!done_flag) + { + rc = dpp_reg_read32(dev, reg_no, 0, 0, &data); + if(ZXIC_OK != rc) + { + ZXIC_COMM_TRACE_ERROR("\n [ErrorCode:0x%x] !-- dpp_reg_read32 Fail!\n", rc); + return rc; + } + + done_flag = (data >> pos) & 0x1; + + if (done_flag) + { + break; + } + + if (rd_cnt > DPP_RD_CNT_MAX * DPP_RD_CNT_MAX) + { + ZXIC_COMM_TRACE_ERROR("Error!!! dpp se rd reg_no [%d] is overtime!\n", reg_no); + return DPP_ERR; + } + + rd_cnt++; + /*zxic_comm_usleep(1000);*/ + } + + return rc; +} + +/***********************************************************/ +/** 读eRam +* @param dev_id 设备号 +* @param base_addr 基地址，以128bit为单位 +* @param index 条目索引,支持128、64、32和1bit的索引值 +* @param rd_mode 读eRam模式, 取值参照ERAM128_OPR_MODE_E定义，读清模式下不支持1bit模式 +* @param rd_clr_mode eRam读清模式, 取值参照ERAM128_RD_CLR_MODE_E定义 +* @param p_data 返回数据缓存的指针 +* +* @return +* @remark 无 +* @see +* @author wcl @date 2015/01/30 +************************************************************/ +DPP_STATUS dpp_se_smmu0_ind_read(DPP_DEV_T *dev, + ZXIC_UINT32 base_addr, + ZXIC_UINT32 index, + ZXIC_UINT32 rd_mode, + ZXIC_UINT32 rd_clr_mode, + ZXIC_UINT32 *p_data) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_UINT32 i = 0; + ZXIC_UINT32 row_index = 0; + ZXIC_UINT32 col_index = 0; + ZXIC_UINT32 temp_data[4] = {0}; + ZXIC_UINT32 *p_temp_data = NULL; + + DPP_SMMU0_SMMU0_CPU_IND_CMD_T cpu_ind_cmd = {0}; + + ZXIC_MUTEX_T *p_ind_mutex = NULL; + + ZXIC_COMM_CHECK_POINT(dev); + + ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev),DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), rd_clr_mode, RD_MODE_HOLD, RD_MODE_CLEAR); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), rd_mode, ERAM128_OPR_128b, ERAM128_OPR_32b); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), base_addr, 0, SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1); + + rc = dpp_dev_opr_mutex_get(DEV_ID(dev), DPP_DEV_MUTEX_T_SMMU0, &p_ind_mutex); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dev_opr_mutex_get"); + + rc = zxic_comm_mutex_lock(p_ind_mutex); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "zxic_comm_mutex_lock"); + + rc = dpp_se_done_status_check(dev, SMMU0_SMMU0_WR_ARB_CPU_RDYr, 0); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "time_out", p_ind_mutex); + + /** 正常模式读数据，仅能以128bit读出数据，软件提取数据*/ + if (RD_MODE_HOLD == rd_clr_mode) + { + cpu_ind_cmd.cpu_ind_rw = SE_OPR_RD; + cpu_ind_cmd.cpu_ind_rd_mode = RD_MODE_HOLD; + cpu_ind_cmd.cpu_req_mode = ERAM128_OPR_128b; + + /* 先以128bit模式读出数据 */ + switch (rd_mode) + { + case ERAM128_OPR_128b: + { + if((0xFFFFFFFF - (base_addr)) < (index)) + { + zxic_comm_mutex_unlock(p_ind_mutex); + ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "ICM %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, base_addr, index, __FUNCTION__); + return ZXIC_PAR_CHK_INVALID_INDEX; + } + if (base_addr + index > SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) + { + ZXIC_COMM_PRINT("dpp_se_smmu0_ind_read : index out of range !\n"); + zxic_comm_mutex_unlock(p_ind_mutex); + return DPP_ERR; + } + + row_index = (index << 7) & DPP_ERAM128_BADDR_MASK; + break; + } + + case ERAM128_OPR_64b: + { + if ((base_addr + (index >> 1)) > SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) + { + ZXIC_COMM_PRINT("dpp_se_smmu0_ind_read : index out of range !\n"); + zxic_comm_mutex_unlock(p_ind_mutex); + return DPP_ERR; + } + + row_index = (index << 6) & DPP_ERAM128_BADDR_MASK; + col_index = index & 0x1; + break; + } + + case ERAM128_OPR_32b: + { + if ((base_addr + (index >> 2)) > SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) + { + ZXIC_COMM_PRINT("dpp_se_smmu0_ind_read : index out of range !\n"); + zxic_comm_mutex_unlock(p_ind_mutex); + return DPP_ERR; + } + + row_index = (index << 5) & DPP_ERAM128_BADDR_MASK; + col_index = index & 0x3; + break; + } + + case ERAM128_OPR_1b: + { + if ((base_addr + (index >> 7)) > SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) + { + ZXIC_COMM_PRINT("dpp_se_smmu0_ind_read : index out of range !\n"); + zxic_comm_mutex_unlock(p_ind_mutex); + return DPP_ERR; + } + + row_index = index & DPP_ERAM128_BADDR_MASK; + col_index = index & 0x7F; + break; + } + } + + cpu_ind_cmd.cpu_ind_addr = ((base_addr << 7) & DPP_ERAM128_BADDR_MASK) + row_index; + } + /** 读清模式*/ + else + { + cpu_ind_cmd.cpu_ind_rw = SE_OPR_RD; + cpu_ind_cmd.cpu_ind_rd_mode = RD_MODE_CLEAR; + + switch (rd_mode) + { + case ERAM128_OPR_128b: + { + if((0xFFFFFFFF - (base_addr)) < (index)) + { + ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "ICM %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, base_addr, index, __FUNCTION__); + zxic_comm_mutex_unlock(p_ind_mutex); + return ZXIC_PAR_CHK_INVALID_INDEX; + } + if (base_addr + index > SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) + { + ZXIC_COMM_PRINT("dpp_se_smmu0_ind_read : index out of range !\n"); + zxic_comm_mutex_unlock(p_ind_mutex); + return DPP_ERR; + } + + row_index = (index << 7); + cpu_ind_cmd.cpu_req_mode = ERAM128_OPR_128b; + break; + } + + case ERAM128_OPR_64b: + { + if ((base_addr + (index >> 1)) > SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) + { + ZXIC_COMM_PRINT("dpp_se_smmu0_ind_read : index out of range !\n"); + zxic_comm_mutex_unlock(p_ind_mutex); + return DPP_ERR; + } + + row_index = (index << 6); + cpu_ind_cmd.cpu_req_mode = 2; + break; + } + + case ERAM128_OPR_32b: + { + if ((base_addr + (index >> 2)) > SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) + { + ZXIC_COMM_PRINT("dpp_se_smmu0_ind_read : index out of range !\n"); + zxic_comm_mutex_unlock(p_ind_mutex); + return DPP_ERR; + } + + row_index = (index << 5); + cpu_ind_cmd.cpu_req_mode = 1; + break; + } + + /** 1bit读清模式硬件不支持 */ + case ERAM128_OPR_1b: + { + ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "Param Error! rd_clr_mode[%d] or rd_mode[%d] error!\n ", rd_clr_mode, rd_mode); + zxic_comm_mutex_unlock(p_ind_mutex); + ZXIC_COMM_ASSERT(0); + return DPP_ERR; + } + } + + cpu_ind_cmd.cpu_ind_addr = ((base_addr << 7) & DPP_ERAM128_BADDR_MASK) + row_index; + } + + rc = dpp_reg_write(dev, + SMMU0_SMMU0_CPU_IND_CMDr, + 0, + 0, + &cpu_ind_cmd); + ZXIC_COMM_CHECK_DEV_RC_UNLOCK(DEV_ID(dev), rc, "dpp_reg_write", p_ind_mutex); + + rc = dpp_se_done_status_check(dev, SMMU0_SMMU0_CPU_IND_RD_DONEr, 0); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "time_out", p_ind_mutex); + + p_temp_data = temp_data; + for (i = 0; i < 4; i++) + { +/* + rc = dpp_reg_read(dev_id, + SMMU0_SMMU0_CPU_IND_RDAT0r + i, + 0, + 0, + temp_data + 3 - i); + ZXIC_COMM_CHECK_DEV_RC_UNLOCK(dev_id, rc, "dpp_reg_read", p_ind_mutex); +*/ + rc = dpp_reg_read(dev, + SMMU0_SMMU0_CPU_IND_RDAT0r + i, + 0, + 0, + p_temp_data + 3 - i); + ZXIC_COMM_CHECK_DEV_RC_UNLOCK(DEV_ID(dev), rc, "dpp_reg_read", p_ind_mutex); + } + + /** 正常模式读数据，仅能以128bit读出数据，软件提取数据*/ + if (RD_MODE_HOLD == rd_clr_mode) + { + switch (rd_mode) + { + case ERAM128_OPR_128b: + { + /* ZXIC_COMM_MEMCPY(p_data, &temp_data[0], (128 / 8)); */ + /* modify by ghm for coverity @20200714 */ + ZXIC_COMM_MEMCPY(p_data, p_temp_data, (128 / 8)); + break; + } + + case ERAM128_OPR_64b: + { + /* ZXIC_COMM_MEMCPY(p_data, &temp_data[(1 - col_index) << 1], (64 / 8)); */ + /* modify by ghm for coverity @20200714 */ + ZXIC_COMM_MEMCPY(p_data, p_temp_data + ((1 - col_index) << 1), (64 / 8)); + break; + } + + case ERAM128_OPR_32b: + { + /* ZXIC_COMM_MEMCPY(p_data, &temp_data[(3 - col_index)], (32 / 8)); */ + /* modify by ghm for coverity @20200714 */ + ZXIC_COMM_MEMCPY(p_data, p_temp_data + ((3 - col_index)), (32 / 8)); + break; + } + + case ERAM128_OPR_1b: + { + /* ZXIC_COMM_UINT32_GET_BITS(p_data[0], temp_data[3 - col_index / 32], (col_index % 32), 1); */ + /* modify by ghm for coverity @20200714 */ + ZXIC_COMM_UINT32_GET_BITS(p_data[0], *(p_temp_data + (3 - col_index / 32)), (col_index % 32), 1); + break; + } + } + } + else /** 读清模式*/ + { + switch (rd_mode) + { + case ERAM128_OPR_128b: + { + /* ZXIC_COMM_MEMCPY(p_data, temp_data, (128 / 8)); */ + /* modify by ghm for coverity @20200714 */ + ZXIC_COMM_MEMCPY(p_data, p_temp_data, (128 / 8)); + break; + } + + case ERAM128_OPR_64b: + { + /* ZXIC_COMM_MEMCPY(p_data, temp_data, (64 / 8)); */ + /* modify by ghm for coverity @20200714 */ + ZXIC_COMM_MEMCPY(p_data, p_temp_data, (64 / 8)); + break; + } + + case ERAM128_OPR_32b: + { + /* ZXIC_COMM_MEMCPY(p_data, temp_data, (32 / 8)); */ + /* modify by ghm for coverity @20200714 */ + ZXIC_COMM_MEMCPY(p_data, p_temp_data, (64 / 8)); + break; + } + } + } + + rc = zxic_comm_mutex_unlock(p_ind_mutex); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "zxic_comm_mutex_unlock"); + + return rc; +} + + + +#endif + +#if ZXIC_REAL("SMMU1") +/***********************************************************/ +/** dpp hash的smmu1属性设置 +* @param dev_id 设备号 +* @param hash_id hash引擎号 +* @param tbl_id hash表号 +* @param ecc_en ecc使能 +* @param baddr ddr基地址 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/04/12 +************************************************************/ +DPP_STATUS dpp_se_smmu1_hash_tbl_cfg_set(DPP_DEV_T *dev, + ZXIC_UINT32 hash_id, + ZXIC_UINT32 tbl_id, + ZXIC_UINT32 ecc_en, + ZXIC_UINT32 baddr) +{ + DPP_STATUS rc = DPP_OK; + + DPP_SMMU14K_SE_SMMU1_HASH0_TBL0_CFG_T hash_tbl_cfg = {0}; + + SMMU1_KSCHD_HASH_DDR_CFG_T *p_hash_ddr_cfg = NULL; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev),DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_INDEX_UPPER(hash_id,DPP_HASH_ID_MAX); + ZXIC_COMM_CHECK_INDEX_UPPER(tbl_id,HASH_BULK_ID_MAX); + ZXIC_COMM_CHECK_INDEX_UPPER(ecc_en,1); + ZXIC_COMM_CHECK_INDEX_UPPER(baddr,DPP_SE_SMMU1_MAX_BADDR_NO_SHARE); + + /* save to soft buffer */ + p_hash_ddr_cfg = GET_SMMU1_KSCHD_HASH_CFG(DEV_ID(dev), hash_id, tbl_id); + p_hash_ddr_cfg->baddr = baddr; + p_hash_ddr_cfg->crcen = ecc_en; + p_hash_ddr_cfg->mode = SMMU1_DDR_SRH_256b; /* alg search ddr mode, not write mode */ + + hash_tbl_cfg.hash0_tbl0_ecc_en = ecc_en; + hash_tbl_cfg.hash0_tbl0_baddr = baddr; + +#ifdef DPP_FLOW_HW_INIT + rc = dpp_reg_write(dev, + SMMU14K_SE_SMMU1_HASH0_TBL0_CFGr + hash_id * HASH_BULK_NUM + tbl_id, + 0, + 0, + &hash_tbl_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write"); +#endif + + return rc; +} + +/***********************************************************/ +/** 获取hash算法访问DDR空间的属性，从软件获取(待优化) +* @param dev_id 设备号 +* @param hash_id hash引擎号 +* @param bulk_id Hash引擎存储资源划分块数的ID号 +* @param p_ecc_en 使能ECC校验 +* @param p_base_addr DDR空间基地址 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author tf @date 2016/06/15 +************************************************************/ +DPP_STATUS dpp_se_smmu1_hash_tbl_soft_cfg_get(DPP_DEV_T *dev, + ZXIC_UINT32 hash_id, + ZXIC_UINT32 bulk_id, + ZXIC_UINT32 *p_ecc_en, + ZXIC_UINT32 *p_base_addr) +{ + + SMMU1_KSCHD_HASH_DDR_CFG_T *p_schd_hash = NULL; + + ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev),DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_INDEX_UPPER(hash_id,DPP_HASH_ID_MAX); + ZXIC_COMM_CHECK_INDEX_UPPER(bulk_id,HASH_BULK_ID_MAX); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_base_addr); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_ecc_en); + + /* read from soft buffer */ + p_schd_hash = GET_SMMU1_KSCHD_HASH_CFG(DEV_ID(dev), hash_id, bulk_id); + *p_base_addr = p_schd_hash->baddr; + *p_ecc_en = p_schd_hash->crcen; + + return DPP_OK; +} + +#endif + +#if ZXIC_REAL("ALG") +/***********************************************************/ +/** 设置zblock service信息 +* @param dev_id +* @param zblk_idx zblock索引(2bit zgroup + 3bit zblock) +* @param serv_sel 0-lpm, 1-hash +* @param hash_id zblock对应的hash_id, lpm不关心此字段 +* @param enable 业务表使能标志 +* +* @return +* @remark 无 +* @see +* @author 王春雷 @date 2014/07/26 +************************************************************/ +DPP_STATUS dpp_se_zblk_serv_cfg_set(DPP_DEV_T *dev, + ZXIC_UINT32 zblk_idx, + ZXIC_UINT32 serv_sel, + ZXIC_UINT32 hash_id, + ZXIC_UINT32 enable) +{ + DPP_STATUS rtn = DPP_OK; + + DPP_SE4K_SE_ALG_ZBLOCK_SERVICE_CONFIGURE_T zblk_cfg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev),DPP_DEV_CHANNEL_MAX - 1); + + zblk_cfg.hash_channel_sel = hash_id; + zblk_cfg.service_sel = serv_sel; + zblk_cfg.st_en = enable; + rtn = dpp_reg_write(dev, + SE4K_SE_ALG_ZBLOCK_SERVICE_CONFIGUREr, + ((ZBLK_ADDR_CONV(zblk_idx) >> 3) & 0x3), + (ZBLK_ADDR_CONV(zblk_idx) & 0x7), + &zblk_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_write"); + + return DPP_OK; +} + +/***********************************************************/ +/** 设置业务表独占的zcell +* @param dev_id +* @param zblk_idx zblock索引(2bit zgroup + 3bit zblock) +* @param zcell0_bulk_id 独占zcell0的业务表号 +* @param zcell0_mono_flag zcell0被独占的标志 +* @param zcell1_bulk_id 独占zcell1的业务表号 +* @param zcell1_mono_flag zcell1被独占的标志 +* @param zcell2_bulk_id 独占zcell2的业务表号 +* @param zcell2_mono_flag zcell2被独占的标志 +* @param zcell3_bulk_id 独占zcell3的业务表号 +* @param zcell3_mono_flag zcell3被独占的标志 +* +* @return +* @remark 无 +* @see +* @author tf @date 2016/04/26 +************************************************************/ +DPP_STATUS dpp_se_zcell_mono_cfg_set(DPP_DEV_T *dev, + ZXIC_UINT32 zblk_idx, + ZXIC_UINT32 zcell0_bulk_id, + ZXIC_UINT32 zcell0_mono_flag, + ZXIC_UINT32 zcell1_bulk_id, + ZXIC_UINT32 zcell1_mono_flag, + ZXIC_UINT32 zcell2_bulk_id, + ZXIC_UINT32 zcell2_mono_flag, + ZXIC_UINT32 zcell3_bulk_id, + ZXIC_UINT32 zcell3_mono_flag) +{ + DPP_STATUS rtn = DPP_OK; + + DPP_SE4K_SE_ALG_ZBLOCK_HASH_ZCELL_MONO_T zblk_zcell_mono_cfg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev),DPP_DEV_CHANNEL_MAX - 1); + + zblk_zcell_mono_cfg.ha_zcell0_tbl_id = zcell0_bulk_id; + zblk_zcell_mono_cfg.ha_zcell0_mono_flag = zcell0_mono_flag; + zblk_zcell_mono_cfg.ha_zcell1_tbl_id = zcell1_bulk_id; + zblk_zcell_mono_cfg.ha_zcell1_mono_flag = zcell1_mono_flag; + zblk_zcell_mono_cfg.ha_zcell2_tbl_id = zcell2_bulk_id; + zblk_zcell_mono_cfg.ha_zcell2_mono_flag = zcell2_mono_flag; + zblk_zcell_mono_cfg.ha_zcell3_tbl_id = zcell3_bulk_id; + zblk_zcell_mono_cfg.ha_zcell3_mono_flag = zcell3_mono_flag; + + rtn = dpp_reg_write(dev, + SE4K_SE_ALG_ZBLOCK_HASH_ZCELL_MONOr, + ((ZBLK_ADDR_CONV(zblk_idx) >> 3) & 0x3), + (ZBLK_ADDR_CONV(zblk_idx) & 0x7), + &zblk_zcell_mono_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_write"); + + return DPP_OK; +} + +/***********************************************************/ +/** 获取业务表独占的zcell +* @param dev_id +* @param zblk_idx +* @param *zcell0_bulk_id +* @param *zcell0_mono_flag +* @param *zcell1_bulk_id +* @param *zcell1_mono_flag +* @param *zcell2_bulk_id +* @param *zcell2_mono_flag +* @param *zcell3_bulk_id +* @param *zcell3_mono_flag +* +* @return +* @remark 无 +* @see +* @author tf @date 2016/04/26 +************************************************************/ +DPP_STATUS dpp_se_zcell_mono_cfg_get(DPP_DEV_T *dev, + ZXIC_UINT32 zblk_idx, + ZXIC_UINT32 *zcell0_bulk_id, + ZXIC_UINT32 *zcell0_mono_flag, + ZXIC_UINT32 *zcell1_bulk_id, + ZXIC_UINT32 *zcell1_mono_flag, + ZXIC_UINT32 *zcell2_bulk_id, + ZXIC_UINT32 *zcell2_mono_flag, + ZXIC_UINT32 *zcell3_bulk_id, + ZXIC_UINT32 *zcell3_mono_flag) +{ + DPP_STATUS rtn = DPP_OK; + + DPP_SE4K_SE_ALG_ZBLOCK_HASH_ZCELL_MONO_T zblk_zcell_mono_cfg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev),DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), zcell0_bulk_id); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), zcell0_mono_flag); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), zcell1_bulk_id); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), zcell1_mono_flag); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), zcell2_bulk_id); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), zcell2_mono_flag); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), zcell3_bulk_id); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), zcell3_mono_flag); + + rtn = dpp_reg_read(dev, + SE4K_SE_ALG_ZBLOCK_HASH_ZCELL_MONOr, + ((ZBLK_ADDR_CONV(zblk_idx) >> 3) & 0x3), + (ZBLK_ADDR_CONV(zblk_idx) & 0x7), + &zblk_zcell_mono_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_write"); + + *zcell0_bulk_id = zblk_zcell_mono_cfg.ha_zcell0_tbl_id; + *zcell0_mono_flag = zblk_zcell_mono_cfg.ha_zcell0_mono_flag; + *zcell1_bulk_id = zblk_zcell_mono_cfg.ha_zcell1_tbl_id; + *zcell1_mono_flag = zblk_zcell_mono_cfg.ha_zcell1_mono_flag; + *zcell2_bulk_id = zblk_zcell_mono_cfg.ha_zcell2_tbl_id; + *zcell2_mono_flag = zblk_zcell_mono_cfg.ha_zcell2_mono_flag; + *zcell3_bulk_id = zblk_zcell_mono_cfg.ha_zcell3_tbl_id; + *zcell3_mono_flag = zblk_zcell_mono_cfg.ha_zcell3_mono_flag; + + return DPP_OK; +} + +/***********************************************************/ +/** 设置业务表独占的zreg +* @param dev_id +* @param zblk_idx zblock索引(2bit zgroup + 3bit zblock) +* @param zreg0_bulk_id 独占zreg0的业务表号 +* @param zreg0_mono_flag zreg0被独占的标志 +* @param zreg1_bulk_id 独占zreg1的业务表号 +* @param zreg1_mono_flag zreg1被独占的标志 +* @param zreg2_bulk_id 独占zreg2的业务表号 +* @param zreg2_mono_flag zreg2被独占的标志 +* @param zreg3_bulk_id 独占zreg3的业务表号 +* @param zreg3_mono_flag zreg3被独占的标志 +* +* @return +* @remark 无 +* @see +* @author tf @date 2016/04/27 +************************************************************/ +DPP_STATUS dpp_se_zreg_mono_cfg_set(DPP_DEV_T *dev, + ZXIC_UINT32 zblk_idx, + ZXIC_UINT32 zreg0_bulk_id, + ZXIC_UINT32 zreg0_mono_flag, + ZXIC_UINT32 zreg1_bulk_id, + ZXIC_UINT32 zreg1_mono_flag, + ZXIC_UINT32 zreg2_bulk_id, + ZXIC_UINT32 zreg2_mono_flag, + ZXIC_UINT32 zreg3_bulk_id, + ZXIC_UINT32 zreg3_mono_flag) +{ + DPP_STATUS rtn = DPP_OK; + + DPP_SE4K_SE_ALG_ZLOCK_HASH_ZREG_MONO_T zblk_zreg_mono_cfg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev),DPP_DEV_CHANNEL_MAX - 1); + + zblk_zreg_mono_cfg.ha_zreg0_tbl_id = zreg0_bulk_id; + zblk_zreg_mono_cfg.ha_zreg0_mono_flag = zreg0_mono_flag; + zblk_zreg_mono_cfg.ha_zreg1_tbl_id = zreg1_bulk_id; + zblk_zreg_mono_cfg.ha_zreg1_mono_flag = zreg1_mono_flag; + zblk_zreg_mono_cfg.ha_zreg2_tbl_id = zreg2_bulk_id; + zblk_zreg_mono_cfg.ha_zreg2_mono_flag = zreg2_mono_flag; + zblk_zreg_mono_cfg.ha_zreg3_tbl_id = zreg3_bulk_id; + zblk_zreg_mono_cfg.ha_zreg3_mono_flag = zreg3_mono_flag; + + rtn = dpp_reg_write(dev, + SE4K_SE_ALG_ZLOCK_HASH_ZREG_MONOr, + ((ZBLK_ADDR_CONV(zblk_idx) >> 3) & 0x3), + (ZBLK_ADDR_CONV(zblk_idx) & 0x7), + &zblk_zreg_mono_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_write"); + + return DPP_OK; +} + +/***********************************************************/ +/** 获取业务表独占的zcell +* @param dev_id +* @param zblk_idx +* @param *zreg0_bulk_id +* @param *zreg0_mono_flag +* @param *zreg1_bulk_id +* @param *zreg1_mono_flag +* @param *zreg2_bulk_id +* @param *zreg2_mono_flag +* @param *zreg3_bulk_id +* @param *zreg3_mono_flag +* +* @return +* @remark 无 +* @see +* @author tf @date 2016/04/27 +************************************************************/ +DPP_STATUS dpp_se_zreg_mono_cfg_get(DPP_DEV_T *dev, + ZXIC_UINT32 zblk_idx, + ZXIC_UINT32 *zreg0_bulk_id, + ZXIC_UINT32 *zreg0_mono_flag, + ZXIC_UINT32 *zreg1_bulk_id, + ZXIC_UINT32 *zreg1_mono_flag, + ZXIC_UINT32 *zreg2_bulk_id, + ZXIC_UINT32 *zreg2_mono_flag, + ZXIC_UINT32 *zreg3_bulk_id, + ZXIC_UINT32 *zreg3_mono_flag) +{ + DPP_STATUS rtn = DPP_OK; + + DPP_SE4K_SE_ALG_ZLOCK_HASH_ZREG_MONO_T zblk_zreg_mono_cfg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev),DPP_DEV_CHANNEL_MAX - 1); + + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), zreg0_bulk_id); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), zreg0_mono_flag); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), zreg1_bulk_id); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), zreg1_mono_flag); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), zreg2_bulk_id); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), zreg2_mono_flag); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), zreg3_bulk_id); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), zreg3_mono_flag); + + rtn = dpp_reg_read(dev, + SE4K_SE_ALG_ZLOCK_HASH_ZREG_MONOr, + ((ZBLK_ADDR_CONV(zblk_idx) >> 3) & 0x3), + (ZBLK_ADDR_CONV(zblk_idx) & 0x7), + &zblk_zreg_mono_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_write"); + + *zreg0_bulk_id = zblk_zreg_mono_cfg.ha_zreg0_tbl_id; + *zreg0_mono_flag = zblk_zreg_mono_cfg.ha_zreg0_mono_flag; + *zreg1_bulk_id = zblk_zreg_mono_cfg.ha_zreg1_tbl_id; + *zreg1_mono_flag = zblk_zreg_mono_cfg.ha_zreg1_mono_flag; + *zreg2_bulk_id = zblk_zreg_mono_cfg.ha_zreg2_tbl_id; + *zreg2_mono_flag = zblk_zreg_mono_cfg.ha_zreg2_mono_flag; + *zreg3_bulk_id = zblk_zreg_mono_cfg.ha_zreg3_tbl_id; + *zreg3_mono_flag = zblk_zreg_mono_cfg.ha_zreg3_mono_flag; + + return DPP_OK; +} + +/***********************************************************/ +/** 设置hash访问片外DDR的属性 +* @param dev_id +* @param hash0_mono_flag +* @param hash1_mono_flag +* @param hash2_mono_flag +* @param hash3_mono_flag +* +* @return +* @remark 无 +* @see +* @author tf @date 2016/05/7 +************************************************************/ +DPP_STATUS dpp_se_hash_zcam_mono_flags_set(DPP_DEV_T *dev, + ZXIC_UINT32 hash0_mono_flag, + ZXIC_UINT32 hash1_mono_flag, + ZXIC_UINT32 hash2_mono_flag, + ZXIC_UINT32 hash3_mono_flag) +{ + DPP_STATUS rtn = DPP_OK; + + DPP_SE4K_SE_ALG_HASH_MONO_FLAG_T hash_mono_flag = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev),DPP_DEV_CHANNEL_MAX - 1); + + hash_mono_flag.hash0_mono_flag = hash0_mono_flag; + hash_mono_flag.hash1_mono_flag = hash1_mono_flag; + hash_mono_flag.hash2_mono_flag = hash2_mono_flag; + hash_mono_flag.hash3_mono_flag = hash3_mono_flag; + + rtn = dpp_reg_write(dev, + SE4K_SE_ALG_HASH_MONO_FLAGr, + 0, + 0, + &hash_mono_flag); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_write"); + + return DPP_OK; +} + +/***********************************************************/ +/** 设置hash访问片外DDR的属性 +* @param dev_id +* @param hash0_mono_flag +* @param hash1_mono_flag +* @param hash2_mono_flag +* @param hash3_mono_flag +* +* @return +* @remark 无 +* @see +* @author tf @date 2016/05/7 +************************************************************/ +DPP_STATUS dpp_se_hash_zcam_mono_flags_get(DPP_DEV_T *dev, + ZXIC_UINT32 *hash0_mono_flag, + ZXIC_UINT32 *hash1_mono_flag, + ZXIC_UINT32 *hash2_mono_flag, + ZXIC_UINT32 *hash3_mono_flag) +{ + DPP_STATUS rtn = DPP_OK; + + DPP_SE4K_SE_ALG_HASH_MONO_FLAG_T hash_mono_flag = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev),DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), hash0_mono_flag); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), hash1_mono_flag); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), hash2_mono_flag); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), hash3_mono_flag); + + rtn = dpp_reg_read(dev, + SE4K_SE_ALG_HASH_MONO_FLAGr, + 0, + 0, + &hash_mono_flag); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_write"); + + *hash0_mono_flag = hash_mono_flag.hash0_mono_flag; + *hash1_mono_flag = hash_mono_flag.hash1_mono_flag; + *hash2_mono_flag = hash_mono_flag.hash2_mono_flag; + *hash3_mono_flag = hash_mono_flag.hash3_mono_flag; + + return DPP_OK; +} + +/***********************************************************/ +/** 设置hash访问片外DDR的属性 +* @param dev_id +* @param hash_id +* @param ext_mode +* @param flag +* +* @return +* @remark 无 +* @see +* @author wcl @date 2014/07/26 +************************************************************/ +DPP_STATUS dpp_se_hash_ext_cfg_set(DPP_DEV_T *dev, + ZXIC_UINT32 hash_id, + ZXIC_UINT32 ext_mode, + ZXIC_UINT32 flag) +{ + DPP_STATUS rtn = DPP_OK; + + DPP_SE4K_SE_ALG_HASH0_EXT_CFG_RGT_T hash_ext_cfg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev),DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_INDEX_UPPER(hash_id,DPP_HASH_ID_MAX); + + hash_ext_cfg.hash0_ext_flag = flag; + hash_ext_cfg.hash0_ext_mode = ext_mode; + + rtn = dpp_reg_write(dev, + SE4K_SE_ALG_HASH0_EXT_CFG_RGTr + hash_id, + 0, + 0, + &hash_ext_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_write"); + + return DPP_OK; +} + +/***********************************************************/ +/** 获取hash访问片外DDR的属性 +* @param dev_id 设备号 +* @param hash_id hash引擎，范围0~3 +* @param p_content_type 每个hash表项读一次ddr3还是两次；1-读512b的宽度，读两次 0-读256宽度，读一次 +* @param p_flag 片外ddr3是否存储hash表，1-片外存储hash表 0-片外不存储hash表 +* +* @return +* @remark 无 +* @see +* @author 王春雷 @date 2014/07/26 +************************************************************/ +DPP_STATUS dpp_se_hash_ext_cfg_get(DPP_DEV_T *dev, + ZXIC_UINT32 hash_id, + ZXIC_UINT32 *p_content_type, + ZXIC_UINT32 *p_flag) +{ + DPP_STATUS rtn = DPP_OK; + + DPP_SE4K_SE_ALG_HASH0_EXT_CFG_RGT_T hash_ext_cfg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev),DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_INDEX_UPPER(hash_id,DPP_HASH_ID_MAX); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_content_type); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_flag); + + rtn = dpp_reg_read(dev, + SE4K_SE_ALG_HASH0_EXT_CFG_RGTr + hash_id, + 0, + 0, + &hash_ext_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_read"); + + *p_content_type = hash_ext_cfg.hash0_ext_mode; + *p_flag = hash_ext_cfg.hash0_ext_flag; + + return DPP_OK; +} + +/***********************************************************/ +/** 设置hash业务表深度 +* @param dev_id +* @param hash_id +* @param depth_bit +* @param content_type +* @param flag +* +* @return +* @remark 无 +* @see +* @author tf @date 2016/01/28 +************************************************************/ +DPP_STATUS dpp_se_hash_tbl_depth_set(DPP_DEV_T *dev, + ZXIC_UINT32 hash_id, + ZXIC_UINT32 hash_tbl0_depth, + ZXIC_UINT32 hash_tbl1_depth, + ZXIC_UINT32 hash_tbl2_depth, + ZXIC_UINT32 hash_tbl3_depth, + ZXIC_UINT32 hash_tbl4_depth, + ZXIC_UINT32 hash_tbl5_depth, + ZXIC_UINT32 hash_tbl6_depth, + ZXIC_UINT32 hash_tbl7_depth) + +{ + DPP_STATUS rtn = DPP_OK; + + DPP_SE4K_SE_ALG_HASH0_TBL30_DEPTH_T hash_tbl30_depth = {0}; + DPP_SE4K_SE_ALG_HASH0_TBL74_DEPTH_T hash_tbl74_depth = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev),DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_INDEX_UPPER(hash_id,DPP_HASH_ID_MAX); + + hash_tbl30_depth.hash0_tbl0_depth = hash_tbl0_depth; + hash_tbl30_depth.hash0_tbl1_depth = hash_tbl1_depth; + hash_tbl30_depth.hash0_tbl2_depth = hash_tbl2_depth; + hash_tbl30_depth.hash0_tbl3_depth = hash_tbl3_depth; + hash_tbl74_depth.hash0_tbl4_depth = hash_tbl4_depth; + hash_tbl74_depth.hash0_tbl5_depth = hash_tbl5_depth; + hash_tbl74_depth.hash0_tbl6_depth = hash_tbl6_depth; + hash_tbl74_depth.hash0_tbl7_depth = hash_tbl7_depth; + + rtn = dpp_reg_write(dev, + SE4K_SE_ALG_HASH0_TBL30_DEPTHr + 2 * hash_id, + 0, + 0, + &hash_tbl30_depth); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_write"); + + rtn = dpp_reg_write(dev, + SE4K_SE_ALG_HASH0_TBL74_DEPTHr + 2 * hash_id, + 0, + 0, + &hash_tbl74_depth); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_write"); + + return DPP_OK; +} + +/***********************************************************/ +/** 获取hash业务表深度 +* @param dev_id +* @param hash_id +* @param p_content_type +* @param p_flag +* +* @return +* @remark 无 +* @see +* @author tf @date 2016/01/28 +************************************************************/ +DPP_STATUS dpp_se_hash_tbl_depth_get(DPP_DEV_T *dev, + ZXIC_UINT32 hash_id, + ZXIC_UINT32 *hash_tbl0_depth, + ZXIC_UINT32 *hash_tbl1_depth, + ZXIC_UINT32 *hash_tbl2_depth, + ZXIC_UINT32 *hash_tbl3_depth, + ZXIC_UINT32 *hash_tbl4_depth, + ZXIC_UINT32 *hash_tbl5_depth, + ZXIC_UINT32 *hash_tbl6_depth, + ZXIC_UINT32 *hash_tbl7_depth) + +{ + DPP_STATUS rtn = DPP_OK; + + DPP_SE4K_SE_ALG_HASH0_TBL30_DEPTH_T hash_tbl30_depth = {0}; + DPP_SE4K_SE_ALG_HASH0_TBL74_DEPTH_T hash_tbl74_depth = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev),DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_INDEX_UPPER(hash_id,DPP_HASH_ID_MAX); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), hash_tbl0_depth); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), hash_tbl1_depth); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), hash_tbl2_depth); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), hash_tbl3_depth); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), hash_tbl4_depth); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), hash_tbl5_depth); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), hash_tbl6_depth); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), hash_tbl7_depth); + + rtn = dpp_reg_read(dev, + SE4K_SE_ALG_HASH0_TBL30_DEPTHr + 2 * hash_id, + 0, + 0, + &hash_tbl30_depth); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_read"); + + rtn = dpp_reg_read(dev, + SE4K_SE_ALG_HASH0_TBL74_DEPTHr + 2 * hash_id, + 0, + 0, + &hash_tbl74_depth); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_read"); + + *hash_tbl0_depth = hash_tbl30_depth.hash0_tbl0_depth; + *hash_tbl1_depth = hash_tbl30_depth.hash0_tbl1_depth; + *hash_tbl2_depth = hash_tbl30_depth.hash0_tbl2_depth; + *hash_tbl3_depth = hash_tbl30_depth.hash0_tbl3_depth; + *hash_tbl4_depth = hash_tbl74_depth.hash0_tbl4_depth; + *hash_tbl5_depth = hash_tbl74_depth.hash0_tbl5_depth; + *hash_tbl6_depth = hash_tbl74_depth.hash0_tbl6_depth; + *hash_tbl7_depth = hash_tbl74_depth.hash0_tbl7_depth; + + return DPP_OK; +} + +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se/dpp_stat_car.c b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se/dpp_stat_car.c new file mode 100755 index 0000000..93ac7d6 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se/dpp_stat_car.c @@ -0,0 +1,4545 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_stat_car.c +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : XXX +* 完成日期 : 2017/02/09 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ + +#include "zxic_common.h" +#include "dpp_type_api.h" +#include "dpp_reg.h" +// #include "dpp_devmng_api.h" +#include "dpp_stat_car.h" +#include "dpp_stat_api.h" + +#if ZXIC_REAL("Global Variable") + + +/** 软复位相关 */ +static DPP_CAR_SOFT_RESET_DATA_T g_car_store_data[DPP_DEV_CHANNEL_MAX] = {{{0}}}; + +#define GET_DPP_CAR_SOFT_RESET_INFO(dev_id) (&g_car_store_data[dev_id]) + +#define DPP_CAR1_REG_OFFSET (0) + +#endif + +#if 0 +/***********************************************************/ +/** car 模块初始化 +* @param dev_id 设备号 +* @param p_car_cfg CAR配置信息 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/05/05 +************************************************************/ +DPP_STATUS dpp_stat_car_init(ZXIC_UINT32 dev_id, DPP_CAR_CFG_T *p_car_cfg) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_UINT32 car_type = 0; + ZXIC_UINT32 car_mono_mode = 0; + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_car_cfg); + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, p_car_cfg->car0_mono_mode[dev_id], CAR_SMMU0_MONO_MODE_NONE, CAR_SMMU0_MONO_MODE_MAX - 1); + /* 已经初始化完成，待后添加重新初始化的代码 */ + if (p_car_cfg->is_init[dev_id]) + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "Error! CAR cfg has been initialized!\n"); + } + + car_mono_mode = p_car_cfg->car0_mono_mode[dev_id]; + + for (car_type = STAT_CAR_A_TYPE; car_type < STAT_CAR_MAX_TYPE; car_type++) + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "dpp_stat_car_hardware_init(car_type[%d]) begin\n", car_type); + rc = dpp_stat_car_hardware_init(dev_id, + car_type, + car_mono_mode); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_stat_car_hardware_init"); + } + + p_car_cfg->is_init[dev_id] = 1; + + /* 软复位相关 */ + ZXIC_COMM_MEMSET(&g_car_store_data[dev_id], 0, sizeof(DPP_CAR_SOFT_RESET_DATA_T)); + g_car_store_data[dev_id].is_init = 1; + + return rc; +} +#endif +#if ZXIC_REAL("Basic Reg Operation ") +/***********************************************************/ +/** car A的流设置 +* @param dev_id 设备号 car编号 +* @param flow_id 流号 +* @param drop_flag 丢弃标志 +* @param plcr_en 监管使能 +* @param profile_id 监管模板号 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/04/05 +************************************************************/ +DPP_STATUS dpp_stat_cara_queue_cfg_set(DPP_DEV_T *dev, + ZXIC_UINT32 flow_id, + ZXIC_UINT32 drop_flag, + ZXIC_UINT32 plcr_en, + ZXIC_UINT32 profile_id) +{ + DPP_STATUS rc = DPP_OK; + + DPP_STAT_CAR0_CARA_QUEUE_RAM0_159_0_T queue_cfg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_A_FLOW_ID_MAX); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), drop_flag, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), plcr_en, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0, DPP_CAR_A_PROFILE_ID_MAX); + + queue_cfg.cara_drop = drop_flag; + queue_cfg.cara_plcr_en = plcr_en; + queue_cfg.cara_profile_id = profile_id; + + rc = dpp_reg_write(dev, + STAT_CAR0_CARA_QUEUE_RAM0_159_0r , + 0, + flow_id, + &queue_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write"); + + return rc; +} + +/***********************************************************/ +/** 获取car A的流设置 +* @param dev_id 设备号 +* @param flow_id 流号 +* @param p_cara_queue_cfg car A流配置信息 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/04/05 +************************************************************/ +DPP_STATUS dpp_stat_cara_queue_cfg_get(DPP_DEV_T *dev, + ZXIC_UINT32 flow_id, + DPP_STAT_CAR_A_QUEUE_CFG_T *p_cara_queue_cfg) +{ + DPP_STATUS rc = DPP_OK; + + DPP_STAT_CAR0_CARA_QUEUE_RAM0_159_0_T queue_cfg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_A_FLOW_ID_MAX); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_cara_queue_cfg); + + rc = dpp_reg_read(dev, + STAT_CAR0_CARA_QUEUE_RAM0_159_0r , + 0, + flow_id, + &queue_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + + p_cara_queue_cfg->flow_id = flow_id; + p_cara_queue_cfg->drop_flag = queue_cfg.cara_drop; + p_cara_queue_cfg->plcr_en = queue_cfg.cara_plcr_en; + p_cara_queue_cfg->profile_id = queue_cfg.cara_profile_id; + + p_cara_queue_cfg->tq = ZXIC_COMM_COUNTER64_BUILD(queue_cfg.cara_tq_h, queue_cfg.cara_tq_l); + + p_cara_queue_cfg->ted = queue_cfg.cara_ted; + p_cara_queue_cfg->tcd = queue_cfg.cara_tcd; + p_cara_queue_cfg->tei = queue_cfg.cara_tei; + p_cara_queue_cfg->tci = queue_cfg.cara_tci; + + return rc; +} + +/***********************************************************/ +/** 获取car A 包长监管流配置 +* @param dev_id 设备号 +* @param flow_id 流号 +* @param p_cara_queue_cfg car A流配置信息 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/04/05 +************************************************************/ +DPP_STATUS dpp_stat_cara_pkt_queue_cfg_get(DPP_DEV_T *dev, + ZXIC_UINT32 flow_id, + DPP_STAT_CAR_A_PKT_QUEUE_CFG_T *p_cara_queue_cfg) +{ + DPP_STATUS rc = DPP_OK; + + DPP_STAT_CAR0_CARA_QUEUE_RAM0_159_0_PKT_T queue_cfg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_A_FLOW_ID_MAX); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_cara_queue_cfg); + + rc = dpp_reg_read(dev, + STAT_CAR0_CARA_QUEUE_RAM0_159_0_PKTr , + 0, + flow_id, + &queue_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + + p_cara_queue_cfg->flow_id = flow_id; + p_cara_queue_cfg->plcr_en = queue_cfg.cara_plcr_en; + p_cara_queue_cfg->profile_id = queue_cfg.cara_profile_id; + + p_cara_queue_cfg->tq = ZXIC_COMM_COUNTER64_BUILD(queue_cfg.cara_tq_h, queue_cfg.cara_tq_l); + + p_cara_queue_cfg->dc = ZXIC_COMM_COUNTER64_BUILD(queue_cfg.cara_dc_high, queue_cfg.cara_dc_low); + p_cara_queue_cfg->tc = queue_cfg.cara_tc; + + return rc; +} + + +/***********************************************************/ +/** car A 字节限速监管模板设定 +* @param dev_id 设备号 +* @param profile_id 监管模板号 +* @param p_cara_profile_cfg 监管模板配置 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/04/05 +************************************************************/ +DPP_STATUS dpp_stat_cara_profile_cfg_set(DPP_DEV_T *dev, + ZXIC_UINT32 profile_id, + DPP_STAT_CAR_PROFILE_CFG_T *p_cara_profile_cfg) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_UINT32 i = 0; + + DPP_STAT_CAR0_CARA_PROFILE_RAM1_255_0_T profile_cfg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0, DPP_CAR_A_PROFILE_ID_MAX); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_cara_profile_cfg); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_cara_profile_cfg->profile_id, 0, DPP_CAR_A_PROFILE_ID_MAX); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_cara_profile_cfg->pkt_sign, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_cara_profile_cfg->cf, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_cara_profile_cfg->cm, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_cara_profile_cfg->cd, CAR_CD_MODE_SRTCM, CAR_CD_MODE_INVALID - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_cara_profile_cfg->cir, 0, DPP_CAR_MAX_CIR_VALUE); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_cara_profile_cfg->eir, 0, DPP_CAR_MAX_EIR_VALUE); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_cara_profile_cfg->cbs, 0, DPP_CAR_MAX_CBS_VALUE); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_cara_profile_cfg->ebs, 0, DPP_CAR_MAX_EBS_VALUE); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_cara_profile_cfg->random_disc_e, 0, 0xffffffff); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_cara_profile_cfg->random_disc_c, 0, 0xffffffff); + + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_cara_profile_cfg->e_yellow_pri[0], 0, DPP_CAR_MAX_PRI_VALUE); + + for (i = 1; i < DPP_CAR_PRI_MAX; i++) + { + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_cara_profile_cfg->c_pri[i], 0, DPP_CAR_MAX_PRI_VALUE); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_cara_profile_cfg->e_green_pri[i], 0, DPP_CAR_MAX_PRI_VALUE); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_cara_profile_cfg->e_yellow_pri[i], 0, DPP_CAR_MAX_PRI_VALUE); + } + ZXIC_COMM_TRACE_DEV_INFO(DEV_ID(dev), "==> dpp_stat_cara_profile_cfg_set profile_id[%d]: \n", profile_id); + ZXIC_COMM_TRACE_DEV_INFO(DEV_ID(dev), "| -------------------------------------------------------------- | \n"); + ZXIC_COMM_TRACE_DEV_INFO(DEV_ID(dev), "| %-5s | %-5s | %-5s | %-10s | %-10s | %-10s | %-10s | \n", "cd", "cf", "cm", "cir", "cbs", "eir", "ebs"); + ZXIC_COMM_TRACE_DEV_INFO(DEV_ID(dev), "| %-5d | %-5d | %-5d | %-10d | %-10d | %-10d | %-10d | \n", p_cara_profile_cfg->cd, + p_cara_profile_cfg->cf, + p_cara_profile_cfg->cm, + p_cara_profile_cfg->cir, + p_cara_profile_cfg->cbs, + p_cara_profile_cfg->eir, + p_cara_profile_cfg->ebs); + ZXIC_COMM_TRACE_DEV_INFO(DEV_ID(dev), "| ----- | ----- | ----- | ---------- | ---------- | ---------- | ---------- | \n"); + + profile_cfg.cara_e_y_pri7 = p_cara_profile_cfg->e_yellow_pri[7]; + profile_cfg.cara_e_y_pri6 = p_cara_profile_cfg->e_yellow_pri[6]; + profile_cfg.cara_e_y_pri5 = p_cara_profile_cfg->e_yellow_pri[5]; + profile_cfg.cara_e_y_pri4 = p_cara_profile_cfg->e_yellow_pri[4]; + profile_cfg.cara_e_y_pri3 = p_cara_profile_cfg->e_yellow_pri[3]; + profile_cfg.cara_e_y_pri2 = p_cara_profile_cfg->e_yellow_pri[2]; + profile_cfg.cara_e_y_pri1 = p_cara_profile_cfg->e_yellow_pri[1]; + profile_cfg.cara_e_y_pri0 = p_cara_profile_cfg->e_yellow_pri[0]; + + profile_cfg.cara_e_g_pri7 = p_cara_profile_cfg->e_green_pri[7]; + profile_cfg.cara_e_g_pri6 = p_cara_profile_cfg->e_green_pri[6]; + profile_cfg.cara_e_g_pri5 = p_cara_profile_cfg->e_green_pri[5]; + profile_cfg.cara_e_g_pri4 = p_cara_profile_cfg->e_green_pri[4]; + profile_cfg.cara_e_g_pri3 = p_cara_profile_cfg->e_green_pri[3]; + profile_cfg.cara_e_g_pri2 = p_cara_profile_cfg->e_green_pri[2]; + profile_cfg.cara_e_g_pri1 = p_cara_profile_cfg->e_green_pri[1]; + + profile_cfg.cara_c_pri7 = p_cara_profile_cfg->c_pri[7]; + profile_cfg.cara_c_pri6 = p_cara_profile_cfg->c_pri[6]; + profile_cfg.cara_c_pri5 = p_cara_profile_cfg->c_pri[5]; + profile_cfg.cara_c_pri4 = p_cara_profile_cfg->c_pri[4]; + profile_cfg.cara_c_pri3 = p_cara_profile_cfg->c_pri[3]; + profile_cfg.cara_c_pri2 = p_cara_profile_cfg->c_pri[2]; + profile_cfg.cara_c_pri1 = p_cara_profile_cfg->c_pri[1]; + + profile_cfg.cara_cbs = p_cara_profile_cfg->cbs; + profile_cfg.cara_ebs_pbs = p_cara_profile_cfg->ebs; + profile_cfg.cara_cir = p_cara_profile_cfg->cir; + profile_cfg.cara_eir = p_cara_profile_cfg->eir; + + profile_cfg.cara_cd = p_cara_profile_cfg->cd; + profile_cfg.cara_cf = p_cara_profile_cfg->cf; + profile_cfg.cara_cm = p_cara_profile_cfg->cm; + profile_cfg.cara_pkt_sign = p_cara_profile_cfg->pkt_sign; + + profile_cfg.cara_profile_wr = 0; + + rc = dpp_reg_write(dev, + STAT_CAR0_CARA_PROFILE_RAM1_255_0r , + 0, + profile_id, + &profile_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write"); + + return rc; +} + + +/***********************************************************/ +/** 获取car A包的监管模板配置 +* @param dev_id 设备号 +* @param profile_id 监管模板号 +* @param p_cara_profile_cfg 监管模板配置 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/04/05 +************************************************************/ +DPP_STATUS dpp_stat_cara_profile_cfg_get(DPP_DEV_T *dev, + ZXIC_UINT32 profile_id, + DPP_STAT_CAR_PROFILE_CFG_T *p_cara_profile_cfg) +{ + DPP_STATUS rc = DPP_OK; + + DPP_STAT_CAR0_CARA_PROFILE_RAM1_255_0_T profile_cfg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0, DPP_CAR_A_PROFILE_ID_MAX); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_cara_profile_cfg); + + rc = dpp_reg_read(dev, + STAT_CAR0_CARA_PROFILE_RAM1_255_0r, + 0, + profile_id, + &profile_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + + p_cara_profile_cfg->profile_id = profile_id; + p_cara_profile_cfg->pkt_sign = profile_cfg.cara_pkt_sign; + p_cara_profile_cfg->cd = profile_cfg.cara_cd; + p_cara_profile_cfg->cf = profile_cfg.cara_cf; + p_cara_profile_cfg->cm = profile_cfg.cara_cm; + p_cara_profile_cfg->eir = profile_cfg.cara_eir; + p_cara_profile_cfg->cir = profile_cfg.cara_cir; + p_cara_profile_cfg->ebs = profile_cfg.cara_ebs_pbs; + p_cara_profile_cfg->cbs = profile_cfg.cara_cbs; + + p_cara_profile_cfg->c_pri[1] = profile_cfg.cara_c_pri1; + p_cara_profile_cfg->c_pri[2] = profile_cfg.cara_c_pri2; + p_cara_profile_cfg->c_pri[3] = profile_cfg.cara_c_pri3; + p_cara_profile_cfg->c_pri[4] = profile_cfg.cara_c_pri4; + p_cara_profile_cfg->c_pri[5] = profile_cfg.cara_c_pri5; + p_cara_profile_cfg->c_pri[6] = profile_cfg.cara_c_pri6; + p_cara_profile_cfg->c_pri[7] = profile_cfg.cara_c_pri7; + + p_cara_profile_cfg->e_green_pri[1] = profile_cfg.cara_e_g_pri1; + p_cara_profile_cfg->e_green_pri[2] = profile_cfg.cara_e_g_pri2; + p_cara_profile_cfg->e_green_pri[3] = profile_cfg.cara_e_g_pri3; + p_cara_profile_cfg->e_green_pri[4] = profile_cfg.cara_e_g_pri4; + p_cara_profile_cfg->e_green_pri[5] = profile_cfg.cara_e_g_pri5; + p_cara_profile_cfg->e_green_pri[6] = profile_cfg.cara_e_g_pri6; + p_cara_profile_cfg->e_green_pri[7] = profile_cfg.cara_e_g_pri7; + + p_cara_profile_cfg->e_yellow_pri[0] = profile_cfg.cara_e_y_pri0; + p_cara_profile_cfg->e_yellow_pri[1] = profile_cfg.cara_e_y_pri1; + p_cara_profile_cfg->e_yellow_pri[2] = profile_cfg.cara_e_y_pri2; + p_cara_profile_cfg->e_yellow_pri[3] = profile_cfg.cara_e_y_pri3; + p_cara_profile_cfg->e_yellow_pri[4] = profile_cfg.cara_e_y_pri4; + p_cara_profile_cfg->e_yellow_pri[5] = profile_cfg.cara_e_y_pri5; + p_cara_profile_cfg->e_yellow_pri[6] = profile_cfg.cara_e_y_pri6; + p_cara_profile_cfg->e_yellow_pri[7] = profile_cfg.cara_e_y_pri7; + + return rc; +} + + +/***********************************************************/ +/** car A包限速监管模板设定 +* @param dev_id 设备号 +* @param profile_id 监管模板号 +* @param p_cara_profile_cfg 监管模板配置 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/04/05 +************************************************************/ +DPP_STATUS dpp_stat_cara_pkt_profile_cfg_set(DPP_DEV_T *dev, + ZXIC_UINT32 profile_id, + DPP_STAT_CAR_PKT_PROFILE_CFG_T *p_cara_profile_cfg) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_UINT32 i = 0; + + DPP_STAT_CAR0_CARA_PROFILE_RAM1_255_0_PKT_T profile_cfg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0, DPP_CAR_A_PROFILE_ID_MAX); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_cara_profile_cfg); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_cara_profile_cfg->pkt_sign, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_cara_profile_cfg->cir, 0, DPP_CAR_MAX_CIR_VALUE); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_cara_profile_cfg->cbs, 0, DPP_CAR_MAX_CBS_VALUE); + + for (i = 0; i < DPP_CAR_PRI_MAX; i++) + { + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_cara_profile_cfg->pri[i], 0, DPP_CAR_MAX_PRI_VALUE); + } + + profile_cfg.cara_pri7 = p_cara_profile_cfg->pri[7]; + profile_cfg.cara_pri6 = p_cara_profile_cfg->pri[6]; + profile_cfg.cara_pri5 = p_cara_profile_cfg->pri[5]; + profile_cfg.cara_pri4 = p_cara_profile_cfg->pri[4]; + profile_cfg.cara_pri3 = p_cara_profile_cfg->pri[3]; + profile_cfg.cara_pri2 = p_cara_profile_cfg->pri[2]; + profile_cfg.cara_pri1 = p_cara_profile_cfg->pri[1]; + profile_cfg.cara_pri0 = p_cara_profile_cfg->pri[0]; + + profile_cfg.cara_pkt_cbs = p_cara_profile_cfg->cbs; + profile_cfg.cara_pkt_cir = p_cara_profile_cfg->cir; + profile_cfg.cara_pkt_sign = p_cara_profile_cfg->pkt_sign; + + profile_cfg.cara_profile_wr = 0; + + rc = dpp_reg_write(dev, + STAT_CAR0_CARA_PROFILE_RAM1_255_0_PKTr, + 0, + profile_id, + &profile_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write"); + + return rc; +} + + +/***********************************************************/ +/** 获取car A包长监管模板配置 +* @param dev_id 设备号 +* @param profile_id 监管模板号 +* @param p_cara_profile_cfg 监管模板配置 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/04/05 +************************************************************/ +DPP_STATUS dpp_stat_cara_pkt_profile_cfg_get(DPP_DEV_T *dev, + ZXIC_UINT32 profile_id, + DPP_STAT_CAR_PKT_PROFILE_CFG_T *p_cara_profile_cfg) +{ + DPP_STATUS rc = DPP_OK; + + DPP_STAT_CAR0_CARA_PROFILE_RAM1_255_0_PKT_T profile_cfg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0, DPP_CAR_A_PROFILE_ID_MAX); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_cara_profile_cfg); + + rc = dpp_reg_read(dev, + STAT_CAR0_CARA_PROFILE_RAM1_255_0_PKTr , + 0, + profile_id, + &profile_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + + p_cara_profile_cfg->profile_id = profile_id; + p_cara_profile_cfg->pkt_sign = profile_cfg.cara_pkt_sign; + p_cara_profile_cfg->cir = profile_cfg.cara_pkt_cir; + p_cara_profile_cfg->cbs = profile_cfg.cara_pkt_cbs; + + p_cara_profile_cfg->pri[0] = profile_cfg.cara_pri0; + p_cara_profile_cfg->pri[1] = profile_cfg.cara_pri1; + p_cara_profile_cfg->pri[2] = profile_cfg.cara_pri2; + p_cara_profile_cfg->pri[3] = profile_cfg.cara_pri3; + p_cara_profile_cfg->pri[4] = profile_cfg.cara_pri4; + p_cara_profile_cfg->pri[5] = profile_cfg.cara_pri5; + p_cara_profile_cfg->pri[6] = profile_cfg.cara_pri6; + p_cara_profile_cfg->pri[7] = profile_cfg.cara_pri7; + + return rc; +} + +/***********************************************************/ +/** 配置car A的qvos溢出模式 +* @param dev_id 设备号 +* @param flow_id 流号 +* @param qvos_mode 溢出模式，参见DPP_CAR_QVOS_MODE_E +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/04/06 +************************************************************/ +DPP_STATUS dpp_stat_cara_queue_qvos_set(DPP_DEV_T *dev, + ZXIC_UINT32 flow_id, + ZXIC_UINT32 qvos_mode) +{ + DPP_STATUS rc = DPP_OK; + DPP_STAT_CAR0_CARA_QOVS_RAM_RAM2_T qvos_cfg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_A_FLOW_ID_MAX); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), qvos_mode, CAR_QVOS_MODE_OVERFLOW_0, CAR_QVOS_MODE_OVERFLOW_MAX - 1); + + qvos_cfg.cara_qovs = qvos_mode; + + rc = dpp_reg_write(dev, + STAT_CAR0_CARA_QOVS_RAM_RAM2r , + 0, + flow_id, + &qvos_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write"); + + return rc; +} + +/***********************************************************/ +/** 获取car A的qvos溢出模式 +* @param dev_id 设备号 +* @param flow_id 流号 +* @param p_qvos_mode qvos溢出模式 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/04/06 +************************************************************/ +DPP_STATUS dpp_stat_cara_queue_qvos_get(DPP_DEV_T *dev, + ZXIC_UINT32 flow_id, + ZXIC_UINT32 *p_qvos_mode) +{ + DPP_STATUS rc = DPP_OK; + DPP_STAT_CAR0_CARA_QOVS_RAM_RAM2_T qvos_cfg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_A_FLOW_ID_MAX); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_qvos_mode); + + rc = dpp_reg_read(dev, + STAT_CAR0_CARA_QOVS_RAM_RAM2r , + 0, + flow_id, + &qvos_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + + *p_qvos_mode = qvos_cfg.cara_qovs; + + return rc; +} + + +/***********************************************************/ +/** 设置第一级的映射关系 +* @param dev_id 设备号 +* @param flow_id 流号 +* @param map_flow_id 映射的流号 +* @param map_sp 映射的优先级 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/04/06 +************************************************************/ +DPP_STATUS dpp_stat_cara_queue_map_set(DPP_DEV_T *dev, + ZXIC_UINT32 flow_id, + ZXIC_UINT32 map_flow_id, + ZXIC_UINT32 map_sp) +{ + DPP_STATUS rc = DPP_OK; + DPP_STAT_CAR0_LOOK_UP_TABLE1_T map_cfg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_A_FLOW_ID_MAX); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), map_flow_id, 0, DPP_CAR_B_FLOW_ID_MAX); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), map_sp, DPP_CAR_PRI0, DPP_CAR_PRI_MAX - 1); + + map_cfg.cara_flow_id = map_flow_id; + map_cfg.cara_sp = map_sp; + + rc = dpp_reg_write(dev, + STAT_CAR0_LOOK_UP_TABLE1r , + 0, + flow_id, + &map_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write"); + + return rc; +} + +/***********************************************************/ +/** 获取第一级的映射关系 +* @param dev_id 设备号 +* @param flow_id 流号 +* @param p_map_flow_id 映射流号 +* @param p_map_sp 映射优先级 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/04/06 +************************************************************/ +DPP_STATUS dpp_stat_cara_queue_map_get(DPP_DEV_T *dev, + ZXIC_UINT32 flow_id, + ZXIC_UINT32 *p_map_flow_id, + ZXIC_UINT32 *p_map_sp) +{ + DPP_STATUS rc = DPP_OK; + DPP_STAT_CAR0_LOOK_UP_TABLE1_T map_cfg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_A_FLOW_ID_MAX); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_map_flow_id); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_map_sp); + + rc = dpp_reg_read(dev, + STAT_CAR0_LOOK_UP_TABLE1r, + 0, + flow_id, + &map_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + + *p_map_flow_id = map_cfg.cara_flow_id; + *p_map_sp = map_cfg.cara_sp; + + return rc; +} + +/***********************************************************/ +/** car A指定队列模式配置，仅用于调试 +* @param dev_id 设备号 +* @param global_en 全局队列使能，0-不使能，1-使能 +* @param sp_en 优先级队列使能，0-不使能，1-使能 +* @param appoint_sp 指定的优先级 +* @param appoint_queue 指定的队列号 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/04/06 +************************************************************/ +DPP_STATUS dpp_stat_cara_queue_appoint_mode_set(DPP_DEV_T *dev, + ZXIC_UINT32 global_en, + ZXIC_UINT32 sp_en, + ZXIC_UINT32 appoint_sp, + ZXIC_UINT32 appoint_queue) +{ + DPP_STATUS rc = DPP_OK; + DPP_STAT_CAR0_CARA_APPOINT_QNUM_OR_SP_T appoint_cfg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), global_en, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), sp_en, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), appoint_sp, DPP_CAR_PRI0, DPP_CAR_PRI_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), appoint_queue, 0, DPP_CAR_A_FLOW_ID_MAX); + + appoint_cfg.cara_appoint_qnum_or_not = global_en; + appoint_cfg.cara_appoint_sp_or_not = sp_en; + appoint_cfg.cara_plcr_stat_sp = appoint_sp; + appoint_cfg.cara_plcr_stat_qnum = appoint_queue; + + rc = dpp_reg_write(dev, + STAT_CAR0_CARA_APPOINT_QNUM_OR_SPr , + 0, + 0, + &appoint_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write"); + + return rc; +} + +/***********************************************************/ +/** 获取car A指定队列模式的配置 +* @param dev_id 设备号 +* @param p_global_en 全局队列使能，0-不使能，1-使能 +* @param p_sp_en 优先级队列使能，0-不使能，1-使能 +* @param p_appoint_sp 指定的优先级 +* @param p_appoint_queue 指定的队列号 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/04/07 +************************************************************/ +DPP_STATUS dpp_stat_cara_queue_appoint_mode_get(DPP_DEV_T *dev, + ZXIC_UINT32 *p_global_en, + ZXIC_UINT32 *p_sp_en, + ZXIC_UINT32 *p_appoint_sp, + ZXIC_UINT32 *p_appoint_queue) +{ + DPP_STATUS rc = DPP_OK; + DPP_STAT_CAR0_CARA_APPOINT_QNUM_OR_SP_T appoint_cfg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_global_en); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_sp_en); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_appoint_sp); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_appoint_queue); + + rc = dpp_reg_read(dev, + STAT_CAR0_CARA_APPOINT_QNUM_OR_SPr, + 0, + 0, + &appoint_cfg); + + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + + *p_global_en = appoint_cfg.cara_appoint_qnum_or_not; + *p_sp_en = appoint_cfg.cara_appoint_sp_or_not; + *p_appoint_sp = appoint_cfg.cara_plcr_stat_sp; + *p_appoint_queue = appoint_cfg.cara_plcr_stat_qnum; + + return rc; +} + + +/***********************************************************/ +/** car A 调试计数读取模式配置 +* @param dev_id 设备号 +* @param overflow_mode 溢出模式，0-计数最大保持，1-计数最大翻转 +* @param rd_mode 读取模式，0-不读清，1-读清模式 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/04/06 +************************************************************/ +DPP_STATUS dpp_stat_cara_dbg_cnt_mode_set(DPP_DEV_T *dev, + ZXIC_UINT32 overflow_mode, + ZXIC_UINT32 rd_mode) +{ + DPP_STATUS rc = DPP_OK; + DPP_STAT_CAR0_CARA_CFGMT_COUNT_MODE_T cnt_mode_cfg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), overflow_mode, CAR_KEEP_COUNT, CAR_RE_COUNT); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), rd_mode, CAR_READ_NOT_CLEAR, CAR_READ_AND_CLEAR); + + cnt_mode_cfg.cara_cfgmt_count_overflow_mode = overflow_mode; + cnt_mode_cfg.cara_cfgmt_count_rd_mode = rd_mode; + + rc = dpp_reg_write(dev, + STAT_CAR0_CARA_CFGMT_COUNT_MODEr , + 0, + 0, + &cnt_mode_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write"); + + return rc; +} + +/***********************************************************/ +/** car A 调试计数读取模式获取 +* @param dev_id 设备号 +* @param p_overflow_mode +* @param p_rd_mode +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/04/06 +************************************************************/ +DPP_STATUS dpp_stat_cara_dbg_cnt_mode_get(DPP_DEV_T *dev, + ZXIC_UINT32 *p_overflow_mode, + ZXIC_UINT32 *p_rd_mode) +{ + DPP_STATUS rc = DPP_OK; + DPP_STAT_CAR0_CARA_CFGMT_COUNT_MODE_T cnt_mode_cfg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_overflow_mode); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_rd_mode); + + rc = dpp_reg_read(dev, + STAT_CAR0_CARA_CFGMT_COUNT_MODEr, + 0, + 0, + &cnt_mode_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + + *p_overflow_mode = cnt_mode_cfg.cara_cfgmt_count_overflow_mode; + *p_rd_mode = cnt_mode_cfg.cara_cfgmt_count_rd_mode; + + return rc; +} + +#if 0 +/***********************************************************/ +/** car a 的调试计数获取 +* @param dev_id +* @param p_car_dbg_cnt +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/09/27 +************************************************************/ +DPP_STATUS dpp_stat_cara_dbg_cnt_get(ZXIC_UINT32 dev_id, + DPP_STAT_CAR_DBG_CNT_T *p_car_dbg_cnt) +{ + DPP_STATUS rc = DPP_OK; + DPP_STAT_CAR0_CARA_PKT_DES_I_CNT_T cara_pkt_in_total_cnt_cfg = {0}; + DPP_STAT_CAR0_CARA_PKT_SIZE_CNT_T cara_pkt_size_cnt_cfg = {0}; + ZXIC_UINT32 i = 0; + ZXIC_UINT32 size = 0; + ZXIC_UINT32 *p_tmp_cnt = NULL; + + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_car_dbg_cnt); + + size = sizeof(DPP_STAT_CAR_DBG_CNT_T) / sizeof(ZXIC_UINT32) - 1; + p_tmp_cnt = (ZXIC_UINT32 *)p_car_dbg_cnt; + + for (i = 0; i < size; i++) + { + rc = dpp_reg_read(dev_id, + STAT_CAR0_CARA_PKT_DES_I_CNTr + i, + 0, + 0, + &cara_pkt_in_total_cnt_cfg); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_reg_read"); + + ZXIC_COMM_MEMCPY(p_tmp_cnt + i, &(cara_pkt_in_total_cnt_cfg.cara_pkt_des_i_cnt), sizeof(ZXIC_UINT32)); + } + + /* STAT_CAR0_CARA_PKT_SIZE_CNTr 不连续，单独读取 */ + rc = dpp_reg_read(dev_id, + STAT_CAR0_CARA_PKT_SIZE_CNTr, + 0, + 0, + &cara_pkt_size_cnt_cfg); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_reg_read"); + + p_car_dbg_cnt->pkt_size_cnt = cara_pkt_size_cnt_cfg.cara_pkt_size_cnt; + + return rc; +} + +/***********************************************************/ +/** 获取car A的初始化状态 +* @param dev_id 设备号 +* @param p_init_done 初始化完成使能 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/04/06 +************************************************************/ +DPP_STATUS dpp_stat_cara_init_done_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *p_init_done) +{ + DPP_STATUS rc = DPP_OK; + DPP_STAT_CAR0_CARA_PLCR_INIT_DONT_T cara_init_done_cfg = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_init_done); + + rc = dpp_reg_read(dev_id, + STAT_CAR0_CARA_PLCR_INIT_DONTr, + 0, + 0, + &cara_init_done_cfg); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_reg_read"); + + *p_init_done = cara_init_done_cfg.cara_plcr_init_done; + + return rc; +} + +#endif +/***********************************************************/ +/** car B的流设置 +* @param dev_id 设备号 +* @param flow_id 流号 +* @param drop_flag 丢弃标志 +* @param plcr_en 监管使能 +* @param profile_id 监管模板号 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/04/05 +************************************************************/ +DPP_STATUS dpp_stat_carb_queue_cfg_set(DPP_DEV_T *dev, + ZXIC_UINT32 flow_id, + ZXIC_UINT32 drop_flag, + ZXIC_UINT32 plcr_en, + ZXIC_UINT32 profile_id) +{ + DPP_STATUS rc = DPP_OK; + + DPP_STAT_CAR0_CARB_QUEUE_RAM0_159_0_T queue_cfg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_B_FLOW_ID_MAX); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), drop_flag, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), plcr_en, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0, DPP_CAR_B_PROFILE_ID_MAX); + + queue_cfg.carb_drop = drop_flag; + queue_cfg.carb_plcr_en = plcr_en; + queue_cfg.carb_profile_id = profile_id; + + rc = dpp_reg_write(dev, + STAT_CAR0_CARB_QUEUE_RAM0_159_0r , + 0, + flow_id, + &queue_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write"); + + return rc; +} + +/***********************************************************/ +/** 获取car B的流设置 +* @param dev_id 设备号 +* @param flow_id 流号 +* @param p_carb_queue_cfg car A流配置信息 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/04/05 +************************************************************/ +DPP_STATUS dpp_stat_carb_queue_cfg_get(DPP_DEV_T *dev, + ZXIC_UINT32 flow_id, + DPP_STAT_CAR_B_QUEUE_CFG_T *p_carb_queue_cfg) +{ + DPP_STATUS rc = DPP_OK; + + DPP_STAT_CAR0_CARB_QUEUE_RAM0_159_0_T queue_cfg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_B_FLOW_ID_MAX); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_carb_queue_cfg); + + rc = dpp_reg_read(dev, + STAT_CAR0_CARB_QUEUE_RAM0_159_0r, + 0, + flow_id, + &queue_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + + p_carb_queue_cfg->flow_id = flow_id; + p_carb_queue_cfg->drop_flag = queue_cfg.carb_drop; + p_carb_queue_cfg->plcr_en = queue_cfg.carb_plcr_en; + p_carb_queue_cfg->profile_id = queue_cfg.carb_profile_id; + + p_carb_queue_cfg->tq = ZXIC_COMM_COUNTER64_BUILD(queue_cfg.carb_tq_h, queue_cfg.carb_tq_l); + + p_carb_queue_cfg->tce_flag = queue_cfg.carb_ted; + p_carb_queue_cfg->tce = queue_cfg.carb_tcd; + p_carb_queue_cfg->te = queue_cfg.carb_tei; + p_carb_queue_cfg->tc = queue_cfg.carb_tci; + + return rc; +} + +/***********************************************************/ +/** car B监管模板设定 +* @param dev_id 设备号 +* @param profile_id 监管模板号 +* @param p_carb_profile_cfg 监管模板配置 +* pkt_sign 包限速标记写死成0，防止用户在carB包限速 +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/04/05 +************************************************************/ +DPP_STATUS dpp_stat_carb_profile_cfg_set(DPP_DEV_T *dev, + ZXIC_UINT32 profile_id, + DPP_STAT_CAR_PROFILE_CFG_T *p_carb_profile_cfg) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_UINT32 i = 0; + + DPP_STAT_CAR0_CARB_PROFILE_RAM1_255_0_T profile_cfg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0, DPP_CAR_B_PROFILE_ID_MAX); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_carb_profile_cfg); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carb_profile_cfg->pkt_sign, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carb_profile_cfg->cf, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carb_profile_cfg->cm, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carb_profile_cfg->random_disc_e, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carb_profile_cfg->random_disc_c, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carb_profile_cfg->cd, CAR_CD_MODE_SRTCM, CAR_CD_MODE_INVALID - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carb_profile_cfg->cir, 0, DPP_CAR_MAX_CIR_VALUE); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carb_profile_cfg->eir, 0, DPP_CAR_MAX_EIR_VALUE); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carb_profile_cfg->cbs, 0, DPP_CAR_MAX_CBS_VALUE); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carb_profile_cfg->ebs, 0, DPP_CAR_MAX_EBS_VALUE); + + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carb_profile_cfg->e_yellow_pri[0], 0, DPP_CAR_MAX_PRI_VALUE); + + for (i = 1; i < DPP_CAR_PRI_MAX; i++) + { + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carb_profile_cfg->c_pri[i], 0, DPP_CAR_MAX_PRI_VALUE); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carb_profile_cfg->e_green_pri[i], 0, DPP_CAR_MAX_PRI_VALUE); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carb_profile_cfg->e_yellow_pri[i], 0, DPP_CAR_MAX_PRI_VALUE); + } + + profile_cfg.carb_e_y_pri7 = p_carb_profile_cfg->e_yellow_pri[7]; + profile_cfg.carb_e_y_pri6 = p_carb_profile_cfg->e_yellow_pri[6]; + profile_cfg.carb_e_y_pri5 = p_carb_profile_cfg->e_yellow_pri[5]; + profile_cfg.carb_e_y_pri4 = p_carb_profile_cfg->e_yellow_pri[4]; + profile_cfg.carb_e_y_pri3 = p_carb_profile_cfg->e_yellow_pri[3]; + profile_cfg.carb_e_y_pri2 = p_carb_profile_cfg->e_yellow_pri[2]; + profile_cfg.carb_e_y_pri1 = p_carb_profile_cfg->e_yellow_pri[1]; + profile_cfg.carb_e_y_pri0 = p_carb_profile_cfg->e_yellow_pri[0]; + + profile_cfg.carb_e_g_pri7 = p_carb_profile_cfg->e_green_pri[7]; + profile_cfg.carb_e_g_pri6 = p_carb_profile_cfg->e_green_pri[6]; + profile_cfg.carb_e_g_pri5 = p_carb_profile_cfg->e_green_pri[5]; + profile_cfg.carb_e_g_pri4 = p_carb_profile_cfg->e_green_pri[4]; + profile_cfg.carb_e_g_pri3 = p_carb_profile_cfg->e_green_pri[3]; + profile_cfg.carb_e_g_pri2 = p_carb_profile_cfg->e_green_pri[2]; + profile_cfg.carb_e_g_pri1 = p_carb_profile_cfg->e_green_pri[1]; + + profile_cfg.carb_c_pri7 = p_carb_profile_cfg->c_pri[7]; + profile_cfg.carb_c_pri6 = p_carb_profile_cfg->c_pri[6]; + profile_cfg.carb_c_pri5 = p_carb_profile_cfg->c_pri[5]; + profile_cfg.carb_c_pri4 = p_carb_profile_cfg->c_pri[4]; + profile_cfg.carb_c_pri3 = p_carb_profile_cfg->c_pri[3]; + profile_cfg.carb_c_pri2 = p_carb_profile_cfg->c_pri[2]; + profile_cfg.carb_c_pri1 = p_carb_profile_cfg->c_pri[1]; + + profile_cfg.carb_cbs = p_carb_profile_cfg->cbs; + profile_cfg.carb_ebs_pbs = p_carb_profile_cfg->ebs; + profile_cfg.carb_cir = p_carb_profile_cfg->cir; + profile_cfg.carb_eir = p_carb_profile_cfg->eir; + + profile_cfg.carb_cd = p_carb_profile_cfg->cd; + profile_cfg.carb_cf = p_carb_profile_cfg->cf; + profile_cfg.carb_cm = p_carb_profile_cfg->cm; + + profile_cfg.carb_random_discard_en_e = p_carb_profile_cfg->random_disc_e; + profile_cfg.carb_random_discard_en_c = p_carb_profile_cfg->random_disc_c; + /* B级car包限速标记写死为0，以免用户配置成1对CARB进行包限速 */ + profile_cfg.carb_pkt_sign = 0; + + profile_cfg.carb_profile_wr = 0; + + rc = dpp_reg_write(dev, + STAT_CAR0_CARB_PROFILE_RAM1_255_0r, + 0, + profile_id, + &profile_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write"); + + return rc; +} + + +/***********************************************************/ +/** 获取car B的监管模板配置 +* @param dev_id 设备号 +* @param profile_id 监管模板号 +* @param p_carb_profile_cfg 监管模板配置 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/04/05 +************************************************************/ +DPP_STATUS dpp_stat_carb_profile_cfg_get(DPP_DEV_T *dev, + ZXIC_UINT32 profile_id, + DPP_STAT_CAR_PROFILE_CFG_T *p_carb_profile_cfg) +{ + DPP_STATUS rc = DPP_OK; + + DPP_STAT_CAR0_CARB_PROFILE_RAM1_255_0_T profile_cfg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0, DPP_CAR_B_PROFILE_ID_MAX); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_carb_profile_cfg); + + rc = dpp_reg_read(dev, + STAT_CAR0_CARB_PROFILE_RAM1_255_0r, + 0, + profile_id, + &profile_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + + p_carb_profile_cfg->profile_id = profile_id; + p_carb_profile_cfg->pkt_sign = profile_cfg.carb_pkt_sign; + p_carb_profile_cfg->cd = profile_cfg.carb_cd; + p_carb_profile_cfg->cf = profile_cfg.carb_cf; + p_carb_profile_cfg->cm = profile_cfg.carb_cm; + p_carb_profile_cfg->eir = profile_cfg.carb_eir; + p_carb_profile_cfg->cir = profile_cfg.carb_cir; + p_carb_profile_cfg->ebs = profile_cfg.carb_ebs_pbs; + p_carb_profile_cfg->cbs = profile_cfg.carb_cbs; + p_carb_profile_cfg->random_disc_e = profile_cfg.carb_random_discard_en_e; + p_carb_profile_cfg->random_disc_c = profile_cfg.carb_random_discard_en_c; + + p_carb_profile_cfg->c_pri[1] = profile_cfg.carb_c_pri1; + p_carb_profile_cfg->c_pri[2] = profile_cfg.carb_c_pri2; + p_carb_profile_cfg->c_pri[3] = profile_cfg.carb_c_pri3; + p_carb_profile_cfg->c_pri[4] = profile_cfg.carb_c_pri4; + p_carb_profile_cfg->c_pri[5] = profile_cfg.carb_c_pri5; + p_carb_profile_cfg->c_pri[6] = profile_cfg.carb_c_pri6; + p_carb_profile_cfg->c_pri[7] = profile_cfg.carb_c_pri7; + + p_carb_profile_cfg->e_green_pri[1] = profile_cfg.carb_e_g_pri1; + p_carb_profile_cfg->e_green_pri[2] = profile_cfg.carb_e_g_pri2; + p_carb_profile_cfg->e_green_pri[3] = profile_cfg.carb_e_g_pri3; + p_carb_profile_cfg->e_green_pri[4] = profile_cfg.carb_e_g_pri4; + p_carb_profile_cfg->e_green_pri[5] = profile_cfg.carb_e_g_pri5; + p_carb_profile_cfg->e_green_pri[6] = profile_cfg.carb_e_g_pri6; + p_carb_profile_cfg->e_green_pri[7] = profile_cfg.carb_e_g_pri7; + + p_carb_profile_cfg->e_yellow_pri[0] = profile_cfg.carb_e_y_pri0; + p_carb_profile_cfg->e_yellow_pri[1] = profile_cfg.carb_e_y_pri1; + p_carb_profile_cfg->e_yellow_pri[2] = profile_cfg.carb_e_y_pri2; + p_carb_profile_cfg->e_yellow_pri[3] = profile_cfg.carb_e_y_pri3; + p_carb_profile_cfg->e_yellow_pri[4] = profile_cfg.carb_e_y_pri4; + p_carb_profile_cfg->e_yellow_pri[5] = profile_cfg.carb_e_y_pri5; + p_carb_profile_cfg->e_yellow_pri[6] = profile_cfg.carb_e_y_pri6; + p_carb_profile_cfg->e_yellow_pri[7] = profile_cfg.carb_e_y_pri7; + + return rc; +} + +/***********************************************************/ +/** 配置car B的qvos溢出模式 +* @param dev_id 设备号 +* @param flow_id 流号 +* @param qvos_mode 溢出模式，参见DPP_CAR_QVOS_MODE_E +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/04/06 +************************************************************/ +DPP_STATUS dpp_stat_carb_queue_qvos_set(DPP_DEV_T *dev, + ZXIC_UINT32 flow_id, + ZXIC_UINT32 qvos_mode) +{ + DPP_STATUS rc = DPP_OK; + DPP_STAT_CAR0_CARB_QOVS_RAM_RAM2_T qvos_cfg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_B_FLOW_ID_MAX); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), qvos_mode, CAR_QVOS_MODE_OVERFLOW_0, CAR_QVOS_MODE_OVERFLOW_MAX - 1); + + qvos_cfg.carb_qovs = qvos_mode; + + rc = dpp_reg_write(dev, + STAT_CAR0_CARB_QOVS_RAM_RAM2r, + 0, + flow_id, + &qvos_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write"); + + return rc; +} +/***********************************************************/ +/** 获取car B的qvos溢出模式 +* @param dev_id 设备号 +* @param flow_id 流号 +* @param p_qvos_mode qvos溢出模式 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/04/06 +************************************************************/ +DPP_STATUS dpp_stat_carb_queue_qvos_get(DPP_DEV_T *dev, + ZXIC_UINT32 flow_id, + ZXIC_UINT32 *p_qvos_mode) +{ + DPP_STATUS rc = DPP_OK; + DPP_STAT_CAR0_CARB_QOVS_RAM_RAM2_T qvos_cfg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_B_FLOW_ID_MAX); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_qvos_mode); + + rc = dpp_reg_read(dev, + STAT_CAR0_CARB_QOVS_RAM_RAM2r , + 0, + flow_id, + &qvos_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + + *p_qvos_mode = qvos_cfg.carb_qovs; + + return rc; +} + +/***********************************************************/ +/** 设置第二级的映射关系 +* @param dev_id 设备号 +* @param flow_id 流号 +* @param map_flow_id 映射的流号 +* @param map_sp 映射的优先级 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/04/06 +************************************************************/ +DPP_STATUS dpp_stat_carb_queue_map_set(DPP_DEV_T *dev, + ZXIC_UINT32 flow_id, + ZXIC_UINT32 map_flow_id, + ZXIC_UINT32 map_sp) +{ + DPP_STATUS rc = DPP_OK; + DPP_STAT_CAR0_LOOK_UP_TABLE2_T map_cfg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_B_FLOW_ID_MAX); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), map_flow_id, 0, DPP_CAR_C_FLOW_ID_MAX); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), map_sp, DPP_CAR_PRI0, DPP_CAR_PRI_MAX - 1); + + map_cfg.carb_flow_id = map_flow_id; + map_cfg.carb_sp = map_sp; + + rc = dpp_reg_write(dev, + STAT_CAR0_LOOK_UP_TABLE2r , + 0, + flow_id, + &map_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write"); + + return rc; +} + +/***********************************************************/ +/** 获取第二级的映射关系 +* @param dev_id 设备号 +* @param flow_id 流号 +* @param p_map_flow_id 映射流号 +* @param p_map_sp 映射优先级 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/04/06 +************************************************************/ +DPP_STATUS dpp_stat_carb_queue_map_get(DPP_DEV_T *dev, + ZXIC_UINT32 flow_id, + ZXIC_UINT32 *p_map_flow_id, + ZXIC_UINT32 *p_map_sp) +{ + DPP_STATUS rc = DPP_OK; + DPP_STAT_CAR0_LOOK_UP_TABLE2_T map_cfg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_B_FLOW_ID_MAX); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_map_flow_id); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_map_sp); + + rc = dpp_reg_read(dev, + STAT_CAR0_LOOK_UP_TABLE2r , + 0, + flow_id, + &map_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + + *p_map_flow_id = map_cfg.carb_flow_id; + *p_map_sp = map_cfg.carb_sp; + + return rc; +} + +#if 0 +/***********************************************************/ +/** car B指定队列模式配置，仅用于调试 +* @param dev_id 设备号 +* @param global_en 全局队列使能，0-不使能，1-使能 +* @param sp_en 优先级队列使能，0-不使能，1-使能 +* @param appoint_sp 指定的优先级 +* @param appoint_queue 指定的队列号 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/04/06 +************************************************************/ +DPP_STATUS dpp_stat_carb_queue_appoint_mode_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 global_en, + ZXIC_UINT32 sp_en, + ZXIC_UINT32 appoint_sp, + ZXIC_UINT32 appoint_queue) +{ + DPP_STATUS rc = DPP_OK; + DPP_STAT_CAR0_CARB_APPOINT_QNUM_OR_SP_T appoint_cfg = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, global_en, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, sp_en, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, appoint_sp, DPP_CAR_PRI0, DPP_CAR_PRI_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, appoint_queue, 0, DPP_CAR_B_FLOW_ID_MAX); + + appoint_cfg.carb_appoint_qnum_or_not = global_en; + appoint_cfg.carb_appoint_sp_or_not = sp_en; + appoint_cfg.carb_plcr_stat_sp = appoint_sp; + appoint_cfg.carb_plcr_stat_qnum = appoint_queue; + + rc = dpp_reg_write(dev_id, + STAT_CAR0_CARB_APPOINT_QNUM_OR_SPr, + 0, + 0, + &appoint_cfg); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_reg_write"); + + return rc; +} + +/***********************************************************/ +/** 获取car B指定队列模式的配置 +* @param dev_id 设备号 +* @param p_global_en 全局队列使能，0-不使能，1-使能 +* @param p_sp_en 优先级队列使能，0-不使能，1-使能 +* @param p_appoint_sp 指定的优先级 +* @param p_appoint_queue 指定的队列号 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/04/07 +************************************************************/ +DPP_STATUS dpp_stat_carb_queue_appoint_mode_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *p_global_en, + ZXIC_UINT32 *p_sp_en, + ZXIC_UINT32 *p_appoint_sp, + ZXIC_UINT32 *p_appoint_queue) +{ + DPP_STATUS rc = DPP_OK; + DPP_STAT_CAR0_CARB_APPOINT_QNUM_OR_SP_T appoint_cfg = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_global_en); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_sp_en); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_appoint_sp); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_appoint_queue); + + rc = dpp_reg_read(dev_id, + STAT_CAR0_CARB_APPOINT_QNUM_OR_SPr, + 0, + 0, + &appoint_cfg); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_reg_read"); + + *p_global_en = appoint_cfg.carb_appoint_qnum_or_not; + *p_sp_en = appoint_cfg.carb_appoint_sp_or_not; + *p_appoint_sp = appoint_cfg.carb_plcr_stat_sp; + *p_appoint_queue = appoint_cfg.carb_plcr_stat_qnum; + + return rc; +} + +/***********************************************************/ +/** car B 调试计数读取模式配置 +* @param dev_id 设备号 +* @param overflow_mode 溢出模式，0-计数最大保持，1-计数最大翻转 +* @param rd_mode 读取模式，0-不读清，1-读清模式 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/04/06 +************************************************************/ +DPP_STATUS dpp_stat_carb_dbg_cnt_mode_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 overflow_mode, + ZXIC_UINT32 rd_mode) +{ + DPP_STATUS rc = DPP_OK; + DPP_STAT_CAR0_CARB_CFGMT_COUNT_MODE_T cnt_mode_cfg = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, overflow_mode, CAR_KEEP_COUNT, CAR_RE_COUNT); + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, rd_mode, CAR_READ_NOT_CLEAR, CAR_READ_AND_CLEAR); + + cnt_mode_cfg.carb_cfgmt_count_overflow_mode = overflow_mode; + cnt_mode_cfg.carb_cfgmt_count_rd_mode = rd_mode; + + rc = dpp_reg_write(dev_id, + STAT_CAR0_CARB_CFGMT_COUNT_MODEr, + 0, + 0, + &cnt_mode_cfg); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_reg_write"); + + return rc; +} + +/***********************************************************/ +/** +* @param dev_id +* @param p_overflow_mode +* @param p_rd_mode +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/04/06 +************************************************************/ +DPP_STATUS dpp_stat_carb_dbg_cnt_mode_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *p_overflow_mode, + ZXIC_UINT32 *p_rd_mode) +{ + DPP_STATUS rc = DPP_OK; + DPP_STAT_CAR0_CARB_CFGMT_COUNT_MODE_T cnt_mode_cfg = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_overflow_mode); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_rd_mode); + + rc = dpp_reg_read(dev_id, + STAT_CAR0_CARB_CFGMT_COUNT_MODEr, + 0, + 0, + &cnt_mode_cfg); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_reg_read"); + + *p_overflow_mode = cnt_mode_cfg.carb_cfgmt_count_overflow_mode; + *p_rd_mode = cnt_mode_cfg.carb_cfgmt_count_rd_mode; + + return rc; +} + +/***********************************************************/ +/** car b 的调试计数获取 +* @param dev_id +* @param p_car_dbg_cnt +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/09/27 +************************************************************/ +DPP_STATUS dpp_stat_carb_dbg_cnt_get(ZXIC_UINT32 dev_id, + DPP_STAT_CAR_DBG_CNT_T *p_car_dbg_cnt) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_UINT32 i = 0; + ZXIC_UINT32 size = 0; + ZXIC_UINT32 *p_tmp_cnt = NULL; + + DPP_STAT_CAR0_CARB_PKT_SIZE_CNT_T carb_pkt_size_cnt_cfg = {0}; + DPP_STAT_CAR0_CARB_PKT_DES_I_CNT_T carb_pkt_in_total_cnt_cfg = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_car_dbg_cnt); + + size = sizeof(DPP_STAT_CAR_DBG_CNT_T) / sizeof(ZXIC_UINT32) - 1; + p_tmp_cnt = (ZXIC_UINT32 *)p_car_dbg_cnt; + + for (i = 0; i < size; i++) + { + rc = dpp_reg_read(dev_id, + STAT_CAR0_CARB_PKT_DES_I_CNTr + i, + 0, + 0, + &carb_pkt_in_total_cnt_cfg); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_reg_read"); + + ZXIC_COMM_MEMCPY(p_tmp_cnt + i, &(carb_pkt_in_total_cnt_cfg.carb_pkt_des_i_cnt), sizeof(ZXIC_UINT32)); + } + + rc = dpp_reg_read(dev_id, + STAT_CAR0_CARB_PKT_SIZE_CNTr, + 0, + 0, + &carb_pkt_size_cnt_cfg); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_reg_read"); + + p_car_dbg_cnt->pkt_size_cnt = carb_pkt_size_cnt_cfg.carb_pkt_size_cnt; + + return rc; +} + + +/***********************************************************/ +/** 获取car B的初始化状态 +* @param dev_id 设备号 car编号 +* @param p_init_done 初始化完成使能 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/04/06 +************************************************************/ +DPP_STATUS dpp_stat_carb_init_done_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *p_init_done) +{ + DPP_STATUS rc = DPP_OK; + DPP_STAT_CAR0_CARB_PLCR_INIT_DONT_T carb_init_done_cfg = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_init_done); + + rc = dpp_reg_read(dev_id, + STAT_CAR0_CARB_PLCR_INIT_DONTr , + 0, + 0, + &carb_init_done_cfg); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_reg_read"); + + *p_init_done = carb_init_done_cfg.carb_plcr_init_done; + + return rc; +} + +#endif +/***********************************************************/ +/** +* @param dev_id +* @param profile_id +* @param p_random_ram +* +* @return +* @remark 无 +* @see +* @author YXH @date 2019/04/01 +************************************************************/ +DPP_STATUS dpp_stat_carb_random_ram_set(DPP_DEV_T *dev, + ZXIC_UINT32 profile_id, + DPP_CAR_RANDOM_RAM_T *p_random_ram_e, + DPP_CAR_RANDOM_RAM_T *p_random_ram_c) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_UINT64 para0_temp = 0; + ZXIC_UINT64 para2_temp = 0; + ZXIC_UINT64 para4_temp = 0; + DPP_STAT_CAR0_CARB_RANDOM_RAM_T carb_random_ram_cfg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_random_ram_e); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_random_ram_e->p1, 0, 100); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_random_ram_e->p2, 0, 100); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_random_ram_e->p3, 0, 100); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_random_ram_c); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_random_ram_c->p1, 0, 100); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_random_ram_c->p2, 0, 100); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_random_ram_c->p3, 0, 100); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0, DPP_CAR_B_PROFILE_ID_RANDOM_MAX); + + para0_temp = ((ZXIC_UINT64)((((ZXIC_UINT64)(p_random_ram_e->t2)) - ((ZXIC_UINT64)(p_random_ram_e->t1))) * ((ZXIC_UINT64)(p_random_ram_e->p1))) << DPP_CAR_RANDOM_OFFSET_VAL) / 100; + carb_random_ram_cfg.para0_l_e = (para0_temp & 0xFFFFFFFF); + carb_random_ram_cfg.para0_h_e = (para0_temp >> 32) & 0xFFFFFFFF; + + carb_random_ram_cfg.para1_e = ((p_random_ram_e->p2 - p_random_ram_e->p1) << DPP_CAR_RANDOM_OFFSET_VAL) / 100; + + para2_temp = ((ZXIC_UINT64)((((ZXIC_UINT64)(p_random_ram_e->t3)) - ((ZXIC_UINT64)(p_random_ram_e->t2))) * ((ZXIC_UINT64)(p_random_ram_e->p2))) << DPP_CAR_RANDOM_OFFSET_VAL) / 100; + carb_random_ram_cfg.para2_l_e = (para2_temp & 0xFFFFFFFF); + carb_random_ram_cfg.para2_h_e = (para2_temp >> 32) & 0xFFFFFFFF; + + carb_random_ram_cfg.para3_e = ((p_random_ram_e->p3 - p_random_ram_e->p2) << DPP_CAR_RANDOM_OFFSET_VAL) / 100; + + para4_temp = ((ZXIC_UINT64)((((ZXIC_UINT64)(p_random_ram_e->tc)) - ((ZXIC_UINT64)(p_random_ram_e->t3))) * ((ZXIC_UINT64)(p_random_ram_e->p3))) << DPP_CAR_RANDOM_OFFSET_VAL) / 100; + carb_random_ram_cfg.para4_l_e = (para4_temp & 0xFFFFFFFF); + carb_random_ram_cfg.para4_h_e = (para4_temp >> 32) & 0xFFFFFFFF; + + carb_random_ram_cfg.para5_e = ((100 - p_random_ram_e->p3) << DPP_CAR_RANDOM_OFFSET_VAL) / 100; + carb_random_ram_cfg.para6_e = p_random_ram_e->t1; + carb_random_ram_cfg.para7_e = p_random_ram_e->t2; + carb_random_ram_cfg.para8_e = p_random_ram_e->t3; + + /* para0_temp = 0; + para2_temp = 0; + para4_temp = 0; */ + + para0_temp = ((ZXIC_UINT64)((((ZXIC_UINT64)(p_random_ram_c->t2)) - ((ZXIC_UINT64)(p_random_ram_c->t1))) * ((ZXIC_UINT64)(p_random_ram_c->p1))) << DPP_CAR_RANDOM_OFFSET_VAL) / 100; + carb_random_ram_cfg.para0_l_c = (para0_temp & 0xFFFFFFFF); + carb_random_ram_cfg.para0_h_c = (para0_temp >> 32) & 0xFFFFFFFF; + + carb_random_ram_cfg.para1_c = ((p_random_ram_c->p2 - p_random_ram_c->p1) << DPP_CAR_RANDOM_OFFSET_VAL) / 100; + + para2_temp = ((ZXIC_UINT64)((((ZXIC_UINT64)(p_random_ram_c->t3)) - ((ZXIC_UINT64)(p_random_ram_c->t2))) * ((ZXIC_UINT64)(p_random_ram_c->p2))) << DPP_CAR_RANDOM_OFFSET_VAL) / 100; + carb_random_ram_cfg.para2_l_c = (para2_temp & 0xFFFFFFFF); + carb_random_ram_cfg.para2_h_c = (para2_temp >> 32) & 0xFFFFFFFF; + + carb_random_ram_cfg.para3_c = ((p_random_ram_c->p3 - p_random_ram_c->p2) << DPP_CAR_RANDOM_OFFSET_VAL) / 100; + + para4_temp = ((ZXIC_UINT64)((((ZXIC_UINT64)(p_random_ram_c->tc)) - ((ZXIC_UINT64)(p_random_ram_c->t3))) * ((ZXIC_UINT64)(p_random_ram_c->p3))) << DPP_CAR_RANDOM_OFFSET_VAL) / 100; + carb_random_ram_cfg.para4_l_c = (para4_temp & 0xFFFFFFFF); + carb_random_ram_cfg.para4_h_c = (para4_temp >> 32) & 0xFFFFFFFF; + + carb_random_ram_cfg.para5_c = ((100 - p_random_ram_c->p3) << DPP_CAR_RANDOM_OFFSET_VAL) / 100; + carb_random_ram_cfg.para6_c = p_random_ram_c->t1; + carb_random_ram_cfg.para7_c = p_random_ram_c->t2; + carb_random_ram_cfg.para8_c = p_random_ram_c->t3; + + rc = dpp_reg_write(dev, + STAT_CAR0_CARB_RANDOM_RAMr , + 0, + profile_id, + &carb_random_ram_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write"); + + return rc; +} + +/***********************************************************/ +/** +* @param dev_id +* @param p_random_ram +* +* @return +* @remark 无 +* @see +* @author YXH @date 2019/04/01 +************************************************************/ +DPP_STATUS dpp_stat_carb_random_ram_get(DPP_DEV_T *dev, + ZXIC_UINT32 profile_id, + DPP_CAR_RANDOM_RAM_T *p_random_ram_e, + DPP_CAR_RANDOM_RAM_T *p_random_ram_c) +{ + DPP_STATUS rc = DPP_OK; + DPP_STAT_CAR0_CARB_RANDOM_RAM_T carb_random_ram_cfg = {0}; + ZXIC_UINT32 tmp_val = 0; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_random_ram_e); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_random_ram_c); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0, DPP_CAR_B_PROFILE_ID_RANDOM_MAX); + + rc = dpp_reg_read(dev, + STAT_CAR0_CARB_RANDOM_RAMr , + 0, + profile_id, + &carb_random_ram_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + + p_random_ram_e->t1 = carb_random_ram_cfg.para6_e; + p_random_ram_e->t2 = carb_random_ram_cfg.para7_e; + p_random_ram_e->t3 = carb_random_ram_cfg.para8_e; + tmp_val = (carb_random_ram_cfg.para5_e * 100) >> DPP_CAR_RANDOM_OFFSET_VAL; + p_random_ram_e->p3 = 100 - tmp_val; + tmp_val = (carb_random_ram_cfg.para3_e * 100) >> DPP_CAR_RANDOM_OFFSET_VAL; + p_random_ram_e->p2 = p_random_ram_e->p3 - tmp_val; + tmp_val = (carb_random_ram_cfg.para1_e * 100) >> DPP_CAR_RANDOM_OFFSET_VAL; + p_random_ram_e->p1 = p_random_ram_e->p2 - tmp_val; + + p_random_ram_c->t1 = carb_random_ram_cfg.para6_c; + p_random_ram_c->t2 = carb_random_ram_cfg.para7_c; + p_random_ram_c->t3 = carb_random_ram_cfg.para8_c; + tmp_val = (carb_random_ram_cfg.para5_c * 100) >> DPP_CAR_RANDOM_OFFSET_VAL; + p_random_ram_c->p3 = 100 - tmp_val; + tmp_val = (carb_random_ram_cfg.para3_c * 100) >> DPP_CAR_RANDOM_OFFSET_VAL; + p_random_ram_c->p2 = p_random_ram_c->p3 - tmp_val; + tmp_val = (carb_random_ram_cfg.para1_c * 100) >> DPP_CAR_RANDOM_OFFSET_VAL; + p_random_ram_c->p1 = p_random_ram_c->p2 - tmp_val; + + return rc; +} + +/***********************************************************/ +/** car C的流设置 +* @param dev_id 设备号 car编号 +* @param flow_id 流号 +* @param drop_flag 丢弃标志 +* @param plcr_en 监管使能 +* @param profile_id 监管模板号 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/04/05 +************************************************************/ +DPP_STATUS dpp_stat_carc_queue_cfg_set(DPP_DEV_T *dev, + ZXIC_UINT32 flow_id, + ZXIC_UINT32 drop_flag, + ZXIC_UINT32 plcr_en, + ZXIC_UINT32 profile_id) +{ + DPP_STATUS rc = DPP_OK; + + DPP_STAT_CAR0_CARC_QUEUE_RAM0_159_0_T queue_cfg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_C_FLOW_ID_MAX); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), drop_flag, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), plcr_en, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0, DPP_CAR_C_PROFILE_ID_MAX); + + queue_cfg.carc_drop = drop_flag; + queue_cfg.carc_plcr_en = plcr_en; + queue_cfg.carc_profile_id = profile_id; + + rc = dpp_reg_write(dev, + STAT_CAR0_CARC_QUEUE_RAM0_159_0r , + 0, + flow_id, + &queue_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write"); + + return rc; +} + +/***********************************************************/ +/** 获取car C的流设置 +* @param dev_id 设备号 car编号 +* @param flow_id 流号 +* @param p_carc_queue_cfg car c流配置信息 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/04/05 +************************************************************/ +DPP_STATUS dpp_stat_carc_queue_cfg_get(DPP_DEV_T *dev, + ZXIC_UINT32 flow_id, + DPP_STAT_CAR_C_QUEUE_CFG_T *p_carc_queue_cfg) +{ + DPP_STATUS rc = DPP_OK; + + DPP_STAT_CAR0_CARC_QUEUE_RAM0_159_0_T queue_cfg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_C_FLOW_ID_MAX); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_carc_queue_cfg); + + rc = dpp_reg_read(dev, + STAT_CAR0_CARC_QUEUE_RAM0_159_0r, + 0, + flow_id, + &queue_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + + p_carc_queue_cfg->flow_id = flow_id; + p_carc_queue_cfg->drop_flag = queue_cfg.carc_drop; + p_carc_queue_cfg->plcr_en = queue_cfg.carc_plcr_en; + p_carc_queue_cfg->profile_id = queue_cfg.carc_profile_id; + + p_carc_queue_cfg->tq = ZXIC_COMM_COUNTER64_BUILD(queue_cfg.carc_tq_h, queue_cfg.carc_tq_l); + + p_carc_queue_cfg->tce_flag = queue_cfg.carc_ted; + p_carc_queue_cfg->tce = queue_cfg.carc_tcd; + p_carc_queue_cfg->te = queue_cfg.carc_tei; + p_carc_queue_cfg->tc = queue_cfg.carc_tci; + + return rc; +} + +/***********************************************************/ +/** car C监管模板设定 +* @param dev_id 设备号 car编号 +* @param profile_id 监管模板号 +* @param p_carc_profile_cfg 监管模板配置 +* pkt_sign 包限速标记写死成0，防止用户在carC包限速 +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/04/05 +************************************************************/ +DPP_STATUS dpp_stat_carc_profile_cfg_set(DPP_DEV_T *dev, + ZXIC_UINT32 profile_id, + DPP_STAT_CAR_PROFILE_CFG_T *p_carc_profile_cfg) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_UINT32 i = 0; + + DPP_STAT_CAR0_CARC_PROFILE_RAM1_255_0_T profile_cfg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0, DPP_CAR_C_PROFILE_ID_MAX); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_carc_profile_cfg); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carc_profile_cfg->pkt_sign, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carc_profile_cfg->cf, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carc_profile_cfg->cm, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carc_profile_cfg->random_disc_e, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carc_profile_cfg->random_disc_c, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carc_profile_cfg->cd, CAR_CD_MODE_SRTCM, CAR_CD_MODE_INVALID - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carc_profile_cfg->cir, 0, DPP_CAR_MAX_CIR_VALUE); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carc_profile_cfg->eir, 0, DPP_CAR_MAX_EIR_VALUE); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carc_profile_cfg->cbs, 0, DPP_CAR_MAX_CBS_VALUE); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carc_profile_cfg->ebs, 0, DPP_CAR_MAX_EBS_VALUE); + + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carc_profile_cfg->e_yellow_pri[0], 0, DPP_CAR_MAX_PRI_VALUE); + + for (i = 1; i < DPP_CAR_PRI_MAX; i++) + { + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carc_profile_cfg->c_pri[i], 0, DPP_CAR_MAX_PRI_VALUE); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carc_profile_cfg->e_green_pri[i], 0, DPP_CAR_MAX_PRI_VALUE); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carc_profile_cfg->e_yellow_pri[i], 0, DPP_CAR_MAX_PRI_VALUE); + } + + profile_cfg.carc_e_y_pri7 = p_carc_profile_cfg->e_yellow_pri[7]; + profile_cfg.carc_e_y_pri6 = p_carc_profile_cfg->e_yellow_pri[6]; + profile_cfg.carc_e_y_pri5 = p_carc_profile_cfg->e_yellow_pri[5]; + profile_cfg.carc_e_y_pri4 = p_carc_profile_cfg->e_yellow_pri[4]; + profile_cfg.carc_e_y_pri3 = p_carc_profile_cfg->e_yellow_pri[3]; + profile_cfg.carc_e_y_pri2 = p_carc_profile_cfg->e_yellow_pri[2]; + profile_cfg.carc_e_y_pri1 = p_carc_profile_cfg->e_yellow_pri[1]; + profile_cfg.carc_e_y_pri0 = p_carc_profile_cfg->e_yellow_pri[0]; + + profile_cfg.carc_e_g_pri7 = p_carc_profile_cfg->e_green_pri[7]; + profile_cfg.carc_e_g_pri6 = p_carc_profile_cfg->e_green_pri[6]; + profile_cfg.carc_e_g_pri5 = p_carc_profile_cfg->e_green_pri[5]; + profile_cfg.carc_e_g_pri4 = p_carc_profile_cfg->e_green_pri[4]; + profile_cfg.carc_e_g_pri3 = p_carc_profile_cfg->e_green_pri[3]; + profile_cfg.carc_e_g_pri2 = p_carc_profile_cfg->e_green_pri[2]; + profile_cfg.carc_e_g_pri1 = p_carc_profile_cfg->e_green_pri[1]; + + profile_cfg.carc_c_pri7 = p_carc_profile_cfg->c_pri[7]; + profile_cfg.carc_c_pri6 = p_carc_profile_cfg->c_pri[6]; + profile_cfg.carc_c_pri5 = p_carc_profile_cfg->c_pri[5]; + profile_cfg.carc_c_pri4 = p_carc_profile_cfg->c_pri[4]; + profile_cfg.carc_c_pri3 = p_carc_profile_cfg->c_pri[3]; + profile_cfg.carc_c_pri2 = p_carc_profile_cfg->c_pri[2]; + profile_cfg.carc_c_pri1 = p_carc_profile_cfg->c_pri[1]; + + profile_cfg.carc_cbs = p_carc_profile_cfg->cbs; + profile_cfg.carc_ebs_pbs = p_carc_profile_cfg->ebs; + profile_cfg.carc_cir = p_carc_profile_cfg->cir; + profile_cfg.carc_eir = p_carc_profile_cfg->eir; + + profile_cfg.carc_cd = p_carc_profile_cfg->cd; + profile_cfg.carc_cf = p_carc_profile_cfg->cf; + profile_cfg.carc_cm = p_carc_profile_cfg->cm; + profile_cfg.carc_random_discard_en_e = p_carc_profile_cfg->random_disc_e; + profile_cfg.carc_random_discard_en_c = p_carc_profile_cfg->random_disc_c; + /* C级car包限速标记写死为0，以免用户配置成1对CARC进行包限速 */ + profile_cfg.carc_pkt_sign = 0; + + profile_cfg.carc_profile_wr = 0; + + rc = dpp_reg_write(dev, + STAT_CAR0_CARC_PROFILE_RAM1_255_0r , + 0, + profile_id, + &profile_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write"); + + return rc; +} + + +/***********************************************************/ +/** 获取car C的监管模板配置 +* @param dev_id 设备号 car编号 +* @param profile_id 监管模板号 +* @param p_carc_profile_cfg 监管模板配置 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/04/05 +************************************************************/ +DPP_STATUS dpp_stat_carc_profile_cfg_get(DPP_DEV_T *dev, + ZXIC_UINT32 profile_id, + DPP_STAT_CAR_PROFILE_CFG_T *p_carc_profile_cfg) +{ + DPP_STATUS rc = DPP_OK; + DPP_STAT_CAR0_CARC_PROFILE_RAM1_255_0_T profile_cfg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0, DPP_CAR_C_PROFILE_ID_MAX); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_carc_profile_cfg); + + rc = dpp_reg_read(dev, + STAT_CAR0_CARC_PROFILE_RAM1_255_0r, + 0, + profile_id, + &profile_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + + p_carc_profile_cfg->profile_id = profile_id; + p_carc_profile_cfg->pkt_sign = profile_cfg.carc_pkt_sign; + p_carc_profile_cfg->cd = profile_cfg.carc_cd; + p_carc_profile_cfg->cf = profile_cfg.carc_cf; + p_carc_profile_cfg->cm = profile_cfg.carc_cm; + + p_carc_profile_cfg->eir = profile_cfg.carc_eir; + p_carc_profile_cfg->cir = profile_cfg.carc_cir; + p_carc_profile_cfg->ebs = profile_cfg.carc_ebs_pbs; + p_carc_profile_cfg->cbs = profile_cfg.carc_cbs; + + p_carc_profile_cfg->random_disc_e = profile_cfg.carc_random_discard_en_e; + p_carc_profile_cfg->random_disc_c = profile_cfg.carc_random_discard_en_c; + + p_carc_profile_cfg->c_pri[1] = profile_cfg.carc_c_pri1; + p_carc_profile_cfg->c_pri[2] = profile_cfg.carc_c_pri2; + p_carc_profile_cfg->c_pri[3] = profile_cfg.carc_c_pri3; + p_carc_profile_cfg->c_pri[4] = profile_cfg.carc_c_pri4; + p_carc_profile_cfg->c_pri[5] = profile_cfg.carc_c_pri5; + p_carc_profile_cfg->c_pri[6] = profile_cfg.carc_c_pri6; + p_carc_profile_cfg->c_pri[7] = profile_cfg.carc_c_pri7; + + p_carc_profile_cfg->e_green_pri[1] = profile_cfg.carc_e_g_pri1; + p_carc_profile_cfg->e_green_pri[2] = profile_cfg.carc_e_g_pri2; + p_carc_profile_cfg->e_green_pri[3] = profile_cfg.carc_e_g_pri3; + p_carc_profile_cfg->e_green_pri[4] = profile_cfg.carc_e_g_pri4; + p_carc_profile_cfg->e_green_pri[5] = profile_cfg.carc_e_g_pri5; + p_carc_profile_cfg->e_green_pri[6] = profile_cfg.carc_e_g_pri6; + p_carc_profile_cfg->e_green_pri[7] = profile_cfg.carc_e_g_pri7; + + p_carc_profile_cfg->e_yellow_pri[0] = profile_cfg.carc_e_y_pri0; + p_carc_profile_cfg->e_yellow_pri[1] = profile_cfg.carc_e_y_pri1; + p_carc_profile_cfg->e_yellow_pri[2] = profile_cfg.carc_e_y_pri2; + p_carc_profile_cfg->e_yellow_pri[3] = profile_cfg.carc_e_y_pri3; + p_carc_profile_cfg->e_yellow_pri[4] = profile_cfg.carc_e_y_pri4; + p_carc_profile_cfg->e_yellow_pri[5] = profile_cfg.carc_e_y_pri5; + p_carc_profile_cfg->e_yellow_pri[6] = profile_cfg.carc_e_y_pri6; + p_carc_profile_cfg->e_yellow_pri[7] = profile_cfg.carc_e_y_pri7; + + return rc; +} + +/***********************************************************/ +/** 配置car C的qvos溢出模式 +* @param dev_id 设备号 car编号 +* @param flow_id 流号 +* @param qvos_mode 溢出模式，参见DPP_CAR_QVOS_MODE_E +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/04/06 +************************************************************/ +DPP_STATUS dpp_stat_carc_queue_qvos_set(DPP_DEV_T *dev, + ZXIC_UINT32 flow_id, + ZXIC_UINT32 qvos_mode) +{ + DPP_STATUS rc = DPP_OK; + DPP_STAT_CAR0_CARC_QOVS_RAM_RAM2_T qvos_cfg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_C_FLOW_ID_MAX); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), qvos_mode, CAR_QVOS_MODE_OVERFLOW_0, CAR_QVOS_MODE_OVERFLOW_MAX - 1); + + qvos_cfg.carc_qovs = qvos_mode; + + rc = dpp_reg_write(dev, + STAT_CAR0_CARC_QOVS_RAM_RAM2r, + 0, + flow_id, + &qvos_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write"); + + return rc; +} +/***********************************************************/ +/** 获取car C的qvos溢出模式 +* @param dev_id 设备号 car编号 +* @param flow_id 流号 +* @param p_qvos_mode qvos溢出模式 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/04/06 +************************************************************/ +DPP_STATUS dpp_stat_carc_queue_qvos_get(DPP_DEV_T *dev, + ZXIC_UINT32 flow_id, + ZXIC_UINT32 *p_qvos_mode) +{ + DPP_STATUS rc = DPP_OK; + DPP_STAT_CAR0_CARC_QOVS_RAM_RAM2_T qvos_cfg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_C_FLOW_ID_MAX); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_qvos_mode); + + rc = dpp_reg_read(dev, + STAT_CAR0_CARC_QOVS_RAM_RAM2r , + 0, + flow_id, + &qvos_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + + *p_qvos_mode = qvos_cfg.carc_qovs; + + return rc; +} + +#if 0 +/***********************************************************/ +/** car C指定队列模式配置，仅用于调试 +* @param dev_id 设备号 car编号 +* @param global_en 全局队列使能，0-不使能，1-使能 +* @param sp_en 优先级队列使能，0-不使能，1-使能 +* @param appoint_sp 指定的优先级 +* @param appoint_queue 指定的队列号 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/04/06 +************************************************************/ +DPP_STATUS dpp_stat_carc_queue_appoint_mode_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 global_en, + ZXIC_UINT32 sp_en, + ZXIC_UINT32 appoint_sp, + ZXIC_UINT32 appoint_queue) +{ + DPP_STATUS rc = DPP_OK; + DPP_STAT_CAR0_CARC_APPOINT_QNUM_OR_SP_T appoint_cfg = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, global_en, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, sp_en, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, appoint_sp, DPP_CAR_PRI0, DPP_CAR_PRI_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, appoint_queue, 0, DPP_CAR_C_FLOW_ID_MAX); + + appoint_cfg.carc_appoint_qnum_or_not = global_en; + appoint_cfg.carc_appoint_sp_or_not = sp_en; + appoint_cfg.carc_plcr_stat_sp = appoint_sp; + appoint_cfg.carc_plcr_stat_qnum = appoint_queue; + + rc = dpp_reg_write(dev_id, + STAT_CAR0_CARC_APPOINT_QNUM_OR_SPr , + 0, + 0, + &appoint_cfg); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_reg_write"); + + return rc; +} + +/***********************************************************/ +/** 获取car C指定队列模式的配置 +* @param dev_id 设备号 car编号 +* @param p_global_en 全局队列使能，0-不使能，1-使能 +* @param p_sp_en 优先级队列使能，0-不使能，1-使能 +* @param p_appoint_sp 指定的优先级 +* @param p_appoint_queue 指定的队列号 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/04/07 +************************************************************/ +DPP_STATUS dpp_stat_carc_queue_appoint_mode_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *p_global_en, + ZXIC_UINT32 *p_sp_en, + ZXIC_UINT32 *p_appoint_sp, + ZXIC_UINT32 *p_appoint_queue) +{ + DPP_STATUS rc = DPP_OK; + + DPP_STAT_CAR0_CARC_APPOINT_QNUM_OR_SP_T appoint_cfg = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_global_en); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_sp_en); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_appoint_sp); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_appoint_queue); + + rc = dpp_reg_read(dev_id, + STAT_CAR0_CARC_APPOINT_QNUM_OR_SPr , + 0, + 0, + &appoint_cfg); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_reg_read"); + + *p_global_en = appoint_cfg.carc_appoint_qnum_or_not; + *p_sp_en = appoint_cfg.carc_appoint_sp_or_not; + *p_appoint_sp = appoint_cfg.carc_plcr_stat_sp; + *p_appoint_queue = appoint_cfg.carc_plcr_stat_qnum; + + return rc; +} + +/***********************************************************/ +/** car C 调试计数读取模式配置 +* @param dev_id 设备号 car编号 +* @param overflow_mode 溢出模式，0-计数最大保持，1-计数最大翻转 +* @param rd_mode 读取模式，0-不读清，1-读清模式 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/04/06 +************************************************************/ +DPP_STATUS dpp_stat_carc_dbg_cnt_mode_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 overflow_mode, + ZXIC_UINT32 rd_mode) +{ + DPP_STATUS rc = DPP_OK; + DPP_STAT_CAR0_CARC_CFGMT_COUNT_MODE_T cnt_mode_cfg = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, overflow_mode, CAR_KEEP_COUNT, CAR_RE_COUNT); + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, rd_mode, CAR_READ_NOT_CLEAR, CAR_READ_AND_CLEAR); + + cnt_mode_cfg.carc_cfgmt_count_overflow_mode = overflow_mode; + cnt_mode_cfg.carc_cfgmt_count_rd_mode = rd_mode; + + rc = dpp_reg_write(dev_id, + STAT_CAR0_CARC_CFGMT_COUNT_MODEr , + 0, + 0, + &cnt_mode_cfg); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_reg_write"); + + return rc; +} + +/***********************************************************/ +/** car C 调试计数读取模式获取 +* @param dev_id 设备号 car编号 +* @param p_overflow_mode 溢出模式，0-计数最大保持，1-计数最大翻转 +* @param p_rd_mode 读清模式，0-不读清，1-读清模式 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/04/06 +************************************************************/ +DPP_STATUS dpp_stat_carc_dbg_cnt_mode_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *p_overflow_mode, + ZXIC_UINT32 *p_rd_mode) +{ + DPP_STATUS rc = DPP_OK; + DPP_STAT_CAR0_CARC_CFGMT_COUNT_MODE_T cnt_mode_cfg = {0}; + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_overflow_mode); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_rd_mode); + + rc = dpp_reg_read(dev_id, + STAT_CAR0_CARC_CFGMT_COUNT_MODEr , + 0, + 0, + &cnt_mode_cfg); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_reg_read"); + + *p_overflow_mode = cnt_mode_cfg.carc_cfgmt_count_overflow_mode; + *p_rd_mode = cnt_mode_cfg.carc_cfgmt_count_rd_mode; + + return rc; +} + +/***********************************************************/ +/** car b 的调试计数获取 +* @param dev_id +* @param p_car_dbg_cnt +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/09/27 +************************************************************/ +DPP_STATUS dpp_stat_carc_dbg_cnt_get(ZXIC_UINT32 dev_id, + DPP_STAT_CAR_DBG_CNT_T *p_car_dbg_cnt) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_UINT32 i = 0; + ZXIC_UINT32 size = 0; + ZXIC_UINT32 *p_tmp_cnt = NULL; + + DPP_STAT_CAR0_CARC_PKT_SIZE_CNT_T carc_pkt_size_cnt_cfg = {0}; + DPP_STAT_CAR0_CARC_PKT_DES_I_CNT_T carc_pkt_in_total_cnt_cfg = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_car_dbg_cnt); + + size = sizeof(DPP_STAT_CAR_DBG_CNT_T) / sizeof(ZXIC_UINT32) - 1; + p_tmp_cnt = (ZXIC_UINT32 *)p_car_dbg_cnt; + + for (i = 0; i < size; i++) + { + rc = dpp_reg_read(dev_id, + STAT_CAR0_CARC_PKT_DES_I_CNTr + i, + 0, + 0, + &carc_pkt_in_total_cnt_cfg); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_reg_read"); + + ZXIC_COMM_MEMCPY(p_tmp_cnt + i, &(carc_pkt_in_total_cnt_cfg.carc_pkt_des_i_cnt), sizeof(ZXIC_UINT32)); + } + + rc = dpp_reg_read(dev_id, + STAT_CAR0_CARC_PKT_SIZE_CNTr, + 0, + 0, + &carc_pkt_size_cnt_cfg); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_reg_read"); + + p_car_dbg_cnt->pkt_size_cnt = carc_pkt_size_cnt_cfg.carc_pkt_size_cnt; + + return rc; +} + +/***********************************************************/ +/** 获取car C的初始化状态 +* @param dev_id 设备号 car编号 +* @param p_init_done 初始化完成使能 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/04/06 +************************************************************/ +DPP_STATUS dpp_stat_carc_init_done_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *p_init_done) +{ + DPP_STATUS rc = DPP_OK; + DPP_STAT_CAR0_CARC_PLCR_INIT_DONT_T carc_init_done_cfg = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_init_done); + + rc = dpp_reg_read(dev_id, + STAT_CAR0_CARC_PLCR_INIT_DONTr , + 0, + 0, + &carc_init_done_cfg); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_reg_read"); + + *p_init_done = carc_init_done_cfg.carc_plcr_init_done; + + return rc; +} + +#endif +/***********************************************************/ +/** +* @param dev_id +* @param profile_id +* @param p_random_ram +* +* @return +* @remark 无 +* @see +* @author YXH @date 2019/04/01 +************************************************************/ +DPP_STATUS dpp_stat_carc_random_ram_set(DPP_DEV_T *dev, + ZXIC_UINT32 profile_id, + DPP_CAR_RANDOM_RAM_T *p_random_ram_e, + DPP_CAR_RANDOM_RAM_T *p_random_ram_c) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_UINT64 para0_temp = 0; + ZXIC_UINT64 para2_temp = 0; + ZXIC_UINT64 para4_temp = 0; + DPP_STAT_CAR0_CARC_RANDOM_RAM_T carc_random_ram_cfg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_random_ram_e); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_random_ram_e->p1, 0, 100); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_random_ram_e->p2, 0, 100); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_random_ram_e->p3, 0, 100); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_random_ram_c); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_random_ram_c->p1, 0, 100); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_random_ram_c->p2, 0, 100); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_random_ram_c->p3, 0, 100); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0, DPP_CAR_C_PROFILE_ID_RANDOM_MAX); + + para0_temp = ((ZXIC_UINT64)((((ZXIC_UINT64)(p_random_ram_e->t2)) - ((ZXIC_UINT64)(p_random_ram_e->t1))) * ((ZXIC_UINT64)(p_random_ram_e->p1))) << DPP_CAR_RANDOM_OFFSET_VAL) / 100; + carc_random_ram_cfg.para0_l_e = (para0_temp & 0xFFFFFFFF); + carc_random_ram_cfg.para0_h_e = (para0_temp >> 32) & 0xFFFFFFFF; + + carc_random_ram_cfg.para1_e = ((p_random_ram_e->p2 - p_random_ram_e->p1) << DPP_CAR_RANDOM_OFFSET_VAL) / 100; + + para2_temp = ((ZXIC_UINT64)((((ZXIC_UINT64)(p_random_ram_e->t3)) - ((ZXIC_UINT64)(p_random_ram_e->t2))) * ((ZXIC_UINT64)(p_random_ram_e->p2))) << DPP_CAR_RANDOM_OFFSET_VAL) / 100; + carc_random_ram_cfg.para2_l_e = (para2_temp & 0xFFFFFFFF); + carc_random_ram_cfg.para2_h_e = (para2_temp >> 32) & 0xFFFFFFFF; + + carc_random_ram_cfg.para3_e = ((p_random_ram_e->p3 - p_random_ram_e->p2) << DPP_CAR_RANDOM_OFFSET_VAL) / 100; + + para4_temp = ((ZXIC_UINT64)((((ZXIC_UINT64)(p_random_ram_e->tc)) - ((ZXIC_UINT64)(p_random_ram_e->t3))) * ((ZXIC_UINT64)(p_random_ram_e->p3))) << DPP_CAR_RANDOM_OFFSET_VAL) / 100; + carc_random_ram_cfg.para4_l_e = (para4_temp & 0xFFFFFFFF); + carc_random_ram_cfg.para4_h_e = (para4_temp >> 32) & 0xFFFFFFFF; + + carc_random_ram_cfg.para5_e = ((100 - p_random_ram_e->p3) << DPP_CAR_RANDOM_OFFSET_VAL) / 100; + carc_random_ram_cfg.para6_e = p_random_ram_e->t1; + carc_random_ram_cfg.para7_e = p_random_ram_e->t2; + carc_random_ram_cfg.para8_e = p_random_ram_e->t3; + + /* para0_temp = 0; + para2_temp = 0; + para4_temp = 0; */ + + para0_temp = ((ZXIC_UINT64)((((ZXIC_UINT64)(p_random_ram_c->t2)) - ((ZXIC_UINT64)(p_random_ram_c->t1))) * ((ZXIC_UINT64)(p_random_ram_c->p1))) << DPP_CAR_RANDOM_OFFSET_VAL) / 100; + carc_random_ram_cfg.para0_l_c = (para0_temp & 0xFFFFFFFF); + carc_random_ram_cfg.para0_h_c = (para0_temp >> 32) & 0xFFFFFFFF; + + carc_random_ram_cfg.para1_c = ((p_random_ram_c->p2 - p_random_ram_c->p1) << DPP_CAR_RANDOM_OFFSET_VAL) / 100; + + para2_temp = ((ZXIC_UINT64)((((ZXIC_UINT64)(p_random_ram_c->t3)) - ((ZXIC_UINT64)(p_random_ram_c->t2))) * ((ZXIC_UINT64)(p_random_ram_c->p2))) << DPP_CAR_RANDOM_OFFSET_VAL) / 100; + carc_random_ram_cfg.para2_l_c = (para2_temp & 0xFFFFFFFF); + carc_random_ram_cfg.para2_h_c = (para2_temp >> 32) & 0xFFFFFFFF; + + carc_random_ram_cfg.para3_c = ((p_random_ram_c->p3 - p_random_ram_c->p2) << DPP_CAR_RANDOM_OFFSET_VAL) / 100; + + para4_temp = ((ZXIC_UINT64)((((ZXIC_UINT64)(p_random_ram_c->tc)) - ((ZXIC_UINT64)(p_random_ram_c->t3))) * ((ZXIC_UINT64)(p_random_ram_c->p3))) << DPP_CAR_RANDOM_OFFSET_VAL) / 100; + carc_random_ram_cfg.para4_l_c = (para4_temp & 0xFFFFFFFF); + carc_random_ram_cfg.para4_h_c = (para4_temp >> 32) & 0xFFFFFFFF; + + carc_random_ram_cfg.para5_c = ((100 - p_random_ram_c->p3) << DPP_CAR_RANDOM_OFFSET_VAL) / 100; + carc_random_ram_cfg.para6_c = p_random_ram_c->t1; + carc_random_ram_cfg.para7_c = p_random_ram_c->t2; + carc_random_ram_cfg.para8_c = p_random_ram_c->t3; + + rc = dpp_reg_write(dev, + STAT_CAR0_CARC_RANDOM_RAMr , + 0, + profile_id, + &carc_random_ram_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write"); + + return rc; +} + +/***********************************************************/ +/** +* @param dev_id +* @param p_random_ram +* +* @return +* @remark 无 +* @see +* @author YXH @date 2019/04/01 +************************************************************/ +DPP_STATUS dpp_stat_carc_random_ram_get(DPP_DEV_T *dev, + ZXIC_UINT32 profile_id, + DPP_CAR_RANDOM_RAM_T *p_random_ram_e, + DPP_CAR_RANDOM_RAM_T *p_random_ram_c) +{ + DPP_STATUS rc = DPP_OK; + DPP_STAT_CAR0_CARB_RANDOM_RAM_T carc_random_ram_cfg = {0}; + ZXIC_UINT32 tmp_val = 0; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_random_ram_e); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_random_ram_c); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0, DPP_CAR_C_PROFILE_ID_RANDOM_MAX); + + rc = dpp_reg_read(dev, + STAT_CAR0_CARC_RANDOM_RAMr , + 0, + profile_id, + &carc_random_ram_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + + p_random_ram_e->t1 = carc_random_ram_cfg.para6_e; + p_random_ram_e->t2 = carc_random_ram_cfg.para7_e; + p_random_ram_e->t3 = carc_random_ram_cfg.para8_e; + tmp_val = (carc_random_ram_cfg.para5_e * 100) >> DPP_CAR_RANDOM_OFFSET_VAL; + p_random_ram_e->p3 = 100 - tmp_val; + tmp_val = (carc_random_ram_cfg.para3_e * 100) >> DPP_CAR_RANDOM_OFFSET_VAL; + p_random_ram_e->p2 = p_random_ram_e->p3 - tmp_val; + tmp_val = (carc_random_ram_cfg.para1_e * 100) >> DPP_CAR_RANDOM_OFFSET_VAL; + p_random_ram_e->p1 = p_random_ram_e->p2 - tmp_val; + + p_random_ram_c->t1 = carc_random_ram_cfg.para6_c; + p_random_ram_c->t2 = carc_random_ram_cfg.para7_c; + p_random_ram_c->t3 = carc_random_ram_cfg.para8_c; + tmp_val = (carc_random_ram_cfg.para5_c * 100) >> DPP_CAR_RANDOM_OFFSET_VAL; + p_random_ram_c->p3 = 100 - tmp_val; + tmp_val = (carc_random_ram_cfg.para3_c * 100) >> DPP_CAR_RANDOM_OFFSET_VAL; + p_random_ram_c->p2 = p_random_ram_c->p3 - tmp_val; + tmp_val = (carc_random_ram_cfg.para1_c * 100) >> DPP_CAR_RANDOM_OFFSET_VAL; + p_random_ram_c->p1 = p_random_ram_c->p2 - tmp_val; + + return rc; +} + +/***********************************************************/ +/** 配置car的层级模式 +* @param dev_id +* @param mode 2 - 三级car, 第一级支持16K +* 1 - 两级car, 第一级扩展为17K +* 0 - 一级car, 第一级扩展为21K +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/09/28 +************************************************************/ +DPP_STATUS dpp_stat_car_en_mode_set(DPP_DEV_T *dev, ZXIC_UINT32 mode) +{ + DPP_STATUS rc = DPP_OK; + DPP_STAT_CAR0_CAR_HIERARCHY_MODE_T car_en_mode_cfg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), mode, DPP_CAR_EN_MODE_BOTH_EN, DPP_CAR_EN_MODE_INVALID - 1); + + car_en_mode_cfg.car_hierarchy_mode = mode; + + rc = dpp_reg_write(dev, + STAT_CAR0_CAR_HIERARCHY_MODEr , + 0, + 0, + &car_en_mode_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write"); + + return rc; +} + +/***********************************************************/ +/** +* @param dev_id +* @param p_mode +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/09/28 +************************************************************/ +DPP_STATUS dpp_stat_car_en_mode_get(DPP_DEV_T *dev, + ZXIC_UINT32 *p_mode) +{ + DPP_STATUS rc = DPP_OK; + DPP_STAT_CAR0_CAR_HIERARCHY_MODE_T car_en_mode_cfg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_mode); + + rc = dpp_reg_read(dev, + STAT_CAR0_CAR_HIERARCHY_MODEr , + 0, + 0, + &car_en_mode_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + + *p_mode = car_en_mode_cfg.car_hierarchy_mode; + + return rc; +} + +/***********************************************************/ +/** 配置car的包长偏移 +* @param dev_id +* @param pkt_size_off +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author wll @date 2019/06/06 +************************************************************/ +DPP_STATUS dpp_stat_car_pkt_size_offset_set(DPP_DEV_T *dev, + ZXIC_UINT32 pkt_size_off) +{ + DPP_STATUS rc = DPP_OK; + DPP_STAT_CAR0_PKT_SIZE_OFFSET_T car_pkt_size_offset = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), pkt_size_off, 0, 0xffffffff); + + car_pkt_size_offset.pkt_size_offset = pkt_size_off; + + rc = dpp_reg_write(dev, + STAT_CAR0_PKT_SIZE_OFFSETr, + 0, + 0, + &car_pkt_size_offset); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write"); + + return rc; +} + +/***********************************************************/ +/** 获取car的包长偏移 +* @param dev_id +* @param p_pkt_size_off +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author wll @date 2019/06/06 +************************************************************/ +DPP_STATUS dpp_stat_car_pkt_size_offset_get(DPP_DEV_T *dev, + ZXIC_UINT32 *p_pkt_size_off) +{ + DPP_STATUS rc = DPP_OK; + DPP_STAT_CAR0_PKT_SIZE_OFFSET_T car_pkt_size_offset = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_pkt_size_off); + + rc = dpp_reg_read(dev, + STAT_CAR0_PKT_SIZE_OFFSETr, + 0, + 0, + &car_pkt_size_offset); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + + *p_pkt_size_off = car_pkt_size_offset.pkt_size_offset; + + return rc; +} + +/***********************************************************/ +/** 配置cara的最大包长 +* @param dev_id +* @param max_pkt_size +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author wll @date 2019/06/06 +************************************************************/ +DPP_STATUS dpp_stat_cara_max_pkt_size_set(DPP_DEV_T *dev, + ZXIC_UINT32 max_pkt_size) +{ + DPP_STATUS rc = DPP_OK; + DPP_STAT_CAR0_MAX_PKT_SIZE_A_T car_max_pkt_size = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), max_pkt_size, 0, 0x3fff); + + car_max_pkt_size.max_pkt_size_a = max_pkt_size; + + rc = dpp_reg_write(dev, + STAT_CAR0_MAX_PKT_SIZE_Ar , + 0, + 0, + &car_max_pkt_size); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write"); + + return rc; +} + +/***********************************************************/ +/** 获取cara的最大包长 +* @param dev_id +* @param p_max_pkt_size +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author wll @date 2019/06/06 +************************************************************/ +DPP_STATUS dpp_stat_cara_max_pkt_size_get(DPP_DEV_T *dev, + ZXIC_UINT32 *p_max_pkt_size) +{ + DPP_STATUS rc = DPP_OK; + DPP_STAT_CAR0_MAX_PKT_SIZE_A_T car_max_pkt_size = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_max_pkt_size); + + rc = dpp_reg_read(dev, + STAT_CAR0_MAX_PKT_SIZE_Ar , + 0, + 0, + &car_max_pkt_size); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + + *p_max_pkt_size = car_max_pkt_size.max_pkt_size_a; + + return rc; +} + +/***********************************************************/ +/** 配置carb的最大包长 +* @param dev_id +* @param max_pkt_size +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author wll @date 2019/06/06 +************************************************************/ +DPP_STATUS dpp_stat_carb_max_pkt_size_set(DPP_DEV_T *dev, + ZXIC_UINT32 max_pkt_size) +{ + DPP_STATUS rc = DPP_OK; + DPP_STAT_CAR0_MAX_PKT_SIZE_B_T car_max_pkt_size = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), max_pkt_size, 0, 0x3fff); + + car_max_pkt_size.max_pkt_size_b = max_pkt_size; + + rc = dpp_reg_write(dev, + STAT_CAR0_MAX_PKT_SIZE_Br, + 0, + 0, + &car_max_pkt_size); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write"); + + return rc; +} + +/***********************************************************/ +/** 获取carb的最大包长 +* @param dev_id +* @param p_max_pkt_size +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author wll @date 2019/06/06 +************************************************************/ +DPP_STATUS dpp_stat_carb_max_pkt_size_get(DPP_DEV_T *dev, + ZXIC_UINT32 *p_max_pkt_size) +{ + DPP_STATUS rc = DPP_OK; + DPP_STAT_CAR0_MAX_PKT_SIZE_B_T car_max_pkt_size = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_max_pkt_size); + + rc = dpp_reg_read(dev, + STAT_CAR0_MAX_PKT_SIZE_Br, + 0, + 0, + &car_max_pkt_size); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + + *p_max_pkt_size = car_max_pkt_size.max_pkt_size_b; + + return rc; +} + +/***********************************************************/ +/** 配置carc的最大包长 +* @param dev_id +* @param max_pkt_size +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author wll @date 2019/06/06 +************************************************************/ +DPP_STATUS dpp_stat_carc_max_pkt_size_set(DPP_DEV_T *dev, + ZXIC_UINT32 max_pkt_size) +{ + DPP_STATUS rc = DPP_OK; + DPP_STAT_CAR0_MAX_PKT_SIZE_C_T car_max_pkt_size = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), max_pkt_size, 0, 0x3fff); + + car_max_pkt_size.max_pkt_size_c = max_pkt_size; + + rc = dpp_reg_write(dev, + STAT_CAR0_MAX_PKT_SIZE_Cr , + 0, + 0, + &car_max_pkt_size); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write"); + + return rc; +} + +/***********************************************************/ +/** 获取carc的最大包长 +* @param dev_id +* @param p_max_pkt_size +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author wll @date 2019/06/06 +************************************************************/ +DPP_STATUS dpp_stat_carc_max_pkt_size_get(DPP_DEV_T *dev, + ZXIC_UINT32 *p_max_pkt_size) +{ + DPP_STATUS rc = DPP_OK; + DPP_STAT_CAR0_MAX_PKT_SIZE_C_T car_max_pkt_size = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_max_pkt_size); + + rc = dpp_reg_read(dev, + STAT_CAR0_MAX_PKT_SIZE_Cr, + 0, + 0, + &car_max_pkt_size); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + + *p_max_pkt_size = car_max_pkt_size.max_pkt_size_c; + + return rc; +} + +#endif + +#if ZXIC_REAL("Advanced Function") +#if 0 +/***********************************************************/ +/** car硬件初始化 +* @param dev_id 设备号 car编号 +* @param car_type car模式，参见STAT_CAR_TYPE_E +* @param car_mono_mode car独占mono模式 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/04/27 +************************************************************/ +DPP_STATUS dpp_stat_car_hardware_init(ZXIC_UINT32 dev_id, + ZXIC_UINT32 car_type, + ZXIC_UINT32 car_mono_mode) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_UINT32 i = 0; + ZXIC_UINT32 init_done = 0; + + DPP_STAT_CAR_A_QUEUE_CFG_T car_a_queue_cfg = {0}; + DPP_STAT_CAR_B_QUEUE_CFG_T car_b_queue_cfg = {0}; + DPP_STAT_CAR_C_QUEUE_CFG_T car_c_queue_cfg = {0}; + DPP_STAT_CAR_PROFILE_CFG_T car_profile_cfg = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, car_type, STAT_CAR_A_TYPE, STAT_CAR_MAX_TYPE - 1); + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, car_mono_mode, CAR_SMMU0_MONO_MODE_NONE, CAR_SMMU0_MONO_MODE_MAX - 1); + + ZXIC_COMM_MEMSET(&car_profile_cfg, 0, sizeof(DPP_STAT_CAR_PROFILE_CFG_T)); + + rc = dpp_se_smmu0_cfg_car_mono_set(dev_id, car_mono_mode); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_se_smmu0_cfg_car_mono_set"); + + switch (car_type) + { + case STAT_CAR_A_TYPE: + { + rc = dpp_stat_cara_init_done_get(dev_id, &init_done); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_stat_cara_init_done_get"); + + if (0 == init_done) + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "Error! Get car_a init done fail!\n"); + return DPP_RC_CAR_INIT_FAIL; + } + + ZXIC_COMM_MEMSET(&car_a_queue_cfg, 0, sizeof(DPP_STAT_CAR_A_QUEUE_CFG_T)); + + /** 清空queue的配置 和绑定队列号配置 稍后补全 */ + for (i = 0; i <= DPP_CAR_A_FLOW_ID_MAX; i++) + { + rc = dpp_stat_cara_queue_cfg_set(dev_id, + i, + 0, + 0, + 0); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_stat_cara_queue_cfg_set"); + } + + /** 清空profile的配置 */ + for (i = 0; i <= DPP_CAR_A_PROFILE_ID_MAX; i++) + { + rc = dpp_stat_cara_profile_cfg_set(dev_id, + i, + &car_profile_cfg); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_stat_cara_profile_cfg_set"); + } + } + break; + + case STAT_CAR_B_TYPE: + { + rc = dpp_stat_carb_init_done_get(dev_id, &init_done); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_stat_carb_init_done_get"); + + if (0 == init_done) + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "Error! Get car_b init done fail!\n"); + return DPP_RC_CAR_INIT_FAIL; + } + + ZXIC_COMM_MEMSET(&car_b_queue_cfg, 0, sizeof(DPP_STAT_CAR_B_QUEUE_CFG_T)); + + /** 清空queue的配置 和绑定队列号配置 稍后补全 */ + + for (i = 0; i <= DPP_CAR_B_FLOW_ID_MAX; i++) + { + rc = dpp_stat_carb_queue_cfg_set(dev_id, + i, + 0, + 0, + 0); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_stat_cara_queue_cfg_set"); + } + + /** 清空profile的配置 */ + for (i = 0; i <= DPP_CAR_B_PROFILE_ID_MAX; i++) + { + rc = dpp_stat_carb_profile_cfg_set(dev_id, + i, + &car_profile_cfg); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_stat_carb_profile_cfg_set"); + } + } + break; + + case STAT_CAR_C_TYPE: + { + rc = dpp_stat_carc_init_done_get(dev_id, + &init_done); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_stat_carc_init_done_get"); + + if (0 == init_done) + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "Error! Get car_c init done fail!\n"); + return DPP_RC_CAR_INIT_FAIL; + } + + ZXIC_COMM_MEMSET(&car_c_queue_cfg, 0, sizeof(DPP_STAT_CAR_C_QUEUE_CFG_T)); + + /** 清空queue的配置 和绑定队列号配置 稍后补全 */ + + for (i = 0; i <= DPP_CAR_C_FLOW_ID_MAX; i++) + { + rc = dpp_stat_carc_queue_cfg_set(dev_id, + i, + 0, + 0, + 0); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_stat_carc_queue_cfg_set"); + } + + /** 清空profile的配置 */ + for (i = 0; i <= DPP_CAR_C_PROFILE_ID_MAX; i++) + { + rc = dpp_stat_carc_profile_cfg_set(dev_id, + i, + &car_profile_cfg); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_stat_carc_profile_cfg_set"); + } + } + break; + + default: + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "car_type[%d] error!\n", car_type); + return DPP_ERR; + } + } + + return rc; +} +#endif +/***********************************************************/ +/** car 模块流配置 +* @param dev_id 设备号 +* @param car_type car模式，参见STAT_CAR_TYPE_E +* @param flow_id 队列号 +* @param drop_flag 丢弃标志 +* @param plcr_en 限速使能 +* @param profile_id 模板编号 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/05/06 +************************************************************/ +DPP_STATUS dpp_stat_car_queue_cfg_set(DPP_DEV_T *dev, + ZXIC_UINT32 car_type, + ZXIC_UINT32 flow_id, + ZXIC_UINT32 drop_flag, + ZXIC_UINT32 plcr_en, + ZXIC_UINT32 profile_id) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_UINT32 flow_num = 0; + + DPP_CAR_SOFT_RESET_DATA_T *p_restore_data = NULL; /* 软复位相关 */ + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), car_type, STAT_CAR_A_TYPE, STAT_CAR_MAX_TYPE - 1); + + if (STAT_CAR_A_TYPE == car_type) + { + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_A_FLOW_ID_MAX); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0, DPP_CAR_A_PROFILE_ID_MAX); + } + else if (STAT_CAR_B_TYPE == car_type) + { + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_B_FLOW_ID_MAX); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0, DPP_CAR_B_PROFILE_ID_MAX); + } + else + { + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_C_FLOW_ID_MAX); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0, DPP_CAR_C_PROFILE_ID_MAX); + } + + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), drop_flag, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), plcr_en, 0, 1); + + p_restore_data = GET_DPP_CAR_SOFT_RESET_INFO(DEV_ID(dev)); /* 软复位相关 */ + + switch (car_type) + { + case STAT_CAR_A_TYPE: + { + rc = dpp_stat_cara_queue_cfg_set(dev, + flow_id, + drop_flag, + plcr_en, + profile_id); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_cara_queue_cfg_set"); + + /* 软复位相关 */ + flow_num = p_restore_data->cara_flow_num; + p_restore_data->cara_item[flow_num].flow_id = flow_id; + p_restore_data->cara_item[flow_num].profile_id = profile_id; + ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW(DEV_ID(dev), p_restore_data->cara_flow_num, 1); + p_restore_data->cara_flow_num++; + } + break; + + case STAT_CAR_B_TYPE: + { + rc = dpp_stat_carb_queue_cfg_set(dev, + flow_id, + drop_flag, + plcr_en, + profile_id); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_carb_queue_cfg_set"); + + /* 软复位相关 */ + flow_num = p_restore_data->carb_flow_num; + p_restore_data->carb_item[flow_num].flow_id = flow_id; + p_restore_data->carb_item[flow_num].profile_id = profile_id; + ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW(DEV_ID(dev), p_restore_data->carb_flow_num, 1); + p_restore_data->carb_flow_num++; + } + break; + + case STAT_CAR_C_TYPE: + { + rc = dpp_stat_carc_queue_cfg_set(dev, + flow_id, + drop_flag, + plcr_en, + profile_id); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_carc_queue_cfg_set"); + + /* 软复位相关 */ + flow_num = p_restore_data->carc_flow_num; + p_restore_data->carc_item[flow_num].flow_id = flow_id; + p_restore_data->carc_item[flow_num].profile_id = profile_id; + ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(DEV_ID(dev), p_restore_data->carc_flow_num, 1); + p_restore_data->carc_flow_num++; + } + break; + } + + return rc; +} + +/***********************************************************/ +/**队列设置参数获取 +* @param dev_id 设备号 car编号 +* @param car_type car模式，参见STAT_CAR_TYPE_E +* @param pkt_sign 限速标志，1-包限速，0-字节限速 +* @param flow_id 队列号 +* @param p_data 获取队列配置信息 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/09/27 +************************************************************/ +DPP_STATUS dpp_stat_car_queue_get(DPP_DEV_T *dev, + ZXIC_UINT32 car_type, + ZXIC_UINT32 pkt_sign, + ZXIC_UINT32 flow_id, + ZXIC_VOID *p_data) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), car_type, STAT_CAR_A_TYPE, STAT_CAR_MAX_TYPE - 1); + + if (STAT_CAR_A_TYPE == car_type) + { + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), pkt_sign, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_A_FLOW_ID_MAX); + } + else if (STAT_CAR_B_TYPE == car_type) + { + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_B_FLOW_ID_MAX); + } + else + { + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_C_FLOW_ID_MAX); + } + + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data); + + switch (car_type) + { + case STAT_CAR_A_TYPE: + { + if (0 == pkt_sign) + { + rc = dpp_stat_cara_queue_cfg_get(dev, + flow_id, + (DPP_STAT_CAR_A_QUEUE_CFG_T *)p_data); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_cara_queue_cfg_get"); + } + else + { + rc = dpp_stat_cara_pkt_queue_cfg_get(dev, + flow_id, + (DPP_STAT_CAR_A_PKT_QUEUE_CFG_T *) p_data); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_cara_pkt_queue_cfg_get"); + } + + } + break; + + case STAT_CAR_B_TYPE: + { + rc = dpp_stat_carb_queue_cfg_get(dev, + flow_id, + (DPP_STAT_CAR_B_QUEUE_CFG_T *)p_data); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_carb_queue_cfg_get"); + } + break; + + case STAT_CAR_C_TYPE: + { + rc = dpp_stat_carc_queue_cfg_get(dev, + flow_id, + (DPP_STAT_CAR_C_QUEUE_CFG_T *)p_data); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_carc_queue_cfg_get"); + } + break; + } + + return rc; +} + +/***********************************************************/ +/** car 模块流配置获取 +* @param dev_id 设备号 +* @param car_type car模式，参见STAT_CAR_TYPE_E +* @param flow_id 队列号 +* @param p_drop_flag drop标记 +* @param p_plcr_en 监管使能信号 +* @param p_profile_id 模板id +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/08/19 +************************************************************/ +DPP_STATUS dpp_stat_car_queue_cfg_get(DPP_DEV_T *dev, + ZXIC_UINT32 car_type, + ZXIC_UINT32 flow_id, + ZXIC_UINT32 *p_drop_flag, + ZXIC_UINT32 *p_plcr_en, + ZXIC_UINT32 *p_profile_id) +{ + DPP_STATUS rc = DPP_OK; + DPP_STAT_CAR_A_QUEUE_CFG_T car_a_queue_cfg = {0}; + DPP_STAT_CAR_B_QUEUE_CFG_T car_b_queue_cfg = {0}; + DPP_STAT_CAR_C_QUEUE_CFG_T car_c_queue_cfg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), car_type, STAT_CAR_A_TYPE, STAT_CAR_MAX_TYPE - 1); + + if (STAT_CAR_A_TYPE == car_type) + { + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_A_FLOW_ID_MAX); + } + else if (STAT_CAR_B_TYPE == car_type) + { + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_B_FLOW_ID_MAX); + } + else + { + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_C_FLOW_ID_MAX); + } + + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_drop_flag); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_plcr_en); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_profile_id); + + switch (car_type) + { + case STAT_CAR_A_TYPE: + { + rc = dpp_stat_cara_queue_cfg_get(dev, + flow_id, + &car_a_queue_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_cara_queue_cfg_get"); + + *p_profile_id = car_a_queue_cfg.profile_id; + *p_plcr_en = car_a_queue_cfg.plcr_en; + *p_drop_flag = car_a_queue_cfg.drop_flag; + } + break; + + case STAT_CAR_B_TYPE: + { + rc = dpp_stat_carb_queue_cfg_get(dev, + flow_id, + &car_b_queue_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_carb_queue_cfg_get"); + + *p_profile_id = car_b_queue_cfg.profile_id; + *p_plcr_en = car_b_queue_cfg.plcr_en; + *p_drop_flag = car_b_queue_cfg.drop_flag; + } + break; + + case STAT_CAR_C_TYPE: + { + rc = dpp_stat_carc_queue_cfg_get(dev, + flow_id, + &car_c_queue_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_carc_queue_cfg_get"); + + *p_profile_id = car_c_queue_cfg.profile_id; + *p_plcr_en = car_c_queue_cfg.plcr_en; + *p_drop_flag = car_c_queue_cfg.drop_flag; + } + break; + } + + return rc; +} + +/***********************************************************/ +/** car profile硬件写入 +* @param dev_id 设备号 car编号 +* @param car_type car模式，参见STAT_CAR_TYPE_E +* @param pkt_sign 限速模式，1-包限速，0-字节限速 +* @param profile_id 模板号 +* @param p_car_profile_cfg 模板配置信息 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/05/06 +************************************************************/ +DPP_STATUS dpp_stat_car_profile_cfg_set(DPP_DEV_T *dev, + ZXIC_UINT32 car_type, + ZXIC_UINT32 pkt_sign, + ZXIC_UINT32 profile_id, + ZXIC_VOID *p_car_profile_cfg) +{ + DPP_STATUS rc = DPP_OK; + + DPP_CAR_SOFT_RESET_DATA_T *p_restore_data = NULL; /* 软复位相关 */ + DPP_STAT_CAR_PROFILE_CFG_T *p_stat_car_profile_cfg = NULL; + DPP_STAT_CAR_PKT_PROFILE_CFG_T *p_stat_pkt_car_profile_cfg = NULL; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), car_type, STAT_CAR_A_TYPE, STAT_CAR_MAX_TYPE - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), pkt_sign, 0, 1); + + if (STAT_CAR_A_TYPE == car_type) + { + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0, DPP_CAR_A_PROFILE_ID_MAX); + } + else if (STAT_CAR_B_TYPE == car_type) + { + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0, DPP_CAR_B_PROFILE_ID_MAX); + } + else + { + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0, DPP_CAR_C_PROFILE_ID_MAX); + } + + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_car_profile_cfg); + + p_restore_data = GET_DPP_CAR_SOFT_RESET_INFO(DEV_ID(dev)); /* 软复位相关 */ + + if ((STAT_CAR_A_TYPE == car_type) && (1 == pkt_sign)) + { + p_stat_pkt_car_profile_cfg = (DPP_STAT_CAR_PKT_PROFILE_CFG_T *)p_car_profile_cfg; + + rc = dpp_stat_cara_pkt_profile_cfg_set(dev, + profile_id, + p_stat_pkt_car_profile_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_cara_pkt_profile_cfg_set"); + + /* 软复位相关 */ + p_restore_data->car_pkt_sign[profile_id] = ZXIC_TRUE; + + ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(DEV_ID(dev), p_restore_data->car0_pkt_num, 1); + p_restore_data->car0_pkt_num++; + } + else + { + p_stat_car_profile_cfg = (DPP_STAT_CAR_PROFILE_CFG_T *)p_car_profile_cfg; + ZXIC_COMM_TRACE_DEV_INFO(DEV_ID(dev), "==> dpp_stat_car_profile_cfg_set : \n"); + ZXIC_COMM_TRACE_DEV_INFO(DEV_ID(dev), "| %-10s | %-10s | %-10s | %-10s | \n", "profile_id", "car_id", "car_type", "pkt_sign"); + ZXIC_COMM_TRACE_DEV_INFO(DEV_ID(dev), "| %-10d | %-10d | %-10d | 0x%-8x | \n", profile_id, 0, car_type, pkt_sign); + ZXIC_COMM_TRACE_DEV_INFO(DEV_ID(dev), "| ------------------------------------------------- | \n"); + ZXIC_COMM_TRACE_DEV_INFO(DEV_ID(dev), "| %-5s | %-5s | %-5s | %-10s | %-10s | %-10s | %-10s | \n", "cd", "cf", "cm", "cir", "cbs", "eir", "ebs"); + ZXIC_COMM_TRACE_DEV_INFO(DEV_ID(dev), "| %-5d | %-5d | %-5d | %-10d | %-10d | %-10d | %-10d | \n", p_stat_car_profile_cfg->cd, + p_stat_car_profile_cfg->cf, + p_stat_car_profile_cfg->cm, + p_stat_car_profile_cfg->cir, + p_stat_car_profile_cfg->cbs, + p_stat_car_profile_cfg->eir, + p_stat_car_profile_cfg->ebs); + + if (STAT_CAR_A_TYPE == car_type) + { + rc = dpp_stat_cara_profile_cfg_set(dev, + profile_id, + p_stat_car_profile_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_cara_profile_cfg_set"); + + /* 软复位相关 */ + if (ZXIC_TRUE == p_restore_data->car_pkt_sign[profile_id]) + { + p_restore_data->car0_pkt_num--; + p_restore_data->car_pkt_sign[profile_id] = ZXIC_FALSE; + } + } + else if (STAT_CAR_B_TYPE == car_type) + { + rc = dpp_stat_carb_profile_cfg_set(dev, + profile_id, + p_stat_car_profile_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_carb_profile_cfg_set"); + } + else + { + rc = dpp_stat_carc_profile_cfg_set(dev, + profile_id, + p_stat_car_profile_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_carc_profile_cfg_set"); + } + } + + return rc; + +} + +/***********************************************************/ +/**获取监管模板配置 +* @param dev_id 设备号 +* @param car_type car模式类型，参见STAT_CAR_TYPE_E +* @param pkt_sign 限速模式，1-包限速，0-字节限速 +* @param profile_id 监管模板id +* @param p_car_profile_cfg 模板配置信息 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/08/29 +************************************************************/ +DPP_STATUS dpp_stat_car_profile_cfg_get(DPP_DEV_T *dev, + ZXIC_UINT32 car_type, + ZXIC_UINT32 pkt_sign, + ZXIC_UINT32 profile_id, + ZXIC_VOID *p_car_profile_cfg) +{ + DPP_STATUS rc = DPP_OK; + DPP_STAT_CAR_PROFILE_CFG_T *p_stat_car_profile_cfg = NULL; + DPP_STAT_CAR_PKT_PROFILE_CFG_T *p_stat_pkt_car_profile_cfg = NULL; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), car_type, STAT_CAR_A_TYPE, STAT_CAR_MAX_TYPE - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), pkt_sign, 0, 1); + + if (STAT_CAR_A_TYPE == car_type) + { + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0, DPP_CAR_A_PROFILE_ID_MAX); + } + else if (STAT_CAR_B_TYPE == car_type) + { + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0, DPP_CAR_B_PROFILE_ID_MAX); + } + else + { + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0, DPP_CAR_C_PROFILE_ID_MAX); + } + + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_car_profile_cfg); + + if ((STAT_CAR_A_TYPE == car_type) && (1 == pkt_sign)) + { + p_stat_pkt_car_profile_cfg = (DPP_STAT_CAR_PKT_PROFILE_CFG_T *)p_car_profile_cfg; + rc = dpp_stat_cara_pkt_profile_cfg_get(dev, + profile_id, + p_stat_pkt_car_profile_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_cara_pkt_profile_cfg_get"); + } + else + { + p_stat_car_profile_cfg = (DPP_STAT_CAR_PROFILE_CFG_T *)p_car_profile_cfg; + + if (STAT_CAR_A_TYPE == car_type) + { + rc = dpp_stat_cara_profile_cfg_get(dev, + profile_id, + p_stat_car_profile_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_cara_profile_cfg_get"); + } + else if (STAT_CAR_B_TYPE == car_type) + { + rc = dpp_stat_carb_profile_cfg_get(dev, + profile_id, + p_stat_car_profile_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_carb_profile_cfg_get"); + } + else + { + rc = dpp_stat_carc_profile_cfg_get(dev, + profile_id, + p_stat_car_profile_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_carc_profile_cfg_get"); + } + } + + return rc; +} + +/***********************************************************/ +/** car 队列映射关系配置 +* @param dev_id 设备号 +* @param car_type car模式类型，参见STAT_CAR_TYPE_E +* @param flow_id 队列号 +* @param map_flow_id 映射队列号 +* @param map_sp 映射sp +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/09/27 +************************************************************/ +DPP_STATUS dpp_stat_car_queue_map_set(DPP_DEV_T *dev, + ZXIC_UINT32 car_type, + ZXIC_UINT32 flow_id, + ZXIC_UINT32 map_flow_id, + ZXIC_UINT32 map_sp) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), car_type, STAT_CAR_A_TYPE, STAT_CAR_B_TYPE); + + if (STAT_CAR_A_TYPE == car_type) + { + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_A_FLOW_ID_MAX); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), map_flow_id, 0, DPP_CAR_B_FLOW_ID_MAX); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), map_sp, DPP_CAR_PRI0, DPP_CAR_PRI_MAX - 1); + rc = dpp_stat_cara_queue_map_set(dev, + flow_id, + map_flow_id, + map_sp); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_cara_queue_map_set"); + } + else + { + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_B_FLOW_ID_MAX); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), map_flow_id, 0, DPP_CAR_C_FLOW_ID_MAX); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), map_sp, DPP_CAR_PRI0, DPP_CAR_PRI_MAX - 1); + rc = dpp_stat_carb_queue_map_set(dev, + flow_id, + map_flow_id, + map_sp); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_carb_queue_map_set"); + } + + return rc; +} + +/***********************************************************/ +/** 获取 car 流号的绑定关系 +* @param dev_id 设备号 +* @param car_type car模式类型，参见STAT_CAR_TYPE_E +* @param flow_id 队列号 +* @param p_map_flow_id 映射队列号 +* @param p_map_sp 映射sp +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/09/27 +************************************************************/ +DPP_STATUS dpp_stat_car_queue_map_get(DPP_DEV_T *dev, + ZXIC_UINT32 car_type, + ZXIC_UINT32 flow_id, + ZXIC_UINT32 *p_map_flow_id, + ZXIC_UINT32 *p_map_sp) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), car_type, STAT_CAR_A_TYPE, STAT_CAR_B_TYPE); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_map_flow_id); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_map_sp); + + if (STAT_CAR_A_TYPE == car_type) + { + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_A_FLOW_ID_MAX); + rc = dpp_stat_cara_queue_map_get(dev, + flow_id, + p_map_flow_id, + p_map_sp); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_cara_queue_map_get"); + } + else + { + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_B_FLOW_ID_MAX); + rc = dpp_stat_carb_queue_map_get(dev, + flow_id, + p_map_flow_id, + p_map_sp); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_carb_queue_map_get"); + } + + return rc; +} + +/***********************************************************/ +/** +* @param dev_id 设备ID +* @param profile_id 模板ID +* @param p_random_ram_e E桶概率丢弃配置参数 +* @param p_random_ram_c C桶概率丢弃配置参数 +* +* @return +* @remark 无 +* @see +* @author YXH @date 2019/04/01 +************************************************************/ +DPP_STATUS dpp_stat_car_random_ram_set(DPP_DEV_T *dev, + ZXIC_UINT32 car_type, + ZXIC_UINT32 profile_id, + DPP_CAR_RANDOM_RAM_T *p_random_ram_e, + DPP_CAR_RANDOM_RAM_T *p_random_ram_c) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), car_type, STAT_CAR_B_TYPE, STAT_CAR_C_TYPE); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_random_ram_e); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_random_ram_c); + + if (STAT_CAR_B_TYPE == car_type) + { + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0, DPP_CAR_B_PROFILE_ID_RANDOM_MAX); + rc = dpp_stat_carb_random_ram_set(dev, + profile_id, + p_random_ram_e, + p_random_ram_c); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_carb_random_ram_set"); + } + else + { + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0, DPP_CAR_C_PROFILE_ID_RANDOM_MAX); + rc = dpp_stat_carc_random_ram_set(dev, + profile_id, + p_random_ram_e, + p_random_ram_c); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_carc_random_ram_set"); + } + + return rc; +} + +/***********************************************************/ +/** +* @param dev_id 设备ID +* @param profile_id 模板ID +* @param p_random_ram_e E桶概率丢弃配置参数 +* @param p_random_ram_c C桶概率丢弃配置参数 +* +* @return +* @remark 无 +* @see +* @author YXH @date 2019/04/01 +************************************************************/ +DPP_STATUS dpp_stat_car_random_ram_get(DPP_DEV_T *dev, + ZXIC_UINT32 car_type, + ZXIC_UINT32 profile_id, + DPP_CAR_RANDOM_RAM_T *p_random_ram_e, + DPP_CAR_RANDOM_RAM_T *p_random_ram_c) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), car_type, STAT_CAR_B_TYPE, STAT_CAR_C_TYPE); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_random_ram_e); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_random_ram_c); + + if (STAT_CAR_B_TYPE == car_type) + { + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0, DPP_CAR_B_PROFILE_ID_RANDOM_MAX); + rc = dpp_stat_carb_random_ram_get(dev, + profile_id, + p_random_ram_e, + p_random_ram_c); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_carb_random_ram_get"); + } + else + { + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0, DPP_CAR_C_PROFILE_ID_RANDOM_MAX); + rc = dpp_stat_carc_random_ram_get(dev, + profile_id, + p_random_ram_e, + p_random_ram_c); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_carc_random_ram_get"); + } + + return rc; +} + +#if 0 +/***********************************************************/ +/**car模块dbg计数模式设置 +* @param dev_id 设备号 +* @param car_type car模式类型，参见STAT_CAR_TYPE_E +* @param overflow_mode 溢出模式，0-计数最大保持，1-计数最大翻转 +* @param rd_mode 读取模式，0-不读清，1-读清模式 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/09/27 +************************************************************/ +DPP_STATUS dpp_stat_car_dbg_cnt_mode_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 car_type, + ZXIC_UINT32 overflow_mode, + ZXIC_UINT32 rd_mode) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, car_type, STAT_CAR_A_TYPE, STAT_CAR_MAX_TYPE - 1); + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, overflow_mode, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, rd_mode, 0, 1); + + switch (car_type) + { + case STAT_CAR_A_TYPE: + { + rc = dpp_stat_cara_dbg_cnt_mode_set(dev_id, + overflow_mode, + rd_mode); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_stat_cara_dbg_cnt_mode_set"); + } + break; + + case STAT_CAR_B_TYPE: + { + rc = dpp_stat_carb_dbg_cnt_mode_set(dev_id, + overflow_mode, + rd_mode); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_stat_carb_dbg_cnt_mode_set"); + } + break; + + case STAT_CAR_C_TYPE: + { + rc = dpp_stat_carc_dbg_cnt_mode_set(dev_id, + overflow_mode, + rd_mode); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_stat_carc_dbg_cnt_mode_set"); + } + break; + } + + return rc; +} + +/***********************************************************/ +/**car模块dbg计数模式获取 +* @param dev_id 设备号 +* @param car_type car模式类型，参见STAT_CAR_TYPE_E +* @param p_overflow_mode 溢出模式，0-计数最大保持，1-计数最大翻转 +* @param p_rd_mode 读取模式，0-不读清，1-读清模式 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/09/27 +************************************************************/ +DPP_STATUS dpp_stat_car_dbg_cnt_mode_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 car_type, + ZXIC_UINT32 *p_overflow_mode, + ZXIC_UINT32 *p_rd_mode) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, car_type, STAT_CAR_A_TYPE, STAT_CAR_MAX_TYPE - 1); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_overflow_mode); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_rd_mode); + + switch (car_type) + { + case STAT_CAR_A_TYPE: + { + rc = dpp_stat_cara_dbg_cnt_mode_get(dev_id, + p_overflow_mode, + p_rd_mode); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_stat_cara_dbg_cnt_mode_get"); + } + break; + + case STAT_CAR_B_TYPE: + { + rc = dpp_stat_carb_dbg_cnt_mode_get(dev_id, + p_overflow_mode, + p_rd_mode); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_stat_carb_dbg_cnt_mode_get"); + } + break; + + case STAT_CAR_C_TYPE: + { + rc = dpp_stat_carc_dbg_cnt_mode_get(dev_id, + p_overflow_mode, + p_rd_mode); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_stat_carc_dbg_cnt_mode_get"); + } + break; + } + + return rc; +} + +/***********************************************************/ +/** car 模块调试计数 获取 +* @param dev_id 设备号 +* @param car_type car模式类型，参见STAT_CAR_TYPE_E +* @param p_car_dbg_cnt dbg计数信息 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/09/27 +************************************************************/ +DPP_STATUS dpp_stat_car_dbg_cnt_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 car_type, + DPP_STAT_CAR_DBG_CNT_T *p_car_dbg_cnt) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, car_type, STAT_CAR_A_TYPE, STAT_CAR_MAX_TYPE - 1); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_car_dbg_cnt); + + switch (car_type) + { + case STAT_CAR_A_TYPE: + { + rc = dpp_stat_cara_dbg_cnt_get(dev_id, + p_car_dbg_cnt); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_stat_cara_dbg_cnt_get"); + } + break; + + case STAT_CAR_B_TYPE: + { + rc = dpp_stat_carb_dbg_cnt_get(dev_id, + p_car_dbg_cnt); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_stat_carb_dbg_cnt_get"); + } + break; + + case STAT_CAR_C_TYPE: + { + rc = dpp_stat_carc_dbg_cnt_get(dev_id, + p_car_dbg_cnt); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_stat_carc_dbg_cnt_get"); + } + break; + } + + return rc; +} +#endif +/***********************************************************/ +/** 获取最大包长 +* @param dev_id +* @param car_type +* @param p_max_pkt_len +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author wll @date 2019/06/06 +************************************************************/ +DPP_STATUS dpp_stat_car_max_pkt_size_get(DPP_DEV_T *dev, + ZXIC_UINT32 car_type, + ZXIC_UINT32 *p_max_pkt_len) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 pkt_len = 0; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), car_type, STAT_CAR_A_TYPE, STAT_CAR_MAX_TYPE - 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_max_pkt_len); + + switch (car_type) + { + case STAT_CAR_A_TYPE: + { + rc = dpp_stat_cara_max_pkt_size_get(dev, + &pkt_len); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_cara_max_pkt_size_get"); + } + break; + + case STAT_CAR_B_TYPE: + { + rc = dpp_stat_carb_max_pkt_size_get(dev, + &pkt_len); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_carb_max_pkt_size_get"); + } + break; + + case STAT_CAR_C_TYPE: + { + rc = dpp_stat_carc_max_pkt_size_get(dev, + &pkt_len); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_carc_max_pkt_size_get"); + } + break; + } + + *p_max_pkt_len = pkt_len; + + return rc; +} + +/***********************************************************/ +/** 配置最大包长 +* @param dev_id +* @param car_type +* @param max_pkt_size +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author wll @date 2019/06/06 +************************************************************/ +DPP_STATUS dpp_stat_car_max_pkt_size_set(DPP_DEV_T *dev, + ZXIC_UINT32 car_type, + ZXIC_UINT32 max_pkt_size) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), car_type, STAT_CAR_A_TYPE, STAT_CAR_MAX_TYPE - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), max_pkt_size, 0, 0x3fff); + + switch (car_type) + { + case STAT_CAR_A_TYPE: + { + rc = dpp_stat_cara_max_pkt_size_set(dev, + max_pkt_size); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_cara_max_pkt_size_set"); + } + break; + + case STAT_CAR_B_TYPE: + { + rc = dpp_stat_carb_max_pkt_size_set(dev, + max_pkt_size); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_carb_max_pkt_size_set"); + } + break; + + case STAT_CAR_C_TYPE: + { + rc = dpp_stat_carc_max_pkt_size_set(dev, + max_pkt_size); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_carc_max_pkt_size_set"); + } + break; + } + + return rc; +} + + +/***********************************************************/ +/** STAT CAR复位获取全局变量大小函数 +* @param dev_id +* @param p_size +* +* @return +* @remark 无 +* @see +* @author yxh @date 2018/06/26 +************************************************************/ +DPP_STATUS dpp_stat_car_glb_size_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_size) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_UINT32 queue_num = 0; + ZXIC_UINT32 profile_num = 0; + ZXIC_UINT32 pkt_profile_num = 0; + + DPP_CAR_SOFT_RESET_DATA_T *p_g_restore_data = NULL; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_size); + + p_g_restore_data = GET_DPP_CAR_SOFT_RESET_INFO(DEV_ID(dev)); + + if (0 == p_g_restore_data->is_init) + { + ZXIC_COMM_PRINT("Not init!!!\n"); + *p_size = sizeof(ZXIC_UINT32); + } + else + { + /* CAR A */ + ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(DEV_ID(dev), queue_num, p_g_restore_data->cara_flow_num); + queue_num += p_g_restore_data->cara_flow_num; + + /* CAR B */ + ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(DEV_ID(dev), queue_num, p_g_restore_data->carb_flow_num); + queue_num += p_g_restore_data->carb_flow_num; + + /* CAR C */ + ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(DEV_ID(dev), queue_num, p_g_restore_data->carc_flow_num); + queue_num += p_g_restore_data->carc_flow_num; + + pkt_profile_num = p_g_restore_data->car0_pkt_num; + ZXIC_COMM_CHECK_DEV_INDEX_SUB_OVERFLOW_NO_ASSERT(DEV_ID(dev), (DPP_CAR_A_PROFILE_ID_MAX + DPP_CAR_B_PROFILE_ID_MAX + DPP_CAR_C_PROFILE_ID_MAX + 3), pkt_profile_num); + profile_num = DPP_CAR_A_PROFILE_ID_MAX + DPP_CAR_B_PROFILE_ID_MAX + DPP_CAR_C_PROFILE_ID_MAX + 3 - pkt_profile_num; + /**占用的格式如下: + (ZXIC_UINT32) (ZXIC_UINT32) (ZXIC_UINT32)(CAR0) (ZXIC_UINT32)(CAR1) (ZXIC_UINT32) + is_init queue_num queue_info pkt_profile_num pkt_profile_num pkt_profile_cfg profile_num profile_cfg + */ + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(DEV_ID(dev), queue_num, ((ZXIC_UINT32)ZXIC_SIZEOF(DPP_CAR_SOFT_RESET_QUEUE_T))); + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(DEV_ID(dev), pkt_profile_num, ((ZXIC_UINT32)ZXIC_SIZEOF(DPP_STAT_CAR_PKT_PROFILE_CFG_T))); + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(DEV_ID(dev), profile_num, ((ZXIC_UINT32)ZXIC_SIZEOF(DPP_STAT_CAR_PROFILE_CFG_T))); + *p_size = ((ZXIC_UINT32)ZXIC_SIZEOF(ZXIC_UINT32)) * 5 + queue_num * ((ZXIC_UINT32)ZXIC_SIZEOF(DPP_CAR_SOFT_RESET_QUEUE_T)) + + pkt_profile_num * ((ZXIC_UINT32)ZXIC_SIZEOF(DPP_STAT_CAR_PKT_PROFILE_CFG_T)) + + profile_num * ((ZXIC_UINT32)ZXIC_SIZEOF(DPP_STAT_CAR_PROFILE_CFG_T)); + ZXIC_COMM_PRINT("glb_size = %d!!!\n", *p_size); + } + + return rc; +} + +#if 0 +/***********************************************************/ +/** STAT CAR复位设置全局变量函数 +* @param dev_id 设备号 +* @param size 大小，字节数 +* @param p_data_buff 全局变量数据 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author yxh @date 2018/06/26 +************************************************************/ +DPP_STATUS dpp_stat_car_glb_mgr_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 size, ZXIC_UINT8 *p_data_buff) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_UINT32 i = 0; + ZXIC_UINT32 j = 0; + ZXIC_UINT32 is_init = 0; + ZXIC_UINT32 queue_num = 0; + ZXIC_UINT32 profile_num = 0; + ZXIC_UINT32 cara_profile_num = 0; + ZXIC_UINT32 car0_pkt_profile_num = 0; + ZXIC_UINT32 buff_offset = 0; + ZXIC_UINT32 size_of_stat_car = 0; + + DPP_CAR_SOFT_RESET_QUEUE_T *p_car_glb_queue_info = NULL; + DPP_STAT_CAR_PROFILE_CFG_T *p_car_glb_profile_info = NULL; + DPP_STAT_CAR_PKT_PROFILE_CFG_T *p_car_glb_pkt_profile_info = NULL; + + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_data_buff); + + rc = dpp_stat_car_glb_size_get(dev_id, &size_of_stat_car); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_stat_car_glb_size_get"); + + if (size < size_of_stat_car) + { + ZXIC_COMM_TRACE_ERROR("dpp stat car glb mgr recovery, size of buffer is smaller than defaultss\n"); + return DPP_ERR; + } + + ZXIC_COMM_MEMCPY(&is_init, p_data_buff, size); + buff_offset = sizeof(ZXIC_UINT32); + + if (0 == is_init) + { + ZXIC_COMM_PRINT("Not init!!!\n"); + } + else + { + /* 获取queue的数目 */ + ZXIC_COMM_MEMCPY(&queue_num, p_data_buff + buff_offset, sizeof(ZXIC_UINT32)); + buff_offset += sizeof(ZXIC_UINT32); + p_car_glb_queue_info = (DPP_CAR_SOFT_RESET_QUEUE_T *)(p_data_buff + buff_offset); + + /* 设置flow_id的信息 */ + for (i = 0; i < queue_num; i++) + { + rc = dpp_stat_car_queue_cfg_set(dev_id, + p_car_glb_queue_info->car_type, + p_car_glb_queue_info->flow_id, + p_car_glb_queue_info->drop_flag, + p_car_glb_queue_info->plcr_en, + p_car_glb_queue_info->profile_id); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_stat_car_queue_cfg_set"); + } + + ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(dev_id, buff_offset, queue_num * ZXIC_SIZEOF(DPP_CAR_SOFT_RESET_QUEUE_T)); + buff_offset += (queue_num * ZXIC_SIZEOF(DPP_CAR_SOFT_RESET_QUEUE_T)) & 0xffffffff; + + ZXIC_COMM_MEMCPY(&car0_pkt_profile_num, p_data_buff + buff_offset, sizeof(ZXIC_UINT32)); + ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(dev_id, buff_offset, sizeof(ZXIC_UINT32)); + buff_offset += sizeof(ZXIC_UINT32); + + /* 设置pkt_frofile的信息 */ + p_car_glb_pkt_profile_info = (DPP_STAT_CAR_PKT_PROFILE_CFG_T *)(p_data_buff + buff_offset); + + for (i = 0; i < car0_pkt_profile_num; i++) + { + rc = dpp_stat_car_profile_cfg_set(dev_id, + STAT_CAR_A_TYPE, + ZXIC_TRUE, + p_car_glb_pkt_profile_info->profile_id, + p_car_glb_pkt_profile_info); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_stat_car_profile_cfg_set"); + p_car_glb_pkt_profile_info++; + } + + ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(dev_id, buff_offset, car0_pkt_profile_num * ZXIC_SIZEOF(DPP_STAT_CAR_PKT_PROFILE_CFG_T)); + buff_offset += (car0_pkt_profile_num * ZXIC_SIZEOF(DPP_STAT_CAR_PKT_PROFILE_CFG_T)) & 0xffffffff; + + ZXIC_COMM_MEMCPY(&profile_num, p_data_buff + buff_offset, sizeof(ZXIC_UINT32)); + ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(dev_id, buff_offset, sizeof(ZXIC_UINT32)); + buff_offset += sizeof(ZXIC_UINT32); + + /* 设置profile的信息 */ + p_car_glb_profile_info = (DPP_STAT_CAR_PROFILE_CFG_T *)(p_data_buff + buff_offset); + + cara_profile_num = DPP_CAR_PKT_PROFILE_ID_MAX - car0_pkt_profile_num; + + ZXIC_COMM_PRINT(">>>>>>>>>>> Set CAR_A_PROFILE info start!\n"); + + for (j = 0; j < cara_profile_num; j++) + { + rc = dpp_stat_car_profile_cfg_set(dev_id, + STAT_CAR_A_TYPE, + ZXIC_FALSE, + p_car_glb_profile_info->profile_id, + p_car_glb_profile_info); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_stat_car_profile_cfg_set"); + p_car_glb_profile_info++; + } + + ZXIC_COMM_PRINT(">>>>>>>>>>> Set car CAR_B_PROFILE info start!\n"); + + for (j = 0; j <= DPP_CAR_B_PROFILE_ID_MAX; j++) + { + rc = dpp_stat_car_profile_cfg_set(dev_id, + STAT_CAR_B_TYPE, + ZXIC_FALSE, + p_car_glb_profile_info->profile_id, + p_car_glb_profile_info); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_stat_car_profile_cfg_set"); + p_car_glb_profile_info++; + } + + ZXIC_COMM_PRINT(">>>>>>>>>>> Set car CAR_C_PROFILE info start!\n"); + + for (j = 0; j <= DPP_CAR_C_PROFILE_ID_MAX; j++) + { + rc = dpp_stat_car_profile_cfg_set(dev_id, + STAT_CAR_C_TYPE, + ZXIC_FALSE, + p_car_glb_profile_info->profile_id, + p_car_glb_profile_info); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_stat_car_profile_cfg_set"); + p_car_glb_profile_info++; + } + + }/* end (1 == is_init) */ + + return rc; +} + +/***********************************************************/ +/** STAT CAR复位获取全局变量函数 +* @param dev_id 设备号 +* @param p_flag 释放使能，1-需要手动free，0-不需要手动free +* @param p_size 数据大小 +* @param pp_data_buff 全局变量数据 +* +* @return NPE_OK-成功，NPE_ERR-失败 +* @remark 无 +* @see +* @author yxh @date 2018/06/26 +************************************************************/ +DPP_STATUS dpp_stat_car_glb_mgr_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *p_flag, + ZXIC_UINT32 *p_size, + ZXIC_UINT8 **pp_data_buff) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_UINT32 j = 0; + ZXIC_UINT32 is_init = 0; + ZXIC_UINT32 flow_num = 0; + ZXIC_UINT32 flow_num_total = 0; + ZXIC_UINT32 plcr_en = 0; + ZXIC_UINT32 drop_flag = 0; + ZXIC_UINT32 profile_id = 0; + ZXIC_UINT32 profile_num_total = 0; + ZXIC_UINT32 profile_pkt_total = 0; + ZXIC_UINT32 buff_offset = 0; + ZXIC_UINT32 size = 0; + DPP_CAR_SOFT_RESET_DATA_T *p_g_restore_data = NULL; + DPP_CAR_SOFT_RESET_QUEUE_T *p_car_glb_queue_info = NULL; + DPP_CAR_SOFT_RESET_QUEUE_T *p_car_glb_queue_info_temp = NULL; + DPP_STAT_CAR_PROFILE_CFG_T *p_car_glb_profile_info = NULL; + DPP_STAT_CAR_PROFILE_CFG_T *p_car_glb_profile_info_temp = NULL; + DPP_STAT_CAR_PKT_PROFILE_CFG_T *p_car_glb_pkt_profile_info = NULL; + DPP_STAT_CAR_PKT_PROFILE_CFG_T *p_car_glb_pkt_profile_info_temp = NULL; + + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_size); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_flag); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, pp_data_buff); + + p_g_restore_data = GET_DPP_CAR_SOFT_RESET_INFO(dev_id); + + is_init = p_g_restore_data->is_init; + + if (0 == is_init) + { + *p_size = sizeof(ZXIC_UINT32); + *p_flag = ZXIC_TRUE; + + ZXIC_COMM_PRINT(">>>>>>>>>>>[dpp_stat_car_glb_mgr_get]: No init\n"); + + *pp_data_buff = ZXIC_COMM_MALLOC(*p_size); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, *pp_data_buff); + ZXIC_COMM_MEMSET(*pp_data_buff, 0, *p_size); + + ZXIC_COMM_MEMCPY(*pp_data_buff, &is_init, sizeof(ZXIC_UINT32)); + } + else + { + ZXIC_COMM_PRINT(">>>>>>>>>>>[dpp_stat_car_glb_mgr_get]: Inited\n"); + + /** queue 绑定的信息 */ + /* CAR A */ + flow_num = p_g_restore_data->cara_flow_num; + ZXIC_COMM_TRACE_DEV_INFO(dev_id, "[dpp_stat_car_glb_mgr_get] cara_queue_num : 0x%08x\n", flow_num); + ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(dev_id, flow_num_total, flow_num); + flow_num_total += flow_num; + + /* CAR B */ + flow_num = p_g_restore_data->carb_flow_num; + ZXIC_COMM_TRACE_DEV_INFO(dev_id, "[dpp_stat_car_glb_mgr_get] carb_queue_num : 0x%08x\n", flow_num); + ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(dev_id, flow_num_total, flow_num); + flow_num_total += flow_num; + + /* CAR C */ + flow_num = p_g_restore_data->carc_flow_num; + ZXIC_COMM_TRACE_DEV_INFO(dev_id, "[dpp_stat_car_glb_mgr_get] carc_queue_num : 0x%08x\n", flow_num); + ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(dev_id, flow_num_total, flow_num); + flow_num_total += flow_num; + + profile_pkt_total = p_g_restore_data->car0_pkt_num; + ZXIC_COMM_CHECK_DEV_INDEX_SUB_OVERFLOW_NO_ASSERT(dev_id, DPP_CAR_PROFILE_ID_TOTAL, profile_pkt_total); + profile_num_total = DPP_CAR_PROFILE_ID_TOTAL - profile_pkt_total; + + /**占用的格式如下: + (ZXIC_UINT32) (ZXIC_UINT32) (ZXIC_UINT32)(CAR0) (ZXIC_UINT32)(CAR1) (ZXIC_UINT32) + is_init queue_num queue_info pkt_profile_num pkt_profile_num pkt_profile_cfg profile_num profile_cfg + */ + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, flow_num_total, ((ZXIC_UINT32)ZXIC_SIZEOF(DPP_CAR_SOFT_RESET_QUEUE_T))); + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, profile_pkt_total, ((ZXIC_UINT32)ZXIC_SIZEOF(DPP_STAT_CAR_PKT_PROFILE_CFG_T))); + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, profile_num_total, ((ZXIC_UINT32)ZXIC_SIZEOF(DPP_STAT_CAR_PROFILE_CFG_T))); + *p_size = ((ZXIC_UINT32)ZXIC_SIZEOF(ZXIC_UINT32)) * 5 + flow_num_total * ((ZXIC_UINT32)ZXIC_SIZEOF(DPP_CAR_SOFT_RESET_QUEUE_T)) + + profile_pkt_total * ((ZXIC_UINT32)ZXIC_SIZEOF(DPP_STAT_CAR_PKT_PROFILE_CFG_T)) + + profile_num_total * ((ZXIC_UINT32)ZXIC_SIZEOF(DPP_STAT_CAR_PROFILE_CFG_T)); + + /* 存放init_flag */ + *pp_data_buff = ZXIC_COMM_MALLOC(*p_size); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, *pp_data_buff); + ZXIC_COMM_MEMSET(*pp_data_buff, 0, *p_size); + ZXIC_COMM_MEMCPY(*pp_data_buff, &is_init, sizeof(ZXIC_UINT32)); + buff_offset = sizeof(ZXIC_UINT32); + + /* 存放queue_num */ + ZXIC_COMM_MEMCPY(*pp_data_buff + buff_offset, &flow_num_total, sizeof(ZXIC_UINT32)); + buff_offset += sizeof(ZXIC_UINT32); + + /* 获取、存放queue 绑定的信息 */ + if (0 != flow_num_total) + { + ZXIC_COMM_PRINT(">>>>>>>>>>>[dpp_stat_car_glb_mgr_get]: Get queue info start!\n"); + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, flow_num_total, ((ZXIC_UINT32)ZXIC_SIZEOF(DPP_CAR_SOFT_RESET_QUEUE_T))); + p_car_glb_queue_info = (DPP_CAR_SOFT_RESET_QUEUE_T *)ZXIC_COMM_MALLOC(flow_num_total * ((ZXIC_UINT32)ZXIC_SIZEOF(DPP_CAR_SOFT_RESET_QUEUE_T))); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_car_glb_queue_info); + ZXIC_COMM_MEMSET(p_car_glb_queue_info, 0, flow_num_total * sizeof(DPP_CAR_SOFT_RESET_QUEUE_T)); + p_car_glb_queue_info_temp = p_car_glb_queue_info; + + /* CAR A */ + flow_num = p_g_restore_data->cara_flow_num; + + for (j = 0; j < flow_num; j++) + { + rc = dpp_stat_car_queue_cfg_get(dev_id, + STAT_CAR_A_TYPE, + p_g_restore_data->cara_item[j].flow_id, + &drop_flag, + &plcr_en, + &profile_id); + if (DPP_OK != rc) + { + ZXIC_COMM_FREE(p_car_glb_queue_info); + ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ICM %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,"dpp_stat_car_queue_cfg_get"); + return rc; + } + + p_car_glb_queue_info_temp->car_type = STAT_CAR_A_TYPE; + p_car_glb_queue_info_temp->flow_id = p_g_restore_data->cara_item[j].flow_id; + p_car_glb_queue_info_temp->drop_flag = drop_flag; + p_car_glb_queue_info_temp->plcr_en = plcr_en; + p_car_glb_queue_info_temp->profile_id = profile_id; + p_car_glb_queue_info_temp++; + ZXIC_COMM_TRACE_DEV_INFO(dev_id, "carA used flow_id[%d] : 0x%08x\n", j, p_g_restore_data->cara_item[j].flow_id); + } + + /* CAR B */ + flow_num = p_g_restore_data->carb_flow_num; + + for (j = 0; j < flow_num; j++) + { + rc = dpp_stat_car_queue_cfg_get(dev_id, + STAT_CAR_B_TYPE, + p_g_restore_data->carb_item[j].flow_id, + &drop_flag, + &plcr_en, + &profile_id); + if (DPP_OK != rc) + { + ZXIC_COMM_FREE(p_car_glb_queue_info); + ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ICM %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,"dpp_stat_car_queue_cfg_get"); + return rc; + } + + p_car_glb_queue_info_temp->car_type = STAT_CAR_B_TYPE; + p_car_glb_queue_info_temp->flow_id = p_g_restore_data->carb_item[j].flow_id; + p_car_glb_queue_info_temp->drop_flag = drop_flag; + p_car_glb_queue_info_temp->plcr_en = plcr_en; + p_car_glb_queue_info_temp->profile_id = profile_id; + p_car_glb_queue_info_temp++; + ZXIC_COMM_TRACE_DEV_INFO(dev_id, "carB used flow_id[%d] : 0x%08x\n", j, p_g_restore_data->carb_item[j].flow_id); + } + + /* CAR C */ + flow_num = p_g_restore_data->carc_flow_num; + + for (j = 0; j < flow_num; j++) + { + rc = dpp_stat_car_queue_cfg_get(dev_id, + STAT_CAR_C_TYPE, + p_g_restore_data->carc_item[j].flow_id, + &drop_flag, + &plcr_en, + &profile_id); + if (DPP_OK != rc) + { + ZXIC_COMM_FREE(p_car_glb_queue_info); + ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ICM %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,"dpp_stat_car_queue_cfg_get"); + return rc; + } + + p_car_glb_queue_info_temp->car_type = STAT_CAR_C_TYPE; + p_car_glb_queue_info_temp->flow_id = p_g_restore_data->carc_item[j].flow_id; + p_car_glb_queue_info_temp->drop_flag = drop_flag; + p_car_glb_queue_info_temp->plcr_en = plcr_en; + p_car_glb_queue_info_temp->profile_id = profile_id; + p_car_glb_queue_info_temp++; + ZXIC_COMM_TRACE_DEV_INFO(dev_id, "carC used flow_id[%d] : 0x%08x\n", j, p_g_restore_data->carb_item[j].flow_id); + } + + ZXIC_COMM_MEMCPY(*pp_data_buff + buff_offset, p_car_glb_queue_info, flow_num_total * sizeof(DPP_CAR_SOFT_RESET_QUEUE_T)); + if((0xFFFFFFFF - (buff_offset)) < (flow_num_total * ZXIC_SIZEOF(DPP_CAR_SOFT_RESET_QUEUE_T))) + { + ZXIC_COMM_FREE(p_car_glb_queue_info); + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "ICM %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, buff_offset, flow_num_total * ZXIC_SIZEOF(DPP_CAR_SOFT_RESET_QUEUE_T), __FUNCTION__); + return ZXIC_PAR_CHK_INVALID_INDEX; + } + buff_offset += (flow_num_total * ZXIC_SIZEOF(DPP_CAR_SOFT_RESET_QUEUE_T)) % 0xffffffff; + } + + ZXIC_COMM_PRINT(">>>>>>>>>>>[dpp_stat_car_glb_mgr_get]: total flow_num = %d !\n", flow_num_total); + + /** profile 的信息 */ + if (0 != profile_pkt_total) + { + p_car_glb_pkt_profile_info = (DPP_STAT_CAR_PKT_PROFILE_CFG_T *)ZXIC_COMM_MALLOC(profile_pkt_total * ZXIC_SIZEOF(DPP_STAT_CAR_PKT_PROFILE_CFG_T)); + if (NULL == (p_car_glb_pkt_profile_info)) + { + ZXIC_COMM_FREE(p_car_glb_queue_info); + ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ICM %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__); + return ZXIC_PAR_CHK_POINT_NULL; + } + + ZXIC_COMM_MEMSET(p_car_glb_pkt_profile_info, 0, profile_pkt_total * sizeof(DPP_STAT_CAR_PKT_PROFILE_CFG_T)); + p_car_glb_pkt_profile_info_temp = p_car_glb_pkt_profile_info; + } + size = ZXIC_SIZEOF(DPP_STAT_CAR_PROFILE_CFG_T); + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, profile_num_total, size); + p_car_glb_profile_info = (DPP_STAT_CAR_PROFILE_CFG_T *)ZXIC_COMM_MALLOC(profile_num_total * size); + if (NULL == (p_car_glb_profile_info)) + { + ZXIC_COMM_FREE(p_car_glb_queue_info); + ZXIC_COMM_FREE(p_car_glb_pkt_profile_info); + ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ICM %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__); + return ZXIC_PAR_CHK_POINT_NULL; + } + + ZXIC_COMM_MEMSET(p_car_glb_profile_info, 0, profile_num_total * sizeof(DPP_STAT_CAR_PROFILE_CFG_T)); + p_car_glb_profile_info_temp = p_car_glb_profile_info; + + ZXIC_COMM_PRINT(">>>>>>>>>>>[dpp_stat_car_glb_mgr_get]: Get profile info start!\n"); + ZXIC_COMM_PRINT(">>>>>>>>>>> Get car CAR_A_PROFILE info start!\n"); + + for (j = 0; j <= DPP_CAR_A_PROFILE_ID_MAX; j++) + { + /* (0 != profile_pkt_total) -- Coverity err : 递增 null 指针 p_car_glb_pkt_profile_info_temp */ + if ((0 != profile_pkt_total) && (ZXIC_TRUE == p_g_restore_data->car_pkt_sign[j])) + { + ZXIC_COMM_TRACE_DEV_INFO(dev_id, "car profile_id[%d] is pkt_profile!!!!\n", j); + rc = dpp_stat_car_profile_cfg_get(dev_id, + STAT_CAR_A_TYPE, + ZXIC_TRUE, + j, + p_car_glb_pkt_profile_info_temp); + if (DPP_OK != rc) + { + ZXIC_COMM_FREE(p_car_glb_queue_info); + ZXIC_COMM_FREE(p_car_glb_pkt_profile_info); + ZXIC_COMM_FREE(p_car_glb_profile_info); + ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ICM %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,"dpp_stat_car_profile_cfg_get"); + return rc; + } + + p_car_glb_pkt_profile_info_temp++; + } + } + + for (j = 0; j <= DPP_CAR_A_PROFILE_ID_MAX; j++) + { + if (ZXIC_TRUE != p_g_restore_data->car_pkt_sign[j]) + { + rc = dpp_stat_car_profile_cfg_get(dev_id, + STAT_CAR_A_TYPE, + ZXIC_FALSE, + j, + p_car_glb_profile_info_temp); + if (DPP_OK != rc) + { + ZXIC_COMM_FREE(p_car_glb_queue_info); + ZXIC_COMM_FREE(p_car_glb_pkt_profile_info); + ZXIC_COMM_FREE(p_car_glb_profile_info); + ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ICM %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,"dpp_stat_car_profile_cfg_get"); + return rc; + } + + p_car_glb_profile_info_temp++; + } + } + + ZXIC_COMM_PRINT(">>>>>>>>>>> Get car CAR_B_PROFILE info start!\n"); + + for (j = 0; j <= DPP_CAR_B_PROFILE_ID_MAX; j++) + { + rc = dpp_stat_car_profile_cfg_get(dev_id, + STAT_CAR_B_TYPE, + ZXIC_FALSE, + j, + p_car_glb_profile_info_temp); + if (DPP_OK != rc) + { + ZXIC_COMM_FREE(p_car_glb_queue_info); + ZXIC_COMM_FREE(p_car_glb_pkt_profile_info); + ZXIC_COMM_FREE(p_car_glb_profile_info); + ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ICM %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,"dpp_stat_car_profile_cfg_get"); + return rc; + } + + p_car_glb_profile_info_temp++; + } + + ZXIC_COMM_PRINT(">>>>>>>>>>> Get car CAR_C_PROFILE info start!\n"); + + for (j = 0; j <= DPP_CAR_C_PROFILE_ID_MAX; j++) + { + rc = dpp_stat_car_profile_cfg_get(dev_id, + STAT_CAR_C_TYPE, + ZXIC_FALSE, + j, + p_car_glb_profile_info_temp); + if (DPP_OK != rc) + { + ZXIC_COMM_FREE(p_car_glb_queue_info); + ZXIC_COMM_FREE(p_car_glb_pkt_profile_info); + ZXIC_COMM_FREE(p_car_glb_profile_info); + ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ICM %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,"dpp_stat_car_profile_cfg_get"); + return rc; + } + p_car_glb_profile_info_temp++; + } + + ZXIC_COMM_MEMCPY(*pp_data_buff + buff_offset, &(p_g_restore_data->car0_pkt_num), sizeof(ZXIC_UINT32)); + buff_offset += sizeof(ZXIC_UINT32); + + if((0xFFFFFFFF - (buff_offset)) < (sizeof(ZXIC_UINT32))) + { + ZXIC_COMM_FREE(p_car_glb_queue_info); + ZXIC_COMM_FREE(p_car_glb_profile_info); + ZXIC_COMM_FREE(p_car_glb_pkt_profile_info); + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "ICM %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, buff_offset, sizeof(ZXIC_UINT32), __FUNCTION__); + return ZXIC_PAR_CHK_INVALID_INDEX; + } + buff_offset += sizeof(ZXIC_UINT32); + + if (0 != profile_pkt_total) + { + ZXIC_COMM_MEMCPY(*pp_data_buff + buff_offset, p_car_glb_pkt_profile_info, profile_pkt_total * sizeof(DPP_STAT_CAR_PKT_PROFILE_CFG_T)); + buff_offset += profile_pkt_total * ZXIC_SIZEOF(DPP_STAT_CAR_PKT_PROFILE_CFG_T); + } + + ZXIC_COMM_PRINT(">>>>>>>>>>>[dpp_stat_car_glb_mgr_get]: total pkt_profile = %d !\n", profile_pkt_total); + + ZXIC_COMM_MEMCPY(*pp_data_buff + buff_offset, &profile_num_total, sizeof(ZXIC_UINT32)); + if((0xFFFFFFFF - (buff_offset)) < (sizeof(ZXIC_UINT32))) + { + ZXIC_COMM_FREE(p_car_glb_queue_info); + ZXIC_COMM_FREE(p_car_glb_profile_info); + ZXIC_COMM_FREE(p_car_glb_pkt_profile_info); + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "ICM %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, buff_offset, sizeof(ZXIC_UINT32), __FUNCTION__); + return ZXIC_PAR_CHK_INVALID_INDEX; + } + buff_offset += sizeof(ZXIC_UINT32); + + if (0 != profile_num_total) + { + ZXIC_COMM_PRINT(">>>>>>>>>>>[dpp_stat_car_glb_mgr_get]: total profile = %d !\n", profile_num_total); + ZXIC_COMM_MEMCPY(*pp_data_buff + buff_offset, p_car_glb_profile_info, profile_num_total * sizeof(DPP_STAT_CAR_PROFILE_CFG_T)); + buff_offset += profile_num_total * ZXIC_SIZEOF(DPP_STAT_CAR_PROFILE_CFG_T); + } + + ZXIC_COMM_PRINT(">>>>>>>>>>>[dpp_stat_car_glb_mgr_get]: total profile = %d !\n", profile_num_total); + ZXIC_COMM_PRINT(">>>>>>>>>>>[dpp_stat_car_glb_mgr_get]: buff_offset= %d !\n", buff_offset); + + *p_flag = ZXIC_TRUE; + + ZXIC_COMM_FREE(p_car_glb_queue_info); + + if (0 != profile_pkt_total) + { + ZXIC_COMM_FREE(p_car_glb_pkt_profile_info); + } + + ZXIC_COMM_FREE(p_car_glb_profile_info); + } + + ZXIC_COMM_PRINT(">>>>>>>>>>>[dpp_stat_car_glb_mgr_get]: END! total size = %d !\n", *p_size); + + return rc; +} + +#endif +#endif + +#if ZXIC_REAL("TEST") + +#if 0 +/***********************************************************/ +/** +* @param p_rb_cfg +* +* @return +* @remark 无 +* @see +* @author XXX @date 2017/10/31 +************************************************************/ +DPP_STATUS dpp_stat_queue_rb_root_prt(ZXIC_RB_CFG *p_rb_cfg) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_UINT32 i = 0; + ZXIC_UINT32 dev_id = 0; + + DPP_CAR_QUEUE_RB_KEY_T *p_tmp_car_queue_rb_key = NULL; + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_rb_cfg); + + if (NULL != p_rb_cfg->p_root) + { + p_tmp_car_queue_rb_key = (DPP_CAR_QUEUE_RB_KEY_T *)p_rb_cfg->p_root->p_key; + + if (NULL != p_tmp_car_queue_rb_key) + { + ZXIC_COMM_PRINT("dpp_stat_queue_rb_root_prt[GET] car_queue_cfg:\n"); + + for (i = 0; i < DPP_CAR_QUEUE_CFG_ZXIC_UINT8; i++) + { + ZXIC_COMM_PRINT("%02x\t", p_tmp_car_queue_rb_key->profile_cfg[i]); + + if (0 == (i + 1) % 4) + { + ZXIC_COMM_PRINT("\n"); + } + } + + ZXIC_COMM_PRINT("\n"); + + } + + } + + return rc; +} + +/***********************************************************/ +/** +* @param p_rb_cfg +* +* @return +* @remark 无 +* @see +* @author XXX @date 2017/10/31 +************************************************************/ +DPP_STATUS dpp_stat_car_profile_id_rb_root_prt(ZXIC_UINT32 dev_id, ZXIC_RB_CFG *p_rb_cfg) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_UINT32 i = 0; + + DPP_CAR_PROFILE_ID_RB_KEY_T *p_tmp_car_profile_id_rb_key = NULL; + ZXIC_RB_TN *p_car_rb_node = NULL; + DPP_CAR_PROFILE_RB_KEY_T *p_car_profile_rb_key = NULL; + + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_rb_cfg); + + if (NULL != p_rb_cfg->p_root) + { + p_tmp_car_profile_id_rb_key = (DPP_CAR_PROFILE_ID_RB_KEY_T *)p_rb_cfg->p_root->p_key; + + if (NULL != p_tmp_car_profile_id_rb_key) + { + /* ZXIC_COMM_PRINT("dpp_stat_car_profile_id_rb_root_prt pp_car_node ADDRESS: 0x%08x\n", (ZXIC_UINT32)p_tmp_car_profile_id_rb_key->p_car_node); */ + p_car_rb_node = (ZXIC_RB_TN * )p_tmp_car_profile_id_rb_key->p_car_node; + + if (NULL != p_car_rb_node) + { + p_car_profile_rb_key = (DPP_CAR_PROFILE_RB_KEY_T *)p_car_rb_node->p_key; + + if (NULL != p_car_profile_rb_key) + { + for (i = 0; i < DPP_CAR_PROFILE_CFG_ZXIC_UINT32; i++) + { + ZXIC_COMM_PRINT("%08x\t", p_car_profile_rb_key->profile_cfg[i]); + + if (0 == (i + 1) % 4) + { + ZXIC_COMM_PRINT("\n"); + } + } + + ZXIC_COMM_PRINT("\n"); + } + } + } + } + + return rc; +} + +#endif +#endif + + + diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se/dpp_stat_cfg.c b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se/dpp_stat_cfg.c new file mode 100755 index 0000000..5187c93 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se/dpp_stat_cfg.c @@ -0,0 +1,310 @@ +/************************************************************** +* Ȩ (C)2013-2015, ͨѶɷ޹˾ +* ļ : dpp_stat_cfg.c +* ļʶ : +* ժҪ : +* ˵ : +* ǰ汾 : +* : ls +* : 2016/03/29 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* ޸ļ¼1: +* ޸: +* : +* : +* ޸: +***************************************************************/ +#include "zxic_common.h" +#include "dpp_type_api.h" +#include "dpp_dev.h" +#include "dpp_stat_reg.h" +#include "dpp_stat_cfg.h" +#include "dpp_stat_api.h" +#include "dpp_se_api.h" +#include "dpp_se.h" +#include "dpp_reg_api.h" +#include "dpp_reg_info.h" + +PPU_STAT_CFG_T g_ppu_stat_cfg = {0}; + +#if ZXIC_REAL("Basic Reg Operation") + +/***********************************************************/ +/** ȡppuͳƬ +* @param dev_id 豸 +* @param p_ppu_eram_depth ppuͳƬ +* +* @return NPE_OK-ɹNPE_ERR-ʧ +* @remark +* @see +* @author ls @date 2016/03/31 +************************************************************/ +DPP_STATUS dpp_stat_ppu_eram_depth_get(DPP_DEV_T *dev, + ZXIC_UINT32 *p_ppu_eram_depth) +{ + DPP_STATUS rc = DPP_OK; + DPP_STAT_STAT_CFG_PPU_ERAM_DEPTH_T ppu_eram_depth_cfg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_ppu_eram_depth); + + rc = dpp_reg_read(dev, + STAT_STAT_CFG_PPU_ERAM_DEPTHr, + 0, + 0, + &ppu_eram_depth_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + + *p_ppu_eram_depth = ppu_eram_depth_cfg.ppu_eram_depth; + + return rc; +} + +/***********************************************************/ +/** ȡppuͳ ERAMַ +* @param dev_id 豸 +* @param p_ppu_eram_baddr ppuͳƬڻַ +* +* @return NPE_OK-ɹNPE_ERR-ʧ +* @remark +* @see +* @author ls @date 2016/03/31 +************************************************************/ +DPP_STATUS dpp_stat_ppu_eram_baddr_get(DPP_DEV_T *dev, + ZXIC_UINT32 *p_ppu_eram_baddr) +{ + DPP_STATUS rc = DPP_OK; + DPP_STAT_STAT_CFG_PPU_ERAM_BASE_ADDR_T ppu_eram_baddr_cfg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_ppu_eram_baddr); + + rc = dpp_reg_read(dev, + STAT_STAT_CFG_PPU_ERAM_BASE_ADDRr, + 0, + 0, + &ppu_eram_baddr_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + + *p_ppu_eram_baddr = ppu_eram_baddr_cfg.ppu_eram_base_addr; + + return rc; +} + +/***********************************************************/ +/** ȡppuͳ ddrַ +* @param dev_id 豸 +* @param p_ppu_ddr_baddr ppuͳƬַ +* +* @return NPE_OK-ɹNPE_ERR-ʧ +* @remark +* @see +* @author ls @date 2016/03/31 +************************************************************/ +DPP_STATUS dpp_stat_ppu_ddr_baddr_get(DPP_DEV_T *dev, + ZXIC_UINT32 *p_ppu_ddr_baddr) +{ + DPP_STATUS rc = DPP_OK; + DPP_STAT_STAT_CFG_PPU_DDR_BASE_ADDR_T ppu_ddr_baddr_cfg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_ppu_ddr_baddr); + + rc = dpp_reg_read(dev, + STAT_STAT_CFG_PPU_DDR_BASE_ADDRr, + 0, + 0, + &ppu_ddr_baddr_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read"); + + *p_ppu_ddr_baddr = ppu_ddr_baddr_cfg.ppu_ddr_base_addr; + + return rc; +} +#endif + +#if ZXIC_REAL("Advanced Function") +/***********************************************************/ +/** ppuֵȡ +* @param dev_id 豸 +* @param rd_mode ȡλģʽμSTAT_CNT_MODE_E0-64bit1-128bit +* @param index λμrd_mode +* @param clr_mode ģʽμSTAT_RD_CLR_MODE_E0-壬1- +* @param p_data Σȡ +* +* @return NPE_OK-ɹNPE_ERR-ʧ +* @remark +* @see +* @author ls @date 2016/07/11 +************************************************************/ +DPP_STATUS dpp_stat_ppu_cnt_get(DPP_DEV_T *dev, + STAT_CNT_MODE_E rd_mode, + ZXIC_UINT32 index, + ZXIC_UINT32 clr_mode, + ZXIC_UINT32 *p_data) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 ppu_eram_baddr = 0; + ZXIC_UINT32 ppu_eram_depth = 0; + ZXIC_UINT32 ppu_ddr_baddr = 0; + ZXIC_UINT32 eram_rd_mode = 0; + ZXIC_UINT32 eram_clr_mode = 0; + // ZXIC_UINT32 ddr_rd_mode = 0; + // ZXIC_UINT32 ddr_clr_mode = 0; + // ZXIC_UINT32 ddr_index = 0; + + ZXIC_COMM_CHECK_POINT(dev); + + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), rd_mode, STAT_64_MODE, STAT_MAX_MODE - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), clr_mode, STAT_RD_CLR_MODE_UNCLR, STAT_RD_CLR_MODE_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data); + + rc = dpp_stat_ppu_eram_depth_get(dev, + &ppu_eram_depth); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_ppu_eram_depth_get"); + + rc = dpp_stat_ppu_eram_baddr_get(dev, + &ppu_eram_baddr); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_ppu_eram_baddr_get"); + + rc = dpp_stat_ppu_ddr_baddr_get(dev, + &ppu_ddr_baddr); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_ppu_ddr_baddr_get"); + + /** Ƭڴ洢 */ + if ((index >> (STAT_128_MODE - rd_mode)) < ppu_eram_depth) + { + if (STAT_128_MODE == rd_mode) + { + eram_rd_mode = ERAM128_OPR_128b; + } + else + { + eram_rd_mode = ERAM128_OPR_64b; + } + + if (STAT_RD_CLR_MODE_UNCLR == clr_mode) + { + eram_clr_mode = RD_MODE_HOLD; + } + else + { + eram_clr_mode = RD_MODE_CLEAR; + } + + rc = dpp_se_smmu0_ind_read(dev, + ppu_eram_baddr, + index, + eram_rd_mode, + eram_clr_mode, + p_data); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_se_smmu0_ind_read"); + } + /** Ƭ洢 */ + else + { + // if (STAT_128_MODE == rd_mode) + // { + // ddr_rd_mode = CMMU_RD_MODE_128; + // } + // else + // { + // ddr_rd_mode = CMMU_RD_MODE_64; + // } + + // if (STAT_RD_CLR_MODE_UNCLR == clr_mode) + // { + // ddr_clr_mode = CMMU_RD_CLR_MODE_UNCLR; + // } + // else + // { + // ddr_clr_mode = CMMU_RD_CLR_MODE_CLR; + // } + + // ddr_index = index - (ppu_eram_depth << (STAT_128_MODE - rd_mode)); + + // rc = dpp_se_cmmu_ddr_read(dev_id, + // ppu_ddr_baddr, + // ddr_rd_mode, + // ddr_clr_mode, + // ddr_index, + // p_data); + // ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_se_cmmu_ddr_read"); + } + + return rc; +} + +/***********************************************************/ +/** ppuͳƬ +* @param dev_id 豸 +* @param ppu_eram_depth ppuͳƬ,128bitΪλ +* +* @return NPE_OK-ɹNPE_ERR-ʧ +* @remark +* @see +* @author ls @date 2016/03/31 +************************************************************/ +DPP_STATUS dpp_stat_ppu_eram_depth_set(DPP_DEV_T *dev, ZXIC_UINT32 ppu_eram_depth) +{ + DPP_STATUS rc = DPP_OK; + DPP_STAT_STAT_CFG_PPU_ERAM_DEPTH_T ppu_eram_depth_cfg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), ppu_eram_depth, 0, DPP_STAT_PPU_ERAM_DEPTH_MAX); + + ppu_eram_depth_cfg.ppu_eram_depth = ppu_eram_depth; + + rc = dpp_reg_write(dev, + STAT_STAT_CFG_PPU_ERAM_DEPTHr, + 0, + 0, + &ppu_eram_depth_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write"); + + g_ppu_stat_cfg.eram_depth = ppu_eram_depth; + + return rc; +} + +/***********************************************************/ +/** ppuͳ ERAMַ +* @param dev_id 豸 +* @param ppu_eram_baddr ppuͳeRamַ,128bitΪλ +* +* @return NPE_OK-ɹNPE_ERR-ʧ +* @remark +* @see +* @author ls @date 2016/03/31 +************************************************************/ +DPP_STATUS dpp_stat_ppu_eram_baddr_set(DPP_DEV_T *dev, ZXIC_UINT32 ppu_eram_baddr) +{ + DPP_STATUS rc = DPP_OK; + DPP_STAT_STAT_CFG_PPU_ERAM_BASE_ADDR_T ppu_eram_baddr_cfg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), ppu_eram_baddr, 0, DPP_STAT_PPU_ERAM_BADDR_MAX); + + ppu_eram_baddr_cfg.ppu_eram_base_addr = ppu_eram_baddr; + + rc = dpp_reg_write(dev, + STAT_STAT_CFG_PPU_ERAM_BASE_ADDRr, + 0, + 0, + &ppu_eram_baddr_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write"); + + g_ppu_stat_cfg.eram_baddr = ppu_eram_baddr; + + return rc; +} + +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se_apt/Kbuild.include b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se_apt/Kbuild.include new file mode 100644 index 0000000..8a8b8cc --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se_apt/Kbuild.include @@ -0,0 +1,2 @@ +cur_dir := en_np/sdk/source/dev/module/se_apt/ +src_files += $(addprefix $(cur_dir),$(notdir $(wildcard $(dinghai_root)/$(cur_dir)*.c))) diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se_apt/dpp_apt_se_acl.c b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se_apt/dpp_apt_se_acl.c new file mode 100644 index 0000000..0da04a1 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se_apt/dpp_apt_se_acl.c @@ -0,0 +1,145 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_apt_se_acl.c +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : 陈勤00181032 +* 完成日期 : 2023/02/22 +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ + +#include "dpp_apt_se.h" +#include "dpp_dev.h" +#include "dpp_sdt.h" +#include "dpp_acl.h" +#include "dpp_dtb_table.h" + +static DPP_ACL_CFG_EX_T g_apt_acl_cfg = {0}; + +/***********************************************************/ +/** acl资源初始化 +* @param dev_id 设备号 +* @param tbl_num etcam对应的sdt表个数 +* @param pAclTblRes acl表资源信息，包括SDT配置信息，acl资源(条目数，存放方式和占用的block)和结构体码流转换回调函数 +* @return +* @remark 无 +* @see +* @author chenqin00181032 @date 2023/02/22 +************************************************************/ +DPP_STATUS dpp_apt_acl_res_init(DPP_DEV_T *dev,ZXIC_UINT32 tbl_num,DPP_APT_ACL_TABLE_T *pAclTblRes) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT8 index = 0; + DPP_APT_ACL_TABLE_T *pTempAclTbl = NULL; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_INDEX_UPPER(tbl_num, DPP_ETCAM_TBLID_NUM); + ZXIC_COMM_CHECK_POINT(pAclTblRes); + + rc = dpp_acl_cfg_init_ex(dev, &g_apt_acl_cfg, + (ZXIC_VOID *)ZXIC_COMM_VAL_TO_PTR(DEV_ID(dev)), + DPP_ACL_FLAG_ETCAM0_EN, + NULL); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_acl_cfg_init_ex"); + + for(index = 0;index < tbl_num;index++) + { + pTempAclTbl = pAclTblRes + index; + rc = dpp_sdt_tbl_write(dev, + pTempAclTbl->sdtNo, + pTempAclTbl->aclSdt.table_type, + &(pTempAclTbl->aclSdt), + SDT_OPER_ADD); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_sdt_tbl_write"); + + rc = dpp_acl_tbl_init_ex(&g_apt_acl_cfg, + pTempAclTbl->aclSdt.etcam_table_id, + pTempAclTbl->aclSdt.as_en, + pTempAclTbl->aclRes.entry_num, + pTempAclTbl->aclRes.pri_mode, + pTempAclTbl->aclSdt.etcam_key_mode, + pTempAclTbl->aclSdt.as_rsp_mode, + pTempAclTbl->aclSdt.as_eram_baddr, + pTempAclTbl->aclRes.block_num, + pTempAclTbl->aclRes.block_index); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_acl_tbl_init_ex"); + + rc = dpp_apt_set_callback(DEV_ID(dev), + pTempAclTbl->sdtNo, + pTempAclTbl->aclSdt.table_type, + (ZXIC_VOID *)pTempAclTbl); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_apt_set_callback"); + + } + + return DPP_OK; +} + +/***********************************************************/ +/** acl表项插入/更新 +* @param dev_id 设备号 +* @param sdt_no sdt号 0~255 +* @param pData 业务插入表项内容，具体结构体由业务确定(结构体的第一个字段必须为index)，SDK不感知 +* @return +* @remark 无 +* @see +* @author chenqin00181032 @date 2023/02/22 +************************************************************/ +DPP_STATUS dpp_apt_dtb_acl_entry_insert(DPP_DEV_T *dev,ZXIC_UINT32 queue_id, ZXIC_UINT32 sdt_no, void *pData) +{ + ZXIC_UINT8 data[DPP_ETCAM_WIDTH_MAX/8] = {0}; /*640bit*/ + ZXIC_UINT8 mask[DPP_ETCAM_WIDTH_MAX/8] = {0}; /*640bit*/ + ZXIC_UINT8 rst[16] = {0}; /*128bit*/ + ZXIC_UINT32 element_id = 0; + ZXIC_UINT32 rc = DPP_OK; + + DPP_ACL_ENTRY_EX_T aclEntry = {0}; + DPP_DTB_ACL_ENTRY_INFO_T tDtbAclEntry = {0}; + DPP_SDTTBL_ETCAM_T sdt_acl_info = {0}; /*SDT内容*/ + SE_APT_CALLBACK_T *pAptCallback = NULL; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_INDEX(sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1); + ZXIC_COMM_CHECK_POINT(pData); + + ZXIC_COMM_MEMSET(data, 0x0, sizeof(data)); + ZXIC_COMM_MEMSET(mask, 0x0, sizeof(mask)); + ZXIC_COMM_MEMSET(rst, 0x0, sizeof(rst)); + ZXIC_COMM_MEMSET(&aclEntry, 0x0, sizeof(DPP_ACL_ENTRY_EX_T)); + ZXIC_COMM_MEMSET(&tDtbAclEntry, 0x0, sizeof(DPP_DTB_ACL_ENTRY_INFO_T)); + + aclEntry.key_data = data; + aclEntry.key_mask = mask; + aclEntry.p_as_rslt = rst; + + //从sdt_no中获取SDT配置 + rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_acl_info); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_soft_sdt_tbl_get"); + + pAptCallback = dpp_apt_get_func(DEV_ID(dev), sdt_no); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), pAptCallback); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), pAptCallback->se_func_info.aclFunc.acl_set_func); + + rc = pAptCallback->se_func_info.aclFunc.acl_set_func((void *)pData, &aclEntry); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "acl_entry_func"); + + tDtbAclEntry.handle = aclEntry.pri; + tDtbAclEntry.key_data = aclEntry.key_data; + tDtbAclEntry.key_mask = aclEntry.key_mask; + tDtbAclEntry.p_as_rslt = aclEntry.p_as_rslt; + + rc = dpp_dtb_acl_dma_insert(dev, queue_id, sdt_no, 1, &tDtbAclEntry, &element_id); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_acl_dma_insert"); + + return rc; +} diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se_apt/dpp_apt_se_comm.c b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se_apt/dpp_apt_se_comm.c new file mode 100644 index 0000000..6b55c52 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se_apt/dpp_apt_se_comm.c @@ -0,0 +1,315 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_apt_se_common.c +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : 陈勤00181032 +* 完成日期 : 2023/02/22 +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ + +#include "dpp_apt_se.h" +#include "dpp_dev.h" +#include "dpp_dtb_table_api.h" +#include "dpp_dtb_table.h" +#include "dpp_kernel_init.h" +#include "dpp_drv_sdt.h" +#include "dpp_tbl_comm.h" + +#define DTB_QUEUE_ACK_SIZE (16) +#define DTB_QUEUE_ELEMENT_NUM (32) +#define DTB_QUEUE_ELEMENT_DATA_SIZE (16*1024 + DTB_QUEUE_ACK_SIZE)//16k+16 +#define DTB_QUEUE_DATA_SIZE (DTB_QUEUE_ELEMENT_DATA_SIZE * DTB_QUEUE_ELEMENT_NUM) +#define DTB_QUEUE_ELEMENT_DUMP_SIZE (16*1024 + DTB_QUEUE_ACK_SIZE)//16K+16 +#define DTB_QUEUE_DUMP_SIZE (DTB_QUEUE_ELEMENT_DUMP_SIZE * DTB_QUEUE_ELEMENT_NUM) +#define DTB_QUEUE_DMA_SIZE (DTB_QUEUE_DATA_SIZE + DTB_QUEUE_DUMP_SIZE) + + +SE_APT_CALLBACK_T g_apt_se_callback[DPP_DEV_CHANNEL_MAX][DPP_DEV_SDT_ID_MAX] = {{{0}}}; + +/***********************************************************/ +/** 根据设备id和sdt号获取指针 +* @param p_new_key 新键值 +* @param p_old_key 旧键值 +* @param key_len 键值长度 +* @return 比较结果 +* @remark 无 +* @see +* @author chenqin00181032 @date 2023/02/24 +************************************************************/ +ZXIC_SINT32 dpp_apt_table_key_cmp(void *p_new_key, void *p_old_key, ZXIC_UINT32 key_len) +{ + ZXIC_COMM_CHECK_POINT(p_new_key); + ZXIC_COMM_CHECK_POINT(p_old_key); + /* 仅比较index */ + ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW_NO_ASSERT(key_len, (ZXIC_UINT32)ZXIC_SIZEOF(ZXIC_UINT32)); + return ZXIC_COMM_MEMCMP((ZXIC_UINT32 *)p_new_key, (ZXIC_UINT32 *)p_old_key,ZXIC_SIZEOF(ZXIC_UINT32)); +} + +/***********************************************************/ +/** 根据设备id和sdt号获取指针 +* @param dev_id 设备号 +* @param sdt_no 业务表对应的sdt号 +* @return +* @remark 无 +* @see +* @author chenqin00181032 @date 2023/02/24 +************************************************************/ +SE_APT_CALLBACK_T *dpp_apt_get_func(ZXIC_UINT32 dev_id,ZXIC_UINT32 sdt_no) +{ + ZXIC_COMM_CHECK_INDEX_RETURN_NULL_NO_ASSERT(dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_INDEX_RETURN_NULL_NO_ASSERT(sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1); + + return &g_apt_se_callback[dev_id][sdt_no]; +} + +/***********************************************************/ +/** 保存回调参数信息 +* @param dev_id 设备号 +* @param sdt_no 业务表对应的sdt号 +* @param table_type SDT属性中的表类型，取值参考DPP_SDT_TABLE_TYPE_E的定义(仅添加操作时有效) +* @param pData 需保存的回调信息，由table_type确定此ZXIC_VOID型指针对应的数据结果 +* @return +* @remark 无 +* @see +* @author chenqin00181032 @date 2023/02/24 +************************************************************/ +DPP_STATUS dpp_apt_set_callback(ZXIC_UINT32 dev_id, ZXIC_UINT32 sdt_no, ZXIC_UINT32 table_type,ZXIC_VOID *pData) +{ + SE_APT_CALLBACK_T *aptFunc = NULL; + + aptFunc = dpp_apt_get_func(dev_id,sdt_no); + ZXIC_COMM_CHECK_POINT(aptFunc); + + aptFunc->sdtNo = sdt_no; + aptFunc->table_type = table_type; + + switch (table_type) + { + case DPP_SDT_TBLT_eRAM: + { + aptFunc->se_func_info.eramFunc.opr_mode = ((DPP_APT_ERAM_TABLE_T *)pData)->opr_mode; + aptFunc->se_func_info.eramFunc.rd_mode = ((DPP_APT_ERAM_TABLE_T *)pData)->rd_mode; + aptFunc->se_func_info.eramFunc.eram_set_func = ((DPP_APT_ERAM_TABLE_T *)pData)->eram_set_func; + aptFunc->se_func_info.eramFunc.eram_get_func = ((DPP_APT_ERAM_TABLE_T *)pData)->eram_get_func; + break; + } + case DPP_SDT_TBLT_DDR3: + { + aptFunc->se_func_info.ddrFunc.ddr_tbl_depth = ((DPP_APT_DDR_TABLE_T *)pData)->ddr_table_depth; + aptFunc->se_func_info.ddrFunc.ddr_set_func = ((DPP_APT_DDR_TABLE_T *)pData)->ddr_set_func; + aptFunc->se_func_info.ddrFunc.ddr_get_func = ((DPP_APT_DDR_TABLE_T *)pData)->ddr_get_func; + break; + } + case DPP_SDT_TBLT_HASH: + { + aptFunc->se_func_info.hashFunc.hash_set_func = ((DPP_APT_HASH_TABLE_T *)pData)->hash_set_func; + aptFunc->se_func_info.hashFunc.hash_get_func = ((DPP_APT_HASH_TABLE_T *)pData)->hash_get_func; + break; + } + case DPP_SDT_TBLT_eTCAM: + { + aptFunc->se_func_info.aclFunc.acl_set_func = ((DPP_APT_ACL_TABLE_T *)pData)->acl_set_func; + aptFunc->se_func_info.aclFunc.acl_get_func = ((DPP_APT_ACL_TABLE_T *)pData)->acl_get_func; + break; + } + default: + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "dpp_apt_se_set_callback table_type[ %d ] is invalid!\n", table_type); + return DPP_ERR; + } + } + + return DPP_OK; +} + +DPP_STATUS dpp_apt_sw_list_insert(ZXIC_RB_CFG *rb_cfg,void *pData,ZXIC_UINT32 len) +{ + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT8 *p_rb_key = NULL; + ZXIC_RB_TN *p_rb_new = NULL; + ZXIC_RB_TN *p_rb_rtn = NULL; + ZXIC_UINT32 rc = DPP_OK; + + ZXIC_COMM_CHECK_POINT(rb_cfg); + ZXIC_COMM_CHECK_POINT(pData); + + p_rb_key = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(len); + ZXIC_COMM_CHECK_POINT(p_rb_key); + ZXIC_COMM_MEMSET(p_rb_key,0x0,len); + ZXIC_COMM_MEMCPY(p_rb_key,pData,len); + + p_rb_new = (ZXIC_RB_TN*)ZXIC_COMM_MALLOC(sizeof(ZXIC_RB_TN)); + if (NULL == (p_rb_new)) + { + ZXIC_COMM_FREE(p_rb_key); + ZXIC_COMM_TRACE_ERROR("\n ICM %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n", __FILE__, __LINE__, __FUNCTION__); + return ZXIC_PAR_CHK_POINT_NULL; + } + ZXIC_COMM_MEMSET(p_rb_new, 0, ZXIC_SIZEOF(ZXIC_RB_TN)); + INIT_RBT_TN(p_rb_new, p_rb_key); + + rc = zxic_comm_rb_insert(rb_cfg, p_rb_new, &p_rb_rtn); + if(rc == ZXIC_RBT_RC_UPDATE) + { + ZXIC_COMM_CHECK_POINT(p_rb_rtn); + ZXIC_COMM_MEMCPY(p_rb_rtn->p_key,pData,len); + ZXIC_COMM_FREE(p_rb_new); + ZXIC_COMM_FREE(p_rb_key); + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "update exist entry!\n"); + return DPP_OK; + } + + return rc; +} + +DPP_STATUS dpp_apt_sw_list_search(ZXIC_RB_CFG *rb_cfg,void *pData,ZXIC_UINT32 len) +{ + ZXIC_UINT32 rc = DPP_OK; + ZXIC_RB_TN *p_rb_rtn = NULL; + + ZXIC_COMM_CHECK_POINT(rb_cfg); + + rc = zxic_comm_rb_search(rb_cfg,pData,&p_rb_rtn); + if(DPP_OK != rc) + { + return rc; + } + //ZXIC_COMM_CHECK_RC_NO_ASSERT( rc, "zxic_comm_rb_search"); + + ZXIC_COMM_MEMCPY(pData,p_rb_rtn->p_key,len); + return rc; +} + +DPP_STATUS dpp_apt_sw_list_delete(ZXIC_RB_CFG *rb_cfg,void *pData,ZXIC_UINT32 len) +{ + ZXIC_UINT32 rc = DPP_OK; + ZXIC_RB_TN *p_rb_rtn = NULL; + + ZXIC_COMM_CHECK_POINT(rb_cfg); + + rc = zxic_comm_rb_delete(rb_cfg,pData,&p_rb_rtn); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "zxic_comm_rb_delete"); + ZXIC_COMM_FREE(p_rb_rtn->p_key); + ZXIC_COMM_FREE(p_rb_rtn); + + return rc; +} + +DPP_STATUS dpp_apt_get_zblock_index(ZXIC_UINT32 zblock_bitmap,ZXIC_UINT32 *zblk_idx) +{ + ZXIC_UINT32 index0 = 0; + ZXIC_UINT32 index1 = 0; + + ZXIC_COMM_CHECK_POINT(zblk_idx); + + for (index0 = 0; index0 < 32;index0++) + { + if((zblock_bitmap>>index0)&0x1) + { + *(zblk_idx + index1) = index0; + index1++; + } + } + + return DPP_OK; +} + +DPP_STATUS dpp_apt_dtb_res_init(DPP_DEV_T *dev) +{ + ZXIC_UINT32 rc = DPP_OK; + ZXIC_UINT32 queue_id = 0; + ZXIC_UINT32 dma_size = 2 * DTB_QUEUE_DMA_SIZE; + ZXIC_UINT16 vport = 0; + + DTB_QUEUE_DMA_ADDR_INFO tDmaAddrInfo = {0}; + + ZXIC_COMM_CHECK_POINT_NO_ASSERT(dev); + + vport = DEV_PCIE_VPORT(dev); + + // 申请队列 + rc = dpp_dtb_queue_requst(dev, "pf", vport, &queue_id); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_queue_requst"); + + /*分配下表DMA内存*/ + ZXIC_COMM_MEMSET(&tDmaAddrInfo, 0x00, sizeof(DTB_QUEUE_DMA_ADDR_INFO)); + rc = dpp_dtb_queue_dma_mem_alloc(dev, queue_id, dma_size); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_queue_dma_mem_alloc"); + + rc = dpp_dtb_queue_dma_mem_get(dev, queue_id, &tDmaAddrInfo); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_queue_dma_mem_get"); + + // 配置下表地址空间 + rc = dpp_dtb_queue_down_table_addr_set(dev, queue_id, + tDmaAddrInfo.dma_phy_addr, tDmaAddrInfo.dma_vir_addr); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_queue_down_table_addr_set"); + + // 配置dump表地址空间 + rc = dpp_dtb_queue_dump_table_addr_set(dev, queue_id, + tDmaAddrInfo.dma_phy_addr + DTB_QUEUE_DMA_SIZE, + tDmaAddrInfo.dma_vir_addr + DTB_QUEUE_DMA_SIZE); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_queue_dump_table_addr_set"); + + rc = dpp_dtb_user_info_set(dev, queue_id, vport, 0); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_user_info_set"); + + return DPP_OK; +} + +/***********************************************************/ +/** 根据设备id对表项公共参数初始化 +* @param dev_id 设备号 +* @return +* @remark 无 +* @see +* @author cq @date 2023/11/09 +************************************************************/ +DPP_STATUS dpp_apt_se_callback_init(ZXIC_UINT32 dev_id) +{ + ZXIC_UINT32 sdt_no = 0; + + ZXIC_COMM_CHECK_INDEX_NO_ASSERT(dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + + for(sdt_no=0;sdt_nosdtNo, + pTempDdrTbl->eDdrSdt.table_type, + &(pTempDdrTbl->eDdrSdt), + SDT_OPER_ADD); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_sdt_tbl_write"); + + rc = dpp_apt_set_callback(DEV_ID(dev), + pTempDdrTbl->sdtNo, + pTempDdrTbl->eDdrSdt.table_type, + (ZXIC_VOID *)pTempDdrTbl); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_apt_set_callback"); + } + + return DPP_OK; +} diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se_apt/dpp_apt_se_eram.c b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se_apt/dpp_apt_se_eram.c new file mode 100644 index 0000000..80ac815 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se_apt/dpp_apt_se_eram.c @@ -0,0 +1,216 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_apt_se_eram.c +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : 陈勤00181032 +* 完成日期 : 2023/02/22 +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ + +#include "dpp_apt_se.h" +#include "dpp_dev.h" +#include "dpp_sdt.h" +#include "dpp_dtb_table.h" +#include "dpp_dtb_table_api.h" +#include "dpp_apt_se.h" + +/***********************************************************/ +/** eram表资源初始化 +* @param dev_id 设备号 +* @param tbl_num 需初始化的eram表个数 +* @param pEramTbl eram资源信息，包括SDT配置信息，直接表读取位宽和结构体码流转换回调函数 +* @return +* @remark 无 +* @see +* @author chenqin00181032 @date 2023/02/22 +************************************************************/ +DPP_STATUS dpp_apt_eram_res_init(DPP_DEV_T *dev,ZXIC_UINT32 tbl_num,DPP_APT_ERAM_TABLE_T *pEramTbl) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT8 index = 0; + DPP_APT_ERAM_TABLE_T *pTempEramTbl = NULL; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_INDEX_UPPER(tbl_num, DPP_DEV_SDT_ID_MAX); + ZXIC_COMM_CHECK_POINT(pEramTbl); + + for(index = 0;index < tbl_num;index++) + { + pTempEramTbl = pEramTbl + index; + rc = dpp_sdt_tbl_write(dev, + pTempEramTbl->sdtNo, + pTempEramTbl->eRamSdt.table_type, + &(pTempEramTbl->eRamSdt), + SDT_OPER_ADD); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_sdt_tbl_write"); + + rc = dpp_apt_set_callback(DEV_ID(dev), + pTempEramTbl->sdtNo, + pTempEramTbl->eRamSdt.table_type, + (ZXIC_VOID *)pTempEramTbl); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_apt_set_callback"); + } + + return DPP_OK; +} + +/***********************************************************/ +/** dtb eram表项插入/更新 +* @param dev_id 设备号 +* @param sdt_no SDT号 0~255 +* @param index 条目index，索引范围随wrt_mode模式不同 +* @param pData 插入表项内容，由业务确定 +* @return +* @remark 无 +* @see +* @author chenqin00181032 @date 2023/02/22 +************************************************************/ +DPP_STATUS dpp_apt_dtb_eram_insert(DPP_DEV_T *dev,ZXIC_UINT32 queue_id,ZXIC_UINT32 sdt_no,ZXIC_UINT32 index,void *pData) +{ + ZXIC_UINT32 rc = DPP_OK; + ZXIC_UINT32 element_id = 0; + ZXIC_UINT32 dump_data[4] = {0}; + + SE_APT_CALLBACK_T *pAptCallback = NULL; + DPP_DTB_ERAM_ENTRY_INFO_T dtb_eram_entry = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_INDEX(sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1); + + ZXIC_COMM_MEMSET(dump_data, 0x00, sizeof(dump_data)); + + pAptCallback = dpp_apt_get_func(DEV_ID(dev), sdt_no); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), pAptCallback); + + rc = pAptCallback->se_func_info.eramFunc.eram_set_func(pData, dump_data); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "eram_set_func"); + + //dtb配表 + dtb_eram_entry.index = index; + dtb_eram_entry.p_data = dump_data; + rc = dpp_dtb_eram_dma_write(dev, + queue_id, + sdt_no, + 1, + &dtb_eram_entry, + &element_id); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_eram_dma_write"); + + return rc; +} + +/***********************************************************/ +/** eram表项数据获取,从软件缓存中获取 +* @param dev_id 设备号 +* @param sdt_no SDT号 0~255 +* @param index 条目index，索引范围随wrt_mode模式不同 +* @param pData 出参，返回业务表项内容 +* @return +* @remark 无 +* @see +* @author chenqin00181032 @date 2023/02/22 +************************************************************/ +DPP_STATUS dpp_apt_dtb_eram_get(DPP_DEV_T *dev, ZXIC_UINT32 queue_id, ZXIC_UINT32 sdt_no, ZXIC_UINT32 index, void *pData) +{ + ZXIC_UINT32 rc = DPP_OK; + ZXIC_UINT32 dump_data[4] = {0}; + SE_APT_CALLBACK_T *pAptCallback = NULL; + DPP_DTB_ERAM_ENTRY_INFO_T dump_eram_entry = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_INDEX(sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1); + + ZXIC_COMM_MEMSET(dump_data, 0x00, sizeof(dump_data)); + + pAptCallback = dpp_apt_get_func(DEV_ID(dev), sdt_no); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), pAptCallback); + + dump_eram_entry.index = index; + dump_eram_entry.p_data = dump_data; + rc = dpp_dtb_eram_data_get(dev, queue_id, sdt_no, &dump_eram_entry); + ZXIC_COMM_CHECK_RC_NO_ASSERT( rc, "dpp_dtb_eram_data_get"); + + rc = pAptCallback->se_func_info.eramFunc.eram_get_func(pData, dump_eram_entry.p_data); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "eram_get_func"); + + return rc; +} + +/***********************************************************/ +/** eram表项删除,软件维护删除 +* @param dev_id 设备号 +* @param sdt_no SDT号 0~255 +* @param index 条目index，索引范围随wrt_mode模式不同 +* @return +* @remark 无 +* @see +* @author chenqin00181032 @date 2023/02/22 +************************************************************/ +DPP_STATUS dpp_apt_dtb_eram_clear(DPP_DEV_T *dev,ZXIC_UINT32 queue_id,ZXIC_UINT32 sdt_no,ZXIC_UINT32 index) +{ + ZXIC_UINT32 rc = DPP_OK; + ZXIC_UINT32 element_id = 0; + ZXIC_UINT32 dump_data[4] = {0}; + + SE_APT_CALLBACK_T *pAptCallback = NULL; + DPP_DTB_ERAM_ENTRY_INFO_T dtb_eram_entry = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_INDEX(sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1); + + ZXIC_COMM_MEMSET(dump_data, 0x00, sizeof(dump_data)); + + pAptCallback = dpp_apt_get_func(DEV_ID(dev), sdt_no); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), pAptCallback); + + //dtb配表 + dtb_eram_entry.index = index; + dtb_eram_entry.p_data = dump_data; + rc = dpp_dtb_eram_dma_write(dev, + queue_id, + sdt_no, + 1, + &dtb_eram_entry, + &element_id); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_eram_dma_write"); + + return rc; +} + +/***********************************************************/ +/** eram表项flush +* @param dev_id 设备号 +* @param sdt_no SDT号 0~255 +* @param index 条目index，索引范围随wrt_mode模式不同 +* @return +* @remark 无 +* @see +* @author chenqin00181032 @date 2023/02/22 +************************************************************/ +DPP_STATUS dpp_apt_dtb_eram_flush(DPP_DEV_T *dev, ZXIC_UINT32 queue_id, ZXIC_UINT32 sdt_no) +{ + ZXIC_UINT32 rc = DPP_OK; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_INDEX(sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1); + + rc = dpp_dtb_eram_table_flush(dev, queue_id, sdt_no); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_eram_table_flush"); + ZXIC_COMM_TRACE_ERROR("dpp_apt_dtb_eram_flush sdt_no %d done.\n", sdt_no); + + return rc; +} diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se_apt/dpp_apt_se_hash.c b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se_apt/dpp_apt_se_hash.c new file mode 100644 index 0000000..9096915 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se_apt/dpp_apt_se_hash.c @@ -0,0 +1,326 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_apt_se_hash.c +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : chenqin00181032 +* 完成日期 : 2023/02/22 +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ + +#include "dpp_apt_se.h" +#include "dpp_dev.h" +#include "dpp_hash.h" +#include "dpp_sdt.h" +#include "dpp_dtb_cfg.h" +#include "dpp_dtb_table.h" +#include "dpp_dtb_table_api.h" + +static DPP_SE_CFG g_apt_se_cfg = {{{0}}}; + +/***********************************************************/ +/** hash表全局资源初始化 +* @param dev_id 设备号 +* @return +* @remark 无 +* @see +* @author chenqin00181032 @date 2023/02/22 +************************************************************/ +DPP_STATUS dpp_apt_hash_global_res_init(DPP_DEV_T *dev) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + + rc = dpp_se_init(dev, &g_apt_se_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_se_init"); + + rc = dpp_se_client_init(&g_apt_se_cfg, ZXIC_COMM_VAL_TO_PTR(DEV_ID(dev))); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_se_client_init"); + + return rc; +} + +/***********************************************************/ +/** hash引擎初始化 +* @param dev_id 设备号 +* @param func_num 需初始化的hash引擎个数 1~4 +* @param pHashFuncRes 每个hash引擎分配的zblock个数和编号，以及分配模式(混合模式或者纯片内模式) +* @return +* @remark 无 +* @see +* @author chenqin00181032 @date 2023/02/22 +************************************************************/ +DPP_STATUS dpp_apt_hash_func_res_init(ZXIC_UINT32 dev_id,ZXIC_UINT32 func_num,DPP_APT_HASH_FUNC_RES_T *pHashFuncRes) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 index = 0; + ZXIC_UINT32 zblk_idx[32] = {0}; + DPP_APT_HASH_FUNC_RES_T *pHashFuncResTemp = NULL; + + ZXIC_COMM_CHECK_INDEX(dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_INDEX_UPPER(func_num, HASH_FUNC_ID_NUM); + ZXIC_COMM_CHECK_POINT(pHashFuncRes); + + for (index = 0; index < func_num;index++) + { + ZXIC_COMM_MEMSET(zblk_idx,0x0,sizeof(zblk_idx)); + pHashFuncResTemp = pHashFuncRes+index; + rc = dpp_apt_get_zblock_index(pHashFuncResTemp->zblk_bitmap,zblk_idx); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_apt_get_zblock_index"); + + rc = dpp_hash_init(&g_apt_se_cfg, + pHashFuncResTemp->func_id, + pHashFuncResTemp->zblk_num, + zblk_idx, + pHashFuncResTemp->ddr_dis); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_hash_init"); + } + + return rc; + +} + +/***********************************************************/ +/** hash引擎初始化(删除硬件数据) +* @param dev_id 设备号 +* @param func_num 需初始化的hash引擎个数 1~4 +* @param pHashFuncRes 每个hash引擎分配的zblock个数和编号，以及分配模式(混合模式或者纯片内模式) +* @return +* @remark 无 +* @see +* @author chenqin00181032 @date 2023/02/22 +************************************************************/ +DPP_STATUS dpp_apt_hash_func_flush_hardware_all(DPP_DEV_T *dev, + ZXIC_UINT32 func_num, + DPP_APT_HASH_FUNC_RES_T *pHashFuncRes, + ZXIC_UINT32 queue_id) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 index = 0; + DPP_APT_HASH_FUNC_RES_T *pHashFuncResTemp = NULL; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_INDEX_UPPER(func_num, HASH_FUNC_ID_NUM); + for (index = 0; index < func_num; index++) + { + pHashFuncResTemp = pHashFuncRes + index; + + rc = dpp_dtb_zcam_space_clr(dev, &g_apt_se_cfg, queue_id, pHashFuncResTemp->func_id); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_zcam_space_clr"); + } + + return rc; + +} + +/***********************************************************/ +/** hash引擎bulk空间初始化 +* @param dev_id 设备号 +* @param bulk_num 需初始化的bulk表个数 1~32 +* @param pBulkRes zcell和zreg资源占用信息，如果是混合模式，需进行DDR资源分配 +* @return +* @remark 无 +* @see +* @author chenqin00181032 @date 2023/02/22 +************************************************************/ +DPP_STATUS dpp_apt_hash_bulk_res_init(ZXIC_UINT32 dev_id,ZXIC_UINT32 bulk_num,DPP_APT_HASH_BULK_RES_T *pBulkRes) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 index = 0; + DPP_APT_HASH_BULK_RES_T *pHashBulkResTemp = NULL; + DPP_HASH_DDR_RESC_CFG_T ddr_resc_cfg = {0}; + + ZXIC_COMM_CHECK_INDEX(dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_INDEX_UPPER(bulk_num, HASH_FUNC_ID_NUM*HASH_BULK_NUM); + ZXIC_COMM_CHECK_POINT(pBulkRes); + + for (index = 0; index < bulk_num;index++) + { + ZXIC_COMM_MEMSET(&ddr_resc_cfg,0x0,sizeof(DPP_HASH_DDR_RESC_CFG_T)); + pHashBulkResTemp = pBulkRes+index; + + ddr_resc_cfg.ddr_baddr = pHashBulkResTemp->ddr_baddr; + ddr_resc_cfg.ddr_item_num = pHashBulkResTemp->ddr_item_num; + ddr_resc_cfg.ddr_width_mode = pHashBulkResTemp->ddr_width_mode; + ddr_resc_cfg.ddr_crc_sel = pHashBulkResTemp->ddr_crc_sel; + ddr_resc_cfg.ddr_ecc_en = pHashBulkResTemp->ddr_ecc_en; + + rc = dpp_hash_bulk_init(&g_apt_se_cfg, + pHashBulkResTemp->func_id, + pHashBulkResTemp->bulk_id, + &ddr_resc_cfg, + pHashBulkResTemp->zcell_num, + pHashBulkResTemp->zreg_num); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_hash_bulk_init"); + } + + return rc; +} + +/***********************************************************/ +/** hash业务表属性初始化 +* @param dev_id 设备号 +* @param tbl_num 需初始化的业务表表个数 1~128 +* @param pHashTbl sdt配置信息，初始化标记和业务结构体码流转换函数 +* @return +* @remark 无 +* @see +* @author chenqin00181032 @date 2023/02/22 +************************************************************/ +DPP_STATUS dpp_apt_hash_tbl_res_init(DPP_DEV_T *dev,ZXIC_UINT32 tbl_num,DPP_APT_HASH_TABLE_T *pHashTbl) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 index = 0; + DPP_APT_HASH_TABLE_T *pHashTblTemp = NULL; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_INDEX_UPPER(tbl_num, HASH_FUNC_ID_NUM*HASH_TBL_ID_NUM); + ZXIC_COMM_CHECK_POINT(pHashTbl); + + for (index = 0; index < tbl_num;index++) + { + pHashTblTemp = pHashTbl+ index; + rc = dpp_sdt_tbl_write(dev, + pHashTblTemp->sdtNo, + pHashTblTemp->hashSdt.table_type, + &pHashTblTemp->hashSdt, + SDT_OPER_ADD); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_sdt_tbl_write"); + + rc = dpp_hash_tbl_id_info_init(&g_apt_se_cfg, + pHashTblTemp->hashSdt.hash_id, + pHashTblTemp->hashSdt.hash_table_id, + pHashTblTemp->tbl_flag, + pHashTblTemp->hashSdt.hash_table_width, + pHashTblTemp->hashSdt.key_size); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_hash_tbl_id_info_init_ex"); + + rc = dpp_apt_set_callback(DEV_ID(dev), + pHashTblTemp->sdtNo, + pHashTblTemp->hashSdt.table_type, + (ZXIC_VOID *)pHashTblTemp); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_apt_set_callback"); + } + + return rc; +} + +/***********************************************************/ +/** dtb hash表项插入/更新 +* @param dev_id 设备号 +* @param sdt_no sdt号 0~255 +* @param pData 插入hash表项信息,由业务确定 +* @return +* @remark 无 +* @see +* @author chenqin00181032 @date 2023/02/22 +************************************************************/ +DPP_STATUS dpp_apt_dtb_hash_insert(DPP_DEV_T *dev,ZXIC_UINT32 queue_id,ZXIC_UINT32 sdt_no,void *pData) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT8 key_valid = 1; + DPP_HASH_ENTRY entry = {0}; + DPP_SDTTBL_HASH_T sdt_hash_info = {0}; /*SDT内容*/ + ZXIC_UINT8 aucKey[HASH_KEY_MAX] = {0}; + ZXIC_UINT8 aucRst[HASH_RST_MAX] = {0}; + SE_APT_CALLBACK_T *pAptCallback = NULL; + DPP_DTB_HASH_ENTRY_INFO_T tDtbHashEntry = {0}; + ZXIC_UINT32 element_id = 0; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_INDEX(queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1); + ZXIC_COMM_CHECK_INDEX(sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1); + + //从sdt_no中获取SDT配置 + rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_hash_info); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_soft_sdt_tbl_get"); + + pAptCallback = dpp_apt_get_func(DEV_ID(dev), sdt_no); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), pAptCallback); + + entry.p_key = aucKey; + entry.p_rst = aucRst; + ZXIC_COMM_MEMSET(entry.p_key,0x0,sizeof(aucKey)); + ZXIC_COMM_MEMSET(entry.p_rst,0x0,sizeof(aucRst)); + entry.p_key[0] = DPP_GET_HASH_KEY_CTRL(key_valid, + sdt_hash_info.hash_table_width, + sdt_hash_info.hash_table_id); + rc = pAptCallback->se_func_info.hashFunc.hash_set_func(pData,&entry); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "hash_set_func"); + + tDtbHashEntry.p_actu_key = &entry.p_key[1]; + tDtbHashEntry.p_rst = entry.p_rst; + + rc = dpp_dtb_hash_dma_insert(dev, queue_id,sdt_no,1,&tDtbHashEntry,&element_id); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_hash_dma_insert"); + + return rc; +} + +/***********************************************************/ +/** dtb hash表项删除 +* @param dev_id 设备号 +* @param sdt_no sdt号 0~255 +* @param pData 删除hash表项信息,由业务传入 +* @return +* @remark 无 +* @see +* @author chenqin00181032 @date 2023/02/22 +************************************************************/ +DPP_STATUS dpp_apt_dtb_hash_delete(DPP_DEV_T *dev,ZXIC_UINT32 queue_id,ZXIC_UINT32 sdt_no,void *pData) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT8 key_valid = 1; + DPP_HASH_ENTRY entry = {0}; + DPP_SDTTBL_HASH_T sdt_hash_info = {0}; /*SDT内容*/ + ZXIC_UINT8 aucKey[HASH_KEY_MAX] = {0}; + ZXIC_UINT8 aucRst[HASH_RST_MAX] = {0}; + SE_APT_CALLBACK_T *pAptCallback = NULL; + DPP_DTB_HASH_ENTRY_INFO_T tDtbHashEntry = {0}; + // ZXIC_UINT32 queue_id = 0; + ZXIC_UINT32 element_id = 0; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_INDEX(queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1); + ZXIC_COMM_CHECK_INDEX(sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1); + + //从sdt_no中获取SDT配置 + rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_hash_info); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_soft_sdt_tbl_get"); + + pAptCallback = dpp_apt_get_func(DEV_ID(dev), sdt_no); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), pAptCallback); + + entry.p_key = aucKey; + entry.p_rst = aucRst; + ZXIC_COMM_MEMSET(entry.p_key,0x0,sizeof(aucKey)); + ZXIC_COMM_MEMSET(entry.p_rst,0x0,sizeof(aucRst)); + entry.p_key[0] = DPP_GET_HASH_KEY_CTRL(key_valid, + sdt_hash_info.hash_table_width, + sdt_hash_info.hash_table_id); + rc = pAptCallback->se_func_info.hashFunc.hash_set_func(pData,&entry); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "hash_set_func"); + + ZXIC_COMM_MEMSET(&tDtbHashEntry,0x0,sizeof(DPP_DTB_HASH_ENTRY_INFO_T)); + ZXIC_COMM_MEMSET(entry.p_rst,0x0,sizeof(aucRst)); + tDtbHashEntry.p_actu_key = &entry.p_key[1]; + tDtbHashEntry.p_rst = entry.p_rst; + rc = dpp_dtb_hash_dma_delete(dev, queue_id,sdt_no,1,&tDtbHashEntry,&element_id); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_hash_dma_delete"); + + return rc; +} diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/Kbuild.include b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/Kbuild.include new file mode 100644 index 0000000..bb99f18 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/Kbuild.include @@ -0,0 +1,4 @@ +cur_dir := en_np/sdk/source/dev/module/table/ +subdirs := sdt/ se/ +src_files += +include $(foreach subdir, $(subdirs), $(dinghai_root)/$(cur_dir)$(subdir)/Kbuild.include) \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/sdt/Kbuild.include b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/sdt/Kbuild.include new file mode 100644 index 0000000..c3eee05 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/sdt/Kbuild.include @@ -0,0 +1,2 @@ +cur_dir := en_np/sdk/source/dev/module/table/sdt/ +src_files += $(addprefix $(cur_dir),$(notdir $(wildcard $(dinghai_root)/$(cur_dir)*.c))) diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/sdt/dpp_sdt.c b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/sdt/dpp_sdt.c new file mode 100755 index 0000000..b71bcdf --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/sdt/dpp_sdt.c @@ -0,0 +1,469 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_sdt.c +* 文件标识 : sdt配置接口实现文件 +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : 王春雷 +* 完成日期 : 2015/06/25 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ + +#include "zxic_common.h" + +#include "dpp_dev.h" +#include "dpp_se.h" +#include "dpp_sdt_def.h" +#include "dpp_sdt_mgr.h" +#include "dpp_sdt.h" + +/* 全局变量*/ +ZXIC_UINT32 g_table_type[DPP_DEV_CHANNEL_MAX][DPP_DEV_SDT_ID_MAX] = {{0}}; +DPP_SDT_TBL_DATA_T g_sdt_info[DPP_DEV_CHANNEL_MAX][DPP_DEV_SDT_ID_MAX] = {{{0}}}; + +/** 获取低n位数据 */ +#define DPP_SDT_GET_LOW_DATA(source_value, low_width) (source_value &((1<table_type = tbl_type; + ZXIC_COMM_UINT32_GET_BITS(p_sdt_eram->eram_mode, sdt_hig32, DPP_SDT_H_ERAM_MODE_BT_POS, DPP_SDT_H_ERAM_MODE_BT_LEN); + ZXIC_COMM_UINT32_GET_BITS(p_sdt_eram->eram_base_addr, sdt_hig32, DPP_SDT_H_ERAM_BASE_ADDR_BT_POS, DPP_SDT_H_ERAM_BASE_ADDR_BT_LEN); + ZXIC_COMM_UINT32_GET_BITS(p_sdt_eram->eram_table_depth, sdt_low32, DPP_SDT_L_ERAM_TABLE_DEPTH_BT_POS, DPP_SDT_L_ERAM_TABLE_DEPTH_BT_LEN); + p_sdt_eram->eram_clutch_en = clutch_en; + break; + } + + case DPP_SDT_TBLT_DDR3: + { + p_sdt_ddr3 = (DPP_SDTTBL_DDR3_T *)p_sdt_info; + p_sdt_ddr3->table_type = tbl_type; + ZXIC_COMM_UINT32_GET_BITS(p_sdt_ddr3->ddr3_base_addr, sdt_hig32, DPP_SDT_H_DDR3_BASE_ADDR_BT_POS, DPP_SDT_H_DDR3_BASE_ADDR_BT_LEN); + ZXIC_COMM_UINT32_GET_BITS(p_sdt_ddr3->ddr3_share_type, sdt_hig32, DPP_SDT_H_DDR3_SHARE_TYPE_BT_POS, DPP_SDT_H_DDR3_SHARE_TYPE_BT_LEN); + ZXIC_COMM_UINT32_GET_BITS(p_sdt_ddr3->ddr3_rw_len, sdt_hig32, DPP_SDT_H_DDR3_RW_LEN_BT_POS, DPP_SDT_H_DDR3_RW_LEN_BT_LEN); + ZXIC_COMM_UINT32_GET_BITS(tmp, sdt_hig32, DPP_SDT_H_DDR3_SDT_NUM_BT_POS, DPP_SDT_H_DDR3_SDT_NUM_BT_LEN); + ZXIC_COMM_UINT32_GET_BITS(p_sdt_ddr3->ddr3_sdt_num, sdt_low32, DPP_SDT_L_DDR3_SDT_NUM_BT_POS, DPP_SDT_L_DDR3_SDT_NUM_BT_LEN); + p_sdt_ddr3->ddr3_sdt_num += (tmp << DPP_SDT_L_DDR3_SDT_NUM_BT_LEN); + ZXIC_COMM_UINT32_GET_BITS(p_sdt_ddr3->ddr3_ecc_en, sdt_low32, DPP_SDT_L_DDR3_ECC_EN_BT_POS, DPP_SDT_L_DDR3_ECC_EN_BT_LEN); + p_sdt_ddr3->ddr3_clutch_en = clutch_en; + break; + } + + case DPP_SDT_TBLT_HASH: + { + p_sdt_hash = (DPP_SDTTBL_HASH_T *)p_sdt_info; + p_sdt_hash->table_type = tbl_type; + ZXIC_COMM_UINT32_GET_BITS(p_sdt_hash->hash_id, sdt_hig32, DPP_SDT_H_HASH_ID_BT_POS, DPP_SDT_H_HASH_ID_BT_LEN); + ZXIC_COMM_UINT32_GET_BITS(p_sdt_hash->hash_table_width, sdt_hig32, DPP_SDT_H_HASH_TABLE_WIDTH_BT_POS, DPP_SDT_H_HASH_TABLE_WIDTH_BT_LEN); + ZXIC_COMM_UINT32_GET_BITS(p_sdt_hash->key_size, sdt_hig32, DPP_SDT_H_HASH_KEY_SIZE_BT_POS, DPP_SDT_H_HASH_KEY_SIZE_BT_LEN); + ZXIC_COMM_UINT32_GET_BITS(p_sdt_hash->hash_table_id, sdt_hig32, DPP_SDT_H_HASH_TABLE_ID_BT_POS, DPP_SDT_H_HASH_TABLE_ID_BT_LEN); + ZXIC_COMM_UINT32_GET_BITS(p_sdt_hash->learn_en, sdt_hig32, DPP_SDT_H_LEARN_EN_BT_POS, DPP_SDT_H_LEARN_EN_BT_LEN); + ZXIC_COMM_UINT32_GET_BITS(p_sdt_hash->keep_alive, sdt_hig32, DPP_SDT_H_KEEP_ALIVE_BT_POS, DPP_SDT_H_KEEP_ALIVE_BT_LEN); + ZXIC_COMM_UINT32_GET_BITS(tmp, sdt_hig32, DPP_SDT_H_KEEP_ALIVE_BADDR_BT_POS, DPP_SDT_H_KEEP_ALIVE_BADDR_BT_LEN); + ZXIC_COMM_UINT32_GET_BITS(p_sdt_hash->keep_alive_baddr, sdt_low32, DPP_SDT_L_KEEP_ALIVE_BADDR_BT_POS, DPP_SDT_L_KEEP_ALIVE_BADDR_BT_LEN); + p_sdt_hash->keep_alive_baddr += (tmp << DPP_SDT_L_KEEP_ALIVE_BADDR_BT_LEN); + ZXIC_COMM_UINT32_GET_BITS(p_sdt_hash->rsp_mode, sdt_low32, DPP_SDT_L_RSP_MODE_BT_POS, DPP_SDT_L_RSP_MODE_BT_LEN); + p_sdt_hash->hash_clutch_en = clutch_en; + break; + } + + case DPP_SDT_TBLT_LPM: + { + p_sdt_lpm = (DPP_SDTTBL_LPM_T *)p_sdt_info; + p_sdt_lpm->table_type = tbl_type; + ZXIC_COMM_UINT32_GET_BITS(p_sdt_lpm->lpm_v46_id, sdt_hig32, DPP_SDT_H_LPM_V46ID_BT_POS, DPP_SDT_H_LPM_V46ID_BT_LEN); + ZXIC_COMM_UINT32_GET_BITS(p_sdt_lpm->rsp_mode, sdt_hig32, DPP_SDT_H_LPM_RSP_MODE_BT_POS, DPP_SDT_H_LPM_RSP_MODE_BT_LEN); + ZXIC_COMM_UINT32_GET_BITS(p_sdt_lpm->lpm_table_depth, sdt_low32, DPP_SDT_L_LPM_TABLE_DEPTH_BT_POS, DPP_SDT_L_LPM_TABLE_DEPTH_BT_LEN); + p_sdt_lpm->lpm_clutch_en = clutch_en; + break; + } + + case DPP_SDT_TBLT_eTCAM: + { + p_sdt_etcam = (DPP_SDTTBL_ETCAM_T *)p_sdt_info; + p_sdt_etcam->table_type = tbl_type; + ZXIC_COMM_UINT32_GET_BITS(p_sdt_etcam->etcam_id, sdt_hig32, DPP_SDT_H_ETCAM_ID_BT_POS, DPP_SDT_H_ETCAM_ID_BT_LEN); + ZXIC_COMM_UINT32_GET_BITS(p_sdt_etcam->etcam_key_mode, sdt_hig32, DPP_SDT_H_ETCAM_KEY_MODE_BT_POS, DPP_SDT_H_ETCAM_KEY_MODE_BT_LEN); + ZXIC_COMM_UINT32_GET_BITS(p_sdt_etcam->etcam_table_id, sdt_hig32, DPP_SDT_H_ETCAM_TABLE_ID_BT_POS, DPP_SDT_H_ETCAM_TABLE_ID_BT_LEN); + ZXIC_COMM_UINT32_GET_BITS(p_sdt_etcam->no_as_rsp_mode, sdt_hig32, DPP_SDT_H_ETCAM_NOAS_RSP_MODE_BT_POS, DPP_SDT_H_ETCAM_NOAS_RSP_MODE_BT_LEN); + ZXIC_COMM_UINT32_GET_BITS(p_sdt_etcam->as_en, sdt_hig32, DPP_SDT_H_ETCAM_AS_EN_BT_POS, DPP_SDT_H_ETCAM_AS_EN_BT_LEN); + + ZXIC_COMM_UINT32_GET_BITS(tmp, sdt_hig32, DPP_SDT_H_ETCAM_AS_ERAM_BADDR_BT_POS, DPP_SDT_H_ETCAM_AS_ERAM_BADDR_BT_LEN); + ZXIC_COMM_UINT32_GET_BITS(p_sdt_etcam->as_eram_baddr, sdt_low32, DPP_SDT_L_ETCAM_AS_ERAM_BADDR_BT_POS, DPP_SDT_L_ETCAM_AS_ERAM_BADDR_BT_LEN); + ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(p_sdt_etcam->as_eram_baddr, (tmp << DPP_SDT_L_ETCAM_AS_ERAM_BADDR_BT_LEN)); + p_sdt_etcam->as_eram_baddr += (tmp << DPP_SDT_L_ETCAM_AS_ERAM_BADDR_BT_LEN); + + ZXIC_COMM_UINT32_GET_BITS(p_sdt_etcam->as_rsp_mode, sdt_low32, DPP_SDT_L_ETCAM_AS_RSP_MODE_BT_POS, DPP_SDT_L_ETCAM_AS_RSP_MODE_BT_LEN); + ZXIC_COMM_UINT32_GET_BITS(p_sdt_etcam->etcam_table_depth, sdt_low32, DPP_SDT_L_ETCAM_TABLE_DEPTH_BT_POS, DPP_SDT_L_ETCAM_TABLE_DEPTH_BT_LEN); + p_sdt_etcam->etcam_clutch_en = clutch_en; + break; + } + + case DPP_SDT_TBLT_PORTTBL: + { + p_sdt_porttbl = (DPP_SDTTBL_PORTTBL_T *)p_sdt_info; + p_sdt_porttbl->table_type = tbl_type; + p_sdt_porttbl->porttbl_clutch_en = clutch_en; + break; + } + + default: + { + ZXIC_COMM_TRACE_ERROR("SDT table_type[ %d ] is invalid!\n", tbl_type); + ZXIC_COMM_ASSERT(0); + return DPP_ERR; + } + } + + return DPP_OK; +} + +/***********************************************************/ +/** 从软件缓存中获取table data信息 +* @param dev_id 设备号 +* @param sdt_no 业务表对应的sdt号,0-255 +* @param p_sdt_data sdt表信息 +* +* @return +* @remark 无 +* @see +* @author lim @date 2020/04/16 +************************************************************/ +DPP_STATUS dpp_sdt_tbl_data_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 sdt_no, DPP_SDT_TBL_DATA_T *p_sdt_data) +{ + DPP_STATUS rc = 0; + + ZXIC_COMM_CHECK_INDEX(dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_INDEX(sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1); + + p_sdt_data->data_high32 = g_sdt_info[dev_id][sdt_no].data_high32; + p_sdt_data->data_low32 = g_sdt_info[dev_id][sdt_no].data_low32; + + return rc; +} + +/***********************************************************/ +/** 将sdt信息保存在软件缓存中 +* @param dev_id 设备号 +* @param sdt_no 业务表对应的sdt号 +* @param table_type SDT属性中的表类型，取值参考DPP_SDT_TABLE_TYPE_E的定义 +* @param p_sdt_info 写入的SDT表信息。 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author lim @date 2020/04/16 +************************************************************/ +DPP_STATUS dpp_soft_sdt_tbl_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 sdt_no, + ZXIC_UINT32 table_type, + DPP_SDT_TBL_DATA_T *p_sdt_info) +{ + DPP_STATUS rc = 0; + + ZXIC_COMM_CHECK_INDEX(dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_INDEX(sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1); + ZXIC_COMM_CHECK_POINT(p_sdt_info); + + /* 将table_type存储到软件缓存中 */ + g_table_type[dev_id][sdt_no] = table_type; + + /* 保存sdt信息 */ + g_sdt_info[dev_id][sdt_no].data_high32 = p_sdt_info->data_high32; + g_sdt_info[dev_id][sdt_no].data_low32 = p_sdt_info->data_low32; + + return rc; +} + +/***********************************************************/ +/** 从软件缓存中获取sdt信息 +* @param device_id 设备号 +* @param sdt_no 业务表对应的sdt号 +* @param p_sdt_info 写入的SDT属性。由table_type确定此ZXIC_VOID型指针对应的数据结构, 包括: \n +* DPP_SDTTBL_ERAM_T、DPP_SDTTBL_DDR_T、DPP_SDTTBL_HASH_T、DPP_SDTTBL_LPM_T、 +* DPP_SDTTBL_ETCAM_T。 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author lim @date 2020/04/16 +************************************************************/ +DPP_STATUS dpp_soft_sdt_tbl_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 sdt_no, ZXIC_VOID *p_sdt_info) +{ + DPP_STATUS rc = 0; + + DPP_SDT_TBL_DATA_T sdt_tbl = {0}; + + ZXIC_COMM_CHECK_INDEX(dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_INDEX(sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1); + ZXIC_COMM_CHECK_POINT(p_sdt_info); + + /** 从软件缓存读取sdt信息 */ + rc = dpp_sdt_tbl_data_get(dev_id, sdt_no, &sdt_tbl); + ZXIC_COMM_CHECK_RC(rc, "dpp_sdt_tbl_data_get"); + + rc = dpp_sdt_tbl_data_parser(dev_id, sdt_tbl.data_high32, sdt_tbl.data_low32, p_sdt_info); + ZXIC_COMM_CHECK_RC(rc, "dpp_sdt_tbl_data_parser"); + + return rc; +} + +/***********************************************************/ +/** 写SDT属性表条目到硬件表，同时向8个cluster写入 +* @param dev_id 设备号 +* @param sdt_no 业务表对应的sdt号 +* @param table_type SDT属性中的表类型，取值参考DPP_SDT_TABLE_TYPE_E的定义(仅添加操作时有效) +* @param p_sdt_info 写入的SDT属性(仅添加操作时有效)。由table_type确定此ZXIC_VOID型指针对应的数据结构, 包括: \n +* DPP_SDTTBL_ERAM_T、DPP_SDTTBL_DDR_T、DPP_SDTTBL_HASH_T、DPP_SDTTBL_LPM_T、\n +* DPP_SDTTBL_ETCAM_T、DPP_SDTTBL_PORTTBL_T。 +* @param opr_type 操作类型: 0-添加条目，1-删除条目. +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author 王春雷 @date 2015/07/11 +************************************************************/ +DPP_STATUS dpp_sdt_tbl_write(DPP_DEV_T *dev, + ZXIC_UINT32 sdt_no, + ZXIC_UINT32 table_type, + ZXIC_VOID *p_sdt_info, + ZXIC_UINT32 opr_type) +{ +#ifdef DPP_FLOW_HW_INIT + ZXIC_UINT32 i = 0; +#endif + DPP_STATUS rtn = 0; + DPP_SDT_TBL_DATA_T sdt_tbl = {0}; + DPP_SDTTBL_ERAM_T *p_sdt_eram = NULL; + DPP_SDTTBL_DDR3_T *p_sdt_ddr3 = NULL; + DPP_SDTTBL_HASH_T *p_sdt_hash = NULL; + DPP_SDTTBL_LPM_T *p_sdt_lpm = NULL; + DPP_SDTTBL_ETCAM_T *p_sdt_etcam = NULL; + DPP_SDTTBL_PORTTBL_T *p_sdt_porttbl = NULL; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1); + + /* 根据表类型解析数据 */ + if (opr_type) + { + /* delete sdt item */ + rtn = dpp_sdt_mgr_sdt_item_del(DEV_ID(dev), sdt_no); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_sdt_mgr_sdt_item_del"); + } + else + { + /* add sdt item*/ + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_sdt_info); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), table_type, DPP_SDT_TBLT_eRAM, DPP_SDT_TBLT_PORTTBL); + + switch (table_type) + { + case DPP_SDT_TBLT_eRAM: + { + p_sdt_eram = (DPP_SDTTBL_ERAM_T *)p_sdt_info; + ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, p_sdt_eram->eram_mode, DPP_SDT_H_ERAM_MODE_BT_POS, DPP_SDT_H_ERAM_MODE_BT_LEN); + ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, p_sdt_eram->eram_base_addr, DPP_SDT_H_ERAM_BASE_ADDR_BT_POS, DPP_SDT_H_ERAM_BASE_ADDR_BT_LEN); + ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, p_sdt_eram->eram_table_depth, DPP_SDT_L_ERAM_TABLE_DEPTH_BT_POS, DPP_SDT_L_ERAM_TABLE_DEPTH_BT_LEN); + ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, p_sdt_eram->eram_clutch_en, DPP_SDT_L_CLUTCH_EN_BT_POS, DPP_SDT_L_CLUTCH_EN_BT_LEN); + break; + } + + case DPP_SDT_TBLT_DDR3: + { + p_sdt_ddr3 = (DPP_SDTTBL_DDR3_T *)p_sdt_info; + + /** 添加操作必须保证sdt号和ddr存储的sdt号一致 */ + ZXIC_COMM_ASSERT(sdt_no == p_sdt_ddr3->ddr3_sdt_num ); + + ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, p_sdt_ddr3->ddr3_base_addr, DPP_SDT_H_DDR3_BASE_ADDR_BT_POS, DPP_SDT_H_DDR3_BASE_ADDR_BT_LEN); + ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, p_sdt_ddr3->ddr3_share_type, DPP_SDT_H_DDR3_SHARE_TYPE_BT_POS, DPP_SDT_H_DDR3_SHARE_TYPE_BT_LEN); + ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, p_sdt_ddr3->ddr3_rw_len, DPP_SDT_H_DDR3_RW_LEN_BT_POS, DPP_SDT_H_DDR3_RW_LEN_BT_LEN); + ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + ((p_sdt_ddr3->ddr3_sdt_num) >> DPP_SDT_L_DDR3_SDT_NUM_BT_LEN), + DPP_SDT_H_DDR3_SDT_NUM_BT_POS, + DPP_SDT_H_DDR3_SDT_NUM_BT_LEN); + ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, + DPP_SDT_GET_LOW_DATA((p_sdt_ddr3->ddr3_sdt_num), DPP_SDT_L_DDR3_SDT_NUM_BT_LEN), + DPP_SDT_L_DDR3_SDT_NUM_BT_POS, + DPP_SDT_L_DDR3_SDT_NUM_BT_LEN); + ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, p_sdt_ddr3->ddr3_ecc_en, DPP_SDT_L_DDR3_ECC_EN_BT_POS, DPP_SDT_L_DDR3_ECC_EN_BT_LEN); + ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, p_sdt_ddr3->ddr3_clutch_en, DPP_SDT_L_CLUTCH_EN_BT_POS, DPP_SDT_L_CLUTCH_EN_BT_LEN); + break; + } + + case DPP_SDT_TBLT_HASH: + { + p_sdt_hash = (DPP_SDTTBL_HASH_T *)p_sdt_info; + ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, p_sdt_hash->hash_id, DPP_SDT_H_HASH_ID_BT_POS, DPP_SDT_H_HASH_ID_BT_LEN); + ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, p_sdt_hash->hash_table_width, DPP_SDT_H_HASH_TABLE_WIDTH_BT_POS, DPP_SDT_H_HASH_TABLE_WIDTH_BT_LEN); + ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, p_sdt_hash->key_size, DPP_SDT_H_HASH_KEY_SIZE_BT_POS, DPP_SDT_H_HASH_KEY_SIZE_BT_LEN); + ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, p_sdt_hash->hash_table_id, DPP_SDT_H_HASH_TABLE_ID_BT_POS, DPP_SDT_H_HASH_TABLE_ID_BT_LEN); + ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, p_sdt_hash->learn_en, DPP_SDT_H_LEARN_EN_BT_POS, DPP_SDT_H_LEARN_EN_BT_LEN); + ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, p_sdt_hash->keep_alive, DPP_SDT_H_KEEP_ALIVE_BT_POS, DPP_SDT_H_KEEP_ALIVE_BT_LEN); + ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + ((p_sdt_hash->keep_alive_baddr) >> DPP_SDT_L_KEEP_ALIVE_BADDR_BT_LEN), + DPP_SDT_H_KEEP_ALIVE_BADDR_BT_POS, + DPP_SDT_H_KEEP_ALIVE_BADDR_BT_LEN); + ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, + DPP_SDT_GET_LOW_DATA((p_sdt_hash->keep_alive_baddr), DPP_SDT_L_KEEP_ALIVE_BADDR_BT_LEN), + DPP_SDT_L_KEEP_ALIVE_BADDR_BT_POS, + DPP_SDT_L_KEEP_ALIVE_BADDR_BT_LEN); + ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, p_sdt_hash->rsp_mode, DPP_SDT_L_RSP_MODE_BT_POS, DPP_SDT_L_RSP_MODE_BT_LEN); + ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, p_sdt_hash->hash_clutch_en, DPP_SDT_L_CLUTCH_EN_BT_POS, DPP_SDT_L_CLUTCH_EN_BT_LEN); + break; + } + + case DPP_SDT_TBLT_LPM: + { + p_sdt_lpm = (DPP_SDTTBL_LPM_T *)p_sdt_info; + ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, p_sdt_lpm->lpm_v46_id, DPP_SDT_H_LPM_V46ID_BT_POS, DPP_SDT_H_LPM_V46ID_BT_LEN); + ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, p_sdt_lpm->rsp_mode, DPP_SDT_H_LPM_RSP_MODE_BT_POS, DPP_SDT_H_LPM_RSP_MODE_BT_LEN); + ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, p_sdt_lpm->lpm_table_depth, DPP_SDT_L_LPM_TABLE_DEPTH_BT_POS, DPP_SDT_L_LPM_TABLE_DEPTH_BT_LEN); + ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, p_sdt_lpm->lpm_clutch_en, DPP_SDT_L_CLUTCH_EN_BT_POS, DPP_SDT_L_CLUTCH_EN_BT_LEN); + break; + } + + case DPP_SDT_TBLT_eTCAM: + { + p_sdt_etcam = (DPP_SDTTBL_ETCAM_T *)p_sdt_info; + ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, p_sdt_etcam->etcam_id, DPP_SDT_H_ETCAM_ID_BT_POS, DPP_SDT_H_ETCAM_ID_BT_LEN); + ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, p_sdt_etcam->etcam_key_mode, DPP_SDT_H_ETCAM_KEY_MODE_BT_POS, DPP_SDT_H_ETCAM_KEY_MODE_BT_LEN); + ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, p_sdt_etcam->etcam_table_id, DPP_SDT_H_ETCAM_TABLE_ID_BT_POS, DPP_SDT_H_ETCAM_TABLE_ID_BT_LEN); + ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, p_sdt_etcam->no_as_rsp_mode, DPP_SDT_H_ETCAM_NOAS_RSP_MODE_BT_POS, DPP_SDT_H_ETCAM_NOAS_RSP_MODE_BT_LEN); + ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, p_sdt_etcam->as_en, DPP_SDT_H_ETCAM_AS_EN_BT_POS, DPP_SDT_H_ETCAM_AS_EN_BT_LEN); + + ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + ((p_sdt_etcam->as_eram_baddr) >> DPP_SDT_L_ETCAM_AS_ERAM_BADDR_BT_LEN), + DPP_SDT_H_ETCAM_AS_ERAM_BADDR_BT_POS, + DPP_SDT_H_ETCAM_AS_ERAM_BADDR_BT_LEN); + ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, + DPP_SDT_GET_LOW_DATA((p_sdt_etcam->as_eram_baddr), DPP_SDT_L_ETCAM_AS_ERAM_BADDR_BT_LEN), + DPP_SDT_L_ETCAM_AS_ERAM_BADDR_BT_POS, + DPP_SDT_L_ETCAM_AS_ERAM_BADDR_BT_LEN); + + ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, p_sdt_etcam->as_rsp_mode, DPP_SDT_L_ETCAM_AS_RSP_MODE_BT_POS, DPP_SDT_L_ETCAM_AS_RSP_MODE_BT_LEN); + ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, p_sdt_etcam->etcam_table_depth, DPP_SDT_L_ETCAM_TABLE_DEPTH_BT_POS, DPP_SDT_L_ETCAM_TABLE_DEPTH_BT_LEN); + ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, p_sdt_etcam->etcam_clutch_en, DPP_SDT_L_CLUTCH_EN_BT_POS, DPP_SDT_L_CLUTCH_EN_BT_LEN); + break; + } + + case DPP_SDT_TBLT_PORTTBL: + { + p_sdt_porttbl = (DPP_SDTTBL_PORTTBL_T *)p_sdt_info; + ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, p_sdt_porttbl->porttbl_clutch_en, DPP_SDT_L_CLUTCH_EN_BT_POS, DPP_SDT_L_CLUTCH_EN_BT_LEN); + break; + } + + default: + { + ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "SDT table_type[ %d ] is invalid!\n", table_type); + return DPP_ERR; + } + } + + ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, table_type, DPP_SDT_H_TBL_TYPE_BT_POS, DPP_SDT_H_TBL_TYPE_BT_LEN); + + /* 将sdt信息存储到软件缓存中 */ + dpp_soft_sdt_tbl_set(DEV_ID(dev), sdt_no, table_type, &sdt_tbl); + + /* 缓存到软件 */ + rtn = dpp_sdt_mgr_sdt_item_add(DEV_ID(dev), sdt_no, sdt_tbl.data_high32, sdt_tbl.data_low32); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_sdt_mgr_sdt_item_add"); + } +#ifdef DPP_FLOW_HW_INIT + for (i = 0; i < DPP_PPU_CLUSTER_NUM; i++) + { + /*cluster 未启用,不需要配置该cluster相关的寄存器*/ + if (!dpp_ppu_cls_use_get(DEV_ID(dev), i)) + { + continue; + } + + rtn = dpp_ppu_sdt_tbl_write(dev, i, sdt_no, &sdt_tbl); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_ppu_sdt_tbl_write"); + } +#endif + return DPP_OK; +} + +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/sdt/dpp_sdt_mgr.c b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/sdt/dpp_sdt_mgr.c new file mode 100755 index 0000000..1fb381c --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/sdt/dpp_sdt_mgr.c @@ -0,0 +1,739 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_sdt_mgr.c +* 文件标识 : +* 内容摘要 : SDT属性软件缓存，以及接收上层配置并下发给底层设备 +* 其它说明 : +* 当前版本 : +* 作 者 : 王春雷 +* 完成日期 : 2015/06/25 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ + +#include "zxic_common.h" + +#include "dpp_dev.h" +#include "dpp_sdt_def.h" +#include "dpp_sdt.h" +#include "dpp_sdt_mgr.h" +#include "dpp_se_api.h" + +static DPP_SDT_MGR_T g_sdt_mgr = {0}; + +static ZXIC_UINT32 g_sdt_mgr_debug = 1; + +#define DPP_SDT_MGR_PTR_GET() (&g_sdt_mgr) + +#define DPP_SDT_SOFT_TBL_GET(id) (g_sdt_mgr.sdt_tbl_array[id]) + +ZXIC_UINT32 dpp_sdt_mgr_init(ZXIC_VOID) +{ + if (!g_sdt_mgr.is_init) + { + g_sdt_mgr.channel_num = 0; + g_sdt_mgr.is_init = 1; + // g_sdt_mgr.p_sdt_mgr_smmu0_mux = dpp_tbl_dir_sdt_smmu0_mux; + // g_sdt_mgr.p_sdt_mgr_smmu1_mux = dpp_tbl_dir_sdt_smmu1_mux; + // g_sdt_mgr.p_sdt_mgr_hash_mux = dpp_tbl_dir_sdt_hash_mux; + // g_sdt_mgr.p_sdt_mgr_lpm_mux = dpp_tbl_dir_sdt_lpm_mux; + // g_sdt_mgr.p_sdt_mgr_etcam_mux = dpp_tbl_dir_sdt_etcam_mux; + ZXIC_COMM_MEMSET(g_sdt_mgr.sdt_tbl_array, 0, DPP_DEV_CHANNEL_MAX * sizeof(DPP_SDT_SOFT_TABLE_T *)); + } + + return DPP_OK; +} + +ZXIC_UINT32 dpp_sdt_mgr_create(ZXIC_UINT32 dev_id) +{ + DPP_SDT_SOFT_TABLE_T *p_sdt_tbl_temp = NULL; + DPP_SDT_MGR_T *p_sdt_mgr = NULL; + + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + + p_sdt_mgr = DPP_SDT_MGR_PTR_GET(); + + if (DPP_SDT_SOFT_TBL_GET(dev_id) == NULL) + { + p_sdt_tbl_temp = ZXIC_COMM_MALLOC(sizeof(DPP_SDT_SOFT_TABLE_T)); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_sdt_tbl_temp); /* mod for KW_0411 # 474 */ + + p_sdt_tbl_temp->device_id = dev_id; + ZXIC_COMM_MEMSET(p_sdt_tbl_temp->sdt_array, 0, DPP_DEV_SDT_ID_MAX * sizeof(DPP_SDT_ITEM_T)); + + DPP_SDT_SOFT_TBL_GET(dev_id) = p_sdt_tbl_temp; + ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(dev_id, p_sdt_mgr->channel_num, 1); + p_sdt_mgr->channel_num++; + } + else + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "Error: dpp_sdt_mgr_create for dev[%d] is called repeatedly!\n", dev_id); + } + + return DPP_OK; +} + +ZXIC_UINT32 dpp_sdt_mgr_destroy(ZXIC_UINT32 dev_id) +{ + DPP_SDT_SOFT_TABLE_T *p_sdt_tbl_temp = NULL; + DPP_SDT_MGR_T *p_sdt_mgr = NULL; + + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + + p_sdt_tbl_temp = DPP_SDT_SOFT_TBL_GET(dev_id); + p_sdt_mgr = DPP_SDT_MGR_PTR_GET(); + + if (NULL != p_sdt_tbl_temp) + { + ZXIC_COMM_FREE(p_sdt_tbl_temp); + } + + DPP_SDT_SOFT_TBL_GET(dev_id) = NULL; + + ZXIC_COMM_CHECK_DEV_INDEX_SUB_OVERFLOW_NO_ASSERT(dev_id, p_sdt_mgr->channel_num, 1); + p_sdt_mgr->channel_num--; + + return DPP_OK; +} + + +#if 1 +/***********************************************************/ +/** 向软件缓存中添加SDT表条目 +* @param dev_id 设备号 +* @param sdt_no 业务表对应的sdt号 +* @param sdt_hig32 SDT属性高32bit +* @param sdt_low32 SDT属性低32bit +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author 王春雷 @date 2015/07/13 +************************************************************/ +DPP_STATUS dpp_sdt_mgr_sdt_item_add(ZXIC_UINT32 dev_id, ZXIC_UINT32 sdt_no, ZXIC_UINT32 sdt_hig32, ZXIC_UINT32 sdt_low32) +{ + DPP_SDT_SOFT_TABLE_T *p_sdt_soft_tbl = NULL; + DPP_SDT_ITEM_T *p_sdt_item = NULL; + + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1); + + p_sdt_soft_tbl = DPP_SDT_SOFT_TBL_GET(dev_id); + + if (NULL == p_sdt_soft_tbl) + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "Error: dpp_sdt_mgr_sdt_item_add soft sdt table not Init! \n"); + ZXIC_COMM_ASSERT(0); + return DPP_RC_TABLE_SDT_MGR_INVALID; + } + + if (dev_id != p_sdt_soft_tbl->device_id) + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "Error: dpp_sdt_mgr_sdt_item_add soft sdt table Item Invalid! \n"); + ZXIC_COMM_ASSERT(0); + return DPP_RC_TABLE_PARA_INVALID; + } + + /*添加SDT表项*/ + p_sdt_item = &(p_sdt_soft_tbl->sdt_array[sdt_no]); + p_sdt_item->valid = DPP_SDT_VALID; + p_sdt_item->table_cfg[0] = sdt_hig32; /* hig32 */ + p_sdt_item->table_cfg[1] = sdt_low32; /* low32 */ + + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "dpp_sdt_mgr_sdt_item_add 0x%08x 0x%08x \n", p_sdt_item->table_cfg[0], p_sdt_item->table_cfg[1]); + + return DPP_OK; +} + +/***********************************************************/ +/** 从软件缓存中读取SDT表条目 +* @param dev_id 设备号 +* @param sdt_no 业务表对应的sdt号 +* @param p_sdt_hig32 SDT属性高32bit +* @param p_sdt_low32 SDT属性低32bit +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author 王春雷 @date 2015/07/13 +************************************************************/ +DPP_STATUS dpp_sdt_mgr_sdt_item_srh(ZXIC_UINT32 dev_id, ZXIC_UINT32 sdt_no, ZXIC_UINT32 *p_sdt_hig32, ZXIC_UINT32 *p_sdt_low32) +{ + DPP_STATUS rc = DPP_OK; + DPP_SDT_SOFT_TABLE_T *p_sdt_soft_tbl = NULL; + DPP_SDT_ITEM_T *p_sdt_item = NULL; + + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_sdt_hig32); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_sdt_low32); + + p_sdt_soft_tbl = DPP_SDT_SOFT_TBL_GET(dev_id); + + if (NULL == p_sdt_soft_tbl) + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "Error: dpp_sdt_mgr_sdt_item_srh Soft Table not Init! \n"); + ZXIC_COMM_ASSERT(0); + return DPP_RC_TABLE_SDT_MGR_INVALID; + } + + if (dev_id != p_sdt_soft_tbl->device_id) + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "Error: dpp_sdt_mgr_sdt_item_srh Soft Table Item Invalid ! \n"); + ZXIC_COMM_ASSERT(0); + return DPP_RC_TABLE_PARA_INVALID; + } + + /* 获取SDT表项 */ + p_sdt_item = &p_sdt_soft_tbl->sdt_array[sdt_no]; + + if (DPP_SDT_VALID == p_sdt_item->valid) + { + *p_sdt_hig32 = p_sdt_item->table_cfg[0]; + *p_sdt_low32 = p_sdt_item->table_cfg[1]; + } + else + { + *p_sdt_hig32 = 0xFFFFFFFF; + *p_sdt_low32 = 0xFFFFFFFF; + } + + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "dpp_sdt_mgr_sdt_item_srh is %s: sdt_no: 0x%08x sdt_hig32:0x%08x sdt_low32:0x%08x \n", ((DPP_SDT_VALID == p_sdt_item->valid) ? ("success") : ("fail")), sdt_no, *p_sdt_hig32, *p_sdt_low32); + + return rc; +} + +/***********************************************************/ +/** 从软件缓存中删除SDT表条目 +* @param dev_id 设备号 +* @param sdt_no 业务表对应的sdt号 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author 王春雷 @date 2015/07/13 +************************************************************/ +DPP_STATUS dpp_sdt_mgr_sdt_item_del(ZXIC_UINT32 dev_id, ZXIC_UINT32 sdt_no) +{ + DPP_SDT_SOFT_TABLE_T *p_sdt_soft_tbl = NULL; + DPP_SDT_ITEM_T *p_sdt_item = NULL; + + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1); + + p_sdt_soft_tbl = DPP_SDT_SOFT_TBL_GET(dev_id); + + if (NULL != p_sdt_soft_tbl) + { + if (dev_id != p_sdt_soft_tbl->device_id) + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "Error: dpp_sdt_mgr_sdt_item_del Soft Table Item Invalid ! \n"); + ZXIC_COMM_ASSERT(0); + return DPP_RC_TABLE_PARA_INVALID; + } + + p_sdt_item = &p_sdt_soft_tbl->sdt_array[sdt_no]; + p_sdt_item->valid = DPP_SDT_INVALID; + p_sdt_item->table_cfg[0] = 0; + p_sdt_item->table_cfg[1] = 0; + } + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "dpp_sdt_mgr_sdt_item_del sdt_no: 0x%08x \n", sdt_no); + return DPP_OK; +} + +#endif + + +#if 1 +/********************************************************************* + * 函数名称：NpeSdtMgr_GetTblType + * + * 功能描述: + * + * 输入参数： + * 输出参数： + * 返 回 值： + * 全局变量： + * 注 释： + ============================================================ + * 修改记录: + * 修改日期 版本号 修改人 修改内容 + * 20120327 v1.0 石金锋 创建 + ============================================================ + * + *********************************************************************/ +DPP_TBL_TYPE_E dpp_sdt_mgr_get_tbl_type(ZXIC_UINT32 dev_id, ZXIC_UINT32 sdt_no) +{ + ZXIC_UINT32 rtn = 0; + DPP_TBL_TYPE_E table_type = 0; + ZXIC_UINT32 table_cfg[DPP_SDT_CFG_LEN] = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1); + + rtn = dpp_sdt_mgr_sdt_item_srh(dev_id, sdt_no, &(table_cfg[0]), &(table_cfg[1])); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "dpp_sdt_mgr_sdt_item_srh"); + + table_type = (DPP_TBL_TYPE_E)((table_cfg[0] >> 29) & 0x7); + + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "dpp_sdt_mgr_get_tbl_type: dev_id: %d, sdt_no: %d, table_type: %d. \n", dev_id, sdt_no, table_type); + + return table_type; +} + +/********************************************************************* + * 函数名称：NpeDriver_GetAsTableEn + * + * 功能描述: + * + * 输入参数： + * 输出参数： + * 返 回 值： + * 全局变量： + * 注 释： + ============================================================ + * 修改记录: + * 修改日期 版本号 修改人 修改内容 + * 20120829 v1.8 徐东伟 创建 + ============================================================ + * + *********************************************************************/ +ZXIC_UINT32 dpp_sdt_mgr_get_as_table_en(ZXIC_UINT32 *table_cfg, ZXIC_UINT32 *p_as_en) +{ + ZXIC_COMM_CHECK_POINT(table_cfg); + ZXIC_COMM_CHECK_POINT(p_as_en); + + *p_as_en = (table_cfg[0] & 0x00004000) >> 14; + + return DPP_OK; +} + +/********************************************************************* + * 函数名称：NpeDriver_GetAsTableType + * + * 功能描述: + * + * 输入参数： + * 输出参数： + * 返 回 值： + * 全局变量： + * 注 释： + ============================================================ + * 修改记录: + * 修改日期 版本号 修改人 修改内容 + * 20120829 v1.8 徐东伟 创建 + ============================================================ + * + *********************************************************************/ +ZXIC_UINT32 dpp_sdt_mgr_get_as_table_type(ZXIC_UINT32 *table_cfg, DPP_TBL_TYPE_E *p_as_type) +{ + ZXIC_COMM_CHECK_POINT(table_cfg); + ZXIC_COMM_CHECK_POINT(p_as_type); + + *p_as_type = (DPP_TBL_TYPE_E)((table_cfg[0] & 0x00003000) >> 12); + + return DPP_OK; +} + +/********************************************************************* + * 函数名称：NpeDriver_GetDDR3Page + * + * 功能描述: + * + * 输入参数： + * 输出参数： + * 返 回 值： + * 全局变量： + * 注 释： + ============================================================ + * 修改记录: + * 修改日期 版本号 修改人 修改内容 + * 20120829 v1.8 徐东伟 创建 + ============================================================ + * + *********************************************************************/ +ZXIC_UINT32 dpp_sdt_mgr_get_ddr3_page(ZXIC_UINT32 copy_type, ZXIC_UINT32 copy_position, ZXIC_UINT32 *p_page) +{ + ZXIC_COMM_CHECK_POINT(p_page); + + return DPP_OK; +} + +/********************************************************************* + * 函数名称：NpeSdtMgr_SdtSmmu0Print + * + * 功能描述: + * + * 输入参数： + * 输出参数： + * 返 回 值： + * 全局变量： + * 注 释： + ============================================================ + * 修改记录: + * 修改日期 版本号 修改人 修改内容 + * 20120327 v1.0 石金锋 创建 + ============================================================ + * + *********************************************************************/ +ZXIC_VOID dpp_sdt_mgr_sdt_smmu0_print(DPP_SDT_SMMU0_T *p_sdt_smmu0) +{ + if (NULL == p_sdt_smmu0) + { + ZXIC_COMM_TRACE_DEBUG("Error: dpp_sdt_mgr_sdt_smmu0_print Input Parameter Invalid !\n"); + return; + } + + if (g_sdt_mgr_debug) + { + ZXIC_COMM_TRACE_DEBUG("wr_rd_flag: 0x%x\n", p_sdt_smmu0->wr_rd_flag); + ZXIC_COMM_TRACE_DEBUG("tbl_index: 0x%x\n", p_sdt_smmu0->tbl_index); + ZXIC_COMM_TRACE_DEBUG("mode: 0x%x\n", p_sdt_smmu0->mode); + ZXIC_COMM_TRACE_DEBUG("tbl_base_addr:0x%x\n", p_sdt_smmu0->tbl_base_addr); + ZXIC_COMM_TRACE_DEBUG("tbl_depth: 0x%x\n", p_sdt_smmu0->tbl_depth); + ZXIC_COMM_TRACE_DEBUG("p_data: 0x%08x 0x%08x 0x%08x 0x%08x\n", *((ZXIC_UINT32 *)p_sdt_smmu0->p_data + 0), + *((ZXIC_UINT32 *)p_sdt_smmu0->p_data + 1), + *((ZXIC_UINT32 *)p_sdt_smmu0->p_data + 2), + *((ZXIC_UINT32 *)p_sdt_smmu0->p_data + 3)); + } + + return; +} + +/********************************************************************* + * 函数名称：NpeSdtMgr_SdtSmmu1Print + * + * 功能描述: + * + * 输入参数： + * 输出参数： + * 返 回 值： + * 全局变量： + * 注 释： + ============================================================ + * 修改记录: + * 修改日期 版本号 修改人 修改内容 + * 20120327 v1.0 石金锋 创建 + ============================================================ + * + *********************************************************************/ +ZXIC_VOID dpp_sdt_mgr_sdt_smmu1_print(DPP_SDT_SMMU1_T *p_sdt_smmu1) +{ + ZXIC_UINT32 i = 0; + ZXIC_UINT32 mode = 4; + + if (NULL == p_sdt_smmu1) + { + ZXIC_COMM_TRACE_DEBUG("Error: dpp_sdt_mgr_sdt_smmu1_print Input Parameter Invalid !\n"); + return; + } + + if (g_sdt_mgr_debug) + { + ZXIC_COMM_TRACE_DEBUG("dwdwCrcChkEn: 0x%x\n", p_sdt_smmu1->crc_chk_en); + ZXIC_COMM_TRACE_DEBUG("wr_rd_flag: 0x%x\n", p_sdt_smmu1->wr_rd_flag); + ZXIC_COMM_TRACE_DEBUG("tbl_index: 0x%x\n", p_sdt_smmu1->tbl_index); + ZXIC_COMM_TRACE_DEBUG("tbl_base_addr: 0x%x\n", p_sdt_smmu1->tbl_base_addr); + ZXIC_COMM_TRACE_DEBUG("ddr_share_type: 0x%x\n", p_sdt_smmu1->ddr_share_type); + ZXIC_COMM_TRACE_DEBUG("ddr_mode: 0x%x\n", p_sdt_smmu1->ddr_mode); + + ZXIC_COMM_TRACE_DEBUG("p_data:"); + + if (0 != p_sdt_smmu1->ddr_mode) + { + mode = 8; + } + + for (i = 0; i < mode; i++) + { + ZXIC_COMM_TRACE_DEBUG("0x%08x ", *((ZXIC_UINT32 *)p_sdt_smmu1->p_data + i)); + } + + ZXIC_COMM_TRACE_DEBUG("\n"); + } + + return; +} + +/********************************************************************* + * 函数名称：NpeSdtMgr_SdtHashPrint + * + * 功能描述: + * + * 输入参数： + * 输出参数： + * 返 回 值： + * 全局变量： + * 注 释： + ============================================================ + * 修改记录: + * 修改日期 版本号 修改人 修改内容 + * 20120327 v1.0 石金锋 创建 + ============================================================ + * + *********************************************************************/ +ZXIC_VOID dpp_sdt_mgr_sdt_hash_print(DPP_SDT_HASH_T *p_sdt_hash) +{ + ZXIC_UINT32 i = 0; + + if (NULL == p_sdt_hash) + { + ZXIC_COMM_TRACE_DEBUG("Error: dpp_sdt_mgr_sdt_hash_print Input Parameter Invalid !\n"); + return; + } + + if (g_sdt_mgr_debug) + { + ZXIC_COMM_TRACE_DEBUG("addr:0x%x\n", p_sdt_hash->addr); + ZXIC_COMM_TRACE_DEBUG("length:%d\n", p_sdt_hash->length); + ZXIC_COMM_TRACE_DEBUG("hash_id:%d\n", p_sdt_hash->id); + ZXIC_COMM_TRACE_DEBUG("table_id:%d\n", p_sdt_hash->tbl_id); + ZXIC_COMM_TRACE_DEBUG("hash_tbl_width:%d\n", p_sdt_hash->key_type); + ZXIC_COMM_TRACE_DEBUG("hash_key_size:%d\n", p_sdt_hash->key_size); + ZXIC_COMM_TRACE_DEBUG("rsp_mode:%d\n", p_sdt_hash->rsp_mode); + + ZXIC_COMM_TRACE_DEBUG("p_data:"); + + for (i = 0; i < p_sdt_hash->length; i++) + { + ZXIC_COMM_TRACE_DEBUG("0x%08x ", *((ZXIC_UINT32 *)p_sdt_hash->p_data + i)); + } + + ZXIC_COMM_TRACE_DEBUG("\n"); + } + + return; +} + +/***********************************************************/ +/** +* @param p_sdt_lpm +* +* @return +* @remark 无 +* @see +* @author 王春雷 @date 2014/06/16 +************************************************************/ +ZXIC_VOID dpp_sdt_mgr_sdt_etcam_print(DPP_SDT_ETCAM_T *p_sdt_etcam) +{ + ZXIC_UINT32 i = 0; + + if (NULL == p_sdt_etcam) + { + ZXIC_COMM_TRACE_DEBUG("Error: dpp_sdt_mgr_sdt_etcam_print Input Parameter Invalid !\n"); + return; + } + + if (g_sdt_mgr_debug) + { + ZXIC_COMM_TRACE_DEBUG("table_id :0x%x\n", p_sdt_etcam->tbl_id); + ZXIC_COMM_TRACE_DEBUG("addr :0x%x\n", p_sdt_etcam->addr); + ZXIC_COMM_TRACE_DEBUG("key_mode :%d\n", p_sdt_etcam->key_mode); + ZXIC_COMM_TRACE_DEBUG("rsp_mode :%d\n", p_sdt_etcam->rsp_mode); + ZXIC_COMM_TRACE_DEBUG("length :%d\n", p_sdt_etcam->length); + ZXIC_COMM_TRACE_DEBUG("as_en :%d\n", p_sdt_etcam->as_en); + ZXIC_COMM_TRACE_DEBUG("as_eram_baddr :0x%x\n", p_sdt_etcam->as_eram_baddr); + ZXIC_COMM_TRACE_DEBUG("as_rsp_mode :%d\n", p_sdt_etcam->as_rsp_mode); + ZXIC_COMM_TRACE_DEBUG("p_data :"); + + for (i = 0; i < p_sdt_etcam->length; i++) + { + ZXIC_COMM_TRACE_DEBUG("0x%08x ", *((ZXIC_UINT32 *)p_sdt_etcam->p_data + i)); + } + + ZXIC_COMM_TRACE_DEBUG("\n"); + } + + return; +} + +/********************************************************************* + * 函数名称：NpeDriver_GetEram128Params + * + * 功能描述: + * + * 输入参数： + * 输出参数： + * 返 回 值： + * 全局变量： + * 注 释： + ============================================================ + * 修改记录: + * 修改日期 版本号 修改人 修改内容 + * 20120924 v1.0 石金锋/徐东伟 创建 + ============================================================ + * + *********************************************************************/ +ZXIC_UINT32 dpp_sdt_mgr_get_eram128_params(ZXIC_UINT32 dev_id, ZXIC_UINT32 table_id, DPP_ERAM128_PARAMS_T *p_eram128_params) +{ + ZXIC_UINT32 rtn = 0; + ZXIC_UINT32 table_cfg[DPP_SDT_CFG_LEN] = {0}; + DPP_ERAM128_MODE_E e128Mode = 0; + + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, table_id, 0, DPP_DEV_SDT_ID_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_eram128_params); + + rtn = dpp_sdt_mgr_sdt_item_srh(dev_id, table_id, &(table_cfg[0]), &(table_cfg[1])); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "dpp_sdt_mgr_sdt_item_srh"); + + /** modify By LiuShuo @2016年2月25日10:01:31*/ + e128Mode = (DPP_ERAM128_MODE_E)((table_cfg[0] & 0x1c000000) >> 26); + p_eram128_params->tbl_base_addr = ((table_cfg[0] & 0x003FFFF80) >> 7); + p_eram128_params->tbl_depth = ((table_cfg[1] & 0x00007FFFE) >> 1); + p_eram128_params->eram128_mode = e128Mode; + + switch (p_eram128_params->eram128_mode) + { + case Eram128Mode_1BITS: + case Eram128Mode_2BITS: + case Eram128Mode_4BITS: + case Eram128Mode_8BITS: + case Eram128Mode_16BITS: + case Eram128Mode_32BITS: + { + p_eram128_params->count = 1; + break; + } + + case Eram128Mode_64BITS: + { + p_eram128_params->count = 2; + break; + } + + default: + { + p_eram128_params->count = 4; /* eRam默认写4个32bit */ + } + } + + return DPP_OK; +} + +/********************************************************************* + * 函数名称：NpeSdtMgr_GetDDR3Params + * + * 功能描述: + * + * 输入参数： + * 输出参数： + * 返 回 值： + * 全局变量： + * 注 释： + ============================================================ + * 修改记录: + * 修改日期 版本号 修改人 修改内容 + * 20120911 v1.8 徐东伟 创建 + ============================================================ + * + *********************************************************************/ +ZXIC_UINT32 dpp_sdt_mgr_get_ddr3_params(ZXIC_UINT32 dev_id, ZXIC_UINT32 table_id, DPP_DDR3_PARAMS_T *p_ddr3_params) +{ + ZXIC_UINT32 rtn = 0; + ZXIC_UINT32 table_cfg[DPP_SDT_CFG_LEN] = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, table_id, 0, DPP_DEV_SDT_ID_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_ddr3_params); + + rtn = dpp_sdt_mgr_sdt_item_srh(dev_id, table_id, &(table_cfg[0]), &(table_cfg[1])); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "dpp_sdt_mgr_sdt_item_srh"); + + p_ddr3_params->base_addr = ((table_cfg[0] & 0x1FFFFE00) >> 9); + p_ddr3_params->tbl_share_mode = ((table_cfg[0] & 0x00000180) >> 7); + p_ddr3_params->ddr3_mode = ((table_cfg[0] & 0x00000060) >> 5); + p_ddr3_params->crc_check = ((table_cfg[1] & 0x10000000) >> 28); + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, p_ddr3_params->ddr3_mode, DDR3Mode_128BITS, DDR3Mode_512BITS); + p_ddr3_params->wr_rd_count = 4U << p_ddr3_params->ddr3_mode; /* 根据DDR3模式计算有效数据长度，以4字节为单位 */ + + return DPP_OK; +} + +/********************************************************************* + * 函数名称：NpeDriver_GetHashParams + * + * 功能描述: + * + * 输入参数： + * 输出参数： + * 返 回 值： + * 全局变量： + * 注 释： + ============================================================ + * 修改记录: + * 修改日期 版本号 修改人 修改内容 + * 20120924 v1.0 石金锋/徐东伟 创建 + ============================================================ + * + *********************************************************************/ +ZXIC_UINT32 dpp_sdt_mgr_get_hash_params(ZXIC_UINT32 dev_id, ZXIC_UINT32 table_id, DPP_HASH_PARAMS_T *p_hash_params) +{ + ZXIC_UINT32 rtn = 0; + ZXIC_UINT32 table_cfg[DPP_SDT_CFG_LEN] = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, table_id, 0, DPP_DEV_SDT_ID_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_hash_params); + + rtn = dpp_sdt_mgr_sdt_item_srh(dev_id, table_id, &(table_cfg[0]), &(table_cfg[1])); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "dpp_sdt_mgr_sdt_item_srh"); + + ZXIC_COMM_UINT32_GET_BITS(p_hash_params->hash_id, table_cfg[0], DPP_SDT_H_HASH_ID_BT_POS, DPP_SDT_H_HASH_ID_BT_LEN); + ZXIC_COMM_UINT32_GET_BITS(p_hash_params->key_tbl_width, table_cfg[0], DPP_SDT_H_HASH_TABLE_WIDTH_BT_POS, DPP_SDT_H_HASH_TABLE_WIDTH_BT_LEN); + ZXIC_COMM_UINT32_GET_BITS(p_hash_params->key_size, table_cfg[0], DPP_SDT_H_HASH_KEY_SIZE_BT_POS, DPP_SDT_H_HASH_KEY_SIZE_BT_LEN); + ZXIC_COMM_UINT32_GET_BITS(p_hash_params->table_id, table_cfg[0], DPP_SDT_H_HASH_TABLE_ID_BT_POS, DPP_SDT_H_HASH_TABLE_ID_BT_LEN); + ZXIC_COMM_UINT32_GET_BITS(p_hash_params->rsp_mode, table_cfg[1], DPP_SDT_L_RSP_MODE_BT_POS, DPP_SDT_L_RSP_MODE_BT_LEN); + return DPP_OK; +} + +/********************************************************************* + * 函数名称：NpeDriver_GetTcamParams + * + * 功能描述: + * + * 输入参数： + * 输出参数： + * 返 回 值： + * 全局变量： + * 注 释： + ============================================================ + * 修改记录: + * 修改日期 版本号 修改人 修改内容 + * 20120924 v1.0 石金锋/徐东伟 创建 + ============================================================ + * + *********************************************************************/ +ZXIC_UINT32 dpp_sdt_mgr_get_etcam_params(ZXIC_UINT32 dev_id, ZXIC_UINT32 table_id, DPP_ETCAM_PARAMS_T *p_etcam_params) +{ + ZXIC_UINT32 rtn = 0; + ZXIC_UINT32 table_cfg[DPP_SDT_CFG_LEN] = {0}; + ZXIC_UINT32 temp = 0; + + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, table_id, 0, DPP_DEV_SDT_ID_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_etcam_params); + + rtn = dpp_sdt_mgr_sdt_item_srh(dev_id, table_id, &(table_cfg[0]), &(table_cfg[1])); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "dpp_sdt_mgr_sdt_item_srh"); + + ZXIC_COMM_UINT32_GET_BITS(p_etcam_params->id, table_cfg[0], DPP_SDT_H_ETCAM_ID_BT_POS, DPP_SDT_H_ETCAM_ID_BT_LEN); + ZXIC_COMM_UINT32_GET_BITS(p_etcam_params->key_mode, table_cfg[0], DPP_SDT_H_ETCAM_KEY_MODE_BT_POS, DPP_SDT_H_ETCAM_KEY_MODE_BT_LEN); + ZXIC_COMM_UINT32_GET_BITS(p_etcam_params->table_id, table_cfg[0], DPP_SDT_H_ETCAM_TABLE_ID_BT_POS, DPP_SDT_H_ETCAM_TABLE_ID_BT_LEN); + ZXIC_COMM_UINT32_GET_BITS(p_etcam_params->rsp_mode, table_cfg[0], DPP_SDT_H_ETCAM_NOAS_RSP_MODE_BT_POS, DPP_SDT_H_ETCAM_NOAS_RSP_MODE_BT_LEN); + ZXIC_COMM_UINT32_GET_BITS(p_etcam_params->as_en, table_cfg[0], DPP_SDT_H_ETCAM_AS_EN_BT_POS, DPP_SDT_H_ETCAM_AS_EN_BT_LEN); + ZXIC_COMM_UINT32_GET_BITS(p_etcam_params->as_baddr, table_cfg[0], DPP_SDT_H_ETCAM_AS_ERAM_BADDR_BT_POS, DPP_SDT_H_ETCAM_AS_ERAM_BADDR_BT_LEN); + ZXIC_COMM_UINT32_GET_BITS(temp, table_cfg[1], DPP_SDT_L_ETCAM_AS_ERAM_BADDR_BT_POS, DPP_SDT_L_ETCAM_AS_ERAM_BADDR_BT_LEN); + p_etcam_params->as_baddr = (p_etcam_params->as_baddr << DPP_SDT_L_ETCAM_AS_ERAM_BADDR_BT_LEN) + temp; + ZXIC_COMM_UINT32_GET_BITS(p_etcam_params->as_rsp_mode, table_cfg[1], DPP_SDT_L_ETCAM_AS_RSP_MODE_BT_POS, DPP_SDT_L_ETCAM_AS_RSP_MODE_BT_LEN); + + return DPP_OK; +} + +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/se/Kbuild.include b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/se/Kbuild.include new file mode 100644 index 0000000..3170968 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/se/Kbuild.include @@ -0,0 +1,2 @@ +cur_dir := en_np/sdk/source/dev/module/table/se/ +src_files += $(addprefix $(cur_dir),$(notdir $(wildcard $(dinghai_root)/$(cur_dir)*.c))) diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/se/dpp_acl.c b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/se/dpp_acl.c new file mode 100755 index 0000000..0150762 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/se/dpp_acl.c @@ -0,0 +1,611 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_acl.c +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : 王春雷 +* 完成日期 : 2014/12/17 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ + +#include "zxic_common.h" + +#include "dpp_dev.h" +#include "dpp_acl.h" +#include "dpp_etcam.h" +#include "dpp_se.h" +#include "dpp_se_reg.h" +#include "dpp_reg_api.h" +#include "dpp_reg_info.h" + +#define BLOCK_IDXBASE_BIT_OFF (9) +#define BLOCK_IDXBASE_BIT_MASK (0x7f) +#define ACL_AS_IDX_OFFSET_MAX (32 * 1024) +#define ACL_IMPLICIT_PRI (0) + +#define DPP_ACL_KEYSIZE_GET(key_mode) (2 * DPP_ETCAM_ENTRY_SIZE_GET(key_mode)) +#define DPP_ACL_ENTRY_WRMODE_GET(key_mode, entry_pos) \ + ((((1U << (8U >> (key_mode))) - 1) << ((8U >> (key_mode)) * (entry_pos))) & 0xFF) + +#define DPP_ACL_AS_RSLT_INFO_GET(buff_base, index, size) \ + (((ZXIC_UINT8 *)(buff_base) + (index) * (size))) + +#define MEM_OFF_NOT_NULL(type,member) \ + (ZXIC_COMM_PTR_TO_VAL(&(((type*)4)->member)) - ZXIC_COMM_PTR_TO_VAL(((type*)4))) + +/*根据当前双链表的指针，找到本节点的指针*/ +#define GET_STRUCT_ENTRY_POINT(ptr, type, member) \ + ((type *)(ZXIC_COMM_PTR_TO_VAL(ptr)-MEM_OFF_NOT_NULL(type,member))) + +static DPP_ACL_CFG_EX_T *g_p_acl_ex_cfg = NULL; + +/***********************************************************/ +/** 根据业务表总条目数计数需要的block数 +* @param entry_num +* @param key_mode +* +* @return +* @remark 无 +* @see +* @author 王春雷 @date 2014/12/23 +************************************************************/ +ZXIC_UINT32 dpp_acl_entrynum_to_blocknum(ZXIC_UINT32 entry_num, ZXIC_UINT32 key_mode) +{ + ZXIC_UINT32 value = 0; + + ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW_NO_ASSERT(DPP_ETCAM_RAM_DEPTH, ((ZXIC_UINT32)1 << key_mode)); + value = entry_num % (DPP_ETCAM_RAM_DEPTH * ((ZXIC_UINT32)1 << key_mode)); + + if (value == 0) + { + return (entry_num / (DPP_ETCAM_RAM_DEPTH * ((ZXIC_UINT32)1 << key_mode))); + } + else + { + ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(entry_num / (DPP_ETCAM_RAM_DEPTH * ((ZXIC_UINT32)1 << key_mode)), 1); + return (entry_num / (DPP_ETCAM_RAM_DEPTH * ((ZXIC_UINT32)1 << key_mode)) + 1); + } +} + +/***********************************************************/ +/** 优先级比较函数，用于显示优先级模式比较优先级 +* @param p_new_key +* @param p_old_key +* @param key_len +* +* @return +* @remark 无 +* @see +* @author 王春雷 @date 2014/12/24 +************************************************************/ +ZXIC_SINT32 dpp_acl_entry_pri_cmp(void *p_new_key, void *p_old_key, ZXIC_UINT32 key_len) +{ + if ((*(ZXIC_UINT32 *)p_new_key) > (*(ZXIC_UINT32 *)p_old_key)) + { + return 1; + } + else if ((*(ZXIC_UINT32 *)p_new_key) < (*(ZXIC_UINT32 *)p_old_key)) + { + return -1; + } + + return 0; +} + +/***********************************************************/ +/** 本地缓存acl键值比较，用于rb树回调 +* @param p_new_key +* @param p_old_key +* @param key_len +* +* @return +* @remark 无 +* @see +* @author 王春雷 @date 2014/12/23 +************************************************************/ +ZXIC_SINT32 dpp_acl_key_cmp(void *p_new_key, void *p_old_key, ZXIC_UINT32 key_len) +{ + ZXIC_COMM_CHECK_POINT(p_new_key); + ZXIC_COMM_CHECK_POINT(p_old_key); + /* 相同data+mask，但优先级不同，则为两个不同条目，因此软件需要比较pri+data+mask, handle不参与比较 */ + ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW_NO_ASSERT(key_len, (ZXIC_UINT32)ZXIC_SIZEOF(ZXIC_UINT32)); + return ZXIC_COMM_MEMCMP(&(((DPP_ACL_KEY_INFO_T *)p_new_key)->pri), &(((DPP_ACL_KEY_INFO_T *)p_old_key)->pri), key_len - ZXIC_SIZEOF(ZXIC_UINT32)); +} + +/***********************************************************/ +/** 根据业务条目索引计算写etcam硬件的地址 +* @param p_tbl_cfg +* @param handle +* @param p_block_idx +* @param p_addr +* @param p_wr_mask +* +* @return +* @remark 无 +* @see +* @author 王春雷 @date 2014/12/23 +************************************************************/ +DPP_STATUS dpp_acl_hdw_addr_get(DPP_ACL_TBL_CFG_T *p_tbl_cfg, ZXIC_UINT32 handle, ZXIC_UINT32 *p_block_idx, ZXIC_UINT32 *p_addr, ZXIC_UINT32 *p_wr_mask) +{ + ZXIC_UINT32 block_entry_num = 0; + ZXIC_UINT32 entry_pos = 0; + ZXIC_COMM_CHECK_POINT(p_tbl_cfg); + ZXIC_COMM_CHECK_POINT(p_block_idx); + ZXIC_COMM_CHECK_POINT(p_addr); + ZXIC_COMM_CHECK_POINT(p_wr_mask); + + block_entry_num = DPP_ACL_ENTRY_MAX_GET(p_tbl_cfg->key_mode, 1); + *p_block_idx = p_tbl_cfg->block_array[handle / block_entry_num]; + *p_addr = (handle % block_entry_num) / (1U << p_tbl_cfg->key_mode); + entry_pos = (handle % block_entry_num) % (1U << p_tbl_cfg->key_mode); + ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW_NO_ASSERT(entry_pos, 8); + *p_wr_mask = DPP_ACL_ENTRY_WRMODE_GET(p_tbl_cfg->key_mode, entry_pos); + return DPP_OK; +} + +/***********************************************************/ +/** +* @param p_tbl_cfg +* @param handle +* @param p_block_idx +* @param p_addr +* @param p_wr_mask +* +* @return +* @remark 无 +* @see +* @author XXX @date 2019/08/03 +************************************************************/ +DPP_STATUS dpp_acl_hdw_addr_get_ex(DPP_ACL_TBL_CFG_T *p_tbl_cfg, ZXIC_UINT32 handle, ZXIC_UINT32 *p_block_idx, ZXIC_UINT32 *p_addr, ZXIC_UINT32 *p_wr_mask) +{ + ZXIC_UINT32 block_entry_num = 0; + ZXIC_UINT32 entry_pos = 0; + DPP_STATUS rc = DPP_OK; + + if (0 == (p_tbl_cfg && p_block_idx && p_addr && p_wr_mask)) + { + ZXIC_COMM_TRACE_ERROR("\n ICM %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n", __FILE__, __LINE__, __FUNCTION__); + rc = ZXIC_PAR_CHK_POINT_NULL; + return rc; + } + block_entry_num = DPP_ACL_ENTRY_MAX_GET(p_tbl_cfg->key_mode, 1); + *p_block_idx = p_tbl_cfg->block_array[handle / block_entry_num]; + *p_addr = (handle % block_entry_num) / (1U << p_tbl_cfg->key_mode); + entry_pos = (handle % block_entry_num) % (1U << p_tbl_cfg->key_mode); + ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW_NO_ASSERT(entry_pos, 8); + *p_wr_mask = DPP_ACL_ENTRY_WRMODE_GET(p_tbl_cfg->key_mode, entry_pos); + return rc; +} + +/***********************************************************/ +/** acl重排写硬件回调函数 +* @param old_index +* @param new_index +* @param p_cfg +* +* @return +* @remark 无 +* @see +* @author 王春雷 @date 2014/12/23 +************************************************************/ +DPP_STATUS dpp_acl_entry_swap(ZXIC_UINT32 old_index, ZXIC_UINT32 new_index, ZXIC_VOID *p_cfg) +{ + DPP_STATUS rc = 0; + ZXIC_UINT32 block_idx = 0; + ZXIC_UINT32 ram_addr = 0; + ZXIC_UINT32 wr_mask = 0; + ZXIC_UINT8 *p_old_rslt_temp = NULL; + ZXIC_UINT8 *p_new_rslt_temp = NULL; + ZXIC_UINT8 temp_data[DPP_ETCAM_WIDTH_MAX / 8] = {0}; + ZXIC_UINT8 temp_mask[DPP_ETCAM_WIDTH_MAX / 8] = {0}; + DPP_ACL_CFG_T *p_acl_cfg = NULL; + DPP_ACL_TBL_CFG_T *p_tbl_cfg = NULL; + DPP_ACL_KEY_INFO_T *p_acl_key = NULL; + DPP_ETCAM_ENTRY_T etcam_entry = {0}; + + ZXIC_COMM_CHECK_POINT(p_cfg); + + p_tbl_cfg = STRUCT_ENTRY_POINT(p_cfg, DPP_ACL_TBL_CFG_T, index_mng); + ZXIC_COMM_CHECK_INDEX(p_tbl_cfg->table_id, 0, DPP_ACL_TBL_ID_NUM - 1); /* modify coverity yinxh 2021.03.10*/ + p_acl_cfg = GET_STRUCT_ENTRY_POINT(p_tbl_cfg, DPP_ACL_CFG_T, acl_tbls[p_tbl_cfg->table_id]); + + ZXIC_COMM_CHECK_INDEX_UPPER(old_index, p_tbl_cfg->entry_num); /* modify coverity yinxh 2021.03.10*/ + p_acl_key = p_tbl_cfg->acl_key_buff[old_index]; + + etcam_entry.p_data = temp_data; + etcam_entry.p_mask = temp_mask; + etcam_entry.mode = p_tbl_cfg->key_mode; + ZXIC_COMM_CHECK_DEV_INDEX(p_acl_cfg->dev_id, p_tbl_cfg->key_mode, DPP_ACL_KEY_640b, DPP_ACL_KEY_INVALID - 1); /* modify coverity yinxh 2021.03.10*/ + ZXIC_COMM_MEMCPY(etcam_entry.p_data, p_acl_key->key, DPP_ETCAM_ENTRY_SIZE_GET(p_tbl_cfg->key_mode)); + ZXIC_COMM_MEMCPY(etcam_entry.p_mask, p_acl_key->key + DPP_ETCAM_ENTRY_SIZE_GET(p_tbl_cfg->key_mode), DPP_ETCAM_ENTRY_SIZE_GET(p_tbl_cfg->key_mode)); + + /* update new as result */ + if (p_tbl_cfg->as_enable) + { + /* eTcam result table as to eRam. */ + ZXIC_COMM_CHECK_DEV_INDEX(p_acl_cfg->dev_id, p_tbl_cfg->as_mode, DPP_ACL_AS_MODE_16b, DPP_ACL_AS_MODE_INVALID - 1); + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(p_acl_cfg->dev_id, old_index, (2U << (p_tbl_cfg->as_mode))); + p_old_rslt_temp = DPP_ACL_AS_RSLT_INFO_GET(p_tbl_cfg->as_rslt_buff, old_index, DPP_ACL_AS_RSLT_SIZE_GET_EX(p_tbl_cfg->as_mode)); + rc = p_acl_cfg->p_as_rslt_write_fun(p_acl_cfg->dev_id, + p_tbl_cfg->as_eRam_base + p_tbl_cfg->as_idx_base, + new_index, + p_tbl_cfg->as_mode, + p_old_rslt_temp); + ZXIC_COMM_CHECK_RC(rc, "acl_as_rslt_write_fun"); + + /* update result buffer */ + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(p_acl_cfg->dev_id, new_index, 2U << p_tbl_cfg->as_mode); + p_new_rslt_temp = DPP_ACL_AS_RSLT_INFO_GET(p_tbl_cfg->as_rslt_buff, new_index, DPP_ACL_AS_RSLT_SIZE_GET_EX(p_tbl_cfg->as_mode)); + ZXIC_COMM_MEMCPY(p_new_rslt_temp, p_old_rslt_temp, (ZXIC_UINT32)DPP_ACL_AS_RSLT_SIZE_GET_EX(p_tbl_cfg->as_mode)); + } + else if (p_tbl_cfg->is_as_ddr) + { + /* eTcam result table as to DDR. */ + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(p_acl_cfg->dev_id, old_index, 2U << p_tbl_cfg->as_mode); + p_old_rslt_temp = DPP_ACL_AS_RSLT_INFO_GET(p_tbl_cfg->as_rslt_buff, old_index, DPP_ACL_AS_RSLT_SIZE_GET_EX(p_tbl_cfg->as_mode)); + + rc = p_tbl_cfg->p_as_ddr_wr_fun(p_acl_cfg->dev_id, + p_tbl_cfg->tbl_type, + p_tbl_cfg->table_id, + p_tbl_cfg->dir_tbl_share_type, + p_tbl_cfg->ddr_baddr, + p_tbl_cfg->ddr_ecc_en, + p_tbl_cfg->idx_offset, + p_tbl_cfg->as_mode, + p_old_rslt_temp); + ZXIC_COMM_CHECK_RC(rc, "acl_as_ddr_rslt_writ_fun"); + + /* update result buffer */ + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(p_acl_cfg->dev_id, new_index, 2U << p_tbl_cfg->as_mode); + p_new_rslt_temp = DPP_ACL_AS_RSLT_INFO_GET(p_tbl_cfg->as_rslt_buff, new_index, DPP_ACL_AS_RSLT_SIZE_GET_EX(p_tbl_cfg->as_mode)); + ZXIC_COMM_MEMCPY(p_new_rslt_temp, p_old_rslt_temp, (ZXIC_UINT32)DPP_ACL_AS_RSLT_SIZE_GET_EX(p_tbl_cfg->as_mode)); + } + + /* add new entry */ + rc = dpp_acl_hdw_addr_get_ex(p_tbl_cfg, new_index, &block_idx, &ram_addr, &wr_mask); + ZXIC_COMM_CHECK_RC(rc, "dpp_acl_hdw_addr_get_ex"); + +#ifdef DPP_FLOW_HW_INIT + rc = dpp_etcam_entry_add(p_acl_cfg->dev, ram_addr, block_idx, wr_mask, DPP_ETCAM_OPR_DM, &etcam_entry); + ZXIC_COMM_CHECK_RC(rc, "dpp_etcam_entry_add"); +#endif + + /* delete old entry */ + rc = dpp_acl_hdw_addr_get_ex(p_tbl_cfg, old_index, &block_idx, &ram_addr, &wr_mask); + ZXIC_COMM_CHECK_RC(rc, "dpp_acl_hdw_addr_get_ex"); + +#ifdef DPP_FLOW_HW_INIT + rc = dpp_etcam_entry_del(p_acl_cfg->dev, ram_addr, block_idx, wr_mask); + ZXIC_COMM_CHECK_RC(rc, "dpp_etcam_entry_del"); +#endif + + p_acl_key->handle = new_index; + p_tbl_cfg->acl_key_buff[new_index] = p_acl_key; + + return DPP_OK; +} + +/***********************************************************/ +/** 获取ACL全局配置 +* @param p_acl_cfg ACL公共管理数据结构指针 +* +* @return DPP_OK-成功，DPP_ERR-失败 +************************************************************/ +DPP_STATUS dpp_acl_cfg_get(DPP_ACL_CFG_EX_T **p_acl_cfg) +{ + DPP_STATUS rc = 0; + + if(NULL == g_p_acl_ex_cfg) + { + ZXIC_COMM_TRACE_ERROR("dpp_acl_cfg_get fail, etcam_is not init!\n"); + ZXIC_COMM_ASSERT(0); + return DPP_ACL_RC_ETCAMID_NOT_INIT; + } + + *p_acl_cfg = g_p_acl_ex_cfg; + + return rc; +} + +#if ZXIC_REAL("init_ex MUL_PRI") + +/***********************************************************/ +/** +* @param p_acl_cfg +* @param p_client +* @param flags +* @param p_as_wrt_fun +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author wcl @date 2015/12/29 +************************************************************/ +DPP_STATUS dpp_acl_cfg_init_ex(DPP_DEV_T *dev, + DPP_ACL_CFG_EX_T *p_acl_cfg, + ZXIC_VOID *p_client, + ZXIC_UINT32 flags, + ACL_AS_RSLT_WRT_FUNCTION p_as_wrt_fun) +{ + DPP_STATUS rc = 0; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_POINT(p_acl_cfg); + + ZXIC_COMM_MEMSET(p_acl_cfg, 0, ZXIC_SIZEOF(DPP_ACL_CFG_EX_T)); + + g_p_acl_ex_cfg = p_acl_cfg; + + p_acl_cfg->p_client = p_client; + // p_acl_cfg->dev_id = (ZXIC_UINT32)(ZXIC_COMM_PTR_TO_VAL(p_acl_cfg->p_client) & 0xFFFFFFFF); + p_acl_cfg->dev_id = DEV_ID(dev); + p_acl_cfg->dev = dev; + p_acl_cfg->flags = flags; + + if (flags & DPP_ACL_FLAG_ETCAM0_EN) + { + p_acl_cfg->acl_etcamids.is_valid = 1; + + /* if (flags & DPP_ACL_FLAG_ETCAM0_AS)*/ + /* {*/ + /* p_acl_cfg->acl_etcamids[0].as_enable = 1;*/ + p_acl_cfg->acl_etcamids.as_eRam_base = 0; + /* }*/ + + rc = zxic_comm_double_link_init(DPP_ACL_TBL_ID_NUM, &(p_acl_cfg->acl_etcamids.tbl_list)); + ZXIC_COMM_CHECK_RC(rc, "zxic_comm_double_link_init"); + } + + if (p_as_wrt_fun == NULL) + { + // p_acl_cfg->p_as_rslt_write_fun = dpp_acl_as_rslt_write; + // p_acl_cfg->p_as_rslt_read_fun = dpp_acl_as_rslt_read; + } + else + { + p_acl_cfg->p_as_rslt_write_fun = p_as_wrt_fun; + } + + return DPP_OK; +} + +/***********************************************************/ +/** acl业务表初始化，注意分配给一个table的多个block_idx + 必须按从小到大的顺序给定。支持多个优先级模式，暂不对外开放。 +* @param p_acl_cfg +* @param table_id +* @param as_enable +* @param entry_num +* @param pri_mode +* @param key_mode +* @param as_mode +* @param block_num +* @param p_block_idx +* +* @return +* @remark 无 +* @see +* @author 王春雷 @date 2014/12/23 +************************************************************/ +DPP_STATUS dpp_acl_tbl_init_ex(DPP_ACL_CFG_EX_T *p_acl_cfg, + ZXIC_UINT32 table_id, + ZXIC_UINT32 as_enable, + ZXIC_UINT32 entry_num, + DPP_ACL_PRI_MODE_E pri_mode, + ZXIC_UINT32 key_mode, + DPP_ACL_AS_MODE_E as_mode, + ZXIC_UINT32 as_baddr, + ZXIC_UINT32 block_num, + ZXIC_UINT32 *p_block_idx) +{ + DPP_STATUS rc = 0; + ZXIC_UINT32 i = 0; + ZXIC_UINT32 acl_key_buff_size = 0; + /* ZXIC_UINT32 as_idx_base = 0;*/ + + ZXIC_COMM_CHECK_POINT(p_acl_cfg); + ZXIC_COMM_CHECK_INDEX(table_id, DPP_ACL_TBL_ID_MIN, DPP_ACL_TBL_ID_MAX); + ZXIC_COMM_CHECK_INDEX(as_enable, 0, 1); + ZXIC_COMM_CHECK_INDEX(pri_mode, DPP_ACL_PRI_EXPLICIT, DPP_ACL_PRI_SPECIFY); + ZXIC_COMM_CHECK_INDEX(key_mode, DPP_ACL_KEY_640b, DPP_ACL_KEY_80b); + ZXIC_COMM_CHECK_INDEX(as_mode, DPP_ACL_AS_MODE_16b, DPP_ACL_AS_MODE_128b); + ZXIC_COMM_CHECK_INDEX(block_num, 0, DPP_ETCAM_BLOCK_NUM); + ZXIC_COMM_CHECK_POINT(p_block_idx); + + g_p_acl_ex_cfg = p_acl_cfg; + + if (p_acl_cfg->acl_tbls[table_id].is_used) + { + ZXIC_COMM_TRACE_ERROR("table_id[ %d ] is already used!\n", table_id); + ZXIC_COMM_ASSERT(0); + return DPP_ACL_RC_INVALID_TBLID; + } + + if (!p_acl_cfg->acl_etcamids.is_valid) + { + ZXIC_COMM_TRACE_ERROR("etcam is not init!\n"); + ZXIC_COMM_ASSERT(0); + return DPP_ACL_RC_ETCAMID_NOT_INIT; + } + + if (dpp_acl_entrynum_to_blocknum(entry_num, key_mode) > block_num) + { + ZXIC_COMM_TRACE_ERROR("key_mode[ %d ], the etcam block_num[ %d ] is not enough for entry_num[ 0x%x ].\n", + key_mode, block_num, entry_num); + ZXIC_COMM_ASSERT(0); + return DPP_ACL_RC_INVALID_BLOCKNUM; + } + else if (dpp_acl_entrynum_to_blocknum(entry_num, key_mode) < block_num) + { + ZXIC_COMM_TRACE_DEBUG("key_mode[ %d ], the etcam block_num[ %d ] is more than entry_num[ 0x%x ], better to reduce block_num in order to match with entry_num.\n", + key_mode, block_num, entry_num); + } + else + { + ZXIC_COMM_TRACE_DEBUG("key_mode[ %d ], the etcam block_num[ %d ] is match with entry_num[ 0x%x ].\n", + key_mode, block_num, entry_num); + } + + p_acl_cfg->acl_tbls[table_id].as_enable = as_enable; + + /* + if ((!p_acl_cfg->acl_etcamids[etcam_id].as_enable && as_enable) || + (p_acl_cfg->acl_etcamids[etcam_id].as_enable && !as_enable)) + { + ZXIC_COMM_TRACE_ERROR( "tbl's as_enable is not according to ETCAM_id's.\n"); + ZXIC_COMM_ASSERT(0); + return DPP_ACL_RC_INVALID_PARA; + } + */ + + if (as_enable) + { + p_acl_cfg->acl_tbls[table_id].as_idx_base = as_baddr; + p_acl_cfg->acl_tbls[table_id].as_rslt_buff = ZXIC_COMM_MALLOC(entry_num * DPP_ACL_AS_RSLT_SIZE_GET_EX(as_mode)); + ZXIC_COMM_CHECK_POINT(p_acl_cfg->acl_tbls[table_id].as_rslt_buff); + } + + if ((pri_mode == DPP_ACL_PRI_EXPLICIT) || (pri_mode == DPP_ACL_PRI_IMPLICIT)) + { + rc = (DPP_STATUS)zxic_comm_indexfill_init(&(p_acl_cfg->acl_tbls[table_id].index_mng), + entry_num, + dpp_acl_entry_pri_cmp, + dpp_acl_entry_swap, + ZXIC_SIZEOF(ZXIC_UINT32)); + ZXIC_COMM_CHECK_RC(rc, "zxic_comm_indexfill_init"); + + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(p_acl_cfg->dev_id, entry_num, (ZXIC_UINT32)ZXIC_SIZEOF(DPP_ACL_KEY_INFO_T *)); + acl_key_buff_size = (entry_num * ZXIC_SIZEOF(DPP_ACL_KEY_INFO_T *)) & 0xffffffff; + p_acl_cfg->acl_tbls[table_id].acl_key_buff = (DPP_ACL_KEY_INFO_T **)ZXIC_COMM_MALLOC(acl_key_buff_size); + ZXIC_COMM_CHECK_POINT(p_acl_cfg->acl_tbls[table_id].acl_key_buff); + } + + rc = (DPP_STATUS)zxic_comm_rb_init(&(p_acl_cfg->acl_tbls[table_id].acl_rb), 0, ZXIC_SIZEOF(DPP_ACL_KEY_INFO_T) + DPP_ACL_KEYSIZE_GET(key_mode), dpp_acl_key_cmp); + ZXIC_COMM_CHECK_RC(rc, "zxic_comm_rb_init"); + + p_acl_cfg->acl_tbls[table_id].table_id = table_id; + p_acl_cfg->acl_tbls[table_id].pri_mode = pri_mode; + p_acl_cfg->acl_tbls[table_id].key_mode = key_mode; + p_acl_cfg->acl_tbls[table_id].entry_num = entry_num; + p_acl_cfg->acl_tbls[table_id].as_mode = as_mode; + p_acl_cfg->acl_tbls[table_id].is_used = 1; + + // ZXIC_COMM_TRACE_ERROR("p_acl_cfg->acl_tbls[%u].table_id [%d]\n", table_id, p_acl_cfg->acl_tbls[table_id].table_id); + // ZXIC_COMM_TRACE_ERROR("p_acl_cfg->acl_tbls[%u].pri_mode [%d]\n", table_id, p_acl_cfg->acl_tbls[table_id].pri_mode); + // ZXIC_COMM_TRACE_ERROR("p_acl_cfg->acl_tbls[%u].key_mode [%d]\n", table_id, p_acl_cfg->acl_tbls[table_id].key_mode); + // ZXIC_COMM_TRACE_ERROR("p_acl_cfg->acl_tbls[%u].entry_num [%d]\n", table_id, p_acl_cfg->acl_tbls[table_id].entry_num); + // ZXIC_COMM_TRACE_ERROR("p_acl_cfg->acl_tbls[%u].as_mode [%d]\n", table_id, p_acl_cfg->acl_tbls[table_id].as_mode); + + INIT_D_NODE(&(p_acl_cfg->acl_tbls[table_id].entry_dn), &(p_acl_cfg->acl_tbls[table_id])); + rc = (DPP_STATUS)zxic_comm_double_link_insert_last(&(p_acl_cfg->acl_tbls[table_id].entry_dn), &(p_acl_cfg->acl_etcamids.tbl_list)); + ZXIC_COMM_CHECK_RC(rc, "zxic_comm_double_link_insert_last"); + + p_acl_cfg->acl_tbls[table_id].block_num = block_num; + p_acl_cfg->acl_tbls[table_id].block_array = ZXIC_COMM_MALLOC(block_num * ZXIC_SIZEOF(ZXIC_UINT32)); + ZXIC_COMM_CHECK_POINT(p_acl_cfg->acl_tbls[table_id].block_array); + + for (i = 0; i < block_num; i++) + { + if (p_acl_cfg->acl_blocks[p_block_idx[i]].is_used) + { + ZXIC_COMM_TRACE_ERROR("the block[ %d ] is already used by table[ %d ]!\n", p_block_idx[i], p_acl_cfg->acl_blocks[p_block_idx[i]].tbl_id); + ZXIC_COMM_ASSERT(0); + return DPP_ACL_RC_INVALID_BLOCKID; + } + + p_acl_cfg->acl_tbls[table_id].block_array[i] = p_block_idx[i]; + p_acl_cfg->acl_blocks[p_block_idx[i]].is_used = 1; + p_acl_cfg->acl_blocks[p_block_idx[i]].tbl_id = table_id; + p_acl_cfg->acl_blocks[p_block_idx[i]].idx_base = ((DPP_ACL_ENTRY_MAX_GET(key_mode, i)) >> BLOCK_IDXBASE_BIT_OFF) & BLOCK_IDXBASE_BIT_MASK; + +#ifdef DPP_FLOW_HW_INIT + /* cfg block table_id */ + rc = dpp_etcam_block_tbl_id_set(p_acl_cfg->dev, p_block_idx[i], table_id); + ZXIC_COMM_CHECK_RC(rc, "dpp_etcam_block_tbl_id_set"); + + /* cfg block base_addr */ + rc = dpp_etcam_block_baddr_set(p_acl_cfg->dev, p_block_idx[i], p_acl_cfg->acl_blocks[p_block_idx[i]].idx_base); + ZXIC_COMM_CHECK_RC(rc, "dpp_etcam_block_baddr_set"); +#endif + + } + + return DPP_OK; +} + +DPP_STATUS dpp_acl_res_destroy(ZXIC_UINT32 dev_id) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 table_id = 0; + ZXIC_UINT32 as_enable = 0; + ZXIC_UINT32 pri_mode = 0; + DPP_ACL_CFG_EX_T *p_acl_cfg = NULL; + DPP_ACL_TBL_CFG_T *p_tbl_cfg = NULL; + + ZXIC_COMM_CHECK_INDEX_NO_ASSERT(dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + + rc = dpp_acl_cfg_get(&p_acl_cfg);//获取ACL表资源配置 + ZXIC_COMM_CHECK_POINT(p_acl_cfg); + ZXIC_COMM_CHECK_RC(rc, "dpp_acl_cfg_get"); + + if(!p_acl_cfg->acl_etcamids.is_valid) + { + ZXIC_COMM_TRACE_ERROR("etcam is not init!\n"); + return DPP_ACL_RC_ETCAMID_NOT_INIT; + } + + for(table_id=DPP_ACL_TBL_ID_MIN;table_id<=DPP_ACL_TBL_ID_MAX;table_id++) + { + p_tbl_cfg = p_acl_cfg->acl_tbls + table_id; + if (!p_tbl_cfg->is_used) + { + ZXIC_COMM_TRACE_DEBUG("table_id[ %d ] is not used!\n", table_id); + continue; + } + + rc = (DPP_STATUS)zxic_comm_rb_destroy(&(p_tbl_cfg->acl_rb)); + ZXIC_COMM_CHECK_RC(rc, "zxic_comm_rb_destroy"); + + rc = zxic_comm_indexfill_destroy(&(p_tbl_cfg->index_mng)); + ZXIC_COMM_CHECK_RC(rc, "zxic_comm_indexfill_destroy"); + + as_enable = p_tbl_cfg->as_enable; + if(as_enable) + { + if(p_tbl_cfg->as_rslt_buff) + { + ZXIC_COMM_FREE(p_tbl_cfg->as_rslt_buff); + p_tbl_cfg->as_rslt_buff = NULL; + } + } + + pri_mode = p_tbl_cfg->pri_mode; + if ((pri_mode == DPP_ACL_PRI_EXPLICIT) || (pri_mode == DPP_ACL_PRI_IMPLICIT)) + { + if(p_tbl_cfg->acl_key_buff) + { + ZXIC_COMM_FREE(p_tbl_cfg->acl_key_buff); + p_tbl_cfg->acl_key_buff = NULL; + } + } + + if(p_tbl_cfg->block_array) + { + ZXIC_COMM_FREE(p_tbl_cfg->block_array); + p_tbl_cfg->block_array = NULL; + } + } + + return DPP_OK; +} + +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/se/dpp_dtb_table.c b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/se/dpp_dtb_table.c new file mode 100644 index 0000000..36f36e2 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/se/dpp_dtb_table.c @@ -0,0 +1,7465 @@ +#include "zxic_private_top.h" +#include "zxic_common.h" +#include "dpp_dtb_table_api.h" +#include "dpp_dtb_table.h" +#include "dpp_se_api.h" +#include "dpp_se_cfg.h" +#include "dpp_hash_crc.h" +#include "dpp_hash.h" +#include "dpp_acl.h" +#include "dpp_etcam.h" +#include "dpp_se.h" +#include "dpp_dtb.h" +#include "dpp_dtb_cfg.h" +#include "dpp_dev.h" +#include "dpp_sdt.h" +#include "dpp_dtb.h" +#include "dpp_apt_se.h" +#include "dpp_hash.h" + +extern ZXIC_UINT32 g_lpm_hw_dat_buf[LPM_HW_DAT_BUFF_SIZE_MAX]; +extern ZXIC_UINT32 g_lpm_hw_dat_offset; + +DPP_DTB_MIXED_TABLE_T *p_dtb_mixed_table_mgr = NULL; + +ZXIC_UINT32 g_dpp_dtb_int_enable = DISABLE;//默认中断不使能 +ZXIC_UINT32 g_dtb_srh_mode = 1; //默认硬件模式 0：软件查找 1：硬件查找 + +static ZXIC_UINT32 g_dtb_cmd_endian = 0; //0:小端 1：大端 + + +DPP_DTB_FIELD_T g_dtb_ddr_table_cmd_info[] = +{ + {"valid", 127, 1}, + {"type_mode", 126, 3}, + {"rw_len", 123, 2}, + {"v46_flag", 121, 1}, + {"lpm_wr_vld", 120, 1}, + {"baddr", 119, 20}, + {"ecc_en", 99, 1}, + {"rw_addr", 29, 30}, +}; + +DPP_DTB_FIELD_T g_dtb_eram_table_cmd_1_info[] = +{ + {"valid", 127, 1}, + {"type_mode", 126, 3}, + {"data_mode",123, 2}, + {"cpu_wr", 121, 1}, + {"cpu_rd", 120, 1}, + {"cpu_rd_mode", 119, 1}, + {"addr", 113, 26}, + {"data_h",0,1}, +}; + +DPP_DTB_FIELD_T g_dtb_eram_table_cmd_64_info[] = +{ + {"valid", 127, 1}, + {"type_mode", 126, 3}, + {"data_mode",123, 2}, + {"cpu_wr", 121, 1}, + {"cpu_rd", 120, 1}, + {"cpu_rd_mode", 119, 1}, + {"addr", 113, 26}, + {"data_h",63,32}, + {"data_l",31,32}, +}; + +DPP_DTB_FIELD_T g_dtb_eram_table_cmd_128_info[] = +{ + {"valid", 127, 1}, + {"type_mode", 126, 3}, + {"data_mode",123, 2}, + {"cpu_wr", 121, 1}, + {"cpu_rd", 120, 1}, + {"cpu_rd_mode", 119, 1}, + {"addr", 113, 26}, +}; + +DPP_DTB_FIELD_T g_dtb_zcam_table_cmd_info[] = +{ + {"valid", 127, 1}, + {"type_mode", 126, 3}, + {"ram_reg_flag",123, 1}, + {"zgroup_id", 122, 2}, + {"zblock_id", 120, 3}, + {"zcell_id", 117, 2}, + {"mask", 115, 4}, + {"sram_addr", 111, 9}, +}; + +DPP_DTB_FIELD_T g_dtb_etcam_table_cmd_info[] = +{ + {"valid", 127, 1}, + {"type_mode", 126, 3}, + {"block_sel",123, 3}, + {"init_en", 120, 1}, + {"row_or_col_msk", 119, 1}, + {"vben", 118, 1}, + {"reg_tcam_flag", 117, 1}, + {"uload", 116, 8}, + {"rd_wr",108, 1}, + {"wr_mode", 107, 8}, + {"data_or_mask", 99, 1}, + {"addr", 98, 9}, + {"vbit", 89, 8}, +}; + +DPP_DTB_FIELD_T g_dtb_mc_hash_table_cmd_info[] = +{ + {"valid", 127, 1}, + {"type_mode", 126, 3}, + {"std_h", 63, 32}, + {"std_l", 31, 32}, +}; + + +DPP_DTB_TABLE_T g_dpp_dtb_table_info[] = +{ + { + "ddr", + DTB_TABLE_DDR, + 8, + g_dtb_ddr_table_cmd_info, + }, + { + "eram 1 bit", + DTB_TABLE_ERAM_1, + 8, + g_dtb_eram_table_cmd_1_info, + }, + { + "eram 64 bit", + DTB_TABLE_ERAM_64, + 9, + g_dtb_eram_table_cmd_64_info, + }, + { + "eram 128 bit", + DTB_TABLE_ERAM_128, + 7, + g_dtb_eram_table_cmd_128_info, + }, + { + "zcam", + DTB_TABLE_ZCAM, + 8, + g_dtb_zcam_table_cmd_info, + }, + { + "etcam", + DTB_TABLE_ETCAM, + 13, + g_dtb_etcam_table_cmd_info, + }, + { + "mc_hash", + DTB_TABLE_MC_HASH, + 4, + g_dtb_mc_hash_table_cmd_info + }, +}; + + +DPP_DTB_FIELD_T g_dtb_eram_dump_cmd_info[] = +{ + {"valid", 127, 1}, + {"up_type", 126, 2}, + {"base_addr", 106, 19}, + {"tb_depth", 83, 20}, + {"tb_dst_addr_h", 63, 32}, + {"tb_dst_addr_l", 31, 32}, +}; + +DPP_DTB_FIELD_T g_dtb_ddr_dump_cmd_info[] = +{ + {"valid", 127, 1}, + {"up_type", 126, 2}, + {"base_addr", 117, 30}, + {"tb_depth", 83, 20}, + {"tb_dst_addr_h", 63, 32}, + {"tb_dst_addr_l", 31, 32}, + +}; + +DPP_DTB_FIELD_T g_dtb_zcam_dump_cmd_info[] = +{ + {"valid", 127, 1}, + {"up_type", 126, 2}, + {"zgroup_id", 124, 2}, + {"zblock_id", 122, 3}, + {"ram_reg_flag", 119, 1}, + {"z_reg_cell_id", 118, 2}, + {"sram_addr", 116, 9}, + {"tb_depth", 97, 10}, + {"tb_width", 65, 2}, + {"tb_dst_addr_h", 63, 32}, + {"tb_dst_addr_l", 31, 32}, + +}; + +DPP_DTB_FIELD_T g_dtb_etcam_dump_cmd_info[] = +{ + {"valid", 127, 1}, + {"up_type", 126, 2}, + {"block_sel", 124, 3}, + {"addr", 121, 9}, + {"rd_mode", 112, 8}, + {"data_or_mask", 104, 1}, + {"tb_depth", 91, 10}, + {"tb_width", 81, 2}, + {"tb_dst_addr_h", 63, 32}, + {"tb_dst_addr_l", 31, 32}, + +}; + + +DPP_DTB_TABLE_T g_dpp_dtb_dump_info[] = +{ + { + "eram", + DTB_DUMP_ERAM, + 6, + g_dtb_eram_dump_cmd_info, + }, + { + "ddr", + DTB_DUMP_DDR, + 6, + g_dtb_ddr_dump_cmd_info, + }, + { + "zcam", + DTB_DUMP_ZCAM, + 11, + g_dtb_zcam_dump_cmd_info, + }, + { + "etcam", + DTB_DUMP_ETCAM, + 10, + g_dtb_etcam_dump_cmd_info, + }, +}; + +/** dtb 中断配置 +* @param int_enable 中断使能 +* +* @return +* @remark 无 +* @see +* @author cbb @date 2022/08/30 +************************************************************/ +DPP_STATUS dpp_dtb_interrupt_status_set(ZXIC_UINT32 int_enable) +{ + g_dpp_dtb_int_enable = int_enable; + + return DPP_OK; +} + +/** dtb 中断获取 +* +* @return +* @remark 无 +* @see +* @author cbb @date 2022/08/30 +************************************************************/ +ZXIC_UINT32 dpp_dtb_interrupt_status_get(ZXIC_VOID) +{ + return g_dpp_dtb_int_enable; +} + +/** dtb cmd 大小端设置 +* @param int_enable 中断使能 +* +* @return +* @remark 无 +* @see +* @author cbb @date 2022/08/30 +************************************************************/ +DPP_STATUS dpp_dtb_cmd_endian_status_set(ZXIC_UINT32 endian) +{ + g_dtb_cmd_endian = endian; + + return DPP_OK; +} + +/** dtb cmd 大小端获取 +* +* @return +* @remark 无 +* @see +* @author cbb @date 2022/08/30 +************************************************************/ +DPP_STATUS dpp_dtb_cmd_endian_status_get(ZXIC_VOID) +{ + return g_dtb_cmd_endian; +} + +/***********************************************************/ +/** 获取 DTB 表属性信息 +* @param table_type DTB表类型 +* +* @return +* @remark 无 +* @see +* @author cbb @date 2022/09/02 +************************************************************/ +DPP_DTB_TABLE_T *dpp_table_info_get(ZXIC_UINT32 table_type) +{ + ZXIC_COMM_CHECK_INDEX_RETURN_NULL(table_type, 0, DTB_TABLE_ENUM_MAX - 1); + + return (&g_dpp_dtb_table_info[table_type]); +} + +/***********************************************************/ +/** 获取 DTB dump表属性信息 +* @param up_type DTB表类型 +* +* @return +* @remark 无 +* @see +* @author cbb @date 2022/09/02 +************************************************************/ +DPP_DTB_TABLE_T *dpp_dump_info_get(ZXIC_UINT32 up_type) +{ + ZXIC_COMM_CHECK_INDEX_RETURN_NULL(up_type, 0, DTB_DUMP_ENUM_MAX - 1); + + return (&g_dpp_dtb_dump_info[up_type]); +} + +/*组装128bit数据格式接口*/ +/** dtb写下表128bit格式数据 +* @param dev_id 设备号 +* @param table_type dtb表类型 +* @param p_cmd_data 表格式命令数据 +* @param p_cmd_buff 表格式命令数据缓存 +* @return +* @remark 无 +* @see +* @author cbb @date 2022/08/30 +************************************************************/ +DPP_STATUS dpp_dtb_write_table_cmd(ZXIC_UINT32 dev_id, + DPP_DTB_TABLE_INFO_E table_type, + ZXIC_VOID *p_cmd_data, + ZXIC_VOID *p_cmd_buff + ) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 field_cnt = 0; + + DPP_DTB_TABLE_T *p_table_info; + DPP_DTB_FIELD_T *p_field_info = NULL; + ZXIC_UINT32 temp_data = 0; + + ZXIC_COMM_CHECK_INDEX_UPPER(dev_id, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, table_type, 0, DTB_TABLE_ENUM_MAX - 1); + ZXIC_COMM_CHECK_POINT(p_cmd_data); + ZXIC_COMM_CHECK_POINT(p_cmd_buff); + + p_table_info = dpp_table_info_get(table_type); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_table_info); + p_field_info = p_table_info->p_fields; + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_field_info); + + /* 提取各字段数据，按各字段实际bit位宽进行拼装 */ + for (field_cnt = 0; field_cnt < p_table_info->field_num; field_cnt++) + { + temp_data = *((ZXIC_UINT32 *)p_cmd_data + field_cnt) & ZXIC_COMM_GET_BIT_MASK(ZXIC_UINT32, p_field_info[field_cnt].len); + + rc = zxic_comm_write_bits_ex((ZXIC_UINT8 *)p_cmd_buff, + DTB_TABLE_CMD_SIZE_BIT, + temp_data, + p_field_info[field_cnt].lsb_pos, + p_field_info[field_cnt].len); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "zxic_comm_write_bits"); + } + + return DPP_OK; +} + +/** dtb写dump表128bit格式数据 +* @param dev_id 设备号 +* @param dump_type dtb dump表类型 +* @param p_cmd_data dump表格式命令数据 +* @param p_cmd_buff dump表格式命令数据缓存 +* @return +* @remark 无 +* @see +* @author cbb @date 2022/08/30 +************************************************************/ +DPP_STATUS dpp_dtb_write_dump_cmd(ZXIC_UINT32 dev_id, + DPP_DTB_DUMP_INFO_E dump_type, + ZXIC_VOID *p_cmd_data, + ZXIC_VOID *p_cmd_buff) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 field_cnt = 0; + + DPP_DTB_TABLE_T *p_table_info; + DPP_DTB_FIELD_T *p_field_info = NULL; + ZXIC_UINT32 temp_data = 0; + + ZXIC_COMM_CHECK_INDEX_UPPER(dev_id, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dump_type, 0, DTB_DUMP_ENUM_MAX - 1); + ZXIC_COMM_CHECK_POINT(p_cmd_data); + ZXIC_COMM_CHECK_POINT(p_cmd_buff); + + p_table_info = dpp_dump_info_get(dump_type); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_table_info); + p_field_info = p_table_info->p_fields; + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_field_info); + + /* 提取各字段数据，按各字段实际bit位宽进行拼装 */ + for (field_cnt = 0; field_cnt < p_table_info->field_num; field_cnt++) + { + + temp_data = *((ZXIC_UINT32 *)p_cmd_data + field_cnt) & ZXIC_COMM_GET_BIT_MASK(ZXIC_UINT32, p_field_info[field_cnt].len); + + rc = zxic_comm_write_bits_ex((ZXIC_UINT8 *)p_cmd_buff, + DTB_TABLE_CMD_SIZE_BIT, + temp_data, + p_field_info[field_cnt].lsb_pos, + p_field_info[field_cnt].len); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "zxic_comm_write_bits"); + } + + return DPP_OK; +} + + +/** 将下表格式+数据写入缓存中 + * entry，data_in_cmd_flag，如果为1，直接拷贝cmd，不拷贝data +* @param p_data_buff 存放数据的buff头指针 +* @param addr_offset 当前数据要写入的位置（相对于buff头的偏移） +* @param entry 要写入缓存的数据指针 +* +* @return +* @remark 无 +* @see +* @author cbb @date 2022/08/30/ +************************************************************/ +DPP_STATUS dpp_dtb_data_write(ZXIC_UINT8 * p_data_buff, + ZXIC_UINT32 addr_offset, + DPP_DTB_ENTRY_T *entry) +{ + ZXIC_UINT8* p_cmd = p_data_buff + addr_offset; + ZXIC_UINT32 cmd_size = DTB_TABLE_CMD_SIZE_BIT / 8; + + ZXIC_UINT8* p_data = p_cmd + cmd_size; + ZXIC_UINT32 data_size = entry->data_size; + + ZXIC_UINT8 * cmd = (ZXIC_UINT8 *)entry->cmd; + ZXIC_UINT8 * data = (ZXIC_UINT8 *)entry->data; + + ZXIC_COMM_CHECK_POINT(p_data_buff); + ZXIC_COMM_CHECK_POINT(entry); + + /*写入命令数据*/ + ZXIC_COMM_MEMCPY_S(p_cmd, cmd_size , cmd, cmd_size); + + /*写入数据*/ + if(!entry->data_in_cmd_flag) + { + zxic_comm_swap(data, data_size); + ZXIC_COMM_MEMCPY_S(p_data, data_size, data, data_size); + } + + return DPP_OK; +} + +/** 下表数据写入命令寄存器 +* @param dev_id 设备号 +* @param queue_id 队列号 +* @param down_table_len 数据长度,单位:字节; +* @param p_down_table_buff 下表数据缓存 +* @param p_element_id 返回下表使用的元素id +* @return +* @remark 无 +* @see +* @author cbb @date 2022/08/30 +************************************************************/ +DPP_STATUS dpp_dtb_write_down_table_data(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 down_table_len, + ZXIC_UINT8* p_down_table_buff, + ZXIC_UINT32 *p_element_id + ) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 dtb_interrupt_status = 0; + ZXIC_UINT32 dtb_down_check_times = 2; + ZXIC_UINT32 element_id = 0; + + ZXIC_COMM_CHECK_POINT_NO_ASSERT(dev); + + dtb_interrupt_status = dpp_dtb_interrupt_status_get(); + + while(dtb_down_check_times) + { + rc = dpp_dtb_tab_down_info_set(dev, + queue_id, + dtb_interrupt_status, + down_table_len / 4, + (ZXIC_UINT32 *)p_down_table_buff, + &element_id); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc,"dpp_dtb_tab_down_info_set"); + + rc = dpp_dtb_tab_down_success_status_check(dev, queue_id, element_id); + + if(rc != DPP_RC_DTB_OVER_TIME) + { + break; + } + + dtb_down_check_times --; + + if(dtb_down_check_times > 0) + { + ZXIC_COMM_PRINT("DTB DOWN TABLE OVERTIME, DOWN TABLE AGAIN----%d!\n", dtb_down_check_times); + } + + } + + *p_element_id = element_id; + + ZXIC_COMM_TRACE_INFO("down slot: %d, queue_id: %d, element id: %d\n", DEV_PCIE_SLOT(dev), queue_id, *p_element_id); + + return DPP_OK; +} + +/** 计算eram 128bit为单位的index +* @param dev_id 设备号 +* @param eram_mode eram 位宽模式 +* @param index 以eram_mode为单位的index +* @param p_row_index 出参，行 +* @param p_col_index 出参，列 +* @return +* @remark 无 +* @see +* @author cbb @date 2022/08/30 +************************************************************/ +DPP_STATUS dtb_eram_index_cal(DPP_DEV_T *dev, + ZXIC_UINT32 eram_mode, + ZXIC_UINT32 index, + ZXIC_UINT32 *p_row_index, + ZXIC_UINT32* p_col_index) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_UINT32 row_index = 0; + ZXIC_UINT32 col_index = 0; + + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_row_index); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_col_index); + + switch (eram_mode) + { + case ERAM128_TBL_128b: + { + row_index = index; + break; + } + + case ERAM128_TBL_64b: + { + row_index = (index >> 1); + col_index = index & 0x1; + break; + } + + case ERAM128_TBL_1b: + { + row_index = (index >> 7); + col_index = index & 0x7F; + break; + } + } + + *p_row_index = row_index; + *p_col_index = col_index; + + return rc; +} + +#if ZXIC_REAL("DTB BASE INTERFACE") + +/** smmu0数据组装函数,输入格式字段和数据，输出一个entry +* @param dev_id 芯片id +* @param mode 位宽模式 +* @param addr 1bit为单位的索引 +* @param p_data 要写入数据 +* @param p_entry 组装好的条目(已分配好空间) +* +* @return +* @remark 无 +* @see +* @author cbb @date 2022/08/30/ +************************************************************/ +DPP_STATUS dpp_dtb_smmu0_write_entry_data(DPP_DEV_T *dev, + ZXIC_UINT32 mode, + ZXIC_UINT32 addr, + ZXIC_UINT32 *p_data, + DPP_DTB_ENTRY_T *p_entry) +{ + + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 i = 0; + DPP_DTB_ERAM_TABLE_FORM_T dtb_eram_form_info = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev),DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_entry); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), mode, ERAM128_OPR_128b, ERAM128_OPR_32b); + + dtb_eram_form_info.valid = DTB_TABLE_VALID; + dtb_eram_form_info.type_mode = DTB_TABLE_MODE_ERAM; + dtb_eram_form_info.data_mode = mode; + dtb_eram_form_info.cpu_wr = 1; + dtb_eram_form_info.addr = addr; + dtb_eram_form_info.cpu_rd = 0; + dtb_eram_form_info.cpu_rd_mode = 0; + + if(dpp_dtb_prt_get()) + { + ZXIC_COMM_PRINT("dpp eram form info: \n"); + ZXIC_COMM_DBGCNT32_PRINT("valid", dtb_eram_form_info.valid); + ZXIC_COMM_DBGCNT32_PRINT("type_mode", dtb_eram_form_info.type_mode); + ZXIC_COMM_DBGCNT32_PRINT("data_mode", dtb_eram_form_info.data_mode); + ZXIC_COMM_DBGCNT32_PRINT("cpu_wr", dtb_eram_form_info.cpu_wr); + ZXIC_COMM_DBGCNT32_PRINT("addr", dtb_eram_form_info.addr); + ZXIC_COMM_DBGCNT32_PRINT("cpu_rd", dtb_eram_form_info.cpu_rd); + ZXIC_COMM_DBGCNT32_PRINT("cpu_rd_mode", dtb_eram_form_info.cpu_rd_mode); + } + + /*清空p_entry中数据*/ + if(ERAM128_OPR_128b == mode) + { + p_entry->data_in_cmd_flag = 0; + p_entry->data_size = 128 / 8; + + rc = dpp_dtb_write_table_cmd(DEV_ID(dev), DTB_TABLE_ERAM_128, &dtb_eram_form_info, p_entry->cmd); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_write_table_cmd"); + + ZXIC_COMM_MEMCPY(p_entry->data, p_data,128 / 8); + } + else if(ERAM128_OPR_64b == mode) + { + p_entry->data_in_cmd_flag = 1; + p_entry->data_size = 64 / 8; + dtb_eram_form_info.data_l = *(p_data + 1); + dtb_eram_form_info.data_h = *(p_data); + + rc = dpp_dtb_write_table_cmd(DEV_ID(dev), DTB_TABLE_ERAM_64, &dtb_eram_form_info, p_entry->cmd); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_write_table_cmd"); + + }else if(ERAM128_OPR_1b == mode) + { + p_entry->data_in_cmd_flag = 1; + p_entry->data_size = 1; + dtb_eram_form_info.data_h = *(p_data); + + rc = dpp_dtb_write_table_cmd(DEV_ID(dev), DTB_TABLE_ERAM_1, &dtb_eram_form_info, p_entry->cmd); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_write_table_cmd"); + } + + //打印出cmd buff中内容128bit + if(dpp_dtb_prt_get()) + { + ZXIC_COMM_PRINT("table type: %d\n", DTB_TABLE_MODE_ERAM); + ZXIC_COMM_PRINT("cmd: "); + for(i = 0; i < 4; i++) + { + ZXIC_COMM_PRINT("0x%08x ", ZXIC_COMM_CONVERT32(*((ZXIC_UINT32 *)(p_entry->cmd + 4 * i))));//转换成大端显示 + } + + if(p_entry->data_in_cmd_flag == 0) + { + if(p_entry->data) + { + ZXIC_COMM_PRINT("\ndata:"); + for(i = 0; i < 4; i++) + { + ZXIC_COMM_PRINT("0x%08x ", *((ZXIC_UINT32 *)(p_entry->data + 4 * i))); + } + ZXIC_COMM_PRINT("\n"); + } + } + + } + + return DPP_OK; +} + +/** smmu1数据组装函数,输入格式字段和数据，输出一个entry +* @param dev_id 芯片id +* @param rw_len 位宽 0-128bit, 1-256bit, 2-384bit, 3-512bit +* @param v46_flag ipv4,ipv6flag +* @param lpm_wr_vld lpm表写标识 lpm表数据时为1 +* @param base_addr 基地址 以4K*128为单位 +* @param index 以位宽为单位的索引 +* @param ecc_en ecc使能 +* @param p_data 要写入数据 +* @param p_entry 组装好的条目(已分配好空间) data空间大小为512bit +* +* @return +* @remark 无 +* @see +* @author cbb @date 2022/08/30/ +************************************************************/ +DPP_STATUS dpp_dtb_smmu1_write_entry_data(ZXIC_UINT32 dev_id, + ZXIC_UINT32 rw_len, + ZXIC_UINT32 v46_flag, + ZXIC_UINT32 lpm_wr_vld, + ZXIC_UINT32 base_addr, + ZXIC_UINT32 index, + ZXIC_UINT32 ecc_en, + ZXIC_UINT8 *p_data, + DPP_DTB_ENTRY_T *p_entry) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 i = 0; + ZXIC_UINT32 j = 0; + + DPP_DTB_DDR_TABLE_FORM_T dtb_ddr_form_info = {0}; /*DDR表格式*/ + + ZXIC_COMM_CHECK_INDEX_UPPER(dev_id, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_INDEX_UPPER(rw_len,SMMU1_DDR_WRT_512b); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_data); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_entry); + + /*DTB下表格式内容填充*/ + dtb_ddr_form_info.valid = DTB_TABLE_VALID; + dtb_ddr_form_info.type_mode = DTB_TABLE_MODE_DDR; + dtb_ddr_form_info.rw_len = rw_len; + dtb_ddr_form_info.v46_flag = v46_flag; + dtb_ddr_form_info.lpm_wr_vld = lpm_wr_vld; + dtb_ddr_form_info.baddr = base_addr; + dtb_ddr_form_info.ecc_en = ecc_en; + dtb_ddr_form_info.rw_addr = index; + + if(dpp_dtb_prt_get()) + { + ZXIC_COMM_PRINT("dtb_ddr_form_info:\n"); + ZXIC_COMM_DBGCNT32_PRINT("valid", dtb_ddr_form_info.valid); + ZXIC_COMM_DBGCNT32_PRINT("type_mode", dtb_ddr_form_info.type_mode); + ZXIC_COMM_DBGCNT32_PRINT("rw_len", dtb_ddr_form_info.rw_len); + ZXIC_COMM_DBGCNT32_PRINT("v46_flag", dtb_ddr_form_info.v46_flag); + ZXIC_COMM_DBGCNT32_PRINT("lpm_wr_vld", dtb_ddr_form_info.lpm_wr_vld); + ZXIC_COMM_DBGCNT32_PRINT("baddr", dtb_ddr_form_info.baddr); + ZXIC_COMM_DBGCNT32_PRINT("ecc_en", dtb_ddr_form_info.ecc_en); + ZXIC_COMM_DBGCNT32_PRINT("rw_addr", dtb_ddr_form_info.rw_addr); + } + + p_entry->data_in_cmd_flag = 0; + p_entry->data_size = DTB_LEN_POS_SETP * (rw_len + 1); + + rc = dpp_dtb_write_table_cmd(dev_id, DTB_TABLE_DDR, &dtb_ddr_form_info, p_entry->cmd); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_write_table_cmd"); + + ZXIC_COMM_MEMCPY(p_entry->data, p_data, DTB_LEN_POS_SETP * (rw_len + 1)); + + //打印出cmd buff中内容128bit + if(dpp_dtb_prt_get()) + { + ZXIC_COMM_PRINT("table type: %d\n", DTB_TABLE_MODE_DDR); + ZXIC_COMM_PRINT("cmd: "); + for(i = 0; i < 4; i++) + { + ZXIC_COMM_PRINT("0x%08x ", ZXIC_COMM_CONVERT32(*((ZXIC_UINT32 *)(p_entry->cmd + 4 * i))));//转换成大端显示 + } + + if(p_entry->data) + { + ZXIC_COMM_PRINT("\ndata:"); + for(j = 0; j < rw_len + 1; j++) + { + for(i = 0; i < 4; i++) + { + ZXIC_COMM_PRINT("0x%08x ", *((ZXIC_UINT32 *)(p_entry->data + 16 * j + 4 * i))); + } + ZXIC_COMM_PRINT("\n"); + } + } + } + + return DPP_OK; +} + + +/** zcam数据组装函数,输入格式字段和数据，输出一个entry +* @param dev_id 芯片id +* @param reg_sram_flag 读写ZCAM寄存器/sram标志位：1'b1：读写寄存器 1'b0：读写sram +* @param zgroup_id +* @param zblock_id +* @param zcell_id +* @param sram_addr 512bit为单位的地址 +* @param mask 写掩码：mask[3:0]分别对应CPU写数据的4个128-bit +* mask[0]对应[127:0],1'b0为不写该128-bit，1'b1为写； +* mask[1]对应[255:128]； +* mask[2]对应[383:256]； +* mask[3]对应[512:384] +* @param p_data 要写入数据 +* @param p_entry 组装好的条目(已分配好空间) data空间大小为512bit +* +* @return +* @remark 无 +* @see +* @author cbb @date 2022/08/30/ +************************************************************/ +DPP_STATUS dpp_dtb_zcam_write_entry_data(ZXIC_UINT32 dev_id, + ZXIC_UINT32 reg_sram_flag, + ZXIC_UINT32 zgroup_id, + ZXIC_UINT32 zblock_id, + ZXIC_UINT32 zcell_id, + ZXIC_UINT32 sram_addr, + ZXIC_UINT32 mask, + ZXIC_UINT8 *p_data, + DPP_DTB_ENTRY_T *p_entry) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 i = 0; + ZXIC_UINT32 j = 0; + + DPP_DTB_ZCAM_TABLE_FORM_T dtb_zcam_form_info = {0}; /*ZCAM表格式*/ + + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, zgroup_id, 0, SE_ZGRP_NUM - 1); + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, zblock_id, 0, ZBLK_NUM_PER_ZGRP - 1); + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, zcell_id, 0, SE_ZCELL_NUM - 1); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_data); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_entry); + + dtb_zcam_form_info.valid = DTB_TABLE_VALID; + dtb_zcam_form_info.type_mode = DTB_TABLE_MODE_ZCAM; + dtb_zcam_form_info.ram_reg_flag = reg_sram_flag; + dtb_zcam_form_info.zgroup_id = zgroup_id; + dtb_zcam_form_info.zblock_id = zblock_id; + dtb_zcam_form_info.zcell_id = zcell_id; + dtb_zcam_form_info.mask = mask; + dtb_zcam_form_info.sram_addr = sram_addr & 0x1FF; + + p_entry->data_in_cmd_flag = 0; + p_entry->data_size = DTB_LEN_POS_SETP * (DTB_ZCAM_LEN_SIZE - 1); + + rc = dpp_dtb_write_table_cmd(dev_id, DTB_TABLE_ZCAM, &dtb_zcam_form_info, p_entry->cmd); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_write_table_cmd"); + + ZXIC_COMM_MEMCPY(p_entry->data, p_data, DTB_LEN_POS_SETP * (DTB_ZCAM_LEN_SIZE - 1)); + + //打印出cmd buff中内容128bit + if(dpp_dtb_prt_get()) + { + ZXIC_COMM_PRINT("table type: %d\n", DTB_TABLE_MODE_ZCAM); + ZXIC_COMM_PRINT("cmd: "); + for(i = 0; i < 4; i++) + { + ZXIC_COMM_PRINT("0x%08x ", ZXIC_COMM_CONVERT32(*((ZXIC_UINT32 *)(p_entry->cmd + 4 * i))));//转换成小端显示 + } + + if(p_entry->data) + { + ZXIC_COMM_PRINT("\ndata:"); + for(j = 0; j < DTB_ZCAM_LEN_SIZE-1; j++) + { + for(i = 0; i < 4; i++) + { + ZXIC_COMM_PRINT("0x%08x ", *((ZXIC_UINT32 *)(p_entry->data + 16 * j + 4 * i))); + } + ZXIC_COMM_PRINT("\n"); + } + } + } + + + return DPP_OK; +} + + +/** etcam数据组装函数,输入格式字段和数据，输出一个entry +* @param dev_id 芯片id +* @param block_idx block索引 0 - 7 +* @param row_or_col_msk 1 write row mask reg 0:write col mask reg +* @param vben enable the valid bit addressed by addr +* @param reg_tcam_flag 1:配置内部row_col_mask寄存器 0：读写tcam +* @param flush 使能标识删除对应addr的表项条目，（80bit为单位，含义与wr_mode一一对应） +* @param rd_wr 读写标志 0写 1读 +* @param wr_mode 写入掩码，最高8bit，对应bit为1代表对应的80bit的数据 +* @param data_or_mask 数据或掩码标志 1：写x(data),0:写y(mask) +* @param ram_addr etcam地址（0-511） +* @param vbit valid bit input +* @param p_data 要写入数据 +* @param p_entry 组装好的条目(已分配好空间) data空间大小为640bit +* +* @return +* @remark 无 +* @see +* @author cbb @date 2022/08/30/ +************************************************************/ +DPP_STATUS dpp_dtb_etcam_write_entry_data(DPP_DEV_T *dev, + ZXIC_UINT32 block_idx, + ZXIC_UINT32 row_or_col_msk, + ZXIC_UINT32 vben, + ZXIC_UINT32 reg_tcam_flag, + ZXIC_UINT32 flush, + ZXIC_UINT32 rd_wr, + ZXIC_UINT32 wr_mode, + ZXIC_UINT32 data_or_mask, + ZXIC_UINT32 ram_addr, + ZXIC_UINT32 vbit, + ZXIC_UINT8 *p_data, + DPP_DTB_ENTRY_T *p_entry) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 i = 0; + ZXIC_UINT32 offset = 0; + ZXIC_UINT8 *p_temp = NULL; + + ZXIC_UINT8 buff[DPP_ETCAM_WIDTH_MAX / 8] = {0}; + DPP_DTB_ETCAM_TABLE_FORM_T dtb_etcam_form_info = {0}; /*etcam表格式*/ + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), block_idx, 0, DPP_ETCAM_BLOCK_NUM - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), row_or_col_msk, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), vben, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), reg_tcam_flag, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flush, 0, DPP_ETCAM_WR_MASK_MAX); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), rd_wr, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), wr_mode, 0, DPP_ETCAM_WR_MASK_MAX); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), data_or_mask, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), ram_addr, 0, DPP_ETCAM_RAM_DEPTH - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), vbit, 0, 0xff); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_entry); + + /*data etcam 下表格式内容填充*/ + dtb_etcam_form_info.valid = DTB_TABLE_VALID; + dtb_etcam_form_info.type_mode = DTB_TABLE_MODE_ETCAM; + dtb_etcam_form_info.block_sel = block_idx; + dtb_etcam_form_info.init_en = 0; + dtb_etcam_form_info.row_or_col_msk = row_or_col_msk; + dtb_etcam_form_info.vben = vben; + dtb_etcam_form_info.reg_tcam_flag = reg_tcam_flag; + dtb_etcam_form_info.uload = flush; + dtb_etcam_form_info.rd_wr = rd_wr;//0:写;1读 + dtb_etcam_form_info.wr_mode = wr_mode; + dtb_etcam_form_info.data_or_mask = data_or_mask; + dtb_etcam_form_info.addr = ram_addr; + dtb_etcam_form_info.vbit = vbit; + + if(dpp_dtb_prt_get()) + { + ZXIC_COMM_PRINT("dpp etcam form info: \n"); + ZXIC_COMM_DBGCNT32_PRINT("valid", dtb_etcam_form_info.valid); + ZXIC_COMM_DBGCNT32_PRINT("type_mode", dtb_etcam_form_info.type_mode); + ZXIC_COMM_DBGCNT32_PRINT("block_sel", dtb_etcam_form_info.block_sel); + ZXIC_COMM_DBGCNT32_PRINT("init_en", dtb_etcam_form_info.init_en); + ZXIC_COMM_DBGCNT32_PRINT("row_or_col_msk", dtb_etcam_form_info.row_or_col_msk); + ZXIC_COMM_DBGCNT32_PRINT("vben", dtb_etcam_form_info.vben); + ZXIC_COMM_DBGCNT32_PRINT("reg_tcam_flag", dtb_etcam_form_info.reg_tcam_flag); + ZXIC_COMM_DBGCNT32_PRINT("uload", dtb_etcam_form_info.uload); + ZXIC_COMM_DBGCNT32_PRINT("rd_wr", dtb_etcam_form_info.rd_wr); + ZXIC_COMM_DBGCNT32_PRINT("wr_mode", dtb_etcam_form_info.wr_mode); + ZXIC_COMM_DBGCNT32_PRINT("data_or_mask", dtb_etcam_form_info.data_or_mask); + ZXIC_COMM_DBGCNT32_PRINT("addr", dtb_etcam_form_info.addr); + ZXIC_COMM_DBGCNT32_PRINT("vbit", dtb_etcam_form_info.vbit); + } + + p_entry->data_in_cmd_flag = 0; + p_entry->data_size = DTB_LEN_POS_SETP * (DTB_ETCAM_LEN_SIZE - 1); + + rc = dpp_dtb_write_table_cmd(DEV_ID(dev), DTB_TABLE_ETCAM, &dtb_etcam_form_info, p_entry->cmd); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_write_table_cmd"); + + p_temp = p_data; + + /*将数据写入ETCAM表项处理*/ + /* 160bit key: high 80bit in tcam_ram1, low 80bit in tcam_ram0, and so on. */ + for (i = 0; i < DPP_ETCAM_RAM_NUM; i++) + { + offset = i * ((ZXIC_UINT32)DPP_ETCAM_WIDTH_MIN / 8); + + if ((wr_mode >> (DPP_ETCAM_RAM_NUM - 1 - i)) & 0x1) + { + ZXIC_COMM_MEMCPY(buff + offset, p_temp, DPP_ETCAM_WIDTH_MIN / 8); + p_temp += DPP_ETCAM_WIDTH_MIN / 8; + } + } + + zxic_comm_swap((ZXIC_UINT8 *)buff, DTB_LEN_POS_SETP * (DTB_ETCAM_LEN_SIZE - 1)); + + ZXIC_COMM_MEMCPY(p_entry->data, buff, DTB_LEN_POS_SETP * (DTB_ETCAM_LEN_SIZE - 1)); + + if(dpp_dtb_prt_get()) + { + ZXIC_COMM_PRINT("dpp_dtb_etcam_write_entry_data: \n"); + ZXIC_COMM_PRINT("wr_mode:0x%08x\n", wr_mode); + for(i = 0; i < 20; i++) + { + ZXIC_COMM_PRINT("0x%08x ",*((ZXIC_UINT32*)(buff + 4 * i))); + } + ZXIC_COMM_PRINT("\n"); + } + + return DPP_OK; +} + +/** 写eram，输出一个entry +* @param dev_id 芯片id +* @param base_addr 基地址，以128bit为单位 +* @param index 条目索引，以mode为单位 +* @param wr_mode 数据位宽模式,支持0：128bit 1：64bit 2:1bit +* @param p_data 待写入的数据 +* @param p_entry 组装好的数据 +* +* @return +* @remark 无 +* @see +* @author cbb @date 2022/08/30/ +************************************************************/ +DPP_STATUS dpp_dtb_se_smmu0_ind_write(DPP_DEV_T *dev, + ZXIC_UINT32 base_addr, + ZXIC_UINT32 index, + ZXIC_UINT32 wrt_mode, + ZXIC_UINT32 *p_data, + DPP_DTB_ENTRY_T *p_entry) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 temp_idx = 0; + ZXIC_UINT32 dtb_ind_addr = 0; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev),DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_entry); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), wrt_mode, ERAM128_OPR_128b, ERAM128_OPR_1b); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), base_addr, 0, SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1); + + if(dpp_dtb_prt_get()) + { + ZXIC_COMM_PRINT("dpp_dtb_se_smmu0_ind_write: \n"); + ZXIC_COMM_PRINT("base addr: 0x%08x\n",base_addr); + ZXIC_COMM_PRINT("index: 0x%08x\n",index); + ZXIC_COMM_PRINT("write mode: %d 0-128bit 1-64bit 2-1bit\n",wrt_mode); + } + + switch (wrt_mode) + { + case ERAM128_OPR_128b: + { + if((0xFFFFFFFF - (base_addr)) < (index)) + { + ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "ICM %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, base_addr, index, __FUNCTION__); + + return ZXIC_PAR_CHK_INVALID_INDEX; + } + if (base_addr + index > SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) + { + ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "dpp_dtb_se_smmu0_ind_write : index out of range !\n"); + return DPP_ERR; + } + + temp_idx = index << 7; + + break; + } + + case ERAM128_OPR_64b: + { + if ((base_addr + (index >> 1)) > SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) + { + ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "dpp_dtb_se_smmu0_ind_write : index out of range !\n"); + return DPP_ERR; + } + + temp_idx = index << 6; + + break; + } + + case ERAM128_OPR_1b: + { + if ((base_addr + (index >> 7)) > SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) + { + ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "dpp_dtb_se_smmu0_ind_write : index out of range !\n"); + return DPP_ERR; + } + + temp_idx = index; + } + } + + if((0xFFFFFFFF - (temp_idx)) < ((base_addr << 7) & DPP_ERAM128_BADDR_MASK)) + { + ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "ICM %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, temp_idx, ((base_addr << 7) & DPP_ERAM128_BADDR_MASK), __FUNCTION__); + return ZXIC_PAR_CHK_INVALID_INDEX; + } + + dtb_ind_addr = ((base_addr << 7) & DPP_ERAM128_BADDR_MASK) + temp_idx; + + if(dpp_dtb_prt_get()) + { + ZXIC_COMM_DBGCNT32_PRINT(" dtb eram item 1bit addr", dtb_ind_addr); + } + + rc = dpp_dtb_smmu0_write_entry_data(dev, + wrt_mode, + dtb_ind_addr, + p_data, + p_entry); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_smmu0_write_entry_data"); + + return DPP_OK; +} + +/** dtb写smmu0中的数据，数据长度在16K范围内 +* @param dev_id 设备号 +* @param queue_id 队列号 +* @param smmu0_base_addr smmu0基地址，以128bit为单位 +* @param smmu0_wr_mode smmu0写模式，参考DPP_ERAM128_OPR_MODE_E，仅支持128bit、64bit、1bit模式 +* @param entry_num 下发的条目数 +* @param p_entry_arr 待下发表项内容结构体数组指针 +* @param element_id 返回下表使用的元素id +* @return +* @remark 无 +* @see +* @author cbb @date 2024/01/04 +************************************************************/ +DPP_STATUS dpp_dtb_smmu0_data_write_cycle(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 smmu0_base_addr, + ZXIC_UINT32 smmu0_wr_mode, + ZXIC_UINT32 entry_num, + DPP_DTB_ERAM_ENTRY_INFO_T *p_entry_arr, + ZXIC_UINT32 *element_id) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_UINT32 item_cnt = 0; + ZXIC_UINT32 addr_offset = 0; + ZXIC_UINT32 dtb_len = 0; + ZXIC_UINT32 index = 0; + + ZXIC_UINT32 *p_entry_data = NULL; + ZXIC_UINT8 *table_data_buff = NULL; + ZXIC_UINT32 entry_data_buff[4] = {0}; + ZXIC_UINT8 cmd_buff[DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; + DPP_DTB_ENTRY_T dtb_one_entry = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DTB_QUEUE_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX_LOWER(DEV_ID(dev), entry_num, 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_entry_arr); + + //分配下表数据缓存 16K + table_data_buff = (ZXIC_UINT8 *) ZXIC_COMM_MALLOC(DPP_DTB_TABLE_DATA_BUFF_SIZE * sizeof(ZXIC_UINT8)); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), table_data_buff); + ZXIC_COMM_MEMSET(table_data_buff, 0, DPP_DTB_TABLE_DATA_BUFF_SIZE * sizeof(ZXIC_UINT8)); + + dtb_one_entry.cmd = cmd_buff; + dtb_one_entry.data = (ZXIC_UINT8 *)entry_data_buff; + + for(item_cnt = 0; item_cnt < entry_num; ++item_cnt) + { + p_entry_data = (ZXIC_UINT32 *)p_entry_arr[item_cnt].p_data; + ZXIC_COMM_CHECK_POINT_MEMORY_FREE_NO_ASSERT(p_entry_data, table_data_buff); + index = p_entry_arr[item_cnt].index; + + //将一个数据写入entry + rc = dpp_dtb_se_smmu0_ind_write(dev, + smmu0_base_addr, + index, + smmu0_wr_mode, + p_entry_data, + &dtb_one_entry); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_se_smmu0_ind_write", table_data_buff); + + switch (smmu0_wr_mode) + { + case ERAM128_OPR_128b: + { + dtb_len += 2; + addr_offset = item_cnt * DTB_LEN_POS_SETP * 2; + break; + } + + case ERAM128_OPR_64b: + { + dtb_len += 1; + addr_offset = item_cnt * DTB_LEN_POS_SETP; + break; + } + + case ERAM128_OPR_1b: + { + dtb_len += 1; + addr_offset = item_cnt * DTB_LEN_POS_SETP; + break; + } + } + + /*将表格式和数据写入缓存buff中*/ + rc = dpp_dtb_data_write(table_data_buff, addr_offset, &dtb_one_entry); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_data_write", table_data_buff); + ZXIC_COMM_MEMSET(cmd_buff, 0, DTB_TABLE_CMD_SIZE_BIT / 8); + ZXIC_COMM_MEMSET(entry_data_buff, 0, 4 * sizeof(ZXIC_UINT32)); + } + + if(dpp_dtb_prt_get()) + { + dpp_data_buff_print(table_data_buff, dtb_len * 16); + ZXIC_COMM_PRINT("start down table to dtb : queue_id: %d, down_data_len: %d\n", queue_id, dtb_len * 16); + } + + rc = dpp_dtb_write_down_table_data(dev, + queue_id, + dtb_len * 16, + table_data_buff, + element_id); + ZXIC_COMM_FREE(table_data_buff); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_write_down_table_data"); + + return DPP_OK; +} + +/** dtb写smmu0中的数据，数据长度不限 +* @param dev_id 设备号 +* @param queue_id 队列号 +* @param smmu0_base_addr smmu0基地址，以128bit为单位 +* @param smmu0_wr_mode smmu0写模式，参考DPP_ERAM128_OPR_MODE_E，仅支持128bit、64bit、1bit模式 +* @param entry_num 下发的条目数 +* @param p_entry_arr 待下发表项内容结构体数组指针 +* @param element_id 返回下表使用的元素id +* @return +* @remark 无 +* @see +* @author cbb @date 2024/01/04 +************************************************************/ +DPP_STATUS dpp_dtb_smmu0_data_write(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 smmu0_base_addr, + ZXIC_UINT32 smmu0_wr_mode, + ZXIC_UINT32 entry_num, + DPP_DTB_ERAM_ENTRY_INFO_T *p_entry_arr, + ZXIC_UINT32 *element_id) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_UINT32 i = 0; + ZXIC_UINT32 entry_num_max = 0; + ZXIC_UINT32 entry_cycle = 0; + ZXIC_UINT32 entry_remains = 0; + + DPP_DTB_ERAM_ENTRY_INFO_T *p_entry = NULL; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_POINT(p_entry_arr); + + switch (smmu0_wr_mode) + { + case ERAM128_OPR_128b: + { + entry_num_max = 0x1ff; + break; + } + + case ERAM128_OPR_64b: + { + entry_num_max = 0x3ff; + break; + } + + case ERAM128_OPR_1b: + { + entry_num_max = 0x3ff; + break; + } + } + + ZXIC_COMM_CHECK_INDEX_EQUAL(entry_num_max, 0); + entry_cycle = entry_num / entry_num_max; + entry_remains = entry_num % entry_num_max; + + for(i = 0; i < entry_cycle; ++i) + { + p_entry = p_entry_arr + entry_num_max * i; + rc = dpp_dtb_smmu0_data_write_cycle(dev, + queue_id, + smmu0_base_addr, + smmu0_wr_mode, + entry_num_max, + p_entry, + element_id); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_smmu0_data_write_cycle"); + + ZXIC_COMM_TRACE_INFO("dpp_dtb_smmu0_data_write_cycle[%d]: element_id = %d\n", i, *element_id); + } + + if(entry_remains) + { + p_entry = p_entry_arr + entry_num_max * entry_cycle; + rc = dpp_dtb_smmu0_data_write_cycle(dev, + queue_id, + smmu0_base_addr, + smmu0_wr_mode, + entry_remains, + p_entry, + element_id); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_smmu0_data_write_cycle"); + + ZXIC_COMM_TRACE_INFO("dpp_dtb_smmu0_data_write_cycle: element_id = %d\n", *element_id); + } + + return DPP_OK; +} + +/** dtb flush smmu0中的数据，数据长度16K以内 +* @param dev_id 设备号 +* @param queue_id 队列号 +* @param smmu0_base_addr smmu0基地址，以128bit为单位 +* @param smmu0_wr_mode smmu0写模式，参考DPP_ERAM128_OPR_MODE_E，仅支持128bit、64bit、1bit模式 +* @param start_index flush开始的条目 +* @param entry_num 下发的条目数 +* @param element_id 返回下表使用的元素id +* @return +* @remark 无 +* @see +* @author cbb @date 2024/01/04 +************************************************************/ +DPP_STATUS dpp_dtb_smmu0_flush_cycle(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 smmu0_base_addr, + ZXIC_UINT32 smmu0_wr_mode, + ZXIC_UINT32 start_index, + ZXIC_UINT32 entry_num, + ZXIC_UINT32 *element_id) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_UINT32 index = 0; + ZXIC_UINT32 current_index = 0; + ZXIC_UINT32 entry_data_buff[4] = {0}; + DPP_DTB_ERAM_ENTRY_INFO_T *p_entry_arr = NULL; + + ZXIC_COMM_CHECK_POINT(dev); + + p_entry_arr = (DPP_DTB_ERAM_ENTRY_INFO_T *)ZXIC_COMM_MALLOC(entry_num * sizeof(DPP_DTB_ERAM_ENTRY_INFO_T)); + ZXIC_COMM_CHECK_POINT(p_entry_arr); + ZXIC_COMM_MEMSET(p_entry_arr, 0, entry_num * sizeof(DPP_DTB_ERAM_ENTRY_INFO_T)); + + for(index = 0; index < entry_num; index++) + { + current_index = start_index + index; + + p_entry_arr[index].index = current_index; + p_entry_arr[index].p_data = entry_data_buff; + } + + rc = dpp_dtb_smmu0_data_write_cycle(dev, + queue_id, + smmu0_base_addr, + smmu0_wr_mode, + entry_num, + p_entry_arr, + element_id); + ZXIC_COMM_FREE(p_entry_arr); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_smmu1_data_write_cycle"); + + return rc; +} + +/** dtb flush smmu0中的数据,大数据量 +* @param dev_id 设备号 +* @param queue_id 队列号 +* @param smmu0_base_addr smmu0基地址，以128bit为单位 +* @param smmu0_wr_mode smmu0写模式，参考DPP_ERAM128_OPR_MODE_E，仅支持128bit、64bit、1bit模式 +* @param start_index flush开始的条目 +* @param entry_num 下发的条目数 +* @param element_id 返回下表使用的元素id +* @return +* @remark 无 +* @see +* @author cbb @date 2024/01/04 +************************************************************/ +DPP_STATUS dpp_dtb_smmu0_flush(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 smmu0_base_addr, + ZXIC_UINT32 smmu0_wr_mode, + ZXIC_UINT32 start_index, + ZXIC_UINT32 entry_num, + ZXIC_UINT32 *element_id) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 entry_num_max = 0; + ZXIC_UINT32 entry_cycle = 0; + ZXIC_UINT32 entry_remains = 0; + ZXIC_UINT32 temp_start_index = 0; + ZXIC_UINT32 i = 0; + + ZXIC_COMM_CHECK_POINT(dev); + + switch (smmu0_wr_mode) + { + case ERAM128_OPR_128b: + { + entry_num_max = 0x1ff; + break; + } + + case ERAM128_OPR_64b: + { + entry_num_max = 0x3ff; + break; + } + + case ERAM128_OPR_1b: + { + entry_num_max = 0x3ff; + break; + } + } + + ZXIC_COMM_CHECK_INDEX_EQUAL(entry_num_max, 0); + entry_cycle = entry_num / entry_num_max; + entry_remains = entry_num % entry_num_max; + + for(i = 0; i < entry_cycle; ++i) + { + temp_start_index = entry_num_max * i + start_index; + + rc = dpp_dtb_smmu0_flush_cycle(dev, + queue_id, + smmu0_base_addr, + smmu0_wr_mode, + temp_start_index, + entry_num_max, + element_id); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_smmu0_flush_cycle"); + + ZXIC_COMM_TRACE_INFO("dpp_dtb_smmu0_flush_cycle[%d] element_id = %d\n",i,*element_id); + } + + if(entry_remains) + { + temp_start_index = entry_num_max * entry_cycle + start_index; + rc = dpp_dtb_smmu0_flush_cycle(dev, + queue_id, + smmu0_base_addr, + smmu0_wr_mode, + temp_start_index, + entry_remains, + element_id); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_smmu0_flush_cycle"); + + ZXIC_COMM_TRACE_INFO("dpp_dtb_smmu0_flush_cycle: element_id = %d\n",*element_id); + } + + return 0; +} + +/** ddr直接表 写数据 +* @param dev_id 芯片id +* @param base_addr 基地址，以4K*128bit为单位 +* @param rw_len 数据位宽模式，位宽 0-128bit, 1-256bit, 2-384bit, 3-512bit,取值参考SMMU1_DDR_WRT_MODE_E的定义 +* @param index 条目索引，以mode为单位 +* @param ecc_en 直接表ECC使能位 +* @param p_data 待写入的数据指针 +* @param p_entry 组装好的条目(已分配好空间) +* +* @return +* @remark 无 +* @see +* @author cbb @date 2022/08/30/ +************************************************************/ +DPP_STATUS dpp_dtb_ddr_dir_table_data_write(ZXIC_UINT32 dev_id, + ZXIC_UINT32 base_addr, + ZXIC_UINT32 rw_len, + ZXIC_UINT32 index, + ZXIC_UINT32 ecc_en, + ZXIC_UINT8 *p_data, + DPP_DTB_ENTRY_T *p_entry) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_UINT32 ipv4_v6_flag = 0; + ZXIC_UINT32 lpm_vld = 0; + + ZXIC_COMM_CHECK_INDEX_UPPER(dev_id, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_INDEX_UPPER(rw_len,SMMU1_DDR_WRT_512b); + ZXIC_COMM_CHECK_INDEX_UPPER(ecc_en,1); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_data); + + rc = dpp_dtb_smmu1_write_entry_data(dev_id, + rw_len, + ipv4_v6_flag, + lpm_vld, + base_addr, + index, + ecc_en, + p_data, + p_entry); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_smmu1_write_entry_data"); + + return DPP_OK; +} + + +/** ddr直接表 写数据 +* @param dev_id 芯片id +* @param base_addr 基地址，以4K*128bit为单位 +* @param rw_len 数据位宽模式，位宽 0-128bit, 1-256bit, 2-384bit, 3-512bit,取值参考SMMU1_DDR_WRT_MODE_E的定义 +* @param index 条目索引，以mode为单位 +* @param ecc_en ecc是否使能 +* @param p_data 待写入的数据指针 +* @param p_entry 组装好的条目(已分配好空间) +* +* @return +* @remark 无 +* @see +* @author cbb @date 2022/08/30/ +************************************************************/ +DPP_STATUS dpp_dtb_ddr_hash_table_data_write(ZXIC_UINT32 dev_id, + ZXIC_UINT32 base_addr, + ZXIC_UINT32 rw_len, + ZXIC_UINT32 index, + ZXIC_UINT32 ecc_en, + ZXIC_UINT8 *p_data, + DPP_DTB_ENTRY_T *p_entry) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 ipv4_v6_flag = 0; + ZXIC_UINT32 lpm_vld = 0; + + ZXIC_COMM_CHECK_INDEX_UPPER(dev_id, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_INDEX_UPPER(rw_len,SMMU1_DDR_WRT_512b); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_data); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_entry); + + rc = dpp_dtb_smmu1_write_entry_data(dev_id, + rw_len, + ipv4_v6_flag, + lpm_vld, + base_addr, + index, + ecc_en, + p_data, + p_entry); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_smmu1_write_entry_data"); + + return DPP_OK; +} + +/** dtb 通道 se alg间接写zcam空间 +* @param dev_id 芯片id +* @param addr 基地址，以4K*128bit为单位 +* @param p_data 待写入的数据指针 +* @param p_entry 组装好的条目(已分配好空间) +* +* @return +* @remark 无 +* @see +* @author cbb @date 2022/08/30/ +************************************************************/ +DPP_STATUS dpp_dtb_se_alg_zcam_data_write(ZXIC_UINT32 dev_id, + ZXIC_UINT32 addr, + ZXIC_UINT8 *p_data, + DPP_DTB_ENTRY_T *p_entry) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 reg_sram_flag = 0; + ZXIC_UINT32 zgroup_id = 0; + ZXIC_UINT32 zblock_id = 0; + ZXIC_UINT32 zcell_id = 0; + ZXIC_UINT32 mask = 0; + ZXIC_UINT32 sram_addr = 0; + + ZXIC_COMM_CHECK_INDEX_UPPER(dev_id, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_data); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_entry); + + mask = (addr >> 17) & 0xF; + reg_sram_flag = (addr >> 16) & 0x1; + zgroup_id = (addr >> 14) & 0x3; + zblock_id = (addr >> 11) & 0x7; + zcell_id = (addr >> 9) & 0x3; + sram_addr = addr & 0x1FF; + + if(dpp_dtb_prt_get()) + { + ZXIC_COMM_PRINT("dpp_dtb_se_alg_zcam_data_write: \n"); + ZXIC_COMM_DBGCNT32_PRINT("addr", addr); + ZXIC_COMM_DBGCNT32_PRINT("mask", mask); + ZXIC_COMM_DBGCNT32_PRINT("reg_sram_flag", reg_sram_flag); + ZXIC_COMM_DBGCNT32_PRINT("zgroup_id", zgroup_id); + ZXIC_COMM_DBGCNT32_PRINT("zblock_id", zblock_id); + ZXIC_COMM_DBGCNT32_PRINT("zcell_id", zcell_id); + ZXIC_COMM_DBGCNT32_PRINT("sram_addr", sram_addr); + } + + rc = dpp_dtb_zcam_write_entry_data(dev_id, + reg_sram_flag, + zgroup_id, + zblock_id, + zcell_id, + sram_addr, + mask, + p_data, + p_entry); + + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_zcam_write_entry_data"); + + return DPP_OK; +} + +#endif + +#if ZXIC_REAL("DOWN_TABLE") +/** 将HASH表数据格式写入form_buff中 +* @param p_hash_cfg hash表配置指针 +* @param p_rbkey_rtn 红黑树新节点信息指针 +* @param entry_data 条目数据缓存缓存 +* +* @return +* @remark 无 +* @see +* @author cbb @date 2022/08/30 +************************************************************/ +DPP_STATUS dpp_dtb_hash_form_write(DPP_HASH_CFG *p_hash_cfg, + DPP_HASH_RBKEY_INFO *p_rbkey_new, + ZXIC_UINT32 actu_key_size, + DPP_DTB_ENTRY_T *p_entry) +{ + ZXIC_UINT8 table_id = 0; + ZXIC_UINT32 key_type = 0; + ZXIC_UINT32 key_by_size = 0; + ZXIC_UINT32 rst_by_size = 0; + ZXIC_UINT32 byte_offset = 0; + + ZXIC_UINT32 i = 0; + ZXIC_UINT32 index = 0; + ZXIC_UINT32 bulk_id = 0; + ZXIC_UINT32 temp_mask = 0; + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 ddr_wr_mode = 0; + ZXIC_UINT32 addr; + + D_NODE *p_entry_dn = NULL; + HASH_DDR_CFG *p_ddr_cfg = NULL; + SE_ITEM_CFG *p_item_info = NULL; + DPP_HASH_RBKEY_INFO *p_rbkey = NULL; + ZXIC_UINT8 entry_data[SE_ENTRY_WIDTH_MAX] = {0}; + + ZXIC_COMM_CHECK_POINT(p_hash_cfg); + ZXIC_COMM_CHECK_POINT(p_rbkey_new); + + dev_id = p_hash_cfg->p_se_info->dev_id; + ZXIC_COMM_CHECK_INDEX_UPPER(dev_id,DPP_DEV_CHANNEL_MAX - 1); + + ZXIC_COMM_MEMSET(entry_data,0x0,sizeof(entry_data)); + p_item_info = p_rbkey_new->p_item_info; + ZXIC_COMM_CHECK_POINT(p_item_info); + + if (p_item_info->item_type == ITEM_DDR_256 || p_item_info->item_type == ITEM_DDR_512)//hash条目存在DDR中 + { + table_id = DPP_GET_HASH_TBL_ID(p_rbkey_new->key); + bulk_id = ((table_id >> 2) & 0x7); + ZXIC_COMM_CHECK_INDEX_UPPER(bulk_id,HASH_BULK_NUM - 1); + p_ddr_cfg = p_hash_cfg->p_bulk_ddr_info[bulk_id]; + key_type = DPP_GET_HASH_KEY_TYPE(p_rbkey_new->key); + key_by_size = DPP_GET_KEY_SIZE(actu_key_size); + + switch (key_type) + { + case HASH_KEY_128b: + { + rst_by_size = 16U - DPP_GET_ACTU_KEY_BY_SIZE(actu_key_size) - HASH_KEY_CTR_SIZE; + break; + } + case HASH_KEY_256b: + { + rst_by_size = 32U - DPP_GET_ACTU_KEY_BY_SIZE(actu_key_size) - HASH_KEY_CTR_SIZE; + break; + } + case HASH_KEY_512b: + { + rst_by_size = 64U - DPP_GET_ACTU_KEY_BY_SIZE(actu_key_size) - HASH_KEY_CTR_SIZE; + break; + } + default: + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n ErrorCode[%x]: Invalid key type.", DPP_HASH_RC_INVALID_KEY_TYPE); + return DPP_HASH_RC_INVALID_KEY_TYPE; + } + + } + + /* 计算index */ + if (DDR_WIDTH_256b == p_ddr_cfg->width_mode) + { + if (HASH_KEY_128b == key_type) + { + index = (p_item_info->hw_addr << 1) + p_rbkey_new->entry_pos; + } + else if (HASH_KEY_256b == key_type) + { + index = p_item_info->hw_addr; + } + } + else if (DDR_WIDTH_512b == p_ddr_cfg->width_mode) + { + if (HASH_KEY_128b == key_type) + { + index = (p_item_info->hw_addr << 2) + p_rbkey_new->entry_pos; + } + else if (HASH_KEY_256b == key_type) + { + index = (p_item_info->hw_addr << 2) + p_rbkey_new->entry_pos; + index = index >> 1; + } + else + { + index = p_item_info->hw_addr; + } + } + + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "ddr index(unit by key_type) is 0x%x \n", index); + + ddr_wr_mode = DPP_GET_DDR_WR_MODE(key_type); + + /*将数据组合成一个数组中并写入缓存中进行保存*/ + ZXIC_COMM_MEMCPY(entry_data, p_rbkey_new->key, key_by_size); + ZXIC_COMM_MEMCPY(entry_data + key_by_size, p_rbkey_new->rst, ((rst_by_size > HASH_RST_MAX) ? HASH_RST_MAX : rst_by_size)); + zxic_comm_swap(entry_data, SE_ENTRY_WIDTH_MAX); + dpp_dtb_ddr_hash_table_data_write(dev_id, + p_ddr_cfg->ddr_baddr, + ddr_wr_mode, + index, + p_ddr_cfg->ddr_ecc_en, + entry_data, + p_entry); + ZXIC_COMM_TRACE_DEBUG("entry_data is:"); + + for (i = 0; i < SE_ENTRY_WIDTH_MAX; i++) + { + ZXIC_COMM_TRACE_DEBUG("0x%02x ", entry_data[i]); + } + + ZXIC_COMM_TRACE_DEBUG("\n"); + + } + else /* hash条目存在zcam上*/ + { + /*写ZCAM表格式*/ + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "zcam p_item_info->hw_addr is 0x%x \n", p_item_info->hw_addr); + addr = p_item_info->hw_addr; + + /*将数据组合成一个数组中并写入缓存中进行保存*/ + p_entry_dn = p_item_info->item_list.p_next; + + while (p_entry_dn) + { + p_rbkey = (DPP_HASH_RBKEY_INFO *)(p_entry_dn->data); + // table_id = DPP_GET_HASH_TBL_ID(p_rbkey->key); + key_type = DPP_GET_HASH_KEY_TYPE(p_rbkey->key); + key_by_size = DPP_GET_KEY_SIZE(actu_key_size); + ZXIC_COMM_CHECK_INDEX_UPPER(key_by_size,HASH_KEY_MAX); + rst_by_size = DPP_GET_RST_SIZE(key_type, actu_key_size); + + byte_offset = p_rbkey->entry_pos * HASH_ENTRY_POS_STEP; + ZXIC_COMM_MEMCPY(entry_data + byte_offset, p_rbkey->key, key_by_size); + ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(dev_id, byte_offset, key_by_size); + byte_offset += key_by_size; + ZXIC_COMM_MEMCPY(entry_data + byte_offset, p_rbkey->rst, ((rst_by_size > HASH_RST_MAX) ? HASH_RST_MAX : rst_by_size)); + + temp_mask |= ((((1U << (p_rbkey->entry_size/16U)) - 1U) << (4U - p_rbkey->entry_size/16U - p_rbkey->entry_pos)) & 0xF);//计算掩码 + + p_entry_dn = p_entry_dn->next; + } + + zxic_comm_swap(entry_data, SE_ENTRY_WIDTH_MAX); + + dpp_dtb_se_alg_zcam_data_write(dev_id, + addr, + entry_data, + p_entry); + + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "zcam_item_data is:"); + + for (i = 0; i < SE_ITEM_WIDTH_MAX; i++) + { + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "0x%02x ", entry_data[i]); + } + + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "\n"); + } + + return DPP_OK; +} + + +/** 增加hash表条目时写buff函数 +* @param dev_id 设备号 +* @param p_hash_entry_cfg 该hash条目的格式内容信息 +* @param p_data_buff 保存用于dtb下表数据的buff +* @param index 该hash条目的编号 +* @param p_dtb_len 下发完该hash表条目后dtb数据的长度 +* @return +* @remark 无 +* @see +* @author cbb @date 2023/06/03 +************************************************************/ +DPP_STATUS dpp_dtb_add_hash_buf_write(ZXIC_UINT32 dev_id, + HASH_ENTRY_CFG *p_hash_entry_cfg, + ZXIC_UINT8 *p_data_buff, + ZXIC_UINT32 index, + ZXIC_UINT32 *p_dtb_len) +{ + DPP_STATUS rc = DPP_OK; + SE_ITEM_CFG *p_item_info = NULL; + ZXIC_UINT32 ddr_wr_mode = 0; + ZXIC_UINT32 addr_offset = 0; + DPP_DTB_ENTRY_T dtb_one_entry = {0}; /*条目结构*/ + ZXIC_UINT8 cmd_buff[DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; /*命令格式缓存*/ + ZXIC_UINT8 hash_entry_data[SE_ENTRY_WIDTH_MAX] = {0}; + + ZXIC_COMM_CHECK_POINT(p_hash_entry_cfg); + ZXIC_COMM_CHECK_POINT(p_hash_entry_cfg->p_rbkey_new); + ZXIC_COMM_CHECK_POINT(p_dtb_len); + + ZXIC_COMM_MEMSET(cmd_buff,0x0,sizeof(cmd_buff)); + ZXIC_COMM_MEMSET(hash_entry_data,0x0,sizeof(hash_entry_data)); + dtb_one_entry.cmd = cmd_buff; + dtb_one_entry.data = hash_entry_data; + + /*将位置信息和数据信息写入buff中*/ + rc = dpp_dtb_hash_form_write(p_hash_entry_cfg->p_hash_cfg, + p_hash_entry_cfg->p_rbkey_new, + p_hash_entry_cfg->actu_key_size, + &dtb_one_entry); /*计算一个条目的位置信息，并保存起来*/ + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_dtb_hash_form_write"); + + p_item_info = p_hash_entry_cfg->p_rbkey_new->p_item_info; + ZXIC_COMM_CHECK_POINT(p_item_info); + ddr_wr_mode = DPP_GET_DDR_WR_MODE(p_hash_entry_cfg->key_type); + + /*将数据写入缓存中，并更新长度统计*/ + if(p_item_info->item_type == ITEM_DDR_256 || p_item_info->item_type == ITEM_DDR_512) + { + dtb_one_entry.data_size = DTB_LEN_POS_SETP * (ddr_wr_mode + 1); + addr_offset = index * (ddr_wr_mode + 2) * DTB_LEN_POS_SETP; /*在缓存中相对于0的offset*/ + (*p_dtb_len) += (ddr_wr_mode + 2);//dtb长度进行计数 + } + else/*ram or reg*/ + { + dtb_one_entry.data_size = DTB_LEN_POS_SETP * (DTB_ZCAM_LEN_SIZE - 1); + addr_offset = index * DTB_ZCAM_LEN_SIZE * DTB_LEN_POS_SETP; /*在缓存中相对于0的offset*/ + (*p_dtb_len) += DTB_ZCAM_LEN_SIZE;//dtb长度进行计数 + } + + rc = dpp_dtb_data_write(p_data_buff, addr_offset, &dtb_one_entry); /*将数据写入缓存中*/ + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_data_write"); + + return rc; +} + +/** 删除hash表条目时写buff函数 +* @param dev_id 设备号 +* @param p_hash_entry_cfg 该hash条目的格式内容信息 +* @param p_data_buff 保存用于dtb下表数据的buff +* @param index 该hash条目的编号 +* @param p_dtb_len 下发完该hash表条目后dtb数据的长度 +* @return +* @remark 无 +* @see +* @author cbb @date 2023/06/03 +************************************************************/ +DPP_STATUS dpp_dtb_delete_hash_buf_write(ZXIC_UINT32 dev_id, + HASH_ENTRY_CFG *p_hash_entry_cfg, + ZXIC_UINT8 *p_data_buff, + ZXIC_UINT32 index, + ZXIC_UINT32 *p_dtb_len) +{ + DPP_STATUS rc = DPP_OK; + SE_ITEM_CFG *p_item_info = NULL; + ZXIC_UINT32 ddr_wr_mode = 0; + ZXIC_UINT32 addr_offset = 0; + DPP_DTB_ENTRY_T dtb_one_entry = {0}; /*条目结构*/ + ZXIC_UINT8 cmd_buff[DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; /*命令格式缓存*/ + ZXIC_UINT8 hash_entry_data[SE_ENTRY_WIDTH_MAX] = {0}; + + ZXIC_COMM_CHECK_POINT(p_hash_entry_cfg); + ZXIC_COMM_CHECK_POINT(p_hash_entry_cfg->p_rbkey_new); + ZXIC_COMM_CHECK_POINT(p_dtb_len); + + ZXIC_COMM_MEMSET(cmd_buff,0x0,sizeof(cmd_buff)); + ZXIC_COMM_MEMSET(hash_entry_data,0x0,sizeof(hash_entry_data)); + dtb_one_entry.cmd = cmd_buff; + dtb_one_entry.data = hash_entry_data; + + /*将位置信息和数据信息写入buff中*/ + rc = dpp_dtb_hash_form_write(p_hash_entry_cfg->p_hash_cfg, + p_hash_entry_cfg->p_rbkey_new, + p_hash_entry_cfg->actu_key_size, + &dtb_one_entry); /*计算一个条目的位置信息，并保存起来*/ + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_dtb_hash_form_write"); + + p_item_info = p_hash_entry_cfg->p_rbkey_new->p_item_info; + ZXIC_COMM_CHECK_POINT(p_item_info); + ddr_wr_mode = DPP_GET_DDR_WR_MODE(p_hash_entry_cfg->key_type); + + /*将数据写入缓存中，并更新长度统计*/ + if(p_item_info->item_type == ITEM_DDR_256 || p_item_info->item_type == ITEM_DDR_512) + { + dtb_one_entry.data_size = DTB_LEN_POS_SETP * (ddr_wr_mode + 1); + addr_offset = index * (ddr_wr_mode + 2) * DTB_LEN_POS_SETP; /*在缓存中相对于0的offset*/ + (*p_dtb_len) += (ddr_wr_mode + 2);//dtb长度进行计数 + } + else/*ram or reg*/ + { + dtb_one_entry.data_size = DTB_LEN_POS_SETP * (DTB_ZCAM_LEN_SIZE - 1); + addr_offset = index * DTB_ZCAM_LEN_SIZE * DTB_LEN_POS_SETP; /*在缓存中相对于0的offset*/ + (*p_dtb_len) += DTB_ZCAM_LEN_SIZE;//dtb长度进行计数 + } + + ZXIC_COMM_MEMSET(dtb_one_entry.data, 0x0, dtb_one_entry.data_size);//清除下表数据 + + rc = dpp_dtb_data_write(p_data_buff, addr_offset, &dtb_one_entry); /*将数据写入缓存中*/ + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_data_write"); + + return rc; +} + + + +/***********************************************************/ +/** dtb 添加eTcam表条目,将etcam条目内容写入到entry中 +* @param dev_id 设备号 +* @param addr 每个block中的ram地址，位宽为8*80bit +* @param block_idx block编号，范围0~7 +* @param wr_mask 写表掩码，共8bit，每bit控制ram中对应位置的80bit数据是否有效 +* @param opr_type etcam操作类型，详见 DPP_ETCAM_OPR_TYPE_E +* @param p_entry 条目数据，data和mask +* @param p_entry_data 组装好的数据条目(已分配好空间) +* @param p_entry_mask 组装好的掩码条目(已分配好空间) +* +* @return +* @remark 无 +* @see +* @author 王春雷 @date 2014/04/03 +************************************************************/ +DPP_STATUS dpp_dtb_etcam_entry_add(DPP_DEV_T *dev, + ZXIC_UINT32 addr, + ZXIC_UINT32 block_idx, + ZXIC_UINT32 wr_mask, + ZXIC_UINT32 opr_type, + DPP_ETCAM_ENTRY_T *p_entry, + DPP_DTB_ENTRY_T *p_entry_data, + DPP_DTB_ENTRY_T *p_entry_mask + ) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT8 temp_data[DPP_ETCAM_WIDTH_MAX / 8] = {0}; + ZXIC_UINT8 temp_mask[DPP_ETCAM_WIDTH_MAX / 8] = {0}; + DPP_ETCAM_ENTRY_T entry_xy = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), addr, 0, DPP_ETCAM_RAM_DEPTH - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), block_idx, 0, DPP_ETCAM_BLOCK_NUM - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), wr_mask, 0, DPP_ETCAM_WR_MASK_MAX); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), opr_type, DPP_ETCAM_OPR_DM, DPP_ETCAM_OPR_XY); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_entry); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_entry_data); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_entry_mask); + + ZXIC_COMM_ASSERT(p_entry->p_data && p_entry->p_mask); + + entry_xy.p_data = temp_data; + entry_xy.p_mask = temp_mask; + + if (opr_type == DPP_ETCAM_OPR_DM) + { + /* convert user D/M data to X/Y */ + rc = dpp_etcam_dm_to_xy(p_entry, &entry_xy, DPP_ETCAM_ENTRY_SIZE_GET(p_entry->mode)); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_etcam_dm_to_xy"); + } + else + { + ZXIC_COMM_MEMCPY(entry_xy.p_data, p_entry->p_data, DPP_ETCAM_ENTRY_SIZE_GET(p_entry->mode));//复制出实际的数据 + ZXIC_COMM_MEMCPY(entry_xy.p_mask, p_entry->p_mask, DPP_ETCAM_ENTRY_SIZE_GET(p_entry->mode)); + } + + if(dpp_dtb_prt_get()) + { + ZXIC_COMM_PRINT("etcam xy:/n"); + dpp_acl_data_print(entry_xy.p_data, entry_xy.p_mask, p_entry->mode); + } + + /*组装data格式*/ + rc = dpp_dtb_etcam_write_entry_data(dev, + block_idx, + 0, + 1, + 0, + 0, + 0,//0:写;1读 + wr_mask, + DPP_ETCAM_DTYPE_DATA, + addr, + 0, + entry_xy.p_data, + p_entry_data); + + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_etcam_write_entry_data"); + + /*组装mask格式*/ + rc = dpp_dtb_etcam_write_entry_data(dev, + block_idx, + 0, + 1, + 0, + 0, + 0, + wr_mask , + DPP_ETCAM_DTYPE_MASK , + addr , + 0xFF, + entry_xy.p_mask, + p_entry_mask); + + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_etcam_write_entry_data"); + + return DPP_OK; +} + +/** dtb写eRam表 +* @param dev_id 设备号 +* @param queue_id 队列号 +* @param sdt_no eram表sdt表号 +* @param entry_cnt 下发的条目数 +* @param p_entry_arr 待下发表项内容结构体数组指针 +* @param element_id 返回下表使用的元素id +* @return +* @remark 无 +* @see +* @author cbb @date 2022/08/30 +************************************************************/ +DPP_STATUS dpp_dtb_eram_dma_write_cycle(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 sdt_no, + ZXIC_UINT32 entry_num, + DPP_DTB_ERAM_ENTRY_INFO_T *p_entry_arr, + ZXIC_UINT32 *element_id + ) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_UINT32 wrt_mode; + ZXIC_UINT32 base_addr; + ZXIC_UINT32 index; + ZXIC_UINT32 item_cnt = 0; + ZXIC_UINT32 addr_offset = 0; + ZXIC_UINT32 *p_entry_data = NULL; + ZXIC_UINT32 dtb_len = 0; + + ZXIC_UINT8 *table_data_buff = NULL; + ZXIC_UINT32 entry_data_buff[4] = {0}; + ZXIC_UINT8 cmd_buff[DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; + + DPP_SDTTBL_ERAM_T sdt_eram_info = {0}; + DPP_DTB_ENTRY_T dtb_one_entry = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DTB_QUEUE_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX_LOWER(DEV_ID(dev), entry_num, 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_entry_arr); + + //分配下表数据缓存 16K + table_data_buff = (ZXIC_UINT8 *) ZXIC_COMM_MALLOC(DPP_DTB_TABLE_DATA_BUFF_SIZE * sizeof(ZXIC_UINT8)); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), table_data_buff); + ZXIC_COMM_MEMSET(table_data_buff, 0, DPP_DTB_TABLE_DATA_BUFF_SIZE * sizeof(ZXIC_UINT8)); + + dtb_one_entry.cmd = cmd_buff; + dtb_one_entry.data = (ZXIC_UINT8 *)entry_data_buff; + + //从sdt_no中获取SDT配置 + rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_eram_info); + ZXIC_COMM_CHECK_DEV_RC_MEMORY_FREE(DEV_ID(dev), rc, "dpp_soft_sdt_tbl_get", table_data_buff); + base_addr = sdt_eram_info.eram_base_addr; + wrt_mode = sdt_eram_info.eram_mode;//3:128 + + switch (wrt_mode) + { + case ERAM128_TBL_128b: + { + wrt_mode = ERAM128_OPR_128b; + break; + } + + case ERAM128_TBL_64b: + { + wrt_mode = ERAM128_OPR_64b; + break; + } + + case ERAM128_TBL_1b: + { + wrt_mode = ERAM128_OPR_1b; + break; + } + } + + for(item_cnt = 0; item_cnt < entry_num; ++item_cnt) + { + p_entry_data = (ZXIC_UINT32 *)p_entry_arr[item_cnt].p_data; + ZXIC_COMM_CHECK_DEV_POINT_MEMORY_FREE(DEV_ID(dev), p_entry_data, table_data_buff); + index = p_entry_arr[item_cnt].index; + + if(dpp_dtb_prt_get()) + { + ZXIC_COMM_PRINT("dpp_dtb_eram_dma_write_cycle : the item index is %d !\n", index); + } + + //将一个数据写入entry + rc = dpp_dtb_se_smmu0_ind_write(dev, + base_addr, + index, + wrt_mode, + p_entry_data, + &dtb_one_entry); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_se_smmu0_ind_write", table_data_buff); + + switch (wrt_mode) + { + case ERAM128_OPR_128b: + { + dtb_len += 2; + addr_offset = item_cnt * DTB_LEN_POS_SETP * 2; + break; + } + + case ERAM128_OPR_64b: + { + dtb_len += 1; + addr_offset = item_cnt * DTB_LEN_POS_SETP; + break; + } + + case ERAM128_OPR_1b: + { + dtb_len += 1; + addr_offset = item_cnt * DTB_LEN_POS_SETP; + break; + } + } + + /*将表格式和数据写入缓存buff中*/ + rc = dpp_dtb_data_write(table_data_buff, addr_offset, &dtb_one_entry); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_data_write", table_data_buff); + ZXIC_COMM_MEMSET(cmd_buff, 0, DTB_TABLE_CMD_SIZE_BIT / 8); + ZXIC_COMM_MEMSET(entry_data_buff, 0, 4 * sizeof(ZXIC_UINT32)); + } + + if(dpp_dtb_prt_get()) + { + dpp_data_buff_print(table_data_buff, dtb_len * 16); + ZXIC_COMM_PRINT("start down table to dtb : queue_id: %d, down_data_len: %d\n", queue_id, dtb_len * 16); + } + + rc = dpp_dtb_write_down_table_data(dev, + queue_id, + dtb_len * 16, + table_data_buff, + element_id + ); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_write_down_table_data", table_data_buff); + + ZXIC_COMM_FREE(table_data_buff); + + return DPP_OK; +} + + +/** dtb写ddr中的数据，数据长度在16K范围内 +* @param dev_id 设备号 +* @param queue_id 队列号 +* @param ddr_base_addr ddr基地址，以4K*128bit为单位 +* @param ddr_wr_mode ddr写模式 0-128bit, 1-256bit, 2-384bit, 3-512bit,取值参考SMMU1_DDR_WRT_MODE_E的定义 +* @param ddr_ecc_en ddr ECC使能 +* @param entry_num 下发的条目数 +* @param p_entry_arr 待下发表项内容结构体数组指针 +* @param element_id 返回下表使用的元素id +* @return +* @remark 无 +* @see +* @author cbb @date 2022/08/30 +************************************************************/ +DPP_STATUS dpp_dtb_smmu1_data_write_cycle(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 ddr_base_addr, + ZXIC_UINT32 ddr_wr_mode, + ZXIC_UINT32 ddr_ecc_en, + ZXIC_UINT32 entry_num, + DPP_DTB_DDR_ENTRY_INFO_T *p_entry_arr, + ZXIC_UINT32 *element_id) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_UINT32 index; + ZXIC_UINT32 item_cnt = 0; + ZXIC_UINT32 addr_offset = 0; + ZXIC_UINT32 *p_entry_data = NULL; + ZXIC_UINT32 dtb_len = 0; + ZXIC_UINT8 *table_data_buff = NULL; + ZXIC_UINT8 cmd_buff[DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; /*命令格式缓存*/ + ZXIC_UINT32 entry_data_buff[DPP_DIR_TBL_BUF_MAX_NUM] = {0}; + + DPP_DTB_ENTRY_T dtb_one_entry = {0}; /*条目结构*/ + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DTB_QUEUE_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX_LOWER(DEV_ID(dev), entry_num, 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_entry_arr); + + //分配下表数据缓存 16K + table_data_buff = (ZXIC_UINT8 *) ZXIC_COMM_MALLOC(DPP_DTB_TABLE_DATA_BUFF_SIZE * sizeof(ZXIC_UINT8)); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), table_data_buff); + ZXIC_COMM_MEMSET(table_data_buff, 0, DPP_DTB_TABLE_DATA_BUFF_SIZE * sizeof(ZXIC_UINT8)); + + dtb_one_entry.cmd = cmd_buff; + dtb_one_entry.data = (ZXIC_UINT8 *)entry_data_buff; + + /*对每一个条目进行处理*/ + for(item_cnt = 0; item_cnt < entry_num; ++item_cnt) + { + p_entry_data = (ZXIC_UINT32 *)p_entry_arr[item_cnt].p_data; + ZXIC_COMM_CHECK_POINT_MEMORY_FREE_NO_ASSERT(p_entry_data, table_data_buff); + + index = p_entry_arr[item_cnt].index; + + //将一个数据写入entry + rc = dpp_dtb_ddr_dir_table_data_write(DEV_ID(dev), + ddr_base_addr, + ddr_wr_mode, + index, + ddr_ecc_en, + (ZXIC_UINT8 *)p_entry_data, + &dtb_one_entry); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_ddr_dir_table_data_write", table_data_buff); + + dtb_len += (ddr_wr_mode + 2); + addr_offset = item_cnt * (ddr_wr_mode + 2) * DTB_LEN_POS_SETP; + + /*数据写入缓存中*/ + rc = dpp_dtb_data_write(table_data_buff, addr_offset, &dtb_one_entry); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_data_write", table_data_buff); + ZXIC_COMM_MEMSET(cmd_buff, 0, DTB_TABLE_CMD_SIZE_BIT / 8); + ZXIC_COMM_MEMSET(entry_data_buff, 0, DPP_DIR_TBL_BUF_MAX_NUM * sizeof(ZXIC_UINT32)); + } + + if(dpp_dtb_prt_get()) + { + dpp_data_buff_print(table_data_buff, dtb_len * 16); + ZXIC_COMM_PRINT("start down table to dtb : queue_id: %d, down_data_len: %d\n", queue_id, dtb_len * 16); + } + + rc = dpp_dtb_write_down_table_data(dev, + queue_id, + dtb_len * 16, + table_data_buff, + element_id + ); + ZXIC_COMM_FREE(table_data_buff); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_write_down_table_data"); + + return DPP_OK; +} + +/** dtb写HASH表,在插入条目时如果冲突，则对冲突条目进行记录 +* @param dev_id 设备号 +* @param queue_id 队列号 +* @param sdt_no hash表sdt表号 +* @param entry_cnt 下发的条目数 +* @param p_entry_arr 待下发表项内容结构体数组指针 +* @param element_id 返回下表使用的元素id +* @return +* @remark 无 是否是有一个写不成功就返回，还是继续进行下一个条目并记录错误的条目 +* @see +* @author cbb @date 2022/08/30 +************************************************************/ +DPP_STATUS dpp_dtb_hash_dma_insert_cycle(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 sdt_no, + ZXIC_UINT32 entry_num, + DPP_DTB_HASH_ENTRY_INFO_T *p_arr_hash_entry, + ZXIC_UINT32 *element_id) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT8 temp_key[HASH_KEY_MAX] = {0}; + ZXIC_UINT8 end_flag = 0; + ZXIC_UINT32 ddr_wr_mode = 0; + ZXIC_UINT32 item_cnt = 0; + ZXIC_UINT8 key_valid = 1; + ZXIC_UINT32 dtb_len = 0; + ZXIC_UINT8 key[HASH_KEY_MAX] = {0}; + ZXIC_UINT8 rst[HASH_RST_MAX] = {0}; + + DPP_SE_CFG *p_se_cfg = NULL; + ZXIC_RB_TN *p_rb_tn_new = NULL; + ZXIC_RB_TN *p_rb_tn_rtn = NULL; + DPP_HASH_CFG *p_hash_cfg = NULL; + DPP_HASH_RBKEY_INFO *p_rbkey_new = NULL; + FUNC_ID_INFO *p_func_info = NULL; + HASH_ENTRY_CFG hash_entry_cfg = {0}; + DPP_SDTTBL_HASH_T sdt_hash_info = {0}; /*SDT内容*/ + DPP_HASH_ENTRY entry = {0}; /* hash条目结构体*/ + ZXIC_UINT8 *p_data_buff = NULL; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DTB_QUEUE_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX_LOWER(DEV_ID(dev), entry_num, 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_arr_hash_entry); + + //从sdt_no中获取SDT配置 + rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_hash_info); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_soft_sdt_tbl_read"); + + hash_entry_cfg.fun_id = sdt_hash_info.hash_id; /*hash引擎*/ + ZXIC_COMM_CHECK_INDEX(hash_entry_cfg.fun_id, HASH_FUNC_ID_MIN, HASH_FUNC_ID_NUM - 1); + hash_entry_cfg.table_id = sdt_hash_info.hash_table_id; /*hash表号*/ + ZXIC_COMM_CHECK_INDEX_UPPER(hash_entry_cfg.table_id,HASH_TBL_ID_NUM - 1); + hash_entry_cfg.bulk_id = ((hash_entry_cfg.table_id >> 2) & 0x7); + ZXIC_COMM_CHECK_INDEX_UPPER(hash_entry_cfg.bulk_id,HASH_BULK_NUM - 1); + hash_entry_cfg.key_type = sdt_hash_info.hash_table_width; /*表宽度*/ + ZXIC_COMM_CHECK_INDEX(hash_entry_cfg.key_type, HASH_KEY_128b, HASH_KEY_512b); + hash_entry_cfg.actu_key_size = sdt_hash_info.key_size; /*业务表键值长度*/ + ZXIC_COMM_CHECK_INDEX(hash_entry_cfg.actu_key_size, HASH_ACTU_KEY_MIN, HASH_ACTU_KEY_MAX); + hash_entry_cfg.key_by_size = DPP_GET_KEY_SIZE(hash_entry_cfg.actu_key_size); + hash_entry_cfg.rst_by_size = DPP_GET_RST_SIZE(hash_entry_cfg.key_type, hash_entry_cfg.actu_key_size); + + /* 取出se配置 */ + rc = dpp_se_cfg_get(DEV_ID(dev), &p_se_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_se_cfg_get"); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_se_cfg); + p_func_info = DPP_GET_FUN_INFO(p_se_cfg, hash_entry_cfg.fun_id); + DPP_SE_CHECK_FUN(p_func_info, hash_entry_cfg.fun_id, FUN_HASH); + hash_entry_cfg.p_hash_cfg = (DPP_HASH_CFG *)p_func_info->fun_ptr; + + /*条目数上限检查*/ + ddr_wr_mode = DPP_GET_DDR_WR_MODE(hash_entry_cfg.key_type); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), entry_num, 1, DTB_DATA_SIZE_BIT / ( (ddr_wr_mode + 2) * DTB_TABLE_CMD_SIZE_BIT)); + + entry.p_key = key; + entry.p_rst = rst; + entry.p_key[0] = (ZXIC_UINT8)(((key_valid & 0x1) << 7) | ((hash_entry_cfg.key_type & 0x3) << 5) | (hash_entry_cfg.table_id & 0x1f)); + + p_data_buff = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(DPP_DTB_TABLE_DATA_BUFF_SIZE); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data_buff); + ZXIC_COMM_MEMSET(p_data_buff,0x0,DPP_DTB_TABLE_DATA_BUFF_SIZE); + + /*对每一个条目进行处理*/ + for(item_cnt = 0; item_cnt < entry_num; ++item_cnt) + { + end_flag = 0; + /*组装数据*/ + ZXIC_COMM_MEMCPY(&entry.p_key[1], p_arr_hash_entry[item_cnt].p_actu_key, hash_entry_cfg.actu_key_size); + ZXIC_COMM_MEMCPY(&entry.p_rst[0], p_arr_hash_entry[item_cnt].p_rst, ((hash_entry_cfg.rst_by_size > HASH_RST_MAX) ? HASH_RST_MAX : hash_entry_cfg.rst_by_size)); + + rc = dpp_hash_red_black_node_alloc(dev,&p_rb_tn_new,&p_rbkey_new); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc,"dpp_hash_red_black_node_alloc",p_data_buff); + ZXIC_COMM_MEMCPY(p_rbkey_new->key, entry.p_key, hash_entry_cfg.key_by_size); + hash_entry_cfg.p_rbkey_new = p_rbkey_new; + hash_entry_cfg.p_rb_tn_new = p_rb_tn_new; + + rc = dpp_hash_rb_insert(dev,&hash_entry_cfg,&entry); + if(DPP_OK != rc) + { + if(DPP_HASH_RC_ADD_UPDATE == rc) + { + /*将位置信息和数据信息写入buff中*/ + rc = dpp_dtb_add_hash_buf_write(DEV_ID(dev),&hash_entry_cfg,p_data_buff,item_cnt,&dtb_len); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_hash_form_write",p_data_buff); + } + continue; + } + + /*insert new hash item*/ + /*1 first form the new key(calc crc)*/ + rc = dpp_hash_set_crc_key(dev,&hash_entry_cfg,&entry,temp_key); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc,"hash_set_crc_key",p_data_buff); + + /*2 if DDR is valid, first insert into DDR.*/ + p_hash_cfg = hash_entry_cfg.p_hash_cfg; + if (p_hash_cfg->ddr_valid) + { + rc = dpp_hash_insert_ddr(dev,&hash_entry_cfg,temp_key,&end_flag); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc,"hash_insert_ddr",p_data_buff); + } + + /*3 if insert into DDR is fail, insert into ZCAM. */ + if (!end_flag) + { + rc = dpp_hash_insert_zcell(dev,p_se_cfg,&hash_entry_cfg,temp_key,&end_flag); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc,"hash_insert_zcell",p_data_buff); + } + + /*4 if insert into ZCAM is fail, insert into ZBLK Reg. */ + if (!end_flag) + { + rc = dpp_hash_insert_zreg(dev,&hash_entry_cfg,temp_key,&end_flag); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc,"hash_insert_zreg",p_data_buff); + } + + if (!end_flag) + { + p_hash_cfg->hash_stat.insert_fail++; + /* recycle rb tree node */ + ZXIC_COMM_MEMCPY(temp_key, entry.p_key, hash_entry_cfg.key_by_size); + rc = zxic_comm_rb_delete(&p_hash_cfg->hash_rb, p_rbkey_new, &p_rb_tn_rtn); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "zxic_comm_rb_delete",p_data_buff); + ZXIC_COMM_ASSERT(p_rb_tn_new == p_rb_tn_rtn); + ZXIC_COMM_FREE(p_rbkey_new); + ZXIC_COMM_FREE(p_rb_tn_rtn); + ZXIC_COMM_FREE(p_data_buff); + dpp_dtb_data_print(temp_key, hash_entry_cfg.key_by_size); + ZXIC_COMM_TRACE_ERROR("DPP_HASH_RC_TBL_FULL.\n"); + return DPP_RC_DTB_DOWN_HASH_CONFLICT; + } + + /*将位置信息和数据信息写入buff中*/ + rc = dpp_dtb_add_hash_buf_write(DEV_ID(dev),&hash_entry_cfg,p_data_buff,item_cnt,&dtb_len); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_hash_form_write",p_data_buff); + + p_hash_cfg->hash_stat.insert_ok++; + } + + if(dpp_dtb_prt_get()) + { + dpp_data_buff_print(p_data_buff, dtb_len * 16); + } + + rc = dpp_dtb_write_down_table_data(dev, + queue_id, + dtb_len * 16, + p_data_buff, + element_id); + ZXIC_COMM_FREE(p_data_buff); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_write_down_table_data"); + + return DPP_OK; +} + + +/** dtb写ACL表 （SPECIFY模式，条目中指定handle，支持级联64bit/128bit） +* @param dev_id 设备号 +* @param queue_id 队列号 +* @param sdt_no ACL表sdt表号 +* @param entry_cnt 下发的条目数 +* @param p_entry_arr 待下发表项内容结构体数组指针 +* @param element_id 返回下表使用的元素id +* @return +* @remark 无 是否是有一个写不成功就返回，还是继续进行下一个条目并记录错误的条目 +* @see +* @author cbb @date 2022/08/30 +************************************************************/ +DPP_STATUS dpp_dtb_acl_dma_insert_cycle(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 sdt_no, + ZXIC_UINT32 entry_num, + DPP_DTB_ACL_ENTRY_INFO_T *p_acl_entry_arr, + ZXIC_UINT32 *element_id + ) +{ + /* + 1、条目的handle值是指定的； + 2、根据级联配置在etcam中保存级联结果值 + */ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 etcam_key_mode; + ZXIC_UINT32 as_eram_baddr; + ZXIC_UINT32 as_enable; + ZXIC_UINT32 etcam_table_id; + ZXIC_UINT32 etcam_as_mode; + ZXIC_UINT32 block_idx = 0; + ZXIC_UINT32 ram_addr = 0; + ZXIC_UINT32 etcam_wr_mode = 0; + ZXIC_UINT32 eram_wrt_mode = 0; + ZXIC_UINT32 eram_index; + + ZXIC_UINT32 item_cnt = 0; + ZXIC_UINT32 addr_offset_bk = 0; + ZXIC_UINT32 dtb_len = 0; + ZXIC_UINT32 as_addr_offset = 0; + ZXIC_UINT32 as_dtb_len = 0; + + DPP_ACL_CFG_EX_T *p_acl_cfg = NULL; + DPP_ACL_TBL_CFG_T *p_tbl_cfg = NULL; + DPP_DTB_ACL_ENTRY_INFO_T *p_acl_entry = NULL; + ZXIC_UINT32 *p_as_eram_data = NULL; + ZXIC_UINT8 *table_data_buff = NULL; + DPP_ETCAM_ENTRY_T etcam_entry = {0}; + + ZXIC_UINT8 entry_data_buff[DPP_ETCAM_WIDTH_MAX / 8] = {0}; + ZXIC_UINT8 entry_mask_buff[DPP_ETCAM_WIDTH_MAX / 8] = {0}; + ZXIC_UINT32 as_eram_data_buff[4] = {0}; + ZXIC_UINT8 entry_data_cmd_buff[DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; + ZXIC_UINT8 entry_mask_cmd_buff[DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; + ZXIC_UINT8 as_eram_cmd_buff[DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; + + DPP_SDTTBL_ETCAM_T sdt_etcam_info = {0}; + DPP_DTB_ENTRY_T entry_data = {0}; + DPP_DTB_ENTRY_T entry_mask = {0}; + DPP_DTB_ENTRY_T dtb_as_data_entry = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DTB_QUEUE_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX_LOWER(DEV_ID(dev), entry_num, 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_acl_entry_arr); + + entry_data.cmd = entry_data_cmd_buff; + entry_data.data = (ZXIC_UINT8 *)entry_data_buff; + + entry_mask.cmd = entry_mask_cmd_buff; + entry_mask.data = (ZXIC_UINT8 *)entry_mask_buff; + + dtb_as_data_entry.cmd = as_eram_cmd_buff; + dtb_as_data_entry.data = (ZXIC_UINT8 *)as_eram_data_buff; + + //分配下表数据缓存 16K + table_data_buff = (ZXIC_UINT8 *) ZXIC_COMM_MALLOC(DPP_DTB_TABLE_DATA_BUFF_SIZE * sizeof(ZXIC_UINT8)); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), table_data_buff); + ZXIC_COMM_MEMSET(table_data_buff, 0, DPP_DTB_TABLE_DATA_BUFF_SIZE * sizeof(ZXIC_UINT8)); + + //从sdt_no中获取SDT配置 + rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_etcam_info); + ZXIC_COMM_CHECK_DEV_RC_MEMORY_FREE(DEV_ID(dev), rc, "dpp_soft_sdt_tbl_get", table_data_buff); + etcam_key_mode = sdt_etcam_info.etcam_key_mode; + ZXIC_COMM_CHECK_INDEX_MEMORY_FREE_NO_ASSERT(etcam_key_mode, DPP_ACL_KEY_640b, DPP_ACL_KEY_80b, table_data_buff); + etcam_as_mode = sdt_etcam_info.as_rsp_mode; + ZXIC_COMM_CHECK_INDEX_MEMORY_FREE_NO_ASSERT(etcam_as_mode, DPP_ACL_AS_MODE_64b, DPP_ACL_AS_MODE_INVALID - 1, table_data_buff); + etcam_table_id = sdt_etcam_info.etcam_table_id; + ZXIC_COMM_CHECK_INDEX_MEMORY_FREE_NO_ASSERT(etcam_table_id, DPP_ACL_TBL_ID_MIN, DPP_ACL_TBL_ID_MAX, table_data_buff); + as_enable = sdt_etcam_info.as_en; + as_eram_baddr = sdt_etcam_info.as_eram_baddr; + + //级联数据下发 + if(as_enable) + { + //mode转换 + switch (etcam_as_mode) + { + case ERAM128_TBL_128b: + { + eram_wrt_mode = ERAM128_OPR_128b; + break; + } + + case ERAM128_TBL_64b: + { + eram_wrt_mode = ERAM128_OPR_64b; + break; + } + + case ERAM128_TBL_1b: + { + eram_wrt_mode = ERAM128_OPR_1b; + break; + } + } + } + + dpp_acl_cfg_get(&p_acl_cfg);//获取ACL表资源配置 + ZXIC_COMM_CHECK_POINT_MEMORY_FREE(p_acl_cfg, table_data_buff); + + p_tbl_cfg = p_acl_cfg->acl_tbls + etcam_table_id;//得到该acl表的资源配置 + + if (!p_tbl_cfg->is_used) + { + ZXIC_COMM_TRACE_ERROR("table[ %d ] is not init!\n", etcam_table_id); + ZXIC_COMM_FREE(table_data_buff); + ZXIC_COMM_ASSERT(0); + return DPP_ACL_RC_TBL_NOT_INIT; + } + + /*对每一个条目进行处理*/ + for(item_cnt = 0; item_cnt < entry_num; ++item_cnt) + { + p_acl_entry = p_acl_entry_arr + item_cnt; + + /* write etcam key */ + etcam_entry.mode = p_tbl_cfg->key_mode; + etcam_entry.p_data = p_acl_entry->key_data; + etcam_entry.p_mask = p_acl_entry->key_mask; + + /*计算地址等信息*/ + rc = dpp_acl_hdw_addr_get(p_tbl_cfg, p_acl_entry->handle, &block_idx, &ram_addr, &etcam_wr_mode); + ZXIC_COMM_CHECK_RC_MEMORY_FREE(rc, "dpp_acl_hdw_addr_get", table_data_buff); + + rc = dpp_dtb_etcam_entry_add(dev, + ram_addr, + block_idx, + etcam_wr_mode, + DPP_ETCAM_OPR_DM, + &etcam_entry, + &entry_data, + &entry_mask + ); + + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_etcam_entry_add", table_data_buff); + + /*data数据写入缓存*/ + dtb_len += DTB_ETCAM_LEN_SIZE; + dpp_dtb_data_write(table_data_buff, addr_offset_bk, &entry_data); /*将数据写入缓存中*/ + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_data_write", table_data_buff); + ZXIC_COMM_MEMSET(entry_data_cmd_buff, 0, DTB_TABLE_CMD_SIZE_BIT / 8); + ZXIC_COMM_MEMSET(entry_data_buff, 0, DPP_ETCAM_WIDTH_MAX / 8); + addr_offset_bk = addr_offset_bk + DTB_ETCAM_LEN_SIZE * DTB_LEN_POS_SETP; /*在缓存中相对于0的offset*/ + + /*mask数据写入缓存*/ + dtb_len += DTB_ETCAM_LEN_SIZE; + rc = dpp_dtb_data_write(table_data_buff, addr_offset_bk, &entry_mask); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_data_write", table_data_buff); + ZXIC_COMM_MEMSET(entry_mask_cmd_buff, 0, DTB_TABLE_CMD_SIZE_BIT / 8); + ZXIC_COMM_MEMSET(entry_mask_buff, 0, 640/8); + addr_offset_bk = addr_offset_bk + DTB_ETCAM_LEN_SIZE * DTB_LEN_POS_SETP; /*在缓存中相对于0的offset*/ + + //处理级联数据 + if(as_enable) + { + p_as_eram_data = (ZXIC_UINT32 *)(p_acl_entry->p_as_rslt); + ZXIC_COMM_CHECK_DEV_POINT_MEMORY_FREE_NO_ASSERT(DEV_ID(dev), p_as_eram_data, table_data_buff); + eram_index = p_acl_entry->handle; + rc = dpp_dtb_se_smmu0_ind_write(dev, + as_eram_baddr, + eram_index, + eram_wrt_mode, + p_as_eram_data, + &dtb_as_data_entry); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_se_smmu0_ind_write", table_data_buff); + + switch (eram_wrt_mode) + { + case ERAM128_OPR_128b: + { + as_dtb_len = 2; + as_addr_offset = DTB_LEN_POS_SETP * 2; + break; + } + + case ERAM128_OPR_64b: + { + as_dtb_len = 1; + as_addr_offset = DTB_LEN_POS_SETP; + break; + } + + case ERAM128_OPR_1b: + { + as_dtb_len = 1; + as_addr_offset = DTB_LEN_POS_SETP; + break; + } + } + + /*将表格式和数据写入缓存buff中*/ + rc = dpp_dtb_data_write(table_data_buff, addr_offset_bk, &dtb_as_data_entry); + addr_offset_bk = addr_offset_bk + as_addr_offset; /*在缓存中相对于0的offset*/ + dtb_len += as_dtb_len; + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_data_write", table_data_buff); + ZXIC_COMM_MEMSET(as_eram_cmd_buff, 0, DTB_TABLE_CMD_SIZE_BIT / 8); + ZXIC_COMM_MEMSET(as_eram_data_buff, 0, 4 * sizeof(ZXIC_UINT32)); + } + } + + if(dpp_dtb_prt_get()) + { + dpp_data_buff_print(table_data_buff, dtb_len * 16); + } + + rc = dpp_dtb_write_down_table_data(dev, + queue_id, + dtb_len * 16, + table_data_buff, + element_id + ); + ZXIC_COMM_FREE(table_data_buff); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_write_down_table_data"); + + return DPP_OK; +} + +#endif /*DTB BASE INTERFACE*/ + +#if ZXIC_REAL("DTB_DOWN_INTERFACE") +/** dtb写eRam表--支持大数据量 +* @param dev_id 设备号 +* @param queue_id 队列号 +* @param sdt_no eram表sdt表号 +* @param entry_cnt 下发的条目数 +* @param p_entry_arr 待下发表项内容结构体数组指针 +* @param element_id 返回下表使用的元素id +* @return +* @remark 无 +* @see +* @author cbb @date 2022/08/30 +************************************************************/ +DPP_STATUS dpp_dtb_eram_dma_write(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 sdt_no, + ZXIC_UINT32 entry_num, + DPP_DTB_ERAM_ENTRY_INFO_T *p_entry_arr, + ZXIC_UINT32 *element_id + ) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 wrt_mode; + ZXIC_UINT32 entry_num_max = 0; + ZXIC_UINT32 entry_cycle = 0; + ZXIC_UINT32 entry_remains = 0; + ZXIC_UINT32 i = 0; + DPP_DTB_ERAM_ENTRY_INFO_T *p_entry = NULL; + + DPP_SDTTBL_ERAM_T sdt_eram_info = {0}; + + ZXIC_COMM_CHECK_POINT_NO_ASSERT(dev); + + rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_eram_info); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_soft_sdt_tbl_get"); + + wrt_mode = sdt_eram_info.eram_mode;//3:128 + + switch (wrt_mode) + { + case ERAM128_TBL_128b: + { + entry_num_max = 0x1ff; + break; + } + + case ERAM128_TBL_64b: + { + entry_num_max = 0x3ff; + break; + } + + case ERAM128_TBL_1b: + { + entry_num_max = 0x3ff; + break; + } + } + + ZXIC_COMM_CHECK_INDEX_EQUAL(entry_num_max, 0); + entry_cycle = entry_num / entry_num_max; + entry_remains = entry_num % entry_num_max; + + for(i = 0; i < entry_cycle; ++i) + { + p_entry = p_entry_arr + entry_num_max * i; + rc = dpp_dtb_eram_dma_write_cycle(dev, + queue_id, + sdt_no, + entry_num_max, + p_entry, + element_id); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_eram_dma_write_cycle"); + + ZXIC_COMM_TRACE_INFO("dpp_dtb_eram_dma_write_cycle: slot [%d] queue [%d] element_id [%d] done.\n",DEV_PCIE_SLOT(dev), queue_id, *element_id); + } + + if(entry_remains) + { + p_entry = p_entry_arr + entry_num_max * entry_cycle; + rc = dpp_dtb_eram_dma_write_cycle(dev, + queue_id, + sdt_no, + entry_remains, + p_entry, + element_id); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_eram_dma_write_cycle"); + + ZXIC_COMM_TRACE_INFO("dpp_dtb_eram_dma_write_cycle: slot [%d] queue [%d] element_id [%d] done.\n",DEV_PCIE_SLOT(dev), queue_id, *element_id); + + } + + return DPP_OK; +} + +DPP_STATUS dpp_dtb_hash_dma_insert(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 sdt_no, + ZXIC_UINT32 entry_num, + DPP_DTB_HASH_ENTRY_INFO_T *p_arr_hash_entry, + ZXIC_UINT32 *element_id) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 entry_num_max = 0; + ZXIC_UINT32 entry_cycle = 0; + ZXIC_UINT32 entry_remains = 0; + ZXIC_UINT32 i = 0; + DPP_DTB_HASH_ENTRY_INFO_T *p_entry = NULL; + + ZXIC_COMM_CHECK_POINT_NO_ASSERT(dev); + + entry_num_max = 0xcc;//按512bit数据进行计算 + + entry_cycle = entry_num / entry_num_max; + entry_remains = entry_num % entry_num_max; + + for(i = 0; i < entry_cycle; ++i) + { + p_entry = p_arr_hash_entry + entry_num_max * i; + rc = dpp_dtb_hash_dma_insert_cycle(dev, + queue_id, + sdt_no, + entry_num_max, + p_entry, + element_id); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_hash_dma_insert_cycle"); + ZXIC_COMM_TRACE_INFO("dpp_dtb_hash_dma_insert_cycle: slot [%d] queue [%d] element_id [%d] done.\n",DEV_PCIE_SLOT(dev), queue_id, *element_id); + } + + if(entry_remains) + { + p_entry = p_arr_hash_entry + entry_num_max * entry_cycle; + rc = dpp_dtb_hash_dma_insert_cycle(dev, + queue_id, + sdt_no, + entry_remains, + p_entry, + element_id); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_hash_dma_insert_cycle"); + ZXIC_COMM_TRACE_INFO("dpp_dtb_hash_dma_insert_cycle: slot [%d] queue [%d] element_id [%d] done.\n",DEV_PCIE_SLOT(dev), queue_id, *element_id); + } + + return DPP_OK; +} + +/** dtb删除HASH表 +* @param dev_id 设备号 +* @param queue_id 队列号 +* @param sdt_no hash表sdt表号 +* @param entry_cnt 删除的条目数 +* @param p_entry_arr 待下发表项内容结构体数组指针 +* @param element_id 返回下表使用的元素id +* @return +* @remark 无 +* @see +* @author @date 2023/03/14 +************************************************************/ +DPP_STATUS dpp_dtb_hash_dma_delete(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 sdt_no, + ZXIC_UINT32 entry_num, + DPP_DTB_HASH_ENTRY_INFO_T *p_arr_hash_entry, + ZXIC_UINT32 *element_id) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_UINT8 key_valid = 1; + ZXIC_UINT32 item_cnt = 0; + ZXIC_UINT32 ddr_wr_mode = 0; + ZXIC_UINT32 dtb_len = 0; + + SE_ITEM_CFG *p_item = NULL; + ZXIC_RB_TN *p_rb_tn_rtn = NULL; + DPP_HASH_CFG *p_hash_cfg = NULL; + DPP_HASH_RBKEY_INFO *p_rbkey_rtn = NULL; + DPP_HASH_RBKEY_INFO temp_rbkey = {{0}}; + ZXIC_UINT8 *p_data_buff = NULL; + + HASH_ENTRY_CFG hash_entry_cfg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DTB_QUEUE_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX_LOWER(DEV_ID(dev), entry_num, 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_arr_hash_entry); + + //从sdt_no中获取hash配置 + rc = dpp_hash_get_hash_info_from_sdt(DEV_ID(dev), sdt_no, &hash_entry_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_hash_get_hash_info_from_sdt"); + + p_hash_cfg = hash_entry_cfg.p_hash_cfg; + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_hash_cfg); + + /*条目数上限检查*/ + ddr_wr_mode = DPP_GET_DDR_WR_MODE(hash_entry_cfg.key_type); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), entry_num, 1, DTB_DATA_SIZE_BIT / ( (ddr_wr_mode + 2) * DTB_TABLE_CMD_SIZE_BIT)); + + p_data_buff = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(DPP_DTB_TABLE_DATA_BUFF_SIZE); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data_buff); + ZXIC_COMM_MEMSET(p_data_buff,0x0,DPP_DTB_TABLE_DATA_BUFF_SIZE); + + /*对每一个条目进行处理*/ + for(item_cnt = 0; item_cnt < entry_num; ++item_cnt) + { + ZXIC_COMM_MEMSET(&temp_rbkey,0x0,sizeof(DPP_HASH_RBKEY_INFO)); + temp_rbkey.key[0] = (ZXIC_UINT8)(((key_valid & 0x1) << 7) | ((hash_entry_cfg.key_type & 0x3) << 5) | (hash_entry_cfg.table_id & 0x1f)); + ZXIC_COMM_MEMCPY(&temp_rbkey.key[1], p_arr_hash_entry[item_cnt].p_actu_key, hash_entry_cfg.actu_key_size); + rc = zxic_comm_rb_delete(&p_hash_cfg->hash_rb, &temp_rbkey, &p_rb_tn_rtn); + if (ZXIC_RBT_RC_SRHFAIL == rc) + { + p_hash_cfg->hash_stat.delete_fail++; + ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev), "Error!there is not item in hash!\n"); + continue; + } + + ZXIC_COMM_CHECK_POINT_MEMORY_FREE_NO_ASSERT(p_rb_tn_rtn,p_data_buff); + + p_rbkey_rtn = (DPP_HASH_RBKEY_INFO *)(p_rb_tn_rtn->p_key); + ZXIC_COMM_MEMSET(p_rbkey_rtn->rst,0x0,sizeof(p_rbkey_rtn->rst)); + hash_entry_cfg.p_rbkey_new = p_rbkey_rtn; + hash_entry_cfg.p_rb_tn_new = p_rb_tn_rtn; + + p_item = p_rbkey_rtn->p_item_info; + rc = zxic_comm_double_link_del(&(p_rbkey_rtn->entry_dn), &(p_item->item_list)); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "zxic_comm_double_link_del",p_data_buff); + p_item->wrt_mask &= ~(DPP_GET_HASH_ENTRY_MASK(p_rbkey_rtn->entry_size, p_rbkey_rtn->entry_pos)) & 0xF; + + /*将位置信息和数据信息写入buff中*/ + rc = dpp_dtb_delete_hash_buf_write(DEV_ID(dev),&hash_entry_cfg,p_data_buff,item_cnt,&dtb_len); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_hash_form_write",p_data_buff); + + if (0 == p_item->item_list.used) + { + if ((ITEM_DDR_256 == p_item->item_type) || (ITEM_DDR_512 == p_item->item_type)) + { + /* modify coverity by yinxh 2021.03.10*,以256bit为单位。暂不考虑512bit的情况*/ + ZXIC_COMM_CHECK_INDEX_UPPER_MEMORY_FREE( + p_item->item_index, + p_hash_cfg->p_bulk_ddr_info[hash_entry_cfg.bulk_id]->item_num, + p_data_buff); + p_hash_cfg->p_bulk_ddr_info[hash_entry_cfg.bulk_id]->p_item_array[p_item->item_index] = NULL; + ZXIC_COMM_FREE(p_item); + } + else + { + p_item->valid = 0; + } + } + + ZXIC_COMM_FREE(p_rbkey_rtn); + ZXIC_COMM_FREE(p_rb_tn_rtn); + + p_hash_cfg->hash_stat.delete_ok++; + } + + if(dtb_len) + { + rc = dpp_dtb_write_down_table_data(dev, + queue_id, + dtb_len * 16, + p_data_buff, + element_id); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_write_down_table_data",p_data_buff); + } + ZXIC_COMM_FREE(p_data_buff); + + return DPP_OK; +} + +/** dtb删除所有的HASH表(硬件查找，硬件删除) +* @param dev_id 设备号 +* @param queue_id 队列号 +* @param sdt_no hash表sdt表号 +* @param entry_cnt 删除的条目数 +* @param p_entry_arr 待下发表项内容结构体数组指针 +* @param element_id 返回下表使用的元素id +* @return +* @remark 无 +* @see +* @author cq @date 2023/12/02 +************************************************************/ +DPP_STATUS dpp_dtb_hash_dma_delete_hardware(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 sdt_no, + ZXIC_UINT32 entry_num, + DPP_DTB_HASH_ENTRY_INFO_T *p_arr_hash_entry, + ZXIC_UINT32 *element_id) +{ + DPP_STATUS rc = DPP_OK; + //ZXIC_UINT32 ddr_wr_mode = 0; + ZXIC_UINT32 item_cnt = 0; + ZXIC_UINT32 dtb_len = 0; + ZXIC_UINT8 srh_succ = 0; + ZXIC_UINT8 key[HASH_KEY_MAX] = {0}; + ZXIC_UINT8 rst[HASH_RST_MAX] = {0}; + ZXIC_UINT8 entry_cmd[DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; + ZXIC_UINT8 entry_data[DPP_ETCAM_WIDTH_MAX/8] = {0}; /*兼容所有表项，按照最大位宽分配，acl最大为640bit(80B)*/ + ZXIC_UINT8 *p_data_buff = NULL; + ZXIC_UINT32 dev_id = 0; + + DPP_HASH_ENTRY entry = {0}; + DPP_HASH_CFG *p_hash_cfg = NULL; + DPP_DTB_ENTRY_T dtb_one_entry = {0}; + HASH_ENTRY_CFG hash_entry_cfg = {0}; + + ZXIC_COMM_CHECK_POINT_NO_ASSERT(dev); + dev_id = DEV_ID(dev); + + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, queue_id, 0, DTB_QUEUE_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_arr_hash_entry); + + dtb_one_entry.cmd = entry_cmd; + dtb_one_entry.data = entry_data; + entry.p_key = key; + entry.p_rst = rst; + + //从sdt_no中获取hash配置 + rc = dpp_hash_get_hash_info_from_sdt(dev_id, sdt_no, &hash_entry_cfg); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_hash_get_hash_info_from_sdt"); + + p_hash_cfg = hash_entry_cfg.p_hash_cfg; + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_hash_cfg); + + /*条目数上限检查*/ + //ddr_wr_mode = DPP_GET_DDR_WR_MODE(hash_entry_cfg.key_type); + //ZXIC_COMM_CHECK_DEV_INDEX(dev_id, entry_num, 1, DTB_DATA_SIZE_BIT / ( (ddr_wr_mode + 2) * DTB_TABLE_CMD_SIZE_BIT)); + + p_data_buff = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(DPP_DTB_TABLE_DATA_BUFF_SIZE); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_data_buff); + ZXIC_COMM_MEMSET(p_data_buff,0x0,DPP_DTB_TABLE_DATA_BUFF_SIZE); + + /*对每一个条目进行处理*/ + for(item_cnt = 0; item_cnt < entry_num; ++item_cnt) + { + srh_succ = 0; + ZXIC_COMM_MEMSET(key,0x0,sizeof(key)); + ZXIC_COMM_MEMSET(rst,0x0,sizeof(rst)); + ZXIC_COMM_MEMSET(entry_cmd,0x0,sizeof(entry_cmd)); + ZXIC_COMM_MEMSET(entry_data,0x0,sizeof(entry_data)); + ZXIC_COMM_MEMCPY(entry.p_key, p_arr_hash_entry[item_cnt].p_actu_key, hash_entry_cfg.key_by_size); + + rc = dpp_dtb_hash_zcam_delete_hardware(dev, + queue_id, + &hash_entry_cfg, + &entry, + &dtb_one_entry, + &srh_succ); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_hash_zcam_delete_hardware",p_data_buff); + + if(srh_succ) + { + rc = dpp_dtb_data_write(p_data_buff, 0, &dtb_one_entry); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_data_write",p_data_buff); + dtb_len = dtb_one_entry.data_size/DTB_LEN_POS_SETP + 1; + + rc = dpp_dtb_write_down_table_data(dev, + queue_id, + dtb_len * DTB_LEN_POS_SETP, + p_data_buff, + element_id); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_write_down_table_data",p_data_buff); + } + } + + ZXIC_COMM_FREE(p_data_buff); + + return DPP_OK; +} + +/***********************************************************/ +/** 将hash表DDR存储位宽(按照256bit/512bit划分)转换为hash在DDR中的实际位置(按照128/256/512bit划分) +* @param index hash表DDR存储位宽索引(按照256bit/512bit划分) +* @param width_mode DDR位宽(256bit/512bit) +* @param key_type hash表项位宽DPP_HASH_KEY_TYPE +* @param byte_offset hash表项在一个DDR存储位宽(256bit/512bit)里的偏移,单位为字节 +* @return +* @remark 无 +* @see +* @author cq @date 2023/08/02 +************************************************************/ +ZXIC_UINT32 dpp_ddr_index_calc(ZXIC_UINT32 index, + ZXIC_UINT32 width_mode, + ZXIC_UINT32 key_type, + ZXIC_UINT32 byte_offset) +{ + ZXIC_UINT32 ddr_index = 0; /*按照hash位宽128/256/512bit进行划分*/ + ZXIC_UINT32 entry_size = 0; + + entry_size = DPP_GET_HASH_ENTRY_SIZE(key_type); + if(0==entry_size) + { + return ddr_index; + } + + if(DDR_WIDTH_256b==width_mode) + { + if (HASH_KEY_128b == key_type) + { + ddr_index = (index<<1) + ((byte_offset/entry_size)&0x1); + } + else if (HASH_KEY_256b == key_type) + { + ddr_index = index; + } + } + else if(DDR_WIDTH_512b==width_mode) + { + if (HASH_KEY_128b == key_type) + { + ddr_index = (index<<2) + ((byte_offset/entry_size)&0x3); + } + else if (HASH_KEY_256b == key_type) + { + ddr_index = (index<<1) + ((byte_offset/entry_size)&0x1); + } + else if (HASH_KEY_512b == key_type) + { + ddr_index = index; + } + } + + return ddr_index; +} + +/***********************************************************/ +/** 查找存储在ZCAM空间的hash表项并删除(硬件处理) +* @param dev_id 设备号，支持多芯片 +* @param queue_id 队列id +* @param p_hash_entry_cfg hash表项配置信息 +* @param p_hash_entry 查找键值信息 +* @param p_entry dtb描述符 +* @param p_srh_succ 出参，查找是否成功 +* @return +* @remark 无 +* @see +* @author cq @date 2023/08/02 +************************************************************/ +ZXIC_UINT32 dpp_dtb_hash_zcam_delete_hardware(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + HASH_ENTRY_CFG *p_hash_entry_cfg, + DPP_HASH_ENTRY *p_hash_entry, + DPP_DTB_ENTRY_T *p_entry, + ZXIC_UINT8 *p_srh_succ) +{ + DPP_STATUS rc = DPP_OK; + DPP_HASH_RBKEY_INFO srh_rbkey = {0}; + DPP_HASH_CFG *p_hash_cfg = NULL; + SE_ZCELL_CFG *p_zcell = NULL; + SE_ZBLK_CFG *p_zblk = NULL; + + ZXIC_UINT32 zblk_idx = 0; + ZXIC_UINT32 pre_zblk_idx = 0xFFFFFFFF;/* -1; */ + ZXIC_UINT16 crc16_value = 0; + ZXIC_UINT32 zcell_id = 0; + ZXIC_UINT32 item_idx = 0; + ZXIC_UINT32 element_id = 0; + ZXIC_UINT8 byte_offset = 0; + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 addr = 0; + ZXIC_UINT32 i = 0; + ZXIC_UINT8 srh_succ = 0; + ZXIC_UINT8 temp_key[HASH_KEY_MAX] = {0}; + ZXIC_UINT8 rd_buff[SE_ITEM_WIDTH_MAX] = {0}; + + D_NODE *p_zblk_dn = NULL; + D_NODE *p_zcell_dn = NULL; + DPP_SE_CFG *p_se_cfg = NULL; + + ZXIC_COMM_CHECK_POINT_NO_ASSERT(dev); + dev_id = DEV_ID(dev); + ZXIC_COMM_CHECK_INDEX_UPPER(dev_id,DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_INDEX(queue_id, 0, DTB_QUEUE_MAX - 1); + ZXIC_COMM_CHECK_POINT(p_hash_entry_cfg); + ZXIC_COMM_CHECK_POINT(p_srh_succ); + ZXIC_COMM_CHECK_POINT(p_hash_entry); + ZXIC_COMM_CHECK_POINT(p_hash_entry->p_key); + ZXIC_COMM_CHECK_POINT(p_hash_entry->p_rst); + + ZXIC_COMM_MEMSET(rd_buff,0x0,sizeof(rd_buff)); + ZXIC_COMM_MEMSET(&srh_rbkey,0x0,sizeof(DPP_HASH_RBKEY_INFO)); + ZXIC_COMM_CHECK_INDEX_UPPER(p_hash_entry_cfg->key_by_size, HASH_KEY_MAX); + ZXIC_COMM_MEMCPY(srh_rbkey.key,p_hash_entry->p_key,p_hash_entry_cfg->key_by_size); + + p_hash_cfg = p_hash_entry_cfg->p_hash_cfg; + ZXIC_COMM_CHECK_POINT(p_hash_cfg); + + /* 取出se配置 */ + rc = dpp_se_cfg_get(dev_id, &p_se_cfg); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_se_cfg_get"); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_se_cfg); + + ZXIC_COMM_CHECK_INDEX_UPPER(p_hash_entry_cfg->key_by_size, HASH_KEY_MAX); + rc = dpp_hash_set_crc_key(dev,p_hash_entry_cfg,p_hash_entry,temp_key); + ZXIC_COMM_CHECK_DEV_RC(dev_id,rc,"hash_set_crc_key"); + + /*查找所有的zcell*/ + p_zcell_dn = p_hash_cfg->hash_shareram.zcell_free_list.p_next; + while (p_zcell_dn) + { + p_zcell = (SE_ZCELL_CFG *)p_zcell_dn->data; + zblk_idx = GET_ZBLK_IDX(p_zcell->zcell_idx); + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, zblk_idx, 0, SE_ZBLK_NUM - 1); + p_zblk = &(p_se_cfg->zblk_info[zblk_idx]); + + if (zblk_idx != pre_zblk_idx) + { + pre_zblk_idx = zblk_idx; + crc16_value = p_hash_cfg->p_hash16_fun(temp_key, p_hash_entry_cfg->key_by_size, p_zblk->hash_arg); + } + + zcell_id = GET_ZCELL_IDX(p_zcell->zcell_idx); + item_idx = GET_ZCELL_CRC_VAL(zcell_id, crc16_value); + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, item_idx, 0, SE_RAM_DEPTH - 1); + addr = ZBLK_ITEM_ADDR_CALC(p_zcell->zcell_idx, item_idx); + rc = dpp_dtb_se_zcam_dma_dump(dev, + queue_id, + addr, + DTB_DUMP_ZCAM_512b, + 1, + (ZXIC_UINT32 *)rd_buff, + &element_id); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_se_zcam_dma_dump"); + zxic_comm_swap(rd_buff,sizeof(rd_buff)); + + rc = dpp_dtb_hash_data_parse(ITEM_RAM,p_hash_entry_cfg->key_by_size,p_hash_entry,rd_buff,&byte_offset); + if(DPP_OK == rc) + { + ZXIC_COMM_TRACE_DEBUG("Hash search hardware succ in zcell. \n"); + srh_succ = 1; + p_hash_cfg->hash_stat.search_ok++; + break; + } + + p_zcell_dn = p_zcell_dn->next; + } + + /*zcell查找失败，则查找所有的zreg*/ + if(0==srh_succ) + { + p_zblk_dn = p_hash_cfg->hash_shareram.zblk_list.p_next; + while (p_zblk_dn) + { + p_zblk = (SE_ZBLK_CFG *)p_zblk_dn->data; + zblk_idx = p_zblk->zblk_idx; + + for (i = 0; i < SE_ZREG_NUM; i++) + { + item_idx = i; + addr = ZBLK_HASH_LIST_REG_ADDR_CALC(zblk_idx, item_idx); + rc = dpp_dtb_se_zcam_dma_dump(dev, + queue_id, + addr, + DTB_DUMP_ZCAM_512b, + 1, + (ZXIC_UINT32 *)rd_buff, + &element_id); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_se_zcam_dma_dump"); + zxic_comm_swap(rd_buff,sizeof(rd_buff)); + + rc = dpp_dtb_hash_data_parse(ITEM_RAM,p_hash_entry_cfg->key_by_size,p_hash_entry,rd_buff,&byte_offset); + if(DPP_OK == rc) + { + ZXIC_COMM_TRACE_DEBUG("Hash search hardware succ in zreg. \n"); + srh_succ = 1; + p_hash_cfg->hash_stat.search_ok++; + break; + } + } + p_zblk_dn = p_zblk_dn->next; + } + } + + /*查找成功，则将对应表项删除*/ + if(srh_succ) + { + ZXIC_COMM_MEMSET(rd_buff+byte_offset,0x0,DPP_GET_HASH_ENTRY_SIZE(p_hash_entry_cfg->key_type)); + zxic_comm_swap(rd_buff,sizeof(rd_buff)); + rc = dpp_dtb_se_alg_zcam_data_write(dev_id, + addr, + rd_buff, + p_entry); + ZXIC_COMM_CHECK_DEV_RC(dev_id,rc,"dpp_dtb_se_alg_zcam_data_write"); + p_hash_cfg->hash_stat.delete_ok++; + } + + *p_srh_succ = srh_succ; + + return DPP_OK; +} + +/** dtb写ACL表 （SPECIFY模式，条目中指定handle，支持级联64bit/128bit） +* @param dev_id 设备号 +* @param queue_id 队列号 +* @param sdt_no ACL表sdt表号 +* @param entry_num 下发的条目数 +* @param p_acl_entry_arr 待下发表项内容结构体数组指针 +* @param element_id 返回下表使用的元素id +* @return +* @remark 无 是否是有一个写不成功就返回，还是继续进行下一个条目并记录错误的条目 +* @see +* @author cbb @date 2022/08/30 +************************************************************/ +DPP_STATUS dpp_dtb_acl_dma_insert(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 sdt_no, + ZXIC_UINT32 entry_num, + DPP_DTB_ACL_ENTRY_INFO_T *p_acl_entry_arr, + ZXIC_UINT32 *element_id + ) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 as_enable; + ZXIC_UINT32 etcam_as_mode; + ZXIC_UINT32 entry_num_max = 0; + ZXIC_UINT32 entry_cycle = 0; + ZXIC_UINT32 entry_remains = 0; + ZXIC_UINT32 i = 0; + DPP_DTB_ACL_ENTRY_INFO_T *p_entry = NULL; + + DPP_SDTTBL_ETCAM_T sdt_etcam_info = {0}; /*SDT内容*/ + + ZXIC_COMM_CHECK_POINT(dev); + rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_etcam_info); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_soft_sdt_tbl_get"); + + as_enable = sdt_etcam_info.as_en; + etcam_as_mode = sdt_etcam_info.as_rsp_mode; + + if(!as_enable) + { + entry_num_max = 0x55; + }else + { + if(etcam_as_mode == ERAM128_TBL_128b) + { + entry_num_max = 0x49; + }else + { + entry_num_max = 0x4e; + } + } + + entry_cycle = entry_num / entry_num_max; + entry_remains = entry_num % entry_num_max; + + for(i = 0; i < entry_cycle; ++i) + { + p_entry = p_acl_entry_arr + entry_num_max * i; + rc = dpp_dtb_acl_dma_insert_cycle(dev, + queue_id, + sdt_no, + entry_num_max, + p_entry, + element_id); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_acl_dma_insert_cycle"); + + ZXIC_COMM_TRACE_INFO("dpp_dtb_acl_dma_insert_cycle[%d]: element_id = %d\n", i, *element_id); + } + + if(entry_remains) + { + p_entry = p_acl_entry_arr + entry_num_max * entry_cycle; + rc = dpp_dtb_acl_dma_insert_cycle(dev, + queue_id, + sdt_no, + entry_remains, + p_entry, + element_id); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_acl_dma_insert_cycle"); + + ZXIC_COMM_TRACE_INFO("dpp_dtb_acl_dma_insert_cycle: element_id = %d\n", *element_id); + } + + return DPP_OK; +} + +#endif + +#if ZXIC_REAL("DTB DUMP BASE") + +/** smmu0 组装dump描述符函数 +* @param dev_id 设备号 +* @param base_addr smmu0空间基地址，以128bit为单位 +* @param depth dump的深度以128bit为单位 +* @param addr_high32 dump缓存地址高32bit +* @param addr_low32 dump缓存地址低32bit +* @param p_dump_info dump描述符指针（已分配好空间128bit） +* @return +* @remark 无 +* @see +* @author cbb @date 2022/08/30 +************************************************************/ +DPP_STATUS dpp_dtb_smmu0_dump_info_write(DPP_DEV_T *dev, + ZXIC_UINT32 base_addr, + ZXIC_UINT32 depth, + ZXIC_UINT32 addr_high32, + ZXIC_UINT32 addr_low32, + ZXIC_UINT32 *p_dump_info) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 i = 0; + + DPP_DTB_ERAM_DUMP_FORM_T dtb_eram_dump_form_info = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_POINT(p_dump_info); + + //组装dump描述符 + dtb_eram_dump_form_info.valid = DTB_TABLE_VALID; + dtb_eram_dump_form_info.up_type = DTB_DUMP_MODE_ERAM; + dtb_eram_dump_form_info.base_addr = base_addr; + dtb_eram_dump_form_info.tb_depth = depth; + dtb_eram_dump_form_info.tb_dst_addr_h = addr_high32; + dtb_eram_dump_form_info.tb_dst_addr_l = addr_low32; + + if(dpp_dtb_prt_get()) + { + ZXIC_COMM_PRINT("dpp_dtb_smmu0_dump_info_write: \n"); + ZXIC_COMM_DBGCNT32_PRINT("valid", dtb_eram_dump_form_info.valid); + ZXIC_COMM_DBGCNT32_PRINT("up_type", dtb_eram_dump_form_info.up_type); + ZXIC_COMM_DBGCNT32_PRINT("base_addr", dtb_eram_dump_form_info.base_addr); + ZXIC_COMM_DBGCNT32_PRINT("tb_depth", dtb_eram_dump_form_info.tb_depth); + ZXIC_COMM_DBGCNT32_PRINT("tb_dst_addr_h", dtb_eram_dump_form_info.tb_dst_addr_h); + ZXIC_COMM_DBGCNT32_PRINT("tb_dst_addr_l", dtb_eram_dump_form_info.tb_dst_addr_l); + } + + /*组装dump描述符*/ + rc = dpp_dtb_write_dump_cmd(DEV_ID(dev), DTB_DUMP_ERAM, &dtb_eram_dump_form_info, p_dump_info); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_write_dump_cmd"); + + //打印出cmd buff中内容128bit + if(dpp_dtb_prt_get()) + { + ZXIC_COMM_PRINT("dump type: %d\n", DTB_DUMP_MODE_ERAM); + ZXIC_COMM_PRINT("cmd: "); + for(i = 0; i < 4; i++) + { + ZXIC_COMM_PRINT("0x%08x ", ZXIC_COMM_CONVERT32(*((ZXIC_UINT32 *)(p_dump_info + i))));//转换成大端显示 + } + ZXIC_COMM_PRINT("\n"); + } + return rc; +} + +/** smmu1 组装dump描述符函数 +* @param dev_id 设备号 +* @param base_addr dump基地址，以512it为单位 +* @param depth dump的深度以512bit为单位 +* @param addr_high32 dump缓存地址高32bit +* @param addr_low32 dump缓存地址低32bit +* @param p_dump_info dump描述符指针（已分配好空间128bit） +* @return +* @remark 无 +* @see +* @author cbb @date 2022/08/30 +************************************************************/ +DPP_STATUS dpp_dtb_smmu1_dump_info_write(DPP_DEV_T *dev, + ZXIC_UINT32 base_addr, + ZXIC_UINT32 depth, + ZXIC_UINT32 addr_high32, + ZXIC_UINT32 addr_low32, + ZXIC_UINT32 *p_dump_info + ) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 i = 0; + + DPP_DTB_DDR_DUMP_FORM_T dtb_ddr_dump_form_info = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_POINT(p_dump_info); + + //组装dump描述符 + dtb_ddr_dump_form_info.valid = DTB_TABLE_VALID; + dtb_ddr_dump_form_info.up_type = DTB_DUMP_MODE_DDR; + dtb_ddr_dump_form_info.base_addr = base_addr; + dtb_ddr_dump_form_info.tb_depth = depth; + dtb_ddr_dump_form_info.tb_dst_addr_h = addr_high32; + dtb_ddr_dump_form_info.tb_dst_addr_l = addr_low32; + + if(dpp_dtb_prt_get()) + { + ZXIC_COMM_PRINT("dpp_dtb_smmu1_dump_info_write: \n"); + ZXIC_COMM_DBGCNT32_PRINT("valid", dtb_ddr_dump_form_info.valid); + ZXIC_COMM_DBGCNT32_PRINT("up_type", dtb_ddr_dump_form_info.up_type); + ZXIC_COMM_DBGCNT32_PRINT("base_addr", dtb_ddr_dump_form_info.base_addr); + ZXIC_COMM_DBGCNT32_PRINT("tb_depth", dtb_ddr_dump_form_info.tb_depth); + ZXIC_COMM_DBGCNT32_PRINT("tb_dst_addr_h", dtb_ddr_dump_form_info.tb_dst_addr_h); + ZXIC_COMM_DBGCNT32_PRINT("tb_dst_addr_l", dtb_ddr_dump_form_info.tb_dst_addr_l); + } + + /*组装dump描述符*/ + rc = dpp_dtb_write_dump_cmd(DEV_ID(dev), DTB_DUMP_DDR, &dtb_ddr_dump_form_info, p_dump_info); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_write_dump_cmd"); + + //打印出cmd buff中内容128bit + if(dpp_dtb_prt_get()) + { + ZXIC_COMM_PRINT("dump type: %d\n", DTB_DUMP_MODE_ERAM); + ZXIC_COMM_PRINT("cmd: "); + for(i = 0; i < 4; i++) + { + ZXIC_COMM_PRINT("0x%08x ", ZXIC_COMM_CONVERT32(*((ZXIC_UINT32 *)(p_dump_info + i))));//转换成大端显示 + } + ZXIC_COMM_PRINT("\n"); + } + + return rc; +} + +/** zcam 组装dump描述符函数 +* @param dev_id 设备号 +* @param addr zcam内部ram地址，包括掩码(512bit为单位) +* @param tb_width dump数据的宽度 00:128bit 01:256bit 10:512bit +* @param depth dump的深度以512bit为单位 +* @param addr_high32 dump缓存地址高32bit +* @param addr_low32 dump缓存地址低32bit +* @param p_dump_info dump描述符指针（已分配好空间128bit） +* @return +* @remark 无 +* @see +* @author cbb @date 2022/08/30 +************************************************************/ +DPP_STATUS dpp_dtb_zcam_dump_info_write(DPP_DEV_T *dev, + ZXIC_UINT32 addr, + ZXIC_UINT32 tb_width, + ZXIC_UINT32 depth, + ZXIC_UINT32 addr_high32, + ZXIC_UINT32 addr_low32, + ZXIC_UINT32 *p_dump_info + ) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 i = 0; + + DPP_DTB_ZCAM_DUMP_FORM_T dtb_zcam_dump_form_info = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_POINT(p_dump_info); + + //组装dump描述符 + dtb_zcam_dump_form_info.valid = DTB_TABLE_VALID; + dtb_zcam_dump_form_info.up_type = DTB_DUMP_MODE_ZCAM; + dtb_zcam_dump_form_info.tb_width = tb_width; + dtb_zcam_dump_form_info.sram_addr = addr & 0x1FF;//512bit为单位 + dtb_zcam_dump_form_info.ram_reg_flag = (addr >> 16) & 0x1; + dtb_zcam_dump_form_info.z_reg_cell_id = (addr >> 9) & 0x3; + dtb_zcam_dump_form_info.zblock_id = (addr >> 11) & 0x7; + dtb_zcam_dump_form_info.zgroup_id = (addr >> 14) & 0x3; + dtb_zcam_dump_form_info.tb_depth = depth; + dtb_zcam_dump_form_info.tb_dst_addr_h = addr_high32; + dtb_zcam_dump_form_info.tb_dst_addr_l = addr_low32; + + if(dpp_dtb_prt_get()) + { + ZXIC_COMM_PRINT("dpp_dtb_zcam_dump_info_write: \n"); + ZXIC_COMM_DBGCNT32_PRINT("addr", addr); + ZXIC_COMM_DBGCNT32_PRINT("valid", dtb_zcam_dump_form_info.valid); + ZXIC_COMM_DBGCNT32_PRINT("up_type", dtb_zcam_dump_form_info.up_type); + ZXIC_COMM_DBGCNT32_PRINT("zgroup_id", dtb_zcam_dump_form_info.zgroup_id); + ZXIC_COMM_DBGCNT32_PRINT("zblock_id", dtb_zcam_dump_form_info.zblock_id); + ZXIC_COMM_DBGCNT32_PRINT("reg_sram_flag", dtb_zcam_dump_form_info.ram_reg_flag); + ZXIC_COMM_DBGCNT32_PRINT("zcell_id", dtb_zcam_dump_form_info.z_reg_cell_id); + ZXIC_COMM_DBGCNT32_PRINT("tb_width", dtb_zcam_dump_form_info.tb_width); + ZXIC_COMM_DBGCNT32_PRINT("sram_addr", dtb_zcam_dump_form_info.sram_addr); + ZXIC_COMM_DBGCNT32_PRINT("tb_depth", dtb_zcam_dump_form_info.tb_depth); + ZXIC_COMM_DBGCNT32_PRINT("tb_dst_addr_h", dtb_zcam_dump_form_info.tb_dst_addr_h); + ZXIC_COMM_DBGCNT32_PRINT("tb_dst_addr_l", dtb_zcam_dump_form_info.tb_dst_addr_l); + } + + //将描述符写入dump缓存中 + rc = dpp_dtb_write_dump_cmd(DEV_ID(dev), DTB_DUMP_ZCAM, &dtb_zcam_dump_form_info, p_dump_info); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_write_dump_cmd"); + + //打印出cmd buff中内容128bit + if(dpp_dtb_prt_get()) + { + ZXIC_COMM_PRINT("dump type: %d\n", DTB_DUMP_MODE_ERAM); + ZXIC_COMM_PRINT("cmd: "); + for(i = 0; i < 4; i++) + { + ZXIC_COMM_PRINT("0x%08x ", ZXIC_COMM_CONVERT32(*((ZXIC_UINT32 *)(p_dump_info + i))));//转换成大端显示 + } + ZXIC_COMM_PRINT("\n"); + } + + return rc; +} + +/** etcam 组装dump描述符函数 +* @param dev_id 设备号 +* @param p_etcam_dump_info etcam dump内容信息 +* @param addr_high32 dump缓存地址高32bit +* @param addr_low32 dump缓存地址低32bit +* @param p_dump_info dump描述符指针（已分配好空间128bit） +* @return +* @remark 无 +* @see +* @author cbb @date 2022/08/30 +************************************************************/ +DPP_STATUS dpp_dtb_etcam_dump_info_write(DPP_DEV_T *dev, + ETCAM_DUMP_INFO_T *p_etcam_dump_info, + ZXIC_UINT32 addr_high32, + ZXIC_UINT32 addr_low32, + ZXIC_UINT32 *p_dump_info + ) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 i = 0; + + DPP_DTB_ETCAM_DUMP_FORM_T dtb_etcam_dump_form_info = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_POINT(p_dump_info); + ZXIC_COMM_CHECK_POINT(p_etcam_dump_info); + + //组装dump描述符 + dtb_etcam_dump_form_info.valid = DTB_TABLE_VALID; + dtb_etcam_dump_form_info.up_type = DTB_DUMP_MODE_ETCAM; + dtb_etcam_dump_form_info.block_sel = p_etcam_dump_info->block_sel; + dtb_etcam_dump_form_info.addr = p_etcam_dump_info->addr; + dtb_etcam_dump_form_info.rd_mode = p_etcam_dump_info->rd_mode; + dtb_etcam_dump_form_info.data_or_mask = p_etcam_dump_info->data_or_mask; + dtb_etcam_dump_form_info.tb_depth = p_etcam_dump_info->tb_depth; + dtb_etcam_dump_form_info.tb_width = p_etcam_dump_info->tb_width;//00:80bit 01:160bit 10:320bit 11:640bit + dtb_etcam_dump_form_info.tb_dst_addr_h = addr_high32; + dtb_etcam_dump_form_info.tb_dst_addr_l = addr_low32; + + if(dpp_dtb_prt_get()) + { + ZXIC_COMM_PRINT("dpp_dtb_etcam_dump_info_write: \n"); + ZXIC_COMM_DBGCNT32_PRINT("valid", dtb_etcam_dump_form_info.valid); + ZXIC_COMM_DBGCNT32_PRINT("up_type", dtb_etcam_dump_form_info.up_type); + ZXIC_COMM_DBGCNT32_PRINT("block_sel", dtb_etcam_dump_form_info.block_sel); + ZXIC_COMM_DBGCNT32_PRINT("addr", dtb_etcam_dump_form_info.addr); + ZXIC_COMM_DBGCNT32_PRINT("rd_mode", dtb_etcam_dump_form_info.rd_mode); + ZXIC_COMM_DBGCNT32_PRINT("data_or_mask", dtb_etcam_dump_form_info.data_or_mask); + ZXIC_COMM_DBGCNT32_PRINT("tb_depth", dtb_etcam_dump_form_info.tb_depth); + ZXIC_COMM_DBGCNT32_PRINT("tb_width", dtb_etcam_dump_form_info.tb_width); + ZXIC_COMM_DBGCNT32_PRINT("tb_dst_addr_h", dtb_etcam_dump_form_info.tb_dst_addr_h); + ZXIC_COMM_DBGCNT32_PRINT("tb_dst_addr_l", dtb_etcam_dump_form_info.tb_dst_addr_l); + } + + //将描述符写入dump缓存中 + rc = dpp_dtb_write_dump_cmd(DEV_ID(dev), DTB_DUMP_ETCAM, &dtb_etcam_dump_form_info, p_dump_info); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_write_dump_cmd"); + + //打印出cmd buff中内容128bit + if(dpp_dtb_prt_get()) + { + ZXIC_COMM_PRINT("dump type: %d\n", DTB_DUMP_MODE_ERAM); + ZXIC_COMM_PRINT("cmd: "); + for(i = 0; i < 4; i++) + { + ZXIC_COMM_PRINT("0x%08x ", ZXIC_COMM_CONVERT32(*((ZXIC_UINT32 *)(p_dump_info + i))));//转换成大端显示 + } + ZXIC_COMM_PRINT("\n"); + } + + return rc; +} + +/** eram 生成dump entry，输入dump描述符，输出一个entry +* @param dev_id 设备号 +* @param base_addr smmu0空间基地址，以128bit为单位 +* @param depth dump的深度以128bit为单位 +* @param addr_high32 dump缓存地址高32bit +* @param addr_low32 dump缓存地址低32bit +* @param p_entry entry指针（已分配好cmd空间128bit,用来存放dump描述符） +* @return +* @remark 无 +* @see +* @author cbb @date 2022/08/30 +************************************************************/ +DPP_STATUS dpp_dtb_smmu0_dump_entry(DPP_DEV_T *dev, + ZXIC_UINT32 base_addr, + ZXIC_UINT32 depth, + ZXIC_UINT32 addr_high32, + ZXIC_UINT32 addr_low32, + DPP_DTB_ENTRY_T *p_entry) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_POINT(p_entry); + + rc = dpp_dtb_smmu0_dump_info_write(dev, + base_addr, + depth, + addr_high32, + addr_low32, + (ZXIC_UINT32 *)p_entry->cmd); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_smmu0_dump_info_write"); + p_entry->data_in_cmd_flag = 1; + + return rc; +} + +/** smmu1生成dump entry，输入dump描述符，输出一个entry +* @param dev_id 设备号 +* @param base_addr dump基地址，以128bit为单位 +* @param depth dump的深度以512bit为单位 +* @param addr_high32 dump缓存地址高32bit +* @param addr_low32 dump缓存地址低32bit +* @param p_entry entry指针（已分配好cmd空间128bit,用来存放dump描述符） +* @return +* @remark 无 +* @see +* @author cbb @date 2022/08/30 +************************************************************/ +DPP_STATUS dpp_dtb_smmu1_dump_entry(DPP_DEV_T *dev, + ZXIC_UINT32 base_addr, + ZXIC_UINT32 depth, + ZXIC_UINT32 addr_high32, + ZXIC_UINT32 addr_low32, + DPP_DTB_ENTRY_T *p_entry) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_POINT(p_entry); + + rc = dpp_dtb_smmu1_dump_info_write(dev, + base_addr, + depth, + addr_high32, + addr_low32, + (ZXIC_UINT32 *)p_entry->cmd); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_smmu1_dump_info_write"); + p_entry->data_in_cmd_flag = 1; + + return rc; +} + +/** zcam 组装dump描述符函数 +* @param dev_id 设备号 +* @param addr zcam内部ram地址，包括掩码(512bit为单位) +* @param tb_width dump数据的宽度 00:128bit 01:256bit 10:512bit +* @param depth dump的深度以512bit为单位 +* @param addr_high32 dump缓存地址高32bit +* @param addr_low32 dump缓存地址低32bit +* @param p_entry entry指针（已分配好cmd空间128bit,用来存放dump描述符） +* @return +* @remark 无 +* @see +* @author cbb @date 2022/08/30 +************************************************************/ +DPP_STATUS dpp_dtb_zcam_dump_entry(DPP_DEV_T *dev, + ZXIC_UINT32 addr, + ZXIC_UINT32 tb_width, + ZXIC_UINT32 depth, + ZXIC_UINT32 addr_high32, + ZXIC_UINT32 addr_low32, + DPP_DTB_ENTRY_T *p_entry) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_POINT(p_entry); + + rc = dpp_dtb_zcam_dump_info_write(dev, + addr, + tb_width, + depth, + addr_high32, + addr_low32, + (ZXIC_UINT32 *)p_entry->cmd); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_zcam_dump_info_write"); + p_entry->data_in_cmd_flag = 1; + + return rc; +} + +/** etcam 生成dump entry，输入dump描述符，输出一个entry +* @param dev_id 设备号 +* @param p_etcam_dump_info etcam dump内容信息 +* @param addr_high32 dump缓存地址高32bit +* @param addr_low32 dump缓存地址低32bit +* @param p_entry entry指针（已分配好cmd空间128bit,用来存放dump描述符） +* @return +* @remark 无 +* @see +* @author cbb @date 2022/08/30 +************************************************************/ +DPP_STATUS dpp_dtb_etcam_dump_entry(DPP_DEV_T *dev, + ETCAM_DUMP_INFO_T *p_etcam_dump_info, + ZXIC_UINT32 addr_high32, + ZXIC_UINT32 addr_low32, + DPP_DTB_ENTRY_T *p_entry) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_POINT(p_entry); + + rc = dpp_dtb_etcam_dump_info_write(dev, + p_etcam_dump_info, + addr_high32, + addr_low32, + (ZXIC_UINT32 *)p_entry->cmd); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_etcam_dump_info_write"); + p_entry->data_in_cmd_flag = 1; + + return rc; +} + + +/** 下发dump描述符，dump出数据 +* @param dev_id 设备号 +* @param queue_id 队列号 +* @param queue_element_id 元素编号 +* @param p_dump_info dump描述符 +* @param data_len dump出数据的长度(32bit为单位) +* @param desc_len dump描述符的长度(32bit为单位) +* @param p_dump_data dump出的数据缓存 +* @return +* @remark 无 +* @see +* @author cbb @date 2022/08/30 +************************************************************/ +DPP_STATUS dpp_dtb_write_dump_desc_info(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 queue_element_id, + ZXIC_UINT32 *p_dump_info, + ZXIC_UINT32 data_len, + ZXIC_UINT32 desc_len, + ZXIC_UINT32 *p_dump_data ) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_UINT32 dtb_interrupt_status = 0; + + ZXIC_COMM_CHECK_POINT(dev); + + /*获取中断配置*/ + dtb_interrupt_status = dpp_dtb_interrupt_status_get(); + + /*下发dump描述符*/ + rc = dpp_dtb_tab_up_info_set(dev, + queue_id, + queue_element_id, + dtb_interrupt_status, + data_len, + desc_len, + p_dump_info); + if(DPP_OK != rc) + { + ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "the queue %d element id %d dump info set failed!", queue_id, queue_element_id); + dpp_dtb_item_ack_wr(dev, queue_id, DPP_DTB_DIR_UP_TYPE, queue_element_id, 0, DPP_DTB_TAB_ACK_UNUSED_MASK); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_dtb_tab_up_info_set"); + } + + /*查询是否dump完成，完成后取出数据 需要在dpp_dtb.c中补充查询一个元素ack是否成功函数*/ + if(!dtb_interrupt_status) + { + + rc = dpp_dtb_tab_up_success_status_check(dev, queue_id, queue_element_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_dtb_tab_up_success_status_check"); + + /*取出数据*/ + rc = dpp_dtb_tab_up_data_get(dev, queue_id, queue_element_id, data_len, p_dump_data); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_dtb_tab_up_data_get"); + }else + { + rc = dpp_dtb_tab_up_success_status_check(dev, queue_id, queue_element_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_dtb_tab_up_success_status_check"); + + /*取出数据*/ + rc = dpp_dtb_tab_up_data_get(dev, queue_id, queue_element_id, data_len, p_dump_data); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_dtb_tab_up_data_get"); + /*清中断*/ + dpp_dtb_finish_interrupt_event_state_clr(dev, queue_id); + } + + return DPP_OK; +} + + +/** smmu0 dump 只写一个dump描述符的接口 +* @param dev_id 设备号 +* @param queue_id 队列号 +* @param base_addr 要dump的内容的基地址，以128bit为单位 +* @param depth dump的深度以128bit为单位 +* @param p_data dump出数据缓存(128bit * depth) +* @param element_id 返回下表使用的元素id +* @return +* @remark 无 +* @see +* @author cbb @date 2022/08/30 +************************************************************/ +DPP_STATUS dpp_dtb_se_smmu0_dma_dump(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 base_addr, + ZXIC_UINT32 depth, + ZXIC_UINT32 *p_data, + ZXIC_UINT32 *element_id + ) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 dump_dst_phy_haddr = 0; + ZXIC_UINT32 dump_dst_phy_laddr = 0; + ZXIC_UINT32 queue_item_index = 0; + ZXIC_UINT32 data_len = 0; + ZXIC_UINT32 desc_len = 0; + + ZXIC_UINT8 form_buff[DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DTB_QUEUE_MAX - 1); + ZXIC_COMM_CHECK_INDEX_LOWER(depth, 1); + + /*获取队列中可用的元素编号*/ + rc = dpp_dtb_tab_up_free_item_get(dev, queue_id, &queue_item_index); + if(rc != DPP_OK) + { + ZXIC_COMM_TRACE_ERROR("dpp_dtb_tab_up_free_item_get failed!\n"); + return DPP_RC_DTB_QUEUE_ITEM_SW_EMPTY; + } + + if(dpp_dtb_prt_get()) + { + ZXIC_COMM_PRINT("dump smmu0:queue %d,item_index: %d\n",queue_id, queue_item_index); + } + + *element_id = queue_item_index;//保存获取的item_index + + /*获取地址*/ + rc = dpp_dtb_tab_up_item_addr_get(dev, queue_id, queue_item_index, &dump_dst_phy_haddr, &dump_dst_phy_laddr); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_tab_up_item_addr_get"); + + rc = dpp_dtb_smmu0_dump_info_write(dev, + base_addr, + depth, + dump_dst_phy_haddr, + dump_dst_phy_laddr, + (ZXIC_UINT32 *)form_buff); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_smmu0_dump_info_write"); + + /*组装下表命令格式*/ + + data_len = depth * 128 / 32; + desc_len = DTB_LEN_POS_SETP / 4; + + rc = dpp_dtb_write_dump_desc_info(dev, queue_id, queue_item_index, (ZXIC_UINT32 *)form_buff, data_len, desc_len, p_data); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_write_dump_desc_info"); + + return DPP_OK; +} + +/** dtb dump DDR表项内容 返回内容以512bit为单位 +* @param dev_id 设备号 +* @param queue_id 队列号 +* @param base_addr dump基地址，以512bit为单位 +* @param depth dump的深度以512bit为单位 +* @param p_data dump出数据缓存(512bit * depth) +* @param element_id 返回下表使用的元素id +* @return +* @remark 无 +* @see +* @author cbb @date 2022/08/30 +************************************************************/ +DPP_STATUS dpp_dtb_se_smmu1_dma_dump(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 base_addr, + ZXIC_UINT32 depth, + ZXIC_UINT32 *p_data, + ZXIC_UINT32 *element_id) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_UINT32 dump_dst_phy_haddr = 0; + ZXIC_UINT32 dump_dst_phy_laddr = 0; + + ZXIC_UINT32 queue_item_index = 0; + ZXIC_UINT32 data_len = 0; + ZXIC_UINT32 desc_len = 0; + + ZXIC_UINT8 form_buff[DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DTB_QUEUE_MAX - 1); + ZXIC_COMM_CHECK_INDEX_LOWER(depth, 1); + + /*获取队列元素*/ + rc = dpp_dtb_tab_up_free_item_get(dev, queue_id, &queue_item_index); + if(rc != DPP_OK) + { + ZXIC_COMM_TRACE_ERROR("dpp_dtb_tab_up_free_item_get failed!\n"); + return DPP_RC_DTB_QUEUE_ITEM_SW_EMPTY; + } + + if(dpp_dtb_prt_get()) + { + ZXIC_COMM_PRINT("dump smmu1:queue %d,item_index: %d\n",queue_id, queue_item_index); + } + + *element_id = queue_item_index;//保存获取的item_index + + /*获取dump dma phy地址*/ + rc = dpp_dtb_tab_up_item_addr_get(dev, queue_id, queue_item_index, &dump_dst_phy_haddr, &dump_dst_phy_laddr); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_tab_up_item_addr_get"); + + rc = dpp_dtb_smmu1_dump_info_write(dev, + base_addr, + depth, + dump_dst_phy_haddr, + dump_dst_phy_laddr, + (ZXIC_UINT32 *)form_buff); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_smmu1_dump_info_write"); + + /*组装下表命令格式*/ + data_len = depth * 512 / 32;//要提取的数据长度，以32bit为单位 + desc_len = DTB_LEN_POS_SETP / 4;//描述符长度，以32bit为单位 + + rc = dpp_dtb_write_dump_desc_info(dev, queue_id, queue_item_index, (ZXIC_UINT32 *)form_buff, data_len, desc_len, p_data); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_write_dump_desc_info"); + + return DPP_OK; +} + +/** dtb dump zcam表项内容 +* @param dev_id 设备号 +* @param queue_id 队列号 +* @param addr zcam内部ram地址，包括掩码 +* @param tb_width dump数据的宽度 +* @param depth dump的深度以tb_width为单位 +* @param p_data dump出数据缓存(tb_width * depth) +* @param element_id 返回下表使用的元素id +* @return +* @remark 无 +* @see +* @author cbb @date 2022/08/30 +************************************************************/ +DPP_STATUS dpp_dtb_se_zcam_dma_dump(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 addr, + ZXIC_UINT32 tb_width, + ZXIC_UINT32 depth, + ZXIC_UINT32 *p_data, + ZXIC_UINT32 *element_id) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_UINT32 dump_dst_phy_haddr = 0; + ZXIC_UINT32 dump_dst_phy_laddr = 0; + + ZXIC_UINT32 queue_item_index = 0; + ZXIC_UINT32 data_len = 0; + ZXIC_UINT32 desc_len = 0; + ZXIC_UINT32 tb_width_len = 0; + + ZXIC_UINT8 form_buff[DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DTB_QUEUE_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), tb_width, DTB_DUMP_ZCAM_128b, DTB_DUMP_ZCAM_RSV - 1); + ZXIC_COMM_CHECK_INDEX_LOWER(depth, 1); + + /*获取队列元素*/ + rc = dpp_dtb_tab_up_free_item_get(dev, queue_id, &queue_item_index); + if(rc != DPP_OK) + { + ZXIC_COMM_TRACE_ERROR("dpp_dtb_tab_up_free_item_get failed!\n"); + return DPP_RC_DTB_QUEUE_ITEM_SW_EMPTY; + } + + if(dpp_dtb_prt_get()) + { + ZXIC_COMM_PRINT("dump smmu0:queue %d,item_index: %d\n",queue_id, queue_item_index); + } + + *element_id = queue_item_index;//保存获取的item_index + + /*获取dump dma phy地址*/ + rc = dpp_dtb_tab_up_item_addr_get(dev, queue_id, queue_item_index, &dump_dst_phy_haddr, &dump_dst_phy_laddr); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_tab_up_item_addr_get"); + + rc = dpp_dtb_zcam_dump_info_write(dev, + addr, + tb_width, + depth, + dump_dst_phy_haddr, + dump_dst_phy_laddr, + (ZXIC_UINT32 *)form_buff); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_zcam_dump_info_write"); + + /*组装下表命令格式*/ + tb_width_len = DTB_LEN_POS_SETP << tb_width; + data_len = depth * tb_width_len / 4;//要提取的数据长度，以32bit为单位 + desc_len = DTB_LEN_POS_SETP / 4;//描述符长度，以32bit为单位 + + rc = dpp_dtb_write_dump_desc_info(dev, queue_id, queue_item_index, (ZXIC_UINT32 *)form_buff, data_len, desc_len, p_data); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_write_dump_desc_info"); + + return DPP_OK; + +} + +#endif + +#if ZXIC_REAL("DTB GET") +/***********************************************************/ +/** 配置数据获取模式 +* @param srh_mode 0:软件获取 1:硬件获取 +* @return +* @remark 无 +* @see +* @author cq @date 2023/08/02 +************************************************************/ +ZXIC_VOID dpp_dtb_srh_mode_set(ZXIC_UINT32 srh_mode) +{ + g_dtb_srh_mode = srh_mode; +} + +/***********************************************************/ +/** 获取查找方式 +* @param +* @return +* @remark 无 +* @see +* @author cq @date 2023/08/02 +************************************************************/ +ZXIC_UINT32 dpp_dtb_srh_mode_get(ZXIC_VOID) +{ + return g_dtb_srh_mode; +} + +/***********************************************************/ +/** hash表项查找校验(软件获取数据) +* @param p_entry 入参：hash表项键值 出参：hash表项结果 +* @param key_by_size 键值大小 +* @param rst_by_size 返回值大小 +* @param p_item_info 512bit单元数据 +* @return +* @remark 无 +* @see +* @author cq @date 2023/08/02 +************************************************************/ +DPP_STATUS dpp_dtb_hash_software_item_check(DPP_HASH_ENTRY *p_entry, + ZXIC_UINT32 key_by_size, + ZXIC_UINT32 rst_by_size, + SE_ITEM_CFG *p_item_info) +{ + ZXIC_UINT8 srh_succ = 0; + ZXIC_UINT8 temp_key_type = 0; + ZXIC_UINT8 srh_key_type = 0; + D_NODE *p_entry_dn = NULL; + DPP_HASH_RBKEY_INFO *p_rbkey = NULL; + + ZXIC_COMM_CHECK_INDEX(key_by_size, 0, HASH_KEY_MAX); + ZXIC_COMM_CHECK_POINT(p_entry); + ZXIC_COMM_CHECK_POINT(p_entry->p_key); + ZXIC_COMM_CHECK_POINT(p_entry->p_rst); + ZXIC_COMM_CHECK_POINT(p_item_info); + + srh_key_type = DPP_GET_HASH_KEY_TYPE(p_entry->p_key); + p_entry_dn = p_item_info->item_list.p_next; + while (p_entry_dn) + { + p_rbkey = (DPP_HASH_RBKEY_INFO *)p_entry_dn->data; + ZXIC_COMM_CHECK_POINT(p_rbkey); + ZXIC_COMM_CHECK_POINT(p_rbkey->key); + ZXIC_COMM_CHECK_POINT(p_rbkey->rst); + + ZXIC_COMM_ASSERT(p_rbkey->p_item_info == p_item_info); + + temp_key_type = DPP_GET_HASH_KEY_TYPE(p_rbkey->key); + + if (DPP_GET_HASH_KEY_VALID(p_rbkey->key) && (srh_key_type == temp_key_type)) + { + if (0 == ZXIC_COMM_MEMCMP(p_entry->p_key, p_rbkey->key, key_by_size)) + { + srh_succ = 1; + break; + } + } + + p_entry_dn = p_entry_dn->next; + } + + if (NULL == p_rbkey) + { + return ZXIC_PAR_CHK_POINT_NULL; + } + + if(!srh_succ) + { + ZXIC_COMM_TRACE_DEBUG("dpp_dtb_hash_software_item_check fail!\n"); + return DPP_HASH_RC_MATCH_ITEM_FAIL; + } + + /* copy result */ + ZXIC_COMM_MEMCPY(p_entry->p_rst, p_rbkey->rst, (rst_by_size > HASH_RST_MAX) ? HASH_RST_MAX : rst_by_size); + + return DPP_OK; +} + +/** hash表项解析，在512bit存储单元里查找并比对 +* @param item_type +* @param key_by_size 键值大小 +* @param p_entry 入参：hash表项键值 出参：hash表项结果 +* @param p_item_data 查找键值信息 +* @param p_data_offset 查找键值在512bit里的偏移位置,单位为字节 +* @return +* @remark 无 +* @see +* @author cq @date 2023/08/02 +************************************************************/ +ZXIC_UINT32 dpp_dtb_hash_data_parse(ZXIC_UINT32 item_type, + ZXIC_UINT32 key_by_size, + DPP_HASH_ENTRY *p_entry, + ZXIC_UINT8 *p_item_data, + ZXIC_UINT8 *p_data_offset) +{ + ZXIC_UINT32 data_offset = 0; + ZXIC_UINT8 temp_key_valid = 0; + ZXIC_UINT8 temp_key_type = 0; + ZXIC_UINT32 temp_entry_size = 0; + ZXIC_UINT8 srh_key_type = 0; + ZXIC_UINT32 srh_entry_size = 0; + ZXIC_UINT32 rst_by_size = 0; + ZXIC_UINT8 srh_succ = 0; + ZXIC_UINT32 item_width = SE_ITEM_WIDTH_MAX; + ZXIC_UINT8 *p_srh_key = NULL; + ZXIC_UINT8 *p_temp_key = NULL; + ZXIC_UINT32 i = 0; + + ZXIC_COMM_CHECK_POINT(p_item_data); + ZXIC_COMM_CHECK_POINT(p_entry); + ZXIC_COMM_CHECK_POINT(p_entry->p_key); + + if (ITEM_DDR_256 == item_type) + { + item_width = item_width / 2; + } + + p_temp_key = p_item_data; + p_srh_key = p_entry->p_key; + srh_key_type = DPP_GET_HASH_KEY_TYPE(p_srh_key); + srh_entry_size = DPP_GET_HASH_ENTRY_SIZE(srh_key_type); + + if(dpp_dtb_prt_get()) + { + ZXIC_COMM_PRINT("srh_key:0x"); + + for(i = 0; i < key_by_size; i++) + { + ZXIC_COMM_PRINT("%02x ", p_srh_key[i]); + } + ZXIC_COMM_PRINT("\n"); + } + + while (data_offset < item_width) + { + temp_key_valid = DPP_GET_HASH_KEY_VALID(p_temp_key); + temp_key_type = DPP_GET_HASH_KEY_TYPE(p_temp_key); + + if (temp_key_valid && (srh_key_type == temp_key_type)) + { + if (0 == ZXIC_COMM_MEMCMP(p_srh_key, p_temp_key, key_by_size)) + { + ZXIC_COMM_TRACE_DEBUG("Hash search hardware successfully. \n"); + srh_succ = 1; + break; + } + + data_offset += srh_entry_size; + } + else if (temp_key_valid && (srh_key_type != temp_key_type)) + { + temp_entry_size = DPP_GET_HASH_ENTRY_SIZE(temp_key_type); + ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(data_offset, temp_entry_size); + data_offset += temp_entry_size; + } + else + { + data_offset += 16;/* 偏移最小的步长128bit */ + } + + p_temp_key = p_item_data; + p_temp_key += data_offset; + } + + if(!srh_succ) + { + ZXIC_COMM_TRACE_DEBUG("Hash search hardware fail. \n"); + return DPP_HASH_RC_MATCH_ITEM_FAIL; + } + + /* copy result */ + rst_by_size = srh_entry_size - key_by_size; + ZXIC_COMM_MEMCPY(p_entry->p_rst, p_temp_key + key_by_size, (rst_by_size > HASH_RST_MAX) ? HASH_RST_MAX : rst_by_size); + *p_data_offset = data_offset; + + return DPP_OK; +} + +/***********************************************************/ +/** 查找存储在DDR空间的hash表项 +* @param dev_id 设备号，支持多芯片 +* @param queue_id 队列id +* @param p_hash_entry_cfg hash表项配置信息 +* @param p_hash_entry 查找键值信息 +* @param p_srh_succ 出参，查找是否成功 +* @return +* @remark 无 +* @see +* @author cq @date 2023/08/02 +************************************************************/ +ZXIC_UINT32 dpp_dtb_hash_ddr_get(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + HASH_ENTRY_CFG *p_hash_entry_cfg, + DPP_HASH_ENTRY *p_hash_entry, + ZXIC_UINT8 *p_srh_succ) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 item_idx = 0xFFFFFFFF;/* -1 */ + ZXIC_UINT32 item_type = 0; + ZXIC_UINT32 crc_value = 0; + ZXIC_UINT32 index = 0; + ZXIC_UINT32 index_offset = 0; + ZXIC_UINT32 hw_addr = 0; /*单位512bit*/ + ZXIC_UINT32 base_addr = 0; /*单位2k*256bit*/ + ZXIC_UINT32 ecc_en = 0; + ZXIC_UINT32 element_id = 0; + ZXIC_UINT32 byte_len = 0; + ZXIC_UINT8 byte_offset = 0; + ZXIC_UINT8 temp_key[HASH_KEY_MAX] = {0}; + HASH_DDR_CFG *p_ddr_cfg = NULL; + DPP_HASH_CFG *p_hash_cfg = NULL; + ZXIC_UINT32 rd_buff[DPP_DIR_TBL_BUF_MAX_NUM] = {0}; + ZXIC_UINT8 temp_data[DPP_DIR_TBL_BUF_MAX_NUM*4] = {0}; + SE_ITEM_CFG *p_item = NULL; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev),DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_INDEX(queue_id, 0, DTB_QUEUE_MAX - 1); + ZXIC_COMM_CHECK_POINT(p_hash_entry_cfg); + ZXIC_COMM_CHECK_POINT(p_hash_entry); + ZXIC_COMM_CHECK_POINT(p_srh_succ); + + ZXIC_COMM_MEMSET((ZXIC_UINT8 *)rd_buff,0x0,sizeof(rd_buff)); + ZXIC_COMM_MEMSET(temp_data,0x0,sizeof(temp_data)); + + rc = dpp_se_smmu1_hash_tbl_soft_cfg_get(dev, + p_hash_entry_cfg->fun_id, + p_hash_entry_cfg->bulk_id, + &ecc_en, + &base_addr); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_se_smmu1_hash_tbl_soft_cfg_get"); + + p_hash_cfg = p_hash_entry_cfg->p_hash_cfg; + ZXIC_COMM_CHECK_POINT(p_hash_cfg); + ZXIC_COMM_CHECK_INDEX_UPPER(p_hash_entry_cfg->bulk_id,HASH_BULK_ID_MAX); + p_ddr_cfg = p_hash_cfg->p_bulk_ddr_info[p_hash_entry_cfg->bulk_id]; + ZXIC_COMM_CHECK_POINT(p_ddr_cfg); + + ZXIC_COMM_CHECK_INDEX_UPPER(p_hash_entry_cfg->key_by_size, HASH_KEY_MAX); + rc = dpp_hash_set_crc_key(dev,p_hash_entry_cfg,p_hash_entry,temp_key); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev),rc,"hash_set_crc_key"); + + crc_value = p_hash_cfg->p_hash32_fun(temp_key, p_hash_entry_cfg->key_by_size, p_ddr_cfg->hash_ddr_arg); + item_idx = crc_value % p_ddr_cfg->item_num; + index = p_ddr_cfg->hw_baddr + item_idx; + if (DDR_WIDTH_512b == p_ddr_cfg->width_mode) + { + item_type = ITEM_DDR_512; + hw_addr = (base_addr<<10) + index; + index_offset = 0; + byte_len = 512/8; + } + else + { + item_type = ITEM_DDR_256; + hw_addr = (base_addr<<10) + (index>>1); + index_offset = index & 0x1; + byte_len = 256/8; + } + + ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev), + "Hash search in ITEM_DDR_%s, CRC32 index is: 0x%x.\n", ((item_type == ITEM_DDR_256) ? "256" : "512"), + item_idx); + if(dpp_dtb_srh_mode_get()) + { + rc = dpp_dtb_se_smmu1_dma_dump(dev, + queue_id, + hw_addr, + 1, + rd_buff, + &element_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,"dpp_dtb_se_smmu1_dma_dump"); + + zxic_comm_swap((ZXIC_UINT8 *)(rd_buff+index_offset*8), byte_len); + ZXIC_COMM_MEMCPY(temp_data, rd_buff+index_offset*8, byte_len); + + rc = dpp_dtb_hash_data_parse(item_type,p_hash_entry_cfg->key_by_size,p_hash_entry,temp_data,&byte_offset); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_dtb_hash_data_parse"); + + ZXIC_COMM_TRACE_DEBUG("Hash search hardware succ in ddr. \n"); + } + else + { + ZXIC_COMM_CHECK_INDEX_UPPER(item_idx, p_ddr_cfg->item_num - 1); + p_item = p_ddr_cfg->p_item_array[item_idx]; + ZXIC_COMM_CHECK_POINT_NO_ASSERT(p_item); + ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(DEV_ID(dev), p_ddr_cfg->hw_baddr, item_idx); + p_item->hw_addr = p_ddr_cfg->hw_baddr+item_idx; + p_item->item_type = item_type; + p_item->item_index = item_idx; + + rc = dpp_dtb_hash_software_item_check(p_hash_entry, + p_hash_entry_cfg->key_by_size, + p_hash_entry_cfg->rst_by_size, + p_item); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_hash_software_item_check"); + } + + *p_srh_succ = 1; + p_hash_cfg->hash_stat.search_ok++; + + return DPP_OK; +} + +/***********************************************************/ +/** 查找存储在ZCAM空间的hash表项 +* @param dev_id 设备号，支持多芯片 +* @param queue_id 队列id +* @param p_hash_entry_cfg hash表项配置信息 +* @param p_hash_entry 查找键值信息 +* @param p_srh_succ 出参，查找是否成功 +* @return +* @remark 无 +* @see +* @author cq @date 2023/08/02 +************************************************************/ +ZXIC_UINT32 dpp_dtb_hash_zcam_get(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + HASH_ENTRY_CFG *p_hash_entry_cfg, + DPP_HASH_ENTRY *p_hash_entry, + ZXIC_UINT8 *p_srh_succ) +{ + DPP_STATUS rc = DPP_OK; + DPP_HASH_RBKEY_INFO srh_rbkey = {0}; + ZXIC_RB_TN *p_rb_tn_rtn = NULL; + DPP_HASH_CFG *p_hash_cfg = NULL; + DPP_HASH_RBKEY_INFO *p_rbkey = NULL; + SE_ITEM_CFG *p_item = NULL; + ZXIC_UINT32 element_id = 0; + ZXIC_UINT8 rd_buff[SE_ITEM_WIDTH_MAX] = {0}; + ZXIC_UINT32 i = 0; + ZXIC_UINT8 byte_offset = 0; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev),DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_INDEX(queue_id, 0, DTB_QUEUE_MAX - 1); + ZXIC_COMM_CHECK_POINT(p_hash_entry_cfg); + ZXIC_COMM_CHECK_POINT(p_srh_succ); + ZXIC_COMM_CHECK_POINT(p_hash_entry); + ZXIC_COMM_CHECK_POINT(p_hash_entry->p_key); + ZXIC_COMM_CHECK_POINT(p_hash_entry->p_rst); + + ZXIC_COMM_MEMSET(rd_buff,0x0,sizeof(rd_buff)); + ZXIC_COMM_MEMSET(&srh_rbkey,0x0,sizeof(DPP_HASH_RBKEY_INFO)); + ZXIC_COMM_CHECK_INDEX_UPPER(p_hash_entry_cfg->key_by_size, HASH_KEY_MAX); + ZXIC_COMM_MEMCPY(srh_rbkey.key,p_hash_entry->p_key,p_hash_entry_cfg->key_by_size); + + p_hash_cfg = p_hash_entry_cfg->p_hash_cfg; + ZXIC_COMM_CHECK_POINT(p_hash_cfg); + + rc = zxic_comm_rb_search(&p_hash_cfg->hash_rb, (ZXIC_VOID *)&srh_rbkey, (ZXIC_VOID *)(&p_rb_tn_rtn)); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "zxic_comm_rb_search hash fail"); + ZXIC_COMM_CHECK_POINT(p_rb_tn_rtn); + p_rbkey = p_rb_tn_rtn->p_key; + + ZXIC_COMM_CHECK_POINT(p_rbkey); + p_item = p_rbkey->p_item_info; + ZXIC_COMM_CHECK_POINT(p_item); + + if(dpp_dtb_srh_mode_get()) + { + rc = dpp_dtb_se_zcam_dma_dump(dev, queue_id, p_item->hw_addr, DTB_DUMP_ZCAM_512b, 1,(ZXIC_UINT32 *)rd_buff, &element_id); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_se_zcam_dma_dump"); + zxic_comm_swap(rd_buff,sizeof(rd_buff)); + + if(dpp_dtb_prt_get()) + { + ZXIC_COMM_PRINT("dump data:\n"); + + for(i = 0; i < SE_ITEM_WIDTH_MAX; i++) + { + ZXIC_COMM_PRINT("%02x ", rd_buff[i]); + if((i + 1) % 16 == 0) + { + ZXIC_COMM_PRINT("\n"); + } + } + ZXIC_COMM_PRINT("\n"); + } + + rc = dpp_dtb_hash_data_parse(ITEM_RAM,p_hash_entry_cfg->key_by_size,p_hash_entry,rd_buff,&byte_offset); + if(DPP_OK == rc) + { + ZXIC_COMM_TRACE_DEBUG("Hash search hardware succ in zcam. \n"); + *p_srh_succ = 1; + p_hash_cfg->hash_stat.search_ok++; + } + else + { + ZXIC_COMM_TRACE_DEBUG("Hash search hardware fail in zcam. \n"); + } + } + else + { + rc = dpp_dtb_hash_software_item_check(p_hash_entry, + p_hash_entry_cfg->key_by_size, + p_hash_entry_cfg->rst_by_size, + p_item); + if(DPP_OK == rc) + { + ZXIC_COMM_TRACE_DEBUG("Hash search software succ in zcell. \n"); + *p_srh_succ = 1; + p_hash_cfg->hash_stat.search_ok++; + } + } + + return DPP_OK; + +} + + +/** dtb根据etcam key计算dump出数据占用的数据长度 +* @param dev_id 设备号 +* @param etcam_key_mode etcam条目位宽，参照DPP_ETCAM_ENTRY_MODE_E定义 +* @param p_etcam_dump_len dtb dump出etcam的数据长度(单位:字节) +* @param p_etcam_dump_inerval dump出etcam数据的间隔数据长度(单位：字节) +* @return +* @remark 无 +* @see +* @author cbb @date 2022/08/30 +************************************************************/ +DPP_STATUS dtb_etcam_dump_data_len(DPP_DEV_T *dev, + ZXIC_UINT32 etcam_key_mode, + ZXIC_UINT32 *p_etcam_dump_len, + ZXIC_UINT32* p_etcam_dump_inerval) +{ + ZXIC_UINT32 dump_data_len = 0; + ZXIC_UINT8 etcam_dump_inerval = 0; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_etcam_dump_len); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_etcam_dump_inerval); + + if(DPP_ETCAM_KEY_640b == etcam_key_mode) + { + dump_data_len = 5 * DTB_LEN_POS_SETP; + etcam_dump_inerval = 0; + } + else if(DPP_ETCAM_KEY_320b == etcam_key_mode) + { + dump_data_len = 3 * DTB_LEN_POS_SETP; + etcam_dump_inerval = 8; + } + else if(DPP_ETCAM_KEY_160b == etcam_key_mode) + { + dump_data_len = 2 * DTB_LEN_POS_SETP; + etcam_dump_inerval = 12; + } + else if(DPP_ETCAM_KEY_80b == etcam_key_mode) + { + dump_data_len = 1 * DTB_LEN_POS_SETP; + etcam_dump_inerval = 6; + } + + *p_etcam_dump_len = dump_data_len; + *p_etcam_dump_inerval = etcam_dump_inerval; + + return DPP_OK; +} + +/** dtb 从dump数据中提取到xy数据 +* @param dev_id 设备号 +* @param p_data dump出的etcam data 指针 +* @param p_mask dump出的etcam mask 指针 +* @param p_etcam_dump_len dtb dump出etcam的数据长度(单位:字节) +* @param p_etcam_dump_inerval dump出etcam数据的间隔数据长度(单位：字节) +* @param p_entry_xy 保存etcam xy数据（已分配内存） +* @return +* @remark 无 +* @see +* @author cbb @date 2022/08/30 +************************************************************/ +DPP_STATUS dpp_dtb_get_etcam_xy_from_dump_data(DPP_DEV_T *dev, + ZXIC_UINT8 *p_data, + ZXIC_UINT8 *p_mask, + ZXIC_UINT32 etcam_dump_len, + ZXIC_UINT32 etcam_dump_inerval, + DPP_ETCAM_ENTRY_T *p_entry_xy) +{ + ZXIC_UINT8 *p_entry_data = NULL; + ZXIC_UINT8 *p_entry_mask = NULL; + + //先对数据进行翻转再进行数据的截取，最后进行数据的复制 + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_mask); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_entry_xy); + + zxic_comm_swap(p_data, etcam_dump_len); + zxic_comm_swap(p_mask, etcam_dump_len); + + p_entry_data = p_data + etcam_dump_inerval; + p_entry_mask = p_mask + etcam_dump_inerval; + + ZXIC_COMM_MEMCPY(p_entry_xy->p_data, p_entry_data, DPP_ETCAM_ENTRY_SIZE_GET(p_entry_xy->mode)); + ZXIC_COMM_MEMCPY(p_entry_xy->p_mask, p_entry_mask, DPP_ETCAM_ENTRY_SIZE_GET(p_entry_xy->mode)); + + return DPP_OK; +} + +/** dtb dump etcam直接表表项内容 级联eram支持64bit/128bit +* @param dev_id 设备号 +* @param p_in_data 长度为640bit的输入数据 +* @param rd_mode 读模式 +* @param p_out_data 按照读模式读出的数据 +* @return +* @remark 无 +* @see +* @author cbb @date 2022/08/30 +************************************************************/ +DPP_STATUS dpp_dtb_etcam_ind_data_get(DPP_DEV_T *dev, ZXIC_UINT8 *p_in_data, ZXIC_UINT32 rd_mode, ZXIC_UINT8 *p_out_data) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_UINT32 i = 0; + ZXIC_UINT8 *p_temp = NULL; + ZXIC_UINT32 offset = 0; + ZXIC_UINT8 buff[DPP_ETCAM_WIDTH_MAX / 8] = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_in_data); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_out_data); + + p_temp = p_out_data; + ZXIC_COMM_MEMCPY(buff, p_in_data, DPP_ETCAM_WIDTH_MAX / 8); + + zxic_comm_swap(buff, DPP_ETCAM_WIDTH_MAX / 8); + + for (i = 0; i < DPP_ETCAM_RAM_NUM; i++) + { + offset = i * (DPP_ETCAM_WIDTH_MIN / 8); + + if ((rd_mode >> (DPP_ETCAM_RAM_NUM - 1 - i)) & 0x1) + { + ZXIC_COMM_MEMCPY(p_temp, buff + offset, DPP_ETCAM_WIDTH_MIN / 8); + p_temp += DPP_ETCAM_WIDTH_MIN / 8; + } + } + + return rc; +} + +/** dtb dump etcam表项内容 +* @param dev_id 设备号 +* @param queue_id 队列号 +* @param block_idx block的索引，范围0-7 +* @param addr 单个block中的RAM地址，范围0~511 +* @param rd_mode 读block RAM行的位图，共8bit，每比特表示一个RAM中的80bit +* @param opr_type 读取的数据类型，0:data/mask格式，1：xy格式 +* @param as_en 级联eram使能 +* @param as_eram_baddr 级联eram基地址 +* @param as_eram_index 级联eram 条目index +* @param as_rsp_mode 级联返回位宽，参见DPP_DIAG_ERAM_MODE_E +* @param p_entry 读取的etcam数据 +* @param p_as_rslt 读取的级联数据(分配128bit存储空间) +* @return +* @remark 无 +* @see +* @author cbb @date 2022/08/30 +************************************************************/ +DPP_STATUS dpp_dtb_etcam_entry_get(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 block_idx, + ZXIC_UINT32 addr, + ZXIC_UINT32 rd_mode, + ZXIC_UINT32 opr_type, + ZXIC_UINT32 as_en, + ZXIC_UINT32 as_eram_baddr, + ZXIC_UINT32 as_eram_index, + ZXIC_UINT32 as_rsp_mode,//128:3 64:2 + DPP_ETCAM_ENTRY_T *p_entry, + ZXIC_UINT8 *p_as_rslt) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_UINT32 etcam_key_mode = 0; + + ZXIC_UINT8 temp_data[DPP_ETCAM_WIDTH_MAX / 8] = {0}; + ZXIC_UINT8 temp_mask[DPP_ETCAM_WIDTH_MAX / 8] = {0}; + DPP_ETCAM_ENTRY_T entry_xy = {0}; + + ZXIC_UINT32 etcam_data_dst_phy_haddr = 0; + ZXIC_UINT32 etcam_data_dst_phy_laddr = 0; + ZXIC_UINT32 etcam_mask_dst_phy_haddr = 0; + ZXIC_UINT32 etcam_mask_dst_phy_laddr = 0; + ZXIC_UINT32 as_rst_dst_phy_haddr = 0; + ZXIC_UINT32 as_rst_dst_phy_laddr = 0; + + ZXIC_UINT32 dump_element_id = 0; + ZXIC_UINT32 etcam_dump_one_data_len = 0; + ZXIC_UINT32 etcam_dump_inerval = 0; + ZXIC_UINT32 dtb_desc_addr_offset = 0; + ZXIC_UINT32 dump_data_len = 0; + ZXIC_UINT32 dtb_desc_len = 0; + + ZXIC_UINT32 eram_dump_base_addr = 0; + ZXIC_UINT32 row_index = 0; + ZXIC_UINT32 col_index = 0; + + ZXIC_UINT8 *p_data = NULL; + ZXIC_UINT8 *p_mask = NULL; + ZXIC_UINT8 *p_rst = NULL; + ZXIC_UINT8 *temp_dump_out_data = NULL; + ZXIC_UINT8 *dump_info_buff = NULL; + ETCAM_DUMP_INFO_T etcam_dump_info = {0}; + DPP_DTB_ENTRY_T dtb_dump_entry = {0}; + ZXIC_UINT8 cmd_buff[DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), addr, 0, DPP_ETCAM_RAM_DEPTH - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), block_idx, 0, DPP_ETCAM_BLOCK_NUM - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), rd_mode, 0, DPP_ETCAM_WR_MASK_MAX); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), opr_type, DPP_ETCAM_OPR_DM, DPP_ETCAM_OPR_XY); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_entry); + + dump_info_buff = (ZXIC_UINT8 *) ZXIC_COMM_MALLOC(DPP_DTB_TABLE_DUMP_INFO_BUFF_SIZE * sizeof(ZXIC_UINT8)); + ZXIC_COMM_CHECK_POINT_NO_ASSERT(dump_info_buff); + ZXIC_COMM_MEMSET(dump_info_buff, 0, DPP_DTB_TABLE_DUMP_INFO_BUFF_SIZE * sizeof(ZXIC_UINT8)); + + dtb_dump_entry.cmd = cmd_buff; + + entry_xy.p_data = temp_data; + entry_xy.p_mask = temp_mask; + + etcam_key_mode = p_entry->mode; + + etcam_dump_info.block_sel = block_idx; + etcam_dump_info.addr = addr; + etcam_dump_info.tb_width = 3 - etcam_key_mode; + etcam_dump_info.rd_mode = rd_mode; + etcam_dump_info.tb_depth = 1; + + rc = dpp_dtb_tab_up_free_item_get(dev, queue_id, &dump_element_id); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_tab_up_free_item_get", dump_info_buff); + ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev), "table up item queue_element_id is: %d.\n",dump_element_id); + + if(dpp_dtb_prt_get()) + { + ZXIC_COMM_PRINT("dump etcam:queue %d,element id: %d\n",queue_id, dump_element_id); + } + + rc = dtb_etcam_dump_data_len(dev, etcam_key_mode, &etcam_dump_one_data_len, &etcam_dump_inerval); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dtb_etcam_dump_data_len", dump_info_buff); + + //etcam data dump描述符 + etcam_dump_info.data_or_mask = DPP_ETCAM_DTYPE_DATA; + rc = dpp_dtb_tab_up_item_offset_addr_get(dev, + queue_id, + dump_element_id, + dump_data_len, + &etcam_data_dst_phy_haddr, + &etcam_data_dst_phy_laddr); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_tab_up_item_offset_addr_get", dump_info_buff); + rc = dpp_dtb_etcam_dump_entry(dev, + &etcam_dump_info, + etcam_data_dst_phy_haddr, + etcam_data_dst_phy_laddr, + &dtb_dump_entry); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_etcam_dump_entry", dump_info_buff); + + rc = dpp_dtb_data_write(dump_info_buff, dtb_desc_addr_offset, &dtb_dump_entry); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_data_write", dump_info_buff); + ZXIC_COMM_MEMSET(cmd_buff, 0, DTB_TABLE_CMD_SIZE_BIT / 8); + dtb_desc_len += 1; + dtb_desc_addr_offset += DTB_LEN_POS_SETP; + dump_data_len += etcam_dump_one_data_len; + + //etcam mask dump描述符 + etcam_dump_info.data_or_mask = DPP_ETCAM_DTYPE_MASK; + rc = dpp_dtb_tab_up_item_offset_addr_get(dev, + queue_id, + dump_element_id, + dump_data_len, + &etcam_mask_dst_phy_haddr, + &etcam_mask_dst_phy_laddr); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_tab_up_item_offset_addr_get", dump_info_buff); + rc = dpp_dtb_etcam_dump_entry(dev, + &etcam_dump_info, + etcam_mask_dst_phy_haddr, + etcam_mask_dst_phy_laddr, + &dtb_dump_entry); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_etcam_dump_entry", dump_info_buff); + rc = dpp_dtb_data_write(dump_info_buff, dtb_desc_addr_offset, &dtb_dump_entry); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_data_write", dump_info_buff); + ZXIC_COMM_MEMSET(cmd_buff, 0, DTB_TABLE_CMD_SIZE_BIT / 8); + dtb_desc_len += 1; + dtb_desc_addr_offset += DTB_LEN_POS_SETP; + dump_data_len += etcam_dump_one_data_len; + + //级联数据dump描述符生成 + if(as_en) + { + rc = dtb_eram_index_cal(dev, as_rsp_mode, as_eram_index, &row_index, &col_index); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dtb_eram_index_cal", dump_info_buff); + + eram_dump_base_addr = as_eram_baddr + row_index; + ZXIC_COMM_TRACE_INFO("eram_dump_base_addr : 0x%x\n",eram_dump_base_addr); + rc = dpp_dtb_tab_up_item_offset_addr_get(dev, + queue_id, + dump_element_id, + dump_data_len, + &as_rst_dst_phy_haddr, + &as_rst_dst_phy_laddr); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_tab_up_item_offset_addr_get", dump_info_buff); + + rc = dpp_dtb_smmu0_dump_entry(dev, + eram_dump_base_addr, + 1, + as_rst_dst_phy_haddr, + as_rst_dst_phy_laddr, + &dtb_dump_entry); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_smmu0_dump_entry", dump_info_buff); + rc = dpp_dtb_data_write(dump_info_buff, dtb_desc_addr_offset, &dtb_dump_entry); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_data_write", dump_info_buff); + ZXIC_COMM_MEMSET(cmd_buff, 0, DTB_TABLE_CMD_SIZE_BIT / 8); + dtb_desc_len += 1; + dtb_desc_addr_offset += DTB_LEN_POS_SETP; + dump_data_len += DTB_LEN_POS_SETP; + } + + //申请data空间 + temp_dump_out_data = (ZXIC_UINT8 *) ZXIC_COMM_MALLOC(dump_data_len * sizeof(ZXIC_UINT8)); + ZXIC_COMM_CHECK_POINT_MEMORY_FREE_NO_ASSERT(temp_dump_out_data, dump_info_buff); + ZXIC_COMM_MEMSET(temp_dump_out_data, 0, dump_data_len * sizeof(ZXIC_UINT8)); + p_data = temp_dump_out_data; + /*下发dump描述符*/ + rc = dpp_dtb_write_dump_desc_info(dev, + queue_id, + dump_element_id, + (ZXIC_UINT32 *)dump_info_buff, + dump_data_len / 4, + dtb_desc_len * 4, + (ZXIC_UINT32 *)temp_dump_out_data); + ZXIC_COMM_CHECK_RC_MEMORY_FREE2PTR_NO_ASSERT(rc,"dpp_dtb_write_dump_desc_info", dump_info_buff, temp_dump_out_data); + + //解析数据 + p_data = temp_dump_out_data; + p_mask = p_data + etcam_dump_one_data_len; + + rc = dpp_dtb_get_etcam_xy_from_dump_data(dev, + p_data, + p_mask, + etcam_dump_one_data_len, + etcam_dump_inerval, + &entry_xy); + ZXIC_COMM_CHECK_RC_MEMORY_FREE2PTR_NO_ASSERT(rc, "dpp_dtb_get_etcam_xy_from_dump_data", dump_info_buff, temp_dump_out_data); + + if (opr_type == DPP_ETCAM_OPR_DM) + { + /* convert hardware data X/Y to user D/M */ + rc = dpp_etcam_xy_to_dm(p_entry, &entry_xy, DPP_ETCAM_ENTRY_SIZE_GET(p_entry->mode)); + ZXIC_COMM_CHECK_RC_MEMORY_FREE2PTR_NO_ASSERT(rc, "dpp_etcam_xy_to_dm", dump_info_buff, temp_dump_out_data); + } + else + { + ZXIC_COMM_MEMCPY(p_entry->p_data, entry_xy.p_data, DPP_ETCAM_ENTRY_SIZE_GET(p_entry->mode)); + ZXIC_COMM_MEMCPY(p_entry->p_mask, entry_xy.p_mask, DPP_ETCAM_ENTRY_SIZE_GET(p_entry->mode)); + } + + if(as_en) + { + //解析dump数据 + p_rst = p_mask + etcam_dump_one_data_len; + ZXIC_COMM_MEMCPY(p_as_rslt, p_rst, (128 / 8)); + } + + ZXIC_COMM_FREE(dump_info_buff); + ZXIC_COMM_FREE(temp_dump_out_data); + + return rc; +} +#endif + +#if ZXIC_REAL("DTB GET INTERFACE") +/** dtb dump eram直接表表项内容 +* @param dev_id 设备号 +* @param queue_id 队列号 +* @param sdt_no eram表sdt表号 +* @param p_dump_eram_entry eram数据结构，数据已分配相应内存 +* @return +* @remark 无 +* @see +* @author cbb @date 2022/08/30 +************************************************************/ +DPP_STATUS dpp_dtb_eram_data_get(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 sdt_no, + DPP_DTB_ERAM_ENTRY_INFO_T *p_dump_eram_entry) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 rd_mode = 0; + ZXIC_UINT32 eram_base_addr = 0; + ZXIC_UINT32 eram_table_depth = 0; + ZXIC_UINT32 eram_dump_base_addr = 0; + ZXIC_UINT32 row_index = 0; + ZXIC_UINT32 col_index = 0; + ZXIC_UINT32 temp_data[4] = {0}; + ZXIC_UINT32 element_id = 0; + + ZXIC_UINT32 index = p_dump_eram_entry->index; + ZXIC_UINT32 *p_data = p_dump_eram_entry->p_data; + + DPP_SDTTBL_ERAM_T sdt_eram_info = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DTB_QUEUE_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1); + + //从sdt_no中获取SDT配置 + rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_eram_info); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_soft_sdt_tbl_get"); + eram_base_addr = sdt_eram_info.eram_base_addr; + rd_mode = sdt_eram_info.eram_mode;//0:1bit;2:64bit;3:128, + eram_table_depth = sdt_eram_info.eram_table_depth; + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), index, 0, eram_table_depth - 1); + + rc = dtb_eram_index_cal(dev, rd_mode, index, &row_index, &col_index); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dtb_eram_index_cal"); + + eram_dump_base_addr = eram_base_addr + row_index; + + rc = dpp_dtb_se_smmu0_dma_dump(dev, + queue_id, + eram_dump_base_addr, + 1, + temp_data, + &element_id); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_se_smmu0_dma_dump"); + if(dpp_dtb_prt_get()) + { + ZXIC_COMM_PRINT("dtb dump eram done, the element id is %d.\n", element_id); + } + + //提取数据 + switch (rd_mode) + { + case ERAM128_TBL_128b: + { + ZXIC_COMM_MEMCPY(p_data, temp_data, (128 / 8)); + break; + } + + case ERAM128_TBL_64b: + { + ZXIC_COMM_MEMCPY(p_data, temp_data + ((1 - col_index) << 1), (64 / 8)); + break; + } + + case ERAM128_TBL_1b: + { + ZXIC_COMM_UINT32_GET_BITS(p_data[0], *(temp_data + (3 - col_index / 32)), (col_index % 32), 1); + break; + } + } + + return rc; + +} + +/** dtb dump eram直接表表项内容 +* @param dev_id 设备号 +* @param queue_id 队列号 +* @param sdt_no eram表sdt表号 +* @param p_dump_eram_entry eram数据结构，数据已分配相应内存 +* @return +* @remark 无 +* @see +* @author cbb @date 2022/08/30 +************************************************************/ +DPP_STATUS dpp_dtb_eram_stat_data_get(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 base_addr, + ZXIC_UINT32 rd_mode, + ZXIC_UINT32 index, + ZXIC_UINT32 *p_data) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 eram_dump_base_addr = 0; + ZXIC_UINT32 row_index = 0; + ZXIC_UINT32 col_index = 0; + ZXIC_UINT32 temp_data[4] = {0}; + ZXIC_UINT32 element_id = 0; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev),p_data); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DTB_QUEUE_MAX - 1); + + rc = dtb_eram_index_cal(dev, rd_mode, index, &row_index, &col_index); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dtb_eram_index_cal"); + + eram_dump_base_addr = base_addr + row_index; + + rc = dpp_dtb_se_smmu0_dma_dump(dev, + queue_id, + eram_dump_base_addr, + 1, + temp_data, + &element_id); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_se_smmu0_dma_dump"); + if(dpp_dtb_prt_get()) + { + ZXIC_COMM_PRINT("dtb dump eram done, the element id is %d.\n", element_id); + } + + //提取数据 + switch (rd_mode) + { + case ERAM128_TBL_128b: + { + ZXIC_COMM_MEMCPY(p_data, temp_data, (128 / 8)); + break; + } + + case ERAM128_TBL_64b: + { + ZXIC_COMM_MEMCPY(p_data, temp_data + ((1 - col_index) << 1), (64 / 8)); + break; + } + + case ERAM128_TBL_1b: + { + ZXIC_COMM_UINT32_GET_BITS(p_data[0], *(temp_data + (3 - col_index / 32)), (col_index % 32), 1); + break; + } + } + + return rc; +} + +/** dtb dump ddr直接表表项内容 +* @param dev_id 设备号 +* @param queue_id 队列号 +* @param sdt_no eram表sdt表号 +* @param p_dump_ddr_entry ddr 数据结构，数据已分配相应内存 +* @return +* @remark 无 +* @see +* @author cbb @date 2022/08/30 +************************************************************/ +DPP_STATUS dpp_dtb_ddr_data_get(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 sdt_no, + DPP_DTB_DDR_ENTRY_INFO_T *p_dump_ddr_entry) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 rd_mode = 0; + ZXIC_UINT32 ddr_base_addr = 0; + ZXIC_UINT32 ddr_dump_base_addr_512bit = 0; + ZXIC_UINT32 row_index = 0; + ZXIC_UINT32 col_index = 0; + ZXIC_UINT32 rd_buff[DPP_DIR_TBL_BUF_MAX_NUM] = {0}; + ZXIC_UINT32 element_id = 0; + + ZXIC_UINT32 index = p_dump_ddr_entry->index; + ZXIC_UINT32 *p_data = p_dump_ddr_entry->p_data; + + DPP_SDTTBL_DDR3_T sdt_ddr_info = {0}; /*SDT内容*/ + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_POINT(p_dump_ddr_entry); + + //从sdt_no中获取SDT配置 + rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_ddr_info); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_soft_sdt_tbl_get"); + ddr_base_addr = sdt_ddr_info.ddr3_base_addr; + ZXIC_COMM_CHECK_INDEX_UPPER(ddr_base_addr,DPP_SMMU1_TOTAL_MAX_BADDR); + rd_mode = sdt_ddr_info.ddr3_rw_len; + + if(SMMU1_DDR_SRH_128b == rd_mode) + { + row_index = index >> 2; + col_index = ((index & 0x3)) << 2; + } + else if(SMMU1_DDR_SRH_256b == rd_mode) + { + row_index = index >> 1; + col_index = ((index & 0x1)) << 3; + } + else if(SMMU1_DDR_SRH_512b == rd_mode) + { + row_index = index; + col_index = 0; + } + + ddr_dump_base_addr_512bit = (ddr_base_addr << 10) + row_index;/**转换成512bit为单位的地址*/ + + rc = dpp_dtb_se_smmu1_dma_dump(dev, + queue_id, + ddr_dump_base_addr_512bit, + 1, + rd_buff, + &element_id); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc,"dpp_dtb_se_smmu1_dma_dump"); + + if(dpp_dtb_prt_get()) + { + ZXIC_COMM_PRINT("dump ddr done ,the element is is %d\n",element_id); + } + + ZXIC_COMM_MEMCPY((ZXIC_UINT8 *)p_data, rd_buff+col_index, DTB_LEN_POS_SETP << rd_mode); + + return rc; +} + + +/** 根据键值查找hash表 +* @param dev_id 设备号，支持多芯片 +* @param queue_id 队列id +* @param sdt_no 0~255 +* @param p_dtb_hash_entry 出参，返回描述符信息 +* @return +* @remark 无 +* @see +* @author cq @date 2023/08/02 +************************************************************/ +ZXIC_UINT32 dpp_dtb_hash_data_get(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 sdt_no, + DPP_DTB_HASH_ENTRY_INFO_T *p_dtb_hash_entry) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT8 srh_succ = 0; + ZXIC_UINT8 key_valid = 1; + DPP_SE_CFG *p_se_cfg = NULL; + FUNC_ID_INFO *p_func_info = NULL; + DPP_HASH_CFG *p_hash_cfg = NULL; + HASH_ENTRY_CFG hash_entry_cfg = {0}; + DPP_SDTTBL_HASH_T sdt_hash_info = {0}; /*SDT内容*/ + DPP_HASH_ENTRY hash_entry = {0}; + ZXIC_UINT8 aucKey[HASH_KEY_MAX] = {0}; + ZXIC_UINT8 aucRst[HASH_RST_MAX] = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_INDEX(queue_id, 0, DTB_QUEUE_MAX - 1); + ZXIC_COMM_CHECK_INDEX(sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1); + ZXIC_COMM_CHECK_POINT(p_dtb_hash_entry); + ZXIC_COMM_CHECK_POINT(p_dtb_hash_entry->p_actu_key); + ZXIC_COMM_CHECK_POINT(p_dtb_hash_entry->p_rst); + + ZXIC_COMM_MEMSET(&hash_entry,0x0,sizeof(DPP_HASH_ENTRY)); + + //从sdt_no中获取SDT配置 + rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_hash_info); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_soft_sdt_tbl_get"); + + hash_entry_cfg.fun_id = sdt_hash_info.hash_id; /*hash引擎*/ + hash_entry_cfg.table_id = sdt_hash_info.hash_table_id; /*hash表号*/ + hash_entry_cfg.bulk_id = ((hash_entry_cfg.table_id >> 2) & 0x7); + hash_entry_cfg.key_type = sdt_hash_info.hash_table_width; /*表宽度*/ + hash_entry_cfg.actu_key_size = sdt_hash_info.key_size; /*业务表键值长度*/ + hash_entry_cfg.key_by_size = DPP_GET_KEY_SIZE(hash_entry_cfg.actu_key_size); + hash_entry_cfg.rst_by_size = DPP_GET_RST_SIZE(hash_entry_cfg.key_type, hash_entry_cfg.actu_key_size); + + /* 取出se配置 */ + rc = dpp_se_cfg_get(DEV_ID(dev), &p_se_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_se_cfg_get"); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_se_cfg); + p_func_info = DPP_GET_FUN_INFO(p_se_cfg, hash_entry_cfg.fun_id); + DPP_SE_CHECK_FUN(p_func_info, hash_entry_cfg.fun_id, FUN_HASH); + hash_entry_cfg.p_hash_cfg = (DPP_HASH_CFG *)p_func_info->fun_ptr; + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), hash_entry_cfg.p_hash_cfg); + p_hash_cfg = hash_entry_cfg.p_hash_cfg; + ZXIC_COMM_CHECK_POINT(p_hash_cfg); + + hash_entry.p_key = aucKey; + hash_entry.p_rst = aucRst; + ZXIC_COMM_MEMSET(hash_entry.p_key,0x0,sizeof(aucKey)); + ZXIC_COMM_MEMSET(hash_entry.p_rst,0x0,sizeof(aucRst)); + hash_entry.p_key[0] = DPP_GET_HASH_KEY_CTRL(key_valid, + hash_entry_cfg.key_type, + hash_entry_cfg.table_id); + ZXIC_COMM_MEMCPY(&hash_entry.p_key[1],p_dtb_hash_entry->p_actu_key,hash_entry_cfg.actu_key_size); + + if(p_hash_cfg->ddr_valid) + { + rc = dpp_dtb_hash_ddr_get(dev,queue_id,&hash_entry_cfg,&hash_entry,&srh_succ); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_dtb_hash_ddr_get"); + } + + if(!srh_succ) + { + rc = dpp_dtb_hash_zcam_get(dev,queue_id,&hash_entry_cfg,&hash_entry,&srh_succ); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_dtb_hash_zcam_get"); + } + + if(!srh_succ) + { + p_hash_cfg->hash_stat.search_fail++; + ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev), "Hash search key fail!\n"); + return DPP_HASH_RC_SRH_FAIL; + } + + ZXIC_COMM_MEMCPY(p_dtb_hash_entry->p_rst,hash_entry.p_rst,1<<(sdt_hash_info.rsp_mode + 2)); + + return DPP_OK; +} + +/** dtb 通过key和mask获取ACL表级联结果 +* @param dev_id 设备号 +* @param queue_id 队列号 +* @param sdt_no eram表sdt表号 +* @param p_dump_acl_entry etcam 数据结构，数据已分配相应内存,需要输入key和mask +* @return +* @remark 无 +* @see +* @author cbb @date 2022/08/30 +************************************************************/ +DPP_STATUS dpp_dtb_acl_data_get(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 sdt_no, + DPP_DTB_ACL_ENTRY_INFO_T *p_dump_acl_entry) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_UINT32 block_idx = 0; + ZXIC_UINT32 ram_addr = 0; + ZXIC_UINT32 etcam_wr_mode = 0; + + ZXIC_UINT32 etcam_key_mode = 0; + ZXIC_UINT32 etcam_table_id = 0; + ZXIC_UINT32 as_enable = 0; + ZXIC_UINT32 as_eram_baddr = 0; + ZXIC_UINT32 etcam_as_mode = 0; + + ZXIC_UINT32 row_index = 0; + ZXIC_UINT32 col_index = 0; + + DPP_ETCAM_ENTRY_T etcam_entry_dm = {0}; + DPP_ETCAM_ENTRY_T etcam_entry_xy = {0}; + ZXIC_UINT32 as_eram_data[4] = {0}; + ZXIC_UINT8 temp_data[DPP_ETCAM_WIDTH_MAX / 8] = {0}; + ZXIC_UINT8 temp_mask[DPP_ETCAM_WIDTH_MAX / 8] = {0}; + + DPP_ACL_CFG_EX_T *p_acl_cfg = NULL; + DPP_ACL_TBL_CFG_T *p_tbl_cfg = NULL; + + DPP_SDTTBL_ETCAM_T sdt_etcam_info = {0}; /*SDT内容*/ + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_dump_acl_entry); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_dump_acl_entry->key_data); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_dump_acl_entry->key_mask); + + //从sdt_no中获取SDT配置 + rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_etcam_info); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_soft_sdt_tbl_get"); + etcam_key_mode = sdt_etcam_info.etcam_key_mode; + etcam_as_mode = sdt_etcam_info.as_rsp_mode; + etcam_table_id = sdt_etcam_info.etcam_table_id; + as_enable = sdt_etcam_info.as_en; + as_eram_baddr = sdt_etcam_info.as_eram_baddr; + + if(as_enable) + { + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_dump_acl_entry->p_as_rslt); + } + + etcam_entry_xy.mode = etcam_key_mode; + etcam_entry_xy.p_data = temp_data; + etcam_entry_xy.p_mask = temp_mask; + etcam_entry_dm.mode = etcam_key_mode; + etcam_entry_dm.p_data = p_dump_acl_entry->key_data; + etcam_entry_dm.p_mask = p_dump_acl_entry->key_mask; + + if(dpp_dtb_prt_get()) + { + ZXIC_COMM_PRINT("acl get DM:/n"); + dpp_acl_data_print(etcam_entry_dm.p_data, etcam_entry_dm.p_mask, etcam_entry_dm.mode); + } + + dpp_acl_cfg_get(&p_acl_cfg);//获取ACL表资源配置 + ZXIC_COMM_CHECK_POINT(p_acl_cfg); + + p_tbl_cfg = p_acl_cfg->acl_tbls + etcam_table_id;//得到该acl表的资源配置 + + if (!p_tbl_cfg->is_used) + { + ZXIC_COMM_TRACE_ERROR("table[ %d ] is not init!\n", etcam_table_id); + ZXIC_COMM_ASSERT(0); + return DPP_ACL_RC_TBL_NOT_INIT; + } + + /*计算地址等信息*/ + rc = dpp_acl_hdw_addr_get(p_tbl_cfg, p_dump_acl_entry->handle, &block_idx, &ram_addr, &etcam_wr_mode); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_acl_hdw_addr_get"); + + rc = dpp_dtb_etcam_entry_get(dev, + queue_id, + block_idx, + ram_addr, + etcam_wr_mode, + DPP_ETCAM_OPR_XY, + as_enable, + as_eram_baddr, + p_dump_acl_entry->handle, + etcam_as_mode,//128:3 64:2 + &etcam_entry_xy, + (ZXIC_UINT8 *)as_eram_data); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_etcam_entry_get"); + + if (dpp_etcam_entry_cmp(&etcam_entry_dm, &etcam_entry_xy) == 0) + { + ZXIC_COMM_PRINT("Acl table[ %d ] search in hardware success: handle[ 0x%x ], block[ %d ], ram_addr[ %d ], rd_mode[ %x ].\n", + p_tbl_cfg->table_id, p_dump_acl_entry->handle, block_idx, ram_addr, etcam_wr_mode); + } + else + { + ZXIC_COMM_PRINT("Acl table[ %d ] search in hardware fail: handle[ 0x%x ], block[ %d ], ram_addr[ %d ], rd_mode[ %x ].\n", + p_tbl_cfg->table_id, p_dump_acl_entry->handle, block_idx, ram_addr, etcam_wr_mode); + + return DPP_ERR; + } + + if(as_enable) + { + rc = dtb_eram_index_cal(dev, etcam_as_mode, p_dump_acl_entry->handle, &row_index, &col_index); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dtb_eram_index_cal"); + switch (etcam_as_mode) + { + case ERAM128_TBL_128b: + { + ZXIC_COMM_MEMCPY(p_dump_acl_entry->p_as_rslt, as_eram_data, (128 / 8)); + break; + } + + case ERAM128_TBL_64b: + { + ZXIC_COMM_MEMCPY(p_dump_acl_entry->p_as_rslt, as_eram_data + ((1 - col_index) << 1), (64 / 8)); + break; + } + + case ERAM128_TBL_1b: + { + ZXIC_COMM_UINT32_GET_BITS(*(ZXIC_UINT32 *)p_dump_acl_entry->p_as_rslt, *(as_eram_data + (3 - col_index / 32)), (col_index % 32), 1); + break; + } + } + } + + return rc; +} + +/** dtb etcam 数据get接口，通过handle值获取etcam数据 +* @param dev_id 设备号 +* @param queue_id 队列号 +* @param sdt_no eram表sdt表号 +* @param p_dump_acl_entry etcam 数据结构，数据已分配相应内存 +* @return +* @remark 无 +* @see +* @author cbb @date 2022/08/30 +************************************************************/ +DPP_STATUS dpp_dtb_etcam_data_get(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 sdt_no, + DPP_DTB_ACL_ENTRY_INFO_T *p_dump_acl_entry) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_UINT32 block_idx = 0; + ZXIC_UINT32 ram_addr = 0; + ZXIC_UINT32 etcam_wr_mode = 0; + + ZXIC_UINT32 etcam_key_mode = 0; + ZXIC_UINT32 etcam_table_id = 0; + ZXIC_UINT32 as_enable = 0; + ZXIC_UINT32 as_eram_baddr = 0; + ZXIC_UINT32 etcam_as_mode = 0; + + ZXIC_UINT32 row_index = 0; + ZXIC_UINT32 col_index = 0; + + DPP_ETCAM_ENTRY_T etcam_entry_dm = {0}; + ZXIC_UINT32 as_eram_data[4] = {0}; + + ZXIC_UINT8 temp_data[DPP_ETCAM_WIDTH_MAX / 8] = {0}; + ZXIC_UINT8 temp_mask[DPP_ETCAM_WIDTH_MAX / 8] = {0}; + + DPP_ACL_CFG_EX_T *p_acl_cfg = NULL; + DPP_ACL_TBL_CFG_T *p_tbl_cfg = NULL; + + DPP_SDTTBL_ETCAM_T sdt_etcam_info = {0}; /*SDT内容*/ + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_dump_acl_entry); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_dump_acl_entry->key_data); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_dump_acl_entry->key_mask); + + //从sdt_no中获取SDT配置 + rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_etcam_info); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_soft_sdt_tbl_get"); + etcam_key_mode = sdt_etcam_info.etcam_key_mode; + etcam_as_mode = sdt_etcam_info.as_rsp_mode; + etcam_table_id = sdt_etcam_info.etcam_table_id; + as_enable = sdt_etcam_info.as_en; + as_eram_baddr = sdt_etcam_info.as_eram_baddr; + + if(as_enable) + { + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_dump_acl_entry->p_as_rslt); + } + + etcam_entry_dm.mode = etcam_key_mode; + etcam_entry_dm.p_data = temp_data; + etcam_entry_dm.p_mask = temp_mask; + + dpp_acl_cfg_get(&p_acl_cfg);//获取ACL表资源配置 + ZXIC_COMM_CHECK_POINT(p_acl_cfg); + + p_tbl_cfg = p_acl_cfg->acl_tbls + etcam_table_id;//得到该acl表的资源配置 + + if (!p_tbl_cfg->is_used) + { + ZXIC_COMM_TRACE_ERROR("table[ %d ] is not init!\n", etcam_table_id); + ZXIC_COMM_ASSERT(0); + return DPP_ACL_RC_TBL_NOT_INIT; + } + + /*计算地址等信息*/ + rc = dpp_acl_hdw_addr_get(p_tbl_cfg, p_dump_acl_entry->handle, &block_idx, &ram_addr, &etcam_wr_mode); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_acl_hdw_addr_get"); + + rc = dpp_dtb_etcam_entry_get(dev, + queue_id, + block_idx, + ram_addr, + etcam_wr_mode, + DPP_ETCAM_OPR_DM, + as_enable, + as_eram_baddr, + p_dump_acl_entry->handle, + etcam_as_mode,//128:3 64:2 + &etcam_entry_dm, + (ZXIC_UINT8 *)as_eram_data); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_etcam_entry_get"); + + ZXIC_COMM_MEMCPY(p_dump_acl_entry->key_data, etcam_entry_dm.p_data, DPP_ETCAM_ENTRY_SIZE_GET(etcam_key_mode)); + ZXIC_COMM_MEMCPY(p_dump_acl_entry->key_mask, etcam_entry_dm.p_mask, DPP_ETCAM_ENTRY_SIZE_GET(etcam_key_mode)); + + if(as_enable) + { + rc = dtb_eram_index_cal(dev, etcam_as_mode, p_dump_acl_entry->handle, &row_index, &col_index); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dtb_eram_index_cal"); + switch (etcam_as_mode) + { + case ERAM128_TBL_128b: + { + ZXIC_COMM_MEMCPY(p_dump_acl_entry->p_as_rslt, as_eram_data, (128 / 8)); + break; + } + + case ERAM128_TBL_64b: + { + ZXIC_COMM_MEMCPY(p_dump_acl_entry->p_as_rslt, as_eram_data + ((1 - col_index) << 1), (64 / 8)); + break; + } + + case ERAM128_TBL_1b: + { + ZXIC_COMM_UINT32_GET_BITS(*(ZXIC_UINT32 *)p_dump_acl_entry->p_as_rslt, *(as_eram_data + (3 - col_index / 32)), (col_index % 32), 1); + break; + } + } + } + + return rc; +} + + +#endif /**DTB GET INTERFACE*/ + +#if ZXIC_REAL("DTB FLUSH INTERFACE") + +/***********************************************************/ +/** DTB dd 整个流表清空Flush +* @param dev_id 设备号 +* @param queue_id 队列号 +* @param ddr_base_addr ddr基地址，以4K*128bit为单位 +* @param ddr_wr_mode ddr写模式 0-128bit, 1-256bit, 2-384bit, 3-512bit,取值参考SMMU1_DDR_WRT_MODE_E的定义 +* @param ddr_ecc_en ddr ECC使能 +* @param start_index flush开始的条目 +* @param entry_num 下发的条目数 +* @param element_id 返回下表使用的元素id +* @return +* @remark 无 +* @see +* @author cbb @date 2023/07/03 +************************************************************/ +DPP_STATUS dpp_dtb_smmu1_flush_cycle(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 ddr_base_addr, + ZXIC_UINT32 ddr_wr_mode, + ZXIC_UINT32 ddr_ecc_en, + ZXIC_UINT32 start_index, + ZXIC_UINT32 entry_num, + ZXIC_UINT32 *element_id) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_UINT32 index = 0; + ZXIC_UINT32 current_index = 0; + ZXIC_UINT32 ddr_entry_len = 0; + ZXIC_UINT32 *data_buff = NULL; + DPP_DTB_DDR_ENTRY_INFO_T *p_entry_arr = NULL; + + ZXIC_COMM_CHECK_POINT(dev); + + ddr_entry_len = 4 * (ddr_wr_mode + 1);//计算数据长度 + + p_entry_arr = (DPP_DTB_DDR_ENTRY_INFO_T *)ZXIC_COMM_MALLOC(entry_num * sizeof(DPP_DTB_DDR_ENTRY_INFO_T)); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_entry_arr); + + data_buff = (ZXIC_UINT32 *)ZXIC_COMM_MALLOC(ddr_entry_len * sizeof(ZXIC_UINT32)); + ZXIC_COMM_CHECK_DEV_POINT_MEMORY_FREE_NO_ASSERT(DEV_ID(dev), data_buff, p_entry_arr); + + ZXIC_COMM_MEMSET(data_buff, 0, ddr_entry_len * sizeof(ZXIC_UINT32)); + + // 下表数据准备 + for(index = 0; index < entry_num; index++) + { + current_index = start_index + index; + + p_entry_arr[index].index = current_index; + p_entry_arr[index].p_data = data_buff; + } + + rc = dpp_dtb_smmu1_data_write_cycle(dev, + queue_id, + ddr_base_addr, + ddr_wr_mode, + ddr_ecc_en, + entry_num, + p_entry_arr, + element_id); + ZXIC_COMM_FREE(data_buff); + ZXIC_COMM_FREE(p_entry_arr); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_smmu1_data_write_cycle"); + + return rc; +} + +/***********************************************************/ +/** DTB dd 整个流表清空Flush +* @param dev_id 设备号 +* @param queue_id 队列号 +* @param ddr_base_addr ddr基地址，以4K*128bit为单位 +* @param ddr_wr_mode ddr写模式 0-128bit, 1-256bit, 2-384bit, 3-512bit,取值参考SMMU1_DDR_WRT_MODE_E的定义 +* @param ddr_ecc_en ddr ECC使能 +* @param start_index flush开始的条目 +* @param entry_num 下发的条目数 +* @param element_id 返回下表使用的元素id +* @return +* @remark 无 +* @see +* @author cbb @date 2023/07/03 +************************************************************/ +DPP_STATUS dpp_dtb_smmu1_flush(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 ddr_base_addr, + ZXIC_UINT32 ddr_wr_mode, + ZXIC_UINT32 ddr_ecc_en, + ZXIC_UINT32 entry_num, + ZXIC_UINT32 *element_id) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 entry_num_max = 0; + ZXIC_UINT32 entry_cycle = 0; + ZXIC_UINT32 entry_remains = 0; + ZXIC_UINT32 start_index = 0; + ZXIC_UINT32 i = 0; + + ZXIC_COMM_CHECK_POINT(dev); + + ZXIC_COMM_TRACE_INFO("%s--[%d]:ddr_base_addr is %d.\n", __FUNCTION__,__LINE__,ddr_base_addr); + ZXIC_COMM_TRACE_INFO("%s--[%d]:ddr_wr_mode is %d.\n", __FUNCTION__,__LINE__,ddr_wr_mode); + ZXIC_COMM_TRACE_INFO("%s--[%d]:entry_num is %d.\n", __FUNCTION__,__LINE__,entry_num); + + switch (ddr_wr_mode) + { + case SMMU1_DDR_WRT_128b://128bit + { + entry_num_max = 0x1ff; + break; + } + + case SMMU1_DDR_WRT_256b://256bit + { + entry_num_max = 0x155; + break; + } + + case SMMU1_DDR_WRT_384b://384bit + { + entry_num_max = 0xcc; + break; + } + + case SMMU1_DDR_WRT_512b://512bit + { + entry_num_max = 0xcc; + break; + } + } + + ZXIC_COMM_CHECK_INDEX_EQUAL(entry_num_max, 0); + entry_cycle = entry_num / entry_num_max; + entry_remains = entry_num % entry_num_max; + + for(i = 0; i < entry_cycle; ++i) + { + start_index = entry_num_max * i; + + rc = dpp_dtb_smmu1_flush_cycle(dev, + queue_id, + ddr_base_addr, + ddr_wr_mode, + ddr_ecc_en, + start_index, + entry_num_max, + element_id); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_smmu1_flush_cycle"); + + ZXIC_COMM_TRACE_INFO("dpp_dtb_smmu1_flush_cycle[%d] element_id = %d\n",i,*element_id); + } + + if(entry_remains) + { + start_index = entry_num_max * entry_cycle; + rc = dpp_dtb_smmu1_flush_cycle(dev, + queue_id, + ddr_base_addr, + ddr_wr_mode, + ddr_ecc_en, + start_index, + entry_remains, + element_id); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_smmu1_flush_cycle"); + + ZXIC_COMM_TRACE_INFO("dpp_dtb_smmu1_flush_cycle: element_id = %d\n",*element_id); + } + + return DPP_OK; +} + + +/***********************************************************/ +/** flush指定ZCELL指定范围空间 +* @param dev_id 设备id +* @param queue_id 队列id +* @param zcell_id zcell id 0~127 +* @param start_index 起始索引 0~511 +* @param num 条目数 +* @return +* @remark 无 +* @see +* @author cq @date 2023/08/02 +************************************************************/ +DPP_STATUS dpp_dtb_hash_zcell_range_clr(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 zcell_id, + ZXIC_UINT32 start_index, + ZXIC_UINT32 num) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_UINT32 zcdep = 0; + ZXIC_UINT32 addr = 0; + ZXIC_UINT32 addr_offset = 0; + ZXIC_UINT32 dtb_len = 0; + ZXIC_UINT32 data[512 / 32] = {0}; + DPP_DTB_ENTRY_T entry = {0}; + ZXIC_UINT32 entry_data_buff[512 / 32] = {0}; + ZXIC_UINT8 entry_cmd_buff[DTB_TABLE_CMD_SIZE_BYTE] = {0}; + ZXIC_UINT8 *p_data_buff = NULL; + ZXIC_UINT32 element_id = 0; + ZXIC_UINT32 end_index = 0; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev), DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), zcell_id, 0, SE_ZCELL_TOTAL_NUM - 1); + ZXIC_COMM_CHECK_INDEX_UPPER(start_index,SE_RAM_DEPTH - 1); + + entry.cmd = entry_cmd_buff; + entry.data = (ZXIC_UINT8 *)entry_data_buff; + ZXIC_COMM_MEMSET(entry_cmd_buff, 0, sizeof(entry_cmd_buff)); + ZXIC_COMM_MEMSET(entry_data_buff, 0, sizeof(entry_data_buff)); + ZXIC_COMM_MEMSET(data, 0, sizeof(data)); + + p_data_buff = (ZXIC_UINT8 *) ZXIC_COMM_MALLOC(DPP_DTB_TABLE_DATA_BUFF_SIZE * sizeof(ZXIC_UINT8)); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data_buff); + ZXIC_COMM_MEMSET(p_data_buff, 0, DPP_DTB_TABLE_DATA_BUFF_SIZE * sizeof(ZXIC_UINT8)); + + end_index = start_index+num; + end_index = (end_index>SE_RAM_DEPTH) ? SE_RAM_DEPTH:end_index; + + for(zcdep=start_index;zcdepdev_id; + p_func_info = DPP_GET_FUN_INFO(p_se_cfg, fun_id); + DPP_SE_CHECK_FUN(p_func_info, fun_id, FUN_HASH); + p_hash_cfg = (DPP_HASH_CFG *)p_func_info->fun_ptr; + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev),p_hash_cfg); + p_zblk_dn = p_hash_cfg->hash_shareram.zblk_list.p_next; + + while (p_zblk_dn) + { + p_zblk = (SE_ZBLK_CFG *)p_zblk_dn->data; + zblock_id = p_zblk->zblk_idx; + + for (i = 0; i < SE_ZCELL_NUM; i++) + { + p_zcell = &(p_zblk->zcell_info[i]); + if ((p_zcell->flag & DPP_ZCELL_FLAG_IS_MONO) && (p_zcell->bulk_id == bulk_id)) + { + rc = dpp_dtb_hash_zcell_clr(dev, queue_id, p_zcell->zcell_idx); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_hash_zcell_clr"); + ZXIC_COMM_TRACE_DEV_INFO(DEV_ID(dev), "the Zblock[%d]'s Mono Zcell_id :%d \n", zblock_id, p_zcell->zcell_idx); + } + } + + for (i = 0; i < SE_ZREG_NUM; i++) + { + p_zreg = &(p_zblk->zreg_info[i]); + if ((p_zreg->flag & DPP_ZREG_FLAG_IS_MONO) && (p_zreg->bulk_id == bulk_id)) + { + rc = dpp_dtb_hash_zreg_clr(dev, queue_id, zblock_id, i); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "npe_hash_zreg_clr"); + ZXIC_COMM_TRACE_DEV_INFO(DEV_ID(dev), "the Zblock[%d]'s Mono Zreg_id :%d \n", zblock_id, i); + } + } + + p_zblk_dn = p_zblk_dn->next; + } + + return DPP_OK; +} + +/***********************************************************/ +/** flush当前hash引擎占用的ZCAM空间 +* @param p_se_cfg 全局数据结构 +* @param queue_id 队列id +* @param fun_id hash引擎0~3 +* @return +* @remark 无 +* @see +* @author cq @date 2023/08/02 +************************************************************/ +DPP_STATUS dpp_dtb_zcam_space_clr(DPP_DEV_T *dev, + DPP_SE_CFG *p_se_cfg, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 fun_id) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 index = 0; + ZXIC_UINT32 zblock_id = 0; + + D_NODE *p_zblk_dn = NULL; + SE_ZBLK_CFG *p_zblk = NULL; + SE_ZCELL_CFG *p_zcell = NULL; + DPP_HASH_CFG *p_hash_cfg = NULL; + FUNC_ID_INFO *p_func_info = NULL; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev),p_se_cfg); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), fun_id, 0, HASH_FUNC_ID_NUM - 1); + ZXIC_COMM_CHECK_INDEX(queue_id, 0, DTB_QUEUE_MAX - 1); + + // dev_id = p_se_cfg->dev_id; + p_func_info = DPP_GET_FUN_INFO(p_se_cfg, fun_id); + DPP_SE_CHECK_FUN(p_func_info, fun_id, FUN_HASH); + p_hash_cfg = (DPP_HASH_CFG *)p_func_info->fun_ptr; + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev),p_hash_cfg); + p_zblk_dn = p_hash_cfg->hash_shareram.zblk_list.p_next; + + while (p_zblk_dn) + { + p_zblk = (SE_ZBLK_CFG *)p_zblk_dn->data; + zblock_id = p_zblk->zblk_idx; + for (index = 0; index < SE_ZCELL_NUM; index++) + { + p_zcell = &(p_zblk->zcell_info[index]); + rc = dpp_dtb_hash_zcell_clr(dev, queue_id, p_zcell->zcell_idx); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_hash_zcell_clr"); + } + + for (index = 0; index < SE_ZREG_NUM; index++) + { + rc = dpp_dtb_hash_zreg_clr(dev, queue_id, zblock_id, index); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_hash_zreg_clr"); + } + p_zblk_dn = p_zblk_dn->next; + } + + return DPP_OK; +} + + +/***********************************************************/ +/** 清除指定空间的hash表项(清除软件配置) +* @param p_se_cfg +* @param hash_id +* @param bulk_id +* +* @return +* @remark 无 +* @see +* @author cq @date 2023/08/18 +************************************************************/ +DPP_STATUS dpp_hash_specify_entry_delete(DPP_SE_CFG *p_se_cfg,ZXIC_UINT32 hash_id, ZXIC_UINT32 bulk_id) +{ + ZXIC_UINT32 rc = 0; + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT8 key_valid = 0; + ZXIC_UINT32 table_id = 0; + ZXIC_UINT32 temp_bulk_id = 0; + + D_NODE *p_node = NULL; + ZXIC_RB_TN *p_rb_tn = NULL; + D_HEAD *p_head_hash_rb = NULL; + DPP_HASH_CFG *p_hash_cfg = NULL; + FUNC_ID_INFO *p_func_info = NULL; + DPP_HASH_RBKEY_INFO *p_rbkey = NULL; + DPP_HASH_RBKEY_INFO *p_rbkey_rtn = NULL; + ZXIC_RB_TN *p_rb_tn_rtn = NULL; + SE_ITEM_CFG *p_item = NULL; + + ZXIC_COMM_CHECK_POINT(p_se_cfg); + ZXIC_COMM_CHECK_INDEX(hash_id, 0, HASH_FUNC_ID_NUM - 1); + ZXIC_COMM_CHECK_INDEX(bulk_id, 0, HASH_BULK_NUM - 1); + + dev_id = p_se_cfg->dev_id; + p_func_info = DPP_GET_FUN_INFO(p_se_cfg, hash_id); + DPP_SE_CHECK_FUN(p_func_info, hash_id, FUN_HASH); + + p_hash_cfg = (DPP_HASH_CFG *)p_func_info->fun_ptr; + p_head_hash_rb = &p_hash_cfg->hash_rb.tn_list; + + p_node = p_head_hash_rb->p_next; + while(p_node) + { + p_rb_tn = (ZXIC_RB_TN *)p_node->data; + p_rbkey = (DPP_HASH_RBKEY_INFO *)p_rb_tn->p_key; + key_valid = DPP_GET_HASH_KEY_VALID(p_rbkey->key); + table_id = DPP_GET_HASH_TBL_ID(p_rbkey->key); + temp_bulk_id = ((table_id >> 2) & 0x7); + if((!key_valid) || (temp_bulk_id != bulk_id)) + { + p_node = p_node->next; + continue; + } + + p_node = p_node->next; /*zxic_comm_rb_delete删除操作之前执行*/ + rc = zxic_comm_rb_delete(&p_hash_cfg->hash_rb, p_rbkey, &p_rb_tn_rtn); + if (ZXIC_RBT_RC_SRHFAIL == rc) + { + p_hash_cfg->hash_stat.delete_fail++; + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "Error!there is not item in hash!\n"); + return DPP_HASH_RC_DEL_SRHFAIL; + } + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_rb_tn_rtn); + p_rbkey_rtn = (DPP_HASH_RBKEY_INFO *)(p_rb_tn_rtn->p_key); + p_item = p_rbkey_rtn->p_item_info; + + rc = zxic_comm_double_link_del(&(p_rbkey_rtn->entry_dn), &(p_item->item_list)); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "zxic_comm_double_link_del"); + p_item->wrt_mask &= ~(DPP_GET_HASH_ENTRY_MASK(p_rbkey_rtn->entry_size, p_rbkey_rtn->entry_pos)) & 0xF; + + if (0 == p_item->item_list.used) + { + if ((ITEM_DDR_256 == p_item->item_type) || (ITEM_DDR_512 == p_item->item_type)) + { + /* modify coverity by yinxh 2021.03.10*,以256bit为单位。暂不考虑512bit的情况*/ + ZXIC_COMM_CHECK_INDEX_UPPER(p_item->item_index, p_hash_cfg->p_bulk_ddr_info[bulk_id]->item_num); + p_hash_cfg->p_bulk_ddr_info[bulk_id]->p_item_array[p_item->item_index] = NULL; + ZXIC_COMM_FREE(p_item); + } + else + { + p_item->valid = 0; + } + } + + ZXIC_COMM_FREE(p_rbkey_rtn); + ZXIC_COMM_FREE(p_rb_tn_rtn); + p_hash_cfg->hash_stat.delete_ok++; + } + + return DPP_OK; +} + +/***********************************************************/ +/** flush指定eram空间 +* @param dev_id 设备id +* @param queue_id 队列id +* @param sdt_no sdt号 +* @return +* @remark 无 +* @see +* @author cq @date 2023/08/02 +************************************************************/ +DPP_STATUS dpp_dtb_eram_table_flush(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 sdt_no) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 eram_depth = 0; + ZXIC_UINT32 element_id = 0; + ZXIC_UINT32 index = 0; + ZXIC_UINT8 *pBuff = NULL; + DPP_DTB_ERAM_ENTRY_INFO_T *p_entry_arr = NULL; + DPP_DTB_ERAM_ENTRY_INFO_T *p_temp_entry_arr = NULL; + DPP_SDTTBL_ERAM_T sdt_eram = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_INDEX(queue_id, 0, DTB_QUEUE_MAX - 1); + ZXIC_COMM_CHECK_INDEX(sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1); + + rc = dpp_soft_sdt_tbl_get(DEV_ID(dev),sdt_no,&sdt_eram); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_soft_sdt_tbl_get"); + + eram_depth = sdt_eram.eram_table_depth; + p_entry_arr = (DPP_DTB_ERAM_ENTRY_INFO_T *)ZXIC_COMM_MALLOC(eram_depth*sizeof(DPP_DTB_ERAM_ENTRY_INFO_T)); + ZXIC_COMM_CHECK_POINT(p_entry_arr); + pBuff = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(eram_depth*4*sizeof(ZXIC_UINT32)); + ZXIC_COMM_CHECK_POINT_MEMORY_FREE(pBuff,p_entry_arr); + ZXIC_COMM_MEMSET((ZXIC_UINT8 *)p_entry_arr,0x0,eram_depth*sizeof(DPP_DTB_ERAM_ENTRY_INFO_T)); + ZXIC_COMM_MEMSET(pBuff,0x0,eram_depth*4*sizeof(ZXIC_UINT32)); + for(index=0;indexindex = index; + p_temp_entry_arr->p_data = (ZXIC_UINT32 *)(pBuff + (index * 4 * sizeof(ZXIC_UINT32))); + } + + rc = dpp_dtb_eram_dma_write(dev, + queue_id, + sdt_no, + eram_depth, + p_entry_arr, + &element_id); + ZXIC_COMM_CHECK_RC_MEMORY_FREE2PTR_NO_ASSERT(rc, "dpp_dtb_eram_dma_write",pBuff,p_entry_arr); + + ZXIC_COMM_FREE(pBuff); + ZXIC_COMM_FREE(p_entry_arr); + return DPP_OK; +} + +/***********************************************************/ +/** flush指定hash空间(DDR/ZCAM) +* @param dev_id 设备id +* @param queue_id 队列id +* @param sdt_no sdt号 +* @return +* @remark 无 +* @see +* @author cq @date 2023/08/02 +************************************************************/ +DPP_STATUS dpp_dtb_hash_table_flush(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 sdt_no) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT8 bulk_id = 0; + ZXIC_UINT8 table_id = 0; + ZXIC_UINT32 ddr_baddr = 0; + ZXIC_UINT32 ddr_item_num = 0; + ZXIC_UINT32 ddr_tbl_wr_mode = 0; + ZXIC_UINT32 element_id = 0; + + DPP_SE_CFG *p_se_cfg = NULL; + FUNC_ID_INFO *p_func_info = NULL; + DPP_HASH_CFG *p_hash_cfg = NULL; + HASH_DDR_CFG *p_ddr_cfg = NULL; + DPP_SDTTBL_HASH_T sdt_hash = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_INDEX(queue_id, 0, DTB_QUEUE_MAX - 1); + ZXIC_COMM_CHECK_INDEX(sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1); + + rc = dpp_soft_sdt_tbl_get(DEV_ID(dev),sdt_no,&sdt_hash); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_soft_sdt_tbl_get"); + + /* 取出se配置 */ + rc = dpp_se_cfg_get(DEV_ID(dev), &p_se_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_se_cfg_get"); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_se_cfg); + p_func_info = DPP_GET_FUN_INFO(p_se_cfg, sdt_hash.hash_id); + DPP_SE_CHECK_FUN(p_func_info, sdt_hash.hash_id, FUN_HASH); + + p_hash_cfg = (DPP_HASH_CFG *)p_func_info->fun_ptr; + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_hash_cfg); + table_id = sdt_hash.hash_table_id; + bulk_id = ((table_id >> 2) & 0x7); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), bulk_id, 0, HASH_BULK_NUM - 1); + + /*独占模式下才执行flush操作*/ + if(!p_hash_cfg->bulk_ram_mono[bulk_id]) + { + ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "fush error:hash[%u] bulk[%u] is not monopolize!\n", sdt_hash.hash_id, bulk_id); + return DPP_HASH_RC_INVALID_PARA; + } + + /*混合模式，先清除DDR空间*/ + if(p_hash_cfg->ddr_valid) + { + p_ddr_cfg = p_hash_cfg->p_bulk_ddr_info[bulk_id]; + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_ddr_cfg); + ddr_baddr = p_ddr_cfg->ddr_baddr; + ddr_item_num = p_ddr_cfg->item_num;/*ddr存储单元数目，以DDR位宽为单位*/ + ddr_tbl_wr_mode = SMMU1_DDR_WRT_256b; + if(DDR_WIDTH_512b == p_ddr_cfg->width_mode) + { + ddr_tbl_wr_mode = SMMU1_DDR_WRT_512b; + } + + ZXIC_COMM_TRACE_INFO("%s--[%d]:ddr_baddr is %d.\n", __FUNCTION__,__LINE__,ddr_baddr); + ZXIC_COMM_TRACE_INFO("%s--[%d]:ddr_item_num is %d.\n", __FUNCTION__,__LINE__,ddr_item_num); + ZXIC_COMM_TRACE_INFO("%s--[%d]:ddr_tbl_wr_mode is %d.\n", __FUNCTION__,__LINE__,ddr_tbl_wr_mode); + + rc = dpp_dtb_smmu1_flush(dev, + queue_id, + ddr_baddr, + ddr_tbl_wr_mode, + p_ddr_cfg->ddr_ecc_en, + ddr_item_num, + &element_id); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_smmu1_flush"); + } + ZXIC_COMM_TRACE_INFO("dpp_dtb_hash_table_flush: DDR DONE!!!\n"); + + /*清除zcam空间*/ + rc = dpp_dtb_specify_zcam_space_clr(dev, p_se_cfg,queue_id,sdt_hash.hash_id,bulk_id); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_specify_zcam_space_clr"); + ZXIC_COMM_TRACE_INFO("dpp_dtb_specify_zcam_space_clr DONE!!!\n"); + + /*软件删除表项*/ + rc = dpp_hash_specify_entry_delete(p_se_cfg,sdt_hash.hash_id,bulk_id); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_hash_specify_entry_delete"); + ZXIC_COMM_TRACE_INFO("dpp_hash_specify_entry_delete DONE!!!\n"); + + return DPP_OK; +} + +/***********************************************************/ +/** 清除hash表资源(硬件和软件，硬件通过dtb方式清除) +* @param dev_id 设备id +* @param queue_id 队列id +* @param hash_id hash引擎 0~3 +* @return +* @remark 无 +* @see +* @author cq @date 2023/09/26 +************************************************************/ +DPP_STATUS dpp_dtb_hash_all_entry_delete(DPP_DEV_T *dev, ZXIC_UINT32 queue_id, ZXIC_UINT32 hash_id) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_UINT32 bulk_id = 0; + ZXIC_UINT32 ddr_baddr = 0; + ZXIC_UINT32 ddr_item_num = 0; + ZXIC_UINT32 ddr_tbl_wr_mode = 0; + ZXIC_UINT32 element_id = 0; + + DPP_SE_CFG *p_se_cfg = NULL; + FUNC_ID_INFO *p_func_info = NULL; + DPP_HASH_CFG *p_hash_cfg = NULL; + HASH_DDR_CFG *p_ddr_cfg = NULL; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_INDEX(queue_id, 0, DTB_QUEUE_MAX - 1); + ZXIC_COMM_CHECK_INDEX(hash_id, 0, HASH_FUNC_ID_NUM - 1); + + /* 取出se配置 */ + rc = dpp_se_cfg_get(DEV_ID(dev), &p_se_cfg); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_se_cfg_get"); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_se_cfg); + p_func_info = DPP_GET_FUN_INFO(p_se_cfg, hash_id); + DPP_SE_CHECK_FUN(p_func_info, hash_id, FUN_HASH); + + p_hash_cfg = (DPP_HASH_CFG *)p_func_info->fun_ptr; + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_hash_cfg); + + /*混合模式，先清除DDR空间*/ + if(p_hash_cfg->ddr_valid) + { + for(bulk_id = 0; bulk_id < HASH_BULK_NUM; bulk_id++) + { + p_ddr_cfg = p_hash_cfg->p_bulk_ddr_info[bulk_id]; + if(NULL==p_ddr_cfg) + { + continue; + } + ddr_baddr = p_ddr_cfg->ddr_baddr; + ddr_item_num = p_ddr_cfg->item_num;/*ddr存储单元数目，以DDR位宽为单位*/ + ddr_tbl_wr_mode = SMMU1_DDR_WRT_256b; + if(DDR_WIDTH_512b == p_ddr_cfg->width_mode) + { + ddr_tbl_wr_mode = SMMU1_DDR_WRT_512b; + } + + ZXIC_COMM_TRACE_INFO("%s--[%d]:ddr_baddr is %d.\n", __FUNCTION__,__LINE__,ddr_baddr); + ZXIC_COMM_TRACE_INFO("%s--[%d]:ddr_item_num is %d.\n", __FUNCTION__,__LINE__,ddr_item_num); + ZXIC_COMM_TRACE_INFO("%s--[%d]:ddr_tbl_wr_mode is %d.\n", __FUNCTION__,__LINE__,ddr_tbl_wr_mode); + + rc = dpp_dtb_smmu1_flush(dev, + queue_id, + ddr_baddr, + ddr_tbl_wr_mode, + p_ddr_cfg->ddr_ecc_en, + ddr_item_num, + &element_id); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_smmu1_flush"); + } + } + + /*清除hash引擎占用的整个zcam空间*/ + rc = dpp_dtb_zcam_space_clr(dev, p_se_cfg, queue_id, hash_id); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_specify_zcam_space_clr"); + ZXIC_COMM_PRINT("dpp_dtb_zcam_space_clr hash id: %d DONE!!!\n", hash_id); + + /*软件删除表项*/ + rc = dpp_hash_soft_all_entry_delete(p_se_cfg, hash_id); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_hash_soft_all_entry_delete"); + ZXIC_COMM_PRINT("dpp_hash_soft_all_entry_delete hash id %d DONE!!!\n", hash_id); + + return DPP_OK; +} + +/***********************************************************/ +/** DTB etcam 整个流表清空Flush +* @param devId NP设备号 +* @param queueId DTB队列编号 +* @param sdtNo 流表std号 +* @return +* @remark 无 +* @see +* @author cbb @date 2023/07/03 +************************************************************/ +DPP_STATUS dpp_dtb_etcam_table_flush(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 sdt_no) +{ + // 按照std 号的深度进行etcam的内容的清理； + DPP_STATUS rc = DPP_OK; + + ZXIC_UINT32 data_byte_size = 0; + ZXIC_UINT32 index = 0; + ZXIC_UINT32 etcam_key_mode = 0; + ZXIC_UINT32 as_enable = 0; + ZXIC_UINT32 etcam_table_depth = 0; + ZXIC_UINT32 element_id = 0; + + DPP_SDTTBL_ETCAM_T sdt_etcam_info = {0}; /*SDT内容*/ + + ZXIC_UINT8 *data_buff = NULL; + ZXIC_UINT8 *mask_buff = NULL; + ZXIC_UINT32 *eram_buff = NULL; + DPP_DTB_ACL_ENTRY_INFO_T *p_entry_arr = NULL; + + ZXIC_COMM_CHECK_POINT(dev); + + rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_etcam_info); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_soft_sdt_tbl_get"); + + etcam_key_mode = sdt_etcam_info.etcam_key_mode; + as_enable = sdt_etcam_info.as_en; + etcam_table_depth = sdt_etcam_info.etcam_table_depth; + + data_byte_size = DPP_ETCAM_ENTRY_SIZE_GET(etcam_key_mode);//80/40 + + //组装数据 + p_entry_arr = (DPP_DTB_ACL_ENTRY_INFO_T *)ZXIC_COMM_MALLOC(etcam_table_depth * sizeof(DPP_DTB_ACL_ENTRY_INFO_T)); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_entry_arr); + ZXIC_COMM_MEMSET(p_entry_arr, 0, etcam_table_depth * sizeof(DPP_DTB_ACL_ENTRY_INFO_T)); + + data_buff = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(data_byte_size * sizeof(ZXIC_UINT8)); + ZXIC_COMM_CHECK_DEV_POINT_MEMORY_FREE_NO_ASSERT(DEV_ID(dev), data_buff, p_entry_arr); + ZXIC_COMM_MEMSET(data_buff, 0, data_byte_size * sizeof(ZXIC_UINT8)); + + mask_buff = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(data_byte_size * sizeof(ZXIC_UINT8)); + ZXIC_COMM_CHECK_DEV_POINT_MEMORY_FREE2PTR_NO_ASSERT(DEV_ID(dev), mask_buff, p_entry_arr, data_buff); + ZXIC_COMM_MEMSET(mask_buff, 0, data_byte_size * sizeof(ZXIC_UINT8)); + + if(as_enable) + { + eram_buff = (ZXIC_UINT32 *)ZXIC_COMM_MALLOC(4 * sizeof(ZXIC_UINT32)); + ZXIC_COMM_CHECK_DEV_POINT_MEMORY_FREE3PTR_NO_ASSERT(0, eram_buff, mask_buff, p_entry_arr, data_buff); + ZXIC_COMM_MEMSET(eram_buff, 0, 4 * sizeof(ZXIC_UINT32)); + } + + for(index = 0; index < etcam_table_depth; index++) + { + p_entry_arr[index].handle = index; + p_entry_arr[index].key_data = data_buff; + p_entry_arr[index].key_mask = mask_buff; + + if(as_enable) + { + p_entry_arr[index].p_as_rslt = (ZXIC_UINT8 *)eram_buff; + } + } + + rc = dpp_dtb_acl_dma_insert(dev, + queue_id, + sdt_no, + etcam_table_depth, + p_entry_arr, + &element_id); + ZXIC_COMM_FREE(data_buff); + ZXIC_COMM_FREE(mask_buff); + if(eram_buff) + { + ZXIC_COMM_FREE(eram_buff); + } + ZXIC_COMM_FREE(p_entry_arr); + ZXIC_COMM_CHECK_DEV_RC(0, rc, "dpp_dtb_acl_dma_insert"); + + return rc; +} + +#endif + +#if ZXIC_REAL("DTB DUMP INTERFACE") + +/***********************************************************/ +/** 根据队列号和sdt号分配元素id和dma地址 +* @param dev_id 设备id +* @param queue_id 队列id 0~127 +* @param sdt_no sdt号 0~255 +* @param element_id 出参，元素id +* @return +* @remark 无 +* @see +* @author cq @date 2023/08/22 +************************************************************/ +DPP_STATUS dpp_dtb_dump_addr_set(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 sdt_no, + ZXIC_UINT32 *element_id) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 dump_element_id = 0; + ZXIC_UINT64 phy_addr = 0; + ZXIC_UINT64 vir_addr = 0; + ZXIC_UINT32 size = 0; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_INDEX(queue_id, 0, DTB_QUEUE_MAX - 1); + ZXIC_COMM_CHECK_INDEX(sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1); + + /*获取dump目的地址*/ + rc = dpp_dtb_dump_sdt_addr_get( dev, + queue_id, + sdt_no, + &phy_addr, + &vir_addr, + &size); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_dump_sdt_addr_get"); + ZXIC_COMM_MEMSET((ZXIC_UINT8 *)vir_addr, 0, size); + + /*获取队列可用元素*/ + rc = dpp_dtb_tab_up_free_item_get(dev, queue_id, &dump_element_id); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_tab_up_free_item_get"); + ZXIC_COMM_TRACE_DEV_INFO(DEV_ID(dev), "table up item queue_element_id is: %d.\n",dump_element_id); + + /*在相应队列的元素上配置用户dma地址信息*/ + rc = dpp_dtb_tab_up_item_user_addr_set(dev, + queue_id, + dump_element_id, + phy_addr, + vir_addr); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_tab_up_item_addr_set"); + + *element_id = dump_element_id; + + return DPP_OK; +} + +/***********************************************************/ +/** 将dump数据解析为hash条目格式 +* @param p_hash_entry_cfg hash配置参数 +* @param item_type 条目类型,见枚举SE_ITEM_TYPE +* @param pdata dump数据 +* @param dump_len dump有效长度 +* @param pOutData 出参，连续内存，hash条目信息DPP_HASH_ENTRY +* @param p_item_num 出参，解析出的hash有效条目数 +* @return +* @remark 无 +* @see +* @author cq @date 2023/08/22 +************************************************************/ +DPP_STATUS dpp_dtb_dump_hash_parse(HASH_ENTRY_CFG *p_hash_entry_cfg, + ZXIC_UINT32 item_type, + ZXIC_UINT8 *pdata, + ZXIC_UINT32 dump_len, + ZXIC_UINT8 *pOutData, + ZXIC_UINT32 *p_item_num) +{ + ZXIC_UINT32 item_num = 0; + ZXIC_UINT32 data_offset = 0; + ZXIC_UINT32 index = 0; + ZXIC_UINT8 temp_key_valid = 0; + ZXIC_UINT8 temp_key_type = 0; + ZXIC_UINT8 temp_tbl_id = 0; + ZXIC_UINT32 srh_entry_size = 0; + ZXIC_UINT32 item_width = SE_ITEM_WIDTH_MAX; + ZXIC_UINT8 *p_temp_key = NULL; + ZXIC_UINT8 *p_hash_item = NULL; + DPP_HASH_ENTRY *p_dtb_hash_entry = NULL; + DPP_HASH_ENTRY *p_temp_entry = NULL; + + ZXIC_COMM_CHECK_POINT(p_hash_entry_cfg); + ZXIC_COMM_CHECK_POINT(pdata); + ZXIC_COMM_CHECK_POINT(pOutData); + ZXIC_COMM_CHECK_POINT(p_item_num); + + if (ITEM_DDR_256 == item_type) + { + item_width = item_width / 2; + } + + p_dtb_hash_entry = (DPP_HASH_ENTRY *)pOutData; + srh_entry_size = DPP_GET_HASH_ENTRY_SIZE(p_hash_entry_cfg->key_type); + + for(index = 0; index < (dump_len / item_width); index++) + { + data_offset = 0; + p_hash_item = pdata + index * item_width; + while(data_offset < item_width) + { + p_temp_key = p_hash_item + data_offset; + temp_key_valid = DPP_GET_HASH_KEY_VALID(p_temp_key); + temp_key_type = DPP_GET_HASH_KEY_TYPE(p_temp_key); + temp_tbl_id = DPP_GET_HASH_TBL_ID(p_temp_key); + p_temp_entry = p_dtb_hash_entry + item_num; + ZXIC_COMM_CHECK_POINT(p_temp_entry); + ZXIC_COMM_CHECK_POINT(p_temp_entry->p_key); + ZXIC_COMM_CHECK_POINT(p_temp_entry->p_rst); + if(temp_key_valid && (temp_key_type == p_hash_entry_cfg->key_type) + && (temp_tbl_id == p_hash_entry_cfg->table_id)) + { + ZXIC_COMM_MEMCPY(p_temp_entry->p_key, p_temp_key, p_hash_entry_cfg->key_by_size + 1); + ZXIC_COMM_MEMCPY(p_temp_entry->p_rst, p_temp_key + 1 + p_hash_entry_cfg->key_by_size, p_hash_entry_cfg->rst_by_size); + item_num++; + } + + data_offset += srh_entry_size; + } + } + + *p_item_num = item_num; + return DPP_OK; +} + +/** dtb dump eram整个表项内容 输入128bit单位index，输出128bit为单位的数据 +* @param dev_id 设备号 +* @param queue_id 队列号 +* @param sdt_no eram表sdt表号 +* @param start_index 要dump的起始index 单位是128bit +* @param depth dump的深度以128bit为单位 +* @param p_data dump出数据缓存(大小128bit * depth) +* @param element_id 返回下表使用的元素id +* @return +* @remark 无 +* @see +* @author cbb @date 2022/08/30 +************************************************************/ +DPP_STATUS dpp_dtb_sdt_eram_table_dump(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 sdt_no, + ZXIC_UINT32 start_index, + ZXIC_UINT32 depth, + ZXIC_UINT32 *p_data, + ZXIC_UINT32 *element_id + ) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_UINT32 eram_base_addr = 0; + ZXIC_UINT32 dump_addr_128bit = 0; + ZXIC_UINT32 dump_item_index = 0; + ZXIC_UINT32 dump_data_len = 0; + ZXIC_UINT32 dump_desc_len = 0; + + ZXIC_ADDR_T dump_sdt_phy_addr = 0; + ZXIC_ADDR_T dump_sdt_vir_addr = 0; + ZXIC_UINT32 dump_addr_size = 0; + + ZXIC_UINT32 dump_dst_phy_haddr = 0; + ZXIC_UINT32 dump_dst_phy_laddr = 0; + + ZXIC_UINT8 form_buff[DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; + + /*获取sdt信息*/ + DPP_SDTTBL_ERAM_T sdt_eram = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DTB_QUEUE_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), element_id); + + rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_eram); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_soft_sdt_tbl_get"); + + eram_base_addr = sdt_eram.eram_base_addr; + dump_addr_128bit = eram_base_addr + start_index; + + //获取dump目的地址 + rc = dpp_dtb_dump_sdt_addr_get( dev, + queue_id, + sdt_no, + &dump_sdt_phy_addr, + &dump_sdt_vir_addr, + &dump_addr_size); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_dump_sdt_addr_get"); + + ZXIC_COMM_MEMSET((ZXIC_UINT8 *)dump_sdt_vir_addr, 0, dump_addr_size); + + rc = dpp_dtb_tab_up_free_item_get(dev, queue_id, &dump_item_index); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_tab_up_free_item_get"); + ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev), "dump queue id %d, element_id is: %d.\n",queue_id, dump_item_index); + + *element_id = dump_item_index;//保存获取的item_index + + ZXIC_COMM_TRACE_INFO("eram dump eram_base_addr %x\n",eram_base_addr); + ZXIC_COMM_TRACE_INFO("eram dump start_index %x\n",start_index); + ZXIC_COMM_TRACE_INFO("eram dump queue %d,item_index: %d\n",queue_id, dump_item_index); + + //在相应队列的元素上配置用户dma地址信息 + rc = dpp_dtb_tab_up_item_user_addr_set(dev, + queue_id, + dump_item_index, + dump_sdt_phy_addr, + dump_sdt_vir_addr); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_tab_up_item_addr_set"); + + /*获取地址*/ + rc = dpp_dtb_tab_up_item_addr_get(dev, queue_id, dump_item_index, &dump_dst_phy_haddr, &dump_dst_phy_laddr); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_tab_up_item_addr_get"); + + rc = dpp_dtb_smmu0_dump_info_write(dev, + dump_addr_128bit, + depth, + dump_dst_phy_haddr, + dump_dst_phy_laddr, + (ZXIC_UINT32 *)form_buff); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_smmu0_dump_info_write"); + + /*组装下表命令格式*/ + dump_data_len = depth * 128 / 32; + dump_desc_len = DTB_LEN_POS_SETP / 4; + + if(dump_data_len * 4 > dump_addr_size) + { + ZXIC_COMM_TRACE_ERROR("eram dump size is too small!\n"); + return DPP_RC_DTB_DUMP_SIZE_SMALL; + } + + rc = dpp_dtb_write_dump_desc_info(dev, queue_id, dump_item_index, (ZXIC_UINT32 *)form_buff, dump_data_len, dump_desc_len, p_data); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_write_dump_desc_info"); + + return DPP_OK; +} + +/** dtb dump eram直接表表项内容 支持64bit/128bit +* @param dev_id 设备号 +* @param queue_id 队列号 +* @param sdt_no eram表sdt表号 +* @param start_index 要dump的起始index，单位是sdt_no该表的mode +* @param p_dump_data_arr 本次dump出的数据，数据格式与下表格式相同 +* @param entry_num 本次dump实际的条目数 +* @param next_start_index 下次dump是开始的index +* @param finish_flag 整个表dump完成标志，1表示完成，0表示未完成 +* @return +* @remark 无 +* @see +* @author cbb @date 2022/08/30 +************************************************************/ + DPP_STATUS dpp_dtb_eram_table_dump(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 sdt_no, + DPP_DTB_DUMP_INDEX_T start_index, + DPP_DTB_ERAM_ENTRY_INFO_T* p_dump_data_arr, + ZXIC_UINT32 *entry_num, + DPP_DTB_DUMP_INDEX_T *next_start_index, + ZXIC_UINT32 *finish_flag) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_UINT32 i = 0; + ZXIC_UINT32 dump_mode = 0; + ZXIC_UINT32 eram_table_depth = 0; + ZXIC_UINT32 start_index_128bit = 0; + ZXIC_UINT32 row_index = 0; + ZXIC_UINT32 col_index = 0; + ZXIC_UINT32 dump_depth_128bit = 0; + ZXIC_UINT32 dump_depth = 0; + ZXIC_UINT32 element_id = 0; + ZXIC_UINT8* dump_data_buff = NULL; + ZXIC_UINT8* temp_data = NULL; + ZXIC_UINT32 remain = 0; + ZXIC_UINT32 *buff = NULL; + + DPP_DTB_ERAM_ENTRY_INFO_T* p_dump_user_data = NULL; + DPP_SDTTBL_ERAM_T sdt_eram = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + + rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_eram); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_soft_sdt_tbl_get"); + + dump_mode = sdt_eram.eram_mode;//0:1bit;2:64bit;3:128, + eram_table_depth = sdt_eram.eram_table_depth; + + rc = dtb_eram_index_cal(dev, dump_mode, eram_table_depth, &dump_depth_128bit, &col_index); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dtb_eram_index_cal"); + + rc = dtb_eram_index_cal(dev, dump_mode, start_index.index, &start_index_128bit, &col_index); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dtb_eram_index_cal"); + + dump_depth = dump_depth_128bit - start_index_128bit; + + dump_data_buff = (ZXIC_UINT8 *) ZXIC_COMM_MALLOC(dump_depth * DTB_LEN_POS_SETP); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), dump_data_buff); + ZXIC_COMM_MEMSET(dump_data_buff, 0, dump_depth * DTB_LEN_POS_SETP); + + rc = dpp_dtb_sdt_eram_table_dump(dev, + queue_id, + sdt_no, + start_index_128bit, + dump_depth, + (ZXIC_UINT32 *)dump_data_buff, + &element_id); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_sdt_eram_table_dump", dump_data_buff); + ZXIC_COMM_TRACE_INFO(" dpp_dtb_sdt_eram_table_dump done queue %d element %d.\n", queue_id, element_id); + + if (dump_mode == ERAM128_TBL_128b) + { + for(i = 0; i < dump_depth; i++) + { + p_dump_user_data = p_dump_data_arr + i; + temp_data = dump_data_buff + i * DTB_LEN_POS_SETP; + if ((p_dump_user_data == NULL) || (p_dump_user_data->p_data == NULL)) + { + ZXIC_COMM_TRACE_ERROR("eram index 0x%x data user buff is NULL!\n",start_index.index + i); + ZXIC_COMM_FREE(dump_data_buff); + return DPP_ERR; + } + + p_dump_user_data->index = start_index.index + i; + ZXIC_COMM_MEMCPY(p_dump_user_data->p_data, temp_data, (128 / 8)); + } + } + else if(dump_mode == ERAM128_TBL_64b) + { + remain = start_index.index % 2; + for(i = 0; i < eram_table_depth - start_index.index; i++) + { + rc = dtb_eram_index_cal(dev, dump_mode, remain, &row_index, &col_index); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dtb_eram_index_cal", dump_data_buff); + temp_data = dump_data_buff + row_index * DTB_LEN_POS_SETP; + + buff = (ZXIC_UINT32*)temp_data; + p_dump_user_data = p_dump_data_arr + i; + if (p_dump_user_data->p_data == NULL) + { + ZXIC_COMM_TRACE_ERROR("eram index 0x%x data point is NULL!\n",start_index.index + i); + ZXIC_COMM_FREE(dump_data_buff); + return DPP_ERR; + } + + p_dump_user_data->index = start_index.index + i; + ZXIC_COMM_MEMCPY(p_dump_user_data->p_data, buff + ((1 - col_index) << 1), (64 / 8)); + + remain ++; + } + } + + *entry_num = eram_table_depth - start_index.index; + *finish_flag = 1; + ZXIC_COMM_TRACE_INFO(" eram table dump entry num %d, finish flag %d\n\n", *entry_num, *finish_flag); + + ZXIC_COMM_FREE(dump_data_buff); + + return DPP_OK; +} + + +/***********************************************************/ +/** dump指定hash表占用的zcam数据 +* @param dev_id 设备id +* @param queue_id 队列id 0~127 +* @param sdt_no sdt号 0~255 +* @param fun_id 需dump的zblock个数 +* @param bulk_id zblock索引 +* @param p_data 出参，dump数据 +* @param p_dump_len 出参，dump长度 +* @return +* @remark 无 +* @see +* @author cq @date 2023/08/22 +************************************************************/ +DPP_STATUS dpp_dtb_sdt_hash_zcam_mono_space_dump(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 sdt_no, + ZXIC_UINT32 fun_id, + ZXIC_UINT32 bulk_id, + ZXIC_UINT8 *p_data, + ZXIC_UINT32 *p_dump_len) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_UINT32 i = 0; + ZXIC_UINT32 zblock_id = 0; + ZXIC_UINT32 zcell_id = 0; + ZXIC_UINT32 start_addr = 0; + ZXIC_UINT32 dtb_desc_len = 0; + ZXIC_UINT32 dump_pa_h = 0; + ZXIC_UINT32 dump_pa_l = 0; + ZXIC_UINT32 dma_addr_offset = 0; + ZXIC_UINT32 desc_addr_offset = 0; + ZXIC_UINT32 element_id = 0; + ZXIC_UINT8 *p_dump_desc_buf = NULL; + + DPP_SE_CFG *p_se_cfg = NULL; + D_NODE *p_zblk_dn = NULL; + SE_ZBLK_CFG *p_zblk = NULL; + SE_ZREG_CFG *p_zreg = NULL; + SE_ZCELL_CFG *p_zcell = NULL; + DPP_HASH_CFG *p_hash_cfg = NULL; + FUNC_ID_INFO *p_func_info = NULL; + + DPP_DTB_ENTRY_T dtb_dump_entry = {0}; + ZXIC_UINT8 cmd_buff[DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), fun_id, 0, HASH_FUNC_ID_NUM - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), bulk_id, 0, HASH_BULK_NUM - 1); + ZXIC_COMM_CHECK_INDEX(queue_id, 0, DTB_QUEUE_MAX - 1); + ZXIC_COMM_CHECK_POINT(p_data); + ZXIC_COMM_CHECK_POINT(p_dump_len); + + rc = dpp_dtb_dump_addr_set(dev, queue_id, sdt_no, &element_id); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_dump_addr_set"); + + p_dump_desc_buf = (ZXIC_UINT8 *) ZXIC_COMM_MALLOC(DPP_DTB_TABLE_DUMP_INFO_BUFF_SIZE * sizeof(ZXIC_UINT8)); + ZXIC_COMM_CHECK_POINT(p_dump_desc_buf); + ZXIC_COMM_MEMSET(p_dump_desc_buf, 0, DPP_DTB_TABLE_DUMP_INFO_BUFF_SIZE * sizeof(ZXIC_UINT8)); + + dtb_dump_entry.cmd = cmd_buff; + + rc = dpp_se_cfg_get(DEV_ID(dev), &p_se_cfg); + ZXIC_COMM_CHECK_DEV_RC_MEMORY_FREE_NO_ASSERT(DEV_ID(dev), rc, "dpp_se_cfg_get", p_dump_desc_buf); + ZXIC_COMM_CHECK_DEV_POINT_MEMORY_FREE_NO_ASSERT(DEV_ID(dev), p_se_cfg, p_dump_desc_buf); + + p_func_info = DPP_GET_FUN_INFO(p_se_cfg, fun_id); + DPP_SE_CHECK_FUN_MEMORY_FREE(p_func_info, fun_id, FUN_HASH, p_dump_desc_buf); + p_hash_cfg = (DPP_HASH_CFG *)p_func_info->fun_ptr; + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_hash_cfg); + p_zblk_dn = p_hash_cfg->hash_shareram.zblk_list.p_next; + + while (p_zblk_dn) + { + p_zblk = (SE_ZBLK_CFG *)p_zblk_dn->data; + zblock_id = p_zblk->zblk_idx; + + //mono zcell dump + for (i = 0; i < SE_ZCELL_NUM; i++) + { + p_zcell = &(p_zblk->zcell_info[i]); + + if ((p_zcell->flag & DPP_ZCELL_FLAG_IS_MONO) && (p_zcell->bulk_id == bulk_id)) + { + zcell_id = p_zcell->zcell_idx; + + start_addr = ZBLK_ITEM_ADDR_CALC(zcell_id, 0); + + /*获取dma上送指定条目的物理地址*/ + rc = dpp_dtb_tab_up_item_offset_addr_get(dev, + queue_id, + element_id, + dma_addr_offset, + &dump_pa_h, + &dump_pa_l); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_tab_up_item_offset_addr_get",p_dump_desc_buf); + + rc = dpp_dtb_zcam_dump_entry(dev, start_addr, DTB_DUMP_ZCAM_512b, SE_RAM_DEPTH, dump_pa_h, dump_pa_l, &dtb_dump_entry); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_zcam_dump_entry",p_dump_desc_buf); + + rc = dpp_dtb_data_write(p_dump_desc_buf, desc_addr_offset, &dtb_dump_entry); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_zcam_dump_entry",p_dump_desc_buf); + + dtb_desc_len++; + dma_addr_offset += SE_RAM_DEPTH * 512 / 8; + desc_addr_offset += DTB_LEN_POS_SETP; + + ZXIC_COMM_TRACE_DEV_INFO(DEV_ID(dev), "the Zblock[%d]'s bulk_id:%d Mono Zcell_id :%d \n", zblock_id, bulk_id, zcell_id); + } + } + + //mono zreg dump + for (i = 0; i < SE_ZREG_NUM; i++) + { + p_zreg = &(p_zblk->zreg_info[i]); + + if ((p_zreg->flag & DPP_ZREG_FLAG_IS_MONO) && (p_zreg->bulk_id == bulk_id)) + { + start_addr = ZBLK_HASH_LIST_REG_ADDR_CALC(zblock_id, i); + + rc = dpp_dtb_tab_up_item_offset_addr_get(dev, + queue_id, + element_id, + dma_addr_offset, + &dump_pa_h, + &dump_pa_l); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_tab_up_item_offset_addr_get",p_dump_desc_buf); + + rc = dpp_dtb_zcam_dump_entry(dev, start_addr, DTB_DUMP_ZCAM_512b, 1, dump_pa_h, dump_pa_l, &dtb_dump_entry); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_zcam_dump_entry",p_dump_desc_buf); + + rc = dpp_dtb_data_write(p_dump_desc_buf, desc_addr_offset, &dtb_dump_entry); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_zcam_dump_entry",p_dump_desc_buf); + + dtb_desc_len++; + dma_addr_offset += 512 / 8; + desc_addr_offset += DTB_LEN_POS_SETP; + + ZXIC_COMM_TRACE_DEV_INFO(DEV_ID(dev), "the Zblock[%d]'s bulk_id:%d Mono Zreg_id :%d \n", zblock_id, p_zreg->bulk_id, i); + } + } + + p_zblk_dn = p_zblk_dn->next; + } + + rc = dpp_dtb_write_dump_desc_info(dev, + queue_id, + element_id, + (ZXIC_UINT32 *)p_dump_desc_buf, + dma_addr_offset / 4, + dtb_desc_len * 4, + (ZXIC_UINT32 *)p_data); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc,"dpp_dtb_write_dump_desc_info",p_dump_desc_buf); + ZXIC_COMM_TRACE_INFO(" dpp_dtb_hash_table_zcam_dump done queue %d element %d.\n", queue_id, element_id); + + zxic_comm_swap(p_data, dma_addr_offset); + ZXIC_COMM_FREE(p_dump_desc_buf); + + *p_dump_len = dma_addr_offset; + + return DPP_OK; +} + +/***********************************************************/ +/** 只dump hash表的zcam内容 +* @param dev_id 设备id +* @param queue_id 队列id 0~127 +* @param sdt_no sdt号 0~255 +* @param pDumpData 出参，dump数据，内存由用户分配，结构体DPP_HASH_ENTRY +* @param entryNum 出参，dump出的有效hash条目 +* @return +* @remark 无 +* @see +* @author cq @date 2023/08/22 +************************************************************/ +DPP_STATUS dpp_dtb_hash_table_only_zcam_dump(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 sdt_no, + ZXIC_UINT8* pDumpData, + ZXIC_UINT32 *entryNum) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_UINT8 *p_data = NULL; + ZXIC_UINT32 data_len = 0; + ZXIC_UINT32 entry_num = 0; + ZXIC_UINT32 bulk_id = 0; + DPP_SE_CFG *p_se_cfg = NULL; + FUNC_ID_INFO *p_func_info = NULL; + DPP_HASH_CFG *p_hash_cfg = NULL; + DPP_SDTTBL_HASH_T sdt_hash = {0}; + HASH_ENTRY_CFG hash_entry_cfg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_INDEX(queue_id, 0, DTB_QUEUE_MAX - 1); + ZXIC_COMM_CHECK_INDEX(sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1); + ZXIC_COMM_CHECK_POINT(pDumpData); + ZXIC_COMM_CHECK_POINT(entryNum); + + ZXIC_COMM_TRACE_INFO("dump hash sdt no: %d\n", sdt_no); + + rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_hash); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_soft_sdt_tbl_get"); + + /* 取出se配置 */ + rc = dpp_se_cfg_get(DEV_ID(dev), &p_se_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_se_cfg_get"); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_se_cfg); + p_func_info = DPP_GET_FUN_INFO(p_se_cfg, sdt_hash.hash_id); + DPP_SE_CHECK_FUN(p_func_info, sdt_hash.hash_id, FUN_HASH); + p_hash_cfg = (DPP_HASH_CFG *)p_func_info->fun_ptr; + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_hash_cfg); + + ZXIC_COMM_MEMSET(&hash_entry_cfg, 0x0, sizeof(HASH_ENTRY_CFG)); + hash_entry_cfg.key_by_size = sdt_hash.key_size; + hash_entry_cfg.key_type = sdt_hash.hash_table_width; + hash_entry_cfg.rst_by_size = 1 << (sdt_hash.rsp_mode + 2); + hash_entry_cfg.table_id = sdt_hash.hash_table_id; + bulk_id = ((hash_entry_cfg.table_id >> 2) & 0x7); + ZXIC_COMM_CHECK_INDEX_UPPER(bulk_id, HASH_BULK_NUM - 1); + + //申请data空间 + p_data = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(DTB_DMUP_DATA_MAX); + ZXIC_COMM_CHECK_POINT(p_data); + ZXIC_COMM_MEMSET(p_data, 0, DTB_DMUP_DATA_MAX); + + rc = dpp_dtb_sdt_hash_zcam_mono_space_dump(dev, + queue_id, + sdt_no, + sdt_hash.hash_id, + bulk_id, + p_data, + &data_len); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_sdt_hash_zcam_mono_space_dump", p_data); + + rc = dpp_dtb_dump_hash_parse(&hash_entry_cfg, + ITEM_RAM, + p_data, + data_len, + pDumpData, + &entry_num); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_dump_hash_parse",p_data); + + *entryNum = entry_num; + + ZXIC_COMM_TRACE_INFO("hash table dump entry num %d end.\n\n", *entryNum); + + ZXIC_COMM_FREE(p_data); + + return rc; +} + +/** dtb dump etcam直接表表项内容 级联eram支持64bit/128bit +* @param dev_id 设备号 +* @param queue_id 队列号 +* @param sdt_no acl表sdt表号 +* @param start_index 要dump的起始index，单位是sdt_no该表的mode +* @param p_dump_data_arr 本次dump出的数据，数据格式与下表格式相同 +* @param entry_num 本次dump实际的条目数 +* @param next_start_index 下次dump是开始的index +* @param finish_flag 整个表dump完成标志，1表示完成，0表示未完成 +* @return +* @remark 无 +* @see +* @author cbb @date 2022/08/30 +************************************************************/ + DPP_STATUS dpp_dtb_acl_table_dump(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 sdt_no, + DPP_DTB_DUMP_INDEX_T start_index, + DPP_DTB_ACL_ENTRY_INFO_T* p_dump_data_arr, + ZXIC_UINT32 *entry_num, + DPP_DTB_DUMP_INDEX_T *next_start_index, + ZXIC_UINT32 *finish_flag) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_UINT32 i = 0; + ZXIC_UINT32 handle = 0; + + ZXIC_UINT32 dump_element_id = 0; + + ZXIC_UINT8 *temp_dump_out_data = NULL; + ZXIC_UINT8 *dump_info_buff = NULL; + ZXIC_UINT8 *p_data_start = NULL; + ZXIC_UINT8 *p_data_640bit = NULL; + ZXIC_UINT8 *p_mask_start = NULL; + ZXIC_UINT8 *p_mask_640bit = NULL; + ZXIC_UINT8 *p_rst_start = NULL; + ZXIC_UINT8 *p_rst_128bit = NULL; + ZXIC_UINT32 *eram_buff = NULL; + + + ZXIC_UINT32 addr_640bit = 0; + ZXIC_UINT32 rd_mask = 0; + ZXIC_UINT32 dump_eram_depth_128bit = 0; + ZXIC_UINT32 eram_row_index = 0; + ZXIC_UINT32 eram_col_index = 0; + + ZXIC_UINT8 cmd_buff[DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; + ZXIC_UINT8 xy_data[DPP_ETCAM_WIDTH_MAX / 8] = {0}; + ZXIC_UINT8 xy_mask[DPP_ETCAM_WIDTH_MAX / 8] = {0}; + ZXIC_UINT8 dm_data[DPP_ETCAM_WIDTH_MAX / 8] = {0}; + ZXIC_UINT8 dm_mask[DPP_ETCAM_WIDTH_MAX / 8] = {0}; + DPP_ETCAM_ENTRY_T entry_xy = {0}; + DPP_ETCAM_ENTRY_T entry_dm = {0}; + DPP_DTB_ACL_ENTRY_INFO_T* p_dump_user_data = NULL; + + ZXIC_UINT32 block_num = 0; + ZXIC_UINT32 etcam_key_mode = 0; + ZXIC_UINT32 etcam_table_id = 0; + ZXIC_UINT32 as_enable = 0; + ZXIC_UINT32 as_eram_baddr = 0; + ZXIC_UINT32 etcam_as_mode = 0; + ZXIC_UINT32 etcam_table_depth = 0; + ZXIC_UINT32 block_idx = 0; + + ZXIC_UINT32 etcam_data_dst_phy_haddr = 0; + ZXIC_UINT32 etcam_data_dst_phy_laddr = 0; + ZXIC_UINT32 etcam_mask_dst_phy_haddr = 0; + ZXIC_UINT32 etcam_mask_dst_phy_laddr = 0; + ZXIC_UINT32 as_rst_dst_phy_haddr = 0; + ZXIC_UINT32 as_rst_dst_phy_laddr = 0; + + ZXIC_UINT32 dtb_desc_addr_offset = 0; + ZXIC_UINT32 dump_data_len = 0; + ZXIC_UINT32 dtb_desc_len = 0; + + ZXIC_UINT32 etcam_data_len_offset = 0; + ZXIC_UINT32 etcam_mask_len_offset = 0; + + DPP_ACL_CFG_EX_T *p_acl_cfg = NULL; + DPP_ACL_TBL_CFG_T *p_tbl_cfg = NULL; + + DPP_SDTTBL_ETCAM_T sdt_etcam_info = {0}; /*SDT内容*/ + ETCAM_DUMP_INFO_T etcam_dump_info = {0}; + DPP_DTB_ENTRY_T dtb_dump_entry = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + + dtb_dump_entry.cmd = cmd_buff; + entry_xy.p_data = xy_data; + entry_xy.p_mask = xy_mask; + entry_dm.p_data = dm_data; + entry_dm.p_mask = dm_mask; + + //从sdt_no中获取SDT配置 + rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_etcam_info); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_soft_sdt_tbl_get"); + etcam_key_mode = sdt_etcam_info.etcam_key_mode; + etcam_as_mode = sdt_etcam_info.as_rsp_mode; + etcam_table_id = sdt_etcam_info.etcam_table_id; + as_enable = sdt_etcam_info.as_en; + as_eram_baddr = sdt_etcam_info.as_eram_baddr; + etcam_table_depth = sdt_etcam_info.etcam_table_depth; + + dpp_acl_cfg_get(&p_acl_cfg);//获取ACL表资源配置 + ZXIC_COMM_CHECK_POINT(p_acl_cfg); + + p_tbl_cfg = p_acl_cfg->acl_tbls + etcam_table_id;//得到该acl表的资源配置 + + if (!p_tbl_cfg->is_used) + { + ZXIC_COMM_TRACE_ERROR("table[ %d ] is not init!\n", etcam_table_id); + ZXIC_COMM_ASSERT(0); + return DPP_ACL_RC_TBL_NOT_INIT; + } + + block_num = p_tbl_cfg->block_num; + + rc = dpp_dtb_dump_addr_set(dev, queue_id, sdt_no, &dump_element_id); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_dump_addr_set"); + + ZXIC_COMM_TRACE_INFO("etcam_key_mode: 0x%x\n", etcam_key_mode); + ZXIC_COMM_TRACE_INFO("etcam_table_id: 0x%x\n", etcam_table_id); + ZXIC_COMM_TRACE_INFO("as_enable: 0x%x\n", as_enable); + ZXIC_COMM_TRACE_INFO("as_eram_baddr: 0x%x\n", as_eram_baddr); + ZXIC_COMM_TRACE_INFO("etcam_as_mode: 0x%x\n", etcam_as_mode); + ZXIC_COMM_TRACE_INFO("block_num: 0x%x\n", block_num); + ZXIC_COMM_TRACE_INFO("dump_element_id: 0x%x\n", dump_element_id); + + dump_info_buff = (ZXIC_UINT8 *) ZXIC_COMM_MALLOC(DPP_DTB_TABLE_DUMP_INFO_BUFF_SIZE * sizeof(ZXIC_UINT8)); + ZXIC_COMM_CHECK_POINT_NO_ASSERT(dump_info_buff); + ZXIC_COMM_MEMSET(dump_info_buff, 0, DPP_DTB_TABLE_DUMP_INFO_BUFF_SIZE * sizeof(ZXIC_UINT8)); + + //etcam data dump描述符，以block为单位，深度是512 起始地址是0 rd_mode = 0xff + for(i = 0; i < block_num; i++) + { + block_idx = p_tbl_cfg->block_array[i]; + + ZXIC_COMM_TRACE_INFO("block_idx: %d\n", block_idx); + + etcam_dump_info.block_sel = block_idx; + etcam_dump_info.addr = 0; + etcam_dump_info.tb_width = 3; + etcam_dump_info.rd_mode = 0xFF; + etcam_dump_info.tb_depth = DPP_ETCAM_RAM_DEPTH; + etcam_dump_info.data_or_mask = DPP_ETCAM_DTYPE_DATA; + + rc = dpp_dtb_tab_up_item_offset_addr_get(dev, + queue_id, + dump_element_id, + dump_data_len, + &etcam_data_dst_phy_haddr, + &etcam_data_dst_phy_laddr); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_tab_up_item_offset_addr_get", dump_info_buff); + rc = dpp_dtb_etcam_dump_entry(dev, + &etcam_dump_info, + etcam_data_dst_phy_haddr, + etcam_data_dst_phy_laddr, + &dtb_dump_entry); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_etcam_dump_entry", dump_info_buff); + rc = dpp_dtb_data_write(dump_info_buff, dtb_desc_addr_offset, &dtb_dump_entry); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_data_write", dump_info_buff); + ZXIC_COMM_MEMSET(cmd_buff, 0, DTB_TABLE_CMD_SIZE_BIT / 8); + + dtb_desc_len += 1; + dtb_desc_addr_offset += DTB_LEN_POS_SETP; + dump_data_len += DPP_ETCAM_RAM_DEPTH * 640 / 8; + } + + etcam_data_len_offset = dump_data_len; + // etcam mask dump描述符，以block为单位，深度是512 起始地址是0 rd_mode = 0xff + for(i = 0; i < block_num; i++) + { + block_idx = p_tbl_cfg->block_array[i]; + + ZXIC_COMM_TRACE_INFO("mask: block_idx: %d\n", block_idx); + + etcam_dump_info.block_sel = block_idx; + etcam_dump_info.addr = 0; + etcam_dump_info.tb_width = 3; + etcam_dump_info.rd_mode = 0xFF; + etcam_dump_info.tb_depth = DPP_ETCAM_RAM_DEPTH; + etcam_dump_info.data_or_mask = DPP_ETCAM_DTYPE_MASK; + + rc = dpp_dtb_tab_up_item_offset_addr_get(dev, + queue_id, + dump_element_id, + dump_data_len, + &etcam_mask_dst_phy_haddr, + &etcam_mask_dst_phy_laddr); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_tab_up_item_offset_addr_get", dump_info_buff); + rc = dpp_dtb_etcam_dump_entry(dev, + &etcam_dump_info, + etcam_mask_dst_phy_haddr, + etcam_mask_dst_phy_laddr, + &dtb_dump_entry); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_etcam_dump_entry", dump_info_buff); + rc = dpp_dtb_data_write(dump_info_buff, dtb_desc_addr_offset, &dtb_dump_entry); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_data_write", dump_info_buff); + ZXIC_COMM_MEMSET(cmd_buff, 0, DTB_TABLE_CMD_SIZE_BIT / 8); + + dtb_desc_len += 1; + dtb_desc_addr_offset += DTB_LEN_POS_SETP; + dump_data_len += DPP_ETCAM_RAM_DEPTH * 640 / 8; + } + etcam_mask_len_offset = dump_data_len; + + //补充级联描述符 + if(as_enable) + { + rc = dtb_eram_index_cal(dev, etcam_as_mode, etcam_table_depth, &dump_eram_depth_128bit, &eram_col_index); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dtb_eram_index_cal", dump_info_buff); + + rc = dpp_dtb_tab_up_item_offset_addr_get(dev, + queue_id, + dump_element_id, + dump_data_len, + &as_rst_dst_phy_haddr, + &as_rst_dst_phy_laddr); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_tab_up_item_offset_addr_get", dump_info_buff); + + rc = dpp_dtb_smmu0_dump_entry(dev, + as_eram_baddr, + dump_eram_depth_128bit, + as_rst_dst_phy_haddr, + as_rst_dst_phy_laddr, + &dtb_dump_entry); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_smmu0_dump_entry", dump_info_buff); + rc = dpp_dtb_data_write(dump_info_buff, dtb_desc_addr_offset, &dtb_dump_entry); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_data_write", dump_info_buff); + ZXIC_COMM_MEMSET(cmd_buff, 0, DTB_TABLE_CMD_SIZE_BIT / 8); + dtb_desc_len += 1; + dtb_desc_addr_offset += DTB_LEN_POS_SETP; + dump_data_len += dump_eram_depth_128bit * 128 / 8; + } + + ZXIC_COMM_TRACE_INFO("dtb_desc_len: 0x%x\n", dtb_desc_len); + ZXIC_COMM_TRACE_INFO("dtb_desc_addr_offset: 0x%x\n", dtb_desc_addr_offset); + ZXIC_COMM_TRACE_INFO("dump_data_len: 0x%x\n", dump_data_len); + + //申请data空间 + temp_dump_out_data = (ZXIC_UINT8 *) ZXIC_COMM_MALLOC(dump_data_len * sizeof(ZXIC_UINT8)); + ZXIC_COMM_CHECK_POINT_MEMORY_FREE_NO_ASSERT(temp_dump_out_data, dump_info_buff); + ZXIC_COMM_MEMSET(temp_dump_out_data, 0, dump_data_len * sizeof(ZXIC_UINT8)); + + /*下发dump描述符*/ + rc = dpp_dtb_write_dump_desc_info(dev, + queue_id, + dump_element_id, + (ZXIC_UINT32 *)dump_info_buff, + dump_data_len / 4, + dtb_desc_len * 4, + (ZXIC_UINT32 *)temp_dump_out_data); + ZXIC_COMM_FREE(dump_info_buff); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc,"dpp_dtb_write_dump_desc_info", temp_dump_out_data); + + //解析数据 + p_data_start = temp_dump_out_data; + p_mask_start = temp_dump_out_data + etcam_data_len_offset; + if(as_enable) + { + p_rst_start = temp_dump_out_data + etcam_mask_len_offset; + } + + for (handle = 0; handle < etcam_table_depth; handle++) + { + p_dump_user_data = p_dump_data_arr + handle; + + if ((p_dump_user_data == NULL) || (p_dump_user_data->key_data == NULL) || (p_dump_user_data->key_mask == NULL)) + { + ZXIC_COMM_TRACE_ERROR("etcam handle 0x%x data user buff is NULL!\n", handle); + ZXIC_COMM_FREE(temp_dump_out_data); + return DPP_ERR; + } + + if(as_enable) + { + if(p_dump_user_data->p_as_rslt == NULL) + { + ZXIC_COMM_TRACE_ERROR("etcam handle 0x%x as data buff is NULL!\n", handle); + ZXIC_COMM_FREE(temp_dump_out_data); + return DPP_ERR; + } + } + + p_dump_user_data->handle = handle; + + addr_640bit = handle / (1U << etcam_key_mode); + rd_mask = (((1U << (8U >> etcam_key_mode)) - 1) << ((8U >> etcam_key_mode) * (handle % (1U << etcam_key_mode)))) & 0xFF; + + p_data_640bit = p_data_start + addr_640bit * 640 / 8; + p_mask_640bit = p_mask_start + addr_640bit * 640 / 8; + + dpp_dtb_etcam_ind_data_get(dev, p_data_640bit, rd_mask, entry_xy.p_data); + dpp_dtb_etcam_ind_data_get(dev, p_mask_640bit, rd_mask, entry_xy.p_mask); + + rc = dpp_etcam_xy_to_dm(&entry_dm, &entry_xy, DPP_ETCAM_ENTRY_SIZE_GET(etcam_key_mode)); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_etcam_xy_to_dm", temp_dump_out_data); + + ZXIC_COMM_MEMCPY(p_dump_user_data->key_data, entry_dm.p_data, DPP_ETCAM_ENTRY_SIZE_GET(etcam_key_mode)); + ZXIC_COMM_MEMCPY(p_dump_user_data->key_mask, entry_dm.p_mask, DPP_ETCAM_ENTRY_SIZE_GET(etcam_key_mode)); + + if(as_enable) + { + rc = dtb_eram_index_cal(dev, etcam_as_mode, handle, &eram_row_index, &eram_col_index); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dtb_eram_index_cal", temp_dump_out_data); + p_rst_128bit = p_rst_start + eram_row_index * DTB_LEN_POS_SETP; + + eram_buff = (ZXIC_UINT32*)p_rst_128bit; + + if(etcam_as_mode == ERAM128_TBL_128b) + { + ZXIC_COMM_MEMCPY(p_dump_user_data->p_as_rslt, eram_buff, (128 / 8)); + } + else if(etcam_as_mode == ERAM128_TBL_64b) + { + ZXIC_COMM_MEMCPY(p_dump_user_data->p_as_rslt, eram_buff + ((1 - eram_col_index) << 1), (64 / 8)); + } + } + + } + + *entry_num = etcam_table_depth; + *finish_flag = 1; + ZXIC_COMM_TRACE_INFO(" etcam table dump entry num %d, finish flag %d\n\n", *entry_num, *finish_flag); + + ZXIC_COMM_FREE(temp_dump_out_data); + + return DPP_OK; +} + +#endif + +#if ZXIC_REAL("DTB DEBUG PRINT") + +/*打印buff中数据，size 单位 字节*/ +ZXIC_VOID dpp_data_buff_print(ZXIC_UINT8 *buff, ZXIC_UINT32 size) +{ + + ZXIC_UINT32 i = 0; + ZXIC_UINT32 j = 0; + ZXIC_UINT8 *temp_buff = NULL; + + ZXIC_COMM_PRINT("buff data is:\n"); + + for (i = 0; i < size / 4 / 4; i++) + { + temp_buff = buff + 16 * i; + for(j = 0; j < 4; j++) + { + ZXIC_COMM_PRINT("0x%08x ", *((ZXIC_UINT32*)(temp_buff + 4 * j))); + } + ZXIC_COMM_PRINT("\n"); + } + + ZXIC_COMM_PRINT("\n"); +} + +ZXIC_VOID dpp_acl_data_print(ZXIC_UINT8 *p_data, ZXIC_UINT8 *p_mask, ZXIC_UINT32 etcam_mode) +{ + int i = 0; + int data_len = 0; + + data_len = DPP_ETCAM_ENTRY_SIZE_GET(etcam_mode); + + if(data_len > 80) + { + return; + } + + ZXIC_COMM_PRINT("%s:", "data"); + + for (i = 0; i < data_len; i++) + { + if ((i % 10) == 0) + { + ZXIC_COMM_PRINT("\n"); + } + + ZXIC_COMM_PRINT("%02x", p_data[i]); + } + + ZXIC_COMM_PRINT("\n"); + + ZXIC_COMM_PRINT("%s:", "mask"); + + for (i = 0; i < data_len; i++) + { + if ((i % 10) == 0) + { + ZXIC_COMM_PRINT("\n"); + } + + ZXIC_COMM_PRINT("%02x", p_mask[i]); + } + ZXIC_COMM_PRINT("\n"); +} + +ZXIC_VOID dpp_dtb_data_print(ZXIC_UINT8 *p_data, ZXIC_UINT32 len) +{ + int i = 0; + int cycle = len / 4; + int remain = len % 4; + + ZXIC_COMM_PRINT("%s:", "data:\n"); + + for(i = 0; i < cycle; i++) + { + ZXIC_COMM_PRINT("0x%02x %02x %02x %02x \n", p_data[4 * i], p_data[4 * i + 1], p_data[4 * i + 2], p_data[4 * i + 3]); + } + + for(i = 0; i < remain; i++) + { + ZXIC_COMM_PRINT("0x%02x", p_data[cycle * 4 + i]); + } + ZXIC_COMM_PRINT("\n"); +} + +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/se/dpp_dtb_table_api.c b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/se/dpp_dtb_table_api.c new file mode 100644 index 0000000..fcffc01 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/se/dpp_dtb_table_api.c @@ -0,0 +1,643 @@ +#include "zxic_common.h" +#include "dpp_dev.h" +#include "dpp_dtb_table_api.h" +#include "dpp_dtb_cfg.h" +#include "dpp_apt_se.h" +#include "zxic_comm_rb_tree.h" +#include "dpp_dtb_table.h" +#include "dpp_sdt.h" +#include "dpp_agent_channel.h" +#include "dpp_dtb.h" +#include "dpp_kernel_init.h" + +#define EP_NUM (5) +static ZXIC_UINT32 msix_interrupt_mode = 1;//1为dbi中断，0为match中断 +static ZXIC_RB_CFG g_dtb_queue_dump_addr_rb[DPP_DEV_SLOT_MAX][DPP_DEV_CHANNEL_MAX][DPP_DTB_QUEUE_NUM_MAX] = {{{{0}}}}; +static ZXIC_UINT32 hardware_ep_id[EP_NUM] = {5, 6, 7, 8, 9}; + +typedef struct dpp_dtb_dump_addr_info_t +{ + ZXIC_UINT32 sdt_no; + ZXIC_UINT64 phyAddr; + ZXIC_UINT64 virAddr; + ZXIC_UINT32 size; +}DPP_DTB_DUMP_ADDR_INFO_T; + +ZXIC_UINT32 dpp_dtb_ep_id_get(ZXIC_UINT32 soft_ep_id) +{ + return hardware_ep_id[soft_ep_id]; +} + +ZXIC_RB_CFG* dpp_dtb_dump_addr_rb_get(DPP_DEV_T *dev, ZXIC_UINT32 queue_id) +{ + ZXIC_COMM_CHECK_POINT_RETURN_NULL(dev); + ZXIC_COMM_CHECK_INDEX_RETURN_NULL(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX_RETURN_NULL(DEV_ID(dev), queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1); + return &g_dtb_queue_dump_addr_rb[DEV_PCIE_SLOT(dev)][DEV_ID(dev)][queue_id]; +} + +ZXIC_UINT32 dpp_dtb_dump_addr_rb_init(DPP_DEV_T *dev, ZXIC_UINT32 queue_id) +{ + ZXIC_UINT32 rc = DPP_OK; + ZXIC_RB_CFG *p_dtb_dump_addr_rb = NULL; + + ZXIC_COMM_CHECK_POINT_NO_ASSERT(dev); + ZXIC_COMM_CHECK_INDEX_NO_ASSERT(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1); + + p_dtb_dump_addr_rb = dpp_dtb_dump_addr_rb_get(dev, queue_id); + + rc = zxic_comm_rb_init(p_dtb_dump_addr_rb, 0, ZXIC_SIZEOF(DPP_DTB_DUMP_ADDR_INFO_T), dpp_apt_table_key_cmp); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "zxic_comm_rb_init"); + + return rc; +} + +ZXIC_UINT32 dpp_dtb_dump_addr_rb_destroy(DPP_DEV_T *dev, ZXIC_UINT32 queue_id) +{ + ZXIC_UINT32 rc = DPP_OK; + + D_NODE *p_node = NULL; + ZXIC_RB_TN *p_rb_tn = NULL; + DPP_DTB_DUMP_ADDR_INFO_T *p_rbkey = NULL; + D_HEAD *p_head_dtb_rb = NULL; + ZXIC_RB_CFG *p_dtb_dump_addr_rb = NULL; + + ZXIC_UINT32 sdt_no = 0; + + ZXIC_COMM_CHECK_POINT_NO_ASSERT(dev); + ZXIC_COMM_CHECK_INDEX_NO_ASSERT(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1); + + p_dtb_dump_addr_rb = dpp_dtb_dump_addr_rb_get(dev, queue_id); + ZXIC_COMM_CHECK_POINT_NO_ASSERT(p_dtb_dump_addr_rb); + + p_head_dtb_rb = &p_dtb_dump_addr_rb->tn_list; + ZXIC_COMM_CHECK_POINT_NO_ASSERT(p_head_dtb_rb); + + while(p_head_dtb_rb->used) + { + p_node = p_head_dtb_rb->p_next; + p_rb_tn = (ZXIC_RB_TN *)p_node->data; + p_rbkey = (DPP_DTB_DUMP_ADDR_INFO_T *)p_rb_tn->p_key; + + sdt_no = p_rbkey->sdt_no; + rc = dpp_dtb_dump_sdt_addr_clear(dev, queue_id, sdt_no); + if (DPP_HASH_RC_DEL_SRHFAIL == rc) + { + ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "dtb dump delete key is not exist, std:%d\n", sdt_no); + } + else + { + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_dump_sdt_addr_clear"); + } + } + + rc = zxic_comm_rb_destroy(p_dtb_dump_addr_rb); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "zxic_comm_rb_init"); + + return rc; +} + +/*dump地址信息获取*/ +ZXIC_UINT32 dpp_dtb_dump_sdt_addr_get(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 sdt_no, + ZXIC_UINT64 *phy_addr, + ZXIC_UINT64 *vir_addr, + ZXIC_UINT32 *size) +{ + ZXIC_UINT32 rc = DPP_OK; + + DPP_DTB_DUMP_ADDR_INFO_T dtb_dump_addr_info = {0}; + ZXIC_RB_CFG *p_dtb_dump_addr_rb = NULL; + + ZXIC_COMM_CHECK_POINT_NO_ASSERT(dev); + ZXIC_COMM_CHECK_INDEX_NO_ASSERT(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1); + + dtb_dump_addr_info.sdt_no = sdt_no; + p_dtb_dump_addr_rb = dpp_dtb_dump_addr_rb_get(dev, queue_id); + rc = dpp_apt_sw_list_search(p_dtb_dump_addr_rb, &dtb_dump_addr_info, sizeof(DPP_DTB_DUMP_ADDR_INFO_T)); + if (rc == DPP_OK) + { + ZXIC_COMM_TRACE_INFO("search sdt_no %d success.\n", sdt_no); + } + else + { + ZXIC_COMM_TRACE_ERROR("search sdt_no %d fail.\n", sdt_no); + return rc; + } + + *phy_addr = dtb_dump_addr_info.phyAddr; + *vir_addr = dtb_dump_addr_info.virAddr; + *size = dtb_dump_addr_info.size; + + ZXIC_COMM_TRACE_INFO("dpp_dtb_dump_sdt_addr_get: queue :%d\n", queue_id); + ZXIC_COMM_TRACE_INFO("dpp_dtb_dump_sdt_addr_get: sdt_no :%d\n", sdt_no); + ZXIC_COMM_TRACE_INFO("dpp_dtb_dump_sdt_addr_get: phyAddr :0x%016llx\n", dtb_dump_addr_info.phyAddr); + ZXIC_COMM_TRACE_INFO("dpp_dtb_dump_sdt_addr_get: vir_addr :0x%016llx\n", dtb_dump_addr_info.virAddr); + ZXIC_COMM_TRACE_INFO("dpp_dtb_dump_sdt_addr_get: size :0x%x\n", dtb_dump_addr_info.size); + + return rc; +} + +/***********************************************************/ +/** DTB通道申请 +* @param devId NP设备号 +* @param pName 申请DTB通道的唯一设备名(最大32字符) +* @param pQueueId 申请到的DTB通道编号 +* @return +* @remark 无 +* @see +* @author cbb @date 2023/07/03 +************************************************************/ +ZXIC_UINT32 dpp_dtb_queue_requst(DPP_DEV_T *dev, ZXIC_CONST ZXIC_UINT8* pName, + ZXIC_UINT16 vPort, + ZXIC_UINT32 *pQueueId) +{ + ZXIC_UINT32 rc = DPP_OK; + ZXIC_UINT32 queue_id = 0; + ZXIC_MUTEX_T *p_dtb_mutex = NULL; + DPP_DEV_MUTEX_TYPE_E mutex = 0; + ZXIC_UINT32 vport_info = (ZXIC_UINT32)vPort; + + ZXIC_COMM_CHECK_POINT_NO_ASSERT(dev); + ZXIC_COMM_CHECK_INDEX_NO_ASSERT(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), pName); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), pQueueId); + + //使用代理通道要加锁 + mutex = DPP_DEV_MUTEX_T_DTB; + rc = dpp_dev_opr_mutex_get(DEV_ID(dev), (ZXIC_UINT32)mutex, &p_dtb_mutex); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dev_opr_mutex_get"); + + rc = zxic_comm_mutex_lock(p_dtb_mutex); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "zxic_comm_mutex_lock"); + + rc = dpp_agent_channel_dtb_queue_request(dev, pName, vport_info, &queue_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_agent_channel_dtb_queue_request", p_dtb_mutex); + + rc = zxic_comm_mutex_unlock(p_dtb_mutex); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "zxic_comm_mutex_unlock"); + + rc = dpp_dtb_dump_addr_rb_init(dev, queue_id); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_dump_addr_rb_init"); + + *pQueueId = queue_id; + + ZXIC_COMM_PRINT("dpp_dtb_queue_requst:slot %d name %s vport 0x%x queue_id %d\n", DEV_PCIE_SLOT(dev), pName, vport_info, queue_id); + + return rc; +} + +/***********************************************************/ +/** DTB通道释放 +* @param devId NP设备号 +* @param pName 要释放DTB通道的唯一设备名(最大32字符) +* @param pQueueId 要释放的DTB通道编号 +* @return +* @remark 无 +* @see +* @author cbb @date 2023/07/03 +************************************************************/ +ZXIC_UINT32 dpp_dtb_queue_release(DPP_DEV_T *dev, ZXIC_CONST ZXIC_UINT8* pName, + ZXIC_UINT32 queueId) +{ + ZXIC_UINT32 rc = DPP_OK; + ZXIC_MUTEX_T *p_dtb_mutex = NULL; + DPP_DEV_MUTEX_TYPE_E mutex = 0; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX_NO_ASSERT(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), queueId, 0, DPP_DTB_QUEUE_NUM_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), pName); + + ZXIC_COMM_TRACE_INFO("dpp_dtb_queue_release:queue_id %d\n", queueId); + + //使用代理通道要加锁 + mutex = DPP_DEV_MUTEX_T_DTB; + rc = dpp_dev_opr_mutex_get(DEV_ID(dev), (ZXIC_UINT32)mutex, &p_dtb_mutex); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dev_opr_mutex_get"); + + rc = zxic_comm_mutex_lock(p_dtb_mutex); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "zxic_comm_mutex_lock"); + + rc = dpp_agent_channel_dtb_queue_release(dev, pName, queueId); + + if(rc == DPP_RC_DTB_QUEUE_NOT_ALLOC) + { + ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "dtb slot %d queue id %d not request. \n", DEV_PCIE_SLOT(dev), queueId); + } + + if(rc == DPP_RC_DTB_QUEUE_NAME_ERROR) + { + ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "dtb slot %d queue %d name error. \n", DEV_PCIE_SLOT(dev), queueId); + } + + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_agent_channel_dtb_queue_release", p_dtb_mutex); + + rc = zxic_comm_mutex_unlock(p_dtb_mutex); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "zxic_comm_mutex_unlock"); + + rc = dpp_dtb_dump_addr_rb_destroy(dev, queueId); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_dump_addr_rb_destroy"); + + rc = dpp_dtb_queue_id_free(dev, queueId); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_queue_id_free"); + + ZXIC_COMM_PRINT("dpp_dtb_queue_release:slot %d name %s queue_id %d\n", DEV_PCIE_SLOT(dev), pName, queueId); + + return rc; +} + +/***********************************************************/ +/** DTB通道用户信息配置 +* @param devId NP设备号 +* @param queueId DTB通道编号 +* @param vPort vport信息 +* @param vector 中断号 +* @return +* @remark 无 +* @see +* @author cbb @date 2023/07/03 +************************************************************/ +ZXIC_UINT32 dpp_dtb_user_info_set(DPP_DEV_T *dev, + ZXIC_UINT32 queueId, + ZXIC_UINT16 vPort, + ZXIC_UINT32 vector) +{ + ZXIC_UINT32 rc = DPP_OK; + + ZXIC_UINT32 temp_epid; + ZXIC_UINT32 temp_func_active; + ZXIC_UINT32 temp_func_num; + ZXIC_UINT32 temp_vfunc_num; + ZXIC_UINT32 virtioPort = (ZXIC_UINT32)vPort; + + DPP_DTB_QUEUE_VM_INFO_T vm_info = {0}; + DPP_DTB_MGR_T *p_dtb_mgr = ZXIC_NULL; + + ZXIC_COMM_CHECK_POINT_NO_ASSERT(dev); + ZXIC_COMM_CHECK_INDEX_NO_ASSERT(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), queueId, 0, DPP_DTB_QUEUE_NUM_MAX - 1); + + p_dtb_mgr = dpp_dtb_mgr_get(DEV_PCIE_SLOT(dev), DEV_ID(dev)); + if (p_dtb_mgr == ZXIC_NULL) + { + ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "ErrorCode[0x%x]: DTB Manager is not exist!!!\n", DPP_RC_DTB_MGR_NOT_EXIST); + return DPP_RC_DTB_MGR_NOT_EXIST; + } + + ZXIC_COMM_UINT32_GET_BITS(temp_epid, virtioPort, VPORT_EPID_BT_START, VPORT_EPID_BT_LEN); + ZXIC_COMM_UINT32_GET_BITS(temp_func_active, virtioPort, VPORT_FUNC_ACTIVE_BT_START, VPORT_FUNC_ACTIVE_BT_LEN); + ZXIC_COMM_UINT32_GET_BITS(temp_func_num, virtioPort, VPORT_FUNC_NUM_BT_START, VPORT_FUNC_NUM_BT_LEN); + ZXIC_COMM_UINT32_GET_BITS(temp_vfunc_num, virtioPort, VPORT_VFUNC_NUM_BT_START, VPORT_VFUNC_NUM_BT_LEN); + + rc = dpp_dtb_queue_vm_info_get(dev, queueId, &vm_info); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_queue_vm_info_get"); + + vm_info.dbi_en = msix_interrupt_mode; + vm_info.epid = dpp_dtb_ep_id_get(temp_epid); + vm_info.vfunc_num = temp_vfunc_num; + vm_info.func_num = temp_func_num; + vm_info.vfunc_active = temp_func_active; + vm_info.vector = vector; + + ZXIC_COMM_PRINT("dpp_dtb_user_info_set:queue %d vport 0x%x, vector:%x\n", queueId, vPort, vector); + ZXIC_COMM_PRINT("dpp_dtb_user_info_set:dbi_en 0x%x\n", vm_info.dbi_en); + ZXIC_COMM_PRINT("dpp_dtb_user_info_set:epid 0x%x\n", vm_info.epid); + ZXIC_COMM_PRINT("dpp_dtb_user_info_set:vfunc_num 0x%x\n", vm_info.vfunc_num); + ZXIC_COMM_PRINT("dpp_dtb_user_info_set:func_num 0x%x\n", vm_info.func_num); + ZXIC_COMM_PRINT("dpp_dtb_user_info_set:vfunc_active 0x%x\n", vm_info.vfunc_active); + + p_dtb_mgr->queue_info[queueId].vport = vPort; + p_dtb_mgr->queue_info[queueId].vector = vector; + + rc = dpp_dtb_queue_vm_info_set(dev, queueId, &vm_info); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_queue_vm_info_set"); + + return rc; +} + +/***********************************************************/ +/** DTB通道下表空间地址设置,空间大小[32*(16+16*1024)B] +* @param devId NP设备号 +* @param queueId DTB通道编号 +* @param phyAddr 物理地址 +* @param virAddr 虚拟地址 +* @return +* @remark 无 +* @see +* @author cbb @date 2023/07/03 +************************************************************/ +ZXIC_UINT32 dpp_dtb_queue_down_table_addr_set(DPP_DEV_T *dev, + ZXIC_UINT32 queueId, + ZXIC_UINT64 phyAddr, + ZXIC_UINT64 virAddr) +{ + ZXIC_UINT32 rc = DPP_OK; + + ZXIC_COMM_CHECK_POINT_NO_ASSERT(dev); + ZXIC_COMM_CHECK_INDEX_NO_ASSERT(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), queueId, 0, DPP_DTB_QUEUE_NUM_MAX - 1); + + ZXIC_COMM_PRINT("dpp_dtb_queue_down_table_addr_set:slot %d queue %d phyAddr 0x%llx\n", DEV_PCIE_SLOT(dev), queueId, phyAddr); + ZXIC_COMM_PRINT("dpp_dtb_queue_down_table_addr_set:slot %d queue %d virAddr 0x%llx\n", DEV_PCIE_SLOT(dev), queueId, virAddr); + + rc = dpp_dtb_down_channel_addr_set(dev, + queueId, + phyAddr, + virAddr, + 0); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_down_channel_addr_set"); + + return rc; +} + +/***********************************************************/ +/** DTB通道dump空间地址设置,空间大小[32*(16+16*1024)B] +* @param devId NP设备号 +* @param pName 要释放DTB通道的设备名 +* @param phyAddr 物理地址 +* @param virAddr 虚拟地址 +* @return +* @remark 无 +* @see +* @author cbb @date 2023/07/03 +************************************************************/ +ZXIC_UINT32 dpp_dtb_queue_dump_table_addr_set(DPP_DEV_T *dev, + ZXIC_UINT32 queueId, + ZXIC_UINT64 phyAddr, + ZXIC_UINT64 virAddr) +{ + ZXIC_UINT32 rc = DPP_OK; + + ZXIC_COMM_CHECK_POINT_NO_ASSERT(dev); + ZXIC_COMM_CHECK_INDEX_NO_ASSERT(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), queueId, 0, DPP_DTB_QUEUE_NUM_MAX - 1); + + ZXIC_COMM_PRINT("dpp_dtb_queue_dump_table_addr_set:slot %d queue %d phyAddr 0x%llx\n", DEV_PCIE_SLOT(dev), queueId, phyAddr); + ZXIC_COMM_PRINT("dpp_dtb_queue_dump_table_addr_set:slot %d queue %d virAddr 0x%llx\n", DEV_PCIE_SLOT(dev), queueId, virAddr); + + rc = dpp_dtb_dump_channel_addr_set(dev, + queueId, + phyAddr, + virAddr, + 0); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_dump_channel_addr_set"); + + return rc; +} + +/***********************************************************/ +/** 大批量dump一个流表使用的地址空间配置 +* @param devId NP设备号 +* @param queueId DTB队列编号 +* @param sdtNo 流表std号 +* @param phyAddr 物理地址 +* @param virAddr 虚拟地址 +* @param size (最大64MB) +* @return +* @remark 无 +* @see +* @author cbb @date 2023/07/03 +************************************************************/ +ZXIC_UINT32 dpp_dtb_dump_sdt_addr_set(DPP_DEV_T *dev, + ZXIC_UINT32 queueId, + ZXIC_UINT32 sdtNo, + ZXIC_UINT64 phyAddr, + ZXIC_UINT64 virAddr, + ZXIC_UINT32 size) +{ + ZXIC_UINT32 rc = DPP_OK; + + DPP_DTB_DUMP_ADDR_INFO_T dtb_dump_addr_info = {0}; + ZXIC_RB_CFG *p_dtb_dump_addr_rb = NULL; + + ZXIC_COMM_CHECK_POINT_NO_ASSERT(dev); + ZXIC_COMM_CHECK_INDEX_NO_ASSERT(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), queueId, 0, DPP_DTB_QUEUE_NUM_MAX - 1); + + ZXIC_COMM_TRACE_INFO("dpp_dtb_dump_sdt_addr_set: slotId :0x%x\n", DEV_PCIE_SLOT(dev)); + ZXIC_COMM_TRACE_INFO("dpp_dtb_dump_sdt_addr_set: queueId :0x%x\n", queueId); + ZXIC_COMM_TRACE_INFO("dpp_dtb_dump_sdt_addr_set: sdtNo :0x%x\n", sdtNo); + ZXIC_COMM_TRACE_INFO("dpp_dtb_dump_sdt_addr_set: phyAddr :0x%016llx\n", phyAddr); + ZXIC_COMM_TRACE_INFO("dpp_dtb_dump_sdt_addr_set: virAddr :0x%016llx\n", virAddr); + ZXIC_COMM_TRACE_INFO("dpp_dtb_dump_sdt_addr_set: size :0x%x\n", size); + + dtb_dump_addr_info.sdt_no = sdtNo; + dtb_dump_addr_info.phyAddr = phyAddr; + dtb_dump_addr_info.virAddr = virAddr; + dtb_dump_addr_info.size = size; + + p_dtb_dump_addr_rb = dpp_dtb_dump_addr_rb_get(dev, queueId); + ZXIC_COMM_CHECK_POINT_NO_ASSERT(p_dtb_dump_addr_rb); + ZXIC_COMM_CHECK_INDEX_UPPER_NO_ASSERT(p_dtb_dump_addr_rb->key_size, (ZXIC_UINT32)sizeof(DPP_DTB_DUMP_ADDR_INFO_T)); + + rc = dpp_apt_sw_list_insert(p_dtb_dump_addr_rb, &dtb_dump_addr_info, sizeof(DPP_DTB_DUMP_ADDR_INFO_T)); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_apt_sw_list_insert"); + + return rc; +} + +/***********************************************************/ +/** 清除大批量dump一个流表使用的地址空间配置 +* @param devId NP设备号 +* @param queueId DTB队列编号 +* @param sdtNo 流表std号 +* @return +* @remark 无 +* @see +* @author cbb @date 2023/07/03 +************************************************************/ +ZXIC_UINT32 dpp_dtb_dump_sdt_addr_clear(DPP_DEV_T *dev, + ZXIC_UINT32 queueId, + ZXIC_UINT32 sdtNo) +{ + ZXIC_UINT32 rc = DPP_OK; + + DPP_DTB_DUMP_ADDR_INFO_T dtb_dump_addr_info = {0}; + ZXIC_RB_CFG *p_dtb_dump_addr_rb = NULL; + + ZXIC_COMM_CHECK_POINT_NO_ASSERT(dev); + ZXIC_COMM_CHECK_INDEX_NO_ASSERT(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), queueId, 0, DPP_DTB_QUEUE_NUM_MAX - 1); + + dtb_dump_addr_info.sdt_no = sdtNo; + + p_dtb_dump_addr_rb = dpp_dtb_dump_addr_rb_get(dev, queueId); + rc = dpp_apt_sw_list_delete(p_dtb_dump_addr_rb, &dtb_dump_addr_info, sizeof(DPP_DTB_DUMP_ADDR_INFO_T)); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_apt_sw_list_delete"); + + return rc; +} + +/***********************************************************/ +/** 释放当前sdt下的所有流表(硬件方式) +* (适用于进程启动后，仅配置流表资源，软件未配置流表，但需要删除硬件上已配置流表的场景) +* @param dev +* @param queue_id 队列号 +* @param sdt_no sdt号 +* @return +* @remark 无 +* @see +* @author cq @date 2023/12/04 +************************************************************/ +DPP_STATUS dpp_dtb_hash_offline_delete(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 sdt_no) + +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 entryNum = 0; + ZXIC_UINT32 index = 0; + ZXIC_UINT32 max_item_num = DTB_DUMP_MULTICAST_MAC_DUMP_NUM; + ZXIC_UINT8* pDumpData = NULL; + ZXIC_UINT8 *pKey = NULL; + ZXIC_UINT8 *pRst = NULL; + ZXIC_UINT32 element_id = 0; + + ZXIC_UINT32 dma_size = 0; + ZXIC_UINT64 dma_phy_addr = 0; + ZXIC_UINT64 dma_vir_addr = 0; + + DPP_DTB_HASH_ENTRY_INFO_T *p_dtb_hash_entry = NULL; + DPP_DTB_HASH_ENTRY_INFO_T *p_temp_entry = NULL; + DPP_SDTTBL_HASH_T sdt_hash_info = {0}; /*SDT内容*/ + + ZXIC_COMM_CHECK_POINT_NO_ASSERT(dev); + ZXIC_COMM_CHECK_INDEX_NO_ASSERT(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + + //从sdt_no中获取SDT配置 + rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_hash_info); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_soft_sdt_tbl_get"); + + pDumpData = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(max_item_num*sizeof(DPP_DTB_HASH_ENTRY_INFO_T)); + ZXIC_COMM_CHECK_POINT_NO_ASSERT(pDumpData); + pKey = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(max_item_num * HASH_KEY_MAX); + ZXIC_COMM_CHECK_POINT_MEMORY_FREE_NO_ASSERT(pKey, pDumpData); + pRst = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(max_item_num * HASH_RST_MAX); + ZXIC_COMM_CHECK_POINT_MEMORY_FREE2PTR_NO_ASSERT(pRst, pKey, pDumpData); + + ZXIC_COMM_MEMSET(pDumpData,0x0,max_item_num*sizeof(DPP_DTB_HASH_ENTRY_INFO_T)); + ZXIC_COMM_MEMSET(pKey,0x0,max_item_num*HASH_KEY_MAX); + ZXIC_COMM_MEMSET(pRst,0x0,max_item_num*HASH_RST_MAX); + + p_dtb_hash_entry = (DPP_DTB_HASH_ENTRY_INFO_T *)pDumpData; + for(index = 0;indexp_actu_key = pKey + index * HASH_KEY_MAX; + p_temp_entry->p_rst = pRst + index * HASH_RST_MAX; + } + + rc = dtb_sdt_dump_dma_alloc(dev, DTB_SDT_DUMP_SIZE, &dma_phy_addr, &dma_vir_addr); + ZXIC_COMM_CHECK_RC_MEMORY_FREE3PTR_NO_ASSERT(rc, "dtb_sdt_dump_dma_alloc", pRst, pKey, pDumpData); + + rc = dpp_dtb_dump_sdt_addr_set(dev, queue_id, sdt_no, dma_phy_addr, dma_vir_addr, DTB_SDT_DUMP_SIZE); + ZXIC_COMM_CHECK_RC_MEMORY_FREE3PTR_NO_ASSERT(rc, "dpp_dtb_dump_sdt_addr_set", pRst, pKey, pDumpData); + + rc = dpp_dtb_hash_table_only_zcam_dump(dev, queue_id, sdt_no, pDumpData, &entryNum); + + dpp_dtb_dump_sdt_addr_get(dev, queue_id, sdt_no, &dma_phy_addr, &dma_vir_addr, &dma_size); + dtb_sdt_dump_dma_release(dev, dma_size, dma_phy_addr, dma_vir_addr); + dpp_dtb_dump_sdt_addr_clear(dev, queue_id, sdt_no); + + if(DPP_OK != rc) + { + ZXIC_COMM_TRACE_ERROR("dpp_dtb_hash_table_only_zcam_dump: sdt :0x%x fail\n", sdt_no); + ZXIC_COMM_FREE(p_dtb_hash_entry); + ZXIC_COMM_FREE(pKey); + ZXIC_COMM_FREE(pRst); + return rc; + } + + ZXIC_COMM_PRINT("dpp_dtb_hash_table_only_zcam_dump valid entry num is %u\n",entryNum); + + for(index = 0; index < entryNum; index++) + { + p_temp_entry = p_dtb_hash_entry + index; + // //打印数据 + dpp_dtb_data_print(p_temp_entry->p_actu_key, DPP_GET_ACTU_KEY_BY_SIZE(sdt_hash_info.key_size) + 1); + dpp_dtb_data_print(p_temp_entry->p_rst, 4 * (0x1 << sdt_hash_info.rsp_mode)); + } + + rc = dpp_dtb_hash_dma_delete_hardware(dev, queue_id, sdt_no, entryNum, p_dtb_hash_entry, &element_id); + ZXIC_COMM_FREE(p_dtb_hash_entry); + ZXIC_COMM_FREE(pKey); + ZXIC_COMM_FREE(pRst); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_hash_dma_delete_hardware"); + + return DPP_OK; +} + +/***********************************************************/ +/** 在线释放当前sdt下的所有流表表项 +* (适用于进程正常退出前删除表项，软件上有存储表项) +* @param dev_id 设备号 +* @param queue_id 队列号 +* @param sdt_no sdt号 +* @return +* @remark 无 +* @see +* @author cq @date 2023/12/04 +************************************************************/ +DPP_STATUS dpp_dtb_hash_online_delete(DPP_DEV_T *dev, + ZXIC_UINT32 queue_id, + ZXIC_UINT32 sdt_no) +{ + ZXIC_UINT32 rc = 0; + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT8 key_valid = 0; + ZXIC_UINT32 table_id = 0; + ZXIC_UINT32 key_type = 0; + ZXIC_UINT32 element_id = 0; + + D_NODE *p_node = NULL; + ZXIC_RB_TN *p_rb_tn = NULL; + D_HEAD *p_head_hash_rb = NULL; + DPP_HASH_CFG *p_hash_cfg = NULL; + DPP_HASH_RBKEY_INFO *p_rbkey = NULL; + HASH_ENTRY_CFG hash_entry_cfg = {0}; + DPP_DTB_HASH_ENTRY_INFO_T hashEntry = {0}; + + ZXIC_COMM_CHECK_POINT_NO_ASSERT(dev); + dev_id = DEV_ID(dev); + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, queue_id, 0, DTB_QUEUE_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1); + + //从sdt_no中获取hash配置 + rc = dpp_hash_get_hash_info_from_sdt(dev_id, sdt_no, &hash_entry_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_hash_get_hash_info_from_sdt"); + + p_hash_cfg = hash_entry_cfg.p_hash_cfg; + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_hash_cfg); + + p_head_hash_rb = &p_hash_cfg->hash_rb.tn_list; + p_node = p_head_hash_rb->p_next; + while(p_node) + { + p_rb_tn = (ZXIC_RB_TN *)p_node->data; + p_rbkey = (DPP_HASH_RBKEY_INFO *)p_rb_tn->p_key; + hashEntry.p_actu_key = p_rbkey->key+1; + hashEntry.p_rst = p_rbkey->key; + + key_valid = DPP_GET_HASH_KEY_VALID(p_rbkey->key); + table_id = DPP_GET_HASH_TBL_ID(p_rbkey->key); + key_type = DPP_GET_HASH_KEY_TYPE(p_rbkey->key); + if((!key_valid) + || (table_id != hash_entry_cfg.table_id) + || (key_type != hash_entry_cfg.key_type)) + { + p_node = p_node->next; + continue; + } + p_node = p_node->next; + + rc = dpp_dtb_hash_dma_delete(dev, queue_id,sdt_no,1,&hashEntry,&element_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_dtb_hash_dma_delete"); + } + + return DPP_OK; +} diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/se/dpp_hash.c b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/se/dpp_hash.c new file mode 100755 index 0000000..cc620f8 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/se/dpp_hash.c @@ -0,0 +1,2960 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_hash.c +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : wcl +* 完成日期 : 2014/02/08 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ + +#include "zxic_common.h" + +#include "dpp_dev.h" +#include "dpp_module.h" +#include "dpp_se_cfg.h" +#include "dpp_hash_crc.h" +#include "dpp_hash.h" +#include "dpp_se.h" +#include "dpp_se_reg.h" +#include "dpp_reg_api.h" +#include "dpp_reg_info.h" +#include "dpp_se4k_reg.h" +#include "dpp_sdt.h" + +#define HASH_CMP_ZCELL (1) +#define HASH_CMP_ZBLK (2) + +#define HASH_ENTRY_STAT + +/* 全局变量定义区 */ +static ZXIC_UINT32 g_ddr_hash_arg[HASH_DDR_CRC_NUM] = { + 0x04C11DB7, 0xF4ACFB13, 0x20044009, 0x00210801 +}; + +static DPP_HASH_TBL_ID_INFO g_tbl_id_info[DPP_DEV_CHANNEL_MAX][HASH_FUNC_ID_NUM][HASH_TBL_ID_NUM] = {{{{0}}}}; + +/** 4个hash引擎，每个最多使用32个zblock */ +static ZXIC_UINT32 g_hash_zblk_idx[DPP_DEV_CHANNEL_MAX][HASH_FUNC_ID_NUM][HASH_TBL_ID_NUM] = {{{0}}}; + +static DPP_HASH_SOFT_RESET_STOR_DAT g_hash_store_dat[DPP_DEV_CHANNEL_MAX] = {{{0}}}; + +static ZXIC_UINT64 g_se_cfg_point = 0; + +#if DPP_WRITE_FILE_EN +static DPP_HASH_FILE_REG_T g_hash_file_reg = { + {0x55550000, 0xffffaaaa}, {1, 1, 1, 1}, + { + {0x12121212, 0x12121212}, {0x12121212, 0x12121212}, + {0x12121212, 0x12121212}, {0x12121212, 0x12121212} + }, + 0, + 0xffff, + 0, + {0}, + {0} +}; +#endif +/* 宏函数定义区 */ +#define GET_DDR_HASH_ARG(ddr_crc_sel) (g_ddr_hash_arg[ddr_crc_sel]) +#define GET_HASH_TBL_ID_INFO(dev_id, fun_id, tbl_id) (&g_tbl_id_info[dev_id][fun_id][tbl_id]) +#define GET_ACTU_KEY_SIZE_BY_TBLID(dev_id,fun_id, tbl_id) (g_tbl_id_info[dev_id][fun_id][tbl_id].actu_key_size) + +#define HASH_TBL_ID_INFO_CHECK(dev_id,fun_id, tbl_id, key_type) \ + do{\ + if (!g_tbl_id_info[dev_id][fun_id][tbl_id].is_init || \ + (g_tbl_id_info[dev_id][fun_id][tbl_id].key_type != key_type)) \ + { \ + ZXIC_COMM_PRINT("init [%d], config ketype[%d] parameter key_type[%d].\n",\ + g_tbl_id_info[dev_id][fun_id][tbl_id].is_init, \ + g_tbl_id_info[dev_id][fun_id][tbl_id].key_type, \ + key_type);\ + ZXIC_COMM_ASSERT(0); \ + return DPP_HASH_RC_INVALID_TBL_ID_INFO; \ + } \ + }while (0) + + +#define GET_HASH_DDR_HW_ADDR(base_addr, item_idx) \ + ((base_addr) + (item_idx)) + +/* 9:zcell depth */ +#define GET_HASH_ZCAM_HW_ADDR(base_addr, zblk_idx, item_idx) \ + ((base_addr) + ((zblk_idx) << 9) + (item_idx)) + +#define DPP_GET_HASH_FILE_REG() (&g_hash_file_reg) + +/* 局部函数声明区 */ + +/* 函数实现区 */ + +#if ZXIC_REAL("inter func.") +/***********************************************************/ +/** zblock资源链表排序比较函数 +* @param data1 待比较的数据1 +* @param data2 待比较的数据2 +* @param data 排序比较的类型，1-zcell比较，2-zblock比较 +* +* @return 1-data1比data2的索引大 + 0-data1和data2索引相同 + -1-data1比data2的索引小 +* @remark 无 +* @see +* @author wcl @date 2014/11/10 +************************************************************/ +ZXIC_SINT32 dpp_hash_list_cmp(D_NODE *data1, D_NODE *data2, void *data) +{ + ZXIC_UINT32 flag = 0; + ZXIC_UINT32 data_new = 0; + ZXIC_UINT32 data_pre = 0; + + ZXIC_COMM_CHECK_POINT(data1); + ZXIC_COMM_CHECK_POINT(data2); + ZXIC_COMM_CHECK_POINT(data); + + flag = *(ZXIC_UINT32 *)data; + + if (flag == HASH_CMP_ZCELL) + { + data_new = ((SE_ZCELL_CFG *)data1->data)->zcell_idx; + data_pre = ((SE_ZCELL_CFG *)data2->data)->zcell_idx; + } + else if (flag == HASH_CMP_ZBLK) + { + data_new = ((SE_ZBLK_CFG *)data1->data)->zblk_idx; + data_pre = ((SE_ZBLK_CFG *)data2->data)->zblk_idx; + } + + if (data_new > data_pre) + { + return 1; + } + else if (data_new == data_pre) + { + return 0; + } + else + { + return -1; + } +} + +/***********************************************************/ +/** hash键值红黑树插入比较函数 +* @param p_new +* @param p_old +* @param key_size +* +* @return +* @remark 无 +* @see +* @author wcl @date 2014/11/10 +************************************************************/ +ZXIC_SINT32 dpp_hash_rb_key_cmp(ZXIC_VOID *p_new, ZXIC_VOID *p_old, ZXIC_UINT32 key_size) +{ + DPP_HASH_RBKEY_INFO *p_rbkey_new = NULL; + DPP_HASH_RBKEY_INFO *p_rbkey_old = NULL; + + ZXIC_COMM_CHECK_POINT(p_new); + ZXIC_COMM_CHECK_POINT(p_old); + p_rbkey_new = (DPP_HASH_RBKEY_INFO *)(p_new); + p_rbkey_old = (DPP_HASH_RBKEY_INFO *)(p_old); + + return ZXIC_COMM_MEMCMP(p_rbkey_new->key, p_rbkey_old->key, HASH_KEY_MAX); +} + +/***********************************************************/ +/** hash键值红黑树插入比较函数 +* @param p_new +* @param p_old +* @param key_size +* +* @return +* @remark 无 +* @see +* @author tf @date 2016/03/26 +************************************************************/ +ZXIC_SINT32 dpp_hash_ddr_cfg_rb_key_cmp(ZXIC_VOID *p_new, ZXIC_VOID *p_old, ZXIC_UINT32 key_size) +{ + HASH_DDR_CFG *p_rbkey_new = NULL; + HASH_DDR_CFG *p_rbkey_old = NULL; + + ZXIC_COMM_CHECK_POINT(p_new); + ZXIC_COMM_CHECK_POINT(p_old); + p_rbkey_new = (HASH_DDR_CFG *)(p_new); + p_rbkey_old = (HASH_DDR_CFG *)(p_old); + + return ZXIC_COMM_MEMCMP(&p_rbkey_new->ddr_baddr, &p_rbkey_old->ddr_baddr, sizeof(ZXIC_UINT32)); +} + +/***********************************************************/ +/** 获取位宽 +* @param ddr_item_num +* +* @return +* @remark 无 +* @see +* @author wcl @date 2014/11/10 +************************************************************/ +ZXIC_UINT32 dpp_hash_ddr_depth_conv(ZXIC_UINT32 ddr_item_num) +{ + ZXIC_UINT32 count = 0; + + while (ddr_item_num > ((ZXIC_UINT32)1 << count)) + { + count++; + } + + return count; +} + +/***********************************************************/ +/** 片内资源初始化 +* @param p_hash_cfg +* @param zblk_num +* @param zblk_idx_array +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author wcl @date 2015/10/13 +************************************************************/ +DPP_STATUS dpp_hash_zcam_resource_init(DPP_HASH_CFG *p_hash_cfg, ZXIC_UINT32 zblk_num, ZXIC_UINT32 *zblk_idx_array) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_UINT32 i = 0; + ZXIC_UINT32 j = 0; + ZXIC_UINT32 cmp_type = 0; + ZXIC_UINT32 zblk_idx = 0; + ZXIC_UINT32 zcell_idx = 0; + ZXIC_UINT32 dev_id = 0; + + D_HEAD *p_zblk_list = NULL; + D_HEAD *p_zcell_free = NULL; + SE_ZBLK_CFG *p_zblk_cfg = NULL; + SE_ZCELL_CFG *p_zcell_cfg = NULL; + + ZXIC_COMM_CHECK_POINT(p_hash_cfg); + ZXIC_COMM_CHECK_INDEX(zblk_num, 0, SE_ZBLK_NUM); + ZXIC_COMM_CHECK_POINT(zblk_idx_array); + + dev_id = p_hash_cfg->p_se_info->dev_id; + + /* init zblock list */ + p_zblk_list = &p_hash_cfg->hash_shareram.zblk_list; + rc = zxic_comm_double_link_init(SE_ZBLK_NUM, p_zblk_list); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "zxic_comm_double_link_init"); + + /* init zcell list */ + p_zcell_free = &p_hash_cfg->hash_shareram.zcell_free_list; + rc = zxic_comm_double_link_init(SE_ZBLK_NUM * SE_ZCELL_NUM, p_zcell_free); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "zxic_comm_double_link_init"); + + for (i = 0; i < zblk_num; i++) + { + zblk_idx = zblk_idx_array[i]; + /* debug start */ + //ZXIC_COMM_PRINT("zblk_idx is [%d]\n", zblk_idx); /* t */ + /* debug end */ + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, zblk_idx, 0, SE_ZBLK_NUM - 1); + p_zblk_cfg = DPP_SE_GET_ZBLK_CFG(p_hash_cfg->p_se_info, zblk_idx); + + if (p_zblk_cfg->is_used) + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "ErrorCode:[0x%x], ZBlock[%d] is already used by other function!\n", \ + DPP_HASH_RC_INVALID_ZBLCK, zblk_idx); + ZXIC_COMM_ASSERT(0); + return DPP_HASH_RC_INVALID_ZBLCK; + } + + for (j = 0; j < SE_ZCELL_NUM; j++) + { + zcell_idx = p_zblk_cfg->zcell_info[j].zcell_idx; + p_zcell_cfg = DPP_SE_GET_ZCELL_CFG(p_hash_cfg->p_se_info, zcell_idx); + + if (p_zcell_cfg->is_used) + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "ErrorCode:[0x%x], ZBlk[%d], ZCell[%d] is already used by other function!\n", \ + DPP_HASH_RC_INVALID_ZCELL, zblk_idx, zcell_idx); + ZXIC_COMM_ASSERT(0); + return DPP_HASH_RC_INVALID_ZCELL; + } + + p_zcell_cfg->is_used = 1; + + /* insert to free zcell free list */ + cmp_type = HASH_CMP_ZCELL; + rc = zxic_comm_double_link_insert_sort(&p_zcell_cfg->zcell_dn, p_zcell_free, dpp_hash_list_cmp, &cmp_type); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "zxic_comm_double_link_insert_sort"); + } + + /* insert to zblock list */ + p_zblk_cfg->is_used = 1; + cmp_type = HASH_CMP_ZBLK; + rc = zxic_comm_double_link_insert_sort(&p_zblk_cfg->zblk_dn, p_zblk_list, dpp_hash_list_cmp, &cmp_type); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "zxic_comm_double_link_insert_last"); + + /* config zblock */ + rc = dpp_hash_zblkcfg_write(p_hash_cfg->p_se_info, p_hash_cfg->fun_id, p_zblk_cfg); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_hash_zblkcfg_write"); + } + + return DPP_OK; +} + +/***********************************************************/ +/** +* @param p_hash_cfg +* +* @return +* @remark 无 +* @see +* @author XCX @date 2018/03/22 +************************************************************/ +DPP_STATUS dpp_hash_zcam_resource_deinit(DPP_HASH_CFG *p_hash_cfg) +{ + ZXIC_UINT32 rc = 0; + ZXIC_UINT32 dev_id = 0; + + D_NODE *p_node = NULL; + D_HEAD *p_head = NULL; + SE_ZBLK_CFG *p_zblk_cfg = NULL; + SE_ZCELL_CFG *p_zcell_cfg = NULL; + + ZXIC_COMM_CHECK_POINT(p_hash_cfg); + + dev_id = p_hash_cfg->p_se_info->dev_id; + + /*delete zcell node*/ + p_head = &p_hash_cfg->hash_shareram.zcell_free_list; + + while (p_head->used) + { + p_node = p_head->p_next; + + rc = zxic_comm_double_link_del(p_node, p_head); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "zxic_comm_double_link_del"); + p_zcell_cfg = (SE_ZCELL_CFG *)p_node->data; + p_zcell_cfg->is_used = 0; + } + + /*delete zblk node*/ + p_head = &p_hash_cfg->hash_shareram.zblk_list; + + while (p_head->used) + { + p_node = p_head->p_next; + + rc = zxic_comm_double_link_del(p_node, p_head); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "zxic_comm_double_link_del"); + + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, ((SE_ZBLK_CFG *)p_node->data)->zblk_idx, 0, HASH_ZBLK_ID_MAX); + p_zblk_cfg = DPP_SE_GET_ZBLK_CFG(p_hash_cfg->p_se_info, ((SE_ZBLK_CFG *)p_node->data)->zblk_idx); + p_zblk_cfg->is_used = 0; + + /*clear zblk config*/ + /* dpp_hash_zblkcfg_clr(p_hash_cfg->p_se_info, p_hash_cfg->fun_id, p_zblk_cfg); */ + } + + return DPP_OK; +} + +/***********************************************************/ +/** +* @param item_entry_max +* @param wrt_mask +* @param entry_size +* +* @return +* @remark 无 +* @see +* @author XCX @date 2018/03/22 +************************************************************/ +ZXIC_UINT32 dpp_hash_get_item_free_pos(ZXIC_UINT32 item_entry_max, ZXIC_UINT32 wrt_mask, ZXIC_UINT32 entry_size) +{ + ZXIC_UINT32 i = 0; + ZXIC_UINT32 pos = 0xFFFFFFFF;/* -1; */ + ZXIC_UINT32 mask = 0; + + for (i = 0; i < item_entry_max; i += entry_size / HASH_ENTRY_POS_STEP) + { + ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(i, entry_size / HASH_ENTRY_POS_STEP); + mask = DPP_GET_HASH_ENTRY_MASK(entry_size, i); + + if (0 == (mask & wrt_mask)) + { + pos = i; + break; + } + } + + return pos; +} + +/***********************************************************/ +/** +* @param p_hash_cfg +* @param p_rbkey +* @param p_item +* @param item_idx +* @param item_type +* @param insrt_key_type +* +* @return +* @remark 无 +* @see +* @author XCX @date 2018/03/22 +************************************************************/ +DPP_STATUS dpp_hash_insrt_to_item(DPP_HASH_CFG *p_hash_cfg, + DPP_HASH_RBKEY_INFO *p_rbkey, + SE_ITEM_CFG *p_item, + ZXIC_UINT32 item_idx, + ZXIC_UINT32 item_type, + ZXIC_UINT32 insrt_key_type) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_UINT32 free_pos = 0; + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 item_entry_max = ITEM_ENTRY_NUM_4; + + ZXIC_COMM_CHECK_POINT(p_hash_cfg); + ZXIC_COMM_CHECK_POINT(p_rbkey); + ZXIC_COMM_CHECK_POINT(p_item); + + dev_id = p_hash_cfg->p_se_info->dev_id; + + if (ITEM_DDR_256 == item_type) + { + item_entry_max = ITEM_ENTRY_NUM_2; + } + + if (!p_item->valid) /* item is not used */ + { + rc = zxic_comm_double_link_init(item_entry_max, &p_item->item_list); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "zxic_comm_double_link_init"); + + p_rbkey->entry_pos = HASH_ITEM_POS_0; + p_item->wrt_mask = DPP_GET_HASH_ENTRY_MASK(p_rbkey->entry_size, p_rbkey->entry_pos); + p_item->item_index = item_idx; + p_item->item_type = item_type; + p_item->valid = 1; + } + else + { + free_pos = dpp_hash_get_item_free_pos(item_entry_max, p_item->wrt_mask, p_rbkey->entry_size); + + if (0xFFFFFFFF == free_pos) + { + return DPP_HASH_RC_ITEM_FULL; + } + else + { + p_rbkey->entry_pos = free_pos; + p_item->wrt_mask |= DPP_GET_HASH_ENTRY_MASK(p_rbkey->entry_size, p_rbkey->entry_pos); + } + } + + /* debug*/ + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "Entry in item pos is: [%d], entry size is: [%d].\n", free_pos, p_rbkey->entry_size); + + rc = zxic_comm_double_link_insert_last(&p_rbkey->entry_dn, &p_item->item_list); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "zxic_comm_double_link_insert_last"); + + p_rbkey->p_item_info = p_item; + + return DPP_OK; +} + +#endif + +#if ZXIC_REAL("External Func.") +/***********************************************************/ +/** 单个hash引擎初始化 +* @param p_se_cfg 算法模块公共管理数据结构指针 +* @param fun_id hash引擎号 +* @param zblk_num 分配给此hash引擎的zblock数目 +* @param zblk_idx 分配给此hash引擎的zblock编号 +* @param ddr_dis DDR关闭位，0-不关闭片外DDR, 1-关闭片外DDR +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author wcl @date 2015/05/15 +************************************************************/ +DPP_STATUS dpp_hash_init(DPP_SE_CFG *p_se_cfg, + ZXIC_UINT32 fun_id, + ZXIC_UINT32 zblk_num, + ZXIC_UINT32 *zblk_idx, + ZXIC_UINT32 ddr_dis) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_UINT32 i = 0; + ZXIC_UINT32 dev_id = 0; + + FUNC_ID_INFO *p_func_info = NULL; + DPP_HASH_CFG *p_hash_cfg = NULL; + + ZXIC_COMM_CHECK_POINT(p_se_cfg); + ZXIC_COMM_CHECK_POINT(zblk_idx); + ZXIC_COMM_CHECK_INDEX(fun_id, HASH_FUNC_ID_MIN, HASH_FUNC_ID_NUM - 1); + ZXIC_COMM_CHECK_INDEX(zblk_num, 0, SE_ZBLK_NUM); + ZXIC_COMM_CHECK_INDEX(ddr_dis, 0, 1); + + dev_id = p_se_cfg->dev_id; + ZXIC_COMM_CHECK_INDEX_UPPER(dev_id,DPP_DEV_CHANNEL_MAX - 1); + + rc = dpp_se_fun_init(p_se_cfg, (fun_id & 0xff), FUN_HASH); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_se_fun_init"); + + p_func_info = DPP_GET_FUN_INFO(p_se_cfg, fun_id); + p_hash_cfg = (DPP_HASH_CFG *)p_func_info->fun_ptr; + p_hash_cfg->fun_id = fun_id; + p_hash_cfg->p_hash32_fun = dpp_crc32_calc; + p_hash_cfg->p_hash16_fun = dpp_crc16_calc; + p_hash_cfg->p_se_info = p_se_cfg; + + /* 判定hash引擎是片内模式还是混合模式*/ + if (ddr_dis == 1) + { + /* disable ddr */ + p_hash_cfg->ddr_valid = 0; + +#ifdef DPP_FLOW_HW_INIT + rc = dpp_hash_ext_cfg_clr(p_se_cfg, fun_id); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_hash_ddrcfg_clr"); + + rc = dpp_hash_tbl_depth_clr(p_se_cfg, fun_id); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_hash_tbl_depth_clr"); +#endif + + } + else + { + p_hash_cfg->ddr_valid = 1; + + } + + /* zcam初始化*/ + p_hash_cfg->hash_stat.zblock_num = zblk_num; + rc = dpp_hash_zcam_resource_init(p_hash_cfg, zblk_num, zblk_idx); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_hash_zcam_resource_init"); + + /* 将zblock_id记录在软件缓存中 */ + for(i = 0; i < zblk_num; i++) + { + p_hash_cfg->hash_stat.zblock_array[i] = zblk_idx[i]; + } + + /* dynamic alloc rb_tree node by user. */ + rc = (DPP_STATUS)zxic_comm_rb_init(&p_hash_cfg->hash_rb, + 0, + sizeof(DPP_HASH_RBKEY_INFO), + dpp_hash_rb_key_cmp); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "zxic_comm_rb_init"); + + /* dynamic alloc rb_tree node by user. */ + rc = (DPP_STATUS)zxic_comm_rb_init(&p_hash_cfg->ddr_cfg_rb, + 0, + sizeof(HASH_DDR_CFG), + dpp_hash_ddr_cfg_rb_key_cmp); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "zxic_comm_rb_init"); + + /** for 软复位 */ + /** 保存zblock内容 */ + for (i = 0; i < zblk_num; i++) + { + g_hash_zblk_idx[dev_id][fun_id][i] = zblk_idx[i]; + } + + g_hash_store_dat[dev_id].ddr_dis_flag[fun_id] = ddr_dis; + g_hash_store_dat[dev_id].zblk_num[fun_id] = zblk_num; + g_hash_store_dat[dev_id].zblk_idx_start[fun_id] = g_hash_zblk_idx[dev_id][fun_id]; + g_hash_store_dat[dev_id].hash_id_valid |= (ZXIC_UINT32)((1U << fun_id) & 0xffffffff); + + /** for diag */ + g_se_cfg_point = ZXIC_COMM_PTR_TO_VAL(p_se_cfg); + + return DPP_OK; +} + +/***********************************************************/ +/** 初始化单个hash引擎内的某个业务表，此接口支持为该业务表分配独占的zcell。 +* 必须先初始化hash引擎，再初始化业务表。 +* @param p_se_cfg 算法模块公共管理数据结构指针 +* @param fun_id hash引擎号 +* @param bulk_id 每个Hash引擎资源划分的空间ID号 +* @param p_ddr_resc_cfg 分配给hash引擎此资源空间的ddr资源属性 +* @param zcell_num 分配给hash引擎此资源空间的zcell数量 +* @param zreg_num 分配给hash引擎此资源空间的zreg数量 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author wcl @date 2015/05/15 +************************************************************/ +DPP_STATUS dpp_hash_bulk_init(DPP_SE_CFG *p_se_cfg, + ZXIC_UINT32 fun_id, + ZXIC_UINT32 bulk_id, + DPP_HASH_DDR_RESC_CFG_T *p_ddr_resc_cfg, + ZXIC_UINT32 zcell_num, + ZXIC_UINT32 zreg_num) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_UINT32 i = 0; + ZXIC_UINT32 j = 0; + ZXIC_UINT32 zblk_idx = 0; + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 ddr_item_num = 0; + + D_NODE *p_zblk_dn = NULL; + D_NODE *p_zcell_dn = NULL; + ZXIC_RB_TN *p_rb_tn_new = NULL; + ZXIC_RB_TN *p_rb_tn_rtn = NULL; + SE_ZBLK_CFG *p_zblk_cfg = NULL; + SE_ZREG_CFG *p_zreg_cfg = NULL; + HASH_DDR_CFG *p_ddr_cfg = NULL; + HASH_DDR_CFG *p_rbkey_new = NULL; + HASH_DDR_CFG *p_rbkey_rtn = NULL; + SE_ZCELL_CFG *p_zcell_cfg = NULL; + DPP_HASH_CFG *p_hash_cfg = NULL; + FUNC_ID_INFO *p_func_info = NULL; + SE_ITEM_CFG **p_item_array = NULL; + DPP_HASH_BULK_ZCAM_STAT *p_bulk_zcam_mono = NULL; + /* D_HEAD *p_zcell_free = NULL;*/ + /* D_HEAD *p_zblk_free = NULL;*/ + + ZXIC_COMM_CHECK_POINT(p_se_cfg); + ZXIC_COMM_CHECK_POINT(p_ddr_resc_cfg); + ZXIC_COMM_CHECK_INDEX(p_ddr_resc_cfg->ddr_crc_sel, 0, HASH_DDR_CRC_NUM - 1); + ZXIC_COMM_CHECK_INDEX(fun_id, DPP_HASH_ID_MIN, DPP_HASH_ID_MAX); + ZXIC_COMM_CHECK_INDEX(bulk_id, HASH_BULK_ID_MIN, HASH_BULK_ID_MAX); + ZXIC_COMM_CHECK_INDEX(zcell_num, 0, SE_ZBLK_NUM * SE_ZCELL_NUM); + ZXIC_COMM_CHECK_INDEX(zreg_num, 0, SE_ZBLK_NUM * SE_ZREG_NUM); + + dev_id = p_se_cfg->dev_id; + + p_func_info = DPP_GET_FUN_INFO(p_se_cfg, fun_id); + p_hash_cfg = (DPP_HASH_CFG *)p_func_info->fun_ptr; + ZXIC_COMM_CHECK_POINT(p_hash_cfg); + + ZXIC_COMM_TRACE_INFO("p_hash_cfg->ddr_valid = %d!\n", p_hash_cfg->ddr_valid); + + if (1 == p_hash_cfg->ddr_valid) + { + /* [a long time ago] hash存储深度不能超过26bit，不然会导致硬件逻辑crc index不一致，微码查表不中 */ + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, p_ddr_resc_cfg->ddr_item_num, HASH_DDR_ITEM_MIN, HASH_DDR_ITEM_MAX); + + ddr_item_num = p_ddr_resc_cfg->ddr_item_num; + + if (DDR_WIDTH_512b == p_ddr_resc_cfg->ddr_width_mode) + { + ddr_item_num = p_ddr_resc_cfg->ddr_item_num >> 1; + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, ddr_item_num, HASH_DDR_ITEM_MIN, HASH_DDR_ITEM_MAX); /* 512bit存储时，hash存储深度不能少于14bit */ + } + + /** red&black key*/ + p_rbkey_new = (HASH_DDR_CFG *)ZXIC_COMM_MALLOC(sizeof(HASH_DDR_CFG)); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_rbkey_new); + ZXIC_COMM_MEMSET(p_rbkey_new, 0, sizeof(HASH_DDR_CFG)); + + p_rbkey_new->ddr_baddr = p_ddr_resc_cfg->ddr_baddr; + + /** red&black tree node*/ + p_rb_tn_new = (ZXIC_RB_TN *)ZXIC_COMM_MALLOC(sizeof(ZXIC_RB_TN)); + if (NULL == (p_rb_tn_new)) + { + ZXIC_COMM_FREE(p_rbkey_new); + ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ICM %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__); + return ZXIC_PAR_CHK_POINT_NULL; + } + INIT_RBT_TN(p_rb_tn_new, p_rbkey_new); + + rc = zxic_comm_rb_insert(&p_hash_cfg->ddr_cfg_rb, (ZXIC_VOID *)p_rb_tn_new, (ZXIC_VOID *)(&p_rb_tn_rtn)); + if (ZXIC_RBT_RC_FULL == rc) + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "The red black tree is full!\n"); + ZXIC_COMM_FREE(p_rbkey_new); + ZXIC_COMM_FREE(p_rb_tn_new); + ZXIC_COMM_ASSERT(0); + return DPP_HASH_RC_RB_TREE_FULL; + } + else if (ZXIC_RBT_RC_UPDATE == rc) + { + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "some bulk_id share one bulk!\n"); + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_rb_tn_rtn); + p_rbkey_rtn = (HASH_DDR_CFG *)(p_rb_tn_rtn->p_key); + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, p_rbkey_rtn->bulk_id, 0, HASH_BULK_NUM - 1); + p_ddr_cfg = p_hash_cfg->p_bulk_ddr_info[p_rbkey_rtn->bulk_id]; /* 已经初始化过的ddr_bulk_id属性 */ + + if (p_ddr_cfg->hash_ddr_arg != GET_DDR_HASH_ARG(p_ddr_resc_cfg->ddr_crc_sel) || + p_ddr_cfg->width_mode != p_ddr_resc_cfg->ddr_width_mode || + p_ddr_cfg->ddr_ecc_en != p_ddr_resc_cfg->ddr_ecc_en || + p_ddr_cfg->item_num != ddr_item_num) + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "The base address is same but other ddr attribute is different\n"); + ZXIC_COMM_FREE(p_rbkey_new); + ZXIC_COMM_FREE(p_rb_tn_new); + ZXIC_COMM_ASSERT(0); + return DPP_HASH_RC_INVALID_PARA; + } + + p_hash_cfg->p_bulk_ddr_info[bulk_id] = p_hash_cfg->p_bulk_ddr_info[p_rbkey_rtn->bulk_id]; + + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "bulk id init bulk_ddr_cfg ptr is:"); + + for (i = 0; i < HASH_BULK_NUM; i++) + { + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "%p ", p_hash_cfg->p_bulk_ddr_info[i]); + } + + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "\n"); + + ZXIC_COMM_FREE(p_rbkey_new); + ZXIC_COMM_FREE(p_rb_tn_new); + } + else + { + p_item_array = (SE_ITEM_CFG **)ZXIC_COMM_MALLOC(ddr_item_num * sizeof(SE_ITEM_CFG *)); + if (NULL == (p_item_array)) + { + ZXIC_COMM_FREE(p_rbkey_new); + ZXIC_COMM_FREE(p_rb_tn_new); + ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ICM %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__); + return ZXIC_PAR_CHK_POINT_NULL; + } + ZXIC_COMM_MEMSET(p_item_array, 0, ddr_item_num * sizeof(SE_ITEM_CFG *)); + + p_rbkey_new->p_item_array = p_item_array; + p_rbkey_new->bulk_id = bulk_id; + p_rbkey_new->hw_baddr = 0; + p_rbkey_new->width_mode = p_ddr_resc_cfg->ddr_width_mode; + p_rbkey_new->item_num = ddr_item_num; + p_rbkey_new->ddr_ecc_en = p_ddr_resc_cfg->ddr_ecc_en; + p_rbkey_new->hash_ddr_arg = GET_DDR_HASH_ARG(p_ddr_resc_cfg->ddr_crc_sel); + p_rbkey_new->bulk_use = 1; + p_rbkey_new->zcell_num = zcell_num; + p_rbkey_new->zreg_num = zreg_num; + p_hash_cfg->p_bulk_ddr_info[bulk_id] = p_rbkey_new; + + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "one new ddr_bulk init!\n"); + } +#ifdef DPP_FLOW_HW_INIT + rc = dpp_hash_tbl_crc_poly_write(p_hash_cfg->p_se_info, p_hash_cfg->fun_id, bulk_id, p_ddr_resc_cfg->ddr_crc_sel); + if (DPP_OK != rc) + { + ZXIC_COMM_FREE(p_rbkey_new); + ZXIC_COMM_FREE(p_rb_tn_new); + ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ICM %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,"dpp_hash_tbl_crc_poly_write"); + return rc; + } + + rc = dpp_hash_ext_cfg_write(p_hash_cfg->p_se_info, p_hash_cfg->fun_id, bulk_id, p_hash_cfg->p_bulk_ddr_info[bulk_id]); + if (DPP_OK != rc) + { + ZXIC_COMM_FREE(p_rbkey_new); + ZXIC_COMM_FREE(p_rb_tn_new); + ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ICM %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,"dpp_hash_ext_cfg_write"); + return rc; + } + rc = dpp_hash_tbl_depth_write(p_hash_cfg->p_se_info, + p_hash_cfg->fun_id, + bulk_id, + p_hash_cfg->p_bulk_ddr_info[bulk_id]); + if (DPP_OK != rc) + { + ZXIC_COMM_FREE(p_rbkey_new); + ZXIC_COMM_FREE(p_rb_tn_new); + ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ICM %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,"dpp_hash_tbl_depth_write"); + return rc; + } +#endif + rc = dpp_se_smmu1_hash_tbl_cfg_set(p_se_cfg->dev, p_hash_cfg->fun_id, bulk_id, p_ddr_resc_cfg->ddr_ecc_en, p_ddr_resc_cfg->ddr_baddr); + if (DPP_OK != rc) + { + ZXIC_COMM_FREE(p_rbkey_new); + ZXIC_COMM_FREE(p_rb_tn_new); + ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ICM %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,"dpp_se_smmu1_hash_tbl_cfg_set"); + return rc; + } + + } + + p_bulk_zcam_mono = (DPP_HASH_BULK_ZCAM_STAT *)ZXIC_COMM_MALLOC(sizeof(DPP_HASH_BULK_ZCAM_STAT)); + if (NULL == (p_bulk_zcam_mono)) + { + ZXIC_COMM_FREE(p_rbkey_new); + ZXIC_COMM_FREE(p_rb_tn_new); + ZXIC_COMM_FREE(p_item_array); + ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ICM %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__); + return ZXIC_PAR_CHK_POINT_NULL; + } + ZXIC_COMM_MEMSET(p_bulk_zcam_mono, 0, sizeof(DPP_HASH_BULK_ZCAM_STAT)); + (&p_hash_cfg->hash_stat)->p_bulk_zcam_mono[bulk_id] = p_bulk_zcam_mono; + + for (i = 0; i < SE_ZBLK_NUM * SE_ZCELL_NUM; i++) + { + p_bulk_zcam_mono->zcell_mono_idx[i] = 0xffffffff; + } + + for (i = 0; i < SE_ZBLK_NUM; i++) + { + for (j = 0; j < SE_ZREG_NUM; j++) + { + p_bulk_zcam_mono->zreg_mono_id[i][j].zblk_id = 0xffffffff; + p_bulk_zcam_mono->zreg_mono_id[i][j].zreg_id = 0xffffffff; + } + } + + if (zcell_num > 0) + { + p_hash_cfg->bulk_ram_mono[bulk_id] = 1; + +#ifdef DPP_FLOW_HW_INIT + rc = dpp_hash_bulk_mono_flags_write(p_se_cfg, fun_id, bulk_id); + if (DPP_OK != rc) + { + ZXIC_COMM_FREE(p_rbkey_new); + ZXIC_COMM_FREE(p_rb_tn_new); + ZXIC_COMM_FREE(p_item_array); + ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ICM %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,"dpp_hash_bulk_mono_flags_write"); + return rc; + } +#endif + + /* 初始分配此业务表独占的zcell，只能在非独占的zcell中分配 */ + /* p_zcell_free = &(p_hash_cfg->hash_shareram.zcell_free_list);*/ + p_zcell_dn = p_hash_cfg->hash_shareram.zcell_free_list.p_next; + + i = 0; + + while (p_zcell_dn) + { + p_zcell_cfg = (SE_ZCELL_CFG *)p_zcell_dn->data; + + if (p_zcell_cfg->is_used) + { + if (!(p_zcell_cfg->flag & DPP_ZCELL_FLAG_IS_MONO)) + { + p_zcell_cfg->flag |= DPP_ZCELL_FLAG_IS_MONO; + p_zcell_cfg->bulk_id = bulk_id; + +#ifdef DPP_FLOW_HW_INIT + rc = dpp_hash_zcell_mono_write(p_se_cfg, p_zcell_cfg); /* 写入硬件 */ + if (DPP_OK != rc) + { + ZXIC_COMM_FREE(p_rbkey_new); + ZXIC_COMM_FREE(p_rb_tn_new); + ZXIC_COMM_FREE(p_item_array); + ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ICM %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,"dpp_hash_zcell_mono_write"); + return rc; + } +#endif + + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, p_zcell_cfg->zcell_idx, 0, SE_ZCELL_TOTAL_NUM - 1); + p_bulk_zcam_mono->zcell_mono_idx[p_zcell_cfg->zcell_idx] = p_zcell_cfg->zcell_idx; /* 统计独占的zcell */ + + if (++i >= zcell_num) + { + break; + } + } + } + else + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "zcell[ %d ] is not init before used!\n", p_zcell_cfg->zcell_idx); + ZXIC_COMM_ASSERT(0); + return DPP_HASH_RC_INVALID_PARA; + } + + p_zcell_dn = p_zcell_dn->next; + } + + if (i < zcell_num) + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "Input param 'zcell_num' is [ %d ], actually bulk[ %d ]monopolize zcells is [ %d ]!\n", zcell_num, bulk_id, i); + } + } + + if (zreg_num > 0) + { + p_hash_cfg->bulk_ram_mono[bulk_id] = 1; + +#ifdef DPP_FLOW_HW_INIT + rc = dpp_hash_bulk_mono_flags_write(p_se_cfg, fun_id, bulk_id); + if (DPP_OK != rc) + { + ZXIC_COMM_FREE(p_rbkey_new); + ZXIC_COMM_FREE(p_rb_tn_new); + ZXIC_COMM_FREE(p_item_array); + ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ICM %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,"dpp_hash_bulk_mono_flags_write"); + return rc; + } +#endif + /* p_tbl_id_info->zreg_num= zreg_num;*/ + + /* 初始分配此业务表独占的zreg，只能在非独占的zreg中分配 */ + /* p_zblk_free = &(p_hash_cfg->hash_shareram.zblk_list);*/ + p_zblk_dn = p_hash_cfg->hash_shareram.zblk_list.p_next; + j = 0; + + while (p_zblk_dn) + { + p_zblk_cfg = (SE_ZBLK_CFG *)p_zblk_dn->data; + zblk_idx = p_zblk_cfg->zblk_idx; + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, zblk_idx, 0, SE_ZBLK_NUM - 1); + + if (p_zblk_cfg->is_used) + { + for (i = 0; i < SE_ZREG_NUM; i++) + { + p_zreg_cfg = &(p_zblk_cfg->zreg_info[i]); + + if (!(p_zreg_cfg->flag & DPP_ZREG_FLAG_IS_MONO)) + { + p_zreg_cfg->flag = DPP_ZREG_FLAG_IS_MONO; + p_zreg_cfg->bulk_id = bulk_id; +#ifdef DPP_FLOW_HW_INIT + rc = dpp_hash_zreg_mono_write(p_se_cfg, bulk_id, zblk_idx, i); /* 写入硬件 */ + if (DPP_OK != rc) + { + ZXIC_COMM_FREE(p_rbkey_new); + ZXIC_COMM_FREE(p_rb_tn_new); + ZXIC_COMM_FREE(p_item_array); + ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ICM %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,"dpp_hash_zreg_mono_write"); + return rc; + } +#endif + p_bulk_zcam_mono->zreg_mono_id[zblk_idx][i].zblk_id = zblk_idx; + p_bulk_zcam_mono->zreg_mono_id[zblk_idx][i].zreg_id = i; + + if (++j >= zreg_num) + { + break; + } + } + } + + if (j >= zreg_num) + { + break; + } + } + else + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "zblk [ %d ] is not init before used!\n", p_zblk_cfg->zblk_idx); + ZXIC_COMM_ASSERT(0); + return DPP_HASH_RC_INVALID_PARA; + } + + p_zblk_dn = p_zblk_dn->next; + } + + if (j < zreg_num) + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "Input param 'zreg_num' is [ %d ], actually bulk[ %d ]monopolize zregs is [ %d ]!\n", zreg_num, bulk_id, j); + } + } + + /** for 软复位 */ + ZXIC_COMM_CHECK_INDEX_UPPER(dev_id,DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_INDEX(fun_id, 0, 3); + ZXIC_COMM_CHECK_INDEX(bulk_id, 0, 7); + g_hash_store_dat[dev_id].ddr_item_num[fun_id][bulk_id] = p_ddr_resc_cfg->ddr_item_num; + + return DPP_OK; +} + +/***********************************************************/ +/** 初始化单个hash引擎内的某个业务表，此接口支持为该业务表分配独占的zcell。 +* 必须先初始化hash引擎，如果是片内+片外模式还必须先初始化dpp_hash_ddr_bulk_init， +* 再初始化业务表。 +* @param p_se_cfg 算法模块公共管理数据结构指针 +* @param fun_id hash引擎号 +* @param tbl_id 业务表 +* @param tbl_flag 初始化标记, bitmap的形式使用，如:HASH_TBL_FLAG_AGE等 +* @param key_type hash条目类型，取值参照DPP_HASH_KEY_TYPE的定义 +* @param actu_key_size 业务键值有效长度: 8bit*N，N=1~48 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author wcl @date 2015/05/15 +************************************************************/ +DPP_STATUS dpp_hash_tbl_id_info_init(DPP_SE_CFG *p_se_cfg, + ZXIC_UINT32 fun_id, + ZXIC_UINT32 tbl_id, + ZXIC_UINT32 tbl_flag, + ZXIC_UINT32 key_type, + ZXIC_UINT32 actu_key_size) +{ + ZXIC_UINT32 key_by_size = 0; + ZXIC_UINT32 entry_size = 0; + + ZXIC_UINT32 dev_id = 0; + + DPP_HASH_TBL_ID_INFO *p_tbl_id_info = NULL; + + ZXIC_COMM_CHECK_INDEX(tbl_id, 0, HASH_TBL_ID_NUM - 1); + ZXIC_COMM_CHECK_INDEX(fun_id, HASH_FUNC_ID_MIN, HASH_FUNC_ID_NUM - 1); + ZXIC_COMM_CHECK_INDEX(actu_key_size, HASH_ACTU_KEY_MIN, HASH_ACTU_KEY_MAX); + ZXIC_COMM_CHECK_INDEX(key_type, HASH_KEY_128b, HASH_KEY_512b); + ZXIC_COMM_CHECK_POINT(p_se_cfg); + + dev_id = p_se_cfg->dev_id; + ZXIC_COMM_CHECK_INDEX_UPPER(dev_id,DPP_DEV_CHANNEL_MAX - 1); + key_by_size = DPP_GET_KEY_SIZE(actu_key_size); + entry_size = DPP_GET_HASH_ENTRY_SIZE(key_type); + + if (key_by_size > entry_size) + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "ErrorCode[%x]: actu_key_size[%d] not match to key_type[%d].\n", + DPP_HASH_RC_INVALID_PARA, + key_by_size, + entry_size); + ZXIC_COMM_ASSERT(0); + return DPP_HASH_RC_INVALID_PARA; + } + + p_tbl_id_info = GET_HASH_TBL_ID_INFO(dev_id, fun_id, tbl_id); + + if (p_tbl_id_info->is_init) + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "fun_id[%d],table_id[%d] is already init, do not init again!\n", fun_id, tbl_id); + return DPP_HASH_RC_REPEAT_INIT; + } + + p_tbl_id_info->fun_id = fun_id; + p_tbl_id_info->actu_key_size = actu_key_size; + p_tbl_id_info->key_type = key_type; + p_tbl_id_info->is_init = 1; + + if (tbl_flag & HASH_TBL_FLAG_AGE) + { + p_tbl_id_info->is_age = 1; + } + + if (tbl_flag & HASH_TBL_FLAG_LEARN) + { + p_tbl_id_info->is_lrn = 1; + } + + if (tbl_flag & HASH_TBL_FLAG_MC_WRT) + { + p_tbl_id_info->is_mc_wrt = 1; + } + + return DPP_OK; +} + +DPP_STATUS dpp_hash_red_black_node_alloc(DPP_DEV_T *dev,ZXIC_RB_TN **p_rb_tn_new,DPP_HASH_RBKEY_INFO **p_rbkey_new) +{ + ZXIC_RB_TN *p_rb_tn_new_temp = NULL; + DPP_HASH_RBKEY_INFO *p_rbkey_new_temp = NULL; + + ZXIC_COMM_CHECK_POINT(dev); + + /** red&black key*/ + p_rbkey_new_temp = (DPP_HASH_RBKEY_INFO *)ZXIC_COMM_MALLOC(sizeof(DPP_HASH_RBKEY_INFO)); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_rbkey_new_temp); + ZXIC_COMM_MEMSET(p_rbkey_new_temp, 0, sizeof(DPP_HASH_RBKEY_INFO)); + + /** red&black tree node*/ + p_rb_tn_new_temp = (ZXIC_RB_TN *)ZXIC_COMM_MALLOC(sizeof(ZXIC_RB_TN)); + if (NULL == p_rb_tn_new_temp) + { + ZXIC_COMM_FREE(p_rbkey_new_temp); + ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev),"\n ICM %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__); + return ZXIC_PAR_CHK_POINT_NULL; + } + + INIT_RBT_TN(p_rb_tn_new_temp, p_rbkey_new_temp); + + *p_rb_tn_new = p_rb_tn_new_temp; + *p_rbkey_new = p_rbkey_new_temp; + + return DPP_OK; +} + +DPP_STATUS dpp_hash_get_hash_info_from_sdt(ZXIC_UINT32 dev_id, ZXIC_UINT32 sdt_no, HASH_ENTRY_CFG *p_hash_entry_cfg) +{ + DPP_STATUS rc = DPP_OK; + FUNC_ID_INFO *p_func_info = NULL; + DPP_SE_CFG *p_se_cfg = NULL; + + DPP_SDTTBL_HASH_T sdt_hash_info = {0}; /*SDT内容*/ + + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_hash_entry_cfg); + + //从sdt_no中获取SDT配置 + rc = dpp_soft_sdt_tbl_get(dev_id, sdt_no, &sdt_hash_info); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_soft_sdt_tbl_read"); + + p_hash_entry_cfg->fun_id = sdt_hash_info.hash_id; /*hash引擎*/ + ZXIC_COMM_CHECK_INDEX(p_hash_entry_cfg->fun_id, HASH_FUNC_ID_MIN, HASH_FUNC_ID_NUM - 1); + + p_hash_entry_cfg->table_id = sdt_hash_info.hash_table_id; /*hash表号*/ + ZXIC_COMM_CHECK_INDEX_UPPER(p_hash_entry_cfg->table_id,HASH_TBL_ID_NUM - 1); + + p_hash_entry_cfg->bulk_id = ((p_hash_entry_cfg->table_id >> 2) & 0x7); + ZXIC_COMM_CHECK_INDEX_UPPER(p_hash_entry_cfg->bulk_id,HASH_BULK_NUM - 1); + + p_hash_entry_cfg->key_type = sdt_hash_info.hash_table_width; /*表宽度*/ + ZXIC_COMM_CHECK_INDEX(p_hash_entry_cfg->key_type, HASH_KEY_128b, HASH_KEY_512b); + + p_hash_entry_cfg->actu_key_size = sdt_hash_info.key_size; /*业务表键值长度*/ + ZXIC_COMM_CHECK_INDEX(p_hash_entry_cfg->actu_key_size, HASH_ACTU_KEY_MIN, HASH_ACTU_KEY_MAX); + p_hash_entry_cfg->key_by_size = DPP_GET_KEY_SIZE(p_hash_entry_cfg->actu_key_size); + p_hash_entry_cfg->rst_by_size = DPP_GET_RST_SIZE(p_hash_entry_cfg->key_type, p_hash_entry_cfg->actu_key_size); + + /* 取出se配置 */ + rc = dpp_se_cfg_get(dev_id, &p_se_cfg); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_se_cfg_get"); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_se_cfg); + p_hash_entry_cfg->p_se_cfg = p_se_cfg; + + p_func_info = DPP_GET_FUN_INFO(p_se_cfg, p_hash_entry_cfg->fun_id); + DPP_SE_CHECK_FUN(p_func_info, p_hash_entry_cfg->fun_id, FUN_HASH); + + p_hash_entry_cfg->p_hash_cfg = (DPP_HASH_CFG *)p_func_info->fun_ptr; + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_hash_entry_cfg->p_hash_cfg); + + return DPP_OK; +} + +DPP_STATUS dpp_hash_rb_insert(DPP_DEV_T *dev,HASH_ENTRY_CFG *p_hash_entry_cfg,DPP_HASH_ENTRY *p_entry) +{ + ZXIC_UINT32 rc = DPP_OK; + DPP_HASH_RBKEY_INFO *p_rbkey_rtn = NULL; + DPP_HASH_CFG *p_hash_cfg = NULL; + DPP_HASH_RBKEY_INFO *p_rbkey_new = NULL; + ZXIC_RB_TN *p_rb_tn_new = NULL; + ZXIC_RB_TN *p_rb_tn_rtn = NULL; + ZXIC_UINT32 rst_actual_size = 0; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_POINT(p_hash_entry_cfg); + ZXIC_COMM_CHECK_POINT(p_hash_entry_cfg->p_hash_cfg); + ZXIC_COMM_CHECK_POINT(p_entry); + ZXIC_COMM_CHECK_POINT(p_entry->p_rst); + + p_rbkey_new = p_hash_entry_cfg->p_rbkey_new; + p_rb_tn_new = p_hash_entry_cfg->p_rb_tn_new; + p_hash_cfg = p_hash_entry_cfg->p_hash_cfg; + rst_actual_size = ((p_hash_entry_cfg->rst_by_size) > HASH_RST_MAX) ? HASH_RST_MAX : p_hash_entry_cfg->rst_by_size; + rc = zxic_comm_rb_insert(&p_hash_cfg->hash_rb, (ZXIC_VOID *)p_rb_tn_new, (ZXIC_VOID *)(&p_rb_tn_rtn)); + if (ZXIC_RBT_RC_FULL == rc) + { + ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "The red black tree is full!\n"); + ZXIC_COMM_FREE(p_rbkey_new); + ZXIC_COMM_FREE(p_rb_tn_new); + ZXIC_COMM_ASSERT(0); + return DPP_HASH_RC_RB_TREE_FULL; + } + else if (ZXIC_RBT_RC_UPDATE == rc) + { + p_hash_cfg->hash_stat.insert_same++; + ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev), "Hash update exist entry!\n"); + + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_rb_tn_rtn); + p_rbkey_rtn = (DPP_HASH_RBKEY_INFO *)(p_rb_tn_rtn->p_key); + + /* when the result is more than 256bit, get first 256bit valid data. */ + ZXIC_COMM_MEMCPY(p_rbkey_rtn->rst, p_entry->p_rst, rst_actual_size); + + ZXIC_COMM_FREE(p_rbkey_new); + ZXIC_COMM_FREE(p_rb_tn_new); + p_hash_entry_cfg->p_rbkey_new = p_rbkey_rtn; + p_hash_entry_cfg->p_rb_tn_new = p_rb_tn_rtn; + + /* 仿真器使用 */ + if(DPP_DEV_TYPE_SIM == dpp_dev_get_dev_type(DEV_ID(dev))) + { + /*dpp_se_simulator_insert_delete_hash(DEV_ID(dev), + p_hash_entry_cfg->fun_id, + p_hash_entry_cfg->table_id, + p_hash_entry_cfg->key_by_size, + p_hash_entry_cfg->rst_by_size, + 0, + p_entry);*/ + } + + return DPP_HASH_RC_ADD_UPDATE; + } + else + { + ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev), "Hash insert new entry!\n"); + /* 仿真器使用 */ + if(DPP_DEV_TYPE_SIM == dpp_dev_get_dev_type(DEV_ID(dev))) + { + /*dpp_se_simulator_insert_delete_hash(DEV_ID(dev), + p_hash_entry_cfg->fun_id, + p_hash_entry_cfg->table_id, + p_hash_entry_cfg->key_by_size, + p_hash_entry_cfg->rst_by_size, + 0, + p_entry);*/ + } + + /* when the result is more than 256bit, get first 256bit valid data. */ + ZXIC_COMM_MEMCPY(p_rbkey_new->rst, p_entry->p_rst, rst_actual_size); + p_rbkey_new->entry_size = DPP_GET_HASH_ENTRY_SIZE(p_hash_entry_cfg->key_type); + INIT_D_NODE(&p_rbkey_new->entry_dn, p_rbkey_new); + } + + return DPP_OK; +} + +DPP_STATUS dpp_hash_set_crc_key(DPP_DEV_T *dev,HASH_ENTRY_CFG *p_hash_entry_cfg,DPP_HASH_ENTRY *p_entry,ZXIC_UINT8 *p_temp_key) +{ + ZXIC_UINT32 key_by_size = 0; + ZXIC_UINT8 temp_tbl_id = 0; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_POINT(p_hash_entry_cfg); + ZXIC_COMM_CHECK_POINT(p_entry); + ZXIC_COMM_CHECK_POINT(p_entry->p_key); + ZXIC_COMM_CHECK_POINT(p_temp_key); + + key_by_size = p_hash_entry_cfg->key_by_size; + ZXIC_COMM_MEMCPY(p_temp_key, p_entry->p_key, key_by_size); + + /* 约定: 参与CRC运算的key, 需要将tbl_id的前面补3bit的0，然后放到actu_key的后面. */ + temp_tbl_id = (*p_temp_key) & 0x1F; + memmove(p_temp_key, p_temp_key+1, key_by_size - HASH_KEY_CTR_SIZE); + ZXIC_COMM_CHECK_DEV_INDEX_SUB_OVERFLOW_NO_ASSERT(DEV_ID(dev), key_by_size, HASH_KEY_CTR_SIZE); + p_temp_key[key_by_size - HASH_KEY_CTR_SIZE] = temp_tbl_id; + + return DPP_OK; +} + +DPP_STATUS dpp_hash_insert_ddr(DPP_DEV_T *dev,HASH_ENTRY_CFG *p_hash_entry_cfg,ZXIC_UINT8 *p_temp_key,ZXIC_UINT8 *p_end_flag) +{ + DPP_HASH_CFG *p_hash_cfg = NULL; + ZXIC_UINT8 bulk_id = 0; + ZXIC_UINT8 key_type = 0; + ZXIC_UINT8 table_id = 0; + ZXIC_UINT32 key_by_size = 0; + ZXIC_UINT32 crc_value = 0; + ZXIC_UINT32 item_idx = 0xFFFFFFFF;/* -1 */ + ZXIC_UINT32 item_type = 0; + HASH_DDR_CFG *p_ddr_cfg = NULL; + SE_ITEM_CFG *p_item = NULL; + DPP_HASH_RBKEY_INFO *p_rbkey_new = NULL; + ZXIC_UINT32 rc = DPP_OK; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_POINT(p_hash_entry_cfg); + ZXIC_COMM_CHECK_POINT(p_temp_key); + ZXIC_COMM_CHECK_POINT(p_end_flag); + + p_hash_cfg = p_hash_entry_cfg->p_hash_cfg; + ZXIC_COMM_CHECK_POINT(p_hash_cfg); + bulk_id = p_hash_entry_cfg->bulk_id; + ZXIC_COMM_CHECK_INDEX_UPPER(bulk_id,HASH_BULK_NUM - 1); + p_ddr_cfg = p_hash_cfg->p_bulk_ddr_info[bulk_id]; + ZXIC_COMM_CHECK_POINT(p_ddr_cfg); + table_id = p_hash_entry_cfg->table_id; + ZXIC_COMM_CHECK_INDEX_UPPER(table_id,HASH_TBL_ID_NUM - 1); + p_rbkey_new = p_hash_entry_cfg->p_rbkey_new; + ZXIC_COMM_CHECK_POINT(p_rbkey_new); + + key_type = p_hash_entry_cfg->key_type; + if ((HASH_KEY_512b == key_type) && (DDR_WIDTH_256b == p_ddr_cfg->width_mode)) + { + ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "ErrorCode[0x%x]: Hash DDR width mode is not match to the key type.\n", DPP_HASH_RC_DDR_WIDTH_MODE_ERR); + return DPP_HASH_RC_DDR_WIDTH_MODE_ERR; + } + + key_by_size = p_hash_entry_cfg->key_by_size; + crc_value = p_hash_cfg->p_hash32_fun(p_temp_key, key_by_size, p_ddr_cfg->hash_ddr_arg); + ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev), "hash ddr arg is: 0x%x.crc_value is 0x%x\n", p_ddr_cfg->hash_ddr_arg, crc_value); /* t */ + item_idx = crc_value % p_ddr_cfg->item_num; /*按照256bit进行划分*/ + item_type = ITEM_DDR_256; + if (DDR_WIDTH_512b == p_ddr_cfg->width_mode) + { + item_idx = crc_value % p_ddr_cfg->item_num;/* 512b模式时，item_num已经在bulk初始化做过转换 ，按照512bit进行划分*/ + item_type = ITEM_DDR_512; + } + + ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev), "Hash insert in ITEM_DDR_%s, item_idx is: 0x%x.\n", ((item_type == ITEM_DDR_256) ? "256" : "512"), item_idx); + + ZXIC_COMM_CHECK_INDEX_UPPER(item_idx, p_ddr_cfg->item_num); /* modify coverity yinxh 2021.03.10*/ + p_item = p_ddr_cfg->p_item_array[item_idx]; + if (NULL == p_item) + { + p_item = (SE_ITEM_CFG *)ZXIC_COMM_MALLOC(sizeof(SE_ITEM_CFG)); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_item); + ZXIC_COMM_MEMSET(p_item, 0, sizeof(SE_ITEM_CFG)); + p_ddr_cfg->p_item_array[item_idx] = p_item; + } + + rc = dpp_hash_insrt_to_item(p_hash_cfg, + p_hash_entry_cfg->p_rbkey_new, + p_item, + item_idx, + item_type, + key_type); + + if (DPP_HASH_RC_ITEM_FULL != rc) + { + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_hash_insrt_to_item"); + *p_end_flag = 1; +#ifdef HASH_ENTRY_STAT + p_hash_cfg->hash_stat.insert_ddr++; + p_hash_cfg->hash_stat.insert_table[table_id].ddr++; +#endif + /* calc the item hardware address in DDR */ + ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(DEV_ID(dev), p_ddr_cfg->hw_baddr, item_idx); + p_item->hw_addr = GET_HASH_DDR_HW_ADDR(p_ddr_cfg->hw_baddr, item_idx); + p_item->bulk_id = p_hash_entry_cfg->bulk_id; + } + +#if OBTAIN_CONFLICT_KEY + /* debug start 获取冲突键值*/ + if (DPP_HASH_RC_ITEM_FULL == rc) + { + p_item->hw_addr = GET_HASH_DDR_HW_ADDR(p_ddr_cfg->hw_baddr, item_idx); + ZXIC_COMM_PRINT("ddr conflict item_idx is:0x%x,p_item->hw_addr is:0x%x\n", item_idx, p_item->hw_addr); + ZXIC_COMM_PRINT("ddr conflict key is:"); + + for (index = 0; index < 10; index++) + { + ZXIC_COMM_PRINT("0x%02x ", p_rbkey_new->key[index]); + } + + ZXIC_COMM_PRINT("\n"); + } + + /* debug end*/ +#endif + + return DPP_OK; +} + +DPP_STATUS dpp_hash_insert_zcell(DPP_DEV_T *dev,DPP_SE_CFG *p_se_cfg,HASH_ENTRY_CFG *p_hash_entry_cfg,ZXIC_UINT8 *p_temp_key,ZXIC_UINT8 *p_end_flag) +{ + ZXIC_UINT8 bulk_id = 0; + D_NODE *p_zcell_dn = NULL; + SE_ZCELL_CFG *p_zcell = NULL; + ZXIC_UINT32 zblk_idx = 0; + ZXIC_UINT32 zcell_id = 0; + ZXIC_UINT32 pre_zblk_idx = 0xFFFFFFFF;/* -1; */ + SE_ITEM_CFG *p_item = NULL; + ZXIC_UINT32 item_idx = 0xFFFFFFFF;/* -1 */ + ZXIC_UINT32 item_type = 0; + ZXIC_UINT32 rc = DPP_OK; + ZXIC_UINT32 crc_value = 0; + ZXIC_UINT8 table_id = 0; + DPP_HASH_CFG *p_hash_cfg = NULL; + SE_ZBLK_CFG *p_zblk = NULL; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_POINT(p_hash_entry_cfg); + ZXIC_COMM_CHECK_POINT(p_temp_key); + ZXIC_COMM_CHECK_POINT(p_se_cfg); + ZXIC_COMM_CHECK_POINT(p_end_flag); + + /* if insert into DDR is fail, insert into ZCAM. */ + ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev), "insert zcell start\n"); + bulk_id = p_hash_entry_cfg->bulk_id; + ZXIC_COMM_CHECK_INDEX_UPPER(bulk_id,HASH_BULK_NUM - 1); + table_id = p_hash_entry_cfg->table_id; + ZXIC_COMM_CHECK_INDEX_UPPER(table_id,HASH_TBL_ID_NUM - 1); + p_hash_cfg = p_hash_entry_cfg->p_hash_cfg; + ZXIC_COMM_CHECK_POINT(p_hash_cfg); + p_zcell_dn = p_hash_cfg->hash_shareram.zcell_free_list.p_next; + + while (p_zcell_dn) + { + p_zcell = (SE_ZCELL_CFG *)p_zcell_dn->data; + ZXIC_COMM_CHECK_POINT(p_zcell); + + /* 只在hash引擎开启zcell独占模式下，才进行相关的处理 */ + if (((p_zcell->flag & DPP_ZCELL_FLAG_IS_MONO) && (p_zcell->bulk_id != bulk_id)) + ||((!(p_zcell->flag & DPP_ZCELL_FLAG_IS_MONO)) && (p_hash_cfg->bulk_ram_mono[bulk_id]))) + { + p_zcell_dn = p_zcell_dn->next; + continue; + } + + zblk_idx = GET_ZBLK_IDX(p_zcell->zcell_idx); + ZXIC_COMM_CHECK_INDEX_UPPER(zblk_idx,SE_ZBLK_NUM - 1); + p_zblk = &(p_se_cfg->zblk_info[zblk_idx]); + if (zblk_idx != pre_zblk_idx) + { + pre_zblk_idx = zblk_idx; + crc_value = p_hash_cfg->p_hash16_fun(p_temp_key, p_hash_entry_cfg->key_by_size, p_zblk->hash_arg); + } + + ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev), "zblk_idx is [0x%x],p_zblk->hash_arg is [0x%x],crc_value is [0x%x]\n", zblk_idx, p_zblk->hash_arg, crc_value); /* t */ + + zcell_id = GET_ZCELL_IDX(p_zcell->zcell_idx); + item_idx = GET_ZCELL_CRC_VAL(zcell_id, crc_value); + ZXIC_COMM_CHECK_INDEX_UPPER(item_idx,SE_RAM_DEPTH - 1); + p_item = &(p_zcell->item_info[item_idx]); + item_type = ITEM_RAM; + + ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev), "zcell_id is [0x%x],item_idx is [0x%x]\n", zcell_id, item_idx); /* t */ + + rc = dpp_hash_insrt_to_item(p_hash_cfg, + p_hash_entry_cfg->p_rbkey_new, + p_item, + item_idx, + item_type, + p_hash_entry_cfg->key_type); + + if (DPP_HASH_RC_ITEM_FULL == rc) + { + ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev), "The item is full, check next. \n"); +#if OBTAIN_CONFLICT_KEY + + /* debug start 获取冲突键值*/ + if (DPP_HASH_RC_ITEM_FULL == rc) + { + p_item->hw_addr = ZBLK_ITEM_ADDR_CALC(p_zcell->zcell_idx, item_idx); + ZXIC_COMM_PRINT("zcell conflict item_idx is:0x%x,p_item->hw_addr is:0x%x\n", item_idx, p_item->hw_addr); + ZXIC_COMM_PRINT("zcell conflict key is:"); + + for (index = 0; index < 10; index++) + { + ZXIC_COMM_PRINT("0x%x ", p_rbkey_new->key[index]); + } + + ZXIC_COMM_PRINT("\n"); + } + + /* debug end*/ +#endif + } + else + { + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_hash_insrt_to_item"); + *p_end_flag = 1; +#ifdef HASH_ENTRY_STAT + p_hash_cfg->hash_stat.insert_zcell++; + p_hash_cfg->hash_stat.insert_table[table_id].zcell++; +#endif + + /* calc the item hardware address in ZCAM. */ + p_item->hw_addr = ZBLK_ITEM_ADDR_CALC(p_zcell->zcell_idx, item_idx); + /* debug start 获取冲突键值*/ + /* ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev), "ZCAM hw_addr is [0x%x]\n", p_item->hw_addr); t*/ + /* ZXIC_COMM_PRINT("after ddr conflict item_idx is:%d,p_item->hw_addr is:%d \n", item_idx, p_item->hw_addr);*/ + /* ZXIC_COMM_PRINT("after ddr conflict zcell_id is [0x%x],zblk_idx is [0x%x]\n", zcell_id, zblk_idx); t;*/ + /* debug end*/ + break; + } + + p_zcell_dn = p_zcell_dn->next; + } + + return DPP_OK; +} + +DPP_STATUS dpp_hash_insert_zreg(DPP_DEV_T *dev,HASH_ENTRY_CFG *p_hash_entry_cfg,ZXIC_UINT8 *p_temp_key,ZXIC_UINT8 *p_end_flag) +{ + DPP_HASH_CFG *p_hash_cfg = NULL; + D_NODE *p_zblk_dn = NULL; + SE_ZBLK_CFG *p_zblk = NULL; + SE_ZREG_CFG *p_zreg = NULL; + SE_ITEM_CFG *p_item = NULL; + ZXIC_UINT8 reg_index = 0; + ZXIC_UINT32 zblk_idx = 0; + ZXIC_UINT32 rc = DPP_OK; + ZXIC_UINT8 bulk_id = 0; + ZXIC_UINT32 item_idx = 0xFFFFFFFF;/* -1; */ + ZXIC_UINT32 item_type = 0; + ZXIC_UINT32 table_id = 0; + DPP_HASH_RBKEY_INFO *p_rbkey_new = NULL; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_POINT(p_hash_entry_cfg); + ZXIC_COMM_CHECK_POINT(p_temp_key); + ZXIC_COMM_CHECK_POINT(p_end_flag); + + ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev), "insert zreg start\n"); /* t */ + bulk_id = p_hash_entry_cfg->bulk_id; + ZXIC_COMM_CHECK_INDEX_UPPER(bulk_id,HASH_BULK_NUM - 1); + table_id = p_hash_entry_cfg->table_id; + ZXIC_COMM_CHECK_INDEX_UPPER(table_id,HASH_TBL_ID_NUM - 1); + p_rbkey_new = p_hash_entry_cfg->p_rbkey_new; + ZXIC_COMM_CHECK_POINT(p_rbkey_new); + + p_hash_cfg = p_hash_entry_cfg->p_hash_cfg; + p_zblk_dn = p_hash_cfg->hash_shareram.zblk_list.p_next; + while (p_zblk_dn) + { + p_zblk = (SE_ZBLK_CFG *)p_zblk_dn->data; + zblk_idx = p_zblk->zblk_idx; + + for (reg_index = 0; reg_index < SE_ZREG_NUM; reg_index++) + { + p_zreg = &(p_zblk->zreg_info[reg_index]); + + if (((p_zreg->flag & DPP_ZREG_FLAG_IS_MONO) && (p_zreg->bulk_id != bulk_id)) || + ((!(p_zreg->flag & DPP_ZREG_FLAG_IS_MONO)) && (p_hash_cfg->bulk_ram_mono[bulk_id]))) + { + continue; + } + + p_item = &(p_zblk->zreg_info[reg_index].item_info); + item_type = ITEM_REG; + item_idx = reg_index; + rc = dpp_hash_insrt_to_item(p_hash_cfg, + p_hash_entry_cfg->p_rbkey_new, + p_item, + item_idx, + item_type, + p_hash_entry_cfg->key_type); + + if (DPP_HASH_RC_ITEM_FULL == rc) + { + ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev), "The item is full, check next. \n"); +#if OBTAIN_CONFLICT_KEY + /* debug start 获取冲突键值*/ + ZXIC_COMM_PRINT("zreg_mono conflict,not inserted,reg_num is:0x%x,zblk_idx is:0x%x,p_item->hw_addr is:0x%x\n", reg_index, zblk_idx, p_item->hw_addr); + ZXIC_COMM_PRINT("zreg_mono conflict,key is:"); + + for (index = 0; index < 8; index++) + { + ZXIC_COMM_PRINT("0x%x ", p_rbkey_new->key[index]); + } + + ZXIC_COMM_PRINT("\n"); + /* debug end*/ +#endif + } + else + { + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_hash_insrt_to_item"); + *p_end_flag = 1; +#ifdef HASH_ENTRY_STAT + p_hash_cfg->hash_stat.insert_zreg++; + p_hash_cfg->hash_stat.insert_table[table_id].zreg++; +#endif + + /* calc the item hardware address in ZBLK Reg. */ + p_item->hw_addr = ZBLK_HASH_LIST_REG_ADDR_CALC(zblk_idx, reg_index); +#if OBTAIN_CONFLICT_KEY + /* debug start 获取冲突键值*/ + ZXIC_COMM_PRINT("zreg_mono conflict,inserted,reg_num is:0x%x,zblk_idx is:0x%x,p_item->hw_addr is:0x%x\n", reg_index, zblk_idx, p_item->hw_addr); + ZXIC_COMM_PRINT("zreg_mono conflict,key is:"); + + for (index = 0; index < 8; index++) + { + ZXIC_COMM_PRINT("0x%x ", p_rbkey_new->key[index]); + } + + ZXIC_COMM_PRINT("\n"); + /* debug end*/ +#endif + break; + } + } + + if (*p_end_flag) + { + break; + } + + p_zblk_dn = p_zblk_dn->next; + } + + return DPP_OK; +} + +/***********************************************************/ +/** +* @param p_se_cfg 算法模块公共管理数据结构指针 +* @param fun_id hash引擎号 +* @param p_zblk_cfg +* +* @return +* @remark 无 +* @see +* @author XCX @date 2017/03/27 +************************************************************/ +DPP_STATUS dpp_hash_zblkcfg_write(DPP_SE_CFG *p_se_cfg, ZXIC_UINT32 fun_id, SE_ZBLK_CFG *p_zblk_cfg) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_UINT8 ram_buf[SE_RAM_WIDTH / 8] = {0}; + + ZXIC_UINT32 dev_id = 0; + +#if DPP_WRITE_FILE_EN + ZXIC_UINT32 hw_addr = 0; +#endif + + ZXIC_COMM_CHECK_POINT(p_se_cfg); + ZXIC_COMM_CHECK_POINT(p_zblk_cfg); + ZXIC_COMM_CHECK_INDEX(fun_id, HASH_FUNC_ID_MIN, HASH_FUNC_ID_NUM - 1); + + dev_id = p_se_cfg->dev_id; + + /* write hash type*/ + rc = zxic_comm_write_bits_ex(ram_buf, + SE_RAM_WIDTH, + 1, + DPP_SE_ZBLK_SERVICE_TYPE_START, + DPP_SE_ZBLK_SERVICE_TYPE_START - DPP_SE_ZBLK_SERVICE_TYPE_END + 1); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "zxic_comm_write_bits_ex"); + + /* write hash channel*/ + rc = zxic_comm_write_bits_ex(ram_buf, + SE_RAM_WIDTH, + fun_id, + DPP_SE_ZBLK_HASH_CHAN_START, + DPP_SE_ZBLK_HASH_CHAN_START - DPP_SE_ZBLK_HASH_CHAN_END + 1); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "zxic_comm_write_bits_ex"); + + /* write enable flag*/ + rc = zxic_comm_write_bits_ex(ram_buf, + SE_RAM_WIDTH, + 1, + DPP_SE_ZBLK_HW_POS_EN_START, + DPP_SE_ZBLK_HW_POS_EN_START - DPP_SE_ZBLK_HW_POS_EN_END + 1); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "zxic_comm_write_bits_ex"); + +#if DPP_WRITE_FILE_EN + hw_addr = ZBLK_REG_ADDR_CALC(p_zblk_cfg->zblk_idx, 0); + + rc = dpp_data_w2f(hw_addr, ram_buf, FILE_TYPE_ZBLK_CFG); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_data_w2f"); +#endif + +#ifdef DPP_FLOW_HW_INIT + rc = dpp_se_zblk_serv_cfg_set(p_se_cfg->dev, + p_zblk_cfg->zblk_idx, + ALG_ZBLK_SERV_HASH, + fun_id, + 1); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_se_zblk_serv_cfg_set"); +#endif + + return DPP_OK; +} + +/***********************************************************/ +/** +* @param p_se_cfg 算法模块公共管理数据结构指针 +* @param hash_id hash引擎号 +* @param bulk_id +* +* @return +* @remark 无 +* @see +* @author XCX @date 2017/03/27 +************************************************************/ +DPP_STATUS dpp_hash_bulk_mono_flags_write(DPP_SE_CFG *p_se_cfg, ZXIC_UINT32 hash_id, ZXIC_UINT32 bulk_id) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 hash0_mono_flag = 0; + ZXIC_UINT32 hash1_mono_flag = 0; + ZXIC_UINT32 hash2_mono_flag = 0; + ZXIC_UINT32 hash3_mono_flag = 0; + +#if DPP_WRITE_FILE_EN + ZXIC_UINT32 hash0_mono_flag_file = 0; + ZXIC_UINT32 hash1_mono_flag_file = 0; + ZXIC_UINT32 hash2_mono_flag_file = 0; + ZXIC_UINT32 hash3_mono_flag_file = 0; + ZXIC_UINT32 hash_mono_flags_file_reg = 0; + ZXIC_UINT32 hash_mono_flags_file_reg_addr = 0; + DPP_HASH_FILE_REG_T *p_hash_file_reg = NULL; +#endif + + ZXIC_COMM_CHECK_POINT(p_se_cfg); + ZXIC_COMM_CHECK_INDEX(hash_id, HASH_FUNC_ID_MIN, HASH_FUNC_ID_NUM - 1); + ZXIC_COMM_CHECK_INDEX(bulk_id, HASH_BULK_ID_MIN, HASH_BULK_ID_MAX); + + dev_id = p_se_cfg->dev_id; + + rc = dpp_se_hash_zcam_mono_flags_get(p_se_cfg->dev, + &hash0_mono_flag, + &hash1_mono_flag, + &hash2_mono_flag, + &hash3_mono_flag); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_se_hash_zcam_mono_flags_get"); + + switch (hash_id) + { + case 0: + { + hash0_mono_flag |= (1U << bulk_id); + break; + } + + case 1: + { + hash1_mono_flag |= (1U << bulk_id); + break; + } + + case 2: + { + hash2_mono_flag |= (1U << bulk_id); + break; + } + + case 3: + { + hash3_mono_flag |= (1U << bulk_id); + break; + } + + default: + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n hash id is out of rang."); + ZXIC_COMM_ASSERT(0); + } + } + + rc = dpp_se_hash_zcam_mono_flags_set(p_se_cfg->dev, + hash0_mono_flag, + hash1_mono_flag, + hash2_mono_flag, + hash3_mono_flag); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_se_hash_zcam_mono_flags_set"); + +#if DPP_WRITE_FILE_EN + hash_mono_flags_file_reg_addr = 0x1c4; + + p_hash_file_reg = DPP_GET_HASH_FILE_REG(); + hash_mono_flags_file_reg = p_hash_file_reg->hash_mono_flags_file_reg; + + ZXIC_COMM_UINT32_GET_BITS(hash0_mono_flag_file, hash_mono_flags_file_reg, HASH0_MONO_FLAG_BT_START, HASH0_MONO_FLAG_BT_WIDTH); + ZXIC_COMM_UINT32_GET_BITS(hash1_mono_flag_file, hash_mono_flags_file_reg, HASH1_MONO_FLAG_BT_START, HASH1_MONO_FLAG_BT_WIDTH); + ZXIC_COMM_UINT32_GET_BITS(hash2_mono_flag_file, hash_mono_flags_file_reg, HASH2_MONO_FLAG_BT_START, HASH2_MONO_FLAG_BT_WIDTH); + ZXIC_COMM_UINT32_GET_BITS(hash3_mono_flag_file, hash_mono_flags_file_reg, HASH3_MONO_FLAG_BT_START, HASH3_MONO_FLAG_BT_WIDTH); + + switch (hash_id) + { + case 0: + { + hash0_mono_flag_file |= (1U << bulk_id); + break; + } + + case 1: + { + hash1_mono_flag_file |= (1U << bulk_id); + break; + } + + case 2: + { + hash2_mono_flag_file |= (1U << bulk_id); + break; + } + + case 3: + { + hash3_mono_flag_file |= (1U << bulk_id); + break; + } + + default: + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n hash id is out of rang."); + ZXIC_COMM_ASSERT(0); + } + } + + ZXIC_COMM_UINT32_WRITE_BITS(hash_mono_flags_file_reg, + hash0_mono_flag_file, + HASH0_MONO_FLAG_BT_START, + HASH0_MONO_FLAG_BT_WIDTH); + ZXIC_COMM_UINT32_WRITE_BITS(hash_mono_flags_file_reg, + hash1_mono_flag_file, + HASH1_MONO_FLAG_BT_START, + HASH1_MONO_FLAG_BT_WIDTH); + ZXIC_COMM_UINT32_WRITE_BITS(hash_mono_flags_file_reg, + hash2_mono_flag_file, + HASH2_MONO_FLAG_BT_START, + HASH2_MONO_FLAG_BT_WIDTH); + ZXIC_COMM_UINT32_WRITE_BITS(hash_mono_flags_file_reg, + hash3_mono_flag_file, + HASH3_MONO_FLAG_BT_START, + HASH3_MONO_FLAG_BT_WIDTH); + + p_hash_file_reg->hash_mono_flags_file_reg = hash_mono_flags_file_reg; + + rc = dpp_data_w2f(p_se_cfg->reg_base + hash_mono_flags_file_reg_addr, &p_hash_file_reg->hash_mono_flags_file_reg, FILE_TYPE_REG); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_data_w2f"); +#endif + + return DPP_OK; +} + +/***********************************************************/ +/** +* @param p_se_cfg 算法模块公共管理数据结构指针 +* @param p_zcell_cfg +* +* @return +* @remark 无 +* @see +* @author XCX @date 2017/03/27 +************************************************************/ +DPP_STATUS dpp_hash_zcell_mono_write(DPP_SE_CFG *p_se_cfg, SE_ZCELL_CFG *p_zcell_cfg) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_UINT32 zblk_idx = 0; + ZXIC_UINT32 zcell_id = 0; + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 zcell0_bulk_id = 0; + ZXIC_UINT32 zcell0_mono_flag = 0; + ZXIC_UINT32 zcell1_bulk_id = 0; + ZXIC_UINT32 zcell1_mono_flag = 0; + ZXIC_UINT32 zcell2_bulk_id = 0; + ZXIC_UINT32 zcell2_mono_flag = 0; + ZXIC_UINT32 zcell3_bulk_id = 0; + ZXIC_UINT32 zcell3_mono_flag = 0; + +#if DPP_WRITE_FILE_EN + ZXIC_UINT32 zcell0_bulk_id_file = 0; + ZXIC_UINT32 zcell0_mono_flag_file = 0; + ZXIC_UINT32 zcell1_bulk_id_file = 0; + ZXIC_UINT32 zcell1_mono_flag_file = 0; + ZXIC_UINT32 zcell2_bulk_id_file = 0; + ZXIC_UINT32 zcell2_mono_flag_file = 0; + ZXIC_UINT32 zcell3_bulk_id_file = 0; + ZXIC_UINT32 zcell3_mono_flag_file = 0; + ZXIC_UINT32 zcell_mono_file_ram_addr = 0; + + ZXIC_UINT8 *zcell_mono_file_ram = NULL; + DPP_HASH_FILE_REG_T *p_hash_file_reg = NULL; +#endif + + ZXIC_COMM_CHECK_POINT(p_se_cfg); + ZXIC_COMM_CHECK_POINT(p_zcell_cfg); + + dev_id = p_se_cfg->dev_id; + + zblk_idx = GET_ZBLK_IDX(p_zcell_cfg->zcell_idx); + zcell_id = p_zcell_cfg->zcell_idx & 0x3; + rc = dpp_se_zcell_mono_cfg_get(p_se_cfg->dev, + zblk_idx, + &zcell0_bulk_id, + &zcell0_mono_flag, + &zcell1_bulk_id, + &zcell1_mono_flag, + &zcell2_bulk_id, + &zcell2_mono_flag, + &zcell3_bulk_id, + &zcell3_mono_flag); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_se_zcell_mono_cfg_get"); + + switch (zcell_id) + { + case 0: + { + zcell0_bulk_id = p_zcell_cfg->bulk_id; + zcell0_mono_flag = 1; + break; + } + + case 1: + { + zcell1_bulk_id = p_zcell_cfg->bulk_id; + zcell1_mono_flag = 1; + break; + } + + case 2: + { + zcell2_bulk_id = p_zcell_cfg->bulk_id; + zcell2_mono_flag = 1; + break; + } + + case 3: + { + zcell3_bulk_id = p_zcell_cfg->bulk_id; + zcell3_mono_flag = 1; + break; + } + + } + + rc = dpp_se_zcell_mono_cfg_set(p_se_cfg->dev, + zblk_idx, + zcell0_bulk_id, + zcell0_mono_flag, + zcell1_bulk_id, + zcell1_mono_flag, + zcell2_bulk_id, + zcell2_mono_flag, + zcell3_bulk_id, + zcell3_mono_flag); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_se_zcell_mono_cfg_set"); + +#if DPP_WRITE_FILE_EN + zcell_mono_file_ram_addr = ZBLK_REG_ADDR_CALC(zblk_idx, 0x14); + + p_hash_file_reg = DPP_GET_HASH_FILE_REG(); + zcell_mono_file_ram = p_hash_file_reg->zcell_mono_file_ram; + + if (0 == zcell_id) + { + ZXIC_COMM_MEMSET(zcell_mono_file_ram, 0, (SE_RAM_WIDTH / 8)); + } + + zxic_comm_read_bits_ex(zcell_mono_file_ram, SE_RAM_WIDTH, &zcell0_bulk_id_file, ZCELL0_BULK_ID_BT_START, ZCELL0_BULK_ID_BT_WIDTH); + zxic_comm_read_bits_ex(zcell_mono_file_ram, SE_RAM_WIDTH, &zcell0_mono_flag_file, ZCELL0_MONO_FLAG_BT_START, ZCELL0_MONO_FLAG_BT_WIDTH); + zxic_comm_read_bits_ex(zcell_mono_file_ram, SE_RAM_WIDTH, &zcell1_bulk_id_file, ZCELL1_BULK_ID_BT_START, ZCELL1_BULK_ID_BT_WIDTH); + zxic_comm_read_bits_ex(zcell_mono_file_ram, SE_RAM_WIDTH, &zcell1_mono_flag_file, ZCELL1_MONO_FLAG_BT_START, ZCELL1_MONO_FLAG_BT_WIDTH); + zxic_comm_read_bits_ex(zcell_mono_file_ram, SE_RAM_WIDTH, &zcell2_bulk_id_file, ZCELL2_BULK_ID_BT_START, ZCELL2_BULK_ID_BT_WIDTH); + zxic_comm_read_bits_ex(zcell_mono_file_ram, SE_RAM_WIDTH, &zcell2_mono_flag_file, ZCELL2_MONO_FLAG_BT_START, ZCELL2_MONO_FLAG_BT_WIDTH); + zxic_comm_read_bits_ex(zcell_mono_file_ram, SE_RAM_WIDTH, &zcell3_bulk_id_file, ZCELL3_BULK_ID_BT_START, ZCELL3_BULK_ID_BT_WIDTH); + zxic_comm_read_bits_ex(zcell_mono_file_ram, SE_RAM_WIDTH, &zcell3_mono_flag_file, ZCELL3_MONO_FLAG_BT_START, ZCELL3_MONO_FLAG_BT_WIDTH); + + switch (zcell_id) + { + case 0: + { + zcell0_bulk_id_file = p_zcell_cfg->bulk_id; + zcell0_mono_flag_file = 1; + break; + } + + case 1: + { + zcell1_bulk_id_file = p_zcell_cfg->bulk_id; + zcell1_mono_flag_file = 1; + break; + } + + case 2: + { + zcell2_bulk_id_file = p_zcell_cfg->bulk_id; + zcell2_mono_flag_file = 1; + break; + } + + case 3: + { + zcell3_bulk_id_file = p_zcell_cfg->bulk_id; + zcell3_mono_flag_file = 1; + break; + } + + default: + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n zcell id is out of rang."); + ZXIC_COMM_ASSERT(0); + } + } + + zxic_comm_write_bits_ex(zcell_mono_file_ram, + SE_RAM_WIDTH, + zcell0_bulk_id_file, + ZCELL0_BULK_ID_BT_START, + ZCELL0_BULK_ID_BT_WIDTH); + zxic_comm_write_bits_ex(zcell_mono_file_ram, + SE_RAM_WIDTH, + zcell0_mono_flag_file, + ZCELL0_MONO_FLAG_BT_START, + ZCELL0_MONO_FLAG_BT_WIDTH); + zxic_comm_write_bits_ex(zcell_mono_file_ram, + SE_RAM_WIDTH, + zcell1_bulk_id_file, + ZCELL1_BULK_ID_BT_START, + ZCELL1_BULK_ID_BT_WIDTH); + zxic_comm_write_bits_ex(zcell_mono_file_ram, + SE_RAM_WIDTH, + zcell1_mono_flag_file, + ZCELL1_MONO_FLAG_BT_START, + ZCELL1_MONO_FLAG_BT_WIDTH); + zxic_comm_write_bits_ex(zcell_mono_file_ram, + SE_RAM_WIDTH, + zcell2_bulk_id_file, + ZCELL2_BULK_ID_BT_START, + ZCELL2_BULK_ID_BT_WIDTH); + zxic_comm_write_bits_ex(zcell_mono_file_ram, + SE_RAM_WIDTH, + zcell2_mono_flag_file, + ZCELL2_MONO_FLAG_BT_START, + ZCELL2_MONO_FLAG_BT_WIDTH); + zxic_comm_write_bits_ex(zcell_mono_file_ram, + SE_RAM_WIDTH, + zcell3_bulk_id_file, + ZCELL3_BULK_ID_BT_START, + ZCELL3_BULK_ID_BT_WIDTH); + zxic_comm_write_bits_ex(zcell_mono_file_ram, + SE_RAM_WIDTH, + zcell3_mono_flag_file, + ZCELL3_MONO_FLAG_BT_START, + ZCELL3_MONO_FLAG_BT_WIDTH); + + rc = dpp_data_w2f(zcell_mono_file_ram_addr, &p_hash_file_reg->zcell_mono_file_ram, FILE_TYPE_ZBLK_CFG); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_data_w2f"); +#endif + + return DPP_OK; +} + +/***********************************************************/ +/** +* @param p_se_cfg 算法模块公共管理数据结构指针 +* @param bulk_id +* @param zblk_idx +* @param zreg_id +* +* @return +* @remark 无 +* @see +* @author XCX @date 2017/03/27 +************************************************************/ +DPP_STATUS dpp_hash_zreg_mono_write(DPP_SE_CFG *p_se_cfg, + ZXIC_UINT32 bulk_id, + ZXIC_UINT32 zblk_idx, + ZXIC_UINT32 zreg_id) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 zreg0_bulk_id = 0; + ZXIC_UINT32 zreg0_mono_flag = 0; + ZXIC_UINT32 zreg1_bulk_id = 0; + ZXIC_UINT32 zreg1_mono_flag = 0; + ZXIC_UINT32 zreg2_bulk_id = 0; + ZXIC_UINT32 zreg2_mono_flag = 0; + ZXIC_UINT32 zreg3_bulk_id = 0; + ZXIC_UINT32 zreg3_mono_flag = 0; + +#if DPP_WRITE_FILE_EN + ZXIC_UINT32 zreg0_bulk_id_file = 0; + ZXIC_UINT32 zreg0_mono_flag_file = 0; + ZXIC_UINT32 zreg1_bulk_id_file = 0; + ZXIC_UINT32 zreg1_mono_flag_file = 0; + ZXIC_UINT32 zreg2_bulk_id_file = 0; + ZXIC_UINT32 zreg2_mono_flag_file = 0; + ZXIC_UINT32 zreg3_bulk_id_file = 0; + ZXIC_UINT32 zreg3_mono_flag_file = 0; + ZXIC_UINT8 *zreg_mono_file_ram = NULL; + ZXIC_UINT32 zreg_mono_file_ram_addr = 0; + DPP_HASH_FILE_REG_T *p_hash_file_reg = NULL; +#endif + + ZXIC_COMM_CHECK_POINT(p_se_cfg); + + dev_id = p_se_cfg->dev_id; + + rc = dpp_se_zreg_mono_cfg_get(p_se_cfg->dev, + zblk_idx, + &zreg0_bulk_id, + &zreg0_mono_flag, + &zreg1_bulk_id, + &zreg1_mono_flag, + &zreg2_bulk_id, + &zreg2_mono_flag, + &zreg3_bulk_id, + &zreg3_mono_flag); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_se_zreg_mono_cfg_get"); + + switch (zreg_id) + { + case 0: + { + zreg0_bulk_id = bulk_id; + zreg0_mono_flag = 1; + break; + } + + case 1: + { + zreg1_bulk_id = bulk_id; + zreg1_mono_flag = 1; + break; + } + + case 2: + { + zreg2_bulk_id = bulk_id; + zreg2_mono_flag = 1; + break; + } + + case 3: + { + zreg3_bulk_id = bulk_id; + zreg3_mono_flag = 1; + break; + } + + default: + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n zreg id is out of rang."); + ZXIC_COMM_ASSERT(0); + } + } + + rc = dpp_se_zreg_mono_cfg_set(p_se_cfg->dev, + zblk_idx, + zreg0_bulk_id, + zreg0_mono_flag, + zreg1_bulk_id, + zreg1_mono_flag, + zreg2_bulk_id, + zreg2_mono_flag, + zreg3_bulk_id, + zreg3_mono_flag); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_se_zreg_mono_cfg_set"); + +#if DPP_WRITE_FILE_EN + zreg_mono_file_ram_addr = ZBLK_REG_ADDR_CALC(zblk_idx, 0x15); + + p_hash_file_reg = DPP_GET_HASH_FILE_REG(); + zreg_mono_file_ram = p_hash_file_reg->zreg_mono_file_ram; + + if (0 == zreg_id) + { + ZXIC_COMM_MEMSET(zreg_mono_file_ram, 0, (SE_RAM_WIDTH / 8)); + } + + zxic_comm_read_bits_ex(zreg_mono_file_ram, + SE_RAM_WIDTH, + &zreg0_bulk_id_file, + ZREG0_BULK_ID_BT_START, + ZREG0_BULK_ID_BT_WIDTH); + zxic_comm_read_bits_ex(zreg_mono_file_ram, + SE_RAM_WIDTH, + &zreg0_mono_flag_file, + ZREG0_MONO_FLAG_BT_START, + ZREG0_MONO_FLAG_BT_WIDTH); + zxic_comm_read_bits_ex(zreg_mono_file_ram, + SE_RAM_WIDTH, + &zreg1_bulk_id_file, + ZREG1_BULK_ID_BT_START, + ZREG1_BULK_ID_BT_WIDTH); + zxic_comm_read_bits_ex(zreg_mono_file_ram, + SE_RAM_WIDTH, + &zreg1_mono_flag_file, + ZREG1_MONO_FLAG_BT_START, + ZREG1_MONO_FLAG_BT_WIDTH); + zxic_comm_read_bits_ex(zreg_mono_file_ram, + SE_RAM_WIDTH, + &zreg2_bulk_id_file, + ZREG2_BULK_ID_BT_START, + ZREG2_BULK_ID_BT_WIDTH); + zxic_comm_read_bits_ex(zreg_mono_file_ram, + SE_RAM_WIDTH, + &zreg2_mono_flag_file, + ZREG2_MONO_FLAG_BT_START, + ZREG2_MONO_FLAG_BT_WIDTH); + zxic_comm_read_bits_ex(zreg_mono_file_ram, + SE_RAM_WIDTH, + &zreg3_bulk_id_file, + ZREG3_BULK_ID_BT_START, + ZREG3_BULK_ID_BT_WIDTH); + zxic_comm_read_bits_ex(zreg_mono_file_ram, + SE_RAM_WIDTH, + &zreg3_mono_flag_file, + ZREG3_MONO_FLAG_BT_START, + ZREG3_MONO_FLAG_BT_WIDTH); + + switch (zreg_id) + { + case 0: + { + zreg0_bulk_id_file = bulk_id; + zreg0_mono_flag_file = 1; + break; + } + + case 1: + { + zreg1_bulk_id_file = bulk_id; + zreg1_mono_flag_file = 1; + break; + } + + case 2: + { + zreg2_bulk_id_file = bulk_id; + zreg2_mono_flag_file = 1; + break; + } + + case 3: + { + zreg3_bulk_id_file = bulk_id; + zreg3_mono_flag_file = 1; + break; + } + + default: + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n zcell id is out of rang."); + ZXIC_COMM_ASSERT(0); + } + } + + zxic_comm_write_bits_ex(zreg_mono_file_ram, + SE_RAM_WIDTH, + zreg0_bulk_id_file, + ZREG0_BULK_ID_BT_START, + ZREG0_BULK_ID_BT_WIDTH); + zxic_comm_write_bits_ex(zreg_mono_file_ram, + SE_RAM_WIDTH, + zreg0_mono_flag_file, + ZREG0_MONO_FLAG_BT_START, + ZREG0_MONO_FLAG_BT_WIDTH); + zxic_comm_write_bits_ex(zreg_mono_file_ram, + SE_RAM_WIDTH, + zreg1_bulk_id_file, + ZREG1_BULK_ID_BT_START, + ZREG1_BULK_ID_BT_WIDTH); + zxic_comm_write_bits_ex(zreg_mono_file_ram, + SE_RAM_WIDTH, + zreg1_mono_flag_file, + ZREG1_MONO_FLAG_BT_START, + ZREG1_MONO_FLAG_BT_WIDTH); + zxic_comm_write_bits_ex(zreg_mono_file_ram, + SE_RAM_WIDTH, + zreg2_bulk_id_file, + ZREG2_BULK_ID_BT_START, + ZREG2_BULK_ID_BT_WIDTH); + zxic_comm_write_bits_ex(zreg_mono_file_ram, + SE_RAM_WIDTH, + zreg2_mono_flag_file, + ZREG2_MONO_FLAG_BT_START, + ZREG2_MONO_FLAG_BT_WIDTH); + zxic_comm_write_bits_ex(zreg_mono_file_ram, + SE_RAM_WIDTH, + zreg3_bulk_id_file, + ZREG3_BULK_ID_BT_START, + ZREG3_BULK_ID_BT_WIDTH); + zxic_comm_write_bits_ex(zreg_mono_file_ram, + SE_RAM_WIDTH, + zreg3_mono_flag_file, + ZREG3_MONO_FLAG_BT_START, + ZREG3_MONO_FLAG_BT_WIDTH); + + rc = dpp_data_w2f(zreg_mono_file_ram_addr, &p_hash_file_reg->zreg_mono_file_ram, FILE_TYPE_ZBLK_CFG); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_data_w2f"); +#endif + + return DPP_OK; +} + +/***********************************************************/ +/** hash ddr参数配置 +* @param p_se_cfg 算法模块公共管理数据结构指针 +* @param fun_id hash引擎号 +* @param bulk_id +* @param p_ddr_cfg +* +* @return +* @remark 无 +* @see +* @author wcl @date 2014/07/31 +************************************************************/ +DPP_STATUS dpp_hash_ext_cfg_write(DPP_SE_CFG *p_se_cfg, + ZXIC_UINT32 fun_id, + ZXIC_UINT32 bulk_id, + HASH_DDR_CFG *p_ddr_cfg) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_UINT32 ext_mode = 0; + ZXIC_UINT32 ext_flag = 0; + ZXIC_UINT32 dev_id = 0; + +#if DPP_WRITE_FILE_EN + ZXIC_UINT32 ext_mode_file = 0; + ZXIC_UINT32 ext_flag_file = 0; + ZXIC_UINT32 ext_cfg_file_reg = 0; + ZXIC_UINT32 ext_cfg_file_reg_addr = 0; + DPP_HASH_FILE_REG_T *p_hash_file_reg = NULL; +#endif + + ZXIC_COMM_CHECK_POINT(p_se_cfg); + ZXIC_COMM_CHECK_POINT(p_ddr_cfg); + ZXIC_COMM_CHECK_INDEX(fun_id, DPP_HASH_ID_MIN, DPP_HASH_ID_MAX); + ZXIC_COMM_CHECK_INDEX(bulk_id, HASH_BULK_ID_MIN, HASH_BULK_ID_MAX); + + dev_id = p_se_cfg->dev_id; + + rc = dpp_se_hash_ext_cfg_get(p_se_cfg->dev, fun_id, &ext_mode, &ext_flag); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_se_hash_ext_cfg_get"); + + ext_flag = 1; + + if (p_ddr_cfg->width_mode == DDR_WIDTH_256b) + { + ext_mode = (ext_mode & (~(1U << bulk_id))); + } + else if (p_ddr_cfg->width_mode == DDR_WIDTH_512b) + { + ext_mode = (ext_mode | (1U << bulk_id)); + } + +#if DPP_WRITE_FILE_EN + ext_cfg_file_reg_addr = 0xbc + fun_id * 4; + + p_hash_file_reg = DPP_GET_HASH_FILE_REG(); + ext_cfg_file_reg = p_hash_file_reg->ext_cfg_file_reg[fun_id]; + + ZXIC_COMM_UINT32_GET_BITS(ext_mode_file, + ext_cfg_file_reg, + HASH_EXT_MODE_BT_START, + HASH_EXT_MODE_BT_WIDTH); + ZXIC_COMM_UINT32_GET_BITS(ext_flag_file, + ext_cfg_file_reg, + HASH_EXT_FLAG_BT_START, + HASH_EXT_FLAG_BT_WIDTH); + + ext_flag_file = 1; + + if (DDR_WIDTH_256b == p_ddr_cfg->width_mode) + { + ext_mode_file = (ext_mode_file & (~(1U << bulk_id))); + } + else if (p_ddr_cfg->width_mode == DDR_WIDTH_512b) + { + ext_mode_file = (ext_mode_file | (1U << bulk_id)); + } + + ZXIC_COMM_UINT32_WRITE_BITS(ext_cfg_file_reg, + ext_mode_file, + HASH_EXT_MODE_BT_START, + HASH_EXT_MODE_BT_WIDTH); + ZXIC_COMM_UINT32_WRITE_BITS(ext_cfg_file_reg, + ext_flag_file, + HASH_EXT_FLAG_BT_START, + HASH_EXT_FLAG_BT_WIDTH); + + p_hash_file_reg->ext_cfg_file_reg[fun_id] = ext_cfg_file_reg; + + rc = dpp_data_w2f(p_se_cfg->reg_base + ext_cfg_file_reg_addr, &p_hash_file_reg->ext_cfg_file_reg[fun_id], FILE_TYPE_REG); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_data_w2f"); +#endif + + rc = dpp_se_hash_ext_cfg_set(p_se_cfg->dev, fun_id, ext_mode, ext_flag); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_se_hash_ext_cfg_set"); + + return DPP_OK; +} + +/***********************************************************/ +/** +* @param p_se_cfg 算法模块公共管理数据结构指针 +* @param fun_id hash引擎号 +* +* @return +* @remark 无 +* @see +* @author wcl @date 2014/07/31 +************************************************************/ +DPP_STATUS dpp_hash_ext_cfg_clr(DPP_SE_CFG *p_se_cfg, ZXIC_UINT32 fun_id) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_UINT32 ext_mode = 0; + ZXIC_UINT32 ext_flag = 0; + ZXIC_UINT32 dev_id = 0; + +#if DPP_WRITE_FILE_EN + ZXIC_UINT32 ddr_cfg_dat = 0; + ZXIC_UINT32 ext_cfg_reg_addr = 0; +#endif + + ZXIC_COMM_CHECK_POINT(p_se_cfg); + ZXIC_COMM_CHECK_INDEX(fun_id, DPP_HASH_ID_MIN, DPP_HASH_ID_MAX); + + dev_id = p_se_cfg->dev_id; + +#if DPP_WRITE_FILE_EN + ext_cfg_reg_addr = 0xbc + fun_id * 4; + + rc = dpp_data_w2f(p_se_cfg->reg_base + ext_cfg_reg_addr, &ddr_cfg_dat, FILE_TYPE_REG); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_data_w2f"); +#endif + + rc = dpp_se_hash_ext_cfg_set(p_se_cfg->dev, + fun_id, + ext_mode, + ext_flag); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_se_hash_ext_cfg_set"); + + return DPP_OK; +} + +/***********************************************************/ +/** hash 业务表ddr深度配置 +* @param p_se_cfg 算法模块公共管理数据结构指针 +* @param fun_id hash引擎号 +* @param bulk_id +* @param p_ddr_cfg +* +* @return +* @remark 无 +* @see +* @author tf @date 2016/01/28 +************************************************************/ +DPP_STATUS dpp_hash_tbl_depth_write(DPP_SE_CFG *p_se_cfg, + ZXIC_UINT32 fun_id, + ZXIC_UINT32 bulk_id, + HASH_DDR_CFG *p_ddr_cfg) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_UINT32 ext_depth = 0; + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 hash_tbl0_depth = 0; + ZXIC_UINT32 hash_tbl1_depth = 0; + ZXIC_UINT32 hash_tbl2_depth = 0; + ZXIC_UINT32 hash_tbl3_depth = 0; + ZXIC_UINT32 hash_tbl4_depth = 0; + ZXIC_UINT32 hash_tbl5_depth = 0; + ZXIC_UINT32 hash_tbl6_depth = 0; + ZXIC_UINT32 hash_tbl7_depth = 0; + +#if DPP_WRITE_FILE_EN + ZXIC_UINT32 hash_tbl0_depth_file = 0; + ZXIC_UINT32 hash_tbl1_depth_file = 0; + ZXIC_UINT32 hash_tbl2_depth_file = 0; + ZXIC_UINT32 hash_tbl3_depth_file = 0; + ZXIC_UINT32 hash_tbl4_depth_file = 0; + ZXIC_UINT32 hash_tbl5_depth_file = 0; + ZXIC_UINT32 hash_tbl6_depth_file = 0; + ZXIC_UINT32 hash_tbl7_depth_file = 0; + ZXIC_UINT32 tbl03_depth_file_reg = 0; + ZXIC_UINT32 tbl47_depth_file_reg = 0; + ZXIC_UINT32 hash_tbl_depth_file_reg_addr = 0; + DPP_HASH_FILE_REG_T *p_hash_file_reg = NULL; +#endif + + ZXIC_UINT32 hash_tbl_depth_array[HASH_BULK_NUM] = {0}; + + ZXIC_COMM_CHECK_POINT(p_se_cfg); + ZXIC_COMM_CHECK_POINT(p_ddr_cfg); + ZXIC_COMM_CHECK_INDEX(fun_id, DPP_HASH_ID_MIN, DPP_HASH_ID_MAX); + ZXIC_COMM_CHECK_INDEX(bulk_id, HASH_BULK_ID_MIN, HASH_BULK_ID_MAX); + + dev_id = p_se_cfg->dev_id; + + ext_depth = dpp_hash_ddr_depth_conv(p_ddr_cfg->item_num); + + if (((ZXIC_UINT32)1 << ext_depth) != p_ddr_cfg->item_num) + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "ErrCode[ 0x%x ]: Hash DDR item num:[ %d ] is not N power of 2.\n", + DPP_HASH_RC_INVALID_PARA, + p_ddr_cfg->item_num); + ZXIC_COMM_ASSERT(0); + return DPP_HASH_RC_INVALID_PARA; + } + + rc = dpp_se_hash_tbl_depth_get(p_se_cfg->dev, + fun_id, + &hash_tbl0_depth, + &hash_tbl1_depth, + &hash_tbl2_depth, + &hash_tbl3_depth, + &hash_tbl4_depth, + &hash_tbl5_depth, + &hash_tbl6_depth, + &hash_tbl7_depth); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_se_hash_tbl_depth_get"); + + hash_tbl_depth_array[0] = hash_tbl0_depth; + hash_tbl_depth_array[1] = hash_tbl1_depth; + hash_tbl_depth_array[2] = hash_tbl2_depth; + hash_tbl_depth_array[3] = hash_tbl3_depth; + hash_tbl_depth_array[4] = hash_tbl4_depth; + hash_tbl_depth_array[5] = hash_tbl5_depth; + hash_tbl_depth_array[6] = hash_tbl6_depth; + hash_tbl_depth_array[7] = hash_tbl7_depth; + + + hash_tbl_depth_array[bulk_id] = ext_depth; + + hash_tbl0_depth = hash_tbl_depth_array[0]; + hash_tbl1_depth = hash_tbl_depth_array[1]; + hash_tbl2_depth = hash_tbl_depth_array[2]; + hash_tbl3_depth = hash_tbl_depth_array[3]; + hash_tbl4_depth = hash_tbl_depth_array[4]; + hash_tbl5_depth = hash_tbl_depth_array[5]; + hash_tbl6_depth = hash_tbl_depth_array[6]; + hash_tbl7_depth = hash_tbl_depth_array[7]; + +#if DPP_WRITE_FILE_EN + hash_tbl_depth_file_reg_addr = 0x01a4 + fun_id * 8; + + p_hash_file_reg = DPP_GET_HASH_FILE_REG(); + tbl03_depth_file_reg = p_hash_file_reg->hash_depth_file_regs[fun_id].tbl03_depth_file_reg; + tbl47_depth_file_reg = p_hash_file_reg->hash_depth_file_regs[fun_id].tbl47_depth_file_reg; + + ZXIC_COMM_UINT32_GET_BITS(hash_tbl0_depth_file, tbl03_depth_file_reg, HASH_TBL0_DEPTH_BT_START, HASH_TBL0_DEPTH_BT_WIDTH); + ZXIC_COMM_UINT32_GET_BITS(hash_tbl1_depth_file, tbl03_depth_file_reg, HASH_TBL1_DEPTH_BT_START, HASH_TBL1_DEPTH_BT_WIDTH); + ZXIC_COMM_UINT32_GET_BITS(hash_tbl2_depth_file, tbl03_depth_file_reg, HASH_TBL2_DEPTH_BT_START, HASH_TBL2_DEPTH_BT_WIDTH); + ZXIC_COMM_UINT32_GET_BITS(hash_tbl3_depth_file, tbl03_depth_file_reg, HASH_TBL3_DEPTH_BT_START, HASH_TBL3_DEPTH_BT_WIDTH); + + ZXIC_COMM_UINT32_GET_BITS(hash_tbl4_depth_file, tbl47_depth_file_reg, HASH_TBL4_DEPTH_BT_START, HASH_TBL4_DEPTH_BT_WIDTH); + ZXIC_COMM_UINT32_GET_BITS(hash_tbl5_depth_file, tbl47_depth_file_reg, HASH_TBL5_DEPTH_BT_START, HASH_TBL5_DEPTH_BT_WIDTH); + ZXIC_COMM_UINT32_GET_BITS(hash_tbl6_depth_file, tbl47_depth_file_reg, HASH_TBL6_DEPTH_BT_START, HASH_TBL6_DEPTH_BT_WIDTH); + ZXIC_COMM_UINT32_GET_BITS(hash_tbl7_depth_file, tbl47_depth_file_reg, HASH_TBL7_DEPTH_BT_START, HASH_TBL7_DEPTH_BT_WIDTH); + + hash_tbl_depth_array[0] = hash_tbl0_depth_file; + hash_tbl_depth_array[1] = hash_tbl1_depth_file; + hash_tbl_depth_array[2] = hash_tbl2_depth_file; + hash_tbl_depth_array[3] = hash_tbl3_depth_file; + hash_tbl_depth_array[4] = hash_tbl4_depth_file; + hash_tbl_depth_array[5] = hash_tbl5_depth_file; + hash_tbl_depth_array[6] = hash_tbl6_depth_file; + hash_tbl_depth_array[7] = hash_tbl7_depth_file; + + + hash_tbl_depth_array[bulk_id] = ext_depth; + + hash_tbl0_depth_file = hash_tbl_depth_array[0]; + hash_tbl1_depth_file = hash_tbl_depth_array[1]; + hash_tbl2_depth_file = hash_tbl_depth_array[2]; + hash_tbl3_depth_file = hash_tbl_depth_array[3]; + hash_tbl4_depth_file = hash_tbl_depth_array[4]; + hash_tbl5_depth_file = hash_tbl_depth_array[5]; + hash_tbl6_depth_file = hash_tbl_depth_array[6]; + hash_tbl7_depth_file = hash_tbl_depth_array[7]; + + ZXIC_COMM_UINT32_WRITE_BITS(tbl03_depth_file_reg, hash_tbl0_depth_file, HASH_TBL0_DEPTH_BT_START, HASH_TBL0_DEPTH_BT_WIDTH); + ZXIC_COMM_UINT32_WRITE_BITS(tbl03_depth_file_reg, hash_tbl1_depth_file, HASH_TBL1_DEPTH_BT_START, HASH_TBL1_DEPTH_BT_WIDTH); + ZXIC_COMM_UINT32_WRITE_BITS(tbl03_depth_file_reg, hash_tbl2_depth_file, HASH_TBL2_DEPTH_BT_START, HASH_TBL2_DEPTH_BT_WIDTH); + ZXIC_COMM_UINT32_WRITE_BITS(tbl03_depth_file_reg, hash_tbl3_depth_file, HASH_TBL3_DEPTH_BT_START, HASH_TBL3_DEPTH_BT_WIDTH); + + ZXIC_COMM_UINT32_WRITE_BITS(tbl47_depth_file_reg, hash_tbl4_depth_file, HASH_TBL4_DEPTH_BT_START, HASH_TBL4_DEPTH_BT_WIDTH); + ZXIC_COMM_UINT32_WRITE_BITS(tbl47_depth_file_reg, hash_tbl5_depth_file, HASH_TBL5_DEPTH_BT_START, HASH_TBL5_DEPTH_BT_WIDTH); + ZXIC_COMM_UINT32_WRITE_BITS(tbl47_depth_file_reg, hash_tbl6_depth_file, HASH_TBL6_DEPTH_BT_START, HASH_TBL6_DEPTH_BT_WIDTH); + ZXIC_COMM_UINT32_WRITE_BITS(tbl47_depth_file_reg, hash_tbl7_depth_file, HASH_TBL7_DEPTH_BT_START, HASH_TBL7_DEPTH_BT_WIDTH); + + p_hash_file_reg->hash_depth_file_regs[fun_id].tbl03_depth_file_reg = tbl03_depth_file_reg; + p_hash_file_reg->hash_depth_file_regs[fun_id].tbl47_depth_file_reg = tbl47_depth_file_reg; + + rc = dpp_data_w2f(p_se_cfg->reg_base + hash_tbl_depth_file_reg_addr, &tbl03_depth_file_reg, FILE_TYPE_REG); + rc = dpp_data_w2f(p_se_cfg->reg_base + hash_tbl_depth_file_reg_addr + 4, &tbl47_depth_file_reg, FILE_TYPE_REG) + rc; + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_data_w2f"); +#endif + + rc = dpp_se_hash_tbl_depth_set(p_se_cfg->dev, + fun_id, + hash_tbl0_depth, + hash_tbl1_depth, + hash_tbl2_depth, + hash_tbl3_depth, + hash_tbl4_depth, + hash_tbl5_depth, + hash_tbl6_depth, + hash_tbl7_depth); + + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_se_hash_tbl_depth_set"); + + return DPP_OK; +} + +/***********************************************************/ +/** hash 业务表ddr深度恢复默认值 +* @param p_se_cfg 算法模块公共管理数据结构指针 +* @param fun_id hash引擎号 +* +* @return +* @remark 无 +* @see +* @author tf @date 2016/01/28 +************************************************************/ +DPP_STATUS dpp_hash_tbl_depth_clr(DPP_SE_CFG *p_se_cfg, ZXIC_UINT32 fun_id) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 hash_tbl0_depth = 0x12; + ZXIC_UINT32 hash_tbl1_depth = 0x12; + ZXIC_UINT32 hash_tbl2_depth = 0x12; + ZXIC_UINT32 hash_tbl3_depth = 0x12; + ZXIC_UINT32 hash_tbl4_depth = 0x12; + ZXIC_UINT32 hash_tbl5_depth = 0x12; + ZXIC_UINT32 hash_tbl6_depth = 0x12; + ZXIC_UINT32 hash_tbl7_depth = 0x12; + +#if DPP_WRITE_FILE_EN + ZXIC_UINT32 hash_tbl_depth_reg_file_addr = 0; + ZXIC_UINT32 hash_tbl03_depth_reg_file_dat = 0; + ZXIC_UINT32 hash_tbl47_depth_reg_file_dat = 0; +#endif + + ZXIC_COMM_CHECK_POINT(p_se_cfg); + ZXIC_COMM_CHECK_INDEX(fun_id, DPP_HASH_ID_MIN, DPP_HASH_ID_MAX); + + dev_id = p_se_cfg->dev_id; + +#if DPP_WRITE_FILE_EN + hash_tbl_depth_reg_file_addr = 0x01a4 + fun_id * 8; + + ZXIC_COMM_UINT32_WRITE_BITS(hash_tbl03_depth_reg_file_dat, hash_tbl0_depth, HASH_TBL0_DEPTH_BT_START, HASH_TBL0_DEPTH_BT_WIDTH); + ZXIC_COMM_UINT32_WRITE_BITS(hash_tbl03_depth_reg_file_dat, hash_tbl1_depth, HASH_TBL1_DEPTH_BT_START, HASH_TBL1_DEPTH_BT_WIDTH); + ZXIC_COMM_UINT32_WRITE_BITS(hash_tbl03_depth_reg_file_dat, hash_tbl2_depth, HASH_TBL2_DEPTH_BT_START, HASH_TBL2_DEPTH_BT_WIDTH); + ZXIC_COMM_UINT32_WRITE_BITS(hash_tbl03_depth_reg_file_dat, hash_tbl3_depth, HASH_TBL3_DEPTH_BT_START, HASH_TBL3_DEPTH_BT_WIDTH); + + ZXIC_COMM_UINT32_WRITE_BITS(hash_tbl47_depth_reg_file_dat, hash_tbl4_depth, HASH_TBL4_DEPTH_BT_START, HASH_TBL4_DEPTH_BT_WIDTH); + ZXIC_COMM_UINT32_WRITE_BITS(hash_tbl47_depth_reg_file_dat, hash_tbl5_depth, HASH_TBL5_DEPTH_BT_START, HASH_TBL5_DEPTH_BT_WIDTH); + ZXIC_COMM_UINT32_WRITE_BITS(hash_tbl47_depth_reg_file_dat, hash_tbl6_depth, HASH_TBL6_DEPTH_BT_START, HASH_TBL6_DEPTH_BT_WIDTH); + ZXIC_COMM_UINT32_WRITE_BITS(hash_tbl47_depth_reg_file_dat, hash_tbl7_depth, HASH_TBL7_DEPTH_BT_START, HASH_TBL7_DEPTH_BT_WIDTH); + + rc = dpp_data_w2f(p_se_cfg->reg_base + hash_tbl_depth_reg_file_addr, &hash_tbl03_depth_reg_file_dat, FILE_TYPE_REG); + rc = dpp_data_w2f(p_se_cfg->reg_base + hash_tbl_depth_reg_file_addr + 4, &hash_tbl47_depth_reg_file_dat, FILE_TYPE_REG) + rc; + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_data_w2f"); +#endif + + rc = dpp_se_hash_tbl_depth_set(p_se_cfg->dev, + fun_id, + hash_tbl0_depth, + hash_tbl1_depth, + hash_tbl2_depth, + hash_tbl3_depth, + hash_tbl4_depth, + hash_tbl5_depth, + hash_tbl6_depth, + hash_tbl7_depth); + + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_se_hash_tbl_depth_set"); + + return DPP_OK; +} + +/***********************************************************/ +/** hash CRC多项式选择 +* @param fun_id hash引擎号 +* @param crc_sel +* +* @return +* @remark 无 +* @see +* @author tf @date 2016/01/28 +************************************************************/ +DPP_STATUS dpp_hash_tbl_crc_poly_write(DPP_SE_CFG *p_se_cfg, + ZXIC_UINT32 fun_id, + ZXIC_UINT32 bulk_id, + ZXIC_UINT32 crc_sel) +{ + DPP_STATUS rtn = DPP_OK; + + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 hash_tbl_crc_cfg_bt_start = 0; + ZXIC_UINT32 hash_tbl_crc_cfg_bt_width = 2; + DPP_SE4K_SE_ALG_HASH10_EXT_CRC_CFG_T hash01_ext_crc_cfg = {0}; + DPP_SE4K_SE_ALG_HASH32_EXT_CRC_CFG_T hash23_ext_crc_cfg = {0}; + +#if DPP_WRITE_FILE_EN + ZXIC_UINT32 ext_crc_cfg_file_reg = 0; + ZXIC_UINT32 ext_crc_cfg_file_reg_addr = 0; + DPP_HASH_FILE_REG_T *p_hash_file_reg = NULL; +#endif + + ZXIC_COMM_ASSERT(p_se_cfg); + + dev_id = p_se_cfg->dev_id; + + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, fun_id, DPP_HASH_ID_MIN, DPP_HASH_ID_MAX); + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, bulk_id, HASH_BULK_ID_MIN, HASH_BULK_ID_MAX); + + hash_tbl_crc_cfg_bt_start = bulk_id * 2; + + if (fun_id == 0 || fun_id == 1) + { + rtn = dpp_reg_read(p_se_cfg->dev, SE4K_SE_ALG_HASH10_EXT_CRC_CFGr, 0, 0, &hash01_ext_crc_cfg); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "dpp_reg_read"); + + if (fun_id == 0) + { + ZXIC_COMM_UINT32_WRITE_BITS(hash01_ext_crc_cfg.hash0_crc_cfg, crc_sel, hash_tbl_crc_cfg_bt_start, hash_tbl_crc_cfg_bt_width); + } + else + { + ZXIC_COMM_UINT32_WRITE_BITS(hash01_ext_crc_cfg.hash1_crc_cfg, crc_sel, hash_tbl_crc_cfg_bt_start, hash_tbl_crc_cfg_bt_width); + } + + rtn = dpp_reg_write(p_se_cfg->dev, SE4K_SE_ALG_HASH10_EXT_CRC_CFGr, 0, 0, &hash01_ext_crc_cfg); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "dpp_reg_write"); + + } + else + { + rtn = dpp_reg_read(p_se_cfg->dev, SE4K_SE_ALG_HASH32_EXT_CRC_CFGr, 0, 0, &hash23_ext_crc_cfg); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "dpp_reg_read"); + + if (fun_id == 2) + { + ZXIC_COMM_UINT32_WRITE_BITS(hash23_ext_crc_cfg.hash2_crc_cfg, crc_sel, hash_tbl_crc_cfg_bt_start, hash_tbl_crc_cfg_bt_width); + } + else + { + ZXIC_COMM_UINT32_WRITE_BITS(hash23_ext_crc_cfg.hash3_crc_cfg, crc_sel, hash_tbl_crc_cfg_bt_start, hash_tbl_crc_cfg_bt_width); + } + + rtn = dpp_reg_write(p_se_cfg->dev, SE4K_SE_ALG_HASH32_EXT_CRC_CFGr, 0, 0, &hash23_ext_crc_cfg); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "dpp_reg_write"); + } + +#if DPP_WRITE_FILE_EN + p_hash_file_reg = DPP_GET_HASH_FILE_REG(); + + if (fun_id == 0 || fun_id == 1) + { + ext_crc_cfg_file_reg_addr = 0x01cc; + + hash_tbl_crc_cfg_bt_start = fun_id * 16 + bulk_id * 2; + + ext_crc_cfg_file_reg = p_hash_file_reg->ext_crc_cfg_file_reg[0]; + ZXIC_COMM_UINT32_WRITE_BITS(ext_crc_cfg_file_reg, crc_sel, hash_tbl_crc_cfg_bt_start, hash_tbl_crc_cfg_bt_width); + + p_hash_file_reg->ext_crc_cfg_file_reg[0] = ext_crc_cfg_file_reg; + + rtn = dpp_data_w2f(p_se_cfg->reg_base + ext_crc_cfg_file_reg_addr, &p_hash_file_reg->ext_crc_cfg_file_reg[0], FILE_TYPE_REG); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "dpp_data_w2f"); + + } + else + { + ext_crc_cfg_file_reg_addr = 0x01d0; + + hash_tbl_crc_cfg_bt_start = (fun_id - 2) * 16 + bulk_id * 2; + + ext_crc_cfg_file_reg = p_hash_file_reg->ext_crc_cfg_file_reg[1]; + ZXIC_COMM_UINT32_WRITE_BITS(ext_crc_cfg_file_reg, crc_sel, hash_tbl_crc_cfg_bt_start, hash_tbl_crc_cfg_bt_width); + + p_hash_file_reg->ext_crc_cfg_file_reg[1] = ext_crc_cfg_file_reg; + + rtn = dpp_data_w2f(p_se_cfg->reg_base + ext_crc_cfg_file_reg_addr, &p_hash_file_reg->ext_crc_cfg_file_reg[1], FILE_TYPE_REG); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "dpp_data_w2f"); + } + +#endif + + return DPP_OK; +} + + +/***********************************************************/ +/** 清除hash引擎的所有hash表项(清除软件配置) +* @param p_se_cfg +* @param hash_id +* @param bulk_id +* +* @return +* @remark 无 +* @see +* @author cq @date 2023/08/18 +************************************************************/ +DPP_STATUS dpp_hash_soft_all_entry_delete(DPP_SE_CFG *p_se_cfg,ZXIC_UINT32 hash_id) +{ + ZXIC_UINT32 rc = 0; + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT8 table_id = 0; + ZXIC_UINT32 bulk_id = 0; + + D_NODE *p_node = NULL; + ZXIC_RB_TN *p_rb_tn = NULL; + ZXIC_RB_TN *p_rb_tn_rtn = NULL; + D_HEAD *p_head_hash_rb = NULL; + DPP_HASH_CFG *p_hash_cfg = NULL; + FUNC_ID_INFO *p_func_info = NULL; + DPP_HASH_RBKEY_INFO *p_rbkey = NULL; + DPP_HASH_RBKEY_INFO *p_rbkey_rtn = NULL; + SE_ITEM_CFG *p_item = NULL; + + ZXIC_COMM_CHECK_POINT(p_se_cfg); + ZXIC_COMM_CHECK_INDEX(hash_id, 0, HASH_FUNC_ID_NUM - 1); + + dev_id = p_se_cfg->dev_id; + + p_func_info = DPP_GET_FUN_INFO(p_se_cfg, hash_id); + DPP_SE_CHECK_FUN(p_func_info, hash_id, FUN_HASH); + + p_hash_cfg = (DPP_HASH_CFG *)p_func_info->fun_ptr; + p_head_hash_rb = &p_hash_cfg->hash_rb.tn_list; + + while (p_head_hash_rb->used) + { + p_node = p_head_hash_rb->p_next; + p_rb_tn = (ZXIC_RB_TN *)p_node->data; + p_rbkey = (DPP_HASH_RBKEY_INFO *)p_rb_tn->p_key; + table_id = DPP_GET_HASH_TBL_ID(p_rbkey->key); + bulk_id = ((table_id >> 2) & 0x7); + ZXIC_COMM_CHECK_DEV_INDEX(dev_id, bulk_id, 0, HASH_BULK_NUM - 1); + + rc = zxic_comm_rb_delete(&p_hash_cfg->hash_rb, p_rbkey, &p_rb_tn_rtn); + if (ZXIC_RBT_RC_SRHFAIL == rc) + { + p_hash_cfg->hash_stat.delete_fail++; + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "Error!there is not item in hash!\n"); + return DPP_HASH_RC_DEL_SRHFAIL; + } + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_rb_tn_rtn); + p_rbkey_rtn = (DPP_HASH_RBKEY_INFO *)(p_rb_tn_rtn->p_key); + p_item = p_rbkey_rtn->p_item_info; + + rc = zxic_comm_double_link_del(&(p_rbkey_rtn->entry_dn), &(p_item->item_list)); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "zxic_comm_double_link_del"); + p_item->wrt_mask &= ~(DPP_GET_HASH_ENTRY_MASK(p_rbkey_rtn->entry_size, p_rbkey_rtn->entry_pos)) & 0xF; + + if (0 == p_item->item_list.used) + { + if ((ITEM_DDR_256 == p_item->item_type) || (ITEM_DDR_512 == p_item->item_type)) + { + /* modify coverity by yinxh 2021.03.10*,以256bit为单位。暂不考虑512bit的情况*/ + ZXIC_COMM_CHECK_INDEX_UPPER(p_item->item_index, p_hash_cfg->p_bulk_ddr_info[bulk_id]->item_num); + p_hash_cfg->p_bulk_ddr_info[bulk_id]->p_item_array[p_item->item_index] = NULL; + ZXIC_COMM_FREE(p_item); + } + else + { + p_item->valid = 0; + } + } + + ZXIC_COMM_FREE(p_rbkey_rtn); + ZXIC_COMM_FREE(p_rb_tn_rtn); + p_hash_cfg->hash_stat.delete_ok++; + } + + return DPP_OK; +} + +/***********************************************************/ +/** 卸载软件上分配的hash资源(主要针对malloc释放) +* @param dev_id 设备号 +* @return +* @remark 无 +* @see +* @author cq @date 2023/12/20 +************************************************************/ +DPP_STATUS dpp_hash_soft_uninstall(ZXIC_UINT32 dev_id) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 hash_id = 0; + + ZXIC_COMM_CHECK_INDEX(dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + + for(hash_id=0;hash_idis_used) + { + ZXIC_COMM_TRACE_DEBUG("Error[0x%x], fun_id [%d] is not init\n!", DPP_SE_RC_FUN_INVALID, hash_id); + return DPP_OK; + } + + /*软件删除表项,删除红黑树节点*/ + rc = dpp_hash_soft_all_entry_delete(p_se_cfg,hash_id); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_hash_soft_all_entry_delete"); + + /*释放独占标识内存*/ + p_hash_cfg = (DPP_HASH_CFG *)p_func_info->fun_ptr; + for (i = 0; i < HASH_BULK_NUM; i++) + { + if ((&p_hash_cfg->hash_stat)->p_bulk_zcam_mono[i] != NULL) + { + ZXIC_COMM_FREE((&p_hash_cfg->hash_stat)->p_bulk_zcam_mono[i]); + (&p_hash_cfg->hash_stat)->p_bulk_zcam_mono[i] = NULL; + } + } + + /*释放DDR分配的所有内存*/ + p_head_ddr_cfg_rb = &p_hash_cfg->ddr_cfg_rb.tn_list; + while (p_head_ddr_cfg_rb->used) + { + p_node = p_head_ddr_cfg_rb->p_next; + + p_rb_tn = (ZXIC_RB_TN *)p_node->data; + p_rbkey = p_rb_tn->p_key; + + rc = zxic_comm_rb_delete(&p_hash_cfg->ddr_cfg_rb, p_rbkey, &p_rb_tn_rtn); + + if (ZXIC_RBT_RC_SRHFAIL == rc) + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "ddr_cfg_rb delete key is not exist, key: 0x"); + } + else + { + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "zxic_comm_rb_delete"); + } + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_rb_tn_rtn); + p_temp_rbkey = (HASH_DDR_CFG *)(p_rb_tn_rtn->p_key); + ZXIC_COMM_FREE(p_temp_rbkey->p_item_array); + p_temp_rbkey->p_item_array = NULL; + ZXIC_COMM_FREE(p_temp_rbkey); + ZXIC_COMM_FREE(p_rb_tn_rtn); + } + + rc = dpp_hash_zcam_resource_deinit(p_hash_cfg); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_hash_zcam_resource_deinit"); + + rc = dpp_se_fun_deinit(p_se_cfg, (hash_id & 0xff), FUN_HASH); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_se_fun_deinit"); + + ZXIC_COMM_MEMSET(g_tbl_id_info[dev_id][hash_id], 0, HASH_TBL_ID_NUM * sizeof(DPP_HASH_TBL_ID_INFO)); + + return DPP_OK; +} + +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/se/dpp_hash_crc.c b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/se/dpp_hash_crc.c new file mode 100755 index 0000000..5dc4ef1 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/se/dpp_hash_crc.c @@ -0,0 +1,381 @@ +#include "zxic_common.h" +#include "dpp_hash_crc.h" + +ZXIC_UINT16 g_crc16_rst[256][8] = { + {0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, + {0x1021, 0x8005, 0x3d65, 0xab47, 0x3453, 0x0357, 0x0589, 0xa02b}, + {0x2042, 0x800f, 0x7aca, 0xfdc9, 0x68a6, 0x06ae, 0x0b12, 0xe07d}, + {0x3063, 0x000a, 0x47af, 0x568e, 0x5cf5, 0x05f9, 0x0e9b, 0x4056}, + {0x4084, 0x801b, 0xf594, 0x50d5, 0xd14c, 0x0d5c, 0x1624, 0x60d1}, + {0x50a5, 0x001e, 0xc8f1, 0xfb92, 0xe51f, 0x0e0b, 0x13ad, 0xc0fa}, + {0x60c6, 0x0014, 0x8f5e, 0xad1c, 0xb9ea, 0x0bf2, 0x1d36, 0x80ac}, + {0x70e7, 0x8011, 0xb23b, 0x065b, 0x8db9, 0x08a5, 0x18bf, 0x2087}, + {0x8108, 0x8033, 0xd64d, 0xa1aa, 0x96cb, 0x1ab8, 0x2c48, 0xc1a2}, + {0x9129, 0x0036, 0xeb28, 0x0aed, 0xa298, 0x19ef, 0x29c1, 0x6189}, + {0xa14a, 0x003c, 0xac87, 0x5c63, 0xfe6d, 0x1c16, 0x275a, 0x21df}, + {0xb16b, 0x8039, 0x91e2, 0xf724, 0xca3e, 0x1f41, 0x22d3, 0x81f4}, + {0xc18c, 0x0028, 0x23d9, 0xf17f, 0x4787, 0x17e4, 0x3a6c, 0xa173}, + {0xd1ad, 0x802d, 0x1ebc, 0x5a38, 0x73d4, 0x14b3, 0x3fe5, 0x0158}, + {0xe1ce, 0x8027, 0x5913, 0x0cb6, 0x2f21, 0x114a, 0x317e, 0x410e}, + {0xf1ef, 0x0022, 0x6476, 0xa7f1, 0x1b72, 0x121d, 0x34f7, 0xe125}, + {0x1231, 0x8063, 0x91ff, 0xe813, 0x19c5, 0x3570, 0x5890, 0x236f}, + {0x0210, 0x0066, 0xac9a, 0x4354, 0x2d96, 0x3627, 0x5d19, 0x8344}, + {0x3273, 0x006c, 0xeb35, 0x15da, 0x7163, 0x33de, 0x5382, 0xc312}, + {0x2252, 0x8069, 0xd650, 0xbe9d, 0x4530, 0x3089, 0x560b, 0x6339}, + {0x52b5, 0x0078, 0x646b, 0xb8c6, 0xc889, 0x382c, 0x4eb4, 0x43be}, + {0x4294, 0x807d, 0x590e, 0x1381, 0xfcda, 0x3b7b, 0x4b3d, 0xe395}, + {0x72f7, 0x8077, 0x1ea1, 0x450f, 0xa02f, 0x3e82, 0x45a6, 0xa3c3}, + {0x62d6, 0x0072, 0x23c4, 0xee48, 0x947c, 0x3dd5, 0x402f, 0x03e8}, + {0x9339, 0x0050, 0x47b2, 0x49b9, 0x8f0e, 0x2fc8, 0x74d8, 0xe2cd}, + {0x8318, 0x8055, 0x7ad7, 0xe2fe, 0xbb5d, 0x2c9f, 0x7151, 0x42e6}, + {0xb37b, 0x805f, 0x3d78, 0xb470, 0xe7a8, 0x2966, 0x7fca, 0x02b0}, + {0xa35a, 0x005a, 0x001d, 0x1f37, 0xd3fb, 0x2a31, 0x7a43, 0xa29b}, + {0xd3bd, 0x804b, 0xb226, 0x196c, 0x5e42, 0x2294, 0x62fc, 0x821c}, + {0xc39c, 0x004e, 0x8f43, 0xb22b, 0x6a11, 0x21c3, 0x6775, 0x2237}, + {0xf3ff, 0x0044, 0xc8ec, 0xe4a5, 0x36e4, 0x243a, 0x69ee, 0x6261}, + {0xe3de, 0x8041, 0xf589, 0x4fe2, 0x02b7, 0x276d, 0x6c67, 0xc24a}, + {0x2462, 0x80c3, 0x1e9b, 0x7b61, 0x338a, 0x6ae0, 0xb120, 0x46de}, + {0x3443, 0x00c6, 0x23fe, 0xd026, 0x07d9, 0x69b7, 0xb4a9, 0xe6f5}, + {0x0420, 0x00cc, 0x6451, 0x86a8, 0x5b2c, 0x6c4e, 0xba32, 0xa6a3}, + {0x1401, 0x80c9, 0x5934, 0x2def, 0x6f7f, 0x6f19, 0xbfbb, 0x0688}, + {0x64e6, 0x00d8, 0xeb0f, 0x2bb4, 0xe2c6, 0x67bc, 0xa704, 0x260f}, + {0x74c7, 0x80dd, 0xd66a, 0x80f3, 0xd695, 0x64eb, 0xa28d, 0x8624}, + {0x44a4, 0x80d7, 0x91c5, 0xd67d, 0x8a60, 0x6112, 0xac16, 0xc672}, + {0x5485, 0x00d2, 0xaca0, 0x7d3a, 0xbe33, 0x6245, 0xa99f, 0x6659}, + {0xa56a, 0x00f0, 0xc8d6, 0xdacb, 0xa541, 0x7058, 0x9d68, 0x877c}, + {0xb54b, 0x80f5, 0xf5b3, 0x718c, 0x9112, 0x730f, 0x98e1, 0x2757}, + {0x8528, 0x80ff, 0xb21c, 0x2702, 0xcde7, 0x76f6, 0x967a, 0x6701}, + {0x9509, 0x00fa, 0x8f79, 0x8c45, 0xf9b4, 0x75a1, 0x93f3, 0xc72a}, + {0xe5ee, 0x80eb, 0x3d42, 0x8a1e, 0x740d, 0x7d04, 0x8b4c, 0xe7ad}, + {0xf5cf, 0x00ee, 0x0027, 0x2159, 0x405e, 0x7e53, 0x8ec5, 0x4786}, + {0xc5ac, 0x00e4, 0x4788, 0x77d7, 0x1cab, 0x7baa, 0x805e, 0x07d0}, + {0xd58d, 0x80e1, 0x7aed, 0xdc90, 0x28f8, 0x78fd, 0x85d7, 0xa7fb}, + {0x3653, 0x00a0, 0x8f64, 0x9372, 0x2a4f, 0x5f90, 0xe9b0, 0x65b1}, + {0x2672, 0x80a5, 0xb201, 0x3835, 0x1e1c, 0x5cc7, 0xec39, 0xc59a}, + {0x1611, 0x80af, 0xf5ae, 0x6ebb, 0x42e9, 0x593e, 0xe2a2, 0x85cc}, + {0x0630, 0x00aa, 0xc8cb, 0xc5fc, 0x76ba, 0x5a69, 0xe72b, 0x25e7}, + {0x76d7, 0x80bb, 0x7af0, 0xc3a7, 0xfb03, 0x52cc, 0xff94, 0x0560}, + {0x66f6, 0x00be, 0x4795, 0x68e0, 0xcf50, 0x519b, 0xfa1d, 0xa54b}, + {0x5695, 0x00b4, 0x003a, 0x3e6e, 0x93a5, 0x5462, 0xf486, 0xe51d}, + {0x46b4, 0x80b1, 0x3d5f, 0x9529, 0xa7f6, 0x5735, 0xf10f, 0x4536}, + {0xb75b, 0x8093, 0x5929, 0x32d8, 0xbc84, 0x4528, 0xc5f8, 0xa413}, + {0xa77a, 0x0096, 0x644c, 0x999f, 0x88d7, 0x467f, 0xc071, 0x0438}, + {0x9719, 0x009c, 0x23e3, 0xcf11, 0xd422, 0x4386, 0xceea, 0x446e}, + {0x8738, 0x8099, 0x1e86, 0x6456, 0xe071, 0x40d1, 0xcb63, 0xe445}, + {0xf7df, 0x0088, 0xacbd, 0x620d, 0x6dc8, 0x4874, 0xd3dc, 0xc4c2}, + {0xe7fe, 0x808d, 0x91d8, 0xc94a, 0x599b, 0x4b23, 0xd655, 0x64e9}, + {0xd79d, 0x8087, 0xd677, 0x9fc4, 0x056e, 0x4eda, 0xd8ce, 0x24bf}, + {0xc7bc, 0x0082, 0xeb12, 0x3483, 0x313d, 0x4d8d, 0xdd47, 0x8494}, + {0x48c4, 0x8183, 0x3d36, 0xf6c2, 0x6714, 0xd5c0, 0x67c9, 0x8dbc}, + {0x58e5, 0x0186, 0x0053, 0x5d85, 0x5347, 0xd697, 0x6240, 0x2d97}, + {0x6886, 0x018c, 0x47fc, 0x0b0b, 0x0fb2, 0xd36e, 0x6cdb, 0x6dc1}, + {0x78a7, 0x8189, 0x7a99, 0xa04c, 0x3be1, 0xd039, 0x6952, 0xcdea}, + {0x0840, 0x0198, 0xc8a2, 0xa617, 0xb658, 0xd89c, 0x71ed, 0xed6d}, + {0x1861, 0x819d, 0xf5c7, 0x0d50, 0x820b, 0xdbcb, 0x7464, 0x4d46}, + {0x2802, 0x8197, 0xb268, 0x5bde, 0xdefe, 0xde32, 0x7aff, 0x0d10}, + {0x3823, 0x0192, 0x8f0d, 0xf099, 0xeaad, 0xdd65, 0x7f76, 0xad3b}, + {0xc9cc, 0x01b0, 0xeb7b, 0x5768, 0xf1df, 0xcf78, 0x4b81, 0x4c1e}, + {0xd9ed, 0x81b5, 0xd61e, 0xfc2f, 0xc58c, 0xcc2f, 0x4e08, 0xec35}, + {0xe98e, 0x81bf, 0x91b1, 0xaaa1, 0x9979, 0xc9d6, 0x4093, 0xac63}, + {0xf9af, 0x01ba, 0xacd4, 0x01e6, 0xad2a, 0xca81, 0x451a, 0x0c48}, + {0x8948, 0x81ab, 0x1eef, 0x07bd, 0x2093, 0xc224, 0x5da5, 0x2ccf}, + {0x9969, 0x01ae, 0x238a, 0xacfa, 0x14c0, 0xc173, 0x582c, 0x8ce4}, + {0xa90a, 0x01a4, 0x6425, 0xfa74, 0x4835, 0xc48a, 0x56b7, 0xccb2}, + {0xb92b, 0x81a1, 0x5940, 0x5133, 0x7c66, 0xc7dd, 0x533e, 0x6c99}, + {0x5af5, 0x01e0, 0xacc9, 0x1ed1, 0x7ed1, 0xe0b0, 0x3f59, 0xaed3}, + {0x4ad4, 0x81e5, 0x91ac, 0xb596, 0x4a82, 0xe3e7, 0x3ad0, 0x0ef8}, + {0x7ab7, 0x81ef, 0xd603, 0xe318, 0x1677, 0xe61e, 0x344b, 0x4eae}, + {0x6a96, 0x01ea, 0xeb66, 0x485f, 0x2224, 0xe549, 0x31c2, 0xee85}, + {0x1a71, 0x81fb, 0x595d, 0x4e04, 0xaf9d, 0xedec, 0x297d, 0xce02}, + {0x0a50, 0x01fe, 0x6438, 0xe543, 0x9bce, 0xeebb, 0x2cf4, 0x6e29}, + {0x3a33, 0x01f4, 0x2397, 0xb3cd, 0xc73b, 0xeb42, 0x226f, 0x2e7f}, + {0x2a12, 0x81f1, 0x1ef2, 0x188a, 0xf368, 0xe815, 0x27e6, 0x8e54}, + {0xdbfd, 0x81d3, 0x7a84, 0xbf7b, 0xe81a, 0xfa08, 0x1311, 0x6f71}, + {0xcbdc, 0x01d6, 0x47e1, 0x143c, 0xdc49, 0xf95f, 0x1698, 0xcf5a}, + {0xfbbf, 0x01dc, 0x004e, 0x42b2, 0x80bc, 0xfca6, 0x1803, 0x8f0c}, + {0xeb9e, 0x81d9, 0x3d2b, 0xe9f5, 0xb4ef, 0xfff1, 0x1d8a, 0x2f27}, + {0x9b79, 0x01c8, 0x8f10, 0xefae, 0x3956, 0xf754, 0x0535, 0x0fa0}, + {0x8b58, 0x81cd, 0xb275, 0x44e9, 0x0d05, 0xf403, 0x00bc, 0xaf8b}, + {0xbb3b, 0x81c7, 0xf5da, 0x1267, 0x51f0, 0xf1fa, 0x0e27, 0xefdd}, + {0xab1a, 0x01c2, 0xc8bf, 0xb920, 0x65a3, 0xf2ad, 0x0bae, 0x4ff6}, + {0x6ca6, 0x0140, 0x23ad, 0x8da3, 0x549e, 0xbf20, 0xd6e9, 0xcb62}, + {0x7c87, 0x8145, 0x1ec8, 0x26e4, 0x60cd, 0xbc77, 0xd360, 0x6b49}, + {0x4ce4, 0x814f, 0x5967, 0x706a, 0x3c38, 0xb98e, 0xddfb, 0x2b1f}, + {0x5cc5, 0x014a, 0x6402, 0xdb2d, 0x086b, 0xbad9, 0xd872, 0x8b34}, + {0x2c22, 0x815b, 0xd639, 0xdd76, 0x85d2, 0xb27c, 0xc0cd, 0xabb3}, + {0x3c03, 0x015e, 0xeb5c, 0x7631, 0xb181, 0xb12b, 0xc544, 0x0b98}, + {0x0c60, 0x0154, 0xacf3, 0x20bf, 0xed74, 0xb4d2, 0xcbdf, 0x4bce}, + {0x1c41, 0x8151, 0x9196, 0x8bf8, 0xd927, 0xb785, 0xce56, 0xebe5}, + {0xedae, 0x8173, 0xf5e0, 0x2c09, 0xc255, 0xa598, 0xfaa1, 0x0ac0}, + {0xfd8f, 0x0176, 0xc885, 0x874e, 0xf606, 0xa6cf, 0xff28, 0xaaeb}, + {0xcdec, 0x017c, 0x8f2a, 0xd1c0, 0xaaf3, 0xa336, 0xf1b3, 0xeabd}, + {0xddcd, 0x8179, 0xb24f, 0x7a87, 0x9ea0, 0xa061, 0xf43a, 0x4a96}, + {0xad2a, 0x0168, 0x0074, 0x7cdc, 0x1319, 0xa8c4, 0xec85, 0x6a11}, + {0xbd0b, 0x816d, 0x3d11, 0xd79b, 0x274a, 0xab93, 0xe90c, 0xca3a}, + {0x8d68, 0x8167, 0x7abe, 0x8115, 0x7bbf, 0xae6a, 0xe797, 0x8a6c}, + {0x9d49, 0x0162, 0x47db, 0x2a52, 0x4fec, 0xad3d, 0xe21e, 0x2a47}, + {0x7e97, 0x8123, 0xb252, 0x65b0, 0x4d5b, 0x8a50, 0x8e79, 0xe80d}, + {0x6eb6, 0x0126, 0x8f37, 0xcef7, 0x7908, 0x8907, 0x8bf0, 0x4826}, + {0x5ed5, 0x012c, 0xc898, 0x9879, 0x25fd, 0x8cfe, 0x856b, 0x0870}, + {0x4ef4, 0x8129, 0xf5fd, 0x333e, 0x11ae, 0x8fa9, 0x80e2, 0xa85b}, + {0x3e13, 0x0138, 0x47c6, 0x3565, 0x9c17, 0x870c, 0x985d, 0x88dc}, + {0x2e32, 0x813d, 0x7aa3, 0x9e22, 0xa844, 0x845b, 0x9dd4, 0x28f7}, + {0x1e51, 0x8137, 0x3d0c, 0xc8ac, 0xf4b1, 0x81a2, 0x934f, 0x68a1}, + {0x0e70, 0x0132, 0x0069, 0x63eb, 0xc0e2, 0x82f5, 0x96c6, 0xc88a}, + {0xff9f, 0x0110, 0x641f, 0xc41a, 0xdb90, 0x90e8, 0xa231, 0x29af}, + {0xefbe, 0x8115, 0x597a, 0x6f5d, 0xefc3, 0x93bf, 0xa7b8, 0x8984}, + {0xdfdd, 0x811f, 0x1ed5, 0x39d3, 0xb336, 0x9646, 0xa923, 0xc9d2}, + {0xcffc, 0x011a, 0x23b0, 0x9294, 0x8765, 0x9511, 0xacaa, 0x69f9}, + {0xbf1b, 0x810b, 0x918b, 0x94cf, 0x0adc, 0x9db4, 0xb415, 0x497e}, + {0xaf3a, 0x010e, 0xacee, 0x3f88, 0x3e8f, 0x9ee3, 0xb19c, 0xe955}, + {0x9f59, 0x0104, 0xeb41, 0x6906, 0x627a, 0x9b1a, 0xbf07, 0xa903}, + {0x8f78, 0x8101, 0xd624, 0xc241, 0x5629, 0x984d, 0xba8e, 0x0928}, + {0x9188, 0x8303, 0x7a6c, 0x46c3, 0xce28, 0xa8d7, 0xcf92, 0xbb53}, + {0x81a9, 0x0306, 0x4709, 0xed84, 0xfa7b, 0xab80, 0xca1b, 0x1b78}, + {0xb1ca, 0x030c, 0x00a6, 0xbb0a, 0xa68e, 0xae79, 0xc480, 0x5b2e}, + {0xa1eb, 0x8309, 0x3dc3, 0x104d, 0x92dd, 0xad2e, 0xc109, 0xfb05}, + {0xd10c, 0x0318, 0x8ff8, 0x1616, 0x1f64, 0xa58b, 0xd9b6, 0xdb82}, + {0xc12d, 0x831d, 0xb29d, 0xbd51, 0x2b37, 0xa6dc, 0xdc3f, 0x7ba9}, + {0xf14e, 0x8317, 0xf532, 0xebdf, 0x77c2, 0xa325, 0xd2a4, 0x3bff}, + {0xe16f, 0x0312, 0xc857, 0x4098, 0x4391, 0xa072, 0xd72d, 0x9bd4}, + {0x1080, 0x0330, 0xac21, 0xe769, 0x58e3, 0xb26f, 0xe3da, 0x7af1}, + {0x00a1, 0x8335, 0x9144, 0x4c2e, 0x6cb0, 0xb138, 0xe653, 0xdada}, + {0x30c2, 0x833f, 0xd6eb, 0x1aa0, 0x3045, 0xb4c1, 0xe8c8, 0x9a8c}, + {0x20e3, 0x033a, 0xeb8e, 0xb1e7, 0x0416, 0xb796, 0xed41, 0x3aa7}, + {0x5004, 0x832b, 0x59b5, 0xb7bc, 0x89af, 0xbf33, 0xf5fe, 0x1a20}, + {0x4025, 0x032e, 0x64d0, 0x1cfb, 0xbdfc, 0xbc64, 0xf077, 0xba0b}, + {0x7046, 0x0324, 0x237f, 0x4a75, 0xe109, 0xb99d, 0xfeec, 0xfa5d}, + {0x6067, 0x8321, 0x1e1a, 0xe132, 0xd55a, 0xbaca, 0xfb65, 0x5a76}, + {0x83b9, 0x0360, 0xeb93, 0xaed0, 0xd7ed, 0x9da7, 0x9702, 0x983c}, + {0x9398, 0x8365, 0xd6f6, 0x0597, 0xe3be, 0x9ef0, 0x928b, 0x3817}, + {0xa3fb, 0x836f, 0x9159, 0x5319, 0xbf4b, 0x9b09, 0x9c10, 0x7841}, + {0xb3da, 0x036a, 0xac3c, 0xf85e, 0x8b18, 0x985e, 0x9999, 0xd86a}, + {0xc33d, 0x837b, 0x1e07, 0xfe05, 0x06a1, 0x90fb, 0x8126, 0xf8ed}, + {0xd31c, 0x037e, 0x2362, 0x5542, 0x32f2, 0x93ac, 0x84af, 0x58c6}, + {0xe37f, 0x0374, 0x64cd, 0x03cc, 0x6e07, 0x9655, 0x8a34, 0x1890}, + {0xf35e, 0x8371, 0x59a8, 0xa88b, 0x5a54, 0x9502, 0x8fbd, 0xb8bb}, + {0x02b1, 0x8353, 0x3dde, 0x0f7a, 0x4126, 0x871f, 0xbb4a, 0x599e}, + {0x1290, 0x0356, 0x00bb, 0xa43d, 0x7575, 0x8448, 0xbec3, 0xf9b5}, + {0x22f3, 0x035c, 0x4714, 0xf2b3, 0x2980, 0x81b1, 0xb058, 0xb9e3}, + {0x32d2, 0x8359, 0x7a71, 0x59f4, 0x1dd3, 0x82e6, 0xb5d1, 0x19c8}, + {0x4235, 0x0348, 0xc84a, 0x5faf, 0x906a, 0x8a43, 0xad6e, 0x394f}, + {0x5214, 0x834d, 0xf52f, 0xf4e8, 0xa439, 0x8914, 0xa8e7, 0x9964}, + {0x6277, 0x8347, 0xb280, 0xa266, 0xf8cc, 0x8ced, 0xa67c, 0xd932}, + {0x7256, 0x0342, 0x8fe5, 0x0921, 0xcc9f, 0x8fba, 0xa3f5, 0x7919}, + {0xb5ea, 0x03c0, 0x64f7, 0x3da2, 0xfda2, 0xc237, 0x7eb2, 0xfd8d}, + {0xa5cb, 0x83c5, 0x5992, 0x96e5, 0xc9f1, 0xc160, 0x7b3b, 0x5da6}, + {0x95a8, 0x83cf, 0x1e3d, 0xc06b, 0x9504, 0xc499, 0x75a0, 0x1df0}, + {0x8589, 0x03ca, 0x2358, 0x6b2c, 0xa157, 0xc7ce, 0x7029, 0xbddb}, + {0xf56e, 0x83db, 0x9163, 0x6d77, 0x2cee, 0xcf6b, 0x6896, 0x9d5c}, + {0xe54f, 0x03de, 0xac06, 0xc630, 0x18bd, 0xcc3c, 0x6d1f, 0x3d77}, + {0xd52c, 0x03d4, 0xeba9, 0x90be, 0x4448, 0xc9c5, 0x6384, 0x7d21}, + {0xc50d, 0x83d1, 0xd6cc, 0x3bf9, 0x701b, 0xca92, 0x660d, 0xdd0a}, + {0x34e2, 0x83f3, 0xb2ba, 0x9c08, 0x6b69, 0xd88f, 0x52fa, 0x3c2f}, + {0x24c3, 0x03f6, 0x8fdf, 0x374f, 0x5f3a, 0xdbd8, 0x5773, 0x9c04}, + {0x14a0, 0x03fc, 0xc870, 0x61c1, 0x03cf, 0xde21, 0x59e8, 0xdc52}, + {0x0481, 0x83f9, 0xf515, 0xca86, 0x379c, 0xdd76, 0x5c61, 0x7c79}, + {0x7466, 0x03e8, 0x472e, 0xccdd, 0xba25, 0xd5d3, 0x44de, 0x5cfe}, + {0x6447, 0x83ed, 0x7a4b, 0x679a, 0x8e76, 0xd684, 0x4157, 0xfcd5}, + {0x5424, 0x83e7, 0x3de4, 0x3114, 0xd283, 0xd37d, 0x4fcc, 0xbc83}, + {0x4405, 0x03e2, 0x0081, 0x9a53, 0xe6d0, 0xd02a, 0x4a45, 0x1ca8}, + {0xa7db, 0x83a3, 0xf508, 0xd5b1, 0xe467, 0xf747, 0x2622, 0xdee2}, + {0xb7fa, 0x03a6, 0xc86d, 0x7ef6, 0xd034, 0xf410, 0x23ab, 0x7ec9}, + {0x8799, 0x03ac, 0x8fc2, 0x2878, 0x8cc1, 0xf1e9, 0x2d30, 0x3e9f}, + {0x97b8, 0x83a9, 0xb2a7, 0x833f, 0xb892, 0xf2be, 0x28b9, 0x9eb4}, + {0xe75f, 0x03b8, 0x009c, 0x8564, 0x352b, 0xfa1b, 0x3006, 0xbe33}, + {0xf77e, 0x83bd, 0x3df9, 0x2e23, 0x0178, 0xf94c, 0x358f, 0x1e18}, + {0xc71d, 0x83b7, 0x7a56, 0x78ad, 0x5d8d, 0xfcb5, 0x3b14, 0x5e4e}, + {0xd73c, 0x03b2, 0x4733, 0xd3ea, 0x69de, 0xffe2, 0x3e9d, 0xfe65}, + {0x26d3, 0x0390, 0x2345, 0x741b, 0x72ac, 0xedff, 0x0a6a, 0x1f40}, + {0x36f2, 0x8395, 0x1e20, 0xdf5c, 0x46ff, 0xeea8, 0x0fe3, 0xbf6b}, + {0x0691, 0x839f, 0x598f, 0x89d2, 0x1a0a, 0xeb51, 0x0178, 0xff3d}, + {0x16b0, 0x039a, 0x64ea, 0x2295, 0x2e59, 0xe806, 0x04f1, 0x5f16}, + {0x6657, 0x838b, 0xd6d1, 0x24ce, 0xa3e0, 0xe0a3, 0x1c4e, 0x7f91}, + {0x7676, 0x038e, 0xebb4, 0x8f89, 0x97b3, 0xe3f4, 0x19c7, 0xdfba}, + {0x4615, 0x0384, 0xac1b, 0xd907, 0xcb46, 0xe60d, 0x175c, 0x9fec}, + {0x5634, 0x8381, 0x917e, 0x7240, 0xff15, 0xe55a, 0x12d5, 0x3fc7}, + {0xd94c, 0x0280, 0x475a, 0xb001, 0xa93c, 0x7d17, 0xa85b, 0x36ef}, + {0xc96d, 0x8285, 0x7a3f, 0x1b46, 0x9d6f, 0x7e40, 0xadd2, 0x96c4}, + {0xf90e, 0x828f, 0x3d90, 0x4dc8, 0xc19a, 0x7bb9, 0xa349, 0xd692}, + {0xe92f, 0x028a, 0x00f5, 0xe68f, 0xf5c9, 0x78ee, 0xa6c0, 0x76b9}, + {0x99c8, 0x829b, 0xb2ce, 0xe0d4, 0x7870, 0x704b, 0xbe7f, 0x563e}, + {0x89e9, 0x029e, 0x8fab, 0x4b93, 0x4c23, 0x731c, 0xbbf6, 0xf615}, + {0xb98a, 0x0294, 0xc804, 0x1d1d, 0x10d6, 0x76e5, 0xb56d, 0xb643}, + {0xa9ab, 0x8291, 0xf561, 0xb65a, 0x2485, 0x75b2, 0xb0e4, 0x1668}, + {0x5844, 0x82b3, 0x9117, 0x11ab, 0x3ff7, 0x67af, 0x8413, 0xf74d}, + {0x4865, 0x02b6, 0xac72, 0xbaec, 0x0ba4, 0x64f8, 0x819a, 0x5766}, + {0x7806, 0x02bc, 0xebdd, 0xec62, 0x5751, 0x6101, 0x8f01, 0x1730}, + {0x6827, 0x82b9, 0xd6b8, 0x4725, 0x6302, 0x6256, 0x8a88, 0xb71b}, + {0x18c0, 0x02a8, 0x6483, 0x417e, 0xeebb, 0x6af3, 0x9237, 0x979c}, + {0x08e1, 0x82ad, 0x59e6, 0xea39, 0xdae8, 0x69a4, 0x97be, 0x37b7}, + {0x3882, 0x82a7, 0x1e49, 0xbcb7, 0x861d, 0x6c5d, 0x9925, 0x77e1}, + {0x28a3, 0x02a2, 0x232c, 0x17f0, 0xb24e, 0x6f0a, 0x9cac, 0xd7ca}, + {0xcb7d, 0x82e3, 0xd6a5, 0x5812, 0xb0f9, 0x4867, 0xf0cb, 0x1580}, + {0xdb5c, 0x02e6, 0xebc0, 0xf355, 0x84aa, 0x4b30, 0xf542, 0xb5ab}, + {0xeb3f, 0x02ec, 0xac6f, 0xa5db, 0xd85f, 0x4ec9, 0xfbd9, 0xf5fd}, + {0xfb1e, 0x82e9, 0x910a, 0x0e9c, 0xec0c, 0x4d9e, 0xfe50, 0x55d6}, + {0x8bf9, 0x02f8, 0x2331, 0x08c7, 0x61b5, 0x453b, 0xe6ef, 0x7551}, + {0x9bd8, 0x82fd, 0x1e54, 0xa380, 0x55e6, 0x466c, 0xe366, 0xd57a}, + {0xabbb, 0x82f7, 0x59fb, 0xf50e, 0x0913, 0x4395, 0xedfd, 0x952c}, + {0xbb9a, 0x02f2, 0x649e, 0x5e49, 0x3d40, 0x40c2, 0xe874, 0x3507}, + {0x4a75, 0x02d0, 0x00e8, 0xf9b8, 0x2632, 0x52df, 0xdc83, 0xd422}, + {0x5a54, 0x82d5, 0x3d8d, 0x52ff, 0x1261, 0x5188, 0xd90a, 0x7409}, + {0x6a37, 0x82df, 0x7a22, 0x0471, 0x4e94, 0x5471, 0xd791, 0x345f}, + {0x7a16, 0x02da, 0x4747, 0xaf36, 0x7ac7, 0x5726, 0xd218, 0x9474}, + {0x0af1, 0x82cb, 0xf57c, 0xa96d, 0xf77e, 0x5f83, 0xcaa7, 0xb4f3}, + {0x1ad0, 0x02ce, 0xc819, 0x022a, 0xc32d, 0x5cd4, 0xcf2e, 0x14d8}, + {0x2ab3, 0x02c4, 0x8fb6, 0x54a4, 0x9fd8, 0x592d, 0xc1b5, 0x548e}, + {0x3a92, 0x82c1, 0xb2d3, 0xffe3, 0xab8b, 0x5a7a, 0xc43c, 0xf4a5}, + {0xfd2e, 0x8243, 0x59c1, 0xcb60, 0x9ab6, 0x17f7, 0x197b, 0x7031}, + {0xed0f, 0x0246, 0x64a4, 0x6027, 0xaee5, 0x14a0, 0x1cf2, 0xd01a}, + {0xdd6c, 0x024c, 0x230b, 0x36a9, 0xf210, 0x1159, 0x1269, 0x904c}, + {0xcd4d, 0x8249, 0x1e6e, 0x9dee, 0xc643, 0x120e, 0x17e0, 0x3067}, + {0xbdaa, 0x0258, 0xac55, 0x9bb5, 0x4bfa, 0x1aab, 0x0f5f, 0x10e0}, + {0xad8b, 0x825d, 0x9130, 0x30f2, 0x7fa9, 0x19fc, 0x0ad6, 0xb0cb}, + {0x9de8, 0x8257, 0xd69f, 0x667c, 0x235c, 0x1c05, 0x044d, 0xf09d}, + {0x8dc9, 0x0252, 0xebfa, 0xcd3b, 0x170f, 0x1f52, 0x01c4, 0x50b6}, + {0x7c26, 0x0270, 0x8f8c, 0x6aca, 0x0c7d, 0x0d4f, 0x3533, 0xb193}, + {0x6c07, 0x8275, 0xb2e9, 0xc18d, 0x382e, 0x0e18, 0x30ba, 0x11b8}, + {0x5c64, 0x827f, 0xf546, 0x9703, 0x64db, 0x0be1, 0x3e21, 0x51ee}, + {0x4c45, 0x027a, 0xc823, 0x3c44, 0x5088, 0x08b6, 0x3ba8, 0xf1c5}, + {0x3ca2, 0x826b, 0x7a18, 0x3a1f, 0xdd31, 0x0013, 0x2317, 0xd142}, + {0x2c83, 0x026e, 0x477d, 0x9158, 0xe962, 0x0344, 0x269e, 0x7169}, + {0x1ce0, 0x0264, 0x00d2, 0xc7d6, 0xb597, 0x06bd, 0x2805, 0x313f}, + {0x0cc1, 0x8261, 0x3db7, 0x6c91, 0x81c4, 0x05ea, 0x2d8c, 0x9114}, + {0xef1f, 0x0220, 0xc83e, 0x2373, 0x8373, 0x2287, 0x41eb, 0x535e}, + {0xff3e, 0x8225, 0xf55b, 0x8834, 0xb720, 0x21d0, 0x4462, 0xf375}, + {0xcf5d, 0x822f, 0xb2f4, 0xdeba, 0xebd5, 0x2429, 0x4af9, 0xb323}, + {0xdf7c, 0x022a, 0x8f91, 0x75fd, 0xdf86, 0x277e, 0x4f70, 0x1308}, + {0xaf9b, 0x823b, 0x3daa, 0x73a6, 0x523f, 0x2fdb, 0x57cf, 0x338f}, + {0xbfba, 0x023e, 0x00cf, 0xd8e1, 0x666c, 0x2c8c, 0x5246, 0x93a4}, + {0x8fd9, 0x0234, 0x4760, 0x8e6f, 0x3a99, 0x2975, 0x5cdd, 0xd3f2}, + {0x9ff8, 0x8231, 0x7a05, 0x2528, 0x0eca, 0x2a22, 0x5954, 0x73d9}, + {0x6e17, 0x8213, 0x1e73, 0x82d9, 0x15b8, 0x383f, 0x6da3, 0x92fc}, + {0x7e36, 0x0216, 0x2316, 0x299e, 0x21eb, 0x3b68, 0x682a, 0x32d7}, + {0x4e55, 0x021c, 0x64b9, 0x7f10, 0x7d1e, 0x3e91, 0x66b1, 0x7281}, + {0x5e74, 0x8219, 0x59dc, 0xd457, 0x494d, 0x3dc6, 0x6338, 0xd2aa}, + {0x2e93, 0x0208, 0xebe7, 0xd20c, 0xc4f4, 0x3563, 0x7b87, 0xf22d}, + {0x3eb2, 0x820d, 0xd682, 0x794b, 0xf0a7, 0x3634, 0x7e0e, 0x5206}, + {0x0ed1, 0x8207, 0x912d, 0x2fc5, 0xac52, 0x33cd, 0x7095, 0x1250}, + {0x1ef0, 0x0202, 0xac48, 0x8482, 0x9801, 0x309a, 0x751c, 0xb27b}, +}; + +ZXIC_UINT32 dpp_crc32_calc(ZXIC_UINT8 *pInputKey, ZXIC_UINT32 dwByteNum, ZXIC_UINT32 dwCrcPoly) +{ + ZXIC_UINT32 dwResult = 0; + ZXIC_UINT32 dwDataType = 0; + + ZXIC_UINT32 i = 0; + ZXIC_UINT32 j = 0; + + while (i < dwByteNum) + { + dwDataType = (ZXIC_UINT32)((dwResult & 0xff000000) ^ (pInputKey[i] << 24)); + for (j = 0; j < 8; j++) + { + if (dwDataType & 0x80000000) + { + dwDataType <<= 1; + dwDataType ^= dwCrcPoly; + } + else + { + dwDataType <<= 1; + } + } + dwResult <<= 8; + dwResult ^= dwDataType; + + i++; + } + + return dwResult; +} + +ZXIC_UINT16 dpp_crc16_calc(ZXIC_UINT8 *pInputKey, ZXIC_UINT32 dwByteNum, ZXIC_UINT16 dwCrcPoly) +{ + ZXIC_UINT16 dwResult = 0; + ZXIC_UINT16 dwDataType = 0; + + ZXIC_UINT32 i = 0; + ZXIC_UINT32 j = 0; + + while (i < dwByteNum) + { + dwDataType = (ZXIC_UINT16)(((dwResult & 0xff00) ^ (pInputKey[i] << 8)) & 0xFFFF); + for (j = 0; j < 8; j++) + { + if (dwDataType & 0x8000) + { + dwDataType <<= 1; + dwDataType ^= dwCrcPoly; + } + else + { + dwDataType <<= 1; + } + } + dwResult <<= 8; + dwResult ^= dwDataType; + + i++; + } + + return dwResult; +} + +ZXIC_UINT16 dpp_crc16_get_idx(ZXIC_UINT16 crc_val) +{ + switch (crc_val) + { + case 0x1021: + return 0; + case 0x8005: + return 1; + case 0x3d65: + return 2; + case 0xab47: + return 3; + case 0x3453: + return 4; + case 0x0357: + return 5; + case 0x0589: + return 6; + case 0xa02b: + return 7; + default: + return 0xFFFF; + } +} + +//查表法 +ZXIC_UINT16 dpp_crc16_table_lookup(ZXIC_UINT8 *pInputKey, ZXIC_UINT32 dwByteNum, ZXIC_UINT16 dwCrcPoly) +{ + ZXIC_UINT16 dwResult = 0; + ZXIC_UINT16 dwDataType = 0; + ZXIC_UINT16 tmp_index = 0; + ZXIC_UINT32 i = 0; + + ZXIC_UINT32 crc_idx = dpp_crc16_get_idx(dwCrcPoly); + + ZXIC_COMM_CHECK_INDEX(crc_idx, 0, 7); + + while (i < dwByteNum) + { + dwDataType = ((dwResult & 0xff00) ^ (pInputKey[i] << 8)) & 0xFFFF; + + tmp_index = dwDataType >> 8; + tmp_index = tmp_index & 0xff; + ZXIC_COMM_CHECK_INDEX(tmp_index, 0, 255); + ZXIC_COMM_CHECK_INDEX(crc_idx, 0, 7); + dwDataType = g_crc16_rst[tmp_index][crc_idx]; + + dwResult <<= 8; + dwResult ^= dwDataType; + + i++; + } + + return dwResult; +} diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/se/dpp_se_cfg.c b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/se/dpp_se_cfg.c new file mode 100755 index 0000000..a9dd43b --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/se/dpp_se_cfg.c @@ -0,0 +1,291 @@ +/***************************************************************************** + * 版权所有 (C)2001-2015, 深圳市中兴通讯股份有限公司。 + * + * 文件名称： dpp_se_cfg.c + * 文件标识： SE配置部分源文件 + * 内容摘要： + * 其它说明： + * 当前版本： + * 作 者： ChenWei10088471 + * 完成日期： + * 当前责任人-1： + * 当前责任人-2： + * + * DEPARTMENT : ASIC_FPGA_R&D_Dept + * MANUAL_PERCENT : 100% + *****************************************************************************/ + +#include "zxic_common.h" +#include "dpp_dev.h" +#include "dpp_module.h" +#include "dpp_se.h" +#include "dpp_se_cfg.h" +#include "dpp_hash.h" +#include "dpp_acl.h" + +DPP_SE_CFG *dpp_se_cfg[DPP_DEV_CHANNEL_MAX] = {0}; + +static ZXIC_UINT16 g_lpm_crc[SE_ZBLK_NUM] = { + 0x1021, 0x8005, 0x3D65, 0xab47, 0x3453, 0x0357, 0x0589, 0xa02b, + 0x1021, 0x8005, 0x3D65, 0xab47, 0x3453, 0x0357, 0x0589, 0xa02b, + 0x1021, 0x8005, 0x3D65, 0xab47, 0x3453, 0x0357, 0x0589, 0xa02b, + 0x1021, 0x8005, 0x3D65, 0xab47, 0x3453, 0x0357, 0x0589, 0xa02b +}; + +#if DPP_WRITE_FILE_EN +static ZXIC_CHAR *prefix_str = "./dpp_se_data"; +#endif + +/***********************************************************/ +/** 配置g_se_cfg 的值 +* @param p_se_cfg 算法模块公共管理数据结构指针 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author yxh @date 2019/02/22 +************************************************************/ +DPP_STATUS dpp_se_cfg_set(ZXIC_UINT32 dev_id, DPP_SE_CFG *p_se_cfg) +{ + ZXIC_UINT64 se_cfg_ptr = 0; + + ZXIC_COMM_CHECK_INDEX(dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_POINT(p_se_cfg); + + dpp_se_cfg[dev_id] = p_se_cfg; + ZXIC_COMM_CHECK_POINT(dpp_se_cfg[dev_id]); + + se_cfg_ptr = ZXIC_COMM_PTR_TO_VAL(p_se_cfg); + ZXIC_COMM_TRACE_INFO("p_se_cfg address 0x%llx.\n", se_cfg_ptr); + + return DPP_OK; +} + +/***********************************************************/ +/** 获取g_se_cfg 的值 +* @param p_se_cfg 算法模块公共管理数据结构指针 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author yxh @date 2019/02/22 +************************************************************/ +DPP_STATUS dpp_se_cfg_get(ZXIC_UINT32 dev_id, DPP_SE_CFG **p_se_cfg) +{ + ZXIC_COMM_CHECK_INDEX(dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + + *p_se_cfg = dpp_se_cfg[dev_id]; + ZXIC_COMM_CHECK_POINT(*p_se_cfg); + + ZXIC_COMM_TRACE_DEBUG("p_se_cfg address %p.\n", (*p_se_cfg)); + + return DPP_OK; +} + +DPP_STATUS dpp_se_init(DPP_DEV_T *dev, DPP_SE_CFG *p_se_cfg) +{ + ZXIC_UINT32 i = 0; + ZXIC_UINT32 j = 0; + ZXIC_UINT32 dev_id = 0; + +#if LPM_THREAD_HW_WRITE_EN + ZXIC_UINT32 rtn = 0; +#endif + + SE_ZBLK_CFG *p_zblk_cfg = NULL; + SE_ZCELL_CFG *p_zcell_cfg = NULL; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_POINT(p_se_cfg); + + // dev_id = ZXIC_COMM_PTR_TO_VAL(p_se_cfg->p_client) & 0xFFFFFFFF; + dev_id = DEV_ID(dev); + ZXIC_COMM_CHECK_INDEX_UPPER(dev_id,DPP_DEV_CHANNEL_MAX - 1); + + ZXIC_COMM_MEMSET(p_se_cfg, 0, sizeof(DPP_SE_CFG)); + + p_se_cfg->dev = dev; + p_se_cfg->dev_id = dev_id; + dpp_se_cfg_set(p_se_cfg->dev_id, p_se_cfg); + + //p_se_cfg->p_as_rslt_wrt_fun = dpp_se_lpm_as_rslt_write; + p_se_cfg->p_client = ZXIC_COMM_VAL_TO_PTR(dev_id); + + for (i = 0; i < SE_ZBLK_NUM; i++) + { + p_zblk_cfg = DPP_SE_GET_ZBLK_CFG(p_se_cfg, i); + + p_zblk_cfg->zblk_idx = i; + p_zblk_cfg->is_used = 0; + p_zblk_cfg->hash_arg = g_lpm_crc[i]; + p_zblk_cfg->zcell_bm = 0; + INIT_D_NODE(&p_zblk_cfg->zblk_dn, p_zblk_cfg); + + for (j = 0; j < SE_ZCELL_NUM; j++) + { + p_zcell_cfg = &p_zblk_cfg->zcell_info[j]; + + p_zcell_cfg->zcell_idx = (i << 2) + j; + p_zcell_cfg->item_used = 0; + p_zcell_cfg->mask_len = 0; + + INIT_D_NODE(&p_zcell_cfg->zcell_dn, p_zcell_cfg); + + p_zcell_cfg->zcell_avl.p_key = p_zcell_cfg; + } + } + +#if DPP_WRITE_FILE_EN +/* icm_trace_set_log_dir(prefix_str);*/ + dpp_se_file_mng_init(); +#else + +#endif + +#if LPM_THREAD_HW_WRITE_EN + for (i = 0; i < MAX_ITEM_INFO_BAK_NUM; i++) + { + rtn = zxic_comm_mutex_create(&(p_se_cfg->cache_index_mutex[i])); + ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_mutex_create"); + } + + rtn = zxic_comm_liststack_creat(MAX_ITEM_INFO_BAK_NUM, &p_se_cfg->p_thread_liststack_mng); + ZXIC_COMM_CHECK_RC(rtn,"zxic_comm_liststack_creat"); +#endif + + return DPP_OK; +} + +/***********************************************************/ +/** 初始化算法管理数据结构用户自定义的数据指针，当前仅用于传入设备号的值 +* @param p_se_cfg 算法管理数据结构指针 +* @param p_client 用户自定义的数据指针 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author 王春雷 @date 2015/05/20 +************************************************************/ +DPP_STATUS dpp_se_client_init(DPP_SE_CFG *p_se_cfg, ZXIC_VOID *p_client) +{ + ZXIC_COMM_CHECK_POINT(p_se_cfg); + + p_se_cfg->p_client = p_client; + p_se_cfg->reg_base = SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR; /* 算法模块芯片内相对基地址 */ + // p_se_cfg->p_write32_fun = dpp_se_reg_write32; + // p_se_cfg->p_read32_fun = dpp_se_reg_read32; + + return DPP_OK; +} + +DPP_STATUS dpp_se_fun_init(DPP_SE_CFG *p_se_cfg, + ZXIC_UINT8 id, + ZXIC_UINT32 fun_type) +{ + FUNC_ID_INFO *p_fun_info = NULL; + + ZXIC_COMM_CHECK_POINT(p_se_cfg); + ZXIC_COMM_CHECK_INDEX(id, 0, MAX_FUN_NUM - 1); + ZXIC_COMM_CHECK_INDEX(fun_type, FUN_HASH, FUN_MAX - 1); + + p_fun_info = DPP_GET_FUN_INFO(p_se_cfg, id); + + if (p_fun_info->is_used) + { + ZXIC_COMM_TRACE_ERROR("\n Error[0x%x], fun_id [%d] is already used!", DPP_SE_RC_FUN_INVALID, id); + return DPP_SE_RC_FUN_INVALID; + } + + p_fun_info->fun_id = id; + p_fun_info->is_used = 1; + + switch (fun_type) + { + case (FUN_LPM): + { + /* + p_fun_info->fun_type = FUN_LPM; + p_fun_info->fun_ptr = ZXIC_COMM_MALLOC(sizeof(DPP_ROUTE_CFG)); + ZXIC_COMM_CHECK_POINT(p_fun_info->fun_ptr); + ZXIC_COMM_MEMSET(p_fun_info->fun_ptr,0,sizeof(DPP_ROUTE_CFG)); + + ((DPP_ROUTE_CFG*)(p_fun_info->fun_ptr))->p_se_cfg = p_se_cfg; + */ + + //dpp_func_lpm_create(p_se_cfg, id); + + } + break; + + case (FUN_HASH): + { + p_fun_info->fun_type = FUN_HASH; + p_fun_info->fun_ptr = ZXIC_COMM_MALLOC(sizeof(DPP_HASH_CFG)); + ZXIC_COMM_CHECK_POINT(p_fun_info->fun_ptr); + ZXIC_COMM_MEMSET(p_fun_info->fun_ptr, 0, sizeof(DPP_HASH_CFG)); + ((DPP_HASH_CFG *)(p_fun_info->fun_ptr))->p_se_info = p_se_cfg; + } + break; + + default: + { + ZXIC_COMM_TRACE_ERROR("\n Error,unrecgnized fun_type[ %d] ", fun_type); + ZXIC_COMM_ASSERT(0); + return DPP_SE_RC_BASE; + } + break; + } + + return DPP_OK; +} + +DPP_STATUS dpp_se_fun_deinit(DPP_SE_CFG *p_se_cfg, + ZXIC_UINT8 id, + ZXIC_UINT32 fun_type) +{ + FUNC_ID_INFO *p_fun_info = NULL; + + ZXIC_COMM_CHECK_POINT(p_se_cfg); + ZXIC_COMM_CHECK_INDEX(id, 0, MAX_FUN_NUM - 1); + ZXIC_COMM_CHECK_INDEX(fun_type, FUN_HASH, FUN_MAX - 1); + + p_fun_info = DPP_GET_FUN_INFO(p_se_cfg, id); + + if (0 == p_fun_info->is_used) + { + ZXIC_COMM_TRACE_ERROR("\n Error[0x%x], fun_id [%d] is already deinit!", DPP_SE_RC_FUN_INVALID, id); + return DPP_SE_RC_FUN_INVALID; + } + + switch (fun_type) + { + case (FUN_LPM): + { +/* dpp_func_lpm_destory(p_se_cfg, id);*/ + } + break; + + case (FUN_HASH): + { + if (p_fun_info->fun_ptr) + { + ZXIC_COMM_FREE(p_fun_info->fun_ptr); + p_fun_info->fun_ptr = NULL; + } + } + break; + + default: + { + ZXIC_COMM_TRACE_ERROR("\n Error,unrecgnized fun_type[ %d] ", fun_type); + ZXIC_COMM_ASSERT(0); + return DPP_SE_RC_BASE; + } + break; + } + + p_fun_info->fun_id = id; + p_fun_info->is_used = 0; + + return DPP_OK; +} diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/tm/Kbuild.include b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/tm/Kbuild.include new file mode 100644 index 0000000..7d9cc41 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/tm/Kbuild.include @@ -0,0 +1,2 @@ +cur_dir := en_np/sdk/source/dev/module/tm/ +src_files += $(addprefix $(cur_dir),$(notdir $(wildcard $(dinghai_root)/$(cur_dir)*.c))) \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/tm/dpp_tm.c b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/tm/dpp_tm.c new file mode 100755 index 0000000..c64a7e2 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/tm/dpp_tm.c @@ -0,0 +1,21525 @@ +/************************************************************** +* 版权所有 (C)2013-2015,深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_tm.c +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : djf +* 完成日期 : 2014/02/17 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ + +/****************************************************************************** + * START: 头文件 * + *****************************************************************************/ +#include "zxic_common.h" +#include "dpp_type_api.h" +#include "dpp_reg_api.h" +#include "dpp_reg_info.h" +#include "dpp_etm_reg.h" +#include "dpp_module.h" +#include "dpp_tm_api.h" +//#include "dpp_tm_diag.h" +#include "dpp_tm.h" +#include "dpp_dev.h" + +/****************************************************************************** + * END: 头文件 * + *****************************************************************************/ + + +/****************************************************************************** + * START: 常量定义 * + *****************************************************************************/ + +DPP_TM_SHAPE_PARA_TABLE g_dpp_etm_shape_para_table[DPP_PCIE_SLOT_MAX][DPP_ETM_SHAP_TABEL_ID_MAX][DPP_TM_SHAP_MAP_ID_MAX] = {{{{0}}}}; /* coverity告警修改：单一变量不能超过10000字节 */ +DPP_TM_SHAPE_PARA_TABLE g_dpp_ftm_shape_para_table[DPP_DEV_CHANNEL_MAX][DPP_FTM_SHAP_TABEL_ID_MAX][DPP_TM_SHAP_MAP_ID_MAX] = {{{{0}}}}; +DPP_ETM_QMU_INIT_PARA g_dpp_etm_qmu_qlist_para = {0}; +DPP_FTM_QMU_INIT_PARA g_dpp_ftm_qmu_qlist_para = {0}; + +/* 全局变量读写互斥锁 */ +ZXIC_MUTEX_T g_dpp_tm_global_var_rw_mutex; +ZXIC_UINT32 g_dpp_tm_global_var_rw_mutex_flag = 0; +// static ZXIC_UINT32 g_qmu_init_case_no = 0; + + +/***********************************************************/ +/** 全局变量读写互斥锁初始化 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author yjd @date 2015/07/23 +************************************************************/ +DPP_STATUS dpp_tm_global_var_mutex_init(ZXIC_VOID) +{ + DPP_STATUS rc = DPP_OK; + + if (!g_dpp_tm_global_var_rw_mutex_flag) + { + rc = zxic_comm_mutex_create(&g_dpp_tm_global_var_rw_mutex); + ZXIC_COMM_CHECK_RC(rc, "zxic_comm_mutex_create"); + + g_dpp_tm_global_var_rw_mutex_flag = 1; + } + + return DPP_OK; +} + + +/****************************************************************************** + * END: 常量定义 * + *****************************************************************************/ + +#if ZXIC_REAL("TM_REG") +#if 0 +/***********************************************************/ +/** 写TM寄存器 +* @param module_id 区分TM子模块 +* @param addr 基于子模块的地址 +* @param data 写入的数据 +* +* @return +* @remark 无 +* @see +* @author yjd @date 2015/07/26 +************************************************************/ +DPP_STATUS dpp_tm_wr_reg(ZXIC_UINT32 dev_id, ZXIC_UINT32 module_id, ZXIC_UINT32 addr, ZXIC_UINT32 data) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 wr_data = 0; + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, module_id, MODULE_TM_CFGMT, MODULE_TM_MAX - 1); + + wr_data = data; + rc = dpp_tm_write(dev_id, module_id, addr, &wr_data); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_write"); + + return DPP_OK; +} + +/***********************************************************/ +/** 读TM寄存器 +* @param tm_type 0-ETM,1-FTM +* @param module_id 区分TM子模块 +* @param addr 基于子模块的地址 +* @return +* @remark 无 +* @see +* @author yjd @date 2015/07/26 +************************************************************/ +DPP_STATUS dpp_tm_rd_reg(ZXIC_UINT32 dev_id, ZXIC_UINT32 module_id, ZXIC_UINT32 addr) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 rd_data = 0; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, module_id, MODULE_TM_CFGMT, MODULE_TM_MAX - 1); + + rc = dpp_tm_read(dev_id, module_id, addr, &rd_data); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_read"); + + ZXIC_COMM_PRINT("[0x%08x] 0x%08x \n", addr, rd_data); + + return DPP_OK; +} + +/***********************************************************/ +/** 写一片连续的TM寄存器 +* @param module_id 区分TM子模块 +* @param first_addr 起始寄存器的地址 +* @param reg_num 总共读取的寄存器数 +* +* @return +* @remark 无 +* @see +* @author yjd @date 2015/07/26 +************************************************************/ +DPP_STATUS dpp_tm_wr_more_reg(ZXIC_UINT32 dev_id, ZXIC_UINT32 module_id, ZXIC_UINT32 first_addr, ZXIC_UINT32 first_data, ZXIC_UINT32 data_step, ZXIC_UINT32 reg_num) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 addr = 0; + ZXIC_UINT32 data = 0; + ZXIC_UINT32 i = 0; + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, module_id, MODULE_TM_CFGMT, MODULE_TM_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(dev_id, first_addr , reg_num); + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, data_step , reg_num); + ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(dev_id, first_data , (data_step * reg_num)); + + for (i = 0; i < reg_num; i++) + { + addr = first_addr + i; + data = first_data + (data_step * i); + rc = dpp_tm_wr_reg(dev_id, module_id, addr, data); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_wr_reg"); + } + + return DPP_OK; +} + +/***********************************************************/ +/** 读一片连续的TM寄存器 +* @param module_id 区分TM子模块 +* @param first_addr 起始寄存器的地址 +* @param reg_num 总共读取的寄存器数 +* +* @return +* @remark 无 +* @see +* @author yjd @date 2017/07/26 +************************************************************/ +DPP_STATUS dpp_tm_rd_more_reg(ZXIC_UINT32 dev_id, ZXIC_UINT32 module_id, ZXIC_UINT32 first_addr, ZXIC_UINT32 reg_num) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 addr = 0; + ZXIC_UINT32 i = 0; + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, module_id, MODULE_TM_CFGMT, MODULE_TM_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(dev_id, first_addr , reg_num); + + for (i = 0; i < reg_num; i++) + { + addr = first_addr + i; + rc = dpp_tm_rd_reg(dev_id, module_id, addr); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_rd_reg"); + } + + return DPP_OK; +} + +/***********************************************************/ +/** 写tm模块二层间接寄存器(仅crdt/shap模块使用) +* @param module_id 区分TM子模块 +* @param addr 基于子模块的地址 +* @param data 写入的数据 +* +* @return +* @remark 无 +* @see +* @author whuashan @date 2019/02/25 +************************************************************/ +DPP_STATUS dpp_tm_ind_wr_reg(ZXIC_UINT32 dev_id, ZXIC_UINT32 module_id, ZXIC_UINT32 addr, ZXIC_UINT64 data) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 wr_data[2] = {0}; + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, module_id, MODULE_TM_SHAP, MODULE_TM_CRDT); + + wr_data[1] = (data & 0xffffffff); + wr_data[0] = (data >> 32)&0xffffffff; + + rc = dpp_tm_ind_write(dev_id, module_id, addr, wr_data); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_ind_write"); + + return DPP_OK; +} + +/***********************************************************/ +/** 读tm模块二层间接寄存器(仅crdt/shap模块使用) +* @param module_id 区分TM子模块 +* @param addr 基于子模块的地址 +* +* @return +* @remark 无 +* @see +* @author whuashan @date 2019/02/25 +************************************************************/ +DPP_STATUS dpp_tm_ind_rd_reg(ZXIC_UINT32 dev_id, ZXIC_UINT32 module_id, ZXIC_UINT32 addr) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 rd_data[2] = {0}; + ZXIC_UINT64 tmp_data = 0; + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, module_id, MODULE_TM_SHAP, MODULE_TM_CRDT); + + rc = dpp_tm_ind_read(dev_id, module_id, addr, rd_data); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_ind_read"); + + tmp_data = ((tmp_data | rd_data[0]) << 32) | (rd_data[1]); + ZXIC_COMM_PRINT("[0x%08x] 0x%016llx \n", addr, tmp_data); + + return DPP_OK; +} +#endif + +#endif + + +#if ZXIC_REAL("TM_CFGMT") + +#if 0 +/***********************************************************/ +/** 校验子系统初始化就绪，所有子系统均初始化就绪，p_rdy值为1 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_rdy 初始化就绪标记，1-就绪，0-未就绪 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/04/09 +************************************************************/ +DPP_STATUS dpp_tm_cfgmt_subsystem_rdy_check(ZXIC_UINT32 dev_id) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 p_rdy = 0; /*tm子系统是否初始化完成判断*/ + ZXIC_UINT32 read_times = 50; + DPP_ETM_CFGMT_SUBSYSTEM_RDY_REG_T subsystem_rdy = {0}; + + + + /* 循环判定TM子系统是否初始化完成 */ + do + { + rc = dpp_reg_read(dev_id, + ETM_CFGMT_SUBSYSTEM_RDY_REGr, + 0, + 0, + &subsystem_rdy); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + p_rdy = (subsystem_rdy.olif_rdy) + && (subsystem_rdy.qmu_rdy) + && (subsystem_rdy.tmmu_rdy) + && (subsystem_rdy.cgavd_rdy) + && (subsystem_rdy.shap_rdy) + && (subsystem_rdy.crdt_rdy); + + if (p_rdy) + { + rc = dpp_tm_cfgmt_subsystem_rdy_print(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_subsystem_rdy_print"); + break; + } + + read_times--; + zxic_comm_sleep(100); + } + while (read_times > 0); + + if (read_times == 0) + { + rc = dpp_tm_cfgmt_subsystem_rdy_print(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_subsystem_rdy_print"); + ZXIC_COMM_PRINT("dpp_tm_cfgmt_subsystem_rdy_check：TM INIT FAILED !!\n"); + return DPP_ERR; + } + + return DPP_OK; +} +#endif + +/***********************************************************/ +/** cpu读写通道验证，其读出值等于写入值。读出值不等于写入值时，返回err +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/04/09 +************************************************************/ +DPP_STATUS dpp_tm_cfgmt_cpu_check(DPP_DEV_T *dev) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 input = 0x5a5a5a5a; + ZXIC_UINT32 output = 0; + DPP_ETM_CFGMT_CPU_CHECK_REG_T cpu_access_input = {0}; + DPP_ETM_CFGMT_CPU_CHECK_REG_T cpu_access_output = {0}; + ZXIC_COMM_CHECK_POINT(dev); + + cpu_access_input.cpu_check_reg = input; + rc = dpp_reg_write(dev, + ETM_CFGMT_CPU_CHECK_REGr, + 0, + 0, + &cpu_access_input); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + rc = dpp_reg_read(dev, + ETM_CFGMT_CPU_CHECK_REGr, + 0, + 0, + &cpu_access_output); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + output = cpu_access_output.cpu_check_reg; + + /* 判断读出值是否等于写入值 */ + if (input != output) + { + ZXIC_COMM_TRACE_ERROR("dpp_tm_cpu_check :input != output"); + return DPP_ERR; + } + + return DPP_OK; +} + +/***********************************************************/ +/** 配置内置TM的工作模式 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param mode 配置的值，0-TM模式，1-SA模式 +*ETM仅工作在TM模式，FTM可以工作TM或SA模式 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/25 +************************************************************/ +DPP_STATUS dpp_tm_cfgmt_sa_work_mode_set(DPP_DEV_T *dev, DPP_TM_WORK_MODE_E mode) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CFGMT_TM_SA_WORK_MODE_T tm_sa_mode = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), mode, DPP_TM_WORK_MODE_TM, DPP_TM_WORK_MODE_TM); + + tm_sa_mode.tm_sa_work_mode = mode; + rc = dpp_reg_write(dev, + ETM_CFGMT_TM_SA_WORK_MODEr, + 0, + 0, + &tm_sa_mode); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + return DPP_OK; +} + + +/***********************************************************/ +/** 读取内置TM的工作模式 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_mode 读取的值，0-TM模式，1-SA模式 +*ETM仅工作在TM模式，FTM可以工作TM或SA模式 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/25 +************************************************************/ +DPP_STATUS dpp_tm_cfgmt_sa_work_mode_get(DPP_DEV_T *dev, DPP_TM_WORK_MODE_E *p_mode) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CFGMT_TM_SA_WORK_MODE_T tm_sa_mode = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_mode); + + *p_mode = DPP_TM_WORK_MODE_INVALID; + + rc = dpp_reg_read(dev, + ETM_CFGMT_TM_SA_WORK_MODEr, + 0, + 0, + &tm_sa_mode); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + *p_mode = tm_sa_mode.tm_sa_work_mode; + + return DPP_OK; +} + +/***********************************************************/ +/** 配置ddr3挂接组数，共10bit[0-9]，每bit对应1组ddr，TM最多使用其中8组 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param ddr_num 单个tm使用的ddr组：bit[0-9]每bit代表一组ddr，如使用4567组，则配置0xf0 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cuiy @date 2016/06/07 +************************************************************/ +DPP_STATUS dpp_tm_cfgmt_ddr_attach_set(DPP_DEV_T *dev, ZXIC_UINT32 ddr_num) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CFGMT_CFGMT_DDR_ATTACH_T ddr_attach = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), ddr_num, 0, 0x3FF); + + ddr_attach.cfgmt_ddr_attach = ddr_num; + rc = dpp_reg_write(dev, + ETM_CFGMT_CFGMT_DDR_ATTACHr, + 0, + 0, + &ddr_attach); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + return DPP_OK; +} + +/***********************************************************/ +/** 读取ddr3挂接组数 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_ddr_num ddr组数,1-6组 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/04/09 +************************************************************/ +DPP_STATUS dpp_tm_cfgmt_ddr_attach_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_ddr_num) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CFGMT_CFGMT_DDR_ATTACH_T ddr_attach = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_ddr_num); + + rc = dpp_reg_read(dev, + ETM_CFGMT_CFGMT_DDR_ATTACHr, + 0, + 0, + &ddr_attach); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + if (ddr_attach.cfgmt_ddr_attach == 1) + { + *p_ddr_num = 1; + } + else if (ddr_attach.cfgmt_ddr_attach == 3) + { + *p_ddr_num = 2; + } + else if (ddr_attach.cfgmt_ddr_attach == 7) + { + *p_ddr_num = 3; + } + else if (ddr_attach.cfgmt_ddr_attach == 15) + { + *p_ddr_num = 4; + } + else if (ddr_attach.cfgmt_ddr_attach == 31) + { + *p_ddr_num = 5; + } + else if (ddr_attach.cfgmt_ddr_attach == 63) + { + *p_ddr_num = 6; + } + else if (ddr_attach.cfgmt_ddr_attach == 127) + { + *p_ddr_num = 7; + } + else if (ddr_attach.cfgmt_ddr_attach == 255) + { + *p_ddr_num = 8; + } + + return DPP_OK; +} + +/***********************************************************/ +/** 配置QMU工作模式，0：8 block工作模式，1：16 block工作模式 +*** (即一个chunk中block个数) 影响tm总可用的缓存节点数。 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param mode 0-128/256K节点，1-256/512K节点，目前固定配1 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/25 +************************************************************/ +DPP_STATUS dpp_tm_cfgmt_qmu_work_mode_set(DPP_DEV_T *dev, DPP_TM_QMU_WORK_MODE_E mode) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CFGMT_QMU_WORK_MODE_T qmu_mode = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), mode, DPP_TM_QMU_WORK_MODE_2M, DPP_TM_QMU_WORK_MODE_4M); + + qmu_mode.qmu_work_mode = mode; + rc = dpp_reg_write(dev, + ETM_CFGMT_QMU_WORK_MODEr, + 0, + 0, + &qmu_mode); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + return DPP_OK; +} + + +/***********************************************************/ +/** 读取QMU工作模式，0：8 block工作模式，1：16 block工作模式 +*** (即一个chunk中block个数) 影响tm总可用的缓存节点数。 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param mode 0-128/256K节点，1-256/512K节点，目前固定配1 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/25 +************************************************************/ +DPP_STATUS dpp_tm_cfgmt_qmu_work_mode_get(DPP_DEV_T *dev, DPP_TM_QMU_WORK_MODE_E *p_mode) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CFGMT_QMU_WORK_MODE_T qmu_mode = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_mode); + + rc = dpp_reg_read(dev, + ETM_CFGMT_QMU_WORK_MODEr, + 0, + 0, + &qmu_mode); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + *p_mode = qmu_mode.qmu_work_mode; + + return DPP_OK; +} + + + +#if 0 +/***********************************************************/ +/** 配置包存储的CRC功能是否使能 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param en 配置的值，0-禁止CRC功能，1-允许CRC功能 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/25 +************************************************************/ +DPP_STATUS dpp_tm_cfgmt_crc_en_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 en) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CFGMT_CFGMT_CRC_EN_T crc_en = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, en, 0, 1); + + crc_en.cfgmt_crc_en = en; + rc = dpp_reg_write(dev_id, + ETM_CFGMT_CFGMT_CRC_ENr, + 0, + 0, + &crc_en); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + return DPP_OK; +} + +/***********************************************************/ +/** 读取包存储的CRC功能是否使能 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_en 读取的值，0-禁止CRC功能，1-允许CRC功能 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/25 +************************************************************/ +DPP_STATUS dpp_tm_cfgmt_crc_en_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_en) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CFGMT_CFGMT_CRC_EN_T crc_en = {0}; + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_en); + + *p_en = 0xffffffff; + rc = dpp_reg_read(dev_id, + ETM_CFGMT_CFGMT_CRC_ENr, + 0, + 0, + &crc_en); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + *p_en = crc_en.cfgmt_crc_en; + + return DPP_OK; +} +#endif +/***********************************************************/ +/** 配置block长度模式 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param size block长度模式:256/512/1024 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/04/09 +************************************************************/ +DPP_STATUS dpp_tm_cfgmt_blk_size_set(DPP_DEV_T *dev, ZXIC_UINT32 size) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CFGMT_CFGMT_BLKSIZE_T blk_size = {0}; + ZXIC_COMM_CHECK_POINT(dev); + + switch (size) + { + case 256: + { + blk_size.cfgmt_blksize = DPP_ETM_BLK_SIZE_256_B; + break; + } + + case 512: + { + blk_size.cfgmt_blksize = DPP_ETM_BLK_SIZE_512_B; + break; + } + + case 1024: + { + blk_size.cfgmt_blksize = DPP_ETM_BLK_SIZE_1024_B; + break; + } + + default: + { + ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "dpp_tm_cfgmt_blk_size_set:TM set block size error!\n"); + return DPP_ERR; + } + } + + rc = dpp_reg_write(dev, + ETM_CFGMT_CFGMT_BLKSIZEr, + 0, + 0, + &blk_size); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + return DPP_OK; +} + +/***********************************************************/ +/** 读取block长度模式 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_size block长度模式，256/512/1024 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/04/09 +************************************************************/ +DPP_STATUS dpp_tm_cfgmt_blk_size_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_size) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CFGMT_CFGMT_BLKSIZE_T blk_size = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_size); + + rc = dpp_reg_read(dev, + ETM_CFGMT_CFGMT_BLKSIZEr, + 0, + 0, + &blk_size); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + switch (blk_size.cfgmt_blksize) + { + case DPP_ETM_BLK_SIZE_256_B: + { + *p_size = 256; + break; + } + + case DPP_ETM_BLK_SIZE_512_B: + { + *p_size = 512; + break; + } + + case DPP_ETM_BLK_SIZE_1024_B: + { + *p_size = 1024; + break; + } + + default: + { + *p_size = 256; + } + } + + return DPP_OK; +} + +#if 0 +/***********************************************************/ +/** 配置计数模式 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_mode 计数模式 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/04/09 +************************************************************/ +DPP_STATUS dpp_tm_cfgmt_cnt_mode_set(ZXIC_UINT32 dev_id, DPP_TM_CNT_MODE_T *p_mode) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CFGMT_CNT_MODE_REG_T cnt_mode = {0}; + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_mode); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, p_mode->fc_count_mode, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, p_mode->count_rd_mode, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, p_mode->count_overflow_mode, 0, 1); + + cnt_mode.cfgmt_fc_count_mode = p_mode->fc_count_mode; + cnt_mode.cfgmt_count_rd_mode = p_mode->count_rd_mode; + cnt_mode.cfgmt_count_overflow_mode = p_mode->count_overflow_mode; + rc = dpp_reg_write(dev_id, + ETM_CFGMT_CNT_MODE_REGr, + 0, + 0, + &cnt_mode); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + return DPP_OK; +} + +/***********************************************************/ +/** 读取计数模式 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_mode 计数模式 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/04/09 +************************************************************/ +DPP_STATUS dpp_tm_cfgmt_cnt_mode_get(ZXIC_UINT32 dev_id, DPP_TM_CNT_MODE_T *p_mode) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CFGMT_CNT_MODE_REG_T cnt_mode = {0}; + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_mode); + + rc = dpp_reg_read(dev_id, + ETM_CFGMT_CNT_MODE_REGr, + 0, + 0, + &cnt_mode); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + p_mode->fc_count_mode = cnt_mode.cfgmt_fc_count_mode; + p_mode->count_rd_mode = cnt_mode.cfgmt_count_rd_mode; + p_mode->count_overflow_mode = cnt_mode.cfgmt_count_overflow_mode; + + return DPP_OK; +} + +/***********************************************************/ +/** 配置中断屏蔽 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_para 中断屏蔽 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/04/09 +************************************************************/ +DPP_STATUS dpp_tm_cfgmt_int_mask_set(ZXIC_UINT32 dev_id, DPP_TM_INT_T *p_para) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CFGMT_REG_INT_MASK_REG_T int_mask = {0}; + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_para); + + int_mask.shap_int_mask = p_para->shap_int; + int_mask.crdt_int_mask = p_para->crdt_int; + int_mask.tmmu_int_mask = p_para->mmu_int; + int_mask.qmu_int_mask = p_para->qmu_int; + int_mask.cgavd_int_mask = p_para->cgavd_int; + int_mask.olif_int_mask = p_para->olif_int; + int_mask.cfgmt_int_buf_mask = p_para->cfgmt_int; + + rc = dpp_reg_write(dev_id, + ETM_CFGMT_REG_INT_MASK_REGr, + 0, + 0, + &int_mask); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + return DPP_OK; +} + + +/***********************************************************/ +/** 读取中断屏蔽 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_para 中断屏蔽 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/04/09 +************************************************************/ +DPP_STATUS dpp_tm_cfgmt_int_mask_get(ZXIC_UINT32 dev_id, DPP_TM_INT_T *p_para) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CFGMT_REG_INT_MASK_REG_T int_mask = {0}; + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_para); + + rc = dpp_reg_read(dev_id, + ETM_CFGMT_REG_INT_MASK_REGr, + 0, + 0, + &int_mask); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + p_para->shap_int = int_mask.shap_int_mask; + p_para->crdt_int = int_mask.crdt_int_mask; + p_para->mmu_int = int_mask.tmmu_int_mask; + p_para->qmu_int = int_mask.qmu_int_mask; + p_para->cgavd_int = int_mask.cgavd_int_mask; + p_para->olif_int = int_mask.olif_int_mask; + p_para->cfgmt_int = int_mask.cfgmt_int_buf_mask; + + return DPP_OK; +} + +/***********************************************************/ +/** 读取中断状态 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_para 中断状态 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/04/09 +************************************************************/ +DPP_STATUS dpp_tm_cfgmt_int_state_get(ZXIC_UINT32 dev_id, DPP_TM_INT_T *p_para) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CFGMT_REG_INT_STATE_REG_T int_state = {0}; + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_para); + + rc = dpp_reg_read(dev_id, + ETM_CFGMT_REG_INT_STATE_REGr, + 0, + 0, + &int_state); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + p_para->shap_int = int_state.shap_int; + p_para->crdt_int = int_state.crdt_int; + p_para->mmu_int = int_state.mmu_int; + p_para->qmu_int = int_state.qmu_int; + p_para->cgavd_int = int_state.cgavd_int; + p_para->olif_int = int_state.olif_int; + p_para->cfgmt_int = int_state.cfgmt_int_buf; + + return DPP_OK; +} + +/***********************************************************/ +/** 配置tm时钟门控是否使能 +* @param dev_id 设备编号 +* @param en 配置的值，0-禁止tm时钟门控，1-使能tm时钟门控 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author lsy @date 2022/08/22 +************************************************************/ +DPP_STATUS dpp_tm_cfgmt_clkgate_en_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 en) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CFGMT_CLKGATE_EN_T clkgate_en = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, en, 0, 1); + + clkgate_en.clkgate_en = en; + rc = dpp_reg_write(dev_id, + ETM_CFGMT_CLKGATE_ENr, + 0, + 0, + &clkgate_en); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + return DPP_OK; +} + +/***********************************************************/ +/** 读取tm时钟门控是否使能 +* @param dev_id 设备编号 +* @param en 配置的值，0-禁止tm时钟门控，1-使能tm时钟门控 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author lsy @date 2022/08/22 + +************************************************************/ +DPP_STATUS dpp_tm_cfgmt_clkgate_en_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_en) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CFGMT_CLKGATE_EN_T clkgate_en = {0}; + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_en); + + *p_en = 0xffffffff; + rc = dpp_reg_read(dev_id, + ETM_CFGMT_CLKGATE_ENr, + 0, + 0, + &clkgate_en); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + *p_en = clkgate_en.clkgate_en; + + return DPP_OK; +} + +/***********************************************************/ +/** 配置tm软复位是否使能 +* @param dev_id 设备编号 +* @param en 配置的值，0-禁止tm软复位，1-使能tm软复位 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author lsy @date 2022/08/22 +************************************************************/ +DPP_STATUS dpp_tm_cfgmt_softrst_en_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 en) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CFGMT_SOFTRST_EN_T softrst_en = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, en, 0, 1); + + softrst_en.softrst_en = en; + rc = dpp_reg_write(dev_id, + ETM_CFGMT_SOFTRST_ENr, + 0, + 0, + &softrst_en); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + return DPP_OK; +} + +/***********************************************************/ +/** 读取tm软复位是否使能 +* @param dev_id 设备编号 +* @param en 配置的值，0-禁止tm软复位，1-使能tm软复位 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author lsy @date 2022/08/22 + +************************************************************/ +DPP_STATUS dpp_tm_cfgmt_softrst_en_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_en) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CFGMT_SOFTRST_EN_T softrst_en = {0}; + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_en); + + *p_en = 0xffffffff; + rc = dpp_reg_read(dev_id, + ETM_CFGMT_SOFTRST_ENr, + 0, + 0, + &softrst_en); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + *p_en = softrst_en.softrst_en; + + return DPP_OK; +} + +#endif +#endif + + + +#if ZXIC_REAL("TM_CGAVD") + +#if 0 +/***********************************************************/ +/** 配置各级搬移功能使能 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param level 要配置的拥塞避免层次号，0:队列级，1:端口级，2:系统级 +* @param en 使能标记，0-不使能，1-使能 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2016/10/18 +************************************************************/ +#ifdef ETM_REAL + +DPP_STATUS dpp_tm_cgavd_move_en_set(ZXIC_UINT32 dev_id, + DPP_TM_CGAVD_LEVEL_E level, + ZXIC_UINT32 en) +{ + DPP_STATUS rc = DPP_OK; + + DPP_ETM_CGAVD_CGAVD_CFG_MOVE_T cgavd_cfg_move = {0}; + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, level, QUEUE_LEVEL, SYS_LEVEL); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, en, 0, 1); + + rc = dpp_reg_read(dev_id, + ETM_CGAVD_CGAVD_CFG_MOVEr, + 0, + 0, + &cgavd_cfg_move); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + if (QUEUE_LEVEL == level) + { + cgavd_cfg_move.cfgmt_flow_move_en = en; + } + + else if (PP_LEVEL == level) + { + cgavd_cfg_move.cfgmt_port_move_en = en; + } + + else if (SYS_LEVEL == level) + { + cgavd_cfg_move.cfgmt_sys_move_en = en; + } + + rc = dpp_reg_write(dev_id, + ETM_CGAVD_CGAVD_CFG_MOVEr, + 0, + 0, + &cgavd_cfg_move); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + return DPP_OK; +} + +/***********************************************************/ +/** 读取各级搬移功能使能 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param level 要配置的拥塞避免层次号，0:队列级，1:端口级，2:系统级 +* @param p_en 读出的使能标记，0-不使能，1-使能 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2016/10/18 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_move_en_get(ZXIC_UINT32 dev_id, + DPP_TM_CGAVD_LEVEL_E level, + ZXIC_UINT32 *p_en) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CGAVD_CGAVD_CFG_MOVE_T cgavd_cfg_move = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, level, QUEUE_LEVEL, SYS_LEVEL); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_en); + + *p_en = 0xffffffff; + + rc = dpp_reg_read(dev_id, + ETM_CGAVD_CGAVD_CFG_MOVEr, + 0, + 0, + &cgavd_cfg_move); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + if (QUEUE_LEVEL == level) + { + *p_en = cgavd_cfg_move.cfgmt_flow_move_en; + } + + else if (PP_LEVEL == level) + { + *p_en = cgavd_cfg_move.cfgmt_port_move_en; + } + + else if (SYS_LEVEL == level) + { + *p_en = cgavd_cfg_move.cfgmt_sys_move_en; + } + + return DPP_OK; +} + + +/***********************************************************/ +/** 配置各级搬移门限 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param level 拥塞避免支持层次号，0:队列级，1:端口级，2:系统级 +* @param id 队列号或端口号，系统级时，id参数无效 +* @param value 端口级和系统级时，为搬移门限值，单位为NPPU存包的单位，256B； + 流级时为搬移profile_id,0~15 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2016/10/18 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_move_th_set(ZXIC_UINT32 dev_id, + DPP_TM_CGAVD_LEVEL_E level, + ZXIC_UINT32 id, + ZXIC_UINT32 value) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 q_move_profile_reg_index = 0; + ZXIC_UINT32 pp_move_th_reg_index = 0; + ZXIC_UINT32 sys_move_th_reg_index = 0; + + DPP_ETM_CGAVD_MOVE_FLOW_TH_PROFILE_T q_move_profile = {0}; + DPP_ETM_CGAVD_MV_PORT_TH_T pp_move_th = {0}; + DPP_ETM_CGAVD_CFGMT_TOTAL_TH_T sys_move_th = {0}; + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, level, QUEUE_LEVEL, SYS_LEVEL); + + + q_move_profile_reg_index = ETM_CGAVD_MOVE_FLOW_TH_PROFILEr; + pp_move_th_reg_index = ETM_CGAVD_MV_PORT_THr; + sys_move_th_reg_index = ETM_CGAVD_CFGMT_TOTAL_THr; + + + if (QUEUE_LEVEL == level) + { + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, value, 0, DPP_TM_CGAVD_MOVE_PROFILE_NUM - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, id, 0, DPP_ETM_Q_NUM - 1); + + q_move_profile.move_drop_profile = value; + rc = dpp_reg_write(dev_id, + q_move_profile_reg_index, + 0, + id, + &q_move_profile); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + } + + else if (PP_LEVEL == level) + { + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, id, 0, DPP_TM_PP_NUM - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, value, 0, 0x3fff); + + pp_move_th.port_th = value; + rc = dpp_reg_write(dev_id, + pp_move_th_reg_index, + 0, + id, + &pp_move_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + else + { + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, value, 0, 0x3fff); + + sys_move_th.cfgmt_total_th = value; + rc = dpp_reg_write(dev_id, + sys_move_th_reg_index, + 0, + 0, + &sys_move_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + return DPP_OK; + +} + + +/***********************************************************/ +/** 读取各级搬移门限 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param level 拥塞避免支持层次号，0:队列级，1:端口级，2:系统级 +* @param id 队列号或端口号，系统级时，id参数无效 +* @param p_value 端口级和系统级时，为搬移门限值，单位为NPPU存包的单位，256B； + 流级时为搬移profile_id,0~15 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2016/10/18 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_move_th_get(ZXIC_UINT32 dev_id, + DPP_TM_CGAVD_LEVEL_E level, + ZXIC_UINT32 id, + ZXIC_UINT32 *p_value) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 q_move_profile_reg_index = 0; + ZXIC_UINT32 pp_move_th_reg_index = 0; + ZXIC_UINT32 sys_move_th_reg_index = 0; + + DPP_ETM_CGAVD_MOVE_FLOW_TH_PROFILE_T q_move_profile = {0}; + DPP_ETM_CGAVD_MV_PORT_TH_T pp_move_th = {0}; + DPP_ETM_CGAVD_CFGMT_TOTAL_TH_T sys_move_th = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, level, QUEUE_LEVEL, SYS_LEVEL); + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_value); + + q_move_profile_reg_index = ETM_CGAVD_MOVE_FLOW_TH_PROFILEr; + pp_move_th_reg_index = ETM_CGAVD_MV_PORT_THr; + sys_move_th_reg_index = ETM_CGAVD_CFGMT_TOTAL_THr; + + + + if (QUEUE_LEVEL == level) + { + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, id, 0, DPP_ETM_Q_NUM - 1); + + rc = dpp_reg_read(dev_id, + q_move_profile_reg_index, + 0, + id, + &q_move_profile); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + *p_value = q_move_profile.move_drop_profile; + } + + else if (PP_LEVEL == level) + { + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, id, 0, DPP_TM_PP_NUM - 1); + rc = dpp_reg_read(dev_id, + pp_move_th_reg_index, + 0, + id, + &pp_move_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + *p_value = pp_move_th.port_th; + } + + else + { + rc = dpp_reg_read(dev_id, + sys_move_th_reg_index, + 0, + 0, + &sys_move_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + *p_value = sys_move_th.cfgmt_total_th; + } + + return DPP_OK; + +} + + +/***********************************************************/ +/** 配置flow级的搬移策略 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param move_profile flow级的搬移门限分组索引,0~15 +* @param th flow级的搬移门限，单位为KB； +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2016/10/18 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_flow_move_profile_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 move_profile, + ZXIC_UINT32 th) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 flow_move_th_reg_index = 0; + ZXIC_UINT32 blk_size = 0; + ZXIC_UINT32 move_th = 0; + ZXIC_UINT32 cgavd_cfg_mode = 0; + DPP_ETM_CGAVD_MOVE_FLOW_TH_T flow_th = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, move_profile, 0, DPP_TM_CGAVD_MOVE_PROFILE_NUM - 1); + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, th , DPP_TM_CGAVD_KILO_UL); + move_th = th * DPP_TM_CGAVD_KILO_UL; + + flow_move_th_reg_index = ETM_CGAVD_MOVE_FLOW_THr; + + rc = dpp_tm_cgavd_cfg_mode_get(dev_id, &cgavd_cfg_mode); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_cfg_mode_get"); + + if (cgavd_cfg_mode == DPP_TM_CGAVD_BLOCK_MODE) + { + rc = dpp_tm_cfgmt_blk_size_get(dev_id, &blk_size); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_blk_size_get"); + + if (blk_size != 0) + { + move_th = (move_th / blk_size); + move_th = (move_th % blk_size == 0) ? (move_th ) : ((move_th) + 1); + } + } + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, move_th, 0, 0x1fffffff); + + flow_th.move_drop_flow_th = move_th; + rc = dpp_reg_write(dev_id, + flow_move_th_reg_index, + 0, + move_profile, + &flow_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + return DPP_OK; +} + + +/***********************************************************/ +/** 读取flow级的搬移策略 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param move_profile flow级的搬移门限分组索引,0~15 +* @param p_th flow级的搬移门限，单位为KB； +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2016/10/18 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_flow_move_profile_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 move_profile, + ZXIC_UINT32 *p_th) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 flow_move_th_reg_index = 0; + ZXIC_UINT32 blk_size = 0; + ZXIC_UINT32 move_th = 0; + ZXIC_UINT32 cgavd_cfg_mode = 0; + + DPP_ETM_CGAVD_MOVE_FLOW_TH_T flow_th = {0}; + + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, move_profile, 0, DPP_TM_CGAVD_MOVE_PROFILE_NUM - 1); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_th); + + flow_move_th_reg_index = ETM_CGAVD_MOVE_FLOW_THr; + + rc = dpp_reg_read(dev_id, + flow_move_th_reg_index, + 0, + move_profile, + &flow_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + move_th = flow_th.move_drop_flow_th; + + rc = dpp_tm_cgavd_cfg_mode_get(dev_id, &cgavd_cfg_mode); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_cfg_mode_get"); + + if (cgavd_cfg_mode == DPP_TM_CGAVD_BLOCK_MODE) + { + rc = dpp_tm_cfgmt_blk_size_get(dev_id, &blk_size); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_blk_size_get"); + + *p_th = (move_th * blk_size) / DPP_TM_CGAVD_KILO_UL; + } + else if (cgavd_cfg_mode == DPP_TM_CGAVD_ZXIC_UINT8_MODE) + { + *p_th = (move_th / DPP_TM_CGAVD_KILO_UL); + } + else + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "dpp_tm_cgavd_flow_move_profile_get:cgavd_cfg_mode is err!!\n"); + return DPP_ERR; + } + + return DPP_OK; +} +#endif +/***********************************************************/ +/** 配置端口共享的搬移门限 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param th 端口共享的搬移门限，单位为NPPU存包的单位，256B； +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2016/10/18 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_port_share_th_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 th) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 port_share_th_reg_index = 0; + + DPP_ETM_CGAVD_CFGMT_PORT_SHARE_TH_T port_share_th = {0}; + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, th, 0, 0x3fff); + + port_share_th_reg_index = ETM_CGAVD_CFGMT_PORT_SHARE_THr; + + port_share_th.cfgmt_port_share_th = th; + + rc = dpp_reg_write(dev_id, + port_share_th_reg_index, + 0, + 0, + &port_share_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + return DPP_OK; +} + + +/***********************************************************/ +/** 读取端口共享的搬移门限 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_th 端口共享的搬移门限，单位为NPPU存包的单位，256B； +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2016/10/18 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_port_share_th_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *p_th) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 port_share_th_reg_index = 0; + + DPP_ETM_CGAVD_CFGMT_PORT_SHARE_TH_T port_share_th = {0}; + + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_th); + + port_share_th_reg_index = ETM_CGAVD_CFGMT_PORT_SHARE_THr; + + rc = dpp_reg_read(dev_id, + port_share_th_reg_index, + 0, + 0, + &port_share_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + *p_th = port_share_th.cfgmt_port_share_th; + + return DPP_OK; +} + +/***********************************************************/ +/** 配置基于优先级的QMU接收NPPU数据的fifo阈值 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param sp 优先级0~7 +* @param th 指定优先级的fifo阈值0~511，单位为fifo条目，fifo深度512 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2016/10/18 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_move_drop_sp_th_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 sp, + ZXIC_UINT32 th) +{ + DPP_STATUS rc = DPP_OK; + + DPP_ETM_CGAVD_MV_DROP_SP_TH_T sp_th = {0}; + + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, th, 0, 0x1ff); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, sp, 0, 7); + + sp_th.mvdrop_sp_th = th; + + rc = dpp_reg_write(dev_id, + ETM_CGAVD_MV_DROP_SP_THr, + 0, + sp, + &sp_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + return DPP_OK; +} + +/***********************************************************/ +/** 读取基于优先级的QMU接收NPPU数据的fifo阈值 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param sp 优先级0~7 +* @param p_th 指定优先级的fifo阈值0~511，单位为fifo条目，fifo深度512 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2016/10/18 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_move_drop_sp_th_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 sp, + ZXIC_UINT32 *p_th) +{ + DPP_STATUS rc = DPP_OK; + + DPP_ETM_CGAVD_MV_DROP_SP_TH_T sp_th = {0}; + + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, sp, 0, 7); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_th); + + rc = dpp_reg_read(dev_id, + ETM_CGAVD_MV_DROP_SP_THr, + 0, + sp, + &sp_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + *p_th = sp_th.mvdrop_sp_th; + + return DPP_OK; +} + + +/***********************************************************/ +/** 配置强制片内或片外 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param en 1:使能 +* @param mode 1 :omem 强制片外 0:imem 强制片内 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author wush @date 2017/10/14 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_imem_omem_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 en, + ZXIC_UINT32 mode) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CGAVD_CGAVD_FORCE_IMEM_OMEM_T cgavd_imem_omem_mode = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, en, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, mode, 0, 1); + + rc = dpp_reg_read(dev_id, + ETM_CGAVD_CGAVD_FORCE_IMEM_OMEMr, + 0, + 0, + &cgavd_imem_omem_mode); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + cgavd_imem_omem_mode.choose_imem_omem = mode; + cgavd_imem_omem_mode.imem_omem_force_en = en; + + rc = dpp_reg_write(dev_id, + ETM_CGAVD_CGAVD_FORCE_IMEM_OMEMr, + 0, + 0, + &cgavd_imem_omem_mode); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + return DPP_OK; +} + + +/***********************************************************/ +/** 获取强制片内或片外 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param en 1:使能 +* @param mode 1 :omem 强制片外 0:imem 强制片内 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author wush @date 2017/10/14 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_imem_omem_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *p_en, + ZXIC_UINT32 *p_mode) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CGAVD_CGAVD_FORCE_IMEM_OMEM_T cgavd_imem_omem_mode = {0}; + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_mode); + + rc = dpp_reg_read(dev_id, + ETM_CGAVD_CGAVD_FORCE_IMEM_OMEMr, + 0, + 0, + &cgavd_imem_omem_mode); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + *p_mode = cgavd_imem_omem_mode.choose_imem_omem; + *p_en = cgavd_imem_omem_mode.imem_omem_force_en; + + return DPP_OK; +} + +#endif + +/***********************************************************/ +/** 配置配置cgavd模式 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param mode 0:block mode 1:byte mode +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cy @date 2016/07/28 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_cfg_mode_set(DPP_DEV_T *dev, + ZXIC_UINT32 mode) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CGAVD_CFGMT_BYTE_MODE_T cgavd_cfg_mode = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), mode, 0, 1); + + rc = dpp_reg_read(dev, + ETM_CGAVD_CFGMT_BYTE_MODEr, + 0, + 0, + &cgavd_cfg_mode); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + cgavd_cfg_mode.cfgmt_byte_mode = mode; + + rc = dpp_reg_write(dev, + ETM_CGAVD_CFGMT_BYTE_MODEr, + 0, + 0, + &cgavd_cfg_mode); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + return DPP_OK; +} + + +/***********************************************************/ +/** 获取cgavd模式 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_mode 0:block mode 1:byte mode +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cy @date 2016/07/29 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_cfg_mode_get(DPP_DEV_T *dev, + ZXIC_UINT32 *p_mode) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CGAVD_CFGMT_BYTE_MODE_T cgavd_cfg_mode = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_mode); + + rc = dpp_reg_read(dev, + ETM_CGAVD_CFGMT_BYTE_MODEr, + 0, + 0, + &cgavd_cfg_mode); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + *p_mode = cgavd_cfg_mode.cfgmt_byte_mode; + + return DPP_OK; +} + + +/***********************************************************/ +/** 配置各级拥塞避免功能使能 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param level 要配置的拥塞避免层次号，0:队列级，1:端口级，2:系统级 +* @param en 使能标记，0-不使能，1-使能 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/28 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_en_set(DPP_DEV_T *dev, + DPP_TM_CGAVD_LEVEL_E level, + ZXIC_UINT32 en) +{ + DPP_STATUS rc = DPP_OK; + + DPP_ETM_CGAVD_CGAVD_SUB_EN_T cgavd_sub_en = {0}; + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_POINT(dev); + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), level, QUEUE_LEVEL, SA_LEVEL); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), en, 0, 1); + + rc = dpp_reg_read(dev, + ETM_CGAVD_CGAVD_SUB_ENr, + 0, + 0, + &cgavd_sub_en); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + if (QUEUE_LEVEL == level) + { + cgavd_sub_en.cgavd_flow_sub_en = en; + } + + else if (PP_LEVEL == level) + { + cgavd_sub_en.cgavd_pp_sub_en = en; + } + + else if (SYS_LEVEL == level) + { + cgavd_sub_en.cgavd_sys_sub_en = en; + } + + rc = dpp_reg_write(dev, + ETM_CGAVD_CGAVD_SUB_ENr, + 0, + 0, + &cgavd_sub_en); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + return DPP_OK; +} + +/***********************************************************/ +/** 读取各级拥塞避免功能使能 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param level 要读取的拥塞避免层次号，0:队列级，1:端口级，2:系统级 +* @param p_en 读出的使能标记，0-不使能，1-使能 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/28 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_en_get(DPP_DEV_T *dev, + DPP_TM_CGAVD_LEVEL_E level, + ZXIC_UINT32 *p_en) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CGAVD_CGAVD_SUB_EN_T cgavd_sub_en = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), level, QUEUE_LEVEL, SA_LEVEL); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_en); + + *p_en = 0xffffffff; + + rc = dpp_reg_read(dev, + ETM_CGAVD_CGAVD_SUB_ENr, + 0, + 0, + &cgavd_sub_en); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + if (level == QUEUE_LEVEL) + { + *p_en = cgavd_sub_en.cgavd_flow_sub_en; + } + + else if (level == PP_LEVEL) + { + *p_en = cgavd_sub_en.cgavd_pp_sub_en; + } + + else if (level == SYS_LEVEL) + { + *p_en = cgavd_sub_en.cgavd_sys_sub_en; + } + + else if (level == SA_LEVEL) + { + *p_en = cgavd_sub_en.cgavd_sa_sub_en; + } + + return DPP_OK; +} + +/***********************************************************/ +/** dp选取来源 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param level 要配置的拥塞避免层次号，0:队列级，1:端口级，2:系统级 +* @param dp_sel dp选取来源，0-dp，1-tc，2-pkt_len[2:0] +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2017/03/14 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_dp_sel_set(DPP_DEV_T *dev, + DPP_TM_CGAVD_LEVEL_E level, + DPP_TM_CGAVD_DP_SEL_E dp_sel) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CGAVD_CGAVD_DP_SEL_T cgavd_dp_sel = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), level, QUEUE_LEVEL, SYS_LEVEL); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), dp_sel, DP_SEL_DP, DP_SEL_PKT_LEN); + + rc = dpp_reg_read(dev, + ETM_CGAVD_CGAVD_DP_SELr, + 0, + 0, + &cgavd_dp_sel); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + if (QUEUE_LEVEL == level) + { + if (DP_SEL_DP == dp_sel) + { + cgavd_dp_sel.flow_dp_sel_high = 0; + cgavd_dp_sel.flow_dp_sel_mid = 0; + cgavd_dp_sel.flow_dp_sel_low = 1; + } + else if (DP_SEL_TC == dp_sel) + { + cgavd_dp_sel.flow_dp_sel_high = 0; + cgavd_dp_sel.flow_dp_sel_mid = 1; + cgavd_dp_sel.flow_dp_sel_low = 0; + } + else if (DP_SEL_PKT_LEN == dp_sel) + { + cgavd_dp_sel.flow_dp_sel_high = 1; + cgavd_dp_sel.flow_dp_sel_mid = 0; + cgavd_dp_sel.flow_dp_sel_low = 0; + } + } + + else if (PP_LEVEL == level) + { + if (DP_SEL_DP == dp_sel) + { + cgavd_dp_sel.pp_dp_sel_high = 0; + cgavd_dp_sel.pp_dp_sel_mid = 0; + cgavd_dp_sel.pp_dp_sel_low = 1; + } + else if (DP_SEL_TC == dp_sel) + { + cgavd_dp_sel.pp_dp_sel_high = 0; + cgavd_dp_sel.pp_dp_sel_mid = 1; + cgavd_dp_sel.pp_dp_sel_low = 0; + } + else if (DP_SEL_PKT_LEN == dp_sel) + { + cgavd_dp_sel.pp_dp_sel_high = 1; + cgavd_dp_sel.pp_dp_sel_mid = 0; + cgavd_dp_sel.pp_dp_sel_low = 0; + } + } + + else if (SYS_LEVEL == level) + { + if (DP_SEL_DP == dp_sel) + { + cgavd_dp_sel.sys_dp_sel_high = 0; + cgavd_dp_sel.sys_dp_sel_mid = 0; + cgavd_dp_sel.sys_dp_sel_low = 1; + } + else if (DP_SEL_TC == dp_sel) + { + cgavd_dp_sel.sys_dp_sel_high = 0; + cgavd_dp_sel.sys_dp_sel_mid = 1; + cgavd_dp_sel.sys_dp_sel_low = 0; + } + else if (DP_SEL_PKT_LEN == dp_sel) + { + cgavd_dp_sel.sys_dp_sel_high = 1; + cgavd_dp_sel.sys_dp_sel_mid = 0; + cgavd_dp_sel.sys_dp_sel_low = 0; + } + } + + rc = dpp_reg_write(dev, + ETM_CGAVD_CGAVD_DP_SELr, + 0, + 0, + &cgavd_dp_sel); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + return DPP_OK; +} + + +/***********************************************************/ +/** 配置拥塞避免算法 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param level 拥塞避免支持层次号，0:队列级，1:端口级，2:系统级 +* @param id 队列号或端口号，系统级时，id参数无效 +* @param method 配置的拥塞避免算法，0:TD，1:WRED/GRED +* 配置TD算法时，先配TD阈值，再配置TD算法 +* 配置WRED算法时,先配置流级或端口级的平均队列深度，再配置WRED算法 +* 配置GRED算法时，先配置系统级的平均队列深度，在配置成GRED算法 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark +* @see +* @author taq @date 2015/04/14 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_method_set(DPP_DEV_T *dev, + DPP_TM_CGAVD_LEVEL_E level, + ZXIC_UINT32 id, + DPP_TM_CGAVD_METHOD_E method) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 q_avg_q_len_reg_index = 0; + ZXIC_UINT32 q_td_th_reg_index = 0; + ZXIC_UINT32 q_ca_mtd_reg_index = 0; + ZXIC_UINT32 pp_avg_q_len_reg_index = 0; + ZXIC_UINT32 pp_td_th_reg_index = 0; + ZXIC_UINT32 pp_ca_mtd_reg_index = 0; + ZXIC_UINT32 sys_avg_q_len_reg_index = 0; + ZXIC_UINT32 sys_td_th_reg_index = 0; + ZXIC_UINT32 sys_ca_mtd_reg_index = 0; + + DPP_ETM_CGAVD_FLOW_CA_MTD_T q_cgavd_method = {0}; + DPP_ETM_CGAVD_PP_CA_MTD_T pp_cgavd_method = {0}; + DPP_ETM_CGAVD_SYS_CGAVD_METD_T sys_cgavd_method = {0}; + DPP_ETM_CGAVD_FLOW_AVG_Q_LEN_T flow_avg_q_len = {0}; + DPP_ETM_CGAVD_PP_AVG_Q_LEN_T pp_avg_q_len = {0}; + DPP_ETM_CGAVD_SYS_AVG_Q_LEN_T sys_avg_q_len = {0}; + DPP_ETM_CGAVD_FLOW_TD_TH_T q_td_th = {0}; + DPP_ETM_CGAVD_PP_TD_TH_T pp_td_th = {0}; + DPP_ETM_CGAVD_SYS_TD_TH_T sys_td_th = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), level, QUEUE_LEVEL, SYS_LEVEL); + + q_avg_q_len_reg_index = ETM_CGAVD_FLOW_AVG_Q_LENr; + q_td_th_reg_index = ETM_CGAVD_FLOW_TD_THr; + q_ca_mtd_reg_index = ETM_CGAVD_FLOW_CA_MTDr; + pp_avg_q_len_reg_index = ETM_CGAVD_PP_AVG_Q_LENr; + pp_td_th_reg_index = ETM_CGAVD_PP_TD_THr; + pp_ca_mtd_reg_index = ETM_CGAVD_PP_CA_MTDr; + sys_avg_q_len_reg_index = ETM_CGAVD_SYS_AVG_Q_LENr; + sys_td_th_reg_index = ETM_CGAVD_SYS_TD_THr; + sys_ca_mtd_reg_index = ETM_CGAVD_SYS_CGAVD_METDr; + + + switch (level) + { + case (QUEUE_LEVEL): + { + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id, 0, DPP_ETM_Q_NUM - 1); + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), method, TD_METHOD, WRED_GRED_METHOD); + + if (1 == method) /* WRED算法，需要先配置平均队列深度，在选择wred算法 */ + { + rc = dpp_reg_read(dev, + q_avg_q_len_reg_index, + 0, + id, + &flow_avg_q_len); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + rc = dpp_reg_write(dev, + q_avg_q_len_reg_index, + 0, + id, + &flow_avg_q_len); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + } + + if (0 == method) /* TD算法，需要先配置尾部丢弃阈值，在选择TD算法 */ + { + rc = dpp_reg_read(dev, + q_td_th_reg_index, + 0, + id, + &q_td_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + + rc = dpp_reg_write(dev, + q_td_th_reg_index, + 0, + id, + &q_td_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + } + + /* 寄存器写入值,0-TD,1-WRED */ + q_cgavd_method.flow_ca_mtd = method; + rc = dpp_reg_write(dev, + q_ca_mtd_reg_index, + 0, + id, + &q_cgavd_method); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + break; + } + + case (PP_LEVEL): + { + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id, 0, DPP_TM_PP_NUM - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), method, TD_METHOD, WRED_GRED_METHOD); + + if (1 == method) /* WRED算法，需要先配置平均队列深度，在选择wred算法 */ + { + rc = dpp_reg_read(dev, + pp_avg_q_len_reg_index, + 0, + id, + &pp_avg_q_len); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + rc = dpp_reg_write(dev, + pp_avg_q_len_reg_index, + 0, + id, + &pp_avg_q_len); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + } + + if (0 == method) /* TD算法，尾部丢弃阈值，在选择TD算法 */ + { + rc = dpp_reg_read(dev, + pp_td_th_reg_index, + 0, + id, + &pp_td_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + rc = dpp_reg_write(dev, + pp_td_th_reg_index, + 0, + id, + &pp_td_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + } + + /* 寄存器写入值,0-TD,1-WRED */ + pp_cgavd_method.pp_ca_mtd = method; + rc = dpp_reg_write(dev, + pp_ca_mtd_reg_index, + 0, + id, + &pp_cgavd_method); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + + break; + } + + case (SYS_LEVEL): + { + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), method, TD_METHOD, WRED_GRED_METHOD); + + if (1 == method) /* GRED算法，需要先配置平均队列深度，在选择gred算法 */ + { + rc = dpp_reg_read(dev, + sys_avg_q_len_reg_index, + 0, + 0, + &sys_avg_q_len); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + rc = dpp_reg_write(dev, + sys_avg_q_len_reg_index, + 0, + 0, + &sys_avg_q_len); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + } + + if (0 == method) /* TD算法，尾部丢弃阈值，在选择TD算法 */ + { + rc = dpp_reg_read(dev, + sys_td_th_reg_index, + 0, + 0, + &sys_td_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + rc = dpp_reg_write(dev, + sys_td_th_reg_index, + 0, + 0, + &sys_td_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + } + + /* 寄存器写入值,0-TD,1-GRED */ + sys_cgavd_method.sys_cgavd_metd = method; + rc = dpp_reg_write(dev, + sys_ca_mtd_reg_index, + 0, + 0, + &sys_cgavd_method); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + break; + } + + default: + { + ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "method=%u error!\n", (method)); + return DPP_ERR; + } + } + + return DPP_OK; + +} + + +/***********************************************************/ +/** 读取拥塞避免算法 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param level 拥塞避免支持层次号，0:队列级，1:端口级，2:系统级 +* @param id 队列号或端口号,系统级时,id参数无效 +* @param p_method 配置的拥塞避免算法,0:TD,1:WRED/GRED +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/17 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_method_get(DPP_DEV_T *dev, + DPP_TM_CGAVD_LEVEL_E level, + ZXIC_UINT32 id, + DPP_TM_CGAVD_METHOD_E *p_method) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 q_ca_mtd_reg_index = 0; + ZXIC_UINT32 pp_ca_mtd_reg_index = 0; + ZXIC_UINT32 sys_ca_mtd_reg_index = 0; + + DPP_ETM_CGAVD_FLOW_CA_MTD_T q_cgavd_method = {0}; + DPP_ETM_CGAVD_PP_CA_MTD_T pp_cgavd_method = {0}; + DPP_ETM_CGAVD_SYS_CGAVD_METD_T sys_cgavd_method = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), level, QUEUE_LEVEL, SYS_LEVEL); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_method); + + *p_method = INVALID_METHOD; + + q_ca_mtd_reg_index = ETM_CGAVD_FLOW_CA_MTDr; + pp_ca_mtd_reg_index = ETM_CGAVD_PP_CA_MTDr; + sys_ca_mtd_reg_index = ETM_CGAVD_SYS_CGAVD_METDr; + + if (QUEUE_LEVEL == level) + { + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id, 0, DPP_ETM_Q_NUM - 1); + + rc = dpp_reg_read(dev, + q_ca_mtd_reg_index, + 0, + id, + &q_cgavd_method); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + *p_method = q_cgavd_method.flow_ca_mtd; + } + + else if (PP_LEVEL == level) + { + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id, 0, DPP_TM_PP_NUM - 1); + + rc = dpp_reg_read(dev, + pp_ca_mtd_reg_index, + 0, + id, + &pp_cgavd_method); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + *p_method = pp_cgavd_method.pp_ca_mtd; + } + + else + { + rc = dpp_reg_read(dev, + sys_ca_mtd_reg_index, + 0, + 0, + &sys_cgavd_method); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + *p_method = sys_cgavd_method.sys_cgavd_metd; + } + + return DPP_OK; +} + + +/***********************************************************/ +/** CPU设置的各级队列深度配置 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param level 拥塞避免支持层次号，0:队列级，1:端口级，2:系统级 +* @param q_len_use_cpu_set_en 0：选取RAM中读出的队列深度； +* @param 1：选取q_len_cpu_set值 +* @param q_len_cpu_set CPU设置的各级队列深度,单位为block。 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author yjd @date 2015/06/19 +************************************************************/ +DPP_STATUS dpp_tm_q_len_use_cpu_set(DPP_DEV_T *dev, + DPP_TM_CGAVD_LEVEL_E level, + ZXIC_UINT32 q_len_use_cpu_set_en, + ZXIC_UINT32 q_len_cpu_set) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 rd_cpu_or_ram_reg_index = 0; + ZXIC_UINT32 q_cpu_set_q_len_reg_index = 0; + ZXIC_UINT32 pp_cpu_set_q_len_reg_index = 0; + ZXIC_UINT32 sys_cpu_set_q_len_reg_index = 0; + + DPP_ETM_CGAVD_RD_CPU_OR_RAM_T len_use_cpu_set_en = {0}; + DPP_ETM_CGAVD_FLOW_CPU_SET_Q_LEN_T flow_q_len_cpu_set = {0}; + DPP_ETM_CGAVD_PP_CPU_SET_Q_LEN_T pp_q_len_cpu_set = {0}; + DPP_ETM_CGAVD_SYS_CPU_SET_Q_LEN_T sys_q_len_cpu_set = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), level, QUEUE_LEVEL, SYS_LEVEL); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), q_len_use_cpu_set_en, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), q_len_cpu_set, 0, 0x1ffffff); + + rd_cpu_or_ram_reg_index = ETM_CGAVD_RD_CPU_OR_RAMr; + q_cpu_set_q_len_reg_index = ETM_CGAVD_FLOW_CPU_SET_Q_LENr; + pp_cpu_set_q_len_reg_index = ETM_CGAVD_PP_CPU_SET_Q_LENr; + sys_cpu_set_q_len_reg_index = ETM_CGAVD_SYS_CPU_SET_Q_LENr; + + rc = dpp_reg_read(dev, + rd_cpu_or_ram_reg_index, + 0, + 0, + &len_use_cpu_set_en); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + switch (level) + { + case (QUEUE_LEVEL): + { + len_use_cpu_set_en.cpu_sel_flow_q_len_en = q_len_use_cpu_set_en; + rc = dpp_reg_write(dev, + rd_cpu_or_ram_reg_index, + 0, + 0, + &len_use_cpu_set_en); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + if (q_len_use_cpu_set_en == 1) + { + flow_q_len_cpu_set.flow_cpu_set_q_len = q_len_cpu_set; + rc = dpp_reg_write(dev, + q_cpu_set_q_len_reg_index, + 0, + 0, + &flow_q_len_cpu_set); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + } + + + break; + } + + case (PP_LEVEL): + { + len_use_cpu_set_en.cpu_sel_pp_q_len_en = q_len_use_cpu_set_en; + rc = dpp_reg_write(dev, + rd_cpu_or_ram_reg_index, + 0, + 0, + &len_use_cpu_set_en); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + if (q_len_use_cpu_set_en == 1) + { + pp_q_len_cpu_set.pp_cpu_set_q_len = q_len_cpu_set; + rc = dpp_reg_write(dev, + pp_cpu_set_q_len_reg_index, + 0, + 0, + &pp_q_len_cpu_set); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + } + + break; + } + + case (SYS_LEVEL): + { + len_use_cpu_set_en.cpu_sel_sys_q_len_en = q_len_use_cpu_set_en; + rc = dpp_reg_write(dev, + rd_cpu_or_ram_reg_index, + 0, + 0, + &len_use_cpu_set_en); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + if (q_len_use_cpu_set_en == 1) + { + sys_q_len_cpu_set.sys_cpu_set_q_len = q_len_cpu_set; + rc = dpp_reg_write(dev, + sys_cpu_set_q_len_reg_index, + 0, + 0, + &sys_q_len_cpu_set); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + } + + break; + } + + default: + { + ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "level=%u error!\n", level); + return DPP_ERR; + } + + } + + return DPP_OK; + +} + + +/***********************************************************/ +/** CPU设置的各级平均队列深度配置 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param level 拥塞避免支持层次号，0:队列级，1:端口级，2:系统级 +* @param q_avg_len_use_cpu_set_en 0：选取RAM中读出的队列深度； +* @param 1：选取q_avg_len_cpu_set值 +* @param q_avg_len_cpu_set CPU设置的各级平均队列深度。 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author yjd @date 2015/06/19 +************************************************************/ +DPP_STATUS dpp_tm_q_avg_len_use_cpu_set(DPP_DEV_T *dev, + DPP_TM_CGAVD_LEVEL_E level, + ZXIC_UINT32 q_avg_len_use_cpu_set_en, + ZXIC_UINT32 q_avg_len_cpu_set) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 rd_cpu_or_ram_reg_index = 0; + ZXIC_UINT32 q_cpu_set_avg_len_reg_index = 0; + ZXIC_UINT32 pp_cpu_set_avg_len_reg_index = 0; + ZXIC_UINT32 sys_cpu_set_avg_len_reg_index = 0; + + DPP_ETM_CGAVD_RD_CPU_OR_RAM_T avg_len_use_cpu_set_en = {0}; + DPP_ETM_CGAVD_FLOW_CPU_SET_AVG_LEN_T flow_q_avg_len_cpu_set = {0}; + DPP_ETM_CGAVD_PP_CPU_SET_AVG_Q_LEN_T pp_q_avg_len_cpu_set = {0}; + DPP_ETM_CGAVD_SYS_CPU_SET_AVG_LEN_T sys_q_avg_len_cpu_set = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), level, QUEUE_LEVEL, SYS_LEVEL); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), q_avg_len_use_cpu_set_en, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), q_avg_len_cpu_set, 0, 0x1ffffff); + + rd_cpu_or_ram_reg_index = ETM_CGAVD_RD_CPU_OR_RAMr; + q_cpu_set_avg_len_reg_index = ETM_CGAVD_FLOW_CPU_SET_AVG_LENr; + pp_cpu_set_avg_len_reg_index = ETM_CGAVD_PP_CPU_SET_AVG_Q_LENr; + sys_cpu_set_avg_len_reg_index = ETM_CGAVD_SYS_CPU_SET_AVG_LENr; + + rc = dpp_reg_read(dev, + rd_cpu_or_ram_reg_index, + 0, + 0, + &avg_len_use_cpu_set_en); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + switch (level) + { + case (QUEUE_LEVEL): + { + avg_len_use_cpu_set_en.cpu_sel_flow_avg_q_len_en = q_avg_len_use_cpu_set_en; + rc = dpp_reg_write(dev, + rd_cpu_or_ram_reg_index, + 0, + 0, + &avg_len_use_cpu_set_en); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + if (q_avg_len_use_cpu_set_en == 1) + { + flow_q_avg_len_cpu_set.flow_cpu_set_avg_len = q_avg_len_cpu_set; + rc = dpp_reg_write(dev, + q_cpu_set_avg_len_reg_index, + 0, + 0, + &flow_q_avg_len_cpu_set); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + } + + break; + } + + case (PP_LEVEL): + { + avg_len_use_cpu_set_en.cpu_sel_pp_avg_q_len_en = q_avg_len_use_cpu_set_en; + rc = dpp_reg_write(dev, + rd_cpu_or_ram_reg_index, + 0, + 0, + &avg_len_use_cpu_set_en); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + if (q_avg_len_use_cpu_set_en == 1) + { + pp_q_avg_len_cpu_set.pp_cpu_set_avg_q_len = q_avg_len_cpu_set; + rc = dpp_reg_write(dev, + pp_cpu_set_avg_len_reg_index, + 0, + 0, + &pp_q_avg_len_cpu_set); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + } + + break; + } + + case (SYS_LEVEL): + { + avg_len_use_cpu_set_en.cpu_sel_sys_avg_q_len_en = q_avg_len_use_cpu_set_en; + rc = dpp_reg_write(dev, + rd_cpu_or_ram_reg_index, + 0, + 0, + &avg_len_use_cpu_set_en); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + if (q_avg_len_use_cpu_set_en == 1) + { + sys_q_avg_len_cpu_set.sys_cpu_set_avg_len = q_avg_len_cpu_set; + rc = dpp_reg_write(dev, + sys_cpu_set_avg_len_reg_index, + 0, + 0, + &sys_q_avg_len_cpu_set); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + } + + break; + } + + default: + { + ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "level=%u error!\n", level); + return DPP_ERR; + } + + } + + return DPP_OK; + +} + + +/***********************************************************/ +/** 流队列级队列深度的获取 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param que_id 队列号 +* p_len 队列深度以KB为单位 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author yjd @date 2015/06/19 +************************************************************/ +DPP_STATUS dpp_tm_flow_que_len_get(DPP_DEV_T *dev, + ZXIC_UINT32 que_id, + ZXIC_UINT32 *p_len) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 blk_size = 0; + ZXIC_UINT32 cgavd_cfg_mode = 0; + + DPP_ETM_CGAVD_FLOW_Q_LEN_T dpp_tm_flow_len = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_len); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), que_id, 0, DPP_ETM_Q_NUM - 1); + + rc = dpp_reg_read(dev, + ETM_CGAVD_FLOW_Q_LENr, + 0, + que_id, + &dpp_tm_flow_len); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + rc = dpp_tm_cgavd_cfg_mode_get(dev, &cgavd_cfg_mode); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_cgavd_cfg_mode_get"); + + if (cgavd_cfg_mode == DPP_TM_CGAVD_BLOCK_MODE) + { + rc = dpp_tm_cfgmt_blk_size_get(dev, &blk_size); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_cfgmt_blk_size_get"); + + *p_len = ((dpp_tm_flow_len.flow_q_len * blk_size) / DPP_TM_CGAVD_KILO_UL); + } + else if (cgavd_cfg_mode == DPP_TM_CGAVD_ZXIC_UINT8_MODE) + { + *p_len = ((dpp_tm_flow_len.flow_q_len) / DPP_TM_CGAVD_KILO_UL); + } + else + { + ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "dpp_tm_flow_que_len_get:cgavd_cfg_mode is err!!\n"); + return DPP_ERR; + } + + return DPP_OK; +} + +#if 0 +/***********************************************************/ +/** 端口级队列深度的获取 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param pp_id 队列号 +* pp_len 队列深度以KB为单位 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author yjd @date 2015/06/19 +************************************************************/ +DPP_STATUS dpp_tm_port_que_len_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 pp_id, + ZXIC_UINT32 *pp_len) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 blk_size = 0; + DPP_ETM_CGAVD_PP_Q_LEN_T dpp_tm_pp_len = {0}; + ZXIC_UINT32 cgavd_cfg_mode = 0; + + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, pp_len); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pp_id, 0, DPP_TM_PP_NUM - 1); + + rc = dpp_reg_read(dev_id, + ETM_CGAVD_FLOW_Q_LENr, + 0, + pp_id, + &dpp_tm_pp_len); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + rc = dpp_tm_cgavd_cfg_mode_get(dev_id, &cgavd_cfg_mode); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_cfg_mode_get"); + + if (cgavd_cfg_mode == DPP_TM_CGAVD_BLOCK_MODE) + { + rc = dpp_tm_cfgmt_blk_size_get(dev_id, &blk_size); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_blk_size_get"); + + *pp_len = ((dpp_tm_pp_len.pp_q_len * blk_size) / DPP_TM_CGAVD_KILO_UL); + } + else if (cgavd_cfg_mode == DPP_TM_CGAVD_ZXIC_UINT8_MODE) + { + *pp_len = ((dpp_tm_pp_len.pp_q_len) / DPP_TM_CGAVD_KILO_UL); + } + else + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "dpp_tm_port_que_len_get err!!\n"); + return DPP_ERR; + } + + return DPP_OK; +} + + +/***********************************************************/ +/** 系统级队列深度的获取 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param sys_len 系统级深度以block为单位 +* sys_protocol_len 系统级包含协议队列深度以KB为单位 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author yjd @date 2015/06/19 +************************************************************/ +DPP_STATUS dpp_tm_sys_que_len_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *sys_len, + ZXIC_UINT32 *sys_protocol_len) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 blk_size = 0; + ZXIC_UINT32 sys_q_len_reg_index = 0; + ZXIC_UINT32 sys_q_len_l_reg_index = 0; + DPP_ETM_CGAVD_SYS_Q_LEN_T dpp_tm_sys_len = {0}; + DPP_ETM_CGAVD_CGAVD_SYS_Q_LEN_L_T dpp_tm_sys_protocol_len = {0}; + ZXIC_UINT32 cgavd_cfg_mode = 0; + + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, sys_protocol_len); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, sys_len); + + sys_q_len_reg_index = ETM_CGAVD_SYS_Q_LENr; + sys_q_len_l_reg_index = ETM_CGAVD_CGAVD_SYS_Q_LEN_Lr; + + rc = dpp_reg_read(dev_id, + sys_q_len_reg_index, + 0, + 0, + &dpp_tm_sys_len); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + rc = dpp_reg_read(dev_id, + sys_q_len_l_reg_index, + 0, + 0, + &dpp_tm_sys_protocol_len); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + rc = dpp_tm_cgavd_cfg_mode_get(dev_id, &cgavd_cfg_mode); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_cfg_mode_get"); + + if (cgavd_cfg_mode == DPP_TM_CGAVD_BLOCK_MODE) + { + rc = dpp_tm_cfgmt_blk_size_get(dev_id, &blk_size); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_blk_size_get"); + + *sys_len = ((dpp_tm_sys_len.sys_q_len * blk_size) / DPP_TM_CGAVD_KILO_UL); + *sys_protocol_len = ((dpp_tm_sys_protocol_len.cgavd_sys_q_len_l * blk_size) / DPP_TM_CGAVD_KILO_UL); + } + else if (cgavd_cfg_mode == DPP_TM_CGAVD_ZXIC_UINT8_MODE) + { + *sys_len = ((dpp_tm_sys_len.sys_q_len) / DPP_TM_CGAVD_KILO_UL); + *sys_protocol_len = ((dpp_tm_sys_protocol_len.cgavd_sys_q_len_l) / DPP_TM_CGAVD_KILO_UL); + } + else + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "dpp_tm_sys_que_len_get err!!\n"); + return DPP_ERR; + } + + return DPP_OK; + +} + +#endif + +/***********************************************************/ +/** 配置TD拥塞避免模式下的丢弃门限值 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param level 拥塞避免支持层次号，0:队列级，1:端口级，2:系统级 +* @param id 队列号或端口号，系统级时，id参数无效 +* @param byte_block_th 配置的丢弃门限值，ZXIC_UINT8/BLOCK单位写入寄存器 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cy @date 2016/07/29 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_td_byte_block_th_set(DPP_DEV_T *dev, + DPP_TM_CGAVD_LEVEL_E level, + ZXIC_UINT32 id, + ZXIC_UINT32 byte_block_th) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 q_td_th_reg_index = 0; + ZXIC_UINT32 q_ca_mtd_reg_index = 0; + ZXIC_UINT32 pp_td_th_reg_index = 0; + ZXIC_UINT32 pp_ca_mtd_reg_index = 0; + ZXIC_UINT32 sys_td_th_reg_index = 0; + ZXIC_UINT32 sys_ca_mtd_reg_index = 0; + ZXIC_UINT32 read_times = 50; + DPP_ETM_CGAVD_FLOW_CA_MTD_T q_cgavd_method = {0}; + DPP_ETM_CGAVD_FLOW_TD_TH_T q_td_th = {0}; + DPP_ETM_CGAVD_PP_CA_MTD_T pp_cgavd_method = {0}; + DPP_ETM_CGAVD_PP_TD_TH_T pp_td_th = {0}; + DPP_ETM_CGAVD_SYS_CGAVD_METD_T sys_cgavd_method = {0}; + DPP_ETM_CGAVD_SYS_TD_TH_T sys_td_th = {0}; + ZXIC_UINT32 qlist_clr_done_flag = 0; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), level, QUEUE_LEVEL, SYS_LEVEL); + + q_td_th_reg_index = ETM_CGAVD_FLOW_TD_THr; + q_ca_mtd_reg_index = ETM_CGAVD_FLOW_CA_MTDr; + pp_td_th_reg_index = ETM_CGAVD_PP_TD_THr; + pp_ca_mtd_reg_index = ETM_CGAVD_PP_CA_MTDr; + sys_td_th_reg_index = ETM_CGAVD_SYS_TD_THr; + sys_ca_mtd_reg_index = ETM_CGAVD_SYS_CGAVD_METDr; + + if (QUEUE_LEVEL == level) + { + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id, 0, DPP_ETM_Q_NUM - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), byte_block_th, 0, 0x1fffffff); + + q_td_th.flow_td_th = byte_block_th; + rc = dpp_reg_write(dev, + q_td_th_reg_index, + 0, + id, + &q_td_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + q_cgavd_method.flow_ca_mtd = TD_METHOD; + + rc = dpp_reg_write(dev, + q_ca_mtd_reg_index, + 0, + id, + &q_cgavd_method); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + /* add by zhmy begin@20151103 */ + if (byte_block_th == 0) + { + do + { + rc = dpp_tm_qmu_qlist_qcfg_clr_done_get(dev, &qlist_clr_done_flag); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_qmu_qlist_qcfg_clr_done_get"); + + read_times--; + + if (1 == qlist_clr_done_flag) + { + break; + } + + zxic_comm_delay(10); + } + while (read_times > 0); + + if (read_times == 0) + { + ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "dpp_tm_qmu_qlist_qcfg_clr_done_get time out\n"); + return DPP_ERR; + } + + } + + /* add by zhmy end@20151103 */ + } + + else if (PP_LEVEL == level) + { + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id, 0, DPP_TM_PP_NUM - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), byte_block_th, 0, 0x1fffffff); + + pp_td_th.pp_td_th = byte_block_th; + rc = dpp_reg_write(dev, + pp_td_th_reg_index, + 0, + id, + &pp_td_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + pp_cgavd_method.pp_ca_mtd = TD_METHOD; + rc = dpp_reg_write(dev, + pp_ca_mtd_reg_index, + 0, + id, + &pp_cgavd_method); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + } + + else + { + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), byte_block_th, 0, 0x1fffffff); + + sys_td_th.sys_td_th = byte_block_th; + rc = dpp_reg_write(dev, + sys_td_th_reg_index, + 0, + 0, + &sys_td_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + sys_cgavd_method.sys_cgavd_metd = TD_METHOD; + + rc = dpp_reg_write(dev, + sys_ca_mtd_reg_index, + 0, + 0, + &sys_cgavd_method); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + } + + return DPP_OK; + +} + + +/***********************************************************/ +/** 配置TD拥塞避免模式下的丢弃门限值 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param level 拥塞避免支持层次号，0:队列级，1:端口级，2:系统级 +* @param id 队列号或端口号，系统级时，id参数无效 +* @param td_th 配置的丢弃门限值，用户配置门限值单位为Kbyte，需要转化为Block或者ZXIC_UINT8单位写入寄存器 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cy @date 2016/07/29 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_td_th_set(DPP_DEV_T *dev, + DPP_TM_CGAVD_LEVEL_E level, + ZXIC_UINT32 id, + ZXIC_UINT32 td_th) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 blk_size = 0; + ZXIC_UINT32 blk_th = 0; + ZXIC_UINT32 cgavd_cfg_mode = 0; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), level, QUEUE_LEVEL, SYS_LEVEL); + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), td_th, 0, 512*1024); + + td_th = (ZXIC_UINT32)(td_th * DPP_TM_CGAVD_KILO_UL); + + rc = dpp_tm_cgavd_cfg_mode_get(dev, &cgavd_cfg_mode); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_cgavd_cfg_mode_get"); + + if (cgavd_cfg_mode == DPP_TM_CGAVD_BLOCK_MODE) + { + rc = dpp_tm_cfgmt_blk_size_get(dev, &blk_size); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_cfgmt_blk_size_get"); + + if (blk_size != 0) + { + blk_th = (td_th / blk_size); + blk_th = (td_th % blk_size == 0) ? (blk_th ) : ((blk_th) + 1); + } + + rc = dpp_tm_cgavd_td_byte_block_th_set(dev, level, id, blk_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_cgavd_td_byte_block_th_set"); + } + else if (cgavd_cfg_mode == DPP_TM_CGAVD_ZXIC_UINT8_MODE) + { + rc = dpp_tm_cgavd_td_byte_block_th_set(dev, level, id, td_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_cgavd_td_byte_block_th_set"); + } + else + { + ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "dpp_tm_cgavd_td_th_set err!!\n"); + return DPP_ERR; + } + + return DPP_OK; + +} + + +/***********************************************************/ +/** 读取TD拥塞避免模式下的丢弃门限值 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param level 拥塞避免支持层次号，0:队列级，1:端口级，2:系统级 +* @param id 队列号或端口号，系统级时，id参数无效 +* @param p_byte_block_th 配置的丢弃门限值ZXIC_UINT8/BLOCK单位 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cy @date 2016/07/29 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_td_byte_block_th_get(DPP_DEV_T *dev, + DPP_TM_CGAVD_LEVEL_E level, + ZXIC_UINT32 id, + ZXIC_UINT32 *p_byte_block_th) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 q_td_th_reg_index = 0; + ZXIC_UINT32 pp_td_th_reg_index = 0; + ZXIC_UINT32 sys_td_th_reg_index = 0; + DPP_ETM_CGAVD_FLOW_TD_TH_T q_td_th = {0}; + DPP_ETM_CGAVD_PP_TD_TH_T pp_td_th = {0}; + DPP_ETM_CGAVD_SYS_TD_TH_T sys_td_th = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), level, QUEUE_LEVEL, SYS_LEVEL); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_byte_block_th); + + + if (QUEUE_LEVEL == level) + { + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id, 0, DPP_ETM_Q_NUM - 1); + } + + else if (PP_LEVEL == level) + { + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id, 0, DPP_TM_PP_NUM - 1); + } + + else + { + ZXIC_COMM_PRINT("sys:id is not to be checked!!\n"); + } + + q_td_th_reg_index = ETM_CGAVD_FLOW_TD_THr; + pp_td_th_reg_index = ETM_CGAVD_PP_TD_THr; + sys_td_th_reg_index = ETM_CGAVD_SYS_TD_THr; + + if (QUEUE_LEVEL == level) + { + rc = dpp_reg_read(dev, + q_td_th_reg_index, + 0, + id, + &q_td_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + *p_byte_block_th = q_td_th.flow_td_th; + } + + else if (PP_LEVEL == level) + { + rc = dpp_reg_read(dev, + pp_td_th_reg_index, + 0, + id, + &pp_td_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + *p_byte_block_th = pp_td_th.pp_td_th; + } + + else + { + rc = dpp_reg_read(dev, + sys_td_th_reg_index, + 0, + 0, + &sys_td_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + *p_byte_block_th = sys_td_th.sys_td_th; + } + + return DPP_OK; + +} + + +/***********************************************************/ +/** 读取TD拥塞避免模式下的丢弃门限值 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param level 拥塞避免支持层次号，0:队列级，1:端口级，2:系统级 +* @param id 队列号或端口号，系统级时，id参数无效 +* @param p_td_th 配置的丢弃门限值KZXIC_UINT8单位 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cy @date 2016/07/29 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_td_th_get(DPP_DEV_T *dev, + DPP_TM_CGAVD_LEVEL_E level, + ZXIC_UINT32 id, + ZXIC_UINT32 *p_td_th) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 cgavd_cfg_mode = 0; + ZXIC_UINT32 block_byte_th = 0; + ZXIC_UINT32 blk_size = 0; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), level, QUEUE_LEVEL, SYS_LEVEL); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_td_th); + + *p_td_th = 0; + + if (QUEUE_LEVEL == level) + { + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id, 0, DPP_ETM_Q_NUM - 1); + } + + else if (PP_LEVEL == level) + { + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id, 0, DPP_TM_PP_NUM - 1); + } + + else + { + ZXIC_COMM_PRINT("sys:id is not to be checked!!\n"); + } + + rc = dpp_tm_cgavd_td_byte_block_th_get(dev, level, id, &block_byte_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_cgavd_td_byte_block_th_get"); + + rc = dpp_tm_cgavd_cfg_mode_get(dev, &cgavd_cfg_mode); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_cgavd_cfg_mode_get"); + + if (cgavd_cfg_mode == DPP_TM_CGAVD_BLOCK_MODE) + { + rc = dpp_tm_cfgmt_blk_size_get(dev, &blk_size); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_cfgmt_blk_size_get"); + + *p_td_th = (block_byte_th * blk_size) / DPP_TM_CGAVD_KILO_UL; + } + else if (cgavd_cfg_mode == DPP_TM_CGAVD_ZXIC_UINT8_MODE) + { + *p_td_th = (block_byte_th / DPP_TM_CGAVD_KILO_UL); + } + else + { + ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "dpp_tm_cgavd_td_th_get err!!\n"); + return DPP_ERR; + } + + return DPP_OK; + +} + +#if 0 +/***********************************************************/ +/** 配置指定端口或队列绑定的WRED GROUP ID +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param level WRED支持层次号，0:队列级，1:端口级 +* @param id 队列号或端口号 +* @param wred_id 配置的WRED GROUP ID +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/17 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_wred_id_set(ZXIC_UINT32 dev_id, + DPP_TM_CGAVD_LEVEL_E level, + ZXIC_UINT32 id, + ZXIC_UINT32 wred_id) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 q_wred_grp_reg_index = 0; + ZXIC_UINT32 pp_wrd_grp_th_en_reg_index = 0; + + DPP_ETM_CGAVD_FLOW_WRED_GRP_T q_wred_group = {0}; + DPP_ETM_CGAVD_PP_WRED_GRP_TH_EN_T pp_wred_group = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, level, QUEUE_LEVEL, PP_LEVEL); + + q_wred_grp_reg_index = ETM_CGAVD_FLOW_WRED_GRPr; + pp_wrd_grp_th_en_reg_index = ETM_CGAVD_PP_WRED_GRP_TH_ENr; + + if (QUEUE_LEVEL == level) + { + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, id, 0, DPP_ETM_Q_NUM - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, wred_id, 0, DPP_TM_Q_WRED_NUM - 1); + + q_wred_group.flow_wred_grp = wred_id; + rc = dpp_reg_write(dev_id, + q_wred_grp_reg_index, + 0, + id, + &q_wred_group); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + else + { + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, id, 0, DPP_TM_PP_NUM - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, wred_id, 0, DPP_TM_PP_WRED_NUM - 1); + + rc = dpp_reg_read(dev_id, + pp_wrd_grp_th_en_reg_index, + 0, + id, + &pp_wred_group); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + pp_wred_group.pp_wred_grp = wred_id; + rc = dpp_reg_write(dev_id, + pp_wrd_grp_th_en_reg_index, + 0, + id, + &pp_wred_group); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + return DPP_OK; + +} + + +/***********************************************************/ +/** 读取指定端口或队列绑定的WRED GROUP ID +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param level WRED支持层次号，0:队列级，1:端口级 +* @param id 队列号或端口号 +* @param p_wred_id 配置的WRED GROUP ID +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/17 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_wred_id_get(ZXIC_UINT32 dev_id, + DPP_TM_CGAVD_LEVEL_E level, + ZXIC_UINT32 id, + ZXIC_UINT32 *p_wred_id) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 q_wred_grp_reg_index = 0; + ZXIC_UINT32 pp_wrd_grp_th_en_reg_index = 0; + + DPP_ETM_CGAVD_FLOW_WRED_GRP_T q_wred_group = {0}; + DPP_ETM_CGAVD_PP_WRED_GRP_TH_EN_T pp_wred_group = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, level, QUEUE_LEVEL, PP_LEVEL); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_wred_id); + + q_wred_grp_reg_index = ETM_CGAVD_FLOW_WRED_GRPr; + pp_wrd_grp_th_en_reg_index = ETM_CGAVD_PP_WRED_GRP_TH_ENr; + + if (QUEUE_LEVEL == level) + { + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, id, 0, DPP_ETM_Q_NUM - 1); + rc = dpp_reg_read(dev_id, + q_wred_grp_reg_index, + 0, + id, + &q_wred_group); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + *p_wred_id = q_wred_group.flow_wred_grp; + } + + else + { + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, id, 0, DPP_TM_PP_NUM - 1); + rc = dpp_reg_read(dev_id, + pp_wrd_grp_th_en_reg_index, + 0, + id, + &pp_wred_group); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + *p_wred_id = pp_wred_group.pp_wred_grp; + } + + return DPP_OK; + +} + + +/***********************************************************/ +/** 配置WRED丢弃曲线对应的参数 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param level WRED支持层次号，0:队列级，1:端口级 +* @param wred_id 队列级共支持16个WRED组0-15，端口级支持8组0-7 +* @param dp 共支持8个dp，取值0-7 +* @param p_para 配置的WRED组参数值，包含以下五个参数 + max_th 平均队列深度上限阈值ZXIC_UINT8/BLOCK单位 + min_th 平均队列深度下限阈值ZXIC_UINT8/BLOCK单位 + max_p 最大丢弃概率 + weight 平均队列深度计算权重 + q_len_th 队列深度阈值ZXIC_UINT8/BLOCK单位 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cy @date 2016/08/01 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_wred_dp_line_block_byte_para_set(ZXIC_UINT32 dev_id, + DPP_TM_CGAVD_LEVEL_E level, + ZXIC_UINT32 wred_id, + ZXIC_UINT32 dp, + DPP_TM_WRED_DP_LINE_PARA_T *p_para) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 index = 0; + ZXIC_UINT32 q_wred_max_th_reg_index = 0; + ZXIC_UINT32 q_wred_min_th_reg_index = 0; + ZXIC_UINT32 q_wred_cfg_para_reg_index = 0; + ZXIC_UINT32 q_wq_reg_index = 0; + ZXIC_UINT32 q_wred_len_th_reg_index = 0; + + ZXIC_UINT32 pp_wred_max_th_reg_index = 0; + ZXIC_UINT32 pp_wred_min_th_reg_index = 0; + ZXIC_UINT32 pp_wred_cfg_para_reg_index = 0; + ZXIC_UINT32 pp_wq_reg_index = 0; + ZXIC_UINT32 pp_wred_len_th_reg_index = 0; + + DPP_ETM_CGAVD_FLOW_WRED_MAX_TH_T q_max_th = {0}; + DPP_ETM_CGAVD_FLOW_WRED_MIN_TH_T q_min_th = {0}; + DPP_ETM_CGAVD_FLOW_WRED_CFG_PARA_T q_cfg_para = {0}; + DPP_ETM_CGAVD_FLOW_WQ_T q_wq = {0}; + DPP_ETM_CGAVD_FLOW_WRED_Q_LEN_TH_T q_len_th = {0}; + DPP_ETM_CGAVD_PP_WRED_MAX_TH_T pp_max_th = {0}; + DPP_ETM_CGAVD_PP_WRED_MIN_TH_T pp_min_th = {0}; + DPP_ETM_CGAVD_PP_CFG_PARA_T pp_cfg_para = {0}; + DPP_ETM_CGAVD_PP_WQ_T pp_wq = {0}; + DPP_ETM_CGAVD_PP_WRED_Q_LEN_TH_T pp_len_th = {0}; + + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, level, QUEUE_LEVEL, PP_LEVEL); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, dp, 0, DPP_TM_DP_NUM - 1); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_para); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, p_para->max_p, 1, DPP_TM_RED_P_MAX); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, p_para->weight, 0, DPP_TM_CGAVD_WEIGHT_MAX); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, p_para->max_th, 0, 0x1fffffff); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, p_para->min_th, 0, 0x1fffffff); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, p_para->q_len_th, 0, 0x1fffffff); + + q_wred_max_th_reg_index = ETM_CGAVD_FLOW_WRED_MAX_THr; + q_wred_min_th_reg_index = ETM_CGAVD_FLOW_WRED_MIN_THr; + q_wred_cfg_para_reg_index = ETM_CGAVD_FLOW_WRED_CFG_PARAr; + q_wq_reg_index = ETM_CGAVD_FLOW_WQr; + q_wred_len_th_reg_index = ETM_CGAVD_FLOW_WRED_Q_LEN_THr; + + pp_wred_max_th_reg_index = ETM_CGAVD_PP_WRED_MAX_THr; + pp_wred_min_th_reg_index = ETM_CGAVD_PP_WRED_MIN_THr; + pp_wred_cfg_para_reg_index = ETM_CGAVD_PP_CFG_PARAr; + pp_wq_reg_index = ETM_CGAVD_PP_WQr; + pp_wred_len_th_reg_index = ETM_CGAVD_PP_WRED_Q_LEN_THr; + + ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW(wred_id, DPP_TM_DP_NUM); + index = wred_id * DPP_TM_DP_NUM + dp; + + if (QUEUE_LEVEL == level) + { + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, wred_id, 0, DPP_TM_Q_WRED_NUM - 1); + + /* q_max_th */ + q_max_th.flow_wred_max_th = p_para->max_th; + rc = dpp_reg_write(dev_id, + q_wred_max_th_reg_index, + 0, + index, + &q_max_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + /* q_min_th */ + q_min_th.flow_wred_min_th = p_para->min_th; + rc = dpp_reg_write(dev_id, + q_wred_min_th_reg_index, + 0, + index, + &q_min_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + /* q_cfg_para，乘以100用来换算百分比，用户配置的是值是1-100 */ + if (p_para->max_p != 0) + { + ZXIC_COMM_CHECK_DEV_INDEX_SUB_OVERFLOW_NO_ASSERT(dev_id, q_max_th.flow_wred_max_th+1 , q_min_th.flow_wred_min_th); + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, 100 , (q_max_th.flow_wred_max_th - q_min_th.flow_wred_min_th)); + q_cfg_para.flow_wred_cfg_para = (ZXIC_UINT32)(100 * (q_max_th.flow_wred_max_th - q_min_th.flow_wred_min_th) / p_para->max_p); + } + else + { + q_cfg_para.flow_wred_cfg_para = DPP_TM_Q_WRED_MAX_CFG_PARA; + } + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, q_cfg_para.flow_wred_cfg_para, 0, 0xffffffff); + + rc = dpp_reg_write(dev_id, + q_wred_cfg_para_reg_index, + 0, + index, + &q_cfg_para); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + /* 必须先写q_wq */ + q_wq.wq_flow = p_para->weight; + rc = dpp_reg_write(dev_id, + q_wq_reg_index, + 0, + wred_id, + &q_wq); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + /* 再写q_len_th */ + q_len_th.flow_wred_q_len_th = p_para->q_len_th; + rc = dpp_reg_write(dev_id, + q_wred_len_th_reg_index, + 0, + wred_id, + &q_len_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + else + { + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, wred_id, 0, DPP_TM_PP_WRED_NUM - 1); + + /* pp_max_th */ + pp_max_th.pp_wred_max_th = p_para->max_th; + rc = dpp_reg_write(dev_id, + pp_wred_max_th_reg_index, + 0, + index, + &pp_max_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + /* pp_min_th */ + pp_min_th.pp_wred_min_th = p_para->min_th; + rc = dpp_reg_write(dev_id, + pp_wred_min_th_reg_index, + 0, + index, + &pp_min_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + /* pp_cfg_para，乘以100用来换算百分比，用户配置的是值是1-100 */ + if (p_para->max_p != 0) + { + ZXIC_COMM_CHECK_DEV_INDEX_SUB_OVERFLOW_NO_ASSERT(dev_id, pp_max_th.pp_wred_max_th+1 , pp_min_th.pp_wred_min_th); + pp_cfg_para.pp_cfg_para = (ZXIC_UINT32)(100 * (pp_max_th.pp_wred_max_th - pp_min_th.pp_wred_min_th) / p_para->max_p); + } + else + { + pp_cfg_para.pp_cfg_para = DPP_TM_PP_WRED_MAX_CFG_PARA; + } + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pp_cfg_para.pp_cfg_para, 0, 0xffffffff); + + rc = dpp_reg_write(dev_id, + pp_wred_cfg_para_reg_index, + 0, + index, + &pp_cfg_para); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + /* 必须先写pp_len_th */ + pp_len_th.pp_wred_q_len_th = p_para->q_len_th; + rc = dpp_reg_write(dev_id, + pp_wred_len_th_reg_index, + 0, + wred_id, + &pp_len_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + /* 再写pp_wq */ + pp_wq.wq_pp = p_para->weight; + rc = dpp_reg_write(dev_id, + pp_wq_reg_index, + 0, + wred_id, + &pp_wq); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + return DPP_OK; + +} + + +/***********************************************************/ +/** 配置WRED丢弃曲线对应的参数 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param level WRED支持层次号，0:队列级，1:端口级 +* @param wred_id 队列级共支持16个WRED组0-15，端口级支持8组0-7 +* @param dp 共支持8个dp，取值0-7 +* @param p_para 配置的WRED组参数值，用户配置门限值单位为Kbyte，需要转化为Block或者ZXIC_UINT8单位写入寄存器 + 包含以下五个参数 + max_th 平均队列深度上限阈值 + min_th 平均队列深度下限阈值 + max_p 最大丢弃概率 + weight 平均队列深度计算权重 + q_len_th 队列深度阈值 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cy @date 2016/08/01 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_wred_dp_line_para_set(ZXIC_UINT32 dev_id, + DPP_TM_CGAVD_LEVEL_E level, + ZXIC_UINT32 wred_id, + ZXIC_UINT32 dp, + DPP_TM_WRED_DP_LINE_PARA_T *p_para) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 cgavd_cfg_mode = 0; + ZXIC_UINT32 blk_size = 0; + DPP_TM_WRED_DP_LINE_PARA_T para = {0}; + + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, level, QUEUE_LEVEL, PP_LEVEL); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, dp, 0, DPP_TM_DP_NUM - 1); + + if (QUEUE_LEVEL == level) + { + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, wred_id, 0, DPP_TM_Q_WRED_NUM - 1); + } + else + { + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, wred_id, 0, DPP_TM_PP_WRED_NUM - 1); + } + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_para); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, p_para->max_p, 1, DPP_TM_RED_P_MAX); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, p_para->weight, 0, DPP_TM_CGAVD_WEIGHT_MAX); + + p_para->max_th = p_para->max_th * DPP_TM_CGAVD_KILO_UL; + p_para->min_th = p_para->min_th * DPP_TM_CGAVD_KILO_UL; + + if ((p_para->q_len_th) * DPP_TM_CGAVD_KILO_UL > 0x1fffffff) + { + p_para->q_len_th = 0x1fffffff; + }else{ + p_para->q_len_th = (ZXIC_UINT32)(p_para->q_len_th) * DPP_TM_CGAVD_KILO_UL; + } + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, p_para->max_th, p_para->min_th, 0x1fffffff); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, p_para->min_th, 0, 0x1fffffff); + + para.max_p = p_para->max_p; + para.weight = p_para->weight; + + if (p_para->max_th == p_para->min_th) + { + para.weight = 0; + } + + rc = dpp_tm_cgavd_cfg_mode_get(dev_id, &cgavd_cfg_mode); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_cfg_mode_get"); + + if (cgavd_cfg_mode == DPP_TM_CGAVD_BLOCK_MODE) + { + rc = dpp_tm_cfgmt_blk_size_get(dev_id, &blk_size); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_blk_size_get"); + + if (blk_size != 0) + { + para.max_th = ((p_para->max_th ) / blk_size); + para.max_th = ((p_para->max_th) % blk_size == 0) ? (para.max_th ) : ((para.max_th) + 1); + para.min_th = ((p_para->min_th ) / blk_size); + para.min_th = ((p_para->min_th) % blk_size == 0) ? (para.min_th ) : ((para.min_th) + 1); + para.q_len_th = ((p_para->q_len_th ) / blk_size); + para.q_len_th = ((p_para->q_len_th) % blk_size == 0) ? (para.q_len_th ) : ((para.q_len_th) + 1); + } + + } + else if (cgavd_cfg_mode == DPP_TM_CGAVD_ZXIC_UINT8_MODE) + { + para.max_th = p_para->max_th; + para.min_th = p_para->min_th; + para.q_len_th = p_para->q_len_th; + } + else + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "dpp_tm_cgavd_wred_dp_line_para_set err!!\n"); + return DPP_ERR; + } + + rc = dpp_tm_cgavd_wred_dp_line_block_byte_para_set(dev_id, level, wred_id, dp, ¶); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_wred_dp_line_block_byte_para_set"); + + return DPP_OK; + +} + + +/***********************************************************/ +/** 读取WRED丢弃曲线对应的参数 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param level WRED支持层次号，0:队列级，1:端口级 +* @param wred_id 队列级共支持16个WRED组0-15，端口级支持8组0-7 +* @param dp 共支持8个dp，取值0-7 +* @param p_para 配置的WRED组参数值，包含以下五个参数 + max_th 平均队列深度上限阈值ZXIC_UINT8/BLOCK单位 + min_th 平均队列深度下限阈值ZXIC_UINT8/BLOCK单位 + max_p 最大丢弃概率 + weight 平均队列深度计算权重 + q_len_th 队列深度阈值ZXIC_UINT8/BLOCK单位 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cy @date 2016/08/01 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_wred_dp_line_block_byte_para_get(ZXIC_UINT32 dev_id, + DPP_TM_CGAVD_LEVEL_E level, + ZXIC_UINT32 wred_id, + ZXIC_UINT32 dp, + DPP_TM_WRED_DP_LINE_PARA_T *p_para) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 index = 0; + ZXIC_UINT32 q_wred_max_th_reg_index = 0; + ZXIC_UINT32 q_wred_min_th_reg_index = 0; + ZXIC_UINT32 q_wred_cfg_para_reg_index = 0; + ZXIC_UINT32 q_wq_reg_index = 0; + ZXIC_UINT32 q_wred_len_th_reg_index = 0; + + ZXIC_UINT32 pp_wred_max_th_reg_index = 0; + ZXIC_UINT32 pp_wred_min_th_reg_index = 0; + ZXIC_UINT32 pp_wred_cfg_para_reg_index = 0; + ZXIC_UINT32 pp_wq_reg_index = 0; + ZXIC_UINT32 pp_wred_len_th_reg_index = 0; + + DPP_ETM_CGAVD_FLOW_WRED_MAX_TH_T q_max_th = {0}; + DPP_ETM_CGAVD_FLOW_WRED_MIN_TH_T q_min_th = {0}; + DPP_ETM_CGAVD_FLOW_WRED_CFG_PARA_T q_cfg_para = {0}; + DPP_ETM_CGAVD_FLOW_WQ_T q_wq = {0}; + DPP_ETM_CGAVD_FLOW_WRED_Q_LEN_TH_T q_len_th = {0}; + DPP_ETM_CGAVD_PP_WRED_MAX_TH_T pp_max_th = {0}; + DPP_ETM_CGAVD_PP_WRED_MIN_TH_T pp_min_th = {0}; + DPP_ETM_CGAVD_PP_CFG_PARA_T pp_cfg_para = {0}; + DPP_ETM_CGAVD_PP_WQ_T pp_wq = {0}; + DPP_ETM_CGAVD_PP_WRED_Q_LEN_TH_T pp_len_th = {0}; + + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, level, QUEUE_LEVEL, PP_LEVEL); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, dp, 0, DPP_TM_DP_NUM - 1); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_para); + + q_wred_max_th_reg_index = ETM_CGAVD_FLOW_WRED_MAX_THr; + q_wred_min_th_reg_index = ETM_CGAVD_FLOW_WRED_MIN_THr; + q_wred_cfg_para_reg_index = ETM_CGAVD_FLOW_WRED_CFG_PARAr; + q_wq_reg_index = ETM_CGAVD_FLOW_WQr; + q_wred_len_th_reg_index = ETM_CGAVD_FLOW_WRED_Q_LEN_THr; + + pp_wred_max_th_reg_index = ETM_CGAVD_PP_WRED_MAX_THr; + pp_wred_min_th_reg_index = ETM_CGAVD_PP_WRED_MIN_THr; + pp_wred_cfg_para_reg_index = ETM_CGAVD_PP_CFG_PARAr; + pp_wq_reg_index = ETM_CGAVD_PP_WQr; + pp_wred_len_th_reg_index = ETM_CGAVD_PP_WRED_Q_LEN_THr; + + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, wred_id , DPP_TM_DP_NUM); + index = wred_id * DPP_TM_DP_NUM + dp; + + if (QUEUE_LEVEL == level) + { + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, wred_id, 0, DPP_TM_Q_WRED_NUM - 1); + + /* q_max_th */ + rc = dpp_reg_read(dev_id, + q_wred_max_th_reg_index, + 0, + index, + &q_max_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + /* q_min_th */ + rc = dpp_reg_read(dev_id, + q_wred_min_th_reg_index, + 0, + index, + &q_min_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + /* q_cfg_para */ + rc = dpp_reg_read(dev_id, + q_wred_cfg_para_reg_index, + 0, + index, + &q_cfg_para); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + /* q_wq */ + rc = dpp_reg_read(dev_id, + q_wq_reg_index, + 0, + wred_id, + &q_wq); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + /* q_len_th */ + rc = dpp_reg_read(dev_id, + q_wred_len_th_reg_index, + 0, + wred_id, + &q_len_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + p_para->max_th = q_max_th.flow_wred_max_th; + p_para->min_th = q_min_th.flow_wred_min_th; + + if (q_cfg_para.flow_wred_cfg_para != 0) + { + p_para->max_p = (ZXIC_UINT32)(100 * (q_max_th.flow_wred_max_th - q_min_th.flow_wred_min_th) / q_cfg_para.flow_wred_cfg_para); + } + else + { + p_para->max_p = 0; + } + + p_para->q_len_th = q_len_th.flow_wred_q_len_th; + p_para->weight = q_wq.wq_flow; + } + + else + { + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, wred_id, 0, DPP_TM_PP_WRED_NUM - 1); + + /* pp_max_th */ + rc = dpp_reg_read(dev_id, + pp_wred_max_th_reg_index, + 0, + index, + &pp_max_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + /* pp_min_th */ + rc = dpp_reg_read(dev_id, + pp_wred_min_th_reg_index, + 0, + index, + &pp_min_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + /* pp_cfg_para */ + rc = dpp_reg_read(dev_id, + pp_wred_cfg_para_reg_index, + 0, + index, + &pp_cfg_para); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + /* pp_wq */ + rc = dpp_reg_read(dev_id, + pp_wq_reg_index, + 0, + wred_id, + &pp_wq); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + /* q_len_th */ + rc = dpp_reg_read(dev_id, + pp_wred_len_th_reg_index, + 0, + wred_id, + &pp_len_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + p_para->max_th = pp_max_th.pp_wred_max_th; + p_para->min_th = pp_min_th.pp_wred_min_th; + + if (pp_cfg_para.pp_cfg_para != 0) + { + p_para->max_p = (ZXIC_UINT32)(100 * (pp_max_th.pp_wred_max_th - pp_min_th.pp_wred_min_th) / pp_cfg_para.pp_cfg_para); + } + else + { + p_para->max_p = 0; + } + + p_para->q_len_th = pp_len_th.pp_wred_q_len_th; + p_para->weight = pp_wq.wq_pp; + } + + return DPP_OK; + +} + +/***********************************************************/ +/** 读取WRED丢弃曲线对应的参数 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param level WRED支持层次号，0:队列级，1:端口级 +* @param wred_id 队列级共支持16个WRED组0-15，端口级支持8组0-7 +* @param dp 共支持8个dp，取值0-7 +* @param p_para 配置的WRED组参数值，包含以下五个参数 + max_th 平均队列深度上限阈值 + min_th 平均队列深度下限阈值 + max_p 最大丢弃概率 + weight 平均队列深度计算权重 + q_len_th 队列深度阈值 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cy @date 2016/08/01 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_wred_dp_line_para_get(ZXIC_UINT32 dev_id, + DPP_TM_CGAVD_LEVEL_E level, + ZXIC_UINT32 wred_id, + ZXIC_UINT32 dp, + DPP_TM_WRED_DP_LINE_PARA_T *p_para) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 blk_size = 0; + ZXIC_UINT32 cgavd_cfg_mode = 0; + DPP_TM_WRED_DP_LINE_PARA_T para = {0}; + + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, level, QUEUE_LEVEL, PP_LEVEL); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, dp, 0, DPP_TM_DP_NUM - 1); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_para); + + if (QUEUE_LEVEL == level) + { + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, wred_id, 0, DPP_TM_Q_WRED_NUM - 1); + } + + else + { + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, wred_id, 0, DPP_TM_PP_WRED_NUM - 1); + } + + rc = dpp_tm_cgavd_wred_dp_line_block_byte_para_get(dev_id, level, wred_id, dp, ¶); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_wred_dp_line_block_byte_para_set"); + + p_para->max_p = para.max_p; + p_para->weight = para.weight; + + rc = dpp_tm_cgavd_cfg_mode_get(dev_id, &cgavd_cfg_mode); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_cfg_mode_get"); + + if (cgavd_cfg_mode == DPP_TM_CGAVD_BLOCK_MODE) + { + rc = dpp_tm_cfgmt_blk_size_get(dev_id, &blk_size); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_blk_size_get"); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, blk_size, 256, 1024); + + p_para->max_th = (para.max_th * blk_size) / DPP_TM_CGAVD_KILO_UL; + p_para->min_th = (para.min_th * blk_size) / DPP_TM_CGAVD_KILO_UL; + p_para->q_len_th = (para.q_len_th * blk_size) / DPP_TM_CGAVD_KILO_UL; + + } + else if (cgavd_cfg_mode == DPP_TM_CGAVD_ZXIC_UINT8_MODE) + { + p_para->max_th = (para.max_th / DPP_TM_CGAVD_KILO_UL); + p_para->min_th = (para.min_th / DPP_TM_CGAVD_KILO_UL); + p_para->q_len_th = (para.q_len_th / DPP_TM_CGAVD_KILO_UL); + + } + else + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "dpp_tm_cgavd_wred_dp_line_para_get err!!\n"); + return DPP_ERR; + } + + return DPP_OK; + +} + + +/***********************************************************/ +/** 配置系统级GRED丢弃曲线对应的参数 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param dp 共支持8个dp，取值0-7 +* @param p_para 配置的GRED丢弃曲线参数值，包含以下六个参数 + max_th 平均队列深度上限阈值ZXIC_UINT8/BLOCK单位 + mid_th 平均队列深度中间阈值ZXIC_UINT8/BLOCK单位 + min_th 平均队列深度下限阈值ZXIC_UINT8/BLOCK单位 + max_p 最大丢弃概率[1-99] + weight 平均队列深度计算权重 + q_len_th 队列深度阈值ZXIC_UINT8/BLOCK单位 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cy @date 2016/08/02 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_gred_dp_line_block_byte_para_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 dp, + DPP_TM_GRED_DP_LINE_PARA_T *p_para) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 gred_max_th_reg_index = 0; + ZXIC_UINT32 gred_mid_th_reg_index = 0; + ZXIC_UINT32 gred_min_th_reg_index = 0; + ZXIC_UINT32 gred_cfg_para0_reg_index = 0; + ZXIC_UINT32 gred_cfg_para1_reg_index = 0; + ZXIC_UINT32 gred_cfg_para2_reg_index = 0; + ZXIC_UINT32 gred_sys_wfq_reg_index = 0; + ZXIC_UINT32 gred_sys_cfg_q_grp_para_reg_index = 0; + + DPP_ETM_CGAVD_GRED_MAX_TH_T max_th = {0}; + DPP_ETM_CGAVD_GRED_MID_TH_T mid_th = {0}; + DPP_ETM_CGAVD_GRED_MIN_TH_T min_th = {0}; + DPP_ETM_CGAVD_GRED_CFG_PARA0_T cfg_para0 = {0}; + DPP_ETM_CGAVD_GRED_CFG_PARA1_T cfg_para1 = {0}; + DPP_ETM_CGAVD_GRED_CFG_PARA2_T cfg_para2 = {0}; + DPP_ETM_CGAVD_SYS_WQ_T sys_wq = {0}; + DPP_ETM_CGAVD_SYS_CFG_Q_GRP_PARA_T sys_len_th = {0}; + + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, dp, 0, DPP_TM_DP_NUM - 1); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_para); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, p_para->max_p, 1, DPP_TM_RED_P_MAX); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, p_para->weight, 0, DPP_TM_CGAVD_WEIGHT_MAX); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, p_para->max_th, 0, 0x1fffffff); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, p_para->mid_th, 0, 0x1fffffff); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, p_para->min_th, 0, 0x1fffffff); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, p_para->q_len_th, 0, 0x1fffffff); + + gred_max_th_reg_index = ETM_CGAVD_GRED_MAX_THr; + gred_mid_th_reg_index = ETM_CGAVD_GRED_MID_THr; + gred_min_th_reg_index = ETM_CGAVD_GRED_MIN_THr; + gred_cfg_para0_reg_index = ETM_CGAVD_GRED_CFG_PARA0r; + gred_cfg_para1_reg_index = ETM_CGAVD_GRED_CFG_PARA1r; + gred_cfg_para2_reg_index = ETM_CGAVD_GRED_CFG_PARA2r; + gred_sys_wfq_reg_index = ETM_CGAVD_SYS_WQr; + gred_sys_cfg_q_grp_para_reg_index = ETM_CGAVD_SYS_CFG_Q_GRP_PARAr; + + /* max_th */ + max_th.gred_max_th = p_para->max_th; + rc = dpp_reg_write(dev_id, + gred_max_th_reg_index, + 0, + dp, + &max_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + /* mid_th */ + mid_th.gred_mid_th = p_para->mid_th; + rc = dpp_reg_write(dev_id, + gred_mid_th_reg_index, + 0, + dp, + &mid_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + /* min_th */ + min_th.gred_min_th = p_para->min_th; + rc = dpp_reg_write(dev_id, + gred_min_th_reg_index, + 0, + dp, + &min_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + /* cfg_para0，乘以100用来换算百分比，用户配置的是值是1-100 */ + ZXIC_COMM_CHECK_DEV_INDEX_SUB_OVERFLOW_NO_ASSERT(dev_id, mid_th.gred_mid_th+1 , min_th.gred_min_th); + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, 100 , (mid_th.gred_mid_th - min_th.gred_min_th)); + cfg_para0.gred_cfg_para0 = (ZXIC_UINT32)(100 * (mid_th.gred_mid_th - min_th.gred_min_th) / p_para->max_p); + + rc = dpp_reg_write(dev_id, + gred_cfg_para0_reg_index, + 0, + dp, + &cfg_para0); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + /* cfg_para1 */ + ZXIC_COMM_CHECK_DEV_INDEX_SUB_OVERFLOW_NO_ASSERT(dev_id, max_th.gred_max_th+1 , mid_th.gred_mid_th); + cfg_para1.gred_cfg_para1 = (ZXIC_UINT32)(100 * (max_th.gred_max_th - mid_th.gred_mid_th) / (100 - p_para->max_p)); + + rc = dpp_reg_write(dev_id, + gred_cfg_para1_reg_index, + 0, + dp, + &cfg_para1); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + + /* cfg_para2 */ + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, p_para->max_p , cfg_para1.gred_cfg_para1); + cfg_para2.gred_cfg_para2 = (ZXIC_UINT32)(p_para->max_p * cfg_para1.gred_cfg_para1 / 100); + + rc = dpp_reg_write(dev_id, + gred_cfg_para2_reg_index, + 0, + dp, + &cfg_para2); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + /* 必须先写sys_len_th */ + sys_len_th.gred_q_len_th_sys = p_para->q_len_th; + rc = dpp_reg_write(dev_id, + gred_sys_cfg_q_grp_para_reg_index, + 0, + 0, + &sys_len_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + /* 再写sys_wq */ + sys_wq.wq_sys = p_para->weight; + rc = dpp_reg_write(dev_id, + gred_sys_wfq_reg_index, + 0, + 0, + &sys_wq); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + return DPP_OK; +} + +/***********************************************************/ +/** 配置系统级GRED丢弃曲线对应的参数 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param dp 共支持8个dp，取值0-7 +* @param p_para 配置的GRED丢弃曲线参数值，用户配置门限值单位为Kbyte，需要转化为Block或者ZXIC_UINT8单位写入寄存器 + 包含以下六个参数 + max_th 平均队列深度上限阈值 + mid_th 平均队列深度中间阈值 + min_th 平均队列深度下限阈值 + max_p 最大丢弃概率 + weight 平均队列深度计算权重 + q_len_th 队列深度阈值 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cy @date 2016/08/02 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_gred_dp_line_para_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 dp, + DPP_TM_GRED_DP_LINE_PARA_T *p_para) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 cgavd_cfg_mode = 0; + ZXIC_UINT32 blk_size = 0; + DPP_TM_GRED_DP_LINE_PARA_T para = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, dp, 0, DPP_TM_DP_NUM - 1); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_para); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, p_para->max_p, 1, DPP_TM_RED_P_MAX); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, p_para->weight, 0, DPP_TM_CGAVD_WEIGHT_MAX); + + p_para->max_th = p_para->max_th * DPP_TM_CGAVD_KILO_UL; + p_para->mid_th = p_para->mid_th * DPP_TM_CGAVD_KILO_UL; + p_para->min_th = p_para->min_th * DPP_TM_CGAVD_KILO_UL; + if ((p_para->q_len_th) * DPP_TM_CGAVD_KILO_UL > 0x1fffffff) + { + p_para->q_len_th = 0x1fffffff; + }else{ + p_para->q_len_th = (p_para->q_len_th) * DPP_TM_CGAVD_KILO_UL; + } + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, p_para->max_th, 0, 0x1fffffff); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, p_para->mid_th, 0, 0x1fffffff); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, p_para->min_th, 0, 0x1fffffff); + + para.max_p = p_para->max_p; + para.weight = p_para->weight; + + rc = dpp_tm_cgavd_cfg_mode_get(dev_id, &cgavd_cfg_mode); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_cfg_mode_get"); + + if (cgavd_cfg_mode == DPP_TM_CGAVD_BLOCK_MODE) + { + rc = dpp_tm_cfgmt_blk_size_get(dev_id, &blk_size); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_blk_size_get"); + + if (blk_size != 0) + { + para.max_th = ((p_para->max_th ) / blk_size); + para.max_th = ((p_para->max_th) % blk_size == 0) ? (para.max_th ) : ((para.max_th) + 1); + para.mid_th = ((p_para->mid_th ) / blk_size); + para.mid_th = ((p_para->mid_th) % blk_size == 0) ? (para.mid_th ) : ((para.mid_th) + 1); + para.min_th = ((p_para->min_th ) / blk_size); + para.min_th = ((p_para->min_th) % blk_size == 0) ? (para.min_th ) : ((para.min_th) + 1); + para.q_len_th = ((p_para->q_len_th ) / blk_size); + para.q_len_th = ((p_para->q_len_th) % blk_size == 0) ? (para.q_len_th ) : ((para.q_len_th) + 1); + } + + } + else if (cgavd_cfg_mode == DPP_TM_CGAVD_ZXIC_UINT8_MODE) + { + para.max_th = p_para->max_th; + para.mid_th = p_para->mid_th; + para.min_th = p_para->min_th; + para.q_len_th = p_para->q_len_th; + } + else + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "dpp_tm_cgavd_gred_dp_line_para_set err!!\n"); + return DPP_ERR; + } + + rc = dpp_tm_cgavd_gred_dp_line_block_byte_para_set(dev_id, dp, ¶); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_gred_dp_line_block_byte_para_set"); + + return DPP_OK; +} + + +/***********************************************************/ +/** 配置系统级阶梯TD 丢弃曲线对应的参数 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param dp 共支持8个dp，取值0-7 +* @param td_th TD 门限 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cy @date 2016/08/02 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_ladtd_dp_line_para_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 dp, + ZXIC_UINT32 td_th) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 gred_max_th_reg_index = 0; + ZXIC_UINT32 gred_mid_th_reg_index = 0; + ZXIC_UINT32 gred_min_th_reg_index = 0; + ZXIC_UINT32 gred_cfg_para0_reg_index = 0; + ZXIC_UINT32 gred_cfg_para1_reg_index = 0; + ZXIC_UINT32 gred_cfg_para2_reg_index = 0; + ZXIC_UINT32 cgavd_cfg_mode = 0; + ZXIC_UINT32 blk_size = 0; + + DPP_ETM_CGAVD_GRED_MAX_TH_T max_th = {0}; + DPP_ETM_CGAVD_GRED_MID_TH_T mid_th = {0}; + DPP_ETM_CGAVD_GRED_MIN_TH_T min_th = {0}; + DPP_ETM_CGAVD_GRED_CFG_PARA0_T cfg_para0 = {0}; + DPP_ETM_CGAVD_GRED_CFG_PARA1_T cfg_para1 = {0}; + DPP_ETM_CGAVD_GRED_CFG_PARA2_T cfg_para2 = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, dp, 0, DPP_TM_DP_NUM - 1); + + td_th = td_th * DPP_TM_CGAVD_KILO_UL; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, td_th, 0, 0x1fffffff); + + rc = dpp_tm_cgavd_cfg_mode_get(dev_id, &cgavd_cfg_mode); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_cfg_mode_get"); + + if (cgavd_cfg_mode == DPP_TM_CGAVD_BLOCK_MODE) + { + rc = dpp_tm_cfgmt_blk_size_get(dev_id, &blk_size); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_blk_size_get"); + + if (blk_size != 0) + { + max_th.gred_max_th = (( td_th ) / blk_size); + max_th.gred_max_th = ((td_th) % blk_size == 0) ? ( max_th.gred_max_th ) : (( max_th.gred_max_th) + 1); + mid_th.gred_mid_th = (( td_th ) / blk_size); + mid_th.gred_mid_th = ((td_th) % blk_size == 0) ? ( mid_th.gred_mid_th ) : (( mid_th.gred_mid_th) + 1); + min_th.gred_min_th = (( td_th ) / blk_size); + min_th.gred_min_th = ((td_th) % blk_size == 0) ? ( min_th.gred_min_th ) : (( min_th.gred_min_th) + 1); + + } + + } + else if (cgavd_cfg_mode == DPP_TM_CGAVD_ZXIC_UINT8_MODE) + { + max_th.gred_max_th = td_th; + mid_th.gred_mid_th = td_th; + min_th.gred_min_th = td_th; + } + else + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "dpp_tm_cgavd_gred_dp_line_para_get err!!\n"); + return DPP_ERR; + } + + gred_max_th_reg_index = ETM_CGAVD_GRED_MAX_THr; + gred_mid_th_reg_index = ETM_CGAVD_GRED_MID_THr; + gred_min_th_reg_index = ETM_CGAVD_GRED_MIN_THr; + gred_cfg_para0_reg_index = ETM_CGAVD_GRED_CFG_PARA0r; + gred_cfg_para1_reg_index = ETM_CGAVD_GRED_CFG_PARA1r; + gred_cfg_para2_reg_index = ETM_CGAVD_GRED_CFG_PARA2r; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, td_th, 0, 0x1fffffff); + + + /* max_th */ + rc = dpp_reg_write(dev_id, + gred_max_th_reg_index, + 0, + dp, + &max_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + /* mid_th */ + rc = dpp_reg_write(dev_id, + gred_mid_th_reg_index, + 0, + dp, + &mid_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + /* min_th */ + rc = dpp_reg_write(dev_id, + gred_min_th_reg_index, + 0, + dp, + &min_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + /* cfg_para0，0 */ + cfg_para0.gred_cfg_para0 = 0; + + rc = dpp_reg_write(dev_id, + gred_cfg_para0_reg_index, + 0, + dp, + &cfg_para0); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + /* cfg_para1 */ + cfg_para1.gred_cfg_para1 = 0; + + rc = dpp_reg_write(dev_id, + gred_cfg_para1_reg_index, + 0, + dp, + &cfg_para1); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + + /* cfg_para2 */ + cfg_para2.gred_cfg_para2 = 0; + + rc = dpp_reg_write(dev_id, + gred_cfg_para2_reg_index, + 0, + dp, + &cfg_para2); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + + return DPP_OK; +} + + +/***********************************************************/ +/** 读取系统级GRED丢弃曲线对应的参数 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param dp 共支持8个dp，取值0-7 +* @param p_para 配置的GRED丢弃曲线参数值，包含以下六个参数 + max_th 平均队列深度上限阈值ZXIC_UINT8/BLOCK单位 + mid_th 平均队列深度中间阈值ZXIC_UINT8/BLOCK单位 + min_th 平均队列深度下限阈值ZXIC_UINT8/BLOCK单位 + max_p 最大丢弃概率 + weight 平均队列深度计算权重 + q_len_th 队列深度阈值ZXIC_UINT8/BLOCK单位 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cy @date 2016/08/02 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_gred_dp_line_block_byte_para_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 dp, + DPP_TM_GRED_DP_LINE_PARA_T *p_para) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 gred_max_th_reg_index = 0; + ZXIC_UINT32 gred_mid_th_reg_index = 0; + ZXIC_UINT32 gred_min_th_reg_index = 0; + ZXIC_UINT32 gred_cfg_para0_reg_index = 0; + ZXIC_UINT32 gred_cfg_para1_reg_index = 0; + ZXIC_UINT32 gred_cfg_para2_reg_index = 0; + ZXIC_UINT32 gred_sys_wfq_reg_index = 0; + ZXIC_UINT32 gred_sys_cfg_q_grp_para_reg_index = 0; + + DPP_ETM_CGAVD_GRED_MAX_TH_T max_th = {0}; + DPP_ETM_CGAVD_GRED_MID_TH_T mid_th = {0}; + DPP_ETM_CGAVD_GRED_MIN_TH_T min_th = {0}; + DPP_ETM_CGAVD_GRED_CFG_PARA0_T cfg_para0 = {0}; + DPP_ETM_CGAVD_GRED_CFG_PARA1_T cfg_para1 = {0}; + DPP_ETM_CGAVD_GRED_CFG_PARA2_T cfg_para2 = {0}; + DPP_ETM_CGAVD_SYS_WQ_T sys_wq = {0}; + DPP_ETM_CGAVD_SYS_CFG_Q_GRP_PARA_T sys_len_th = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, dp, 0, DPP_TM_DP_NUM - 1); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_para); + + gred_max_th_reg_index = ETM_CGAVD_GRED_MAX_THr; + gred_mid_th_reg_index = ETM_CGAVD_GRED_MID_THr; + gred_min_th_reg_index = ETM_CGAVD_GRED_MIN_THr; + gred_cfg_para0_reg_index = ETM_CGAVD_GRED_CFG_PARA0r; + gred_cfg_para1_reg_index = ETM_CGAVD_GRED_CFG_PARA1r; + gred_cfg_para2_reg_index = ETM_CGAVD_GRED_CFG_PARA2r; + gred_sys_wfq_reg_index = ETM_CGAVD_SYS_WQr; + gred_sys_cfg_q_grp_para_reg_index = ETM_CGAVD_SYS_CFG_Q_GRP_PARAr; + + /* max_th */ + rc = dpp_reg_read(dev_id, + gred_max_th_reg_index, + 0, + dp, + &max_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + /* mid_th */ + rc = dpp_reg_read(dev_id, + gred_mid_th_reg_index, + 0, + dp, + &mid_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + /* min_th */ + rc = dpp_reg_read(dev_id, + gred_min_th_reg_index, + 0, + dp, + &min_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + /* cfg_para0 */ + rc = dpp_reg_read(dev_id, + gred_cfg_para0_reg_index, + 0, + dp, + &cfg_para0); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + /* cfg_para1 */ + rc = dpp_reg_read(dev_id, + gred_cfg_para1_reg_index, + 0, + dp, + &cfg_para1); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + + /* cfg_para2 */ + rc = dpp_reg_read(dev_id, + gred_cfg_para2_reg_index, + 0, + dp, + &cfg_para2); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + /* sys_len_th */ + rc = dpp_reg_read(dev_id, + gred_sys_cfg_q_grp_para_reg_index, + 0, + 0, + &sys_len_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + /* sys_wq */ + rc = dpp_reg_read(dev_id, + gred_sys_wfq_reg_index, + 0, + 0, + &sys_wq); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + p_para->max_th = max_th.gred_max_th; + p_para->mid_th = mid_th.gred_mid_th; + p_para->min_th = min_th.gred_min_th; + + if (cfg_para0.gred_cfg_para0) + { + p_para->max_p = (ZXIC_UINT32)(100 * (mid_th.gred_mid_th - min_th.gred_min_th) / cfg_para0.gred_cfg_para0); + } + + p_para->weight = sys_wq.wq_sys; + p_para->q_len_th = sys_len_th.gred_q_len_th_sys; + + return DPP_OK; + +} + + +/***********************************************************/ +/** 读取系统级GRED丢弃曲线对应的参数 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param dp 共支持8个dp，取值0-7 +* @param p_para 配置的GRED丢弃曲线参数值，包含以下六个参数 + max_th 平均队列深度上限阈值 + mid_th 平均队列深度中间阈值 + min_th 平均队列深度下限阈值 + max_p 最大丢弃概率 + weight 平均队列深度计算权重 + q_len_th 队列深度阈值 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author taq @date 2015/04/20 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_gred_dp_line_para_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 dp, + DPP_TM_GRED_DP_LINE_PARA_T *p_para) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 cgavd_cfg_mode = 0; + ZXIC_UINT32 blk_size = 0; + DPP_TM_GRED_DP_LINE_PARA_T para = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, dp, 0, DPP_TM_DP_NUM - 1); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_para); + + + rc = dpp_tm_cgavd_gred_dp_line_block_byte_para_get(dev_id, dp, ¶); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_gred_dp_line_block_byte_para_get"); + + p_para->max_p = para.max_p; + p_para->weight = para.weight; + + rc = dpp_tm_cgavd_cfg_mode_get(dev_id, &cgavd_cfg_mode); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_cfg_mode_get"); + + if (cgavd_cfg_mode == DPP_TM_CGAVD_BLOCK_MODE) + { + rc = dpp_tm_cfgmt_blk_size_get(dev_id, &blk_size); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_blk_size_get"); + + p_para->max_th = (para.max_th * blk_size) / DPP_TM_CGAVD_KILO_UL; + p_para->mid_th = (para.mid_th * blk_size) / DPP_TM_CGAVD_KILO_UL; + p_para->min_th = (para.min_th * blk_size) / DPP_TM_CGAVD_KILO_UL; + p_para->q_len_th = (para.q_len_th * blk_size) / DPP_TM_CGAVD_KILO_UL; + + } + else if (cgavd_cfg_mode == DPP_TM_CGAVD_ZXIC_UINT8_MODE) + { + p_para->max_th = (para.max_th / DPP_TM_CGAVD_KILO_UL); + p_para->mid_th = (para.mid_th / DPP_TM_CGAVD_KILO_UL); + p_para->min_th = (para.min_th / DPP_TM_CGAVD_KILO_UL); + p_para->q_len_th = (para.q_len_th / DPP_TM_CGAVD_KILO_UL); + + } + else + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "dpp_tm_cgavd_gred_dp_line_para_get err!!\n"); + return DPP_ERR; + } + + return DPP_OK; + +} + +#endif +/***********************************************************/ +/** 配置指定端口或队列是否支持动态门限机制 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param level WRED支持层次号，0:队列级，1:端口级 +* @param id 队列号或端口号 +* @param en 配置的值，0-不支持动态门限机制，1-支持动态门限机制 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/17 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_dyn_th_en_set(DPP_DEV_T *dev, + DPP_TM_CGAVD_LEVEL_E level, + ZXIC_UINT32 id, + ZXIC_UINT32 en) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 q_dyn_th_en_reg_index = 0; + ZXIC_UINT32 pp_wrd_grp_th_en_reg_index = 0; + + DPP_ETM_CGAVD_FLOW_DYNAMIC_TH_EN_T q_dyn_th_en = {0}; + DPP_ETM_CGAVD_PP_WRED_GRP_TH_EN_T pp_dyn_th_en = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), level, QUEUE_LEVEL, PP_LEVEL); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), en, 0, 1); + + q_dyn_th_en_reg_index = ETM_CGAVD_FLOW_DYNAMIC_TH_ENr; + pp_wrd_grp_th_en_reg_index = ETM_CGAVD_PP_WRED_GRP_TH_ENr; + + if (QUEUE_LEVEL == level) + { + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id, 0, DPP_ETM_Q_NUM - 1); + + q_dyn_th_en.flow_dynamic_th_en = en; + rc = dpp_reg_write(dev, + q_dyn_th_en_reg_index, + 0, + id, + &q_dyn_th_en); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + } + + else + { + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id, 0, DPP_TM_PP_NUM - 1); + + rc = dpp_reg_read(dev, + pp_wrd_grp_th_en_reg_index, + 0, + id, + &pp_dyn_th_en); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + pp_dyn_th_en.pp_wred_grp_th_en = en; + rc = dpp_reg_write(dev, + pp_wrd_grp_th_en_reg_index, + 0, + id, + &pp_dyn_th_en); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + } + + return DPP_OK; + +} + + +/***********************************************************/ +/** 读取指定端口或队列是否支持动态门限机制 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param level WRED支持层次号，0:队列级，1:端口级 +* @param id 队列号或端口号 +* @param p_en 读取的值，0-不支持动态门限机制，1-支持动态门限机制 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/17 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_dyn_th_en_get(DPP_DEV_T *dev, + DPP_TM_CGAVD_LEVEL_E level, + ZXIC_UINT32 id, + ZXIC_UINT32 *p_en) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 q_dyn_th_en_reg_index = 0; + ZXIC_UINT32 pp_wrd_grp_th_en_reg_index = 0; + + DPP_ETM_CGAVD_FLOW_DYNAMIC_TH_EN_T q_dyn_th_en = {0}; + DPP_ETM_CGAVD_PP_WRED_GRP_TH_EN_T pp_dyn_th_en = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), level, QUEUE_LEVEL, PP_LEVEL); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_en); + + q_dyn_th_en_reg_index = ETM_CGAVD_FLOW_DYNAMIC_TH_ENr; + pp_wrd_grp_th_en_reg_index = ETM_CGAVD_PP_WRED_GRP_TH_ENr; + + if (QUEUE_LEVEL == level) + { + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id, 0, DPP_ETM_Q_NUM - 1); + + rc = dpp_reg_read(dev, + q_dyn_th_en_reg_index, + 0, + id, + &q_dyn_th_en); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + *p_en = q_dyn_th_en.flow_dynamic_th_en; + + } + + else + { + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id, 0, DPP_TM_PP_NUM - 1); + + rc = dpp_reg_read(dev, + pp_wrd_grp_th_en_reg_index, + 0, + id, + &pp_dyn_th_en); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + *p_en = pp_dyn_th_en.pp_wred_grp_th_en; + } + + return DPP_OK; + +} + + +/***********************************************************/ +/** 配置等价包长使能 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param en 使能标记，0-不使能，1-使能 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/28 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_equal_pkt_len_en_set(DPP_DEV_T *dev, ZXIC_UINT32 en) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CGAVD_EQUAL_PKT_LEN_EN_T equal_pkt_len_en = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), en, 0, 1); + + equal_pkt_len_en.equal_pkt_len_en = en; + rc = dpp_reg_write(dev, + ETM_CGAVD_EQUAL_PKT_LEN_ENr, + 0, + 0, + &equal_pkt_len_en); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + return DPP_OK; +} + +/***********************************************************/ +/** 读取等价包长使能 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_en 使能标记，0-不使能，1-使能 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/28 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_equal_pkt_len_en_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_en) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CGAVD_EQUAL_PKT_LEN_EN_T equal_pkt_len_en = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_en); + + *p_en = 0xffffffff; + rc = dpp_reg_read(dev, + ETM_CGAVD_EQUAL_PKT_LEN_ENr, + 0, + 0, + &equal_pkt_len_en); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + *p_en = equal_pkt_len_en.equal_pkt_len_en; + + return DPP_OK; +} + +/***********************************************************/ +/** 配置等价包长 +* @param dev_id +* @param tm_type 0-ETM,1-FTM +* @param p_equal_pkt_len 等价包长 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/28 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_equal_pkt_len_para_set(DPP_DEV_T *dev, + DPP_ETM_EQUAL_PKT_LEN_PARA_T *p_equal_pkt_len) +{ + /* 返回值变量定义 */ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 i = 0; + + /* 结构体变量定义 */ + DPP_ETM_CGAVD_EQUAL_PKT_LEN0_T equal_pkt_len0 = {0}; + + /* 入参检查 */ + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_equal_pkt_len); + + for (i = 0; i < 8; i++) + { + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), p_equal_pkt_len->equal_pkt_len[i], 0x0, 0x7fff); + equal_pkt_len0.equal_pkt_len0 = p_equal_pkt_len->equal_pkt_len[i]; + rc = dpp_reg_write(dev, + ETM_CGAVD_EQUAL_PKT_LEN0r + i, + 0, + 0, + &equal_pkt_len0); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + } + + return DPP_OK; +} + + + +/***********************************************************/ +/** 读取等价包长 +* @param dev_id +* @param tm_type 0-ETM,1-FTM +* @param p_equal_pkt_len 等价包长 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/28 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_equal_pkt_len_para_get(DPP_DEV_T *dev, + DPP_ETM_EQUAL_PKT_LEN_PARA_T *p_equal_pkt_len) +{ + /* 返回值变量定义 */ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 i = 0; + + /* 结构体变量定义 */ + DPP_ETM_CGAVD_EQUAL_PKT_LEN0_T equal_pkt_len0 = {0}; + + /* 入参检查 */ + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_equal_pkt_len); + + for (i = 0; i < 8; i++) + { + ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(ETM_CGAVD_EQUAL_PKT_LEN0r, i); + rc = dpp_reg_read(dev, + ETM_CGAVD_EQUAL_PKT_LEN0r + i, + 0, + 0, + &equal_pkt_len0); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + p_equal_pkt_len->equal_pkt_len[i] = equal_pkt_len0.equal_pkt_len0; + } + + return DPP_OK; +} + +/***********************************************************/ +/** 配置等价包长阈值 +* @param dev_id +* @param tm_type 0-ETM,1-FTM +* @param p_equal_pkt_len_th 等价包长阈值 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/28 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_equal_pkt_len_th_para_set(DPP_DEV_T *dev, + DPP_ETM_EQUAL_PKT_LEN_TH_PARA_T *p_equal_pkt_len_th) +{ + /* 返回值变量定义 */ + DPP_STATUS rc = 0; + ZXIC_UINT32 i = 0; + + /* 结构体变量定义 */ + DPP_ETM_CGAVD_EQUAL_PKT_LEN_TH0_T equal_pkt_len_th0 = {0}; + + /* 入参检查 */ + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_equal_pkt_len_th); + + for (i = 0; i < 7; i++) + { + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), p_equal_pkt_len_th->equal_pkt_len_th[i], 0x0, 0x7fff); + + if (i <= 5 ) + { + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), p_equal_pkt_len_th->equal_pkt_len_th[i + 1], p_equal_pkt_len_th->equal_pkt_len_th[i], 0x7fff); + } + + equal_pkt_len_th0.equal_pkt_len_th0 = p_equal_pkt_len_th->equal_pkt_len_th[i]; + rc = dpp_reg_write(dev, + ETM_CGAVD_EQUAL_PKT_LEN_TH0r + i, + 0, + 0, + &equal_pkt_len_th0); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + } + + return DPP_OK; +} + + +/***********************************************************/ +/** 读取等价包长阈值 +* @param dev_id +* @param tm_type 0-ETM,1-FTM +* @param p_equal_pkt_len_th 等价包长阈值 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/28 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_equal_pkt_len_th_para_get(DPP_DEV_T *dev, + DPP_ETM_EQUAL_PKT_LEN_TH_PARA_T *p_equal_pkt_len_th) +{ + /* 返回值变量定义 */ + DPP_STATUS rc = 0; + ZXIC_UINT32 i = 0; + + /* 结构体变量定义 */ + DPP_ETM_CGAVD_EQUAL_PKT_LEN_TH0_T equal_pkt_len_th0 = {0}; + + /* 入参检查 */ + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_equal_pkt_len_th); + + for (i = 0; i < 7; i++) + { + ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(DEV_ID(dev), i, ETM_CGAVD_EQUAL_PKT_LEN_TH0r); + rc = dpp_reg_read(dev, + ETM_CGAVD_EQUAL_PKT_LEN_TH0r + i, + 0, + 0, + &equal_pkt_len_th0); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + p_equal_pkt_len_th->equal_pkt_len_th[i] = equal_pkt_len_th0.equal_pkt_len_th0; + } + + return DPP_OK; +} + +/***********************************************************/ +/** 动态门限放大因子参数配置 +* @param dev_id +* @param tm_type 0-ETM,1-FTM +* @param p_amplify_gene_para 动态门限放大因子参数 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/28 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_amplify_gene_para_set(DPP_DEV_T *dev, + DPP_ETM_AMPLIFY_GENE_PARA_T *p_amplify_gene_para) +{ + /* 返回值变量定义 */ + DPP_STATUS rc = 0; + ZXIC_UINT32 i = 0; + + /* 结构体变量定义 */ + DPP_ETM_CGAVD_AMPLIFY_GENE0_T amplify_gene0 = {0}; + + /* 入参检查 */ + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_amplify_gene_para); + + for (i = 0; i < 16; i++) + { + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), p_amplify_gene_para->amplify_gene[i], 0x0, 0xfff); + amplify_gene0.amplify_gene0 = p_amplify_gene_para->amplify_gene[i]; + rc = dpp_reg_write(dev, + ETM_CGAVD_AMPLIFY_GENE0r + i, + 0, + 0, + &lify_gene0); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + } + + return DPP_OK; +} + +/***********************************************************/ +/** 动态门限放大因子参数获取 +* @param dev_id +* @param tm_type 0-ETM,1-FTM +* @param p_amplify_gene_para 动态门限放大因子参数 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/28 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_amplify_gene_para_get(DPP_DEV_T *dev, + DPP_ETM_AMPLIFY_GENE_PARA_T *p_amplify_gene_para) +{ + /* 返回值变量定义 */ + DPP_STATUS rc = 0; + ZXIC_UINT32 i = 0; + + /* 结构体变量定义 */ + DPP_ETM_CGAVD_AMPLIFY_GENE0_T amplify_gene0 = {0}; + + /* 入参检查 */ + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_amplify_gene_para); + + for (i = 0; i < 16; i++) + { + ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(ETM_CGAVD_AMPLIFY_GENE0r, i); + rc = dpp_reg_read(dev, + ETM_CGAVD_AMPLIFY_GENE0r + i, + 0, + 0, + &lify_gene0); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + p_amplify_gene_para->amplify_gene[i] = amplify_gene0.amplify_gene0; + } + + return DPP_OK; +} + +#if 0 +/***********************************************************/ +/** 配置默认队列使能 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param en 配置的值，0-不使能默认队列，1-使能默认队列， +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author wush @date 2016/08/16 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_default_queue_en_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 en) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CGAVD_DEFAULT_QUEUE_EN_T default_que_en = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, en, 0, 1); + + default_que_en.default_queue_en = en; + rc = dpp_reg_write(dev_id, + ETM_CGAVD_DEFAULT_QUEUE_ENr, + 0, + 0, + &default_que_en); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + return DPP_OK; +} + +/***********************************************************/ +/** 读取默认队列使能 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_en 读取的值，0-不使能默认队列，1-使能默认队列， +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author wush @date 2016/08/16 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_default_queue_en_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_en) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CGAVD_DEFAULT_QUEUE_EN_T default_que_en = {0}; + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_en); + + rc = dpp_reg_read(dev_id, + ETM_CGAVD_DEFAULT_QUEUE_ENr, + 0, + 0, + &default_que_en); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + *p_en = default_que_en.default_queue_en; + + return DPP_OK; +} + + +/***********************************************************/ +/** 配置默认队列起始末尾 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param def_start_que 起始默认队列block/byte单位 +* @param def_finish_que 结束默认队列block/byte单位 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author wush @date 2016/08/16 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_default_queue_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 def_start_queue, ZXIC_UINT32 def_finish_queue) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CGAVD_DEFAULT_START_QUEUE_T def_start_que = {0}; + DPP_ETM_CGAVD_DEFAULT_FINISH_QUEUE_T def_finish_que = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, def_start_queue, 0, 0x1fffffff); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, def_finish_queue, 0, 0x1fffffff); + + def_start_que.default_start_queue = def_start_queue; + def_finish_que.default_finish_queue = def_finish_queue; + + + rc = dpp_reg_write(dev_id, + ETM_CGAVD_DEFAULT_START_QUEUEr, + 0, + 0, + &def_start_que); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + rc = dpp_reg_write(dev_id, + ETM_CGAVD_DEFAULT_FINISH_QUEUEr, + 0, + 0, + &def_finish_que); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + return DPP_OK; +} + + +/***********************************************************/ +/** 读取默认队列起始末尾值 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_def_start_que 默认队列起始值block/byte单位 +* @param p_def_finish_que 默认队列结束值block/byte单位 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author wush @date 2016/08/16 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_default_queue_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_def_start_queue, ZXIC_UINT32 *p_def_finish_queue) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CGAVD_DEFAULT_START_QUEUE_T def_start_que = {0}; + DPP_ETM_CGAVD_DEFAULT_FINISH_QUEUE_T def_finish_que = {0}; + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_def_finish_queue); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_def_start_queue); + + rc = dpp_reg_read(dev_id, + ETM_CGAVD_DEFAULT_START_QUEUEr, + 0, + 0, + &def_start_que); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + rc = dpp_reg_read(dev_id, + ETM_CGAVD_DEFAULT_FINISH_QUEUEr, + 0, + 0, + &def_finish_que); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + *p_def_start_queue = def_start_que.default_start_queue; + *p_def_finish_queue = def_finish_que.default_finish_queue; + + return DPP_OK; +} + + +/***********************************************************/ +/** 配置协议队列使能 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param en 配置的值，0-不使能默认队列，1-使能默认队列， +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author wush @date 2016/08/16 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_protocol_queue_en_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 en) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CGAVD_PROTOCOL_QUEUE_EN_T protocol_que_en = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, en, 0, 1); + + protocol_que_en.protocol_queue_en = en; + rc = dpp_reg_write(dev_id, + ETM_CGAVD_PROTOCOL_QUEUE_ENr, + 0, + 0, + &protocol_que_en); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + return DPP_OK; +} + +/***********************************************************/ +/** 读取协议队列使能 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_en 读取的值，0-不使能通用门限，1-使能通用门限， +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author wush @date 2016/08/16 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_protocol_queue_en_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_en) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CGAVD_PROTOCOL_QUEUE_EN_T protocol_que_en = {0}; + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_en); + + rc = dpp_reg_read(dev_id, + ETM_CGAVD_PROTOCOL_QUEUE_ENr, + 0, + 0, + &protocol_que_en); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + *p_en = protocol_que_en.protocol_queue_en; + + return DPP_OK; +} + + +/***********************************************************/ +/** 配置协议队列起始末尾 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param protocol_start_que 起始协议队列block/byte单位 +*@param protocol_-finish_que 末尾协议队列block/byte单位 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author wush @date 2016/08/16 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_protocol_queue_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 protocol_start_que, ZXIC_UINT32 protocol_finish_que) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CGAVD_PROTOCOL_START_QUEUE_T pro_start_que = {0}; + DPP_ETM_CGAVD_PROTOCOL_FINISH_QUEUE_T pro_finish_que = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, protocol_start_que, 0, 0x1fffffff); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, protocol_finish_que, 0, 0x1fffffff); + + pro_start_que.protocol_start_queue = protocol_start_que; + pro_finish_que.protocol_finish_queue = protocol_finish_que; + + + rc = dpp_reg_write(dev_id, + ETM_CGAVD_PROTOCOL_START_QUEUEr, + 0, + 0, + &pro_start_que); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + rc = dpp_reg_write(dev_id, + ETM_CGAVD_PROTOCOL_FINISH_QUEUEr, + 0, + 0, + &pro_finish_que); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + return DPP_OK; +} + + +/***********************************************************/ +/** 读取协议队列起始末尾值 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_protocol_start_que 协议认队列起始值block/byte单位 +* @param p_protocol_finish_que 协议认队列末尾值block/byte单位 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author wush @date 2016/08/16 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_protocol_queue_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_protocol_start_que, ZXIC_UINT32 *p_protocol_finish_que) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CGAVD_PROTOCOL_START_QUEUE_T pro_start_que = {0}; + DPP_ETM_CGAVD_PROTOCOL_FINISH_QUEUE_T pro_finish_que = {0}; + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_protocol_finish_que); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_protocol_start_que); + + rc = dpp_reg_read(dev_id, + ETM_CGAVD_PROTOCOL_START_QUEUEr, + 0, + 0, + &pro_start_que); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + rc = dpp_reg_read(dev_id, + ETM_CGAVD_PROTOCOL_FINISH_QUEUEr, + 0, + 0, + &pro_finish_que); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + *p_protocol_start_que = pro_start_que.protocol_start_queue; + *p_protocol_finish_que = pro_finish_que.protocol_finish_queue; + + return DPP_OK; +} + +#endif +/***********************************************************/ +/** 配置通用门限使能 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param en 配置的值，0-不使能通用门限，1-使能通用门限， +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/17 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_uniform_th_en_set(DPP_DEV_T *dev, ZXIC_UINT32 en) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CGAVD_UNIFORM_TD_TH_EN_T uniform_en = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), en, 0, 1); + + uniform_en.uniform_td_th_en = en; + rc = dpp_reg_write(dev, + ETM_CGAVD_UNIFORM_TD_TH_ENr, + 0, + 0, + &uniform_en); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + return DPP_OK; +} + +/***********************************************************/ +/** 读取通用门限使能 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_en 读取的值，0-不使能通用门限，1-使能通用门限， +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/17 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_uniform_th_en_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_en) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CGAVD_UNIFORM_TD_TH_EN_T uniform_en = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_en); + + rc = dpp_reg_read(dev, + ETM_CGAVD_UNIFORM_TD_TH_ENr, + 0, + 0, + &uniform_en); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + *p_en = uniform_en.uniform_td_th_en; + + return DPP_OK; +} + +/***********************************************************/ +/** 配置通用门限 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param byte_block_uni_th 通用门限值block/byte单位 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cy @date 2016/08/01 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_uniform_byte_block_th_set(DPP_DEV_T *dev, ZXIC_UINT32 byte_block_uni_th) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CGAVD_UNIFORM_TD_TH_T uniform_block_th = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), byte_block_uni_th, 0, 0x1fffffff); + + uniform_block_th.uniform_td_th = byte_block_uni_th; + rc = dpp_reg_write(dev, + ETM_CGAVD_UNIFORM_TD_THr, + 0, + 0, + &uniform_block_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + return DPP_OK; +} + + +/***********************************************************/ +/** 配置通用门限 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param th 通用门限值 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cy @date 2014/02/17 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_uniform_th_set(DPP_DEV_T *dev, ZXIC_UINT32 uni_th) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 blk_size = 0; + ZXIC_UINT32 blk_th = 0; + ZXIC_UINT32 cgavd_cfg_mode = 0; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW(DEV_ID(dev), uni_th, DPP_TM_CGAVD_KILO_UL); + if ((uni_th * DPP_TM_CGAVD_KILO_UL) > 0x1fffffff) + { + uni_th = 0x1fffffff; + } + else + { + uni_th = (uni_th * DPP_TM_CGAVD_KILO_UL); + } + + rc = dpp_tm_cgavd_cfg_mode_get(dev, &cgavd_cfg_mode); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_cgavd_cfg_mode_get"); + + if (cgavd_cfg_mode == DPP_TM_CGAVD_BLOCK_MODE) + { + rc = dpp_tm_cfgmt_blk_size_get(dev, &blk_size); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_cfgmt_blk_size_get"); + + if (blk_size != 0) + { + blk_th = (uni_th / blk_size); + blk_th = (uni_th % blk_size == 0) ? (blk_th ) : ((blk_th) + 1); + } + + rc = dpp_tm_cgavd_uniform_byte_block_th_set(dev, blk_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_cgavd_uniform_byte_block_th_set"); + } + else if (cgavd_cfg_mode == DPP_TM_CGAVD_ZXIC_UINT8_MODE) + { + rc = dpp_tm_cgavd_uniform_byte_block_th_set(dev, uni_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_cgavd_uniform_byte_block_th_set"); + } + else + { + ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "dpp_tm_cgavd_uniform_th_set err!!\n"); + return DPP_ERR; + } + + return DPP_OK; +} + + +/***********************************************************/ +/** 读取通用门限 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_byte_block_uni_th 通用门限值block/byte单位 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cy @date 2016/08/01 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_uniform_byte_block_th_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_byte_block_uni_th) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CGAVD_UNIFORM_TD_TH_T uniform_block_th = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_byte_block_uni_th); + + rc = dpp_reg_read(dev, + ETM_CGAVD_UNIFORM_TD_THr, + 0, + 0, + &uniform_block_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + *p_byte_block_uni_th = uniform_block_th.uniform_td_th; + + return DPP_OK; +} + +/***********************************************************/ +/** 读取通用门限 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_uni_th 通用门限值kbyte单位 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cy @date 2016/08/01 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_uniform_th_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_uni_th) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 blk_size = 0; + ZXIC_UINT32 cgavd_cfg_mode = 0; + ZXIC_UINT32 block_byte_th = 0; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_uni_th); + + + rc = dpp_tm_cgavd_uniform_byte_block_th_get(dev, &block_byte_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_cgavd_uniform_byte_block_th_get"); + + rc = dpp_tm_cgavd_cfg_mode_get(dev, &cgavd_cfg_mode); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_cgavd_cfg_mode_get"); + + if (cgavd_cfg_mode == DPP_TM_CGAVD_BLOCK_MODE) + { + rc = dpp_tm_cfgmt_blk_size_get(dev, &blk_size); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_cfgmt_blk_size_get"); + + *p_uni_th = (block_byte_th * blk_size) / DPP_TM_CGAVD_KILO_UL; + + } + else if (cgavd_cfg_mode == DPP_TM_CGAVD_ZXIC_UINT8_MODE) + { + *p_uni_th = (block_byte_th / DPP_TM_CGAVD_KILO_UL); + } + else + { + ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "dpp_tm_cgavd_uniform_th_get err!!\n"); + return DPP_ERR; + } + + return DPP_OK; +} + +/***********************************************************/ +/** 配置流队列所属优先级 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param q_id 队列号 +* @param pri 配置的优先级，0~4 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/17 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_q_pri_set(DPP_DEV_T *dev, + ZXIC_UINT32 q_id, + ZXIC_UINT32 pri) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CGAVD_Q_PRI_T q_pri = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), pri, 0, 4); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), q_id, 0, DPP_ETM_Q_NUM - 1); + + q_pri.qpri_flow_cfg_din = pri; + rc = dpp_reg_write(dev, + ETM_CGAVD_Q_PRIr, + 0, + q_id, + &q_pri); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + return DPP_OK; +} + + +/***********************************************************/ +/** 配置TM模式下流队列挂接的端口号；SA模式下流队列映射的目的芯片ID +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param q_id 队列号 +* @param pp_id 配置的端口号 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/18 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_q_map_pp_set(DPP_DEV_T *dev, + ZXIC_UINT32 q_id, + ZXIC_UINT32 pp_id) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CGAVD_PP_NUM_T pp_num = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), q_id, 0, DPP_ETM_Q_NUM - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), pp_id, 0, DPP_TM_PP_NUM - 1); + + pp_num.pp_num = pp_id; + rc = dpp_reg_write(dev, + ETM_CGAVD_PP_NUMr, + 0, + q_id, + &pp_num); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + return DPP_OK; +} + +/***********************************************************/ +/** 读取TM模式下流队列挂接的端口号；SA模式下流队列映射的目的芯片ID +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param q_id 队列号 +* @param p_pp_id 读取的端口号 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/18 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_q_map_pp_get(DPP_DEV_T *dev, + ZXIC_UINT32 q_id, + ZXIC_UINT32 *p_pp_id) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CGAVD_PP_NUM_T pp_num = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_pp_id); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), q_id, 0, DPP_ETM_Q_NUM - 1); + + *p_pp_id = 0xffffffff; + rc = dpp_reg_read(dev, + ETM_CGAVD_PP_NUMr, + 0, + q_id, + &pp_num); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + *p_pp_id = pp_num.pp_num; + + return DPP_OK; +} + +/***********************************************************/ +/** 配置TM模式tc到flow的映射 +* @param dev_id 设备编号 +* @param tc_id itmd tc优先级（0~7） +* @param flow_id 映射的flowid号 （0~4095） +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author sun @date 2023/07/04 +************************************************************/ +DPP_STATUS dpp_tm_tc_map_flow_set(DPP_DEV_T *dev, + ZXIC_UINT32 tc_id, + ZXIC_UINT32 flow_id) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CGAVD_CFG_TC_FLOWID_DAT_T cfg_tc_flow = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), tc_id, 0, DPP_TM_TC_NUM - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), flow_id, 0, DPP_ETM_Q_NUM - 1); + + cfg_tc_flow.cfg_tc_flowid_dat = flow_id; + rc = dpp_reg_write(dev, + ETM_CGAVD_CFG_TC_FLOWID_DATr, + 0, + tc_id, + &cfg_tc_flow); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + return DPP_OK; +} + +/***********************************************************/ +/** 读取配置TM模式tc到flow的映射 +* @param dev_id 设备编号 +* @param tc_id itmd tc优先级（0~7） +* @param flow_id 读取映射的flowid号 （0~4095） +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author sun @date 2023/07/04 +************************************************************/ +DPP_STATUS dpp_tm_tc_map_flow_get(DPP_DEV_T *dev, + ZXIC_UINT32 tc_id, + ZXIC_UINT32 *flow_id) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CGAVD_CFG_TC_FLOWID_DAT_T cfg_tc_flow = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), flow_id); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), tc_id, 0, DPP_TM_TC_NUM - 1); + + *flow_id = 0xffffffff; + rc = dpp_reg_read(dev, + ETM_CGAVD_CFG_TC_FLOWID_DATr, + 0, + tc_id, + &cfg_tc_flow); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + *flow_id = cfg_tc_flow.cfg_tc_flowid_dat; + + return DPP_OK; +} + +#if 0 +/***********************************************************/ +/** 系统级缓存使用上下限阈值配置 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param th_h: 系统级缓存使用上限阈值 +* @param th_l: 系统级缓存使用下限阈值 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author yjd @date 2015/07/03 +************************************************************/ +DPP_STATUS dpp_tm_sys_window_th_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 th_h, + ZXIC_UINT32 th_l) +{ + DPP_STATUS rc = DPP_OK; + + DPP_ETM_CGAVD_SYS_WINDOW_TH_H_T sys_window_th_h = {0}; + DPP_ETM_CGAVD_SYS_WINDOW_TH_L_T sys_window_th_l = {0}; + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, th_h, 0, 0x1fffffff); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, th_l, 0, 0x1fffffff); + + if (th_l > th_h) + { + ZXIC_COMM_PRINT("input error th_l > th_h"); + return DPP_ERR; + } + + sys_window_th_h.sys_window_th_h = th_h; + sys_window_th_l.sys_window_th_l = th_l; + + rc = dpp_reg_write(dev_id, + ETM_CGAVD_SYS_WINDOW_TH_Hr, + 0, + 0, + &sys_window_th_h); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + rc = dpp_reg_write(dev_id, + ETM_CGAVD_SYS_WINDOW_TH_Lr, + 0, + 0, + &sys_window_th_l); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + return DPP_OK; +} + +#endif +/***********************************************************/ +/** 配置QMU查询队列Qos开关 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param q_id: 队列号 +* @param qos_sign: qos开关 0:关闭 1:开启 +* @param +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author yjd @date 2015/07/03 +************************************************************/ +DPP_STATUS dpp_tm_qmu_qos_sign_set(DPP_DEV_T *dev, + ZXIC_UINT32 q_id, + ZXIC_UINT32 qos_sign) +{ + DPP_STATUS rc = DPP_OK; + + DPP_ETM_CGAVD_QOS_SIGN_T qmu_qos_sign = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), qos_sign, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), q_id, 0, DPP_ETM_Q_NUM - 1); + + qmu_qos_sign.qos_sign_flow_cfg_din = qos_sign; + + rc = dpp_reg_write(dev, + ETM_CGAVD_QOS_SIGNr, + 0, + q_id, + &qmu_qos_sign); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + return DPP_OK; +} + +#if 0 +/***********************************************************/ +/** 配置cgavd强制反压 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param cgavd_fc: 0:不强制反压 1:强制反压 +* @param +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/07/03 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_cfg_fc_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 cgavd_fc) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CGAVD_CGAVD_CFG_FC_T cgavd_cfg_fc_t = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, cgavd_fc, 0, 1); + + cgavd_cfg_fc_t.cgavd_cfg_fc = cgavd_fc; + + rc = dpp_reg_write(dev_id, + ETM_CGAVD_CGAVD_CFG_FCr, + 0, + 0, + &cgavd_cfg_fc_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + return DPP_OK; +} + + +/***********************************************************/ +/** 获取cgavd强制反压状态 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param cgavd_fc: 0:不强制反压 1:强制反压 +* @param +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/07/03 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_cfg_fc_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *cgavd_fc) + +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CGAVD_CGAVD_CFG_FC_T cgavd_cfg_fc_t = {0}; + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, cgavd_fc); + + rc = dpp_reg_read(dev_id, + ETM_CGAVD_CGAVD_CFG_FCr, + 0, + 0, + &cgavd_cfg_fc_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + *cgavd_fc = cgavd_cfg_fc_t.cgavd_cfg_fc; + + return DPP_OK; +} + +/***********************************************************/ +/** 配置cgavd强制不反压 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param cgavd_no_fc: 0:不强制 1:强制不反压 +* @param +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/07/03 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_cfg_no_fc_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 cgavd_no_fc) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CGAVD_CGAVD_CFG_NO_FC_T cgavd_cfg_no_fc_t = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, cgavd_no_fc, 0, 1); + + cgavd_cfg_no_fc_t.cgavd_cfg_no_fc = cgavd_no_fc; + + rc = dpp_reg_write(dev_id, + ETM_CGAVD_CGAVD_CFG_NO_FCr, + 0, + 0, + &cgavd_cfg_no_fc_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + return DPP_OK; +} + + +/***********************************************************/ +/** 获取cgavd强制不反压状态 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param cgavd_no_fc: 0:不强制 1:强制不反压 +* @param +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/07/03 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_cfg_no_fc_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *cgavd_no_fc) + +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CGAVD_CGAVD_CFG_NO_FC_T cgavd_cfg_no_fc_t = {0}; + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, cgavd_no_fc); + + rc = dpp_reg_read(dev_id, + ETM_CGAVD_CGAVD_CFG_NO_FCr, + 0, + 0, + &cgavd_cfg_no_fc_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + *cgavd_no_fc = cgavd_cfg_no_fc_t.cgavd_cfg_no_fc; + + return DPP_OK; +} + + +/***********************************************************/ +/** 配置cgavd平均队列深度归零 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param en: 0:关闭 1:使能 +* @param +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xuhb @date 2020/08/05 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_avg_qlen_return_zero_en_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 en) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CGAVD_AVG_QLEN_RETURN_ZERO_EN_T return_zero_en = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, en, 0, 1); + + return_zero_en.avg_qlen_return_zero_en = en; + + rc = dpp_reg_write(dev_id, + ETM_CGAVD_AVG_QLEN_RETURN_ZERO_ENr, + 0, + 0, + &return_zero_en); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + return DPP_OK; +} + +#endif +#endif + + +#if ZXIC_REAL("TM_QMU") +#if 0 +/***********************************************************/ +/** QMU MMU 配置清除 +* @param dev_id +* @param tm_type +* +* @return +* @remark 无 +* @see +* @author XXX @date 2020/04/13 +************************************************************/ +DPP_STATUS dpp_tm_qmu_mmu_cfg_clr(ZXIC_UINT32 dev_id) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CFGMT_CFGMT_DDR_ATTACH_T attach = {0}; + + ZXIC_UINT32 bdep[64] = {0}; + ZXIC_UINT32 bhead[64] = {0}; + ZXIC_UINT32 btail[64] = {0}; + ZXIC_UINT32 ddr_in_mmu[8] = {0}; + ZXIC_UINT32 ddr_in_qmu[10] = {0}; + ZXIC_UINT32 bank_to_mmu[64] = {0}; + ZXIC_UINT32 bank_to_qmu[80] = {0}; + ZXIC_UINT32 active[16] = {0}; + ZXIC_UINT32 random_grp[64] = {0}; + ZXIC_UINT32 random_ddr0[64] = {0}; + ZXIC_UINT32 random_ddr1[64] = {0}; + ZXIC_UINT32 random_ddr2[64] = {0}; + ZXIC_UINT32 random_ddr3[64] = {0}; + ZXIC_UINT32 random_ddr4[64] = {0}; + ZXIC_UINT32 random_ddr5[64] = {0}; + ZXIC_UINT32 random_ddr6[64] = {0}; + ZXIC_UINT32 random_ddr7[64] = {0}; + //ZXIC_UINT32 mmu_addr[128] = {0}; + + ZXIC_UINT32 i = 0; + + ZXIC_UINT32 reg_attach = 0; + ZXIC_UINT32 reg_ddr_in_mmu = 0; + ZXIC_UINT32 reg_ddr_in_qmu = 0; + ZXIC_UINT32 reg_bank_to_mmu = 0; + ZXIC_UINT32 reg_bank_to_qmu = 0; + ZXIC_UINT32 reg_bdep = 0; + ZXIC_UINT32 reg_bhead = 0; + ZXIC_UINT32 reg_btail = 0; + ZXIC_UINT32 reg_active = 0; + ZXIC_UINT32 reg_random_grp = 0; + ZXIC_UINT32 reg_random_ddr0 = 0; + ZXIC_UINT32 reg_random_ddr1 = 0; + ZXIC_UINT32 reg_random_ddr2 = 0; + ZXIC_UINT32 reg_random_ddr3 = 0; + ZXIC_UINT32 reg_random_ddr4 = 0; + ZXIC_UINT32 reg_random_ddr5 = 0; + ZXIC_UINT32 reg_random_ddr6 = 0; + ZXIC_UINT32 reg_random_ddr7 = 0; + //ZXIC_UINT32 reg_mmu_addr = 0; + + reg_attach = ETM_CFGMT_CFGMT_DDR_ATTACHr; + reg_ddr_in_mmu = ETM_QMU_CFGMT_DDR_IN_MMU_CFGr; + reg_ddr_in_qmu = ETM_QMU_CFGMT_DDR_IN_QMU_CFGr; + reg_bank_to_mmu = ETM_QMU_CFGMT_BANK_TO_MMU_CFGr; + reg_bank_to_qmu = ETM_QMU_CFGMT_BANK_TO_QMU_CFGr; + reg_bdep = ETM_QMU_QCFG_QLIST_BDEPr; + reg_bhead = ETM_QMU_QCFG_QLIST_BHEADr; + reg_btail = ETM_QMU_QCFG_QLIST_BTAILr; + reg_active = ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFGr; + reg_random_grp = ETM_QMU_QCFG_QLIST_GRPr; + reg_random_ddr0 = ETM_QMU_QCFG_QLIST_GRP0_BANKr; + reg_random_ddr1 = ETM_QMU_QCFG_QLIST_GRP1_BANKr; + reg_random_ddr2 = ETM_QMU_QCFG_QLIST_GRP2_BANKr; + reg_random_ddr3 = ETM_QMU_QCFG_QLIST_GRP3_BANKr; + reg_random_ddr4 = ETM_QMU_QCFG_QLIST_GRP4_BANKr; + reg_random_ddr5 = ETM_QMU_QCFG_QLIST_GRP5_BANKr; + reg_random_ddr6 = ETM_QMU_QCFG_QLIST_GRP6_BANKr; + reg_random_ddr7 = ETM_QMU_QCFG_QLIST_GRP7_BANKr; + + rc = dpp_reg_write(dev_id, reg_attach, 0, 0, &attach); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + for (i = 0; i < 8; i++) + { + rc = dpp_reg_write32_bymn(dev_id, reg_ddr_in_mmu, 0, i, ddr_in_mmu[i]); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write32_bymn"); + } + + for (i = 0; i < 10; i++) + { + rc = dpp_reg_write32_bymn(dev_id, reg_ddr_in_qmu, 0, i, ddr_in_qmu[i]); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write32_bymn"); + } + + for (i = 0; i < 64; i++) + { + rc = dpp_reg_write32_bymn(dev_id, reg_bank_to_mmu, 0, i, bank_to_mmu[i]); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write32_bymn"); + } + + for (i = 0; i < 80; i++) + { + rc = dpp_reg_write32_bymn(dev_id, reg_bank_to_qmu, 0, i, bank_to_qmu[i]); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write32_bymn"); + } + + for (i = 0; i < 64; i++) + { + rc = dpp_reg_write32_bymn(dev_id, reg_bhead, 0, i, bhead[i]); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write32_bymn"); + + rc = dpp_reg_write32_bymn(dev_id, reg_btail, 0, i, btail[i]); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write32_bymn"); + + rc = dpp_reg_write32_bymn(dev_id, reg_bdep, 0, i, bdep[i]); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write32_bymn"); + } + + for (i = 0; i < 16; i++) + { + rc = dpp_reg_write32_bymn(dev_id, reg_active, 0, i, active[i]); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write32_bymn"); + } + + for (i = 0; i < 64; i++) + { + rc = dpp_reg_write32_bymn(dev_id, reg_random_grp, 0, i, random_grp[i]); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write32_bymn"); + + rc = dpp_reg_write32_bymn(dev_id, reg_random_ddr0, 0, i, random_ddr0[i]); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write32_bymn"); + + rc = dpp_reg_write32_bymn(dev_id, reg_random_ddr1, 0, i, random_ddr1[i]); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write32_bymn"); + + rc = dpp_reg_write32_bymn(dev_id, reg_random_ddr2, 0, i, random_ddr2[i]); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write32_bymn"); + + rc = dpp_reg_write32_bymn(dev_id, reg_random_ddr3, 0, i, random_ddr3[i]); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write32_bymn"); + + rc = dpp_reg_write32_bymn(dev_id, reg_random_ddr4, 0, i, random_ddr4[i]); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write32_bymn"); + + rc = dpp_reg_write32_bymn(dev_id, reg_random_ddr5, 0, i, random_ddr5[i]); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write32_bymn"); + + rc = dpp_reg_write32_bymn(dev_id, reg_random_ddr6, 0, i, random_ddr6[i]); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write32_bymn"); + + rc = dpp_reg_write32_bymn(dev_id, reg_random_ddr7, 0, i, random_ddr7[i]); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write32_bymn"); + } + + /*for (i = 0; i < 128; i++) + { + rc = dpp_reg_write32_bymn(dev_id, reg_mmu_addr + i, 0, 0, mmu_addr[i]); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write32_bymn"); + }*/ + + return rc; +} + +/***********************************************************/ +/** 配置QMU队列授权价值 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param credit_value 授权价值，默认值是533Byte +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/03/04 +************************************************************/ +DPP_STATUS dpp_tm_qmu_credit_value_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 credit_value) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_QCFG_QSCH_CREDIT_VALUE_T credit_val = {0}; + + credit_val.qcfg_qsch_credit_value = credit_value; + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QSCH_CREDIT_VALUEr, + 0, + 0, + &credit_val); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + return DPP_OK; +} + +#endif +/***********************************************************/ +/** 读取QMU队列授权价值 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_credit_value 授权价值，默认值是533Byte +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cuiy @date 2016/04/14 +************************************************************/ +DPP_STATUS dpp_tm_qmu_credit_value_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_credit_value) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_QCFG_QSCH_CREDIT_VALUE_T credit_val = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_credit_value); + + *p_credit_value = 0; + + rc = dpp_reg_read(dev, + ETM_QMU_QCFG_QSCH_CREDIT_VALUEr, + 0, + 0, + &credit_val); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + *p_credit_value = credit_val.qcfg_qsch_credit_value; + + return DPP_OK; +} + +#if 0 +/***********************************************************/ +/** 配置授权盈余初始化值 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param crbal_initial_value 授权盈余初始化值 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/03/04 +************************************************************/ +DPP_STATUS dpp_tm_qmu_crbal_initial_value_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 crbal_initial_value) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_QCFG_QSCH_CRBAL_INIT_VALUE_T crbal_init_val = {0}; + + crbal_init_val.qcfg_qsch_crbal_init_value = crbal_initial_value; + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QSCH_CRBAL_INIT_VALUEr, + 0, + 0, + &crbal_init_val); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + return DPP_OK; +} + + + +/***********************************************************/ +/** 配置CRS过滤使能 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param en 配置的值，0-不使能过滤，1-使能过滤 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/03/04 +************************************************************/ +DPP_STATUS dpp_tm_qmu_crs_filter_en_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 en) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_QCFG_QSCH_CRS_FILTER_T crs_filter_en = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, en, 0, 1); + + crs_filter_en.qcfg_qsch_crs_filter = en; + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QSCH_CRS_FILTERr, + 0, + 0, + &crs_filter_en); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + return DPP_OK; +} + + +/***********************************************************/ +/** 配置CRS发送强制使能 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param en 配置的值，0-不使能，1-使能 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/03/04 +************************************************************/ +DPP_STATUS dpp_tm_qmu_crs_force_en_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 en) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_QCFG_QSCH_CRS_FORCE_EN_T crs_force_en = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, en, 0, 1); + + crs_force_en.qcfg_qsch_crs_force_en = en; + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QSCH_CRS_FORCE_ENr, + 0, + 0, + &crs_force_en); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + return DPP_OK; +} + + +/***********************************************************/ +/** 配置CRS发送强制的队列 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param q_id 队列号 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/03/04 +************************************************************/ +DPP_STATUS dpp_tm_qmu_crs_force_q_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 q_id) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_QCFG_QSCH_CRS_FORCE_QNUM_T crs_force_q = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, q_id, 0, DPP_ETM_Q_NUM - 1); + + crs_force_q.qcfg_qsch_crs_force_qnum = q_id; + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QSCH_CRS_FORCE_QNUMr, + 0, + 0, + &crs_force_q); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + return DPP_OK; +} + + + +/***********************************************************/ +/** 配置CRS发送强置的状态 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param crs_state CRS发送强置的状态 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/06/18 +************************************************************/ +DPP_STATUS dpp_tm_qmu_crs_force_state_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 crs_state) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_QCFG_QSCH_CRS_FORCE_CRS_T crs_force_crs = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, crs_state, 0, 1); + + crs_force_crs.qcfg_qsch_crs_force_crs = crs_state; + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QSCH_CRS_FORCE_CRSr, + 0, + 0, + &crs_force_crs); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + return DPP_OK; +} + + +/***********************************************************/ +/** 配置特定队列发送特定CRS +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param qnum 队列号 +* qcfg_qsch_crs_force_crs:CRS状态(0：off；1：normal。) + qcfg_qsch_crs_force_en:CRS发送强置使能(0：不使能；1：使能。) +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/03/04 +************************************************************/ +DPP_STATUS dpp_tm_qmu_qnum_crs_force(ZXIC_UINT32 dev_id, + ZXIC_UINT32 qnum, + ZXIC_UINT32 qcfg_qsch_crs_force_crs, + ZXIC_UINT32 qcfg_qsch_crs_force_en) + +{ + DPP_STATUS rc = DPP_OK; + + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, qnum, 0, DPP_ETM_Q_NUM - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, qcfg_qsch_crs_force_en, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, qcfg_qsch_crs_force_crs, 0, 1); + + + rc = dpp_tm_qmu_crs_force_q_set(dev_id, qnum); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_crs_force_q_set"); + + rc = dpp_tm_qmu_crs_force_state_set(dev_id, qcfg_qsch_crs_force_crs); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_crs_force_state_set"); + + rc = dpp_tm_qmu_crs_force_en_set(dev_id, qcfg_qsch_crs_force_en); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_crs_force_en_set"); + + return DPP_OK; + +} + +/***********************************************************/ +/** 配置QMU空闲链表:TM独享模式 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param ddr_num ddr组数，1-8组 +* @param bank_vld bank有效信号 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cuiy @date 2016/06/07 +************************************************************/ +DPP_STATUS dpp_tm_qmu_qlist_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 ddr_num, + ZXIC_UINT32 bank_num_para, + ZXIC_UINT32 bank_vld, + ZXIC_UINT32 gene_para) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 k = 0; + ZXIC_UINT32 i = 0; + ZXIC_UINT32 j = 0; + ZXIC_UINT32 reg_index = 0; + ZXIC_UINT32 bdep_reg_index = 0; + ZXIC_UINT32 bhead_reg_index = 0; + ZXIC_UINT32 btail_reg_index = 0; + ZXIC_UINT32 qmu_cfgmt_ddr_in_mmu_index = 0; + ZXIC_UINT32 qmu_cfgmt_ddr_in_qmu_index = 0; + ZXIC_UINT32 qmu_cfgmt_bank_to_mmu_index = 0; + ZXIC_UINT32 qmu_cfgmt_bank_to_qmu_index = 0; + ZXIC_UINT32 qmu_cfgmt_active_to_bank_index = 0; + ZXIC_UINT32 qmu_qcfg_qlist_grp0_bank_index = 0; + ZXIC_UINT32 qmu_qcfg_qlist_grp1_bank_index = 0; + ZXIC_UINT32 qlist_grp0_bank_data[8] = {1, 2, 3, 4, 5, 6, 7, 0}; + DPP_ETM_QMU_QCFG_QLIST_BDEP_T qlist_bdep = {0}; + DPP_ETM_QMU_QCFG_QLIST_BHEAD_T qlist_bhead = {0}; + DPP_ETM_QMU_QCFG_QLIST_BTAIL_T qlist_btail = {0}; + DPP_ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFG_T active_to_bank_cfg = {0}; + DPP_ETM_QMU_CFGMT_DDR_IN_MMU_CFG_T ddr_in_mmu_cfg = {0}; + DPP_ETM_QMU_CFGMT_DDR_IN_QMU_CFG_T ddr_in_qmu_cfg = {0}; + DPP_ETM_QMU_CFGMT_BANK_TO_MMU_CFG_T bank_to_mmu_cfg = {0}; + DPP_ETM_QMU_CFGMT_BANK_TO_QMU_CFG_T bank_to_qmu_cfg = {0}; + DPP_ETM_QMU_QCFG_QLIST_GRP0_BANK_T qlist_grp0_bank = {0}; + DPP_ETM_QMU_QCFG_QLIST_GRP1_BANK_T qlist_grp1_bank = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, ddr_num, 1, 8); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, bank_num_para, 1, 8); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, bank_vld, 0, 1); + + bdep_reg_index = ETM_QMU_QCFG_QLIST_BDEPr; + bhead_reg_index = ETM_QMU_QCFG_QLIST_BHEADr; + btail_reg_index = ETM_QMU_QCFG_QLIST_BTAILr; + qmu_cfgmt_ddr_in_mmu_index = ETM_QMU_CFGMT_DDR_IN_MMU_CFGr; + qmu_cfgmt_ddr_in_qmu_index = ETM_QMU_CFGMT_DDR_IN_QMU_CFGr; + qmu_cfgmt_bank_to_mmu_index = ETM_QMU_CFGMT_BANK_TO_MMU_CFGr; + qmu_cfgmt_bank_to_qmu_index = ETM_QMU_CFGMT_BANK_TO_QMU_CFGr; + qmu_cfgmt_active_to_bank_index = ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFGr; + qmu_qcfg_qlist_grp0_bank_index = ETM_QMU_QCFG_QLIST_GRP0_BANKr; + qmu_qcfg_qlist_grp1_bank_index = ETM_QMU_QCFG_QLIST_GRP1_BANKr; + + /* cfgmt配置ddr_num组ddr */ + rc = dpp_tm_cfgmt_ddr_attach_set(dev_id, ddr_num); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_ddr_attach_set"); + + /* ddr组映射: qmu <--> mmu: ddr0~1 映射 0~1 */ + for (i = 0; i < ddr_num; i++) + { + /* qmu --> mmu */ + ddr_in_mmu_cfg.cfgmt_ddr_in_mmu_cfg = i; + rc = dpp_reg_write(dev_id, + qmu_cfgmt_ddr_in_mmu_index, + 0, + i, + &ddr_in_mmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + /* mmu --> qmu */ + ddr_in_qmu_cfg.cfgmt_ddr_in_qmu_cfg = i; + rc = dpp_reg_write(dev_id, + qmu_cfgmt_ddr_in_qmu_index, + 0, + i, + &ddr_in_qmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + + + /* qmu链表首尾指针及bank深度配置 */ + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "++++++dpp_tm_qmu_qlist_set starting++++++\n"); + + for (i = 0; i < ddr_num; i++) + { + for (j = 0; j < bank_num_para; j++) + { + reg_index = (i * 8 + j); + + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "++++++ reg_index=%d ++++++\n", reg_index); + + qlist_bdep.qcfg_qlist_bdep = gene_para; + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "++++++ qlist_bdep.qcfg_qlist_bdep=0x%x ++++++\n", qlist_bdep.qcfg_qlist_bdep); + rc = dpp_reg_write(dev_id, + bdep_reg_index, + 0, + reg_index, + &qlist_bdep); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + qlist_bhead.bank_vld = bank_vld; + qlist_bhead.qcfg_qlist_bhead = (gene_para * (i * bank_num_para + j)); + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "++++++ qlist_bhead.bank_vld=0x%x ++++++\n", qlist_bhead.bank_vld); + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "++++++ qlist_bhead.qcfg_qlist_bhead=0x%x ++++++\n", qlist_bhead.qcfg_qlist_bhead); + rc = dpp_reg_write(dev_id, + bhead_reg_index, + 0, + reg_index, + &qlist_bhead); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, gene_para , ((i * bank_num_para + j) + 1) ); + ZXIC_COMM_CHECK_DEV_INDEX_SUB_OVERFLOW_NO_ASSERT(dev_id, (gene_para * ((i * bank_num_para + j) + 1)) , 1 ); + qlist_btail.qcfg_qlist_btail = ((gene_para * ((i * bank_num_para + j) + 1)) - 1); + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "++++++ qlist_btail.qcfg_qlist_btail=0x%x ++++++\n", qlist_btail.qcfg_qlist_btail); + rc = dpp_reg_write(dev_id, + btail_reg_index, + 0, + reg_index, + &qlist_btail); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "++++++ j=%d ++++++\n", j); + + if (j != 8 ) + { + for (k = bank_num_para; k < 8; k++) + { + reg_index = (i * 8 + k); + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "++++++ reg_index=%d ++++++\n", reg_index); + qlist_bhead.bank_vld = 0; + qlist_bhead.qcfg_qlist_bhead = 0; + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "++++++ qlist_bhead.bank_vld=0x%x ++++++\n", qlist_bhead.bank_vld); + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "++++++ qlist_bhead.qcfg_qlist_bhead=0x%x ++++++\n", qlist_bhead.qcfg_qlist_bhead); + rc = dpp_reg_write(dev_id, + bhead_reg_index, + 0, + reg_index, + &qlist_bhead); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + } + } + + + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "++++++ i=%d ++++++\n", i); + + if (i != 8 ) + { + for (k = ddr_num; k < 8; k++) + { + for (j = 0; j < 8; j++) + { + reg_index = (k * 8 + j); + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "++++++ reg_index=%d ++++++\n", reg_index); + qlist_bhead.bank_vld = 0; + qlist_bhead.qcfg_qlist_bhead = 0; + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "++++++ qlist_bhead.bank_vld=0x%x ++++++\n", qlist_bhead.bank_vld); + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "++++++ qlist_bhead.qcfg_qlist_bhead=0x%x ++++++\n", qlist_bhead.qcfg_qlist_bhead); + rc = dpp_reg_write(dev_id, + bhead_reg_index, + 0, + reg_index, + &qlist_bhead); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + } + } + + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "++++++dpp_tm_qmu_qlist_set end++++++\n"); + + /*** bank号映射： + qmu-->mmu: bank0~7 映射 bank0~7 + mmu-->qmu: bank0~7 映射 bank0~7 *****/ + for (j = 0; j < ddr_num; j++) + { + for (i = 0; i < bank_num_para; i++) + { + /* qmu-->mmu: bank0~7 映射 bank0~7 */ + k = j * 8 + i; + bank_to_mmu_cfg.cfgmt_bank_in_mmu_cfg = i; + rc = dpp_reg_write(dev_id, + qmu_cfgmt_bank_to_mmu_index, + 0, + k, + &bank_to_mmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + /* mmu-->qmu: bank0~7 映射 bank0~7 */ + bank_to_qmu_cfg.cfgmt_bank_in_qmu_cfg = i; + + rc = dpp_reg_write(dev_id, + qmu_cfgmt_bank_to_qmu_index, + 0, + k, + &bank_to_qmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + } + + /* random映射ram */ + for (j = 0; j < ddr_num; j++) + { + for (i = 0; i < bank_num_para; i++) + { + k = j * bank_num_para + i; + + active_to_bank_cfg.cfgmt_active_to_bank_cfg = i; + + rc = dpp_reg_write(dev_id, + qmu_cfgmt_active_to_bank_index, + 0, + k, + &active_to_bank_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + } + + + /* 随机表配置，决定每组bank的轮询顺序 */ + for (j = 0; j < ddr_num; j++) + { + for (i = 0; i < bank_num_para; i++) + { + k = j * 8 + i; + + qlist_grp0_bank.qcfg_qlist_grp0_bank_wr = qlist_grp0_bank_data[i]; + + rc = dpp_reg_write(dev_id, + qmu_qcfg_qlist_grp0_bank_index, + 0, + k, + &qlist_grp0_bank); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + } + } + + for (j = 0; j < ddr_num; j++) + { + for (i = 0; i < bank_num_para; i++) + { + k = j * 8 + i; + + qlist_grp1_bank.qcfg_qlist_grp1_bank_wr = qlist_grp0_bank_data[i]; + + rc = dpp_reg_write(dev_id, + qmu_qcfg_qlist_grp1_bank_index, + 0, + k, + &qlist_grp1_bank); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + } + } + + /* qmu配置完成 */ + rc = dpp_tm_qmu_cfg_done_set(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_cfg_done_set"); + + return DPP_OK; +} + + +/***********************************************************/ +/** QMU DDR随机模式时，DDR随机组配置 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param ddr_num ddr组数，1-6组 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/03/04 +************************************************************/ +DPP_STATUS dpp_tm_qmu_ddr_rand_grp_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 ddr_num) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 i = 0; + ZXIC_UINT32 bank_no[6][16] = {{0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7}, + {0, 8, 1, 9, 2, 10, 3, 11, 4, 12, 5, 13, 6, 14, 7, 15}, + {0, 8, 16, 1, 9, 17, 2, 10, 18, 3, 11, 19, 4, 12, 20, 5}, + {0, 8, 16, 24, 1, 9, 17, 25, 2, 10, 18, 26, 3, 11, 19, 27}, + {0, 8, 16, 24, 32, 1, 9, 17, 25, 33, 2, 10, 18, 26, 34, 3}, + {0, 8, 16, 24, 32, 40, 1, 9, 17, 25, 33, 41, 2, 10, 18, 26} + }; + + DPP_ETM_QMU_QCFG_QLIST_GRP_T grp = {0}; + DPP_ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFG_T bank = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, ddr_num, 1, 6); + + for (i = 0; i < 64; i++) + { + grp.qcfg_qlist_grp_wr = i % ddr_num; + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_GRPr, + 0, + i, + &grp); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + for (i = 0; i < 16; i++) + { + bank.cfgmt_active_to_bank_cfg = bank_no[ddr_num - 1][i]; + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFGr, + 0, + i, + &bank); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + return DPP_OK; +} + + +/***********************************************************/ +/** 配置QMU DDR BANK随机模式 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param ddr_random 模式:0-轮询模式；1-随机模式 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/03/04 +************************************************************/ +DPP_STATUS dpp_tm_qmu_ddr_random_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 ddr_random) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_QCFG_QLIST_DDR_RANDOM_T ddr_rand = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, ddr_random, 0, 1); + + ddr_rand.qcfg_qlist_ddr_random = ddr_random; + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_DDR_RANDOMr, + 0, + 0, + &ddr_rand); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + return DPP_OK; +} + + +/***********************************************************/ +/** 配置QMU DDR BANK随机模式 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_ddr_random 模式:0-轮询模式；1-随机模式 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/03/04 +************************************************************/ +DPP_STATUS dpp_tm_qmu_ddr_random_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_ddr_random) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_QCFG_QLIST_DDR_RANDOM_T ddr_rand = {0}; + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_ddr_random); + + rc = dpp_reg_read(dev_id, + ETM_QMU_QCFG_QLIST_DDR_RANDOMr, + 0, + 0, + &ddr_rand); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + *p_ddr_random = ddr_rand.qcfg_qlist_ddr_random; + + return DPP_OK; +} + + +/***********************************************************/ +/** QMU配置完成寄存器，在QMU链表和DDR随机模式寄存器写入后，将此寄存器写1，完成QMU配置 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cuiy @date 2016/05/08 +************************************************************/ +DPP_STATUS dpp_tm_qmu_cfg_done_set(ZXIC_UINT32 dev_id) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_QCFG_QLIST_CFG_DONE_T cfg_done = {0}; + + cfg_done.qcfg_qlist_cfg_done = 1; + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_CFG_DONEr, + 0, + 0, + &cfg_done); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + return DPP_OK; +} + +/***********************************************************/ +/** 配置CRS的e桶产生的crbal门限值 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param index crs组数：0~15 +* @param crs_th CRS产生的crbal门限值 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author xuhb @date 2021/02/14 +************************************************************/ +DPP_STATUS dpp_tm_qmu_crs_eir_th_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 index, + ZXIC_UINT32 crs_th) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_QCFG_QSCH_CRS_EIR_TH_T crs_eir_th = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, index, 0, 0xf); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, crs_th, 0, 0x3ffff); + + crs_eir_th.qcfg_qsch_crs_eir_th = crs_th; + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QSCH_CRS_EIR_THr, + 0, + index, + &crs_eir_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + return DPP_OK; +} + + +/***********************************************************/ +/** 配置CRS产生的crbal门限值 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param index crs组数：0~15 +* @param crs_th CRS产生的crbal门限值 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/03/11 +************************************************************/ +DPP_STATUS dpp_tm_qmu_crs_th_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 index, + ZXIC_UINT32 crs_th) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_QCFG_QSCH_CRS_TH1_T crs_th1 = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, index, 0, 0xf); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, crs_th, 0, 0xffffffff); + + crs_th1.qcfg_qsch_crs_th1 = crs_th; + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QSCH_CRS_TH1r, + 0, + index, + &crs_th1); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + return DPP_OK; +} + +/***********************************************************/ +/** 配置CRS产生的空队列确保门限值 +* @param dev_id 设备索引编号 +* @param tm_type 0-ETM,1-FTM +* @param que_type 队列类型编号(0~15) +* @param empty_que_ack_th 空队列确保授权门限 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/03/09 +************************************************************/ +DPP_STATUS dpp_tm_qmu_crs_th2_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 que_type, + ZXIC_UINT32 empty_que_ack_th) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_QCFG_QSCH_CRS_TH2_T crs_th2 = {0}; + ZXIC_UINT32 rem_bit_sum = 4; + ZXIC_UINT32 rem = 0; + ZXIC_UINT32 exp = 0; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, que_type, 0, 15); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, empty_que_ack_th, 0, 0x78000); + + rc = dpp_tm_rem_and_exp_translate(empty_que_ack_th, + rem_bit_sum, + &rem, + &exp); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + crs_th2.qcfg_qsch_crs_th2 = (rem << 4) + (exp & 0xf); + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QSCH_CRS_TH2r, + 0, + que_type, + &crs_th2); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + return DPP_OK; +} + +/***********************************************************/ +/** 配置CRS发送的速率 +* @param dev_id 设备索引编号 +* @param tm_type 0-ETM,1-FTM +* @param sent_cyc CRS发送的间隔(单位:时钟周期) +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author szq @date 2015/03/25 +************************************************************/ +DPP_STATUS dpp_tm_qmu_crs_sent_rate_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 sent_cyc) +{ + DPP_STATUS rc = DPP_OK; + + DPP_ETM_QMU_CFGMT_CRS_INTERVAL_T crs_interval = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, sent_cyc, 1, 0xffffffff); + + crs_interval.cfgmt_crs_interval = sent_cyc; + + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_CRS_INTERVALr, + 0, + 0, + &crs_interval); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + return DPP_OK; +} + +/***********************************************************/ +/** 获取CRS发送的速率 +* @param dev_id 设备索引编号 +* @param tm_type 0-ETM,1-FTM +* @param p_sent_cyc CRS发送的间隔(单位:时钟周期) +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author szq @date 2015/03/25 +************************************************************/ +DPP_STATUS dpp_tm_qmu_crs_sent_rate_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_sent_cyc) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_CFGMT_CRS_INTERVAL_T crs_interval = {0}; + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_sent_cyc); + + + *p_sent_cyc = 0; + + rc = dpp_reg_read(dev_id, + ETM_QMU_CFGMT_CRS_INTERVALr, + 0, + 0, + &crs_interval); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + *p_sent_cyc = crs_interval.cfgmt_crs_interval; + + return DPP_OK; +} + +/***********************************************************/ +/** 配置QMU端口间交织模式 +* @param dev_id 设备索引编号 +* @param tm_type 0-ETM,1-FTM +* @param pkt_blk_mode 交织模式: 1-按包交织; 0-按block交织 SA模式只能配置为1 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author szq @date 2015/03/25 +************************************************************/ +DPP_STATUS dpp_tm_qmu_pkt_blk_mode_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 pkt_blk_mode) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_QCFG_CSW_PKT_BLK_MODE_T csw_pkt_blk_mode = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pkt_blk_mode, 0, 1); + + csw_pkt_blk_mode.qcfg_csw_pkt_blk_mode = pkt_blk_mode; + + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_CSW_PKT_BLK_MODEr, + 0, + 0, + &csw_pkt_blk_mode); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + return DPP_OK; +} + +/***********************************************************/ +/** 获取QMU端口间交织模式 +* @param dev_id 设备索引编号 +* @param tm_type 0-ETM,1-FTM +* @param p_pkt_blk_mode 交织模式: 0-按包交织 ; 1-按block交织SA模式只能配置为1 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author szq @date 2015/03/25 +************************************************************/ +DPP_STATUS dpp_tm_qmu_pkt_blk_mode_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_pkt_blk_mode) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_QCFG_CSW_PKT_BLK_MODE_T csw_pkt_blk_mode = {0}; + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_pkt_blk_mode); + + *p_pkt_blk_mode = 0; + + rc = dpp_reg_read(dev_id, + ETM_QMU_QCFG_CSW_PKT_BLK_MODEr, + 0, + 0, + &csw_pkt_blk_mode); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + *p_pkt_blk_mode = csw_pkt_blk_mode.qcfg_csw_pkt_blk_mode; + + return DPP_OK; +} + +/***********************************************************/ +/** 配置SA模式下各个版本的授权价值 +* @param dev_id 设备索引编号 +* @param tm_type 0-ETM,1-FTM +* @param sa_ver_id 版本号(0~7) +* @param sa_credit_value 授权价值 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author szq @date 2015/03/25 +************************************************************/ +DPP_STATUS dpp_tm_qmu_sa_credit_value_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 sa_ver_id, + ZXIC_UINT32 sa_credit_value) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_0_T qmu_sa_credit_value = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, sa_ver_id, 0, 7); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, sa_credit_value, 0, 0x3ffff); + + qmu_sa_credit_value.cfg_qsch_sa_credit_value_0 = sa_credit_value; + rc = dpp_reg_write(dev_id, + ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_0r + sa_ver_id, + 0, + 0, + &qmu_sa_credit_value); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + return DPP_OK; +} + +/***********************************************************/ +/** 获取SA模式下各个版本的授权价值 +* @param dev_id 设备索引编号 +* @param tm_type 0-ETM,1-FTM +* @param sa_ver_id 版本号(0~7) +* @param p_sa_credit_value 授权价值 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author szq @date 2015/03/25 +************************************************************/ +DPP_STATUS dpp_tm_qmu_sa_credit_value_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 sa_ver_id, + ZXIC_UINT32 *p_sa_credit_value) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_0_T qmu_sa_credit_value = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, sa_ver_id, 0, 7); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_sa_credit_value); + + *p_sa_credit_value = 0; + + rc = dpp_reg_read(dev_id, + ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_0r + sa_ver_id, + 0, + 0, + &qmu_sa_credit_value); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + *p_sa_credit_value = qmu_sa_credit_value.cfg_qsch_sa_credit_value_0; + + return DPP_OK; +} + +/***********************************************************/ +/** 配置多播授权令牌添加个数 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param token_add_num 令牌添加时，每次增加的令牌数目，取值范围为1~255，默认为1；禁止配置为0，配置为0时，将不会产生授权。 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/03/09 +************************************************************/ +DPP_STATUS dpp_tm_qmu_mul_token_gen_num_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 token_add_num) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_CFG_QSCH_MUL_TOKEN_GEN_NUM_T token_gen_num = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, token_add_num, 1, 255); + + token_gen_num.cfg_qsch_mul_token_gen_num = token_add_num; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFG_QSCH_MUL_TOKEN_GEN_NUMr, + 0, + 0, + &token_gen_num); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + return DPP_OK; +} + +/***********************************************************/ +/** 配置多播授权整形桶参数和使能参数 +* @param dev_id 设备索引编号 +* @param tm_type 0-ETM,1-FTM +* @param q3_lb_control_en 3号队列整形功能开启使能。0：关闭；1：开启。 +* @param q012_lb_control_en 0～2号队列整形功能开启使能。0：关闭；1：开启。 +* @param q3_lb_max_cnt 3号队列整形桶桶深。 +* @param q012_lb_max_cnt 0～2号队列整形桶桶深。 +* @param q3_lb_add_rate 3号队列令牌添加速率，时钟周期为单位。不可配置为0，配置为0整形使能时，不能产生队列3授权调度信号。 +* @param q012_lb_add_rate 0～2号队列令牌添加速率，以时钟周期单位。不可配置为0，配置为0并整形使能时，不能产生队列0、1、2授权调度信号。 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/03/09 +************************************************************/ +DPP_STATUS dpp_tm_qmu_mul_ack_lb_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 q3_lb_control_en, + ZXIC_UINT32 q012_lb_control_en, + ZXIC_UINT32 q3_lb_max_cnt, + ZXIC_UINT32 q012_lb_max_cnt, + ZXIC_UINT32 q3_lb_add_rate, + ZXIC_UINT32 q012_lb_add_rate) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 q3_crdt_lb_ctrl_en_reg_index = 0; + ZXIC_UINT32 q012_crdt_lb_ctrl_en_reg_index = 0; + ZXIC_UINT32 q3_crdt_lb_max_cnt_reg_index = 0; + ZXIC_UINT32 q012_crdt_lb_max_cnt_reg_index = 0; + ZXIC_UINT32 q3_crdt_lb_add_rate_reg_index = 0; + ZXIC_UINT32 q012_crdt_lb_add_rate_reg_index = 0; + DPP_ETM_QMU_CFG_QSCH_Q3_CREDIT_LB_CONTROL_EN_T q3_en = {0}; + DPP_ETM_QMU_CFG_QSCH_Q012_CREDIT_LB_CONTROL_EN_T q012_en = {0}; + DPP_ETM_QMU_CFG_QSCH_Q3CREDITLBMAXCNT_T q3_max_cnt = {0}; + DPP_ETM_QMU_CFG_QSCH_Q012CREDITLBMAXCNT_T q012_max_cnt = {0}; + DPP_ETM_QMU_CFG_QSCH_Q3LBADDRATE_T q3_rate = {0}; + DPP_ETM_QMU_CFG_QSCH_Q012LBADDRATE_T q012_rate = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX_NONE(dev_id, q3_lb_control_en, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX_NONE(dev_id, q012_lb_control_en, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX_NONE(dev_id, q3_lb_max_cnt, 0, 0xff); + ZXIC_COMM_CHECK_DEV_INDEX_NONE(dev_id, q012_lb_max_cnt, 0, 0xff); + ZXIC_COMM_CHECK_DEV_INDEX_NONE(dev_id, q3_lb_add_rate, 0, 0xfffffff); + ZXIC_COMM_CHECK_DEV_INDEX_NONE(dev_id, q012_lb_add_rate, 0, 0xfffffff); + + q3_crdt_lb_ctrl_en_reg_index = ETM_QMU_CFG_QSCH_Q3_CREDIT_LB_CONTROL_ENr; + q012_crdt_lb_ctrl_en_reg_index = ETM_QMU_CFG_QSCH_Q012_CREDIT_LB_CONTROL_ENr; + q3_crdt_lb_max_cnt_reg_index = ETM_QMU_CFG_QSCH_Q3CREDITLBMAXCNTr; + q012_crdt_lb_max_cnt_reg_index = ETM_QMU_CFG_QSCH_Q012CREDITLBMAXCNTr; + q3_crdt_lb_add_rate_reg_index = ETM_QMU_CFG_QSCH_Q3LBADDRATEr; + q012_crdt_lb_add_rate_reg_index = ETM_QMU_CFG_QSCH_Q012LBADDRATEr; + + q3_en.cfg_qsch_q3_credit_lb_control_en = q3_lb_control_en; + rc = dpp_reg_write(dev_id, + q3_crdt_lb_ctrl_en_reg_index, + 0, + 0, + &q3_en); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + q012_en.cfg_qsch_q012_credit_lb_control_en = q012_lb_control_en; + rc = dpp_reg_write(dev_id, + q012_crdt_lb_ctrl_en_reg_index, + 0, + 0, + &q012_en); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + q3_max_cnt.cfg_qsch_q3creditlbmaxcnt = q3_lb_max_cnt; + rc = dpp_reg_write(dev_id, + q3_crdt_lb_max_cnt_reg_index, + 0, + 0, + &q3_max_cnt); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + q012_max_cnt.cfg_qsch_q012creditlbmaxcnt = q012_lb_max_cnt; + rc = dpp_reg_write(dev_id, + q012_crdt_lb_max_cnt_reg_index, + 0, + 0, + &q012_max_cnt); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + q3_rate.cfg_qsch_q3lbaddrate = q3_lb_add_rate; + rc = dpp_reg_write(dev_id, + q3_crdt_lb_add_rate_reg_index, + 0, + 0, + &q3_rate); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + q012_rate.cfg_qsch_q012lbaddrate = q012_lb_add_rate; + rc = dpp_reg_write(dev_id, + q012_crdt_lb_add_rate_reg_index, + 0, + 0, + &q012_rate); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + return DPP_OK; +} + +/***********************************************************/ +/** 配置0,1号队列挂接1或2号MCN漏桶信息 +* @param tm_type 0-ETM,1-FTM +* @param dev_id 设备索引编号 +* @param mcn_lb_sel 0：0,1号队列挂接1号MCN漏桶 1：0,1号队列挂接2号MCN漏桶 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/03/09 +************************************************************/ +DPP_STATUS dpp_tm_qmu_mcn_lb_sel_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 mcn_lb_sel) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_CFG_QSCH_Q01_ATTACH_EN_T q01_attach_en = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, mcn_lb_sel, 0, 1); + + q01_attach_en.cfg_qsch_q01_attach_en = mcn_lb_sel; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFG_QSCH_Q01_ATTACH_ENr, + 0, + 0, + &q01_attach_en); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + return DPP_OK; +} + +/***********************************************************/ +/** 配置多播队列0~2的授权输出SP、DWRR +* @param dev_id 设备索引编号 +* @param tm_type 0-ETM,1-FTM +* @param sp_or_dwrr SP、DWRR模式选择。0：SP；1：DWRR。 +* @param dwrr_w0 0号队列DWRR权重(0~127) +* @param dwrr_w1 1号队列DWRR权重(0~127) +* @param dwrr_w2 2号队列DWRR权重(0~127) +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/03/09 +************************************************************/ +DPP_STATUS dpp_tm_qmu_mul_sp_dwrr_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 sp_or_dwrr, + ZXIC_UINT32 dwrr_w0, + ZXIC_UINT32 dwrr_w1, + ZXIC_UINT32 dwrr_w2) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_CFG_QSCH_SP_DWRR_EN_T sp_dwrr_en = {0}; + DPP_ETM_QMU_CFG_QSCH_W0_T qsch_w0 = {0}; + DPP_ETM_QMU_CFG_QSCH_W1_T qsch_w1 = {0}; + DPP_ETM_QMU_CFG_QSCH_W2_T qsch_w2 = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, sp_or_dwrr, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, dwrr_w0, 0, 0x7f); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, dwrr_w1, 0, 0x7f); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, dwrr_w2, 0, 0x7f); + + sp_dwrr_en.cfg_qsch_sp_dwrr_en = sp_or_dwrr; + rc = dpp_reg_write(dev_id, + ETM_QMU_CFG_QSCH_SP_DWRR_ENr, + 0, + 0, + &sp_dwrr_en); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + qsch_w0.cfg_qsch_w0 = dwrr_w0; + rc = dpp_reg_write(dev_id, + ETM_QMU_CFG_QSCH_W0r, + 0, + 0, + &qsch_w0); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + qsch_w1.cfg_qsch_w1 = dwrr_w1; + rc = dpp_reg_write(dev_id, + ETM_QMU_CFG_QSCH_W1r, + 0, + 0, + &qsch_w1); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + qsch_w2.cfg_qsch_w2 = dwrr_w2; + rc = dpp_reg_write(dev_id, + ETM_QMU_CFG_QSCH_W2r, + 0, + 0, + &qsch_w2); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + return DPP_OK; +} + +/***********************************************************/ +/** 配置分目的SA整形打开或关闭 +* @param dev_id 设备索引编号 +* @param tm_type 0-ETM,1-FTM +* @param shap_en 分目的SA整形使能开关 0：表示关闭 1：表示打开 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/03/09 +************************************************************/ +DPP_STATUS dpp_tm_qmu_dest_sa_shap_en_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 shap_en) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_CFGMT_QMU_SASHAP_EN_T sa_shap_en = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, shap_en, 0, 1); + + sa_shap_en.cfgmt_qmu_sashap_en = shap_en; + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_QMU_SASHAP_ENr, + 0, + 0, + &sa_shap_en); + + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + return DPP_OK; +} + +/***********************************************************/ +/** 配置轮转扫描使能和扫描速率 +* @param dev_id 设备索引编号 +* @param tm_type 0-ETM,1-FTM +* @param scan_en 轮转扫描使能。0：关闭，1：开启 +* @param scan_rate 轮转扫描速率，配置扫描周期不得少于256个周期 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/03/10 +************************************************************/ +DPP_STATUS dpp_tm_qmu_scan_rate_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 scan_en, + ZXIC_UINT32 scan_rate) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_CFG_QSCH_SCAN_EN_T qsch_scan_en = {0}; + DPP_ETM_QMU_CFG_QSCH_SCANRATE_T qsch_scanrate = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, scan_en, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, scan_rate, 0x100, 0xfffff); + + + qsch_scan_en.cfg_qsch_scan_en = scan_en; + rc = dpp_reg_write(dev_id, + ETM_QMU_CFG_QSCH_SCAN_ENr, + 0, + 0, + &qsch_scan_en); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + qsch_scanrate.cfg_qsch_scanrate = scan_rate; + rc = dpp_reg_write(dev_id, + ETM_QMU_CFG_QSCH_SCANRATEr, + 0, + 0, + &qsch_scanrate); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + return DPP_OK; +} + +/***********************************************************/ +/** 获得轮转扫描使能和扫描速率 +* @param dev_id 设备索引编号 +* @param tm_type 0-ETM,1-FTM +* @param scan_en 轮转扫描使能。0：关闭，1：开启 +* @param scan_rate 轮转扫描速率，配置扫描周期不得少于256个周期 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/03/10 +************************************************************/ +DPP_STATUS dpp_tm_qmu_scan_rate_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *p_scan_en, + ZXIC_UINT32 *p_scan_rate) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_CFG_QSCH_SCAN_EN_T qsch_scan_en = {0}; + DPP_ETM_QMU_CFG_QSCH_SCANRATE_T qsch_scanrate = {0}; + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_scan_en); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_scan_rate); + + + rc = dpp_reg_read(dev_id, + ETM_QMU_CFG_QSCH_SCAN_ENr, + 0, + 0, + &qsch_scan_en); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + *p_scan_en = qsch_scan_en.cfg_qsch_scan_en; + + rc = dpp_reg_read(dev_id, + ETM_QMU_CFG_QSCH_SCANRATEr, + 0, + 0, + &qsch_scanrate); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + *p_scan_rate = qsch_scanrate.cfg_qsch_scanrate; + + return DPP_OK; + + +} + +/***********************************************************/ +/** 配置轮转扫描队列范围 +* @param dev_id 设备索引编号 +* @param tm_type 0-ETM,1-FTM +* @param first_que 起始队列号 +* @param last_que 终止队列号 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author whuashan @date 2019/09/10 +************************************************************/ +DPP_STATUS dpp_tm_qmu_scan_que_range_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 first_que, + ZXIC_UINT32 last_que) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_CFG_QSCH_SCANFRSTQUE_T qsch_scanfirstque_t = {0}; + DPP_ETM_QMU_CFG_QSCH_SCANLASTQUE_T qsch_scanlastque_t = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, first_que, 0, DPP_ETM_Q_NUM - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, last_que, 0, DPP_ETM_Q_NUM - 1); + + qsch_scanfirstque_t.cfg_qsch_scanfrstque = first_que; + qsch_scanlastque_t.cfg_qsch_scanlastque = last_que; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFG_QSCH_SCANFRSTQUEr, + 0, + 0, + &qsch_scanfirstque_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFG_QSCH_SCANLASTQUEr, + 0, + 0, + &qsch_scanlastque_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + return DPP_OK; + +} + +/***********************************************************/ +/** 获取轮转扫描队列范围 +* @param dev_id 设备索引编号 +* @param tm_type 0-ETM,1-FTM +* @param first_que 起始队列号 +* @param last_que 终止队列号 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author whuashan @date 2019/09/10 +************************************************************/ +DPP_STATUS dpp_tm_qmu_scan_que_range_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *first_que, + ZXIC_UINT32 *last_que) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_CFG_QSCH_SCANFRSTQUE_T qsch_scanfirstque_t = {0}; + DPP_ETM_QMU_CFG_QSCH_SCANLASTQUE_T qsch_scanlastque_t = {0}; + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, first_que); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, last_que); + + rc = dpp_reg_read(dev_id, + ETM_QMU_CFG_QSCH_SCANFRSTQUEr, + 0, + 0, + &qsch_scanfirstque_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + rc = dpp_reg_read(dev_id, + ETM_QMU_CFG_QSCH_SCANLASTQUEr, + 0, + 0, + &qsch_scanlastque_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + *first_que = qsch_scanfirstque_t.cfg_qsch_scanfrstque; + *last_que = qsch_scanlastque_t.cfg_qsch_scanlastque; + + return DPP_OK; + +} +#endif + +/***********************************************************/ +/** 配置读命令老化使能 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param aged_en 读命令老化使能：0：不使能；1：使能 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/03/11 +************************************************************/ +DPP_STATUS dpp_tm_qmu_wr_aged_en_set(DPP_DEV_T *dev, ZXIC_UINT32 aged_en) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_QCFG_CSCH_AGED_CFG_T aged_cfg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), aged_en, 0, 1); + + + aged_cfg.qcfg_csch_aged_cfg = aged_en; + + rc = dpp_reg_write(dev, + ETM_QMU_QCFG_CSCH_AGED_CFGr, + 0, + 0, + &aged_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + return DPP_OK; +} + +/***********************************************************/ +/** 配置读命令老化速率 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param scan_time 读命令老化速率（扫描间隔时间） +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/03/11 +************************************************************/ +DPP_STATUS dpp_tm_qmu_wr_aged_scan_time_set(DPP_DEV_T *dev, ZXIC_UINT32 scan_time) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_QCFG_CSCH_AGED_SCAN_TIME_T aged_scan_time = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), scan_time, 0, 0xffffffff); + + aged_scan_time.qcfg_csch_aged_scan_time = scan_time; + + rc = dpp_reg_write(dev, + ETM_QMU_QCFG_CSCH_AGED_SCAN_TIMEr, + 0, + 0, + &aged_scan_time); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + return DPP_OK; +} + +/***********************************************************/ +/** 获得读命令老化速率 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_scan_time 读命令老化速率（扫描间隔时间） +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/03/11 +************************************************************/ +DPP_STATUS dpp_tm_qmu_wr_aged_scan_time_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_scan_time) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_QCFG_CSCH_AGED_SCAN_TIME_T aged_scan_time = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_scan_time); + + rc = dpp_reg_read(dev, + ETM_QMU_QCFG_CSCH_AGED_SCAN_TIMEr, + 0, + 0, + &aged_scan_time); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + *p_scan_time = aged_scan_time.qcfg_csch_aged_scan_time; + + return DPP_OK; +} + + +/***********************************************************/ +/** 获取QMU清空状态 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_clr_done_flag 队列是否清空完成 +* +* @return +* @remark 无 +* @see +* @author szq @date 2015/05/21 +************************************************************/ +DPP_STATUS dpp_tm_qmu_qlist_qcfg_clr_done_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_clr_done_flag) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_QLIST_QCFG_CLR_DONE_T clr_done_flag = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_clr_done_flag); + + + rc = dpp_reg_read(dev, + ETM_QMU_QLIST_QCFG_CLR_DONEr, + 0, + 0, + &clr_done_flag); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + *p_clr_done_flag = clr_done_flag.qlist_qcfg_clr_done; + + return DPP_OK; +} + +/***********************************************************/ +/** 配置qsch调度分端口整形速率和使能 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param shape_en 整形使能 +* @param token_add_num [23:12]:添加令牌数目 +* @param token_gap [11:0]:添加令牌间隔，其中实际间隔为配置间隔+1 +* @param token_depth 桶深，单位B,范围[0-0x1EE00] +*公式：（1000*8*token_num）/(gap+1) = X Mbps +* 主频= 600 MHz +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author xuhb 2020-5-15 +************************************************************/ +DPP_STATUS dpp_tm_qmu_qsch_port_shape_set(DPP_DEV_T *dev, + ZXIC_UINT32 port_id, + ZXIC_UINT32 token_add_num, + ZXIC_UINT32 token_gap, + ZXIC_UINT32 token_depth, + ZXIC_UINT32 shape_en) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_QCFG_QSCH_SHAP_PARAM_T qsch_shap_param = {0}; + DPP_ETM_QMU_QCFG_QSCH_SHAP_TOKEN_T qsch_shap_token_depth = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), port_id, 0, DPP_TM_PP_NUM - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), shape_en, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), token_add_num, 0, 0xfff); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), token_gap, 0, 0xfff); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), token_depth, 0, 0x1f000); + + /* 配置整形桶深 */ + qsch_shap_token_depth.qcfg_qsch_shap_token= token_depth; + rc = dpp_reg_write(dev, + ETM_QMU_QCFG_QSCH_SHAP_TOKENr, + 0, + port_id, + &qsch_shap_token_depth); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + qsch_shap_param.qcfg_qsch_shap_en = shape_en; + qsch_shap_param.qcfg_qsch_shap_param1= token_add_num ; + qsch_shap_param.qcfg_qsch_shap_param2= token_gap; + rc = dpp_reg_write(dev, + ETM_QMU_QCFG_QSCH_SHAP_PARAMr, + 0, + port_id, + &qsch_shap_param); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + + return DPP_OK; + +} + + +/***********************************************************/ +/** 配置CMD_SW分端口整形速率和使能 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param shape_en 整形使能 +* @param token_add_num [23:12]:添加令牌数目 +* @param token_gap [11:0]:添加令牌间隔，其中实际间隔为配置间隔+1 +* @param token_depth 桶深，单位B,范围[0-0x1EE00] +*公式：（1000*8*token_num）/(gap+1) = X Mbps +* 主频= 600 MHz +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author whuashan 2020-3-17 +************************************************************/ +DPP_STATUS dpp_tm_qmu_port_shape_set(DPP_DEV_T *dev, + ZXIC_UINT32 port_id, + ZXIC_UINT32 token_add_num, + ZXIC_UINT32 token_gap, + ZXIC_UINT32 token_depth, + ZXIC_UINT32 shape_en) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_QCFG_CSW_SHAP_PARAMETER_T csw_shap_param = {0}; + DPP_ETM_QMU_QCFG_CSW_SHAP_TOKEN_DEPTH_T csw_shap_token_depth = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), port_id, 0, DPP_TM_PP_NUM - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), shape_en, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), token_add_num, 0, 0xfff); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), token_gap, 0, 0xfff); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), token_depth, 0, 0x1ee00); + + /* 配置整形桶深 */ + csw_shap_token_depth.qcfg_csw_shap_token_depth = token_depth; + rc = dpp_reg_write(dev, + ETM_QMU_QCFG_CSW_SHAP_TOKEN_DEPTHr, + 0, + port_id, + &csw_shap_token_depth); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + csw_shap_param.qcfg_csw_shap_en = shape_en; + csw_shap_param.qcfg_csw_shap_parameter = (token_add_num << 12) | token_gap; + rc = dpp_reg_write(dev, + ETM_QMU_QCFG_CSW_SHAP_PARAMETERr, + 0, + port_id, + &csw_shap_param); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + return DPP_OK; + +} + +/***********************************************************/ +/** 获得CMD_SW分端口整形速率和使能 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_shape_en 整形使能 +* @param p_token_add_num [23:12]:添加令牌数目 +* @param p_token_gap [11:0]:添加令牌间隔，其中实际间隔为配置间隔+1 +* @param p_token_depth 桶深，单位B +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author whuashan 2020-3-17 +************************************************************/ +DPP_STATUS dpp_tm_qmu_port_shape_get(DPP_DEV_T *dev, + ZXIC_UINT32 port_id, + ZXIC_UINT32 *p_token_add_num, + ZXIC_UINT32 *p_token_gap, + ZXIC_UINT32 *p_token_depth, + ZXIC_UINT32 *p_shape_en) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_QCFG_CSW_SHAP_PARAMETER_T csw_shap_param = {0}; + DPP_ETM_QMU_QCFG_CSW_SHAP_TOKEN_DEPTH_T csw_shap_token_depth = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), port_id, 0, DPP_TM_PP_NUM - 1); + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_token_add_num); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_token_gap); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_token_depth); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_shape_en); + + rc = dpp_reg_read(dev, + ETM_QMU_QCFG_CSW_SHAP_PARAMETERr, + 0, + port_id, + &csw_shap_param); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + *p_shape_en = csw_shap_param.qcfg_csw_shap_en; + *p_token_add_num = (csw_shap_param.qcfg_csw_shap_parameter >> 12) & 0xfff; + *p_token_gap = csw_shap_param.qcfg_csw_shap_parameter & 0xfff; + + rc = dpp_reg_read(dev, + ETM_QMU_QCFG_CSW_SHAP_TOKEN_DEPTHr, + 0, + port_id, + &csw_shap_token_depth); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + *p_token_depth = csw_shap_token_depth.qcfg_csw_shap_token_depth; + + return DPP_OK; + +} + +#if 0 +/***********************************************************/ +/** 配置CMD_SW分端口(qmu出端口)整形速率和使能 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param shape_cir 整形值，单位Mbps，范围[0-160000] +* @param shape_cbs 桶深， 单位B，范围[0-0x1EE00] +* @param shape_en 整形使能 +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author whuashan 2020-3-17 +************************************************************/ +DPP_STATUS dpp_tm_qmu_egress_shape_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 port_id, + ZXIC_UINT32 shape_cir, + ZXIC_UINT32 shape_cbs, + ZXIC_UINT32 shape_en) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_QCFG_CSW_SHAP_PARAMETER_T csw_shap_param = {0}; + DPP_ETM_QMU_QCFG_CSW_SHAP_TOKEN_DEPTH_T csw_shap_token_depth = {0}; + QMU_PORT_SHAPE_PARA qmu_port_shape_para[100] = {{0}}; + + ZXIC_UINT32 token_add_num = 0; + ZXIC_UINT32 token_gap = 0; + ZXIC_UINT32 shape_value_amplified = 0; + ZXIC_UINT32 compare_value = 0; + ZXIC_UINT32 shape_para_cnt = 0; + ZXIC_UINT32 shape_para_final_cnt = 0; + ZXIC_UINT32 shape_min_value = 0; + ZXIC_UINT32 shape_min_value_num = 0; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, port_id, 0, DPP_TM_PP_NUM - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, shape_cir, 0, 400000); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, shape_cbs, 0, 0x1EE00); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, shape_en, 0, 1); + + /* 获取token_add_num、token_gap */ + for (token_gap = 10; token_gap <= 0xfff; token_gap++ ) + { + for (token_add_num = 1; token_add_num <= 0xfff; token_add_num++) + { + shape_value_amplified = (1000 * 8 * token_add_num) / (token_gap + 1); + compare_value = (shape_value_amplified - (shape_cir * DPP_TM_QMU_PORT_SHAP_MAG)); + + /* 0~20的范围,避免获取token_add_num、token_gap失败 */ + if ( (compare_value > 0) && (compare_value < 20) && (shape_para_cnt<100)) + { + qmu_port_shape_para[shape_para_cnt].shape_value_amplified = shape_value_amplified; + qmu_port_shape_para[shape_para_cnt].token_add_num = token_add_num; + qmu_port_shape_para[shape_para_cnt].token_gap = token_gap; + shape_para_final_cnt = shape_para_cnt + 1; + shape_para_cnt++; + } + } + } + + /* 获取最小的整形值参数 */ + shape_min_value = qmu_port_shape_para[0].shape_value_amplified; + + for (shape_para_cnt = 0; shape_para_cnt < shape_para_final_cnt; shape_para_cnt++) + { + if (shape_min_value > qmu_port_shape_para[shape_para_cnt].shape_value_amplified) + { + shape_min_value = qmu_port_shape_para[shape_para_cnt].shape_value_amplified; + shape_min_value_num = shape_para_cnt ; + } + } + + /* 配置整形桶深 */ + csw_shap_token_depth.qcfg_csw_shap_token_depth = shape_cbs; + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_CSW_SHAP_TOKEN_DEPTHr, + 0, + port_id, + &csw_shap_token_depth); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + /* 配置整形速率 */ + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, shape_min_value_num, 0, 99); + csw_shap_param.qcfg_csw_shap_en = shape_en; + csw_shap_param.qcfg_csw_shap_parameter = (qmu_port_shape_para[shape_min_value_num].token_add_num << 12) | qmu_port_shape_para[shape_min_value_num].token_gap; + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_CSW_SHAP_PARAMETERr, + 0, + port_id, + &csw_shap_param); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + return DPP_OK; + +} + + +/***********************************************************/ +/** 获取CMD_SW分端口整形速率和使能 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param shape_vlue 整形值，单位Mbps +* @param shape_en 整形使能 +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author zmy @20151217 +************************************************************/ +DPP_STATUS dpp_tm_qmu_egress_shape_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 port_id, + ZXIC_UINT32 *shape_value, + ZXIC_UINT32 *shape_en) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_QCFG_CSW_SHAP_PARAMETER_T csw_shap_param = {0}; + ZXIC_UINT32 token_add_num = 0; + ZXIC_UINT32 token_gap = 0; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, port_id, 0, DPP_TM_PP_NUM - 1); + + rc = dpp_reg_read(dev_id, + ETM_QMU_QCFG_CSW_SHAP_PARAMETERr, + 0, + port_id, + &csw_shap_param); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + + token_add_num = (csw_shap_param.qcfg_csw_shap_parameter >> 12) & 0xfff; + token_gap = csw_shap_param.qcfg_csw_shap_parameter & 0xfff; + + *shape_value = (((600 * 8 * token_add_num) / (token_gap + 1 )) / DPP_TM_QMU_PORT_SHAP_MAG); + + *shape_en = csw_shap_param.qcfg_csw_shap_en; + + return DPP_OK; + +} + +#endif +/***********************************************************/ +/** 配置需要检测的特定队列号 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param qnum 需要检测统计的特定的队列号 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/06/18 +************************************************************/ +DPP_STATUS dpp_tm_qmu_spec_qnum_set(DPP_DEV_T *dev, ZXIC_UINT32 qnum) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_OBSERVE_QNUM_SET_T observe_qnum = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), qnum, 0, DPP_ETM_Q_NUM - 1); + + observe_qnum.observe_qnum_set = qnum; + rc = dpp_reg_write(dev, + ETM_QMU_OBSERVE_QNUM_SETr, + 0, + 0, + &observe_qnum); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + return DPP_OK; + +} + +/***********************************************************/ +/** 获得特定的队列号 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_qnum 需要检测统计的特定的队列号 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/06/23 +************************************************************/ +DPP_STATUS dpp_tm_qmu_spec_qnum_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_qnum) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_OBSERVE_QNUM_SET_T observe_qnum = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_qnum); + + rc = dpp_reg_read(dev, + ETM_QMU_OBSERVE_QNUM_SETr, + 0, + 0, + &observe_qnum); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + *p_qnum = observe_qnum.observe_qnum_set; + + return DPP_OK; + +} + +/***********************************************************/ +/** 配置需要检测的队列组 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param group_num 需要检测统计的特定的队列组。这里按取q的低3bit +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/06/18 +************************************************************/ +DPP_STATUS dpp_tm_qmu_spec_group_set(DPP_DEV_T *dev, ZXIC_UINT32 group_num) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_OBSERVE_BATCH_SET_T observe_batch = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), group_num, 0, 7); + + observe_batch.observe_batch_set = group_num; + rc = dpp_reg_write(dev, + ETM_QMU_OBSERVE_BATCH_SETr, + 0, + 0, + &observe_batch); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + return DPP_OK; +} + +/***********************************************************/ +/** 获得需要检测的队列组 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_group_num 需要检测统计的特定的队列组。这里按取q的低3bit +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/06/23 +************************************************************/ +DPP_STATUS dpp_tm_qmu_spec_group_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_group_num) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_OBSERVE_BATCH_SET_T observe_batch = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_group_num); + + rc = dpp_reg_read(dev, + ETM_QMU_OBSERVE_BATCH_SETr, + 0, + 0, + &observe_batch); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + *p_group_num = observe_batch.observe_batch_set; + + return DPP_OK; +} + +#if 0 +/***********************************************************/ +/** 配置出队暂存使用的进程总数 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param used_inall 出队暂存使用的进程总数=19-N，默认3表示使用16个进程 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/06/18 +************************************************************/ +DPP_STATUS dpp_tm_qmu_pid_use_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 used_inall) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_CFG_PID_USE_INALL_T pid_use_inall = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, used_inall, 0, 19); + + pid_use_inall.cfgmt_nod_rd_buf_0_aful_th = 19 - used_inall; + rc = dpp_reg_write(dev_id, + ETM_QMU_CFG_PID_USE_INALLr, + 0, + 0, + &pid_use_inall); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + return DPP_OK; +} + +/***********************************************************/ +/** 获得出队暂存使用的进程总数 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_used_inall 出队暂存使用的进程总数=19-N，默认3表示使用16个进程 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/06/23 +************************************************************/ +DPP_STATUS dpp_tm_qmu_pid_use_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_used_inall) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_CFG_PID_USE_INALL_T pid_use_inall = {0}; + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_used_inall); + + rc = dpp_reg_read(dev_id, + ETM_QMU_CFG_PID_USE_INALLr, + 0, + 0, + &pid_use_inall); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + *p_used_inall = 19 - pid_use_inall.cfgmt_nod_rd_buf_0_aful_th; + + return DPP_OK; +} + +/***********************************************************/ +/** 配置出队暂存自回加进程总数阈值 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param round_th 出队暂存自回加进程总数阈值=19-N，默认4表示使用15个进程就自回加 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/06/18 +************************************************************/ +DPP_STATUS dpp_tm_qmu_pid_round_th_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 round_th) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_CFG_PID_ROUND_TH_T pid_round_th = {0}; + ZXIC_COMM_CHECK_DEV_INDEX_SUB_OVERFLOW_NO_ASSERT(dev_id, 19 , round_th); + pid_round_th.cfgmt_nod_rd_buf_1_aful_th = 19 - round_th; + + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFG_PID_ROUND_THr, + 0, + 0, + &pid_round_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + return DPP_OK; +} + +/***********************************************************/ +/** 获得出队暂存自回加进程总数阈值 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_round_th 出队暂存自回加进程总数阈值=19-N，默认4表示使用15个进程就自回加 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/06/23 +************************************************************/ + +DPP_STATUS dpp_tm_qmu_pid_round_th_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_round_th) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_CFG_PID_ROUND_TH_T pid_round_th = {0}; + + + rc = dpp_reg_read(dev_id, + ETM_QMU_CFG_PID_ROUND_THr, + 0, + 0, + &pid_round_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + *p_round_th = 19 - pid_round_th.cfgmt_nod_rd_buf_1_aful_th; + + return DPP_OK; +} + + +/***********************************************************/ +/** 配置队列授权盈余 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param qnum 配置的队列号 +* @param value 授权盈余 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/06/18 +************************************************************/ +DPP_STATUS dpp_tm_qmu_crbal_value_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 qnum, + ZXIC_UINT32 value) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_QSCH_RW_CRBAL_T qsch_rw_crbal = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, value, 0, 0x1ffff); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, qnum, 0, DPP_ETM_Q_NUM - 1); + + qsch_rw_crbal.qsch_rw_crbal = value; + rc = dpp_reg_write(dev_id, + ETM_QMU_QSCH_RW_CRBALr, + 0, + qnum, + &qsch_rw_crbal); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + return DPP_OK; +} + +/***********************************************************/ +/** 获得队列授权盈余 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param qnum 配置的队列号 +* @param p_value 授权盈余 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/06/23 +************************************************************/ +DPP_STATUS dpp_tm_qmu_crbal_value_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 qnum, + ZXIC_UINT32 *p_value) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_QSCH_RW_CRBAL_T qsch_rw_crbal = {0}; + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_value); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, qnum, 0, DPP_ETM_Q_NUM - 1); + + rc = dpp_reg_read(dev_id, + ETM_QMU_QSCH_RW_CRBALr, + 0, + qnum, + &qsch_rw_crbal); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + *p_value = qsch_rw_crbal.qsch_rw_crbal & 0x1ffff; + + return DPP_OK; +} + +/***********************************************************/ +/** 配置分目的SA整形桶深上、下限参数 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param max_value 分目的SA整形桶深上限，必须配置为正值 +* @param min_value 分目的SA整形桶深下限，必须配置为负值 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/06/18 +************************************************************/ +DPP_STATUS dpp_tm_qmu_dest_sa_shape_para_set(ZXIC_UINT32 dev_id, + ZXIC_SINT32 max_value, + ZXIC_SINT32 min_value) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_CFGMT_SASHAP_TOKEN_MAX_T sashap_token_max = {0}; + DPP_ETM_QMU_CFGMT_SASHAP_TOKEN_MIN_T sashap_token_min = {0}; + + + if (max_value < 0) + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "[dev_id %d] max_value < 0, err!!!\n", dev_id); + ZXIC_COMM_ASSERT(0); + return DPP_ERR; + } + + if (min_value > 0) + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "[dev_id %d] min_value > 0, err!!!\n", dev_id); + ZXIC_COMM_ASSERT(0); + return DPP_ERR; + } + + sashap_token_max.cfgmt_sashap_token_max = max_value; + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_SASHAP_TOKEN_MAXr, + 0, + 0, + &sashap_token_max); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + sashap_token_min.cfgmt_sashap_token_min = min_value; + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_SASHAP_TOKEN_MINr, + 0, + 0, + &sashap_token_min); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + return DPP_OK; +} + +/***********************************************************/ +/** 获得分目的SA整形桶深上、下限参数 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_max_value 分目的SA整形桶深上限，必须配置为正值 +* @param p_min_value 分目的SA整形桶深下限，必须配置为负值 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/06/23 +************************************************************/ +DPP_STATUS dpp_tm_qmu_dest_sa_shape_para_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *p_max_value, + ZXIC_UINT32 *p_min_value) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_CFGMT_SASHAP_TOKEN_MAX_T sashap_token_max = {0}; + DPP_ETM_QMU_CFGMT_SASHAP_TOKEN_MIN_T sashap_token_min = {0}; + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_max_value); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_min_value); + + + rc = dpp_reg_read(dev_id, + ETM_QMU_CFGMT_SASHAP_TOKEN_MAXr, + 0, + 0, + &sashap_token_max); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + *p_max_value = sashap_token_max.cfgmt_sashap_token_max; + + rc = dpp_reg_read(dev_id, + ETM_QMU_CFGMT_SASHAP_TOKEN_MINr, + 0, + 0, + &sashap_token_min); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + *p_min_value = sashap_token_min.cfgmt_sashap_token_min; + + return DPP_OK; +} + +/***********************************************************/ +/** 配置CRS状态 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param qnum 队列号 +* @param state +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/06/19 +************************************************************/ +DPP_STATUS dpp_tm_qmu_crs_state_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 qnum, + ZXIC_UINT32 state) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_QSCH_RW_CRS_T qsch_rw_crs = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, state, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, qnum, 0, DPP_ETM_Q_NUM - 1); + + qsch_rw_crs.qsch_rw_crs = state; + rc = dpp_reg_write(dev_id, + ETM_QMU_QSCH_RW_CRSr, + 0, + qnum, + &qsch_rw_crs); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + return DPP_OK; +} + +/***********************************************************/ +/** 获得CRS状态 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param qnum 队列号 +* @param p_state +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/06/23 +************************************************************/ +DPP_STATUS dpp_tm_qmu_crs_state_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 qnum, + ZXIC_UINT32 *p_state) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_QSCH_RW_CRS_T qsch_rw_crs = {0}; + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_state); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, qnum, 0, DPP_ETM_Q_NUM - 1); + + + rc = dpp_reg_read(dev_id, + ETM_QMU_QSCH_RW_CRSr, + 0, + qnum, + &qsch_rw_crs); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + *p_state = qsch_rw_crs.qsch_rw_crs; + + return DPP_OK; +} + +#endif +/***********************************************************/ +/** 配置自动授权队列范围 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param first_que 自授权起始队列号 +* @param last_que 自授权终止队列号 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/06/19 +************************************************************/ +DPP_STATUS dpp_tm_qmu_auto_credit_que_set(DPP_DEV_T *dev, + ZXIC_UINT32 first_que, + ZXIC_UINT32 last_que) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_CFG_QSCH_AUTOCRFRSTQUE_T qsch_autocrfrstque = {0}; + DPP_ETM_QMU_CFG_QSCH_AUTOCRLASTQUE_T qsch_autocrlastque = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), first_que, 0, DPP_ETM_Q_NUM - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), last_que, 0, DPP_ETM_Q_NUM - 1); + + if (first_que > last_que) + { + ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "[dev_id %d] first_que > last_que, err!!!\n", DEV_ID(dev)); + + return DPP_ERR; + } + + qsch_autocrfrstque.cfg_qsch_autocrfrstque = first_que; + rc = dpp_reg_write(dev, + ETM_QMU_CFG_QSCH_AUTOCRFRSTQUEr, + 0, + 0, + &qsch_autocrfrstque); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + qsch_autocrlastque.cfg_qsch_autocrlastque = last_que; + rc = dpp_reg_write(dev, + ETM_QMU_CFG_QSCH_AUTOCRLASTQUEr, + 0, + 0, + &qsch_autocrlastque); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + return DPP_OK; +} + +/***********************************************************/ +/** 获得自动授权队列范围 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_first_que 自授权起始队列号 +* @param p_last_que 自授权终止队列号 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/06/23 +************************************************************/ +DPP_STATUS dpp_tm_qmu_auto_credit_que_get(DPP_DEV_T *dev, + ZXIC_UINT32 *p_first_que, + ZXIC_UINT32 *p_last_que) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_CFG_QSCH_AUTOCRFRSTQUE_T qsch_autocrfrstque = {0}; + DPP_ETM_QMU_CFG_QSCH_AUTOCRLASTQUE_T qsch_autocrlastque = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_first_que); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_last_que); + + rc = dpp_reg_read(dev, + ETM_QMU_CFG_QSCH_AUTOCRFRSTQUEr, + 0, + 0, + &qsch_autocrfrstque); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + *p_first_que = qsch_autocrfrstque.cfg_qsch_autocrfrstque; + + rc = dpp_reg_read(dev, + ETM_QMU_CFG_QSCH_AUTOCRLASTQUEr, + 0, + 0, + &qsch_autocrlastque); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + *p_last_que = qsch_autocrlastque.cfg_qsch_autocrlastque; + + return DPP_OK; +} + +/***********************************************************/ +/** 配置自动授权开启使能及扫描速率 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param auto_crdt_en 自动授权开启使能，默认关闭。0：关闭；1：开启 +* @param auto_crdt_rate 自授权速率配置 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/06/19 +************************************************************/ +DPP_STATUS dpp_tm_qmu_auto_credit_rate_set(DPP_DEV_T *dev, + ZXIC_UINT32 auto_crdt_en, + ZXIC_UINT32 auto_crdt_rate) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_CFG_QSCH_AUTO_CREDIT_CONTROL_EN_T credit_control_en = {0}; + DPP_ETM_QMU_CFG_QSCH_AUTOCREDITRATE_T autocredit_rate = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), auto_crdt_en, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), auto_crdt_rate, 0, 0xfffff); + + + credit_control_en.cfg_qsch_auto_credit_control_en = auto_crdt_en; + rc = dpp_reg_write(dev, + ETM_QMU_CFG_QSCH_AUTO_CREDIT_CONTROL_ENr, + 0, + 0, + &credit_control_en); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + autocredit_rate.cfg_qsch_autocreditrate = auto_crdt_rate; + rc = dpp_reg_write(dev, + ETM_QMU_CFG_QSCH_AUTOCREDITRATEr, + 0, + 0, + &autocredit_rate); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + return DPP_OK; +} + +/***********************************************************/ +/** 获得自动授权开启使能及扫描速率 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_auto_crdt_en 自动授权开启使能，默认关闭。0：关闭；1：开启 +* @param p_auto_crdt_rate 自授权速率配置 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/06/23 +************************************************************/ +DPP_STATUS dpp_tm_qmu_auto_credit_rate_get(DPP_DEV_T *dev, + ZXIC_UINT32 *p_auto_crdt_en, + ZXIC_UINT32 *p_auto_crdt_rate) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_CFG_QSCH_AUTO_CREDIT_CONTROL_EN_T credit_control_en = {0}; + DPP_ETM_QMU_CFG_QSCH_AUTOCREDITRATE_T autocredit_rate = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_auto_crdt_en); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_auto_crdt_rate); + + rc = dpp_reg_read(dev, + ETM_QMU_CFG_QSCH_AUTO_CREDIT_CONTROL_ENr, + 0, + 0, + &credit_control_en); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + *p_auto_crdt_en = credit_control_en.cfg_qsch_auto_credit_control_en; + + rc = dpp_reg_read(dev, + ETM_QMU_CFG_QSCH_AUTOCREDITRATEr, + 0, + 0, + &autocredit_rate); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + *p_auto_crdt_rate = autocredit_rate.cfg_qsch_autocreditrate; + + return DPP_OK; +} + +#if 0 +/***********************************************************/ +/** 配置授权丢弃使能 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param all_drop_en 所有授权丢弃使能：1：允许丢弃所有授权；0：仅允许丢弃拥塞授权 +* @param drop_en 授权丢弃使能：1：允许丢弃授权；0：禁止丢弃授权 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/06/23 +************************************************************/ +DPP_STATUS dpp_tm_qmu_crbal_drop_en_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 all_drop_en, + ZXIC_UINT32 drop_en) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_CFGMT_QSCH_CRBAL_DROP_EN_T crbal_drop_en = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, all_drop_en, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, drop_en, 0, 1); + + crbal_drop_en.cfgmt_qsch_all_crbal_drop_en = all_drop_en; + crbal_drop_en.cfgmt_qsch_crbal_drop_en = drop_en; + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_QSCH_CRBAL_DROP_ENr, + 0, + 0, + &crbal_drop_en); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + return DPP_OK; +} + +/***********************************************************/ +/** 获得授权丢弃使能 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_all_drop_en 所有授权丢弃使能：1：允许丢弃所有授权；0：仅允许丢弃拥塞授权 +* @param p_drop_en 授权丢弃使能：1：允许丢弃授权；0：禁止丢弃授权 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/06/23 +************************************************************/ +DPP_STATUS dpp_tm_qmu_crbal_drop_en_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 *p_all_drop_en, + ZXIC_UINT32 *p_drop_en) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_CFGMT_QSCH_CRBAL_DROP_EN_T crbal_drop_en = {0}; + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_all_drop_en); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_drop_en); + + rc = dpp_reg_read(dev_id, + ETM_QMU_CFGMT_QSCH_CRBAL_DROP_ENr, + 0, + 0, + &crbal_drop_en); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + *p_all_drop_en = crbal_drop_en.cfgmt_qsch_all_crbal_drop_en; + *p_drop_en = crbal_drop_en.cfgmt_qsch_crbal_drop_en; + + return DPP_OK; +} + + +/***********************************************************/ +/** 获取特定队列发送的crs normal的个数 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param 注 须先设置统计的特定队列 +* @param +* @return +* @remark 无 +* @see +* @author yjd @date 2015/07/09 +************************************************************/ +DPP_STATUS dpp_tm_qmu_spec_q_crs_normal_cnt(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_que_crs_normal_cnt) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_SPEC_Q_CRS_NORMAL_CNT_T crs_normal_cnt; + + rc = dpp_reg_read(dev_id, + ETM_QMU_SPEC_Q_CRS_NORMAL_CNTr, + 0, + 0, + &crs_normal_cnt); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + *p_que_crs_normal_cnt = crs_normal_cnt.spec_q_crs_normal_cnt; + return DPP_OK; +} + +/***********************************************************/ +/** 获取特定队列发送的crs off的个数 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param 注 须先设置统计的特定队列 +* @param +* @return +* @remark 无 +* @see +* @author yjd @date 2015/07/09 +************************************************************/ +DPP_STATUS dpp_tm_qmu_spec_q_crs_off_cnt(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_que_crs_off_cnt) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_SPEC_Q_CRS_OFF_CNT_T crs_off_cnt; + + rc = dpp_reg_read(dev_id, + ETM_QMU_SPEC_Q_CRS_OFF_CNTr, + 0, + 0, + &crs_off_cnt); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + *p_que_crs_off_cnt = crs_off_cnt.spec_q_crs_off_cnt; + return DPP_OK; +} + +#endif +/***********************************************************/ +/**设置自然拥塞反压门限值 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param +* @return +* @remark 无 +* @see +* @author yjd @date 2015/07/16 +************************************************************/ +DPP_STATUS dpp_tm_qmu_qcfg_csch_congest_th_set(DPP_DEV_T *dev, ZXIC_UINT32 port_id, ZXIC_UINT32 qmu_congest_th) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_QCFG_CSCH_CONGEST_TH_T qcfg_csch_congest_th = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), port_id, 0, DPP_TM_PP_NUM - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), qmu_congest_th, 0, 0x1ffff); + + qcfg_csch_congest_th.qcfg_csch_congest_th = qmu_congest_th; + rc = dpp_reg_write(dev, + ETM_QMU_QCFG_CSCH_CONGEST_THr, + 0, + port_id, + &qcfg_csch_congest_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + return DPP_OK; +} + +/***********************************************************/ +/**获取自然拥塞反压门限值 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param +* @return +* @remark 无 +* @see +* @author yjd @date 2015/07/16 +************************************************************/ +DPP_STATUS dpp_tm_qmu_qcfg_csch_congest_th_get(DPP_DEV_T *dev, ZXIC_UINT32 port_id, ZXIC_UINT32 *p_qmu_congest_th) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_QCFG_CSCH_CONGEST_TH_T qcfg_csch_congest_th = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_qmu_congest_th); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), port_id, 0, DPP_TM_PP_NUM - 1); + + rc = dpp_reg_read(dev, + ETM_QMU_QCFG_CSCH_CONGEST_THr, + 0, + port_id, + &qcfg_csch_congest_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + *p_qmu_congest_th = qcfg_csch_congest_th.qcfg_csch_congest_th; + + return DPP_OK; +} + +/***********************************************************/ +/**设置CMD_SCH分优先级反压门限值 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param +* @return +* @remark 无 +* @see +* @author yjd @date 2015/07/16 +************************************************************/ +DPP_STATUS dpp_tm_qmu_qcfg_csch_sp_fc_th_set(DPP_DEV_T *dev, ZXIC_UINT32 port_id, ZXIC_UINT32 q_pri, ZXIC_UINT32 qmu_sp_fc_th) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 index = 0; + DPP_ETM_QMU_QCFG_CSCH_SP_FC_TH_T qcfg_csch_sp_fc_th = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), port_id, 0, DPP_TM_PP_NUM - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), q_pri, 0, 4); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), qmu_sp_fc_th, 0, 0x1ffff); + + index = port_id * 5 + q_pri; + qcfg_csch_sp_fc_th.qcfg_csch_sp_fc_th = qmu_sp_fc_th; + + rc = dpp_reg_write(dev, + ETM_QMU_QCFG_CSCH_SP_FC_THr, + 0, + index, + &qcfg_csch_sp_fc_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + return DPP_OK; +} + +/***********************************************************/ +/**获取自然拥塞反压门限值 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param +* @return +* @remark 无 +* @see +* @author yjd @date 2015/07/16 +************************************************************/ +DPP_STATUS dpp_tm_qmu_qcfg_csch_sp_fc_th_get(DPP_DEV_T *dev, ZXIC_UINT32 port_id, ZXIC_UINT32 q_pri, ZXIC_UINT32 *p_qmu_sp_fc_th) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 index = 0; + DPP_ETM_QMU_QCFG_CSCH_SP_FC_TH_T qcfg_csch_sp_fc_th = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), port_id, 0, DPP_TM_PP_NUM - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), q_pri, 0, 4); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_qmu_sp_fc_th); + + index = port_id * 5 + q_pri; + + rc = dpp_reg_read(dev, + ETM_QMU_QCFG_CSCH_SP_FC_THr, + 0, + index, + &qcfg_csch_sp_fc_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + *p_qmu_sp_fc_th = qcfg_csch_sp_fc_th.qcfg_csch_sp_fc_th; + + return DPP_OK; +} + +#if 0 +/***********************************************************/ +/**每隔10s获取crs状态的个数 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param +* @return +* @remark 无 +* @see +* @author zmy @date 2015/08/07 +************************************************************/ + +DPP_STATUS dpp_tm_crs_statics(ZXIC_UINT32 dev_id, ZXIC_UINT32 que_id) +{ + DPP_STATUS rc = DPP_OK; + DPP_TM_CNT_MODE_T que_get_mode = {0}; + ZXIC_UINT32 i = 0; + ZXIC_UINT32 q_crs_normal_cnt = 0; + ZXIC_UINT32 q_crs_off_cnt = 0; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, que_id, 0, DPP_ETM_Q_NUM - 1); + + rc = dpp_tm_cfgmt_cnt_mode_get(dev_id, &que_get_mode); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_cnt_mode_get"); + que_get_mode.count_rd_mode = 1; + + rc = dpp_tm_cfgmt_cnt_mode_set(dev_id, &que_get_mode); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_cnt_mode_set"); + + rc = dpp_tm_qmu_spec_qnum_set(dev_id, que_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_spec_qnum_set"); + rc = dpp_tm_qmu_spec_q_crs_normal_cnt(dev_id, &q_crs_normal_cnt); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_spec_q_crs_normal_cnt"); + rc = dpp_tm_qmu_spec_q_crs_off_cnt(dev_id, &q_crs_off_cnt); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_spec_q_crs_off_cnt"); + + for (i = 0; i <= 2; i++) + { + zxic_comm_sleep(10000); + rc = dpp_tm_qmu_spec_q_crs_normal_cnt(dev_id, &q_crs_normal_cnt); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_spec_q_crs_normal_cnt"); + ZXIC_COMM_PRINT("q_crs_normal_cnt is %d\n ", q_crs_normal_cnt); + + rc = dpp_tm_qmu_spec_q_crs_off_cnt(dev_id, &q_crs_off_cnt); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_spec_q_crs_off_cnt"); + ZXIC_COMM_PRINT("q_crs_off_cnt is %d\n ", q_crs_off_cnt); + } + + rc = dpp_tm_cfgmt_cnt_mode_get(dev_id, &que_get_mode); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_cnt_mode_get"); + que_get_mode.count_rd_mode = 0; + + rc = dpp_tm_cfgmt_cnt_mode_set(dev_id, &que_get_mode); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_cnt_mode_set"); + + return DPP_OK; +} + + + +/***********************************************************/ +/** 统计QMU发送和CRDT模块指定授权流接收的CRS计数(10s内) +* @param dev_id 设备编号 +* @param que_id QMU队列号 +* @param ackflow_id 授权流号 +* @param valid_flag 0:队列发送和授权流接收都统计; 1:只关注队列发送，2:只关注授权流接收。 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author wush @date 2017/05/12 +************************************************************/ +DPP_STATUS dpp_tm_crs_cnt_prt(ZXIC_UINT32 dev_id, ZXIC_UINT32 que_id, ZXIC_UINT32 ackflow_id, ZXIC_UINT32 valid_flag) +{ + DPP_STATUS rc = DPP_OK; + DPP_TM_CNT_MODE_T que_get_mode = {0}; + ZXIC_UINT32 i = 0; + ZXIC_UINT32 q_crs_normal_cnt = 0; + ZXIC_UINT32 q_crs_off_cnt = 0; + ZXIC_UINT32 crdt_crs_que_id_index = 0; + ZXIC_UINT32 all_crs_normal_cnt_index = 0; + ZXIC_UINT32 all_crs_off_cnt_index = 0; + ZXIC_UINT32 que_crs_normal_cnt_index = 0; + ZXIC_UINT32 que_crd_off_cnt_index = 0; + ZXIC_UINT32 crs_end_state_index = 0; + + + + /* 结构体变量定义 */ + DPP_ETM_CRDT_CRS_QUE_ID_T crdt_crs_que_id = {0}; + DPP_ETM_CRDT_FIFO_OUT_ALL_CRS_NORMAL_CNT_T all_crs_normal_cnt = {0}; + DPP_ETM_CRDT_FIFO_OUT_ALL_CRS_OFF_CNT_T all_crs_off_cnt = {0}; + DPP_ETM_CRDT_FIFO_OUT_QUE_CRS_NORMAL_CNT_T que_crs_normal_cnt = {0}; + DPP_ETM_CRDT_FIFO_OUT_QUE_CRS_OFF_CNT_T que_crd_off_cnt = {0}; + DPP_ETM_CRDT_QMU_CRS_END_STATE_T crs_end_state = {0}; + + crdt_crs_que_id_index = ETM_CRDT_CRS_QUE_IDr; + all_crs_normal_cnt_index = ETM_CRDT_FIFO_OUT_ALL_CRS_NORMAL_CNTr; + all_crs_off_cnt_index = ETM_CRDT_FIFO_OUT_ALL_CRS_OFF_CNTr; + que_crs_normal_cnt_index = ETM_CRDT_FIFO_OUT_QUE_CRS_NORMAL_CNTr; + que_crd_off_cnt_index = ETM_CRDT_FIFO_OUT_QUE_CRS_OFF_CNTr; + crs_end_state_index = ETM_CRDT_QMU_CRS_END_STATEr; + + if (0 == valid_flag) + { + /* 设置统计CRDT CRS 接收个数的队列号 */ + crdt_crs_que_id.crs_que_id = ackflow_id; + rc = dpp_reg_write(dev_id, + crdt_crs_que_id_index, + 0, + 0, + &crdt_crs_que_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + + /* 1.先配置读清 */ + rc = dpp_tm_cfgmt_cnt_mode_get(dev_id, &que_get_mode); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_cnt_mode_get"); + que_get_mode.count_rd_mode = 1; + + rc = dpp_tm_cfgmt_cnt_mode_set(dev_id, &que_get_mode); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_cnt_mode_set"); + + /* 队列发送crs读清 */ + + rc = dpp_tm_qmu_spec_qnum_set(dev_id, que_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_spec_qnum_set"); + rc = dpp_tm_qmu_spec_q_crs_normal_cnt(dev_id, &q_crs_normal_cnt); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_spec_q_crs_normal_cnt"); + rc = dpp_tm_qmu_spec_q_crs_off_cnt(dev_id, &q_crs_off_cnt); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_spec_q_crs_off_cnt"); + + /* crdt接收crs读清 */ + rc = dpp_tm_crdt_clr_diag(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_crdt_clr_diag"); + + + /* 2.连读两次统计CRS发送和接收 */ + for (i = 0; i < 2; i++) + { + zxic_comm_sleep(10000); + + ZXIC_COMM_PRINT("------(%d th)qmu_send & crdt_recv crs_cnt in 10s------\n ", i + 1); + /* 统计CRS发送 */ + rc = dpp_tm_qmu_spec_q_crs_normal_cnt(dev_id, &q_crs_normal_cnt); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_spec_q_crs_normal_cnt"); + ZXIC_COMM_PRINT("que_id(0x%08x)qmu_send_crs_normal_cnt: 0x%08x\n ", que_id, q_crs_normal_cnt); + + rc = dpp_tm_qmu_spec_q_crs_off_cnt(dev_id, &q_crs_off_cnt); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_spec_q_crs_off_cnt"); + ZXIC_COMM_PRINT("que_id(0x%08x)qmu_send_crs_off_cnt: 0x%08x\n ", que_id, q_crs_off_cnt); + + /* 统计CRS接收 */ + + /* 统计CRDT接收到的CRS off总数 */ + rc = dpp_reg_read(dev_id, + all_crs_off_cnt_index, + 0, + 0, + &all_crs_off_cnt); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + /* 统计CRDT指定队列接收到的CRS off总数 */ + rc = dpp_reg_read(dev_id, + que_crd_off_cnt_index, + 0, + 0, + &que_crd_off_cnt); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + /* 统计CRDT接收到的CRS normal总数 */ + rc = dpp_reg_read(dev_id, + all_crs_normal_cnt_index, + 0, + 0, + &all_crs_normal_cnt); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + + + /* 统计CRDT指定队列接收到的CRS normal总数 */ + rc = dpp_reg_read(dev_id, + que_crs_normal_cnt_index, + 0, + 0, + &que_crs_normal_cnt); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + + + /* 统计CRDT指定队列接收到的crs最后的状态 */ + rc = dpp_reg_read(dev_id, + crs_end_state_index, + 0, + 0, + &crs_end_state); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + /* crdt接收crs读清 */ + rc = dpp_tm_crdt_clr_diag(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_crdt_clr_diag"); + + /* 打印统计信息 */ + ZXIC_COMM_PRINT("crdt_recv_all_crs_normal_cnt: 0x%08x\n ", all_crs_normal_cnt.fifo_out_all_crs_normal_cnt); + ZXIC_COMM_PRINT("crdt_recv_all_crs_off_cnt: 0x%08x\n ", all_crs_off_cnt.fifo_out_all_crs_off_cnt); + ZXIC_COMM_PRINT("ackflow_id(0x%08x)recv_crs_normal_cnt: 0x%08x\n ", ackflow_id, que_crs_normal_cnt.fifo_out_que_crs_normal_cnt); + ZXIC_COMM_PRINT("ackflow_id(0x%08x)recv_crs_off_cnt: 0x%08x\n ", ackflow_id, que_crd_off_cnt.fifo_out_que_crs_off_cnt); + ZXIC_COMM_PRINT("ackflow_id(0x%08x)recv_crs_end_state: %d\n ", ackflow_id, crs_end_state.qmu_crs_end_state); + + } + + /* 3.配置成crs非读清 */ + rc = dpp_tm_cfgmt_cnt_mode_get(dev_id, &que_get_mode); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_cnt_mode_get"); + que_get_mode.count_rd_mode = 0; + + rc = dpp_tm_cfgmt_cnt_mode_set(dev_id, &que_get_mode); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_cnt_mode_set"); + + } + else if (1 == valid_flag) + { + /* 1.先配置读清 */ + rc = dpp_tm_cfgmt_cnt_mode_get(dev_id, &que_get_mode); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_cnt_mode_get"); + que_get_mode.count_rd_mode = 1; + + rc = dpp_tm_cfgmt_cnt_mode_set(dev_id, &que_get_mode); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_cnt_mode_set"); + + /* 队列发送crs读清 */ + + rc = dpp_tm_qmu_spec_qnum_set(dev_id, que_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_spec_qnum_set"); + rc = dpp_tm_qmu_spec_q_crs_normal_cnt(dev_id, &q_crs_normal_cnt); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_spec_q_crs_normal_cnt"); + rc = dpp_tm_qmu_spec_q_crs_off_cnt(dev_id, &q_crs_off_cnt); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_spec_q_crs_off_cnt"); + + /* 2.连读两次统计CRS发送和接收 */ + for (i = 0; i < 2; i++) + { + zxic_comm_sleep(10000); + + ZXIC_COMM_PRINT("------(%d th)qmu_send crs_cnt in 10s------\n ", i + 1); + /* 统计CRS发送 */ + rc = dpp_tm_qmu_spec_q_crs_normal_cnt(dev_id, &q_crs_normal_cnt); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_spec_q_crs_normal_cnt"); + ZXIC_COMM_PRINT("que_id(0x%08x)qmu_send_crs_normal_cnt: 0x%08x\n ", que_id, q_crs_normal_cnt); + + rc = dpp_tm_qmu_spec_q_crs_off_cnt(dev_id, &q_crs_off_cnt); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_spec_q_crs_off_cnt"); + ZXIC_COMM_PRINT("que_id(0x%08x)qmu_send_crs_off_cnt: 0x%08x\n ", que_id, q_crs_off_cnt); + } + + /* 3.配置成crs非读清 */ + rc = dpp_tm_cfgmt_cnt_mode_get(dev_id, &que_get_mode); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_cnt_mode_get"); + que_get_mode.count_rd_mode = 0; + + rc = dpp_tm_cfgmt_cnt_mode_set(dev_id, &que_get_mode); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_cnt_mode_set"); + } + + else if (2 == valid_flag) + { + + /* 设置统计CRDT CRS 接收个数的队列号 */ + crdt_crs_que_id.crs_que_id = ackflow_id; + rc = dpp_reg_write(dev_id, + crdt_crs_que_id_index, + 0, + 0, + &crdt_crs_que_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + + /* 2.连读两次统计CRS发送和接收 */ + for (i = 0; i < 2; i++) + { + + /* crdt接收crs读清 */ + rc = dpp_tm_crdt_clr_diag(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_crdt_clr_diag"); + + zxic_comm_sleep(10000); + + ZXIC_COMM_PRINT("------(%d th)crdt_recv crs_cnt in 10s------\n ", i + 1); + + /* 统计CRS接收 */ + /* 统计CRDT指定队列接收到的CRS off总数 */ + rc = dpp_reg_read(dev_id, + que_crd_off_cnt_index, + 0, + 0, + &que_crd_off_cnt); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + /* 统计CRDT接收到的CRS off 总数 */ + rc = dpp_reg_read(dev_id, + all_crs_off_cnt_index, + 0, + 0, + &all_crs_off_cnt); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + /* 统计CRDT接收到的CRS normal总数 */ + rc = dpp_reg_read(dev_id, + all_crs_normal_cnt_index, + 0, + 0, + &all_crs_normal_cnt); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + + + /* 统计CRDT指定队列接收到的CRS normal总数 */ + rc = dpp_reg_read(dev_id, + que_crs_normal_cnt_index, + 0, + 0, + &que_crs_normal_cnt); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + + /* 统计CRDT指定队列接收到的crs最后的状态 */ + rc = dpp_reg_read(dev_id, + crs_end_state_index, + 0, + 0, + &crs_end_state); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + /* crdt接收crs读清 */ + rc = dpp_tm_crdt_clr_diag(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_crdt_clr_diag"); + /* 打印统计信息 */ + ZXIC_COMM_PRINT("crdt_recv_all_crs_normal_cnt: 0x%08x\n ", all_crs_normal_cnt.fifo_out_all_crs_normal_cnt); + ZXIC_COMM_PRINT("crdt_recv_all_crs_off_cnt: 0x%08x\n ", all_crs_off_cnt.fifo_out_all_crs_off_cnt); + ZXIC_COMM_PRINT("ackflow_id(0x%08x)recv_crs_normal_cnt: 0x%08x\n ", ackflow_id, que_crs_normal_cnt.fifo_out_que_crs_normal_cnt); + ZXIC_COMM_PRINT("ackflow_id(0x%08x)recv_crs_off_cnt: 0x%08x\n ", ackflow_id, que_crd_off_cnt.fifo_out_que_crs_off_cnt); + ZXIC_COMM_PRINT("ackflow_id(0x%08x)recv_crs_end_state: %d\n ", ackflow_id, crs_end_state.qmu_crs_end_state); + } + + } + else + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "dpp_tm_crs_cnt_prt:valid_flag_error!!: 0: print crs of que and ackflow;1:print que crs only; 2:print ackflow crs only!\n"); + + } + + + return DPP_OK; + +} + +/***********************************************************/ +/** 带停流的统计QMU发送和CRDT模块指定授权流接收的CRS计数 +* @param dev_id 设备编号 +* @param que_id QMU队列号 +* @param ackflow_id 授权流号 +* @param valid_flag 0:默认队列发送和授权流接收都统计,此时队列授权都在本板; +* 1:只关注队列发送，2:只关注授权流接收，需要与源端队列停流配合使用， + 先停流，运行该函数；或者直接不停流得到的是某段时间的计数。 +* @param sleep_time 统计多长时间内的crs计数 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author wush @date 2017/05/12 +************************************************************/ +DPP_STATUS dpp_tm_crs_cnt_prt_1(ZXIC_UINT32 dev_id, + ZXIC_UINT32 que_id, + ZXIC_UINT32 ackflow_id, + ZXIC_UINT32 valid_flag, + ZXIC_UINT32 sleep_time) +{ + DPP_STATUS rc = DPP_OK; + DPP_TM_CNT_MODE_T que_get_mode = {0}; + ZXIC_UINT32 flow_td_th = 0; + ZXIC_UINT32 q_crs_normal_cnt = 0; + ZXIC_UINT32 q_crs_off_cnt = 0; + ZXIC_UINT32 crdt_crs_que_id_index = 0; + ZXIC_UINT32 all_crs_normal_cnt_index = 0; + ZXIC_UINT32 all_crs_off_cnt_index = 0; + ZXIC_UINT32 que_crs_normal_cnt_index = 0; + ZXIC_UINT32 que_crd_off_cnt_index = 0; + ZXIC_UINT32 crs_end_state_index = 0; + + /* 结构体变量定义 */ + DPP_ETM_CRDT_CRS_QUE_ID_T crdt_crs_que_id = {0}; + DPP_ETM_CRDT_FIFO_OUT_ALL_CRS_NORMAL_CNT_T all_crs_normal_cnt = {0}; + DPP_ETM_CRDT_FIFO_OUT_ALL_CRS_OFF_CNT_T all_crs_off_cnt = {0}; + DPP_ETM_CRDT_FIFO_OUT_QUE_CRS_NORMAL_CNT_T que_crs_normal_cnt = {0}; + DPP_ETM_CRDT_FIFO_OUT_QUE_CRS_OFF_CNT_T que_crd_off_cnt = {0}; + DPP_ETM_CRDT_QMU_CRS_END_STATE_T crs_end_state = {0}; + + crdt_crs_que_id_index = ETM_CRDT_CRS_QUE_IDr; + all_crs_normal_cnt_index = ETM_CRDT_FIFO_OUT_ALL_CRS_NORMAL_CNTr; + all_crs_off_cnt_index = ETM_CRDT_FIFO_OUT_ALL_CRS_OFF_CNTr; + que_crs_normal_cnt_index = ETM_CRDT_FIFO_OUT_QUE_CRS_NORMAL_CNTr; + que_crd_off_cnt_index = ETM_CRDT_FIFO_OUT_QUE_CRS_OFF_CNTr; + crs_end_state_index = ETM_CRDT_QMU_CRS_END_STATEr; + + rc = dpp_tm_cgavd_td_th_get(dev_id, QUEUE_LEVEL, que_id, &flow_td_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_td_th_get"); + + if (0 == valid_flag) + { + + + /* 设置统计CRDT CRS 接收个数的队列号 */ + crdt_crs_que_id.crs_que_id = ackflow_id; + rc = dpp_reg_write(dev_id, + crdt_crs_que_id_index, + 0, + 0, + &crdt_crs_que_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + rc = dpp_tm_cgavd_td_th_set(dev_id, QUEUE_LEVEL, que_id, 0); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_td_th_set"); + + /* 1.停流配置读清 */ + rc = dpp_tm_cfgmt_cnt_mode_get(dev_id, &que_get_mode); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_cnt_mode_get"); + que_get_mode.count_rd_mode = 1; + + rc = dpp_tm_cfgmt_cnt_mode_set(dev_id, &que_get_mode); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_cnt_mode_set"); + + /* 队列发送crs读清 */ + + rc = dpp_tm_qmu_spec_qnum_set(dev_id, que_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_spec_qnum_set"); + rc = dpp_tm_qmu_spec_q_crs_normal_cnt(dev_id, &q_crs_normal_cnt); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_spec_q_crs_normal_cnt"); + rc = dpp_tm_qmu_spec_q_crs_off_cnt(dev_id, &q_crs_off_cnt); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_spec_q_crs_off_cnt"); + + /* crdt接收crs读清 */ + rc = dpp_tm_crdt_clr_diag(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_crdt_clr_diag"); + + + /* 2.统计CRS发送和接收 */ + rc = dpp_tm_cgavd_td_th_set(dev_id, QUEUE_LEVEL, que_id, flow_td_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_td_th_set"); + + + zxic_comm_sleep(sleep_time); + + rc = dpp_tm_qmu_spec_q_crs_off_cnt(dev_id, &q_crs_off_cnt); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_spec_q_crs_off_cnt"); + + /* 统计CRDT接收到的CRS off总数 */ + rc = dpp_reg_read(dev_id, + all_crs_off_cnt_index, + 0, + 0, + &all_crs_off_cnt); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + /* 统计CRDT指定队列接收到的CRS off总数 */ + rc = dpp_reg_read(dev_id, + que_crd_off_cnt_index, + 0, + 0, + &que_crd_off_cnt); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + rc = dpp_tm_cgavd_td_th_set(dev_id, QUEUE_LEVEL, que_id, 0); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_td_th_set"); + zxic_comm_sleep(1000); + + /* 统计CRS发送 */ + rc = dpp_tm_qmu_spec_q_crs_normal_cnt(dev_id, &q_crs_normal_cnt); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_spec_q_crs_normal_cnt"); + ZXIC_COMM_PRINT("que_id(0x%08x)qmu_send_crs_normal_cnt: 0x%08x\n ", que_id, q_crs_normal_cnt); + ZXIC_COMM_PRINT("que_id(0x%08x)qmu_send_crs_off_cnt: 0x%08x\n ", que_id, q_crs_off_cnt); + /* 统计CRS接收 */ + /* 统计CRDT接收到的CRS normal总数 */ + rc = dpp_reg_read(dev_id, + all_crs_normal_cnt_index, + 0, + 0, + &all_crs_normal_cnt); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + /* 统计CRDT指定队列接收到的CRS normal总数 */ + rc = dpp_reg_read(dev_id, + que_crs_normal_cnt_index, + 0, + 0, + &que_crs_normal_cnt); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + + + /* 统计CRDT指定队列接收到的crs最后的状态 */ + rc = dpp_reg_read(dev_id, + crs_end_state_index, + 0, + 0, + &crs_end_state); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + /* crdt接收crs读清 */ + rc = dpp_tm_crdt_clr_diag(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_crdt_clr_diag"); + /* 打印统计信息 */ + ZXIC_COMM_PRINT("crdt_recv_all_crs_normal_cnt: 0x%08x\n", all_crs_normal_cnt.fifo_out_all_crs_normal_cnt); + ZXIC_COMM_PRINT("crdt_recv_all_crs_off_cnt: 0x%08x\n", all_crs_off_cnt.fifo_out_all_crs_off_cnt); + ZXIC_COMM_PRINT("ackflow_id(0x%08x)recv_crs_normal_cnt: 0x%08x\n", ackflow_id, que_crs_normal_cnt.fifo_out_que_crs_normal_cnt); + ZXIC_COMM_PRINT("ackflow_id(0x%08x)recv_crs_off_cnt: 0x%08x\n", ackflow_id, que_crd_off_cnt.fifo_out_que_crs_off_cnt); + ZXIC_COMM_PRINT("ackflow_id(0x%08x)recv_crs_end_state: %d\n", ackflow_id, crs_end_state.qmu_crs_end_state); + + + + /* 4.配置成crs非读清 */ + rc = dpp_tm_cfgmt_cnt_mode_get(dev_id, &que_get_mode); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_cnt_mode_get"); + que_get_mode.count_rd_mode = 0; + + rc = dpp_tm_cfgmt_cnt_mode_set(dev_id, &que_get_mode); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_cnt_mode_set"); + + /* 5.恢复通流 */ + rc = dpp_tm_cgavd_td_th_set(dev_id, 0, que_id, flow_td_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_td_th_set"); + + } + else if (1 == valid_flag) /* 仅统计停流清零再发流该段时间发送的CRS */ + { + rc = dpp_tm_cgavd_td_th_set(dev_id, QUEUE_LEVEL, que_id, 0); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_td_th_set"); + + /* 1.停流配置读清 */ + rc = dpp_tm_cfgmt_cnt_mode_get(dev_id, &que_get_mode); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_cnt_mode_get"); + que_get_mode.count_rd_mode = 1; + + rc = dpp_tm_cfgmt_cnt_mode_set(dev_id, &que_get_mode); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_cnt_mode_set"); + + /* 队列发送crs读清 */ + + rc = dpp_tm_qmu_spec_qnum_set(dev_id, que_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_spec_qnum_set"); + rc = dpp_tm_qmu_spec_q_crs_normal_cnt(dev_id, &q_crs_normal_cnt); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_spec_q_crs_normal_cnt"); + rc = dpp_tm_qmu_spec_q_crs_off_cnt(dev_id, &q_crs_off_cnt); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_spec_q_crs_off_cnt"); + + /* 2.开流设定时间后停流统计CRS发送 */ + rc = dpp_tm_cgavd_td_th_set(dev_id, QUEUE_LEVEL, que_id, flow_td_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_td_th_set"); + + + zxic_comm_sleep(sleep_time); + + rc = dpp_tm_qmu_spec_q_crs_off_cnt(dev_id, &q_crs_off_cnt); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_spec_q_crs_off_cnt"); + + rc = dpp_tm_cgavd_td_th_set(dev_id, QUEUE_LEVEL, que_id, 0); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_td_th_set"); + zxic_comm_sleep(1000); + + /* 统计CRS发送 */ + rc = dpp_tm_qmu_spec_q_crs_normal_cnt(dev_id, &q_crs_normal_cnt); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_spec_q_crs_normal_cnt"); + ZXIC_COMM_PRINT("que_id(0x%08x)qmu_send_crs_normal_cnt: 0x%08x\n ", que_id, q_crs_normal_cnt); + ZXIC_COMM_PRINT("que_id(0x%08x)qmu_send_crs_off_cnt: 0x%08x\n ", que_id, q_crs_off_cnt); + + /* 3.配置成crs非读清 */ + rc = dpp_tm_cfgmt_cnt_mode_get(dev_id, &que_get_mode); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_cnt_mode_get"); + que_get_mode.count_rd_mode = 0; + + rc = dpp_tm_cfgmt_cnt_mode_set(dev_id, &que_get_mode); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_cnt_mode_set"); + + /* 4.恢复通流 */ + rc = dpp_tm_cgavd_td_th_set(dev_id, QUEUE_LEVEL, que_id, flow_td_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_td_th_set"); + } + + else if (2 == valid_flag) /* 仅统计接收，需要源端停流之后运行。*/ + { + /* 设置统计CRDT CRS 接收个数的队列号 */ + crdt_crs_que_id.crs_que_id = ackflow_id; + rc = dpp_reg_write(dev_id, + crdt_crs_que_id_index, + 0, + 0, + &crdt_crs_que_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + /* 1.停流配置读清 */ + /* crdt接收crs读清 */ + rc = dpp_tm_crdt_clr_diag(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_crdt_clr_diag"); + + zxic_comm_sleep(sleep_time); + + + /* 统计CRDT接收到的CRS off总数 */ + rc = dpp_reg_read(dev_id, + all_crs_off_cnt_index, + 0, + 0, + &all_crs_off_cnt); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + /* 统计CRDT指定队列接收到的CRS off总数 */ + rc = dpp_reg_read(dev_id, + que_crd_off_cnt_index, + 0, + 0, + &que_crd_off_cnt); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + + /* 统计CRS接收 */ + /* 统计CRDT接收到的CRS normal总数 */ + rc = dpp_reg_read(dev_id, + all_crs_normal_cnt_index, + 0, + 0, + &all_crs_normal_cnt); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + /* 统计CRDT指定队列接收到的CRS normal总数 */ + rc = dpp_reg_read(dev_id, + que_crs_normal_cnt_index, + 0, + 0, + &que_crs_normal_cnt); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + + + /* 统计CRDT指定队列接收到的crs最后的状态 */ + rc = dpp_reg_read(dev_id, + crs_end_state_index, + 0, + 0, + &crs_end_state); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + /* crdt接收crs读清 */ + rc = dpp_tm_crdt_clr_diag(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_crdt_clr_diag"); + /* 打印统计信息 */ + ZXIC_COMM_PRINT("crdt_recv_all_crs_normal_cnt: 0x%08x\n", all_crs_normal_cnt.fifo_out_all_crs_normal_cnt); + ZXIC_COMM_PRINT("crdt_recv_all_crs_off_cnt: 0x%08x\n", all_crs_off_cnt.fifo_out_all_crs_off_cnt); + ZXIC_COMM_PRINT("ackflow_id(0x%08x)recv_crs_normal_cnt: 0x%08x\n", ackflow_id, que_crs_normal_cnt.fifo_out_que_crs_normal_cnt); + ZXIC_COMM_PRINT("ackflow_id(0x%08x)recv_crs_off_cnt: 0x%08x\n", ackflow_id, que_crd_off_cnt.fifo_out_que_crs_off_cnt); + ZXIC_COMM_PRINT("ackflow_id(0x%08x)recv_crs_end_state: %d\n", ackflow_id, crs_end_state.qmu_crs_end_state); + + + } + else + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "dpp_tm_crs_cnt_prt_1:valid_flag_error!!: 0: print crs of que and ackflow;1:print que crs only; 2:print ackflow crs only\n"); + + } + + + return DPP_OK; + +} + + +/***********************************************************/ +/** 读取qlist入队及出队状态监控 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cy @date 2015/08/26 +************************************************************/ +DPP_STATUS dpp_tm_qmu_qlist_state_query(ZXIC_UINT32 dev_id) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_QCFG_QMU_QLIST_STATE_QUERY_T qcfg_qmu_qlist_state_query = {0}; + + + rc = dpp_reg_read(dev_id, + ETM_QMU_QCFG_QMU_QLIST_STATE_QUERYr, + 0, + 0, + &qcfg_qmu_qlist_state_query); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + ZXIC_COMM_PRINT("pkt_age_req_fifo_afull : %d\n", qcfg_qmu_qlist_state_query.pkt_age_req_fifo_afull); + ZXIC_COMM_PRINT("rd_release_fwft_afull : %d\n", qcfg_qmu_qlist_state_query.rd_release_fwft_afull); + ZXIC_COMM_PRINT("drop_imem_fwft_afull : %d\n", qcfg_qmu_qlist_state_query.drop_imem_fwft_afull); + ZXIC_COMM_PRINT("pkt_age_req_fifo_empty : %d\n", qcfg_qmu_qlist_state_query.pkt_age_req_fifo_empty); + ZXIC_COMM_PRINT("rd_release_fwft_empty : %d\n", qcfg_qmu_qlist_state_query.rd_release_fwft_empty); + ZXIC_COMM_PRINT("drop_imem_fwft_empty : %d\n", qcfg_qmu_qlist_state_query.drop_imem_fwft_empty); + ZXIC_COMM_PRINT("mmu_qmu_sop_rd_rdy : %d\n", qcfg_qmu_qlist_state_query.mmu_qmu_sop_rd_rdy); + ZXIC_COMM_PRINT("big_fifo_empty : %d\n", qcfg_qmu_qlist_state_query.big_fifo_empty); + ZXIC_COMM_PRINT("qmu_mmu_rd_release_rdy : %d\n", qcfg_qmu_qlist_state_query.qmu_mmu_rd_release_rdy); + ZXIC_COMM_PRINT("xsw_qmu_crs_rdy : %d\n", qcfg_qmu_qlist_state_query.xsw_qmu_crs_rdy); + ZXIC_COMM_PRINT("mmu_qmu_rdy : %d\n", qcfg_qmu_qlist_state_query.mmu_qmu_rdy); + ZXIC_COMM_PRINT("mmu_ql_wr_rdy : %d\n", qcfg_qmu_qlist_state_query.mmu_ql_wr_rdy); + ZXIC_COMM_PRINT("mmu_ql_rd_rdy : %d\n", qcfg_qmu_qlist_state_query.mmu_ql_rd_rdy); + ZXIC_COMM_PRINT("csw_ql_rdy : %d\n", qcfg_qmu_qlist_state_query.csw_ql_rdy); + ZXIC_COMM_PRINT("ql_init_done : %d\n", qcfg_qmu_qlist_state_query.ql_init_done); + ZXIC_COMM_PRINT("free_addr_ready : %d\n", qcfg_qmu_qlist_state_query.free_addr_ready); + ZXIC_COMM_PRINT("bank_group_afull : %d\n", qcfg_qmu_qlist_state_query.bank_group_afull); + ZXIC_COMM_PRINT("pds_fwft_empty : %d\n", qcfg_qmu_qlist_state_query.pds_fwft_empty); + ZXIC_COMM_PRINT("enq_rpt_fwft_afull : %d\n", qcfg_qmu_qlist_state_query.enq_rpt_fwft_afull); + + + return DPP_OK; +} + +#endif +/***********************************************************/ +/** 配置QMU流控计数模式 +* @param dev_id 设备号 +* @param tm_type 0-ETM,1-FTM +* @param mode 流控模式，0-电平流控；1-边沿流控 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/05/07 +************************************************************/ +DPP_STATUS dpp_tm_qmu_fc_cnt_mode_set(DPP_DEV_T *dev, ZXIC_UINT32 mode) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_FC_CNT_MODE_T fc_cnt_mode_reg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), mode, 0, 1); + + fc_cnt_mode_reg.fc_cnt_mode = mode; + rc = dpp_reg_write(dev, + ETM_QMU_FC_CNT_MODEr, + 0, + 0, + &fc_cnt_mode_reg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + return DPP_OK; +} + +/***********************************************************/ +/** 读取QMU流控计数模式 +* @param dev_id 设备号 +* @param tm_type 0-ETM,1-FTM +* @param p_mode 流控模式，0-电平流控；1-边沿流控 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/05/07 +************************************************************/ +DPP_STATUS dpp_tm_qmu_fc_cnt_mode_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_mode) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_FC_CNT_MODE_T fc_cnt_mode_reg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_mode); + + rc = dpp_reg_read(dev, + ETM_QMU_FC_CNT_MODEr, + 0, + 0, + &fc_cnt_mode_reg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + *p_mode = fc_cnt_mode_reg.fc_cnt_mode; + + return DPP_OK; +} + +/***********************************************************/ +/** 配置QMU需要检测流控的端口号 +* @param dev_id 设备号 +* @param tm_type 0-ETM,1-FTM +* @param port_id 端口号 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/05/07 +************************************************************/ +DPP_STATUS dpp_tm_qmu_observe_portfc_set(DPP_DEV_T *dev, ZXIC_UINT32 port_id) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_OBSERVE_PORTFC_SPEC_T observe_portfc_reg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), port_id, 0, DPP_TM_PP_NUM - 1); + + + observe_portfc_reg.observe_portfc_spec = port_id; + rc = dpp_reg_write(dev, + ETM_QMU_OBSERVE_PORTFC_SPECr, + 0, + 0, + &observe_portfc_reg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + return DPP_OK; +} + + +/***********************************************************/ +/** 配置QMU需要统计的队列号 +* @param dev_id 设备号 +* @param tm_type 0-ETM,1-FTM +* @param q_id 队列号 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/05/07 +************************************************************/ +DPP_STATUS dpp_tm_qmu_observe_qnum_set(DPP_DEV_T *dev, ZXIC_UINT32 q_id) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_OBSERVE_QNUM_SET_T observe_qnum_reg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), q_id, 0, DPP_ETM_Q_NUM - 1); + + observe_qnum_reg.observe_qnum_set = q_id; + rc = dpp_reg_write(dev, + ETM_QMU_OBSERVE_PORTFC_SPECr, + 0, + 0, + &observe_qnum_reg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + return DPP_OK; +} + + +/***********************************************************/ +/** 配置QMU需要统计的队列组 +* @param dev_id 设备号 +* @param tm_type 0-ETM,1-FTM +* @param batch_id 队列组 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/05/07 +************************************************************/ +DPP_STATUS dpp_tm_qmu_observe_batch_set(DPP_DEV_T *dev, ZXIC_UINT32 batch_id) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_OBSERVE_BATCH_SET_T observe_batch_reg = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), batch_id, 0, 7); + + observe_batch_reg.observe_batch_set = batch_id; + rc = dpp_reg_write(dev, + ETM_QMU_OBSERVE_BATCH_SETr, + 0, + 0, + &observe_batch_reg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + return DPP_OK; +} + + +/****************************************************************************** +*包老化配置 +* @param: dev_id: 设备索引编号 +* @param tm_type 0-ETM,1-FTM +* aging_en: 包老化使能：1表示包老化功能使能；0表示包老化功能关闭。 +* aging_interval: 普通老化两次的间隔配置 +* aging_step_interval: 普通老化的老化时间的步进配置值 +* aging_start_qnum: 老化起始队列 +* aging_end_qnum: 老化结束队列 +* aging_req_aful_th: 普通老化FIFO的将满阈值 +* aging_pkt_num: 一次老化的包个数 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cuiy @date 2016/05/10 +************************************************************/ +DPP_STATUS dpp_tm_qmu_pkt_aging_set(DPP_DEV_T *dev, + ZXIC_UINT32 aging_en, + ZXIC_UINT32 aging_interval, + ZXIC_UINT32 aging_step_interval, + ZXIC_UINT32 aging_start_qnum, + ZXIC_UINT32 aging_end_qnum, + ZXIC_UINT32 aging_pkt_num, + ZXIC_UINT32 aging_req_aful_th) +{ + /* 返回值变量定义 */ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 age_pkt_num_reg_index = 0; + ZXIC_UINT32 age_step_interval_reg_index = 0; + ZXIC_UINT32 age_interval_reg_index = 0; + ZXIC_UINT32 age_qnum_reg_index = 0; + ZXIC_UINT32 age_req_aful_th_reg_index = 0; + ZXIC_UINT32 age_en_reg_index = 0; + + /* 结构体变量定义 */ + DPP_ETM_QMU_CFGMT_QMU_PKT_AGE_EN_T cfg_age_en = {0}; + DPP_ETM_QMU_CFGMT_PKT_AGE_STEP_INTERVAL_T cfg_age_step_interval = {0}; + DPP_ETM_QMU_CFGMT_QMU_PKT_AGE_INTERVAL_T cfg_age_interval = {0}; + DPP_ETM_QMU_CFGMT_QMU_PKT_AGE_START_END_T cfg_age_qnum = {0}; + DPP_ETM_QMU_CFGMT_PKT_AGE_REQ_AFUL_TH_T cfg_age_req_aful_th = {0}; + DPP_ETM_QMU_CFGMT_AGE_PKT_NUM_T cfg_age_pkt_num = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), aging_en, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), aging_step_interval, 0, 0xff); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), aging_interval, 0, 0xffff); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), aging_req_aful_th, 0, 0x3f); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), aging_pkt_num, 0, 0xf); + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), aging_start_qnum, 0, DPP_ETM_Q_NUM - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), aging_end_qnum, 0, DPP_ETM_Q_NUM - 1); + age_pkt_num_reg_index = ETM_QMU_CFGMT_AGE_PKT_NUMr; + age_step_interval_reg_index = ETM_QMU_CFGMT_PKT_AGE_STEP_INTERVALr; + age_interval_reg_index = ETM_QMU_CFGMT_QMU_PKT_AGE_INTERVALr; + age_qnum_reg_index = ETM_QMU_CFGMT_QMU_PKT_AGE_START_ENDr; + age_req_aful_th_reg_index = ETM_QMU_CFGMT_PKT_AGE_REQ_AFUL_THr; + age_en_reg_index = ETM_QMU_CFGMT_QMU_PKT_AGE_ENr; + + cfg_age_en.cfgmt_qmu_pkt_age_en = aging_en; + cfg_age_step_interval.cfgmt_pkt_age_step_interval = aging_step_interval; + cfg_age_interval.cfgmt_qmu_pkt_age_interval = aging_interval; + cfg_age_qnum.cfgmt_qmu_pkt_age_start = aging_start_qnum; + cfg_age_qnum.cfgmt_qmu_pkt_age_end = aging_end_qnum; + cfg_age_req_aful_th.cfgmt_pkt_age_req_aful_th = aging_req_aful_th; + cfg_age_pkt_num.cfgmt_age_pkt_num = aging_pkt_num; + + + rc = dpp_reg_write(dev, + age_pkt_num_reg_index, + 0, + 0, + &cfg_age_pkt_num); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + rc = dpp_reg_write(dev, + age_step_interval_reg_index, + 0, + 0, + &cfg_age_step_interval); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + rc = dpp_reg_write(dev, + age_interval_reg_index, + 0, + 0, + &cfg_age_interval); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + rc = dpp_reg_write(dev, + age_qnum_reg_index, + 0, + 0, + &cfg_age_qnum); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + rc = dpp_reg_write(dev, + age_req_aful_th_reg_index, + 0, + 0, + &cfg_age_req_aful_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + rc = dpp_reg_write(dev, + age_en_reg_index, + 0, + 0, + &cfg_age_en); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + return DPP_OK; +} + + +/****************************************************************************** +*配置老化一个包的时间，一次老化一个包，老化队列范围为可配 +* @param: dev_id: 设备索引编号 +* @param tm_type 0: etm; 1: ftm; +* aging_en: 包老化使能：1表示包老化功能使能；0表示包老化功能关闭。 +* aging_time: 老化一个包的时间，单位ms + aging_que_start:老化起始队列 + aging_que_start:老化终止队列 +老化时间=2*aging_interval*step_interval*q_num +aging_interval = (aging_time * 600000) / (2 * 1 * DPP_TM_Q_NUM); +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xuhb @date 2020/12/08 +************************************************************/ +DPP_STATUS dpp_tm_qmu_pkt_age_time_set(DPP_DEV_T *dev, + ZXIC_UINT32 aging_en, + ZXIC_UINT32 aging_time, + ZXIC_UINT32 aging_que_start, + ZXIC_UINT32 aging_que_end) +{ + /* 返回值变量定义 */ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 aging_interval = 0; + //DPP_CRM_CSR_PLL_CLK_SEL_T pll_clk_sel_t = {0}; + // ZXIC_UINT32 sys_clk = 0; + // ZXIC_UINT32 sys_clk_temp[8]={200,250,300,500,600,800,1000,1200}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), aging_en, 0, 1); + + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), aging_que_start, 0, DPP_ETM_Q_NUM - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), aging_que_end, 0, DPP_ETM_Q_NUM - 1); +#if 0 + rc = dpp_reg_read(dev_id, + CRM_CSR_PLL_CLK_SELr, + 0, + 0, + &pll_clk_sel_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pll_clk_sel_t.sys_clk_2x_sel, CRM_SYS_CLK_200M, CRM_SYS_CLK_INVALID - 1); + + sys_clk = sys_clk_temp[pll_clk_sel_t.sys_clk_2x_sel] / 2; + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, aging_time , sys_clk ); + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, aging_time * sys_clk , DPP_TM_KILO_ULL); + aging_interval = (aging_time * sys_clk * DPP_TM_KILO_ULL * DPP_TM_KILO_ULL / 1000) / (2 * 1 * (aging_que_end - aging_que_start + 1)); +#endif + + + if (0 == aging_interval) + { + aging_interval = 1; /* 防止算出来的是小数，导致写入0 */ + } + + rc = dpp_tm_qmu_pkt_aging_set(dev, aging_en, aging_interval, 1, aging_que_start, aging_que_end, 1, 0xa); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_qmu_pkt_aging_set"); + + return DPP_OK; +} + +#if 0 +/***********************************************************/ +/** 获得队列空标志查询 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param qnum 配置的队列号 +* @param p_value 队列空标志查询 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author cy @date 2016/06/20 +************************************************************/ +DPP_STATUS dpp_tm_qlist_ept_flag_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 qnum, + ZXIC_UINT32 *p_value) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_QCFG_QLIST_EPT_RD_T qcfg_qlist_ept_rd = {0}; + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_value); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, qnum, 0, DPP_ETM_Q_NUM - 1); + + rc = dpp_reg_read(dev_id, + ETM_QMU_QCFG_QLIST_EPT_RDr, + 0, + qnum, + &qcfg_qlist_ept_rd); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + *p_value = qcfg_qlist_ept_rd.qcfg_qlist_ept_rd; + + return DPP_OK; +} + + +/***********************************************************/ +/** 获得队列深度计数 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param qnum 配置的队列号 +* @param p_value 队列深度计数 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author cy @date 2016/06/20 +************************************************************/ +DPP_STATUS dpp_tm_qlist_r_bcnt_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 qnum, + ZXIC_UINT32 *p_value) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_QLIST_R_BCNT_T qlist_r_bcnt = {0}; + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_value); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, qnum, 0, DPP_ETM_Q_NUM - 1); + + rc = dpp_reg_read(dev_id, + ETM_QMU_QLIST_R_BCNTr, + 0, + qnum, + &qlist_r_bcnt); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + *p_value = qlist_r_bcnt.qlist_r_bcnt; + + return DPP_OK; +} + +#endif +/***********************************************************/ +/** 配置pfc使能 +* @param dev_id 设备编号 +* @param pfc_en 配置的值，0-不使能pfc，1-使能pfc +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author lsy @date 2022/08/22 +************************************************************/ +DPP_STATUS dpp_tm_qmu_pfc_en_set(DPP_DEV_T *dev, ZXIC_UINT32 pfc_en) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_CFGMT_QMU_PFC_EN_T qmu_pfc_en = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), pfc_en, 0, 1); + + qmu_pfc_en.cfgmt_qmu_pfc_en = pfc_en; + rc = dpp_reg_write(dev, + ETM_QMU_CFGMT_QMU_PFC_ENr, + 0, + 0, + &qmu_pfc_en); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + return DPP_OK; +} + +/***********************************************************/ +/** 读取pfc使能 +* @param dev_id 设备编号 +* @param pfc_en 配置的值，0-不使能pfc，1-使能pfc +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author lsy @date 2022/08/22 +************************************************************/ +DPP_STATUS dpp_tm_qmu_pfc_en_get(DPP_DEV_T *dev, ZXIC_UINT32 *pfc_en) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_CFGMT_QMU_PFC_EN_T qmu_pfc_en = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), pfc_en); + + *pfc_en = 0xffffffff; + rc = dpp_reg_read(dev, + ETM_QMU_CFGMT_QMU_PFC_ENr, + 0, + 0, + &qmu_pfc_en); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + *pfc_en = qmu_pfc_en.cfgmt_qmu_pfc_en; + + return DPP_OK; +} + +/***********************************************************/ +/** 配置端口pfc掩码 +* @param dev_id 设备编号 +* @param port_id 端口号：0~63 +* @param port_en 端口掩码配置，1pfc模式下该端口接收olif的优先级反压， +* 0pfc模式下该端口不接受olif的优先级反压，并将反压信号全部置1 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author lsy @date 2022/08/22 +************************************************************/ +DPP_STATUS dpp_tm_qmu_port_pfc_make_set(DPP_DEV_T *dev, + ZXIC_UINT32 port_id, + ZXIC_UINT32 port_en) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 value = 0; + DPP_ETM_QMU_CFGMT_QMU_PFC_MASK_1_T pfc_mask_31_0 = {0}; + DPP_ETM_QMU_CFGMT_QMU_PFC_MASK_2_T pfc_mask_63_32 = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), port_id, 0, DPP_TM_PP_NUM - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), port_en, 0, 1); + + if (port_id <= 31) + { + /* port_id:[0-31] */ + rc = dpp_reg_read(dev, + ETM_QMU_CFGMT_QMU_PFC_MASK_1r, + 0, + 0, + &pfc_mask_31_0); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + value = pfc_mask_31_0.cfgmt_qmu_pfc_mask_1; + + if (port_en == 0) + { + value = value & (~(1u << port_id)); + } + else + { + value = value | (1u << port_id); + } + + pfc_mask_31_0.cfgmt_qmu_pfc_mask_1 = value; + + rc = dpp_reg_write(dev, + ETM_QMU_CFGMT_QMU_PFC_MASK_1r, + 0, + 0, + &pfc_mask_31_0); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + } + else + { + /* port_id:[32-63] */ + rc = dpp_reg_read(dev, + ETM_QMU_CFGMT_QMU_PFC_MASK_2r, + 0, + 0, + &pfc_mask_63_32); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + value = pfc_mask_63_32.cfgmt_qmu_pfc_mask_2; + + if (port_en == 0) + { + value = value & (~(1u << (port_id - 32))); + } + else + { + value = value | (1u<< (port_id - 32)); + } + + pfc_mask_63_32.cfgmt_qmu_pfc_mask_2 = value; + + rc = dpp_reg_write(dev, + ETM_QMU_CFGMT_QMU_PFC_MASK_2r, + 0, + 0, + &pfc_mask_63_32); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + } + + return DPP_OK; +} + +/***********************************************************/ +/** 获得端口pfc掩码 +* @param dev_id 设备编号 +* @param port_id 端口号：0~63 +* @param port_en 端口掩码配置，1pfc模式下该端口接收olif的优先级反压， +* 0pfc模式下该端口不接受olif的优先级反压，并将反压信号全部置1 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author lsy @date 2022/08/22 +************************************************************/ +DPP_STATUS dpp_tm_qmu_port_pfc_make_get(DPP_DEV_T *dev, + ZXIC_UINT32 port_id, + ZXIC_UINT32 *p_port_en) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 value = 0; + DPP_ETM_QMU_CFGMT_QMU_PFC_MASK_1_T pfc_mask_31_0 = {0}; + DPP_ETM_QMU_CFGMT_QMU_PFC_MASK_2_T pfc_mask_63_32 = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), port_id, 0, DPP_TM_PP_NUM - 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_port_en); + + if (port_id <= 31) + { + /* port_id:[0-31] */ + rc = dpp_reg_read(dev, + ETM_QMU_CFGMT_QMU_PFC_MASK_1r, + 0, + 0, + &pfc_mask_31_0); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + value = pfc_mask_31_0.cfgmt_qmu_pfc_mask_1; + + *p_port_en = 1 & (value >> port_id); + } + else + { + /* port_id:[32-63] */ + rc = dpp_reg_read(dev, + ETM_QMU_CFGMT_QMU_PFC_MASK_2r, + 0, + 0, + &pfc_mask_63_32); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + value = pfc_mask_63_32.cfgmt_qmu_pfc_mask_2; + + *p_port_en = 1 & (value >> (port_id - 32)); + } + + return DPP_OK; +} + +#if 0 +/***********************************************************/ +/** QMU初始化配置场景 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param case_no QMU初始化场景编号 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cuiy @date 2020/4/14 +************************************************************/ +DPP_STATUS dpp_tm_qmu_init_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 case_no_temp) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 case_no = 0; + ZXIC_UINT32 ftm_ddr_no = 0; + ZXIC_UINT32 etm_ddr_no = 0; + + + g_qmu_init_case_no = case_no_temp; + + if ((case_no_temp & 0xff) == 0xef && (case_no_temp >> 8)!= 0 && (case_no_temp >> + 16 != 0)) + { + case_no = 0xef; + ZXIC_COMM_PRINT("Here get in qmu init:%d case_num is %d\n", case_no); + /*低8-15bit作为FTM的DDR0-9中的编号,高16-23bit作为ETM的DDR0-9中的编号(only case_16 use)*/ + ftm_ddr_no = (case_no_temp >> 8) & 0xff; + etm_ddr_no = (case_no_temp >> 16) & 0xff; + } + else if ((case_no_temp & 0xf) == 0xc) + { + /*etm 和ftm共享指定1组ddr 8bank,其中etm 0-3bank ftm 4-7bank*/ + case_no = 0xc; + } + else if ((case_no_temp & 0xf) == 0xd) + { + /*一个tm独享指定4组8bank*/ + case_no = 0xd; + } + else if(((case_no_temp & 0xf) == 0xe) || ((case_no_temp & 0xf) == 0xf) \ + || ((case_no_temp & 0xf) == 0xb)) + { + /*提取case_no_temp的低4bit作为case_no*/ + case_no = case_no_temp & 0xf; + ZXIC_COMM_PRINT("Here get in qmu init:%d case_num is %d\n", case_no); + + /*中间4bit作为ETM的DDR0-9中的编号,最高4bit作为FTM的DDR0-9中的编号(only case_11 14 15 use)*/ + ftm_ddr_no = (case_no_temp >> 4) & 0xf; + etm_ddr_no = (case_no_temp >> 8) & 0xf; + } + else + { + case_no = case_no_temp & 0xf; + } + /**clear mmu qmu**/ + rc = dpp_tm_qmu_mmu_cfg_clr(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_mmu_cfg_clr"); + + + if (case_no == 0) + { + /**纯片内pd16k模式**/ + //rc = dpp_tm_qmu_init_set_pd16k_2(dev_id, 64); + //ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_init_set_pd16k_2"); + + rc = dpp_tm_qmu_init_set_chuk32(dev_id, 512); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_init_set_chuk32"); + } + else if (case_no == 1) + { + /* 场景1：每个tm用8组*4bank，MMU实际分配ftm:0-7组(0145bank); etm:2-9组(2367bank) */ + rc = dpp_tm_qmu_init_set_1(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_init_set_1"); + } + else if (case_no == 2) + { + /* 场景2：tm独享8组ddr:ftm为0-7组ddr的0123bank，etm为0-7组ddr 4567bank */ + rc = dpp_tm_qmu_init_set_2(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_init_set_2"); + } + else if (case_no == 3) + { + /* 场景3：TM独享8组ddr:FTM为0-3组ddr的0~3bank，ETM为4-7组ddr 0~3bank */ + rc = dpp_tm_qmu_init_set_3(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_init_set_3"); + } + else if (case_no == 4) + { + /* 场景4：TM共享2组ddr:FTM为2、4组ddr的01bank，ETM为2、4组ddr 23bank */ + /*需开启IP_rotation、mmu multi_burst,关闭mmu_rotation_en*/ + rc = dpp_tm_qmu_init_set_4(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_init_set_4"); + } + else if (case_no == 5) + { + /* 场景5：TM共享4组ddr:FTM为1234组ddr的01bank，ETM为1234组ddr 23bank */ + /*需开启IP_rotation、mmu multi_burst,关闭mmu_rotation_en*/ + rc = dpp_tm_qmu_init_set_5(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_init_set_5"); + } + else if (case_no == 6) + { + /*场景6：4组*2bank，MMU实际分配4,6,7,9; etm使用01bank,ftm使用23bank*/ + /*需开启IP_rotation、mmu multi_burst,关闭mmu_rotation_en*/ + rc = dpp_tm_qmu_init_set_6(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_init_set_6"); + } + else if (case_no == 7) + { + /* 关闭rotation*/ + //rc = dpp_mmu_init(0, 0, 0, 0, 0); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_mmu_init"); + /* 场景7：每个tm用8组*4bank，MMU实际分配ftm:2-9组(0145bank); etm:2-9组(2367bank) */ + rc = dpp_tm_qmu_init_set_7(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_init_set_7"); + } + else if (case_no == 8) + { + /* 场景8：每个tm用8组*4bank，MMU实际分配ftm:2-9组(01bank); etm:2-9组(23bank) */ + /*需开启IP_rotation、mmu multi_burst,关闭mmu_rotation_en*/ + rc = dpp_tm_qmu_init_set_8(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_init_set_8"); + } + else if (case_no == 9) + { + /*场景9：4组*2bank，MMU实际分配6,7,8,9; etm使用01bank,ftm使用23bank*/ + /*需开启IP_rotation、mmu multi_burst,关闭mmu_rotation_en*/ + rc = dpp_tm_qmu_init_set_9(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_init_set_9"); + } + else if (case_no == 10) + { + /* 关闭rotation*/ + //rc = dpp_mmu_init(0, 0, 0, 0, 0); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_mmu_init"); + /*场景10：独享2组*8bank，MMU实际分配1,2; etm or ftm使用0-7bank*/ + rc = dpp_tm_qmu_init_set_10(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_init_set_10"); + } + else if (case_no == 11) + { + /*场景11：TM共享2组ddr:FTM为ddr_no1,ddr_no2组ddr的01bank，ETM为ddr_no1,ddr_no2组ddr 23bank*/ + rc = dpp_tm_qmu_init_set_11(dev_id, ftm_ddr_no, etm_ddr_no); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_init_set_11"); + } + else if (case_no == 0xc) + { + /*etm 和ftm共享指定1组ddr 8bank,其中etm 0-3bank ftm 4-7bank*/ + rc = dpp_tm_qmu_init_set_12(dev_id, case_no_temp >> 4); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_init_set_12"); + } + else if (case_no == 0xd) + { + /* 关闭rotation 配置8bank必须关掉，不然会出现crc错包*/ + //rc = dpp_mmu_init(0, 0, 0, 0, 0); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_mmu_init"); + /*场景13：TM独享4组0-7bank,ddr编号来自传参,如0x6789 即代表独享6 7 8 + 9组ddr的全部bank*/ + rc = dpp_tm_qmu_init_set_13(dev_id, case_no_temp >> 4); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_init_set_13"); + } + else if (case_no == 0xe) + { + /* 关闭rotation*/ + //rc = dpp_mmu_init(dev_id, 0, 0, 0, 0); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_mmu_init"); + + /* 场景14：每个tm只用1组*8bank，MMU实际分配ftm:0-9中指定组(0-7bank); etm:0-9中指定组(0-7bank) */ + rc = dpp_tm_qmu_init_set_14(dev_id, etm_ddr_no, ftm_ddr_no); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_init_set_8"); + } + else if (case_no == 0xf) + { + /* 场景15：每个tm只用1组*4bank，MMU实际分配ftm:0-9中指定组(0123bank); etm:0-9中指定组(0123bank) */ + rc = dpp_tm_qmu_init_set_15(dev_id, etm_ddr_no, ftm_ddr_no); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_init_set_8"); + } + else/* if (case_no == 0xef)*/ + { + /* 关闭rotation*/ + //rc = dpp_mmu_init(0, 0, 0, 0, 0); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_mmu_init"); + /* 场景15：每个tm只用2组*8bank，MMU实际分配ftm:0-9中指定组(0-7bank); etm:0-9中指定组(0-7bank) */ + rc = dpp_tm_qmu_init_set_16(dev_id, etm_ddr_no, ftm_ddr_no); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_init_set_16"); + } + + return DPP_OK; +} + + + +/***********************************************************/ +/** QMU/MMU初始化配置场景1：每个tm用8组*4bank，MMU实际分配ftm:0-7组(0145bank); etm:2-9组(2367bank) +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/10/14 +************************************************************/ +DPP_STATUS dpp_etm_qmu_init_set_1(ZXIC_UINT32 dev_id) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 k = 0; + ZXIC_UINT32 i = 0; + ZXIC_UINT32 j = 0; + ZXIC_UINT32 depth = 1024; + ZXIC_UINT32 bank_to_mmu_cfg_map[4] = {2, 3, 6, 7}; + ZXIC_UINT32 qlist_grp0_bank_data[4] = {0, 1, 2, 3}; + + + DPP_ETM_QMU_QCFG_QLIST_BDEP_T qlist_bdep = {0}; + DPP_ETM_QMU_QCFG_QLIST_BHEAD_T qlist_bhead = {0}; + DPP_ETM_QMU_QCFG_QLIST_BTAIL_T qlist_btail = {0}; + + DPP_ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFG_T active_to_bank_cfg = {0}; + DPP_ETM_QMU_CFGMT_DDR_IN_MMU_CFG_T ddr_in_mmu_cfg = {0}; + DPP_ETM_QMU_CFGMT_DDR_IN_QMU_CFG_T ddr_in_qmu_cfg = {0}; + DPP_ETM_QMU_CFGMT_BANK_TO_MMU_CFG_T bank_to_mmu_cfg = {0}; + DPP_ETM_QMU_CFGMT_BANK_TO_QMU_CFG_T bank_to_qmu_cfg = {0}; + DPP_ETM_QMU_QCFG_QLIST_GRP0_BANK_T qlist_grp0_bank = {0}; + + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "========dpp_etm_qmu_init_set_1 start========n"); + + + /* ddr组从qmu到mmu映射,0~7映射成2~9 */ + for (i = 0; i < 8; i++) + { + ddr_in_mmu_cfg.cfgmt_ddr_in_mmu_cfg = (i + 2); + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_DDR_IN_MMU_CFGr, + 0, + i, + &ddr_in_mmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + /* ddr组从mmu到qmu映射,2~9映射成0~7 */ + for (i = 2; i < 10; i++) + { + ddr_in_qmu_cfg.cfgmt_ddr_in_qmu_cfg = (i - 2); + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_DDR_IN_QMU_CFGr, + 0, + i, + &ddr_in_qmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + + /* bank号从qmu到mmu映射，每组的bank0~3映射成bank2、3、6、7 */ + for (j = 0; j < 8; j++) + { + for (i = 0; i < 4; i++) + { + k = j * 8 + i; + + bank_to_mmu_cfg.cfgmt_bank_in_mmu_cfg = bank_to_mmu_cfg_map[i]; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_BANK_TO_MMU_CFGr, + 0, + k, + &bank_to_mmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + } + + + /* bank号从mmu到qmu映射，每组的bank2、3、6、7映射成bank0、1、2、3 */ + for (j = 2; j < 10; j++) + { + for (i = 0; i < 4; i++) + { + ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(dev_id, j * 8 , bank_to_mmu_cfg_map[i]); + k = j * 8 + bank_to_mmu_cfg_map[i]; + + bank_to_qmu_cfg.cfgmt_bank_in_qmu_cfg = i; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_BANK_TO_QMU_CFGr, + 0, + k, + &bank_to_qmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + } + + /* random映射ram:配置一个chunk中，bank的轮询顺序 */ + for (i = 0; i < 16; i++) + { + + + active_to_bank_cfg.cfgmt_active_to_bank_cfg = i % 4; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFGr, + 0, + i, + &active_to_bank_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + } + + + /* 首尾深度指针配置 */ + for (j = 0; j < 8; j++) + { + for (i = 0; i < 4; i++) + { + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, (j * 4 + i) , depth); + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, (j * 4 + i + 1) , depth); + k = j * 8 + i; + qlist_bhead.bank_vld = 1; + qlist_bhead.qcfg_qlist_bhead = (j * 4 + i) * depth; + qlist_btail.qcfg_qlist_btail = ((j * 4 + i + 1) * depth - 1); + qlist_bdep.qcfg_qlist_bdep = depth; + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BHEADr, + 0, + k, + &qlist_bhead); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BTAILr, + 0, + k, + &qlist_btail); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BDEPr, + 0, + k, + &qlist_bdep); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + } + + + ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(ETM_QMU_QCFG_QLIST_GRP0_BANKr, 8); + /* 随机表配置，决定每组bank的轮询顺序 */ + for (j = 0; j < 8; j++) + { + for (i = 0; i < 64; i++) + { + qlist_grp0_bank.qcfg_qlist_grp0_bank_wr = qlist_grp0_bank_data[i % 4]; + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_GRP0_BANKr + j, + 0, + i, + &qlist_grp0_bank); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + } + + rc = dpp_tm_qmu_cfg_done_set(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_cfg_done_set"); + + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "========dpp_etm_qmu_init_set_1 END=======\n"); + + return DPP_OK; +} + + + + +/***********************************************************/ +/** QMU/MMU初始化配置场景1：每个tm用8组*4bank，MMU实际分配ftm:0-7组(0145bank); etm:2-9组(2367bank) +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/10/14 +************************************************************/ +DPP_STATUS dpp_tm_qmu_init_set_1(ZXIC_UINT32 dev_id) +{ + DPP_STATUS rc = DPP_OK; + + /* etm mmu基址配置:ddr2-9组，bank号2367，bank深度1024 */ + //rc = dpp_mmu_bank_base_addr_set(dev_id, 0x3fc, 0xcc, 1024); + //ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_mmu_bank_base_addr_set"); + + rc = dpp_etm_qmu_init_set_1(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_etm_qmu_init_set"); + + return DPP_OK; +} + +/***********************************************************/ +/** QMU/MMU初始化配置场景二：tm独享8组ddr:ftm为0-7组ddr的0123bank，etm为0-7组ddr 4567bank +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/10/16 +************************************************************/ +DPP_STATUS dpp_etm_qmu_init_set_2(ZXIC_UINT32 dev_id) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 k = 0; + ZXIC_UINT32 i = 0; + ZXIC_UINT32 j = 0; + ZXIC_UINT32 depth = 1024; + ZXIC_UINT32 qlist_grp0_bank_data[4] = {1, 2, 3, 0}; + + DPP_ETM_QMU_QCFG_QLIST_BDEP_T qlist_bdep = {0}; + DPP_ETM_QMU_QCFG_QLIST_BHEAD_T qlist_bhead = {0}; + DPP_ETM_QMU_QCFG_QLIST_BTAIL_T qlist_btail = {0}; + + DPP_ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFG_T active_to_bank_cfg = {0}; + DPP_ETM_QMU_CFGMT_DDR_IN_MMU_CFG_T ddr_in_mmu_cfg = {0}; + DPP_ETM_QMU_CFGMT_DDR_IN_QMU_CFG_T ddr_in_qmu_cfg = {0}; + DPP_ETM_QMU_CFGMT_BANK_TO_MMU_CFG_T bank_to_mmu_cfg = {0}; + DPP_ETM_QMU_CFGMT_BANK_TO_QMU_CFG_T bank_to_qmu_cfg = {0}; + DPP_ETM_QMU_QCFG_QLIST_GRP0_BANK_T qlist_grp0_bank = {0}; + + + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "++++++dpp_etm_qmu_init_set starting++++++\n"); + + + /* ddr组从qmu到mmu映射,0~7映射成0~7 */ + for (i = 0; i < 8; i++) + { + ddr_in_mmu_cfg.cfgmt_ddr_in_mmu_cfg = i; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_DDR_IN_MMU_CFGr, + 0, + i, + &ddr_in_mmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + /* ddr组从mmu到qmu映射,0~7映射成0~7 */ + for (i = 0; i < 8; i++) + { + ddr_in_qmu_cfg.cfgmt_ddr_in_qmu_cfg = i; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_DDR_IN_QMU_CFGr, + 0, + i, + &ddr_in_qmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + + /* bank号从qmu到mmu映射，每组bank0、1、2、3映射成bank4567，组0~7循环配置 */ + for (j = 0; j < 8; j++) + { + for (i = 0; i < 4; i++) + { + k = j * 8 + i; + bank_to_mmu_cfg.cfgmt_bank_in_mmu_cfg = (i + 4); + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_BANK_TO_MMU_CFGr, + 0, + k, + &bank_to_mmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + } + + + /* bank号从mmu到qmu映射，每组bank4567映射成bank0、1、2、3，组0~7循环配置 */ + for (j = 0; j < 8; j++) + { + for (i = 4; i < 8; i++) + { + + k = j * 8 + i; + bank_to_qmu_cfg.cfgmt_bank_in_qmu_cfg = (i - 4); + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_BANK_TO_QMU_CFGr, + 0, + k, + &bank_to_qmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + } + + /* random映射ram:配置一个chunk中，bank的轮询顺序 */ + for (i = 0; i < 16; i++) + { + active_to_bank_cfg.cfgmt_active_to_bank_cfg = i % 4; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFGr, + 0, + i, + &active_to_bank_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + + /* 首尾深度指针配置:j为4组循环 */ + for (j = 0; j < 8; j++) + { + for (i = 0; i < 4; i++) + { + k = j * 8 + i; + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, (j * 4 + i), depth); + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, (j * 4 + i + 1), depth); + qlist_bhead.bank_vld = 1; + qlist_bhead.qcfg_qlist_bhead = (j * 4 + i) * depth; + qlist_btail.qcfg_qlist_btail = ((j * 4 + i + 1) * depth - 1); + qlist_bdep.qcfg_qlist_bdep = depth; + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BHEADr, + 0, + k, + &qlist_bhead); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BTAILr, + 0, + k, + &qlist_btail); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BDEPr, + 0, + k, + &qlist_bdep); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + } + + ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(ETM_QMU_QCFG_QLIST_GRP0_BANKr, 8); + /* 随机表配置，决定ddr内bank的轮询顺序:使用几组ddr需要配置几组 */ + for (j = 0; j < 8; j++) + { + for (i = 0; i < 64; i++) + { + + qlist_grp0_bank.qcfg_qlist_grp0_bank_wr = qlist_grp0_bank_data[i % 4]; + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_GRP0_BANKr + j, + 0, + i, + &qlist_grp0_bank); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + } + } + + rc = dpp_tm_qmu_cfg_done_set(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_cfg_done_set"); + + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "++++++dpp_etm_qmu_init_set end++++++\n"); + + return DPP_OK; +} + + + +/***********************************************************/ +/** QMU/MMU初始化配置场景二：tm独享8组ddr:ftm为0-7组ddr的0123bank，etm为0-7组ddr 4567bank +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/10/16 +************************************************************/ +DPP_STATUS dpp_tm_qmu_init_set_2(ZXIC_UINT32 dev_id) +{ + DPP_STATUS rc = DPP_OK; + + /* etm mmu基址配置:ddr0-7组，bank号4567，bank深度1024 */ + //rc = dpp_mmu_bank_base_addr_set(dev_id, 0xff, 0xf0, 1024); + //ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_mmu_bank_base_addr_set"); + + rc = dpp_etm_qmu_init_set_2(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_etm_qmu_init_set"); + + + return DPP_OK; +} + +/***********************************************************/ +/** QMU初始化配置场景二：ddr3模式，tm看到4组*4bank，对应DDR分配4~7组，每组2~3,6~7bank +* depth=64,代表16k +* @param dev_id 设备编号 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cuiy @date 2016/11/17 +************************************************************/ +DPP_STATUS dpp_etm_qmu_init_set_pd16k_2(ZXIC_UINT32 dev_id, ZXIC_UINT32 depth) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 k = 0; + ZXIC_UINT32 i = 0; + ZXIC_UINT32 j = 0; + ZXIC_UINT32 qlist_grp0_bank_data[4] = {1, 2, 3, 0}; + ZXIC_UINT32 ddr_num = 4; + + DPP_ETM_QMU_QCFG_QLIST_BDEP_T qlist_bdep = {0}; + DPP_ETM_QMU_QCFG_QLIST_BHEAD_T qlist_bhead = {0}; + DPP_ETM_QMU_QCFG_QLIST_BTAIL_T qlist_btail = {0}; + DPP_ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFG_T active_to_bank_cfg = {0}; + DPP_ETM_QMU_CFGMT_DDR_IN_MMU_CFG_T ddr_in_mmu_cfg = {0}; + DPP_ETM_QMU_CFGMT_DDR_IN_QMU_CFG_T ddr_in_qmu_cfg = {0}; + DPP_ETM_QMU_CFGMT_BANK_TO_MMU_CFG_T bank_to_mmu_cfg = {0}; + DPP_ETM_QMU_CFGMT_BANK_TO_QMU_CFG_T bank_to_qmu_cfg = {0}; + DPP_ETM_QMU_QCFG_QLIST_GRP0_BANK_T qlist_grp0_bank = {0}; + DPP_ETM_QMU_QCFG_QLIST_GRP1_BANK_T qlist_grp1_bank = {0}; + DPP_ETM_QMU_QCFG_QLIST_GRP2_BANK_T qlist_grp2_bank = {0}; + DPP_ETM_QMU_QCFG_QLIST_GRP3_BANK_T qlist_grp3_bank = {0}; + + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "++++++dpp_etm_qmu_init_set starting++++++\n"); + + /* cfgmt配置4组ddr */ + rc = dpp_tm_cfgmt_ddr_attach_set(dev_id, ddr_num); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_ddr_attach_set"); + + + /* ddr组从qmu到mmu映射,0~3映射成4~7 */ + for (i = 0; i < 4; i++) + { + ddr_in_mmu_cfg.cfgmt_ddr_in_mmu_cfg = (i + 4); + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_DDR_IN_MMU_CFGr, + 0, + i, + &ddr_in_mmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + /* ddr组从mmu到qmu映射,4~7映射成0~3 */ + for (i = 4; i < 8; i++) + { + ddr_in_qmu_cfg.cfgmt_ddr_in_qmu_cfg = (i - 4); + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_DDR_IN_QMU_CFGr, + 0, + i, + &ddr_in_qmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + + /* bank号从qmu到mmu映射，每组bank0、1、2、3映射成bank2、3、6、7，组0~3循环配置 */ + for (j = 0; j < 4; j++) + { + for (i = 0; i < 4; i++) + { + k = j * 8 + i; + + if (i < 2) + { + bank_to_mmu_cfg.cfgmt_bank_in_mmu_cfg = (i + 2); + } + else + { + bank_to_mmu_cfg.cfgmt_bank_in_mmu_cfg = (i + 4); + } + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_BANK_TO_MMU_CFGr, + 0, + k, + &bank_to_mmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + } + + + /* bank号从mmu到qmu映射，每组bank2、3、6、7映射成bank0、1、2、3，组4~7循环配置 */ + for (j = 4; j < 8; j++) + { + for (i = 2; i < 6; i++) + { + if (i < 4) + { + k = j * 8 + i; + } + else + { + k = j * 8 + i + 2; + } + + bank_to_qmu_cfg.cfgmt_bank_in_qmu_cfg = (i - 2); + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_BANK_TO_QMU_CFGr, + 0, + k, + &bank_to_qmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + } + + /* random映射ram */ + for (j = 0; j < 4; j++) + { + for (i = 0; i < 4; i++) + { + k = j * 4 + i; + + active_to_bank_cfg.cfgmt_active_to_bank_cfg = i; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFGr, + 0, + k, + &active_to_bank_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + } + + + /* 首尾深度指针配置:j为4组循环 */ + for (j = 0; j < 4; j++) + { + for (i = 0; i < 4; i++) + { + k = j * 8 + i; + + qlist_bhead.bank_vld = 1; + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, (j * 4 + i), depth); + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, (j * 4 + i + 1), depth); + qlist_bhead.qcfg_qlist_bhead = (j * 4 + i) * depth; + qlist_btail.qcfg_qlist_btail = ((j * 4 + i + 1) * depth - 1); + qlist_bdep.qcfg_qlist_bdep = depth; + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BHEADr, + 0, + k, + &qlist_bhead); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BTAILr, + 0, + k, + &qlist_btail); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BDEPr, + 0, + k, + &qlist_bdep); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + } + + + /* 随机表配置，决定每组bank的轮询顺序 */ + for (j = 0; j < 16; j++) + { + for (i = 0; i < 4; i++) + { + k = j * 4 + i; + + qlist_grp0_bank.qcfg_qlist_grp0_bank_wr = qlist_grp0_bank_data[i];; + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_GRP0_BANKr, + 0, + k, + &qlist_grp0_bank); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + } + } + + for (j = 0; j < 16; j++) + { + for (i = 0; i < 4; i++) + { + k = j * 4 + i; + + qlist_grp1_bank.qcfg_qlist_grp1_bank_wr = qlist_grp0_bank_data[i];; + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_GRP1_BANKr, + 0, + k, + &qlist_grp1_bank); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + } + } + + for (j = 0; j < 16; j++) + { + for (i = 0; i < 4; i++) + { + k = j * 4 + i; + + qlist_grp2_bank.qcfg_qlist_grp2_bank_wr = qlist_grp0_bank_data[i];; + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_GRP2_BANKr, + 0, + k, + &qlist_grp2_bank); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + } + } + + for (j = 0; j < 16; j++) + { + for (i = 0; i < 4; i++) + { + k = j * 4 + i; + + qlist_grp3_bank.qcfg_qlist_grp3_bank_wr = qlist_grp0_bank_data[i];; + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_GRP3_BANKr, + 0, + k, + &qlist_grp3_bank); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + } + } + + rc = dpp_tm_qmu_cfg_done_set(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_cfg_done_set"); + + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "++++++dpp_etm_qmu_init_set end++++++\n"); + + return DPP_OK; +} + + +/***********************************************************/ +/** QMU初始化配置场景二：ddr3模式，tm看到4组*4bank，对应DDR分配4~7组，每组2~3,6~7bank +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cuiy @date 2016/11/17 +************************************************************/ +DPP_STATUS dpp_tm_qmu_init_set_pd16k_2(ZXIC_UINT32 dev_id, ZXIC_UINT32 depth) +{ + DPP_STATUS rc = DPP_OK; + + rc = dpp_etm_qmu_init_set_pd16k_2(dev_id, depth); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_etm_qmu_init_set"); + + return DPP_OK; +} + + +DPP_STATUS dpp_qmu_init_info(ZXIC_UINT32 dev_id) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 ddr_num = 0; + ZXIC_UINT32 k = 0; + ZXIC_UINT32 i = 0; + ZXIC_UINT32 j = 0; + DPP_ETM_QMU_QCFG_QLIST_BDEP_T qlist_bdep = {0}; + DPP_ETM_QMU_QCFG_QLIST_BHEAD_T qlist_bhead = {0}; + DPP_ETM_QMU_QCFG_QLIST_BTAIL_T qlist_btail = {0}; + DPP_ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFG_T active_to_bank_cfg = {0}; + DPP_ETM_QMU_QCFG_QLIST_GRP0_BANK_T qlist_grp0_bank = {0}; + DPP_ETM_QMU_QCFG_QLIST_GRP1_BANK_T qlist_grp1_bank = {0}; + DPP_ETM_QMU_QCFG_QLIST_GRP2_BANK_T qlist_grp2_bank = {0}; + DPP_ETM_QMU_QCFG_QLIST_GRP3_BANK_T qlist_grp3_bank = {0}; + DPP_ETM_QMU_QCFG_QLIST_GRP4_BANK_T qlist_grp4_bank = {0}; + DPP_ETM_QMU_QCFG_QLIST_GRP5_BANK_T qlist_grp5_bank = {0}; + DPP_ETM_QMU_QCFG_QLIST_GRP6_BANK_T qlist_grp6_bank = {0}; + DPP_ETM_QMU_QCFG_QLIST_GRP7_BANK_T qlist_grp7_bank = {0}; + DPP_ETM_QMU_QCFG_QLIST_GRP_T qcfg_qlist_grp = {0}; + dpp_tm_cfgmt_ddr_attach_get(0, &ddr_num); + ZXIC_COMM_PRINT("dpp_tm_cfgmt_ddr_attach_get ddr_num:%d\n",ddr_num); + + /* random映射ram */ + for (j = 0; j < 4; j++) + { + for (i = 0, k = 0; i < 4; i++) + { + k = j * 4 + i; + + active_to_bank_cfg.cfgmt_active_to_bank_cfg = 0; + + rc = dpp_reg_read(dev_id, + ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFGr, + 0, + k, + &active_to_bank_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + ZXIC_COMM_PRINT("cfgmt_active_to_bank_cfg: cfgmt_active_to_bank_cfg-%d value:%d\n",k,active_to_bank_cfg.cfgmt_active_to_bank_cfg); + } + } + + /* 首尾深度指针配置: */ + for (j = 0, k = 0; j < 8; j++) + { + k = j * 8; + rc = dpp_reg_read(dev_id, + ETM_QMU_QCFG_QLIST_BHEADr, + 0, + k, + &qlist_bhead); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + ZXIC_COMM_PRINT("qlist_bhead: qlist_bhead-%d bank_vld:%d qcfg_qlist_bhead:%d\n",k,qlist_bhead.bank_vld,qlist_bhead.qcfg_qlist_bhead); + + rc = dpp_reg_read(dev_id, + ETM_QMU_QCFG_QLIST_BTAILr, + 0, + k, + &qlist_btail); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + ZXIC_COMM_PRINT("qlist_btail: qlist_btail-%d qcfg_qlist_btail:%d\n",k,qlist_btail.qcfg_qlist_btail); + + + } + for (j = 0; j < 64; j++) + { + + rc = dpp_reg_read(dev_id, + ETM_QMU_QCFG_QLIST_BDEPr, + 0, + j, + &qlist_bdep); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + ZXIC_COMM_PRINT("qlist_bdep: qlist_bdep-%d qcfg_qlist_bdep:%d\n",j,qlist_bdep.qcfg_qlist_bdep); + } + + /* 随机表配置，决定每组bank的轮询顺序 */ + for (j = 0; j < 16; j++) + { + for (i = 0, k = 0; i < 4; i++) + { + k = j * 4 + i; + + rc = dpp_reg_read(dev_id, + ETM_QMU_QCFG_QLIST_GRP0_BANKr, + 0, + k, + &qlist_grp0_bank); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + ZXIC_COMM_PRINT("qlist_grp0_bank: qlist_grp0_bank-%d qcfg_qlist_grp0_bank_wr:%d\n",k,qlist_grp0_bank.qcfg_qlist_grp0_bank_wr); + } + } + + for (j = 0; j < 16; j++) + { + for (i = 0, k = 0; i < 4; i++) + { + k = j * 4 + i; + + rc = dpp_reg_read(dev_id, + ETM_QMU_QCFG_QLIST_GRP1_BANKr, + 0, + k, + &qlist_grp1_bank); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + ZXIC_COMM_PRINT("qlist_grp1_bank: qlist_grp1_bank-%d qcfg_qlist_grp1_bank_wr:%d\n",k,qlist_grp1_bank.qcfg_qlist_grp1_bank_wr); + + } + } + + for (j = 0; j < 16; j++) + { + for (i = 0, k = 0; i < 4; i++) + { + k = j * 4 + i; + + rc = dpp_reg_read(dev_id, + ETM_QMU_QCFG_QLIST_GRP2_BANKr, + 0, + k, + &qlist_grp2_bank); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + ZXIC_COMM_PRINT("qlist_grp2_bank: qlist_grp2_bank-%d qcfg_qlist_grp2_bank_wr:%d\n",k,qlist_grp2_bank.qcfg_qlist_grp2_bank_wr); + + } + } + + for (j = 0; j < 16; j++) + { + for (i = 0, k = 0; i < 4; i++) + { + k = j * 4 + i; + + rc = dpp_reg_read(dev_id, + ETM_QMU_QCFG_QLIST_GRP3_BANKr, + 0, + k, + &qlist_grp3_bank); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + ZXIC_COMM_PRINT("qlist_grp3_bank: qlist_grp3_bank-%d qcfg_qlist_grp3_bank_wr:%d\n",k,qlist_grp3_bank.qcfg_qlist_grp3_bank_wr); + + } + } + + for (j = 0; j < 16; j++) + { + for (i = 0, k = 0; i < 4; i++) + { + k = j * 4 + i; + + rc = dpp_reg_read(dev_id, + ETM_QMU_QCFG_QLIST_GRP4_BANKr, + 0, + k, + &qlist_grp4_bank); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + ZXIC_COMM_PRINT("qlist_grp4_bank: qlist_grp4_bank-%d qcfg_qlist_grp4_bank_wr:%d\n",k,qlist_grp4_bank.qcfg_qlist_grp4_bank_wr); + + } + } + + for (j = 0; j < 16; j++) + { + for (i = 0, k = 0; i < 4; i++) + { + k = j * 4 + i; + + rc = dpp_reg_read(dev_id, + ETM_QMU_QCFG_QLIST_GRP5_BANKr, + 0, + k, + &qlist_grp5_bank); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + ZXIC_COMM_PRINT("qlist_grp5_bank: qlist_grp5_bank-%d qcfg_qlist_grp5_bank_wr:%d\n",k,qlist_grp5_bank.qcfg_qlist_grp5_bank_wr); + + } + } + + for (j = 0; j < 16; j++) + { + for (i = 0, k = 0; i < 4; i++) + { + k = j * 4 + i; + + rc = dpp_reg_read(dev_id, + ETM_QMU_QCFG_QLIST_GRP6_BANKr, + 0, + k, + &qlist_grp6_bank); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + ZXIC_COMM_PRINT("qlist_grp6_bank: qlist_grp6_bank-%d qcfg_qlist_grp6_bank_wr:%d\n",k,qlist_grp6_bank.qcfg_qlist_grp6_bank_wr); + + } + } + + for (j = 0; j < 16; j++) + { + for (i = 0, k = 0; i < 4; i++) + { + k = j * 4 + i; + + rc = dpp_reg_read(dev_id, + ETM_QMU_QCFG_QLIST_GRP7_BANKr, + 0, + k, + &qlist_grp7_bank); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + ZXIC_COMM_PRINT("qlist_grp7_bank: qlist_grp7_bank-%d qcfg_qlist_grp7_bank_wr:%d\n",k,qlist_grp7_bank.qcfg_qlist_grp7_bank_wr); + + } + } + + for (j = 0; j < 8; j++) + { + for (i = 0, k = 0; i < 8; i++) + { + k = j * 8 + i; + + rc = dpp_reg_read(dev_id, + ETM_QMU_QCFG_QLIST_GRPr, + 0, + k, + &qcfg_qlist_grp); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + ZXIC_COMM_PRINT("qcfg_qlist_grp: qcfg_qlist_grp-%d qcfg_qlist_grp_wr:%d\n",k,qcfg_qlist_grp.qcfg_qlist_grp_wr); + } + } + + + return DPP_OK; +} +/***********************************************************/ +/** QMU初始化配置场景二：ddr3模式，8组*8bank +* depth=512,代表32k +* @param dev_id 设备编号 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author sun @date 2023/04/12 +************************************************************/ +DPP_STATUS dpp_etm_qmu_init_set_chuk32(ZXIC_UINT32 dev_id, ZXIC_UINT32 depth) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 k = 0; + ZXIC_UINT32 i = 0; + ZXIC_UINT32 j = 0; + ZXIC_UINT32 qlist_grp0_bank_data[8] = {0, 0, 0, 0, 0, 0, 0, 0}; + ZXIC_UINT32 qlist_grp_bank_data[8] = {0, 1, 2, 3, 4, 5, 6, 7}; + ZXIC_UINT32 ddr_num = 0xff; + + DPP_ETM_QMU_QCFG_QLIST_BDEP_T qlist_bdep = {0}; + DPP_ETM_QMU_QCFG_QLIST_BHEAD_T qlist_bhead = {0}; + DPP_ETM_QMU_QCFG_QLIST_BTAIL_T qlist_btail = {0}; + DPP_ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFG_T active_to_bank_cfg = {0}; + DPP_ETM_QMU_QCFG_QLIST_GRP0_BANK_T qlist_grp0_bank = {0}; + DPP_ETM_QMU_QCFG_QLIST_GRP1_BANK_T qlist_grp1_bank = {0}; + DPP_ETM_QMU_QCFG_QLIST_GRP2_BANK_T qlist_grp2_bank = {0}; + DPP_ETM_QMU_QCFG_QLIST_GRP3_BANK_T qlist_grp3_bank = {0}; + DPP_ETM_QMU_QCFG_QLIST_GRP4_BANK_T qlist_grp4_bank = {0}; + DPP_ETM_QMU_QCFG_QLIST_GRP5_BANK_T qlist_grp5_bank = {0}; + DPP_ETM_QMU_QCFG_QLIST_GRP6_BANK_T qlist_grp6_bank = {0}; + DPP_ETM_QMU_QCFG_QLIST_GRP7_BANK_T qlist_grp7_bank = {0}; + DPP_ETM_QMU_QCFG_QLIST_GRP_T qcfg_qlist_grp = {0}; + + + + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "++++++dpp_etm_qmu_init_set starting++++++\n"); + + /* cfgmt配置8组ddr */ + rc = dpp_tm_cfgmt_ddr_attach_set(dev_id, ddr_num); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_ddr_attach_set"); + + /* 首尾深度指针配置: */ + for (j = 0, k = 0; j < 8; j++) + { + + k = j * 8; + qlist_bhead.bank_vld = 1; + qlist_bhead.qcfg_qlist_bhead = j * depth; + qlist_btail.qcfg_qlist_btail = 511 + j * depth; + + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BHEADr, + 0, + k, + &qlist_bhead); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BTAILr, + 0, + k, + &qlist_btail); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + } + for (j = 0; j < 64; j++) + { + qlist_bdep.qcfg_qlist_bdep = depth; + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BDEPr, + 0, + j, + &qlist_bdep); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + /* 随机表配置，决定每组bank的轮询顺序 */ + for (j = 0; j < 16; j++) + { + for (i = 0, k = 0; i < 4; i++) + { + k = j * 4 + i; + + qlist_grp0_bank.qcfg_qlist_grp0_bank_wr = qlist_grp0_bank_data[0]; + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_GRP0_BANKr, + 0, + k, + &qlist_grp0_bank); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + } + } + + for (j = 0; j < 16; j++) + { + for (i = 0, k = 0; i < 4; i++) + { + k = j * 4 + i; + + qlist_grp1_bank.qcfg_qlist_grp1_bank_wr = qlist_grp0_bank_data[1];; + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_GRP1_BANKr, + 0, + k, + &qlist_grp1_bank); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + } + } + + for (j = 0; j < 16; j++) + { + for (i = 0, k = 0; i < 4; i++) + { + k = j * 4 + i; + + qlist_grp2_bank.qcfg_qlist_grp2_bank_wr = qlist_grp0_bank_data[2];; + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_GRP2_BANKr, + 0, + k, + &qlist_grp2_bank); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + } + } + + for (j = 0; j < 16; j++) + { + for (i = 0, k = 0; i < 4; i++) + { + k = j * 4 + i; + + qlist_grp3_bank.qcfg_qlist_grp3_bank_wr = qlist_grp0_bank_data[3];; + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_GRP3_BANKr, + 0, + k, + &qlist_grp3_bank); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + } + } + + for (j = 0; j < 16; j++) + { + for (i = 0, k = 0; i < 4; i++) + { + k = j * 4 + i; + + qlist_grp4_bank.qcfg_qlist_grp4_bank_wr = qlist_grp0_bank_data[4];; + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_GRP4_BANKr, + 0, + k, + &qlist_grp4_bank); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + } + } + + for (j = 0; j < 16; j++) + { + for (i = 0, k = 0; i < 4; i++) + { + k = j * 4 + i; + + qlist_grp5_bank.qcfg_qlist_grp5_bank_wr = qlist_grp0_bank_data[5];; + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_GRP5_BANKr, + 0, + k, + &qlist_grp5_bank); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + } + } + + for (j = 0; j < 16; j++) + { + for (i = 0, k = 0; i < 4; i++) + { + k = j * 4 + i; + + qlist_grp6_bank.qcfg_qlist_grp6_bank_wr = qlist_grp0_bank_data[6];; + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_GRP6_BANKr, + 0, + k, + &qlist_grp6_bank); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + } + } + + for (j = 0; j < 16; j++) + { + for (i = 0, k = 0; i < 4; i++) + { + k = j * 4 + i; + + qlist_grp7_bank.qcfg_qlist_grp7_bank_wr = qlist_grp0_bank_data[7];; + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_GRP7_BANKr, + 0, + k, + &qlist_grp7_bank); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + } + } + + for (j = 0; j < 8; j++) + { + for (i = 0, k = 0; i < 8; i++) + { + k = j * 8 + i; + qcfg_qlist_grp.qcfg_qlist_grp_wr = qlist_grp_bank_data[i]; + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_GRPr, + 0, + k, + &qcfg_qlist_grp); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + } + + /* random映射ram */ + for (j = 0; j < 4; j++) + { + for (i = 0, k = 0; i < 4; i++) + { + + k = j * 4 + i; + + active_to_bank_cfg.cfgmt_active_to_bank_cfg = 0; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFGr, + 0, + k, + &active_to_bank_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + } + zxic_comm_sleep(5); + rc = dpp_tm_qmu_cfg_done_set(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_cfg_done_set"); + + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "++++++dpp_etm_qmu_init_set end++++++\n"); + + return DPP_OK; +} + +/***********************************************************/ +/** QMU初始化配置场景：ddr3模式，8组ddr*8bank +* @param dev_id 设备编号 +* @param depth bank depth +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author sun @date 2023/04/12 +************************************************************/ +DPP_STATUS dpp_tm_qmu_init_set_chuk32(ZXIC_UINT32 dev_id, ZXIC_UINT32 depth) +{ + DPP_STATUS rc = DPP_OK; + + rc = dpp_etm_qmu_init_set_chuk32(dev_id, depth); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_etm_qmu_init_set"); + + return DPP_OK; +} + +/***********************************************************/ +/** QMU初始化配置场景二：TM独享8组ddr:FTM为0-3组ddr的0~3bank，ETM为4-7组ddr 0~3bank +* @param dev_id 设备编号 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cuiy @date 2016/11/17 +************************************************************/ +DPP_STATUS dpp_etm_qmu_init_set_3(ZXIC_UINT32 dev_id) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 k = 0; + ZXIC_UINT32 i = 0; + ZXIC_UINT32 j = 0; + ZXIC_UINT32 depth = 2048; + ZXIC_UINT32 qlist_grp0_bank_data[8] = {0, 1, 2, 3, 4, 5, 6, 7}; + + + DPP_ETM_QMU_QCFG_QLIST_BDEP_T qlist_bdep = {0}; + DPP_ETM_QMU_QCFG_QLIST_BHEAD_T qlist_bhead = {0}; + DPP_ETM_QMU_QCFG_QLIST_BTAIL_T qlist_btail = {0}; + DPP_ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFG_T active_to_bank_cfg = {0}; + DPP_ETM_QMU_CFGMT_DDR_IN_MMU_CFG_T ddr_in_mmu_cfg = {0}; + DPP_ETM_QMU_CFGMT_DDR_IN_QMU_CFG_T ddr_in_qmu_cfg = {0}; + DPP_ETM_QMU_CFGMT_BANK_TO_MMU_CFG_T bank_to_mmu_cfg = {0}; + DPP_ETM_QMU_CFGMT_BANK_TO_QMU_CFG_T bank_to_qmu_cfg = {0}; + DPP_ETM_QMU_QCFG_QLIST_GRP0_BANK_T qlist_grp0_bank = {0}; + DPP_ETM_QMU_QCFG_QLIST_GRP_T qcfg_qlist_grp = {0}; + + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "++++++dpp_etm_qmu_init_set starting++++++\n"); + + + /* ddr组从qmu到mmu映射,0~3映射成4~7 */ + for (i = 0; i < 4; i++) + { + ddr_in_mmu_cfg.cfgmt_ddr_in_mmu_cfg = i + 4; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_DDR_IN_MMU_CFGr, + 0, + i, + &ddr_in_mmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + /* ddr组从mmu到qmu映射,4~7映射成0~3 */ + for (i = 4; i < 8; i++) + { + ddr_in_qmu_cfg.cfgmt_ddr_in_qmu_cfg = i - 4; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_DDR_IN_QMU_CFGr, + 0, + i, + &ddr_in_qmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + /* bank号从qmu到mmu映射，组0~3的bank0-3映射成bank0-3 */ + for (j = 0; j < 4; j++) + { + for (i = 0; i < 4; i++) + { + k = j * 8 + i; + + bank_to_mmu_cfg.cfgmt_bank_in_mmu_cfg = i; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_BANK_TO_MMU_CFGr, + 0, + k, + &bank_to_mmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + } + + + /* bank号从mmu到qmu映射，组4~7的bank0-7映射成bank0-7 */ + for (j = 4; j < 8; j++) + { + for (i = 0; i < 4; i++) + { + k = j * 8 + i; + + bank_to_qmu_cfg.cfgmt_bank_in_qmu_cfg = i; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_BANK_TO_QMU_CFGr, + 0, + k, + &bank_to_qmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + } + + /* random映射ram:配置一个chunk中，bank的轮询顺序 */ + for (i = 0; i < 16; i++) + { + active_to_bank_cfg.cfgmt_active_to_bank_cfg = i % 4; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFGr, + 0, + i, + &active_to_bank_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + /* 首尾深度指针配置:j为8组循环 */ + for (j = 0; j < 4; j++) + { + for (i = 0; i < 4; i++) + { + k = j * 8 + i; + + qlist_bhead.bank_vld = 1; + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, (j * 4 + i), depth); + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, (j * 4 + i + 1), depth); + qlist_bhead.qcfg_qlist_bhead = (j * 4 + i) * depth; + qlist_btail.qcfg_qlist_btail = ((j * 4 + i + 1) * depth - 1); + qlist_bdep.qcfg_qlist_bdep = depth; + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BHEADr, + 0, + k, + &qlist_bhead); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BTAILr, + 0, + k, + &qlist_btail); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BDEPr, + 0, + k, + &qlist_bdep); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + } + + ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(ETM_QMU_QCFG_QLIST_GRP0_BANKr, 8); + /* 随机表配置，决定ddr内bank的轮询顺序:使用几组ddr需要配置几组 */ + for (j = 0; j < 8; j++) + { + for (i = 0; i < 64; i++) + { + + qlist_grp0_bank.qcfg_qlist_grp0_bank_wr = qlist_grp0_bank_data[i % 4]; + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_GRP0_BANKr + j, + 0, + i, + &qlist_grp0_bank); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + } + } + + for (j = 0; j < 64; j++) + { + qcfg_qlist_grp.qcfg_qlist_grp_wr = j % 4; + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_GRPr, + 0, + j, + &qcfg_qlist_grp); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + rc = dpp_tm_qmu_cfg_done_set(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_cfg_done_set"); + + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "++++++dpp_etm_qmu_init_set end++++++\n"); + + return DPP_OK; +} + + + + +/***********************************************************/ +/** QMU/MMU初始化配置场景三：TM独享8组ddr:FTM为0-3组ddr的0~3bank，ETM为4-7组ddr 0~3bank +* MMU开启rotatjon +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cuiy @date 2016/11/17 +************************************************************/ +DPP_STATUS dpp_tm_qmu_init_set_3(ZXIC_UINT32 dev_id) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_RANDOM_BYPASS_EN_T etm_bypass = {0}; +// DPP_FTM_QMU_RANDOM_BYPASS_EN_T ftm_bypass = {0}; + + /* etm mmu基址配置:ddr4-7组，bank号0-3，bank深度2048 */ + //rc = dpp_mmu_bank_base_addr_set(dev_id, 0xf0, 0xf, 2048); + //ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_mmu_bank_base_addr_set"); + + rc = dpp_etm_qmu_init_set_3(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_etm_qmu_init_set_1"); + + /* 关闭etm映射配置 */ + etm_bypass.random_bypass_en = 0; + rc = dpp_reg_write(dev_id, + ETM_QMU_RANDOM_BYPASS_ENr, + 0, + 0, + &etm_bypass); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + + return DPP_OK; +} + + +/***********************************************************/ +/**场景4：TM共享2组ddr:FTM为2、4组ddr的01bank，ETM为2、4组ddr 23bank +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xuhb @date 2020/06/06 +************************************************************/ +DPP_STATUS dpp_etm_qmu_init_set_4(ZXIC_UINT32 dev_id) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 k = 0; + ZXIC_UINT32 i = 0; + ZXIC_UINT32 j = 0; + ZXIC_UINT32 depth = 8 * 1024; + ZXIC_UINT32 ddr_to_mmu_cfg_map[2] = {2, 4}; + ZXIC_UINT32 bank_to_mmu_cfg_map[2] = {2, 3}; + ZXIC_UINT32 qlist_grp0_bank_data[2] = {0, 1}; + + + DPP_ETM_QMU_QCFG_QLIST_BDEP_T qlist_bdep = {0}; + DPP_ETM_QMU_QCFG_QLIST_BHEAD_T qlist_bhead = {0}; + DPP_ETM_QMU_QCFG_QLIST_BTAIL_T qlist_btail = {0}; + + DPP_ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFG_T active_to_bank_cfg = {0}; + DPP_ETM_QMU_CFGMT_DDR_IN_MMU_CFG_T ddr_in_mmu_cfg = {0}; + DPP_ETM_QMU_CFGMT_DDR_IN_QMU_CFG_T ddr_in_qmu_cfg = {0}; + DPP_ETM_QMU_CFGMT_BANK_TO_MMU_CFG_T bank_to_mmu_cfg = {0}; + DPP_ETM_QMU_CFGMT_BANK_TO_QMU_CFG_T bank_to_qmu_cfg = {0}; + DPP_ETM_QMU_QCFG_QLIST_GRP0_BANK_T qlist_grp0_bank = {0}; + DPP_ETM_QMU_QCFG_QLIST_GRP_T qcfg_qlist_grp = {0}; + + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "========dpp_etm_qmu_init_set_4 start========n"); + + + /* ddr组从qmu到mmu映射,0~1映射成2 4 */ + for (i = 0; i < 2; i++) + { + ddr_in_mmu_cfg.cfgmt_ddr_in_mmu_cfg = ddr_to_mmu_cfg_map[i]; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_DDR_IN_MMU_CFGr, + 0, + i, + &ddr_in_mmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + /* ddr组从mmu到qmu映射,2 4映射成0~1 */ + for (i = 0; i < 2; i++) + { + ddr_in_qmu_cfg.cfgmt_ddr_in_qmu_cfg = i; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_DDR_IN_QMU_CFGr, + 0, + ddr_to_mmu_cfg_map[i], + &ddr_in_qmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + + /* bank号从qmu到mmu映射，每组的bank0~1映射成bank2、3 */ + for (j = 0; j < 2; j++) + { + for (i = 0; i < 2; i++) + { + k = j * 8 + i; + + bank_to_mmu_cfg.cfgmt_bank_in_mmu_cfg = bank_to_mmu_cfg_map[i]; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_BANK_TO_MMU_CFGr, + 0, + k, + &bank_to_mmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + } + + + /* bank号从mmu到qmu映射，每组的bank2、3映射成bank0、1 */ + for (j = 0; j < 2; j++) + { + for (i = 0; i < 2; i++) + { + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, ddr_to_mmu_cfg_map[j] , 8); + ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(dev_id, ddr_to_mmu_cfg_map[j] * 8 , bank_to_mmu_cfg_map[i]); + k = ddr_to_mmu_cfg_map[j] * 8 + bank_to_mmu_cfg_map[i]; + bank_to_qmu_cfg.cfgmt_bank_in_qmu_cfg = i; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_BANK_TO_QMU_CFGr, + 0, + k, + &bank_to_qmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + } + + /* random映射ram:配置一个chunk中，bank的轮询顺序 */ + for (i = 0; i < 16; i++) + { + + + active_to_bank_cfg.cfgmt_active_to_bank_cfg = i % 2; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFGr, + 0, + i, + &active_to_bank_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + } + + + /* 首尾深度指针配置 */ + for (j = 0; j < 2; j++) + { + for (i = 0; i < 2; i++) + { + k = j * 8 + i; + + qlist_bhead.bank_vld = 1; + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, (j * 2 + i), depth); + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, (j * 2 + i + 1), depth); + qlist_bhead.qcfg_qlist_bhead = (j * 2 + i) * depth; + qlist_btail.qcfg_qlist_btail = ((j * 2 + i + 1) * depth - 1); + qlist_bdep.qcfg_qlist_bdep = depth; + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BHEADr, + 0, + k, + &qlist_bhead); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BTAILr, + 0, + k, + &qlist_btail); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BDEPr, + 0, + k, + &qlist_bdep); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + } + + for (i = 0; i < 64; i++) + { + qlist_bdep.qcfg_qlist_bdep = depth; + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BDEPr, + 0, + i, + &qlist_bdep); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(ETM_QMU_QCFG_QLIST_GRP0_BANKr, 8); + /* 随机表配置，决定每组bank的轮询顺序 */ + for (j = 0; j < 8; j++) + { + for (i = 0; i < 64; i++) + { + qlist_grp0_bank.qcfg_qlist_grp0_bank_wr = qlist_grp0_bank_data[i % 2]; + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_GRP0_BANKr + j, + 0, + i, + &qlist_grp0_bank); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + } + + for (j = 0; j < 64; j++) + { + qcfg_qlist_grp.qcfg_qlist_grp_wr = j % 2; + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_GRPr, + 0, + j, + &qcfg_qlist_grp); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + rc = dpp_tm_qmu_cfg_done_set(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_cfg_done_set"); + + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "========dpp_etm_qmu_init_set_4 END=======\n"); + + return DPP_OK; +} + + + + +/***********************************************************/ +/**场景4：TM共享2组ddr:FTM为2、4组ddr的01bank，ETM为2、4组ddr 23bank +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xuhb @date 2020/06/06 +************************************************************/ +DPP_STATUS dpp_tm_qmu_init_set_4(ZXIC_UINT32 dev_id) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_RANDOM_BYPASS_EN_T etm_bypass = {0}; + //DPP_FTM_QMU_RANDOM_BYPASS_EN_T ftm_bypass = {0}; + + /* etm mmu基址配置:ddr2、4组，bank号23，bank深度8*1024 */ + //rc = dpp_mmu_bank_base_addr_set(dev_id, 0x14, 0xc, 8 * 1024); + //ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_mmu_bank_base_addr_set"); + + rc = dpp_etm_qmu_init_set_4(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_etm_qmu_init_set_4"); + + /* 关闭etm映射配置 */ + etm_bypass.random_bypass_en = 0; + rc = dpp_reg_write(dev_id, + ETM_QMU_RANDOM_BYPASS_ENr, + 0, + 0, + &etm_bypass); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + return DPP_OK; +} + +/***********************************************************/ +/** 场景5：TM共享4组ddr:FTM为1234组ddr的01bank，ETM为1234组ddr 23bank +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xuhb @date 2020/06/06 +************************************************************/ +DPP_STATUS dpp_etm_qmu_init_set_5(ZXIC_UINT32 dev_id) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 k = 0; + ZXIC_UINT32 i = 0; + ZXIC_UINT32 j = 0; + ZXIC_UINT32 depth = 4*1024; + ZXIC_UINT32 bank_to_mmu_cfg_map[2] = {2, 3}; + ZXIC_UINT32 qlist_grp0_bank_data[2] = {0, 1}; + ZXIC_UINT32 ddr_no[4] = {1, 2, 3, 4}; + + + DPP_ETM_QMU_QCFG_QLIST_BDEP_T qlist_bdep = {0}; + DPP_ETM_QMU_QCFG_QLIST_BHEAD_T qlist_bhead = {0}; + DPP_ETM_QMU_QCFG_QLIST_BTAIL_T qlist_btail = {0}; + + DPP_ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFG_T active_to_bank_cfg = {0}; + DPP_ETM_QMU_CFGMT_DDR_IN_MMU_CFG_T ddr_in_mmu_cfg = {0}; + DPP_ETM_QMU_CFGMT_DDR_IN_QMU_CFG_T ddr_in_qmu_cfg = {0}; + DPP_ETM_QMU_CFGMT_BANK_TO_MMU_CFG_T bank_to_mmu_cfg = {0}; + DPP_ETM_QMU_CFGMT_BANK_TO_QMU_CFG_T bank_to_qmu_cfg = {0}; + DPP_ETM_QMU_QCFG_QLIST_GRP0_BANK_T qlist_grp0_bank = {0}; + DPP_ETM_QMU_QCFG_QLIST_GRP_T qcfg_qlist_grp = {0}; + + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "========dpp_etm_qmu_init_set_5 start========n"); + + + /* ddr组从qmu到mmu映射,0~3映射成1234 */ + for (i = 0; i < 4; i++) + { + ddr_in_mmu_cfg.cfgmt_ddr_in_mmu_cfg = ddr_no[i]; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_DDR_IN_MMU_CFGr, + 0, + i, + &ddr_in_mmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + /* ddr组从mmu到qmu映射,1234映射成0~3 */ + for (i = 0; i < 4; i++) + { + ddr_in_qmu_cfg.cfgmt_ddr_in_qmu_cfg = i; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_DDR_IN_QMU_CFGr, + 0, + ddr_no[i], + &ddr_in_qmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + + /* bank号从qmu到mmu映射，每组的bank0~1映射成bank2、3 */ + for (j = 0; j < 4; j++) + { + for (i = 0; i < 2; i++) + { + k = j * 8 + i; + + bank_to_mmu_cfg.cfgmt_bank_in_mmu_cfg = bank_to_mmu_cfg_map[i]; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_BANK_TO_MMU_CFGr, + 0, + k, + &bank_to_mmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + } + + + /* bank号从mmu到qmu映射，每组的bank2、3映射成bank0、1 */ + for (j = 0; j < 4; j++) + { + for (i = 0; i < 2; i++) + { + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, ddr_no[j] , 8); + ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(dev_id, ddr_no[j] * 8 , bank_to_mmu_cfg_map[i]); + k = ddr_no[j] * 8 + bank_to_mmu_cfg_map[i]; + bank_to_qmu_cfg.cfgmt_bank_in_qmu_cfg = i; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_BANK_TO_QMU_CFGr, + 0, + k, + &bank_to_qmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + } + + /* random映射ram:配置一个chunk中，bank的轮询顺序 */ + for (i = 0; i < 16; i++) + { + + + active_to_bank_cfg.cfgmt_active_to_bank_cfg = i % 2; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFGr, + 0, + i, + &active_to_bank_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + } + + + /* 首尾深度指针配置 */ + for (j = 0; j < 4; j++) + { + for (i = 0; i < 2; i++) + { + k = j * 8 + i; + + qlist_bhead.bank_vld = 1; + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, (j * 2 + i), depth); + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, (j * 2 + i + 1), depth); + qlist_bhead.qcfg_qlist_bhead = (j * 2 + i) * depth; + qlist_btail.qcfg_qlist_btail = ((j * 2 + i + 1) * depth - 1); + qlist_bdep.qcfg_qlist_bdep = depth; + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BHEADr, + 0, + k, + &qlist_bhead); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BTAILr, + 0, + k, + &qlist_btail); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BDEPr, + 0, + k, + &qlist_bdep); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + } + + for (i = 0; i < 64; i++) + { + qlist_bdep.qcfg_qlist_bdep = depth; + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BDEPr, + 0, + i, + &qlist_bdep); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(ETM_QMU_QCFG_QLIST_GRP0_BANKr, 8); + /* 随机表配置，决定每组bank的轮询顺序 */ + for (j = 0; j < 8; j++) + { + for (i = 0; i < 64; i++) + { + qlist_grp0_bank.qcfg_qlist_grp0_bank_wr = qlist_grp0_bank_data[i % 2]; + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_GRP0_BANKr + j, + 0, + i, + &qlist_grp0_bank); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + } + + for (j = 0; j < 64; j++) + { + qcfg_qlist_grp.qcfg_qlist_grp_wr = j % 4; + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_GRPr, + 0, + j, + &qcfg_qlist_grp); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + rc = dpp_tm_qmu_cfg_done_set(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_cfg_done_set"); + + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "========dpp_etm_qmu_init_set_5 END=======\n"); + + return DPP_OK; +} + + +/***********************************************************/ +/** 场景5：TM共享4组ddr:FTM为1234组ddr的01bank，ETM为1234组ddr 23bank +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xuhb @date 2020/06/06 +************************************************************/ +DPP_STATUS dpp_tm_qmu_init_set_5(ZXIC_UINT32 dev_id) +{ + DPP_STATUS rc = DPP_OK; + + /* etm mmu基址配置:ddr1234组，bank号23，bank深度4*1024 */ + //rc = dpp_mmu_bank_base_addr_set(dev_id, 0x1e, 0xc, 4*1024); + //ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_mmu_bank_base_addr_set"); + + rc = dpp_etm_qmu_init_set_5(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_etm_qmu_init_set_5"); + + return DPP_OK; +} + + +/***********************************************************/ +/** QMU初始化配置场景6：4组*2bank，MMU实际分配ftm:4,6,7,9组(01bank); etm:4,6,7,9组(23bank) +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xuhb @date 2020/05/13 +************************************************************/ +DPP_STATUS dpp_etm_qmu_init_set_6(ZXIC_UINT32 dev_id) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 k = 0; + ZXIC_UINT32 i = 0; + ZXIC_UINT32 j = 0; + ZXIC_UINT32 depth = 4*1024; + ZXIC_UINT32 bank_to_mmu_cfg_map[4] = {2, 3}; + ZXIC_UINT32 qlist_grp0_bank_data[4] = {0, 1}; + ZXIC_UINT32 ddr_no[4] = {4, 6, 7, 9}; + + + DPP_ETM_QMU_QCFG_QLIST_BDEP_T qlist_bdep = {0}; + DPP_ETM_QMU_QCFG_QLIST_BHEAD_T qlist_bhead = {0}; + DPP_ETM_QMU_QCFG_QLIST_BTAIL_T qlist_btail = {0}; + + DPP_ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFG_T active_to_bank_cfg = {0}; + DPP_ETM_QMU_CFGMT_DDR_IN_MMU_CFG_T ddr_in_mmu_cfg = {0}; + DPP_ETM_QMU_CFGMT_DDR_IN_QMU_CFG_T ddr_in_qmu_cfg = {0}; + DPP_ETM_QMU_CFGMT_BANK_TO_MMU_CFG_T bank_to_mmu_cfg = {0}; + DPP_ETM_QMU_CFGMT_BANK_TO_QMU_CFG_T bank_to_qmu_cfg = {0}; + DPP_ETM_QMU_QCFG_QLIST_GRP0_BANK_T qlist_grp0_bank = {0}; + DPP_ETM_QMU_QCFG_QLIST_GRP_T qcfg_qlist_grp = {0}; + + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "========dpp_etm_qmu_init_set_1 start========n"); + + + /* ddr组从qmu到mmu映射,0~3映射成4679 */ + for (i = 0; i < 4; i++) + { + ddr_in_mmu_cfg.cfgmt_ddr_in_mmu_cfg = ddr_no[i]; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_DDR_IN_MMU_CFGr, + 0, + i, + &ddr_in_mmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + /* ddr组从mmu到qmu映射,4679映射成0~3 */ + for (i = 0; i < 4; i++) + { + ddr_in_qmu_cfg.cfgmt_ddr_in_qmu_cfg = i; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_DDR_IN_QMU_CFGr, + 0, + ddr_no[i], + &ddr_in_qmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + + /* bank号从qmu到mmu映射，每组的bank0~1映射成bank2、3 */ + for (j = 0; j < 4; j++) + { + for (i = 0; i < 2; i++) + { + k = j * 8 + i; + + bank_to_mmu_cfg.cfgmt_bank_in_mmu_cfg = bank_to_mmu_cfg_map[i]; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_BANK_TO_MMU_CFGr, + 0, + k, + &bank_to_mmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + } + + + /* bank号从mmu到qmu映射，每组的bank2、3映射成bank0、1 */ + for (j = 0; j < 4; j++) + { + for (i = 0; i < 2; i++) + { + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, ddr_no[j] , 8); + ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(dev_id, ddr_no[j] * 8 , bank_to_mmu_cfg_map[i]); + k = ddr_no[j] * 8 + bank_to_mmu_cfg_map[i]; + bank_to_qmu_cfg.cfgmt_bank_in_qmu_cfg = i; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_BANK_TO_QMU_CFGr, + 0, + k, + &bank_to_qmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + } + + /* random映射ram:配置一个chunk中，bank的轮询顺序 */ + for (i = 0; i < 16; i++) + { + + + active_to_bank_cfg.cfgmt_active_to_bank_cfg = i % 2; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFGr, + 0, + i, + &active_to_bank_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + } + + + /* 首尾深度指针配置 */ + for (j = 0; j < 4; j++) + { + for (i = 0; i < 2; i++) + { + k = j * 8 + i; + + qlist_bhead.bank_vld = 1; + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, (j * 2 + i), depth); + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, (j * 2 + i + 1), depth); + qlist_bhead.qcfg_qlist_bhead = (j * 2 + i) * depth; + qlist_btail.qcfg_qlist_btail = ((j * 2 + i + 1) * depth - 1); + qlist_bdep.qcfg_qlist_bdep = depth; + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BHEADr, + 0, + k, + &qlist_bhead); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BTAILr, + 0, + k, + &qlist_btail); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BDEPr, + 0, + k, + &qlist_bdep); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + } + + for (i = 0; i < 64; i++) + { + qlist_bdep.qcfg_qlist_bdep = depth; + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BDEPr, + 0, + i, + &qlist_bdep); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(ETM_QMU_QCFG_QLIST_GRP0_BANKr, 8); + /* 随机表配置，决定每组bank的轮询顺序 */ + for (j = 0; j < 8; j++) + { + for (i = 0; i < 64; i++) + { + qlist_grp0_bank.qcfg_qlist_grp0_bank_wr = qlist_grp0_bank_data[i % 2]; + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_GRP0_BANKr + j, + 0, + i, + &qlist_grp0_bank); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + } + + for (j = 0; j < 64; j++) + { + qcfg_qlist_grp.qcfg_qlist_grp_wr = j % 4; + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_GRPr, + 0, + j, + &qcfg_qlist_grp); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + rc = dpp_tm_qmu_cfg_done_set(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_cfg_done_set"); + + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "========dpp_etm_qmu_init_set_1 END=======\n"); + + return DPP_OK; +} + + + +/***********************************************************/ +/** QMU初始化配置场景6：4组*2bank，MMU实际分配ftm:4,6,7,9组(01bank); etm:4,6,7,9组(23bank) +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xuhb @date 2020/05/13 +************************************************************/ +DPP_STATUS dpp_tm_qmu_init_set_6(ZXIC_UINT32 dev_id) +{ + DPP_STATUS rc = DPP_OK; + + /* etm mmu基址配置:ddr4,6,7,9组，bank号01，bank深度4*1024 */ + //rc = dpp_mmu_bank_base_addr_set(dev_id, 0x2d0, 0xc, 4*1024); + //ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_mmu_bank_base_addr_set"); + + rc = dpp_etm_qmu_init_set_6(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_etm_qmu_init_set"); + + return DPP_OK; +} + + +/***********************************************************/ +/** QMU/MMU初始化配置场景7：每个tm用8组*4bank，MMU实际分配ftm:2-9组(0145bank); etm:2-9组(2367bank) +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/10/14 +************************************************************/ +DPP_STATUS dpp_etm_qmu_init_set_7(ZXIC_UINT32 dev_id) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 k = 0; + ZXIC_UINT32 i = 0; + ZXIC_UINT32 j = 0; + ZXIC_UINT32 depth = 1024; + ZXIC_UINT32 bank_to_mmu_cfg_map[4] = {2, 3, 6, 7}; + ZXIC_UINT32 qlist_grp0_bank_data[4] = {0, 1, 2, 3}; + + + DPP_ETM_QMU_QCFG_QLIST_BDEP_T qlist_bdep = {0}; + DPP_ETM_QMU_QCFG_QLIST_BHEAD_T qlist_bhead = {0}; + DPP_ETM_QMU_QCFG_QLIST_BTAIL_T qlist_btail = {0}; + + DPP_ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFG_T active_to_bank_cfg = {0}; + DPP_ETM_QMU_CFGMT_DDR_IN_MMU_CFG_T ddr_in_mmu_cfg = {0}; + DPP_ETM_QMU_CFGMT_DDR_IN_QMU_CFG_T ddr_in_qmu_cfg = {0}; + DPP_ETM_QMU_CFGMT_BANK_TO_MMU_CFG_T bank_to_mmu_cfg = {0}; + DPP_ETM_QMU_CFGMT_BANK_TO_QMU_CFG_T bank_to_qmu_cfg = {0}; + DPP_ETM_QMU_QCFG_QLIST_GRP0_BANK_T qlist_grp0_bank = {0}; + DPP_ETM_QMU_QCFG_QLIST_GRP_T qcfg_qlist_grp = {0}; + + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "========dpp_etm_qmu_init_set_1 start========n"); + + + /* ddr组从qmu到mmu映射,0~7映射成2~9 */ + for (i = 0; i < 8; i++) + { + ddr_in_mmu_cfg.cfgmt_ddr_in_mmu_cfg = (i + 2); + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_DDR_IN_MMU_CFGr, + 0, + i, + &ddr_in_mmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + /* ddr组从mmu到qmu映射,2~9映射成0~7 */ + for (i = 2; i < 10; i++) + { + ddr_in_qmu_cfg.cfgmt_ddr_in_qmu_cfg = (i - 2); + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_DDR_IN_QMU_CFGr, + 0, + i, + &ddr_in_qmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + + /* bank号从qmu到mmu映射，每组的bank0~3映射成bank2、3、6、7 */ + for (j = 0; j < 8; j++) + { + for (i = 0; i < 4; i++) + { + k = j * 8 + i; + + bank_to_mmu_cfg.cfgmt_bank_in_mmu_cfg = bank_to_mmu_cfg_map[i]; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_BANK_TO_MMU_CFGr, + 0, + k, + &bank_to_mmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + } + + + /* bank号从mmu到qmu映射，每组的bank2、3、6、7映射成bank0、1、2、3 */ + for (j = 2; j < 10; j++) + { + for (i = 0; i < 4; i++) + { + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, j , 8); + ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(dev_id, j* 8 , bank_to_mmu_cfg_map[i]); + k = j * 8 + bank_to_mmu_cfg_map[i]; + bank_to_qmu_cfg.cfgmt_bank_in_qmu_cfg = i; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_BANK_TO_QMU_CFGr, + 0, + k, + &bank_to_qmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + } + + /* random映射ram:配置一个chunk中，bank的轮询顺序 */ + for (i = 0; i < 16; i++) + { + + + active_to_bank_cfg.cfgmt_active_to_bank_cfg = i % 4; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFGr, + 0, + i, + &active_to_bank_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + } + + + /* 首尾深度指针配置 */ + for (j = 0; j < 8; j++) + { + for (i = 0; i < 4; i++) + { + k = j * 8 + i; + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, (j * 4 + i), depth); + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, (j * 4 + i + 1), depth); + qlist_bhead.bank_vld = 1; + qlist_bhead.qcfg_qlist_bhead = (j * 4 + i) * depth; + qlist_btail.qcfg_qlist_btail = ((j * 4 + i + 1) * depth - 1); + qlist_bdep.qcfg_qlist_bdep = depth; + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BHEADr, + 0, + k, + &qlist_bhead); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BTAILr, + 0, + k, + &qlist_btail); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BDEPr, + 0, + k, + &qlist_bdep); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + } + + for (i = 0; i < 64; i++) + { + qlist_bdep.qcfg_qlist_bdep = depth; + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BDEPr, + 0, + i, + &qlist_bdep); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(ETM_QMU_QCFG_QLIST_GRP0_BANKr, 8); + /* 随机表配置，决定每组bank的轮询顺序 */ + for (j = 0; j < 8; j++) + { + for (i = 0; i < 64; i++) + { + qlist_grp0_bank.qcfg_qlist_grp0_bank_wr = qlist_grp0_bank_data[i % 4]; + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_GRP0_BANKr + j, + 0, + i, + &qlist_grp0_bank); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + } + + for (j = 0; j < 64; j++) + { + qcfg_qlist_grp.qcfg_qlist_grp_wr = j % 8; + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_GRPr, + 0, + j, + &qcfg_qlist_grp); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + rc = dpp_tm_qmu_cfg_done_set(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_cfg_done_set"); + + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "========dpp_etm_qmu_init_set_1 END=======\n"); + + return DPP_OK; +} + + + +/***********************************************************/ +/** QMU/MMU初始化配置场景7：每个tm用8组*4bank，MMU实际分配ftm:2-9组(0145bank); etm:2-9组(2367bank) +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/10/14 +************************************************************/ +DPP_STATUS dpp_tm_qmu_init_set_7(ZXIC_UINT32 dev_id) +{ + DPP_STATUS rc = DPP_OK; + + + + /*关闭随机模式*/ + rc = dpp_tm_qmu_ddr_random_set(dev_id, 0); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_ddr_random_set"); + + /* etm mmu基址配置:ddr2-9组，bank号2367，bank深度1024 */ + //rc = dpp_mmu_bank_base_addr_set(dev_id, 0x3fc, 0xcc, 1024); + //ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_mmu_bank_base_addr_set"); + + rc = dpp_etm_qmu_init_set_7(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_etm_qmu_init_set"); + + return DPP_OK; +} + + +/***********************************************************/ +/** QMU/MMU初始化配置场景8：每个tm用8组*4bank，MMU实际分配ftm:2-9组(01bank); etm:2-9组(23bank) +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/10/14 +************************************************************/ +DPP_STATUS dpp_etm_qmu_init_set_8(ZXIC_UINT32 dev_id) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 k = 0; + ZXIC_UINT32 i = 0; + ZXIC_UINT32 j = 0; + ZXIC_UINT32 depth = 2048; + ZXIC_UINT32 bank_to_mmu_cfg_map[4] = {2, 3}; + ZXIC_UINT32 qlist_grp0_bank_data[4] = {0, 1}; + + + DPP_ETM_QMU_QCFG_QLIST_BDEP_T qlist_bdep = {0}; + DPP_ETM_QMU_QCFG_QLIST_BHEAD_T qlist_bhead = {0}; + DPP_ETM_QMU_QCFG_QLIST_BTAIL_T qlist_btail = {0}; + + DPP_ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFG_T active_to_bank_cfg = {0}; + DPP_ETM_QMU_CFGMT_DDR_IN_MMU_CFG_T ddr_in_mmu_cfg = {0}; + DPP_ETM_QMU_CFGMT_DDR_IN_QMU_CFG_T ddr_in_qmu_cfg = {0}; + DPP_ETM_QMU_CFGMT_BANK_TO_MMU_CFG_T bank_to_mmu_cfg = {0}; + DPP_ETM_QMU_CFGMT_BANK_TO_QMU_CFG_T bank_to_qmu_cfg = {0}; + DPP_ETM_QMU_QCFG_QLIST_GRP0_BANK_T qlist_grp0_bank = {0}; + DPP_ETM_QMU_QCFG_QLIST_GRP_T qcfg_qlist_grp = {0}; + + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "========dpp_etm_qmu_init_set_1 start========n"); + + + /* ddr组从qmu到mmu映射,0~7映射成2~9 */ + for (i = 0; i < 8; i++) + { + ddr_in_mmu_cfg.cfgmt_ddr_in_mmu_cfg = (i + 2); + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_DDR_IN_MMU_CFGr, + 0, + i, + &ddr_in_mmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + /* ddr组从mmu到qmu映射,2~9映射成0~7 */ + for (i = 2; i < 10; i++) + { + ddr_in_qmu_cfg.cfgmt_ddr_in_qmu_cfg = (i - 2); + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_DDR_IN_QMU_CFGr, + 0, + i, + &ddr_in_qmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + + /* bank号从qmu到mmu映射，每组的bank0~1映射成bank2、3 */ + for (j = 0; j < 8; j++) + { + for (i = 0; i < 2; i++) + { + k = j * 8 + i; + + bank_to_mmu_cfg.cfgmt_bank_in_mmu_cfg = bank_to_mmu_cfg_map[i]; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_BANK_TO_MMU_CFGr, + 0, + k, + &bank_to_mmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + } + + + /* bank号从mmu到qmu映射，每组的bank2、3映射成bank0、1 */ + for (j = 2; j < 10; j++) + { + for (i = 0; i < 2; i++) + { + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, j, 8); + ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(dev_id, j * 8 , bank_to_mmu_cfg_map[i]); + k = j * 8 + bank_to_mmu_cfg_map[i]; + bank_to_qmu_cfg.cfgmt_bank_in_qmu_cfg = i; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_BANK_TO_QMU_CFGr, + 0, + k, + &bank_to_qmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + } + + /* random映射ram:配置一个chunk中，bank的轮询顺序 */ + for (i = 0; i < 16; i++) + { + + + active_to_bank_cfg.cfgmt_active_to_bank_cfg = i % 2; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFGr, + 0, + i, + &active_to_bank_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + } + + + /* 首尾深度指针配置 */ + for (j = 0; j < 8; j++) + { + for (i = 0; i < 2; i++) + { + k = j * 8 + i; + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, (j * 2 + i), depth); + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, (j * 2 + i + 1), depth); + qlist_bhead.bank_vld = 1; + qlist_bhead.qcfg_qlist_bhead = (j * 2 + i) * depth; + qlist_btail.qcfg_qlist_btail = ((j * 2 + i + 1) * depth - 1); + qlist_bdep.qcfg_qlist_bdep = depth; + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BHEADr, + 0, + k, + &qlist_bhead); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BTAILr, + 0, + k, + &qlist_btail); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BDEPr, + 0, + k, + &qlist_bdep); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + } + + ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(ETM_QMU_QCFG_QLIST_GRP0_BANKr, 8); + /* 随机表配置，决定每组bank的轮询顺序 */ + for (j = 0; j < 8; j++) + { + for (i = 0; i < 64; i++) + { + qlist_grp0_bank.qcfg_qlist_grp0_bank_wr = qlist_grp0_bank_data[i % 2]; + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_GRP0_BANKr + j, + 0, + i, + &qlist_grp0_bank); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + } + + for (j = 0; j < 64; j++) + { + qcfg_qlist_grp.qcfg_qlist_grp_wr = j % 8; + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_GRPr, + 0, + j, + &qcfg_qlist_grp); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + rc = dpp_tm_qmu_cfg_done_set(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_cfg_done_set"); + + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "========dpp_etm_qmu_init_set_1 END=======\n"); + + return DPP_OK; +} + + + +/***********************************************************/ +/** QMU/MMU初始化配置场景8：每个tm用8组*4bank，MMU实际分配ftm:2-9组(01bank); etm:2-9组(23bank) +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/10/14 +************************************************************/ +DPP_STATUS dpp_tm_qmu_init_set_8(ZXIC_UINT32 dev_id) +{ + DPP_STATUS rc = DPP_OK; + + /* etm mmu基址配置:ddr2-9组，bank号23，bank深度1024 */ + //rc = dpp_mmu_bank_base_addr_set(dev_id, 0x3fc, 0xc, 2048); + //ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_mmu_bank_base_addr_set"); + + rc = dpp_etm_qmu_init_set_8(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_etm_qmu_init_set"); + + return DPP_OK; +} + + +/***********************************************************/ +/** QMU初始化配置场景9：4组*2bank，MMU实际分配ftm:6,7,8,9组(01bank); etm:6,7,8,9组(23bank) +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xuhb @date 2020/09/28 +************************************************************/ +DPP_STATUS dpp_etm_qmu_init_set_9(ZXIC_UINT32 dev_id) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 k = 0; + ZXIC_UINT32 i = 0; + ZXIC_UINT32 j = 0; + ZXIC_UINT32 depth = 4*1024; + ZXIC_UINT32 bank_to_mmu_cfg_map[4] = {2, 3}; + ZXIC_UINT32 qlist_grp0_bank_data[4] = {0, 1}; + ZXIC_UINT32 ddr_no[4] = {6, 7, 8, 9}; + + + DPP_ETM_QMU_QCFG_QLIST_BDEP_T qlist_bdep = {0}; + DPP_ETM_QMU_QCFG_QLIST_BHEAD_T qlist_bhead = {0}; + DPP_ETM_QMU_QCFG_QLIST_BTAIL_T qlist_btail = {0}; + + DPP_ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFG_T active_to_bank_cfg = {0}; + DPP_ETM_QMU_CFGMT_DDR_IN_MMU_CFG_T ddr_in_mmu_cfg = {0}; + DPP_ETM_QMU_CFGMT_DDR_IN_QMU_CFG_T ddr_in_qmu_cfg = {0}; + DPP_ETM_QMU_CFGMT_BANK_TO_MMU_CFG_T bank_to_mmu_cfg = {0}; + DPP_ETM_QMU_CFGMT_BANK_TO_QMU_CFG_T bank_to_qmu_cfg = {0}; + DPP_ETM_QMU_QCFG_QLIST_GRP0_BANK_T qlist_grp0_bank = {0}; + DPP_ETM_QMU_QCFG_QLIST_GRP_T qcfg_qlist_grp = {0}; + + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "========dpp_etm_qmu_init_set_1 start========n"); + + + /* ddr组从qmu到mmu映射,0~3映射成4679 */ + for (i = 0; i < 4; i++) + { + ddr_in_mmu_cfg.cfgmt_ddr_in_mmu_cfg = ddr_no[i]; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_DDR_IN_MMU_CFGr, + 0, + i, + &ddr_in_mmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + /* ddr组从mmu到qmu映射,4679映射成0~3 */ + for (i = 0; i < 4; i++) + { + ddr_in_qmu_cfg.cfgmt_ddr_in_qmu_cfg = i; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_DDR_IN_QMU_CFGr, + 0, + ddr_no[i], + &ddr_in_qmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + + /* bank号从qmu到mmu映射，每组的bank0~1映射成bank2、3 */ + for (j = 0; j < 4; j++) + { + for (i = 0; i < 2; i++) + { + k = j * 8 + i; + + bank_to_mmu_cfg.cfgmt_bank_in_mmu_cfg = bank_to_mmu_cfg_map[i]; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_BANK_TO_MMU_CFGr, + 0, + k, + &bank_to_mmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + } + + + /* bank号从mmu到qmu映射，每组的bank2、3映射成bank0、1 */ + for (j = 0; j < 4; j++) + { + for (i = 0; i < 2; i++) + { + ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW_NO_ASSERT(ddr_no[j], 8); + ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(ddr_no[j] * 8, bank_to_mmu_cfg_map[i]); + k = ddr_no[j] * 8 + bank_to_mmu_cfg_map[i]; + + bank_to_qmu_cfg.cfgmt_bank_in_qmu_cfg = i; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_BANK_TO_QMU_CFGr, + 0, + k, + &bank_to_qmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + } + + /* random映射ram:配置一个chunk中，bank的轮询顺序 */ + for (i = 0; i < 16; i++) + { + + + active_to_bank_cfg.cfgmt_active_to_bank_cfg = i % 2; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFGr, + 0, + i, + &active_to_bank_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + } + + + /* 首尾深度指针配置 */ + for (j = 0; j < 4; j++) + { + for (i = 0; i < 2; i++) + { + k = j * 8 + i; + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, (j * 2 + i), depth); + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, (j * 2 + i + 1), depth); + qlist_bhead.bank_vld = 1; + qlist_bhead.qcfg_qlist_bhead = (j * 2 + i) * depth; + qlist_btail.qcfg_qlist_btail = ((j * 2 + i + 1) * depth - 1); + qlist_bdep.qcfg_qlist_bdep = depth; + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BHEADr, + 0, + k, + &qlist_bhead); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BTAILr, + 0, + k, + &qlist_btail); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BDEPr, + 0, + k, + &qlist_bdep); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + } + + for (i = 0; i < 64; i++) + { + qlist_bdep.qcfg_qlist_bdep = depth; + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BDEPr, + 0, + i, + &qlist_bdep); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + + ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(ETM_QMU_QCFG_QLIST_GRP0_BANKr, 8); + /* 随机表配置，决定每组bank的轮询顺序 */ + for (j = 0; j < 8; j++) + { + for (i = 0; i < 64; i++) + { + qlist_grp0_bank.qcfg_qlist_grp0_bank_wr = qlist_grp0_bank_data[i % 2]; + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_GRP0_BANKr + j, + 0, + i, + &qlist_grp0_bank); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + } + + for (j = 0; j < 64; j++) + { + qcfg_qlist_grp.qcfg_qlist_grp_wr = j % 4; + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_GRPr, + 0, + j, + &qcfg_qlist_grp); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + rc = dpp_tm_qmu_cfg_done_set(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_cfg_done_set"); + + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "========dpp_etm_qmu_init_set_1 END=======\n"); + + return DPP_OK; +} + + +/***********************************************************/ +/** QMU/MMU初始化配置场景8：每个tm用8组*4bank，MMU实际分配ftm:2-9组(01bank); etm:2-9组(23bank) +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/10/14 +************************************************************/ +DPP_STATUS dpp_tm_qmu_init_set_9(ZXIC_UINT32 dev_id) +{ + DPP_STATUS rc = DPP_OK; + + /* etm mmu基址配置:ddr2-9组，bank号23，bank深度1024 */ + //rc = dpp_mmu_bank_base_addr_set(dev_id, 0x3fc, 0xc, 2048); + //ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_mmu_bank_base_addr_set"); + + rc = dpp_etm_qmu_init_set_8(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_etm_qmu_init_set"); + + return DPP_OK; +} + +/***********************************************************/ +/** QMU初始化配置场景10：独享2组*8bank，MMU实际分配1,2; etm or ftm使用0-7bank +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xuhb @date 2020/12/16 +************************************************************/ +DPP_STATUS dpp_etm_qmu_init_set_10(ZXIC_UINT32 dev_id) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 k = 0; + ZXIC_UINT32 i = 0; + ZXIC_UINT32 j = 0; + ZXIC_UINT32 depth = 2*1024; + ZXIC_UINT32 bank_to_mmu_cfg_map[8] = {0, 1, 2, 3, 4, 5, 6, 7}; + ZXIC_UINT32 qlist_grp0_bank_data[8] = {0, 1, 2, 3, 4, 5, 6, 7}; + ZXIC_UINT32 ddr_no[2] = {1,2}; + + + DPP_ETM_QMU_QCFG_QLIST_BDEP_T qlist_bdep = {0}; + DPP_ETM_QMU_QCFG_QLIST_BHEAD_T qlist_bhead = {0}; + DPP_ETM_QMU_QCFG_QLIST_BTAIL_T qlist_btail = {0}; + + DPP_ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFG_T active_to_bank_cfg = {0}; + DPP_ETM_QMU_CFGMT_DDR_IN_MMU_CFG_T ddr_in_mmu_cfg = {0}; + DPP_ETM_QMU_CFGMT_DDR_IN_QMU_CFG_T ddr_in_qmu_cfg = {0}; + DPP_ETM_QMU_CFGMT_BANK_TO_MMU_CFG_T bank_to_mmu_cfg = {0}; + DPP_ETM_QMU_CFGMT_BANK_TO_QMU_CFG_T bank_to_qmu_cfg = {0}; + DPP_ETM_QMU_QCFG_QLIST_GRP0_BANK_T qlist_grp0_bank = {0}; + DPP_ETM_QMU_QCFG_QLIST_GRP_T qcfg_qlist_grp = {0}; + + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "========dpp_etm_qmu_init_set_1 start========n"); + + + /* ddr组从qmu到mmu映射,0~1映射成12 */ + for (i = 0; i < 2; i++) + { + ddr_in_mmu_cfg.cfgmt_ddr_in_mmu_cfg = ddr_no[i]; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_DDR_IN_MMU_CFGr, + 0, + i, + &ddr_in_mmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + /* ddr组从mmu到qmu映射,12映射成0~1 */ + for (i = 0; i < 2; i++) + { + ddr_in_qmu_cfg.cfgmt_ddr_in_qmu_cfg = i; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_DDR_IN_QMU_CFGr, + 0, + ddr_no[i], + &ddr_in_qmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + + /* bank号从qmu到mmu映射，每组的bank0~7映射成bank0-7 */ + for (j = 0; j < 2; j++) + { + for (i = 0; i < 8; i++) + { + k = j * 8 + i; + + bank_to_mmu_cfg.cfgmt_bank_in_mmu_cfg = bank_to_mmu_cfg_map[i]; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_BANK_TO_MMU_CFGr, + 0, + k, + &bank_to_mmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + } + + + /* bank号从mmu到qmu映射，每组的bank0-7映射成bank0-7 */ + for (j = 0; j < 2; j++) + { + for (i = 0; i < 8; i++) + { + ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW_NO_ASSERT(ddr_no[j], 8); + ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(ddr_no[j] * 8, bank_to_mmu_cfg_map[i]); + k = ddr_no[j] * 8 + bank_to_mmu_cfg_map[i]; + + bank_to_qmu_cfg.cfgmt_bank_in_qmu_cfg = i; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_BANK_TO_QMU_CFGr, + 0, + k, + &bank_to_qmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + } + + /* random映射ram:配置一个chunk中，bank的轮询顺序 */ + for (i = 0; i < 16; i++) + { + + + active_to_bank_cfg.cfgmt_active_to_bank_cfg = i % 8; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFGr, + 0, + i, + &active_to_bank_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + } + + + /* 首尾深度指针配置 */ + for (j = 0; j < 2; j++) + { + for (i = 0; i < 8; i++) + { + k = j * 8 + i; + + qlist_bhead.bank_vld = 1; + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, (j * 8 + i), depth); + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, (j * 8 + i + 1), depth); + qlist_bhead.qcfg_qlist_bhead = (j * 8 + i) * depth; + qlist_btail.qcfg_qlist_btail = ((j * 8 + i + 1) * depth - 1); + qlist_bdep.qcfg_qlist_bdep = depth; + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BHEADr, + 0, + k, + &qlist_bhead); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BTAILr, + 0, + k, + &qlist_btail); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BDEPr, + 0, + k, + &qlist_bdep); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + } + + for (i = 0; i < 64; i++) + { + qlist_bdep.qcfg_qlist_bdep = depth; + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BDEPr, + 0, + i, + &qlist_bdep); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(ETM_QMU_QCFG_QLIST_GRP0_BANKr, 8); + /* 随机表配置，决定每组bank的轮询顺序 */ + for (j = 0; j < 8; j++) + { + for (i = 0; i < 64; i++) + { + qlist_grp0_bank.qcfg_qlist_grp0_bank_wr = qlist_grp0_bank_data[i % 8]; + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_GRP0_BANKr + j, + 0, + i, + &qlist_grp0_bank); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + } + + for (j = 0; j < 64; j++) + { + qcfg_qlist_grp.qcfg_qlist_grp_wr = j % 2; + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_GRPr, + 0, + j, + &qcfg_qlist_grp); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + rc = dpp_tm_qmu_cfg_done_set(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_cfg_done_set"); + + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "========dpp_etm_qmu_init_set_1 END=======\n"); + + return DPP_OK; +} + +/***********************************************************/ +/** QMU初始化配置场景10：独享2组*8bank，MMU实际分配1,2; etm or ftm使用0-7bank +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xuhb @date 2020/12/16 +************************************************************/ +DPP_STATUS dpp_tm_qmu_init_set_10(ZXIC_UINT32 dev_id) +{ + DPP_STATUS rc = DPP_OK; + + /* etm mmu基址配置:ddr1,2组，bank号0-7，bank深度2*1024 */ + //rc = dpp_mmu_bank_base_addr_set(dev_id, 0x6, 0xff, 2*1024); + //ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_mmu_bank_base_addr_set"); + + rc = dpp_etm_qmu_init_set_10(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_etm_qmu_init_set_10"); + + return DPP_OK; +} + + +/***********************************************************/ +/**场景11：TM共享2组ddr:FTM为ddr_no1、ddr_no2组ddr的01bank，ETM为ddr_no1、ddr_no2组ddr 23bank +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xuhb @date 2020/06/06 +************************************************************/ +DPP_STATUS dpp_etm_qmu_init_set_11(ZXIC_UINT32 dev_id, ZXIC_UINT32 ddr_no1, ZXIC_UINT32 ddr_no2) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 k = 0; + ZXIC_UINT32 i = 0; + ZXIC_UINT32 j = 0; + ZXIC_UINT32 depth = 8 * 1024; + ZXIC_UINT32 ddr_to_mmu_cfg_map[2] = {ddr_no1, ddr_no2}; + ZXIC_UINT32 bank_to_mmu_cfg_map[2] = {2, 3}; + ZXIC_UINT32 qlist_grp0_bank_data[2] = {0, 1}; + + + DPP_ETM_QMU_QCFG_QLIST_BDEP_T qlist_bdep = {0}; + DPP_ETM_QMU_QCFG_QLIST_BHEAD_T qlist_bhead = {0}; + DPP_ETM_QMU_QCFG_QLIST_BTAIL_T qlist_btail = {0}; + + DPP_ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFG_T active_to_bank_cfg = {0}; + DPP_ETM_QMU_CFGMT_DDR_IN_MMU_CFG_T ddr_in_mmu_cfg = {0}; + DPP_ETM_QMU_CFGMT_DDR_IN_QMU_CFG_T ddr_in_qmu_cfg = {0}; + DPP_ETM_QMU_CFGMT_BANK_TO_MMU_CFG_T bank_to_mmu_cfg = {0}; + DPP_ETM_QMU_CFGMT_BANK_TO_QMU_CFG_T bank_to_qmu_cfg = {0}; + DPP_ETM_QMU_QCFG_QLIST_GRP0_BANK_T qlist_grp0_bank = {0}; + DPP_ETM_QMU_QCFG_QLIST_GRP_T qcfg_qlist_grp = {0}; + + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "========dpp_etm_qmu_init_set_11 start========n"); + + + /* ddr组从qmu到mmu映射,0~1映射成ddr_no1 ddr_no2 */ + for (i = 0; i < 2; i++) + { + ddr_in_mmu_cfg.cfgmt_ddr_in_mmu_cfg = ddr_to_mmu_cfg_map[i]; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_DDR_IN_MMU_CFGr, + 0, + i, + &ddr_in_mmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + /* ddr组从mmu到qmu映射,ddr_no1 ddr_no2映射成0~1 */ + for (i = 0; i < 2; i++) + { + ddr_in_qmu_cfg.cfgmt_ddr_in_qmu_cfg = i; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_DDR_IN_QMU_CFGr, + 0, + ddr_to_mmu_cfg_map[i], + &ddr_in_qmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + + /* bank号从qmu到mmu映射，每组的bank0~1映射成bank2、3 */ + for (j = 0; j < 2; j++) + { + for (i = 0; i < 2; i++) + { + k = j * 8 + i; + + bank_to_mmu_cfg.cfgmt_bank_in_mmu_cfg = bank_to_mmu_cfg_map[i]; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_BANK_TO_MMU_CFGr, + 0, + k, + &bank_to_mmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + } + + + /* bank号从mmu到qmu映射，每组的bank2、3映射成bank0、1 */ + for (j = 0; j < 2; j++) + { + for (i = 0; i < 2; i++) + { + ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW_NO_ASSERT(ddr_to_mmu_cfg_map[j], 8); + ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(ddr_to_mmu_cfg_map[j] * 8, bank_to_mmu_cfg_map[i]); + k = ddr_to_mmu_cfg_map[j] * 8 + bank_to_mmu_cfg_map[i]; + + bank_to_qmu_cfg.cfgmt_bank_in_qmu_cfg = i; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_BANK_TO_QMU_CFGr, + 0, + k, + &bank_to_qmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + } + + /* random映射ram:配置一个chunk中，bank的轮询顺序 */ + for (i = 0; i < 16; i++) + { + + + active_to_bank_cfg.cfgmt_active_to_bank_cfg = i % 2; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFGr, + 0, + i, + &active_to_bank_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + } + + + /* 首尾深度指针配置 */ + for (j = 0; j < 2; j++) + { + for (i = 0; i < 2; i++) + { + k = j * 8 + i; + + qlist_bhead.bank_vld = 1; + ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW_NO_ASSERT((j * 2 + i), depth); + qlist_bhead.qcfg_qlist_bhead = (j * 2 + i) * depth; + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, (j * 2 + i), depth); + qlist_btail.qcfg_qlist_btail = ((j * 2 + i + 1) * depth - 1); + qlist_bdep.qcfg_qlist_bdep = depth; + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BHEADr, + 0, + k, + &qlist_bhead); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BTAILr, + 0, + k, + &qlist_btail); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BDEPr, + 0, + k, + &qlist_bdep); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + } + + for (i = 0; i < 64; i++) + { + qlist_bdep.qcfg_qlist_bdep = depth; + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BDEPr, + 0, + i, + &qlist_bdep); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(ETM_QMU_QCFG_QLIST_GRP0_BANKr, 8); + /* 随机表配置，决定每组bank的轮询顺序 */ + for (j = 0; j < 8; j++) + { + for (i = 0; i < 64; i++) + { + qlist_grp0_bank.qcfg_qlist_grp0_bank_wr = qlist_grp0_bank_data[i % 2]; + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_GRP0_BANKr + j, + 0, + i, + &qlist_grp0_bank); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + } + + for (j = 0; j < 64; j++) + { + qcfg_qlist_grp.qcfg_qlist_grp_wr = j % 2; + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_GRPr, + 0, + j, + &qcfg_qlist_grp); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + rc = dpp_tm_qmu_cfg_done_set(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_cfg_done_set"); + + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "========dpp_etm_qmu_init_set_11 END=======\n"); + + return DPP_OK; +} + + + +/***********************************************************/ +/**场景4：TM共享2组ddr:FTM为ddr_no1,ddr_no2组ddr的01bank，ETM为ddr_no1,ddr_no2组ddr 23bank +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xuhb @date 2020/06/06 +************************************************************/ +DPP_STATUS dpp_tm_qmu_init_set_11(ZXIC_UINT32 dev_id, ZXIC_UINT32 ddr_no1, ZXIC_UINT32 ddr_no2) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_RANDOM_BYPASS_EN_T etm_bypass = {0}; + //DPP_FTM_QMU_RANDOM_BYPASS_EN_T ftm_bypass = {0}; + + + ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT((1U<> 4) & 0xf; + ddr_no_data[1] = (ddr_no >> 8) & 0xf; + ddr_no_data[0] = (ddr_no >> 12) & 0xf; + + /* ddr组从qmu到mmu映射,0~3映射成ddr_no */ + for (i = 0; i < 4; i++) + { + ddr_in_mmu_cfg.cfgmt_ddr_in_mmu_cfg = ddr_no_data[i]; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_DDR_IN_MMU_CFGr, + 0, + i, + &ddr_in_mmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + /* ddr组从mmu到qmu映射,ddr_no映射成0~3 */ + for (i = 0; i < 4; i++) + { + ddr_in_qmu_cfg.cfgmt_ddr_in_qmu_cfg = i; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_DDR_IN_QMU_CFGr, + 0, + ddr_no_data[i], + &ddr_in_qmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + /* bank号从qmu到mmu映射，组0~3的bank0-7映射成bank0-7 */ + for (j = 0; j < 4; j++) + { + for (i = 0; i < 8; i++) + { + k = j * 8 + i; + + bank_to_mmu_cfg.cfgmt_bank_in_mmu_cfg = i; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_BANK_TO_MMU_CFGr, + 0, + k, + &bank_to_mmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + } + + + /* bank号从mmu到qmu映射，组ddr_no的bank0-7映射成bank0-7 */ + for (j = 0; j < 4; j++) + { + for (i = 0; i < 8; i++) + { + ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW_NO_ASSERT(ddr_no_data[j], 8); + ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(ddr_no_data[j] * 8, i); + k = ddr_no_data[j] * 8 + i; + + bank_to_qmu_cfg.cfgmt_bank_in_qmu_cfg = i; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_BANK_TO_QMU_CFGr, + 0, + k, + &bank_to_qmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + } + + /* random映射ram:配置一个chunk中，bank的轮询顺序 */ + for (i = 0; i < 16; i++) + { + active_to_bank_cfg.cfgmt_active_to_bank_cfg = i % 8; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFGr, + 0, + i, + &active_to_bank_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + /* 首尾深度指针配置:j为4组循环 */ + for (j = 0; j < 4; j++) + { + for (i = 0; i < 8; i++) + { + k = j * 8 + i; + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, (j * 8 + i), depth); + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, (j * 8 + i + 1), depth); + qlist_bhead.bank_vld = 1; + qlist_bhead.qcfg_qlist_bhead = (j * 8 + i) * depth; + qlist_btail.qcfg_qlist_btail = ((j * 8 + i + 1) * depth - 1); + qlist_bdep.qcfg_qlist_bdep = depth; + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BHEADr, + 0, + k, + &qlist_bhead); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BTAILr, + 0, + k, + &qlist_btail); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BDEPr, + 0, + k, + &qlist_bdep); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + } + for (i = 0; i < 64; i++) + { + qlist_bdep.qcfg_qlist_bdep = depth; + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BDEPr, + 0, + i, + &qlist_bdep); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(ETM_QMU_QCFG_QLIST_GRP0_BANKr, 8); + /* 随机表配置，决定ddr内bank的轮询顺序:使用几组ddr需要配置几组 */ + for (j = 0; j < 8; j++) + { + for (i = 0; i < 64; i++) + { + + qlist_grp0_bank.qcfg_qlist_grp0_bank_wr = qlist_grp0_bank_data[i % 8]; + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_GRP0_BANKr + j, + 0, + i, + &qlist_grp0_bank); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + } + } + + for (j = 0; j < 64; j++) + { + qcfg_qlist_grp.qcfg_qlist_grp_wr = j % 4; + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_GRPr, + 0, + j, + &qcfg_qlist_grp); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + rc = dpp_tm_qmu_cfg_done_set(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_cfg_done_set"); + + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "++++++dpp_etm_qmu_init_set end++++++\n"); + + return DPP_OK; +} + + + + +/***********************************************************/ +/** QMU/MMU初始化配置场景13：TM独享4组ddr:FTM为指定4组ddr的0~7bank + ETM为指定4组ddr的0-7bank +* MMU开启rotatjon +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xuhb @date 2016/11/17 +************************************************************/ +DPP_STATUS dpp_tm_qmu_init_set_13(ZXIC_UINT32 dev_id, ZXIC_UINT32 ddr_no) +{ + DPP_STATUS rc = DPP_OK; + DPP_STATUS ddr_no_temp = 0; + DPP_ETM_QMU_RANDOM_BYPASS_EN_T etm_bypass = {0}; + //DPP_FTM_QMU_RANDOM_BYPASS_EN_T ftm_bypass = {0}; + + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, ((ddr_no >> 0) & 0xfU), 0, 9); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, ((ddr_no >> 4) & 0xfU), 0, 9); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, ((ddr_no >> 8) & 0xfU), 0, 9); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, ((ddr_no >> 12) & 0xfU), 0, 9); + + ddr_no_temp = ((1U << (ddr_no & 0xfU)) + (1U << ((ddr_no >> 4) & 0xfU))+ \ + (1U << ((ddr_no >> 8) & 0xfU)) + (1U << ((ddr_no >> 12) & 0xfU))) & 0x3ff; + + + /* etm mmu基址配置:ddr_no中的4组，bank号0-7，bank深度1024 */ + //rc = dpp_mmu_bank_base_addr_set(dev_id, ddr_no_temp, 0xff, 1024); + //ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_mmu_bank_base_addr_set"); + + rc = dpp_etm_qmu_init_set_13(dev_id, ddr_no); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_etm_qmu_init_set_13"); + + /* 关闭etm映射配置 */ + etm_bypass.random_bypass_en = 0; + rc = dpp_reg_write(dev_id, + ETM_QMU_RANDOM_BYPASS_ENr, + 0, + 0, + &etm_bypass); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + + return DPP_OK; +} + + + +/***********************************************************/ +/** QMU/MMU初始化配置场景14：每个tm只用1组*8bank，MMU实际分配ftm:0-9中指定组(0-7bank); etm:0-9中指定组(0-7bank) +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xuhb @date 2020/4/14 +************************************************************/ +DPP_STATUS dpp_etm_qmu_init_set_14(ZXIC_UINT32 dev_id, ZXIC_UINT32 etm_ddr_no) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 k = 0; + ZXIC_UINT32 i = 0; + ZXIC_UINT32 j = 0; + ZXIC_UINT32 depth = 4 * 1024; + ZXIC_UINT32 bank_to_mmu_cfg_map[8] = {0, 1, 2, 3, 4, 5, 6, 7}; + ZXIC_UINT32 qlist_grp0_bank_data[8] = {0, 1, 2, 3, 4, 5, 6, 7}; + + + DPP_ETM_QMU_QCFG_QLIST_BDEP_T qlist_bdep = {0}; + DPP_ETM_QMU_QCFG_QLIST_BHEAD_T qlist_bhead = {0}; + DPP_ETM_QMU_QCFG_QLIST_BTAIL_T qlist_btail = {0}; + + DPP_ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFG_T active_to_bank_cfg = {0}; + DPP_ETM_QMU_CFGMT_DDR_IN_MMU_CFG_T ddr_in_mmu_cfg = {0}; + DPP_ETM_QMU_CFGMT_DDR_IN_QMU_CFG_T ddr_in_qmu_cfg = {0}; + DPP_ETM_QMU_CFGMT_BANK_TO_MMU_CFG_T bank_to_mmu_cfg = {0}; + DPP_ETM_QMU_CFGMT_BANK_TO_QMU_CFG_T bank_to_qmu_cfg = {0}; + DPP_ETM_QMU_QCFG_QLIST_GRP0_BANK_T qlist_grp0_bank = {0}; + DPP_ETM_QMU_QCFG_QLIST_GRP_T qcfg_qlist_grp = {0}; + + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "========dpp_etm_qmu_init_set_1 start========n"); + + + /* ddr组从qmu到mmu映射,将0映射成etm_ddr_no */ + i = 0; + ddr_in_mmu_cfg.cfgmt_ddr_in_mmu_cfg = etm_ddr_no; + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_DDR_IN_MMU_CFGr, + 0, + i, + &ddr_in_mmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + + /* ddr组从mmu到qmu映射,etm_ddr_no映射成0 */ + i = etm_ddr_no; + ddr_in_qmu_cfg.cfgmt_ddr_in_qmu_cfg = 0; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_DDR_IN_QMU_CFGr, + 0, + i, + &ddr_in_qmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + + /* bank号从qmu到mmu映射，每组的bank0-7映射成bank0-7 */ + j = 0; + + for (i = 0; i < 8; i++) + { + k = j * 8 + i; + bank_to_mmu_cfg.cfgmt_bank_in_mmu_cfg = bank_to_mmu_cfg_map[i]; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_BANK_TO_MMU_CFGr, + 0, + k, + &bank_to_mmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + + /* bank号从mmu到qmu映射，每组的bank0-7映射成bank0-7 */ + j = etm_ddr_no; + + for (i = 0; i < 8; i++) + { + ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW_NO_ASSERT(j, 8); + ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(j * 8, bank_to_mmu_cfg_map[i]); + k = j * 8 + bank_to_mmu_cfg_map[i]; + bank_to_qmu_cfg.cfgmt_bank_in_qmu_cfg = i; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_BANK_TO_QMU_CFGr, + 0, + k, + &bank_to_qmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + + /* random映射ram:配置一个chunk中，bank的轮询顺序 */ + for (i = 0; i < 16; i++) + { + active_to_bank_cfg.cfgmt_active_to_bank_cfg = i % 8; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFGr, + 0, + i, + &active_to_bank_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + + /* 首尾深度指针配置 */ + j = 0; + + for (i = 0; i < 8; i++) + { + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, (j * 8 + i), depth); + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, (j * 8 + i + 1), depth); + k = j * 8 + i; + qlist_bhead.bank_vld = 1; + qlist_bhead.qcfg_qlist_bhead = (j * 8 + i) * depth; + qlist_btail.qcfg_qlist_btail = ((j * 8 + i + 1) * depth - 1); + qlist_bdep.qcfg_qlist_bdep = depth; + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BHEADr, + 0, + k, + &qlist_bhead); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BTAILr, + 0, + k, + &qlist_btail); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BDEPr, + 0, + k, + &qlist_bdep); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + for (i = 0; i < 64; i++) + { + qlist_bdep.qcfg_qlist_bdep = depth; + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BDEPr, + 0, + i, + &qlist_bdep); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(ETM_QMU_QCFG_QLIST_GRP0_BANKr, 8); + /* 随机表配置，决定每组bank的轮询顺序 */ + for (j = 0; j < 8; j++) + { + for (i = 0; i < 64; i++) + { + qlist_grp0_bank.qcfg_qlist_grp0_bank_wr = qlist_grp0_bank_data[i % 8]; + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_GRP0_BANKr + j, + 0, + i, + &qlist_grp0_bank); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + } + + for (j = 0; j < 64; j++) + { + qcfg_qlist_grp.qcfg_qlist_grp_wr = 0; + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_GRPr, + 0, + j, + &qcfg_qlist_grp); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + rc = dpp_tm_qmu_cfg_done_set(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_cfg_done_set"); + + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "========dpp_etm_qmu_init_set_1 END=======\n"); + + return DPP_OK; +} + + + +/***********************************************************/ +/** QMU/MMU初始化配置场景14：每个tm只用1组*8bank，MMU实际分配ftm:0-9中指定组(0-7bank); etm:0-9中指定组(0-7bank) +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xuhb @date 2020/4/14 +************************************************************/ +DPP_STATUS dpp_tm_qmu_init_set_14(ZXIC_UINT32 dev_id, ZXIC_UINT32 etm_ddr_no, ZXIC_UINT32 ftm_ddr_no) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 etm_ddr_no_temp = 0; /*ETM使用的ddr,bit位表示*/ + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, etm_ddr_no, 0, 9); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, ftm_ddr_no, 0, 9); + + /*etm ftm不能使用同一组ddr*/ + if (etm_ddr_no == ftm_ddr_no) + { + ZXIC_COMM_PRINT("dpp_tm_qmu_init_set_15: etm_ddr_no can't equal to ftm_ddr_no!!!\n"); + } + + ZXIC_COMM_ASSERT(etm_ddr_no != ftm_ddr_no); + + /*将etm ftm使用的ddr号转换成对应的bit位,bit[0-9]每bit代表一组ddr */ + etm_ddr_no_temp = 0x1u << etm_ddr_no; + + /*开启随机模式*/ + rc = dpp_tm_qmu_ddr_random_set(dev_id, 1); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_ddr_random_set"); + + /* etm mmu基址配置:ddr指定etm_ddr_no组，bank号0-7bank，bank深度4K */ + //rc = dpp_mmu_bank_base_addr_set(dev_id, etm_ddr_no_temp, 0xff, 4 * 1024); + //ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_mmu_bank_base_addr_set"); + + rc = dpp_etm_qmu_init_set_14(dev_id, etm_ddr_no); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_etm_qmu_init_set"); + + return DPP_OK; +} + + +/***********************************************************/ +/** QMU/MMU初始化配置场景15：每个tm只用1组*4bank，MMU实际分配ftm:0-9中指定组(0123bank); etm:0-9中指定组(0123bank) +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xuhb @date 2020/4/14 +************************************************************/ +DPP_STATUS dpp_etm_qmu_init_set_15(ZXIC_UINT32 dev_id, ZXIC_UINT32 etm_ddr_no) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 k = 0; + ZXIC_UINT32 i = 0; + ZXIC_UINT32 j = 0; + ZXIC_UINT32 depth = 8 * 1024; + ZXIC_UINT32 bank_to_mmu_cfg_map[4] = {0, 1, 2, 3}; + ZXIC_UINT32 qlist_grp0_bank_data[4] = {0, 1, 2, 3}; + + + DPP_ETM_QMU_QCFG_QLIST_BDEP_T qlist_bdep = {0}; + DPP_ETM_QMU_QCFG_QLIST_BHEAD_T qlist_bhead = {0}; + DPP_ETM_QMU_QCFG_QLIST_BTAIL_T qlist_btail = {0}; + + DPP_ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFG_T active_to_bank_cfg = {0}; + DPP_ETM_QMU_CFGMT_DDR_IN_MMU_CFG_T ddr_in_mmu_cfg = {0}; + DPP_ETM_QMU_CFGMT_DDR_IN_QMU_CFG_T ddr_in_qmu_cfg = {0}; + DPP_ETM_QMU_CFGMT_BANK_TO_MMU_CFG_T bank_to_mmu_cfg = {0}; + DPP_ETM_QMU_CFGMT_BANK_TO_QMU_CFG_T bank_to_qmu_cfg = {0}; + DPP_ETM_QMU_QCFG_QLIST_GRP0_BANK_T qlist_grp0_bank = {0}; + DPP_ETM_QMU_QCFG_QLIST_GRP_T qcfg_qlist_grp = {0}; + + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "========dpp_etm_qmu_init_set_1 start========n"); + + + + /* ddr组从qmu到mmu映射,将0映射成etm_ddr_no */ + i = 0; + ddr_in_mmu_cfg.cfgmt_ddr_in_mmu_cfg = etm_ddr_no; + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_DDR_IN_MMU_CFGr, + 0, + i, + &ddr_in_mmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + + /* ddr组从mmu到qmu映射,etm_ddr_no映射成0 */ + i = etm_ddr_no; + ddr_in_qmu_cfg.cfgmt_ddr_in_qmu_cfg = 0; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_DDR_IN_QMU_CFGr, + 0, + i, + &ddr_in_qmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + + /* bank号从qmu到mmu映射，每组的bank0123映射成bank0123 */ + j = 0; + + for (i = 0; i < 4; i++) + { + k = j * 8 + i; + bank_to_mmu_cfg.cfgmt_bank_in_mmu_cfg = bank_to_mmu_cfg_map[i]; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_BANK_TO_MMU_CFGr, + 0, + k, + &bank_to_mmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + + /* bank号从mmu到qmu映射，每组的bank0123映射成bank0123 */ + j = etm_ddr_no; + + for (i = 0; i < 4; i++) + { + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, j, 8); + ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(dev_id, j * 8 , bank_to_mmu_cfg_map[i]); + k = j * 8 + bank_to_mmu_cfg_map[i]; + bank_to_qmu_cfg.cfgmt_bank_in_qmu_cfg = i; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_BANK_TO_QMU_CFGr, + 0, + k, + &bank_to_qmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + + /* random映射ram:配置一个chunk中，bank的轮询顺序 */ + for (i = 0; i < 16; i++) + { + active_to_bank_cfg.cfgmt_active_to_bank_cfg = i % 4; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFGr, + 0, + i, + &active_to_bank_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + + /* 首尾深度指针配置 */ + j = 0; + + for (i = 0; i < 4; i++) + { + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, (j * 4 + i), depth); + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, (j * 4 + i + 1), depth); + k = j * 8 + i; + qlist_bhead.bank_vld = 1; + qlist_bhead.qcfg_qlist_bhead = (j * 4 + i) * depth; + qlist_btail.qcfg_qlist_btail = ((j * 4 + i + 1) * depth - 1); + qlist_bdep.qcfg_qlist_bdep = depth; + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BHEADr, + 0, + k, + &qlist_bhead); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BTAILr, + 0, + k, + &qlist_btail); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BDEPr, + 0, + k, + &qlist_bdep); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + for (i = 0; i < 64; i++) + { + qlist_bdep.qcfg_qlist_bdep = depth; + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BDEPr, + 0, + i, + &qlist_bdep); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(ETM_QMU_QCFG_QLIST_GRP0_BANKr, 8); + /* 随机表配置，决定每组bank的轮询顺序 */ + for (j = 0; j < 8; j++) + { + for (i = 0; i < 64; i++) + { + qlist_grp0_bank.qcfg_qlist_grp0_bank_wr = qlist_grp0_bank_data[i % 4]; + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_GRP0_BANKr + j, + 0, + i, + &qlist_grp0_bank); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + } + + for (j = 0; j < 64; j++) + { + qcfg_qlist_grp.qcfg_qlist_grp_wr = 0; + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_GRPr, + 0, + j, + &qcfg_qlist_grp); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + rc = dpp_tm_qmu_cfg_done_set(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_cfg_done_set"); + + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "========dpp_etm_qmu_init_set_1 END=======\n"); + + return DPP_OK; +} + + + + +/***********************************************************/ +/** QMU/MMU初始化配置场景15：每个tm只用1组*4bank，MMU实际分配ftm:0-9中指定组(0123bank); etm:0-9中指定组(0123bank) +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xuhb @date 2020/4/14 +************************************************************/ +DPP_STATUS dpp_tm_qmu_init_set_15(ZXIC_UINT32 dev_id, ZXIC_UINT32 etm_ddr_no, ZXIC_UINT32 ftm_ddr_no) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 etm_ddr_no_temp = 0; /*ETM使用的ddr,bit位表示*/ + + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, etm_ddr_no, 0, 9); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, ftm_ddr_no, 0, 9); + + /*etm ftm不能使用同一组ddr*/ + if (etm_ddr_no == ftm_ddr_no) + { + ZXIC_COMM_PRINT("dpp_tm_qmu_init_set_15: etm_ddr_no can't equal to ftm_ddr_no!!!\n"); + } + + ZXIC_COMM_ASSERT(etm_ddr_no == ftm_ddr_no); + + /*将etm ftm使用的ddr号转换成对应的bit位,bit[0-9]每bit代表一组ddr */ + etm_ddr_no_temp = 0x1u << etm_ddr_no; + + /*关闭随机模式*/ + rc = dpp_tm_qmu_ddr_random_set(dev_id, 0); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_ddr_random_set"); + + /* etm mmu基址配置:ddr指定etm_ddr_no组，bank号0123，bank深度8K */ + //rc = dpp_mmu_bank_base_addr_set(dev_id, etm_ddr_no_temp, 0xf, 8 * 1024); + //ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_mmu_bank_base_addr_set"); + + rc = dpp_etm_qmu_init_set_15(dev_id, etm_ddr_no); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_etm_qmu_init_set"); + + + return DPP_OK; +} + +/***********************************************************/ +/** QMU初始化配置场景16：独享2组*8bank，MMU实际分配etm_ddr_no; etm or ftm使用0-7bank +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xuhb @date 2020/12/16 +************************************************************/ +DPP_STATUS dpp_etm_qmu_init_set_16(ZXIC_UINT32 dev_id, ZXIC_UINT32 etm_ddr_no) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 k = 0; + ZXIC_UINT32 i = 0; + ZXIC_UINT32 j = 0; + ZXIC_UINT32 depth = 2*1024; + ZXIC_UINT32 bank_to_mmu_cfg_map[8] = {0, 1, 2, 3, 4, 5, 6, 7}; + ZXIC_UINT32 qlist_grp0_bank_data[8] = {0, 1, 2, 3, 4, 5, 6, 7}; + ZXIC_UINT32 ddr_no[2] = {(etm_ddr_no>>4)&0xf, etm_ddr_no & 0xf}; + + + DPP_ETM_QMU_QCFG_QLIST_BDEP_T qlist_bdep = {0}; + DPP_ETM_QMU_QCFG_QLIST_BHEAD_T qlist_bhead = {0}; + DPP_ETM_QMU_QCFG_QLIST_BTAIL_T qlist_btail = {0}; + + DPP_ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFG_T active_to_bank_cfg = {0}; + DPP_ETM_QMU_CFGMT_DDR_IN_MMU_CFG_T ddr_in_mmu_cfg = {0}; + DPP_ETM_QMU_CFGMT_DDR_IN_QMU_CFG_T ddr_in_qmu_cfg = {0}; + DPP_ETM_QMU_CFGMT_BANK_TO_MMU_CFG_T bank_to_mmu_cfg = {0}; + DPP_ETM_QMU_CFGMT_BANK_TO_QMU_CFG_T bank_to_qmu_cfg = {0}; + DPP_ETM_QMU_QCFG_QLIST_GRP0_BANK_T qlist_grp0_bank = {0}; + DPP_ETM_QMU_QCFG_QLIST_GRP_T qcfg_qlist_grp = {0}; + + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "========dpp_etm_qmu_init_set_16 start========n"); + + + /* ddr组从qmu到mmu映射,0~1映射成12 */ + for (i = 0; i < 2; i++) + { + ddr_in_mmu_cfg.cfgmt_ddr_in_mmu_cfg = ddr_no[i]; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_DDR_IN_MMU_CFGr, + 0, + i, + &ddr_in_mmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + /* ddr组从mmu到qmu映射,12映射成0~1 */ + for (i = 0; i < 2; i++) + { + ddr_in_qmu_cfg.cfgmt_ddr_in_qmu_cfg = i; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_DDR_IN_QMU_CFGr, + 0, + ddr_no[i], + &ddr_in_qmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + + /* bank号从qmu到mmu映射，每组的bank0~7映射成bank0-7 */ + for (j = 0; j < 2; j++) + { + for (i = 0; i < 8; i++) + { + k = j * 8 + i; + + bank_to_mmu_cfg.cfgmt_bank_in_mmu_cfg = bank_to_mmu_cfg_map[i]; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_BANK_TO_MMU_CFGr, + 0, + k, + &bank_to_mmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + } + + + /* bank号从mmu到qmu映射，每组的bank0-7映射成bank0-7 */ + for (j = 0; j < 2; j++) + { + for (i = 0; i < 8; i++) + { + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, ddr_no[j], 8); + ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(ddr_no[j] * 8, bank_to_mmu_cfg_map[i]); + k = ddr_no[j] * 8 + bank_to_mmu_cfg_map[i]; + + bank_to_qmu_cfg.cfgmt_bank_in_qmu_cfg = i; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_BANK_TO_QMU_CFGr, + 0, + k, + &bank_to_qmu_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + } + + /* random映射ram:配置一个chunk中，bank的轮询顺序 */ + for (i = 0; i < 16; i++) + { + + + active_to_bank_cfg.cfgmt_active_to_bank_cfg = i % 8; + + rc = dpp_reg_write(dev_id, + ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFGr, + 0, + i, + &active_to_bank_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + } + + + /* 首尾深度指针配置 */ + for (j = 0; j < 2; j++) + { + for (i = 0; i < 8; i++) + { + k = j * 8 + i; + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, (j * 8 + i), depth); + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, (j * 8 + i + 1), depth); + qlist_bhead.bank_vld = 1; + qlist_bhead.qcfg_qlist_bhead = (j * 8 + i) * depth; + qlist_btail.qcfg_qlist_btail = ((j * 8 + i + 1) * depth - 1); + qlist_bdep.qcfg_qlist_bdep = depth; + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BHEADr, + 0, + k, + &qlist_bhead); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BTAILr, + 0, + k, + &qlist_btail); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BDEPr, + 0, + k, + &qlist_bdep); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + } + + for (i = 0; i < 64; i++) + { + qlist_bdep.qcfg_qlist_bdep = depth; + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_BDEPr, + 0, + i, + &qlist_bdep); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(ETM_QMU_QCFG_QLIST_GRP0_BANKr, 8); + /* 随机表配置，决定每组bank的轮询顺序 */ + for (j = 0; j < 8; j++) + { + for (i = 0; i < 64; i++) + { + qlist_grp0_bank.qcfg_qlist_grp0_bank_wr = qlist_grp0_bank_data[i % 8]; + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_GRP0_BANKr + j, + 0, + i, + &qlist_grp0_bank); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + } + + for (j = 0; j < 64; j++) + { + qcfg_qlist_grp.qcfg_qlist_grp_wr = j % 2; + rc = dpp_reg_write(dev_id, + ETM_QMU_QCFG_QLIST_GRPr, + 0, + j, + &qcfg_qlist_grp); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + rc = dpp_tm_qmu_cfg_done_set(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_cfg_done_set"); + + ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "========dpp_etm_qmu_init_set_16 END=======\n"); + + return DPP_OK; +} + +/***********************************************************/ +/** QMU初始化配置场景16：独享2组*8bank，MMU实际分配1,2; etm or ftm使用0-7bank +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xuhb @date 2020/12/16 +************************************************************/ +DPP_STATUS dpp_tm_qmu_init_set_16(ZXIC_UINT32 dev_id, ZXIC_UINT32 etm_ddr_no, ZXIC_UINT32 ftm_ddr_no) +{ + DPP_STATUS rc = DPP_OK; + + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, etm_ddr_no, 0, 0xff); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, ftm_ddr_no, 0, 0xff); + ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(dev_id, (1UL<<(etm_ddr_no>>4&0xf)), (1UL<<(etm_ddr_no&0xf))); + ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(dev_id, (1UL<<(ftm_ddr_no>>4&0xf)), (1UL<<(ftm_ddr_no&0xf))); + + /* etm mmu基址配置:ddr1,2组，bank号0-7，bank深度2*1024 */ + //rc = dpp_mmu_bank_base_addr_set(dev_id, ((1UL<<(etm_ddr_no>>4&0xf))+(1UL<<(etm_ddr_no&0xf)))&0x3ff, 0xff, 2*1024); + //ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_mmu_bank_base_addr_set"); + + rc = dpp_etm_qmu_init_set_16(dev_id, etm_ddr_no); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_etm_qmu_init_set_16"); + + return DPP_OK; +} + +#endif +#endif + + +#if ZXIC_REAL("TM_TMMU") + +#if 0 +/***********************************************************/ +/** TMMU TM纯片内模式配置 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param imem_en 1纯片内 +* +* @return +* @remark 说明：高有效，表示使能打开，TMMU不会再发起对MMU的读写操作，用户需要保证Cache PD全部命中。 +* @see +* @author wush @date 2017/10/14 +************************************************************/ +DPP_STATUS dpp_tm_tmmu_imem_en_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 imem_en) +{ + DPP_STATUS rc = DPP_OK; + + DPP_ETM_TMMU_CFGMT_TM_PURE_IMEM_EN_T pure_imem_t = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, imem_en, 0, 1); + + pure_imem_t.cfgmt_tm_pure_imem_en = imem_en; + rc = dpp_reg_write(dev_id, + ETM_TMMU_CFGMT_TM_PURE_IMEM_ENr, + 0, + 0, + &pure_imem_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + return DPP_OK; +} + +/***********************************************************/ +/** TMMU TM纯片内模式配置获取 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_imem_en 1纯片内 +* +* @return +* @remark 无 +* @see +* @author wush @date 2017/10/14 +************************************************************/ +DPP_STATUS dpp_tm_tmmu_imem_en_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_imem_en) +{ + DPP_STATUS rc = DPP_OK; + + DPP_ETM_TMMU_CFGMT_TM_PURE_IMEM_EN_T pure_imem_t = {0}; + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_imem_en); + + rc = dpp_reg_read(dev_id, + ETM_TMMU_CFGMT_TM_PURE_IMEM_ENr, + 0, + 0, + &pure_imem_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + *p_imem_en = pure_imem_t.cfgmt_tm_pure_imem_en; + + return DPP_OK; +} + +/***********************************************************/ +/** TMMU 强制DDR RDY配置 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param ddr_force_rdy 1、如果bit【0】配置为1，则QMU看到的DDR0 RDY一直为1。 + 2、bit【0】代表DDR0，bit【7】代表DDR7。 + 3、纯片内模式需要配置为8'hff，排除DDR干扰。 +* +* @return +* @remark +* @see +* @author wush @date 2017/10/14 +************************************************************/ +DPP_STATUS dpp_tm_tmmu_ddr_force_rdy_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 ddr_force_rdy) +{ + DPP_STATUS rc = DPP_OK; + + DPP_ETM_TMMU_CFGMT_FORCE_DDR_RDY_CFG_T ddr_force_rdy_t = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, ddr_force_rdy, 0, 0x3FF); + + + ddr_force_rdy_t.cfgmt_force_ddr_rdy_cfg = ddr_force_rdy; + rc = dpp_reg_write(dev_id, + ETM_TMMU_CFGMT_FORCE_DDR_RDY_CFGr, + 0, + 0, + &ddr_force_rdy_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + return DPP_OK; +} + +/***********************************************************/ +/** TMMU 强制DDR RDY配置获取 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_ddr_force_rdy 1、如果bit【0】配置为1，则QMU看到的DDR0 RDY一直为1。 + 2、bit【0】代表DDR0，bit【7】代表DDR7。 + 3、纯片内模式需要配置为8'hff，排除DDR干扰。 +* +* @return +* @remark 无 +* @see +* @author wush @date 2017/10/14 +************************************************************/ +DPP_STATUS dpp_tm_tmmu_ddr_force_rdy_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_ddr_force_rdy) +{ + DPP_STATUS rc = DPP_OK; + + DPP_ETM_TMMU_CFGMT_FORCE_DDR_RDY_CFG_T ddr_force_rdy_t = {0}; + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_ddr_force_rdy); + + rc = dpp_reg_read(dev_id, + ETM_TMMU_CFGMT_FORCE_DDR_RDY_CFGr, + 0, + 0, + &ddr_force_rdy_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + *p_ddr_force_rdy = ddr_force_rdy_t.cfgmt_force_ddr_rdy_cfg; + + return DPP_OK; +} + +#endif +#endif + + +#if ZXIC_REAL("TM_CRDT") + +#if 0 +/***********************************************************/ +/** crdt ram初始化 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/03/22 +************************************************************/ +DPP_STATUS dpp_tm_crdt_ram_init(ZXIC_UINT32 dev_id) +{ + + + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 read_times = 0; + DPP_ETM_CRDT_CRDT_CFG_RAM_INIT_T crdt_ram_cfg_init_t = {0}; + DPP_ETM_CRDT_CRDT_STA_RAM_INIT_T crdt_ram_sta_init_t = {0}; + + /**RAM初始化**/ + crdt_ram_cfg_init_t.cfg_ram_init_en = 1; + rc = dpp_reg_write(dev_id, + ETM_CRDT_CRDT_CFG_RAM_INITr, + 0, + 0, + &crdt_ram_cfg_init_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + crdt_ram_sta_init_t.sta_ram_init_en = 1; + rc = dpp_reg_write(dev_id, + ETM_CRDT_CRDT_STA_RAM_INITr, + 0, + 0, + &crdt_ram_sta_init_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + + + /**初始化done确认**/ + do + { + rc = dpp_reg_read(dev_id, + ETM_CRDT_CRDT_CFG_RAM_INITr, + 0, + 0, + &crdt_ram_cfg_init_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + rc = dpp_reg_read(dev_id, + ETM_CRDT_CRDT_STA_RAM_INITr, + 0, + 0, + &crdt_ram_sta_init_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + read_times++; + zxic_comm_usleep(100); + + } + while (0 == crdt_ram_cfg_init_t.cfg_ram_init_done || 0 == crdt_ram_sta_init_t.sta_ram_init_done); + + ZXIC_COMM_PRINT("wait_crdt_ram_done_times=%d\n",read_times); + ZXIC_COMM_PRINT("crdt_ram_cfg_init_t.cfg_ram_init_done=%d, crdt_ram_sta_init_t.sta_ram_init_done=%d\n", + crdt_ram_cfg_init_t.cfg_ram_init_done,crdt_ram_sta_init_t.sta_ram_init_done); + + return DPP_OK; + +} + +#endif +/***********************************************************/ +/** 分配etm-FQ类型调度器资源：fq/fq2/fq4/fq8 个数，(共16K= 16384) +* @param dev_id 设备编号 +* @param fq_num FQ调度器个数，须是8的倍数 +* @param fq2_num FQ2调度器个数，须是4的倍数 +* @param fq4_num FQ4调度器个数，须是2的倍数 +* @param fq8_num FQ8调度器个数 +* 调度器总数不能超过：16K= 16384 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/02/26 +************************************************************/ +DPP_STATUS dpp_etm_crdt_fq_set(DPP_DEV_T *dev, + ZXIC_UINT32 fq_num, + ZXIC_UINT32 fq2_num, + ZXIC_UINT32 fq4_num, + ZXIC_UINT32 fq8_num) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 total_fq_num = 0; + DPP_ETM_CRDT_TH_WFQ_FQ_T etm_crdt_th_wfqfq_t = {0}; + DPP_ETM_CRDT_TH_WFQ2_FQ2_T etm_crdt_th_wfqfq2_t = {0}; + DPP_ETM_CRDT_TH_WFQ4_FQ4_T etm_crdt_th_wfqfq4_t = {0}; + ZXIC_UINT32 th_wfq_fq_index = ETM_CRDT_TH_WFQ_FQr; + ZXIC_UINT32 th_wfq_fq2_index = ETM_CRDT_TH_WFQ2_FQ2r; + ZXIC_UINT32 th_wfq_fq4_index = ETM_CRDT_TH_WFQ4_FQ4r; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + /* 参数合法性检查:fq调度器总数校验 */ + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(DEV_ID(dev), fq2_num , 2); + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(DEV_ID(dev), fq4_num , 4); + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(DEV_ID(dev), fq8_num , 8); + ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(DEV_ID(dev), fq_num , fq2_num * 2); + ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(DEV_ID(dev), fq_num + fq2_num * 2 , fq4_num * 4); + ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(DEV_ID(dev), fq_num + fq2_num * 2 + fq4_num * 4 , fq8_num * 8); + + total_fq_num = (fq_num + fq2_num * 2 + fq4_num * 4 + fq8_num * 8); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), total_fq_num, 0, DPP_ETM_FQ_NUM); + + /* 各调度器数整齐性校验 */ + if ((fq_num != 0 && fq_num % 8 != 0) || (fq2_num != 0 && fq2_num % 4 != 0) || (fq4_num != 0 && fq4_num % 2 != 0)) + { + //ZXIC_COMM__TRACE_ERR("Bad parameter: sp_num or wfq_num %8 != 0 !"); + return DPP_ERR; + } + + + /* 开始调度器阈值配置：th_fq参数配置：th_fq = fq_num/8 */ + rc = dpp_reg_read(dev, + th_wfq_fq_index, + 0, + 0, + &etm_crdt_th_wfqfq_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + etm_crdt_th_wfqfq_t.th_fq = (fq_num / 8); + rc = dpp_reg_write(dev, + th_wfq_fq_index, + 0, + 0, + &etm_crdt_th_wfqfq_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + /* th_fq2参数配置：th_fq2 = (th_fq + fq2_num/4) */ + rc = dpp_reg_read(dev, + th_wfq_fq2_index, + 0, + 0, + &etm_crdt_th_wfqfq2_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + etm_crdt_th_wfqfq2_t.th_fq2 = (etm_crdt_th_wfqfq_t.th_fq + fq2_num / 4); + rc = dpp_reg_write(dev, + th_wfq_fq2_index, + 0, + 0, + &etm_crdt_th_wfqfq2_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + /* th_fq4参数配置：th_fq4 = (th_fq2 + fq4_num/2) */ + rc = dpp_reg_read(dev, + th_wfq_fq4_index, + 0, + 0, + &etm_crdt_th_wfqfq4_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + etm_crdt_th_wfqfq4_t.th_fq4 = (etm_crdt_th_wfqfq2_t.th_fq2 + fq4_num / 2); + rc = dpp_reg_write(dev, + th_wfq_fq4_index, + 0, + 0, + &etm_crdt_th_wfqfq4_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + return DPP_OK; + +} + +/***********************************************************/ +/** 分配TM-SP/WFQ类型调度器资源：sp/wfq/wfq2/wfq4/wfq8 个数，（etm共9K=9216,ftm共1920个） +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param sp_num SP调度器个数，须是8的倍数 +* @param wfq_num WFQ调度器个数，须是8的倍数 +* @param wfq2_num WFQ2调度器个数，须是4的倍数 +* @param wfq4_num WFQ4调度器个数，须是2的倍数 +* @param wfq8_num WFQ8调度器个数 +* 调度器总数不能超过：ETM= 9216; FTM= 1920 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/02/26 +************************************************************/ +DPP_STATUS dpp_tm_crdt_wfqsp_set(DPP_DEV_T *dev, + ZXIC_UINT32 sp_num, + ZXIC_UINT32 wfq_num, + ZXIC_UINT32 wfq2_num, + ZXIC_UINT32 wfq4_num, + ZXIC_UINT32 wfq8_num) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 total_wfqsp_num = 0; + DPP_ETM_CRDT_TH_SP_T etm_crdt_th_sp_t = {0}; + DPP_ETM_CRDT_TH_WFQ_FQ_T etm_crdt_th_wfqfq_t = {0}; + DPP_ETM_CRDT_TH_WFQ2_FQ2_T etm_crdt_th_wfqfq2_t = {0}; + DPP_ETM_CRDT_TH_WFQ4_FQ4_T etm_crdt_th_wfqfq4_t = {0}; + ZXIC_UINT32 th_sp_index = ETM_CRDT_TH_SPr; + ZXIC_UINT32 th_wfq_fq_index = ETM_CRDT_TH_WFQ_FQr; + ZXIC_UINT32 th_wfq_fq2_index = ETM_CRDT_TH_WFQ2_FQ2r; + ZXIC_UINT32 th_wfq_fq4_index = ETM_CRDT_TH_WFQ4_FQ4r; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + /* 参数合法性检查 */ + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(DEV_ID(dev), wfq2_num , 2); + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(DEV_ID(dev), wfq4_num , 4); + ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(DEV_ID(dev), wfq8_num , 8); + ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(DEV_ID(dev), sp_num , wfq_num); + ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(DEV_ID(dev), sp_num + wfq_num , wfq2_num * 2); + ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(DEV_ID(dev), sp_num + wfq_num + wfq2_num * 2 , wfq4_num * 4); + ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(DEV_ID(dev), sp_num + wfq_num + wfq2_num * 2 + wfq4_num * 4 , wfq8_num * 8); + /* 调度器总数校验 */ + total_wfqsp_num = (sp_num + wfq_num + wfq2_num * 2 + wfq4_num * 4 + wfq8_num * 8); + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), total_wfqsp_num, 0, DPP_ETM_WFQSP_NUM); + + /* 各调度器数整齐性校验 */ + if ((sp_num != 0 && sp_num % 8 != 0) || (wfq_num != 0 && wfq_num % 8 != 0) || + (wfq2_num != 0 && wfq2_num % 4 != 0) || (wfq4_num != 0 && wfq4_num % 2 != 0)) + { + ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "Bad parameter: sp_num or wfq_num mod 8 != 0 !\n"); + return DPP_ERR; + } + + th_sp_index = ETM_CRDT_TH_SPr; + th_wfq_fq_index = ETM_CRDT_TH_WFQ_FQr; + th_wfq_fq2_index = ETM_CRDT_TH_WFQ2_FQ2r; + th_wfq_fq4_index = ETM_CRDT_TH_WFQ4_FQ4r; + + /* 开始调度器阈值配置：th_sp参数配置：th_sp= sp_num/8 */ + rc = dpp_reg_read(dev, + th_sp_index, + 0, + 0, + &etm_crdt_th_sp_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + etm_crdt_th_sp_t.th_sp = (sp_num / 8); + rc = dpp_reg_write(dev, + th_sp_index, + 0, + 0, + &etm_crdt_th_sp_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + /* th_wfq参数配置：th_wfq = (th_sp + wfq_num/8) */ + rc = dpp_reg_read(dev, + th_wfq_fq_index, + 0, + 0, + &etm_crdt_th_wfqfq_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + etm_crdt_th_wfqfq_t.th_wfq = (etm_crdt_th_sp_t.th_sp + wfq_num / 8); + rc = dpp_reg_write(dev, + th_wfq_fq_index, + 0, + 0, + &etm_crdt_th_wfqfq_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + /* th_wfq2参数配置：th_wfq2 = (th_wfq + wfq2_num/4) */ + rc = dpp_reg_read(dev, + th_wfq_fq2_index, + 0, + 0, + &etm_crdt_th_wfqfq2_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + etm_crdt_th_wfqfq2_t.th_wfq2 = (etm_crdt_th_wfqfq_t.th_wfq + wfq2_num / 4); + rc = dpp_reg_write(dev, + th_wfq_fq2_index, + 0, + 0, + &etm_crdt_th_wfqfq2_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + /* th_wfq4参数配置：th_wfq4 = (th_wfq2 + wfq4_num/2) */ + rc = dpp_reg_read(dev, + th_wfq_fq4_index, + 0, + 0, + &etm_crdt_th_wfqfq4_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + etm_crdt_th_wfqfq4_t.th_wfq4 = (etm_crdt_th_wfqfq2_t.th_wfq2 + wfq4_num / 2); + rc = dpp_reg_write(dev, + th_wfq_fq4_index, + 0, + 0, + &etm_crdt_th_wfqfq4_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + return DPP_OK; + +} + + +/***********************************************************/ +/** 获取各调度器的起始编号（etm共25K=25600,ftm共1920个） +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_spwfq_start_num 调度器起始编号结构体 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/02/26 +************************************************************/ +DPP_STATUS dpp_tm_crdt_wfqsp_get(DPP_DEV_T *dev, + DPP_TM_CRDT_SPWFQ_START_NUM_T *p_spwfq_start_num) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CRDT_TH_SP_T etm_crdt_th_sp_t = {0}; + DPP_ETM_CRDT_TH_WFQ_FQ_T etm_crdt_th_wfqfq_t = {0}; + DPP_ETM_CRDT_TH_WFQ2_FQ2_T etm_crdt_th_wfqfq2_t = {0}; + DPP_ETM_CRDT_TH_WFQ4_FQ4_T etm_crdt_th_wfqfq4_t = {0}; + ZXIC_UINT32 th_sp_index = ETM_CRDT_TH_SPr; + ZXIC_UINT32 th_wfq_fq_index = ETM_CRDT_TH_WFQ_FQr; + ZXIC_UINT32 th_wfq_fq2_index = ETM_CRDT_TH_WFQ2_FQ2r; + ZXIC_UINT32 th_wfq_fq4_index = ETM_CRDT_TH_WFQ4_FQ4r; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_spwfq_start_num); + + /* 读取调度器阈值配置：th_sp参数配置：th_sp= sp_num/8 */ + rc = dpp_reg_read(dev, + th_sp_index, + 0, + 0, + &etm_crdt_th_sp_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + /* th_wfq阈值读取：th_wfq = (th_sp + wfq_num/8) */ + rc = dpp_reg_read(dev, + th_wfq_fq_index, + 0, + 0, + &etm_crdt_th_wfqfq_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + /* th_wfq2阈值读取：th_wfq2 = (th_wfq + wfq2_num/4) */ + rc = dpp_reg_read(dev, + th_wfq_fq2_index, + 0, + 0, + &etm_crdt_th_wfqfq2_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + /* th_wfq4阈值读取：th_wfq4 = (th_wfq2 + wfq4_num/2) */ + rc = dpp_reg_read(dev, + th_wfq_fq4_index, + 0, + 0, + &etm_crdt_th_wfqfq4_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + /* 各调度器起始编号计算 */ + p_spwfq_start_num->start_num_fq = 0; + p_spwfq_start_num->start_num_fq2 = etm_crdt_th_wfqfq_t.th_fq * 8; + p_spwfq_start_num->start_num_fq4 = etm_crdt_th_wfqfq2_t.th_fq2 * 8; + p_spwfq_start_num->start_num_fq8 = etm_crdt_th_wfqfq4_t.th_fq4 * 8; + p_spwfq_start_num->start_num_sp = DPP_ETM_WFQSP_OFFSET; + p_spwfq_start_num->start_num_wfq = (DPP_ETM_WFQSP_OFFSET + etm_crdt_th_sp_t.th_sp * 8); + p_spwfq_start_num->start_num_wfq2 = (DPP_ETM_WFQSP_OFFSET + etm_crdt_th_wfqfq_t.th_wfq * 8); + p_spwfq_start_num->start_num_wfq4 = (DPP_ETM_WFQSP_OFFSET + etm_crdt_th_wfqfq2_t.th_wfq2 * 8); + p_spwfq_start_num->start_num_wfq8 = (DPP_ETM_WFQSP_OFFSET + etm_crdt_th_wfqfq4_t.th_wfq4 * 8); + + return DPP_OK; + + +} + + +/***********************************************************/ +/** 获取调度器类型 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param se_id 调度器编号 +* @param item_num 调度器中包含的子调度器个数 +* @param sch_type_num 调度器类型编号 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/02/26 +************************************************************/ +DPP_STATUS dpp_tm_crdt_sch_type_get(DPP_DEV_T *dev, ZXIC_UINT32 se_id, ZXIC_UINT32 *item_num, ZXIC_UINT32 *sch_type_num) +{ + DPP_STATUS rc = DPP_OK; + + DPP_TM_CRDT_SPWFQ_START_NUM_T spwfq_start_num_t = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), item_num); + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_id, 0, DPP_ETM_FQSPWFQ_NUM - 1); + + + rc = dpp_tm_crdt_wfqsp_get(dev, &spwfq_start_num_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_crdt_wfqsp_get"); + + + if (se_id < spwfq_start_num_t.start_num_fq2) + { + *item_num = 1; + *sch_type_num = 5; + } + else if (se_id < spwfq_start_num_t.start_num_fq4) + { + *item_num = 2; + *sch_type_num = 6; + } + else if (se_id < spwfq_start_num_t.start_num_fq8) + { + *item_num = 4; + *sch_type_num = 7; + } + else if (se_id < spwfq_start_num_t.start_num_sp) + { + *item_num = 8; + *sch_type_num = 8; + } + else if (se_id < spwfq_start_num_t.start_num_wfq) + { + *item_num = 1; + *sch_type_num = 0; + } + else if (se_id < spwfq_start_num_t.start_num_wfq2) + { + *item_num = 1; + *sch_type_num = 1; + } + else if (se_id < spwfq_start_num_t.start_num_wfq4) + { + *item_num = 2; + *sch_type_num = 2; + } + else if (se_id < spwfq_start_num_t.start_num_wfq8) + { + *item_num = 4; + *sch_type_num = 3; + } + else + { + *item_num = 8; + *sch_type_num = 4; + } + + return DPP_OK; + +} + + +/***********************************************************/ +/** 获取pp->dev挂接关系 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param pp_id 0~63 +* @param p_weight 0~127 +* @param p_sp_mapping 0~7 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cuiy @date 2016/04/20 +************************************************************/ +DPP_STATUS dpp_tm_crdt_pp_para_get(DPP_DEV_T *dev, + ZXIC_UINT32 pp_id, + ZXIC_UINT32 *p_weight, + ZXIC_UINT32 *p_sp_mapping) +{ + DPP_STATUS rc = DPP_OK; + + DPP_ETM_CRDT_PP_CFG_T pp_cfg_r = {0}; + DPP_ETM_CRDT_PP_WEIGHT_T pp_weight_r = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), pp_id, 0, DPP_TM_PP_NUM - 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_weight); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_sp_mapping); + + + rc = dpp_reg_read(dev, + ETM_CRDT_PP_WEIGHTr, + 0, + pp_id, + &pp_weight_r); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + *p_weight = pp_weight_r.pp_weight; + + rc = dpp_reg_read(dev, + ETM_CRDT_PP_CFGr, + 0, + pp_id, + &pp_cfg_r); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + *p_sp_mapping = pp_cfg_r.pp_cfg; + + return DPP_OK; +} + +/***********************************************************/ +/** 配置se->pp->dev挂接关系 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param se_id 往端口挂接的调度器id +* @param pp_id [0-63] +* @param weight [1-511] +* @param sp_mapping [0~8] +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/3/4 +************************************************************/ +DPP_STATUS dpp_tm_crdt_se_pp_link_set(DPP_DEV_T *dev, + ZXIC_UINT32 se_id, + ZXIC_UINT32 pp_id, + ZXIC_UINT32 weight, + ZXIC_UINT32 sp_mapping) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 delay_time = 10; + + DPP_ETM_CRDT_PP_CFG_T pp_cfg = {0}; + DPP_ETM_CRDT_PP_WEIGHT_T pp_weight = {0}; + DPP_ETM_CRDT_PP_CFG_T pp_cfg_r = {0}; + DPP_ETM_CRDT_PP_WEIGHT_T pp_weight_r = {0}; + DPP_TM_SCH_SE_PARA_T sch_se_para_t = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_id, 0, DPP_ETM_FQSPWFQ_NUM - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), pp_id, 0, DPP_TM_PP_NUM - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), weight, 0, DPP_TM_SCH_WEIGHT_MAX); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), sp_mapping, DPP_TM_SCH_SP_0, DPP_TM_SCH_SP_8); + + /* 参数赋值:仅需端口号 ,配置调度器到端口的挂接 */ + sch_se_para_t.se_linkid = DPP_ETM_PORT_LINKID_BASE + pp_id; + + rc = dpp_tm_crdt_se_link_wr(dev, se_id, &sch_se_para_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_crdt_se_link_wr"); + + /* 检测CRDT寄存器是否空闲 */ + rc = dpp_tm_crdt_idle_check(dev); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_crdt_idle_check"); + + pp_weight.pp_weight = weight; + rc = dpp_reg_write(dev, + ETM_CRDT_PP_WEIGHTr, + 0, + pp_id, + &pp_weight); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + /* 写入后，重新读出来校验 */ +#if (ETM_WRITE_CHECK) + { + zxic_comm_delay(delay_time); + rc = dpp_reg_read(dev, + ETM_CRDT_PP_WEIGHTr, + 0, + pp_id, + &pp_weight_r); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + if (pp_weight_r.pp_weight != pp_weight.pp_weight) + { + ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "dpp_tm_crdt_pp_para_set pp[0x%x] wt_pp_weight[0x%x] rd_pp_weight[0x%x]\n", pp_id, pp_weight.pp_weight, pp_weight_r.pp_weight); + return DPP_ERR; + } + } +#endif + + /* 检测CRDT寄存器是否空闲 */ + rc = dpp_tm_crdt_idle_check(dev); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_crdt_idle_check"); + + pp_cfg.pp_cfg = sp_mapping; + rc = dpp_reg_write(dev, + ETM_CRDT_PP_CFGr, + 0, + pp_id, + &pp_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + /* 写入后，重新读出来校验 */ +#if (ETM_WRITE_CHECK) + { + zxic_comm_delay(delay_time); + rc = dpp_reg_read(dev, + ETM_CRDT_PP_CFGr, + 0, + pp_id, + &pp_cfg_r); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + if (pp_cfg_r.pp_cfg != pp_cfg.pp_cfg) + { + ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "dpp_tm_crdt_pp_para_set pp[0x%x] wt_pp_cfg[0x%x] rd_pp_cfg[0x%x]\n", pp_id, pp_cfg.pp_cfg, pp_cfg_r.pp_cfg); + return DPP_ERR; + } + } +#endif + + return DPP_OK; +} + +/***********************************************************/ +/** 配置flow级流队列的挂接关系(flow到上级调度器的挂接) +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param flow_id 流队列号 +* @param c_linkid c桶要挂接到的上级调度器id +* @param c_weight c桶挂接到上级调度器的权重[1~511] +* @param c_sp c桶挂接到上级调度器的sp优先级,有效值[0-8],共9级，优先级依次降低 +* @param mode 挂接模式：0-单桶 1-双桶。配置单桶时无需关注后续参数，配0即可 +* @param e_linkid e桶要挂接到的上级调度器id +* @param e_weight e桶挂接到上级调度器的权重[1~511] +* @param e_sp e桶挂接到上级调度器的sp优先级，有效值[0-8],共9级，优先级依次降低 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/02/27 +************************************************************/ +DPP_STATUS dpp_tm_crdt_flow_link_wr(DPP_DEV_T *dev, + ZXIC_UINT32 flow_id, + DPP_TM_SCH_FLOW_PARA_T *p_flow_para) + +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 flow_id_e = 0; + ZXIC_UINT32 c_linkid; + ZXIC_UINT32 c_weight; + ZXIC_UINT32 c_sp; + ZXIC_UINT32 mode; + ZXIC_UINT32 e_linkid; + ZXIC_UINT32 e_weight; + ZXIC_UINT32 e_sp; + DPP_ETM_CRDT_FLOWQUE_PARA_TBL_T etm_crdt_flow_para_tbl_t = {0}; + + /* 取配置参数 */ + c_linkid = p_flow_para->c_linkid; + c_weight = p_flow_para->c_weight; + c_sp = p_flow_para->c_sp; + mode = p_flow_para->mode; + e_linkid = p_flow_para->e_linkid; + e_weight = p_flow_para->e_weight; + e_sp = p_flow_para->e_sp; + /* 参数校验 */ + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_flow_para); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), c_weight, 0, DPP_TM_SCH_WEIGHT_MAX); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), e_weight, 0, DPP_TM_SCH_WEIGHT_MAX); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), c_sp, 0, DPP_TM_SCH_SP_NUM); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), e_sp, 0, DPP_TM_SCH_SP_NUM); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), mode, 0, 1); + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), flow_id, 0, DPP_ETM_Q_NUM - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), c_linkid, 0, DPP_ETM_FQSPWFQ_NUM - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), e_linkid, 0, DPP_ETM_FQSPWFQ_NUM - 1); + + + /* 开始流级挂接配置 */ + + if (mode == 1) + { + flow_id_e = (flow_id + 0x2400); + } + + /* c桶挂接配置 */ + etm_crdt_flow_para_tbl_t.flowque_link = c_linkid; + etm_crdt_flow_para_tbl_t.flowque_w = c_weight; + etm_crdt_flow_para_tbl_t.flowque_pri = c_sp; + + rc = dpp_reg_write(dev, + ETM_CRDT_FLOWQUE_PARA_TBLr, + 0, + flow_id, + &etm_crdt_flow_para_tbl_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + zxic_comm_delay(5); + + /* mode-1 需要配置双桶挂接 */ + if (mode == 1) + { + /* e桶挂接配置 */ + etm_crdt_flow_para_tbl_t.flowque_link = e_linkid; + etm_crdt_flow_para_tbl_t.flowque_w = e_weight; + etm_crdt_flow_para_tbl_t.flowque_pri = e_sp; + + rc = dpp_reg_write(dev, + ETM_CRDT_FLOWQUE_PARA_TBLr, + 0, + flow_id_e, + &etm_crdt_flow_para_tbl_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + } + + zxic_comm_delay(5); + + return DPP_OK; + + +} + +/***********************************************************/ +/** 配置flow级流队列的挂接关系(flow到上级调度器的挂接) +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param flow_id 流队列号 +* @param c_linkid c桶要挂接到的上级调度器id +* @param c_weight c桶挂接到上级调度器的权重[1~511] +* @param c_sp c桶挂接到上级调度器的sp优先级,有效值[0-8],共9级，优先级依次降低 +* @param mode 挂接模式：0-单桶 1-双桶。配置单桶时无需关注后续参数，配0即可 +* @param e_linkid e桶要挂接到的上级调度器id +* @param e_weight e桶挂接到上级调度器的权重[1~511] +* @param e_sp e桶挂接到上级调度器的sp优先级，有效值[0-8],共9级，优先级依次降低 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/02/27 +************************************************************/ +DPP_STATUS dpp_tm_crdt_flow_link_set(DPP_DEV_T *dev, + ZXIC_UINT32 flow_id, + ZXIC_UINT32 c_linkid, + ZXIC_UINT32 c_weight, + ZXIC_UINT32 c_sp, + ZXIC_UINT32 mode, + ZXIC_UINT32 e_linkid, + ZXIC_UINT32 e_weight, + ZXIC_UINT32 e_sp) +{ + DPP_STATUS rc = DPP_OK; + DPP_TM_SCH_FLOW_PARA_T sch_flow_para_t = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + /* 参数赋值 */ + sch_flow_para_t.c_linkid = c_linkid; + sch_flow_para_t.c_weight = c_weight; + sch_flow_para_t.c_sp = c_sp; + sch_flow_para_t.mode = mode; + sch_flow_para_t.e_linkid = e_linkid; + sch_flow_para_t.e_weight = e_weight; + sch_flow_para_t.e_sp = e_sp; + + rc = dpp_tm_crdt_flow_link_wr(dev, flow_id, &sch_flow_para_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_crdt_flow_link_wr"); + + return DPP_OK; + +} + +/***********************************************************/ +/** 批量配置flow级流队列的挂接关系 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param flow_id_s 起始流队列号 +* @param flow_id_e 终止流队列号 +* @param c_linkid c桶要挂接到的上级调度器id +* @param c_weight c桶挂接到上级调度器的权重[1~511] +* @param c_sp c桶挂接到上级调度器的sp优先级,有效值[0-8],共9级，优先级依次降低 +* @param mode 挂接模式：0-单桶 1-双桶。配置单桶时无需关注后续参数，配0即可 +* @param e_linkid e桶要挂接到的上级调度器id +* @param e_weight e桶挂接到上级调度器的权重[1~511] +* @param e_sp e桶挂接到上级调度器的sp优先级，有效值[0-8],共9级，优先级依次降低 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/02/27 +************************************************************/ +DPP_STATUS dpp_tm_crdt_flow_link_more_set(DPP_DEV_T *dev, + ZXIC_UINT32 flow_id_s, + ZXIC_UINT32 flow_id_e, + ZXIC_UINT32 c_linkid, + ZXIC_UINT32 c_weight, + ZXIC_UINT32 c_sp, + ZXIC_UINT32 mode, + ZXIC_UINT32 e_linkid, + ZXIC_UINT32 e_weight, + ZXIC_UINT32 e_sp) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 flow_id = 0; + DPP_TM_SCH_FLOW_PARA_T sch_flow_para_t = {0}; + ZXIC_COMM_CHECK_POINT(dev); + + + if (flow_id_s > flow_id_e) + { + ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "Bad parameters! flow_id_s > flow_id_e !\n"); + return DPP_ERR; + } + + /* 参数赋值 */ + sch_flow_para_t.c_linkid = c_linkid; + sch_flow_para_t.c_weight = c_weight; + sch_flow_para_t.c_sp = c_sp; + sch_flow_para_t.mode = mode; + sch_flow_para_t.e_linkid = e_linkid; + sch_flow_para_t.e_weight = e_weight; + sch_flow_para_t.e_sp = e_sp; + + for (flow_id = flow_id_s; flow_id <= flow_id_e; flow_id++) + { + rc = dpp_tm_crdt_flow_link_wr(dev, flow_id, &sch_flow_para_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_crdt_flow_link_wr"); + } + + return DPP_OK; + +} + + +/***********************************************************/ +/** 配置调度器层次化QOS的挂接关系:非优先级传递 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param se_id 本级调度器id +* 对于FQX/WFQX必须是调度单元中首个调度器id +* @param se_linkid 要挂接到的上级调度器id +* @param se_weight 挂接到上级调度器的权重[1~511] +* @param se_sp 挂接到上级调度器的sp优先级,有效值[0-8],共9级，优先级依次降低 +* @param se_insw 优先级传递使能：0-关 1-开。该参数不传递直接配0 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/02/27 +************************************************************/ +DPP_STATUS dpp_tm_crdt_se_link_wr(DPP_DEV_T *dev, + ZXIC_UINT32 se_id, + DPP_TM_SCH_SE_PARA_T *p_sch_se_para) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 se_linkid = 0; + ZXIC_UINT32 se_weight = 0; + ZXIC_UINT32 se_sp = 0; + ZXIC_UINT32 se_insw = 0; /* 优先级传递关闭 */ + ZXIC_UINT32 item_num = 0; /* 调度单元中调度器的个数 */ + ZXIC_UINT32 sch_type_num = 0; + ZXIC_UINT32 i = 0; + DPP_ETM_CRDT_SE_PARA_TBL_T etm_crdt_se_para_tbl_t = {0}; + + + /* 取配置参数 */ + se_linkid = p_sch_se_para->se_linkid; + se_weight = p_sch_se_para->se_weight; + se_sp = p_sch_se_para->se_sp; + + + /* 参数校验 */ + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_weight, 0, DPP_TM_SCH_WEIGHT_MAX); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_sp, 0, DPP_TM_SCH_SP_NUM); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_insw, 0, 0); + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_id, 0, DPP_ETM_FQSPWFQ_NUM - 1); + + if (se_linkid > DPP_ETM_FQSPWFQ_NUM) + { + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_linkid, DPP_TM_PP_LINKID_PORT0, DPP_TM_PP_LINKID_PORT63); + } + else + { + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_linkid, 0, DPP_ETM_FQSPWFQ_NUM - 1); + } + + + /* 开始调度器挂接配置 */ + + /* 先区分调度器类型：sp/fq/wfq调度器挂接方式相同，wfqx/fqx=2/4/8是另一种挂接方式 */ + rc = dpp_tm_crdt_sch_type_get(dev, se_id, &item_num, &sch_type_num); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_crdt_sch_type_get"); + + + /* 非优先级传递挂接:各调度器参数须相同 */ + etm_crdt_se_para_tbl_t.se_link = se_linkid; + etm_crdt_se_para_tbl_t.se_w = se_weight; + etm_crdt_se_para_tbl_t.se_pri = se_sp; + etm_crdt_se_para_tbl_t.se_insw = se_insw; + etm_crdt_se_para_tbl_t.cp_token_en = 1; + + for (i = 0; i < item_num; i++) + { + rc = dpp_reg_write(dev, + ETM_CRDT_SE_PARA_TBLr, + 0, + se_id + i, + &etm_crdt_se_para_tbl_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + } + + return DPP_OK; +} + + +/***********************************************************/ +/** 配置调度器层次化QOS的挂接关系:非优先级传递 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param se_id 本级调度器id +* 对于FQX/WFQX必须是调度单元中首个调度器id +* @param se_linkid 要挂接到的上级调度器id +* @param se_weight 挂接到上级调度器的权重[1~511] +* @param se_sp 挂接到上级调度器的sp优先级,有效值[0-8],共9级，优先级依次降低 +* @param se_insw 优先级传递使能：0-关 1-开. 该参数不传递直接配0 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/02/27 +************************************************************/ +DPP_STATUS dpp_tm_crdt_se_link_set(DPP_DEV_T *dev, + ZXIC_UINT32 se_id, + ZXIC_UINT32 se_linkid, + ZXIC_UINT32 se_weight, + ZXIC_UINT32 se_sp) +{ + DPP_STATUS rc = DPP_OK; + DPP_TM_SCH_SE_PARA_T sch_se_para_t = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + /* 参数赋值 */ + sch_se_para_t.se_linkid = se_linkid; + sch_se_para_t.se_weight = se_weight; + sch_se_para_t.se_sp = se_sp; + + rc = dpp_tm_crdt_se_link_wr(dev, se_id, &sch_se_para_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_crdt_se_link_wr"); + + return DPP_OK; +} + +/***********************************************************/ +/** 配置调度器层次化QOS的挂接关系:优先级传递 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param se_id 本级调度器id +* @param se_linkid 要挂接到的上级调度器id +* @param se_sp 挂接到上级调度器的sp优先级,有效值[0-3],最多4级，优先级按调度单元分配， +* 每个调度单元内部调度器优先级相同！ +* @param se_weight0-7 WFQ8中各调度器权重值[1~511]，若是WFQ2/4 只取前面对应值，后面无效 +* @param se_insw 优先级传递使能：0-关 1-开. 该参数不传递直接配1 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/02/27 +************************************************************/ +DPP_STATUS dpp_tm_crdt_se_link_insw_wr(DPP_DEV_T *dev, + ZXIC_UINT32 se_id, + DPP_TM_SCH_SE_PARA_INSW_T *p_sch_se_para_insw) +{ + ZXIC_UINT32 rc = DPP_OK; + ZXIC_UINT32 se_linkid; /** 要挂接到的上级调度器id */ + ZXIC_UINT32 se_sp; /** 挂接到上级调度器的sp优先级,有效值[0-3],共4级，优先级依次降低,优先级按调度单元分配 */ + ZXIC_UINT32 se_weight[8] = {0}; /** WFQ8中各调度器权重值[1~511]，若是WFQ2/4 只取前面对应值，后面无效 */ + ZXIC_UINT32 se_insw = 1; /* 优先级传递开启 */ + ZXIC_UINT32 item_num = 1; /* 调度单元中调度器的个数 */ + ZXIC_UINT32 sch_type_num = 0; + ZXIC_UINT32 item_num_link = 0; /* 上级调度单元中调度器的个数 */ + ZXIC_UINT32 sch_type_num_link = 0; + ZXIC_UINT32 i = 0; + DPP_ETM_CRDT_SE_PARA_TBL_T etm_crdt_se_para_tbl_t = {0}; + + /* 取配置参数 */ + se_linkid = p_sch_se_para_insw->se_linkid; + se_sp = p_sch_se_para_insw->se_sp; + se_weight[0] = p_sch_se_para_insw->se_weight[0]; + se_weight[1] = p_sch_se_para_insw->se_weight[1]; + se_weight[2] = p_sch_se_para_insw->se_weight[2]; + se_weight[3] = p_sch_se_para_insw->se_weight[3]; + se_weight[4] = p_sch_se_para_insw->se_weight[4]; + se_weight[5] = p_sch_se_para_insw->se_weight[5]; + se_weight[6] = p_sch_se_para_insw->se_weight[6]; + se_weight[7] = p_sch_se_para_insw->se_weight[7]; + + + /* 参数校验 */ + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_sp, 0, DPP_TM_SCH_SP_NUM - 5); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_insw, 1, 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_weight[0], 0, DPP_TM_SCH_WEIGHT_MAX); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_weight[1], 0, DPP_TM_SCH_WEIGHT_MAX); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_weight[2], 0, DPP_TM_SCH_WEIGHT_MAX); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_weight[3], 0, DPP_TM_SCH_WEIGHT_MAX); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_weight[4], 0, DPP_TM_SCH_WEIGHT_MAX); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_weight[5], 0, DPP_TM_SCH_WEIGHT_MAX); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_weight[6], 0, DPP_TM_SCH_WEIGHT_MAX); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_weight[7], 0, DPP_TM_SCH_WEIGHT_MAX); + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_id, 0, DPP_ETM_FQSPWFQ_NUM - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_linkid, 0, DPP_ETM_FQSPWFQ_NUM - 1); + + + + /* 开始调度器挂接配置 */ + + /* 先区分调度器类型：sp/fq/wfq调度器挂接方式相同，wfqx/fqx=2/4/8是另一种挂接方式 */ + rc = dpp_tm_crdt_sch_type_get(dev, se_id, &item_num, &sch_type_num); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_crdt_sch_type_get"); + rc = dpp_tm_crdt_sch_type_get(dev, se_linkid, &item_num_link, &sch_type_num_link); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_crdt_sch_type_get"); + + /* 优先级传递挂接合法性检查:下级传入调度器需是首编号，且下级<=上级 */ + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), item_num, 1, 8); + + if (se_id % item_num != 0 || item_num > item_num_link) + { + ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "dpp_tm_crdt_se_link_insw_wr： NOT CORRECT,bad parameters!\n"); + return DPP_ERR; + } + + + /* 优先级传递挂接:各调度器挂接的se_linkid依次递增1,需相邻不能错开 + se_weight不限，取值[1-511] + se_sp:根据下级往上级挂接情况，取值[0-3]，调度单元内部须相同 + se_insw 写死为1 */ + etm_crdt_se_para_tbl_t.se_pri = se_sp; + etm_crdt_se_para_tbl_t.se_insw = se_insw; + etm_crdt_se_para_tbl_t.cp_token_en = 1; + + for (i = 0; i < item_num; i++) + { + etm_crdt_se_para_tbl_t.se_link = (se_linkid + i); + etm_crdt_se_para_tbl_t.se_w = se_weight[i]; + + rc = dpp_reg_write(dev, + ETM_CRDT_SE_PARA_TBLr, + 0, + se_id + i, + &etm_crdt_se_para_tbl_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + } + + return DPP_OK; +} + + +/***********************************************************/ +/** 配置调度器层次化QOS的挂接关系:优先级传递 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param se_id 本级调度器id +* @param se_linkid 要挂接到的上级调度器id +* @param se_weight WFQ2/4/8中各调度器权重值[1~511]，取相等的值 +* @param se_sp 挂接到上级调度器的sp优先级,有效值[0-7],共8级，优先级依次降低 +* @param se_insw 优先级传递使能：0-关 1-开. 该参数不传递直接配1 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/02/27 +************************************************************/ +DPP_STATUS dpp_tm_crdt_se_link_insw_set(DPP_DEV_T *dev, + ZXIC_UINT32 se_id, + ZXIC_UINT32 se_linkid, + ZXIC_UINT32 se_weight, + ZXIC_UINT32 se_sp) +{ + ZXIC_UINT32 rc = DPP_OK; + DPP_TM_SCH_SE_PARA_INSW_T sch_se_para_insw_t = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + /* 参数赋值 */ + sch_se_para_insw_t.se_linkid = se_linkid; + sch_se_para_insw_t.se_sp = se_sp; + sch_se_para_insw_t.se_weight[0] = se_weight; + sch_se_para_insw_t.se_weight[1] = se_weight; + sch_se_para_insw_t.se_weight[2] = se_weight; + sch_se_para_insw_t.se_weight[3] = se_weight; + sch_se_para_insw_t.se_weight[4] = se_weight; + sch_se_para_insw_t.se_weight[5] = se_weight; + sch_se_para_insw_t.se_weight[6] = se_weight; + sch_se_para_insw_t.se_weight[7] = se_weight; + + rc = dpp_tm_crdt_se_link_insw_wr(dev, se_id, &sch_se_para_insw_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_crdt_se_link_insw_wr"); + + return DPP_OK; + + +} + + +/***********************************************************/ +/** 配置调度器层次化QOS的挂接关系:优先级传递,单个调度器挂接 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param se_id 本级调度器id +* @param se_linkid 要挂接到的上级调度器id +* @param se_weight WFQ8中对应调度器权重值[1~511] +* @param se_sp 挂接到上级调度器的sp优先级,有效值[0-7],共8级，优先级依次降低 +* @param se_insw 优先级传递使能：0-关 1-开. 该参数不传递直接配1 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/02/27 +************************************************************/ +DPP_STATUS dpp_tm_crdt_se_link_insw_single_set(DPP_DEV_T *dev, + ZXIC_UINT32 se_id, + ZXIC_UINT32 se_linkid, + ZXIC_UINT32 se_weight, + ZXIC_UINT32 se_sp) +{ + ZXIC_UINT32 rc = DPP_OK; + ZXIC_UINT32 se_insw = 1; /* 优先级传递开启 */ + DPP_ETM_CRDT_SE_PARA_TBL_T etm_crdt_se_para_tbl_t = {0}; + + + /* 参数校验 */ + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_sp, 0, DPP_TM_SCH_SP_NUM - 5); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_insw, 1, 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_weight, 0, DPP_TM_SCH_WEIGHT_MAX); + + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_id, 0, DPP_ETM_FQSPWFQ_NUM - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_linkid, 0, DPP_ETM_FQSPWFQ_NUM - 1); + + + /* 开始调度器挂接配置 */ + + /* 优先级传递挂接:各调度器挂接的se_linkid依次递增1,需相邻不能错开 + se_weight不限，取值[1-511] + se_sp:根据下级往上级挂接情况，取值[0-3]，调度单元内部须相同 + se_insw 写死为1 */ + etm_crdt_se_para_tbl_t.se_pri = se_sp; + etm_crdt_se_para_tbl_t.se_insw = se_insw; + etm_crdt_se_para_tbl_t.cp_token_en = 1; + etm_crdt_se_para_tbl_t.se_link = se_linkid; + etm_crdt_se_para_tbl_t.se_w = se_weight; + + rc = dpp_reg_write(dev, + ETM_CRDT_SE_PARA_TBLr, + 0, + se_id, + &etm_crdt_se_para_tbl_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + + return DPP_OK; + + +} + +/***********************************************************/ +/** 获取调度器挂接配置参数 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param se_id 调度器编号 +* @param p_se_para_tbl 调度器参数 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/02/27 +************************************************************/ +DPP_STATUS dpp_tm_crdt_se_para_get(DPP_DEV_T *dev, ZXIC_UINT32 se_id, DPP_ETM_CRDT_SE_PARA_TBL_T *p_se_para_tbl) +{ + DPP_STATUS rc = DPP_OK; + + /* 参数校验 */ + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_se_para_tbl); + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_id, 0, DPP_ETM_FQSPWFQ_NUM - 1); + + rc = dpp_reg_read(dev, + ETM_CRDT_SE_PARA_TBLr, + 0, + se_id, + p_se_para_tbl); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + return DPP_OK; + +} + + + +/***********************************************************/ +/** 获取流队列入链状态 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param flow_id 流队列号 +* @param link_state 0-未入链 1-在调度器链表中 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/02/27 +************************************************************/ +DPP_STATUS dpp_tm_crdt_flow_link_state_get(DPP_DEV_T *dev, ZXIC_UINT32 flow_id, ZXIC_UINT32 *link_state) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CRDT_FLOWQUE_INS_TBL_T crdt_flow_ins_tbl_t = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), link_state); + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), flow_id, 0, DPP_ETM_CRDT_NUM); + + rc = dpp_reg_read(dev, + ETM_CRDT_FLOWQUE_INS_TBLr, + 0, + flow_id, + &crdt_flow_ins_tbl_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + *link_state = crdt_flow_ins_tbl_t.flowque_ins; + + return DPP_OK; + +} + +/***********************************************************/ +/** 获取调度器入链状态 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param se_id 调度器编号 +* @param link_state 0-未入链 1-在调度器链表中 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/02/27 +************************************************************/ +DPP_STATUS dpp_tm_crdt_se_link_state_get(DPP_DEV_T *dev, ZXIC_UINT32 se_id, ZXIC_UINT32 *link_state) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CRDT_SE_INS_TBL_T crdt_se_ins_tbl_t = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), link_state); + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_id, 0, DPP_ETM_FQSPWFQ_NUM - 1); + + rc = dpp_reg_read(dev, + ETM_CRDT_SE_INS_TBLr, + 0, + se_id, + &crdt_se_ins_tbl_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + *link_state = crdt_se_ins_tbl_t.se_ins_flag; + + return DPP_OK; + +} + +/***********************************************************/ +/** 判断crdt流删除命令是否空闲 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/02/27 +************************************************************/ +DPP_STATUS dpp_tm_crdt_del_cmd_idle(DPP_DEV_T *dev) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 read_times = 30; + DPP_ETM_CRDT_FLOW_DEL_CMD_T crdt_del_cmd_busy = {0}; + ZXIC_COMM_CHECK_POINT(dev); + + do + { + rc = dpp_reg_read(dev, + ETM_CRDT_FLOW_DEL_CMDr, + 0, + 0, + &crdt_del_cmd_busy); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + read_times--; + zxic_comm_delay(5); + } + while ((0 != (crdt_del_cmd_busy.flow_del_busy)) && (read_times > 0)); + + if (0 == read_times) + { + ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "CRDT Del command busy!\n"); + return DPP_ERR; + } + + return DPP_OK; + +} + +/***********************************************************/ +/** 删除流/调度器挂接关系(调度器编号非从0开始，需要偏移) +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param id 要删除的流号或调度器id +* ETM范围:0--0xABFF; FTM范围:0-0x177F +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/02/27 +************************************************************/ +DPP_STATUS dpp_tm_crdt_del_link_set(DPP_DEV_T *dev, ZXIC_UINT32 id) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 c_sta = 0; + ZXIC_UINT32 e_sta = 0; + ZXIC_UINT32 flow_e = 0; + ZXIC_UINT32 link_state = 0; /*流或调度器入链状态*/ + ZXIC_UINT32 read_times = 300; + ZXIC_UINT32 crdt_del_cmd_reg_index = 0; + DPP_ETM_CRDT_FLOW_DEL_CMD_T crdt_del_cmd_t = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id, 0, DPP_ETM_SCH_DEL_NUM); + flow_e = DPP_ETM_Q_NUM; + + /* 循环判断入链状态是否为1 */ + do + { + + /* 判断当前流或调度器入链状态：非入链情况才能删除挂接 */ + if (id <= DPP_ETM_CRDT_NUM) + { + /* 流入链状态 */ + rc = dpp_tm_crdt_flow_link_state_get(dev, id, &c_sta); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_crdt_flow_link_state_get"); + + rc = dpp_tm_crdt_flow_link_state_get(dev, id + DPP_ETM_Q_NUM, &e_sta); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_crdt_flow_link_state_get"); + + link_state = c_sta || e_sta; + } + else + { + /*调度器入链状态*/ + rc = dpp_tm_crdt_se_link_state_get(dev, id - DPP_ETM_SHAP_SEID_BASE, &link_state); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_crdt_se_link_state_get"); + + } + + if (0 == link_state) + { + break; + } + read_times--; + zxic_comm_delay(1); + } + while (read_times > 0); + + if (read_times == 0) + { + ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(id, flow_e); + ZXIC_COMM_TRACE_ERROR("id: 0x%08x ins_flag is always 1 (Maybe it's because cir equal zero) !!!\n", id); + /*此时要 继续往下走，执行强删！如果不删除队列没释放下次直接覆写问题更严重。zhaoyan*/ + } + + /*删挂接命令是否空闲*/ + rc = dpp_tm_crdt_del_cmd_idle(dev); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_crdt_del_cmd_idle"); + + + /*进行流或调度器删除操作*/ + crdt_del_cmd_reg_index = ETM_CRDT_FLOW_DEL_CMDr; + crdt_del_cmd_t.flow_alt_cmd = 1; + crdt_del_cmd_t.flow_alt_ind = id; + + /* 流删除：如果删除c桶，需要同时删除e桶 */ + if (id < DPP_ETM_Q_NUM) + { + rc = dpp_reg_write(dev, + crdt_del_cmd_reg_index, + 0, + 0, + &crdt_del_cmd_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + /*删挂e桶：判断命令是否空闲*/ + rc = dpp_tm_crdt_del_cmd_idle(dev); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_crdt_del_cmd_idle"); + crdt_del_cmd_t.flow_alt_ind = (id + DPP_ETM_Q_NUM); + rc = dpp_reg_write(dev, + crdt_del_cmd_reg_index, + 0, + 0, + &crdt_del_cmd_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + } + else + { + + rc = dpp_reg_write(dev, + crdt_del_cmd_reg_index, + 0, + 0, + &crdt_del_cmd_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + } + + return DPP_OK; +} + +/***********************************************************/ +/** 删除调度器挂接关系(调度器编号从0开始)：对外API +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param se_id_s 要删除的起始调度器id +* @param se_id_e 要删除的终止调度器id +* ETM范围:0--0x63FF; FTM范围:0-0x77F +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/02/27 +************************************************************/ +DPP_STATUS dpp_tm_crdt_del_se_link_set(DPP_DEV_T *dev, ZXIC_UINT32 id_s, ZXIC_UINT32 id_e) +{ + + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 se_id_offset = 0; + ZXIC_UINT32 id = 0 ; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id_s, 0, DPP_ETM_FQSPWFQ_NUM - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id_e, 0, DPP_ETM_FQSPWFQ_NUM - 1); + se_id_offset = DPP_ETM_SHAP_SEID_BASE; + + if (id_s > id_e) + { + ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "Bad parameters! id_s > id_e!\n"); + return DPP_ERR; + } + + for (id = id_s; id <= id_e; id++) + { + ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(DEV_ID(dev), id , se_id_offset); + rc = dpp_tm_crdt_del_link_set(dev, id + se_id_offset); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_crdt_del_link_set"); + } + + + return DPP_OK; + +} + + +/***********************************************************/ +/** 删除流挂接关系：对外API +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param id_s 要删除的流号或调度器起始id +* @param id_e 要删除的流号或调度器终止id +* ETM范围:0--0x47FF; FTM范围:0-0xFFF +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/02/27 +************************************************************/ +DPP_STATUS dpp_tm_crdt_del_flow_link_set(DPP_DEV_T *dev, ZXIC_UINT32 id_s, ZXIC_UINT32 id_e) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 id = 0; + ZXIC_UINT32 q_td_th = 0; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id_s, 0, DPP_ETM_CRDT_NUM); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id_e, 0, DPP_ETM_CRDT_NUM); + + if (id_s > id_e) + { + ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "Bad parameters! id_s > id_e !\n"); + return DPP_ERR; + } + + for (id = id_s; id <= id_e; id++) + { + rc = dpp_tm_cgavd_td_th_get(dev, QUEUE_LEVEL, id, &q_td_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_cgavd_td_th_get"); + + if (q_td_th != 0) + { + ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "queue TD_TH is not equal 0 ! q_td_th != 0 !\n"); + return DPP_ERR; + } + } + + for (id = id_s; id <= id_e; id++) + { + rc = dpp_tm_crdt_del_link_set(dev, id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_crdt_del_link_set"); + } + + return DPP_OK; +} + +#if 0 +/***********************************************************/ +/** 配置授权分发使能或者关闭 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param en 配置的值，0-关闭授权分发，1-使能授权分发 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/25 +************************************************************/ +DPP_STATUS dpp_tm_crdt_credit_en_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 en) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CRDT_CREDIT_EN_T credit_en = {0}; + + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, en, 0, 1); + + credit_en.credit_en = en; + rc = dpp_reg_write(dev_id, + ETM_CRDT_CREDIT_ENr, + 0, + 0, + &credit_en); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + return DPP_OK; +} + +/***********************************************************/ +/** 读取授权分发使能或者关闭 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_en 读出的值，0-关闭授权分发，1-使能授权分发 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/25 +************************************************************/ +DPP_STATUS dpp_tm_crdt_credit_en_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_en) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CRDT_CREDIT_EN_T credit_en = {0}; + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_en); + + *p_en = 0xffffffff; + rc = dpp_reg_read(dev_id, + ETM_CRDT_CREDIT_ENr, + 0, + 0, + &credit_en); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + *p_en = credit_en.credit_en; + + return DPP_OK; +} + +/***********************************************************/ +/** 配置授权产生间隔 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param crdt_space_choose 授权发送间隔 0:固定16个周期 1：查表 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/03/10 +************************************************************/ +DPP_STATUS dpp_tm_crdt_space_choose_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 crdt_space_choose) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CRDT_CREDIT_SPACE_SELECT_T space_select = {0}; + + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, crdt_space_choose, 0, 1); + + space_select.credit_space_select = crdt_space_choose; + + rc = dpp_reg_write(dev_id, + ETM_CRDT_CREDIT_SPACE_SELECTr, + 0, + 0, + &space_select); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + return DPP_OK; +} + +/***********************************************************/ +/** 获得授权产生间隔 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param crdt_space_choose 授权发送间隔 0:固定16个周期 1：查表 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/03/10 +************************************************************/ +DPP_STATUS dpp_tm_crdt_space_choose_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_crdt_space_choose) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CRDT_CREDIT_SPACE_SELECT_T space_select = {0}; + + + rc = dpp_reg_read(dev_id, + ETM_CRDT_CREDIT_SPACE_SELECTr, + 0, + 0, + &space_select); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + *p_crdt_space_choose = space_select.credit_space_select; + + return DPP_OK; +} + +#endif +/***********************************************************/ +/** 配置端口拥塞令牌桶使能 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param port_id 端口号：0~63 +* @param port_en 端口拥塞令牌桶使能，1表示不使用拥塞令牌桶的授权，0表示可以使用拥塞令牌桶授权 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author taq @date 2015/03/11 +************************************************************/ +DPP_STATUS dpp_tm_crdt_port_congest_en_set(DPP_DEV_T *dev, + ZXIC_UINT32 port_id, + ZXIC_UINT32 port_en) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 value = 0; + DPP_ETM_CRDT_CONGEST_TOKEN_DISABLE_31_0_T disable_31_0 = {0}; + DPP_ETM_CRDT_CONGEST_TOKEN_DISABLE_63_32_T disable_63_32 = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), port_id, 0, DPP_TM_PP_NUM - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), port_en, 0, 1); + + if (port_id <= 31) + { + /* port_id:[0-31] */ + rc = dpp_reg_read(dev, + ETM_CRDT_CONGEST_TOKEN_DISABLE_31_0r, + 0, + 0, + &disable_31_0); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + value = disable_31_0.congest_token_disable_31_0; + + if (port_en == 0) + { + value = value & (~(1u << port_id)); + } + else + { + value = value | (1u << port_id); + } + + disable_31_0.congest_token_disable_31_0 = value; + + rc = dpp_reg_write(dev, + ETM_CRDT_CONGEST_TOKEN_DISABLE_31_0r, + 0, + 0, + &disable_31_0); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + } + else + { + /* port_id:[32-63] */ + rc = dpp_reg_read(dev, + ETM_CRDT_CONGEST_TOKEN_DISABLE_63_32r, + 0, + 0, + &disable_63_32); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + value = disable_63_32.congest_token_disable_63_32; + + if (port_en == 0) + { + value = value & (~(1u << (port_id - 32))); + } + else + { + value = value | (1u<< (port_id - 32)); + } + + disable_63_32.congest_token_disable_63_32 = value; + + rc = dpp_reg_write(dev, + ETM_CRDT_CONGEST_TOKEN_DISABLE_63_32r, + 0, + 0, + &disable_63_32); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + } + + return DPP_OK; +} + +/***********************************************************/ +/** 获得端口拥塞令牌桶使能 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param port_id 端口号：0~120 +* @param p_port_en 端口拥塞令牌桶使能，1表示不使用拥塞令牌桶的授权，0表示可以使用拥塞令牌桶授权 +* +* @return +* @remark 无 +* @see +* @author djf @date 2015/03/11 +************************************************************/ +DPP_STATUS dpp_tm_crdt_port_congest_en_get(DPP_DEV_T *dev, + ZXIC_UINT32 port_id, + ZXIC_UINT32 *p_port_en) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 value = 0; + DPP_ETM_CRDT_CONGEST_TOKEN_DISABLE_31_0_T disable_31_0 = {0}; + DPP_ETM_CRDT_CONGEST_TOKEN_DISABLE_63_32_T disable_63_32 = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), port_id, 0, DPP_TM_PP_NUM - 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_port_en); + + if (port_id <= 31) + { + /* port_id:[0-31] */ + rc = dpp_reg_read(dev, + ETM_CRDT_CONGEST_TOKEN_DISABLE_31_0r, + 0, + 0, + &disable_31_0); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + value = disable_31_0.congest_token_disable_31_0; + + *p_port_en = 1 & (value >> port_id); + } + else + { + /* port_id:[32-63] */ + rc = dpp_reg_read(dev, + ETM_CRDT_CONGEST_TOKEN_DISABLE_63_32r, + 0, + 0, + &disable_63_32); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + value = disable_63_32.congest_token_disable_63_32; + + *p_port_en = 1 & (value >> (port_id - 32)); + } + + return DPP_OK; +} + + +/***********************************************************/ +/** CRDT 模块 读写是否超时检查:只有端口sp优先级的配置需检测cfg_state的状态 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* +* @return DPP_OK-空闲，DPP_ERR-忙 +* @remark 无 +* @see +* @author szq @date 2015/05/26 +************************************************************/ +DPP_STATUS dpp_tm_crdt_idle_check(DPP_DEV_T *dev) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 read_times = 30; + DPP_ETM_CRDT_CFG_STATE_T is_idle_flag = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + + do + { + rc = dpp_reg_read(dev, + ETM_CRDT_CFG_STATEr, + 0, + 0, + &is_idle_flag); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + read_times--; + zxic_comm_delay(5); + + } + while ((1 == is_idle_flag.cfg_state) && (read_times > 0)); + + if (0 == read_times) + { + ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "crdt rw time out\n"); + return DPP_ERR; + } + + return DPP_OK; +} + +#if 0 +/***********************************************************/ +/** 授权个数统计寄存器清零 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author taq @date 2015/06/19 +************************************************************/ +DPP_STATUS dpp_tm_crdt_clr_diag(ZXIC_UINT32 dev_id) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CRDT_CNT_CLR_T cnt_clr = {0}; + + /* 不使能CRDT */ + rc = dpp_tm_crdt_credit_en_set(dev_id, 0); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_crdt_credit_en_set"); + + /* 清零所有的授权数统计寄存器 */ + cnt_clr.cnt_clr = 1; + rc = dpp_reg_write(dev_id, + ETM_CRDT_CNT_CLRr, + 0, + 0, + &cnt_clr); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + /* 保持所有的授权数统计寄存器值 */ + cnt_clr.cnt_clr = 0; + rc = dpp_reg_write(dev_id, + ETM_CRDT_CNT_CLRr, + 0, + 0, + &cnt_clr); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + /* 使能CRDT */ + rc = dpp_tm_crdt_credit_en_set(dev_id, 1); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_crdt_credit_en_set"); + + return DPP_OK; +} + + + +/***********************************************************/ +/** 打印各级及指定被统计的第0~15个授权流得到的授权个数 stm模式下使用 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author yjd @date 2015/06/19 +************************************************************/ +DPP_STATUS dpp_tm_crdt_ackcnt_diag(ZXIC_UINT32 dev_id, ZXIC_UINT32 delay_ms) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 credit_value = 0; + ZXIC_UINT32 flow_spec_id_offset = 0; + ZXIC_FLOAT traffic_amplified = 0.0; + ZXIC_FLOAT flow_spec_traffic = 0.0; + + DPP_ETM_CRDT_DEV_CREDIT_CNT_T dev_crdit_cnt = {0}; + //DPP_ETM_CRDT_PP_CREDIT_CNT_T pp_crdit_cnt = {0}; + + DPP_ETM_CRDT_STAT_QUE_ID_0_T stat_que_id_0 = {0}; + DPP_ETM_CRDT_STAT_QUE_CREDIT_T que_credit = {0}; + + rc = dpp_tm_crdt_clr_diag(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_crdt_clr_diag"); + zxic_comm_sleep(delay_ms); + + + /* dev级接收到的授权总数 */ + rc = dpp_reg_read(dev_id, + ETM_CRDT_DEV_CREDIT_CNTr, + 0, + 0, + &dev_crdit_cnt); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + /* pp级接收到的授权总数 + rc = dpp_reg_read(dev_id, + ETM_CRDT_PP_CREDIT_CNTr, + 0, + 0, + &pp_crdit_cnt); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); */ + + + /* 读取credit_value */ + rc = dpp_tm_qmu_credit_value_get(dev_id, &credit_value); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_credit_value_get"); + + traffic_amplified = ((ZXIC_FLOAT)delay_ms * (ZXIC_FLOAT)(1000000.0)) / ((ZXIC_FLOAT)(8.0) * (ZXIC_FLOAT)(credit_value)); + ZXIC_COMM_PRINT("dev: ack_cnt = 0x%08x, traffic = %.6f.(Gb)\n", dev_crdit_cnt.dev_credit_cnt, (ZXIC_FLOAT)(dev_crdit_cnt.dev_credit_cnt) / traffic_amplified); + //ZXIC_COMM_PRINT("pp: ack_cnt = 0x%08x, traffic = %.6f.(G)\n", pp_crdit_cnt.pp_credit_cnt, (ZXIC_FLOAT)(pp_crdit_cnt.pp_credit_cnt) / traffic_amplified); + + for (flow_spec_id_offset = 0; flow_spec_id_offset < 16; flow_spec_id_offset++) + { + rc = dpp_reg_read(dev_id, + ETM_CRDT_STAT_QUE_ID_0r + flow_spec_id_offset, + 0, + 0, + &stat_que_id_0); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + rc = dpp_reg_read(dev_id, + ETM_CRDT_STAT_QUE_CREDITr, + 0, + flow_spec_id_offset, + &que_credit); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + flow_spec_traffic = (ZXIC_FLOAT)(que_credit.stat_que_credit_cnt) / traffic_amplified; + + ZXIC_COMM_PRINT("flow_0x%04x(%5d): ", (stat_que_id_0.stat_que_id_0 & 0xffff), (stat_que_id_0.stat_que_id_0 & 0xffff)); + ZXIC_COMM_PRINT("ack_cnt = 0x%08x, ", que_credit.stat_que_credit_cnt); + ZXIC_COMM_PRINT("traffic = %.6f.(Gb)\n", flow_spec_traffic); + + } + + + return DPP_OK; +} + +/***********************************************************/ +/** +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param que_id queue id +* @param en 1:过滤E桶队列CRS状态为SLOW的入链请求；0:E桶队列CRS SLOW正常入链； +* +* @return +* @remark 无 +* @see +* @author XXX @date 2019/05/08 +************************************************************/ +DPP_STATUS dpp_tm_crdt_eir_crs_filter_en_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 que_id, ZXIC_UINT32 en) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CRDT_EIR_CRS_FILTER_TBL_T eir_crs_filter = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, en, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, que_id, 0, DPP_ETM_Q_NUM - 1); + + eir_crs_filter.eir_crs_filter = en; + rc = dpp_reg_write(dev_id, + ETM_CRDT_EIR_CRS_FILTER_TBLr, + 0, + que_id, + &eir_crs_filter); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + return rc; +} + +/***********************************************************/ +/** +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param que_id_s 起始队列号 +* @param que_id_e 终止队列号 +* @param en 1:过滤E桶队列CRS状态为SLOW的入链请求；0:E桶队列CRS SLOW正常入链； +* +* @return +* @remark 无 +* @see +* @author XXX @date 2019/05/08 +************************************************************/ +DPP_STATUS dpp_tm_crdt_eir_crs_filter_en_more_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 que_id_s, ZXIC_UINT32 que_id_e, ZXIC_UINT32 en) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 i = 0; + + if (que_id_s > que_id_e) + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "Bad parameters! que_id_s > que_id_e !\n"); + return DPP_ERR; + } + + for (i = que_id_s; i <= que_id_e; i++) + { + rc = dpp_tm_crdt_eir_crs_filter_en_set(dev_id, i, en); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_crdt_eir_crs_filter_en_set"); + } + + return DPP_OK; +} + + +/***********************************************************/ +/** +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param que_id queue id +* @param p_en +* +* @return +* @remark 无 +* @see +* @author XXX @date 2019/05/08 +************************************************************/ +DPP_STATUS dpp_tm_crdt_eir_crs_filter_en_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 que_id, ZXIC_UINT32 *p_en) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CRDT_EIR_CRS_FILTER_TBL_T eir_crs_filter = {0}; + + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_en); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, que_id, 0, DPP_ETM_Q_NUM - 1); + + rc = dpp_reg_read(dev_id, + ETM_CRDT_EIR_CRS_FILTER_TBLr, + 0, + que_id, + &eir_crs_filter); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + *p_en = eir_crs_filter.eir_crs_filter; + + return rc; +} + + +/***********************************************************/ +/**cpu配置flow_id的crs强制为normal或者off开关使能，用于检测SA模式下队列到授权流的多对一问题 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param flow_id:流号(和授权流号一一对应) +* en 强制配置crs的使能，0-不使能，1-使能 +* crs_value:强制配置crs的值2'b00:off; 2'b01:low; 2'b10:normal； +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cuiy @date 2016/04/25 +************************************************************/ +DPP_STATUS dpp_tm_crdt_crs_sheild_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 flow_id, ZXIC_UINT32 en, ZXIC_UINT32 crs_value) +{ + DPP_STATUS rc = DPP_OK; + + DPP_ETM_CRDT_CRS_SHEILD_FLOW_ID_CFG_T crs_sheild_flow_id_cfg = {0}; + DPP_ETM_CRDT_CRS_SHEILD_EN_CFG_T crs_sheild_en_cfg = {0}; + DPP_ETM_CRDT_CRS_SHEILD_VALUE_CFG_T crs_sheild_value_cfg = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, en, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, crs_value, 0, 2); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, flow_id, 0, DPP_ETM_Q_NUM - 1); + + + crs_sheild_flow_id_cfg.crs_sheild_flow_id_cfg = flow_id; + rc = dpp_reg_write(dev_id, + ETM_CRDT_CRS_SHEILD_FLOW_ID_CFGr, + 0, + 0, + &crs_sheild_flow_id_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + crs_sheild_en_cfg.crs_sheild_en_cfg = en; + rc = dpp_reg_write(dev_id, + ETM_CRDT_CRS_SHEILD_EN_CFGr, + 0, + 0, + &crs_sheild_en_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + crs_sheild_value_cfg.crs_sheild_value_cfg = crs_value; + rc = dpp_reg_write(dev_id, + ETM_CRDT_CRS_SHEILD_VALUE_CFGr, + 0, + 0, + &crs_sheild_value_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + return DPP_OK; +} + + +/***********************************************************/ +/**获取flow_id的crs强制为normal或者off开关使能，用于检测SA模式下队列到授权流的多对一问题 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param flow_id:流号(和授权流号一一对应) +* en 强制配置crs的使能，0-不使能，1-使能 +* crs_value:强制配置crs的值2'b00:off; 2'b01:low; 2'b10:normal； +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cuiy @date 2016/04/25 +************************************************************/ +DPP_STATUS dpp_tm_crdt_crs_sheild_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_flow_id, ZXIC_UINT32 *p_en, ZXIC_UINT32 *p_crs_value) +{ + DPP_STATUS rc = DPP_OK; + + DPP_ETM_CRDT_CRS_SHEILD_FLOW_ID_CFG_T crs_sheild_flow_id_cfg = {0}; + DPP_ETM_CRDT_CRS_SHEILD_EN_CFG_T crs_sheild_en_cfg = {0}; + DPP_ETM_CRDT_CRS_SHEILD_VALUE_CFG_T crs_sheild_value_cfg = {0}; + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_flow_id); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_en); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_crs_value); + + rc = dpp_reg_read(dev_id, + ETM_CRDT_CRS_SHEILD_FLOW_ID_CFGr, + 0, + 0, + &crs_sheild_flow_id_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + *p_flow_id = crs_sheild_flow_id_cfg.crs_sheild_flow_id_cfg; + + rc = dpp_reg_read(dev_id, + ETM_CRDT_CRS_SHEILD_EN_CFGr, + 0, + 0, + &crs_sheild_en_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + *p_en = crs_sheild_en_cfg.crs_sheild_en_cfg; + + rc = dpp_reg_read(dev_id, + ETM_CRDT_CRS_SHEILD_VALUE_CFGr, + 0, + 0, + &crs_sheild_value_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + *p_crs_value = crs_sheild_value_cfg.crs_sheild_value_cfg; + + return DPP_OK; +} + +/***********************************************************/ +/** 控制授权速率的门限 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param index 0~6 +* @param rci_grade_th_0_data +* +* @return +* @remark 无 +* @see +* @author wush @date 2017/10/17 +************************************************************/ +DPP_STATUS dpp_tm_crdt_rci_grade_th_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 index, ZXIC_UINT32 rci_grade_th_0_data) +{ + DPP_STATUS rc = DPP_OK; + + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, index, 0, 6); + + rc = dpp_reg_write(dev_id, + ETM_CRDT_RCI_GRADE_TH_0_CFGr + index, + 0, + 0, + &rci_grade_th_0_data); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + return DPP_OK; +} + + +DPP_STATUS dpp_tm_crdt_rci_grade_th_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 index, ZXIC_UINT32 *p_rci_grade_th_0_data) +{ + DPP_STATUS rc = DPP_OK; + + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, index, 0, 6); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_rci_grade_th_0_data); + + rc = dpp_reg_read(dev_id, + ETM_CRDT_RCI_GRADE_TH_0_CFGr + index, + 0, + 0, + p_rci_grade_th_0_data); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + return DPP_OK; +} + +/***********************************************************/ +/** 控制授权间隔的门限，建议大于等于0XF，不可取0； +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param index 0~7 +* @param asm_interval_0_data 控制授权间隔的门限，建议大于等于0XF，不可取0； +* +* @return +* @remark 无 +* @see +* @author wush @date 2017/10/17 +************************************************************/ +DPP_STATUS dpp_tm_crdt_asm_interval_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 index, ZXIC_UINT32 asm_interval_0_data) +{ + DPP_STATUS rc = DPP_OK; + + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, index, 0, 7); + + rc = dpp_reg_write(dev_id, + ETM_CRDT_ASM_INTERVAL_0_CFGr + index, + 0, + 0, + &asm_interval_0_data); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + + return DPP_OK; +} + +DPP_STATUS dpp_tm_crdt_asm_interval_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 index, ZXIC_UINT32 *p_asm_interval_0_data) +{ + DPP_STATUS rc = DPP_OK; + + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, index, 0, 7); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_asm_interval_0_data); + + rc = dpp_reg_read(dev_id, + ETM_CRDT_ASM_INTERVAL_0_CFGr + index, + 0, + 0, + p_asm_interval_0_data); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + return DPP_OK; +} + +/***********************************************************/ +/** rci的级别 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_rci_grade_data +* +* @return +* @remark 无 +* @see +* @author wush @date 2017/10/17 +************************************************************/ +DPP_STATUS dpp_tm_crdt_rci_grade_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_rci_grade_data) +{ + DPP_STATUS rc = DPP_OK; + + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_rci_grade_data); + + rc = dpp_reg_read(dev_id, + ETM_CRDT_RCI_GRADEr, + 0, + 0, + p_rci_grade_data); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + return DPP_OK; +} + +DPP_STATUS dpp_tm_crdt_rci_value_r_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_crdt_rci_value_r_data) +{ + DPP_STATUS rc = DPP_OK; + + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_crdt_rci_value_r_data); + + + rc = dpp_reg_read(dev_id, + ETM_CRDT_CRDT_RCI_VALUE_Rr, + 0, + 0, + p_crdt_rci_value_r_data); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + return DPP_OK; +} + +DPP_STATUS dpp_tm_crdt_interval_now_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_crdt_interval_now_data) +{ + DPP_STATUS rc = DPP_OK; + + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_crdt_interval_now_data); + + rc = dpp_reg_read(dev_id, + ETM_CRDT_CRDT_INTERVAL_NOWr, + 0, + 0, + p_crdt_interval_now_data); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + return DPP_OK; +} + +/***********************************************************/ +/** 配置crdt interval使能， +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param crdt_interval_en_cfg_data 授权分发间隔使能，1打开，0关闭 +* +* @return +* @remark 无 +* @see +* @author wush @date 2017/03/27 +************************************************************/ +DPP_STATUS dpp_tm_crdt_interval_en_cfg_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 crdt_interval_en_cfg_data) +{ + DPP_STATUS rc = DPP_OK; + + rc = dpp_reg_write(dev_id, + ETM_CRDT_CRDT_INTERVAL_EN_CFGr, + 0, + 0, + &crdt_interval_en_cfg_data); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + return DPP_OK; +} + +/***********************************************************/ +/** 读取crdt interval使能 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param crdt_interval_en_cfg_data 授权分发间隔使能，1打开，0关闭 +* +* @return +* @remark 无 +* @see +* @author wush @date 2017/03/27 +************************************************************/ +DPP_STATUS dpp_tm_crdt_interval_en_cfg_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_crdt_interval_en_cfg_data) +{ + DPP_STATUS rc = DPP_OK; + + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_crdt_interval_en_cfg_data); + + rc = dpp_reg_read(dev_id, + ETM_CRDT_CRDT_INTERVAL_EN_CFGr, + 0, + 0, + p_crdt_interval_en_cfg_data); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + return DPP_OK; +} + +/***********************************************************/ +/** 屏蔽ucn/asm_rdy的时能信号 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param ucn_rdy_shield_en 是否屏蔽ucn_rdy信号，1屏蔽，0不屏蔽 +* @param asm_rdy_shield_en 是否屏蔽asm_rdy信号，1屏蔽，0不屏蔽 +* +* @return +* @remark 无 +* @see +* @author wush @date 2017/10/17 +************************************************************/ +DPP_STATUS dpp_tm_crdt_ucn_asm_rdy_shield_en_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 ucn_rdy_shield_en, ZXIC_UINT32 asm_rdy_shield_en) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CRDT_UCN_ASM_RDY_SHIELD_EN_T ucn_rdy_shield_en_data = {0}; + + + + ucn_rdy_shield_en_data.ucn_rdy_shield_en = ucn_rdy_shield_en; + ucn_rdy_shield_en_data.asm_rdy_shield_en = asm_rdy_shield_en; + + rc = dpp_reg_write(dev_id, + ETM_CRDT_UCN_ASM_RDY_SHIELD_ENr, + 0, + 0, + &ucn_rdy_shield_en_data); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + return DPP_OK; +} + +DPP_STATUS dpp_tm_crdt_ucn_asm_rdy_shield_en_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_ucn_rdy_shield_en, ZXIC_UINT32 *p_asm_rdy_shield_en) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CRDT_UCN_ASM_RDY_SHIELD_EN_T ucn_rdy_shield_en_data = {0}; + + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_ucn_rdy_shield_en); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_asm_rdy_shield_en); + + rc = dpp_reg_read(dev_id, + ETM_CRDT_UCN_ASM_RDY_SHIELD_ENr, + 0, + 0, + &ucn_rdy_shield_en_data); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + *p_ucn_rdy_shield_en = ucn_rdy_shield_en_data.ucn_rdy_shield_en; + *p_asm_rdy_shield_en = ucn_rdy_shield_en_data.asm_rdy_shield_en; + + return DPP_OK; +} + +#endif +#endif + + +#if ZXIC_REAL("TM_SHAPE") + +#if 0 +/***********************************************************/ +/** 把整数分解成(指定位长)最高有效数和(2的)指数位数的形式，data=p_remdata*2^(p_exp) +* @param data 需要转换前的数 +* @param rembitsum 余数的位数 +* @param p_remdata 余数大小 +* @param p_exp 指数大小 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/27 +************************************************************/ +DPP_STATUS dpp_tm_rem_and_exp_translate(ZXIC_UINT32 data, + ZXIC_UINT32 rembitsum, + ZXIC_UINT32 *p_remdata, + ZXIC_UINT32 *p_exp) +{ + ZXIC_UINT32 i = 0; + ZXIC_COMM_CHECK_POINT(p_remdata); + ZXIC_COMM_CHECK_POINT(p_exp); + + if ((0 == data) || (0 == rembitsum)) + { + *p_remdata = 0; + *p_exp = 0; + return DPP_OK; + } + + for (i = 1; i <= 32; i++) + { + /* ZXIC_UINT64位长64位，如果ZXIC_UINT32在，左移32位时会有问题 */ + if (0 == (data & (((ZXIC_UINT64) 0xffffffff) << i))) + { + break; + } + } + + if (i <= rembitsum) + { + *p_remdata = data; + *p_exp = 0; + } + else + { + *p_remdata = (data >> (i - rembitsum)); + *p_exp = i - rembitsum; + } + + return DPP_OK; + +} + +/***********************************************************/ +/** shap ram初始化 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/03/22 +************************************************************/ +DPP_STATUS dpp_tm_shap_ram_init(ZXIC_UINT32 dev_id) +{ + + + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 read_times = 30; + DPP_ETM_SHAP_SHAP_CFG_INIT_CFG_T shap_ram_cfg_init_t = {0}; + DPP_ETM_SHAP_SHAP_STA_INIT_CFG_T shap_ram_sta_init_t = {0}; + + + /**RAM初始化**/ + shap_ram_cfg_init_t.cfg_ram_init_en = 1; + rc = dpp_reg_write(dev_id, + ETM_SHAP_SHAP_CFG_INIT_CFGr, + 0, + 0, + &shap_ram_cfg_init_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + shap_ram_sta_init_t.sta_ram_init_en = 1; + rc = dpp_reg_write(dev_id, + ETM_SHAP_SHAP_STA_INIT_CFGr, + 0, + 0, + &shap_ram_sta_init_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + + + /**初始化done确认**/ + do + { + rc = dpp_reg_read(dev_id, + ETM_SHAP_SHAP_CFG_INIT_CFGr, + 0, + 0, + &shap_ram_cfg_init_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + rc = dpp_reg_read(dev_id, + ETM_SHAP_SHAP_STA_INIT_CFGr, + 0, + 0, + &shap_ram_sta_init_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + read_times--; + zxic_comm_usleep(100); + + } + while ((0 == shap_ram_cfg_init_t.cfg_ram_init_done || 0 == shap_ram_sta_init_t.sta_ram_init_done ) && (read_times > 0)); + + if (0 == read_times) + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "SHAP RAM init failed!\n"); + return DPP_ERR; + } + + return DPP_OK; + +} + +#endif +/***********************************************************/ +/** 配置流队列双桶整形使能及模式 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param db_en 双桶整形使能 +* @param mode 0:c+e模式，1:c+p模式 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/03/11 +************************************************************/ +DPP_STATUS dpp_tm_shape_flow_db_en_set(DPP_DEV_T *dev, + ZXIC_UINT32 db_en, + ZXIC_UINT32 mode) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CRDT_DB_TOKEN_T tm_shape_db_en_t = {0}; + DPP_ETM_SHAP_TOKEN_MODE_SWITCH_T tm_shap_db_mode_t = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), db_en, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), mode, 0, 1); + + + tm_shape_db_en_t.db_token = db_en; + tm_shap_db_mode_t.token_mode_switch = mode; + + rc = dpp_reg_write(dev, + ETM_CRDT_DB_TOKENr, + 0, + 0, + &tm_shape_db_en_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + rc = dpp_reg_write(dev, + ETM_SHAP_TOKEN_MODE_SWITCHr, + 0, + 0, + &tm_shap_db_mode_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + return DPP_OK; +} + +/***********************************************************/ +/** 获取流队列双桶整形使能及模式 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param db_en 双桶整形使能 +* @param mode 0:c+e模式，1:c+p模式 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/03/11 +************************************************************/ +DPP_STATUS dpp_tm_shape_flow_db_en_get(DPP_DEV_T *dev, + ZXIC_UINT32 *db_en, + ZXIC_UINT32 *mode) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CRDT_DB_TOKEN_T tm_shape_db_en_t = {0}; + DPP_ETM_SHAP_TOKEN_MODE_SWITCH_T tm_shap_db_mode_t = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), db_en); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), mode); + + rc = dpp_reg_read(dev, + ETM_CRDT_DB_TOKENr, + 0, + 0, + &tm_shape_db_en_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + rc = dpp_reg_read(dev, + ETM_SHAP_TOKEN_MODE_SWITCHr, + 0, + 0, + &tm_shap_db_mode_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + *db_en = tm_shape_db_en_t.db_token; + *mode = tm_shap_db_mode_t.token_mode_switch; + + return DPP_OK; +} + +#if 0 +/***********************************************************/ +/** 配置桶深最小单位配置:共8档：0-7 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param token_grain 3’d0：最小单位为128K +* 3’d1：最小单位为64k +* 3’d2：最小单位为32k +* 3’d3：最小单位为16k +* 3’d4：最小单位为8k +* 3’d5：最小单位为4k +* 3’d6：最小单位为2k +* 3’d7：最小单位为1k +* 默认为0，即128K +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/03/11 +************************************************************/ +DPP_STATUS dpp_tm_shape_token_grain_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 token_grain) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_SHAP_TOKEN_GRAIN_T tm_shape_token_grain_t = {0}; + + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, token_grain, 0, 7); + + tm_shape_token_grain_t.token_grain = token_grain; + + rc = dpp_reg_write(dev_id, + ETM_SHAP_TOKEN_GRAINr, + 0, + 0, + &tm_shape_token_grain_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + return DPP_OK; + +} + +#endif +/***********************************************************/ +/** 获取桶深最小单位配置:共8档：0-7 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param token_grain 3’d0：最小单位为128K +* 3’d1：最小单位为64k +* 3’d2：最小单位为32k +* 3’d3：最小单位为16k +* 3’d4：最小单位为8k +* 3’d5：最小单位为4k +* 3’d6：最小单位为2k +* 3’d7：最小单位为1k +* 默认为0，即128K +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/03/11 +************************************************************/ +DPP_STATUS dpp_tm_shape_token_grain_get(DPP_DEV_T *dev, + ZXIC_UINT32 *token_grain) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_SHAP_TOKEN_GRAIN_T tm_shape_token_grain_t = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), token_grain); + + + rc = dpp_reg_read(dev, + ETM_SHAP_TOKEN_GRAINr, + 0, + 0, + &tm_shape_token_grain_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + *token_grain = tm_shape_token_grain_t.token_grain; + + return DPP_OK; + +} + +/***********************************************************/ +/** 配置流或调度器映射到整形参数表的某个ID +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param id 流或调度器编号ETM:0-ABFF,FTM:0-177F +* @param profile_id 整形参数表id索引:[0-127] +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/03/11 +************************************************************/ +DPP_STATUS dpp_tm_shape_map_table_set(DPP_DEV_T *dev, + ZXIC_UINT32 id, + ZXIC_UINT32 profile_id) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_SHAP_SHAP_BUCKET_MAP_TBL_T tm_shape_map_tbl_t = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), profile_id, 0, 127); + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id, 0, DPP_ETM_SCH_DEL_NUM); + + tm_shape_map_tbl_t.shap_map = profile_id; + + rc = dpp_reg_write(dev, + ETM_SHAP_SHAP_BUCKET_MAP_TBLr, + 0, + id, + &tm_shape_map_tbl_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + return DPP_OK; + +} + +/***********************************************************/ +/** 获取流或调度器映射到整形参数表的配置ID +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param id 流或调度器编号ETM:0-ABFF,FTM:0-177F +* @param profile_id 整形参数表:[0-127] +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/03/11 +************************************************************/ +DPP_STATUS dpp_tm_shape_map_table_get(DPP_DEV_T *dev, + ZXIC_UINT32 id, + ZXIC_UINT32 *profile_id) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_SHAP_SHAP_BUCKET_MAP_TBL_T tm_shape_map_tbl_t = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), profile_id); + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id, 0, DPP_ETM_SCH_DEL_NUM); + + rc = dpp_reg_read(dev, + ETM_SHAP_SHAP_BUCKET_MAP_TBLr, + 0, + id, + &tm_shape_map_tbl_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + *profile_id = tm_shape_map_tbl_t.shap_map; + + return DPP_OK; + +} + +/***********************************************************/ +/** 根据流或调度器id查找对应配置表中的模板id + 找到直接进行整形配置并返回1；未找到返回0 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param id 流或调度器编号 ETM:0-ABFF,FTM:0-AFF +* @param cir cir速率，单位Kb，范围[64Kb - 160Gb] +* @param cbs cbs桶深，单位KB，范围[1KB - 64M] +* @return 找到：1，未找到：0 +* @remark 无 +* @see +* @author whuashan @date 2019/03/11 +************************************************************/ +DPP_STATUS dpp_tm_shape_find_map_id(DPP_DEV_T *dev, + ZXIC_UINT32 id, + ZXIC_UINT32 cir, + ZXIC_UINT32 cbs) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 i = 0; + ZXIC_UINT32 table_id = 0; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 2); + + + /* 根据id计算归属哪张表：每2K对应一个128项表 */ + table_id = id / 2048; + + for (i = 1; i < 128; i++) + { + if (g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][i].shape_cir == cir && + g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][i].shape_cbs == cbs) + { + rc = dpp_tm_shape_map_table_set(dev, id, i); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_shape_map_table_set"); + g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][i].shape_num++; + + return 1; + } + + } + + return 0; + +} + +/***********************************************************/ +/** 配置流级整形参数 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param flow_id 流队列号 ETM:0-9215,FTM:0-2047 +* @param cir cir速率，单位Kb，范围[64Kb - 160Gb] +* @param cbs cbs桶深，单位KB，范围[1KB - 64M] +* 注：cbs=0 表示关闭整形,即不限速 +* @param db_en 双桶整形使能，0-单桶，1-双桶 +* @param eir eir速率，单位Kb，范围同cir +* @param ebs ebs桶深，单位KB，范围同cbs +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/03/11 +************************************************************/ +DPP_STATUS dpp_tm_shape_flow_para_set(DPP_DEV_T *dev, + ZXIC_UINT32 flow_id, + ZXIC_UINT32 cir, + ZXIC_UINT32 cbs, + ZXIC_UINT32 db_en, + ZXIC_UINT32 eir, + ZXIC_UINT32 ebs) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + + + rc = dpp_etm_shape_flow_para_set(dev, flow_id, cir, cbs, db_en, eir, ebs); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_etm_shape_flow_para_set"); + + return DPP_OK; + +} + +/***********************************************************/ +/** 获取流级整形参数 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param flow_id 流队列号 ETM:0-9215,FTM:0-2047 +* @param cir cir速率，单位Kb，范围[64Kb - 160Gb] +* @param cbs cbs桶深，单位KB，范围[1KB - 64M] +* 注：cbs=0 表示关闭整形,即不限速 +* @param mode_e 整形模式，0-获取c桶参数，1-获取对应e桶参数 +* @param p_para_id 整形模板索引：ETM=[0-AFF]，FTM=[0-17F] +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/03/11 +************************************************************/ +DPP_STATUS dpp_tm_shape_flow_para_get(DPP_DEV_T *dev, + ZXIC_UINT32 flow_id, + ZXIC_UINT32 mode, + ZXIC_UINT32 *p_para_id, + DPP_TM_SHAPE_PARA_TABLE *p_flow_para_tbl) +{ + + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 flow_id_e = 0; + ZXIC_UINT32 table_id = 0; + ZXIC_UINT32 profile_id = 0; + ZXIC_UINT32 bucket_para_n = 0; + ZXIC_UINT32 bucket_depth = 0; /* 实际写入寄存器的桶深，为多少个调节单位 */ + ZXIC_UINT32 bucket_rate = 0; /* 实际写入寄存器的速率，为每4096周期添加的字节数 */ + ZXIC_UINT32 token_grain = 0; /* 令牌桶调节档位 */ + ZXIC_UINT32 token_grain_kb[8] = {128, 64, 32, 16, 8, 4, 2, 1}; /* 档位对应值 */ + DPP_ETM_SHAP_BKT_PARA_TBL_T shap_para_tbl_t = {0}; + + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), mode, 0, 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_para_id); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_flow_para_tbl); + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), flow_id, 0, DPP_ETM_Q_NUM - 1); + + flow_id_e = flow_id + DPP_ETM_Q_NUM; + + table_id = flow_id / 2048; + + /*获取流的profile_id*/ + if (mode) + { + table_id = flow_id_e / 2048; + rc = dpp_tm_shape_map_table_get(dev, flow_id_e, &profile_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_shape_map_table_get"); + } + else + { + rc = dpp_tm_shape_map_table_get(dev, flow_id, &profile_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_shape_map_table_get"); + + } + + /*从寄存器读取流配置参数*/ + bucket_para_n = table_id * 128 + profile_id; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), bucket_para_n, 0, 0xAFF); + + rc = dpp_reg_read(dev, + ETM_SHAP_BKT_PARA_TBLr, + 0, + bucket_para_n, + &shap_para_tbl_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + bucket_depth = shap_para_tbl_t.bucket_depth; + bucket_rate = shap_para_tbl_t.bucket_rate; + + /*数据转换处理*/ + rc = dpp_tm_shape_token_grain_get(dev, &token_grain); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_shape_token_grain_get"); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), token_grain, 0, 7); + + *p_para_id = bucket_para_n; + p_flow_para_tbl->shape_cbs = bucket_depth * token_grain_kb[token_grain]; + p_flow_para_tbl->shape_cir = (ZXIC_UINT64)bucket_rate * DPP_TM_SYS_HZ * 8 / ((ZXIC_UINT64)4096 * DPP_TM_KILO_ULL * 64); + + return DPP_OK; + +} + +/***********************************************************/ +/** etm配置流级整形参数 +* @param dev_id 设备编号 +* @param flow_id 流队列号 ETM:0-9215,FTM:0-2047 +* @param cir cir速率，单位Kb，范围[20Kb - 160Gb] +* @param cbs cbs桶深，单位KB，范围[1KB - 64M] +* 注：cbs=0 表示关闭整形,即不限速 +* @param db_en 双桶整形使能，0-单桶，1-双桶 +* @param eir eir速率，单位Kb，范围同cir +* @param ebs ebs桶深，单位KB，范围同cbs +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/03/11 +************************************************************/ +DPP_STATUS dpp_etm_shape_flow_para_set(DPP_DEV_T *dev, + ZXIC_UINT32 flow_id, + ZXIC_UINT32 cir, + ZXIC_UINT32 cbs, + ZXIC_UINT32 db_en, + ZXIC_UINT32 eir, + ZXIC_UINT32 ebs) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 i = 0; + ZXIC_UINT32 table_id = 0; + ZXIC_UINT32 profile_id = 0; + ZXIC_UINT32 total_para_id = 0; + ZXIC_UINT32 get_profile_success_flag_c = 0; /* 当前已配置表中是否找到需要的整形模板 */ + ZXIC_UINT32 get_profile_success_flag_e = 0; /* 当前已配置表中是否找到需要的整形模板 */ + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 2); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), flow_id, 0, DPP_ETM_Q_NUM - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), cir, DPP_TM_SHAPE_CIR_MIN, DPP_TM_SHAPE_CIR_MAX); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), cbs, DPP_TM_SHAPE_CBS_MIN, DPP_TM_SHAPE_CBS_MAX); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), db_en, 0, 1); + + if (db_en) + { + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), eir, DPP_TM_SHAPE_CIR_MIN, DPP_TM_SHAPE_CIR_MAX); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), ebs, DPP_TM_SHAPE_CBS_MIN, DPP_TM_SHAPE_CBS_MAX); + } + + rc = dpp_tm_global_var_mutex_init(); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_global_var_mutex_init"); + + rc = zxic_comm_mutex_lock(&g_dpp_tm_global_var_rw_mutex); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "zxic_comm_mutex_lock"); + + /**双桶开关配置**/ + rc = dpp_tm_shape_flow_db_en_set(dev, db_en, 0); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_tm_shape_flow_db_en_set", &g_dpp_tm_global_var_rw_mutex); + + /******STEP1:先解除原profile_id映射******/ + /**处理c桶**/ + rc = dpp_tm_shape_map_table_get(dev, flow_id, &profile_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_tm_shape_map_table_get", &g_dpp_tm_global_var_rw_mutex); + + if (profile_id > 0 && (profile_id < DPP_TM_SHAP_MAP_ID_MAX)) + { + /***表示当前有配置整形: 根据id计算归属哪张表：每2K队列对应一个128项表***/ + table_id = flow_id / 2048; + + if (g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][profile_id].shape_num != 0) + { + g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][profile_id].shape_num--; + + if (0 == g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][profile_id].shape_num) + { + g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][profile_id].shape_cbs = 0; + g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][profile_id].shape_cir = 0; + } + } + } + + /**处理e桶**/ + rc = dpp_tm_shape_map_table_get(dev, (flow_id + DPP_ETM_Q_NUM), &profile_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_tm_shape_map_table_get", &g_dpp_tm_global_var_rw_mutex); + + if (profile_id > 0 && (profile_id < DPP_TM_SHAP_MAP_ID_MAX)) + { + /*表示当前有配置整形*/ + table_id = (flow_id + DPP_ETM_Q_NUM) / 2048; + + if (g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][profile_id].shape_num != 0) + { + g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][profile_id].shape_num--; + + if (0 == g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][profile_id].shape_num) + { + g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][profile_id].shape_cbs = 0; + g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][profile_id].shape_cir = 0; + } + } + } + + + /******STEP2:整形关闭的处理******/ + if (cbs == 0) + { + /*关闭c桶e桶整形,并返回函数*/ + rc = dpp_tm_shape_map_table_set(dev, (flow_id), 0); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_tm_shape_map_table_set", &g_dpp_tm_global_var_rw_mutex); + rc = dpp_tm_shape_map_table_set(dev, (flow_id + DPP_ETM_Q_NUM), 0); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_tm_shape_map_table_set", &g_dpp_tm_global_var_rw_mutex); + + rc = zxic_comm_mutex_unlock(&g_dpp_tm_global_var_rw_mutex); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "zxic_comm_mutex_unlock"); + return DPP_OK; + } + + if (ebs == 0 || db_en == 0) + { + /*关闭e桶整形*/ + rc = dpp_tm_shape_map_table_set(dev, (flow_id + DPP_ETM_Q_NUM), 0); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_tm_shape_map_table_set", &g_dpp_tm_global_var_rw_mutex); + get_profile_success_flag_e = 1; + + } + + + /******STEP3:整形配置处理,先在现有模板中查找******/ + /* 单桶整形 :c桶 */ + if (ebs == 0) + { + /* 此时只有cbs>0，仅开启c桶整形：先查找c桶整形profile配置 */ + rc = dpp_tm_shape_find_map_id(dev, flow_id, cir, cbs); + + if (rc) + { + get_profile_success_flag_c = 1; + } + else + { + get_profile_success_flag_c = 0; + } + } + /* 双桶整形 :c+e桶 */ + else + { + /* 此时cbs>0,ebs>0：先查找c桶整形profile配置 */ + rc = dpp_tm_shape_find_map_id(dev, flow_id, cir, cbs); + + if (rc) + { + get_profile_success_flag_c = 1; + } + else + { + get_profile_success_flag_c = 0; + } + + /* 查找e桶整形profile配置 */ + rc = dpp_tm_shape_find_map_id(dev, flow_id + DPP_ETM_Q_NUM, eir, ebs); + + if (rc ) + { + get_profile_success_flag_e = 1; + } + else + { + get_profile_success_flag_e = 0; + } + + } + + /******STEP4:现有整形模板中未找到所需profile******/ + if (!get_profile_success_flag_c) + { + /* 根据id计算归属哪张表：每2K对应一个128项表 */ + table_id = flow_id / 2048; + + for (i = 1; i < 128; i++) + { + if (g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][i].shape_num == 0) + { + + /**********映射模板id********/ + rc = dpp_tm_shape_map_table_set(dev, flow_id, i); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_tm_shape_map_table_set", &g_dpp_tm_global_var_rw_mutex); + + /*********整形参数配置********/ + total_para_id = table_id * 128 + i; + rc = dpp_tm_shape_para_set(dev, total_para_id, cir, cbs); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_tm_shape_para_set", &g_dpp_tm_global_var_rw_mutex); + + /********同步更新全局数组******/ + g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][i].shape_cir = cir; + g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][i].shape_cbs = cbs; + g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][i].shape_num++; + + get_profile_success_flag_c = 1; + break; + } + + } + } + + if (!get_profile_success_flag_e && ebs) + { + /* 根据id计算归属哪张表：每2K对应一个128项表 */ + table_id = (flow_id + DPP_ETM_Q_NUM) / 2048; + + for (i = 1; i < 128; i++) + { + if (g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][i].shape_num == 0) + { + + /**********映射模板id********/ + rc = dpp_tm_shape_map_table_set(dev, (flow_id + DPP_ETM_Q_NUM), i); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_tm_shape_map_table_set", &g_dpp_tm_global_var_rw_mutex); + + /*********整形参数配置********/ + total_para_id = table_id * 128 + i; + rc = dpp_tm_shape_para_set(dev, total_para_id, eir, ebs); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_tm_shape_para_set", &g_dpp_tm_global_var_rw_mutex); + + /********同步更新全局数组******/ + g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][i].shape_cir = eir; + g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][i].shape_cbs = ebs; + g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][i].shape_num++; + + get_profile_success_flag_e = 1; + break; + } + + } + } + + + if (!get_profile_success_flag_c || !get_profile_success_flag_e) + { + ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "Failure! Profile resource are FULL!\n"); + rc = zxic_comm_mutex_unlock(&g_dpp_tm_global_var_rw_mutex); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "zxic_comm_mutex_unlock"); + + return DPP_ERR; + } + + rc = zxic_comm_mutex_unlock(&g_dpp_tm_global_var_rw_mutex); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "zxic_comm_mutex_unlock"); + + return DPP_OK; +} + + +/***********************************************************/ +/** tm配置调度器整形参数 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param se_id 调度器编号号,用户看到：ETM 0-0x63FF, FTM 0-0x77F +* 实际：ETM:0x4800-0xABFF,FTM:0x1000-0x177F +* @param pir pir总速率，单位Kb，范围同cir +* @param pbs pbs总桶深，单位KB，范围同cbs +* @param db_en 整形模式，0-单桶，1-双桶，仅FQ8/WFQ8有效 +* @param cir [0-3]调度器cir速率，单位Kb，范围[64Kb - 160Gb] +* @param cbs [0-3]调度器cbs桶深，单位KB，范围[1KB - 64M] +* 注：cbs=0 表示关闭整形,即不限速 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/03/11 +************************************************************/ +DPP_STATUS dpp_tm_shape_se_para_set(DPP_DEV_T *dev, + ZXIC_UINT32 se_id, + ZXIC_UINT32 pir, + ZXIC_UINT32 pbs, + ZXIC_UINT32 db_en, + ZXIC_UINT32 cir, + ZXIC_UINT32 cbs) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + + rc = dpp_etm_shape_se_para_set(dev, se_id, pir, pbs, db_en, cir, cbs); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_etm_shape_se_para_set"); + + + return DPP_OK; + +} + +/***********************************************************/ +/** 获取调度单元整形参数 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param se_id 调度器单元号 ETM:0-63FF,FTM:0-77F +* @param cir cir速率，单位Kb，范围[64Kb - 160Gb] +* @param cbs cbs桶深，单位KB，范围[1KB - 64M] +* 注：cbs=0 表示关闭整形,即不限速 +* @param mode 整形模式，0-获取p桶参数，1-获取对应c桶参数(仅FQ8/WFQ8支持) +* @param p_para_id 整形模板索引：ETM=[0-AFF]，FTM=[0-17F] +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/03/11 +************************************************************/ +DPP_STATUS dpp_tm_shape_se_para_get(DPP_DEV_T *dev, + ZXIC_UINT32 se_id, + ZXIC_UINT32 mode, + ZXIC_UINT32 *p_para_id, + DPP_TM_SHAPE_PARA_TABLE *p_se_para_tbl) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 real_se_id = 0; + ZXIC_UINT32 se_id_c = 0; + ZXIC_UINT32 table_id = 0; + ZXIC_UINT32 profile_id = 0; + ZXIC_UINT32 bucket_para_n = 0; + ZXIC_UINT32 bucket_depth = 0; /* 实际写入寄存器的桶深，为多少个调节单位 */ + ZXIC_UINT32 bucket_rate = 0; /* 实际写入寄存器的速率，为每4096周期添加的字节数 */ + ZXIC_UINT32 token_grain = 0; /* 令牌桶调节档位 */ + ZXIC_UINT32 token_grain_kb[8] = {128, 64, 32, 16, 8, 4, 2, 1}; /* 档位对应值 */ + DPP_ETM_SHAP_BKT_PARA_TBL_T shap_para_tbl_t = {0}; + + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), mode, 0, 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_para_id); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_se_para_tbl); + + real_se_id = (se_id + DPP_ETM_SHAP_SEID_BASE); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), real_se_id, 0, DPP_ETM_SCH_DEL_NUM); + + + se_id_c = real_se_id + 4; + + table_id = real_se_id / 2048; + + /*获取调度器的profile_id*/ + if (mode) + { + rc = dpp_tm_shape_map_table_get(dev, se_id_c, &profile_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_shape_map_table_get"); + } + else + { + rc = dpp_tm_shape_map_table_get(dev, real_se_id, &profile_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_shape_map_table_get"); + + } + + + /*从寄存器读取调度器配置参数*/ + bucket_para_n = table_id * 128 + profile_id; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), bucket_para_n, 0, 0xAFF); + + rc = dpp_reg_read(dev, + ETM_SHAP_BKT_PARA_TBLr, + 0, + bucket_para_n, + &shap_para_tbl_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + bucket_depth = shap_para_tbl_t.bucket_depth; + bucket_rate = shap_para_tbl_t.bucket_rate; + + /*数据转换处理*/ + rc = dpp_tm_shape_token_grain_get(dev, &token_grain); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_shape_token_grain_get"); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), token_grain, 0, 7); + + *p_para_id = bucket_para_n; + p_se_para_tbl->shape_cbs = bucket_depth * token_grain_kb[token_grain]; + p_se_para_tbl->shape_cir = (ZXIC_UINT64)bucket_rate * DPP_TM_SYS_HZ * 8 / ((ZXIC_UINT64)4096 * DPP_TM_KILO_ULL * 64); + + return DPP_OK; + +} + + + + +/***********************************************************/ +/** etm配置调度器整形参数 +* @param dev_id 设备编号 +* @param se_id 调度器编号号 ETM 0-0x63FF, FTM 0-0x77F +* 实际：ETM:0x4800-0xABFF,FTM:0x1000-0x177F +* @param pir pir总速率，单位Kb，范围同cir +* @param pbs pbs总桶深，单位Kb，范围同cbs +* @param db_en 整形模式，0-单桶，1-双桶，仅FQ8/WFQ8有效 +* @param cir [0-3]调度器cir速率，单位Kb，范围[64Kb - 160Gb] +* @param cbs [0-3]调度器cbs桶深，单位KB，范围[1KB - 64M] +* 注：cbs=0 表示关闭整形,即不限速 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/03/11 +************************************************************/ +DPP_STATUS dpp_etm_shape_se_para_set(DPP_DEV_T *dev, + ZXIC_UINT32 se_id, + ZXIC_UINT32 pir, + ZXIC_UINT32 pbs, + ZXIC_UINT32 db_en, + ZXIC_UINT32 cir, + ZXIC_UINT32 cbs) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 i = 0; + ZXIC_UINT32 real_se_id = 0; + ZXIC_UINT32 sch_type = 0; + ZXIC_UINT32 sch_type_num = 0; + ZXIC_UINT32 table_id = 0; + ZXIC_UINT32 profile_id = 0; + ZXIC_UINT32 total_para_id = 0; + ZXIC_UINT32 get_profile_success_flag_p = 0; /* 当前已配置表中是否找到需要的p桶整形模板 */ + ZXIC_UINT32 get_profile_success_flag_c = 0; /* 当前已配置表中是否找到需要的c桶整形模板 */ + DPP_ETM_CRDT_SE_PARA_TBL_T crdt_se_para_tabl_t = {0}; /*配置cp双桶模式,仅FQ8/WFQ8使用*/ + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 2); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_id, 0, DPP_ETM_FQSPWFQ_NUM-1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), pir, DPP_TM_SHAPE_CIR_MIN, DPP_TM_SHAPE_CIR_MAX); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), pbs, DPP_TM_SHAPE_CBS_MIN, DPP_TM_SHAPE_CBS_MAX); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), db_en, 0, 1); + + real_se_id = (se_id + DPP_ETM_SHAP_SEID_BASE); + + if (db_en) + { + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), cir, DPP_TM_SHAPE_CIR_MIN, DPP_TM_SHAPE_CIR_MAX); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), cbs, DPP_TM_SHAPE_CBS_MIN, DPP_TM_SHAPE_CBS_MAX); + } + + rc = dpp_tm_global_var_mutex_init(); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_global_var_mutex_init"); + + rc = zxic_comm_mutex_lock(&g_dpp_tm_global_var_rw_mutex); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "zxic_comm_mutex_lock"); + + + rc = dpp_tm_crdt_sch_type_get(dev, se_id, &sch_type, &sch_type_num); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_tm_crdt_sch_type_get", &g_dpp_tm_global_var_rw_mutex); + + /**双桶模式配置:crdt模块se_id不用转换**/ + if (sch_type == 8) + { + + for (i = 0; i < 8; i++) + { + rc = dpp_reg_read(dev, + ETM_CRDT_SE_PARA_TBLr, + 0, + se_id + i, + &crdt_se_para_tabl_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_reg_read", &g_dpp_tm_global_var_rw_mutex); + + crdt_se_para_tabl_t.cp_token_en = db_en; + + rc = dpp_reg_write(dev, + ETM_CRDT_SE_PARA_TBLr, + 0, + se_id + i, + &crdt_se_para_tabl_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_reg_write", &g_dpp_tm_global_var_rw_mutex); + } + + } + + /******STEP1:先解除原profile_id映射******/ + /**处理p桶**/ + rc = dpp_tm_shape_map_table_get(dev, real_se_id, &profile_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_tm_shape_map_table_get", &g_dpp_tm_global_var_rw_mutex); + + if (profile_id > 0 && (profile_id < DPP_TM_SHAP_MAP_ID_MAX)) + { + /***表示当前有配置整形: 根据id计算归属哪张表：每2K队列对应一个128项表***/ + table_id = real_se_id / 2048; + + if (g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][profile_id].shape_num != 0) + { + g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][profile_id].shape_num--; + } + } + + if (sch_type == 8) + { + /**处理c桶**/ + rc = dpp_tm_shape_map_table_get(dev, (real_se_id + 4), &profile_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_tm_shape_map_table_get", &g_dpp_tm_global_var_rw_mutex); + + if (profile_id > 0 && (profile_id < DPP_TM_SHAP_MAP_ID_MAX)) + { + /*表示当前有配置整形*/ + table_id = (real_se_id + 4) / 2048; + + if (g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][profile_id].shape_num != 0) + { + g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][profile_id].shape_num--; + } + } + } + + + + /******STEP2:整形关闭的处理******/ + if (sch_type < 8) + { + /**非FQ8/WFQ8类型调度器：无双桶模式**/ + if (pbs == 0 ) + { + /*关闭p桶整形,并返回函数*/ + rc = dpp_tm_shape_map_table_set(dev, (real_se_id), 0); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_tm_shape_map_table_set", &g_dpp_tm_global_var_rw_mutex); + + rc = zxic_comm_mutex_unlock(&g_dpp_tm_global_var_rw_mutex); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "zxic_comm_mutex_unlock"); + + return DPP_OK; + } + } + else + { + /**FQ8/WFQ8类型调度器：考虑双桶**/ + if (pbs == 0 && db_en == 0) + { + /*单桶模式：关闭p桶整形,并返回函数*/ + rc = dpp_tm_shape_map_table_set(dev, (real_se_id), 0); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_tm_shape_map_table_set", &g_dpp_tm_global_var_rw_mutex); + + rc = zxic_comm_mutex_unlock(&g_dpp_tm_global_var_rw_mutex); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "zxic_comm_mutex_unlock"); + + return DPP_OK; + } + + if (pbs == 0 && db_en == 1 && cbs == 0) + { + /*双桶模式：关闭p+c桶整形，并返回函数*/ + rc = dpp_tm_shape_map_table_set(dev, (real_se_id), 0); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_tm_shape_map_table_set", &g_dpp_tm_global_var_rw_mutex); + rc = dpp_tm_shape_map_table_set(dev, (real_se_id + 4), 0); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_tm_shape_map_table_set", &g_dpp_tm_global_var_rw_mutex); + + rc = zxic_comm_mutex_unlock(&g_dpp_tm_global_var_rw_mutex); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "zxic_comm_mutex_unlock"); + + return DPP_OK; + } + + } + + + /******STEP3:整形配置处理,先在现有模板中查找******/ + /* 非FQ8/WFQ8类型：仅处理p桶，c桶flag直接至1 */ + if (sch_type < 8) + { + /* 查找p桶整形profile配置 */ + rc = dpp_tm_shape_find_map_id(dev, real_se_id, pir, pbs); + + if (rc) + { + get_profile_success_flag_p = 1; + } + else + { + get_profile_success_flag_p = 0; + } + + get_profile_success_flag_c = 1; + } + else + { + /* FQ8/WFQ8类型：p+c桶 */ + if (db_en == 0) + { + /* 单桶模式：仅查找p桶整形profile配置 */ + rc = dpp_tm_shape_find_map_id(dev, real_se_id, pir, pbs); + + if (rc) + { + get_profile_success_flag_p = 1; + } + else + { + get_profile_success_flag_p = 0; + } + + get_profile_success_flag_c = 1; + } + else + { + + /* 双桶模式：先查找p桶整形profile配置 */ + if (pbs == 0) + { + rc = dpp_tm_shape_map_table_set(dev, real_se_id, 0); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_tm_shape_map_table_set", &g_dpp_tm_global_var_rw_mutex); + + get_profile_success_flag_p = 1; + } + else + { + rc = dpp_tm_shape_find_map_id(dev, real_se_id, pir, pbs); + + if (rc) + { + get_profile_success_flag_p = 1; + } + else + { + get_profile_success_flag_p = 0; + } + } + + + /* 查找c桶整形profile配置 */ + if (cbs == 0) + { + rc = dpp_tm_shape_map_table_set(dev, (real_se_id + 4), 0); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_tm_shape_map_table_set", &g_dpp_tm_global_var_rw_mutex); + + get_profile_success_flag_c = 1; + } + else + { + rc = dpp_tm_shape_find_map_id(dev, (real_se_id + 4), cir, cbs); + + if (rc ) + { + get_profile_success_flag_c = 1; + } + else + { + get_profile_success_flag_c = 0; + } + + } + + + } + + + } + + + /******STEP4:现有整形模板中未找到所需profile******/ + if (!get_profile_success_flag_p) + { + /* 根据id计算归属哪张表：每2K对应一个128项表 */ + table_id = real_se_id / 2048; + + for (i = 1; i < 128; i++) + { + if (g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][i].shape_num == 0) + { + + /**********映射模板id********/ + rc = dpp_tm_shape_map_table_set(dev, real_se_id, i); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_tm_shape_map_table_set", &g_dpp_tm_global_var_rw_mutex); + + /*********整形参数配置********/ + total_para_id = table_id * 128 + i; + rc = dpp_tm_shape_para_set(dev, total_para_id, pir, pbs); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_tm_shape_para_set", &g_dpp_tm_global_var_rw_mutex); + + /********同步更新全局数组******/ + g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][i].shape_cir = pir; + g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][i].shape_cbs = pbs; + g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][i].shape_num++; + + get_profile_success_flag_p = 1; + break; + } + + } + } + + if (!get_profile_success_flag_c) + { + /* 根据id计算归属哪张表：每2K对应一个128项表 */ + table_id = (real_se_id + 4) / 2048; + + for (i = 1; i < 128; i++) + { + if (g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][i].shape_num == 0) + { + + /**********映射模板id********/ + rc = dpp_tm_shape_map_table_set(dev, (real_se_id + 4), i); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_tm_shape_map_table_set", &g_dpp_tm_global_var_rw_mutex); + + /*********整形参数配置********/ + total_para_id = table_id * 128 + i; + rc = dpp_tm_shape_para_set(dev, total_para_id, cir, cbs); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_tm_shape_para_set", &g_dpp_tm_global_var_rw_mutex); + + /********同步更新全局数组******/ + g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][i].shape_cir = cir; + g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][i].shape_cbs = cbs; + g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][i].shape_num++; + + get_profile_success_flag_c = 1; + break; + } + + } + } + + + if (!get_profile_success_flag_p || !get_profile_success_flag_c) + { + ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "Failure! Profile resource are FULL!\n"); + + rc = zxic_comm_mutex_unlock(&g_dpp_tm_global_var_rw_mutex); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "zxic_comm_mutex_unlock"); + return DPP_ERR; + } + + rc = zxic_comm_mutex_unlock(&g_dpp_tm_global_var_rw_mutex); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "zxic_comm_mutex_unlock"); + + return DPP_OK; +} + + +/***********************************************************/ +/** 写入流/调度器整形参数配置表 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param total_para_id 整形参数表中模板索引id ETM:0-AFF,FTM:0-17F +* @param cir 整形速率(c/e桶统一) +* @param cbs 桶深 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/03/11 +************************************************************/ +DPP_STATUS dpp_tm_shape_para_set(DPP_DEV_T *dev, + ZXIC_UINT32 total_para_id, + ZXIC_UINT32 cir, + ZXIC_UINT32 cbs) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 bucket_depth = 0; /* 实际写入寄存器的桶深，为多少个调节单位 */ + ZXIC_UINT32 bucket_rate = 0; /* 实际写入寄存器的速率，为每4096周期添加的字节数 */ + ZXIC_UINT32 token_grain = 0; /* 令牌桶调节档位 */ + ZXIC_UINT32 token_grain_kb[8] = {128, 64, 32, 16, 8, 4, 2, 1}; /* 档位对应值 */ + DPP_ETM_SHAP_BKT_PARA_TBL_T shap_para_tbl_t = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), cir, DPP_TM_SHAPE_CIR_MIN, DPP_TM_SHAPE_CIR_MAX); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), cbs, DPP_TM_SHAPE_CBS_MIN, DPP_TM_SHAPE_CBS_MAX); + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), total_para_id, 0, 0xAFF); + + + /********* 数据转换处理:Begin ********/ + + rc = dpp_tm_shape_token_grain_get(dev, &token_grain); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_shape_token_grain_get"); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), token_grain, 0, 7); + + if (cbs < token_grain_kb[token_grain] && (cbs != 0)) + { + bucket_depth = 1; /* 最小为1个桶深调节单位 */ + } + else + { + bucket_depth = cbs / token_grain_kb[token_grain]; + } + + /* 寄存器最大可写范围为[0-2047] */ + if (bucket_depth > DPP_TM_SHAPE_CBS_REG_MAX) + { + bucket_depth = DPP_TM_SHAPE_CBS_REG_MAX; + } + + /* 平均每周期添加cir*1/64bit，即每4096周期添加的字节数 */ + //bucket_rate = (ZXIC_UINT64)4096 * cir * DPP_TM_KILO_ULL * 64 / (((ZXIC_UINT64)DPP_TM_SYS_HZ / (ZXIC_UINT64)13393) * 8); + bucket_rate = (ZXIC_UINT64)4096 * cir * DPP_TM_KILO_ULL * 64 / ((ZXIC_UINT64)DPP_TM_SYS_HZ * 8); + shap_para_tbl_t.bucket_rate = bucket_rate; + shap_para_tbl_t.bucket_depth = bucket_depth; + + /******** 数据转换处理:End *********/ + + rc = dpp_reg_write(dev, + ETM_SHAP_BKT_PARA_TBLr, + 0, + total_para_id, + &shap_para_tbl_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + return DPP_OK; + +} + + +/***********************************************************/ +/** 读取流/调度器整形参数配置表 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param total_para_id 整形参数表中模板索引id ETM:0-AFF,FTM:0-17F +* @param cir 整形速率(c/e桶统一) +* @param cbs 桶深 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/03/11 +************************************************************/ +DPP_STATUS dpp_tm_shape_para_get(DPP_DEV_T *dev, + ZXIC_UINT32 total_para_id, + DPP_TM_SHAPE_PARA_TABLE *p_shap_para_tbl) +{ + + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 token_grain = 0; /* 令牌桶调节档位 */ + ZXIC_UINT32 token_grain_kb[8] = {128, 64, 32, 16, 8, 4, 2, 1}; /* 档位对应值 */ + DPP_ETM_SHAP_BKT_PARA_TBL_T shap_para_tbl_t = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_shap_para_tbl); + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), total_para_id, 0, 0xAFF); + + + /*读取配置*/ + rc = dpp_reg_read(dev, + ETM_SHAP_BKT_PARA_TBLr, + 0, + total_para_id, + &shap_para_tbl_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + /********* 数据转换处理: ********/ + rc = dpp_tm_shape_token_grain_get(dev, &token_grain); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_shape_token_grain_get"); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), token_grain, 0, 7); + + p_shap_para_tbl->shape_cbs = shap_para_tbl_t.bucket_depth * token_grain_kb[token_grain]; + p_shap_para_tbl->shape_cir = (ZXIC_UINT64)shap_para_tbl_t.bucket_rate * DPP_TM_SYS_HZ * 8 / ((ZXIC_UINT64)4096 * DPP_TM_KILO_ULL * 64); + + return DPP_OK; + +} + + +/***********************************************************/ +/** 配置端口级整形参数 更改整形转换公式 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param port_id 端口号 +* @param p_para 整形信息:CIR/CBS/EN +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cuiy @date 2016/04/15 +************************************************************/ +DPP_STATUS dpp_tm_shape_pp_para_set(DPP_DEV_T *dev, + ZXIC_UINT32 port_id, + const DPP_TM_SHAPE_PP_PARA_T *p_para) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 cir = 0;/* 颗粒度的倍数 */ + ZXIC_UINT32 cbs = 0;/* Credit的倍数 */ + ZXIC_UINT32 qmu_credit_value = 0; + //ZXIC_FLOAT DPP_TM_SHAPE_CIR_STEP_TEST = 160.069565217 * 1000 * 1000 * 1000 / 0x3FFFFFE;/*测试使用 by xuhb*/ + + DPP_ETM_CRDT_PP_WEIGHT_RAM_T pp_weight = {0}; + DPP_ETM_CRDT_PP_CBS_SHAPE_EN_RAM_T pp_cbs_shape_en = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_para); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), port_id, 0, DPP_TM_PP_NUM - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), p_para->c_en, 0, 1); + + if (p_para->c_en == 0) + { + rc = dpp_reg_read(dev, + ETM_CRDT_PP_CBS_SHAPE_EN_RAMr, + 0, + port_id, + &pp_cbs_shape_en); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + pp_cbs_shape_en.pp_c_shap_en = p_para->c_en; + rc = dpp_reg_write(dev, + ETM_CRDT_PP_CBS_SHAPE_EN_RAMr, + 0, + port_id, + &pp_cbs_shape_en); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + } + else + { + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), p_para->cir, DPP_TM_SHAPE_CIR_MIN, DPP_TM_SHAPE_CIR_MAX); + + /* 读取授权价值 */ + rc = dpp_tm_qmu_credit_value_get(dev, &qmu_credit_value); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_qmu_credit_value_get"); + + cir = p_para->cir; + //cir = (ZXIC_UINT32)(((ZXIC_UINT64)cir * DPP_TM_KILO_ULL) / DPP_TM_SHAPE_CIR_STEP)*(crdt_credit_value / qmu_credit_value); + cir = (ZXIC_UINT32)(((ZXIC_UINT64)cir * DPP_TM_KILO_ULL) / DPP_TM_SHAPE_CIR_STEP); + + + + /* 解决160Gbps设置出错的问题add by cuiy at 2016-4-15 */ + if (cir > 0x3FFFFFE) + { + cir = 0x3FFFFFE; + } + + /* 检查以kbyte为单位的CBS */ + if (qmu_credit_value != 0) + { + cbs = p_para->cbs; + cbs = cbs * DPP_TM_KILO_UL / qmu_credit_value; + } + + /* 寄存器写入CBS的最小值为20，小于该值时，整形不准 */ + if (cbs < DPP_TM_SHAPE_DEFAULT_CBS) + { + cbs = DPP_TM_SHAPE_DEFAULT_CBS; + } + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), cbs, DPP_TM_SHAPE_DEFAULT_CBS, 0x1ffff); + + pp_cbs_shape_en.pp_cbs = cbs; + pp_weight.pp_c_weight = cir; + pp_cbs_shape_en.pp_c_shap_en = p_para->c_en; + + rc = dpp_reg_write(dev, + ETM_CRDT_PP_WEIGHT_RAMr, + 0, + port_id, + &pp_weight); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + + rc = dpp_reg_write(dev, + ETM_CRDT_PP_CBS_SHAPE_EN_RAMr, + 0, + port_id, + &pp_cbs_shape_en); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write"); + } + + return DPP_OK; +} + + +/***********************************************************/ +/** 读取端口级整形参数 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param port_id 端口号 +* @param p_para 整形信息:CIR/CBS/EN +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cuiy @date 2016/04/15 +************************************************************/ +DPP_STATUS dpp_tm_shape_pp_para_get(DPP_DEV_T *dev, + ZXIC_UINT32 port_id, + DPP_TM_SHAPE_PP_PARA_T *p_para) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 cbs = 0;/* Credit的倍数 */ + ZXIC_UINT32 cir = 0;/* 颗粒度的倍数 */ + ZXIC_UINT32 qmu_credit_value = 0; + + DPP_ETM_CRDT_PP_WEIGHT_RAM_T pp_weight = {0}; + DPP_ETM_CRDT_PP_CBS_SHAPE_EN_RAM_T pp_cbs_shape_en = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_para); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), port_id, 0, DPP_TM_PP_NUM - 1); + + /* 读取授权价值 */ + rc = dpp_tm_qmu_credit_value_get(dev, &qmu_credit_value); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_qmu_credit_value_get"); + + rc = dpp_reg_read(dev, + ETM_CRDT_PP_WEIGHT_RAMr, + 0, + port_id, + &pp_weight); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + rc = dpp_reg_read(dev, + ETM_CRDT_PP_CBS_SHAPE_EN_RAMr, + 0, + port_id, + &pp_cbs_shape_en); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read"); + + cbs = pp_cbs_shape_en.pp_cbs; + cir = pp_weight.pp_c_weight; + p_para->c_en = pp_cbs_shape_en.pp_c_shap_en; + p_para->cir = (ZXIC_UINT32)((ZXIC_UINT64)cir * DPP_TM_SHAPE_CIR_STEP / DPP_TM_KILO_ULL) ; + p_para->cbs = (cbs * qmu_credit_value / DPP_TM_KILO_UL); + + return DPP_OK; + +} + +/***********************************************************/ +/** 写入端口级整形信息 +* @param tm_type 0-ETM,1-FTM +* @param port_id 端口号0-63 +* @param cir 单位Kb +* @param cbs 单位KB +* @param c_en c桶使能 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/03/03 +************************************************************/ +DPP_STATUS dpp_tm_shape_pp_para_wr(DPP_DEV_T *dev, + ZXIC_UINT32 port_id, + ZXIC_UINT32 cir, + ZXIC_UINT32 cbs, + ZXIC_UINT32 c_en) +{ + DPP_STATUS rc = DPP_OK; + DPP_TM_SHAPE_PP_PARA_T para = {0}; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), port_id, 0, DPP_TM_PP_NUM - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), c_en, 0, 1); + + para.cir = cir; + para.cbs = cbs; + para.c_en = c_en; + + rc = dpp_tm_shape_pp_para_set(dev, port_id, ¶); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_shape_pp_para_set"); + + return DPP_OK; +} + +#if 0 +/***********************************************************/ +/** 配置第0~15个被统计得到令牌个数的端口号 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param port_id 被统计得到令牌个数的端口号 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/3/15 STM模式下使用 +************************************************************/ +DPP_STATUS dpp_tm_shape_token_pp_cfg(ZXIC_UINT32 dev_id, + ZXIC_UINT32 port_id) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 tmp_port = 0; + ZXIC_UINT32 i = 0; + DPP_ETM_CRDT_Q_TOKEN_STAUE_CFG_T crdt_q_token_staue_cfg = {0}; + + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, port_id, 0, 63); + + tmp_port = port_id; + + if (tmp_port > 48) + { + tmp_port = 48; + } + + for (i = 0; i < 16; i++) + { + crdt_q_token_staue_cfg.test_token_q_id = tmp_port + i; + rc = dpp_reg_write(dev_id, + ETM_CRDT_Q_TOKEN_STAUE_CFGr, + 0, + i, + &crdt_q_token_staue_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + + return DPP_OK; +} + + +/***********************************************************/ +/** 打印被指定统计的第0~15个端口消耗的令牌个数 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM + +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 统计时间为2s，其中c桶统计1s，e桶统计1s +* @see +* @author whuashan @date 2019/03/15 +************************************************************/ +DPP_STATUS dpp_tm_shape_token_dec_cnt_diag(ZXIC_UINT32 dev_id) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 i = 0; + ZXIC_UINT32 dec_num[16] = {0}; + ZXIC_UINT32 credit_value = 0; + ZXIC_UINT32 port_num = 0; + ZXIC_FLOAT traffic_amplified = 0.0; + ZXIC_UINT32 shape_token_cycle_reg_index = 0; + ZXIC_UINT32 shape_q_token_sta_cfg_reg_index = 0; + ZXIC_UINT32 shape_test_token_calc_ctrl_reg_index = 0; + ZXIC_UINT32 shape_q_token_dec_cnt_reg_index = 0; + + DPP_TM_WORK_MODE_E sa_work_mode = 0; + DPP_TM_CNT_MODE_T que_get_mode = {0}; + DPP_ETM_CRDT_TEST_TOKEN_CALC_CTRL_T shap_test_token_calc_ctrl = {0}; + DPP_ETM_CRDT_TEST_TOKEN_SAMPLE_CYCLE_NUM_T test_token_sample_cycle_num = {0}; + DPP_ETM_CRDT_Q_TOKEN_STAUE_CFG_T q_token_staue_cfg = {0}; + DPP_ETM_CRDT_Q_TOKEN_DEC_CNT_T q_token_dec_cnt = {0}; + + + shape_token_cycle_reg_index = ETM_CRDT_TEST_TOKEN_SAMPLE_CYCLE_NUMr; + shape_q_token_sta_cfg_reg_index = ETM_CRDT_Q_TOKEN_STAUE_CFGr; + shape_test_token_calc_ctrl_reg_index = ETM_CRDT_TEST_TOKEN_CALC_CTRLr; + shape_q_token_dec_cnt_reg_index = ETM_CRDT_Q_TOKEN_DEC_CNTr; + + + /* 配置寄存器为读清模式 */ + rc = dpp_tm_cfgmt_cnt_mode_get(dev_id, &que_get_mode); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_cnt_mode_get"); + que_get_mode.count_rd_mode = 1; + + rc = dpp_tm_cfgmt_cnt_mode_set(dev_id, &que_get_mode); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_cnt_mode_set"); + + /* 获取端口号 */ + rc = dpp_reg_read(dev_id, + shape_q_token_sta_cfg_reg_index, + 0, + 0, + &q_token_staue_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + port_num = q_token_staue_cfg.test_token_q_id; + + /* 配置统计的时间，单位是令牌下发周期，令牌下发频率为600M/32 */ + test_token_sample_cycle_num.sample_cycle_num = 18750000; + rc = dpp_reg_write(dev_id, + shape_token_cycle_reg_index, + 0, + 0, + &test_token_sample_cycle_num); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + + /* 启动统计功能 */ + shap_test_token_calc_ctrl.test_token_calc_trigger = 1; + rc = dpp_reg_write(dev_id, + shape_test_token_calc_ctrl_reg_index, + 0, + 0, + &shap_test_token_calc_ctrl); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + /* 等待统计完成 */ + rc = dpp_reg_read(dev_id, + shape_test_token_calc_ctrl_reg_index, + 0, + 0, + &shap_test_token_calc_ctrl); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + while (!shap_test_token_calc_ctrl.test_token_calc_state) + { + rc = dpp_reg_read(dev_id, + shape_test_token_calc_ctrl_reg_index, + 0, + 0, + &shap_test_token_calc_ctrl); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + } + + /* 关闭统计功能 */ + shap_test_token_calc_ctrl.test_token_calc_trigger = 0; + rc = dpp_reg_write(dev_id, + shape_test_token_calc_ctrl_reg_index, + 0, + 0, + &shap_test_token_calc_ctrl); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + + /* 读取计数器的计数 */ + for (i = 0; i < 16; i++) + { + rc = dpp_reg_read(dev_id, + shape_q_token_dec_cnt_reg_index, + 0, + i, + &q_token_dec_cnt); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + dec_num[i] = q_token_dec_cnt.q_token_dec_counter; + + } + + + rc = dpp_tm_cfgmt_sa_work_mode_get(dev_id, &sa_work_mode); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_sa_work_mode_get"); + + if (0 == sa_work_mode) + { + rc = dpp_tm_qmu_credit_value_get(dev_id, &credit_value); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_credit_value_get"); + } + else if (1 == sa_work_mode) + { + rc = dpp_tm_qmu_sa_credit_value_get(dev_id, 4, &credit_value); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_sa_credit_value_get"); + } + else + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "SA work mode error\n"); + return DPP_ERR; + } + + + /* 计算各级消耗令牌速率:cnt*8*credit_value/(2*cycle_num*32/600M) */ + traffic_amplified = (ZXIC_FLOAT)(credit_value) * (ZXIC_FLOAT)(8.0) / ( (ZXIC_FLOAT)(2.0) * (ZXIC_FLOAT)(18750000.0)); + + for (i = 0; i < 16; i++) + { + ZXIC_COMM_PRINT("pp_%d: traffic = %.6f.(M)\n", (port_num + i), (ZXIC_FLOAT)(dec_num[i]) * traffic_amplified); + } + + + /* 配置寄存器为不读清模式 */ + rc = dpp_tm_cfgmt_cnt_mode_get(dev_id, &que_get_mode); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_cnt_mode_get"); + + que_get_mode.count_rd_mode = 0; + rc = dpp_tm_cfgmt_cnt_mode_set(dev_id, &que_get_mode); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_cnt_mode_set"); + + return DPP_OK; +} + + +/***********************************************************/ +/** 打印被指定统计的第0~15个端口接收的令牌个数 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 统计时间为2s，其中c桶统计1s，e桶统计1s +* @see +* @author whuashan @date 2019/03/15 +************************************************************/ +DPP_STATUS dpp_tm_shape_token_dist_cnt_diag(ZXIC_UINT32 dev_id) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 i = 0; + ZXIC_UINT32 dist_num[16] = {0}; + ZXIC_UINT32 credit_value = 0; + ZXIC_UINT32 port_num = 0; + ZXIC_FLOAT traffic_amplified = 0.0; + ZXIC_UINT32 shape_token_cycle_reg_index = 0; + ZXIC_UINT32 shape_q_token_sta_cfg_reg_index = 0; + ZXIC_UINT32 shape_test_token_calc_ctrl_reg_index = 0; + ZXIC_UINT32 shape_q_token_dist_cnt_reg_index = 0; + DPP_TM_WORK_MODE_E sa_work_mode = 0; + DPP_TM_CNT_MODE_T que_get_mode = {0}; + DPP_ETM_CRDT_TEST_TOKEN_CALC_CTRL_T shap_test_token_calc_ctrl = {0}; + DPP_ETM_CRDT_TEST_TOKEN_SAMPLE_CYCLE_NUM_T test_token_sample_cycle_num = {0}; + DPP_ETM_CRDT_Q_TOKEN_STAUE_CFG_T q_token_staue_cfg = {0}; + DPP_ETM_CRDT_Q_TOKEN_DIST_CNT_T q_token_dist_cnt = {0}; + + shape_token_cycle_reg_index = ETM_CRDT_TEST_TOKEN_SAMPLE_CYCLE_NUMr; + shape_q_token_sta_cfg_reg_index = ETM_CRDT_Q_TOKEN_STAUE_CFGr; + shape_test_token_calc_ctrl_reg_index = ETM_CRDT_TEST_TOKEN_CALC_CTRLr; + shape_q_token_dist_cnt_reg_index = ETM_CRDT_Q_TOKEN_DIST_CNTr; + + /* 配置寄存器为读清模式 */ + rc = dpp_tm_cfgmt_cnt_mode_get(dev_id, &que_get_mode); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_cnt_mode_get"); + que_get_mode.count_rd_mode = 1; + + rc = dpp_tm_cfgmt_cnt_mode_set(dev_id, &que_get_mode); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_cnt_mode_set"); + + /* 获取端口号 */ + rc = dpp_reg_read(dev_id, + shape_q_token_sta_cfg_reg_index, + 0, + 0, + &q_token_staue_cfg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + port_num = q_token_staue_cfg.test_token_q_id; + + /* 配置统计的时间，单位是令牌下发周期，令牌下发频率为600M/32 */ + test_token_sample_cycle_num.sample_cycle_num = 18750000; + rc = dpp_reg_write(dev_id, + shape_token_cycle_reg_index, + 0, + 0, + &test_token_sample_cycle_num); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + + /* 启动统计功能 */ + shap_test_token_calc_ctrl.test_token_calc_trigger = 1; + rc = dpp_reg_write(dev_id, + shape_test_token_calc_ctrl_reg_index, + 0, + 0, + &shap_test_token_calc_ctrl); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + /* 等待统计完成 */ + rc = dpp_reg_read(dev_id, + shape_test_token_calc_ctrl_reg_index, + 0, + 0, + &shap_test_token_calc_ctrl); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + while (!shap_test_token_calc_ctrl.test_token_calc_state) + { + rc = dpp_reg_read(dev_id, + shape_test_token_calc_ctrl_reg_index, + 0, + 0, + &shap_test_token_calc_ctrl); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + } + + /* 关闭统计功能 */ + shap_test_token_calc_ctrl.test_token_calc_trigger = 0; + rc = dpp_reg_write(dev_id, + shape_test_token_calc_ctrl_reg_index, + 0, + 0, + &shap_test_token_calc_ctrl); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + /* 读取c桶计数器的计数 */ + for (i = 0; i < 16; i++) + { + + rc = dpp_reg_read(dev_id, + shape_q_token_dist_cnt_reg_index, + 0, + i, + &q_token_dist_cnt); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + dist_num[i] = q_token_dist_cnt.q_token_dist_counter; + + } + + + rc = dpp_tm_qmu_credit_value_get(dev_id, &credit_value); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_credit_value_get"); + rc = dpp_tm_cfgmt_sa_work_mode_get(dev_id, &sa_work_mode); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_sa_work_mode_get"); + + if (0 == sa_work_mode) + { + rc = dpp_tm_qmu_credit_value_get(dev_id, &credit_value); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_credit_value_get"); + } + else if (1 == sa_work_mode) + { + rc = dpp_tm_qmu_sa_credit_value_get(dev_id, 4, &credit_value); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_sa_credit_value_get"); + } + else + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "SA work mode error\n"); + return DPP_ERR; + } + + /* 计算各级消耗令牌速率:cnt*8*credit_value/(2*cycle_num*32/600M) */ + traffic_amplified = (ZXIC_FLOAT)(credit_value) * (ZXIC_FLOAT)(8.0) / ( (ZXIC_FLOAT)(2.0) * (ZXIC_FLOAT)(18750000.0)); + + for (i = 0; i < 16; i++) + { + ZXIC_COMM_PRINT("pp_%d: traffic = %.6f.(M)\n", (port_num + i), (ZXIC_FLOAT)(dist_num[i]) * traffic_amplified); + } + + + /* 配置寄存器为不读清模式 */ + rc = dpp_tm_cfgmt_cnt_mode_get(dev_id, &que_get_mode); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_cnt_mode_get"); + que_get_mode.count_rd_mode = 0; + rc = dpp_tm_cfgmt_cnt_mode_set(dev_id, &que_get_mode); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_cnt_mode_set"); + + return DPP_OK; +} + +/***********************************************************/ +/** 打印指定的全局数组值以及清空全局数组 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param para_x 数组index_x +* @param para_y 数组index_y +* @param clear_flag 清空shape全局数组 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark +* @see +* @author xuhb @date 2019/06/10 +************************************************************/ +DPP_STATUS dpp_tm_shape_para_array_prt(ZXIC_UINT32 dev_id, ZXIC_UINT32 para_x, ZXIC_UINT32 para_y, ZXIC_UINT32 clear_flag) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 2); + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, para_x, 0, 21); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, para_y, 0, 127); + ZXIC_COMM_PRINT("cir(kb):%d cbs(KB):%d num:%d\n", g_dpp_etm_shape_para_table[dev_id][para_x][para_y].shape_cir, + g_dpp_etm_shape_para_table[dev_id][para_x][para_y].shape_cbs, + g_dpp_etm_shape_para_table[dev_id][para_x][para_y].shape_num); + + if (clear_flag) + { + rc = dpp_tm_clr_shape_para(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_clr_shape_para"); + } + + + return DPP_OK; +} + +#endif +/***********************************************************/ +/** 获取全局数组中用户实际配置的整形值 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param flow_id 流队列号 ETM:0-9215,FTM:0-2047 +* @param cir cir速率，单位Kb，范围[64Kb - 160Gb] +* @param cbs cbs桶深，单位KB，范围[1KB - 64M] +* 注：cbs=0 表示关闭整形,即不限速 +* @param mode_e 整形模式，0-获取c桶参数，1-获取对应e桶参数 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark +* @see +* @author xuhb @date 2020/09/22 +************************************************************/ +DPP_STATUS dpp_tm_shape_flow_para_array_get(DPP_DEV_T *dev, + ZXIC_UINT32 flow_id, + ZXIC_UINT32 mode, + DPP_TM_SHAPE_PARA_TABLE *p_flow_para_tbl) +{ + + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 flow_id_e = 0; + ZXIC_UINT32 table_id = 0; + ZXIC_UINT32 profile_id = 0; + + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), mode, 0, 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_flow_para_tbl); + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), flow_id, 0, DPP_ETM_Q_NUM - 1); + + flow_id_e = flow_id + DPP_ETM_Q_NUM; + + table_id = flow_id / 2048; + + /*获取流的profile_id*/ + if (mode) + { + table_id = flow_id_e / 2048; + rc = dpp_tm_shape_map_table_get(dev, flow_id_e, &profile_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_shape_map_table_get"); + } + else + { + rc = dpp_tm_shape_map_table_get(dev, flow_id, &profile_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_shape_map_table_get"); + + } + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), profile_id, 0, DPP_TM_SHAP_MAP_ID_MAX - 1); + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), table_id, 0, DPP_ETM_SHAP_TABEL_ID_MAX - 1); + p_flow_para_tbl->shape_cbs = g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][profile_id].shape_cbs; + p_flow_para_tbl->shape_cir = g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][profile_id].shape_cir; + + return DPP_OK; + +} + + + +#if 0 +/***********************************************************/ +/** 配置shap模块中 crd_grain授权价值 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param credit_value 授权价值，默认值是0x5feByte +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xuhb @date 2020/08/13 +************************************************************/ +DPP_STATUS dpp_tm_shap_crd_grain_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 credit_value) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_SHAP_CRD_GRAIN_T credit_val = {0}; + + credit_val.crd_grain = credit_value; + rc = dpp_reg_write(dev_id, + ETM_SHAP_CRD_GRAINr, + 0, + 0, + &credit_val); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + return DPP_OK; +} + +#endif +#endif + +#if ZXIC_REAL("TM_EXTEND_API") + +#if 0 +/***********************************************************/ +/** 打印队列空标志查询 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param qnum 配置的队列号 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author cy @date 2016/06/20 +************************************************************/ +DPP_STATUS dpp_tm_qlist_ept_flag_get_diag(ZXIC_UINT32 dev_id, ZXIC_UINT32 qnum) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 value = 0; + + rc = dpp_tm_qlist_ept_flag_get(dev_id, qnum, &value); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qlist_ept_flag_get"); + ZXIC_COMM_PRINT("qlist_ept_flag is %d\n", value); + + return DPP_OK; +} + + +/***********************************************************/ +/** 打印队列深度计数 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param qnum 配置的队列号 +* @param p_value 队列深度计数 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author cy @date 2016/06/20 +************************************************************/ +DPP_STATUS dpp_tm_qlist_r_bcnt_get_diag(ZXIC_UINT32 dev_id, ZXIC_UINT32 qnum) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 value = 0; + + rc = dpp_tm_qlist_r_bcnt_get(dev_id, qnum, &value); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qlist_r_bcnt_get"); + ZXIC_COMM_PRINT("qlist_r_bcnt is 0x%x\n", value); + + return DPP_OK; +} + +/***********************************************************/ +/** CMDSCH中分端口分优先级的BLOCK计数 +* @param dev_id 设备编号 +* @param pri +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author sun @date 2023/09/19 +************************************************************/ +DPP_STATUS dpp_tm_csch_r_block_cnt_get(ZXIC_UINT32 dev_id, + ZXIC_UINT32 pri, + ZXIC_UINT32 *p_value) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_CSCH_R_BLOCK_CNT_T csch_r_block_cnt = {0}; + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_value); + + rc = dpp_reg_read(dev_id, + ETM_QMU_CSCH_R_BLOCK_CNTr, + 0, + pri, + &csch_r_block_cnt); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + *p_value = csch_r_block_cnt.csch_r_block_cnt; + + return DPP_OK; +} + +/***********************************************************/ +/** 打印CMDSCH中分端口分优先级的BLOCK计数 +* @param dev_id 设备编号 +* @param port +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author sun @date 2023/09/19 +************************************************************/ +DPP_STATUS dpp_tm_csch_r_block_cnt_diag(ZXIC_UINT32 dev_id, ZXIC_UINT32 port) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 pri = 0; + ZXIC_UINT32 pri_th = 0; + for(int i = 0; i < 8; ++i) + { + pri = port * 8 + i; + rc = dpp_tm_csch_r_block_cnt_get(dev_id, pri, &pri_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_csch_r_block_cnt_get"); + ZXIC_COMM_PRINT("csch_r_block_pri 0x%x value is 0x%x\n", pri, pri_th); + } + + return DPP_OK; +} + +/***********************************************************/ +/** 打印队列入链状态 +* @param dev_id 设备编号 +* @param flow_id +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author sun @date 2023/09/19 +************************************************************/ +DPP_STATUS dpp_tm_crdt_flow_link_state_get_diag(ZXIC_UINT32 dev_id, ZXIC_UINT32 flow_id) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 link_status = 0; + DPP_ETM_CRDT_FLOWQUE_INS_TBL_T crdt_flow_ins_tbl_t = {0}; + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, flow_id, 0, DPP_ETM_CRDT_NUM); + rc = dpp_tm_crdt_flow_link_state_get(dev_id, flow_id, &crdt_flow_ins_tbl_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_crdt_flow_link_state_get"); + + link_status = crdt_flow_ins_tbl_t.flowque_ins; + ZXIC_COMM_PRINT("flowque_ins_tbl flow 0x%x linkstatus is 0x%x\n", flow_id, link_status); + + return DPP_OK; +} + +/***********************************************************/ +/** 打印调度器入链状态 +* @param dev_id 设备编号 +* @param flow_id +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author sun @date 2023/09/19 +************************************************************/ +DPP_STATUS dpp_tm_crdt_se_link_state_get_diag(ZXIC_UINT32 dev_id, ZXIC_UINT32 se_id) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 link_status = 0; + DPP_ETM_CRDT_SE_INS_TBL_T crdt_se_ins_tbl_t = {0}; + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, se_id, 0, DPP_ETM_FQSPWFQ_NUM - 1); + rc = dpp_tm_crdt_se_link_state_get(dev_id, se_id, &crdt_se_ins_tbl_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_crdt_se_link_state_get"); + + link_status = crdt_se_ins_tbl_t.se_ins_flag; + ZXIC_COMM_PRINT("flowque_ins_tbl se_id 0x%x linkstatus is 0x%x\n", se_id, link_status); + + return DPP_OK; +} + +/***********************************************************/ +/** 打印olif的fifo是否空状态 +* @param dev_id 设备编号 +* @param +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author sun @date 2023/09/19 +************************************************************/ +DPP_STATUS dpp_tm_olif_fifo_empty_state_get_diag(ZXIC_UINT32 dev_id) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 qmu_para_fifo_empty = 0; + ZXIC_UINT32 emem_empty = 0; + ZXIC_UINT32 imem_empty = 0; + DPP_ETM_OLIF_OLIF_FIFO_EMPTY_STATE_T empty_status = {0}; + + rc = dpp_reg_read(dev_id, + ETM_OLIF_OLIF_FIFO_EMPTY_STATEr, + 0, + 0, + &empty_status); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + qmu_para_fifo_empty = empty_status.qmu_para_fifo_empty; + emem_empty = empty_status.emem_empty; + imem_empty = empty_status.imem_empty; + ZXIC_COMM_PRINT("qmu_para_fifo_empty 0x%x, emem_empty 0x%x, imem_empty 0x%x\n", qmu_para_fifo_empty, emem_empty, imem_empty); + + return DPP_OK; +} + +/***********************************************************/ +/** +* @param dev_id +* @param tm_type +* @param que_id +* +* @return +* @remark 无 +* @see +* @author XXX @date 2019/05/08 +************************************************************/ +DPP_STATUS dpp_tm_crdt_eir_crs_filter_en_get_diag(ZXIC_UINT32 dev_id, ZXIC_UINT32 que_id) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CRDT_EIR_CRS_FILTER_TBL_T eir_crs_filter = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, que_id, 0, DPP_ETM_Q_NUM - 1); + + rc = dpp_reg_read(dev_id, + ETM_CRDT_EIR_CRS_FILTER_TBLr, + 0, + que_id, + &eir_crs_filter); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + ZXIC_COMM_PRINT("Tm type:%d [0:ftm 1:etm] eir_crs_filter_en:%d [1:enable 0:disable]", eir_crs_filter.eir_crs_filter); + + return rc; +} + + + +/***********************************************************/ +/** 读取指定队列获得授权个数(只打印授权非零的队列号) +* @param dev_id 设备编号 +* @param ackflow_start 授权起始流号 +* @param ackflow_end 授权终止流号 +* @param sleep_time_ms 等待时间 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author wush @date 2017/01/19 +************************************************************/ +DPP_STATUS dpp_etm_crdt_traffic_diag(ZXIC_UINT32 dev_id, + ZXIC_UINT32 ackflow_start, + ZXIC_UINT32 ackflow_end, + ZXIC_UINT32 sleep_time_ms) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 index = 0; + ZXIC_UINT32 ackflow_id = 0; + ZXIC_UINT32 credit_value = 0; + ZXIC_FLOAT traffic_amplified = 0.0; + ZXIC_FLOAT flow_spec_traffic = 0.0; + + DPP_ETM_CRDT_STAT_QUE_CREDIT_T que_credit = {0}; + DPP_TM_WORK_MODE_E sa_work_mode = {0}; + DPP_ETM_CRDT_STAT_QUE_ID_0_T stat_que_id_0 = {0}; + + if (ackflow_start > DPP_ETM_Q_NUM - 1) + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "ackflow_start is out of range!!!\n"); + return DPP_ERR; + } + + if (ackflow_end > DPP_ETM_Q_NUM - 1) + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "ackflow_end is out of range!!!\n"); + return DPP_ERR; + } + + rc = dpp_tm_cfgmt_sa_work_mode_get(dev_id, &sa_work_mode); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_sa_work_mode_get"); + + if (0 == sa_work_mode) + { + rc = dpp_tm_qmu_credit_value_get(dev_id, &credit_value); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_credit_value_get"); + } + else if (1 == sa_work_mode) + { + rc = dpp_tm_qmu_sa_credit_value_get(dev_id, 4, &credit_value); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_sa_credit_value_get"); + } + else + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "SA work mode error\n"); + return DPP_ERR; + } + + traffic_amplified = ((ZXIC_FLOAT)sleep_time_ms * (ZXIC_FLOAT)(1000000.0)) / ((ZXIC_FLOAT)(8.0) * (ZXIC_FLOAT)(credit_value)); + + for (ackflow_id = ackflow_start; ackflow_id <= ackflow_end; ackflow_id += 16) + { + /* 配置16条授权流 */ + for (index = 0; index < 16; index++) + { + + stat_que_id_0.stat_que_id_0 = ackflow_id + index; + rc = dpp_reg_write(dev_id, + ETM_CRDT_STAT_QUE_ID_0r + index, + 0, + 0, + &stat_que_id_0); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + } + + /* 授权个数统计计数器清零 */ + rc = dpp_tm_crdt_clr_diag(0); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_crdt_clr_diag"); + + zxic_comm_sleep(sleep_time_ms); + /* 不使能CRDT */ + rc = dpp_tm_crdt_credit_en_set(dev_id, 0); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_crdt_credit_en_set"); + + for (index = 0; index < 16; index++) + { + + rc = dpp_reg_read(dev_id, + ETM_CRDT_STAT_QUE_ID_0r + index, + 0, + 0, + &stat_que_id_0); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "DPP_reg_read"); + + rc = dpp_reg_read(dev_id, + ETM_CRDT_STAT_QUE_CREDITr, + 0, + index, + &que_credit); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "DPP_reg_read"); + + flow_spec_traffic = (ZXIC_FLOAT)(que_credit.stat_que_credit_cnt) / traffic_amplified; + + if (que_credit.stat_que_credit_cnt != 0) + { + ZXIC_COMM_PRINT("flow_0x%04x(%5d): ", (stat_que_id_0.stat_que_id_0), (stat_que_id_0.stat_que_id_0)); + ZXIC_COMM_PRINT("ack_cnt = 0x%08x, ", que_credit.stat_que_credit_cnt); + ZXIC_COMM_PRINT("traffic = %.6f.(G)\n", flow_spec_traffic); + } + } + } + + /* 使能CRDT */ + rc = dpp_tm_crdt_credit_en_set(dev_id, 1); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_crdt_credit_en_set"); + + return DPP_OK; +} + + + +/***********************************************************/ +/** 读取QMU所有队列的统计信息 +* @param dev_id 设备编号 +* @param p_para 获得的统计信息 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/03/04 +************************************************************/ +DPP_STATUS dpp_tm_qmu_stat_get(ZXIC_UINT32 dev_id, DPP_ETM_QMU_STAT_INFO_T *p_para) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_FC_CNT_MODE_T fc_cnt_mode_reg = {0}; + DPP_ETM_QMU_MMU_QMU_WR_FC_CNT_T mmu_qmu_wr_fc_cnt_reg = {0}; + DPP_ETM_QMU_MMU_QMU_RD_FC_CNT_T mmu_qmu_rd_fc_cnt_reg = {0}; + DPP_ETM_QMU_QMU_CGAVD_FC_CNT_T qmu_cgavd_fc_cnt_reg = {0}; + DPP_ETM_QMU_CGAVD_QMU_PKT_CNT_T cgavd_qmu_pkt_cnt_reg = {0}; + DPP_ETM_QMU_CGAVD_QMU_PKTLEN_ALL_T cgavd_qmu_pktlen_all_reg = {0}; + DPP_ETM_QMU_LAST_DROP_QNUM_GET_T last_drop_qnum_reg = {0}; + DPP_ETM_QMU_CRDT_QMU_CREDIT_CNT_T crdt_qmu_credit_cnt_reg = {0}; + DPP_ETM_QMU_QMU_TO_QSCH_REPORT_CNT_T qmu_to_qsch_report_cnt_reg = {0}; + DPP_ETM_QMU_QMU_TO_CGAVD_REPORT_CNT_T qmu_to_cgavd_report_cnt_reg = {0}; + DPP_ETM_QMU_QMU_CRDT_CRS_NORMAL_CNT_T qmu_crdt_crs_normal_cnt_reg = {0}; + DPP_ETM_QMU_QMU_CRDT_CRS_OFF_CNT_T qmu_crdt_crs_off_cnt_reg = {0}; + DPP_ETM_QMU_QSCH_QLIST_SHEDULE_CNT_T qsch_qlist_shedule_cnt_reg = {0}; + DPP_ETM_QMU_QSCH_QLIST_SCH_EPT_CNT_T qsch_qlist_sch_ept_cnt_reg = {0}; + DPP_ETM_QMU_QMU_TO_MMU_BLK_WR_CNT_T qmu_to_mmu_blk_wr_cnt_reg = {0}; + DPP_ETM_QMU_QMU_TO_CSW_BLK_RD_CNT_T qmu_to_csw_blk_rd_cnt_reg = {0}; + DPP_ETM_QMU_QMU_TO_MMU_SOP_WR_CNT_T qmu_to_mmu_sop_wr_cnt_reg = {0}; + DPP_ETM_QMU_QMU_TO_MMU_EOP_WR_CNT_T qmu_to_mmu_eop_wr_cnt_reg = {0}; + DPP_ETM_QMU_QMU_TO_MMU_DROP_WR_CNT_T qmu_to_mmu_drop_wr_cnt_reg = {0}; + DPP_ETM_QMU_QMU_TO_CSW_SOP_RD_CNT_T qmu_to_csw_sop_rd_cnt_reg = {0}; + DPP_ETM_QMU_QMU_TO_CSW_EOP_RD_CNT_T qmu_to_csw_eop_rd_cnt_reg = {0}; + DPP_ETM_QMU_QMU_TO_CSW_DROP_RD_CNT_T qmu_to_csw_drop_rd_cnt_reg = {0}; + DPP_ETM_QMU_MMU_TO_QMU_WR_RELEASE_CNT_T mmu_to_qmu_wr_release_cnt_reg = {0}; + DPP_ETM_QMU_MMU_TO_QMU_RD_RELEASE_CNT_T mmu_to_qmu_rd_release_cnt_reg = {0}; + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_para); + + rc = dpp_reg_read(dev_id, + ETM_QMU_FC_CNT_MODEr, + 0, + 0, + &fc_cnt_mode_reg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + rc = dpp_reg_read(dev_id, + ETM_QMU_MMU_QMU_WR_FC_CNTr, + 0, + 0, + &mmu_qmu_wr_fc_cnt_reg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + rc = dpp_reg_read(dev_id, + ETM_QMU_MMU_QMU_RD_FC_CNTr, + 0, + 0, + &mmu_qmu_rd_fc_cnt_reg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + rc = dpp_reg_read(dev_id, + ETM_QMU_QMU_CGAVD_FC_CNTr, + 0, + 0, + &qmu_cgavd_fc_cnt_reg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + rc = dpp_reg_read(dev_id, + ETM_QMU_CGAVD_QMU_PKT_CNTr, + 0, + 0, + &cgavd_qmu_pkt_cnt_reg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + rc = dpp_reg_read(dev_id, + ETM_QMU_CGAVD_QMU_PKTLEN_ALLr, + 0, + 0, + &cgavd_qmu_pktlen_all_reg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + rc = dpp_reg_read(dev_id, + ETM_QMU_LAST_DROP_QNUM_GETr, + 0, + 0, + &last_drop_qnum_reg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + rc = dpp_reg_read(dev_id, + ETM_QMU_CRDT_QMU_CREDIT_CNTr, + 0, + 0, + &crdt_qmu_credit_cnt_reg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + rc = dpp_reg_read(dev_id, + ETM_QMU_QMU_TO_QSCH_REPORT_CNTr, + 0, + 0, + &qmu_to_qsch_report_cnt_reg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + rc = dpp_reg_read(dev_id, + ETM_QMU_QMU_TO_CGAVD_REPORT_CNTr, + 0, + 0, + &qmu_to_cgavd_report_cnt_reg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + rc = dpp_reg_read(dev_id, + ETM_QMU_QMU_CRDT_CRS_NORMAL_CNTr, + 0, + 0, + &qmu_crdt_crs_normal_cnt_reg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + rc = dpp_reg_read(dev_id, + ETM_QMU_QMU_CRDT_CRS_OFF_CNTr, + 0, + 0, + &qmu_crdt_crs_off_cnt_reg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + rc = dpp_reg_read(dev_id, + ETM_QMU_QSCH_QLIST_SHEDULE_CNTr, + 0, + 0, + &qsch_qlist_shedule_cnt_reg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + rc = dpp_reg_read(dev_id, + ETM_QMU_QSCH_QLIST_SCH_EPT_CNTr, + 0, + 0, + &qsch_qlist_sch_ept_cnt_reg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + rc = dpp_reg_read(dev_id, + ETM_QMU_QMU_TO_MMU_BLK_WR_CNTr, + 0, + 0, + &qmu_to_mmu_blk_wr_cnt_reg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + rc = dpp_reg_read(dev_id, + ETM_QMU_QMU_TO_CSW_BLK_RD_CNTr, + 0, + 0, + &qmu_to_csw_blk_rd_cnt_reg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + rc = dpp_reg_read(dev_id, + ETM_QMU_QMU_TO_MMU_SOP_WR_CNTr, + 0, + 0, + &qmu_to_mmu_sop_wr_cnt_reg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + rc = dpp_reg_read(dev_id, + ETM_QMU_QMU_TO_MMU_EOP_WR_CNTr, + 0, + 0, + &qmu_to_mmu_eop_wr_cnt_reg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + rc = dpp_reg_read(dev_id, + ETM_QMU_QMU_TO_MMU_DROP_WR_CNTr, + 0, + 0, + &qmu_to_mmu_drop_wr_cnt_reg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + rc = dpp_reg_read(dev_id, + ETM_QMU_QMU_TO_CSW_SOP_RD_CNTr, + 0, + 0, + &qmu_to_csw_sop_rd_cnt_reg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + rc = dpp_reg_read(dev_id, + ETM_QMU_QMU_TO_CSW_EOP_RD_CNTr, + 0, + 0, + &qmu_to_csw_eop_rd_cnt_reg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + rc = dpp_reg_read(dev_id, + ETM_QMU_QMU_TO_CSW_DROP_RD_CNTr, + 0, + 0, + &qmu_to_csw_drop_rd_cnt_reg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + rc = dpp_reg_read(dev_id, + ETM_QMU_MMU_TO_QMU_WR_RELEASE_CNTr, + 0, + 0, + &mmu_to_qmu_wr_release_cnt_reg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + rc = dpp_reg_read(dev_id, + ETM_QMU_MMU_TO_QMU_RD_RELEASE_CNTr, + 0, + 0, + &mmu_to_qmu_rd_release_cnt_reg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + p_para->fc_cnt_mode = fc_cnt_mode_reg.fc_cnt_mode; + p_para->mmu_qmu_wr_fc_cnt = mmu_qmu_wr_fc_cnt_reg.mmu_qmu_wr_fc_cnt; + p_para->mmu_qmu_rd_fc_cnt = mmu_qmu_rd_fc_cnt_reg.mmu_qmu_rd_fc_cnt; + p_para->qmu_cgavd_fc_cnt = qmu_cgavd_fc_cnt_reg.qmu_cgavd_fc_cnt; + p_para->cgavd_qmu_pkt_cnt = cgavd_qmu_pkt_cnt_reg.cgavd_qmu_pkt_cnt; + p_para->cgavd_qmu_pktlen_all = cgavd_qmu_pktlen_all_reg.cgavd_qmu_pktlen_all; + p_para->cgavd_qmu_drop_tap = last_drop_qnum_reg.cgavd_qmu_drop_tap; + p_para->last_drop_qnum = last_drop_qnum_reg.last_drop_qnum; + p_para->crdt_qmu_credit_cnt = crdt_qmu_credit_cnt_reg.crdt_qmu_credit_cnt; + p_para->qmu_to_qsch_report_cnt = qmu_to_qsch_report_cnt_reg.qmu_to_qsch_report_cnt; + p_para->qmu_to_cgavd_report_cnt = qmu_to_cgavd_report_cnt_reg.qmu_to_cgavd_report_cnt; + p_para->qmu_crdt_crs_normal_cnt = qmu_crdt_crs_normal_cnt_reg.qmu_crdt_crs_normal_cnt; + p_para->qmu_crdt_crs_off_cnt = qmu_crdt_crs_off_cnt_reg.qmu_crdt_crs_off_cnt; + p_para->qsch_qlist_shedule_cnt = qsch_qlist_shedule_cnt_reg.qsch_qlist_shedule_cnt; + p_para->qsch_qlist_sch_ept_cnt = qsch_qlist_sch_ept_cnt_reg.qsch_qlist_sch_ept_cnt; + p_para->qmu_to_mmu_blk_wr_cnt = qmu_to_mmu_blk_wr_cnt_reg.qmu_to_mmu_blk_wr_cnt; + p_para->qmu_to_csw_blk_rd_cnt = qmu_to_csw_blk_rd_cnt_reg.qmu_to_csw_blk_rd_cnt; + p_para->qmu_to_mmu_sop_wr_cnt = qmu_to_mmu_sop_wr_cnt_reg.qmu_to_mmu_sop_wr_cnt; + p_para->qmu_to_mmu_eop_wr_cnt = qmu_to_mmu_eop_wr_cnt_reg.qmu_to_mmu_eop_wr_cnt; + p_para->qmu_to_mmu_drop_wr_cnt = qmu_to_mmu_drop_wr_cnt_reg.qmu_to_mmu_drop_wr_cnt; + p_para->qmu_to_csw_sop_rd_cnt = qmu_to_csw_sop_rd_cnt_reg.qmu_to_csw_sop_rd_cnt; + p_para->qmu_to_csw_eop_rd_cnt = qmu_to_csw_eop_rd_cnt_reg.qmu_to_csw_eop_rd_cnt; + p_para->qmu_to_csw_drop_rd_cnt = qmu_to_csw_drop_rd_cnt_reg.qmu_to_csw_drop_rd_cnt; + p_para->mmu_to_qmu_wr_release_cnt = mmu_to_qmu_wr_release_cnt_reg.mmu_to_qmu_wr_release_cnt; + p_para->mmu_to_qmu_rd_release_cnt = mmu_to_qmu_rd_release_cnt_reg.mmu_to_qmu_rd_release_cnt; + + return DPP_OK; + +} + + +/***********************************************************/ +/** 读取QMU指定队列的计数信息 +* @param dev_id 设备编号 +* @param p_para 获得的统计信息 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/03/04 +************************************************************/ +DPP_STATUS dpp_tm_qmu_spec_q_stat_get(ZXIC_UINT32 dev_id, DPP_ETM_QMU_SPEC_Q_STAT_INFO_T *p_para) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_OBSERVE_PORTFC_SPEC_T observe_portfc_spec_reg = {0}; + DPP_ETM_QMU_SPEC_LIF_PORTFC_COUNT_T spec_lif_portfc_count_reg = {0}; + DPP_ETM_QMU_OBSERVE_QNUM_SET_T observe_qnum_set_reg = {0}; + DPP_ETM_QMU_SPEC_Q_PKT_RECEIVED_T spec_q_pkt_received_reg = {0}; + DPP_ETM_QMU_SPEC_Q_PKT_DROPPED_T spec_q_pkt_dropped_reg = {0}; + DPP_ETM_QMU_SPEC_Q_PKT_SCHEDULED_T spec_q_pkt_scheduled_reg = {0}; + DPP_ETM_QMU_SPEC_Q_WR_CMD_SENT_T spec_q_wr_cmd_sent_reg = {0}; + DPP_ETM_QMU_SPEC_Q_RD_CMD_SENT_T spec_q_rd_cmd_sent_reg = {0}; + DPP_ETM_QMU_SPEC_Q_PKT_ENQ_T spec_q_pkt_enq_reg = {0}; + DPP_ETM_QMU_SPEC_Q_PKT_DEQ_T spec_q_pkt_deq_reg = {0}; + DPP_ETM_QMU_SPEC_Q_CRDT_UNCON_RECEIVED_T spec_q_crdt_uncon_received_reg = {0}; + DPP_ETM_QMU_SPEC_Q_CRDT_CONG_RECEIVED_T spec_q_crdt_cong_received_reg = {0}; + DPP_ETM_QMU_SPEC_Q_CRS_NORMAL_CNT_T spec_q_crs_normal_cnt_reg = {0}; + DPP_ETM_QMU_SPEC_Q_CRS_OFF_CNT_T spec_q_crs_off_cnt_reg = {0}; + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_para); + + rc = dpp_reg_read(dev_id, + ETM_QMU_OBSERVE_PORTFC_SPECr, + 0, + 0, + &observe_portfc_spec_reg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + rc = dpp_reg_read(dev_id, + ETM_QMU_SPEC_LIF_PORTFC_COUNTr, + 0, + 0, + &spec_lif_portfc_count_reg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + rc = dpp_reg_read(dev_id, + ETM_QMU_OBSERVE_QNUM_SETr, + 0, + 0, + &observe_qnum_set_reg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + rc = dpp_reg_read(dev_id, + ETM_QMU_SPEC_Q_PKT_RECEIVEDr, + 0, + 0, + &spec_q_pkt_received_reg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + rc = dpp_reg_read(dev_id, + ETM_QMU_SPEC_Q_PKT_DROPPEDr, + 0, + 0, + &spec_q_pkt_dropped_reg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + rc = dpp_reg_read(dev_id, + ETM_QMU_SPEC_Q_PKT_SCHEDULEDr, + 0, + 0, + &spec_q_pkt_scheduled_reg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + rc = dpp_reg_read(dev_id, + ETM_QMU_SPEC_Q_WR_CMD_SENTr, + 0, + 0, + &spec_q_wr_cmd_sent_reg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + rc = dpp_reg_read(dev_id, + ETM_QMU_SPEC_Q_RD_CMD_SENTr, + 0, + 0, + &spec_q_rd_cmd_sent_reg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + rc = dpp_reg_read(dev_id, + ETM_QMU_SPEC_Q_PKT_ENQr, + 0, + 0, + &spec_q_pkt_enq_reg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + rc = dpp_reg_read(dev_id, + ETM_QMU_SPEC_Q_PKT_DEQr, + 0, + 0, + &spec_q_pkt_deq_reg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + rc = dpp_reg_read(dev_id, + ETM_QMU_SPEC_Q_CRDT_UNCON_RECEIVEDr, + 0, + 0, + &spec_q_crdt_uncon_received_reg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + rc = dpp_reg_read(dev_id, + ETM_QMU_SPEC_Q_CRDT_CONG_RECEIVEDr, + 0, + 0, + &spec_q_crdt_cong_received_reg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + rc = dpp_reg_read(dev_id, + ETM_QMU_SPEC_Q_CRS_NORMAL_CNTr, + 0, + 0, + &spec_q_crs_normal_cnt_reg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + rc = dpp_reg_read(dev_id, + ETM_QMU_SPEC_Q_CRS_OFF_CNTr, + 0, + 0, + &spec_q_crs_off_cnt_reg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + p_para->observe_portfc_spec = observe_portfc_spec_reg.observe_portfc_spec; + p_para->spec_lif_portfc_count = spec_lif_portfc_count_reg.spec_lif_portfc_count; + p_para->observe_qnum_set = observe_qnum_set_reg.observe_qnum_set; + p_para->spec_q_pkt_received = spec_q_pkt_received_reg.spec_q_pkt_received; + p_para->spec_q_pkt_dropped = spec_q_pkt_dropped_reg.spec_q_pkt_dropped; + p_para->spec_q_pkt_scheduled = spec_q_pkt_scheduled_reg.spec_q_pkt_scheduled; + p_para->spec_q_wr_cmd_sent = spec_q_wr_cmd_sent_reg.spec_q_wr_cmd_sent; + p_para->spec_q_rd_cmd_sent = spec_q_rd_cmd_sent_reg.spec_q_rd_cmd_sent; + p_para->spec_q_pkt_enq = spec_q_pkt_enq_reg.spec_q_pkt_enq; + p_para->spec_q_pkt_deq = spec_q_pkt_deq_reg.spec_q_pkt_deq; + p_para->spec_q_crdt_uncon_received = spec_q_crdt_uncon_received_reg.spec_q_crdt_uncon_received; + p_para->spec_q_crdt_cong_received = spec_q_crdt_cong_received_reg.spec_q_crdt_cong_received; + p_para->spec_q_crs_normal_cnt = spec_q_crs_normal_cnt_reg.spec_q_crs_normal_cnt; + p_para->spec_q_crs_off_cnt = spec_q_crs_off_cnt_reg.spec_q_crs_off_cnt; + + return DPP_OK; + +} + +/***********************************************************/ +/** 读取QMU指定队列组的计数信息 +* @param dev_id 设备编号 +* @param p_para 获得的统计信息 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/03/04 +************************************************************/ +DPP_STATUS dpp_tm_qmu_spec_bat_stat_get(ZXIC_UINT32 dev_id, DPP_ETM_QMU_SPEC_BAT_STAT_INFO_T *p_para) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_QMU_OBSERVE_BATCH_SET_T observe_batch_set_reg = {0}; + DPP_ETM_QMU_SPEC_BAT_PKT_RECEIVED_T spec_bat_pkt_received_reg = {0}; + DPP_ETM_QMU_SPEC_BAT_PKT_DROPPED_T spec_bat_pkt_dropped_reg = {0}; + DPP_ETM_QMU_SPEC_BAT_BLK_SCHEDULED_T spec_bat_blk_scheduled_reg = {0}; + DPP_ETM_QMU_SPEC_BAT_WR_CMD_SENT_T spec_bat_wr_cmd_sent_reg = {0}; + DPP_ETM_QMU_SPEC_BAT_RD_CMD_SENT_T spec_bat_rd_cmd_sent_reg = {0}; + DPP_ETM_QMU_SPEC_BAT_PKT_ENQ_T spec_bat_pkt_enq_reg = {0}; + DPP_ETM_QMU_SPEC_BAT_PKT_DEQ_T spec_bat_pkt_deq_reg = {0}; + DPP_ETM_QMU_SPEC_BAT_CRDT_UNCON_RECEIVED_T spec_bat_crdt_uncon_received_reg = {0}; + DPP_ETM_QMU_SPEC_BAT_CRDT_CONG_RECEIVED_T spec_bat_crdt_cong_received_reg = {0}; + DPP_ETM_QMU_SPEC_BAT_CRS_NORMAL_CNT_T spec_bat_crs_normal_cnt_reg = {0}; + DPP_ETM_QMU_SPEC_BAT_CRS_OFF_CNT_T spec_bat_crs_off_cnt_reg = {0}; + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_para); + + rc = dpp_reg_read(dev_id, + ETM_QMU_OBSERVE_BATCH_SETr, + 0, + 0, + &observe_batch_set_reg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + rc = dpp_reg_read(dev_id, + ETM_QMU_SPEC_BAT_PKT_RECEIVEDr, + 0, + 0, + &spec_bat_pkt_received_reg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + rc = dpp_reg_read(dev_id, + ETM_QMU_SPEC_BAT_PKT_DROPPEDr, + 0, + 0, + &spec_bat_pkt_dropped_reg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + rc = dpp_reg_read(dev_id, + ETM_QMU_SPEC_BAT_BLK_SCHEDULEDr, + 0, + 0, + &spec_bat_blk_scheduled_reg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + rc = dpp_reg_read(dev_id, + ETM_QMU_SPEC_BAT_WR_CMD_SENTr, + 0, + 0, + &spec_bat_wr_cmd_sent_reg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + rc = dpp_reg_read(dev_id, + ETM_QMU_SPEC_BAT_RD_CMD_SENTr, + 0, + 0, + &spec_bat_rd_cmd_sent_reg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + rc = dpp_reg_read(dev_id, + ETM_QMU_SPEC_BAT_PKT_ENQr, + 0, + 0, + &spec_bat_pkt_enq_reg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + rc = dpp_reg_read(dev_id, + ETM_QMU_SPEC_BAT_PKT_DEQr, + 0, + 0, + &spec_bat_pkt_deq_reg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + rc = dpp_reg_read(dev_id, + ETM_QMU_SPEC_BAT_CRDT_UNCON_RECEIVEDr, + 0, + 0, + &spec_bat_crdt_uncon_received_reg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + rc = dpp_reg_read(dev_id, + ETM_QMU_SPEC_BAT_CRDT_CONG_RECEIVEDr, + 0, + 0, + &spec_bat_crdt_cong_received_reg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + rc = dpp_reg_read(dev_id, + ETM_QMU_SPEC_BAT_CRS_NORMAL_CNTr, + 0, + 0, + &spec_bat_crs_normal_cnt_reg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + rc = dpp_reg_read(dev_id, + ETM_QMU_SPEC_BAT_CRS_OFF_CNTr, + 0, + 0, + &spec_bat_crs_off_cnt_reg); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + + p_para->observe_batch_set = observe_batch_set_reg.observe_batch_set; + p_para->spec_bat_pkt_received = spec_bat_pkt_received_reg.spec_bat_pkt_received; + p_para->spec_bat_pkt_dropped = spec_bat_pkt_dropped_reg.spec_bat_pkt_dropped; + p_para->spec_bat_blk_scheduled = spec_bat_blk_scheduled_reg.spec_bat_blk_scheduled; + p_para->spec_bat_wr_cmd_sent = spec_bat_wr_cmd_sent_reg.spec_bat_wr_cmd_sent; + p_para->spec_bat_rd_cmd_sent = spec_bat_rd_cmd_sent_reg.spec_bat_rd_cmd_sent; + p_para->spec_bat_pkt_enq = spec_bat_pkt_enq_reg.spec_bat_pkt_enq; + p_para->spec_bat_pkt_deq = spec_bat_pkt_deq_reg.spec_bat_pkt_deq; + p_para->spec_bat_crdt_uncon_received = spec_bat_crdt_uncon_received_reg.spec_bat_crdt_uncon_received; + p_para->spec_bat_crdt_cong_received = spec_bat_crdt_cong_received_reg.spec_bat_crdt_cong_received; + p_para->spec_bat_crs_normal_cnt = spec_bat_crs_normal_cnt_reg.spec_bat_crs_normal_cnt; + p_para->spec_bat_crs_off_cnt = spec_bat_crs_off_cnt_reg.spec_bat_crs_off_cnt; + + return DPP_OK; + +} + +/***********************************************************/ +/** 连续配置各级搬移门限 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param level 拥塞避免支持层次号，0:队列级，1:端口级，2:系统级 +* @param start_id 为起始 队列号或端口号，系统级时，id参数无效 +* @param value 端口级和系统级时，为搬移门限值，单位为NPPU存包的单位，256B； + 流级时为搬移profile_id,0~15 +* @param num 为队列或端口个数 +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author wush @date 2016/11/19 +************************************************************/ +#ifdef ETM_REAL +DPP_STATUS dpp_tm_cgavd_move_th_together_wr(ZXIC_UINT32 dev_id, + DPP_TM_CGAVD_LEVEL_E level, + ZXIC_UINT32 start_id, + ZXIC_UINT32 value, + ZXIC_UINT32 num) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 i = 0; + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, level, QUEUE_LEVEL, SYS_LEVEL); + + + for (i = 0; i < num; i++) + { + ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW(start_id, i); + rc = dpp_tm_cgavd_move_th_set(dev_id, level, start_id + i, value); + zxic_comm_usleep(100); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_move_th_set"); + + } + + return DPP_OK; + +} +#endif +#endif +/***********************************************************/ +/** 连续设置多个队列或端口的TD门限 +* @param level 层次号，0:队列级，1:端口级 +* @param tm_type 0-ETM,1-FTM +* @param id 起始队列号或端口号 +* @param td_th TD门限，单位是KB，转换为block写入寄存器 +* @param num 需要设置的队列或端口数量 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/17 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_td_th_together_wr(DPP_DEV_T *dev, + ZXIC_UINT32 level, + ZXIC_UINT32 id, + ZXIC_UINT32 td_th, + ZXIC_UINT32 num) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 i = 0; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), level, QUEUE_LEVEL, PP_LEVEL); + ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(DEV_ID(dev), id , num); + + for (i = 0; i < num; i++) + { + rc = dpp_tm_cgavd_td_th_set(dev, level, id + i, td_th); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_cgavd_td_th_set"); + } + + return DPP_OK; + +} + + +/***********************************************************/ +/** 连续获取多个队列或端口的TD门限 +* @param level 层次号，0:队列级，1:端口级 +* @param tm_type 0-ETM,1-FTM +* @param level 拥塞避免支持层次号，0:队列级，1:端口级，2:系统级 +* @param id 起始队列号或端口号 +* @param num 需要设置的队列或端口数量 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cy @date 2016/03/22 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_td_th_together_get(DPP_DEV_T *dev, + ZXIC_UINT32 level, + ZXIC_UINT32 id, + ZXIC_UINT32 num) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 i = 0; + ZXIC_UINT32 td_th = 0; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), level, QUEUE_LEVEL, PP_LEVEL); + ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(DEV_ID(dev), id , num); + + for (i = 0; i < num; i++) + { + rc = dpp_tm_cgavd_td_th_get(dev, level, id + i, &td_th); + zxic_comm_delay(5); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_cgavd_td_th_get"); + + ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(DEV_ID(dev), id , i); + if (level == QUEUE_LEVEL) + { + ZXIC_COMM_PRINT(" flow_id: 0x%x, td_th: 0x%x\n", id + i, td_th); + } + else + { + ZXIC_COMM_PRINT(" pp_id: 0x%x, td_th: 0x%x\n", id + i, td_th); + } + + } + + return DPP_OK; + +} + +/***********************************************************/ +/** 连续配置多个队列或端口是否支持动态门限机制 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param level WRED支持层次号，0:队列级，1:端口级 +* @param id 队列号或端口号 +* @param en 配置的值，0-不支持动态门限机制，1-支持动态门限机制 +* @param num 连续配置的队列数 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author djf @date 2014/02/17 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_dyn_th_en_set_more(DPP_DEV_T *dev, + DPP_TM_CGAVD_LEVEL_E level, + ZXIC_UINT32 id, + ZXIC_UINT32 en, + ZXIC_UINT32 num) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 i = 0; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), level, QUEUE_LEVEL, PP_LEVEL); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), en, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(DEV_ID(dev), id , num); + + for (i = 0; i < num; i++) + { + rc = dpp_tm_cgavd_dyn_th_en_set(dev, level, id + i, en); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_cgavd_dyn_th_en_set"); + + } + + return DPP_OK; + +} + +#if 0 +/***********************************************************/ +/** 配置各级WRED丢弃曲线对应的参数 +* @param tm_type 0-ETM,1-FTM +* @param level WRED支持层次号，0:队列级，1:端口级 +* @param wred_id 队列级共支持16个WRED组0-15，端口级支持8组0-7 +* @param dp 共支持8个dp，取值0-7 +* @param max_th 平均队列深度上限阈值 +* @param min_th 平均队列深度下限阈值 +* @param max_p 最大丢弃概率 +* @param weight 平均队列深度计算权重 +* @param q_len_th 队列深度阈值 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author taq @date 2015/04/20 +************************************************************/ +DPP_STATUS dpp_tm_wred_dp_line_para_wr(ZXIC_UINT32 dev_id, + ZXIC_UINT32 level, + ZXIC_UINT32 wred_id, + ZXIC_UINT32 dp, + ZXIC_UINT32 max_th, + ZXIC_UINT32 min_th, + ZXIC_UINT32 max_p, + ZXIC_UINT32 weight, + ZXIC_UINT32 q_len_th) +{ + DPP_STATUS rc = DPP_OK; + DPP_TM_WRED_DP_LINE_PARA_T para = {0}; + + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, level, QUEUE_LEVEL, PP_LEVEL); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, dp, 0, DPP_TM_DP_NUM - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, max_p, 1, DPP_TM_RED_P_MAX); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, weight, 0, DPP_TM_CGAVD_WEIGHT_MAX); + + if (QUEUE_LEVEL == level) + { + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, wred_id, 0, DPP_TM_Q_WRED_NUM - 1); + } + else + { + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, wred_id, 0, DPP_TM_PP_WRED_NUM - 1); + } + + para.max_th = max_th; + para.min_th = min_th; + para.max_p = max_p; + para.weight = weight; + para.q_len_th = q_len_th; + + rc = dpp_tm_cgavd_wred_dp_line_para_set(dev_id, level, wred_id, dp, ¶); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_wred_dp_line_para_set"); + + return DPP_OK; + +} + + +/***********************************************************/ +/** 配置各级WRED丢弃曲线对应的参数 +* @param tm_type 0-ETM,1-FTM +* @param level WRED支持层次号，0:队列级，1:端口级 +* @param wred_id 队列级共支持16个WRED组0-15，端口级支持8组0-7 +* @param dp 共支持8个dp，取值0-7 +* @param max_th 平均队列深度上限阈值 +* @param min_th 平均队列深度下限阈值 +* @param max_p 最大丢弃概率 +* @param weight 平均队列深度计算权重 +* @param q_len_th 队列深度阈值 +* @param flag 忽略乘法里的当前包长和最大包长比标志位:1为忽略 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cy @date 2015/11/9 +************************************************************/ +DPP_STATUS dpp_tm_wred_dp_line_para_flag_wr(ZXIC_UINT32 dev_id, + ZXIC_UINT32 level, + ZXIC_UINT32 wred_id, + ZXIC_UINT32 dp, + ZXIC_UINT32 max_th, + ZXIC_UINT32 min_th, + ZXIC_UINT32 max_p, + ZXIC_UINT32 weight, + ZXIC_UINT32 q_len_th, + ZXIC_UINT32 flag) +{ + DPP_STATUS rc = DPP_OK; + DPP_TM_WRED_DP_LINE_PARA_T para = {0}; + DPP_ETM_CGAVD_PKE_LEN_CALC_SIGN_T cgavd_pke_len_calc_sign = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, level, QUEUE_LEVEL, PP_LEVEL); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, dp, 0, DPP_TM_DP_NUM - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, max_p, 1, DPP_TM_RED_P_MAX); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, weight, 0, DPP_TM_CGAVD_WEIGHT_MAX); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, flag, 0, 1); + + if (QUEUE_LEVEL == level) + { + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, wred_id, 0, DPP_TM_Q_WRED_NUM - 1); + } + else + { + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, wred_id, 0, DPP_TM_PP_WRED_NUM - 1); + } + + para.max_th = max_th; + para.min_th = min_th; + para.max_p = max_p; + para.weight = weight; + para.q_len_th = q_len_th; + + cgavd_pke_len_calc_sign.pke_len_calc_sign = flag; + rc = dpp_reg_write(dev_id, + ETM_CGAVD_PKE_LEN_CALC_SIGNr, + 0, + 0, + &cgavd_pke_len_calc_sign); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + rc = dpp_tm_cgavd_wred_dp_line_para_set(dev_id, level, wred_id, dp, ¶); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_wred_dp_line_para_set"); + + return DPP_OK; + +} + + +/***********************************************************/ +/** 配置CPU设置的报文长度是否参与计算丢弃概率的使能 +* @param tm_type 0-ETM,1-FTM +* @param flag 忽略乘法里的当前包长和最大包长比标志位:1为忽略 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cy @date 2015/11/9 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_wred_pke_len_calc_sign_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 flag) +{ + DPP_STATUS rc = DPP_OK; + + DPP_ETM_CGAVD_PKE_LEN_CALC_SIGN_T cgavd_pke_len_calc_sign = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, flag, 0, 1); + + cgavd_pke_len_calc_sign.pke_len_calc_sign = flag; + rc = dpp_reg_write(dev_id, + ETM_CGAVD_PKE_LEN_CALC_SIGNr, + 0, + 0, + &cgavd_pke_len_calc_sign); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + return DPP_OK; + +} + + +/***********************************************************/ +/** 获取配置CPU设置的报文长度是否参与计算丢弃概率的使能 +* @param tm_type 0-ETM,1-FTM +* @param flag 忽略乘法里的当前包长和最大包长比标志位:1为忽略 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cy @date 2015/11/9 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_wred_pke_len_calc_sign_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_flag) +{ + DPP_STATUS rc = DPP_OK; + + DPP_ETM_CGAVD_PKE_LEN_CALC_SIGN_T cgavd_pke_len_calc_sign = {0}; + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_flag); + + rc = dpp_reg_read(dev_id, + ETM_CGAVD_PKE_LEN_CALC_SIGNr, + 0, + 0, + &cgavd_pke_len_calc_sign); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + *p_flag = cgavd_pke_len_calc_sign.pke_len_calc_sign; + + return DPP_OK; + +} + +/***********************************************************/ +/** 配置系统级GRED丢弃曲线对应的参数 +* @param tm_type 0-ETM,1-FTM +* @param dp 共支持8个dp，取值0-7 +* @param max_th 平均队列深度上限阈值 +* @param mid_th 平均队列深度中间阈值 +* @param min_th 平均队列深度下限阈值 +* @param max_p 最大丢弃概率 1~99 +* @param weight 平均队列深度计算权重 +* @param q_len_th 队列深度阈值 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author taq @date 2015/04/20 +************************************************************/ +DPP_STATUS dpp_tm_gred_dp_line_para_wr(ZXIC_UINT32 dev_id, + ZXIC_UINT32 dp, + ZXIC_UINT32 max_th, + ZXIC_UINT32 mid_th, + ZXIC_UINT32 min_th, + ZXIC_UINT32 max_p, + ZXIC_UINT32 weight, + ZXIC_UINT32 q_len_th) +{ + DPP_STATUS rc = DPP_OK; + DPP_TM_GRED_DP_LINE_PARA_T para = {0}; + + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, dp, 0, DPP_TM_DP_NUM - 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, max_p, 1, DPP_TM_RED_P_MAX); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, weight, 0, DPP_TM_CGAVD_WEIGHT_MAX); + + para.max_th = max_th; + para.mid_th = mid_th; + para.min_th = min_th; + para.max_p = max_p; + + + para.weight = weight; + para.q_len_th = q_len_th; + + rc = dpp_tm_cgavd_gred_dp_line_para_set(dev_id, dp, ¶); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_gred_dp_line_para_set"); + + + return DPP_OK; + +} + + + +/***********************************************************/ +/** 配置olif统计组信息 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param id olif统计组号 +* @param all_or_by_port 0-统计所有，1-统计某一端口或某一dest_id +* @param i_or_e_sel 10-统计片外，01-统计片内，其他值-统计所有 +* @param port_or_dest_id_sel 0-统计port，1-统计dest_id +* @param port_dest_id port号或dest_id号 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author cuiy @date 2016/04/21 +************************************************************/ +DPP_STATUS dpp_tm_olif_stat_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 id, + ZXIC_UINT32 all_or_by_port, + ZXIC_UINT32 i_or_e_sel, + ZXIC_UINT32 port_or_dest_id_sel, + ZXIC_UINT32 port_dest_id) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_OLIF_TM_LIF_STAT_CFG_T tm_lif_stat_cft = {0}; + + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, id, 0, 15); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, all_or_by_port, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, i_or_e_sel, 0, 3); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, port_or_dest_id_sel, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, port_dest_id, 0, 255); + + + tm_lif_stat_cft.all_or_by_port = all_or_by_port; + tm_lif_stat_cft.i_or_e_sel = i_or_e_sel; + tm_lif_stat_cft.port_or_dest_id_sel = port_or_dest_id_sel; + tm_lif_stat_cft.port_dest_id = port_dest_id; + rc = dpp_reg_write(dev_id, + ETM_OLIF_TM_LIF_STAT_CFGr, + 0, + id, + &tm_lif_stat_cft); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + return DPP_OK; +} + +/***********************************************************/ +/** +* @param dev_id +* @param tm_type +* @param i_or_e_sel +* @param port_or_dest_id_sel +* @param start_id +* @param start_port_dest_id +* @param num +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xjw @date 2018/02/01 +************************************************************/ +DPP_STATUS dpp_tm_olif_stat_set_mul(ZXIC_UINT32 dev_id, + ZXIC_UINT32 i_or_e_sel, + ZXIC_UINT32 port_or_dest_id_sel, + ZXIC_UINT32 start_id, + ZXIC_UINT32 start_port_dest_id, + ZXIC_UINT32 num) +{ + DPP_STATUS rt = DPP_OK; + ZXIC_UINT32 i = 0; + + for (i = 0; i < num; i++) + { + ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(dev_id, start_port_dest_id, i); + ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(dev_id, start_id , i); + + rt = dpp_tm_olif_stat_set(dev_id, start_id + i, + 1, i_or_e_sel, port_or_dest_id_sel, start_port_dest_id + i); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rt, "dpp_reg_write"); + } + + return rt; +} + +DPP_STATUS dpp_tm_mr_init(ZXIC_UINT32 dev_id) +{ + DPP_STATUS rc = DPP_OK; + rc = dpp_tm_qmu_qos_sign_set(dev_id, 0, 0); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_qos_sign_set"); + rc = dpp_tm_cgavd_q_map_pp_set(dev_id, 0, 60); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_q_map_pp_set"); + rc = dpp_tm_cgavd_td_byte_block_th_get_diag(dev_id, 1, 60); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_td_byte_block_th_get_diag"); + rc = dpp_tm_cgavd_td_byte_block_th_set(dev_id, 0, 0, 1024); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_td_byte_block_th_set"); + rc = dpp_tm_cgavd_td_th_set(dev_id, 0, 0, 200); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_td_th_set"); + // rc = dpp_tm_shape_pp_para_wr(dev_id, 60, 1000000, 1000, 1); + // ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_shape_pp_para_wr"); + rc = dpp_tm_qmu_port_shape_set(dev_id, 60, 4, 31, 8192, 1); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_port_shape_set"); + + return rc; +} + +#if 0 +/***********************************************************/ +/** 配置TM模式下初始化代码 +* @param dev_id +* @param tm_type 0-ETM,1-FTM +* @param p_tm_init_info 配置TM模式下初始化信息包括以下 +* blk_size 配置qmu block大小：512B[default]/1024B +* case_num QMU初始化场景编号：0/1/2/3... +* imem_omem; 0-片内外混合; 1-纯片内;2-纯片外 +* mode 0-TM; 1-SA +* +* @return +* @remark 无 +* @see +* @author whuashan @date 2015/03/26 +************************************************************/ +DPP_STATUS dpp_tm_asic_init(ZXIC_UINT32 dev_id, DPP_TM_ASIC_INIT_INFO_T *p_tm_asic_init_info) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 case_num = 0; + ZXIC_UINT32 blk_size = 0; + ZXIC_UINT32 imem_omem = 0; + ZXIC_UINT32 mode = 0; + //ZXIC_UINT32 port_id = 0; + /*ZXIC_UINT32 flow_id_index = 0;*/ + ZXIC_UINT32 index = 0; + ZXIC_UINT32 sys_cgavd_td = 0; + DPP_TM_CNT_MODE_T cfgmt_count_mode = {0}; + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_tm_asic_init_info); + +/* + if (tm_type == DPP_ETM) + { + flow_id_index = DPP_ETM_Q_NUM; + } + else if (tm_type == DPP_FTM) + { + flow_id_index = DPP_FTM_Q_NUM; + } +*/ + case_num = p_tm_asic_init_info->case_num; + ZXIC_COMM_PRINT("case_num =:%d TM ASIC INIT START! <======\n", case_num); + blk_size = p_tm_asic_init_info->blk_size; + imem_omem = p_tm_asic_init_info->imem_omem; + mode = p_tm_asic_init_info->mode; + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, mode, 0, 1); + + ZXIC_COMM_PRINT("======>dev_id:%d TM ASIC INIT START! <======\n", dev_id); + + /*开启tm时钟门控使能*/ + rc = dpp_tm_cfgmt_clkgate_en_set(dev_id, 1); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_clkgate_en_set"); + ZXIC_COMM_PRINT("DPP tm clk enable ok\n"); + zxic_comm_sleep(5); + /*开启tm软复位使能*/ + rc = dpp_tm_cfgmt_softrst_en_set(dev_id, 1); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_softrst_en_set"); + ZXIC_COMM_PRINT("DPP tm softrst enable ok\n"); + zxic_comm_sleep(5); + + + DPP_ETM_CFGMT_CLKGATE_EN_T timeout = {0}; + timeout.clkgate_en = 0xfff; + rc = dpp_reg_write(dev_id, + ETM_CFGMT_TIMEOUT_LIMITr, + 0, + 0, + &timeout); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + + + /* 整包和交织模式:TM模式配置成交织模式 */ + rc = dpp_tm_qmu_pkt_blk_mode_set(dev_id, 0); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_pkt_blk_mode_set"); + ZXIC_COMM_PRINT("DPP tm mode cfg ok\n"); + + /* 配置block大小 */ + rc = dpp_tm_cfgmt_blk_size_set(dev_id, blk_size); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_blk_size_set"); + + /* 启动包存储CRC使能 */ + rc = dpp_tm_cfgmt_crc_en_set(dev_id, 1); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_crc_en_set"); + + /* 配置QMU的每chunk节点数：目前配置1chk=8 block */ + rc = dpp_tm_cfgmt_qmu_work_mode_set(dev_id, 0); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_qmu_work_mode_set"); + ZXIC_COMM_PRINT("DPP tm qmu_work_mode_set ok\n"); + /* 计数模式配置 */ + cfgmt_count_mode.fc_count_mode = 1; /* 翻转 */ + cfgmt_count_mode.count_rd_mode = 0; /* 非读清 */ + cfgmt_count_mode.count_overflow_mode = 1; /* 允许溢出翻转 */ + rc = dpp_tm_cfgmt_cnt_mode_set(dev_id, &cfgmt_count_mode); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_cnt_mode_set"); + + /* 总缓存字节数=节点数量*节点大小ftm256k etm512k:配置总缓存90% */ + sys_cgavd_td = (512 * 1024) * blk_size; + sys_cgavd_td = sys_cgavd_td / 1024; + sys_cgavd_td = sys_cgavd_td / 100 * 90; + rc = dpp_tm_cgavd_td_th_set(dev_id, SYS_LEVEL, 0, sys_cgavd_td); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_td_th_set"); + + /* 纯片内模式 */ + dpp_tm_tmmu_imem_en_set(dev_id, 1); + dpp_tm_cgavd_imem_omem_set(dev_id, 1, 0); + dpp_tm_tmmu_ddr_force_rdy_set(dev_id, 0x3ff); + + /* QMU链表配置：保证16K配置 */ + rc = dpp_tm_qmu_init_set(dev_id, 0); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_init_set"); + + /* 空队列确保门限值配置 */ + rc = dpp_tm_qmu_crs_th2_set(dev_id, 0, 200); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_crs_th2_set"); + + /*crs的e桶产生门限:每个队列可映射16种配置， + 映射表是cgavd的流队列WRED队列策略组*/ + for (index = 0 ; index < 16; index++) + { + rc = dpp_tm_qmu_crs_eir_th_set(dev_id, index, 0); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_crs_eir_th_set"); + } + + /* CRS限速 */ + + /* 普通老化使能和配置 */ + rc = dpp_tm_qmu_pkt_aging_set(dev_id, 0, 0x1ff, 0xff, 0, DPP_ETM_Q_NUM - 1, 1, 0xa); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_pkt_aging_set"); + + /* CRDT SHAP配置 */ + rc = dpp_tm_crdt_ram_init(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_crdt_ram_init"); + rc = dpp_tm_shap_ram_init(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_shap_ram_init"); + /* CRDT 授权使能打开 */ + rc = dpp_tm_crdt_credit_en_set(dev_id, 1); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_crdt_credit_en_set"); + ZXIC_COMM_PRINT("dev_id:%d DPP_TM crdt credit enable set success!!!\n", dev_id); + + /* CRDT开启E桶CRS过滤使能(不能打开,会导致延时大) */ + /*for (index = 0; index < flow_id_index; index++) + { + rc = dpp_tm_ind_write32(dev_id, MODULE_TM_CRDT, 0x600000 + index, 0); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_move_th_set"); + }*/ + + /*打开flow db_token,配置成c+e*/ + rc = dpp_tm_shape_flow_db_en_set(dev_id, 1, 0); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_shape_flow_db_en_set"); + + /*开启cgavd平均队列深度归零使能*/ + rc = dpp_tm_cgavd_avg_qlen_return_zero_en_set(dev_id, 1); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_avg_qlen_return_zero_en_set"); + + rc = dpp_tm_qmu_qlist_cfgmt_ram_init_done_print(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_qlist_cfgmt_ram_init_done_print"); + + /*开启tm时钟门控使能*/ + // rc = dpp_tm_cfgmt_clkgate_en_set(dev_id, 1); + // ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_clkgate_en_set"); + + // /*开启tm软复位使能*/ + // rc = dpp_tm_cfgmt_softrst_en_set(dev_id, 1); + // ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_softrst_en_set"); + + /* 子系统就绪判断 */ + rc = dpp_tm_cfgmt_subsystem_rdy_check(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_subsystem_rdy_check"); + + + ZXIC_COMM_PRINT("=====>dev_id:%d TM ASIC INIT END! <======\n", dev_id); + + return DPP_OK; +} + +/***********************************************************/ +/** 配置TM模式下初始化代码 +* @param dev_id +* @param tm_type 0-ETM,1-FTM +* @param p_tm_init_info 配置TM模式下初始化信息包括以下 +* blk_size 配置qmu block大小：512B[default]/1024B +* case_num QMU初始化场景编号：0/1/2/3... +* imem_omem; 0-片内外混合; 1-纯片内;2-纯片外 +* mode 0-TM; 1-SA +* +* @return +* @remark 无 +* @see +* @author szq @date 2015/03/26 +************************************************************/ +DPP_STATUS dpp_tm_asic_init_diag(ZXIC_UINT32 dev_id, ZXIC_UINT32 blk_size, ZXIC_UINT32 case_num, ZXIC_UINT32 imem_omem, ZXIC_UINT32 mode) +{ + DPP_STATUS rc = DPP_OK; + DPP_TM_ASIC_INIT_INFO_T tm_asic_init_info = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1); + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, blk_size, 256, 1024); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, case_num, 0, 0x99F); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, imem_omem, 0, 2); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, mode, 0, 1); + + tm_asic_init_info.blk_size = blk_size; + tm_asic_init_info.case_num = case_num; + tm_asic_init_info.imem_omem = imem_omem; + tm_asic_init_info.mode = mode; + rc = dpp_tm_asic_init(dev_id, &tm_asic_init_info); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_asic_init"); + + return DPP_OK; +} + +#endif +/**************************************************************************** +* 函数名称: dpp_tm_avg_que_len_get +* 功能描述: 各级平均队列深度获取 +* 输入参数: dev_id: 设备索引编号 +* @param tm_type 0-ETM,1-FTM +* cgavd_level: 拥塞避免支持层次号，0:队列级，1:端口级，2:系统级 +* que_id: 本级别层次内的队列编号。 +* 输出参数: p_avg_len: 平均队列深度，单位为BLOCK。 +* 返 回 值: DPP_OK-成功，DPP_ERR-失败 +* 其它说明: +* author cy @date 2015/06/29 +*****************************************************************************/ +DPP_STATUS dpp_tm_avg_que_len_get(ZXIC_UINT32 dev_id, + DPP_TM_CGAVD_LEVEL_E cgavd_level, + ZXIC_UINT32 que_id, + ZXIC_UINT32 *p_avg_len) +{ + /* 返回值变量定义 */ + DPP_STATUS rc = DPP_OK; + + /* 结构体变量定义 */ + DPP_ETM_CGAVD_PP_AVG_Q_LEN_T cgavd_pp_avg_q_len = {0}; + DPP_ETM_CGAVD_SYS_AVG_Q_LEN_T cgavd_sys_avg_q_len = {0}; + DPP_ETM_CGAVD_FLOW_AVG_Q_LEN_T cgavd_flow_avg_q_len = {0}; + + + /* 入参检查 */ + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, cgavd_level, QUEUE_LEVEL, SYS_LEVEL); + + if (QUEUE_LEVEL == cgavd_level) + { + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, que_id, 0, DPP_ETM_Q_NUM - 1); + } + else if (PP_LEVEL == cgavd_level) + { + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, que_id, 0, DPP_TM_PP_NUM - 1); + } + else + { + + } + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_avg_len); + + switch (cgavd_level) + { + case QUEUE_LEVEL: + { + rc = dpp_reg_read(dev_id, ETM_CGAVD_FLOW_AVG_Q_LENr, 0, que_id, &cgavd_flow_avg_q_len); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + *p_avg_len = cgavd_flow_avg_q_len.flow_avg_q_len; + break; + } + + case PP_LEVEL: + { + rc = dpp_reg_read(dev_id, ETM_CGAVD_PP_AVG_Q_LENr, 0, que_id, &cgavd_pp_avg_q_len); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + *p_avg_len = cgavd_pp_avg_q_len.pp_avg_q_len; + break; + } + + case SYS_LEVEL: + { + rc = dpp_reg_read(dev_id, ETM_CGAVD_SYS_AVG_Q_LENr, 0, 0, &cgavd_sys_avg_q_len); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read"); + *p_avg_len = cgavd_sys_avg_q_len.sys_avg_q_len; + break; + } + + default: + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "[dev_id %d] cgavd_level is out of dev_id!!!\n", dev_id); + return DPP_ERR; + } + } + + return DPP_OK; +} + +#endif +/***********************************************************/ +/** 清除整形表格里面的值 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author yjd @date 2015/07/16 +************************************************************/ +DPP_STATUS dpp_tm_clr_shape_para(DPP_DEV_T *dev) +{ + /*DPP_STATUS rc = DPP_OK;*/ + +/* rc = dpp_tm_global_var_mutex_init(); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_global_var_mutex_init"); + + rc = zxic_comm_mutex_lock(&g_dpp_tm_global_var_rw_mutex); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "zxic_comm_mutex_lock");*/ + + // ZXIC_COMM_CHECK_POINT(dev); + // ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 2); + + memset(g_dpp_etm_shape_para_table[0], 0, 256 * 22 * 128 * sizeof(DPP_TM_SHAPE_PARA_TABLE)); + + +/* rc = zxic_comm_mutex_unlock(&g_dpp_tm_global_var_rw_mutex); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "zxic_comm_mutex_unlock");*/ + return DPP_OK; + +} + +#if 0 +/***********************************************************/ +/** 配置CFGMT中断屏蔽 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param shap_int_mask_flag shap模块中断屏蔽位 0:不屏蔽 1:屏蔽 +* @param crdt_int_mask_flag crdt模块中断屏蔽位 +* @param mmu_int_mask_flag mmu模块中断屏蔽位 +* @param qmu_int_mask_flag qmu模块中断屏蔽位 +* @param cgavd_int_mask_flag cgavd模块中断屏蔽位 +* @param olif_int_mask_flag olif模块中断屏蔽位 +* @param cfgmt_int_buf_mask_flag cfgmt模块中断屏蔽位 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author yjd @date 2015/07/08 +************************************************************/ +DPP_STATUS dpp_tm_cfgmt_int_mask_set_diag(ZXIC_UINT32 dev_id, + ZXIC_UINT32 shap_int_mask_flag, + ZXIC_UINT32 crdt_int_mask_flag, + ZXIC_UINT32 mmu_int_mask_flag, + ZXIC_UINT32 qmu_int_mask_flag, + ZXIC_UINT32 cgavd_int_mask_flag, + ZXIC_UINT32 olif_int_mask_flag, + ZXIC_UINT32 cfgmt_int_buf_mask_flag) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CFGMT_REG_INT_MASK_REG_T int_mask = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, shap_int_mask_flag, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, crdt_int_mask_flag, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, mmu_int_mask_flag, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, qmu_int_mask_flag, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, cgavd_int_mask_flag, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, olif_int_mask_flag, 0, 1); + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, cfgmt_int_buf_mask_flag, 0, 1); + + int_mask.shap_int_mask = shap_int_mask_flag; + int_mask.crdt_int_mask = crdt_int_mask_flag; + int_mask.tmmu_int_mask = mmu_int_mask_flag; + int_mask.qmu_int_mask = qmu_int_mask_flag; + int_mask.cgavd_int_mask = cgavd_int_mask_flag; + int_mask.olif_int_mask = olif_int_mask_flag; + int_mask.cfgmt_int_buf_mask = cfgmt_int_buf_mask_flag; + + rc = dpp_reg_write(dev_id, + ETM_CFGMT_REG_INT_MASK_REGr, + 0, + 0, + &int_mask); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + return DPP_OK; +} + +/***********************************************************/ +/** 读取CFGMT中断状态 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_para 中断状态 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author yjd @date 2015/07/08 +************************************************************/ +DPP_STATUS dpp_tm_cfgmt_int_state_get_diag(ZXIC_UINT32 dev_id) +{ + DPP_STATUS rc = DPP_OK; + + rc = dpp_reg_fields_print_with_def(dev_id, ETM_CFGMT_REG_INT_STATE_REGr, 0, 0); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_fields_print_with_def"); + + return DPP_OK; +} + +/***********************************************************/ +/** 读取olif中断状态 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author yjd @date 2015/07/08 +************************************************************/ +DPP_STATUS dpp_tm_olif_int_state_get(ZXIC_UINT32 dev_id) +{ + DPP_STATUS rc = DPP_OK; + + rc = dpp_reg_fields_print_with_def(dev_id, ETM_OLIF_ITMHRAM_PARITY_ERR_2_INTr, 0, 0); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_fields_print_with_def"); + + + return DPP_OK; +} + + +/***********************************************************/ +/** 配置OLIF中断屏蔽 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param crcram_parity_err_mask 0:不屏蔽 1:屏蔽 +* @param itmhram_parity_err_mask +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author yjd @date 2015/07/08 +************************************************************/ +DPP_STATUS dpp_tm_olif_int_mask_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 olif_int_mask_flag) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_OLIF_OLIF_INT_MASK_T int_mask = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, olif_int_mask_flag, 0, 1); + + int_mask.crcram_parity_err_mask = olif_int_mask_flag; + int_mask.emem_fifo_ecc_mask = olif_int_mask_flag; + int_mask.emem_fifo_ovf_mask = olif_int_mask_flag; + int_mask.emem_fifo_udf_mask = olif_int_mask_flag; + int_mask.imem_fifo_ecc_mask = olif_int_mask_flag; + int_mask.imem_fifo_ovf_mask = olif_int_mask_flag; + int_mask.imem_fifo_udf_mask = olif_int_mask_flag; + int_mask.itmh_ecc_double_err_mask = olif_int_mask_flag; + int_mask.itmh_ecc_single_err_mask = olif_int_mask_flag; + int_mask.order_fifo_ovf_mask = olif_int_mask_flag; + int_mask.order_fifo_parity_err_mask = olif_int_mask_flag; + int_mask.order_fifo_udf_mask = olif_int_mask_flag; + int_mask.para_fifo_ecc_mask = olif_int_mask_flag; + int_mask.para_fifo_ovf_mask = olif_int_mask_flag; + int_mask.para_fifo_udf_mask = olif_int_mask_flag; + + rc = dpp_reg_write(dev_id, + ETM_OLIF_OLIF_INT_MASKr, + 0, + 0, + &int_mask); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + return DPP_OK; +} + + +/***********************************************************/ +/** 配置cgavd中断屏蔽 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param cgavd_int_mask_flag 0:不屏蔽 1:屏蔽 +* @param 写1 屏蔽cgavd中断寄存器和cgavd_ram_err寄存器所有位 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author yjd @date 2015/07/08 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_int_mask_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 cgavd_int_mask_flag) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CGAVD_CGAVD_INT_MASK_T cgavd_int_mask = {0}; + DPP_ETM_CGAVD_CGAVD_RAM_ERR_INT_MASK_T cgavd_ram_err_int_mask = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, cgavd_int_mask_flag, 0, 1); + + + cgavd_int_mask.cgavd_int_mask = cgavd_int_mask_flag; + cgavd_ram_err_int_mask.flow_qlen_inta_mask = cgavd_int_mask_flag; + cgavd_ram_err_int_mask.flow_qlen_intb_mask = cgavd_int_mask_flag; + cgavd_ram_err_int_mask.flow_qnum_inta_mask = cgavd_int_mask_flag; + cgavd_ram_err_int_mask.flow_qnum_intb_mask = cgavd_int_mask_flag; + cgavd_ram_err_int_mask.flow_tdth_inta_mask = cgavd_int_mask_flag; + cgavd_ram_err_int_mask.flow_tdth_intb_mask = cgavd_int_mask_flag; + + cgavd_ram_err_int_mask.pds_deal_fifo_ov_int_mask = cgavd_int_mask_flag; + cgavd_ram_err_int_mask.pds_deal_fifo_uv_int_mask = cgavd_int_mask_flag; + cgavd_ram_err_int_mask.pp_qlen_inta_mask = cgavd_int_mask_flag; + cgavd_ram_err_int_mask.pp_qlen_intb_mask = cgavd_int_mask_flag; + cgavd_ram_err_int_mask.pp_tdth_int_mask = cgavd_int_mask_flag; + cgavd_ram_err_int_mask.qmu_cgavd_fifo_ov_int_mask = cgavd_int_mask_flag; + cgavd_ram_err_int_mask.qmu_cgavd_fifo_uv_int_mask = cgavd_int_mask_flag; + + rc = dpp_reg_write(dev_id, + ETM_CGAVD_CGAVD_INT_MASKr, + 0, + 0, + &cgavd_int_mask); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + rc = dpp_reg_write(dev_id, + ETM_CGAVD_CGAVD_RAM_ERR_INT_MASKr, + 0, + 0, + &cgavd_ram_err_int_mask); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + return DPP_OK; +} + +/***********************************************************/ +/** 读取cgavd中断状态 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_para 中断状态 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author yjd @date 2015/07/08 +************************************************************/ +DPP_STATUS dpp_tm_cgavd_int_state_get(ZXIC_UINT32 dev_id) +{ + DPP_STATUS rc = DPP_OK; + + + rc = dpp_reg_fields_print_with_def(dev_id, ETM_CGAVD_CGAVD_INTr, 0, 0); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_fields_print_with_def"); + + rc = dpp_reg_fields_print_with_def(dev_id, ETM_CGAVD_CGAVD_RAM_ERRr, 0, 0); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_fields_print_with_def"); + + return DPP_OK; +} + +/***********************************************************/ +/** 读取tmmu中断状态 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param p_para 中断状态 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author yjd @date 2015/07/08 +************************************************************/ +DPP_STATUS dpp_tm_tmmu_int_state_get(ZXIC_UINT32 dev_id) +{ + DPP_STATUS rc = DPP_OK; + + rc = dpp_reg_fields_print_with_def(dev_id, ETM_TMMU_TMMU_STATES_1r, 0, 0); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_fields_print_with_def"); + + + return DPP_OK; +} + + +/***********************************************************/ +/** 配置crdt中断屏蔽 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param crdt_int_mask_flag 0:不屏蔽 1:屏蔽 +* @param 写1 屏蔽ETM_CGAVD_RD_CPU_OR_RAMr +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/4/10 +************************************************************/ +DPP_STATUS dpp_tm_crdt_int_mask_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 crdt_int_mask_flag) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CRDT_CRDT_INT_MASK_T crdt_int_mask = {0}; + + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, crdt_int_mask_flag, 0, 1); + + + crdt_int_mask.crdt_int_mask = crdt_int_mask_flag; + rc = dpp_reg_write(dev_id, + ETM_CRDT_CRDT_INT_MASKr, + 0, + 0, + &crdt_int_mask); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + + return DPP_OK; +} + +/***********************************************************/ +/** 读取crdt中断状态 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/4/10 +************************************************************/ +DPP_STATUS dpp_tm_crdt_int_state_get(ZXIC_UINT32 dev_id) +{ + DPP_STATUS rc = DPP_OK; + + + rc = dpp_reg_fields_print_with_def(dev_id, ETM_CRDT_CRDT_INT_BUSr, 0, 0); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_fields_print_with_def"); + + return DPP_OK; +} + +/***********************************************************/ +/** 配置qmu中断屏蔽 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param qmu_int_mask_flag 0:不屏蔽 1:屏蔽 +* @param 写1 屏蔽qmu_int_mask5的所有位 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author yjd @date 2015/07/09 +************************************************************/ +DPP_STATUS dpp_tm_qmu_int_mask_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 qmu_int_mask_flag) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 qmu_qsch_crbal_init_mask_reg_index = 0; + ZXIC_UINT32 qmu_int_mask1_reg_index = 0; + ZXIC_UINT32 qmu_int_mask2_reg_index = 0; + ZXIC_UINT32 qmu_int_mask3_reg_index = 0; + ZXIC_UINT32 qmu_int_mask4_reg_index = 0; + ZXIC_UINT32 qmu_int_mask5_reg_index = 0; + + DPP_ETM_QMU_QCFG_QSCH_CRBAL_INIT_MASK_T qmu_qsch_crbal_init_mask = {0}; + DPP_ETM_QMU_QMU_INT_MASK1_T qmu_int_mask1 = {0}; + DPP_ETM_QMU_QMU_INT_MASK2_T qmu_int_mask2 = {0}; + DPP_ETM_QMU_QMU_INT_MASK3_T qmu_int_mask3 = {0}; + DPP_ETM_QMU_QMU_INT_MASK4_T qmu_int_mask4 = {0}; + DPP_ETM_QMU_QMU_INT_MASK5_T qmu_int_mask5 = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, qmu_int_mask_flag, 0, 1); + + qmu_qsch_crbal_init_mask_reg_index = ETM_QMU_QCFG_QSCH_CRBAL_INIT_MASKr; + qmu_int_mask1_reg_index = ETM_QMU_QMU_INT_MASK1r; + qmu_int_mask2_reg_index = ETM_QMU_QMU_INT_MASK2r; + qmu_int_mask3_reg_index = ETM_QMU_QMU_INT_MASK3r; + qmu_int_mask4_reg_index = ETM_QMU_QMU_INT_MASK4r; + qmu_int_mask5_reg_index = ETM_QMU_QMU_INT_MASK5r; + + qmu_qsch_crbal_init_mask.qcfg_qsch_crbal_init_mask = qmu_int_mask_flag; + + qmu_int_mask1.qmu_int_mask1 = qmu_int_mask_flag; + qmu_int_mask2.qmu_int_mask2 = qmu_int_mask_flag; + qmu_int_mask3.qmu_int_mask3 = qmu_int_mask_flag; + qmu_int_mask4.qmu_int_mask4 = qmu_int_mask_flag; + qmu_int_mask5.qmu_int_mask5 = qmu_int_mask_flag; + + rc = dpp_reg_write(dev_id, + qmu_qsch_crbal_init_mask_reg_index, + 0, + 0, + &qmu_qsch_crbal_init_mask); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + rc = dpp_reg_write(dev_id, + qmu_int_mask1_reg_index, + 0, + 0, + &qmu_int_mask1); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + rc = dpp_reg_write(dev_id, + qmu_int_mask2_reg_index, + 0, + 0, + &qmu_int_mask2); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + rc = dpp_reg_write(dev_id, + qmu_int_mask3_reg_index, + 0, + 0, + &qmu_int_mask3); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + rc = dpp_reg_write(dev_id, + qmu_int_mask4_reg_index, + 0, + 0, + &qmu_int_mask4); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + + rc = dpp_reg_write(dev_id, + qmu_int_mask5_reg_index, + 0, + 0, + &qmu_int_mask5); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + return DPP_OK; +} + +/***********************************************************/ +/** 读取qmu中断状态 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author yjd @date 2015/07/09 +************************************************************/ +DPP_STATUS dpp_tm_qmu_int_state_get(ZXIC_UINT32 dev_id) +{ + DPP_STATUS rc = DPP_OK; + + rc = dpp_reg_fields_print_with_def(dev_id, ETM_QMU_QLIST_CFGMT_FIFO_STATEr, 0, 0); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_fields_print_with_def"); + rc = dpp_reg_fields_print_with_def(dev_id, ETM_QMU_CMD_SCH_CFGMT_FIFO_STATEr, 0, 0); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_fields_print_with_def"); + + return DPP_OK; +} + +/***********************************************************/ +/** 配置shape中断屏蔽 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param shape_int_mask_flag 0:不屏蔽 1:屏蔽 +* @param 写1 屏蔽ETM_CGAVD_RD_CPU_OR_RAMr +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/4/10 +************************************************************/ +DPP_STATUS dpp_tm_shape_int_mask_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 shape_int_mask_flag) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CRDT_SHAP_INT_MASK_REG_T shap_int_mask = {0}; + + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, shape_int_mask_flag, 0, 1); + + shap_int_mask.pp_c_token_min_int_mask = shape_int_mask_flag; + rc = dpp_reg_write(dev_id, + ETM_CRDT_SHAP_INT_MASK_REGr, + 0, + 0, + &shap_int_mask); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write"); + + + return DPP_OK; +} + + +/***********************************************************/ +/** 读取shape中断状态 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author whuashan @date 2019/4/10 +************************************************************/ +DPP_STATUS dpp_tm_shape_int_state_get(ZXIC_UINT32 dev_id) +{ + DPP_STATUS rc = DPP_OK; + DPP_ETM_CRDT_SHAP_INT_REG_T shap_int_reg_t = {0}; + + rc = dpp_reg_fields_print_with_def(dev_id, ETM_CRDT_SHAP_INT_REGr, 0, 0); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_fields_print_with_def"); + + + ZXIC_COMM_PRINT("pp_c_token_min_int : %d\n", shap_int_reg_t.pp_c_token_min_int); + + return DPP_OK; +} + + +/***********************************************************/ +/** 配置dpp tm所有模块中断屏蔽 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param int_mask_flag 0:不屏蔽 1:屏蔽 +* @param +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author yjd @date 2015/07/09 +************************************************************/ +DPP_STATUS dpp_tm_int_mask_set(ZXIC_UINT32 dev_id, + ZXIC_UINT32 int_mask_flag) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, int_mask_flag, 0, 1); + + + rc = dpp_tm_cfgmt_int_mask_set_diag(dev_id, + int_mask_flag, + int_mask_flag, + int_mask_flag, + int_mask_flag, + int_mask_flag, + int_mask_flag, + int_mask_flag); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_int_mask_set_diag"); + + rc = dpp_tm_olif_int_mask_set(dev_id, int_mask_flag); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_olif_int_mask_set"); + + rc = dpp_tm_cgavd_int_mask_set(dev_id, int_mask_flag); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_int_mask_set"); + + rc = dpp_tm_shape_int_mask_set(dev_id, int_mask_flag); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_shape_int_mask_set"); + + rc = dpp_tm_crdt_int_mask_set(dev_id, int_mask_flag); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_crdt_int_mask_set"); + + rc = dpp_tm_qmu_int_mask_set(dev_id, int_mask_flag); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_int_mask_set"); + + + return DPP_OK; +} + +/***********************************************************/ +/** 打印dpp tm所有模块中断状态 +* @param tm_type 0-ETM,1-FTM +* @param dev_id 设备编号 +* @param +* @param +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author yjd @date 2015/07/09 +************************************************************/ +DPP_STATUS diag_dpp_tm_int(ZXIC_UINT32 dev_id) +{ + DPP_STATUS rc = DPP_OK; + + ZXIC_COMM_PRINT("**************************************\n"); + ZXIC_COMM_PRINT("dpp tm cfgmt int state\n"); + ZXIC_COMM_PRINT("**************************************\n"); + rc = dpp_tm_cfgmt_int_state_get_diag(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_int_state_get_diag"); + + ZXIC_COMM_PRINT("**************************************\n"); + ZXIC_COMM_PRINT("dpp tm olif int state\n"); + ZXIC_COMM_PRINT("**************************************\n"); + rc = dpp_tm_olif_int_state_get(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_olif_int_state_get"); + + ZXIC_COMM_PRINT("**************************************\n"); + ZXIC_COMM_PRINT("dpp tm cgavd int state\n"); + ZXIC_COMM_PRINT("**************************************\n"); + rc = dpp_tm_cgavd_int_state_get(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_int_state_get"); + + ZXIC_COMM_PRINT("**************************************\n"); + ZXIC_COMM_PRINT("dpp tm tmmu int state\n"); + ZXIC_COMM_PRINT("**************************************\n"); + rc = dpp_tm_tmmu_int_state_get(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_tmmu_int_state_get"); + + ZXIC_COMM_PRINT("**************************************\n"); + ZXIC_COMM_PRINT("dpp tm shap int state\n"); + ZXIC_COMM_PRINT("**************************************\n"); + rc = dpp_tm_shape_int_state_get(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_shape_int_state_get"); + + ZXIC_COMM_PRINT("**************************************\n"); + ZXIC_COMM_PRINT("dpp tm crdt int state\n"); + ZXIC_COMM_PRINT("**************************************\n"); + rc = dpp_tm_crdt_int_state_get(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_crdt_int_state_get"); + + ZXIC_COMM_PRINT("**************************************\n"); + ZXIC_COMM_PRINT("dpp tm qmu int state\n"); + ZXIC_COMM_PRINT("**************************************\n"); + rc = dpp_tm_qmu_int_state_get(dev_id); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_int_state_get"); + + ZXIC_COMM_PRINT("**************************************\n"); + ZXIC_COMM_PRINT("dpp tm qmu int case_no\n"); + ZXIC_COMM_PRINT("**************************************\n"); + ZXIC_COMM_PRINT("g_qmu_init_case_no = 0x%x\n", g_qmu_init_case_no); + + return DPP_OK; +} + + +/***********************************************************/ +/** 获取tm.c中qmu_init_set中配置的case_num +* @param tm_type 0-ETM,1-FTM +* @param dev_id 设备编号 +* @param +* @param +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xuhb @date 2020/04/15 +************************************************************/ +DPP_STATUS dpp_tm_case_no_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *case_no) +{ + ZXIC_COMM_CHECK_DEV_POINT(dev_id, case_no); + + *case_no = g_qmu_init_case_no; + + return DPP_OK; +} + +/***********************************************************/ +/** 配置tm授权价值总接口,包含qmu授权价值、shap授权价值、FTM对应授权价值版本设置 +* @param dev_id 设备编号 +* @param tm_type 0-ETM,1-FTM +* @param credit_value 授权价值，默认值是0x5feByte +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author xuhb @date 2020/08/13 +************************************************************/ +DPP_STATUS dpp_tm_credit_value_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 credit_value) +{ + DPP_STATUS rc = DPP_OK; + + rc = dpp_tm_qmu_credit_value_set(dev_id, credit_value); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_credit_value_set"); + + rc = dpp_tm_shap_crd_grain_set(dev_id, credit_value); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_shap_crd_grain_set"); + + return DPP_OK; +} + +#endif +#endif + +#if ZXIC_REAL("TM_CPU_SOFT_RESET") +#if 0 +/***********************************************************/ +/** 设置TM的全局变量，shape_para只保存profile被使用的数量，整形相关参数从寄存器中重新读取 +* @param dev_id +* @param size data_buff的长度 +* @param p_data_buff 需要恢复的内容 +* +* @return +* @remark 无 +* @see +* @author XXX @date 2017/03/09 +************************************************************/ +DPP_STATUS dpp_tm_glb_mgr_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 size, ZXIC_UINT8 *p_data_buff) +{ + DPP_STATUS rc = DPP_OK; + ZXIC_UINT32 shape_table_profile_num = 128; + static ZXIC_UINT32 etm_shape_num[22][128] = {{0}}; + ZXIC_UINT32 total_para_id = 0; + ZXIC_UINT32 i = 0; + ZXIC_UINT32 j = 0; + DPP_TM_SHAPE_PARA_TABLE shap_para_tbl_t = {0}; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 2); + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_data_buff); + + rc = zxic_comm_mutex_lock(&g_dpp_tm_global_var_rw_mutex); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "zxic_comm_mutex_lock"); + + if (size != (22 * 128 * sizeof(ZXIC_UINT32))) + { + ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "date is not complete.size[%d] err!!\n", size); + rc = zxic_comm_mutex_unlock(&g_dpp_tm_global_var_rw_mutex); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "zxic_comm_mutex_unlock"); + + return DPP_ERR; + } + + ZXIC_COMM_MEMCPY(etm_shape_num, p_data_buff, 22 * 128 * sizeof(ZXIC_UINT32)); + + + /* ETM: set flow and se profile to cpu mem */ + for (i = 0; i < 22; i++) + { + for (j = 0; j < shape_table_profile_num; j++) + { + total_para_id = i * shape_table_profile_num + j; + + rc = dpp_tm_shape_para_get(dev_id, total_para_id, &shap_para_tbl_t); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(dev_id, rc, "dpp_tm_shape_para_get", &g_dpp_tm_global_var_rw_mutex); + + g_dpp_etm_shape_para_table[dev_id][i][j].shape_num = etm_shape_num[i][j]; + g_dpp_etm_shape_para_table[dev_id][i][j].shape_cbs = shap_para_tbl_t.shape_cbs; + g_dpp_etm_shape_para_table[dev_id][i][j].shape_cir = shap_para_tbl_t.shape_cir; + + } + } + + + rc = zxic_comm_mutex_unlock(&g_dpp_tm_global_var_rw_mutex); + ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "zxic_comm_mutex_unlock"); + + return DPP_OK; + +} + +/***********************************************************/ +/** 获取TM的全局变量，shape_para只保存profile被使用的数量，整形相关参数从寄存器中重新读取 +* @param dev_id +* @param p_flag 上层释放data_buff的标志，1:需要上层free,0:不需要上层free +* @param p_size data_buff的长度 +* @param pp_data_buff 二级指针(指向函数内部malloc空间的地址) +* +* @return +* @remark 无 +* @see +* @author XXX @date 2017/03/09 +************************************************************/ +DPP_STATUS dpp_tm_glb_mgr_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_flag, ZXIC_UINT32 *p_size, ZXIC_UINT8 **pp_data_buff) +{ + ZXIC_UINT32 size = 0; + static ZXIC_UINT32 etm_shape_num[22][128] = {{0}}; + ZXIC_UINT32 i = 0; + ZXIC_UINT32 j = 0; + + ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 2); + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_flag); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_size); + + size = 22 * 128 * sizeof(ZXIC_UINT32); + *pp_data_buff = ZXIC_COMM_MALLOC(size); + ZXIC_COMM_CHECK_DEV_POINT(dev_id, *pp_data_buff); + + for (i = 0; i < 22; i++) + { + for (j = 0; j < 128; j++) + { + etm_shape_num[i][j] = g_dpp_etm_shape_para_table[dev_id][i][j].shape_num; + } + + } + + ZXIC_COMM_MEMCPY(*pp_data_buff, etm_shape_num, 22 * 128 * sizeof(ZXIC_UINT32)); + + + *p_flag = 1; + *p_size = size; + + return DPP_OK; +} + +/***********************************************************/ +/** 获取TM的全局变量大小，shape_para只保存profile被使用的数量，整形相关参数从寄存器中重新读取 +* @param dev_id +* @param p_size data_buff的长度 +* +* @return +* @remark 无 +* @see +* @author XXX @date 2017/03/09 +************************************************************/ +DPP_STATUS dpp_tm_glb_size_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_size) +{ + + ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_size); + + *p_size = 22 * 128 * sizeof(ZXIC_UINT32); + + return DPP_OK; +} + +#endif +#endif + + + + + + + + + + + + + diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/reg/Kbuild.include b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/reg/Kbuild.include new file mode 100644 index 0000000..6fdfdb7 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/reg/Kbuild.include @@ -0,0 +1,2 @@ +cur_dir := en_np/sdk/source/dev/reg/ +src_files += $(addprefix $(cur_dir),$(notdir $(wildcard $(dinghai_root)/$(cur_dir)*.c))) \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/reg/dpp_module.c b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/reg/dpp_module.c new file mode 100755 index 0000000..9268caf --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/reg/dpp_module.c @@ -0,0 +1,294 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_module.c +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : 石金锋 +* 完成日期 : 2014/02/10 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ +#include "zxic_common.h" +#include "dpp_type_api.h" +#include "dpp_module.h" +#include "dpp_dev.h" +#include "dpp_reg_struct.h" +#include "dpp_reg_api.h" + +/***********************************************************/ +/** dpp通用读寄存器函数 +* @param dev_id 设备id +* @param addr 地址读地址 +* @param p_data 返回数据 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author 石金锋 @date 2014/01/28 +************************************************************/ +DPP_STATUS dpp_read(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 *p_data) +{ + return dpp_dev_read_channel(dev, + addr, + 1, + p_data); +} + +/***********************************************************/ +/** dpp通用写寄存器函数 +* @param dev_id 设备id +* @param addr 地址写地址 +* @param p_data 写入数据 +* +* @return 0表示成功 非0表示操作失败 +* @remark 无 +* @see +* @author 石金锋 @date 2014/01/28 +************************************************************/ +DPP_STATUS dpp_write(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 *p_data) +{ + return dpp_dev_write_channel(dev, + addr, + 1, + p_data); +} + +#if ZXIC_REAL("SE") + +/***********************************************************/ +/** SE读接口 +* @param dev_id 设备号 +* @param addr 地址 +* @param p_data 数据 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/11/15 +************************************************************/ +DPP_STATUS dpp_se_read(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 *p_data) +{ + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data); + + return dpp_read(dev, addr, p_data); +} + +/***********************************************************/ +/** SE写接口 +* @param dev_id 设备号 +* @param addr 地址 +* @param p_data 数据 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/11/15 +************************************************************/ +DPP_STATUS dpp_se_write(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 *p_data) +{ + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data); + + return dpp_write(dev, addr, p_data); +} +#endif + +#if ZXIC_REAL("SE ALG") +/***********************************************************/ +/** se alg模块读寄存器函数 +* @param dev_id 设备id +* @param addr 地址 读地址 +* @param p_data 返回数据 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author 王春雷 @date 2014/04/03 +************************************************************/ +DPP_STATUS dpp_se_alg_read(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 *p_data) +{ + DPP_STATUS rtn = DPP_OK; + + ZXIC_UINT32 cpu_rd_rdy_addr = SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0048; + ZXIC_UINT32 ind_data0_addr = SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x004c; + ZXIC_UINT32 ind_cmd_addr = SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0004; + ZXIC_UINT32 cpu_rd_rdy_reg = 0; + ZXIC_UINT32 ind_data0_reg = 0; + ZXIC_UINT32 ind_cmd_reg = 0; + ZXIC_UINT32 cmd_data = 0; + ZXIC_UINT32 i = 0; + ZXIC_UINT32 cpu_rdy = 0; + ZXIC_UINT32 read_cnt = 0; + ZXIC_UINT32 recheck_flag = 20; + + ZXIC_MUTEX_T *p_alg_mutex = NULL; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data); + + ind_data0_reg = dpp_reg_addr_convert(DEV_ID(dev), SE4K, DPP_REG_FLAG_DIRECT,ind_data0_addr); + ind_cmd_reg = dpp_reg_addr_convert(DEV_ID(dev), SE4K, DPP_REG_FLAG_DIRECT,ind_cmd_addr); + cpu_rd_rdy_reg = dpp_reg_addr_convert(DEV_ID(dev), SE4K, DPP_REG_FLAG_DIRECT,cpu_rd_rdy_addr); + + rtn = dpp_dev_opr_mutex_get(DEV_ID(dev), DPP_DEV_MUTEX_T_REG, &p_alg_mutex); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_dev_opr_mutex_get"); + + rtn = zxic_comm_mutex_lock(p_alg_mutex); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "zxic_comm_mutex_lock"); + + /* dpp_module_get_se_alg_baseaddr(&base_addr); */ + + cmd_data = ((ZXIC_UINT32)0x1 << 31) | ((ZXIC_UINT32)0xF << 17) | addr; + rtn = dpp_dev_write_channel(dev, ind_cmd_reg, 1, &cmd_data); + ZXIC_COMM_CHECK_DEV_RC_UNLOCK(DEV_ID(dev), rtn, "dpp_dev_write_channel", p_alg_mutex); + + while (!(cpu_rdy & 0x1)) + { + rtn = dpp_dev_read_channel(dev, cpu_rd_rdy_reg, 1, &cpu_rdy); + ZXIC_COMM_CHECK_DEV_RC_UNLOCK(DEV_ID(dev), rtn, "dpp_dev_read_channel", p_alg_mutex); + + read_cnt++; + /* zxic_comm_sleep(10); */ + + if (read_cnt > DPP_RD_CNT_MAX * DPP_RD_CNT_MAX) + { + if (recheck_flag > 0) + { + recheck_flag--; + read_cnt = 0; + rtn = dpp_dev_write_channel(dev, ind_cmd_reg, 1, &cmd_data); + ZXIC_COMM_CHECK_DEV_RC_UNLOCK(DEV_ID(dev), rtn, "dpp_dev_write_channel", p_alg_mutex); + } + else + { + ZXIC_COMM_PRINT("Error!!! dpp_se_alg_read get cpu_rd_rdone failed!!!\n"); + zxic_comm_mutex_unlock(p_alg_mutex); + /* ZXIC_COMM_ASSERT(0); */ /* xjw mod for OLT to not assert because of causing reboot at 18.8.7 */ + return DPP_ERR; + } + } + + /* ZXIC_COMM_CHECK_DEV_INDEX(dev_id, read_cnt, 0, DPP_RD_CNT_MAX); */ + } + + for (i = 0; i < 16; i++) + { + rtn = dpp_dev_read_channel(dev, ind_data0_reg + 4 * i, 1, p_data + 15 - i); + ZXIC_COMM_CHECK_DEV_RC_UNLOCK(DEV_ID(dev), rtn, "dpp_dev_read_channel", p_alg_mutex); + } + + rtn = zxic_comm_mutex_unlock(p_alg_mutex); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "zxic_comm_mutex_unlock"); + + return DPP_OK; +} + +/***********************************************************/ +/** se alg模块写寄存器函数 +* @param dev_id 设备id +* @param addr 地址 读地址 +* @param p_data 返回数据 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author 王春雷 @date 2014/04/03 +************************************************************/ +DPP_STATUS dpp_se_alg_write(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 *p_data) +{ + DPP_STATUS rtn = DPP_OK; + + ZXIC_UINT32 ind_data0_addr = SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0008; + ZXIC_UINT32 cmd_data = 0; + ZXIC_UINT32 ind_cmd_addr = SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0004; + ZXIC_UINT32 ind_data0_reg = 0; + ZXIC_UINT32 ind_cmd_reg = 0; + ZXIC_UINT32 i = 0; + ZXIC_MUTEX_T *p_alg_mutex = NULL; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data); + + ind_data0_reg = dpp_reg_addr_convert(DEV_ID(dev), SE4K, DPP_REG_FLAG_DIRECT, ind_data0_addr); + ind_cmd_reg = dpp_reg_addr_convert(DEV_ID(dev), SE4K, DPP_REG_FLAG_DIRECT, ind_cmd_addr); + + /* dpp_module_get_se_alg_baseaddr(&base_addr); */ + rtn = dpp_dev_opr_mutex_get(DEV_ID(dev), DPP_DEV_MUTEX_T_REG, &p_alg_mutex); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_dev_opr_mutex_get"); + + rtn = zxic_comm_mutex_lock(p_alg_mutex); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "zxic_comm_mutex_lock"); + + /* write data */ + for (i = 0; i < 16; i++) + { + ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev), "dpp_se_alg_write: addr=0x%08x, data=0x%08x.\n", ind_data0_reg + 4 * i, *(p_data + 15 - i)); + rtn = dpp_dev_write_channel(dev, ind_data0_reg + 4 * i, 1, p_data + 15 - i); + ZXIC_COMM_CHECK_DEV_RC_UNLOCK(DEV_ID(dev), rtn, "dpp_dev_write_channel", p_alg_mutex); + } + + /* write cmd */ + /* cmd_data = ((ZXIC_UINT32)0xF << 17) | addr; */ + cmd_data = addr & 0x1fffff; /* mod by tf */ + ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev), "dpp_se_alg_write: addr=0x%08x, data=0x%08x.\n", ind_cmd_reg, cmd_data); + rtn = dpp_dev_write_channel(dev, ind_cmd_reg, 1, &cmd_data); + ZXIC_COMM_CHECK_DEV_RC_UNLOCK(DEV_ID(dev), rtn, "dpp_dev_write_channel", p_alg_mutex); + + rtn = zxic_comm_mutex_unlock(p_alg_mutex); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "zxic_comm_mutex_unlock"); + + return DPP_OK; +} + +#endif + +#if ZXIC_REAL("PPU") +/***********************************************************/ +/** PPU读接口 +* @param dev_id 设备号 +* @param addr 地址 +* @param p_data 数据 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/11/15 +************************************************************/ +DPP_STATUS dpp_ppu_read(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 *p_data) +{ + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data); + + return dpp_read(dev, addr, p_data); +} + +/***********************************************************/ +/** PPU写接口 +* @param dev_id 设备号 +* @param addr 地址 +* @param p_data 数据 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author ls @date 2016/11/15 +************************************************************/ +DPP_STATUS dpp_ppu_write(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 *p_data) +{ + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data); + + return dpp_write(dev, addr, p_data); +} +#endif \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/reg/dpp_pci.c b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/reg/dpp_pci.c new file mode 100755 index 0000000..b900e33 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/reg/dpp_pci.c @@ -0,0 +1,89 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_pci.c +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : 石金锋 +* 完成日期 : 2014/02/10 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: 代码规范性修改 +* 修改日期: 2014/02/10 +* 版 本 号: +* 修 改 人: 丁金凤 +* 修改内容: +***************************************************************/ +#include "zxic_common.h" +#include "dpp_type_api.h" +#include "dpp_pci.h" +#include "dpp_dev.h" + +/***********************************************************/ +/** +* @param abs_addr +* @param p_data +* +* @return +* @remark 无 +* @see +* @author 王春雷 @date 2014/02/14 +************************************************************/ +ZXIC_UINT32 dpp_pci_write32(DPP_DEV_T *dev, ZXIC_ADDR_T abs_addr, ZXIC_UINT32 *p_data) +{ + /* ZXIC_UINT32 rtn = 0; */ + ZXIC_UINT32 data = 0; + ZXIC_UINT64 addr = 0; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_POINT(p_data); + + data = *p_data; + + if (zxic_comm_is_big_endian()) + { + data = ZXIC_COMM_CONVERT32(data); + } + + addr = abs_addr + SYS_VF_NP_BASE_OFFSET; + *((ZXIC_VOL ZXIC_UINT32 *)addr) = data; + + return DPP_OK; +} + +/***********************************************************/ +/** +* @param abs_addr +* @param p_data +* +* @return +* @remark 无 +* @see +* @author 王春雷 @date 2014/02/14 +************************************************************/ +ZXIC_UINT32 dpp_pci_read32(DPP_DEV_T *dev, ZXIC_ADDR_T abs_addr, ZXIC_UINT32 *p_data) +{ + ZXIC_UINT32 data = 0; + ZXIC_UINT64 addr = 0; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_POINT(p_data); + + addr = abs_addr + SYS_VF_NP_BASE_OFFSET; + data = *((ZXIC_VOL ZXIC_UINT32 *)addr); + + if (zxic_comm_is_big_endian()) + { + data = ZXIC_COMM_CONVERT32(data); + } + *p_data = data; + + if (0xdadedade == *p_data) + { + ZXIC_COMM_TRACE_DEBUG("PCIE time out err happening at addr[0x%llx]\n", abs_addr); + } + + return DPP_OK; +} diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/reg/dpp_reg_api.c b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/reg/dpp_reg_api.c new file mode 100755 index 0000000..c732daa --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/reg/dpp_reg_api.c @@ -0,0 +1,544 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_reg.c +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : 王春雷 +* 完成日期 : 2014/02/12 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ + +#include "zxic_common.h" +#include "dpp_type_api.h" +#include "dpp_module.h" +#include "dpp_dev.h" +#include "dpp_reg_api.h" +#include "dpp_reg_info.h" +#include "dpp_agent_channel.h" +#include "dpp_pci.h" + +#define REG_DATA_MAX (512/32) + +static DPP_REG_OFFSET_ADDR g_module_offset_addr[] = +{ + {DTB4K, BAR_4K_DTB, SYS_DTB_BASE_ADDR + MODULE_DTB_ENQ_BASE_ADDR}, + {STAT4K, BAR_4K_ETCAM, SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR}, + {PPU4K, BAR_4K_CLS0, SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4000}, + {SE4K, BAR_4K_SE, SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR}, + {SMMU14K, BAR_4K_SMMU1, SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR } +}; + +/***********************************************************/ +/** 获取寄存器属性 +* @param reg_no 寄存器编号 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author 王春雷 @date 2014/04/17 +************************************************************/ +DPP_REG_T *dpp_reg_info_get(ZXIC_UINT32 reg_no) +{ + ZXIC_COMM_CHECK_INDEX_RETURN_NULL(reg_no, 0, REG_ENUM_MAX_VALUE - 1); + + return (&g_dpp_reg_info[reg_no]); +} + +/***********************************************************/ +/** 根据寄存器编号获得寄存器芯片内绝对地址 +* @param reg_no +* @param m_offset +* @param n_offset +* +* @return +* @remark 无 +* @see +* @author 王春雷 @date 2014/03/19 +************************************************************/ +ZXIC_UINT32 dpp_reg_get_reg_addr(ZXIC_UINT32 reg_no, ZXIC_UINT32 m_offset, ZXIC_UINT32 n_offset) +{ + ZXIC_UINT32 addr = 0; + DPP_REG_T *p_reg_info = NULL; + + ZXIC_COMM_CHECK_INDEX(reg_no, 0, REG_ENUM_MAX_VALUE - 1); + + p_reg_info = dpp_reg_info_get(reg_no); + ZXIC_COMM_CHECK_POINT(p_reg_info); + + /* 计算写地址 */ + addr = p_reg_info->addr; + + if (p_reg_info->array_type & DPP_REG_UNI_ARRAY) + { + if (n_offset > (p_reg_info->n_size - 1)) + ZXIC_COMM_TRACE_ERROR("reg n_offset is out of range, reg_no:%d, n:%d, size:%d\n", + reg_no, n_offset, p_reg_info->n_size - 1); + + ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(addr, n_offset * p_reg_info->n_step); + addr += n_offset * p_reg_info->n_step; + } + else if (p_reg_info->array_type & DPP_REG_BIN_ARRAY) + { + if ((n_offset > (p_reg_info->n_size - 1)) || (m_offset > (p_reg_info->m_size - 1))) + ZXIC_COMM_TRACE_ERROR("reg n_offset or m_offset is out of range, reg_no:%d, n:%d, n_size:%d, m:%d, m_size:%d,\n", + reg_no, n_offset, p_reg_info->n_size - 1, m_offset, p_reg_info->m_size - 1); + + ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW_NO_ASSERT(m_offset, p_reg_info->m_step); + ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT((m_offset * (p_reg_info->m_step)), (n_offset * (p_reg_info->n_step))); + ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(addr, (m_offset * (p_reg_info->m_step)) + (n_offset * (p_reg_info->n_step))); + addr += (m_offset * (p_reg_info->m_step)) + (n_offset * (p_reg_info->n_step)); + } + + return addr; +} + +/***********************************************************/ +/** 判断是否为4K寄存器 +* @param reg_module +* +* @return +* @remark 无 +* @see +* @author cq @date 2023/11/29 +************************************************************/ +BOOLEAN dpp_4k_reg(ZXIC_UINT32 reg_module) +{ + if((DTB4K<=reg_module)&&(SMMU14K>=reg_module)) + { + return ZXIC_TRUE; + } + + return ZXIC_FALSE; +} + +/***********************************************************/ +/** 获取NP对应模块的映射地址偏移(riscv或者非4K寄存器不做转换，host根据映射情况做转换) +* @param dev_id +* @param reg_module +* @param flags 标志位，DPP_REG_FLAG_INDIRECT DPP_REG_FLAG_DIRECT +* @param addr +* +* @return 映射地址 +* @remark 无 +* @see +* @author cq @date 2023/11/29 +************************************************************/ +ZXIC_UINT32 dpp_reg_addr_convert(ZXIC_UINT32 dev_id, ZXIC_UINT32 reg_module,ZXIC_UINT32 flags, ZXIC_UINT32 addr) +{ + ZXIC_UINT32 convert_addr = addr; + ZXIC_UINT32 i = 0; + ZXIC_UINT32 cluster_index = 0; + ZXIC_UINT32 index_4k = 0; + ZXIC_UINT32 size_4k = 4096; + ZXIC_UINT32 module_addr_offset = 0; + ZXIC_UINT32 dtb_addr_offset = SYS_DTB_BASE_ADDR + MODULE_DTB_ENQ_BASE_ADDR; + + if(DPP_REG_FLAG_INDIRECT == flags) + { + return addr; + } + + for(i=0;i<(sizeof(g_module_offset_addr)/sizeof(DPP_REG_OFFSET_ADDR));i++) + { + if(reg_module==g_module_offset_addr[i].reg_module) + { + module_addr_offset = g_module_offset_addr[i].addr_offset; + if(PPU4K==reg_module) + { + cluster_index = (addr-module_addr_offset)/DPP_PPU_CLUSTER_SPACE_SIZE; + index_4k = g_module_offset_addr[i].index_4k + cluster_index; + module_addr_offset += cluster_index * DPP_PPU_CLUSTER_SPACE_SIZE; + } + else + { + index_4k = g_module_offset_addr[i].index_4k; + } + convert_addr = ((addr + (size_4k * index_4k) + dtb_addr_offset)>module_addr_offset) + ? (addr + (size_4k * index_4k) + dtb_addr_offset - module_addr_offset) : addr; + } + } + + return convert_addr; +} + +/***********************************************************/ +/** 通用寄存器写函数 +* @param dev_id 设备号，支持多芯片 +* @param reg_no 寄存器编号 +* @param m_offset 二元寄存器的m偏移 +* @param n_offset 一元寄存器或二元寄存器的n偏移 +* @param p_data 数据指针 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author 王春雷 @date 2014/02/12 +************************************************************/ +DPP_STATUS dpp_reg_write(DPP_DEV_T *dev, ZXIC_UINT32 reg_no, ZXIC_UINT32 m_offset, ZXIC_UINT32 n_offset, ZXIC_VOID *p_data) +{ + DPP_STATUS rc = 0; + ZXIC_UINT32 i = 0; + ZXIC_UINT32 addr = 0; + +#ifdef DPP_FLOW_HW_INIT + ZXIC_UINT32 convert_addr = 0; +#endif + + ZXIC_UINT32 p_buff[REG_DATA_MAX] = {0}; + ZXIC_UINT32 temp_data = 0; + ZXIC_UINT32 reg_type = 0; + ZXIC_UINT32 reg_module = 0; + ZXIC_UINT32 reg_width = 0; + DPP_REG_T *p_reg_info = NULL; + DPP_FIELD_T *p_field_info = NULL; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev), DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), reg_no, 0, REG_ENUM_MAX_VALUE - 1); + ZXIC_COMM_CHECK_POINT(p_data); + + p_reg_info = dpp_reg_info_get(reg_no); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_reg_info); + p_field_info = p_reg_info->p_fields; + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_field_info); + reg_type = p_reg_info->flags; + reg_module = p_reg_info->module_no; + reg_width = p_reg_info->width; + ZXIC_COMM_CHECK_INDEX_UPPER(reg_width, REG_DATA_MAX*4); + +#ifndef ZXIC_OS_WIN +#ifdef DPP_FOR_LLT + if (dpp_stump_reg_en_check(DEV_ID(dev), reg_no) && (p_reg_info->flags == DPP_REG_FLAG_DIRECT || p_reg_info->flags == DPP_REG_FLAG_WO | DPP_REG_FLAG_DIRECT)) + { + rc = dpp_stump_reg_write(DEV_ID(dev), + reg_no, + m_offset, + n_offset, + p_data); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stump_reg_write"); + + return DPP_OK; + } +#endif +#endif + + /* 提取各字段数据，按各字段实际bit位宽进行拼装 */ + for (i = 0; i < p_reg_info->field_num; i++) + { + if (p_field_info[i].len <= 32) + { + /* lint -e64 */ + temp_data = *((ZXIC_UINT32 *)p_data + i) & ZXIC_COMM_GET_BIT_MASK(ZXIC_UINT32, p_field_info[i].len); + rc = zxic_comm_write_bits_ex((ZXIC_UINT8 *)p_buff, + p_reg_info->width * 8, + temp_data, + p_field_info[i].msb_pos, + p_field_info[i].len); + /* lint +e64 */ + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "zxic_comm_write_bits_ex"); + } + } + + ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev), "zxic_comm_write_bits_ex data = 0x%08x.\n", p_buff[0]); + /* 若host cpu为小端字节序，则以4字节为单位对数据进行字节序转换 */ + if(!zxic_comm_is_big_endian()) + { + for (i = 0; i < ((p_reg_info->width) / 4); i++) + { + p_buff[i] = ZXIC_COMM_CONVERT32(p_buff[i]); + + /* for debug */ + ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev), "ZXIC_COMM_CONVERT32 data = 0x%08x.\n", p_buff[i]); + } + } + + /* 计算写地址 */ + addr = dpp_reg_get_reg_addr(reg_no, m_offset, n_offset);/* 通过寄存器编号等三个参数获得寄存器的基地址 */ + + ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev), "reg_no = %d. m_offset = %d n_offset = %d\n", reg_no,m_offset,n_offset); + ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev), "baseaddr = 0x%08x.\n", addr); + +#ifdef DPP_FLOW_HW_INIT + if(dpp_4k_reg(reg_module)) + { + /* 调用寄存器写接口 */ + convert_addr = dpp_reg_addr_convert(DEV_ID(dev), reg_module, reg_type, addr); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_reg_info->p_write_fun); + rc = p_reg_info->p_write_fun(dev, convert_addr, p_buff); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "p_reg_info->p_write_fun"); + } +#else + if(DTB4K == reg_module) + { + /* 调用寄存器写接口 */ + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_reg_info->p_write_fun); + rc = p_reg_info->p_write_fun(dev, addr, p_buff); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "p_reg_info->p_write_fun"); + } +#endif + else + { + /* 调用代理通道寄存器写接口 */ + rc = dpp_agent_channel_reg_write(dev, reg_type, reg_no, reg_width, addr, p_buff); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_agent_channel_reg_write"); + } + + return DPP_OK; +} + +/***********************************************************/ +/** 通用寄存器读函数 +* @param dev_id 设备号，支持多芯片 +* @param reg_no 寄存器编号 +* @param m_offset 二元寄存器的m偏移 +* @param n_offset 一元寄存器或二元寄存器的n偏移 +* @param p_data 数据指针 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author 王春雷 @date 2014/02/12 +************************************************************/ +DPP_STATUS dpp_reg_read(DPP_DEV_T *dev, ZXIC_UINT32 reg_no, ZXIC_UINT32 m_offset, ZXIC_UINT32 n_offset, ZXIC_VOID *p_data) +{ + DPP_STATUS rc = 0; + ZXIC_UINT32 i = 0; + ZXIC_UINT32 addr = 0; +#ifdef DPP_FLOW_HW_INIT + ZXIC_UINT32 convert_addr = 0; +#endif + ZXIC_UINT32 reg_type = 0; + ZXIC_UINT32 p_buff[REG_DATA_MAX] = {0}; + ZXIC_UINT32 reg_module = 0; + ZXIC_UINT32 reg_width = 0; + DPP_REG_T *p_reg_info = NULL; + DPP_FIELD_T *p_field_info = NULL; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev), DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), reg_no, 0, REG_ENUM_MAX_VALUE - 1); + ZXIC_COMM_CHECK_POINT(p_data); + + p_reg_info = dpp_reg_info_get(reg_no); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_reg_info); + p_field_info = p_reg_info->p_fields; + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_field_info); + reg_type = p_reg_info->flags; + reg_module = p_reg_info->module_no; + reg_width = p_reg_info->width; + ZXIC_COMM_CHECK_INDEX_UPPER(reg_width, REG_DATA_MAX*4); + +#ifndef ZXIC_OS_WIN +#ifdef DPP_FOR_LLT + if (dpp_stump_reg_en_check(DEV_ID(dev), reg_no) && (p_reg_info->flags == DPP_REG_FLAG_DIRECT || p_reg_info->flags == DPP_REG_FLAG_WO | DPP_REG_FLAG_DIRECT)) + { + rc = dpp_stump_reg_read(DEV_ID(dev), + reg_no, + m_offset, + n_offset, + p_data); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stump_reg_read"); + + return DPP_OK; + } +#endif +#endif + + /* 计算读地址 */ + addr = dpp_reg_get_reg_addr(reg_no, m_offset, n_offset); +#ifdef DPP_FLOW_HW_INIT + if(dpp_4k_reg(reg_module)) + { + /* 调用寄存器读接口 */ + convert_addr = dpp_reg_addr_convert(DEV_ID(dev), reg_module, reg_type, addr); + ZXIC_COMM_CHECK_POINT(p_reg_info->p_read_fun); + rc = p_reg_info->p_read_fun(dev, convert_addr, p_buff); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "p_reg_info->p_read_fun"); + } +#else + if(DTB4K == reg_module) + { + /* 调用寄存器读接口 */ + ZXIC_COMM_CHECK_POINT(p_reg_info->p_read_fun); + rc = p_reg_info->p_read_fun(dev, addr, p_buff); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "p_reg_info->p_read_fun"); + } +#endif + else + { + /* 调用代理通道寄存器读接口 */ + rc = dpp_agent_channel_reg_read(dev, reg_type, reg_no, reg_width, addr, p_buff); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_agent_channel_reg_read"); + } + + /* 若host cpu为小端字节序，则以4字节为单位对数据进行字节序转换 */ + if (!zxic_comm_is_big_endian()) + { + for (i = 0; i < ((p_reg_info->width) / 4); i++) + { + /* for debug */ + + //printf("dpp_reg_read data = 0x%08x.\n", p_buff[i]); + ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev), "dpp_reg_read data = 0x%08x.\n", p_buff[i]); + + p_buff[i] = ZXIC_COMM_CONVERT32(p_buff[i]); + } + } + + /* 提取各字段数据，每字段以ZXIC_UINT32形式返回 */ + for (i = 0; i < p_reg_info->field_num; i++) + { + /* lint -e64 */ + rc = zxic_comm_read_bits_ex((ZXIC_UINT8 *)p_buff, + p_reg_info->width * 8, + (ZXIC_UINT32 *)p_data + i, + p_field_info[i].msb_pos, + p_field_info[i].len); + ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "zxic_comm_read_bits_ex"); + /* lint +e64 */ + } + + return DPP_OK; +} + +/***********************************************************/ +/** 通过寄存器编号配置寄存器，仅适用于32bit位宽 + 的常规寄存器 +* @param dev_id 设备号 +* @param reg_no 寄存器编号 +* @param data 数据，32bit +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author XXX @date 2019/07/10 +************************************************************/ +DPP_STATUS dpp_reg_write32(DPP_DEV_T *dev, ZXIC_UINT32 reg_no, ZXIC_UINT32 data) +{ + DPP_STATUS rc = 0; + ZXIC_UINT32 addr = 0; + DPP_REG_T *p_reg_info = NULL; + ZXIC_UINT32 value = data; + ZXIC_UINT32 j = 0; + ZXIC_UINT32 k = 0; + ZXIC_UINT32 m_size = 0; + ZXIC_UINT32 n_size = 0; + ZXIC_UINT32 reg_type = 0; + // ZXIC_UINT32 reg_module = 0; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev), DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), reg_no, 0, REG_ENUM_MAX_VALUE - 1); + + p_reg_info = dpp_reg_info_get(reg_no); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_reg_info); + reg_type = p_reg_info->flags; + // reg_module = p_reg_info->module_no; + + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_reg_info->width, 4, 4); /* width must be 32bit */ + + m_size = (p_reg_info->m_size == 0) ? (1) : (p_reg_info->m_size); + n_size = (p_reg_info->n_size == 0) ? (1) : (p_reg_info->n_size); + + /* 计算读地址 */ + for (j = 0; j < m_size; j++) + { + for (k = 0; k < n_size; k++) + { +#ifndef ZXIC_OS_WIN +#ifdef DPP_FOR_LLT + if (dpp_stump_reg_en_check(DEV_ID(dev), reg_no) && (p_reg_info->flags == DPP_REG_FLAG_DIRECT)) + { + rc = dpp_stump_reg_write(DEV_ID(dev), + reg_no, + j, + k, + &data); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stump_reg_write"); + + return DPP_OK; + } +#endif +#endif + /* 计算写地址 */ + addr = dpp_reg_get_reg_addr(reg_no, j, k); + + /* 调用代理通道寄存器写接口 */ + rc = dpp_agent_channel_reg_write(dev, reg_type, reg_no, 4, addr, &value); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_agent_channel_reg_write"); + } + } + + return DPP_OK; +} + +/***********************************************************/ +/** 通过寄存器编号读取寄存器的值，仅适用于32bit位宽的常规寄存器 +* @param dev_id 设备号 +* @param reg_no 寄存器编号 +* @param m_offset 二元寄存器的m偏移 +* @param n_offset 一元寄存器或二元寄存器的n偏移 +* @param p_data 出参，返回读取寄存器数值 +* +* @return DPP_OK-成功，DPP_ERR-失败 +* @remark 无 +* @see +* @author 石金锋 @date 2015/03/09 +************************************************************/ +DPP_STATUS dpp_reg_read32(DPP_DEV_T *dev, ZXIC_UINT32 reg_no, ZXIC_UINT32 m_offset, ZXIC_UINT32 n_offset, ZXIC_UINT32 *p_data) +{ + DPP_STATUS rc = 0; + ZXIC_UINT32 addr = 0; + ZXIC_UINT32 reg_type = 0; + // ZXIC_UINT32 reg_module = 0; + ZXIC_UINT32 p_buff[REG_DATA_MAX] = {0}; + + DPP_REG_T *p_reg_info = NULL; + + ZXIC_COMM_CHECK_POINT(dev); + ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev), DPP_DEV_CHANNEL_MAX - 1); + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), reg_no, 0, REG_ENUM_MAX_VALUE - 1); + ZXIC_COMM_CHECK_POINT(p_data); + + p_reg_info = dpp_reg_info_get(reg_no); + ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_reg_info); + reg_type = p_reg_info->flags; + // reg_module = p_reg_info->module_no; + + ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_reg_info->width, 4, 4); /* width must be 32bit */ + +#ifndef ZXIC_OS_WIN +#ifdef DPP_FOR_LLT + if (dpp_stump_reg_en_check(DEV_ID(dev), reg_no) && (p_reg_info->flags == DPP_REG_FLAG_DIRECT)) + { + rc = dpp_stump_reg_read(DEV_ID(dev), + reg_no, + m_offset, + n_offset, + p_data); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stump_reg_read"); + + return DPP_OK; + } +#endif +#endif + + /* 计算读地址 */ + addr = dpp_reg_get_reg_addr(reg_no, m_offset, n_offset); + + /* 调用代理通道寄存器读接口 */ + rc =dpp_agent_channel_reg_read(dev, reg_type, reg_no, 4, addr, p_buff); + ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_agent_channel_reg_read"); + *p_data = p_buff[0]; + + return DPP_OK; +} diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/reg/dpp_reg_info.c b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/reg/dpp_reg_info.c new file mode 100644 index 0000000..6fb5a54 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/reg/dpp_reg_info.c @@ -0,0 +1,101395 @@ +#include "dpp_module.h" +#include "dpp_reg_struct.h" +#include "dpp_reg_info.h" + +DPP_FIELD_T g_etm_cfgmt_cpu_check_reg_reg[] = + { + {"cpu_check_reg", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_etm_cfgmt_cfgmt_blksize_reg[] = + { + {"cfgmt_blksize", DPP_FIELD_FLAG_RW, 1, 2, 0x1, 0x0}, + }; +DPP_FIELD_T g_etm_cfgmt_reg_int_state_reg_reg[] = + { + {"shap_int", DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0}, + {"crdt_int", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0}, + {"mmu_int", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0}, + {"qmu_int", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0}, + {"cgavd_int", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0}, + {"olif_int", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0}, + {"cfgmt_int_buf", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cfgmt_reg_int_mask_reg_reg[] = + { + {"shap_int_mask", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"crdt_int_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"tmmu_int_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"qmu_int_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"cgavd_int_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"olif_int_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"cfgmt_int_buf_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_etm_cfgmt_timeout_limit_reg[] = + { + {"timeout_limit", DPP_FIELD_FLAG_RW, 15, 16, 0xfff, 0x0}, + }; +DPP_FIELD_T g_etm_cfgmt_subsystem_rdy_reg_reg[] = + { + {"olif_rdy", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0}, + {"qmu_rdy", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0}, + {"cgavd_rdy", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0}, + {"tmmu_rdy", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0}, + {"shap_rdy", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0}, + {"crdt_rdy", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cfgmt_subsystem_en_reg_reg[] = + { + {"subsystem_en_buf_31_28", DPP_FIELD_FLAG_RW, 31, 4, 0x0, 0x0}, + {"subsystem_en_buf_25_0", DPP_FIELD_FLAG_RW, 25, 26, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cfgmt_cfgmt_int_reg_reg[] = + { + {"cfgmt_int_buf", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cfgmt_qmu_work_mode_reg[] = + { + {"qmu_work_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cfgmt_cfgmt_ddr_attach_reg[] = + { + {"cfgmt_ddr_attach", DPP_FIELD_FLAG_RW, 9, 10, 0xf, 0x0}, + }; +DPP_FIELD_T g_etm_cfgmt_cnt_mode_reg_reg[] = + { + {"cfgmt_fc_count_mode", DPP_FIELD_FLAG_RW, 2, 1, 0x0, 0x0}, + {"cfgmt_count_rd_mode", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0}, + {"cfgmt_count_overflow_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_etm_cfgmt_clkgate_en_reg[] = + { + {"clkgate_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cfgmt_softrst_en_reg[] = + { + {"softrst_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_olif_imem_prog_full_reg[] = + { + {"imem_prog_full_assert", DPP_FIELD_FLAG_RW, 24, 9, 0x9c, 0x0}, + {"imem_prog_full_negate", DPP_FIELD_FLAG_RW, 8, 9, 0x94, 0x0}, + }; +DPP_FIELD_T g_etm_olif_qmu_para_prog_full_reg[] = + { + {"qmu_para_prog_full_assert", DPP_FIELD_FLAG_RW, 26, 11, 0x370, 0x0}, + {"qmu_para_prog_full_negate", DPP_FIELD_FLAG_RW, 10, 11, 0x370, 0x0}, + }; +DPP_FIELD_T g_etm_olif_olif_int_mask_reg[] = + { + {"emem_dat_sop_err_mask", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + {"emem_dat_eop_err_mask", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0}, + {"imem_dat_sop_err_mask", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"imem_dat_eop_err_mask", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"crcram_parity_err_mask", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"emem_fifo_ecc_mask", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"imem_fifo_ecc_mask", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"emem_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"emem_fifo_udf_mask", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"imem_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"imem_fifo_udf_mask", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"para_fifo_ecc_mask", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"para_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"para_fifo_udf_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"itmh_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"itmh_ecc_double_err_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"order_fifo_parity_err_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"order_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"order_fifo_udf_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_etm_olif_itmhram_parity_err_2_int_reg[] = + { + {"emem_dat_sop_err", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"emem_dat_eop_err", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"imem_dat_sop_err", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"imem_dat_eop_err", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"crcram_parity_err_1_int", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"emem_fifo_ecc_single_err_int", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"emem_fifo_ecc_double_err_int", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"imem_fifo_ecc_single_err_int", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"imem_fifo_ecc_double_err_int", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"emem_fifo_ovf_int", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"emem_fifo_udf_int", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"imem_fifo_ovf_int", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"imem_fifo_udf_int", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"para_fifo_ecc_single_err_int", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"para_fifo_ecc_double_err_int", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"para_fifo_ovf_int", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"para_fifo_udf_int", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"itmh_ecc_single_err_int", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"itmh_ecc_double_err_int", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"order_fifo_parity_err_int", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"order_fifo_ovf_int", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"order_fifo_udf_int", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_olif_lif0_port_rdy_mask_h_reg[] = + { + {"lif0_port_rdy_mask_h", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_olif_lif0_port_rdy_mask_l_reg[] = + { + {"lif0_port_rdy_mask_l", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_olif_lif0_port_rdy_cfg_h_reg[] = + { + {"lif0_port_rdy_cfg_h", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_olif_lif0_port_rdy_cfg_l_reg[] = + { + {"lif0_port_rdy_cfg_l", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_olif_lif0_link_rdy_mask_cfg_reg[] = + { + {"lif0_link_rdy_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0}, + {"lif0_link_rdy_cfg", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_olif_tm_lif_stat_cfg_reg[] = + { + {"all_or_by_port", DPP_FIELD_FLAG_RW, 24, 1, 0x0, 0x0}, + {"i_or_e_sel", DPP_FIELD_FLAG_RW, 17, 2, 0x0, 0x0}, + {"port_or_dest_id_sel", DPP_FIELD_FLAG_RW, 8, 1, 0x0, 0x0}, + {"port_dest_id", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x1}, + }; +DPP_FIELD_T g_etm_olif_tm_lif_sop_stat_reg[] = + { + {"tm_lif_sop_stat", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_olif_tm_lif_eop_stat_reg[] = + { + {"tm_lif_eop_stat", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_olif_tm_lif_vld_stat_reg[] = + { + {"tm_lif_vld_stat", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_prog_full_assert_cfg_reg[] = + { + {"prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 31, 16, 0xdc, 0x0}, + {"prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 15, 16, 0xc8, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cgavd_int_reg[] = + { + {"cgavd_int", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cgavd_ram_err_reg[] = + { + {"flow_qnum_intb", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"flow_qnum_inta", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"pp_qlen_inta", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"pp_qlen_intb", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"pp_tdth_int", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"flow_tdth_inta", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"flow_tdth_intb", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"flow_qlen_inta", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"flow_qlen_intb", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"qmu_cgavd_fifo_uv_int", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"qmu_cgavd_fifo_ov_int", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"pds_deal_fifo_ov_int", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"pds_deal_fifo_uv_int", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cgavd_int_mask_reg[] = + { + {"cgavd_int_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cgavd_ram_err_int_mask_reg[] = + { + {"flow_qnum_inta_mask", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"flow_qnum_intb_mask", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"pp_qlen_inta_mask", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"pp_qlen_intb_mask", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"pp_tdth_int_mask", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"flow_tdth_inta_mask", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"flow_tdth_intb_mask", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"flow_qlen_inta_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"flow_qlen_intb_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"qmu_cgavd_fifo_uv_int_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"qmu_cgavd_fifo_ov_int_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"pds_deal_fifo_ov_int_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"pds_deal_fifo_uv_int_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cfgmt_byte_mode_reg[] = + { + {"cfgmt_byte_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_avg_qlen_return_zero_en_reg[] = + { + {"avg_qlen_return_zero_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_flow_wred_q_len_th_reg[] = + { + {"flow_wred_q_len_th", DPP_FIELD_FLAG_RW, 28, 29, 0x400, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_flow_wq_reg[] = + { + {"wq_flow", DPP_FIELD_FLAG_RW, 3, 4, 0x9, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_flow_wred_max_th_reg[] = + { + {"flow_wred_max_th", DPP_FIELD_FLAG_RW, 28, 29, 0x1000, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_flow_wred_min_th_reg[] = + { + {"flow_wred_min_th", DPP_FIELD_FLAG_RW, 28, 29, 0x10, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_flow_wred_cfg_para_reg[] = + { + {"flow_wred_cfg_para", DPP_FIELD_FLAG_RW, 31, 32, 0x13ec, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_pp_avg_q_len_reg[] = + { + {"pp_avg_q_len", DPP_FIELD_FLAG_RW, 28, 29, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_pp_td_th_reg[] = + { + {"pp_td_th", DPP_FIELD_FLAG_RW, 28, 29, 0x400, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_pp_ca_mtd_reg[] = + { + {"pp_ca_mtd", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_pp_wred_grp_th_en_reg[] = + { + {"pp_wred_grp", DPP_FIELD_FLAG_RW, 3, 3, 0x0, 0x0}, + {"pp_wred_grp_th_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_pp_wred_q_len_th_reg[] = + { + {"pp_wred_q_len_th", DPP_FIELD_FLAG_RW, 28, 29, 0x100000, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_pp_wq_reg[] = + { + {"wq_pp", DPP_FIELD_FLAG_RW, 3, 4, 0x9, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_pp_wred_max_th_reg[] = + { + {"pp_wred_max_th", DPP_FIELD_FLAG_RW, 28, 29, 0x80000, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_pp_wred_min_th_reg[] = + { + {"pp_wred_min_th", DPP_FIELD_FLAG_RW, 28, 29, 0x800, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_pp_cfg_para_reg[] = + { + {"pp_cfg_para", DPP_FIELD_FLAG_RW, 31, 32, 0x9f600, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_sys_avg_q_len_reg[] = + { + {"sys_avg_q_len", DPP_FIELD_FLAG_RW, 28, 29, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_sys_td_th_reg[] = + { + {"sys_td_th", DPP_FIELD_FLAG_RW, 28, 29, 0x1ff00, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_sys_cgavd_metd_reg[] = + { + {"sys_cgavd_metd", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_sys_cfg_q_grp_para_reg[] = + { + {"gred_q_len_th_sys", DPP_FIELD_FLAG_RW, 28, 29, 0x1fffe00, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_sys_wq_reg[] = + { + {"wq_sys", DPP_FIELD_FLAG_RW, 3, 4, 0x9, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_gred_max_th_reg[] = + { + {"gred_max_th", DPP_FIELD_FLAG_RW, 28, 29, 0x1000000, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_gred_mid_th_reg[] = + { + {"gred_mid_th", DPP_FIELD_FLAG_RW, 28, 29, 0x600000, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_gred_min_th_reg[] = + { + {"gred_min_th", DPP_FIELD_FLAG_RW, 28, 29, 0x80000, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_gred_cfg_para0_reg[] = + { + {"gred_cfg_para0", DPP_FIELD_FLAG_RW, 31, 32, 0x92aaaa, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_gred_cfg_para1_reg[] = + { + {"gred_cfg_para1", DPP_FIELD_FLAG_RW, 31, 32, 0x1900000, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_gred_cfg_para2_reg[] = + { + {"gred_cfg_para2", DPP_FIELD_FLAG_RW, 31, 32, 0xf00000, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_sys_window_th_h_reg[] = + { + {"sys_window_th_h", DPP_FIELD_FLAG_RW, 28, 29, 0x1d00000, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_sys_window_th_l_reg[] = + { + {"sys_window_th_l", DPP_FIELD_FLAG_RW, 28, 29, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_amplify_gene0_reg[] = + { + {"amplify_gene0", DPP_FIELD_FLAG_RW, 11, 12, 0x200, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_amplify_gene1_reg[] = + { + {"amplify_gene1", DPP_FIELD_FLAG_RW, 11, 12, 0x82, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_amplify_gene2_reg[] = + { + {"amplify_gene2", DPP_FIELD_FLAG_RW, 11, 12, 0x80, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_amplify_gene3_reg[] = + { + {"amplify_gene3", DPP_FIELD_FLAG_RW, 11, 12, 0x7e, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_amplify_gene4_reg[] = + { + {"amplify_gene4", DPP_FIELD_FLAG_RW, 11, 12, 0x7c, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_amplify_gene5_reg[] = + { + {"amplify_gene5", DPP_FIELD_FLAG_RW, 11, 12, 0x78, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_amplify_gene6_reg[] = + { + {"amplify_gene6", DPP_FIELD_FLAG_RW, 11, 12, 0x70, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_amplify_gene7_reg[] = + { + {"amplify_gene7", DPP_FIELD_FLAG_RW, 11, 12, 0x68, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_amplify_gene8_reg[] = + { + {"amplify_gene8", DPP_FIELD_FLAG_RW, 11, 12, 0x60, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_amplify_gene9_reg[] = + { + {"amplify_gene9", DPP_FIELD_FLAG_RW, 11, 12, 0x58, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_amplify_gene10_reg[] = + { + {"amplify_gene10", DPP_FIELD_FLAG_RW, 11, 12, 0x50, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_amplify_gene11_reg[] = + { + {"amplify_gene11", DPP_FIELD_FLAG_RW, 11, 12, 0x40, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_amplify_gene12_reg[] = + { + {"amplify_gene12", DPP_FIELD_FLAG_RW, 11, 12, 0x20, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_amplify_gene13_reg[] = + { + {"amplify_gene13", DPP_FIELD_FLAG_RW, 11, 12, 0x8, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_amplify_gene14_reg[] = + { + {"amplify_gene14", DPP_FIELD_FLAG_RW, 11, 12, 0x2, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_amplify_gene15_reg[] = + { + {"amplify_gene15", DPP_FIELD_FLAG_RW, 11, 12, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_equal_pkt_len_en_reg[] = + { + {"equal_pkt_len_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_equal_pkt_len_th0_reg[] = + { + {"equal_pkt_len_th0", DPP_FIELD_FLAG_RW, 14, 15, 0x4, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_equal_pkt_len_th1_reg[] = + { + {"equal_pkt_len_th1", DPP_FIELD_FLAG_RW, 14, 15, 0x8, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_equal_pkt_len_th2_reg[] = + { + {"equal_pkt_len_th2", DPP_FIELD_FLAG_RW, 14, 15, 0x10, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_equal_pkt_len_th3_reg[] = + { + {"equal_pkt_len_th3", DPP_FIELD_FLAG_RW, 14, 15, 0x18, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_equal_pkt_len_th4_reg[] = + { + {"equal_pkt_len_th4", DPP_FIELD_FLAG_RW, 14, 15, 0x20, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_equal_pkt_len_th5_reg[] = + { + {"equal_pkt_len_th5", DPP_FIELD_FLAG_RW, 14, 15, 0x40, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_equal_pkt_len_th6_reg[] = + { + {"equal_pkt_len_th6", DPP_FIELD_FLAG_RW, 14, 15, 0x60, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_equal_pkt_len0_reg[] = + { + {"equal_pkt_len0", DPP_FIELD_FLAG_RW, 14, 15, 0x20, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_equal_pkt_len1_reg[] = + { + {"equal_pkt_len1", DPP_FIELD_FLAG_RW, 14, 15, 0x30, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_equal_pkt_len2_reg[] = + { + {"equal_pkt_len2", DPP_FIELD_FLAG_RW, 14, 15, 0x40, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_equal_pkt_len3_reg[] = + { + {"equal_pkt_len3", DPP_FIELD_FLAG_RW, 14, 15, 0x50, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_equal_pkt_len4_reg[] = + { + {"equal_pkt_len4", DPP_FIELD_FLAG_RW, 14, 15, 0x60, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_equal_pkt_len5_reg[] = + { + {"equal_pkt_len5", DPP_FIELD_FLAG_RW, 14, 15, 0x70, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_equal_pkt_len6_reg[] = + { + {"equal_pkt_len6", DPP_FIELD_FLAG_RW, 14, 15, 0x78, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_equal_pkt_len7_reg[] = + { + {"equal_pkt_len7", DPP_FIELD_FLAG_RW, 14, 15, 0x80, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_flow_cpu_set_avg_len_reg[] = + { + {"flow_cpu_set_avg_len", DPP_FIELD_FLAG_RW, 28, 29, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_flow_cpu_set_q_len_reg[] = + { + {"flow_cpu_set_q_len", DPP_FIELD_FLAG_RW, 28, 29, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_pp_cpu_set_avg_q_len_reg[] = + { + {"pp_cpu_set_avg_q_len", DPP_FIELD_FLAG_RW, 28, 29, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_pp_cpu_set_q_len_reg[] = + { + {"pp_cpu_set_q_len", DPP_FIELD_FLAG_RW, 28, 29, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_sys_cpu_set_avg_len_reg[] = + { + {"sys_cpu_set_avg_len", DPP_FIELD_FLAG_RW, 28, 29, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_sys_cpu_set_q_len_reg[] = + { + {"sys_cpu_set_q_len", DPP_FIELD_FLAG_RW, 28, 29, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_pke_len_calc_sign_reg[] = + { + {"pke_len_calc_sign", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_rd_cpu_or_ram_reg[] = + { + {"cpu_sel_sys_q_len_en", DPP_FIELD_FLAG_RW, 5, 1, 0x0, 0x0}, + {"cpu_sel_sys_avg_q_len_en", DPP_FIELD_FLAG_RW, 4, 1, 0x0, 0x0}, + {"cpu_sel_pp_q_len_en", DPP_FIELD_FLAG_RW, 3, 1, 0x0, 0x0}, + {"cpu_sel_pp_avg_q_len_en", DPP_FIELD_FLAG_RW, 2, 1, 0x0, 0x0}, + {"cpu_sel_flow_q_len_en", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0}, + {"cpu_sel_flow_avg_q_len_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_q_len_update_disable_reg[] = + { + {"q_len_sys_update_en", DPP_FIELD_FLAG_RW, 2, 1, 0x0, 0x0}, + {"q_len_pp_update_en", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0}, + {"q_len_flow_update_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cgavd_dp_sel_reg[] = + { + {"flow_dp_sel_high", DPP_FIELD_FLAG_RW, 8, 1, 0x0, 0x0}, + {"flow_dp_sel_mid", DPP_FIELD_FLAG_RW, 7, 1, 0x0, 0x0}, + {"flow_dp_sel_low", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"pp_dp_sel_high", DPP_FIELD_FLAG_RW, 5, 1, 0x0, 0x0}, + {"pp_dp_sel_mid", DPP_FIELD_FLAG_RW, 4, 1, 0x0, 0x0}, + {"pp_dp_sel_low", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"sys_dp_sel_high", DPP_FIELD_FLAG_RW, 2, 1, 0x0, 0x0}, + {"sys_dp_sel_mid", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0}, + {"sys_dp_sel_low", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cgavd_sub_en_reg[] = + { + {"cgavd_sa_sub_en", DPP_FIELD_FLAG_RW, 3, 1, 0x0, 0x0}, + {"cgavd_sys_sub_en", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"cgavd_pp_sub_en", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0}, + {"cgavd_flow_sub_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_default_start_queue_reg[] = + { + {"default_start_queue", DPP_FIELD_FLAG_RW, 13, 14, 0x100, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_default_finish_queue_reg[] = + { + {"default_finish_queue", DPP_FIELD_FLAG_RW, 13, 14, 0x1ff, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_protocol_start_queue_reg[] = + { + {"protocol_start_queue", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_protocol_finish_queue_reg[] = + { + {"protocol_finish_queue", DPP_FIELD_FLAG_RW, 13, 14, 0xff, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_uniform_td_th_reg[] = + { + {"uniform_td_th", DPP_FIELD_FLAG_RW, 28, 29, 0x200, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_uniform_td_th_en_reg[] = + { + {"uniform_td_th_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cgavd_cfg_fc_reg[] = + { + {"cgavd_cfg_fc", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cgavd_cfg_no_fc_reg[] = + { + {"cgavd_cfg_no_fc", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cgavd_force_imem_omem_reg[] = + { + {"imem_omem_force_en", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0}, + {"choose_imem_omem", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cgavd_sys_q_len_l_reg[] = + { + {"cgavd_sys_q_len_l", DPP_FIELD_FLAG_RO, 28, 29, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_default_queue_en_reg[] = + { + {"default_queue_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_protocol_queue_en_reg[] = + { + {"protocol_queue_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cfg_tc_flowid_dat_reg[] = + { + {"cfg_tc_flowid_dat", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_flow_td_th_reg[] = + { + {"flow_td_th", DPP_FIELD_FLAG_RW, 28, 29, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_flow_ca_mtd_reg[] = + { + {"flow_ca_mtd", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_flow_dynamic_th_en_reg[] = + { + {"flow_dynamic_th_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_pp_num_reg[] = + { + {"pp_num", DPP_FIELD_FLAG_RW, 6, 7, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_flow_q_len_reg[] = + { + {"flow_q_len", DPP_FIELD_FLAG_RO, 28, 29, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_flow_wred_grp_reg[] = + { + {"flow_wred_grp", DPP_FIELD_FLAG_RW, 4, 5, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_flow_avg_q_len_reg[] = + { + {"flow_avg_q_len", DPP_FIELD_FLAG_RW, 28, 29, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_qos_sign_reg[] = + { + {"qos_sign_flow_cfg_din", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_q_pri_reg[] = + { + {"qpri_flow_cfg_din", DPP_FIELD_FLAG_RW, 2, 3, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_odma_tm_itmd_rd_low_reg[] = + { + {"odma_tm_itmd_low", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_odma_tm_itmd_rd_mid_reg[] = + { + {"odma_tm_itmd_mid", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_odma_tm_itmd_rd_high_reg[] = + { + {"odma_tm_itmd_high", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cgavd_stat_pkt_len_reg[] = + { + {"expect_deq_pkt_len", DPP_FIELD_FLAG_RW, 25, 10, 0x0, 0x0}, + {"expect_enq_pkt_len", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cgavd_stat_qnum_reg[] = + { + {"cgavd_unexcept_qnum", DPP_FIELD_FLAG_RW, 29, 14, 0x0, 0x0}, + {"cgavd_except_qnum", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cgavd_stat_dp_reg[] = + { + {"cgavd_stat_dp", DPP_FIELD_FLAG_RW, 2, 3, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_flow_num0_reg[] = + { + {"flow_num0", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_flow_num1_reg[] = + { + {"flow_num1", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_flow_num2_reg[] = + { + {"flow_num2", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_flow_num3_reg[] = + { + {"flow_num3", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_flow_num4_reg[] = + { + {"flow_num4", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_flow0_imem_cnt_reg[] = + { + {"flow0_imem_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_flow1_imem_cnt_reg[] = + { + {"flow1_imem_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_flow2_imem_cnt_reg[] = + { + {"flow2_imem_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_flow3_imem_cnt_reg[] = + { + {"flow3_imem_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_flow4_imem_cnt_reg[] = + { + {"flow4_imem_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_flow0_drop_cnt_reg[] = + { + {"flow0_drop_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_flow1_drop_cnt_reg[] = + { + {"flow1_drop_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_flow2_drop_cnt_reg[] = + { + {"flow2_drop_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_flow3_drop_cnt_reg[] = + { + {"flow3_drop_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_flow4_drop_cnt_reg[] = + { + {"flow4_drop_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_fc_count_mode_reg[] = + { + {"fc_count_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_qmu_cgavd_fc_num_reg[] = + { + {"qmu_cgavd_fc_state", DPP_FIELD_FLAG_RO, 31, 1, 0x0, 0x0}, + {"qmu_cgavd_fc_num", DPP_FIELD_FLAG_RO, 30, 31, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cgavd_odma_fc_num_reg[] = + { + {"cgavd_lif_fc_state", DPP_FIELD_FLAG_RO, 31, 1, 0x0, 0x0}, + {"cgavd_lif_fc_num", DPP_FIELD_FLAG_RO, 30, 31, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cfg_offset_reg[] = + { + {"cfg_offset", DPP_FIELD_FLAG_RW, 8, 9, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_tmmu_init_done_reg[] = + { + {"tmmu_init_done", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_tmmu_int_mask_1_reg[] = + { + {"imem_enq_rd_fifo_full_mask", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0}, + {"imem_enq_rd_fifo_overflow_mask", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0}, + {"imem_enq_rd_fifo_underflow_mask", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0}, + {"imem_enq_drop_fifo_full_mask", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0}, + {"imem_enq_drop_fifo_overflow_mask", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0}, + {"imem_enq_drop_fifo_underflow_mask", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0}, + {"imem_deq_rd_fifo_full_mask", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"imem_deq_rd_fifo_overflow_mask", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0}, + {"imem_deq_rd_fifo_underflow_mask", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + {"imem_deq_drop_fifo_full_mask", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0}, + {"imem_deq_drop_fifo_overflow_mask", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"imem_deq_drop_fifo_underflow_mask", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"dma_data_fifo_full_mask", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"dma_data_fifo_overflow_mask", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"dma_data_fifo_underflow_mask", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"wr_cmd_fifo_full_mask", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"wr_cmd_fifo_overflow_mask", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"wr_cmd_fifo_underflow_mask", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"cached_pd_fifo_full_mask", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"cached_pd_fifo_overflow_mask", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"cached_pd_fifo_underflow_mask", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"emem_pd_fifo_full_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"emem_pd_fifo_overflow_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"emem_pd_fifo_underflow_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"pd_order_fifo_full_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"pd_order_fifo_overflow_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"pd_order_fifo_underflow_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_tmmu_int_mask_2_reg[] = + { + {"dma_data_fifo_parity_err_mask", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"imem_enq_rd_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"imem_enq_rd_fifo_ecc_double_err_mask", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"imem_enq_drop_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"imem_enq_drop_fifo_ecc_double_err_mask", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"imem_deq_rd_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"imem_deq_rd_fifo_ecc_double_err_mask", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"imem_deq_drop_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"imem_deq_drop_fifo_ecc_double_err_mask", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"wr_cmd_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"wr_cmd_fifo_ecc_double_err_mask", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"pd_cache_ram_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"pd_cache_ram_ecc_double_err_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"cached_pd_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"cached_pd_fifo_ecc_double_err_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"emem_pd_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"emem_pd_fifo_ecc_double_err_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_cfgmt_tm_pure_imem_en_reg[] = + { + {"cfgmt_tm_pure_imem_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_cfgmt_force_ddr_rdy_cfg_reg[] = + { + {"cfgmt_force_ddr_rdy_cfg", DPP_FIELD_FLAG_RW, 9, 10, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_pd_order_fifo_aful_th_reg[] = + { + {"pd_order_fifo_aful_th", DPP_FIELD_FLAG_RW, 10, 11, 0x384, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_cached_pd_fifo_aful_th_reg[] = + { + {"cached_pd_fifo_aful_th", DPP_FIELD_FLAG_RW, 9, 10, 0x1f0, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_wr_cmd_fifo_aful_th_reg[] = + { + {"wr_cmd_fifo_aful_th", DPP_FIELD_FLAG_RW, 9, 10, 0x190, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_imem_enq_rd_fifo_aful_th_reg[] = + { + {"imem_enq_rd_fifo_aful_th", DPP_FIELD_FLAG_RW, 6, 7, 0x10, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_imem_enq_drop_fifo_aful_th_reg[] = + { + {"imem_enq_drop_fifo_aful_th", DPP_FIELD_FLAG_RW, 6, 7, 0x10, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_imem_deq_drop_fifo_aful_th_reg[] = + { + {"imem_deq_drop_fifo_aful_th", DPP_FIELD_FLAG_RW, 6, 7, 0x10, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_imem_deq_rd_fifo_aful_th_reg[] = + { + {"imem_deq_rd_fifo_aful_th", DPP_FIELD_FLAG_RW, 10, 11, 0x320, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_tmmu_states_1_reg[] = + { + {"imem_enq_rd_fifo_full", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"imem_enq_rd_fifo_overflow", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"imem_enq_rd_fifo_underflow", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"imem_enq_drop_fifo_full", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"imem_enq_drop_fifo_overflow", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"imem_enq_drop_fifo_underflow", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"imem_deq_rd_fifo_full", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"imem_deq_rd_fifo_overflow", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"imem_deq_rd_fifo_underflow", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"imem_deq_drop_fifo_full", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"imem_deq_drop_fifo_overflow", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"imem_deq_drop_fifo_underflow", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"dma_data_fifo_full", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"dma_data_fifo_overflow", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"dma_data_fifo_underflow", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"wr_cmd_fifo_full", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"wr_cmd_fifo_overflow", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"wr_cmd_fifo_underflow", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"cached_pd_fifo_full", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"cached_pd_fifo_overflow", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"cached_pd_fifo_underflow", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"emem_pd_fifo_full", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"emem_pd_fifo_overflow", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"emem_pd_fifo_underflow", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"pd_order_fifo_full", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"pd_order_fifo_overflow", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"pd_order_fifo_underflow", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_tmmu_states_2_reg[] = + { + {"dma_data_fifo_parity_err", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"imem_enq_rd_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"imem_enq_rd_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"imem_enq_drop_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"imem_enq_drop_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"imem_deq_rd_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"imem_deq_rd_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"imem_deq_drop_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"imem_deq_drop_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"wr_cmd_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"wr_cmd_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"pd_cache_ram_ecc_single_err", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"pd_cache_ram_ecc_double_err", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"cached_pd_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"cached_pd_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"emem_pd_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"emem_pd_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_shap_shap_ind_cmd_reg[] = + { + {"rd", DPP_FIELD_FLAG_RW, 28, 1, 0x0, 0x0}, + {"mem_id", DPP_FIELD_FLAG_RW, 27, 8, 0x0, 0x0}, + {"addr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_shap_shap_ind_sta_reg[] = + { + {"indirectaccessdone", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_etm_shap_shap_ind_data0_reg[] = + { + {"indirectdata0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_shap_shap_ind_data1_reg[] = + { + {"indirectdata1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_shap_full_threshold_reg[] = + { + {"full_threshold", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_shap_empty_threshold_reg[] = + { + {"empty_threshold", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_shap_shap_sta_init_cfg_reg[] = + { + {"sta_ram_init_done", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0}, + {"sta_ram_init_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_shap_shap_cfg_init_cfg_reg[] = + { + {"cfg_ram_init_done", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0}, + {"cfg_ram_init_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_shap_token_mode_switch_reg[] = + { + {"token_mode_switch", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_shap_token_grain_reg[] = + { + {"token_grain", DPP_FIELD_FLAG_RW, 2, 3, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_shap_crd_grain_reg[] = + { + {"crd_grain", DPP_FIELD_FLAG_RW, 20, 21, 0x8fc, 0x0}, + }; +DPP_FIELD_T g_etm_shap_shap_stat_ctrl_reg[] = + { + {"shap_stat_ctrl", DPP_FIELD_FLAG_RW, 1, 2, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_shap_token_stat_id_reg[] = + { + {"token_stat_id", DPP_FIELD_FLAG_RW, 10, 11, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_shap_token_stat_reg[] = + { + {"token_stat", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_shap_shap_stat_clk_cnt_reg[] = + { + {"shap_stat_clk_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_shap_shap_bucket_map_tbl_reg[] = + { + {"shap_map", DPP_FIELD_FLAG_RW, 6, 7, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_shap_bkt_para_tbl_reg[] = + { + {"bucket_depth", DPP_FIELD_FLAG_RW, 35, 11, 0x0, 0x0}, + {"bucket_rate", DPP_FIELD_FLAG_RW, 24, 25, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_credit_en_reg[] = + { + {"credit_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_crt_inter1_reg[] = + { + {"crd_inter1", DPP_FIELD_FLAG_RW, 8, 9, 0x2d, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_db_token_reg[] = + { + {"db_token", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_crs_flt_cfg_reg[] = + { + {"crs_flt_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_th_sp_reg[] = + { + {"th_sp", DPP_FIELD_FLAG_RW, 14, 15, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_th_wfq_fq_reg[] = + { + {"th_fq", DPP_FIELD_FLAG_RW, 31, 16, 0x0, 0x0}, + {"th_wfq", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_th_wfq2_fq2_reg[] = + { + {"th_fq2", DPP_FIELD_FLAG_RW, 31, 16, 0x0, 0x0}, + {"th_wfq2", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_th_wfq4_fq4_reg[] = + { + {"th_fq4", DPP_FIELD_FLAG_RW, 31, 16, 0x0, 0x0}, + {"th_wfq4", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_cfg_state_reg[] = + { + {"cfg_state", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_crdt_ind_cmd_reg[] = + { + {"rd", DPP_FIELD_FLAG_RW, 28, 1, 0x0, 0x0}, + {"mem_id", DPP_FIELD_FLAG_RW, 27, 8, 0x0, 0x0}, + {"addr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_crdt_ind_sta_reg[] = + { + {"indirectaccessdone", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_crdt_ind_data0_reg[] = + { + {"indirectdata0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_crdt_ind_data1_reg[] = + { + {"indirectdata1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_crdt_state_reg[] = + { + {"crdt_int", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0}, + {"crdt_rdy", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_stat_que_id_0_reg[] = + { + {"stat_que_id_0", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_stat_que_id_1_reg[] = + { + {"stat_que_id_1", DPP_FIELD_FLAG_RW, 13, 14, 0x1, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_stat_que_id_2_reg[] = + { + {"stat_que_id_2", DPP_FIELD_FLAG_RW, 13, 14, 0x2, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_stat_que_id_3_reg[] = + { + {"stat_que_id_3", DPP_FIELD_FLAG_RW, 13, 14, 0x3, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_stat_que_id_4_reg[] = + { + {"stat_que_id_4", DPP_FIELD_FLAG_RW, 13, 14, 0x4, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_stat_que_id_5_reg[] = + { + {"stat_que_id_5", DPP_FIELD_FLAG_RW, 13, 14, 0x5, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_stat_que_id_6_reg[] = + { + {"stat_que_id_6", DPP_FIELD_FLAG_RW, 13, 14, 0x6, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_stat_que_id_7_reg[] = + { + {"stat_que_id_7", DPP_FIELD_FLAG_RW, 13, 14, 0x7, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_stat_que_id_8_reg[] = + { + {"stat_que_id_8", DPP_FIELD_FLAG_RW, 13, 14, 0x8, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_stat_que_id_9_reg[] = + { + {"stat_que_id_9", DPP_FIELD_FLAG_RW, 13, 14, 0x9, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_stat_que_id_10_reg[] = + { + {"stat_que_id_10", DPP_FIELD_FLAG_RW, 13, 14, 0xa, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_stat_que_id_11_reg[] = + { + {"stat_que_id_11", DPP_FIELD_FLAG_RW, 13, 14, 0xb, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_stat_que_id_12_reg[] = + { + {"stat_que_id_12", DPP_FIELD_FLAG_RW, 13, 14, 0xc, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_stat_que_id_13_reg[] = + { + {"stat_que_id_13", DPP_FIELD_FLAG_RW, 13, 14, 0xd, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_stat_que_id_14_reg[] = + { + {"stat_que_id_14", DPP_FIELD_FLAG_RW, 13, 14, 0xe, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_stat_que_id_15_reg[] = + { + {"stat_que_id_15", DPP_FIELD_FLAG_RW, 13, 14, 0xf, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_stat_que_credit_reg[] = + { + {"stat_que_credit_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_crdt_cfg_ram_init_reg[] = + { + {"cfg_ram_init_done", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0}, + {"cfg_ram_init_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_crdt_sta_ram_init_reg[] = + { + {"sta_ram_init_done", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0}, + {"sta_ram_init_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_crs_que_id_reg[] = + { + {"crs_que_id", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_qmu_crs_end_state_reg[] = + { + {"qmu_crs_end_state", DPP_FIELD_FLAG_RO, 1, 2, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_shap_rdy_reg[] = + { + {"shap_rdy", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_shap_int_reg_reg[] = + { + {"pp_c_token_min_int", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_shap_int_mask_reg_reg[] = + { + {"pp_c_token_min_int_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_token_state_almost_empty_th_reg[] = + { + {"token_state_almost_empty_th", DPP_FIELD_FLAG_RW, 16, 17, 0x1, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_token_state_empty_th_reg[] = + { + {"token_state_empty_th", DPP_FIELD_FLAG_RW, 16, 17, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_full_th_reg[] = + { + {"token_state_full_th", DPP_FIELD_FLAG_RW, 16, 17, 0x2, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_pp_c_level_shap_en_reg[] = + { + {"pp_c_level_shap_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_enq_token_th_reg[] = + { + {"enq_token_th", DPP_FIELD_FLAG_RW, 11, 12, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_pp_tokenq_level1_qstate_weight_cir_reg[] = + { + {"pp_pp_q_state_cir", DPP_FIELD_FLAG_RO, 31, 1, 0x0, 0x0}, + {"pp_pp_q_weight_wfq_l1_cir", DPP_FIELD_FLAG_RO, 29, 30, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_pp_idle_weight_level1_cir_reg[] = + { + {"pp_idle_q_weight_wfq_l1_cir", DPP_FIELD_FLAG_RO, 25, 26, 0x1ffffff, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_rci_grade_th_0_cfg_reg[] = + { + {"rci_grade_th_0_cfg", DPP_FIELD_FLAG_RW, 11, 12, 0x177, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_rci_grade_th_1_cfg_reg[] = + { + {"rci_grade_th_1_cfg", DPP_FIELD_FLAG_RW, 11, 12, 0x2ee, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_rci_grade_th_2_cfg_reg[] = + { + {"rci_grade_th_2_cfg", DPP_FIELD_FLAG_RW, 11, 12, 0x465, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_rci_grade_th_3_cfg_reg[] = + { + {"rci_grade_th_3_cfg", DPP_FIELD_FLAG_RW, 11, 12, 0x47e, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_rci_grade_th_4_cfg_reg[] = + { + {"rci_grade_th_4_cfg", DPP_FIELD_FLAG_RW, 11, 12, 0x753, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_rci_grade_th_5_cfg_reg[] = + { + {"rci_grade_th_5_cfg", DPP_FIELD_FLAG_RW, 11, 12, 0x8ca, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_rci_grade_th_6_cfg_reg[] = + { + {"rci_grade_th_6_cfg", DPP_FIELD_FLAG_RW, 11, 12, 0xa41, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_flow_del_cmd_reg[] = + { + {"flow_del_busy", DPP_FIELD_FLAG_RO, 19, 1, 0x0, 0x0}, + {"flow_alt_cmd", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + {"flow_alt_ind", DPP_FIELD_FLAG_RW, 15, 16, 0xffff, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_cnt_clr_reg[] = + { + {"cnt_clr", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_crdt_int_bus_reg[] = + { + {"ldstr_fifo15_ovf_int", DPP_FIELD_FLAG_RO, 31, 1, 0x0, 0x0}, + {"ldstr_fifo14_ovf_int", DPP_FIELD_FLAG_RO, 30, 1, 0x0, 0x0}, + {"ldstr_fifo13_ovf_int", DPP_FIELD_FLAG_RO, 29, 1, 0x0, 0x0}, + {"ldstr_fifo12_ovf_int", DPP_FIELD_FLAG_RO, 28, 1, 0x0, 0x0}, + {"ldstr_fifo11_ovf_int", DPP_FIELD_FLAG_RO, 27, 1, 0x0, 0x0}, + {"ldstr_fifo10_ovf_int", DPP_FIELD_FLAG_RO, 26, 1, 0x0, 0x0}, + {"ldstr_fifo9_ovf_int", DPP_FIELD_FLAG_RO, 25, 1, 0x0, 0x0}, + {"ldstr_fifo8_ovf_int", DPP_FIELD_FLAG_RO, 24, 1, 0x0, 0x0}, + {"ldstr_fifo7_ovf_int", DPP_FIELD_FLAG_RO, 23, 1, 0x0, 0x0}, + {"ldstr_fifo6_ovf_int", DPP_FIELD_FLAG_RO, 22, 1, 0x0, 0x0}, + {"ldstr_fifo5_ovf_int", DPP_FIELD_FLAG_RO, 21, 1, 0x0, 0x0}, + {"ldstr_fifo4_ovf_int", DPP_FIELD_FLAG_RO, 20, 1, 0x0, 0x0}, + {"ldstr_fifo3_ovf_int", DPP_FIELD_FLAG_RO, 19, 1, 0x0, 0x0}, + {"ldstr_fifo2_ovf_int", DPP_FIELD_FLAG_RO, 18, 1, 0x0, 0x0}, + {"ldstr_fifo1_ovf_int", DPP_FIELD_FLAG_RO, 17, 1, 0x0, 0x0}, + {"ldstr_fifo0_ovf_int", DPP_FIELD_FLAG_RO, 16, 1, 0x0, 0x0}, + {"cfg_del_err_int", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0}, + {"flwin_secrs_fifo_ovf_int", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0}, + {"flwin_voqcrs_fifo_ovf_int", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_crdt_int_mask_reg[] = + { + {"crdt_int_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_cfg_weight_together_reg[] = + { + {"cfg_weight_together", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_weight_reg[] = + { + {"c_weight", DPP_FIELD_FLAG_RW, 22, 7, 0x0, 0x0}, + {"e_weight", DPP_FIELD_FLAG_RW, 6, 7, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_dev_sp_state_reg[] = + { + {"dev_sp_state", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_dev_crs_reg[] = + { + {"dev_crs", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_congest_token_disable_31_0_reg[] = + { + {"congest_token_disable_31_0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_congest_token_disable_63_32_reg[] = + { + {"congest_token_disable_63_32", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_crdt_interval_en_cfg_reg[] = + { + {"crdt_interval_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_q_token_staue_cfg_reg[] = + { + {"test_token_q_id", DPP_FIELD_FLAG_RW, 6, 7, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_q_token_dist_cnt_reg[] = + { + {"q_token_dist_counter", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_q_token_dec_cnt_reg[] = + { + {"q_token_dec_counter", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_pp_weight_ram_reg[] = + { + {"pp_c_weight", DPP_FIELD_FLAG_RW, 25, 26, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_pp_cbs_shape_en_ram_reg[] = + { + {"pp_cbs", DPP_FIELD_FLAG_RW, 17, 17, 0x0, 0x0}, + {"pp_c_shap_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_pp_next_pc_q_state_ram_reg[] = + { + {"pp_next_pc", DPP_FIELD_FLAG_RO, 24, 6, 0x0, 0x0}, + {"pp_token_num", DPP_FIELD_FLAG_RO, 18, 18, 0x20000, 0x0}, + {"pp_q_state", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_dev_interval_reg[] = + { + {"dev_interval", DPP_FIELD_FLAG_RW, 21, 22, 0xf, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_dev_wfq_cnt_reg[] = + { + {"dev_wfq_cnt", DPP_FIELD_FLAG_RO, 6, 7, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_dev_wfq_state_reg[] = + { + {"dev_wfq_state", DPP_FIELD_FLAG_RO, 6, 7, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_dev_active_head_ptr_reg[] = + { + {"dev_active_head_ptr", DPP_FIELD_FLAG_RO, 5, 6, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_dev_active_tail_ptr_reg[] = + { + {"dev_active_tail_ptr", DPP_FIELD_FLAG_RO, 5, 6, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_dev_unactive_head_ptr_reg[] = + { + {"dev_unactive_head_ptr", DPP_FIELD_FLAG_RO, 5, 6, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_dev_unactive_tail_ptr_reg[] = + { + {"dev_unactive_tail_ptr", DPP_FIELD_FLAG_RO, 5, 6, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_pp_weight_reg[] = + { + {"pp_weight", DPP_FIELD_FLAG_RW, 6, 7, 0x1, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_pp_que_state_reg[] = + { + {"pp_enque_flag", DPP_FIELD_FLAG_RO, 16, 1, 0x0, 0x0}, + {"pp_cir", DPP_FIELD_FLAG_RO, 15, 2, 0x2, 0x0}, + {"pp_congest_cir", DPP_FIELD_FLAG_RO, 13, 2, 0x0, 0x0}, + {"pp_crs", DPP_FIELD_FLAG_RO, 8, 1, 0x0, 0x0}, + {"dev_sp", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_pp_next_ptr_reg[] = + { + {"pp_next_ptr", DPP_FIELD_FLAG_RO, 5, 6, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_pp_cfg_reg[] = + { + {"pp_cfg", DPP_FIELD_FLAG_RW, 3, 4, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_pp_up_ptr_reg[] = + { + {"pp_up_ptr", DPP_FIELD_FLAG_RO, 5, 6, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_credit_drop_num_reg[] = + { + {"credit_drop_num", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_se_id_lv0_reg[] = + { + {"se_id_out_lv0", DPP_FIELD_FLAG_RO, 17, 18, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_se_id_lv1_reg[] = + { + {"se_id_out_lv1", DPP_FIELD_FLAG_RO, 17, 18, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_se_id_lv2_reg[] = + { + {"se_id_out_lv2", DPP_FIELD_FLAG_RO, 17, 18, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_se_id_lv3_reg[] = + { + {"se_id_out_lv3", DPP_FIELD_FLAG_RO, 17, 18, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_se_id_lv4_reg[] = + { + {"se_id_out_lv4", DPP_FIELD_FLAG_RO, 17, 18, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_que_id_reg[] = + { + {"que_id_out", DPP_FIELD_FLAG_RO, 17, 18, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_se_info_lv0_reg[] = + { + {"se_shape_lv0", DPP_FIELD_FLAG_RO, 25, 2, 0x0, 0x0}, + {"se_ins_out_lv0", DPP_FIELD_FLAG_RO, 23, 8, 0x0, 0x0}, + {"se_state_out_lv0", DPP_FIELD_FLAG_RO, 15, 8, 0x0, 0x0}, + {"se_new_state_out_lv0", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_se_info_lv1_reg[] = + { + {"se_shape_lv1", DPP_FIELD_FLAG_RO, 25, 2, 0x0, 0x0}, + {"se_ins_out_lv1", DPP_FIELD_FLAG_RO, 23, 8, 0x0, 0x0}, + {"se_state_out_lv1", DPP_FIELD_FLAG_RO, 15, 8, 0x0, 0x0}, + {"se_new_state_out_lv1", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_se_info_lv2_reg[] = + { + {"se_shape_lv2", DPP_FIELD_FLAG_RO, 25, 2, 0x0, 0x0}, + {"se_ins_out_lv2", DPP_FIELD_FLAG_RO, 23, 8, 0x0, 0x0}, + {"se_state_out_lv2", DPP_FIELD_FLAG_RO, 15, 8, 0x0, 0x0}, + {"se_new_state_out_lv2", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_se_info_lv3_reg[] = + { + {"se_shape_lv3", DPP_FIELD_FLAG_RO, 25, 2, 0x0, 0x0}, + {"se_ins_out_lv3", DPP_FIELD_FLAG_RO, 23, 8, 0x0, 0x0}, + {"se_state_out_lv3", DPP_FIELD_FLAG_RO, 15, 8, 0x0, 0x0}, + {"se_new_state_out_lv3", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_se_info_lv4_reg[] = + { + {"se_shape_lv4", DPP_FIELD_FLAG_RO, 25, 2, 0x0, 0x0}, + {"se_ins_out_lv4", DPP_FIELD_FLAG_RO, 23, 8, 0x0, 0x0}, + {"se_state_out_lv4", DPP_FIELD_FLAG_RO, 15, 8, 0x0, 0x0}, + {"se_new_state_out_lv4", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_que_state_reg[] = + { + {"que_state_out", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_eir_off_in_advance_reg[] = + { + {"eir_crs_filter", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_double_level_shap_prevent_reg[] = + { + {"double_level_shap_prevent", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_add_store_cycle_reg[] = + { + {"add_store_cycle", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_tflag2_wr_flag_sum_reg[] = + { + {"tflag2_wr_flag_sum", DPP_FIELD_FLAG_RO, 4, 5, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_flowque_para_tbl_reg[] = + { + {"flowque_link", DPP_FIELD_FLAG_RW, 30, 15, 0x7fff, 0x0}, + {"flowque_w", DPP_FIELD_FLAG_RW, 14, 11, 0x0, 0x0}, + {"flowque_pri", DPP_FIELD_FLAG_RW, 3, 4, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_se_para_tbl_reg[] = + { + {"se_insw", DPP_FIELD_FLAG_RW, 33, 1, 0x0, 0x0}, + {"se_link", DPP_FIELD_FLAG_RW, 30, 15, 0x7fff, 0x0}, + {"cp_token_en", DPP_FIELD_FLAG_RW, 15, 1, 0x0, 0x0}, + {"se_w", DPP_FIELD_FLAG_RW, 14, 11, 0x0, 0x0}, + {"se_pri", DPP_FIELD_FLAG_RW, 3, 4, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_flowque_ins_tbl_reg[] = + { + {"flowque_ins", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_se_ins_tbl_reg[] = + { + {"se_ins_flag", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0}, + {"se_ins_priority", DPP_FIELD_FLAG_RO, 2, 3, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_eir_crs_filter_tbl_reg[] = + { + {"eir_crs_filter", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qcfg_qlist_cfg_done_reg[] = + { + {"qcfg_qlist_cfg_done", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qcfg_qsch_credit_value_reg[] = + { + {"qcfg_qsch_credit_value", DPP_FIELD_FLAG_RW, 13, 14, 0x8fc, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qcfg_qsch_crbal_init_value_reg[] = + { + {"qcfg_qsch_crbal_init_value", DPP_FIELD_FLAG_RW, 16, 17, 0xff, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qcfg_qsch_crbal_init_mask_reg[] = + { + {"qcfg_qsch_crbal_init_mask", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cmdsch_rd_cmd_aful_th_reg[] = + { + {"cmdsch_rd_cmd_aful_th", DPP_FIELD_FLAG_RW, 9, 10, 0x80, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_port_fc_interval_reg[] = + { + {"cfg_port_fc_interval", DPP_FIELD_FLAG_RW, 2, 3, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qcfg_csch_aged_cfg_reg[] = + { + {"qcfg_csch_aged_cfg", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qcfg_csch_aged_scan_time_reg[] = + { + {"qcfg_csch_aged_scan_time", DPP_FIELD_FLAG_RW, 31, 32, 0xffff, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qcfg_qmu_qlist_state_query_reg[] = + { + {"pkt_age_req_fifo_afull", DPP_FIELD_FLAG_RO, 27, 1, 0x0, 0x0}, + {"rd_release_fwft_afull", DPP_FIELD_FLAG_RO, 26, 1, 0x0, 0x0}, + {"drop_imem_fwft_afull", DPP_FIELD_FLAG_RO, 25, 1, 0x0, 0x0}, + {"pkt_age_req_fifo_empty", DPP_FIELD_FLAG_RO, 24, 1, 0x1, 0x0}, + {"rd_release_fwft_empty", DPP_FIELD_FLAG_RO, 23, 1, 0x1, 0x0}, + {"drop_imem_fwft_empty", DPP_FIELD_FLAG_RO, 22, 1, 0x1, 0x0}, + {"mmu_qmu_sop_rd_rdy", DPP_FIELD_FLAG_RO, 21, 1, 0x0, 0x0}, + {"big_fifo_empty", DPP_FIELD_FLAG_RO, 20, 1, 0x1, 0x0}, + {"qmu_mmu_rd_release_rdy", DPP_FIELD_FLAG_RO, 19, 1, 0x0, 0x0}, + {"xsw_qmu_crs_rdy", DPP_FIELD_FLAG_RO, 18, 1, 0x0, 0x0}, + {"mmu_qmu_rdy", DPP_FIELD_FLAG_RO, 17, 10, 0x0, 0x0}, + {"mmu_ql_wr_rdy", DPP_FIELD_FLAG_RO, 7, 1, 0x0, 0x0}, + {"mmu_ql_rd_rdy", DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0}, + {"csw_ql_rdy", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0}, + {"ql_init_done", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0}, + {"free_addr_ready", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0}, + {"bank_group_afull", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0}, + {"pds_fwft_empty", DPP_FIELD_FLAG_RO, 1, 1, 0x1, 0x0}, + {"enq_rpt_fwft_afull", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfgmt_qsch_crbal_drop_en_reg[] = + { + {"cfgmt_qsch_all_crbal_drop_en", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0}, + {"cfgmt_qsch_crbal_drop_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfgmt_wlist_qnum_fifo_aful_th_reg[] = + { + {"cfgmt_wlist_qnum_fifo_aful_th", DPP_FIELD_FLAG_RW, 3, 4, 0x4, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qcfg_csw_pkt_blk_mode_reg[] = + { + {"qcfg_csw_pkt_blk_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qcfg_qlist_ram_init_cancel_reg[] = + { + {"qcfg_qlist_ram_init_cancel", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qcfg_qsch_crbal_transfer_mode_reg[] = + { + {"qcfg_qsch_crbal_transfer_mode", DPP_FIELD_FLAG_RW, 16, 1, 0x0, 0x0}, + {"qcfg_qsch_crbal_transfer_value", DPP_FIELD_FLAG_RW, 15, 16, 0x3e8, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qcfg_qlist_qclr_interval_reg[] = + { + {"qcfg_qlist_qclr_interval", DPP_FIELD_FLAG_RW, 31, 32, 0x400, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qcfg_qsch_qclr_rate_reg[] = + { + {"qcfg_qsch_qclr_rate", DPP_FIELD_FLAG_RW, 31, 32, 0xff, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qcfg_qlist_ddr_random_reg[] = + { + {"qcfg_qlist_ddr_random", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfgmt_qlist_pds_fifo_afull_th_reg[] = + { + {"cfgmt_qlist_pds_fifo_afull_th", DPP_FIELD_FLAG_RW, 5, 6, 0xc, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfgmt_sop_cmd_fifo_afull_th_reg[] = + { + {"cfgmt_sop_cmd_fifo_afull_th", DPP_FIELD_FLAG_RW, 7, 8, 0x78, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfgmt_non_sop_cmd_fifo_afull_th_reg[] = + { + {"cfgmt_non_sop_cmd_fifo_afull_th", DPP_FIELD_FLAG_RW, 10, 11, 0x3e8, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfgmt_mmu_data_fifo_afull_th_reg[] = + { + {"cfgmt_mmu_data_fifo_afull_th", DPP_FIELD_FLAG_RW, 9, 10, 0xf0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qcfg_qlist_bank_ept_th_reg[] = + { + {"qcfg_qlist_bank_ept_th", DPP_FIELD_FLAG_RW, 17, 18, 0x3, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_random_bypass_en_reg[] = + { + {"random_bypass_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfgmt_crs_spd_bypass_reg[] = + { + {"cfgmt_crs_spd_bypass", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfgmt_crs_interval_reg[] = + { + {"cfgmt_crs_interval", DPP_FIELD_FLAG_RW, 31, 32, 0x8, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_auto_credit_control_en_reg[] = + { + {"cfg_qsch_auto_credit_control_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_autocrfrstque_reg[] = + { + {"cfg_qsch_autocrfrstque", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_autocrlastque_reg[] = + { + {"cfg_qsch_autocrlastque", DPP_FIELD_FLAG_RW, 15, 16, 0x3ff, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_autocreditrate_reg[] = + { + {"cfg_qsch_autocreditrate", DPP_FIELD_FLAG_RW, 19, 20, 0x20, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_scanfrstque_reg[] = + { + {"cfg_qsch_scanfrstque", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_scanlastque_reg[] = + { + {"cfg_qsch_scanlastque", DPP_FIELD_FLAG_RW, 13, 14, 0x3ff, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_scanrate_reg[] = + { + {"cfg_qsch_scanrate", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_scan_en_reg[] = + { + {"cfg_qsch_scan_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfgmt_qsch_rd_credit_fifo_rate_reg[] = + { + {"cfgmt_qsch_rd_credit_fifo_rate", DPP_FIELD_FLAG_RW, 23, 24, 0xa, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qcfg_qlist_bdep_reg[] = + { + {"qcfg_qlist_bdep", DPP_FIELD_FLAG_RW, 14, 15, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qcfg_qlist_bhead_reg[] = + { + {"bank_vld", DPP_FIELD_FLAG_RW, 16, 1, 0x0, 0x0}, + {"qcfg_qlist_bhead", DPP_FIELD_FLAG_RW, 14, 15, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qcfg_qlist_btail_reg[] = + { + {"qcfg_qlist_btail", DPP_FIELD_FLAG_RW, 14, 15, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qcfg_qsch_shap_param_reg[] = + { + {"qcfg_qsch_shap_en", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, + {"qcfg_qsch_shap_param1", DPP_FIELD_FLAG_RW, 23, 12, 0x0, 0x0}, + {"qcfg_qsch_shap_param2", DPP_FIELD_FLAG_RW, 11, 12, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qcfg_qsch_shap_token_reg[] = + { + {"qcfg_qsch_shap_token", DPP_FIELD_FLAG_RW, 16, 17, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qcfg_qsch_shap_offset_reg[] = + { + {"qcfg_qsch_shap_offset", DPP_FIELD_FLAG_RW, 8, 9, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qcfg_qsch_crs_eir_th_reg[] = + { + {"qcfg_qsch_crs_eir_th", DPP_FIELD_FLAG_RW, 18, 19, 0x80, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qcfg_qsch_crs_th1_reg[] = + { + {"qcfg_qsch_crs_th1", DPP_FIELD_FLAG_RW, 31, 32, 0x57584c4c, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qcfg_qsch_crs_th2_reg[] = + { + {"qcfg_qsch_crs_th2", DPP_FIELD_FLAG_RW, 31, 32, 0x200, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qcfg_csch_congest_th_reg[] = + { + {"qcfg_csch_congest_th", DPP_FIELD_FLAG_RW, 13, 14, 0xc8, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qcfg_csch_sp_fc_th_reg[] = + { + {"qcfg_csch_sp_fc_th", DPP_FIELD_FLAG_RW, 13, 14, 0x12c, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qcfg_csw_shap_parameter_reg[] = + { + {"qcfg_csw_shap_en", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, + {"qcfg_csw_shap_parameter", DPP_FIELD_FLAG_RW, 23, 24, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfgmt_rd_release_aful_th_reg[] = + { + {"cfgmt_rd_release_aful_th", DPP_FIELD_FLAG_RW, 8, 9, 0x80, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfgmt_drop_imem_release_fifo_aful_th_reg[] = + { + {"cfgmt_drop_imem_release_fifo_aful_th", DPP_FIELD_FLAG_RW, 8, 9, 0x80, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfgmt_nnh_rd_buf_aful_th_reg[] = + { + {"cfgmt_nnh_rd_buf_aful_th", DPP_FIELD_FLAG_RW, 5, 6, 0xa, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_pid_use_inall_reg[] = + { + {"cfgmt_nod_rd_buf_0_aful_th", DPP_FIELD_FLAG_RW, 4, 5, 0x3, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_pid_round_th_reg[] = + { + {"cfgmt_nod_rd_buf_1_aful_th", DPP_FIELD_FLAG_RW, 4, 5, 0x4, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfgmt_credit_fifo_afull_th_reg[] = + { + {"cfgmt_credit_fifo_afull_th", DPP_FIELD_FLAG_RW, 5, 6, 0xa, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfgmt_scan_fifo_afull_th_reg[] = + { + {"cfgmt_scan_fifo_afull_th", DPP_FIELD_FLAG_RW, 5, 6, 0xa, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfgmt_small_fifo_aful_th_reg[] = + { + {"cfgmt_small_fifo_aful_th", DPP_FIELD_FLAG_RW, 5, 6, 0x9, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfgmt_free_addr_fifo_aful_th_reg[] = + { + {"cfgmt_free_addr_fifo_aful_th", DPP_FIELD_FLAG_RW, 5, 6, 0x16, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfgmt_enq_rpt_fifo_aful_th_reg[] = + { + {"cfgmt_enq_rpt_fifo_aful_th", DPP_FIELD_FLAG_RW, 9, 10, 0x3e8, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qcfg_csw_shap_token_depth_reg[] = + { + {"qcfg_csw_shap_token_depth", DPP_FIELD_FLAG_RW, 16, 17, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qcfg_csw_shap_offset_value_reg[] = + { + {"qcfg_csw_shap_offset_value", DPP_FIELD_FLAG_RW, 8, 9, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qcfg_csw_fc_offset_value_reg[] = + { + {"qcfg_csw_fc_offset_value", DPP_FIELD_FLAG_RW, 8, 9, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qmu_init_done_state_reg[] = + { + {"csch_qcfg_init_done", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0}, + {"qsch_qcfg_init_done", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0}, + {"qlist_qcfg_init_done", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0}, + {"qcsr_ram_init_done", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_csw_qcfg_port_shap_rdy_0_reg[] = + { + {"csw_qcfg_port_shap_rdy_0", DPP_FIELD_FLAG_RO, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_csw_qcfg_port_shap_rdy_1_reg[] = + { + {"csw_qcfg_port_shap_rdy_1", DPP_FIELD_FLAG_RO, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qlist_cfgmt_ram_init_done_reg[] = + { + {"qlist_qcfg_qds_ram_init_done", DPP_FIELD_FLAG_RO, 7, 1, 0x0, 0x0}, + {"qlist_qcfg_chk_ram_init_done", DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0}, + {"qlist_qcfg_ept_ram_init_done", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0}, + {"qlist_qcfg_cti_ram_init_done", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0}, + {"qlist_qcfg_cto_ram_init_done", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0}, + {"qlist_qcfg_bcnt_ram_init_done", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0}, + {"qlist_qcfg_biu_ram_init_done", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0}, + {"qlist_qcfg_baram_init_done", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qlist_cfgmt_ram_ecc_err_reg[] = + { + {"qds_ram_parity_err", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"qcsr_qnum_fifo_parity_err", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"sa_id_ram_parity_err", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"enq_rpt_fifo_parity_err", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"bcnts_parity_err", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"baram_parity_err_a", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"baram_parity_err_b", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"bcntm_ram_parity_err", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"biu_ram_single_ecc_err", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"chk_ram_single_ecc_err", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"cmd_sch_cmd_ram_single_ecc_err", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"cmd_sch_list_ram_single_ecc_err", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"cmd_sch_hp_ram_single_ecc_err", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"cmd_sch_tp_ram_single_ecc_err", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"cmd_sch_enq_active_ram_single_ecc_err", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"cmd_sch_deq_active_ram_single_ecc_err", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"cmd_sch_empty_ram_single_ecc_err", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"cmd_sch_eop_ram_single_ecc_err", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"cmd_sch_blkcnt_ram_single_ecc_err", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"biu_ram_double_ecc_err", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"chk_ram_double_ecc_err", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"cmd_sch_cmd_ram_double_ecc_err", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"cmd_sch_list_ram_double_ecc_err", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"cmd_sch_hp_ram_double_ecc_err", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"cmd_sch_tp_ram_double_ecc_err", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"cmd_sch_enq_active_ram_double_ecc_err", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"cmd_sch_deq_active_ram_double_ecc_err", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"cmd_sch_empty_ram_double_ecc_err", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"cmd_sch_eop_ram_double_ecc_err", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"cmd_sch_blkcnt_ram_double_ecc_err", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qlist_cfgmt_ram_slot_err_reg[] = + { + {"qds_ram_enq_rd_slot_err", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"qds_ram_deq_rd_slot_err", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"qds_ram_enq_wr_slot_err", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"qds_ram_deq_wr_slot_err", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"chk_ram_enq_rd_slot_err", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"chk_ram_deq_rd_slot_err", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"chk_ram_enq_wr_slot_err", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"chk_ram_deq_wr_slot_err", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"ept_ram_enq_rd_slot_err", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"ept_ram_deq_rd_slot_err", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"ept_ram_enq_wr_slot_err", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"ept_ram_deq_wr_slot_err", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"cti_ram_enq_rd_slot_err", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"cti_ram_deq_rd_slot_err", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"cti_ram_enq_wr_slot_err", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"cti_ram_deq_wr_slot_err", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"cto_ram_enq_rd_slot_err", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"cto_ram_deq_rd_slot_err", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"cto_ram_enq_wr_slot_err", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"cto_ram_deq_wr_slot_err", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qsch_cfgmt_ram_ecc_reg[] = + { + {"crbal_rama_parity_error", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"crbal_ramb_parity_error", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"crs_ram_parity_error", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"wlist_flag_ram_single_ecc_err", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"wlist_next_single_ecc_err", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"wlist_wactive_ram_single_ecc_err", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"wlist_ractive_ram_single_ecc_err", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"wlist_tp1_ram_single_ecc_err", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"wlist_tp2_ram_single_ecc_err", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"wlist_empty1_ram_single_ecc_err_a", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"wlist_empty1_ram_single_ecc_err_b", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"wlist_empty2_ram_single_ecc_err_a", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"wlist_empty2_ram_single_ecc_err_b", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"wlist_hp_ram_single_ecc_err_a", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"wlist_hp_ram_single_ecc_err_b", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"wlist_flag_ram_double_ecc_err", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"wlist_next_double_ecc_err", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"wlist_wactive_ram_double_ecc_err", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"wlist_ractive_ram_double_ecc_err", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"wlist_tp1_ram_double_ecc_err", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"wlist_tp2_ram_double_ecc_err", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"wlist_empty1_ram_double_ecc_err_a", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"wlist_empty1_ram_double_ecc_err_b", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"wlist_empty2_ram_double_ecc_err_a", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"wlist_empty2_ram_double_ecc_err_b", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"wlist_hp_ram_double_ecc_err_a", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"wlist_hp_ram_double_ecc_err_b", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qlist_cfgmt_fifo_state_reg[] = + { + {"pkt_age_req_fifo_overflow", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"pkt_age_req_fifo_underflow", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"qcsr_big_fifo_ovfl", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"qcsr_small_fifo_overflow", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"enq_rpt_fifo_overflow", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"enq_rpt_fifo_underflow", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"pds_fwft_overflow", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"pds_fwft_underflow", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"free_addr_fifo_overflow", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"free_addr_fifo_underflow", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"rd_release_fwft_overflow", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"rd_release_fwft_underflow", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"pid_free_list_overflow", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"pid_free_list_underflow", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"pid_prp_list_overflow", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"pid_prp_list_underflow", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"pid_rdy_list_overflow", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"pid_rdy_list_underflow", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"drop_imem_release_fwft_overflow", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"drop_imem_release_fwft_underflow", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"nnh_rd_buf_fifo_overflow", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"nnh_rd_buf_fifo_underflow", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"nod_rd_buf_0_fifo_overflow", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"nod_rd_buf_0_fifo_underflow", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"nod_rd_buf_1_fifo_overflow", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"nod_rd_buf_1_fifo_underflow", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qlist_qcfg_clr_done_reg[] = + { + {"qlist_qcfg_clr_done", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qmu_int_mask1_reg[] = + { + {"qmu_int_mask1", DPP_FIELD_FLAG_RW, 29, 30, 0x3fffffff, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qmu_int_mask2_reg[] = + { + {"qmu_int_mask2", DPP_FIELD_FLAG_RW, 19, 20, 0xfffff, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qmu_int_mask3_reg[] = + { + {"qmu_int_mask3", DPP_FIELD_FLAG_RW, 26, 27, 0x7ffffff, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qmu_int_mask4_reg[] = + { + {"qmu_int_mask4", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qmu_int_mask5_reg[] = + { + {"qmu_int_mask5", DPP_FIELD_FLAG_RW, 30, 31, 0x7fffffff, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qmu_int_mask6_reg[] = + { + {"qmu_int_mask6", DPP_FIELD_FLAG_RW, 15, 16, 0xffff, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cmd_sch_cfgmt_fifo_state_reg[] = + { + {"nsop_fifo_parity_err", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"cmdsch_rd_cmd_fifo_parity_err", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"sop_fifo_afull", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"sop_fifo_empty", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0}, + {"sop_fifo_overflow", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"sop_fifo_underflow", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"mmu_data_fifo_afull", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"mmu_data_fifo_empty", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0}, + {"mmudat_fifo_overflow", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"mmudat_fifo_underflow", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"non_sop_fifo_afull", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"non_sop_fifo_empty", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0}, + {"nsop_fifo_overflow", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"nsop_fifo_underflow", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"cmdsch_rd_cmd_fifo_afull", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"cmdsch_rd_cmd_fifo_empty", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0}, + {"cmdsch_rd_cmd_fifo_overflow", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"cmdsch_rd_cmd_fifo_underflow", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"wlist_qnum_fifo_overflow", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"wlist_qnum_fifo_underflow", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"qsch_scan_fifo_overflow", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"qsch_scan_fifo_underflow", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"qsch_credit_fifo_overflow", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"qsch_credit_fifo_underflow", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"qsch_credit_fifo2_overflow", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"qsch_credit_fifo2_underflow", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qlist_r_bcnt_reg[] = + { + {"qlist_r_bcnt", DPP_FIELD_FLAG_RO, 21, 22, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qsch_rw_crbal_reg[] = + { + {"qsch_rw_crbal", DPP_FIELD_FLAG_RW, 16, 17, 0xff, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qsch_rw_crs_reg[] = + { + {"qsch_rw_crs", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qsch_r_wlist_empty_reg[] = + { + {"qsch_r_wlist_empty", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qcfg_qlist_baram_rd_reg[] = + { + {"qcfg_qlist_baram_rd", DPP_FIELD_FLAG_RO, 6, 7, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qcfg_qsch_crbal_fb_rw_reg[] = + { + {"qcfg_qlist_crbal_fb_rw", DPP_FIELD_FLAG_RW, 16, 17, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qcfg_qlist_grp0_bank_reg[] = + { + {"qcfg_qlist_grp0_bank_wr", DPP_FIELD_FLAG_RW, 2, 3, 0x1, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qcfg_qlist_grp1_bank_reg[] = + { + {"qcfg_qlist_grp1_bank_wr", DPP_FIELD_FLAG_RW, 2, 3, 0x1, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qcfg_qlist_grp2_bank_reg[] = + { + {"qcfg_qlist_grp2_bank_wr", DPP_FIELD_FLAG_RW, 2, 3, 0x1, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qcfg_qlist_grp3_bank_reg[] = + { + {"qcfg_qlist_grp3_bank_wr", DPP_FIELD_FLAG_RW, 2, 3, 0x1, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qcfg_qlist_grp4_bank_reg[] = + { + {"qcfg_qlist_grp4_bank_wr", DPP_FIELD_FLAG_RW, 2, 3, 0x1, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qcfg_qlist_grp5_bank_reg[] = + { + {"qcfg_qlist_grp5_bank_wr", DPP_FIELD_FLAG_RW, 2, 3, 0x1, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qcfg_qlist_grp6_bank_reg[] = + { + {"qcfg_qlist_grp6_bank_wr", DPP_FIELD_FLAG_RW, 2, 3, 0x1, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qcfg_qlist_grp7_bank_reg[] = + { + {"qcfg_qlist_grp7_bank_wr", DPP_FIELD_FLAG_RW, 2, 3, 0x1, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qcfg_qlist_grp_reg[] = + { + {"qcfg_qlist_grp_wr", DPP_FIELD_FLAG_RW, 2, 3, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfgmt_active_to_bank_cfg_reg[] = + { + {"cfgmt_active_to_bank_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x0, 0x1}, + }; +DPP_FIELD_T g_etm_qmu_cfgmt_ddr_in_mmu_cfg_reg[] = + { + {"cfgmt_ddr_in_mmu_cfg", DPP_FIELD_FLAG_RW, 3, 4, 0x0, 0x1}, + }; +DPP_FIELD_T g_etm_qmu_cfgmt_ddr_in_qmu_cfg_reg[] = + { + {"cfgmt_ddr_in_qmu_cfg", DPP_FIELD_FLAG_RW, 2, 3, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfgmt_bank_to_mmu_cfg_reg[] = + { + {"cfgmt_bank_in_mmu_cfg", DPP_FIELD_FLAG_RW, 2, 3, 0x0, 0x1}, + }; +DPP_FIELD_T g_etm_qmu_cfgmt_bank_to_qmu_cfg_reg[] = + { + {"cfgmt_bank_in_qmu_cfg", DPP_FIELD_FLAG_RW, 2, 3, 0x0, 0x1}, + }; +DPP_FIELD_T g_etm_qmu_cfgmt_grp_ram_n_clr_thd_reg[] = + { + {"cfgmt_grp_ram_n_clr_thd", DPP_FIELD_FLAG_RW, 5, 6, 0x3f, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfgmt_age_pkt_num_reg[] = + { + {"cfgmt_age_pkt_num", DPP_FIELD_FLAG_RW, 3, 4, 0x1, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfgmt_age_multi_interval_reg[] = + { + {"cfgmt_age_multi_interval", DPP_FIELD_FLAG_RW, 15, 16, 0xff, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfgmt_qmu_pkt_age_en_reg[] = + { + {"cfgmt_qmu_pkt_age_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfgmt_qmu_pkt_age_interval_reg[] = + { + {"cfgmt_qmu_pkt_age_interval", DPP_FIELD_FLAG_RW, 31, 32, 0xff, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfgmt_qmu_pkt_age_start_end_reg[] = + { + {"cfgmt_qmu_pkt_age_end", DPP_FIELD_FLAG_RW, 31, 16, 0x23ff, 0x0}, + {"cfgmt_qmu_pkt_age_start", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfgmt_pkt_age_req_aful_th_reg[] = + { + {"cfgmt_pkt_age_req_aful_th", DPP_FIELD_FLAG_RW, 5, 6, 0xa, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfgmt_pkt_age_step_interval_reg[] = + { + {"cfgmt_pkt_age_step_interval", DPP_FIELD_FLAG_RW, 7, 8, 0xff, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfgmt_qmu_imem_age_mode_reg[] = + { + {"cfgmt_qmu_imem_age_en", DPP_FIELD_FLAG_RW, 2, 1, 0x0, 0x0}, + {"cfgmt_qmu_imem_age_qlen_en", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0}, + {"cfgmt_qmu_imem_age_time_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfgmt_qmu_imem_qlen_age_interval_reg[] = + { + {"cfgmt_qmu_imem_qlen_age_interval", DPP_FIELD_FLAG_RW, 15, 16, 0xff, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfgmt_qmu_imem_time_age_interval_reg[] = + { + {"cfgmt_qmu_imem_time_age_interval", DPP_FIELD_FLAG_RW, 31, 32, 0xff, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfgmt_qmu_imem_qlen_age_thd_reg[] = + { + {"cfgmt_qmu_imem_qlen_age_thd", DPP_FIELD_FLAG_RW, 13, 14, 0x1000, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfgmt_imem_age_step_interval_reg[] = + { + {"cfgmt_imem_age_step_interval", DPP_FIELD_FLAG_RW, 7, 8, 0xff, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfgmt_qmu_ecc_bypass_read_reg[] = + { + {"cfgmt_qmu_ecc_bypass_read", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfgmt_qmu_resp_stat_fc_en_reg[] = + { + {"cfgmt_qmu_resp_stat_fc_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfgmt_qmu_bank_xoff_pds_mode_reg[] = + { + {"cfgmt_qmu_bank_xoff_pds_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfgmt_qmu_stat_offset_reg[] = + { + {"cfgmt_qmu_stat_offset", DPP_FIELD_FLAG_RW, 8, 9, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_fc_cnt_mode_reg[] = + { + {"fc_cnt_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_mmu_qmu_wr_fc_cnt_reg[] = + { + {"mmu_qmu_wr_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_mmu_qmu_rd_fc_cnt_reg[] = + { + {"mmu_qmu_rd_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qmu_cgavd_fc_cnt_reg[] = + { + {"qmu_cgavd_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cgavd_qmu_pkt_cnt_reg[] = + { + {"cgavd_qmu_pkt_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cgavd_qmu_pktlen_all_reg[] = + { + {"cgavd_qmu_pktlen_all", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_observe_portfc_spec_reg[] = + { + {"observe_portfc_spec", DPP_FIELD_FLAG_RW, 5, 6, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_spec_lif_portfc_count_reg[] = + { + {"spec_lif_portfc_count", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfgmt_qmu_pfc_en_reg[] = + { + {"cfgmt_qmu_pfc_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfgmt_qmu_pfc_mask_1_reg[] = + { + {"cfgmt_qmu_pfc_mask_1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfgmt_qmu_pfc_mask_2_reg[] = + { + {"cfgmt_qmu_pfc_mask_2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_int_repeat_reg[] = + { + {"int_repeat", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_cfg_dma_dma_up_size_reg[] = + { + {"dma_up_size", DPP_FIELD_FLAG_RW, 9, 10, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_csr_soc_wr_time_out_thresh_reg[] = + { + {"soc_wr_time_out_thresh", DPP_FIELD_FLAG_RW, 31, 32, 0xfa0, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_cfg_shap_param_reg[] = + { + {"shap_en", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, + {"shap_rate", DPP_FIELD_FLAG_RW, 30, 31, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_cfg_shap_token_reg[] = + { + {"cfg_shap_plen_offset", DPP_FIELD_FLAG_RW, 31, 8, 0x00, 0x0}, + {"cfg_shap_token", DPP_FIELD_FLAG_RW, 16, 17, 0xf0, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_idle_ptr_fifo_aful_th_reg[] = + { + {"idle_ptr3_fifo_aful_th", DPP_FIELD_FLAG_RW, 31, 8, 0x5a, 0x0}, + {"idle_ptr2_fifo_aful_th", DPP_FIELD_FLAG_RW, 23, 8, 0x5a, 0x0}, + {"idle_ptr1_fifo_aful_th", DPP_FIELD_FLAG_RW, 15, 8, 0x5a, 0x0}, + {"idle_ptr0_fifo_aful_th", DPP_FIELD_FLAG_RW, 7, 8, 0x5a, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_mr_cos_port_cfg_reg[] = + { + {"cos3_port_cfg", DPP_FIELD_FLAG_RW, 31, 8, 0x3f, 0x0}, + {"cos2_port_cfg", DPP_FIELD_FLAG_RW, 23, 8, 0x3e, 0x0}, + {"cos1_port_cfg", DPP_FIELD_FLAG_RW, 15, 8, 0x3d, 0x0}, + {"cos0_port_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x3c, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_ind_status_reg[] = + { + {"ind_access_done", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_ind_cmd_reg[] = + { + {"ind_rd_or_wr", DPP_FIELD_FLAG_RW, 28, 1, 0x0, 0x0}, + {"ind_mem_id", DPP_FIELD_FLAG_RW, 22, 3, 0x0, 0x0}, + {"ind_mem_addr", DPP_FIELD_FLAG_RW, 11, 12, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_ind_data0_reg[] = + { + {"ind_dat0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_ind_data1_reg[] = + { + {"ind_dat1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_ind_data2_reg[] = + { + {"ind_dat2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_ind_data3_reg[] = + { + {"ind_dat3", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_ind_data4_reg[] = + { + {"ind_dat4", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_ind_data5_reg[] = + { + {"ind_dat5", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_ind_data6_reg[] = + { + {"ind_dat6", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_ind_data7_reg[] = + { + {"ind_dat7", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_tcam_0_cmd_reg[] = + { + {"cfg_vben", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0}, + {"cfg_vbi", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0}, + {"cfg_t_strwc", DPP_FIELD_FLAG_RW, 22, 2, 0x1, 0x0}, + {"tcam0_sm", DPP_FIELD_FLAG_RW, 20, 6, 0x0, 0x0}, + {"tcam0_smen", DPP_FIELD_FLAG_RW, 14, 1, 0x0, 0x0}, + {"tcam0_rm", DPP_FIELD_FLAG_RW, 13, 2, 0x2, 0x0}, + {"tcam0_rmen", DPP_FIELD_FLAG_RW, 11, 1, 0x0, 0x0}, + {"tcam0_enable", DPP_FIELD_FLAG_RW, 10, 1, 0x0, 0x0}, + {"tcam0_flush", DPP_FIELD_FLAG_WO, 9, 1, 0x0, 0x0}, + {"tcam0_unload", DPP_FIELD_FLAG_WO, 8, 1, 0x0, 0x0}, + {"tcam0_unload_addr", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_tcam_1_cmd_reg[] = + { + {"tcam1_sm", DPP_FIELD_FLAG_RW, 20, 6, 0x0, 0x0}, + {"tcam1_smen", DPP_FIELD_FLAG_RW, 14, 1, 0x0, 0x0}, + {"tcam1_rm", DPP_FIELD_FLAG_RW, 13, 2, 0x2, 0x0}, + {"tcam1_rmen", DPP_FIELD_FLAG_RW, 11, 1, 0x0, 0x0}, + {"tcam1_enable", DPP_FIELD_FLAG_RW, 10, 1, 0x0, 0x0}, + {"tcam1_flush", DPP_FIELD_FLAG_WO, 9, 1, 0x0, 0x0}, + {"tcam1_unload", DPP_FIELD_FLAG_WO, 8, 1, 0x0, 0x0}, + {"tcam1_unload_addr", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_port_en_0_reg[] = + { + {"cfg_isch_port_en_0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_port_en_1_reg[] = + { + {"cfg_isch_port_en_1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_port_en_2_reg[] = + { + {"cfg_isch_port_en_2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_port_en_3_reg[] = + { + {"cfg_port_change_en_0", DPP_FIELD_FLAG_RW, 26, 1, 0x0, 0x0}, + {"cfg_port_change_en_1", DPP_FIELD_FLAG_RW, 25, 1, 0x0, 0x0}, + {"cfg_isch_port_en_3", DPP_FIELD_FLAG_RW, 22, 23, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_cfg_port_l2_offset_mode_0_reg[] = + { + {"cfg_port_l2_offset_mode_0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_cfg_port_l2_offset_mode_1_reg[] = + { + {"cfg_port_l2_offset_mode_1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_cfg_port_l2_offset_mode_2_reg[] = + { + {"cfg_port_l2_offset_mode_2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_cfg_port_l2_offset_mode_3_reg[] = + { + {"cfg_port_l2_offset_mode_3", DPP_FIELD_FLAG_RW, 22, 23, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_port_fc_mode_0_reg[] = + { + {"cfg_isch_fc_mode_0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_port_fc_mode_1_reg[] = + { + {"cfg_isch_fc_mode_1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_port_fc_mode_2_reg[] = + { + {"cfg_isch_fc_mode_2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_port_fc_mode_3_reg[] = + { + {"cfg_isch_fc_mode_3", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_port_fc_mode_4_reg[] = + { + {"cfg_isch_fc_mode_4", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_port_fc_mode_5_reg[] = + { + {"cfg_isch_fc_mode_5", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_port_fc_mode_6_reg[] = + { + {"cfg_isch_fc_mode_6", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_port_fc_mode_7_reg[] = + { + {"cfg_pfu_aging_en", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"cfg_isch_aging_en", DPP_FIELD_FLAG_RW, 14, 1, 0x0, 0x0}, + {"cfg_isch_fc_mode_7", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_cfg_isch_aging_th_reg[] = + { + {"cfg_pfu_delay_cycle", DPP_FIELD_FLAG_RW, 31, 16, 0x8000, 0x0}, + {"cfg_isch_aging_th", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_isch_fifo_th_0_reg[] = + { + {"cfg_sch_fifo3_fc_th", DPP_FIELD_FLAG_RW, 29, 6, 0x30, 0x0}, + {"cfg_sch_fifo2_fc_th", DPP_FIELD_FLAG_RW, 21, 6, 0x30, 0x0}, + {"cfg_sch_fifo1_fc_th", DPP_FIELD_FLAG_RW, 13, 6, 0x30, 0x0}, + {"cfg_sch_fifo0_fc_th", DPP_FIELD_FLAG_RW, 5, 6, 0x30, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_isch_cfg_1_reg[] = + { + {"cfg_parser_max_len_en", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0}, + {"cfg_parser_max_len", DPP_FIELD_FLAG_RW, 30, 15, 0x3e80, 0x0}, + {"cfg_parser_min_len_en", DPP_FIELD_FLAG_RW, 15, 1, 0x0, 0x0}, + {"cfg_parser_min_len", DPP_FIELD_FLAG_RW, 14, 7, 0x3c, 0x0}, + {"sp_sch_sel", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_tcam_0_vld_reg[] = + { + {"cfg_tcam0_vld", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_tcam_1_vld_reg[] = + { + {"cfg_tcam1_vld", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_cpu_port_en_mask_reg[] = + { + {"cpu_port_en_mask", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_pktrx_glbal_cfg_0_reg[] = + { + {"pktrx_glbal_cfg_0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_pktrx_glbal_cfg_1_reg[] = + { + {"pktrx_glbal_cfg_1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_pktrx_glbal_cfg_2_reg[] = + { + {"pktrx_glbal_cfg_2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_pktrx_glbal_cfg_3_reg[] = + { + {"pktrx_glbal_cfg_3", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_nppu_start_reg[] = + { + {"nppu_start", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_stat_ind_status_reg[] = + { + {"ind_access_done", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_stat_ind_cmd_reg[] = + { + {"ind_rd_or_wr", DPP_FIELD_FLAG_RW, 28, 1, 0x0, 0x0}, + {"ind_mem_id", DPP_FIELD_FLAG_RW, 22, 3, 0x0, 0x0}, + {"ind_mem_addr", DPP_FIELD_FLAG_RW, 11, 12, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_stat_ind_data0_reg[] = + { + {"ind_dat0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_idma_cfg_debug_cnt_ovfl_mode_reg[] = + { + {"debug_cnt_ovfl_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_idma_stat_ind_status_reg[] = + { + {"ind_access_done", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_idma_stat_ind_cmd_reg[] = + { + {"ind_rd_or_wr", DPP_FIELD_FLAG_RW, 28, 1, 0x0, 0x0}, + {"ind_mem_id", DPP_FIELD_FLAG_RW, 27, 8, 0x0, 0x0}, + {"ind_mem_addr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_idma_stat_ind_data0_reg[] = + { + {"ind_data0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_ind_status_reg[] = + { + {"ind_access_done", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_ind_cmd_reg[] = + { + {"ind_rd_or_wr", DPP_FIELD_FLAG_RW, 28, 1, 0x0, 0x0}, + {"ind_mem_id", DPP_FIELD_FLAG_RW, 27, 8, 0x0, 0x0}, + {"ind_mem_addr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_ind_data0_reg[] = + { + {"ind_data0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_ind_data1_reg[] = + { + {"ind_data1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_ind_data2_reg[] = + { + {"ind_data2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_ind_data3_reg[] = + { + {"ind_data3", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_ind_data4_reg[] = + { + {"ind_data4", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_ind_data5_reg[] = + { + {"ind_data5", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_ind_data6_reg[] = + { + {"ind_data6", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_ind_data7_reg[] = + { + {"ind_data7", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_idma_public_th_reg[] = + { + {"idma_public_th", DPP_FIELD_FLAG_RW, 14, 15, 0x400, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_lif_public_th_reg[] = + { + {"lif_public_th", DPP_FIELD_FLAG_RW, 14, 15, 0x400, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_idma_total_th_reg[] = + { + {"idma_total_th", DPP_FIELD_FLAG_RW, 14, 15, 0x3ffc, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_lif_total_th_reg[] = + { + {"lif_total_th", DPP_FIELD_FLAG_RW, 14, 15, 0x3fa2, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_mc_total_th_reg[] = + { + {"mc_total_th", DPP_FIELD_FLAG_RW, 14, 15, 0x400, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_mc_cos10_th_reg[] = + { + {"mc_cos1_mode", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, + {"mc_cos0_mode", DPP_FIELD_FLAG_RW, 30, 1, 0x0, 0x0}, + {"mc_cos1_th", DPP_FIELD_FLAG_RW, 29, 15, 0x80, 0x0}, + {"mc_cos0_th", DPP_FIELD_FLAG_RW, 14, 15, 0x80, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_mc_cos32_th_reg[] = + { + {"mc_cos3_mode", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, + {"mc_cos2_mode", DPP_FIELD_FLAG_RW, 30, 1, 0x0, 0x0}, + {"mc_cos3_th", DPP_FIELD_FLAG_RW, 29, 15, 0x80, 0x0}, + {"mc_cos2_th", DPP_FIELD_FLAG_RW, 14, 15, 0x80, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_mc_cos54_th_reg[] = + { + {"mc_cos5_mode", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, + {"mc_cos4_mode", DPP_FIELD_FLAG_RW, 30, 1, 0x0, 0x0}, + {"mc_cos5_th", DPP_FIELD_FLAG_RW, 29, 15, 0x80, 0x0}, + {"mc_cos4_th", DPP_FIELD_FLAG_RW, 14, 15, 0x80, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_mc_cos76_th_reg[] = + { + {"mc_cos7_mode", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, + {"mc_cos6_mode", DPP_FIELD_FLAG_RW, 30, 1, 0x0, 0x0}, + {"mc_cos7_th", DPP_FIELD_FLAG_RW, 29, 15, 0x80, 0x0}, + {"mc_cos6_th", DPP_FIELD_FLAG_RW, 14, 15, 0x80, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_debug_cnt_ovfl_mode_reg[] = + { + {"debug_cnt_ovfl_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_se_key_aful_negate_cfg_reg[] = + { + {"se_key_aful_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_sa_flag_reg[] = + { + {"sa_flag", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_stat_ind_data_reg[] = + { + {"ind_data", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_stat_ind_status_reg[] = + { + {"ind_access_done", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_stat_ind_cmd_reg[] = + { + {"ind_rd_or_wr", DPP_FIELD_FLAG_RW, 28, 1, 0x0, 0x0}, + {"ind_mem_id", DPP_FIELD_FLAG_RW, 27, 8, 0x0, 0x0}, + {"ind_mem_addr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_stat_total_cnt_reg[] = + { + {"total_cnt", DPP_FIELD_FLAG_RO, 14, 15, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_stat_idma_pub_cnt_reg[] = + { + {"idma_pub_cnt", DPP_FIELD_FLAG_RO, 14, 15, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_stat_lif_pub_cnt_reg[] = + { + {"lif_pub_cnt", DPP_FIELD_FLAG_RO, 14, 15, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_stat_mc_total_cnt_reg[] = + { + {"mc_total_cnt", DPP_FIELD_FLAG_RO, 14, 15, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_stat_pbu_thram_init_done_reg[] = + { + {"pbu_thram_init_done", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_stat_ifb_fptr_init_done_reg[] = + { + {"ifb_fptr_init_done", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_isu_cfg_weight_normal_uc_reg[] = + { + {"weight_normal_uc", DPP_FIELD_FLAG_RW, 6, 7, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_isu_cfg_fabric_or_saip_reg[] = + { + {"fabric_or_saip", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_isu_stat_ind_status_reg[] = + { + {"ind_access_done", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_isu_stat_ind_cmd_reg[] = + { + {"ind_rd_or_wr", DPP_FIELD_FLAG_RW, 28, 1, 0x0, 0x0}, + {"ind_mem_id", DPP_FIELD_FLAG_RW, 27, 8, 0x0, 0x0}, + {"ind_mem_addr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_isu_stat_ind_dat0_reg[] = + { + {"ind_dat0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_ind_access_done_reg[] = + { + {"ind_access_done", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_ind_command_reg[] = + { + {"ind_rd_or_wr", DPP_FIELD_FLAG_RW, 28, 1, 0x0, 0x0}, + {"ind_mem_id", DPP_FIELD_FLAG_RW, 27, 8, 0x0, 0x0}, + {"ind_mem_addr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_ind_dat0_reg[] = + { + {"ind_dat0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_ind_dat1_reg[] = + { + {"ind_dat1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_fabric_or_saip_reg[] = + { + {"fabric_or_saip", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_max_pkt_len_reg[] = + { + {"max_pkt_len", DPP_FIELD_FLAG_RW, 14, 15, 0x3f00, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_age_en_reg[] = + { + {"age_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_age_mode_reg[] = + { + {"age_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_age_value_time_reg[] = + { + {"age_value_time", DPP_FIELD_FLAG_RW, 31, 32, 0xe4e1c0, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_age_value_room_reg[] = + { + {"age_value_room", DPP_FIELD_FLAG_RW, 31, 32, 0x1e, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_age_out_cnt_reg[] = + { + {"age_out_cnt", DPP_FIELD_FLAG_RW, 6, 7, 0xa, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_token_value_a_reg[] = + { + {"token_value_a", DPP_FIELD_FLAG_RW, 31, 12, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_token_value_b_reg[] = + { + {"token_value_b", DPP_FIELD_FLAG_RW, 31, 12, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_cfg_shap_en_p0_reg[] = + { + {"cfg_shap_en_p0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_cfg_shap_en_p1_reg[] = + { + {"cfg_shap_en_p1", DPP_FIELD_FLAG_RW, 31, 28, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_cfg_shap_en_tm_reg[] = + { + {"cfg_shap_en_tm", DPP_FIELD_FLAG_RW, 31, 2, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_stat_ind_status_reg[] = + { + {"ind_access_done", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_stat_ind_cmd_reg[] = + { + {"ind_rd_or_wr", DPP_FIELD_FLAG_RW, 28, 1, 0x0, 0x0}, + {"ind_mem_id", DPP_FIELD_FLAG_RW, 27, 8, 0x0, 0x0}, + {"ind_mem_addr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_stat_ind_data0_reg[] = + { + {"ind_dat0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_stat_debug_cnt_cfg_reg[] = + { + {"debug_cnt_ovf_mode", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, + {"debug_cnt_rdclr_mode", DPP_FIELD_FLAG_RW, 30, 1, 0x0, 0x0}, + {"user_cnt_value", DPP_FIELD_FLAG_RW, 29, 4, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_bfd_firstchk_th_reg[] = + { + {"bfd_firstchk_th", DPP_FIELD_FLAG_RW, 18, 19, 0xc350, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_memid_0_pbu_fc_idmath_ram_reg[] = + { + {"lif_th_15", DPP_FIELD_FLAG_RW, 164, 15, 0x0, 0x0}, + {"lif_prv_15", DPP_FIELD_FLAG_RW, 149, 15, 0x0, 0x0}, + {"idma_prv_15", DPP_FIELD_FLAG_RW, 134, 15, 0x0, 0x0}, + {"idma_th_cos0_15", DPP_FIELD_FLAG_RW, 119, 15, 0x0, 0x0}, + {"idma_th_cos1_15", DPP_FIELD_FLAG_RW, 104, 15, 0x0, 0x0}, + {"idma_th_cos2_15", DPP_FIELD_FLAG_RW, 89, 15, 0x0, 0x0}, + {"idma_th_cos3_15", DPP_FIELD_FLAG_RW, 74, 15, 0x0, 0x0}, + {"idma_th_cos4_15", DPP_FIELD_FLAG_RW, 59, 15, 0x0, 0x0}, + {"idma_th_cos5_15", DPP_FIELD_FLAG_RW, 44, 15, 0x0, 0x0}, + {"idma_th_cos6_15", DPP_FIELD_FLAG_RW, 29, 15, 0x0, 0x0}, + {"idma_th_cos7_15", DPP_FIELD_FLAG_RW, 14, 15, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_memid_1_pbu_fc_macth_ram_reg[] = + { + {"cos7_th", DPP_FIELD_FLAG_RW, 119, 15, 0x0, 0x0}, + {"cos6_th", DPP_FIELD_FLAG_RW, 104, 15, 0x0, 0x0}, + {"cos5_th", DPP_FIELD_FLAG_RW, 89, 15, 0x0, 0x0}, + {"cos4_th", DPP_FIELD_FLAG_RW, 74, 15, 0x0, 0x0}, + {"cos3_th", DPP_FIELD_FLAG_RW, 59, 15, 0x0, 0x0}, + {"cos2_th", DPP_FIELD_FLAG_RW, 44, 15, 0x0, 0x0}, + {"cos1_th", DPP_FIELD_FLAG_RW, 29, 15, 0x0, 0x0}, + {"cos0_th", DPP_FIELD_FLAG_RW, 14, 15, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_stat_memid_1_all_kind_port_cnt_reg[] = + { + {"peak_port_cnt", DPP_FIELD_FLAG_RO, 29, 15, 0x0, 0x0}, + {"current_port_cnt", DPP_FIELD_FLAG_RO, 14, 15, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_stat_memid_2_ppu_pbu_ifb_req_vld_cnt_reg[] = + { + {"ppu_pbu_ifb_req_vld_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_stat_memid_2_pbu_ppu_ifb_rsp_vld_cnt_reg[] = + { + {"pbu_ppu_ifb_rsp_vld_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_stat_memid_2_odma_pbu_recy_ptr_vld_cnt_reg[] = + { + {"odma_pbu_recy_ptr_vld_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_stat_memid_2_ppu_pbu_mcode_pf_req_cnt_reg[] = + { + {"ppu_pbu_mcode_pf_req_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_stat_memid_2_pbu_ppu_mcode_pf_rsp_cnt_reg[] = + { + {"pbu_ppu_mcode_pf_rsp_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_stat_memid_2_ppu_pbu_logic_pf_req_cnt_reg[] = + { + {"ppu_pbu_logic_pf_req_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_stat_memid_2_pbu_ppu_logic_pf_rsp_cnt_reg[] = + { + {"pbu_ppu_logic_pf_rsp_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_stat_memid_2_ppu_use_ptr_pulse_cnt_reg[] = + { + {"ppu_use_ptr_pulse_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_stat_memid_2_ppu_pbu_wb_vld_cnt_reg[] = + { + {"ppu_pbu_wb_vld_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_stat_memid_2_pbu_ppu_reorder_para_vld_cnt_reg[] = + { + {"pbu_ppu_reorder_para_vld_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_stat_memid_2_se_pbu_dpi_key_vld_cnt_reg[] = + { + {"se_pbu_dpi_key_vld_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_stat_memid_2_pbu_se_dpi_rsp_datvld_cnt_reg[] = + { + {"pbu_se_dpi_rsp_datvld_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_stat_memid_2_odma_pbu_ifb_rd1_cnt_reg[] = + { + {"odma_pbu_ifb_rd1_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_stat_memid_2_odma_pbu_ifb_rd2_cnt_reg[] = + { + {"odma_pbu_ifb_rd2_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_stat_memid_2_pbu_ppu_mcode_pf_no_rsp_cnt_reg[] = + { + {"pbu_ppu_mcode_pf_no_rsp_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_stat_memid_2_pbu_ppu_logic_pf_no_rsp_cnt_reg[] = + { + {"pbu_ppu_logic_pf_no_rsp_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_stat_memid_3_cpu_rd_ifb_data_reg[] = + { + {"cpu_rd_ifb_data", DPP_FIELD_FLAG_RO, 2047, 2048, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_stat_memid_4_mux_sel_rgt_reg[] = + { + {"current_port_cnt", DPP_FIELD_FLAG_RW, 3, 4, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_stat_memid_5_port_pub_cnt_reg[] = + { + {"port_pub_cnt", DPP_FIELD_FLAG_RO, 14, 15, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_idma_stat_memid_1_idma_o_isu_pkt_pulse_total_cnt_reg[] = + { + {"idma_o_isu_pkt_pulse_total_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_idma_stat_memid_1_idma_o_isu_epkt_pulse_total_cnt_reg[] = + { + {"idma_o_isu_epkt_pulse_total_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_idma_stat_memid_1_idma_dispkt_pulse_total_cnt_reg[] = + { + {"idma_dispkt_pulse_total_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_idma_stat_memid_0_idma_o_isu_pkt_pulse_cnt_reg[] = + { + {"idma_o_isu_pkt_pulse_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_idma_stat_memid_0_idma_o_isu_epkt_pulse_cnt_reg[] = + { + {"idma_o_isu_epkt_pulse_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_idma_stat_memid_0_idma_dispkt_pulse_cnt_reg[] = + { + {"idma_dispkt_pulse_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_test_r_reg[] = + { + {"test_r", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_debug_en_r_reg[] = + { + {"debug_en_r", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_csr_dup_table_wr_data_reg[] = + { + {"item_vld", DPP_FIELD_FLAG_RW, 24, 1, 0x0, 0x0}, + {"flownum_vld", DPP_FIELD_FLAG_RW, 23, 1, 0x0, 0x0}, + {"start_pc", DPP_FIELD_FLAG_RW, 22, 15, 0x0, 0x0}, + {"flownum", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_csr_dup_table_rd_data_reg[] = + { + {"item_vld", DPP_FIELD_FLAG_RO, 24, 1, 0x0, 0x0}, + {"flownum_vld", DPP_FIELD_FLAG_RO, 23, 1, 0x0, 0x0}, + {"start_pc", DPP_FIELD_FLAG_RO, 22, 15, 0x0, 0x0}, + {"flownum", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_csr_dup_table_addr_reg[] = + { + {"csr_dup_table_operation", DPP_FIELD_FLAG_WO, 6, 1, 0x0, 0x0}, + {"csr_dup_table_addr", DPP_FIELD_FLAG_WO, 5, 6, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_debug_vld_reg[] = + { + {"ppu_debug_vld", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_cop_thash_rsk_319_288_reg[] = + { + {"rsk_319_288", DPP_FIELD_FLAG_RW, 31, 32, 0x6d5a56da, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_cop_thash_rsk_287_256_reg[] = + { + {"rsk_287_256", DPP_FIELD_FLAG_RW, 31, 32, 0x255b0ec2, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_cop_thash_rsk_255_224_reg[] = + { + {"rsk_255_224", DPP_FIELD_FLAG_RW, 31, 32, 0x4167253d, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_cop_thash_rsk_223_192_reg[] = + { + {"rsk_223_192", DPP_FIELD_FLAG_RW, 31, 32, 0x43a38fb0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_cop_thash_rsk_191_160_reg[] = + { + {"rsk_191_160", DPP_FIELD_FLAG_RW, 31, 32, 0xd0ca2bcb, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_cop_thash_rsk_159_128_reg[] = + { + {"rsk_159_128", DPP_FIELD_FLAG_RW, 31, 32, 0xae7b30b4, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_cop_thash_rsk_127_096_reg[] = + { + {"rsk_127_096", DPP_FIELD_FLAG_RW, 31, 32, 0x77cb2da3, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_cop_thash_rsk_095_064_reg[] = + { + {"rsk_095_064", DPP_FIELD_FLAG_RW, 31, 32, 0x8030f20c, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_cop_thash_rsk_063_032_reg[] = + { + {"rsk_063_032", DPP_FIELD_FLAG_RW, 31, 32, 0x6a42b73b, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_cop_thash_rsk_031_000_reg[] = + { + {"rsk_031_000", DPP_FIELD_FLAG_RW, 31, 32, 0xbeac01fa, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_cfg_ipv4_ipid_start_value_reg[] = + { + {"cfg_ipv4_ipid_start_value", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_cfg_ipv4_ipid_end_value_reg[] = + { + {"cfg_ipv4_ipid_end_value", DPP_FIELD_FLAG_RW, 15, 16, 0xffff, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_cluster_mf_in_en_reg[] = + { + {"cluster_mf_in_en", DPP_FIELD_FLAG_RW, 5, 6, 0x3f, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_empty_reg[] = + { + {"ppu_empty", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_instrmem_w_addr_reg[] = + { + {"instrmem_w_addr", DPP_FIELD_FLAG_WO, 12, 13, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_instrmem_w_data_191_160_reg[] = + { + {"instrmem_w_data_191_160", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_instrmem_w_data_159_128_reg[] = + { + {"instrmem_w_data_159_128", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_instrmem_w_data_127_96_reg[] = + { + {"instrmem_w_data_127_96", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_instrmem_w_data_95_64_reg[] = + { + {"instrmem_w_data_95_64", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_instrmem_w_data_63_32_reg[] = + { + {"instrmem_w_data_63_32", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_instrmem_w_data_31_0_reg[] = + { + {"instrmem_w_data_31_0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_isu_fwft_mf_fifo_prog_full_assert_cfg_reg[] = + { + {"isu_fwft_mf_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x1e, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_isu_fwft_mf_fifo_prog_full_negate_cfg_reg[] = + { + {"isu_fwft_mf_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x1e, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_int_1200m_mask_reg[] = + { + {"me7_interrupt_mask", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"me6_interrupt_mask", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"me5_interrupt_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"me4_interrupt_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"me3_interrupt_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"me2_interrupt_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"me1_interrupt_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"me0_interrupt_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_ppu4k_cluster_wr_high_data_r_mex_reg[] = + { + {"wr_high_data_r_mex", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu4k_cluster_wr_low_data_r_mex_reg[] = + { + {"wr_low_data_r_mex", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu4k_cluster_addr_r_mex_reg[] = + { + {"operate_type", DPP_FIELD_FLAG_WO, 8, 1, 0x0, 0x0}, + {"addr_r_mex", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu4k_cluster_sdt_tbl_ind_access_done_reg[] = + { + {"rd_addr_r_mex", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu4k_cluster_rd_high_data_r_mex_reg[] = + { + {"rd_high_data_r_mex", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu4k_cluster_rd_low_data_r_mex_reg[] = + { + {"rd_low_data_r_mex", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_init_ok_reg[] = + { + {"init_ok", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_cpu_rd_rdy_reg[] = + { + {"cpu_rd_rdy", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_cpu_rd_data_tmp0_reg[] = + { + {"cpu_rd_data_tmp0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_cpu_rd_data_tmp1_reg[] = + { + {"cpu_rd_data_tmp1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_cpu_rd_data_tmp2_reg[] = + { + {"cpu_rd_data_tmp2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_cpu_rd_data_tmp3_reg[] = + { + {"cpu_rd_data_tmp3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_cpu_rd_data_tmp4_reg[] = + { + {"cpu_rd_data_tmp4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_cpu_rd_data_tmp5_reg[] = + { + {"cpu_rd_data_tmp5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_cpu_rd_data_tmp6_reg[] = + { + {"cpu_rd_data_tmp6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_cpu_rd_data_tmp7_reg[] = + { + {"cpu_rd_data_tmp7", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_cpu_rd_data_tmp8_reg[] = + { + {"cpu_rd_data_tmp8", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_cpu_rd_data_tmp9_reg[] = + { + {"cpu_rd_data_tmp9", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_cpu_rd_data_tmp10_reg[] = + { + {"cpu_rd_data_tmp10", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_cpu_rd_data_tmp11_reg[] = + { + {"cpu_rd_data_tmp11", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_cpu_rd_data_tmp12_reg[] = + { + {"cpu_rd_data_tmp12", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_cpu_rd_data_tmp13_reg[] = + { + {"cpu_rd_data_tmp13", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_cpu_rd_data_tmp14_reg[] = + { + {"cpu_rd_data_tmp14", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_cpu_rd_data_tmp15_reg[] = + { + {"cpu_rd_data_tmp15", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_lpm_v4_config_rgt_reg[] = + { + {"lpm_v4_shift_sel", DPP_FIELD_FLAG_RW, 4, 2, 0x0, 0x0}, + {"lpm_v4_sram_cmp_flag", DPP_FIELD_FLAG_RW, 2, 1, 0x0, 0x0}, + {"lpm_v4_ddr3_addr_sel", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_lpm_v6_config_rgt_reg[] = + { + {"lpm_v6_shift_sel", DPP_FIELD_FLAG_RW, 5, 2, 0x0, 0x0}, + {"lpm_v6_sram_cmp_flag", DPP_FIELD_FLAG_RW, 3, 1, 0x0, 0x0}, + {"lpm_v6_ddr3_addr_sel", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_lpm_ext_rsp_fifo_u0_pfull_ast_reg[] = + { + {"lpm_ext_rsp_fifo_u0_pfull_ast", DPP_FIELD_FLAG_RW, 6, 7, 0x24, 0x0}, + }; +DPP_FIELD_T g_se_as_hash_age_pat_cfg_reg[] = + { + {"hash_age_pat_cfg", DPP_FIELD_FLAG_RW, 3, 4, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_as_learn_rdy_cfg_reg[] = + { + {"learn_rdy_cfg", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_kschd_kschd_as_pful_cfg_reg[] = + { + {"kschd_as_pful_cfg", DPP_FIELD_FLAG_RW, 13, 14, 0x1326, 0x0}, + }; +DPP_FIELD_T g_se_kschd_kschd_dir_pful_cfg_reg[] = + { + {"kschd_dir_pful_cfg", DPP_FIELD_FLAG_RW, 13, 14, 0x1326, 0x0}, + }; +DPP_FIELD_T g_se_kschd_kschd_as_ept_cfg_reg[] = + { + {"kschd_as_ept_cfg", DPP_FIELD_FLAG_RW, 13, 14, 0xc18, 0x0}, + }; +DPP_FIELD_T g_se_kschd_cpu_arbi_pful_cfg_reg[] = + { + {"cpu_arbi_pful_cfg", DPP_FIELD_FLAG_RW, 13, 14, 0x1326, 0x0}, + }; +DPP_FIELD_T g_se_kschd_kschd_pbu_pful_cfg_reg[] = + { + {"kschd_pbu_pful_cfg", DPP_FIELD_FLAG_RW, 13, 14, 0x1326, 0x0}, + }; +DPP_FIELD_T g_se_rschd_rschd_dir_pful_cfg_reg[] = + { + {"rschd_dir_pful_cfg", DPP_FIELD_FLAG_RW, 31, 32, 0x00360036, 0x0}, + }; +DPP_FIELD_T g_se_rschd_rschd_dir_ept_cfg_reg[] = + { + {"rschd_dir_ept_cfg", DPP_FIELD_FLAG_RW, 31, 32, 0x000a000a, 0x0}, + }; +DPP_FIELD_T g_se4k_se_alg_cpu_cmd_rgt_reg[] = + { + {"rd_flag", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, + {"mask", DPP_FIELD_FLAG_RW, 20, 4, 0x0, 0x0}, + {"reg_sram_flag", DPP_FIELD_FLAG_RW, 16, 1, 0x0, 0x0}, + {"zgroup_id", DPP_FIELD_FLAG_RW, 15, 2, 0x0, 0x0}, + {"zblock_id", DPP_FIELD_FLAG_RW, 13, 3, 0x0, 0x0}, + {"zcell_id", DPP_FIELD_FLAG_RW, 10, 2, 0x0, 0x0}, + {"addr", DPP_FIELD_FLAG_RW, 8, 9, 0x0, 0x0}, + }; +DPP_FIELD_T g_se4k_se_alg_cpu_wr_data_tmp0_reg[] = + { + {"cpu_wr_data_tmp0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se4k_se_alg_cpu_wr_data_tmp1_reg[] = + { + {"cpu_wr_data_tmp1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se4k_se_alg_cpu_wr_data_tmp2_reg[] = + { + {"cpu_wr_data_tmp2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se4k_se_alg_cpu_wr_data_tmp3_reg[] = + { + {"cpu_wr_data_tmp3", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se4k_se_alg_cpu_wr_data_tmp4_reg[] = + { + {"cpu_wr_data_tmp4", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se4k_se_alg_cpu_wr_data_tmp5_reg[] = + { + {"cpu_wr_data_tmp5", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se4k_se_alg_cpu_wr_data_tmp6_reg[] = + { + {"cpu_wr_data_tmp6", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se4k_se_alg_cpu_wr_data_tmp7_reg[] = + { + {"cpu_wr_data_tmp7", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se4k_se_alg_cpu_wr_data_tmp8_reg[] = + { + {"cpu_wr_data_tmp8", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se4k_se_alg_cpu_wr_data_tmp9_reg[] = + { + {"cpu_wr_data_tmp9", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se4k_se_alg_cpu_wr_data_tmp10_reg[] = + { + {"cpu_wr_data_tmp10", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se4k_se_alg_cpu_wr_data_tmp11_reg[] = + { + {"cpu_wr_data_tmp11", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se4k_se_alg_cpu_wr_data_tmp12_reg[] = + { + {"cpu_wr_data_tmp12", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se4k_se_alg_cpu_wr_data_tmp13_reg[] = + { + {"cpu_wr_data_tmp13", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se4k_se_alg_cpu_wr_data_tmp14_reg[] = + { + {"cpu_wr_data_tmp14", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se4k_se_alg_cpu_wr_data_tmp15_reg[] = + { + {"cpu_wr_data_tmp15", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se4k_se_alg_cpu_rd_rdy_reg[] = + { + {"cpu_rd_rdy", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_se4k_se_alg_cpu_rd_data_tmp0_reg[] = + { + {"cpu_rd_data_tmp0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se4k_se_alg_cpu_rd_data_tmp1_reg[] = + { + {"cpu_rd_data_tmp1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se4k_se_alg_cpu_rd_data_tmp2_reg[] = + { + {"cpu_rd_data_tmp2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se4k_se_alg_cpu_rd_data_tmp3_reg[] = + { + {"cpu_rd_data_tmp3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se4k_se_alg_cpu_rd_data_tmp4_reg[] = + { + {"cpu_rd_data_tmp4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se4k_se_alg_cpu_rd_data_tmp5_reg[] = + { + {"cpu_rd_data_tmp5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se4k_se_alg_cpu_rd_data_tmp6_reg[] = + { + {"cpu_rd_data_tmp6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se4k_se_alg_cpu_rd_data_tmp7_reg[] = + { + {"cpu_rd_data_tmp7", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se4k_se_alg_cpu_rd_data_tmp8_reg[] = + { + {"cpu_rd_data_tmp8", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se4k_se_alg_cpu_rd_data_tmp9_reg[] = + { + {"cpu_rd_data_tmp9", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se4k_se_alg_cpu_rd_data_tmp10_reg[] = + { + {"cpu_rd_data_tmp10", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se4k_se_alg_cpu_rd_data_tmp11_reg[] = + { + {"cpu_rd_data_tmp11", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se4k_se_alg_cpu_rd_data_tmp12_reg[] = + { + {"cpu_rd_data_tmp12", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se4k_se_alg_cpu_rd_data_tmp13_reg[] = + { + {"cpu_rd_data_tmp13", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se4k_se_alg_cpu_rd_data_tmp14_reg[] = + { + {"cpu_rd_data_tmp14", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se4k_se_alg_cpu_rd_data_tmp15_reg[] = + { + {"cpu_rd_data_tmp15", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se4k_se_alg_hash0_ext_cfg_rgt_reg[] = + { + {"hash0_ext_mode", DPP_FIELD_FLAG_RW, 8, 8, 0x0, 0x0}, + {"hash0_ext_flag", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_se4k_se_alg_hash1_ext_cfg_rgt_reg[] = + { + {"hash1_ext_mode", DPP_FIELD_FLAG_RW, 8, 8, 0x0, 0x0}, + {"hash1_ext_flag", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_se4k_se_alg_hash2_ext_cfg_rgt_reg[] = + { + {"hash2_ext_mode", DPP_FIELD_FLAG_RW, 8, 8, 0x0, 0x0}, + {"hash2_ext_flag", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_se4k_se_alg_hash3_ext_cfg_rgt_reg[] = + { + {"hash3_ext_mode", DPP_FIELD_FLAG_RW, 8, 8, 0x0, 0x0}, + {"hash3_ext_flag", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_se4k_se_alg_hash0_tbl30_depth_reg[] = + { + {"hash0_tbl3_depth", DPP_FIELD_FLAG_RW, 31, 8, 0x12, 0x0}, + {"hash0_tbl2_depth", DPP_FIELD_FLAG_RW, 23, 8, 0x12, 0x0}, + {"hash0_tbl1_depth", DPP_FIELD_FLAG_RW, 15, 8, 0x12, 0x0}, + {"hash0_tbl0_depth", DPP_FIELD_FLAG_RW, 7, 8, 0x12, 0x0}, + }; +DPP_FIELD_T g_se4k_se_alg_hash0_tbl74_depth_reg[] = + { + {"hash0_tbl7_depth", DPP_FIELD_FLAG_RW, 31, 8, 0x12, 0x0}, + {"hash0_tbl6_depth", DPP_FIELD_FLAG_RW, 23, 8, 0x12, 0x0}, + {"hash0_tbl5_depth", DPP_FIELD_FLAG_RW, 15, 8, 0x12, 0x0}, + {"hash0_tbl4_depth", DPP_FIELD_FLAG_RW, 7, 8, 0x12, 0x0}, + }; +DPP_FIELD_T g_se4k_se_alg_hash1_tbl30_depth_reg[] = + { + {"hash1_tbl3_depth", DPP_FIELD_FLAG_RW, 31, 8, 0x12, 0x0}, + {"hash1_tbl2_depth", DPP_FIELD_FLAG_RW, 23, 8, 0x12, 0x0}, + {"hash1_tbl1_depth", DPP_FIELD_FLAG_RW, 15, 8, 0x12, 0x0}, + {"hash1_tbl0_depth", DPP_FIELD_FLAG_RW, 7, 8, 0x12, 0x0}, + }; +DPP_FIELD_T g_se4k_se_alg_hash1_tbl74_depth_reg[] = + { + {"hash1_tbl7_depth", DPP_FIELD_FLAG_RW, 31, 8, 0x12, 0x0}, + {"hash1_tbl6_depth", DPP_FIELD_FLAG_RW, 23, 8, 0x12, 0x0}, + {"hash1_tbl5_depth", DPP_FIELD_FLAG_RW, 15, 8, 0x12, 0x0}, + {"hash1_tbl4_depth", DPP_FIELD_FLAG_RW, 7, 8, 0x12, 0x0}, + }; +DPP_FIELD_T g_se4k_se_alg_hash2_tbl30_depth_reg[] = + { + {"hash2_tbl3_depth", DPP_FIELD_FLAG_RW, 31, 8, 0x12, 0x0}, + {"hash2_tbl2_depth", DPP_FIELD_FLAG_RW, 23, 8, 0x12, 0x0}, + {"hash2_tbl1_depth", DPP_FIELD_FLAG_RW, 15, 8, 0x12, 0x0}, + {"hash2_tbl0_depth", DPP_FIELD_FLAG_RW, 7, 8, 0x12, 0x0}, + }; +DPP_FIELD_T g_se4k_se_alg_hash2_tbl74_depth_reg[] = + { + {"hash2_tbl7_depth", DPP_FIELD_FLAG_RW, 31, 8, 0x12, 0x0}, + {"hash2_tbl6_depth", DPP_FIELD_FLAG_RW, 23, 8, 0x12, 0x0}, + {"hash2_tbl5_depth", DPP_FIELD_FLAG_RW, 15, 8, 0x12, 0x0}, + {"hash2_tbl4_depth", DPP_FIELD_FLAG_RW, 7, 8, 0x12, 0x0}, + }; +DPP_FIELD_T g_se4k_se_alg_hash3_tbl30_depth_reg[] = + { + {"hash3_tbl3_depth", DPP_FIELD_FLAG_RW, 31, 8, 0x12, 0x0}, + {"hash3_tbl2_depth", DPP_FIELD_FLAG_RW, 23, 8, 0x12, 0x0}, + {"hash3_tbl1_depth", DPP_FIELD_FLAG_RW, 15, 8, 0x12, 0x0}, + {"hash3_tbl0_depth", DPP_FIELD_FLAG_RW, 7, 8, 0x12, 0x0}, + }; +DPP_FIELD_T g_se4k_se_alg_hash3_tbl74_depth_reg[] = + { + {"hash3_tbl7_depth", DPP_FIELD_FLAG_RW, 31, 8, 0x12, 0x0}, + {"hash3_tbl6_depth", DPP_FIELD_FLAG_RW, 23, 8, 0x12, 0x0}, + {"hash3_tbl5_depth", DPP_FIELD_FLAG_RW, 15, 8, 0x12, 0x0}, + {"hash3_tbl4_depth", DPP_FIELD_FLAG_RW, 7, 8, 0x12, 0x0}, + }; +DPP_FIELD_T g_se4k_se_alg_wr_rsp_cfg_reg[] = + { + {"wr_rsp_fifo_cfg", DPP_FIELD_FLAG_RW, 9, 10, 0x18c, 0x0}, + }; +DPP_FIELD_T g_se4k_se_alg_hash_mono_flag_reg[] = + { + {"hash3_mono_flag", DPP_FIELD_FLAG_RW, 31, 8, 0x0, 0x0}, + {"hash2_mono_flag", DPP_FIELD_FLAG_RW, 23, 8, 0x0, 0x0}, + {"hash1_mono_flag", DPP_FIELD_FLAG_RW, 15, 8, 0x0, 0x0}, + {"hash0_mono_flag", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0}, + }; +DPP_FIELD_T g_se4k_se_alg_hash10_ext_crc_cfg_reg[] = + { + {"hash1_crc_cfg", DPP_FIELD_FLAG_RW, 31, 16, 0x5555, 0x0}, + {"hash0_crc_cfg", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_se4k_se_alg_hash32_ext_crc_cfg_reg[] = + { + {"hash3_crc_cfg", DPP_FIELD_FLAG_RW, 31, 16, 0xffff, 0x0}, + {"hash2_crc_cfg", DPP_FIELD_FLAG_RW, 15, 16, 0xaaaa, 0x0}, + }; +DPP_FIELD_T g_se4k_se_alg_zblock_service_configure_reg[] = + { + {"service_sel", DPP_FIELD_FLAG_RW, 3, 1, 0x0, 0x0}, + {"hash_channel_sel", DPP_FIELD_FLAG_RW, 2, 2, 0x0, 0x0}, + {"st_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_se4k_se_alg_zblock_hash_zcell_mono_reg[] = + { + {"ha_zcell3_mono_flag", DPP_FIELD_FLAG_RW, 27, 1, 0x0, 0x0}, + {"ha_zcell3_tbl_id", DPP_FIELD_FLAG_RW, 26, 3, 0x0, 0x0}, + {"ha_zcell2_mono_flag", DPP_FIELD_FLAG_RW, 19, 1, 0x0, 0x0}, + {"ha_zcell2_tbl_id", DPP_FIELD_FLAG_RW, 18, 3, 0x0, 0x0}, + {"ha_zcell1_mono_flag", DPP_FIELD_FLAG_RW, 11, 1, 0x0, 0x0}, + {"ha_zcell1_tbl_id", DPP_FIELD_FLAG_RW, 10, 3, 0x0, 0x0}, + {"ha_zcell0_mono_flag", DPP_FIELD_FLAG_RW, 3, 1, 0x0, 0x0}, + {"ha_zcell0_tbl_id", DPP_FIELD_FLAG_RW, 2, 3, 0x0, 0x0}, + }; +DPP_FIELD_T g_se4k_se_alg_zlock_hash_zreg_mono_reg[] = + { + {"ha_zreg3_mono_flag", DPP_FIELD_FLAG_RW, 27, 1, 0x0, 0x0}, + {"ha_zreg3_tbl_id", DPP_FIELD_FLAG_RW, 26, 3, 0x0, 0x0}, + {"ha_zreg2_mono_flag", DPP_FIELD_FLAG_RW, 19, 1, 0x0, 0x0}, + {"ha_zreg2_tbl_id", DPP_FIELD_FLAG_RW, 18, 3, 0x0, 0x0}, + {"ha_zreg1_mono_flag", DPP_FIELD_FLAG_RW, 11, 1, 0x0, 0x0}, + {"ha_zreg1_tbl_id", DPP_FIELD_FLAG_RW, 10, 3, 0x0, 0x0}, + {"ha_zreg0_mono_flag", DPP_FIELD_FLAG_RW, 3, 1, 0x0, 0x0}, + {"ha_zreg0_tbl_id", DPP_FIELD_FLAG_RW, 2, 3, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_init_done_reg[] = + { + {"init_done", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_cpu_ind_wdat0_reg[] = + { + {"cpu_ind_wdat0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_cpu_ind_wdat1_reg[] = + { + {"cpu_ind_wdat1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_cpu_ind_wdat2_reg[] = + { + {"cpu_ind_wdat2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_cpu_ind_wdat3_reg[] = + { + {"cpu_ind_wdat3", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_cpu_ind_cmd_reg[] = + { + {"cpu_ind_rw", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, + {"cpu_ind_rd_mode", DPP_FIELD_FLAG_RW, 30, 1, 0x0, 0x0}, + {"cpu_req_mode", DPP_FIELD_FLAG_RW, 27, 2, 0x0, 0x0}, + {"cpu_ind_addr", DPP_FIELD_FLAG_RW, 25, 26, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_cpu_ind_rd_done_reg[] = + { + {"cpu_ind_rd_done", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_cpu_ind_rdat0_reg[] = + { + {"cpu_ind_rdat0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_cpu_ind_rdat1_reg[] = + { + {"cpu_ind_rdat1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_cpu_ind_rdat2_reg[] = + { + {"cpu_ind_rdat2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_cpu_ind_rdat3_reg[] = + { + {"cpu_ind_rdat3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_cfg_plcr_mono_reg[] = + { + {"cfg_plcr_mono", DPP_FIELD_FLAG_RW, 1, 2, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_wr_arb_cpu_rdy_reg[] = + { + {"wr_arb_cpu_rdy", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_tm_stat_en_cfg_reg[] = + { + {"tm_stat_en_cfg", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_ddr_wdat0_reg[] = + { + {"ddr_wdat0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_dir_arbi_ser_rpful_reg[] = + { + {"dir_arbi_ser_rpful", DPP_FIELD_FLAG_RW, 9, 10, 0x14a, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_cfg_wr_arbi_pful2_reg[] = + { + {"hash_wr_pful", DPP_FIELD_FLAG_RW, 19, 10, 0x14a, 0x0}, + {"dir_wr_pful", DPP_FIELD_FLAG_RW, 9, 10, 0x14a, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_etm_tbl_cfg_reg[] = + { + {"etm_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_cfg_cash_addr_pful_reg[] = + { + {"cfg_cash_addr_pful", DPP_FIELD_FLAG_RW, 19, 20, 0x7e1f8, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_ctrl_rfifo_cfg_reg[] = + { + {"brst_fwft_fifo_prog_empty_assert", DPP_FIELD_FLAG_RW, 31, 10, 0x2, 0x0}, + {"brst_fwft_fifo_prog_empty_negate", DPP_FIELD_FLAG_RW, 21, 10, 0x2, 0x0}, + {"brst_fwft_fifo_prog_full_assert", DPP_FIELD_FLAG_RW, 11, 6, 0x18, 0x0}, + {"brst_fwft_fifo_prog_full_negate", DPP_FIELD_FLAG_RW, 5, 6, 0x18, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_cache_req_fifo_cfg_reg[] = + { + {"srch_fifo_pfull_assert", DPP_FIELD_FLAG_RW, 9, 5, 0xc, 0x0}, + {"srch_fifo_pfull_negate", DPP_FIELD_FLAG_RW, 4, 5, 0xc, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_cpu_ind_eram_wdat0_reg[] = + { + {"cpu_ind_eram_wdat0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_etm_port_sel_cfg_reg[] = + { + {"etm_port0_sel_cfg", DPP_FIELD_FLAG_RW, 19, 5, 0x0, 0x0}, + {"etm_port1_sel_cfg", DPP_FIELD_FLAG_RW, 14, 5, 0x1, 0x0}, + {"etm_port2_sel_cfg", DPP_FIELD_FLAG_RW, 9, 5, 0xf, 0x0}, + {"etm_port3_sel_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x10, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_tm_stat_cfg_reg[] = + { + {"stat_overflow_mode", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"tm_stat_mode_cfg", DPP_FIELD_FLAG_RW, 6, 3, 0x4, 0x0}, + {"tm_flow_control_cfg", DPP_FIELD_FLAG_RW, 3, 4, 0xf, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_ppu_eram_depth_reg[] = + { + {"ppu_eram_depth", DPP_FIELD_FLAG_RW, 18, 19, 0x38000, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_ppu_eram_base_addr_reg[] = + { + {"ppu_eram_base_addr", DPP_FIELD_FLAG_RW, 18, 19, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_ppu_ddr_base_addr_reg[] = + { + {"ppu_ddr_base_addr", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_plcr0_base_addr_reg[] = + { + {"plcr0_base_addr", DPP_FIELD_FLAG_RW, 18, 19, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_etm_stat_start_addr_cfg_reg[] = + { + {"etm_stat_start_addr_cfg", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_etm_stat_depth_cfg_reg[] = + { + {"etm_stat_depth_cfg", DPP_FIELD_FLAG_RW, 2, 3, 0x5, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_cycle_mov_en_cfg_reg[] = + { + {"cycle_mov_en_cfg", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_cpu_ind_wdat0_reg[] = + { + {"wdat0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_cpu_ind_ctrl_tmp0_reg[] = + { + {"reg_tcam_flag", DPP_FIELD_FLAG_RW, 30, 1, 0x0, 0x0}, + {"flush", DPP_FIELD_FLAG_RW, 29, 8, 0x0, 0x0}, + {"rd_wr", DPP_FIELD_FLAG_RW, 21, 1, 0x0, 0x0}, + {"wr_mode", DPP_FIELD_FLAG_RW, 20, 8, 0x0, 0x0}, + {"dat_or_mask", DPP_FIELD_FLAG_RW, 12, 1, 0x0, 0x0}, + {"ram_sel", DPP_FIELD_FLAG_RW, 11, 3, 0x0, 0x0}, + {"addr", DPP_FIELD_FLAG_RW, 8, 9, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_cpu_ind_ctrl_tmp1_reg[] = + { + {"row_or_col_msk", DPP_FIELD_FLAG_RW, 9, 1, 0x0, 0x0}, + {"vben", DPP_FIELD_FLAG_RW, 8, 1, 0x0, 0x0}, + {"vbit", DPP_FIELD_FLAG_RW, 7, 8, 0xff, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_cpu_ind_rd_done_reg[] = + { + {"cpu_ind_rd_done", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_cpu_rdat0_reg[] = + { + {"cpu_rdat0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_cpu_rdat1_reg[] = + { + {"cpu_rdat1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_cpu_rdat2_reg[] = + { + {"cpu_rdat2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_cpu_rdat3_reg[] = + { + {"cpu_rdat3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_cpu_rdat4_reg[] = + { + {"cpu_rdat4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_cpu_rdat5_reg[] = + { + {"cpu_rdat5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_cpu_rdat6_reg[] = + { + {"cpu_rdat6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_cpu_rdat7_reg[] = + { + {"cpu_rdat7", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_cpu_rdat8_reg[] = + { + {"cpu_rdat8", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_cpu_rdat9_reg[] = + { + {"cpu_rdat9", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_cpu_rdat10_reg[] = + { + {"cpu_rdat10", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_cpu_rdat11_reg[] = + { + {"cpu_rdat11", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_cpu_rdat12_reg[] = + { + {"cpu_rdat12", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_cpu_rdat13_reg[] = + { + {"cpu_rdat13", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_cpu_rdat14_reg[] = + { + {"cpu_rdat14", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_cpu_rdat15_reg[] = + { + {"cpu_rdat15", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_cpu_rdat16_reg[] = + { + {"cpu_rdat16", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_cpu_rdat17_reg[] = + { + {"cpu_rdat17", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_cpu_rdat18_reg[] = + { + {"cpu_rdat18", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_cpu_rdat19_reg[] = + { + {"cpu_rdat19", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_qvbo_reg[] = + { + {"qvbo", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_cnt_overflow_mode_reg[] = + { + {"cnt_rd_mode", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0}, + {"cnt_overflow_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_stat_car0_cara_queue_ram0_159_0_reg[] = + { + {"cara_drop", DPP_FIELD_FLAG_RW, 147, 1, 0x0, 0x0}, + {"cara_plcr_en", DPP_FIELD_FLAG_RW, 146, 1, 0x0, 0x0}, + {"cara_profile_id", DPP_FIELD_FLAG_RW, 145, 9, 0x0, 0x0}, + {"cara_tq_h", DPP_FIELD_FLAG_RO, 136, 13, 0x0, 0x0}, + {"cara_tq_l", DPP_FIELD_FLAG_RO, 123, 32, 0x0, 0x0}, + {"cara_ted", DPP_FIELD_FLAG_RO, 91, 19, 0x0, 0x0}, + {"cara_tcd", DPP_FIELD_FLAG_RO, 72, 19, 0x0, 0x0}, + {"cara_tei", DPP_FIELD_FLAG_RO, 53, 27, 0x0, 0x0}, + {"cara_tci", DPP_FIELD_FLAG_RO, 26, 27, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_cara_profile_ram1_255_0_reg[] = + { + {"cara_profile_wr", DPP_FIELD_FLAG_RW, 224, 1, 0x0, 0x0}, + {"cara_pkt_sign", DPP_FIELD_FLAG_RW, 216, 1, 0x0, 0x0}, + {"cara_cd", DPP_FIELD_FLAG_RW, 215, 2, 0x0, 0x0}, + {"cara_cf", DPP_FIELD_FLAG_RW, 213, 1, 0x0, 0x0}, + {"cara_cm", DPP_FIELD_FLAG_RW, 212, 1, 0x0, 0x0}, + {"cara_eir", DPP_FIELD_FLAG_RW, 211, 24, 0x0, 0x0}, + {"cara_cir", DPP_FIELD_FLAG_RW, 187, 24, 0x0, 0x0}, + {"cara_ebs_pbs", DPP_FIELD_FLAG_RW, 163, 27, 0x0, 0x0}, + {"cara_cbs", DPP_FIELD_FLAG_RW, 136, 27, 0x0, 0x0}, + {"cara_c_pri1", DPP_FIELD_FLAG_RW, 109, 5, 0x0, 0x0}, + {"cara_c_pri2", DPP_FIELD_FLAG_RW, 104, 5, 0x0, 0x0}, + {"cara_c_pri3", DPP_FIELD_FLAG_RW, 99, 5, 0x0, 0x0}, + {"cara_c_pri4", DPP_FIELD_FLAG_RW, 94, 5, 0x0, 0x0}, + {"cara_c_pri5", DPP_FIELD_FLAG_RW, 89, 5, 0x0, 0x0}, + {"cara_c_pri6", DPP_FIELD_FLAG_RW, 84, 5, 0x0, 0x0}, + {"cara_c_pri7", DPP_FIELD_FLAG_RW, 79, 5, 0x0, 0x0}, + {"cara_e_g_pri1", DPP_FIELD_FLAG_RW, 74, 5, 0x0, 0x0}, + {"cara_e_g_pri2", DPP_FIELD_FLAG_RW, 69, 5, 0x0, 0x0}, + {"cara_e_g_pri3", DPP_FIELD_FLAG_RW, 64, 5, 0x0, 0x0}, + {"cara_e_g_pri4", DPP_FIELD_FLAG_RW, 59, 5, 0x0, 0x0}, + {"cara_e_g_pri5", DPP_FIELD_FLAG_RW, 54, 5, 0x0, 0x0}, + {"cara_e_g_pri6", DPP_FIELD_FLAG_RW, 49, 5, 0x0, 0x0}, + {"cara_e_g_pri7", DPP_FIELD_FLAG_RW, 44, 5, 0x0, 0x0}, + {"cara_e_y_pri0", DPP_FIELD_FLAG_RW, 39, 5, 0x0, 0x0}, + {"cara_e_y_pri1", DPP_FIELD_FLAG_RW, 34, 5, 0x0, 0x0}, + {"cara_e_y_pri2", DPP_FIELD_FLAG_RW, 29, 5, 0x0, 0x0}, + {"cara_e_y_pri3", DPP_FIELD_FLAG_RW, 24, 5, 0x0, 0x0}, + {"cara_e_y_pri4", DPP_FIELD_FLAG_RW, 19, 5, 0x0, 0x0}, + {"cara_e_y_pri5", DPP_FIELD_FLAG_RW, 14, 5, 0x0, 0x0}, + {"cara_e_y_pri6", DPP_FIELD_FLAG_RW, 9, 5, 0x0, 0x0}, + {"cara_e_y_pri7", DPP_FIELD_FLAG_RW, 4, 5, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_cara_qovs_ram_ram2_reg[] = + { + {"cara_qovs", DPP_FIELD_FLAG_RW, 1, 2, 0x2, 0x0}, + }; +DPP_FIELD_T g_stat_car0_look_up_table1_reg[] = + { + {"cara_flow_id", DPP_FIELD_FLAG_RW, 14, 12, 0x0, 0x0}, + {"cara_sp", DPP_FIELD_FLAG_RW, 2, 3, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_cara_pkt_des_i_cnt_reg[] = + { + {"cara_pkt_des_i_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_cara_green_pkt_i_cnt_reg[] = + { + {"cara_green_pkt_i_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_cara_yellow_pkt_i_cnt_reg[] = + { + {"cara_yellow_pkt_i_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_cara_red_pkt_i_cnt_reg[] = + { + {"cara_red_pkt_i_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_cara_pkt_des_o_cnt_reg[] = + { + {"cara_pkt_des_o_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_cara_green_pkt_o_cnt_reg[] = + { + {"cara_green_pkt_o_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_cara_yellow_pkt_o_cnt_reg[] = + { + {"cara_yellow_pkt_o_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_cara_red_pkt_o_cnt_reg[] = + { + {"cara_red_pkt_o_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_cara_pkt_des_fc_for_cfg_cnt_reg[] = + { + {"cara_pkt_des_fc_for_cfg_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_cara_appoint_qnum_or_sp_reg[] = + { + {"cara_appoint_qnum_or_not", DPP_FIELD_FLAG_RW, 19, 1, 0x0, 0x0}, + {"cara_appoint_sp_or_not", DPP_FIELD_FLAG_RW, 18, 1, 0x0, 0x0}, + {"cara_plcr_stat_sp", DPP_FIELD_FLAG_RW, 17, 3, 0x0, 0x0}, + {"cara_plcr_stat_qnum", DPP_FIELD_FLAG_RW, 14, 15, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_cara_cfgmt_count_mode_reg[] = + { + {"cara_cfgmt_count_overflow_mode", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"cara_cfgmt_count_rd_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_stat_car0_cara_pkt_size_cnt_reg[] = + { + {"cara_pkt_size_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_cara_plcr_init_dont_reg[] = + { + {"cara_plcr_init_done", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_carb_queue_ram0_159_0_reg[] = + { + {"carb_drop", DPP_FIELD_FLAG_RW, 147, 1, 0x0, 0x0}, + {"carb_plcr_en", DPP_FIELD_FLAG_RW, 146, 1, 0x0, 0x0}, + {"carb_profile_id", DPP_FIELD_FLAG_RW, 145, 9, 0x0, 0x0}, + {"carb_tq_h", DPP_FIELD_FLAG_RO, 136, 13, 0x0, 0x0}, + {"carb_tq_l", DPP_FIELD_FLAG_RO, 123, 32, 0x0, 0x0}, + {"carb_ted", DPP_FIELD_FLAG_RO, 91, 19, 0x0, 0x0}, + {"carb_tcd", DPP_FIELD_FLAG_RO, 72, 19, 0x0, 0x0}, + {"carb_tei", DPP_FIELD_FLAG_RO, 53, 27, 0x0, 0x0}, + {"carb_tci", DPP_FIELD_FLAG_RO, 26, 27, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_carb_profile_ram1_255_0_reg[] = + { + {"carb_profile_wr", DPP_FIELD_FLAG_RW, 224, 1, 0x0, 0x0}, + {"carb_random_discard_en_e", DPP_FIELD_FLAG_RW, 218, 1, 0x0, 0x0}, + {"carb_random_discard_en_c", DPP_FIELD_FLAG_RW, 217, 1, 0x0, 0x0}, + {"carb_pkt_sign", DPP_FIELD_FLAG_RW, 216, 1, 0x0, 0x0}, + {"carb_cd", DPP_FIELD_FLAG_RW, 215, 2, 0x0, 0x0}, + {"carb_cf", DPP_FIELD_FLAG_RW, 213, 1, 0x0, 0x0}, + {"carb_cm", DPP_FIELD_FLAG_RW, 212, 1, 0x0, 0x0}, + {"carb_eir", DPP_FIELD_FLAG_RW, 211, 24, 0x0, 0x0}, + {"carb_cir", DPP_FIELD_FLAG_RW, 187, 24, 0x0, 0x0}, + {"carb_ebs_pbs", DPP_FIELD_FLAG_RW, 163, 27, 0x0, 0x0}, + {"carb_cbs", DPP_FIELD_FLAG_RW, 136, 27, 0x0, 0x0}, + {"carb_c_pri1", DPP_FIELD_FLAG_RW, 109, 5, 0x0, 0x0}, + {"carb_c_pri2", DPP_FIELD_FLAG_RW, 104, 5, 0x0, 0x0}, + {"carb_c_pri3", DPP_FIELD_FLAG_RW, 99, 5, 0x0, 0x0}, + {"carb_c_pri4", DPP_FIELD_FLAG_RW, 94, 5, 0x0, 0x0}, + {"carb_c_pri5", DPP_FIELD_FLAG_RW, 89, 5, 0x0, 0x0}, + {"carb_c_pri6", DPP_FIELD_FLAG_RW, 84, 5, 0x0, 0x0}, + {"carb_c_pri7", DPP_FIELD_FLAG_RW, 79, 5, 0x0, 0x0}, + {"carb_e_g_pri1", DPP_FIELD_FLAG_RW, 74, 5, 0x0, 0x0}, + {"carb_e_g_pri2", DPP_FIELD_FLAG_RW, 69, 5, 0x0, 0x0}, + {"carb_e_g_pri3", DPP_FIELD_FLAG_RW, 64, 5, 0x0, 0x0}, + {"carb_e_g_pri4", DPP_FIELD_FLAG_RW, 59, 5, 0x0, 0x0}, + {"carb_e_g_pri5", DPP_FIELD_FLAG_RW, 54, 5, 0x0, 0x0}, + {"carb_e_g_pri6", DPP_FIELD_FLAG_RW, 49, 5, 0x0, 0x0}, + {"carb_e_g_pri7", DPP_FIELD_FLAG_RW, 44, 5, 0x0, 0x0}, + {"carb_e_y_pri0", DPP_FIELD_FLAG_RW, 39, 5, 0x0, 0x0}, + {"carb_e_y_pri1", DPP_FIELD_FLAG_RW, 34, 5, 0x0, 0x0}, + {"carb_e_y_pri2", DPP_FIELD_FLAG_RW, 29, 5, 0x0, 0x0}, + {"carb_e_y_pri3", DPP_FIELD_FLAG_RW, 24, 5, 0x0, 0x0}, + {"carb_e_y_pri4", DPP_FIELD_FLAG_RW, 19, 5, 0x0, 0x0}, + {"carb_e_y_pri5", DPP_FIELD_FLAG_RW, 14, 5, 0x0, 0x0}, + {"carb_e_y_pri6", DPP_FIELD_FLAG_RW, 9, 5, 0x0, 0x0}, + {"carb_e_y_pri7", DPP_FIELD_FLAG_RW, 4, 5, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_carb_qovs_ram_ram2_reg[] = + { + {"carb_qovs", DPP_FIELD_FLAG_RW, 1, 2, 0x2, 0x0}, + }; +DPP_FIELD_T g_stat_car0_look_up_table2_reg[] = + { + {"carb_flow_id", DPP_FIELD_FLAG_RW, 12, 10, 0x0, 0x0}, + {"carb_sp", DPP_FIELD_FLAG_RW, 2, 3, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_carb_pkt_des_i_cnt_reg[] = + { + {"carb_pkt_des_i_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_carb_green_pkt_i_cnt_reg[] = + { + {"carb_green_pkt_i_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_carb_yellow_pkt_i_cnt_reg[] = + { + {"carb_yellow_pkt_i_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_carb_red_pkt_i_cnt_reg[] = + { + {"carb_red_pkt_i_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_carb_pkt_des_o_cnt_reg[] = + { + {"carb_pkt_des_o_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_carb_green_pkt_o_cnt_reg[] = + { + {"carb_green_pkt_o_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_carb_yellow_pkt_o_cnt_reg[] = + { + {"carb_yellow_pkt_o_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_carb_red_pkt_o_cnt_reg[] = + { + {"carb_red_pkt_o_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_carb_pkt_des_fc_for_cfg_cnt_reg[] = + { + {"carb_pkt_des_fc_for_cfg_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_carb_appoint_qnum_or_sp_reg[] = + { + {"carb_appoint_qnum_or_not", DPP_FIELD_FLAG_RW, 16, 1, 0x0, 0x0}, + {"carb_appoint_sp_or_not", DPP_FIELD_FLAG_RW, 15, 1, 0x0, 0x0}, + {"carb_plcr_stat_sp", DPP_FIELD_FLAG_RW, 14, 3, 0x0, 0x0}, + {"carb_plcr_stat_qnum", DPP_FIELD_FLAG_RW, 11, 12, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_carb_cfgmt_count_mode_reg[] = + { + {"carb_cfgmt_count_overflow_mode", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"carb_cfgmt_count_rd_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_stat_car0_carb_pkt_size_cnt_reg[] = + { + {"carb_pkt_size_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_carb_plcr_init_dont_reg[] = + { + {"carb_plcr_init_done", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_carc_queue_ram0_159_0_reg[] = + { + {"carc_drop", DPP_FIELD_FLAG_RW, 147, 1, 0x0, 0x0}, + {"carc_plcr_en", DPP_FIELD_FLAG_RW, 146, 1, 0x0, 0x0}, + {"carc_profile_id", DPP_FIELD_FLAG_RW, 145, 9, 0x0, 0x0}, + {"carc_tq_h", DPP_FIELD_FLAG_RO, 136, 13, 0x0, 0x0}, + {"carc_tq_l", DPP_FIELD_FLAG_RO, 123, 32, 0x0, 0x0}, + {"carc_ted", DPP_FIELD_FLAG_RO, 91, 19, 0x0, 0x0}, + {"carc_tcd", DPP_FIELD_FLAG_RO, 72, 19, 0x0, 0x0}, + {"carc_tei", DPP_FIELD_FLAG_RO, 53, 27, 0x0, 0x0}, + {"carc_tci", DPP_FIELD_FLAG_RO, 26, 27, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_carc_profile_ram1_255_0_reg[] = + { + {"carc_profile_wr", DPP_FIELD_FLAG_RW, 224, 1, 0x0, 0x0}, + {"carc_random_discard_en_e", DPP_FIELD_FLAG_RW, 218, 1, 0x0, 0x0}, + {"carc_random_discard_en_c", DPP_FIELD_FLAG_RW, 217, 1, 0x0, 0x0}, + {"carc_pkt_sign", DPP_FIELD_FLAG_RW, 216, 1, 0x0, 0x0}, + {"carc_cd", DPP_FIELD_FLAG_RW, 215, 2, 0x0, 0x0}, + {"carc_cf", DPP_FIELD_FLAG_RW, 213, 1, 0x0, 0x0}, + {"carc_cm", DPP_FIELD_FLAG_RW, 212, 1, 0x0, 0x0}, + {"carc_eir", DPP_FIELD_FLAG_RW, 211, 24, 0x0, 0x0}, + {"carc_cir", DPP_FIELD_FLAG_RW, 187, 24, 0x0, 0x0}, + {"carc_ebs_pbs", DPP_FIELD_FLAG_RW, 163, 27, 0x0, 0x0}, + {"carc_cbs", DPP_FIELD_FLAG_RW, 136, 27, 0x0, 0x0}, + {"carc_c_pri1", DPP_FIELD_FLAG_RW, 109, 5, 0x0, 0x0}, + {"carc_c_pri2", DPP_FIELD_FLAG_RW, 104, 5, 0x0, 0x0}, + {"carc_c_pri3", DPP_FIELD_FLAG_RW, 99, 5, 0x0, 0x0}, + {"carc_c_pri4", DPP_FIELD_FLAG_RW, 94, 5, 0x0, 0x0}, + {"carc_c_pri5", DPP_FIELD_FLAG_RW, 89, 5, 0x0, 0x0}, + {"carc_c_pri6", DPP_FIELD_FLAG_RW, 84, 5, 0x0, 0x0}, + {"carc_c_pri7", DPP_FIELD_FLAG_RW, 79, 5, 0x0, 0x0}, + {"carc_e_g_pri1", DPP_FIELD_FLAG_RW, 74, 5, 0x0, 0x0}, + {"carc_e_g_pri2", DPP_FIELD_FLAG_RW, 69, 5, 0x0, 0x0}, + {"carc_e_g_pri3", DPP_FIELD_FLAG_RW, 64, 5, 0x0, 0x0}, + {"carc_e_g_pri4", DPP_FIELD_FLAG_RW, 59, 5, 0x0, 0x0}, + {"carc_e_g_pri5", DPP_FIELD_FLAG_RW, 54, 5, 0x0, 0x0}, + {"carc_e_g_pri6", DPP_FIELD_FLAG_RW, 49, 5, 0x0, 0x0}, + {"carc_e_g_pri7", DPP_FIELD_FLAG_RW, 44, 5, 0x0, 0x0}, + {"carc_e_y_pri0", DPP_FIELD_FLAG_RW, 39, 5, 0x0, 0x0}, + {"carc_e_y_pri1", DPP_FIELD_FLAG_RW, 34, 5, 0x0, 0x0}, + {"carc_e_y_pri2", DPP_FIELD_FLAG_RW, 29, 5, 0x0, 0x0}, + {"carc_e_y_pri3", DPP_FIELD_FLAG_RW, 24, 5, 0x0, 0x0}, + {"carc_e_y_pri4", DPP_FIELD_FLAG_RW, 19, 5, 0x0, 0x0}, + {"carc_e_y_pri5", DPP_FIELD_FLAG_RW, 14, 5, 0x0, 0x0}, + {"carc_e_y_pri6", DPP_FIELD_FLAG_RW, 9, 5, 0x0, 0x0}, + {"carc_e_y_pri7", DPP_FIELD_FLAG_RW, 4, 5, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_carc_qovs_ram_ram2_reg[] = + { + {"carc_qovs", DPP_FIELD_FLAG_RW, 1, 2, 0x2, 0x0}, + }; +DPP_FIELD_T g_stat_car0_carc_pkt_des_i_cnt_reg[] = + { + {"carc_pkt_des_i_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_carc_green_pkt_i_cnt_reg[] = + { + {"carc_green_pkt_i_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_carc_yellow_pkt_i_cnt_reg[] = + { + {"carc_yellow_pkt_i_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_carc_red_pkt_i_cnt_reg[] = + { + {"carc_red_pkt_i_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_carc_pkt_des_o_cnt_reg[] = + { + {"carc_pkt_des_o_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_carc_green_pkt_o_cnt_reg[] = + { + {"carc_green_pkt_o_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_carc_yellow_pkt_o_cnt_reg[] = + { + {"carc_yellow_pkt_o_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_carc_red_pkt_o_cnt_reg[] = + { + {"carc_red_pkt_o_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_carc_pkt_des_fc_for_cfg_cnt_reg[] = + { + {"carc_pkt_des_fc_for_cfg_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_carc_appoint_qnum_or_sp_reg[] = + { + {"carc_appoint_qnum_or_not", DPP_FIELD_FLAG_RW, 14, 1, 0x0, 0x0}, + {"carc_appoint_sp_or_not", DPP_FIELD_FLAG_RW, 13, 1, 0x0, 0x0}, + {"carc_plcr_stat_sp", DPP_FIELD_FLAG_RW, 12, 3, 0x0, 0x0}, + {"carc_plcr_stat_qnum", DPP_FIELD_FLAG_RW, 9, 10, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_carc_cfgmt_count_mode_reg[] = + { + {"carc_cfgmt_count_overflow_mode", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"carc_cfgmt_count_rd_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_stat_car0_carc_pkt_size_cnt_reg[] = + { + {"carc_pkt_size_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_carc_plcr_init_dont_reg[] = + { + {"carc_plcr_init_done", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_carb_random_ram_reg[] = + { + {"para8_e", DPP_FIELD_FLAG_RW, 491, 27, 0x0, 0x0}, + {"para7_e", DPP_FIELD_FLAG_RW, 464, 27, 0x0, 0x0}, + {"para6_e", DPP_FIELD_FLAG_RW, 437, 27, 0x0, 0x0}, + {"para5_e", DPP_FIELD_FLAG_RW, 410, 14, 0x0, 0x0}, + {"para4_h_e", DPP_FIELD_FLAG_RW, 396, 9, 0x0, 0x0}, + {"para4_l_e", DPP_FIELD_FLAG_RW, 387, 32, 0x0, 0x0}, + {"para3_e", DPP_FIELD_FLAG_RW, 355, 14, 0x0, 0x0}, + {"para2_h_e", DPP_FIELD_FLAG_RW, 341, 9, 0x0, 0x0}, + {"para2_l_e", DPP_FIELD_FLAG_RW, 332, 32, 0x0, 0x0}, + {"para1_e", DPP_FIELD_FLAG_RW, 300, 14, 0x0, 0x0}, + {"para0_h_e", DPP_FIELD_FLAG_RW, 286, 9, 0x0, 0x0}, + {"para0_l_e", DPP_FIELD_FLAG_RW, 277, 32, 0x0, 0x0}, + {"para8_c", DPP_FIELD_FLAG_RW, 245, 27, 0x0, 0x0}, + {"para7_c", DPP_FIELD_FLAG_RW, 218, 27, 0x0, 0x0}, + {"para6_c", DPP_FIELD_FLAG_RW, 191, 27, 0x0, 0x0}, + {"para5_c", DPP_FIELD_FLAG_RW, 164, 14, 0x0, 0x0}, + {"para4_h_c", DPP_FIELD_FLAG_RW, 150, 9, 0x0, 0x0}, + {"para4_l_c", DPP_FIELD_FLAG_RW, 141, 32, 0x0, 0x0}, + {"para3_c", DPP_FIELD_FLAG_RW, 109, 14, 0x0, 0x0}, + {"para2_h_c", DPP_FIELD_FLAG_RW, 95, 9, 0x0, 0x0}, + {"para2_l_c", DPP_FIELD_FLAG_RW, 86, 32, 0x0, 0x0}, + {"para1_c", DPP_FIELD_FLAG_RW, 54, 14, 0x0, 0x0}, + {"para0_h_c", DPP_FIELD_FLAG_RW, 40, 9, 0x0, 0x0}, + {"para0_l_c", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_carc_random_ram_reg[] = + { + {"para8_e", DPP_FIELD_FLAG_RW, 491, 27, 0x0, 0x0}, + {"para7_e", DPP_FIELD_FLAG_RW, 464, 27, 0x0, 0x0}, + {"para6_e", DPP_FIELD_FLAG_RW, 437, 27, 0x0, 0x0}, + {"para5_e", DPP_FIELD_FLAG_RW, 410, 14, 0x0, 0x0}, + {"para4_h_e", DPP_FIELD_FLAG_RW, 396, 9, 0x0, 0x0}, + {"para4_l_e", DPP_FIELD_FLAG_RW, 387, 32, 0x0, 0x0}, + {"para3_e", DPP_FIELD_FLAG_RW, 355, 14, 0x0, 0x0}, + {"para2_h_e", DPP_FIELD_FLAG_RW, 341, 9, 0x0, 0x0}, + {"para2_l_e", DPP_FIELD_FLAG_RW, 332, 32, 0x0, 0x0}, + {"para1_e", DPP_FIELD_FLAG_RW, 300, 14, 0x0, 0x0}, + {"para0_h_e", DPP_FIELD_FLAG_RW, 286, 9, 0x0, 0x0}, + {"para0_l_e", DPP_FIELD_FLAG_RW, 277, 32, 0x0, 0x0}, + {"para8_c", DPP_FIELD_FLAG_RW, 245, 27, 0x0, 0x0}, + {"para7_c", DPP_FIELD_FLAG_RW, 218, 27, 0x0, 0x0}, + {"para6_c", DPP_FIELD_FLAG_RW, 191, 27, 0x0, 0x0}, + {"para5_c", DPP_FIELD_FLAG_RW, 164, 14, 0x0, 0x0}, + {"para4_h_c", DPP_FIELD_FLAG_RW, 150, 9, 0x0, 0x0}, + {"para4_l_c", DPP_FIELD_FLAG_RW, 141, 32, 0x0, 0x0}, + {"para3_c", DPP_FIELD_FLAG_RW, 109, 14, 0x0, 0x0}, + {"para2_h_c", DPP_FIELD_FLAG_RW, 95, 9, 0x0, 0x0}, + {"para2_l_c", DPP_FIELD_FLAG_RW, 86, 32, 0x0, 0x0}, + {"para1_c", DPP_FIELD_FLAG_RW, 54, 14, 0x0, 0x0}, + {"para0_h_c", DPP_FIELD_FLAG_RW, 40, 9, 0x0, 0x0}, + {"para0_l_c", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_cara_begin_flow_id_reg[] = + { + {"cara_begin_flow_id", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_carb_begin_flow_id_reg[] = + { + {"carb_begin_flow_id", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_carc_begin_flow_id_reg[] = + { + {"carc_begin_flow_id", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_prog_full_assert_cfg_w_reg[] = + { + {"prog_full_assert_cfg_w", DPP_FIELD_FLAG_RW, 7, 8, 0xe0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_prog_full_negate_cfg_w_reg[] = + { + {"prog_full_negate_cfg_w", DPP_FIELD_FLAG_RW, 7, 8, 0xdf, 0x0}, + }; +DPP_FIELD_T g_stat_car0_timeout_limit_reg[] = + { + {"timeout_limit", DPP_FIELD_FLAG_RW, 15, 16, 0x100, 0x0}, + }; +DPP_FIELD_T g_stat_car0_pkt_des_fifo_overflow_reg[] = + { + {"pkt_des_fifo_overflow", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_pkt_des_fifo_underflow_reg[] = + { + {"pkt_des_fifo_underflow", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_pkt_des_fifo_prog_full_reg[] = + { + {"pkt_des_fifo_prog_full", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_pkt_des_fifo_prog_empty_reg[] = + { + {"pkt_des_fifo_prog_empty", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_stat_car0_pkt_des_fifo_full_reg[] = + { + {"pkt_des_fifo_full", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_pkt_des_fifo_empty_reg[] = + { + {"pkt_des_fifo_empty", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_stat_car0_pkt_size_offset_reg[] = + { + {"pkt_size_offset", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_car_plcr_init_dont_reg[] = + { + {"plcr_init_done", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_max_pkt_size_a_reg[] = + { + {"max_pkt_size_a", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_max_pkt_size_b_reg[] = + { + {"max_pkt_size_b", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_max_pkt_size_c_reg[] = + { + {"max_pkt_size_c", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_car_hierarchy_mode_reg[] = + { + {"car_hierarchy_mode", DPP_FIELD_FLAG_RW, 1, 2, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_prog_empty_assert_cfg_w_reg[] = + { + {"prog_empty_assert_cfg_w", DPP_FIELD_FLAG_RW, 7, 8, 0x3, 0x0}, + }; +DPP_FIELD_T g_stat_car0_prog_empty_negate_cfg_w_reg[] = + { + {"prog_empty_negate_cfg_w", DPP_FIELD_FLAG_RW, 7, 8, 0x4, 0x0}, + }; +DPP_FIELD_T g_stat_car0_pkt_des_fifo_ovf_int_reg[] = + { + {"pkt_des_fifo_ovf_int", DPP_FIELD_FLAG_RO, 1, 2, 0x00, 0x0}, + }; +DPP_FIELD_T g_stat_car0_pkt_des_fifo_data_count_reg[] = + { + {"pkt_des_fifo_data_count", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_pkt_des_fifo_udf_int_reg[] = + { + {"pkt_des_fifo_udf_int", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_cara_queue_ram0_159_0_pkt_reg[] = + { + {"cara_drop", DPP_FIELD_FLAG_RW, 147, 1, 0x0, 0x0}, + {"cara_plcr_en", DPP_FIELD_FLAG_RW, 146, 1, 0x0, 0x0}, + {"cara_profile_id", DPP_FIELD_FLAG_RW, 145, 9, 0x0, 0x0}, + {"cara_tq_h", DPP_FIELD_FLAG_RO, 136, 13, 0x0, 0x0}, + {"cara_tq_l", DPP_FIELD_FLAG_RO, 123, 32, 0x0, 0x0}, + {"cara_dc_high", DPP_FIELD_FLAG_RO, 50, 5, 0x0, 0x0}, + {"cara_dc_low", DPP_FIELD_FLAG_RO, 45, 32, 0x0, 0x0}, + {"cara_tc", DPP_FIELD_FLAG_RO, 13, 14, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_car0_cara_profile_ram1_255_0_pkt_reg[] = + { + {"cara_profile_wr", DPP_FIELD_FLAG_RW, 224, 1, 0x0, 0x0}, + {"cara_pkt_sign", DPP_FIELD_FLAG_RW, 216, 1, 0x0, 0x0}, + {"cara_pkt_cir", DPP_FIELD_FLAG_RW, 189, 30, 0x0, 0x0}, + {"cara_pkt_cbs", DPP_FIELD_FLAG_RW, 150, 14, 0x0, 0x0}, + {"cara_pri0", DPP_FIELD_FLAG_RW, 39, 5, 0x0, 0x0}, + {"cara_pri1", DPP_FIELD_FLAG_RW, 34, 5, 0x0, 0x0}, + {"cara_pri2", DPP_FIELD_FLAG_RW, 29, 5, 0x0, 0x0}, + {"cara_pri3", DPP_FIELD_FLAG_RW, 24, 5, 0x0, 0x0}, + {"cara_pri4", DPP_FIELD_FLAG_RW, 19, 5, 0x0, 0x0}, + {"cara_pri5", DPP_FIELD_FLAG_RW, 14, 5, 0x0, 0x0}, + {"cara_pri6", DPP_FIELD_FLAG_RW, 9, 5, 0x0, 0x0}, + {"cara_pri7", DPP_FIELD_FLAG_RW, 4, 5, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat4k_etcam_block0_7_port_id_cfg_reg[] = + { + {"block7_port_id", DPP_FIELD_FLAG_RW, 31, 4, 0x0, 0x0}, + {"block6_port_id", DPP_FIELD_FLAG_RW, 27, 4, 0x0, 0x0}, + {"block5_port_id", DPP_FIELD_FLAG_RW, 23, 4, 0x0, 0x0}, + {"block4_port_id", DPP_FIELD_FLAG_RW, 19, 4, 0x0, 0x0}, + {"block3_port_id", DPP_FIELD_FLAG_RW, 15, 4, 0x0, 0x0}, + {"block2_port_id", DPP_FIELD_FLAG_RW, 11, 4, 0x0, 0x0}, + {"block1_port_id", DPP_FIELD_FLAG_RW, 7, 4, 0x0, 0x0}, + {"block0_port_id", DPP_FIELD_FLAG_RW, 3, 4, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat4k_etcam_block0_3_base_addr_cfg_reg[] = + { + {"block3_base_addr_cfg", DPP_FIELD_FLAG_RW, 30, 7, 0x0, 0x0}, + {"block2_base_addr_cfg", DPP_FIELD_FLAG_RW, 22, 7, 0x0, 0x0}, + {"block1_base_addr_cfg", DPP_FIELD_FLAG_RW, 14, 7, 0x0, 0x0}, + {"block0_base_addr_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat4k_etcam_block4_7_base_addr_cfg_reg[] = + { + {"block7_base_addr_cfg", DPP_FIELD_FLAG_RW, 30, 7, 0x0, 0x0}, + {"block6_base_addr_cfg", DPP_FIELD_FLAG_RW, 22, 7, 0x0, 0x0}, + {"block5_base_addr_cfg", DPP_FIELD_FLAG_RW, 14, 7, 0x0, 0x0}, + {"block4_base_addr_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_cfg_eram_wr_interval_cnt_reg[] = + { + {"cfg_eram_wr_interval_cnt", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_cfg_zcam_wr_interval_cnt_reg[] = + { + {"cfg_zcam_wr_interval_cnt", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_cfg_tcam_wr_interval_cnt_reg[] = + { + {"cfg_zcam_wr_interval_cnt", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_cfg_ddr_wr_interval_cnt_reg[] = + { + {"cfg_ddr_wr_interval_cnt", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_cfg_hash_wr_interval_cnt_reg[] = + { + {"cfg_hash_wr_interval_cnt", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_cfg_eram_rd_interval_cnt_reg[] = + { + {"cfg_eram_rd_interval_cnt", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_cfg_zcam_rd_interval_cnt_reg[] = + { + {"cfg_zcam_rd_interval_cnt", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_cfg_tcam_rd_interval_cnt_reg[] = + { + {"cfg_tcam_rd_interval_cnt", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_cfg_ddr_rd_interval_cnt_reg[] = + { + {"cfg_ddr_rd_interval_cnt", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_cfg_dtb_queue_lock_state_0_3_reg[] = + { + {"cfg_dtb_queue_lock_state", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_axim0_w_convert_0_mode_reg[] = + { + {"w_convert_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_axim0_r_convert_0_mode_reg[] = + { + {"r_convert_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_axim0_aximr_os_reg[] = + { + {"aximr_os", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_axim1_w_convert_1_mode_reg[] = + { + {"w_convert_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_axim1_r_convert_1_mode_reg[] = + { + {"r_convert_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_axis_axis_convert_mode_reg[] = + { + {"w_r_convert_mode", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb4k_dtb_enq_cfg_queue_dtb_addr_h_0_127_reg[] = + { + {"cfg_queue_dtb_addr_h", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb4k_dtb_enq_cfg_queue_dtb_addr_l_0_127_reg[] = + { + {"cfg_queue_dtb_addr_l", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb4k_dtb_enq_cfg_queue_dtb_len_0_127_reg[] = + { + {"cfg_dtb_cmd_type", DPP_FIELD_FLAG_RW, 30, 1, 0x0, 0x0}, + {"cfg_dtb_cmd_int_en", DPP_FIELD_FLAG_RW, 29, 1, 0x0, 0x0}, + {"cfg_queue_dtb_len", DPP_FIELD_FLAG_RW, 9, 10, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb4k_dtb_enq_info_queue_buf_space_left_0_127_reg[] = + { + {"info_queue_buf_space_left", DPP_FIELD_FLAG_RO, 5, 6, 0x20, 0x0}, + }; +DPP_FIELD_T g_dtb4k_dtb_enq_cfg_epid_v_func_num_0_127_reg[] = + { + {"dbi_en", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, + {"queue_en", DPP_FIELD_FLAG_RW, 30, 1, 0x0, 0x0}, + {"cfg_epid", DPP_FIELD_FLAG_RW, 27, 4, 0x0, 0x0}, + {"cfg_vfunc_num", DPP_FIELD_FLAG_RW, 23, 8, 0x0, 0x0}, + {"cfg_vector", DPP_FIELD_FLAG_RW, 14, 7, 0x0, 0x0}, + {"cfg_func_num", DPP_FIELD_FLAG_RW, 7, 3, 0x0, 0x0}, + {"cfg_vfunc_active", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpg_ms_en_reg[] = + { + {"cpu_trpgrx_ms_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpg_port_en_reg[] = + { + {"cpu_trpgrx_port_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpg_look_en_reg[] = + { + {"cpu_trpgrx_look_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_ram_almost_full_reg[] = + { + {"cpu_trpgrx_ram_almost_full", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_ram_test_en_reg[] = + { + {"cpu_trpgrx_ram_test_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_inmod_pfc_rdy_en_reg[] = + { + {"cpu_trpgrx_inmod_pfc_rdy_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_pkt_num_h_reg[] = + { + {"cpu_trpgrx_pkt_num_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_pkt_num_l_reg[] = + { + {"cpu_trpgrx_pkt_num_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_pkt_byte_num_h_reg[] = + { + {"cpu_trpgrx_pkt_byte_num_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_pkt_byte_num_l_reg[] = + { + {"cpu_trpgrx_pkt_byte_num_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_pkt_cnt_clr_reg[] = + { + {"cpu_trpgrx_pkt_cnt_clr", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_fc_clk_freq_reg[] = + { + {"cpu_trpgrx_fc_clk_freq", DPP_FIELD_FLAG_RW, 10, 11, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_fc_en_reg[] = + { + {"cpu_trpgrx_fc_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_fc_token_add_num_reg[] = + { + {"cpu_trpgrx_fc_token_add_num", DPP_FIELD_FLAG_RW, 14, 15, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_fc_token_max_num_reg[] = + { + {"cpu_trpgrx_fc_token_max_num", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_port_state_info_reg[] = + { + {"cpu_trpgrx_port_state_info", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_ram_past_max_dep_reg[] = + { + {"cpu_trpgrx_ram_past_max_dep", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_ram_past_max_dep_clr_reg[] = + { + {"cpu_trpgrx_ram_past_max_dep_clr", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_pkt_past_max_len_reg[] = + { + {"cpu_trpgrx_pkt_past_max_len", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_pkt_past_max_len_clr_reg[] = + { + {"cpu_trpgrx_pkt_past_max_len_clr", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_pkt_past_min_len_reg[] = + { + {"cpu_trpgrx_pkt_past_min_len", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_pkt_past_min_len_clr_reg[] = + { + {"cpu_trpgrx_pkt_past_min_len_clr", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_rx_ram_trpg_rx_data_ram_reg[] = + { + {"trpg_rx_data_ram", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_rx_ram_trpg_rx_info_ram_reg[] = + { + {"trpg_rx_info_ram", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpg_ms_en_reg[] = + { + {"cpu_trpgtx_ms_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpg_port_en_reg[] = + { + {"cpu_trpgtx_port_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpg_look_en_reg[] = + { + {"cpu_trpgtx_look_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpgtx_ram_almost_full_reg[] = + { + {"cpu_trpgtx_ram_almost_full", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpgtx_ram_test_en_reg[] = + { + {"cpu_trpgtx_ram_test_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpgtx_pkt_num_h_reg[] = + { + {"cpu_trpgtx_pkt_num_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpgtx_pkt_num_l_reg[] = + { + {"cpu_trpgtx_pkt_num_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpgtx_pkt_byte_num_h_reg[] = + { + {"cpu_trpgtx_pkt_byte_num_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpgtx_pkt_byte_num_l_reg[] = + { + {"cpu_trpgtx_pkt_byte_num_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpgtx_pkt_cnt_clr_reg[] = + { + {"cpu_trpgtx_pkt_cnt_clr", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpgtx_fc_clk_freq_reg[] = + { + {"cpu_trpgtx_fc_clk_freq", DPP_FIELD_FLAG_RW, 10, 11, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpgtx_fc_en_reg[] = + { + {"cpu_trpgtx_fc_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpgtx_fc_token_add_num_reg[] = + { + {"cpu_trpgtx_fc_token_add_num", DPP_FIELD_FLAG_RW, 14, 15, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpgtx_fc_token_max_num_reg[] = + { + {"cpu_trpgtx_fc_token_max_num", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpgtx_port_state_info_reg[] = + { + {"cpu_trpgtx_port_state_info", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpgtx_ram_past_max_dep_reg[] = + { + {"cpu_trpgtx_ram_past_max_dep", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpgtx_ram_past_max_dep_clr_reg[] = + { + {"cpu_trpgtx_ram_past_max_dep_clr", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpgtx_pkt_past_max_len_reg[] = + { + {"cpu_trpgtx_pkt_past_max_len", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpgtx_pkt_past_max_len_clr_reg[] = + { + {"cpu_trpgtx_pkt_past_max_len_clr", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpgtx_pkt_past_min_len_reg[] = + { + {"cpu_trpgtx_pkt_past_min_len", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpgtx_pkt_past_min_len_clr_reg[] = + { + {"cpu_trpgtx_pkt_past_min_len_clr", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_tx_etm_port_cpu_trpgtx_etm_ram_almost_full_reg[] = + { + {"cpu_trpgtx_etm_ram_almost_full", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_tx_etm_port_cpu_trpgtx_etm_ram_test_en_reg[] = + { + {"cpu_trpgtx_etm_ram_test_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_tx_glb_cpu_todtime_update_int_mask_reg[] = + { + {"cpu_todtime_update_int_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_tx_glb_cpu_todtime_update_int_clr_reg[] = + { + {"cpu_todtime_update_int_clr", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_tx_glb_cpu_todtime_ram_test_en_reg[] = + { + {"cpu_todtime_ram_test_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_tx_ram_trpg_tx_data_ram_reg[] = + { + {"trpg_tx_data_ram", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_tx_ram_trpg_tx_info_ram_reg[] = + { + {"trpg_tx_info_ram", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_tx_etm_ram_trpg_tx_etm_data_ram_reg[] = + { + {"trpg_tx_etm_data_ram", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_tx_etm_ram_trpg_tx_etm_info_ram_reg[] = + { + {"trpg_tx_etm_info_ram", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cfgmt_chip_version_reg_reg[] = + { + {"chip_version_reg", DPP_FIELD_FLAG_RO, 31, 4, 0x1, 0x0}, + {"chip_sub_reg", DPP_FIELD_FLAG_RO, 27, 4, 0x0, 0x0}, + {"chip_type_reg", DPP_FIELD_FLAG_RO, 23, 24, 0x211650, 0x0}, + }; +DPP_FIELD_T g_etm_cfgmt_chip_date_reg_reg[] = + { + {"chip_date_reg", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cfgmt_cfgmt_crc_en_reg[] = + { + {"cfgmt_crc_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cfgmt_cfg_port_transfer_en_reg[] = + { + {"cfg_port_transfer_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cfgmt_tm_sa_work_mode_reg[] = + { + {"tm_sa_work_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cfgmt_local_sa_id_reg[] = + { + {"local_sa_id", DPP_FIELD_FLAG_RW, 6, 7, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_olif_olif_rdy_reg[] = + { + {"cfgmt_block_mode", DPP_FIELD_FLAG_RO, 5, 2, 0x2, 0x0}, + {"cfgmt_count_overflow_mode", DPP_FIELD_FLAG_RO, 3, 1, 0x1, 0x0}, + {"cfgmt_count_rd_mode", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0}, + {"olif_rdy", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_olif_emem_prog_full_reg[] = + { + {"emem_prog_full_assert", DPP_FIELD_FLAG_RW, 24, 9, 0xb9, 0x0}, + {"emem_prog_full_negate", DPP_FIELD_FLAG_RW, 8, 9, 0xac, 0x0}, + }; +DPP_FIELD_T g_etm_olif_port_order_fifo_full_reg[] = + { + {"port_order_fifo_full_assert", DPP_FIELD_FLAG_RW, 22, 7, 0x32, 0x0}, + {"port_order_fifo_full_negate", DPP_FIELD_FLAG_RW, 6, 7, 0x32, 0x0}, + }; +DPP_FIELD_T g_etm_olif_olif_release_last_reg[] = + { + {"olif_release_last_addr", DPP_FIELD_FLAG_RO, 24, 19, 0x0, 0x0}, + {"olif_release_last_bank", DPP_FIELD_FLAG_RO, 5, 6, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_olif_olif_fifo_empty_state_reg[] = + { + {"qmu_para_fifo_empty", DPP_FIELD_FLAG_RO, 2, 1, 0x1, 0x0}, + {"emem_empty", DPP_FIELD_FLAG_RO, 1, 1, 0x1, 0x0}, + {"imem_empty", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_etm_olif_qmu_olif_release_fc_cnt_reg[] = + { + {"qmu_olif_release_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_olif_olif_qmu_link_fc_cnt_reg[] = + { + {"olif_qmu_link_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_olif_lif0_link_fc_cnt_reg[] = + { + {"lif0_link_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_olif_olif_tmmu_fc_cnt_reg[] = + { + {"olif_tmmu_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_olif_olif_mmu_fc_cnt_reg[] = + { + {"olif_mmu_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_olif_olif_qmu_port_rdy_h_reg[] = + { + {"olif_qmu_port_rdy_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_olif_olif_qmu_port_rdy_l_reg[] = + { + {"olif_qmu_port_rdy_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_olif_lif0_port_rdy_h_reg[] = + { + {"lif0_port_rdy_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_olif_lif0_port_rdy_l_reg[] = + { + {"lif0_port_rdy_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_olif_qmu_olif_rd_sop_cnt_reg[] = + { + {"qmu_olif_rd_sop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_olif_qmu_olif_rd_eop_cnt_reg[] = + { + {"qmu_olif_rd_eop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_olif_qmu_olif_rd_vld_cnt_reg[] = + { + {"qmu_olif_rd_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_olif_qmu_olif_rd_blk_cnt_reg[] = + { + {"qmu_olif_rd_blk_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_olif_mmu_tm_data_sop_cnt_reg[] = + { + {"mmu_tm_data_sop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_olif_mmu_tm_data_eop_cnt_reg[] = + { + {"mmu_tm_data_eop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_olif_mmu_tm_data_vld_cnt_reg[] = + { + {"mmu_tm_data_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_olif_odma_tm_data_sop_cnt_reg[] = + { + {"odma_tm_data_sop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_olif_odma_tm_data_eop_cnt_reg[] = + { + {"odma_tm_data_eop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_olif_odma_tm_deq_vld_cnt_reg[] = + { + {"odma_tm_deq_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_olif_olif_qmu_release_vld_cnt_reg[] = + { + {"olif_qmu_release_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_olif_emem_dat_vld_cnt_reg[] = + { + {"emem_dat_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_olif_imem_dat_vld_cnt_reg[] = + { + {"imem_dat_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_olif_emem_dat_rd_cnt_reg[] = + { + {"emem_dat_rd_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_olif_imem_dat_rd_cnt_reg[] = + { + {"imem_dat_rd_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_olif_qmu_olif_rd_sop_emem_cnt_reg[] = + { + {"qmu_olif_rd_sop_emem_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_olif_qmu_olif_rd_vld_emem_cnt_reg[] = + { + {"qmu_olif_rd_vld_emem_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_olif_cpu_last_wr_addr_reg[] = + { + {"cpu_last_wr_addr", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_olif_cpu_last_wr_data_reg[] = + { + {"cpu_last_wr_data", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_olif_cpu_last_rd_addr_reg[] = + { + {"cpu_last_rd_addr", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_olif_qmu_olif_last_port_reg[] = + { + {"qmu_olif_last_port", DPP_FIELD_FLAG_RO, 6, 7, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_olif_qmu_olif_last_addr_reg[] = + { + {"qmu_olif_last_addr", DPP_FIELD_FLAG_RO, 18, 19, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_olif_qmu_olif_last_bank_reg[] = + { + {"qmu_olif_last_bank", DPP_FIELD_FLAG_RO, 6, 7, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_olif_tm_lif_byte_stat_reg[] = + { + {"tm_lif_byte_stat", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_olif_tm_lif_err_stat_reg[] = + { + {"tm_lif_err_stat", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_port_share_cnt_reg[] = + { + {"port_share_cnt", DPP_FIELD_FLAG_RO, 13, 14, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_total_imem_cnt_reg[] = + { + {"total_imem_cnt", DPP_FIELD_FLAG_RO, 14, 15, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_pp_q_len_reg[] = + { + {"pp_q_len", DPP_FIELD_FLAG_RO, 28, 29, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_sys_q_len_reg[] = + { + {"sys_q_len", DPP_FIELD_FLAG_RO, 28, 29, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cgavd_cfg_error_warning_reg[] = + { + {"error_correction_11", DPP_FIELD_FLAG_RO, 11, 1, 0x0, 0x0}, + {"error_correction_10", DPP_FIELD_FLAG_RO, 10, 1, 0x0, 0x0}, + {"error_correction_9", DPP_FIELD_FLAG_RO, 9, 1, 0x0, 0x0}, + {"error_correction_8", DPP_FIELD_FLAG_RO, 8, 1, 0x0, 0x0}, + {"error_correction_7", DPP_FIELD_FLAG_RO, 7, 1, 0x0, 0x0}, + {"error_correction_6", DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0}, + {"error_correction5", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0}, + {"error_correction_4", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0}, + {"error_correction_3", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0}, + {"error_correction_2", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0}, + {"error_correction_1", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0}, + {"error_correction_0", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_mult_qlen_th_en_reg[] = + { + {"mult_qlen_th", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_mult_qlen_th_reg[] = + { + {"mult_qlen_th", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cgavd_cfg_move_reg[] = + { + {"cfgmt_sys_move_en", DPP_FIELD_FLAG_RW, 2, 1, 0x0, 0x0}, + {"cfgmt_port_move_en", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0}, + {"cfgmt_flow_move_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cfgmt_total_th_reg[] = + { + {"cfgmt_total_th", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cfgmt_port_share_th_reg[] = + { + {"cfgmt_port_share_th", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_sa_unreach_state_reg[] = + { + {"sa_unreach_state", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_mv_port_th_reg[] = + { + {"port_th", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_mv_drop_sp_th_reg[] = + { + {"mvdrop_sp_th", DPP_FIELD_FLAG_RW, 8, 9, 0x100, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cgavd_state_warning_reg[] = + { + {"deq_q_num_warning", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0}, + {"deq_pkt_len_warning", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0}, + {"enq_pkt_dp_warning", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0}, + {"unenq_q_num_warning", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0}, + {"enq_q_num_warning", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0}, + {"enq_pkt_len_warning", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_tmmu_cgavd_dma_fifo_cnt_reg[] = + { + {"tmmu_cgavd_dma_fifo_cnt", DPP_FIELD_FLAG_RO, 8, 9, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_tmmu_cgavd_dma_fifo_cnt_max_reg[] = + { + {"tmmu_cgavd_dma_fifo_cnt_max", DPP_FIELD_FLAG_RO, 8, 9, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_imem_total_cnt_reg[] = + { + {"imem_total_cnt", DPP_FIELD_FLAG_RO, 13, 14, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_imem_total_cnt_max_reg[] = + { + {"imem_total_cnt_max", DPP_FIELD_FLAG_RO, 13, 14, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_flow0_omem_cnt_reg[] = + { + {"flow0_omem_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_flow1_omem_cnt_reg[] = + { + {"flow1_omem_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_flow2_omem_cnt_reg[] = + { + {"flow2_omem_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_flow3_omem_cnt_reg[] = + { + {"flow3_omem_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_flow4_omem_cnt_reg[] = + { + {"flow4_omem_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_appoint_flow_num_message_1_reg[] = + { + {"appoint_flow_num_en_1", DPP_FIELD_FLAG_RW, 15, 1, 0x0, 0x0}, + {"appoint_flow_num_1", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_appoint_flow_num_message_2_reg[] = + { + {"appoint_flow_num_en_2", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"appoint_flow_num_2", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_odma_cgavd_pkt_num_1_reg[] = + { + {"odma_cgavd_pkt_num_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_odma_cgavd_byte_num_1_reg[] = + { + {"odma_cgavd_byte_num_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cgavd_enqueue_pkt_num_1_reg[] = + { + {"cgavd_enqueue_pkt_num_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cgavd_dequeue_pkt_num_1_reg[] = + { + {"cgavd_dequeue_pkt_num_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cgavd_qmu_pkt_imem_num_1_reg[] = + { + {"cgavd_qmu_pkt_imem_num_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cgavd_qmu_pkt_omem_num_1_reg[] = + { + {"cgavd_qmu_pkt_omem_num_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cgavd_qmu_byte_imem_num_1_reg[] = + { + {"cgavd_qmu_byte_imem_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cgavd_qmu_byte_omem_num_1_reg[] = + { + {"cgavd_qmu_byte_omem_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cgavd_qmu_pkt_drop_num_1_reg[] = + { + {"cgavd_qmu_pkt_drop_num_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cgavd_qmu_byte_drop_num_1_reg[] = + { + {"cgavd_qmu_byte_drop_num_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cgavd_qmu_forbid_drop_num_1_reg[] = + { + {"cgavd_qmu_forbid_drop_num_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cgavd_qmu_flow_td_drop_num_1_reg[] = + { + {"cgavd_qmu_flow_td_drop_num_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cgavd_qmu_flow_wred_drop_num_1_reg[] = + { + {"cgavd_qmu_flow_wred_drop_num_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cgavd_qmu_flow_wred_dp_drop_num_1_reg[] = + { + {"cgavd_qmu_flow_wred_dp_drop_num1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cgavd_qmu_pp_td_num_1_reg[] = + { + {"cgavd_qmu_pp_td_num_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cgavd_qmu_pp_wred_drop_num_1_reg[] = + { + {"cgavd_qmu_pp_wred_drop_num_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cgavd_qmu_pp_wred_dp_drop_num_1_reg[] = + { + {"cgavd_qmu_pp_wred_dp_drop_num1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cgavd_qmu_sys_td_drop_num_1_reg[] = + { + {"cgavd_qmu_sys_td_drop_num_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cgavd_qmu_sys_gred_drop_num_1_reg[] = + { + {"cgavd_qmu_sys_gred_drop_num_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cgavd_qmu_sys_gred_dp_drop_num1_reg[] = + { + {"cgavd_qmu_sys_gred_dp_drop_num1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cgavd_qmu_sa_drop_num_1_reg[] = + { + {"cgavd_qmu_sa_drop_num_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cgavd_qmu_move_drop_num_1_reg[] = + { + {"cgavd_qmu_move_drop_num_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cgavd_qmu_tm_mult_drop_num_1_reg[] = + { + {"cgavd_qmu_tm_mult_drop_num_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cgavd_qmu_tm_error_drop_num_1_reg[] = + { + {"cgavd_qmu_tm_error_drop_num_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_odma_cgavd_pkt_num_2_reg[] = + { + {"odma_cgavd_pkt_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_odma_cgavd_byte_num_2_reg[] = + { + {"odma_cgavd_byte_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cgavd_enqueue_pkt_num_2_reg[] = + { + {"cgavd_enqueue_pkt_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cgavd_dequeue_pkt_num_2_reg[] = + { + {"cgavd_dequeue_pkt_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cgavd_qmu_pkt_imem_num_2_reg[] = + { + {"cgavd_qmu_pkt_imem_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cgavd_qmu_pkt_omem_num_2_reg[] = + { + {"cgavd_qmu_pkt_omem_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cgavd_qmu_byte_imem_num_2_reg[] = + { + {"cgavd_qmu_byte_imem_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cgavd_qmu_byte_omem_num_2_reg[] = + { + {"cgavd_qmu_byte_omem_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cgavd_qmu_pkt_drop_num_2_reg[] = + { + {"cgavd_qmu_pkt_drop_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cgavd_qmu_byte_drop_num_2_reg[] = + { + {"cgavd_qmu_byte_drop_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cgavd_qmu_forbid_drop_num_2_reg[] = + { + {"cgavd_qmu_forbid_drop_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cgavd_qmu_flow_td_drop_num_2_reg[] = + { + {"cgavd_qmu_flow_td_drop_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cgavd_qmu_flow_wred_drop_num_2_reg[] = + { + {"cgavd_qmu_flow_wred_drop_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cgavd_qmu_flow_wred_dp_drop_num_2_reg[] = + { + {"cgavd_qmu_flow_wred_dp_drop_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cgavd_qmu_pp_td_num_2_reg[] = + { + {"cgavd_qmu_pp_td_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cgavd_qmu_pp_wred_drop_num_2_reg[] = + { + {"cgavd_qmu_pp_wred_drop_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cgavd_qmu_pp_wred_dp_drop_num_2_reg[] = + { + {"cgavd_qmu_pp_wred_dp_drop_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cgavd_qmu_sys_td_drop_num_2_reg[] = + { + {"cgavd_qmu_sys_td_drop_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cgavd_qmu_sys_gred_drop_num_2_reg[] = + { + {"cgavd_qmu_sys_gred_drop_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cgavd_qmu_sys_gred_dp_drop_num_2_reg[] = + { + {"cgavd_qmu_sys_gred_dp_drop_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cgavd_qmu_sa_drop_num_2_reg[] = + { + {"cgavd_qmu_sa_drop_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cgavd_qmu_move_drop_num_2_reg[] = + { + {"cgavd_qmu_move_drop_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cgavd_qmu_tm_mult_drop_num_2_reg[] = + { + {"cgavd_qmu_tm_mult_drop_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_cgavd_qmu_tm_error_drop_num_2_reg[] = + { + {"cgavd_qmu_tm_error_drop_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_move_flow_th_profile_reg[] = + { + {"move_drop_profile", DPP_FIELD_FLAG_RW, 3, 4, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_cgavd_move_flow_th_reg[] = + { + {"move_drop_flow_th", DPP_FIELD_FLAG_RW, 28, 29, 0x50, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_emem_pd_fifo_aful_th_reg[] = + { + {"emem_pd_fifo_aful_th", DPP_FIELD_FLAG_RW, 7, 8, 0x40, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_dma_data_fifo_aful_th_reg[] = + { + {"dma_data_fifo_aful_th", DPP_FIELD_FLAG_RW, 9, 10, 0x190, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_tmmu_states_0_reg[] = + { + {"tm_odma_pkt_rdy", DPP_FIELD_FLAG_RO, 30, 1, 0x1, 0x0}, + {"dma_data_fifo_empty", DPP_FIELD_FLAG_RO, 29, 1, 0x1, 0x0}, + {"imem_enq_rd_fifo_empty", DPP_FIELD_FLAG_RO, 28, 1, 0x1, 0x0}, + {"imem_enq_drop_fifo_empty", DPP_FIELD_FLAG_RO, 27, 1, 0x1, 0x0}, + {"imem_deq_rd_fifo_empty", DPP_FIELD_FLAG_RO, 26, 1, 0x1, 0x0}, + {"imem_deq_drop_fifo_empty", DPP_FIELD_FLAG_RO, 25, 1, 0x1, 0x0}, + {"wr_cmd_fifo_empty", DPP_FIELD_FLAG_RO, 24, 1, 0x1, 0x0}, + {"cached_pd_fifo_empty", DPP_FIELD_FLAG_RO, 23, 1, 0x1, 0x0}, + {"emem_pd_fifo_empty", DPP_FIELD_FLAG_RO, 22, 1, 0x1, 0x0}, + {"pd_order_fifo_empty", DPP_FIELD_FLAG_RO, 21, 1, 0x1, 0x0}, + {"odma_tm_data_rdy", DPP_FIELD_FLAG_RO, 20, 1, 0x1, 0x0}, + {"odma_tm_discard_rdy", DPP_FIELD_FLAG_RO, 19, 1, 0x1, 0x0}, + {"olif_tmmu_rdy", DPP_FIELD_FLAG_RO, 18, 1, 0x1, 0x0}, + {"mmu_tm_cmd_wr_rdy", DPP_FIELD_FLAG_RO, 17, 1, 0x1, 0x0}, + {"mmu_tm_data_wr_rdy", DPP_FIELD_FLAG_RO, 16, 1, 0x1, 0x0}, + {"mmu_tm_rd_rdy", DPP_FIELD_FLAG_RO, 15, 1, 0x1, 0x0}, + {"mmu_tm_sop_rd_rdy", DPP_FIELD_FLAG_RO, 14, 1, 0x1, 0x0}, + {"qmu_tmmu_sop_data_rdy", DPP_FIELD_FLAG_RO, 13, 1, 0x1, 0x0}, + {"tmmu_cmdsw_imem_release_rdy", DPP_FIELD_FLAG_RO, 12, 1, 0x1, 0x0}, + {"imem_age_release_rdy", DPP_FIELD_FLAG_RO, 11, 1, 0x1, 0x0}, + {"tmmu_qmu_wr_rdy", DPP_FIELD_FLAG_RO, 10, 1, 0x1, 0x0}, + {"tmmu_qmu_rdy_7", DPP_FIELD_FLAG_RO, 9, 1, 0x1, 0x0}, + {"tmmu_qmu_rdy_6", DPP_FIELD_FLAG_RO, 8, 1, 0x1, 0x0}, + {"tmmu_qmu_rdy_5", DPP_FIELD_FLAG_RO, 7, 1, 0x1, 0x0}, + {"tmmu_qmu_rdy_4", DPP_FIELD_FLAG_RO, 6, 1, 0x1, 0x0}, + {"tmmu_qmu_rdy_3", DPP_FIELD_FLAG_RO, 5, 1, 0x1, 0x0}, + {"tmmu_qmu_rdy_2", DPP_FIELD_FLAG_RO, 4, 1, 0x1, 0x0}, + {"tmmu_qmu_rdy_1", DPP_FIELD_FLAG_RO, 3, 1, 0x1, 0x0}, + {"tmmu_qmu_rdy_0", DPP_FIELD_FLAG_RO, 2, 1, 0x1, 0x0}, + {"tmmu_qmu_rd_rdy", DPP_FIELD_FLAG_RO, 1, 1, 0x1, 0x0}, + {"tmmu_qmu_sop_rd_rdy", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_qmu_tmmu_wr_sop_cnt_reg[] = + { + {"qmu_tmmu_wr_sop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_qmu_tmmu_wr_eop_cnt_reg[] = + { + {"qmu_tmmu_wr_eop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_qmu_tmmu_wr_drop_cnt_reg[] = + { + {"qmu_tmmu_wr_drop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_qmu_tmmu_wr_emem_cnt_reg[] = + { + {"qmu_tmmu_wr_emem_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_qmu_tmmu_wr_imem_cnt_reg[] = + { + {"qmu_tmmu_wr_imem_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_tmmu_mmu_wr_sop_cnt_reg[] = + { + {"tmmu_mmu_wr_sop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_tmmu_mmu_wr_eop_cnt_reg[] = + { + {"tmmu_mmu_wr_eop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_qmu_tmmu_rd_sop_cnt_reg[] = + { + {"qmu_tmmu_rd_sop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_qmu_tmmu_rd_eop_cnt_reg[] = + { + {"qmu_tmmu_rd_eop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_qmu_tmmu_rd_drop_cnt_reg[] = + { + {"qmu_tmmu_rd_drop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_qmu_tmmu_rd_emem_cnt_reg[] = + { + {"qmu_tmmu_rd_emem_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_qmu_tmmu_rd_imem_cnt_reg[] = + { + {"qmu_tmmu_rd_imem_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_tmmu_mmu_rd_sop_cnt_reg[] = + { + {"tmmu_mmu_rd_sop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_tmmu_mmu_rd_eop_cnt_reg[] = + { + {"tmmu_mmu_rd_eop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_tmmu_odma_in_sop_cnt_reg[] = + { + {"tmmu_odma_in_sop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_tmmu_odma_in_eop_cnt_reg[] = + { + {"tmmu_odma_in_eop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_tmmu_odma_vld_cnt_reg[] = + { + {"tmmu_odma_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_qmu_pd_in_cnt_reg[] = + { + {"qmu_pd_in_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_tmmu_pd_hit_cnt_reg[] = + { + {"tmmu_pd_hit_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_tmmu_pd_out_cnt_reg[] = + { + {"tmmu_pd_out_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_tmmu_wr_cmd_fifo_wr_cnt_reg[] = + { + {"tmmu_wr_cmd_fifo_wr_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_tmmu_imem_age_cnt_reg[] = + { + {"tmmu_imem_age_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_tmmu_cmdsch_rd_cnt_reg[] = + { + {"tmmu_cmdsch_rd_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_tmmu_cmdsch_drop_cnt_reg[] = + { + {"tmmu_cmdsch_drop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_tmmu_cmdsw_drop_cnt_reg[] = + { + {"tmmu_cmdsw_drop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_tmmu_odma_enq_rd_cnt_reg[] = + { + {"tmmu_odma_enq_rd_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_tmmu_odma_enq_drop_cnt_reg[] = + { + {"tmmu_odma_enq_drop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_tmmu_odma_imem_age_cnt_reg[] = + { + {"tmmu_odma_imem_age_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_tmmu_odma_deq_rd_cnt_reg[] = + { + {"tmmu_odma_deq_rd_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_tmmu_odma_deq_drop_cnt_reg[] = + { + {"tmmu_odma_deq_drop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_olif_tmmu_xoff_cnt_reg[] = + { + {"olif_tmmu_xoff_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_odma_tm_data_xoff_cnt_reg[] = + { + {"odma_tm_data_xoff_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_tm_odma_pkt_xoff_cnt_reg[] = + { + {"tm_odma_pkt_xoff_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_tm_state_3_reg[] = + { + {"tmmu_qmu_rdy_9", DPP_FIELD_FLAG_RO, 1, 1, 0x1, 0x0}, + {"tmmu_qmu_rdy_8", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_cfgmt_pd_cache_cmd_reg[] = + { + {"cfgmt_pd_cache_addr", DPP_FIELD_FLAG_RW, 12, 13, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_cfgmt_pd_cache_rd_done_reg[] = + { + {"cfgmt_pd_cache_rd_done", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_cfgmt_pd_cache_rd_data_0_reg[] = + { + {"cfgmt_pd_cache_rd_data_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_cfgmt_pd_cache_rd_data_1_reg[] = + { + {"cfgmt_pd_cache_rd_data_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_cfgmt_pd_cache_rd_data_2_reg[] = + { + {"cfgmt_pd_cache_rd_data_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_cfgmt_pd_cache_rd_data_3_reg[] = + { + {"cfgmt_pd_cache_rd_data_3", DPP_FIELD_FLAG_RO, 14, 15, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_cfgmt_tmmu_to_odma_para_reg[] = + { + {"cfgmt_tmmu_to_odma_para", DPP_FIELD_FLAG_RO, 25, 26, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_cfgmt_dma_data_fifo_cnt_reg[] = + { + {"cfgmt_dma_data_fifo_cnt", DPP_FIELD_FLAG_RO, 8, 9, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_cfgmt_cache_tag_bit0_offset_reg[] = + { + {"cfgmt_cache_tag_bit0_offset", DPP_FIELD_FLAG_RW, 4, 5, 0xd, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_cfgmt_cache_tag_bit1_offset_reg[] = + { + {"cfgmt_cache_tag_bit1_offset", DPP_FIELD_FLAG_RW, 4, 5, 0xe, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_cfgmt_cache_tag_bit2_offset_reg[] = + { + {"cfgmt_cache_tag_bit2_offset", DPP_FIELD_FLAG_RW, 4, 5, 0xf, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_cfgmt_cache_tag_bit3_offset_reg[] = + { + {"cfgmt_cache_tag_bit3_offset", DPP_FIELD_FLAG_RW, 4, 5, 0x10, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_cfgmt_cache_tag_bit4_offset_reg[] = + { + {"cfgmt_cache_tag_bit4_offset", DPP_FIELD_FLAG_RW, 4, 5, 0x11, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_cfgmt_cache_tag_bit5_offset_reg[] = + { + {"cfgmt_cache_tag_bit5_offset", DPP_FIELD_FLAG_RW, 4, 5, 0x12, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_cfgmt_cache_index_bit0_offset_reg[] = + { + {"cfgmt_cache_index_bit0_offset", DPP_FIELD_FLAG_RW, 4, 5, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_cfgmt_cache_index_bit1_offset_reg[] = + { + {"cfgmt_cache_index_bit1_offset", DPP_FIELD_FLAG_RW, 4, 5, 0x1, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_cfgmt_cache_index_bit2_offset_reg[] = + { + {"cfgmt_cache_index_bit2_offset", DPP_FIELD_FLAG_RW, 4, 5, 0x2, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_cfgmt_cache_index_bit3_offset_reg[] = + { + {"cfgmt_cache_index_bit3_offset", DPP_FIELD_FLAG_RW, 4, 5, 0x3, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_cfgmt_cache_index_bit4_offset_reg[] = + { + {"cfgmt_cache_index_bit4_offset", DPP_FIELD_FLAG_RW, 4, 5, 0x4, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_cfgmt_cache_index_bit5_offset_reg[] = + { + {"cfgmt_cache_index_bit5_offset", DPP_FIELD_FLAG_RW, 4, 5, 0x5, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_cfgmt_cache_index_bit6_offset_reg[] = + { + {"cfgmt_cache_index_bit6_offset", DPP_FIELD_FLAG_RW, 4, 5, 0x6, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_cfgmt_cache_index_bit7_offset_reg[] = + { + {"cfgmt_cache_index_bit7_offset", DPP_FIELD_FLAG_RW, 4, 5, 0x7, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_cfgmt_cache_index_bit8_offset_reg[] = + { + {"cfgmt_cache_index_bit8_offset", DPP_FIELD_FLAG_RW, 4, 5, 0x8, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_cfgmt_cache_index_bit9_offset_reg[] = + { + {"cfgmt_cache_index_bit9_offset", DPP_FIELD_FLAG_RW, 4, 5, 0x9, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_cfgmt_cache_index_bit10_offset_reg[] = + { + {"cfgmt_cache_index_bit10_offset", DPP_FIELD_FLAG_RW, 4, 5, 0xa, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_cfgmt_cache_index_bit11_offset_reg[] = + { + {"cfgmt_cache_index_bit11_offset", DPP_FIELD_FLAG_RW, 4, 5, 0xb, 0x0}, + }; +DPP_FIELD_T g_etm_tmmu_cfgmt_cache_index_bit12_offset_reg[] = + { + {"cfgmt_cache_index_bit12_offset", DPP_FIELD_FLAG_RW, 4, 5, 0xc, 0x0}, + }; +DPP_FIELD_T g_etm_shap_bktfull_fifo_full_flagregister_reg[] = + { + {"bktfull_fifo_full_flag_core", DPP_FIELD_FLAG_RC, 21, 22, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_shap_fifo_full_regregister_reg[] = + { + {"fifo_full_reg", DPP_FIELD_FLAG_RO, 21, 22, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_shap_fifo_empty_regregister_reg[] = + { + {"fifo_empty_reg", DPP_FIELD_FLAG_RO, 21, 22, 0x7, 0x0}, + }; +DPP_FIELD_T g_etm_shap_fifo_almost_full_regregister_reg[] = + { + {"fifo_almost_full_reg", DPP_FIELD_FLAG_RO, 21, 22, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_shap_fifo_almost_empty_regregister_reg[] = + { + {"fifo_almost_empty_reg", DPP_FIELD_FLAG_RO, 21, 22, 0x7, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_credit_space_select_reg[] = + { + {"credit_space_select", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_stat_space_max_reg[] = + { + {"stat_space_max", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_stat_space_min_reg[] = + { + {"stat_space_min", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_stat_space_credit_reg[] = + { + {"stat_space_credit", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_stat_que_step8_credit_reg[] = + { + {"stat_que_step8_credit", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_special_que_reg[] = + { + {"special_que_id", DPP_FIELD_FLAG_RW, 5, 6, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_special_que_credit_reg[] = + { + {"special_que_credit", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_lif_congest_credit_cnt_reg[] = + { + {"lif_congest_credit_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_lif_port_congest_credit_cnt_reg[] = + { + {"lif_port_congest_credit_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_crdt_congest_credit_cnt_reg[] = + { + {"crdt_congest_credit_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_crdt_port_congest_credit_cnt_reg[] = + { + {"crdt_port_congest_credit_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_congest_port_id_reg[] = + { + {"congest_port_id", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_dev_link_control_reg[] = + { + {"dev_link_control", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_crdt_sa_port_rdy_reg[] = + { + {"crdt_sa_port_rdy", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_crdt_congest_mode_select_reg[] = + { + {"crdt_congest_mode_selectr", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_fifo_out_all_crs_normal_cnt_reg[] = + { + {"fifo_out_all_crs_normal_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_fifo_out_all_crs_off_cnt_reg[] = + { + {"fifo_out_all_crs_off_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_fifo_out_que_crs_normal_cnt_reg[] = + { + {"fifo_out_que_crs_normal_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_fifo_out_que_crs_off_cnt_reg[] = + { + {"fifo_out_que_crs_off_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_mode_add_60g_reg[] = + { + {"mode_add_60g", DPP_FIELD_FLAG_RW, 15, 16, 0xff, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_pp_token_add_reg[] = + { + {"pp_token_add_cir", DPP_FIELD_FLAG_RO, 4, 5, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_pp_cir_token_total_dist_cnt_reg[] = + { + {"pp_cir_token_total_dist_counter", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_pp_cir_token_total_dec_cnt_reg[] = + { + {"pp_cir_token_total_dec_counter", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_dev_credit_cnt_reg[] = + { + {"dev_credit_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_no_credit_cnt1_reg[] = + { + {"no_credit_cnt1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_no_credit_cnt2_reg[] = + { + {"no_credit_cnt2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_asm_interval_0_cfg_reg[] = + { + {"asm_interval_0_cfg", DPP_FIELD_FLAG_RW, 21, 22, 0xf, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_asm_interval_1_cfg_reg[] = + { + {"asm_interval_1_cfg", DPP_FIELD_FLAG_RW, 21, 22, 0x1f, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_asm_interval_2_cfg_reg[] = + { + {"asm_interval_2_cfg", DPP_FIELD_FLAG_RW, 21, 22, 0x2f, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_asm_interval_3_cfg_reg[] = + { + {"asm_interval_3_cfg", DPP_FIELD_FLAG_RW, 21, 22, 0x3f, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_asm_interval_4_cfg_reg[] = + { + {"asm_interval_4_cfg", DPP_FIELD_FLAG_RW, 21, 22, 0x4f, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_asm_interval_5cfg_reg[] = + { + {"asm_interval_5_cfg", DPP_FIELD_FLAG_RW, 21, 22, 0x5f, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_asm_interval_6_cfg_reg[] = + { + {"asm_interval_6_cfg", DPP_FIELD_FLAG_RW, 21, 22, 0x6f, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_asm_interval_7_cfg_reg[] = + { + {"asm_interval_7_cfg", DPP_FIELD_FLAG_RW, 21, 22, 0x7f, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_crdt_total_congest_mode_cfg_reg[] = + { + {"crdt_total_congest_mode_cfg", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_rci_fifo_ini_deep_cfg_reg[] = + { + {"rci_fifo_ini_deep_cfg", DPP_FIELD_FLAG_RW, 8, 9, 0x1f4, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_crdt_ecc_reg[] = + { + {"seinfo_wfq_single_ecc_err", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0}, + {"seinfo_wfq_double_ecc_err", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0}, + {"seinfo_fq_single_ecc_err", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0}, + {"seinfo_fq_double_ecc_err", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0}, + {"ecc_bypass", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_ucn_asm_rdy_shield_en_reg[] = + { + {"ucn_rdy_shield_en", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"asm_rdy_shield_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_ucn_asm_rdy_reg[] = + { + {"ucn_rdy", DPP_FIELD_FLAG_RO, 1, 1, 0x1, 0x0}, + {"asm_rdy", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_rci_grade_reg[] = + { + {"rci_grade", DPP_FIELD_FLAG_RO, 2, 3, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_crdt_rci_value_r_reg[] = + { + {"crdt_rci_value_r", DPP_FIELD_FLAG_RO, 11, 12, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_crdt_interval_now_reg[] = + { + {"crdt_interval_now", DPP_FIELD_FLAG_RO, 21, 22, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_crs_sheild_flow_id_cfg_reg[] = + { + {"crs_sheild_flow_id_cfg", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_crs_sheild_en_cfg_reg[] = + { + {"crs_sheild_en_cfg", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_crs_sheild_value_cfg_reg[] = + { + {"crs_sheild_value_cfg", DPP_FIELD_FLAG_RW, 1, 2, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_test_token_calc_ctrl_reg[] = + { + {"test_token_calc_state", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0}, + {"test_token_calc_trigger", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_test_token_sample_cycle_num_reg[] = + { + {"sample_cycle_num", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_q_state_0_7_reg[] = + { + {"q_token_state_7", DPP_FIELD_FLAG_RO, 29, 2, 0x0, 0x0}, + {"q_token_state_6", DPP_FIELD_FLAG_RO, 25, 2, 0x0, 0x0}, + {"q_token_state_5", DPP_FIELD_FLAG_RO, 21, 2, 0x0, 0x0}, + {"q_token_state_4", DPP_FIELD_FLAG_RO, 17, 2, 0x0, 0x0}, + {"q_token_state_3", DPP_FIELD_FLAG_RO, 13, 2, 0x0, 0x0}, + {"q_token_state_2", DPP_FIELD_FLAG_RO, 9, 2, 0x0, 0x0}, + {"q_token_state_1", DPP_FIELD_FLAG_RO, 5, 2, 0x0, 0x0}, + {"q_token_state_0", DPP_FIELD_FLAG_RO, 1, 2, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_crdt_q_state_8_15_reg[] = + { + {"q_token_state_15", DPP_FIELD_FLAG_RO, 29, 2, 0x0, 0x0}, + {"q_token_state_14", DPP_FIELD_FLAG_RO, 25, 2, 0x0, 0x0}, + {"q_token_state_13", DPP_FIELD_FLAG_RO, 21, 2, 0x0, 0x0}, + {"q_token_state_12", DPP_FIELD_FLAG_RO, 17, 2, 0x0, 0x0}, + {"q_token_state_11", DPP_FIELD_FLAG_RO, 13, 2, 0x0, 0x0}, + {"q_token_state_10", DPP_FIELD_FLAG_RO, 9, 2, 0x0, 0x0}, + {"q_token_state_9", DPP_FIELD_FLAG_RO, 5, 2, 0x0, 0x0}, + {"q_token_state_8", DPP_FIELD_FLAG_RO, 1, 2, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_csw_csch_rd_cmd_cnt_reg[] = + { + {"csw_csch_rd_cmd_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_csw_csch_rd_sop_cnt_reg[] = + { + {"csw_csch_rd_sop_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_csw_csch_rd_eop_cnt_reg[] = + { + {"csw_csch_rd_eop_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_csw_csch_rd_drop_cnt_reg[] = + { + {"csw_csch_rd_drop_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_csch_mmu_rd_cmd_cnt_reg[] = + { + {"csch_mmu_rd_cmd_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_csch_mmu_rd_sop_cnt_reg[] = + { + {"csch_mmu_rd_sop_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_csch_mmu_rd_eop_cnt_reg[] = + { + {"csch_mmu_rd_eop_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_csch_mmu_rd_drop_cnt_reg[] = + { + {"csch_mmu_rd_drop_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qcfg_qsch_crs_filter_reg[] = + { + {"qcfg_qsch_crs_filter", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qcfg_qsch_crs_force_en_reg[] = + { + {"qcfg_qsch_crs_force_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qcfg_qsch_crs_force_qnum_reg[] = + { + {"qcfg_qsch_crs_force_qnum", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qcfg_qsch_crs_force_crs_reg[] = + { + {"qcfg_qsch_crs_force_crs", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfgmt_oshp_sgmii_shap_mode_reg[] = + { + {"cfgmt_oshp_sgmii_shap_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfgmt_qmu_sashap_en_reg[] = + { + {"cfgmt_qmu_sashap_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfgmt_sashap_token_max_reg[] = + { + {"cfgmt_sashap_token_max", DPP_FIELD_FLAG_RW, 31, 32, 0x2000, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfgmt_sashap_token_min_reg[] = + { + {"cfgmt_sashap_token_min", DPP_FIELD_FLAG_RW, 31, 32, 0xffffe000, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_q3lbaddrate_reg[] = + { + {"cfg_qsch_q3lbaddrate", DPP_FIELD_FLAG_RW, 27, 28, 0x80, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_q012lbaddrate_reg[] = + { + {"cfg_qsch_q012lbaddrate", DPP_FIELD_FLAG_RW, 27, 28, 0x80, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_q3creditlbmaxcnt_reg[] = + { + {"cfg_qsch_q3creditlbmaxcnt", DPP_FIELD_FLAG_RW, 7, 8, 0x80, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_q012creditlbmaxcnt_reg[] = + { + {"cfg_qsch_q012creditlbmaxcnt", DPP_FIELD_FLAG_RW, 7, 8, 0x80, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_mul_token_gen_num_reg[] = + { + {"cfg_qsch_mul_token_gen_num", DPP_FIELD_FLAG_RW, 7, 8, 0x1, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_q3_credit_lb_control_en_reg[] = + { + {"cfg_qsch_q3_credit_lb_control_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_q012_credit_lb_control_en_reg[] = + { + {"cfg_qsch_q012_credit_lb_control_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_sp_dwrr_en_reg[] = + { + {"cfg_qsch_sp_dwrr_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_q01_attach_en_reg[] = + { + {"cfg_qsch_q01_attach_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_w0_reg[] = + { + {"cfg_qsch_w0", DPP_FIELD_FLAG_RW, 6, 7, 0x10, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_w1_reg[] = + { + {"cfg_qsch_w1", DPP_FIELD_FLAG_RW, 6, 7, 0x20, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_w2_reg[] = + { + {"cfg_qsch_w2", DPP_FIELD_FLAG_RW, 6, 7, 0x40, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_lkybktmaxcnt1_reg[] = + { + {"cfg_qsch_lkybktmaxcnt1", DPP_FIELD_FLAG_RW, 31, 32, 0x80, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_lkybktmaxcnt2_reg[] = + { + {"cfg_qsch_lkybktmaxcnt2", DPP_FIELD_FLAG_RW, 31, 32, 0x80, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_lkybktdcrrate1_reg[] = + { + {"cfg_qsch_lkybktdcrrate1", DPP_FIELD_FLAG_RW, 31, 32, 0x80000020, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_lkybktdcrrate2_reg[] = + { + {"cfg_qsch_lkybktdcrrate2", DPP_FIELD_FLAG_RW, 31, 32, 0x80000010, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_lkybktdcrrate3_reg[] = + { + {"cfg_qsch_lkybktdcrrate3", DPP_FIELD_FLAG_RW, 31, 32, 0x80000004, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_lkybktmaxcnt3_reg[] = + { + {"cfg_qsch_lkybktmaxcnt3", DPP_FIELD_FLAG_RW, 31, 32, 0x80, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_qmu_mul_auto_sa_version_reg[] = + { + {"cfg_qsch_qmu_mul_auto_sa_version", DPP_FIELD_FLAG_RW, 4, 5, 0x4, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_sa_credit_value_0_reg[] = + { + {"cfg_qsch_sa_credit_value_0", DPP_FIELD_FLAG_RW, 13, 14, 0x85, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_sa_credit_value_1_reg[] = + { + {"cfg_qsch_sa_credit_value_1", DPP_FIELD_FLAG_RW, 13, 14, 0x29a, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_sa_credit_value_2_reg[] = + { + {"cfg_qsch_sa_credit_value_2", DPP_FIELD_FLAG_RW, 13, 14, 0x190, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_sa_credit_value_3_reg[] = + { + {"cfg_qsch_sa_credit_value_3", DPP_FIELD_FLAG_RW, 13, 14, 0x4e2, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_sa_credit_value_4_reg[] = + { + {"cfg_qsch_sa_credit_value_4", DPP_FIELD_FLAG_RW, 13, 14, 0x5fe, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_sa_credit_value_5_reg[] = + { + {"cfg_qsch_sa_credit_value_5", DPP_FIELD_FLAG_RW, 13, 14, 0x8a0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_sa_credit_value_6_reg[] = + { + {"cfg_qsch_sa_credit_value_6", DPP_FIELD_FLAG_RW, 13, 14, 0x8a0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_sa_credit_value_7_reg[] = + { + {"cfg_qsch_sa_credit_value_7", DPP_FIELD_FLAG_RW, 13, 14, 0x8a0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_remote_credit_fifo_almost_full_th_reg[] = + { + {"cfg_qsch_remote_credit_fifo_almost_full_th", DPP_FIELD_FLAG_RW, 10, 11, 0x7ff, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_auto_credit_fifo_almost_full_th_reg[] = + { + {"cfg_qsch_auto_credit_fifo_almost_full_th", DPP_FIELD_FLAG_RW, 5, 6, 0x1c, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_q3_credit_fifo_almost_full_th_reg[] = + { + {"cfg_qsch_q3_credit_fifo_almost_full_th", DPP_FIELD_FLAG_RW, 5, 6, 0x1c, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_q012_credit_fifo_almost_full_th_reg[] = + { + {"cfg_qsch_q012_credit_fifo_almost_full_th", DPP_FIELD_FLAG_RW, 5, 6, 0x1c, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_mul_fc_res_en_reg[] = + { + {"cfg_qsch_mul_fc_res_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfgmt_mul_ovf_udf_flg_query_reg[] = + { + {"qsch_cfg_remote_credit_fifo_full", DPP_FIELD_FLAG_RO, 18, 1, 0x0, 0x0}, + {"qsch_cfg_remote_credit_fifo_empty", DPP_FIELD_FLAG_RO, 17, 1, 0x1, 0x0}, + {"qsch_cfg_remote_credit_fifo_overflow", DPP_FIELD_FLAG_RO, 16, 1, 0x0, 0x0}, + {"qsch_cfg_remote_credit_fifo_underflow", DPP_FIELD_FLAG_RO, 15, 1, 0x0, 0x0}, + {"qsch_cfg_auto_credit_fifo_full", DPP_FIELD_FLAG_RO, 14, 1, 0x0, 0x0}, + {"qsch_cfg_auto_credit_fifo_empty", DPP_FIELD_FLAG_RO, 13, 1, 0x1, 0x0}, + {"qsch_cfg_auto_credit_fifo_overflow", DPP_FIELD_FLAG_RO, 12, 1, 0x0, 0x0}, + {"qsch_cfg_auto_credit_fifo_underflow", DPP_FIELD_FLAG_RO, 11, 1, 0x0, 0x0}, + {"qsch_cfg_q3_credit_fifo_full", DPP_FIELD_FLAG_RO, 10, 1, 0x0, 0x0}, + {"qsch_cfg_q3_credit_fifo_empty", DPP_FIELD_FLAG_RO, 9, 1, 0x1, 0x0}, + {"qsch_cfg_q3_credit_fifo_overflow", DPP_FIELD_FLAG_RO, 8, 1, 0x0, 0x0}, + {"qsch_cfg_q3_credit_fifo_underflow", DPP_FIELD_FLAG_RO, 7, 1, 0x0, 0x0}, + {"qsch_cfg_q012_credit_fifo_full", DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0}, + {"qsch_cfg_q012_credit_fifo_empty", DPP_FIELD_FLAG_RO, 5, 1, 0x1, 0x0}, + {"qsch_cfg_q012_credit_fifo_overflow", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0}, + {"qsch_cfg_q012_credit_fifo_underflow", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0}, + {"qsch_cfg_lkybktoverflow1", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0}, + {"qsch_cfg_lkybktoverflow2", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0}, + {"qsch_cfg_lkybktoverflow3", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfgmt_mul_cng_flg_query_reg[] = + { + {"qsch_cfg_q3cngflag", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0}, + {"qsch_cfg_q012cngflag", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0}, + {"qsch_cfg_cngflag1", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0}, + {"qsch_cfg_cngflag2", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0}, + {"qsch_cfg_cngflag3", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qsch_cfg_lkybktval1_reg[] = + { + {"qsch_cfg_lkybktval1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qsch_cfg_lkybktval2_reg[] = + { + {"qsch_cfg_lkybktval2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qsch_cfg_lkybktval3_reg[] = + { + {"qsch_cfg_lkybktval3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qsch_cfg_q3lbval_reg[] = + { + {"qsch_cfg_q3lbval", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qsch_cfg_q012lbval_reg[] = + { + {"qsch_cfg_q012lbval", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qlist_cfgmt_ram_ecc_err2_reg[] = + { + {"qlist_imem_pd_ram_single_ecc_err", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"qlist_imem_pd_ram_double_ecc_err", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"qlist_imem_up_ptr_ram_single_ecc_err", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"qlist_imem_up_ptr_ram_double_ecc_err", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"qlist_imem_down_ptr_ram_single_ecc_err", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"qlist_imem_down_ptr_ram_double_ecc_err", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"cmdsw_sop_fifo_single_ecc_err", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"cmdsw_sop_fifo_double_ecc_err", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"cmdsw_nsop_fifo_single_ecc_err", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"cmdsw_nsop_fifo_double_ecc_err", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"cmdsw_mmudat_fifo_single_ecc_err", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"cmdsw_mmudat_fifo_double_ecc_err", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"qlist_rd_release_fwft_single_ecc_err", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"qlist_rd_release_fwft_double_ecc_err", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"qlist_drop_imem_fwft_single_ecc_err", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"qlist_drop_imem_fwft_double_ecc_err", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_csch_aged_cmd_cnt_reg[] = + { + {"csch_aged_cmd_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_csch_qcfg_csch_congest_cnt_reg[] = + { + {"csch_qcfg_csch_congest_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_csch_qcfg_qlist_csch_sop_cnt_reg[] = + { + {"csch_qcfg_qlist_csch_sop_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_csch_qcfg_qlist_csch_eop_cnt_reg[] = + { + {"csch_qcfg_qlist_csch_eop_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_csch_qcfg_csch_csw_sop_cnt_reg[] = + { + {"csch_qcfg_csch_csw_sop_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_csch_qcfg_csch_csw_eop_cnt_reg[] = + { + {"csch_qcfg_csch_csw_eop_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_csch_qcfg_qlist_csch_drop_cnt_reg[] = + { + {"csch_qcfg_qlist_csch_drop_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_csch_qcfg_csch_csw_drop_cnt_reg[] = + { + {"csch_qcfg_csch_csw_drop_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_csw_mmu_sop_cmd_cnt_reg[] = + { + {"csw_mmu_sop_cmd_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_mmu_csw_sop_data_cnt_reg[] = + { + {"mmu_csw_sop_data_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_csw_qsch_feedb_cnt_reg[] = + { + {"csw_qsch_feedb_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qmu_crdt_port_fc_cnt_reg[] = + { + {"qmu_crdt_port_fc_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_csch_r_block_cnt_reg[] = + { + {"csch_r_block_cnt", DPP_FIELD_FLAG_RO, 16, 17, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qcfg_qlist_qds_head_rd_reg[] = + { + {"qcfg_qlist_qds_head_rd", DPP_FIELD_FLAG_RO, 18, 19, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qcfg_qlist_qds_tail_rd_reg[] = + { + {"qcfg_qlist_qds_tail_rd", DPP_FIELD_FLAG_RO, 18, 19, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qcfg_qlist_ept_rd_reg[] = + { + {"qcfg_qlist_ept_rd", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qcfg_qlist_age_flag_rd_reg[] = + { + {"qcfg_qlist_age_flag_rd", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qcfg_qlist_cti_rd_reg[] = + { + {"qcfg_qlist_cti_rd", DPP_FIELD_FLAG_RO, 3, 4, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qcfg_qlist_cto_rd_reg[] = + { + {"qcfg_qlist_cto_rd", DPP_FIELD_FLAG_RO, 3, 4, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qcfg_qlist_chk_rd_reg[] = + { + {"qcfg_qlist_chk_rd", DPP_FIELD_FLAG_RO, 18, 19, 0x1, 0x1}, + }; +DPP_FIELD_T g_etm_qmu_qcfg_qlist_nod_rd_reg[] = + { + {"qcfg_qlist_nod_rd", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qcfg_qlist_biu_rd_reg[] = + { + {"qcfg_qlist_biu_rd", DPP_FIELD_FLAG_RO, 4, 5, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qsch_r_wlist_flag_reg[] = + { + {"qsch_r_wlist_flag", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qcfg_crs_flg_rd_reg[] = + { + {"qcfg_crs_flg_rd", DPP_FIELD_FLAG_RO, 8, 9, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfgmt_qmu_imem_age_qds_reg[] = + { + {"cfgmt_qmu_imem_tp", DPP_FIELD_FLAG_RO, 30, 15, 0x0, 0x0}, + {"cfgmt_qmu_imem_hp", DPP_FIELD_FLAG_RO, 13, 14, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfgmt_qmu_imem_age_qlen_reg[] = + { + {"cfgmt_qmu_imem_no_empty", DPP_FIELD_FLAG_RO, 16, 1, 0x0, 0x0}, + {"cfgmt_qmu_imem_qlen", DPP_FIELD_FLAG_RO, 13, 14, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfgmt_qmu_imem_pd_ram_low_reg[] = + { + {"cfgmt_qmu_imem_pd_ram_low", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfgmt_qmu_imem_pd_ram_high_reg[] = + { + {"cfgmt_qmu_imem_pd_ram_high", DPP_FIELD_FLAG_RO, 3, 4, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfgmt_qmu_imem_up_ptr_reg[] = + { + {"cfgmt_qmu_imem_up_ptr", DPP_FIELD_FLAG_RO, 13, 14, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfgmt_qmu_imem_down_ptr_reg[] = + { + {"cfgmt_qmu_imem_down_ptr", DPP_FIELD_FLAG_RO, 13, 14, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfgmt_qmu_imem_age_flag_reg[] = + { + {"cfgmt_qmu_imem_age_flag", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_lkybkt2cngth_reg[] = + { + {"cfg_qsch_lkybkt2cngth", DPP_FIELD_FLAG_RW, 31, 32, 0x40, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_lkybkt1cngth_reg[] = + { + {"cfg_qsch_lkybkt1cngth", DPP_FIELD_FLAG_RW, 31, 32, 0x40, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_lkybkt3cngth_reg[] = + { + {"cfg_qsch_lkybkt3cngth", DPP_FIELD_FLAG_RW, 31, 32, 0x40, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_rm_mul_mcn1_credit_value_reg[] = + { + {"cfg_qsch_rm_mul_mcn1_credit_value", DPP_FIELD_FLAG_RW, 13, 14, 0x5fe, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_rm_mul_mcn2_credit_value_reg[] = + { + {"cfg_qsch_rm_mul_mcn2_credit_value", DPP_FIELD_FLAG_RW, 13, 14, 0x5fe, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_rm_mul_mcn3_credit_value_reg[] = + { + {"cfg_qsch_rm_mul_mcn3_credit_value", DPP_FIELD_FLAG_RW, 13, 14, 0x5fe, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_rm_mul_mcn1_rand_ansr_seed_reg[] = + { + {"cfg_qsch_rm_mul_mcn1_rand_mchsm_en", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, + {"cfg_qsch_rm_mul_mcn1_rand_ansr_seed", DPP_FIELD_FLAG_RW, 7, 8, 0x1, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_rm_mul_mcn2_rand_ansr_seed_reg[] = + { + {"cfg_qsch_rm_mul_mcn2_rand_mchsm_en", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, + {"cfg_qsch_rm_mul_mcn2_rand_ansr_seed", DPP_FIELD_FLAG_RW, 7, 8, 0x1, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_rm_mul_mcn3_rand_ansr_seed_reg[] = + { + {"cfg_qsch_rm_mul_mcn3_rand_mchsm_en", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, + {"cfg_qsch_rm_mul_mcn3_rand_ansr_seed", DPP_FIELD_FLAG_RW, 7, 8, 0x1, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_rm_mul_mcn1_rand_ansr_th_reg[] = + { + {"cfg_qsch_rm_mul_mcn1_rand_ansr_th", DPP_FIELD_FLAG_RW, 7, 8, 0x80, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_rm_mul_mcn2_rand_ansr_th_reg[] = + { + {"cfg_qsch_rm_mul_mcn2_rand_ansr_th", DPP_FIELD_FLAG_RW, 7, 8, 0x80, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_rm_mul_mcn3_rand_ansr_th_reg[] = + { + {"cfg_qsch_rm_mul_mcn3_rand_ansr_th", DPP_FIELD_FLAG_RW, 7, 8, 0x80, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_rm_mul_mcn1_rand_hold_base_reg[] = + { + {"cfg_qsch_rm_mul_mcn1_rand_mchsm_en", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0}, + {"cfg_qsch_rm_mul_mcn1_rand_hold_base", DPP_FIELD_FLAG_RW, 23, 24, 0x1000, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_rm_mul_mcn2_rand_hold_base_reg[] = + { + {"cfg_qsch_rm_mul_mcn2_rand_mchsm_en", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0}, + {"cfg_qsch_rm_mul_mcn2_rand_hold_base", DPP_FIELD_FLAG_RW, 23, 24, 0x1000, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_rm_mul_mcn3_rand_hold_base_reg[] = + { + {"cfg_qsch_rm_mul_mcn3_rand_mchsm_en", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0}, + {"cfg_qsch_rm_mul_mcn3_rand_hold_base", DPP_FIELD_FLAG_RW, 23, 24, 0x1000, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_rm_mul_mcn1_rand_sel_mask_reg[] = + { + {"cfg_qsch_rm_mul_mcn1_rand_sel_mask", DPP_FIELD_FLAG_RW, 8, 9, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_rm_mul_mcn2_rand_sel_mask_reg[] = + { + {"cfg_qsch_rm_mul_mcn2_rand_sel_mask", DPP_FIELD_FLAG_RW, 8, 9, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_rm_mul_mcn3_rand_sel_mask_reg[] = + { + {"cfg_qsch_rm_mul_mcn3_rand_sel_mask", DPP_FIELD_FLAG_RW, 8, 9, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_rm_mul_mcn1_rand_sel_seed_reg0_reg[] = + { + {"rm_mul_mcn1_rand_sel_seed7", DPP_FIELD_FLAG_RW, 31, 4, 0x8, 0x0}, + {"rm_mul_mcn1_rand_sel_seed6", DPP_FIELD_FLAG_RW, 27, 4, 0x7, 0x0}, + {"rm_mul_mcn1_rand_sel_seed5", DPP_FIELD_FLAG_RW, 23, 4, 0x6, 0x0}, + {"rm_mul_mcn1_rand_sel_seed4", DPP_FIELD_FLAG_RW, 19, 4, 0x5, 0x0}, + {"rm_mul_mcn1_rand_sel_seed3", DPP_FIELD_FLAG_RW, 15, 4, 0x4, 0x0}, + {"rm_mul_mcn1_rand_sel_seed2", DPP_FIELD_FLAG_RW, 11, 4, 0x3, 0x0}, + {"rm_mul_mcn1_rand_sel_seed1", DPP_FIELD_FLAG_RW, 7, 4, 0x2, 0x0}, + {"rm_mul_mcn1_rand_sel_seed0", DPP_FIELD_FLAG_RW, 3, 4, 0x1, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_rm_mul_mcn1_rand_sel_seed_reg1_reg[] = + { + {"rm_mul_mcn1_rand_sel_seed8", DPP_FIELD_FLAG_RW, 3, 4, 0x9, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_rm_mul_mcn2_rand_sel_seed_reg0_reg[] = + { + {"rm_mul_mcn2_rand_sel_seed7", DPP_FIELD_FLAG_RW, 31, 4, 0x8, 0x0}, + {"rm_mul_mcn2_rand_sel_seed6", DPP_FIELD_FLAG_RW, 27, 4, 0x7, 0x0}, + {"rm_mul_mcn2_rand_sel_seed5", DPP_FIELD_FLAG_RW, 23, 4, 0x6, 0x0}, + {"rm_mul_mcn2_rand_sel_seed4", DPP_FIELD_FLAG_RW, 19, 4, 0x5, 0x0}, + {"rm_mul_mcn2_rand_sel_seed3", DPP_FIELD_FLAG_RW, 15, 4, 0x4, 0x0}, + {"rm_mul_mcn2_rand_sel_seed2", DPP_FIELD_FLAG_RW, 11, 4, 0x3, 0x0}, + {"rm_mul_mcn2_rand_sel_seed1", DPP_FIELD_FLAG_RW, 7, 4, 0x2, 0x0}, + {"rm_mul_mcn2_rand_sel_seed0", DPP_FIELD_FLAG_RW, 3, 4, 0x1, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_rm_mul_mcn2_rand_sel_seed_reg1_reg[] = + { + {"rm_mul_mcn2_rand_sel_seed8", DPP_FIELD_FLAG_RW, 3, 4, 0x9, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_rm_mul_mcn3_rand_sel_seed_reg0_reg[] = + { + {"rm_mul_mcn3_rand_sel_seed7", DPP_FIELD_FLAG_RW, 31, 4, 0x8, 0x0}, + {"rm_mul_mcn3_rand_sel_seed6", DPP_FIELD_FLAG_RW, 27, 4, 0x7, 0x0}, + {"rm_mul_mcn3_rand_sel_seed5", DPP_FIELD_FLAG_RW, 23, 4, 0x6, 0x0}, + {"rm_mul_mcn3_rand_sel_seed4", DPP_FIELD_FLAG_RW, 19, 4, 0x5, 0x0}, + {"rm_mul_mcn3_rand_sel_seed3", DPP_FIELD_FLAG_RW, 15, 4, 0x4, 0x0}, + {"rm_mul_mcn3_rand_sel_seed2", DPP_FIELD_FLAG_RW, 11, 4, 0x3, 0x0}, + {"rm_mul_mcn3_rand_sel_seed1", DPP_FIELD_FLAG_RW, 7, 4, 0x2, 0x0}, + {"rm_mul_mcn3_rand_sel_seed0", DPP_FIELD_FLAG_RW, 3, 4, 0x1, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_rm_mul_mcn3_rand_sel_seed_reg1_reg[] = + { + {"rm_mul_mcn3_rand_sel_seed8", DPP_FIELD_FLAG_RW, 3, 4, 0x9, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_rm_mul_mcn1_step_wait_th1_reg[] = + { + {"cfg_qsch_rm_mul_mcn1_step_wait_th1", DPP_FIELD_FLAG_RW, 15, 16, 0x80, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_rm_mul_mcn1_step_wait_th2_reg[] = + { + {"cfg_qsch_rm_mul_mcn1_step_wait_th2", DPP_FIELD_FLAG_RW, 15, 16, 0x80, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_rm_mul_mcn1_step_wait_th3_reg[] = + { + {"cfg_qsch_rm_mul_mcn1_step_wait_th3", DPP_FIELD_FLAG_RW, 15, 16, 0x80, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_rm_mul_mcn1_step_wait_th4_reg[] = + { + {"cfg_qsch_rm_mul_mcn1_step_wait_th4", DPP_FIELD_FLAG_RW, 15, 16, 0x80, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_rm_mul_mcn1_step_wait_th5_reg[] = + { + {"cfg_qsch_rm_mul_mcn1_step_wait_th5", DPP_FIELD_FLAG_RW, 15, 16, 0x80, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_rm_mul_mcn1_step_wait_th6_reg[] = + { + {"cfg_qsch_rm_mul_mcn1_step_wait_th6", DPP_FIELD_FLAG_RW, 15, 16, 0x80, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_rm_mul_mcn1_step_wait_th7_reg[] = + { + {"cfg_qsch_rm_mul_mcn1_step_wait_th7", DPP_FIELD_FLAG_RW, 15, 16, 0x80, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_rm_mul_mcn2_step_wait_th1_reg[] = + { + {"cfg_qsch_rm_mul_mcn2_step_wait_th1", DPP_FIELD_FLAG_RW, 15, 16, 0x80, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_rm_mul_mcn2_step_wait_th2_reg[] = + { + {"cfg_qsch_rm_mul_mcn2_step_wait_th2", DPP_FIELD_FLAG_RW, 15, 16, 0x80, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_rm_mul_mcn2_step_wait_th3_reg[] = + { + {"cfg_qsch_rm_mul_mcn2_step_wait_th3", DPP_FIELD_FLAG_RW, 15, 16, 0x80, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_rm_mul_mcn2_step_wait_th4_reg[] = + { + {"cfg_qsch_rm_mul_mcn2_step_wait_th4", DPP_FIELD_FLAG_RW, 15, 16, 0x80, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_rm_mul_mcn2_step_wait_th5_reg[] = + { + {"cfg_qsch_rm_mul_mcn2_step_wait_th5", DPP_FIELD_FLAG_RW, 15, 16, 0x80, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_rm_mul_mcn2_step_wait_th6_reg[] = + { + {"cfg_qsch_rm_mul_mcn2_step_wait_th6", DPP_FIELD_FLAG_RW, 15, 16, 0x80, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_rm_mul_mcn2_step_wait_th7_reg[] = + { + {"cfg_qsch_rm_mul_mcn2_step_wait_th7", DPP_FIELD_FLAG_RW, 15, 16, 0x80, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_rm_mul_mcn3_step_wait_th1_reg[] = + { + {"cfg_qsch_rm_mul_mcn3_step_wait_th1", DPP_FIELD_FLAG_RW, 15, 16, 0x80, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_rm_mul_mcn3_step_wait_th2_reg[] = + { + {"cfg_qsch_rm_mul_mcn3_step_wait_th2", DPP_FIELD_FLAG_RW, 15, 16, 0x80, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_rm_mul_mcn3_step_wait_th3_reg[] = + { + {"cfg_qsch_rm_mul_mcn3_step_wait_th3", DPP_FIELD_FLAG_RW, 15, 16, 0x80, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_rm_mul_mcn3_step_wait_th4_reg[] = + { + {"cfg_qsch_rm_mul_mcn3_step_wait_th4", DPP_FIELD_FLAG_RW, 15, 16, 0x80, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_rm_mul_mcn3_step_wait_th5_reg[] = + { + {"cfg_qsch_rm_mul_mcn3_step_wait_th5", DPP_FIELD_FLAG_RW, 15, 16, 0x80, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_rm_mul_mcn3_step_wait_th6_reg[] = + { + {"cfg_qsch_rm_mul_mcn3_step_wait_th6", DPP_FIELD_FLAG_RW, 15, 16, 0x80, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_rm_mul_mcn3step_wait_th7_reg[] = + { + {"cfg_qsch_rm_mul_mcn3_step_wait_th7", DPP_FIELD_FLAG_RW, 15, 16, 0x80, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate0_reg[] = + { + {"cfg_qsch_mulcrdcntrate0", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate1_reg[] = + { + {"cfg_qsch_mulcrdcntrate1", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate2_reg[] = + { + {"cfg_qsch_mulcrdcntrate2", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate3_reg[] = + { + {"cfg_qsch_mulcrdcntrate3", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate4_reg[] = + { + {"cfg_qsch_mulcrdcntrate4", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate5_reg[] = + { + {"cfg_qsch_mulcrdcntrate5", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate6_reg[] = + { + {"cfg_qsch_mulcrdcntrate6", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate7_reg[] = + { + {"cfg_qsch_mulcrdcntrate7", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate8_reg[] = + { + {"cfg_qsch_mulcrdcntrate8", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate9_reg[] = + { + {"cfg_qsch_mulcrdcntrate9", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate10_reg[] = + { + {"cfg_qsch_mulcrdcntrate10", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate11_reg[] = + { + {"cfg_qsch_mulcrdcntrate11", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate12_reg[] = + { + {"cfg_qsch_mulcrdcntrate12", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate13_reg[] = + { + {"cfg_qsch_mulcrdcntrate13", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate14_reg[] = + { + {"cfg_qsch_mulcrdcntrate14", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate15_reg[] = + { + {"cfg_qsch_mulcrdcntrate15", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate16_reg[] = + { + {"cfg_qsch_mulcrdcntrate16", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate17_reg[] = + { + {"cfg_qsch_mulcrdcntrate17", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate18_reg[] = + { + {"cfg_qsch_mulcrdcntrate18", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate19_reg[] = + { + {"cfg_qsch_mulcrdcntrate19", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate20_reg[] = + { + {"cfg_qsch_mulcrdcntrate20", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate21_reg[] = + { + {"cfg_qsch_mulcrdcntrate21", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate22_reg[] = + { + {"cfg_qsch_mulcrdcntrate22", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate23_reg[] = + { + {"cfg_qsch_mulcrdcntrate23", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate24_reg[] = + { + {"cfg_qsch_mulcrdcntrate24", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate25_reg[] = + { + {"cfg_qsch_mulcrdcntrate25", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate26_reg[] = + { + {"cfg_qsch_mulcrdcntrate26", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate27_reg[] = + { + {"cfg_qsch_mulcrdcntrate27", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate28_reg[] = + { + {"cfg_qsch_mulcrdcntrate28", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate29_reg[] = + { + {"cfg_qsch_mulcrdcntrate29", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate30_reg[] = + { + {"cfg_qsch_mulcrdcntrate30", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate31_reg[] = + { + {"cfg_qsch_mulcrdcntrate31", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate32_reg[] = + { + {"cfg_qsch_mulcrdcntrate32", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate33_reg[] = + { + {"cfg_qsch_mulcrdcntrate33", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate34_reg[] = + { + {"cfg_qsch_mulcrdcntrate34", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate35_reg[] = + { + {"cfg_qsch_mulcrdcntrate35", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate36_reg[] = + { + {"cfg_qsch_mulcrdcntrate36", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_rm_mul_mcn1_rand_hold_shift_reg[] = + { + {"cfg_qsch_rm_mul_mcn1_rand_hold_shift", DPP_FIELD_FLAG_RW, 2, 3, 0x7, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_rm_mul_mcn2_rand_hold_shift_reg[] = + { + {"cfg_qsch_rm_mul_mcn2_rand_hold_shift", DPP_FIELD_FLAG_RW, 2, 3, 0x7, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_cfg_qsch_rm_mul_mcn3_rand_hold_shift_reg[] = + { + {"cfg_qsch_rm_mul_mcn3_rand_hold_shift", DPP_FIELD_FLAG_RW, 2, 3, 0x7, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_last_drop_qnum_get_reg[] = + { + {"cgavd_qmu_drop_tap", DPP_FIELD_FLAG_RC, 31, 4, 0x0, 0x0}, + {"last_drop_qnum", DPP_FIELD_FLAG_RC, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_crdt_qmu_credit_cnt_reg[] = + { + {"crdt_qmu_credit_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qmu_to_qsch_report_cnt_reg[] = + { + {"qmu_to_qsch_report_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qmu_to_cgavd_report_cnt_reg[] = + { + {"qmu_to_cgavd_report_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qmu_crdt_crs_normal_cnt_reg[] = + { + {"qmu_crdt_crs_normal_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qmu_crdt_crs_off_cnt_reg[] = + { + {"qmu_crdt_crs_off_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qsch_qlist_shedule_cnt_reg[] = + { + {"qsch_qlist_shedule_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qsch_qlist_sch_ept_cnt_reg[] = + { + {"qsch_qlist_sch_ept_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qmu_to_mmu_blk_wr_cnt_reg[] = + { + {"qmu_to_mmu_blk_wr_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qmu_to_csw_blk_rd_cnt_reg[] = + { + {"qmu_to_csw_blk_rd_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qmu_to_mmu_sop_wr_cnt_reg[] = + { + {"qmu_to_mmu_sop_wr_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qmu_to_mmu_eop_wr_cnt_reg[] = + { + {"qmu_to_mmu_eop_wr_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qmu_to_mmu_drop_wr_cnt_reg[] = + { + {"qmu_to_mmu_drop_wr_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qmu_to_csw_sop_rd_cnt_reg[] = + { + {"qmu_to_csw_sop_rd_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qmu_to_csw_eop_rd_cnt_reg[] = + { + {"qmu_to_csw_eop_rd_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_qmu_to_csw_drop_rd_cnt_reg[] = + { + {"qmu_to_csw_drop_rd_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_mmu_to_qmu_wr_release_cnt_reg[] = + { + {"mmu_to_qmu_wr_release_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_mmu_to_qmu_rd_release_cnt_reg[] = + { + {"mmu_to_qmu_rd_release_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_observe_qnum_set_reg[] = + { + {"observe_qnum_set", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_spec_q_pkt_received_reg[] = + { + {"spec_q_pkt_received", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_spec_q_pkt_dropped_reg[] = + { + {"spec_q_pkt_dropped", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_spec_q_pkt_scheduled_reg[] = + { + {"spec_q_pkt_scheduled", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_spec_q_wr_cmd_sent_reg[] = + { + {"spec_q_wr_cmd_sent", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_spec_q_rd_cmd_sent_reg[] = + { + {"spec_q_rd_cmd_sent", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_spec_q_pkt_enq_reg[] = + { + {"spec_q_pkt_enq", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_spec_q_pkt_deq_reg[] = + { + {"spec_q_pkt_deq", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_spec_q_crdt_uncon_received_reg[] = + { + {"spec_q_crdt_uncon_received", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_spec_q_crdt_cong_received_reg[] = + { + {"spec_q_crdt_cong_received", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_spec_q_crs_normal_cnt_reg[] = + { + {"spec_q_crs_normal_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_spec_q_crs_off_cnt_reg[] = + { + {"spec_q_crs_off_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_observe_batch_set_reg[] = + { + {"observe_batch_set", DPP_FIELD_FLAG_RW, 2, 3, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_spec_bat_pkt_received_reg[] = + { + {"spec_bat_pkt_received", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_spec_bat_pkt_dropped_reg[] = + { + {"spec_bat_pkt_dropped", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_spec_bat_blk_scheduled_reg[] = + { + {"spec_bat_blk_scheduled", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_spec_bat_wr_cmd_sent_reg[] = + { + {"spec_bat_wr_cmd_sent", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_spec_bat_rd_cmd_sent_reg[] = + { + {"spec_bat_rd_cmd_sent", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_spec_bat_pkt_enq_reg[] = + { + {"spec_bat_pkt_enq", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_spec_bat_pkt_deq_reg[] = + { + {"spec_bat_pkt_deq", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_spec_bat_crdt_uncon_received_reg[] = + { + {"spec_bat_crdt_uncon_received", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_spec_bat_crdt_cong_received_reg[] = + { + {"spec_bat_crdt_cong_received", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_spec_bat_crs_normal_cnt_reg[] = + { + {"spec_bat_crs_normal_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_spec_bat_crs_off_cnt_reg[] = + { + {"spec_bat_crs_off_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_bcntm_ovfl_qnum_get_reg[] = + { + {"bcntm_ovfl_qnum_get", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_crbal_a_ovf_qnum_get_reg[] = + { + {"crbal_a_ovf_qnum_get", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_crbal_b_ovf_qnum_get_reg[] = + { + {"crbal_b_ovf_qnum_get", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_crbal_drop_qnum_get_reg[] = + { + {"crbal_drop_qnum_get", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_deq_flg_report_cnt_reg[] = + { + {"deq_flg_report_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_spec_q_crs_get_reg[] = + { + {"spec_q_crs_get", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_spec_q_crs_in_get_reg[] = + { + {"spec_q_crs_in_get", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_spec_q_crs_flg_csol_get_reg[] = + { + {"spec_q_crs_flg_csol_get", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_etm_qmu_ept_sch_qnum_get_reg[] = + { + {"ept_sch_qnum_get", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_pcie_ddr_switch_reg[] = + { + {"pcie_ddr_switch", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_user0_int_en_reg[] = + { + {"user_int_en", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_user0_int_mask_reg[] = + { + {"user_int_mask", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_user0_int_status_reg[] = + { + {"user_int_status", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_user1_int_en_reg[] = + { + {"user_int_en", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_user1_int_mask_reg[] = + { + {"user_int_mask", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_user1_int_status_reg[] = + { + {"user_int_status", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_user2_int_en_reg[] = + { + {"user_int_en", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_user2_int_mask_reg[] = + { + {"user_int_mask", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_user2_int_status_reg[] = + { + {"user_int_status", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_ecc_1b_int_en_reg[] = + { + {"ecc_1b_int_en", DPP_FIELD_FLAG_RW, 2, 3, 0xfffff, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_ecc_1b_int_mask_reg[] = + { + {"ecc_1b_int_mask", DPP_FIELD_FLAG_RW, 2, 3, 0xfffff, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_ecc_1b_int_status_reg[] = + { + {"ecc_1b_int_status", DPP_FIELD_FLAG_RC, 2, 3, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_ecc_2b_int_en_reg[] = + { + {"ecc_2b_int_en", DPP_FIELD_FLAG_RW, 2, 3, 0xfffff, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_ecc_2b_int_mask_reg[] = + { + {"ecc_2b_int_mask", DPP_FIELD_FLAG_RW, 2, 3, 0xfffff, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_ecc_2b_int_status_reg[] = + { + {"ecc_2b_int_status", DPP_FIELD_FLAG_RC, 2, 3, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_cfg_int_status_reg[] = + { + {"cfg_int_status", DPP_FIELD_FLAG_RC, 4, 5, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_i_core_to_cntl_reg[] = + { + {"i_core_to_cntl", DPP_FIELD_FLAG_RW, 15, 16, 0xaaaa, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_test_in_low_reg[] = + { + {"test_in_low", DPP_FIELD_FLAG_RW, 31, 32, 0x00004000, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_test_in_high_reg[] = + { + {"test_in_high", DPP_FIELD_FLAG_RW, 31, 32, 0x00000000, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_local_interrupt_out_reg[] = + { + {"local_interrupt_out", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_pl_ltssm_reg[] = + { + {"pl_ltssm", DPP_FIELD_FLAG_RO, 4, 5, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_test_out0_reg[] = + { + {"test_out0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_test_out1_reg[] = + { + {"test_out1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_test_out2_reg[] = + { + {"test_out2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_test_out3_reg[] = + { + {"test_out3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_test_out4_reg[] = + { + {"test_out4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_test_out5_reg[] = + { + {"test_out5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_test_out6_reg[] = + { + {"test_out6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_test_out7_reg[] = + { + {"test_out7", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_sync_o_core_status_reg[] = + { + {"sync_o_core_status", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_sync_o_alert_dbe_reg[] = + { + {"sync_o_alert_dbe", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_sync_o_alert_sbe_reg[] = + { + {"sync_o_alert_sbe", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_sync_o_link_loopback_en_reg[] = + { + {"sync_o_link_loopback_en", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_sync_o_local_fs_lf_valid_reg[] = + { + {"sync_o_local_fs_lf_valid", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_sync_o_rx_idle_detect_reg[] = + { + {"sync_o_rx_idle_detect", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_sync_o_rx_rdy_reg[] = + { + {"sync_o_rx_rdy", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_sync_o_tx_rdy_reg[] = + { + {"sync_o_tx_rdy", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_pcie_link_up_cnt_reg[] = + { + {"pcie_link_up_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_test_out_pcie0_reg[] = + { + {"test_out_pcie0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_test_out_pcie1_reg[] = + { + {"test_out_pcie1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_test_out_pcie2_reg[] = + { + {"test_out_pcie2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_test_out_pcie3_reg[] = + { + {"test_out_pcie3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_test_out_pcie4_reg[] = + { + {"test_out_pcie4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_test_out_pcie5_reg[] = + { + {"test_out_pcie5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_test_out_pcie6_reg[] = + { + {"test_out_pcie6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_test_out_pcie7_reg[] = + { + {"test_out_pcie7", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_test_out_pcie8_reg[] = + { + {"test_out_pcie8", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_test_out_pcie9_reg[] = + { + {"test_out_pcie9", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_test_out_pcie10_reg[] = + { + {"test_out_pcie10", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_test_out_pcie11_reg[] = + { + {"test_out_pcie11", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_test_out_pcie12_reg[] = + { + {"test_out_pcie12", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_test_out_pcie13_reg[] = + { + {"test_out_pcie13", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_test_out_pcie14_reg[] = + { + {"test_out_pcie14", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_test_out_pcie15_reg[] = + { + {"test_out_pcie15", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_int_repeat_en_reg[] = + { + {"int_repeat_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg_awid_axi_mst_reg[] = + { + {"dbg_awid_axi_mst", DPP_FIELD_FLAG_RO, 2, 3, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg_awaddr_axi_mst0_reg[] = + { + {"dbg_awaddr_axi_mst0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg_awaddr_axi_mst1_reg[] = + { + {"dbg_awaddr_axi_mst1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg_awlen_axi_mst_reg[] = + { + {"dbg_awlen_axi_mst", DPP_FIELD_FLAG_RO, 3, 4, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg_awsize_axi_mst_reg[] = + { + {"dbg_awid_axi_mst", DPP_FIELD_FLAG_RO, 2, 3, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg_awburst_axi_mst_reg[] = + { + {"dbg_awburst_axi_mst", DPP_FIELD_FLAG_RO, 1, 2, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg_awlock_axi_mst_reg[] = + { + {"dbg_awlock_axi_mst", DPP_FIELD_FLAG_RO, 1, 2, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg_awcache_axi_mst_reg[] = + { + {"dbg_awcache_axi_mst", DPP_FIELD_FLAG_RO, 3, 4, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg_awprot_axi_mst_reg[] = + { + {"dbg_awprot_axi_mst", DPP_FIELD_FLAG_RO, 2, 3, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg_wid_axi_mst_reg[] = + { + {"dbg_wid_axi_mst", DPP_FIELD_FLAG_RO, 3, 4, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg_wdata_axi_mst0_reg[] = + { + {"dbg_wdata_axi_mst0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg_wdata_axi_mst1_reg[] = + { + {"dbg_wdata_axi_mst1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg_wdata_axi_mst2_reg[] = + { + {"dbg_wdata_axi_mst2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg_wdata_axi_mst3_reg[] = + { + {"dbg_wdata_axi_mst3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg_wstrb_axi_mst_reg[] = + { + {"dbg_wstrb_axi_mst", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg_wlast_axi_mst_reg[] = + { + {"dbg_wlast_axi_mst", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg_arid_axi_mst_reg[] = + { + {"dbg_arid_axi_mst", DPP_FIELD_FLAG_RO, 3, 4, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg_araddr_axi_mst0_reg[] = + { + {"dbg_araddr_axi_mst0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg_araddr_axi_mst1_reg[] = + { + {"dbg_araddr_axi_mst1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg_arlen_axi_mst_reg[] = + { + {"dbg_arlen_axi_mst", DPP_FIELD_FLAG_RO, 3, 4, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg_arsize_axi_mst_reg[] = + { + {"dbg_arsize_axi_mst", DPP_FIELD_FLAG_RO, 2, 3, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg_arburst_axi_mst_reg[] = + { + {"dbg_arburst_axi_mst", DPP_FIELD_FLAG_RO, 1, 2, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg_arlock_axi_mst_reg[] = + { + {"dbg_arlock_axi_mst", DPP_FIELD_FLAG_RO, 1, 2, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg_arcache_axi_mst_reg[] = + { + {"dbg_arcache_axi_mst", DPP_FIELD_FLAG_RO, 3, 4, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg_arprot_axi_mst_reg[] = + { + {"dbg_arprot_axi_mst", DPP_FIELD_FLAG_RO, 2, 3, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg_rdata_axi_mst0_reg[] = + { + {"dbg_rdata_axi_mst0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg_rdata_axi_mst1_reg[] = + { + {"dbg_rdata_axi_mst1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg_rdata_axi_mst2_reg[] = + { + {"dbg_rdata_axi_mst2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg_rdata_axi_mst3_reg[] = + { + {"dbg_rdata_axi_mst3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_axi_mst_state_reg[] = + { + {"axi_mst_state", DPP_FIELD_FLAG_RO, 2, 3, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_axi_cfg_state_reg[] = + { + {"axi_cfg_state", DPP_FIELD_FLAG_RO, 2, 3, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_axi_slv_rd_state_reg[] = + { + {"axi_slv_rd_state", DPP_FIELD_FLAG_RO, 1, 2, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_axi_slv_wr_state_reg[] = + { + {"axi_slv_wr_state", DPP_FIELD_FLAG_RO, 1, 2, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_axim_delay_en_reg[] = + { + {"axim_delay_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_axim_delay_reg[] = + { + {"axim_delay", DPP_FIELD_FLAG_RW, 31, 32, 0xff, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_axim_speed_wr_reg[] = + { + {"axim_speed_wr", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_axim_speed_rd_reg[] = + { + {"axim_speed_rd", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg_awaddr_axi_slv0_reg[] = + { + {"dbg_awaddr_axi_slv0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg_awaddr_axi_slv1_reg[] = + { + {"dbg_awaddr_axi_slv1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg0_wdata_axi_slv0_reg[] = + { + {"dbg0_wdata_axi_slv0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg0_wdata_axi_slv1_reg[] = + { + {"dbg0_wdata_axi_slv1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg0_wdata_axi_slv2_reg[] = + { + {"dbg0_wdata_axi_slv2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg0_wdata_axi_slv3_reg[] = + { + {"dbg0_wdata_axi_slv3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg1_wdata_axi_slv0_reg[] = + { + {"dbg1_wdata_axi_slv0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg1_wdata_axi_slv1_reg[] = + { + {"dbg1_wdata_axi_slv1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg1_wdata_axi_slv2_reg[] = + { + {"dbg1_wdata_axi_slv2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg1_wdata_axi_slv3_reg[] = + { + {"dbg1_wdata_axi_slv3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg2_wdata_axi_slv0_reg[] = + { + {"dbg2_wdata_axi_slv0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg2_wdata_axi_slv1_reg[] = + { + {"dbg2_wdata_axi_slv1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg2_wdata_axi_slv2_reg[] = + { + {"dbg2_wdata_axi_slv2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg2_wdata_axi_slv3_reg[] = + { + {"dbg2_wdata_axi_slv3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg3_wdata_axi_slv0_reg[] = + { + {"dbg3_wdata_axi_slv0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg3_wdata_axi_slv1_reg[] = + { + {"dbg3_wdata_axi_slv1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg3_wdata_axi_slv2_reg[] = + { + {"dbg3_wdata_axi_slv2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg3_wdata_axi_slv3_reg[] = + { + {"dbg3_wdata_axi_slv3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg4_wdata_axi_slv0_reg[] = + { + {"dbg4_wdata_axi_slv0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg4_wdata_axi_slv1_reg[] = + { + {"dbg4_wdata_axi_slv1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg4_wdata_axi_slv2_reg[] = + { + {"dbg4_wdata_axi_slv2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg4_wdata_axi_slv3_reg[] = + { + {"dbg4_wdata_axi_slv3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg5_wdata_axi_slv0_reg[] = + { + {"dbg5_wdata_axi_slv0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg5_wdata_axi_slv1_reg[] = + { + {"dbg5_wdata_axi_slv1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg5_wdata_axi_slv2_reg[] = + { + {"dbg5_wdata_axi_slv2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg5_wdata_axi_slv3_reg[] = + { + {"dbg5_wdata_axi_slv3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg6_wdata_axi_slv0_reg[] = + { + {"dbg6_wdata_axi_slv0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg6_wdata_axi_slv1_reg[] = + { + {"dbg6_wdata_axi_slv1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg6_wdata_axi_slv2_reg[] = + { + {"dbg6_wdata_axi_slv2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg6_wdata_axi_slv3_reg[] = + { + {"dbg6_wdata_axi_slv3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg7_wdata_axi_slv0_reg[] = + { + {"dbg7_wdata_axi_slv0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg7_wdata_axi_slv1_reg[] = + { + {"dbg7_wdata_axi_slv1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg7_wdata_axi_slv2_reg[] = + { + {"dbg7_wdata_axi_slv2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg7_wdata_axi_slv3_reg[] = + { + {"dbg7_wdata_axi_slv3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg8_wdata_axi_slv0_reg[] = + { + {"dbg8_wdata_axi_slv0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg8_wdata_axi_slv1_reg[] = + { + {"dbg8_wdata_axi_slv1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg8_wdata_axi_slv2_reg[] = + { + {"dbg8_wdata_axi_slv2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg8_wdata_axi_slv3_reg[] = + { + {"dbg8_wdata_axi_slv3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg9_wdata_axi_slv0_reg[] = + { + {"dbg9_wdata_axi_slv0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg9_wdata_axi_slv1_reg[] = + { + {"dbg9_wdata_axi_slv1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg9_wdata_axi_slv2_reg[] = + { + {"dbg9_wdata_axi_slv2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg9_wdata_axi_slv3_reg[] = + { + {"dbg9_wdata_axi_slv3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg_awlen_axi_slv_reg[] = + { + {"dbg_awlen_axi_slv", DPP_FIELD_FLAG_RO, 3, 4, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg_wlast_axi_slv_reg[] = + { + {"dbg_wlast_axi_slv", DPP_FIELD_FLAG_RO, 9, 10, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg_araddr_axi_slv0_reg[] = + { + {"dbg5_wdata_axi_slv1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg_araddr_axi_slv1_reg[] = + { + {"dbg5_wdata_axi_slv2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg0_rdata_axi_slv0_reg[] = + { + {"dbg5_wdata_axi_slv3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg0_rdata_axi_slv1_reg[] = + { + {"dbg6_wdata_axi_slv0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg0_rdata_axi_slv2_reg[] = + { + {"dbg6_wdata_axi_slv1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg0_rdata_axi_slv3_reg[] = + { + {"dbg6_wdata_axi_slv2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg1_rdata_axi_slv0_reg[] = + { + {"dbg6_wdata_axi_slv3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg1_rdata_axi_slv1_reg[] = + { + {"dbg7_wdata_axi_slv0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg1_rdata_axi_slv2_reg[] = + { + {"dbg7_wdata_axi_slv1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg1_rdata_axi_slv3_reg[] = + { + {"dbg7_wdata_axi_slv2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_pcie_dbg_rlast_axi_slv_reg[] = + { + {"dbg_rlast_axi_slv", DPP_FIELD_FLAG_RO, 1, 2, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_dma_dma_enable_reg[] = + { + {"dma_enable", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_dma_up_req_reg[] = + { + {"up_req", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_dma_dma_up_current_state_reg[] = + { + {"dma_up_current_state", DPP_FIELD_FLAG_RO, 2, 3, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_dma_dma_up_req_ack_reg[] = + { + {"dma_up_req_ack", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_dma_dma_done_latch_reg[] = + { + {"done_latch", DPP_FIELD_FLAG_RO, 1, 2, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_dma_dma_up_cpu_addr_low32_reg[] = + { + {"dma_up_cpu_addr_low", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_dma_dma_up_cpu_addr_high32_reg[] = + { + {"dma_up_cpu_addr_high", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_dma_dma_up_se_addr_reg[] = + { + {"dma_up_se_addr", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_dma_dma_done_int_reg[] = + { + {"dma_done_int", DPP_FIELD_FLAG_RO, 2, 3, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_dma_sp_cfg_reg[] = + { + {"sp_cfg", DPP_FIELD_FLAG_RW, 1, 2, 0x1, 0x0}, + }; +DPP_FIELD_T g_cfg_dma_dma_ing_reg[] = + { + {"dma_ing", DPP_FIELD_FLAG_RO, 1, 2, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_dma_rd_timeout_thresh_reg[] = + { + {"rd_timeout_thresh", DPP_FIELD_FLAG_RW, 31, 32, 0x7d0, 0x0}, + }; +DPP_FIELD_T g_cfg_dma_dma_tab_sta_up_fifo_gap_reg[] = + { + {"dma_tab_sta_up_fifo_gap", DPP_FIELD_FLAG_RW, 8, 9, 0xfa, 0x0}, + }; +DPP_FIELD_T g_cfg_dma_cfg_mac_tim_reg[] = + { + {"cfg_mac_tim", DPP_FIELD_FLAG_RW, 31, 32, 0x50, 0x0}, + }; +DPP_FIELD_T g_cfg_dma_cfg_mac_num_reg[] = + { + {"cfg_mac_num", DPP_FIELD_FLAG_RW, 8, 9, 0x28, 0x0}, + }; +DPP_FIELD_T g_cfg_dma_init_bd_addr_reg[] = + { + {"init_bd_addr", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_dma_mac_up_bd_addr1_low32_reg[] = + { + {"mac_up_bd_addr1_low32", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_dma_mac_up_bd_addr1_high32_reg[] = + { + {"mac_up_bd_addr1_high32", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_dma_mac_up_bd_addr2_low32_reg[] = + { + {"mac_up_bd_addr2_low32", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_dma_mac_up_bd_addr2_high32_reg[] = + { + {"mac_up_bd_addr2_high32", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_dma_cfg_mac_max_num_reg[] = + { + {"cfg_mac_max_num", DPP_FIELD_FLAG_RW, 8, 9, 0x1ff, 0x0}, + }; +DPP_FIELD_T g_cfg_dma_dma_wbuf_ff_empty_reg[] = + { + {"dma_wbuf_ff_empty", DPP_FIELD_FLAG_RO, 1, 2, 0x3, 0x0}, + }; +DPP_FIELD_T g_cfg_dma_dma_wbuf_state_reg[] = + { + {"dma_wbuf_state", DPP_FIELD_FLAG_RO, 2, 3, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_dma_dma_mac_bd_addr_low32_reg[] = + { + {"dma_mac_bd_addr_low32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_dma_dma_mac_bd_addr_high32_reg[] = + { + {"dma_mac_bd_addr_high32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_dma_mac_up_enable_reg[] = + { + {"mac_up_enable", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_dma_mac_endian_reg[] = + { + {"mac_endian", DPP_FIELD_FLAG_RW, 1, 2, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_dma_up_endian_reg[] = + { + {"up_endian", DPP_FIELD_FLAG_RW, 1, 2, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_dma_dma_up_rd_cnt_latch_reg[] = + { + {"dma_up_rd_cnt_latch", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_dma_dma_up_rcv_cnt_latch_reg[] = + { + {"dma_up_rcv_cnt_latch", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_dma_dma_up_cnt_latch_reg[] = + { + {"dma_up_cnt_latch", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_dma_cpu_rd_bd_pulse_reg[] = + { + {"cpu_rd_bd_pulse", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_dma_cpu_bd_threshold_reg[] = + { + {"cpu_bd_threshold", DPP_FIELD_FLAG_RW, 31, 32, 0x64, 0x0}, + }; +DPP_FIELD_T g_cfg_dma_cpu_bd_used_cnt_reg[] = + { + {"cpu_bd_used_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_dma_dma_up_rcv_status_reg[] = + { + {"dma_up_rcv_status", DPP_FIELD_FLAG_RO, 31, 32, 0x1, 0x0}, + }; +DPP_FIELD_T g_cfg_dma_slv_rid_err_en_reg[] = + { + {"slv_rid_err_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_dma_slv_rresp_err_en_reg[] = + { + {"slv_rresp_err_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_cfg_dma_se_rdbk_ff_full_reg[] = + { + {"se_rdbk_ff_full", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_dma_dma_up_data_count_reg[] = + { + {"dma_up_data_count", DPP_FIELD_FLAG_RO, 9, 10, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_dma_dma_mwr_fifo_afull_gap_reg[] = + { + {"dma_mwr_fifo_afull_gap", DPP_FIELD_FLAG_RW, 5, 6, 0x14, 0x0}, + }; +DPP_FIELD_T g_cfg_dma_dma_info_fifo_afull_gap_reg[] = + { + {"dma_mwr_fifo_afull_gap", DPP_FIELD_FLAG_RW, 5, 6, 0x10, 0x0}, + }; +DPP_FIELD_T g_cfg_dma_dma_rd_timeout_set_reg[] = + { + {"dma_rd_timeout_set", DPP_FIELD_FLAG_RW, 31, 32, 0x3ffffff, 0x0}, + }; +DPP_FIELD_T g_cfg_dma_dma_bd_dat_err_en_reg[] = + { + {"dma_bd_dat_err_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_dma_dma_repeat_cnt_reg[] = + { + {"dma_repeat_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_dma_dma_rd_timeout_en_reg[] = + { + {"dma_rd_timeout_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_dma_dma_repeat_read_reg[] = + { + {"dma_repeat_read", DPP_FIELD_FLAG_RW, 31, 32, 0xa, 0x0}, + }; +DPP_FIELD_T g_cfg_dma_dma_repeat_read_en_reg[] = + { + {"dma_repeat_read_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_dma_bd_ctl_state_reg[] = + { + {"bd_ctl_state", DPP_FIELD_FLAG_RO, 1, 2, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_dma_dma_done_int_cnt_wr_reg[] = + { + {"dma_done_int_cnt_wr", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_dma_dma_done_int_cnt_mac_reg[] = + { + {"dma_done_int_cnt_mac", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_dma_current_mac_num_reg[] = + { + {"current_mac_num", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_dma_cfg_mac_afifo_afull_reg[] = + { + {"cfg_mac_afifo_afull", DPP_FIELD_FLAG_RW, 8, 9, 0xc8, 0x0}, + }; +DPP_FIELD_T g_cfg_dma_dma_mac_ff_full_reg[] = + { + {"dma_mac_ff_full", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_dma_user_axi_mst_reg[] = + { + {"user_en", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, + {"cfg_epid", DPP_FIELD_FLAG_RW, 27, 4, 0x0, 0x0}, + {"cfg_vfunc_num", DPP_FIELD_FLAG_RW, 23, 8, 0x0, 0x0}, + {"cfg_func_num", DPP_FIELD_FLAG_RW, 7, 3, 0x0, 0x0}, + {"cfg_vfunc_active", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_csr_sbus_state_reg[] = + { + {"sbus_state", DPP_FIELD_FLAG_RO, 2, 3, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_csr_mst_debug_en_reg[] = + { + {"mst_debug_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_cfg_csr_sbus_command_sel_reg[] = + { + {"sbus_command_sel", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_csr_soc_rd_time_out_thresh_reg[] = + { + {"soc_rd_time_out_thresh", DPP_FIELD_FLAG_RW, 31, 32, 0x2710, 0x0}, + }; +DPP_FIELD_T g_cfg_csr_big_little_byte_order_reg[] = + { + {"big_little_byte_order", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_csr_ecc_bypass_read_reg[] = + { + {"ecc_bypass_read", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_cfg_csr_ahb_async_wr_fifo_afull_gap_reg[] = + { + {"ahb_async_wr_fifo_afull_gap", DPP_FIELD_FLAG_RW, 5, 6, 0x18, 0x0}, + }; +DPP_FIELD_T g_cfg_csr_ahb_async_rd_fifo_afull_gap_reg[] = + { + {"ahb_async_rd_fifo_afull_gap", DPP_FIELD_FLAG_RW, 4, 5, 0xc, 0x0}, + }; +DPP_FIELD_T g_cfg_csr_ahb_async_cpl_fifo_afull_gap_reg[] = + { + {"ahb_async_cpl_fifo_afull_gap", DPP_FIELD_FLAG_RW, 4, 5, 0xc, 0x0}, + }; +DPP_FIELD_T g_cfg_csr_mst_debug_data0_high26_reg[] = + { + {"mst_debug_data0_high26", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_csr_mst_debug_data0_low32_reg[] = + { + {"mst_debug_data0_low32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_csr_mst_debug_data1_high26_reg[] = + { + {"mst_debug_data1_high26", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_csr_mst_debug_data1_low32_reg[] = + { + {"mst_debug_data1_low32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_csr_mst_debug_data2_high26_reg[] = + { + {"mst_debug_data2_high26", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_csr_mst_debug_data2_low32_reg[] = + { + {"mst_debug_data2_low32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_csr_mst_debug_data3_high26_reg[] = + { + {"mst_debug_data3_high26", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_csr_mst_debug_data3_low32_reg[] = + { + {"mst_debug_data3_low32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_csr_mst_debug_data4_high26_reg[] = + { + {"mst_debug_data4_high26", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_csr_mst_debug_data4_low32_reg[] = + { + {"mst_debug_data4_low32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_csr_mst_debug_data5_high26_reg[] = + { + {"mst_debug_data5_high26", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_csr_mst_debug_data5_low32_reg[] = + { + {"mst_debug_data5_low32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_csr_mst_debug_data6_high26_reg[] = + { + {"mst_debug_data6_high26", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_csr_mst_debug_data6_low32_reg[] = + { + {"mst_debug_data6_low32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_csr_mst_debug_data7_high26_reg[] = + { + {"mst_debug_data7_high26", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_csr_mst_debug_data7_low32_reg[] = + { + {"mst_debug_data7_low32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_csr_mst_debug_data8_high26_reg[] = + { + {"mst_debug_data8_high26", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_csr_mst_debug_data8_low32_reg[] = + { + {"mst_debug_data8_low32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_csr_mst_debug_data9_high26_reg[] = + { + {"mst_debug_data9_high26", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_csr_mst_debug_data9_low32_reg[] = + { + {"mst_debug_data9_low32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_csr_mst_debug_data10_high26_reg[] = + { + {"mst_debug_data10_high26", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_csr_mst_debug_data10_low32_reg[] = + { + {"mst_debug_data10_low32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_csr_mst_debug_data11_high26_reg[] = + { + {"mst_debug_data11_high26", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_csr_mst_debug_data11_low32_reg[] = + { + {"mst_debug_data11_low32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_csr_mst_debug_data12_high26_reg[] = + { + {"mst_debug_data12_high26", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_csr_mst_debug_data12_low32_reg[] = + { + {"mst_debug_data12_low32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_csr_mst_debug_data13_high26_reg[] = + { + {"mst_debug_data13_high26", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_csr_mst_debug_data13_low32_reg[] = + { + {"mst_debug_data13_low32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_csr_mst_debug_data14_high26_reg[] = + { + {"mst_debug_data14_high26", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_csr_mst_debug_data14_low32_reg[] = + { + {"mst_debug_data14_low32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_csr_mst_debug_data15_high26_reg[] = + { + {"mst_debug_data15_high26", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_cfg_csr_mst_debug_data15_low32_reg[] = + { + {"mst_debug_data15_low32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_ind_access_states_reg[] = + { + {"ind_access_done", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_ind_access_cmd0_reg[] = + { + {"wr_mode", DPP_FIELD_FLAG_RW, 29, 1, 0x0, 0x0}, + {"rd_or_wr", DPP_FIELD_FLAG_RW, 28, 1, 0x0, 0x0}, + {"ind_access_addr0", DPP_FIELD_FLAG_RW, 16, 17, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_ind_access_data0_reg[] = + { + {"ind_access_data0", DPP_FIELD_FLAG_RW, 20, 21, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_ind_access_data1_reg[] = + { + {"ind_access_data1", DPP_FIELD_FLAG_RW, 20, 21, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_ind_access_cmd1_reg[] = + { + {"ind_access_addr1", DPP_FIELD_FLAG_RW, 16, 17, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_mr_init_done_reg[] = + { + {"mr_init_done", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_cnt_mode_reg_reg[] = + { + {"cfgmt_count_rd_mode", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"cfgmt_count_overflow_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_cfg_ecc_bypass_read_reg[] = + { + {"cfg_ecc_bypass_read", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_cfg_rep_mod_reg[] = + { + {"cfg_rep_mod", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_block_ptr_fifo_aful_th_reg[] = + { + {"block_ptr3_fifo_aful_th", DPP_FIELD_FLAG_RW, 31, 8, 0xa0, 0x0}, + {"block_ptr2_fifo_aful_th", DPP_FIELD_FLAG_RW, 23, 8, 0xa0, 0x0}, + {"block_ptr1_fifo_aful_th", DPP_FIELD_FLAG_RW, 15, 8, 0xa0, 0x0}, + {"block_ptr0_fifo_aful_th", DPP_FIELD_FLAG_RW, 7, 8, 0xa0, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_pre_rcv_ptr_fifo_aful_th_reg[] = + { + {"pre_rcv_ptr3_fifo_aful_th", DPP_FIELD_FLAG_RW, 31, 8, 0xa0, 0x0}, + {"pre_rcv_ptr2_fifo_aful_th", DPP_FIELD_FLAG_RW, 23, 8, 0xa0, 0x0}, + {"pre_rcv_ptr1_fifo_aful_th", DPP_FIELD_FLAG_RW, 15, 8, 0xa0, 0x0}, + {"pre_rcv_ptr0_fifo_aful_th", DPP_FIELD_FLAG_RW, 7, 8, 0xa0, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_mgid_fifo_aful_th_reg[] = + { + {"mgid3_fifo_aful_th", DPP_FIELD_FLAG_RW, 31, 8, 0xa0, 0x0}, + {"mgid2_fifo_aful_th", DPP_FIELD_FLAG_RW, 23, 8, 0xa0, 0x0}, + {"mgid1_fifo_aful_th", DPP_FIELD_FLAG_RW, 15, 8, 0xa0, 0x0}, + {"mgid0_fifo_aful_th", DPP_FIELD_FLAG_RW, 7, 8, 0xa0, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_rep_cmd_fifo_aful_th_reg[] = + { + {"rep_cmd3_fifo_aful_th", DPP_FIELD_FLAG_RW, 31, 8, 0x14, 0x0}, + {"rep_cmd2_fifo_aful_th", DPP_FIELD_FLAG_RW, 23, 8, 0x14, 0x0}, + {"rep_cmd1_fifo_aful_th", DPP_FIELD_FLAG_RW, 15, 8, 0x14, 0x0}, + {"rep_cmd0_fifo_aful_th", DPP_FIELD_FLAG_RW, 7, 8, 0x14, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_mr_int_mask_1_reg[] = + { + {"free_ptr0_fifo_full_mask", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0}, + {"free_ptr1_fifo_full_mask", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + {"free_ptr2_fifo_full_mask", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0}, + {"free_ptr3_fifo_full_mask", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"block_ptr0_fifo_full_mask", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"block_ptr1_fifo_full_mask", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"block_ptr2_fifo_full_mask", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"block_ptr3_fifo_full_mask", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"mgid0_fifo_full_mask", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"mgid1_fifo_full_mask", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"mgid2_fifo_full_mask", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"mgid3_fifo_full_mask", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"pre_rcv_ptr0_fifo_full_mask", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"pre_rcv_ptr1_fifo_full_mask", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"pre_rcv_ptr2_fifo_full_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"pre_rcv_ptr3_fifo_full_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"rep_cmd0_fifo_full_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"rep_cmd1_fifo_full_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"rep_cmd2_fifo_full_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"rep_cmd3_fifo_full_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_mr_int_mask_2_reg[] = + { + {"free_ptr0_fifo_udf_mask", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0}, + {"free_ptr1_fifo_udf_mask", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + {"free_ptr2_fifo_udf_mask", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0}, + {"free_ptr3_fifo_udf_mask", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"block_ptr0_fifo_udf_mask", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"block_ptr1_fifo_udf_mask", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"block_ptr2_fifo_udf_mask", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"block_ptr3_fifo_udf_mask", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"mgid0_fifo_udf_mask", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"mgid1_fifo_udf_mask", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"mgid2_fifo_udf_mask", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"mgid3_fifo_udf_mask", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"pre_rcv_ptr0_fifo_udf_mask", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"pre_rcv_ptr1_fifo_udf_mask", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"pre_rcv_ptr2_fifo_udf_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"pre_rcv_ptr3_fifo_udf_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"rep_cmd0_fifo_udf_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"rep_cmd1_fifo_udf_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"rep_cmd2_fifo_udf_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"rep_cmd3_fifo_udf_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_mr_int_mask_3_reg[] = + { + {"free_ptr0_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0}, + {"free_ptr1_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + {"free_ptr2_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0}, + {"free_ptr3_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"block_ptr0_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"block_ptr1_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"block_ptr2_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"block_ptr3_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"mgid0_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"mgid1_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"mgid2_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"mgid3_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"pre_rcv_ptr0_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"pre_rcv_ptr1_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"pre_rcv_ptr2_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"pre_rcv_ptr3_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"rep_cmd0_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"rep_cmd1_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"rep_cmd2_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"rep_cmd3_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_mr_int_mask_4_reg[] = + { + {"data_buf0_ram_parity_err_mask", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0}, + {"data_buf1_ram_parity_err_mask", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0}, + {"data_buf2_ram_parity_err_mask", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0}, + {"data_buf3_ram_parity_err_mask", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0}, + {"mlt_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"free_ptr0_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0}, + {"free_ptr1_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + {"free_ptr2_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0}, + {"free_ptr3_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"block_ptr0_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"block_ptr1_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"block_ptr2_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"block_ptr3_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"mgid0_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"mgid1_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"mgid2_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"mgid3_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"pre_rcv_ptr0_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"pre_rcv_ptr1_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"pre_rcv_ptr2_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"pre_rcv_ptr3_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"rep_cmd0_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"rep_cmd1_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"rep_cmd2_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"rep_cmd3_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_mr_states_1_reg[] = + { + {"free_ptr0_fifo_full", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"free_ptr1_fifo_full", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"free_ptr2_fifo_full", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"free_ptr3_fifo_full", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"block_ptr0_fifo_full", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"block_ptr1_fifo_full", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"block_ptr2_fifo_full", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"block_ptr3_fifo_full", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"mgid0_fifo_full", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"mgid1_fifo_full", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"mgid2_fifo_full", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"mgid3_fifo_full", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"pre_rcv_ptr0_fifo_full", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"pre_rcv_ptr1_fifo_full", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"pre_rcv_ptr2_fifo_full", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"pre_rcv_ptr3_fifo_full", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"rep_cmd0_fifo_full", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"rep_cmd1_fifo_full", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"rep_cmd2_fifo_full", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"rep_cmd3_fifo_full", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_mr_states_2_reg[] = + { + {"free_ptr0_fifo_udf", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"free_ptr1_fifo_udf", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"free_ptr2_fifo_udf", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"free_ptr3_fifo_udf", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"block_ptr0_fifo_udf", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"block_ptr1_fifo_udf", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"block_ptr2_fifo_udf", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"block_ptr3_fifo_udf", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"mgid0_fifo_udf", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"mgid1_fifo_udf", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"mgid2_fifo_udf", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"mgid3_fifo_udf", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"pre_rcv_ptr0_fifo_udf", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"pre_rcv_ptr1_fifo_udf", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"pre_rcv_ptr2_fifo_udf", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"pre_rcv_ptr3_fifo_udf", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"rep_cmd0_fifo_udf", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"rep_cmd1_fifo_udf", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"rep_cmd2_fifo_udf", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"rep_cmd3_fifo_udf", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_mr_states_3_reg[] = + { + {"free_ptr0_fifo_ovf", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"free_ptr1_fifo_ovf", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"free_ptr2_fifo_ovf", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"free_ptr3_fifo_ovf", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"block_ptr0_fifo_ovf", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"block_ptr1_fifo_ovf", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"block_ptr2_fifo_ovf", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"block_ptr3_fifo_ovf", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"mgid0_fifo_ovf", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"mgid1_fifo_ovf", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"mgid2_fifo_ovf", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"mgid3_fifo_ovf", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"pre_rcv_ptr0_fifo_ovf", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"pre_rcv_ptr1_fifo_ovf", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"pre_rcv_ptr2_fifo_ovf", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"pre_rcv_ptr3_fifo_ovf", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"rep_cmd0_fifo_ovf", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"rep_cmd1_fifo_ovf", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"rep_cmd2_fifo_ovf", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"rep_cmd3_fifo_ovf", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_mr_states_4_reg[] = + { + {"data_buf0_ram_parity_err", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"data_buf1_ram_parity_err", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"data_buf2_ram_parity_err", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"data_buf3_ram_parity_err", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"mlt_ecc_single_err", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"free_ptr0_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"free_ptr1_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"free_ptr2_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"free_ptr3_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"block_ptr0_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"block_ptr1_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"block_ptr2_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"block_ptr3_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"mgid0_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"mgid1_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"mgid2_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"mgid3_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"pre_rcv_ptr0_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"pre_rcv_ptr1_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"pre_rcv_ptr2_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"pre_rcv_ptr3_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"rep_cmd0_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"rep_cmd1_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"rep_cmd2_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"rep_cmd3_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_mr_states_5_reg[] = + { + {"mlt_ecc_double_err", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"free_ptr0_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"free_ptr1_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"free_ptr2_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"free_ptr3_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"block_ptr0_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"block_ptr1_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"block_ptr2_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"block_ptr3_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"mgid0_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"mgid1_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"mgid2_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"mgid3_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"pre_rcv_ptr0_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"pre_rcv_ptr1_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"pre_rcv_ptr2_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"pre_rcv_ptr3_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"rep_cmd0_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"rep_cmd1_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"rep_cmd2_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"rep_cmd3_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_mr_states_6_reg[] = + { + {"free_ptr0_fifo_empty", DPP_FIELD_FLAG_RO, 19, 1, 0x1, 0x0}, + {"free_ptr1_fifo_empty", DPP_FIELD_FLAG_RO, 18, 1, 0x1, 0x0}, + {"free_ptr2_fifo_empty", DPP_FIELD_FLAG_RO, 17, 1, 0x1, 0x0}, + {"free_ptr3_fifo_empty", DPP_FIELD_FLAG_RO, 16, 1, 0x1, 0x0}, + {"block_ptr0_fifo_empty", DPP_FIELD_FLAG_RO, 15, 1, 0x1, 0x0}, + {"block_ptr1_fifo_empty", DPP_FIELD_FLAG_RO, 14, 1, 0x1, 0x0}, + {"block_ptr2_fifo_empty", DPP_FIELD_FLAG_RO, 13, 1, 0x1, 0x0}, + {"block_ptr3_fifo_empty", DPP_FIELD_FLAG_RO, 12, 1, 0x1, 0x0}, + {"mgid0_fifo_empty", DPP_FIELD_FLAG_RO, 11, 1, 0x1, 0x0}, + {"mgid1_fifo_empty", DPP_FIELD_FLAG_RO, 10, 1, 0x1, 0x0}, + {"mgid2_fifo_empty", DPP_FIELD_FLAG_RO, 9, 1, 0x1, 0x0}, + {"mgid3_fifo_empty", DPP_FIELD_FLAG_RO, 8, 1, 0x1, 0x0}, + {"pre_rcv_ptr0_fifo_empty", DPP_FIELD_FLAG_RO, 7, 1, 0x1, 0x0}, + {"pre_rcv_ptr1_fifo_empty", DPP_FIELD_FLAG_RO, 6, 1, 0x1, 0x0}, + {"pre_rcv_ptr2_fifo_empty", DPP_FIELD_FLAG_RO, 5, 1, 0x1, 0x0}, + {"pre_rcv_ptr3_fifo_empty", DPP_FIELD_FLAG_RO, 4, 1, 0x1, 0x0}, + {"rep_cmd0_fifo_empty", DPP_FIELD_FLAG_RO, 3, 1, 0x1, 0x0}, + {"rep_cmd1_fifo_empty", DPP_FIELD_FLAG_RO, 2, 1, 0x1, 0x0}, + {"rep_cmd2_fifo_empty", DPP_FIELD_FLAG_RO, 1, 1, 0x1, 0x0}, + {"rep_cmd3_fifo_empty", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_mr_states_7_reg[] = + { + {"cos0_is_rep_busy", DPP_FIELD_FLAG_RO, 21, 1, 0x0, 0x0}, + {"cos1_is_rep_busy", DPP_FIELD_FLAG_RO, 20, 1, 0x0, 0x0}, + {"cos2_is_rep_busy", DPP_FIELD_FLAG_RO, 19, 1, 0x0, 0x0}, + {"cos3_is_rep_busy", DPP_FIELD_FLAG_RO, 18, 1, 0x0, 0x0}, + {"block_ptr0_fifo_non_sop_ren_rdy", DPP_FIELD_FLAG_RO, 17, 1, 0x0, 0x0}, + {"block_ptr1_fifo_non_sop_ren_rdy", DPP_FIELD_FLAG_RO, 16, 1, 0x0, 0x0}, + {"block_ptr2_fifo_non_sop_ren_rdy", DPP_FIELD_FLAG_RO, 15, 1, 0x0, 0x0}, + {"block_ptr3_fifo_non_sop_ren_rdy", DPP_FIELD_FLAG_RO, 14, 1, 0x0, 0x0}, + {"pre_rcv_ptr0_fifo_non_sop_ren_rdy", DPP_FIELD_FLAG_RO, 13, 1, 0x0, 0x0}, + {"pre_rcv_ptr1_fifo_non_sop_ren_rdy", DPP_FIELD_FLAG_RO, 12, 1, 0x0, 0x0}, + {"pre_rcv_ptr2_fifo_non_sop_ren_rdy", DPP_FIELD_FLAG_RO, 11, 1, 0x0, 0x0}, + {"pre_rcv_ptr3_fifo_non_sop_ren_rdy", DPP_FIELD_FLAG_RO, 10, 1, 0x0, 0x0}, + {"port_shap_rdy", DPP_FIELD_FLAG_RO, 9, 1, 0x1, 0x0}, + {"mr_lif_group0_rdy_3", DPP_FIELD_FLAG_RO, 8, 1, 0x1, 0x0}, + {"mr_lif_group0_rdy_2", DPP_FIELD_FLAG_RO, 7, 1, 0x1, 0x0}, + {"mr_lif_group0_rdy_1", DPP_FIELD_FLAG_RO, 6, 1, 0x1, 0x0}, + {"mr_lif_group0_rdy_0", DPP_FIELD_FLAG_RO, 5, 1, 0x1, 0x0}, + {"pktrx_pfc_rdy_3", DPP_FIELD_FLAG_RO, 4, 1, 0x1, 0x0}, + {"pktrx_pfc_rdy_2", DPP_FIELD_FLAG_RO, 3, 1, 0x1, 0x0}, + {"pktrx_pfc_rdy_1", DPP_FIELD_FLAG_RO, 2, 1, 0x1, 0x0}, + {"pktrx_pfc_rdy_0", DPP_FIELD_FLAG_RO, 1, 1, 0x1, 0x0}, + {"pktrx_link_rdy", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_mr_states_8_reg[] = + { + {"mr_head", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_mr_sop_in_cnt_reg[] = + { + {"mr_sop_in_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_mr_eop_in_cnt_reg[] = + { + {"mr_eop_in_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_mr_sop_out_cnt_reg[] = + { + {"mr_sop_out_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_mr_eop_out_cnt_reg[] = + { + {"mr_eop_out_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_mr_cos0_in_cnt_reg[] = + { + {"mr_cos0_in_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_mr_cos1_in_cnt_reg[] = + { + {"mr_cos1_in_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_mr_cos2_in_cnt_reg[] = + { + {"mr_cos2_in_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_mr_cos3_in_cnt_reg[] = + { + {"mr_cos3_in_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_mr_cos0_out_cnt_reg[] = + { + {"mr_cos0_out_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_mr_cos1_out_cnt_reg[] = + { + {"mr_cos1_out_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_mr_cos2_out_cnt_reg[] = + { + {"mr_cos2_out_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_mr_cos3_out_cnt_reg[] = + { + {"mr_cos3_out_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_mr_err_in_cnt_reg[] = + { + {"mr_err_in_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_mr_cos0_sop_in_cnt_reg[] = + { + {"mr_cos0_sop_in_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_mr_cos0_eop_in_cnt_reg[] = + { + {"mr_cos0_eop_in_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_mr_cos1_sop_in_cnt_reg[] = + { + {"mr_cos1_sop_in_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_mr_cos1_eop_in_cnt_reg[] = + { + {"mr_cos1_eop_in_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_mr_cos2_sop_in_cnt_reg[] = + { + {"mr_cos2_sop_in_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_mr_cos2_eop_in_cnt_reg[] = + { + {"mr_cos2_eop_in_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_mr_cos3_sop_in_cnt_reg[] = + { + {"mr_cos3_sop_in_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_mr_cos3_eop_in_cnt_reg[] = + { + {"mr_cos3_eop_in_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_mr_cos0_in_err_cnt_reg[] = + { + {"mr_cos0_in_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_mr_cos1_in_err_cnt_reg[] = + { + {"mr_cos1_in_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_mr_cos2_in_err_cnt_reg[] = + { + {"mr_cos2_in_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_mr_cos3_in_err_cnt_reg[] = + { + {"mr_cos3_in_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_mr_cos0_sop_out_cnt_reg[] = + { + {"mr_cos0_sop_out_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_mr_cos0_eop_out_cnt_reg[] = + { + {"mr_cos0_eop_out_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_mr_cos1_sop_out_cnt_reg[] = + { + {"mr_cos1_sop_out_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_mr_cos1_eop_out_cnt_reg[] = + { + {"mr_cos1_eop_out_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_mr_cos2_sop_out_cnt_reg[] = + { + {"mr_cos2_sop_out_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_mr_cos2_eop_out_cnt_reg[] = + { + {"mr_cos2_eop_out_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_mr_cos3_sop_out_cnt_reg[] = + { + {"mr_cos3_sop_out_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_mr_cos3_eop_out_cnt_reg[] = + { + {"mr_cos3_eop_out_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_mr_mlt_unvld_cnt_reg[] = + { + {"mr_mlt_unvld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_mr_sop_eop_match_cfg_reg[] = + { + {"mr_sop_eop_macth_en", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"mr_sop_eop_macth_dicard_th", DPP_FIELD_FLAG_RW, 7, 8, 0xbc, 0x0}, + }; +DPP_FIELD_T g_nppu_mr_cfg_mr_mlt_unvld_mgid_reg[] = + { + {"mr_mlt_unvld_mgid", DPP_FIELD_FLAG_RO, 16, 17, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_isch_fifo_th_1_reg[] = + { + {"cfg_sch_fifo7_fc_th", DPP_FIELD_FLAG_RW, 29, 6, 0x30, 0x0}, + {"cfg_sch_fifo6_fc_th", DPP_FIELD_FLAG_RW, 21, 6, 0x30, 0x0}, + {"cfg_sch_fifo5_fc_th", DPP_FIELD_FLAG_RW, 13, 6, 0x30, 0x0}, + {"cfg_sch_fifo4_fc_th", DPP_FIELD_FLAG_RW, 5, 6, 0x30, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_isch_fifo_th_2_reg[] = + { + {"cfg_sch_fifo3_drop_th", DPP_FIELD_FLAG_RW, 29, 6, 0x38, 0x0}, + {"cfg_sch_fifo1_drop_th", DPP_FIELD_FLAG_RW, 21, 6, 0x38, 0x0}, + {"cfg_sch_fifo0_drop_th", DPP_FIELD_FLAG_RW, 13, 6, 0x38, 0x0}, + {"cfg_sch_fifo8_fc_th", DPP_FIELD_FLAG_RW, 5, 6, 0x30, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_isch_fifo_th_3_reg[] = + { + {"cfg_sch_fifo6_drop_th", DPP_FIELD_FLAG_RW, 29, 6, 0x38, 0x0}, + {"cfg_sch_fifo5_drop_th", DPP_FIELD_FLAG_RW, 21, 6, 0x38, 0x0}, + {"cfg_sch_fifo4_drop_th", DPP_FIELD_FLAG_RW, 13, 6, 0x38, 0x0}, + {"cfg_sch_fifo2_drop_th", DPP_FIELD_FLAG_RW, 5, 6, 0x38, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_isch_fifo_th_4_reg[] = + { + {"cfg_sch_fifo9_fc_th", DPP_FIELD_FLAG_RW, 29, 6, 0x30, 0x0}, + {"cfg_sch_fifo9_drop_th", DPP_FIELD_FLAG_RW, 21, 6, 0x38, 0x0}, + {"cfg_sch_fifo8_drop_th", DPP_FIELD_FLAG_RW, 13, 6, 0x38, 0x0}, + {"cfg_sch_fifo7_drop_th", DPP_FIELD_FLAG_RW, 5, 6, 0x38, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_isch_cfg_0_reg[] = + { + {"cfg_sch_wrr1_weight1", DPP_FIELD_FLAG_RW, 6, 7, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_hdu_ex_tpid_0_reg[] = + { + {"cfg_type0", DPP_FIELD_FLAG_RW, 31, 16, 0x8100, 0x0}, + {"cfg_type1", DPP_FIELD_FLAG_RW, 15, 16, 0x9100, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_hdu_ex_tpid_1_reg[] = + { + {"cfg_type2", DPP_FIELD_FLAG_RW, 31, 16, 0x88a8, 0x0}, + {"cfg_type3", DPP_FIELD_FLAG_RW, 15, 16, 0x9200, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_hdu_int_tpid_0_reg[] = + { + {"cfg_inner_type0", DPP_FIELD_FLAG_RW, 31, 16, 0x8100, 0x0}, + {"cfg_inner_type1", DPP_FIELD_FLAG_RW, 15, 16, 0x9100, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_hdu_int_tpid_1_reg[] = + { + {"cfg_inner_type2", DPP_FIELD_FLAG_RW, 31, 16, 0x88a8, 0x0}, + {"cfg_inner_type3", DPP_FIELD_FLAG_RW, 15, 16, 0x9200, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_hdu_hdlc_0_reg[] = + { + {"hdlc_cfg0_type", DPP_FIELD_FLAG_RW, 31, 16, 0x0, 0x0}, + {"hdlc_cfg1_type", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_hdu_hdlc_1_reg[] = + { + {"hdlc_cfg2_type", DPP_FIELD_FLAG_RW, 31, 16, 0x0, 0x0}, + {"hdlc_cfg3_type", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_hdu_udf_l3type_0_reg[] = + { + {"cfg_l3_type0", DPP_FIELD_FLAG_RW, 31, 16, 0xffff, 0x0}, + {"cfg_l3_type1", DPP_FIELD_FLAG_RW, 15, 16, 0xffff, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_hdu_udf_l3type_1_reg[] = + { + {"cfg_l3_type2", DPP_FIELD_FLAG_RW, 31, 16, 0xffff, 0x0}, + {"cfg_l3_type3", DPP_FIELD_FLAG_RW, 15, 16, 0xffff, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_hdu_udf_l3type_2_reg[] = + { + {"cfg_l3_type4", DPP_FIELD_FLAG_RW, 31, 16, 0xffff, 0x0}, + {"cfg_l3_type5", DPP_FIELD_FLAG_RW, 15, 16, 0xffff, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_hdu_udf_l3type_3_reg[] = + { + {"cfg_l3_type6", DPP_FIELD_FLAG_RW, 31, 16, 0xffff, 0x0}, + {"cfg_l3_type7", DPP_FIELD_FLAG_RW, 15, 16, 0xffff, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_hdu_udf_l4type_0_reg[] = + { + {"cfg_l4_type0", DPP_FIELD_FLAG_RW, 31, 8, 0xff, 0x0}, + {"cfg_l4_type1", DPP_FIELD_FLAG_RW, 23, 8, 0xff, 0x0}, + {"cfg_l4_type2", DPP_FIELD_FLAG_RW, 15, 8, 0xff, 0x0}, + {"cfg_l4_type3", DPP_FIELD_FLAG_RW, 7, 8, 0xff, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_hdu_udf_l4type_1_reg[] = + { + {"cfg_l4_type4", DPP_FIELD_FLAG_RW, 31, 8, 0xff, 0x0}, + {"cfg_l4_type5", DPP_FIELD_FLAG_RW, 23, 8, 0xff, 0x0}, + {"cfg_l4_type6", DPP_FIELD_FLAG_RW, 15, 8, 0xff, 0x0}, + {"cfg_l4_type7", DPP_FIELD_FLAG_RW, 7, 8, 0xff, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_hdu_udf_l4type_2_reg[] = + { + {"cfg_l4_type8", DPP_FIELD_FLAG_RW, 23, 8, 0xff, 0x0}, + {"cfg_l4_type9", DPP_FIELD_FLAG_RW, 15, 8, 0xff, 0x0}, + {"cfg_l4_type10", DPP_FIELD_FLAG_RW, 7, 8, 0xff, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_slot_no_cfg_reg[] = + { + {"cfg_parser_slot_no", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_pktrx_int_en_0_reg[] = + { + {"pktrx_int_en_31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0}, + {"pktrx_int_en_30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0}, + {"pktrx_int_en_29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0}, + {"pktrx_int_en_28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0}, + {"pktrx_int_en_27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0}, + {"pktrx_int_en_26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0}, + {"pktrx_int_en_25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0}, + {"pktrx_int_en_24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0}, + {"pktrx_int_en_23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0}, + {"pktrx_int_en_22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0}, + {"pktrx_int_en_21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0}, + {"pktrx_int_en_20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"pktrx_int_en_19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0}, + {"pktrx_int_en_18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + {"pktrx_int_en_17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0}, + {"pktrx_int_en_16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"pktrx_int_en_15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"pktrx_int_en_14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"pktrx_int_en_13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"pktrx_int_en_12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"pktrx_int_en_11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"pktrx_int_en_10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"pktrx_int_en_9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"pktrx_int_en_8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"pktrx_int_en_7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"pktrx_int_en_6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"pktrx_int_en_5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"pktrx_int_en_4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"pktrx_int_en_3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"pktrx_int_en_2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"pktrx_int_en_1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"pktrx_int_en_0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_pktrx_int_en_1_reg[] = + { + {"pktrx_int_en_35", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"pktrx_int_en_34", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"pktrx_int_en_33", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"pktrx_int_en_32", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_pktrx_int_mask_0_reg[] = + { + {"pktrx_int_mask_31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0}, + {"pktrx_int_mask_30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0}, + {"pktrx_int_mask_29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0}, + {"pktrx_int_mask_28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0}, + {"pktrx_int_mask_27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0}, + {"pktrx_int_mask_26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0}, + {"pktrx_int_mask_25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0}, + {"pktrx_int_mask_24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0}, + {"pktrx_int_mask_23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0}, + {"pktrx_int_mask_22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0}, + {"pktrx_int_mask_21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0}, + {"pktrx_int_mask_20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"pktrx_int_mask_19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0}, + {"pktrx_int_mask_18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + {"pktrx_int_mask_17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0}, + {"pktrx_int_mask_16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"pktrx_int_mask_15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"pktrx_int_mask_14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"pktrx_int_mask_13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"pktrx_int_mask_12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"pktrx_int_mask_11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"pktrx_int_mask_10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"pktrx_int_mask_9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"pktrx_int_mask_8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"pktrx_int_mask_7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"pktrx_int_mask_6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"pktrx_int_mask_5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"pktrx_int_mask_4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"pktrx_int_mask_3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"pktrx_int_mask_2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"pktrx_int_mask_1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"pktrx_int_mask_0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_pktrx_int_mask_1_reg[] = + { + {"pktrx_int_mask_35", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"pktrx_int_mask_34", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"pktrx_int_mask_33", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"pktrx_int_mask_32", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_pktrx_int_status_reg[] = + { + {"int_status", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_pktrx_port_rdy0_reg[] = + { + {"pktrx_trpgrx_r1_rdy", DPP_FIELD_FLAG_RO, 31, 10, 0x3ff, 0x0}, + {"pktrx_trpgrx_r2_rdy", DPP_FIELD_FLAG_RO, 4, 5, 0x1f, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy0_reg[] = + { + {"pktrx_trpgrx_r1_pfc_rdy_0", DPP_FIELD_FLAG_RO, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy1_reg[] = + { + {"pktrx_trpgrx_r1_pfc_rdy_1", DPP_FIELD_FLAG_RO, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy2_reg[] = + { + {"pktrx_trpgrx_r1_pfc_rdy_2", DPP_FIELD_FLAG_RO, 31, 16, 0xffff, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy3_reg[] = + { + {"pktrx_trpgrx_r2_pfc_rdy_3", DPP_FIELD_FLAG_RO, 31, 8, 0xf, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy4_reg[] = + { + {"pktrx_trpgrx_r2_pfc_rdy_4", DPP_FIELD_FLAG_RO, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy5_reg[] = + { + {"pktrx_trpgrx_r2_pfc_rdy_5", DPP_FIELD_FLAG_RO, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy6_reg[] = + { + {"pktrx_trpgrx_r2_pfc_rdy_6", DPP_FIELD_FLAG_RO, 31, 24, 0xffffff, 0x0}, + }; +DPP_FIELD_T g_nppu_pktrx_cfg_cfg_port_l2_offset_mode_reg[] = + { + {"cfg_port_l2_offset_mode", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_idma_cfg_int_ram_en_reg[] = + { + {"phy_sts_parity_err", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"ptr_buf_parity_err", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_idma_cfg_int_ram_mask_reg[] = + { + {"phy_sts_parity_err", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"ptr_buf_parity_err", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_idma_cfg_int_ram_status_reg[] = + { + {"phy_sts_parity_err", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0}, + {"ptr_buf_parity_err", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_idma_cfg_subsys_int_mask_flag_reg[] = + { + {"subsys_int_mask_flag", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_idma_cfg_subsys_int_unmask_flag_reg[] = + { + {"subsys_int_unmask_flag", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_idma_cfg_debug_cnt_rdclr_mode_reg[] = + { + {"debug_cnt_rdclr_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_int_ram_en0_reg[] = + { + {"int_ram_en_31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0}, + {"int_ram_en_30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0}, + {"int_ram_en_29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0}, + {"int_ram_en_28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0}, + {"int_ram_en_27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0}, + {"int_ram_en_26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0}, + {"int_ram_en_25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0}, + {"int_ram_en_24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0}, + {"int_ram_en_23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0}, + {"int_ram_en_22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0}, + {"int_ram_en_21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0}, + {"int_ram_en_20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"int_ram_en_19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0}, + {"int_ram_en_18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + {"int_ram_en_17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0}, + {"int_ram_en_16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"int_ram_en_15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"int_ram_en_14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"int_ram_en_13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"int_ram_en_12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"int_ram_en_11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"int_ram_en_10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"int_ram_en_9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"int_ram_en_8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"int_ram_en_7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"int_ram_en_6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"int_ram_en_5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"int_ram_en_4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"int_ram_en_3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"int_ram_en_2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"int_ram_en_1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"int_ram_en_0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_int_ram_mask0_reg[] = + { + {"int_ram_mask_31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0}, + {"int_ram_mask_30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0}, + {"int_ram_mask_29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0}, + {"int_ram_mask_28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0}, + {"int_ram_mask_27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0}, + {"int_ram_mask_26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0}, + {"int_ram_mask_25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0}, + {"int_ram_mask_24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0}, + {"int_ram_mask_23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0}, + {"int_ram_mask_22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0}, + {"int_ram_mask_21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0}, + {"int_ram_mask_20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"int_ram_mask_19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0}, + {"int_ram_mask_18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + {"int_ram_mask_17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0}, + {"int_ram_mask_16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"int_ram_mask_15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"int_ram_mask_14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"int_ram_mask_13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"int_ram_mask_12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"int_ram_mask_11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"int_ram_mask_10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"int_ram_mask_9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"int_ram_mask_8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"int_ram_mask_7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"int_ram_mask_6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"int_ram_mask_5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"int_ram_mask_4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"int_ram_mask_3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"int_ram_mask_2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"int_ram_mask_1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"int_ram_mask_0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_int_ram_status0_reg[] = + { + {"int_ram_status_31", DPP_FIELD_FLAG_RO, 31, 1, 0x0, 0x0}, + {"int_ram_status_30", DPP_FIELD_FLAG_RO, 30, 1, 0x0, 0x0}, + {"int_ram_status_29", DPP_FIELD_FLAG_RO, 29, 1, 0x0, 0x0}, + {"int_ram_status_28", DPP_FIELD_FLAG_RO, 28, 1, 0x0, 0x0}, + {"int_ram_status_27", DPP_FIELD_FLAG_RO, 27, 1, 0x0, 0x0}, + {"int_ram_status_26", DPP_FIELD_FLAG_RO, 26, 1, 0x0, 0x0}, + {"int_ram_status_25", DPP_FIELD_FLAG_RO, 25, 1, 0x0, 0x0}, + {"int_ram_status_24", DPP_FIELD_FLAG_RO, 24, 1, 0x0, 0x0}, + {"int_ram_status_23", DPP_FIELD_FLAG_RO, 23, 1, 0x0, 0x0}, + {"int_ram_status_22", DPP_FIELD_FLAG_RO, 22, 1, 0x0, 0x0}, + {"int_ram_status_21", DPP_FIELD_FLAG_RO, 21, 1, 0x0, 0x0}, + {"int_ram_status_20", DPP_FIELD_FLAG_RO, 20, 1, 0x0, 0x0}, + {"int_ram_status_19", DPP_FIELD_FLAG_RO, 19, 1, 0x0, 0x0}, + {"int_ram_status_18", DPP_FIELD_FLAG_RO, 18, 1, 0x0, 0x0}, + {"int_ram_status_17", DPP_FIELD_FLAG_RO, 17, 1, 0x0, 0x0}, + {"int_ram_status_16", DPP_FIELD_FLAG_RO, 16, 1, 0x0, 0x0}, + {"int_ram_status_15", DPP_FIELD_FLAG_RO, 15, 1, 0x0, 0x0}, + {"int_ram_status_14", DPP_FIELD_FLAG_RO, 14, 1, 0x0, 0x0}, + {"int_ram_status_13", DPP_FIELD_FLAG_RO, 13, 1, 0x0, 0x0}, + {"int_ram_status_12", DPP_FIELD_FLAG_RO, 12, 1, 0x0, 0x0}, + {"int_ram_status_11", DPP_FIELD_FLAG_RO, 11, 1, 0x0, 0x0}, + {"int_ram_status_10", DPP_FIELD_FLAG_RO, 10, 1, 0x0, 0x0}, + {"int_ram_status_9", DPP_FIELD_FLAG_RO, 9, 1, 0x0, 0x0}, + {"int_ram_status_8", DPP_FIELD_FLAG_RO, 8, 1, 0x0, 0x0}, + {"int_ram_status_7", DPP_FIELD_FLAG_RO, 7, 1, 0x0, 0x0}, + {"int_ram_status_6", DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0}, + {"int_ram_status_5", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0}, + {"int_ram_status_4", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0}, + {"int_ram_status_3", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0}, + {"int_ram_status_2", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0}, + {"int_ram_status_1", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0}, + {"int_ram_status_0", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_int_fifo_en0_reg[] = + { + {"int_fifo_en_31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0}, + {"int_fifo_en_30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0}, + {"int_fifo_en_29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0}, + {"int_fifo_en_28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0}, + {"int_fifo_en_27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0}, + {"int_fifo_en_26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0}, + {"int_fifo_en_25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0}, + {"int_fifo_en_24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0}, + {"int_fifo_en_23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0}, + {"int_fifo_en_22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0}, + {"int_fifo_en_21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0}, + {"int_fifo_en_20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"int_fifo_en_19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0}, + {"int_fifo_en_18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + {"int_fifo_en_17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0}, + {"int_fifo_en_16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"int_fifo_en_15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"int_fifo_en_14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"int_fifo_en_13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"int_fifo_en_12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"int_fifo_en_11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"int_fifo_en_10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"int_fifo_en_9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"int_fifo_en_8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"int_fifo_en_7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"int_fifo_en_6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"int_fifo_en_5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"int_fifo_en_4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"int_fifo_en_3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"int_fifo_en_2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"int_fifo_en_1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"int_fifo_en_0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_int_fifo_en1_reg[] = + { + {"int_fifo_en_35", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"int_fifo_en_34", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"int_fifo_en_33", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"int_fifo_en_32", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_int_fifo_mask0_reg[] = + { + {"int_fifo_mask_31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0}, + {"int_fifo_mask_30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0}, + {"int_fifo_mask_29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0}, + {"int_fifo_mask_28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0}, + {"int_fifo_mask_27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0}, + {"int_fifo_mask_26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0}, + {"int_fifo_mask_25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0}, + {"int_fifo_mask_24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0}, + {"int_fifo_mask_23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0}, + {"int_fifo_mask_22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0}, + {"int_fifo_mask_21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0}, + {"int_fifo_mask_20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"int_fifo_mask_19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0}, + {"int_fifo_mask_18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + {"int_fifo_mask_17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0}, + {"int_fifo_mask_16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"int_fifo_mask_15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"int_fifo_mask_14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"int_fifo_mask_13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"int_fifo_mask_12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"int_fifo_mask_11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"int_fifo_mask_10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"int_fifo_mask_9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"int_fifo_mask_8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"int_fifo_mask_7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"int_fifo_mask_6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"int_fifo_mask_5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"int_fifo_mask_4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"int_fifo_mask_3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"int_fifo_mask_2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"int_fifo_mask_1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"int_fifo_mask_0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_int_fifo_mask1_reg[] = + { + {"int_fifo_mask_35", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"int_fifo_mask_34", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"int_fifo_mask_33", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"int_fifo_mask_32", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_int_fifo_status0_reg[] = + { + {"int_fifo_status_31", DPP_FIELD_FLAG_RO, 31, 1, 0x0, 0x0}, + {"int_fifo_status_30", DPP_FIELD_FLAG_RO, 30, 1, 0x0, 0x0}, + {"int_fifo_status_29", DPP_FIELD_FLAG_RO, 29, 1, 0x0, 0x0}, + {"int_fifo_status_28", DPP_FIELD_FLAG_RO, 28, 1, 0x0, 0x0}, + {"int_fifo_status_27", DPP_FIELD_FLAG_RO, 27, 1, 0x0, 0x0}, + {"int_fifo_status_26", DPP_FIELD_FLAG_RO, 26, 1, 0x0, 0x0}, + {"int_fifo_status_25", DPP_FIELD_FLAG_RO, 25, 1, 0x0, 0x0}, + {"int_fifo_status_24", DPP_FIELD_FLAG_RO, 24, 1, 0x0, 0x0}, + {"int_fifo_status_23", DPP_FIELD_FLAG_RO, 23, 1, 0x0, 0x0}, + {"int_fifo_status_22", DPP_FIELD_FLAG_RO, 22, 1, 0x0, 0x0}, + {"int_fifo_status_21", DPP_FIELD_FLAG_RO, 21, 1, 0x0, 0x0}, + {"int_fifo_status_20", DPP_FIELD_FLAG_RO, 20, 1, 0x0, 0x0}, + {"int_fifo_status_19", DPP_FIELD_FLAG_RO, 19, 1, 0x0, 0x0}, + {"int_fifo_status_18", DPP_FIELD_FLAG_RO, 18, 1, 0x0, 0x0}, + {"int_fifo_status_17", DPP_FIELD_FLAG_RO, 17, 1, 0x0, 0x0}, + {"int_fifo_status_16", DPP_FIELD_FLAG_RO, 16, 1, 0x0, 0x0}, + {"int_fifo_status_15", DPP_FIELD_FLAG_RO, 15, 1, 0x0, 0x0}, + {"int_fifo_status_14", DPP_FIELD_FLAG_RO, 14, 1, 0x0, 0x0}, + {"int_fifo_status_13", DPP_FIELD_FLAG_RO, 13, 1, 0x0, 0x0}, + {"int_fifo_status_12", DPP_FIELD_FLAG_RO, 12, 1, 0x0, 0x0}, + {"int_fifo_status_11", DPP_FIELD_FLAG_RO, 11, 1, 0x0, 0x0}, + {"int_fifo_status_10", DPP_FIELD_FLAG_RO, 10, 1, 0x0, 0x0}, + {"int_fifo_status_9", DPP_FIELD_FLAG_RO, 9, 1, 0x0, 0x0}, + {"int_fifo_status_8", DPP_FIELD_FLAG_RO, 8, 1, 0x0, 0x0}, + {"int_fifo_status_7", DPP_FIELD_FLAG_RO, 7, 1, 0x0, 0x0}, + {"int_fifo_status_6", DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0}, + {"int_fifo_status_5", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0}, + {"int_fifo_status_4", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0}, + {"int_fifo_status_3", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0}, + {"int_fifo_status_2", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0}, + {"int_fifo_status_1", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0}, + {"int_fifo_status_0", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_int_fifo_status1_reg[] = + { + {"int_fifo_status_35", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0}, + {"int_fifo_status_34", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0}, + {"int_fifo_status_33", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0}, + {"int_fifo_status_32", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_subsys_int_mask_flag_reg[] = + { + {"subsys_int_mask_flag", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_subsys_int_unmask_flag_reg[] = + { + {"subsys_int_unmask_flag", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_sa_ip_en_reg[] = + { + {"sa_ip_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_debug_cnt_rdclr_mode_reg[] = + { + {"debug_cnt_rdclr_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_fptr_fifo_aful_assert_cfg_reg[] = + { + {"fptr_fifo_aful_assert_cfg", DPP_FIELD_FLAG_RW, 12, 13, 0xff0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_fptr_fifo_aful_negate_cfg_reg[] = + { + {"fptr_fifo_aful_negate_cfg", DPP_FIELD_FLAG_RW, 12, 13, 0xff0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_pf_fifo_aful_assert_cfg_reg[] = + { + {"pf_fifo_aful_assert_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x8, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_pf_fifo_aful_negate_cfg_reg[] = + { + {"pf_fifo_aful_negate_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x8, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_pf_fifo_aept_assert_cfg_reg[] = + { + {"pf_fifo_aept_assert_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x4, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_pf_fifo_aept_negate_cfg_reg[] = + { + {"pf_fifo_aept_negate_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x4, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_wb_aful_assert_cfg_reg[] = + { + {"wb_aful_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x12, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_wb_aful_negate_cfg_reg[] = + { + {"wb_aful_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x12, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_se_key_aful_assert_cfg_reg[] = + { + {"se_key_aful_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_ifbrd_se_aful_assert_cfg_reg[] = + { + {"ifbrd_se_aful_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x18, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_ifbrd_se_aful_negate_cfg_reg[] = + { + {"ifbrd_se_aful_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x18, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_ifbrd_odma_aful_assert_cfg_reg[] = + { + {"ifbrd_odma_aful_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x18, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_ifbrd_odma_aful_negate_cfg_reg[] = + { + {"ifbrd_odma_aful_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x18, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_ifbrd_ppu_aful_assert_cfg_reg[] = + { + {"ifbrd_ppu_aful_assert_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x10, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_ifbrd_ppu_aful_negate_cfg_reg[] = + { + {"ifbrd_ppu_aful_negate_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x10, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_mc_logic_aful_assert_cfg_reg[] = + { + {"mc_logic_aful_assert_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x10, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_mc_logic_aful_negate_cfg_reg[] = + { + {"mc_logic_aful_negate_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x10, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_mc_logic_diff_reg[] = + { + {"mc_logic_diff", DPP_FIELD_FLAG_RW, 7, 8, 0xa, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_cfg_peak_port_cnt_clr_reg[] = + { + {"cfg_peak_port_cnt_clr", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_all_ftm_crdt_th_reg[] = + { + {"ftm_crdt_port_cng_th", DPP_FIELD_FLAG_RW, 29, 15, 0x0, 0x0}, + {"ftm_crdt_port_th", DPP_FIELD_FLAG_RW, 14, 15, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_all_ftm_link_th_01_reg[] = + { + {"total_congest_th1", DPP_FIELD_FLAG_RW, 29, 15, 0x0, 0x0}, + {"total_congest_th0", DPP_FIELD_FLAG_RW, 14, 15, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_all_ftm_link_th_23_reg[] = + { + {"total_congest_th3", DPP_FIELD_FLAG_RW, 29, 15, 0x0, 0x0}, + {"total_congest_th2", DPP_FIELD_FLAG_RW, 14, 15, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_all_ftm_link_th_45_reg[] = + { + {"total_congest_th5", DPP_FIELD_FLAG_RW, 29, 15, 0x0, 0x0}, + {"total_congest_th4", DPP_FIELD_FLAG_RW, 14, 15, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_all_ftm_link_th_6_reg[] = + { + {"total_congest_th6", DPP_FIELD_FLAG_RW, 14, 15, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_all_ftm_total_congest_th_reg[] = + { + {"all_ftm_total_congest_th", DPP_FIELD_FLAG_RW, 14, 15, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_cfg_crdt_mode_reg[] = + { + {"cfg_crdt_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_cfg_pfc_rdy_high_time_reg[] = + { + {"cfg_pfc_rdy_high_time", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_cfg_cfg_pfc_rdy_low_time_reg[] = + { + {"cfg_pfc_rdy_low_time", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_stat_pbu_fc_rdy_reg[] = + { + {"pbu_oam_send_fc_rdy", DPP_FIELD_FLAG_RO, 7, 2, 0x0, 0x0}, + {"pbu_odma_fc_rdy", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0}, + {"pbu_tm_fc_rdy", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0}, + {"pbu_idma_cos_rdy", DPP_FIELD_FLAG_RO, 1, 2, 0x2, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_stat_pbu_lif_group0_rdy0_reg[] = + { + {"pbu_ipg1_rdy", DPP_FIELD_FLAG_RO, 27, 3, 0x0, 0x0}, + {"pbu_ipg0_rdy", DPP_FIELD_FLAG_RO, 24, 9, 0x0, 0x0}, + {"pbu_trpgrx_xge_rdy", DPP_FIELD_FLAG_RO, 9, 2, 0x0, 0x0}, + {"pbu_trpgrx_cge1_rdy", DPP_FIELD_FLAG_RO, 7, 4, 0x0, 0x0}, + {"pbu_trpgrx_cge0_rdy", DPP_FIELD_FLAG_RO, 3, 4, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_stat_pbu_lif_group0_rdy1_reg[] = + { + {"pbu_lif_group0_rdy1", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_stat_pbu_lif_group1_rdy_reg[] = + { + {"pbu_lif_group1_rdy1", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_stat_pbu_lif_group0_pfc_rdy_reg[] = + { + {"pbu_lif_group0_pfc_rdy", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_stat_pbu_lif_group1_pfc_rdy_reg[] = + { + {"pbu_lif_group1_pfc_rdy", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_stat_pbu_sa_port_rdy_0_31_reg[] = + { + {"pbu_sa_port_rdy_0_31", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_stat_pbu_sa_port_rdy_32_50_reg[] = + { + {"pbu_sa_port_rdy_32_50", DPP_FIELD_FLAG_RO, 18, 19, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_stat_pbu_pktrx_mr_pfc_rdy_reg[] = + { + {"pbu_pktrx_mr_pfc_rdy", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_stat_pbu_ftm_crdt_port_rdy_0_31_reg[] = + { + {"pbu_ftm_crdt_port_rdy_0_31", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_stat_pbu_ftm_crdt_port_rdy_32_47_reg[] = + { + {"pbu_ftm_crdt_port_rdy_32_47", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_stat_pbu_ftm_crdt_port_cng_rdy_0_31_reg[] = + { + {"pbu_ftm_crdt_port_cng_rdy_0_31", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_stat_pbu_ftm_crdt_port_cng_rdy_32_47_reg[] = + { + {"pbu_ftm_crdt_port_cng_rdy_32_47", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_pbu_stat_pbu_ftm_crdt_sys_info_reg[] = + { + {"pbu_ftm_crdt_sys_info", DPP_FIELD_FLAG_RO, 2, 3, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_isu_cfg_weight_normal_mc_reg[] = + { + {"weight_normal_mc", DPP_FIELD_FLAG_RW, 6, 7, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_isu_cfg_weight_sa_mc_reg[] = + { + {"weight_sa_mc", DPP_FIELD_FLAG_RW, 6, 7, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_isu_cfg_weight_etm_reg[] = + { + {"weight_etm", DPP_FIELD_FLAG_RW, 6, 7, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_isu_cfg_weight_lp_mc_reg[] = + { + {"weight_lp_mc", DPP_FIELD_FLAG_RW, 6, 7, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_isu_cfg_weight_oam_reg[] = + { + {"weight_oam", DPP_FIELD_FLAG_RW, 6, 7, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_isu_cfg_weight_lif_ctrl1_reg[] = + { + {"weight_lif_ctrl1", DPP_FIELD_FLAG_RW, 6, 7, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_isu_cfg_weight_lif_ctrl2_reg[] = + { + {"weight_lif_ctrl2", DPP_FIELD_FLAG_RW, 6, 7, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_isu_cfg_ecc_bypass_read_reg[] = + { + {"eccbypass", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_isu_cfg_isu_int_mask_reg[] = + { + {"isu_int_mask", DPP_FIELD_FLAG_RW, 26, 27, 0x7ffffff, 0x0}, + }; +DPP_FIELD_T g_nppu_isu_cfg_cfg_crdt_cycle_reg[] = + { + {"cfg_cycle", DPP_FIELD_FLAG_RW, 5, 6, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_isu_cfg_cfg_crdt_value_reg[] = + { + {"cfg_value", DPP_FIELD_FLAG_RW, 13, 14, 0x216, 0x0}, + }; +DPP_FIELD_T g_nppu_isu_cfg_isu_int_en_reg[] = + { + {"isu_int_en", DPP_FIELD_FLAG_RW, 26, 27, 0x7ffffff, 0x0}, + }; +DPP_FIELD_T g_nppu_isu_cfg_isu_ppu_fifo_fc_reg[] = + { + {"isu_ppu_fifo_fc", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_isu_cfg_isu_int_status_reg[] = + { + {"isu_int_status_26", DPP_FIELD_FLAG_RO, 26, 1, 0x0, 0x0}, + {"isu_int_status_25", DPP_FIELD_FLAG_RO, 25, 1, 0x0, 0x0}, + {"isu_int_status_24", DPP_FIELD_FLAG_RO, 24, 1, 0x0, 0x0}, + {"isu_int_status_23", DPP_FIELD_FLAG_RO, 23, 1, 0x0, 0x0}, + {"isu_int_status_22", DPP_FIELD_FLAG_RO, 22, 1, 0x0, 0x0}, + {"isu_int_status_21", DPP_FIELD_FLAG_RO, 21, 1, 0x0, 0x0}, + {"isu_int_status_20", DPP_FIELD_FLAG_RO, 20, 1, 0x0, 0x0}, + {"isu_int_status_19", DPP_FIELD_FLAG_RO, 19, 1, 0x0, 0x0}, + {"isu_int_status_18", DPP_FIELD_FLAG_RO, 18, 1, 0x0, 0x0}, + {"isu_int_status_17", DPP_FIELD_FLAG_RO, 17, 1, 0x0, 0x0}, + {"isu_int_status_16", DPP_FIELD_FLAG_RO, 16, 1, 0x0, 0x0}, + {"isu_int_status_15", DPP_FIELD_FLAG_RO, 15, 1, 0x0, 0x0}, + {"isu_int_status_14", DPP_FIELD_FLAG_RO, 14, 1, 0x0, 0x0}, + {"isu_int_status_13", DPP_FIELD_FLAG_RO, 13, 1, 0x0, 0x0}, + {"isu_int_status_12", DPP_FIELD_FLAG_RO, 12, 1, 0x0, 0x0}, + {"isu_int_status_11", DPP_FIELD_FLAG_RO, 11, 1, 0x0, 0x0}, + {"isu_int_status_10", DPP_FIELD_FLAG_RO, 10, 1, 0x0, 0x0}, + {"isu_int_status_9", DPP_FIELD_FLAG_RO, 9, 1, 0x0, 0x0}, + {"isu_int_status_8", DPP_FIELD_FLAG_RO, 8, 1, 0x0, 0x0}, + {"isu_int_status_7", DPP_FIELD_FLAG_RO, 7, 1, 0x0, 0x0}, + {"isu_int_status_6", DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0}, + {"isu_int_status_5", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0}, + {"isu_int_status_4", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0}, + {"isu_int_status_3", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0}, + {"isu_int_status_2", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0}, + {"isu_int_status_1", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0}, + {"isu_int_status_0", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_isu_cfg_fd_prog_full_assert_cfg_reg[] = + { + {"fd_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 10, 11, 0x3e8, 0x0}, + }; +DPP_FIELD_T g_nppu_isu_cfg_fd_prog_full_negate_cfg_reg[] = + { + {"fd_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 10, 11, 0x3e8, 0x0}, + }; +DPP_FIELD_T g_nppu_isu_cfg_lp_prog_full_assert_cfg_reg[] = + { + {"lp_prog_ept_assert_cfg", DPP_FIELD_FLAG_RW, 11, 12, 0x80, 0x0}, + }; +DPP_FIELD_T g_nppu_isu_cfg_lp_prog_full_negate_cfg_reg[] = + { + {"lp_prog_ept_negate_cfg", DPP_FIELD_FLAG_RW, 11, 12, 0x80, 0x0}, + }; +DPP_FIELD_T g_nppu_isu_stat_debug_cnt_dat0_reg[] = + { + {"debug_cnt_dat0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_isu_stat_debug_cnt_dat1_reg[] = + { + {"debug_cnt_dat1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_isu_stat_debug_cnt_dat2_reg[] = + { + {"debug_cnt_dat2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_isu_stat_debug_cnt_dat3_reg[] = + { + {"debug_cnt_dat3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_isu_stat_debug_cnt_dat4_reg[] = + { + {"debug_cnt_dat4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_isu_stat_debug_cnt_dat5_reg[] = + { + {"debug_cnt_dat5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_isu_stat_debug_cnt_dat6_reg[] = + { + {"debug_cnt_dat6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_isu_stat_debug_cnt_dat7_reg[] = + { + {"debug_cnt_dat7", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_isu_stat_debug_cnt_dat8_reg[] = + { + {"debug_cnt_dat8", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_isu_stat_debug_cnt_dat9_reg[] = + { + {"debug_cnt_dat9", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_isu_stat_debug_cnt_dat10_reg[] = + { + {"debug_cnt_dat10", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_isu_stat_debug_cnt_dat11_reg[] = + { + {"debug_cnt_dat11", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_isu_stat_debug_cnt_dat12_reg[] = + { + {"debug_cnt_dat12", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_isu_stat_debug_cnt_dat13_reg[] = + { + {"debug_cnt_dat13", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_isu_stat_debug_cnt_dat14_reg[] = + { + {"debug_cnt_dat14", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_isu_stat_debug_cnt_dat15_reg[] = + { + {"debug_cnt_dat15", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_isu_stat_debug_cnt_dat16_reg[] = + { + {"debug_cnt_dat16", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_isu_stat_debug_cnt_dat17_reg[] = + { + {"debug_cnt_dat17", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_isu_stat_debug_cnt_dat18_reg[] = + { + {"debug_cnt_dat18", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_isu_stat_debug_cnt_dat19_reg[] = + { + {"debug_cnt_dat18", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_isu_stat_debug_cnt_cfg_reg[] = + { + {"debug_cnt_ovf_mode", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, + {"debug_cnt_rdclr_mode", DPP_FIELD_FLAG_RW, 30, 1, 0x0, 0x0}, + {"user_cnt_value", DPP_FIELD_FLAG_RW, 29, 4, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_exsa_tdm_offset_reg[] = + { + {"exsa_tdm_offset", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_ecc_bypass_readt_reg[] = + { + {"ecc_bypass_read", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_odma_int_en_0_reg[] = + { + {"odma_int_en_31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0}, + {"odma_int_en_30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0}, + {"odma_int_en_29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0}, + {"odma_int_en_28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0}, + {"odma_int_en_27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0}, + {"odma_int_en_26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0}, + {"odma_int_en_25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0}, + {"odma_int_en_24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0}, + {"odma_int_en_22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0}, + {"odma_int_en_21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0}, + {"odma_int_en_18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_odma_int_en_1_reg[] = + { + {"odma_int_en_63", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0}, + {"odma_int_en_62", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0}, + {"odma_int_en_61", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0}, + {"odma_int_en_59", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0}, + {"odma_int_en_58", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0}, + {"odma_int_en_57", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0}, + {"odma_int_en_56", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0}, + {"odma_int_en_55", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0}, + {"odma_int_en_54", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0}, + {"odma_int_en_53", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0}, + {"odma_int_en_52", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"odma_int_en_51", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0}, + {"odma_int_en_49", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0}, + {"odma_int_en_47", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"odma_int_en_45", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"odma_int_en_39", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"odma_int_en_38", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"odma_int_en_37", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"odma_int_en_36", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"odma_int_en_35", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"odma_int_en_34", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"odma_int_en_33", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"odma_int_en_32", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_odma_int_en_2_reg[] = + { + {"odma_int_en_91", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0}, + {"odma_int_en_88", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0}, + {"odma_int_en_85", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0}, + {"odma_int_en_82", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + {"odma_int_en_79", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"odma_int_en_75", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"odma_int_en_74", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"odma_int_en_71", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"odma_int_en_65", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"odma_int_en_64", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_odma_int_en_3_reg[] = + { + {"odma_int_en_115", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0}, + {"odma_int_en_114", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + {"odma_int_en_112", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"odma_int_en_110", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"odma_int_en_109", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"odma_int_en_108", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"odma_int_en_107", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"odma_int_en_106", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"odma_int_en_102", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"odma_int_en_101", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"odma_int_en_100", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"odma_int_en_98", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"odma_int_en_96", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_odma_int_mask_0_reg[] = + { + {"odma_int_mask_31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0}, + {"odma_int_mask_30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0}, + {"odma_int_mask_29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0}, + {"odma_int_mask_28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0}, + {"odma_int_mask_27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0}, + {"odma_int_mask_26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0}, + {"odma_int_mask_25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0}, + {"odma_int_mask_24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0}, + {"odma_int_mask_22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0}, + {"odma_int_mask_21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0}, + {"odma_int_mask_18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_odma_int_mask_1_reg[] = + { + {"odma_int_mask_63", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0}, + {"odma_int_mask_62", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0}, + {"odma_int_mask_61", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0}, + {"odma_int_mask_59", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0}, + {"odma_int_mask_58", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0}, + {"odma_int_mask_57", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0}, + {"odma_int_mask_56", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0}, + {"odma_int_mask_55", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0}, + {"odma_int_mask_54", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0}, + {"odma_int_mask_53", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0}, + {"odma_int_mask_52", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"odma_int_mask_51", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0}, + {"odma_int_mask_50", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + {"odma_int_mask_49", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0}, + {"odma_int_mask_47", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"odma_int_mask_45", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"odma_int_mask_39", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"odma_int_mask_38", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"odma_int_mask_37", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"odma_int_mask_36", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"odma_int_mask_35", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"odma_int_mask_34", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"odma_int_mask_33", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"odma_int_mask_32", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_odma_int_mask_2_reg[] = + { + {"odma_int_mask_91", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0}, + {"odma_int_mask_88", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0}, + {"odma_int_mask_85", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0}, + {"odma_int_mask_82", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + {"odma_int_mask_79", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"odma_int_mask_75", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"odma_int_mask_74", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"odma_int_mask_71", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"odma_int_mask_65", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"odma_int_mask_64", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_odma_int_mask_3_reg[] = + { + {"odma_int_mask_115", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0}, + {"odma_int_mask_114", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + {"odma_int_mask_112", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"odma_int_mask_110", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"odma_int_mask_109", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"odma_int_mask_108", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"odma_int_mask_107", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"odma_int_mask_106", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"odma_int_mask_102", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"odma_int_mask_101", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"odma_int_mask_100", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"odma_int_mask_98", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"odma_int_mask_96", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_odma_int_status_0_reg[] = + { + {"odma_int_status_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"odma_int_status_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"odma_int_status_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"odma_int_status_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"odma_int_status_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"odma_int_status_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"odma_int_status_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"odma_int_status_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"odma_int_status_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"odma_int_status_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"odma_int_status_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_odma_int_status_1_reg[] = + { + {"odma_int_status_63", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"odma_int_status_62", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"odma_int_status_61", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"odma_int_status_59", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"odma_int_status_58", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"odma_int_status_57", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"odma_int_status_56", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"odma_int_status_55", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"odma_int_status_54", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"odma_int_status_53", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"odma_int_status_52", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"odma_int_status_51", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"odma_int_status_49", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"odma_int_status_47", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"odma_int_status_45", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"odma_int_status_39", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"odma_int_status_38", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"odma_int_status_37", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"odma_int_status_36", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"odma_int_status_35", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"odma_int_status_34", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"odma_int_status_33", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"odma_int_status_32", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_odma_int_status_2_reg[] = + { + {"odma_int_status_91", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"odma_int_status_88", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"odma_int_status_85", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"odma_int_status_82", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"odma_int_status_79", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"odma_int_status_75", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"odma_int_status_74", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"odma_int_status_71", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"odma_int_status_65", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"odma_int_status_64", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_odma_int_status_3_reg[] = + { + {"odma_int_status_117", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"odma_int_status_116", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"odma_int_status_115", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"odma_int_status_114", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"odma_int_status_112", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"odma_int_status_110", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"odma_int_status_109", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"odma_int_status_108", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"odma_int_status_107", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"odma_int_status_106", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"odma_int_status_102", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"odma_int_status_101", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"odma_int_status_100", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"odma_int_status_98", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"odma_int_status_96", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_sp_tdm_err_nor_cfg_reg[] = + { + {"sp_tdm_err_nor_cfg", DPP_FIELD_FLAG_RW, 1, 2, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_etm_dis_ptr_prog_full_cfg_a_reg[] = + { + {"etm_dis_ptr_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_etm_dis_ptr_prog_full_cfg_n_reg[] = + { + {"etm_dis_ptr_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_ftm_dis_ptr_prog_full_cfg_a_reg[] = + { + {"ftm_dis_ptr_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_ftm_dis_ptr_prog_full_cfg_n_reg[] = + { + {"ftm_dis_ptr_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_tm_dis_fifo_prog_full_cfg_a_reg[] = + { + {"tm_dis_fifo_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_tm_dis_fifo_prog_full_cfg_n_reg[] = + { + {"tm_dis_fifo_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_err_prog_full_cfg_a_reg[] = + { + {"err_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_err_prog_full_cfg_n_reg[] = + { + {"err_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_tdmuc_prog_full_cfg_a_reg[] = + { + {"tdmuc_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 10, 11, 0x3e8, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_tdmuc_prog_full_cfg_n_reg[] = + { + {"tdmuc_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 10, 11, 0x3e8, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_tdmmc_groupid_prog_full_cfg_a_reg[] = + { + {"tdmmc_groupid_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 10, 11, 0x3e8, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_tdmmc_groupid_prog_full_cfg_n_reg[] = + { + {"tdmmc_groupid_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 10, 11, 0x3e8, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_tdmmc_no_bitmap_prog_full_cfg_a_reg[] = + { + {"tdmmc_no_bitmap_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 10, 11, 0x3e8, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_tdmmc_no_bitmap_prog_full_cfg_n_reg[] = + { + {"tdmmc_no_bitmap_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 10, 11, 0x3e8, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_tdmmc_prog_full_cfg_a_reg[] = + { + {"tdmmc_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 10, 11, 0x3e8, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_tdmmc_prog_full_cfg_n_reg[] = + { + {"tdmmc_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 10, 11, 0x3e8, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_desc_prog_full_cfg_a_reg[] = + { + {"desc_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 7, 8, 0x64, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_desc_prog_full_cfg_n_reg[] = + { + {"desc_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_dly_prog_full_cfg_a_reg[] = + { + {"dly_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_dly_prog_full_cfg_n_reg[] = + { + {"dly_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_rsp_prog_full_cfg_a_reg[] = + { + {"rsp_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_rsp_prog_full_cfg_n_reg[] = + { + {"rsp_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_nor_prog_full_cfg_a_reg[] = + { + {"nor_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 10, 11, 0x3e8, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_nor_prog_full_cfg_n_reg[] = + { + {"nor_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 10, 11, 0x3e8, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_etm_nor_prog_full_cfg_a_reg[] = + { + {"etm_nor_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_etm_nor_prog_full_cfg_n_reg[] = + { + {"etm_nor_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_ftm_nor_prog_full_cfg_a_reg[] = + { + {"ftm_nor_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_ftm_nor_prog_full_cfg_n_reg[] = + { + {"ftm_nor_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_etm_prog_full_cfg_a_reg[] = + { + {"etm_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_etm_prog_full_cfg_n_reg[] = + { + {"etm_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_ftm_prog_full_cfg_a_reg[] = + { + {"ftm_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_ftm_prog_full_cfg_n_reg[] = + { + {"ftm_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_etm_nrdcnt_prog_full_cfg_a_reg[] = + { + {"etm_nrdcnt_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_etm_nrdcnt_prog_full_cfg_n_reg[] = + { + {"etm_nrdcnt_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_ftm_nrdcnt_prog_full_cfg_a_reg[] = + { + {"ftm_nrdcnt_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_ftm_nrdcnt_prog_full_cfg_n_reg[] = + { + {"ftm_nrdcnt_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_pp_prog_full_cfg_a_reg[] = + { + {"pp_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_pp_prog_full_cfg_n_reg[] = + { + {"pp_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_tm_weight_reg[] = + { + {"tm_weight", DPP_FIELD_FLAG_RW, 6, 7, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_pp_weight_reg[] = + { + {"pp_weight", DPP_FIELD_FLAG_RW, 6, 7, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_ifbcmd_prog_full_cfg_a_reg[] = + { + {"ifbcmd_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 6, 7, 0x32, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_ifbcmd_prog_full_cfg_n_reg[] = + { + {"ifbcmd_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 6, 7, 0x32, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_mccnt_prog_full_cfg_a_reg[] = + { + {"mccnt_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 5, 6, 0x10, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_mccnt_prog_full_cfg_n_reg[] = + { + {"mccnt_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 5, 6, 0x19, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_int_or_pon_reg[] = + { + {"int_or_pon", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_quemng_cnt_in_err_cnt_reg[] = + { + {"quemng_cnt_in_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_lif0_port_eop_cnt_reg[] = + { + {"lif0_port_eop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_lif1_port_eop_cnt_reg[] = + { + {"lif1_port_eop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_lifc_port0_eop_cnt_reg[] = + { + {"lifc_port0_eop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_lifc_port1_eop_cnt_reg[] = + { + {"lifc_port1_eop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_fptr_fifo_prog_ept_cfg_n_reg[] = + { + {"fptr_fifo_prog_ept_cfg_n", DPP_FIELD_FLAG_RW, 14, 15, 0x40, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_isu_fifo_prog_full_cfg_a_reg[] = + { + {"isu_fifo_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 7, 8, 0x60, 0x0}, + }; +DPP_FIELD_T g_nppu_odma_cfg_isu_fifo_prog_full_cfg_n_reg[] = + { + {"isu_fifo_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 7, 8, 0x60, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_ind_access_done_reg[] = + { + {"ind_access_done", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_ind_access_command_reg[] = + { + {"ind_rd_or_wr", DPP_FIELD_FLAG_RW, 21, 1, 0x0, 0x0}, + {"ind_mem_mask", DPP_FIELD_FLAG_RW, 20, 4, 0x0, 0x0}, + {"ind_mem_id", DPP_FIELD_FLAG_RW, 16, 4, 0x0, 0x0}, + {"ind_mem_addr", DPP_FIELD_FLAG_RW, 12, 13, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_ind_dat0_reg[] = + { + {"ind_dat0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_ind_dat1_reg[] = + { + {"ind_dat1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_ind_dat2_reg[] = + { + {"ind_dat2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_ind_dat3_reg[] = + { + {"ind_dat3", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_oam_tx_main_en_reg[] = + { + {"oam_tx_main_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_tx_total_num_reg[] = + { + {"tx_total_num", DPP_FIELD_FLAG_RW, 12, 13, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_oam_chk_main_en_reg[] = + { + {"oam_chk_main_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_chk_total_num0_reg[] = + { + {"chk_total_num0", DPP_FIELD_FLAG_RW, 12, 13, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_ma_chk_main_en_reg[] = + { + {"oam_chk_main_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_chk_total_num1_reg[] = + { + {"chk_total_num0", DPP_FIELD_FLAG_RW, 12, 13, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_tx_stat_en_reg[] = + { + {"tx_stat_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_rec_stat_en_reg[] = + { + {"rec_stat_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_stat_oam_rdy_mask_reg[] = + { + {"stat_oam_rdy_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_session_grading0_reg[] = + { + {"session_grading0", DPP_FIELD_FLAG_RW, 2, 3, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_session_grading1_reg[] = + { + {"session_grading1", DPP_FIELD_FLAG_RW, 2, 3, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_session_grading2_reg[] = + { + {"session_grading2", DPP_FIELD_FLAG_RW, 2, 3, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_session_grading3_reg[] = + { + {"session_grading3", DPP_FIELD_FLAG_RW, 2, 3, 0x7, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_bfd_chk_haddr_reg[] = + { + {"bfd_chk_haddr", DPP_FIELD_FLAG_RW, 11, 12, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_ethccm_chk_haddr_reg[] = + { + {"ethccm_chk_haddr", DPP_FIELD_FLAG_RW, 11, 12, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_tpbfd_chk_haddr_reg[] = + { + {"tpbfd_chk_haddr", DPP_FIELD_FLAG_RW, 11, 12, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_tpoam_ccm_chk_haddr_reg[] = + { + {"tpoam_ccm_chk_haddr", DPP_FIELD_FLAG_RW, 11, 12, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_bfd_tx_haddr_reg[] = + { + {"bfd_tx_haddr", DPP_FIELD_FLAG_RW, 11, 12, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_ethccm_tx_haddr_reg[] = + { + {"ethccm_tx_haddr", DPP_FIELD_FLAG_RW, 11, 12, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_tpbfd_tx_haddr_reg[] = + { + {"tpbfd_tx_haddr", DPP_FIELD_FLAG_RW, 11, 12, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_tpoam_ccm_tx_haddr_reg[] = + { + {"tpoam_ccm_tx_haddr", DPP_FIELD_FLAG_RW, 11, 12, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_ethccm_ma_chk_haddr_reg[] = + { + {"ethccm_ma_chk_haddr", DPP_FIELD_FLAG_RW, 11, 12, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_tpccm_ma_chk_haddr_reg[] = + { + {"tpccm_ma_chk_haddr", DPP_FIELD_FLAG_RW, 11, 12, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_groupnum_ram_clr_reg[] = + { + {"groupnum_ram_clr", DPP_FIELD_FLAG_WO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_index_ram0_clr_reg[] = + { + {"index_ram0_clr", DPP_FIELD_FLAG_WO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_index_ram1_clr_reg[] = + { + {"index_ram1_clr", DPP_FIELD_FLAG_WO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_rmep_ram_clr_reg[] = + { + {"rmep_ram_clr", DPP_FIELD_FLAG_WO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_ma_ram_clr_reg[] = + { + {"ma_ram_clr", DPP_FIELD_FLAG_WO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_ram_init_done_reg[] = + { + {"ram_init_done", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_rec_bfd_debug_en_reg[] = + { + {"rec_bfd_debug_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_oam_session_int_reg[] = + { + {"tpma_int", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0}, + {"ethma_int", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0}, + {"bfd_int", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0}, + {"ethoam_int", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0}, + {"tpbfd_int", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0}, + {"tpoam_int", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_pon_int_reg[] = + { + {"fifo_int", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0}, + {"pon_protect_int", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_oam_int_clr_reg[] = + { + {"oam_int_clr", DPP_FIELD_FLAG_WO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_type_int_clr0_reg[] = + { + {"tpma_int_clr", DPP_FIELD_FLAG_WO, 5, 1, 0x0, 0x0}, + {"ethma_int_clr", DPP_FIELD_FLAG_WO, 4, 1, 0x0, 0x0}, + {"bfd_int_clr", DPP_FIELD_FLAG_WO, 3, 1, 0x0, 0x0}, + {"ethoam_int_clr", DPP_FIELD_FLAG_WO, 2, 1, 0x0, 0x0}, + {"tpbfd_int_clr", DPP_FIELD_FLAG_WO, 1, 1, 0x0, 0x0}, + {"tpoam_int_clr", DPP_FIELD_FLAG_WO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_type_int_clr1_reg[] = + { + {"fifo_int_clr", DPP_FIELD_FLAG_WO, 1, 1, 0x0, 0x0}, + {"pon_protect_int_clr", DPP_FIELD_FLAG_WO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_interrupt_mask_reg[] = + { + {"fifo_interrupt_mask", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"pon_protect_interruptmask", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"tpma_interrupt_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"ethma_interrupt_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"bfd_interrupt_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"ethoam_interrupt_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"tpbfd_interrupt_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"tpoam_interrupt_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_int0_index_reg[] = + { + {"int0_index0", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_int1_index_reg[] = + { + {"int1_index0", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_int0_index_region_reg[] = + { + {"int0_index_region", DPP_FIELD_FLAG_RO, 3, 4, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_int1_index_region_reg[] = + { + {"int1_index_region", DPP_FIELD_FLAG_RO, 3, 4, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_bdiinfo_fwft_fifo_th_reg[] = + { + {"bdiinfo_fwft_fifo_th", DPP_FIELD_FLAG_RW, 6, 7, 0x30, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_recsec_fwft_fifo_th_reg[] = + { + {"recsec_fwft_fifo_th", DPP_FIELD_FLAG_RW, 7, 8, 0x40, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_timing_chk_info0_fwft_fifo_th_reg[] = + { + {"timing_chk_info0_fwft_fifo_th", DPP_FIELD_FLAG_RW, 6, 7, 0x30, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_recma_fwft_fifo_th_reg[] = + { + {"recma_fwft_fifo_th", DPP_FIELD_FLAG_RW, 7, 8, 0x40, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_timing_chk_info1_fwft_fifo_th_reg[] = + { + {"timing_chk_info1_fwft_fifo_th", DPP_FIELD_FLAG_RW, 6, 7, 0x30, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_oam_txinst_fifo_th_reg[] = + { + {"oam_txinst_fifo_th", DPP_FIELD_FLAG_RW, 10, 11, 0x300, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_oam_rdinfo_fwft_fifo_th_reg[] = + { + {"oam_rdinfo_fwft_fifo_th", DPP_FIELD_FLAG_RW, 9, 10, 0x180, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_lm_cnt_fwft_fifo_th_reg[] = + { + {"lm_cnt_fwft_fifo_th", DPP_FIELD_FLAG_RW, 6, 7, 0x30, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_oam_pkt_fifo_th_reg[] = + { + {"oam_pkt_fifo_th", DPP_FIELD_FLAG_RW, 9, 10, 0x180, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_reclm_stat_fifo_th_reg[] = + { + {"reclm_stat_fifo_th", DPP_FIELD_FLAG_RW, 7, 8, 0x40, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_txlm_stat_fifo_th_reg[] = + { + {"txlm_stat_fifo_th", DPP_FIELD_FLAG_RW, 5, 6, 0x18, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_oam_chk_fwft_fifo_th_reg[] = + { + {"oam_chk_fwft_fifo_th", DPP_FIELD_FLAG_RW, 9, 10, 0x180, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_txoam_stat_fifo_th_reg[] = + { + {"txoam_stat_fifo_th", DPP_FIELD_FLAG_RW, 6, 7, 0x30, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_recoam_stat_fifo_th_reg[] = + { + {"recoam_stat_fifo_th", DPP_FIELD_FLAG_RW, 6, 7, 0x30, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_txpkt_data_fwft_fifo_th_reg[] = + { + {"txpkt_data_fwft_fifo_th", DPP_FIELD_FLAG_RW, 8, 9, 0xc0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_tstpkt_fwft_fifo_th_reg[] = + { + {"tstpkt_fwft_fifo_th", DPP_FIELD_FLAG_RW, 8, 9, 0x80, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_tst_txinst_fwft_fifo_th_reg[] = + { + {"tst_txinst_fwft_fifo_th", DPP_FIELD_FLAG_RW, 4, 5, 0x8, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_tstrx_main_en_reg[] = + { + {"tstrx_main_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_tsttx_cfg_para_tbl2_reg[] = + { + {"ddr_self_test_tx_en", DPP_FIELD_FLAG_RW, 16, 1, 0x0, 0x0}, + {"tm_self_test_tx_en", DPP_FIELD_FLAG_RW, 15, 1, 0x0, 0x0}, + {"fast_aging_tx_en", DPP_FIELD_FLAG_RW, 14, 1, 0x0, 0x0}, + {"timing_aging_tx_en", DPP_FIELD_FLAG_RW, 13, 1, 0x0, 0x0}, + {"backgroud_flow_tx_en", DPP_FIELD_FLAG_RW, 12, 1, 0x0, 0x0}, + {"tsttx_tx_en", DPP_FIELD_FLAG_RW, 11, 1, 0x0, 0x0}, + {"tx_freq", DPP_FIELD_FLAG_RW, 10, 3, 0x1, 0x0}, + {"tx_offset", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_tsttx_cfg_para_tbl1_reg[] = + { + {"tx_count", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_tsttx_cfg_para_tbl0_reg[] = + { + {"fast_tx_mode_en", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, + {"tsttx_tx_head_len", DPP_FIELD_FLAG_RW, 30, 15, 0x0, 0x0}, + {"tsttx_tx_interval", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_tstrx_cfg_para_reg[] = + { + {"tstrx_session_num", DPP_FIELD_FLAG_RW, 16, 16, 0x0, 0x0}, + {"tstrx_session_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_fifo_status_int_en_0_reg[] = + { + {"fifo_status_int_en_31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0}, + {"fifo_status_int_en_30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0}, + {"fifo_status_int_en_29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0}, + {"fifo_status_int_en_28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0}, + {"fifo_status_int_en_27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0}, + {"fifo_status_int_en_26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0}, + {"fifo_status_int_en_25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0}, + {"fifo_status_int_en_24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0}, + {"fifo_status_int_en_23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0}, + {"fifo_status_int_en_22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0}, + {"fifo_status_int_en_21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0}, + {"fifo_status_int_en_20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"fifo_status_int_en_19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0}, + {"fifo_status_int_en_18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + {"fifo_status_int_en_17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0}, + {"fifo_status_int_en_16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"fifo_status_int_en_15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"fifo_status_int_en_14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"fifo_status_int_en_13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"fifo_status_int_en_12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"fifo_status_int_en_11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"fifo_status_int_en_10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"fifo_status_int_en_9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"fifo_status_int_en_8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"fifo_status_int_en_7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"fifo_status_int_en_6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"fifo_status_int_en_5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"fifo_status_int_en_4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"fifo_status_int_en_3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"fifo_status_int_en_2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"fifo_status_int_en_1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"fifo_status_int_en_0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_fifo_status_int_en_1_reg[] = + { + {"fifo_status_int_en_41", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"fifo_status_int_en_40", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"fifo_status_int_en_39", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"fifo_status_int_en_38", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"fifo_status_int_en_37", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"fifo_status_int_en_36", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"fifo_status_int_en_35", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"fifo_status_int_en_34", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"fifo_status_int_en_33", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"fifo_status_int_en_32", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_fifo_status_int_mask_0_reg[] = + { + {"fifo_status_int_mask_31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0}, + {"fifo_status_int_mask_30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0}, + {"fifo_status_int_mask_29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0}, + {"fifo_status_int_mask_28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0}, + {"fifo_status_int_mask_27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0}, + {"fifo_status_int_mask_26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0}, + {"fifo_status_int_mask_25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0}, + {"fifo_status_int_mask_24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0}, + {"fifo_status_int_mask_23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0}, + {"fifo_status_int_mask_22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0}, + {"fifo_status_int_mask_21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0}, + {"fifo_status_int_mask_20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"fifo_status_int_mask_19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0}, + {"fifo_status_int_mask_18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + {"fifo_status_int_mask_17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0}, + {"fifo_status_int_mask_16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"fifo_status_int_mask_15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"fifo_status_int_mask_14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"fifo_status_int_mask_13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"fifo_status_int_mask_12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"fifo_status_int_mask_11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"fifo_status_int_mask_10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"fifo_status_int_mask_9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"fifo_status_int_mask_8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"fifo_status_int_mask_7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"fifo_status_int_mask_6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"fifo_status_int_mask_5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"fifo_status_int_mask_4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"fifo_status_int_mask_3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"fifo_status_int_mask_2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"fifo_status_int_mask_1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"fifo_status_int_mask_0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_fifo_status_int_mask_1_reg[] = + { + {"fifo_status_int_mask_41", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"fifo_status_int_mask_40", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"fifo_status_int_mask_39", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"fifo_status_int_mask_38", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"fifo_status_int_mask_37", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"fifo_status_int_mask_36", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"fifo_status_int_mask_35", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"fifo_status_int_mask_34", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"fifo_status_int_mask_33", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"fifo_status_int_mask_32", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_fifo_status_int_status_reg[] = + { + {"fifo_status_int_status", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_main_frequency_reg[] = + { + {"main_frequency", DPP_FIELD_FLAG_RW, 9, 10, 0x258, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_oam_cfg_type_reg[] = + { + {"oam_cfg_type", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_fst_swch_eth_head0_reg[] = + { + {"fst_swch_eth_head", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_fst_swch_eth_head1_reg[] = + { + {"fst_swch_eth_head1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_fst_swch_eth_head2_reg[] = + { + {"fst_swch_eth_head2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_fst_swch_eth_head3_reg[] = + { + {"fst_swch_eth_head3", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_oam_fs_txinst_fifo_th_reg[] = + { + {"oam_fs_txinst_fifo_th", DPP_FIELD_FLAG_RW, 8, 9, 0x1f4, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_oam_ma_fs_txinst_fifo_th_reg[] = + { + {"oam_ma_fs_txinst_fifo_th", DPP_FIELD_FLAG_RW, 8, 9, 0x1f4, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_pon_int_ram_clr_reg[] = + { + {"pon_int_ram_clr", DPP_FIELD_FLAG_WO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_pon_p_int_index_reg[] = + { + {"pon_p_int_index", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_pon_protect_pkt_fifo_th_reg[] = + { + {"pon_protect_pkt_fifo_th", DPP_FIELD_FLAG_RW, 8, 9, 0x1f4, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_pon_laser_off_en_reg[] = + { + {"pon_laser_off_en", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_pon_prtct_pkt_tx_en_reg[] = + { + {"pon_prtct_pkt_tx_en", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_cfg_pon_master_reg[] = + { + {"cfg_pon_master", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_level_mode_reg[] = + { + {"level_mode", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_interrupt_en_reg[] = + { + {"interrupt_en", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_pon_laser_on_en_reg[] = + { + {"pon_laser_on_en", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_ti_pon_sd_reg[] = + { + {"ti_pon_sd", DPP_FIELD_FLAG_RW, 7, 8, 0x2, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_ti_pon_los_reg[] = + { + {"ti_pon_los", DPP_FIELD_FLAG_RW, 7, 8, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_ind_dat4_reg[] = + { + {"ind_dat4", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_ind_dat5_reg[] = + { + {"ind_dat5", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_ind_dat6_reg[] = + { + {"ind_dat6", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_ind_dat7_reg[] = + { + {"ind_dat7", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_ind_dat8_reg[] = + { + {"ind_dat8", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_ind_dat9_reg[] = + { + {"ind_dat9", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_ind_dat10_reg[] = + { + {"ind_dat10", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_ind_dat11_reg[] = + { + {"ind_dat11", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_ind_dat12_reg[] = + { + {"ind_dat12", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_ind_dat13_reg[] = + { + {"ind_dat13", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_ind_dat14_reg[] = + { + {"ind_dat14", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_ind_dat15_reg[] = + { + {"ind_dat15", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_oam_2544_pkt_fifo_th_reg[] = + { + {"oam_2544_pkt_fifo_th", DPP_FIELD_FLAG_RW, 8, 9, 0xc0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_txinfo_ram_clr_reg[] = + { + {"txinfo_ram_clr", DPP_FIELD_FLAG_WO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_txinfo_ram_init_done_reg[] = + { + {"txinfo_ram_init_done", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_fifo_status_int_status40_reg[] = + { + {"fifo_status_int_status40", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_fifo_status_int_status41_reg[] = + { + {"fifo_status_int_status41", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_oam_2544_fun_en_reg[] = + { + {"oam_2544_fun_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_oam_2544_stat_clr_reg[] = + { + {"oam_2544_stat_clr", DPP_FIELD_FLAG_WO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_txdis_default_reg[] = + { + {"txdis_default", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_txdis_default_en_reg[] = + { + {"txdis_default_en", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_tpbfd_firstchk_th_reg[] = + { + {"tpbfd_firstchk_th", DPP_FIELD_FLAG_RW, 18, 19, 0xc350, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_ethccm_firstchk_th_reg[] = + { + {"ethccm_firstchk_th", DPP_FIELD_FLAG_RW, 18, 19, 0xc350, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_tpccm_firstchk_th_reg[] = + { + {"tpccm_firstchk_th", DPP_FIELD_FLAG_RW, 18, 19, 0xc350, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_stat_txstat_req_cnt_reg[] = + { + {"txstat_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_stat_chkstat_req_cnt_reg[] = + { + {"chkstat_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_stat_stat_oam_fc_cnt_reg[] = + { + {"stat1_oam_fc_cnt", DPP_FIELD_FLAG_RC, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_stat_bfdseq_req_cnt_reg[] = + { + {"bfdseq_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_stat_lmcnt_req_cnt_reg[] = + { + {"lmcnt_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_stat_stat_oam_lm_rsp_cnt_reg[] = + { + {"stat2_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_stat_stat_oam_lm_fc_cnt_reg[] = + { + {"stat2_oam_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_stat_se_req_cnt_reg[] = + { + {"se_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_stat_se_rsp_cnt_reg[] = + { + {"se_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_stat_se_oam_fc_cnt_reg[] = + { + {"se_oam_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_stat_oam_se_fc_cnt_reg[] = + { + {"oam_se_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_stat_oam_pktrx_sop_cnt_reg[] = + { + {"oam_pktrx_sop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_stat_oam_pktrx_eop_cnt_reg[] = + { + {"oam_pktrx_eop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_stat_pktrx_oam_fc_cnt_reg[] = + { + {"pktrx_oam_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_stat_pktrx_oam_tst_fc_cnt_reg[] = + { + {"pktrx_oam_tst_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_stat_odma_oam_sop_cnt_reg[] = + { + {"odma_oam_sop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_stat_odma_oam_eop_cnt_reg[] = + { + {"odma_oam_eop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_stat_oam_odma_fc_cnt_reg[] = + { + {"oam_odma_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_stat_rec_ma_pkt_illegal_cnt_reg[] = + { + {"rec_ma_pkt_illegal_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_stat_rec_rmep_pkt_illegal_cnt_reg[] = + { + {"rec_rmep_pkt_illegal_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_stat_rec_eth_ais_pkt_cnt_reg[] = + { + {"rec_eth_ais_pkt_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_stat_rec_tp_ais_pkt_cnt_reg[] = + { + {"rec_tp_ais_pkt_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_stat_rec_tp_csf_pkt_cnt_reg[] = + { + {"rec_tp_csf_pkt_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_stat_rec_eth_level_defect_cnt_reg[] = + { + {"rec_eth_level_defect_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_stat_rec_eth_megid_defect_cnt_reg[] = + { + {"rec_eth_megid_defect_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_stat_rec_eth_mepid_defect_cnt_reg[] = + { + {"rec_eth_mepid_defect_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_stat_rec_eth_interval_defect_cnt_reg[] = + { + {"rec_eth_interval_defect_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_stat_rec_sess_unenable_cnt_reg[] = + { + {"rec_sess_unenable_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_stat_oam_2544_rd_pkt_cnt_reg[] = + { + {"oam_2544_rd_pkt_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_stat_debug_cnt_clr_reg[] = + { + {"debug_cnt_clr", DPP_FIELD_FLAG_WO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_stat_oam_pktrx_catch_data_reg[] = + { + {"oam_pktrx_catch_data", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_stat_odma_oam_catch_data_reg[] = + { + {"odma_oam_catch_data", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_stat_tst_session_tx_cnt_reg[] = + { + {"tst_session_tx_cnt", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_stat_tst_session_rx_cnt_reg[] = + { + {"tst_session_rx_cnt", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_stat_tstrx_lost_cnt_reg[] = + { + {"tstrx_lost_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_stat_bfdseq_wr_cnt_reg[] = + { + {"bfdseq_wr_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_stat_bfdtime_wr_cnt_reg[] = + { + {"bfdtime_wr_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_stat_lmcnt_wr_cnt_reg[] = + { + {"lmcnt_wr_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_stat_oam_fs_pkt_cnt_reg[] = + { + {"oam_fs_pkt_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_stat_oam_ma_fs_pkt_cnt_reg[] = + { + {"lmcnt_wr_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_stat_rec_tp_level_defect_cnt_reg[] = + { + {"rec_tp_level_defect_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_stat_rec_tp_megid_defect_cnt_reg[] = + { + {"rec_tp_megid_defect_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_stat_rec_tp_mepid_defect_cnt_reg[] = + { + {"rec_tp_mepid_defect_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_stat_rec_tp_interval_defect_cnt_reg[] = + { + {"rec_tp_interval_defect_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_stat_rd_reg_clear_mode_reg[] = + { + {"rd_clear_mode_cfg", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_stat_rd_data_reg_clear_mode_reg[] = + { + {"rd_data_reg_clear_mode_cfg", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_indir_oam_int_status_ram_0_reg[] = + { + {"bfd_diag_value_bit4", DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0}, + {"bfd_diag_value_bit3", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0}, + {"bfd_diag_value_bit2", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0}, + {"bfd_diag_value_bit1", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0}, + {"bfd_diag_value_bit0", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0}, + {"dloc_int", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"drdi_int", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_indir_oam_int_status_ram1_reg[] = + { + {"sticky_error_level_defect", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"sticky_error_megid_defect", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"sticky_error_mepid_defect", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"sticky_error_inter_defect", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"sticky_ais_defect", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"sticky_csf_defect", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"current_error_level_defect", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0}, + {"current_error_megid_defect", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0}, + {"current_error_mepid_defect", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0}, + {"current_error_inter_defect", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0}, + {"current_ais_defect", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0}, + {"current_csf_defect", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_indir_tst_pkt_tx_para_ram_reg[] = + { + {"ddr_self_test_tx_en", DPP_FIELD_FLAG_RW, 80, 1, 0x0, 0x0}, + {"tm_self_test_tx_en", DPP_FIELD_FLAG_RW, 79, 1, 0x0, 0x0}, + {"fast_aging_tx_en", DPP_FIELD_FLAG_RW, 78, 1, 0x0, 0x0}, + {"timing_aging_tx_en", DPP_FIELD_FLAG_RW, 77, 1, 0x0, 0x0}, + {"backgroud_flow_tx_en", DPP_FIELD_FLAG_RW, 76, 1, 0x0, 0x0}, + {"tsttx_session_en", DPP_FIELD_FLAG_RW, 75, 1, 0x0, 0x0}, + {"tx_freq", DPP_FIELD_FLAG_RW, 74, 3, 0x0, 0x0}, + {"tx_offset", DPP_FIELD_FLAG_RW, 71, 8, 0x0, 0x0}, + {"tx_count", DPP_FIELD_FLAG_RW, 63, 32, 0x0, 0x0}, + {"fast_tx_mode_en", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, + {"tsttx_pkthead_len", DPP_FIELD_FLAG_RW, 30, 15, 0x0, 0x0}, + {"tsttx_interval", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_indir_groupnumram_reg[] = + { + {"mep_down_num", DPP_FIELD_FLAG_RW, 8, 9, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_indir_oam_tx_tbl_ram_reg[] = + { + {"oam_tx_en", DPP_FIELD_FLAG_RW, 62, 1, 0x0, 0x0}, + {"oam_tx_type", DPP_FIELD_FLAG_RW, 61, 4, 0x0, 0x0}, + {"oam_fetch_len", DPP_FIELD_FLAG_RW, 57, 14, 0x0, 0x0}, + {"bfd_seq_tx_en", DPP_FIELD_FLAG_RW, 43, 1, 0x0, 0x0}, + {"tx_para", DPP_FIELD_FLAG_RW, 42, 7, 0x0, 0x0}, + {"oam_tx_interval", DPP_FIELD_FLAG_RW, 35, 16, 0x0, 0x0}, + {"hd_ena_flag", DPP_FIELD_FLAG_RO, 19, 1, 0x0, 0x0}, + {"last_tx_time", DPP_FIELD_FLAG_RO, 18, 19, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_indir_oam_chk_tbl_ram_reg[] = + { + {"fast_switch_en", DPP_FIELD_FLAG_RW, 55, 1, 0x0, 0x0}, + {"oam_chk_en", DPP_FIELD_FLAG_RW, 54, 1, 0x0, 0x0}, + {"oam_chk_type", DPP_FIELD_FLAG_RW, 53, 4, 0x0, 0x0}, + {"ccm_predel_flag", DPP_FIELD_FLAG_RW, 49, 1, 0x0, 0x0}, + {"lm_chk_en", DPP_FIELD_FLAG_RW, 48, 1, 0x0, 0x0}, + {"ccm_group_id", DPP_FIELD_FLAG_RW, 47, 12, 0x0, 0x0}, + {"oam_chk_internal", DPP_FIELD_FLAG_RW, 35, 16, 0x0, 0x0}, + {"fist_chk_flag", DPP_FIELD_FLAG_RO, 19, 1, 0x0, 0x0}, + {"last_chk_time", DPP_FIELD_FLAG_RO, 18, 19, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_indir_oam_ma_chk_tbl_ram_reg[] = + { + {"ma_fast_switch_en", DPP_FIELD_FLAG_RW, 141, 1, 0x0, 0x0}, + {"ma_chk_en", DPP_FIELD_FLAG_RW, 140, 1, 0x0, 0x0}, + {"ma_type", DPP_FIELD_FLAG_RW, 139, 1, 0x0, 0x0}, + {"error_level_defect_en", DPP_FIELD_FLAG_RW, 138, 1, 0x0, 0x0}, + {"error_megid_defect_en", DPP_FIELD_FLAG_RW, 137, 1, 0x0, 0x0}, + {"error_mepid_defect_en", DPP_FIELD_FLAG_RW, 136, 1, 0x0, 0x0}, + {"error_inter_defect_en", DPP_FIELD_FLAG_RW, 135, 1, 0x0, 0x0}, + {"ais_defect_en", DPP_FIELD_FLAG_RW, 134, 1, 0x0, 0x0}, + {"csf_defect_en", DPP_FIELD_FLAG_RW, 133, 1, 0x0, 0x0}, + {"error_level_defect_ccm", DPP_FIELD_FLAG_RW, 132, 3, 0x0, 0x0}, + {"error_megid_defect_ccm", DPP_FIELD_FLAG_RW, 129, 3, 0x0, 0x0}, + {"error_mepid_defect_ccm", DPP_FIELD_FLAG_RW, 126, 3, 0x0, 0x0}, + {"error_inter_defect_ccm", DPP_FIELD_FLAG_RW, 123, 3, 0x0, 0x0}, + {"ais_defect_ccm", DPP_FIELD_FLAG_RW, 120, 3, 0x0, 0x0}, + {"csf_defect_ccm", DPP_FIELD_FLAG_RW, 117, 3, 0x0, 0x0}, + {"ma_predel_en", DPP_FIELD_FLAG_RW, 114, 1, 0x0, 0x0}, + {"error_level_defect_ts", DPP_FIELD_FLAG_RO, 113, 19, 0x0, 0x0}, + {"error_megid_defect_ts", DPP_FIELD_FLAG_RO, 94, 19, 0x0, 0x0}, + {"error_mepid_defect_ts", DPP_FIELD_FLAG_RO, 75, 19, 0x0, 0x0}, + {"error_inter_defect_ts", DPP_FIELD_FLAG_RO, 56, 19, 0x0, 0x0}, + {"ais_defect_ts", DPP_FIELD_FLAG_RO, 37, 19, 0x0, 0x0}, + {"csf_defect_ts", DPP_FIELD_FLAG_RO, 18, 19, 0x0, 0x0}, + }; +DPP_FIELD_T g_nppu_oam_cfg_indir_oam_2544_tx_ram_reg[] = + { + {"tx_en_2544", DPP_FIELD_FLAG_RW, 46, 1, 0x0, 0x0}, + {"tx_cfg_times_2544", DPP_FIELD_FLAG_RW, 45, 16, 0x0, 0x0}, + {"current_times", DPP_FIELD_FLAG_RW, 29, 16, 0x0, 0x0}, + {"slice_num", DPP_FIELD_FLAG_RW, 13, 7, 0x0, 0x0}, + {"pkt_mty", DPP_FIELD_FLAG_RW, 6, 7, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_interrupt_en_r_reg[] = + { + {"interrupt_en_r", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_mec_host_interrupt_reg[] = + { + {"mec_host_interrupt", DPP_FIELD_FLAG_RO, 5, 6, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_dbg_rtl_date_reg[] = + { + {"dbg_rtl_date", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_dup_start_num_cfg_reg[] = + { + {"dup_start_num_cfg", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_debug_data_write_complete_reg[] = + { + {"debug_data_write_complete", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_uc_mc_wrr_cfg_reg[] = + { + {"uc_mc_wrr_cfg", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_debug_pkt_send_en_reg[] = + { + {"debug_pkt_send_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_dup_tbl_ind_access_done_reg[] = + { + {"dup_tbl_ind_access_done", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_isu_ppu_demux_fifo_interrupt_mask_reg[] = + { + {"isu_in_para_fwft_fifo_32x81_wrapper_u0_overflow_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"isu_in_para_fwft_fifo_32x81_wrapper_u0_underflow_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"isu_in_fifo_64x81_wrapper_u0_overflow_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"isu_in_fifo_64x81_wrapper_u0_underflow_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_multicast_fifo_interrupt_mask_reg[] = + { + {"ppu_pktrx_mc_ptr_fifo_16384x17_wrapper_u0_underflow_mask", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0}, + {"ppu_pktrx_mc_ptr_fifo_16384x17_wrapper_u0_overflow_mask", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + {"pf_req_fwft_fifo_16x36_wrapper_u0_overflow_mask", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0}, + {"pf_req_fwft_fifo_16x36_wrapper_u0_underflow_mask", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"pf_rsp_fwft_fifo_32x34_wrapper_u0_overflow_mask", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"pf_rsp_fwft_fifo_32x34_wrapper_u0_underflow_mask", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"dup_para_fwft_fifo_16x35_wrapper_u0_overflow_mask", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"dup_para_fwft_fifo_16x35_wrapper_u0_underflow_mask", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"se_mc_rsp_fwft_fifo_32x17_wrapper_u0_overflow_mask", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"se_mc_rsp_fwft_fifo_32x17_wrapper_u0_underflow_mask", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"sa_para_fwft_fifo_64x17_wrapper_u0_overflow_mask", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"sa_para_fwft_fifo_64x17_wrapper_u0_underflow_mask", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"group_id_fifo_64x16_wrapper_u0_overflow_mask", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"group_id_fifo_64x16_wrapper_u0_underflow_mask", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"isu_mc_para_fwft_fifo_128x34_wrapper_u0_overflow_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"isu_mc_para_fwft_fifo_128x34_wrapper_u0_underflow_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"dup_freeptr_fwft_fifo_128x7_wrapper_u0_overflow_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"dup_freeptr_fwft_fifo_128x7_wrapper_u0_underflow_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"car_flag_fifo_32x1_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"car_flag_fifo_32x1_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_in_schedule_fifo_interrupt_mask_reg[] = + { + {"free_global_num_fwft_fifo_8192x13_wrapper_u0_overflow_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"free_global_num_fwft_fifo_8192x13_wrapper_u0_underflow_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"mc_mf_fifo_16x2048_wrapper_u0_overflow_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"mc_mf_fifo_16x2048_wrapper_u0_underflow_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"uc_mf_fifo_96x2048_wrapper_u0_overflow_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"uc_mf_fifo_96x2048_wrapper_u0_underflow_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_mf_out_fifo_interrupt_mask_reg[] = + { + {"ppu_cluster5_mf_out_afifo_32x2048_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"ppu_cluster5_mf_out_afifo_32x2048_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"ppu_cluster4_mf_out_afifo_32x2048_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"ppu_cluster4_mf_out_afifo_32x2048_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"ppu_cluster3_mf_out_afifo_32x2048_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"ppu_cluster3_mf_out_afifo_32x2048_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"ppu_cluster2_mf_out_afifo_32x2048_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"ppu_cluster2_mf_out_afifo_32x2048_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"ppu_cluster1_mf_out_afifo_32x2048_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"ppu_cluster1_mf_out_afifo_32x2048_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"ppu_cluster0_mf_out_afifo_32x2048_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"ppu_cluster0_mf_out_afifo_32x2048_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pbu_mcode_pf_req_schedule_fifo_interrupt_mask_reg[] = + { + {"ppu_cluster5_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"ppu_cluster4_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"ppu_cluster3_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"ppu_cluster2_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"ppu_cluster1_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"ppu_cluster0_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"ppu_cluster5_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"ppu_cluster4_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"ppu_cluster3_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"ppu_cluster2_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"ppu_cluster1_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"ppu_cluster0_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pbu_mcode_pf_rsp_schedule_fifo_interrupt_mask_reg[] = + { + {"ppu_pbu_mcode_pf_rsp_afifo_64x16_wrapper_u0r_underflow_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"ppu_pbu_mcode_pf_rsp_afifo_64x16_wrapper_u0_overflow_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_mccnt_fifo_interrupt_mask_reg[] = + { + {"ppu_mccnt_fifo_32x15_wrapper_u0_overflow_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"ppu_mccnt_fifo_32x15_wrapper_u0_underflow_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"ppu_wb_data_fifo_32x2048_wrapper_u0_overflow_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"ppu_wb_data_fifo_32x2048_wrapper_u0_underflow_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"mccnt_rsp_fifo_32x1_wrapper_u0_overflow_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"mccnt_rsp_fifo_32x1_wrapper_u0_underflow_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_coprocessor_fifo_interrupt_mask_l_reg[] = + { + {"mec3_cop_key_crc_fifo_32x625_wrapper_overflow_flg_mask", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0}, + {"mec3_cop_key_crc_fifo_32x625_wrapper_underflow_flg_mask", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0}, + {"mec3_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_mask", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0}, + {"mec3_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_mask", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0}, + {"mec3_cop_key_mul_fifo_32x52_wrapper_overflow_flg_mask", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0}, + {"mec3_cop_key_mul_fifo_32x52_wrapper_underflow_flg_mask", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0}, + {"mec3_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_mask", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0}, + {"mec3_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_mask", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0}, + {"mec2_cop_key_crc_fifo_32x625_wrapper_overflow_flg_mask", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0}, + {"mec2_cop_key_crc_fifo_32x625_wrapper_underflow_flg_mask", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0}, + {"mec2_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_mask", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0}, + {"mec2_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_mask", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"mec2_cop_key_mul_fifo_32x52_wrapper_overflow_flg_mask", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0}, + {"mec2_cop_key_mul_fifo_32x52_wrapper_underflow_flg_mask", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + {"mec2_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_mask", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0}, + {"mec2_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_mask", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"mec1_cop_key_crc_fifo_32x625_wrapper_overflow_flg_mask", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"mec1_cop_key_crc_fifo_32x625_wrapper_underflow_flg_mask", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"mec1_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_mask", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"mec1_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_mask", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"mec1_cop_key_mul_fifo_32x52_wrapper_overflow_flg_mask", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"mec1_cop_key_mul_fifo_32x52_wrapper_underflow_flg_mask", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"mec1_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_mask", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"mec1_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_mask", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"mec0_cop_key_crc_fifo_32x625_wrapper_overflow_flg_mask", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"mec0_cop_key_crc_fifo_32x625_wrapper_underflow_flg_mask", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"mec0_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"mec0_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"mec0_cop_key_mul_fifo_32x52_wrapper_overflow_flg_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"mec0_cop_key_mul_fifo_32x52_wrapper_underflow_flg_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"mec0_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"mec0_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_coprocessor_fifo_interrupt_mask_m_reg[] = + { + {"ppu_cop_result_fwft_fifo_80x80_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0}, + {"ppu_cop_result_fwft_fifo_80x80_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0}, + {"ppu_cop_delay_fifo_48x16_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0}, + {"ppu_cop_delay_fifo_48x16_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0}, + {"ppu_cop_delay_fifo_16x48_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0}, + {"ppu_cop_delay_fifo_16x48_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0}, + {"ppu_cop_delay_fifo_16x32_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0}, + {"ppu_cop_delay_fifo_16x32_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0}, + {"ppu_cop_result_fwft_fifo_96x80_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0}, + {"ppu_cop_result_fwft_fifo_96x80_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0}, + {"ppu_cop_delay_fifo_16x16_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0}, + {"ppu_cop_delay_fifo_16x16_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"ppu_cop_result_fwft_fifo_32x80_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0}, + {"ppu_cop_result_fwft_fifo_32x80_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + {"ppu_cop_result_fwft_fifo_16x80_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0}, + {"ppu_cop_result_fwft_fifo_16x80_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"mec5_cop_key_crc_fifo_32x625_wrapper_overflow_flg_mask", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"mec5_cop_key_crc_fifo_32x625_wrapper_underflow_flg_mask", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"mec5_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_mask", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"mec5_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_mask", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"mec5_cop_key_mul_fifo_32x52_wrapper_overflow_flg_mask", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"mec5_cop_key_mul_fifo_32x52_wrapper_underflow_flg_mask", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"mec5_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_mask", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"mec5_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_mask", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"mec4_cop_key_crc_fifo_32x625_wrapper_overflow_flg_mask", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"mec4_cop_key_crc_fifo_32x625_wrapper_underflow_flg_mask", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"mec4_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"mec4_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"mec4_cop_key_mul_fifo_32x52_wrapper_overflow_flg_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"mec4_cop_key_mul_fifo_32x52_wrapper_underflow_flg_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"mec4_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"mec4_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_coprocessor_fifo_interrupt_mask_h_reg[] = + { + {"coprocessor_fwft_fifo_16x80_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"coprocessor_fwft_fifo_16x80_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"ppu_cop_random_mod_para_delay_fifo_48x16_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"ppu_cop_random_mod_para_delay_fifo_48x16_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_ram_check_err_mask_reg[] = + { + {"parity_err_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_instrmem_fifo_interrupt_mask_reg[] = + { + {"instrmem2_wr_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"instrmem2_wr_fifo_udf_mask", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"instrmem2_rd_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"instrmem2_rd_fifo_udf_mask", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"instrmem1_wr_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"instrmem1_wr_fifo_udf_mask", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"instrmem1_rd_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"instrmem1_rd_fifo_udf_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"instrmem0_wr_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"instrmem0_wr_fifo_udf_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"instrmem0_rd_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"instrmem0_rd_fifo_udf_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_isu_ppu_demux_fifo_interrupt_sta_reg[] = + { + {"isu_in_para_fwft_fifo_32x81_wrapper_u0_overflow_sta", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0}, + {"isu_in_para_fwft_fifo_32x81_wrapper_u0_underflow_sta", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0}, + {"isu_in_fifo_64x81_wrapper_u0_overflow_sta", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0}, + {"isu_in_fifo_64x81_wrapper_u0_underflow_sta", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_multicast_fifo_interrupt_sta_reg[] = + { + {"ppu_pktrx_mc_ptr_fifo_16384x17_wrapper_u0_overflow_sta", DPP_FIELD_FLAG_RO, 19, 1, 0x0, 0x0}, + {"ppu_pktrx_mc_ptr_fifo_16384x17_wrapper_u0_underflow_sta", DPP_FIELD_FLAG_RO, 18, 1, 0x0, 0x0}, + {"pf_req_fwft_fifo_16x36_wrapper_u0_overflow_sta", DPP_FIELD_FLAG_RO, 17, 1, 0x0, 0x0}, + {"pf_req_fwft_fifo_16x36_wrapper_u0_underflow_sta", DPP_FIELD_FLAG_RO, 16, 1, 0x0, 0x0}, + {"pf_rsp_fwft_fifo_32x34_wrapper_u0_overflow_sta", DPP_FIELD_FLAG_RO, 15, 1, 0x0, 0x0}, + {"pf_rsp_fwft_fifo_32x34_wrapper_u0_underflow_sta", DPP_FIELD_FLAG_RO, 14, 1, 0x0, 0x0}, + {"dup_para_fwft_fifo_16x35_wrapper_u0_overflow_sta", DPP_FIELD_FLAG_RO, 13, 1, 0x0, 0x0}, + {"dup_para_fwft_fifo_16x35_wrapper_u0_underflow_sta", DPP_FIELD_FLAG_RO, 12, 1, 0x0, 0x0}, + {"se_mc_rsp_fwft_fifo_32x17_wrapper_u0_overflow_sta", DPP_FIELD_FLAG_RO, 11, 1, 0x0, 0x0}, + {"se_mc_rsp_fwft_fifo_32x17_wrapper_u0_underflow_sta", DPP_FIELD_FLAG_RO, 10, 1, 0x0, 0x0}, + {"sa_para_fwft_fifo_64x17_wrapper_u0_overflow_sta", DPP_FIELD_FLAG_RO, 9, 1, 0x0, 0x0}, + {"sa_para_fwft_fifo_64x17_wrapper_u0_underflow_sta", DPP_FIELD_FLAG_RO, 8, 1, 0x0, 0x0}, + {"group_id_fifo_64x16_wrapper_u0_overflow_sta", DPP_FIELD_FLAG_RO, 7, 1, 0x0, 0x0}, + {"group_id_fifo_64x16_wrapper_u0_underflow_sta", DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0}, + {"isu_mc_para_fwft_fifo_128x34_wrapper_u0_overflow_sta", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0}, + {"isu_mc_para_fwft_fifo_128x34_wrapper_u0_underflow_sta", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0}, + {"dup_freeptr_fwft_fifo_128x7_wrapper_u0_overflow_sta", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0}, + {"dup_freeptr_fwft_fifo_128x7_wrapper_u0_underflow_sta", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0}, + {"car_flag_fifo_32x1_wrapper_overflow_sta", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0}, + {"car_flag_fifo_32x1_wrapper_underflow_sta", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_in_schedule_fifo_interrupt_sta_reg[] = + { + {"free_global_num_fwft_fifo_8192x13_wrapper_u0_overflow_sta", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0}, + {"free_global_num_fwft_fifo_8192x13_wrapper_u0_underflow_sta", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0}, + {"mc_mf_fifo_16x2048_wrapper_u0_overflow_sta", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0}, + {"mc_mf_fifo_16x2048_wrapper_u0_underflow_sta", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0}, + {"uc_mf_fifo_96x2048_wrapper_u0_overflow_sta", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0}, + {"uc_mf_fifo_96x2048_wrapper_u0_underflow_sta", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_mf_out_fifo_interrupt_sta_reg[] = + { + {"ppu_cluster5_mf_out_afifo_32x2048_wrapper_overflow_sta", DPP_FIELD_FLAG_RO, 11, 1, 0x0, 0x0}, + {"ppu_cluster5_mf_out_afifo_32x2048_wrapper_underflow_sta", DPP_FIELD_FLAG_RO, 10, 1, 0x0, 0x0}, + {"ppu_cluster4_mf_out_afifo_32x2048_wrapper_overflow_sta", DPP_FIELD_FLAG_RO, 9, 1, 0x0, 0x0}, + {"ppu_cluster4_mf_out_afifo_32x2048_wrapper_underflow_sta", DPP_FIELD_FLAG_RO, 8, 1, 0x0, 0x0}, + {"ppu_cluster3_mf_out_afifo_32x2048_wrapper_overflow_sta", DPP_FIELD_FLAG_RO, 7, 1, 0x0, 0x0}, + {"ppu_cluster3_mf_out_afifo_32x2048_wrapper_underflow_sta", DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0}, + {"ppu_cluster2_mf_out_afifo_32x2048_wrapper_overflow_sta", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0}, + {"ppu_cluster2_mf_out_afifo_32x2048_wrapper_underflow_sta", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0}, + {"ppu_cluster1_mf_out_afifo_32x2048_wrapper_overflow_sta", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0}, + {"ppu_cluster1_mf_out_afifo_32x2048_wrapper_underflow_sta", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0}, + {"ppu_cluster0_mf_out_afifo_32x2048_wrapper_overflow_sta", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0}, + {"ppu_cluster0_mf_out_afifo_32x2048_wrapper_underflow_sta", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pbu_mcode_pf_req_schedule_fifo_interrupt_sta_reg[] = + { + {"ppu_cluster5_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_sta", DPP_FIELD_FLAG_RO, 11, 1, 0x0, 0x0}, + {"ppu_cluster4_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_sta", DPP_FIELD_FLAG_RO, 10, 1, 0x0, 0x0}, + {"ppu_cluster3_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_sta", DPP_FIELD_FLAG_RO, 9, 1, 0x0, 0x0}, + {"ppu_cluster2_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_sta", DPP_FIELD_FLAG_RO, 8, 1, 0x0, 0x0}, + {"ppu_cluster1_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_sta", DPP_FIELD_FLAG_RO, 7, 1, 0x0, 0x0}, + {"ppu_cluster0_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_sta", DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0}, + {"ppu_cluster5_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_sta", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0}, + {"ppu_cluster4_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_sta", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0}, + {"ppu_cluster3_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_sta", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0}, + {"ppu_cluster2_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_sta", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0}, + {"ppu_cluster1_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_sta", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0}, + {"ppu_cluster0_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_sta", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pbu_mcode_pf_rsp_schedule_fifo_interrupt_sta_reg[] = + { + {"ppu_pbu_mcode_pf_rsp_afifo_64x16_wrapper_u0r_underflow_sta", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0}, + {"ppu_pbu_mcode_pf_rsp_afifo_64x16_wrapper_u0_overflow_sta", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_mccnt_fifo_interrupt_sta_reg[] = + { + {"ppu_mccnt_fifo_32x15_wrapper_u0_overflow_sta", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0}, + {"ppu_mccnt_fifo_32x15_wrapper_u0_underflow_sta", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0}, + {"ppu_wb_data_fifo_32x2048_wrapper_u0_overflow_sta", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0}, + {"ppu_wb_data_fifo_32x2048_wrapper_u0_underflow_sta", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0}, + {"mccnt_rsp_fifo_32x1_wrapper_u0_overflow_sta", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0}, + {"mccnt_rsp_fifo_32x1_wrapper_u0_underflow_sta", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_coprocessor_fifo_interrupt_sta_l_reg[] = + { + {"mec3_cop_key_crc_fifo_32x625_wrapper_overflow_flg_sta", DPP_FIELD_FLAG_RO, 31, 1, 0x0, 0x0}, + {"mec3_cop_key_crc_fifo_32x625_wrapper_underflow_flg_sta", DPP_FIELD_FLAG_RO, 30, 1, 0x0, 0x0}, + {"mec3_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_sta", DPP_FIELD_FLAG_RO, 29, 1, 0x0, 0x0}, + {"mec3_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_sta", DPP_FIELD_FLAG_RO, 28, 1, 0x0, 0x0}, + {"mec3_cop_key_mul_fifo_32x52_wrapper_overflow_flg_sta", DPP_FIELD_FLAG_RO, 27, 1, 0x0, 0x0}, + {"mec3_cop_key_mul_fifo_32x52_wrapper_underflow_flg_sta", DPP_FIELD_FLAG_RO, 26, 1, 0x0, 0x0}, + {"mec3_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_sta", DPP_FIELD_FLAG_RO, 25, 1, 0x0, 0x0}, + {"mec3_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_sta", DPP_FIELD_FLAG_RO, 24, 1, 0x0, 0x0}, + {"mec2_cop_key_crc_fifo_32x625_wrapper_overflow_flg_sta", DPP_FIELD_FLAG_RO, 23, 1, 0x0, 0x0}, + {"mec2_cop_key_crc_fifo_32x625_wrapper_underflow_flg_sta", DPP_FIELD_FLAG_RO, 22, 1, 0x0, 0x0}, + {"mec2_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_sta", DPP_FIELD_FLAG_RO, 21, 1, 0x0, 0x0}, + {"mec2_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_sta", DPP_FIELD_FLAG_RO, 20, 1, 0x0, 0x0}, + {"mec2_cop_key_mul_fifo_32x52_wrapper_overflow_flg_sta", DPP_FIELD_FLAG_RO, 19, 1, 0x0, 0x0}, + {"mec2_cop_key_mul_fifo_32x52_wrapper_underflow_flg_sta", DPP_FIELD_FLAG_RO, 18, 1, 0x0, 0x0}, + {"mec2_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_sta", DPP_FIELD_FLAG_RO, 17, 1, 0x0, 0x0}, + {"mec2_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_sta", DPP_FIELD_FLAG_RO, 16, 1, 0x0, 0x0}, + {"mec1_cop_key_crc_fifo_32x625_wrapper_overflow_flg_sta", DPP_FIELD_FLAG_RO, 15, 1, 0x0, 0x0}, + {"mec1_cop_key_crc_fifo_32x625_wrapper_underflow_flg_sta", DPP_FIELD_FLAG_RO, 14, 1, 0x0, 0x0}, + {"mec1_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_sta", DPP_FIELD_FLAG_RO, 13, 1, 0x0, 0x0}, + {"mec1_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_sta", DPP_FIELD_FLAG_RO, 12, 1, 0x0, 0x0}, + {"mec1_cop_key_mul_fifo_32x52_wrapper_overflow_flg_sta", DPP_FIELD_FLAG_RO, 11, 1, 0x0, 0x0}, + {"mec1_cop_key_mul_fifo_32x52_wrapper_underflow_flg_sta", DPP_FIELD_FLAG_RO, 10, 1, 0x0, 0x0}, + {"mec1_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_sta", DPP_FIELD_FLAG_RO, 9, 1, 0x0, 0x0}, + {"mec1_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_sta", DPP_FIELD_FLAG_RO, 8, 1, 0x0, 0x0}, + {"mec0_cop_key_crc_fifo_32x625_wrapper_overflow_flg_sta", DPP_FIELD_FLAG_RO, 7, 1, 0x0, 0x0}, + {"mec0_cop_key_crc_fifo_32x625_wrapper_underflow_flg_sta", DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0}, + {"mec0_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_sta", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0}, + {"mec0_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_sta", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0}, + {"mec0_cop_key_mul_fifo_32x52_wrapper_overflow_flg_sta", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0}, + {"mec0_cop_key_mul_fifo_32x52_wrapper_underflow_flg_sta", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0}, + {"mec0_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_sta", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0}, + {"mec0_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_sta", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_coprocessor_fifo_interrupt_sta_m_reg[] = + { + {"ppu_cop_result_fwft_fifo_80x80_wrapper_overflow_sta", DPP_FIELD_FLAG_RO, 31, 1, 0x0, 0x0}, + {"ppu_cop_result_fwft_fifo_80x80_wrapper_underflow_sta", DPP_FIELD_FLAG_RO, 30, 1, 0x0, 0x0}, + {"ppu_cop_delay_fifo_48x16_wrapper_overflow_sta", DPP_FIELD_FLAG_RO, 29, 1, 0x0, 0x0}, + {"ppu_cop_delay_fifo_48x16_wrapper_underflow_sta", DPP_FIELD_FLAG_RO, 28, 1, 0x0, 0x0}, + {"ppu_cop_delay_fifo_16x48_wrapper_overflow_sta", DPP_FIELD_FLAG_RO, 27, 1, 0x0, 0x0}, + {"ppu_cop_delay_fifo_16x48_wrapper_underflow_sta", DPP_FIELD_FLAG_RO, 26, 1, 0x0, 0x0}, + {"ppu_cop_delay_fifo_16x32_wrapper_overflow_sta", DPP_FIELD_FLAG_RO, 25, 1, 0x0, 0x0}, + {"ppu_cop_delay_fifo_16x32_wrapper_underflow_sta", DPP_FIELD_FLAG_RO, 24, 1, 0x0, 0x0}, + {"ppu_cop_result_fwft_fifo_96x80_wrapper_overflow_sta", DPP_FIELD_FLAG_RO, 23, 1, 0x0, 0x0}, + {"ppu_cop_result_fwft_fifo_96x80_wrapper_underflow_sta", DPP_FIELD_FLAG_RO, 22, 1, 0x0, 0x0}, + {"ppu_cop_delay_fifo_16x16_wrapper_overflow_sta", DPP_FIELD_FLAG_RO, 21, 1, 0x0, 0x0}, + {"ppu_cop_delay_fifo_16x16_wrapper_underflow_sta", DPP_FIELD_FLAG_RO, 20, 1, 0x0, 0x0}, + {"ppu_cop_result_fwft_fifo_32x80_wrapper_overflow_sta", DPP_FIELD_FLAG_RO, 19, 1, 0x0, 0x0}, + {"ppu_cop_result_fwft_fifo_32x80_wrapper_underflow_sta", DPP_FIELD_FLAG_RO, 18, 1, 0x0, 0x0}, + {"ppu_cop_result_fwft_fifo_16x80_wrapper_overflow_sta", DPP_FIELD_FLAG_RO, 17, 1, 0x0, 0x0}, + {"ppu_cop_result_fwft_fifo_16x80_wrapper_underflow_sta", DPP_FIELD_FLAG_RO, 16, 1, 0x0, 0x0}, + {"mec5_cop_key_crc_fifo_32x625_wrapper_overflow_flg_sta", DPP_FIELD_FLAG_RO, 15, 1, 0x0, 0x0}, + {"mec5_cop_key_crc_fifo_32x625_wrapper_underflow_flg_sta", DPP_FIELD_FLAG_RO, 14, 1, 0x0, 0x0}, + {"mec5_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_sta", DPP_FIELD_FLAG_RO, 13, 1, 0x0, 0x0}, + {"mec5_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_sta", DPP_FIELD_FLAG_RO, 12, 1, 0x0, 0x0}, + {"mec5_cop_key_mul_fifo_32x52_wrapper_overflow_flg_sta", DPP_FIELD_FLAG_RO, 11, 1, 0x0, 0x0}, + {"mec5_cop_key_mul_fifo_32x52_wrapper_underflow_flg_sta", DPP_FIELD_FLAG_RO, 10, 1, 0x0, 0x0}, + {"mec5_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_sta", DPP_FIELD_FLAG_RO, 9, 1, 0x0, 0x0}, + {"mec5_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_sta", DPP_FIELD_FLAG_RO, 8, 1, 0x0, 0x0}, + {"mec4_cop_key_crc_fifo_32x625_wrapper_overflow_flg_sta", DPP_FIELD_FLAG_RO, 7, 1, 0x0, 0x0}, + {"mec4_cop_key_crc_fifo_32x625_wrapper_underflow_flg_sta", DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0}, + {"mec4_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_sta", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0}, + {"mec4_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_sta", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0}, + {"mec4_cop_key_mul_fifo_32x52_wrapper_overflow_flg_sta", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0}, + {"mec4_cop_key_mul_fifo_32x52_wrapper_underflow_flg_sta", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0}, + {"mec4_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_sta", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0}, + {"mec4_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_sta", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_coprocessor_fifo_interrupt_sta_h_reg[] = + { + {"ppu_cop_random_mod_para_delay_fifo_48x16_wrapper_overflow_sta", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0}, + {"ppu_cop_random_mod_para_delay_fifo_48x16_wrapper_underflow_sta", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_instrmem_fifo_interrupt_sta_reg[] = + { + {"instrmem1_wr_fifo_ovf_sta", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"instrmem1_wr_fifo_udf_sta", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"instrmem1_rd_fifo_ovf_sta", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"instrmem1_rd_fifo_udf_sta", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"instrmem0_wr_fifo_ovf_sta", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"instrmem0_wr_fifo_udf_sta", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"instrmem0_rd_fifo_ovf_sta", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"instrmem0_rd_fifo_udf_sta", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_ram_check_ecc_err_flag_1_reg[] = + { + {"ecc_single_err_sa_para_fifo_int_flag", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"ecc_double_err_sa_para_fifo_int_flag", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"ecc_single_err_dup_para_fifo_int_flag", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"ecc_double_err_dup_para_fifo_int_flag", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"ecc_single_err_pf_rsp_fifo_int_flag", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"ecc_double_err_pf_rsp_fifo_int_flag", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"ecc_single_err_pf_req_fifo_int_flag", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"ecc_double_err_pf_req_fifo_int_flag", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"ecc_single_err_ppu_reorder_link_ram0_int_flag", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"ecc_double_err_ppu_reorder_link_ram0_int_flag", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"ecc_single_err_ppu_reorder_link_ram1_int_flag", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"ecc_double_err_ppu_reorder_link_ram1_int_flag", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"ecc_single_err_ppu_reorder_link_flag_array_ram0_int_flag", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"ecc_single_err_ppu_reorder_link_flag_array_ram1_int_flag", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"ecc_single_err_ppu_reorder_ifb_ram_int_flag", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"ecc_double_err_ppu_reorder_ifb_ram_int_flag", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"ecc_single_err_ppu_reorder_flag_array_ram0_int_flag", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"ecc_single_err_ppu_reorder_flag_array_ram1_int_flag", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"ecc_single_err_ppu_reorder_flag_ram0_int_flag", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"ecc_single_err_ppu_reorder_flag_ram1_int_flag", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"ecc_single_err_uc_mf_fifo_int_flag", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"ecc_double_err_uc_mf_fifo_int_flag", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"ecc_single_err_mc_mf_fifo_int_flag", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"ecc_double_err_mc_mf_fifo_int_flag", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"ecc_single_err_free_global_num_fifo_int_flag", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"ecc_double_err_free_global_num_fifo_int_flag", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_isu_ppu_demux_fifo_interrupt_flag_reg[] = + { + {"isu_in_para_fwft_fifo_32x81_wrapper_u0_overflow_flag", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"isu_in_para_fwft_fifo_32x81_wrapper_u0_underflow_flag", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"isu_in_fifo_64x81_wrapper_u0_overflow_flag", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"isu_in_fifo_64x81_wrapper_u0_underflow_flag", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_multicast_fifo_interrupt_flag_reg[] = + { + {"ppu_pktrx_mc_ptr_fifo_16384x17_wrapper_u0_overflow_flag", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"ppu_pktrx_mc_ptr_fifo_16384x17_wrapper_u0_underflow_flag", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"pf_req_fwft_fifo_16x36_wrapper_u0_overflow_flag", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"pf_req_fwft_fifo_16x36_wrapper_u0_underflow_flag", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"pf_rsp_fwft_fifo_32x34_wrapper_u0_overflow_flag", DPP_FIELD_FLAG_RO, 15, 1, 0x0, 0x0}, + {"pf_rsp_fwft_fifo_32x34_wrapper_u0_underflow_flag", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"dup_para_fwft_fifo_16x35_wrapper_u0_overflow_flag", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"dup_para_fwft_fifo_16x35_wrapper_u0_underflow_flag", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"se_mc_rsp_fwft_fifo_32x17_wrapper_u0_overflow_flag", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"se_mc_rsp_fwft_fifo_32x17_wrapper_u0_underflow_flag", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"sa_para_fwft_fifo_64x17_wrapper_u0_overflow_flag", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"sa_para_fwft_fifo_64x17_wrapper_u0_underflow_flag", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"group_id_fifo_64x16_wrapper_u0_overflow_flag", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"group_id_fifo_64x16_wrapper_u0_underflow_flag", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"isu_mc_para_fwft_fifo_128x34_wrapper_u0_overflow_flag", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"isu_mc_para_fwft_fifo_128x34_wrapper_u0_underflow_flag", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"dup_freeptr_fwft_fifo_128x7_wrapper_u0_overflow_flag", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"dup_freeptr_fwft_fifo_128x7_wrapper_u0_underflow_flag", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"car_flag_fifo_32x1_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"car_flag_fifo_32x1_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_in_schedule_fifo_interrupt_flag_reg[] = + { + {"free_global_num_fwft_fifo_8192x13_wrapper_u0_overflow_flag", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"free_global_num_fwft_fifo_8192x13_wrapper_u0_underflow_flag", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"mc_mf_fifo_16x2048_wrapper_u0_overflow_flag", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"mc_mf_fifo_16x2048_wrapper_u0_underflow_flag", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"uc_mf_fifo_96x2048_wrapper_u0_overflow_flag", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"uc_mf_fifo_96x2048_wrapper_u0_underflow_flag", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_mf_out_fifo_interrupt_flag_reg[] = + { + {"ppu_cluster5_mf_out_afifo_32x2048_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"ppu_cluster5_mf_out_afifo_32x2048_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"ppu_cluster4_mf_out_afifo_32x2048_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"ppu_cluster4_mf_out_afifo_32x2048_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"ppu_cluster3_mf_out_afifo_32x2048_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"ppu_cluster3_mf_out_afifo_32x2048_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"ppu_cluster2_mf_out_afifo_32x2048_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"ppu_cluster2_mf_out_afifo_32x2048_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"ppu_cluster1_mf_out_afifo_32x2048_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"ppu_cluster1_mf_out_afifo_32x2048_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"ppu_cluster0_mf_out_afifo_32x2048_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"ppu_cluster0_mf_out_afifo_32x2048_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pbu_mcode_pf_req_schedule_fifo_interrupt_flag_reg[] = + { + {"ppu_cluster5_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"ppu_cluster4_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"ppu_cluster3_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"ppu_cluster2_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"ppu_cluster1_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"ppu_cluster0_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"ppu_cluster5_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"ppu_cluster4_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"ppu_cluster3_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"ppu_cluster2_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"ppu_cluster1_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"ppu_cluster0_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pbu_mcode_pf_rsp_schedule_fifo_interrupt_flag_reg[] = + { + {"ppu_pbu_mcode_pf_rsp_afifo_64x16_wrapper_u0r_underflow_flag", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"ppu_pbu_mcode_pf_rsp_afifo_64x16_wrapper_u0_overflow_flag", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_mccnt_fifo_interrupt_flag_reg[] = + { + {"ppu_mccnt_fifo_32x15_wrapper_u0_overflow_flag", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"ppu_mccnt_fifo_32x15_wrapper_u0_underflow_flag", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"ppu_wb_data_fifo_32x2048_wrapper_u0_overflow_flag", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"ppu_wb_data_fifo_32x2048_wrapper_u0_underflow_flag", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"mccnt_rsp_fifo_32x1_wrapper_u0_overflow_flag", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"mccnt_rsp_fifo_32x1_wrapper_u0_underflow_flag", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_coprocessor_fifo_interrupt_flag_l_reg[] = + { + {"mec3_cop_key_crc_fifo_32x625_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"mec3_cop_key_crc_fifo_32x625_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"mec3_cop_key_checksum_fifo_32x180_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"mec3_cop_key_checksum_fifo_32x180_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"mec3_cop_key_mul_fifo_32x52_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"mec3_cop_key_mul_fifo_32x52_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"mec3_cop_key_random_mod_fifo_32x44_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"mec3_cop_key_random_mod_fifo_32x44_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"mec2_cop_key_crc_fifo_32x625_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"mec2_cop_key_crc_fifo_32x625_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"mec2_cop_key_checksum_fifo_32x180_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"mec2_cop_key_checksum_fifo_32x180_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"mec2_cop_key_mul_fifo_32x52_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"mec2_cop_key_mul_fifo_32x52_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"mec2_cop_key_random_mod_fifo_32x44_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"mec2_cop_key_random_mod_fifo_32x44_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"mec1_cop_key_crc_fifo_32x625_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"mec1_cop_key_crc_fifo_32x625_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"mec1_cop_key_checksum_fifo_32x180_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"mec1_cop_key_checksum_fifo_32x180_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"mec1_cop_key_mul_fifo_32x52_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"mec1_cop_key_mul_fifo_32x52_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"mec1_cop_key_random_mod_fifo_32x44_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"mec1_cop_key_random_mod_fifo_32x44_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"mec0_cop_key_crc_fifo_32x625_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"mec0_cop_key_crc_fifo_32x625_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"mec0_cop_key_checksum_fifo_32x180_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"mec0_cop_key_checksum_fifo_32x180_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"mec0_cop_key_mul_fifo_32x52_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"mec0_cop_key_mul_fifo_32x52_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"mec0_cop_key_random_mod_fifo_32x44_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"mec0_cop_key_random_mod_fifo_32x44_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_coprocessor_fifo_interrupt_flag_m_reg[] = + { + {"ppu_cop_result_fwft_fifo_80x80_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"ppu_cop_result_fwft_fifo_80x80_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"ppu_cop_delay_fifo_48x16_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"ppu_cop_delay_fifo_48x16_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"ppu_cop_delay_fifo_16x48_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"ppu_cop_delay_fifo_16x48_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"ppu_cop_delay_fifo_16x32_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"ppu_cop_delay_fifo_16x32_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"ppu_cop_result_fwft_fifo_96x80_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"ppu_cop_result_fwft_fifo_96x80_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"ppu_cop_delay_fifo_16x16_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"ppu_cop_delay_fifo_16x16_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"ppu_cop_result_fwft_fifo_32x80_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"ppu_cop_result_fwft_fifo_32x80_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"ppu_cop_result_fwft_fifo_16x80_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"ppu_cop_result_fwft_fifo_16x80_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"mec5_cop_key_crc_fifo_32x625_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"mec5_cop_key_crc_fifo_32x625_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"mec5_cop_key_checksum_fifo_32x180_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"mec5_cop_key_checksum_fifo_32x180_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"mec5_cop_key_mul_fifo_32x52_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"mec5_cop_key_mul_fifo_32x52_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"mec5_cop_key_random_mod_fifo_32x44_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"mec5_cop_key_random_mod_fifo_32x44_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"mec4_cop_key_crc_fifo_32x625_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"mec4_cop_key_crc_fifo_32x625_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"mec4_cop_key_checksum_fifo_32x180_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"mec4_cop_key_checksum_fifo_32x180_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"mec4_cop_key_mul_fifo_32x52_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"mec4_cop_key_mul_fifo_32x52_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"mec4_cop_key_random_mod_fifo_32x44_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"mec4_cop_key_random_mod_fifo_32x44_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_coprocessor_fifo_interrupt_flag_h_reg[] = + { + {"ppu_cop_random_mod_para_delay_fifo_48x16_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"ppu_cop_random_mod_para_delay_fifo_48x16_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_instrmem_fifo_interrupt_flag_reg[] = + { + {"instrmem2_wr_fifo_ovf_flag", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"instrmem2_wr_fifo_udf_flag", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"instrmem2_rd_fifo_ovf_flag", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"instrmem2_rd_fifo_udf_flag", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"instrmem1_wr_fifo_ovf_flag", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"instrmem1_wr_fifo_udf_flag", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"instrmem1_rd_fifo_ovf_flag", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"instrmem1_rd_fifo_udf_flag", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"instrmem0_wr_fifo_ovf_flag", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"instrmem0_wr_fifo_udf_flag", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"instrmem0_rd_fifo_ovf_flag", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"instrmem0_rd_fifo_udf_flag", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_instrmem_ram_int_out_reg[] = + { + {"instrmem2_bank3_ram_parity_err_int_out", DPP_FIELD_FLAG_RO, 11, 1, 0x0, 0x0}, + {"instrmem2_bank2_ram_parity_err_int_out", DPP_FIELD_FLAG_RO, 10, 1, 0x0, 0x0}, + {"instrmem2_bank1_ram_parity_err_int_out", DPP_FIELD_FLAG_RO, 9, 1, 0x0, 0x0}, + {"instrmem2_bank0_ram_parity_err_int_out", DPP_FIELD_FLAG_RO, 8, 1, 0x0, 0x0}, + {"instrmem1_bank3_ram_parity_err_int_out", DPP_FIELD_FLAG_RO, 7, 1, 0x0, 0x0}, + {"instrmem1_bank2_ram_parity_err_int_out", DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0}, + {"instrmem1_bank1_ram_parity_err_int_out", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0}, + {"instrmem1_bank0_ram_parity_err_int_out", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0}, + {"instrmem0_bank3_ram_parity_err_int_out", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0}, + {"instrmem0_bank2_ram_parity_err_int_out", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0}, + {"instrmem0_bank1_ram_parity_err_int_out", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0}, + {"instrmem0_bank0_ram_parity_err_int_out", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_instrmem_ram_int_mask_reg[] = + { + {"instrmem2_bank3_ram_parity_err_mask", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"instrmem2_bank2_ram_parity_err_mask", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"instrmem2_bank1_ram_parity_err_mask", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"instrmem2_bank0_ram_parity_err_mask", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"instrmem1_bank3_ram_parity_err_mask", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"instrmem1_bank2_ram_parity_err_mask", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"instrmem1_bank1_ram_parity_err_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"instrmem1_bank0_ram_parity_err_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"instrmem0_bank3_ram_parity_err_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"instrmem0_bank2_ram_parity_err_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"instrmem0_bank1_ram_parity_err_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"instrmem0_bank0_ram_parity_err_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_instrmem_ram_int_stat_reg[] = + { + {"instrmem2_bank3_ram_parity_errstat", DPP_FIELD_FLAG_RO, 11, 1, 0x0, 0x0}, + {"instrmem2_bank2_ram_parity_errstat", DPP_FIELD_FLAG_RO, 10, 1, 0x0, 0x0}, + {"instrmem2_bank1_ram_parity_errstat", DPP_FIELD_FLAG_RO, 9, 1, 0x0, 0x0}, + {"instrmem2_bank0_ram_parity_errstat", DPP_FIELD_FLAG_RO, 8, 1, 0x0, 0x0}, + {"instrmem1_bank3_ram_parity_errstat", DPP_FIELD_FLAG_RO, 7, 1, 0x0, 0x0}, + {"instrmem1_bank2_ram_parity_errstat", DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0}, + {"instrmem1_bank1_ram_parity_errstat", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0}, + {"instrmem1_bank0_ram_parity_errstat", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0}, + {"instrmem0_bank3_ram_parity_errstat", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0}, + {"instrmem0_bank2_ram_parity_errstat", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0}, + {"instrmem0_bank1_ram_parity_errstat", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0}, + {"instrmem0_bank0_ram_parity_errstat", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_instrmem_ram_int_flag_reg[] = + { + {"instrmem2_bank3_ram_parity_err_flag", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"instrmem2_bank2_ram_parity_err_flag", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"instrmem2_bank1_ram_parity_err_flag", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"instrmem2_bank0_ram_parity_err_flag", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"instrmem1_bank3_ram_parity_err_flag", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"instrmem1_bank2_ram_parity_err_flag", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"instrmem1_bank1_ram_parity_err_flag", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"instrmem1_bank0_ram_parity_err_flag", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"instrmem0_bank3_ram_parity_err_flag", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"instrmem0_bank2_ram_parity_err_flag", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"instrmem0_bank1_ram_parity_err_flag", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"instrmem0_bank0_ram_parity_err_flag", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_count_cfg_reg[] = + { + {"ppu_count_overflow_mode", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"ppu_count_rd_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_statics_cfg_reg[] = + { + {"csr_statics_mc_type", DPP_FIELD_FLAG_RW, 24, 1, 0x0, 0x0}, + {"csr_statics_bufnum", DPP_FIELD_FLAG_RW, 22, 7, 0x0, 0x0}, + {"csr_statics_portnum1", DPP_FIELD_FLAG_RW, 15, 8, 0xc1, 0x0}, + {"csr_statics_portnum0", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_statics_wb_cfg_reg[] = + { + {"csr_statics_wb_halt_send_type", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"csr_statics_wb_mf_type", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"csr_statics_wb_halt_continue_end", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"csr_statics_wb_dup_flag", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"csr_statics_wb_last_flag", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"csr_statics_wb_dis_flag", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_wr_table_self_rsp_en_cfg_reg[] = + { + {"wr_table_self_rsp_en_cfg", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_random_arbiter_8to1_cfg_reg[] = + { + {"ppu_random_arbiter_8to1_cfg", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_reorder_bypass_flow_num_cfg_reg[] = + { + {"ppu_reorder_bypass_flow_num_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_cos_meter_cfg_h_reg[] = + { + {"cbs", DPP_FIELD_FLAG_RW, 22, 10, 0x3ff, 0x0}, + {"pbs", DPP_FIELD_FLAG_RW, 12, 10, 0x3ff, 0x0}, + {"green_action", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"yellow_action", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"red_action", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_cos_meter_cfg_l_reg[] = + { + {"cir", DPP_FIELD_FLAG_RW, 20, 10, 0x24a, 0x0}, + {"pir", DPP_FIELD_FLAG_RW, 10, 10, 0x24a, 0x0}, + {"car_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_instrmem_rdy_reg[] = + { + {"instrmem_rdy", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_instrmem_addr_reg[] = + { + {"instrmem_operate", DPP_FIELD_FLAG_WO, 13, 1, 0x0, 0x0}, + {"instrmem_addr", DPP_FIELD_FLAG_WO, 12, 13, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_instrmem_ind_access_done_reg[] = + { + {"instrmem_ind_access_done", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_instrmem_instr0_data_l_reg[] = + { + {"instrmem_instr0_data_l", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_instrmem_instr0_data_h_reg[] = + { + {"instrmem_instr0_data_h", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_instrmem_instr1_data_l_reg[] = + { + {"instrmem_instr1_data_l", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_instrmem_instr1_data_h_reg[] = + { + {"instrmem_instr1_data_h", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_instrmem_instr2_data_l_reg[] = + { + {"instrmem_instr2_data_l", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_instrmem_instr2_data_h_reg[] = + { + {"instrmem_instr2_data_h", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_instrmem_instr3_data_l_reg[] = + { + {"instrmem_instr3_data_l", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_instrmem_instr3_data_h_reg[] = + { + {"instrmem_instr3_data_h", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_instrmem_read_instr0_data_l_reg[] = + { + {"instrmem_read_instr0_data_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_instrmem_read_instr0_data_h_reg[] = + { + {"instrmem_read_instr0_data_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_instrmem_read_instr1_data_l_reg[] = + { + {"instrmem_read_instr1_data_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_instrmem_read_instr1_data_h_reg[] = + { + {"instrmem_read_instr1_data_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_instrmem_read_instr2_data_l_reg[] = + { + {"instrmem_read_instr2_data_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_instrmem_read_instr2_data_h_reg[] = + { + {"instrmem_read_instr2_data_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_instrmem_read_instr3_data_l_reg[] = + { + {"instrmem_read_instr3_data_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_instrmem_read_instr3_data_h_reg[] = + { + {"instrmem_read_instr3_data_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_se_ppu_mc_srh_fc_cnt_h_reg[] = + { + {"se_ppu_mc_srh_fc_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_se_ppu_mc_srh_fc_cnt_l_reg[] = + { + {"se_ppu_mc_srh_fc_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_se_mc_srh_fc_cnt_h_reg[] = + { + {"ppu_se_mc_srh_fc_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_se_mc_srh_fc_cnt_l_reg[] = + { + {"ppu_se_mc_srh_fc_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_se_mc_srh_vld_cnt_h_reg[] = + { + {"ppu_se_mc_srh_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_se_mc_srh_vld_cnt_l_reg[] = + { + {"ppu_se_mc_srh_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_se_ppu_mc_srh_vld_cnt_h_reg[] = + { + {"se_ppu_mc_srh_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_se_ppu_mc_srh_vld_cnt_l_reg[] = + { + {"se_ppu_mc_srh_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pbu_ppu_logic_pf_fc_cnt_h_reg[] = + { + {"pbu_ppu_logic_pf_fc_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pbu_ppu_logic_pf_fc_cnt_l_reg[] = + { + {"pbu_ppu_logic_pf_fc_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_pbu_logic_rsp_fc_cnt_h_reg[] = + { + {"ppu_pbu_logic_rsp_fc_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_pbu_logic_rsp_fc_cnt_l_reg[] = + { + {"ppu_pbu_logic_rsp_fc_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_pbu_logic_pf_req_vld_cnt_h_reg[] = + { + {"ppu_pbu_logic_pf_req_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_pbu_logic_pf_req_vld_cnt_l_reg[] = + { + {"ppu_pbu_logic_pf_req_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pbu_ppu_logic_pf_rsp_vld_cnt_h_reg[] = + { + {"pbu_ppu_logic_pf_rsp_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pbu_ppu_logic_pf_rsp_vld_cnt_l_reg[] = + { + {"pbu_ppu_logic_pf_rsp_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pbu_ppu_ifb_rd_fc_cnt_h_reg[] = + { + {"pbu_ppu_ifb_rd_fc_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pbu_ppu_ifb_rd_fc_cnt_l_reg[] = + { + {"pbu_ppu_ifb_rd_fc_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pbu_ppu_wb_fc_cnt_h_reg[] = + { + {"pbu_ppu_wb_fc_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pbu_ppu_wb_fc_cnt_l_reg[] = + { + {"pbu_ppu_wb_fc_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_pbu_mcode_pf_req_vld_cnt_h_reg[] = + { + {"ppu_pbu_mcode_pf_req_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_pbu_mcode_pf_req_vld_cnt_l_reg[] = + { + {"ppu_pbu_mcode_pf_req_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pbu_ppu_mcode_pf_rsp_vld_cnt_h_reg[] = + { + {"pbu_ppu_mcode_pf_rsp_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pbu_ppu_mcode_pf_rsp_vld_cnt_l_reg[] = + { + {"pbu_ppu_mcode_pf_rsp_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_odma_ppu_para_fc_cnt_h_reg[] = + { + {"odma_ppu_para_fc_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_odma_ppu_para_fc_cnt_l_reg[] = + { + {"odma_ppu_para_fc_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_odma_ppu_mccnt_wr_fc_cnt_h_reg[] = + { + {"odma_ppu_mccnt_wr_fc_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_odma_ppu_mccnt_wr_fc_cnt_l_reg[] = + { + {"odma_ppu_mccnt_wr_fc_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_odma_mccnt_wr_vld_cnt_h_reg[] = + { + {"ppu_odma_mccnt_wr_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_odma_mccnt_wr_vld_cnt_l_reg[] = + { + {"ppu_odma_mccnt_wr_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_odma_ppu_mccnt_rsp_vld_cnt_h_reg[] = + { + {"odma_ppu_mccnt_rsp_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_odma_ppu_mccnt_rsp_vld_cnt_l_reg[] = + { + {"odma_ppu_mccnt_rsp_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_pktrx_uc_fc_cnt_h_reg[] = + { + {"ppu_pktrx_uc_fc_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_pktrx_uc_fc_cnt_l_reg[] = + { + {"ppu_pktrx_uc_fc_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_pktrx_mc_fc_cnt_h_reg[] = + { + {"ppu_pktrx_mc_fc_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_pktrx_mc_fc_cnt_l_reg[] = + { + {"ppu_pktrx_mc_fc_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pktrx_ppu_desc_vld_cnt_h_reg[] = + { + {"pktrx_ppu_desc_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pktrx_ppu_desc_vld_cnt_l_reg[] = + { + {"pktrx_ppu_desc_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_pbu_ifb_req_vld_cnt_h_reg[] = + { + {"ppu_pbu_ifb_req_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_pbu_ifb_req_vld_cnt_l_reg[] = + { + {"ppu_pbu_ifb_req_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pbu_ppu_ifb_rsp_vld_cnt_h_reg[] = + { + {"pbu_ppu_ifb_rsp_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pbu_ppu_ifb_rsp_vld_cnt_l_reg[] = + { + {"pbu_ppu_ifb_rsp_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_pbu_wb_vld_cnt_h_reg[] = + { + {"ppu_pbu_wb_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_pbu_wb_vld_cnt_l_reg[] = + { + {"ppu_pbu_wb_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pbu_ppu_reorder_para_vld_cnt_h_reg[] = + { + {"pbu_ppu_reorder_para_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pbu_ppu_reorder_para_vld_cnt_l_reg[] = + { + {"pbu_ppu_reorder_para_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_odma_para_vld_cnt_h_reg[] = + { + {"ppu_odma_para_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_odma_para_vld_cnt_l_reg[] = + { + {"ppu_odma_para_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_statics_isu_ppu_mc_vld_cnt_h_reg[] = + { + {"statics_isu_ppu_mc_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_statics_isu_ppu_mc_vld_cnt_l_reg[] = + { + {"statics_isu_ppu_mc_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_statics_isu_ppu_mc_loop_vld_cnt_h_reg[] = + { + {"statics_isu_ppu_mc_loop_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_statics_isu_ppu_mc_loop_vld_cnt_l_reg[] = + { + {"statics_isu_ppu_mc_loop_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_statics_isu_ppu_uc_vld_cnt_h_reg[] = + { + {"statics_isu_ppu_uc_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_statics_isu_ppu_uc_vld_cnt_l_reg[] = + { + {"statics_isu_ppu_uc_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_statics_isu_ppu_uc_bufnumis0_vld_cnt_h_reg[] = + { + {"statics_isu_ppu_uc_bufnumis0_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_statics_isu_ppu_uc_bufnumis0_vld_cnt_l_reg[] = + { + {"statics_isu_ppu_uc_bufnumis0_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_statics_demux_schedule_mc_vld_cnt_h_reg[] = + { + {"statics_demux_schedule_mc_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_statics_demux_schedule_mc_vld_cnt_l_reg[] = + { + {"statics_demux_schedule_mc_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_statics_demux_schedule_mc_bufnumis0_vld_cnt_h_reg[] = + { + {"statics_demux_schedule_mc_bufnumis0_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_statics_demux_schedule_mc_bufnumis0_vld_cnt_l_reg[] = + { + {"statics_demux_schedule_mc_bufnumis0_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_statics_demux_schedule_mc_srcportis0_vld_cnt_h_reg[] = + { + {"statics_demux_schedule_mc_srcportis0_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_statics_demux_schedule_mc_srcportis0_vld_cnt_l_reg[] = + { + {"statics_demux_schedule_mc_srcportis0_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_statics_demux_schedule_mc_srcportis1_vld_cnt_h_reg[] = + { + {"statics_demux_schedule_mc_srcportis1_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_statics_demux_schedule_mc_srcportis1_vld_cnt_l_reg[] = + { + {"statics_demux_schedule_mc_srcportis1_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_statics_demux_schedule_uc_vld_cnt_h_reg[] = + { + {"statics_demux_schedule_uc_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_statics_demux_schedule_uc_vld_cnt_l_reg[] = + { + {"statics_demux_schedule_uc_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_statics_demux_schedule_uc_bufnumis0_vld_cnt_h_reg[] = + { + {"statics_demux_schedule_uc_bufnumis0_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_statics_demux_schedule_uc_bufnumis0_vld_cnt_l_reg[] = + { + {"statics_demux_schedule_uc_bufnumis0_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_statics_demux_schedule_uc_srcportis0_vld_cnt_h_reg[] = + { + {"statics_demux_schedule_uc_srcportis0_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_statics_demux_schedule_uc_srcportis0_vld_cnt_l_reg[] = + { + {"statics_demux_schedule_uc_srcportis0_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_statics_demux_schedule_uc_srcportis1_vld_cnt_h_reg[] = + { + {"statics_demux_schedule_uc_srcportis1_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_statics_demux_schedule_uc_srcportis1_vld_cnt_l_reg[] = + { + {"statics_demux_schedule_uc_srcportis1_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_statics_ppu_wb_vld_cnt_h_reg[] = + { + {"statics_ppu_wb_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_statics_ppu_wb_vld_cnt_l_reg[] = + { + {"statics_ppu_wb_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_statics_ppu_wb_bufnumis0_vld_cnt_h_reg[] = + { + {"statics_ppu_wb_bufnumis0_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_statics_ppu_wb_bufnumis0_vld_cnt_l_reg[] = + { + {"statics_ppu_wb_bufnumis0_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_statics_ppu_wb_srcportis0_vld_cnt_h_reg[] = + { + {"statics_ppu_wb_srcportis0_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_statics_ppu_wb_srcportis0_vld_cnt_l_reg[] = + { + {"statics_ppu_wb_srcportis0_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_statics_ppu_wb_srcportis1_vld_cnt_h_reg[] = + { + {"statics_ppu_wb_srcportis1_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_statics_ppu_wb_srcportis1_vld_cnt_l_reg[] = + { + {"statics_ppu_wb_srcportis1_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_statics_ppu_wb_halt_send_type_vld_cnt_h_reg[] = + { + {"statics_ppu_wb_halt_send_type_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_statics_ppu_wb_halt_send_type_vld_cnt_l_reg[] = + { + {"statics_ppu_wb_halt_send_type_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_statics_ppu_wb_mf_type_vld_cnt_h_reg[] = + { + {"statics_ppu_wb_mf_type_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_statics_ppu_wb_mf_type_vld_cnt_l_reg[] = + { + {"statics_ppu_wb_mf_type_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_statics_ppu_wb_halt_continue_end_vld_cnt_h_reg[] = + { + {"statics_ppu_wb_halt_continue_end_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_statics_ppu_wb_halt_continue_end_vld_cnt_l_reg[] = + { + {"statics_ppu_wb_halt_continue_end_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_statics_ppu_wb_dup_flag_vld_cnt_h_reg[] = + { + {"statics_ppu_wb_dup_flag_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_statics_ppu_wb_dup_flag_vld_cnt_l_reg[] = + { + {"statics_ppu_wb_dup_flag_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_statics_ppu_wb_last_flag_vld_cnt_h_reg[] = + { + {"statics_ppu_wb_last_flag_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_statics_ppu_wb_last_flag_vld_cnt_l_reg[] = + { + {"statics_ppu_wb_last_flag_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_statics_ppu_wb_dis_flag_vld_cnt_h_reg[] = + { + {"statics_ppu_wb_dis_flag_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_statics_ppu_wb_dis_flag_vld_cnt_l_reg[] = + { + {"statics_ppu_wb_dis_flag_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_statics_pbu_ppu_reorder_halt_send_type_vld_cnt_h_reg[] = + { + {"statics_pbu_ppu_reorder_halt_send_type_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_statics_pbu_ppu_reorder_halt_send_type_vld_cnt_l_reg[] = + { + {"statics_pbu_ppu_reorder_halt_send_type_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_statics_pbu_ppu_reorder_mf_type_vld_cnt_h_reg[] = + { + {"statics_pbu_ppu_reorder_mf_type_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_statics_pbu_ppu_reorder_mf_type_vld_cnt_l_reg[] = + { + {"statics_pbu_ppu_reorder_mf_type_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_statics_pbu_ppu_reorder_halt_continue_end_vld_cnt_h_reg[] = + { + {"statics_pbu_ppu_reorder_halt_continue_end_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_statics_pbu_ppu_reorder_halt_continue_end_vld_cnt_l_reg[] = + { + {"statics_pbu_ppu_reorder_halt_continue_end_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_car_green_pkt_vld_cnt_h_reg[] = + { + {"car_green_pkt_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_car_green_pkt_vld_cnt_l_reg[] = + { + {"car_green_pkt_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_car_yellow_pkt_vld_cnt_h_reg[] = + { + {"car_yellow_pkt_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_car_yellow_pkt_vld_cnt_l_reg[] = + { + {"car_yellow_pkt_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_car_red_pkt_vld_cnt_h_reg[] = + { + {"car_red_pkt_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_car_red_pkt_vld_cnt_l_reg[] = + { + {"car_red_pkt_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_car_drop_pkt_vld_cnt_h_reg[] = + { + {"car_drop_pkt_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_car_drop_pkt_vld_cnt_l_reg[] = + { + {"car_drop_pkt_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_pktrx_mc_ptr_vld_cnt_h_reg[] = + { + {"ppu_pktrx_mc_ptr_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_pktrx_mc_ptr_vld_cnt_l_reg[] = + { + {"ppu_pktrx_mc_ptr_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_isu_ppu_loopback_fc_cnt_h_reg[] = + { + {"ppu_pktrx_mc_ptr_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_isu_ppu_loopback_fc_cnt_l_reg[] = + { + {"ppu_pktrx_mc_ptr_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_culster_pbu_mcode_pf_req_prog_full_assert_cfg_reg[] = + { + {"ppu_culster_pbu_mcode_pf_req_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x10, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_culster_pbu_mcode_pf_req_prog_full_negate_cfg_reg[] = + { + {"ppu_culster_pbu_mcode_pf_req_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x10, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_culster_pbu_mcode_pf_req_prog_empty_assert_cfg_reg[] = + { + {"ppu_culster_pbu_mcode_pf_req_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_culster_pbu_mcode_pf_req_prog_empty_negate_cfg_reg[] = + { + {"ppu_culster_pbu_mcode_pf_req_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_pbu_mcode_pf_rsp_prog_full_assert_cfg_reg[] = + { + {"ppu_pbu_mcode_pf_rsp_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x20, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_pbu_mcode_pf_rsp_prog_full_negate_cfg_reg[] = + { + {"ppu_pbu_mcode_pf_rsp_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x20, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_pbu_mcode_pf_rsp_prog_empty_assert_cfg_reg[] = + { + {"ppu_pbu_mcode_pf_rsp_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_pbu_mcode_pf_rsp_prog_empty_negate_cfg_reg[] = + { + {"ppu_pbu_mcode_pf_rsp_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_mccnt_fifo_prog_full_assert_cfg_reg[] = + { + {"mccnt_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x1c, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_mccnt_fifo_prog_full_negate_cfg_reg[] = + { + {"mccnt_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x1c, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_mccnt_fifo_prog_empty_assert_cfg_reg[] = + { + {"mccnt_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_mccnt_fifo_prog_empty_negate_cfg_reg[] = + { + {"mccnt_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_uc_mf_fifo_prog_full_assert_cfg_reg[] = + { + {"uc_mf_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x10, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_uc_mf_fifo_prog_full_negate_cfg_reg[] = + { + {"uc_mf_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x10, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_uc_mf_fifo_prog_empty_assert_cfg_reg[] = + { + {"uc_mf_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_uc_mf_fifo_prog_empty_negate_cfg_reg[] = + { + {"uc_mf_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_mc_mf_fifo_prog_full_assert_cfg_reg[] = + { + {"mc_mf_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0xa, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_mc_mf_fifo_prog_full_negate_cfg_reg[] = + { + {"mc_mf_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0xa, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_mc_mf_fifo_prog_empty_assert_cfg_reg[] = + { + {"mc_mf_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_mc_mf_fifo_prog_empty_negate_cfg_reg[] = + { + {"mc_mf_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_isu_mf_fifo_prog_full_assert_cfg_reg[] = + { + {"isu_mf_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x10, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_isu_mf_fifo_prog_full_negate_cfg_reg[] = + { + {"isu_mf_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x10, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_isu_mf_fifo_prog_empty_assert_cfg_reg[] = + { + {"isu_mf_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_isu_mf_fifo_prog_empty_negate_cfg_reg[] = + { + {"isu_mf_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_isu_fwft_mf_fifo_prog_empty_assert_cfg_reg[] = + { + {"isu_fwft_mf_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_isu_fwft_mf_fifo_prog_empty_negate_cfg_reg[] = + { + {"isu_fwft_mf_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_isu_mc_para_mf_fifo_prog_full_assert_cfg_reg[] = + { + {"isu_mc_para_mf_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x50, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_isu_mc_para_mf_fifo_prog_full_negate_cfg_reg[] = + { + {"isu_mc_para_mf_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x50, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_isu_mc_para_mf_fifo_prog_empty_assert_cfg_reg[] = + { + {"isu_mc_para_mf_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_isu_mc_para_mf_fifo_prog_empty_negate_cfg_reg[] = + { + {"isu_mc_para_mf_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_group_id_fifo_prog_full_assert_cfg_reg[] = + { + {"group_id_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x3c, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_group_id_fifo_prog_full_negate_cfg_reg[] = + { + {"group_id_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x3c, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_group_id_fifo_prog_empty_assert_cfg_reg[] = + { + {"group_id_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_group_id_fifo_prog_empty_negate_cfg_reg[] = + { + {"group_id_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_sa_para_fifo_prog_full_assert_cfg_reg[] = + { + {"sa_para_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x3c, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_sa_para_fifo_prog_full_negate_cfg_reg[] = + { + {"sa_para_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x3c, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_sa_para_fifo_prog_empty_assert_cfg_reg[] = + { + {"sa_para_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_sa_para_fifo_prog_empty_negate_cfg_reg[] = + { + {"sa_para_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_se_mc_rsp_fifo_prog_full_assert_cfg_reg[] = + { + {"se_mc_rsp_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0xa, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_se_mc_rsp_fifo_prog_full_negate_cfg_reg[] = + { + {"se_mc_rsp_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0xa, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_se_mc_rsp_fifo_prog_empty_assert_cfg_reg[] = + { + {"se_mc_rsp_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_se_mc_rsp_fifo_prog_empty_negate_cfg_reg[] = + { + {"se_mc_rsp_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_dup_para_fifo_prog_full_assert_cfg_reg[] = + { + {"dup_para_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0xc, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_dup_para_fifo_prog_full_negate_cfg_reg[] = + { + {"dup_para_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0xc, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_dup_para_fifo_prog_empty_assert_cfg_reg[] = + { + {"dup_para_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_dup_para_fifo_prog_empty_negate_cfg_reg[] = + { + {"dup_para_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pf_rsp_fifo_prog_full_assert_cfg_reg[] = + { + {"pf_rsp_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x10, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pf_rsp_fifo_prog_full_negate_cfg_reg[] = + { + {"pf_rsp_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x10, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pf_rsp_fifo_prog_empty_assert_cfg_reg[] = + { + {"pf_rsp_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pf_rsp_fifo_prog_empty_negate_cfg_reg[] = + { + {"pf_rsp_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_dup_freeptr_fifo_prog_full_assert_cfg_reg[] = + { + {"dup_freeptr_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x7c, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_dup_freeptr_fifo_prog_full_negate_cfg_reg[] = + { + {"dup_freeptr_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x7c, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_dup_freeptr_fifo_prog_empty_assert_cfg_reg[] = + { + {"dup_freeptr_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x58, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_dup_freeptr_fifo_prog_empty_negate_cfg_reg[] = + { + {"dup_freeptr_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x58, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pf_req_fifo_prog_full_assert_cfg_reg[] = + { + {"pf_req_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0xc, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pf_req_fifo_prog_full_negate_cfg_reg[] = + { + {"pf_req_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0xc, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pf_req_fifo_prog_empty_assert_cfg_reg[] = + { + {"pf_req_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pf_req_fifo_prog_empty_negate_cfg_reg[] = + { + {"pf_req_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_car_flag_fifo_prog_full_assert_cfg_reg[] = + { + {"car_flag_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x18, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_car_flag_fifo_prog_full_negate_cfg_reg[] = + { + {"car_flag_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x18, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_car_flag_fifo_prog_empty_assert_cfg_reg[] = + { + {"car_flag_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_car_flag_fifo_prog_empty_negate_cfg_reg[] = + { + {"car_flag_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_cluster_mf_out_afifo_prog_full_assert_cfg_reg[] = + { + {"ppu_cluster_mf_out_afifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x10, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_cluster_mf_out_afifo_prog_full_negate_cfg_reg[] = + { + {"ppu_cluster_mf_out_afifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x10, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_cluster_mf_out_afifo_prog_empty_assert_cfg_reg[] = + { + {"ppu_cluster_mf_out_afifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_cluster_mf_out_afifo_prog_empty_negate_cfg_reg[] = + { + {"ppu_cluster_mf_out_afifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_cop_key_fifo_prog_full_assert_cfg_reg[] = + { + {"ppu_cop_key_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x18, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_cop_key_fifo_prog_full_negate_cfg_reg[] = + { + {"ppu_cop_key_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x18, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_cop_key_fifo_prog_empty_assert_cfg_reg[] = + { + {"ppu_cop_key_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_cop_key_fifo_prog_empty_negate_cfg_reg[] = + { + {"ppu_cop_key_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_cop_random_mod_para_fifo_prog_full_assert_cfg_reg[] = + { + {"ppu_cop_random_mod_para_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x24, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_cop_random_mod_para_fifo_prog_full_negate_cfg_reg[] = + { + {"ppu_cop_random_mod_para_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x24, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_cop_random_mod_para_fifo_prog_empty_assert_cfg_reg[] = + { + {"ppu_cop_random_mod_para_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_cop_random_mod_para_fifo_prog_empty_negate_cfg_reg[] = + { + {"ppu_cop_random_mod_para_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_cop_random_mod_result_fifo_prog_full_assert_cfg_reg[] = + { + {"ppu_cop_random_mod_result_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x28, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_cop_random_mod_result_fifo_prog_full_negate_cfg_reg[] = + { + {"ppu_cop_random_mod_result_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x28, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_cop_random_mod_result_fifo_prog_empty_assert_cfg_reg[] = + { + {"ppu_cop_random_mod_result_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_cop_random_mod_result_fifo_prog_empty_negate_cfg_reg[] = + { + {"ppu_cop_random_mod_result_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_cop_checksum_result_fifo_prog_full_assert_cfg_reg[] = + { + {"ppu_cop_checksum_result_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0xa, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_cop_checksum_result_fifo_prog_full_negate_cfg_reg[] = + { + {"ppu_cop_checksum_result_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0xa, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_cop_checksum_result_fifo_prog_empty_assert_cfg_reg[] = + { + {"ppu_cop_checksum_result_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_cop_checksum_result_fifo_prog_empty_negate_cfg_reg[] = + { + {"ppu_cop_checksum_result_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_cop_crc_first_para_fifo_prog_full_assert_cfg_reg[] = + { + {"ppu_cop_crc_first_para_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0xe, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_cop_crc_first_para_fifo_prog_full_negate_cfg_reg[] = + { + {"ppu_cop_crc_first_para_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0xe, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_cop_crc_first_para_fifo_prog_empty_assert_cfg_reg[] = + { + {"ppu_cop_crc_first_para_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_cop_crc_first_para_fifo_prog_empty_negate_cfg_reg[] = + { + {"ppu_cop_crc_first_para_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_cop_crc_bypass_delay_prog_full_assert_cfg_reg[] = + { + {"ppu_cop_crc_bypass_delay_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0xe, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_cop_crc_bypass_delay_prog_full_negate_cfg_reg[] = + { + {"ppu_cop_crc_bypass_delay_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0xe, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_cop_crc_bypass_delay_prog_empty_assert_cfg_reg[] = + { + {"ppu_cop_crc_bypass_delay_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_cop_crc_bypass_delay_prog_empty_negate_cfg_reg[] = + { + {"ppu_cop_crc_bypass_delay_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_cop_crc_second_para_fifo_prog_full_assert_cfg_reg[] = + { + {"ppu_cop_crc_second_para_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x24, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_cop_crc_second_para_fifo_prog_full_negate_cfg_reg[] = + { + {"ppu_cop_crc_second_para_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x24, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_cop_crc_second_para_fifo_prog_empty_assert_cfg_reg[] = + { + {"ppu_cop_crc_second_para_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_cop_crc_second_para_fifo_prog_empty_negate_cfg_reg[] = + { + {"ppu_cop_crc_second_para_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_cop_crc_result_fwft_fifo_prog_full_assert_cfg_reg[] = + { + {"ppu_cop_crc_result_fwft_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x30, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_cop_crc_result_fwft_fifo_prog_full_negate_cfg_reg[] = + { + {"ppu_cop_crc_result_fwft_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x30, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_cop_crc_result_fwft_fifo_prog_empty_assert_cfg_reg[] = + { + {"ppu_cop_crc_result_fwft_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_cop_crc_result_fwft_fifo_prog_empty_negate_cfg_reg[] = + { + {"ppu_cop_crc_result_fwft_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_cop_multiply_para_fifo_prog_full_assert_cfg_reg[] = + { + {"ppu_cop_multiply_para_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0xa, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_cop_multiply_para_fifo_prog_full_negate_cfg_reg[] = + { + {"ppu_cop_multiply_para_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0xa, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_cop_multiply_para_fifo_prog_empty_assert_cfg_reg[] = + { + {"ppu_cop_multiply_para_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_cop_multiply_para_fifo_prog_empty_negate_cfg_reg[] = + { + {"ppu_cop_multiply_para_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_cop_multiply_para_result_fifo_prog_full_assert_cfg_reg[] = + { + {"ppu_cop_multiply_para_result_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x18, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_cop_multiply_para_result_fifo_prog_full_negate_cfg_reg[] = + { + {"ppu_cop_multiply_para_result_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x18, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_cop_multiply_para_result_fifo_prog_empty_assert_cfg_reg[] = + { + {"ppu_cop_multiply_para_result_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_cop_multiply_para_result_fifo_prog_empty_negate_cfg_reg[] = + { + {"ppu_cop_multiply_para_result_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_free_global_num_fwft_fifo_prog_full_assert_cfg_reg[] = + { + {"free_global_num_fwft_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 12, 13, 0xffc, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_free_global_num_fwft_fifo_prog_full_negate_cfg_reg[] = + { + {"free_global_num_fwft_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 12, 13, 0xffc, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_free_global_num_fwft_fifo_prog_empty_assert_cfg_reg[] = + { + {"free_global_num_fwft_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 12, 13, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_free_global_num_fwft_fifo_prog_empty_negate_cfg_reg[] = + { + {"free_global_num_fwft_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 12, 13, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_pktrx_mc_ptr_fifo_prog_full_assert_cfg_reg[] = + { + {"ppu_pktrx_mc_ptr_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 14, 15, 0x3ff6, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_pktrx_mc_ptr_fifo_prog_full_negate_cfg_reg[] = + { + {"ppu_pktrx_mc_ptr_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 14, 15, 0x3ff6, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_pktrx_mc_ptr_fifo_prog_empty_assert_cfg_reg[] = + { + {"ppu_pktrx_mc_ptr_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 14, 15, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_ppu_pktrx_mc_ptr_fifo_prog_empty_negate_cfg_reg[] = + { + {"ppu_pktrx_mc_ptr_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 14, 15, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data0_reg[] = + { + {"pkt_data0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data1_reg[] = + { + {"pkt_data1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data2_reg[] = + { + {"pkt_data2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data3_reg[] = + { + {"pkt_data3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data4_reg[] = + { + {"pkt_data4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data5_reg[] = + { + {"pkt_data5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data6_reg[] = + { + {"pkt_data6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data7_reg[] = + { + {"pkt_data7", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data8_reg[] = + { + {"pkt_data8", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data9_reg[] = + { + {"pkt_data9", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data10_reg[] = + { + {"pkt_data10", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data11_reg[] = + { + {"pkt_data11", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data12_reg[] = + { + {"pkt_data12", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data13_reg[] = + { + {"pkt_data13", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data14_reg[] = + { + {"pkt_data14", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data15_reg[] = + { + {"pkt_data15", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data16_reg[] = + { + {"pkt_data16", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data17_reg[] = + { + {"pkt_data17", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data18_reg[] = + { + {"pkt_data18", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data19_reg[] = + { + {"pkt_data19", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data20_reg[] = + { + {"pkt_data20", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data21_reg[] = + { + {"pkt_data21", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data22_reg[] = + { + {"pkt_data22", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data23_reg[] = + { + {"pkt_data23", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data24_reg[] = + { + {"pkt_data24", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data25_reg[] = + { + {"pkt_data25", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data26_reg[] = + { + {"pkt_data26", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data27_reg[] = + { + {"pkt_data27", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data28_reg[] = + { + {"pkt_data28", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data29_reg[] = + { + {"pkt_data29", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data30_reg[] = + { + {"pkt_data30", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data31_reg[] = + { + {"pkt_data31", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data32_reg[] = + { + {"pkt_data32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data33_reg[] = + { + {"pkt_data33", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data34_reg[] = + { + {"pkt_data34", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data35_reg[] = + { + {"pkt_data35", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data36_reg[] = + { + {"pkt_data36", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data37_reg[] = + { + {"pkt_data37", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data38_reg[] = + { + {"pkt_data38", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data39_reg[] = + { + {"pkt_data39", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data40_reg[] = + { + {"pkt_data40", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data41_reg[] = + { + {"pkt_data41", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data42_reg[] = + { + {"pkt_data42", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data43_reg[] = + { + {"pkt_data43", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data44_reg[] = + { + {"pkt_data44", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data45_reg[] = + { + {"pkt_data45", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data46_reg[] = + { + {"pkt_data46", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data47_reg[] = + { + {"pkt_data47", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data48_reg[] = + { + {"pkt_data48", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data49_reg[] = + { + {"pkt_data49", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data50_reg[] = + { + {"pkt_data50", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data51_reg[] = + { + {"pkt_data51", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data52_reg[] = + { + {"pkt_data52", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data53_reg[] = + { + {"pkt_data53", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data54_reg[] = + { + {"pkt_data54", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data55_reg[] = + { + {"pkt_data55", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data56_reg[] = + { + {"pkt_data56", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data57_reg[] = + { + {"pkt_data57", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data58_reg[] = + { + {"pkt_data58", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data59_reg[] = + { + {"pkt_data59", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data60_reg[] = + { + {"pkt_data60", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data61_reg[] = + { + {"pkt_data61", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data62_reg[] = + { + {"pkt_data62", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data63_reg[] = + { + {"pkt_data63", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data64_reg[] = + { + {"pkt_data64", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data65_reg[] = + { + {"pkt_data65", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data66_reg[] = + { + {"pkt_data66", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data67_reg[] = + { + {"pkt_data67", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data68_reg[] = + { + {"pkt_data68", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data69_reg[] = + { + {"pkt_data69", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data70_reg[] = + { + {"pkt_data70", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data71_reg[] = + { + {"pkt_data71", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data72_reg[] = + { + {"pkt_data72", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data73_reg[] = + { + {"pkt_data73", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data74_reg[] = + { + {"pkt_data74", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data75_reg[] = + { + {"pkt_data75", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data76_reg[] = + { + {"pkt_data76", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data77_reg[] = + { + {"pkt_data77", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data78_reg[] = + { + {"pkt_data78", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data79_reg[] = + { + {"pkt_data79", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data80_reg[] = + { + {"pkt_data80", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data81_reg[] = + { + {"pkt_data81", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data82_reg[] = + { + {"pkt_data82", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data83_reg[] = + { + {"pkt_data83", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data84_reg[] = + { + {"pkt_data84", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data85_reg[] = + { + {"pkt_data85", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data86_reg[] = + { + {"pkt_data86", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data87_reg[] = + { + {"pkt_data87", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data88_reg[] = + { + {"pkt_data88", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data89_reg[] = + { + {"pkt_data89", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data90_reg[] = + { + {"pkt_data90", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data91_reg[] = + { + {"pkt_data91", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data92_reg[] = + { + {"pkt_data92", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data93_reg[] = + { + {"pkt_data93", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data94_reg[] = + { + {"pkt_data94", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data95_reg[] = + { + {"pkt_data95", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data96_reg[] = + { + {"pkt_data96", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data97_reg[] = + { + {"pkt_data97", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data98_reg[] = + { + {"pkt_data98", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data99_reg[] = + { + {"pkt_data99", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data100_reg[] = + { + {"pkt_data100", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data101_reg[] = + { + {"pkt_data101", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data102_reg[] = + { + {"pkt_data102", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data103_reg[] = + { + {"pkt_data103", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data104_reg[] = + { + {"pkt_data104", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data105_reg[] = + { + {"pkt_data105", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data106_reg[] = + { + {"pkt_data106", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data107_reg[] = + { + {"pkt_data107", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data108_reg[] = + { + {"pkt_data108", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data109_reg[] = + { + {"pkt_data109", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data110_reg[] = + { + {"pkt_data110", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data111_reg[] = + { + {"pkt_data111", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data112_reg[] = + { + {"pkt_data112", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data113_reg[] = + { + {"pkt_data113", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data114_reg[] = + { + {"pkt_data114", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data115_reg[] = + { + {"pkt_data115", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data116_reg[] = + { + {"pkt_data116", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data117_reg[] = + { + {"pkt_data117", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data118_reg[] = + { + {"pkt_data118", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data119_reg[] = + { + {"pkt_data119", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data120_reg[] = + { + {"pkt_data120", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data121_reg[] = + { + {"pkt_data121", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data122_reg[] = + { + {"pkt_data122", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data123_reg[] = + { + {"pkt_data123", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data124_reg[] = + { + {"pkt_data124", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data125_reg[] = + { + {"pkt_data125", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data126_reg[] = + { + {"pkt_data126", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_pkt_data127_reg[] = + { + {"pkt_data127", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_spr0_reg[] = + { + {"spr0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_spr1_reg[] = + { + {"spr1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_spr2_reg[] = + { + {"spr2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_spr3_reg[] = + { + {"spr3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_spr4_reg[] = + { + {"spr4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_spr5_reg[] = + { + {"spr5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_spr6_reg[] = + { + {"spr6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_spr7_reg[] = + { + {"spr7", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_spr8_reg[] = + { + {"spr8", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_spr9_reg[] = + { + {"spr9", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_spr10_reg[] = + { + {"spr10", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_spr11_reg[] = + { + {"spr11", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_spr12_reg[] = + { + {"spr12", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_spr13_reg[] = + { + {"spr13", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_spr14_reg[] = + { + {"spr14", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_spr15_reg[] = + { + {"spr15", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_spr16_reg[] = + { + {"spr16", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_spr17_reg[] = + { + {"spr17", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_spr18_reg[] = + { + {"spr18", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_spr19_reg[] = + { + {"spr19", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_spr20_reg[] = + { + {"spr20", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_spr21_reg[] = + { + {"spr21", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_spr22_reg[] = + { + {"spr22", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_spr23_reg[] = + { + {"spr23", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_spr24_reg[] = + { + {"spr24", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_spr25_reg[] = + { + {"spr25", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_spr26_reg[] = + { + {"spr26", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_spr27_reg[] = + { + {"spr27", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_spr28_reg[] = + { + {"spr28", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_spr29_reg[] = + { + {"spr29", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_spr30_reg[] = + { + {"spr30", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_spr31_reg[] = + { + {"spr31", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_rsp0_reg[] = + { + {"rsp0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_rsp1_reg[] = + { + {"rsp1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_rsp2_reg[] = + { + {"rsp2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_rsp3_reg[] = + { + {"rsp3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_rsp4_reg[] = + { + {"rsp4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_rsp5_reg[] = + { + {"rsp5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_rsp6_reg[] = + { + {"rsp6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_rsp7_reg[] = + { + {"rsp7", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_rsp8_reg[] = + { + {"rsp8", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_rsp9_reg[] = + { + {"rsp9", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_rsp10_reg[] = + { + {"rsp10", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_rsp11_reg[] = + { + {"rsp11", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_rsp12_reg[] = + { + {"rsp12", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_rsp13_reg[] = + { + {"rsp13", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_rsp14_reg[] = + { + {"rsp14", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_rsp15_reg[] = + { + {"rsp15", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_rsp16_reg[] = + { + {"rsp16", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_rsp17_reg[] = + { + {"rsp17", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_rsp18_reg[] = + { + {"rsp18", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_rsp19_reg[] = + { + {"rsp19", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_rsp20_reg[] = + { + {"rsp20", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_rsp21_reg[] = + { + {"rsp21", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_rsp22_reg[] = + { + {"rsp22", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_rsp23_reg[] = + { + {"rsp23", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_rsp24_reg[] = + { + {"rsp24", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_rsp25_reg[] = + { + {"rsp25", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_rsp26_reg[] = + { + {"rsp26", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_rsp27_reg[] = + { + {"rsp27", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_rsp28_reg[] = + { + {"rsp28", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_rsp29_reg[] = + { + {"rsp29", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_rsp30_reg[] = + { + {"rsp30", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_rsp31_reg[] = + { + {"rsp31", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_key0_reg[] = + { + {"key0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_key1_reg[] = + { + {"key1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_key2_reg[] = + { + {"key2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_key3_reg[] = + { + {"key3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_key4_reg[] = + { + {"key4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_key5_reg[] = + { + {"key5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_key6_reg[] = + { + {"key6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_key7_reg[] = + { + {"key7", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_key8_reg[] = + { + {"key8", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_key9_reg[] = + { + {"key9", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_key10_reg[] = + { + {"key10", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_key11_reg[] = + { + {"key11", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_key12_reg[] = + { + {"key12", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_key13_reg[] = + { + {"key13", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_key14_reg[] = + { + {"key14", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_key15_reg[] = + { + {"key15", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_key16_reg[] = + { + {"key16", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_key17_reg[] = + { + {"key17", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_key18_reg[] = + { + {"key18", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_key19_reg[] = + { + {"key19", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_ppu_flag_reg[] = + { + {"me_num", DPP_FIELD_FLAG_RO, 26, 3, 0x0, 0x0}, + {"thread_num", DPP_FIELD_FLAG_RO, 19, 4, 0x0, 0x0}, + {"flag", DPP_FIELD_FLAG_RO, 11, 12, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_int_1200m_flag_reg[] = + { + {"me7_interrupt_flag", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"me6_interrupt_flag", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"me5_interrupt_flag", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"me4_interrupt_flag", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"me3_interrupt_flag", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"me2_interrupt_flag", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"me1_interrupt_flag", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"me0_interrupt_flag", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_bp_instr_l_reg[] = + { + {"bp_instr_l", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_bp_instr_h_reg[] = + { + {"bp_instr_h", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_bp_addr_reg[] = + { + {"bp_addr", DPP_FIELD_FLAG_RO, 14, 15, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_drr_reg[] = + { + {"drr", DPP_FIELD_FLAG_RO, 4, 5, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_dsr_reg[] = + { + {"dsr", DPP_FIELD_FLAG_RW, 2, 3, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_dbg_rtl_date_reg[] = + { + {"dbg_rtl_date", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_me_continue_reg[] = + { + {"me_continue", DPP_FIELD_FLAG_WO, 7, 8, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_me_step_reg[] = + { + {"me_step", DPP_FIELD_FLAG_WO, 7, 8, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_me_refresh_reg[] = + { + {"me_refresh", DPP_FIELD_FLAG_WO, 7, 8, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_drr_clr_reg[] = + { + {"drr_clr", DPP_FIELD_FLAG_WO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_me_busy_thresold_reg[] = + { + {"me_busy_thresold", DPP_FIELD_FLAG_RW, 15, 16, 0x7fff, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_int_1200m_sta_reg[] = + { + {"me7_interrupt_sta", DPP_FIELD_FLAG_RO, 7, 1, 0x0, 0x0}, + {"me6_interrupt_sta", DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0}, + {"me5_interrupt_sta", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0}, + {"me4_interrupt_sta", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0}, + {"me3_interrupt_sta", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0}, + {"me2_interrupt_sta", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0}, + {"me1_interrupt_sta", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0}, + {"me0_interrupt_sta", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_int_1200m_me_fifo_mask_l_reg[] = + { + {"me_free_pkt_q_overflow_mask", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0}, + {"me_free_pkt_q_underflow_mask", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0}, + {"me_free_thread_q_overflow_mask", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0}, + {"me_free_thread_q_underflow_mask", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0}, + {"me_pkt_in_overflow_mask", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0}, + {"me_pkt_in_underflow_mask", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0}, + {"me_rdy_q_overflow_mask", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0}, + {"me_rdy_q_underflow_mask", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0}, + {"me_pkt_out_q_overflow_mask", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0}, + {"me_pkt_out_q_underflow_mask", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0}, + {"me_continue_q_overflow_mask", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0}, + {"me_continue_q_underflow_mask", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"me_esrh_q_overflow_mask", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0}, + {"me_esrh_q_underflow_mask", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + {"me_isrh_q_overflow_mask", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0}, + {"me_isrh_q_underflow_mask", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"me_cache_miss_q_overflow_mask", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"me_cache_miss_q_underflow_mask", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"me_base_q_u0_overflow_mask", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"me_base_q_u0_underflow_mask", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"me_base_q_u1_overflow_mask", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"me_base_q_u1_underflow_mask", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"me_base_q_u2_overflow_mask", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"me_base_q_u2_underflow_mask", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"me_base_q_u3_overflow_mask", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"me_base_q_u3_underflow_mask", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"me_reg_pc_q_overflow_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"me_reg_pc_q_underflow_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"me_branch_q_overflow_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"me_branch_q_underflow_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"me_pkt_base_q_overflow_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"me_pkt_base_q_underflow_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_int_1200m_me_fifo_mask_h_reg[] = + { + {"me_except_refetch_pc_overflow_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"me_except_refetch_pc_underflow_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_me_fifo_interrupt_flag_l_reg[] = + { + {"me_free_pkt_q_overflow_flag", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"me_free_pkt_q_underflow_flag", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"me_free_thread_q_overflow_flag", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"me_free_thread_q_underflow_flag", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"me_pkt_in_overflow_flag", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"me_pkt_in_underflow_flag", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"me_rdy_q_overflow_flag", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"me_rdy_q_underflow_flag", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"me_pkt_out_q_overflow_flag", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"me_pkt_out_q_underflow_flag", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"me_continue_q_overflow_flag", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"me_continue_q_underflow_flag", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"me_esrh_q_overflow_flag", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"me_esrh_q_underflow_flag", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"me_isrh_q_overflow_flag", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"me_isrh_q_underflow_flag", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"me_cache_miss_q_overflow_flag", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"me_cache_miss_q_underflow_flag", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"me_base_q_u0_overflow_flag", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"me_base_q_u0_underflow_flag", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"me_base_q_u1_overflow_flag", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"me_base_q_u1_underflow_flag", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"me_base_q_u2_overflow_flag", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"me_base_q_u2_underflow_flag", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"me_base_q_u3_overflow_flag", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"me_base_q_u3_underflow_flag", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"me_reg_pc_q_overflow_flag", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"me_reg_pc_q_underflow_flag", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"me_branch_q_overflow_flag", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"me_branch_q_underflow_flag", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"me_pkt_base_q_overflow_flag", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"me_pkt_base_q_underflow_flag", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_me_fifo_interrupt_flag_h_reg[] = + { + {"me_except_refetch_pc_overflow_flag", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"me_except_refetch_pc_underflow_flag", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_me_fifo_interrupt_sta_l_reg[] = + { + {"me_free_pkt_q_overflow_sta", DPP_FIELD_FLAG_RO, 31, 1, 0x0, 0x0}, + {"me_free_pkt_q_underflow_sta", DPP_FIELD_FLAG_RO, 30, 1, 0x0, 0x0}, + {"me_free_thread_q_overflow_sta", DPP_FIELD_FLAG_RO, 29, 1, 0x0, 0x0}, + {"me_free_thread_q_underflow_sta", DPP_FIELD_FLAG_RO, 28, 1, 0x0, 0x0}, + {"me_pkt_in_overflow_sta", DPP_FIELD_FLAG_RO, 27, 1, 0x0, 0x0}, + {"me_pkt_in_underflow_sta", DPP_FIELD_FLAG_RO, 26, 1, 0x0, 0x0}, + {"me_rdy_q_overflow_sta", DPP_FIELD_FLAG_RO, 25, 1, 0x0, 0x0}, + {"me_rdy_q_underflow_sta", DPP_FIELD_FLAG_RO, 24, 1, 0x0, 0x0}, + {"me_pkt_out_q_overflow_sta", DPP_FIELD_FLAG_RO, 23, 1, 0x0, 0x0}, + {"me_pkt_out_q_underflow_sta", DPP_FIELD_FLAG_RO, 22, 1, 0x0, 0x0}, + {"me_continue_q_overflow_sta", DPP_FIELD_FLAG_RO, 21, 1, 0x0, 0x0}, + {"me_continue_q_underflow_sta", DPP_FIELD_FLAG_RO, 20, 1, 0x0, 0x0}, + {"me_esrh_q_overflow_sta", DPP_FIELD_FLAG_RO, 19, 1, 0x0, 0x0}, + {"me_esrh_q_underflow_sta", DPP_FIELD_FLAG_RO, 18, 1, 0x0, 0x0}, + {"me_isrh_q_overflow_sta", DPP_FIELD_FLAG_RO, 17, 1, 0x0, 0x0}, + {"me_isrh_q_underflow_sta", DPP_FIELD_FLAG_RO, 16, 1, 0x0, 0x0}, + {"me_cache_miss_q_overflow_sta", DPP_FIELD_FLAG_RO, 15, 1, 0x0, 0x0}, + {"me_cache_miss_q_underflow_sta", DPP_FIELD_FLAG_RO, 14, 1, 0x0, 0x0}, + {"me_base_q_u0_overflow_sta", DPP_FIELD_FLAG_RO, 13, 1, 0x0, 0x0}, + {"me_base_q_u0_underflow_sta", DPP_FIELD_FLAG_RO, 12, 1, 0x0, 0x0}, + {"me_base_q_u1_overflow_sta", DPP_FIELD_FLAG_RO, 11, 1, 0x0, 0x0}, + {"me_base_q_u1_underflow_sta", DPP_FIELD_FLAG_RO, 10, 1, 0x0, 0x0}, + {"me_base_q_u2_overflow_sta", DPP_FIELD_FLAG_RO, 9, 1, 0x0, 0x0}, + {"me_base_q_u2_underflow_sta", DPP_FIELD_FLAG_RO, 8, 1, 0x0, 0x0}, + {"me_base_q_u3_overflow_sta", DPP_FIELD_FLAG_RO, 7, 1, 0x0, 0x0}, + {"me_base_q_u3_underflow_sta", DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0}, + {"me_reg_pc_q_overflow_sta", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0}, + {"me_reg_pc_q_underflow_sta", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0}, + {"me_branch_q_overflow_sta", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0}, + {"me_branch_q_underflow_sta", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0}, + {"me_pkt_base_q_overflow_sta", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0}, + {"me_pkt_base_q_underflow_sta", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_me_fifo_interrupt_sta_h_reg[] = + { + {"me_except_refetch_pc_overflow_sta", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0}, + {"me_except_refetch_pc_underflow_sta", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_int_1200m_cluster_mex_fifo_mask_l_reg[] = + { + {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u3_overflow_mask", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0}, + {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u3_underflow_mask", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0}, + {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u4_overflow_mask", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0}, + {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u4_underflow_mask", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0}, + {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u5_overflow_mask", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0}, + {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u5_underflow_mask", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0}, + {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u6_overflow_mask", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0}, + {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u6_underflow_mask", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0}, + {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u7_overflow_mask", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0}, + {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u7_underflow_mask", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0}, + {"ppu_ise_rsp_afifo_64x143_wrapper_u0_underflow_mask", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0}, + {"ise_rsp_ram_free_ptr_u0_overflow_mask", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"ise_rsp_ram_free_ptr_u0_underflow_mask", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0}, + {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u0_overflow_mask", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u0_underflow_mask", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0}, + {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u1_overflow_mask", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u1_underflow_mask", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u2_overflow_mask", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u2_underflow_mask", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u3_overflow_mask", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u3_underflow_mask", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u4_overflow_mask", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u4_underflow_mask", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u5_overflow_mask", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u5_underflow_mask", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u6_overflow_mask", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u6_underflow_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u7_overflow_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u7_underflow_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"ppu_sta_rsp_afifo_64x79_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"ppu_sta_rsp_fwft_fifo_128x79_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"ppu_sta_rsp_fwft_fifo_128x79_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_int_1200m_cluster_mex_fifo_mask_h_reg[] = + { + {"ppu_se_key_afifo_32x54_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + {"ppu_se_key_afifo_32x665_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0}, + {"ppu_sta_key_afifo_32x110_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"ppu_cluster_mf_in_afifo_32x2048_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"ppu_pbu_mcode_pf_rsp_fifo_32x13_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"ppu_pbu_mcode_pf_rsp_fifo_32x13_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"ppu_coprocess_rsp_fifo_32x77_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"ppu_coprocess_rsp_fifo_32x77_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"ppu_coprocess_rsp_fwft_fifo_128x78_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"ppu_coprocess_rsp_fwft_fifo_128x78_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"ppu_ese_rsp_afifo_64x271_wrapper_u0_underflow_mask", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"ese_rsp_ram_free_ptr_u0_overflow_mask", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"ese_rsp_ram_free_ptr_u0_underflow_mask", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u0_overflow_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u0_underflow_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u1_overflow_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u1_underflow_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u2_overflow_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u2_underflow_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_int_1200m_cluster_mex_fifo_flag_l_reg[] = + { + {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u3_overflow_flag", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u3_underflow_flag", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u4_overflow_flag", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u4_underflow_flag", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u5_overflow_flag", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u5_underflow_flag", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u6_overflow_flag", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u6_underflow_flag", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u7_overflow_flag", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u7_underflow_flag", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"ppu_ise_rsp_afifo_64x143_wrapper_u0_underflow_flag", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"ise_rsp_ram_free_ptr_u0_overflow_flag", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"ise_rsp_ram_free_ptr_u0_underflow_flag", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u0_overflow_flag", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u0_underflow_flag", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u1_overflow_flag", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u1_underflow_flag", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u2_overflow_flag", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u2_underflow_flag", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u3_overflow_flag", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u3_underflow_flag", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u4_overflow_flag", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u4_underflow_flag", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u5_overflow_flag", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u5_underflow_flag", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u6_overflow_flag", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u6_underflow_flag", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u7_overflow_flag", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u7_underflow_flag", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"ppu_sta_rsp_afifo_64x79_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"ppu_sta_rsp_fwft_fifo_128x79_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"ppu_sta_rsp_fwft_fifo_128x79_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_int_1200m_cluster_mex_fifo_flag_h_reg[] = + { + {"ppu_se_key_afifo_32x54_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"ppu_se_key_afifo_32x665_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"ppu_sta_key_afifo_32x110_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"ppu_cluster_mf_in_afifo_32x2048_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"ppu_pbu_mcode_pf_rsp_fifo_32x13_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"ppu_pbu_mcode_pf_rsp_fifo_32x13_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"ppu_coprocess_rsp_fifo_32x77_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"ppu_coprocess_rsp_fifo_32x77_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"ppu_coprocess_rsp_fwft_fifo_128x78_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"ppu_coprocess_rsp_fwft_fifo_128x78_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"ppu_ese_rsp_afifo_64x271_wrapper_u0_underflow_flag", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"ese_rsp_ram_free_ptr_u0_overflow_flag", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"ese_rsp_ram_free_ptr_u0_underflow_flag", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u0_overflow_flag", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u0_underflow_flag", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u1_overflow_flag", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u1_underflow_flag", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u2_overflow_flag", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u2_underflow_flag", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_int_1200m_cluster_mex_fifo_stat_l_reg[] = + { + {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u3_overflow_stat", DPP_FIELD_FLAG_RO, 31, 1, 0x0, 0x0}, + {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u3_underflow_stat", DPP_FIELD_FLAG_RO, 30, 1, 0x0, 0x0}, + {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u4_overflow_stat", DPP_FIELD_FLAG_RO, 29, 1, 0x0, 0x0}, + {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u4_underflow_stat", DPP_FIELD_FLAG_RO, 28, 1, 0x0, 0x0}, + {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u5_overflow_stat", DPP_FIELD_FLAG_RO, 27, 1, 0x0, 0x0}, + {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u5_underflow_stat", DPP_FIELD_FLAG_RO, 26, 1, 0x0, 0x0}, + {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u6_overflow_stat", DPP_FIELD_FLAG_RO, 25, 1, 0x0, 0x0}, + {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u6_underflow_stat", DPP_FIELD_FLAG_RO, 24, 1, 0x0, 0x0}, + {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u7_overflow_stat", DPP_FIELD_FLAG_RO, 23, 1, 0x0, 0x0}, + {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u7_underflow_stat", DPP_FIELD_FLAG_RO, 22, 1, 0x0, 0x0}, + {"ppu_ise_rsp_afifo_64x143_wrapper_u0_underflow_stat", DPP_FIELD_FLAG_RO, 21, 1, 0x0, 0x0}, + {"ise_rsp_ram_free_ptr_u0_overflow_stat", DPP_FIELD_FLAG_RO, 20, 1, 0x0, 0x0}, + {"ise_rsp_ram_free_ptr_u0_underflow_stat", DPP_FIELD_FLAG_RO, 19, 1, 0x0, 0x0}, + {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u0_overflow_stat", DPP_FIELD_FLAG_RO, 18, 1, 0x0, 0x0}, + {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u0_underflow_stat", DPP_FIELD_FLAG_RO, 17, 1, 0x0, 0x0}, + {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u1_overflow_stat", DPP_FIELD_FLAG_RO, 16, 1, 0x0, 0x0}, + {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u1_underflow_stat", DPP_FIELD_FLAG_RO, 15, 1, 0x0, 0x0}, + {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u2_overflow_stat", DPP_FIELD_FLAG_RO, 14, 1, 0x0, 0x0}, + {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u2_underflow_stat", DPP_FIELD_FLAG_RO, 13, 1, 0x0, 0x0}, + {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u3_overflow_stat", DPP_FIELD_FLAG_RO, 12, 1, 0x0, 0x0}, + {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u3_underflow_stat", DPP_FIELD_FLAG_RO, 11, 1, 0x0, 0x0}, + {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u4_overflow_stat", DPP_FIELD_FLAG_RO, 10, 1, 0x0, 0x0}, + {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u4_underflow_stat", DPP_FIELD_FLAG_RO, 9, 1, 0x0, 0x0}, + {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u5_overflow_stat", DPP_FIELD_FLAG_RO, 8, 1, 0x0, 0x0}, + {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u5_underflow_stat", DPP_FIELD_FLAG_RO, 7, 1, 0x0, 0x0}, + {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u6_overflow_stat", DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0}, + {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u6_underflow_stat", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0}, + {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u7_overflow_stat", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0}, + {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u7_underflow_stat", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0}, + {"ppu_sta_rsp_afifo_64x79_wrapper_underflow_stat", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0}, + {"ppu_sta_rsp_fwft_fifo_128x79_wrapper_overflow_stat", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0}, + {"ppu_sta_rsp_fwft_fifo_128x79_wrapper_underflow_stat", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_int_1200m_cluster_mex_fifo_stat_h_reg[] = + { + {"ppu_se_key_afifo_32x54_wrapper_overflow_stat", DPP_FIELD_FLAG_RO, 18, 1, 0x0, 0x0}, + {"ppu_se_key_afifo_32x665_wrapper_overflow_stat", DPP_FIELD_FLAG_RO, 17, 1, 0x0, 0x0}, + {"ppu_sta_key_afifo_32x110_wrapper_overflow_stat", DPP_FIELD_FLAG_RO, 16, 1, 0x0, 0x0}, + {"ppu_cluster_mf_in_afifo_32x2048_wrapper_underflow_stat", DPP_FIELD_FLAG_RO, 15, 1, 0x0, 0x0}, + {"ppu_pbu_mcode_pf_rsp_fifo_32x13_wrapper_overflow_stat", DPP_FIELD_FLAG_RO, 14, 1, 0x0, 0x0}, + {"ppu_pbu_mcode_pf_rsp_fifo_32x13_wrapper_underflow_stat", DPP_FIELD_FLAG_RO, 13, 1, 0x0, 0x0}, + {"ppu_coprocess_rsp_fifo_32x77_wrapper_overflow_stat", DPP_FIELD_FLAG_RO, 12, 1, 0x0, 0x0}, + {"ppu_coprocess_rsp_fifo_32x77_wrapper_underflow_stat", DPP_FIELD_FLAG_RO, 11, 1, 0x0, 0x0}, + {"ppu_coprocess_rsp_fwft_fifo_128x78_wrapper_overflow_stat", DPP_FIELD_FLAG_RO, 10, 1, 0x0, 0x0}, + {"ppu_coprocess_rsp_fwft_fifo_128x78_wrapper_underflow_stat", DPP_FIELD_FLAG_RO, 9, 1, 0x0, 0x0}, + {"ppu_ese_rsp_afifo_64x271_wrapper_u0_underflow_stat", DPP_FIELD_FLAG_RO, 8, 1, 0x0, 0x0}, + {"ese_rsp_ram_free_ptr_u0_overflow_stat", DPP_FIELD_FLAG_RO, 7, 1, 0x0, 0x0}, + {"ese_rsp_ram_free_ptr_u0_underflow_stat", DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0}, + {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u0_overflow_stat", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0}, + {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u0_underflow_stat", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0}, + {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u1_overflow_stat", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0}, + {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u1_underflow_stat", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0}, + {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u2_overflow_stat", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0}, + {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u2_underflow_stat", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_ppu_statics_wb_exception_cfg_reg[] = + { + {"csr_statics_wb_exception_code5", DPP_FIELD_FLAG_RW, 22, 3, 0x7, 0x0}, + {"csr_statics_wb_exception_code4", DPP_FIELD_FLAG_RW, 18, 3, 0x6, 0x0}, + {"csr_statics_wb_exception_code3", DPP_FIELD_FLAG_RW, 14, 3, 0x5, 0x0}, + {"csr_statics_wb_exception_code2", DPP_FIELD_FLAG_RW, 10, 3, 0x4, 0x0}, + {"csr_statics_wb_exception_code1", DPP_FIELD_FLAG_RW, 6, 3, 0x3, 0x0}, + {"csr_statics_wb_exception_code0", DPP_FIELD_FLAG_RW, 2, 3, 0x2, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_thread_switch_en_reg[] = + { + {"thread_switch_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_is_me_not_idle_reg[] = + { + {"me7_is_not_idle", DPP_FIELD_FLAG_RO, 7, 1, 0x0, 0x0}, + {"me6_is_not_idle", DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0}, + {"me5_is_not_idle", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0}, + {"me4_is_not_idle", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0}, + {"me3_is_not_idle", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0}, + {"me2_is_not_idle", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0}, + {"me1_is_not_idle", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0}, + {"me0_is_not_idle", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_ppu_cluster_mf_in_afifo_prog_empty_assert_cfg_reg[] = + { + {"ppu_cluster_mf_in_afifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_ppu_cluster_mf_in_afifo_prog_empty_negate_cfg_reg[] = + { + {"ppu_cluster_mf_in_afifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_ese_rsp_afifo_prog_empty_assert_cfg_reg[] = + { + {"ese_rsp_afifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0xe, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_ese_rsp_afifo_prog_empty_negate_cfg_reg[] = + { + {"ese_rsp_afifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0xe, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_ise_rsp_afifo_prog_empty_assert_cfg_reg[] = + { + {"ise_rsp_afifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x20, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_ise_rsp_afifo_prog_empty_negate_cfg_reg[] = + { + {"ise_rsp_afifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x20, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_ppu_rsp_ptr_fwft_fifo0_prog_full_assert_cfg_reg[] = + { + {"ppu_rsp_ptr_fwft_fifo0_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x78, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_ppu_rsp_ptr_fwft_fifo0_prog_full_negate_cfg_reg[] = + { + {"ppu_rsp_ptr_fwft_fifo0_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x78, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_ppu_rsp_ptr_fwft_fifo0_prog_empty_assert_cfg_reg[] = + { + {"ppu_rsp_ptr_fwft_fifo0_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x6, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_ppu_rsp_ptr_fwft_fifo0_prog_empty_negate_cfg_reg[] = + { + {"ppu_rsp_ptr_fwft_fifo0_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x6, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_ppu_rsp_ptr_fwft_fifo1_prog_full_assert_cfg_reg[] = + { + {"ppu_rsp_ptr_fwft_fifo1_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x78, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_ppu_rsp_ptr_fwft_fifo1_prog_full_negate_cfg_reg[] = + { + {"ppu_rsp_ptr_fwft_fifo1_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x78, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_ppu_rsp_ptr_fwft_fifo1_prog_empty_assert_cfg_reg[] = + { + {"ppu_rsp_ptr_fwft_fifo1_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_ppu_rsp_ptr_fwft_fifo1_prog_empty_negate_cfg_reg[] = + { + {"ppu_rsp_ptr_fwft_fifo1_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_sta_rsp_afifo_prog_empty_assert_cfg_reg[] = + { + {"sta_rsp_afifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_sta_rsp_afifo_prog_empty_negate_cfg_reg[] = + { + {"sta_rsp_afifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_ppu_sta_rsp_fwft_fifo_prog_full_assert_cfg_reg[] = + { + {"ppu_sta_rsp_fwft_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x78, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_ppu_sta_rsp_fwft_fifo_prog_full_negate_cfg_reg[] = + { + {"ppu_sta_rsp_fwft_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x78, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_ppu_sta_rsp_fwft_fifo_prog_empty_assert_cfg_reg[] = + { + {"ppu_sta_rsp_fwft_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_ppu_sta_rsp_fwft_fifo_prog_empty_negate_cfg_reg[] = + { + {"ppu_sta_rsp_fwft_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_cop_rsp_fifo_prog_full_assert_cfg_reg[] = + { + {"cop_rsp_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x17, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_cop_rsp_fifo_prog_full_negate_cfg_reg[] = + { + {"cop_rsp_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x17, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_cop_rsp_fifo_prog_empty_assert_cfg_reg[] = + { + {"cop_rsp_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_cop_rsp_fifo_prog_empty_negate_cfg_reg[] = + { + {"cop_rsp_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_mcode_pf_rsp_fifo_prog_full_assert_cfg_reg[] = + { + {"mcode_pf_rsp_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x18, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_mcode_pf_rsp_fifo_prog_full_negate_cfg_reg[] = + { + {"mcode_pf_rsp_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x18, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_mcode_pf_rsp_fifo_prog_empty_assert_cfg_reg[] = + { + {"mcode_pf_rsp_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_mcode_pf_rsp_fifo_prog_empty_negate_cfg_reg[] = + { + {"mcode_pf_rsp_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_ppu_cop_rsp_fwft_fifo_prog_full_assert_cfg_reg[] = + { + {"ppu_cop_rsp_fwft_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x78, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_ppu_cop_rsp_fwft_fifo_prog_full_negate_cfg_reg[] = + { + {"ppu_cop_rsp_fwft_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x78, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_ppu_cop_rsp_fwft_fifo_prog_empty_assert_cfg_reg[] = + { + {"ppu_cop_rsp_fwft_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_ppu_cop_rsp_fwft_fifo_prog_empty_negate_cfg_reg[] = + { + {"ppu_cop_rsp_fwft_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_ppu_ise_key_afifo_prog_full_assert_cfg_reg[] = + { + {"ppu_ise_key_afifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x14, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_ppu_ise_key_afifo_prog_full_negate_cfg_reg[] = + { + {"ppu_ise_key_afifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x14, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_ppu_ese_key_afifo_prog_full_assert_cfg_reg[] = + { + {"ppu_ese_key_afifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x14, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_ppu_ese_key_afifo_prog_full_negate_cfg_reg[] = + { + {"ppu_ese_key_afifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x14, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_ppu_sta_key_afifo_prog_full_assert_cfg_reg[] = + { + {"ppu_sta_key_afifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x14, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_ppu_sta_key_afifo_prog_full_negate_cfg_reg[] = + { + {"ppu_sta_key_afifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x14, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_int_600m_cluster_mex_fifo_mask_reg[] = + { + {"ppu_se_key_afifo_32x54_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"ppu_se_key_afifo_32x665_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"ppu_sta_key_afifo_32x110_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"ppu_cluster_mf_in_afifo_32x2048_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"ppu_ese_rsp_afifo_64x271_wrapper_u0_overflow_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"ppu_ise_rsp_afifo_64x143_wrapper_u0_overflow_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"ppu_sta_rsp_afifo_64x79_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_cluster_mex_fifo_600m_interrupt_flag_reg[] = + { + {"ppu_se_key_afifo_32x54_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"ppu_se_key_afifo_32x665_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"ppu_sta_key_afifo_32x110_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"ppu_cluster_mf_in_afifo_32x2048_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"ppu_ese_rsp_afifo_64x271_wrapper_u0_overflow_flag", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"ppu_ise_rsp_afifo_64x143_wrapper_u0_overflow_flag", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"ppu_sta_rsp_afifo_64x79_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_cluster_mex_fifo_600m_interrupt_sta_reg[] = + { + {"ppu_se_key_afifo_32x54_wrapper_underflow_sta", DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0}, + {"ppu_se_key_afifo_32x665_wrapper_underflow_sta", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0}, + {"ppu_sta_key_afifo_32x110_wrapper_underflow_sta", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0}, + {"ppu_cluster_mf_in_afifo_32x2048_wrapper_overflow_sta", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0}, + {"ppu_ese_rsp_afifo_64x271_wrapper_u0_overflow_sta", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0}, + {"ppu_ise_rsp_afifo_64x143_wrapper_u0_overflow_sta", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0}, + {"ppu_sta_rsp_afifo_64x79_wrapper_overflow_sta", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_mex_cnt_cfg_reg[] = + { + {"csr_count_overflow_mode", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"csr_count_rd_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_int_600m_cluster_mex_ram_ecc_error_interrupt_mask_reg[] = + { + {"ppu_sta_key_ram_1r1w_32x110_ecc_double_err_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"ppu_se_key_afifo_32x665_ecc_double_err_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"ppu_se_key_afifo_32x54_ecc_double_err_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"ppu_sta_key_ram_1r1w_32x110_ecc_single_err_flag", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"ppu_se_key_afifo_32x665_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"ppu_se_key_afifo_32x54_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_cluster_mex_ram_600m_ecc_error_interrupt_flag_reg[] = + { + {"ppu_sta_key_ram_1r1w_32x110_ecc_double_err_flag", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"ppu_se_key_afifo_32x665_ecc_double_err_flag", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"ppu_se_key_afifo_32x54_ecc_double_err_flag", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"ppu_sta_key_ram_1r1w_32x110_ecc_single_err_flag", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"ppu_se_key_afifo_32x665_ecc_single_err_flag", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"ppu_se_key_afifo_32x54_ecc_single_err_flag", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_cluster_mex_ram_600m_ecc_error_interrupt_sta_reg[] = + { + {"ppu_sta_key_ram_1r1w_32x110_ecc_double_err_stat", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0}, + {"ppu_se_key_afifo_32x665_ecc_double_err_stat", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0}, + {"ppu_se_key_afifo_32x54_ecc_double_err_stat", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0}, + {"ppu_sta_key_ram_1r1w_32x110_ecc_single_err_stat", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0}, + {"ppu_se_key_afifo_32x665_ecc_single_err_stat", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0}, + {"ppu_se_key_afifo_32x54_ecc_single_err_stat", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_ppu_cluster_mf_in_afifo_prog_full_assert_cfg_reg[] = + { + {"ppu_cluster_mf_in_afifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x10, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_ppu_cluster_mf_in_afifo_prog_full_negate_cfg_reg[] = + { + {"ppu_cluster_mf_in_afifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x10, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_ese_rsp_afifo_prog_full_assert_cfg_reg[] = + { + {"ese_rsp_afifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x2c, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_ese_rsp_afifo_prog_full_negate_cfg_reg[] = + { + {"ese_rsp_afifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x2c, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_ise_rsp_afifo_prog_full_assert_cfg_reg[] = + { + {"ise_rsp_afifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x29, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_ise_rsp_afifo_prog_full_negate_cfg_reg[] = + { + {"ise_rsp_afifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x29, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_sta_rsp_afifo_prog_full_assert_cfg_reg[] = + { + {"sta_rsp_afifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x27, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_sta_rsp_afifo_prog_full_negate_cfg_reg[] = + { + {"sta_rsp_afifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x27, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_ppu_ise_key_afifo_prog_empty_assert_cfg_reg[] = + { + {"ppu_ise_key_afifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_ppu_ise_key_afifo_prog_empty_negate_cfg_reg[] = + { + {"ppu_ise_key_afifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_ppu_ese_key_afifo_prog_empty_assert_cfg_reg[] = + { + {"ppu_ese_key_afifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_ppu_ese_key_afifo_prog_empty_negate_cfg_reg[] = + { + {"ppu_ese_key_afifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_ppu_sta_key_afifo_prog_empty_assert_cfg_reg[] = + { + {"ppu_sta_key_afifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_ppu_sta_key_afifo_prog_empty_negate_cfg_reg[] = + { + {"ppu_sta_key_afifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_ppu_cluster_mf_vld_cnt_h_reg[] = + { + {"ppu_cluster_mf_vld_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_ppu_cluster_mf_vld_cnt_l_reg[] = + { + {"ppu_cluster_mf_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_cluster_ise_key_out_vld_cnt_reg[] = + { + {"cluster_ise_key_out_vld_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_ise_cluster_rsp_in_vld_cnt_reg[] = + { + {"ise_cluster_rsp_in_vld_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_cluster_ese_key_out_vld_cnt_reg[] = + { + {"cluster_ese_key_out_vld_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_ese_cluster_rsp_in_vld_cnt_reg[] = + { + {"ese_cluster_rsp_in_vld_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_cluster_stat_cmd_vld_cnt_reg[] = + { + {"cluster_stat_cmd_vld_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_stat_cluster_rsp_vld_cnt_reg[] = + { + {"stat_cluster_rsp_vld_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_mex_debug_key_vld_cnt_reg[] = + { + {"mex_debug_key_vld_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_ise_cluster_key_fc_cnt_reg[] = + { + {"ise_cluster_key_fc_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_ese_cluster_key_fc_cnt_reg[] = + { + {"ese_cluster_key_fc_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_cluster_ise_rsp_fc_cnt_reg[] = + { + {"cluster_ise_rsp_fc_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_cluster_ese_rsp_fc_cnt_reg[] = + { + {"cluster_ese_rsp_fc_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_stat_cluster_cmd_fc_cnt_reg[] = + { + {"stat_cluster_cmd_fc_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_cluster_stat_rsp_fc_cnt_reg[] = + { + {"cluster_stat_rsp_fc_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_cluster_ppu_mf_vld_cnt_l_reg[] = + { + {"cluster_ppu_mf_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_cluster_ppu_mf_vld_cnt_h_reg[] = + { + {"cluster_ppu_mf_vld_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_cluster_cop_key_vld_cnt_l_reg[] = + { + {"cluster_cop_key_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_cluster_cop_key_vld_cnt_h_reg[] = + { + {"cluster_cop_key_vld_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_cop_cluster_rsp_vld_cnt_l_reg[] = + { + {"cop_cluster_rsp_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_cop_cluster_rsp_vld_cnt_h_reg[] = + { + {"cop_cluster_rsp_vld_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_mex_me_pkt_in_sop_cnt_l_reg[] = + { + {"mex_me_pkt_in_sop_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_mex_me_pkt_in_sop_cnt_h_reg[] = + { + {"mex_me_pkt_in_sop_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_mex_me_pkt_in_eop_cnt_l_reg[] = + { + {"mex_me_pkt_in_eop_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_mex_me_pkt_in_eop_cnt_h_reg[] = + { + {"mex_me_pkt_in_eop_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_mex_me_pkt_in_vld_cnt_l_reg[] = + { + {"mex_me_pkt_in_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_mex_me_pkt_in_vld_cnt_h_reg[] = + { + {"mex_me_pkt_in_vld_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_me_mex_pkt_out_sop_cnt_l_reg[] = + { + {"me_mex_pkt_out_sop_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_me_mex_pkt_out_sop_cnt_h_reg[] = + { + {"me_mex_pkt_out_sop_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_me_mex_pkt_out_eop_cnt_l_reg[] = + { + {"me_mex_pkt_out_eop_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_me_mex_pkt_out_eop_cnt_h_reg[] = + { + {"me_mex_pkt_out_eop_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_me_mex_pkt_out_vld_cnt_l_reg[] = + { + {"me_mex_pkt_out_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_me_mex_pkt_out_vld_cnt_h_reg[] = + { + {"me_mex_pkt_out_vld_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_me_mex_i_key_out_sop_cnt_l_reg[] = + { + {"me_mex_i_key_out_sop_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_me_mex_i_key_out_sop_cnt_h_reg[] = + { + {"me_mex_i_key_out_sop_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_me_mex_i_key_out_eop_cnt_l_reg[] = + { + {"me_mex_i_key_out_eop_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_me_mex_i_key_out_eop_cnt_h_reg[] = + { + {"me_mex_i_key_out_eop_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_me_mex_i_key_out_vld_cnt_l_reg[] = + { + {"me_mex_i_key_out_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_me_mex_i_key_out_vld_cnt_h_reg[] = + { + {"me_mex_i_key_out_vld_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_me_mex_e_key_out_sop_cnt_l_reg[] = + { + {"me_mex_e_key_out_sop_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_me_mex_e_key_out_sop_cnt_h_reg[] = + { + {"me_mex_e_key_out_sop_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_me_mex_e_key_out_eop_cnt_l_reg[] = + { + {"me_mex_e_key_out_eop_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_me_mex_e_key_out_eop_cnt_h_reg[] = + { + {"me_mex_e_key_out_eop_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_me_mex_e_key_out_vld_cnt_l_reg[] = + { + {"me_mex_e_key_out_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_me_mex_e_key_out_vld_cnt_h_reg[] = + { + {"me_mex_e_key_out_vld_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_me_mex_demux_ise_key_vld_cnt_l_reg[] = + { + {"me_mex_demux_ise_key_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_me_mex_demux_ise_key_vld_cnt_h_reg[] = + { + {"me_mex_demux_ise_key_vld_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_me_mex_demux_ese_key_vld_cnt_l_reg[] = + { + {"me_mex_demux_ese_key_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_me_mex_demux_ese_key_vld_cnt_h_reg[] = + { + {"me_mex_demux_ese_key_vld_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_me_mex_demux_sta_key_vld_cnt_l_reg[] = + { + {"me_mex_demux_sta_key_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_me_mex_demux_sta_key_vld_cnt_h_reg[] = + { + {"me_mex_demux_sta_key_vld_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_me_mex_demux_cop_key_vld_cnt_l_reg[] = + { + {"me_mex_demux_cop_key_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_me_mex_demux_cop_key_vld_cnt_h_reg[] = + { + {"me_mex_demux_cop_key_vld_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_mex_me_demux_ise_rsp_vld_cnt_l_reg[] = + { + {"mex_me_demux_ise_rsp_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_mex_me_demux_ise_rsp_vld_cnt_h_reg[] = + { + {"mex_me_demux_ise_rsp_vld_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_mex_me_demux_ese_rsp_vld_cnt_l_reg[] = + { + {"mex_me_demux_ese_rsp_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_mex_me_demux_ese_rsp_vld_cnt_h_reg[] = + { + {"mex_me_demux_ese_rsp_vld_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_mex_me_demux_sta_rsp_vld_cnt_l_reg[] = + { + {"mex_me_demux_sta_rsp_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_mex_me_demux_sta_rsp_vld_cnt_h_reg[] = + { + {"mex_me_demux_sta_rsp_vld_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_mex_me_demux_cop_rsp_vld_cnt_l_reg[] = + { + {"mex_me_demux_cop_rsp_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_mex_me_demux_cop_rsp_vld_cnt_h_reg[] = + { + {"mex_me_demux_cop_rsp_vld_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_me_exception_code0_cnt_l_reg[] = + { + {"me_exception_code0_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_me_exception_code0_cnt_h_reg[] = + { + {"me_exception_code0_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_me_exception_code1_cnt_l_reg[] = + { + {"me_exception_code1_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_me_exception_code1_cnt_h_reg[] = + { + {"me_exception_code1_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_me_exception_code2_cnt_l_reg[] = + { + {"me_exception_code2_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_me_exception_code2_cnt_h_reg[] = + { + {"me_exception_code2_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_me_exception_code3_cnt_l_reg[] = + { + {"me_exception_code3_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_me_exception_code3_cnt_h_reg[] = + { + {"me_exception_code3_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_me_exception_code4_cnt_l_reg[] = + { + {"me_exception_code4_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_me_exception_code4_cnt_h_reg[] = + { + {"me_exception_code4_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_me_exception_code5_cnt_l_reg[] = + { + {"me_exception_code5_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ppu_cluster_me_exception_code5_cnt_h_reg[] = + { + {"me_exception_code5_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_ppu_soft_rst_reg[] = + { + {"ppu_soft_rst", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_ept_flag_reg[] = + { + {"ept_flag", DPP_FIELD_FLAG_RO, 5, 6, 0x3f, 0x0}, + }; +DPP_FIELD_T g_se_cfg_ddr_key_lk0_3_reg[] = + { + {"ddr_key_lk0_3", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_ddr_key_lk0_2_reg[] = + { + {"ddr_key_lk0_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_ddr_key_lk0_1_reg[] = + { + {"ddr_key_lk0_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_ddr_key_lk0_0_reg[] = + { + {"ddr_key_lk0_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_ddr_key_lk1_3_reg[] = + { + {"ddr_key_lk1_3", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_ddr_key_lk1_2_reg[] = + { + {"ddr_key_lk1_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_ddr_key_lk1_1_reg[] = + { + {"ddr_key_lk1_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_ddr_key_lk1_0_reg[] = + { + {"ddr_key_lk1_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk0_18_reg[] = + { + {"hash_key_lk0_18", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk0_17_reg[] = + { + {"hash_key_lk0_17", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk0_16_reg[] = + { + {"hash_key_lk0_16", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk0_15_reg[] = + { + {"hash_key_lk0_15", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk0_14_reg[] = + { + {"hash_key_lk0_14", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk0_13_reg[] = + { + {"hash_key_lk0_13", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk0_12_reg[] = + { + {"hash_key_lk0_12", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk0_11_reg[] = + { + {"hash_key_lk0_11", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk0_10_reg[] = + { + {"hash_key_lk0_10", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk0_9_reg[] = + { + {"hash_key_lk0_9", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk0_8_reg[] = + { + {"hash_key_lk0_8", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk0_7_reg[] = + { + {"hash_key_lk0_7", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk0_6_reg[] = + { + {"hash_key_lk0_6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk0_5_reg[] = + { + {"hash_key_lk0_5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk0_4_reg[] = + { + {"hash_key_lk0_4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk0_3_reg[] = + { + {"hash_key_lk0_3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk0_2_reg[] = + { + {"hash_key_lk0_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk0_1_reg[] = + { + {"hash_key_lk0_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk0_0_reg[] = + { + {"hash_key_lk0_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk1_18_reg[] = + { + {"hash_key_lk1_18", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk1_17_reg[] = + { + {"hash_key_lk1_17", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk1_16_reg[] = + { + {"hash_key_lk1_16", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk1_15_reg[] = + { + {"hash_key_lk1_15", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk1_14_reg[] = + { + {"hash_key_lk1_14", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk1_13_reg[] = + { + {"hash_key_lk1_13", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk1_12_reg[] = + { + {"hash_key_lk1_12", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk1_11_reg[] = + { + {"hash_key_lk1_11", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk1_10_reg[] = + { + {"hash_key_lk1_10", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk1_9_reg[] = + { + {"hash_key_lk1_9", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk1_8_reg[] = + { + {"hash_key_lk1_8", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk1_7_reg[] = + { + {"hash_key_lk1_7", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk1_6_reg[] = + { + {"hash_key_lk1_6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk1_5_reg[] = + { + {"hash_key_lk1_5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk1_4_reg[] = + { + {"hash_key_lk1_4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk1_3_reg[] = + { + {"hash_key_lk1_3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk1_2_reg[] = + { + {"hash_key_lk1_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk1_1_reg[] = + { + {"hash_key_lk1_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk1_0_reg[] = + { + {"hash_key_lk1_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk2_18_reg[] = + { + {"hash_key_lk2_18", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk2_17_reg[] = + { + {"hash_key_lk2_17", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk2_16_reg[] = + { + {"hash_key_lk2_16", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk2_15_reg[] = + { + {"hash_key_lk2_15", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk2_14_reg[] = + { + {"hash_key_lk2_14", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk2_13_reg[] = + { + {"hash_key_lk2_13", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk2_12_reg[] = + { + {"hash_key_lk2_12", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk2_11_reg[] = + { + {"hash_key_lk2_11", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk2_10_reg[] = + { + {"hash_key_lk2_10", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk2_9_reg[] = + { + {"hash_key_lk2_9", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk2_8_reg[] = + { + {"hash_key_lk2_8", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk2_7_reg[] = + { + {"hash_key_lk2_7", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk2_6_reg[] = + { + {"hash_key_lk2_6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk2_5_reg[] = + { + {"hash_key_lk2_5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk2_4_reg[] = + { + {"hash_key_lk2_4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk2_3_reg[] = + { + {"hash_key_lk2_3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk2_2_reg[] = + { + {"hash_key_lk2_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk2_1_reg[] = + { + {"hash_key_lk2_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk2_0_reg[] = + { + {"hash_key_lk2_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk3_18_reg[] = + { + {"hash_key_lk3_18", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk3_17_reg[] = + { + {"hash_key_lk3_17", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk3_16_reg[] = + { + {"hash_key_lk3_16", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk3_15_reg[] = + { + {"hash_key_lk3_15", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk3_14_reg[] = + { + {"hash_key_lk3_14", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk3_13_reg[] = + { + {"hash_key_lk3_13", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk3_12_reg[] = + { + {"hash_key_lk3_12", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk3_11_reg[] = + { + {"hash_key_lk3_11", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk3_10_reg[] = + { + {"hash_key_lk3_10", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk3_9_reg[] = + { + {"hash_key_lk3_9", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk3_8_reg[] = + { + {"hash_key_lk3_8", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk3_7_reg[] = + { + {"hash_key_lk3_7", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk3_6_reg[] = + { + {"hash_key_lk3_6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk3_5_reg[] = + { + {"hash_key_lk3_5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk3_4_reg[] = + { + {"hash_key_lk3_4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk3_3_reg[] = + { + {"hash_key_lk3_3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk3_2_reg[] = + { + {"hash_key_lk3_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk3_1_reg[] = + { + {"hash_key_lk3_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_hash_key_lk3_0_reg[] = + { + {"hash_key_lk3_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_lpm_key_lk0_6_reg[] = + { + {"lpm_key_lk0_6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_lpm_key_lk0_5_reg[] = + { + {"lpm_key_lk0_5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_lpm_key_lk0_4_reg[] = + { + {"lpm_key_lk0_4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_lpm_key_lk0_3_reg[] = + { + {"lpm_key_lk0_3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_lpm_key_lk0_2_reg[] = + { + {"lpm_key_lk0_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_lpm_key_lk0_1_reg[] = + { + {"lpm_key_lk0_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_lpm_key_lk0_0_reg[] = + { + {"lpm_key_lk0_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_lpm_key_lk1_6_reg[] = + { + {"lpm_key_lk1_6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_lpm_key_lk1_5_reg[] = + { + {"lpm_key_lk1_5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_lpm_key_lk1_4_reg[] = + { + {"lpm_key_lk1_4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_lpm_key_lk1_3_reg[] = + { + {"lpm_key_lk1_3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_lpm_key_lk1_2_reg[] = + { + {"lpm_key_lk1_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_lpm_key_lk1_1_reg[] = + { + {"lpm_key_lk1_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_lpm_key_lk1_0_reg[] = + { + {"lpm_key_lk1_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_lpm_key_lk2_6_reg[] = + { + {"lpm_key_lk2_6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_lpm_key_lk2_5_reg[] = + { + {"lpm_key_lk2_5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_lpm_key_lk2_4_reg[] = + { + {"lpm_key_lk2_4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_lpm_key_lk2_3_reg[] = + { + {"lpm_key_lk2_3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_lpm_key_lk2_2_reg[] = + { + {"lpm_key_lk2_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_lpm_key_lk2_1_reg[] = + { + {"lpm_key_lk2_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_lpm_key_lk2_0_reg[] = + { + {"lpm_key_lk2_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_lpm_key_lk3_6_reg[] = + { + {"lpm_key_lk3_6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_lpm_key_lk3_5_reg[] = + { + {"lpm_key_lk3_5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_lpm_key_lk3_4_reg[] = + { + {"lpm_key_lk3_4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_lpm_key_lk3_3_reg[] = + { + {"lpm_key_lk3_3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_lpm_key_lk3_2_reg[] = + { + {"lpm_key_lk3_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_lpm_key_lk3_1_reg[] = + { + {"lpm_key_lk3_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_lpm_key_lk3_0_reg[] = + { + {"lpm_key_lk3_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk0_22_reg[] = + { + {"etcam_key_lk0_22", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk0_21_reg[] = + { + {"etcam_key_lk0_21", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk0_20_reg[] = + { + {"etcam_key_lk0_20", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk0_19_reg[] = + { + {"etcam_key_lk0_19", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk0_18_reg[] = + { + {"etcam_key_lk0_18", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk0_17_reg[] = + { + {"etcam_key_lk0_17", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk0_16_reg[] = + { + {"etcam_key_lk0_16", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk0_15_reg[] = + { + {"etcam_key_lk0_15", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk0_14_reg[] = + { + {"etcam_key_lk0_14", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk0_13_reg[] = + { + {"etcam_key_lk0_13", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk0_12_reg[] = + { + {"etcam_key_lk0_12", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk0_11_reg[] = + { + {"etcam_key_lk0_11", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk0_10_reg[] = + { + {"etcam_key_lk0_10", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk0_9_reg[] = + { + {"etcam_key_lk0_9", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk0_8_reg[] = + { + {"etcam_key_lk0_8", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk0_7_reg[] = + { + {"etcam_key_lk0_7", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk0_6_reg[] = + { + {"etcam_key_lk0_6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk0_5_reg[] = + { + {"etcam_key_lk0_5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk0_4_reg[] = + { + {"etcam_key_lk0_4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk0_3_reg[] = + { + {"etcam_key_lk0_3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk0_2_reg[] = + { + {"etcam_key_lk0_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk0_1_reg[] = + { + {"etcam_key_lk0_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk0_0_reg[] = + { + {"etcam_key_lk0_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk1_22_reg[] = + { + {"etcam_key_lk1_22", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk1_21_reg[] = + { + {"etcam_key_lk1_21", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk1_20_reg[] = + { + {"etcam_key_lk1_20", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk1_19_reg[] = + { + {"etcam_key_lk1_19", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk1_18_reg[] = + { + {"etcam_key_lk1_18", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk1_17_reg[] = + { + {"etcam_key_lk1_17", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk1_16_reg[] = + { + {"etcam_key_lk1_16", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk1_15_reg[] = + { + {"etcam_key_lk1_15", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk1_14_reg[] = + { + {"etcam_key_lk1_14", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk1_13_reg[] = + { + {"etcam_key_lk1_13", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk1_12_reg[] = + { + {"etcam_key_lk1_12", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk1_11_reg[] = + { + {"etcam_key_lk1_11", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk1_10_reg[] = + { + {"etcam_key_lk1_10", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk1_9_reg[] = + { + {"etcam_key_lk1_9", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk1_8_reg[] = + { + {"etcam_key_lk1_8", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk1_7_reg[] = + { + {"etcam_key_lk1_7", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk1_6_reg[] = + { + {"etcam_key_lk1_6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk1_5_reg[] = + { + {"etcam_key_lk1_5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk1_4_reg[] = + { + {"etcam_key_lk1_4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk1_3_reg[] = + { + {"etcam_key_lk1_3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk1_2_reg[] = + { + {"etcam_key_lk1_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk1_1_reg[] = + { + {"etcam_key_lk1_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk1_0_reg[] = + { + {"etcam_key_lk1_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk2_22_reg[] = + { + {"etcam_key_lk2_22", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk2_21_reg[] = + { + {"etcam_key_lk2_21", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk2_20_reg[] = + { + {"etcam_key_lk2_20", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk2_19_reg[] = + { + {"etcam_key_lk2_19", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk2_18_reg[] = + { + {"etcam_key_lk2_18", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk2_17_reg[] = + { + {"etcam_key_lk2_17", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk2_16_reg[] = + { + {"etcam_key_lk2_16", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk2_15_reg[] = + { + {"etcam_key_lk2_15", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk2_14_reg[] = + { + {"etcam_key_lk2_14", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk2_13_reg[] = + { + {"etcam_key_lk2_13", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk2_12_reg[] = + { + {"etcam_key_lk2_12", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk2_11_reg[] = + { + {"etcam_key_lk2_11", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk2_10_reg[] = + { + {"etcam_key_lk2_10", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk2_9_reg[] = + { + {"etcam_key_lk2_9", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk2_8_reg[] = + { + {"etcam_key_lk2_8", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk2_7_reg[] = + { + {"etcam_key_lk2_7", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk2_6_reg[] = + { + {"etcam_key_lk2_6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk2_5_reg[] = + { + {"etcam_key_lk2_5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk2_4_reg[] = + { + {"etcam_key_lk2_4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk2_3_reg[] = + { + {"etcam_key_lk2_3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk2_2_reg[] = + { + {"etcam_key_lk2_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk2_1_reg[] = + { + {"etcam_key_lk2_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk2_0_reg[] = + { + {"etcam_key_lk2_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk3_22_reg[] = + { + {"etcam_key_lk3_22", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk3_21_reg[] = + { + {"etcam_key_lk3_21", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk3_20_reg[] = + { + {"etcam_key_lk3_20", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk3_19_reg[] = + { + {"etcam_key_lk3_19", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk3_18_reg[] = + { + {"etcam_key_lk3_18", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk3_17_reg[] = + { + {"etcam_key_lk3_17", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk3_16_reg[] = + { + {"etcam_key_lk3_16", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk3_15_reg[] = + { + {"etcam_key_lk3_15", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk3_14_reg[] = + { + {"etcam_key_lk3_14", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk3_13_reg[] = + { + {"etcam_key_lk3_13", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk3_12_reg[] = + { + {"etcam_key_lk3_12", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk3_11_reg[] = + { + {"etcam_key_lk3_11", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk3_10_reg[] = + { + {"etcam_key_lk3_10", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk3_9_reg[] = + { + {"etcam_key_lk3_9", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk3_8_reg[] = + { + {"etcam_key_lk3_8", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk3_7_reg[] = + { + {"etcam_key_lk3_7", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk3_6_reg[] = + { + {"etcam_key_lk3_6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk3_5_reg[] = + { + {"etcam_key_lk3_5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk3_4_reg[] = + { + {"etcam_key_lk3_4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk3_3_reg[] = + { + {"etcam_key_lk3_3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk3_2_reg[] = + { + {"etcam_key_lk3_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk3_1_reg[] = + { + {"etcam_key_lk3_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_etcam_key_lk3_0_reg[] = + { + {"etcam_key_lk3_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_pbu_key_lk0_3_reg[] = + { + {"pbu_key_lk0_3", DPP_FIELD_FLAG_RO, 20, 21, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_pbu_key_lk0_2_reg[] = + { + {"pbu_key_lk0_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_pbu_key_lk0_1_reg[] = + { + {"pbu_key_lk0_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_pbu_key_lk0_0_reg[] = + { + {"pbu_key_lk0_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_pbu_key_lk1_3_reg[] = + { + {"pbu_key_lk1_3", DPP_FIELD_FLAG_RO, 20, 21, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_pbu_key_lk1_2_reg[] = + { + {"pbu_key_lk1_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_pbu_key_lk1_1_reg[] = + { + {"pbu_key_lk1_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_pbu_key_lk1_0_reg[] = + { + {"pbu_key_lk1_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_pbu_key_lk2_3_reg[] = + { + {"pbu_key_lk2_3", DPP_FIELD_FLAG_RO, 20, 21, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_pbu_key_lk2_2_reg[] = + { + {"pbu_key_lk2_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_pbu_key_lk2_1_reg[] = + { + {"pbu_key_lk2_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_pbu_key_lk2_0_reg[] = + { + {"pbu_key_lk2_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_pbu_key_lk3_3_reg[] = + { + {"pbu_key_lk3_3", DPP_FIELD_FLAG_RO, 20, 21, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_pbu_key_lk3_2_reg[] = + { + {"pbu_key_lk3_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_pbu_key_lk3_1_reg[] = + { + {"pbu_key_lk3_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cfg_pbu_key_lk3_0_reg[] = + { + {"pbu_key_lk3_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_schd_learn_fifo_pfull_ast_reg[] = + { + {"schd_learn_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 5, 6, 0x14, 0x0}, + }; +DPP_FIELD_T g_se_alg_schd_learn_fifo_pfull_neg_reg[] = + { + {"schd_learn_fifo_pfull_neg", DPP_FIELD_FLAG_RW, 5, 6, 0x10, 0x0}, + }; +DPP_FIELD_T g_se_alg_schd_hash0_fifo_pfull_ast_reg[] = + { + {"schd_hash0_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 5, 6, 0x14, 0x0}, + }; +DPP_FIELD_T g_se_alg_schd_hash0_fifo_pfull_neg_reg[] = + { + {"schd_hash0_fifo_pfull_neg", DPP_FIELD_FLAG_RW, 5, 6, 0x10, 0x0}, + }; +DPP_FIELD_T g_se_alg_schd_hash1_fifo_pfull_ast_reg[] = + { + {"schd_hash1_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 5, 6, 0x14, 0x0}, + }; +DPP_FIELD_T g_se_alg_schd_hash1_fifo_pfull_neg_reg[] = + { + {"schd_hash1_fifo_pfull_neg", DPP_FIELD_FLAG_RW, 5, 6, 0x10, 0x0}, + }; +DPP_FIELD_T g_se_alg_schd_hash2_fifo_pfull_ast_reg[] = + { + {"schd_hash2_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 5, 6, 0x14, 0x0}, + }; +DPP_FIELD_T g_se_alg_schd_hash2_fifo_pfull_neg_reg[] = + { + {"schd_hash2_fifo_pfull_neg", DPP_FIELD_FLAG_RW, 5, 6, 0x10, 0x0}, + }; +DPP_FIELD_T g_se_alg_schd_hash3_fifo_pfull_ast_reg[] = + { + {"schd_hash3_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 5, 6, 0x14, 0x0}, + }; +DPP_FIELD_T g_se_alg_schd_hash3_fifo_pfull_neg_reg[] = + { + {"schd_hash3_fifo_pfull_neg", DPP_FIELD_FLAG_RW, 5, 6, 0x10, 0x0}, + }; +DPP_FIELD_T g_se_alg_schd_lpm_fifo_pfull_ast_reg[] = + { + {"schd_lpm_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 5, 6, 0x14, 0x0}, + }; +DPP_FIELD_T g_se_alg_schd_lpm_fifo_pfull_neg_reg[] = + { + {"schd_lpm_fifo_pfull_neg", DPP_FIELD_FLAG_RW, 5, 6, 0x10, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash0_key_fifo_pfull_ast_reg[] = + { + {"hash0_key_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 9, 10, 0x1cc, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash0_key_fifo_pfull_neg_reg[] = + { + {"hash0_key_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 9, 10, 0x1c8, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash0_sreq_fifo_pfull_ast_reg[] = + { + {"hash0_sreq_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 5, 6, 0x1c, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash0_sreq_fifo_pfull_neg_reg[] = + { + {"hash0_sreq_fifo_pfull_neg", DPP_FIELD_FLAG_RW, 5, 6, 0x14, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash0_int_rsp_fifo_pfull_ast_reg[] = + { + {"hash0_int_rsp_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 9, 10, 0x1cc, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash0_int_rsp_fifo_pfull_neg_reg[] = + { + {"hash0_int_rsp_fifo_pfull_neg", DPP_FIELD_FLAG_RW, 9, 10, 0x1c8, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash0_ext_rsp_fifo_pfull_ast_reg[] = + { + {"hash0_ext_rsp_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 5, 6, 0x20, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash0_ext_rsp_fifo_pfull_neg_reg[] = + { + {"hash0_ext_rsp_fifo_pfull_neg", DPP_FIELD_FLAG_RW, 5, 6, 0x1e, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash1_key_fifo_pfull_ast_reg[] = + { + {"hash1_key_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 9, 10, 0x1cc, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash1_key_fifo_pfull_neg_reg[] = + { + {"hash1_key_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 9, 10, 0x1c8, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash1_sreq_fifo_pfull_ast_reg[] = + { + {"hash1_sreq_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 5, 6, 0x1c, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash1_sreq_fifo_pfull_neg_reg[] = + { + {"hash1_sreq_fifo_pfull_neg", DPP_FIELD_FLAG_RW, 5, 6, 0x14, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash1_int_rsp_fifo_pfull_ast_reg[] = + { + {"hash1_int_rsp_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 9, 10, 0x1cc, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash1_int_rsp_fifo_pfull_neg_reg[] = + { + {"hash1_int_rsp_fifo_pfull_neg", DPP_FIELD_FLAG_RW, 9, 10, 0x1c8, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash1_ext_rsp_fifo_pfull_ast_reg[] = + { + {"hash1_ext_rsp_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 5, 6, 0x20, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash1_ext_rsp_fifo_pfull_neg_reg[] = + { + {"hash1_ext_rsp_fifo_pfull_neg", DPP_FIELD_FLAG_RW, 5, 6, 0x1e, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash2_key_fifo_pfull_ast_reg[] = + { + {"hash2_key_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 9, 10, 0x1cc, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash2_key_fifo_pfull_neg_reg[] = + { + {"hash2_key_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 9, 10, 0x1c8, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash2_sreq_fifo_pfull_ast_reg[] = + { + {"hash2_sreq_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 5, 6, 0x1c, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash2_sreq_fifo_pfull_neg_reg[] = + { + {"hash2_sreq_fifo_pfull_neg", DPP_FIELD_FLAG_RW, 5, 6, 0x14, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash2_int_rsp_fifo_pfull_ast_reg[] = + { + {"hash2_int_rsp_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 9, 10, 0x1cc, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash2_int_rsp_fifo_pfull_neg_reg[] = + { + {"hash2_int_rsp_fifo_pfull_neg", DPP_FIELD_FLAG_RW, 9, 10, 0x1c8, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash2_ext_rsp_fifo_pfull_ast_reg[] = + { + {"hash2_ext_rsp_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 5, 6, 0x20, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash2_ext_rsp_fifo_pfull_neg_reg[] = + { + {"hash2_ext_rsp_fifo_pfull_neg", DPP_FIELD_FLAG_RW, 5, 6, 0x1e, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash3_key_fifo_pfull_ast_reg[] = + { + {"hash3_key_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 9, 10, 0x1cc, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash3_key_fifo_pfull_neg_reg[] = + { + {"hash3_key_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 9, 10, 0x1c8, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash3_sreq_fifo_pfull_ast_reg[] = + { + {"hash3_sreq_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 5, 6, 0x1c, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash3_sreq_fifo_pfull_neg_reg[] = + { + {"hash3_sreq_fifo_pfull_neg", DPP_FIELD_FLAG_RW, 5, 6, 0x14, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash3_int_rsp_fifo_pfull_ast_reg[] = + { + {"hash3_int_rsp_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 9, 10, 0x1cc, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash3_int_rsp_fifo_pfull_neg_reg[] = + { + {"hash3_int_rsp_fifo_pfull_neg", DPP_FIELD_FLAG_RW, 9, 10, 0x1c8, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash3_ext_rsp_fifo_pfull_ast_reg[] = + { + {"hash3_ext_rsp_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 5, 6, 0x20, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash3_ext_rsp_fifo_pfull_neg_reg[] = + { + {"hash3_ext_rsp_fifo_pfull_neg", DPP_FIELD_FLAG_RW, 5, 6, 0x1e, 0x0}, + }; +DPP_FIELD_T g_se_alg_lpm_as_info_reg[] = + { + {"lpm_as_type", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"lpm_as_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_se_alg_lpm_ext_rsp_fifo_u0_pfull_neg_reg[] = + { + {"lpm_ext_rsp_fifo_u0_pfull_neg", DPP_FIELD_FLAG_RW, 6, 7, 0x20, 0x0}, + }; +DPP_FIELD_T g_se_alg_lpm_ext_rsp_fifo_u2_pfull_ast_reg[] = + { + {"lpm_ext_rsp_fifo_u2_pfull_ast", DPP_FIELD_FLAG_RW, 9, 10, 0x1e4, 0x0}, + }; +DPP_FIELD_T g_se_alg_lpm_ext_rsp_fifo_u2_pfull_neg_reg[] = + { + {"lpm_ext_rsp_fifo_u2_pfull_neg", DPP_FIELD_FLAG_RW, 9, 10, 0x1e0, 0x0}, + }; +DPP_FIELD_T g_se_alg_lpm_ext_rsp_fifo_u3_pfull_ast_reg[] = + { + {"lpm_ext_rsp_fifo_u3_pfull_ast", DPP_FIELD_FLAG_RW, 9, 10, 0x1e4, 0x0}, + }; +DPP_FIELD_T g_se_alg_lpm_ext_rsp_fifo_u3_pfull_neg_reg[] = + { + {"lpm_ext_rsp_fifo_u3_pfull_neg", DPP_FIELD_FLAG_RW, 9, 10, 0x1e0, 0x0}, + }; +DPP_FIELD_T g_se_alg_lpm_ext_rsp_fifo_u4_pfull_ast_reg[] = + { + {"lpm_ext_rsp_fifo_u4_pfull_ast", DPP_FIELD_FLAG_RW, 5, 6, 0x14, 0x0}, + }; +DPP_FIELD_T g_se_alg_lpm_ext_rsp_fifo_u4_pfull_neg_reg[] = + { + {"lpm_ext_rsp_fifo_u4_pfull_neg", DPP_FIELD_FLAG_RW, 5, 6, 0x14, 0x0}, + }; +DPP_FIELD_T g_se_alg_lpm_as_rsp_fifo_u0_pfull_ast_reg[] = + { + {"lpm_as_rsp_fifo_u0_pfull_ast", DPP_FIELD_FLAG_RW, 6, 7, 0x24, 0x0}, + }; +DPP_FIELD_T g_se_alg_lpm_as_rsp_fifo_u0_pfull_neg_reg[] = + { + {"lpm_as_rsp_fifo_u0_pfull_neg", DPP_FIELD_FLAG_RW, 6, 7, 0x20, 0x0}, + }; +DPP_FIELD_T g_se_alg_lpm_as_rsp_fifo_u1_pfull_ast_reg[] = + { + {"lpm_as_rsp_fifo_u1_pfull_ast", DPP_FIELD_FLAG_RW, 9, 10, 0x1e2, 0x0}, + }; +DPP_FIELD_T g_se_alg_lpm_as_rsp_fifo_u1_pfull_neg_reg[] = + { + {"lpm_as_rsp_fifo_u1_pfull_neg", DPP_FIELD_FLAG_RW, 9, 10, 0x1dc, 0x0}, + }; +DPP_FIELD_T g_se_alg_lpm_v4_ddr3_base_addr_reg[] = + { + {"lpm_v4_ddr3_base_addr", DPP_FIELD_FLAG_RW, 25, 26, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_lpm_v6_ddr3_base_addr_reg[] = + { + {"lpm_v6_ddr3_base_addr", DPP_FIELD_FLAG_RW, 25, 26, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_debug_cnt_mode_reg[] = + { + {"cnt_rd_mode", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0}, + {"cnt_overflow_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash_p0_key_vld_cnt_reg[] = + { + {"hash_p0_key_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash_p1_key_vld_cnt_reg[] = + { + {"hash_p1_key_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash_p2_key_vld_cnt_reg[] = + { + {"hash_p2_key_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash_p3_key_vld_cnt_reg[] = + { + {"hash_p3_key_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_lpm_p0_key_vld_cnt_reg[] = + { + {"lpm_p0_key_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash_p0_rsp_vld_cnt_reg[] = + { + {"hash_p0_rsp_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash_p1_rsp_vld_cnt_reg[] = + { + {"hash_p1_rsp_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash_p2_rsp_vld_cnt_reg[] = + { + {"hash_p2_rsp_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash_p3_rsp_vld_cnt_reg[] = + { + {"hash_p3_rsp_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_lpm_p0_rsp_vld_cnt_reg[] = + { + {"lpm_p0_rsp_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash_p0_smf_cnt_reg[] = + { + {"hash_p0_smf_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash_p1_smf_cnt_reg[] = + { + {"hash_p1_smf_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash_p2_smf_cnt_reg[] = + { + {"hash_p2_smf_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash_p3_smf_cnt_reg[] = + { + {"hash_p3_smf_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_lpm_p0_smf_cnt_reg[] = + { + {"lpm_p0_smf_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash_p0_spacevld_cnt_reg[] = + { + {"hash_p0_spacevld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash_p1_spacevld_cnt_reg[] = + { + {"hash_p1_spacevld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash_p2_spacevld_cnt_reg[] = + { + {"hash_p2_spacevld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash_p3_spacevld_cnt_reg[] = + { + {"hash_p3_spacevld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_smmu1_p0_req_vld_cnt_reg[] = + { + {"smmu1_p0_req_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_smmu1_p1_req_vld_cnt_reg[] = + { + {"smmu1_p1_req_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_smmu1_p2_req_vld_cnt_reg[] = + { + {"smmu1_p2_req_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_smmu1_p3_req_vld_cnt_reg[] = + { + {"smmu1_p3_req_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_smmu1_p4_req_vld_cnt_reg[] = + { + {"smmu1_p4_req_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_smmu1_p5_req_vld_cnt_reg[] = + { + {"smmu1_p5_req_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_smmu1_p0_rsp_vld_cnt_reg[] = + { + {"smmu1_p0_rsp_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_smmu1_p1_rsp_vld_cnt_reg[] = + { + {"smmu1_p1_rsp_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_smmu1_p2_rsp_vld_cnt_reg[] = + { + {"smmu1_p2_rsp_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_smmu1_p3_rsp_vld_cnt_reg[] = + { + {"smmu1_p3_rsp_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_smmu1_p4_rsp_vld_cnt_reg[] = + { + {"smmu1_p4_rsp_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_smmu1_p5_rsp_vld_cnt_reg[] = + { + {"smmu1_p5_rsp_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_schd_learn_fifo_int_cnt_reg[] = + { + {"schd_learn_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_schd_hash0_fifo_int_cnt_reg[] = + { + {"schd_hash0_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_schd_hash1_fifo_int_cnt_reg[] = + { + {"schd_hash1_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_schd_hash2_fifo_int_cnt_reg[] = + { + {"schd_hash2_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_schd_hash3_fifo_int_cnt_reg[] = + { + {"schd_hash3_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_schd_lpm_fifo_int_cnt_reg[] = + { + {"schd_lpm_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_schd_learn_fifo_parity_err_cnt_reg[] = + { + {"schd_learn_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_schd_hash0_fifo_parity_err_cnt_reg[] = + { + {"schd_hash0_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_schd_hash1_fifo_parity_err_cnt_reg[] = + { + {"schd_hash1_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_schd_hash2_fifo_parity_err_cnt_reg[] = + { + {"schd_hash2_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_schd_hash3_fifo_parity_err_cnt_reg[] = + { + {"schd_hash3_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_schd_lpm_fifo_parity_err_cnt_reg[] = + { + {"schd_lpm_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_rd_init_cft_cnt_reg[] = + { + {"rd_init_cft_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_zgp0_zblk0_ecc_err_cnt_reg[] = + { + {"zgp0_zblk0_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_zgp0_zblk1_ecc_err_cnt_reg[] = + { + {"zgp0_zblk1_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_zgp0_zblk2_ecc_err_cnt_reg[] = + { + {"zgp0_zblk2_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_zgp0_zblk3_ecc_err_cnt_reg[] = + { + {"zgp0_zblk3_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_zgp0_zblk4_ecc_err_cnt_reg[] = + { + {"zgp0_zblk4_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_zgp0_zblk5_ecc_err_cnt_reg[] = + { + {"zgp0_zblk5_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_zgp0_zblk6_ecc_err_cnt_reg[] = + { + {"zgp0_zblk6_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_zgp0_zblk7_ecc_err_cnt_reg[] = + { + {"zgp0_zblk7_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_zgp1_zblk0_ecc_err_cnt_reg[] = + { + {"zgp1_zblk0_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_zgp1_zblk1_ecc_err_cnt_reg[] = + { + {"zgp1_zblk1_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_zgp1_zblk2_ecc_err_cnt_reg[] = + { + {"zgp1_zblk2_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_zgp1_zblk3_ecc_err_cnt_reg[] = + { + {"zgp1_zblk3_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_zgp1_zblk4_ecc_err_cnt_reg[] = + { + {"zgp1_zblk4_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_zgp1_zblk5_ecc_err_cnt_reg[] = + { + {"zgp1_zblk5_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_zgp1_zblk6_ecc_err_cnt_reg[] = + { + {"zgp1_zblk6_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_zgp1_zblk7_ecc_err_cnt_reg[] = + { + {"zgp1_zblk7_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_zgp2_zblk0_ecc_err_cnt_reg[] = + { + {"zgp2_zblk0_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_zgp2_zblk1_ecc_err_cnt_reg[] = + { + {"zgp2_zblk1_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_zgp2_zblk2_ecc_err_cnt_reg[] = + { + {"zgp2_zblk2_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_zgp2_zblk3_ecc_err_cnt_reg[] = + { + {"zgp2_zblk3_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_zgp2_zblk4_ecc_err_cnt_reg[] = + { + {"zgp2_zblk4_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_zgp2_zblk5_ecc_err_cnt_reg[] = + { + {"zgp2_zblk5_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_zgp2_zblk6_ecc_err_cnt_reg[] = + { + {"zgp2_zblk6_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_zgp2_zblk7_ecc_err_cnt_reg[] = + { + {"zgp2_zblk7_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_zgp3_zblk0_ecc_err_cnt_reg[] = + { + {"zgp3_zblk0_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_zgp3_zblk1_ecc_err_cnt_reg[] = + { + {"zgp3_zblk1_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_zgp3_zblk2_ecc_err_cnt_reg[] = + { + {"zgp3_zblk2_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_zgp3_zblk3_ecc_err_cnt_reg[] = + { + {"zgp3_zblk3_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_zgp3_zblk4_ecc_err_cnt_reg[] = + { + {"zgp3_zblk4_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_zgp3_zblk5_ecc_err_cnt_reg[] = + { + {"zgp3_zblk5_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_zgp3_zblk6_ecc_err_cnt_reg[] = + { + {"zgp3_zblk6_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_zgp3_zblk7_ecc_err_cnt_reg[] = + { + {"zgp3_zblk7_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_zcam_hash_p0_err_cnt_reg[] = + { + {"zcam_hash_p0_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_zcam_hash_p1_err_cnt_reg[] = + { + {"zcam_hash_p1_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_zcam_hash_p2_err_cnt_reg[] = + { + {"zcam_hash_p2_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_zcam_hash_p3_err_cnt_reg[] = + { + {"zcam_hash_p3_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_zcam_lpm_err_cnt_reg[] = + { + {"zcam_lpm_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash0_sreq_fifo_parity_err_cnt_reg[] = + { + {"hash0_sreq_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash0_sreq_fifo_int_cnt_reg[] = + { + {"hash0_sreq_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash0_key_fifo_int_cnt_reg[] = + { + {"hash0_key_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash0_int_rsp_fifo_parity_err_cnt_reg[] = + { + {"hash0_int_rsp_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash0_ext_rsp_fifo_parity_err_cnt_reg[] = + { + {"hash0_ext_rsp_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash0_ext_rsp_fifo_int_cnt_reg[] = + { + {"hash0_ext_rsp_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash0_int_rsp_fifo_int_cnt_reg[] = + { + {"hash0_int_rsp_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash1_sreq_fifo_parity_err_cnt_reg[] = + { + {"hash1_sreq_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash1_sreq_fifo_int_cnt_reg[] = + { + {"hash1_sreq_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash1_key_fifo_int_cnt_reg[] = + { + {"hash1_key_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash1_int_rsp_fifo_parity_err_cnt_reg[] = + { + {"hash1_int_rsp_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash1_ext_rsp_fifo_parity_err_cnt_reg[] = + { + {"hash1_ext_rsp_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash1_ext_rsp_fifo_int_cnt_reg[] = + { + {"hash1_ext_rsp_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash1_int_rsp_fifo_int_cnt_reg[] = + { + {"hash1_int_rsp_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash2_sreq_fifo_parity_err_cnt_reg[] = + { + {"hash2_sreq_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash2_sreq_fifo_int_cnt_reg[] = + { + {"hash2_sreq_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash2_key_fifo_int_cnt_reg[] = + { + {"hash2_key_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash2_int_rsp_fifo_parity_err_cnt_reg[] = + { + {"hash2_int_rsp_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash2_ext_rsp_fifo_parity_err_cnt_reg[] = + { + {"hash2_ext_rsp_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash2_ext_rsp_fifo_int_cnt_reg[] = + { + {"hash2_ext_rsp_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash2_int_rsp_fifo_int_cnt_reg[] = + { + {"hash2_int_rsp_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash3_sreq_fifo_parity_err_cnt_reg[] = + { + {"hash3_sreq_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash3_sreq_fifo_int_cnt_reg[] = + { + {"hash3_sreq_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash3_key_fifo_int_cnt_reg[] = + { + {"hash3_key_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash3_int_rsp_fifo_parity_err_cnt_reg[] = + { + {"hash3_int_rsp_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash3_ext_rsp_fifo_parity_err_cnt_reg[] = + { + {"hash3_ext_rsp_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash3_ext_rsp_fifo_int_cnt_reg[] = + { + {"hash3_ext_rsp_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash3_int_rsp_fifo_int_cnt_reg[] = + { + {"hash3_int_rsp_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_lpm_ext_rsp_fifo_int_cnt_reg[] = + { + {"lpm_ext_rsp_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_lpm_ext_v6_fifo_int_cnt_reg[] = + { + {"lpm_ext_v6_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_lpm_ext_v4_fifo_int_cnt_reg[] = + { + {"lpm_ext_v4_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_lpm_ext_addr_fifo_int_cnt_reg[] = + { + {"lpm_ext_addr_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_lpm_ext_v4_fifo_parity_err_cnt_reg[] = + { + {"lpm_ext_v4_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_lpm_ext_v6_fifo_parity_err_cnt_reg[] = + { + {"lpm_ext_v6_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_lpm_ext_rsp_fifo_parity_err_cnt_reg[] = + { + {"lpm_ext_rsp_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_lpm_as_req_fifo_int_cnt_reg[] = + { + {"lpm_as_req_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_lpm_as_int_rsp_fifo_int_cnt_reg[] = + { + {"lpm_as_int_rsp_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_se_alg_int_status_reg[] = + { + {"schd_int_unmask_flag", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"zblk_ecc_int_unmask_flag", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"hash0_int_unmask_flag", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"hash1_int_unmask_flag", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"hash2_int_unmask_flag", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"hash3_int_unmask_flag", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"lpm_int_unmask_flag", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_schd_int_en_reg[] = + { + {"wr_rsp_fifo_ovfl", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"init_rd_cft_en", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"schd_lpm_fifo_parity_errl", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"schd_hash3_fifo_parity_err", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"schd_hash2_fifo_parity_err", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"schd_hash1_fifo_parity_err", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"schd_hash0_fifo_parity_err", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"schd_learn_fifo_parity_err", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"schd_lpm_fifo_ovfl", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"schd_hash3_fifo_ovfl", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"schd_hash2_fifo_unfl", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"schd_hash1_fifo_ovfl", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"schd_hash0_fifo_ovfl", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"schd_learn_fifo_ovfl", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_se_alg_schd_int_mask_reg[] = + { + {"schd_int_mask", DPP_FIELD_FLAG_RW, 13, 14, 0x3fff, 0x0}, + }; +DPP_FIELD_T g_se_alg_schd_int_status_reg[] = + { + {"schd_int_status", DPP_FIELD_FLAG_RC, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_zblk_ecc_int_en_reg[] = + { + {"zblk_ecc_int_en", DPP_FIELD_FLAG_RW, 31, 32, 0xffffff, 0x0}, + }; +DPP_FIELD_T g_se_alg_zblk_ecc_int_mask_reg[] = + { + {"zblk_ecc_int_mask", DPP_FIELD_FLAG_RW, 31, 32, 0xffffff, 0x0}, + }; +DPP_FIELD_T g_se_alg_zblk_ecc_int_status_reg[] = + { + {"zblk_ecc_int_status", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash0_int_en_reg[] = + { + {"zcam_hash_p0_err_en", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"hash0_agree_int_fifo_ovf_en", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"hash0_agree_ext_fifo_ovf_en", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"hash0_agree_ext_fifo_parity_err_en", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"hash0_agree_int_fifo_parity_err_en", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"hash0_key_fifo_ovfl_en", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"hash0_sreq_fifo_ovfl_en", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"hash0_key_fifo_parity_err_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash0_int_mask_reg[] = + { + {"hash0_int_mask", DPP_FIELD_FLAG_RW, 7, 8, 0xff, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash0_int_status_reg[] = + { + {"hash0_int_status", DPP_FIELD_FLAG_RC, 7, 8, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash1_int_en_reg[] = + { + {"zcam_hash_p1_err_en", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"hash1_agree_int_fifo_ovf_en", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"hash1_agree_ext_fifo_ovf_en", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"hash1_agree_ext_fifo_parity_err_en", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"hash1_agree_int_fifo_parity_err_en", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"hash1_key_fifo_ovfl_en", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"hash1_sreq_fifo_ovfl_en", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"hash1_key_fifo_parity_err_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash1_int_mask_reg[] = + { + {"hash1_int_mask", DPP_FIELD_FLAG_RW, 7, 8, 0xff, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash1_int_status_reg[] = + { + {"hash1_int_status", DPP_FIELD_FLAG_RC, 7, 8, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash2_int_en_reg[] = + { + {"zcam_hash_p2_err_en", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"hash2_agree_int_fifo_ovf_en", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"hash2_agree_ext_fifo_ovf_en", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"hash2_agree_ext_fifo_parity_err_en", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"hash2_agree_int_fifo_parity_err_en", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"hash2_key_fifo_ovfl_en", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"hash2_sreq_fifo_ovfl_en", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"hash2_key_fifo_parity_err_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash2_int_mask_reg[] = + { + {"hash2_int_mask", DPP_FIELD_FLAG_RW, 7, 8, 0xff, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash2_int_status_reg[] = + { + {"hash2_int_status", DPP_FIELD_FLAG_RC, 7, 8, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash3_int_en_reg[] = + { + {"zcam_hash_p3_err_en", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"hash3_agree_int_fifo_ovf_en", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"hash3_agree_ext_fifo_ovf_en", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"hash3_agree_ext_fifo_parity_err_en", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"hash3_agree_int_fifo_parity_err_en", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"hash3_key_fifo_ovfl_en", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"hash3_sreq_fifo_ovfl_en", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"hash3_key_fifo_parity_err_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash3_int_mask_reg[] = + { + {"hash3_int_mask", DPP_FIELD_FLAG_RW, 7, 8, 0xff, 0x0}, + }; +DPP_FIELD_T g_se_alg_hash3_int_status_reg[] = + { + {"hash3_int_status", DPP_FIELD_FLAG_RC, 7, 8, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_lpm_int_en_reg[] = + { + {"zcam_lpm_err_en", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"lpm_as_int_rsp_fifo_ovfl_en", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"lpm_as_req_fifo_ovfl_en", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"lpm_ext_ddr_rsp_fifo_parity_en", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"lpm_ext_v6_key_parity_en", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"lpm_ext_v4_key_parity_en", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"lpm_ext_addr_fifo_ovfl_en", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"lpm_ext_v4_fifo_ovfl_en", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"lpm_ext_v6_fifo_ovfl_en", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"lpm_ext_ddr_rsp_ovf_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_se_alg_lpm_int_mask_reg[] = + { + {"lpm_int_mask", DPP_FIELD_FLAG_RW, 9, 10, 0x3ff, 0x0}, + }; +DPP_FIELD_T g_se_alg_lpm_int_status_reg[] = + { + {"lpm_int_status", DPP_FIELD_FLAG_RC, 9, 10, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_zblock_lpm_mask0_reg[] = + { + {"vpn_id_mask", DPP_FIELD_FLAG_RW, 143, 16, 0x0, 0x0}, + {"prefix0_mask", DPP_FIELD_FLAG_RW, 127, 32, 0x0, 0x0}, + {"prefix1_mask", DPP_FIELD_FLAG_RW, 95, 32, 0x0, 0x0}, + {"prefix2_mask", DPP_FIELD_FLAG_RW, 63, 32, 0x0, 0x0}, + {"prefix3_mask", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_zblock_lpm_mask1_reg[] = + { + {"vpn_id_mask", DPP_FIELD_FLAG_RW, 143, 16, 0x0, 0x0}, + {"prefix0_mask", DPP_FIELD_FLAG_RW, 127, 32, 0x0, 0x0}, + {"prefix1_mask", DPP_FIELD_FLAG_RW, 95, 32, 0x0, 0x0}, + {"prefix2_mask", DPP_FIELD_FLAG_RW, 63, 32, 0x0, 0x0}, + {"prefix3_mask", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_zblock_lpm_mask2_reg[] = + { + {"vpn_id_mask", DPP_FIELD_FLAG_RW, 143, 16, 0x0, 0x0}, + {"prefix0_mask", DPP_FIELD_FLAG_RW, 127, 32, 0x0, 0x0}, + {"prefix1_mask", DPP_FIELD_FLAG_RW, 95, 32, 0x0, 0x0}, + {"prefix2_mask", DPP_FIELD_FLAG_RW, 63, 32, 0x0, 0x0}, + {"prefix3_mask", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_zblock_lpm_mask3_reg[] = + { + {"vpn_id_mask", DPP_FIELD_FLAG_RW, 143, 16, 0x0, 0x0}, + {"prefix0_mask", DPP_FIELD_FLAG_RW, 127, 32, 0x0, 0x0}, + {"prefix1_mask", DPP_FIELD_FLAG_RW, 95, 32, 0x0, 0x0}, + {"prefix2_mask", DPP_FIELD_FLAG_RW, 63, 32, 0x0, 0x0}, + {"prefix3_mask", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_zblock_default_route0_reg[] = + { + {"vpn_id", DPP_FIELD_FLAG_RW, 39, 16, 0x0, 0x0}, + {"vpn_dresult", DPP_FIELD_FLAG_RW, 23, 22, 0x0, 0x0}, + {"vpn_flag", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0}, + {"vpn_vld", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_zblock_default_route1_reg[] = + { + {"vpn_id", DPP_FIELD_FLAG_RW, 39, 16, 0x0, 0x0}, + {"vpn_dresult", DPP_FIELD_FLAG_RW, 23, 22, 0x0, 0x0}, + {"vpn_flag", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0}, + {"vpn_vld", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_zblock_default_route2_reg[] = + { + {"vpn_id", DPP_FIELD_FLAG_RW, 39, 16, 0x0, 0x0}, + {"vpn_dresult", DPP_FIELD_FLAG_RW, 23, 22, 0x0, 0x0}, + {"vpn_flag", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0}, + {"vpn_vld", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_zblock_default_route3_reg[] = + { + {"vpn_id", DPP_FIELD_FLAG_RW, 39, 16, 0x0, 0x0}, + {"vpn_dresult", DPP_FIELD_FLAG_RW, 23, 22, 0x0, 0x0}, + {"vpn_flag", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0}, + {"vpn_vld", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_zblock_default_route4_reg[] = + { + {"vpn_id", DPP_FIELD_FLAG_RW, 39, 16, 0x0, 0x0}, + {"vpn_dresult", DPP_FIELD_FLAG_RW, 23, 22, 0x0, 0x0}, + {"vpn_flag", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0}, + {"vpn_vld", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_zblock_default_route5_reg[] = + { + {"vpn_id", DPP_FIELD_FLAG_RW, 39, 16, 0x0, 0x0}, + {"vpn_dresult", DPP_FIELD_FLAG_RW, 23, 22, 0x0, 0x0}, + {"vpn_flag", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0}, + {"vpn_vld", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_zblock_default_route6_reg[] = + { + {"vpn_id", DPP_FIELD_FLAG_RW, 39, 16, 0x0, 0x0}, + {"vpn_dresult", DPP_FIELD_FLAG_RW, 23, 22, 0x0, 0x0}, + {"vpn_flag", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0}, + {"vpn_vld", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_zblock_default_route7_reg[] = + { + {"vpn_id", DPP_FIELD_FLAG_RW, 39, 16, 0x0, 0x0}, + {"vpn_dresult", DPP_FIELD_FLAG_RW, 23, 22, 0x0, 0x0}, + {"vpn_flag", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0}, + {"vpn_vld", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_zblock_hash_listtable_item0_reg[] = + { + {"hash_item", DPP_FIELD_FLAG_RW, 511, 512, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_zblock_hash_listtable_item1_reg[] = + { + {"hash_item", DPP_FIELD_FLAG_RW, 511, 512, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_zblock_hash_listtable_item2_reg[] = + { + {"hash_item", DPP_FIELD_FLAG_RW, 511, 512, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_zblock_hash_listtable_item3_reg[] = + { + {"hash_item", DPP_FIELD_FLAG_RW, 511, 512, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_zblock_ecc_err_status_reg[] = + { + {"sram3_ecc_err", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"sram2_ecc_err", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"sram1_ecc_err", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"sram0_ecc_err", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_zblock_lpm_v6_sram_cmp_reg[] = + { + {"sram_cmp_flag", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_alg_zblock_lpm_v4_sram_cmp_reg[] = + { + {"sram_cmp_flag", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_parser_kschd_pful_cfg_reg[] = + { + {"kschd_pful_assert", DPP_FIELD_FLAG_RW, 11, 6, 0xc, 0x0}, + {"kschd_pful_negate", DPP_FIELD_FLAG_RW, 5, 6, 0xc, 0x0}, + }; +DPP_FIELD_T g_se_parser_debug_cnt_mode_reg[] = + { + {"cnt_rd_mode", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0}, + {"cnt_overflow_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_se_parser_parser_int_en_reg[] = + { + {"parser_int_en", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_se_parser_parser_int_mask_reg[] = + { + {"parser_int_mask", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_se_parser_parser_int_status_reg[] = + { + {"parser_int_status", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_parser_parser_int_unmask_flag_reg[] = + { + {"parser_int_unmask_flag", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_parser_ecc_bypass_read_reg[] = + { + {"ecc_bypass_read", DPP_FIELD_FLAG_RW, 5, 6, 0x3f, 0x0}, + }; +DPP_FIELD_T g_se_parser_mex0_5_req_cnt_reg[] = + { + {"mex0_5_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_parser_kschd_req0_5_cnt_reg[] = + { + {"kschd_req0_5_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_parser_kschd_parser_fc0_5_cnt_reg[] = + { + {"kschd_parser_fc0_5_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_parser_se_ppu_mex0_5_fc_cnt_reg[] = + { + {"se_ppu_mex0_5_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_parser_smmu0_marc_fc_cnt_reg[] = + { + {"smmu0_marc_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_parser_smmu0_marc_key_cnt_reg[] = + { + {"smmu0_marc_key_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_parser_cmmu_key_cnt_reg[] = + { + {"cmmu_key_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_parser_cmmu_parser_fc_cnt_reg[] = + { + {"cmmu_parser_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_parser_marc_tab_type_err_mex0_5_cnt_reg[] = + { + {"marc_tab_type_err_mex0_5_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_parser_eram_fulladdr_drop_cnt_reg[] = + { + {"eram_fulladdr_drop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_as_hash0_pful_cfg_reg[] = + { + {"hash0_pful_cfg", DPP_FIELD_FLAG_RW, 19, 20, 0x7d9f6, 0x0}, + }; +DPP_FIELD_T g_se_as_hash1_pful_cfg_reg[] = + { + {"hash1_pful_cfg", DPP_FIELD_FLAG_RW, 19, 20, 0x7d9f6, 0x0}, + }; +DPP_FIELD_T g_se_as_hash2_pful_cfg_reg[] = + { + {"hash2_pful_cfg", DPP_FIELD_FLAG_RW, 19, 20, 0x7d9f6, 0x0}, + }; +DPP_FIELD_T g_se_as_hash3_pful_cfg_reg[] = + { + {"hash3_pful_cfg", DPP_FIELD_FLAG_RW, 19, 20, 0x7d9f6, 0x0}, + }; +DPP_FIELD_T g_se_as_pbu_pful_cfg_reg[] = + { + {"pbu_pful_cfg", DPP_FIELD_FLAG_RW, 11, 12, 0x69a, 0x0}, + }; +DPP_FIELD_T g_se_as_lpm_pful_cfg_reg[] = + { + {"lpm_pful_cfg", DPP_FIELD_FLAG_RW, 19, 20, 0x7d9f6, 0x0}, + }; +DPP_FIELD_T g_se_as_etcam_pful_cfg_reg[] = + { + {"etcam_pful_cfg", DPP_FIELD_FLAG_RW, 13, 14, 0x1c38, 0x0}, + }; +DPP_FIELD_T g_se_as_as_learn0_fifo_cfg_reg[] = + { + {"as_learn1_pful_negate", DPP_FIELD_FLAG_RW, 27, 7, 0x38, 0x0}, + {"as_learn1_pful_asert", DPP_FIELD_FLAG_RW, 20, 7, 0x38, 0x0}, + {"as_learn0_pful_negate", DPP_FIELD_FLAG_RW, 13, 7, 0x38, 0x0}, + {"as_learn0_pful_asert", DPP_FIELD_FLAG_RW, 6, 7, 0x38, 0x0}, + }; +DPP_FIELD_T g_se_as_as_learn1_fifo_cfg_reg[] = + { + {"as_learn3_pful_negate", DPP_FIELD_FLAG_RW, 27, 7, 0x38, 0x0}, + {"as_learn3_pful_asert", DPP_FIELD_FLAG_RW, 20, 7, 0x38, 0x0}, + {"as_learn2_pful_negate", DPP_FIELD_FLAG_RW, 13, 7, 0x38, 0x0}, + {"as_learn2_pful_asert", DPP_FIELD_FLAG_RW, 6, 7, 0x38, 0x0}, + }; +DPP_FIELD_T g_se_as_as_dma_fifo_cfg_reg[] = + { + {"as_dma_fifo_cfg", DPP_FIELD_FLAG_RW, 15, 16, 0x7272, 0x0}, + }; +DPP_FIELD_T g_se_as_age_pful_cfg_reg[] = + { + {"age_pful_cfg", DPP_FIELD_FLAG_RW, 11, 12, 0x618, 0x0}, + }; +DPP_FIELD_T g_se_as_etcam_rsp_cfg_reg[] = + { + {"eram_rsp_pful_negate", DPP_FIELD_FLAG_RW, 27, 7, 0x24, 0x0}, + {"eram_rsp_pful_assert", DPP_FIELD_FLAG_RW, 20, 7, 0x24, 0x0}, + {"etcam_rsp_pful_negate", DPP_FIELD_FLAG_RW, 13, 7, 0x21, 0x0}, + {"etcam_rsp_pful_assert", DPP_FIELD_FLAG_RW, 6, 7, 0x21, 0x0}, + }; +DPP_FIELD_T g_se_as_pbu_ecc_bypass_read_reg[] = + { + {"pbu_ecc_bypass_read", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_se_as_etcam0_ecc_bypass_read_reg[] = + { + {"etcam0_ecc_bypass_read", DPP_FIELD_FLAG_RW, 2, 3, 0x7, 0x0}, + }; +DPP_FIELD_T g_se_as_etcam1_ecc_bypass_read_reg[] = + { + {"etcam1_ecc_bypass_read", DPP_FIELD_FLAG_RW, 2, 3, 0x7, 0x0}, + }; +DPP_FIELD_T g_se_as_lpm_ecc_bypass_read_reg[] = + { + {"lpm_ecc_bypass_read", DPP_FIELD_FLAG_RW, 1, 2, 0x3, 0x0}, + }; +DPP_FIELD_T g_se_as_hash_ecc_bypass_read_reg[] = + { + {"hash3_ecc_bypass_read", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"hash2_ecc_bypass_read", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"hash1_ecc_bypass_read", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"hash0_ecc_bypass_read", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_se_as_hash_learn_ecc_bypass_read_reg[] = + { + {"hash_learn_ecc_bypass_read", DPP_FIELD_FLAG_RW, 3, 4, 0xf, 0x0}, + }; +DPP_FIELD_T g_se_as_debug_cnt_mode_reg[] = + { + {"cnt_rd_mode", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0}, + {"cnt_overflow_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_se_as_as_int_0_en_reg[] = + { + {"as_int_0_en", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_se_as_as_int_0_mask_reg[] = + { + {"as_int_0_mask", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_se_as_as_int_1_en_reg[] = + { + {"as_int_1_en", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_se_as_as_int_1_mask_reg[] = + { + {"as_int_1_mask", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_se_as_as_int_2_en_reg[] = + { + {"as_int_2_en", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_se_as_as_int_2_mask_reg[] = + { + {"as_int_2_mask", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_se_as_as_int_0_status_reg[] = + { + {"port0_int_status", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_as_as_int_1_status_reg[] = + { + {"port1_int_status", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_as_as_int_2_status_reg[] = + { + {"port2_int_status", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_as_se_as_int_status_reg[] = + { + {"as_int_2_unmask_flag", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0}, + {"as_int_1_unmask_flag", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0}, + {"as_int_0_unmask_flag", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_as_hash0_3_wr_req_cnt_reg[] = + { + {"hash0_3_wr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_as_smmu0_etcam0_1_fc_cnt_reg[] = + { + {"smmu0_etcam0_1_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_as_etcam0_1_smmu0_req_cnt_reg[] = + { + {"etcam0_1_smmu0_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_as_smmu0_etcam0_1_rsp_cnt_reg[] = + { + {"smmu0_etcam0_1_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_as_as_hla_hash_p0_3_key_cnt_reg[] = + { + {"as_hla_hash_p0_3_key_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_as_as_hla_lpm_p0_key_cnt_reg[] = + { + {"as_hla_lpm_p0_key_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_as_alg_as_hash_p0_3_rsp_cnt_reg[] = + { + {"alg_as_hash_p0_3_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_as_alg_as_hash_p0_3_smf_rsp_cnt_reg[] = + { + {"alg_as_hash_p0_3_smf_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_as_alg_as_lpm_p0_rsp_cnt_reg[] = + { + {"alg_as_lpm_p0_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_as_alg_as_lpm_p0_3_smf_rsp_cnt_reg[] = + { + {"alg_as_lpm_p0_3_smf_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_as_as_pbu_key_cnt_reg[] = + { + {"as_pbu_key_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_as_pbu_se_dpi_rsp_dat_cnt_reg[] = + { + {"pbu_se_dpi_rsp_dat_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_as_as_etcam_ctrl_req0_cnt_reg[] = + { + {"as_etcam_ctrl_req0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_as_etcam_ctrl_as_index0_1_cnt_reg[] = + { + {"etcam_ctrl_as_index0_1_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_as_etcam_ctrl_as_hit0_1_cnt_reg[] = + { + {"etcam_ctrl_as_hit0_1_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_as_as_smmu0_req_cnt_reg[] = + { + {"as_smmu0_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_as_learn_hla_wr_cnt_reg[] = + { + {"learn_hla_wr_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_as_as_smmu1_req_cnt_reg[] = + { + {"as_smmu1_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_as_se_cfg_mac_dat_cnt_reg[] = + { + {"se_cfg_mac_dat_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_as_alg_as_hash_p0_3_fc_cnt_reg[] = + { + {"alg_as_hash_p0_3_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_as_alg_as_lpm_p0_fc_cnt_reg[] = + { + {"alg_as_lpm_p0_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_as_as_alg_hash_p0_3_fc_cnt_reg[] = + { + {"as_alg_hash_p0_3_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_as_as_alg_lpm_p0_fc_cnt_reg[] = + { + {"as_alg_lpm_p0_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_as_as_pbu_fc_cnt_reg[] = + { + {"as_pbu_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_as_pbu_se_dpi_key_fc_cnt_reg[] = + { + {"pbu_se_dpi_key_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_as_as_etcam_ctrl_fc0_1_cnt_reg[] = + { + {"as_etcam_ctrl_fc0_1_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_as_etcam_ctrl_as_fc0_1_cnt_reg[] = + { + {"etcam_ctrl_as_fc0_1_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_as_smmu0_as_mac_age_fc_cnt_reg[] = + { + {"smmu0_as_mac_age_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_as_alg_learn_fc_cnt_reg[] = + { + {"alg_learn_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_as_smmu1_as_fc_cnt_reg[] = + { + {"smmu1_as_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_as_cfg_se_mac_fc_cnt_reg[] = + { + {"cfg_se_mac_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_kschd_kschd_cpu_rdy_reg[] = + { + {"kschd_cpu_rdy", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_kschd_ppu0_ecc_bypass_read_reg[] = + { + {"ppu0_ecc_bypass_read", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_se_kschd_pbu_ecc_bypass_read_reg[] = + { + {"pbu_ecc_bypass_read", DPP_FIELD_FLAG_RW, 5, 6, 0x3f, 0x0}, + }; +DPP_FIELD_T g_se_kschd_smmu1_ecc_bypass_read_reg[] = + { + {"u3_smmu1_ecc_bypass_read", DPP_FIELD_FLAG_RO, 23, 6, 0x3f, 0x0}, + {"u2_smmu1_ecc_bypass_read", DPP_FIELD_FLAG_RO, 17, 6, 0x3f, 0x0}, + {"u1_smmu1_ecc_bypass_read", DPP_FIELD_FLAG_RO, 11, 6, 0x3f, 0x0}, + {"u0_smmu1_ecc_bypass_read", DPP_FIELD_FLAG_RW, 5, 6, 0x3f, 0x0}, + }; +DPP_FIELD_T g_se_kschd_ass_ecc_bypass_read_reg[] = + { + {"ass_ecc_bypass_read", DPP_FIELD_FLAG_RW, 5, 6, 0x3f, 0x0}, + }; +DPP_FIELD_T g_se_kschd_sdt_h_reg[] = + { + {"sdt_h", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_kschd_sdt_l_reg[] = + { + {"sdt_l", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_kschd_hash_key15_reg[] = + { + {"dma_en", DPP_FIELD_FLAG_RW, 25, 1, 0x0, 0x0}, + {"delete_en", DPP_FIELD_FLAG_RW, 24, 1, 0x0, 0x0}, + {"hash_key15", DPP_FIELD_FLAG_RW, 23, 24, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_kschd_hash_key14_reg[] = + { + {"hash_key14", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_kschd_hash_key13_reg[] = + { + {"hash_key13", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_kschd_hash_key12_reg[] = + { + {"hash_key12", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_kschd_hash_key11_reg[] = + { + {"hash_key11", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_kschd_hash_key10_reg[] = + { + {"hash_key10", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_kschd_hash_key9_reg[] = + { + {"hash_key9", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_kschd_hash_key8_reg[] = + { + {"hash_key8", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_kschd_hash_key7_reg[] = + { + {"hash_key7", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_kschd_hash_key6_reg[] = + { + {"hash_key6", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_kschd_hash_key5_reg[] = + { + {"hash_key5", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_kschd_hash_key4_reg[] = + { + {"hash_key4", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_kschd_hash_key3_reg[] = + { + {"hash_key3", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_kschd_hash_key2_reg[] = + { + {"hash_key2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_kschd_hash_key1_reg[] = + { + {"hash_key1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_kschd_hash_key0_reg[] = + { + {"hash_key0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_kschd_schd_int_0_en_reg[] = + { + {"port0_int_en", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_se_kschd_schd_int_0_mask_reg[] = + { + {"port0_int_mask", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_se_kschd_schd_int_1_en_reg[] = + { + {"port1_int_en", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_se_kschd_schd_int_1_mask_reg[] = + { + {"port1_int_mask", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_se_kschd_schd_int_2_en_reg[] = + { + {"port2_int_en", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_se_kschd_schd_int_2_mask_reg[] = + { + {"port2_int_mask", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_se_kschd_schd_int_3_en_reg[] = + { + {"port3_int_en", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_se_kschd_schd_int_3_mask_reg[] = + { + {"port3_int_mask", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_se_kschd_schd_int_4_en_reg[] = + { + {"port4_int_en", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_se_kschd_schd_int_4_mask_reg[] = + { + {"port4_int_mask", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_se_kschd_schd_int_0_status_reg[] = + { + {"port0_int_status", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_kschd_schd_int_1_status_reg[] = + { + {"port1_int_status", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_kschd_schd_int_2_status_reg[] = + { + {"port2_int_status", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_kschd_schd_int_3_status_reg[] = + { + {"port3_int_status", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_kschd_schd_int_4_status_reg[] = + { + {"port4_int_status", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_kschd_se_kschd_int_status_reg[] = + { + {"schd_int4_unmask_flag", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0}, + {"schd_int3_unmask_flag", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0}, + {"schd_int2_unmask_flag", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0}, + {"schd_int1_unmask_flag", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0}, + {"schd_int0_unmask_flag", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_kschd_debug_cnt_mode_reg[] = + { + {"cnt_rd_mode", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0}, + {"cnt_overflow_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_se_kschd_se_parser_kschd_key0_3_cnt_reg[] = + { + {"se_parser_kschd_key0_3_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_kschd_se_smmu1_key0_3_cnt_reg[] = + { + {"se_smmu1_key0_3_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_kschd_kschd_as_key0_cnt_reg[] = + { + {"kschd_as_key0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_kschd_kschd_as_key1_cnt_reg[] = + { + {"kschd_as_key1_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_kschd_kschd_as_key2_cnt_reg[] = + { + {"kschd_as_key2_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_kschd_kschd_as_key3_cnt_reg[] = + { + {"kschd_as_key3_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_kschd_kschd_as_key4_cnt_reg[] = + { + {"kschd_as_key4_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_kschd_kschd_as_key5_cnt_reg[] = + { + {"kschd_as_key5_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_kschd_kschd_as_key6_cnt_reg[] = + { + {"kschd_as_key6_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_kschd_kschd_as_key9_cnt_reg[] = + { + {"kschd_as_key9_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_kschd_kschd_se_parser_fc0_3_cnt_reg[] = + { + {"kschd_se_parser_fc0_3_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_kschd_smmu1_se_fc0_3_cnt_reg[] = + { + {"smmu1_se_fc0_3_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_kschd_as_kschd_fc_cnt0_reg[] = + { + {"as_kschd_fc_cnt0", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_kschd_as_kschd_fc_cnt1_reg[] = + { + {"as_kschd_fc_cnt1", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_kschd_as_kschd_fc_cnt2_reg[] = + { + {"as_kschd_fc_cnt2", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_kschd_as_kschd_fc_cnt3_reg[] = + { + {"as_kschd_fc_cnt3", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_kschd_as_kschd_fc_cnt4_reg[] = + { + {"as_kschd_fc_cnt4", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_kschd_as_kschd_fc_cnt5_reg[] = + { + {"as_kschd_fc_cnt5", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_kschd_as_kschd_fc_cnt6_reg[] = + { + {"as_kschd_fc_cnt6", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_kschd_as_kschd_fc_cnt9_reg[] = + { + {"as_kschd_fc_cnt9", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_rschd_rschd_hash_pful_cfg_reg[] = + { + {"rschd_hash_pful_cfg", DPP_FIELD_FLAG_RW, 31, 32, 0x00370037, 0x0}, + }; +DPP_FIELD_T g_se_rschd_rschd_hash_ept_cfg_reg[] = + { + {"rschd_hash_ept_cfg", DPP_FIELD_FLAG_RW, 31, 32, 0x00090009, 0x0}, + }; +DPP_FIELD_T g_se_rschd_rschd_pbu_pful_cfg_reg[] = + { + {"rschd_pbu_pful_cfg", DPP_FIELD_FLAG_RW, 31, 32, 0x002d002d, 0x0}, + }; +DPP_FIELD_T g_se_rschd_rschd_pbu_ept_cfg_reg[] = + { + {"rschd_pbu_ept_cfg", DPP_FIELD_FLAG_RW, 31, 32, 0x00130013, 0x0}, + }; +DPP_FIELD_T g_se_rschd_rschd_lpm_pful_cfg_reg[] = + { + {"rschd_lpm_pful_cfg", DPP_FIELD_FLAG_RW, 31, 32, 0x00240024, 0x0}, + }; +DPP_FIELD_T g_se_rschd_rschd_lpm_ept_cfg_reg[] = + { + {"rschd_lpm_ept_cfg", DPP_FIELD_FLAG_RW, 31, 32, 0x001c001c, 0x0}, + }; +DPP_FIELD_T g_se_rschd_rschd_etcam_pful_cfg_reg[] = + { + {"rschd_etcam_pful_cfg", DPP_FIELD_FLAG_RW, 31, 32, 0x00110011, 0x0}, + }; +DPP_FIELD_T g_se_rschd_rschd_etcam_ept_cfg_reg[] = + { + {"rschd_etcam_ept_cfg", DPP_FIELD_FLAG_RW, 31, 32, 0x002f002f, 0x0}, + }; +DPP_FIELD_T g_se_rschd_smmu0_wb_pful_cfg_reg[] = + { + {"smmu0_wb_pful_cfg", DPP_FIELD_FLAG_RW, 31, 32, 0x00330033, 0x0}, + }; +DPP_FIELD_T g_se_rschd_smmu0_wb_ept_cfg_reg[] = + { + {"smmu0_wb_ept_cfg", DPP_FIELD_FLAG_RW, 31, 32, 0x000d000d, 0x0}, + }; +DPP_FIELD_T g_se_rschd_smmu1_wb_pful_cfg_reg[] = + { + {"smmu1_wb_pful_cfg", DPP_FIELD_FLAG_RW, 31, 32, 0x003a003a, 0x0}, + }; +DPP_FIELD_T g_se_rschd_smmu1_wb_ept_cfg_reg[] = + { + {"smmu1_wb_ept_cfg", DPP_FIELD_FLAG_RW, 31, 32, 0x00060006, 0x0}, + }; +DPP_FIELD_T g_se_rschd_alg_wb_pful_cfg_reg[] = + { + {"alg_wb_pful_cfg", DPP_FIELD_FLAG_RW, 31, 32, 0x003a003a, 0x0}, + }; +DPP_FIELD_T g_se_rschd_alg_wb_ept_cfg_reg[] = + { + {"alg_wb_ept_cfg", DPP_FIELD_FLAG_RW, 31, 32, 0x00060006, 0x0}, + }; +DPP_FIELD_T g_se_rschd_wr_rsp_vld_en_reg[] = + { + {"wr_rsp_vld_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_se_rschd_nppu_wb_pful_cfg_reg[] = + { + {"nppu_wb_pful_cfg", DPP_FIELD_FLAG_RW, 31, 32, 0x00380038, 0x0}, + }; +DPP_FIELD_T g_se_rschd_nppu_wb_ept_cfg_reg[] = + { + {"nppu_wb_ept_cfg", DPP_FIELD_FLAG_RW, 31, 32, 0x00080008, 0x0}, + }; +DPP_FIELD_T g_se_rschd_port0_int_en_reg[] = + { + {"port0_int_en", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_se_rschd_port0_int_mask_reg[] = + { + {"port0_int_mask", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_se_rschd_port1_int_en_reg[] = + { + {"port1_int_en", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_se_rschd_port1_int_mask_reg[] = + { + {"port1_int_mask", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_se_rschd_port0_int_status_reg[] = + { + {"port0_int_status", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_rschd_port1_int_status_reg[] = + { + {"port1_int_status", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_rschd_se_rschd_int_status_reg[] = + { + {"port1_int_unmask_flag", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0}, + {"port0_int_unmask_flag", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_rschd_debug_cnt_mode_reg[] = + { + {"cnt_rd_mode", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0}, + {"cnt_overflow_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_se_rschd_se_ppu_mex0_5_rsp1_cnt_reg[] = + { + {"se_ppu_mex0_5_rsp1_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_rschd_as_rschd_rsp0_cnt_reg[] = + { + {"as_rschd_rsp0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_rschd_as_rschd_rsp1_cnt_reg[] = + { + {"as_rschd_rsp1_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_rschd_as_rschd_rsp2_cnt_reg[] = + { + {"as_rschd_rsp2_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_rschd_as_rschd_rsp3_cnt_reg[] = + { + {"as_rschd_rsp3_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_rschd_as_rschd_rsp4_cnt_reg[] = + { + {"as_rschd_rsp4_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_rschd_as_rschd_rsp5_cnt_reg[] = + { + {"as_rschd_rsp5_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_rschd_as_rschd_rsp6_cnt_reg[] = + { + {"as_rschd_rsp6_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_rschd_as_rschd_rsp9_cnt_reg[] = + { + {"as_rschd_rsp9_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_rschd_smmu1_se_rsp0_3_cnt_reg[] = + { + {"smmu1_se_rsp0_3_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_rschd_ppu_se_mex0_3_fc_cnt_reg[] = + { + {"ppu_se_mex0_3_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_rschd_rschd_as_fc_cnt0_reg[] = + { + {"rschd_as_fc_cnt0", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_rschd_rschd_as_fc_cnt1_reg[] = + { + {"rschd_as_fc_cnt1", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_rschd_rschd_as_fc_cnt2_reg[] = + { + {"rschd_as_fc_cnt2", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_rschd_rschd_as_fc_cnt3_reg[] = + { + {"rschd_as_fc_cnt3", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_rschd_rschd_as_fc_cnt4_reg[] = + { + {"rschd_as_fc_cnt4", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_rschd_rschd_as_fc_cnt5_reg[] = + { + {"rschd_as_fc_cnt5", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_rschd_rschd_as_fc_cnt6_reg[] = + { + {"rschd_as_fc_cnt6", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_rschd_rschd_as_fc_cnt9_reg[] = + { + {"rschd_as_fc_cnt9", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_rschd_se_smmu1_fc0_3_cnt_reg[] = + { + {"se_smmu1_fc0_3_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_rschd_smmu0_se_wr_done_cnt_reg[] = + { + {"smmu0_se_wr_done_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_rschd_se_smmu0_wr_done_fc_cnt_reg[] = + { + {"se_smmu0_wr_done_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_rschd_smmu1_se_wr_rsp_cnt_reg[] = + { + {"smmu1_se_wr_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_rschd_se_smmu1_wr_rsp_fc_cnt_reg[] = + { + {"se_smmu1_wr_rsp_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_rschd_alg_se_wr_rsp_cnt_reg[] = + { + {"alg_se_wr_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_rschd_se_alg_wr_rsp_fc_cnt_reg[] = + { + {"se_alg_wr_rsp_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_kschd_pful_cfg0_reg[] = + { + {"kschd_pful_assert0_1", DPP_FIELD_FLAG_RW, 27, 7, 0x18, 0x0}, + {"kschd_pful_negate0_1", DPP_FIELD_FLAG_RW, 20, 7, 0x18, 0x0}, + {"kschd_pful_assert0_0", DPP_FIELD_FLAG_RW, 13, 7, 0x20, 0x0}, + {"kschd_pful_negate0_0", DPP_FIELD_FLAG_RW, 6, 7, 0x20, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_kschd_pful_cfg1_reg[] = + { + {"kschd_pful_assert1_1", DPP_FIELD_FLAG_RW, 25, 7, 0x20, 0x0}, + {"kschd_pful_negate1_1", DPP_FIELD_FLAG_RW, 18, 7, 0x20, 0x0}, + {"kschd_pful_assert1_0", DPP_FIELD_FLAG_RW, 11, 6, 0x0c, 0x0}, + {"kschd_pful_negate1_0", DPP_FIELD_FLAG_RW, 5, 6, 0x0c, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl_pful1_cfg_reg[] = + { + {"ctrl_pful1_assert", DPP_FIELD_FLAG_RW, 7, 4, 0x3, 0x0}, + {"ctrl_pful1_negate", DPP_FIELD_FLAG_RW, 3, 4, 0x2, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl_pful2_cfg_reg[] = + { + {"ctrl_pful2_assert", DPP_FIELD_FLAG_RW, 9, 5, 0x0a, 0x0}, + {"ctrl_pful2_negate", DPP_FIELD_FLAG_RW, 4, 5, 0x08, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl_pful3_cfg_reg[] = + { + {"ctrl_pful3_assert", DPP_FIELD_FLAG_RW, 13, 7, 0x38, 0x0}, + {"ctrl_pful3_negate", DPP_FIELD_FLAG_RW, 6, 7, 0x36, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_rschd_pful_cfg_reg[] = + { + {"rschd_pful_assert", DPP_FIELD_FLAG_RW, 13, 7, 0x24, 0x0}, + {"rschd_pful_negate", DPP_FIELD_FLAG_RW, 6, 7, 0x24, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_rschd_ept_cfg_reg[] = + { + {"rschd_ept_assert", DPP_FIELD_FLAG_RW, 13, 7, 0x1c, 0x0}, + {"rschd_ept_negate", DPP_FIELD_FLAG_RW, 6, 7, 0x1c, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_alucmd_pful_cfg_reg[] = + { + {"alucmd_pful_assert", DPP_FIELD_FLAG_RW, 11, 6, 0x18, 0x0}, + {"alucmd_pful_negate", DPP_FIELD_FLAG_RW, 5, 6, 0x16, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_aluwr_pful_cfg_reg[] = + { + {"aluwr_pful_assert", DPP_FIELD_FLAG_RW, 7, 4, 0x5, 0x0}, + {"aluwr_pful_negate", DPP_FIELD_FLAG_RW, 3, 4, 0x4, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_wr_arb_pful_cfg0_reg[] = + { + {"wr_arb_pful0_assert", DPP_FIELD_FLAG_RW, 11, 6, 0x15, 0x0}, + {"wr_arb_pful0_negate", DPP_FIELD_FLAG_RW, 5, 6, 0x15, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_wr_arb_pful_cfg1_reg[] = + { + {"wr_arb_pful1_assert", DPP_FIELD_FLAG_RW, 15, 8, 0x64, 0x0}, + {"wr_arb_pful1_negate", DPP_FIELD_FLAG_RW, 7, 8, 0x64, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ord_pful_cfg_reg[] = + { + {"ord_pful_assert", DPP_FIELD_FLAG_RW, 13, 7, 0x2a, 0x0}, + {"ord_pful_negate", DPP_FIELD_FLAG_RW, 6, 7, 0x2a, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_cfg_dma_baddr_reg[] = + { + {"cfg_dma_baddr", DPP_FIELD_FLAG_RW, 18, 19, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_cfg_odma0_baddr_reg[] = + { + {"cfg_odma0_baddr", DPP_FIELD_FLAG_RW, 18, 19, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_cfg_odma1_baddr_reg[] = + { + {"cfg_odma1_baddr", DPP_FIELD_FLAG_RW, 18, 19, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_cfg_odma2_baddr_reg[] = + { + {"cfg_odma2_baddr", DPP_FIELD_FLAG_RW, 18, 19, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_cfg_odma_tdm_baddr_reg[] = + { + {"cfg_odma_tdm_baddr", DPP_FIELD_FLAG_RW, 18, 19, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_cfg_mcast_baddr_reg[] = + { + {"cfg_mcast_baddr", DPP_FIELD_FLAG_RW, 18, 19, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_cfg_lpm0_reg[] = + { + {"lpm0_rsp_mode", DPP_FIELD_FLAG_RW, 21, 3, 0x0, 0x0}, + {"lpm0_baddr", DPP_FIELD_FLAG_RW, 18, 19, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_cfg_lpm1_reg[] = + { + {"lpm1_rsp_mode", DPP_FIELD_FLAG_RW, 21, 3, 0x0, 0x0}, + {"lpm1_baddr", DPP_FIELD_FLAG_RW, 18, 19, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_cfg_lpm2_reg[] = + { + {"lpm2_rsp_mode", DPP_FIELD_FLAG_RW, 21, 3, 0x0, 0x0}, + {"lpm2_baddr", DPP_FIELD_FLAG_RW, 18, 19, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_cfg_lpm3_reg[] = + { + {"lpm3_rsp_mode", DPP_FIELD_FLAG_RW, 21, 3, 0x0, 0x0}, + {"lpm3_baddr", DPP_FIELD_FLAG_RW, 18, 19, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_cfg_lpm4_reg[] = + { + {"lpm4_rsp_mode", DPP_FIELD_FLAG_RW, 21, 3, 0x0, 0x0}, + {"lpm4_baddr", DPP_FIELD_FLAG_RW, 18, 19, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_cfg_lpm5_reg[] = + { + {"lpm5_rsp_mode", DPP_FIELD_FLAG_RW, 21, 3, 0x0, 0x0}, + {"lpm5_baddr", DPP_FIELD_FLAG_RW, 18, 19, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_cfg_lpm6_reg[] = + { + {"lpm6_rsp_mode", DPP_FIELD_FLAG_RW, 21, 3, 0x0, 0x0}, + {"lpm6_baddr", DPP_FIELD_FLAG_RW, 18, 19, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_cfg_lpm7_reg[] = + { + {"lpm7_rsp_mode", DPP_FIELD_FLAG_RW, 21, 3, 0x0, 0x0}, + {"lpm7_baddr", DPP_FIELD_FLAG_RW, 18, 19, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_debug_cnt_mode_reg[] = + { + {"cnt_rd_mode", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0}, + {"cnt_overflow_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_stat_overflow_mode_reg[] = + { + {"stat_overflow_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_init_en_cfg_tmp_reg[] = + { + {"init_en_cfg_tmp31", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, + {"init_en_cfg_tmp30", DPP_FIELD_FLAG_RW, 30, 1, 0x0, 0x0}, + {"init_en_cfg_tmp29", DPP_FIELD_FLAG_RW, 29, 1, 0x0, 0x0}, + {"init_en_cfg_tmp28", DPP_FIELD_FLAG_RW, 28, 1, 0x0, 0x0}, + {"init_en_cfg_tmp27", DPP_FIELD_FLAG_RW, 27, 1, 0x0, 0x0}, + {"init_en_cfg_tmp26", DPP_FIELD_FLAG_RW, 26, 1, 0x0, 0x0}, + {"init_en_cfg_tmp25", DPP_FIELD_FLAG_RW, 25, 1, 0x0, 0x0}, + {"init_en_cfg_tmp24", DPP_FIELD_FLAG_RW, 24, 1, 0x0, 0x0}, + {"init_en_cfg_tmp23", DPP_FIELD_FLAG_RW, 23, 1, 0x0, 0x0}, + {"init_en_cfg_tmp22", DPP_FIELD_FLAG_RW, 22, 1, 0x0, 0x0}, + {"init_en_cfg_tmp21", DPP_FIELD_FLAG_RW, 21, 1, 0x0, 0x0}, + {"init_en_cfg_tmp20", DPP_FIELD_FLAG_RW, 20, 1, 0x0, 0x0}, + {"init_en_cfg_tmp19", DPP_FIELD_FLAG_RW, 19, 1, 0x0, 0x0}, + {"init_en_cfg_tmp18", DPP_FIELD_FLAG_RW, 18, 1, 0x0, 0x0}, + {"init_en_cfg_tmp17", DPP_FIELD_FLAG_RW, 17, 1, 0x0, 0x0}, + {"init_en_cfg_tmp16", DPP_FIELD_FLAG_RW, 16, 1, 0x0, 0x0}, + {"init_en_cfg_tmp15", DPP_FIELD_FLAG_RW, 15, 1, 0x0, 0x0}, + {"init_en_cfg_tmp14", DPP_FIELD_FLAG_RW, 14, 1, 0x0, 0x0}, + {"init_en_cfg_tmp13", DPP_FIELD_FLAG_RW, 13, 1, 0x0, 0x0}, + {"init_en_cfg_tmp12", DPP_FIELD_FLAG_RW, 12, 1, 0x0, 0x0}, + {"init_en_cfg_tmp11", DPP_FIELD_FLAG_RW, 11, 1, 0x0, 0x0}, + {"init_en_cfg_tmp10", DPP_FIELD_FLAG_RW, 10, 1, 0x0, 0x0}, + {"init_en_cfg_tmp9", DPP_FIELD_FLAG_RW, 9, 1, 0x0, 0x0}, + {"init_en_cfg_tmp8", DPP_FIELD_FLAG_RW, 8, 1, 0x0, 0x0}, + {"init_en_cfg_tmp7", DPP_FIELD_FLAG_RW, 7, 1, 0x0, 0x0}, + {"init_en_cfg_tmp6", DPP_FIELD_FLAG_RW, 6, 1, 0x0, 0x0}, + {"init_en_cfg_tmp5", DPP_FIELD_FLAG_RW, 5, 1, 0x0, 0x0}, + {"init_en_cfg_tmp4", DPP_FIELD_FLAG_RW, 4, 1, 0x0, 0x0}, + {"init_en_cfg_tmp3", DPP_FIELD_FLAG_RW, 3, 1, 0x0, 0x0}, + {"init_en_cfg_tmp2", DPP_FIELD_FLAG_RW, 2, 1, 0x0, 0x0}, + {"init_en_cfg_tmp1", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0}, + {"init_en_cfg_tmp0", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int_unmask_flag_reg[] = + { + {"smmu0_int0_31_unmask_flag", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int0_en_reg[] = + { + {"smmu0_int0_en31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0}, + {"smmu0_int0_en30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0}, + {"smmu0_int0_en29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0}, + {"smmu0_int0_en28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0}, + {"smmu0_int0_en27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0}, + {"smmu0_int0_en26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0}, + {"smmu0_int0_en25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0}, + {"smmu0_int0_en24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0}, + {"smmu0_int0_en23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0}, + {"smmu0_int0_en22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0}, + {"smmu0_int0_en21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0}, + {"smmu0_int0_en20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"smmu0_int0_en19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0}, + {"smmu0_int0_en18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + {"smmu0_int0_en17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0}, + {"smmu0_int0_en16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"smmu0_int0_en15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"smmu0_int0_en14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"smmu0_int0_en13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"smmu0_int0_en12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"smmu0_int0_en11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"smmu0_int0_en10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"smmu0_int0_en9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"smmu0_int0_en8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"smmu0_int0_en7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"smmu0_int0_en6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"smmu0_int0_en5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"smmu0_int0_en4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"smmu0_int0_en3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"smmu0_int0_en2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"smmu0_int0_en1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"smmu0_int0_en0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int0_mask_reg[] = + { + {"smmu0_int0_mask31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0}, + {"smmu0_int0_mask30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0}, + {"smmu0_int0_mask29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0}, + {"smmu0_int0_mask28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0}, + {"smmu0_int0_mask27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0}, + {"smmu0_int0_mask26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0}, + {"smmu0_int0_mask25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0}, + {"smmu0_int0_mask24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0}, + {"smmu0_int0_mask23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0}, + {"smmu0_int0_mask22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0}, + {"smmu0_int0_mask21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0}, + {"smmu0_int0_mask20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"smmu0_int0_mask19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0}, + {"smmu0_int0_mask18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + {"smmu0_int0_mask17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0}, + {"smmu0_int0_mask16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"smmu0_int0_mask15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"smmu0_int0_mask14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"smmu0_int0_mask13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"smmu0_int0_mask12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"smmu0_int0_mask11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"smmu0_int0_mask10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"smmu0_int0_mask9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"smmu0_int0_mask8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"smmu0_int0_mask7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"smmu0_int0_mask6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"smmu0_int0_mask5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"smmu0_int0_mask4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"smmu0_int0_mask3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"smmu0_int0_mask2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"smmu0_int0_mask1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"smmu0_int0_mask0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int0_status_reg[] = + { + {"smmu0_int0_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"smmu0_int0_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"smmu0_int0_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"smmu0_int0_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"smmu0_int0_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"smmu0_int0_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"smmu0_int0_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"smmu0_int0_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"smmu0_int0_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"smmu0_int0_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"smmu0_int0_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"smmu0_int0_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"smmu0_int0_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"smmu0_int0_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"smmu0_int0_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"smmu0_int0_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"smmu0_int0_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"smmu0_int0_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"smmu0_int0_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"smmu0_int0_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"smmu0_int0_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"smmu0_int0_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"smmu0_int0_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"smmu0_int0_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"smmu0_int0_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"smmu0_int0_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"smmu0_int0_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"smmu0_int0_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"smmu0_int0_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"smmu0_int0_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"smmu0_int0_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"smmu0_int0_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int1_en_reg[] = + { + {"smmu0_int1_en31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0}, + {"smmu0_int1_en30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0}, + {"smmu0_int1_en29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0}, + {"smmu0_int1_en28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0}, + {"smmu0_int1_en27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0}, + {"smmu0_int1_en26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0}, + {"smmu0_int1_en25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0}, + {"smmu0_int1_en24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0}, + {"smmu0_int1_en23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0}, + {"smmu0_int1_en22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0}, + {"smmu0_int1_en21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0}, + {"smmu0_int1_en20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"smmu0_int1_en19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0}, + {"smmu0_int1_en18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + {"smmu0_int1_en17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0}, + {"smmu0_int1_en16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"smmu0_int1_en15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"smmu0_int1_en14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"smmu0_int1_en13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"smmu0_int1_en12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"smmu0_int1_en11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"smmu0_int1_en10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"smmu0_int1_en9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"smmu0_int1_en8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"smmu0_int1_en7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"smmu0_int1_en6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"smmu0_int1_en5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"smmu0_int1_en4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"smmu0_int1_en3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"smmu0_int1_en2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"smmu0_int1_en1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"smmu0_int1_en0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int1_mask_reg[] = + { + {"smmu0_int1_mask31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0}, + {"smmu0_int1_mask30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0}, + {"smmu0_int1_mask29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0}, + {"smmu0_int1_mask28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0}, + {"smmu0_int1_mask27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0}, + {"smmu0_int1_mask26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0}, + {"smmu0_int1_mask25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0}, + {"smmu0_int1_mask24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0}, + {"smmu0_int1_mask23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0}, + {"smmu0_int1_mask22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0}, + {"smmu0_int1_mask21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0}, + {"smmu0_int1_mask20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"smmu0_int1_mask19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0}, + {"smmu0_int1_mask18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + {"smmu0_int1_mask17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0}, + {"smmu0_int1_mask16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"smmu0_int1_mask15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"smmu0_int1_mask14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"smmu0_int1_mask13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"smmu0_int1_mask12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"smmu0_int1_mask11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"smmu0_int1_mask10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"smmu0_int1_mask9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"smmu0_int1_mask8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"smmu0_int1_mask7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"smmu0_int1_mask6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"smmu0_int1_mask5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"smmu0_int1_mask4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"smmu0_int1_mask3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"smmu0_int1_mask2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"smmu0_int1_mask1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"smmu0_int1_mask0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int1_status_reg[] = + { + {"smmu0_int1_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"smmu0_int1_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"smmu0_int1_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"smmu0_int1_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"smmu0_int1_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"smmu0_int1_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"smmu0_int1_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"smmu0_int1_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"smmu0_int1_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"smmu0_int1_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"smmu0_int1_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"smmu0_int1_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"smmu0_int1_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"smmu0_int1_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"smmu0_int1_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"smmu0_int1_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"smmu0_int1_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"smmu0_int1_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"smmu0_int1_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"smmu0_int1_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"smmu0_int1_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"smmu0_int1_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"smmu0_int1_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"smmu0_int1_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"smmu0_int1_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"smmu0_int1_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"smmu0_int1_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"smmu0_int1_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"smmu0_int1_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"smmu0_int1_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"smmu0_int1_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"smmu0_int1_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int2_en_reg[] = + { + {"smmu0_int2_en31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0}, + {"smmu0_int2_en30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0}, + {"smmu0_int2_en29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0}, + {"smmu0_int2_en28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0}, + {"smmu0_int2_en27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0}, + {"smmu0_int2_en26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0}, + {"smmu0_int2_en25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0}, + {"smmu0_int2_en24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0}, + {"smmu0_int2_en23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0}, + {"smmu0_int2_en22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0}, + {"smmu0_int2_en21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0}, + {"smmu0_int2_en20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"smmu0_int2_en19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0}, + {"smmu0_int2_en18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + {"smmu0_int2_en17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0}, + {"smmu0_int2_en16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"smmu0_int2_en15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"smmu0_int2_en14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"smmu0_int2_en13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"smmu0_int2_en12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"smmu0_int2_en11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"smmu0_int2_en10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"smmu0_int2_en9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"smmu0_int2_en8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"smmu0_int2_en7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"smmu0_int2_en6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"smmu0_int2_en5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"smmu0_int2_en4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"smmu0_int2_en3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"smmu0_int2_en2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"smmu0_int2_en1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"smmu0_int2_en0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int2_mask_reg[] = + { + {"smmu0_int2_mask31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0}, + {"smmu0_int2_mask30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0}, + {"smmu0_int2_mask29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0}, + {"smmu0_int2_mask28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0}, + {"smmu0_int2_mask27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0}, + {"smmu0_int2_mask26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0}, + {"smmu0_int2_mask25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0}, + {"smmu0_int2_mask24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0}, + {"smmu0_int2_mask23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0}, + {"smmu0_int2_mask22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0}, + {"smmu0_int2_mask21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0}, + {"smmu0_int2_mask20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"smmu0_int2_mask19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0}, + {"smmu0_int2_mask18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + {"smmu0_int2_mask17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0}, + {"smmu0_int2_mask16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"smmu0_int2_mask15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"smmu0_int2_mask14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"smmu0_int2_mask13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"smmu0_int2_mask12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"smmu0_int2_mask11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"smmu0_int2_mask10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"smmu0_int2_mask9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"smmu0_int2_mask8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"smmu0_int2_mask7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"smmu0_int2_mask6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"smmu0_int2_mask5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"smmu0_int2_mask4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"smmu0_int2_mask3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"smmu0_int2_mask2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"smmu0_int2_mask1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"smmu0_int2_mask0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int2_status_reg[] = + { + {"smmu0_int2_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"smmu0_int2_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"smmu0_int2_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"smmu0_int2_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"smmu0_int2_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"smmu0_int2_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"smmu0_int2_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"smmu0_int2_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"smmu0_int2_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"smmu0_int2_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"smmu0_int2_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"smmu0_int2_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"smmu0_int2_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"smmu0_int2_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"smmu0_int2_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"smmu0_int2_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"smmu0_int2_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"smmu0_int2_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"smmu0_int2_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"smmu0_int2_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"smmu0_int2_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"smmu0_int2_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"smmu0_int2_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"smmu0_int2_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"smmu0_int2_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"smmu0_int2_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"smmu0_int2_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"smmu0_int2_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"smmu0_int2_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"smmu0_int2_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"smmu0_int2_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"smmu0_int2_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int3_en_reg[] = + { + {"smmu0_int3_en31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0}, + {"smmu0_int3_en30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0}, + {"smmu0_int3_en29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0}, + {"smmu0_int3_en28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0}, + {"smmu0_int3_en27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0}, + {"smmu0_int3_en26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0}, + {"smmu0_int3_en25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0}, + {"smmu0_int3_en24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0}, + {"smmu0_int3_en23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0}, + {"smmu0_int3_en22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0}, + {"smmu0_int3_en21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0}, + {"smmu0_int3_en20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"smmu0_int3_en19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0}, + {"smmu0_int3_en18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + {"smmu0_int3_en17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0}, + {"smmu0_int3_en16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"smmu0_int3_en15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"smmu0_int3_en14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"smmu0_int3_en13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"smmu0_int3_en12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"smmu0_int3_en11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"smmu0_int3_en10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"smmu0_int3_en9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"smmu0_int3_en8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"smmu0_int3_en7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"smmu0_int3_en6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"smmu0_int3_en5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"smmu0_int3_en4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"smmu0_int3_en3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"smmu0_int3_en2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"smmu0_int3_en1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"smmu0_int3_en0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int3_mask_reg[] = + { + {"smmu0_int3_mask31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0}, + {"smmu0_int3_mask30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0}, + {"smmu0_int3_mask29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0}, + {"smmu0_int3_mask28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0}, + {"smmu0_int3_mask27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0}, + {"smmu0_int3_mask26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0}, + {"smmu0_int3_mask25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0}, + {"smmu0_int3_mask24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0}, + {"smmu0_int3_mask23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0}, + {"smmu0_int3_mask22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0}, + {"smmu0_int3_mask21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0}, + {"smmu0_int3_mask20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"smmu0_int3_mask19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0}, + {"smmu0_int3_mask18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + {"smmu0_int3_mask17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0}, + {"smmu0_int3_mask16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"smmu0_int3_mask15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"smmu0_int3_mask14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"smmu0_int3_mask13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"smmu0_int3_mask12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"smmu0_int3_mask11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"smmu0_int3_mask10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"smmu0_int3_mask9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"smmu0_int3_mask8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"smmu0_int3_mask7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"smmu0_int3_mask6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"smmu0_int3_mask5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"smmu0_int3_mask4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"smmu0_int3_mask3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"smmu0_int3_mask2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"smmu0_int3_mask1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"smmu0_int3_mask0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int3_status_reg[] = + { + {"smmu0_int3_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"smmu0_int3_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"smmu0_int3_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"smmu0_int3_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"smmu0_int3_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"smmu0_int3_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"smmu0_int3_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"smmu0_int3_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"smmu0_int3_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"smmu0_int3_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"smmu0_int3_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"smmu0_int3_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"smmu0_int3_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"smmu0_int3_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"smmu0_int3_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"smmu0_int3_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"smmu0_int3_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"smmu0_int3_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"smmu0_int3_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"smmu0_int3_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"smmu0_int3_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"smmu0_int3_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"smmu0_int3_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"smmu0_int3_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"smmu0_int3_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"smmu0_int3_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"smmu0_int3_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"smmu0_int3_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"smmu0_int3_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"smmu0_int3_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"smmu0_int3_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"smmu0_int3_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int4_en_reg[] = + { + {"smmu0_int4_en31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0}, + {"smmu0_int4_en30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0}, + {"smmu0_int4_en29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0}, + {"smmu0_int4_en28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0}, + {"smmu0_int4_en27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0}, + {"smmu0_int4_en26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0}, + {"smmu0_int4_en25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0}, + {"smmu0_int4_en24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0}, + {"smmu0_int4_en23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0}, + {"smmu0_int4_en22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0}, + {"smmu0_int4_en21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0}, + {"smmu0_int4_en20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"smmu0_int4_en19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0}, + {"smmu0_int4_en18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + {"smmu0_int4_en17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0}, + {"smmu0_int4_en16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"smmu0_int4_en15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"smmu0_int4_en14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"smmu0_int4_en13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"smmu0_int4_en12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"smmu0_int4_en11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"smmu0_int4_en10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"smmu0_int4_en9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"smmu0_int4_en8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"smmu0_int4_en7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"smmu0_int4_en6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"smmu0_int4_en5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"smmu0_int4_en4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"smmu0_int4_en3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"smmu0_int4_en2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"smmu0_int4_en1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"smmu0_int4_en0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int4_mask_reg[] = + { + {"smmu0_int4_mask31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0}, + {"smmu0_int4_mask30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0}, + {"smmu0_int4_mask29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0}, + {"smmu0_int4_mask28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0}, + {"smmu0_int4_mask27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0}, + {"smmu0_int4_mask26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0}, + {"smmu0_int4_mask25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0}, + {"smmu0_int4_mask24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0}, + {"smmu0_int4_mask23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0}, + {"smmu0_int4_mask22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0}, + {"smmu0_int4_mask21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0}, + {"smmu0_int4_mask20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"smmu0_int4_mask19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0}, + {"smmu0_int4_mask18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + {"smmu0_int4_mask17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0}, + {"smmu0_int4_mask16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"smmu0_int4_mask15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"smmu0_int4_mask14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"smmu0_int4_mask13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"smmu0_int4_mask12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"smmu0_int4_mask11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"smmu0_int4_mask10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"smmu0_int4_mask9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"smmu0_int4_mask8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"smmu0_int4_mask7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"smmu0_int4_mask6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"smmu0_int4_mask5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"smmu0_int4_mask4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"smmu0_int4_mask3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"smmu0_int4_mask2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"smmu0_int4_mask1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"smmu0_int4_mask0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int4_status_reg[] = + { + {"smmu0_int4_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"smmu0_int4_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"smmu0_int4_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"smmu0_int4_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"smmu0_int4_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"smmu0_int4_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"smmu0_int4_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"smmu0_int4_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"smmu0_int4_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"smmu0_int4_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"smmu0_int4_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"smmu0_int4_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"smmu0_int4_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"smmu0_int4_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"smmu0_int4_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"smmu0_int4_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"smmu0_int4_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"smmu0_int4_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"smmu0_int4_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"smmu0_int4_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"smmu0_int4_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"smmu0_int4_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"smmu0_int4_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"smmu0_int4_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"smmu0_int4_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"smmu0_int4_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"smmu0_int4_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"smmu0_int4_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"smmu0_int4_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"smmu0_int4_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"smmu0_int4_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"smmu0_int4_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int5_en_reg[] = + { + {"smmu0_int5_en31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0}, + {"smmu0_int5_en30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0}, + {"smmu0_int5_en29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0}, + {"smmu0_int5_en28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0}, + {"smmu0_int5_en27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0}, + {"smmu0_int5_en26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0}, + {"smmu0_int5_en25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0}, + {"smmu0_int5_en24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0}, + {"smmu0_int5_en23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0}, + {"smmu0_int5_en22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0}, + {"smmu0_int5_en21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0}, + {"smmu0_int5_en20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"smmu0_int5_en19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0}, + {"smmu0_int5_en18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + {"smmu0_int5_en17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0}, + {"smmu0_int5_en16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"smmu0_int5_en15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"smmu0_int5_en14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"smmu0_int5_en13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"smmu0_int5_en12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"smmu0_int5_en11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"smmu0_int5_en10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"smmu0_int5_en9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"smmu0_int5_en8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"smmu0_int5_en7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"smmu0_int5_en6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"smmu0_int5_en5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"smmu0_int5_en4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"smmu0_int5_en3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"smmu0_int5_en2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"smmu0_int5_en1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"smmu0_int5_en0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int5_mask_reg[] = + { + {"smmu0_int5_mask31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0}, + {"smmu0_int5_mask30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0}, + {"smmu0_int5_mask29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0}, + {"smmu0_int5_mask28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0}, + {"smmu0_int5_mask27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0}, + {"smmu0_int5_mask26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0}, + {"smmu0_int5_mask25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0}, + {"smmu0_int5_mask24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0}, + {"smmu0_int5_mask23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0}, + {"smmu0_int5_mask22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0}, + {"smmu0_int5_mask21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0}, + {"smmu0_int5_mask20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"smmu0_int5_mask19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0}, + {"smmu0_int5_mask18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + {"smmu0_int5_mask17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0}, + {"smmu0_int5_mask16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"smmu0_int5_mask15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"smmu0_int5_mask14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"smmu0_int5_mask13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"smmu0_int5_mask12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"smmu0_int5_mask11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"smmu0_int5_mask10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"smmu0_int5_mask9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"smmu0_int5_mask8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"smmu0_int5_mask7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"smmu0_int5_mask6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"smmu0_int5_mask5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"smmu0_int5_mask4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"smmu0_int5_mask3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"smmu0_int5_mask2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"smmu0_int5_mask1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"smmu0_int5_mask0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int5_status_reg[] = + { + {"smmu0_int5_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"smmu0_int5_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"smmu0_int5_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"smmu0_int5_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"smmu0_int5_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"smmu0_int5_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"smmu0_int5_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"smmu0_int5_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"smmu0_int5_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"smmu0_int5_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"smmu0_int5_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"smmu0_int5_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"smmu0_int5_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"smmu0_int5_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"smmu0_int5_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"smmu0_int5_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"smmu0_int5_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"smmu0_int5_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"smmu0_int5_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"smmu0_int5_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"smmu0_int5_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"smmu0_int5_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"smmu0_int5_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"smmu0_int5_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"smmu0_int5_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"smmu0_int5_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"smmu0_int5_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"smmu0_int5_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"smmu0_int5_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"smmu0_int5_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"smmu0_int5_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"smmu0_int5_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int6_en_reg[] = + { + {"smmu0_int6_en31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0}, + {"smmu0_int6_en30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0}, + {"smmu0_int6_en29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0}, + {"smmu0_int6_en28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0}, + {"smmu0_int6_en27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0}, + {"smmu0_int6_en26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0}, + {"smmu0_int6_en25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0}, + {"smmu0_int6_en24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0}, + {"smmu0_int6_en23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0}, + {"smmu0_int6_en22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0}, + {"smmu0_int6_en21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0}, + {"smmu0_int6_en20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"smmu0_int6_en19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0}, + {"smmu0_int6_en18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + {"smmu0_int6_en17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0}, + {"smmu0_int6_en16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"smmu0_int6_en15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"smmu0_int6_en14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"smmu0_int6_en13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"smmu0_int6_en12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"smmu0_int6_en11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"smmu0_int6_en10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"smmu0_int6_en9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"smmu0_int6_en8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"smmu0_int6_en7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"smmu0_int6_en6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"smmu0_int6_en5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"smmu0_int6_en4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"smmu0_int6_en3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"smmu0_int6_en2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"smmu0_int6_en1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"smmu0_int6_en0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int6_mask_reg[] = + { + {"smmu0_int6_mask31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0}, + {"smmu0_int6_mask30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0}, + {"smmu0_int6_mask29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0}, + {"smmu0_int6_mask28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0}, + {"smmu0_int6_mask27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0}, + {"smmu0_int6_mask26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0}, + {"smmu0_int6_mask25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0}, + {"smmu0_int6_mask24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0}, + {"smmu0_int6_mask23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0}, + {"smmu0_int6_mask22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0}, + {"smmu0_int6_mask21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0}, + {"smmu0_int6_mask20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"smmu0_int6_mask19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0}, + {"smmu0_int6_mask18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + {"smmu0_int6_mask17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0}, + {"smmu0_int6_mask16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"smmu0_int6_mask15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"smmu0_int6_mask14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"smmu0_int6_mask13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"smmu0_int6_mask12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"smmu0_int6_mask11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"smmu0_int6_mask10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"smmu0_int6_mask9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"smmu0_int6_mask8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"smmu0_int6_mask7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"smmu0_int6_mask6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"smmu0_int6_mask5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"smmu0_int6_mask4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"smmu0_int6_mask3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"smmu0_int6_mask2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"smmu0_int6_mask1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"smmu0_int6_mask0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int6_status_reg[] = + { + {"smmu0_int6_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"smmu0_int6_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"smmu0_int6_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"smmu0_int6_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"smmu0_int6_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"smmu0_int6_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"smmu0_int6_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"smmu0_int6_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"smmu0_int6_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"smmu0_int6_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"smmu0_int6_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"smmu0_int6_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"smmu0_int6_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"smmu0_int6_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"smmu0_int6_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"smmu0_int6_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"smmu0_int6_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"smmu0_int6_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"smmu0_int6_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"smmu0_int6_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"smmu0_int6_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"smmu0_int6_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"smmu0_int6_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"smmu0_int6_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"smmu0_int6_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"smmu0_int6_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"smmu0_int6_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"smmu0_int6_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"smmu0_int6_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"smmu0_int6_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"smmu0_int6_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"smmu0_int6_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int7_en_reg[] = + { + {"smmu0_int7_en31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0}, + {"smmu0_int7_en30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0}, + {"smmu0_int7_en29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0}, + {"smmu0_int7_en28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0}, + {"smmu0_int7_en27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0}, + {"smmu0_int7_en26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0}, + {"smmu0_int7_en25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0}, + {"smmu0_int7_en24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0}, + {"smmu0_int7_en23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0}, + {"smmu0_int7_en22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0}, + {"smmu0_int7_en21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0}, + {"smmu0_int7_en20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"smmu0_int7_en19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0}, + {"smmu0_int7_en18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + {"smmu0_int7_en17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0}, + {"smmu0_int7_en16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"smmu0_int7_en15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"smmu0_int7_en14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"smmu0_int7_en13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"smmu0_int7_en12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"smmu0_int7_en11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"smmu0_int7_en10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"smmu0_int7_en9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"smmu0_int7_en8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"smmu0_int7_en7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"smmu0_int7_en6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"smmu0_int7_en5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"smmu0_int7_en4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"smmu0_int7_en3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"smmu0_int7_en2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"smmu0_int7_en1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"smmu0_int7_en0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int7_mask_reg[] = + { + {"smmu0_int7_mask31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0}, + {"smmu0_int7_mask30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0}, + {"smmu0_int7_mask29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0}, + {"smmu0_int7_mask28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0}, + {"smmu0_int7_mask27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0}, + {"smmu0_int7_mask26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0}, + {"smmu0_int7_mask25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0}, + {"smmu0_int7_mask24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0}, + {"smmu0_int7_mask23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0}, + {"smmu0_int7_mask22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0}, + {"smmu0_int7_mask21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0}, + {"smmu0_int7_mask20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"smmu0_int7_mask19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0}, + {"smmu0_int7_mask18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + {"smmu0_int7_mask17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0}, + {"smmu0_int7_mask16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"smmu0_int7_mask15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"smmu0_int7_mask14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"smmu0_int7_mask13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"smmu0_int7_mask12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"smmu0_int7_mask11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"smmu0_int7_mask10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"smmu0_int7_mask9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"smmu0_int7_mask8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"smmu0_int7_mask7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"smmu0_int7_mask6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"smmu0_int7_mask5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"smmu0_int7_mask4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"smmu0_int7_mask3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"smmu0_int7_mask2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"smmu0_int7_mask1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"smmu0_int7_mask0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int7_status_reg[] = + { + {"smmu0_int7_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"smmu0_int7_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"smmu0_int7_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"smmu0_int7_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"smmu0_int7_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"smmu0_int7_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"smmu0_int7_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"smmu0_int7_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"smmu0_int7_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"smmu0_int7_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"smmu0_int7_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"smmu0_int7_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"smmu0_int7_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"smmu0_int7_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"smmu0_int7_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"smmu0_int7_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"smmu0_int7_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"smmu0_int7_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"smmu0_int7_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"smmu0_int7_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"smmu0_int7_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"smmu0_int7_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"smmu0_int7_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"smmu0_int7_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"smmu0_int7_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"smmu0_int7_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"smmu0_int7_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"smmu0_int7_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"smmu0_int7_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"smmu0_int7_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"smmu0_int7_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"smmu0_int7_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int8_en_reg[] = + { + {"smmu0_int8_en31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0}, + {"smmu0_int8_en30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0}, + {"smmu0_int8_en29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0}, + {"smmu0_int8_en28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0}, + {"smmu0_int8_en27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0}, + {"smmu0_int8_en26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0}, + {"smmu0_int8_en25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0}, + {"smmu0_int8_en24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0}, + {"smmu0_int8_en23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0}, + {"smmu0_int8_en22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0}, + {"smmu0_int8_en21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0}, + {"smmu0_int8_en20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"smmu0_int8_en19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0}, + {"smmu0_int8_en18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + {"smmu0_int8_en17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0}, + {"smmu0_int8_en16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"smmu0_int8_en15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"smmu0_int8_en14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"smmu0_int8_en13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"smmu0_int8_en12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"smmu0_int8_en11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"smmu0_int8_en10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"smmu0_int8_en9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"smmu0_int8_en8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"smmu0_int8_en7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"smmu0_int8_en6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"smmu0_int8_en5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"smmu0_int8_en4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"smmu0_int8_en3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"smmu0_int8_en2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"smmu0_int8_en1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"smmu0_int8_en0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int8_mask_reg[] = + { + {"smmu0_int8_mask31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0}, + {"smmu0_int8_mask30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0}, + {"smmu0_int8_mask29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0}, + {"smmu0_int8_mask28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0}, + {"smmu0_int8_mask27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0}, + {"smmu0_int8_mask26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0}, + {"smmu0_int8_mask25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0}, + {"smmu0_int8_mask24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0}, + {"smmu0_int8_mask23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0}, + {"smmu0_int8_mask22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0}, + {"smmu0_int8_mask21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0}, + {"smmu0_int8_mask20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"smmu0_int8_mask19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0}, + {"smmu0_int8_mask18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + {"smmu0_int8_mask17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0}, + {"smmu0_int8_mask16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"smmu0_int8_mask15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"smmu0_int8_mask14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"smmu0_int8_mask13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"smmu0_int8_mask12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"smmu0_int8_mask11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"smmu0_int8_mask10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"smmu0_int8_mask9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"smmu0_int8_mask8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"smmu0_int8_mask7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"smmu0_int8_mask6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"smmu0_int8_mask5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"smmu0_int8_mask4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"smmu0_int8_mask3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"smmu0_int8_mask2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"smmu0_int8_mask1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"smmu0_int8_mask0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int8_status_reg[] = + { + {"smmu0_int8_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"smmu0_int8_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"smmu0_int8_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"smmu0_int8_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"smmu0_int8_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"smmu0_int8_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"smmu0_int8_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"smmu0_int8_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"smmu0_int8_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"smmu0_int8_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"smmu0_int8_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"smmu0_int8_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"smmu0_int8_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"smmu0_int8_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"smmu0_int8_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"smmu0_int8_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"smmu0_int8_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"smmu0_int8_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"smmu0_int8_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"smmu0_int8_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"smmu0_int8_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"smmu0_int8_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"smmu0_int8_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"smmu0_int8_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"smmu0_int8_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"smmu0_int8_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"smmu0_int8_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"smmu0_int8_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"smmu0_int8_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"smmu0_int8_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"smmu0_int8_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"smmu0_int8_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int9_en_reg[] = + { + {"smmu0_int8_en31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0}, + {"smmu0_int8_en30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0}, + {"smmu0_int8_en29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0}, + {"smmu0_int8_en28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0}, + {"smmu0_int8_en27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0}, + {"smmu0_int8_en26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0}, + {"smmu0_int8_en25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0}, + {"smmu0_int8_en24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0}, + {"smmu0_int8_en23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0}, + {"smmu0_int8_en22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0}, + {"smmu0_int8_en21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0}, + {"smmu0_int8_en20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"smmu0_int9_en19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0}, + {"smmu0_int9_en18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + {"smmu0_int9_en17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0}, + {"smmu0_int9_en16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"smmu0_int9_en15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"smmu0_int9_en14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"smmu0_int9_en13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"smmu0_int9_en12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"smmu0_int9_en11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"smmu0_int9_en10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"smmu0_int9_en9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"smmu0_int9_en8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"smmu0_int9_en7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"smmu0_int9_en6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"smmu0_int9_en5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"smmu0_int9_en4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"smmu0_int9_en3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"smmu0_int9_en2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"smmu0_int9_en1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"smmu0_int9_en0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int9_mask_reg[] = + { + {"smmu0_int9_mask0_31", DPP_FIELD_FLAG_RW, 31, 32, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int9_status_reg[] = + { + {"smmu0_int9_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int10_en_reg[] = + { + {"smmu0_int10_en31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0}, + {"smmu0_int10_en30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0}, + {"smmu0_int10_en29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0}, + {"smmu0_int10_en28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0}, + {"smmu0_int10_en27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0}, + {"smmu0_int10_en26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0}, + {"smmu0_int10_en25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0}, + {"smmu0_int10_en24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0}, + {"smmu0_int10_en23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0}, + {"smmu0_int10_en22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0}, + {"smmu0_int10_en21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0}, + {"smmu0_int10_en20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"smmu0_int10_en19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0}, + {"smmu0_int10_en18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + {"smmu0_int10_en17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0}, + {"smmu0_int10_en16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"smmu0_int10_en15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"smmu0_int10_en14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"smmu0_int10_en13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"smmu0_int10_en12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"smmu0_int10_en11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"smmu0_int10_en10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"smmu0_int10_en9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"smmu0_int10_en8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"smmu0_int10_en7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"smmu0_int10_en6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"smmu0_int10_en5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"smmu0_int10_en4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"smmu0_int10_en3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"smmu0_int10_en2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"smmu0_int10_en1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"smmu0_int10_en0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int10_mask_reg[] = + { + {"smmu0_int10_mask0_31", DPP_FIELD_FLAG_RW, 31, 32, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int10_status_reg[] = + { + {"smmu0_int10_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int11_en_reg[] = + { + {"smmu0_int11_en0_31", DPP_FIELD_FLAG_RW, 31, 32, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int11_mask_reg[] = + { + {"smmu0_int11_mask0_31", DPP_FIELD_FLAG_RW, 31, 32, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int11_status_reg[] = + { + {"smmu0_int11_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int12_en_reg[] = + { + {"smmu0_int12_en0_31", DPP_FIELD_FLAG_RW, 31, 32, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int12_mask_reg[] = + { + {"smmu0_int12_mask0_31", DPP_FIELD_FLAG_RW, 31, 32, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int12_status_reg[] = + { + {"smmu0_int12_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int13_en_reg[] = + { + {"smmu0_int13_en19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0}, + {"smmu0_int13_en18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + {"smmu0_int13_en17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0}, + {"smmu0_int13_en16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"smmu0_int13_en15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"smmu0_int13_en14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"smmu0_int13_en13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"smmu0_int13_en12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"smmu0_int13_en11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"smmu0_int13_en10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"smmu0_int13_en9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"smmu0_int13_en8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"smmu0_int13_en7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"smmu0_int13_en6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"smmu0_int13_en5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"smmu0_int13_en4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"smmu0_int13_en3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"smmu0_int13_en2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"smmu0_int13_en1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"smmu0_int13_en0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int13_mask_reg[] = + { + {"smmu0_int13_mask19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0}, + {"smmu0_int13_mask18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + {"smmu0_int13_mask17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0}, + {"smmu0_int13_mask16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"smmu0_int13_mask15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"smmu0_int13_mask14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"smmu0_int13_mask13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"smmu0_int13_mask12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"smmu0_int13_mask11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"smmu0_int13_mask10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"smmu0_int13_mask9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"smmu0_int13_mask8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"smmu0_int13_mask7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"smmu0_int13_mask6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"smmu0_int13_mask5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"smmu0_int13_mask4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"smmu0_int13_mask3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"smmu0_int13_mask2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"smmu0_int13_mask1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"smmu0_int13_mask0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int13_status_reg[] = + { + {"smmu0_int13_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"smmu0_int13_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"smmu0_int13_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"smmu0_int13_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"smmu0_int13_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"smmu0_int13_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"smmu0_int13_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"smmu0_int13_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"smmu0_int13_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"smmu0_int13_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"smmu0_int13_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"smmu0_int13_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"smmu0_int13_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"smmu0_int13_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"smmu0_int13_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"smmu0_int13_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"smmu0_int13_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"smmu0_int13_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"smmu0_int13_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"smmu0_int13_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int14_en_reg[] = + { + {"smmu0_int14_en16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"smmu0_int14_en15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"smmu0_int14_en14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"smmu0_int14_en13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"smmu0_int14_en12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"smmu0_int14_en11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"smmu0_int14_en10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"smmu0_int14_en9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"smmu0_int14_en8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"smmu0_int14_en7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"smmu0_int14_en6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"smmu0_int14_en5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"smmu0_int14_en4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"smmu0_int14_en3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"smmu0_int14_en2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"smmu0_int14_en1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"smmu0_int14_en0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int14_mask_reg[] = + { + {"smmu0_int14_mask16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"smmu0_int14_mask15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"smmu0_int14_mask14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"smmu0_int14_mask13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"smmu0_int14_mask12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"smmu0_int14_mask11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"smmu0_int14_mask10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"smmu0_int14_mask9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"smmu0_int14_mask8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"smmu0_int14_mask7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"smmu0_int14_mask6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"smmu0_int14_mask5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"smmu0_int14_mask4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"smmu0_int14_mask3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"smmu0_int14_mask2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"smmu0_int14_mask1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"smmu0_int14_mask0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int14_status_reg[] = + { + {"smmu0_int14_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"smmu0_int14_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"smmu0_int14_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"smmu0_int14_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"smmu0_int14_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"smmu0_int14_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"smmu0_int14_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"smmu0_int14_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"smmu0_int14_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"smmu0_int14_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"smmu0_int14_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"smmu0_int14_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"smmu0_int14_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"smmu0_int14_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"smmu0_int14_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"smmu0_int14_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"smmu0_int14_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_ecc_unmask_flag_reg[] = + { + {"smmu0_int53_unmask_flag", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"smmu0_int52_unmask_flag", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"smmu0_int51_unmask_flag", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"smmu0_int50_unmask_flag", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"smmu0_int49_unmask_flag", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"smmu0_int48_unmask_flag", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"smmu0_int47_unmask_flag", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"smmu0_int46_unmask_flag", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"smmu0_int45_unmask_flag", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"smmu0_int44_unmask_flag", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"smmu0_int43_unmask_flag", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"smmu0_int42_unmask_flag", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"smmu0_int41_unmask_flag", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"smmu0_int40_unmask_flag", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"smmu0_int39_unmask_flag", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"smmu0_int38_unmask_flag", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"smmu0_int37_unmask_flag", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"smmu0_int36_unmask_flag", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"smmu0_int35_unmask_flag", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"smmu0_int34_unmask_flag", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"smmu0_int33_unmask_flag", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"smmu0_int32_unmask_flag", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int15_en_reg[] = + { + {"smmu0_int15_en31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0}, + {"smmu0_int15_en30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0}, + {"smmu0_int15_en29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0}, + {"smmu0_int15_en28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0}, + {"smmu0_int15_en27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0}, + {"smmu0_int15_en26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0}, + {"smmu0_int15_en25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0}, + {"smmu0_int15_en24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0}, + {"smmu0_int15_en23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0}, + {"smmu0_int15_en22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0}, + {"smmu0_int15_en21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0}, + {"smmu0_int15_en20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0}, + {"smmu0_int15_en19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0}, + {"smmu0_int15_en18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0}, + {"smmu0_int15_en17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0}, + {"smmu0_int15_en16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0}, + {"smmu0_int15_en15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0}, + {"smmu0_int15_en14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0}, + {"smmu0_int15_en13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0}, + {"smmu0_int15_en12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0}, + {"smmu0_int15_en11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0}, + {"smmu0_int15_en10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0}, + {"smmu0_int15_en9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0}, + {"smmu0_int15_en8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0}, + {"smmu0_int15_en7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0}, + {"smmu0_int15_en6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0}, + {"smmu0_int15_en5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0}, + {"smmu0_int15_en4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0}, + {"smmu0_int15_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0}, + {"smmu0_int15_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0}, + {"smmu0_int15_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0}, + {"smmu0_int15_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int15_mask_reg[] = + { + {"smmu0_int15_mask31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0}, + {"smmu0_int15_mask30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0}, + {"smmu0_int15_mask29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0}, + {"smmu0_int15_mask28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0}, + {"smmu0_int15_mask27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0}, + {"smmu0_int15_mask26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0}, + {"smmu0_int15_mask25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0}, + {"smmu0_int15_mask24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0}, + {"smmu0_int15_mask23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0}, + {"smmu0_int15_mask22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0}, + {"smmu0_int15_mask21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0}, + {"smmu0_int15_mask20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0}, + {"smmu0_int15_mask19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0}, + {"smmu0_int15_mask18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0}, + {"smmu0_int15_mask17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0}, + {"smmu0_int15_mask16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0}, + {"smmu0_int15_mask15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0}, + {"smmu0_int15_mask14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0}, + {"smmu0_int15_mask13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0}, + {"smmu0_int15_mask12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0}, + {"smmu0_int15_mask11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0}, + {"smmu0_int15_mask10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0}, + {"smmu0_int15_mask9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0}, + {"smmu0_int15_mask8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0}, + {"smmu0_int15_mask7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0}, + {"smmu0_int15_mask6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0}, + {"smmu0_int15_mask5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0}, + {"smmu0_int15_mask4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0}, + {"smmu0_int15_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0}, + {"smmu0_int15_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0}, + {"smmu0_int15_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0}, + {"smmu0_int15_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int15_status_reg[] = + { + {"smmu0_int15_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"smmu0_int15_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"smmu0_int15_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"smmu0_int15_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"smmu0_int15_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"smmu0_int15_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"smmu0_int15_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"smmu0_int15_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"smmu0_int15_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"smmu0_int15_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"smmu0_int15_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"smmu0_int15_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"smmu0_int15_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"smmu0_int15_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"smmu0_int15_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"smmu0_int15_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"smmu0_int15_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"smmu0_int15_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"smmu0_int15_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"smmu0_int15_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"smmu0_int15_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"smmu0_int15_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"smmu0_int15_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"smmu0_int15_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"smmu0_int15_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"smmu0_int15_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"smmu0_int15_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"smmu0_int15_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"smmu0_int15_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"smmu0_int15_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"smmu0_int15_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"smmu0_int15_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int16_en_reg[] = + { + {"smmu0_int16_en31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0}, + {"smmu0_int16_en30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0}, + {"smmu0_int16_en29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0}, + {"smmu0_int16_en28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0}, + {"smmu0_int16_en27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0}, + {"smmu0_int16_en26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0}, + {"smmu0_int16_en25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0}, + {"smmu0_int16_en24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0}, + {"smmu0_int16_en23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0}, + {"smmu0_int16_en22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0}, + {"smmu0_int16_en21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0}, + {"smmu0_int16_en20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0}, + {"smmu0_int16_en19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0}, + {"smmu0_int16_en18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0}, + {"smmu0_int16_en17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0}, + {"smmu0_int16_en16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0}, + {"smmu0_int16_en15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0}, + {"smmu0_int16_en14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0}, + {"smmu0_int16_en13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0}, + {"smmu0_int16_en12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0}, + {"smmu0_int16_en11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0}, + {"smmu0_int16_en10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0}, + {"smmu0_int16_en9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0}, + {"smmu0_int16_en8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0}, + {"smmu0_int16_en7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0}, + {"smmu0_int16_en6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0}, + {"smmu0_int16_en5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0}, + {"smmu0_int16_en4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0}, + {"smmu0_int16_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0}, + {"smmu0_int16_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0}, + {"smmu0_int16_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0}, + {"smmu0_int16_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int16_mask_reg[] = + { + {"smmu0_int16_mask31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0}, + {"smmu0_int16_mask30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0}, + {"smmu0_int16_mask29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0}, + {"smmu0_int16_mask28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0}, + {"smmu0_int16_mask27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0}, + {"smmu0_int16_mask26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0}, + {"smmu0_int16_mask25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0}, + {"smmu0_int16_mask24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0}, + {"smmu0_int16_mask23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0}, + {"smmu0_int16_mask22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0}, + {"smmu0_int16_mask21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0}, + {"smmu0_int16_mask20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0}, + {"smmu0_int16_mask19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0}, + {"smmu0_int16_mask18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0}, + {"smmu0_int16_mask17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0}, + {"smmu0_int16_mask16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0}, + {"smmu0_int16_mask15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0}, + {"smmu0_int16_mask14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0}, + {"smmu0_int16_mask13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0}, + {"smmu0_int16_mask12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0}, + {"smmu0_int16_mask11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0}, + {"smmu0_int16_mask10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0}, + {"smmu0_int16_mask9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0}, + {"smmu0_int16_mask8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0}, + {"smmu0_int16_mask7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0}, + {"smmu0_int16_mask6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0}, + {"smmu0_int16_mask5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0}, + {"smmu0_int16_mask4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0}, + {"smmu0_int16_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0}, + {"smmu0_int16_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0}, + {"smmu0_int16_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0}, + {"smmu0_int16_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int16_status_reg[] = + { + {"smmu0_int16_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"smmu0_int16_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"smmu0_int16_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"smmu0_int16_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"smmu0_int16_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"smmu0_int16_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"smmu0_int16_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"smmu0_int16_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"smmu0_int16_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"smmu0_int16_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"smmu0_int16_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"smmu0_int16_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"smmu0_int16_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"smmu0_int16_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"smmu0_int16_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"smmu0_int16_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"smmu0_int16_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"smmu0_int16_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"smmu0_int16_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"smmu0_int16_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"smmu0_int16_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"smmu0_int16_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"smmu0_int16_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"smmu0_int16_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"smmu0_int16_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"smmu0_int16_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"smmu0_int16_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"smmu0_int16_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"smmu0_int16_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"smmu0_int16_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"smmu0_int16_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"smmu0_int16_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int17_en_reg[] = + { + {"smmu0_int17_en31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0}, + {"smmu0_int17_en30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0}, + {"smmu0_int17_en29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0}, + {"smmu0_int17_en28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0}, + {"smmu0_int17_en27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0}, + {"smmu0_int17_en26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0}, + {"smmu0_int17_en25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0}, + {"smmu0_int17_en24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0}, + {"smmu0_int17_en23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0}, + {"smmu0_int17_en22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0}, + {"smmu0_int17_en21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0}, + {"smmu0_int17_en20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0}, + {"smmu0_int17_en19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0}, + {"smmu0_int17_en18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0}, + {"smmu0_int17_en17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0}, + {"smmu0_int17_en16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0}, + {"smmu0_int17_en15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0}, + {"smmu0_int17_en14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0}, + {"smmu0_int17_en13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0}, + {"smmu0_int17_en12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0}, + {"smmu0_int17_en11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0}, + {"smmu0_int17_en10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0}, + {"smmu0_int17_en9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0}, + {"smmu0_int17_en8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0}, + {"smmu0_int17_en7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0}, + {"smmu0_int17_en6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0}, + {"smmu0_int17_en5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0}, + {"smmu0_int17_en4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0}, + {"smmu0_int17_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0}, + {"smmu0_int17_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0}, + {"smmu0_int17_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0}, + {"smmu0_int17_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int17_mask_reg[] = + { + {"smmu0_int17_mask31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0}, + {"smmu0_int17_mask30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0}, + {"smmu0_int17_mask29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0}, + {"smmu0_int17_mask28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0}, + {"smmu0_int17_mask27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0}, + {"smmu0_int17_mask26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0}, + {"smmu0_int17_mask25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0}, + {"smmu0_int17_mask24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0}, + {"smmu0_int17_mask23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0}, + {"smmu0_int17_mask22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0}, + {"smmu0_int17_mask21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0}, + {"smmu0_int17_mask20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0}, + {"smmu0_int17_mask19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0}, + {"smmu0_int17_mask18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0}, + {"smmu0_int17_mask17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0}, + {"smmu0_int17_mask16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0}, + {"smmu0_int17_mask15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0}, + {"smmu0_int17_mask14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0}, + {"smmu0_int17_mask13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0}, + {"smmu0_int17_mask12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0}, + {"smmu0_int17_mask11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0}, + {"smmu0_int17_mask10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0}, + {"smmu0_int17_mask9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0}, + {"smmu0_int17_mask8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0}, + {"smmu0_int17_mask7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0}, + {"smmu0_int17_mask6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0}, + {"smmu0_int17_mask5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0}, + {"smmu0_int17_mask4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0}, + {"smmu0_int17_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0}, + {"smmu0_int17_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0}, + {"smmu0_int17_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0}, + {"smmu0_int17_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int17_status_reg[] = + { + {"smmu0_int17_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"smmu0_int17_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"smmu0_int17_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"smmu0_int17_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"smmu0_int17_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"smmu0_int17_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"smmu0_int17_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"smmu0_int17_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"smmu0_int17_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"smmu0_int17_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"smmu0_int17_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"smmu0_int17_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"smmu0_int17_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"smmu0_int17_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"smmu0_int17_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"smmu0_int17_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"smmu0_int17_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"smmu0_int17_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"smmu0_int17_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"smmu0_int17_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"smmu0_int17_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"smmu0_int17_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"smmu0_int17_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"smmu0_int17_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"smmu0_int17_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"smmu0_int17_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"smmu0_int17_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"smmu0_int17_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"smmu0_int17_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"smmu0_int17_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"smmu0_int17_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"smmu0_int17_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int18_en_reg[] = + { + {"smmu0_int18_en31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0}, + {"smmu0_int18_en30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0}, + {"smmu0_int18_en29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0}, + {"smmu0_int18_en28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0}, + {"smmu0_int18_en27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0}, + {"smmu0_int18_en26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0}, + {"smmu0_int18_en25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0}, + {"smmu0_int18_en24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0}, + {"smmu0_int18_en23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0}, + {"smmu0_int18_en22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0}, + {"smmu0_int18_en21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0}, + {"smmu0_int18_en20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0}, + {"smmu0_int18_en19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0}, + {"smmu0_int18_en18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0}, + {"smmu0_int18_en17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0}, + {"smmu0_int18_en16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0}, + {"smmu0_int18_en15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0}, + {"smmu0_int18_en14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0}, + {"smmu0_int18_en13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0}, + {"smmu0_int18_en12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0}, + {"smmu0_int18_en11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0}, + {"smmu0_int18_en10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0}, + {"smmu0_int18_en9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0}, + {"smmu0_int18_en8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0}, + {"smmu0_int18_en7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0}, + {"smmu0_int18_en6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0}, + {"smmu0_int18_en5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0}, + {"smmu0_int18_en4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0}, + {"smmu0_int18_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0}, + {"smmu0_int18_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0}, + {"smmu0_int18_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0}, + {"smmu0_int18_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int18_mask_reg[] = + { + {"smmu0_int18_mask31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0}, + {"smmu0_int18_mask30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0}, + {"smmu0_int18_mask29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0}, + {"smmu0_int18_mask28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0}, + {"smmu0_int18_mask27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0}, + {"smmu0_int18_mask26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0}, + {"smmu0_int18_mask25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0}, + {"smmu0_int18_mask24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0}, + {"smmu0_int18_mask23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0}, + {"smmu0_int18_mask22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0}, + {"smmu0_int18_mask21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0}, + {"smmu0_int18_mask20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0}, + {"smmu0_int18_mask19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0}, + {"smmu0_int18_mask18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0}, + {"smmu0_int18_mask17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0}, + {"smmu0_int18_mask16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0}, + {"smmu0_int18_mask15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0}, + {"smmu0_int18_mask14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0}, + {"smmu0_int18_mask13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0}, + {"smmu0_int18_mask12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0}, + {"smmu0_int18_mask11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0}, + {"smmu0_int18_mask10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0}, + {"smmu0_int18_mask9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0}, + {"smmu0_int18_mask8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0}, + {"smmu0_int18_mask7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0}, + {"smmu0_int18_mask6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0}, + {"smmu0_int18_mask5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0}, + {"smmu0_int18_mask4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0}, + {"smmu0_int18_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0}, + {"smmu0_int18_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0}, + {"smmu0_int18_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0}, + {"smmu0_int18_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int18_status_reg[] = + { + {"smmu0_int18_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"smmu0_int18_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"smmu0_int18_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"smmu0_int18_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"smmu0_int18_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"smmu0_int18_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"smmu0_int18_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"smmu0_int18_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"smmu0_int18_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"smmu0_int18_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"smmu0_int18_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"smmu0_int18_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"smmu0_int18_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"smmu0_int18_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"smmu0_int18_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"smmu0_int18_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"smmu0_int18_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"smmu0_int18_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"smmu0_int18_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"smmu0_int18_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"smmu0_int18_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"smmu0_int18_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"smmu0_int18_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"smmu0_int18_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"smmu0_int18_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"smmu0_int18_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"smmu0_int18_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"smmu0_int18_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"smmu0_int18_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"smmu0_int18_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"smmu0_int18_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"smmu0_int18_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int19_en_reg[] = + { + {"smmu0_int19_en31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0}, + {"smmu0_int19_en30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0}, + {"smmu0_int19_en29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0}, + {"smmu0_int19_en28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0}, + {"smmu0_int19_en27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0}, + {"smmu0_int19_en26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0}, + {"smmu0_int19_en25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0}, + {"smmu0_int19_en24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0}, + {"smmu0_int19_en23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0}, + {"smmu0_int19_en22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0}, + {"smmu0_int19_en21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0}, + {"smmu0_int19_en20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0}, + {"smmu0_int19_en19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0}, + {"smmu0_int19_en18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0}, + {"smmu0_int19_en17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0}, + {"smmu0_int19_en16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0}, + {"smmu0_int19_en15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0}, + {"smmu0_int19_en14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0}, + {"smmu0_int19_en13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0}, + {"smmu0_int19_en12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0}, + {"smmu0_int19_en11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0}, + {"smmu0_int19_en10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0}, + {"smmu0_int19_en9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0}, + {"smmu0_int19_en8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0}, + {"smmu0_int19_en7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0}, + {"smmu0_int19_en6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0}, + {"smmu0_int19_en5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0}, + {"smmu0_int19_en4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0}, + {"smmu0_int19_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0}, + {"smmu0_int19_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0}, + {"smmu0_int19_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0}, + {"smmu0_int19_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int19_mask_reg[] = + { + {"smmu0_int19_mask31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0}, + {"smmu0_int19_mask30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0}, + {"smmu0_int19_mask29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0}, + {"smmu0_int19_mask28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0}, + {"smmu0_int19_mask27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0}, + {"smmu0_int19_mask26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0}, + {"smmu0_int19_mask25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0}, + {"smmu0_int19_mask24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0}, + {"smmu0_int19_mask23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0}, + {"smmu0_int19_mask22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0}, + {"smmu0_int19_mask21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0}, + {"smmu0_int19_mask20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0}, + {"smmu0_int19_mask19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0}, + {"smmu0_int19_mask18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0}, + {"smmu0_int19_mask17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0}, + {"smmu0_int19_mask16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0}, + {"smmu0_int19_mask15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0}, + {"smmu0_int19_mask14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0}, + {"smmu0_int19_mask13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0}, + {"smmu0_int19_mask12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0}, + {"smmu0_int19_mask11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0}, + {"smmu0_int19_mask10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0}, + {"smmu0_int19_mask9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0}, + {"smmu0_int19_mask8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0}, + {"smmu0_int19_mask7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0}, + {"smmu0_int19_mask6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0}, + {"smmu0_int19_mask5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0}, + {"smmu0_int19_mask4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0}, + {"smmu0_int19_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0}, + {"smmu0_int19_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0}, + {"smmu0_int19_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0}, + {"smmu0_int19_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int19_status_reg[] = + { + {"smmu0_int19_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"smmu0_int19_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"smmu0_int19_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"smmu0_int19_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"smmu0_int19_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"smmu0_int19_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"smmu0_int19_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"smmu0_int19_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"smmu0_int19_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"smmu0_int19_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"smmu0_int19_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"smmu0_int19_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"smmu0_int19_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"smmu0_int19_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"smmu0_int19_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"smmu0_int19_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"smmu0_int19_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"smmu0_int19_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"smmu0_int19_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"smmu0_int19_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"smmu0_int19_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"smmu0_int19_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"smmu0_int19_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"smmu0_int19_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"smmu0_int19_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"smmu0_int19_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"smmu0_int19_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"smmu0_int19_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"smmu0_int19_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"smmu0_int19_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"smmu0_int19_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"smmu0_int19_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int20_en_reg[] = + { + {"smmu0_int20_en31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0}, + {"smmu0_int20_en30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0}, + {"smmu0_int20_en29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0}, + {"smmu0_int20_en28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0}, + {"smmu0_int20_en27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0}, + {"smmu0_int20_en26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0}, + {"smmu0_int20_en25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0}, + {"smmu0_int20_en24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0}, + {"smmu0_int20_en23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0}, + {"smmu0_int20_en22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0}, + {"smmu0_int20_en21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0}, + {"smmu0_int20_en20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0}, + {"smmu0_int20_en19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0}, + {"smmu0_int20_en18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0}, + {"smmu0_int20_en17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0}, + {"smmu0_int20_en16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0}, + {"smmu0_int20_en15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0}, + {"smmu0_int20_en14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0}, + {"smmu0_int20_en13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0}, + {"smmu0_int20_en12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0}, + {"smmu0_int20_en11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0}, + {"smmu0_int20_en10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0}, + {"smmu0_int20_en9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0}, + {"smmu0_int20_en8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0}, + {"smmu0_int20_en7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0}, + {"smmu0_int20_en6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0}, + {"smmu0_int20_en5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0}, + {"smmu0_int20_en4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0}, + {"smmu0_int20_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0}, + {"smmu0_int20_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0}, + {"smmu0_int20_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0}, + {"smmu0_int20_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int20_mask_reg[] = + { + {"smmu0_int20_mask31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0}, + {"smmu0_int20_mask30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0}, + {"smmu0_int20_mask29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0}, + {"smmu0_int20_mask28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0}, + {"smmu0_int20_mask27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0}, + {"smmu0_int20_mask26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0}, + {"smmu0_int20_mask25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0}, + {"smmu0_int20_mask24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0}, + {"smmu0_int20_mask23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0}, + {"smmu0_int20_mask22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0}, + {"smmu0_int20_mask21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0}, + {"smmu0_int20_mask20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0}, + {"smmu0_int20_mask19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0}, + {"smmu0_int20_mask18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0}, + {"smmu0_int20_mask17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0}, + {"smmu0_int20_mask16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0}, + {"smmu0_int20_mask15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0}, + {"smmu0_int20_mask14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0}, + {"smmu0_int20_mask13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0}, + {"smmu0_int20_mask12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0}, + {"smmu0_int20_mask11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0}, + {"smmu0_int20_mask10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0}, + {"smmu0_int20_mask9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0}, + {"smmu0_int20_mask8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0}, + {"smmu0_int20_mask7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0}, + {"smmu0_int20_mask6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0}, + {"smmu0_int20_mask5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0}, + {"smmu0_int20_mask4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0}, + {"smmu0_int20_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0}, + {"smmu0_int20_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0}, + {"smmu0_int20_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0}, + {"smmu0_int20_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int20_status_reg[] = + { + {"smmu0_int20_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"smmu0_int20_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"smmu0_int20_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"smmu0_int20_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"smmu0_int20_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"smmu0_int20_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"smmu0_int20_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"smmu0_int20_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"smmu0_int20_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"smmu0_int20_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"smmu0_int20_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"smmu0_int20_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"smmu0_int20_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"smmu0_int20_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"smmu0_int20_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"smmu0_int20_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"smmu0_int20_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"smmu0_int20_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"smmu0_int20_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"smmu0_int20_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"smmu0_int20_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"smmu0_int20_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"smmu0_int20_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"smmu0_int20_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"smmu0_int20_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"smmu0_int20_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"smmu0_int20_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"smmu0_int20_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"smmu0_int20_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"smmu0_int20_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"smmu0_int20_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"smmu0_int20_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int21_en_reg[] = + { + {"smmu0_int21_en31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0}, + {"smmu0_int21_en30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0}, + {"smmu0_int21_en29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0}, + {"smmu0_int21_en28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0}, + {"smmu0_int21_en27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0}, + {"smmu0_int21_en26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0}, + {"smmu0_int21_en25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0}, + {"smmu0_int21_en24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0}, + {"smmu0_int21_en23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0}, + {"smmu0_int21_en22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0}, + {"smmu0_int21_en21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0}, + {"smmu0_int21_en20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0}, + {"smmu0_int21_en19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0}, + {"smmu0_int21_en18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0}, + {"smmu0_int21_en17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0}, + {"smmu0_int21_en16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0}, + {"smmu0_int21_en15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0}, + {"smmu0_int21_en14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0}, + {"smmu0_int21_en13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0}, + {"smmu0_int21_en12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0}, + {"smmu0_int21_en11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0}, + {"smmu0_int21_en10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0}, + {"smmu0_int21_en9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0}, + {"smmu0_int21_en8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0}, + {"smmu0_int21_en7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0}, + {"smmu0_int21_en6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0}, + {"smmu0_int21_en5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0}, + {"smmu0_int21_en4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0}, + {"smmu0_int21_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0}, + {"smmu0_int21_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0}, + {"smmu0_int21_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0}, + {"smmu0_int21_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int21_mask_reg[] = + { + {"smmu0_int21_mask31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0}, + {"smmu0_int21_mask30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0}, + {"smmu0_int21_mask29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0}, + {"smmu0_int21_mask28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0}, + {"smmu0_int21_mask27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0}, + {"smmu0_int21_mask26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0}, + {"smmu0_int21_mask25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0}, + {"smmu0_int21_mask24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0}, + {"smmu0_int21_mask23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0}, + {"smmu0_int21_mask22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0}, + {"smmu0_int21_mask21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0}, + {"smmu0_int21_mask20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0}, + {"smmu0_int21_mask19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0}, + {"smmu0_int21_mask18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0}, + {"smmu0_int21_mask17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0}, + {"smmu0_int21_mask16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0}, + {"smmu0_int21_mask15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0}, + {"smmu0_int21_mask14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0}, + {"smmu0_int21_mask13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0}, + {"smmu0_int21_mask12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0}, + {"smmu0_int21_mask11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0}, + {"smmu0_int21_mask10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0}, + {"smmu0_int21_mask9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0}, + {"smmu0_int21_mask8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0}, + {"smmu0_int21_mask7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0}, + {"smmu0_int21_mask6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0}, + {"smmu0_int21_mask5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0}, + {"smmu0_int21_mask4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0}, + {"smmu0_int21_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0}, + {"smmu0_int21_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0}, + {"smmu0_int21_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0}, + {"smmu0_int21_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int21_status_reg[] = + { + {"smmu0_int21_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"smmu0_int21_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"smmu0_int21_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"smmu0_int21_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"smmu0_int21_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"smmu0_int21_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"smmu0_int21_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"smmu0_int21_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"smmu0_int21_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"smmu0_int21_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"smmu0_int21_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"smmu0_int21_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"smmu0_int21_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"smmu0_int21_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"smmu0_int21_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"smmu0_int21_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"smmu0_int21_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"smmu0_int21_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"smmu0_int21_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"smmu0_int21_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"smmu0_int21_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"smmu0_int21_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"smmu0_int21_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"smmu0_int21_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"smmu0_int21_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"smmu0_int21_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"smmu0_int21_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"smmu0_int21_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"smmu0_int21_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"smmu0_int21_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"smmu0_int21_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"smmu0_int21_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int22_en_reg[] = + { + {"smmu0_int22_en31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0}, + {"smmu0_int22_en30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0}, + {"smmu0_int22_en29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0}, + {"smmu0_int22_en28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0}, + {"smmu0_int22_en27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0}, + {"smmu0_int22_en26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0}, + {"smmu0_int22_en25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0}, + {"smmu0_int22_en24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0}, + {"smmu0_int22_en23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0}, + {"smmu0_int22_en22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0}, + {"smmu0_int22_en21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0}, + {"smmu0_int22_en20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0}, + {"smmu0_int22_en19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0}, + {"smmu0_int22_en18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0}, + {"smmu0_int22_en17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0}, + {"smmu0_int22_en16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0}, + {"smmu0_int22_en15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0}, + {"smmu0_int22_en14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0}, + {"smmu0_int22_en13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0}, + {"smmu0_int22_en12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0}, + {"smmu0_int22_en11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0}, + {"smmu0_int22_en10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0}, + {"smmu0_int22_en9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0}, + {"smmu0_int22_en8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0}, + {"smmu0_int22_en7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0}, + {"smmu0_int22_en6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0}, + {"smmu0_int22_en5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0}, + {"smmu0_int22_en4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0}, + {"smmu0_int22_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0}, + {"smmu0_int22_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0}, + {"smmu0_int22_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0}, + {"smmu0_int22_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int22_mask_reg[] = + { + {"smmu0_int22_mask31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0}, + {"smmu0_int22_mask30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0}, + {"smmu0_int22_mask29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0}, + {"smmu0_int22_mask28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0}, + {"smmu0_int22_mask27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0}, + {"smmu0_int22_mask26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0}, + {"smmu0_int22_mask25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0}, + {"smmu0_int22_mask24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0}, + {"smmu0_int22_mask23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0}, + {"smmu0_int22_mask22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0}, + {"smmu0_int22_mask21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0}, + {"smmu0_int22_mask20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0}, + {"smmu0_int22_mask19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0}, + {"smmu0_int22_mask18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0}, + {"smmu0_int22_mask17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0}, + {"smmu0_int22_mask16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0}, + {"smmu0_int22_mask15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0}, + {"smmu0_int22_mask14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0}, + {"smmu0_int22_mask13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0}, + {"smmu0_int22_mask12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0}, + {"smmu0_int22_mask11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0}, + {"smmu0_int22_mask10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0}, + {"smmu0_int22_mask9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0}, + {"smmu0_int22_mask8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0}, + {"smmu0_int22_mask7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0}, + {"smmu0_int22_mask6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0}, + {"smmu0_int22_mask5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0}, + {"smmu0_int22_mask4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0}, + {"smmu0_int22_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0}, + {"smmu0_int22_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0}, + {"smmu0_int22_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0}, + {"smmu0_int22_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int22_status_reg[] = + { + {"smmu0_int22_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"smmu0_int22_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"smmu0_int22_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"smmu0_int22_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"smmu0_int22_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"smmu0_int22_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"smmu0_int22_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"smmu0_int22_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"smmu0_int22_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"smmu0_int22_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"smmu0_int22_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"smmu0_int22_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"smmu0_int22_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"smmu0_int22_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"smmu0_int22_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"smmu0_int22_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"smmu0_int22_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"smmu0_int22_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"smmu0_int22_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"smmu0_int22_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"smmu0_int22_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"smmu0_int22_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"smmu0_int22_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"smmu0_int22_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"smmu0_int22_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"smmu0_int22_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"smmu0_int22_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"smmu0_int22_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"smmu0_int22_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"smmu0_int22_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"smmu0_int22_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"smmu0_int22_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int23_en_reg[] = + { + {"smmu0_int23_en31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0}, + {"smmu0_int23_en30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0}, + {"smmu0_int23_en29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0}, + {"smmu0_int23_en28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0}, + {"smmu0_int23_en27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0}, + {"smmu0_int23_en26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0}, + {"smmu0_int23_en25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0}, + {"smmu0_int23_en24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0}, + {"smmu0_int23_en23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0}, + {"smmu0_int23_en22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0}, + {"smmu0_int23_en21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0}, + {"smmu0_int23_en20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0}, + {"smmu0_int23_en19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0}, + {"smmu0_int23_en18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0}, + {"smmu0_int23_en17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0}, + {"smmu0_int23_en16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0}, + {"smmu0_int23_en15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0}, + {"smmu0_int23_en14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0}, + {"smmu0_int23_en13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0}, + {"smmu0_int23_en12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0}, + {"smmu0_int23_en11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0}, + {"smmu0_int23_en10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0}, + {"smmu0_int23_en9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0}, + {"smmu0_int23_en8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0}, + {"smmu0_int23_en7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0}, + {"smmu0_int23_en6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0}, + {"smmu0_int23_en5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0}, + {"smmu0_int23_en4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0}, + {"smmu0_int23_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0}, + {"smmu0_int23_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0}, + {"smmu0_int23_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0}, + {"smmu0_int23_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int23_mask_reg[] = + { + {"smmu0_int23_mask31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0}, + {"smmu0_int23_mask30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0}, + {"smmu0_int23_mask29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0}, + {"smmu0_int23_mask28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0}, + {"smmu0_int23_mask27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0}, + {"smmu0_int23_mask26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0}, + {"smmu0_int23_mask25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0}, + {"smmu0_int23_mask24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0}, + {"smmu0_int23_mask23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0}, + {"smmu0_int23_mask22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0}, + {"smmu0_int23_mask21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0}, + {"smmu0_int23_mask20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0}, + {"smmu0_int23_mask19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0}, + {"smmu0_int23_mask18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0}, + {"smmu0_int23_mask17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0}, + {"smmu0_int23_mask16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0}, + {"smmu0_int23_mask15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0}, + {"smmu0_int23_mask14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0}, + {"smmu0_int23_mask13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0}, + {"smmu0_int23_mask12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0}, + {"smmu0_int23_mask11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0}, + {"smmu0_int23_mask10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0}, + {"smmu0_int23_mask9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0}, + {"smmu0_int23_mask8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0}, + {"smmu0_int23_mask7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0}, + {"smmu0_int23_mask6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0}, + {"smmu0_int23_mask5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0}, + {"smmu0_int23_mask4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0}, + {"smmu0_int23_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0}, + {"smmu0_int23_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0}, + {"smmu0_int23_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0}, + {"smmu0_int23_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int23_status_reg[] = + { + {"smmu0_int23_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"smmu0_int23_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"smmu0_int23_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"smmu0_int23_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"smmu0_int23_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"smmu0_int23_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"smmu0_int23_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"smmu0_int23_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"smmu0_int23_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"smmu0_int23_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"smmu0_int23_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"smmu0_int23_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"smmu0_int23_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"smmu0_int23_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"smmu0_int23_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"smmu0_int23_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"smmu0_int23_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"smmu0_int23_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"smmu0_int23_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"smmu0_int23_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"smmu0_int23_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"smmu0_int23_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"smmu0_int23_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"smmu0_int23_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"smmu0_int23_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"smmu0_int23_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"smmu0_int23_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"smmu0_int23_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"smmu0_int23_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"smmu0_int23_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"smmu0_int23_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"smmu0_int23_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int24_en_reg[] = + { + {"smmu0_int24_en31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0}, + {"smmu0_int24_en30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0}, + {"smmu0_int24_en29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0}, + {"smmu0_int24_en28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0}, + {"smmu0_int24_en27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0}, + {"smmu0_int24_en26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0}, + {"smmu0_int24_en25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0}, + {"smmu0_int24_en24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0}, + {"smmu0_int24_en23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0}, + {"smmu0_int24_en22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0}, + {"smmu0_int24_en21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0}, + {"smmu0_int24_en20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0}, + {"smmu0_int24_en19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0}, + {"smmu0_int24_en18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0}, + {"smmu0_int24_en17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0}, + {"smmu0_int24_en16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0}, + {"smmu0_int24_en15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0}, + {"smmu0_int24_en14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0}, + {"smmu0_int24_en13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0}, + {"smmu0_int24_en12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0}, + {"smmu0_int24_en11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0}, + {"smmu0_int24_en10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0}, + {"smmu0_int24_en9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0}, + {"smmu0_int24_en8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0}, + {"smmu0_int24_en7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0}, + {"smmu0_int24_en6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0}, + {"smmu0_int24_en5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0}, + {"smmu0_int24_en4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0}, + {"smmu0_int24_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0}, + {"smmu0_int24_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0}, + {"smmu0_int24_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0}, + {"smmu0_int24_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int24_mask_reg[] = + { + {"smmu0_int24_mask31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0}, + {"smmu0_int24_mask30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0}, + {"smmu0_int24_mask29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0}, + {"smmu0_int24_mask28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0}, + {"smmu0_int24_mask27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0}, + {"smmu0_int24_mask26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0}, + {"smmu0_int24_mask25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0}, + {"smmu0_int24_mask24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0}, + {"smmu0_int24_mask23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0}, + {"smmu0_int24_mask22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0}, + {"smmu0_int24_mask21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0}, + {"smmu0_int24_mask20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0}, + {"smmu0_int24_mask19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0}, + {"smmu0_int24_mask18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0}, + {"smmu0_int24_mask17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0}, + {"smmu0_int24_mask16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0}, + {"smmu0_int24_mask15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0}, + {"smmu0_int24_mask14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0}, + {"smmu0_int24_mask13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0}, + {"smmu0_int24_mask12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0}, + {"smmu0_int24_mask11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0}, + {"smmu0_int24_mask10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0}, + {"smmu0_int24_mask9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0}, + {"smmu0_int24_mask8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0}, + {"smmu0_int24_mask7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0}, + {"smmu0_int24_mask6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0}, + {"smmu0_int24_mask5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0}, + {"smmu0_int24_mask4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0}, + {"smmu0_int24_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0}, + {"smmu0_int24_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0}, + {"smmu0_int24_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0}, + {"smmu0_int24_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int24_status_reg[] = + { + {"smmu0_int24_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"smmu0_int24_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"smmu0_int24_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"smmu0_int24_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"smmu0_int24_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"smmu0_int24_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"smmu0_int24_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"smmu0_int24_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"smmu0_int24_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"smmu0_int24_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"smmu0_int24_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"smmu0_int24_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"smmu0_int24_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"smmu0_int24_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"smmu0_int24_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"smmu0_int24_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"smmu0_int24_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"smmu0_int24_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"smmu0_int24_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"smmu0_int24_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"smmu0_int24_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"smmu0_int24_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"smmu0_int24_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"smmu0_int24_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"smmu0_int24_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"smmu0_int24_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"smmu0_int24_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"smmu0_int24_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"smmu0_int24_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"smmu0_int24_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"smmu0_int24_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"smmu0_int24_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int25_en_reg[] = + { + {"smmu0_int25_en31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0}, + {"smmu0_int25_en30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0}, + {"smmu0_int25_en29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0}, + {"smmu0_int25_en28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0}, + {"smmu0_int25_en27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0}, + {"smmu0_int25_en26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0}, + {"smmu0_int25_en25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0}, + {"smmu0_int25_en24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0}, + {"smmu0_int25_en23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0}, + {"smmu0_int25_en22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0}, + {"smmu0_int25_en21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0}, + {"smmu0_int25_en20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0}, + {"smmu0_int25_en19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0}, + {"smmu0_int25_en18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0}, + {"smmu0_int25_en17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0}, + {"smmu0_int25_en16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0}, + {"smmu0_int25_en15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0}, + {"smmu0_int25_en14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0}, + {"smmu0_int25_en13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0}, + {"smmu0_int25_en12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0}, + {"smmu0_int25_en11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0}, + {"smmu0_int25_en10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0}, + {"smmu0_int25_en9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0}, + {"smmu0_int25_en8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0}, + {"smmu0_int25_en7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0}, + {"smmu0_int25_en6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0}, + {"smmu0_int25_en5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0}, + {"smmu0_int25_en4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0}, + {"smmu0_int25_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0}, + {"smmu0_int25_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0}, + {"smmu0_int25_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0}, + {"smmu0_int25_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int25_mask_reg[] = + { + {"smmu0_int25_mask31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0}, + {"smmu0_int25_mask30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0}, + {"smmu0_int25_mask29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0}, + {"smmu0_int25_mask28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0}, + {"smmu0_int25_mask27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0}, + {"smmu0_int25_mask26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0}, + {"smmu0_int25_mask25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0}, + {"smmu0_int25_mask24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0}, + {"smmu0_int25_mask23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0}, + {"smmu0_int25_mask22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0}, + {"smmu0_int25_mask21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0}, + {"smmu0_int25_mask20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0}, + {"smmu0_int25_mask19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0}, + {"smmu0_int25_mask18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0}, + {"smmu0_int25_mask17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0}, + {"smmu0_int25_mask16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0}, + {"smmu0_int25_mask15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0}, + {"smmu0_int25_mask14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0}, + {"smmu0_int25_mask13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0}, + {"smmu0_int25_mask12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0}, + {"smmu0_int25_mask11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0}, + {"smmu0_int25_mask10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0}, + {"smmu0_int25_mask9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0}, + {"smmu0_int25_mask8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0}, + {"smmu0_int25_mask7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0}, + {"smmu0_int25_mask6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0}, + {"smmu0_int25_mask5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0}, + {"smmu0_int25_mask4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0}, + {"smmu0_int25_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0}, + {"smmu0_int25_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0}, + {"smmu0_int25_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0}, + {"smmu0_int25_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int25_status_reg[] = + { + {"smmu0_int25_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"smmu0_int25_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"smmu0_int25_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"smmu0_int25_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"smmu0_int25_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"smmu0_int25_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"smmu0_int25_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"smmu0_int25_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"smmu0_int25_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"smmu0_int25_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"smmu0_int25_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"smmu0_int25_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"smmu0_int25_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"smmu0_int25_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"smmu0_int25_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"smmu0_int25_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"smmu0_int25_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"smmu0_int25_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"smmu0_int25_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"smmu0_int25_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"smmu0_int25_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"smmu0_int25_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"smmu0_int25_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"smmu0_int25_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"smmu0_int25_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"smmu0_int25_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"smmu0_int25_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"smmu0_int25_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"smmu0_int25_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"smmu0_int25_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"smmu0_int25_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"smmu0_int25_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int26_en_reg[] = + { + {"smmu0_int26_en31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0}, + {"smmu0_int26_en30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0}, + {"smmu0_int26_en29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0}, + {"smmu0_int26_en28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0}, + {"smmu0_int26_en27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0}, + {"smmu0_int26_en26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0}, + {"smmu0_int26_en25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0}, + {"smmu0_int26_en24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0}, + {"smmu0_int26_en23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0}, + {"smmu0_int26_en22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0}, + {"smmu0_int26_en21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0}, + {"smmu0_int26_en20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0}, + {"smmu0_int26_en19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0}, + {"smmu0_int26_en18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0}, + {"smmu0_int26_en17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0}, + {"smmu0_int26_en16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0}, + {"smmu0_int26_en15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0}, + {"smmu0_int26_en14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0}, + {"smmu0_int26_en13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0}, + {"smmu0_int26_en12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0}, + {"smmu0_int26_en11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0}, + {"smmu0_int26_en10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0}, + {"smmu0_int26_en9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0}, + {"smmu0_int26_en8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0}, + {"smmu0_int26_en7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0}, + {"smmu0_int26_en6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0}, + {"smmu0_int26_en5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0}, + {"smmu0_int26_en4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0}, + {"smmu0_int26_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0}, + {"smmu0_int26_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0}, + {"smmu0_int26_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0}, + {"smmu0_int26_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int26_mask_reg[] = + { + {"smmu0_int26_mask31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0}, + {"smmu0_int26_mask30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0}, + {"smmu0_int26_mask29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0}, + {"smmu0_int26_mask28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0}, + {"smmu0_int26_mask27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0}, + {"smmu0_int26_mask26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0}, + {"smmu0_int26_mask25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0}, + {"smmu0_int26_mask24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0}, + {"smmu0_int26_mask23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0}, + {"smmu0_int26_mask22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0}, + {"smmu0_int26_mask21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0}, + {"smmu0_int26_mask20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0}, + {"smmu0_int26_mask19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0}, + {"smmu0_int26_mask18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0}, + {"smmu0_int26_mask17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0}, + {"smmu0_int26_mask16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0}, + {"smmu0_int26_mask15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0}, + {"smmu0_int26_mask14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0}, + {"smmu0_int26_mask13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0}, + {"smmu0_int26_mask12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0}, + {"smmu0_int26_mask11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0}, + {"smmu0_int26_mask10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0}, + {"smmu0_int26_mask9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0}, + {"smmu0_int26_mask8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0}, + {"smmu0_int26_mask7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0}, + {"smmu0_int26_mask6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0}, + {"smmu0_int26_mask5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0}, + {"smmu0_int26_mask4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0}, + {"smmu0_int26_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0}, + {"smmu0_int26_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0}, + {"smmu0_int26_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0}, + {"smmu0_int26_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int26_status_reg[] = + { + {"smmu0_int26_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"smmu0_int26_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"smmu0_int26_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"smmu0_int26_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"smmu0_int26_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"smmu0_int26_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"smmu0_int26_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"smmu0_int26_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"smmu0_int26_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"smmu0_int26_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"smmu0_int26_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"smmu0_int26_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"smmu0_int26_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"smmu0_int26_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"smmu0_int26_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"smmu0_int26_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"smmu0_int26_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"smmu0_int26_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"smmu0_int26_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"smmu0_int26_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"smmu0_int26_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"smmu0_int26_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"smmu0_int26_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"smmu0_int26_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"smmu0_int26_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"smmu0_int26_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"smmu0_int26_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"smmu0_int26_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"smmu0_int26_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"smmu0_int26_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"smmu0_int26_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"smmu0_int26_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int27_en_reg[] = + { + {"smmu0_int27_en31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0}, + {"smmu0_int27_en30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0}, + {"smmu0_int27_en29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0}, + {"smmu0_int27_en28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0}, + {"smmu0_int27_en27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0}, + {"smmu0_int27_en26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0}, + {"smmu0_int27_en25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0}, + {"smmu0_int27_en24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0}, + {"smmu0_int27_en23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0}, + {"smmu0_int27_en22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0}, + {"smmu0_int27_en21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0}, + {"smmu0_int27_en20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0}, + {"smmu0_int27_en19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0}, + {"smmu0_int27_en18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0}, + {"smmu0_int27_en17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0}, + {"smmu0_int27_en16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0}, + {"smmu0_int27_en15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0}, + {"smmu0_int27_en14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0}, + {"smmu0_int27_en13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0}, + {"smmu0_int27_en12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0}, + {"smmu0_int27_en11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0}, + {"smmu0_int27_en10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0}, + {"smmu0_int27_en9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0}, + {"smmu0_int27_en8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0}, + {"smmu0_int27_en7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0}, + {"smmu0_int27_en6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0}, + {"smmu0_int27_en5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0}, + {"smmu0_int27_en4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0}, + {"smmu0_int27_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0}, + {"smmu0_int27_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0}, + {"smmu0_int27_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0}, + {"smmu0_int27_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int27_mask_reg[] = + { + {"smmu0_int27_mask31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0}, + {"smmu0_int27_mask30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0}, + {"smmu0_int27_mask29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0}, + {"smmu0_int27_mask28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0}, + {"smmu0_int27_mask27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0}, + {"smmu0_int27_mask26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0}, + {"smmu0_int27_mask25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0}, + {"smmu0_int27_mask24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0}, + {"smmu0_int27_mask23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0}, + {"smmu0_int27_mask22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0}, + {"smmu0_int27_mask21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0}, + {"smmu0_int27_mask20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0}, + {"smmu0_int27_mask19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0}, + {"smmu0_int27_mask18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0}, + {"smmu0_int27_mask17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0}, + {"smmu0_int27_mask16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0}, + {"smmu0_int27_mask15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0}, + {"smmu0_int27_mask14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0}, + {"smmu0_int27_mask13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0}, + {"smmu0_int27_mask12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0}, + {"smmu0_int27_mask11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0}, + {"smmu0_int27_mask10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0}, + {"smmu0_int27_mask9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0}, + {"smmu0_int27_mask8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0}, + {"smmu0_int27_mask7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0}, + {"smmu0_int27_mask6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0}, + {"smmu0_int27_mask5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0}, + {"smmu0_int27_mask4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0}, + {"smmu0_int27_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0}, + {"smmu0_int27_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0}, + {"smmu0_int27_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0}, + {"smmu0_int27_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int27_status_reg[] = + { + {"smmu0_int27_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"smmu0_int27_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"smmu0_int27_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"smmu0_int27_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"smmu0_int27_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"smmu0_int27_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"smmu0_int27_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"smmu0_int27_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"smmu0_int27_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"smmu0_int27_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"smmu0_int27_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"smmu0_int27_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"smmu0_int27_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"smmu0_int27_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"smmu0_int27_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"smmu0_int27_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"smmu0_int27_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"smmu0_int27_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"smmu0_int27_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"smmu0_int27_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"smmu0_int27_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"smmu0_int27_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"smmu0_int27_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"smmu0_int27_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"smmu0_int27_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"smmu0_int27_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"smmu0_int27_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"smmu0_int27_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"smmu0_int27_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"smmu0_int27_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"smmu0_int27_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"smmu0_int27_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int28_en_reg[] = + { + {"smmu0_int28_en31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0}, + {"smmu0_int28_en30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0}, + {"smmu0_int28_en29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0}, + {"smmu0_int28_en28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0}, + {"smmu0_int28_en27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0}, + {"smmu0_int28_en26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0}, + {"smmu0_int28_en25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0}, + {"smmu0_int28_en24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0}, + {"smmu0_int28_en23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0}, + {"smmu0_int28_en22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0}, + {"smmu0_int28_en21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0}, + {"smmu0_int28_en20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0}, + {"smmu0_int28_en19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0}, + {"smmu0_int28_en18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0}, + {"smmu0_int28_en17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0}, + {"smmu0_int28_en16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0}, + {"smmu0_int28_en15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0}, + {"smmu0_int28_en14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0}, + {"smmu0_int28_en13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0}, + {"smmu0_int28_en12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0}, + {"smmu0_int28_en11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0}, + {"smmu0_int28_en10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0}, + {"smmu0_int28_en9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0}, + {"smmu0_int28_en8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0}, + {"smmu0_int28_en7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0}, + {"smmu0_int28_en6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0}, + {"smmu0_int28_en5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0}, + {"smmu0_int28_en4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0}, + {"smmu0_int28_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0}, + {"smmu0_int28_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0}, + {"smmu0_int28_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0}, + {"smmu0_int28_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int28_mask_reg[] = + { + {"smmu0_int28_mask31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0}, + {"smmu0_int28_mask30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0}, + {"smmu0_int28_mask29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0}, + {"smmu0_int28_mask28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0}, + {"smmu0_int28_mask27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0}, + {"smmu0_int28_mask26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0}, + {"smmu0_int28_mask25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0}, + {"smmu0_int28_mask24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0}, + {"smmu0_int28_mask23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0}, + {"smmu0_int28_mask22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0}, + {"smmu0_int28_mask21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0}, + {"smmu0_int28_mask20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0}, + {"smmu0_int28_mask19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0}, + {"smmu0_int28_mask18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0}, + {"smmu0_int28_mask17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0}, + {"smmu0_int28_mask16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0}, + {"smmu0_int28_mask15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0}, + {"smmu0_int28_mask14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0}, + {"smmu0_int28_mask13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0}, + {"smmu0_int28_mask12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0}, + {"smmu0_int28_mask11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0}, + {"smmu0_int28_mask10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0}, + {"smmu0_int28_mask9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0}, + {"smmu0_int28_mask8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0}, + {"smmu0_int28_mask7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0}, + {"smmu0_int28_mask6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0}, + {"smmu0_int28_mask5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0}, + {"smmu0_int28_mask4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0}, + {"smmu0_int28_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0}, + {"smmu0_int28_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0}, + {"smmu0_int28_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0}, + {"smmu0_int28_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int28_status_reg[] = + { + {"smmu0_int28_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"smmu0_int28_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"smmu0_int28_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"smmu0_int28_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"smmu0_int28_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"smmu0_int28_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"smmu0_int28_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"smmu0_int28_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"smmu0_int28_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"smmu0_int28_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"smmu0_int28_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"smmu0_int28_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"smmu0_int28_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"smmu0_int28_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"smmu0_int28_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"smmu0_int28_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"smmu0_int28_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"smmu0_int28_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"smmu0_int28_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"smmu0_int28_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"smmu0_int28_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"smmu0_int28_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"smmu0_int28_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"smmu0_int28_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"smmu0_int28_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"smmu0_int28_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"smmu0_int28_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"smmu0_int28_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"smmu0_int28_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"smmu0_int28_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"smmu0_int28_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"smmu0_int28_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int29_en_reg[] = + { + {"smmu0_int29_en31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0}, + {"smmu0_int29_en30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0}, + {"smmu0_int29_en29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0}, + {"smmu0_int29_en28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0}, + {"smmu0_int29_en27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0}, + {"smmu0_int29_en26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0}, + {"smmu0_int29_en25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0}, + {"smmu0_int29_en24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0}, + {"smmu0_int29_en23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0}, + {"smmu0_int29_en22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0}, + {"smmu0_int29_en21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0}, + {"smmu0_int29_en20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0}, + {"smmu0_int29_en19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0}, + {"smmu0_int29_en18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0}, + {"smmu0_int29_en17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0}, + {"smmu0_int29_en16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0}, + {"smmu0_int29_en15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0}, + {"smmu0_int29_en14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0}, + {"smmu0_int29_en13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0}, + {"smmu0_int29_en12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0}, + {"smmu0_int29_en11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0}, + {"smmu0_int29_en10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0}, + {"smmu0_int29_en9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0}, + {"smmu0_int29_en8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0}, + {"smmu0_int29_en7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0}, + {"smmu0_int29_en6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0}, + {"smmu0_int29_en5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0}, + {"smmu0_int29_en4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0}, + {"smmu0_int29_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0}, + {"smmu0_int29_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0}, + {"smmu0_int29_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0}, + {"smmu0_int29_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int29_mask_reg[] = + { + {"smmu0_int29_mask31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0}, + {"smmu0_int29_mask30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0}, + {"smmu0_int29_mask29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0}, + {"smmu0_int29_mask28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0}, + {"smmu0_int29_mask27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0}, + {"smmu0_int29_mask26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0}, + {"smmu0_int29_mask25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0}, + {"smmu0_int29_mask24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0}, + {"smmu0_int29_mask23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0}, + {"smmu0_int29_mask22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0}, + {"smmu0_int29_mask21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0}, + {"smmu0_int29_mask20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0}, + {"smmu0_int29_mask19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0}, + {"smmu0_int29_mask18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0}, + {"smmu0_int29_mask17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0}, + {"smmu0_int29_mask16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0}, + {"smmu0_int29_mask15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0}, + {"smmu0_int29_mask14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0}, + {"smmu0_int29_mask13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0}, + {"smmu0_int29_mask12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0}, + {"smmu0_int29_mask11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0}, + {"smmu0_int29_mask10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0}, + {"smmu0_int29_mask9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0}, + {"smmu0_int29_mask8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0}, + {"smmu0_int29_mask7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0}, + {"smmu0_int29_mask6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0}, + {"smmu0_int29_mask5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0}, + {"smmu0_int29_mask4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0}, + {"smmu0_int29_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0}, + {"smmu0_int29_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0}, + {"smmu0_int29_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0}, + {"smmu0_int29_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int29_status_reg[] = + { + {"smmu0_int29_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"smmu0_int29_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"smmu0_int29_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"smmu0_int29_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"smmu0_int29_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"smmu0_int29_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"smmu0_int29_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"smmu0_int29_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"smmu0_int29_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"smmu0_int29_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"smmu0_int29_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"smmu0_int29_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"smmu0_int29_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"smmu0_int29_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"smmu0_int29_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"smmu0_int29_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"smmu0_int29_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"smmu0_int29_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"smmu0_int29_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"smmu0_int29_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"smmu0_int29_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"smmu0_int29_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"smmu0_int29_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"smmu0_int29_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"smmu0_int29_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"smmu0_int29_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"smmu0_int29_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"smmu0_int29_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"smmu0_int29_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"smmu0_int29_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"smmu0_int29_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"smmu0_int29_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int30_en_reg[] = + { + {"smmu0_int30_en31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0}, + {"smmu0_int30_en30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0}, + {"smmu0_int30_en29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0}, + {"smmu0_int30_en28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0}, + {"smmu0_int30_en27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0}, + {"smmu0_int30_en26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0}, + {"smmu0_int30_en25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0}, + {"smmu0_int30_en24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0}, + {"smmu0_int30_en23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0}, + {"smmu0_int30_en22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0}, + {"smmu0_int30_en21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0}, + {"smmu0_int30_en20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0}, + {"smmu0_int30_en19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0}, + {"smmu0_int30_en18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0}, + {"smmu0_int30_en17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0}, + {"smmu0_int30_en16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0}, + {"smmu0_int30_en15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0}, + {"smmu0_int30_en14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0}, + {"smmu0_int30_en13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0}, + {"smmu0_int30_en12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0}, + {"smmu0_int30_en11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0}, + {"smmu0_int30_en10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0}, + {"smmu0_int30_en9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0}, + {"smmu0_int30_en8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0}, + {"smmu0_int30_en7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0}, + {"smmu0_int30_en6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0}, + {"smmu0_int30_en5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0}, + {"smmu0_int30_en4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0}, + {"smmu0_int30_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0}, + {"smmu0_int30_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0}, + {"smmu0_int30_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0}, + {"smmu0_int30_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int30_mask_reg[] = + { + {"smmu0_int30_mask31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0}, + {"smmu0_int30_mask30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0}, + {"smmu0_int30_mask29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0}, + {"smmu0_int30_mask28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0}, + {"smmu0_int30_mask27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0}, + {"smmu0_int30_mask26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0}, + {"smmu0_int30_mask25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0}, + {"smmu0_int30_mask24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0}, + {"smmu0_int30_mask23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0}, + {"smmu0_int30_mask22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0}, + {"smmu0_int30_mask21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0}, + {"smmu0_int30_mask20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0}, + {"smmu0_int30_mask19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0}, + {"smmu0_int30_mask18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0}, + {"smmu0_int30_mask17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0}, + {"smmu0_int30_mask16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0}, + {"smmu0_int30_mask15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0}, + {"smmu0_int30_mask14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0}, + {"smmu0_int30_mask13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0}, + {"smmu0_int30_mask12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0}, + {"smmu0_int30_mask11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0}, + {"smmu0_int30_mask10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0}, + {"smmu0_int30_mask9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0}, + {"smmu0_int30_mask8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0}, + {"smmu0_int30_mask7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0}, + {"smmu0_int30_mask6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0}, + {"smmu0_int30_mask5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0}, + {"smmu0_int30_mask4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0}, + {"smmu0_int30_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0}, + {"smmu0_int30_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0}, + {"smmu0_int30_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0}, + {"smmu0_int30_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int30_status_reg[] = + { + {"smmu0_int30_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"smmu0_int30_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"smmu0_int30_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"smmu0_int30_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"smmu0_int30_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"smmu0_int30_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"smmu0_int30_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"smmu0_int30_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"smmu0_int30_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"smmu0_int30_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"smmu0_int30_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"smmu0_int30_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"smmu0_int30_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"smmu0_int30_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"smmu0_int30_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"smmu0_int30_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"smmu0_int30_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"smmu0_int30_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"smmu0_int30_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"smmu0_int30_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"smmu0_int30_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"smmu0_int30_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"smmu0_int30_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"smmu0_int30_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"smmu0_int30_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"smmu0_int30_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"smmu0_int30_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"smmu0_int30_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"smmu0_int30_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"smmu0_int30_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"smmu0_int30_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"smmu0_int30_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int31_en_reg[] = + { + {"smmu0_int31_en31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0}, + {"smmu0_int31_en30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0}, + {"smmu0_int31_en29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0}, + {"smmu0_int31_en28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0}, + {"smmu0_int31_en27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0}, + {"smmu0_int31_en26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0}, + {"smmu0_int31_en25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0}, + {"smmu0_int31_en24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0}, + {"smmu0_int31_en23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0}, + {"smmu0_int31_en22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0}, + {"smmu0_int31_en21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0}, + {"smmu0_int31_en20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0}, + {"smmu0_int31_en19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0}, + {"smmu0_int31_en18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0}, + {"smmu0_int31_en17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0}, + {"smmu0_int31_en16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0}, + {"smmu0_int31_en15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0}, + {"smmu0_int31_en14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0}, + {"smmu0_int31_en13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0}, + {"smmu0_int31_en12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0}, + {"smmu0_int31_en11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0}, + {"smmu0_int31_en10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0}, + {"smmu0_int31_en9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0}, + {"smmu0_int31_en8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0}, + {"smmu0_int31_en7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0}, + {"smmu0_int31_en6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0}, + {"smmu0_int31_en5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0}, + {"smmu0_int31_en4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0}, + {"smmu0_int31_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0}, + {"smmu0_int31_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0}, + {"smmu0_int31_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0}, + {"smmu0_int31_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int31_mask_reg[] = + { + {"smmu0_int31_mask31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0}, + {"smmu0_int31_mask30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0}, + {"smmu0_int31_mask29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0}, + {"smmu0_int31_mask28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0}, + {"smmu0_int31_mask27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0}, + {"smmu0_int31_mask26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0}, + {"smmu0_int31_mask25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0}, + {"smmu0_int31_mask24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0}, + {"smmu0_int31_mask23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0}, + {"smmu0_int31_mask22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0}, + {"smmu0_int31_mask21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0}, + {"smmu0_int31_mask20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0}, + {"smmu0_int31_mask19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0}, + {"smmu0_int31_mask18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0}, + {"smmu0_int31_mask17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0}, + {"smmu0_int31_mask16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0}, + {"smmu0_int31_mask15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0}, + {"smmu0_int31_mask14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0}, + {"smmu0_int31_mask13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0}, + {"smmu0_int31_mask12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0}, + {"smmu0_int31_mask11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0}, + {"smmu0_int31_mask10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0}, + {"smmu0_int31_mask9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0}, + {"smmu0_int31_mask8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0}, + {"smmu0_int31_mask7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0}, + {"smmu0_int31_mask6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0}, + {"smmu0_int31_mask5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0}, + {"smmu0_int31_mask4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0}, + {"smmu0_int31_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0}, + {"smmu0_int31_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0}, + {"smmu0_int31_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0}, + {"smmu0_int31_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int31_status_reg[] = + { + {"smmu0_int31_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"smmu0_int31_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"smmu0_int31_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"smmu0_int31_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"smmu0_int31_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"smmu0_int31_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"smmu0_int31_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"smmu0_int31_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"smmu0_int31_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"smmu0_int31_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"smmu0_int31_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"smmu0_int31_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"smmu0_int31_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"smmu0_int31_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"smmu0_int31_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"smmu0_int31_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"smmu0_int31_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"smmu0_int31_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"smmu0_int31_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"smmu0_int31_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"smmu0_int31_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"smmu0_int31_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"smmu0_int31_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"smmu0_int31_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"smmu0_int31_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"smmu0_int31_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"smmu0_int31_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"smmu0_int31_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"smmu0_int31_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"smmu0_int31_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"smmu0_int31_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"smmu0_int31_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int32_en_reg[] = + { + {"smmu0_int32_en31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0}, + {"smmu0_int32_en30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0}, + {"smmu0_int32_en29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0}, + {"smmu0_int32_en28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0}, + {"smmu0_int32_en27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0}, + {"smmu0_int32_en26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0}, + {"smmu0_int32_en25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0}, + {"smmu0_int32_en24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0}, + {"smmu0_int32_en23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0}, + {"smmu0_int32_en22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0}, + {"smmu0_int32_en21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0}, + {"smmu0_int32_en20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0}, + {"smmu0_int32_en19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0}, + {"smmu0_int32_en18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0}, + {"smmu0_int32_en17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0}, + {"smmu0_int32_en16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0}, + {"smmu0_int32_en15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0}, + {"smmu0_int32_en14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0}, + {"smmu0_int32_en13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0}, + {"smmu0_int32_en12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0}, + {"smmu0_int32_en11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0}, + {"smmu0_int32_en10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0}, + {"smmu0_int32_en9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0}, + {"smmu0_int32_en8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0}, + {"smmu0_int32_en7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0}, + {"smmu0_int32_en6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0}, + {"smmu0_int32_en5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0}, + {"smmu0_int32_en4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0}, + {"smmu0_int32_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0}, + {"smmu0_int32_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0}, + {"smmu0_int32_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0}, + {"smmu0_int32_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int32_mask_reg[] = + { + {"smmu0_int32_mask31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0}, + {"smmu0_int32_mask30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0}, + {"smmu0_int32_mask29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0}, + {"smmu0_int32_mask28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0}, + {"smmu0_int32_mask27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0}, + {"smmu0_int32_mask26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0}, + {"smmu0_int32_mask25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0}, + {"smmu0_int32_mask24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0}, + {"smmu0_int32_mask23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0}, + {"smmu0_int32_mask22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0}, + {"smmu0_int32_mask21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0}, + {"smmu0_int32_mask20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0}, + {"smmu0_int32_mask19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0}, + {"smmu0_int32_mask18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0}, + {"smmu0_int32_mask17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0}, + {"smmu0_int32_mask16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0}, + {"smmu0_int32_mask15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0}, + {"smmu0_int32_mask14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0}, + {"smmu0_int32_mask13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0}, + {"smmu0_int32_mask12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0}, + {"smmu0_int32_mask11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0}, + {"smmu0_int32_mask10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0}, + {"smmu0_int32_mask9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0}, + {"smmu0_int32_mask8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0}, + {"smmu0_int32_mask7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0}, + {"smmu0_int32_mask6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0}, + {"smmu0_int32_mask5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0}, + {"smmu0_int32_mask4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0}, + {"smmu0_int32_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0}, + {"smmu0_int32_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0}, + {"smmu0_int32_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0}, + {"smmu0_int32_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int32_status_reg[] = + { + {"smmu0_int32_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"smmu0_int32_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"smmu0_int32_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"smmu0_int32_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"smmu0_int32_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"smmu0_int32_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"smmu0_int32_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"smmu0_int32_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"smmu0_int32_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"smmu0_int32_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"smmu0_int32_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"smmu0_int32_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"smmu0_int32_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"smmu0_int32_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"smmu0_int32_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"smmu0_int32_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"smmu0_int32_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"smmu0_int32_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"smmu0_int32_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"smmu0_int32_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"smmu0_int32_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"smmu0_int32_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"smmu0_int32_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"smmu0_int32_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"smmu0_int32_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"smmu0_int32_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"smmu0_int32_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"smmu0_int32_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"smmu0_int32_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"smmu0_int32_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"smmu0_int32_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"smmu0_int32_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int33_en_reg[] = + { + {"smmu0_int33_en31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0}, + {"smmu0_int33_en30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0}, + {"smmu0_int33_en29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0}, + {"smmu0_int33_en28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0}, + {"smmu0_int33_en27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0}, + {"smmu0_int33_en26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0}, + {"smmu0_int33_en25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0}, + {"smmu0_int33_en24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0}, + {"smmu0_int33_en23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0}, + {"smmu0_int33_en22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0}, + {"smmu0_int33_en21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0}, + {"smmu0_int33_en20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0}, + {"smmu0_int33_en19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0}, + {"smmu0_int33_en18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0}, + {"smmu0_int33_en17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0}, + {"smmu0_int33_en16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0}, + {"smmu0_int33_en15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0}, + {"smmu0_int33_en14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0}, + {"smmu0_int33_en13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0}, + {"smmu0_int33_en12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0}, + {"smmu0_int33_en11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0}, + {"smmu0_int33_en10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0}, + {"smmu0_int33_en9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0}, + {"smmu0_int33_en8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0}, + {"smmu0_int33_en7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0}, + {"smmu0_int33_en6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0}, + {"smmu0_int33_en5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0}, + {"smmu0_int33_en4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0}, + {"smmu0_int33_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0}, + {"smmu0_int33_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0}, + {"smmu0_int33_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0}, + {"smmu0_int33_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int33_mask_reg[] = + { + {"smmu0_int33_mask31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0}, + {"smmu0_int33_mask30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0}, + {"smmu0_int33_mask29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0}, + {"smmu0_int33_mask28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0}, + {"smmu0_int33_mask27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0}, + {"smmu0_int33_mask26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0}, + {"smmu0_int33_mask25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0}, + {"smmu0_int33_mask24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0}, + {"smmu0_int33_mask23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0}, + {"smmu0_int33_mask22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0}, + {"smmu0_int33_mask21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0}, + {"smmu0_int33_mask20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0}, + {"smmu0_int33_mask19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0}, + {"smmu0_int33_mask18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0}, + {"smmu0_int33_mask17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0}, + {"smmu0_int33_mask16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0}, + {"smmu0_int33_mask15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0}, + {"smmu0_int33_mask14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0}, + {"smmu0_int33_mask13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0}, + {"smmu0_int33_mask12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0}, + {"smmu0_int33_mask11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0}, + {"smmu0_int33_mask10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0}, + {"smmu0_int33_mask9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0}, + {"smmu0_int33_mask8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0}, + {"smmu0_int33_mask7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0}, + {"smmu0_int33_mask6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0}, + {"smmu0_int33_mask5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0}, + {"smmu0_int33_mask4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0}, + {"smmu0_int33_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0}, + {"smmu0_int33_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0}, + {"smmu0_int33_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0}, + {"smmu0_int33_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int33_status_reg[] = + { + {"smmu0_int33_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"smmu0_int33_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"smmu0_int33_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"smmu0_int33_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"smmu0_int33_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"smmu0_int33_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"smmu0_int33_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"smmu0_int33_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"smmu0_int33_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"smmu0_int33_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"smmu0_int33_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"smmu0_int33_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"smmu0_int33_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"smmu0_int33_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"smmu0_int33_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"smmu0_int33_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"smmu0_int33_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"smmu0_int33_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"smmu0_int33_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"smmu0_int33_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"smmu0_int33_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"smmu0_int33_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"smmu0_int33_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"smmu0_int33_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"smmu0_int33_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"smmu0_int33_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"smmu0_int33_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"smmu0_int33_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"smmu0_int33_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"smmu0_int33_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"smmu0_int33_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"smmu0_int33_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int34_en_reg[] = + { + {"smmu0_int34_en31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0}, + {"smmu0_int34_en30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0}, + {"smmu0_int34_en29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0}, + {"smmu0_int34_en28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0}, + {"smmu0_int34_en27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0}, + {"smmu0_int34_en26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0}, + {"smmu0_int34_en25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0}, + {"smmu0_int34_en24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0}, + {"smmu0_int34_en23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0}, + {"smmu0_int34_en22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0}, + {"smmu0_int34_en21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0}, + {"smmu0_int34_en20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0}, + {"smmu0_int34_en19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0}, + {"smmu0_int34_en18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0}, + {"smmu0_int34_en17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0}, + {"smmu0_int34_en16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0}, + {"smmu0_int34_en15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0}, + {"smmu0_int34_en14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0}, + {"smmu0_int34_en13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0}, + {"smmu0_int34_en12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0}, + {"smmu0_int34_en11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0}, + {"smmu0_int34_en10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0}, + {"smmu0_int34_en9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0}, + {"smmu0_int34_en8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0}, + {"smmu0_int34_en7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0}, + {"smmu0_int34_en6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0}, + {"smmu0_int34_en5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0}, + {"smmu0_int34_en4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0}, + {"smmu0_int34_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0}, + {"smmu0_int34_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0}, + {"smmu0_int34_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0}, + {"smmu0_int34_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int34_mask_reg[] = + { + {"smmu0_int34_mask31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0}, + {"smmu0_int34_mask30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0}, + {"smmu0_int34_mask29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0}, + {"smmu0_int34_mask28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0}, + {"smmu0_int34_mask27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0}, + {"smmu0_int34_mask26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0}, + {"smmu0_int34_mask25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0}, + {"smmu0_int34_mask24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0}, + {"smmu0_int34_mask23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0}, + {"smmu0_int34_mask22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0}, + {"smmu0_int34_mask21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0}, + {"smmu0_int34_mask20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0}, + {"smmu0_int34_mask19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0}, + {"smmu0_int34_mask18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0}, + {"smmu0_int34_mask17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0}, + {"smmu0_int34_mask16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0}, + {"smmu0_int34_mask15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0}, + {"smmu0_int34_mask14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0}, + {"smmu0_int34_mask13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0}, + {"smmu0_int34_mask12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0}, + {"smmu0_int34_mask11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0}, + {"smmu0_int34_mask10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0}, + {"smmu0_int34_mask9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0}, + {"smmu0_int34_mask8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0}, + {"smmu0_int34_mask7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0}, + {"smmu0_int34_mask6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0}, + {"smmu0_int34_mask5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0}, + {"smmu0_int34_mask4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0}, + {"smmu0_int34_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0}, + {"smmu0_int34_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0}, + {"smmu0_int34_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0}, + {"smmu0_int34_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int34_status_reg[] = + { + {"smmu0_int34_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"smmu0_int34_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"smmu0_int34_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"smmu0_int34_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"smmu0_int34_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"smmu0_int34_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"smmu0_int34_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"smmu0_int34_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"smmu0_int34_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"smmu0_int34_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"smmu0_int34_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"smmu0_int34_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"smmu0_int34_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"smmu0_int34_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"smmu0_int34_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"smmu0_int34_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"smmu0_int34_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"smmu0_int34_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"smmu0_int34_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"smmu0_int34_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"smmu0_int34_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"smmu0_int34_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"smmu0_int34_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"smmu0_int34_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"smmu0_int34_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"smmu0_int34_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"smmu0_int34_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"smmu0_int34_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"smmu0_int34_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"smmu0_int34_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"smmu0_int34_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"smmu0_int34_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int35_en_reg[] = + { + {"smmu0_int35_en0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int35_mask_reg[] = + { + {"smmu0_int35_mask0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int35_status_reg[] = + { + {"smmu0_int35_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int36_en_reg[] = + { + {"smmu0_int36_en0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int36_mask_reg[] = + { + {"smmu0_int36_mask0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int36_status_reg[] = + { + {"smmu0_int36_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int37_en_reg[] = + { + {"smmu0_int37_en0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int37_mask_reg[] = + { + {"smmu0_int37_mask0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int37_status_reg[] = + { + {"smmu0_int37_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int38_en_reg[] = + { + {"smmu0_int38_en0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int38_mask_reg[] = + { + {"smmu0_int38_mask0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int38_status_reg[] = + { + {"smmu0_int38_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int39_en_reg[] = + { + {"smmu0_int39_en0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int39_mask_reg[] = + { + {"smmu0_int39_mask0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int39_status_reg[] = + { + {"smmu0_int39_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int40_en_reg[] = + { + {"smmu0_int40_en0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int40_mask_reg[] = + { + {"smmu0_int40_mask0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int40_status_reg[] = + { + {"smmu0_int40_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int41_en_reg[] = + { + {"smmu0_int41_en0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int41_mask_reg[] = + { + {"smmu0_int41_mask0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int41_status_reg[] = + { + {"smmu0_int41_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int42_en_reg[] = + { + {"smmu0_int42_en0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int42_mask_reg[] = + { + {"smmu0_int42_mask0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int42_status_reg[] = + { + {"smmu0_int42_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int43_en_reg[] = + { + {"smmu0_int43_en0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int43_mask_reg[] = + { + {"smmu0_int43_mask0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int43_status_reg[] = + { + {"smmu0_int43_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int44_en_reg[] = + { + {"smmu0_int44_en0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int44_mask_reg[] = + { + {"smmu0_int44_mask0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int44_status_reg[] = + { + {"smmu0_int44_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int45_en_reg[] = + { + {"smmu0_int45_en0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int45_mask_reg[] = + { + {"smmu0_int45_mask0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int45_status_reg[] = + { + {"smmu0_int45_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int46_en_reg[] = + { + {"smmu0_int46_en0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int46_mask_reg[] = + { + {"smmu0_int46_mask0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int46_status_reg[] = + { + {"smmu0_int46_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int47_en_reg[] = + { + {"smmu0_int47_en0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int47_mask_reg[] = + { + {"smmu0_int47_mask0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int47_status_reg[] = + { + {"smmu0_int47_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int48_en_reg[] = + { + {"smmu0_int48_en0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int48_mask_reg[] = + { + {"smmu0_int48_mask0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int48_status_reg[] = + { + {"smmu0_int48_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int49_en_reg[] = + { + {"smmu0_int49_en0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int49_mask_reg[] = + { + {"smmu0_int49_mask0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int49_status_reg[] = + { + {"smmu0_int49_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int50_en_reg[] = + { + {"smmu0_int50_en0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int50_mask_reg[] = + { + {"smmu0_int50_mask0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int50_status_reg[] = + { + {"smmu0_int50_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int51_en_reg[] = + { + {"smmu0_int51_en0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int51_mask_reg[] = + { + {"smmu0_int51_mask0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int51_status_reg[] = + { + {"smmu0_int51_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int52_en_reg[] = + { + {"smmu0_int52_en0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int52_mask_reg[] = + { + {"smmu0_int52_mask0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int52_status_reg[] = + { + {"smmu0_int52_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int53_en_reg[] = + { + {"smmu0_int53_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0}, + {"smmu0_int53_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0}, + {"smmu0_int53_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0}, + {"smmu0_int53_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int53_mask_reg[] = + { + {"smmu0_int53_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0}, + {"smmu0_int53_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0}, + {"smmu0_int53_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0}, + {"smmu0_int53_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_int53_status_reg[] = + { + {"smmu0_int53_status15", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"smmu0_int53_status14", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"smmu0_int53_status13", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"smmu0_int53_status12", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl0_arbiter_ecc_bypass_reg[] = + { + {"ctrl1_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0}, + {"ctrl1_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0}, + {"ctrl1_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0}, + {"ctrl1_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0}, + {"ctrl1_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0}, + {"ctrl1_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0}, + {"ctrl1_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0}, + {"ctrl1_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0}, + {"ctrl1_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0}, + {"ctrl1_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0}, + {"ctrl1_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0}, + {"ctrl1_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0}, + {"ctrl1_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0}, + {"ctrl1_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0}, + {"ctrl1_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0}, + {"ctrl1_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0}, + {"ctrl0_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0}, + {"ctrl0_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0}, + {"ctrl0_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0}, + {"ctrl0_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0}, + {"ctrl0_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0}, + {"ctrl0_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0}, + {"ctrl0_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0}, + {"ctrl0_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0}, + {"ctrl0_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0}, + {"ctrl0_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0}, + {"ctrl0_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0}, + {"ctrl0_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0}, + {"ctrl0_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0}, + {"ctrl0_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0}, + {"ctrl0_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0}, + {"ctrl0_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl2_arbiter_ecc_bypass_reg[] = + { + {"ctrl3_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0}, + {"ctrl3_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0}, + {"ctrl3_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0}, + {"ctrl3_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0}, + {"ctrl3_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0}, + {"ctrl3_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0}, + {"ctrl3_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0}, + {"ctrl3_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0}, + {"ctrl3_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0}, + {"ctrl3_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0}, + {"ctrl3_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0}, + {"ctrl3_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0}, + {"ctrl3_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0}, + {"ctrl3_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0}, + {"ctrl3_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0}, + {"ctrl3_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0}, + {"ctrl2_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0}, + {"ctrl2_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0}, + {"ctrl2_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0}, + {"ctrl2_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0}, + {"ctrl2_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0}, + {"ctrl2_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0}, + {"ctrl2_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0}, + {"ctrl2_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0}, + {"ctrl2_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0}, + {"ctrl2_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0}, + {"ctrl2_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0}, + {"ctrl2_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0}, + {"ctrl2_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0}, + {"ctrl2_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0}, + {"ctrl2_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0}, + {"ctrl2_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl4_arbiter_ecc_bypass_reg[] = + { + {"ctrl5_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0}, + {"ctrl5_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0}, + {"ctrl5_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0}, + {"ctrl5_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0}, + {"ctrl5_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0}, + {"ctrl5_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0}, + {"ctrl5_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0}, + {"ctrl5_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0}, + {"ctrl5_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0}, + {"ctrl5_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0}, + {"ctrl5_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0}, + {"ctrl5_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0}, + {"ctrl5_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0}, + {"ctrl5_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0}, + {"ctrl5_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0}, + {"ctrl5_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0}, + {"ctrl4_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0}, + {"ctrl4_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0}, + {"ctrl4_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0}, + {"ctrl4_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0}, + {"ctrl4_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0}, + {"ctrl4_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0}, + {"ctrl4_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0}, + {"ctrl4_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0}, + {"ctrl4_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0}, + {"ctrl4_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0}, + {"ctrl4_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0}, + {"ctrl4_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0}, + {"ctrl4_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0}, + {"ctrl4_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0}, + {"ctrl4_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0}, + {"ctrl4_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl6_arbiter_ecc_bypass_reg[] = + { + {"ctrl7_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0}, + {"ctrl7_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0}, + {"ctrl7_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0}, + {"ctrl7_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0}, + {"ctrl7_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0}, + {"ctrl7_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0}, + {"ctrl7_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0}, + {"ctrl7_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0}, + {"ctrl7_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0}, + {"ctrl7_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0}, + {"ctrl7_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0}, + {"ctrl7_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0}, + {"ctrl7_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0}, + {"ctrl7_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0}, + {"ctrl7_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0}, + {"ctrl7_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0}, + {"ctrl6_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0}, + {"ctrl6_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0}, + {"ctrl6_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0}, + {"ctrl6_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0}, + {"ctrl6_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0}, + {"ctrl6_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0}, + {"ctrl6_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0}, + {"ctrl6_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0}, + {"ctrl6_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0}, + {"ctrl6_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0}, + {"ctrl6_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0}, + {"ctrl6_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0}, + {"ctrl6_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0}, + {"ctrl6_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0}, + {"ctrl6_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0}, + {"ctrl6_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl8_arbiter_ecc_bypass_reg[] = + { + {"ctrl9_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0}, + {"ctrl9_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0}, + {"ctrl9_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0}, + {"ctrl9_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0}, + {"ctrl9_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0}, + {"ctrl9_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0}, + {"ctrl9_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0}, + {"ctrl9_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0}, + {"ctrl9_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0}, + {"ctrl9_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0}, + {"ctrl9_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0}, + {"ctrl9_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0}, + {"ctrl9_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0}, + {"ctrl9_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0}, + {"ctrl9_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0}, + {"ctrl9_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0}, + {"ctrl8_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0}, + {"ctrl8_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0}, + {"ctrl8_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0}, + {"ctrl8_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0}, + {"ctrl8_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0}, + {"ctrl8_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0}, + {"ctrl8_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0}, + {"ctrl8_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0}, + {"ctrl8_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0}, + {"ctrl8_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0}, + {"ctrl8_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0}, + {"ctrl8_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0}, + {"ctrl8_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0}, + {"ctrl8_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0}, + {"ctrl8_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0}, + {"ctrl8_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl10_arbiter_ecc_bypass_reg[] = + { + {"ctrl11_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0}, + {"ctrl11_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0}, + {"ctrl11_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0}, + {"ctrl11_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0}, + {"ctrl11_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0}, + {"ctrl11_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0}, + {"ctrl11_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0}, + {"ctrl11_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0}, + {"ctrl11_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0}, + {"ctrl11_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0}, + {"ctrl11_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0}, + {"ctrl11_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0}, + {"ctrl11_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0}, + {"ctrl11_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0}, + {"ctrl11_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0}, + {"ctrl11_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0}, + {"ctrl10_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0}, + {"ctrl10_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0}, + {"ctrl10_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0}, + {"ctrl10_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0}, + {"ctrl10_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0}, + {"ctrl10_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0}, + {"ctrl10_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0}, + {"ctrl10_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0}, + {"ctrl10_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0}, + {"ctrl10_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0}, + {"ctrl10_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0}, + {"ctrl10_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0}, + {"ctrl10_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0}, + {"ctrl10_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0}, + {"ctrl10_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0}, + {"ctrl10_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl12_arbiter_ecc_bypass_reg[] = + { + {"ctrl13_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0}, + {"ctrl13_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0}, + {"ctrl13_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0}, + {"ctrl13_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0}, + {"ctrl13_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0}, + {"ctrl13_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0}, + {"ctrl13_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0}, + {"ctrl13_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0}, + {"ctrl13_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0}, + {"ctrl13_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0}, + {"ctrl13_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0}, + {"ctrl13_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0}, + {"ctrl13_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0}, + {"ctrl13_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0}, + {"ctrl13_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0}, + {"ctrl13_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0}, + {"ctrl12_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0}, + {"ctrl12_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0}, + {"ctrl12_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0}, + {"ctrl12_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0}, + {"ctrl12_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0}, + {"ctrl12_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0}, + {"ctrl12_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0}, + {"ctrl12_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0}, + {"ctrl12_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0}, + {"ctrl12_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0}, + {"ctrl12_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0}, + {"ctrl12_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0}, + {"ctrl12_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0}, + {"ctrl12_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0}, + {"ctrl12_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0}, + {"ctrl12_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl14_arbiter_ecc_bypass_reg[] = + { + {"ctrl15_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0}, + {"ctrl15_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0}, + {"ctrl15_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0}, + {"ctrl15_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0}, + {"ctrl15_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0}, + {"ctrl15_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0}, + {"ctrl15_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0}, + {"ctrl15_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0}, + {"ctrl15_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0}, + {"ctrl15_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0}, + {"ctrl15_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0}, + {"ctrl15_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0}, + {"ctrl15_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0}, + {"ctrl15_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0}, + {"ctrl15_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0}, + {"ctrl15_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0}, + {"ctrl14_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0}, + {"ctrl14_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0}, + {"ctrl14_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0}, + {"ctrl14_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0}, + {"ctrl14_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0}, + {"ctrl14_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0}, + {"ctrl14_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0}, + {"ctrl14_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0}, + {"ctrl14_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0}, + {"ctrl14_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0}, + {"ctrl14_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0}, + {"ctrl14_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0}, + {"ctrl14_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0}, + {"ctrl14_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0}, + {"ctrl14_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0}, + {"ctrl14_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl16_arbiter_ecc_bypass_reg[] = + { + {"ctrl17_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0}, + {"ctrl17_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0}, + {"ctrl17_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0}, + {"ctrl17_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0}, + {"ctrl17_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0}, + {"ctrl17_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0}, + {"ctrl17_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0}, + {"ctrl17_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0}, + {"ctrl17_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0}, + {"ctrl17_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0}, + {"ctrl17_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0}, + {"ctrl17_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0}, + {"ctrl17_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0}, + {"ctrl17_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0}, + {"ctrl17_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0}, + {"ctrl17_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0}, + {"ctrl16_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0}, + {"ctrl16_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0}, + {"ctrl16_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0}, + {"ctrl16_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0}, + {"ctrl16_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0}, + {"ctrl16_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0}, + {"ctrl16_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0}, + {"ctrl16_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0}, + {"ctrl16_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0}, + {"ctrl16_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0}, + {"ctrl16_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0}, + {"ctrl16_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0}, + {"ctrl16_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0}, + {"ctrl16_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0}, + {"ctrl16_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0}, + {"ctrl16_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl18_arbiter_ecc_bypass_reg[] = + { + {"ctrl19_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0}, + {"ctrl19_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0}, + {"ctrl19_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0}, + {"ctrl19_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0}, + {"ctrl19_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0}, + {"ctrl19_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0}, + {"ctrl19_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0}, + {"ctrl19_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0}, + {"ctrl19_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0}, + {"ctrl19_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0}, + {"ctrl19_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0}, + {"ctrl19_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0}, + {"ctrl19_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0}, + {"ctrl19_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0}, + {"ctrl19_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0}, + {"ctrl19_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0}, + {"ctrl18_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0}, + {"ctrl18_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0}, + {"ctrl18_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0}, + {"ctrl18_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0}, + {"ctrl18_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0}, + {"ctrl18_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0}, + {"ctrl18_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0}, + {"ctrl18_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0}, + {"ctrl18_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0}, + {"ctrl18_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0}, + {"ctrl18_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0}, + {"ctrl18_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0}, + {"ctrl18_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0}, + {"ctrl18_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0}, + {"ctrl18_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0}, + {"ctrl18_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl20_arbiter_ecc_bypass_reg[] = + { + {"ctrl21_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0}, + {"ctrl21_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0}, + {"ctrl21_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0}, + {"ctrl21_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0}, + {"ctrl21_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0}, + {"ctrl21_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0}, + {"ctrl21_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0}, + {"ctrl21_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0}, + {"ctrl21_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0}, + {"ctrl21_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0}, + {"ctrl21_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0}, + {"ctrl21_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0}, + {"ctrl21_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0}, + {"ctrl21_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0}, + {"ctrl21_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0}, + {"ctrl21_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0}, + {"ctrl20_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0}, + {"ctrl20_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0}, + {"ctrl20_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0}, + {"ctrl20_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0}, + {"ctrl20_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0}, + {"ctrl20_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0}, + {"ctrl20_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0}, + {"ctrl20_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0}, + {"ctrl20_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0}, + {"ctrl20_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0}, + {"ctrl20_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0}, + {"ctrl20_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0}, + {"ctrl20_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0}, + {"ctrl20_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0}, + {"ctrl20_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0}, + {"ctrl20_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl22_arbiter_ecc_bypass_reg[] = + { + {"ctrl23_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0}, + {"ctrl23_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0}, + {"ctrl23_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0}, + {"ctrl23_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0}, + {"ctrl23_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0}, + {"ctrl23_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0}, + {"ctrl23_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0}, + {"ctrl23_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0}, + {"ctrl23_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0}, + {"ctrl23_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0}, + {"ctrl23_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0}, + {"ctrl23_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0}, + {"ctrl23_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0}, + {"ctrl23_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0}, + {"ctrl23_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0}, + {"ctrl23_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0}, + {"ctrl22_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0}, + {"ctrl22_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0}, + {"ctrl22_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0}, + {"ctrl22_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0}, + {"ctrl22_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0}, + {"ctrl22_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0}, + {"ctrl22_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0}, + {"ctrl22_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0}, + {"ctrl22_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0}, + {"ctrl22_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0}, + {"ctrl22_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0}, + {"ctrl22_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0}, + {"ctrl22_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0}, + {"ctrl22_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0}, + {"ctrl22_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0}, + {"ctrl22_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl24_arbiter_ecc_bypass_reg[] = + { + {"ctrl25_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0}, + {"ctrl25_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0}, + {"ctrl25_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0}, + {"ctrl25_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0}, + {"ctrl25_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0}, + {"ctrl25_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0}, + {"ctrl25_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0}, + {"ctrl25_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0}, + {"ctrl25_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0}, + {"ctrl25_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0}, + {"ctrl25_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0}, + {"ctrl25_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0}, + {"ctrl25_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0}, + {"ctrl25_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0}, + {"ctrl25_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0}, + {"ctrl25_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0}, + {"ctrl24_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0}, + {"ctrl24_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0}, + {"ctrl24_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0}, + {"ctrl24_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0}, + {"ctrl24_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0}, + {"ctrl24_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0}, + {"ctrl24_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0}, + {"ctrl24_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0}, + {"ctrl24_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0}, + {"ctrl24_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0}, + {"ctrl24_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0}, + {"ctrl24_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0}, + {"ctrl24_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0}, + {"ctrl24_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0}, + {"ctrl24_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0}, + {"ctrl24_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl26_arbiter_ecc_bypass_reg[] = + { + {"ctrl27_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0}, + {"ctrl27_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0}, + {"ctrl27_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0}, + {"ctrl27_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0}, + {"ctrl27_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0}, + {"ctrl27_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0}, + {"ctrl27_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0}, + {"ctrl27_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0}, + {"ctrl27_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0}, + {"ctrl27_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0}, + {"ctrl27_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0}, + {"ctrl27_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0}, + {"ctrl27_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0}, + {"ctrl27_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0}, + {"ctrl27_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0}, + {"ctrl27_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0}, + {"ctrl26_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0}, + {"ctrl26_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0}, + {"ctrl26_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0}, + {"ctrl26_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0}, + {"ctrl26_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0}, + {"ctrl26_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0}, + {"ctrl26_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0}, + {"ctrl26_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0}, + {"ctrl26_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0}, + {"ctrl26_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0}, + {"ctrl26_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0}, + {"ctrl26_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0}, + {"ctrl26_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0}, + {"ctrl26_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0}, + {"ctrl26_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0}, + {"ctrl26_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl28_arbiter_ecc_bypass_reg[] = + { + {"ctrl29_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0}, + {"ctrl29_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0}, + {"ctrl29_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0}, + {"ctrl29_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0}, + {"ctrl29_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0}, + {"ctrl29_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0}, + {"ctrl29_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0}, + {"ctrl29_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0}, + {"ctrl29_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0}, + {"ctrl29_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0}, + {"ctrl29_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0}, + {"ctrl29_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0}, + {"ctrl29_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0}, + {"ctrl29_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0}, + {"ctrl29_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0}, + {"ctrl29_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0}, + {"ctrl28_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0}, + {"ctrl28_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0}, + {"ctrl28_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0}, + {"ctrl28_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0}, + {"ctrl28_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0}, + {"ctrl28_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0}, + {"ctrl28_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0}, + {"ctrl28_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0}, + {"ctrl28_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0}, + {"ctrl28_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0}, + {"ctrl28_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0}, + {"ctrl28_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0}, + {"ctrl28_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0}, + {"ctrl28_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0}, + {"ctrl28_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0}, + {"ctrl28_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl30_arbiter_ecc_bypass_reg[] = + { + {"ctrl31_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0}, + {"ctrl31_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0}, + {"ctrl31_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0}, + {"ctrl31_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0}, + {"ctrl31_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0}, + {"ctrl31_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0}, + {"ctrl31_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0}, + {"ctrl31_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0}, + {"ctrl31_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0}, + {"ctrl31_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0}, + {"ctrl31_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0}, + {"ctrl31_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0}, + {"ctrl31_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0}, + {"ctrl31_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0}, + {"ctrl31_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0}, + {"ctrl31_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0}, + {"ctrl30_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0}, + {"ctrl30_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0}, + {"ctrl30_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0}, + {"ctrl30_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0}, + {"ctrl30_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0}, + {"ctrl30_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0}, + {"ctrl30_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0}, + {"ctrl30_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0}, + {"ctrl30_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0}, + {"ctrl30_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0}, + {"ctrl30_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0}, + {"ctrl30_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0}, + {"ctrl30_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0}, + {"ctrl30_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0}, + {"ctrl30_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0}, + {"ctrl30_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl_req_ecc_bypass_reg[] = + { + {"ctrl_req_ecc_bypass_0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl_info_ecc_bypass_reg[] = + { + {"ctrl_info_ecc_bypass_0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_rschd_ecc_bypass_reg[] = + { + {"smmu0_rschd_ecc_bypass_0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_wr_ecc_bypass_reg[] = + { + {"smmu0_wr_ecc_bypass1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0}, + {"smmu0_wr_ecc_bypass0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl0_arbiter_ecc_err_reg[] = + { + {"ctrl0_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"ctrl0_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"ctrl0_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"ctrl0_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"ctrl0_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"ctrl0_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"ctrl0_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"ctrl0_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"ctrl0_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"ctrl0_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"ctrl0_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"ctrl0_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"ctrl0_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"ctrl0_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"ctrl0_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"ctrl0_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"ctrl0_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"ctrl0_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"ctrl0_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"ctrl0_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"ctrl0_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"ctrl0_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"ctrl0_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"ctrl0_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"ctrl0_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"ctrl0_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"ctrl0_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"ctrl0_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"ctrl0_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"ctrl0_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"ctrl0_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"ctrl0_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl1_arbiter_ecc_err_reg[] = + { + {"ctrl1_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"ctrl1_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"ctrl1_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"ctrl1_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"ctrl1_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"ctrl1_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"ctrl1_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"ctrl1_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"ctrl1_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"ctrl1_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"ctrl1_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"ctrl1_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"ctrl1_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"ctrl1_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"ctrl1_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"ctrl1_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"ctrl1_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"ctrl1_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"ctrl1_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"ctrl1_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"ctrl1_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"ctrl1_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"ctrl1_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"ctrl1_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"ctrl1_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"ctrl1_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"ctrl1_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"ctrl1_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"ctrl1_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"ctrl1_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"ctrl1_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"ctrl1_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl2_arbiter_ecc_err_reg[] = + { + {"ctrl2_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"ctrl2_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"ctrl2_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"ctrl2_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"ctrl2_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"ctrl2_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"ctrl2_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"ctrl2_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"ctrl2_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"ctrl2_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"ctrl2_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"ctrl2_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"ctrl2_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"ctrl2_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"ctrl2_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"ctrl2_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"ctrl2_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"ctrl2_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"ctrl2_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"ctrl2_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"ctrl2_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"ctrl2_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"ctrl2_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"ctrl2_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"ctrl2_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"ctrl2_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"ctrl2_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"ctrl2_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"ctrl2_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"ctrl2_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"ctrl2_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"ctrl2_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl3_arbiter_ecc_err_reg[] = + { + {"ctrl3_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"ctrl3_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"ctrl3_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"ctrl3_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"ctrl3_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"ctrl3_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"ctrl3_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"ctrl3_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"ctrl3_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"ctrl3_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"ctrl3_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"ctrl3_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"ctrl3_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"ctrl3_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"ctrl3_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"ctrl3_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"ctrl3_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"ctrl3_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"ctrl3_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"ctrl3_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"ctrl3_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"ctrl3_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"ctrl3_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"ctrl3_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"ctrl3_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"ctrl3_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"ctrl3_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"ctrl3_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"ctrl3_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"ctrl3_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"ctrl3_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"ctrl3_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl4_arbiter_ecc_err_reg[] = + { + {"ctrl4_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"ctrl4_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"ctrl4_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"ctrl4_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"ctrl4_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"ctrl4_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"ctrl4_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"ctrl4_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"ctrl4_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"ctrl4_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"ctrl4_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"ctrl4_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"ctrl4_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"ctrl4_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"ctrl4_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"ctrl4_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"ctrl4_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"ctrl4_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"ctrl4_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"ctrl4_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"ctrl4_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"ctrl4_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"ctrl4_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"ctrl4_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"ctrl4_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"ctrl4_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"ctrl4_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"ctrl4_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"ctrl4_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"ctrl4_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"ctrl4_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"ctrl4_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl5_arbiter_ecc_err_reg[] = + { + {"ctrl5_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"ctrl5_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"ctrl5_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"ctrl5_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"ctrl5_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"ctrl5_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"ctrl5_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"ctrl5_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"ctrl5_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"ctrl5_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"ctrl5_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"ctrl5_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"ctrl5_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"ctrl5_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"ctrl5_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"ctrl5_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"ctrl5_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"ctrl5_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"ctrl5_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"ctrl5_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"ctrl5_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"ctrl5_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"ctrl5_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"ctrl5_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"ctrl5_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"ctrl5_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"ctrl5_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"ctrl5_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"ctrl5_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"ctrl5_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"ctrl5_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"ctrl5_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl6_arbiter_ecc_err_reg[] = + { + {"ctrl6_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"ctrl6_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"ctrl6_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"ctrl6_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"ctrl6_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"ctrl6_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"ctrl6_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"ctrl6_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"ctrl6_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"ctrl6_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"ctrl6_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"ctrl6_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"ctrl6_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"ctrl6_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"ctrl6_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"ctrl6_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"ctrl6_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"ctrl6_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"ctrl6_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"ctrl6_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"ctrl6_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"ctrl6_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"ctrl6_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"ctrl6_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"ctrl6_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"ctrl6_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"ctrl6_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"ctrl6_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"ctrl6_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"ctrl6_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"ctrl6_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"ctrl6_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl7_arbiter_ecc_err_reg[] = + { + {"ctrl7_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"ctrl7_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"ctrl7_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"ctrl7_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"ctrl7_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"ctrl7_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"ctrl7_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"ctrl7_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"ctrl7_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"ctrl7_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"ctrl7_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"ctrl7_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"ctrl7_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"ctrl7_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"ctrl7_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"ctrl7_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"ctrl7_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"ctrl7_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"ctrl7_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"ctrl7_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"ctrl7_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"ctrl7_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"ctrl7_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"ctrl7_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"ctrl7_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"ctrl7_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"ctrl7_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"ctrl7_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"ctrl7_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"ctrl7_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"ctrl7_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"ctrl7_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl8_arbiter_ecc_err_reg[] = + { + {"ctrl8_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"ctrl8_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"ctrl8_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"ctrl8_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"ctrl8_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"ctrl8_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"ctrl8_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"ctrl8_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"ctrl8_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"ctrl8_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"ctrl8_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"ctrl8_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"ctrl8_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"ctrl8_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"ctrl8_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"ctrl8_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"ctrl8_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"ctrl8_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"ctrl8_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"ctrl8_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"ctrl8_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"ctrl8_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"ctrl8_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"ctrl8_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"ctrl8_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"ctrl8_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"ctrl8_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"ctrl8_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"ctrl8_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"ctrl8_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"ctrl8_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"ctrl8_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl9_arbiter_ecc_err_reg[] = + { + {"ctrl9_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"ctrl9_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"ctrl9_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"ctrl9_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"ctrl9_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"ctrl9_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"ctrl9_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"ctrl9_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"ctrl9_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"ctrl9_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"ctrl9_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"ctrl9_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"ctrl9_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"ctrl9_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"ctrl9_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"ctrl9_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"ctrl9_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"ctrl9_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"ctrl9_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"ctrl9_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"ctrl9_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"ctrl9_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"ctrl9_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"ctrl9_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"ctrl9_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"ctrl9_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"ctrl9_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"ctrl9_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"ctrl9_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"ctrl9_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"ctrl9_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"ctrl9_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl10_arbiter_ecc_err_reg[] = + { + {"ctrl10_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"ctrl10_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"ctrl10_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"ctrl10_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"ctrl10_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"ctrl10_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"ctrl10_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"ctrl10_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"ctrl10_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"ctrl10_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"ctrl10_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"ctrl10_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"ctrl10_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"ctrl10_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"ctrl10_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"ctrl10_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"ctrl10_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"ctrl10_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"ctrl10_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"ctrl10_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"ctrl10_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"ctrl10_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"ctrl10_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"ctrl10_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"ctrl10_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"ctrl10_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"ctrl10_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"ctrl10_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"ctrl10_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"ctrl10_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"ctrl10_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"ctrl10_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl11_arbiter_ecc_err_reg[] = + { + {"ctrl11_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"ctrl11_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"ctrl11_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"ctrl11_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"ctrl11_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"ctrl11_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"ctrl11_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"ctrl11_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"ctrl11_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"ctrl11_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"ctrl11_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"ctrl11_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"ctrl11_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"ctrl11_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"ctrl11_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"ctrl11_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"ctrl11_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"ctrl11_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"ctrl11_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"ctrl11_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"ctrl11_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"ctrl11_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"ctrl11_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"ctrl11_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"ctrl11_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"ctrl11_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"ctrl11_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"ctrl11_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"ctrl11_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"ctrl11_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"ctrl11_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"ctrl11_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl12_arbiter_ecc_err_reg[] = + { + {"ctrl12_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"ctrl12_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"ctrl12_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"ctrl12_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"ctrl12_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"ctrl12_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"ctrl12_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"ctrl12_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"ctrl12_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"ctrl12_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"ctrl12_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"ctrl12_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"ctrl12_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"ctrl12_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"ctrl12_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"ctrl12_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"ctrl12_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"ctrl12_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"ctrl12_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"ctrl12_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"ctrl12_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"ctrl12_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"ctrl12_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"ctrl12_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"ctrl12_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"ctrl12_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"ctrl12_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"ctrl12_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"ctrl12_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"ctrl12_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"ctrl12_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"ctrl12_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl13_arbiter_ecc_err_reg[] = + { + {"ctrl13_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"ctrl13_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"ctrl13_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"ctrl13_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"ctrl13_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"ctrl13_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"ctrl13_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"ctrl13_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"ctrl13_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"ctrl13_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"ctrl13_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"ctrl13_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"ctrl13_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"ctrl13_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"ctrl13_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"ctrl13_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"ctrl13_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"ctrl13_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"ctrl13_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"ctrl13_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"ctrl13_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"ctrl13_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"ctrl13_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"ctrl13_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"ctrl13_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"ctrl13_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"ctrl13_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"ctrl13_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"ctrl13_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"ctrl13_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"ctrl13_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"ctrl13_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl14_arbiter_ecc_err_reg[] = + { + {"ctrl14_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"ctrl14_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"ctrl14_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"ctrl14_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"ctrl14_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"ctrl14_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"ctrl14_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"ctrl14_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"ctrl14_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"ctrl14_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"ctrl14_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"ctrl14_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"ctrl14_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"ctrl14_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"ctrl14_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"ctrl14_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"ctrl14_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"ctrl14_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"ctrl14_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"ctrl14_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"ctrl14_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"ctrl14_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"ctrl14_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"ctrl14_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"ctrl14_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"ctrl14_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"ctrl14_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"ctrl14_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"ctrl14_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"ctrl14_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"ctrl14_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"ctrl14_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl15_arbiter_ecc_err_reg[] = + { + {"ctrl15_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"ctrl15_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"ctrl15_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"ctrl15_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"ctrl15_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"ctrl15_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"ctrl15_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"ctrl15_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"ctrl15_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"ctrl15_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"ctrl15_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"ctrl15_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"ctrl15_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"ctrl15_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"ctrl15_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"ctrl15_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"ctrl15_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"ctrl15_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"ctrl15_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"ctrl15_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"ctrl15_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"ctrl15_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"ctrl15_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"ctrl15_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"ctrl15_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"ctrl15_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"ctrl15_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"ctrl15_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"ctrl15_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"ctrl15_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"ctrl15_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"ctrl15_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl16_arbiter_ecc_err_reg[] = + { + {"ctrl16_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"ctrl16_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"ctrl16_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"ctrl16_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"ctrl16_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"ctrl16_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"ctrl16_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"ctrl16_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"ctrl16_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"ctrl16_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"ctrl16_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"ctrl16_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"ctrl16_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"ctrl16_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"ctrl16_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"ctrl16_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"ctrl16_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"ctrl16_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"ctrl16_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"ctrl16_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"ctrl16_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"ctrl16_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"ctrl16_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"ctrl16_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"ctrl16_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"ctrl16_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"ctrl16_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"ctrl16_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"ctrl16_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"ctrl16_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"ctrl16_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"ctrl16_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl17_arbiter_ecc_err_reg[] = + { + {"ctrl17_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"ctrl17_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"ctrl17_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"ctrl17_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"ctrl17_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"ctrl17_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"ctrl17_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"ctrl17_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"ctrl17_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"ctrl17_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"ctrl17_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"ctrl17_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"ctrl17_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"ctrl17_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"ctrl17_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"ctrl17_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"ctrl17_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"ctrl17_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"ctrl17_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"ctrl17_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"ctrl17_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"ctrl17_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"ctrl17_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"ctrl17_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"ctrl17_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"ctrl17_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"ctrl17_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"ctrl17_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"ctrl17_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"ctrl17_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"ctrl17_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"ctrl17_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl18_arbiter_ecc_err_reg[] = + { + {"ctrl18_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"ctrl18_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"ctrl18_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"ctrl18_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"ctrl18_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"ctrl18_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"ctrl18_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"ctrl18_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"ctrl18_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"ctrl18_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"ctrl18_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"ctrl18_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"ctrl18_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"ctrl18_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"ctrl18_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"ctrl18_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"ctrl18_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"ctrl18_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"ctrl18_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"ctrl18_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"ctrl18_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"ctrl18_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"ctrl18_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"ctrl18_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"ctrl18_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"ctrl18_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"ctrl18_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"ctrl18_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"ctrl18_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"ctrl18_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"ctrl18_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"ctrl18_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl19_arbiter_ecc_err_reg[] = + { + {"ctrl19_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"ctrl19_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"ctrl19_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"ctrl19_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"ctrl19_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"ctrl19_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"ctrl19_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"ctrl19_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"ctrl19_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"ctrl19_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"ctrl19_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"ctrl19_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"ctrl19_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"ctrl19_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"ctrl19_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"ctrl19_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"ctrl19_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"ctrl19_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"ctrl19_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"ctrl19_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"ctrl19_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"ctrl19_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"ctrl19_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"ctrl19_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"ctrl19_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"ctrl19_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"ctrl19_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"ctrl19_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"ctrl19_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"ctrl19_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"ctrl19_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"ctrl19_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl20_arbiter_ecc_err_reg[] = + { + {"ctrl20_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"ctrl20_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"ctrl20_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"ctrl20_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"ctrl20_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"ctrl20_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"ctrl20_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"ctrl20_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"ctrl20_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"ctrl20_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"ctrl20_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"ctrl20_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"ctrl20_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"ctrl20_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"ctrl20_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"ctrl20_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"ctrl20_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"ctrl20_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"ctrl20_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"ctrl20_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"ctrl20_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"ctrl20_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"ctrl20_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"ctrl20_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"ctrl20_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"ctrl20_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"ctrl20_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"ctrl20_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"ctrl20_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"ctrl20_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"ctrl20_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"ctrl20_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl21_arbiter_ecc_err_reg[] = + { + {"ctrl21_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"ctrl21_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"ctrl21_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"ctrl21_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"ctrl21_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"ctrl21_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"ctrl21_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"ctrl21_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"ctrl21_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"ctrl21_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"ctrl21_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"ctrl21_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"ctrl21_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"ctrl21_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"ctrl21_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"ctrl21_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"ctrl21_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"ctrl21_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"ctrl21_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"ctrl21_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"ctrl21_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"ctrl21_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"ctrl21_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"ctrl21_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"ctrl21_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"ctrl21_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"ctrl21_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"ctrl21_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"ctrl21_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"ctrl21_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"ctrl21_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"ctrl21_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl22_arbiter_ecc_err_reg[] = + { + {"ctrl22_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"ctrl22_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"ctrl22_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"ctrl22_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"ctrl22_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"ctrl22_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"ctrl22_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"ctrl22_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"ctrl22_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"ctrl22_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"ctrl22_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"ctrl22_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"ctrl22_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"ctrl22_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"ctrl22_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"ctrl22_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"ctrl22_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"ctrl22_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"ctrl22_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"ctrl22_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"ctrl22_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"ctrl22_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"ctrl22_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"ctrl22_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"ctrl22_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"ctrl22_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"ctrl22_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"ctrl22_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"ctrl22_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"ctrl22_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"ctrl22_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"ctrl22_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl23_arbiter_ecc_err_reg[] = + { + {"ctrl23_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"ctrl23_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"ctrl23_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"ctrl23_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"ctrl23_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"ctrl23_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"ctrl23_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"ctrl23_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"ctrl23_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"ctrl23_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"ctrl23_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"ctrl23_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"ctrl23_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"ctrl23_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"ctrl23_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"ctrl23_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"ctrl23_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"ctrl23_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"ctrl23_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"ctrl23_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"ctrl23_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"ctrl23_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"ctrl23_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"ctrl23_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"ctrl23_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"ctrl23_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"ctrl23_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"ctrl23_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"ctrl23_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"ctrl23_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"ctrl23_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"ctrl23_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl24_arbiter_ecc_err_reg[] = + { + {"ctrl24_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"ctrl24_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"ctrl24_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"ctrl24_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"ctrl24_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"ctrl24_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"ctrl24_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"ctrl24_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"ctrl24_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"ctrl24_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"ctrl24_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"ctrl24_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"ctrl24_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"ctrl24_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"ctrl24_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"ctrl24_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"ctrl24_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"ctrl24_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"ctrl24_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"ctrl24_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"ctrl24_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"ctrl24_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"ctrl24_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"ctrl24_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"ctrl24_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"ctrl24_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"ctrl24_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"ctrl24_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"ctrl24_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"ctrl24_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"ctrl24_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"ctrl24_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl25_arbiter_ecc_err_reg[] = + { + {"ctrl25_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"ctrl25_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"ctrl25_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"ctrl25_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"ctrl25_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"ctrl25_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"ctrl25_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"ctrl25_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"ctrl25_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"ctrl25_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"ctrl25_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"ctrl25_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"ctrl25_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"ctrl25_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"ctrl25_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"ctrl25_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"ctrl25_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"ctrl25_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"ctrl25_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"ctrl25_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"ctrl25_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"ctrl25_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"ctrl25_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"ctrl25_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"ctrl25_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"ctrl25_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"ctrl25_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"ctrl25_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"ctrl25_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"ctrl25_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"ctrl25_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"ctrl25_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl26_arbiter_ecc_err_reg[] = + { + {"ctrl26_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"ctrl26_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"ctrl26_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"ctrl26_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"ctrl26_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"ctrl26_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"ctrl26_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"ctrl26_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"ctrl26_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"ctrl26_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"ctrl26_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"ctrl26_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"ctrl26_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"ctrl26_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"ctrl26_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"ctrl26_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"ctrl26_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"ctrl26_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"ctrl26_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"ctrl26_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"ctrl26_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"ctrl26_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"ctrl26_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"ctrl26_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"ctrl26_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"ctrl26_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"ctrl26_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"ctrl26_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"ctrl26_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"ctrl26_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"ctrl26_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"ctrl26_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl27_arbiter_ecc_err_reg[] = + { + {"ctrl27_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"ctrl27_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"ctrl27_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"ctrl27_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"ctrl27_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"ctrl27_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"ctrl27_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"ctrl27_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"ctrl27_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"ctrl27_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"ctrl27_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"ctrl27_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"ctrl27_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"ctrl27_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"ctrl27_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"ctrl27_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"ctrl27_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"ctrl27_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"ctrl27_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"ctrl27_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"ctrl27_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"ctrl27_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"ctrl27_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"ctrl27_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"ctrl27_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"ctrl27_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"ctrl27_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"ctrl27_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"ctrl27_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"ctrl27_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"ctrl27_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"ctrl27_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl28_arbiter_ecc_err_reg[] = + { + {"ctrl28_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"ctrl28_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"ctrl28_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"ctrl28_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"ctrl28_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"ctrl28_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"ctrl28_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"ctrl28_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"ctrl28_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"ctrl28_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"ctrl28_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"ctrl28_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"ctrl28_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"ctrl28_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"ctrl28_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"ctrl28_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"ctrl28_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"ctrl28_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"ctrl28_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"ctrl28_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"ctrl28_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"ctrl28_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"ctrl28_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"ctrl28_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"ctrl28_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"ctrl28_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"ctrl28_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"ctrl28_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"ctrl28_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"ctrl28_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"ctrl28_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"ctrl28_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl29_arbiter_ecc_err_reg[] = + { + {"ctrl29_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"ctrl29_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"ctrl29_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"ctrl29_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"ctrl29_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"ctrl29_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"ctrl29_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"ctrl29_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"ctrl29_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"ctrl29_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"ctrl29_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"ctrl29_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"ctrl29_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"ctrl29_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"ctrl29_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"ctrl29_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"ctrl29_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"ctrl29_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"ctrl29_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"ctrl29_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"ctrl29_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"ctrl29_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"ctrl29_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"ctrl29_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"ctrl29_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"ctrl29_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"ctrl29_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"ctrl29_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"ctrl29_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"ctrl29_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"ctrl29_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"ctrl29_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl30_arbiter_ecc_err_reg[] = + { + {"ctrl30_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"ctrl30_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"ctrl30_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"ctrl30_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"ctrl30_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"ctrl30_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"ctrl30_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"ctrl30_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"ctrl30_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"ctrl30_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"ctrl30_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"ctrl30_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"ctrl30_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"ctrl30_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"ctrl30_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"ctrl30_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"ctrl30_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"ctrl30_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"ctrl30_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"ctrl30_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"ctrl30_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"ctrl30_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"ctrl30_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"ctrl30_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"ctrl30_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"ctrl30_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"ctrl30_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"ctrl30_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"ctrl30_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"ctrl30_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"ctrl30_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"ctrl30_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl31_arbiter_ecc_err_reg[] = + { + {"ctrl31_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"ctrl31_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"ctrl31_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"ctrl31_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"ctrl31_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"ctrl31_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"ctrl31_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"ctrl31_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"ctrl31_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"ctrl31_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"ctrl31_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"ctrl31_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"ctrl31_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"ctrl31_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"ctrl31_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"ctrl31_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"ctrl31_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"ctrl31_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"ctrl31_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"ctrl31_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"ctrl31_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"ctrl31_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"ctrl31_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"ctrl31_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"ctrl31_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"ctrl31_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"ctrl31_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"ctrl31_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"ctrl31_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"ctrl31_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"ctrl31_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"ctrl31_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl_req_ecc_single_err_reg[] = + { + {"ctrl_req_ecc_single_err_0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl_req_ecc_double_err_reg[] = + { + {"ctrl_req_ecc_double_err_0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl_info_ecc_single_err_reg[] = + { + {"ctrl_info_ecc_single_err_0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl_info_ecc_double_err_reg[] = + { + {"ctrl_info_ecc_double_err_0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_wr_ecc_err_reg[] = + { + {"smmu0_wr_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"smmu0_wr_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"smmu0_wr_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"smmu0_wr_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_rschd_ecc_single_err_reg[] = + { + {"smmu0_rschd_ecc_single_err_0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_rschd_ecc_double_err_reg[] = + { + {"smmu0_rschd_ecc_double_err_0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ord_fifo_empty_reg[] = + { + {"ord_fifo_empty", DPP_FIELD_FLAG_RO, 4, 5, 0x1f, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_wr_arb_fifo_empty_reg[] = + { + {"wr_arb_fifo_empty", DPP_FIELD_FLAG_RO, 3, 4, 0xf, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl_fifo_empty0_reg[] = + { + {"ctrl_fifo_empty0_5", DPP_FIELD_FLAG_RO, 29, 5, 0x1f, 0x0}, + {"ctrl_fifo_empty0_4", DPP_FIELD_FLAG_RO, 24, 5, 0x1f, 0x0}, + {"ctrl_fifo_empty0_3", DPP_FIELD_FLAG_RO, 19, 5, 0x1f, 0x0}, + {"ctrl_fifo_empty0_2", DPP_FIELD_FLAG_RO, 14, 5, 0x1f, 0x0}, + {"ctrl_fifo_empty0_1", DPP_FIELD_FLAG_RO, 9, 5, 0x1f, 0x0}, + {"ctrl_fifo_empty0_0", DPP_FIELD_FLAG_RO, 4, 5, 0x1f, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl_fifo_empty1_reg[] = + { + {"ctrl_fifo_empty1_5", DPP_FIELD_FLAG_RO, 29, 5, 0x1f, 0x0}, + {"ctrl_fifo_empty1_4", DPP_FIELD_FLAG_RO, 24, 5, 0x1f, 0x0}, + {"ctrl_fifo_empty1_3", DPP_FIELD_FLAG_RO, 19, 5, 0x1f, 0x0}, + {"ctrl_fifo_empty1_2", DPP_FIELD_FLAG_RO, 14, 5, 0x1f, 0x0}, + {"ctrl_fifo_empty1_1", DPP_FIELD_FLAG_RO, 9, 5, 0x1f, 0x0}, + {"ctrl_fifo_empty1_0", DPP_FIELD_FLAG_RO, 4, 5, 0x1f, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl_fifo_empty2_reg[] = + { + {"ctrl_fifo_empty2_5", DPP_FIELD_FLAG_RO, 29, 5, 0x1f, 0x0}, + {"ctrl_fifo_empty2_4", DPP_FIELD_FLAG_RO, 24, 5, 0x1f, 0x0}, + {"ctrl_fifo_empty2_3", DPP_FIELD_FLAG_RO, 19, 5, 0x1f, 0x0}, + {"ctrl_fifo_empty2_2", DPP_FIELD_FLAG_RO, 14, 5, 0x1f, 0x0}, + {"ctrl_fifo_empty2_1", DPP_FIELD_FLAG_RO, 9, 5, 0x1f, 0x0}, + {"ctrl_fifo_empty2_0", DPP_FIELD_FLAG_RO, 4, 5, 0x1f, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl_fifo_empty3_reg[] = + { + {"ctrl_fifo_empty3_5", DPP_FIELD_FLAG_RO, 29, 5, 0x1f, 0x0}, + {"ctrl_fifo_empty3_4", DPP_FIELD_FLAG_RO, 24, 5, 0x1f, 0x0}, + {"ctrl_fifo_empty3_3", DPP_FIELD_FLAG_RO, 19, 5, 0x1f, 0x0}, + {"ctrl_fifo_empty3_2", DPP_FIELD_FLAG_RO, 14, 5, 0x1f, 0x0}, + {"ctrl_fifo_empty3_1", DPP_FIELD_FLAG_RO, 9, 5, 0x1f, 0x0}, + {"ctrl_fifo_empty3_0", DPP_FIELD_FLAG_RO, 4, 5, 0x1f, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl_fifo_empty4_reg[] = + { + {"ctrl_fifo_empty4_5", DPP_FIELD_FLAG_RO, 29, 5, 0x1f, 0x0}, + {"ctrl_fifo_empty4_4", DPP_FIELD_FLAG_RO, 24, 5, 0x1f, 0x0}, + {"ctrl_fifo_empty4_3", DPP_FIELD_FLAG_RO, 19, 5, 0x1f, 0x0}, + {"ctrl_fifo_empty4_2", DPP_FIELD_FLAG_RO, 14, 5, 0x1f, 0x0}, + {"ctrl_fifo_empty4_1", DPP_FIELD_FLAG_RO, 9, 5, 0x1f, 0x0}, + {"ctrl_fifo_empty4_0", DPP_FIELD_FLAG_RO, 4, 5, 0x1f, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ctrl_fifo_empty5_reg[] = + { + {"ctrl_fifo_empty5_1", DPP_FIELD_FLAG_RO, 9, 5, 0x1f, 0x0}, + {"ctrl_fifo_empty5_0", DPP_FIELD_FLAG_RO, 4, 5, 0x1f, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty0_reg[] = + { + {"kschd_fifo_empty0", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty1_reg[] = + { + {"kschd_fifo_empty1", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty2_reg[] = + { + {"kschd_fifo_empty2", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty3_reg[] = + { + {"kschd_fifo_empty3", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty4_reg[] = + { + {"kschd_fifo_empty4", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty5_reg[] = + { + {"kschd_fifo_empty5", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty6_reg[] = + { + {"kschd_fifo_empty6", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty7_reg[] = + { + {"kschd_fifo_empty7", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty8_reg[] = + { + {"kschd_fifo_empty8", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty9_reg[] = + { + {"kschd_fifo_empty9", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty10_reg[] = + { + {"kschd_fifo_empty10", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty11_reg[] = + { + {"kschd_fifo_empty11", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty12_reg[] = + { + {"kschd_fifo_empty12", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty13_reg[] = + { + {"kschd_fifo_empty13", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty14_reg[] = + { + {"kschd_fifo_empty14", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty15_reg[] = + { + {"kschd_fifo_empty15", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty16_reg[] = + { + {"kschd_fifo_empty16", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty17_reg[] = + { + {"kschd_fifo_empty17", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty18_reg[] = + { + {"kschd_fifo_empty18", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty19_reg[] = + { + {"kschd_fifo_empty19", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty20_reg[] = + { + {"kschd_fifo_empty20", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty21_reg[] = + { + {"kschd_fifo_empty21", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty22_reg[] = + { + {"kschd_fifo_empty22", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty23_reg[] = + { + {"kschd_fifo_empty23", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty24_reg[] = + { + {"kschd_fifo_empty24", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty25_reg[] = + { + {"kschd_fifo_empty25", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty26_reg[] = + { + {"kschd_fifo_empty26", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty27_reg[] = + { + {"kschd_fifo_empty27", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty28_reg[] = + { + {"kschd_fifo_empty28", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty29_reg[] = + { + {"kschd_fifo_empty29", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty30_reg[] = + { + {"kschd_fifo_empty30", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty31_reg[] = + { + {"kschd_fifo_empty31", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty0_reg[] = + { + {"rschd_fifo_empty0", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty1_reg[] = + { + {"rschd_fifo_empty1", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty2_reg[] = + { + {"rschd_fifo_empty2", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty3_reg[] = + { + {"rschd_fifo_empty3", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty4_reg[] = + { + {"rschd_fifo_empty4", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty5_reg[] = + { + {"rschd_fifo_empty5", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty6_reg[] = + { + {"rschd_fifo_empty6", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty7_reg[] = + { + {"rschd_fifo_empty7", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty8_reg[] = + { + {"rschd_fifo_empty8", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty9_reg[] = + { + {"rschd_fifo_empty9", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty10_reg[] = + { + {"rschd_fifo_empty10", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty11_reg[] = + { + {"rschd_fifo_empty11", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty12_reg[] = + { + {"rschd_fifo_empty12", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty13_reg[] = + { + {"rschd_fifo_empty13", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty14_reg[] = + { + {"rschd_fifo_empty14", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty15_reg[] = + { + {"rschd_fifo_empty15", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty16_reg[] = + { + {"rschd_fifo_empty16", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty17_reg[] = + { + {"rschd_fifo_empty17", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty18_reg[] = + { + {"rschd_fifo_empty18", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty19_reg[] = + { + {"rschd_fifo_empty19", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty20_reg[] = + { + {"rschd_fifo_empty20", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty21_reg[] = + { + {"rschd_fifo_empty21", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty22_reg[] = + { + {"rschd_fifo_empty22", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty23_reg[] = + { + {"rschd_fifo_empty23", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty24_reg[] = + { + {"rschd_fifo_empty24", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty25_reg[] = + { + {"rschd_fifo_empty25", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty26_reg[] = + { + {"rschd_fifo_empty26", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty27_reg[] = + { + {"rschd_fifo_empty27", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty28_reg[] = + { + {"rschd_fifo_empty28", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty29_reg[] = + { + {"rschd_fifo_empty29", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty30_reg[] = + { + {"rschd_fifo_empty30", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty31_reg[] = + { + {"rschd_fifo_empty31", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ept_flag_reg[] = + { + {"ept_flag8", DPP_FIELD_FLAG_RO, 8, 1, 0x1, 0x0}, + {"ept_flag7", DPP_FIELD_FLAG_RO, 7, 1, 0x1, 0x0}, + {"ept_flag6", DPP_FIELD_FLAG_RO, 6, 1, 0x1, 0x0}, + {"ept_flag5", DPP_FIELD_FLAG_RO, 5, 1, 0x1, 0x0}, + {"ept_flag4", DPP_FIELD_FLAG_RO, 4, 1, 0x1, 0x0}, + {"ept_flag3", DPP_FIELD_FLAG_RO, 3, 1, 0x1, 0x0}, + {"ept_flag2", DPP_FIELD_FLAG_RO, 2, 1, 0x1, 0x0}, + {"ept_flag1", DPP_FIELD_FLAG_RO, 1, 1, 0x1, 0x0}, + {"ept_flag0", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ppu_soft_rst_reg[] = + { + {"ppu_soft_rst", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_as_mac_age_fc_cnt_reg[] = + { + {"smmu0_as_mac_age_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_marc_se_parser_fc_cnt_reg[] = + { + {"smmu0_marc_se_parser_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_wr_arb_cpu_fc_cnt_reg[] = + { + {"wr_arb_cpu_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_lpm_as_fc_cnt_reg[] = + { + {"smmu0_lpm_as_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_lpm_as_smmu0_fc_cnt_reg[] = + { + {"lpm_as_smmu0_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_etcam1_0_as_fc_cnt_reg[] = + { + {"smmu0_etcam1_0_as_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_as_etcam1_0_smmu0_fc_cnt_reg[] = + { + {"as_etcam1_0_smmu0_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_ppu_mcast_fc_cnt_reg[] = + { + {"smmu0_ppu_mcast_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ppu_smmu0_mcast_fc_cnt_reg[] = + { + {"ppu_smmu0_mcast_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_odma_smmu0_tdm_fc_rsp_fc_cnt_reg[] = + { + {"odma_smmu0_tdm_fc_rsp_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_odma_tdm_fc_key_fc_cnt_reg[] = + { + {"smmu0_odma_tdm_fc_key_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_odma_fc_cnt_reg[] = + { + {"smmu0_odma_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_cfg_tab_rd_fc_cnt_reg[] = + { + {"smmu0_cfg_tab_rd_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_stat_fc15_0_cnt_reg[] = + { + {"smmu0_stat_fc15_0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_stat_smmu0_fc15_0_cnt_reg[] = + { + {"stat_smmu0_fc15_0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_ppu_mex5_0_fc_cnt_reg[] = + { + {"smmu0_ppu_mex5_0_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ppu_smmu0_mex5_0_fc_cnt_reg[] = + { + {"ppu_smmu0_mex5_0_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_as_smmu0_mac_age_req_cnt_reg[] = + { + {"as_smmu0_mac_age_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_se_parser_smmu0_marc_key_cnt_reg[] = + { + {"se_parser_smmu0_marc_key_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_cpu_ind_rdat_cnt_reg[] = + { + {"cpu_ind_rdat_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_cpu_ind_rd_req_cnt_reg[] = + { + {"cpu_ind_rd_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_cpu_ind_wr_req_cnt_reg[] = + { + {"cpu_ind_wr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_plcr_rsp0_cnt_reg[] = + { + {"smmu0_plcr_rsp0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_plcr_smmu0_req0_cnt_reg[] = + { + {"plcr_smmu0_req0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_lpm_as_rsp_cnt_reg[] = + { + {"smmu0_lpm_as_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_lpm_as_smmu0_req_cnt_reg[] = + { + {"lpm_as_smmu0_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_etcam1_0_as_rsp_cnt_reg[] = + { + {"smmu0_etcam1_0_as_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_etcam1_0_as_smmu0_req_cnt_reg[] = + { + {"etcam1_0_as_smmu0_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_ppu_mcast_rsp_cnt_reg[] = + { + {"smmu0_ppu_mcast_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ppu_smmu0_mcast_key_cnt_reg[] = + { + {"ppu_smmu0_mcast_key_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_odma_tdm_mc_rsp_cnt_reg[] = + { + {"smmu0_odma_tdm_mc_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_odma_smmu0_tdm_mc_key_cnt_reg[] = + { + {"odma_smmu0_tdm_mc_key_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_odma_rsp_cnt_reg[] = + { + {"smmu0_odma_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_odma_smmu0_cmd_cnt_reg[] = + { + {"odma_smmu0_cmd_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_cfg_tab_rdat_cnt_reg[] = + { + {"smmu0_cfg_tab_rdat_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_cfg_smmu0_tab_rd_cnt_reg[] = + { + {"cfg_smmu0_tab_rd_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_stat_rsp15_0_cnt_reg[] = + { + {"smmu0_stat_rsp15_0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_stat_smmu0_req15_0_cnt_reg[] = + { + {"stat_smmu0_req15_0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_smmu0_ppu_mex5_0_rsp_cnt_reg[] = + { + {"smmu0_ppu_mex5_0_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ppu_smmu0_mex5_0_key_cnt_reg[] = + { + {"ppu_smmu0_mex5_0_key_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ftm_stat_smmu0_req0_cnt_reg[] = + { + {"ftm_stat_smmu0_req0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_ftm_stat_smmu0_req1_cnt_reg[] = + { + {"ftm_stat_smmu0_req1_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_etm_stat_smmu0_req0_cnt_reg[] = + { + {"etm_stat_smmu0_req0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_etm_stat_smmu0_req1_cnt_reg[] = + { + {"etm_stat_smmu0_req1_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_req_eram0_31_rd_cnt_reg[] = + { + {"req_eram0_31_rd_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu0_smmu0_req_eram0_31_wr_cnt_reg[] = + { + {"req_eram0_31_wr_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_ddr_wdat1_reg[] = + { + {"ddr_wdat1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_ddr_wdat2_reg[] = + { + {"ddr_wdat2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_ddr_wdat3_reg[] = + { + {"ddr_wdat3", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_ddr_wdat4_reg[] = + { + {"ddr_wdat4", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_ddr_wdat5_reg[] = + { + {"ddr_wdat5", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_ddr_wdat6_reg[] = + { + {"ddr_wdat6", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_ddr_wdat7_reg[] = + { + {"ddr_wdat7", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_ddr_wdat8_reg[] = + { + {"ddr_wdat8", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_ddr_wdat9_reg[] = + { + {"ddr_wdat9", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_ddr_wdat10_reg[] = + { + {"ddr_wdat10", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_ddr_wdat11_reg[] = + { + {"ddr_wdat11", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_ddr_wdat12_reg[] = + { + {"ddr_wdat12", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_ddr_wdat13_reg[] = + { + {"ddr_wdat13", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_ddr_wdat14_reg[] = + { + {"ddr_wdat14", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_ddr_wdat15_reg[] = + { + {"ddr_wdat15", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_cnt_stat_cache_en_reg[] = + { + {"cnt_stat_cache_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_cnt_stat_cache_clr_reg[] = + { + {"cnt_stat_cache_clr", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_cnt_stat_cache_req_63_32_reg[] = + { + {"cnt_stat_cache_req_63_32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_cnt_stat_cache_req_31_0_reg[] = + { + {"cnt_stat_cache_req_31_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_cnt_stat_cache_hit_63_32_reg[] = + { + {"cnt_stat_cache_hit_63_32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_cnt_stat_cache_hit_31_0_reg[] = + { + {"cnt_stat_cache_hit_31_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_ddr_cmd0_reg[] = + { + {"ecc_en", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0}, + {"rw_len", DPP_FIELD_FLAG_RW, 21, 2, 0x0, 0x0}, + {"baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_info_addr_reg[] = + { + {"info_addr", DPP_FIELD_FLAG_RW, 5, 6, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_ddr_cmd1_reg[] = + { + {"rw_flag", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, + {"rw_addr", DPP_FIELD_FLAG_RW, 29, 30, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_clr_start_addr_reg[] = + { + {"clr_start_addr", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_clr_end_addr_reg[] = + { + {"clr_end_addr", DPP_FIELD_FLAG_RW, 31, 32, 0xffffff, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_clr_tbl_en_reg[] = + { + {"cfg_init_en", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0}, + {"clr_tbl_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_debug_cnt_mode_reg[] = + { + {"cnt_rd_mode", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0}, + {"cnt_overflow_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_init_done_reg[] = + { + {"cache_init_done", DPP_FIELD_FLAG_RO, 7, 1, 0x0, 0x0}, + {"clr_done", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0}, + {"init_ok", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_cpu_rsp_rd_done_reg[] = + { + {"cpu_rsp_rd_done", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_ksch_oam_sp_en_reg[] = + { + {"ksch_oam_sp_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_cfg_cache_en_reg[] = + { + {"cfg_cache_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_cache_age_en_reg[] = + { + {"cache_age_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_cpu_rdat0_reg[] = + { + {"cpu_rdat0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_cpu_rdat1_reg[] = + { + {"cpu_rdat1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_cpu_rdat2_reg[] = + { + {"cpu_rdat2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_cpu_rdat3_reg[] = + { + {"cpu_rdat3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_cpu_rdat4_reg[] = + { + {"cpu_rdat4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_cpu_rdat5_reg[] = + { + {"cpu_rdat5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_cpu_rdat6_reg[] = + { + {"cpu_rdat6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_cpu_rdat7_reg[] = + { + {"cpu_rdat7", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_cpu_rdat8_reg[] = + { + {"cpu_rdat8", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_cpu_rdat9_reg[] = + { + {"cpu_rdat9", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_cpu_rdat10_reg[] = + { + {"cpu_rdat10", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_cpu_rdat11_reg[] = + { + {"cpu_rdat11", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_cpu_rdat12_reg[] = + { + {"cpu_rdat12", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_cpu_rdat13_reg[] = + { + {"cpu_rdat13", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_cpu_rdat14_reg[] = + { + {"cpu_rdat14", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_cpu_rdat15_reg[] = + { + {"cpu_rdat15", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_ctrl_cpu_rd_rdy_reg[] = + { + {"ctrl_cpu_rd_rdy", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_cpu_warbi_rdy_cfg_reg[] = + { + {"cpu_warbi_rdy_cfg", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_dir_arbi_cpu_rpful_reg[] = + { + {"smmu1_cfg_rpful", DPP_FIELD_FLAG_RW, 15, 8, 0x44, 0x0}, + {"smmu1_cfg_wpful", DPP_FIELD_FLAG_RW, 7, 8, 0x44, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_dir_arbi_wpful_reg[] = + { + {"smmu1_ser_wdir_pful", DPP_FIELD_FLAG_RW, 17, 10, 0x14a, 0x0}, + {"smmu1_cfg_wdir_pful", DPP_FIELD_FLAG_RW, 7, 8, 0x22, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_cfg_wr_arbi_pful0_reg[] = + { + {"arbi_out_pful", DPP_FIELD_FLAG_RW, 17, 12, 0x71c, 0x0}, + {"cpu_wr_pful", DPP_FIELD_FLAG_RW, 5, 6, 0x22, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_cfg_wr_arbi_pful1_reg[] = + { + {"tm_wr_pful", DPP_FIELD_FLAG_RW, 23, 12, 0x4d3, 0x0}, + {"stat_wr_pful", DPP_FIELD_FLAG_RW, 11, 12, 0x555, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_smmu1_wdone_pful_cfg_reg[] = + { + {"smmu1_wdone_pful_cfg", DPP_FIELD_FLAG_RW, 19, 20, 0x7e1f8, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_stat_rate_cfg_cnt_reg[] = + { + {"stat_rate_cfg_cnt", DPP_FIELD_FLAG_RW, 9, 10, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_ftm_rate_cfg_cnt_reg[] = + { + {"ftm_rate_cfg_cnt", DPP_FIELD_FLAG_RW, 9, 10, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_etm_rate_cfg_cnt_reg[] = + { + {"etm_rate_cfg_cnt", DPP_FIELD_FLAG_RW, 9, 10, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_dir_rate_cfg_cnt_reg[] = + { + {"dir_rate_cfg_cnt", DPP_FIELD_FLAG_RW, 9, 10, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_hash_rate_cfg_cnt_reg[] = + { + {"hash_rate_cfg_cnt", DPP_FIELD_FLAG_RW, 9, 10, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_ftm_tbl_cfg_reg[] = + { + {"ftm_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_lpm_v4_as_tbl_cfg_reg[] = + { + {"lpm_v4_as_rsp_len", DPP_FIELD_FLAG_RW, 22, 2, 0x0, 0x0}, + {"lpm_v4_as_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"lpm_v4_as_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_lpm_v4_tbl_cfg_reg[] = + { + {"lpm_v4_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0}, + {"lpm_v4_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"lpm_v4_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_lpm_v6_tbl_cfg_reg[] = + { + {"lpm_v6_len", DPP_FIELD_FLAG_RO, 22, 2, 0x2, 0x0}, + {"lpm_v6_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"lpm_v6_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_lpm_v6_as_tbl_cfg_reg[] = + { + {"lpm_v6_as_rsp_len", DPP_FIELD_FLAG_RW, 22, 2, 0x0, 0x0}, + {"lpm_v6_as_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"lpm_v6_as_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_dma_tbl_cfg_reg[] = + { + {"dma_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_oam_tbl_cfg_reg[] = + { + {"oam_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_ctrl_rpar_cpu_pful_reg[] = + { + {"ctrl_rpar_cpu_pful", DPP_FIELD_FLAG_RW, 7, 8, 0x44, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_cfg_ksch_dir_pful_reg[] = + { + {"cfg_ksch_dir_pful", DPP_FIELD_FLAG_RW, 15, 16, 0x3434, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_cfg_ksch_hash_pful_reg[] = + { + {"cfg_ksch_hash_pful", DPP_FIELD_FLAG_RW, 15, 16, 0x3030, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_cfg_ksch_lpm_pful_reg[] = + { + {"cfg_ksch_lpm_pful", DPP_FIELD_FLAG_RW, 15, 16, 0x3030, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_cfg_ksch_lpm_as_pful_reg[] = + { + {"cfg_ksch_lpm_as_pful", DPP_FIELD_FLAG_RW, 15, 16, 0x3030, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_cfg_ksch_stat_pful_reg[] = + { + {"cfg_ksch_stat_pful", DPP_FIELD_FLAG_RW, 15, 16, 0x3434, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_cfg_ksch_tm_pful_reg[] = + { + {"cfg_ksch_tm_pful", DPP_FIELD_FLAG_RW, 15, 16, 0x3232, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_cfg_ksch_oam_pful_reg[] = + { + {"cfg_ksch_oam_pful", DPP_FIELD_FLAG_RW, 15, 16, 0x2a2a, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_cfg_ksch_dma_pful_reg[] = + { + {"cfg_ksch_dma_pful", DPP_FIELD_FLAG_RW, 15, 16, 0x2727, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_ctrl_wfifo_cfg_reg[] = + { + {"ctrl_wfifo_cfg", DPP_FIELD_FLAG_RW, 9, 10, 0x18c, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_rsch_hash_ptr_cfg_reg[] = + { + {"rsch_hash_ptr_cfg", DPP_FIELD_FLAG_RW, 8, 9, 0xe, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_rsch_lpm_ptr_cfg_reg[] = + { + {"rsch_lpm_ptr_cfg", DPP_FIELD_FLAG_RW, 8, 9, 0xe, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_rsch_lpm_as_ptr_cfg_reg[] = + { + {"rsch_lpm_as_ptr_cfg", DPP_FIELD_FLAG_RW, 8, 9, 0xe, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_rsch_stat_ptr_cfg_reg[] = + { + {"rsch_stat_ptr_cfg", DPP_FIELD_FLAG_RW, 8, 9, 0xe, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_rsch_oam_ptr_cfg_reg[] = + { + {"rsch_oam_ptr_cfg", DPP_FIELD_FLAG_RW, 8, 9, 0x12, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_rschd_fifo_pept_cfg_reg[] = + { + {"rschd_fifo_pept_cfg", DPP_FIELD_FLAG_RW, 13, 14, 0x204, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_dir_fifo_pful_cfg_reg[] = + { + {"dir_fifo_pful_cfg", DPP_FIELD_FLAG_RW, 13, 14, 0x1e3c, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_hash_fifo_pful_cfg_reg[] = + { + {"hash_fifo_pful_cfg", DPP_FIELD_FLAG_RW, 13, 14, 0x1e3c, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_lpm_fifo_pful_cfg_reg[] = + { + {"lpm_fifo_pful_cfg", DPP_FIELD_FLAG_RW, 13, 14, 0x1e3c, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_lpm_as_fifo_pful_cfg_reg[] = + { + {"lpm_as_fifo_pful_cfg", DPP_FIELD_FLAG_RW, 13, 14, 0x1e3c, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_stat_fifo_pful_cfg_reg[] = + { + {"stat_fifo_pful_cfg", DPP_FIELD_FLAG_RW, 13, 14, 0x1e3c, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_ftm_fifo_pful_cfg_reg[] = + { + {"ftm_fifo_pful_cfg", DPP_FIELD_FLAG_RW, 13, 14, 0x1e3c, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_etm_fifo_pful_cfg_reg[] = + { + {"etm_fifo_pful_cfg", DPP_FIELD_FLAG_RW, 13, 14, 0x1e3c, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_oam_fifo_pful_cfg_reg[] = + { + {"oam_fifo_pful_cfg", DPP_FIELD_FLAG_RW, 13, 14, 0x1e3c, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_dma_fifo_pful_cfg_reg[] = + { + {"dma_fifo_pful_cfg", DPP_FIELD_FLAG_RW, 13, 14, 0x1e3c, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_cache_rsp_rr_fifo_cfg_reg[] = + { + {"rr_pfull_assert0", DPP_FIELD_FLAG_RW, 11, 6, 0x14, 0x0}, + {"rr_pfull_negate0", DPP_FIELD_FLAG_RW, 5, 6, 0x14, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_ddr_rsp_rr_fifo_cfg_reg[] = + { + {"rr_pfull_assert1", DPP_FIELD_FLAG_RW, 13, 7, 0x20, 0x0}, + {"rr_pfull_negate1", DPP_FIELD_FLAG_RW, 6, 7, 0x20, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_cpu_cahce_fifo_cfg_reg[] = + { + {"smmu1_cahce_fwft_fifo_pfull_assert", DPP_FIELD_FLAG_RW, 7, 4, 0x6, 0x0}, + {"smmu1_cahce_fwft_fifo_pfull_negate", DPP_FIELD_FLAG_RW, 3, 4, 0x6, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_cache_rsp_fifo_cfg_reg[] = + { + {"rschd_fifo_pfull_assert", DPP_FIELD_FLAG_RW, 11, 6, 0x10, 0x0}, + {"rschd_fifo_pfull_negate", DPP_FIELD_FLAG_RW, 5, 6, 0x10, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_test_state_reg[] = + { + {"test_state", DPP_FIELD_FLAG_RW, 31, 32, 0x11111111, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_cache_fifo_ept_reg[] = + { + {"cache_fifo_ept", DPP_FIELD_FLAG_RO, 1, 2, 0x3, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_rr_fifo_ept_reg[] = + { + {"rr_fifo_ept", DPP_FIELD_FLAG_RO, 1, 2, 0x3, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_wr_fifo_ept_reg[] = + { + {"dir_arbi_ept", DPP_FIELD_FLAG_RO, 6, 7, 0x7f, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_wdone_fifo_ept_reg[] = + { + {"wdone_fifo_ept", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_kschd_fifo_ept0_reg[] = + { + {"kschd_fifo_ept0", DPP_FIELD_FLAG_RO, 14, 15, 0x7fff, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_cash_fifo_ept_reg[] = + { + {"cash_fifo_ept", DPP_FIELD_FLAG_RO, 1, 2, 0x3, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_ctrl_fifo_ept_reg[] = + { + {"ctrl_fifo_ept", DPP_FIELD_FLAG_RO, 2, 3, 0x7, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_smmu1_rschd_ept3_reg[] = + { + {"rschd_fifo_ept3", DPP_FIELD_FLAG_RO, 31, 32, 0xffffff, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_smmu1_rschd_ept2_reg[] = + { + {"rschd_fifo_ept2", DPP_FIELD_FLAG_RO, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_smmu1_rschd_ept1_reg[] = + { + {"rschd_fifo_ept1", DPP_FIELD_FLAG_RO, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_smmu1_rschd_ept0_reg[] = + { + {"rschd_fifo_ept0", DPP_FIELD_FLAG_RO, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_cash0_ecc_err_addr_reg[] = + { + {"cash0_ecc_err_addr", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_arbi_cpu_wr_rdy_reg[] = + { + {"arbi_cpu_wr_rdy", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_smmu1_int_0_en_reg[] = + { + {"smmu1_int_0_en", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_smmu1_int_0_mask_reg[] = + { + {"smmu1_int_0_mask", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_smmu1_int_1_en_reg[] = + { + {"smmu1_int_1_en", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_smmu1_int_1_mask_reg[] = + { + {"smmu1_int_1_mask", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_smmu1_int_2_en_reg[] = + { + {"smmu1_int_2_en", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_smmu1_int_2_mask_reg[] = + { + {"smmu1_int_2_mask", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_smmu1_int_3_en_reg[] = + { + {"smmu1_int_3_en", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_smmu1_int_3_mask_reg[] = + { + {"smmu1_int_3_mask", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_smmu1_int_0_status_reg[] = + { + {"smmu1_int_0_status", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_smmu1_int_1_status_reg[] = + { + {"smmu1_int_1_status", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_smmu1_int_2_status_reg[] = + { + {"smmu1_int_2_status", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_smmu1_int_3_status_reg[] = + { + {"smmu1_int_3_status", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_smmu1_int_status_reg[] = + { + {"smmu1_int_status", DPP_FIELD_FLAG_RO, 3, 4, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_ctrl_to_cash7_0_fc_cnt_reg[] = + { + {"ctrl_to_cash7_0_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_cash7_0_to_ctrl_req_cnt_reg[] = + { + {"cash7_0_to_ctrl_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_rschd_to_cache7_fc_cnt_reg[] = + { + {"rschd_to_cache7_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_cash7_to_cache_rsp_cnt_reg[] = + { + {"cash7_to_cache_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_cash7_to_ctrl_fc_cnt_reg[] = + { + {"cash7_to_ctrl_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_ctrl_to_cash7_0_rsp_cnt_reg[] = + { + {"ctrl_to_cash7_0_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_kschd_to_cache7_0_req_cnt_reg[] = + { + {"kschd_to_cache7_0_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_cache7_0_to_kschd_fc_cnt_reg[] = + { + {"cache7_0_to_kschd_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_dma_to_smmu1_rd_req_cnt_reg[] = + { + {"dma_to_smmu1_rd_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_oam_to_kschd_req_cnt_reg[] = + { + {"oam_to_kschd_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_oam_rr_state_rsp_cnt_reg[] = + { + {"oam_rr_state_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_oam_clash_info_cnt_reg[] = + { + {"oam_clash_info_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_oam_to_rr_req_cnt_reg[] = + { + {"oam_to_rr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_lpm_as_to_kschd_req_cnt_reg[] = + { + {"lpm_as_to_kschd_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_lpm_as_rr_state_rsp_cnt_reg[] = + { + {"lpm_as_rr_state_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_lpm_as_clash_info_cnt_reg[] = + { + {"lpm_as_clash_info_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_lpm_as_to_rr_req_cnt_reg[] = + { + {"lpm_as_to_rr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_lpm_to_kschd_req_cnt_reg[] = + { + {"lpm_to_kschd_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_lpm_rr_state_rsp_cnt_reg[] = + { + {"lpm_rr_state_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_lpm_clash_info_cnt_reg[] = + { + {"lpm_clash_info_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_lpm_to_rr_req_cnt_reg[] = + { + {"lpm_to_rr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_hash3_0_to_kschd_req_cnt_reg[] = + { + {"hash3_0_to_kschd_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_hash3_0_rr_state_rsp_cnt_reg[] = + { + {"hash3_0_rr_state_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_hash3_0_clash_info_cnt_reg[] = + { + {"hash3_0_clash_info_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_hash3_0_to_rr_req_cnt_reg[] = + { + {"hash3_0_to_rr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_dir3_0_to_kschd_req_cnt_reg[] = + { + {"dir3_0_to_kschd_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_dir3_0_clash_info_cnt_reg[] = + { + {"dir3_0_clash_info_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_dir_tbl_wr_req_cnt_reg[] = + { + {"dir_tbl_wr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_warbi_to_dir_tbl_warbi_fc_cnt_reg[] = + { + {"warbi_to_dir_tbl_warbi_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_dir3_0_to_bank_rr_req_cnt_reg[] = + { + {"dir3_0_to_bank_rr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_kschd_to_dir3_0_fc_cnt_reg[] = + { + {"kschd_to_dir3_0_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_dir3_0_rr_state_rsp_cnt_reg[] = + { + {"dir3_0_rr_state_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_wr_done_to_warbi_fc_cnt_reg[] = + { + {"wr_done_to_warbi_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_wr_done_ptr_req_cnt_reg[] = + { + {"wr_done_ptr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_ctrl7_0_to_warbi_fc_cnt_reg[] = + { + {"ctrl7_0_to_warbi_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_warbi_to_ctrl7_0_wr_req_cnt_reg[] = + { + {"warbi_to_ctrl7_0_wr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_warbi_to_cash7_0_wr_req_cnt_reg[] = + { + {"warbi_to_cash7_0_wr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_warbi_to_cpu_wr_fc_cnt_reg[] = + { + {"warbi_to_cpu_wr_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_cpu_wr_req_cnt_reg[] = + { + {"cpu_wr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_ctrl7_0_to_cpu_rd_rsp_cnt_reg[] = + { + {"ctrl7_0_to_cpu_rd_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_cpu_to_ctrl7_0_rd_req_cnt_reg[] = + { + {"cpu_to_ctrl7_0_rd_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_cpu_rd_dir_tbl_rsp_cnt_reg[] = + { + {"cpu_rd_dir_tbl_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_cpu_to_dir_tbl_rd_wr_req_cnt_reg[] = + { + {"cpu_to_dir_tbl_rd_wr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_smmu1_to_mmu_7_0_rsp_fc_cnt_reg[] = + { + {"smmu1_to_mmu_7_0_rsp_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_mmu_7_0_to_smmu1_rd_rsp_cnt_reg[] = + { + {"mmu_7_0_to_smmu1_rd_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_mmu_7_0_to_smmu1_rd_fc_cnt_reg[] = + { + {"mmu_7_0_to_smmu1_rd_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_smmu1_to_mmu_7_rd_req_cnt_reg[] = + { + {"smmu1_to_mmu_7_rd_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_mmu_7_to_smmu1_wr_fc_cnt_reg[] = + { + {"mmu_7_to_smmu1_wr_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_smmu1_to_mmu_7_0_wr_req_cnt_reg[] = + { + {"smmu1_to_mmu_7_0_wr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_se_to_smmu1_wr_rsp_fc_cnt_reg[] = + { + {"se_to_smmu1_wr_rsp_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_smmu1_to_se_wr_rsp_cnt_reg[] = + { + {"smmu1_to_se_wr_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_ddr7_0_wr_rsp_cnt_reg[] = + { + {"ddr7_0_wr_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_smmu1_to_as_fc_cnt_reg[] = + { + {"smmu1_to_as_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_as_to_smmu1_wr_req_cnt_reg[] = + { + {"as_to_smmu1_wr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_smmu1_to_se_parser_fc_cnt_reg[] = + { + {"smmu1_to_se_parser_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_se_parser_to_smmu1_req_cnt_reg[] = + { + {"se_parser_to_smmu1_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_smmu1_to_etm_wr_fc_cnt_reg[] = + { + {"smmu1_to_etm_wr_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_etm_wr_req_cnt_reg[] = + { + {"etm_wr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_smmu1_to_ftm_wr_fc_cnt_reg[] = + { + {"smmu1_to_ftm_wr_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_ftm_wr_req_cnt_reg[] = + { + {"ftm_wr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_smmu1_to_state_wr_fc_cnt_reg[] = + { + {"smmu1_to_state_wr_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_state_wr_req_cnt_reg[] = + { + {"state_wr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_se_to_dma_rsp_cnt_reg[] = + { + {"se_to_dma_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_se_to_dma_fc_cnt_reg[] = + { + {"se_to_dma_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_oam_to_smmu1_fc_cnt_reg[] = + { + {"oam_to_smmu1_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_smmu1_to_oam_rsp_cnt_reg[] = + { + {"smmu1_to_oam_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_smmu1_to_oam_fc_cnt_reg[] = + { + {"smmu1_to_oam_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_oam_to_smmu1_req_cnt_reg[] = + { + {"oam_to_smmu1_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_smmu1_to_etm_rsp_cnt_reg[] = + { + {"smmu1_to_etm_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_smmu1_to_ftm_rsp_cnt_reg[] = + { + {"smmu1_to_ftm_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_smmu1_to_etm_fc_cnt_reg[] = + { + {"smmu1_to_etm_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_etm_to_smmu1_req_cnt_reg[] = + { + {"etm_to_smmu1_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_smmu1_to_ftm_fc_cnt_reg[] = + { + {"smmu1_to_ftm_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_ftm_to_smmu1_req_cnt_reg[] = + { + {"ftm_to_smmu1_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_smmu1_to_stat_rsp_cnt_reg[] = + { + {"smmu1_to_stat_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_smmu1_to_stat_fc_cnt_reg[] = + { + {"smmu1_to_stat_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_stat_to_smmu1_req_cnt_reg[] = + { + {"stat_to_smmu1_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_lpm_as_to_smmu1_fc_cnt_reg[] = + { + {"lpm_as_to_smmu1_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_lpm_to_smmu1_fc_cnt_reg[] = + { + {"lpm_to_smmu1_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_smmu1_to_lpm_as_rsp_cnt_reg[] = + { + {"smmu1_to_lpm_as_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_smmu1_to_lpm_rsp_cnt_reg[] = + { + {"smmu1_to_lpm_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_smmu1_to_lpm_as_fc_cnt_reg[] = + { + {"smmu1_to_lpm_as_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_smmu1_to_lpm_fc_cnt_reg[] = + { + {"smmu1_to_lpm_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_lpm_as_to_smmu1_req_cnt_reg[] = + { + {"lpm_as_to_smmu1_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_lpm_to_smmu1_req_cnt_reg[] = + { + {"lpm_to_smmu1_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_hash3_0_to_smmu1_fc_cnt_reg[] = + { + {"hash3_0_to_smmu1_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_smmu1_to_hash3_0_rsp_cnt_reg[] = + { + {"smmu1_to_hash3_0_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_smmu1_to_hash3_0_fc_cnt_reg[] = + { + {"smmu1_to_hash3_0_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_hash3_0_to_smmu1_cnt_reg[] = + { + {"hash3_0_to_smmu1_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_se_to_smmu1_dir3_0_rsp_fc_cnt_reg[] = + { + {"se_to_smmu1_dir3_0_rsp_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_smmu1_to_se_dir3_0_rsp_cnt_reg[] = + { + {"smmu1_to_se_dir3_0_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_smmu1_to_se_dir3_0_fc_cnt_reg[] = + { + {"smmu1_to_se_dir3_0_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_se_to_smmu1_dir3_0_cnt_reg[] = + { + {"se_to_smmu1_dir3_0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_smmu1_cache7_0_to_rschd_rsp_cnt_reg[] = + { + {"cache7_0_to_rschd_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cmmu_ddr_rw_addr_reg[] = + { + {"ddr_wr", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cmmu_ddr_rw_mode_reg[] = + { + {"ddr_rw_flag", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, + {"ddr_rw_mode", DPP_FIELD_FLAG_RW, 2, 3, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cmmu_cp_cmd_reg[] = + { + {"stat_tbl_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cmmu_cpu_ind_rd_done_reg[] = + { + {"cpu_ind_rd_done", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cmmu_cpu_ind_rdat0_reg[] = + { + {"cpu_ind_rdat0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cmmu_cpu_ind_rdat1_reg[] = + { + {"cpu_ind_rdat1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cmmu_cpu_ind_rdat2_reg[] = + { + {"cpu_ind_rdat2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cmmu_cpu_ind_rdat3_reg[] = + { + {"cpu_ind_rdat3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cmmu_cpu_ddr_fifo_almful_reg[] = + { + {"cpu_ddr_fifo_almful", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cmmu_debug_cnt_mode_reg[] = + { + {"cnt_rd_mode", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0}, + {"cnt_overflow_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_se_cmmu_cmmu_pful_cfg_reg[] = + { + {"alu_cmd_pful_negate", DPP_FIELD_FLAG_RW, 17, 9, 0xf8, 0x0}, + {"alu_cmd_pful_assert", DPP_FIELD_FLAG_RW, 8, 9, 0xf8, 0x0}, + }; +DPP_FIELD_T g_se_cmmu_cmmu_stat_pful_cfg_reg[] = + { + {"cmmu_stat_pful_negate", DPP_FIELD_FLAG_RW, 11, 6, 0x14, 0x0}, + {"cmmu_stat_pful_assert", DPP_FIELD_FLAG_RW, 5, 6, 0x14, 0x0}, + }; +DPP_FIELD_T g_se_cmmu_stat_overflow_mode_reg[] = + { + {"stat_overflow_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_se_cmmu_cmmu_cp_fifo_pful_reg[] = + { + {"cmmu_cp_fifo_pful", DPP_FIELD_FLAG_RW, 7, 8, 0x66, 0x0}, + }; +DPP_FIELD_T g_se_cmmu_ddr_wr_dat0_reg[] = + { + {"ddr_wr_dat0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cmmu_ddr_wr_dat1_reg[] = + { + {"ddr_wr_dat1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cmmu_cmmu_int_unmask_flag_reg[] = + { + {"cmmu_int_unmask_flag", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cmmu_cmmu_int_en_reg[] = + { + {"cmmu_int_en12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"cmmu_int_en11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"cmmu_int_en10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"cmmu_int_en9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"cmmu_int_en8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"cmmu_int_en7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"cmmu_int_en6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"cmmu_int_en5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"cmmu_int_en4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"cmmu_int_en3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"cmmu_int_en2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"cmmu_int_en1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"cmmu_int_en0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_se_cmmu_cmmu_int_mask_reg[] = + { + {"cmmu_int_mask12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"cmmu_int_mask11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"cmmu_int_mask10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"cmmu_int_mask9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"cmmu_int_mask8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"cmmu_int_mask7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"cmmu_int_mask6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"cmmu_int_mask5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"cmmu_int_mask4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"cmmu_int_mask3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"cmmu_int_mask2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"cmmu_int_mask1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"cmmu_int_mask0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_se_cmmu_cmmu_int_status_reg[] = + { + {"cmmu_int_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"cmmu_int_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"cmmu_int_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"cmmu_int_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"cmmu_int_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"cmmu_int_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"cmmu_int_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"cmmu_int_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"cmmu_int_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"cmmu_int_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"cmmu_int_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"cmmu_int_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"cmmu_int_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cmmu_stat_cmmu_req_cnt_reg[] = + { + {"stat_cmmu_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cmmu_cmmu_fc0_cnt_reg[] = + { + {"cmmu_stat_rdy", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cmmu_cmmu_fc1_cnt_reg[] = + { + {"smmu1_cmmu_wr_rdy", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_se_cmmu_cmmu_fc2_cnt_reg[] = + { + {"smmu1_cmmu_rd_rdy", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu14k_se_smmu1_hash0_tbl0_cfg_reg[] = + { + {"hash0_tbl0_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0}, + {"hash0_tbl0_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"hash0_tbl0_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu14k_se_smmu1_hash0_tbl1_cfg_reg[] = + { + {"hash0_tbl1_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0}, + {"hash0_tbl1_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"hash0_tbl1_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu14k_se_smmu1_hash0_tbl2_cfg_reg[] = + { + {"hash0_tbl2_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0}, + {"hash0_tbl2_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"hash0_tbl2_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu14k_se_smmu1_hash0_tbl3_cfg_reg[] = + { + {"hash0_tbl3_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0}, + {"hash0_tbl3_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"hash0_tbl3_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu14k_se_smmu1_hash0_tbl4_cfg_reg[] = + { + {"hash0_tbl4_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0}, + {"hash0_tbl4_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"hash0_tbl4_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu14k_se_smmu1_hash0_tbl5_cfg_reg[] = + { + {"hash0_tbl5_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0}, + {"hash0_tbl5_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"hash0_tbl5_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu14k_se_smmu1_hash0_tbl6_cfg_reg[] = + { + {"hash0_tbl6_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0}, + {"hash0_tbl6_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"hash0_tbl6_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu14k_se_smmu1_hash0_tbl7_cfg_reg[] = + { + {"hash0_tbl7_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0}, + {"hash0_tbl7_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"hash0_tbl7_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu14k_se_smmu1_hash1_tbl0_cfg_reg[] = + { + {"hash1_tbl0_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0}, + {"hash1_tbl0_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"hash1_tbl0_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu14k_se_smmu1_hash1_tbl1_cfg_reg[] = + { + {"hash1_tbl1_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0}, + {"hash1_tbl1_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"hash1_tbl1_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu14k_se_smmu1_hash1_tbl2_cfg_reg[] = + { + {"hash1_tbl2_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0}, + {"hash1_tbl2_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"hash1_tbl2_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu14k_se_smmu1_hash1_tbl3_cfg_reg[] = + { + {"hash1_tbl3_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0}, + {"hash1_tbl3_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"hash1_tbl3_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu14k_se_smmu1_hash1_tbl4_cfg_reg[] = + { + {"hash1_tbl4_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0}, + {"hash1_tbl4_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"hash1_tbl4_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu14k_se_smmu1_hash1_tbl5_cfg_reg[] = + { + {"hash1_tbl5_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0}, + {"hash1_tbl5_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"hash1_tbl5_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu14k_se_smmu1_hash1_tbl6_cfg_reg[] = + { + {"hash1_tbl6_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0}, + {"hash1_tbl6_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"hash1_tbl6_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu14k_se_smmu1_hash1_tbl7_cfg_reg[] = + { + {"hash1_tbl7_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0}, + {"hash1_tbl7_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"hash1_tbl7_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu14k_se_smmu1_hash2_tbl0_cfg_reg[] = + { + {"hash2_tbl0_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0}, + {"hash2_tbl0_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"hash2_tbl0_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu14k_se_smmu1_hash2_tbl1_cfg_reg[] = + { + {"hash2_tbl1_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0}, + {"hash2_tbl1_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"hash2_tbl1_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu14k_se_smmu1_hash2_tbl2_cfg_reg[] = + { + {"hash2_tbl2_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0}, + {"hash2_tbl2_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"hash2_tbl2_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu14k_se_smmu1_hash2_tbl3_cfg_reg[] = + { + {"hash2_tbl3_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0}, + {"hash2_tbl3_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"hash2_tbl3_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu14k_se_smmu1_hash2_tbl4_cfg_reg[] = + { + {"hash2_tbl4_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0}, + {"hash2_tbl4_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"hash2_tbl4_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu14k_se_smmu1_hash2_tbl5_cfg_reg[] = + { + {"hash2_tbl5_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0}, + {"hash2_tbl5_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"hash2_tbl5_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu14k_se_smmu1_hash2_tbl6_cfg_reg[] = + { + {"hash2_tbl6_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0}, + {"hash2_tbl6_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"hash2_tbl6_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu14k_se_smmu1_hash2_tbl7_cfg_reg[] = + { + {"hash2_tbl7_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0}, + {"hash2_tbl7_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"hash2_tbl7_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu14k_se_smmu1_hash3_tbl0_cfg_reg[] = + { + {"hash3_tbl0_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0}, + {"hash3_tbl0_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"hash3_tbl0_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu14k_se_smmu1_hash3_tbl1_cfg_reg[] = + { + {"hash3_tbl1_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0}, + {"hash3_tbl1_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"hash3_tbl1_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu14k_se_smmu1_hash3_tbl2_cfg_reg[] = + { + {"hash3_tbl2_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0}, + {"hash3_tbl2_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"hash3_tbl2_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu14k_se_smmu1_hash3_tbl3_cfg_reg[] = + { + {"hash3_tbl3_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0}, + {"hash3_tbl3_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"hash3_tbl3_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu14k_se_smmu1_hash3_tbl4_cfg_reg[] = + { + {"hash3_tbl4_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0}, + {"hash3_tbl4_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"hash3_tbl4_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu14k_se_smmu1_hash3_tbl5_cfg_reg[] = + { + {"hash3_tbl5_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0}, + {"hash3_tbl5_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"hash3_tbl5_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu14k_se_smmu1_hash3_tbl6_cfg_reg[] = + { + {"hash3_tbl6_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0}, + {"hash3_tbl6_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"hash3_tbl6_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0}, + }; +DPP_FIELD_T g_smmu14k_se_smmu1_hash3_tbl7_cfg_reg[] = + { + {"hash3_tbl7_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0}, + {"hash3_tbl7_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"hash3_tbl7_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_cpu_ind_eram_wdat1_reg[] = + { + {"cpu_ind_eram_wdat1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_cpu_ind_eram_wdat2_reg[] = + { + {"cpu_ind_eram_wdat2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_cpu_ind_eram_wdat3_reg[] = + { + {"cpu_ind_eram_wdat3", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_cpu_ind_eram_req_info_reg[] = + { + {"rw_mode", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, + {"read_mode", DPP_FIELD_FLAG_RW, 16, 1, 0x0, 0x0}, + {"tm_cs", DPP_FIELD_FLAG_RW, 15, 1, 0x0, 0x0}, + {"queue_cs", DPP_FIELD_FLAG_RW, 14, 1, 0x0, 0x0}, + {"rw_addr", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_cpu_ind_eram_rd_done_reg[] = + { + {"cpu_ind_eram_rd_done", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_cpu_ind_eram_rdat0_reg[] = + { + {"cpu_ind_eram_rdat0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_cpu_ind_eram_rdat1_reg[] = + { + {"cpu_ind_eram_rdat1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_cpu_ind_eram_rdat2_reg[] = + { + {"cpu_ind_eram_rdat2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_cpu_ind_eram_rdat3_reg[] = + { + {"cpu_ind_eram_rdat3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_tm_alu_eram_cpu_rdy_reg[] = + { + {"tm_alu_eram_cpu_rdy", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_oam_stat_cfg_reg[] = + { + {"oam_flow_control_cfg", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"oam_lm_flow_control_cfg", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"oam_in_eram_cfg", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_ftm_port_sel_cfg_reg[] = + { + {"ftm_port0_sel_cfg", DPP_FIELD_FLAG_RW, 19, 5, 0x0, 0x0}, + {"ftm_port1_sel_cfg", DPP_FIELD_FLAG_RW, 14, 5, 0x1, 0x0}, + {"ftm_port2_sel_cfg", DPP_FIELD_FLAG_RW, 9, 5, 0xf, 0x0}, + {"ftm_port3_sel_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x10, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_oam_eram_base_addr_reg[] = + { + {"oam_eram_base_addr", DPP_FIELD_FLAG_RW, 18, 19, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_oam_lm_eram_base_addr_reg[] = + { + {"oam_lm_eram_base_addr", DPP_FIELD_FLAG_RW, 18, 19, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_oam_ddr_base_addr_reg[] = + { + {"oam_ddr_base_addr", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_plcr0_schd_pful_cfg_reg[] = + { + {"plcr0_schd_pful_assert", DPP_FIELD_FLAG_RW, 13, 7, 0x2c, 0x0}, + {"plcr0_schd_pful_negate", DPP_FIELD_FLAG_RW, 6, 7, 0x2c, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_oam_lm_ord_pful_cfg_reg[] = + { + {"oam_lm_ord_pful_assert", DPP_FIELD_FLAG_RW, 13, 7, 0x28, 0x0}, + {"oam_lm_ord_pful_negate", DPP_FIELD_FLAG_RW, 6, 7, 0x28, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_ddr_schd_pful_cfg_reg[] = + { + {"ddr_schd_pful_assert", DPP_FIELD_FLAG_RW, 13, 7, 0x2c, 0x0}, + {"ddr_schd_pful_negate", DPP_FIELD_FLAG_RW, 6, 7, 0x2c, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_eram_schd_pful_cfg_reg[] = + { + {"eram_schd_pful_assert", DPP_FIELD_FLAG_RW, 13, 7, 0x28, 0x0}, + {"eram_schd_pful_negate", DPP_FIELD_FLAG_RW, 6, 7, 0x28, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_eram_schd_pept_cfg_reg[] = + { + {"eram_schd_pept_assert", DPP_FIELD_FLAG_RW, 13, 7, 0x18, 0x0}, + {"eram_schd_pept_negate", DPP_FIELD_FLAG_RW, 6, 7, 0x18, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_eram_schd_oam_pful_cfg_reg[] = + { + {"eram_schd_oam_pful_assert", DPP_FIELD_FLAG_RW, 13, 7, 0x28, 0x0}, + {"eram_schd_oam_pful_negate", DPP_FIELD_FLAG_RW, 6, 7, 0x28, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_eram_schd_oam_pept_cfg_reg[] = + { + {"eram_schd_oam_pept_assert", DPP_FIELD_FLAG_RW, 13, 7, 0x18, 0x0}, + {"eram_schd_oam_pept_negate", DPP_FIELD_FLAG_RW, 6, 7, 0x18, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_eram_schd_oam_lm_pful_cfg_reg[] = + { + {"eram_schd_oam_lm_pful_assert", DPP_FIELD_FLAG_RW, 13, 7, 0x28, 0x0}, + {"eram_schd_oam_lm_pful_negate", DPP_FIELD_FLAG_RW, 6, 7, 0x28, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_eram_schd_oam_lm_pept_cfg_reg[] = + { + {"eram_schd_oam_lm_pept_assert", DPP_FIELD_FLAG_RW, 13, 7, 0x18, 0x0}, + {"eram_schd_oam_lm_pept_negate", DPP_FIELD_FLAG_RW, 6, 7, 0x18, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_rschd_pful_cfg_reg[] = + { + {"rschd_pful_assert", DPP_FIELD_FLAG_RW, 13, 7, 0x24, 0x0}, + {"rschd_pful_negate", DPP_FIELD_FLAG_RW, 6, 7, 0x24, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_rschd_pept_cfg_reg[] = + { + {"rschd_pept_assert", DPP_FIELD_FLAG_RW, 13, 7, 0x1c, 0x0}, + {"rschd_pept_negate", DPP_FIELD_FLAG_RW, 6, 7, 0x1c, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_rschd_plcr_pful_cfg_reg[] = + { + {"rschd_plcr_pful_assert", DPP_FIELD_FLAG_RW, 15, 8, 0x40, 0x0}, + {"rschd_plcr_pful_negate", DPP_FIELD_FLAG_RW, 7, 8, 0x40, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_rschd_plcr_pept_cfg_reg[] = + { + {"rschd_plcr_pept_assert", DPP_FIELD_FLAG_RW, 15, 8, 0x40, 0x0}, + {"rschd_plcr_pept_negate", DPP_FIELD_FLAG_RW, 7, 8, 0x40, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_rschd_plcr_info_pful_cfg_reg[] = + { + {"rschd_plcr_info_pful_assert", DPP_FIELD_FLAG_RW, 13, 7, 0x38, 0x0}, + {"rschd_plcr_info_pful_negate", DPP_FIELD_FLAG_RW, 6, 7, 0x38, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_alu_arb_cpu_pful_cfg_reg[] = + { + {"alu_arb_cpu_pful_assert", DPP_FIELD_FLAG_RW, 9, 5, 0x08, 0x0}, + {"alu_arb_cpu_pful_negate", DPP_FIELD_FLAG_RW, 4, 5, 0x08, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_alu_arb_user_pful_cfg_reg[] = + { + {"alu_arb_user_pful_assert", DPP_FIELD_FLAG_RW, 9, 5, 0x0d, 0x0}, + {"alu_arb_user_pful_negate", DPP_FIELD_FLAG_RW, 4, 5, 0x0d, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_alu_arb_stat_pful_cfg_reg[] = + { + {"alu_arb_stat_pful_assert", DPP_FIELD_FLAG_RW, 13, 7, 0x20, 0x0}, + {"alu_arb_stat_pful_negate", DPP_FIELD_FLAG_RW, 6, 7, 0x20, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_cycmov_dat_pful_cfg_reg[] = + { + {"cycmov_dat_pful_assert", DPP_FIELD_FLAG_RW, 9, 5, 0x0d, 0x0}, + {"cycmov_dat_pful_negate", DPP_FIELD_FLAG_RW, 4, 5, 0x0d, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_ddr_opr_pful_cfg_reg[] = + { + {"ddr_opr_pful_assert", DPP_FIELD_FLAG_RW, 9, 5, 0xc, 0x0}, + {"ddr_opr_pful_negate", DPP_FIELD_FLAG_RW, 4, 5, 0xc, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_cycle_mov_pful_cfg_reg[] = + { + {"cycle_mov_pful_assert", DPP_FIELD_FLAG_RW, 11, 6, 0x1c, 0x0}, + {"cycle_mov_pful_negate", DPP_FIELD_FLAG_RW, 5, 6, 0x1c, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_cntovf_pful_cfg_reg[] = + { + {"cntovf_pful_assert", DPP_FIELD_FLAG_RW, 13, 7, 0x32, 0x0}, + {"cntovf_pful_negate", DPP_FIELD_FLAG_RW, 6, 7, 0x32, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_eram_schd_plcr_pful_cfg_reg[] = + { + {"eram_schd_plcr_pful_assert", DPP_FIELD_FLAG_RW, 15, 8, 0x40, 0x0}, + {"eram_schd_plcr_pful_negate", DPP_FIELD_FLAG_RW, 7, 8, 0x40, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_eram_schd_plcr_pept_cfg_reg[] = + { + {"eram_schd_plcr_pept_assert", DPP_FIELD_FLAG_RW, 15, 8, 0x40, 0x0}, + {"eram_schd_plcr_pept_negate", DPP_FIELD_FLAG_RW, 7, 8, 0x40, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_debug_cnt_mode_reg[] = + { + {"cnt_rd_mode", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0}, + {"cnt_overflow_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_tm_mov_period_cfg_reg[] = + { + {"etm_mov_period_cfg", DPP_FIELD_FLAG_RW, 15, 8, 0x3c, 0x0}, + {"ftm_mov_period_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x3c, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_alu_ddr_cpu_req_pful_cfg_reg[] = + { + {"alu_ddr_cpu_req_pful_assert", DPP_FIELD_FLAG_RW, 7, 4, 0x4, 0x0}, + {"alu_ddr_cpu_req_pful_negate", DPP_FIELD_FLAG_RW, 3, 4, 0x4, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_cycmov_addr_pful_cfg_reg[] = + { + {"cycmov_addr_pful_assert", DPP_FIELD_FLAG_RW, 9, 5, 0xd, 0x0}, + {"cycmov_addr_pful_negate", DPP_FIELD_FLAG_RW, 4, 5, 0xd, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_ord_ddr_plcr_fifo_empty_reg[] = + { + {"ord_oam_lm_empty", DPP_FIELD_FLAG_RO, 19, 1, 0x1, 0x0}, + {"ddr_schd_fifo_empty", DPP_FIELD_FLAG_RO, 18, 7, 0x7f, 0x0}, + {"plcr0_schd_fifo_empty", DPP_FIELD_FLAG_RO, 5, 6, 0x3f, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_tm_stat_fifo_empty_reg[] = + { + {"tm_stat_fifo_empty", DPP_FIELD_FLAG_RO, 13, 14, 0x3fff, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_eram_schd_fifo_empty_0_1_reg[] = + { + {"eram_schd_fifo_empty1", DPP_FIELD_FLAG_RO, 31, 16, 0xffff, 0x0}, + {"eram_schd_fifo_empty0", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_eram_schd_fifo_empty_2_3_reg[] = + { + {"eram_schd_fifo_empty3", DPP_FIELD_FLAG_RO, 31, 16, 0xffff, 0x0}, + {"eram_schd_fifo_empty2", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_eram_schd_fifo_empty_4_5_reg[] = + { + {"eram_schd_fifo_empty5", DPP_FIELD_FLAG_RO, 31, 16, 0xffff, 0x0}, + {"eram_schd_fifo_empty4", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_eram_schd_fifo_empty_6_7_reg[] = + { + {"eram_schd_fifo_empty7", DPP_FIELD_FLAG_RO, 31, 16, 0xffff, 0x0}, + {"eram_schd_fifo_empty6", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_eram_schd_fifo_empty_free_8_reg[] = + { + {"eram_schd_free_fifo_empty8", DPP_FIELD_FLAG_RO, 24, 1, 0x1, 0x0}, + {"eram_schd_free_fifo_empty7", DPP_FIELD_FLAG_RO, 23, 1, 0x1, 0x0}, + {"eram_schd_free_fifo_empty6", DPP_FIELD_FLAG_RO, 22, 1, 0x1, 0x0}, + {"eram_schd_free_fifo_empty5", DPP_FIELD_FLAG_RO, 21, 1, 0x1, 0x0}, + {"eram_schd_free_fifo_empty4", DPP_FIELD_FLAG_RO, 20, 1, 0x1, 0x0}, + {"eram_schd_free_fifo_empty3", DPP_FIELD_FLAG_RO, 19, 1, 0x1, 0x0}, + {"eram_schd_free_fifo_empty2", DPP_FIELD_FLAG_RO, 18, 1, 0x1, 0x0}, + {"eram_schd_free_fifo_empty1", DPP_FIELD_FLAG_RO, 17, 1, 0x1, 0x0}, + {"eram_schd_free_fifo_empty0", DPP_FIELD_FLAG_RO, 16, 1, 0x1, 0x0}, + {"eram_schd_fifo_empty8", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_rschd_fifo_empty_0_3_reg[] = + { + {"rschd_fifo_empty3", DPP_FIELD_FLAG_RO, 31, 8, 0xff, 0x0}, + {"rschd_fifo_empty2", DPP_FIELD_FLAG_RO, 23, 8, 0xff, 0x0}, + {"rschd_fifo_empty1", DPP_FIELD_FLAG_RO, 15, 8, 0xff, 0x0}, + {"rschd_fifo_empty0", DPP_FIELD_FLAG_RO, 7, 8, 0xff, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_rschd_fifo_empty_4_7_reg[] = + { + {"rschd_fifo_empty7", DPP_FIELD_FLAG_RO, 31, 8, 0xff, 0x0}, + {"rschd_fifo_empty6", DPP_FIELD_FLAG_RO, 23, 8, 0xff, 0x0}, + {"rschd_fifo_empty5", DPP_FIELD_FLAG_RO, 15, 8, 0xff, 0x0}, + {"rschd_fifo_empty4", DPP_FIELD_FLAG_RO, 7, 8, 0xff, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_rschd_fifo_empty_8_11_reg[] = + { + {"rschd_fifo_empty11", DPP_FIELD_FLAG_RO, 31, 8, 0xff, 0x0}, + {"rschd_fifo_empty10", DPP_FIELD_FLAG_RO, 23, 8, 0xff, 0x0}, + {"rschd_fifo_empty9", DPP_FIELD_FLAG_RO, 15, 8, 0xff, 0x0}, + {"rschd_fifo_empty8", DPP_FIELD_FLAG_RO, 7, 8, 0xff, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_rschd_fifo_empty_12_15_reg[] = + { + {"rschd_fifo_empty15", DPP_FIELD_FLAG_RO, 31, 8, 0xff, 0x0}, + {"rschd_fifo_empty14", DPP_FIELD_FLAG_RO, 23, 8, 0xff, 0x0}, + {"rschd_fifo_empty13", DPP_FIELD_FLAG_RO, 15, 8, 0xff, 0x0}, + {"rschd_fifo_empty12", DPP_FIELD_FLAG_RO, 7, 8, 0xff, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_rschd_fifo_empty_plcr_16_17_reg[] = + { + {"rschd_fifo_empty_plcr", DPP_FIELD_FLAG_RO, 16, 1, 0x1, 0x0}, + {"rschd_fifo_empty17", DPP_FIELD_FLAG_RO, 15, 8, 0xff, 0x0}, + {"rschd_fifo_empty16", DPP_FIELD_FLAG_RO, 7, 8, 0xff, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_stat_int_unmask_flag_reg[] = + { + {"stat_int5_unmask_flag", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0}, + {"stat_int4_unmask_flag", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0}, + {"stat_int3_unmask_flag", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0}, + {"stat_int2_unmask_flag", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0}, + {"stat_int1_unmask_flag", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0}, + {"stat_int0_unmask_flag", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_stat_int0_en_reg[] = + { + {"stat_int0_en31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0}, + {"stat_int0_en30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0}, + {"stat_int0_en29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0}, + {"stat_int0_en28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0}, + {"stat_int0_en27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0}, + {"stat_int0_en26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0}, + {"stat_int0_en25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0}, + {"stat_int0_en24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0}, + {"stat_int0_en23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0}, + {"stat_int0_en22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0}, + {"stat_int0_en21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0}, + {"stat_int0_en20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"stat_int0_en19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0}, + {"stat_int0_en18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + {"stat_int0_en17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0}, + {"stat_int0_en16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"stat_int0_en15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"stat_int0_en14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"stat_int0_en13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"stat_int0_en12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"stat_int0_en11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"stat_int0_en10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"stat_int0_en9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"stat_int0_en8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"stat_int0_en7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"stat_int0_en6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"stat_int0_en5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"stat_int0_en4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"stat_int0_en3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"stat_int0_en2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"stat_int0_en1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"stat_int0_en0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_stat_int0_mask_reg[] = + { + {"stat_int0_mask31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0}, + {"stat_int0_mask30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0}, + {"stat_int0_mask29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0}, + {"stat_int0_mask28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0}, + {"stat_int0_mask27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0}, + {"stat_int0_mask26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0}, + {"stat_int0_mask25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0}, + {"stat_int0_mask24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0}, + {"stat_int0_mask23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0}, + {"stat_int0_mask22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0}, + {"stat_int0_mask21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0}, + {"stat_int0_mask20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"stat_int0_mask19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0}, + {"stat_int0_mask18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + {"stat_int0_mask17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0}, + {"stat_int0_mask16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"stat_int0_mask15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"stat_int0_mask14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"stat_int0_mask13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"stat_int0_mask12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"stat_int0_mask11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"stat_int0_mask10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"stat_int0_mask9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"stat_int0_mask8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"stat_int0_mask7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"stat_int0_mask6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"stat_int0_mask5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"stat_int0_mask4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"stat_int0_mask3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"stat_int0_mask2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"stat_int0_mask1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"stat_int0_mask0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_stat_int0_status_reg[] = + { + {"stat_int0_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"stat_int0_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"stat_int0_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"stat_int0_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"stat_int0_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"stat_int0_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"stat_int0_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"stat_int0_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"stat_int0_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"stat_int0_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"stat_int0_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"stat_int0_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"stat_int0_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"stat_int0_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"stat_int0_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"stat_int0_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"stat_int0_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"stat_int0_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"stat_int0_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"stat_int0_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"stat_int0_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"stat_int0_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"stat_int0_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"stat_int0_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"stat_int0_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"stat_int0_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"stat_int0_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"stat_int0_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"stat_int0_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"stat_int0_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"stat_int0_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"stat_int0_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_stat_int1_en_reg[] = + { + {"stat_int1_en31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0}, + {"stat_int1_en30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0}, + {"stat_int1_en29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0}, + {"stat_int1_en28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0}, + {"stat_int1_en27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0}, + {"stat_int1_en26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0}, + {"stat_int1_en25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0}, + {"stat_int1_en24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0}, + {"stat_int1_en23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0}, + {"stat_int1_en22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0}, + {"stat_int1_en21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0}, + {"stat_int1_en20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"stat_int1_en19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0}, + {"stat_int1_en18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + {"stat_int1_en17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0}, + {"stat_int1_en16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"stat_int1_en15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"stat_int1_en14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"stat_int1_en13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"stat_int1_en12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"stat_int1_en11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"stat_int1_en10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"stat_int1_en9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"stat_int1_en8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"stat_int1_en7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"stat_int1_en6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"stat_int1_en5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"stat_int1_en4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"stat_int1_en3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"stat_int1_en2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"stat_int1_en1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"stat_int1_en0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_stat_int1_mask_reg[] = + { + {"stat_int1_mask31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0}, + {"stat_int1_mask30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0}, + {"stat_int1_mask29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0}, + {"stat_int1_mask28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0}, + {"stat_int1_mask27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0}, + {"stat_int1_mask26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0}, + {"stat_int1_mask25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0}, + {"stat_int1_mask24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0}, + {"stat_int1_mask23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0}, + {"stat_int1_mask22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0}, + {"stat_int1_mask21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0}, + {"stat_int1_mask20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"stat_int1_mask19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0}, + {"stat_int1_mask18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + {"stat_int1_mask17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0}, + {"stat_int1_mask16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"stat_int1_mask15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"stat_int1_mask14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"stat_int1_mask13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"stat_int1_mask12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"stat_int1_mask11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"stat_int1_mask10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"stat_int1_mask9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"stat_int1_mask8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"stat_int1_mask7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"stat_int1_mask6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"stat_int1_mask5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"stat_int1_mask4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"stat_int1_mask3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"stat_int1_mask2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"stat_int1_mask1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"stat_int1_mask0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_stat_int1_status_reg[] = + { + {"stat_int1_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"stat_int1_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"stat_int1_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"stat_int1_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"stat_int1_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"stat_int1_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"stat_int1_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"stat_int1_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"stat_int1_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"stat_int1_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"stat_int1_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"stat_int1_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"stat_int1_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"stat_int1_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"stat_int1_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"stat_int1_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"stat_int1_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"stat_int1_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"stat_int1_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"stat_int1_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"stat_int1_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"stat_int1_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"stat_int1_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"stat_int1_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"stat_int1_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"stat_int1_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"stat_int1_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"stat_int1_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"stat_int1_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"stat_int1_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"stat_int1_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"stat_int1_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_stat_int2_en_reg[] = + { + {"stat_int2_en31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0}, + {"stat_int2_en30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0}, + {"stat_int2_en29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0}, + {"stat_int2_en28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0}, + {"stat_int2_en27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0}, + {"stat_int2_en26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0}, + {"stat_int2_en25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0}, + {"stat_int2_en24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0}, + {"stat_int2_en23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0}, + {"stat_int2_en22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0}, + {"stat_int2_en21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0}, + {"stat_int2_en20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"stat_int2_en19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0}, + {"stat_int2_en18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + {"stat_int2_en17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0}, + {"stat_int2_en16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"stat_int2_en15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"stat_int2_en14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"stat_int2_en13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"stat_int2_en12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"stat_int2_en11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"stat_int2_en10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"stat_int2_en9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"stat_int2_en8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"stat_int2_en7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"stat_int2_en6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"stat_int2_en5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"stat_int2_en4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"stat_int2_en3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"stat_int2_en2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"stat_int2_en1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"stat_int2_en0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_stat_int2_mask_reg[] = + { + {"stat_int2_mask31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0}, + {"stat_int2_mask30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0}, + {"stat_int2_mask29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0}, + {"stat_int2_mask28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0}, + {"stat_int2_mask27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0}, + {"stat_int2_mask26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0}, + {"stat_int2_mask25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0}, + {"stat_int2_mask24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0}, + {"stat_int2_mask23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0}, + {"stat_int2_mask22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0}, + {"stat_int2_mask21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0}, + {"stat_int2_mask20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"stat_int2_mask19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0}, + {"stat_int2_mask18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + {"stat_int2_mask17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0}, + {"stat_int2_mask16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"stat_int2_mask15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"stat_int2_mask14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"stat_int2_mask13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"stat_int2_mask12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"stat_int2_mask11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"stat_int2_mask10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"stat_int2_mask9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"stat_int2_mask8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"stat_int2_mask7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"stat_int2_mask6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"stat_int2_mask5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"stat_int2_mask4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"stat_int2_mask3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"stat_int2_mask2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"stat_int2_mask1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"stat_int2_mask0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_stat_int2_status_reg[] = + { + {"stat_int2_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"stat_int2_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"stat_int2_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"stat_int2_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"stat_int2_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"stat_int2_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"stat_int2_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"stat_int2_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"stat_int2_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"stat_int2_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"stat_int2_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"stat_int2_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"stat_int2_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"stat_int2_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"stat_int2_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"stat_int2_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"stat_int2_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"stat_int2_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"stat_int2_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"stat_int2_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"stat_int2_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"stat_int2_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"stat_int2_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"stat_int2_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"stat_int2_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"stat_int2_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"stat_int2_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"stat_int2_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"stat_int2_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"stat_int2_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"stat_int2_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"stat_int2_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_stat_int3_en_reg[] = + { + {"stat_int3_en31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0}, + {"stat_int3_en30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0}, + {"stat_int3_en29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0}, + {"stat_int3_en28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0}, + {"stat_int3_en27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0}, + {"stat_int3_en26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0}, + {"stat_int3_en25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0}, + {"stat_int3_en24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0}, + {"stat_int3_en23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0}, + {"stat_int3_en22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0}, + {"stat_int3_en21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0}, + {"stat_int3_en20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"stat_int3_en19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0}, + {"stat_int3_en18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + {"stat_int3_en17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0}, + {"stat_int3_en16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"stat_int3_en15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"stat_int3_en14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"stat_int3_en13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"stat_int3_en12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"stat_int3_en11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"stat_int3_en10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"stat_int3_en9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"stat_int3_en8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"stat_int3_en7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"stat_int3_en6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"stat_int3_en5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"stat_int3_en4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"stat_int3_en3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"stat_int3_en2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"stat_int3_en1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"stat_int3_en0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_stat_int3_mask_reg[] = + { + {"stat_int3_mask31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0}, + {"stat_int3_mask30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0}, + {"stat_int3_mask29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0}, + {"stat_int3_mask28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0}, + {"stat_int3_mask27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0}, + {"stat_int3_mask26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0}, + {"stat_int3_mask25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0}, + {"stat_int3_mask24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0}, + {"stat_int3_mask23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0}, + {"stat_int3_mask22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0}, + {"stat_int3_mask21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0}, + {"stat_int3_mask20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0}, + {"stat_int3_mask19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0}, + {"stat_int3_mask18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + {"stat_int3_mask17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0}, + {"stat_int3_mask16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"stat_int3_mask15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"stat_int3_mask14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"stat_int3_mask13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"stat_int3_mask12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"stat_int3_mask11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"stat_int3_mask10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"stat_int3_mask9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"stat_int3_mask8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"stat_int3_mask7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"stat_int3_mask6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"stat_int3_mask5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"stat_int3_mask4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"stat_int3_mask3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"stat_int3_mask2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"stat_int3_mask1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"stat_int3_mask0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_stat_int3_status_reg[] = + { + {"stat_int3_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0}, + {"stat_int3_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0}, + {"stat_int3_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0}, + {"stat_int3_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0}, + {"stat_int3_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0}, + {"stat_int3_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0}, + {"stat_int3_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0}, + {"stat_int3_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0}, + {"stat_int3_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0}, + {"stat_int3_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0}, + {"stat_int3_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0}, + {"stat_int3_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0}, + {"stat_int3_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0}, + {"stat_int3_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"stat_int3_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"stat_int3_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"stat_int3_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"stat_int3_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"stat_int3_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"stat_int3_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"stat_int3_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"stat_int3_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"stat_int3_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"stat_int3_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"stat_int3_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"stat_int3_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"stat_int3_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"stat_int3_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"stat_int3_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"stat_int3_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"stat_int3_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"stat_int3_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_stat_int4_en_reg[] = + { + {"stat_int4_en_18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + {"stat_int4_en_17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0}, + {"stat_int4_en_16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"stat_int4_en_15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"stat_int4_en_14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"stat_int4_en_13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"stat_int4_en_12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"stat_int4_en_11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"stat_int4_en_10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"stat_int4_en_9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"stat_int4_en_8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"stat_int4_en_7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"stat_int4_en_6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"stat_int4_en_5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"stat_int4_en_4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"stat_int4_en_3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"stat_int4_en_2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"stat_int4_en_1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"stat_int4_en_0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_stat_int4_mask_reg[] = + { + {"stat_int4_mask_18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + {"stat_int4_mask_17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0}, + {"stat_int4_mask_16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"stat_int4_mask_15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"stat_int4_mask_14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"stat_int4_mask_13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"stat_int4_mask_12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"stat_int4_mask_11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"stat_int4_mask_10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"stat_int4_mask_9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"stat_int4_mask_8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"stat_int4_mask_7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"stat_int4_mask_6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"stat_int4_mask_5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"stat_int4_mask_4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"stat_int4_mask_3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"stat_int4_mask_2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"stat_int4_mask_1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"stat_int4_mask_0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_stat_int4_status_reg[] = + { + {"stat_int4_mask_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"stat_int4_mask_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"stat_int4_mask_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"stat_int4_mask_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"stat_int4_mask_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"stat_int4_mask_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"stat_int4_mask_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"stat_int4_mask_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"stat_int4_mask_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"stat_int4_mask_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"stat_int4_mask_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"stat_int4_mask_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"stat_int4_mask_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"stat_int4_mask_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"stat_int4_mask_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"stat_int4_mask_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"stat_int4_mask_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"stat_int4_mask_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"stat_int4_mask_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_stat_int5_en_reg[] = + { + {"stat_int5_en_18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + {"stat_int5_en_17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0}, + {"stat_int5_en_16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"stat_int5_en_15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"stat_int5_en_14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"stat_int5_en_13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"stat_int5_en_12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"stat_int5_en_11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"stat_int5_en_10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"stat_int5_en_9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"stat_int5_en_8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"stat_int5_en_7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"stat_int5_en_6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"stat_int5_en_5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"stat_int5_en_4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"stat_int5_en_3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"stat_int5_en_2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"stat_int5_en_1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"stat_int5_en_0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_stat_int5_mask_reg[] = + { + {"stat_int5_mask_18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + {"stat_int5_mask_17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0}, + {"stat_int5_mask_16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"stat_int5_mask_15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"stat_int5_mask_14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"stat_int5_mask_13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"stat_int5_mask_12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"stat_int5_mask_11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"stat_int5_mask_10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"stat_int5_mask_9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"stat_int5_mask_8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"stat_int5_mask_7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"stat_int5_mask_6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"stat_int5_mask_5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"stat_int5_mask_4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"stat_int5_mask_3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"stat_int5_mask_2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"stat_int5_mask_1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"stat_int5_mask_0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_stat_int5_status_reg[] = + { + {"stat_int5_mask_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"stat_int5_mask_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"stat_int5_mask_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"stat_int5_mask_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"stat_int5_mask_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"stat_int5_mask_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"stat_int5_mask_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"stat_int5_mask_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"stat_int5_mask_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"stat_int5_mask_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"stat_int5_mask_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"stat_int5_mask_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"stat_int5_mask_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"stat_int5_mask_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"stat_int5_mask_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"stat_int5_mask_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"stat_int5_mask_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"stat_int5_mask_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"stat_int5_mask_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_rschd_ecc_bypass_reg[] = + { + {"rschd_ecc_bypass_18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0}, + {"rschd_ecc_bypass_17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0}, + {"rschd_ecc_bypass_16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"rschd_ecc_bypass_15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"rschd_ecc_bypass_14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"rschd_ecc_bypass_13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"rschd_ecc_bypass_12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"rschd_ecc_bypass_11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"rschd_ecc_bypass_10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"rschd_ecc_bypass_9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"rschd_ecc_bypass_8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"rschd_ecc_bypass_7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"rschd_ecc_bypass_6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"rschd_ecc_bypass_5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"rschd_ecc_bypass_4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"rschd_ecc_bypass_3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"rschd_ecc_bypass_2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"rschd_ecc_bypass_1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"rschd_ecc_bypass_0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_rschd_ecc_single_err_reg[] = + { + {"rschd_ecc_single_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"rschd_ecc_single_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"rschd_ecc_single_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"rschd_ecc_single_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"rschd_ecc_single_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"rschd_ecc_single_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"rschd_ecc_single_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"rschd_ecc_single_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"rschd_ecc_single_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"rschd_ecc_single_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"rschd_ecc_single_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"rschd_ecc_single_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"rschd_ecc_single_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"rschd_ecc_single_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"rschd_ecc_single_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"rschd_ecc_single_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"rschd_ecc_single_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"rschd_ecc_single_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"rschd_ecc_single_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_rschd_ecc_double_err_reg[] = + { + {"rschd_ecc_double_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0}, + {"rschd_ecc_double_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"rschd_ecc_double_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"rschd_ecc_double_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"rschd_ecc_double_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"rschd_ecc_double_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"rschd_ecc_double_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"rschd_ecc_double_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"rschd_ecc_double_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"rschd_ecc_double_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"rschd_ecc_double_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"rschd_ecc_double_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"rschd_ecc_double_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"rschd_ecc_double_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"rschd_ecc_double_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"rschd_ecc_double_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"rschd_ecc_double_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"rschd_ecc_double_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"rschd_ecc_double_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_wdat0_reg[] = + { + {"cpu_ind_ddr_wdat0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_wdat1_reg[] = + { + {"cpu_ind_ddr_wdat1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_wdat2_reg[] = + { + {"cpu_ind_ddr_wdat2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_wdat3_reg[] = + { + {"cpu_ind_ddr_wdat3", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_wdat4_reg[] = + { + {"cpu_ind_ddr_wdat4", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_wdat5_reg[] = + { + {"cpu_ind_ddr_wdat5", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_wdat6_reg[] = + { + {"cpu_ind_ddr_wdat6", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_wdat7_reg[] = + { + {"cpu_ind_ddr_wdat7", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_wdat8_reg[] = + { + {"cpu_ind_ddr_wdat8", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_wdat9_reg[] = + { + {"cpu_ind_ddr_wdat9", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_wdat10_reg[] = + { + {"cpu_ind_ddr_wdat10", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_wdat11_reg[] = + { + {"cpu_ind_ddr_wdat11", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_wdat12_reg[] = + { + {"cpu_ind_ddr_wdat12", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_wdat13_reg[] = + { + {"cpu_ind_ddr_wdat13", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_wdat14_reg[] = + { + {"cpu_ind_ddr_wdat14", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_wdat15_reg[] = + { + {"cpu_ind_ddr_wdat15", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_req_info_reg[] = + { + {"rw_mode", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, + {"read_mode", DPP_FIELD_FLAG_RW, 15, 1, 0x0, 0x0}, + {"tm_cs", DPP_FIELD_FLAG_RW, 14, 1, 0x0, 0x0}, + {"rw_addr", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_rd_done_reg[] = + { + {"cpu_ind_ddr_rd_done", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_rdat0_reg[] = + { + {"cpu_ind_ddr_rdat0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_rdat1_reg[] = + { + {"cpu_ind_ddr_rdat1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_rdat2_reg[] = + { + {"cpu_ind_ddr_rdat2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_rdat3_reg[] = + { + {"cpu_ind_ddr_rdat3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_rdat4_reg[] = + { + {"cpu_ind_ddr_rdat4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_rdat5_reg[] = + { + {"cpu_ind_ddr_rdat5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_rdat6_reg[] = + { + {"cpu_ind_ddr_rdat6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_rdat7_reg[] = + { + {"cpu_ind_ddr_rdat7", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_rdat8_reg[] = + { + {"cpu_ind_ddr_rdat8", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_rdat9_reg[] = + { + {"cpu_ind_ddr_rdat9", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_rdat10_reg[] = + { + {"cpu_ind_ddr_rdat10", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_rdat11_reg[] = + { + {"cpu_ind_ddr_rdat11", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_rdat12_reg[] = + { + {"cpu_ind_ddr_rdat12", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_rdat13_reg[] = + { + {"cpu_ind_ddr_rdat13", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_rdat14_reg[] = + { + {"cpu_ind_ddr_rdat14", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_rdat15_reg[] = + { + {"cpu_ind_ddr_rdat15", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_tm_alu_ddr_cpu_rdy_reg[] = + { + {"tm_alu_ddr_cpu_rdy", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_ept_flag_reg[] = + { + {"ept_flag", DPP_FIELD_FLAG_RO, 5, 6, 0x3f, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_ppu_soft_rst_reg[] = + { + {"ppu_soft_rst", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_stat_smmu0_fc15_0_cnt_reg[] = + { + {"stat_smmu0_fc15_0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_smmu0_stat_fc15_0_cnt_reg[] = + { + {"smmu0_stat_fc15_0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_smmu0_stat_rsp15_0_cnt_reg[] = + { + {"smmu0_stat_rsp15_0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_stat_smmu0_req15_0_cnt_reg[] = + { + {"stat_smmu0_req15_0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_ppu_stat_mec5_0_rsp_fc_cnt_reg[] = + { + {"ppu_stat_mec5_0_rsp_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_stat_ppu_mec5_0_key_fc_cnt_reg[] = + { + {"stat_ppu_mec5_0_key_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_stat_ppu_mec5_0_rsp_cnt_reg[] = + { + {"stat_ppu_mec5_0_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_ppu_stat_mec5_0_key_cnt_reg[] = + { + {"ppu_stat_mec5_0_key_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_ppu5_0_no_exist_opcd_ex_cnt_reg[] = + { + {"ppu5_0_no_exist_opcd_ex_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_se_etm_stat_wr_fc_cnt_reg[] = + { + {"se_etm_stat_wr_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_se_etm_stat_rd_fc_cnt_reg[] = + { + {"se_etm_stat_rd_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_stat_etm_deq_fc_cnt_reg[] = + { + {"stat_etm_deq_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_stat_etm_enq_fc_cnt_reg[] = + { + {"stat_etm_enq_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_stat_oam_lm_fc_cnt_reg[] = + { + {"stat_oam_lm_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_oam_stat_lm_fc_cnt_reg[] = + { + {"oam_stat_lm_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_stat_oam_fc_cnt_reg[] = + { + {"stat_oam_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_cmmu_stat_fc_cnt_reg[] = + { + {"cmmu_stat_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_stat_cmmu_req_cnt_reg[] = + { + {"stat_cmmu_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_smmu0_plcr_rsp0_cnt_reg[] = + { + {"smmu0_plcr_rsp0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_plcr_smmu0_req0_cnt_reg[] = + { + {"plcr_smmu0_req0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_stat_oam_lm_rsp_cnt_reg[] = + { + {"stat_oam_lm_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_oam_stat_lm_req_cnt_reg[] = + { + {"oam_stat_lm_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_oam_stat_req_cnt_reg[] = + { + {"oam_stat_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_se_etm_stat_rsp_cnt_reg[] = + { + {"se_etm_stat_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_etm_stat_se_wr_req_cnt_reg[] = + { + {"etm_stat_se_wr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_etm_stat_se_rd_req_cnt_reg[] = + { + {"etm_stat_se_rd_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_etm_stat_smmu0_req_cnt0_reg[] = + { + {"etm_stat_smmu0_req_cnt0", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_etm_stat_smmu0_req_cnt1_reg[] = + { + {"etm_stat_smmu0_req_cnt1", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_tm_stat_eram_cpu_rsp_cnt_reg[] = + { + {"tm_stat_eram_cpu_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_cpu_rd_eram_req_cnt_reg[] = + { + {"cpu_rd_eram_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_cpu_wr_eram_req_cnt_reg[] = + { + {"cpu_wr_eram_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_tm_stat_ddr_cpu_rsp_cnt_reg[] = + { + {"tm_stat_ddr_cpu_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_cpu_rd_ddr_req_cnt_reg[] = + { + {"cpu_rd_ddr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_stat_cfg_cpu_wr_ddr_req_cnt_reg[] = + { + {"cpu_wr_ddr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_cpu_ind_wdat1_reg[] = + { + {"wdat1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_cpu_ind_wdat2_reg[] = + { + {"wdat2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_cpu_ind_wdat3_reg[] = + { + {"wdat3", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_cpu_ind_wdat4_reg[] = + { + {"wdat4", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_cpu_ind_wdat5_reg[] = + { + {"wdat5", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_cpu_ind_wdat6_reg[] = + { + {"wdat6", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_cpu_ind_wdat7_reg[] = + { + {"wdat7", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_cpu_ind_wdat8_reg[] = + { + {"wdat8", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_cpu_ind_wdat9_reg[] = + { + {"wdat9", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_cpu_ind_wdat10_reg[] = + { + {"wdat10", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_cpu_ind_wdat11_reg[] = + { + {"wdat11", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_cpu_ind_wdat12_reg[] = + { + {"wdat12", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_cpu_ind_wdat13_reg[] = + { + {"wdat13", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_cpu_ind_wdat14_reg[] = + { + {"wdat14", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_cpu_ind_wdat15_reg[] = + { + {"wdat15", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_cpu_ind_wdat16_reg[] = + { + {"wdat16", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_cpu_ind_wdat17_reg[] = + { + {"wdat17", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_cpu_ind_wdat18_reg[] = + { + {"wdat18", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_cpu_ind_wdat19_reg[] = + { + {"wdat19", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_t_strwc_cfg_reg[] = + { + {"t_strwc_cfg", DPP_FIELD_FLAG_RW, 1, 2, 0x1, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_etcam_int_unmask_flag_reg[] = + { + {"etcam_int_unmask_flag", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_etcam_int_en0_reg[] = + { + {"etcam_int_en17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0}, + {"etcam_int_en16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"etcam_int_en15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"etcam_int_en14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"etcam_int_en13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"etcam_int_en12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"etcam_int_en11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"etcam_int_en10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"etcam_int_en9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"etcam_int_en8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"etcam_int_en7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"etcam_int_en6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"etcam_int_en5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"etcam_int_en4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"etcam_int_en3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"etcam_int_en2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"etcam_int_en1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"etcam_int_en0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_etcam_int_mask0_reg[] = + { + {"etcam_int_mask17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0}, + {"etcam_int_mask16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0}, + {"etcam_int_mask15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0}, + {"etcam_int_mask14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"etcam_int_mask13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0}, + {"etcam_int_mask12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0}, + {"etcam_int_mask11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0}, + {"etcam_int_mask10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0}, + {"etcam_int_mask9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0}, + {"etcam_int_mask8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0}, + {"etcam_int_mask7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0}, + {"etcam_int_mask6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0}, + {"etcam_int_mask5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0}, + {"etcam_int_mask4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0}, + {"etcam_int_mask3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0}, + {"etcam_int_mask2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0}, + {"etcam_int_mask1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0}, + {"etcam_int_mask0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_etcam_int_status_reg[] = + { + {"etcam_int_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0}, + {"etcam_int_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0}, + {"etcam_int_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0}, + {"etcam_int_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0}, + {"etcam_int_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0}, + {"etcam_int_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0}, + {"etcam_int_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0}, + {"etcam_int_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0}, + {"etcam_int_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0}, + {"etcam_int_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0}, + {"etcam_int_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0}, + {"etcam_int_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0}, + {"etcam_int_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0}, + {"etcam_int_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0}, + {"etcam_int_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0}, + {"etcam_int_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0}, + {"etcam_int_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0}, + {"etcam_int_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_int_tb_ini_ok_reg[] = + { + {"int_tb_ini_ok", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_etcam_clk_en_reg[] = + { + {"etcam_clk_en", DPP_FIELD_FLAG_RW, 7, 8, 0xff, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_as_etcam_req0_cnt_reg[] = + { + {"as_etcam_req0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_as_etcam_req1_cnt_reg[] = + { + {"as_etcam_req1_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_etcam_as_index0_cnt_reg[] = + { + {"etcam_as_index0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_etcam_as_index1_cnt_reg[] = + { + {"etcam_as_index1_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_etcam_not_hit0_cnt_reg[] = + { + {"etcam_not_hit0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_etcam_not_hit1_cnt_reg[] = + { + {"etcam_not_hit1_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_table_id_not_match_cnt_reg[] = + { + {"table_id_not_match_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_table_id_clash01_cnt_reg[] = + { + {"table_id_clash01_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_etcam_cpu_fl_reg[] = + { + {"etcam_cpu_fl", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_stat_etcam_etcam_arb_empty_reg[] = + { + {"etcam_arb_empty", DPP_FIELD_FLAG_RO, 31, 32, 0xffffffff, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_cfg_finish_int_event0_reg[] = + { + {"cfg_finish_int_event0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_cfg_finish_int_event1_reg[] = + { + {"cfg_finish_int_event1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_cfg_finish_int_event2_reg[] = + { + {"cfg_finish_int_event2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_cfg_finish_int_event3_reg[] = + { + {"cfg_finish_int_event3", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_cfg_finish_int_maks0_reg[] = + { + {"cfg_finish_int_mask0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_cfg_finish_int_maks1_reg[] = + { + {"cfg_finish_int_mask1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_cfg_finish_int_maks2_reg[] = + { + {"cfg_finish_int_mask2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_cfg_finish_int_maks3_reg[] = + { + {"cfg_finish_int_mask3", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_cfg_finish_int_test0_reg[] = + { + {"cfg_finish_int_test0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_cfg_finish_int_test1_reg[] = + { + {"cfg_finish_int_test1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_cfg_finish_int_test2_reg[] = + { + {"cfg_finish_int_test2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_cfg_finish_int_test3_reg[] = + { + {"cfg_finish_int_test3", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_cfg_dtb_int_to_riscv_sel_reg[] = + { + {"cfg_dtb_int_to_riscv_sel0", DPP_FIELD_FLAG_RW, 6, 7, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_cfg_dtb_ep_int_msix_enable_reg[] = + { + {"cfg_dtb_ep_int_msix_enable", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_cfg_dtb_ep_doorbell_addr_h_0_15_reg[] = + { + {"cfg_dtb_ep_doorbell_addr_h_0_15", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_cfg_dtb_ep_doorbell_addr_l_0_15_reg[] = + { + {"cfg_dtb_ep_doorbell_addr_l_0_15", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_cfg_dtb_debug_mode_en_reg[] = + { + {"cfg_dtb_debug_mode_en", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_rd_table_addr_high_reg[] = + { + {"info_axi_last_rd_table_addr_high", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_rd_table_addr_low_reg[] = + { + {"info_axi_last_rd_table_addr_low", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_rd_table_len_reg[] = + { + {"info_axi_last_rd_table_len", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_rd_table_user_reg[] = + { + {"info_rd_table_user_en", DPP_FIELD_FLAG_RO, 31, 1, 0x0, 0x0}, + {"info_rd_table_epid", DPP_FIELD_FLAG_RO, 27, 4, 0x0, 0x0}, + {"info_rd_table_vfunc_num", DPP_FIELD_FLAG_RO, 23, 8, 0x0, 0x0}, + {"info_rd_table_func_num", DPP_FIELD_FLAG_RO, 7, 3, 0x0, 0x0}, + {"info_rd_table_vfunc_active", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_rd_table_onload_cnt_reg[] = + { + {"info_axi_last_rd_table_onload_cnt", DPP_FIELD_FLAG_RO, 3, 4, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_cnt_axi_rd_table_resp_err_reg[] = + { + {"cnt_axi_rd_table_resp_err", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_rd_pd_addr_high_reg[] = + { + {"info_axi_last_rd_pd_addr_high", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_rd_pd_addr_low_reg[] = + { + {"info_axi_last_rd_pd_addr_low", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_rd_pd_len_reg[] = + { + {"info_axi_last_rd_pd_len", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_rd_pd_user_reg[] = + { + {"info_rd_pd_user_en", DPP_FIELD_FLAG_RO, 31, 1, 0x0, 0x0}, + {"info_rd_pd_epid", DPP_FIELD_FLAG_RO, 27, 4, 0x0, 0x0}, + {"info_rd_pd_vfunc_num", DPP_FIELD_FLAG_RO, 23, 8, 0x0, 0x0}, + {"info_rd_pd_func_num", DPP_FIELD_FLAG_RO, 7, 3, 0x0, 0x0}, + {"info_rd_pd_vfunc_active", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_rd_pd_onload_cnt_reg[] = + { + {"info_axi_last_rd_pd_onload_cnt", DPP_FIELD_FLAG_RO, 3, 4, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_cnt_axi_rd_pd_resp_err_reg[] = + { + {"cnt_axi_rd_pd_resp_err", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_wr_ctrl_addr_high_reg[] = + { + {"info_axi_last_wr_ctrl_addr_high", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_wr_ctrl_addr_low_reg[] = + { + {"info_axi_last_wr_ctrl_addr_low", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_wr_ctrl_len_reg[] = + { + {"info_axi_last_wr_ctrl_len", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_wr_ctrl_user_reg[] = + { + {"info_wr_ctrl_user_en", DPP_FIELD_FLAG_RO, 31, 1, 0x0, 0x0}, + {"info_wr_ctrl_epid", DPP_FIELD_FLAG_RO, 27, 4, 0x0, 0x0}, + {"info_wr_ctrl_vfunc_num", DPP_FIELD_FLAG_RO, 23, 8, 0x0, 0x0}, + {"info_wr_ctrl_func_num", DPP_FIELD_FLAG_RO, 7, 3, 0x0, 0x0}, + {"info_wr_ctrl_vfunc_active", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_wr_ctrl_onload_cnt_reg[] = + { + {"info_axi_last_wr_ctrl_onload_cnt", DPP_FIELD_FLAG_RO, 3, 4, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_cnt_axi_wr_ctrl_resp_err_reg[] = + { + {"cnt_axi_wr_ctrl_resp_err", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_wr_ddr_addr_high_reg[] = + { + {"info_axi_last_wr_ddr_addr_high", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_wr_ddr_addr_low_reg[] = + { + {"info_axi_last_wr_ddr_addr_low", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_wr_ddr_len_reg[] = + { + {"info_axi_last_wr_ddr_len", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_wr_ddr_user_reg[] = + { + {"info_wr_ddr_user_en", DPP_FIELD_FLAG_RO, 31, 1, 0x0, 0x0}, + {"info_wr_ddr_epid", DPP_FIELD_FLAG_RO, 27, 4, 0x0, 0x0}, + {"info_wr_ddr_vfunc_num", DPP_FIELD_FLAG_RO, 23, 8, 0x0, 0x0}, + {"info_wr_ddr_func_num", DPP_FIELD_FLAG_RO, 7, 3, 0x0, 0x0}, + {"info_wr_ddr_vfunc_active", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_wr_ddr_onload_cnt_reg[] = + { + {"info_axi_last_wr_ddr_onload_cnt", DPP_FIELD_FLAG_RO, 3, 4, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_cnt_axi_wr_ddr_resp_err_reg[] = + { + {"cnt_axi_wr_ddr_resp_err", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_wr_fin_addr_high_reg[] = + { + {"info_axi_last_wr_fin_addr_high", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_wr_fin_addr_low_reg[] = + { + {"info_axi_last_wr_fin_addr_low", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_wr_fin_len_reg[] = + { + {"info_axi_last_wr_fin_len", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_wr_fin_user_reg[] = + { + {"info_wr_fin_user_en", DPP_FIELD_FLAG_RO, 31, 1, 0x0, 0x0}, + {"info_wr_fin_epid", DPP_FIELD_FLAG_RO, 27, 4, 0x0, 0x0}, + {"info_wr_fin_vfunc_num", DPP_FIELD_FLAG_RO, 23, 8, 0x0, 0x0}, + {"info_wr_fin_func_num", DPP_FIELD_FLAG_RO, 7, 3, 0x0, 0x0}, + {"info_wr_fin_vfunc_active", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_wr_fin_onload_cnt_reg[] = + { + {"info_axi_last_wr_fin_onload_cnt", DPP_FIELD_FLAG_RO, 3, 4, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_cnt_axi_wr_fin_resp_err_reg[] = + { + {"cnt_axi_wr_fin_resp_err", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_cnt_dtb_wr_smmu0_table_high_reg[] = + { + {"cnt_dtb_wr_smmu0_table_high", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_cnt_dtb_wr_smmu0_table_low_reg[] = + { + {"cnt_dtb_wr_smmu0_table_low", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_cnt_dtb_wr_smmu1_table_high_reg[] = + { + {"cnt_dtb_wr_smmu1_table_high", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_cnt_dtb_wr_smmu1_table_low_reg[] = + { + {"cnt_dtb_wr_smmu1_table_low", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_cnt_dtb_wr_zcam_table_high_reg[] = + { + {"cnt_dtb_wr_zcam_table_high", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_cnt_dtb_wr_zcam_table_low_reg[] = + { + {"cnt_dtb_wr_zcam_table_low", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_cnt_dtb_wr_etcam_table_high_reg[] = + { + {"cnt_dtb_wr_etcam_table_high", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_cnt_dtb_wr_etcam_table_low_reg[] = + { + {"cnt_dtb_wr_etcam_table_low", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_cnt_dtb_wr_hash_table_high_reg[] = + { + {"cnt_dtb_wr_hash_table_high", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_cnt_dtb_wr_hash_table_low_reg[] = + { + {"cnt_dtb_wr_hash_table_low", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_cnt_dtb_rd_smmu0_table_high_reg[] = + { + {"cnt_dtb_rd_smmu0_table_high", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_cnt_dtb_rd_smmu0_table_low_reg[] = + { + {"cnt_dtb_rd_smmu0_table_low", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_cnt_dtb_rd_smmu1_table_high_reg[] = + { + {"cnt_dtb_rd_smmu1_table_high", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_cnt_dtb_rd_smmu1_table_low_reg[] = + { + {"cnt_dtb_rd_smmu1_table_low", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_cnt_dtb_rd_zcam_table_high_reg[] = + { + {"cnt_dtb_rd_zcam_table_high", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_cnt_dtb_rd_zcam_table_low_reg[] = + { + {"cnt_dtb_rd_zcam_table_low", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_cnt_dtb_rd_etcam_table_high_reg[] = + { + {"cnt_dtb_rd_etcam_table_high", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_cnt_dtb_rd_etcam_table_low_reg[] = + { + {"cnt_dtb_rd_etcam_table_low", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_info_wr_ctrl_state_reg[] = + { + {"info_wr_ctrl_state", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_info_rd_table_state_reg[] = + { + {"info_rd_table_state", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_info_rd_pd_state_reg[] = + { + {"info_rd_pd_state", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_info_dump_cmd_state_reg[] = + { + {"info_dump_cmd_state", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_info_wr_ddr_state_reg[] = + { + {"info_wr_ddr_state", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_cfg_cfg_dtb_debug_info_clr_reg[] = + { + {"cfg_dtb_debug_info_clr", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_ddos_cfg_ddos_stat_dump_thrd_0_15_reg[] = + { + {"cfg_ddos_stat_dump_thrd", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_ddos_cfg_ddos_stat_dump_thrd_comp_en_reg[] = + { + {"cfg_ddos_stat_dump_thrd_comp_en", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_ddos_cfg_ddos_dump_stat_num_reg[] = + { + {"cfg_ddos_dump_stat_num", DPP_FIELD_FLAG_RW, 23, 24, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_ddos_cfg_ddos_even_hash_table_baddr_reg[] = + { + {"cfg_ddos_even_hash_table_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_ddos_cfg_ddos_odd_hash_table_baddr_reg[] = + { + {"cfg_ddos_odd_hash_table_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_ddos_cfg_ddos_stat_index_offset_reg[] = + { + {"cfg_ddos_stat_index_offset", DPP_FIELD_FLAG_RW, 18, 19, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_ddos_cfg_ddos_ns_flag_cnt_reg[] = + { + {"cfg_ddos_ns_flag_cnt", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_ddos_cfg_ddos_even_stat_table_baddr_reg[] = + { + {"cfg_ddos_even_stat_table_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_ddos_cfg_ddos_odd_stat_table_baddr_reg[] = + { + {"cfg_ddos_odd_stat_table_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_ddos_cfg_ddos_even_stat_dump_daddr_h_reg[] = + { + {"cfg_ddos_even_stat_dump_daddr_h", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_ddos_cfg_ddos_even_stat_dump_daddr_l_reg[] = + { + {"cfg_ddos_even_stat_dump_daddr_l", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_ddos_cfg_ddos_odd_stat_dump_daddr_h_reg[] = + { + {"cfg_ddos_odd_stat_dump_daddr_h", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_ddos_cfg_ddos_odd_stat_dump_daddr_l_reg[] = + { + {"cfg_ddos_odd_stat_dump_daddr_l", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_ddos_cfg_ddos_work_mode_enable_reg[] = + { + {"cfg_ddos_mode_work_enable", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_ddos_cfg_ddos_stat_table_len_reg[] = + { + {"cfg_ddos_stat_table_len", DPP_FIELD_FLAG_RW, 29, 30, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_ddos_cfg_ddos_hash_table_len_reg[] = + { + {"cfg_ddos_hash_table_len", DPP_FIELD_FLAG_RW, 29, 30, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_ram_traf_ctrl_ram0_0_255_reg[] = + { + {"traf_ctrl_ram0_0_255", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_ram_traf_ctrl_ram1_0_255_reg[] = + { + {"traf_ctrl_ram1_0_255", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_ram_traf_ctrl_ram2_0_255_reg[] = + { + {"traf_ctrl_ram2_0_255", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_ram_traf_ctrl_ram3_0_255_reg[] = + { + {"traf_ctrl_ram3_0_255", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_ram_traf_ctrl_ram4_0_255_reg[] = + { + {"traf_ctrl_ram4_0_255", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_ram_traf_ctrl_ram5_0_63_reg[] = + { + {"traf_ctrl_ram5_0_63", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_ram_dump_pd_ram_0_2047_reg[] = + { + {"dump_pd_ram_0_2047", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_ram_rd_ctrl_ram_0_4095_reg[] = + { + {"rd_ctrl_ram_0_4095", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_ram_rd_table_ram_0_8191_reg[] = + { + {"rd_table_ram_0_8191", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_dtb_dtb_ram_dtb_cmd_man_ram_0_16383_reg[] = + { + {"dtb_cmd_man_ram_0_16383", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpg_ms_st_reg[] = + { + {"cpu_trpgrx_ms_st", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpg_ms_ind_reg[] = + { + {"cpu_trpgrx_ms_ind", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpg_ms_slave_ind_reg[] = + { + {"cpu_trpgrx_ms_slave_ind", DPP_FIELD_FLAG_RW, 3, 4, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_up_water_level_reg[] = + { + {"cpu_trpgrx_up_water_level", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_low_water_level_reg[] = + { + {"cpu_trpgrx_low_water_level", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpg_ms_st_reg[] = + { + {"cpu_trpgtx_ms_st", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpg_ms_ind_reg[] = + { + {"cpu_trpgtx_ms_ind", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpg_ms_slave_ind_reg[] = + { + {"cpu_trpgtx_ms_slave_ind", DPP_FIELD_FLAG_RW, 3, 4, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_tx_glb_cpu_todtime_update_int_event_reg[] = + { + {"cpu_todtime_update_int_event", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_tx_glb_cpu_todtime_update_int_test_reg[] = + { + {"cpu_todtime_update_int_test", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_tx_glb_cpu_todtime_update_int_addr_reg[] = + { + {"cpu_todtime_update_int_addr", DPP_FIELD_FLAG_RO, 10, 11, 0x0, 0x0}, + }; +DPP_FIELD_T g_trpg_trpg_tx_todtime_ram_trpg_tx_todtime_ram_reg[] = + { + {"trpg_tx_todtime_ram", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_test_reg_reg[] = + { + {"cfg_tsn_test_reg", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_port_qbv_enable_reg[] = + { + {"cfg_tsn_port_qbv_enable", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_phy_port_sel_reg[] = + { + {"cfg_tsn_phy_port_sel", DPP_FIELD_FLAG_RW, 3, 4, 0xf, 0x0}, + }; +DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_port_time_sel_reg[] = + { + {"cfg_tsn_port_time_sel", DPP_FIELD_FLAG_RW, 1, 2, 0x0, 0x0}, + }; +DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_clk_freq_reg[] = + { + {"en", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, + {"cfg_tsn_clk_freq", DPP_FIELD_FLAG_RW, 30, 31, 0x64, 0x0}, + }; +DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_read_ram_n_reg[] = + { + {"cfg_tsn_data", DPP_FIELD_FLAG_RO, 15, 8, 0x0, 0x0}, + {"cfg_tsn_read_status", DPP_FIELD_FLAG_RO, 5, 4, 0x0, 0x0}, + {"cfg_tsn_read_ram_n", DPP_FIELD_FLAG_RO, 1, 2, 0x0, 0x0}, + }; +DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_exe_time_reg[] = + { + {"cfg_tsn_exe_time", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_port_itr_shift_reg[] = + { + {"cfg_tsn_port_itr_shift", DPP_FIELD_FLAG_RW, 3, 4, 0x0, 0x0}, + }; +DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_port_base_time_h_reg[] = + { + {"cfg_tsn_port_base_time_h", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_port_base_time_l_reg[] = + { + {"cfg_tsn_port_base_time_l", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_port_cycle_time_h_reg[] = + { + {"cfg_tsn_port_cycle_time_h", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0}, + }; +DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_port_cycle_time_l_reg[] = + { + {"cfg_tsn_port_cycle_time_l", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0}, + }; +DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_port_guard_band_time_reg[] = + { + {"cfg_tsn_port_guard_band_time", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_port_default_gate_en_reg[] = + { + {"cfg_tsn_port_default_gate_en", DPP_FIELD_FLAG_RW, 7, 8, 0xff, 0x0}, + }; +DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_port_change_gate_en_reg[] = + { + {"cfg_tsn_port_change_gate_en", DPP_FIELD_FLAG_RW, 7, 8, 0xff, 0x0}, + }; +DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_port_init_finish_reg[] = + { + {"cfg_tsn_port_init_finish", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_port_change_en_reg[] = + { + {"cfg_tsn_port_change_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_port_gcl_num0_reg[] = + { + {"cfg_tsn_port_gcl_num0", DPP_FIELD_FLAG_RW, 8, 9, 0x0, 0x0}, + }; +DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_port_gcl_num1_reg[] = + { + {"cfg_tsn_port_gcl_num1", DPP_FIELD_FLAG_RW, 8, 9, 0x0, 0x0}, + }; +DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_port_gcl_value0_reg[] = + { + {"cfg_tsn_port_gcl_gate_control0", DPP_FIELD_FLAG_RW, 31, 8, 0x0, 0x0}, + {"cfg_tsn_port_gcl_interval_time0", DPP_FIELD_FLAG_RW, 23, 24, 0x0, 0x0}, + }; +DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_port_gcl_value1_reg[] = + { + {"cfg_tsn_port_gcl_gate_control1", DPP_FIELD_FLAG_RW, 31, 8, 0x0, 0x0}, + {"cfg_tsn_port_gcl_interval_time1", DPP_FIELD_FLAG_RW, 23, 24, 0x0, 0x0}, + }; +DPP_FIELD_T g_axi_axi_conv_cfg_epid_v_func_num_reg[] = + { + {"user_en", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, + {"cfg_epid", DPP_FIELD_FLAG_RW, 27, 4, 0x0, 0x0}, + {"cfg_vfunc_num", DPP_FIELD_FLAG_RW, 23, 8, 0x0, 0x0}, + {"cfg_func_num", DPP_FIELD_FLAG_RW, 7, 3, 0x0, 0x0}, + {"cfg_vfunc_active", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_axi_axi_conv_info_axim_rw_hsk_cnt_reg[] = + { + {"axim_rd_handshake_cnt", DPP_FIELD_FLAG_RO, 24, 9, 0x0, 0x0}, + {"axim_wr_handshake_cnt", DPP_FIELD_FLAG_RO, 8, 9, 0x0, 0x0}, + }; +DPP_FIELD_T g_axi_axi_conv_info_axim_last_wr_id_reg[] = + { + {"axim_rd_id", DPP_FIELD_FLAG_RO, 24, 9, 0x0, 0x0}, + {"axim_wr_id", DPP_FIELD_FLAG_RO, 8, 9, 0x0, 0x0}, + }; +DPP_FIELD_T g_axi_axi_conv_info_axim_last_wr_addr_h_reg[] = + { + {"aximlastwraddrhigh", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_axi_axi_conv_info_axim_last_wr_addr_l_reg[] = + { + {"aximlastrdaddrlow", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_axi_axi_conv_cfg_debug_info_clr_en_reg[] = + { + {"cfg_global_clr_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptp_top_pp1s_interrupt_reg[] = + { + {"int_state", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0}, + {"int_test", DPP_FIELD_FLAG_RW, 2, 1, 0x0, 0x0}, + {"int_clr", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0}, + {"int_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptp_top_pp1s_external_select_reg[] = + { + {"pp1s_external_select", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptp_top_pp1s_out_select_reg[] = + { + {"pp1s_out_sel", DPP_FIELD_FLAG_RW, 1, 2, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptp_top_test_pp1s_select_reg[] = + { + {"test_pp1s_sel", DPP_FIELD_FLAG_RW, 2, 3, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptp_top_local_pp1s_en_reg[] = + { + {"local_pp1s_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptp_top_local_pp1s_adjust_reg[] = + { + {"local_pp1s_adjust_sel", DPP_FIELD_FLAG_RW, 2, 2, 0x0, 0x0}, + {"local_pp1s_adjust_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptp_top_local_pp1s_adjust_value_reg[] = + { + {"local_pp1s_adjust_value", DPP_FIELD_FLAG_RW, 29, 30, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptp_top_pp1s_to_np_select_reg[] = + { + {"pp1s_to_np_sel", DPP_FIELD_FLAG_RW, 1, 2, 0x3, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptp_top_pd_u1_sel_reg[] = + { + {"pd_u1_sel1", DPP_FIELD_FLAG_RW, 5, 3, 0x0, 0x0}, + {"pd_u1_sel0", DPP_FIELD_FLAG_RW, 2, 3, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptp_top_pd_u1_pd0_shift_reg[] = + { + {"pd_u1_pd0_shift", DPP_FIELD_FLAG_RW, 29, 30, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptp_top_pd_u1_pd1_shift_reg[] = + { + {"pd_u1_pd1_shift", DPP_FIELD_FLAG_RW, 29, 30, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptp_top_pd_u1_result_reg[] = + { + {"pd_u1_result_sign", DPP_FIELD_FLAG_RO, 30, 1, 0x0, 0x0}, + {"pd_u1_overflow", DPP_FIELD_FLAG_RO, 29, 1, 0x0, 0x0}, + {"pd_u1_result", DPP_FIELD_FLAG_RO, 28, 29, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptp_top_pd_u2_sel_reg[] = + { + {"pd_u2_sel1", DPP_FIELD_FLAG_RW, 5, 3, 0x0, 0x0}, + {"pd_u2_sel0", DPP_FIELD_FLAG_RW, 2, 3, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptp_top_pd_u2_pd0_shift_reg[] = + { + {"pd_u2_pd0_shift", DPP_FIELD_FLAG_RW, 29, 30, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptp_top_pd_u2_pd1_shift_reg[] = + { + {"pd_u2_pd1_shift", DPP_FIELD_FLAG_RW, 29, 30, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptp_top_pd_u2_result_reg[] = + { + {"pd_u2_result_sign", DPP_FIELD_FLAG_RO, 30, 1, 0x0, 0x0}, + {"pd_u2_overflow", DPP_FIELD_FLAG_RO, 29, 1, 0x0, 0x0}, + {"pd_u2_result", DPP_FIELD_FLAG_RO, 28, 29, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptp_top_tsn_group_nanosecond_delay0_reg[] = + { + {"tsn_group_nanosecond_delay0", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptp_top_tsn_group_fracnanosecond_delay0_reg[] = + { + {"tsn_group_fracnanosecond_delay0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptp_top_tsn_group_nanosecond_delay1_reg[] = + { + {"tsn_group_nanosecond_delay1", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptp_top_tsn_group_fracnanosecond_delay1_reg[] = + { + {"tsn_group_fracnanosecond_delay1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptp_top_tsn_group_nanosecond_delay2_reg[] = + { + {"tsn_group_nanosecond_delay2", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptp_top_tsn_group_fracnanosecond_delay2_reg[] = + { + {"tsn_group_fracnanosecond_delay2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptp_top_tsn_group_nanosecond_delay3_reg[] = + { + {"tsn_group_nanosecond_delay3", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptp_top_tsn_group_fracnanosecond_delay3_reg[] = + { + {"tsn_group_fracnanosecond_delay3", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptp_top_tsn_ptp1588_rdma_nanosecond_delay_reg[] = + { + {"ptp1588_rdma_nanosecond_delay", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptp_top_ptp1588_rdma_fracnanosecond_delay_reg[] = + { + {"ptp1588_rdma_fracnanosecond_delay", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptp_top_ptp1588_np_nanosecond_delay_reg[] = + { + {"ptp1588_np_nanosecond_delay", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptp_top_ptp1588_np_fracnanosecond_delay_reg[] = + { + {"ptp1588_np_fracnanosecond_delay", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptp_top_time_sync_period_reg[] = + { + {"time_sync_period", DPP_FIELD_FLAG_RW, 2, 3, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_module_id_reg[] = + { + {"module_id", DPP_FIELD_FLAG_RO, 15, 16, 0x89, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_module_version_reg[] = + { + {"module_major_version", DPP_FIELD_FLAG_RO, 15, 8, 0x3, 0x0}, + {"module_minor_version", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_module_date_reg[] = + { + {"year", DPP_FIELD_FLAG_RO, 31, 16, 0x2017, 0x0}, + {"month", DPP_FIELD_FLAG_RO, 15, 8, 0x1, 0x0}, + {"date", DPP_FIELD_FLAG_RO, 7, 8, 0x1, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_interrupt_status_reg[] = + { + {"pps_in_status", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0}, + {"fifo_almost_full_status", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0}, + {"fifo_no_empty_status", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0}, + {"trigger_output_status", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0}, + {"trigger_input_status", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_interrupt_event_reg[] = + { + {"pps_in_event", DPP_FIELD_FLAG_RW, 4, 1, 0x0, 0x0}, + {"fifo_almost_full_event", DPP_FIELD_FLAG_RW, 3, 1, 0x0, 0x0}, + {"fifo_no_empty_event", DPP_FIELD_FLAG_RW, 2, 1, 0x0, 0x0}, + {"trigger_output_event", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0}, + {"trigger_input_event", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_interrupt_mask_reg[] = + { + {"pps_in_event_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x0, 0x0}, + {"fifo_almost_full_event_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x0, 0x0}, + {"fifo_no_empty_event_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x0, 0x0}, + {"trigger_output_event_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0}, + {"trigger_input_eventt_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_interrupt_test_reg[] = + { + {"trigger_pps_in_event_test", DPP_FIELD_FLAG_RW, 4, 1, 0x0, 0x0}, + {"trigger_fifo_almost_full_event_test", DPP_FIELD_FLAG_RW, 3, 1, 0x0, 0x0}, + {"trigger_fifo_no_empty_event_test", DPP_FIELD_FLAG_RW, 2, 1, 0x0, 0x0}, + {"trigger_output_event_test", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0}, + {"trigger_input_event_test", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_hw_clock_cycle_integer_reg[] = + { + {"integeral_nanosecond_of_hw_clock_cycle", DPP_FIELD_FLAG_RW, 7, 8, 0x1, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_hw_clock_cycle_fraction_reg[] = + { + {"fractional_nanosecond_of_hw_clock_cycle", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_ptp_clock_cycle_integer_reg[] = + { + {"integeral_nanosecond_of_ptp_clock_cycle", DPP_FIELD_FLAG_RW, 7, 8, 0x1, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_ptp_clock_cycle_fraction_reg[] = + { + {"fractional_nanosecond_of_ptp_clock_cycle", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_ptp_configuration_reg[] = + { + {"trig_oe", DPP_FIELD_FLAG_RW, 18, 1, 0x0, 0x0}, + {"hw_time_update_en", DPP_FIELD_FLAG_RW, 17, 1, 0x0, 0x0}, + {"ptp1588_tod_time_update_en", DPP_FIELD_FLAG_RW, 16, 1, 0x0, 0x0}, + {"timer_enable", DPP_FIELD_FLAG_RW, 15, 1, 0x0, 0x0}, + {"pps_output_enable", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0}, + {"pp1_output_enable", DPP_FIELD_FLAG_RW, 13, 1, 0x0, 0x0}, + {"pp2_output_enable", DPP_FIELD_FLAG_RW, 12, 1, 0x0, 0x0}, + {"enable_writing_timestamps_to_the_fifo", DPP_FIELD_FLAG_RW, 11, 1, 0x0, 0x0}, + {"l2s_time_output_select", DPP_FIELD_FLAG_RW, 10, 1, 0x0, 0x0}, + {"reserved_9", DPP_FIELD_FLAG_RO, 9, 1, 0x0, 0x0}, + {"pps_input_select", DPP_FIELD_FLAG_RW, 8, 1, 0x0, 0x0}, + {"pp_output_select", DPP_FIELD_FLAG_RW, 7, 1, 0x0, 0x0}, + {"reserved_6", DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0}, + {"timer_run_mode", DPP_FIELD_FLAG_RW, 5, 2, 0x0, 0x0}, + {"update_command_select", DPP_FIELD_FLAG_RW, 3, 1, 0x0, 0x0}, + {"trigger_out_enable", DPP_FIELD_FLAG_RW, 2, 1, 0x0, 0x0}, + {"trigger_in_enable", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0}, + {"timer_capture_slave_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_timer_control_reg[] = + { + {"ptpmoutputsynchroningstate", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0}, + {"ptp1588_fifo_read_command", DPP_FIELD_FLAG_RW, 2, 1, 0x0, 0x0}, + {"adjust_the_timer", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_pps_income_delay_reg[] = + { + {"pps_income_delay_nanosecond", DPP_FIELD_FLAG_RW, 31, 16, 0x0, 0x0}, + {"pps_income_delay_frac_nanosecond", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_clock_cycle_update_reg[] = + { + {"tsn3_clock_cycle_update_enable", DPP_FIELD_FLAG_RW, 4, 1, 0x0, 0x0}, + {"tsn2_clock_cycle_update_enable", DPP_FIELD_FLAG_RW, 3, 1, 0x0, 0x0}, + {"tsn1_clock_cycle_update_enable", DPP_FIELD_FLAG_RW, 2, 1, 0x0, 0x0}, + {"tsn0_clock_cycle_update_enable", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0}, + {"ptp1588_clock_cycle_update_enable", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_cycle_time_of_output_period_pulse_1_reg[] = + { + {"clock_number_of_output_period_pulse_1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_cycle_time_of_output_period_pulse_2_reg[] = + { + {"clock_number_of_output_period_pulse_2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_timer_latch_en_reg[] = + { + {"latch_the_timer_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_timer_latch_sel_reg[] = + { + {"timer_latch_sel", DPP_FIELD_FLAG_RW, 5, 6, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_trigger_in_tod_nanosecond_reg[] = + { + {"trigger_in_tod_nanosecond", DPP_FIELD_FLAG_RO, 29, 30, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_trigger_in_lower_tod_second_reg[] = + { + {"trigger_in_lower_tod_second", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_trigger_in_high_tod_second_reg[] = + { + {"trigger_in_high_tod_second", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_trigger_in_fracnanosecond_reg[] = + { + {"trigger_in_fracnanosecond", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_trigger_in_hardware_time_low_reg[] = + { + {"trigger_in_hardware_time_low", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_trigger_in_hardware_time_high_reg[] = + { + {"trigger_in_hardware_time_high", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_trigger_out_tod_nanosecond_reg[] = + { + {"trigger_out_tod_nanosecond", DPP_FIELD_FLAG_RW, 29, 30, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_trigger_out_lower_tod_second_reg[] = + { + {"trigger_out_lower_tod_second", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_trigger_out_high_tod_second_reg[] = + { + {"trigger_out_high_tod_second", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_trigger_out_hardware_time_low_reg[] = + { + {"trigger_out_hardware_time_low", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_trigger_out_hardware_time_high_reg[] = + { + {"trigger_out_hardware_time_high", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_adjust_tod_nanosecond_reg[] = + { + {"adjust_tod_nanosecond", DPP_FIELD_FLAG_RW, 29, 30, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_adjust_lower_tod_second_reg[] = + { + {"adjust_lower_tod_second", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_adjust_high_tod_second_reg[] = + { + {"adjust_high_tod_second", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_adjust_fracnanosecond_reg[] = + { + {"adjust_fracnanosecond", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_adjust_hardware_time_low_reg[] = + { + {"adjust_hardware_time_low", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_adjust_hardware_time_high_reg[] = + { + {"adjust_hardware_time_high", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_latch_tod_nanosecond_reg[] = + { + {"latch_tod_nanosecond", DPP_FIELD_FLAG_RO, 29, 30, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_latch_lower_tod_second_reg[] = + { + {"latch_lower_tod_second", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_latch_high_tod_second_reg[] = + { + {"latch_high_tod_second", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_latch_fracnanosecond_reg[] = + { + {"latch_fracnanosecond", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_latch_hardware_time_low_reg[] = + { + {"latch_hardware_time_low", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_latch_hardware_time_high_reg[] = + { + {"latch_hardware_time_high", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_real_tod_nanosecond_reg[] = + { + {"real_tod_nanosecond", DPP_FIELD_FLAG_RO, 29, 30, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_real_lower_tod_second_reg[] = + { + {"real_lower_tod_second", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_real_high_tod_second_reg[] = + { + {"real_high_tod_second", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_real_hardware_time_low_reg[] = + { + {"real_hardware_time_low", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_real_hardware_time_high_reg[] = + { + {"real_hardware_time_high", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_ptp1588_event_message_port_reg[] = + { + {"ptp1588_event_message_port", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_ptp1588_event_message_timestamp_low_reg[] = + { + {"ptp1588_event_message_timestamp_low", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_ptp1588_event_message_timestamp_high_reg[] = + { + {"ptp1588_event_message_timestamp_high", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_ptp1588_event_message_fifo_status_reg[] = + { + {"fifo_full", DPP_FIELD_FLAG_RO, 9, 1, 0x0, 0x0}, + {"fifo_empty", DPP_FIELD_FLAG_RO, 8, 1, 0x1, 0x0}, + {"timestamps_count", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_pp1s_latch_tod_nanosecond_reg[] = + { + {"latch_1588tod_nanosecond", DPP_FIELD_FLAG_RO, 29, 30, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_pp1s_latch_lower_tod_second_reg[] = + { + {"latch_lower_1588tod_second", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_pp1s_latch_high_tod_second_reg[] = + { + {"latch_high_1588tod_second", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_pp1s_latch_fracnanosecond_reg[] = + { + {"latch_1588fracnanosecond", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_tsn_time_configuration_reg[] = + { + {"tsn_pps_enable", DPP_FIELD_FLAG_RW, 19, 4, 0x0, 0x0}, + {"tsn_timer_enable", DPP_FIELD_FLAG_RW, 15, 4, 0x0, 0x0}, + {"tsn_timer_run_mode", DPP_FIELD_FLAG_RW, 11, 8, 0x0, 0x0}, + {"timer_capture_slave_mode", DPP_FIELD_FLAG_RW, 3, 4, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_tsn_timer_control_reg[] = + { + {"adjust_the_tsn3_timer", DPP_FIELD_FLAG_RW, 3, 1, 0x0, 0x0}, + {"adjust_the_tsn2_timer", DPP_FIELD_FLAG_RW, 2, 1, 0x0, 0x0}, + {"adjust_the_tsn1_timer", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0}, + {"adjust_the_tsn0_timer", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_tsn0_clock_cycle_integer_reg[] = + { + {"integeral_nanosecond_of_tsn0_clock_cycle", DPP_FIELD_FLAG_RW, 7, 8, 0x1, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_tsn0_clock_cycle_fraction_reg[] = + { + {"fractional_nanosecond_of_tsn0_clock_cycle", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_tsn1_clock_cycle_integer_reg[] = + { + {"integeral_nanosecond_of_tsn1_clock_cycle", DPP_FIELD_FLAG_RW, 7, 8, 0x1, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_tsn1_clock_cycle_fraction_reg[] = + { + {"fractional_nanosecond_of_tsn1_clock_cycle", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_tsn2_clock_cycle_integer_reg[] = + { + {"integeral_nanosecond_of_tsn2_clock_cycle", DPP_FIELD_FLAG_RW, 7, 8, 0x1, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_tsn2_clock_cycle_fraction_reg[] = + { + {"fractional_nanosecond_of_tsn2_clock_cycle", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_tsn3_clock_cycle_integer_reg[] = + { + {"integeral_nanosecond_of_tsn3_clock_cycle", DPP_FIELD_FLAG_RW, 7, 8, 0x1, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_tsn3_clock_cycle_fraction_reg[] = + { + {"fractional_nanosecond_of_tsn3_clock_cycle", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_tsn0_adjust_tod_nanosecond_reg[] = + { + {"tsn0_adjust_tod_nanosecond", DPP_FIELD_FLAG_RW, 29, 30, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_tsn0_adjust_lower_tod_second_reg[] = + { + {"tsn0_adjust_lower_tod_second", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_tsn0_adjust_high_tod_second_reg[] = + { + {"tsn0_adjust_high_tod_second", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_tsn0_adjust_fracnanosecond_reg[] = + { + {"tsn0_adjust_fracnanosecond", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_tsn1_adjust_tod_nanosecond_reg[] = + { + {"tsn1_adjust_tod_nanosecond", DPP_FIELD_FLAG_RW, 29, 30, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_tsn1_adjust_lower_tod_second_reg[] = + { + {"tsn1_adjust_lower_tod_second", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_tsn1_adjust_high_tod_second_reg[] = + { + {"tsn1_adjust_high_tod_second", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_tsn1_adjust_fracnanosecond_reg[] = + { + {"tsn1_adjust_fracnanosecond", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_tsn2_adjust_tod_nanosecond_reg[] = + { + {"tsn2_adjust_tod_nanosecond", DPP_FIELD_FLAG_RW, 29, 30, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_tsn2_adjust_lower_tod_second_reg[] = + { + {"tsn2_adjust_lower_tod_second", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_tsn2_adjust_high_tod_second_reg[] = + { + {"tsn2_adjust_high_tod_second", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_tsn2_adjust_fracnanosecond_reg[] = + { + {"tsn2_adjust_fracnanosecond", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_tsn3_adjust_tod_nanosecond_reg[] = + { + {"tsn3_adjust_tod_nanosecond", DPP_FIELD_FLAG_RW, 29, 30, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_tsn3_adjust_lower_tod_second_reg[] = + { + {"tsn3_adjust_lower_tod_second", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_tsn3_adjust_high_tod_second_reg[] = + { + {"tsn3_adjust_high_tod_second", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_tsn3_adjust_fracnanosecond_reg[] = + { + {"tsn3_adjust_fracnanosecond", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_tsn0_latch_tod_nanosecond_reg[] = + { + {"tsn0_latch_tod_nanosecond", DPP_FIELD_FLAG_RO, 29, 30, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_tsn0_latch_lower_tod_second_reg[] = + { + {"tsn0_latch_lower_tod_second", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_tsn0_latch_high_tod_second_reg[] = + { + {"tsn0_latch_high_tod_second", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_tsn0_latch_fracnanosecond_reg[] = + { + {"tsn0_latch_fracnanosecond", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_tsn1_latch_tod_nanosecond_reg[] = + { + {"tsn1_latch_tod_nanosecond", DPP_FIELD_FLAG_RO, 29, 30, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_tsn1_latch_lower_tod_second_reg[] = + { + {"tsn1_latch_lower_tod_second", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_tsn1_latch_high_tod_second_reg[] = + { + {"tsn1_latch_high_tod_second", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_tsn1_latch_fracnanosecond_reg[] = + { + {"tsn1_latch_fracnanosecond", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_tsn2_latch_tod_nanosecond_reg[] = + { + {"tsn2_latch_tod_nanosecond", DPP_FIELD_FLAG_RO, 29, 30, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_tsn2_latch_lower_tod_second_reg[] = + { + {"tsn2_latch_lower_tod_second", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_tsn2_latch_high_tod_second_reg[] = + { + {"tsn2_latch_high_tod_second", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_tsn2_latch_fracnanosecond_reg[] = + { + {"tsn2_latch_fracnanosecond", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_tsn3_latch_tod_nanosecond_reg[] = + { + {"tsn3_latch_tod_nanosecond", DPP_FIELD_FLAG_RO, 29, 30, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_tsn3_latch_lower_tod_second_reg[] = + { + {"tsn3_latch_lower_tod_second", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_tsn3_latch_high_tod_second_reg[] = + { + {"tsn3_latch_high_tod_second", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_tsn3_latch_fracnanosecond_reg[] = + { + {"tsn3_latch_fracnanosecond", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_pp1s_latch_tsn0_tod_nanosecond_reg[] = + { + {"latch_tsn0_tod_nanosecond", DPP_FIELD_FLAG_RO, 29, 30, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_pp1s_latch_tsn0_lower_tod_second_reg[] = + { + {"latch_lower_tsn0_tod_second", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_pp1s_latch_tsn0_high_tod_second_reg[] = + { + {"latch_high_tsn0_tod_second", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_pp1s_latch_tsn0_fracnanosecond_reg[] = + { + {"latch_tsn0_fracnanosecond", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_pp1s_latch_tsn1_tod_nanosecond_reg[] = + { + {"latch_tsn1_tod_nanosecond", DPP_FIELD_FLAG_RO, 29, 30, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_pp1s_latch_tsn1_lower_tod_second_reg[] = + { + {"latch_lower_tsn1_tod_second", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_pp1s_latch_tsn1_high_tod_second_reg[] = + { + {"latch_high_tsn1_tod_second", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_pp1s_latch_tsn1_fracnanosecond_reg[] = + { + {"latch_tsn1_fracnanosecond", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_pp1s_latch_tsn2_tod_nanosecond_reg[] = + { + {"latch_tsn2_tod_nanosecond", DPP_FIELD_FLAG_RO, 29, 30, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_pp1s_latch_tsn2_lower_tod_second_reg[] = + { + {"latch_lower_tsn2_tod_second", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_pp1s_latch_tsn2_high_tod_second_reg[] = + { + {"latch_high_tsn2_tod_second", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_pp1s_latch_tsn2_fracnanosecond_reg[] = + { + {"latch_tsn2_fracnanosecond", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_pp1s_latch_tsn3_tod_nanosecond_reg[] = + { + {"latch_tsn3_tod_nanosecond", DPP_FIELD_FLAG_RO, 29, 30, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_pp1s_latch_tsn3_lower_tod_second_reg[] = + { + {"latch_lower_tsn3_tod_second", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_pp1s_latch_tsn3_high_tod_second_reg[] = + { + {"latch_high_tsn3_tod_second", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_pp1s_latch_tsn3_fracnanosecond_reg[] = + { + {"latch_tsn3_fracnanosecond", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_tsn0_real_tod_nanosecond_reg[] = + { + {"tsn0_real_tod_nanosecond", DPP_FIELD_FLAG_RO, 29, 30, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_tsn0_real_lower_tod_second_reg[] = + { + {"tsn0_real_lower_tod_second", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_tsn0_real_high_tod_second_reg[] = + { + {"tsn0_real_high_tod_second", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_tsn1_real_tod_nanosecond_reg[] = + { + {"tsn1_real_tod_nanosecond", DPP_FIELD_FLAG_RO, 29, 30, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_tsn1_real_lower_tod_second_reg[] = + { + {"tsn1_real_lower_tod_second", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_tsn1_real_high_tod_second_reg[] = + { + {"tsn1_real_high_tod_second", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_tsn2_real_tod_nanosecond_reg[] = + { + {"tsn2_real_tod_nanosecond", DPP_FIELD_FLAG_RO, 29, 30, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_tsn2_real_lower_tod_second_reg[] = + { + {"tsn2_real_lower_tod_second", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_tsn2_real_high_tod_second_reg[] = + { + {"tsn2_real_high_tod_second", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_tsn3_real_tod_nanosecond_reg[] = + { + {"tsn3_real_tod_nanosecond", DPP_FIELD_FLAG_RO, 29, 30, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_tsn3_real_lower_tod_second_reg[] = + { + {"tsn3_real_lower_tod_second", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_tsn3_real_high_tod_second_reg[] = + { + {"tsn3_real_high_tod_second", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_real_ptp_clock_cycle_integer_reg[] = + { + {"integeral_nanosecond_of_real_ptp_clock_cycle", DPP_FIELD_FLAG_RO, 7, 8, 0x1, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_real_ptp_clock_cycle_fraction_reg[] = + { + {"fractional_nanosecond_of_real_ptp_clock_cycle", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_real_tsn0_clock_cycle_integer_reg[] = + { + {"integeral_nanosecond_of_real_tsn0_clock_cycle", DPP_FIELD_FLAG_RO, 7, 8, 0x1, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_real_tsn0_clock_cycle_fraction_reg[] = + { + {"fractional_nanosecond_of_real_tsn0_clock_cycle", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_real_tsn1_clock_cycle_integer_reg[] = + { + {"integeral_nanosecond_of_real_tsn1_clock_cycle", DPP_FIELD_FLAG_RO, 7, 8, 0x1, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_real_tsn1_clock_cycle_fraction_reg[] = + { + {"fractional_nanosecond_of_real_tsn1_clock_cycle", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_real_tsn2_clock_cycle_integer_reg[] = + { + {"integeral_nanosecond_of_real_tsn2_clock_cycle", DPP_FIELD_FLAG_RO, 7, 8, 0x1, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_real_tsn2_clock_cycle_fraction_reg[] = + { + {"fractional_nanosecond_of_real_tsn2_clock_cycle", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_real_tsn3_clock_cycle_integer_reg[] = + { + {"integeral_nanosecond_of_real_tsn3_clock_cycle", DPP_FIELD_FLAG_RO, 7, 8, 0x1, 0x0}, + }; +DPP_FIELD_T g_ptptm_ptptm_real_tsn3_clock_cycle_fraction_reg[] = + { + {"fractional_nanosecond_of_real_tsn3_clock_cycle", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, + }; +DPP_REG_T g_dpp_reg_info[] = +{ + { + "cpu_check_reg", + ETM_CFGMT_CPU_CHECK_REGr, + ETM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + 0x60, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cfgmt_cpu_check_reg_reg, + NULL, + NULL, + }, + { + "cfgmt_blksize", + ETM_CFGMT_CFGMT_BLKSIZEr, + ETM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + 0x70, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cfgmt_cfgmt_blksize_reg, + NULL, + NULL, + }, + { + "reg_int_state_reg", + ETM_CFGMT_REG_INT_STATE_REGr, + ETM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + 0x90, + (32/8), + 0, + 0, + 0, + 0, + 7, + g_etm_cfgmt_reg_int_state_reg_reg, + NULL, + NULL, + }, + { + "reg_int_mask_reg", + ETM_CFGMT_REG_INT_MASK_REGr, + ETM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + 0xa0, + (32/8), + 0, + 0, + 0, + 0, + 7, + g_etm_cfgmt_reg_int_mask_reg_reg, + NULL, + NULL, + }, + { + "timeout_limit", + ETM_CFGMT_TIMEOUT_LIMITr, + ETM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + 0xb0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cfgmt_timeout_limit_reg, + NULL, + NULL, + }, + { + "subsystem_rdy_reg", + ETM_CFGMT_SUBSYSTEM_RDY_REGr, + ETM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + 0xc0, + (32/8), + 0, + 0, + 0, + 0, + 6, + g_etm_cfgmt_subsystem_rdy_reg_reg, + NULL, + NULL, + }, + { + "subsystem_en_reg", + ETM_CFGMT_SUBSYSTEM_EN_REGr, + ETM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + 0xd0, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_etm_cfgmt_subsystem_en_reg_reg, + NULL, + NULL, + }, + { + "cfgmt_int_reg", + ETM_CFGMT_CFGMT_INT_REGr, + ETM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + 0xe0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cfgmt_cfgmt_int_reg_reg, + NULL, + NULL, + }, + { + "qmu_work_mode", + ETM_CFGMT_QMU_WORK_MODEr, + ETM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + 0x100, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cfgmt_qmu_work_mode_reg, + NULL, + NULL, + }, + { + "cfgmt_ddr_attach", + ETM_CFGMT_CFGMT_DDR_ATTACHr, + ETM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + 0x120, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cfgmt_cfgmt_ddr_attach_reg, + NULL, + NULL, + }, + { + "cnt_mode_reg", + ETM_CFGMT_CNT_MODE_REGr, + ETM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + 0x140, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_etm_cfgmt_cnt_mode_reg_reg, + NULL, + NULL, + }, + { + "clkgate_en", + ETM_CFGMT_CLKGATE_ENr, + ETM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + 0x1c0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cfgmt_clkgate_en_reg, + NULL, + NULL, + }, + { + "softrst_en", + ETM_CFGMT_SOFTRST_ENr, + ETM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + 0x1d0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cfgmt_softrst_en_reg, + NULL, + NULL, + }, + { + "imem_prog_full", + ETM_OLIF_IMEM_PROG_FULLr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_etm_olif_imem_prog_full_reg, + NULL, + NULL, + }, + { + "qmu_para_prog_full", + ETM_OLIF_QMU_PARA_PROG_FULLr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x4, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_etm_olif_qmu_para_prog_full_reg, + NULL, + NULL, + }, + { + "olif_int_mask", + ETM_OLIF_OLIF_INT_MASKr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x8, + (32/8), + 0, + 0, + 0, + 0, + 19, + g_etm_olif_olif_int_mask_reg, + NULL, + NULL, + }, + { + "itmhram_parity_err_2_int", + ETM_OLIF_ITMHRAM_PARITY_ERR_2_INTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x9, + (32/8), + 0, + 0, + 0, + 0, + 22, + g_etm_olif_itmhram_parity_err_2_int_reg, + NULL, + NULL, + }, + { + "lif0_port_rdy_mask_h", + ETM_OLIF_LIF0_PORT_RDY_MASK_Hr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x30, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_olif_lif0_port_rdy_mask_h_reg, + NULL, + NULL, + }, + { + "lif0_port_rdy_mask_l", + ETM_OLIF_LIF0_PORT_RDY_MASK_Lr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x31, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_olif_lif0_port_rdy_mask_l_reg, + NULL, + NULL, + }, + { + "lif0_port_rdy_cfg_h", + ETM_OLIF_LIF0_PORT_RDY_CFG_Hr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x32, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_olif_lif0_port_rdy_cfg_h_reg, + NULL, + NULL, + }, + { + "lif0_port_rdy_cfg_l", + ETM_OLIF_LIF0_PORT_RDY_CFG_Lr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x33, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_olif_lif0_port_rdy_cfg_l_reg, + NULL, + NULL, + }, + { + "lif0_link_rdy_mask_cfg", + ETM_OLIF_LIF0_LINK_RDY_MASK_CFGr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x34, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_etm_olif_lif0_link_rdy_mask_cfg_reg, + NULL, + NULL, + }, + { + "tm_lif_stat_cfg", + ETM_OLIF_TM_LIF_STAT_CFGr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x40, + (32/8), + 0, + 0xf + 1, + 0, + 0x1, + 4, + g_etm_olif_tm_lif_stat_cfg_reg, + NULL, + NULL, + }, + { + "tm_lif_sop_stat", + ETM_OLIF_TM_LIF_SOP_STATr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x50, + (32/8), + 0, + 0xf + 1, + 0, + 0x1, + 1, + g_etm_olif_tm_lif_sop_stat_reg, + NULL, + NULL, + }, + { + "tm_lif_eop_stat", + ETM_OLIF_TM_LIF_EOP_STATr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x60, + (32/8), + 0, + 0xf + 1, + 0, + 0x1, + 1, + g_etm_olif_tm_lif_eop_stat_reg, + NULL, + NULL, + }, + { + "tm_lif_vld_stat", + ETM_OLIF_TM_LIF_VLD_STATr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x80, + (32/8), + 0, + 0xf + 1, + 0, + 0x1, + 1, + g_etm_olif_tm_lif_vld_stat_reg, + NULL, + NULL, + }, + { + "prog_full_assert_cfg", + ETM_CGAVD_PROG_FULL_ASSERT_CFGr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x1, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_etm_cgavd_prog_full_assert_cfg_reg, + NULL, + NULL, + }, + { + "cgavd_int", + ETM_CGAVD_CGAVD_INTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_cgavd_int_reg, + NULL, + NULL, + }, + { + "cgavd_ram_err", + ETM_CGAVD_CGAVD_RAM_ERRr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x3, + (32/8), + 0, + 0, + 0, + 0, + 13, + g_etm_cgavd_cgavd_ram_err_reg, + NULL, + NULL, + }, + { + "cgavd_int_mask", + ETM_CGAVD_CGAVD_INT_MASKr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_cgavd_int_mask_reg, + NULL, + NULL, + }, + { + "cgavd_ram_err_int_mask", + ETM_CGAVD_CGAVD_RAM_ERR_INT_MASKr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x5, + (32/8), + 0, + 0, + 0, + 0, + 13, + g_etm_cgavd_cgavd_ram_err_int_mask_reg, + NULL, + NULL, + }, + { + "cfgmt_byte_mode", + ETM_CGAVD_CFGMT_BYTE_MODEr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x6, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_cfgmt_byte_mode_reg, + NULL, + NULL, + }, + { + "avg_qlen_return_zero_en", + ETM_CGAVD_AVG_QLEN_RETURN_ZERO_ENr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x7, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_avg_qlen_return_zero_en_reg, + NULL, + NULL, + }, + { + "flow_wred_q_len_th", + ETM_CGAVD_FLOW_WRED_Q_LEN_THr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x20, + (32/8), + 0, + 0x1f + 1, + 0, + 0x1, + 1, + g_etm_cgavd_flow_wred_q_len_th_reg, + NULL, + NULL, + }, + { + "flow_wq", + ETM_CGAVD_FLOW_WQr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x40, + (32/8), + 0, + 0x1f + 1, + 0, + 0x1, + 1, + g_etm_cgavd_flow_wq_reg, + NULL, + NULL, + }, + { + "flow_wred_max_th", + ETM_CGAVD_FLOW_WRED_MAX_THr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x100, + (32/8), + 0, + 0xff + 1, + 0, + 0x1, + 1, + g_etm_cgavd_flow_wred_max_th_reg, + NULL, + NULL, + }, + { + "flow_wred_min_th", + ETM_CGAVD_FLOW_WRED_MIN_THr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x200, + (32/8), + 0, + 0xff + 1, + 0, + 0x1, + 1, + g_etm_cgavd_flow_wred_min_th_reg, + NULL, + NULL, + }, + { + "flow_wred_cfg_para", + ETM_CGAVD_FLOW_WRED_CFG_PARAr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x300, + (32/8), + 0, + 0xff + 1, + 0, + 0x1, + 1, + g_etm_cgavd_flow_wred_cfg_para_reg, + NULL, + NULL, + }, + { + "pp_avg_q_len", + ETM_CGAVD_PP_AVG_Q_LENr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x400, + (32/8), + 0, + 0x7f + 1, + 0, + 0x1, + 1, + g_etm_cgavd_pp_avg_q_len_reg, + NULL, + NULL, + }, + { + "pp_td_th", + ETM_CGAVD_PP_TD_THr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x600, + (32/8), + 0, + 0x7f + 1, + 0, + 0x1, + 1, + g_etm_cgavd_pp_td_th_reg, + NULL, + NULL, + }, + { + "pp_ca_mtd", + ETM_CGAVD_PP_CA_MTDr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x800, + (32/8), + 0, + 0x7f + 1, + 0, + 0x1, + 1, + g_etm_cgavd_pp_ca_mtd_reg, + NULL, + NULL, + }, + { + "pp_wred_grp_th_en", + ETM_CGAVD_PP_WRED_GRP_TH_ENr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0xc00, + (32/8), + 0, + 0x7f + 1, + 0, + 0x1, + 2, + g_etm_cgavd_pp_wred_grp_th_en_reg, + NULL, + NULL, + }, + { + "pp_wred_q_len_th", + ETM_CGAVD_PP_WRED_Q_LEN_THr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0xe00, + (32/8), + 0, + 0x7 + 1, + 0, + 0x1, + 1, + g_etm_cgavd_pp_wred_q_len_th_reg, + NULL, + NULL, + }, + { + "pp_wq", + ETM_CGAVD_PP_WQr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0xe08, + (32/8), + 0, + 0x7 + 1, + 0, + 0x1, + 1, + g_etm_cgavd_pp_wq_reg, + NULL, + NULL, + }, + { + "pp_wred_max_th", + ETM_CGAVD_PP_WRED_MAX_THr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x1000, + (32/8), + 0, + 0x3f + 1, + 0, + 0x1, + 1, + g_etm_cgavd_pp_wred_max_th_reg, + NULL, + NULL, + }, + { + "pp_wred_min_th", + ETM_CGAVD_PP_WRED_MIN_THr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x1080, + (32/8), + 0, + 0x3f + 1, + 0, + 0x1, + 1, + g_etm_cgavd_pp_wred_min_th_reg, + NULL, + NULL, + }, + { + "pp_cfg_para", + ETM_CGAVD_PP_CFG_PARAr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x1100, + (32/8), + 0, + 0x3f + 1, + 0, + 0x1, + 1, + g_etm_cgavd_pp_cfg_para_reg, + NULL, + NULL, + }, + { + "sys_avg_q_len", + ETM_CGAVD_SYS_AVG_Q_LENr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x1200, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_sys_avg_q_len_reg, + NULL, + NULL, + }, + { + "sys_td_th", + ETM_CGAVD_SYS_TD_THr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x1202, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_sys_td_th_reg, + NULL, + NULL, + }, + { + "sys_cgavd_metd", + ETM_CGAVD_SYS_CGAVD_METDr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x1204, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_sys_cgavd_metd_reg, + NULL, + NULL, + }, + { + "sys_cfg_q_grp_para", + ETM_CGAVD_SYS_CFG_Q_GRP_PARAr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x1208, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_sys_cfg_q_grp_para_reg, + NULL, + NULL, + }, + { + "sys_wq", + ETM_CGAVD_SYS_WQr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x1210, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_sys_wq_reg, + NULL, + NULL, + }, + { + "gred_max_th", + ETM_CGAVD_GRED_MAX_THr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x1218, + (32/8), + 0, + 0x7 + 1, + 0, + 0x1, + 1, + g_etm_cgavd_gred_max_th_reg, + NULL, + NULL, + }, + { + "gred_mid_th", + ETM_CGAVD_GRED_MID_THr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x1228, + (32/8), + 0, + 0x7 + 1, + 0, + 0x1, + 1, + g_etm_cgavd_gred_mid_th_reg, + NULL, + NULL, + }, + { + "gred_min_th", + ETM_CGAVD_GRED_MIN_THr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x1238, + (32/8), + 0, + 0x7 + 1, + 0, + 0x1, + 1, + g_etm_cgavd_gred_min_th_reg, + NULL, + NULL, + }, + { + "gred_cfg_para0", + ETM_CGAVD_GRED_CFG_PARA0r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x1248, + (32/8), + 0, + 0x7 + 1, + 0, + 0x1, + 1, + g_etm_cgavd_gred_cfg_para0_reg, + NULL, + NULL, + }, + { + "gred_cfg_para1", + ETM_CGAVD_GRED_CFG_PARA1r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x1258, + (32/8), + 0, + 0x7 + 1, + 0, + 0x1, + 1, + g_etm_cgavd_gred_cfg_para1_reg, + NULL, + NULL, + }, + { + "gred_cfg_para2", + ETM_CGAVD_GRED_CFG_PARA2r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x1268, + (32/8), + 0, + 0x7 + 1, + 0, + 0x1, + 1, + g_etm_cgavd_gred_cfg_para2_reg, + NULL, + NULL, + }, + { + "sys_window_th_h", + ETM_CGAVD_SYS_WINDOW_TH_Hr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x1278, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_sys_window_th_h_reg, + NULL, + NULL, + }, + { + "sys_window_th_l", + ETM_CGAVD_SYS_WINDOW_TH_Lr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x127a, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_sys_window_th_l_reg, + NULL, + NULL, + }, + { + "amplify_gene0", + ETM_CGAVD_AMPLIFY_GENE0r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x127c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_amplify_gene0_reg, + NULL, + NULL, + }, + { + "amplify_gene1", + ETM_CGAVD_AMPLIFY_GENE1r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x127d, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_amplify_gene1_reg, + NULL, + NULL, + }, + { + "amplify_gene2", + ETM_CGAVD_AMPLIFY_GENE2r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x127e, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_amplify_gene2_reg, + NULL, + NULL, + }, + { + "amplify_gene3", + ETM_CGAVD_AMPLIFY_GENE3r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x127f, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_amplify_gene3_reg, + NULL, + NULL, + }, + { + "amplify_gene4", + ETM_CGAVD_AMPLIFY_GENE4r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x1280, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_amplify_gene4_reg, + NULL, + NULL, + }, + { + "amplify_gene5", + ETM_CGAVD_AMPLIFY_GENE5r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x1281, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_amplify_gene5_reg, + NULL, + NULL, + }, + { + "amplify_gene6", + ETM_CGAVD_AMPLIFY_GENE6r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x1282, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_amplify_gene6_reg, + NULL, + NULL, + }, + { + "amplify_gene7", + ETM_CGAVD_AMPLIFY_GENE7r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x1283, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_amplify_gene7_reg, + NULL, + NULL, + }, + { + "amplify_gene8", + ETM_CGAVD_AMPLIFY_GENE8r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x1284, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_amplify_gene8_reg, + NULL, + NULL, + }, + { + "amplify_gene9", + ETM_CGAVD_AMPLIFY_GENE9r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x1285, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_amplify_gene9_reg, + NULL, + NULL, + }, + { + "amplify_gene10", + ETM_CGAVD_AMPLIFY_GENE10r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x1286, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_amplify_gene10_reg, + NULL, + NULL, + }, + { + "amplify_gene11", + ETM_CGAVD_AMPLIFY_GENE11r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x1287, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_amplify_gene11_reg, + NULL, + NULL, + }, + { + "amplify_gene12", + ETM_CGAVD_AMPLIFY_GENE12r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x1288, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_amplify_gene12_reg, + NULL, + NULL, + }, + { + "amplify_gene13", + ETM_CGAVD_AMPLIFY_GENE13r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x1289, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_amplify_gene13_reg, + NULL, + NULL, + }, + { + "amplify_gene14", + ETM_CGAVD_AMPLIFY_GENE14r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x128a, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_amplify_gene14_reg, + NULL, + NULL, + }, + { + "amplify_gene15", + ETM_CGAVD_AMPLIFY_GENE15r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x128b, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_amplify_gene15_reg, + NULL, + NULL, + }, + { + "equal_pkt_len_en", + ETM_CGAVD_EQUAL_PKT_LEN_ENr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x128c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_equal_pkt_len_en_reg, + NULL, + NULL, + }, + { + "equal_pkt_len_th0", + ETM_CGAVD_EQUAL_PKT_LEN_TH0r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x128d, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_equal_pkt_len_th0_reg, + NULL, + NULL, + }, + { + "equal_pkt_len_th1", + ETM_CGAVD_EQUAL_PKT_LEN_TH1r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x128e, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_equal_pkt_len_th1_reg, + NULL, + NULL, + }, + { + "equal_pkt_len_th2", + ETM_CGAVD_EQUAL_PKT_LEN_TH2r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x128f, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_equal_pkt_len_th2_reg, + NULL, + NULL, + }, + { + "equal_pkt_len_th3", + ETM_CGAVD_EQUAL_PKT_LEN_TH3r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x1290, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_equal_pkt_len_th3_reg, + NULL, + NULL, + }, + { + "equal_pkt_len_th4", + ETM_CGAVD_EQUAL_PKT_LEN_TH4r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x1291, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_equal_pkt_len_th4_reg, + NULL, + NULL, + }, + { + "equal_pkt_len_th5", + ETM_CGAVD_EQUAL_PKT_LEN_TH5r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x1292, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_equal_pkt_len_th5_reg, + NULL, + NULL, + }, + { + "equal_pkt_len_th6", + ETM_CGAVD_EQUAL_PKT_LEN_TH6r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x1293, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_equal_pkt_len_th6_reg, + NULL, + NULL, + }, + { + "equal_pkt_len0", + ETM_CGAVD_EQUAL_PKT_LEN0r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x1294, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_equal_pkt_len0_reg, + NULL, + NULL, + }, + { + "equal_pkt_len1", + ETM_CGAVD_EQUAL_PKT_LEN1r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x1295, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_equal_pkt_len1_reg, + NULL, + NULL, + }, + { + "equal_pkt_len2", + ETM_CGAVD_EQUAL_PKT_LEN2r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x1296, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_equal_pkt_len2_reg, + NULL, + NULL, + }, + { + "equal_pkt_len3", + ETM_CGAVD_EQUAL_PKT_LEN3r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x1297, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_equal_pkt_len3_reg, + NULL, + NULL, + }, + { + "equal_pkt_len4", + ETM_CGAVD_EQUAL_PKT_LEN4r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x1298, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_equal_pkt_len4_reg, + NULL, + NULL, + }, + { + "equal_pkt_len5", + ETM_CGAVD_EQUAL_PKT_LEN5r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x1299, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_equal_pkt_len5_reg, + NULL, + NULL, + }, + { + "equal_pkt_len6", + ETM_CGAVD_EQUAL_PKT_LEN6r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x129a, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_equal_pkt_len6_reg, + NULL, + NULL, + }, + { + "equal_pkt_len7", + ETM_CGAVD_EQUAL_PKT_LEN7r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x129b, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_equal_pkt_len7_reg, + NULL, + NULL, + }, + { + "flow_cpu_set_avg_len", + ETM_CGAVD_FLOW_CPU_SET_AVG_LENr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x129c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_flow_cpu_set_avg_len_reg, + NULL, + NULL, + }, + { + "flow_cpu_set_q_len", + ETM_CGAVD_FLOW_CPU_SET_Q_LENr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x129d, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_flow_cpu_set_q_len_reg, + NULL, + NULL, + }, + { + "pp_cpu_set_avg_q_len", + ETM_CGAVD_PP_CPU_SET_AVG_Q_LENr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x12ef, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_pp_cpu_set_avg_q_len_reg, + NULL, + NULL, + }, + { + "pp_cpu_set_q_len", + ETM_CGAVD_PP_CPU_SET_Q_LENr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x129e, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_pp_cpu_set_q_len_reg, + NULL, + NULL, + }, + { + "sys_cpu_set_avg_len", + ETM_CGAVD_SYS_CPU_SET_AVG_LENr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x12a0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_sys_cpu_set_avg_len_reg, + NULL, + NULL, + }, + { + "sys_cpu_set_q_len", + ETM_CGAVD_SYS_CPU_SET_Q_LENr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x12a2, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_sys_cpu_set_q_len_reg, + NULL, + NULL, + }, + { + "pke_len_calc_sign", + ETM_CGAVD_PKE_LEN_CALC_SIGNr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x12a3, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_pke_len_calc_sign_reg, + NULL, + NULL, + }, + { + "rd_cpu_or_ram", + ETM_CGAVD_RD_CPU_OR_RAMr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x12a4, + (32/8), + 0, + 0, + 0, + 0, + 6, + g_etm_cgavd_rd_cpu_or_ram_reg, + NULL, + NULL, + }, + { + "q_len_update_disable", + ETM_CGAVD_Q_LEN_UPDATE_DISABLEr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x12a5, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_etm_cgavd_q_len_update_disable_reg, + NULL, + NULL, + }, + { + "cgavd_dp_sel", + ETM_CGAVD_CGAVD_DP_SELr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x12ad, + (32/8), + 0, + 0, + 0, + 0, + 9, + g_etm_cgavd_cgavd_dp_sel_reg, + NULL, + NULL, + }, + { + "cgavd_sub_en", + ETM_CGAVD_CGAVD_SUB_ENr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x12e6, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_etm_cgavd_cgavd_sub_en_reg, + NULL, + NULL, + }, + { + "default_start_queue", + ETM_CGAVD_DEFAULT_START_QUEUEr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x12e7, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_default_start_queue_reg, + NULL, + NULL, + }, + { + "default_finish_queue", + ETM_CGAVD_DEFAULT_FINISH_QUEUEr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x12e8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_default_finish_queue_reg, + NULL, + NULL, + }, + { + "protocol_start_queue", + ETM_CGAVD_PROTOCOL_START_QUEUEr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x12e9, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_protocol_start_queue_reg, + NULL, + NULL, + }, + { + "protocol_finish_queue", + ETM_CGAVD_PROTOCOL_FINISH_QUEUEr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x12ea, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_protocol_finish_queue_reg, + NULL, + NULL, + }, + { + "uniform_td_th", + ETM_CGAVD_UNIFORM_TD_THr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x12eb, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_uniform_td_th_reg, + NULL, + NULL, + }, + { + "uniform_td_th_en", + ETM_CGAVD_UNIFORM_TD_TH_ENr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x12ec, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_uniform_td_th_en_reg, + NULL, + NULL, + }, + { + "cgavd_cfg_fc", + ETM_CGAVD_CGAVD_CFG_FCr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x12ed, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_cgavd_cfg_fc_reg, + NULL, + NULL, + }, + { + "cgavd_cfg_no_fc", + ETM_CGAVD_CGAVD_CFG_NO_FCr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x12ee, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_cgavd_cfg_no_fc_reg, + NULL, + NULL, + }, + { + "cgavd_force_imem_omem", + ETM_CGAVD_CGAVD_FORCE_IMEM_OMEMr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x12f0, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_etm_cgavd_cgavd_force_imem_omem_reg, + NULL, + NULL, + }, + { + "cgavd_sys_q_len_l", + ETM_CGAVD_CGAVD_SYS_Q_LEN_Lr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x12f1, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_cgavd_sys_q_len_l_reg, + NULL, + NULL, + }, + { + "default_queue_en", + ETM_CGAVD_DEFAULT_QUEUE_ENr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x12f5, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_default_queue_en_reg, + NULL, + NULL, + }, + { + "protocol_queue_en", + ETM_CGAVD_PROTOCOL_QUEUE_ENr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x12f6, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_protocol_queue_en_reg, + NULL, + NULL, + }, + { + "cfg_tc_flowid_dat", + ETM_CGAVD_CFG_TC_FLOWID_DATr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x1400, + (32/8), + 0, + 0x7 + 1, + 0, + 0x1, + 1, + g_etm_cgavd_cfg_tc_flowid_dat_reg, + NULL, + NULL, + }, + { + "flow_td_th", + ETM_CGAVD_FLOW_TD_THr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x40000, + (32/8), + 0, + 0x23FF + 1, + 0, + 0x1, + 1, + g_etm_cgavd_flow_td_th_reg, + NULL, + NULL, + }, + { + "flow_ca_mtd", + ETM_CGAVD_FLOW_CA_MTDr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x80000, + (32/8), + 0, + 0x23FF + 1, + 0, + 0x1, + 1, + g_etm_cgavd_flow_ca_mtd_reg, + NULL, + NULL, + }, + { + "flow_dynamic_th_en", + ETM_CGAVD_FLOW_DYNAMIC_TH_ENr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0xc0000, + (32/8), + 0, + 0x23FF + 1, + 0, + 0x1, + 1, + g_etm_cgavd_flow_dynamic_th_en_reg, + NULL, + NULL, + }, + { + "pp_num", + ETM_CGAVD_PP_NUMr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x100000, + (32/8), + 0, + 0x23FF + 1, + 0, + 0x1, + 1, + g_etm_cgavd_pp_num_reg, + NULL, + NULL, + }, + { + "flow_q_len", + ETM_CGAVD_FLOW_Q_LENr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x140000, + (32/8), + 0, + 0x23FF + 1, + 0, + 0x1, + 1, + g_etm_cgavd_flow_q_len_reg, + NULL, + NULL, + }, + { + "flow_wred_grp", + ETM_CGAVD_FLOW_WRED_GRPr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x180000, + (32/8), + 0, + 0x23FF + 1, + 0, + 0x1, + 1, + g_etm_cgavd_flow_wred_grp_reg, + NULL, + NULL, + }, + { + "flow_avg_q_len", + ETM_CGAVD_FLOW_AVG_Q_LENr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x1c0000, + (32/8), + 0, + 0x23FF + 1, + 0, + 0x1, + 1, + g_etm_cgavd_flow_avg_q_len_reg, + NULL, + NULL, + }, + { + "qos_sign", + ETM_CGAVD_QOS_SIGNr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x200000, + (32/8), + 0, + 0x23FF + 1, + 0, + 0x1, + 1, + g_etm_cgavd_qos_sign_reg, + NULL, + NULL, + }, + { + "q_pri", + ETM_CGAVD_Q_PRIr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x240000, + (32/8), + 0, + 0x23FF + 1, + 0, + 0x1, + 1, + g_etm_cgavd_q_pri_reg, + NULL, + NULL, + }, + { + "odma_tm_itmd_rd_low", + ETM_CGAVD_ODMA_TM_ITMD_RD_LOWr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x250000, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_odma_tm_itmd_rd_low_reg, + NULL, + NULL, + }, + { + "odma_tm_itmd_rd_mid", + ETM_CGAVD_ODMA_TM_ITMD_RD_MIDr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x250001, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_odma_tm_itmd_rd_mid_reg, + NULL, + NULL, + }, + { + "odma_tm_itmd_rd_high", + ETM_CGAVD_ODMA_TM_ITMD_RD_HIGHr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x250002, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_odma_tm_itmd_rd_high_reg, + NULL, + NULL, + }, + { + "cgavd_stat_pkt_len", + ETM_CGAVD_CGAVD_STAT_PKT_LENr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x250003, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_etm_cgavd_cgavd_stat_pkt_len_reg, + NULL, + NULL, + }, + { + "cgavd_stat_qnum", + ETM_CGAVD_CGAVD_STAT_QNUMr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x250004, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_etm_cgavd_cgavd_stat_qnum_reg, + NULL, + NULL, + }, + { + "cgavd_stat_dp", + ETM_CGAVD_CGAVD_STAT_DPr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x250005, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_cgavd_stat_dp_reg, + NULL, + NULL, + }, + { + "flow_num0", + ETM_CGAVD_FLOW_NUM0r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x260000, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_flow_num0_reg, + NULL, + NULL, + }, + { + "flow_num1", + ETM_CGAVD_FLOW_NUM1r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x260001, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_flow_num1_reg, + NULL, + NULL, + }, + { + "flow_num2", + ETM_CGAVD_FLOW_NUM2r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x260002, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_flow_num2_reg, + NULL, + NULL, + }, + { + "flow_num3", + ETM_CGAVD_FLOW_NUM3r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x260003, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_flow_num3_reg, + NULL, + NULL, + }, + { + "flow_num4", + ETM_CGAVD_FLOW_NUM4r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x260004, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_flow_num4_reg, + NULL, + NULL, + }, + { + "flow0_imem_cnt", + ETM_CGAVD_FLOW0_IMEM_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x260010, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_flow0_imem_cnt_reg, + NULL, + NULL, + }, + { + "flow1_imem_cnt", + ETM_CGAVD_FLOW1_IMEM_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x260011, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_flow1_imem_cnt_reg, + NULL, + NULL, + }, + { + "flow2_imem_cnt", + ETM_CGAVD_FLOW2_IMEM_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x260012, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_flow2_imem_cnt_reg, + NULL, + NULL, + }, + { + "flow3_imem_cnt", + ETM_CGAVD_FLOW3_IMEM_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x260013, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_flow3_imem_cnt_reg, + NULL, + NULL, + }, + { + "flow4_imem_cnt", + ETM_CGAVD_FLOW4_IMEM_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x260014, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_flow4_imem_cnt_reg, + NULL, + NULL, + }, + { + "flow0_drop_cnt", + ETM_CGAVD_FLOW0_DROP_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x260030, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_flow0_drop_cnt_reg, + NULL, + NULL, + }, + { + "flow1_drop_cnt", + ETM_CGAVD_FLOW1_DROP_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x260031, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_flow1_drop_cnt_reg, + NULL, + NULL, + }, + { + "flow2_drop_cnt", + ETM_CGAVD_FLOW2_DROP_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x260032, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_flow2_drop_cnt_reg, + NULL, + NULL, + }, + { + "flow3_drop_cnt", + ETM_CGAVD_FLOW3_DROP_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x260033, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_flow3_drop_cnt_reg, + NULL, + NULL, + }, + { + "flow4_drop_cnt", + ETM_CGAVD_FLOW4_DROP_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x260034, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_flow4_drop_cnt_reg, + NULL, + NULL, + }, + { + "fc_count_mode", + ETM_CGAVD_FC_COUNT_MODEr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x264000, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_fc_count_mode_reg, + NULL, + NULL, + }, + { + "qmu_cgavd_fc_num", + ETM_CGAVD_QMU_CGAVD_FC_NUMr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x264100, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_etm_cgavd_qmu_cgavd_fc_num_reg, + NULL, + NULL, + }, + { + "cgavd_odma_fc_num", + ETM_CGAVD_CGAVD_ODMA_FC_NUMr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x264101, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_etm_cgavd_cgavd_odma_fc_num_reg, + NULL, + NULL, + }, + { + "cfg_offset", + ETM_CGAVD_CFG_OFFSETr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x290000, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_cfg_offset_reg, + NULL, + NULL, + }, + { + "tmmu_init_done", + ETM_TMMU_TMMU_INIT_DONEr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0001, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_tmmu_init_done_reg, + NULL, + NULL, + }, + { + "tmmu_int_mask_1", + ETM_TMMU_TMMU_INT_MASK_1r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x002, + (32/8), + 0, + 0, + 0, + 0, + 27, + g_etm_tmmu_tmmu_int_mask_1_reg, + NULL, + NULL, + }, + { + "tmmu_int_mask_2", + ETM_TMMU_TMMU_INT_MASK_2r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0003, + (32/8), + 0, + 0, + 0, + 0, + 17, + g_etm_tmmu_tmmu_int_mask_2_reg, + NULL, + NULL, + }, + { + "cfgmt_tm_pure_imem_en", + ETM_TMMU_CFGMT_TM_PURE_IMEM_ENr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0004, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_cfgmt_tm_pure_imem_en_reg, + NULL, + NULL, + }, + { + "cfgmt_force_ddr_rdy_cfg", + ETM_TMMU_CFGMT_FORCE_DDR_RDY_CFGr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0005, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_cfgmt_force_ddr_rdy_cfg_reg, + NULL, + NULL, + }, + { + "pd_order_fifo_aful_th", + ETM_TMMU_PD_ORDER_FIFO_AFUL_THr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0007, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_pd_order_fifo_aful_th_reg, + NULL, + NULL, + }, + { + "cached_pd_fifo_aful_th", + ETM_TMMU_CACHED_PD_FIFO_AFUL_THr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0008, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_cached_pd_fifo_aful_th_reg, + NULL, + NULL, + }, + { + "wr_cmd_fifo_aful_th", + ETM_TMMU_WR_CMD_FIFO_AFUL_THr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x000b, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_wr_cmd_fifo_aful_th_reg, + NULL, + NULL, + }, + { + "imem_enq_rd_fifo_aful_th", + ETM_TMMU_IMEM_ENQ_RD_FIFO_AFUL_THr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x000c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_imem_enq_rd_fifo_aful_th_reg, + NULL, + NULL, + }, + { + "imem_enq_drop_fifo_aful_th", + ETM_TMMU_IMEM_ENQ_DROP_FIFO_AFUL_THr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x000d, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_imem_enq_drop_fifo_aful_th_reg, + NULL, + NULL, + }, + { + "imem_deq_drop_fifo_aful_th", + ETM_TMMU_IMEM_DEQ_DROP_FIFO_AFUL_THr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x000e, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_imem_deq_drop_fifo_aful_th_reg, + NULL, + NULL, + }, + { + "imem_deq_rd_fifo_aful_th", + ETM_TMMU_IMEM_DEQ_RD_FIFO_AFUL_THr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x000f, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_imem_deq_rd_fifo_aful_th_reg, + NULL, + NULL, + }, + { + "tmmu_states_1", + ETM_TMMU_TMMU_STATES_1r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0011, + (32/8), + 0, + 0, + 0, + 0, + 27, + g_etm_tmmu_tmmu_states_1_reg, + NULL, + NULL, + }, + { + "tmmu_states_2", + ETM_TMMU_TMMU_STATES_2r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0012, + (32/8), + 0, + 0, + 0, + 0, + 17, + g_etm_tmmu_tmmu_states_2_reg, + NULL, + NULL, + }, + { + "shap_ind_cmd", + ETM_SHAP_SHAP_IND_CMDr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x000a, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_etm_shap_shap_ind_cmd_reg, + NULL, + NULL, + }, + { + "shap_ind_sta", + ETM_SHAP_SHAP_IND_STAr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x000b, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_shap_shap_ind_sta_reg, + NULL, + NULL, + }, + { + "shap_ind_data0", + ETM_SHAP_SHAP_IND_DATA0r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x000c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_shap_shap_ind_data0_reg, + NULL, + NULL, + }, + { + "shap_ind_data1", + ETM_SHAP_SHAP_IND_DATA1r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x000d, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_shap_shap_ind_data1_reg, + NULL, + NULL, + }, + { + "full_threshold", + ETM_SHAP_FULL_THRESHOLDr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x1c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_shap_full_threshold_reg, + NULL, + NULL, + }, + { + "empty_threshold", + ETM_SHAP_EMPTY_THRESHOLDr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x1d, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_shap_empty_threshold_reg, + NULL, + NULL, + }, + { + "shap_sta_init_cfg", + ETM_SHAP_SHAP_STA_INIT_CFGr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x1e, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_etm_shap_shap_sta_init_cfg_reg, + NULL, + NULL, + }, + { + "shap_cfg_init_cfg", + ETM_SHAP_SHAP_CFG_INIT_CFGr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x1f, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_etm_shap_shap_cfg_init_cfg_reg, + NULL, + NULL, + }, + { + "token_mode_switch", + ETM_SHAP_TOKEN_MODE_SWITCHr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_shap_token_mode_switch_reg, + NULL, + NULL, + }, + { + "token_grain", + ETM_SHAP_TOKEN_GRAINr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x21, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_shap_token_grain_reg, + NULL, + NULL, + }, + { + "crd_grain", + ETM_SHAP_CRD_GRAINr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x22, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_shap_crd_grain_reg, + NULL, + NULL, + }, + { + "shap_stat_ctrl", + ETM_SHAP_SHAP_STAT_CTRLr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x37, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_shap_shap_stat_ctrl_reg, + NULL, + NULL, + }, + { + "token_stat_id", + ETM_SHAP_TOKEN_STAT_IDr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x38, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_shap_token_stat_id_reg, + NULL, + NULL, + }, + { + "token_stat", + ETM_SHAP_TOKEN_STATr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x39, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_shap_token_stat_reg, + NULL, + NULL, + }, + { + "shap_stat_clk_cnt", + ETM_SHAP_SHAP_STAT_CLK_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x74, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_shap_shap_stat_clk_cnt_reg, + NULL, + NULL, + }, + { + "shap_bucket_map_tbl", + ETM_SHAP_SHAP_BUCKET_MAP_TBLr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x80000000 + 0x000000, + (64/8), + 0, + 0xABFF + 1, + 0, + 1, + 1, + g_etm_shap_shap_bucket_map_tbl_reg, + NULL, + NULL, + }, + { + "bkt_para_tbl", + ETM_SHAP_BKT_PARA_TBLr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x80000000 + 0x100000, + (64/8), + 0, + 0xAFF + 1, + 0, + 1, + 2, + g_etm_shap_bkt_para_tbl_reg, + NULL, + NULL, + }, + { + "credit_en", + ETM_CRDT_CREDIT_ENr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0001, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_credit_en_reg, + NULL, + NULL, + }, + { + "crt_inter1", + ETM_CRDT_CRT_INTER1r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0002, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_crt_inter1_reg, + NULL, + NULL, + }, + { + "db_token", + ETM_CRDT_DB_TOKENr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0003, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_db_token_reg, + NULL, + NULL, + }, + { + "crs_flt_cfg", + ETM_CRDT_CRS_FLT_CFGr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0004, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_crs_flt_cfg_reg, + NULL, + NULL, + }, + { + "th_sp", + ETM_CRDT_TH_SPr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0005, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_th_sp_reg, + NULL, + NULL, + }, + { + "th_wfq_fq", + ETM_CRDT_TH_WFQ_FQr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0006, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_etm_crdt_th_wfq_fq_reg, + NULL, + NULL, + }, + { + "th_wfq2_fq2", + ETM_CRDT_TH_WFQ2_FQ2r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0007, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_etm_crdt_th_wfq2_fq2_reg, + NULL, + NULL, + }, + { + "th_wfq4_fq4", + ETM_CRDT_TH_WFQ4_FQ4r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0008, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_etm_crdt_th_wfq4_fq4_reg, + NULL, + NULL, + }, + { + "cfg_state", + ETM_CRDT_CFG_STATEr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0009, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_cfg_state_reg, + NULL, + NULL, + }, + { + "crdt_ind_cmd", + ETM_CRDT_CRDT_IND_CMDr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x000a, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_etm_crdt_crdt_ind_cmd_reg, + NULL, + NULL, + }, + { + "crdt_ind_sta", + ETM_CRDT_CRDT_IND_STAr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x000b, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_crdt_ind_sta_reg, + NULL, + NULL, + }, + { + "crdt_ind_data0", + ETM_CRDT_CRDT_IND_DATA0r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x000c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_crdt_ind_data0_reg, + NULL, + NULL, + }, + { + "crdt_ind_data1", + ETM_CRDT_CRDT_IND_DATA1r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x000d, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_crdt_ind_data1_reg, + NULL, + NULL, + }, + { + "crdt_state", + ETM_CRDT_CRDT_STATEr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x000f, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_etm_crdt_crdt_state_reg, + NULL, + NULL, + }, + { + "stat_que_id_0", + ETM_CRDT_STAT_QUE_ID_0r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x10, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_stat_que_id_0_reg, + NULL, + NULL, + }, + { + "stat_que_id_1", + ETM_CRDT_STAT_QUE_ID_1r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x11, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_stat_que_id_1_reg, + NULL, + NULL, + }, + { + "stat_que_id_2", + ETM_CRDT_STAT_QUE_ID_2r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x12, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_stat_que_id_2_reg, + NULL, + NULL, + }, + { + "stat_que_id_3", + ETM_CRDT_STAT_QUE_ID_3r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x13, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_stat_que_id_3_reg, + NULL, + NULL, + }, + { + "stat_que_id_4", + ETM_CRDT_STAT_QUE_ID_4r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x14, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_stat_que_id_4_reg, + NULL, + NULL, + }, + { + "stat_que_id_5", + ETM_CRDT_STAT_QUE_ID_5r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x15, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_stat_que_id_5_reg, + NULL, + NULL, + }, + { + "stat_que_id_6", + ETM_CRDT_STAT_QUE_ID_6r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x16, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_stat_que_id_6_reg, + NULL, + NULL, + }, + { + "stat_que_id_7", + ETM_CRDT_STAT_QUE_ID_7r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x17, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_stat_que_id_7_reg, + NULL, + NULL, + }, + { + "stat_que_id_8", + ETM_CRDT_STAT_QUE_ID_8r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x18, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_stat_que_id_8_reg, + NULL, + NULL, + }, + { + "stat_que_id_9", + ETM_CRDT_STAT_QUE_ID_9r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x19, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_stat_que_id_9_reg, + NULL, + NULL, + }, + { + "stat_que_id_10", + ETM_CRDT_STAT_QUE_ID_10r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x1a, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_stat_que_id_10_reg, + NULL, + NULL, + }, + { + "stat_que_id_11", + ETM_CRDT_STAT_QUE_ID_11r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x1b, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_stat_que_id_11_reg, + NULL, + NULL, + }, + { + "stat_que_id_12", + ETM_CRDT_STAT_QUE_ID_12r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x1c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_stat_que_id_12_reg, + NULL, + NULL, + }, + { + "stat_que_id_13", + ETM_CRDT_STAT_QUE_ID_13r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x1d, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_stat_que_id_13_reg, + NULL, + NULL, + }, + { + "stat_que_id_14", + ETM_CRDT_STAT_QUE_ID_14r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x1e, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_stat_que_id_14_reg, + NULL, + NULL, + }, + { + "stat_que_id_15", + ETM_CRDT_STAT_QUE_ID_15r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x1f, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_stat_que_id_15_reg, + NULL, + NULL, + }, + { + "stat_que_credit", + ETM_CRDT_STAT_QUE_CREDITr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x20, + (32/8), + 0, + 0x0f + 1, + 0, + 1, + 1, + g_etm_crdt_stat_que_credit_reg, + NULL, + NULL, + }, + { + "crdt_cfg_ram_init", + ETM_CRDT_CRDT_CFG_RAM_INITr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x7a, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_etm_crdt_crdt_cfg_ram_init_reg, + NULL, + NULL, + }, + { + "crdt_sta_ram_init", + ETM_CRDT_CRDT_STA_RAM_INITr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x7b, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_etm_crdt_crdt_sta_ram_init_reg, + NULL, + NULL, + }, + { + "crs_que_id", + ETM_CRDT_CRS_QUE_IDr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x86, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_crs_que_id_reg, + NULL, + NULL, + }, + { + "qmu_crs_end_state", + ETM_CRDT_QMU_CRS_END_STATEr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x87, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_qmu_crs_end_state_reg, + NULL, + NULL, + }, + { + "shap_rdy", + ETM_CRDT_SHAP_RDYr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x90, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_shap_rdy_reg, + NULL, + NULL, + }, + { + "shap_int_reg", + ETM_CRDT_SHAP_INT_REGr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x91, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_shap_int_reg_reg, + NULL, + NULL, + }, + { + "shap_int_mask_reg", + ETM_CRDT_SHAP_INT_MASK_REGr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x92, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_shap_int_mask_reg_reg, + NULL, + NULL, + }, + { + "token_state_almost_empty_th", + ETM_CRDT_TOKEN_STATE_ALMOST_EMPTY_THr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x93, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_token_state_almost_empty_th_reg, + NULL, + NULL, + }, + { + "token_state_empty_th", + ETM_CRDT_TOKEN_STATE_EMPTY_THr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x94, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_token_state_empty_th_reg, + NULL, + NULL, + }, + { + "full_th", + ETM_CRDT_FULL_THr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x95, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_full_th_reg, + NULL, + NULL, + }, + { + "pp_c_level_shap_en", + ETM_CRDT_PP_C_LEVEL_SHAP_ENr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x96, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_pp_c_level_shap_en_reg, + NULL, + NULL, + }, + { + "enq_token_th", + ETM_CRDT_ENQ_TOKEN_THr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x97, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_enq_token_th_reg, + NULL, + NULL, + }, + { + "pp_tokenq_level1_qstate_weight_cir", + ETM_CRDT_PP_TOKENQ_LEVEL1_QSTATE_WEIGHT_CIRr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x98, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_etm_crdt_pp_tokenq_level1_qstate_weight_cir_reg, + NULL, + NULL, + }, + { + "pp_idle_weight_level1_cir", + ETM_CRDT_PP_IDLE_WEIGHT_LEVEL1_CIRr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x99, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_pp_idle_weight_level1_cir_reg, + NULL, + NULL, + }, + { + "rci_grade_th_0_cfg", + ETM_CRDT_RCI_GRADE_TH_0_CFGr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0xc0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_rci_grade_th_0_cfg_reg, + NULL, + NULL, + }, + { + "rci_grade_th_1_cfg", + ETM_CRDT_RCI_GRADE_TH_1_CFGr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0xc1, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_rci_grade_th_1_cfg_reg, + NULL, + NULL, + }, + { + "rci_grade_th_2_cfg", + ETM_CRDT_RCI_GRADE_TH_2_CFGr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0xc2, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_rci_grade_th_2_cfg_reg, + NULL, + NULL, + }, + { + "rci_grade_th_3_cfg", + ETM_CRDT_RCI_GRADE_TH_3_CFGr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0xc3, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_rci_grade_th_3_cfg_reg, + NULL, + NULL, + }, + { + "rci_grade_th_4_cfg", + ETM_CRDT_RCI_GRADE_TH_4_CFGr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0xc4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_rci_grade_th_4_cfg_reg, + NULL, + NULL, + }, + { + "rci_grade_th_5_cfg", + ETM_CRDT_RCI_GRADE_TH_5_CFGr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0xc5, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_rci_grade_th_5_cfg_reg, + NULL, + NULL, + }, + { + "rci_grade_th_6_cfg", + ETM_CRDT_RCI_GRADE_TH_6_CFGr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0xc6, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_rci_grade_th_6_cfg_reg, + NULL, + NULL, + }, + { + "flow_del_cmd", + ETM_CRDT_FLOW_DEL_CMDr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x00f1, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_etm_crdt_flow_del_cmd_reg, + NULL, + NULL, + }, + { + "cnt_clr", + ETM_CRDT_CNT_CLRr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x00f2, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_cnt_clr_reg, + NULL, + NULL, + }, + { + "crdt_int_bus", + ETM_CRDT_CRDT_INT_BUSr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x00f3, + (32/8), + 0, + 0, + 0, + 0, + 19, + g_etm_crdt_crdt_int_bus_reg, + NULL, + NULL, + }, + { + "crdt_int_mask", + ETM_CRDT_CRDT_INT_MASKr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x00f8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_crdt_int_mask_reg, + NULL, + NULL, + }, + { + "cfg_weight_together", + ETM_CRDT_CFG_WEIGHT_TOGETHERr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x00f9, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_cfg_weight_together_reg, + NULL, + NULL, + }, + { + "weight", + ETM_CRDT_WEIGHTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x00fa, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_etm_crdt_weight_reg, + NULL, + NULL, + }, + { + "dev_sp_state", + ETM_CRDT_DEV_SP_STATEr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x11e, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_dev_sp_state_reg, + NULL, + NULL, + }, + { + "dev_crs", + ETM_CRDT_DEV_CRSr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x11f, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_dev_crs_reg, + NULL, + NULL, + }, + { + "congest_token_disable_31_0", + ETM_CRDT_CONGEST_TOKEN_DISABLE_31_0r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x130, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_congest_token_disable_31_0_reg, + NULL, + NULL, + }, + { + "congest_token_disable_63_32", + ETM_CRDT_CONGEST_TOKEN_DISABLE_63_32r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x131, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_congest_token_disable_63_32_reg, + NULL, + NULL, + }, + { + "crdt_interval_en_cfg", + ETM_CRDT_CRDT_INTERVAL_EN_CFGr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0139, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_crdt_interval_en_cfg_reg, + NULL, + NULL, + }, + { + "q_token_staue_cfg", + ETM_CRDT_Q_TOKEN_STAUE_CFGr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x150, + (32/8), + 0, + 0xf + 1, + 0, + 1, + 1, + g_etm_crdt_q_token_staue_cfg_reg, + NULL, + NULL, + }, + { + "q_token_dist_cnt", + ETM_CRDT_Q_TOKEN_DIST_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x160, + (32/8), + 0, + 0xf + 1, + 0, + 1, + 1, + g_etm_crdt_q_token_dist_cnt_reg, + NULL, + NULL, + }, + { + "q_token_dec_cnt", + ETM_CRDT_Q_TOKEN_DEC_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x170, + (32/8), + 0, + 0xf + 1, + 0, + 1, + 1, + g_etm_crdt_q_token_dec_cnt_reg, + NULL, + NULL, + }, + { + "pp_weight_ram", + ETM_CRDT_PP_WEIGHT_RAMr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x41000000, + (32/8), + 0, + 0x003F + 1, + 0, + 1, + 1, + g_etm_crdt_pp_weight_ram_reg, + NULL, + NULL, + }, + { + "pp_cbs_shape_en_ram", + ETM_CRDT_PP_CBS_SHAPE_EN_RAMr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x42000000, + (32/8), + 0, + 0x003f + 1, + 0, + 1, + 2, + g_etm_crdt_pp_cbs_shape_en_ram_reg, + NULL, + NULL, + }, + { + "pp_next_pc_q_state_ram", + ETM_CRDT_PP_NEXT_PC_Q_STATE_RAMr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x43000000, + (32/8), + 0, + 0x003f + 1, + 0, + 1, + 3, + g_etm_crdt_pp_next_pc_q_state_ram_reg, + NULL, + NULL, + }, + { + "dev_interval", + ETM_CRDT_DEV_INTERVALr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x50000000, + (32/8), + 0, + 0x0127 + 1, + 0, + 1, + 1, + g_etm_crdt_dev_interval_reg, + NULL, + NULL, + }, + { + "dev_wfq_cnt", + ETM_CRDT_DEV_WFQ_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x51000000, + (32/8), + 0, + 0x0007 + 1, + 0, + 1, + 1, + g_etm_crdt_dev_wfq_cnt_reg, + NULL, + NULL, + }, + { + "dev_wfq_state", + ETM_CRDT_DEV_WFQ_STATEr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x52000000, + (32/8), + 0, + 0x0007 + 1, + 0, + 1, + 1, + g_etm_crdt_dev_wfq_state_reg, + NULL, + NULL, + }, + { + "dev_active_head_ptr", + ETM_CRDT_DEV_ACTIVE_HEAD_PTRr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x53000000, + (32/8), + 0, + 0x0007 + 1, + 0, + 1, + 1, + g_etm_crdt_dev_active_head_ptr_reg, + NULL, + NULL, + }, + { + "dev_active_tail_ptr", + ETM_CRDT_DEV_ACTIVE_TAIL_PTRr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x54000000, + (32/8), + 0, + 0x0007 + 1, + 0, + 1, + 1, + g_etm_crdt_dev_active_tail_ptr_reg, + NULL, + NULL, + }, + { + "dev_unactive_head_ptr", + ETM_CRDT_DEV_UNACTIVE_HEAD_PTRr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x55000000, + (32/8), + 0, + 0x0037 + 1, + 0, + 1, + 1, + g_etm_crdt_dev_unactive_head_ptr_reg, + NULL, + NULL, + }, + { + "dev_unactive_tail_ptr", + ETM_CRDT_DEV_UNACTIVE_TAIL_PTRr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x56000000, + (32/8), + 0, + 0x0037 + 1, + 0, + 1, + 1, + g_etm_crdt_dev_unactive_tail_ptr_reg, + NULL, + NULL, + }, + { + "pp_weight", + ETM_CRDT_PP_WEIGHTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x44000000, + (32/8), + 0, + 0x003F + 1, + 0, + 1, + 1, + g_etm_crdt_pp_weight_reg, + NULL, + NULL, + }, + { + "pp_que_state", + ETM_CRDT_PP_QUE_STATEr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x46000000, + (32/8), + 0, + 0x003f + 1, + 0, + 1, + 5, + g_etm_crdt_pp_que_state_reg, + NULL, + NULL, + }, + { + "pp_next_ptr", + ETM_CRDT_PP_NEXT_PTRr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x49000000, + (32/8), + 0, + 0x003f + 1, + 0, + 1, + 1, + g_etm_crdt_pp_next_ptr_reg, + NULL, + NULL, + }, + { + "pp_cfg", + ETM_CRDT_PP_CFGr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x4a000000, + (32/8), + 0, + 0x003f + 1, + 0, + 1, + 1, + g_etm_crdt_pp_cfg_reg, + NULL, + NULL, + }, + { + "pp_up_ptr", + ETM_CRDT_PP_UP_PTRr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x4b000000, + (32/8), + 0, + 0x003f + 1, + 0, + 1, + 1, + g_etm_crdt_pp_up_ptr_reg, + NULL, + NULL, + }, + { + "credit_drop_num", + ETM_CRDT_CREDIT_DROP_NUMr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x180, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_credit_drop_num_reg, + NULL, + NULL, + }, + { + "se_id_lv0", + ETM_CRDT_SE_ID_LV0r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x181, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_se_id_lv0_reg, + NULL, + NULL, + }, + { + "se_id_lv1", + ETM_CRDT_SE_ID_LV1r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x182, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_se_id_lv1_reg, + NULL, + NULL, + }, + { + "se_id_lv2", + ETM_CRDT_SE_ID_LV2r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x183, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_se_id_lv2_reg, + NULL, + NULL, + }, + { + "se_id_lv3", + ETM_CRDT_SE_ID_LV3r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x184, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_se_id_lv3_reg, + NULL, + NULL, + }, + { + "se_id_lv4", + ETM_CRDT_SE_ID_LV4r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x185, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_se_id_lv4_reg, + NULL, + NULL, + }, + { + "que_id", + ETM_CRDT_QUE_IDr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x186, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_que_id_reg, + NULL, + NULL, + }, + { + "se_info_lv0", + ETM_CRDT_SE_INFO_LV0r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x187, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_etm_crdt_se_info_lv0_reg, + NULL, + NULL, + }, + { + "se_info_lv1", + ETM_CRDT_SE_INFO_LV1r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x188, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_etm_crdt_se_info_lv1_reg, + NULL, + NULL, + }, + { + "se_info_lv2", + ETM_CRDT_SE_INFO_LV2r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x189, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_etm_crdt_se_info_lv2_reg, + NULL, + NULL, + }, + { + "se_info_lv3", + ETM_CRDT_SE_INFO_LV3r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x18a, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_etm_crdt_se_info_lv3_reg, + NULL, + NULL, + }, + { + "se_info_lv4", + ETM_CRDT_SE_INFO_LV4r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x18b, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_etm_crdt_se_info_lv4_reg, + NULL, + NULL, + }, + { + "que_state", + ETM_CRDT_QUE_STATEr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x18c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_que_state_reg, + NULL, + NULL, + }, + { + "eir_off_in_advance", + ETM_CRDT_EIR_OFF_IN_ADVANCEr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x190, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_eir_off_in_advance_reg, + NULL, + NULL, + }, + { + "double_level_shap_prevent", + ETM_CRDT_DOUBLE_LEVEL_SHAP_PREVENTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x192, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_double_level_shap_prevent_reg, + NULL, + NULL, + }, + { + "add_store_cycle", + ETM_CRDT_ADD_STORE_CYCLEr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x193, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_add_store_cycle_reg, + NULL, + NULL, + }, + { + "tflag2_wr_flag_sum", + ETM_CRDT_TFLAG2_WR_FLAG_SUMr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x194, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_tflag2_wr_flag_sum_reg, + NULL, + NULL, + }, + { + "flowque_para_tbl", + ETM_CRDT_FLOWQUE_PARA_TBLr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x00000000 + 0x200000, + (32/8), + 0, + 0x47FF + 1, + 0, + 1, + 3, + g_etm_crdt_flowque_para_tbl_reg, + NULL, + NULL, + }, + { + "se_para_tbl", + ETM_CRDT_SE_PARA_TBLr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x80000000 + 0x300000, + (64/8), + 0, + 0x63FF + 1, + 0, + 1, + 5, + g_etm_crdt_se_para_tbl_reg, + NULL, + NULL, + }, + { + "flowque_ins_tbl", + ETM_CRDT_FLOWQUE_INS_TBLr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x00000000 + 0x400000, + (32/8), + 0, + 0x47FF + 1, + 0, + 1, + 1, + g_etm_crdt_flowque_ins_tbl_reg, + NULL, + NULL, + }, + { + "se_ins_tbl", + ETM_CRDT_SE_INS_TBLr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x00000000 + 0x500000, + (32/8), + 0, + 0x63FF + 1, + 0, + 1, + 2, + g_etm_crdt_se_ins_tbl_reg, + NULL, + NULL, + }, + { + "eir_crs_filter_tbl", + ETM_CRDT_EIR_CRS_FILTER_TBLr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x00000000 + 0x600000, + (32/8), + 0, + 0x23FF + 1, + 0, + 1, + 1, + g_etm_crdt_eir_crs_filter_tbl_reg, + NULL, + NULL, + }, + { + "qcfg_qlist_cfg_done", + ETM_QMU_QCFG_QLIST_CFG_DONEr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x10, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_qcfg_qlist_cfg_done_reg, + NULL, + NULL, + }, + { + "qcfg_qsch_credit_value", + ETM_QMU_QCFG_QSCH_CREDIT_VALUEr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x11, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_qcfg_qsch_credit_value_reg, + NULL, + NULL, + }, + { + "qcfg_qsch_crbal_init_value", + ETM_QMU_QCFG_QSCH_CRBAL_INIT_VALUEr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x12, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_qcfg_qsch_crbal_init_value_reg, + NULL, + NULL, + }, + { + "qcfg_qsch_crbal_init_mask", + ETM_QMU_QCFG_QSCH_CRBAL_INIT_MASKr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x13, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_qcfg_qsch_crbal_init_mask_reg, + NULL, + NULL, + }, + { + "cmdsch_rd_cmd_aful_th", + ETM_QMU_CMDSCH_RD_CMD_AFUL_THr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x22, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cmdsch_rd_cmd_aful_th_reg, + NULL, + NULL, + }, + { + "cfg_port_fc_interval", + ETM_QMU_CFG_PORT_FC_INTERVALr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x23, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_port_fc_interval_reg, + NULL, + NULL, + }, + { + "qcfg_csch_aged_cfg", + ETM_QMU_QCFG_CSCH_AGED_CFGr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x24, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_qcfg_csch_aged_cfg_reg, + NULL, + NULL, + }, + { + "qcfg_csch_aged_scan_time", + ETM_QMU_QCFG_CSCH_AGED_SCAN_TIMEr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x25, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_qcfg_csch_aged_scan_time_reg, + NULL, + NULL, + }, + { + "qcfg_qmu_qlist_state_query", + ETM_QMU_QCFG_QMU_QLIST_STATE_QUERYr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x26, + (32/8), + 0, + 0, + 0, + 0, + 19, + g_etm_qmu_qcfg_qmu_qlist_state_query_reg, + NULL, + NULL, + }, + { + "cfgmt_qsch_crbal_drop_en", + ETM_QMU_CFGMT_QSCH_CRBAL_DROP_ENr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x27, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_etm_qmu_cfgmt_qsch_crbal_drop_en_reg, + NULL, + NULL, + }, + { + "cfgmt_wlist_qnum_fifo_aful_th", + ETM_QMU_CFGMT_WLIST_QNUM_FIFO_AFUL_THr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x29, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfgmt_wlist_qnum_fifo_aful_th_reg, + NULL, + NULL, + }, + { + "qcfg_csw_pkt_blk_mode", + ETM_QMU_QCFG_CSW_PKT_BLK_MODEr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x28, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_qcfg_csw_pkt_blk_mode_reg, + NULL, + NULL, + }, + { + "qcfg_qlist_ram_init_cancel", + ETM_QMU_QCFG_QLIST_RAM_INIT_CANCELr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2a, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_qcfg_qlist_ram_init_cancel_reg, + NULL, + NULL, + }, + { + "qcfg_qsch_crbal_transfer_mode", + ETM_QMU_QCFG_QSCH_CRBAL_TRANSFER_MODEr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2b, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_etm_qmu_qcfg_qsch_crbal_transfer_mode_reg, + NULL, + NULL, + }, + { + "qcfg_qlist_qclr_interval", + ETM_QMU_QCFG_QLIST_QCLR_INTERVALr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_qcfg_qlist_qclr_interval_reg, + NULL, + NULL, + }, + { + "qcfg_qsch_qclr_rate", + ETM_QMU_QCFG_QSCH_QCLR_RATEr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2d, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_qcfg_qsch_qclr_rate_reg, + NULL, + NULL, + }, + { + "qcfg_qlist_ddr_random", + ETM_QMU_QCFG_QLIST_DDR_RANDOMr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2f, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_qcfg_qlist_ddr_random_reg, + NULL, + NULL, + }, + { + "cfgmt_qlist_pds_fifo_afull_th", + ETM_QMU_CFGMT_QLIST_PDS_FIFO_AFULL_THr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x30, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfgmt_qlist_pds_fifo_afull_th_reg, + NULL, + NULL, + }, + { + "cfgmt_sop_cmd_fifo_afull_th", + ETM_QMU_CFGMT_SOP_CMD_FIFO_AFULL_THr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x31, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfgmt_sop_cmd_fifo_afull_th_reg, + NULL, + NULL, + }, + { + "cfgmt_non_sop_cmd_fifo_afull_th", + ETM_QMU_CFGMT_NON_SOP_CMD_FIFO_AFULL_THr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x32, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfgmt_non_sop_cmd_fifo_afull_th_reg, + NULL, + NULL, + }, + { + "cfgmt_mmu_data_fifo_afull_th", + ETM_QMU_CFGMT_MMU_DATA_FIFO_AFULL_THr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x33, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfgmt_mmu_data_fifo_afull_th_reg, + NULL, + NULL, + }, + { + "qcfg_qlist_bank_ept_th", + ETM_QMU_QCFG_QLIST_BANK_EPT_THr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x34, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_qcfg_qlist_bank_ept_th_reg, + NULL, + NULL, + }, + { + "random_bypass_en", + ETM_QMU_RANDOM_BYPASS_ENr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x36, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_random_bypass_en_reg, + NULL, + NULL, + }, + { + "cfgmt_crs_spd_bypass", + ETM_QMU_CFGMT_CRS_SPD_BYPASSr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x37, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfgmt_crs_spd_bypass_reg, + NULL, + NULL, + }, + { + "cfgmt_crs_interval", + ETM_QMU_CFGMT_CRS_INTERVALr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x38, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfgmt_crs_interval_reg, + NULL, + NULL, + }, + { + "cfg_qsch_auto_credit_control_en", + ETM_QMU_CFG_QSCH_AUTO_CREDIT_CONTROL_ENr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x3b, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_auto_credit_control_en_reg, + NULL, + NULL, + }, + { + "cfg_qsch_autocrfrstque", + ETM_QMU_CFG_QSCH_AUTOCRFRSTQUEr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x3c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_autocrfrstque_reg, + NULL, + NULL, + }, + { + "cfg_qsch_autocrlastque", + ETM_QMU_CFG_QSCH_AUTOCRLASTQUEr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x3d, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_autocrlastque_reg, + NULL, + NULL, + }, + { + "cfg_qsch_autocreditrate", + ETM_QMU_CFG_QSCH_AUTOCREDITRATEr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x3e, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_autocreditrate_reg, + NULL, + NULL, + }, + { + "cfg_qsch_scanfrstque", + ETM_QMU_CFG_QSCH_SCANFRSTQUEr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x51, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_scanfrstque_reg, + NULL, + NULL, + }, + { + "cfg_qsch_scanlastque", + ETM_QMU_CFG_QSCH_SCANLASTQUEr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x52, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_scanlastque_reg, + NULL, + NULL, + }, + { + "cfg_qsch_scanrate", + ETM_QMU_CFG_QSCH_SCANRATEr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x53, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_scanrate_reg, + NULL, + NULL, + }, + { + "cfg_qsch_scan_en", + ETM_QMU_CFG_QSCH_SCAN_ENr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x54, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_scan_en_reg, + NULL, + NULL, + }, + { + "cfgmt_qsch_rd_credit_fifo_rate", + ETM_QMU_CFGMT_QSCH_RD_CREDIT_FIFO_RATEr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x7c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfgmt_qsch_rd_credit_fifo_rate_reg, + NULL, + NULL, + }, + { + "qcfg_qlist_bdep", + ETM_QMU_QCFG_QLIST_BDEPr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x9a7, + (32/8), + 0, + 0x3F + 1, + 0, + 1, + 1, + g_etm_qmu_qcfg_qlist_bdep_reg, + NULL, + NULL, + }, + { + "qcfg_qlist_bhead", + ETM_QMU_QCFG_QLIST_BHEADr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x9e7, + (32/8), + 0, + 0x3F + 1, + 0, + 1, + 2, + g_etm_qmu_qcfg_qlist_bhead_reg, + NULL, + NULL, + }, + { + "qcfg_qlist_btail", + ETM_QMU_QCFG_QLIST_BTAILr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0xa27, + (32/8), + 0, + 0x3F + 1, + 0, + 1, + 1, + g_etm_qmu_qcfg_qlist_btail_reg, + NULL, + NULL, + }, + { + "qcfg_qsch_shap_param", + ETM_QMU_QCFG_QSCH_SHAP_PARAMr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0xfc, + (32/8), + 0, + 0x3F + 1, + 0, + 1, + 3, + g_etm_qmu_qcfg_qsch_shap_param_reg, + NULL, + NULL, + }, + { + "qcfg_qsch_shap_token", + ETM_QMU_QCFG_QSCH_SHAP_TOKENr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x185, + (32/8), + 0, + 0x3F + 1, + 0, + 1, + 1, + g_etm_qmu_qcfg_qsch_shap_token_reg, + NULL, + NULL, + }, + { + "qcfg_qsch_shap_offset", + ETM_QMU_QCFG_QSCH_SHAP_OFFSETr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x20e, + (32/8), + 0, + 0x3F + 1, + 0, + 1, + 1, + g_etm_qmu_qcfg_qsch_shap_offset_reg, + NULL, + NULL, + }, + { + "qcfg_qsch_crs_eir_th", + ETM_QMU_QCFG_QSCH_CRS_EIR_THr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x250, + (32/8), + 0, + 0xF + 1, + 0, + 1, + 1, + g_etm_qmu_qcfg_qsch_crs_eir_th_reg, + NULL, + NULL, + }, + { + "qcfg_qsch_crs_th1", + ETM_QMU_QCFG_QSCH_CRS_TH1r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x297, + (32/8), + 0, + 0xF + 1, + 0, + 1, + 1, + g_etm_qmu_qcfg_qsch_crs_th1_reg, + NULL, + NULL, + }, + { + "qcfg_qsch_crs_th2", + ETM_QMU_QCFG_QSCH_CRS_TH2r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x2a7, + (32/8), + 0, + 0xF + 1, + 0, + 1, + 1, + g_etm_qmu_qcfg_qsch_crs_th2_reg, + NULL, + NULL, + }, + { + "qcfg_csch_congest_th", + ETM_QMU_QCFG_CSCH_CONGEST_THr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x2b7, + (32/8), + 0, + 0x3F + 1, + 0, + 1, + 1, + g_etm_qmu_qcfg_csch_congest_th_reg, + NULL, + NULL, + }, + { + "qcfg_csch_sp_fc_th", + ETM_QMU_QCFG_CSCH_SP_FC_THr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x330, + (32/8), + 0, + 0x140 + 1, + 0, + 1, + 1, + g_etm_qmu_qcfg_csch_sp_fc_th_reg, + NULL, + NULL, + }, + { + "qcfg_csw_shap_parameter", + ETM_QMU_QCFG_CSW_SHAP_PARAMETERr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x5d0, + (32/8), + 0, + 0x3F + 1, + 0, + 1, + 2, + g_etm_qmu_qcfg_csw_shap_parameter_reg, + NULL, + NULL, + }, + { + "cfgmt_rd_release_aful_th", + ETM_QMU_CFGMT_RD_RELEASE_AFUL_THr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x58e, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfgmt_rd_release_aful_th_reg, + NULL, + NULL, + }, + { + "cfgmt_drop_imem_release_fifo_aful_th", + ETM_QMU_CFGMT_DROP_IMEM_RELEASE_FIFO_AFUL_THr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x58f, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfgmt_drop_imem_release_fifo_aful_th_reg, + NULL, + NULL, + }, + { + "cfgmt_nnh_rd_buf_aful_th", + ETM_QMU_CFGMT_NNH_RD_BUF_AFUL_THr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x590, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfgmt_nnh_rd_buf_aful_th_reg, + NULL, + NULL, + }, + { + "cfg_pid_use_inall", + ETM_QMU_CFG_PID_USE_INALLr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x591, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_pid_use_inall_reg, + NULL, + NULL, + }, + { + "cfg_pid_round_th", + ETM_QMU_CFG_PID_ROUND_THr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x592, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_pid_round_th_reg, + NULL, + NULL, + }, + { + "cfgmt_credit_fifo_afull_th", + ETM_QMU_CFGMT_CREDIT_FIFO_AFULL_THr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x593, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfgmt_credit_fifo_afull_th_reg, + NULL, + NULL, + }, + { + "cfgmt_scan_fifo_afull_th", + ETM_QMU_CFGMT_SCAN_FIFO_AFULL_THr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x594, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfgmt_scan_fifo_afull_th_reg, + NULL, + NULL, + }, + { + "cfgmt_small_fifo_aful_th", + ETM_QMU_CFGMT_SMALL_FIFO_AFUL_THr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x595, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfgmt_small_fifo_aful_th_reg, + NULL, + NULL, + }, + { + "cfgmt_free_addr_fifo_aful_th", + ETM_QMU_CFGMT_FREE_ADDR_FIFO_AFUL_THr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x596, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfgmt_free_addr_fifo_aful_th_reg, + NULL, + NULL, + }, + { + "cfgmt_enq_rpt_fifo_aful_th", + ETM_QMU_CFGMT_ENQ_RPT_FIFO_AFUL_THr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x597, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfgmt_enq_rpt_fifo_aful_th_reg, + NULL, + NULL, + }, + { + "qcfg_csw_shap_token_depth", + ETM_QMU_QCFG_CSW_SHAP_TOKEN_DEPTHr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x656, + (32/8), + 0, + 0x3F + 1, + 0, + 1, + 1, + g_etm_qmu_qcfg_csw_shap_token_depth_reg, + NULL, + NULL, + }, + { + "qcfg_csw_shap_offset_value", + ETM_QMU_QCFG_CSW_SHAP_OFFSET_VALUEr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x6cf, + (32/8), + 0, + 0x3F + 1, + 0, + 1, + 1, + g_etm_qmu_qcfg_csw_shap_offset_value_reg, + NULL, + NULL, + }, + { + "qcfg_csw_fc_offset_value", + ETM_QMU_QCFG_CSW_FC_OFFSET_VALUEr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x750, + (32/8), + 0, + 0x3F + 1, + 0, + 1, + 1, + g_etm_qmu_qcfg_csw_fc_offset_value_reg, + NULL, + NULL, + }, + { + "qmu_init_done_state", + ETM_QMU_QMU_INIT_DONE_STATEr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2000, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_etm_qmu_qmu_init_done_state_reg, + NULL, + NULL, + }, + { + "csw_qcfg_port_shap_rdy_0", + ETM_QMU_CSW_QCFG_PORT_SHAP_RDY_0r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2001, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_csw_qcfg_port_shap_rdy_0_reg, + NULL, + NULL, + }, + { + "csw_qcfg_port_shap_rdy_1", + ETM_QMU_CSW_QCFG_PORT_SHAP_RDY_1r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2002, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_csw_qcfg_port_shap_rdy_1_reg, + NULL, + NULL, + }, + { + "qlist_cfgmt_ram_init_done", + ETM_QMU_QLIST_CFGMT_RAM_INIT_DONEr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2015, + (32/8), + 0, + 0, + 0, + 0, + 8, + g_etm_qmu_qlist_cfgmt_ram_init_done_reg, + NULL, + NULL, + }, + { + "qlist_cfgmt_ram_ecc_err", + ETM_QMU_QLIST_CFGMT_RAM_ECC_ERRr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2016, + (32/8), + 0, + 0, + 0, + 0, + 30, + g_etm_qmu_qlist_cfgmt_ram_ecc_err_reg, + NULL, + NULL, + }, + { + "qlist_cfgmt_ram_slot_err", + ETM_QMU_QLIST_CFGMT_RAM_SLOT_ERRr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2017, + (32/8), + 0, + 0, + 0, + 0, + 20, + g_etm_qmu_qlist_cfgmt_ram_slot_err_reg, + NULL, + NULL, + }, + { + "qsch_cfgmt_ram_ecc", + ETM_QMU_QSCH_CFGMT_RAM_ECCr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2018, + (32/8), + 0, + 0, + 0, + 0, + 27, + g_etm_qmu_qsch_cfgmt_ram_ecc_reg, + NULL, + NULL, + }, + { + "qlist_cfgmt_fifo_state", + ETM_QMU_QLIST_CFGMT_FIFO_STATEr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2019, + (32/8), + 0, + 0, + 0, + 0, + 26, + g_etm_qmu_qlist_cfgmt_fifo_state_reg, + NULL, + NULL, + }, + { + "qlist_qcfg_clr_done", + ETM_QMU_QLIST_QCFG_CLR_DONEr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x201a, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_qlist_qcfg_clr_done_reg, + NULL, + NULL, + }, + { + "qmu_int_mask1", + ETM_QMU_QMU_INT_MASK1r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x201b, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_qmu_int_mask1_reg, + NULL, + NULL, + }, + { + "qmu_int_mask2", + ETM_QMU_QMU_INT_MASK2r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x201c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_qmu_int_mask2_reg, + NULL, + NULL, + }, + { + "qmu_int_mask3", + ETM_QMU_QMU_INT_MASK3r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x201d, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_qmu_int_mask3_reg, + NULL, + NULL, + }, + { + "qmu_int_mask4", + ETM_QMU_QMU_INT_MASK4r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x201e, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_qmu_int_mask4_reg, + NULL, + NULL, + }, + { + "qmu_int_mask5", + ETM_QMU_QMU_INT_MASK5r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x201f, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_qmu_int_mask5_reg, + NULL, + NULL, + }, + { + "qmu_int_mask6", + ETM_QMU_QMU_INT_MASK6r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2013, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_qmu_int_mask6_reg, + NULL, + NULL, + }, + { + "cmd_sch_cfgmt_fifo_state", + ETM_QMU_CMD_SCH_CFGMT_FIFO_STATEr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2020, + (32/8), + 0, + 0, + 0, + 0, + 26, + g_etm_qmu_cmd_sch_cfgmt_fifo_state_reg, + NULL, + NULL, + }, + { + "qlist_r_bcnt", + ETM_QMU_QLIST_R_BCNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x60000, + (32/8), + 0, + 0x23ff + 1, + 0, + 1, + 1, + g_etm_qmu_qlist_r_bcnt_reg, + NULL, + NULL, + }, + { + "qsch_rw_crbal", + ETM_QMU_QSCH_RW_CRBALr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x70000, + (32/8), + 0, + 0x23ff + 1, + 0, + 1, + 1, + g_etm_qmu_qsch_rw_crbal_reg, + NULL, + NULL, + }, + { + "qsch_rw_crs", + ETM_QMU_QSCH_RW_CRSr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x80000, + (32/8), + 0, + 0x23ff + 1, + 0, + 1, + 1, + g_etm_qmu_qsch_rw_crs_reg, + NULL, + NULL, + }, + { + "qsch_r_wlist_empty", + ETM_QMU_QSCH_R_WLIST_EMPTYr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0xa0000, + (32/8), + 0, + 0xfff + 1, + 0, + 1, + 1, + g_etm_qmu_qsch_r_wlist_empty_reg, + NULL, + NULL, + }, + { + "qcfg_qlist_baram_rd", + ETM_QMU_QCFG_QLIST_BARAM_RDr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0xe0000, + (32/8), + 0, + 0x7ff + 1, + 0, + 1, + 1, + g_etm_qmu_qcfg_qlist_baram_rd_reg, + NULL, + NULL, + }, + { + "qcfg_qsch_crbal_fb_rw", + ETM_QMU_QCFG_QSCH_CRBAL_FB_RWr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0xb0000, + (32/8), + 0, + 0x23ff + 1, + 0, + 1, + 1, + g_etm_qmu_qcfg_qsch_crbal_fb_rw_reg, + NULL, + NULL, + }, + { + "qcfg_qlist_grp0_bank", + ETM_QMU_QCFG_QLIST_GRP0_BANKr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x7c1, + (32/8), + 0, + 0x3f + 1, + 0, + 1, + 1, + g_etm_qmu_qcfg_qlist_grp0_bank_reg, + NULL, + NULL, + }, + { + "qcfg_qlist_grp1_bank", + ETM_QMU_QCFG_QLIST_GRP1_BANKr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x801, + (32/8), + 0, + 0x3f + 1, + 0, + 1, + 1, + g_etm_qmu_qcfg_qlist_grp1_bank_reg, + NULL, + NULL, + }, + { + "qcfg_qlist_grp2_bank", + ETM_QMU_QCFG_QLIST_GRP2_BANKr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x841, + (32/8), + 0, + 0x3f + 1, + 0, + 1, + 1, + g_etm_qmu_qcfg_qlist_grp2_bank_reg, + NULL, + NULL, + }, + { + "qcfg_qlist_grp3_bank", + ETM_QMU_QCFG_QLIST_GRP3_BANKr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x881, + (32/8), + 0, + 0x3f + 1, + 0, + 1, + 1, + g_etm_qmu_qcfg_qlist_grp3_bank_reg, + NULL, + NULL, + }, + { + "qcfg_qlist_grp4_bank", + ETM_QMU_QCFG_QLIST_GRP4_BANKr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x8c1, + (32/8), + 0, + 0x3f + 1, + 0, + 1, + 1, + g_etm_qmu_qcfg_qlist_grp4_bank_reg, + NULL, + NULL, + }, + { + "qcfg_qlist_grp5_bank", + ETM_QMU_QCFG_QLIST_GRP5_BANKr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x967, + (32/8), + 0, + 0x3f + 1, + 0, + 1, + 1, + g_etm_qmu_qcfg_qlist_grp5_bank_reg, + NULL, + NULL, + }, + { + "qcfg_qlist_grp6_bank", + ETM_QMU_QCFG_QLIST_GRP6_BANKr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0xc00, + (32/8), + 0, + 0x3f + 1, + 0, + 1, + 1, + g_etm_qmu_qcfg_qlist_grp6_bank_reg, + NULL, + NULL, + }, + { + "qcfg_qlist_grp7_bank", + ETM_QMU_QCFG_QLIST_GRP7_BANKr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0xc40, + (32/8), + 0, + 0x3f + 1, + 0, + 1, + 1, + g_etm_qmu_qcfg_qlist_grp7_bank_reg, + NULL, + NULL, + }, + { + "qcfg_qlist_grp", + ETM_QMU_QCFG_QLIST_GRPr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x901, + (32/8), + 0, + 0x3f + 1, + 0, + 1, + 1, + g_etm_qmu_qcfg_qlist_grp_reg, + NULL, + NULL, + }, + { + "cfgmt_active_to_bank_cfg", + ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFGr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x941, + (32/8), + 0, + 0xf + 1, + 0, + 1, + 1, + g_etm_qmu_cfgmt_active_to_bank_cfg_reg, + NULL, + NULL, + }, + { + "cfgmt_ddr_in_mmu_cfg", + ETM_QMU_CFGMT_DDR_IN_MMU_CFGr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x951, + (32/8), + 0, + 0x7 + 1, + 0, + 1, + 1, + g_etm_qmu_cfgmt_ddr_in_mmu_cfg_reg, + NULL, + NULL, + }, + { + "cfgmt_ddr_in_qmu_cfg", + ETM_QMU_CFGMT_DDR_IN_QMU_CFGr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x959, + (32/8), + 0, + 0x9 + 1, + 0, + 1, + 1, + g_etm_qmu_cfgmt_ddr_in_qmu_cfg_reg, + NULL, + NULL, + }, + { + "cfgmt_bank_to_mmu_cfg", + ETM_QMU_CFGMT_BANK_TO_MMU_CFGr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0xb00, + (32/8), + 0, + 0x3f + 1, + 0, + 1, + 1, + g_etm_qmu_cfgmt_bank_to_mmu_cfg_reg, + NULL, + NULL, + }, + { + "cfgmt_bank_to_qmu_cfg", + ETM_QMU_CFGMT_BANK_TO_QMU_CFGr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0xb40, + (32/8), + 0, + 0x4f + 1, + 0, + 1, + 1, + g_etm_qmu_cfgmt_bank_to_qmu_cfg_reg, + NULL, + NULL, + }, + { + "cfgmt_grp_ram_n_clr_thd", + ETM_QMU_CFGMT_GRP_RAM_N_CLR_THDr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0xe0a, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfgmt_grp_ram_n_clr_thd_reg, + NULL, + NULL, + }, + { + "cfgmt_age_pkt_num", + ETM_QMU_CFGMT_AGE_PKT_NUMr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0xe00, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfgmt_age_pkt_num_reg, + NULL, + NULL, + }, + { + "cfgmt_age_multi_interval", + ETM_QMU_CFGMT_AGE_MULTI_INTERVALr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0xe01, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfgmt_age_multi_interval_reg, + NULL, + NULL, + }, + { + "cfgmt_qmu_pkt_age_en", + ETM_QMU_CFGMT_QMU_PKT_AGE_ENr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0xe02, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfgmt_qmu_pkt_age_en_reg, + NULL, + NULL, + }, + { + "cfgmt_qmu_pkt_age_interval", + ETM_QMU_CFGMT_QMU_PKT_AGE_INTERVALr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0xe03, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfgmt_qmu_pkt_age_interval_reg, + NULL, + NULL, + }, + { + "cfgmt_qmu_pkt_age_start_end", + ETM_QMU_CFGMT_QMU_PKT_AGE_START_ENDr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0xe04, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_etm_qmu_cfgmt_qmu_pkt_age_start_end_reg, + NULL, + NULL, + }, + { + "cfgmt_pkt_age_req_aful_th", + ETM_QMU_CFGMT_PKT_AGE_REQ_AFUL_THr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0xe05, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfgmt_pkt_age_req_aful_th_reg, + NULL, + NULL, + }, + { + "cfgmt_pkt_age_step_interval", + ETM_QMU_CFGMT_PKT_AGE_STEP_INTERVALr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0xe12, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfgmt_pkt_age_step_interval_reg, + NULL, + NULL, + }, + { + "cfgmt_qmu_imem_age_mode", + ETM_QMU_CFGMT_QMU_IMEM_AGE_MODEr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0xe06, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_etm_qmu_cfgmt_qmu_imem_age_mode_reg, + NULL, + NULL, + }, + { + "cfgmt_qmu_imem_qlen_age_interval", + ETM_QMU_CFGMT_QMU_IMEM_QLEN_AGE_INTERVALr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0xe07, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfgmt_qmu_imem_qlen_age_interval_reg, + NULL, + NULL, + }, + { + "cfgmt_qmu_imem_time_age_interval", + ETM_QMU_CFGMT_QMU_IMEM_TIME_AGE_INTERVALr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0xe08, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfgmt_qmu_imem_time_age_interval_reg, + NULL, + NULL, + }, + { + "cfgmt_qmu_imem_qlen_age_thd", + ETM_QMU_CFGMT_QMU_IMEM_QLEN_AGE_THDr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0xe09, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfgmt_qmu_imem_qlen_age_thd_reg, + NULL, + NULL, + }, + { + "cfgmt_imem_age_step_interval", + ETM_QMU_CFGMT_IMEM_AGE_STEP_INTERVALr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0xe13, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfgmt_imem_age_step_interval_reg, + NULL, + NULL, + }, + { + "cfgmt_qmu_ecc_bypass_read", + ETM_QMU_CFGMT_QMU_ECC_BYPASS_READr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0xe0b, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfgmt_qmu_ecc_bypass_read_reg, + NULL, + NULL, + }, + { + "cfgmt_qmu_resp_stat_fc_en", + ETM_QMU_CFGMT_QMU_RESP_STAT_FC_ENr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0xe0c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfgmt_qmu_resp_stat_fc_en_reg, + NULL, + NULL, + }, + { + "cfgmt_qmu_bank_xoff_pds_mode", + ETM_QMU_CFGMT_QMU_BANK_XOFF_PDS_MODEr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0xe10, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfgmt_qmu_bank_xoff_pds_mode_reg, + NULL, + NULL, + }, + { + "cfgmt_qmu_stat_offset", + ETM_QMU_CFGMT_QMU_STAT_OFFSETr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0xe11, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfgmt_qmu_stat_offset_reg, + NULL, + NULL, + }, + { + "fc_cnt_mode", + ETM_QMU_FC_CNT_MODEr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2800, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_fc_cnt_mode_reg, + NULL, + NULL, + }, + { + "mmu_qmu_wr_fc_cnt", + ETM_QMU_MMU_QMU_WR_FC_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2801, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_mmu_qmu_wr_fc_cnt_reg, + NULL, + NULL, + }, + { + "mmu_qmu_rd_fc_cnt", + ETM_QMU_MMU_QMU_RD_FC_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2802, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_mmu_qmu_rd_fc_cnt_reg, + NULL, + NULL, + }, + { + "qmu_cgavd_fc_cnt", + ETM_QMU_QMU_CGAVD_FC_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2803, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_qmu_cgavd_fc_cnt_reg, + NULL, + NULL, + }, + { + "cgavd_qmu_pkt_cnt", + ETM_QMU_CGAVD_QMU_PKT_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2804, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cgavd_qmu_pkt_cnt_reg, + NULL, + NULL, + }, + { + "cgavd_qmu_pktlen_all", + ETM_QMU_CGAVD_QMU_PKTLEN_ALLr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2805, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cgavd_qmu_pktlen_all_reg, + NULL, + NULL, + }, + { + "observe_portfc_spec", + ETM_QMU_OBSERVE_PORTFC_SPECr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2818, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_observe_portfc_spec_reg, + NULL, + NULL, + }, + { + "spec_lif_portfc_count", + ETM_QMU_SPEC_LIF_PORTFC_COUNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2819, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_spec_lif_portfc_count_reg, + NULL, + NULL, + }, + { + "cfgmt_qmu_pfc_en", + ETM_QMU_CFGMT_QMU_PFC_ENr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20e0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfgmt_qmu_pfc_en_reg, + NULL, + NULL, + }, + { + "cfgmt_qmu_pfc_mask_1", + ETM_QMU_CFGMT_QMU_PFC_MASK_1r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20e1, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfgmt_qmu_pfc_mask_1_reg, + NULL, + NULL, + }, + { + "cfgmt_qmu_pfc_mask_2", + ETM_QMU_CFGMT_QMU_PFC_MASK_2r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20e2, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfgmt_qmu_pfc_mask_2_reg, + NULL, + NULL, + }, + { + "int_repeat", + CFG_PCIE_INT_REPEATr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x0dc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_int_repeat_reg, + NULL, + NULL, + }, + { + "dma_up_size", + CFG_DMA_DMA_UP_SIZEr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x020, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_dma_dma_up_size_reg, + NULL, + NULL, + }, + { + "soc_wr_time_out_thresh", + CFG_CSR_SOC_WR_TIME_OUT_THRESHr, + CFG, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x028, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_csr_soc_wr_time_out_thresh_reg, + NULL, + NULL, + }, + { + "cfg_shap_param", + NPPU_MR_CFG_CFG_SHAP_PARAMr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0024, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_nppu_mr_cfg_cfg_shap_param_reg, + NULL, + NULL, + }, + { + "cfg_shap_token", + NPPU_MR_CFG_CFG_SHAP_TOKENr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0028, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_nppu_mr_cfg_cfg_shap_token_reg, + NULL, + NULL, + }, + { + "idle_ptr_fifo_aful_th", + NPPU_MR_CFG_IDLE_PTR_FIFO_AFUL_THr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x003c, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_nppu_mr_cfg_idle_ptr_fifo_aful_th_reg, + NULL, + NULL, + }, + { + "mr_cos_port_cfg", + NPPU_MR_CFG_MR_COS_PORT_CFGr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0104, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_nppu_mr_cfg_mr_cos_port_cfg_reg, + NULL, + NULL, + }, + { + "ind_status", + NPPU_PKTRX_CFG_IND_STATUSr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0000, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pktrx_cfg_ind_status_reg, + NULL, + NULL, + }, + { + "ind_cmd", + NPPU_PKTRX_CFG_IND_CMDr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0004, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_nppu_pktrx_cfg_ind_cmd_reg, + NULL, + NULL, + }, + { + "ind_data0", + NPPU_PKTRX_CFG_IND_DATA0r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0008, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pktrx_cfg_ind_data0_reg, + NULL, + NULL, + }, + { + "ind_data1", + NPPU_PKTRX_CFG_IND_DATA1r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x000c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pktrx_cfg_ind_data1_reg, + NULL, + NULL, + }, + { + "ind_data2", + NPPU_PKTRX_CFG_IND_DATA2r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0010, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pktrx_cfg_ind_data2_reg, + NULL, + NULL, + }, + { + "ind_data3", + NPPU_PKTRX_CFG_IND_DATA3r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0014, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pktrx_cfg_ind_data3_reg, + NULL, + NULL, + }, + { + "ind_data4", + NPPU_PKTRX_CFG_IND_DATA4r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0018, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pktrx_cfg_ind_data4_reg, + NULL, + NULL, + }, + { + "ind_data5", + NPPU_PKTRX_CFG_IND_DATA5r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x001c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pktrx_cfg_ind_data5_reg, + NULL, + NULL, + }, + { + "ind_data6", + NPPU_PKTRX_CFG_IND_DATA6r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0020, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pktrx_cfg_ind_data6_reg, + NULL, + NULL, + }, + { + "ind_data7", + NPPU_PKTRX_CFG_IND_DATA7r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0024, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pktrx_cfg_ind_data7_reg, + NULL, + NULL, + }, + { + "tcam_0_cmd", + NPPU_PKTRX_CFG_TCAM_0_CMDr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0028, + (32/8), + 0, + 0, + 0, + 0, + 11, + g_nppu_pktrx_cfg_tcam_0_cmd_reg, + NULL, + NULL, + }, + { + "tcam_1_cmd", + NPPU_PKTRX_CFG_TCAM_1_CMDr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x002c, + (32/8), + 0, + 0, + 0, + 0, + 8, + g_nppu_pktrx_cfg_tcam_1_cmd_reg, + NULL, + NULL, + }, + { + "port_en_0", + NPPU_PKTRX_CFG_PORT_EN_0r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0030, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pktrx_cfg_port_en_0_reg, + NULL, + NULL, + }, + { + "port_en_1", + NPPU_PKTRX_CFG_PORT_EN_1r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0034, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pktrx_cfg_port_en_1_reg, + NULL, + NULL, + }, + { + "port_en_2", + NPPU_PKTRX_CFG_PORT_EN_2r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0038, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pktrx_cfg_port_en_2_reg, + NULL, + NULL, + }, + { + "port_en_3", + NPPU_PKTRX_CFG_PORT_EN_3r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x003c, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_nppu_pktrx_cfg_port_en_3_reg, + NULL, + NULL, + }, + { + "cfg_port_l2_offset_mode_0", + NPPU_PKTRX_CFG_CFG_PORT_L2_OFFSET_MODE_0r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0040, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pktrx_cfg_cfg_port_l2_offset_mode_0_reg, + NULL, + NULL, + }, + { + "cfg_port_l2_offset_mode_1", + NPPU_PKTRX_CFG_CFG_PORT_L2_OFFSET_MODE_1r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0044, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pktrx_cfg_cfg_port_l2_offset_mode_1_reg, + NULL, + NULL, + }, + { + "cfg_port_l2_offset_mode_2", + NPPU_PKTRX_CFG_CFG_PORT_L2_OFFSET_MODE_2r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0048, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pktrx_cfg_cfg_port_l2_offset_mode_2_reg, + NULL, + NULL, + }, + { + "cfg_port_l2_offset_mode_3", + NPPU_PKTRX_CFG_CFG_PORT_L2_OFFSET_MODE_3r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x004c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pktrx_cfg_cfg_port_l2_offset_mode_3_reg, + NULL, + NULL, + }, + { + "port_fc_mode_0", + NPPU_PKTRX_CFG_PORT_FC_MODE_0r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0050, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pktrx_cfg_port_fc_mode_0_reg, + NULL, + NULL, + }, + { + "port_fc_mode_1", + NPPU_PKTRX_CFG_PORT_FC_MODE_1r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0054, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pktrx_cfg_port_fc_mode_1_reg, + NULL, + NULL, + }, + { + "port_fc_mode_2", + NPPU_PKTRX_CFG_PORT_FC_MODE_2r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0058, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pktrx_cfg_port_fc_mode_2_reg, + NULL, + NULL, + }, + { + "port_fc_mode_3", + NPPU_PKTRX_CFG_PORT_FC_MODE_3r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x005c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pktrx_cfg_port_fc_mode_3_reg, + NULL, + NULL, + }, + { + "port_fc_mode_4", + NPPU_PKTRX_CFG_PORT_FC_MODE_4r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0060, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pktrx_cfg_port_fc_mode_4_reg, + NULL, + NULL, + }, + { + "port_fc_mode_5", + NPPU_PKTRX_CFG_PORT_FC_MODE_5r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0064, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pktrx_cfg_port_fc_mode_5_reg, + NULL, + NULL, + }, + { + "port_fc_mode_6", + NPPU_PKTRX_CFG_PORT_FC_MODE_6r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0068, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pktrx_cfg_port_fc_mode_6_reg, + NULL, + NULL, + }, + { + "port_fc_mode_7", + NPPU_PKTRX_CFG_PORT_FC_MODE_7r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x006c, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_nppu_pktrx_cfg_port_fc_mode_7_reg, + NULL, + NULL, + }, + { + "cfg_isch_aging_th", + NPPU_PKTRX_CFG_CFG_ISCH_AGING_THr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0070, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_nppu_pktrx_cfg_cfg_isch_aging_th_reg, + NULL, + NULL, + }, + { + "isch_fifo_th_0", + NPPU_PKTRX_CFG_ISCH_FIFO_TH_0r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0074, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_nppu_pktrx_cfg_isch_fifo_th_0_reg, + NULL, + NULL, + }, + { + "isch_cfg_1", + NPPU_PKTRX_CFG_ISCH_CFG_1r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x008c, + (32/8), + 0, + 0, + 0, + 0, + 5, + g_nppu_pktrx_cfg_isch_cfg_1_reg, + NULL, + NULL, + }, + { + "tcam_0_vld", + NPPU_PKTRX_CFG_TCAM_0_VLDr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x00d4, + (32/8), + 0, + 7 + 1, + 0, + 4, + 1, + g_nppu_pktrx_cfg_tcam_0_vld_reg, + NULL, + NULL, + }, + { + "tcam_1_vld", + NPPU_PKTRX_CFG_TCAM_1_VLDr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x00f4, + (32/8), + 0, + 7 + 1, + 0, + 4, + 1, + g_nppu_pktrx_cfg_tcam_1_vld_reg, + NULL, + NULL, + }, + { + "cpu_port_en_mask", + NPPU_PKTRX_CFG_CPU_PORT_EN_MASKr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x01f4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pktrx_cfg_cpu_port_en_mask_reg, + NULL, + NULL, + }, + { + "pktrx_glbal_cfg_0", + NPPU_PKTRX_CFG_PKTRX_GLBAL_CFG_0r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x01f8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pktrx_cfg_pktrx_glbal_cfg_0_reg, + NULL, + NULL, + }, + { + "pktrx_glbal_cfg_1", + NPPU_PKTRX_CFG_PKTRX_GLBAL_CFG_1r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x01fc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pktrx_cfg_pktrx_glbal_cfg_1_reg, + NULL, + NULL, + }, + { + "pktrx_glbal_cfg_2", + NPPU_PKTRX_CFG_PKTRX_GLBAL_CFG_2r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0200, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pktrx_cfg_pktrx_glbal_cfg_2_reg, + NULL, + NULL, + }, + { + "pktrx_glbal_cfg_3", + NPPU_PKTRX_CFG_PKTRX_GLBAL_CFG_3r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0204, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pktrx_cfg_pktrx_glbal_cfg_3_reg, + NULL, + NULL, + }, + { + "nppu_start", + NPPU_PKTRX_CFG_NPPU_STARTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0208, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pktrx_cfg_nppu_start_reg, + NULL, + NULL, + }, + { + "ind_status", + NPPU_PKTRX_STAT_IND_STATUSr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_STAT_BASE_ADDR + 0x0000, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pktrx_stat_ind_status_reg, + NULL, + NULL, + }, + { + "ind_cmd", + NPPU_PKTRX_STAT_IND_CMDr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_STAT_BASE_ADDR + 0x0004, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_nppu_pktrx_stat_ind_cmd_reg, + NULL, + NULL, + }, + { + "ind_data0", + NPPU_PKTRX_STAT_IND_DATA0r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_STAT_BASE_ADDR + 0x0008, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pktrx_stat_ind_data0_reg, + NULL, + NULL, + }, + { + "debug_cnt_ovfl_mode", + NPPU_IDMA_CFG_DEBUG_CNT_OVFL_MODEr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_IDMA_CFG_BASE_ADDR + 0x4f4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_idma_cfg_debug_cnt_ovfl_mode_reg, + NULL, + NULL, + }, + { + "ind_status", + NPPU_IDMA_STAT_IND_STATUSr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_IDMA_STAT_BASE_ADDR + 0x0400, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_idma_stat_ind_status_reg, + NULL, + NULL, + }, + { + "ind_cmd", + NPPU_IDMA_STAT_IND_CMDr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_IDMA_STAT_BASE_ADDR + 0x0404, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_nppu_idma_stat_ind_cmd_reg, + NULL, + NULL, + }, + { + "ind_data0", + NPPU_IDMA_STAT_IND_DATA0r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_IDMA_STAT_BASE_ADDR + 0x0408, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_idma_stat_ind_data0_reg, + NULL, + NULL, + }, + { + "ind_status", + NPPU_PBU_CFG_IND_STATUSr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x400, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_cfg_ind_status_reg, + NULL, + NULL, + }, + { + "ind_cmd", + NPPU_PBU_CFG_IND_CMDr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x404, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_nppu_pbu_cfg_ind_cmd_reg, + NULL, + NULL, + }, + { + "ind_data0", + NPPU_PBU_CFG_IND_DATA0r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x408, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_cfg_ind_data0_reg, + NULL, + NULL, + }, + { + "ind_data1", + NPPU_PBU_CFG_IND_DATA1r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x40c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_cfg_ind_data1_reg, + NULL, + NULL, + }, + { + "ind_data2", + NPPU_PBU_CFG_IND_DATA2r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x410, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_cfg_ind_data2_reg, + NULL, + NULL, + }, + { + "ind_data3", + NPPU_PBU_CFG_IND_DATA3r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x414, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_cfg_ind_data3_reg, + NULL, + NULL, + }, + { + "ind_data4", + NPPU_PBU_CFG_IND_DATA4r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x418, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_cfg_ind_data4_reg, + NULL, + NULL, + }, + { + "ind_data5", + NPPU_PBU_CFG_IND_DATA5r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x41c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_cfg_ind_data5_reg, + NULL, + NULL, + }, + { + "ind_data6", + NPPU_PBU_CFG_IND_DATA6r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x420, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_cfg_ind_data6_reg, + NULL, + NULL, + }, + { + "ind_data7", + NPPU_PBU_CFG_IND_DATA7r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x424, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_cfg_ind_data7_reg, + NULL, + NULL, + }, + { + "idma_public_th", + NPPU_PBU_CFG_IDMA_PUBLIC_THr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x4c8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_cfg_idma_public_th_reg, + NULL, + NULL, + }, + { + "lif_public_th", + NPPU_PBU_CFG_LIF_PUBLIC_THr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x4cc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_cfg_lif_public_th_reg, + NULL, + NULL, + }, + { + "idma_total_th", + NPPU_PBU_CFG_IDMA_TOTAL_THr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x4d0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_cfg_idma_total_th_reg, + NULL, + NULL, + }, + { + "lif_total_th", + NPPU_PBU_CFG_LIF_TOTAL_THr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x4d4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_cfg_lif_total_th_reg, + NULL, + NULL, + }, + { + "mc_total_th", + NPPU_PBU_CFG_MC_TOTAL_THr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x4d8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_cfg_mc_total_th_reg, + NULL, + NULL, + }, + { + "mc_cos10_th", + NPPU_PBU_CFG_MC_COS10_THr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x4dc, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_nppu_pbu_cfg_mc_cos10_th_reg, + NULL, + NULL, + }, + { + "mc_cos32_th", + NPPU_PBU_CFG_MC_COS32_THr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x4e0, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_nppu_pbu_cfg_mc_cos32_th_reg, + NULL, + NULL, + }, + { + "mc_cos54_th", + NPPU_PBU_CFG_MC_COS54_THr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x4e4, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_nppu_pbu_cfg_mc_cos54_th_reg, + NULL, + NULL, + }, + { + "mc_cos76_th", + NPPU_PBU_CFG_MC_COS76_THr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x4e8, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_nppu_pbu_cfg_mc_cos76_th_reg, + NULL, + NULL, + }, + { + "debug_cnt_ovfl_mode", + NPPU_PBU_CFG_DEBUG_CNT_OVFL_MODEr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x4f4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_cfg_debug_cnt_ovfl_mode_reg, + NULL, + NULL, + }, + { + "se_key_aful_negate_cfg", + NPPU_PBU_CFG_SE_KEY_AFUL_NEGATE_CFGr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x530, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_cfg_se_key_aful_negate_cfg_reg, + NULL, + NULL, + }, + { + "sa_flag", + NPPU_PBU_CFG_SA_FLAGr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x724, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_cfg_sa_flag_reg, + NULL, + NULL, + }, + { + "ind_data", + NPPU_PBU_STAT_IND_DATAr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x0000, + (32/8), + 0, + 127 + 1, + 0, + 4, + 1, + g_nppu_pbu_stat_ind_data_reg, + NULL, + NULL, + }, + { + "ind_status", + NPPU_PBU_STAT_IND_STATUSr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x0400, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_stat_ind_status_reg, + NULL, + NULL, + }, + { + "ind_cmd", + NPPU_PBU_STAT_IND_CMDr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x0404, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_nppu_pbu_stat_ind_cmd_reg, + NULL, + NULL, + }, + { + "total_cnt", + NPPU_PBU_STAT_TOTAL_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x558, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_stat_total_cnt_reg, + NULL, + NULL, + }, + { + "idma_pub_cnt", + NPPU_PBU_STAT_IDMA_PUB_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x55c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_stat_idma_pub_cnt_reg, + NULL, + NULL, + }, + { + "lif_pub_cnt", + NPPU_PBU_STAT_LIF_PUB_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x560, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_stat_lif_pub_cnt_reg, + NULL, + NULL, + }, + { + "mc_total_cnt", + NPPU_PBU_STAT_MC_TOTAL_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x564, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_stat_mc_total_cnt_reg, + NULL, + NULL, + }, + { + "pbu_thram_init_done", + NPPU_PBU_STAT_PBU_THRAM_INIT_DONEr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x568, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_stat_pbu_thram_init_done_reg, + NULL, + NULL, + }, + { + "ifb_fptr_init_done", + NPPU_PBU_STAT_IFB_FPTR_INIT_DONEr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x56c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_stat_ifb_fptr_init_done_reg, + NULL, + NULL, + }, + { + "weight_normal_uc", + NPPU_ISU_CFG_WEIGHT_NORMAL_UCr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_CFG_BASE_ADDR + 0x0000, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_isu_cfg_weight_normal_uc_reg, + NULL, + NULL, + }, + { + "fabric_or_saip", + NPPU_ISU_CFG_FABRIC_OR_SAIPr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_CFG_BASE_ADDR + 0x0028, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_isu_cfg_fabric_or_saip_reg, + NULL, + NULL, + }, + { + "ind_status", + NPPU_ISU_STAT_IND_STATUSr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x0000, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_isu_stat_ind_status_reg, + NULL, + NULL, + }, + { + "ind_cmd", + NPPU_ISU_STAT_IND_CMDr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x0004, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_nppu_isu_stat_ind_cmd_reg, + NULL, + NULL, + }, + { + "ind_dat0", + NPPU_ISU_STAT_IND_DAT0r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x0008, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_isu_stat_ind_dat0_reg, + NULL, + NULL, + }, + { + "ind_access_done", + NPPU_ODMA_CFG_IND_ACCESS_DONEr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0000, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_ind_access_done_reg, + NULL, + NULL, + }, + { + "ind_command", + NPPU_ODMA_CFG_IND_COMMANDr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0004, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_nppu_odma_cfg_ind_command_reg, + NULL, + NULL, + }, + { + "ind_dat0", + NPPU_ODMA_CFG_IND_DAT0r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0008, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_ind_dat0_reg, + NULL, + NULL, + }, + { + "ind_dat1", + NPPU_ODMA_CFG_IND_DAT1r, + NPPU, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x000c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_ind_dat1_reg, + NULL, + NULL, + }, + { + "fabric_or_saip", + NPPU_ODMA_CFG_FABRIC_OR_SAIPr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0010, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_fabric_or_saip_reg, + NULL, + NULL, + }, + { + "max_pkt_len", + NPPU_ODMA_CFG_MAX_PKT_LENr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x001c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_max_pkt_len_reg, + NULL, + NULL, + }, + { + "age_en", + NPPU_ODMA_CFG_AGE_ENr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0054, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_age_en_reg, + NULL, + NULL, + }, + { + "age_mode", + NPPU_ODMA_CFG_AGE_MODEr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0058, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_age_mode_reg, + NULL, + NULL, + }, + { + "age_value_time", + NPPU_ODMA_CFG_AGE_VALUE_TIMEr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x005c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_age_value_time_reg, + NULL, + NULL, + }, + { + "age_value_room", + NPPU_ODMA_CFG_AGE_VALUE_ROOMr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0060, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_age_value_room_reg, + NULL, + NULL, + }, + { + "age_out_cnt", + NPPU_ODMA_CFG_AGE_OUT_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0064, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_age_out_cnt_reg, + NULL, + NULL, + }, + { + "token_value_a", + NPPU_ODMA_CFG_TOKEN_VALUE_Ar, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0114, + (32/8), + 0, + 59 + 1, + 0, + 4, + 1, + g_nppu_odma_cfg_token_value_a_reg, + NULL, + NULL, + }, + { + "token_value_b", + NPPU_ODMA_CFG_TOKEN_VALUE_Br, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0204, + (32/8), + 0, + 1 + 1, + 0, + 4, + 1, + g_nppu_odma_cfg_token_value_b_reg, + NULL, + NULL, + }, + { + "cfg_shap_en_p0", + NPPU_ODMA_CFG_CFG_SHAP_EN_P0r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x020c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_cfg_shap_en_p0_reg, + NULL, + NULL, + }, + { + "cfg_shap_en_p1", + NPPU_ODMA_CFG_CFG_SHAP_EN_P1r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0210, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_cfg_shap_en_p1_reg, + NULL, + NULL, + }, + { + "cfg_shap_en_tm", + NPPU_ODMA_CFG_CFG_SHAP_EN_TMr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0214, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_cfg_shap_en_tm_reg, + NULL, + NULL, + }, + { + "ind_status", + NPPU_ODMA_STAT_IND_STATUSr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_STAT_BASE_ADDR + 0x0000, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_stat_ind_status_reg, + NULL, + NULL, + }, + { + "ind_cmd", + NPPU_ODMA_STAT_IND_CMDr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_STAT_BASE_ADDR + 0x0004, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_nppu_odma_stat_ind_cmd_reg, + NULL, + NULL, + }, + { + "ind_data0", + NPPU_ODMA_STAT_IND_DATA0r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_STAT_BASE_ADDR + 0x0008, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_stat_ind_data0_reg, + NULL, + NULL, + }, + { + "debug_cnt_cfg", + NPPU_ODMA_STAT_DEBUG_CNT_CFGr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_STAT_BASE_ADDR + 0x000c, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_nppu_odma_stat_debug_cnt_cfg_reg, + NULL, + NULL, + }, + { + "bfd_firstchk_th", + NPPU_OAM_CFG_BFD_FIRSTCHK_THr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0030, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_bfd_firstchk_th_reg, + NULL, + NULL, + }, + { + "pbu_fc_idmath_ram", + NPPU_PBU_CFG_MEMID_0_PBU_FC_IDMATH_RAMr, + NPPU, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x0000, + (192/8), + 0, + 127 + 1, + 0, + 1, + 11, + g_nppu_pbu_cfg_memid_0_pbu_fc_idmath_ram_reg, + NULL, + NULL, + }, + { + "pbu_fc_macth_ram", + NPPU_PBU_CFG_MEMID_1_PBU_FC_MACTH_RAMr, + NPPU, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x0000, + (128/8), + 0, + 56 + 1, + 0, + 1, + 8, + g_nppu_pbu_cfg_memid_1_pbu_fc_macth_ram_reg, + NULL, + NULL, + }, + { + "all_kind_port_cnt", + NPPU_PBU_STAT_MEMID_1_ALL_KIND_PORT_CNTr, + NPPU, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x0000, + (32/8), + 0, + 127 + 1, + 0, + 1, + 2, + g_nppu_pbu_stat_memid_1_all_kind_port_cnt_reg, + NULL, + NULL, + }, + { + "ppu_pbu_ifb_req_vld_cnt", + NPPU_PBU_STAT_MEMID_2_PPU_PBU_IFB_REQ_VLD_CNTr, + NPPU, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0004, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_stat_memid_2_ppu_pbu_ifb_req_vld_cnt_reg, + NULL, + NULL, + }, + { + "pbu_ppu_ifb_rsp_vld_cnt", + NPPU_PBU_STAT_MEMID_2_PBU_PPU_IFB_RSP_VLD_CNTr, + NPPU, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0005, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_stat_memid_2_pbu_ppu_ifb_rsp_vld_cnt_reg, + NULL, + NULL, + }, + { + "odma_pbu_recy_ptr_vld_cnt", + NPPU_PBU_STAT_MEMID_2_ODMA_PBU_RECY_PTR_VLD_CNTr, + NPPU, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0006, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_stat_memid_2_odma_pbu_recy_ptr_vld_cnt_reg, + NULL, + NULL, + }, + { + "ppu_pbu_mcode_pf_req_cnt", + NPPU_PBU_STAT_MEMID_2_PPU_PBU_MCODE_PF_REQ_CNTr, + NPPU, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0007, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_stat_memid_2_ppu_pbu_mcode_pf_req_cnt_reg, + NULL, + NULL, + }, + { + "pbu_ppu_mcode_pf_rsp_cnt", + NPPU_PBU_STAT_MEMID_2_PBU_PPU_MCODE_PF_RSP_CNTr, + NPPU, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0008, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_stat_memid_2_pbu_ppu_mcode_pf_rsp_cnt_reg, + NULL, + NULL, + }, + { + "ppu_pbu_logic_pf_req_cnt", + NPPU_PBU_STAT_MEMID_2_PPU_PBU_LOGIC_PF_REQ_CNTr, + NPPU, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0009, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_stat_memid_2_ppu_pbu_logic_pf_req_cnt_reg, + NULL, + NULL, + }, + { + "pbu_ppu_logic_pf_rsp_cnt", + NPPU_PBU_STAT_MEMID_2_PBU_PPU_LOGIC_PF_RSP_CNTr, + NPPU, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x000a, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_stat_memid_2_pbu_ppu_logic_pf_rsp_cnt_reg, + NULL, + NULL, + }, + { + "ppu_use_ptr_pulse_cnt", + NPPU_PBU_STAT_MEMID_2_PPU_USE_PTR_PULSE_CNTr, + NPPU, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x000b, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_stat_memid_2_ppu_use_ptr_pulse_cnt_reg, + NULL, + NULL, + }, + { + "ppu_pbu_wb_vld_cnt", + NPPU_PBU_STAT_MEMID_2_PPU_PBU_WB_VLD_CNTr, + NPPU, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x000c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_stat_memid_2_ppu_pbu_wb_vld_cnt_reg, + NULL, + NULL, + }, + { + "pbu_ppu_reorder_para_vld_cnt", + NPPU_PBU_STAT_MEMID_2_PBU_PPU_REORDER_PARA_VLD_CNTr, + NPPU, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x000d, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_stat_memid_2_pbu_ppu_reorder_para_vld_cnt_reg, + NULL, + NULL, + }, + { + "se_pbu_dpi_key_vld_cnt", + NPPU_PBU_STAT_MEMID_2_SE_PBU_DPI_KEY_VLD_CNTr, + NPPU, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x000e, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_stat_memid_2_se_pbu_dpi_key_vld_cnt_reg, + NULL, + NULL, + }, + { + "pbu_se_dpi_rsp_datvld_cnt", + NPPU_PBU_STAT_MEMID_2_PBU_SE_DPI_RSP_DATVLD_CNTr, + NPPU, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x000f, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_stat_memid_2_pbu_se_dpi_rsp_datvld_cnt_reg, + NULL, + NULL, + }, + { + "odma_pbu_ifb_rd1_cnt", + NPPU_PBU_STAT_MEMID_2_ODMA_PBU_IFB_RD1_CNTr, + NPPU, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0010, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_stat_memid_2_odma_pbu_ifb_rd1_cnt_reg, + NULL, + NULL, + }, + { + "odma_pbu_ifb_rd2_cnt", + NPPU_PBU_STAT_MEMID_2_ODMA_PBU_IFB_RD2_CNTr, + NPPU, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0011, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_stat_memid_2_odma_pbu_ifb_rd2_cnt_reg, + NULL, + NULL, + }, + { + "pbu_ppu_mcode_pf_no_rsp_cnt", + NPPU_PBU_STAT_MEMID_2_PBU_PPU_MCODE_PF_NO_RSP_CNTr, + NPPU, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0015, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_stat_memid_2_pbu_ppu_mcode_pf_no_rsp_cnt_reg, + NULL, + NULL, + }, + { + "pbu_ppu_logic_pf_no_rsp_cnt", + NPPU_PBU_STAT_MEMID_2_PBU_PPU_LOGIC_PF_NO_RSP_CNTr, + NPPU, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0016, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_stat_memid_2_pbu_ppu_logic_pf_no_rsp_cnt_reg, + NULL, + NULL, + }, + { + "cpu_rd_ifb_data", + NPPU_PBU_STAT_MEMID_3_CPU_RD_IFB_DATAr, + NPPU, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x0000, + (2048/8), + 0, + 16383 + 1, + 0, + 1, + 1, + g_nppu_pbu_stat_memid_3_cpu_rd_ifb_data_reg, + NULL, + NULL, + }, + { + "mux_sel_rgt", + NPPU_PBU_STAT_MEMID_4_MUX_SEL_RGTr, + NPPU, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0000, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_stat_memid_4_mux_sel_rgt_reg, + NULL, + NULL, + }, + { + "port_pub_cnt", + NPPU_PBU_STAT_MEMID_5_PORT_PUB_CNTr, + NPPU, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x0000, + (32/8), + 0, + 127 + 1, + 0, + 1, + 1, + g_nppu_pbu_stat_memid_5_port_pub_cnt_reg, + NULL, + NULL, + }, + { + "idma_o_isu_pkt_pulse_total_cnt", + NPPU_IDMA_STAT_MEMID_1_IDMA_O_ISU_PKT_PULSE_TOTAL_CNTr, + NPPU, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0012, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_idma_stat_memid_1_idma_o_isu_pkt_pulse_total_cnt_reg, + NULL, + NULL, + }, + { + "idma_o_isu_epkt_pulse_total_cnt", + NPPU_IDMA_STAT_MEMID_1_IDMA_O_ISU_EPKT_PULSE_TOTAL_CNTr, + NPPU, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0013, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_idma_stat_memid_1_idma_o_isu_epkt_pulse_total_cnt_reg, + NULL, + NULL, + }, + { + "idma_dispkt_pulse_total_cnt", + NPPU_IDMA_STAT_MEMID_1_IDMA_DISPKT_PULSE_TOTAL_CNTr, + NPPU, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0014, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_idma_stat_memid_1_idma_dispkt_pulse_total_cnt_reg, + NULL, + NULL, + }, + { + "idma_o_isu_pkt_pulse_cnt", + NPPU_IDMA_STAT_MEMID_0_IDMA_O_ISU_PKT_PULSE_CNTr, + NPPU, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x0000, + (32/8), + 0, + 127 + 1, + 0, + 1, + 1, + g_nppu_idma_stat_memid_0_idma_o_isu_pkt_pulse_cnt_reg, + NULL, + NULL, + }, + { + "idma_o_isu_epkt_pulse_cnt", + NPPU_IDMA_STAT_MEMID_0_IDMA_O_ISU_EPKT_PULSE_CNTr, + NPPU, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x0080, + (32/8), + 0, + 127 + 1, + 0, + 1, + 1, + g_nppu_idma_stat_memid_0_idma_o_isu_epkt_pulse_cnt_reg, + NULL, + NULL, + }, + { + "idma_dispkt_pulse_cnt", + NPPU_IDMA_STAT_MEMID_0_IDMA_DISPKT_PULSE_CNTr, + NPPU, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x0100, + (32/8), + 0, + 127 + 1, + 0, + 1, + 1, + g_nppu_idma_stat_memid_0_idma_dispkt_pulse_cnt_reg, + NULL, + NULL, + }, + { + "test_r", + PPU_PPU_TEST_Rr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x000, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_test_r_reg, + NULL, + NULL, + }, + { + "ppu_debug_en_r", + PPU_PPU_PPU_DEBUG_EN_Rr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x00c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_debug_en_r_reg, + NULL, + NULL, + }, + { + "csr_dup_table_wr_data", + PPU_PPU_CSR_DUP_TABLE_WR_DATAr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x034, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_ppu_ppu_csr_dup_table_wr_data_reg, + NULL, + NULL, + }, + { + "csr_dup_table_rd_data", + PPU_PPU_CSR_DUP_TABLE_RD_DATAr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x038, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_ppu_ppu_csr_dup_table_rd_data_reg, + NULL, + NULL, + }, + { + "csr_dup_table_addr", + PPU_PPU_CSR_DUP_TABLE_ADDRr, + PPU, + DPP_REG_FLAG_WO | DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x03c, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_ppu_ppu_csr_dup_table_addr_reg, + NULL, + NULL, + }, + { + "ppu_debug_vld", + PPU_PPU_PPU_DEBUG_VLDr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x048, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_debug_vld_reg, + NULL, + NULL, + }, + { + "cop_thash_rsk_319_288", + PPU_PPU_COP_THASH_RSK_319_288r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x050, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_cop_thash_rsk_319_288_reg, + NULL, + NULL, + }, + { + "cop_thash_rsk_287_256", + PPU_PPU_COP_THASH_RSK_287_256r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x054, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_cop_thash_rsk_287_256_reg, + NULL, + NULL, + }, + { + "cop_thash_rsk_255_224", + PPU_PPU_COP_THASH_RSK_255_224r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x058, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_cop_thash_rsk_255_224_reg, + NULL, + NULL, + }, + { + "cop_thash_rsk_223_192", + PPU_PPU_COP_THASH_RSK_223_192r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x05c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_cop_thash_rsk_223_192_reg, + NULL, + NULL, + }, + { + "cop_thash_rsk_191_160", + PPU_PPU_COP_THASH_RSK_191_160r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x060, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_cop_thash_rsk_191_160_reg, + NULL, + NULL, + }, + { + "cop_thash_rsk_159_128", + PPU_PPU_COP_THASH_RSK_159_128r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x064, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_cop_thash_rsk_159_128_reg, + NULL, + NULL, + }, + { + "cop_thash_rsk_127_096", + PPU_PPU_COP_THASH_RSK_127_096r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x068, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_cop_thash_rsk_127_096_reg, + NULL, + NULL, + }, + { + "cop_thash_rsk_095_064", + PPU_PPU_COP_THASH_RSK_095_064r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x06c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_cop_thash_rsk_095_064_reg, + NULL, + NULL, + }, + { + "cop_thash_rsk_063_032", + PPU_PPU_COP_THASH_RSK_063_032r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x070, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_cop_thash_rsk_063_032_reg, + NULL, + NULL, + }, + { + "cop_thash_rsk_031_000", + PPU_PPU_COP_THASH_RSK_031_000r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x074, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_cop_thash_rsk_031_000_reg, + NULL, + NULL, + }, + { + "cfg_ipv4_ipid_start_value", + PPU_PPU_CFG_IPV4_IPID_START_VALUEr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x078, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_cfg_ipv4_ipid_start_value_reg, + NULL, + NULL, + }, + { + "cfg_ipv4_ipid_end_value", + PPU_PPU_CFG_IPV4_IPID_END_VALUEr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x07c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_cfg_ipv4_ipid_end_value_reg, + NULL, + NULL, + }, + { + "cluster_mf_in_en", + PPU_PPU_CLUSTER_MF_IN_ENr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x150, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_cluster_mf_in_en_reg, + NULL, + NULL, + }, + { + "ppu_empty", + PPU_PPU_PPU_EMPTYr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x154, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_empty_reg, + NULL, + NULL, + }, + { + "instrmem_w_addr", + PPU_PPU_INSTRMEM_W_ADDRr, + PPU, + DPP_REG_FLAG_WO | DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x514, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_instrmem_w_addr_reg, + NULL, + NULL, + }, + { + "instrmem_w_data_191_160", + PPU_PPU_INSTRMEM_W_DATA_191_160r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x518, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_instrmem_w_data_191_160_reg, + NULL, + NULL, + }, + { + "instrmem_w_data_159_128", + PPU_PPU_INSTRMEM_W_DATA_159_128r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x51c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_instrmem_w_data_159_128_reg, + NULL, + NULL, + }, + { + "instrmem_w_data_127_96", + PPU_PPU_INSTRMEM_W_DATA_127_96r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x520, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_instrmem_w_data_127_96_reg, + NULL, + NULL, + }, + { + "instrmem_w_data_95_64", + PPU_PPU_INSTRMEM_W_DATA_95_64r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x524, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_instrmem_w_data_95_64_reg, + NULL, + NULL, + }, + { + "instrmem_w_data_63_32", + PPU_PPU_INSTRMEM_W_DATA_63_32r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x528, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_instrmem_w_data_63_32_reg, + NULL, + NULL, + }, + { + "instrmem_w_data_31_0", + PPU_PPU_INSTRMEM_W_DATA_31_0r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x52c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_instrmem_w_data_31_0_reg, + NULL, + NULL, + }, + { + "isu_fwft_mf_fifo_prog_full_assert_cfg", + PPU_PPU_ISU_FWFT_MF_FIFO_PROG_FULL_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5f0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_isu_fwft_mf_fifo_prog_full_assert_cfg_reg, + NULL, + NULL, + }, + { + "isu_fwft_mf_fifo_prog_full_negate_cfg", + PPU_PPU_ISU_FWFT_MF_FIFO_PROG_FULL_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5f4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_isu_fwft_mf_fifo_prog_full_negate_cfg_reg, + NULL, + NULL, + }, + { + "int_1200m_mask", + PPU_CLUSTER_INT_1200M_MASKr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x98, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 8, + g_ppu_cluster_int_1200m_mask_reg, + NULL, + NULL, + }, + { + "wr_high_data_r_mex", + PPU4K_CLUSTER_WR_HIGH_DATA_R_MEXr, + PPU4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4000, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu4k_cluster_wr_high_data_r_mex_reg, + dpp_ppu_write, + dpp_ppu_read, + }, + { + "wr_low_data_r_mex", + PPU4K_CLUSTER_WR_LOW_DATA_R_MEXr, + PPU4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4004, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu4k_cluster_wr_low_data_r_mex_reg, + dpp_ppu_write, + dpp_ppu_read, + }, + { + "addr_r_mex", + PPU4K_CLUSTER_ADDR_R_MEXr, + PPU4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4008, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 2, + g_ppu4k_cluster_addr_r_mex_reg, + dpp_ppu_write, + dpp_ppu_read, + }, + { + "sdt_tbl_ind_access_done", + PPU4K_CLUSTER_SDT_TBL_IND_ACCESS_DONEr, + PPU4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x400c, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu4k_cluster_sdt_tbl_ind_access_done_reg, + dpp_ppu_write, + dpp_ppu_read, + }, + { + "rd_high_data_r_mex", + PPU4K_CLUSTER_RD_HIGH_DATA_R_MEXr, + PPU4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4010, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu4k_cluster_rd_high_data_r_mex_reg, + dpp_ppu_write, + dpp_ppu_read, + }, + { + "rd_low_data_r_mex", + PPU4K_CLUSTER_RD_LOW_DATA_R_MEXr, + PPU4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4014, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu4k_cluster_rd_low_data_r_mex_reg, + dpp_ppu_write, + dpp_ppu_read, + }, + { + "init_ok", + SE_ALG_INIT_OKr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0000, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_init_ok_reg, + NULL, + NULL, + }, + { + "cpu_rd_rdy", + SE_ALG_CPU_RD_RDYr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0048, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_cpu_rd_rdy_reg, + NULL, + NULL, + }, + { + "cpu_rd_data_tmp0", + SE_ALG_CPU_RD_DATA_TMP0r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x004c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_cpu_rd_data_tmp0_reg, + NULL, + NULL, + }, + { + "cpu_rd_data_tmp1", + SE_ALG_CPU_RD_DATA_TMP1r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0050, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_cpu_rd_data_tmp1_reg, + NULL, + NULL, + }, + { + "cpu_rd_data_tmp2", + SE_ALG_CPU_RD_DATA_TMP2r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0054, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_cpu_rd_data_tmp2_reg, + NULL, + NULL, + }, + { + "cpu_rd_data_tmp3", + SE_ALG_CPU_RD_DATA_TMP3r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0058, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_cpu_rd_data_tmp3_reg, + NULL, + NULL, + }, + { + "cpu_rd_data_tmp4", + SE_ALG_CPU_RD_DATA_TMP4r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x005c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_cpu_rd_data_tmp4_reg, + NULL, + NULL, + }, + { + "cpu_rd_data_tmp5", + SE_ALG_CPU_RD_DATA_TMP5r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0060, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_cpu_rd_data_tmp5_reg, + NULL, + NULL, + }, + { + "cpu_rd_data_tmp6", + SE_ALG_CPU_RD_DATA_TMP6r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0064, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_cpu_rd_data_tmp6_reg, + NULL, + NULL, + }, + { + "cpu_rd_data_tmp7", + SE_ALG_CPU_RD_DATA_TMP7r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0068, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_cpu_rd_data_tmp7_reg, + NULL, + NULL, + }, + { + "cpu_rd_data_tmp8", + SE_ALG_CPU_RD_DATA_TMP8r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x006c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_cpu_rd_data_tmp8_reg, + NULL, + NULL, + }, + { + "cpu_rd_data_tmp9", + SE_ALG_CPU_RD_DATA_TMP9r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0070, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_cpu_rd_data_tmp9_reg, + NULL, + NULL, + }, + { + "cpu_rd_data_tmp10", + SE_ALG_CPU_RD_DATA_TMP10r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0074, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_cpu_rd_data_tmp10_reg, + NULL, + NULL, + }, + { + "cpu_rd_data_tmp11", + SE_ALG_CPU_RD_DATA_TMP11r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0078, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_cpu_rd_data_tmp11_reg, + NULL, + NULL, + }, + { + "cpu_rd_data_tmp12", + SE_ALG_CPU_RD_DATA_TMP12r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x007c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_cpu_rd_data_tmp12_reg, + NULL, + NULL, + }, + { + "cpu_rd_data_tmp13", + SE_ALG_CPU_RD_DATA_TMP13r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0080, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_cpu_rd_data_tmp13_reg, + NULL, + NULL, + }, + { + "cpu_rd_data_tmp14", + SE_ALG_CPU_RD_DATA_TMP14r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0084, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_cpu_rd_data_tmp14_reg, + NULL, + NULL, + }, + { + "cpu_rd_data_tmp15", + SE_ALG_CPU_RD_DATA_TMP15r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0088, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_cpu_rd_data_tmp15_reg, + NULL, + NULL, + }, + { + "lpm_v4_config_rgt", + SE_ALG_LPM_V4_CONFIG_RGTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x014c, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_se_alg_lpm_v4_config_rgt_reg, + NULL, + NULL, + }, + { + "lpm_v6_config_rgt", + SE_ALG_LPM_V6_CONFIG_RGTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0150, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_se_alg_lpm_v6_config_rgt_reg, + NULL, + NULL, + }, + { + "lpm_ext_rsp_fifo_u0_pfull_ast", + SE_ALG_LPM_EXT_RSP_FIFO_U0_PFULL_ASTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x015c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_lpm_ext_rsp_fifo_u0_pfull_ast_reg, + NULL, + NULL, + }, + { + "hash_age_pat_cfg", + SE_AS_HASH_AGE_PAT_CFGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000001d8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_as_hash_age_pat_cfg_reg, + NULL, + NULL, + }, + { + "learn_rdy_cfg", + SE_AS_LEARN_RDY_CFGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000001f8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_as_learn_rdy_cfg_reg, + NULL, + NULL, + }, + { + "kschd_as_pful_cfg", + SE_KSCHD_KSCHD_AS_PFUL_CFGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000008, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_kschd_kschd_as_pful_cfg_reg, + NULL, + NULL, + }, + { + "kschd_dir_pful_cfg", + SE_KSCHD_KSCHD_DIR_PFUL_CFGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x0000000c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_kschd_kschd_dir_pful_cfg_reg, + NULL, + NULL, + }, + { + "kschd_as_ept_cfg", + SE_KSCHD_KSCHD_AS_EPT_CFGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000000014, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_kschd_kschd_as_ept_cfg_reg, + NULL, + NULL, + }, + { + "cpu_arbi_pful_cfg", + SE_KSCHD_CPU_ARBI_PFUL_CFGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x0000001c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_kschd_cpu_arbi_pful_cfg_reg, + NULL, + NULL, + }, + { + "kschd_pbu_pful_cfg", + SE_KSCHD_KSCHD_PBU_PFUL_CFGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000020, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_kschd_kschd_pbu_pful_cfg_reg, + NULL, + NULL, + }, + { + "rschd_dir_pful_cfg", + SE_RSCHD_RSCHD_DIR_PFUL_CFGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000030, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_rschd_rschd_dir_pful_cfg_reg, + NULL, + NULL, + }, + { + "rschd_dir_ept_cfg", + SE_RSCHD_RSCHD_DIR_EPT_CFGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000034, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_rschd_rschd_dir_ept_cfg_reg, + NULL, + NULL, + }, + { + "cpu_cmd_rgt", + SE4K_SE_ALG_CPU_CMD_RGTr, + SE4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0004, + (32/8), + 0, + 0, + 0, + 0, + 7, + g_se4k_se_alg_cpu_cmd_rgt_reg, + dpp_se_write, + dpp_se_read, + }, + { + "cpu_wr_data_tmp0", + SE4K_SE_ALG_CPU_WR_DATA_TMP0r, + SE4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0008, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se4k_se_alg_cpu_wr_data_tmp0_reg, + dpp_se_write, + dpp_se_read, + }, + { + "cpu_wr_data_tmp1", + SE4K_SE_ALG_CPU_WR_DATA_TMP1r, + SE4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x000c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se4k_se_alg_cpu_wr_data_tmp1_reg, + dpp_se_write, + dpp_se_read, + }, + { + "cpu_wr_data_tmp2", + SE4K_SE_ALG_CPU_WR_DATA_TMP2r, + SE4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0010, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se4k_se_alg_cpu_wr_data_tmp2_reg, + dpp_se_write, + dpp_se_read, + }, + { + "cpu_wr_data_tmp3", + SE4K_SE_ALG_CPU_WR_DATA_TMP3r, + SE4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0014, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se4k_se_alg_cpu_wr_data_tmp3_reg, + dpp_se_write, + dpp_se_read, + }, + { + "cpu_wr_data_tmp4", + SE4K_SE_ALG_CPU_WR_DATA_TMP4r, + SE4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0018, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se4k_se_alg_cpu_wr_data_tmp4_reg, + dpp_se_write, + dpp_se_read, + }, + { + "cpu_wr_data_tmp5", + SE4K_SE_ALG_CPU_WR_DATA_TMP5r, + SE4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x001c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se4k_se_alg_cpu_wr_data_tmp5_reg, + dpp_se_write, + dpp_se_read, + }, + { + "cpu_wr_data_tmp6", + SE4K_SE_ALG_CPU_WR_DATA_TMP6r, + SE4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0020, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se4k_se_alg_cpu_wr_data_tmp6_reg, + dpp_se_write, + dpp_se_read, + }, + { + "cpu_wr_data_tmp7", + SE4K_SE_ALG_CPU_WR_DATA_TMP7r, + SE4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0024, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se4k_se_alg_cpu_wr_data_tmp7_reg, + dpp_se_write, + dpp_se_read, + }, + { + "cpu_wr_data_tmp8", + SE4K_SE_ALG_CPU_WR_DATA_TMP8r, + SE4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0028, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se4k_se_alg_cpu_wr_data_tmp8_reg, + dpp_se_write, + dpp_se_read, + }, + { + "cpu_wr_data_tmp9", + SE4K_SE_ALG_CPU_WR_DATA_TMP9r, + SE4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x002c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se4k_se_alg_cpu_wr_data_tmp9_reg, + dpp_se_write, + dpp_se_read, + }, + { + "cpu_wr_data_tmp10", + SE4K_SE_ALG_CPU_WR_DATA_TMP10r, + SE4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0030, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se4k_se_alg_cpu_wr_data_tmp10_reg, + dpp_se_write, + dpp_se_read, + }, + { + "cpu_wr_data_tmp11", + SE4K_SE_ALG_CPU_WR_DATA_TMP11r, + SE4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0034, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se4k_se_alg_cpu_wr_data_tmp11_reg, + dpp_se_write, + dpp_se_read, + }, + { + "cpu_wr_data_tmp12", + SE4K_SE_ALG_CPU_WR_DATA_TMP12r, + SE4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0038, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se4k_se_alg_cpu_wr_data_tmp12_reg, + dpp_se_write, + dpp_se_read, + }, + { + "cpu_wr_data_tmp13", + SE4K_SE_ALG_CPU_WR_DATA_TMP13r, + SE4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x003c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se4k_se_alg_cpu_wr_data_tmp13_reg, + dpp_se_write, + dpp_se_read, + }, + { + "cpu_wr_data_tmp14", + SE4K_SE_ALG_CPU_WR_DATA_TMP14r, + SE4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0040, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se4k_se_alg_cpu_wr_data_tmp14_reg, + dpp_se_write, + dpp_se_read, + }, + { + "cpu_wr_data_tmp15", + SE4K_SE_ALG_CPU_WR_DATA_TMP15r, + SE4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0044, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se4k_se_alg_cpu_wr_data_tmp15_reg, + dpp_se_write, + dpp_se_read, + }, + { + "cpu_rd_rdy", + SE4K_SE_ALG_CPU_RD_RDYr, + SE4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0048, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se4k_se_alg_cpu_rd_rdy_reg, + dpp_se_write, + dpp_se_read, + }, + { + "cpu_rd_data_tmp0", + SE4K_SE_ALG_CPU_RD_DATA_TMP0r, + SE4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x004c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se4k_se_alg_cpu_rd_data_tmp0_reg, + dpp_se_write, + dpp_se_read, + }, + { + "cpu_rd_data_tmp1", + SE4K_SE_ALG_CPU_RD_DATA_TMP1r, + SE4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0050, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se4k_se_alg_cpu_rd_data_tmp1_reg, + dpp_se_write, + dpp_se_read, + }, + { + "cpu_rd_data_tmp2", + SE4K_SE_ALG_CPU_RD_DATA_TMP2r, + SE4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0054, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se4k_se_alg_cpu_rd_data_tmp2_reg, + dpp_se_write, + dpp_se_read, + }, + { + "cpu_rd_data_tmp3", + SE4K_SE_ALG_CPU_RD_DATA_TMP3r, + SE4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0058, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se4k_se_alg_cpu_rd_data_tmp3_reg, + dpp_se_write, + dpp_se_read, + }, + { + "cpu_rd_data_tmp4", + SE4K_SE_ALG_CPU_RD_DATA_TMP4r, + SE4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x005c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se4k_se_alg_cpu_rd_data_tmp4_reg, + dpp_se_write, + dpp_se_read, + }, + { + "cpu_rd_data_tmp5", + SE4K_SE_ALG_CPU_RD_DATA_TMP5r, + SE4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0060, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se4k_se_alg_cpu_rd_data_tmp5_reg, + dpp_se_write, + dpp_se_read, + }, + { + "cpu_rd_data_tmp6", + SE4K_SE_ALG_CPU_RD_DATA_TMP6r, + SE4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0064, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se4k_se_alg_cpu_rd_data_tmp6_reg, + dpp_se_write, + dpp_se_read, + }, + { + "cpu_rd_data_tmp7", + SE4K_SE_ALG_CPU_RD_DATA_TMP7r, + SE4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0068, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se4k_se_alg_cpu_rd_data_tmp7_reg, + dpp_se_write, + dpp_se_read, + }, + { + "cpu_rd_data_tmp8", + SE4K_SE_ALG_CPU_RD_DATA_TMP8r, + SE4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x006c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se4k_se_alg_cpu_rd_data_tmp8_reg, + dpp_se_write, + dpp_se_read, + }, + { + "cpu_rd_data_tmp9", + SE4K_SE_ALG_CPU_RD_DATA_TMP9r, + SE4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0070, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se4k_se_alg_cpu_rd_data_tmp9_reg, + dpp_se_write, + dpp_se_read, + }, + { + "cpu_rd_data_tmp10", + SE4K_SE_ALG_CPU_RD_DATA_TMP10r, + SE4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0074, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se4k_se_alg_cpu_rd_data_tmp10_reg, + dpp_se_write, + dpp_se_read, + }, + { + "cpu_rd_data_tmp11", + SE4K_SE_ALG_CPU_RD_DATA_TMP11r, + SE4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0078, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se4k_se_alg_cpu_rd_data_tmp11_reg, + dpp_se_write, + dpp_se_read, + }, + { + "cpu_rd_data_tmp12", + SE4K_SE_ALG_CPU_RD_DATA_TMP12r, + SE4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x007c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se4k_se_alg_cpu_rd_data_tmp12_reg, + dpp_se_write, + dpp_se_read, + }, + { + "cpu_rd_data_tmp13", + SE4K_SE_ALG_CPU_RD_DATA_TMP13r, + SE4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0080, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se4k_se_alg_cpu_rd_data_tmp13_reg, + dpp_se_write, + dpp_se_read, + }, + { + "cpu_rd_data_tmp14", + SE4K_SE_ALG_CPU_RD_DATA_TMP14r, + SE4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0084, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se4k_se_alg_cpu_rd_data_tmp14_reg, + dpp_se_write, + dpp_se_read, + }, + { + "cpu_rd_data_tmp15", + SE4K_SE_ALG_CPU_RD_DATA_TMP15r, + SE4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0088, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se4k_se_alg_cpu_rd_data_tmp15_reg, + dpp_se_write, + dpp_se_read, + }, + { + "hash0_ext_cfg_rgt", + SE4K_SE_ALG_HASH0_EXT_CFG_RGTr, + SE4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0bc, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_se4k_se_alg_hash0_ext_cfg_rgt_reg, + dpp_se_write, + dpp_se_read, + }, + { + "hash1_ext_cfg_rgt", + SE4K_SE_ALG_HASH1_EXT_CFG_RGTr, + SE4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0c0, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_se4k_se_alg_hash1_ext_cfg_rgt_reg, + dpp_se_write, + dpp_se_read, + }, + { + "hash2_ext_cfg_rgt", + SE4K_SE_ALG_HASH2_EXT_CFG_RGTr, + SE4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0c4, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_se4k_se_alg_hash2_ext_cfg_rgt_reg, + dpp_se_write, + dpp_se_read, + }, + { + "hash3_ext_cfg_rgt", + SE4K_SE_ALG_HASH3_EXT_CFG_RGTr, + SE4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0c8, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_se4k_se_alg_hash3_ext_cfg_rgt_reg, + dpp_se_write, + dpp_se_read, + }, + { + "hash0_tbl30_depth", + SE4K_SE_ALG_HASH0_TBL30_DEPTHr, + SE4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x01a4, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_se4k_se_alg_hash0_tbl30_depth_reg, + dpp_se_write, + dpp_se_read, + }, + { + "hash0_tbl74_depth", + SE4K_SE_ALG_HASH0_TBL74_DEPTHr, + SE4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x01a8, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_se4k_se_alg_hash0_tbl74_depth_reg, + dpp_se_write, + dpp_se_read, + }, + { + "hash1_tbl30_depth", + SE4K_SE_ALG_HASH1_TBL30_DEPTHr, + SE4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x01ac, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_se4k_se_alg_hash1_tbl30_depth_reg, + dpp_se_write, + dpp_se_read, + }, + { + "hash1_tbl74_depth", + SE4K_SE_ALG_HASH1_TBL74_DEPTHr, + SE4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x01b0, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_se4k_se_alg_hash1_tbl74_depth_reg, + dpp_se_write, + dpp_se_read, + }, + { + "hash2_tbl30_depth", + SE4K_SE_ALG_HASH2_TBL30_DEPTHr, + SE4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x01b4, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_se4k_se_alg_hash2_tbl30_depth_reg, + dpp_se_write, + dpp_se_read, + }, + { + "hash2_tbl74_depth", + SE4K_SE_ALG_HASH2_TBL74_DEPTHr, + SE4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x01b8, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_se4k_se_alg_hash2_tbl74_depth_reg, + dpp_se_write, + dpp_se_read, + }, + { + "hash3_tbl30_depth", + SE4K_SE_ALG_HASH3_TBL30_DEPTHr, + SE4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x01bc, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_se4k_se_alg_hash3_tbl30_depth_reg, + dpp_se_write, + dpp_se_read, + }, + { + "hash3_tbl74_depth", + SE4K_SE_ALG_HASH3_TBL74_DEPTHr, + SE4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x01c0, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_se4k_se_alg_hash3_tbl74_depth_reg, + dpp_se_write, + dpp_se_read, + }, + { + "wr_rsp_cfg", + SE4K_SE_ALG_WR_RSP_CFGr, + SE4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x01c4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se4k_se_alg_wr_rsp_cfg_reg, + dpp_se_write, + dpp_se_read, + }, + { + "hash_mono_flag", + SE4K_SE_ALG_HASH_MONO_FLAGr, + SE4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x01c8, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_se4k_se_alg_hash_mono_flag_reg, + dpp_se_write, + dpp_se_read, + }, + { + "hash10_ext_crc_cfg", + SE4K_SE_ALG_HASH10_EXT_CRC_CFGr, + SE4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x01cc, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_se4k_se_alg_hash10_ext_crc_cfg_reg, + dpp_se_write, + dpp_se_read, + }, + { + "hash32_ext_crc_cfg", + SE4K_SE_ALG_HASH32_EXT_CRC_CFGr, + SE4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x01d0, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_se4k_se_alg_hash32_ext_crc_cfg_reg, + dpp_se_write, + dpp_se_read, + }, + { + "zblock_service_configure", + SE4K_SE_ALG_ZBLOCK_SERVICE_CONFIGUREr, + SE4K, + DPP_REG_FLAG_INDIRECT, + DPP_REG_BIN_ARRAY, + 0x10000, + (512/8), + 3 + 1, + 7 + 1, + 0x4000, + 0x800, + 3, + g_se4k_se_alg_zblock_service_configure_reg, + dpp_se_alg_write, + dpp_se_alg_read, + }, + { + "zblock_hash_zcell_mono", + SE4K_SE_ALG_ZBLOCK_HASH_ZCELL_MONOr, + SE4K, + DPP_REG_FLAG_INDIRECT, + DPP_REG_BIN_ARRAY, + 0x10014, + (512/8), + 3 + 1, + 7 + 1, + 0x4000, + 0x800, + 8, + g_se4k_se_alg_zblock_hash_zcell_mono_reg, + dpp_se_alg_write, + dpp_se_alg_read, + }, + { + "zlock_hash_zreg_mono", + SE4K_SE_ALG_ZLOCK_HASH_ZREG_MONOr, + SE4K, + DPP_REG_FLAG_INDIRECT, + DPP_REG_BIN_ARRAY, + 0x10015, + (512/8), + 3 + 1, + 7 + 1, + 0x4000, + 0x800, + 8, + g_se4k_se_alg_zlock_hash_zreg_mono_reg, + dpp_se_alg_write, + dpp_se_alg_read, + }, + { + "init_done", + SMMU0_SMMU0_INIT_DONEr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000000, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_init_done_reg, + NULL, + NULL, + }, + { + "cpu_ind_wdat0", + SMMU0_SMMU0_CPU_IND_WDAT0r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000004, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_cpu_ind_wdat0_reg, + NULL, + NULL, + }, + { + "cpu_ind_wdat1", + SMMU0_SMMU0_CPU_IND_WDAT1r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000008, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_cpu_ind_wdat1_reg, + NULL, + NULL, + }, + { + "cpu_ind_wdat2", + SMMU0_SMMU0_CPU_IND_WDAT2r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000000c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_cpu_ind_wdat2_reg, + NULL, + NULL, + }, + { + "cpu_ind_wdat3", + SMMU0_SMMU0_CPU_IND_WDAT3r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000010, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_cpu_ind_wdat3_reg, + NULL, + NULL, + }, + { + "cpu_ind_cmd", + SMMU0_SMMU0_CPU_IND_CMDr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000014, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_smmu0_smmu0_cpu_ind_cmd_reg, + NULL, + NULL, + }, + { + "cpu_ind_rd_done", + SMMU0_SMMU0_CPU_IND_RD_DONEr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000040, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_cpu_ind_rd_done_reg, + NULL, + NULL, + }, + { + "cpu_ind_rdat0", + SMMU0_SMMU0_CPU_IND_RDAT0r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000044, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_cpu_ind_rdat0_reg, + NULL, + NULL, + }, + { + "cpu_ind_rdat1", + SMMU0_SMMU0_CPU_IND_RDAT1r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000048, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_cpu_ind_rdat1_reg, + NULL, + NULL, + }, + { + "cpu_ind_rdat2", + SMMU0_SMMU0_CPU_IND_RDAT2r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000004c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_cpu_ind_rdat2_reg, + NULL, + NULL, + }, + { + "cpu_ind_rdat3", + SMMU0_SMMU0_CPU_IND_RDAT3r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000050, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_cpu_ind_rdat3_reg, + NULL, + NULL, + }, + { + "cfg_plcr_mono", + SMMU0_SMMU0_CFG_PLCR_MONOr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000108, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_cfg_plcr_mono_reg, + NULL, + NULL, + }, + { + "wr_arb_cpu_rdy", + SMMU0_SMMU0_WR_ARB_CPU_RDYr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000010c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_wr_arb_cpu_rdy_reg, + NULL, + NULL, + }, + { + "tm_stat_en_cfg", + SMMU0_SMMU0_TM_STAT_EN_CFGr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000110, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_tm_stat_en_cfg_reg, + NULL, + NULL, + }, + { + "ddr_wdat0", + SE_SMMU1_DDR_WDAT0r, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000000, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_ddr_wdat0_reg, + NULL, + NULL, + }, + { + "dir_arbi_ser_rpful", + SE_SMMU1_DIR_ARBI_SER_RPFULr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000010c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_dir_arbi_ser_rpful_reg, + NULL, + NULL, + }, + { + "cfg_wr_arbi_pful2", + SE_SMMU1_CFG_WR_ARBI_PFUL2r, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000120, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_se_smmu1_cfg_wr_arbi_pful2_reg, + NULL, + NULL, + }, + { + "etm_tbl_cfg", + SE_SMMU1_ETM_TBL_CFGr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001cc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_etm_tbl_cfg_reg, + NULL, + NULL, + }, + { + "cfg_cash_addr_pful", + SE_SMMU1_CFG_CASH_ADDR_PFULr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000020c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_cfg_cash_addr_pful_reg, + NULL, + NULL, + }, + { + "ctrl_rfifo_cfg", + SE_SMMU1_CTRL_RFIFO_CFGr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000234, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_se_smmu1_ctrl_rfifo_cfg_reg, + NULL, + NULL, + }, + { + "cache_req_fifo_cfg", + SE_SMMU1_CACHE_REQ_FIFO_CFGr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000288, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_se_smmu1_cache_req_fifo_cfg_reg, + NULL, + NULL, + }, + { + "cpu_ind_eram_wdat0", + STAT_STAT_CFG_CPU_IND_ERAM_WDAT0r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000000, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_cpu_ind_eram_wdat0_reg, + NULL, + NULL, + }, + { + "etm_port_sel_cfg", + STAT_STAT_CFG_ETM_PORT_SEL_CFGr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000044, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_stat_stat_cfg_etm_port_sel_cfg_reg, + NULL, + NULL, + }, + { + "tm_stat_cfg", + STAT_STAT_CFG_TM_STAT_CFGr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000004c, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_stat_stat_cfg_tm_stat_cfg_reg, + NULL, + NULL, + }, + { + "ppu_eram_depth", + STAT_STAT_CFG_PPU_ERAM_DEPTHr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000050, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_ppu_eram_depth_reg, + NULL, + NULL, + }, + { + "ppu_eram_base_addr", + STAT_STAT_CFG_PPU_ERAM_BASE_ADDRr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000054, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_ppu_eram_base_addr_reg, + NULL, + NULL, + }, + { + "ppu_ddr_base_addr", + STAT_STAT_CFG_PPU_DDR_BASE_ADDRr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000060, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_ppu_ddr_base_addr_reg, + NULL, + NULL, + }, + { + "plcr0_base_addr", + STAT_STAT_CFG_PLCR0_BASE_ADDRr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000006c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_plcr0_base_addr_reg, + NULL, + NULL, + }, + { + "etm_stat_start_addr_cfg", + STAT_STAT_CFG_ETM_STAT_START_ADDR_CFGr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000e0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_etm_stat_start_addr_cfg_reg, + NULL, + NULL, + }, + { + "etm_stat_depth_cfg", + STAT_STAT_CFG_ETM_STAT_DEPTH_CFGr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000e4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_etm_stat_depth_cfg_reg, + NULL, + NULL, + }, + { + "cycle_mov_en_cfg", + STAT_STAT_CFG_CYCLE_MOV_EN_CFGr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000e8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_cycle_mov_en_cfg_reg, + NULL, + NULL, + }, + { + "cpu_ind_wdat0", + STAT_ETCAM_CPU_IND_WDAT0r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000004, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_etcam_cpu_ind_wdat0_reg, + NULL, + NULL, + }, + { + "cpu_ind_ctrl_tmp0", + STAT_ETCAM_CPU_IND_CTRL_TMP0r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000054, + (32/8), + 0, + 0, + 0, + 0, + 7, + g_stat_etcam_cpu_ind_ctrl_tmp0_reg, + NULL, + NULL, + }, + { + "cpu_ind_ctrl_tmp1", + STAT_ETCAM_CPU_IND_CTRL_TMP1r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000058, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_stat_etcam_cpu_ind_ctrl_tmp1_reg, + NULL, + NULL, + }, + { + "cpu_ind_rd_done", + STAT_ETCAM_CPU_IND_RD_DONEr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x000001fc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_etcam_cpu_ind_rd_done_reg, + NULL, + NULL, + }, + { + "cpu_rdat0", + STAT_ETCAM_CPU_RDAT0r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000200, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_etcam_cpu_rdat0_reg, + NULL, + NULL, + }, + { + "cpu_rdat1", + STAT_ETCAM_CPU_RDAT1r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000204, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_etcam_cpu_rdat1_reg, + NULL, + NULL, + }, + { + "cpu_rdat2", + STAT_ETCAM_CPU_RDAT2r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000208, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_etcam_cpu_rdat2_reg, + NULL, + NULL, + }, + { + "cpu_rdat3", + STAT_ETCAM_CPU_RDAT3r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x0000020c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_etcam_cpu_rdat3_reg, + NULL, + NULL, + }, + { + "cpu_rdat4", + STAT_ETCAM_CPU_RDAT4r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000210, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_etcam_cpu_rdat4_reg, + NULL, + NULL, + }, + { + "cpu_rdat5", + STAT_ETCAM_CPU_RDAT5r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000214, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_etcam_cpu_rdat5_reg, + NULL, + NULL, + }, + { + "cpu_rdat6", + STAT_ETCAM_CPU_RDAT6r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000218, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_etcam_cpu_rdat6_reg, + NULL, + NULL, + }, + { + "cpu_rdat7", + STAT_ETCAM_CPU_RDAT7r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x0000021c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_etcam_cpu_rdat7_reg, + NULL, + NULL, + }, + { + "cpu_rdat8", + STAT_ETCAM_CPU_RDAT8r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000220, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_etcam_cpu_rdat8_reg, + NULL, + NULL, + }, + { + "cpu_rdat9", + STAT_ETCAM_CPU_RDAT9r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000224, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_etcam_cpu_rdat9_reg, + NULL, + NULL, + }, + { + "cpu_rdat10", + STAT_ETCAM_CPU_RDAT10r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000228, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_etcam_cpu_rdat10_reg, + NULL, + NULL, + }, + { + "cpu_rdat11", + STAT_ETCAM_CPU_RDAT11r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x0000022c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_etcam_cpu_rdat11_reg, + NULL, + NULL, + }, + { + "cpu_rdat12", + STAT_ETCAM_CPU_RDAT12r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000230, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_etcam_cpu_rdat12_reg, + NULL, + NULL, + }, + { + "cpu_rdat13", + STAT_ETCAM_CPU_RDAT13r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000234, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_etcam_cpu_rdat13_reg, + NULL, + NULL, + }, + { + "cpu_rdat14", + STAT_ETCAM_CPU_RDAT14r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000238, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_etcam_cpu_rdat14_reg, + NULL, + NULL, + }, + { + "cpu_rdat15", + STAT_ETCAM_CPU_RDAT15r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x0000023c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_etcam_cpu_rdat15_reg, + NULL, + NULL, + }, + { + "cpu_rdat16", + STAT_ETCAM_CPU_RDAT16r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000240, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_etcam_cpu_rdat16_reg, + NULL, + NULL, + }, + { + "cpu_rdat17", + STAT_ETCAM_CPU_RDAT17r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000244, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_etcam_cpu_rdat17_reg, + NULL, + NULL, + }, + { + "cpu_rdat18", + STAT_ETCAM_CPU_RDAT18r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000248, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_etcam_cpu_rdat18_reg, + NULL, + NULL, + }, + { + "cpu_rdat19", + STAT_ETCAM_CPU_RDAT19r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x0000024c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_etcam_cpu_rdat19_reg, + NULL, + NULL, + }, + { + "qvbo", + STAT_ETCAM_QVBOr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000250, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_etcam_qvbo_reg, + NULL, + NULL, + }, + { + "cnt_overflow_mode", + STAT_ETCAM_CNT_OVERFLOW_MODEr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x000003ec, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_stat_etcam_cnt_overflow_mode_reg, + NULL, + NULL, + }, + { + "cara_queue_ram0_159_0", + STAT_CAR0_CARA_QUEUE_RAM0_159_0r, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x000000 + 0x14000000, + (160/8), + 0, + 0x7FFF + 1, + 0, + 8, + 9, + g_stat_car0_cara_queue_ram0_159_0_reg, + NULL, + NULL, + }, + { + "cara_profile_ram1_255_0", + STAT_CAR0_CARA_PROFILE_RAM1_255_0r, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x040000 + 0x20000000, + (256/8), + 0, + 0x1FF + 1, + 0, + 8, + 31, + g_stat_car0_cara_profile_ram1_255_0_reg, + NULL, + NULL, + }, + { + "cara_qovs_ram_ram2", + STAT_CAR0_CARA_QOVS_RAM_RAM2r, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x80000, + (32/8), + 0, + 0x7FFF + 1, + 0, + 1, + 1, + g_stat_car0_cara_qovs_ram_ram2_reg, + NULL, + NULL, + }, + { + "look_up_table1", + STAT_CAR0_LOOK_UP_TABLE1r, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0xc0000, + (32/8), + 0, + 0x7FFF + 1, + 0, + 1, + 2, + g_stat_car0_look_up_table1_reg, + NULL, + NULL, + }, + { + "cara_pkt_des_i_cnt", + STAT_CAR0_CARA_PKT_DES_I_CNTr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2c0000, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_car0_cara_pkt_des_i_cnt_reg, + NULL, + NULL, + }, + { + "cara_green_pkt_i_cnt", + STAT_CAR0_CARA_GREEN_PKT_I_CNTr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2c0001, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_car0_cara_green_pkt_i_cnt_reg, + NULL, + NULL, + }, + { + "cara_yellow_pkt_i_cnt", + STAT_CAR0_CARA_YELLOW_PKT_I_CNTr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2c0002, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_car0_cara_yellow_pkt_i_cnt_reg, + NULL, + NULL, + }, + { + "cara_red_pkt_i_cnt", + STAT_CAR0_CARA_RED_PKT_I_CNTr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2c0003, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_car0_cara_red_pkt_i_cnt_reg, + NULL, + NULL, + }, + { + "cara_pkt_des_o_cnt", + STAT_CAR0_CARA_PKT_DES_O_CNTr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2c0004, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_car0_cara_pkt_des_o_cnt_reg, + NULL, + NULL, + }, + { + "cara_green_pkt_o_cnt", + STAT_CAR0_CARA_GREEN_PKT_O_CNTr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2c0005, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_car0_cara_green_pkt_o_cnt_reg, + NULL, + NULL, + }, + { + "cara_yellow_pkt_o_cnt", + STAT_CAR0_CARA_YELLOW_PKT_O_CNTr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2c0006, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_car0_cara_yellow_pkt_o_cnt_reg, + NULL, + NULL, + }, + { + "cara_red_pkt_o_cnt", + STAT_CAR0_CARA_RED_PKT_O_CNTr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2c0007, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_car0_cara_red_pkt_o_cnt_reg, + NULL, + NULL, + }, + { + "cara_pkt_des_fc_for_cfg_cnt", + STAT_CAR0_CARA_PKT_DES_FC_FOR_CFG_CNTr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2c0008, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_car0_cara_pkt_des_fc_for_cfg_cnt_reg, + NULL, + NULL, + }, + { + "cara_appoint_qnum_or_sp", + STAT_CAR0_CARA_APPOINT_QNUM_OR_SPr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2c0009, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_stat_car0_cara_appoint_qnum_or_sp_reg, + NULL, + NULL, + }, + { + "cara_cfgmt_count_mode", + STAT_CAR0_CARA_CFGMT_COUNT_MODEr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2c000a, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_stat_car0_cara_cfgmt_count_mode_reg, + NULL, + NULL, + }, + { + "cara_pkt_size_cnt", + STAT_CAR0_CARA_PKT_SIZE_CNTr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2c000b, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_car0_cara_pkt_size_cnt_reg, + NULL, + NULL, + }, + { + "cara_plcr_init_dont", + STAT_CAR0_CARA_PLCR_INIT_DONTr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2c000c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_car0_cara_plcr_init_dont_reg, + NULL, + NULL, + }, + { + "carb_queue_ram0_159_0", + STAT_CAR0_CARB_QUEUE_RAM0_159_0r, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x100000 + 0x14000000, + (160/8), + 0, + 0xFFF + 1, + 0, + 8, + 9, + g_stat_car0_carb_queue_ram0_159_0_reg, + NULL, + NULL, + }, + { + "carb_profile_ram1_255_0", + STAT_CAR0_CARB_PROFILE_RAM1_255_0r, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x140000 + 0x20000000, + (256/8), + 0, + 0x7F + 1, + 0, + 8, + 33, + g_stat_car0_carb_profile_ram1_255_0_reg, + NULL, + NULL, + }, + { + "carb_qovs_ram_ram2", + STAT_CAR0_CARB_QOVS_RAM_RAM2r, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x180000, + (32/8), + 0, + 0xFFF + 1, + 0, + 1, + 1, + g_stat_car0_carb_qovs_ram_ram2_reg, + NULL, + NULL, + }, + { + "look_up_table2", + STAT_CAR0_LOOK_UP_TABLE2r, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x1c0000, + (32/8), + 0, + 0xFFF + 1, + 0, + 1, + 2, + g_stat_car0_look_up_table2_reg, + NULL, + NULL, + }, + { + "carb_pkt_des_i_cnt", + STAT_CAR0_CARB_PKT_DES_I_CNTr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2c1000, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_car0_carb_pkt_des_i_cnt_reg, + NULL, + NULL, + }, + { + "carb_green_pkt_i_cnt", + STAT_CAR0_CARB_GREEN_PKT_I_CNTr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2c1001, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_car0_carb_green_pkt_i_cnt_reg, + NULL, + NULL, + }, + { + "carb_yellow_pkt_i_cnt", + STAT_CAR0_CARB_YELLOW_PKT_I_CNTr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2c1002, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_car0_carb_yellow_pkt_i_cnt_reg, + NULL, + NULL, + }, + { + "carb_red_pkt_i_cnt", + STAT_CAR0_CARB_RED_PKT_I_CNTr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2c1003, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_car0_carb_red_pkt_i_cnt_reg, + NULL, + NULL, + }, + { + "carb_pkt_des_o_cnt", + STAT_CAR0_CARB_PKT_DES_O_CNTr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2c1004, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_car0_carb_pkt_des_o_cnt_reg, + NULL, + NULL, + }, + { + "carb_green_pkt_o_cnt", + STAT_CAR0_CARB_GREEN_PKT_O_CNTr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2c1005, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_car0_carb_green_pkt_o_cnt_reg, + NULL, + NULL, + }, + { + "carb_yellow_pkt_o_cnt", + STAT_CAR0_CARB_YELLOW_PKT_O_CNTr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2c1006, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_car0_carb_yellow_pkt_o_cnt_reg, + NULL, + NULL, + }, + { + "carb_red_pkt_o_cnt", + STAT_CAR0_CARB_RED_PKT_O_CNTr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2c1007, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_car0_carb_red_pkt_o_cnt_reg, + NULL, + NULL, + }, + { + "carb_pkt_des_fc_for_cfg_cnt", + STAT_CAR0_CARB_PKT_DES_FC_FOR_CFG_CNTr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2c1008, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_car0_carb_pkt_des_fc_for_cfg_cnt_reg, + NULL, + NULL, + }, + { + "carb_appoint_qnum_or_sp", + STAT_CAR0_CARB_APPOINT_QNUM_OR_SPr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2c1009, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_stat_car0_carb_appoint_qnum_or_sp_reg, + NULL, + NULL, + }, + { + "carb_cfgmt_count_mode", + STAT_CAR0_CARB_CFGMT_COUNT_MODEr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2c100a, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_stat_car0_carb_cfgmt_count_mode_reg, + NULL, + NULL, + }, + { + "carb_pkt_size_cnt", + STAT_CAR0_CARB_PKT_SIZE_CNTr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2c100b, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_car0_carb_pkt_size_cnt_reg, + NULL, + NULL, + }, + { + "carb_plcr_init_dont", + STAT_CAR0_CARB_PLCR_INIT_DONTr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2c100c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_car0_carb_plcr_init_dont_reg, + NULL, + NULL, + }, + { + "carc_queue_ram0_159_0", + STAT_CAR0_CARC_QUEUE_RAM0_159_0r, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x200000 + 0x14000000, + (160/8), + 0, + 0x3FF + 1, + 0, + 8, + 9, + g_stat_car0_carc_queue_ram0_159_0_reg, + NULL, + NULL, + }, + { + "carc_profile_ram1_255_0", + STAT_CAR0_CARC_PROFILE_RAM1_255_0r, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x240000 + 0x20000000, + (256/8), + 0, + 0x1F + 1, + 0, + 8, + 33, + g_stat_car0_carc_profile_ram1_255_0_reg, + NULL, + NULL, + }, + { + "carc_qovs_ram_ram2", + STAT_CAR0_CARC_QOVS_RAM_RAM2r, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x280000, + (32/8), + 0, + 0x3FF + 1, + 0, + 1, + 1, + g_stat_car0_carc_qovs_ram_ram2_reg, + NULL, + NULL, + }, + { + "carc_pkt_des_i_cnt", + STAT_CAR0_CARC_PKT_DES_I_CNTr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2c2000, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_car0_carc_pkt_des_i_cnt_reg, + NULL, + NULL, + }, + { + "carc_green_pkt_i_cnt", + STAT_CAR0_CARC_GREEN_PKT_I_CNTr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2c2001, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_car0_carc_green_pkt_i_cnt_reg, + NULL, + NULL, + }, + { + "carc_yellow_pkt_i_cnt", + STAT_CAR0_CARC_YELLOW_PKT_I_CNTr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2c2002, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_car0_carc_yellow_pkt_i_cnt_reg, + NULL, + NULL, + }, + { + "carc_red_pkt_i_cnt", + STAT_CAR0_CARC_RED_PKT_I_CNTr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2c2003, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_car0_carc_red_pkt_i_cnt_reg, + NULL, + NULL, + }, + { + "carc_pkt_des_o_cnt", + STAT_CAR0_CARC_PKT_DES_O_CNTr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2c2004, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_car0_carc_pkt_des_o_cnt_reg, + NULL, + NULL, + }, + { + "carc_green_pkt_o_cnt", + STAT_CAR0_CARC_GREEN_PKT_O_CNTr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2c2005, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_car0_carc_green_pkt_o_cnt_reg, + NULL, + NULL, + }, + { + "carc_yellow_pkt_o_cnt", + STAT_CAR0_CARC_YELLOW_PKT_O_CNTr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2c2006, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_car0_carc_yellow_pkt_o_cnt_reg, + NULL, + NULL, + }, + { + "carc_red_pkt_o_cnt", + STAT_CAR0_CARC_RED_PKT_O_CNTr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2c2007, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_car0_carc_red_pkt_o_cnt_reg, + NULL, + NULL, + }, + { + "carc_pkt_des_fc_for_cfg_cnt", + STAT_CAR0_CARC_PKT_DES_FC_FOR_CFG_CNTr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2c2008, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_car0_carc_pkt_des_fc_for_cfg_cnt_reg, + NULL, + NULL, + }, + { + "carc_appoint_qnum_or_sp", + STAT_CAR0_CARC_APPOINT_QNUM_OR_SPr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2c2009, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_stat_car0_carc_appoint_qnum_or_sp_reg, + NULL, + NULL, + }, + { + "carc_cfgmt_count_mode", + STAT_CAR0_CARC_CFGMT_COUNT_MODEr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2c200a, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_stat_car0_carc_cfgmt_count_mode_reg, + NULL, + NULL, + }, + { + "carc_pkt_size_cnt", + STAT_CAR0_CARC_PKT_SIZE_CNTr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2c200b, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_car0_carc_pkt_size_cnt_reg, + NULL, + NULL, + }, + { + "carc_plcr_init_dont", + STAT_CAR0_CARC_PLCR_INIT_DONTr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2c200c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_car0_carc_plcr_init_dont_reg, + NULL, + NULL, + }, + { + "carb_random_ram", + STAT_CAR0_CARB_RANDOM_RAMr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x2d0000 + 0x40000000, + (512/8), + 0, + 0x1f + 1, + 0, + 16, + 24, + g_stat_car0_carb_random_ram_reg, + NULL, + NULL, + }, + { + "carc_random_ram", + STAT_CAR0_CARC_RANDOM_RAMr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x2e0000 + 0x40000000, + (512/8), + 0, + 0x7 + 1, + 0, + 16, + 24, + g_stat_car0_carc_random_ram_reg, + NULL, + NULL, + }, + { + "cara_begin_flow_id", + STAT_CAR0_CARA_BEGIN_FLOW_IDr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x300000, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_car0_cara_begin_flow_id_reg, + NULL, + NULL, + }, + { + "carb_begin_flow_id", + STAT_CAR0_CARB_BEGIN_FLOW_IDr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x300001, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_car0_carb_begin_flow_id_reg, + NULL, + NULL, + }, + { + "carc_begin_flow_id", + STAT_CAR0_CARC_BEGIN_FLOW_IDr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x300002, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_car0_carc_begin_flow_id_reg, + NULL, + NULL, + }, + { + "prog_full_assert_cfg_w", + STAT_CAR0_PROG_FULL_ASSERT_CFG_Wr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x300003, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_car0_prog_full_assert_cfg_w_reg, + NULL, + NULL, + }, + { + "prog_full_negate_cfg_w", + STAT_CAR0_PROG_FULL_NEGATE_CFG_Wr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x300004, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_car0_prog_full_negate_cfg_w_reg, + NULL, + NULL, + }, + { + "timeout_limit", + STAT_CAR0_TIMEOUT_LIMITr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x300005, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_car0_timeout_limit_reg, + NULL, + NULL, + }, + { + "pkt_des_fifo_overflow", + STAT_CAR0_PKT_DES_FIFO_OVERFLOWr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x300006, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_car0_pkt_des_fifo_overflow_reg, + NULL, + NULL, + }, + { + "pkt_des_fifo_underflow", + STAT_CAR0_PKT_DES_FIFO_UNDERFLOWr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x300007, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_car0_pkt_des_fifo_underflow_reg, + NULL, + NULL, + }, + { + "pkt_des_fifo_prog_full", + STAT_CAR0_PKT_DES_FIFO_PROG_FULLr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x300008, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_car0_pkt_des_fifo_prog_full_reg, + NULL, + NULL, + }, + { + "pkt_des_fifo_prog_empty", + STAT_CAR0_PKT_DES_FIFO_PROG_EMPTYr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x300009, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_car0_pkt_des_fifo_prog_empty_reg, + NULL, + NULL, + }, + { + "pkt_des_fifo_full", + STAT_CAR0_PKT_DES_FIFO_FULLr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x30000a, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_car0_pkt_des_fifo_full_reg, + NULL, + NULL, + }, + { + "pkt_des_fifo_empty", + STAT_CAR0_PKT_DES_FIFO_EMPTYr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x30000b, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_car0_pkt_des_fifo_empty_reg, + NULL, + NULL, + }, + { + "pkt_size_offset", + STAT_CAR0_PKT_SIZE_OFFSETr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x30000e, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_car0_pkt_size_offset_reg, + NULL, + NULL, + }, + { + "car_plcr_init_dont", + STAT_CAR0_CAR_PLCR_INIT_DONTr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x30000f, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_car0_car_plcr_init_dont_reg, + NULL, + NULL, + }, + { + "max_pkt_size_a", + STAT_CAR0_MAX_PKT_SIZE_Ar, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x300010, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_car0_max_pkt_size_a_reg, + NULL, + NULL, + }, + { + "max_pkt_size_b", + STAT_CAR0_MAX_PKT_SIZE_Br, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x300011, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_car0_max_pkt_size_b_reg, + NULL, + NULL, + }, + { + "max_pkt_size_c", + STAT_CAR0_MAX_PKT_SIZE_Cr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x300012, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_car0_max_pkt_size_c_reg, + NULL, + NULL, + }, + { + "car_hierarchy_mode", + STAT_CAR0_CAR_HIERARCHY_MODEr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x300013, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_car0_car_hierarchy_mode_reg, + NULL, + NULL, + }, + { + "prog_empty_assert_cfg_w", + STAT_CAR0_PROG_EMPTY_ASSERT_CFG_Wr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x300014, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_car0_prog_empty_assert_cfg_w_reg, + NULL, + NULL, + }, + { + "prog_empty_negate_cfg_w", + STAT_CAR0_PROG_EMPTY_NEGATE_CFG_Wr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x300015, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_car0_prog_empty_negate_cfg_w_reg, + NULL, + NULL, + }, + { + "pkt_des_fifo_ovf_int", + STAT_CAR0_PKT_DES_FIFO_OVF_INTr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x300016, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_car0_pkt_des_fifo_ovf_int_reg, + NULL, + NULL, + }, + { + "pkt_des_fifo_data_count", + STAT_CAR0_PKT_DES_FIFO_DATA_COUNTr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x300017, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_car0_pkt_des_fifo_data_count_reg, + NULL, + NULL, + }, + { + "pkt_des_fifo_udf_int", + STAT_CAR0_PKT_DES_FIFO_UDF_INTr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x300018, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_car0_pkt_des_fifo_udf_int_reg, + NULL, + NULL, + }, + { + "cara_queue_ram0_159_0_pkt", + STAT_CAR0_CARA_QUEUE_RAM0_159_0_PKTr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x000000 + 0x14000000, + (160/8), + 0, + 0x7FFF + 1, + 0, + 8, + 8, + g_stat_car0_cara_queue_ram0_159_0_pkt_reg, + NULL, + NULL, + }, + { + "cara_profile_ram1_255_0_pkt", + STAT_CAR0_CARA_PROFILE_RAM1_255_0_PKTr, + STAT, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x040000 + 0x20000000, + (256/8), + 0, + 0x1FF + 1, + 0, + 8, + 12, + g_stat_car0_cara_profile_ram1_255_0_pkt_reg, + NULL, + NULL, + }, + { + "block0_7_port_id_cfg", + STAT4K_ETCAM_BLOCK0_7_PORT_ID_CFGr, + STAT4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x0000005c, + (32/8), + 0, + 0, + 0, + 0, + 8, + g_stat4k_etcam_block0_7_port_id_cfg_reg, + dpp_write, + dpp_read, + }, + { + "block0_3_base_addr_cfg", + STAT4K_ETCAM_BLOCK0_3_BASE_ADDR_CFGr, + STAT4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000064, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_stat4k_etcam_block0_3_base_addr_cfg_reg, + dpp_write, + dpp_read, + }, + { + "block4_7_base_addr_cfg", + STAT4K_ETCAM_BLOCK4_7_BASE_ADDR_CFGr, + STAT4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000068, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_stat4k_etcam_block4_7_base_addr_cfg_reg, + dpp_write, + dpp_read, + }, + { + "cfg_eram_wr_interval_cnt", + DTB_DTB_CFG_CFG_ERAM_WR_INTERVAL_CNTr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0040, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_cfg_eram_wr_interval_cnt_reg, + NULL, + NULL, + }, + { + "cfg_zcam_wr_interval_cnt", + DTB_DTB_CFG_CFG_ZCAM_WR_INTERVAL_CNTr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0044, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_cfg_zcam_wr_interval_cnt_reg, + NULL, + NULL, + }, + { + "cfg_tcam_wr_interval_cnt", + DTB_DTB_CFG_CFG_TCAM_WR_INTERVAL_CNTr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0048, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_cfg_tcam_wr_interval_cnt_reg, + NULL, + NULL, + }, + { + "cfg_ddr_wr_interval_cnt", + DTB_DTB_CFG_CFG_DDR_WR_INTERVAL_CNTr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x004c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_cfg_ddr_wr_interval_cnt_reg, + NULL, + NULL, + }, + { + "cfg_hash_wr_interval_cnt", + DTB_DTB_CFG_CFG_HASH_WR_INTERVAL_CNTr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0050, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_cfg_hash_wr_interval_cnt_reg, + NULL, + NULL, + }, + { + "cfg_eram_rd_interval_cnt", + DTB_DTB_CFG_CFG_ERAM_RD_INTERVAL_CNTr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0058, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_cfg_eram_rd_interval_cnt_reg, + NULL, + NULL, + }, + { + "cfg_zcam_rd_interval_cnt", + DTB_DTB_CFG_CFG_ZCAM_RD_INTERVAL_CNTr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x005c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_cfg_zcam_rd_interval_cnt_reg, + NULL, + NULL, + }, + { + "cfg_tcam_rd_interval_cnt", + DTB_DTB_CFG_CFG_TCAM_RD_INTERVAL_CNTr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0060, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_cfg_tcam_rd_interval_cnt_reg, + NULL, + NULL, + }, + { + "cfg_ddr_rd_interval_cnt", + DTB_DTB_CFG_CFG_DDR_RD_INTERVAL_CNTr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0064, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_cfg_ddr_rd_interval_cnt_reg, + NULL, + NULL, + }, + { + "cfg_dtb_queue_lock_state_0_3", + DTB_DTB_CFG_CFG_DTB_QUEUE_LOCK_STATE_0_3r, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0080, + (32/8), + 0, + 3 + 1, + 0, + 4, + 1, + g_dtb_dtb_cfg_cfg_dtb_queue_lock_state_0_3_reg, + NULL, + NULL, + }, + { + "w_convert_0_mode", + DTB_DTB_AXIM0_W_CONVERT_0_MODEr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_AXIM0_BASE_ADDR + 0x6060, + (32/8), + 0, + 1 + 1, + 0, + 256, + 1, + g_dtb_dtb_axim0_w_convert_0_mode_reg, + NULL, + NULL, + }, + { + "r_convert_0_mode", + DTB_DTB_AXIM0_R_CONVERT_0_MODEr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_AXIM0_BASE_ADDR + 0x2060, + (32/8), + 0, + 1 + 1, + 0, + 256, + 1, + g_dtb_dtb_axim0_r_convert_0_mode_reg, + NULL, + NULL, + }, + { + "aximr_os", + DTB_DTB_AXIM0_AXIMR_OSr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_AXIM0_BASE_ADDR + 0x2000, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_axim0_aximr_os_reg, + NULL, + NULL, + }, + { + "w_convert_1_mode", + DTB_DTB_AXIM1_W_CONVERT_1_MODEr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_AXIM1_BASE_ADDR + 0x6060, + (32/8), + 0, + 2 + 1, + 0, + 256, + 1, + g_dtb_dtb_axim1_w_convert_1_mode_reg, + NULL, + NULL, + }, + { + "r_convert_1_mode", + DTB_DTB_AXIM1_R_CONVERT_1_MODEr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_AXIM1_BASE_ADDR + 0x2060, + (32/8), + 0, + 2 + 1, + 0, + 256, + 1, + g_dtb_dtb_axim1_r_convert_1_mode_reg, + NULL, + NULL, + }, + { + "axis_convert_mode", + DTB_DTB_AXIS_AXIS_CONVERT_MODEr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_AXIS_BASE_ADDR + 0x0450, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_axis_axis_convert_mode_reg, + NULL, + NULL, + }, + { + "cfg_queue_dtb_addr_h_0_127", + DTB4K_DTB_ENQ_CFG_QUEUE_DTB_ADDR_H_0_127r, + DTB4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_ENQ_BASE_ADDR + 0x0000, + (32/8), + 0, + 127 + 1, + 0, + 32, + 1, + g_dtb4k_dtb_enq_cfg_queue_dtb_addr_h_0_127_reg, + dpp_write, + dpp_read, + }, + { + "cfg_queue_dtb_addr_l_0_127", + DTB4K_DTB_ENQ_CFG_QUEUE_DTB_ADDR_L_0_127r, + DTB4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_ENQ_BASE_ADDR + 0x0004, + (32/8), + 0, + 127 + 1, + 0, + 32, + 1, + g_dtb4k_dtb_enq_cfg_queue_dtb_addr_l_0_127_reg, + dpp_write, + dpp_read, + }, + { + "cfg_queue_dtb_len_0_127", + DTB4K_DTB_ENQ_CFG_QUEUE_DTB_LEN_0_127r, + DTB4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_ENQ_BASE_ADDR + 0x0008, + (32/8), + 0, + 127 + 1, + 0, + 32, + 3, + g_dtb4k_dtb_enq_cfg_queue_dtb_len_0_127_reg, + dpp_write, + dpp_read, + }, + { + "info_queue_buf_space_left_0_127", + DTB4K_DTB_ENQ_INFO_QUEUE_BUF_SPACE_LEFT_0_127r, + DTB4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_ENQ_BASE_ADDR + 0x000c, + (32/8), + 0, + 127 + 1, + 0, + 32, + 1, + g_dtb4k_dtb_enq_info_queue_buf_space_left_0_127_reg, + dpp_write, + dpp_read, + }, + { + "cfg_epid_v_func_num_0_127", + DTB4K_DTB_ENQ_CFG_EPID_V_FUNC_NUM_0_127r, + DTB4K, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_ENQ_BASE_ADDR + 0x0010, + (32/8), + 0, + 127 + 1, + 0, + 32, + 7, + g_dtb4k_dtb_enq_cfg_epid_v_func_num_0_127_reg, + dpp_write, + dpp_read, + }, + { + "cpu_trpg_ms_en", + TRPG_TRPG_RX_PORT_CPU_TRPG_MS_ENr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0004, + (32/8), + DPP_TRPG_PORT_NUM, + 0, + DPP_TRPG_PORT_SPACE_SIZE, + 0, + 1, + g_trpg_trpg_rx_port_cpu_trpg_ms_en_reg, + NULL, + NULL, + }, + { + "cpu_trpg_port_en", + TRPG_TRPG_RX_PORT_CPU_TRPG_PORT_ENr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0010, + (32/8), + DPP_TRPG_PORT_NUM, + 0, + DPP_TRPG_PORT_SPACE_SIZE, + 0, + 1, + g_trpg_trpg_rx_port_cpu_trpg_port_en_reg, + NULL, + NULL, + }, + { + "cpu_trpg_look_en", + TRPG_TRPG_RX_PORT_CPU_TRPG_LOOK_ENr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0014, + (32/8), + DPP_TRPG_PORT_NUM, + 0, + DPP_TRPG_PORT_SPACE_SIZE, + 0, + 1, + g_trpg_trpg_rx_port_cpu_trpg_look_en_reg, + NULL, + NULL, + }, + { + "cpu_trpgrx_ram_almost_full", + TRPG_TRPG_RX_PORT_CPU_TRPGRX_RAM_ALMOST_FULLr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0028, + (32/8), + DPP_TRPG_PORT_NUM, + 0, + DPP_TRPG_PORT_SPACE_SIZE, + 0, + 1, + g_trpg_trpg_rx_port_cpu_trpgrx_ram_almost_full_reg, + NULL, + NULL, + }, + { + "cpu_trpgrx_ram_test_en", + TRPG_TRPG_RX_PORT_CPU_TRPGRX_RAM_TEST_ENr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x002c, + (32/8), + DPP_TRPG_PORT_NUM, + 0, + DPP_TRPG_PORT_SPACE_SIZE, + 0, + 1, + g_trpg_trpg_rx_port_cpu_trpgrx_ram_test_en_reg, + NULL, + NULL, + }, + { + "cpu_trpgrx_inmod_pfc_rdy_en", + TRPG_TRPG_RX_PORT_CPU_TRPGRX_INMOD_PFC_RDY_ENr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0030, + (32/8), + DPP_TRPG_PORT_NUM, + 0, + DPP_TRPG_PORT_SPACE_SIZE, + 0, + 1, + g_trpg_trpg_rx_port_cpu_trpgrx_inmod_pfc_rdy_en_reg, + NULL, + NULL, + }, + { + "cpu_trpgrx_pkt_num_h", + TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_NUM_Hr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0034, + (32/8), + DPP_TRPG_PORT_NUM, + 0, + DPP_TRPG_PORT_SPACE_SIZE, + 0, + 1, + g_trpg_trpg_rx_port_cpu_trpgrx_pkt_num_h_reg, + NULL, + NULL, + }, + { + "cpu_trpgrx_pkt_num_l", + TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_NUM_Lr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0038, + (32/8), + DPP_TRPG_PORT_NUM, + 0, + DPP_TRPG_PORT_SPACE_SIZE, + 0, + 1, + g_trpg_trpg_rx_port_cpu_trpgrx_pkt_num_l_reg, + NULL, + NULL, + }, + { + "cpu_trpgrx_pkt_byte_num_h", + TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_BYTE_NUM_Hr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x003c, + (32/8), + DPP_TRPG_PORT_NUM, + 0, + DPP_TRPG_PORT_SPACE_SIZE, + 0, + 1, + g_trpg_trpg_rx_port_cpu_trpgrx_pkt_byte_num_h_reg, + NULL, + NULL, + }, + { + "cpu_trpgrx_pkt_byte_num_l", + TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_BYTE_NUM_Lr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0040, + (32/8), + DPP_TRPG_PORT_NUM, + 0, + DPP_TRPG_PORT_SPACE_SIZE, + 0, + 1, + g_trpg_trpg_rx_port_cpu_trpgrx_pkt_byte_num_l_reg, + NULL, + NULL, + }, + { + "cpu_trpgrx_pkt_cnt_clr", + TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_CNT_CLRr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0044, + (32/8), + DPP_TRPG_PORT_NUM, + 0, + DPP_TRPG_PORT_SPACE_SIZE, + 0, + 1, + g_trpg_trpg_rx_port_cpu_trpgrx_pkt_cnt_clr_reg, + NULL, + NULL, + }, + { + "cpu_trpgrx_fc_clk_freq", + TRPG_TRPG_RX_PORT_CPU_TRPGRX_FC_CLK_FREQr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0048, + (32/8), + DPP_TRPG_PORT_NUM, + 0, + DPP_TRPG_PORT_SPACE_SIZE, + 0, + 1, + g_trpg_trpg_rx_port_cpu_trpgrx_fc_clk_freq_reg, + NULL, + NULL, + }, + { + "cpu_trpgrx_fc_en", + TRPG_TRPG_RX_PORT_CPU_TRPGRX_FC_ENr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x004c, + (32/8), + DPP_TRPG_PORT_NUM, + 0, + DPP_TRPG_PORT_SPACE_SIZE, + 0, + 1, + g_trpg_trpg_rx_port_cpu_trpgrx_fc_en_reg, + NULL, + NULL, + }, + { + "cpu_trpgrx_fc_token_add_num", + TRPG_TRPG_RX_PORT_CPU_TRPGRX_FC_TOKEN_ADD_NUMr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0050, + (32/8), + DPP_TRPG_PORT_NUM, + 0, + DPP_TRPG_PORT_SPACE_SIZE, + 0, + 1, + g_trpg_trpg_rx_port_cpu_trpgrx_fc_token_add_num_reg, + NULL, + NULL, + }, + { + "cpu_trpgrx_fc_token_max_num", + TRPG_TRPG_RX_PORT_CPU_TRPGRX_FC_TOKEN_MAX_NUMr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0054, + (32/8), + DPP_TRPG_PORT_NUM, + 0, + DPP_TRPG_PORT_SPACE_SIZE, + 0, + 1, + g_trpg_trpg_rx_port_cpu_trpgrx_fc_token_max_num_reg, + NULL, + NULL, + }, + { + "cpu_trpgrx_port_state_info", + TRPG_TRPG_RX_PORT_CPU_TRPGRX_PORT_STATE_INFOr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0058, + (32/8), + DPP_TRPG_PORT_NUM, + 0, + DPP_TRPG_PORT_SPACE_SIZE, + 0, + 1, + g_trpg_trpg_rx_port_cpu_trpgrx_port_state_info_reg, + NULL, + NULL, + }, + { + "cpu_trpgrx_ram_past_max_dep", + TRPG_TRPG_RX_PORT_CPU_TRPGRX_RAM_PAST_MAX_DEPr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x005c, + (32/8), + DPP_TRPG_PORT_NUM, + 0, + DPP_TRPG_PORT_SPACE_SIZE, + 0, + 1, + g_trpg_trpg_rx_port_cpu_trpgrx_ram_past_max_dep_reg, + NULL, + NULL, + }, + { + "cpu_trpgrx_ram_past_max_dep_clr", + TRPG_TRPG_RX_PORT_CPU_TRPGRX_RAM_PAST_MAX_DEP_CLRr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0060, + (32/8), + DPP_TRPG_PORT_NUM, + 0, + DPP_TRPG_PORT_SPACE_SIZE, + 0, + 1, + g_trpg_trpg_rx_port_cpu_trpgrx_ram_past_max_dep_clr_reg, + NULL, + NULL, + }, + { + "cpu_trpgrx_pkt_past_max_len", + TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_PAST_MAX_LENr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0064, + (32/8), + DPP_TRPG_PORT_NUM, + 0, + DPP_TRPG_PORT_SPACE_SIZE, + 0, + 1, + g_trpg_trpg_rx_port_cpu_trpgrx_pkt_past_max_len_reg, + NULL, + NULL, + }, + { + "cpu_trpgrx_pkt_past_max_len_clr", + TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_PAST_MAX_LEN_CLRr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0068, + (32/8), + DPP_TRPG_PORT_NUM, + 0, + DPP_TRPG_PORT_SPACE_SIZE, + 0, + 1, + g_trpg_trpg_rx_port_cpu_trpgrx_pkt_past_max_len_clr_reg, + NULL, + NULL, + }, + { + "cpu_trpgrx_pkt_past_min_len", + TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_PAST_MIN_LENr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x006c, + (32/8), + DPP_TRPG_PORT_NUM, + 0, + DPP_TRPG_PORT_SPACE_SIZE, + 0, + 1, + g_trpg_trpg_rx_port_cpu_trpgrx_pkt_past_min_len_reg, + NULL, + NULL, + }, + { + "cpu_trpgrx_pkt_past_min_len_clr", + TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_PAST_MIN_LEN_CLRr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0070, + (32/8), + DPP_TRPG_PORT_NUM, + 0, + DPP_TRPG_PORT_SPACE_SIZE, + 0, + 1, + g_trpg_trpg_rx_port_cpu_trpgrx_pkt_past_min_len_clr_reg, + NULL, + NULL, + }, + { + "trpg_rx_data_ram", + TRPG_TRPG_RX_RAM_TRPG_RX_DATA_RAMr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_RAM_BASE_ADDR + 0x0000, + (32/8), + DPP_TRPG_RAM_NUM, + 2047 + 1, + DPP_TRPG_RAM_SPACE_SIZE, + 4, + 1, + g_trpg_trpg_rx_ram_trpg_rx_data_ram_reg, + NULL, + NULL, + }, + { + "trpg_rx_info_ram", + TRPG_TRPG_RX_RAM_TRPG_RX_INFO_RAMr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_RAM_BASE_ADDR + 0x2000, + (32/8), + DPP_TRPG_RAM_NUM, + 255 + 1, + DPP_TRPG_RAM_SPACE_SIZE, + 4, + 1, + g_trpg_trpg_rx_ram_trpg_rx_info_ram_reg, + NULL, + NULL, + }, + { + "cpu_trpg_ms_en", + TRPG_TRPG_TX_PORT_CPU_TRPG_MS_ENr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x0004, + (32/8), + DPP_TRPG_PORT_NUM, + 0, + DPP_TRPG_PORT_SPACE_SIZE, + 0, + 1, + g_trpg_trpg_tx_port_cpu_trpg_ms_en_reg, + NULL, + NULL, + }, + { + "cpu_trpg_port_en", + TRPG_TRPG_TX_PORT_CPU_TRPG_PORT_ENr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x0010, + (32/8), + DPP_TRPG_PORT_NUM, + 0, + DPP_TRPG_PORT_SPACE_SIZE, + 0, + 1, + g_trpg_trpg_tx_port_cpu_trpg_port_en_reg, + NULL, + NULL, + }, + { + "cpu_trpg_look_en", + TRPG_TRPG_TX_PORT_CPU_TRPG_LOOK_ENr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x0014, + (32/8), + DPP_TRPG_PORT_NUM, + 0, + DPP_TRPG_PORT_SPACE_SIZE, + 0, + 1, + g_trpg_trpg_tx_port_cpu_trpg_look_en_reg, + NULL, + NULL, + }, + { + "cpu_trpgtx_ram_almost_full", + TRPG_TRPG_TX_PORT_CPU_TRPGTX_RAM_ALMOST_FULLr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x0018, + (32/8), + DPP_TRPG_PORT_NUM, + 0, + DPP_TRPG_PORT_SPACE_SIZE, + 0, + 1, + g_trpg_trpg_tx_port_cpu_trpgtx_ram_almost_full_reg, + NULL, + NULL, + }, + { + "cpu_trpgtx_ram_test_en", + TRPG_TRPG_TX_PORT_CPU_TRPGTX_RAM_TEST_ENr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x001c, + (32/8), + DPP_TRPG_PORT_NUM, + 0, + DPP_TRPG_PORT_SPACE_SIZE, + 0, + 1, + g_trpg_trpg_tx_port_cpu_trpgtx_ram_test_en_reg, + NULL, + NULL, + }, + { + "cpu_trpgtx_pkt_num_h", + TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_NUM_Hr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x0034, + (32/8), + DPP_TRPG_PORT_NUM, + 0, + DPP_TRPG_PORT_SPACE_SIZE, + 0, + 1, + g_trpg_trpg_tx_port_cpu_trpgtx_pkt_num_h_reg, + NULL, + NULL, + }, + { + "cpu_trpgtx_pkt_num_l", + TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_NUM_Lr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x0038, + (32/8), + DPP_TRPG_PORT_NUM, + 0, + DPP_TRPG_PORT_SPACE_SIZE, + 0, + 1, + g_trpg_trpg_tx_port_cpu_trpgtx_pkt_num_l_reg, + NULL, + NULL, + }, + { + "cpu_trpgtx_pkt_byte_num_h", + TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_BYTE_NUM_Hr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x003c, + (32/8), + DPP_TRPG_PORT_NUM, + 0, + DPP_TRPG_PORT_SPACE_SIZE, + 0, + 1, + g_trpg_trpg_tx_port_cpu_trpgtx_pkt_byte_num_h_reg, + NULL, + NULL, + }, + { + "cpu_trpgtx_pkt_byte_num_l", + TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_BYTE_NUM_Lr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x0040, + (32/8), + DPP_TRPG_PORT_NUM, + 0, + DPP_TRPG_PORT_SPACE_SIZE, + 0, + 1, + g_trpg_trpg_tx_port_cpu_trpgtx_pkt_byte_num_l_reg, + NULL, + NULL, + }, + { + "cpu_trpgtx_pkt_cnt_clr", + TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_CNT_CLRr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x0044, + (32/8), + DPP_TRPG_PORT_NUM, + 0, + DPP_TRPG_PORT_SPACE_SIZE, + 0, + 1, + g_trpg_trpg_tx_port_cpu_trpgtx_pkt_cnt_clr_reg, + NULL, + NULL, + }, + { + "cpu_trpgtx_fc_clk_freq", + TRPG_TRPG_TX_PORT_CPU_TRPGTX_FC_CLK_FREQr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x0048, + (32/8), + DPP_TRPG_PORT_NUM, + 0, + DPP_TRPG_PORT_SPACE_SIZE, + 0, + 1, + g_trpg_trpg_tx_port_cpu_trpgtx_fc_clk_freq_reg, + NULL, + NULL, + }, + { + "cpu_trpgtx_fc_en", + TRPG_TRPG_TX_PORT_CPU_TRPGTX_FC_ENr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x004c, + (32/8), + DPP_TRPG_PORT_NUM, + 0, + DPP_TRPG_PORT_SPACE_SIZE, + 0, + 1, + g_trpg_trpg_tx_port_cpu_trpgtx_fc_en_reg, + NULL, + NULL, + }, + { + "cpu_trpgtx_fc_token_add_num", + TRPG_TRPG_TX_PORT_CPU_TRPGTX_FC_TOKEN_ADD_NUMr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x0050, + (32/8), + DPP_TRPG_PORT_NUM, + 0, + DPP_TRPG_PORT_SPACE_SIZE, + 0, + 1, + g_trpg_trpg_tx_port_cpu_trpgtx_fc_token_add_num_reg, + NULL, + NULL, + }, + { + "cpu_trpgtx_fc_token_max_num", + TRPG_TRPG_TX_PORT_CPU_TRPGTX_FC_TOKEN_MAX_NUMr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x0054, + (32/8), + DPP_TRPG_PORT_NUM, + 0, + DPP_TRPG_PORT_SPACE_SIZE, + 0, + 1, + g_trpg_trpg_tx_port_cpu_trpgtx_fc_token_max_num_reg, + NULL, + NULL, + }, + { + "cpu_trpgtx_port_state_info", + TRPG_TRPG_TX_PORT_CPU_TRPGTX_PORT_STATE_INFOr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x0058, + (32/8), + DPP_TRPG_PORT_NUM, + 0, + DPP_TRPG_PORT_SPACE_SIZE, + 0, + 1, + g_trpg_trpg_tx_port_cpu_trpgtx_port_state_info_reg, + NULL, + NULL, + }, + { + "cpu_trpgtx_ram_past_max_dep", + TRPG_TRPG_TX_PORT_CPU_TRPGTX_RAM_PAST_MAX_DEPr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x005c, + (32/8), + DPP_TRPG_PORT_NUM, + 0, + DPP_TRPG_PORT_SPACE_SIZE, + 0, + 1, + g_trpg_trpg_tx_port_cpu_trpgtx_ram_past_max_dep_reg, + NULL, + NULL, + }, + { + "cpu_trpgtx_ram_past_max_dep_clr", + TRPG_TRPG_TX_PORT_CPU_TRPGTX_RAM_PAST_MAX_DEP_CLRr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x0060, + (32/8), + DPP_TRPG_PORT_NUM, + 0, + DPP_TRPG_PORT_SPACE_SIZE, + 0, + 1, + g_trpg_trpg_tx_port_cpu_trpgtx_ram_past_max_dep_clr_reg, + NULL, + NULL, + }, + { + "cpu_trpgtx_pkt_past_max_len", + TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_PAST_MAX_LENr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x0064, + (32/8), + DPP_TRPG_PORT_NUM, + 0, + DPP_TRPG_PORT_SPACE_SIZE, + 0, + 1, + g_trpg_trpg_tx_port_cpu_trpgtx_pkt_past_max_len_reg, + NULL, + NULL, + }, + { + "cpu_trpgtx_pkt_past_max_len_clr", + TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_PAST_MAX_LEN_CLRr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x0068, + (32/8), + DPP_TRPG_PORT_NUM, + 0, + DPP_TRPG_PORT_SPACE_SIZE, + 0, + 1, + g_trpg_trpg_tx_port_cpu_trpgtx_pkt_past_max_len_clr_reg, + NULL, + NULL, + }, + { + "cpu_trpgtx_pkt_past_min_len", + TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_PAST_MIN_LENr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x006c, + (32/8), + DPP_TRPG_PORT_NUM, + 0, + DPP_TRPG_PORT_SPACE_SIZE, + 0, + 1, + g_trpg_trpg_tx_port_cpu_trpgtx_pkt_past_min_len_reg, + NULL, + NULL, + }, + { + "cpu_trpgtx_pkt_past_min_len_clr", + TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_PAST_MIN_LEN_CLRr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x0070, + (32/8), + DPP_TRPG_PORT_NUM, + 0, + DPP_TRPG_PORT_SPACE_SIZE, + 0, + 1, + g_trpg_trpg_tx_port_cpu_trpgtx_pkt_past_min_len_clr_reg, + NULL, + NULL, + }, + { + "cpu_trpgtx_etm_ram_almost_full", + TRPG_TRPG_TX_ETM_PORT_CPU_TRPGTX_ETM_RAM_ALMOST_FULLr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_ETM_PORT_BASE_ADDR + 0x0000, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_trpg_trpg_tx_etm_port_cpu_trpgtx_etm_ram_almost_full_reg, + NULL, + NULL, + }, + { + "cpu_trpgtx_etm_ram_test_en", + TRPG_TRPG_TX_ETM_PORT_CPU_TRPGTX_ETM_RAM_TEST_ENr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_ETM_PORT_BASE_ADDR + 0x0010, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_trpg_trpg_tx_etm_port_cpu_trpgtx_etm_ram_test_en_reg, + NULL, + NULL, + }, + { + "cpu_todtime_update_int_mask", + TRPG_TRPG_TX_GLB_CPU_TODTIME_UPDATE_INT_MASKr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_GLB_BASE_ADDR + 0x000c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_trpg_trpg_tx_glb_cpu_todtime_update_int_mask_reg, + NULL, + NULL, + }, + { + "cpu_todtime_update_int_clr", + TRPG_TRPG_TX_GLB_CPU_TODTIME_UPDATE_INT_CLRr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_GLB_BASE_ADDR + 0x0010, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_trpg_trpg_tx_glb_cpu_todtime_update_int_clr_reg, + NULL, + NULL, + }, + { + "cpu_todtime_ram_test_en", + TRPG_TRPG_TX_GLB_CPU_TODTIME_RAM_TEST_ENr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_GLB_BASE_ADDR + 0x004c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_trpg_trpg_tx_glb_cpu_todtime_ram_test_en_reg, + NULL, + NULL, + }, + { + "trpg_tx_data_ram", + TRPG_TRPG_TX_RAM_TRPG_TX_DATA_RAMr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_RAM_BASE_ADDR + 0x0000, + (32/8), + DPP_TRPG_RAM_NUM, + 12031 + 1, + DPP_TRPG_RAM_SPACE_SIZE, + 4, + 1, + g_trpg_trpg_tx_ram_trpg_tx_data_ram_reg, + NULL, + NULL, + }, + { + "trpg_tx_info_ram", + TRPG_TRPG_TX_RAM_TRPG_TX_INFO_RAMr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_RAM_BASE_ADDR + 0xc000, + (32/8), + DPP_TRPG_RAM_NUM, + 751 + 1, + DPP_TRPG_RAM_SPACE_SIZE, + 4, + 1, + g_trpg_trpg_tx_ram_trpg_tx_info_ram_reg, + NULL, + NULL, + }, + { + "trpg_tx_etm_data_ram", + TRPG_TRPG_TX_ETM_RAM_TRPG_TX_ETM_DATA_RAMr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_ETM_RAM_BASE_ADDR + 0x0000, + (32/8), + 0, + 511 + 1, + 0, + 4, + 1, + g_trpg_trpg_tx_etm_ram_trpg_tx_etm_data_ram_reg, + NULL, + NULL, + }, + { + "trpg_tx_etm_info_ram", + TRPG_TRPG_TX_ETM_RAM_TRPG_TX_ETM_INFO_RAMr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_ETM_RAM_BASE_ADDR + 0x800, + (32/8), + 0, + 31 + 1, + 0, + 4, + 1, + g_trpg_trpg_tx_etm_ram_trpg_tx_etm_info_ram_reg, + NULL, + NULL, + }, + { + "chip_version_reg", + ETM_CFGMT_CHIP_VERSION_REGr, + ETM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + 0x40, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_etm_cfgmt_chip_version_reg_reg, + NULL, + NULL, + }, + { + "chip_date_reg", + ETM_CFGMT_CHIP_DATE_REGr, + ETM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + 0x50, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cfgmt_chip_date_reg_reg, + NULL, + NULL, + }, + { + "cfgmt_crc_en", + ETM_CFGMT_CFGMT_CRC_ENr, + ETM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + 0x80, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cfgmt_cfgmt_crc_en_reg, + NULL, + NULL, + }, + { + "cfg_port_transfer_en", + ETM_CFGMT_CFG_PORT_TRANSFER_ENr, + ETM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + 0x130, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cfgmt_cfg_port_transfer_en_reg, + NULL, + NULL, + }, + { + "tm_sa_work_mode", + ETM_CFGMT_TM_SA_WORK_MODEr, + ETM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + 0x180, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cfgmt_tm_sa_work_mode_reg, + NULL, + NULL, + }, + { + "local_sa_id", + ETM_CFGMT_LOCAL_SA_IDr, + ETM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + 0x190, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cfgmt_local_sa_id_reg, + NULL, + NULL, + }, + { + "olif_rdy", + ETM_OLIF_OLIF_RDYr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_etm_olif_olif_rdy_reg, + NULL, + NULL, + }, + { + "emem_prog_full", + ETM_OLIF_EMEM_PROG_FULLr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x3, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_etm_olif_emem_prog_full_reg, + NULL, + NULL, + }, + { + "port_order_fifo_full", + ETM_OLIF_PORT_ORDER_FIFO_FULLr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x5, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_etm_olif_port_order_fifo_full_reg, + NULL, + NULL, + }, + { + "olif_release_last", + ETM_OLIF_OLIF_RELEASE_LASTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x6, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_etm_olif_olif_release_last_reg, + NULL, + NULL, + }, + { + "olif_fifo_empty_state", + ETM_OLIF_OLIF_FIFO_EMPTY_STATEr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0xa, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_etm_olif_olif_fifo_empty_state_reg, + NULL, + NULL, + }, + { + "qmu_olif_release_fc_cnt", + ETM_OLIF_QMU_OLIF_RELEASE_FC_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0xb, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_olif_qmu_olif_release_fc_cnt_reg, + NULL, + NULL, + }, + { + "olif_qmu_link_fc_cnt", + ETM_OLIF_OLIF_QMU_LINK_FC_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0xc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_olif_olif_qmu_link_fc_cnt_reg, + NULL, + NULL, + }, + { + "lif0_link_fc_cnt", + ETM_OLIF_LIF0_LINK_FC_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0xd, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_olif_lif0_link_fc_cnt_reg, + NULL, + NULL, + }, + { + "olif_tmmu_fc_cnt", + ETM_OLIF_OLIF_TMMU_FC_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0xe, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_olif_olif_tmmu_fc_cnt_reg, + NULL, + NULL, + }, + { + "olif_mmu_fc_cnt", + ETM_OLIF_OLIF_MMU_FC_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0xf, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_olif_olif_mmu_fc_cnt_reg, + NULL, + NULL, + }, + { + "olif_qmu_port_rdy_h", + ETM_OLIF_OLIF_QMU_PORT_RDY_Hr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x10, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_olif_olif_qmu_port_rdy_h_reg, + NULL, + NULL, + }, + { + "olif_qmu_port_rdy_l", + ETM_OLIF_OLIF_QMU_PORT_RDY_Lr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x11, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_olif_olif_qmu_port_rdy_l_reg, + NULL, + NULL, + }, + { + "lif0_port_rdy_h", + ETM_OLIF_LIF0_PORT_RDY_Hr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x12, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_olif_lif0_port_rdy_h_reg, + NULL, + NULL, + }, + { + "lif0_port_rdy_l", + ETM_OLIF_LIF0_PORT_RDY_Lr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x13, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_olif_lif0_port_rdy_l_reg, + NULL, + NULL, + }, + { + "qmu_olif_rd_sop_cnt", + ETM_OLIF_QMU_OLIF_RD_SOP_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x14, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_olif_qmu_olif_rd_sop_cnt_reg, + NULL, + NULL, + }, + { + "qmu_olif_rd_eop_cnt", + ETM_OLIF_QMU_OLIF_RD_EOP_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x15, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_olif_qmu_olif_rd_eop_cnt_reg, + NULL, + NULL, + }, + { + "qmu_olif_rd_vld_cnt", + ETM_OLIF_QMU_OLIF_RD_VLD_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x16, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_olif_qmu_olif_rd_vld_cnt_reg, + NULL, + NULL, + }, + { + "qmu_olif_rd_blk_cnt", + ETM_OLIF_QMU_OLIF_RD_BLK_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x17, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_olif_qmu_olif_rd_blk_cnt_reg, + NULL, + NULL, + }, + { + "mmu_tm_data_sop_cnt", + ETM_OLIF_MMU_TM_DATA_SOP_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x18, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_olif_mmu_tm_data_sop_cnt_reg, + NULL, + NULL, + }, + { + "mmu_tm_data_eop_cnt", + ETM_OLIF_MMU_TM_DATA_EOP_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x19, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_olif_mmu_tm_data_eop_cnt_reg, + NULL, + NULL, + }, + { + "mmu_tm_data_vld_cnt", + ETM_OLIF_MMU_TM_DATA_VLD_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x1a, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_olif_mmu_tm_data_vld_cnt_reg, + NULL, + NULL, + }, + { + "odma_tm_data_sop_cnt", + ETM_OLIF_ODMA_TM_DATA_SOP_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x1b, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_olif_odma_tm_data_sop_cnt_reg, + NULL, + NULL, + }, + { + "odma_tm_data_eop_cnt", + ETM_OLIF_ODMA_TM_DATA_EOP_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x1c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_olif_odma_tm_data_eop_cnt_reg, + NULL, + NULL, + }, + { + "odma_tm_deq_vld_cnt", + ETM_OLIF_ODMA_TM_DEQ_VLD_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x1d, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_olif_odma_tm_deq_vld_cnt_reg, + NULL, + NULL, + }, + { + "olif_qmu_release_vld_cnt", + ETM_OLIF_OLIF_QMU_RELEASE_VLD_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x1f, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_olif_olif_qmu_release_vld_cnt_reg, + NULL, + NULL, + }, + { + "emem_dat_vld_cnt", + ETM_OLIF_EMEM_DAT_VLD_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_olif_emem_dat_vld_cnt_reg, + NULL, + NULL, + }, + { + "imem_dat_vld_cnt", + ETM_OLIF_IMEM_DAT_VLD_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x21, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_olif_imem_dat_vld_cnt_reg, + NULL, + NULL, + }, + { + "emem_dat_rd_cnt", + ETM_OLIF_EMEM_DAT_RD_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x22, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_olif_emem_dat_rd_cnt_reg, + NULL, + NULL, + }, + { + "imem_dat_rd_cnt", + ETM_OLIF_IMEM_DAT_RD_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x23, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_olif_imem_dat_rd_cnt_reg, + NULL, + NULL, + }, + { + "qmu_olif_rd_sop_emem_cnt", + ETM_OLIF_QMU_OLIF_RD_SOP_EMEM_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x24, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_olif_qmu_olif_rd_sop_emem_cnt_reg, + NULL, + NULL, + }, + { + "qmu_olif_rd_vld_emem_cnt", + ETM_OLIF_QMU_OLIF_RD_VLD_EMEM_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x25, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_olif_qmu_olif_rd_vld_emem_cnt_reg, + NULL, + NULL, + }, + { + "cpu_last_wr_addr", + ETM_OLIF_CPU_LAST_WR_ADDRr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x26, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_olif_cpu_last_wr_addr_reg, + NULL, + NULL, + }, + { + "cpu_last_wr_data", + ETM_OLIF_CPU_LAST_WR_DATAr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x27, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_olif_cpu_last_wr_data_reg, + NULL, + NULL, + }, + { + "cpu_last_rd_addr", + ETM_OLIF_CPU_LAST_RD_ADDRr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x28, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_olif_cpu_last_rd_addr_reg, + NULL, + NULL, + }, + { + "qmu_olif_last_port", + ETM_OLIF_QMU_OLIF_LAST_PORTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x35, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_olif_qmu_olif_last_port_reg, + NULL, + NULL, + }, + { + "qmu_olif_last_addr", + ETM_OLIF_QMU_OLIF_LAST_ADDRr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x36, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_olif_qmu_olif_last_addr_reg, + NULL, + NULL, + }, + { + "qmu_olif_last_bank", + ETM_OLIF_QMU_OLIF_LAST_BANKr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x37, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_olif_qmu_olif_last_bank_reg, + NULL, + NULL, + }, + { + "tm_lif_byte_stat", + ETM_OLIF_TM_LIF_BYTE_STATr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x70, + (32/8), + 0, + 0xf + 1, + 0, + 0x1, + 1, + g_etm_olif_tm_lif_byte_stat_reg, + NULL, + NULL, + }, + { + "tm_lif_err_stat", + ETM_OLIF_TM_LIF_ERR_STATr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x90, + (32/8), + 0, + 0xf + 1, + 0, + 0x1, + 1, + g_etm_olif_tm_lif_err_stat_reg, + NULL, + NULL, + }, + { + "port_share_cnt", + ETM_CGAVD_PORT_SHARE_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_port_share_cnt_reg, + NULL, + NULL, + }, + { + "total_imem_cnt", + ETM_CGAVD_TOTAL_IMEM_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0xa, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_total_imem_cnt_reg, + NULL, + NULL, + }, + { + "pp_q_len", + ETM_CGAVD_PP_Q_LENr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0xa00, + (32/8), + 0, + 0x7f + 1, + 0, + 0x1, + 1, + g_etm_cgavd_pp_q_len_reg, + NULL, + NULL, + }, + { + "sys_q_len", + ETM_CGAVD_SYS_Q_LENr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x1205, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_sys_q_len_reg, + NULL, + NULL, + }, + { + "cgavd_cfg_error_warning", + ETM_CGAVD_CGAVD_CFG_ERROR_WARNINGr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x12de, + (32/8), + 0, + 0, + 0, + 0, + 12, + g_etm_cgavd_cgavd_cfg_error_warning_reg, + NULL, + NULL, + }, + { + "mult_qlen_th_en", + ETM_CGAVD_MULT_QLEN_TH_ENr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x12df, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_mult_qlen_th_en_reg, + NULL, + NULL, + }, + { + "mult_qlen_th", + ETM_CGAVD_MULT_QLEN_THr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x12e0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_mult_qlen_th_reg, + NULL, + NULL, + }, + { + "cgavd_cfg_move", + ETM_CGAVD_CGAVD_CFG_MOVEr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x12e1, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_etm_cgavd_cgavd_cfg_move_reg, + NULL, + NULL, + }, + { + "cfgmt_total_th", + ETM_CGAVD_CFGMT_TOTAL_THr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x12e2, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_cfgmt_total_th_reg, + NULL, + NULL, + }, + { + "cfgmt_port_share_th", + ETM_CGAVD_CFGMT_PORT_SHARE_THr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x12e3, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_cfgmt_port_share_th_reg, + NULL, + NULL, + }, + { + "sa_unreach_state", + ETM_CGAVD_SA_UNREACH_STATEr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x1300, + (32/8), + 0, + 0x3 + 1, + 0, + 0x1, + 1, + g_etm_cgavd_sa_unreach_state_reg, + NULL, + NULL, + }, + { + "mv_port_th", + ETM_CGAVD_MV_PORT_THr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x2000, + (32/8), + 0, + 0x3f + 1, + 0, + 0x1, + 1, + g_etm_cgavd_mv_port_th_reg, + NULL, + NULL, + }, + { + "mv_drop_sp_th", + ETM_CGAVD_MV_DROP_SP_THr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x3000, + (32/8), + 0, + 0x7 + 1, + 0, + 0x1, + 1, + g_etm_cgavd_mv_drop_sp_th_reg, + NULL, + NULL, + }, + { + "cgavd_state_warning", + ETM_CGAVD_CGAVD_STATE_WARNINGr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x250006, + (32/8), + 0, + 0, + 0, + 0, + 6, + g_etm_cgavd_cgavd_state_warning_reg, + NULL, + NULL, + }, + { + "tmmu_cgavd_dma_fifo_cnt", + ETM_CGAVD_TMMU_CGAVD_DMA_FIFO_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x250008, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_tmmu_cgavd_dma_fifo_cnt_reg, + NULL, + NULL, + }, + { + "tmmu_cgavd_dma_fifo_cnt_max", + ETM_CGAVD_TMMU_CGAVD_DMA_FIFO_CNT_MAXr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x250009, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_tmmu_cgavd_dma_fifo_cnt_max_reg, + NULL, + NULL, + }, + { + "imem_total_cnt", + ETM_CGAVD_IMEM_TOTAL_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x25000a, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_imem_total_cnt_reg, + NULL, + NULL, + }, + { + "imem_total_cnt_max", + ETM_CGAVD_IMEM_TOTAL_CNT_MAXr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x25000b, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_imem_total_cnt_max_reg, + NULL, + NULL, + }, + { + "flow0_omem_cnt", + ETM_CGAVD_FLOW0_OMEM_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x260020, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_flow0_omem_cnt_reg, + NULL, + NULL, + }, + { + "flow1_omem_cnt", + ETM_CGAVD_FLOW1_OMEM_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x260021, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_flow1_omem_cnt_reg, + NULL, + NULL, + }, + { + "flow2_omem_cnt", + ETM_CGAVD_FLOW2_OMEM_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x260022, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_flow2_omem_cnt_reg, + NULL, + NULL, + }, + { + "flow3_omem_cnt", + ETM_CGAVD_FLOW3_OMEM_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x260023, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_flow3_omem_cnt_reg, + NULL, + NULL, + }, + { + "flow4_omem_cnt", + ETM_CGAVD_FLOW4_OMEM_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x260024, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_flow4_omem_cnt_reg, + NULL, + NULL, + }, + { + "appoint_flow_num_message_1", + ETM_CGAVD_APPOINT_FLOW_NUM_MESSAGE_1r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x261000, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_etm_cgavd_appoint_flow_num_message_1_reg, + NULL, + NULL, + }, + { + "appoint_flow_num_message_2", + ETM_CGAVD_APPOINT_FLOW_NUM_MESSAGE_2r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x261001, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_etm_cgavd_appoint_flow_num_message_2_reg, + NULL, + NULL, + }, + { + "odma_cgavd_pkt_num_1", + ETM_CGAVD_ODMA_CGAVD_PKT_NUM_1r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x262000, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_odma_cgavd_pkt_num_1_reg, + NULL, + NULL, + }, + { + "odma_cgavd_byte_num_1", + ETM_CGAVD_ODMA_CGAVD_BYTE_NUM_1r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x262001, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_odma_cgavd_byte_num_1_reg, + NULL, + NULL, + }, + { + "cgavd_enqueue_pkt_num_1", + ETM_CGAVD_CGAVD_ENQUEUE_PKT_NUM_1r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x262002, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_cgavd_enqueue_pkt_num_1_reg, + NULL, + NULL, + }, + { + "cgavd_dequeue_pkt_num_1", + ETM_CGAVD_CGAVD_DEQUEUE_PKT_NUM_1r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x262003, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_cgavd_dequeue_pkt_num_1_reg, + NULL, + NULL, + }, + { + "cgavd_qmu_pkt_imem_num_1", + ETM_CGAVD_CGAVD_QMU_PKT_IMEM_NUM_1r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x262004, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_cgavd_qmu_pkt_imem_num_1_reg, + NULL, + NULL, + }, + { + "cgavd_qmu_pkt_omem_num_1", + ETM_CGAVD_CGAVD_QMU_PKT_OMEM_NUM_1r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x262005, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_cgavd_qmu_pkt_omem_num_1_reg, + NULL, + NULL, + }, + { + "cgavd_qmu_byte_imem_num_1", + ETM_CGAVD_CGAVD_QMU_BYTE_IMEM_NUM_1r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x262006, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_cgavd_qmu_byte_imem_num_1_reg, + NULL, + NULL, + }, + { + "cgavd_qmu_byte_omem_num_1", + ETM_CGAVD_CGAVD_QMU_BYTE_OMEM_NUM_1r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x262007, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_cgavd_qmu_byte_omem_num_1_reg, + NULL, + NULL, + }, + { + "cgavd_qmu_pkt_drop_num_1", + ETM_CGAVD_CGAVD_QMU_PKT_DROP_NUM_1r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x262008, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_cgavd_qmu_pkt_drop_num_1_reg, + NULL, + NULL, + }, + { + "cgavd_qmu_byte_drop_num_1", + ETM_CGAVD_CGAVD_QMU_BYTE_DROP_NUM_1r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x262009, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_cgavd_qmu_byte_drop_num_1_reg, + NULL, + NULL, + }, + { + "cgavd_qmu_forbid_drop_num_1", + ETM_CGAVD_CGAVD_QMU_FORBID_DROP_NUM_1r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x262010, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_cgavd_qmu_forbid_drop_num_1_reg, + NULL, + NULL, + }, + { + "cgavd_qmu_flow_td_drop_num_1", + ETM_CGAVD_CGAVD_QMU_FLOW_TD_DROP_NUM_1r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x262011, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_cgavd_qmu_flow_td_drop_num_1_reg, + NULL, + NULL, + }, + { + "cgavd_qmu_flow_wred_drop_num_1", + ETM_CGAVD_CGAVD_QMU_FLOW_WRED_DROP_NUM_1r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x262012, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_cgavd_qmu_flow_wred_drop_num_1_reg, + NULL, + NULL, + }, + { + "cgavd_qmu_flow_wred_dp_drop_num_1", + ETM_CGAVD_CGAVD_QMU_FLOW_WRED_DP_DROP_NUM_1r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x262100, + (32/8), + 0, + 0x7 + 1, + 0, + 0x1, + 1, + g_etm_cgavd_cgavd_qmu_flow_wred_dp_drop_num_1_reg, + NULL, + NULL, + }, + { + "cgavd_qmu_pp_td_num_1", + ETM_CGAVD_CGAVD_QMU_PP_TD_NUM_1r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x262200, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_cgavd_qmu_pp_td_num_1_reg, + NULL, + NULL, + }, + { + "cgavd_qmu_pp_wred_drop_num_1", + ETM_CGAVD_CGAVD_QMU_PP_WRED_DROP_NUM_1r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x262201, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_cgavd_qmu_pp_wred_drop_num_1_reg, + NULL, + NULL, + }, + { + "cgavd_qmu_pp_wred_dp_drop_num_1", + ETM_CGAVD_CGAVD_QMU_PP_WRED_DP_DROP_NUM_1r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x262300, + (32/8), + 0, + 0x7 + 1, + 0, + 0x1, + 1, + g_etm_cgavd_cgavd_qmu_pp_wred_dp_drop_num_1_reg, + NULL, + NULL, + }, + { + "cgavd_qmu_sys_td_drop_num_1", + ETM_CGAVD_CGAVD_QMU_SYS_TD_DROP_NUM_1r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x262400, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_cgavd_qmu_sys_td_drop_num_1_reg, + NULL, + NULL, + }, + { + "cgavd_qmu_sys_gred_drop_num_1", + ETM_CGAVD_CGAVD_QMU_SYS_GRED_DROP_NUM_1r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x262401, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_cgavd_qmu_sys_gred_drop_num_1_reg, + NULL, + NULL, + }, + { + "cgavd_qmu_sys_gred_dp_drop_num1", + ETM_CGAVD_CGAVD_QMU_SYS_GRED_DP_DROP_NUM1r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x262500, + (32/8), + 0, + 0x7 + 1, + 0, + 0x1, + 1, + g_etm_cgavd_cgavd_qmu_sys_gred_dp_drop_num1_reg, + NULL, + NULL, + }, + { + "cgavd_qmu_sa_drop_num_1", + ETM_CGAVD_CGAVD_QMU_SA_DROP_NUM_1r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x262600, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_cgavd_qmu_sa_drop_num_1_reg, + NULL, + NULL, + }, + { + "cgavd_qmu_move_drop_num_1", + ETM_CGAVD_CGAVD_QMU_MOVE_DROP_NUM_1r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x262601, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_cgavd_qmu_move_drop_num_1_reg, + NULL, + NULL, + }, + { + "cgavd_qmu_tm_mult_drop_num_1", + ETM_CGAVD_CGAVD_QMU_TM_MULT_DROP_NUM_1r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x262602, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_cgavd_qmu_tm_mult_drop_num_1_reg, + NULL, + NULL, + }, + { + "cgavd_qmu_tm_error_drop_num_1", + ETM_CGAVD_CGAVD_QMU_TM_ERROR_DROP_NUM_1r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x262603, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_cgavd_qmu_tm_error_drop_num_1_reg, + NULL, + NULL, + }, + { + "odma_cgavd_pkt_num_2", + ETM_CGAVD_ODMA_CGAVD_PKT_NUM_2r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x263000, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_odma_cgavd_pkt_num_2_reg, + NULL, + NULL, + }, + { + "odma_cgavd_byte_num_2", + ETM_CGAVD_ODMA_CGAVD_BYTE_NUM_2r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x263001, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_odma_cgavd_byte_num_2_reg, + NULL, + NULL, + }, + { + "cgavd_enqueue_pkt_num_2", + ETM_CGAVD_CGAVD_ENQUEUE_PKT_NUM_2r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x263002, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_cgavd_enqueue_pkt_num_2_reg, + NULL, + NULL, + }, + { + "cgavd_dequeue_pkt_num_2", + ETM_CGAVD_CGAVD_DEQUEUE_PKT_NUM_2r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x263003, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_cgavd_dequeue_pkt_num_2_reg, + NULL, + NULL, + }, + { + "cgavd_qmu_pkt_imem_num_2", + ETM_CGAVD_CGAVD_QMU_PKT_IMEM_NUM_2r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x263004, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_cgavd_qmu_pkt_imem_num_2_reg, + NULL, + NULL, + }, + { + "cgavd_qmu_pkt_omem_num_2", + ETM_CGAVD_CGAVD_QMU_PKT_OMEM_NUM_2r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x263005, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_cgavd_qmu_pkt_omem_num_2_reg, + NULL, + NULL, + }, + { + "cgavd_qmu_byte_imem_num_2", + ETM_CGAVD_CGAVD_QMU_BYTE_IMEM_NUM_2r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x263006, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_cgavd_qmu_byte_imem_num_2_reg, + NULL, + NULL, + }, + { + "cgavd_qmu_byte_omem_num_2", + ETM_CGAVD_CGAVD_QMU_BYTE_OMEM_NUM_2r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x263007, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_cgavd_qmu_byte_omem_num_2_reg, + NULL, + NULL, + }, + { + "cgavd_qmu_pkt_drop_num_2", + ETM_CGAVD_CGAVD_QMU_PKT_DROP_NUM_2r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x263008, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_cgavd_qmu_pkt_drop_num_2_reg, + NULL, + NULL, + }, + { + "cgavd_qmu_byte_drop_num_2", + ETM_CGAVD_CGAVD_QMU_BYTE_DROP_NUM_2r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x263009, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_cgavd_qmu_byte_drop_num_2_reg, + NULL, + NULL, + }, + { + "cgavd_qmu_forbid_drop_num_2", + ETM_CGAVD_CGAVD_QMU_FORBID_DROP_NUM_2r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x263010, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_cgavd_qmu_forbid_drop_num_2_reg, + NULL, + NULL, + }, + { + "cgavd_qmu_flow_td_drop_num_2", + ETM_CGAVD_CGAVD_QMU_FLOW_TD_DROP_NUM_2r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x263011, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_cgavd_qmu_flow_td_drop_num_2_reg, + NULL, + NULL, + }, + { + "cgavd_qmu_flow_wred_drop_num_2", + ETM_CGAVD_CGAVD_QMU_FLOW_WRED_DROP_NUM_2r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x263012, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_cgavd_qmu_flow_wred_drop_num_2_reg, + NULL, + NULL, + }, + { + "cgavd_qmu_flow_wred_dp_drop_num_2", + ETM_CGAVD_CGAVD_QMU_FLOW_WRED_DP_DROP_NUM_2r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x263100, + (32/8), + 0, + 0x7 + 1, + 0, + 0x1, + 1, + g_etm_cgavd_cgavd_qmu_flow_wred_dp_drop_num_2_reg, + NULL, + NULL, + }, + { + "cgavd_qmu_pp_td_num_2", + ETM_CGAVD_CGAVD_QMU_PP_TD_NUM_2r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x263200, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_cgavd_qmu_pp_td_num_2_reg, + NULL, + NULL, + }, + { + "cgavd_qmu_pp_wred_drop_num_2", + ETM_CGAVD_CGAVD_QMU_PP_WRED_DROP_NUM_2r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x263201, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_cgavd_qmu_pp_wred_drop_num_2_reg, + NULL, + NULL, + }, + { + "cgavd_qmu_pp_wred_dp_drop_num_2", + ETM_CGAVD_CGAVD_QMU_PP_WRED_DP_DROP_NUM_2r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x263300, + (32/8), + 0, + 0x7 + 1, + 0, + 0x1, + 1, + g_etm_cgavd_cgavd_qmu_pp_wred_dp_drop_num_2_reg, + NULL, + NULL, + }, + { + "cgavd_qmu_sys_td_drop_num_2", + ETM_CGAVD_CGAVD_QMU_SYS_TD_DROP_NUM_2r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x263400, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_cgavd_qmu_sys_td_drop_num_2_reg, + NULL, + NULL, + }, + { + "cgavd_qmu_sys_gred_drop_num_2", + ETM_CGAVD_CGAVD_QMU_SYS_GRED_DROP_NUM_2r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x263401, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_cgavd_qmu_sys_gred_drop_num_2_reg, + NULL, + NULL, + }, + { + "cgavd_qmu_sys_gred_dp_drop_num_2", + ETM_CGAVD_CGAVD_QMU_SYS_GRED_DP_DROP_NUM_2r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x263500, + (32/8), + 0, + 0x7 + 1, + 0, + 0x1, + 1, + g_etm_cgavd_cgavd_qmu_sys_gred_dp_drop_num_2_reg, + NULL, + NULL, + }, + { + "cgavd_qmu_sa_drop_num_2", + ETM_CGAVD_CGAVD_QMU_SA_DROP_NUM_2r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x263600, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_cgavd_qmu_sa_drop_num_2_reg, + NULL, + NULL, + }, + { + "cgavd_qmu_move_drop_num_2", + ETM_CGAVD_CGAVD_QMU_MOVE_DROP_NUM_2r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x263601, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_cgavd_qmu_move_drop_num_2_reg, + NULL, + NULL, + }, + { + "cgavd_qmu_tm_mult_drop_num_2", + ETM_CGAVD_CGAVD_QMU_TM_MULT_DROP_NUM_2r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x263602, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_cgavd_qmu_tm_mult_drop_num_2_reg, + NULL, + NULL, + }, + { + "cgavd_qmu_tm_error_drop_num_2", + ETM_CGAVD_CGAVD_QMU_TM_ERROR_DROP_NUM_2r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x263603, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_cgavd_cgavd_qmu_tm_error_drop_num_2_reg, + NULL, + NULL, + }, + { + "move_flow_th_profile", + ETM_CGAVD_MOVE_FLOW_TH_PROFILEr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x270000, + (32/8), + 0, + 0x23FF + 1, + 0, + 0x1, + 1, + g_etm_cgavd_move_flow_th_profile_reg, + NULL, + NULL, + }, + { + "move_flow_th", + ETM_CGAVD_MOVE_FLOW_THr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x280000, + (32/8), + 0, + 0xF + 1, + 0, + 0x1, + 1, + g_etm_cgavd_move_flow_th_reg, + NULL, + NULL, + }, + { + "emem_pd_fifo_aful_th", + ETM_TMMU_EMEM_PD_FIFO_AFUL_THr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0009, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_emem_pd_fifo_aful_th_reg, + NULL, + NULL, + }, + { + "dma_data_fifo_aful_th", + ETM_TMMU_DMA_DATA_FIFO_AFUL_THr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x000a, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_dma_data_fifo_aful_th_reg, + NULL, + NULL, + }, + { + "tmmu_states_0", + ETM_TMMU_TMMU_STATES_0r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0010, + (32/8), + 0, + 0, + 0, + 0, + 31, + g_etm_tmmu_tmmu_states_0_reg, + NULL, + NULL, + }, + { + "qmu_tmmu_wr_sop_cnt", + ETM_TMMU_QMU_TMMU_WR_SOP_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0013, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_qmu_tmmu_wr_sop_cnt_reg, + NULL, + NULL, + }, + { + "qmu_tmmu_wr_eop_cnt", + ETM_TMMU_QMU_TMMU_WR_EOP_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0014, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_qmu_tmmu_wr_eop_cnt_reg, + NULL, + NULL, + }, + { + "qmu_tmmu_wr_drop_cnt", + ETM_TMMU_QMU_TMMU_WR_DROP_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0015, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_qmu_tmmu_wr_drop_cnt_reg, + NULL, + NULL, + }, + { + "qmu_tmmu_wr_emem_cnt", + ETM_TMMU_QMU_TMMU_WR_EMEM_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0016, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_qmu_tmmu_wr_emem_cnt_reg, + NULL, + NULL, + }, + { + "qmu_tmmu_wr_imem_cnt", + ETM_TMMU_QMU_TMMU_WR_IMEM_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0017, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_qmu_tmmu_wr_imem_cnt_reg, + NULL, + NULL, + }, + { + "tmmu_mmu_wr_sop_cnt", + ETM_TMMU_TMMU_MMU_WR_SOP_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0018, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_tmmu_mmu_wr_sop_cnt_reg, + NULL, + NULL, + }, + { + "tmmu_mmu_wr_eop_cnt", + ETM_TMMU_TMMU_MMU_WR_EOP_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0019, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_tmmu_mmu_wr_eop_cnt_reg, + NULL, + NULL, + }, + { + "qmu_tmmu_rd_sop_cnt", + ETM_TMMU_QMU_TMMU_RD_SOP_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x001a, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_qmu_tmmu_rd_sop_cnt_reg, + NULL, + NULL, + }, + { + "qmu_tmmu_rd_eop_cnt", + ETM_TMMU_QMU_TMMU_RD_EOP_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x001b, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_qmu_tmmu_rd_eop_cnt_reg, + NULL, + NULL, + }, + { + "qmu_tmmu_rd_drop_cnt", + ETM_TMMU_QMU_TMMU_RD_DROP_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x001c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_qmu_tmmu_rd_drop_cnt_reg, + NULL, + NULL, + }, + { + "qmu_tmmu_rd_emem_cnt", + ETM_TMMU_QMU_TMMU_RD_EMEM_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x001d, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_qmu_tmmu_rd_emem_cnt_reg, + NULL, + NULL, + }, + { + "qmu_tmmu_rd_imem_cnt", + ETM_TMMU_QMU_TMMU_RD_IMEM_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x001e, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_qmu_tmmu_rd_imem_cnt_reg, + NULL, + NULL, + }, + { + "tmmu_mmu_rd_sop_cnt", + ETM_TMMU_TMMU_MMU_RD_SOP_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x001f, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_tmmu_mmu_rd_sop_cnt_reg, + NULL, + NULL, + }, + { + "tmmu_mmu_rd_eop_cnt", + ETM_TMMU_TMMU_MMU_RD_EOP_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0020, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_tmmu_mmu_rd_eop_cnt_reg, + NULL, + NULL, + }, + { + "tmmu_odma_in_sop_cnt", + ETM_TMMU_TMMU_ODMA_IN_SOP_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0021, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_tmmu_odma_in_sop_cnt_reg, + NULL, + NULL, + }, + { + "tmmu_odma_in_eop_cnt", + ETM_TMMU_TMMU_ODMA_IN_EOP_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0022, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_tmmu_odma_in_eop_cnt_reg, + NULL, + NULL, + }, + { + "tmmu_odma_vld_cnt", + ETM_TMMU_TMMU_ODMA_VLD_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0023, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_tmmu_odma_vld_cnt_reg, + NULL, + NULL, + }, + { + "qmu_pd_in_cnt", + ETM_TMMU_QMU_PD_IN_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0024, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_qmu_pd_in_cnt_reg, + NULL, + NULL, + }, + { + "tmmu_pd_hit_cnt", + ETM_TMMU_TMMU_PD_HIT_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0025, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_tmmu_pd_hit_cnt_reg, + NULL, + NULL, + }, + { + "tmmu_pd_out_cnt", + ETM_TMMU_TMMU_PD_OUT_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0026, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_tmmu_pd_out_cnt_reg, + NULL, + NULL, + }, + { + "tmmu_wr_cmd_fifo_wr_cnt", + ETM_TMMU_TMMU_WR_CMD_FIFO_WR_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0027, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_tmmu_wr_cmd_fifo_wr_cnt_reg, + NULL, + NULL, + }, + { + "tmmu_imem_age_cnt", + ETM_TMMU_TMMU_IMEM_AGE_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0028, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_tmmu_imem_age_cnt_reg, + NULL, + NULL, + }, + { + "tmmu_cmdsch_rd_cnt", + ETM_TMMU_TMMU_CMDSCH_RD_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0029, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_tmmu_cmdsch_rd_cnt_reg, + NULL, + NULL, + }, + { + "tmmu_cmdsch_drop_cnt", + ETM_TMMU_TMMU_CMDSCH_DROP_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x002a, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_tmmu_cmdsch_drop_cnt_reg, + NULL, + NULL, + }, + { + "tmmu_cmdsw_drop_cnt", + ETM_TMMU_TMMU_CMDSW_DROP_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x002b, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_tmmu_cmdsw_drop_cnt_reg, + NULL, + NULL, + }, + { + "tmmu_odma_enq_rd_cnt", + ETM_TMMU_TMMU_ODMA_ENQ_RD_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x002c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_tmmu_odma_enq_rd_cnt_reg, + NULL, + NULL, + }, + { + "tmmu_odma_enq_drop_cnt", + ETM_TMMU_TMMU_ODMA_ENQ_DROP_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x002d, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_tmmu_odma_enq_drop_cnt_reg, + NULL, + NULL, + }, + { + "tmmu_odma_imem_age_cnt", + ETM_TMMU_TMMU_ODMA_IMEM_AGE_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x002e, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_tmmu_odma_imem_age_cnt_reg, + NULL, + NULL, + }, + { + "tmmu_odma_deq_rd_cnt", + ETM_TMMU_TMMU_ODMA_DEQ_RD_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x002f, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_tmmu_odma_deq_rd_cnt_reg, + NULL, + NULL, + }, + { + "tmmu_odma_deq_drop_cnt", + ETM_TMMU_TMMU_ODMA_DEQ_DROP_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0030, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_tmmu_odma_deq_drop_cnt_reg, + NULL, + NULL, + }, + { + "olif_tmmu_xoff_cnt", + ETM_TMMU_OLIF_TMMU_XOFF_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0031, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_olif_tmmu_xoff_cnt_reg, + NULL, + NULL, + }, + { + "odma_tm_data_xoff_cnt", + ETM_TMMU_ODMA_TM_DATA_XOFF_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0032, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_odma_tm_data_xoff_cnt_reg, + NULL, + NULL, + }, + { + "tm_odma_pkt_xoff_cnt", + ETM_TMMU_TM_ODMA_PKT_XOFF_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0033, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_tm_odma_pkt_xoff_cnt_reg, + NULL, + NULL, + }, + { + "tm_state_3", + ETM_TMMU_TM_STATE_3r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0034, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_etm_tmmu_tm_state_3_reg, + NULL, + NULL, + }, + { + "cfgmt_pd_cache_cmd", + ETM_TMMU_CFGMT_PD_CACHE_CMDr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0050, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_cfgmt_pd_cache_cmd_reg, + NULL, + NULL, + }, + { + "cfgmt_pd_cache_rd_done", + ETM_TMMU_CFGMT_PD_CACHE_RD_DONEr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0051, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_cfgmt_pd_cache_rd_done_reg, + NULL, + NULL, + }, + { + "cfgmt_pd_cache_rd_data_0", + ETM_TMMU_CFGMT_PD_CACHE_RD_DATA_0r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0052, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_cfgmt_pd_cache_rd_data_0_reg, + NULL, + NULL, + }, + { + "cfgmt_pd_cache_rd_data_1", + ETM_TMMU_CFGMT_PD_CACHE_RD_DATA_1r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0053, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_cfgmt_pd_cache_rd_data_1_reg, + NULL, + NULL, + }, + { + "cfgmt_pd_cache_rd_data_2", + ETM_TMMU_CFGMT_PD_CACHE_RD_DATA_2r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0054, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_cfgmt_pd_cache_rd_data_2_reg, + NULL, + NULL, + }, + { + "cfgmt_pd_cache_rd_data_3", + ETM_TMMU_CFGMT_PD_CACHE_RD_DATA_3r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0055, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_cfgmt_pd_cache_rd_data_3_reg, + NULL, + NULL, + }, + { + "cfgmt_tmmu_to_odma_para", + ETM_TMMU_CFGMT_TMMU_TO_ODMA_PARAr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0056, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_cfgmt_tmmu_to_odma_para_reg, + NULL, + NULL, + }, + { + "cfgmt_dma_data_fifo_cnt", + ETM_TMMU_CFGMT_DMA_DATA_FIFO_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0057, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_cfgmt_dma_data_fifo_cnt_reg, + NULL, + NULL, + }, + { + "cfgmt_cache_tag_bit0_offset", + ETM_TMMU_CFGMT_CACHE_TAG_BIT0_OFFSETr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0060, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_cfgmt_cache_tag_bit0_offset_reg, + NULL, + NULL, + }, + { + "cfgmt_cache_tag_bit1_offset", + ETM_TMMU_CFGMT_CACHE_TAG_BIT1_OFFSETr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0061, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_cfgmt_cache_tag_bit1_offset_reg, + NULL, + NULL, + }, + { + "cfgmt_cache_tag_bit2_offset", + ETM_TMMU_CFGMT_CACHE_TAG_BIT2_OFFSETr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0062, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_cfgmt_cache_tag_bit2_offset_reg, + NULL, + NULL, + }, + { + "cfgmt_cache_tag_bit3_offset", + ETM_TMMU_CFGMT_CACHE_TAG_BIT3_OFFSETr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0063, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_cfgmt_cache_tag_bit3_offset_reg, + NULL, + NULL, + }, + { + "cfgmt_cache_tag_bit4_offset", + ETM_TMMU_CFGMT_CACHE_TAG_BIT4_OFFSETr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0064, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_cfgmt_cache_tag_bit4_offset_reg, + NULL, + NULL, + }, + { + "cfgmt_cache_tag_bit5_offset", + ETM_TMMU_CFGMT_CACHE_TAG_BIT5_OFFSETr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0065, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_cfgmt_cache_tag_bit5_offset_reg, + NULL, + NULL, + }, + { + "cfgmt_cache_index_bit0_offset", + ETM_TMMU_CFGMT_CACHE_INDEX_BIT0_OFFSETr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0066, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_cfgmt_cache_index_bit0_offset_reg, + NULL, + NULL, + }, + { + "cfgmt_cache_index_bit1_offset", + ETM_TMMU_CFGMT_CACHE_INDEX_BIT1_OFFSETr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0067, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_cfgmt_cache_index_bit1_offset_reg, + NULL, + NULL, + }, + { + "cfgmt_cache_index_bit2_offset", + ETM_TMMU_CFGMT_CACHE_INDEX_BIT2_OFFSETr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0068, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_cfgmt_cache_index_bit2_offset_reg, + NULL, + NULL, + }, + { + "cfgmt_cache_index_bit3_offset", + ETM_TMMU_CFGMT_CACHE_INDEX_BIT3_OFFSETr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0069, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_cfgmt_cache_index_bit3_offset_reg, + NULL, + NULL, + }, + { + "cfgmt_cache_index_bit4_offset", + ETM_TMMU_CFGMT_CACHE_INDEX_BIT4_OFFSETr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x006a, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_cfgmt_cache_index_bit4_offset_reg, + NULL, + NULL, + }, + { + "cfgmt_cache_index_bit5_offset", + ETM_TMMU_CFGMT_CACHE_INDEX_BIT5_OFFSETr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x006b, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_cfgmt_cache_index_bit5_offset_reg, + NULL, + NULL, + }, + { + "cfgmt_cache_index_bit6_offset", + ETM_TMMU_CFGMT_CACHE_INDEX_BIT6_OFFSETr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x006c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_cfgmt_cache_index_bit6_offset_reg, + NULL, + NULL, + }, + { + "cfgmt_cache_index_bit7_offset", + ETM_TMMU_CFGMT_CACHE_INDEX_BIT7_OFFSETr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x006d, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_cfgmt_cache_index_bit7_offset_reg, + NULL, + NULL, + }, + { + "cfgmt_cache_index_bit8_offset", + ETM_TMMU_CFGMT_CACHE_INDEX_BIT8_OFFSETr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x006e, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_cfgmt_cache_index_bit8_offset_reg, + NULL, + NULL, + }, + { + "cfgmt_cache_index_bit9_offset", + ETM_TMMU_CFGMT_CACHE_INDEX_BIT9_OFFSETr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x006f, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_cfgmt_cache_index_bit9_offset_reg, + NULL, + NULL, + }, + { + "cfgmt_cache_index_bit10_offset", + ETM_TMMU_CFGMT_CACHE_INDEX_BIT10_OFFSETr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0070, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_cfgmt_cache_index_bit10_offset_reg, + NULL, + NULL, + }, + { + "cfgmt_cache_index_bit11_offset", + ETM_TMMU_CFGMT_CACHE_INDEX_BIT11_OFFSETr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0071, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_cfgmt_cache_index_bit11_offset_reg, + NULL, + NULL, + }, + { + "cfgmt_cache_index_bit12_offset", + ETM_TMMU_CFGMT_CACHE_INDEX_BIT12_OFFSETr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0072, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_tmmu_cfgmt_cache_index_bit12_offset_reg, + NULL, + NULL, + }, + { + "bktfull_fifo_full_flagregister", + ETM_SHAP_BKTFULL_FIFO_FULL_FLAGREGISTERr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x26, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_shap_bktfull_fifo_full_flagregister_reg, + NULL, + NULL, + }, + { + "fifo_full_regregister", + ETM_SHAP_FIFO_FULL_REGREGISTERr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x29, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_shap_fifo_full_regregister_reg, + NULL, + NULL, + }, + { + "fifo_empty_regregister", + ETM_SHAP_FIFO_EMPTY_REGREGISTERr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_shap_fifo_empty_regregister_reg, + NULL, + NULL, + }, + { + "fifo_almost_full_regregister", + ETM_SHAP_FIFO_ALMOST_FULL_REGREGISTERr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2f, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_shap_fifo_almost_full_regregister_reg, + NULL, + NULL, + }, + { + "fifo_almost_empty_regregister", + ETM_SHAP_FIFO_ALMOST_EMPTY_REGREGISTERr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x32, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_shap_fifo_almost_empty_regregister_reg, + NULL, + NULL, + }, + { + "credit_space_select", + ETM_CRDT_CREDIT_SPACE_SELECTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x000e, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_credit_space_select_reg, + NULL, + NULL, + }, + { + "stat_space_max", + ETM_CRDT_STAT_SPACE_MAXr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x30, + (32/8), + 0, + 0x0f + 1, + 0, + 1, + 1, + g_etm_crdt_stat_space_max_reg, + NULL, + NULL, + }, + { + "stat_space_min", + ETM_CRDT_STAT_SPACE_MINr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x40, + (32/8), + 0, + 0x0f + 1, + 0, + 1, + 1, + g_etm_crdt_stat_space_min_reg, + NULL, + NULL, + }, + { + "stat_space_credit", + ETM_CRDT_STAT_SPACE_CREDITr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x50, + (32/8), + 0, + 0x0f + 1, + 0, + 1, + 1, + g_etm_crdt_stat_space_credit_reg, + NULL, + NULL, + }, + { + "stat_que_step8_credit", + ETM_CRDT_STAT_QUE_STEP8_CREDITr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x60, + (32/8), + 0, + 0x07 + 1, + 0, + 1, + 1, + g_etm_crdt_stat_que_step8_credit_reg, + NULL, + NULL, + }, + { + "special_que", + ETM_CRDT_SPECIAL_QUEr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x68, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_special_que_reg, + NULL, + NULL, + }, + { + "special_que_credit", + ETM_CRDT_SPECIAL_QUE_CREDITr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x69, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_special_que_credit_reg, + NULL, + NULL, + }, + { + "lif_congest_credit_cnt", + ETM_CRDT_LIF_CONGEST_CREDIT_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x70, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_lif_congest_credit_cnt_reg, + NULL, + NULL, + }, + { + "lif_port_congest_credit_cnt", + ETM_CRDT_LIF_PORT_CONGEST_CREDIT_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x71, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_lif_port_congest_credit_cnt_reg, + NULL, + NULL, + }, + { + "crdt_congest_credit_cnt", + ETM_CRDT_CRDT_CONGEST_CREDIT_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x72, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_crdt_congest_credit_cnt_reg, + NULL, + NULL, + }, + { + "crdt_port_congest_credit_cnt", + ETM_CRDT_CRDT_PORT_CONGEST_CREDIT_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x73, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_crdt_port_congest_credit_cnt_reg, + NULL, + NULL, + }, + { + "congest_port_id", + ETM_CRDT_CONGEST_PORT_IDr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x74, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_congest_port_id_reg, + NULL, + NULL, + }, + { + "dev_link_control", + ETM_CRDT_DEV_LINK_CONTROLr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x75, + (32/8), + 0, + 0x1 + 1, + 0, + 1, + 1, + g_etm_crdt_dev_link_control_reg, + NULL, + NULL, + }, + { + "crdt_sa_port_rdy", + ETM_CRDT_CRDT_SA_PORT_RDYr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x77, + (32/8), + 0, + 0x1 + 1, + 0, + 1, + 1, + g_etm_crdt_crdt_sa_port_rdy_reg, + NULL, + NULL, + }, + { + "crdt_congest_mode_select", + ETM_CRDT_CRDT_CONGEST_MODE_SELECTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x81, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_crdt_congest_mode_select_reg, + NULL, + NULL, + }, + { + "fifo_out_all_crs_normal_cnt", + ETM_CRDT_FIFO_OUT_ALL_CRS_NORMAL_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x82, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_fifo_out_all_crs_normal_cnt_reg, + NULL, + NULL, + }, + { + "fifo_out_all_crs_off_cnt", + ETM_CRDT_FIFO_OUT_ALL_CRS_OFF_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x83, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_fifo_out_all_crs_off_cnt_reg, + NULL, + NULL, + }, + { + "fifo_out_que_crs_normal_cnt", + ETM_CRDT_FIFO_OUT_QUE_CRS_NORMAL_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x84, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_fifo_out_que_crs_normal_cnt_reg, + NULL, + NULL, + }, + { + "fifo_out_que_crs_off_cnt", + ETM_CRDT_FIFO_OUT_QUE_CRS_OFF_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x85, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_fifo_out_que_crs_off_cnt_reg, + NULL, + NULL, + }, + { + "mode_add_60g", + ETM_CRDT_MODE_ADD_60Gr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x9a, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_mode_add_60g_reg, + NULL, + NULL, + }, + { + "pp_token_add", + ETM_CRDT_PP_TOKEN_ADDr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x9b, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_pp_token_add_reg, + NULL, + NULL, + }, + { + "pp_cir_token_total_dist_cnt", + ETM_CRDT_PP_CIR_TOKEN_TOTAL_DIST_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x9c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_pp_cir_token_total_dist_cnt_reg, + NULL, + NULL, + }, + { + "pp_cir_token_total_dec_cnt", + ETM_CRDT_PP_CIR_TOKEN_TOTAL_DEC_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x9d, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_pp_cir_token_total_dec_cnt_reg, + NULL, + NULL, + }, + { + "dev_credit_cnt", + ETM_CRDT_DEV_CREDIT_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0xb0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_dev_credit_cnt_reg, + NULL, + NULL, + }, + { + "no_credit_cnt1", + ETM_CRDT_NO_CREDIT_CNT1r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0xb7, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_no_credit_cnt1_reg, + NULL, + NULL, + }, + { + "no_credit_cnt2", + ETM_CRDT_NO_CREDIT_CNT2r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0xb8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_no_credit_cnt2_reg, + NULL, + NULL, + }, + { + "asm_interval_0_cfg", + ETM_CRDT_ASM_INTERVAL_0_CFGr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0xc7, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_asm_interval_0_cfg_reg, + NULL, + NULL, + }, + { + "asm_interval_1_cfg", + ETM_CRDT_ASM_INTERVAL_1_CFGr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0xc8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_asm_interval_1_cfg_reg, + NULL, + NULL, + }, + { + "asm_interval_2_cfg", + ETM_CRDT_ASM_INTERVAL_2_CFGr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0xc9, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_asm_interval_2_cfg_reg, + NULL, + NULL, + }, + { + "asm_interval_3_cfg", + ETM_CRDT_ASM_INTERVAL_3_CFGr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0xca, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_asm_interval_3_cfg_reg, + NULL, + NULL, + }, + { + "asm_interval_4_cfg", + ETM_CRDT_ASM_INTERVAL_4_CFGr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0xcb, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_asm_interval_4_cfg_reg, + NULL, + NULL, + }, + { + "asm_interval_5cfg", + ETM_CRDT_ASM_INTERVAL_5CFGr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0xcc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_asm_interval_5cfg_reg, + NULL, + NULL, + }, + { + "asm_interval_6_cfg", + ETM_CRDT_ASM_INTERVAL_6_CFGr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0xcd, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_asm_interval_6_cfg_reg, + NULL, + NULL, + }, + { + "asm_interval_7_cfg", + ETM_CRDT_ASM_INTERVAL_7_CFGr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0xce, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_asm_interval_7_cfg_reg, + NULL, + NULL, + }, + { + "crdt_total_congest_mode_cfg", + ETM_CRDT_CRDT_TOTAL_CONGEST_MODE_CFGr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0xcf, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_crdt_total_congest_mode_cfg_reg, + NULL, + NULL, + }, + { + "rci_fifo_ini_deep_cfg", + ETM_CRDT_RCI_FIFO_INI_DEEP_CFGr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0xd0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_rci_fifo_ini_deep_cfg_reg, + NULL, + NULL, + }, + { + "crdt_ecc", + ETM_CRDT_CRDT_ECCr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x121, + (32/8), + 0, + 0, + 0, + 0, + 5, + g_etm_crdt_crdt_ecc_reg, + NULL, + NULL, + }, + { + "ucn_asm_rdy_shield_en", + ETM_CRDT_UCN_ASM_RDY_SHIELD_ENr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x013a, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_etm_crdt_ucn_asm_rdy_shield_en_reg, + NULL, + NULL, + }, + { + "ucn_asm_rdy", + ETM_CRDT_UCN_ASM_RDYr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x013b, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_etm_crdt_ucn_asm_rdy_reg, + NULL, + NULL, + }, + { + "rci_grade", + ETM_CRDT_RCI_GRADEr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x013c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_rci_grade_reg, + NULL, + NULL, + }, + { + "crdt_rci_value_r", + ETM_CRDT_CRDT_RCI_VALUE_Rr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x013d, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_crdt_rci_value_r_reg, + NULL, + NULL, + }, + { + "crdt_interval_now", + ETM_CRDT_CRDT_INTERVAL_NOWr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x013e, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_crdt_interval_now_reg, + NULL, + NULL, + }, + { + "crs_sheild_flow_id_cfg", + ETM_CRDT_CRS_SHEILD_FLOW_ID_CFGr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0140, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_crs_sheild_flow_id_cfg_reg, + NULL, + NULL, + }, + { + "crs_sheild_en_cfg", + ETM_CRDT_CRS_SHEILD_EN_CFGr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0141, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_crs_sheild_en_cfg_reg, + NULL, + NULL, + }, + { + "crs_sheild_value_cfg", + ETM_CRDT_CRS_SHEILD_VALUE_CFGr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x0142, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_crs_sheild_value_cfg_reg, + NULL, + NULL, + }, + { + "test_token_calc_ctrl", + ETM_CRDT_TEST_TOKEN_CALC_CTRLr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x14c, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_etm_crdt_test_token_calc_ctrl_reg, + NULL, + NULL, + }, + { + "test_token_sample_cycle_num", + ETM_CRDT_TEST_TOKEN_SAMPLE_CYCLE_NUMr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x14d, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_crdt_test_token_sample_cycle_num_reg, + NULL, + NULL, + }, + { + "q_state_0_7", + ETM_CRDT_Q_STATE_0_7r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x14e, + (32/8), + 0, + 0, + 0, + 0, + 8, + g_etm_crdt_q_state_0_7_reg, + NULL, + NULL, + }, + { + "q_state_8_15", + ETM_CRDT_Q_STATE_8_15r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x14f, + (32/8), + 0, + 0, + 0, + 0, + 8, + g_etm_crdt_q_state_8_15_reg, + NULL, + NULL, + }, + { + "csw_csch_rd_cmd_cnt", + ETM_QMU_CSW_CSCH_RD_CMD_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x14, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_csw_csch_rd_cmd_cnt_reg, + NULL, + NULL, + }, + { + "csw_csch_rd_sop_cnt", + ETM_QMU_CSW_CSCH_RD_SOP_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x15, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_csw_csch_rd_sop_cnt_reg, + NULL, + NULL, + }, + { + "csw_csch_rd_eop_cnt", + ETM_QMU_CSW_CSCH_RD_EOP_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x16, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_csw_csch_rd_eop_cnt_reg, + NULL, + NULL, + }, + { + "csw_csch_rd_drop_cnt", + ETM_QMU_CSW_CSCH_RD_DROP_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x17, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_csw_csch_rd_drop_cnt_reg, + NULL, + NULL, + }, + { + "csch_mmu_rd_cmd_cnt", + ETM_QMU_CSCH_MMU_RD_CMD_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x18, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_csch_mmu_rd_cmd_cnt_reg, + NULL, + NULL, + }, + { + "csch_mmu_rd_sop_cnt", + ETM_QMU_CSCH_MMU_RD_SOP_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x19, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_csch_mmu_rd_sop_cnt_reg, + NULL, + NULL, + }, + { + "csch_mmu_rd_eop_cnt", + ETM_QMU_CSCH_MMU_RD_EOP_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x1a, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_csch_mmu_rd_eop_cnt_reg, + NULL, + NULL, + }, + { + "csch_mmu_rd_drop_cnt", + ETM_QMU_CSCH_MMU_RD_DROP_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x1b, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_csch_mmu_rd_drop_cnt_reg, + NULL, + NULL, + }, + { + "qcfg_qsch_crs_filter", + ETM_QMU_QCFG_QSCH_CRS_FILTERr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x1c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_qcfg_qsch_crs_filter_reg, + NULL, + NULL, + }, + { + "qcfg_qsch_crs_force_en", + ETM_QMU_QCFG_QSCH_CRS_FORCE_ENr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x1d, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_qcfg_qsch_crs_force_en_reg, + NULL, + NULL, + }, + { + "qcfg_qsch_crs_force_qnum", + ETM_QMU_QCFG_QSCH_CRS_FORCE_QNUMr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x1e, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_qcfg_qsch_crs_force_qnum_reg, + NULL, + NULL, + }, + { + "qcfg_qsch_crs_force_crs", + ETM_QMU_QCFG_QSCH_CRS_FORCE_CRSr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x1f, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_qcfg_qsch_crs_force_crs_reg, + NULL, + NULL, + }, + { + "cfgmt_oshp_sgmii_shap_mode", + ETM_QMU_CFGMT_OSHP_SGMII_SHAP_MODEr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfgmt_oshp_sgmii_shap_mode_reg, + NULL, + NULL, + }, + { + "cfgmt_qmu_sashap_en", + ETM_QMU_CFGMT_QMU_SASHAP_ENr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x21, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfgmt_qmu_sashap_en_reg, + NULL, + NULL, + }, + { + "cfgmt_sashap_token_max", + ETM_QMU_CFGMT_SASHAP_TOKEN_MAXr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x39, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfgmt_sashap_token_max_reg, + NULL, + NULL, + }, + { + "cfgmt_sashap_token_min", + ETM_QMU_CFGMT_SASHAP_TOKEN_MINr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x3a, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfgmt_sashap_token_min_reg, + NULL, + NULL, + }, + { + "cfg_qsch_q3lbaddrate", + ETM_QMU_CFG_QSCH_Q3LBADDRATEr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x3f, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_q3lbaddrate_reg, + NULL, + NULL, + }, + { + "cfg_qsch_q012lbaddrate", + ETM_QMU_CFG_QSCH_Q012LBADDRATEr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x40, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_q012lbaddrate_reg, + NULL, + NULL, + }, + { + "cfg_qsch_q3creditlbmaxcnt", + ETM_QMU_CFG_QSCH_Q3CREDITLBMAXCNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x41, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_q3creditlbmaxcnt_reg, + NULL, + NULL, + }, + { + "cfg_qsch_q012creditlbmaxcnt", + ETM_QMU_CFG_QSCH_Q012CREDITLBMAXCNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x42, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_q012creditlbmaxcnt_reg, + NULL, + NULL, + }, + { + "cfg_qsch_mul_token_gen_num", + ETM_QMU_CFG_QSCH_MUL_TOKEN_GEN_NUMr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x43, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_mul_token_gen_num_reg, + NULL, + NULL, + }, + { + "cfg_qsch_q3_credit_lb_control_en", + ETM_QMU_CFG_QSCH_Q3_CREDIT_LB_CONTROL_ENr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x44, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_q3_credit_lb_control_en_reg, + NULL, + NULL, + }, + { + "cfg_qsch_q012_credit_lb_control_en", + ETM_QMU_CFG_QSCH_Q012_CREDIT_LB_CONTROL_ENr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x45, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_q012_credit_lb_control_en_reg, + NULL, + NULL, + }, + { + "cfg_qsch_sp_dwrr_en", + ETM_QMU_CFG_QSCH_SP_DWRR_ENr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x46, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_sp_dwrr_en_reg, + NULL, + NULL, + }, + { + "cfg_qsch_q01_attach_en", + ETM_QMU_CFG_QSCH_Q01_ATTACH_ENr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x47, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_q01_attach_en_reg, + NULL, + NULL, + }, + { + "cfg_qsch_w0", + ETM_QMU_CFG_QSCH_W0r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x48, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_w0_reg, + NULL, + NULL, + }, + { + "cfg_qsch_w1", + ETM_QMU_CFG_QSCH_W1r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x49, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_w1_reg, + NULL, + NULL, + }, + { + "cfg_qsch_w2", + ETM_QMU_CFG_QSCH_W2r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x4a, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_w2_reg, + NULL, + NULL, + }, + { + "cfg_qsch_lkybktmaxcnt1", + ETM_QMU_CFG_QSCH_LKYBKTMAXCNT1r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x4b, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_lkybktmaxcnt1_reg, + NULL, + NULL, + }, + { + "cfg_qsch_lkybktmaxcnt2", + ETM_QMU_CFG_QSCH_LKYBKTMAXCNT2r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x4c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_lkybktmaxcnt2_reg, + NULL, + NULL, + }, + { + "cfg_qsch_lkybktdcrrate1", + ETM_QMU_CFG_QSCH_LKYBKTDCRRATE1r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x4d, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_lkybktdcrrate1_reg, + NULL, + NULL, + }, + { + "cfg_qsch_lkybktdcrrate2", + ETM_QMU_CFG_QSCH_LKYBKTDCRRATE2r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x4e, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_lkybktdcrrate2_reg, + NULL, + NULL, + }, + { + "cfg_qsch_lkybktdcrrate3", + ETM_QMU_CFG_QSCH_LKYBKTDCRRATE3r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x4f, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_lkybktdcrrate3_reg, + NULL, + NULL, + }, + { + "cfg_qsch_lkybktmaxcnt3", + ETM_QMU_CFG_QSCH_LKYBKTMAXCNT3r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x50, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_lkybktmaxcnt3_reg, + NULL, + NULL, + }, + { + "cfg_qsch_qmu_mul_auto_sa_version", + ETM_QMU_CFG_QSCH_QMU_MUL_AUTO_SA_VERSIONr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x55, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_qmu_mul_auto_sa_version_reg, + NULL, + NULL, + }, + { + "cfg_qsch_sa_credit_value_0", + ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_0r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x56, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_sa_credit_value_0_reg, + NULL, + NULL, + }, + { + "cfg_qsch_sa_credit_value_1", + ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_1r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x57, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_sa_credit_value_1_reg, + NULL, + NULL, + }, + { + "cfg_qsch_sa_credit_value_2", + ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_2r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x58, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_sa_credit_value_2_reg, + NULL, + NULL, + }, + { + "cfg_qsch_sa_credit_value_3", + ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_3r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x59, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_sa_credit_value_3_reg, + NULL, + NULL, + }, + { + "cfg_qsch_sa_credit_value_4", + ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_4r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x5a, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_sa_credit_value_4_reg, + NULL, + NULL, + }, + { + "cfg_qsch_sa_credit_value_5", + ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_5r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x5b, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_sa_credit_value_5_reg, + NULL, + NULL, + }, + { + "cfg_qsch_sa_credit_value_6", + ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_6r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x5c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_sa_credit_value_6_reg, + NULL, + NULL, + }, + { + "cfg_qsch_sa_credit_value_7", + ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_7r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x5d, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_sa_credit_value_7_reg, + NULL, + NULL, + }, + { + "cfg_qsch_remote_credit_fifo_almost_full_th", + ETM_QMU_CFG_QSCH_REMOTE_CREDIT_FIFO_ALMOST_FULL_THr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x76, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_remote_credit_fifo_almost_full_th_reg, + NULL, + NULL, + }, + { + "cfg_qsch_auto_credit_fifo_almost_full_th", + ETM_QMU_CFG_QSCH_AUTO_CREDIT_FIFO_ALMOST_FULL_THr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x77, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_auto_credit_fifo_almost_full_th_reg, + NULL, + NULL, + }, + { + "cfg_qsch_q3_credit_fifo_almost_full_th", + ETM_QMU_CFG_QSCH_Q3_CREDIT_FIFO_ALMOST_FULL_THr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x78, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_q3_credit_fifo_almost_full_th_reg, + NULL, + NULL, + }, + { + "cfg_qsch_q012_credit_fifo_almost_full_th", + ETM_QMU_CFG_QSCH_Q012_CREDIT_FIFO_ALMOST_FULL_THr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x79, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_q012_credit_fifo_almost_full_th_reg, + NULL, + NULL, + }, + { + "cfg_qsch_mul_fc_res_en", + ETM_QMU_CFG_QSCH_MUL_FC_RES_ENr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x7a, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_mul_fc_res_en_reg, + NULL, + NULL, + }, + { + "cfgmt_mul_ovf_udf_flg_query", + ETM_QMU_CFGMT_MUL_OVF_UDF_FLG_QUERYr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x7d, + (32/8), + 0, + 0, + 0, + 0, + 19, + g_etm_qmu_cfgmt_mul_ovf_udf_flg_query_reg, + NULL, + NULL, + }, + { + "cfgmt_mul_cng_flg_query", + ETM_QMU_CFGMT_MUL_CNG_FLG_QUERYr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x7e, + (32/8), + 0, + 0, + 0, + 0, + 5, + g_etm_qmu_cfgmt_mul_cng_flg_query_reg, + NULL, + NULL, + }, + { + "qsch_cfg_lkybktval1", + ETM_QMU_QSCH_CFG_LKYBKTVAL1r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x7f, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_qsch_cfg_lkybktval1_reg, + NULL, + NULL, + }, + { + "qsch_cfg_lkybktval2", + ETM_QMU_QSCH_CFG_LKYBKTVAL2r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x80, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_qsch_cfg_lkybktval2_reg, + NULL, + NULL, + }, + { + "qsch_cfg_lkybktval3", + ETM_QMU_QSCH_CFG_LKYBKTVAL3r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x81, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_qsch_cfg_lkybktval3_reg, + NULL, + NULL, + }, + { + "qsch_cfg_q3lbval", + ETM_QMU_QSCH_CFG_Q3LBVALr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x82, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_qsch_cfg_q3lbval_reg, + NULL, + NULL, + }, + { + "qsch_cfg_q012lbval", + ETM_QMU_QSCH_CFG_Q012LBVALr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x83, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_qsch_cfg_q012lbval_reg, + NULL, + NULL, + }, + { + "qlist_cfgmt_ram_ecc_err2", + ETM_QMU_QLIST_CFGMT_RAM_ECC_ERR2r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2014, + (32/8), + 0, + 0, + 0, + 0, + 16, + g_etm_qmu_qlist_cfgmt_ram_ecc_err2_reg, + NULL, + NULL, + }, + { + "csch_aged_cmd_cnt", + ETM_QMU_CSCH_AGED_CMD_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2838, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_csch_aged_cmd_cnt_reg, + NULL, + NULL, + }, + { + "csch_qcfg_csch_congest_cnt", + ETM_QMU_CSCH_QCFG_CSCH_CONGEST_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2839, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_csch_qcfg_csch_congest_cnt_reg, + NULL, + NULL, + }, + { + "csch_qcfg_qlist_csch_sop_cnt", + ETM_QMU_CSCH_QCFG_QLIST_CSCH_SOP_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x283a, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_csch_qcfg_qlist_csch_sop_cnt_reg, + NULL, + NULL, + }, + { + "csch_qcfg_qlist_csch_eop_cnt", + ETM_QMU_CSCH_QCFG_QLIST_CSCH_EOP_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x283b, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_csch_qcfg_qlist_csch_eop_cnt_reg, + NULL, + NULL, + }, + { + "csch_qcfg_csch_csw_sop_cnt", + ETM_QMU_CSCH_QCFG_CSCH_CSW_SOP_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x283c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_csch_qcfg_csch_csw_sop_cnt_reg, + NULL, + NULL, + }, + { + "csch_qcfg_csch_csw_eop_cnt", + ETM_QMU_CSCH_QCFG_CSCH_CSW_EOP_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x283d, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_csch_qcfg_csch_csw_eop_cnt_reg, + NULL, + NULL, + }, + { + "csch_qcfg_qlist_csch_drop_cnt", + ETM_QMU_CSCH_QCFG_QLIST_CSCH_DROP_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x283e, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_csch_qcfg_qlist_csch_drop_cnt_reg, + NULL, + NULL, + }, + { + "csch_qcfg_csch_csw_drop_cnt", + ETM_QMU_CSCH_QCFG_CSCH_CSW_DROP_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x283f, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_csch_qcfg_csch_csw_drop_cnt_reg, + NULL, + NULL, + }, + { + "csw_mmu_sop_cmd_cnt", + ETM_QMU_CSW_MMU_SOP_CMD_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2840, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_csw_mmu_sop_cmd_cnt_reg, + NULL, + NULL, + }, + { + "mmu_csw_sop_data_cnt", + ETM_QMU_MMU_CSW_SOP_DATA_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2841, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_mmu_csw_sop_data_cnt_reg, + NULL, + NULL, + }, + { + "csw_qsch_feedb_cnt", + ETM_QMU_CSW_QSCH_FEEDB_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2842, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_csw_qsch_feedb_cnt_reg, + NULL, + NULL, + }, + { + "qmu_crdt_port_fc_cnt", + ETM_QMU_QMU_CRDT_PORT_FC_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2843, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_qmu_crdt_port_fc_cnt_reg, + NULL, + NULL, + }, + { + "csch_r_block_cnt", + ETM_QMU_CSCH_R_BLOCK_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x3400, + (32/8), + 0, + 0x1ff + 1, + 0, + 1, + 1, + g_etm_qmu_csch_r_block_cnt_reg, + NULL, + NULL, + }, + { + "qcfg_qlist_qds_head_rd", + ETM_QMU_QCFG_QLIST_QDS_HEAD_RDr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x10000, + (32/8), + 0, + 0x23ff + 1, + 0, + 1, + 1, + g_etm_qmu_qcfg_qlist_qds_head_rd_reg, + NULL, + NULL, + }, + { + "qcfg_qlist_qds_tail_rd", + ETM_QMU_QCFG_QLIST_QDS_TAIL_RDr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x20000, + (32/8), + 0, + 0x23ff + 1, + 0, + 1, + 1, + g_etm_qmu_qcfg_qlist_qds_tail_rd_reg, + NULL, + NULL, + }, + { + "qcfg_qlist_ept_rd", + ETM_QMU_QCFG_QLIST_EPT_RDr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x30000, + (32/8), + 0, + 0x23ff + 1, + 0, + 1, + 1, + g_etm_qmu_qcfg_qlist_ept_rd_reg, + NULL, + NULL, + }, + { + "qcfg_qlist_age_flag_rd", + ETM_QMU_QCFG_QLIST_AGE_FLAG_RDr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x38000, + (32/8), + 0, + 0x23ff + 1, + 0, + 1, + 1, + g_etm_qmu_qcfg_qlist_age_flag_rd_reg, + NULL, + NULL, + }, + { + "qcfg_qlist_cti_rd", + ETM_QMU_QCFG_QLIST_CTI_RDr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x40000, + (32/8), + 0, + 0x23ff + 1, + 0, + 1, + 1, + g_etm_qmu_qcfg_qlist_cti_rd_reg, + NULL, + NULL, + }, + { + "qcfg_qlist_cto_rd", + ETM_QMU_QCFG_QLIST_CTO_RDr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x50000, + (32/8), + 0, + 0x23ff + 1, + 0, + 1, + 1, + g_etm_qmu_qcfg_qlist_cto_rd_reg, + NULL, + NULL, + }, + { + "qcfg_qlist_chk_rd", + ETM_QMU_QCFG_QLIST_CHK_RDr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x100000, + (32/8), + 0, + 0x7fff + 1, + 0, + 1, + 1, + g_etm_qmu_qcfg_qlist_chk_rd_reg, + NULL, + NULL, + }, + { + "qcfg_qlist_nod_rd", + ETM_QMU_QCFG_QLIST_NOD_RDr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x140000, + (32/8), + 0, + 0x7fff + 1, + 0, + 1, + 1, + g_etm_qmu_qcfg_qlist_nod_rd_reg, + NULL, + NULL, + }, + { + "qcfg_qlist_biu_rd", + ETM_QMU_QCFG_QLIST_BIU_RDr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x180000, + (32/8), + 0, + 0x7fff + 1, + 0, + 1, + 1, + g_etm_qmu_qcfg_qlist_biu_rd_reg, + NULL, + NULL, + }, + { + "qsch_r_wlist_flag", + ETM_QMU_QSCH_R_WLIST_FLAGr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x90000, + (32/8), + 0, + 0x23ff + 1, + 0, + 1, + 1, + g_etm_qmu_qsch_r_wlist_flag_reg, + NULL, + NULL, + }, + { + "qcfg_crs_flg_rd", + ETM_QMU_QCFG_CRS_FLG_RDr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0xd0000, + (32/8), + 0, + 0x23ff + 1, + 0, + 1, + 1, + g_etm_qmu_qcfg_crs_flg_rd_reg, + NULL, + NULL, + }, + { + "cfgmt_qmu_imem_age_qds", + ETM_QMU_CFGMT_QMU_IMEM_AGE_QDSr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0xe0d, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_etm_qmu_cfgmt_qmu_imem_age_qds_reg, + NULL, + NULL, + }, + { + "cfgmt_qmu_imem_age_qlen", + ETM_QMU_CFGMT_QMU_IMEM_AGE_QLENr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0xe0e, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_etm_qmu_cfgmt_qmu_imem_age_qlen_reg, + NULL, + NULL, + }, + { + "cfgmt_qmu_imem_pd_ram_low", + ETM_QMU_CFGMT_QMU_IMEM_PD_RAM_LOWr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x1c0000, + (32/8), + 0, + 0x3fff + 1, + 0, + 1, + 1, + g_etm_qmu_cfgmt_qmu_imem_pd_ram_low_reg, + NULL, + NULL, + }, + { + "cfgmt_qmu_imem_pd_ram_high", + ETM_QMU_CFGMT_QMU_IMEM_PD_RAM_HIGHr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x1c4000, + (32/8), + 0, + 0x3fff + 1, + 0, + 1, + 1, + g_etm_qmu_cfgmt_qmu_imem_pd_ram_high_reg, + NULL, + NULL, + }, + { + "cfgmt_qmu_imem_up_ptr", + ETM_QMU_CFGMT_QMU_IMEM_UP_PTRr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x200000, + (32/8), + 0, + 0x3fff + 1, + 0, + 1, + 1, + g_etm_qmu_cfgmt_qmu_imem_up_ptr_reg, + NULL, + NULL, + }, + { + "cfgmt_qmu_imem_down_ptr", + ETM_QMU_CFGMT_QMU_IMEM_DOWN_PTRr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x240000, + (32/8), + 0, + 0x3fff + 1, + 0, + 1, + 1, + g_etm_qmu_cfgmt_qmu_imem_down_ptr_reg, + NULL, + NULL, + }, + { + "cfgmt_qmu_imem_age_flag", + ETM_QMU_CFGMT_QMU_IMEM_AGE_FLAGr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x280000, + (32/8), + 0, + 0x7ffff + 1, + 0, + 1, + 1, + g_etm_qmu_cfgmt_qmu_imem_age_flag_reg, + NULL, + NULL, + }, + { + "cfg_qsch_lkybkt2cngth", + ETM_QMU_CFG_QSCH_LKYBKT2CNGTHr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x2040, + (32/8), + 0, + 7 + 1, + 0, + 1, + 1, + g_etm_qmu_cfg_qsch_lkybkt2cngth_reg, + NULL, + NULL, + }, + { + "cfg_qsch_lkybkt1cngth", + ETM_QMU_CFG_QSCH_LKYBKT1CNGTHr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x2030, + (32/8), + 0, + 7 + 1, + 0, + 1, + 1, + g_etm_qmu_cfg_qsch_lkybkt1cngth_reg, + NULL, + NULL, + }, + { + "cfg_qsch_lkybkt3cngth", + ETM_QMU_CFG_QSCH_LKYBKT3CNGTHr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x2050, + (32/8), + 0, + 7 + 1, + 0, + 1, + 1, + g_etm_qmu_cfg_qsch_lkybkt3cngth_reg, + NULL, + NULL, + }, + { + "cfg_qsch_rm_mul_mcn1_credit_value", + ETM_QMU_CFG_QSCH_RM_MUL_MCN1_CREDIT_VALUEr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x2060, + (32/8), + 0, + 7 + 1, + 0, + 1, + 1, + g_etm_qmu_cfg_qsch_rm_mul_mcn1_credit_value_reg, + NULL, + NULL, + }, + { + "cfg_qsch_rm_mul_mcn2_credit_value", + ETM_QMU_CFG_QSCH_RM_MUL_MCN2_CREDIT_VALUEr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x2070, + (32/8), + 0, + 7 + 1, + 0, + 1, + 1, + g_etm_qmu_cfg_qsch_rm_mul_mcn2_credit_value_reg, + NULL, + NULL, + }, + { + "cfg_qsch_rm_mul_mcn3_credit_value", + ETM_QMU_CFG_QSCH_RM_MUL_MCN3_CREDIT_VALUEr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x2080, + (32/8), + 0, + 7 + 1, + 0, + 1, + 1, + g_etm_qmu_cfg_qsch_rm_mul_mcn3_credit_value_reg, + NULL, + NULL, + }, + { + "rm_mul_mcn1_rand_ansr_seed", + ETM_QMU_RM_MUL_MCN1_RAND_ANSR_SEEDr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2090, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_etm_qmu_rm_mul_mcn1_rand_ansr_seed_reg, + NULL, + NULL, + }, + { + "rm_mul_mcn2_rand_ansr_seed", + ETM_QMU_RM_MUL_MCN2_RAND_ANSR_SEEDr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2091, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_etm_qmu_rm_mul_mcn2_rand_ansr_seed_reg, + NULL, + NULL, + }, + { + "rm_mul_mcn3_rand_ansr_seed", + ETM_QMU_RM_MUL_MCN3_RAND_ANSR_SEEDr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2092, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_etm_qmu_rm_mul_mcn3_rand_ansr_seed_reg, + NULL, + NULL, + }, + { + "rm_mul_mcn1_rand_ansr_th", + ETM_QMU_RM_MUL_MCN1_RAND_ANSR_THr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2093, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_rm_mul_mcn1_rand_ansr_th_reg, + NULL, + NULL, + }, + { + "rm_mul_mcn2_rand_ansr_th", + ETM_QMU_RM_MUL_MCN2_RAND_ANSR_THr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2094, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_rm_mul_mcn2_rand_ansr_th_reg, + NULL, + NULL, + }, + { + "rm_mul_mcn3_rand_ansr_th", + ETM_QMU_RM_MUL_MCN3_RAND_ANSR_THr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2095, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_rm_mul_mcn3_rand_ansr_th_reg, + NULL, + NULL, + }, + { + "rm_mul_mcn1_rand_hold_base", + ETM_QMU_RM_MUL_MCN1_RAND_HOLD_BASEr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2096, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_etm_qmu_rm_mul_mcn1_rand_hold_base_reg, + NULL, + NULL, + }, + { + "rm_mul_mcn2_rand_hold_base", + ETM_QMU_RM_MUL_MCN2_RAND_HOLD_BASEr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2097, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_etm_qmu_rm_mul_mcn2_rand_hold_base_reg, + NULL, + NULL, + }, + { + "rm_mul_mcn3_rand_hold_base", + ETM_QMU_RM_MUL_MCN3_RAND_HOLD_BASEr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2098, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_etm_qmu_rm_mul_mcn3_rand_hold_base_reg, + NULL, + NULL, + }, + { + "rm_mul_mcn1_rand_sel_mask", + ETM_QMU_RM_MUL_MCN1_RAND_SEL_MASKr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2099, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_rm_mul_mcn1_rand_sel_mask_reg, + NULL, + NULL, + }, + { + "rm_mul_mcn2_rand_sel_mask", + ETM_QMU_RM_MUL_MCN2_RAND_SEL_MASKr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x209a, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_rm_mul_mcn2_rand_sel_mask_reg, + NULL, + NULL, + }, + { + "rm_mul_mcn3_rand_sel_mask", + ETM_QMU_RM_MUL_MCN3_RAND_SEL_MASKr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x209b, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_rm_mul_mcn3_rand_sel_mask_reg, + NULL, + NULL, + }, + { + "rm_mul_mcn1_rand_sel_seed_reg0", + ETM_QMU_RM_MUL_MCN1_RAND_SEL_SEED_REG0r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x209c, + (32/8), + 0, + 0, + 0, + 0, + 8, + g_etm_qmu_rm_mul_mcn1_rand_sel_seed_reg0_reg, + NULL, + NULL, + }, + { + "rm_mul_mcn1_rand_sel_seed_reg1", + ETM_QMU_RM_MUL_MCN1_RAND_SEL_SEED_REG1r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x209d, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_rm_mul_mcn1_rand_sel_seed_reg1_reg, + NULL, + NULL, + }, + { + "rm_mul_mcn2_rand_sel_seed_reg0", + ETM_QMU_RM_MUL_MCN2_RAND_SEL_SEED_REG0r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x209e, + (32/8), + 0, + 0, + 0, + 0, + 8, + g_etm_qmu_rm_mul_mcn2_rand_sel_seed_reg0_reg, + NULL, + NULL, + }, + { + "rm_mul_mcn2_rand_sel_seed_reg1", + ETM_QMU_RM_MUL_MCN2_RAND_SEL_SEED_REG1r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x209f, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_rm_mul_mcn2_rand_sel_seed_reg1_reg, + NULL, + NULL, + }, + { + "rm_mul_mcn3_rand_sel_seed_reg0", + ETM_QMU_RM_MUL_MCN3_RAND_SEL_SEED_REG0r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20a0, + (32/8), + 0, + 0, + 0, + 0, + 8, + g_etm_qmu_rm_mul_mcn3_rand_sel_seed_reg0_reg, + NULL, + NULL, + }, + { + "rm_mul_mcn3_rand_sel_seed_reg1", + ETM_QMU_RM_MUL_MCN3_RAND_SEL_SEED_REG1r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20a1, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_rm_mul_mcn3_rand_sel_seed_reg1_reg, + NULL, + NULL, + }, + { + "rm_mul_mcn1_step_wait_th1", + ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH1r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20a2, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_rm_mul_mcn1_step_wait_th1_reg, + NULL, + NULL, + }, + { + "rm_mul_mcn1_step_wait_th2", + ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH2r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20a3, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_rm_mul_mcn1_step_wait_th2_reg, + NULL, + NULL, + }, + { + "rm_mul_mcn1_step_wait_th3", + ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH3r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20a4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_rm_mul_mcn1_step_wait_th3_reg, + NULL, + NULL, + }, + { + "rm_mul_mcn1_step_wait_th4", + ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH4r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20a5, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_rm_mul_mcn1_step_wait_th4_reg, + NULL, + NULL, + }, + { + "rm_mul_mcn1_step_wait_th5", + ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH5r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20a6, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_rm_mul_mcn1_step_wait_th5_reg, + NULL, + NULL, + }, + { + "rm_mul_mcn1_step_wait_th6", + ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH6r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20a7, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_rm_mul_mcn1_step_wait_th6_reg, + NULL, + NULL, + }, + { + "rm_mul_mcn1_step_wait_th7", + ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH7r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20a8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_rm_mul_mcn1_step_wait_th7_reg, + NULL, + NULL, + }, + { + "rm_mul_mcn2_step_wait_th1", + ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH1r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20a9, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_rm_mul_mcn2_step_wait_th1_reg, + NULL, + NULL, + }, + { + "rm_mul_mcn2_step_wait_th2", + ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH2r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20aa, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_rm_mul_mcn2_step_wait_th2_reg, + NULL, + NULL, + }, + { + "rm_mul_mcn2_step_wait_th3", + ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH3r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20ab, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_rm_mul_mcn2_step_wait_th3_reg, + NULL, + NULL, + }, + { + "rm_mul_mcn2_step_wait_th4", + ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH4r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20ac, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_rm_mul_mcn2_step_wait_th4_reg, + NULL, + NULL, + }, + { + "rm_mul_mcn2_step_wait_th5", + ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH5r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20ad, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_rm_mul_mcn2_step_wait_th5_reg, + NULL, + NULL, + }, + { + "rm_mul_mcn2_step_wait_th6", + ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH6r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20ae, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_rm_mul_mcn2_step_wait_th6_reg, + NULL, + NULL, + }, + { + "rm_mul_mcn2_step_wait_th7", + ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH7r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20af, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_rm_mul_mcn2_step_wait_th7_reg, + NULL, + NULL, + }, + { + "rm_mul_mcn3_step_wait_th1", + ETM_QMU_RM_MUL_MCN3_STEP_WAIT_TH1r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20b0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_rm_mul_mcn3_step_wait_th1_reg, + NULL, + NULL, + }, + { + "rm_mul_mcn3_step_wait_th2", + ETM_QMU_RM_MUL_MCN3_STEP_WAIT_TH2r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20b1, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_rm_mul_mcn3_step_wait_th2_reg, + NULL, + NULL, + }, + { + "rm_mul_mcn3_step_wait_th3", + ETM_QMU_RM_MUL_MCN3_STEP_WAIT_TH3r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20b2, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_rm_mul_mcn3_step_wait_th3_reg, + NULL, + NULL, + }, + { + "rm_mul_mcn3_step_wait_th4", + ETM_QMU_RM_MUL_MCN3_STEP_WAIT_TH4r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20b3, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_rm_mul_mcn3_step_wait_th4_reg, + NULL, + NULL, + }, + { + "rm_mul_mcn3_step_wait_th5", + ETM_QMU_RM_MUL_MCN3_STEP_WAIT_TH5r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20b4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_rm_mul_mcn3_step_wait_th5_reg, + NULL, + NULL, + }, + { + "rm_mul_mcn3_step_wait_th6", + ETM_QMU_RM_MUL_MCN3_STEP_WAIT_TH6r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20b5, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_rm_mul_mcn3_step_wait_th6_reg, + NULL, + NULL, + }, + { + "rm_mul_mcn3step_wait_th7", + ETM_QMU_RM_MUL_MCN3STEP_WAIT_TH7r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20b6, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_rm_mul_mcn3step_wait_th7_reg, + NULL, + NULL, + }, + { + "cfg_qsch_mulcrdcntrate0", + ETM_QMU_CFG_QSCH_MULCRDCNTRATE0r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20b7, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_mulcrdcntrate0_reg, + NULL, + NULL, + }, + { + "cfg_qsch_mulcrdcntrate1", + ETM_QMU_CFG_QSCH_MULCRDCNTRATE1r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20b8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_mulcrdcntrate1_reg, + NULL, + NULL, + }, + { + "cfg_qsch_mulcrdcntrate2", + ETM_QMU_CFG_QSCH_MULCRDCNTRATE2r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20b9, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_mulcrdcntrate2_reg, + NULL, + NULL, + }, + { + "cfg_qsch_mulcrdcntrate3", + ETM_QMU_CFG_QSCH_MULCRDCNTRATE3r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20ba, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_mulcrdcntrate3_reg, + NULL, + NULL, + }, + { + "cfg_qsch_mulcrdcntrate4", + ETM_QMU_CFG_QSCH_MULCRDCNTRATE4r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20bb, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_mulcrdcntrate4_reg, + NULL, + NULL, + }, + { + "cfg_qsch_mulcrdcntrate5", + ETM_QMU_CFG_QSCH_MULCRDCNTRATE5r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20bc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_mulcrdcntrate5_reg, + NULL, + NULL, + }, + { + "cfg_qsch_mulcrdcntrate6", + ETM_QMU_CFG_QSCH_MULCRDCNTRATE6r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20bd, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_mulcrdcntrate6_reg, + NULL, + NULL, + }, + { + "cfg_qsch_mulcrdcntrate7", + ETM_QMU_CFG_QSCH_MULCRDCNTRATE7r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20be, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_mulcrdcntrate7_reg, + NULL, + NULL, + }, + { + "cfg_qsch_mulcrdcntrate8", + ETM_QMU_CFG_QSCH_MULCRDCNTRATE8r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20bf, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_mulcrdcntrate8_reg, + NULL, + NULL, + }, + { + "cfg_qsch_mulcrdcntrate9", + ETM_QMU_CFG_QSCH_MULCRDCNTRATE9r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20c0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_mulcrdcntrate9_reg, + NULL, + NULL, + }, + { + "cfg_qsch_mulcrdcntrate10", + ETM_QMU_CFG_QSCH_MULCRDCNTRATE10r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20c1, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_mulcrdcntrate10_reg, + NULL, + NULL, + }, + { + "cfg_qsch_mulcrdcntrate11", + ETM_QMU_CFG_QSCH_MULCRDCNTRATE11r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20c2, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_mulcrdcntrate11_reg, + NULL, + NULL, + }, + { + "cfg_qsch_mulcrdcntrate12", + ETM_QMU_CFG_QSCH_MULCRDCNTRATE12r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20c3, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_mulcrdcntrate12_reg, + NULL, + NULL, + }, + { + "cfg_qsch_mulcrdcntrate13", + ETM_QMU_CFG_QSCH_MULCRDCNTRATE13r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20c4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_mulcrdcntrate13_reg, + NULL, + NULL, + }, + { + "cfg_qsch_mulcrdcntrate14", + ETM_QMU_CFG_QSCH_MULCRDCNTRATE14r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20c5, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_mulcrdcntrate14_reg, + NULL, + NULL, + }, + { + "cfg_qsch_mulcrdcntrate15", + ETM_QMU_CFG_QSCH_MULCRDCNTRATE15r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20c6, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_mulcrdcntrate15_reg, + NULL, + NULL, + }, + { + "cfg_qsch_mulcrdcntrate16", + ETM_QMU_CFG_QSCH_MULCRDCNTRATE16r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20c7, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_mulcrdcntrate16_reg, + NULL, + NULL, + }, + { + "cfg_qsch_mulcrdcntrate17", + ETM_QMU_CFG_QSCH_MULCRDCNTRATE17r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20c8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_mulcrdcntrate17_reg, + NULL, + NULL, + }, + { + "cfg_qsch_mulcrdcntrate18", + ETM_QMU_CFG_QSCH_MULCRDCNTRATE18r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20c9, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_mulcrdcntrate18_reg, + NULL, + NULL, + }, + { + "cfg_qsch_mulcrdcntrate19", + ETM_QMU_CFG_QSCH_MULCRDCNTRATE19r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20ca, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_mulcrdcntrate19_reg, + NULL, + NULL, + }, + { + "cfg_qsch_mulcrdcntrate20", + ETM_QMU_CFG_QSCH_MULCRDCNTRATE20r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20cb, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_mulcrdcntrate20_reg, + NULL, + NULL, + }, + { + "cfg_qsch_mulcrdcntrate21", + ETM_QMU_CFG_QSCH_MULCRDCNTRATE21r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20cc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_mulcrdcntrate21_reg, + NULL, + NULL, + }, + { + "cfg_qsch_mulcrdcntrate22", + ETM_QMU_CFG_QSCH_MULCRDCNTRATE22r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20cd, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_mulcrdcntrate22_reg, + NULL, + NULL, + }, + { + "cfg_qsch_mulcrdcntrate23", + ETM_QMU_CFG_QSCH_MULCRDCNTRATE23r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20ce, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_mulcrdcntrate23_reg, + NULL, + NULL, + }, + { + "cfg_qsch_mulcrdcntrate24", + ETM_QMU_CFG_QSCH_MULCRDCNTRATE24r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20cf, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_mulcrdcntrate24_reg, + NULL, + NULL, + }, + { + "cfg_qsch_mulcrdcntrate25", + ETM_QMU_CFG_QSCH_MULCRDCNTRATE25r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20d0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_mulcrdcntrate25_reg, + NULL, + NULL, + }, + { + "cfg_qsch_mulcrdcntrate26", + ETM_QMU_CFG_QSCH_MULCRDCNTRATE26r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20d1, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_mulcrdcntrate26_reg, + NULL, + NULL, + }, + { + "cfg_qsch_mulcrdcntrate27", + ETM_QMU_CFG_QSCH_MULCRDCNTRATE27r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20d2, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_mulcrdcntrate27_reg, + NULL, + NULL, + }, + { + "cfg_qsch_mulcrdcntrate28", + ETM_QMU_CFG_QSCH_MULCRDCNTRATE28r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20d3, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_mulcrdcntrate28_reg, + NULL, + NULL, + }, + { + "cfg_qsch_mulcrdcntrate29", + ETM_QMU_CFG_QSCH_MULCRDCNTRATE29r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20d4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_mulcrdcntrate29_reg, + NULL, + NULL, + }, + { + "cfg_qsch_mulcrdcntrate30", + ETM_QMU_CFG_QSCH_MULCRDCNTRATE30r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20d5, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_mulcrdcntrate30_reg, + NULL, + NULL, + }, + { + "cfg_qsch_mulcrdcntrate31", + ETM_QMU_CFG_QSCH_MULCRDCNTRATE31r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20d6, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_mulcrdcntrate31_reg, + NULL, + NULL, + }, + { + "cfg_qsch_mulcrdcntrate32", + ETM_QMU_CFG_QSCH_MULCRDCNTRATE32r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20d7, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_mulcrdcntrate32_reg, + NULL, + NULL, + }, + { + "cfg_qsch_mulcrdcntrate33", + ETM_QMU_CFG_QSCH_MULCRDCNTRATE33r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20d8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_mulcrdcntrate33_reg, + NULL, + NULL, + }, + { + "cfg_qsch_mulcrdcntrate34", + ETM_QMU_CFG_QSCH_MULCRDCNTRATE34r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20d9, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_mulcrdcntrate34_reg, + NULL, + NULL, + }, + { + "cfg_qsch_mulcrdcntrate35", + ETM_QMU_CFG_QSCH_MULCRDCNTRATE35r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20da, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_mulcrdcntrate35_reg, + NULL, + NULL, + }, + { + "cfg_qsch_mulcrdcntrate36", + ETM_QMU_CFG_QSCH_MULCRDCNTRATE36r, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20db, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_mulcrdcntrate36_reg, + NULL, + NULL, + }, + { + "cfg_qsch_rm_mul_mcn1_rand_hold_shift", + ETM_QMU_CFG_QSCH_RM_MUL_MCN1_RAND_HOLD_SHIFTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20dc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_rm_mul_mcn1_rand_hold_shift_reg, + NULL, + NULL, + }, + { + "cfg_qsch_rm_mul_mcn2_rand_hold_shift", + ETM_QMU_CFG_QSCH_RM_MUL_MCN2_RAND_HOLD_SHIFTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20dd, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_rm_mul_mcn2_rand_hold_shift_reg, + NULL, + NULL, + }, + { + "cfg_qsch_rm_mul_mcn3_rand_hold_shift", + ETM_QMU_CFG_QSCH_RM_MUL_MCN3_RAND_HOLD_SHIFTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x20de, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_cfg_qsch_rm_mul_mcn3_rand_hold_shift_reg, + NULL, + NULL, + }, + { + "last_drop_qnum_get", + ETM_QMU_LAST_DROP_QNUM_GETr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2806, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_etm_qmu_last_drop_qnum_get_reg, + NULL, + NULL, + }, + { + "crdt_qmu_credit_cnt", + ETM_QMU_CRDT_QMU_CREDIT_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2807, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_crdt_qmu_credit_cnt_reg, + NULL, + NULL, + }, + { + "qmu_to_qsch_report_cnt", + ETM_QMU_QMU_TO_QSCH_REPORT_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2808, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_qmu_to_qsch_report_cnt_reg, + NULL, + NULL, + }, + { + "qmu_to_cgavd_report_cnt", + ETM_QMU_QMU_TO_CGAVD_REPORT_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2809, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_qmu_to_cgavd_report_cnt_reg, + NULL, + NULL, + }, + { + "qmu_crdt_crs_normal_cnt", + ETM_QMU_QMU_CRDT_CRS_NORMAL_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x280a, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_qmu_crdt_crs_normal_cnt_reg, + NULL, + NULL, + }, + { + "qmu_crdt_crs_off_cnt", + ETM_QMU_QMU_CRDT_CRS_OFF_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x280b, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_qmu_crdt_crs_off_cnt_reg, + NULL, + NULL, + }, + { + "qsch_qlist_shedule_cnt", + ETM_QMU_QSCH_QLIST_SHEDULE_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x280c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_qsch_qlist_shedule_cnt_reg, + NULL, + NULL, + }, + { + "qsch_qlist_sch_ept_cnt", + ETM_QMU_QSCH_QLIST_SCH_EPT_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x280d, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_qsch_qlist_sch_ept_cnt_reg, + NULL, + NULL, + }, + { + "qmu_to_mmu_blk_wr_cnt", + ETM_QMU_QMU_TO_MMU_BLK_WR_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x280e, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_qmu_to_mmu_blk_wr_cnt_reg, + NULL, + NULL, + }, + { + "qmu_to_csw_blk_rd_cnt", + ETM_QMU_QMU_TO_CSW_BLK_RD_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x280f, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_qmu_to_csw_blk_rd_cnt_reg, + NULL, + NULL, + }, + { + "qmu_to_mmu_sop_wr_cnt", + ETM_QMU_QMU_TO_MMU_SOP_WR_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2810, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_qmu_to_mmu_sop_wr_cnt_reg, + NULL, + NULL, + }, + { + "qmu_to_mmu_eop_wr_cnt", + ETM_QMU_QMU_TO_MMU_EOP_WR_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2811, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_qmu_to_mmu_eop_wr_cnt_reg, + NULL, + NULL, + }, + { + "qmu_to_mmu_drop_wr_cnt", + ETM_QMU_QMU_TO_MMU_DROP_WR_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2812, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_qmu_to_mmu_drop_wr_cnt_reg, + NULL, + NULL, + }, + { + "qmu_to_csw_sop_rd_cnt", + ETM_QMU_QMU_TO_CSW_SOP_RD_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2813, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_qmu_to_csw_sop_rd_cnt_reg, + NULL, + NULL, + }, + { + "qmu_to_csw_eop_rd_cnt", + ETM_QMU_QMU_TO_CSW_EOP_RD_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2814, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_qmu_to_csw_eop_rd_cnt_reg, + NULL, + NULL, + }, + { + "qmu_to_csw_drop_rd_cnt", + ETM_QMU_QMU_TO_CSW_DROP_RD_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2815, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_qmu_to_csw_drop_rd_cnt_reg, + NULL, + NULL, + }, + { + "mmu_to_qmu_wr_release_cnt", + ETM_QMU_MMU_TO_QMU_WR_RELEASE_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2816, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_mmu_to_qmu_wr_release_cnt_reg, + NULL, + NULL, + }, + { + "mmu_to_qmu_rd_release_cnt", + ETM_QMU_MMU_TO_QMU_RD_RELEASE_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2817, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_mmu_to_qmu_rd_release_cnt_reg, + NULL, + NULL, + }, + { + "observe_qnum_set", + ETM_QMU_OBSERVE_QNUM_SETr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2820, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_observe_qnum_set_reg, + NULL, + NULL, + }, + { + "spec_q_pkt_received", + ETM_QMU_SPEC_Q_PKT_RECEIVEDr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2821, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_spec_q_pkt_received_reg, + NULL, + NULL, + }, + { + "spec_q_pkt_dropped", + ETM_QMU_SPEC_Q_PKT_DROPPEDr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2822, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_spec_q_pkt_dropped_reg, + NULL, + NULL, + }, + { + "spec_q_pkt_scheduled", + ETM_QMU_SPEC_Q_PKT_SCHEDULEDr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2823, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_spec_q_pkt_scheduled_reg, + NULL, + NULL, + }, + { + "spec_q_wr_cmd_sent", + ETM_QMU_SPEC_Q_WR_CMD_SENTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2824, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_spec_q_wr_cmd_sent_reg, + NULL, + NULL, + }, + { + "spec_q_rd_cmd_sent", + ETM_QMU_SPEC_Q_RD_CMD_SENTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2825, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_spec_q_rd_cmd_sent_reg, + NULL, + NULL, + }, + { + "spec_q_pkt_enq", + ETM_QMU_SPEC_Q_PKT_ENQr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2826, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_spec_q_pkt_enq_reg, + NULL, + NULL, + }, + { + "spec_q_pkt_deq", + ETM_QMU_SPEC_Q_PKT_DEQr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2827, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_spec_q_pkt_deq_reg, + NULL, + NULL, + }, + { + "spec_q_crdt_uncon_received", + ETM_QMU_SPEC_Q_CRDT_UNCON_RECEIVEDr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2828, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_spec_q_crdt_uncon_received_reg, + NULL, + NULL, + }, + { + "spec_q_crdt_cong_received", + ETM_QMU_SPEC_Q_CRDT_CONG_RECEIVEDr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2829, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_spec_q_crdt_cong_received_reg, + NULL, + NULL, + }, + { + "spec_q_crs_normal_cnt", + ETM_QMU_SPEC_Q_CRS_NORMAL_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x282a, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_spec_q_crs_normal_cnt_reg, + NULL, + NULL, + }, + { + "spec_q_crs_off_cnt", + ETM_QMU_SPEC_Q_CRS_OFF_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x282b, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_spec_q_crs_off_cnt_reg, + NULL, + NULL, + }, + { + "observe_batch_set", + ETM_QMU_OBSERVE_BATCH_SETr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x282c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_observe_batch_set_reg, + NULL, + NULL, + }, + { + "spec_bat_pkt_received", + ETM_QMU_SPEC_BAT_PKT_RECEIVEDr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x282d, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_spec_bat_pkt_received_reg, + NULL, + NULL, + }, + { + "spec_bat_pkt_dropped", + ETM_QMU_SPEC_BAT_PKT_DROPPEDr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x282e, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_spec_bat_pkt_dropped_reg, + NULL, + NULL, + }, + { + "spec_bat_blk_scheduled", + ETM_QMU_SPEC_BAT_BLK_SCHEDULEDr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x282f, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_spec_bat_blk_scheduled_reg, + NULL, + NULL, + }, + { + "spec_bat_wr_cmd_sent", + ETM_QMU_SPEC_BAT_WR_CMD_SENTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2830, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_spec_bat_wr_cmd_sent_reg, + NULL, + NULL, + }, + { + "spec_bat_rd_cmd_sent", + ETM_QMU_SPEC_BAT_RD_CMD_SENTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2831, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_spec_bat_rd_cmd_sent_reg, + NULL, + NULL, + }, + { + "spec_bat_pkt_enq", + ETM_QMU_SPEC_BAT_PKT_ENQr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2832, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_spec_bat_pkt_enq_reg, + NULL, + NULL, + }, + { + "spec_bat_pkt_deq", + ETM_QMU_SPEC_BAT_PKT_DEQr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2833, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_spec_bat_pkt_deq_reg, + NULL, + NULL, + }, + { + "spec_bat_crdt_uncon_received", + ETM_QMU_SPEC_BAT_CRDT_UNCON_RECEIVEDr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2834, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_spec_bat_crdt_uncon_received_reg, + NULL, + NULL, + }, + { + "spec_bat_crdt_cong_received", + ETM_QMU_SPEC_BAT_CRDT_CONG_RECEIVEDr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2835, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_spec_bat_crdt_cong_received_reg, + NULL, + NULL, + }, + { + "spec_bat_crs_normal_cnt", + ETM_QMU_SPEC_BAT_CRS_NORMAL_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2836, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_spec_bat_crs_normal_cnt_reg, + NULL, + NULL, + }, + { + "spec_bat_crs_off_cnt", + ETM_QMU_SPEC_BAT_CRS_OFF_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2837, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_spec_bat_crs_off_cnt_reg, + NULL, + NULL, + }, + { + "bcntm_ovfl_qnum_get", + ETM_QMU_BCNTM_OVFL_QNUM_GETr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2844, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_bcntm_ovfl_qnum_get_reg, + NULL, + NULL, + }, + { + "crbal_a_ovf_qnum_get", + ETM_QMU_CRBAL_A_OVF_QNUM_GETr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2845, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_crbal_a_ovf_qnum_get_reg, + NULL, + NULL, + }, + { + "crbal_b_ovf_qnum_get", + ETM_QMU_CRBAL_B_OVF_QNUM_GETr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2846, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_crbal_b_ovf_qnum_get_reg, + NULL, + NULL, + }, + { + "crbal_drop_qnum_get", + ETM_QMU_CRBAL_DROP_QNUM_GETr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2847, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_crbal_drop_qnum_get_reg, + NULL, + NULL, + }, + { + "deq_flg_report_cnt", + ETM_QMU_DEQ_FLG_REPORT_CNTr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2848, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_deq_flg_report_cnt_reg, + NULL, + NULL, + }, + { + "spec_q_crs_get", + ETM_QMU_SPEC_Q_CRS_GETr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x2849, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_spec_q_crs_get_reg, + NULL, + NULL, + }, + { + "spec_q_crs_in_get", + ETM_QMU_SPEC_Q_CRS_IN_GETr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x284a, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_spec_q_crs_in_get_reg, + NULL, + NULL, + }, + { + "spec_q_crs_flg_csol_get", + ETM_QMU_SPEC_Q_CRS_FLG_CSOL_GETr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x284b, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_spec_q_crs_flg_csol_get_reg, + NULL, + NULL, + }, + { + "ept_sch_qnum_get", + ETM_QMU_EPT_SCH_QNUM_GETr, + ETM, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + 0x284c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_etm_qmu_ept_sch_qnum_get_reg, + NULL, + NULL, + }, + { + "pcie_ddr_switch", + CFG_PCIE_PCIE_DDR_SWITCHr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x000, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_pcie_ddr_switch_reg, + NULL, + NULL, + }, + { + "user0_int_en", + CFG_PCIE_USER0_INT_ENr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x004, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_user0_int_en_reg, + NULL, + NULL, + }, + { + "user0_int_mask", + CFG_PCIE_USER0_INT_MASKr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x008, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_user0_int_mask_reg, + NULL, + NULL, + }, + { + "user0_int_status", + CFG_PCIE_USER0_INT_STATUSr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x00c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_user0_int_status_reg, + NULL, + NULL, + }, + { + "user1_int_en", + CFG_PCIE_USER1_INT_ENr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x010, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_user1_int_en_reg, + NULL, + NULL, + }, + { + "user1_int_mask", + CFG_PCIE_USER1_INT_MASKr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x014, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_user1_int_mask_reg, + NULL, + NULL, + }, + { + "user1_int_status", + CFG_PCIE_USER1_INT_STATUSr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x018, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_user1_int_status_reg, + NULL, + NULL, + }, + { + "user2_int_en", + CFG_PCIE_USER2_INT_ENr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x01c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_user2_int_en_reg, + NULL, + NULL, + }, + { + "user2_int_mask", + CFG_PCIE_USER2_INT_MASKr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x020, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_user2_int_mask_reg, + NULL, + NULL, + }, + { + "user2_int_status", + CFG_PCIE_USER2_INT_STATUSr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x024, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_user2_int_status_reg, + NULL, + NULL, + }, + { + "ecc_1b_int_en", + CFG_PCIE_ECC_1B_INT_ENr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x028, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_ecc_1b_int_en_reg, + NULL, + NULL, + }, + { + "ecc_1b_int_mask", + CFG_PCIE_ECC_1B_INT_MASKr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x02c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_ecc_1b_int_mask_reg, + NULL, + NULL, + }, + { + "ecc_1b_int_status", + CFG_PCIE_ECC_1B_INT_STATUSr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x030, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_ecc_1b_int_status_reg, + NULL, + NULL, + }, + { + "ecc_2b_int_en", + CFG_PCIE_ECC_2B_INT_ENr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x034, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_ecc_2b_int_en_reg, + NULL, + NULL, + }, + { + "ecc_2b_int_mask", + CFG_PCIE_ECC_2B_INT_MASKr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x038, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_ecc_2b_int_mask_reg, + NULL, + NULL, + }, + { + "ecc_2b_int_status", + CFG_PCIE_ECC_2B_INT_STATUSr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x03c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_ecc_2b_int_status_reg, + NULL, + NULL, + }, + { + "cfg_int_status", + CFG_PCIE_CFG_INT_STATUSr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x040, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_cfg_int_status_reg, + NULL, + NULL, + }, + { + "i_core_to_cntl", + CFG_PCIE_I_CORE_TO_CNTLr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x044, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_i_core_to_cntl_reg, + NULL, + NULL, + }, + { + "test_in_low", + CFG_PCIE_TEST_IN_LOWr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x048, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_test_in_low_reg, + NULL, + NULL, + }, + { + "test_in_high", + CFG_PCIE_TEST_IN_HIGHr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x04c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_test_in_high_reg, + NULL, + NULL, + }, + { + "local_interrupt_out", + CFG_PCIE_LOCAL_INTERRUPT_OUTr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x050, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_local_interrupt_out_reg, + NULL, + NULL, + }, + { + "pl_ltssm", + CFG_PCIE_PL_LTSSMr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x054, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_pl_ltssm_reg, + NULL, + NULL, + }, + { + "test_out0", + CFG_PCIE_TEST_OUT0r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x058, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_test_out0_reg, + NULL, + NULL, + }, + { + "test_out1", + CFG_PCIE_TEST_OUT1r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x05c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_test_out1_reg, + NULL, + NULL, + }, + { + "test_out2", + CFG_PCIE_TEST_OUT2r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x060, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_test_out2_reg, + NULL, + NULL, + }, + { + "test_out3", + CFG_PCIE_TEST_OUT3r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x064, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_test_out3_reg, + NULL, + NULL, + }, + { + "test_out4", + CFG_PCIE_TEST_OUT4r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x068, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_test_out4_reg, + NULL, + NULL, + }, + { + "test_out5", + CFG_PCIE_TEST_OUT5r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x06c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_test_out5_reg, + NULL, + NULL, + }, + { + "test_out6", + CFG_PCIE_TEST_OUT6r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x070, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_test_out6_reg, + NULL, + NULL, + }, + { + "test_out7", + CFG_PCIE_TEST_OUT7r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x074, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_test_out7_reg, + NULL, + NULL, + }, + { + "sync_o_core_status", + CFG_PCIE_SYNC_O_CORE_STATUSr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x078, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_sync_o_core_status_reg, + NULL, + NULL, + }, + { + "sync_o_alert_dbe", + CFG_PCIE_SYNC_O_ALERT_DBEr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x07c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_sync_o_alert_dbe_reg, + NULL, + NULL, + }, + { + "sync_o_alert_sbe", + CFG_PCIE_SYNC_O_ALERT_SBEr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x080, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_sync_o_alert_sbe_reg, + NULL, + NULL, + }, + { + "sync_o_link_loopback_en", + CFG_PCIE_SYNC_O_LINK_LOOPBACK_ENr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x084, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_sync_o_link_loopback_en_reg, + NULL, + NULL, + }, + { + "sync_o_local_fs_lf_valid", + CFG_PCIE_SYNC_O_LOCAL_FS_LF_VALIDr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x088, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_sync_o_local_fs_lf_valid_reg, + NULL, + NULL, + }, + { + "sync_o_rx_idle_detect", + CFG_PCIE_SYNC_O_RX_IDLE_DETECTr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x08c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_sync_o_rx_idle_detect_reg, + NULL, + NULL, + }, + { + "sync_o_rx_rdy", + CFG_PCIE_SYNC_O_RX_RDYr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x090, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_sync_o_rx_rdy_reg, + NULL, + NULL, + }, + { + "sync_o_tx_rdy", + CFG_PCIE_SYNC_O_TX_RDYr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x094, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_sync_o_tx_rdy_reg, + NULL, + NULL, + }, + { + "pcie_link_up_cnt", + CFG_PCIE_PCIE_LINK_UP_CNTr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x098, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_pcie_link_up_cnt_reg, + NULL, + NULL, + }, + { + "test_out_pcie0", + CFG_PCIE_TEST_OUT_PCIE0r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x09c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_test_out_pcie0_reg, + NULL, + NULL, + }, + { + "test_out_pcie1", + CFG_PCIE_TEST_OUT_PCIE1r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x0a0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_test_out_pcie1_reg, + NULL, + NULL, + }, + { + "test_out_pcie2", + CFG_PCIE_TEST_OUT_PCIE2r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x0a4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_test_out_pcie2_reg, + NULL, + NULL, + }, + { + "test_out_pcie3", + CFG_PCIE_TEST_OUT_PCIE3r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x0a8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_test_out_pcie3_reg, + NULL, + NULL, + }, + { + "test_out_pcie4", + CFG_PCIE_TEST_OUT_PCIE4r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x0ac, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_test_out_pcie4_reg, + NULL, + NULL, + }, + { + "test_out_pcie5", + CFG_PCIE_TEST_OUT_PCIE5r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x0b0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_test_out_pcie5_reg, + NULL, + NULL, + }, + { + "test_out_pcie6", + CFG_PCIE_TEST_OUT_PCIE6r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x0b4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_test_out_pcie6_reg, + NULL, + NULL, + }, + { + "test_out_pcie7", + CFG_PCIE_TEST_OUT_PCIE7r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x0b8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_test_out_pcie7_reg, + NULL, + NULL, + }, + { + "test_out_pcie8", + CFG_PCIE_TEST_OUT_PCIE8r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x0bc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_test_out_pcie8_reg, + NULL, + NULL, + }, + { + "test_out_pcie9", + CFG_PCIE_TEST_OUT_PCIE9r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x0c0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_test_out_pcie9_reg, + NULL, + NULL, + }, + { + "test_out_pcie10", + CFG_PCIE_TEST_OUT_PCIE10r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x0c4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_test_out_pcie10_reg, + NULL, + NULL, + }, + { + "test_out_pcie11", + CFG_PCIE_TEST_OUT_PCIE11r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x0c8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_test_out_pcie11_reg, + NULL, + NULL, + }, + { + "test_out_pcie12", + CFG_PCIE_TEST_OUT_PCIE12r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x0cc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_test_out_pcie12_reg, + NULL, + NULL, + }, + { + "test_out_pcie13", + CFG_PCIE_TEST_OUT_PCIE13r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x0d0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_test_out_pcie13_reg, + NULL, + NULL, + }, + { + "test_out_pcie14", + CFG_PCIE_TEST_OUT_PCIE14r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x0d4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_test_out_pcie14_reg, + NULL, + NULL, + }, + { + "test_out_pcie15", + CFG_PCIE_TEST_OUT_PCIE15r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x0d8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_test_out_pcie15_reg, + NULL, + NULL, + }, + { + "int_repeat_en", + CFG_PCIE_INT_REPEAT_ENr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x0e0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_int_repeat_en_reg, + NULL, + NULL, + }, + { + "dbg_awid_axi_mst", + CFG_PCIE_DBG_AWID_AXI_MSTr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x400, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg_awid_axi_mst_reg, + NULL, + NULL, + }, + { + "dbg_awaddr_axi_mst0", + CFG_PCIE_DBG_AWADDR_AXI_MST0r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x404, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg_awaddr_axi_mst0_reg, + NULL, + NULL, + }, + { + "dbg_awaddr_axi_mst1", + CFG_PCIE_DBG_AWADDR_AXI_MST1r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x408, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg_awaddr_axi_mst1_reg, + NULL, + NULL, + }, + { + "dbg_awlen_axi_mst", + CFG_PCIE_DBG_AWLEN_AXI_MSTr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x40c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg_awlen_axi_mst_reg, + NULL, + NULL, + }, + { + "dbg_awsize_axi_mst", + CFG_PCIE_DBG_AWSIZE_AXI_MSTr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x410, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg_awsize_axi_mst_reg, + NULL, + NULL, + }, + { + "dbg_awburst_axi_mst", + CFG_PCIE_DBG_AWBURST_AXI_MSTr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x414, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg_awburst_axi_mst_reg, + NULL, + NULL, + }, + { + "dbg_awlock_axi_mst", + CFG_PCIE_DBG_AWLOCK_AXI_MSTr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x418, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg_awlock_axi_mst_reg, + NULL, + NULL, + }, + { + "dbg_awcache_axi_mst", + CFG_PCIE_DBG_AWCACHE_AXI_MSTr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x41c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg_awcache_axi_mst_reg, + NULL, + NULL, + }, + { + "dbg_awprot_axi_mst", + CFG_PCIE_DBG_AWPROT_AXI_MSTr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x420, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg_awprot_axi_mst_reg, + NULL, + NULL, + }, + { + "dbg_wid_axi_mst", + CFG_PCIE_DBG_WID_AXI_MSTr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x424, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg_wid_axi_mst_reg, + NULL, + NULL, + }, + { + "dbg_wdata_axi_mst0", + CFG_PCIE_DBG_WDATA_AXI_MST0r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x428, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg_wdata_axi_mst0_reg, + NULL, + NULL, + }, + { + "dbg_wdata_axi_mst1", + CFG_PCIE_DBG_WDATA_AXI_MST1r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x42c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg_wdata_axi_mst1_reg, + NULL, + NULL, + }, + { + "dbg_wdata_axi_mst2", + CFG_PCIE_DBG_WDATA_AXI_MST2r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x430, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg_wdata_axi_mst2_reg, + NULL, + NULL, + }, + { + "dbg_wdata_axi_mst3", + CFG_PCIE_DBG_WDATA_AXI_MST3r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x434, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg_wdata_axi_mst3_reg, + NULL, + NULL, + }, + { + "dbg_wstrb_axi_mst", + CFG_PCIE_DBG_WSTRB_AXI_MSTr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x438, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg_wstrb_axi_mst_reg, + NULL, + NULL, + }, + { + "dbg_wlast_axi_mst", + CFG_PCIE_DBG_WLAST_AXI_MSTr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x43c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg_wlast_axi_mst_reg, + NULL, + NULL, + }, + { + "dbg_arid_axi_mst", + CFG_PCIE_DBG_ARID_AXI_MSTr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x440, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg_arid_axi_mst_reg, + NULL, + NULL, + }, + { + "dbg_araddr_axi_mst0", + CFG_PCIE_DBG_ARADDR_AXI_MST0r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x444, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg_araddr_axi_mst0_reg, + NULL, + NULL, + }, + { + "dbg_araddr_axi_mst1", + CFG_PCIE_DBG_ARADDR_AXI_MST1r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x448, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg_araddr_axi_mst1_reg, + NULL, + NULL, + }, + { + "dbg_arlen_axi_mst", + CFG_PCIE_DBG_ARLEN_AXI_MSTr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x44c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg_arlen_axi_mst_reg, + NULL, + NULL, + }, + { + "dbg_arsize_axi_mst", + CFG_PCIE_DBG_ARSIZE_AXI_MSTr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x450, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg_arsize_axi_mst_reg, + NULL, + NULL, + }, + { + "dbg_arburst_axi_mst", + CFG_PCIE_DBG_ARBURST_AXI_MSTr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x454, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg_arburst_axi_mst_reg, + NULL, + NULL, + }, + { + "dbg_arlock_axi_mst", + CFG_PCIE_DBG_ARLOCK_AXI_MSTr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x458, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg_arlock_axi_mst_reg, + NULL, + NULL, + }, + { + "dbg_arcache_axi_mst", + CFG_PCIE_DBG_ARCACHE_AXI_MSTr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x45c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg_arcache_axi_mst_reg, + NULL, + NULL, + }, + { + "dbg_arprot_axi_mst", + CFG_PCIE_DBG_ARPROT_AXI_MSTr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x460, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg_arprot_axi_mst_reg, + NULL, + NULL, + }, + { + "dbg_rdata_axi_mst0", + CFG_PCIE_DBG_RDATA_AXI_MST0r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x464, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg_rdata_axi_mst0_reg, + NULL, + NULL, + }, + { + "dbg_rdata_axi_mst1", + CFG_PCIE_DBG_RDATA_AXI_MST1r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x468, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg_rdata_axi_mst1_reg, + NULL, + NULL, + }, + { + "dbg_rdata_axi_mst2", + CFG_PCIE_DBG_RDATA_AXI_MST2r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x46c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg_rdata_axi_mst2_reg, + NULL, + NULL, + }, + { + "dbg_rdata_axi_mst3", + CFG_PCIE_DBG_RDATA_AXI_MST3r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x470, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg_rdata_axi_mst3_reg, + NULL, + NULL, + }, + { + "axi_mst_state", + CFG_PCIE_AXI_MST_STATEr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x474, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_axi_mst_state_reg, + NULL, + NULL, + }, + { + "axi_cfg_state", + CFG_PCIE_AXI_CFG_STATEr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x478, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_axi_cfg_state_reg, + NULL, + NULL, + }, + { + "axi_slv_rd_state", + CFG_PCIE_AXI_SLV_RD_STATEr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x47c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_axi_slv_rd_state_reg, + NULL, + NULL, + }, + { + "axi_slv_wr_state", + CFG_PCIE_AXI_SLV_WR_STATEr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x480, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_axi_slv_wr_state_reg, + NULL, + NULL, + }, + { + "axim_delay_en", + CFG_PCIE_AXIM_DELAY_ENr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x484, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_axim_delay_en_reg, + NULL, + NULL, + }, + { + "axim_delay", + CFG_PCIE_AXIM_DELAYr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x488, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_axim_delay_reg, + NULL, + NULL, + }, + { + "axim_speed_wr", + CFG_PCIE_AXIM_SPEED_WRr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x48c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_axim_speed_wr_reg, + NULL, + NULL, + }, + { + "axim_speed_rd", + CFG_PCIE_AXIM_SPEED_RDr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x490, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_axim_speed_rd_reg, + NULL, + NULL, + }, + { + "dbg_awaddr_axi_slv0", + CFG_PCIE_DBG_AWADDR_AXI_SLV0r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x4c0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg_awaddr_axi_slv0_reg, + NULL, + NULL, + }, + { + "dbg_awaddr_axi_slv1", + CFG_PCIE_DBG_AWADDR_AXI_SLV1r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x4c4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg_awaddr_axi_slv1_reg, + NULL, + NULL, + }, + { + "dbg0_wdata_axi_slv0", + CFG_PCIE_DBG0_WDATA_AXI_SLV0r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x4c8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg0_wdata_axi_slv0_reg, + NULL, + NULL, + }, + { + "dbg0_wdata_axi_slv1", + CFG_PCIE_DBG0_WDATA_AXI_SLV1r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x4cc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg0_wdata_axi_slv1_reg, + NULL, + NULL, + }, + { + "dbg0_wdata_axi_slv2", + CFG_PCIE_DBG0_WDATA_AXI_SLV2r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x4d0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg0_wdata_axi_slv2_reg, + NULL, + NULL, + }, + { + "dbg0_wdata_axi_slv3", + CFG_PCIE_DBG0_WDATA_AXI_SLV3r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x4d4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg0_wdata_axi_slv3_reg, + NULL, + NULL, + }, + { + "dbg1_wdata_axi_slv0", + CFG_PCIE_DBG1_WDATA_AXI_SLV0r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x4d8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg1_wdata_axi_slv0_reg, + NULL, + NULL, + }, + { + "dbg1_wdata_axi_slv1", + CFG_PCIE_DBG1_WDATA_AXI_SLV1r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x4dc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg1_wdata_axi_slv1_reg, + NULL, + NULL, + }, + { + "dbg1_wdata_axi_slv2", + CFG_PCIE_DBG1_WDATA_AXI_SLV2r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x4e0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg1_wdata_axi_slv2_reg, + NULL, + NULL, + }, + { + "dbg1_wdata_axi_slv3", + CFG_PCIE_DBG1_WDATA_AXI_SLV3r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x4e4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg1_wdata_axi_slv3_reg, + NULL, + NULL, + }, + { + "dbg2_wdata_axi_slv0", + CFG_PCIE_DBG2_WDATA_AXI_SLV0r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x4e8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg2_wdata_axi_slv0_reg, + NULL, + NULL, + }, + { + "dbg2_wdata_axi_slv1", + CFG_PCIE_DBG2_WDATA_AXI_SLV1r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x4ec, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg2_wdata_axi_slv1_reg, + NULL, + NULL, + }, + { + "dbg2_wdata_axi_slv2", + CFG_PCIE_DBG2_WDATA_AXI_SLV2r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x4f0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg2_wdata_axi_slv2_reg, + NULL, + NULL, + }, + { + "dbg2_wdata_axi_slv3", + CFG_PCIE_DBG2_WDATA_AXI_SLV3r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x4f4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg2_wdata_axi_slv3_reg, + NULL, + NULL, + }, + { + "dbg3_wdata_axi_slv0", + CFG_PCIE_DBG3_WDATA_AXI_SLV0r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x4f8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg3_wdata_axi_slv0_reg, + NULL, + NULL, + }, + { + "dbg3_wdata_axi_slv1", + CFG_PCIE_DBG3_WDATA_AXI_SLV1r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x4fc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg3_wdata_axi_slv1_reg, + NULL, + NULL, + }, + { + "dbg3_wdata_axi_slv2", + CFG_PCIE_DBG3_WDATA_AXI_SLV2r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x500, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg3_wdata_axi_slv2_reg, + NULL, + NULL, + }, + { + "dbg3_wdata_axi_slv3", + CFG_PCIE_DBG3_WDATA_AXI_SLV3r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x504, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg3_wdata_axi_slv3_reg, + NULL, + NULL, + }, + { + "dbg4_wdata_axi_slv0", + CFG_PCIE_DBG4_WDATA_AXI_SLV0r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x508, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg4_wdata_axi_slv0_reg, + NULL, + NULL, + }, + { + "dbg4_wdata_axi_slv1", + CFG_PCIE_DBG4_WDATA_AXI_SLV1r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x50c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg4_wdata_axi_slv1_reg, + NULL, + NULL, + }, + { + "dbg4_wdata_axi_slv2", + CFG_PCIE_DBG4_WDATA_AXI_SLV2r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x510, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg4_wdata_axi_slv2_reg, + NULL, + NULL, + }, + { + "dbg4_wdata_axi_slv3", + CFG_PCIE_DBG4_WDATA_AXI_SLV3r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x514, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg4_wdata_axi_slv3_reg, + NULL, + NULL, + }, + { + "dbg5_wdata_axi_slv0", + CFG_PCIE_DBG5_WDATA_AXI_SLV0r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x518, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg5_wdata_axi_slv0_reg, + NULL, + NULL, + }, + { + "dbg5_wdata_axi_slv1", + CFG_PCIE_DBG5_WDATA_AXI_SLV1r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x51c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg5_wdata_axi_slv1_reg, + NULL, + NULL, + }, + { + "dbg5_wdata_axi_slv2", + CFG_PCIE_DBG5_WDATA_AXI_SLV2r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x520, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg5_wdata_axi_slv2_reg, + NULL, + NULL, + }, + { + "dbg5_wdata_axi_slv3", + CFG_PCIE_DBG5_WDATA_AXI_SLV3r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x524, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg5_wdata_axi_slv3_reg, + NULL, + NULL, + }, + { + "dbg6_wdata_axi_slv0", + CFG_PCIE_DBG6_WDATA_AXI_SLV0r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x528, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg6_wdata_axi_slv0_reg, + NULL, + NULL, + }, + { + "dbg6_wdata_axi_slv1", + CFG_PCIE_DBG6_WDATA_AXI_SLV1r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x52c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg6_wdata_axi_slv1_reg, + NULL, + NULL, + }, + { + "dbg6_wdata_axi_slv2", + CFG_PCIE_DBG6_WDATA_AXI_SLV2r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x530, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg6_wdata_axi_slv2_reg, + NULL, + NULL, + }, + { + "dbg6_wdata_axi_slv3", + CFG_PCIE_DBG6_WDATA_AXI_SLV3r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x534, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg6_wdata_axi_slv3_reg, + NULL, + NULL, + }, + { + "dbg7_wdata_axi_slv0", + CFG_PCIE_DBG7_WDATA_AXI_SLV0r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x538, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg7_wdata_axi_slv0_reg, + NULL, + NULL, + }, + { + "dbg7_wdata_axi_slv1", + CFG_PCIE_DBG7_WDATA_AXI_SLV1r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x53c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg7_wdata_axi_slv1_reg, + NULL, + NULL, + }, + { + "dbg7_wdata_axi_slv2", + CFG_PCIE_DBG7_WDATA_AXI_SLV2r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x540, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg7_wdata_axi_slv2_reg, + NULL, + NULL, + }, + { + "dbg7_wdata_axi_slv3", + CFG_PCIE_DBG7_WDATA_AXI_SLV3r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x544, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg7_wdata_axi_slv3_reg, + NULL, + NULL, + }, + { + "dbg8_wdata_axi_slv0", + CFG_PCIE_DBG8_WDATA_AXI_SLV0r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x548, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg8_wdata_axi_slv0_reg, + NULL, + NULL, + }, + { + "dbg8_wdata_axi_slv1", + CFG_PCIE_DBG8_WDATA_AXI_SLV1r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x54c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg8_wdata_axi_slv1_reg, + NULL, + NULL, + }, + { + "dbg8_wdata_axi_slv2", + CFG_PCIE_DBG8_WDATA_AXI_SLV2r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x550, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg8_wdata_axi_slv2_reg, + NULL, + NULL, + }, + { + "dbg8_wdata_axi_slv3", + CFG_PCIE_DBG8_WDATA_AXI_SLV3r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x554, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg8_wdata_axi_slv3_reg, + NULL, + NULL, + }, + { + "dbg9_wdata_axi_slv0", + CFG_PCIE_DBG9_WDATA_AXI_SLV0r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x558, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg9_wdata_axi_slv0_reg, + NULL, + NULL, + }, + { + "dbg9_wdata_axi_slv1", + CFG_PCIE_DBG9_WDATA_AXI_SLV1r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x55c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg9_wdata_axi_slv1_reg, + NULL, + NULL, + }, + { + "dbg9_wdata_axi_slv2", + CFG_PCIE_DBG9_WDATA_AXI_SLV2r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x560, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg9_wdata_axi_slv2_reg, + NULL, + NULL, + }, + { + "dbg9_wdata_axi_slv3", + CFG_PCIE_DBG9_WDATA_AXI_SLV3r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x564, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg9_wdata_axi_slv3_reg, + NULL, + NULL, + }, + { + "dbg_awlen_axi_slv", + CFG_PCIE_DBG_AWLEN_AXI_SLVr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x568, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg_awlen_axi_slv_reg, + NULL, + NULL, + }, + { + "dbg_wlast_axi_slv", + CFG_PCIE_DBG_WLAST_AXI_SLVr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x56c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg_wlast_axi_slv_reg, + NULL, + NULL, + }, + { + "dbg_araddr_axi_slv0", + CFG_PCIE_DBG_ARADDR_AXI_SLV0r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x580, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg_araddr_axi_slv0_reg, + NULL, + NULL, + }, + { + "dbg_araddr_axi_slv1", + CFG_PCIE_DBG_ARADDR_AXI_SLV1r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x584, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg_araddr_axi_slv1_reg, + NULL, + NULL, + }, + { + "dbg0_rdata_axi_slv0", + CFG_PCIE_DBG0_RDATA_AXI_SLV0r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x588, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg0_rdata_axi_slv0_reg, + NULL, + NULL, + }, + { + "dbg0_rdata_axi_slv1", + CFG_PCIE_DBG0_RDATA_AXI_SLV1r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x58c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg0_rdata_axi_slv1_reg, + NULL, + NULL, + }, + { + "dbg0_rdata_axi_slv2", + CFG_PCIE_DBG0_RDATA_AXI_SLV2r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x590, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg0_rdata_axi_slv2_reg, + NULL, + NULL, + }, + { + "dbg0_rdata_axi_slv3", + CFG_PCIE_DBG0_RDATA_AXI_SLV3r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x594, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg0_rdata_axi_slv3_reg, + NULL, + NULL, + }, + { + "dbg1_rdata_axi_slv0", + CFG_PCIE_DBG1_RDATA_AXI_SLV0r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x598, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg1_rdata_axi_slv0_reg, + NULL, + NULL, + }, + { + "dbg1_rdata_axi_slv1", + CFG_PCIE_DBG1_RDATA_AXI_SLV1r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x59c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg1_rdata_axi_slv1_reg, + NULL, + NULL, + }, + { + "dbg1_rdata_axi_slv2", + CFG_PCIE_DBG1_RDATA_AXI_SLV2r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x5a0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg1_rdata_axi_slv2_reg, + NULL, + NULL, + }, + { + "dbg1_rdata_axi_slv3", + CFG_PCIE_DBG1_RDATA_AXI_SLV3r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x5a4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg1_rdata_axi_slv3_reg, + NULL, + NULL, + }, + { + "dbg_rlast_axi_slv", + CFG_PCIE_DBG_RLAST_AXI_SLVr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x5a8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_pcie_dbg_rlast_axi_slv_reg, + NULL, + NULL, + }, + { + "dma_enable", + CFG_DMA_DMA_ENABLEr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x000, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_dma_dma_enable_reg, + NULL, + NULL, + }, + { + "up_req", + CFG_DMA_UP_REQr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x004, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_dma_up_req_reg, + NULL, + NULL, + }, + { + "dma_up_current_state", + CFG_DMA_DMA_UP_CURRENT_STATEr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x010, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_dma_dma_up_current_state_reg, + NULL, + NULL, + }, + { + "dma_up_req_ack", + CFG_DMA_DMA_UP_REQ_ACKr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x00c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_dma_dma_up_req_ack_reg, + NULL, + NULL, + }, + { + "dma_done_latch", + CFG_DMA_DMA_DONE_LATCHr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x014, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_dma_dma_done_latch_reg, + NULL, + NULL, + }, + { + "dma_up_cpu_addr_low32", + CFG_DMA_DMA_UP_CPU_ADDR_LOW32r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x018, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_dma_dma_up_cpu_addr_low32_reg, + NULL, + NULL, + }, + { + "dma_up_cpu_addr_high32", + CFG_DMA_DMA_UP_CPU_ADDR_HIGH32r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x01c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_dma_dma_up_cpu_addr_high32_reg, + NULL, + NULL, + }, + { + "dma_up_se_addr", + CFG_DMA_DMA_UP_SE_ADDRr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x024, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_dma_dma_up_se_addr_reg, + NULL, + NULL, + }, + { + "dma_done_int", + CFG_DMA_DMA_DONE_INTr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x034, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_dma_dma_done_int_reg, + NULL, + NULL, + }, + { + "sp_cfg", + CFG_DMA_SP_CFGr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x038, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_dma_sp_cfg_reg, + NULL, + NULL, + }, + { + "dma_ing", + CFG_DMA_DMA_INGr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x03c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_dma_dma_ing_reg, + NULL, + NULL, + }, + { + "rd_timeout_thresh", + CFG_DMA_RD_TIMEOUT_THRESHr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x040, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_dma_rd_timeout_thresh_reg, + NULL, + NULL, + }, + { + "dma_tab_sta_up_fifo_gap", + CFG_DMA_DMA_TAB_STA_UP_FIFO_GAPr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x044, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_dma_dma_tab_sta_up_fifo_gap_reg, + NULL, + NULL, + }, + { + "cfg_mac_tim", + CFG_DMA_CFG_MAC_TIMr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x048, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_dma_cfg_mac_tim_reg, + NULL, + NULL, + }, + { + "cfg_mac_num", + CFG_DMA_CFG_MAC_NUMr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x04c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_dma_cfg_mac_num_reg, + NULL, + NULL, + }, + { + "init_bd_addr", + CFG_DMA_INIT_BD_ADDRr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x050, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_dma_init_bd_addr_reg, + NULL, + NULL, + }, + { + "mac_up_bd_addr1_low32", + CFG_DMA_MAC_UP_BD_ADDR1_LOW32r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x054, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_dma_mac_up_bd_addr1_low32_reg, + NULL, + NULL, + }, + { + "mac_up_bd_addr1_high32", + CFG_DMA_MAC_UP_BD_ADDR1_HIGH32r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x058, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_dma_mac_up_bd_addr1_high32_reg, + NULL, + NULL, + }, + { + "mac_up_bd_addr2_low32", + CFG_DMA_MAC_UP_BD_ADDR2_LOW32r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x05c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_dma_mac_up_bd_addr2_low32_reg, + NULL, + NULL, + }, + { + "mac_up_bd_addr2_high32", + CFG_DMA_MAC_UP_BD_ADDR2_HIGH32r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x060, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_dma_mac_up_bd_addr2_high32_reg, + NULL, + NULL, + }, + { + "cfg_mac_max_num", + CFG_DMA_CFG_MAC_MAX_NUMr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x064, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_dma_cfg_mac_max_num_reg, + NULL, + NULL, + }, + { + "dma_wbuf_ff_empty", + CFG_DMA_DMA_WBUF_FF_EMPTYr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x068, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_dma_dma_wbuf_ff_empty_reg, + NULL, + NULL, + }, + { + "dma_wbuf_state", + CFG_DMA_DMA_WBUF_STATEr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x06c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_dma_dma_wbuf_state_reg, + NULL, + NULL, + }, + { + "dma_mac_bd_addr_low32", + CFG_DMA_DMA_MAC_BD_ADDR_LOW32r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x070, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_dma_dma_mac_bd_addr_low32_reg, + NULL, + NULL, + }, + { + "dma_mac_bd_addr_high32", + CFG_DMA_DMA_MAC_BD_ADDR_HIGH32r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x074, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_dma_dma_mac_bd_addr_high32_reg, + NULL, + NULL, + }, + { + "mac_up_enable", + CFG_DMA_MAC_UP_ENABLEr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x078, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_dma_mac_up_enable_reg, + NULL, + NULL, + }, + { + "mac_endian", + CFG_DMA_MAC_ENDIANr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x07c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_dma_mac_endian_reg, + NULL, + NULL, + }, + { + "up_endian", + CFG_DMA_UP_ENDIANr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x080, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_dma_up_endian_reg, + NULL, + NULL, + }, + { + "dma_up_rd_cnt_latch", + CFG_DMA_DMA_UP_RD_CNT_LATCHr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x084, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_dma_dma_up_rd_cnt_latch_reg, + NULL, + NULL, + }, + { + "dma_up_rcv_cnt_latch", + CFG_DMA_DMA_UP_RCV_CNT_LATCHr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x088, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_dma_dma_up_rcv_cnt_latch_reg, + NULL, + NULL, + }, + { + "dma_up_cnt_latch", + CFG_DMA_DMA_UP_CNT_LATCHr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x08c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_dma_dma_up_cnt_latch_reg, + NULL, + NULL, + }, + { + "cpu_rd_bd_pulse", + CFG_DMA_CPU_RD_BD_PULSEr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x090, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_dma_cpu_rd_bd_pulse_reg, + NULL, + NULL, + }, + { + "cpu_bd_threshold", + CFG_DMA_CPU_BD_THRESHOLDr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x094, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_dma_cpu_bd_threshold_reg, + NULL, + NULL, + }, + { + "cpu_bd_used_cnt", + CFG_DMA_CPU_BD_USED_CNTr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x098, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_dma_cpu_bd_used_cnt_reg, + NULL, + NULL, + }, + { + "dma_up_rcv_status", + CFG_DMA_DMA_UP_RCV_STATUSr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x09c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_dma_dma_up_rcv_status_reg, + NULL, + NULL, + }, + { + "slv_rid_err_en", + CFG_DMA_SLV_RID_ERR_ENr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x0a0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_dma_slv_rid_err_en_reg, + NULL, + NULL, + }, + { + "slv_rresp_err_en", + CFG_DMA_SLV_RRESP_ERR_ENr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x0a4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_dma_slv_rresp_err_en_reg, + NULL, + NULL, + }, + { + "se_rdbk_ff_full", + CFG_DMA_SE_RDBK_FF_FULLr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x0a8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_dma_se_rdbk_ff_full_reg, + NULL, + NULL, + }, + { + "dma_up_data_count", + CFG_DMA_DMA_UP_DATA_COUNTr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x0ac, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_dma_dma_up_data_count_reg, + NULL, + NULL, + }, + { + "dma_mwr_fifo_afull_gap", + CFG_DMA_DMA_MWR_FIFO_AFULL_GAPr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0xb0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_dma_dma_mwr_fifo_afull_gap_reg, + NULL, + NULL, + }, + { + "dma_info_fifo_afull_gap", + CFG_DMA_DMA_INFO_FIFO_AFULL_GAPr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0xb4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_dma_dma_info_fifo_afull_gap_reg, + NULL, + NULL, + }, + { + "dma_rd_timeout_set", + CFG_DMA_DMA_RD_TIMEOUT_SETr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x0c0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_dma_dma_rd_timeout_set_reg, + NULL, + NULL, + }, + { + "dma_bd_dat_err_en", + CFG_DMA_DMA_BD_DAT_ERR_ENr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x0c4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_dma_dma_bd_dat_err_en_reg, + NULL, + NULL, + }, + { + "dma_repeat_cnt", + CFG_DMA_DMA_REPEAT_CNTr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x0c8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_dma_dma_repeat_cnt_reg, + NULL, + NULL, + }, + { + "dma_rd_timeout_en", + CFG_DMA_DMA_RD_TIMEOUT_ENr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x0cc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_dma_dma_rd_timeout_en_reg, + NULL, + NULL, + }, + { + "dma_repeat_read", + CFG_DMA_DMA_REPEAT_READr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x0d0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_dma_dma_repeat_read_reg, + NULL, + NULL, + }, + { + "dma_repeat_read_en", + CFG_DMA_DMA_REPEAT_READ_ENr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x0d4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_dma_dma_repeat_read_en_reg, + NULL, + NULL, + }, + { + "bd_ctl_state", + CFG_DMA_BD_CTL_STATEr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x0d8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_dma_bd_ctl_state_reg, + NULL, + NULL, + }, + { + "dma_done_int_cnt_wr", + CFG_DMA_DMA_DONE_INT_CNT_WRr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x0dc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_dma_dma_done_int_cnt_wr_reg, + NULL, + NULL, + }, + { + "dma_done_int_cnt_mac", + CFG_DMA_DMA_DONE_INT_CNT_MACr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x0e4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_dma_dma_done_int_cnt_mac_reg, + NULL, + NULL, + }, + { + "current_mac_num", + CFG_DMA_CURRENT_MAC_NUMr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x0f4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_dma_current_mac_num_reg, + NULL, + NULL, + }, + { + "cfg_mac_afifo_afull", + CFG_DMA_CFG_MAC_AFIFO_AFULLr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x0f8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_dma_cfg_mac_afifo_afull_reg, + NULL, + NULL, + }, + { + "dma_mac_ff_full", + CFG_DMA_DMA_MAC_FF_FULLr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x0fc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_dma_dma_mac_ff_full_reg, + NULL, + NULL, + }, + { + "user_axi_mst", + CFG_DMA_USER_AXI_MSTr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x0100, + (32/8), + 0, + 0, + 0, + 0, + 5, + g_cfg_dma_user_axi_mst_reg, + NULL, + NULL, + }, + { + "sbus_state", + CFG_CSR_SBUS_STATEr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x000, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_csr_sbus_state_reg, + NULL, + NULL, + }, + { + "mst_debug_en", + CFG_CSR_MST_DEBUG_ENr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x020, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_csr_mst_debug_en_reg, + NULL, + NULL, + }, + { + "sbus_command_sel", + CFG_CSR_SBUS_COMMAND_SELr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x024, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_csr_sbus_command_sel_reg, + NULL, + NULL, + }, + { + "soc_rd_time_out_thresh", + CFG_CSR_SOC_RD_TIME_OUT_THRESHr, + CFG, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x02c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_csr_soc_rd_time_out_thresh_reg, + NULL, + NULL, + }, + { + "big_little_byte_order", + CFG_CSR_BIG_LITTLE_BYTE_ORDERr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x030, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_csr_big_little_byte_order_reg, + NULL, + NULL, + }, + { + "ecc_bypass_read", + CFG_CSR_ECC_BYPASS_READr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x034, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_csr_ecc_bypass_read_reg, + NULL, + NULL, + }, + { + "ahb_async_wr_fifo_afull_gap", + CFG_CSR_AHB_ASYNC_WR_FIFO_AFULL_GAPr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x038, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_csr_ahb_async_wr_fifo_afull_gap_reg, + NULL, + NULL, + }, + { + "ahb_async_rd_fifo_afull_gap", + CFG_CSR_AHB_ASYNC_RD_FIFO_AFULL_GAPr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x03c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_csr_ahb_async_rd_fifo_afull_gap_reg, + NULL, + NULL, + }, + { + "ahb_async_cpl_fifo_afull_gap", + CFG_CSR_AHB_ASYNC_CPL_FIFO_AFULL_GAPr, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x040, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_csr_ahb_async_cpl_fifo_afull_gap_reg, + NULL, + NULL, + }, + { + "mst_debug_data0_high26", + CFG_CSR_MST_DEBUG_DATA0_HIGH26r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x080, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_csr_mst_debug_data0_high26_reg, + NULL, + NULL, + }, + { + "mst_debug_data0_low32", + CFG_CSR_MST_DEBUG_DATA0_LOW32r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x084, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_csr_mst_debug_data0_low32_reg, + NULL, + NULL, + }, + { + "mst_debug_data1_high26", + CFG_CSR_MST_DEBUG_DATA1_HIGH26r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x088, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_csr_mst_debug_data1_high26_reg, + NULL, + NULL, + }, + { + "mst_debug_data1_low32", + CFG_CSR_MST_DEBUG_DATA1_LOW32r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x08c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_csr_mst_debug_data1_low32_reg, + NULL, + NULL, + }, + { + "mst_debug_data2_high26", + CFG_CSR_MST_DEBUG_DATA2_HIGH26r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x090, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_csr_mst_debug_data2_high26_reg, + NULL, + NULL, + }, + { + "mst_debug_data2_low32", + CFG_CSR_MST_DEBUG_DATA2_LOW32r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x094, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_csr_mst_debug_data2_low32_reg, + NULL, + NULL, + }, + { + "mst_debug_data3_high26", + CFG_CSR_MST_DEBUG_DATA3_HIGH26r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x098, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_csr_mst_debug_data3_high26_reg, + NULL, + NULL, + }, + { + "mst_debug_data3_low32", + CFG_CSR_MST_DEBUG_DATA3_LOW32r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x09c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_csr_mst_debug_data3_low32_reg, + NULL, + NULL, + }, + { + "mst_debug_data4_high26", + CFG_CSR_MST_DEBUG_DATA4_HIGH26r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0a0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_csr_mst_debug_data4_high26_reg, + NULL, + NULL, + }, + { + "mst_debug_data4_low32", + CFG_CSR_MST_DEBUG_DATA4_LOW32r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0a4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_csr_mst_debug_data4_low32_reg, + NULL, + NULL, + }, + { + "mst_debug_data5_high26", + CFG_CSR_MST_DEBUG_DATA5_HIGH26r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0a8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_csr_mst_debug_data5_high26_reg, + NULL, + NULL, + }, + { + "mst_debug_data5_low32", + CFG_CSR_MST_DEBUG_DATA5_LOW32r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0ac, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_csr_mst_debug_data5_low32_reg, + NULL, + NULL, + }, + { + "mst_debug_data6_high26", + CFG_CSR_MST_DEBUG_DATA6_HIGH26r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0b0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_csr_mst_debug_data6_high26_reg, + NULL, + NULL, + }, + { + "mst_debug_data6_low32", + CFG_CSR_MST_DEBUG_DATA6_LOW32r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0b4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_csr_mst_debug_data6_low32_reg, + NULL, + NULL, + }, + { + "mst_debug_data7_high26", + CFG_CSR_MST_DEBUG_DATA7_HIGH26r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0b8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_csr_mst_debug_data7_high26_reg, + NULL, + NULL, + }, + { + "mst_debug_data7_low32", + CFG_CSR_MST_DEBUG_DATA7_LOW32r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0bc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_csr_mst_debug_data7_low32_reg, + NULL, + NULL, + }, + { + "mst_debug_data8_high26", + CFG_CSR_MST_DEBUG_DATA8_HIGH26r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0c0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_csr_mst_debug_data8_high26_reg, + NULL, + NULL, + }, + { + "mst_debug_data8_low32", + CFG_CSR_MST_DEBUG_DATA8_LOW32r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0c4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_csr_mst_debug_data8_low32_reg, + NULL, + NULL, + }, + { + "mst_debug_data9_high26", + CFG_CSR_MST_DEBUG_DATA9_HIGH26r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0c8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_csr_mst_debug_data9_high26_reg, + NULL, + NULL, + }, + { + "mst_debug_data9_low32", + CFG_CSR_MST_DEBUG_DATA9_LOW32r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0cc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_csr_mst_debug_data9_low32_reg, + NULL, + NULL, + }, + { + "mst_debug_data10_high26", + CFG_CSR_MST_DEBUG_DATA10_HIGH26r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0d0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_csr_mst_debug_data10_high26_reg, + NULL, + NULL, + }, + { + "mst_debug_data10_low32", + CFG_CSR_MST_DEBUG_DATA10_LOW32r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0d4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_csr_mst_debug_data10_low32_reg, + NULL, + NULL, + }, + { + "mst_debug_data11_high26", + CFG_CSR_MST_DEBUG_DATA11_HIGH26r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0d8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_csr_mst_debug_data11_high26_reg, + NULL, + NULL, + }, + { + "mst_debug_data11_low32", + CFG_CSR_MST_DEBUG_DATA11_LOW32r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0dc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_csr_mst_debug_data11_low32_reg, + NULL, + NULL, + }, + { + "mst_debug_data12_high26", + CFG_CSR_MST_DEBUG_DATA12_HIGH26r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0e0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_csr_mst_debug_data12_high26_reg, + NULL, + NULL, + }, + { + "mst_debug_data12_low32", + CFG_CSR_MST_DEBUG_DATA12_LOW32r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0e4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_csr_mst_debug_data12_low32_reg, + NULL, + NULL, + }, + { + "mst_debug_data13_high26", + CFG_CSR_MST_DEBUG_DATA13_HIGH26r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0e8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_csr_mst_debug_data13_high26_reg, + NULL, + NULL, + }, + { + "mst_debug_data13_low32", + CFG_CSR_MST_DEBUG_DATA13_LOW32r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0ec, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_csr_mst_debug_data13_low32_reg, + NULL, + NULL, + }, + { + "mst_debug_data14_high26", + CFG_CSR_MST_DEBUG_DATA14_HIGH26r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0f0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_csr_mst_debug_data14_high26_reg, + NULL, + NULL, + }, + { + "mst_debug_data14_low32", + CFG_CSR_MST_DEBUG_DATA14_LOW32r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0f4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_csr_mst_debug_data14_low32_reg, + NULL, + NULL, + }, + { + "mst_debug_data15_high26", + CFG_CSR_MST_DEBUG_DATA15_HIGH26r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0f8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_csr_mst_debug_data15_high26_reg, + NULL, + NULL, + }, + { + "mst_debug_data15_low32", + CFG_CSR_MST_DEBUG_DATA15_LOW32r, + CFG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0fc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_cfg_csr_mst_debug_data15_low32_reg, + NULL, + NULL, + }, + { + "ind_access_states", + NPPU_MR_CFG_IND_ACCESS_STATESr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0000, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_mr_cfg_ind_access_states_reg, + NULL, + NULL, + }, + { + "ind_access_cmd0", + NPPU_MR_CFG_IND_ACCESS_CMD0r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0004, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_nppu_mr_cfg_ind_access_cmd0_reg, + NULL, + NULL, + }, + { + "ind_access_data0", + NPPU_MR_CFG_IND_ACCESS_DATA0r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0008, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_mr_cfg_ind_access_data0_reg, + NULL, + NULL, + }, + { + "ind_access_data1", + NPPU_MR_CFG_IND_ACCESS_DATA1r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x000c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_mr_cfg_ind_access_data1_reg, + NULL, + NULL, + }, + { + "ind_access_cmd1", + NPPU_MR_CFG_IND_ACCESS_CMD1r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0010, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_mr_cfg_ind_access_cmd1_reg, + NULL, + NULL, + }, + { + "mr_init_done", + NPPU_MR_CFG_MR_INIT_DONEr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0014, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_mr_cfg_mr_init_done_reg, + NULL, + NULL, + }, + { + "cnt_mode_reg", + NPPU_MR_CFG_CNT_MODE_REGr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0018, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_nppu_mr_cfg_cnt_mode_reg_reg, + NULL, + NULL, + }, + { + "cfg_ecc_bypass_read", + NPPU_MR_CFG_CFG_ECC_BYPASS_READr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x001c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_mr_cfg_cfg_ecc_bypass_read_reg, + NULL, + NULL, + }, + { + "cfg_rep_mod", + NPPU_MR_CFG_CFG_REP_MODr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0020, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_mr_cfg_cfg_rep_mod_reg, + NULL, + NULL, + }, + { + "block_ptr_fifo_aful_th", + NPPU_MR_CFG_BLOCK_PTR_FIFO_AFUL_THr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x002c, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_nppu_mr_cfg_block_ptr_fifo_aful_th_reg, + NULL, + NULL, + }, + { + "pre_rcv_ptr_fifo_aful_th", + NPPU_MR_CFG_PRE_RCV_PTR_FIFO_AFUL_THr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0030, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_nppu_mr_cfg_pre_rcv_ptr_fifo_aful_th_reg, + NULL, + NULL, + }, + { + "mgid_fifo_aful_th", + NPPU_MR_CFG_MGID_FIFO_AFUL_THr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0034, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_nppu_mr_cfg_mgid_fifo_aful_th_reg, + NULL, + NULL, + }, + { + "rep_cmd_fifo_aful_th", + NPPU_MR_CFG_REP_CMD_FIFO_AFUL_THr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0038, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_nppu_mr_cfg_rep_cmd_fifo_aful_th_reg, + NULL, + NULL, + }, + { + "mr_int_mask_1", + NPPU_MR_CFG_MR_INT_MASK_1r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x00c0, + (32/8), + 0, + 0, + 0, + 0, + 20, + g_nppu_mr_cfg_mr_int_mask_1_reg, + NULL, + NULL, + }, + { + "mr_int_mask_2", + NPPU_MR_CFG_MR_INT_MASK_2r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x00c4, + (32/8), + 0, + 0, + 0, + 0, + 20, + g_nppu_mr_cfg_mr_int_mask_2_reg, + NULL, + NULL, + }, + { + "mr_int_mask_3", + NPPU_MR_CFG_MR_INT_MASK_3r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x00c8, + (32/8), + 0, + 0, + 0, + 0, + 20, + g_nppu_mr_cfg_mr_int_mask_3_reg, + NULL, + NULL, + }, + { + "mr_int_mask_4", + NPPU_MR_CFG_MR_INT_MASK_4r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x00cc, + (32/8), + 0, + 0, + 0, + 0, + 25, + g_nppu_mr_cfg_mr_int_mask_4_reg, + NULL, + NULL, + }, + { + "mr_states_1", + NPPU_MR_CFG_MR_STATES_1r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0040, + (32/8), + 0, + 0, + 0, + 0, + 20, + g_nppu_mr_cfg_mr_states_1_reg, + NULL, + NULL, + }, + { + "mr_states_2", + NPPU_MR_CFG_MR_STATES_2r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0044, + (32/8), + 0, + 0, + 0, + 0, + 20, + g_nppu_mr_cfg_mr_states_2_reg, + NULL, + NULL, + }, + { + "mr_states_3", + NPPU_MR_CFG_MR_STATES_3r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0048, + (32/8), + 0, + 0, + 0, + 0, + 20, + g_nppu_mr_cfg_mr_states_3_reg, + NULL, + NULL, + }, + { + "mr_states_4", + NPPU_MR_CFG_MR_STATES_4r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x004c, + (32/8), + 0, + 0, + 0, + 0, + 25, + g_nppu_mr_cfg_mr_states_4_reg, + NULL, + NULL, + }, + { + "mr_states_5", + NPPU_MR_CFG_MR_STATES_5r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0050, + (32/8), + 0, + 0, + 0, + 0, + 21, + g_nppu_mr_cfg_mr_states_5_reg, + NULL, + NULL, + }, + { + "mr_states_6", + NPPU_MR_CFG_MR_STATES_6r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0054, + (32/8), + 0, + 0, + 0, + 0, + 20, + g_nppu_mr_cfg_mr_states_6_reg, + NULL, + NULL, + }, + { + "mr_states_7", + NPPU_MR_CFG_MR_STATES_7r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0058, + (32/8), + 0, + 0, + 0, + 0, + 22, + g_nppu_mr_cfg_mr_states_7_reg, + NULL, + NULL, + }, + { + "mr_states_8", + NPPU_MR_CFG_MR_STATES_8r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x005c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_mr_cfg_mr_states_8_reg, + NULL, + NULL, + }, + { + "mr_sop_in_cnt", + NPPU_MR_CFG_MR_SOP_IN_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0060, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_mr_cfg_mr_sop_in_cnt_reg, + NULL, + NULL, + }, + { + "mr_eop_in_cnt", + NPPU_MR_CFG_MR_EOP_IN_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0064, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_mr_cfg_mr_eop_in_cnt_reg, + NULL, + NULL, + }, + { + "mr_sop_out_cnt", + NPPU_MR_CFG_MR_SOP_OUT_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0068, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_mr_cfg_mr_sop_out_cnt_reg, + NULL, + NULL, + }, + { + "mr_eop_out_cnt", + NPPU_MR_CFG_MR_EOP_OUT_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x006c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_mr_cfg_mr_eop_out_cnt_reg, + NULL, + NULL, + }, + { + "mr_cos0_in_cnt", + NPPU_MR_CFG_MR_COS0_IN_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0070, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_mr_cfg_mr_cos0_in_cnt_reg, + NULL, + NULL, + }, + { + "mr_cos1_in_cnt", + NPPU_MR_CFG_MR_COS1_IN_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0074, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_mr_cfg_mr_cos1_in_cnt_reg, + NULL, + NULL, + }, + { + "mr_cos2_in_cnt", + NPPU_MR_CFG_MR_COS2_IN_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0078, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_mr_cfg_mr_cos2_in_cnt_reg, + NULL, + NULL, + }, + { + "mr_cos3_in_cnt", + NPPU_MR_CFG_MR_COS3_IN_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x007c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_mr_cfg_mr_cos3_in_cnt_reg, + NULL, + NULL, + }, + { + "mr_cos0_out_cnt", + NPPU_MR_CFG_MR_COS0_OUT_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0080, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_mr_cfg_mr_cos0_out_cnt_reg, + NULL, + NULL, + }, + { + "mr_cos1_out_cnt", + NPPU_MR_CFG_MR_COS1_OUT_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0084, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_mr_cfg_mr_cos1_out_cnt_reg, + NULL, + NULL, + }, + { + "mr_cos2_out_cnt", + NPPU_MR_CFG_MR_COS2_OUT_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0088, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_mr_cfg_mr_cos2_out_cnt_reg, + NULL, + NULL, + }, + { + "mr_cos3_out_cnt", + NPPU_MR_CFG_MR_COS3_OUT_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x008c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_mr_cfg_mr_cos3_out_cnt_reg, + NULL, + NULL, + }, + { + "mr_err_in_cnt", + NPPU_MR_CFG_MR_ERR_IN_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0090, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_mr_cfg_mr_err_in_cnt_reg, + NULL, + NULL, + }, + { + "mr_cos0_sop_in_cnt", + NPPU_MR_CFG_MR_COS0_SOP_IN_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0140, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_mr_cfg_mr_cos0_sop_in_cnt_reg, + NULL, + NULL, + }, + { + "mr_cos0_eop_in_cnt", + NPPU_MR_CFG_MR_COS0_EOP_IN_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0144, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_mr_cfg_mr_cos0_eop_in_cnt_reg, + NULL, + NULL, + }, + { + "mr_cos1_sop_in_cnt", + NPPU_MR_CFG_MR_COS1_SOP_IN_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0148, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_mr_cfg_mr_cos1_sop_in_cnt_reg, + NULL, + NULL, + }, + { + "mr_cos1_eop_in_cnt", + NPPU_MR_CFG_MR_COS1_EOP_IN_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x014c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_mr_cfg_mr_cos1_eop_in_cnt_reg, + NULL, + NULL, + }, + { + "mr_cos2_sop_in_cnt", + NPPU_MR_CFG_MR_COS2_SOP_IN_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0150, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_mr_cfg_mr_cos2_sop_in_cnt_reg, + NULL, + NULL, + }, + { + "mr_cos2_eop_in_cnt", + NPPU_MR_CFG_MR_COS2_EOP_IN_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0154, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_mr_cfg_mr_cos2_eop_in_cnt_reg, + NULL, + NULL, + }, + { + "mr_cos3_sop_in_cnt", + NPPU_MR_CFG_MR_COS3_SOP_IN_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0158, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_mr_cfg_mr_cos3_sop_in_cnt_reg, + NULL, + NULL, + }, + { + "mr_cos3_eop_in_cnt", + NPPU_MR_CFG_MR_COS3_EOP_IN_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x015c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_mr_cfg_mr_cos3_eop_in_cnt_reg, + NULL, + NULL, + }, + { + "mr_cos0_in_err_cnt", + NPPU_MR_CFG_MR_COS0_IN_ERR_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0160, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_mr_cfg_mr_cos0_in_err_cnt_reg, + NULL, + NULL, + }, + { + "mr_cos1_in_err_cnt", + NPPU_MR_CFG_MR_COS1_IN_ERR_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0164, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_mr_cfg_mr_cos1_in_err_cnt_reg, + NULL, + NULL, + }, + { + "mr_cos2_in_err_cnt", + NPPU_MR_CFG_MR_COS2_IN_ERR_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0168, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_mr_cfg_mr_cos2_in_err_cnt_reg, + NULL, + NULL, + }, + { + "mr_cos3_in_err_cnt", + NPPU_MR_CFG_MR_COS3_IN_ERR_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x016c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_mr_cfg_mr_cos3_in_err_cnt_reg, + NULL, + NULL, + }, + { + "mr_cos0_sop_out_cnt", + NPPU_MR_CFG_MR_COS0_SOP_OUT_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0170, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_mr_cfg_mr_cos0_sop_out_cnt_reg, + NULL, + NULL, + }, + { + "mr_cos0_eop_out_cnt", + NPPU_MR_CFG_MR_COS0_EOP_OUT_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0174, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_mr_cfg_mr_cos0_eop_out_cnt_reg, + NULL, + NULL, + }, + { + "mr_cos1_sop_out_cnt", + NPPU_MR_CFG_MR_COS1_SOP_OUT_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0178, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_mr_cfg_mr_cos1_sop_out_cnt_reg, + NULL, + NULL, + }, + { + "mr_cos1_eop_out_cnt", + NPPU_MR_CFG_MR_COS1_EOP_OUT_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x017c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_mr_cfg_mr_cos1_eop_out_cnt_reg, + NULL, + NULL, + }, + { + "mr_cos2_sop_out_cnt", + NPPU_MR_CFG_MR_COS2_SOP_OUT_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0180, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_mr_cfg_mr_cos2_sop_out_cnt_reg, + NULL, + NULL, + }, + { + "mr_cos2_eop_out_cnt", + NPPU_MR_CFG_MR_COS2_EOP_OUT_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0184, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_mr_cfg_mr_cos2_eop_out_cnt_reg, + NULL, + NULL, + }, + { + "mr_cos3_sop_out_cnt", + NPPU_MR_CFG_MR_COS3_SOP_OUT_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0188, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_mr_cfg_mr_cos3_sop_out_cnt_reg, + NULL, + NULL, + }, + { + "mr_cos3_eop_out_cnt", + NPPU_MR_CFG_MR_COS3_EOP_OUT_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x018c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_mr_cfg_mr_cos3_eop_out_cnt_reg, + NULL, + NULL, + }, + { + "mr_mlt_unvld_cnt", + NPPU_MR_CFG_MR_MLT_UNVLD_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0190, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_mr_cfg_mr_mlt_unvld_cnt_reg, + NULL, + NULL, + }, + { + "mr_sop_eop_match_cfg", + NPPU_MR_CFG_MR_SOP_EOP_MATCH_CFGr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0100, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_nppu_mr_cfg_mr_sop_eop_match_cfg_reg, + NULL, + NULL, + }, + { + "mr_mlt_unvld_mgid", + NPPU_MR_CFG_MR_MLT_UNVLD_MGIDr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0108, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_mr_cfg_mr_mlt_unvld_mgid_reg, + NULL, + NULL, + }, + { + "isch_fifo_th_1", + NPPU_PKTRX_CFG_ISCH_FIFO_TH_1r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0078, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_nppu_pktrx_cfg_isch_fifo_th_1_reg, + NULL, + NULL, + }, + { + "isch_fifo_th_2", + NPPU_PKTRX_CFG_ISCH_FIFO_TH_2r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x007c, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_nppu_pktrx_cfg_isch_fifo_th_2_reg, + NULL, + NULL, + }, + { + "isch_fifo_th_3", + NPPU_PKTRX_CFG_ISCH_FIFO_TH_3r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0080, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_nppu_pktrx_cfg_isch_fifo_th_3_reg, + NULL, + NULL, + }, + { + "isch_fifo_th_4", + NPPU_PKTRX_CFG_ISCH_FIFO_TH_4r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0084, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_nppu_pktrx_cfg_isch_fifo_th_4_reg, + NULL, + NULL, + }, + { + "isch_cfg_0", + NPPU_PKTRX_CFG_ISCH_CFG_0r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0088, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pktrx_cfg_isch_cfg_0_reg, + NULL, + NULL, + }, + { + "hdu_ex_tpid_0", + NPPU_PKTRX_CFG_HDU_EX_TPID_0r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0090, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_nppu_pktrx_cfg_hdu_ex_tpid_0_reg, + NULL, + NULL, + }, + { + "hdu_ex_tpid_1", + NPPU_PKTRX_CFG_HDU_EX_TPID_1r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0094, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_nppu_pktrx_cfg_hdu_ex_tpid_1_reg, + NULL, + NULL, + }, + { + "hdu_int_tpid_0", + NPPU_PKTRX_CFG_HDU_INT_TPID_0r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0098, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_nppu_pktrx_cfg_hdu_int_tpid_0_reg, + NULL, + NULL, + }, + { + "hdu_int_tpid_1", + NPPU_PKTRX_CFG_HDU_INT_TPID_1r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x009c, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_nppu_pktrx_cfg_hdu_int_tpid_1_reg, + NULL, + NULL, + }, + { + "hdu_hdlc_0", + NPPU_PKTRX_CFG_HDU_HDLC_0r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x00a0, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_nppu_pktrx_cfg_hdu_hdlc_0_reg, + NULL, + NULL, + }, + { + "hdu_hdlc_1", + NPPU_PKTRX_CFG_HDU_HDLC_1r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x00a4, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_nppu_pktrx_cfg_hdu_hdlc_1_reg, + NULL, + NULL, + }, + { + "hdu_udf_l3type_0", + NPPU_PKTRX_CFG_HDU_UDF_L3TYPE_0r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x00a8, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_nppu_pktrx_cfg_hdu_udf_l3type_0_reg, + NULL, + NULL, + }, + { + "hdu_udf_l3type_1", + NPPU_PKTRX_CFG_HDU_UDF_L3TYPE_1r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x00ac, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_nppu_pktrx_cfg_hdu_udf_l3type_1_reg, + NULL, + NULL, + }, + { + "hdu_udf_l3type_2", + NPPU_PKTRX_CFG_HDU_UDF_L3TYPE_2r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x00b0, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_nppu_pktrx_cfg_hdu_udf_l3type_2_reg, + NULL, + NULL, + }, + { + "hdu_udf_l3type_3", + NPPU_PKTRX_CFG_HDU_UDF_L3TYPE_3r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x00b4, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_nppu_pktrx_cfg_hdu_udf_l3type_3_reg, + NULL, + NULL, + }, + { + "hdu_udf_l4type_0", + NPPU_PKTRX_CFG_HDU_UDF_L4TYPE_0r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x00b8, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_nppu_pktrx_cfg_hdu_udf_l4type_0_reg, + NULL, + NULL, + }, + { + "hdu_udf_l4type_1", + NPPU_PKTRX_CFG_HDU_UDF_L4TYPE_1r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x00bc, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_nppu_pktrx_cfg_hdu_udf_l4type_1_reg, + NULL, + NULL, + }, + { + "hdu_udf_l4type_2", + NPPU_PKTRX_CFG_HDU_UDF_L4TYPE_2r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x00c0, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_nppu_pktrx_cfg_hdu_udf_l4type_2_reg, + NULL, + NULL, + }, + { + "slot_no_cfg", + NPPU_PKTRX_CFG_SLOT_NO_CFGr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x00d0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pktrx_cfg_slot_no_cfg_reg, + NULL, + NULL, + }, + { + "pktrx_int_en_0", + NPPU_PKTRX_CFG_PKTRX_INT_EN_0r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0114, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_nppu_pktrx_cfg_pktrx_int_en_0_reg, + NULL, + NULL, + }, + { + "pktrx_int_en_1", + NPPU_PKTRX_CFG_PKTRX_INT_EN_1r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0118, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_nppu_pktrx_cfg_pktrx_int_en_1_reg, + NULL, + NULL, + }, + { + "pktrx_int_mask_0", + NPPU_PKTRX_CFG_PKTRX_INT_MASK_0r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x011c, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_nppu_pktrx_cfg_pktrx_int_mask_0_reg, + NULL, + NULL, + }, + { + "pktrx_int_mask_1", + NPPU_PKTRX_CFG_PKTRX_INT_MASK_1r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0120, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_nppu_pktrx_cfg_pktrx_int_mask_1_reg, + NULL, + NULL, + }, + { + "pktrx_int_status", + NPPU_PKTRX_CFG_PKTRX_INT_STATUSr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0124, + (32/8), + 0, + 35 + 1, + 0, + 4, + 1, + g_nppu_pktrx_cfg_pktrx_int_status_reg, + NULL, + NULL, + }, + { + "pktrx_port_rdy0", + NPPU_PKTRX_CFG_PKTRX_PORT_RDY0r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x01b4, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_nppu_pktrx_cfg_pktrx_port_rdy0_reg, + NULL, + NULL, + }, + { + "pktrx_lif0_pfc_rdy0", + NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY0r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x01bc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy0_reg, + NULL, + NULL, + }, + { + "pktrx_lif0_pfc_rdy1", + NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY1r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x01c0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy1_reg, + NULL, + NULL, + }, + { + "pktrx_lif0_pfc_rdy2", + NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY2r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x01c4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy2_reg, + NULL, + NULL, + }, + { + "pktrx_lif0_pfc_rdy3", + NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY3r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x01c8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy3_reg, + NULL, + NULL, + }, + { + "pktrx_lif0_pfc_rdy4", + NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY4r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x01cc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy4_reg, + NULL, + NULL, + }, + { + "pktrx_lif0_pfc_rdy5", + NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY5r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x01d0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy5_reg, + NULL, + NULL, + }, + { + "pktrx_lif0_pfc_rdy6", + NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY6r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x01d4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy6_reg, + NULL, + NULL, + }, + { + "cfg_port_l2_offset_mode", + NPPU_PKTRX_CFG_CFG_PORT_L2_OFFSET_MODEr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x01d8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pktrx_cfg_cfg_port_l2_offset_mode_reg, + NULL, + NULL, + }, + { + "int_ram_en", + NPPU_IDMA_CFG_INT_RAM_ENr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_IDMA_CFG_BASE_ADDR + 0x000, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_nppu_idma_cfg_int_ram_en_reg, + NULL, + NULL, + }, + { + "int_ram_mask", + NPPU_IDMA_CFG_INT_RAM_MASKr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_IDMA_CFG_BASE_ADDR + 0x040, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_nppu_idma_cfg_int_ram_mask_reg, + NULL, + NULL, + }, + { + "int_ram_status", + NPPU_IDMA_CFG_INT_RAM_STATUSr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_IDMA_CFG_BASE_ADDR + 0x080, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_nppu_idma_cfg_int_ram_status_reg, + NULL, + NULL, + }, + { + "subsys_int_mask_flag", + NPPU_IDMA_CFG_SUBSYS_INT_MASK_FLAGr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_IDMA_CFG_BASE_ADDR + 0x180, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_idma_cfg_subsys_int_mask_flag_reg, + NULL, + NULL, + }, + { + "subsys_int_unmask_flag", + NPPU_IDMA_CFG_SUBSYS_INT_UNMASK_FLAGr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_IDMA_CFG_BASE_ADDR + 0x184, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_idma_cfg_subsys_int_unmask_flag_reg, + NULL, + NULL, + }, + { + "debug_cnt_rdclr_mode", + NPPU_IDMA_CFG_DEBUG_CNT_RDCLR_MODEr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_IDMA_CFG_BASE_ADDR + 0x4f8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_idma_cfg_debug_cnt_rdclr_mode_reg, + NULL, + NULL, + }, + { + "int_ram_en0", + NPPU_PBU_CFG_INT_RAM_EN0r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x000, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_nppu_pbu_cfg_int_ram_en0_reg, + NULL, + NULL, + }, + { + "int_ram_mask0", + NPPU_PBU_CFG_INT_RAM_MASK0r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x040, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_nppu_pbu_cfg_int_ram_mask0_reg, + NULL, + NULL, + }, + { + "int_ram_status0", + NPPU_PBU_CFG_INT_RAM_STATUS0r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x080, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_nppu_pbu_cfg_int_ram_status0_reg, + NULL, + NULL, + }, + { + "int_fifo_en0", + NPPU_PBU_CFG_INT_FIFO_EN0r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x0c0, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_nppu_pbu_cfg_int_fifo_en0_reg, + NULL, + NULL, + }, + { + "int_fifo_en1", + NPPU_PBU_CFG_INT_FIFO_EN1r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x0c4, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_nppu_pbu_cfg_int_fifo_en1_reg, + NULL, + NULL, + }, + { + "int_fifo_mask0", + NPPU_PBU_CFG_INT_FIFO_MASK0r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x100, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_nppu_pbu_cfg_int_fifo_mask0_reg, + NULL, + NULL, + }, + { + "int_fifo_mask1", + NPPU_PBU_CFG_INT_FIFO_MASK1r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x104, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_nppu_pbu_cfg_int_fifo_mask1_reg, + NULL, + NULL, + }, + { + "int_fifo_status0", + NPPU_PBU_CFG_INT_FIFO_STATUS0r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x140, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_nppu_pbu_cfg_int_fifo_status0_reg, + NULL, + NULL, + }, + { + "int_fifo_status1", + NPPU_PBU_CFG_INT_FIFO_STATUS1r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x144, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_nppu_pbu_cfg_int_fifo_status1_reg, + NULL, + NULL, + }, + { + "subsys_int_mask_flag", + NPPU_PBU_CFG_SUBSYS_INT_MASK_FLAGr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x180, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_cfg_subsys_int_mask_flag_reg, + NULL, + NULL, + }, + { + "subsys_int_unmask_flag", + NPPU_PBU_CFG_SUBSYS_INT_UNMASK_FLAGr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x184, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_cfg_subsys_int_unmask_flag_reg, + NULL, + NULL, + }, + { + "sa_ip_en", + NPPU_PBU_CFG_SA_IP_ENr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x4ec, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_cfg_sa_ip_en_reg, + NULL, + NULL, + }, + { + "debug_cnt_rdclr_mode", + NPPU_PBU_CFG_DEBUG_CNT_RDCLR_MODEr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x4f8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_cfg_debug_cnt_rdclr_mode_reg, + NULL, + NULL, + }, + { + "fptr_fifo_aful_assert_cfg", + NPPU_PBU_CFG_FPTR_FIFO_AFUL_ASSERT_CFGr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x50c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_cfg_fptr_fifo_aful_assert_cfg_reg, + NULL, + NULL, + }, + { + "fptr_fifo_aful_negate_cfg", + NPPU_PBU_CFG_FPTR_FIFO_AFUL_NEGATE_CFGr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x510, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_cfg_fptr_fifo_aful_negate_cfg_reg, + NULL, + NULL, + }, + { + "pf_fifo_aful_assert_cfg", + NPPU_PBU_CFG_PF_FIFO_AFUL_ASSERT_CFGr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x514, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_cfg_pf_fifo_aful_assert_cfg_reg, + NULL, + NULL, + }, + { + "pf_fifo_aful_negate_cfg", + NPPU_PBU_CFG_PF_FIFO_AFUL_NEGATE_CFGr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x518, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_cfg_pf_fifo_aful_negate_cfg_reg, + NULL, + NULL, + }, + { + "pf_fifo_aept_assert_cfg", + NPPU_PBU_CFG_PF_FIFO_AEPT_ASSERT_CFGr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x51c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_cfg_pf_fifo_aept_assert_cfg_reg, + NULL, + NULL, + }, + { + "pf_fifo_aept_negate_cfg", + NPPU_PBU_CFG_PF_FIFO_AEPT_NEGATE_CFGr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x520, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_cfg_pf_fifo_aept_negate_cfg_reg, + NULL, + NULL, + }, + { + "wb_aful_assert_cfg", + NPPU_PBU_CFG_WB_AFUL_ASSERT_CFGr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x524, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_cfg_wb_aful_assert_cfg_reg, + NULL, + NULL, + }, + { + "wb_aful_negate_cfg", + NPPU_PBU_CFG_WB_AFUL_NEGATE_CFGr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x528, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_cfg_wb_aful_negate_cfg_reg, + NULL, + NULL, + }, + { + "se_key_aful_assert_cfg", + NPPU_PBU_CFG_SE_KEY_AFUL_ASSERT_CFGr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x52c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_cfg_se_key_aful_assert_cfg_reg, + NULL, + NULL, + }, + { + "ifbrd_se_aful_assert_cfg", + NPPU_PBU_CFG_IFBRD_SE_AFUL_ASSERT_CFGr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x534, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_cfg_ifbrd_se_aful_assert_cfg_reg, + NULL, + NULL, + }, + { + "ifbrd_se_aful_negate_cfg", + NPPU_PBU_CFG_IFBRD_SE_AFUL_NEGATE_CFGr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x538, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_cfg_ifbrd_se_aful_negate_cfg_reg, + NULL, + NULL, + }, + { + "ifbrd_odma_aful_assert_cfg", + NPPU_PBU_CFG_IFBRD_ODMA_AFUL_ASSERT_CFGr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x53c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_cfg_ifbrd_odma_aful_assert_cfg_reg, + NULL, + NULL, + }, + { + "ifbrd_odma_aful_negate_cfg", + NPPU_PBU_CFG_IFBRD_ODMA_AFUL_NEGATE_CFGr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x540, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_cfg_ifbrd_odma_aful_negate_cfg_reg, + NULL, + NULL, + }, + { + "ifbrd_ppu_aful_assert_cfg", + NPPU_PBU_CFG_IFBRD_PPU_AFUL_ASSERT_CFGr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x544, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_cfg_ifbrd_ppu_aful_assert_cfg_reg, + NULL, + NULL, + }, + { + "ifbrd_ppu_aful_negate_cfg", + NPPU_PBU_CFG_IFBRD_PPU_AFUL_NEGATE_CFGr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x548, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_cfg_ifbrd_ppu_aful_negate_cfg_reg, + NULL, + NULL, + }, + { + "mc_logic_aful_assert_cfg", + NPPU_PBU_CFG_MC_LOGIC_AFUL_ASSERT_CFGr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x54c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_cfg_mc_logic_aful_assert_cfg_reg, + NULL, + NULL, + }, + { + "mc_logic_aful_negate_cfg", + NPPU_PBU_CFG_MC_LOGIC_AFUL_NEGATE_CFGr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x550, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_cfg_mc_logic_aful_negate_cfg_reg, + NULL, + NULL, + }, + { + "mc_logic_diff", + NPPU_PBU_CFG_MC_LOGIC_DIFFr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x5e4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_cfg_mc_logic_diff_reg, + NULL, + NULL, + }, + { + "cfg_peak_port_cnt_clr", + NPPU_PBU_CFG_CFG_PEAK_PORT_CNT_CLRr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x0600, + (32/8), + 0, + 3 + 1, + 0, + 4, + 1, + g_nppu_pbu_cfg_cfg_peak_port_cnt_clr_reg, + NULL, + NULL, + }, + { + "all_ftm_crdt_th", + NPPU_PBU_CFG_ALL_FTM_CRDT_THr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x0640, + (32/8), + 0, + 47 + 1, + 0, + 4, + 2, + g_nppu_pbu_cfg_all_ftm_crdt_th_reg, + NULL, + NULL, + }, + { + "all_ftm_link_th_01", + NPPU_PBU_CFG_ALL_FTM_LINK_TH_01r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x700, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_nppu_pbu_cfg_all_ftm_link_th_01_reg, + NULL, + NULL, + }, + { + "all_ftm_link_th_23", + NPPU_PBU_CFG_ALL_FTM_LINK_TH_23r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x704, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_nppu_pbu_cfg_all_ftm_link_th_23_reg, + NULL, + NULL, + }, + { + "all_ftm_link_th_45", + NPPU_PBU_CFG_ALL_FTM_LINK_TH_45r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x708, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_nppu_pbu_cfg_all_ftm_link_th_45_reg, + NULL, + NULL, + }, + { + "all_ftm_link_th_6", + NPPU_PBU_CFG_ALL_FTM_LINK_TH_6r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x70c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_cfg_all_ftm_link_th_6_reg, + NULL, + NULL, + }, + { + "all_ftm_total_congest_th", + NPPU_PBU_CFG_ALL_FTM_TOTAL_CONGEST_THr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x710, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_cfg_all_ftm_total_congest_th_reg, + NULL, + NULL, + }, + { + "cfg_crdt_mode", + NPPU_PBU_CFG_CFG_CRDT_MODEr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x720, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_cfg_cfg_crdt_mode_reg, + NULL, + NULL, + }, + { + "cfg_pfc_rdy_high_time", + NPPU_PBU_CFG_CFG_PFC_RDY_HIGH_TIMEr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x728, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_cfg_cfg_pfc_rdy_high_time_reg, + NULL, + NULL, + }, + { + "cfg_pfc_rdy_low_time", + NPPU_PBU_CFG_CFG_PFC_RDY_LOW_TIMEr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x72c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_cfg_cfg_pfc_rdy_low_time_reg, + NULL, + NULL, + }, + { + "pbu_fc_rdy", + NPPU_PBU_STAT_PBU_FC_RDYr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x580, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_nppu_pbu_stat_pbu_fc_rdy_reg, + NULL, + NULL, + }, + { + "pbu_lif_group0_rdy0", + NPPU_PBU_STAT_PBU_LIF_GROUP0_RDY0r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x5c0, + (32/8), + 0, + 0, + 0, + 0, + 5, + g_nppu_pbu_stat_pbu_lif_group0_rdy0_reg, + NULL, + NULL, + }, + { + "pbu_lif_group0_rdy1", + NPPU_PBU_STAT_PBU_LIF_GROUP0_RDY1r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x5c4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_stat_pbu_lif_group0_rdy1_reg, + NULL, + NULL, + }, + { + "pbu_lif_group1_rdy", + NPPU_PBU_STAT_PBU_LIF_GROUP1_RDYr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x5e0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_stat_pbu_lif_group1_rdy_reg, + NULL, + NULL, + }, + { + "pbu_lif_group0_pfc_rdy", + NPPU_PBU_STAT_PBU_LIF_GROUP0_PFC_RDYr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x0600, + (32/8), + 0, + 11 + 1, + 0, + 4, + 1, + g_nppu_pbu_stat_pbu_lif_group0_pfc_rdy_reg, + NULL, + NULL, + }, + { + "pbu_lif_group1_pfc_rdy", + NPPU_PBU_STAT_PBU_LIF_GROUP1_PFC_RDYr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x0640, + (32/8), + 0, + 1 + 1, + 0, + 4, + 1, + g_nppu_pbu_stat_pbu_lif_group1_pfc_rdy_reg, + NULL, + NULL, + }, + { + "pbu_sa_port_rdy_0_31", + NPPU_PBU_STAT_PBU_SA_PORT_RDY_0_31r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x680, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_stat_pbu_sa_port_rdy_0_31_reg, + NULL, + NULL, + }, + { + "pbu_sa_port_rdy_32_50", + NPPU_PBU_STAT_PBU_SA_PORT_RDY_32_50r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x684, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_stat_pbu_sa_port_rdy_32_50_reg, + NULL, + NULL, + }, + { + "pbu_pktrx_mr_pfc_rdy", + NPPU_PBU_STAT_PBU_PKTRX_MR_PFC_RDYr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x6a0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_stat_pbu_pktrx_mr_pfc_rdy_reg, + NULL, + NULL, + }, + { + "pbu_ftm_crdt_port_rdy_0_31", + NPPU_PBU_STAT_PBU_FTM_CRDT_PORT_RDY_0_31r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x6a4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_stat_pbu_ftm_crdt_port_rdy_0_31_reg, + NULL, + NULL, + }, + { + "pbu_ftm_crdt_port_rdy_32_47", + NPPU_PBU_STAT_PBU_FTM_CRDT_PORT_RDY_32_47r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x6a8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_stat_pbu_ftm_crdt_port_rdy_32_47_reg, + NULL, + NULL, + }, + { + "pbu_ftm_crdt_port_cng_rdy_0_31", + NPPU_PBU_STAT_PBU_FTM_CRDT_PORT_CNG_RDY_0_31r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x6ac, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_stat_pbu_ftm_crdt_port_cng_rdy_0_31_reg, + NULL, + NULL, + }, + { + "pbu_ftm_crdt_port_cng_rdy_32_47", + NPPU_PBU_STAT_PBU_FTM_CRDT_PORT_CNG_RDY_32_47r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x6b0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_stat_pbu_ftm_crdt_port_cng_rdy_32_47_reg, + NULL, + NULL, + }, + { + "pbu_ftm_crdt_sys_info", + NPPU_PBU_STAT_PBU_FTM_CRDT_SYS_INFOr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x6b4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_pbu_stat_pbu_ftm_crdt_sys_info_reg, + NULL, + NULL, + }, + { + "weight_normal_mc", + NPPU_ISU_CFG_WEIGHT_NORMAL_MCr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_CFG_BASE_ADDR + 0x0004, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_isu_cfg_weight_normal_mc_reg, + NULL, + NULL, + }, + { + "weight_sa_mc", + NPPU_ISU_CFG_WEIGHT_SA_MCr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_CFG_BASE_ADDR + 0x0008, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_isu_cfg_weight_sa_mc_reg, + NULL, + NULL, + }, + { + "weight_etm", + NPPU_ISU_CFG_WEIGHT_ETMr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_CFG_BASE_ADDR + 0x000c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_isu_cfg_weight_etm_reg, + NULL, + NULL, + }, + { + "weight_lp_mc", + NPPU_ISU_CFG_WEIGHT_LP_MCr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_CFG_BASE_ADDR + 0x0010, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_isu_cfg_weight_lp_mc_reg, + NULL, + NULL, + }, + { + "weight_oam", + NPPU_ISU_CFG_WEIGHT_OAMr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_CFG_BASE_ADDR + 0x0014, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_isu_cfg_weight_oam_reg, + NULL, + NULL, + }, + { + "weight_lif_ctrl1", + NPPU_ISU_CFG_WEIGHT_LIF_CTRL1r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_CFG_BASE_ADDR + 0x0018, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_isu_cfg_weight_lif_ctrl1_reg, + NULL, + NULL, + }, + { + "weight_lif_ctrl2", + NPPU_ISU_CFG_WEIGHT_LIF_CTRL2r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_CFG_BASE_ADDR + 0x001c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_isu_cfg_weight_lif_ctrl2_reg, + NULL, + NULL, + }, + { + "ecc_bypass_read", + NPPU_ISU_CFG_ECC_BYPASS_READr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_CFG_BASE_ADDR + 0x0020, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_isu_cfg_ecc_bypass_read_reg, + NULL, + NULL, + }, + { + "isu_int_mask", + NPPU_ISU_CFG_ISU_INT_MASKr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_CFG_BASE_ADDR + 0x0024, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_isu_cfg_isu_int_mask_reg, + NULL, + NULL, + }, + { + "cfg_crdt_cycle", + NPPU_ISU_CFG_CFG_CRDT_CYCLEr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_CFG_BASE_ADDR + 0x002c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_isu_cfg_cfg_crdt_cycle_reg, + NULL, + NULL, + }, + { + "cfg_crdt_value", + NPPU_ISU_CFG_CFG_CRDT_VALUEr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_CFG_BASE_ADDR + 0x0030, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_isu_cfg_cfg_crdt_value_reg, + NULL, + NULL, + }, + { + "isu_int_en", + NPPU_ISU_CFG_ISU_INT_ENr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_CFG_BASE_ADDR + 0x0034, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_isu_cfg_isu_int_en_reg, + NULL, + NULL, + }, + { + "isu_ppu_fifo_fc", + NPPU_ISU_CFG_ISU_PPU_FIFO_FCr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_CFG_BASE_ADDR + 0x0038, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_isu_cfg_isu_ppu_fifo_fc_reg, + NULL, + NULL, + }, + { + "isu_int_status", + NPPU_ISU_CFG_ISU_INT_STATUSr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_CFG_BASE_ADDR + 0x003c, + (32/8), + 0, + 0, + 0, + 0, + 27, + g_nppu_isu_cfg_isu_int_status_reg, + NULL, + NULL, + }, + { + "fd_prog_full_assert_cfg", + NPPU_ISU_CFG_FD_PROG_FULL_ASSERT_CFGr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_CFG_BASE_ADDR + 0x0040, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_isu_cfg_fd_prog_full_assert_cfg_reg, + NULL, + NULL, + }, + { + "fd_prog_full_negate_cfg", + NPPU_ISU_CFG_FD_PROG_FULL_NEGATE_CFGr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_CFG_BASE_ADDR + 0x0044, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_isu_cfg_fd_prog_full_negate_cfg_reg, + NULL, + NULL, + }, + { + "lp_prog_full_assert_cfg", + NPPU_ISU_CFG_LP_PROG_FULL_ASSERT_CFGr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_CFG_BASE_ADDR + 0x0048, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_isu_cfg_lp_prog_full_assert_cfg_reg, + NULL, + NULL, + }, + { + "lp_prog_full_negate_cfg", + NPPU_ISU_CFG_LP_PROG_FULL_NEGATE_CFGr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_CFG_BASE_ADDR + 0x004c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_isu_cfg_lp_prog_full_negate_cfg_reg, + NULL, + NULL, + }, + { + "debug_cnt_dat0", + NPPU_ISU_STAT_DEBUG_CNT_DAT0r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x000c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_isu_stat_debug_cnt_dat0_reg, + NULL, + NULL, + }, + { + "debug_cnt_dat1", + NPPU_ISU_STAT_DEBUG_CNT_DAT1r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x0010, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_isu_stat_debug_cnt_dat1_reg, + NULL, + NULL, + }, + { + "debug_cnt_dat2", + NPPU_ISU_STAT_DEBUG_CNT_DAT2r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x0014, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_isu_stat_debug_cnt_dat2_reg, + NULL, + NULL, + }, + { + "debug_cnt_dat3", + NPPU_ISU_STAT_DEBUG_CNT_DAT3r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x0018, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_isu_stat_debug_cnt_dat3_reg, + NULL, + NULL, + }, + { + "debug_cnt_dat4", + NPPU_ISU_STAT_DEBUG_CNT_DAT4r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x001c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_isu_stat_debug_cnt_dat4_reg, + NULL, + NULL, + }, + { + "debug_cnt_dat5", + NPPU_ISU_STAT_DEBUG_CNT_DAT5r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x0020, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_isu_stat_debug_cnt_dat5_reg, + NULL, + NULL, + }, + { + "debug_cnt_dat6", + NPPU_ISU_STAT_DEBUG_CNT_DAT6r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x0024, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_isu_stat_debug_cnt_dat6_reg, + NULL, + NULL, + }, + { + "debug_cnt_dat7", + NPPU_ISU_STAT_DEBUG_CNT_DAT7r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x0028, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_isu_stat_debug_cnt_dat7_reg, + NULL, + NULL, + }, + { + "debug_cnt_dat8", + NPPU_ISU_STAT_DEBUG_CNT_DAT8r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x002c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_isu_stat_debug_cnt_dat8_reg, + NULL, + NULL, + }, + { + "debug_cnt_dat9", + NPPU_ISU_STAT_DEBUG_CNT_DAT9r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x0030, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_isu_stat_debug_cnt_dat9_reg, + NULL, + NULL, + }, + { + "debug_cnt_dat10", + NPPU_ISU_STAT_DEBUG_CNT_DAT10r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x0034, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_isu_stat_debug_cnt_dat10_reg, + NULL, + NULL, + }, + { + "debug_cnt_dat11", + NPPU_ISU_STAT_DEBUG_CNT_DAT11r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x0038, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_isu_stat_debug_cnt_dat11_reg, + NULL, + NULL, + }, + { + "debug_cnt_dat12", + NPPU_ISU_STAT_DEBUG_CNT_DAT12r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x003c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_isu_stat_debug_cnt_dat12_reg, + NULL, + NULL, + }, + { + "debug_cnt_dat13", + NPPU_ISU_STAT_DEBUG_CNT_DAT13r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x0040, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_isu_stat_debug_cnt_dat13_reg, + NULL, + NULL, + }, + { + "debug_cnt_dat14", + NPPU_ISU_STAT_DEBUG_CNT_DAT14r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x0044, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_isu_stat_debug_cnt_dat14_reg, + NULL, + NULL, + }, + { + "debug_cnt_dat15", + NPPU_ISU_STAT_DEBUG_CNT_DAT15r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x0048, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_isu_stat_debug_cnt_dat15_reg, + NULL, + NULL, + }, + { + "debug_cnt_dat16", + NPPU_ISU_STAT_DEBUG_CNT_DAT16r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x004c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_isu_stat_debug_cnt_dat16_reg, + NULL, + NULL, + }, + { + "debug_cnt_dat17", + NPPU_ISU_STAT_DEBUG_CNT_DAT17r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x0050, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_isu_stat_debug_cnt_dat17_reg, + NULL, + NULL, + }, + { + "debug_cnt_dat18", + NPPU_ISU_STAT_DEBUG_CNT_DAT18r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x0054, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_isu_stat_debug_cnt_dat18_reg, + NULL, + NULL, + }, + { + "debug_cnt_dat19", + NPPU_ISU_STAT_DEBUG_CNT_DAT19r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x0058, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_isu_stat_debug_cnt_dat19_reg, + NULL, + NULL, + }, + { + "debug_cnt_cfg", + NPPU_ISU_STAT_DEBUG_CNT_CFGr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x0100, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_nppu_isu_stat_debug_cnt_cfg_reg, + NULL, + NULL, + }, + { + "exsa_tdm_offset", + NPPU_ODMA_CFG_EXSA_TDM_OFFSETr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0014, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_exsa_tdm_offset_reg, + NULL, + NULL, + }, + { + "ecc_bypass_readt", + NPPU_ODMA_CFG_ECC_BYPASS_READTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0018, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_ecc_bypass_readt_reg, + NULL, + NULL, + }, + { + "odma_int_en_0", + NPPU_ODMA_CFG_ODMA_INT_EN_0r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0020, + (32/8), + 0, + 0, + 0, + 0, + 11, + g_nppu_odma_cfg_odma_int_en_0_reg, + NULL, + NULL, + }, + { + "odma_int_en_1", + NPPU_ODMA_CFG_ODMA_INT_EN_1r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0024, + (32/8), + 0, + 0, + 0, + 0, + 23, + g_nppu_odma_cfg_odma_int_en_1_reg, + NULL, + NULL, + }, + { + "odma_int_en_2", + NPPU_ODMA_CFG_ODMA_INT_EN_2r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0028, + (32/8), + 0, + 0, + 0, + 0, + 10, + g_nppu_odma_cfg_odma_int_en_2_reg, + NULL, + NULL, + }, + { + "odma_int_en_3", + NPPU_ODMA_CFG_ODMA_INT_EN_3r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x002c, + (32/8), + 0, + 0, + 0, + 0, + 13, + g_nppu_odma_cfg_odma_int_en_3_reg, + NULL, + NULL, + }, + { + "odma_int_mask_0", + NPPU_ODMA_CFG_ODMA_INT_MASK_0r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0030, + (32/8), + 0, + 0, + 0, + 0, + 11, + g_nppu_odma_cfg_odma_int_mask_0_reg, + NULL, + NULL, + }, + { + "odma_int_mask_1", + NPPU_ODMA_CFG_ODMA_INT_MASK_1r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0034, + (32/8), + 0, + 0, + 0, + 0, + 24, + g_nppu_odma_cfg_odma_int_mask_1_reg, + NULL, + NULL, + }, + { + "odma_int_mask_2", + NPPU_ODMA_CFG_ODMA_INT_MASK_2r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0038, + (32/8), + 0, + 0, + 0, + 0, + 10, + g_nppu_odma_cfg_odma_int_mask_2_reg, + NULL, + NULL, + }, + { + "odma_int_mask_3", + NPPU_ODMA_CFG_ODMA_INT_MASK_3r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x003c, + (32/8), + 0, + 0, + 0, + 0, + 13, + g_nppu_odma_cfg_odma_int_mask_3_reg, + NULL, + NULL, + }, + { + "odma_int_status_0", + NPPU_ODMA_CFG_ODMA_INT_STATUS_0r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0040, + (32/8), + 0, + 0, + 0, + 0, + 11, + g_nppu_odma_cfg_odma_int_status_0_reg, + NULL, + NULL, + }, + { + "odma_int_status_1", + NPPU_ODMA_CFG_ODMA_INT_STATUS_1r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0044, + (32/8), + 0, + 0, + 0, + 0, + 23, + g_nppu_odma_cfg_odma_int_status_1_reg, + NULL, + NULL, + }, + { + "odma_int_status_2", + NPPU_ODMA_CFG_ODMA_INT_STATUS_2r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0048, + (32/8), + 0, + 0, + 0, + 0, + 10, + g_nppu_odma_cfg_odma_int_status_2_reg, + NULL, + NULL, + }, + { + "odma_int_status_3", + NPPU_ODMA_CFG_ODMA_INT_STATUS_3r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x004c, + (32/8), + 0, + 0, + 0, + 0, + 15, + g_nppu_odma_cfg_odma_int_status_3_reg, + NULL, + NULL, + }, + { + "sp_tdm_err_nor_cfg", + NPPU_ODMA_CFG_SP_TDM_ERR_NOR_CFGr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0050, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_sp_tdm_err_nor_cfg_reg, + NULL, + NULL, + }, + { + "etm_dis_ptr_prog_full_cfg_a", + NPPU_ODMA_CFG_ETM_DIS_PTR_PROG_FULL_CFG_Ar, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0068, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_etm_dis_ptr_prog_full_cfg_a_reg, + NULL, + NULL, + }, + { + "etm_dis_ptr_prog_full_cfg_n", + NPPU_ODMA_CFG_ETM_DIS_PTR_PROG_FULL_CFG_Nr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x006c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_etm_dis_ptr_prog_full_cfg_n_reg, + NULL, + NULL, + }, + { + "ftm_dis_ptr_prog_full_cfg_a", + NPPU_ODMA_CFG_FTM_DIS_PTR_PROG_FULL_CFG_Ar, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0070, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_ftm_dis_ptr_prog_full_cfg_a_reg, + NULL, + NULL, + }, + { + "ftm_dis_ptr_prog_full_cfg_n", + NPPU_ODMA_CFG_FTM_DIS_PTR_PROG_FULL_CFG_Nr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0074, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_ftm_dis_ptr_prog_full_cfg_n_reg, + NULL, + NULL, + }, + { + "tm_dis_fifo_prog_full_cfg_a", + NPPU_ODMA_CFG_TM_DIS_FIFO_PROG_FULL_CFG_Ar, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0078, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_tm_dis_fifo_prog_full_cfg_a_reg, + NULL, + NULL, + }, + { + "tm_dis_fifo_prog_full_cfg_n", + NPPU_ODMA_CFG_TM_DIS_FIFO_PROG_FULL_CFG_Nr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x007c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_tm_dis_fifo_prog_full_cfg_n_reg, + NULL, + NULL, + }, + { + "err_prog_full_cfg_a", + NPPU_ODMA_CFG_ERR_PROG_FULL_CFG_Ar, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0088, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_err_prog_full_cfg_a_reg, + NULL, + NULL, + }, + { + "err_prog_full_cfg_n", + NPPU_ODMA_CFG_ERR_PROG_FULL_CFG_Nr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x008c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_err_prog_full_cfg_n_reg, + NULL, + NULL, + }, + { + "tdmuc_prog_full_cfg_a", + NPPU_ODMA_CFG_TDMUC_PROG_FULL_CFG_Ar, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0090, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_tdmuc_prog_full_cfg_a_reg, + NULL, + NULL, + }, + { + "tdmuc_prog_full_cfg_n", + NPPU_ODMA_CFG_TDMUC_PROG_FULL_CFG_Nr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0094, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_tdmuc_prog_full_cfg_n_reg, + NULL, + NULL, + }, + { + "tdmmc_groupid_prog_full_cfg_a", + NPPU_ODMA_CFG_TDMMC_GROUPID_PROG_FULL_CFG_Ar, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0098, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_tdmmc_groupid_prog_full_cfg_a_reg, + NULL, + NULL, + }, + { + "tdmmc_groupid_prog_full_cfg_n", + NPPU_ODMA_CFG_TDMMC_GROUPID_PROG_FULL_CFG_Nr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x009c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_tdmmc_groupid_prog_full_cfg_n_reg, + NULL, + NULL, + }, + { + "tdmmc_no_bitmap_prog_full_cfg_a", + NPPU_ODMA_CFG_TDMMC_NO_BITMAP_PROG_FULL_CFG_Ar, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00a0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_tdmmc_no_bitmap_prog_full_cfg_a_reg, + NULL, + NULL, + }, + { + "tdmmc_no_bitmap_prog_full_cfg_n", + NPPU_ODMA_CFG_TDMMC_NO_BITMAP_PROG_FULL_CFG_Nr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00a4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_tdmmc_no_bitmap_prog_full_cfg_n_reg, + NULL, + NULL, + }, + { + "tdmmc_prog_full_cfg_a", + NPPU_ODMA_CFG_TDMMC_PROG_FULL_CFG_Ar, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00a8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_tdmmc_prog_full_cfg_a_reg, + NULL, + NULL, + }, + { + "tdmmc_prog_full_cfg_n", + NPPU_ODMA_CFG_TDMMC_PROG_FULL_CFG_Nr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00ac, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_tdmmc_prog_full_cfg_n_reg, + NULL, + NULL, + }, + { + "desc_prog_full_cfg_a", + NPPU_ODMA_CFG_DESC_PROG_FULL_CFG_Ar, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00b0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_desc_prog_full_cfg_a_reg, + NULL, + NULL, + }, + { + "desc_prog_full_cfg_n", + NPPU_ODMA_CFG_DESC_PROG_FULL_CFG_Nr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00b4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_desc_prog_full_cfg_n_reg, + NULL, + NULL, + }, + { + "dly_prog_full_cfg_a", + NPPU_ODMA_CFG_DLY_PROG_FULL_CFG_Ar, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00b8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_dly_prog_full_cfg_a_reg, + NULL, + NULL, + }, + { + "dly_prog_full_cfg_n", + NPPU_ODMA_CFG_DLY_PROG_FULL_CFG_Nr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00bc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_dly_prog_full_cfg_n_reg, + NULL, + NULL, + }, + { + "rsp_prog_full_cfg_a", + NPPU_ODMA_CFG_RSP_PROG_FULL_CFG_Ar, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00c0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_rsp_prog_full_cfg_a_reg, + NULL, + NULL, + }, + { + "rsp_prog_full_cfg_n", + NPPU_ODMA_CFG_RSP_PROG_FULL_CFG_Nr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00c4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_rsp_prog_full_cfg_n_reg, + NULL, + NULL, + }, + { + "nor_prog_full_cfg_a", + NPPU_ODMA_CFG_NOR_PROG_FULL_CFG_Ar, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00c8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_nor_prog_full_cfg_a_reg, + NULL, + NULL, + }, + { + "nor_prog_full_cfg_n", + NPPU_ODMA_CFG_NOR_PROG_FULL_CFG_Nr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00cc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_nor_prog_full_cfg_n_reg, + NULL, + NULL, + }, + { + "etm_nor_prog_full_cfg_a", + NPPU_ODMA_CFG_ETM_NOR_PROG_FULL_CFG_Ar, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00d0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_etm_nor_prog_full_cfg_a_reg, + NULL, + NULL, + }, + { + "etm_nor_prog_full_cfg_n", + NPPU_ODMA_CFG_ETM_NOR_PROG_FULL_CFG_Nr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00d4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_etm_nor_prog_full_cfg_n_reg, + NULL, + NULL, + }, + { + "ftm_nor_prog_full_cfg_a", + NPPU_ODMA_CFG_FTM_NOR_PROG_FULL_CFG_Ar, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00d8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_ftm_nor_prog_full_cfg_a_reg, + NULL, + NULL, + }, + { + "ftm_nor_prog_full_cfg_n", + NPPU_ODMA_CFG_FTM_NOR_PROG_FULL_CFG_Nr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00dc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_ftm_nor_prog_full_cfg_n_reg, + NULL, + NULL, + }, + { + "etm_prog_full_cfg_a", + NPPU_ODMA_CFG_ETM_PROG_FULL_CFG_Ar, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00e0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_etm_prog_full_cfg_a_reg, + NULL, + NULL, + }, + { + "etm_prog_full_cfg_n", + NPPU_ODMA_CFG_ETM_PROG_FULL_CFG_Nr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00e4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_etm_prog_full_cfg_n_reg, + NULL, + NULL, + }, + { + "ftm_prog_full_cfg_a", + NPPU_ODMA_CFG_FTM_PROG_FULL_CFG_Ar, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00e8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_ftm_prog_full_cfg_a_reg, + NULL, + NULL, + }, + { + "ftm_prog_full_cfg_n", + NPPU_ODMA_CFG_FTM_PROG_FULL_CFG_Nr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00ec, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_ftm_prog_full_cfg_n_reg, + NULL, + NULL, + }, + { + "etm_nrdcnt_prog_full_cfg_a", + NPPU_ODMA_CFG_ETM_NRDCNT_PROG_FULL_CFG_Ar, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00f0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_etm_nrdcnt_prog_full_cfg_a_reg, + NULL, + NULL, + }, + { + "etm_nrdcnt_prog_full_cfg_n", + NPPU_ODMA_CFG_ETM_NRDCNT_PROG_FULL_CFG_Nr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00f4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_etm_nrdcnt_prog_full_cfg_n_reg, + NULL, + NULL, + }, + { + "ftm_nrdcnt_prog_full_cfg_a", + NPPU_ODMA_CFG_FTM_NRDCNT_PROG_FULL_CFG_Ar, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00f8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_ftm_nrdcnt_prog_full_cfg_a_reg, + NULL, + NULL, + }, + { + "ftm_nrdcnt_prog_full_cfg_n", + NPPU_ODMA_CFG_FTM_NRDCNT_PROG_FULL_CFG_Nr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00fc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_ftm_nrdcnt_prog_full_cfg_n_reg, + NULL, + NULL, + }, + { + "pp_prog_full_cfg_a", + NPPU_ODMA_CFG_PP_PROG_FULL_CFG_Ar, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0104, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_pp_prog_full_cfg_a_reg, + NULL, + NULL, + }, + { + "pp_prog_full_cfg_n", + NPPU_ODMA_CFG_PP_PROG_FULL_CFG_Nr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0108, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_pp_prog_full_cfg_n_reg, + NULL, + NULL, + }, + { + "tm_weight", + NPPU_ODMA_CFG_TM_WEIGHTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x010c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_tm_weight_reg, + NULL, + NULL, + }, + { + "pp_weight", + NPPU_ODMA_CFG_PP_WEIGHTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0110, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_pp_weight_reg, + NULL, + NULL, + }, + { + "ifbcmd_prog_full_cfg_a", + NPPU_ODMA_CFG_IFBCMD_PROG_FULL_CFG_Ar, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0218, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_ifbcmd_prog_full_cfg_a_reg, + NULL, + NULL, + }, + { + "ifbcmd_prog_full_cfg_n", + NPPU_ODMA_CFG_IFBCMD_PROG_FULL_CFG_Nr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x021c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_ifbcmd_prog_full_cfg_n_reg, + NULL, + NULL, + }, + { + "mccnt_prog_full_cfg_a", + NPPU_ODMA_CFG_MCCNT_PROG_FULL_CFG_Ar, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0220, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_mccnt_prog_full_cfg_a_reg, + NULL, + NULL, + }, + { + "mccnt_prog_full_cfg_n", + NPPU_ODMA_CFG_MCCNT_PROG_FULL_CFG_Nr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0224, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_mccnt_prog_full_cfg_n_reg, + NULL, + NULL, + }, + { + "int_or_pon", + NPPU_ODMA_CFG_INT_OR_PONr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x228, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_int_or_pon_reg, + NULL, + NULL, + }, + { + "quemng_cnt_in_err_cnt", + NPPU_ODMA_CFG_QUEMNG_CNT_IN_ERR_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x22c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_quemng_cnt_in_err_cnt_reg, + NULL, + NULL, + }, + { + "lif0_port_eop_cnt", + NPPU_ODMA_CFG_LIF0_PORT_EOP_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x240, + (32/8), + 0, + 47 + 1, + 0, + 4, + 1, + g_nppu_odma_cfg_lif0_port_eop_cnt_reg, + NULL, + NULL, + }, + { + "lif1_port_eop_cnt", + NPPU_ODMA_CFG_LIF1_PORT_EOP_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x300, + (32/8), + 0, + 7 + 1, + 0, + 4, + 1, + g_nppu_odma_cfg_lif1_port_eop_cnt_reg, + NULL, + NULL, + }, + { + "lifc_port0_eop_cnt", + NPPU_ODMA_CFG_LIFC_PORT0_EOP_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x320, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_lifc_port0_eop_cnt_reg, + NULL, + NULL, + }, + { + "lifc_port1_eop_cnt", + NPPU_ODMA_CFG_LIFC_PORT1_EOP_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x324, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_lifc_port1_eop_cnt_reg, + NULL, + NULL, + }, + { + "fptr_fifo_prog_ept_cfg_n", + NPPU_ODMA_CFG_FPTR_FIFO_PROG_EPT_CFG_Nr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0404, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_fptr_fifo_prog_ept_cfg_n_reg, + NULL, + NULL, + }, + { + "isu_fifo_prog_full_cfg_a", + NPPU_ODMA_CFG_ISU_FIFO_PROG_FULL_CFG_Ar, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0408, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_isu_fifo_prog_full_cfg_a_reg, + NULL, + NULL, + }, + { + "isu_fifo_prog_full_cfg_n", + NPPU_ODMA_CFG_ISU_FIFO_PROG_FULL_CFG_Nr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x040c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_odma_cfg_isu_fifo_prog_full_cfg_n_reg, + NULL, + NULL, + }, + { + "ind_access_done", + NPPU_OAM_CFG_IND_ACCESS_DONEr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0000, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_ind_access_done_reg, + NULL, + NULL, + }, + { + "ind_access_command", + NPPU_OAM_CFG_IND_ACCESS_COMMANDr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0004, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_nppu_oam_cfg_ind_access_command_reg, + NULL, + NULL, + }, + { + "ind_dat0", + NPPU_OAM_CFG_IND_DAT0r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0008, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_ind_dat0_reg, + NULL, + NULL, + }, + { + "ind_dat1", + NPPU_OAM_CFG_IND_DAT1r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x000c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_ind_dat1_reg, + NULL, + NULL, + }, + { + "ind_dat2", + NPPU_OAM_CFG_IND_DAT2r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0010, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_ind_dat2_reg, + NULL, + NULL, + }, + { + "ind_dat3", + NPPU_OAM_CFG_IND_DAT3r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0014, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_ind_dat3_reg, + NULL, + NULL, + }, + { + "oam_tx_main_en", + NPPU_OAM_CFG_OAM_TX_MAIN_ENr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0018, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_oam_tx_main_en_reg, + NULL, + NULL, + }, + { + "tx_total_num", + NPPU_OAM_CFG_TX_TOTAL_NUMr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x001c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_tx_total_num_reg, + NULL, + NULL, + }, + { + "oam_chk_main_en", + NPPU_OAM_CFG_OAM_CHK_MAIN_ENr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0020, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_oam_chk_main_en_reg, + NULL, + NULL, + }, + { + "chk_total_num0", + NPPU_OAM_CFG_CHK_TOTAL_NUM0r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0024, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_chk_total_num0_reg, + NULL, + NULL, + }, + { + "ma_chk_main_en", + NPPU_OAM_CFG_MA_CHK_MAIN_ENr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0028, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_ma_chk_main_en_reg, + NULL, + NULL, + }, + { + "chk_total_num1", + NPPU_OAM_CFG_CHK_TOTAL_NUM1r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x002c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_chk_total_num1_reg, + NULL, + NULL, + }, + { + "tx_stat_en", + NPPU_OAM_CFG_TX_STAT_ENr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0034, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_tx_stat_en_reg, + NULL, + NULL, + }, + { + "rec_stat_en", + NPPU_OAM_CFG_REC_STAT_ENr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0038, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_rec_stat_en_reg, + NULL, + NULL, + }, + { + "stat_oam_rdy_mask", + NPPU_OAM_CFG_STAT_OAM_RDY_MASKr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x003c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_stat_oam_rdy_mask_reg, + NULL, + NULL, + }, + { + "session_grading0", + NPPU_OAM_CFG_SESSION_GRADING0r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0040, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_session_grading0_reg, + NULL, + NULL, + }, + { + "session_grading1", + NPPU_OAM_CFG_SESSION_GRADING1r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0044, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_session_grading1_reg, + NULL, + NULL, + }, + { + "session_grading2", + NPPU_OAM_CFG_SESSION_GRADING2r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0048, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_session_grading2_reg, + NULL, + NULL, + }, + { + "session_grading3", + NPPU_OAM_CFG_SESSION_GRADING3r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x004c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_session_grading3_reg, + NULL, + NULL, + }, + { + "bfd_chk_haddr", + NPPU_OAM_CFG_BFD_CHK_HADDRr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0050, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_bfd_chk_haddr_reg, + NULL, + NULL, + }, + { + "ethccm_chk_haddr", + NPPU_OAM_CFG_ETHCCM_CHK_HADDRr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0054, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_ethccm_chk_haddr_reg, + NULL, + NULL, + }, + { + "tpbfd_chk_haddr", + NPPU_OAM_CFG_TPBFD_CHK_HADDRr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0058, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_tpbfd_chk_haddr_reg, + NULL, + NULL, + }, + { + "tpoam_ccm_chk_haddr", + NPPU_OAM_CFG_TPOAM_CCM_CHK_HADDRr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x005c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_tpoam_ccm_chk_haddr_reg, + NULL, + NULL, + }, + { + "bfd_tx_haddr", + NPPU_OAM_CFG_BFD_TX_HADDRr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0060, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_bfd_tx_haddr_reg, + NULL, + NULL, + }, + { + "ethccm_tx_haddr", + NPPU_OAM_CFG_ETHCCM_TX_HADDRr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0064, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_ethccm_tx_haddr_reg, + NULL, + NULL, + }, + { + "tpbfd_tx_haddr", + NPPU_OAM_CFG_TPBFD_TX_HADDRr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0068, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_tpbfd_tx_haddr_reg, + NULL, + NULL, + }, + { + "tpoam_ccm_tx_haddr", + NPPU_OAM_CFG_TPOAM_CCM_TX_HADDRr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x006c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_tpoam_ccm_tx_haddr_reg, + NULL, + NULL, + }, + { + "ethccm_ma_chk_haddr", + NPPU_OAM_CFG_ETHCCM_MA_CHK_HADDRr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0070, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_ethccm_ma_chk_haddr_reg, + NULL, + NULL, + }, + { + "tpccm_ma_chk_haddr", + NPPU_OAM_CFG_TPCCM_MA_CHK_HADDRr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0074, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_tpccm_ma_chk_haddr_reg, + NULL, + NULL, + }, + { + "groupnum_ram_clr", + NPPU_OAM_CFG_GROUPNUM_RAM_CLRr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0078, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_groupnum_ram_clr_reg, + NULL, + NULL, + }, + { + "index_ram0_clr", + NPPU_OAM_CFG_INDEX_RAM0_CLRr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x007c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_index_ram0_clr_reg, + NULL, + NULL, + }, + { + "index_ram1_clr", + NPPU_OAM_CFG_INDEX_RAM1_CLRr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0080, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_index_ram1_clr_reg, + NULL, + NULL, + }, + { + "rmep_ram_clr", + NPPU_OAM_CFG_RMEP_RAM_CLRr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0084, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_rmep_ram_clr_reg, + NULL, + NULL, + }, + { + "ma_ram_clr", + NPPU_OAM_CFG_MA_RAM_CLRr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0088, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_ma_ram_clr_reg, + NULL, + NULL, + }, + { + "ram_init_done", + NPPU_OAM_CFG_RAM_INIT_DONEr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x008c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_ram_init_done_reg, + NULL, + NULL, + }, + { + "rec_bfd_debug_en", + NPPU_OAM_CFG_REC_BFD_DEBUG_ENr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0090, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_rec_bfd_debug_en_reg, + NULL, + NULL, + }, + { + "oam_session_int", + NPPU_OAM_CFG_OAM_SESSION_INTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0098, + (32/8), + 0, + 0, + 0, + 0, + 6, + g_nppu_oam_cfg_oam_session_int_reg, + NULL, + NULL, + }, + { + "pon_int", + NPPU_OAM_CFG_PON_INTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x009c, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_nppu_oam_cfg_pon_int_reg, + NULL, + NULL, + }, + { + "oam_int_clr", + NPPU_OAM_CFG_OAM_INT_CLRr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x00a0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_oam_int_clr_reg, + NULL, + NULL, + }, + { + "type_int_clr0", + NPPU_OAM_CFG_TYPE_INT_CLR0r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x00a4, + (32/8), + 0, + 0, + 0, + 0, + 6, + g_nppu_oam_cfg_type_int_clr0_reg, + NULL, + NULL, + }, + { + "type_int_clr1", + NPPU_OAM_CFG_TYPE_INT_CLR1r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x00a8, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_nppu_oam_cfg_type_int_clr1_reg, + NULL, + NULL, + }, + { + "interrupt_mask", + NPPU_OAM_CFG_INTERRUPT_MASKr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x00ac, + (32/8), + 0, + 0, + 0, + 0, + 8, + g_nppu_oam_cfg_interrupt_mask_reg, + NULL, + NULL, + }, + { + "int0_index", + NPPU_OAM_CFG_INT0_INDEXr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x00b0, + (32/8), + 0, + 3 + 1, + 0, + 4, + 1, + g_nppu_oam_cfg_int0_index_reg, + NULL, + NULL, + }, + { + "int1_index", + NPPU_OAM_CFG_INT1_INDEXr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x00c0, + (32/8), + 0, + 3 + 1, + 0, + 4, + 1, + g_nppu_oam_cfg_int1_index_reg, + NULL, + NULL, + }, + { + "int0_index_region", + NPPU_OAM_CFG_INT0_INDEX_REGIONr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x00d0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_int0_index_region_reg, + NULL, + NULL, + }, + { + "int1_index_region", + NPPU_OAM_CFG_INT1_INDEX_REGIONr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x00d4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_int1_index_region_reg, + NULL, + NULL, + }, + { + "bdiinfo_fwft_fifo_th", + NPPU_OAM_CFG_BDIINFO_FWFT_FIFO_THr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x00d8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_bdiinfo_fwft_fifo_th_reg, + NULL, + NULL, + }, + { + "recsec_fwft_fifo_th", + NPPU_OAM_CFG_RECSEC_FWFT_FIFO_THr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x00dc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_recsec_fwft_fifo_th_reg, + NULL, + NULL, + }, + { + "timing_chk_info0_fwft_fifo_th", + NPPU_OAM_CFG_TIMING_CHK_INFO0_FWFT_FIFO_THr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x00e0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_timing_chk_info0_fwft_fifo_th_reg, + NULL, + NULL, + }, + { + "recma_fwft_fifo_th", + NPPU_OAM_CFG_RECMA_FWFT_FIFO_THr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x00e4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_recma_fwft_fifo_th_reg, + NULL, + NULL, + }, + { + "timing_chk_info1_fwft_fifo_th", + NPPU_OAM_CFG_TIMING_CHK_INFO1_FWFT_FIFO_THr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x00e8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_timing_chk_info1_fwft_fifo_th_reg, + NULL, + NULL, + }, + { + "oam_txinst_fifo_th", + NPPU_OAM_CFG_OAM_TXINST_FIFO_THr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x00ec, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_oam_txinst_fifo_th_reg, + NULL, + NULL, + }, + { + "oam_rdinfo_fwft_fifo_th", + NPPU_OAM_CFG_OAM_RDINFO_FWFT_FIFO_THr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x00f0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_oam_rdinfo_fwft_fifo_th_reg, + NULL, + NULL, + }, + { + "lm_cnt_fwft_fifo_th", + NPPU_OAM_CFG_LM_CNT_FWFT_FIFO_THr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x00f4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_lm_cnt_fwft_fifo_th_reg, + NULL, + NULL, + }, + { + "oam_pkt_fifo_th", + NPPU_OAM_CFG_OAM_PKT_FIFO_THr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x00f8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_oam_pkt_fifo_th_reg, + NULL, + NULL, + }, + { + "reclm_stat_fifo_th", + NPPU_OAM_CFG_RECLM_STAT_FIFO_THr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x00fc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_reclm_stat_fifo_th_reg, + NULL, + NULL, + }, + { + "txlm_stat_fifo_th", + NPPU_OAM_CFG_TXLM_STAT_FIFO_THr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x00100, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_txlm_stat_fifo_th_reg, + NULL, + NULL, + }, + { + "oam_chk_fwft_fifo_th", + NPPU_OAM_CFG_OAM_CHK_FWFT_FIFO_THr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0104, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_oam_chk_fwft_fifo_th_reg, + NULL, + NULL, + }, + { + "txoam_stat_fifo_th", + NPPU_OAM_CFG_TXOAM_STAT_FIFO_THr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0108, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_txoam_stat_fifo_th_reg, + NULL, + NULL, + }, + { + "recoam_stat_fifo_th", + NPPU_OAM_CFG_RECOAM_STAT_FIFO_THr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x010c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_recoam_stat_fifo_th_reg, + NULL, + NULL, + }, + { + "txpkt_data_fwft_fifo_th", + NPPU_OAM_CFG_TXPKT_DATA_FWFT_FIFO_THr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0110, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_txpkt_data_fwft_fifo_th_reg, + NULL, + NULL, + }, + { + "tstpkt_fwft_fifo_th", + NPPU_OAM_CFG_TSTPKT_FWFT_FIFO_THr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0114, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_tstpkt_fwft_fifo_th_reg, + NULL, + NULL, + }, + { + "tst_txinst_fwft_fifo_th", + NPPU_OAM_CFG_TST_TXINST_FWFT_FIFO_THr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0118, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_tst_txinst_fwft_fifo_th_reg, + NULL, + NULL, + }, + { + "tstrx_main_en", + NPPU_OAM_CFG_TSTRX_MAIN_ENr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x011c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_tstrx_main_en_reg, + NULL, + NULL, + }, + { + "tsttx_cfg_para_tbl2", + NPPU_OAM_CFG_TSTTX_CFG_PARA_TBL2r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0120, + (32/8), + 0, + 9 + 1, + 0, + 12, + 8, + g_nppu_oam_cfg_tsttx_cfg_para_tbl2_reg, + NULL, + NULL, + }, + { + "tsttx_cfg_para_tbl1", + NPPU_OAM_CFG_TSTTX_CFG_PARA_TBL1r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0124, + (32/8), + 0, + 9 + 1, + 0, + 12, + 1, + g_nppu_oam_cfg_tsttx_cfg_para_tbl1_reg, + NULL, + NULL, + }, + { + "tsttx_cfg_para_tbl0", + NPPU_OAM_CFG_TSTTX_CFG_PARA_TBL0r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0128, + (32/8), + 0, + 9 + 1, + 0, + 12, + 3, + g_nppu_oam_cfg_tsttx_cfg_para_tbl0_reg, + NULL, + NULL, + }, + { + "tstrx_cfg_para", + NPPU_OAM_CFG_TSTRX_CFG_PARAr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0198, + (32/8), + 0, + 0x9 + 1, + 0, + 4, + 2, + g_nppu_oam_cfg_tstrx_cfg_para_reg, + NULL, + NULL, + }, + { + "fifo_status_int_en_0", + NPPU_OAM_CFG_FIFO_STATUS_INT_EN_0r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x01c0, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_nppu_oam_cfg_fifo_status_int_en_0_reg, + NULL, + NULL, + }, + { + "fifo_status_int_en_1", + NPPU_OAM_CFG_FIFO_STATUS_INT_EN_1r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x01c4, + (32/8), + 0, + 0, + 0, + 0, + 10, + g_nppu_oam_cfg_fifo_status_int_en_1_reg, + NULL, + NULL, + }, + { + "fifo_status_int_mask_0", + NPPU_OAM_CFG_FIFO_STATUS_INT_MASK_0r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x01c8, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_nppu_oam_cfg_fifo_status_int_mask_0_reg, + NULL, + NULL, + }, + { + "fifo_status_int_mask_1", + NPPU_OAM_CFG_FIFO_STATUS_INT_MASK_1r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x01cc, + (32/8), + 0, + 0, + 0, + 0, + 10, + g_nppu_oam_cfg_fifo_status_int_mask_1_reg, + NULL, + NULL, + }, + { + "fifo_status_int_status", + NPPU_OAM_CFG_FIFO_STATUS_INT_STATUSr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x01d0, + (32/8), + 0, + 39 + 1, + 0, + 4, + 1, + g_nppu_oam_cfg_fifo_status_int_status_reg, + NULL, + NULL, + }, + { + "main_frequency", + NPPU_OAM_CFG_MAIN_FREQUENCYr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0270, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_main_frequency_reg, + NULL, + NULL, + }, + { + "oam_cfg_type", + NPPU_OAM_CFG_OAM_CFG_TYPEr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0274, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_oam_cfg_type_reg, + NULL, + NULL, + }, + { + "fst_swch_eth_head0", + NPPU_OAM_CFG_FST_SWCH_ETH_HEAD0r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0278, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_fst_swch_eth_head0_reg, + NULL, + NULL, + }, + { + "fst_swch_eth_head1", + NPPU_OAM_CFG_FST_SWCH_ETH_HEAD1r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x027c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_fst_swch_eth_head1_reg, + NULL, + NULL, + }, + { + "fst_swch_eth_head2", + NPPU_OAM_CFG_FST_SWCH_ETH_HEAD2r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0280, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_fst_swch_eth_head2_reg, + NULL, + NULL, + }, + { + "fst_swch_eth_head3", + NPPU_OAM_CFG_FST_SWCH_ETH_HEAD3r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0284, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_fst_swch_eth_head3_reg, + NULL, + NULL, + }, + { + "oam_fs_txinst_fifo_th", + NPPU_OAM_CFG_OAM_FS_TXINST_FIFO_THr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0288, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_oam_fs_txinst_fifo_th_reg, + NULL, + NULL, + }, + { + "oam_ma_fs_txinst_fifo_th", + NPPU_OAM_CFG_OAM_MA_FS_TXINST_FIFO_THr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x028c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_oam_ma_fs_txinst_fifo_th_reg, + NULL, + NULL, + }, + { + "pon_int_ram_clr", + NPPU_OAM_CFG_PON_INT_RAM_CLRr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0290, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_pon_int_ram_clr_reg, + NULL, + NULL, + }, + { + "pon_p_int_index", + NPPU_OAM_CFG_PON_P_INT_INDEXr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0294, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_pon_p_int_index_reg, + NULL, + NULL, + }, + { + "pon_protect_pkt_fifo_th", + NPPU_OAM_CFG_PON_PROTECT_PKT_FIFO_THr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0298, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_pon_protect_pkt_fifo_th_reg, + NULL, + NULL, + }, + { + "pon_laser_off_en", + NPPU_OAM_CFG_PON_LASER_OFF_ENr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x029c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_pon_laser_off_en_reg, + NULL, + NULL, + }, + { + "pon_prtct_pkt_tx_en", + NPPU_OAM_CFG_PON_PRTCT_PKT_TX_ENr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02a0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_pon_prtct_pkt_tx_en_reg, + NULL, + NULL, + }, + { + "cfg_pon_master", + NPPU_OAM_CFG_CFG_PON_MASTERr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02a4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_cfg_pon_master_reg, + NULL, + NULL, + }, + { + "level_mode", + NPPU_OAM_CFG_LEVEL_MODEr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02a8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_level_mode_reg, + NULL, + NULL, + }, + { + "interrupt_en", + NPPU_OAM_CFG_INTERRUPT_ENr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02ac, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_interrupt_en_reg, + NULL, + NULL, + }, + { + "pon_laser_on_en", + NPPU_OAM_CFG_PON_LASER_ON_ENr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02b0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_pon_laser_on_en_reg, + NULL, + NULL, + }, + { + "ti_pon_sd", + NPPU_OAM_CFG_TI_PON_SDr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02b4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_ti_pon_sd_reg, + NULL, + NULL, + }, + { + "ti_pon_los", + NPPU_OAM_CFG_TI_PON_LOSr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02b8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_ti_pon_los_reg, + NULL, + NULL, + }, + { + "ind_dat4", + NPPU_OAM_CFG_IND_DAT4r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02bc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_ind_dat4_reg, + NULL, + NULL, + }, + { + "ind_dat5", + NPPU_OAM_CFG_IND_DAT5r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02c0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_ind_dat5_reg, + NULL, + NULL, + }, + { + "ind_dat6", + NPPU_OAM_CFG_IND_DAT6r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02c4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_ind_dat6_reg, + NULL, + NULL, + }, + { + "ind_dat7", + NPPU_OAM_CFG_IND_DAT7r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02c8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_ind_dat7_reg, + NULL, + NULL, + }, + { + "ind_dat8", + NPPU_OAM_CFG_IND_DAT8r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02cc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_ind_dat8_reg, + NULL, + NULL, + }, + { + "ind_dat9", + NPPU_OAM_CFG_IND_DAT9r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02d0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_ind_dat9_reg, + NULL, + NULL, + }, + { + "ind_dat10", + NPPU_OAM_CFG_IND_DAT10r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02d4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_ind_dat10_reg, + NULL, + NULL, + }, + { + "ind_dat11", + NPPU_OAM_CFG_IND_DAT11r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02d8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_ind_dat11_reg, + NULL, + NULL, + }, + { + "ind_dat12", + NPPU_OAM_CFG_IND_DAT12r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02dc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_ind_dat12_reg, + NULL, + NULL, + }, + { + "ind_dat13", + NPPU_OAM_CFG_IND_DAT13r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02e0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_ind_dat13_reg, + NULL, + NULL, + }, + { + "ind_dat14", + NPPU_OAM_CFG_IND_DAT14r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02e4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_ind_dat14_reg, + NULL, + NULL, + }, + { + "ind_dat15", + NPPU_OAM_CFG_IND_DAT15r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02e8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_ind_dat15_reg, + NULL, + NULL, + }, + { + "oam_2544_pkt_fifo_th", + NPPU_OAM_CFG_OAM_2544_PKT_FIFO_THr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02ec, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_oam_2544_pkt_fifo_th_reg, + NULL, + NULL, + }, + { + "txinfo_ram_clr", + NPPU_OAM_CFG_TXINFO_RAM_CLRr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02f0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_txinfo_ram_clr_reg, + NULL, + NULL, + }, + { + "txinfo_ram_init_done", + NPPU_OAM_CFG_TXINFO_RAM_INIT_DONEr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02f4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_txinfo_ram_init_done_reg, + NULL, + NULL, + }, + { + "fifo_status_int_status40", + NPPU_OAM_CFG_FIFO_STATUS_INT_STATUS40r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02f8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_fifo_status_int_status40_reg, + NULL, + NULL, + }, + { + "fifo_status_int_status41", + NPPU_OAM_CFG_FIFO_STATUS_INT_STATUS41r, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02fc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_fifo_status_int_status41_reg, + NULL, + NULL, + }, + { + "oam_2544_fun_en", + NPPU_OAM_CFG_OAM_2544_FUN_ENr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0300, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_oam_2544_fun_en_reg, + NULL, + NULL, + }, + { + "oam_2544_stat_clr", + NPPU_OAM_CFG_OAM_2544_STAT_CLRr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0304, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_oam_2544_stat_clr_reg, + NULL, + NULL, + }, + { + "txdis_default", + NPPU_OAM_CFG_TXDIS_DEFAULTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0308, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_txdis_default_reg, + NULL, + NULL, + }, + { + "txdis_default_en", + NPPU_OAM_CFG_TXDIS_DEFAULT_ENr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x030c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_txdis_default_en_reg, + NULL, + NULL, + }, + { + "tpbfd_firstchk_th", + NPPU_OAM_CFG_TPBFD_FIRSTCHK_THr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0310, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_tpbfd_firstchk_th_reg, + NULL, + NULL, + }, + { + "ethccm_firstchk_th", + NPPU_OAM_CFG_ETHCCM_FIRSTCHK_THr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0314, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_ethccm_firstchk_th_reg, + NULL, + NULL, + }, + { + "tpccm_firstchk_th", + NPPU_OAM_CFG_TPCCM_FIRSTCHK_THr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0318, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_cfg_tpccm_firstchk_th_reg, + NULL, + NULL, + }, + { + "txstat_req_cnt", + NPPU_OAM_STAT_TXSTAT_REQ_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0000, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_stat_txstat_req_cnt_reg, + NULL, + NULL, + }, + { + "chkstat_req_cnt", + NPPU_OAM_STAT_CHKSTAT_REQ_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0004, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_stat_chkstat_req_cnt_reg, + NULL, + NULL, + }, + { + "stat_oam_fc_cnt", + NPPU_OAM_STAT_STAT_OAM_FC_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0008, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_stat_stat_oam_fc_cnt_reg, + NULL, + NULL, + }, + { + "bfdseq_req_cnt", + NPPU_OAM_STAT_BFDSEQ_REQ_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x000c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_stat_bfdseq_req_cnt_reg, + NULL, + NULL, + }, + { + "lmcnt_req_cnt", + NPPU_OAM_STAT_LMCNT_REQ_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0010, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_stat_lmcnt_req_cnt_reg, + NULL, + NULL, + }, + { + "stat_oam_lm_rsp_cnt", + NPPU_OAM_STAT_STAT_OAM_LM_RSP_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0014, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_stat_stat_oam_lm_rsp_cnt_reg, + NULL, + NULL, + }, + { + "stat_oam_lm_fc_cnt", + NPPU_OAM_STAT_STAT_OAM_LM_FC_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0018, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_stat_stat_oam_lm_fc_cnt_reg, + NULL, + NULL, + }, + { + "se_req_cnt", + NPPU_OAM_STAT_SE_REQ_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x001c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_stat_se_req_cnt_reg, + NULL, + NULL, + }, + { + "se_rsp_cnt", + NPPU_OAM_STAT_SE_RSP_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0020, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_stat_se_rsp_cnt_reg, + NULL, + NULL, + }, + { + "se_oam_fc_cnt", + NPPU_OAM_STAT_SE_OAM_FC_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0024, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_stat_se_oam_fc_cnt_reg, + NULL, + NULL, + }, + { + "oam_se_fc_cnt", + NPPU_OAM_STAT_OAM_SE_FC_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0028, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_stat_oam_se_fc_cnt_reg, + NULL, + NULL, + }, + { + "oam_pktrx_sop_cnt", + NPPU_OAM_STAT_OAM_PKTRX_SOP_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x002c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_stat_oam_pktrx_sop_cnt_reg, + NULL, + NULL, + }, + { + "oam_pktrx_eop_cnt", + NPPU_OAM_STAT_OAM_PKTRX_EOP_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0030, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_stat_oam_pktrx_eop_cnt_reg, + NULL, + NULL, + }, + { + "pktrx_oam_fc_cnt", + NPPU_OAM_STAT_PKTRX_OAM_FC_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0034, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_stat_pktrx_oam_fc_cnt_reg, + NULL, + NULL, + }, + { + "pktrx_oam_tst_fc_cnt", + NPPU_OAM_STAT_PKTRX_OAM_TST_FC_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0038, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_stat_pktrx_oam_tst_fc_cnt_reg, + NULL, + NULL, + }, + { + "odma_oam_sop_cnt", + NPPU_OAM_STAT_ODMA_OAM_SOP_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x003c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_stat_odma_oam_sop_cnt_reg, + NULL, + NULL, + }, + { + "odma_oam_eop_cnt", + NPPU_OAM_STAT_ODMA_OAM_EOP_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0040, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_stat_odma_oam_eop_cnt_reg, + NULL, + NULL, + }, + { + "oam_odma_fc_cnt", + NPPU_OAM_STAT_OAM_ODMA_FC_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0044, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_stat_oam_odma_fc_cnt_reg, + NULL, + NULL, + }, + { + "rec_ma_pkt_illegal_cnt", + NPPU_OAM_STAT_REC_MA_PKT_ILLEGAL_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0048, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_stat_rec_ma_pkt_illegal_cnt_reg, + NULL, + NULL, + }, + { + "rec_rmep_pkt_illegal_cnt", + NPPU_OAM_STAT_REC_RMEP_PKT_ILLEGAL_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x004c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_stat_rec_rmep_pkt_illegal_cnt_reg, + NULL, + NULL, + }, + { + "rec_eth_ais_pkt_cnt", + NPPU_OAM_STAT_REC_ETH_AIS_PKT_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0050, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_stat_rec_eth_ais_pkt_cnt_reg, + NULL, + NULL, + }, + { + "rec_tp_ais_pkt_cnt", + NPPU_OAM_STAT_REC_TP_AIS_PKT_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0054, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_stat_rec_tp_ais_pkt_cnt_reg, + NULL, + NULL, + }, + { + "rec_tp_csf_pkt_cnt", + NPPU_OAM_STAT_REC_TP_CSF_PKT_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0058, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_stat_rec_tp_csf_pkt_cnt_reg, + NULL, + NULL, + }, + { + "rec_eth_level_defect_cnt", + NPPU_OAM_STAT_REC_ETH_LEVEL_DEFECT_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x005c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_stat_rec_eth_level_defect_cnt_reg, + NULL, + NULL, + }, + { + "rec_eth_megid_defect_cnt", + NPPU_OAM_STAT_REC_ETH_MEGID_DEFECT_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0060, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_stat_rec_eth_megid_defect_cnt_reg, + NULL, + NULL, + }, + { + "rec_eth_mepid_defect_cnt", + NPPU_OAM_STAT_REC_ETH_MEPID_DEFECT_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0064, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_stat_rec_eth_mepid_defect_cnt_reg, + NULL, + NULL, + }, + { + "rec_eth_interval_defect_cnt", + NPPU_OAM_STAT_REC_ETH_INTERVAL_DEFECT_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0068, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_stat_rec_eth_interval_defect_cnt_reg, + NULL, + NULL, + }, + { + "rec_sess_unenable_cnt", + NPPU_OAM_STAT_REC_SESS_UNENABLE_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x006c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_stat_rec_sess_unenable_cnt_reg, + NULL, + NULL, + }, + { + "oam_2544_rd_pkt_cnt", + NPPU_OAM_STAT_OAM_2544_RD_PKT_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0070, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_stat_oam_2544_rd_pkt_cnt_reg, + NULL, + NULL, + }, + { + "debug_cnt_clr", + NPPU_OAM_STAT_DEBUG_CNT_CLRr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0074, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_stat_debug_cnt_clr_reg, + NULL, + NULL, + }, + { + "oam_pktrx_catch_data", + NPPU_OAM_STAT_OAM_PKTRX_CATCH_DATAr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0078, + (32/8), + 0, + 0x1F + 1, + 0, + 4, + 1, + g_nppu_oam_stat_oam_pktrx_catch_data_reg, + NULL, + NULL, + }, + { + "odma_oam_catch_data", + NPPU_OAM_STAT_ODMA_OAM_CATCH_DATAr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x00f8, + (32/8), + 0, + 0x1F + 1, + 0, + 4, + 1, + g_nppu_oam_stat_odma_oam_catch_data_reg, + NULL, + NULL, + }, + { + "tst_session_tx_cnt", + NPPU_OAM_STAT_TST_SESSION_TX_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0178, + (32/8), + 0, + 0x9 + 1, + 0, + 4, + 1, + g_nppu_oam_stat_tst_session_tx_cnt_reg, + NULL, + NULL, + }, + { + "tst_session_rx_cnt", + NPPU_OAM_STAT_TST_SESSION_RX_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x01a0, + (32/8), + 0, + 0x9 + 1, + 0, + 4, + 1, + g_nppu_oam_stat_tst_session_rx_cnt_reg, + NULL, + NULL, + }, + { + "tstrx_lost_cnt", + NPPU_OAM_STAT_TSTRX_LOST_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x01c8, + (32/8), + 0, + 0x9 + 1, + 0, + 4, + 1, + g_nppu_oam_stat_tstrx_lost_cnt_reg, + NULL, + NULL, + }, + { + "bfdseq_wr_cnt", + NPPU_OAM_STAT_BFDSEQ_WR_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x01f0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_stat_bfdseq_wr_cnt_reg, + NULL, + NULL, + }, + { + "bfdtime_wr_cnt", + NPPU_OAM_STAT_BFDTIME_WR_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x01f4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_stat_bfdtime_wr_cnt_reg, + NULL, + NULL, + }, + { + "lmcnt_wr_cnt", + NPPU_OAM_STAT_LMCNT_WR_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x01f8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_stat_lmcnt_wr_cnt_reg, + NULL, + NULL, + }, + { + "oam_fs_pkt_cnt", + NPPU_OAM_STAT_OAM_FS_PKT_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x01fc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_stat_oam_fs_pkt_cnt_reg, + NULL, + NULL, + }, + { + "oam_ma_fs_pkt_cnt", + NPPU_OAM_STAT_OAM_MA_FS_PKT_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0200, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_stat_oam_ma_fs_pkt_cnt_reg, + NULL, + NULL, + }, + { + "rec_tp_level_defect_cnt", + NPPU_OAM_STAT_REC_TP_LEVEL_DEFECT_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0204, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_stat_rec_tp_level_defect_cnt_reg, + NULL, + NULL, + }, + { + "rec_tp_megid_defect_cnt", + NPPU_OAM_STAT_REC_TP_MEGID_DEFECT_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0208, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_stat_rec_tp_megid_defect_cnt_reg, + NULL, + NULL, + }, + { + "rec_tp_mepid_defect_cnt", + NPPU_OAM_STAT_REC_TP_MEPID_DEFECT_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x020c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_stat_rec_tp_mepid_defect_cnt_reg, + NULL, + NULL, + }, + { + "rec_tp_interval_defect_cnt", + NPPU_OAM_STAT_REC_TP_INTERVAL_DEFECT_CNTr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0210, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_stat_rec_tp_interval_defect_cnt_reg, + NULL, + NULL, + }, + { + "rd_reg_clear_mode", + NPPU_OAM_STAT_RD_REG_CLEAR_MODEr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0214, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_stat_rd_reg_clear_mode_reg, + NULL, + NULL, + }, + { + "rd_data_reg_clear_mode", + NPPU_OAM_STAT_RD_DATA_REG_CLEAR_MODEr, + NPPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0218, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_nppu_oam_stat_rd_data_reg_clear_mode_reg, + NULL, + NULL, + }, + { + "oam_int_status_ram_0", + NPPU_OAM_CFG_INDIR_OAM_INT_STATUS_RAM_0r, + NPPU, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x00000000, + (32/8), + 0, + 4095 + 1, + 0, + 1, + 7, + g_nppu_oam_cfg_indir_oam_int_status_ram_0_reg, + NULL, + NULL, + }, + { + "oam_int_status_ram1", + NPPU_OAM_CFG_INDIR_OAM_INT_STATUS_RAM1r, + NPPU, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x10000000, + (32/8), + 0, + 4095 + 1, + 0, + 1, + 12, + g_nppu_oam_cfg_indir_oam_int_status_ram1_reg, + NULL, + NULL, + }, + { + "tst_pkt_tx_para_ram", + NPPU_OAM_CFG_INDIR_TST_PKT_TX_PARA_RAMr, + NPPU, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x20000000, + (96/8), + 0, + 127 + 1, + 0, + 1, + 12, + g_nppu_oam_cfg_indir_tst_pkt_tx_para_ram_reg, + NULL, + NULL, + }, + { + "groupnumram", + NPPU_OAM_CFG_INDIR_GROUPNUMRAMr, + NPPU, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x30000000, + (32/8), + 0, + 4095 + 1, + 0, + 1, + 1, + g_nppu_oam_cfg_indir_groupnumram_reg, + NULL, + NULL, + }, + { + "oam_tx_tbl_ram", + NPPU_OAM_CFG_INDIR_OAM_TX_TBL_RAMr, + NPPU, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x40000000, + (64/8), + 0, + 4095 + 1, + 0, + 1, + 8, + g_nppu_oam_cfg_indir_oam_tx_tbl_ram_reg, + NULL, + NULL, + }, + { + "oam_chk_tbl_ram", + NPPU_OAM_CFG_INDIR_OAM_CHK_TBL_RAMr, + NPPU, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x50000000, + (64/8), + 0, + 4095 + 1, + 0, + 1, + 9, + g_nppu_oam_cfg_indir_oam_chk_tbl_ram_reg, + NULL, + NULL, + }, + { + "oam_ma_chk_tbl_ram", + NPPU_OAM_CFG_INDIR_OAM_MA_CHK_TBL_RAMr, + NPPU, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x60000000, + (160/8), + 0, + 4095 + 1, + 0, + 1, + 22, + g_nppu_oam_cfg_indir_oam_ma_chk_tbl_ram_reg, + NULL, + NULL, + }, + { + "oam_2544_tx_ram", + NPPU_OAM_CFG_INDIR_OAM_2544_TX_RAMr, + NPPU, + DPP_REG_FLAG_INDIRECT, + DPP_REG_UNI_ARRAY, + 0x90000000, + (64/8), + 0, + 127 + 1, + 0, + 1, + 5, + g_nppu_oam_cfg_indir_oam_2544_tx_ram_reg, + NULL, + NULL, + }, + { + "interrupt_en_r", + PPU_PPU_INTERRUPT_EN_Rr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x004, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_interrupt_en_r_reg, + NULL, + NULL, + }, + { + "mec_host_interrupt", + PPU_PPU_MEC_HOST_INTERRUPTr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x008, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_mec_host_interrupt_reg, + NULL, + NULL, + }, + { + "dbg_rtl_date", + PPU_PPU_DBG_RTL_DATEr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x014, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_dbg_rtl_date_reg, + NULL, + NULL, + }, + { + "dup_start_num_cfg", + PPU_PPU_DUP_START_NUM_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x02c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_dup_start_num_cfg_reg, + NULL, + NULL, + }, + { + "debug_data_write_complete", + PPU_PPU_DEBUG_DATA_WRITE_COMPLETEr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x030, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_debug_data_write_complete_reg, + NULL, + NULL, + }, + { + "uc_mc_wrr_cfg", + PPU_PPU_UC_MC_WRR_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x040, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_uc_mc_wrr_cfg_reg, + NULL, + NULL, + }, + { + "debug_pkt_send_en", + PPU_PPU_DEBUG_PKT_SEND_ENr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x044, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_debug_pkt_send_en_reg, + NULL, + NULL, + }, + { + "dup_tbl_ind_access_done", + PPU_PPU_DUP_TBL_IND_ACCESS_DONEr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x04c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_dup_tbl_ind_access_done_reg, + NULL, + NULL, + }, + { + "isu_ppu_demux_fifo_interrupt_mask", + PPU_PPU_ISU_PPU_DEMUX_FIFO_INTERRUPT_MASKr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x080, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_ppu_ppu_isu_ppu_demux_fifo_interrupt_mask_reg, + NULL, + NULL, + }, + { + "ppu_multicast_fifo_interrupt_mask", + PPU_PPU_PPU_MULTICAST_FIFO_INTERRUPT_MASKr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x084, + (32/8), + 0, + 0, + 0, + 0, + 20, + g_ppu_ppu_ppu_multicast_fifo_interrupt_mask_reg, + NULL, + NULL, + }, + { + "ppu_in_schedule_fifo_interrupt_mask", + PPU_PPU_PPU_IN_SCHEDULE_FIFO_INTERRUPT_MASKr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x088, + (32/8), + 0, + 0, + 0, + 0, + 6, + g_ppu_ppu_ppu_in_schedule_fifo_interrupt_mask_reg, + NULL, + NULL, + }, + { + "ppu_mf_out_fifo_interrupt_mask", + PPU_PPU_PPU_MF_OUT_FIFO_INTERRUPT_MASKr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x08c, + (32/8), + 0, + 0, + 0, + 0, + 12, + g_ppu_ppu_ppu_mf_out_fifo_interrupt_mask_reg, + NULL, + NULL, + }, + { + "pbu_mcode_pf_req_schedule_fifo_interrupt_mask", + PPU_PPU_PBU_MCODE_PF_REQ_SCHEDULE_FIFO_INTERRUPT_MASKr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x090, + (32/8), + 0, + 0, + 0, + 0, + 12, + g_ppu_ppu_pbu_mcode_pf_req_schedule_fifo_interrupt_mask_reg, + NULL, + NULL, + }, + { + "pbu_mcode_pf_rsp_schedule_fifo_interrupt_mask", + PPU_PPU_PBU_MCODE_PF_RSP_SCHEDULE_FIFO_INTERRUPT_MASKr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x094, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_ppu_ppu_pbu_mcode_pf_rsp_schedule_fifo_interrupt_mask_reg, + NULL, + NULL, + }, + { + "ppu_mccnt_fifo_interrupt_mask", + PPU_PPU_PPU_MCCNT_FIFO_INTERRUPT_MASKr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x098, + (32/8), + 0, + 0, + 0, + 0, + 6, + g_ppu_ppu_ppu_mccnt_fifo_interrupt_mask_reg, + NULL, + NULL, + }, + { + "coprocessor_fifo_interrupt_mask_l", + PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_MASK_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x09c, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_ppu_ppu_coprocessor_fifo_interrupt_mask_l_reg, + NULL, + NULL, + }, + { + "coprocessor_fifo_interrupt_mask_m", + PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_MASK_Mr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x0a0, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_ppu_ppu_coprocessor_fifo_interrupt_mask_m_reg, + NULL, + NULL, + }, + { + "coprocessor_fifo_interrupt_mask_h", + PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_MASK_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa4, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_ppu_ppu_coprocessor_fifo_interrupt_mask_h_reg, + NULL, + NULL, + }, + { + "ppu_ram_check_err_mask", + PPU_PPU_PPU_RAM_CHECK_ERR_MASKr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x0a8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_ram_check_err_mask_reg, + NULL, + NULL, + }, + { + "instrmem_fifo_interrupt_mask", + PPU_PPU_INSTRMEM_FIFO_INTERRUPT_MASKr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x0ac, + (32/8), + 0, + 0, + 0, + 0, + 12, + g_ppu_ppu_instrmem_fifo_interrupt_mask_reg, + NULL, + NULL, + }, + { + "isu_ppu_demux_fifo_interrupt_sta", + PPU_PPU_ISU_PPU_DEMUX_FIFO_INTERRUPT_STAr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xc0, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_ppu_ppu_isu_ppu_demux_fifo_interrupt_sta_reg, + NULL, + NULL, + }, + { + "ppu_multicast_fifo_interrupt_sta", + PPU_PPU_PPU_MULTICAST_FIFO_INTERRUPT_STAr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x0c4, + (32/8), + 0, + 0, + 0, + 0, + 20, + g_ppu_ppu_ppu_multicast_fifo_interrupt_sta_reg, + NULL, + NULL, + }, + { + "ppu_in_schedule_fifo_interrupt_sta", + PPU_PPU_PPU_IN_SCHEDULE_FIFO_INTERRUPT_STAr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x0c8, + (32/8), + 0, + 0, + 0, + 0, + 6, + g_ppu_ppu_ppu_in_schedule_fifo_interrupt_sta_reg, + NULL, + NULL, + }, + { + "ppu_mf_out_fifo_interrupt_sta", + PPU_PPU_PPU_MF_OUT_FIFO_INTERRUPT_STAr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xcc, + (32/8), + 0, + 0, + 0, + 0, + 12, + g_ppu_ppu_ppu_mf_out_fifo_interrupt_sta_reg, + NULL, + NULL, + }, + { + "pbu_mcode_pf_req_schedule_fifo_interrupt_sta", + PPU_PPU_PBU_MCODE_PF_REQ_SCHEDULE_FIFO_INTERRUPT_STAr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x0d0, + (32/8), + 0, + 0, + 0, + 0, + 12, + g_ppu_ppu_pbu_mcode_pf_req_schedule_fifo_interrupt_sta_reg, + NULL, + NULL, + }, + { + "pbu_mcode_pf_rsp_schedule_fifo_interrupt_sta", + PPU_PPU_PBU_MCODE_PF_RSP_SCHEDULE_FIFO_INTERRUPT_STAr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x0d4, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_ppu_ppu_pbu_mcode_pf_rsp_schedule_fifo_interrupt_sta_reg, + NULL, + NULL, + }, + { + "ppu_mccnt_fifo_interrupt_sta", + PPU_PPU_PPU_MCCNT_FIFO_INTERRUPT_STAr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x0d8, + (32/8), + 0, + 0, + 0, + 0, + 6, + g_ppu_ppu_ppu_mccnt_fifo_interrupt_sta_reg, + NULL, + NULL, + }, + { + "coprocessor_fifo_interrupt_sta_l", + PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_STA_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x0dc, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_ppu_ppu_coprocessor_fifo_interrupt_sta_l_reg, + NULL, + NULL, + }, + { + "coprocessor_fifo_interrupt_sta_m", + PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_STA_Mr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x0e0, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_ppu_ppu_coprocessor_fifo_interrupt_sta_m_reg, + NULL, + NULL, + }, + { + "coprocessor_fifo_interrupt_sta_h", + PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_STA_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xe4, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_ppu_ppu_coprocessor_fifo_interrupt_sta_h_reg, + NULL, + NULL, + }, + { + "instrmem_fifo_interrupt_sta", + PPU_PPU_INSTRMEM_FIFO_INTERRUPT_STAr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x0e8, + (32/8), + 0, + 0, + 0, + 0, + 8, + g_ppu_ppu_instrmem_fifo_interrupt_sta_reg, + NULL, + NULL, + }, + { + "ppu_ram_check_ecc_err_flag_1", + PPU_PPU_PPU_RAM_CHECK_ECC_ERR_FLAG_1r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x0f0, + (32/8), + 0, + 0, + 0, + 0, + 26, + g_ppu_ppu_ppu_ram_check_ecc_err_flag_1_reg, + NULL, + NULL, + }, + { + "isu_ppu_demux_fifo_interrupt_flag", + PPU_PPU_ISU_PPU_DEMUX_FIFO_INTERRUPT_FLAGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x100, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_ppu_ppu_isu_ppu_demux_fifo_interrupt_flag_reg, + NULL, + NULL, + }, + { + "ppu_multicast_fifo_interrupt_flag", + PPU_PPU_PPU_MULTICAST_FIFO_INTERRUPT_FLAGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x104, + (32/8), + 0, + 0, + 0, + 0, + 20, + g_ppu_ppu_ppu_multicast_fifo_interrupt_flag_reg, + NULL, + NULL, + }, + { + "ppu_in_schedule_fifo_interrupt_flag", + PPU_PPU_PPU_IN_SCHEDULE_FIFO_INTERRUPT_FLAGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x108, + (32/8), + 0, + 0, + 0, + 0, + 6, + g_ppu_ppu_ppu_in_schedule_fifo_interrupt_flag_reg, + NULL, + NULL, + }, + { + "ppu_mf_out_fifo_interrupt_flag", + PPU_PPU_PPU_MF_OUT_FIFO_INTERRUPT_FLAGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x10c, + (32/8), + 0, + 0, + 0, + 0, + 12, + g_ppu_ppu_ppu_mf_out_fifo_interrupt_flag_reg, + NULL, + NULL, + }, + { + "pbu_mcode_pf_req_schedule_fifo_interrupt_flag", + PPU_PPU_PBU_MCODE_PF_REQ_SCHEDULE_FIFO_INTERRUPT_FLAGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x110, + (32/8), + 0, + 0, + 0, + 0, + 12, + g_ppu_ppu_pbu_mcode_pf_req_schedule_fifo_interrupt_flag_reg, + NULL, + NULL, + }, + { + "pbu_mcode_pf_rsp_schedule_fifo_interrupt_flag", + PPU_PPU_PBU_MCODE_PF_RSP_SCHEDULE_FIFO_INTERRUPT_FLAGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x114, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_ppu_ppu_pbu_mcode_pf_rsp_schedule_fifo_interrupt_flag_reg, + NULL, + NULL, + }, + { + "ppu_mccnt_fifo_interrupt_flag", + PPU_PPU_PPU_MCCNT_FIFO_INTERRUPT_FLAGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x118, + (32/8), + 0, + 0, + 0, + 0, + 6, + g_ppu_ppu_ppu_mccnt_fifo_interrupt_flag_reg, + NULL, + NULL, + }, + { + "coprocessor_fifo_interrupt_flag_l", + PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_FLAG_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x11c, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_ppu_ppu_coprocessor_fifo_interrupt_flag_l_reg, + NULL, + NULL, + }, + { + "coprocessor_fifo_interrupt_flag_m", + PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_FLAG_Mr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x120, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_ppu_ppu_coprocessor_fifo_interrupt_flag_m_reg, + NULL, + NULL, + }, + { + "coprocessor_fifo_interrupt_flag_h", + PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_FLAG_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x124, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_ppu_ppu_coprocessor_fifo_interrupt_flag_h_reg, + NULL, + NULL, + }, + { + "instrmem_fifo_interrupt_flag", + PPU_PPU_INSTRMEM_FIFO_INTERRUPT_FLAGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x128, + (32/8), + 0, + 0, + 0, + 0, + 12, + g_ppu_ppu_instrmem_fifo_interrupt_flag_reg, + NULL, + NULL, + }, + { + "instrmem_ram_int_out", + PPU_PPU_INSTRMEM_RAM_INT_OUTr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x140, + (32/8), + 0, + 0, + 0, + 0, + 12, + g_ppu_ppu_instrmem_ram_int_out_reg, + NULL, + NULL, + }, + { + "instrmem_ram_int_mask", + PPU_PPU_INSTRMEM_RAM_INT_MASKr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x144, + (32/8), + 0, + 0, + 0, + 0, + 12, + g_ppu_ppu_instrmem_ram_int_mask_reg, + NULL, + NULL, + }, + { + "instrmem_ram_int_stat", + PPU_PPU_INSTRMEM_RAM_INT_STATr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x148, + (32/8), + 0, + 0, + 0, + 0, + 12, + g_ppu_ppu_instrmem_ram_int_stat_reg, + NULL, + NULL, + }, + { + "instrmem_ram_int_flag", + PPU_PPU_INSTRMEM_RAM_INT_FLAGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x14c, + (32/8), + 0, + 0, + 0, + 0, + 12, + g_ppu_ppu_instrmem_ram_int_flag_reg, + NULL, + NULL, + }, + { + "ppu_count_cfg", + PPU_PPU_PPU_COUNT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x158, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_ppu_ppu_ppu_count_cfg_reg, + NULL, + NULL, + }, + { + "ppu_statics_cfg", + PPU_PPU_PPU_STATICS_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x15c, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_ppu_ppu_ppu_statics_cfg_reg, + NULL, + NULL, + }, + { + "ppu_statics_wb_cfg", + PPU_PPU_PPU_STATICS_WB_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x160, + (32/8), + 0, + 0, + 0, + 0, + 6, + g_ppu_ppu_ppu_statics_wb_cfg_reg, + NULL, + NULL, + }, + { + "wr_table_self_rsp_en_cfg", + PPU_PPU_WR_TABLE_SELF_RSP_EN_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x164, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_wr_table_self_rsp_en_cfg_reg, + NULL, + NULL, + }, + { + "ppu_random_arbiter_8to1_cfg", + PPU_PPU_PPU_RANDOM_ARBITER_8TO1_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x168, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_random_arbiter_8to1_cfg_reg, + NULL, + NULL, + }, + { + "ppu_reorder_bypass_flow_num_cfg", + PPU_PPU_PPU_REORDER_BYPASS_FLOW_NUM_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x16c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_reorder_bypass_flow_num_cfg_reg, + NULL, + NULL, + }, + { + "cos_meter_cfg_h", + PPU_PPU_COS_METER_CFG_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x170, + (32/8), + 0, + 7 + 1, + 0, + 8, + 5, + g_ppu_ppu_cos_meter_cfg_h_reg, + NULL, + NULL, + }, + { + "cos_meter_cfg_l", + PPU_PPU_COS_METER_CFG_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x174, + (32/8), + 0, + 7 + 1, + 0, + 8, + 3, + g_ppu_ppu_cos_meter_cfg_l_reg, + NULL, + NULL, + }, + { + "instrmem_rdy", + PPU_PPU_INSTRMEM_RDYr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x1c0, + (32/8), + 0, + 2 + 1, + 0, + 4, + 1, + g_ppu_ppu_instrmem_rdy_reg, + NULL, + NULL, + }, + { + "instrmem_addr", + PPU_PPU_INSTRMEM_ADDRr, + PPU, + DPP_REG_FLAG_WO | DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x1d0, + (32/8), + 0, + 2 + 1, + 0, + 4, + 2, + g_ppu_ppu_instrmem_addr_reg, + NULL, + NULL, + }, + { + "instrmem_ind_access_done", + PPU_PPU_INSTRMEM_IND_ACCESS_DONEr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x1e0, + (32/8), + 0, + 2 + 1, + 0, + 4, + 1, + g_ppu_ppu_instrmem_ind_access_done_reg, + NULL, + NULL, + }, + { + "instrmem_instr0_data_l", + PPU_PPU_INSTRMEM_INSTR0_DATA_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x1f0, + (32/8), + 0, + 2 + 1, + 0, + 4, + 1, + g_ppu_ppu_instrmem_instr0_data_l_reg, + NULL, + NULL, + }, + { + "instrmem_instr0_data_h", + PPU_PPU_INSTRMEM_INSTR0_DATA_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x200, + (32/8), + 0, + 2 + 1, + 0, + 4, + 1, + g_ppu_ppu_instrmem_instr0_data_h_reg, + NULL, + NULL, + }, + { + "instrmem_instr1_data_l", + PPU_PPU_INSTRMEM_INSTR1_DATA_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x210, + (32/8), + 0, + 2 + 1, + 0, + 4, + 1, + g_ppu_ppu_instrmem_instr1_data_l_reg, + NULL, + NULL, + }, + { + "instrmem_instr1_data_h", + PPU_PPU_INSTRMEM_INSTR1_DATA_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x220, + (32/8), + 0, + 2 + 1, + 0, + 4, + 1, + g_ppu_ppu_instrmem_instr1_data_h_reg, + NULL, + NULL, + }, + { + "instrmem_instr2_data_l", + PPU_PPU_INSTRMEM_INSTR2_DATA_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x230, + (32/8), + 0, + 2 + 1, + 0, + 4, + 1, + g_ppu_ppu_instrmem_instr2_data_l_reg, + NULL, + NULL, + }, + { + "instrmem_instr2_data_h", + PPU_PPU_INSTRMEM_INSTR2_DATA_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x240, + (32/8), + 0, + 2 + 1, + 0, + 4, + 1, + g_ppu_ppu_instrmem_instr2_data_h_reg, + NULL, + NULL, + }, + { + "instrmem_instr3_data_l", + PPU_PPU_INSTRMEM_INSTR3_DATA_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x250, + (32/8), + 0, + 2 + 1, + 0, + 4, + 1, + g_ppu_ppu_instrmem_instr3_data_l_reg, + NULL, + NULL, + }, + { + "instrmem_instr3_data_h", + PPU_PPU_INSTRMEM_INSTR3_DATA_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x260, + (32/8), + 0, + 2 + 1, + 0, + 4, + 1, + g_ppu_ppu_instrmem_instr3_data_h_reg, + NULL, + NULL, + }, + { + "instrmem_read_instr0_data_l", + PPU_PPU_INSTRMEM_READ_INSTR0_DATA_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x270, + (32/8), + 0, + 2 + 1, + 0, + 4, + 1, + g_ppu_ppu_instrmem_read_instr0_data_l_reg, + NULL, + NULL, + }, + { + "instrmem_read_instr0_data_h", + PPU_PPU_INSTRMEM_READ_INSTR0_DATA_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x280, + (32/8), + 0, + 2 + 1, + 0, + 4, + 1, + g_ppu_ppu_instrmem_read_instr0_data_h_reg, + NULL, + NULL, + }, + { + "instrmem_read_instr1_data_l", + PPU_PPU_INSTRMEM_READ_INSTR1_DATA_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x290, + (32/8), + 0, + 2 + 1, + 0, + 4, + 1, + g_ppu_ppu_instrmem_read_instr1_data_l_reg, + NULL, + NULL, + }, + { + "instrmem_read_instr1_data_h", + PPU_PPU_INSTRMEM_READ_INSTR1_DATA_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x2a0, + (32/8), + 0, + 2 + 1, + 0, + 4, + 1, + g_ppu_ppu_instrmem_read_instr1_data_h_reg, + NULL, + NULL, + }, + { + "instrmem_read_instr2_data_l", + PPU_PPU_INSTRMEM_READ_INSTR2_DATA_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x2b0, + (32/8), + 0, + 2 + 1, + 0, + 4, + 1, + g_ppu_ppu_instrmem_read_instr2_data_l_reg, + NULL, + NULL, + }, + { + "instrmem_read_instr2_data_h", + PPU_PPU_INSTRMEM_READ_INSTR2_DATA_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x2c0, + (32/8), + 0, + 2 + 1, + 0, + 4, + 1, + g_ppu_ppu_instrmem_read_instr2_data_h_reg, + NULL, + NULL, + }, + { + "instrmem_read_instr3_data_l", + PPU_PPU_INSTRMEM_READ_INSTR3_DATA_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x2d0, + (32/8), + 0, + 2 + 1, + 0, + 4, + 1, + g_ppu_ppu_instrmem_read_instr3_data_l_reg, + NULL, + NULL, + }, + { + "instrmem_read_instr3_data_h", + PPU_PPU_INSTRMEM_READ_INSTR3_DATA_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x2e0, + (32/8), + 0, + 2 + 1, + 0, + 4, + 1, + g_ppu_ppu_instrmem_read_instr3_data_h_reg, + NULL, + NULL, + }, + { + "se_ppu_mc_srh_fc_cnt_h", + PPU_PPU_SE_PPU_MC_SRH_FC_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x300, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_se_ppu_mc_srh_fc_cnt_h_reg, + NULL, + NULL, + }, + { + "se_ppu_mc_srh_fc_cnt_l", + PPU_PPU_SE_PPU_MC_SRH_FC_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x304, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_se_ppu_mc_srh_fc_cnt_l_reg, + NULL, + NULL, + }, + { + "ppu_se_mc_srh_fc_cnt_h", + PPU_PPU_PPU_SE_MC_SRH_FC_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x308, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_se_mc_srh_fc_cnt_h_reg, + NULL, + NULL, + }, + { + "ppu_se_mc_srh_fc_cnt_l", + PPU_PPU_PPU_SE_MC_SRH_FC_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x30c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_se_mc_srh_fc_cnt_l_reg, + NULL, + NULL, + }, + { + "ppu_se_mc_srh_vld_cnt_h", + PPU_PPU_PPU_SE_MC_SRH_VLD_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x310, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_se_mc_srh_vld_cnt_h_reg, + NULL, + NULL, + }, + { + "ppu_se_mc_srh_vld_cnt_l", + PPU_PPU_PPU_SE_MC_SRH_VLD_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x314, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_se_mc_srh_vld_cnt_l_reg, + NULL, + NULL, + }, + { + "se_ppu_mc_srh_vld_cnt_h", + PPU_PPU_SE_PPU_MC_SRH_VLD_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x318, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_se_ppu_mc_srh_vld_cnt_h_reg, + NULL, + NULL, + }, + { + "se_ppu_mc_srh_vld_cnt_l", + PPU_PPU_SE_PPU_MC_SRH_VLD_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x31c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_se_ppu_mc_srh_vld_cnt_l_reg, + NULL, + NULL, + }, + { + "pbu_ppu_logic_pf_fc_cnt_h", + PPU_PPU_PBU_PPU_LOGIC_PF_FC_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x320, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pbu_ppu_logic_pf_fc_cnt_h_reg, + NULL, + NULL, + }, + { + "pbu_ppu_logic_pf_fc_cnt_l", + PPU_PPU_PBU_PPU_LOGIC_PF_FC_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x324, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pbu_ppu_logic_pf_fc_cnt_l_reg, + NULL, + NULL, + }, + { + "ppu_pbu_logic_rsp_fc_cnt_h", + PPU_PPU_PPU_PBU_LOGIC_RSP_FC_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x328, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_pbu_logic_rsp_fc_cnt_h_reg, + NULL, + NULL, + }, + { + "ppu_pbu_logic_rsp_fc_cnt_l", + PPU_PPU_PPU_PBU_LOGIC_RSP_FC_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x32c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_pbu_logic_rsp_fc_cnt_l_reg, + NULL, + NULL, + }, + { + "ppu_pbu_logic_pf_req_vld_cnt_h", + PPU_PPU_PPU_PBU_LOGIC_PF_REQ_VLD_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x330, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_pbu_logic_pf_req_vld_cnt_h_reg, + NULL, + NULL, + }, + { + "ppu_pbu_logic_pf_req_vld_cnt_l", + PPU_PPU_PPU_PBU_LOGIC_PF_REQ_VLD_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x334, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_pbu_logic_pf_req_vld_cnt_l_reg, + NULL, + NULL, + }, + { + "pbu_ppu_logic_pf_rsp_vld_cnt_h", + PPU_PPU_PBU_PPU_LOGIC_PF_RSP_VLD_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x338, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pbu_ppu_logic_pf_rsp_vld_cnt_h_reg, + NULL, + NULL, + }, + { + "pbu_ppu_logic_pf_rsp_vld_cnt_l", + PPU_PPU_PBU_PPU_LOGIC_PF_RSP_VLD_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x33c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pbu_ppu_logic_pf_rsp_vld_cnt_l_reg, + NULL, + NULL, + }, + { + "pbu_ppu_ifb_rd_fc_cnt_h", + PPU_PPU_PBU_PPU_IFB_RD_FC_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x340, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pbu_ppu_ifb_rd_fc_cnt_h_reg, + NULL, + NULL, + }, + { + "pbu_ppu_ifb_rd_fc_cnt_l", + PPU_PPU_PBU_PPU_IFB_RD_FC_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x344, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pbu_ppu_ifb_rd_fc_cnt_l_reg, + NULL, + NULL, + }, + { + "pbu_ppu_wb_fc_cnt_h", + PPU_PPU_PBU_PPU_WB_FC_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x348, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pbu_ppu_wb_fc_cnt_h_reg, + NULL, + NULL, + }, + { + "pbu_ppu_wb_fc_cnt_l", + PPU_PPU_PBU_PPU_WB_FC_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x34c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pbu_ppu_wb_fc_cnt_l_reg, + NULL, + NULL, + }, + { + "ppu_pbu_mcode_pf_req_vld_cnt_h", + PPU_PPU_PPU_PBU_MCODE_PF_REQ_VLD_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x350, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_pbu_mcode_pf_req_vld_cnt_h_reg, + NULL, + NULL, + }, + { + "ppu_pbu_mcode_pf_req_vld_cnt_l", + PPU_PPU_PPU_PBU_MCODE_PF_REQ_VLD_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x354, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_pbu_mcode_pf_req_vld_cnt_l_reg, + NULL, + NULL, + }, + { + "pbu_ppu_mcode_pf_rsp_vld_cnt_h", + PPU_PPU_PBU_PPU_MCODE_PF_RSP_VLD_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x358, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pbu_ppu_mcode_pf_rsp_vld_cnt_h_reg, + NULL, + NULL, + }, + { + "pbu_ppu_mcode_pf_rsp_vld_cnt_l", + PPU_PPU_PBU_PPU_MCODE_PF_RSP_VLD_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x35c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pbu_ppu_mcode_pf_rsp_vld_cnt_l_reg, + NULL, + NULL, + }, + { + "odma_ppu_para_fc_cnt_h", + PPU_PPU_ODMA_PPU_PARA_FC_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x360, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_odma_ppu_para_fc_cnt_h_reg, + NULL, + NULL, + }, + { + "odma_ppu_para_fc_cnt_l", + PPU_PPU_ODMA_PPU_PARA_FC_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x364, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_odma_ppu_para_fc_cnt_l_reg, + NULL, + NULL, + }, + { + "odma_ppu_mccnt_wr_fc_cnt_h", + PPU_PPU_ODMA_PPU_MCCNT_WR_FC_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x368, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_odma_ppu_mccnt_wr_fc_cnt_h_reg, + NULL, + NULL, + }, + { + "odma_ppu_mccnt_wr_fc_cnt_l", + PPU_PPU_ODMA_PPU_MCCNT_WR_FC_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x36c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_odma_ppu_mccnt_wr_fc_cnt_l_reg, + NULL, + NULL, + }, + { + "ppu_odma_mccnt_wr_vld_cnt_h", + PPU_PPU_PPU_ODMA_MCCNT_WR_VLD_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x370, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_odma_mccnt_wr_vld_cnt_h_reg, + NULL, + NULL, + }, + { + "ppu_odma_mccnt_wr_vld_cnt_l", + PPU_PPU_PPU_ODMA_MCCNT_WR_VLD_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x374, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_odma_mccnt_wr_vld_cnt_l_reg, + NULL, + NULL, + }, + { + "odma_ppu_mccnt_rsp_vld_cnt_h", + PPU_PPU_ODMA_PPU_MCCNT_RSP_VLD_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x378, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_odma_ppu_mccnt_rsp_vld_cnt_h_reg, + NULL, + NULL, + }, + { + "odma_ppu_mccnt_rsp_vld_cnt_l", + PPU_PPU_ODMA_PPU_MCCNT_RSP_VLD_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x37c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_odma_ppu_mccnt_rsp_vld_cnt_l_reg, + NULL, + NULL, + }, + { + "ppu_pktrx_uc_fc_cnt_h", + PPU_PPU_PPU_PKTRX_UC_FC_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x380, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_pktrx_uc_fc_cnt_h_reg, + NULL, + NULL, + }, + { + "ppu_pktrx_uc_fc_cnt_l", + PPU_PPU_PPU_PKTRX_UC_FC_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x384, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_pktrx_uc_fc_cnt_l_reg, + NULL, + NULL, + }, + { + "ppu_pktrx_mc_fc_cnt_h", + PPU_PPU_PPU_PKTRX_MC_FC_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x388, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_pktrx_mc_fc_cnt_h_reg, + NULL, + NULL, + }, + { + "ppu_pktrx_mc_fc_cnt_l", + PPU_PPU_PPU_PKTRX_MC_FC_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x38c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_pktrx_mc_fc_cnt_l_reg, + NULL, + NULL, + }, + { + "pktrx_ppu_desc_vld_cnt_h", + PPU_PPU_PKTRX_PPU_DESC_VLD_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x390, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pktrx_ppu_desc_vld_cnt_h_reg, + NULL, + NULL, + }, + { + "pktrx_ppu_desc_vld_cnt_l", + PPU_PPU_PKTRX_PPU_DESC_VLD_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x394, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pktrx_ppu_desc_vld_cnt_l_reg, + NULL, + NULL, + }, + { + "ppu_pbu_ifb_req_vld_cnt_h", + PPU_PPU_PPU_PBU_IFB_REQ_VLD_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x398, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_pbu_ifb_req_vld_cnt_h_reg, + NULL, + NULL, + }, + { + "ppu_pbu_ifb_req_vld_cnt_l", + PPU_PPU_PPU_PBU_IFB_REQ_VLD_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x39c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_pbu_ifb_req_vld_cnt_l_reg, + NULL, + NULL, + }, + { + "pbu_ppu_ifb_rsp_vld_cnt_h", + PPU_PPU_PBU_PPU_IFB_RSP_VLD_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x3a0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pbu_ppu_ifb_rsp_vld_cnt_h_reg, + NULL, + NULL, + }, + { + "pbu_ppu_ifb_rsp_vld_cnt_l", + PPU_PPU_PBU_PPU_IFB_RSP_VLD_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x3a4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pbu_ppu_ifb_rsp_vld_cnt_l_reg, + NULL, + NULL, + }, + { + "ppu_pbu_wb_vld_cnt_h", + PPU_PPU_PPU_PBU_WB_VLD_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x3a8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_pbu_wb_vld_cnt_h_reg, + NULL, + NULL, + }, + { + "ppu_pbu_wb_vld_cnt_l", + PPU_PPU_PPU_PBU_WB_VLD_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x3ac, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_pbu_wb_vld_cnt_l_reg, + NULL, + NULL, + }, + { + "pbu_ppu_reorder_para_vld_cnt_h", + PPU_PPU_PBU_PPU_REORDER_PARA_VLD_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x3b0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pbu_ppu_reorder_para_vld_cnt_h_reg, + NULL, + NULL, + }, + { + "pbu_ppu_reorder_para_vld_cnt_l", + PPU_PPU_PBU_PPU_REORDER_PARA_VLD_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x3b4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pbu_ppu_reorder_para_vld_cnt_l_reg, + NULL, + NULL, + }, + { + "ppu_odma_para_vld_cnt_h", + PPU_PPU_PPU_ODMA_PARA_VLD_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x3b8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_odma_para_vld_cnt_h_reg, + NULL, + NULL, + }, + { + "ppu_odma_para_vld_cnt_l", + PPU_PPU_PPU_ODMA_PARA_VLD_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x3bc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_odma_para_vld_cnt_l_reg, + NULL, + NULL, + }, + { + "statics_isu_ppu_mc_vld_cnt_h", + PPU_PPU_STATICS_ISU_PPU_MC_VLD_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x400, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_statics_isu_ppu_mc_vld_cnt_h_reg, + NULL, + NULL, + }, + { + "statics_isu_ppu_mc_vld_cnt_l", + PPU_PPU_STATICS_ISU_PPU_MC_VLD_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x404, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_statics_isu_ppu_mc_vld_cnt_l_reg, + NULL, + NULL, + }, + { + "statics_isu_ppu_mc_loop_vld_cnt_h", + PPU_PPU_STATICS_ISU_PPU_MC_LOOP_VLD_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x410, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_statics_isu_ppu_mc_loop_vld_cnt_h_reg, + NULL, + NULL, + }, + { + "statics_isu_ppu_mc_loop_vld_cnt_l", + PPU_PPU_STATICS_ISU_PPU_MC_LOOP_VLD_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x414, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_statics_isu_ppu_mc_loop_vld_cnt_l_reg, + NULL, + NULL, + }, + { + "statics_isu_ppu_uc_vld_cnt_h", + PPU_PPU_STATICS_ISU_PPU_UC_VLD_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x418, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_statics_isu_ppu_uc_vld_cnt_h_reg, + NULL, + NULL, + }, + { + "statics_isu_ppu_uc_vld_cnt_l", + PPU_PPU_STATICS_ISU_PPU_UC_VLD_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x41c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_statics_isu_ppu_uc_vld_cnt_l_reg, + NULL, + NULL, + }, + { + "statics_isu_ppu_uc_bufnumis0_vld_cnt_h", + PPU_PPU_STATICS_ISU_PPU_UC_BUFNUMIS0_VLD_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x420, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_statics_isu_ppu_uc_bufnumis0_vld_cnt_h_reg, + NULL, + NULL, + }, + { + "statics_isu_ppu_uc_bufnumis0_vld_cnt_l", + PPU_PPU_STATICS_ISU_PPU_UC_BUFNUMIS0_VLD_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x424, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_statics_isu_ppu_uc_bufnumis0_vld_cnt_l_reg, + NULL, + NULL, + }, + { + "statics_demux_schedule_mc_vld_cnt_h", + PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_VLD_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x438, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_statics_demux_schedule_mc_vld_cnt_h_reg, + NULL, + NULL, + }, + { + "statics_demux_schedule_mc_vld_cnt_l", + PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_VLD_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x43c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_statics_demux_schedule_mc_vld_cnt_l_reg, + NULL, + NULL, + }, + { + "statics_demux_schedule_mc_bufnumis0_vld_cnt_h", + PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_BUFNUMIS0_VLD_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x440, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_statics_demux_schedule_mc_bufnumis0_vld_cnt_h_reg, + NULL, + NULL, + }, + { + "statics_demux_schedule_mc_bufnumis0_vld_cnt_l", + PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_BUFNUMIS0_VLD_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x444, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_statics_demux_schedule_mc_bufnumis0_vld_cnt_l_reg, + NULL, + NULL, + }, + { + "statics_demux_schedule_mc_srcportis0_vld_cnt_h", + PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_SRCPORTIS0_VLD_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x448, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_statics_demux_schedule_mc_srcportis0_vld_cnt_h_reg, + NULL, + NULL, + }, + { + "statics_demux_schedule_mc_srcportis0_vld_cnt_l", + PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_SRCPORTIS0_VLD_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x44c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_statics_demux_schedule_mc_srcportis0_vld_cnt_l_reg, + NULL, + NULL, + }, + { + "statics_demux_schedule_mc_srcportis1_vld_cnt_h", + PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_SRCPORTIS1_VLD_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x450, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_statics_demux_schedule_mc_srcportis1_vld_cnt_h_reg, + NULL, + NULL, + }, + { + "statics_demux_schedule_mc_srcportis1_vld_cnt_l", + PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_SRCPORTIS1_VLD_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x454, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_statics_demux_schedule_mc_srcportis1_vld_cnt_l_reg, + NULL, + NULL, + }, + { + "statics_demux_schedule_uc_vld_cnt_h", + PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_VLD_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x458, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_statics_demux_schedule_uc_vld_cnt_h_reg, + NULL, + NULL, + }, + { + "statics_demux_schedule_uc_vld_cnt_l", + PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_VLD_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x45c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_statics_demux_schedule_uc_vld_cnt_l_reg, + NULL, + NULL, + }, + { + "statics_demux_schedule_uc_bufnumis0_vld_cnt_h", + PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_BUFNUMIS0_VLD_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x460, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_statics_demux_schedule_uc_bufnumis0_vld_cnt_h_reg, + NULL, + NULL, + }, + { + "statics_demux_schedule_uc_bufnumis0_vld_cnt_l", + PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_BUFNUMIS0_VLD_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x464, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_statics_demux_schedule_uc_bufnumis0_vld_cnt_l_reg, + NULL, + NULL, + }, + { + "statics_demux_schedule_uc_srcportis0_vld_cnt_h", + PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_SRCPORTIS0_VLD_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x468, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_statics_demux_schedule_uc_srcportis0_vld_cnt_h_reg, + NULL, + NULL, + }, + { + "statics_demux_schedule_uc_srcportis0_vld_cnt_l", + PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_SRCPORTIS0_VLD_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x46c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_statics_demux_schedule_uc_srcportis0_vld_cnt_l_reg, + NULL, + NULL, + }, + { + "statics_demux_schedule_uc_srcportis1_vld_cnt_h", + PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_SRCPORTIS1_VLD_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x470, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_statics_demux_schedule_uc_srcportis1_vld_cnt_h_reg, + NULL, + NULL, + }, + { + "statics_demux_schedule_uc_srcportis1_vld_cnt_l", + PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_SRCPORTIS1_VLD_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x474, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_statics_demux_schedule_uc_srcportis1_vld_cnt_l_reg, + NULL, + NULL, + }, + { + "statics_ppu_wb_vld_cnt_h", + PPU_PPU_STATICS_PPU_WB_VLD_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x478, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_statics_ppu_wb_vld_cnt_h_reg, + NULL, + NULL, + }, + { + "statics_ppu_wb_vld_cnt_l", + PPU_PPU_STATICS_PPU_WB_VLD_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x47c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_statics_ppu_wb_vld_cnt_l_reg, + NULL, + NULL, + }, + { + "statics_ppu_wb_bufnumis0_vld_cnt_h", + PPU_PPU_STATICS_PPU_WB_BUFNUMIS0_VLD_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x480, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_statics_ppu_wb_bufnumis0_vld_cnt_h_reg, + NULL, + NULL, + }, + { + "statics_ppu_wb_bufnumis0_vld_cnt_l", + PPU_PPU_STATICS_PPU_WB_BUFNUMIS0_VLD_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x484, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_statics_ppu_wb_bufnumis0_vld_cnt_l_reg, + NULL, + NULL, + }, + { + "statics_ppu_wb_srcportis0_vld_cnt_h", + PPU_PPU_STATICS_PPU_WB_SRCPORTIS0_VLD_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x488, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_statics_ppu_wb_srcportis0_vld_cnt_h_reg, + NULL, + NULL, + }, + { + "statics_ppu_wb_srcportis0_vld_cnt_l", + PPU_PPU_STATICS_PPU_WB_SRCPORTIS0_VLD_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x48c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_statics_ppu_wb_srcportis0_vld_cnt_l_reg, + NULL, + NULL, + }, + { + "statics_ppu_wb_srcportis1_vld_cnt_h", + PPU_PPU_STATICS_PPU_WB_SRCPORTIS1_VLD_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x490, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_statics_ppu_wb_srcportis1_vld_cnt_h_reg, + NULL, + NULL, + }, + { + "statics_ppu_wb_srcportis1_vld_cnt_l", + PPU_PPU_STATICS_PPU_WB_SRCPORTIS1_VLD_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x494, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_statics_ppu_wb_srcportis1_vld_cnt_l_reg, + NULL, + NULL, + }, + { + "statics_ppu_wb_halt_send_type_vld_cnt_h", + PPU_PPU_STATICS_PPU_WB_HALT_SEND_TYPE_VLD_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x498, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_statics_ppu_wb_halt_send_type_vld_cnt_h_reg, + NULL, + NULL, + }, + { + "statics_ppu_wb_halt_send_type_vld_cnt_l", + PPU_PPU_STATICS_PPU_WB_HALT_SEND_TYPE_VLD_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x49c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_statics_ppu_wb_halt_send_type_vld_cnt_l_reg, + NULL, + NULL, + }, + { + "statics_ppu_wb_mf_type_vld_cnt_h", + PPU_PPU_STATICS_PPU_WB_MF_TYPE_VLD_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4a0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_statics_ppu_wb_mf_type_vld_cnt_h_reg, + NULL, + NULL, + }, + { + "statics_ppu_wb_mf_type_vld_cnt_l", + PPU_PPU_STATICS_PPU_WB_MF_TYPE_VLD_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4a4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_statics_ppu_wb_mf_type_vld_cnt_l_reg, + NULL, + NULL, + }, + { + "statics_ppu_wb_halt_continue_end_vld_cnt_h", + PPU_PPU_STATICS_PPU_WB_HALT_CONTINUE_END_VLD_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4a8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_statics_ppu_wb_halt_continue_end_vld_cnt_h_reg, + NULL, + NULL, + }, + { + "statics_ppu_wb_halt_continue_end_vld_cnt_l", + PPU_PPU_STATICS_PPU_WB_HALT_CONTINUE_END_VLD_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4ac, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_statics_ppu_wb_halt_continue_end_vld_cnt_l_reg, + NULL, + NULL, + }, + { + "statics_ppu_wb_dup_flag_vld_cnt_h", + PPU_PPU_STATICS_PPU_WB_DUP_FLAG_VLD_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4b0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_statics_ppu_wb_dup_flag_vld_cnt_h_reg, + NULL, + NULL, + }, + { + "statics_ppu_wb_dup_flag_vld_cnt_l", + PPU_PPU_STATICS_PPU_WB_DUP_FLAG_VLD_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4b4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_statics_ppu_wb_dup_flag_vld_cnt_l_reg, + NULL, + NULL, + }, + { + "statics_ppu_wb_last_flag_vld_cnt_h", + PPU_PPU_STATICS_PPU_WB_LAST_FLAG_VLD_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4b8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_statics_ppu_wb_last_flag_vld_cnt_h_reg, + NULL, + NULL, + }, + { + "statics_ppu_wb_last_flag_vld_cnt_l", + PPU_PPU_STATICS_PPU_WB_LAST_FLAG_VLD_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4bc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_statics_ppu_wb_last_flag_vld_cnt_l_reg, + NULL, + NULL, + }, + { + "statics_ppu_wb_dis_flag_vld_cnt_h", + PPU_PPU_STATICS_PPU_WB_DIS_FLAG_VLD_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4c0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_statics_ppu_wb_dis_flag_vld_cnt_h_reg, + NULL, + NULL, + }, + { + "statics_ppu_wb_dis_flag_vld_cnt_l", + PPU_PPU_STATICS_PPU_WB_DIS_FLAG_VLD_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4c4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_statics_ppu_wb_dis_flag_vld_cnt_l_reg, + NULL, + NULL, + }, + { + "statics_pbu_ppu_reorder_halt_send_type_vld_cnt_h", + PPU_PPU_STATICS_PBU_PPU_REORDER_HALT_SEND_TYPE_VLD_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4c8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_statics_pbu_ppu_reorder_halt_send_type_vld_cnt_h_reg, + NULL, + NULL, + }, + { + "statics_pbu_ppu_reorder_halt_send_type_vld_cnt_l", + PPU_PPU_STATICS_PBU_PPU_REORDER_HALT_SEND_TYPE_VLD_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4c0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_statics_pbu_ppu_reorder_halt_send_type_vld_cnt_l_reg, + NULL, + NULL, + }, + { + "statics_pbu_ppu_reorder_mf_type_vld_cnt_h", + PPU_PPU_STATICS_PBU_PPU_REORDER_MF_TYPE_VLD_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4d0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_statics_pbu_ppu_reorder_mf_type_vld_cnt_h_reg, + NULL, + NULL, + }, + { + "statics_pbu_ppu_reorder_mf_type_vld_cnt_l", + PPU_PPU_STATICS_PBU_PPU_REORDER_MF_TYPE_VLD_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4d4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_statics_pbu_ppu_reorder_mf_type_vld_cnt_l_reg, + NULL, + NULL, + }, + { + "statics_pbu_ppu_reorder_halt_continue_end_vld_cnt_h", + PPU_PPU_STATICS_PBU_PPU_REORDER_HALT_CONTINUE_END_VLD_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4d8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_statics_pbu_ppu_reorder_halt_continue_end_vld_cnt_h_reg, + NULL, + NULL, + }, + { + "statics_pbu_ppu_reorder_halt_continue_end_vld_cnt_l", + PPU_PPU_STATICS_PBU_PPU_REORDER_HALT_CONTINUE_END_VLD_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4dc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_statics_pbu_ppu_reorder_halt_continue_end_vld_cnt_l_reg, + NULL, + NULL, + }, + { + "car_green_pkt_vld_cnt_h", + PPU_PPU_CAR_GREEN_PKT_VLD_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4e0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_car_green_pkt_vld_cnt_h_reg, + NULL, + NULL, + }, + { + "car_green_pkt_vld_cnt_l", + PPU_PPU_CAR_GREEN_PKT_VLD_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4e4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_car_green_pkt_vld_cnt_l_reg, + NULL, + NULL, + }, + { + "car_yellow_pkt_vld_cnt_h", + PPU_PPU_CAR_YELLOW_PKT_VLD_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4e8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_car_yellow_pkt_vld_cnt_h_reg, + NULL, + NULL, + }, + { + "car_yellow_pkt_vld_cnt_l", + PPU_PPU_CAR_YELLOW_PKT_VLD_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4ec, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_car_yellow_pkt_vld_cnt_l_reg, + NULL, + NULL, + }, + { + "car_red_pkt_vld_cnt_h", + PPU_PPU_CAR_RED_PKT_VLD_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4f0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_car_red_pkt_vld_cnt_h_reg, + NULL, + NULL, + }, + { + "car_red_pkt_vld_cnt_l", + PPU_PPU_CAR_RED_PKT_VLD_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4f4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_car_red_pkt_vld_cnt_l_reg, + NULL, + NULL, + }, + { + "car_drop_pkt_vld_cnt_h", + PPU_PPU_CAR_DROP_PKT_VLD_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4f8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_car_drop_pkt_vld_cnt_h_reg, + NULL, + NULL, + }, + { + "car_drop_pkt_vld_cnt_l", + PPU_PPU_CAR_DROP_PKT_VLD_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4fc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_car_drop_pkt_vld_cnt_l_reg, + NULL, + NULL, + }, + { + "ppu_pktrx_mc_ptr_vld_cnt_h", + PPU_PPU_PPU_PKTRX_MC_PTR_VLD_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x500, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_pktrx_mc_ptr_vld_cnt_h_reg, + NULL, + NULL, + }, + { + "ppu_pktrx_mc_ptr_vld_cnt_l", + PPU_PPU_PPU_PKTRX_MC_PTR_VLD_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x504, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_pktrx_mc_ptr_vld_cnt_l_reg, + NULL, + NULL, + }, + { + "isu_ppu_loopback_fc_cnt_h", + PPU_PPU_ISU_PPU_LOOPBACK_FC_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x508, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_isu_ppu_loopback_fc_cnt_h_reg, + NULL, + NULL, + }, + { + "isu_ppu_loopback_fc_cnt_l", + PPU_PPU_ISU_PPU_LOOPBACK_FC_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x50c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_isu_ppu_loopback_fc_cnt_l_reg, + NULL, + NULL, + }, + { + "ppu_culster_pbu_mcode_pf_req_prog_full_assert_cfg", + PPU_PPU_PPU_CULSTER_PBU_MCODE_PF_REQ_PROG_FULL_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x540, + (32/8), + 0, + 0x5 + 1, + 0, + 4, + 1, + g_ppu_ppu_ppu_culster_pbu_mcode_pf_req_prog_full_assert_cfg_reg, + NULL, + NULL, + }, + { + "ppu_culster_pbu_mcode_pf_req_prog_full_negate_cfg", + PPU_PPU_PPU_CULSTER_PBU_MCODE_PF_REQ_PROG_FULL_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x558, + (32/8), + 0, + 0x5 + 1, + 0, + 4, + 1, + g_ppu_ppu_ppu_culster_pbu_mcode_pf_req_prog_full_negate_cfg_reg, + NULL, + NULL, + }, + { + "ppu_culster_pbu_mcode_pf_req_prog_empty_assert_cfg", + PPU_PPU_PPU_CULSTER_PBU_MCODE_PF_REQ_PROG_EMPTY_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x570, + (32/8), + 0, + 0x5 + 1, + 0, + 4, + 1, + g_ppu_ppu_ppu_culster_pbu_mcode_pf_req_prog_empty_assert_cfg_reg, + NULL, + NULL, + }, + { + "ppu_culster_pbu_mcode_pf_req_prog_empty_negate_cfg", + PPU_PPU_PPU_CULSTER_PBU_MCODE_PF_REQ_PROG_EMPTY_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x588, + (32/8), + 0, + 0x5 + 1, + 0, + 4, + 1, + g_ppu_ppu_ppu_culster_pbu_mcode_pf_req_prog_empty_negate_cfg_reg, + NULL, + NULL, + }, + { + "ppu_pbu_mcode_pf_rsp_prog_full_assert_cfg", + PPU_PPU_PPU_PBU_MCODE_PF_RSP_PROG_FULL_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5a0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_pbu_mcode_pf_rsp_prog_full_assert_cfg_reg, + NULL, + NULL, + }, + { + "ppu_pbu_mcode_pf_rsp_prog_full_negate_cfg", + PPU_PPU_PPU_PBU_MCODE_PF_RSP_PROG_FULL_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5a4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_pbu_mcode_pf_rsp_prog_full_negate_cfg_reg, + NULL, + NULL, + }, + { + "ppu_pbu_mcode_pf_rsp_prog_empty_assert_cfg", + PPU_PPU_PPU_PBU_MCODE_PF_RSP_PROG_EMPTY_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5a8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_pbu_mcode_pf_rsp_prog_empty_assert_cfg_reg, + NULL, + NULL, + }, + { + "ppu_pbu_mcode_pf_rsp_prog_empty_negate_cfg", + PPU_PPU_PPU_PBU_MCODE_PF_RSP_PROG_EMPTY_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5ac, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_pbu_mcode_pf_rsp_prog_empty_negate_cfg_reg, + NULL, + NULL, + }, + { + "mccnt_fifo_prog_full_assert_cfg", + PPU_PPU_MCCNT_FIFO_PROG_FULL_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5b0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_mccnt_fifo_prog_full_assert_cfg_reg, + NULL, + NULL, + }, + { + "mccnt_fifo_prog_full_negate_cfg", + PPU_PPU_MCCNT_FIFO_PROG_FULL_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5b4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_mccnt_fifo_prog_full_negate_cfg_reg, + NULL, + NULL, + }, + { + "mccnt_fifo_prog_empty_assert_cfg", + PPU_PPU_MCCNT_FIFO_PROG_EMPTY_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5b8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_mccnt_fifo_prog_empty_assert_cfg_reg, + NULL, + NULL, + }, + { + "mccnt_fifo_prog_empty_negate_cfg", + PPU_PPU_MCCNT_FIFO_PROG_EMPTY_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5bc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_mccnt_fifo_prog_empty_negate_cfg_reg, + NULL, + NULL, + }, + { + "uc_mf_fifo_prog_full_assert_cfg", + PPU_PPU_UC_MF_FIFO_PROG_FULL_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5c0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_uc_mf_fifo_prog_full_assert_cfg_reg, + NULL, + NULL, + }, + { + "uc_mf_fifo_prog_full_negate_cfg", + PPU_PPU_UC_MF_FIFO_PROG_FULL_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5c4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_uc_mf_fifo_prog_full_negate_cfg_reg, + NULL, + NULL, + }, + { + "uc_mf_fifo_prog_empty_assert_cfg", + PPU_PPU_UC_MF_FIFO_PROG_EMPTY_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5c8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_uc_mf_fifo_prog_empty_assert_cfg_reg, + NULL, + NULL, + }, + { + "uc_mf_fifo_prog_empty_negate_cfg", + PPU_PPU_UC_MF_FIFO_PROG_EMPTY_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5cc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_uc_mf_fifo_prog_empty_negate_cfg_reg, + NULL, + NULL, + }, + { + "mc_mf_fifo_prog_full_assert_cfg", + PPU_PPU_MC_MF_FIFO_PROG_FULL_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5d0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_mc_mf_fifo_prog_full_assert_cfg_reg, + NULL, + NULL, + }, + { + "mc_mf_fifo_prog_full_negate_cfg", + PPU_PPU_MC_MF_FIFO_PROG_FULL_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5d4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_mc_mf_fifo_prog_full_negate_cfg_reg, + NULL, + NULL, + }, + { + "mc_mf_fifo_prog_empty_assert_cfg", + PPU_PPU_MC_MF_FIFO_PROG_EMPTY_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5d8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_mc_mf_fifo_prog_empty_assert_cfg_reg, + NULL, + NULL, + }, + { + "mc_mf_fifo_prog_empty_negate_cfg", + PPU_PPU_MC_MF_FIFO_PROG_EMPTY_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5dc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_mc_mf_fifo_prog_empty_negate_cfg_reg, + NULL, + NULL, + }, + { + "isu_mf_fifo_prog_full_assert_cfg", + PPU_PPU_ISU_MF_FIFO_PROG_FULL_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5e0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_isu_mf_fifo_prog_full_assert_cfg_reg, + NULL, + NULL, + }, + { + "isu_mf_fifo_prog_full_negate_cfg", + PPU_PPU_ISU_MF_FIFO_PROG_FULL_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5e4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_isu_mf_fifo_prog_full_negate_cfg_reg, + NULL, + NULL, + }, + { + "isu_mf_fifo_prog_empty_assert_cfg", + PPU_PPU_ISU_MF_FIFO_PROG_EMPTY_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5e8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_isu_mf_fifo_prog_empty_assert_cfg_reg, + NULL, + NULL, + }, + { + "isu_mf_fifo_prog_empty_negate_cfg", + PPU_PPU_ISU_MF_FIFO_PROG_EMPTY_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5ec, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_isu_mf_fifo_prog_empty_negate_cfg_reg, + NULL, + NULL, + }, + { + "isu_fwft_mf_fifo_prog_empty_assert_cfg", + PPU_PPU_ISU_FWFT_MF_FIFO_PROG_EMPTY_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5f8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_isu_fwft_mf_fifo_prog_empty_assert_cfg_reg, + NULL, + NULL, + }, + { + "isu_fwft_mf_fifo_prog_empty_negate_cfg", + PPU_PPU_ISU_FWFT_MF_FIFO_PROG_EMPTY_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5fc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_isu_fwft_mf_fifo_prog_empty_negate_cfg_reg, + NULL, + NULL, + }, + { + "isu_mc_para_mf_fifo_prog_full_assert_cfg", + PPU_PPU_ISU_MC_PARA_MF_FIFO_PROG_FULL_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x600, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_isu_mc_para_mf_fifo_prog_full_assert_cfg_reg, + NULL, + NULL, + }, + { + "isu_mc_para_mf_fifo_prog_full_negate_cfg", + PPU_PPU_ISU_MC_PARA_MF_FIFO_PROG_FULL_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x604, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_isu_mc_para_mf_fifo_prog_full_negate_cfg_reg, + NULL, + NULL, + }, + { + "isu_mc_para_mf_fifo_prog_empty_assert_cfg", + PPU_PPU_ISU_MC_PARA_MF_FIFO_PROG_EMPTY_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x608, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_isu_mc_para_mf_fifo_prog_empty_assert_cfg_reg, + NULL, + NULL, + }, + { + "isu_mc_para_mf_fifo_prog_empty_negate_cfg", + PPU_PPU_ISU_MC_PARA_MF_FIFO_PROG_EMPTY_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x60c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_isu_mc_para_mf_fifo_prog_empty_negate_cfg_reg, + NULL, + NULL, + }, + { + "group_id_fifo_prog_full_assert_cfg", + PPU_PPU_GROUP_ID_FIFO_PROG_FULL_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x610, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_group_id_fifo_prog_full_assert_cfg_reg, + NULL, + NULL, + }, + { + "group_id_fifo_prog_full_negate_cfg", + PPU_PPU_GROUP_ID_FIFO_PROG_FULL_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x614, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_group_id_fifo_prog_full_negate_cfg_reg, + NULL, + NULL, + }, + { + "group_id_fifo_prog_empty_assert_cfg", + PPU_PPU_GROUP_ID_FIFO_PROG_EMPTY_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x618, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_group_id_fifo_prog_empty_assert_cfg_reg, + NULL, + NULL, + }, + { + "group_id_fifo_prog_empty_negate_cfg", + PPU_PPU_GROUP_ID_FIFO_PROG_EMPTY_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x61c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_group_id_fifo_prog_empty_negate_cfg_reg, + NULL, + NULL, + }, + { + "sa_para_fifo_prog_full_assert_cfg", + PPU_PPU_SA_PARA_FIFO_PROG_FULL_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x620, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_sa_para_fifo_prog_full_assert_cfg_reg, + NULL, + NULL, + }, + { + "sa_para_fifo_prog_full_negate_cfg", + PPU_PPU_SA_PARA_FIFO_PROG_FULL_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x624, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_sa_para_fifo_prog_full_negate_cfg_reg, + NULL, + NULL, + }, + { + "sa_para_fifo_prog_empty_assert_cfg", + PPU_PPU_SA_PARA_FIFO_PROG_EMPTY_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x628, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_sa_para_fifo_prog_empty_assert_cfg_reg, + NULL, + NULL, + }, + { + "sa_para_fifo_prog_empty_negate_cfg", + PPU_PPU_SA_PARA_FIFO_PROG_EMPTY_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x62c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_sa_para_fifo_prog_empty_negate_cfg_reg, + NULL, + NULL, + }, + { + "se_mc_rsp_fifo_prog_full_assert_cfg", + PPU_PPU_SE_MC_RSP_FIFO_PROG_FULL_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x630, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_se_mc_rsp_fifo_prog_full_assert_cfg_reg, + NULL, + NULL, + }, + { + "se_mc_rsp_fifo_prog_full_negate_cfg", + PPU_PPU_SE_MC_RSP_FIFO_PROG_FULL_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x634, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_se_mc_rsp_fifo_prog_full_negate_cfg_reg, + NULL, + NULL, + }, + { + "se_mc_rsp_fifo_prog_empty_assert_cfg", + PPU_PPU_SE_MC_RSP_FIFO_PROG_EMPTY_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x638, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_se_mc_rsp_fifo_prog_empty_assert_cfg_reg, + NULL, + NULL, + }, + { + "se_mc_rsp_fifo_prog_empty_negate_cfg", + PPU_PPU_SE_MC_RSP_FIFO_PROG_EMPTY_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x63c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_se_mc_rsp_fifo_prog_empty_negate_cfg_reg, + NULL, + NULL, + }, + { + "dup_para_fifo_prog_full_assert_cfg", + PPU_PPU_DUP_PARA_FIFO_PROG_FULL_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x640, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_dup_para_fifo_prog_full_assert_cfg_reg, + NULL, + NULL, + }, + { + "dup_para_fifo_prog_full_negate_cfg", + PPU_PPU_DUP_PARA_FIFO_PROG_FULL_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x644, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_dup_para_fifo_prog_full_negate_cfg_reg, + NULL, + NULL, + }, + { + "dup_para_fifo_prog_empty_assert_cfg", + PPU_PPU_DUP_PARA_FIFO_PROG_EMPTY_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x648, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_dup_para_fifo_prog_empty_assert_cfg_reg, + NULL, + NULL, + }, + { + "dup_para_fifo_prog_empty_negate_cfg", + PPU_PPU_DUP_PARA_FIFO_PROG_EMPTY_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x64c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_dup_para_fifo_prog_empty_negate_cfg_reg, + NULL, + NULL, + }, + { + "pf_rsp_fifo_prog_full_assert_cfg", + PPU_PPU_PF_RSP_FIFO_PROG_FULL_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x650, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pf_rsp_fifo_prog_full_assert_cfg_reg, + NULL, + NULL, + }, + { + "pf_rsp_fifo_prog_full_negate_cfg", + PPU_PPU_PF_RSP_FIFO_PROG_FULL_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x654, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pf_rsp_fifo_prog_full_negate_cfg_reg, + NULL, + NULL, + }, + { + "pf_rsp_fifo_prog_empty_assert_cfg", + PPU_PPU_PF_RSP_FIFO_PROG_EMPTY_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x658, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pf_rsp_fifo_prog_empty_assert_cfg_reg, + NULL, + NULL, + }, + { + "pf_rsp_fifo_prog_empty_negate_cfg", + PPU_PPU_PF_RSP_FIFO_PROG_EMPTY_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x65c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pf_rsp_fifo_prog_empty_negate_cfg_reg, + NULL, + NULL, + }, + { + "dup_freeptr_fifo_prog_full_assert_cfg", + PPU_PPU_DUP_FREEPTR_FIFO_PROG_FULL_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x660, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_dup_freeptr_fifo_prog_full_assert_cfg_reg, + NULL, + NULL, + }, + { + "dup_freeptr_fifo_prog_full_negate_cfg", + PPU_PPU_DUP_FREEPTR_FIFO_PROG_FULL_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x664, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_dup_freeptr_fifo_prog_full_negate_cfg_reg, + NULL, + NULL, + }, + { + "dup_freeptr_fifo_prog_empty_assert_cfg", + PPU_PPU_DUP_FREEPTR_FIFO_PROG_EMPTY_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x668, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_dup_freeptr_fifo_prog_empty_assert_cfg_reg, + NULL, + NULL, + }, + { + "dup_freeptr_fifo_prog_empty_negate_cfg", + PPU_PPU_DUP_FREEPTR_FIFO_PROG_EMPTY_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x66c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_dup_freeptr_fifo_prog_empty_negate_cfg_reg, + NULL, + NULL, + }, + { + "pf_req_fifo_prog_full_assert_cfg", + PPU_PPU_PF_REQ_FIFO_PROG_FULL_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x670, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pf_req_fifo_prog_full_assert_cfg_reg, + NULL, + NULL, + }, + { + "pf_req_fifo_prog_full_negate_cfg", + PPU_PPU_PF_REQ_FIFO_PROG_FULL_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x674, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pf_req_fifo_prog_full_negate_cfg_reg, + NULL, + NULL, + }, + { + "pf_req_fifo_prog_empty_assert_cfg", + PPU_PPU_PF_REQ_FIFO_PROG_EMPTY_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x678, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pf_req_fifo_prog_empty_assert_cfg_reg, + NULL, + NULL, + }, + { + "pf_req_fifo_prog_empty_negate_cfg", + PPU_PPU_PF_REQ_FIFO_PROG_EMPTY_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x67c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pf_req_fifo_prog_empty_negate_cfg_reg, + NULL, + NULL, + }, + { + "car_flag_fifo_prog_full_assert_cfg", + PPU_PPU_CAR_FLAG_FIFO_PROG_FULL_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x680, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_car_flag_fifo_prog_full_assert_cfg_reg, + NULL, + NULL, + }, + { + "car_flag_fifo_prog_full_negate_cfg", + PPU_PPU_CAR_FLAG_FIFO_PROG_FULL_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x684, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_car_flag_fifo_prog_full_negate_cfg_reg, + NULL, + NULL, + }, + { + "car_flag_fifo_prog_empty_assert_cfg", + PPU_PPU_CAR_FLAG_FIFO_PROG_EMPTY_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x688, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_car_flag_fifo_prog_empty_assert_cfg_reg, + NULL, + NULL, + }, + { + "car_flag_fifo_prog_empty_negate_cfg", + PPU_PPU_CAR_FLAG_FIFO_PROG_EMPTY_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x68c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_car_flag_fifo_prog_empty_negate_cfg_reg, + NULL, + NULL, + }, + { + "ppu_cluster_mf_out_afifo_prog_full_assert_cfg", + PPU_PPU_PPU_CLUSTER_MF_OUT_AFIFO_PROG_FULL_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x690, + (32/8), + 0, + 0x5 + 1, + 0, + 16, + 1, + g_ppu_ppu_ppu_cluster_mf_out_afifo_prog_full_assert_cfg_reg, + NULL, + NULL, + }, + { + "ppu_cluster_mf_out_afifo_prog_full_negate_cfg", + PPU_PPU_PPU_CLUSTER_MF_OUT_AFIFO_PROG_FULL_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x694, + (32/8), + 0, + 0x5 + 1, + 0, + 16, + 1, + g_ppu_ppu_ppu_cluster_mf_out_afifo_prog_full_negate_cfg_reg, + NULL, + NULL, + }, + { + "ppu_cluster_mf_out_afifo_prog_empty_assert_cfg", + PPU_PPU_PPU_CLUSTER_MF_OUT_AFIFO_PROG_EMPTY_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x698, + (32/8), + 0, + 0x5 + 1, + 0, + 16, + 1, + g_ppu_ppu_ppu_cluster_mf_out_afifo_prog_empty_assert_cfg_reg, + NULL, + NULL, + }, + { + "ppu_cluster_mf_out_afifo_prog_empty_negate_cfg", + PPU_PPU_PPU_CLUSTER_MF_OUT_AFIFO_PROG_EMPTY_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x69c, + (32/8), + 0, + 0x5 + 1, + 0, + 16, + 1, + g_ppu_ppu_ppu_cluster_mf_out_afifo_prog_empty_negate_cfg_reg, + NULL, + NULL, + }, + { + "ppu_cop_key_fifo_prog_full_assert_cfg", + PPU_PPU_PPU_COP_KEY_FIFO_PROG_FULL_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x6f0, + (32/8), + 0, + 0x5 + 1, + 0, + 16, + 1, + g_ppu_ppu_ppu_cop_key_fifo_prog_full_assert_cfg_reg, + NULL, + NULL, + }, + { + "ppu_cop_key_fifo_prog_full_negate_cfg", + PPU_PPU_PPU_COP_KEY_FIFO_PROG_FULL_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x6f4, + (32/8), + 0, + 0x5 + 1, + 0, + 16, + 1, + g_ppu_ppu_ppu_cop_key_fifo_prog_full_negate_cfg_reg, + NULL, + NULL, + }, + { + "ppu_cop_key_fifo_prog_empty_assert_cfg", + PPU_PPU_PPU_COP_KEY_FIFO_PROG_EMPTY_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x6f8, + (32/8), + 0, + 0x5 + 1, + 0, + 16, + 1, + g_ppu_ppu_ppu_cop_key_fifo_prog_empty_assert_cfg_reg, + NULL, + NULL, + }, + { + "ppu_cop_key_fifo_prog_empty_negate_cfg", + PPU_PPU_PPU_COP_KEY_FIFO_PROG_EMPTY_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x6fc, + (32/8), + 0, + 0x5 + 1, + 0, + 16, + 1, + g_ppu_ppu_ppu_cop_key_fifo_prog_empty_negate_cfg_reg, + NULL, + NULL, + }, + { + "ppu_cop_random_mod_para_fifo_prog_full_assert_cfg", + PPU_PPU_PPU_COP_RANDOM_MOD_PARA_FIFO_PROG_FULL_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x750, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_cop_random_mod_para_fifo_prog_full_assert_cfg_reg, + NULL, + NULL, + }, + { + "ppu_cop_random_mod_para_fifo_prog_full_negate_cfg", + PPU_PPU_PPU_COP_RANDOM_MOD_PARA_FIFO_PROG_FULL_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x754, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_cop_random_mod_para_fifo_prog_full_negate_cfg_reg, + NULL, + NULL, + }, + { + "ppu_cop_random_mod_para_fifo_prog_empty_assert_cfg", + PPU_PPU_PPU_COP_RANDOM_MOD_PARA_FIFO_PROG_EMPTY_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x758, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_cop_random_mod_para_fifo_prog_empty_assert_cfg_reg, + NULL, + NULL, + }, + { + "ppu_cop_random_mod_para_fifo_prog_empty_negate_cfg", + PPU_PPU_PPU_COP_RANDOM_MOD_PARA_FIFO_PROG_EMPTY_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x75c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_cop_random_mod_para_fifo_prog_empty_negate_cfg_reg, + NULL, + NULL, + }, + { + "ppu_cop_random_mod_result_fifo_prog_full_assert_cfg", + PPU_PPU_PPU_COP_RANDOM_MOD_RESULT_FIFO_PROG_FULL_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x760, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_cop_random_mod_result_fifo_prog_full_assert_cfg_reg, + NULL, + NULL, + }, + { + "ppu_cop_random_mod_result_fifo_prog_full_negate_cfg", + PPU_PPU_PPU_COP_RANDOM_MOD_RESULT_FIFO_PROG_FULL_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x764, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_cop_random_mod_result_fifo_prog_full_negate_cfg_reg, + NULL, + NULL, + }, + { + "ppu_cop_random_mod_result_fifo_prog_empty_assert_cfg", + PPU_PPU_PPU_COP_RANDOM_MOD_RESULT_FIFO_PROG_EMPTY_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x768, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_cop_random_mod_result_fifo_prog_empty_assert_cfg_reg, + NULL, + NULL, + }, + { + "ppu_cop_random_mod_result_fifo_prog_empty_negate_cfg", + PPU_PPU_PPU_COP_RANDOM_MOD_RESULT_FIFO_PROG_EMPTY_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x76c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_cop_random_mod_result_fifo_prog_empty_negate_cfg_reg, + NULL, + NULL, + }, + { + "ppu_cop_checksum_result_fifo_prog_full_assert_cfg", + PPU_PPU_PPU_COP_CHECKSUM_RESULT_FIFO_PROG_FULL_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x770, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_cop_checksum_result_fifo_prog_full_assert_cfg_reg, + NULL, + NULL, + }, + { + "ppu_cop_checksum_result_fifo_prog_full_negate_cfg", + PPU_PPU_PPU_COP_CHECKSUM_RESULT_FIFO_PROG_FULL_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x774, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_cop_checksum_result_fifo_prog_full_negate_cfg_reg, + NULL, + NULL, + }, + { + "ppu_cop_checksum_result_fifo_prog_empty_assert_cfg", + PPU_PPU_PPU_COP_CHECKSUM_RESULT_FIFO_PROG_EMPTY_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x778, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_cop_checksum_result_fifo_prog_empty_assert_cfg_reg, + NULL, + NULL, + }, + { + "ppu_cop_checksum_result_fifo_prog_empty_negate_cfg", + PPU_PPU_PPU_COP_CHECKSUM_RESULT_FIFO_PROG_EMPTY_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x77c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_cop_checksum_result_fifo_prog_empty_negate_cfg_reg, + NULL, + NULL, + }, + { + "ppu_cop_crc_first_para_fifo_prog_full_assert_cfg", + PPU_PPU_PPU_COP_CRC_FIRST_PARA_FIFO_PROG_FULL_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x780, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_cop_crc_first_para_fifo_prog_full_assert_cfg_reg, + NULL, + NULL, + }, + { + "ppu_cop_crc_first_para_fifo_prog_full_negate_cfg", + PPU_PPU_PPU_COP_CRC_FIRST_PARA_FIFO_PROG_FULL_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x784, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_cop_crc_first_para_fifo_prog_full_negate_cfg_reg, + NULL, + NULL, + }, + { + "ppu_cop_crc_first_para_fifo_prog_empty_assert_cfg", + PPU_PPU_PPU_COP_CRC_FIRST_PARA_FIFO_PROG_EMPTY_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x788, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_cop_crc_first_para_fifo_prog_empty_assert_cfg_reg, + NULL, + NULL, + }, + { + "ppu_cop_crc_first_para_fifo_prog_empty_negate_cfg", + PPU_PPU_PPU_COP_CRC_FIRST_PARA_FIFO_PROG_EMPTY_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x78c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_cop_crc_first_para_fifo_prog_empty_negate_cfg_reg, + NULL, + NULL, + }, + { + "ppu_cop_crc_bypass_delay_prog_full_assert_cfg", + PPU_PPU_PPU_COP_CRC_BYPASS_DELAY_PROG_FULL_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x790, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_cop_crc_bypass_delay_prog_full_assert_cfg_reg, + NULL, + NULL, + }, + { + "ppu_cop_crc_bypass_delay_prog_full_negate_cfg", + PPU_PPU_PPU_COP_CRC_BYPASS_DELAY_PROG_FULL_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x794, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_cop_crc_bypass_delay_prog_full_negate_cfg_reg, + NULL, + NULL, + }, + { + "ppu_cop_crc_bypass_delay_prog_empty_assert_cfg", + PPU_PPU_PPU_COP_CRC_BYPASS_DELAY_PROG_EMPTY_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x798, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_cop_crc_bypass_delay_prog_empty_assert_cfg_reg, + NULL, + NULL, + }, + { + "ppu_cop_crc_bypass_delay_prog_empty_negate_cfg", + PPU_PPU_PPU_COP_CRC_BYPASS_DELAY_PROG_EMPTY_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x79c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_cop_crc_bypass_delay_prog_empty_negate_cfg_reg, + NULL, + NULL, + }, + { + "ppu_cop_crc_second_para_fifo_prog_full_assert_cfg", + PPU_PPU_PPU_COP_CRC_SECOND_PARA_FIFO_PROG_FULL_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7a0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_cop_crc_second_para_fifo_prog_full_assert_cfg_reg, + NULL, + NULL, + }, + { + "ppu_cop_crc_second_para_fifo_prog_full_negate_cfg", + PPU_PPU_PPU_COP_CRC_SECOND_PARA_FIFO_PROG_FULL_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7a4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_cop_crc_second_para_fifo_prog_full_negate_cfg_reg, + NULL, + NULL, + }, + { + "ppu_cop_crc_second_para_fifo_prog_empty_assert_cfg", + PPU_PPU_PPU_COP_CRC_SECOND_PARA_FIFO_PROG_EMPTY_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7a8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_cop_crc_second_para_fifo_prog_empty_assert_cfg_reg, + NULL, + NULL, + }, + { + "ppu_cop_crc_second_para_fifo_prog_empty_negate_cfg", + PPU_PPU_PPU_COP_CRC_SECOND_PARA_FIFO_PROG_EMPTY_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7ac, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_cop_crc_second_para_fifo_prog_empty_negate_cfg_reg, + NULL, + NULL, + }, + { + "ppu_cop_crc_result_fwft_fifo_prog_full_assert_cfg", + PPU_PPU_PPU_COP_CRC_RESULT_FWFT_FIFO_PROG_FULL_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7b0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_cop_crc_result_fwft_fifo_prog_full_assert_cfg_reg, + NULL, + NULL, + }, + { + "ppu_cop_crc_result_fwft_fifo_prog_full_negate_cfg", + PPU_PPU_PPU_COP_CRC_RESULT_FWFT_FIFO_PROG_FULL_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7b4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_cop_crc_result_fwft_fifo_prog_full_negate_cfg_reg, + NULL, + NULL, + }, + { + "ppu_cop_crc_result_fwft_fifo_prog_empty_assert_cfg", + PPU_PPU_PPU_COP_CRC_RESULT_FWFT_FIFO_PROG_EMPTY_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7b8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_cop_crc_result_fwft_fifo_prog_empty_assert_cfg_reg, + NULL, + NULL, + }, + { + "ppu_cop_crc_result_fwft_fifo_prog_empty_negate_cfg", + PPU_PPU_PPU_COP_CRC_RESULT_FWFT_FIFO_PROG_EMPTY_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7bc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_cop_crc_result_fwft_fifo_prog_empty_negate_cfg_reg, + NULL, + NULL, + }, + { + "ppu_cop_multiply_para_fifo_prog_full_assert_cfg", + PPU_PPU_PPU_COP_MULTIPLY_PARA_FIFO_PROG_FULL_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7c0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_cop_multiply_para_fifo_prog_full_assert_cfg_reg, + NULL, + NULL, + }, + { + "ppu_cop_multiply_para_fifo_prog_full_negate_cfg", + PPU_PPU_PPU_COP_MULTIPLY_PARA_FIFO_PROG_FULL_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7c4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_cop_multiply_para_fifo_prog_full_negate_cfg_reg, + NULL, + NULL, + }, + { + "ppu_cop_multiply_para_fifo_prog_empty_assert_cfg", + PPU_PPU_PPU_COP_MULTIPLY_PARA_FIFO_PROG_EMPTY_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7c8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_cop_multiply_para_fifo_prog_empty_assert_cfg_reg, + NULL, + NULL, + }, + { + "ppu_cop_multiply_para_fifo_prog_empty_negate_cfg", + PPU_PPU_PPU_COP_MULTIPLY_PARA_FIFO_PROG_EMPTY_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7cc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_cop_multiply_para_fifo_prog_empty_negate_cfg_reg, + NULL, + NULL, + }, + { + "ppu_cop_multiply_para_result_fifo_prog_full_assert_cfg", + PPU_PPU_PPU_COP_MULTIPLY_PARA_RESULT_FIFO_PROG_FULL_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7d0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_cop_multiply_para_result_fifo_prog_full_assert_cfg_reg, + NULL, + NULL, + }, + { + "ppu_cop_multiply_para_result_fifo_prog_full_negate_cfg", + PPU_PPU_PPU_COP_MULTIPLY_PARA_RESULT_FIFO_PROG_FULL_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7d4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_cop_multiply_para_result_fifo_prog_full_negate_cfg_reg, + NULL, + NULL, + }, + { + "ppu_cop_multiply_para_result_fifo_prog_empty_assert_cfg", + PPU_PPU_PPU_COP_MULTIPLY_PARA_RESULT_FIFO_PROG_EMPTY_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7d8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_cop_multiply_para_result_fifo_prog_empty_assert_cfg_reg, + NULL, + NULL, + }, + { + "ppu_cop_multiply_para_result_fifo_prog_empty_negate_cfg", + PPU_PPU_PPU_COP_MULTIPLY_PARA_RESULT_FIFO_PROG_EMPTY_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7dc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_cop_multiply_para_result_fifo_prog_empty_negate_cfg_reg, + NULL, + NULL, + }, + { + "free_global_num_fwft_fifo_prog_full_assert_cfg", + PPU_PPU_FREE_GLOBAL_NUM_FWFT_FIFO_PROG_FULL_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7e0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_free_global_num_fwft_fifo_prog_full_assert_cfg_reg, + NULL, + NULL, + }, + { + "free_global_num_fwft_fifo_prog_full_negate_cfg", + PPU_PPU_FREE_GLOBAL_NUM_FWFT_FIFO_PROG_FULL_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7e4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_free_global_num_fwft_fifo_prog_full_negate_cfg_reg, + NULL, + NULL, + }, + { + "free_global_num_fwft_fifo_prog_empty_assert_cfg", + PPU_PPU_FREE_GLOBAL_NUM_FWFT_FIFO_PROG_EMPTY_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7e8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_free_global_num_fwft_fifo_prog_empty_assert_cfg_reg, + NULL, + NULL, + }, + { + "free_global_num_fwft_fifo_prog_empty_negate_cfg", + PPU_PPU_FREE_GLOBAL_NUM_FWFT_FIFO_PROG_EMPTY_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7ec, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_free_global_num_fwft_fifo_prog_empty_negate_cfg_reg, + NULL, + NULL, + }, + { + "ppu_pktrx_mc_ptr_fifo_prog_full_assert_cfg", + PPU_PPU_PPU_PKTRX_MC_PTR_FIFO_PROG_FULL_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7f0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_pktrx_mc_ptr_fifo_prog_full_assert_cfg_reg, + NULL, + NULL, + }, + { + "ppu_pktrx_mc_ptr_fifo_prog_full_negate_cfg", + PPU_PPU_PPU_PKTRX_MC_PTR_FIFO_PROG_FULL_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7f4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_pktrx_mc_ptr_fifo_prog_full_negate_cfg_reg, + NULL, + NULL, + }, + { + "ppu_pktrx_mc_ptr_fifo_prog_empty_assert_cfg", + PPU_PPU_PPU_PKTRX_MC_PTR_FIFO_PROG_EMPTY_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7f8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_pktrx_mc_ptr_fifo_prog_empty_assert_cfg_reg, + NULL, + NULL, + }, + { + "ppu_pktrx_mc_ptr_fifo_prog_empty_negate_cfg", + PPU_PPU_PPU_PKTRX_MC_PTR_FIFO_PROG_EMPTY_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7fc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_ppu_pktrx_mc_ptr_fifo_prog_empty_negate_cfg_reg, + NULL, + NULL, + }, + { + "pkt_data0", + PPU_PPU_PKT_DATA0r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x800, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data0_reg, + NULL, + NULL, + }, + { + "pkt_data1", + PPU_PPU_PKT_DATA1r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x804, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data1_reg, + NULL, + NULL, + }, + { + "pkt_data2", + PPU_PPU_PKT_DATA2r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x808, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data2_reg, + NULL, + NULL, + }, + { + "pkt_data3", + PPU_PPU_PKT_DATA3r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x80c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data3_reg, + NULL, + NULL, + }, + { + "pkt_data4", + PPU_PPU_PKT_DATA4r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x810, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data4_reg, + NULL, + NULL, + }, + { + "pkt_data5", + PPU_PPU_PKT_DATA5r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x814, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data5_reg, + NULL, + NULL, + }, + { + "pkt_data6", + PPU_PPU_PKT_DATA6r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x818, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data6_reg, + NULL, + NULL, + }, + { + "pkt_data7", + PPU_PPU_PKT_DATA7r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x81c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data7_reg, + NULL, + NULL, + }, + { + "pkt_data8", + PPU_PPU_PKT_DATA8r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x820, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data8_reg, + NULL, + NULL, + }, + { + "pkt_data9", + PPU_PPU_PKT_DATA9r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x824, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data9_reg, + NULL, + NULL, + }, + { + "pkt_data10", + PPU_PPU_PKT_DATA10r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x828, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data10_reg, + NULL, + NULL, + }, + { + "pkt_data11", + PPU_PPU_PKT_DATA11r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x82c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data11_reg, + NULL, + NULL, + }, + { + "pkt_data12", + PPU_PPU_PKT_DATA12r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x830, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data12_reg, + NULL, + NULL, + }, + { + "pkt_data13", + PPU_PPU_PKT_DATA13r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x834, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data13_reg, + NULL, + NULL, + }, + { + "pkt_data14", + PPU_PPU_PKT_DATA14r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x838, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data14_reg, + NULL, + NULL, + }, + { + "pkt_data15", + PPU_PPU_PKT_DATA15r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x83c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data15_reg, + NULL, + NULL, + }, + { + "pkt_data16", + PPU_PPU_PKT_DATA16r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x840, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data16_reg, + NULL, + NULL, + }, + { + "pkt_data17", + PPU_PPU_PKT_DATA17r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x844, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data17_reg, + NULL, + NULL, + }, + { + "pkt_data18", + PPU_PPU_PKT_DATA18r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x848, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data18_reg, + NULL, + NULL, + }, + { + "pkt_data19", + PPU_PPU_PKT_DATA19r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x84c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data19_reg, + NULL, + NULL, + }, + { + "pkt_data20", + PPU_PPU_PKT_DATA20r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x850, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data20_reg, + NULL, + NULL, + }, + { + "pkt_data21", + PPU_PPU_PKT_DATA21r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x854, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data21_reg, + NULL, + NULL, + }, + { + "pkt_data22", + PPU_PPU_PKT_DATA22r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x858, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data22_reg, + NULL, + NULL, + }, + { + "pkt_data23", + PPU_PPU_PKT_DATA23r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x85c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data23_reg, + NULL, + NULL, + }, + { + "pkt_data24", + PPU_PPU_PKT_DATA24r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x860, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data24_reg, + NULL, + NULL, + }, + { + "pkt_data25", + PPU_PPU_PKT_DATA25r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x864, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data25_reg, + NULL, + NULL, + }, + { + "pkt_data26", + PPU_PPU_PKT_DATA26r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x868, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data26_reg, + NULL, + NULL, + }, + { + "pkt_data27", + PPU_PPU_PKT_DATA27r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x86c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data27_reg, + NULL, + NULL, + }, + { + "pkt_data28", + PPU_PPU_PKT_DATA28r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x870, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data28_reg, + NULL, + NULL, + }, + { + "pkt_data29", + PPU_PPU_PKT_DATA29r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x874, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data29_reg, + NULL, + NULL, + }, + { + "pkt_data30", + PPU_PPU_PKT_DATA30r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x878, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data30_reg, + NULL, + NULL, + }, + { + "pkt_data31", + PPU_PPU_PKT_DATA31r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x87c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data31_reg, + NULL, + NULL, + }, + { + "pkt_data32", + PPU_PPU_PKT_DATA32r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x880, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data32_reg, + NULL, + NULL, + }, + { + "pkt_data33", + PPU_PPU_PKT_DATA33r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x884, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data33_reg, + NULL, + NULL, + }, + { + "pkt_data34", + PPU_PPU_PKT_DATA34r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x888, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data34_reg, + NULL, + NULL, + }, + { + "pkt_data35", + PPU_PPU_PKT_DATA35r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x88c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data35_reg, + NULL, + NULL, + }, + { + "pkt_data36", + PPU_PPU_PKT_DATA36r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x890, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data36_reg, + NULL, + NULL, + }, + { + "pkt_data37", + PPU_PPU_PKT_DATA37r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x894, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data37_reg, + NULL, + NULL, + }, + { + "pkt_data38", + PPU_PPU_PKT_DATA38r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x898, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data38_reg, + NULL, + NULL, + }, + { + "pkt_data39", + PPU_PPU_PKT_DATA39r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x89c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data39_reg, + NULL, + NULL, + }, + { + "pkt_data40", + PPU_PPU_PKT_DATA40r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8a0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data40_reg, + NULL, + NULL, + }, + { + "pkt_data41", + PPU_PPU_PKT_DATA41r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8a4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data41_reg, + NULL, + NULL, + }, + { + "pkt_data42", + PPU_PPU_PKT_DATA42r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8a8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data42_reg, + NULL, + NULL, + }, + { + "pkt_data43", + PPU_PPU_PKT_DATA43r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8ac, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data43_reg, + NULL, + NULL, + }, + { + "pkt_data44", + PPU_PPU_PKT_DATA44r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8b0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data44_reg, + NULL, + NULL, + }, + { + "pkt_data45", + PPU_PPU_PKT_DATA45r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8b4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data45_reg, + NULL, + NULL, + }, + { + "pkt_data46", + PPU_PPU_PKT_DATA46r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8b8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data46_reg, + NULL, + NULL, + }, + { + "pkt_data47", + PPU_PPU_PKT_DATA47r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8bc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data47_reg, + NULL, + NULL, + }, + { + "pkt_data48", + PPU_PPU_PKT_DATA48r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8c0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data48_reg, + NULL, + NULL, + }, + { + "pkt_data49", + PPU_PPU_PKT_DATA49r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8c4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data49_reg, + NULL, + NULL, + }, + { + "pkt_data50", + PPU_PPU_PKT_DATA50r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8c8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data50_reg, + NULL, + NULL, + }, + { + "pkt_data51", + PPU_PPU_PKT_DATA51r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8cc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data51_reg, + NULL, + NULL, + }, + { + "pkt_data52", + PPU_PPU_PKT_DATA52r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8d0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data52_reg, + NULL, + NULL, + }, + { + "pkt_data53", + PPU_PPU_PKT_DATA53r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8d4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data53_reg, + NULL, + NULL, + }, + { + "pkt_data54", + PPU_PPU_PKT_DATA54r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8d8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data54_reg, + NULL, + NULL, + }, + { + "pkt_data55", + PPU_PPU_PKT_DATA55r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8dc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data55_reg, + NULL, + NULL, + }, + { + "pkt_data56", + PPU_PPU_PKT_DATA56r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8e0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data56_reg, + NULL, + NULL, + }, + { + "pkt_data57", + PPU_PPU_PKT_DATA57r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8e4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data57_reg, + NULL, + NULL, + }, + { + "pkt_data58", + PPU_PPU_PKT_DATA58r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8e8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data58_reg, + NULL, + NULL, + }, + { + "pkt_data59", + PPU_PPU_PKT_DATA59r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8ec, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data59_reg, + NULL, + NULL, + }, + { + "pkt_data60", + PPU_PPU_PKT_DATA60r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8f0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data60_reg, + NULL, + NULL, + }, + { + "pkt_data61", + PPU_PPU_PKT_DATA61r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8f4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data61_reg, + NULL, + NULL, + }, + { + "pkt_data62", + PPU_PPU_PKT_DATA62r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8f8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data62_reg, + NULL, + NULL, + }, + { + "pkt_data63", + PPU_PPU_PKT_DATA63r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8fc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data63_reg, + NULL, + NULL, + }, + { + "pkt_data64", + PPU_PPU_PKT_DATA64r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x900, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data64_reg, + NULL, + NULL, + }, + { + "pkt_data65", + PPU_PPU_PKT_DATA65r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x904, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data65_reg, + NULL, + NULL, + }, + { + "pkt_data66", + PPU_PPU_PKT_DATA66r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x908, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data66_reg, + NULL, + NULL, + }, + { + "pkt_data67", + PPU_PPU_PKT_DATA67r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x90c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data67_reg, + NULL, + NULL, + }, + { + "pkt_data68", + PPU_PPU_PKT_DATA68r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x910, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data68_reg, + NULL, + NULL, + }, + { + "pkt_data69", + PPU_PPU_PKT_DATA69r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x914, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data69_reg, + NULL, + NULL, + }, + { + "pkt_data70", + PPU_PPU_PKT_DATA70r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x918, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data70_reg, + NULL, + NULL, + }, + { + "pkt_data71", + PPU_PPU_PKT_DATA71r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x91c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data71_reg, + NULL, + NULL, + }, + { + "pkt_data72", + PPU_PPU_PKT_DATA72r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x920, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data72_reg, + NULL, + NULL, + }, + { + "pkt_data73", + PPU_PPU_PKT_DATA73r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x924, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data73_reg, + NULL, + NULL, + }, + { + "pkt_data74", + PPU_PPU_PKT_DATA74r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x928, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data74_reg, + NULL, + NULL, + }, + { + "pkt_data75", + PPU_PPU_PKT_DATA75r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x92c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data75_reg, + NULL, + NULL, + }, + { + "pkt_data76", + PPU_PPU_PKT_DATA76r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x930, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data76_reg, + NULL, + NULL, + }, + { + "pkt_data77", + PPU_PPU_PKT_DATA77r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x934, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data77_reg, + NULL, + NULL, + }, + { + "pkt_data78", + PPU_PPU_PKT_DATA78r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x938, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data78_reg, + NULL, + NULL, + }, + { + "pkt_data79", + PPU_PPU_PKT_DATA79r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x93c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data79_reg, + NULL, + NULL, + }, + { + "pkt_data80", + PPU_PPU_PKT_DATA80r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x940, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data80_reg, + NULL, + NULL, + }, + { + "pkt_data81", + PPU_PPU_PKT_DATA81r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x944, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data81_reg, + NULL, + NULL, + }, + { + "pkt_data82", + PPU_PPU_PKT_DATA82r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x948, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data82_reg, + NULL, + NULL, + }, + { + "pkt_data83", + PPU_PPU_PKT_DATA83r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x94c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data83_reg, + NULL, + NULL, + }, + { + "pkt_data84", + PPU_PPU_PKT_DATA84r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x950, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data84_reg, + NULL, + NULL, + }, + { + "pkt_data85", + PPU_PPU_PKT_DATA85r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x954, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data85_reg, + NULL, + NULL, + }, + { + "pkt_data86", + PPU_PPU_PKT_DATA86r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x958, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data86_reg, + NULL, + NULL, + }, + { + "pkt_data87", + PPU_PPU_PKT_DATA87r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x95c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data87_reg, + NULL, + NULL, + }, + { + "pkt_data88", + PPU_PPU_PKT_DATA88r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x960, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data88_reg, + NULL, + NULL, + }, + { + "pkt_data89", + PPU_PPU_PKT_DATA89r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x964, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data89_reg, + NULL, + NULL, + }, + { + "pkt_data90", + PPU_PPU_PKT_DATA90r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x968, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data90_reg, + NULL, + NULL, + }, + { + "pkt_data91", + PPU_PPU_PKT_DATA91r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x96c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data91_reg, + NULL, + NULL, + }, + { + "pkt_data92", + PPU_PPU_PKT_DATA92r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x970, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data92_reg, + NULL, + NULL, + }, + { + "pkt_data93", + PPU_PPU_PKT_DATA93r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x974, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data93_reg, + NULL, + NULL, + }, + { + "pkt_data94", + PPU_PPU_PKT_DATA94r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x978, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data94_reg, + NULL, + NULL, + }, + { + "pkt_data95", + PPU_PPU_PKT_DATA95r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x97c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data95_reg, + NULL, + NULL, + }, + { + "pkt_data96", + PPU_PPU_PKT_DATA96r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x980, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data96_reg, + NULL, + NULL, + }, + { + "pkt_data97", + PPU_PPU_PKT_DATA97r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x984, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data97_reg, + NULL, + NULL, + }, + { + "pkt_data98", + PPU_PPU_PKT_DATA98r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x988, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data98_reg, + NULL, + NULL, + }, + { + "pkt_data99", + PPU_PPU_PKT_DATA99r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x98c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data99_reg, + NULL, + NULL, + }, + { + "pkt_data100", + PPU_PPU_PKT_DATA100r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x990, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data100_reg, + NULL, + NULL, + }, + { + "pkt_data101", + PPU_PPU_PKT_DATA101r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x994, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data101_reg, + NULL, + NULL, + }, + { + "pkt_data102", + PPU_PPU_PKT_DATA102r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x998, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data102_reg, + NULL, + NULL, + }, + { + "pkt_data103", + PPU_PPU_PKT_DATA103r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x99c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data103_reg, + NULL, + NULL, + }, + { + "pkt_data104", + PPU_PPU_PKT_DATA104r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9a0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data104_reg, + NULL, + NULL, + }, + { + "pkt_data105", + PPU_PPU_PKT_DATA105r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9a4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data105_reg, + NULL, + NULL, + }, + { + "pkt_data106", + PPU_PPU_PKT_DATA106r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9a8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data106_reg, + NULL, + NULL, + }, + { + "pkt_data107", + PPU_PPU_PKT_DATA107r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9ac, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data107_reg, + NULL, + NULL, + }, + { + "pkt_data108", + PPU_PPU_PKT_DATA108r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9b0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data108_reg, + NULL, + NULL, + }, + { + "pkt_data109", + PPU_PPU_PKT_DATA109r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9b4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data109_reg, + NULL, + NULL, + }, + { + "pkt_data110", + PPU_PPU_PKT_DATA110r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9b8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data110_reg, + NULL, + NULL, + }, + { + "pkt_data111", + PPU_PPU_PKT_DATA111r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9bc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data111_reg, + NULL, + NULL, + }, + { + "pkt_data112", + PPU_PPU_PKT_DATA112r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9c0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data112_reg, + NULL, + NULL, + }, + { + "pkt_data113", + PPU_PPU_PKT_DATA113r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9c4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data113_reg, + NULL, + NULL, + }, + { + "pkt_data114", + PPU_PPU_PKT_DATA114r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9c8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data114_reg, + NULL, + NULL, + }, + { + "pkt_data115", + PPU_PPU_PKT_DATA115r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9cc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data115_reg, + NULL, + NULL, + }, + { + "pkt_data116", + PPU_PPU_PKT_DATA116r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9d0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data116_reg, + NULL, + NULL, + }, + { + "pkt_data117", + PPU_PPU_PKT_DATA117r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9d4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data117_reg, + NULL, + NULL, + }, + { + "pkt_data118", + PPU_PPU_PKT_DATA118r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9d8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data118_reg, + NULL, + NULL, + }, + { + "pkt_data119", + PPU_PPU_PKT_DATA119r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9dc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data119_reg, + NULL, + NULL, + }, + { + "pkt_data120", + PPU_PPU_PKT_DATA120r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9e0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data120_reg, + NULL, + NULL, + }, + { + "pkt_data121", + PPU_PPU_PKT_DATA121r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9e4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data121_reg, + NULL, + NULL, + }, + { + "pkt_data122", + PPU_PPU_PKT_DATA122r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9e8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data122_reg, + NULL, + NULL, + }, + { + "pkt_data123", + PPU_PPU_PKT_DATA123r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9ec, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data123_reg, + NULL, + NULL, + }, + { + "pkt_data124", + PPU_PPU_PKT_DATA124r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9f0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data124_reg, + NULL, + NULL, + }, + { + "pkt_data125", + PPU_PPU_PKT_DATA125r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9f4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data125_reg, + NULL, + NULL, + }, + { + "pkt_data126", + PPU_PPU_PKT_DATA126r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9f8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data126_reg, + NULL, + NULL, + }, + { + "pkt_data127", + PPU_PPU_PKT_DATA127r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9fc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_pkt_data127_reg, + NULL, + NULL, + }, + { + "spr0", + PPU_PPU_SPR0r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa00, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_spr0_reg, + NULL, + NULL, + }, + { + "spr1", + PPU_PPU_SPR1r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa04, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_spr1_reg, + NULL, + NULL, + }, + { + "spr2", + PPU_PPU_SPR2r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa08, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_spr2_reg, + NULL, + NULL, + }, + { + "spr3", + PPU_PPU_SPR3r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa0c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_spr3_reg, + NULL, + NULL, + }, + { + "spr4", + PPU_PPU_SPR4r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa10, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_spr4_reg, + NULL, + NULL, + }, + { + "spr5", + PPU_PPU_SPR5r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa14, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_spr5_reg, + NULL, + NULL, + }, + { + "spr6", + PPU_PPU_SPR6r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa18, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_spr6_reg, + NULL, + NULL, + }, + { + "spr7", + PPU_PPU_SPR7r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa1c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_spr7_reg, + NULL, + NULL, + }, + { + "spr8", + PPU_PPU_SPR8r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa20, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_spr8_reg, + NULL, + NULL, + }, + { + "spr9", + PPU_PPU_SPR9r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa24, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_spr9_reg, + NULL, + NULL, + }, + { + "spr10", + PPU_PPU_SPR10r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa28, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_spr10_reg, + NULL, + NULL, + }, + { + "spr11", + PPU_PPU_SPR11r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa2c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_spr11_reg, + NULL, + NULL, + }, + { + "spr12", + PPU_PPU_SPR12r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa30, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_spr12_reg, + NULL, + NULL, + }, + { + "spr13", + PPU_PPU_SPR13r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa34, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_spr13_reg, + NULL, + NULL, + }, + { + "spr14", + PPU_PPU_SPR14r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa38, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_spr14_reg, + NULL, + NULL, + }, + { + "spr15", + PPU_PPU_SPR15r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa3c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_spr15_reg, + NULL, + NULL, + }, + { + "spr16", + PPU_PPU_SPR16r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa40, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_spr16_reg, + NULL, + NULL, + }, + { + "spr17", + PPU_PPU_SPR17r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa44, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_spr17_reg, + NULL, + NULL, + }, + { + "spr18", + PPU_PPU_SPR18r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa48, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_spr18_reg, + NULL, + NULL, + }, + { + "spr19", + PPU_PPU_SPR19r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa4c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_spr19_reg, + NULL, + NULL, + }, + { + "spr20", + PPU_PPU_SPR20r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa50, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_spr20_reg, + NULL, + NULL, + }, + { + "spr21", + PPU_PPU_SPR21r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa54, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_spr21_reg, + NULL, + NULL, + }, + { + "spr22", + PPU_PPU_SPR22r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa58, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_spr22_reg, + NULL, + NULL, + }, + { + "spr23", + PPU_PPU_SPR23r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa5c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_spr23_reg, + NULL, + NULL, + }, + { + "spr24", + PPU_PPU_SPR24r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa60, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_spr24_reg, + NULL, + NULL, + }, + { + "spr25", + PPU_PPU_SPR25r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa64, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_spr25_reg, + NULL, + NULL, + }, + { + "spr26", + PPU_PPU_SPR26r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa68, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_spr26_reg, + NULL, + NULL, + }, + { + "spr27", + PPU_PPU_SPR27r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa6c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_spr27_reg, + NULL, + NULL, + }, + { + "spr28", + PPU_PPU_SPR28r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa70, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_spr28_reg, + NULL, + NULL, + }, + { + "spr29", + PPU_PPU_SPR29r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa74, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_spr29_reg, + NULL, + NULL, + }, + { + "spr30", + PPU_PPU_SPR30r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa78, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_spr30_reg, + NULL, + NULL, + }, + { + "spr31", + PPU_PPU_SPR31r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa7c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_spr31_reg, + NULL, + NULL, + }, + { + "rsp0", + PPU_PPU_RSP0r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa80, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_rsp0_reg, + NULL, + NULL, + }, + { + "rsp1", + PPU_PPU_RSP1r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa84, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_rsp1_reg, + NULL, + NULL, + }, + { + "rsp2", + PPU_PPU_RSP2r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa88, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_rsp2_reg, + NULL, + NULL, + }, + { + "rsp3", + PPU_PPU_RSP3r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa8c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_rsp3_reg, + NULL, + NULL, + }, + { + "rsp4", + PPU_PPU_RSP4r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa90, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_rsp4_reg, + NULL, + NULL, + }, + { + "rsp5", + PPU_PPU_RSP5r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa94, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_rsp5_reg, + NULL, + NULL, + }, + { + "rsp6", + PPU_PPU_RSP6r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa98, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_rsp6_reg, + NULL, + NULL, + }, + { + "rsp7", + PPU_PPU_RSP7r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa9c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_rsp7_reg, + NULL, + NULL, + }, + { + "rsp8", + PPU_PPU_RSP8r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xaa0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_rsp8_reg, + NULL, + NULL, + }, + { + "rsp9", + PPU_PPU_RSP9r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xaa4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_rsp9_reg, + NULL, + NULL, + }, + { + "rsp10", + PPU_PPU_RSP10r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xaa8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_rsp10_reg, + NULL, + NULL, + }, + { + "rsp11", + PPU_PPU_RSP11r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xaac, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_rsp11_reg, + NULL, + NULL, + }, + { + "rsp12", + PPU_PPU_RSP12r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xab0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_rsp12_reg, + NULL, + NULL, + }, + { + "rsp13", + PPU_PPU_RSP13r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xab4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_rsp13_reg, + NULL, + NULL, + }, + { + "rsp14", + PPU_PPU_RSP14r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xab8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_rsp14_reg, + NULL, + NULL, + }, + { + "rsp15", + PPU_PPU_RSP15r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xabc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_rsp15_reg, + NULL, + NULL, + }, + { + "rsp16", + PPU_PPU_RSP16r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xac0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_rsp16_reg, + NULL, + NULL, + }, + { + "rsp17", + PPU_PPU_RSP17r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xac4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_rsp17_reg, + NULL, + NULL, + }, + { + "rsp18", + PPU_PPU_RSP18r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xac8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_rsp18_reg, + NULL, + NULL, + }, + { + "rsp19", + PPU_PPU_RSP19r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xacc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_rsp19_reg, + NULL, + NULL, + }, + { + "rsp20", + PPU_PPU_RSP20r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xad0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_rsp20_reg, + NULL, + NULL, + }, + { + "rsp21", + PPU_PPU_RSP21r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xad4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_rsp21_reg, + NULL, + NULL, + }, + { + "rsp22", + PPU_PPU_RSP22r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xad8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_rsp22_reg, + NULL, + NULL, + }, + { + "rsp23", + PPU_PPU_RSP23r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xadc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_rsp23_reg, + NULL, + NULL, + }, + { + "rsp24", + PPU_PPU_RSP24r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xae0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_rsp24_reg, + NULL, + NULL, + }, + { + "rsp25", + PPU_PPU_RSP25r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xae4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_rsp25_reg, + NULL, + NULL, + }, + { + "rsp26", + PPU_PPU_RSP26r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xae8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_rsp26_reg, + NULL, + NULL, + }, + { + "rsp27", + PPU_PPU_RSP27r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xaec, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_rsp27_reg, + NULL, + NULL, + }, + { + "rsp28", + PPU_PPU_RSP28r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xaf0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_rsp28_reg, + NULL, + NULL, + }, + { + "rsp29", + PPU_PPU_RSP29r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xaf4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_rsp29_reg, + NULL, + NULL, + }, + { + "rsp30", + PPU_PPU_RSP30r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xaf8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_rsp30_reg, + NULL, + NULL, + }, + { + "rsp31", + PPU_PPU_RSP31r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xafc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_rsp31_reg, + NULL, + NULL, + }, + { + "key0", + PPU_PPU_KEY0r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb00, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_key0_reg, + NULL, + NULL, + }, + { + "key1", + PPU_PPU_KEY1r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb04, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_key1_reg, + NULL, + NULL, + }, + { + "key2", + PPU_PPU_KEY2r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb08, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_key2_reg, + NULL, + NULL, + }, + { + "key3", + PPU_PPU_KEY3r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb0c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_key3_reg, + NULL, + NULL, + }, + { + "key4", + PPU_PPU_KEY4r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb10, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_key4_reg, + NULL, + NULL, + }, + { + "key5", + PPU_PPU_KEY5r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb14, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_key5_reg, + NULL, + NULL, + }, + { + "key6", + PPU_PPU_KEY6r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb18, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_key6_reg, + NULL, + NULL, + }, + { + "key7", + PPU_PPU_KEY7r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb1c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_key7_reg, + NULL, + NULL, + }, + { + "key8", + PPU_PPU_KEY8r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb20, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_key8_reg, + NULL, + NULL, + }, + { + "key9", + PPU_PPU_KEY9r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb24, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_key9_reg, + NULL, + NULL, + }, + { + "key10", + PPU_PPU_KEY10r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb28, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_key10_reg, + NULL, + NULL, + }, + { + "key11", + PPU_PPU_KEY11r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb2c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_key11_reg, + NULL, + NULL, + }, + { + "key12", + PPU_PPU_KEY12r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb30, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_key12_reg, + NULL, + NULL, + }, + { + "key13", + PPU_PPU_KEY13r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb34, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_key13_reg, + NULL, + NULL, + }, + { + "key14", + PPU_PPU_KEY14r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb38, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_key14_reg, + NULL, + NULL, + }, + { + "key15", + PPU_PPU_KEY15r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb3c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_key15_reg, + NULL, + NULL, + }, + { + "key16", + PPU_PPU_KEY16r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb40, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_key16_reg, + NULL, + NULL, + }, + { + "key17", + PPU_PPU_KEY17r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb44, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_key17_reg, + NULL, + NULL, + }, + { + "key18", + PPU_PPU_KEY18r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb48, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_key18_reg, + NULL, + NULL, + }, + { + "key19", + PPU_PPU_KEY19r, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb4c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ppu_ppu_key19_reg, + NULL, + NULL, + }, + { + "flag", + PPU_PPU_FLAGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb50, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_ppu_ppu_flag_reg, + NULL, + NULL, + }, + { + "int_1200m_flag", + PPU_CLUSTER_INT_1200M_FLAGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x00, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 8, + g_ppu_cluster_int_1200m_flag_reg, + NULL, + NULL, + }, + { + "bp_instr_l", + PPU_CLUSTER_BP_INSTR_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x04, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_bp_instr_l_reg, + NULL, + NULL, + }, + { + "bp_instr_h", + PPU_CLUSTER_BP_INSTR_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x08, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_bp_instr_h_reg, + NULL, + NULL, + }, + { + "bp_addr", + PPU_CLUSTER_BP_ADDRr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x0c, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0x7 + 1, + DPP_PPU_CLUSTER_SPACE_SIZE, + 4, + 1, + g_ppu_cluster_bp_addr_reg, + NULL, + NULL, + }, + { + "drr", + PPU_CLUSTER_DRRr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2c, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0x7 + 1, + DPP_PPU_CLUSTER_SPACE_SIZE, + 4, + 1, + g_ppu_cluster_drr_reg, + NULL, + NULL, + }, + { + "dsr", + PPU_CLUSTER_DSRr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4c, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_dsr_reg, + NULL, + NULL, + }, + { + "dbg_rtl_date", + PPU_CLUSTER_DBG_RTL_DATEr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x50, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_dbg_rtl_date_reg, + NULL, + NULL, + }, + { + "me_continue", + PPU_CLUSTER_ME_CONTINUEr, + PPU, + DPP_REG_FLAG_WO | DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x80, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_me_continue_reg, + NULL, + NULL, + }, + { + "me_step", + PPU_CLUSTER_ME_STEPr, + PPU, + DPP_REG_FLAG_WO | DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x84, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_me_step_reg, + NULL, + NULL, + }, + { + "me_refresh", + PPU_CLUSTER_ME_REFRESHr, + PPU, + DPP_REG_FLAG_WO | DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x88, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_me_refresh_reg, + NULL, + NULL, + }, + { + "drr_clr", + PPU_CLUSTER_DRR_CLRr, + PPU, + DPP_REG_FLAG_WO | DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x8c, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_drr_clr_reg, + NULL, + NULL, + }, + { + "me_busy_thresold", + PPU_CLUSTER_ME_BUSY_THRESOLDr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x90, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_me_busy_thresold_reg, + NULL, + NULL, + }, + { + "int_1200m_sta", + PPU_CLUSTER_INT_1200M_STAr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x94, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 8, + g_ppu_cluster_int_1200m_sta_reg, + NULL, + NULL, + }, + { + "int_1200m_me_fifo_mask_l", + PPU_CLUSTER_INT_1200M_ME_FIFO_MASK_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc0, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0x7 + 1, + DPP_PPU_CLUSTER_SPACE_SIZE, + 4, + 32, + g_ppu_cluster_int_1200m_me_fifo_mask_l_reg, + NULL, + NULL, + }, + { + "int_1200m_me_fifo_mask_h", + PPU_CLUSTER_INT_1200M_ME_FIFO_MASK_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xe0, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0x7 + 1, + DPP_PPU_CLUSTER_SPACE_SIZE, + 4, + 2, + g_ppu_cluster_int_1200m_me_fifo_mask_h_reg, + NULL, + NULL, + }, + { + "me_fifo_interrupt_flag_l", + PPU_CLUSTER_ME_FIFO_INTERRUPT_FLAG_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x100, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0x7 + 1, + DPP_PPU_CLUSTER_SPACE_SIZE, + 4, + 32, + g_ppu_cluster_me_fifo_interrupt_flag_l_reg, + NULL, + NULL, + }, + { + "me_fifo_interrupt_flag_h", + PPU_CLUSTER_ME_FIFO_INTERRUPT_FLAG_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x120, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0x7 + 1, + DPP_PPU_CLUSTER_SPACE_SIZE, + 4, + 2, + g_ppu_cluster_me_fifo_interrupt_flag_h_reg, + NULL, + NULL, + }, + { + "me_fifo_interrupt_sta_l", + PPU_CLUSTER_ME_FIFO_INTERRUPT_STA_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x140, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0x7 + 1, + DPP_PPU_CLUSTER_SPACE_SIZE, + 4, + 32, + g_ppu_cluster_me_fifo_interrupt_sta_l_reg, + NULL, + NULL, + }, + { + "me_fifo_interrupt_sta_h", + PPU_CLUSTER_ME_FIFO_INTERRUPT_STA_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x160, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0x7 + 1, + DPP_PPU_CLUSTER_SPACE_SIZE, + 4, + 2, + g_ppu_cluster_me_fifo_interrupt_sta_h_reg, + NULL, + NULL, + }, + { + "int_1200m_cluster_mex_fifo_mask_l", + PPU_CLUSTER_INT_1200M_CLUSTER_MEX_FIFO_MASK_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x800, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 32, + g_ppu_cluster_int_1200m_cluster_mex_fifo_mask_l_reg, + NULL, + NULL, + }, + { + "int_1200m_cluster_mex_fifo_mask_h", + PPU_CLUSTER_INT_1200M_CLUSTER_MEX_FIFO_MASK_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x804, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 19, + g_ppu_cluster_int_1200m_cluster_mex_fifo_mask_h_reg, + NULL, + NULL, + }, + { + "int_1200m_cluster_mex_fifo_flag_l", + PPU_CLUSTER_INT_1200M_CLUSTER_MEX_FIFO_FLAG_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x808, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 32, + g_ppu_cluster_int_1200m_cluster_mex_fifo_flag_l_reg, + NULL, + NULL, + }, + { + "int_1200m_cluster_mex_fifo_flag_h", + PPU_CLUSTER_INT_1200M_CLUSTER_MEX_FIFO_FLAG_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x80c, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 19, + g_ppu_cluster_int_1200m_cluster_mex_fifo_flag_h_reg, + NULL, + NULL, + }, + { + "int_1200m_cluster_mex_fifo_stat_l", + PPU_CLUSTER_INT_1200M_CLUSTER_MEX_FIFO_STAT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x810, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 32, + g_ppu_cluster_int_1200m_cluster_mex_fifo_stat_l_reg, + NULL, + NULL, + }, + { + "int_1200m_cluster_mex_fifo_stat_h", + PPU_CLUSTER_INT_1200M_CLUSTER_MEX_FIFO_STAT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x814, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 19, + g_ppu_cluster_int_1200m_cluster_mex_fifo_stat_h_reg, + NULL, + NULL, + }, + { + "ppu_statics_wb_exception_cfg", + PPU_CLUSTER_PPU_STATICS_WB_EXCEPTION_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x824, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 6, + g_ppu_cluster_ppu_statics_wb_exception_cfg_reg, + NULL, + NULL, + }, + { + "thread_switch_en", + PPU_CLUSTER_THREAD_SWITCH_ENr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x8c0, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_thread_switch_en_reg, + NULL, + NULL, + }, + { + "is_me_not_idle", + PPU_CLUSTER_IS_ME_NOT_IDLEr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x8c4, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 8, + g_ppu_cluster_is_me_not_idle_reg, + NULL, + NULL, + }, + { + "ppu_cluster_mf_in_afifo_prog_empty_assert_cfg", + PPU_CLUSTER_PPU_CLUSTER_MF_IN_AFIFO_PROG_EMPTY_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc00, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_ppu_cluster_mf_in_afifo_prog_empty_assert_cfg_reg, + NULL, + NULL, + }, + { + "ppu_cluster_mf_in_afifo_prog_empty_negate_cfg", + PPU_CLUSTER_PPU_CLUSTER_MF_IN_AFIFO_PROG_EMPTY_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc04, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_ppu_cluster_mf_in_afifo_prog_empty_negate_cfg_reg, + NULL, + NULL, + }, + { + "ese_rsp_afifo_prog_empty_assert_cfg", + PPU_CLUSTER_ESE_RSP_AFIFO_PROG_EMPTY_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc08, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_ese_rsp_afifo_prog_empty_assert_cfg_reg, + NULL, + NULL, + }, + { + "ese_rsp_afifo_prog_empty_negate_cfg", + PPU_CLUSTER_ESE_RSP_AFIFO_PROG_EMPTY_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc0c, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_ese_rsp_afifo_prog_empty_negate_cfg_reg, + NULL, + NULL, + }, + { + "ise_rsp_afifo_prog_empty_assert_cfg", + PPU_CLUSTER_ISE_RSP_AFIFO_PROG_EMPTY_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc10, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_ise_rsp_afifo_prog_empty_assert_cfg_reg, + NULL, + NULL, + }, + { + "ise_rsp_afifo_prog_empty_negate_cfg", + PPU_CLUSTER_ISE_RSP_AFIFO_PROG_EMPTY_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc14, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_ise_rsp_afifo_prog_empty_negate_cfg_reg, + NULL, + NULL, + }, + { + "ppu_rsp_ptr_fwft_fifo0_prog_full_assert_cfg", + PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO0_PROG_FULL_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc18, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_ppu_rsp_ptr_fwft_fifo0_prog_full_assert_cfg_reg, + NULL, + NULL, + }, + { + "ppu_rsp_ptr_fwft_fifo0_prog_full_negate_cfg", + PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO0_PROG_FULL_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc1c, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_ppu_rsp_ptr_fwft_fifo0_prog_full_negate_cfg_reg, + NULL, + NULL, + }, + { + "ppu_rsp_ptr_fwft_fifo0_prog_empty_assert_cfg", + PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO0_PROG_EMPTY_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc20, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_ppu_rsp_ptr_fwft_fifo0_prog_empty_assert_cfg_reg, + NULL, + NULL, + }, + { + "ppu_rsp_ptr_fwft_fifo0_prog_empty_negate_cfg", + PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO0_PROG_EMPTY_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc24, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_ppu_rsp_ptr_fwft_fifo0_prog_empty_negate_cfg_reg, + NULL, + NULL, + }, + { + "ppu_rsp_ptr_fwft_fifo1_prog_full_assert_cfg", + PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO1_PROG_FULL_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc28, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_ppu_rsp_ptr_fwft_fifo1_prog_full_assert_cfg_reg, + NULL, + NULL, + }, + { + "ppu_rsp_ptr_fwft_fifo1_prog_full_negate_cfg", + PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO1_PROG_FULL_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc2c, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_ppu_rsp_ptr_fwft_fifo1_prog_full_negate_cfg_reg, + NULL, + NULL, + }, + { + "ppu_rsp_ptr_fwft_fifo1_prog_empty_assert_cfg", + PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO1_PROG_EMPTY_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc30, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_ppu_rsp_ptr_fwft_fifo1_prog_empty_assert_cfg_reg, + NULL, + NULL, + }, + { + "ppu_rsp_ptr_fwft_fifo1_prog_empty_negate_cfg", + PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO1_PROG_EMPTY_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc34, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_ppu_rsp_ptr_fwft_fifo1_prog_empty_negate_cfg_reg, + NULL, + NULL, + }, + { + "sta_rsp_afifo_prog_empty_assert_cfg", + PPU_CLUSTER_STA_RSP_AFIFO_PROG_EMPTY_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc38, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_sta_rsp_afifo_prog_empty_assert_cfg_reg, + NULL, + NULL, + }, + { + "sta_rsp_afifo_prog_empty_negate_cfg", + PPU_CLUSTER_STA_RSP_AFIFO_PROG_EMPTY_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc3c, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_sta_rsp_afifo_prog_empty_negate_cfg_reg, + NULL, + NULL, + }, + { + "ppu_sta_rsp_fwft_fifo_prog_full_assert_cfg", + PPU_CLUSTER_PPU_STA_RSP_FWFT_FIFO_PROG_FULL_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc40, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_ppu_sta_rsp_fwft_fifo_prog_full_assert_cfg_reg, + NULL, + NULL, + }, + { + "ppu_sta_rsp_fwft_fifo_prog_full_negate_cfg", + PPU_CLUSTER_PPU_STA_RSP_FWFT_FIFO_PROG_FULL_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc44, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_ppu_sta_rsp_fwft_fifo_prog_full_negate_cfg_reg, + NULL, + NULL, + }, + { + "ppu_sta_rsp_fwft_fifo_prog_empty_assert_cfg", + PPU_CLUSTER_PPU_STA_RSP_FWFT_FIFO_PROG_EMPTY_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc48, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_ppu_sta_rsp_fwft_fifo_prog_empty_assert_cfg_reg, + NULL, + NULL, + }, + { + "ppu_sta_rsp_fwft_fifo_prog_empty_negate_cfg", + PPU_CLUSTER_PPU_STA_RSP_FWFT_FIFO_PROG_EMPTY_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc4c, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_ppu_sta_rsp_fwft_fifo_prog_empty_negate_cfg_reg, + NULL, + NULL, + }, + { + "cop_rsp_fifo_prog_full_assert_cfg", + PPU_CLUSTER_COP_RSP_FIFO_PROG_FULL_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc50, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_cop_rsp_fifo_prog_full_assert_cfg_reg, + NULL, + NULL, + }, + { + "cop_rsp_fifo_prog_full_negate_cfg", + PPU_CLUSTER_COP_RSP_FIFO_PROG_FULL_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc54, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_cop_rsp_fifo_prog_full_negate_cfg_reg, + NULL, + NULL, + }, + { + "cop_rsp_fifo_prog_empty_assert_cfg", + PPU_CLUSTER_COP_RSP_FIFO_PROG_EMPTY_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc58, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_cop_rsp_fifo_prog_empty_assert_cfg_reg, + NULL, + NULL, + }, + { + "cop_rsp_fifo_prog_empty_negate_cfg", + PPU_CLUSTER_COP_RSP_FIFO_PROG_EMPTY_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc5c, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_cop_rsp_fifo_prog_empty_negate_cfg_reg, + NULL, + NULL, + }, + { + "mcode_pf_rsp_fifo_prog_full_assert_cfg", + PPU_CLUSTER_MCODE_PF_RSP_FIFO_PROG_FULL_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc60, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_mcode_pf_rsp_fifo_prog_full_assert_cfg_reg, + NULL, + NULL, + }, + { + "mcode_pf_rsp_fifo_prog_full_negate_cfg", + PPU_CLUSTER_MCODE_PF_RSP_FIFO_PROG_FULL_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc64, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_mcode_pf_rsp_fifo_prog_full_negate_cfg_reg, + NULL, + NULL, + }, + { + "mcode_pf_rsp_fifo_prog_empty_assert_cfg", + PPU_CLUSTER_MCODE_PF_RSP_FIFO_PROG_EMPTY_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc68, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_mcode_pf_rsp_fifo_prog_empty_assert_cfg_reg, + NULL, + NULL, + }, + { + "mcode_pf_rsp_fifo_prog_empty_negate_cfg", + PPU_CLUSTER_MCODE_PF_RSP_FIFO_PROG_EMPTY_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc6c, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_mcode_pf_rsp_fifo_prog_empty_negate_cfg_reg, + NULL, + NULL, + }, + { + "ppu_cop_rsp_fwft_fifo_prog_full_assert_cfg", + PPU_CLUSTER_PPU_COP_RSP_FWFT_FIFO_PROG_FULL_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc70, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_ppu_cop_rsp_fwft_fifo_prog_full_assert_cfg_reg, + NULL, + NULL, + }, + { + "ppu_cop_rsp_fwft_fifo_prog_full_negate_cfg", + PPU_CLUSTER_PPU_COP_RSP_FWFT_FIFO_PROG_FULL_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc74, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_ppu_cop_rsp_fwft_fifo_prog_full_negate_cfg_reg, + NULL, + NULL, + }, + { + "ppu_cop_rsp_fwft_fifo_prog_empty_assert_cfg", + PPU_CLUSTER_PPU_COP_RSP_FWFT_FIFO_PROG_EMPTY_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc78, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_ppu_cop_rsp_fwft_fifo_prog_empty_assert_cfg_reg, + NULL, + NULL, + }, + { + "ppu_cop_rsp_fwft_fifo_prog_empty_negate_cfg", + PPU_CLUSTER_PPU_COP_RSP_FWFT_FIFO_PROG_EMPTY_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc7c, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_ppu_cop_rsp_fwft_fifo_prog_empty_negate_cfg_reg, + NULL, + NULL, + }, + { + "ppu_ise_key_afifo_prog_full_assert_cfg", + PPU_CLUSTER_PPU_ISE_KEY_AFIFO_PROG_FULL_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc80, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_ppu_ise_key_afifo_prog_full_assert_cfg_reg, + NULL, + NULL, + }, + { + "ppu_ise_key_afifo_prog_full_negate_cfg", + PPU_CLUSTER_PPU_ISE_KEY_AFIFO_PROG_FULL_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc84, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_ppu_ise_key_afifo_prog_full_negate_cfg_reg, + NULL, + NULL, + }, + { + "ppu_ese_key_afifo_prog_full_assert_cfg", + PPU_CLUSTER_PPU_ESE_KEY_AFIFO_PROG_FULL_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc88, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_ppu_ese_key_afifo_prog_full_assert_cfg_reg, + NULL, + NULL, + }, + { + "ppu_ese_key_afifo_prog_full_negate_cfg", + PPU_CLUSTER_PPU_ESE_KEY_AFIFO_PROG_FULL_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc8c, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_ppu_ese_key_afifo_prog_full_negate_cfg_reg, + NULL, + NULL, + }, + { + "ppu_sta_key_afifo_prog_full_assert_cfg", + PPU_CLUSTER_PPU_STA_KEY_AFIFO_PROG_FULL_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc90, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_ppu_sta_key_afifo_prog_full_assert_cfg_reg, + NULL, + NULL, + }, + { + "ppu_sta_key_afifo_prog_full_negate_cfg", + PPU_CLUSTER_PPU_STA_KEY_AFIFO_PROG_FULL_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc94, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_ppu_sta_key_afifo_prog_full_negate_cfg_reg, + NULL, + NULL, + }, + { + "int_600m_cluster_mex_fifo_mask", + PPU_CLUSTER_INT_600M_CLUSTER_MEX_FIFO_MASKr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4034, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 7, + g_ppu_cluster_int_600m_cluster_mex_fifo_mask_reg, + NULL, + NULL, + }, + { + "cluster_mex_fifo_600m_interrupt_flag", + PPU_CLUSTER_CLUSTER_MEX_FIFO_600M_INTERRUPT_FLAGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4038, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 7, + g_ppu_cluster_cluster_mex_fifo_600m_interrupt_flag_reg, + NULL, + NULL, + }, + { + "cluster_mex_fifo_600m_interrupt_sta", + PPU_CLUSTER_CLUSTER_MEX_FIFO_600M_INTERRUPT_STAr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x403c, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 7, + g_ppu_cluster_cluster_mex_fifo_600m_interrupt_sta_reg, + NULL, + NULL, + }, + { + "mex_cnt_cfg", + PPU_CLUSTER_MEX_CNT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4050, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 2, + g_ppu_cluster_mex_cnt_cfg_reg, + NULL, + NULL, + }, + { + "int_600m_cluster_mex_ram_ecc_error_interrupt_mask", + PPU_CLUSTER_INT_600M_CLUSTER_MEX_RAM_ECC_ERROR_INTERRUPT_MASKr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4064, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 6, + g_ppu_cluster_int_600m_cluster_mex_ram_ecc_error_interrupt_mask_reg, + NULL, + NULL, + }, + { + "cluster_mex_ram_600m_ecc_error_interrupt_flag", + PPU_CLUSTER_CLUSTER_MEX_RAM_600M_ECC_ERROR_INTERRUPT_FLAGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4068, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 6, + g_ppu_cluster_cluster_mex_ram_600m_ecc_error_interrupt_flag_reg, + NULL, + NULL, + }, + { + "cluster_mex_ram_600m_ecc_error_interrupt_sta", + PPU_CLUSTER_CLUSTER_MEX_RAM_600M_ECC_ERROR_INTERRUPT_STAr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x406c, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 6, + g_ppu_cluster_cluster_mex_ram_600m_ecc_error_interrupt_sta_reg, + NULL, + NULL, + }, + { + "ppu_cluster_mf_in_afifo_prog_full_assert_cfg", + PPU_CLUSTER_PPU_CLUSTER_MF_IN_AFIFO_PROG_FULL_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4400, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_ppu_cluster_mf_in_afifo_prog_full_assert_cfg_reg, + NULL, + NULL, + }, + { + "ppu_cluster_mf_in_afifo_prog_full_negate_cfg", + PPU_CLUSTER_PPU_CLUSTER_MF_IN_AFIFO_PROG_FULL_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4410, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_ppu_cluster_mf_in_afifo_prog_full_negate_cfg_reg, + NULL, + NULL, + }, + { + "ese_rsp_afifo_prog_full_assert_cfg", + PPU_CLUSTER_ESE_RSP_AFIFO_PROG_FULL_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4420, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_ese_rsp_afifo_prog_full_assert_cfg_reg, + NULL, + NULL, + }, + { + "ese_rsp_afifo_prog_full_negate_cfg", + PPU_CLUSTER_ESE_RSP_AFIFO_PROG_FULL_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4430, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_ese_rsp_afifo_prog_full_negate_cfg_reg, + NULL, + NULL, + }, + { + "ise_rsp_afifo_prog_full_assert_cfg", + PPU_CLUSTER_ISE_RSP_AFIFO_PROG_FULL_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4440, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_ise_rsp_afifo_prog_full_assert_cfg_reg, + NULL, + NULL, + }, + { + "ise_rsp_afifo_prog_full_negate_cfg", + PPU_CLUSTER_ISE_RSP_AFIFO_PROG_FULL_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4450, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_ise_rsp_afifo_prog_full_negate_cfg_reg, + NULL, + NULL, + }, + { + "sta_rsp_afifo_prog_full_assert_cfg", + PPU_CLUSTER_STA_RSP_AFIFO_PROG_FULL_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4460, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_sta_rsp_afifo_prog_full_assert_cfg_reg, + NULL, + NULL, + }, + { + "sta_rsp_afifo_prog_full_negate_cfg", + PPU_CLUSTER_STA_RSP_AFIFO_PROG_FULL_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4470, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_sta_rsp_afifo_prog_full_negate_cfg_reg, + NULL, + NULL, + }, + { + "ppu_ise_key_afifo_prog_empty_assert_cfg", + PPU_CLUSTER_PPU_ISE_KEY_AFIFO_PROG_EMPTY_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4480, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_ppu_ise_key_afifo_prog_empty_assert_cfg_reg, + NULL, + NULL, + }, + { + "ppu_ise_key_afifo_prog_empty_negate_cfg", + PPU_CLUSTER_PPU_ISE_KEY_AFIFO_PROG_EMPTY_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4490, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_ppu_ise_key_afifo_prog_empty_negate_cfg_reg, + NULL, + NULL, + }, + { + "ppu_ese_key_afifo_prog_empty_assert_cfg", + PPU_CLUSTER_PPU_ESE_KEY_AFIFO_PROG_EMPTY_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x44a0, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_ppu_ese_key_afifo_prog_empty_assert_cfg_reg, + NULL, + NULL, + }, + { + "ppu_ese_key_afifo_prog_empty_negate_cfg", + PPU_CLUSTER_PPU_ESE_KEY_AFIFO_PROG_EMPTY_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x44b0, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_ppu_ese_key_afifo_prog_empty_negate_cfg_reg, + NULL, + NULL, + }, + { + "ppu_sta_key_afifo_prog_empty_assert_cfg", + PPU_CLUSTER_PPU_STA_KEY_AFIFO_PROG_EMPTY_ASSERT_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x44c0, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_ppu_sta_key_afifo_prog_empty_assert_cfg_reg, + NULL, + NULL, + }, + { + "ppu_sta_key_afifo_prog_empty_negate_cfg", + PPU_CLUSTER_PPU_STA_KEY_AFIFO_PROG_EMPTY_NEGATE_CFGr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x44d0, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_ppu_sta_key_afifo_prog_empty_negate_cfg_reg, + NULL, + NULL, + }, + { + "ppu_cluster_mf_vld_cnt_h", + PPU_CLUSTER_PPU_CLUSTER_MF_VLD_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x6000, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_ppu_cluster_mf_vld_cnt_h_reg, + NULL, + NULL, + }, + { + "ppu_cluster_mf_vld_cnt_l", + PPU_CLUSTER_PPU_CLUSTER_MF_VLD_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x6004, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_ppu_cluster_mf_vld_cnt_l_reg, + NULL, + NULL, + }, + { + "cluster_ise_key_out_vld_cnt", + PPU_CLUSTER_CLUSTER_ISE_KEY_OUT_VLD_CNTr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x6008, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_cluster_ise_key_out_vld_cnt_reg, + NULL, + NULL, + }, + { + "ise_cluster_rsp_in_vld_cnt", + PPU_CLUSTER_ISE_CLUSTER_RSP_IN_VLD_CNTr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x600c, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_ise_cluster_rsp_in_vld_cnt_reg, + NULL, + NULL, + }, + { + "cluster_ese_key_out_vld_cnt", + PPU_CLUSTER_CLUSTER_ESE_KEY_OUT_VLD_CNTr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x6010, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_cluster_ese_key_out_vld_cnt_reg, + NULL, + NULL, + }, + { + "ese_cluster_rsp_in_vld_cnt", + PPU_CLUSTER_ESE_CLUSTER_RSP_IN_VLD_CNTr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x6014, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_ese_cluster_rsp_in_vld_cnt_reg, + NULL, + NULL, + }, + { + "cluster_stat_cmd_vld_cnt", + PPU_CLUSTER_CLUSTER_STAT_CMD_VLD_CNTr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x6018, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_cluster_stat_cmd_vld_cnt_reg, + NULL, + NULL, + }, + { + "stat_cluster_rsp_vld_cnt", + PPU_CLUSTER_STAT_CLUSTER_RSP_VLD_CNTr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x601c, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_stat_cluster_rsp_vld_cnt_reg, + NULL, + NULL, + }, + { + "mex_debug_key_vld_cnt", + PPU_CLUSTER_MEX_DEBUG_KEY_VLD_CNTr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x6020, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_mex_debug_key_vld_cnt_reg, + NULL, + NULL, + }, + { + "ise_cluster_key_fc_cnt", + PPU_CLUSTER_ISE_CLUSTER_KEY_FC_CNTr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x6024, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_ise_cluster_key_fc_cnt_reg, + NULL, + NULL, + }, + { + "ese_cluster_key_fc_cnt", + PPU_CLUSTER_ESE_CLUSTER_KEY_FC_CNTr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x6028, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_ese_cluster_key_fc_cnt_reg, + NULL, + NULL, + }, + { + "cluster_ise_rsp_fc_cnt", + PPU_CLUSTER_CLUSTER_ISE_RSP_FC_CNTr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x602c, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_cluster_ise_rsp_fc_cnt_reg, + NULL, + NULL, + }, + { + "cluster_ese_rsp_fc_cnt", + PPU_CLUSTER_CLUSTER_ESE_RSP_FC_CNTr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x6030, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_cluster_ese_rsp_fc_cnt_reg, + NULL, + NULL, + }, + { + "stat_cluster_cmd_fc_cnt", + PPU_CLUSTER_STAT_CLUSTER_CMD_FC_CNTr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x6034, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_stat_cluster_cmd_fc_cnt_reg, + NULL, + NULL, + }, + { + "cluster_stat_rsp_fc_cnt", + PPU_CLUSTER_CLUSTER_STAT_RSP_FC_CNTr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x6038, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_cluster_stat_rsp_fc_cnt_reg, + NULL, + NULL, + }, + { + "cluster_ppu_mf_vld_cnt_l", + PPU_CLUSTER_CLUSTER_PPU_MF_VLD_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2000, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_cluster_ppu_mf_vld_cnt_l_reg, + NULL, + NULL, + }, + { + "cluster_ppu_mf_vld_cnt_h", + PPU_CLUSTER_CLUSTER_PPU_MF_VLD_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2004, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_cluster_ppu_mf_vld_cnt_h_reg, + NULL, + NULL, + }, + { + "cluster_cop_key_vld_cnt_l", + PPU_CLUSTER_CLUSTER_COP_KEY_VLD_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2008, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_cluster_cop_key_vld_cnt_l_reg, + NULL, + NULL, + }, + { + "cluster_cop_key_vld_cnt_h", + PPU_CLUSTER_CLUSTER_COP_KEY_VLD_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x200c, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_cluster_cop_key_vld_cnt_h_reg, + NULL, + NULL, + }, + { + "cop_cluster_rsp_vld_cnt_l", + PPU_CLUSTER_COP_CLUSTER_RSP_VLD_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2010, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_cop_cluster_rsp_vld_cnt_l_reg, + NULL, + NULL, + }, + { + "cop_cluster_rsp_vld_cnt_h", + PPU_CLUSTER_COP_CLUSTER_RSP_VLD_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2014, + (32/8), + DPP_PPU_CLUSTER_NUM, + 0, + DPP_PPU_CLUSTER_SPACE_SIZE, + 0, + 1, + g_ppu_cluster_cop_cluster_rsp_vld_cnt_h_reg, + NULL, + NULL, + }, + { + "mex_me_pkt_in_sop_cnt_l", + PPU_CLUSTER_MEX_ME_PKT_IN_SOP_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2018, + (32/8), + DPP_PPU_CLUSTER_NUM, + 7 + 1, + DPP_PPU_CLUSTER_SPACE_SIZE, + 24, + 1, + g_ppu_cluster_mex_me_pkt_in_sop_cnt_l_reg, + NULL, + NULL, + }, + { + "mex_me_pkt_in_sop_cnt_h", + PPU_CLUSTER_MEX_ME_PKT_IN_SOP_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x201c, + (32/8), + DPP_PPU_CLUSTER_NUM, + 7 + 1, + DPP_PPU_CLUSTER_SPACE_SIZE, + 24, + 1, + g_ppu_cluster_mex_me_pkt_in_sop_cnt_h_reg, + NULL, + NULL, + }, + { + "mex_me_pkt_in_eop_cnt_l", + PPU_CLUSTER_MEX_ME_PKT_IN_EOP_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2020, + (32/8), + DPP_PPU_CLUSTER_NUM, + 7 + 1, + DPP_PPU_CLUSTER_SPACE_SIZE, + 24, + 1, + g_ppu_cluster_mex_me_pkt_in_eop_cnt_l_reg, + NULL, + NULL, + }, + { + "mex_me_pkt_in_eop_cnt_h", + PPU_CLUSTER_MEX_ME_PKT_IN_EOP_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2024, + (32/8), + DPP_PPU_CLUSTER_NUM, + 7 + 1, + DPP_PPU_CLUSTER_SPACE_SIZE, + 24, + 1, + g_ppu_cluster_mex_me_pkt_in_eop_cnt_h_reg, + NULL, + NULL, + }, + { + "mex_me_pkt_in_vld_cnt_l", + PPU_CLUSTER_MEX_ME_PKT_IN_VLD_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2028, + (32/8), + DPP_PPU_CLUSTER_NUM, + 7 + 1, + DPP_PPU_CLUSTER_SPACE_SIZE, + 24, + 1, + g_ppu_cluster_mex_me_pkt_in_vld_cnt_l_reg, + NULL, + NULL, + }, + { + "mex_me_pkt_in_vld_cnt_h", + PPU_CLUSTER_MEX_ME_PKT_IN_VLD_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x202c, + (32/8), + DPP_PPU_CLUSTER_NUM, + 7 + 1, + DPP_PPU_CLUSTER_SPACE_SIZE, + 24, + 1, + g_ppu_cluster_mex_me_pkt_in_vld_cnt_h_reg, + NULL, + NULL, + }, + { + "me_mex_pkt_out_sop_cnt_l", + PPU_CLUSTER_ME_MEX_PKT_OUT_SOP_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x20d8, + (32/8), + DPP_PPU_CLUSTER_NUM, + 7 + 1, + DPP_PPU_CLUSTER_SPACE_SIZE, + 24, + 1, + g_ppu_cluster_me_mex_pkt_out_sop_cnt_l_reg, + NULL, + NULL, + }, + { + "me_mex_pkt_out_sop_cnt_h", + PPU_CLUSTER_ME_MEX_PKT_OUT_SOP_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x20dc, + (32/8), + DPP_PPU_CLUSTER_NUM, + 7 + 1, + DPP_PPU_CLUSTER_SPACE_SIZE, + 24, + 1, + g_ppu_cluster_me_mex_pkt_out_sop_cnt_h_reg, + NULL, + NULL, + }, + { + "me_mex_pkt_out_eop_cnt_l", + PPU_CLUSTER_ME_MEX_PKT_OUT_EOP_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x20e0, + (32/8), + DPP_PPU_CLUSTER_NUM, + 7 + 1, + DPP_PPU_CLUSTER_SPACE_SIZE, + 24, + 1, + g_ppu_cluster_me_mex_pkt_out_eop_cnt_l_reg, + NULL, + NULL, + }, + { + "me_mex_pkt_out_eop_cnt_h", + PPU_CLUSTER_ME_MEX_PKT_OUT_EOP_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x20e4, + (32/8), + DPP_PPU_CLUSTER_NUM, + 7 + 1, + DPP_PPU_CLUSTER_SPACE_SIZE, + 24, + 1, + g_ppu_cluster_me_mex_pkt_out_eop_cnt_h_reg, + NULL, + NULL, + }, + { + "me_mex_pkt_out_vld_cnt_l", + PPU_CLUSTER_ME_MEX_PKT_OUT_VLD_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x20e8, + (32/8), + DPP_PPU_CLUSTER_NUM, + 7 + 1, + DPP_PPU_CLUSTER_SPACE_SIZE, + 24, + 1, + g_ppu_cluster_me_mex_pkt_out_vld_cnt_l_reg, + NULL, + NULL, + }, + { + "me_mex_pkt_out_vld_cnt_h", + PPU_CLUSTER_ME_MEX_PKT_OUT_VLD_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x20ec, + (32/8), + DPP_PPU_CLUSTER_NUM, + 7 + 1, + DPP_PPU_CLUSTER_SPACE_SIZE, + 24, + 1, + g_ppu_cluster_me_mex_pkt_out_vld_cnt_h_reg, + NULL, + NULL, + }, + { + "me_mex_i_key_out_sop_cnt_l", + PPU_CLUSTER_ME_MEX_I_KEY_OUT_SOP_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2198, + (32/8), + DPP_PPU_CLUSTER_NUM, + 7 + 1, + DPP_PPU_CLUSTER_SPACE_SIZE, + 24, + 1, + g_ppu_cluster_me_mex_i_key_out_sop_cnt_l_reg, + NULL, + NULL, + }, + { + "me_mex_i_key_out_sop_cnt_h", + PPU_CLUSTER_ME_MEX_I_KEY_OUT_SOP_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x219c, + (32/8), + DPP_PPU_CLUSTER_NUM, + 7 + 1, + DPP_PPU_CLUSTER_SPACE_SIZE, + 24, + 1, + g_ppu_cluster_me_mex_i_key_out_sop_cnt_h_reg, + NULL, + NULL, + }, + { + "me_mex_i_key_out_eop_cnt_l", + PPU_CLUSTER_ME_MEX_I_KEY_OUT_EOP_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x21a0, + (32/8), + DPP_PPU_CLUSTER_NUM, + 7 + 1, + DPP_PPU_CLUSTER_SPACE_SIZE, + 24, + 1, + g_ppu_cluster_me_mex_i_key_out_eop_cnt_l_reg, + NULL, + NULL, + }, + { + "me_mex_i_key_out_eop_cnt_h", + PPU_CLUSTER_ME_MEX_I_KEY_OUT_EOP_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x21a4, + (32/8), + DPP_PPU_CLUSTER_NUM, + 7 + 1, + DPP_PPU_CLUSTER_SPACE_SIZE, + 24, + 1, + g_ppu_cluster_me_mex_i_key_out_eop_cnt_h_reg, + NULL, + NULL, + }, + { + "me_mex_i_key_out_vld_cnt_l", + PPU_CLUSTER_ME_MEX_I_KEY_OUT_VLD_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x21a8, + (32/8), + DPP_PPU_CLUSTER_NUM, + 7 + 1, + DPP_PPU_CLUSTER_SPACE_SIZE, + 24, + 1, + g_ppu_cluster_me_mex_i_key_out_vld_cnt_l_reg, + NULL, + NULL, + }, + { + "me_mex_i_key_out_vld_cnt_h", + PPU_CLUSTER_ME_MEX_I_KEY_OUT_VLD_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x21ac, + (32/8), + DPP_PPU_CLUSTER_NUM, + 7 + 1, + DPP_PPU_CLUSTER_SPACE_SIZE, + 24, + 1, + g_ppu_cluster_me_mex_i_key_out_vld_cnt_h_reg, + NULL, + NULL, + }, + { + "me_mex_e_key_out_sop_cnt_l", + PPU_CLUSTER_ME_MEX_E_KEY_OUT_SOP_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2258, + (32/8), + DPP_PPU_CLUSTER_NUM, + 7 + 1, + DPP_PPU_CLUSTER_SPACE_SIZE, + 24, + 1, + g_ppu_cluster_me_mex_e_key_out_sop_cnt_l_reg, + NULL, + NULL, + }, + { + "me_mex_e_key_out_sop_cnt_h", + PPU_CLUSTER_ME_MEX_E_KEY_OUT_SOP_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x225c, + (32/8), + DPP_PPU_CLUSTER_NUM, + 7 + 1, + DPP_PPU_CLUSTER_SPACE_SIZE, + 24, + 1, + g_ppu_cluster_me_mex_e_key_out_sop_cnt_h_reg, + NULL, + NULL, + }, + { + "me_mex_e_key_out_eop_cnt_l", + PPU_CLUSTER_ME_MEX_E_KEY_OUT_EOP_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2260, + (32/8), + DPP_PPU_CLUSTER_NUM, + 7 + 1, + DPP_PPU_CLUSTER_SPACE_SIZE, + 24, + 1, + g_ppu_cluster_me_mex_e_key_out_eop_cnt_l_reg, + NULL, + NULL, + }, + { + "me_mex_e_key_out_eop_cnt_h", + PPU_CLUSTER_ME_MEX_E_KEY_OUT_EOP_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2264, + (32/8), + DPP_PPU_CLUSTER_NUM, + 7 + 1, + DPP_PPU_CLUSTER_SPACE_SIZE, + 24, + 1, + g_ppu_cluster_me_mex_e_key_out_eop_cnt_h_reg, + NULL, + NULL, + }, + { + "me_mex_e_key_out_vld_cnt_l", + PPU_CLUSTER_ME_MEX_E_KEY_OUT_VLD_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2268, + (32/8), + DPP_PPU_CLUSTER_NUM, + 7 + 1, + DPP_PPU_CLUSTER_SPACE_SIZE, + 24, + 1, + g_ppu_cluster_me_mex_e_key_out_vld_cnt_l_reg, + NULL, + NULL, + }, + { + "me_mex_e_key_out_vld_cnt_h", + PPU_CLUSTER_ME_MEX_E_KEY_OUT_VLD_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x226c, + (32/8), + DPP_PPU_CLUSTER_NUM, + 7 + 1, + DPP_PPU_CLUSTER_SPACE_SIZE, + 24, + 1, + g_ppu_cluster_me_mex_e_key_out_vld_cnt_h_reg, + NULL, + NULL, + }, + { + "me_mex_demux_ise_key_vld_cnt_l", + PPU_CLUSTER_ME_MEX_DEMUX_ISE_KEY_VLD_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2318, + (32/8), + DPP_PPU_CLUSTER_NUM, + 7 + 1, + DPP_PPU_CLUSTER_SPACE_SIZE, + 8, + 1, + g_ppu_cluster_me_mex_demux_ise_key_vld_cnt_l_reg, + NULL, + NULL, + }, + { + "me_mex_demux_ise_key_vld_cnt_h", + PPU_CLUSTER_ME_MEX_DEMUX_ISE_KEY_VLD_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x231c, + (32/8), + DPP_PPU_CLUSTER_NUM, + 7 + 1, + DPP_PPU_CLUSTER_SPACE_SIZE, + 8, + 1, + g_ppu_cluster_me_mex_demux_ise_key_vld_cnt_h_reg, + NULL, + NULL, + }, + { + "me_mex_demux_ese_key_vld_cnt_l", + PPU_CLUSTER_ME_MEX_DEMUX_ESE_KEY_VLD_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2358, + (32/8), + DPP_PPU_CLUSTER_NUM, + 7 + 1, + DPP_PPU_CLUSTER_SPACE_SIZE, + 8, + 1, + g_ppu_cluster_me_mex_demux_ese_key_vld_cnt_l_reg, + NULL, + NULL, + }, + { + "me_mex_demux_ese_key_vld_cnt_h", + PPU_CLUSTER_ME_MEX_DEMUX_ESE_KEY_VLD_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x235c, + (32/8), + DPP_PPU_CLUSTER_NUM, + 7 + 1, + DPP_PPU_CLUSTER_SPACE_SIZE, + 8, + 1, + g_ppu_cluster_me_mex_demux_ese_key_vld_cnt_h_reg, + NULL, + NULL, + }, + { + "me_mex_demux_sta_key_vld_cnt_l", + PPU_CLUSTER_ME_MEX_DEMUX_STA_KEY_VLD_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2398, + (32/8), + DPP_PPU_CLUSTER_NUM, + 7 + 1, + DPP_PPU_CLUSTER_SPACE_SIZE, + 8, + 1, + g_ppu_cluster_me_mex_demux_sta_key_vld_cnt_l_reg, + NULL, + NULL, + }, + { + "me_mex_demux_sta_key_vld_cnt_h", + PPU_CLUSTER_ME_MEX_DEMUX_STA_KEY_VLD_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x239c, + (32/8), + DPP_PPU_CLUSTER_NUM, + 7 + 1, + DPP_PPU_CLUSTER_SPACE_SIZE, + 8, + 1, + g_ppu_cluster_me_mex_demux_sta_key_vld_cnt_h_reg, + NULL, + NULL, + }, + { + "me_mex_demux_cop_key_vld_cnt_l", + PPU_CLUSTER_ME_MEX_DEMUX_COP_KEY_VLD_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x23d8, + (32/8), + DPP_PPU_CLUSTER_NUM, + 7 + 1, + DPP_PPU_CLUSTER_SPACE_SIZE, + 8, + 1, + g_ppu_cluster_me_mex_demux_cop_key_vld_cnt_l_reg, + NULL, + NULL, + }, + { + "me_mex_demux_cop_key_vld_cnt_h", + PPU_CLUSTER_ME_MEX_DEMUX_COP_KEY_VLD_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x23dc, + (32/8), + DPP_PPU_CLUSTER_NUM, + 7 + 1, + DPP_PPU_CLUSTER_SPACE_SIZE, + 8, + 1, + g_ppu_cluster_me_mex_demux_cop_key_vld_cnt_h_reg, + NULL, + NULL, + }, + { + "mex_me_demux_ise_rsp_vld_cnt_l", + PPU_CLUSTER_MEX_ME_DEMUX_ISE_RSP_VLD_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2418, + (32/8), + DPP_PPU_CLUSTER_NUM, + 7 + 1, + DPP_PPU_CLUSTER_SPACE_SIZE, + 8, + 1, + g_ppu_cluster_mex_me_demux_ise_rsp_vld_cnt_l_reg, + NULL, + NULL, + }, + { + "mex_me_demux_ise_rsp_vld_cnt_h", + PPU_CLUSTER_MEX_ME_DEMUX_ISE_RSP_VLD_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x241c, + (32/8), + DPP_PPU_CLUSTER_NUM, + 7 + 1, + DPP_PPU_CLUSTER_SPACE_SIZE, + 8, + 1, + g_ppu_cluster_mex_me_demux_ise_rsp_vld_cnt_h_reg, + NULL, + NULL, + }, + { + "mex_me_demux_ese_rsp_vld_cnt_l", + PPU_CLUSTER_MEX_ME_DEMUX_ESE_RSP_VLD_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2458, + (32/8), + DPP_PPU_CLUSTER_NUM, + 7 + 1, + DPP_PPU_CLUSTER_SPACE_SIZE, + 8, + 1, + g_ppu_cluster_mex_me_demux_ese_rsp_vld_cnt_l_reg, + NULL, + NULL, + }, + { + "mex_me_demux_ese_rsp_vld_cnt_h", + PPU_CLUSTER_MEX_ME_DEMUX_ESE_RSP_VLD_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x245c, + (32/8), + DPP_PPU_CLUSTER_NUM, + 7 + 1, + DPP_PPU_CLUSTER_SPACE_SIZE, + 8, + 1, + g_ppu_cluster_mex_me_demux_ese_rsp_vld_cnt_h_reg, + NULL, + NULL, + }, + { + "mex_me_demux_sta_rsp_vld_cnt_l", + PPU_CLUSTER_MEX_ME_DEMUX_STA_RSP_VLD_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2498, + (32/8), + DPP_PPU_CLUSTER_NUM, + 7 + 1, + DPP_PPU_CLUSTER_SPACE_SIZE, + 8, + 1, + g_ppu_cluster_mex_me_demux_sta_rsp_vld_cnt_l_reg, + NULL, + NULL, + }, + { + "mex_me_demux_sta_rsp_vld_cnt_h", + PPU_CLUSTER_MEX_ME_DEMUX_STA_RSP_VLD_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x249c, + (32/8), + DPP_PPU_CLUSTER_NUM, + 7 + 1, + DPP_PPU_CLUSTER_SPACE_SIZE, + 8, + 1, + g_ppu_cluster_mex_me_demux_sta_rsp_vld_cnt_h_reg, + NULL, + NULL, + }, + { + "mex_me_demux_cop_rsp_vld_cnt_l", + PPU_CLUSTER_MEX_ME_DEMUX_COP_RSP_VLD_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x24d8, + (32/8), + DPP_PPU_CLUSTER_NUM, + 7 + 1, + DPP_PPU_CLUSTER_SPACE_SIZE, + 8, + 1, + g_ppu_cluster_mex_me_demux_cop_rsp_vld_cnt_l_reg, + NULL, + NULL, + }, + { + "mex_me_demux_cop_rsp_vld_cnt_h", + PPU_CLUSTER_MEX_ME_DEMUX_COP_RSP_VLD_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x24dc, + (32/8), + DPP_PPU_CLUSTER_NUM, + 7 + 1, + DPP_PPU_CLUSTER_SPACE_SIZE, + 8, + 1, + g_ppu_cluster_mex_me_demux_cop_rsp_vld_cnt_h_reg, + NULL, + NULL, + }, + { + "me_exception_code0_cnt_l", + PPU_CLUSTER_ME_EXCEPTION_CODE0_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2518, + (32/8), + DPP_PPU_CLUSTER_NUM, + 7 + 1, + DPP_PPU_CLUSTER_SPACE_SIZE, + 24, + 1, + g_ppu_cluster_me_exception_code0_cnt_l_reg, + NULL, + NULL, + }, + { + "me_exception_code0_cnt_h", + PPU_CLUSTER_ME_EXCEPTION_CODE0_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x251c, + (32/8), + DPP_PPU_CLUSTER_NUM, + 7 + 1, + DPP_PPU_CLUSTER_SPACE_SIZE, + 24, + 1, + g_ppu_cluster_me_exception_code0_cnt_h_reg, + NULL, + NULL, + }, + { + "me_exception_code1_cnt_l", + PPU_CLUSTER_ME_EXCEPTION_CODE1_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2520, + (32/8), + DPP_PPU_CLUSTER_NUM, + 7 + 1, + DPP_PPU_CLUSTER_SPACE_SIZE, + 24, + 1, + g_ppu_cluster_me_exception_code1_cnt_l_reg, + NULL, + NULL, + }, + { + "me_exception_code1_cnt_h", + PPU_CLUSTER_ME_EXCEPTION_CODE1_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2524, + (32/8), + DPP_PPU_CLUSTER_NUM, + 7 + 1, + DPP_PPU_CLUSTER_SPACE_SIZE, + 24, + 1, + g_ppu_cluster_me_exception_code1_cnt_h_reg, + NULL, + NULL, + }, + { + "me_exception_code2_cnt_l", + PPU_CLUSTER_ME_EXCEPTION_CODE2_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2528, + (32/8), + DPP_PPU_CLUSTER_NUM, + 7 + 1, + DPP_PPU_CLUSTER_SPACE_SIZE, + 24, + 1, + g_ppu_cluster_me_exception_code2_cnt_l_reg, + NULL, + NULL, + }, + { + "me_exception_code2_cnt_h", + PPU_CLUSTER_ME_EXCEPTION_CODE2_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x252c, + (32/8), + DPP_PPU_CLUSTER_NUM, + 7 + 1, + DPP_PPU_CLUSTER_SPACE_SIZE, + 24, + 1, + g_ppu_cluster_me_exception_code2_cnt_h_reg, + NULL, + NULL, + }, + { + "me_exception_code3_cnt_l", + PPU_CLUSTER_ME_EXCEPTION_CODE3_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x25d8, + (32/8), + DPP_PPU_CLUSTER_NUM, + 7 + 1, + DPP_PPU_CLUSTER_SPACE_SIZE, + 24, + 1, + g_ppu_cluster_me_exception_code3_cnt_l_reg, + NULL, + NULL, + }, + { + "me_exception_code3_cnt_h", + PPU_CLUSTER_ME_EXCEPTION_CODE3_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x25dc, + (32/8), + DPP_PPU_CLUSTER_NUM, + 7 + 1, + DPP_PPU_CLUSTER_SPACE_SIZE, + 24, + 1, + g_ppu_cluster_me_exception_code3_cnt_h_reg, + NULL, + NULL, + }, + { + "me_exception_code4_cnt_l", + PPU_CLUSTER_ME_EXCEPTION_CODE4_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x25e0, + (32/8), + DPP_PPU_CLUSTER_NUM, + 7 + 1, + DPP_PPU_CLUSTER_SPACE_SIZE, + 24, + 1, + g_ppu_cluster_me_exception_code4_cnt_l_reg, + NULL, + NULL, + }, + { + "me_exception_code4_cnt_h", + PPU_CLUSTER_ME_EXCEPTION_CODE4_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x25e4, + (32/8), + DPP_PPU_CLUSTER_NUM, + 7 + 1, + DPP_PPU_CLUSTER_SPACE_SIZE, + 24, + 1, + g_ppu_cluster_me_exception_code4_cnt_h_reg, + NULL, + NULL, + }, + { + "me_exception_code5_cnt_l", + PPU_CLUSTER_ME_EXCEPTION_CODE5_CNT_Lr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x25e8, + (32/8), + DPP_PPU_CLUSTER_NUM, + 7 + 1, + DPP_PPU_CLUSTER_SPACE_SIZE, + 24, + 1, + g_ppu_cluster_me_exception_code5_cnt_l_reg, + NULL, + NULL, + }, + { + "me_exception_code5_cnt_h", + PPU_CLUSTER_ME_EXCEPTION_CODE5_CNT_Hr, + PPU, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x25ec, + (32/8), + DPP_PPU_CLUSTER_NUM, + 7 + 1, + DPP_PPU_CLUSTER_SPACE_SIZE, + 24, + 1, + g_ppu_cluster_me_exception_code5_cnt_h_reg, + NULL, + NULL, + }, + { + "ppu_soft_rst", + SE_CFG_PPU_SOFT_RSTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000000, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_ppu_soft_rst_reg, + NULL, + NULL, + }, + { + "ept_flag", + SE_CFG_EPT_FLAGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000004, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_ept_flag_reg, + NULL, + NULL, + }, + { + "ddr_key_lk0_3", + SE_CFG_DDR_KEY_LK0_3r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000020, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_ddr_key_lk0_3_reg, + NULL, + NULL, + }, + { + "ddr_key_lk0_2", + SE_CFG_DDR_KEY_LK0_2r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000024, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_ddr_key_lk0_2_reg, + NULL, + NULL, + }, + { + "ddr_key_lk0_1", + SE_CFG_DDR_KEY_LK0_1r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000028, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_ddr_key_lk0_1_reg, + NULL, + NULL, + }, + { + "ddr_key_lk0_0", + SE_CFG_DDR_KEY_LK0_0r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000002c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_ddr_key_lk0_0_reg, + NULL, + NULL, + }, + { + "ddr_key_lk1_3", + SE_CFG_DDR_KEY_LK1_3r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000030, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_ddr_key_lk1_3_reg, + NULL, + NULL, + }, + { + "ddr_key_lk1_2", + SE_CFG_DDR_KEY_LK1_2r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000034, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_ddr_key_lk1_2_reg, + NULL, + NULL, + }, + { + "ddr_key_lk1_1", + SE_CFG_DDR_KEY_LK1_1r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000038, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_ddr_key_lk1_1_reg, + NULL, + NULL, + }, + { + "ddr_key_lk1_0", + SE_CFG_DDR_KEY_LK1_0r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000003c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_ddr_key_lk1_0_reg, + NULL, + NULL, + }, + { + "hash_key_lk0_18", + SE_CFG_HASH_KEY_LK0_18r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000080, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk0_18_reg, + NULL, + NULL, + }, + { + "hash_key_lk0_17", + SE_CFG_HASH_KEY_LK0_17r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000084, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk0_17_reg, + NULL, + NULL, + }, + { + "hash_key_lk0_16", + SE_CFG_HASH_KEY_LK0_16r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000088, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk0_16_reg, + NULL, + NULL, + }, + { + "hash_key_lk0_15", + SE_CFG_HASH_KEY_LK0_15r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000008c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk0_15_reg, + NULL, + NULL, + }, + { + "hash_key_lk0_14", + SE_CFG_HASH_KEY_LK0_14r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000090, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk0_14_reg, + NULL, + NULL, + }, + { + "hash_key_lk0_13", + SE_CFG_HASH_KEY_LK0_13r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000094, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk0_13_reg, + NULL, + NULL, + }, + { + "hash_key_lk0_12", + SE_CFG_HASH_KEY_LK0_12r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000098, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk0_12_reg, + NULL, + NULL, + }, + { + "hash_key_lk0_11", + SE_CFG_HASH_KEY_LK0_11r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000009c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk0_11_reg, + NULL, + NULL, + }, + { + "hash_key_lk0_10", + SE_CFG_HASH_KEY_LK0_10r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000a0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk0_10_reg, + NULL, + NULL, + }, + { + "hash_key_lk0_9", + SE_CFG_HASH_KEY_LK0_9r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000a4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk0_9_reg, + NULL, + NULL, + }, + { + "hash_key_lk0_8", + SE_CFG_HASH_KEY_LK0_8r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000a8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk0_8_reg, + NULL, + NULL, + }, + { + "hash_key_lk0_7", + SE_CFG_HASH_KEY_LK0_7r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000ac, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk0_7_reg, + NULL, + NULL, + }, + { + "hash_key_lk0_6", + SE_CFG_HASH_KEY_LK0_6r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000b0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk0_6_reg, + NULL, + NULL, + }, + { + "hash_key_lk0_5", + SE_CFG_HASH_KEY_LK0_5r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000b4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk0_5_reg, + NULL, + NULL, + }, + { + "hash_key_lk0_4", + SE_CFG_HASH_KEY_LK0_4r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000b8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk0_4_reg, + NULL, + NULL, + }, + { + "hash_key_lk0_3", + SE_CFG_HASH_KEY_LK0_3r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000bc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk0_3_reg, + NULL, + NULL, + }, + { + "hash_key_lk0_2", + SE_CFG_HASH_KEY_LK0_2r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000c0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk0_2_reg, + NULL, + NULL, + }, + { + "hash_key_lk0_1", + SE_CFG_HASH_KEY_LK0_1r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000c4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk0_1_reg, + NULL, + NULL, + }, + { + "hash_key_lk0_0", + SE_CFG_HASH_KEY_LK0_0r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000c8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk0_0_reg, + NULL, + NULL, + }, + { + "hash_key_lk1_18", + SE_CFG_HASH_KEY_LK1_18r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000cc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk1_18_reg, + NULL, + NULL, + }, + { + "hash_key_lk1_17", + SE_CFG_HASH_KEY_LK1_17r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000d0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk1_17_reg, + NULL, + NULL, + }, + { + "hash_key_lk1_16", + SE_CFG_HASH_KEY_LK1_16r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000d4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk1_16_reg, + NULL, + NULL, + }, + { + "hash_key_lk1_15", + SE_CFG_HASH_KEY_LK1_15r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000d8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk1_15_reg, + NULL, + NULL, + }, + { + "hash_key_lk1_14", + SE_CFG_HASH_KEY_LK1_14r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000dc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk1_14_reg, + NULL, + NULL, + }, + { + "hash_key_lk1_13", + SE_CFG_HASH_KEY_LK1_13r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000e0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk1_13_reg, + NULL, + NULL, + }, + { + "hash_key_lk1_12", + SE_CFG_HASH_KEY_LK1_12r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000e4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk1_12_reg, + NULL, + NULL, + }, + { + "hash_key_lk1_11", + SE_CFG_HASH_KEY_LK1_11r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000e8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk1_11_reg, + NULL, + NULL, + }, + { + "hash_key_lk1_10", + SE_CFG_HASH_KEY_LK1_10r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000ec, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk1_10_reg, + NULL, + NULL, + }, + { + "hash_key_lk1_9", + SE_CFG_HASH_KEY_LK1_9r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000f0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk1_9_reg, + NULL, + NULL, + }, + { + "hash_key_lk1_8", + SE_CFG_HASH_KEY_LK1_8r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000f4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk1_8_reg, + NULL, + NULL, + }, + { + "hash_key_lk1_7", + SE_CFG_HASH_KEY_LK1_7r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000f8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk1_7_reg, + NULL, + NULL, + }, + { + "hash_key_lk1_6", + SE_CFG_HASH_KEY_LK1_6r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000fc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk1_6_reg, + NULL, + NULL, + }, + { + "hash_key_lk1_5", + SE_CFG_HASH_KEY_LK1_5r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000100, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk1_5_reg, + NULL, + NULL, + }, + { + "hash_key_lk1_4", + SE_CFG_HASH_KEY_LK1_4r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000104, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk1_4_reg, + NULL, + NULL, + }, + { + "hash_key_lk1_3", + SE_CFG_HASH_KEY_LK1_3r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000108, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk1_3_reg, + NULL, + NULL, + }, + { + "hash_key_lk1_2", + SE_CFG_HASH_KEY_LK1_2r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000010c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk1_2_reg, + NULL, + NULL, + }, + { + "hash_key_lk1_1", + SE_CFG_HASH_KEY_LK1_1r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000110, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk1_1_reg, + NULL, + NULL, + }, + { + "hash_key_lk1_0", + SE_CFG_HASH_KEY_LK1_0r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000114, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk1_0_reg, + NULL, + NULL, + }, + { + "hash_key_lk2_18", + SE_CFG_HASH_KEY_LK2_18r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000118, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk2_18_reg, + NULL, + NULL, + }, + { + "hash_key_lk2_17", + SE_CFG_HASH_KEY_LK2_17r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000011c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk2_17_reg, + NULL, + NULL, + }, + { + "hash_key_lk2_16", + SE_CFG_HASH_KEY_LK2_16r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000120, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk2_16_reg, + NULL, + NULL, + }, + { + "hash_key_lk2_15", + SE_CFG_HASH_KEY_LK2_15r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000124, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk2_15_reg, + NULL, + NULL, + }, + { + "hash_key_lk2_14", + SE_CFG_HASH_KEY_LK2_14r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000128, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk2_14_reg, + NULL, + NULL, + }, + { + "hash_key_lk2_13", + SE_CFG_HASH_KEY_LK2_13r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000012c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk2_13_reg, + NULL, + NULL, + }, + { + "hash_key_lk2_12", + SE_CFG_HASH_KEY_LK2_12r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000130, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk2_12_reg, + NULL, + NULL, + }, + { + "hash_key_lk2_11", + SE_CFG_HASH_KEY_LK2_11r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000134, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk2_11_reg, + NULL, + NULL, + }, + { + "hash_key_lk2_10", + SE_CFG_HASH_KEY_LK2_10r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000138, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk2_10_reg, + NULL, + NULL, + }, + { + "hash_key_lk2_9", + SE_CFG_HASH_KEY_LK2_9r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000013c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk2_9_reg, + NULL, + NULL, + }, + { + "hash_key_lk2_8", + SE_CFG_HASH_KEY_LK2_8r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000140, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk2_8_reg, + NULL, + NULL, + }, + { + "hash_key_lk2_7", + SE_CFG_HASH_KEY_LK2_7r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000144, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk2_7_reg, + NULL, + NULL, + }, + { + "hash_key_lk2_6", + SE_CFG_HASH_KEY_LK2_6r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000148, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk2_6_reg, + NULL, + NULL, + }, + { + "hash_key_lk2_5", + SE_CFG_HASH_KEY_LK2_5r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000014c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk2_5_reg, + NULL, + NULL, + }, + { + "hash_key_lk2_4", + SE_CFG_HASH_KEY_LK2_4r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000150, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk2_4_reg, + NULL, + NULL, + }, + { + "hash_key_lk2_3", + SE_CFG_HASH_KEY_LK2_3r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000154, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk2_3_reg, + NULL, + NULL, + }, + { + "hash_key_lk2_2", + SE_CFG_HASH_KEY_LK2_2r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000158, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk2_2_reg, + NULL, + NULL, + }, + { + "hash_key_lk2_1", + SE_CFG_HASH_KEY_LK2_1r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000015c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk2_1_reg, + NULL, + NULL, + }, + { + "hash_key_lk2_0", + SE_CFG_HASH_KEY_LK2_0r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000160, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk2_0_reg, + NULL, + NULL, + }, + { + "hash_key_lk3_18", + SE_CFG_HASH_KEY_LK3_18r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000164, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk3_18_reg, + NULL, + NULL, + }, + { + "hash_key_lk3_17", + SE_CFG_HASH_KEY_LK3_17r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000168, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk3_17_reg, + NULL, + NULL, + }, + { + "hash_key_lk3_16", + SE_CFG_HASH_KEY_LK3_16r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000016c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk3_16_reg, + NULL, + NULL, + }, + { + "hash_key_lk3_15", + SE_CFG_HASH_KEY_LK3_15r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000170, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk3_15_reg, + NULL, + NULL, + }, + { + "hash_key_lk3_14", + SE_CFG_HASH_KEY_LK3_14r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000174, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk3_14_reg, + NULL, + NULL, + }, + { + "hash_key_lk3_13", + SE_CFG_HASH_KEY_LK3_13r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000178, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk3_13_reg, + NULL, + NULL, + }, + { + "hash_key_lk3_12", + SE_CFG_HASH_KEY_LK3_12r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000017c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk3_12_reg, + NULL, + NULL, + }, + { + "hash_key_lk3_11", + SE_CFG_HASH_KEY_LK3_11r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000180, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk3_11_reg, + NULL, + NULL, + }, + { + "hash_key_lk3_10", + SE_CFG_HASH_KEY_LK3_10r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000184, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk3_10_reg, + NULL, + NULL, + }, + { + "hash_key_lk3_9", + SE_CFG_HASH_KEY_LK3_9r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000188, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk3_9_reg, + NULL, + NULL, + }, + { + "hash_key_lk3_8", + SE_CFG_HASH_KEY_LK3_8r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000018c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk3_8_reg, + NULL, + NULL, + }, + { + "hash_key_lk3_7", + SE_CFG_HASH_KEY_LK3_7r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000190, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk3_7_reg, + NULL, + NULL, + }, + { + "hash_key_lk3_6", + SE_CFG_HASH_KEY_LK3_6r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000194, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk3_6_reg, + NULL, + NULL, + }, + { + "hash_key_lk3_5", + SE_CFG_HASH_KEY_LK3_5r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000198, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk3_5_reg, + NULL, + NULL, + }, + { + "hash_key_lk3_4", + SE_CFG_HASH_KEY_LK3_4r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000019c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk3_4_reg, + NULL, + NULL, + }, + { + "hash_key_lk3_3", + SE_CFG_HASH_KEY_LK3_3r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000001a0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk3_3_reg, + NULL, + NULL, + }, + { + "hash_key_lk3_2", + SE_CFG_HASH_KEY_LK3_2r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000001a4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk3_2_reg, + NULL, + NULL, + }, + { + "hash_key_lk3_1", + SE_CFG_HASH_KEY_LK3_1r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000001a8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk3_1_reg, + NULL, + NULL, + }, + { + "hash_key_lk3_0", + SE_CFG_HASH_KEY_LK3_0r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000001ac, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_hash_key_lk3_0_reg, + NULL, + NULL, + }, + { + "lpm_key_lk0_6", + SE_CFG_LPM_KEY_LK0_6r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000002e0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_lpm_key_lk0_6_reg, + NULL, + NULL, + }, + { + "lpm_key_lk0_5", + SE_CFG_LPM_KEY_LK0_5r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000002e4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_lpm_key_lk0_5_reg, + NULL, + NULL, + }, + { + "lpm_key_lk0_4", + SE_CFG_LPM_KEY_LK0_4r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000002e8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_lpm_key_lk0_4_reg, + NULL, + NULL, + }, + { + "lpm_key_lk0_3", + SE_CFG_LPM_KEY_LK0_3r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000002ec, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_lpm_key_lk0_3_reg, + NULL, + NULL, + }, + { + "lpm_key_lk0_2", + SE_CFG_LPM_KEY_LK0_2r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000002f0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_lpm_key_lk0_2_reg, + NULL, + NULL, + }, + { + "lpm_key_lk0_1", + SE_CFG_LPM_KEY_LK0_1r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000002f4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_lpm_key_lk0_1_reg, + NULL, + NULL, + }, + { + "lpm_key_lk0_0", + SE_CFG_LPM_KEY_LK0_0r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000002f8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_lpm_key_lk0_0_reg, + NULL, + NULL, + }, + { + "lpm_key_lk1_6", + SE_CFG_LPM_KEY_LK1_6r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000002fc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_lpm_key_lk1_6_reg, + NULL, + NULL, + }, + { + "lpm_key_lk1_5", + SE_CFG_LPM_KEY_LK1_5r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000300, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_lpm_key_lk1_5_reg, + NULL, + NULL, + }, + { + "lpm_key_lk1_4", + SE_CFG_LPM_KEY_LK1_4r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000304, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_lpm_key_lk1_4_reg, + NULL, + NULL, + }, + { + "lpm_key_lk1_3", + SE_CFG_LPM_KEY_LK1_3r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000308, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_lpm_key_lk1_3_reg, + NULL, + NULL, + }, + { + "lpm_key_lk1_2", + SE_CFG_LPM_KEY_LK1_2r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000030c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_lpm_key_lk1_2_reg, + NULL, + NULL, + }, + { + "lpm_key_lk1_1", + SE_CFG_LPM_KEY_LK1_1r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000310, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_lpm_key_lk1_1_reg, + NULL, + NULL, + }, + { + "lpm_key_lk1_0", + SE_CFG_LPM_KEY_LK1_0r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000314, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_lpm_key_lk1_0_reg, + NULL, + NULL, + }, + { + "lpm_key_lk2_6", + SE_CFG_LPM_KEY_LK2_6r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000318, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_lpm_key_lk2_6_reg, + NULL, + NULL, + }, + { + "lpm_key_lk2_5", + SE_CFG_LPM_KEY_LK2_5r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000031c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_lpm_key_lk2_5_reg, + NULL, + NULL, + }, + { + "lpm_key_lk2_4", + SE_CFG_LPM_KEY_LK2_4r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000320, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_lpm_key_lk2_4_reg, + NULL, + NULL, + }, + { + "lpm_key_lk2_3", + SE_CFG_LPM_KEY_LK2_3r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000324, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_lpm_key_lk2_3_reg, + NULL, + NULL, + }, + { + "lpm_key_lk2_2", + SE_CFG_LPM_KEY_LK2_2r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000328, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_lpm_key_lk2_2_reg, + NULL, + NULL, + }, + { + "lpm_key_lk2_1", + SE_CFG_LPM_KEY_LK2_1r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000032c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_lpm_key_lk2_1_reg, + NULL, + NULL, + }, + { + "lpm_key_lk2_0", + SE_CFG_LPM_KEY_LK2_0r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000330, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_lpm_key_lk2_0_reg, + NULL, + NULL, + }, + { + "lpm_key_lk3_6", + SE_CFG_LPM_KEY_LK3_6r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000334, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_lpm_key_lk3_6_reg, + NULL, + NULL, + }, + { + "lpm_key_lk3_5", + SE_CFG_LPM_KEY_LK3_5r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000338, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_lpm_key_lk3_5_reg, + NULL, + NULL, + }, + { + "lpm_key_lk3_4", + SE_CFG_LPM_KEY_LK3_4r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000033c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_lpm_key_lk3_4_reg, + NULL, + NULL, + }, + { + "lpm_key_lk3_3", + SE_CFG_LPM_KEY_LK3_3r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000340, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_lpm_key_lk3_3_reg, + NULL, + NULL, + }, + { + "lpm_key_lk3_2", + SE_CFG_LPM_KEY_LK3_2r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000344, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_lpm_key_lk3_2_reg, + NULL, + NULL, + }, + { + "lpm_key_lk3_1", + SE_CFG_LPM_KEY_LK3_1r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000348, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_lpm_key_lk3_1_reg, + NULL, + NULL, + }, + { + "lpm_key_lk3_0", + SE_CFG_LPM_KEY_LK3_0r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000034c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_lpm_key_lk3_0_reg, + NULL, + NULL, + }, + { + "etcam_key_lk0_22", + SE_CFG_ETCAM_KEY_LK0_22r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000003c0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk0_22_reg, + NULL, + NULL, + }, + { + "etcam_key_lk0_21", + SE_CFG_ETCAM_KEY_LK0_21r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000003c4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk0_21_reg, + NULL, + NULL, + }, + { + "etcam_key_lk0_20", + SE_CFG_ETCAM_KEY_LK0_20r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000003c8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk0_20_reg, + NULL, + NULL, + }, + { + "etcam_key_lk0_19", + SE_CFG_ETCAM_KEY_LK0_19r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000003cc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk0_19_reg, + NULL, + NULL, + }, + { + "etcam_key_lk0_18", + SE_CFG_ETCAM_KEY_LK0_18r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000003d0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk0_18_reg, + NULL, + NULL, + }, + { + "etcam_key_lk0_17", + SE_CFG_ETCAM_KEY_LK0_17r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000003d4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk0_17_reg, + NULL, + NULL, + }, + { + "etcam_key_lk0_16", + SE_CFG_ETCAM_KEY_LK0_16r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000003d8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk0_16_reg, + NULL, + NULL, + }, + { + "etcam_key_lk0_15", + SE_CFG_ETCAM_KEY_LK0_15r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000003dc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk0_15_reg, + NULL, + NULL, + }, + { + "etcam_key_lk0_14", + SE_CFG_ETCAM_KEY_LK0_14r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000003e0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk0_14_reg, + NULL, + NULL, + }, + { + "etcam_key_lk0_13", + SE_CFG_ETCAM_KEY_LK0_13r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000003e4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk0_13_reg, + NULL, + NULL, + }, + { + "etcam_key_lk0_12", + SE_CFG_ETCAM_KEY_LK0_12r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000003e8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk0_12_reg, + NULL, + NULL, + }, + { + "etcam_key_lk0_11", + SE_CFG_ETCAM_KEY_LK0_11r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000003ec, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk0_11_reg, + NULL, + NULL, + }, + { + "etcam_key_lk0_10", + SE_CFG_ETCAM_KEY_LK0_10r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000003f0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk0_10_reg, + NULL, + NULL, + }, + { + "etcam_key_lk0_9", + SE_CFG_ETCAM_KEY_LK0_9r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000003f4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk0_9_reg, + NULL, + NULL, + }, + { + "etcam_key_lk0_8", + SE_CFG_ETCAM_KEY_LK0_8r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000003f8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk0_8_reg, + NULL, + NULL, + }, + { + "etcam_key_lk0_7", + SE_CFG_ETCAM_KEY_LK0_7r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000003fc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk0_7_reg, + NULL, + NULL, + }, + { + "etcam_key_lk0_6", + SE_CFG_ETCAM_KEY_LK0_6r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000400, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk0_6_reg, + NULL, + NULL, + }, + { + "etcam_key_lk0_5", + SE_CFG_ETCAM_KEY_LK0_5r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000404, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk0_5_reg, + NULL, + NULL, + }, + { + "etcam_key_lk0_4", + SE_CFG_ETCAM_KEY_LK0_4r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000408, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk0_4_reg, + NULL, + NULL, + }, + { + "etcam_key_lk0_3", + SE_CFG_ETCAM_KEY_LK0_3r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000040c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk0_3_reg, + NULL, + NULL, + }, + { + "etcam_key_lk0_2", + SE_CFG_ETCAM_KEY_LK0_2r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000410, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk0_2_reg, + NULL, + NULL, + }, + { + "etcam_key_lk0_1", + SE_CFG_ETCAM_KEY_LK0_1r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000414, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk0_1_reg, + NULL, + NULL, + }, + { + "etcam_key_lk0_0", + SE_CFG_ETCAM_KEY_LK0_0r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000418, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk0_0_reg, + NULL, + NULL, + }, + { + "etcam_key_lk1_22", + SE_CFG_ETCAM_KEY_LK1_22r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000041c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk1_22_reg, + NULL, + NULL, + }, + { + "etcam_key_lk1_21", + SE_CFG_ETCAM_KEY_LK1_21r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000420, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk1_21_reg, + NULL, + NULL, + }, + { + "etcam_key_lk1_20", + SE_CFG_ETCAM_KEY_LK1_20r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000424, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk1_20_reg, + NULL, + NULL, + }, + { + "etcam_key_lk1_19", + SE_CFG_ETCAM_KEY_LK1_19r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000428, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk1_19_reg, + NULL, + NULL, + }, + { + "etcam_key_lk1_18", + SE_CFG_ETCAM_KEY_LK1_18r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000042c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk1_18_reg, + NULL, + NULL, + }, + { + "etcam_key_lk1_17", + SE_CFG_ETCAM_KEY_LK1_17r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000430, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk1_17_reg, + NULL, + NULL, + }, + { + "etcam_key_lk1_16", + SE_CFG_ETCAM_KEY_LK1_16r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000434, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk1_16_reg, + NULL, + NULL, + }, + { + "etcam_key_lk1_15", + SE_CFG_ETCAM_KEY_LK1_15r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000438, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk1_15_reg, + NULL, + NULL, + }, + { + "etcam_key_lk1_14", + SE_CFG_ETCAM_KEY_LK1_14r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000043c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk1_14_reg, + NULL, + NULL, + }, + { + "etcam_key_lk1_13", + SE_CFG_ETCAM_KEY_LK1_13r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000440, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk1_13_reg, + NULL, + NULL, + }, + { + "etcam_key_lk1_12", + SE_CFG_ETCAM_KEY_LK1_12r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000444, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk1_12_reg, + NULL, + NULL, + }, + { + "etcam_key_lk1_11", + SE_CFG_ETCAM_KEY_LK1_11r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000448, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk1_11_reg, + NULL, + NULL, + }, + { + "etcam_key_lk1_10", + SE_CFG_ETCAM_KEY_LK1_10r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000044c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk1_10_reg, + NULL, + NULL, + }, + { + "etcam_key_lk1_9", + SE_CFG_ETCAM_KEY_LK1_9r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000450, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk1_9_reg, + NULL, + NULL, + }, + { + "etcam_key_lk1_8", + SE_CFG_ETCAM_KEY_LK1_8r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000454, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk1_8_reg, + NULL, + NULL, + }, + { + "etcam_key_lk1_7", + SE_CFG_ETCAM_KEY_LK1_7r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000458, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk1_7_reg, + NULL, + NULL, + }, + { + "etcam_key_lk1_6", + SE_CFG_ETCAM_KEY_LK1_6r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000045c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk1_6_reg, + NULL, + NULL, + }, + { + "etcam_key_lk1_5", + SE_CFG_ETCAM_KEY_LK1_5r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000460, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk1_5_reg, + NULL, + NULL, + }, + { + "etcam_key_lk1_4", + SE_CFG_ETCAM_KEY_LK1_4r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000464, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk1_4_reg, + NULL, + NULL, + }, + { + "etcam_key_lk1_3", + SE_CFG_ETCAM_KEY_LK1_3r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000468, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk1_3_reg, + NULL, + NULL, + }, + { + "etcam_key_lk1_2", + SE_CFG_ETCAM_KEY_LK1_2r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000046c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk1_2_reg, + NULL, + NULL, + }, + { + "etcam_key_lk1_1", + SE_CFG_ETCAM_KEY_LK1_1r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000470, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk1_1_reg, + NULL, + NULL, + }, + { + "etcam_key_lk1_0", + SE_CFG_ETCAM_KEY_LK1_0r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000474, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk1_0_reg, + NULL, + NULL, + }, + { + "etcam_key_lk2_22", + SE_CFG_ETCAM_KEY_LK2_22r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000478, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk2_22_reg, + NULL, + NULL, + }, + { + "etcam_key_lk2_21", + SE_CFG_ETCAM_KEY_LK2_21r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000047c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk2_21_reg, + NULL, + NULL, + }, + { + "etcam_key_lk2_20", + SE_CFG_ETCAM_KEY_LK2_20r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000480, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk2_20_reg, + NULL, + NULL, + }, + { + "etcam_key_lk2_19", + SE_CFG_ETCAM_KEY_LK2_19r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000484, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk2_19_reg, + NULL, + NULL, + }, + { + "etcam_key_lk2_18", + SE_CFG_ETCAM_KEY_LK2_18r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000488, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk2_18_reg, + NULL, + NULL, + }, + { + "etcam_key_lk2_17", + SE_CFG_ETCAM_KEY_LK2_17r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000048c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk2_17_reg, + NULL, + NULL, + }, + { + "etcam_key_lk2_16", + SE_CFG_ETCAM_KEY_LK2_16r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000490, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk2_16_reg, + NULL, + NULL, + }, + { + "etcam_key_lk2_15", + SE_CFG_ETCAM_KEY_LK2_15r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000494, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk2_15_reg, + NULL, + NULL, + }, + { + "etcam_key_lk2_14", + SE_CFG_ETCAM_KEY_LK2_14r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000498, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk2_14_reg, + NULL, + NULL, + }, + { + "etcam_key_lk2_13", + SE_CFG_ETCAM_KEY_LK2_13r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000049c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk2_13_reg, + NULL, + NULL, + }, + { + "etcam_key_lk2_12", + SE_CFG_ETCAM_KEY_LK2_12r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004a0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk2_12_reg, + NULL, + NULL, + }, + { + "etcam_key_lk2_11", + SE_CFG_ETCAM_KEY_LK2_11r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004a4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk2_11_reg, + NULL, + NULL, + }, + { + "etcam_key_lk2_10", + SE_CFG_ETCAM_KEY_LK2_10r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004a8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk2_10_reg, + NULL, + NULL, + }, + { + "etcam_key_lk2_9", + SE_CFG_ETCAM_KEY_LK2_9r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004ac, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk2_9_reg, + NULL, + NULL, + }, + { + "etcam_key_lk2_8", + SE_CFG_ETCAM_KEY_LK2_8r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004b0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk2_8_reg, + NULL, + NULL, + }, + { + "etcam_key_lk2_7", + SE_CFG_ETCAM_KEY_LK2_7r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004b4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk2_7_reg, + NULL, + NULL, + }, + { + "etcam_key_lk2_6", + SE_CFG_ETCAM_KEY_LK2_6r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004b8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk2_6_reg, + NULL, + NULL, + }, + { + "etcam_key_lk2_5", + SE_CFG_ETCAM_KEY_LK2_5r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004bc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk2_5_reg, + NULL, + NULL, + }, + { + "etcam_key_lk2_4", + SE_CFG_ETCAM_KEY_LK2_4r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004c0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk2_4_reg, + NULL, + NULL, + }, + { + "etcam_key_lk2_3", + SE_CFG_ETCAM_KEY_LK2_3r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004c4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk2_3_reg, + NULL, + NULL, + }, + { + "etcam_key_lk2_2", + SE_CFG_ETCAM_KEY_LK2_2r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004c8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk2_2_reg, + NULL, + NULL, + }, + { + "etcam_key_lk2_1", + SE_CFG_ETCAM_KEY_LK2_1r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004cc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk2_1_reg, + NULL, + NULL, + }, + { + "etcam_key_lk2_0", + SE_CFG_ETCAM_KEY_LK2_0r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004d0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk2_0_reg, + NULL, + NULL, + }, + { + "etcam_key_lk3_22", + SE_CFG_ETCAM_KEY_LK3_22r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004d4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk3_22_reg, + NULL, + NULL, + }, + { + "etcam_key_lk3_21", + SE_CFG_ETCAM_KEY_LK3_21r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004d8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk3_21_reg, + NULL, + NULL, + }, + { + "etcam_key_lk3_20", + SE_CFG_ETCAM_KEY_LK3_20r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004dc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk3_20_reg, + NULL, + NULL, + }, + { + "etcam_key_lk3_19", + SE_CFG_ETCAM_KEY_LK3_19r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004e0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk3_19_reg, + NULL, + NULL, + }, + { + "etcam_key_lk3_18", + SE_CFG_ETCAM_KEY_LK3_18r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004e4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk3_18_reg, + NULL, + NULL, + }, + { + "etcam_key_lk3_17", + SE_CFG_ETCAM_KEY_LK3_17r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004e8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk3_17_reg, + NULL, + NULL, + }, + { + "etcam_key_lk3_16", + SE_CFG_ETCAM_KEY_LK3_16r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004ec, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk3_16_reg, + NULL, + NULL, + }, + { + "etcam_key_lk3_15", + SE_CFG_ETCAM_KEY_LK3_15r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004f0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk3_15_reg, + NULL, + NULL, + }, + { + "etcam_key_lk3_14", + SE_CFG_ETCAM_KEY_LK3_14r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004f4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk3_14_reg, + NULL, + NULL, + }, + { + "etcam_key_lk3_13", + SE_CFG_ETCAM_KEY_LK3_13r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004f8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk3_13_reg, + NULL, + NULL, + }, + { + "etcam_key_lk3_12", + SE_CFG_ETCAM_KEY_LK3_12r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004fc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk3_12_reg, + NULL, + NULL, + }, + { + "etcam_key_lk3_11", + SE_CFG_ETCAM_KEY_LK3_11r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000500, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk3_11_reg, + NULL, + NULL, + }, + { + "etcam_key_lk3_10", + SE_CFG_ETCAM_KEY_LK3_10r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000504, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk3_10_reg, + NULL, + NULL, + }, + { + "etcam_key_lk3_9", + SE_CFG_ETCAM_KEY_LK3_9r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000508, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk3_9_reg, + NULL, + NULL, + }, + { + "etcam_key_lk3_8", + SE_CFG_ETCAM_KEY_LK3_8r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000050c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk3_8_reg, + NULL, + NULL, + }, + { + "etcam_key_lk3_7", + SE_CFG_ETCAM_KEY_LK3_7r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000510, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk3_7_reg, + NULL, + NULL, + }, + { + "etcam_key_lk3_6", + SE_CFG_ETCAM_KEY_LK3_6r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000514, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk3_6_reg, + NULL, + NULL, + }, + { + "etcam_key_lk3_5", + SE_CFG_ETCAM_KEY_LK3_5r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000518, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk3_5_reg, + NULL, + NULL, + }, + { + "etcam_key_lk3_4", + SE_CFG_ETCAM_KEY_LK3_4r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000051c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk3_4_reg, + NULL, + NULL, + }, + { + "etcam_key_lk3_3", + SE_CFG_ETCAM_KEY_LK3_3r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000520, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk3_3_reg, + NULL, + NULL, + }, + { + "etcam_key_lk3_2", + SE_CFG_ETCAM_KEY_LK3_2r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000524, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk3_2_reg, + NULL, + NULL, + }, + { + "etcam_key_lk3_1", + SE_CFG_ETCAM_KEY_LK3_1r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000528, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk3_1_reg, + NULL, + NULL, + }, + { + "etcam_key_lk3_0", + SE_CFG_ETCAM_KEY_LK3_0r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000052c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_etcam_key_lk3_0_reg, + NULL, + NULL, + }, + { + "pbu_key_lk0_3", + SE_CFG_PBU_KEY_LK0_3r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000006a0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_pbu_key_lk0_3_reg, + NULL, + NULL, + }, + { + "pbu_key_lk0_2", + SE_CFG_PBU_KEY_LK0_2r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000006a4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_pbu_key_lk0_2_reg, + NULL, + NULL, + }, + { + "pbu_key_lk0_1", + SE_CFG_PBU_KEY_LK0_1r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000006a8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_pbu_key_lk0_1_reg, + NULL, + NULL, + }, + { + "pbu_key_lk0_0", + SE_CFG_PBU_KEY_LK0_0r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000006ac, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_pbu_key_lk0_0_reg, + NULL, + NULL, + }, + { + "pbu_key_lk1_3", + SE_CFG_PBU_KEY_LK1_3r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000006b0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_pbu_key_lk1_3_reg, + NULL, + NULL, + }, + { + "pbu_key_lk1_2", + SE_CFG_PBU_KEY_LK1_2r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000006b4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_pbu_key_lk1_2_reg, + NULL, + NULL, + }, + { + "pbu_key_lk1_1", + SE_CFG_PBU_KEY_LK1_1r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000006b8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_pbu_key_lk1_1_reg, + NULL, + NULL, + }, + { + "pbu_key_lk1_0", + SE_CFG_PBU_KEY_LK1_0r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000006bc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_pbu_key_lk1_0_reg, + NULL, + NULL, + }, + { + "pbu_key_lk2_3", + SE_CFG_PBU_KEY_LK2_3r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000006c0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_pbu_key_lk2_3_reg, + NULL, + NULL, + }, + { + "pbu_key_lk2_2", + SE_CFG_PBU_KEY_LK2_2r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000006c4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_pbu_key_lk2_2_reg, + NULL, + NULL, + }, + { + "pbu_key_lk2_1", + SE_CFG_PBU_KEY_LK2_1r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000006c8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_pbu_key_lk2_1_reg, + NULL, + NULL, + }, + { + "pbu_key_lk2_0", + SE_CFG_PBU_KEY_LK2_0r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000006cc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_pbu_key_lk2_0_reg, + NULL, + NULL, + }, + { + "pbu_key_lk3_3", + SE_CFG_PBU_KEY_LK3_3r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000006d0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_pbu_key_lk3_3_reg, + NULL, + NULL, + }, + { + "pbu_key_lk3_2", + SE_CFG_PBU_KEY_LK3_2r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000006d4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_pbu_key_lk3_2_reg, + NULL, + NULL, + }, + { + "pbu_key_lk3_1", + SE_CFG_PBU_KEY_LK3_1r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000006d8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_pbu_key_lk3_1_reg, + NULL, + NULL, + }, + { + "pbu_key_lk3_0", + SE_CFG_PBU_KEY_LK3_0r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000006dc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cfg_pbu_key_lk3_0_reg, + NULL, + NULL, + }, + { + "schd_learn_fifo_pfull_ast", + SE_ALG_SCHD_LEARN_FIFO_PFULL_ASTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x008c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_schd_learn_fifo_pfull_ast_reg, + NULL, + NULL, + }, + { + "schd_learn_fifo_pfull_neg", + SE_ALG_SCHD_LEARN_FIFO_PFULL_NEGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0090, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_schd_learn_fifo_pfull_neg_reg, + NULL, + NULL, + }, + { + "schd_hash0_fifo_pfull_ast", + SE_ALG_SCHD_HASH0_FIFO_PFULL_ASTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0094, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_schd_hash0_fifo_pfull_ast_reg, + NULL, + NULL, + }, + { + "schd_hash0_fifo_pfull_neg", + SE_ALG_SCHD_HASH0_FIFO_PFULL_NEGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0098, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_schd_hash0_fifo_pfull_neg_reg, + NULL, + NULL, + }, + { + "schd_hash1_fifo_pfull_ast", + SE_ALG_SCHD_HASH1_FIFO_PFULL_ASTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x009c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_schd_hash1_fifo_pfull_ast_reg, + NULL, + NULL, + }, + { + "schd_hash1_fifo_pfull_neg", + SE_ALG_SCHD_HASH1_FIFO_PFULL_NEGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0a0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_schd_hash1_fifo_pfull_neg_reg, + NULL, + NULL, + }, + { + "schd_hash2_fifo_pfull_ast", + SE_ALG_SCHD_HASH2_FIFO_PFULL_ASTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0a4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_schd_hash2_fifo_pfull_ast_reg, + NULL, + NULL, + }, + { + "schd_hash2_fifo_pfull_neg", + SE_ALG_SCHD_HASH2_FIFO_PFULL_NEGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0a8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_schd_hash2_fifo_pfull_neg_reg, + NULL, + NULL, + }, + { + "schd_hash3_fifo_pfull_ast", + SE_ALG_SCHD_HASH3_FIFO_PFULL_ASTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0ac, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_schd_hash3_fifo_pfull_ast_reg, + NULL, + NULL, + }, + { + "schd_hash3_fifo_pfull_neg", + SE_ALG_SCHD_HASH3_FIFO_PFULL_NEGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0b0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_schd_hash3_fifo_pfull_neg_reg, + NULL, + NULL, + }, + { + "schd_lpm_fifo_pfull_ast", + SE_ALG_SCHD_LPM_FIFO_PFULL_ASTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0b4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_schd_lpm_fifo_pfull_ast_reg, + NULL, + NULL, + }, + { + "schd_lpm_fifo_pfull_neg", + SE_ALG_SCHD_LPM_FIFO_PFULL_NEGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0b8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_schd_lpm_fifo_pfull_neg_reg, + NULL, + NULL, + }, + { + "hash0_key_fifo_pfull_ast", + SE_ALG_HASH0_KEY_FIFO_PFULL_ASTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0cc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash0_key_fifo_pfull_ast_reg, + NULL, + NULL, + }, + { + "hash0_key_fifo_pfull_neg", + SE_ALG_HASH0_KEY_FIFO_PFULL_NEGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0d0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash0_key_fifo_pfull_neg_reg, + NULL, + NULL, + }, + { + "hash0_sreq_fifo_pfull_ast", + SE_ALG_HASH0_SREQ_FIFO_PFULL_ASTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0d4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash0_sreq_fifo_pfull_ast_reg, + NULL, + NULL, + }, + { + "hash0_sreq_fifo_pfull_neg", + SE_ALG_HASH0_SREQ_FIFO_PFULL_NEGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0d8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash0_sreq_fifo_pfull_neg_reg, + NULL, + NULL, + }, + { + "hash0_int_rsp_fifo_pfull_ast", + SE_ALG_HASH0_INT_RSP_FIFO_PFULL_ASTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0dc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash0_int_rsp_fifo_pfull_ast_reg, + NULL, + NULL, + }, + { + "hash0_int_rsp_fifo_pfull_neg", + SE_ALG_HASH0_INT_RSP_FIFO_PFULL_NEGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0e0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash0_int_rsp_fifo_pfull_neg_reg, + NULL, + NULL, + }, + { + "hash0_ext_rsp_fifo_pfull_ast", + SE_ALG_HASH0_EXT_RSP_FIFO_PFULL_ASTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0e4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash0_ext_rsp_fifo_pfull_ast_reg, + NULL, + NULL, + }, + { + "hash0_ext_rsp_fifo_pfull_neg", + SE_ALG_HASH0_EXT_RSP_FIFO_PFULL_NEGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0e8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash0_ext_rsp_fifo_pfull_neg_reg, + NULL, + NULL, + }, + { + "hash1_key_fifo_pfull_ast", + SE_ALG_HASH1_KEY_FIFO_PFULL_ASTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0ec, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash1_key_fifo_pfull_ast_reg, + NULL, + NULL, + }, + { + "hash1_key_fifo_pfull_neg", + SE_ALG_HASH1_KEY_FIFO_PFULL_NEGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0f0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash1_key_fifo_pfull_neg_reg, + NULL, + NULL, + }, + { + "hash1_sreq_fifo_pfull_ast", + SE_ALG_HASH1_SREQ_FIFO_PFULL_ASTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0f4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash1_sreq_fifo_pfull_ast_reg, + NULL, + NULL, + }, + { + "hash1_sreq_fifo_pfull_neg", + SE_ALG_HASH1_SREQ_FIFO_PFULL_NEGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0f8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash1_sreq_fifo_pfull_neg_reg, + NULL, + NULL, + }, + { + "hash1_int_rsp_fifo_pfull_ast", + SE_ALG_HASH1_INT_RSP_FIFO_PFULL_ASTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0fc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash1_int_rsp_fifo_pfull_ast_reg, + NULL, + NULL, + }, + { + "hash1_int_rsp_fifo_pfull_neg", + SE_ALG_HASH1_INT_RSP_FIFO_PFULL_NEGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0100, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash1_int_rsp_fifo_pfull_neg_reg, + NULL, + NULL, + }, + { + "hash1_ext_rsp_fifo_pfull_ast", + SE_ALG_HASH1_EXT_RSP_FIFO_PFULL_ASTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0104, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash1_ext_rsp_fifo_pfull_ast_reg, + NULL, + NULL, + }, + { + "hash1_ext_rsp_fifo_pfull_neg", + SE_ALG_HASH1_EXT_RSP_FIFO_PFULL_NEGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0108, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash1_ext_rsp_fifo_pfull_neg_reg, + NULL, + NULL, + }, + { + "hash2_key_fifo_pfull_ast", + SE_ALG_HASH2_KEY_FIFO_PFULL_ASTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x010c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash2_key_fifo_pfull_ast_reg, + NULL, + NULL, + }, + { + "hash2_key_fifo_pfull_neg", + SE_ALG_HASH2_KEY_FIFO_PFULL_NEGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0110, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash2_key_fifo_pfull_neg_reg, + NULL, + NULL, + }, + { + "hash2_sreq_fifo_pfull_ast", + SE_ALG_HASH2_SREQ_FIFO_PFULL_ASTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0114, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash2_sreq_fifo_pfull_ast_reg, + NULL, + NULL, + }, + { + "hash2_sreq_fifo_pfull_neg", + SE_ALG_HASH2_SREQ_FIFO_PFULL_NEGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0118, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash2_sreq_fifo_pfull_neg_reg, + NULL, + NULL, + }, + { + "hash2_int_rsp_fifo_pfull_ast", + SE_ALG_HASH2_INT_RSP_FIFO_PFULL_ASTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x011c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash2_int_rsp_fifo_pfull_ast_reg, + NULL, + NULL, + }, + { + "hash2_int_rsp_fifo_pfull_neg", + SE_ALG_HASH2_INT_RSP_FIFO_PFULL_NEGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0120, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash2_int_rsp_fifo_pfull_neg_reg, + NULL, + NULL, + }, + { + "hash2_ext_rsp_fifo_pfull_ast", + SE_ALG_HASH2_EXT_RSP_FIFO_PFULL_ASTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0124, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash2_ext_rsp_fifo_pfull_ast_reg, + NULL, + NULL, + }, + { + "hash2_ext_rsp_fifo_pfull_neg", + SE_ALG_HASH2_EXT_RSP_FIFO_PFULL_NEGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0128, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash2_ext_rsp_fifo_pfull_neg_reg, + NULL, + NULL, + }, + { + "hash3_key_fifo_pfull_ast", + SE_ALG_HASH3_KEY_FIFO_PFULL_ASTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x012c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash3_key_fifo_pfull_ast_reg, + NULL, + NULL, + }, + { + "hash3_key_fifo_pfull_neg", + SE_ALG_HASH3_KEY_FIFO_PFULL_NEGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0130, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash3_key_fifo_pfull_neg_reg, + NULL, + NULL, + }, + { + "hash3_sreq_fifo_pfull_ast", + SE_ALG_HASH3_SREQ_FIFO_PFULL_ASTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0134, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash3_sreq_fifo_pfull_ast_reg, + NULL, + NULL, + }, + { + "hash3_sreq_fifo_pfull_neg", + SE_ALG_HASH3_SREQ_FIFO_PFULL_NEGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0138, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash3_sreq_fifo_pfull_neg_reg, + NULL, + NULL, + }, + { + "hash3_int_rsp_fifo_pfull_ast", + SE_ALG_HASH3_INT_RSP_FIFO_PFULL_ASTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x013c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash3_int_rsp_fifo_pfull_ast_reg, + NULL, + NULL, + }, + { + "hash3_int_rsp_fifo_pfull_neg", + SE_ALG_HASH3_INT_RSP_FIFO_PFULL_NEGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0140, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash3_int_rsp_fifo_pfull_neg_reg, + NULL, + NULL, + }, + { + "hash3_ext_rsp_fifo_pfull_ast", + SE_ALG_HASH3_EXT_RSP_FIFO_PFULL_ASTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0144, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash3_ext_rsp_fifo_pfull_ast_reg, + NULL, + NULL, + }, + { + "hash3_ext_rsp_fifo_pfull_neg", + SE_ALG_HASH3_EXT_RSP_FIFO_PFULL_NEGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0148, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash3_ext_rsp_fifo_pfull_neg_reg, + NULL, + NULL, + }, + { + "lpm_as_info", + SE_ALG_LPM_AS_INFOr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0158, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_se_alg_lpm_as_info_reg, + NULL, + NULL, + }, + { + "lpm_ext_rsp_fifo_u0_pfull_neg", + SE_ALG_LPM_EXT_RSP_FIFO_U0_PFULL_NEGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0160, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_lpm_ext_rsp_fifo_u0_pfull_neg_reg, + NULL, + NULL, + }, + { + "lpm_ext_rsp_fifo_u2_pfull_ast", + SE_ALG_LPM_EXT_RSP_FIFO_U2_PFULL_ASTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x016c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_lpm_ext_rsp_fifo_u2_pfull_ast_reg, + NULL, + NULL, + }, + { + "lpm_ext_rsp_fifo_u2_pfull_neg", + SE_ALG_LPM_EXT_RSP_FIFO_U2_PFULL_NEGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0170, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_lpm_ext_rsp_fifo_u2_pfull_neg_reg, + NULL, + NULL, + }, + { + "lpm_ext_rsp_fifo_u3_pfull_ast", + SE_ALG_LPM_EXT_RSP_FIFO_U3_PFULL_ASTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0174, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_lpm_ext_rsp_fifo_u3_pfull_ast_reg, + NULL, + NULL, + }, + { + "lpm_ext_rsp_fifo_u3_pfull_neg", + SE_ALG_LPM_EXT_RSP_FIFO_U3_PFULL_NEGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0178, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_lpm_ext_rsp_fifo_u3_pfull_neg_reg, + NULL, + NULL, + }, + { + "lpm_ext_rsp_fifo_u4_pfull_ast", + SE_ALG_LPM_EXT_RSP_FIFO_U4_PFULL_ASTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x017c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_lpm_ext_rsp_fifo_u4_pfull_ast_reg, + NULL, + NULL, + }, + { + "lpm_ext_rsp_fifo_u4_pfull_neg", + SE_ALG_LPM_EXT_RSP_FIFO_U4_PFULL_NEGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0180, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_lpm_ext_rsp_fifo_u4_pfull_neg_reg, + NULL, + NULL, + }, + { + "lpm_as_rsp_fifo_u0_pfull_ast", + SE_ALG_LPM_AS_RSP_FIFO_U0_PFULL_ASTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x018c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_lpm_as_rsp_fifo_u0_pfull_ast_reg, + NULL, + NULL, + }, + { + "lpm_as_rsp_fifo_u0_pfull_neg", + SE_ALG_LPM_AS_RSP_FIFO_U0_PFULL_NEGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0190, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_lpm_as_rsp_fifo_u0_pfull_neg_reg, + NULL, + NULL, + }, + { + "lpm_as_rsp_fifo_u1_pfull_ast", + SE_ALG_LPM_AS_RSP_FIFO_U1_PFULL_ASTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0194, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_lpm_as_rsp_fifo_u1_pfull_ast_reg, + NULL, + NULL, + }, + { + "lpm_as_rsp_fifo_u1_pfull_neg", + SE_ALG_LPM_AS_RSP_FIFO_U1_PFULL_NEGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0198, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_lpm_as_rsp_fifo_u1_pfull_neg_reg, + NULL, + NULL, + }, + { + "lpm_v4_ddr3_base_addr", + SE_ALG_LPM_V4_DDR3_BASE_ADDRr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x019c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_lpm_v4_ddr3_base_addr_reg, + NULL, + NULL, + }, + { + "lpm_v6_ddr3_base_addr", + SE_ALG_LPM_V6_DDR3_BASE_ADDRr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x01a0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_lpm_v6_ddr3_base_addr_reg, + NULL, + NULL, + }, + { + "debug_cnt_mode", + SE_ALG_DEBUG_CNT_MODEr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x01d4, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_se_alg_debug_cnt_mode_reg, + NULL, + NULL, + }, + { + "hash_p0_key_vld_cnt", + SE_ALG_HASH_P0_KEY_VLD_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1000, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash_p0_key_vld_cnt_reg, + NULL, + NULL, + }, + { + "hash_p1_key_vld_cnt", + SE_ALG_HASH_P1_KEY_VLD_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1004, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash_p1_key_vld_cnt_reg, + NULL, + NULL, + }, + { + "hash_p2_key_vld_cnt", + SE_ALG_HASH_P2_KEY_VLD_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1008, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash_p2_key_vld_cnt_reg, + NULL, + NULL, + }, + { + "hash_p3_key_vld_cnt", + SE_ALG_HASH_P3_KEY_VLD_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x100c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash_p3_key_vld_cnt_reg, + NULL, + NULL, + }, + { + "lpm_p0_key_vld_cnt", + SE_ALG_LPM_P0_KEY_VLD_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1010, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_lpm_p0_key_vld_cnt_reg, + NULL, + NULL, + }, + { + "hash_p0_rsp_vld_cnt", + SE_ALG_HASH_P0_RSP_VLD_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1014, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash_p0_rsp_vld_cnt_reg, + NULL, + NULL, + }, + { + "hash_p1_rsp_vld_cnt", + SE_ALG_HASH_P1_RSP_VLD_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1018, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash_p1_rsp_vld_cnt_reg, + NULL, + NULL, + }, + { + "hash_p2_rsp_vld_cnt", + SE_ALG_HASH_P2_RSP_VLD_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x101c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash_p2_rsp_vld_cnt_reg, + NULL, + NULL, + }, + { + "hash_p3_rsp_vld_cnt", + SE_ALG_HASH_P3_RSP_VLD_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1020, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash_p3_rsp_vld_cnt_reg, + NULL, + NULL, + }, + { + "lpm_p0_rsp_vld_cnt", + SE_ALG_LPM_P0_RSP_VLD_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1024, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_lpm_p0_rsp_vld_cnt_reg, + NULL, + NULL, + }, + { + "hash_p0_smf_cnt", + SE_ALG_HASH_P0_SMF_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1028, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash_p0_smf_cnt_reg, + NULL, + NULL, + }, + { + "hash_p1_smf_cnt", + SE_ALG_HASH_P1_SMF_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x102c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash_p1_smf_cnt_reg, + NULL, + NULL, + }, + { + "hash_p2_smf_cnt", + SE_ALG_HASH_P2_SMF_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1030, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash_p2_smf_cnt_reg, + NULL, + NULL, + }, + { + "hash_p3_smf_cnt", + SE_ALG_HASH_P3_SMF_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1034, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash_p3_smf_cnt_reg, + NULL, + NULL, + }, + { + "lpm_p0_smf_cnt", + SE_ALG_LPM_P0_SMF_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1038, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_lpm_p0_smf_cnt_reg, + NULL, + NULL, + }, + { + "hash_p0_spacevld_cnt", + SE_ALG_HASH_P0_SPACEVLD_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x103c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash_p0_spacevld_cnt_reg, + NULL, + NULL, + }, + { + "hash_p1_spacevld_cnt", + SE_ALG_HASH_P1_SPACEVLD_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1040, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash_p1_spacevld_cnt_reg, + NULL, + NULL, + }, + { + "hash_p2_spacevld_cnt", + SE_ALG_HASH_P2_SPACEVLD_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1044, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash_p2_spacevld_cnt_reg, + NULL, + NULL, + }, + { + "hash_p3_spacevld_cnt", + SE_ALG_HASH_P3_SPACEVLD_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1048, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash_p3_spacevld_cnt_reg, + NULL, + NULL, + }, + { + "smmu1_p0_req_vld_cnt", + SE_ALG_SMMU1_P0_REQ_VLD_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x104c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_smmu1_p0_req_vld_cnt_reg, + NULL, + NULL, + }, + { + "smmu1_p1_req_vld_cnt", + SE_ALG_SMMU1_P1_REQ_VLD_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1050, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_smmu1_p1_req_vld_cnt_reg, + NULL, + NULL, + }, + { + "smmu1_p2_req_vld_cnt", + SE_ALG_SMMU1_P2_REQ_VLD_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1054, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_smmu1_p2_req_vld_cnt_reg, + NULL, + NULL, + }, + { + "smmu1_p3_req_vld_cnt", + SE_ALG_SMMU1_P3_REQ_VLD_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1058, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_smmu1_p3_req_vld_cnt_reg, + NULL, + NULL, + }, + { + "smmu1_p4_req_vld_cnt", + SE_ALG_SMMU1_P4_REQ_VLD_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x105c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_smmu1_p4_req_vld_cnt_reg, + NULL, + NULL, + }, + { + "smmu1_p5_req_vld_cnt", + SE_ALG_SMMU1_P5_REQ_VLD_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1060, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_smmu1_p5_req_vld_cnt_reg, + NULL, + NULL, + }, + { + "smmu1_p0_rsp_vld_cnt", + SE_ALG_SMMU1_P0_RSP_VLD_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1064, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_smmu1_p0_rsp_vld_cnt_reg, + NULL, + NULL, + }, + { + "smmu1_p1_rsp_vld_cnt", + SE_ALG_SMMU1_P1_RSP_VLD_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1068, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_smmu1_p1_rsp_vld_cnt_reg, + NULL, + NULL, + }, + { + "smmu1_p2_rsp_vld_cnt", + SE_ALG_SMMU1_P2_RSP_VLD_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x106c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_smmu1_p2_rsp_vld_cnt_reg, + NULL, + NULL, + }, + { + "smmu1_p3_rsp_vld_cnt", + SE_ALG_SMMU1_P3_RSP_VLD_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1070, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_smmu1_p3_rsp_vld_cnt_reg, + NULL, + NULL, + }, + { + "smmu1_p4_rsp_vld_cnt", + SE_ALG_SMMU1_P4_RSP_VLD_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1074, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_smmu1_p4_rsp_vld_cnt_reg, + NULL, + NULL, + }, + { + "smmu1_p5_rsp_vld_cnt", + SE_ALG_SMMU1_P5_RSP_VLD_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1078, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_smmu1_p5_rsp_vld_cnt_reg, + NULL, + NULL, + }, + { + "schd_learn_fifo_int_cnt", + SE_ALG_SCHD_LEARN_FIFO_INT_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x107c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_schd_learn_fifo_int_cnt_reg, + NULL, + NULL, + }, + { + "schd_hash0_fifo_int_cnt", + SE_ALG_SCHD_HASH0_FIFO_INT_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1080, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_schd_hash0_fifo_int_cnt_reg, + NULL, + NULL, + }, + { + "schd_hash1_fifo_int_cnt", + SE_ALG_SCHD_HASH1_FIFO_INT_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1084, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_schd_hash1_fifo_int_cnt_reg, + NULL, + NULL, + }, + { + "schd_hash2_fifo_int_cnt", + SE_ALG_SCHD_HASH2_FIFO_INT_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1088, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_schd_hash2_fifo_int_cnt_reg, + NULL, + NULL, + }, + { + "schd_hash3_fifo_int_cnt", + SE_ALG_SCHD_HASH3_FIFO_INT_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x108c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_schd_hash3_fifo_int_cnt_reg, + NULL, + NULL, + }, + { + "schd_lpm_fifo_int_cnt", + SE_ALG_SCHD_LPM_FIFO_INT_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1090, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_schd_lpm_fifo_int_cnt_reg, + NULL, + NULL, + }, + { + "schd_learn_fifo_parity_err_cnt", + SE_ALG_SCHD_LEARN_FIFO_PARITY_ERR_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1094, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_schd_learn_fifo_parity_err_cnt_reg, + NULL, + NULL, + }, + { + "schd_hash0_fifo_parity_err_cnt", + SE_ALG_SCHD_HASH0_FIFO_PARITY_ERR_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1098, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_schd_hash0_fifo_parity_err_cnt_reg, + NULL, + NULL, + }, + { + "schd_hash1_fifo_parity_err_cnt", + SE_ALG_SCHD_HASH1_FIFO_PARITY_ERR_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x109c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_schd_hash1_fifo_parity_err_cnt_reg, + NULL, + NULL, + }, + { + "schd_hash2_fifo_parity_err_cnt", + SE_ALG_SCHD_HASH2_FIFO_PARITY_ERR_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10a0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_schd_hash2_fifo_parity_err_cnt_reg, + NULL, + NULL, + }, + { + "schd_hash3_fifo_parity_err_cnt", + SE_ALG_SCHD_HASH3_FIFO_PARITY_ERR_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10a4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_schd_hash3_fifo_parity_err_cnt_reg, + NULL, + NULL, + }, + { + "schd_lpm_fifo_parity_err_cnt", + SE_ALG_SCHD_LPM_FIFO_PARITY_ERR_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10a8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_schd_lpm_fifo_parity_err_cnt_reg, + NULL, + NULL, + }, + { + "rd_init_cft_cnt", + SE_ALG_RD_INIT_CFT_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10ac, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_rd_init_cft_cnt_reg, + NULL, + NULL, + }, + { + "zgp0_zblk0_ecc_err_cnt", + SE_ALG_ZGP0_ZBLK0_ECC_ERR_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10b0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_zgp0_zblk0_ecc_err_cnt_reg, + NULL, + NULL, + }, + { + "zgp0_zblk1_ecc_err_cnt", + SE_ALG_ZGP0_ZBLK1_ECC_ERR_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10b4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_zgp0_zblk1_ecc_err_cnt_reg, + NULL, + NULL, + }, + { + "zgp0_zblk2_ecc_err_cnt", + SE_ALG_ZGP0_ZBLK2_ECC_ERR_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10b8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_zgp0_zblk2_ecc_err_cnt_reg, + NULL, + NULL, + }, + { + "zgp0_zblk3_ecc_err_cnt", + SE_ALG_ZGP0_ZBLK3_ECC_ERR_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10bc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_zgp0_zblk3_ecc_err_cnt_reg, + NULL, + NULL, + }, + { + "zgp0_zblk4_ecc_err_cnt", + SE_ALG_ZGP0_ZBLK4_ECC_ERR_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10c0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_zgp0_zblk4_ecc_err_cnt_reg, + NULL, + NULL, + }, + { + "zgp0_zblk5_ecc_err_cnt", + SE_ALG_ZGP0_ZBLK5_ECC_ERR_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10c4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_zgp0_zblk5_ecc_err_cnt_reg, + NULL, + NULL, + }, + { + "zgp0_zblk6_ecc_err_cnt", + SE_ALG_ZGP0_ZBLK6_ECC_ERR_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10c8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_zgp0_zblk6_ecc_err_cnt_reg, + NULL, + NULL, + }, + { + "zgp0_zblk7_ecc_err_cnt", + SE_ALG_ZGP0_ZBLK7_ECC_ERR_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10cc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_zgp0_zblk7_ecc_err_cnt_reg, + NULL, + NULL, + }, + { + "zgp1_zblk0_ecc_err_cnt", + SE_ALG_ZGP1_ZBLK0_ECC_ERR_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10d0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_zgp1_zblk0_ecc_err_cnt_reg, + NULL, + NULL, + }, + { + "zgp1_zblk1_ecc_err_cnt", + SE_ALG_ZGP1_ZBLK1_ECC_ERR_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10d4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_zgp1_zblk1_ecc_err_cnt_reg, + NULL, + NULL, + }, + { + "zgp1_zblk2_ecc_err_cnt", + SE_ALG_ZGP1_ZBLK2_ECC_ERR_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10d8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_zgp1_zblk2_ecc_err_cnt_reg, + NULL, + NULL, + }, + { + "zgp1_zblk3_ecc_err_cnt", + SE_ALG_ZGP1_ZBLK3_ECC_ERR_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10dc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_zgp1_zblk3_ecc_err_cnt_reg, + NULL, + NULL, + }, + { + "zgp1_zblk4_ecc_err_cnt", + SE_ALG_ZGP1_ZBLK4_ECC_ERR_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10e0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_zgp1_zblk4_ecc_err_cnt_reg, + NULL, + NULL, + }, + { + "zgp1_zblk5_ecc_err_cnt", + SE_ALG_ZGP1_ZBLK5_ECC_ERR_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10e4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_zgp1_zblk5_ecc_err_cnt_reg, + NULL, + NULL, + }, + { + "zgp1_zblk6_ecc_err_cnt", + SE_ALG_ZGP1_ZBLK6_ECC_ERR_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10e8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_zgp1_zblk6_ecc_err_cnt_reg, + NULL, + NULL, + }, + { + "zgp1_zblk7_ecc_err_cnt", + SE_ALG_ZGP1_ZBLK7_ECC_ERR_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10ec, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_zgp1_zblk7_ecc_err_cnt_reg, + NULL, + NULL, + }, + { + "zgp2_zblk0_ecc_err_cnt", + SE_ALG_ZGP2_ZBLK0_ECC_ERR_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10f0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_zgp2_zblk0_ecc_err_cnt_reg, + NULL, + NULL, + }, + { + "zgp2_zblk1_ecc_err_cnt", + SE_ALG_ZGP2_ZBLK1_ECC_ERR_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10f4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_zgp2_zblk1_ecc_err_cnt_reg, + NULL, + NULL, + }, + { + "zgp2_zblk2_ecc_err_cnt", + SE_ALG_ZGP2_ZBLK2_ECC_ERR_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10f8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_zgp2_zblk2_ecc_err_cnt_reg, + NULL, + NULL, + }, + { + "zgp2_zblk3_ecc_err_cnt", + SE_ALG_ZGP2_ZBLK3_ECC_ERR_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10fc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_zgp2_zblk3_ecc_err_cnt_reg, + NULL, + NULL, + }, + { + "zgp2_zblk4_ecc_err_cnt", + SE_ALG_ZGP2_ZBLK4_ECC_ERR_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1100, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_zgp2_zblk4_ecc_err_cnt_reg, + NULL, + NULL, + }, + { + "zgp2_zblk5_ecc_err_cnt", + SE_ALG_ZGP2_ZBLK5_ECC_ERR_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1104, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_zgp2_zblk5_ecc_err_cnt_reg, + NULL, + NULL, + }, + { + "zgp2_zblk6_ecc_err_cnt", + SE_ALG_ZGP2_ZBLK6_ECC_ERR_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1108, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_zgp2_zblk6_ecc_err_cnt_reg, + NULL, + NULL, + }, + { + "zgp2_zblk7_ecc_err_cnt", + SE_ALG_ZGP2_ZBLK7_ECC_ERR_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x110c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_zgp2_zblk7_ecc_err_cnt_reg, + NULL, + NULL, + }, + { + "zgp3_zblk0_ecc_err_cnt", + SE_ALG_ZGP3_ZBLK0_ECC_ERR_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1110, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_zgp3_zblk0_ecc_err_cnt_reg, + NULL, + NULL, + }, + { + "zgp3_zblk1_ecc_err_cnt", + SE_ALG_ZGP3_ZBLK1_ECC_ERR_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1114, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_zgp3_zblk1_ecc_err_cnt_reg, + NULL, + NULL, + }, + { + "zgp3_zblk2_ecc_err_cnt", + SE_ALG_ZGP3_ZBLK2_ECC_ERR_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1118, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_zgp3_zblk2_ecc_err_cnt_reg, + NULL, + NULL, + }, + { + "zgp3_zblk3_ecc_err_cnt", + SE_ALG_ZGP3_ZBLK3_ECC_ERR_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x111c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_zgp3_zblk3_ecc_err_cnt_reg, + NULL, + NULL, + }, + { + "zgp3_zblk4_ecc_err_cnt", + SE_ALG_ZGP3_ZBLK4_ECC_ERR_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1120, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_zgp3_zblk4_ecc_err_cnt_reg, + NULL, + NULL, + }, + { + "zgp3_zblk5_ecc_err_cnt", + SE_ALG_ZGP3_ZBLK5_ECC_ERR_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1124, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_zgp3_zblk5_ecc_err_cnt_reg, + NULL, + NULL, + }, + { + "zgp3_zblk6_ecc_err_cnt", + SE_ALG_ZGP3_ZBLK6_ECC_ERR_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1128, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_zgp3_zblk6_ecc_err_cnt_reg, + NULL, + NULL, + }, + { + "zgp3_zblk7_ecc_err_cnt", + SE_ALG_ZGP3_ZBLK7_ECC_ERR_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x112c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_zgp3_zblk7_ecc_err_cnt_reg, + NULL, + NULL, + }, + { + "zcam_hash_p0_err_cnt", + SE_ALG_ZCAM_HASH_P0_ERR_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1130, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_zcam_hash_p0_err_cnt_reg, + NULL, + NULL, + }, + { + "zcam_hash_p1_err_cnt", + SE_ALG_ZCAM_HASH_P1_ERR_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1134, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_zcam_hash_p1_err_cnt_reg, + NULL, + NULL, + }, + { + "zcam_hash_p2_err_cnt", + SE_ALG_ZCAM_HASH_P2_ERR_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1138, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_zcam_hash_p2_err_cnt_reg, + NULL, + NULL, + }, + { + "zcam_hash_p3_err_cnt", + SE_ALG_ZCAM_HASH_P3_ERR_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x113c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_zcam_hash_p3_err_cnt_reg, + NULL, + NULL, + }, + { + "zcam_lpm_err_cnt", + SE_ALG_ZCAM_LPM_ERR_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1140, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_zcam_lpm_err_cnt_reg, + NULL, + NULL, + }, + { + "hash0_sreq_fifo_parity_err_cnt", + SE_ALG_HASH0_SREQ_FIFO_PARITY_ERR_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1144, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash0_sreq_fifo_parity_err_cnt_reg, + NULL, + NULL, + }, + { + "hash0_sreq_fifo_int_cnt", + SE_ALG_HASH0_SREQ_FIFO_INT_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1148, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash0_sreq_fifo_int_cnt_reg, + NULL, + NULL, + }, + { + "hash0_key_fifo_int_cnt", + SE_ALG_HASH0_KEY_FIFO_INT_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x114c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash0_key_fifo_int_cnt_reg, + NULL, + NULL, + }, + { + "hash0_int_rsp_fifo_parity_err_cnt", + SE_ALG_HASH0_INT_RSP_FIFO_PARITY_ERR_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1150, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash0_int_rsp_fifo_parity_err_cnt_reg, + NULL, + NULL, + }, + { + "hash0_ext_rsp_fifo_parity_err_cnt", + SE_ALG_HASH0_EXT_RSP_FIFO_PARITY_ERR_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1154, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash0_ext_rsp_fifo_parity_err_cnt_reg, + NULL, + NULL, + }, + { + "hash0_ext_rsp_fifo_int_cnt", + SE_ALG_HASH0_EXT_RSP_FIFO_INT_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1158, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash0_ext_rsp_fifo_int_cnt_reg, + NULL, + NULL, + }, + { + "hash0_int_rsp_fifo_int_cnt", + SE_ALG_HASH0_INT_RSP_FIFO_INT_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x115c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash0_int_rsp_fifo_int_cnt_reg, + NULL, + NULL, + }, + { + "hash1_sreq_fifo_parity_err_cnt", + SE_ALG_HASH1_SREQ_FIFO_PARITY_ERR_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1160, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash1_sreq_fifo_parity_err_cnt_reg, + NULL, + NULL, + }, + { + "hash1_sreq_fifo_int_cnt", + SE_ALG_HASH1_SREQ_FIFO_INT_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1164, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash1_sreq_fifo_int_cnt_reg, + NULL, + NULL, + }, + { + "hash1_key_fifo_int_cnt", + SE_ALG_HASH1_KEY_FIFO_INT_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1168, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash1_key_fifo_int_cnt_reg, + NULL, + NULL, + }, + { + "hash1_int_rsp_fifo_parity_err_cnt", + SE_ALG_HASH1_INT_RSP_FIFO_PARITY_ERR_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x116c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash1_int_rsp_fifo_parity_err_cnt_reg, + NULL, + NULL, + }, + { + "hash1_ext_rsp_fifo_parity_err_cnt", + SE_ALG_HASH1_EXT_RSP_FIFO_PARITY_ERR_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1170, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash1_ext_rsp_fifo_parity_err_cnt_reg, + NULL, + NULL, + }, + { + "hash1_ext_rsp_fifo_int_cnt", + SE_ALG_HASH1_EXT_RSP_FIFO_INT_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1174, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash1_ext_rsp_fifo_int_cnt_reg, + NULL, + NULL, + }, + { + "hash1_int_rsp_fifo_int_cnt", + SE_ALG_HASH1_INT_RSP_FIFO_INT_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1178, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash1_int_rsp_fifo_int_cnt_reg, + NULL, + NULL, + }, + { + "hash2_sreq_fifo_parity_err_cnt", + SE_ALG_HASH2_SREQ_FIFO_PARITY_ERR_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x117c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash2_sreq_fifo_parity_err_cnt_reg, + NULL, + NULL, + }, + { + "hash2_sreq_fifo_int_cnt", + SE_ALG_HASH2_SREQ_FIFO_INT_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1180, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash2_sreq_fifo_int_cnt_reg, + NULL, + NULL, + }, + { + "hash2_key_fifo_int_cnt", + SE_ALG_HASH2_KEY_FIFO_INT_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1184, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash2_key_fifo_int_cnt_reg, + NULL, + NULL, + }, + { + "hash2_int_rsp_fifo_parity_err_cnt", + SE_ALG_HASH2_INT_RSP_FIFO_PARITY_ERR_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1188, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash2_int_rsp_fifo_parity_err_cnt_reg, + NULL, + NULL, + }, + { + "hash2_ext_rsp_fifo_parity_err_cnt", + SE_ALG_HASH2_EXT_RSP_FIFO_PARITY_ERR_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x118c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash2_ext_rsp_fifo_parity_err_cnt_reg, + NULL, + NULL, + }, + { + "hash2_ext_rsp_fifo_int_cnt", + SE_ALG_HASH2_EXT_RSP_FIFO_INT_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1190, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash2_ext_rsp_fifo_int_cnt_reg, + NULL, + NULL, + }, + { + "hash2_int_rsp_fifo_int_cnt", + SE_ALG_HASH2_INT_RSP_FIFO_INT_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1194, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash2_int_rsp_fifo_int_cnt_reg, + NULL, + NULL, + }, + { + "hash3_sreq_fifo_parity_err_cnt", + SE_ALG_HASH3_SREQ_FIFO_PARITY_ERR_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1198, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash3_sreq_fifo_parity_err_cnt_reg, + NULL, + NULL, + }, + { + "hash3_sreq_fifo_int_cnt", + SE_ALG_HASH3_SREQ_FIFO_INT_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x119c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash3_sreq_fifo_int_cnt_reg, + NULL, + NULL, + }, + { + "hash3_key_fifo_int_cnt", + SE_ALG_HASH3_KEY_FIFO_INT_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x11a0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash3_key_fifo_int_cnt_reg, + NULL, + NULL, + }, + { + "hash3_int_rsp_fifo_parity_err_cnt", + SE_ALG_HASH3_INT_RSP_FIFO_PARITY_ERR_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x11a4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash3_int_rsp_fifo_parity_err_cnt_reg, + NULL, + NULL, + }, + { + "hash3_ext_rsp_fifo_parity_err_cnt", + SE_ALG_HASH3_EXT_RSP_FIFO_PARITY_ERR_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x11a8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash3_ext_rsp_fifo_parity_err_cnt_reg, + NULL, + NULL, + }, + { + "hash3_ext_rsp_fifo_int_cnt", + SE_ALG_HASH3_EXT_RSP_FIFO_INT_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x11ac, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash3_ext_rsp_fifo_int_cnt_reg, + NULL, + NULL, + }, + { + "hash3_int_rsp_fifo_int_cnt", + SE_ALG_HASH3_INT_RSP_FIFO_INT_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x11b0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash3_int_rsp_fifo_int_cnt_reg, + NULL, + NULL, + }, + { + "lpm_ext_rsp_fifo_int_cnt", + SE_ALG_LPM_EXT_RSP_FIFO_INT_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x11b4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_lpm_ext_rsp_fifo_int_cnt_reg, + NULL, + NULL, + }, + { + "lpm_ext_v6_fifo_int_cnt", + SE_ALG_LPM_EXT_V6_FIFO_INT_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x11b8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_lpm_ext_v6_fifo_int_cnt_reg, + NULL, + NULL, + }, + { + "lpm_ext_v4_fifo_int_cnt", + SE_ALG_LPM_EXT_V4_FIFO_INT_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x11bc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_lpm_ext_v4_fifo_int_cnt_reg, + NULL, + NULL, + }, + { + "lpm_ext_addr_fifo_int_cnt", + SE_ALG_LPM_EXT_ADDR_FIFO_INT_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x11c0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_lpm_ext_addr_fifo_int_cnt_reg, + NULL, + NULL, + }, + { + "lpm_ext_v4_fifo_parity_err_cnt", + SE_ALG_LPM_EXT_V4_FIFO_PARITY_ERR_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x11c4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_lpm_ext_v4_fifo_parity_err_cnt_reg, + NULL, + NULL, + }, + { + "lpm_ext_v6_fifo_parity_err_cnt", + SE_ALG_LPM_EXT_V6_FIFO_PARITY_ERR_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x11c8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_lpm_ext_v6_fifo_parity_err_cnt_reg, + NULL, + NULL, + }, + { + "lpm_ext_rsp_fifo_parity_err_cnt", + SE_ALG_LPM_EXT_RSP_FIFO_PARITY_ERR_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x11cc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_lpm_ext_rsp_fifo_parity_err_cnt_reg, + NULL, + NULL, + }, + { + "lpm_as_req_fifo_int_cnt", + SE_ALG_LPM_AS_REQ_FIFO_INT_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x11d0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_lpm_as_req_fifo_int_cnt_reg, + NULL, + NULL, + }, + { + "lpm_as_int_rsp_fifo_int_cnt", + SE_ALG_LPM_AS_INT_RSP_FIFO_INT_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x11d4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_lpm_as_int_rsp_fifo_int_cnt_reg, + NULL, + NULL, + }, + { + "se_alg_int_status", + SE_ALG_SE_ALG_INT_STATUSr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1800, + (32/8), + 0, + 0, + 0, + 0, + 7, + g_se_alg_se_alg_int_status_reg, + NULL, + NULL, + }, + { + "schd_int_en", + SE_ALG_SCHD_INT_ENr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1804, + (32/8), + 0, + 0, + 0, + 0, + 14, + g_se_alg_schd_int_en_reg, + NULL, + NULL, + }, + { + "schd_int_mask", + SE_ALG_SCHD_INT_MASKr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1808, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_schd_int_mask_reg, + NULL, + NULL, + }, + { + "schd_int_status", + SE_ALG_SCHD_INT_STATUSr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x180c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_schd_int_status_reg, + NULL, + NULL, + }, + { + "zblk_ecc_int_en", + SE_ALG_ZBLK_ECC_INT_ENr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1810, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_zblk_ecc_int_en_reg, + NULL, + NULL, + }, + { + "zblk_ecc_int_mask", + SE_ALG_ZBLK_ECC_INT_MASKr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1814, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_zblk_ecc_int_mask_reg, + NULL, + NULL, + }, + { + "zblk_ecc_int_status", + SE_ALG_ZBLK_ECC_INT_STATUSr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1818, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_zblk_ecc_int_status_reg, + NULL, + NULL, + }, + { + "hash0_int_en", + SE_ALG_HASH0_INT_ENr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x181c, + (32/8), + 0, + 0, + 0, + 0, + 8, + g_se_alg_hash0_int_en_reg, + NULL, + NULL, + }, + { + "hash0_int_mask", + SE_ALG_HASH0_INT_MASKr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1820, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash0_int_mask_reg, + NULL, + NULL, + }, + { + "hash0_int_status", + SE_ALG_HASH0_INT_STATUSr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1824, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash0_int_status_reg, + NULL, + NULL, + }, + { + "hash1_int_en", + SE_ALG_HASH1_INT_ENr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1828, + (32/8), + 0, + 0, + 0, + 0, + 8, + g_se_alg_hash1_int_en_reg, + NULL, + NULL, + }, + { + "hash1_int_mask", + SE_ALG_HASH1_INT_MASKr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x182c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash1_int_mask_reg, + NULL, + NULL, + }, + { + "hash1_int_status", + SE_ALG_HASH1_INT_STATUSr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1830, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash1_int_status_reg, + NULL, + NULL, + }, + { + "hash2_int_en", + SE_ALG_HASH2_INT_ENr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1834, + (32/8), + 0, + 0, + 0, + 0, + 8, + g_se_alg_hash2_int_en_reg, + NULL, + NULL, + }, + { + "hash2_int_mask", + SE_ALG_HASH2_INT_MASKr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1838, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash2_int_mask_reg, + NULL, + NULL, + }, + { + "hash2_int_status", + SE_ALG_HASH2_INT_STATUSr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x183c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash2_int_status_reg, + NULL, + NULL, + }, + { + "hash3_int_en", + SE_ALG_HASH3_INT_ENr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1840, + (32/8), + 0, + 0, + 0, + 0, + 8, + g_se_alg_hash3_int_en_reg, + NULL, + NULL, + }, + { + "hash3_int_mask", + SE_ALG_HASH3_INT_MASKr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1844, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash3_int_mask_reg, + NULL, + NULL, + }, + { + "hash3_int_status", + SE_ALG_HASH3_INT_STATUSr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1848, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_hash3_int_status_reg, + NULL, + NULL, + }, + { + "lpm_int_en", + SE_ALG_LPM_INT_ENr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x184c, + (32/8), + 0, + 0, + 0, + 0, + 10, + g_se_alg_lpm_int_en_reg, + NULL, + NULL, + }, + { + "lpm_int_mask", + SE_ALG_LPM_INT_MASKr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1850, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_lpm_int_mask_reg, + NULL, + NULL, + }, + { + "lpm_int_status", + SE_ALG_LPM_INT_STATUSr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1854, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_alg_lpm_int_status_reg, + NULL, + NULL, + }, + { + "zblock_lpm_mask0", + SE_ALG_ZBLOCK_LPM_MASK0r, + SE, + DPP_REG_FLAG_INDIRECT, + DPP_REG_BIN_ARRAY, + 0x10001, + (512/8), + 3 + 1, + 7 + 1, + 0x4000, + 0x800, + 5, + g_se_alg_zblock_lpm_mask0_reg, + NULL, + NULL, + }, + { + "zblock_lpm_mask1", + SE_ALG_ZBLOCK_LPM_MASK1r, + SE, + DPP_REG_FLAG_INDIRECT, + DPP_REG_BIN_ARRAY, + 0x10002, + (512/8), + 3 + 1, + 7 + 1, + 0x4000, + 0x800, + 5, + g_se_alg_zblock_lpm_mask1_reg, + NULL, + NULL, + }, + { + "zblock_lpm_mask2", + SE_ALG_ZBLOCK_LPM_MASK2r, + SE, + DPP_REG_FLAG_INDIRECT, + DPP_REG_BIN_ARRAY, + 0x10003, + (512/8), + 3 + 1, + 7 + 1, + 0x4000, + 0x800, + 5, + g_se_alg_zblock_lpm_mask2_reg, + NULL, + NULL, + }, + { + "zblock_lpm_mask3", + SE_ALG_ZBLOCK_LPM_MASK3r, + SE, + DPP_REG_FLAG_INDIRECT, + DPP_REG_BIN_ARRAY, + 0x10004, + (512/8), + 3 + 1, + 7 + 1, + 0x4000, + 0x800, + 5, + g_se_alg_zblock_lpm_mask3_reg, + NULL, + NULL, + }, + { + "zblock_default_route0", + SE_ALG_ZBLOCK_DEFAULT_ROUTE0r, + SE, + DPP_REG_FLAG_INDIRECT, + DPP_REG_BIN_ARRAY, + 0x10005, + (512/8), + 3 + 1, + 7 + 1, + 0x4000, + 0x800, + 4, + g_se_alg_zblock_default_route0_reg, + NULL, + NULL, + }, + { + "zblock_default_route1", + SE_ALG_ZBLOCK_DEFAULT_ROUTE1r, + SE, + DPP_REG_FLAG_INDIRECT, + DPP_REG_BIN_ARRAY, + 0x10006, + (512/8), + 3 + 1, + 7 + 1, + 0x4000, + 0x800, + 4, + g_se_alg_zblock_default_route1_reg, + NULL, + NULL, + }, + { + "zblock_default_route2", + SE_ALG_ZBLOCK_DEFAULT_ROUTE2r, + SE, + DPP_REG_FLAG_INDIRECT, + DPP_REG_BIN_ARRAY, + 0x10007, + (512/8), + 3 + 1, + 7 + 1, + 0x4000, + 0x800, + 4, + g_se_alg_zblock_default_route2_reg, + NULL, + NULL, + }, + { + "zblock_default_route3", + SE_ALG_ZBLOCK_DEFAULT_ROUTE3r, + SE, + DPP_REG_FLAG_INDIRECT, + DPP_REG_BIN_ARRAY, + 0x10008, + (512/8), + 3 + 1, + 7 + 1, + 0x4000, + 0x800, + 4, + g_se_alg_zblock_default_route3_reg, + NULL, + NULL, + }, + { + "zblock_default_route4", + SE_ALG_ZBLOCK_DEFAULT_ROUTE4r, + SE, + DPP_REG_FLAG_INDIRECT, + DPP_REG_BIN_ARRAY, + 0x10009, + (512/8), + 3 + 1, + 7 + 1, + 0x4000, + 0x800, + 4, + g_se_alg_zblock_default_route4_reg, + NULL, + NULL, + }, + { + "zblock_default_route5", + SE_ALG_ZBLOCK_DEFAULT_ROUTE5r, + SE, + DPP_REG_FLAG_INDIRECT, + DPP_REG_BIN_ARRAY, + 0x1000a, + (512/8), + 3 + 1, + 7 + 1, + 0x4000, + 0x800, + 4, + g_se_alg_zblock_default_route5_reg, + NULL, + NULL, + }, + { + "zblock_default_route6", + SE_ALG_ZBLOCK_DEFAULT_ROUTE6r, + SE, + DPP_REG_FLAG_INDIRECT, + DPP_REG_BIN_ARRAY, + 0x1000b, + (512/8), + 3 + 1, + 7 + 1, + 0x4000, + 0x800, + 4, + g_se_alg_zblock_default_route6_reg, + NULL, + NULL, + }, + { + "zblock_default_route7", + SE_ALG_ZBLOCK_DEFAULT_ROUTE7r, + SE, + DPP_REG_FLAG_INDIRECT, + DPP_REG_BIN_ARRAY, + 0x1000c, + (512/8), + 3 + 1, + 7 + 1, + 0x4000, + 0x800, + 4, + g_se_alg_zblock_default_route7_reg, + NULL, + NULL, + }, + { + "zblock_hash_listtable_item0", + SE_ALG_ZBLOCK_HASH_LISTTABLE_ITEM0r, + SE, + DPP_REG_FLAG_INDIRECT, + DPP_REG_BIN_ARRAY, + 0x1000d, + (512/8), + 3 + 1, + 7 + 1, + 0x4000, + 0x800, + 1, + g_se_alg_zblock_hash_listtable_item0_reg, + NULL, + NULL, + }, + { + "zblock_hash_listtable_item1", + SE_ALG_ZBLOCK_HASH_LISTTABLE_ITEM1r, + SE, + DPP_REG_FLAG_INDIRECT, + DPP_REG_BIN_ARRAY, + 0x1000e, + (512/8), + 3 + 1, + 7 + 1, + 0x4000, + 0x800, + 1, + g_se_alg_zblock_hash_listtable_item1_reg, + NULL, + NULL, + }, + { + "zblock_hash_listtable_item2", + SE_ALG_ZBLOCK_HASH_LISTTABLE_ITEM2r, + SE, + DPP_REG_FLAG_INDIRECT, + DPP_REG_BIN_ARRAY, + 0x1000f, + (512/8), + 3 + 1, + 7 + 1, + 0x4000, + 0x800, + 1, + g_se_alg_zblock_hash_listtable_item2_reg, + NULL, + NULL, + }, + { + "zblock_hash_listtable_item3", + SE_ALG_ZBLOCK_HASH_LISTTABLE_ITEM3r, + SE, + DPP_REG_FLAG_INDIRECT, + DPP_REG_BIN_ARRAY, + 0x10010, + (512/8), + 3 + 1, + 7 + 1, + 0x4000, + 0x800, + 1, + g_se_alg_zblock_hash_listtable_item3_reg, + NULL, + NULL, + }, + { + "zblock_ecc_err_status", + SE_ALG_ZBLOCK_ECC_ERR_STATUSr, + SE, + DPP_REG_FLAG_INDIRECT, + DPP_REG_BIN_ARRAY, + 0x10011, + (512/8), + 3 + 1, + 7 + 1, + 0x4000, + 0x800, + 4, + g_se_alg_zblock_ecc_err_status_reg, + NULL, + NULL, + }, + { + "zblock_lpm_v6_sram_cmp", + SE_ALG_ZBLOCK_LPM_V6_SRAM_CMPr, + SE, + DPP_REG_FLAG_INDIRECT, + DPP_REG_BIN_ARRAY, + 0x10012, + (512/8), + 3 + 1, + 7 + 1, + 0x4000, + 0x800, + 1, + g_se_alg_zblock_lpm_v6_sram_cmp_reg, + NULL, + NULL, + }, + { + "zblock_lpm_v4_sram_cmp", + SE_ALG_ZBLOCK_LPM_V4_SRAM_CMPr, + SE, + DPP_REG_FLAG_INDIRECT, + DPP_REG_BIN_ARRAY, + 0x10013, + (512/8), + 3 + 1, + 5 + 1, + 0x4000, + 0x800, + 1, + g_se_alg_zblock_lpm_v4_sram_cmp_reg, + NULL, + NULL, + }, + { + "kschd_pful_cfg", + SE_PARSER_KSCHD_PFUL_CFGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_PARSER_BASE_ADDR + 0x00000000, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_se_parser_kschd_pful_cfg_reg, + NULL, + NULL, + }, + { + "debug_cnt_mode", + SE_PARSER_DEBUG_CNT_MODEr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_PARSER_BASE_ADDR + 0x00000004, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_se_parser_debug_cnt_mode_reg, + NULL, + NULL, + }, + { + "parser_int_en", + SE_PARSER_PARSER_INT_ENr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_PARSER_BASE_ADDR + 0x0000000c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_parser_parser_int_en_reg, + NULL, + NULL, + }, + { + "parser_int_mask", + SE_PARSER_PARSER_INT_MASKr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_PARSER_BASE_ADDR + 0x00000010, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_parser_parser_int_mask_reg, + NULL, + NULL, + }, + { + "parser_int_status", + SE_PARSER_PARSER_INT_STATUSr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_PARSER_BASE_ADDR + 0x00000014, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_parser_parser_int_status_reg, + NULL, + NULL, + }, + { + "parser_int_unmask_flag", + SE_PARSER_PARSER_INT_UNMASK_FLAGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_PARSER_BASE_ADDR + 0x00000018, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_parser_parser_int_unmask_flag_reg, + NULL, + NULL, + }, + { + "ecc_bypass_read", + SE_PARSER_ECC_BYPASS_READr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_PARSER_BASE_ADDR + 0x0000001c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_parser_ecc_bypass_read_reg, + NULL, + NULL, + }, + { + "mex0_5_req_cnt", + SE_PARSER_MEX0_5_REQ_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_PARSER_BASE_ADDR + 0x00000400, + (32/8), + 0, + 5 + 1, + 0, + 4, + 1, + g_se_parser_mex0_5_req_cnt_reg, + NULL, + NULL, + }, + { + "kschd_req0_5_cnt", + SE_PARSER_KSCHD_REQ0_5_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_PARSER_BASE_ADDR + 0x00000420, + (32/8), + 0, + 5 + 1, + 0, + 4, + 1, + g_se_parser_kschd_req0_5_cnt_reg, + NULL, + NULL, + }, + { + "kschd_parser_fc0_5_cnt", + SE_PARSER_KSCHD_PARSER_FC0_5_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_PARSER_BASE_ADDR + 0x00000440, + (32/8), + 0, + 5 + 1, + 0, + 4, + 1, + g_se_parser_kschd_parser_fc0_5_cnt_reg, + NULL, + NULL, + }, + { + "se_ppu_mex0_5_fc_cnt", + SE_PARSER_SE_PPU_MEX0_5_FC_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_PARSER_BASE_ADDR + 0x00000460, + (32/8), + 0, + 5 + 1, + 0, + 4, + 1, + g_se_parser_se_ppu_mex0_5_fc_cnt_reg, + NULL, + NULL, + }, + { + "smmu0_marc_fc_cnt", + SE_PARSER_SMMU0_MARC_FC_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_PARSER_BASE_ADDR + 0x00000480, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_parser_smmu0_marc_fc_cnt_reg, + NULL, + NULL, + }, + { + "smmu0_marc_key_cnt", + SE_PARSER_SMMU0_MARC_KEY_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_PARSER_BASE_ADDR + 0x00000484, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_parser_smmu0_marc_key_cnt_reg, + NULL, + NULL, + }, + { + "cmmu_key_cnt", + SE_PARSER_CMMU_KEY_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_PARSER_BASE_ADDR + 0x00000488, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_parser_cmmu_key_cnt_reg, + NULL, + NULL, + }, + { + "cmmu_parser_fc_cnt", + SE_PARSER_CMMU_PARSER_FC_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_PARSER_BASE_ADDR + 0x0000048c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_parser_cmmu_parser_fc_cnt_reg, + NULL, + NULL, + }, + { + "marc_tab_type_err_mex0_5_cnt", + SE_PARSER_MARC_TAB_TYPE_ERR_MEX0_5_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_PARSER_BASE_ADDR + 0x00000490, + (32/8), + 0, + 5 + 1, + 0, + 4, + 1, + g_se_parser_marc_tab_type_err_mex0_5_cnt_reg, + NULL, + NULL, + }, + { + "eram_fulladdr_drop_cnt", + SE_PARSER_ERAM_FULLADDR_DROP_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_PARSER_BASE_ADDR + 0x000004b0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_parser_eram_fulladdr_drop_cnt_reg, + NULL, + NULL, + }, + { + "hash0_pful_cfg", + SE_AS_HASH0_PFUL_CFGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000001c0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_as_hash0_pful_cfg_reg, + NULL, + NULL, + }, + { + "hash1_pful_cfg", + SE_AS_HASH1_PFUL_CFGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000001c4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_as_hash1_pful_cfg_reg, + NULL, + NULL, + }, + { + "hash2_pful_cfg", + SE_AS_HASH2_PFUL_CFGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000001c8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_as_hash2_pful_cfg_reg, + NULL, + NULL, + }, + { + "hash3_pful_cfg", + SE_AS_HASH3_PFUL_CFGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000001cc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_as_hash3_pful_cfg_reg, + NULL, + NULL, + }, + { + "pbu_pful_cfg", + SE_AS_PBU_PFUL_CFGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000001d0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_as_pbu_pful_cfg_reg, + NULL, + NULL, + }, + { + "lpm_pful_cfg", + SE_AS_LPM_PFUL_CFGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000001d4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_as_lpm_pful_cfg_reg, + NULL, + NULL, + }, + { + "etcam_pful_cfg", + SE_AS_ETCAM_PFUL_CFGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000001dc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_as_etcam_pful_cfg_reg, + NULL, + NULL, + }, + { + "as_learn0_fifo_cfg", + SE_AS_AS_LEARN0_FIFO_CFGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000001e0, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_se_as_as_learn0_fifo_cfg_reg, + NULL, + NULL, + }, + { + "as_learn1_fifo_cfg", + SE_AS_AS_LEARN1_FIFO_CFGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000001e4, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_se_as_as_learn1_fifo_cfg_reg, + NULL, + NULL, + }, + { + "as_dma_fifo_cfg", + SE_AS_AS_DMA_FIFO_CFGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000001e8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_as_as_dma_fifo_cfg_reg, + NULL, + NULL, + }, + { + "age_pful_cfg", + SE_AS_AGE_PFUL_CFGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000001ec, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_as_age_pful_cfg_reg, + NULL, + NULL, + }, + { + "etcam_rsp_cfg", + SE_AS_ETCAM_RSP_CFGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000001f4, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_se_as_etcam_rsp_cfg_reg, + NULL, + NULL, + }, + { + "pbu_ecc_bypass_read", + SE_AS_PBU_ECC_BYPASS_READr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000001fc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_as_pbu_ecc_bypass_read_reg, + NULL, + NULL, + }, + { + "etcam0_ecc_bypass_read", + SE_AS_ETCAM0_ECC_BYPASS_READr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000200, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_as_etcam0_ecc_bypass_read_reg, + NULL, + NULL, + }, + { + "etcam1_ecc_bypass_read", + SE_AS_ETCAM1_ECC_BYPASS_READr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000204, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_as_etcam1_ecc_bypass_read_reg, + NULL, + NULL, + }, + { + "lpm_ecc_bypass_read", + SE_AS_LPM_ECC_BYPASS_READr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000208, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_as_lpm_ecc_bypass_read_reg, + NULL, + NULL, + }, + { + "hash_ecc_bypass_read", + SE_AS_HASH_ECC_BYPASS_READr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x0000020c, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_se_as_hash_ecc_bypass_read_reg, + NULL, + NULL, + }, + { + "hash_learn_ecc_bypass_read", + SE_AS_HASH_LEARN_ECC_BYPASS_READr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000210, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_as_hash_learn_ecc_bypass_read_reg, + NULL, + NULL, + }, + { + "debug_cnt_mode", + SE_AS_DEBUG_CNT_MODEr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000003e8, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_se_as_debug_cnt_mode_reg, + NULL, + NULL, + }, + { + "as_int_0_en", + SE_AS_AS_INT_0_ENr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000440, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_as_as_int_0_en_reg, + NULL, + NULL, + }, + { + "as_int_0_mask", + SE_AS_AS_INT_0_MASKr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000444, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_as_as_int_0_mask_reg, + NULL, + NULL, + }, + { + "as_int_1_en", + SE_AS_AS_INT_1_ENr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000448, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_as_as_int_1_en_reg, + NULL, + NULL, + }, + { + "as_int_1_mask", + SE_AS_AS_INT_1_MASKr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x0000044c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_as_as_int_1_mask_reg, + NULL, + NULL, + }, + { + "as_int_2_en", + SE_AS_AS_INT_2_ENr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000450, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_as_as_int_2_en_reg, + NULL, + NULL, + }, + { + "as_int_2_mask", + SE_AS_AS_INT_2_MASKr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000454, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_as_as_int_2_mask_reg, + NULL, + NULL, + }, + { + "as_int_0_status", + SE_AS_AS_INT_0_STATUSr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000458, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_as_as_int_0_status_reg, + NULL, + NULL, + }, + { + "as_int_1_status", + SE_AS_AS_INT_1_STATUSr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x0000045c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_as_as_int_1_status_reg, + NULL, + NULL, + }, + { + "as_int_2_status", + SE_AS_AS_INT_2_STATUSr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000460, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_as_as_int_2_status_reg, + NULL, + NULL, + }, + { + "se_as_int_status", + SE_AS_SE_AS_INT_STATUSr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000464, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_se_as_se_as_int_status_reg, + NULL, + NULL, + }, + { + "hash0_3_wr_req_cnt", + SE_AS_HASH0_3_WR_REQ_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x0000082c, + (32/8), + 0, + 3 + 1, + 0, + 4, + 1, + g_se_as_hash0_3_wr_req_cnt_reg, + NULL, + NULL, + }, + { + "smmu0_etcam0_1_fc_cnt", + SE_AS_SMMU0_ETCAM0_1_FC_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x0000083c, + (32/8), + 0, + 0 + 1, + 0, + 4, + 1, + g_se_as_smmu0_etcam0_1_fc_cnt_reg, + NULL, + NULL, + }, + { + "etcam0_1_smmu0_req_cnt", + SE_AS_ETCAM0_1_SMMU0_REQ_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000844, + (32/8), + 0, + 0 + 1, + 0, + 8, + 1, + g_se_as_etcam0_1_smmu0_req_cnt_reg, + NULL, + NULL, + }, + { + "smmu0_etcam0_1_rsp_cnt", + SE_AS_SMMU0_ETCAM0_1_RSP_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000848, + (32/8), + 0, + 0 + 1, + 0, + 8, + 1, + g_se_as_smmu0_etcam0_1_rsp_cnt_reg, + NULL, + NULL, + }, + { + "as_hla_hash_p0_3_key_cnt", + SE_AS_AS_HLA_HASH_P0_3_KEY_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000854, + (32/8), + 0, + 3 + 1, + 0, + 4, + 1, + g_se_as_as_hla_hash_p0_3_key_cnt_reg, + NULL, + NULL, + }, + { + "as_hla_lpm_p0_key_cnt", + SE_AS_AS_HLA_LPM_P0_KEY_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000864, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_as_as_hla_lpm_p0_key_cnt_reg, + NULL, + NULL, + }, + { + "alg_as_hash_p0_3_rsp_cnt", + SE_AS_ALG_AS_HASH_P0_3_RSP_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000868, + (32/8), + 0, + 3 + 1, + 0, + 8, + 1, + g_se_as_alg_as_hash_p0_3_rsp_cnt_reg, + NULL, + NULL, + }, + { + "alg_as_hash_p0_3_smf_rsp_cnt", + SE_AS_ALG_AS_HASH_P0_3_SMF_RSP_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x0000086c, + (32/8), + 0, + 3 + 1, + 0, + 8, + 1, + g_se_as_alg_as_hash_p0_3_smf_rsp_cnt_reg, + NULL, + NULL, + }, + { + "alg_as_lpm_p0_rsp_cnt", + SE_AS_ALG_AS_LPM_P0_RSP_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000888, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_as_alg_as_lpm_p0_rsp_cnt_reg, + NULL, + NULL, + }, + { + "alg_as_lpm_p0_3_smf_rsp_cnt", + SE_AS_ALG_AS_LPM_P0_3_SMF_RSP_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x0000088c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_as_alg_as_lpm_p0_3_smf_rsp_cnt_reg, + NULL, + NULL, + }, + { + "as_pbu_key_cnt", + SE_AS_AS_PBU_KEY_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000890, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_as_as_pbu_key_cnt_reg, + NULL, + NULL, + }, + { + "pbu_se_dpi_rsp_dat_cnt", + SE_AS_PBU_SE_DPI_RSP_DAT_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000894, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_as_pbu_se_dpi_rsp_dat_cnt_reg, + NULL, + NULL, + }, + { + "as_etcam_ctrl_req0_cnt", + SE_AS_AS_ETCAM_CTRL_REQ0_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000898, + (32/8), + 0, + 0 + 1, + 0, + 4, + 1, + g_se_as_as_etcam_ctrl_req0_cnt_reg, + NULL, + NULL, + }, + { + "etcam_ctrl_as_index0_1_cnt", + SE_AS_ETCAM_CTRL_AS_INDEX0_1_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000008a0, + (32/8), + 0, + 0 + 1, + 0, + 8, + 1, + g_se_as_etcam_ctrl_as_index0_1_cnt_reg, + NULL, + NULL, + }, + { + "etcam_ctrl_as_hit0_1_cnt", + SE_AS_ETCAM_CTRL_AS_HIT0_1_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000008a4, + (32/8), + 0, + 0 + 1, + 0, + 8, + 1, + g_se_as_etcam_ctrl_as_hit0_1_cnt_reg, + NULL, + NULL, + }, + { + "as_smmu0_req_cnt", + SE_AS_AS_SMMU0_REQ_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000008b0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_as_as_smmu0_req_cnt_reg, + NULL, + NULL, + }, + { + "learn_hla_wr_cnt", + SE_AS_LEARN_HLA_WR_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000008b4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_as_learn_hla_wr_cnt_reg, + NULL, + NULL, + }, + { + "as_smmu1_req_cnt", + SE_AS_AS_SMMU1_REQ_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000008b8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_as_as_smmu1_req_cnt_reg, + NULL, + NULL, + }, + { + "se_cfg_mac_dat_cnt", + SE_AS_SE_CFG_MAC_DAT_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000008bc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_as_se_cfg_mac_dat_cnt_reg, + NULL, + NULL, + }, + { + "alg_as_hash_p0_3_fc_cnt", + SE_AS_ALG_AS_HASH_P0_3_FC_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000008c0, + (32/8), + 0, + 3 + 1, + 0, + 4, + 1, + g_se_as_alg_as_hash_p0_3_fc_cnt_reg, + NULL, + NULL, + }, + { + "alg_as_lpm_p0_fc_cnt", + SE_AS_ALG_AS_LPM_P0_FC_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000008d0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_as_alg_as_lpm_p0_fc_cnt_reg, + NULL, + NULL, + }, + { + "as_alg_hash_p0_3_fc_cnt", + SE_AS_AS_ALG_HASH_P0_3_FC_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000008d4, + (32/8), + 0, + 3 + 1, + 0, + 4, + 1, + g_se_as_as_alg_hash_p0_3_fc_cnt_reg, + NULL, + NULL, + }, + { + "as_alg_lpm_p0_fc_cnt", + SE_AS_AS_ALG_LPM_P0_FC_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000008e4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_as_as_alg_lpm_p0_fc_cnt_reg, + NULL, + NULL, + }, + { + "as_pbu_fc_cnt", + SE_AS_AS_PBU_FC_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000008e8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_as_as_pbu_fc_cnt_reg, + NULL, + NULL, + }, + { + "pbu_se_dpi_key_fc_cnt", + SE_AS_PBU_SE_DPI_KEY_FC_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000008ec, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_as_pbu_se_dpi_key_fc_cnt_reg, + NULL, + NULL, + }, + { + "as_etcam_ctrl_fc0_1_cnt", + SE_AS_AS_ETCAM_CTRL_FC0_1_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000008f0, + (32/8), + 0, + 0 + 1, + 0, + 4, + 1, + g_se_as_as_etcam_ctrl_fc0_1_cnt_reg, + NULL, + NULL, + }, + { + "etcam_ctrl_as_fc0_1_cnt", + SE_AS_ETCAM_CTRL_AS_FC0_1_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000008f8, + (32/8), + 0, + 0 + 1, + 0, + 4, + 1, + g_se_as_etcam_ctrl_as_fc0_1_cnt_reg, + NULL, + NULL, + }, + { + "smmu0_as_mac_age_fc_cnt", + SE_AS_SMMU0_AS_MAC_AGE_FC_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000900, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_as_smmu0_as_mac_age_fc_cnt_reg, + NULL, + NULL, + }, + { + "alg_learn_fc_cnt", + SE_AS_ALG_LEARN_FC_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000904, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_as_alg_learn_fc_cnt_reg, + NULL, + NULL, + }, + { + "smmu1_as_fc_cnt", + SE_AS_SMMU1_AS_FC_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000908, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_as_smmu1_as_fc_cnt_reg, + NULL, + NULL, + }, + { + "cfg_se_mac_fc_cnt", + SE_AS_CFG_SE_MAC_FC_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x0000090c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_as_cfg_se_mac_fc_cnt_reg, + NULL, + NULL, + }, + { + "kschd_cpu_rdy", + SE_KSCHD_KSCHD_CPU_RDYr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000018, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_kschd_kschd_cpu_rdy_reg, + NULL, + NULL, + }, + { + "ppu0_ecc_bypass_read", + SE_KSCHD_PPU0_ECC_BYPASS_READr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000024, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_kschd_ppu0_ecc_bypass_read_reg, + NULL, + NULL, + }, + { + "pbu_ecc_bypass_read", + SE_KSCHD_PBU_ECC_BYPASS_READr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000028, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_kschd_pbu_ecc_bypass_read_reg, + NULL, + NULL, + }, + { + "smmu1_ecc_bypass_read", + SE_KSCHD_SMMU1_ECC_BYPASS_READr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x0000002c, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_se_kschd_smmu1_ecc_bypass_read_reg, + NULL, + NULL, + }, + { + "ass_ecc_bypass_read", + SE_KSCHD_ASS_ECC_BYPASS_READr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000030, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_kschd_ass_ecc_bypass_read_reg, + NULL, + NULL, + }, + { + "sdt_h", + SE_KSCHD_SDT_Hr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000040, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_kschd_sdt_h_reg, + NULL, + NULL, + }, + { + "sdt_l", + SE_KSCHD_SDT_Lr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000044, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_kschd_sdt_l_reg, + NULL, + NULL, + }, + { + "hash_key15", + SE_KSCHD_HASH_KEY15r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000048, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_se_kschd_hash_key15_reg, + NULL, + NULL, + }, + { + "hash_key14", + SE_KSCHD_HASH_KEY14r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x0000004c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_kschd_hash_key14_reg, + NULL, + NULL, + }, + { + "hash_key13", + SE_KSCHD_HASH_KEY13r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000050, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_kschd_hash_key13_reg, + NULL, + NULL, + }, + { + "hash_key12", + SE_KSCHD_HASH_KEY12r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000054, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_kschd_hash_key12_reg, + NULL, + NULL, + }, + { + "hash_key11", + SE_KSCHD_HASH_KEY11r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000058, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_kschd_hash_key11_reg, + NULL, + NULL, + }, + { + "hash_key10", + SE_KSCHD_HASH_KEY10r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x0000005c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_kschd_hash_key10_reg, + NULL, + NULL, + }, + { + "hash_key9", + SE_KSCHD_HASH_KEY9r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000060, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_kschd_hash_key9_reg, + NULL, + NULL, + }, + { + "hash_key8", + SE_KSCHD_HASH_KEY8r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000064, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_kschd_hash_key8_reg, + NULL, + NULL, + }, + { + "hash_key7", + SE_KSCHD_HASH_KEY7r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000068, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_kschd_hash_key7_reg, + NULL, + NULL, + }, + { + "hash_key6", + SE_KSCHD_HASH_KEY6r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x0000006c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_kschd_hash_key6_reg, + NULL, + NULL, + }, + { + "hash_key5", + SE_KSCHD_HASH_KEY5r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000070, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_kschd_hash_key5_reg, + NULL, + NULL, + }, + { + "hash_key4", + SE_KSCHD_HASH_KEY4r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000074, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_kschd_hash_key4_reg, + NULL, + NULL, + }, + { + "hash_key3", + SE_KSCHD_HASH_KEY3r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000078, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_kschd_hash_key3_reg, + NULL, + NULL, + }, + { + "hash_key2", + SE_KSCHD_HASH_KEY2r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x0000007c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_kschd_hash_key2_reg, + NULL, + NULL, + }, + { + "hash_key1", + SE_KSCHD_HASH_KEY1r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000080, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_kschd_hash_key1_reg, + NULL, + NULL, + }, + { + "hash_key0", + SE_KSCHD_HASH_KEY0r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000084, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_kschd_hash_key0_reg, + NULL, + NULL, + }, + { + "schd_int_0_en", + SE_KSCHD_SCHD_INT_0_ENr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000000c0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_kschd_schd_int_0_en_reg, + NULL, + NULL, + }, + { + "schd_int_0_mask", + SE_KSCHD_SCHD_INT_0_MASKr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000000c4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_kschd_schd_int_0_mask_reg, + NULL, + NULL, + }, + { + "schd_int_1_en", + SE_KSCHD_SCHD_INT_1_ENr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000000c8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_kschd_schd_int_1_en_reg, + NULL, + NULL, + }, + { + "schd_int_1_mask", + SE_KSCHD_SCHD_INT_1_MASKr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000000cc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_kschd_schd_int_1_mask_reg, + NULL, + NULL, + }, + { + "schd_int_2_en", + SE_KSCHD_SCHD_INT_2_ENr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000000d0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_kschd_schd_int_2_en_reg, + NULL, + NULL, + }, + { + "schd_int_2_mask", + SE_KSCHD_SCHD_INT_2_MASKr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000000d4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_kschd_schd_int_2_mask_reg, + NULL, + NULL, + }, + { + "schd_int_3_en", + SE_KSCHD_SCHD_INT_3_ENr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000000d8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_kschd_schd_int_3_en_reg, + NULL, + NULL, + }, + { + "schd_int_3_mask", + SE_KSCHD_SCHD_INT_3_MASKr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000000dc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_kschd_schd_int_3_mask_reg, + NULL, + NULL, + }, + { + "schd_int_4_en", + SE_KSCHD_SCHD_INT_4_ENr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000000e0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_kschd_schd_int_4_en_reg, + NULL, + NULL, + }, + { + "schd_int_4_mask", + SE_KSCHD_SCHD_INT_4_MASKr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000000e4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_kschd_schd_int_4_mask_reg, + NULL, + NULL, + }, + { + "schd_int_0_status", + SE_KSCHD_SCHD_INT_0_STATUSr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000000e8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_kschd_schd_int_0_status_reg, + NULL, + NULL, + }, + { + "schd_int_1_status", + SE_KSCHD_SCHD_INT_1_STATUSr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000000ec, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_kschd_schd_int_1_status_reg, + NULL, + NULL, + }, + { + "schd_int_2_status", + SE_KSCHD_SCHD_INT_2_STATUSr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000000f0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_kschd_schd_int_2_status_reg, + NULL, + NULL, + }, + { + "schd_int_3_status", + SE_KSCHD_SCHD_INT_3_STATUSr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000000f4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_kschd_schd_int_3_status_reg, + NULL, + NULL, + }, + { + "schd_int_4_status", + SE_KSCHD_SCHD_INT_4_STATUSr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000000f8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_kschd_schd_int_4_status_reg, + NULL, + NULL, + }, + { + "se_kschd_int_status", + SE_KSCHD_SE_KSCHD_INT_STATUSr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000148, + (32/8), + 0, + 0, + 0, + 0, + 5, + g_se_kschd_se_kschd_int_status_reg, + NULL, + NULL, + }, + { + "debug_cnt_mode", + SE_KSCHD_DEBUG_CNT_MODEr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000003ec, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_se_kschd_debug_cnt_mode_reg, + NULL, + NULL, + }, + { + "se_parser_kschd_key0_3_cnt", + SE_KSCHD_SE_PARSER_KSCHD_KEY0_3_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000878, + (32/8), + 0, + 5 + 1, + 0, + 4, + 1, + g_se_kschd_se_parser_kschd_key0_3_cnt_reg, + NULL, + NULL, + }, + { + "se_smmu1_key0_3_cnt", + SE_KSCHD_SE_SMMU1_KEY0_3_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000890, + (32/8), + 0, + 3 + 1, + 0, + 4, + 1, + g_se_kschd_se_smmu1_key0_3_cnt_reg, + NULL, + NULL, + }, + { + "kschd_as_key0_cnt", + SE_KSCHD_KSCHD_AS_KEY0_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000008a0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_kschd_kschd_as_key0_cnt_reg, + NULL, + NULL, + }, + { + "kschd_as_key1_cnt", + SE_KSCHD_KSCHD_AS_KEY1_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000008a4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_kschd_kschd_as_key1_cnt_reg, + NULL, + NULL, + }, + { + "kschd_as_key2_cnt", + SE_KSCHD_KSCHD_AS_KEY2_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000008a8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_kschd_kschd_as_key2_cnt_reg, + NULL, + NULL, + }, + { + "kschd_as_key3_cnt", + SE_KSCHD_KSCHD_AS_KEY3_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000008ac, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_kschd_kschd_as_key3_cnt_reg, + NULL, + NULL, + }, + { + "kschd_as_key4_cnt", + SE_KSCHD_KSCHD_AS_KEY4_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000008b0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_kschd_kschd_as_key4_cnt_reg, + NULL, + NULL, + }, + { + "kschd_as_key5_cnt", + SE_KSCHD_KSCHD_AS_KEY5_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000008b4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_kschd_kschd_as_key5_cnt_reg, + NULL, + NULL, + }, + { + "kschd_as_key6_cnt", + SE_KSCHD_KSCHD_AS_KEY6_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000008b8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_kschd_kschd_as_key6_cnt_reg, + NULL, + NULL, + }, + { + "kschd_as_key9_cnt", + SE_KSCHD_KSCHD_AS_KEY9_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000008bc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_kschd_kschd_as_key9_cnt_reg, + NULL, + NULL, + }, + { + "kschd_se_parser_fc0_3_cnt", + SE_KSCHD_KSCHD_SE_PARSER_FC0_3_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000008c0, + (32/8), + 0, + 5 + 1, + 0, + 4, + 1, + g_se_kschd_kschd_se_parser_fc0_3_cnt_reg, + NULL, + NULL, + }, + { + "smmu1_se_fc0_3_cnt", + SE_KSCHD_SMMU1_SE_FC0_3_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000008d8, + (32/8), + 0, + 3 + 1, + 0, + 4, + 1, + g_se_kschd_smmu1_se_fc0_3_cnt_reg, + NULL, + NULL, + }, + { + "as_kschd_fc_cnt0", + SE_KSCHD_AS_KSCHD_FC_CNT0r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000008e8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_kschd_as_kschd_fc_cnt0_reg, + NULL, + NULL, + }, + { + "as_kschd_fc_cnt1", + SE_KSCHD_AS_KSCHD_FC_CNT1r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000008ec, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_kschd_as_kschd_fc_cnt1_reg, + NULL, + NULL, + }, + { + "as_kschd_fc_cnt2", + SE_KSCHD_AS_KSCHD_FC_CNT2r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000008f0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_kschd_as_kschd_fc_cnt2_reg, + NULL, + NULL, + }, + { + "as_kschd_fc_cnt3", + SE_KSCHD_AS_KSCHD_FC_CNT3r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000008f4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_kschd_as_kschd_fc_cnt3_reg, + NULL, + NULL, + }, + { + "as_kschd_fc_cnt4", + SE_KSCHD_AS_KSCHD_FC_CNT4r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000008f8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_kschd_as_kschd_fc_cnt4_reg, + NULL, + NULL, + }, + { + "as_kschd_fc_cnt5", + SE_KSCHD_AS_KSCHD_FC_CNT5r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000008fc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_kschd_as_kschd_fc_cnt5_reg, + NULL, + NULL, + }, + { + "as_kschd_fc_cnt6", + SE_KSCHD_AS_KSCHD_FC_CNT6r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000900, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_kschd_as_kschd_fc_cnt6_reg, + NULL, + NULL, + }, + { + "as_kschd_fc_cnt9", + SE_KSCHD_AS_KSCHD_FC_CNT9r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000904, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_kschd_as_kschd_fc_cnt9_reg, + NULL, + NULL, + }, + { + "rschd_hash_pful_cfg", + SE_RSCHD_RSCHD_HASH_PFUL_CFGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000008, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_rschd_rschd_hash_pful_cfg_reg, + NULL, + NULL, + }, + { + "rschd_hash_ept_cfg", + SE_RSCHD_RSCHD_HASH_EPT_CFGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x0000000c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_rschd_rschd_hash_ept_cfg_reg, + NULL, + NULL, + }, + { + "rschd_pbu_pful_cfg", + SE_RSCHD_RSCHD_PBU_PFUL_CFGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000010, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_rschd_rschd_pbu_pful_cfg_reg, + NULL, + NULL, + }, + { + "rschd_pbu_ept_cfg", + SE_RSCHD_RSCHD_PBU_EPT_CFGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000014, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_rschd_rschd_pbu_ept_cfg_reg, + NULL, + NULL, + }, + { + "rschd_lpm_pful_cfg", + SE_RSCHD_RSCHD_LPM_PFUL_CFGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000018, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_rschd_rschd_lpm_pful_cfg_reg, + NULL, + NULL, + }, + { + "rschd_lpm_ept_cfg", + SE_RSCHD_RSCHD_LPM_EPT_CFGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x0000001c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_rschd_rschd_lpm_ept_cfg_reg, + NULL, + NULL, + }, + { + "rschd_etcam_pful_cfg", + SE_RSCHD_RSCHD_ETCAM_PFUL_CFGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000020, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_rschd_rschd_etcam_pful_cfg_reg, + NULL, + NULL, + }, + { + "rschd_etcam_ept_cfg", + SE_RSCHD_RSCHD_ETCAM_EPT_CFGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000024, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_rschd_rschd_etcam_ept_cfg_reg, + NULL, + NULL, + }, + { + "smmu0_wb_pful_cfg", + SE_RSCHD_SMMU0_WB_PFUL_CFGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000040, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_rschd_smmu0_wb_pful_cfg_reg, + NULL, + NULL, + }, + { + "smmu0_wb_ept_cfg", + SE_RSCHD_SMMU0_WB_EPT_CFGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000044, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_rschd_smmu0_wb_ept_cfg_reg, + NULL, + NULL, + }, + { + "smmu1_wb_pful_cfg", + SE_RSCHD_SMMU1_WB_PFUL_CFGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000048, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_rschd_smmu1_wb_pful_cfg_reg, + NULL, + NULL, + }, + { + "smmu1_wb_ept_cfg", + SE_RSCHD_SMMU1_WB_EPT_CFGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x0000004c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_rschd_smmu1_wb_ept_cfg_reg, + NULL, + NULL, + }, + { + "alg_wb_pful_cfg", + SE_RSCHD_ALG_WB_PFUL_CFGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000050, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_rschd_alg_wb_pful_cfg_reg, + NULL, + NULL, + }, + { + "alg_wb_ept_cfg", + SE_RSCHD_ALG_WB_EPT_CFGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000054, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_rschd_alg_wb_ept_cfg_reg, + NULL, + NULL, + }, + { + "wr_rsp_vld_en", + SE_RSCHD_WR_RSP_VLD_ENr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000058, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_rschd_wr_rsp_vld_en_reg, + NULL, + NULL, + }, + { + "nppu_wb_pful_cfg", + SE_RSCHD_NPPU_WB_PFUL_CFGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x0000005c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_rschd_nppu_wb_pful_cfg_reg, + NULL, + NULL, + }, + { + "nppu_wb_ept_cfg", + SE_RSCHD_NPPU_WB_EPT_CFGr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000060, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_rschd_nppu_wb_ept_cfg_reg, + NULL, + NULL, + }, + { + "port0_int_en", + SE_RSCHD_PORT0_INT_ENr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000000c0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_rschd_port0_int_en_reg, + NULL, + NULL, + }, + { + "port0_int_mask", + SE_RSCHD_PORT0_INT_MASKr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000000c4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_rschd_port0_int_mask_reg, + NULL, + NULL, + }, + { + "port1_int_en", + SE_RSCHD_PORT1_INT_ENr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000000c8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_rschd_port1_int_en_reg, + NULL, + NULL, + }, + { + "port1_int_mask", + SE_RSCHD_PORT1_INT_MASKr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000000cc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_rschd_port1_int_mask_reg, + NULL, + NULL, + }, + { + "port0_int_status", + SE_RSCHD_PORT0_INT_STATUSr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000000d0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_rschd_port0_int_status_reg, + NULL, + NULL, + }, + { + "port1_int_status", + SE_RSCHD_PORT1_INT_STATUSr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000000d4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_rschd_port1_int_status_reg, + NULL, + NULL, + }, + { + "se_rschd_int_status", + SE_RSCHD_SE_RSCHD_INT_STATUSr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x0000018c, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_se_rschd_se_rschd_int_status_reg, + NULL, + NULL, + }, + { + "debug_cnt_mode", + SE_RSCHD_DEBUG_CNT_MODEr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000003ec, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_se_rschd_debug_cnt_mode_reg, + NULL, + NULL, + }, + { + "se_ppu_mex0_5_rsp1_cnt", + SE_RSCHD_SE_PPU_MEX0_5_RSP1_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000880, + (32/8), + 0, + 5 + 1, + 0, + 4, + 1, + g_se_rschd_se_ppu_mex0_5_rsp1_cnt_reg, + NULL, + NULL, + }, + { + "as_rschd_rsp0_cnt", + SE_RSCHD_AS_RSCHD_RSP0_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000898, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_rschd_as_rschd_rsp0_cnt_reg, + NULL, + NULL, + }, + { + "as_rschd_rsp1_cnt", + SE_RSCHD_AS_RSCHD_RSP1_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x0000089c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_rschd_as_rschd_rsp1_cnt_reg, + NULL, + NULL, + }, + { + "as_rschd_rsp2_cnt", + SE_RSCHD_AS_RSCHD_RSP2_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000008a0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_rschd_as_rschd_rsp2_cnt_reg, + NULL, + NULL, + }, + { + "as_rschd_rsp3_cnt", + SE_RSCHD_AS_RSCHD_RSP3_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000008a4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_rschd_as_rschd_rsp3_cnt_reg, + NULL, + NULL, + }, + { + "as_rschd_rsp4_cnt", + SE_RSCHD_AS_RSCHD_RSP4_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000008a8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_rschd_as_rschd_rsp4_cnt_reg, + NULL, + NULL, + }, + { + "as_rschd_rsp5_cnt", + SE_RSCHD_AS_RSCHD_RSP5_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000008ac, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_rschd_as_rschd_rsp5_cnt_reg, + NULL, + NULL, + }, + { + "as_rschd_rsp6_cnt", + SE_RSCHD_AS_RSCHD_RSP6_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000008b0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_rschd_as_rschd_rsp6_cnt_reg, + NULL, + NULL, + }, + { + "as_rschd_rsp9_cnt", + SE_RSCHD_AS_RSCHD_RSP9_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000008b4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_rschd_as_rschd_rsp9_cnt_reg, + NULL, + NULL, + }, + { + "smmu1_se_rsp0_3_cnt", + SE_RSCHD_SMMU1_SE_RSP0_3_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000008b8, + (32/8), + 0, + 3 + 1, + 0, + 4, + 1, + g_se_rschd_smmu1_se_rsp0_3_cnt_reg, + NULL, + NULL, + }, + { + "ppu_se_mex0_3_fc_cnt", + SE_RSCHD_PPU_SE_MEX0_3_FC_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000008c4, + (32/8), + 0, + 5 + 1, + 0, + 4, + 1, + g_se_rschd_ppu_se_mex0_3_fc_cnt_reg, + NULL, + NULL, + }, + { + "rschd_as_fc_cnt0", + SE_RSCHD_RSCHD_AS_FC_CNT0r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000008e0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_rschd_rschd_as_fc_cnt0_reg, + NULL, + NULL, + }, + { + "rschd_as_fc_cnt1", + SE_RSCHD_RSCHD_AS_FC_CNT1r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000008e4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_rschd_rschd_as_fc_cnt1_reg, + NULL, + NULL, + }, + { + "rschd_as_fc_cnt2", + SE_RSCHD_RSCHD_AS_FC_CNT2r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000008e8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_rschd_rschd_as_fc_cnt2_reg, + NULL, + NULL, + }, + { + "rschd_as_fc_cnt3", + SE_RSCHD_RSCHD_AS_FC_CNT3r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000008ec, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_rschd_rschd_as_fc_cnt3_reg, + NULL, + NULL, + }, + { + "rschd_as_fc_cnt4", + SE_RSCHD_RSCHD_AS_FC_CNT4r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000008f0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_rschd_rschd_as_fc_cnt4_reg, + NULL, + NULL, + }, + { + "rschd_as_fc_cnt5", + SE_RSCHD_RSCHD_AS_FC_CNT5r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000008f4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_rschd_rschd_as_fc_cnt5_reg, + NULL, + NULL, + }, + { + "rschd_as_fc_cnt6", + SE_RSCHD_RSCHD_AS_FC_CNT6r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000008f8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_rschd_rschd_as_fc_cnt6_reg, + NULL, + NULL, + }, + { + "rschd_as_fc_cnt9", + SE_RSCHD_RSCHD_AS_FC_CNT9r, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000008fc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_rschd_rschd_as_fc_cnt9_reg, + NULL, + NULL, + }, + { + "se_smmu1_fc0_3_cnt", + SE_RSCHD_SE_SMMU1_FC0_3_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000900, + (32/8), + 0, + 3 + 1, + 0, + 4, + 1, + g_se_rschd_se_smmu1_fc0_3_cnt_reg, + NULL, + NULL, + }, + { + "smmu0_se_wr_done_cnt", + SE_RSCHD_SMMU0_SE_WR_DONE_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000910, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_rschd_smmu0_se_wr_done_cnt_reg, + NULL, + NULL, + }, + { + "se_smmu0_wr_done_fc_cnt", + SE_RSCHD_SE_SMMU0_WR_DONE_FC_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000914, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_rschd_se_smmu0_wr_done_fc_cnt_reg, + NULL, + NULL, + }, + { + "smmu1_se_wr_rsp_cnt", + SE_RSCHD_SMMU1_SE_WR_RSP_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000918, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_rschd_smmu1_se_wr_rsp_cnt_reg, + NULL, + NULL, + }, + { + "se_smmu1_wr_rsp_fc_cnt", + SE_RSCHD_SE_SMMU1_WR_RSP_FC_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x0000091c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_rschd_se_smmu1_wr_rsp_fc_cnt_reg, + NULL, + NULL, + }, + { + "alg_se_wr_rsp_cnt", + SE_RSCHD_ALG_SE_WR_RSP_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000920, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_rschd_alg_se_wr_rsp_cnt_reg, + NULL, + NULL, + }, + { + "se_alg_wr_rsp_fc_cnt", + SE_RSCHD_SE_ALG_WR_RSP_FC_CNTr, + SE, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000924, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_rschd_se_alg_wr_rsp_fc_cnt_reg, + NULL, + NULL, + }, + { + "kschd_pful_cfg0", + SMMU0_SMMU0_KSCHD_PFUL_CFG0r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000080, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_smmu0_smmu0_kschd_pful_cfg0_reg, + NULL, + NULL, + }, + { + "kschd_pful_cfg1", + SMMU0_SMMU0_KSCHD_PFUL_CFG1r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000084, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_smmu0_smmu0_kschd_pful_cfg1_reg, + NULL, + NULL, + }, + { + "ctrl_pful1_cfg", + SMMU0_SMMU0_CTRL_PFUL1_CFGr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000088, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_smmu0_smmu0_ctrl_pful1_cfg_reg, + NULL, + NULL, + }, + { + "ctrl_pful2_cfg", + SMMU0_SMMU0_CTRL_PFUL2_CFGr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000008c, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_smmu0_smmu0_ctrl_pful2_cfg_reg, + NULL, + NULL, + }, + { + "ctrl_pful3_cfg", + SMMU0_SMMU0_CTRL_PFUL3_CFGr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000090, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_smmu0_smmu0_ctrl_pful3_cfg_reg, + NULL, + NULL, + }, + { + "rschd_pful_cfg", + SMMU0_SMMU0_RSCHD_PFUL_CFGr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000094, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_smmu0_smmu0_rschd_pful_cfg_reg, + NULL, + NULL, + }, + { + "rschd_ept_cfg", + SMMU0_SMMU0_RSCHD_EPT_CFGr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000098, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_smmu0_smmu0_rschd_ept_cfg_reg, + NULL, + NULL, + }, + { + "alucmd_pful_cfg", + SMMU0_SMMU0_ALUCMD_PFUL_CFGr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000009c, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_smmu0_smmu0_alucmd_pful_cfg_reg, + NULL, + NULL, + }, + { + "aluwr_pful_cfg", + SMMU0_SMMU0_ALUWR_PFUL_CFGr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000000a0, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_smmu0_smmu0_aluwr_pful_cfg_reg, + NULL, + NULL, + }, + { + "wr_arb_pful_cfg0", + SMMU0_SMMU0_WR_ARB_PFUL_CFG0r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000000a4, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_smmu0_smmu0_wr_arb_pful_cfg0_reg, + NULL, + NULL, + }, + { + "wr_arb_pful_cfg1", + SMMU0_SMMU0_WR_ARB_PFUL_CFG1r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000000a8, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_smmu0_smmu0_wr_arb_pful_cfg1_reg, + NULL, + NULL, + }, + { + "ord_pful_cfg", + SMMU0_SMMU0_ORD_PFUL_CFGr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000000ac, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_smmu0_smmu0_ord_pful_cfg_reg, + NULL, + NULL, + }, + { + "cfg_dma_baddr", + SMMU0_SMMU0_CFG_DMA_BADDRr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000000c0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_cfg_dma_baddr_reg, + NULL, + NULL, + }, + { + "cfg_odma0_baddr", + SMMU0_SMMU0_CFG_ODMA0_BADDRr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000000c4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_cfg_odma0_baddr_reg, + NULL, + NULL, + }, + { + "cfg_odma1_baddr", + SMMU0_SMMU0_CFG_ODMA1_BADDRr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000000c8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_cfg_odma1_baddr_reg, + NULL, + NULL, + }, + { + "cfg_odma2_baddr", + SMMU0_SMMU0_CFG_ODMA2_BADDRr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000000cc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_cfg_odma2_baddr_reg, + NULL, + NULL, + }, + { + "cfg_odma_tdm_baddr", + SMMU0_SMMU0_CFG_ODMA_TDM_BADDRr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000000d0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_cfg_odma_tdm_baddr_reg, + NULL, + NULL, + }, + { + "cfg_mcast_baddr", + SMMU0_SMMU0_CFG_MCAST_BADDRr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000000d4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_cfg_mcast_baddr_reg, + NULL, + NULL, + }, + { + "cfg_lpm0", + SMMU0_SMMU0_CFG_LPM0r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000000d8, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_smmu0_smmu0_cfg_lpm0_reg, + NULL, + NULL, + }, + { + "cfg_lpm1", + SMMU0_SMMU0_CFG_LPM1r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000000dc, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_smmu0_smmu0_cfg_lpm1_reg, + NULL, + NULL, + }, + { + "cfg_lpm2", + SMMU0_SMMU0_CFG_LPM2r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000000e0, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_smmu0_smmu0_cfg_lpm2_reg, + NULL, + NULL, + }, + { + "cfg_lpm3", + SMMU0_SMMU0_CFG_LPM3r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000000e4, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_smmu0_smmu0_cfg_lpm3_reg, + NULL, + NULL, + }, + { + "cfg_lpm4", + SMMU0_SMMU0_CFG_LPM4r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000000e8, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_smmu0_smmu0_cfg_lpm4_reg, + NULL, + NULL, + }, + { + "cfg_lpm5", + SMMU0_SMMU0_CFG_LPM5r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000000ec, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_smmu0_smmu0_cfg_lpm5_reg, + NULL, + NULL, + }, + { + "cfg_lpm6", + SMMU0_SMMU0_CFG_LPM6r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000000f0, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_smmu0_smmu0_cfg_lpm6_reg, + NULL, + NULL, + }, + { + "cfg_lpm7", + SMMU0_SMMU0_CFG_LPM7r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000000f4, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_smmu0_smmu0_cfg_lpm7_reg, + NULL, + NULL, + }, + { + "debug_cnt_mode", + SMMU0_SMMU0_DEBUG_CNT_MODEr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000100, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_smmu0_smmu0_debug_cnt_mode_reg, + NULL, + NULL, + }, + { + "stat_overflow_mode", + SMMU0_SMMU0_STAT_OVERFLOW_MODEr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000104, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_stat_overflow_mode_reg, + NULL, + NULL, + }, + { + "init_en_cfg_tmp", + SMMU0_SMMU0_INIT_EN_CFG_TMPr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000013c, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_init_en_cfg_tmp_reg, + NULL, + NULL, + }, + { + "smmu0_int_unmask_flag", + SMMU0_SMMU0_SMMU0_INT_UNMASK_FLAGr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000140, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int_unmask_flag_reg, + NULL, + NULL, + }, + { + "smmu0_int0_en", + SMMU0_SMMU0_SMMU0_INT0_ENr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000144, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int0_en_reg, + NULL, + NULL, + }, + { + "smmu0_int0_mask", + SMMU0_SMMU0_SMMU0_INT0_MASKr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000148, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int0_mask_reg, + NULL, + NULL, + }, + { + "smmu0_int0_status", + SMMU0_SMMU0_SMMU0_INT0_STATUSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000014c, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int0_status_reg, + NULL, + NULL, + }, + { + "smmu0_int1_en", + SMMU0_SMMU0_SMMU0_INT1_ENr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000150, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int1_en_reg, + NULL, + NULL, + }, + { + "smmu0_int1_mask", + SMMU0_SMMU0_SMMU0_INT1_MASKr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000154, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int1_mask_reg, + NULL, + NULL, + }, + { + "smmu0_int1_status", + SMMU0_SMMU0_SMMU0_INT1_STATUSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000158, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int1_status_reg, + NULL, + NULL, + }, + { + "smmu0_int2_en", + SMMU0_SMMU0_SMMU0_INT2_ENr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000015c, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int2_en_reg, + NULL, + NULL, + }, + { + "smmu0_int2_mask", + SMMU0_SMMU0_SMMU0_INT2_MASKr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000160, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int2_mask_reg, + NULL, + NULL, + }, + { + "smmu0_int2_status", + SMMU0_SMMU0_SMMU0_INT2_STATUSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000164, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int2_status_reg, + NULL, + NULL, + }, + { + "smmu0_int3_en", + SMMU0_SMMU0_SMMU0_INT3_ENr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000168, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int3_en_reg, + NULL, + NULL, + }, + { + "smmu0_int3_mask", + SMMU0_SMMU0_SMMU0_INT3_MASKr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000016c, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int3_mask_reg, + NULL, + NULL, + }, + { + "smmu0_int3_status", + SMMU0_SMMU0_SMMU0_INT3_STATUSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000170, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int3_status_reg, + NULL, + NULL, + }, + { + "smmu0_int4_en", + SMMU0_SMMU0_SMMU0_INT4_ENr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000174, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int4_en_reg, + NULL, + NULL, + }, + { + "smmu0_int4_mask", + SMMU0_SMMU0_SMMU0_INT4_MASKr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000178, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int4_mask_reg, + NULL, + NULL, + }, + { + "smmu0_int4_status", + SMMU0_SMMU0_SMMU0_INT4_STATUSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000017c, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int4_status_reg, + NULL, + NULL, + }, + { + "smmu0_int5_en", + SMMU0_SMMU0_SMMU0_INT5_ENr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000180, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int5_en_reg, + NULL, + NULL, + }, + { + "smmu0_int5_mask", + SMMU0_SMMU0_SMMU0_INT5_MASKr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000184, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int5_mask_reg, + NULL, + NULL, + }, + { + "smmu0_int5_status", + SMMU0_SMMU0_SMMU0_INT5_STATUSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000188, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int5_status_reg, + NULL, + NULL, + }, + { + "smmu0_int6_en", + SMMU0_SMMU0_SMMU0_INT6_ENr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000018c, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int6_en_reg, + NULL, + NULL, + }, + { + "smmu0_int6_mask", + SMMU0_SMMU0_SMMU0_INT6_MASKr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000190, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int6_mask_reg, + NULL, + NULL, + }, + { + "smmu0_int6_status", + SMMU0_SMMU0_SMMU0_INT6_STATUSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000194, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int6_status_reg, + NULL, + NULL, + }, + { + "smmu0_int7_en", + SMMU0_SMMU0_SMMU0_INT7_ENr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000198, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int7_en_reg, + NULL, + NULL, + }, + { + "smmu0_int7_mask", + SMMU0_SMMU0_SMMU0_INT7_MASKr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000019c, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int7_mask_reg, + NULL, + NULL, + }, + { + "smmu0_int7_status", + SMMU0_SMMU0_SMMU0_INT7_STATUSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001a0, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int7_status_reg, + NULL, + NULL, + }, + { + "smmu0_int8_en", + SMMU0_SMMU0_SMMU0_INT8_ENr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001a4, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int8_en_reg, + NULL, + NULL, + }, + { + "smmu0_int8_mask", + SMMU0_SMMU0_SMMU0_INT8_MASKr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001a8, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int8_mask_reg, + NULL, + NULL, + }, + { + "smmu0_int8_status", + SMMU0_SMMU0_SMMU0_INT8_STATUSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001ac, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int8_status_reg, + NULL, + NULL, + }, + { + "smmu0_int9_en", + SMMU0_SMMU0_SMMU0_INT9_ENr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001b0, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int9_en_reg, + NULL, + NULL, + }, + { + "smmu0_int9_mask", + SMMU0_SMMU0_SMMU0_INT9_MASKr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001b4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int9_mask_reg, + NULL, + NULL, + }, + { + "smmu0_int9_status", + SMMU0_SMMU0_SMMU0_INT9_STATUSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001b8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int9_status_reg, + NULL, + NULL, + }, + { + "smmu0_int10_en", + SMMU0_SMMU0_SMMU0_INT10_ENr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001bc, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int10_en_reg, + NULL, + NULL, + }, + { + "smmu0_int10_mask", + SMMU0_SMMU0_SMMU0_INT10_MASKr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001c0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int10_mask_reg, + NULL, + NULL, + }, + { + "smmu0_int10_status", + SMMU0_SMMU0_SMMU0_INT10_STATUSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001c4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int10_status_reg, + NULL, + NULL, + }, + { + "smmu0_int11_en", + SMMU0_SMMU0_SMMU0_INT11_ENr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001c8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int11_en_reg, + NULL, + NULL, + }, + { + "smmu0_int11_mask", + SMMU0_SMMU0_SMMU0_INT11_MASKr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001cc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int11_mask_reg, + NULL, + NULL, + }, + { + "smmu0_int11_status", + SMMU0_SMMU0_SMMU0_INT11_STATUSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001d0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int11_status_reg, + NULL, + NULL, + }, + { + "smmu0_int12_en", + SMMU0_SMMU0_SMMU0_INT12_ENr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001d4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int12_en_reg, + NULL, + NULL, + }, + { + "smmu0_int12_mask", + SMMU0_SMMU0_SMMU0_INT12_MASKr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001d8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int12_mask_reg, + NULL, + NULL, + }, + { + "smmu0_int12_status", + SMMU0_SMMU0_SMMU0_INT12_STATUSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001dc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int12_status_reg, + NULL, + NULL, + }, + { + "smmu0_int13_en", + SMMU0_SMMU0_SMMU0_INT13_ENr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001e0, + (32/8), + 0, + 0, + 0, + 0, + 20, + g_smmu0_smmu0_smmu0_int13_en_reg, + NULL, + NULL, + }, + { + "smmu0_int13_mask", + SMMU0_SMMU0_SMMU0_INT13_MASKr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001e4, + (32/8), + 0, + 0, + 0, + 0, + 20, + g_smmu0_smmu0_smmu0_int13_mask_reg, + NULL, + NULL, + }, + { + "smmu0_int13_status", + SMMU0_SMMU0_SMMU0_INT13_STATUSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001e8, + (32/8), + 0, + 0, + 0, + 0, + 20, + g_smmu0_smmu0_smmu0_int13_status_reg, + NULL, + NULL, + }, + { + "smmu0_int14_en", + SMMU0_SMMU0_SMMU0_INT14_ENr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001ec, + (32/8), + 0, + 0, + 0, + 0, + 17, + g_smmu0_smmu0_smmu0_int14_en_reg, + NULL, + NULL, + }, + { + "smmu0_int14_mask", + SMMU0_SMMU0_SMMU0_INT14_MASKr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001f0, + (32/8), + 0, + 0, + 0, + 0, + 17, + g_smmu0_smmu0_smmu0_int14_mask_reg, + NULL, + NULL, + }, + { + "smmu0_int14_status", + SMMU0_SMMU0_SMMU0_INT14_STATUSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001f4, + (32/8), + 0, + 0, + 0, + 0, + 17, + g_smmu0_smmu0_smmu0_int14_status_reg, + NULL, + NULL, + }, + { + "smmu0_ecc_unmask_flag", + SMMU0_SMMU0_SMMU0_ECC_UNMASK_FLAGr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001f8, + (32/8), + 0, + 0, + 0, + 0, + 22, + g_smmu0_smmu0_smmu0_ecc_unmask_flag_reg, + NULL, + NULL, + }, + { + "smmu0_int15_en", + SMMU0_SMMU0_SMMU0_INT15_ENr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001fc, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int15_en_reg, + NULL, + NULL, + }, + { + "smmu0_int15_mask", + SMMU0_SMMU0_SMMU0_INT15_MASKr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000200, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int15_mask_reg, + NULL, + NULL, + }, + { + "smmu0_int15_status", + SMMU0_SMMU0_SMMU0_INT15_STATUSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000204, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int15_status_reg, + NULL, + NULL, + }, + { + "smmu0_int16_en", + SMMU0_SMMU0_SMMU0_INT16_ENr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000208, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int16_en_reg, + NULL, + NULL, + }, + { + "smmu0_int16_mask", + SMMU0_SMMU0_SMMU0_INT16_MASKr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000020c, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int16_mask_reg, + NULL, + NULL, + }, + { + "smmu0_int16_status", + SMMU0_SMMU0_SMMU0_INT16_STATUSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000210, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int16_status_reg, + NULL, + NULL, + }, + { + "smmu0_int17_en", + SMMU0_SMMU0_SMMU0_INT17_ENr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000214, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int17_en_reg, + NULL, + NULL, + }, + { + "smmu0_int17_mask", + SMMU0_SMMU0_SMMU0_INT17_MASKr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000218, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int17_mask_reg, + NULL, + NULL, + }, + { + "smmu0_int17_status", + SMMU0_SMMU0_SMMU0_INT17_STATUSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000021c, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int17_status_reg, + NULL, + NULL, + }, + { + "smmu0_int18_en", + SMMU0_SMMU0_SMMU0_INT18_ENr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000220, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int18_en_reg, + NULL, + NULL, + }, + { + "smmu0_int18_mask", + SMMU0_SMMU0_SMMU0_INT18_MASKr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000224, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int18_mask_reg, + NULL, + NULL, + }, + { + "smmu0_int18_status", + SMMU0_SMMU0_SMMU0_INT18_STATUSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000228, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int18_status_reg, + NULL, + NULL, + }, + { + "smmu0_int19_en", + SMMU0_SMMU0_SMMU0_INT19_ENr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000022c, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int19_en_reg, + NULL, + NULL, + }, + { + "smmu0_int19_mask", + SMMU0_SMMU0_SMMU0_INT19_MASKr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000230, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int19_mask_reg, + NULL, + NULL, + }, + { + "smmu0_int19_status", + SMMU0_SMMU0_SMMU0_INT19_STATUSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000234, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int19_status_reg, + NULL, + NULL, + }, + { + "smmu0_int20_en", + SMMU0_SMMU0_SMMU0_INT20_ENr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000238, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int20_en_reg, + NULL, + NULL, + }, + { + "smmu0_int20_mask", + SMMU0_SMMU0_SMMU0_INT20_MASKr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000023c, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int20_mask_reg, + NULL, + NULL, + }, + { + "smmu0_int20_status", + SMMU0_SMMU0_SMMU0_INT20_STATUSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000240, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int20_status_reg, + NULL, + NULL, + }, + { + "smmu0_int21_en", + SMMU0_SMMU0_SMMU0_INT21_ENr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000244, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int21_en_reg, + NULL, + NULL, + }, + { + "smmu0_int21_mask", + SMMU0_SMMU0_SMMU0_INT21_MASKr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000248, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int21_mask_reg, + NULL, + NULL, + }, + { + "smmu0_int21_status", + SMMU0_SMMU0_SMMU0_INT21_STATUSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000024c, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int21_status_reg, + NULL, + NULL, + }, + { + "smmu0_int22_en", + SMMU0_SMMU0_SMMU0_INT22_ENr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000250, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int22_en_reg, + NULL, + NULL, + }, + { + "smmu0_int22_mask", + SMMU0_SMMU0_SMMU0_INT22_MASKr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000254, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int22_mask_reg, + NULL, + NULL, + }, + { + "smmu0_int22_status", + SMMU0_SMMU0_SMMU0_INT22_STATUSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000258, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int22_status_reg, + NULL, + NULL, + }, + { + "smmu0_int23_en", + SMMU0_SMMU0_SMMU0_INT23_ENr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000025c, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int23_en_reg, + NULL, + NULL, + }, + { + "smmu0_int23_mask", + SMMU0_SMMU0_SMMU0_INT23_MASKr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000260, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int23_mask_reg, + NULL, + NULL, + }, + { + "smmu0_int23_status", + SMMU0_SMMU0_SMMU0_INT23_STATUSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000264, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int23_status_reg, + NULL, + NULL, + }, + { + "smmu0_int24_en", + SMMU0_SMMU0_SMMU0_INT24_ENr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000268, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int24_en_reg, + NULL, + NULL, + }, + { + "smmu0_int24_mask", + SMMU0_SMMU0_SMMU0_INT24_MASKr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000026c, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int24_mask_reg, + NULL, + NULL, + }, + { + "smmu0_int24_status", + SMMU0_SMMU0_SMMU0_INT24_STATUSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000270, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int24_status_reg, + NULL, + NULL, + }, + { + "smmu0_int25_en", + SMMU0_SMMU0_SMMU0_INT25_ENr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000274, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int25_en_reg, + NULL, + NULL, + }, + { + "smmu0_int25_mask", + SMMU0_SMMU0_SMMU0_INT25_MASKr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000278, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int25_mask_reg, + NULL, + NULL, + }, + { + "smmu0_int25_status", + SMMU0_SMMU0_SMMU0_INT25_STATUSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000027c, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int25_status_reg, + NULL, + NULL, + }, + { + "smmu0_int26_en", + SMMU0_SMMU0_SMMU0_INT26_ENr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000280, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int26_en_reg, + NULL, + NULL, + }, + { + "smmu0_int26_mask", + SMMU0_SMMU0_SMMU0_INT26_MASKr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000284, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int26_mask_reg, + NULL, + NULL, + }, + { + "smmu0_int26_status", + SMMU0_SMMU0_SMMU0_INT26_STATUSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000288, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int26_status_reg, + NULL, + NULL, + }, + { + "smmu0_int27_en", + SMMU0_SMMU0_SMMU0_INT27_ENr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000028c, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int27_en_reg, + NULL, + NULL, + }, + { + "smmu0_int27_mask", + SMMU0_SMMU0_SMMU0_INT27_MASKr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000290, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int27_mask_reg, + NULL, + NULL, + }, + { + "smmu0_int27_status", + SMMU0_SMMU0_SMMU0_INT27_STATUSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000294, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int27_status_reg, + NULL, + NULL, + }, + { + "smmu0_int28_en", + SMMU0_SMMU0_SMMU0_INT28_ENr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000298, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int28_en_reg, + NULL, + NULL, + }, + { + "smmu0_int28_mask", + SMMU0_SMMU0_SMMU0_INT28_MASKr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000029c, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int28_mask_reg, + NULL, + NULL, + }, + { + "smmu0_int28_status", + SMMU0_SMMU0_SMMU0_INT28_STATUSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002a0, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int28_status_reg, + NULL, + NULL, + }, + { + "smmu0_int29_en", + SMMU0_SMMU0_SMMU0_INT29_ENr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002a4, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int29_en_reg, + NULL, + NULL, + }, + { + "smmu0_int29_mask", + SMMU0_SMMU0_SMMU0_INT29_MASKr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002a8, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int29_mask_reg, + NULL, + NULL, + }, + { + "smmu0_int29_status", + SMMU0_SMMU0_SMMU0_INT29_STATUSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002ac, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int29_status_reg, + NULL, + NULL, + }, + { + "smmu0_int30_en", + SMMU0_SMMU0_SMMU0_INT30_ENr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002b0, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int30_en_reg, + NULL, + NULL, + }, + { + "smmu0_int30_mask", + SMMU0_SMMU0_SMMU0_INT30_MASKr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002b4, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int30_mask_reg, + NULL, + NULL, + }, + { + "smmu0_int30_status", + SMMU0_SMMU0_SMMU0_INT30_STATUSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002b8, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int30_status_reg, + NULL, + NULL, + }, + { + "smmu0_int31_en", + SMMU0_SMMU0_SMMU0_INT31_ENr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002bc, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int31_en_reg, + NULL, + NULL, + }, + { + "smmu0_int31_mask", + SMMU0_SMMU0_SMMU0_INT31_MASKr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002c0, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int31_mask_reg, + NULL, + NULL, + }, + { + "smmu0_int31_status", + SMMU0_SMMU0_SMMU0_INT31_STATUSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002c4, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int31_status_reg, + NULL, + NULL, + }, + { + "smmu0_int32_en", + SMMU0_SMMU0_SMMU0_INT32_ENr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002c8, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int32_en_reg, + NULL, + NULL, + }, + { + "smmu0_int32_mask", + SMMU0_SMMU0_SMMU0_INT32_MASKr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002cc, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int32_mask_reg, + NULL, + NULL, + }, + { + "smmu0_int32_status", + SMMU0_SMMU0_SMMU0_INT32_STATUSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002d0, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int32_status_reg, + NULL, + NULL, + }, + { + "smmu0_int33_en", + SMMU0_SMMU0_SMMU0_INT33_ENr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002d4, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int33_en_reg, + NULL, + NULL, + }, + { + "smmu0_int33_mask", + SMMU0_SMMU0_SMMU0_INT33_MASKr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002d8, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int33_mask_reg, + NULL, + NULL, + }, + { + "smmu0_int33_status", + SMMU0_SMMU0_SMMU0_INT33_STATUSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002dc, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int33_status_reg, + NULL, + NULL, + }, + { + "smmu0_int34_en", + SMMU0_SMMU0_SMMU0_INT34_ENr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002e0, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int34_en_reg, + NULL, + NULL, + }, + { + "smmu0_int34_mask", + SMMU0_SMMU0_SMMU0_INT34_MASKr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002e4, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int34_mask_reg, + NULL, + NULL, + }, + { + "smmu0_int34_status", + SMMU0_SMMU0_SMMU0_INT34_STATUSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002e8, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_smmu0_int34_status_reg, + NULL, + NULL, + }, + { + "smmu0_int35_en", + SMMU0_SMMU0_SMMU0_INT35_ENr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002ec, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int35_en_reg, + NULL, + NULL, + }, + { + "smmu0_int35_mask", + SMMU0_SMMU0_SMMU0_INT35_MASKr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002f0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int35_mask_reg, + NULL, + NULL, + }, + { + "smmu0_int35_status", + SMMU0_SMMU0_SMMU0_INT35_STATUSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002f4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int35_status_reg, + NULL, + NULL, + }, + { + "smmu0_int36_en", + SMMU0_SMMU0_SMMU0_INT36_ENr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002f8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int36_en_reg, + NULL, + NULL, + }, + { + "smmu0_int36_mask", + SMMU0_SMMU0_SMMU0_INT36_MASKr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002fc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int36_mask_reg, + NULL, + NULL, + }, + { + "smmu0_int36_status", + SMMU0_SMMU0_SMMU0_INT36_STATUSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000300, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int36_status_reg, + NULL, + NULL, + }, + { + "smmu0_int37_en", + SMMU0_SMMU0_SMMU0_INT37_ENr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000304, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int37_en_reg, + NULL, + NULL, + }, + { + "smmu0_int37_mask", + SMMU0_SMMU0_SMMU0_INT37_MASKr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000308, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int37_mask_reg, + NULL, + NULL, + }, + { + "smmu0_int37_status", + SMMU0_SMMU0_SMMU0_INT37_STATUSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000030c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int37_status_reg, + NULL, + NULL, + }, + { + "smmu0_int38_en", + SMMU0_SMMU0_SMMU0_INT38_ENr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000310, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int38_en_reg, + NULL, + NULL, + }, + { + "smmu0_int38_mask", + SMMU0_SMMU0_SMMU0_INT38_MASKr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000314, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int38_mask_reg, + NULL, + NULL, + }, + { + "smmu0_int38_status", + SMMU0_SMMU0_SMMU0_INT38_STATUSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000318, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int38_status_reg, + NULL, + NULL, + }, + { + "smmu0_int39_en", + SMMU0_SMMU0_SMMU0_INT39_ENr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000036c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int39_en_reg, + NULL, + NULL, + }, + { + "smmu0_int39_mask", + SMMU0_SMMU0_SMMU0_INT39_MASKr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000370, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int39_mask_reg, + NULL, + NULL, + }, + { + "smmu0_int39_status", + SMMU0_SMMU0_SMMU0_INT39_STATUSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000374, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int39_status_reg, + NULL, + NULL, + }, + { + "smmu0_int40_en", + SMMU0_SMMU0_SMMU0_INT40_ENr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000378, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int40_en_reg, + NULL, + NULL, + }, + { + "smmu0_int40_mask", + SMMU0_SMMU0_SMMU0_INT40_MASKr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000037c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int40_mask_reg, + NULL, + NULL, + }, + { + "smmu0_int40_status", + SMMU0_SMMU0_SMMU0_INT40_STATUSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000380, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int40_status_reg, + NULL, + NULL, + }, + { + "smmu0_int41_en", + SMMU0_SMMU0_SMMU0_INT41_ENr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000384, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int41_en_reg, + NULL, + NULL, + }, + { + "smmu0_int41_mask", + SMMU0_SMMU0_SMMU0_INT41_MASKr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000388, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int41_mask_reg, + NULL, + NULL, + }, + { + "smmu0_int41_status", + SMMU0_SMMU0_SMMU0_INT41_STATUSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000038c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int41_status_reg, + NULL, + NULL, + }, + { + "smmu0_int42_en", + SMMU0_SMMU0_SMMU0_INT42_ENr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000390, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int42_en_reg, + NULL, + NULL, + }, + { + "smmu0_int42_mask", + SMMU0_SMMU0_SMMU0_INT42_MASKr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000394, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int42_mask_reg, + NULL, + NULL, + }, + { + "smmu0_int42_status", + SMMU0_SMMU0_SMMU0_INT42_STATUSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000398, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int42_status_reg, + NULL, + NULL, + }, + { + "smmu0_int43_en", + SMMU0_SMMU0_SMMU0_INT43_ENr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000039c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int43_en_reg, + NULL, + NULL, + }, + { + "smmu0_int43_mask", + SMMU0_SMMU0_SMMU0_INT43_MASKr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003a0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int43_mask_reg, + NULL, + NULL, + }, + { + "smmu0_int43_status", + SMMU0_SMMU0_SMMU0_INT43_STATUSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003a4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int43_status_reg, + NULL, + NULL, + }, + { + "smmu0_int44_en", + SMMU0_SMMU0_SMMU0_INT44_ENr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003a8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int44_en_reg, + NULL, + NULL, + }, + { + "smmu0_int44_mask", + SMMU0_SMMU0_SMMU0_INT44_MASKr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003ac, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int44_mask_reg, + NULL, + NULL, + }, + { + "smmu0_int44_status", + SMMU0_SMMU0_SMMU0_INT44_STATUSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003b0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int44_status_reg, + NULL, + NULL, + }, + { + "smmu0_int45_en", + SMMU0_SMMU0_SMMU0_INT45_ENr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003b4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int45_en_reg, + NULL, + NULL, + }, + { + "smmu0_int45_mask", + SMMU0_SMMU0_SMMU0_INT45_MASKr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003b8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int45_mask_reg, + NULL, + NULL, + }, + { + "smmu0_int45_status", + SMMU0_SMMU0_SMMU0_INT45_STATUSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003bc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int45_status_reg, + NULL, + NULL, + }, + { + "smmu0_int46_en", + SMMU0_SMMU0_SMMU0_INT46_ENr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003c0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int46_en_reg, + NULL, + NULL, + }, + { + "smmu0_int46_mask", + SMMU0_SMMU0_SMMU0_INT46_MASKr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003c4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int46_mask_reg, + NULL, + NULL, + }, + { + "smmu0_int46_status", + SMMU0_SMMU0_SMMU0_INT46_STATUSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003c8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int46_status_reg, + NULL, + NULL, + }, + { + "smmu0_int47_en", + SMMU0_SMMU0_SMMU0_INT47_ENr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003cc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int47_en_reg, + NULL, + NULL, + }, + { + "smmu0_int47_mask", + SMMU0_SMMU0_SMMU0_INT47_MASKr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003d0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int47_mask_reg, + NULL, + NULL, + }, + { + "smmu0_int47_status", + SMMU0_SMMU0_SMMU0_INT47_STATUSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003d4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int47_status_reg, + NULL, + NULL, + }, + { + "smmu0_int48_en", + SMMU0_SMMU0_SMMU0_INT48_ENr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003d8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int48_en_reg, + NULL, + NULL, + }, + { + "smmu0_int48_mask", + SMMU0_SMMU0_SMMU0_INT48_MASKr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003dc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int48_mask_reg, + NULL, + NULL, + }, + { + "smmu0_int48_status", + SMMU0_SMMU0_SMMU0_INT48_STATUSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003e0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int48_status_reg, + NULL, + NULL, + }, + { + "smmu0_int49_en", + SMMU0_SMMU0_SMMU0_INT49_ENr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003e4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int49_en_reg, + NULL, + NULL, + }, + { + "smmu0_int49_mask", + SMMU0_SMMU0_SMMU0_INT49_MASKr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003e8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int49_mask_reg, + NULL, + NULL, + }, + { + "smmu0_int49_status", + SMMU0_SMMU0_SMMU0_INT49_STATUSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003ec, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int49_status_reg, + NULL, + NULL, + }, + { + "smmu0_int50_en", + SMMU0_SMMU0_SMMU0_INT50_ENr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003f0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int50_en_reg, + NULL, + NULL, + }, + { + "smmu0_int50_mask", + SMMU0_SMMU0_SMMU0_INT50_MASKr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003f4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int50_mask_reg, + NULL, + NULL, + }, + { + "smmu0_int50_status", + SMMU0_SMMU0_SMMU0_INT50_STATUSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003f8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int50_status_reg, + NULL, + NULL, + }, + { + "smmu0_int51_en", + SMMU0_SMMU0_SMMU0_INT51_ENr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003fc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int51_en_reg, + NULL, + NULL, + }, + { + "smmu0_int51_mask", + SMMU0_SMMU0_SMMU0_INT51_MASKr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000400, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int51_mask_reg, + NULL, + NULL, + }, + { + "smmu0_int51_status", + SMMU0_SMMU0_SMMU0_INT51_STATUSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000404, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int51_status_reg, + NULL, + NULL, + }, + { + "smmu0_int52_en", + SMMU0_SMMU0_SMMU0_INT52_ENr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000408, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int52_en_reg, + NULL, + NULL, + }, + { + "smmu0_int52_mask", + SMMU0_SMMU0_SMMU0_INT52_MASKr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000040c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int52_mask_reg, + NULL, + NULL, + }, + { + "smmu0_int52_status", + SMMU0_SMMU0_SMMU0_INT52_STATUSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000410, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_int52_status_reg, + NULL, + NULL, + }, + { + "smmu0_int53_en", + SMMU0_SMMU0_SMMU0_INT53_ENr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000414, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_smmu0_smmu0_smmu0_int53_en_reg, + NULL, + NULL, + }, + { + "smmu0_int53_mask", + SMMU0_SMMU0_SMMU0_INT53_MASKr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000418, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_smmu0_smmu0_smmu0_int53_mask_reg, + NULL, + NULL, + }, + { + "smmu0_int53_status", + SMMU0_SMMU0_SMMU0_INT53_STATUSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000041c, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_smmu0_smmu0_smmu0_int53_status_reg, + NULL, + NULL, + }, + { + "ctrl0_arbiter_ecc_bypass", + SMMU0_SMMU0_CTRL0_ARBITER_ECC_BYPASSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000031c, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_ctrl0_arbiter_ecc_bypass_reg, + NULL, + NULL, + }, + { + "ctrl2_arbiter_ecc_bypass", + SMMU0_SMMU0_CTRL2_ARBITER_ECC_BYPASSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000320, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_ctrl2_arbiter_ecc_bypass_reg, + NULL, + NULL, + }, + { + "ctrl4_arbiter_ecc_bypass", + SMMU0_SMMU0_CTRL4_ARBITER_ECC_BYPASSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000324, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_ctrl4_arbiter_ecc_bypass_reg, + NULL, + NULL, + }, + { + "ctrl6_arbiter_ecc_bypass", + SMMU0_SMMU0_CTRL6_ARBITER_ECC_BYPASSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000328, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_ctrl6_arbiter_ecc_bypass_reg, + NULL, + NULL, + }, + { + "ctrl8_arbiter_ecc_bypass", + SMMU0_SMMU0_CTRL8_ARBITER_ECC_BYPASSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000032c, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_ctrl8_arbiter_ecc_bypass_reg, + NULL, + NULL, + }, + { + "ctrl10_arbiter_ecc_bypass", + SMMU0_SMMU0_CTRL10_ARBITER_ECC_BYPASSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000330, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_ctrl10_arbiter_ecc_bypass_reg, + NULL, + NULL, + }, + { + "ctrl12_arbiter_ecc_bypass", + SMMU0_SMMU0_CTRL12_ARBITER_ECC_BYPASSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000334, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_ctrl12_arbiter_ecc_bypass_reg, + NULL, + NULL, + }, + { + "ctrl14_arbiter_ecc_bypass", + SMMU0_SMMU0_CTRL14_ARBITER_ECC_BYPASSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000338, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_ctrl14_arbiter_ecc_bypass_reg, + NULL, + NULL, + }, + { + "ctrl16_arbiter_ecc_bypass", + SMMU0_SMMU0_CTRL16_ARBITER_ECC_BYPASSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000033c, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_ctrl16_arbiter_ecc_bypass_reg, + NULL, + NULL, + }, + { + "ctrl18_arbiter_ecc_bypass", + SMMU0_SMMU0_CTRL18_ARBITER_ECC_BYPASSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000340, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_ctrl18_arbiter_ecc_bypass_reg, + NULL, + NULL, + }, + { + "ctrl20_arbiter_ecc_bypass", + SMMU0_SMMU0_CTRL20_ARBITER_ECC_BYPASSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000344, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_ctrl20_arbiter_ecc_bypass_reg, + NULL, + NULL, + }, + { + "ctrl22_arbiter_ecc_bypass", + SMMU0_SMMU0_CTRL22_ARBITER_ECC_BYPASSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000348, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_ctrl22_arbiter_ecc_bypass_reg, + NULL, + NULL, + }, + { + "ctrl24_arbiter_ecc_bypass", + SMMU0_SMMU0_CTRL24_ARBITER_ECC_BYPASSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000034c, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_ctrl24_arbiter_ecc_bypass_reg, + NULL, + NULL, + }, + { + "ctrl26_arbiter_ecc_bypass", + SMMU0_SMMU0_CTRL26_ARBITER_ECC_BYPASSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000350, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_ctrl26_arbiter_ecc_bypass_reg, + NULL, + NULL, + }, + { + "ctrl28_arbiter_ecc_bypass", + SMMU0_SMMU0_CTRL28_ARBITER_ECC_BYPASSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000354, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_ctrl28_arbiter_ecc_bypass_reg, + NULL, + NULL, + }, + { + "ctrl30_arbiter_ecc_bypass", + SMMU0_SMMU0_CTRL30_ARBITER_ECC_BYPASSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000358, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_ctrl30_arbiter_ecc_bypass_reg, + NULL, + NULL, + }, + { + "ctrl_req_ecc_bypass", + SMMU0_SMMU0_CTRL_REQ_ECC_BYPASSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000035c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_ctrl_req_ecc_bypass_reg, + NULL, + NULL, + }, + { + "ctrl_info_ecc_bypass", + SMMU0_SMMU0_CTRL_INFO_ECC_BYPASSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000360, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_ctrl_info_ecc_bypass_reg, + NULL, + NULL, + }, + { + "smmu0_rschd_ecc_bypass", + SMMU0_SMMU0_SMMU0_RSCHD_ECC_BYPASSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000368, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_rschd_ecc_bypass_reg, + NULL, + NULL, + }, + { + "smmu0_wr_ecc_bypass", + SMMU0_SMMU0_SMMU0_WR_ECC_BYPASSr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000364, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_smmu0_smmu0_smmu0_wr_ecc_bypass_reg, + NULL, + NULL, + }, + { + "ctrl0_arbiter_ecc_err", + SMMU0_SMMU0_CTRL0_ARBITER_ECC_ERRr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000f50, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_ctrl0_arbiter_ecc_err_reg, + NULL, + NULL, + }, + { + "ctrl1_arbiter_ecc_err", + SMMU0_SMMU0_CTRL1_ARBITER_ECC_ERRr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000f54, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_ctrl1_arbiter_ecc_err_reg, + NULL, + NULL, + }, + { + "ctrl2_arbiter_ecc_err", + SMMU0_SMMU0_CTRL2_ARBITER_ECC_ERRr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000f58, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_ctrl2_arbiter_ecc_err_reg, + NULL, + NULL, + }, + { + "ctrl3_arbiter_ecc_err", + SMMU0_SMMU0_CTRL3_ARBITER_ECC_ERRr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000f5c, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_ctrl3_arbiter_ecc_err_reg, + NULL, + NULL, + }, + { + "ctrl4_arbiter_ecc_err", + SMMU0_SMMU0_CTRL4_ARBITER_ECC_ERRr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000f60, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_ctrl4_arbiter_ecc_err_reg, + NULL, + NULL, + }, + { + "ctrl5_arbiter_ecc_err", + SMMU0_SMMU0_CTRL5_ARBITER_ECC_ERRr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000f64, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_ctrl5_arbiter_ecc_err_reg, + NULL, + NULL, + }, + { + "ctrl6_arbiter_ecc_err", + SMMU0_SMMU0_CTRL6_ARBITER_ECC_ERRr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000f68, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_ctrl6_arbiter_ecc_err_reg, + NULL, + NULL, + }, + { + "ctrl7_arbiter_ecc_err", + SMMU0_SMMU0_CTRL7_ARBITER_ECC_ERRr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000f6c, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_ctrl7_arbiter_ecc_err_reg, + NULL, + NULL, + }, + { + "ctrl8_arbiter_ecc_err", + SMMU0_SMMU0_CTRL8_ARBITER_ECC_ERRr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000f70, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_ctrl8_arbiter_ecc_err_reg, + NULL, + NULL, + }, + { + "ctrl9_arbiter_ecc_err", + SMMU0_SMMU0_CTRL9_ARBITER_ECC_ERRr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000f74, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_ctrl9_arbiter_ecc_err_reg, + NULL, + NULL, + }, + { + "ctrl10_arbiter_ecc_err", + SMMU0_SMMU0_CTRL10_ARBITER_ECC_ERRr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000f78, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_ctrl10_arbiter_ecc_err_reg, + NULL, + NULL, + }, + { + "ctrl11_arbiter_ecc_err", + SMMU0_SMMU0_CTRL11_ARBITER_ECC_ERRr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000f7c, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_ctrl11_arbiter_ecc_err_reg, + NULL, + NULL, + }, + { + "ctrl12_arbiter_ecc_err", + SMMU0_SMMU0_CTRL12_ARBITER_ECC_ERRr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000f80, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_ctrl12_arbiter_ecc_err_reg, + NULL, + NULL, + }, + { + "ctrl13_arbiter_ecc_err", + SMMU0_SMMU0_CTRL13_ARBITER_ECC_ERRr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000f84, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_ctrl13_arbiter_ecc_err_reg, + NULL, + NULL, + }, + { + "ctrl14_arbiter_ecc_err", + SMMU0_SMMU0_CTRL14_ARBITER_ECC_ERRr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000f88, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_ctrl14_arbiter_ecc_err_reg, + NULL, + NULL, + }, + { + "ctrl15_arbiter_ecc_err", + SMMU0_SMMU0_CTRL15_ARBITER_ECC_ERRr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000f8c, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_ctrl15_arbiter_ecc_err_reg, + NULL, + NULL, + }, + { + "ctrl16_arbiter_ecc_err", + SMMU0_SMMU0_CTRL16_ARBITER_ECC_ERRr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000f90, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_ctrl16_arbiter_ecc_err_reg, + NULL, + NULL, + }, + { + "ctrl17_arbiter_ecc_err", + SMMU0_SMMU0_CTRL17_ARBITER_ECC_ERRr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000f94, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_ctrl17_arbiter_ecc_err_reg, + NULL, + NULL, + }, + { + "ctrl18_arbiter_ecc_err", + SMMU0_SMMU0_CTRL18_ARBITER_ECC_ERRr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000f98, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_ctrl18_arbiter_ecc_err_reg, + NULL, + NULL, + }, + { + "ctrl19_arbiter_ecc_err", + SMMU0_SMMU0_CTRL19_ARBITER_ECC_ERRr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000f9c, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_ctrl19_arbiter_ecc_err_reg, + NULL, + NULL, + }, + { + "ctrl20_arbiter_ecc_err", + SMMU0_SMMU0_CTRL20_ARBITER_ECC_ERRr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000fa0, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_ctrl20_arbiter_ecc_err_reg, + NULL, + NULL, + }, + { + "ctrl21_arbiter_ecc_err", + SMMU0_SMMU0_CTRL21_ARBITER_ECC_ERRr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000fa4, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_ctrl21_arbiter_ecc_err_reg, + NULL, + NULL, + }, + { + "ctrl22_arbiter_ecc_err", + SMMU0_SMMU0_CTRL22_ARBITER_ECC_ERRr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000fa8, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_ctrl22_arbiter_ecc_err_reg, + NULL, + NULL, + }, + { + "ctrl23_arbiter_ecc_err", + SMMU0_SMMU0_CTRL23_ARBITER_ECC_ERRr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000fac, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_ctrl23_arbiter_ecc_err_reg, + NULL, + NULL, + }, + { + "ctrl24_arbiter_ecc_err", + SMMU0_SMMU0_CTRL24_ARBITER_ECC_ERRr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000fb0, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_ctrl24_arbiter_ecc_err_reg, + NULL, + NULL, + }, + { + "ctrl25_arbiter_ecc_err", + SMMU0_SMMU0_CTRL25_ARBITER_ECC_ERRr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000fb4, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_ctrl25_arbiter_ecc_err_reg, + NULL, + NULL, + }, + { + "ctrl26_arbiter_ecc_err", + SMMU0_SMMU0_CTRL26_ARBITER_ECC_ERRr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000fbc, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_ctrl26_arbiter_ecc_err_reg, + NULL, + NULL, + }, + { + "ctrl27_arbiter_ecc_err", + SMMU0_SMMU0_CTRL27_ARBITER_ECC_ERRr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000fc0, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_ctrl27_arbiter_ecc_err_reg, + NULL, + NULL, + }, + { + "ctrl28_arbiter_ecc_err", + SMMU0_SMMU0_CTRL28_ARBITER_ECC_ERRr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000fc4, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_ctrl28_arbiter_ecc_err_reg, + NULL, + NULL, + }, + { + "ctrl29_arbiter_ecc_err", + SMMU0_SMMU0_CTRL29_ARBITER_ECC_ERRr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000fc8, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_ctrl29_arbiter_ecc_err_reg, + NULL, + NULL, + }, + { + "ctrl30_arbiter_ecc_err", + SMMU0_SMMU0_CTRL30_ARBITER_ECC_ERRr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000fcc, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_ctrl30_arbiter_ecc_err_reg, + NULL, + NULL, + }, + { + "ctrl31_arbiter_ecc_err", + SMMU0_SMMU0_CTRL31_ARBITER_ECC_ERRr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000fd0, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_smmu0_smmu0_ctrl31_arbiter_ecc_err_reg, + NULL, + NULL, + }, + { + "ctrl_req_ecc_single_err", + SMMU0_SMMU0_CTRL_REQ_ECC_SINGLE_ERRr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000fd4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_ctrl_req_ecc_single_err_reg, + NULL, + NULL, + }, + { + "ctrl_req_ecc_double_err", + SMMU0_SMMU0_CTRL_REQ_ECC_DOUBLE_ERRr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000fd8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_ctrl_req_ecc_double_err_reg, + NULL, + NULL, + }, + { + "ctrl_info_ecc_single_err", + SMMU0_SMMU0_CTRL_INFO_ECC_SINGLE_ERRr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000fdc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_ctrl_info_ecc_single_err_reg, + NULL, + NULL, + }, + { + "ctrl_info_ecc_double_err", + SMMU0_SMMU0_CTRL_INFO_ECC_DOUBLE_ERRr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000fe0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_ctrl_info_ecc_double_err_reg, + NULL, + NULL, + }, + { + "smmu0_wr_ecc_err", + SMMU0_SMMU0_SMMU0_WR_ECC_ERRr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000fe4, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_smmu0_smmu0_smmu0_wr_ecc_err_reg, + NULL, + NULL, + }, + { + "smmu0_rschd_ecc_single_err", + SMMU0_SMMU0_SMMU0_RSCHD_ECC_SINGLE_ERRr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000fe8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_rschd_ecc_single_err_reg, + NULL, + NULL, + }, + { + "smmu0_rschd_ecc_double_err", + SMMU0_SMMU0_SMMU0_RSCHD_ECC_DOUBLE_ERRr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000fec, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_rschd_ecc_double_err_reg, + NULL, + NULL, + }, + { + "ord_fifo_empty", + SMMU0_SMMU0_ORD_FIFO_EMPTYr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000440, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_ord_fifo_empty_reg, + NULL, + NULL, + }, + { + "wr_arb_fifo_empty", + SMMU0_SMMU0_WR_ARB_FIFO_EMPTYr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000444, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_wr_arb_fifo_empty_reg, + NULL, + NULL, + }, + { + "ctrl_fifo_empty0", + SMMU0_SMMU0_CTRL_FIFO_EMPTY0r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000448, + (32/8), + 0, + 0, + 0, + 0, + 6, + g_smmu0_smmu0_ctrl_fifo_empty0_reg, + NULL, + NULL, + }, + { + "ctrl_fifo_empty1", + SMMU0_SMMU0_CTRL_FIFO_EMPTY1r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000044c, + (32/8), + 0, + 0, + 0, + 0, + 6, + g_smmu0_smmu0_ctrl_fifo_empty1_reg, + NULL, + NULL, + }, + { + "ctrl_fifo_empty2", + SMMU0_SMMU0_CTRL_FIFO_EMPTY2r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000450, + (32/8), + 0, + 0, + 0, + 0, + 6, + g_smmu0_smmu0_ctrl_fifo_empty2_reg, + NULL, + NULL, + }, + { + "ctrl_fifo_empty3", + SMMU0_SMMU0_CTRL_FIFO_EMPTY3r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000454, + (32/8), + 0, + 0, + 0, + 0, + 6, + g_smmu0_smmu0_ctrl_fifo_empty3_reg, + NULL, + NULL, + }, + { + "ctrl_fifo_empty4", + SMMU0_SMMU0_CTRL_FIFO_EMPTY4r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000560, + (32/8), + 0, + 0, + 0, + 0, + 6, + g_smmu0_smmu0_ctrl_fifo_empty4_reg, + NULL, + NULL, + }, + { + "ctrl_fifo_empty5", + SMMU0_SMMU0_CTRL_FIFO_EMPTY5r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000564, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_smmu0_smmu0_ctrl_fifo_empty5_reg, + NULL, + NULL, + }, + { + "kschd_fifo_empty0", + SMMU0_SMMU0_KSCHD_FIFO_EMPTY0r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000458, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_kschd_fifo_empty0_reg, + NULL, + NULL, + }, + { + "kschd_fifo_empty1", + SMMU0_SMMU0_KSCHD_FIFO_EMPTY1r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000045c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_kschd_fifo_empty1_reg, + NULL, + NULL, + }, + { + "kschd_fifo_empty2", + SMMU0_SMMU0_KSCHD_FIFO_EMPTY2r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000460, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_kschd_fifo_empty2_reg, + NULL, + NULL, + }, + { + "kschd_fifo_empty3", + SMMU0_SMMU0_KSCHD_FIFO_EMPTY3r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000464, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_kschd_fifo_empty3_reg, + NULL, + NULL, + }, + { + "kschd_fifo_empty4", + SMMU0_SMMU0_KSCHD_FIFO_EMPTY4r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000468, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_kschd_fifo_empty4_reg, + NULL, + NULL, + }, + { + "kschd_fifo_empty5", + SMMU0_SMMU0_KSCHD_FIFO_EMPTY5r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000046c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_kschd_fifo_empty5_reg, + NULL, + NULL, + }, + { + "kschd_fifo_empty6", + SMMU0_SMMU0_KSCHD_FIFO_EMPTY6r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000470, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_kschd_fifo_empty6_reg, + NULL, + NULL, + }, + { + "kschd_fifo_empty7", + SMMU0_SMMU0_KSCHD_FIFO_EMPTY7r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000474, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_kschd_fifo_empty7_reg, + NULL, + NULL, + }, + { + "kschd_fifo_empty8", + SMMU0_SMMU0_KSCHD_FIFO_EMPTY8r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000478, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_kschd_fifo_empty8_reg, + NULL, + NULL, + }, + { + "kschd_fifo_empty9", + SMMU0_SMMU0_KSCHD_FIFO_EMPTY9r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000047c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_kschd_fifo_empty9_reg, + NULL, + NULL, + }, + { + "kschd_fifo_empty10", + SMMU0_SMMU0_KSCHD_FIFO_EMPTY10r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000480, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_kschd_fifo_empty10_reg, + NULL, + NULL, + }, + { + "kschd_fifo_empty11", + SMMU0_SMMU0_KSCHD_FIFO_EMPTY11r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000484, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_kschd_fifo_empty11_reg, + NULL, + NULL, + }, + { + "kschd_fifo_empty12", + SMMU0_SMMU0_KSCHD_FIFO_EMPTY12r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000488, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_kschd_fifo_empty12_reg, + NULL, + NULL, + }, + { + "kschd_fifo_empty13", + SMMU0_SMMU0_KSCHD_FIFO_EMPTY13r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000048c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_kschd_fifo_empty13_reg, + NULL, + NULL, + }, + { + "kschd_fifo_empty14", + SMMU0_SMMU0_KSCHD_FIFO_EMPTY14r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000490, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_kschd_fifo_empty14_reg, + NULL, + NULL, + }, + { + "kschd_fifo_empty15", + SMMU0_SMMU0_KSCHD_FIFO_EMPTY15r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000494, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_kschd_fifo_empty15_reg, + NULL, + NULL, + }, + { + "kschd_fifo_empty16", + SMMU0_SMMU0_KSCHD_FIFO_EMPTY16r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000498, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_kschd_fifo_empty16_reg, + NULL, + NULL, + }, + { + "kschd_fifo_empty17", + SMMU0_SMMU0_KSCHD_FIFO_EMPTY17r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000049c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_kschd_fifo_empty17_reg, + NULL, + NULL, + }, + { + "kschd_fifo_empty18", + SMMU0_SMMU0_KSCHD_FIFO_EMPTY18r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004a0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_kschd_fifo_empty18_reg, + NULL, + NULL, + }, + { + "kschd_fifo_empty19", + SMMU0_SMMU0_KSCHD_FIFO_EMPTY19r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004a4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_kschd_fifo_empty19_reg, + NULL, + NULL, + }, + { + "kschd_fifo_empty20", + SMMU0_SMMU0_KSCHD_FIFO_EMPTY20r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004a8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_kschd_fifo_empty20_reg, + NULL, + NULL, + }, + { + "kschd_fifo_empty21", + SMMU0_SMMU0_KSCHD_FIFO_EMPTY21r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004ac, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_kschd_fifo_empty21_reg, + NULL, + NULL, + }, + { + "kschd_fifo_empty22", + SMMU0_SMMU0_KSCHD_FIFO_EMPTY22r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004b0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_kschd_fifo_empty22_reg, + NULL, + NULL, + }, + { + "kschd_fifo_empty23", + SMMU0_SMMU0_KSCHD_FIFO_EMPTY23r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004b4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_kschd_fifo_empty23_reg, + NULL, + NULL, + }, + { + "kschd_fifo_empty24", + SMMU0_SMMU0_KSCHD_FIFO_EMPTY24r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004b8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_kschd_fifo_empty24_reg, + NULL, + NULL, + }, + { + "kschd_fifo_empty25", + SMMU0_SMMU0_KSCHD_FIFO_EMPTY25r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004bc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_kschd_fifo_empty25_reg, + NULL, + NULL, + }, + { + "kschd_fifo_empty26", + SMMU0_SMMU0_KSCHD_FIFO_EMPTY26r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004c0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_kschd_fifo_empty26_reg, + NULL, + NULL, + }, + { + "kschd_fifo_empty27", + SMMU0_SMMU0_KSCHD_FIFO_EMPTY27r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004c4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_kschd_fifo_empty27_reg, + NULL, + NULL, + }, + { + "kschd_fifo_empty28", + SMMU0_SMMU0_KSCHD_FIFO_EMPTY28r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004c8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_kschd_fifo_empty28_reg, + NULL, + NULL, + }, + { + "kschd_fifo_empty29", + SMMU0_SMMU0_KSCHD_FIFO_EMPTY29r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004cc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_kschd_fifo_empty29_reg, + NULL, + NULL, + }, + { + "kschd_fifo_empty30", + SMMU0_SMMU0_KSCHD_FIFO_EMPTY30r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004d0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_kschd_fifo_empty30_reg, + NULL, + NULL, + }, + { + "kschd_fifo_empty31", + SMMU0_SMMU0_KSCHD_FIFO_EMPTY31r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004d4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_kschd_fifo_empty31_reg, + NULL, + NULL, + }, + { + "rschd_fifo_empty0", + SMMU0_SMMU0_RSCHD_FIFO_EMPTY0r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004d8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_rschd_fifo_empty0_reg, + NULL, + NULL, + }, + { + "rschd_fifo_empty1", + SMMU0_SMMU0_RSCHD_FIFO_EMPTY1r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004dc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_rschd_fifo_empty1_reg, + NULL, + NULL, + }, + { + "rschd_fifo_empty2", + SMMU0_SMMU0_RSCHD_FIFO_EMPTY2r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004e0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_rschd_fifo_empty2_reg, + NULL, + NULL, + }, + { + "rschd_fifo_empty3", + SMMU0_SMMU0_RSCHD_FIFO_EMPTY3r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004e4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_rschd_fifo_empty3_reg, + NULL, + NULL, + }, + { + "rschd_fifo_empty4", + SMMU0_SMMU0_RSCHD_FIFO_EMPTY4r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004e8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_rschd_fifo_empty4_reg, + NULL, + NULL, + }, + { + "rschd_fifo_empty5", + SMMU0_SMMU0_RSCHD_FIFO_EMPTY5r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004ec, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_rschd_fifo_empty5_reg, + NULL, + NULL, + }, + { + "rschd_fifo_empty6", + SMMU0_SMMU0_RSCHD_FIFO_EMPTY6r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004f0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_rschd_fifo_empty6_reg, + NULL, + NULL, + }, + { + "rschd_fifo_empty7", + SMMU0_SMMU0_RSCHD_FIFO_EMPTY7r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004f4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_rschd_fifo_empty7_reg, + NULL, + NULL, + }, + { + "rschd_fifo_empty8", + SMMU0_SMMU0_RSCHD_FIFO_EMPTY8r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004f8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_rschd_fifo_empty8_reg, + NULL, + NULL, + }, + { + "rschd_fifo_empty9", + SMMU0_SMMU0_RSCHD_FIFO_EMPTY9r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004fc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_rschd_fifo_empty9_reg, + NULL, + NULL, + }, + { + "rschd_fifo_empty10", + SMMU0_SMMU0_RSCHD_FIFO_EMPTY10r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000500, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_rschd_fifo_empty10_reg, + NULL, + NULL, + }, + { + "rschd_fifo_empty11", + SMMU0_SMMU0_RSCHD_FIFO_EMPTY11r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000504, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_rschd_fifo_empty11_reg, + NULL, + NULL, + }, + { + "rschd_fifo_empty12", + SMMU0_SMMU0_RSCHD_FIFO_EMPTY12r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000508, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_rschd_fifo_empty12_reg, + NULL, + NULL, + }, + { + "rschd_fifo_empty13", + SMMU0_SMMU0_RSCHD_FIFO_EMPTY13r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000050c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_rschd_fifo_empty13_reg, + NULL, + NULL, + }, + { + "rschd_fifo_empty14", + SMMU0_SMMU0_RSCHD_FIFO_EMPTY14r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000510, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_rschd_fifo_empty14_reg, + NULL, + NULL, + }, + { + "rschd_fifo_empty15", + SMMU0_SMMU0_RSCHD_FIFO_EMPTY15r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000514, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_rschd_fifo_empty15_reg, + NULL, + NULL, + }, + { + "rschd_fifo_empty16", + SMMU0_SMMU0_RSCHD_FIFO_EMPTY16r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000518, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_rschd_fifo_empty16_reg, + NULL, + NULL, + }, + { + "rschd_fifo_empty17", + SMMU0_SMMU0_RSCHD_FIFO_EMPTY17r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000051c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_rschd_fifo_empty17_reg, + NULL, + NULL, + }, + { + "rschd_fifo_empty18", + SMMU0_SMMU0_RSCHD_FIFO_EMPTY18r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000520, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_rschd_fifo_empty18_reg, + NULL, + NULL, + }, + { + "rschd_fifo_empty19", + SMMU0_SMMU0_RSCHD_FIFO_EMPTY19r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000524, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_rschd_fifo_empty19_reg, + NULL, + NULL, + }, + { + "rschd_fifo_empty20", + SMMU0_SMMU0_RSCHD_FIFO_EMPTY20r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000528, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_rschd_fifo_empty20_reg, + NULL, + NULL, + }, + { + "rschd_fifo_empty21", + SMMU0_SMMU0_RSCHD_FIFO_EMPTY21r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000052c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_rschd_fifo_empty21_reg, + NULL, + NULL, + }, + { + "rschd_fifo_empty22", + SMMU0_SMMU0_RSCHD_FIFO_EMPTY22r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000530, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_rschd_fifo_empty22_reg, + NULL, + NULL, + }, + { + "rschd_fifo_empty23", + SMMU0_SMMU0_RSCHD_FIFO_EMPTY23r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000534, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_rschd_fifo_empty23_reg, + NULL, + NULL, + }, + { + "rschd_fifo_empty24", + SMMU0_SMMU0_RSCHD_FIFO_EMPTY24r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000538, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_rschd_fifo_empty24_reg, + NULL, + NULL, + }, + { + "rschd_fifo_empty25", + SMMU0_SMMU0_RSCHD_FIFO_EMPTY25r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000053c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_rschd_fifo_empty25_reg, + NULL, + NULL, + }, + { + "rschd_fifo_empty26", + SMMU0_SMMU0_RSCHD_FIFO_EMPTY26r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000540, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_rschd_fifo_empty26_reg, + NULL, + NULL, + }, + { + "rschd_fifo_empty27", + SMMU0_SMMU0_RSCHD_FIFO_EMPTY27r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000544, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_rschd_fifo_empty27_reg, + NULL, + NULL, + }, + { + "rschd_fifo_empty28", + SMMU0_SMMU0_RSCHD_FIFO_EMPTY28r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000548, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_rschd_fifo_empty28_reg, + NULL, + NULL, + }, + { + "rschd_fifo_empty29", + SMMU0_SMMU0_RSCHD_FIFO_EMPTY29r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000054c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_rschd_fifo_empty29_reg, + NULL, + NULL, + }, + { + "rschd_fifo_empty30", + SMMU0_SMMU0_RSCHD_FIFO_EMPTY30r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000550, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_rschd_fifo_empty30_reg, + NULL, + NULL, + }, + { + "rschd_fifo_empty31", + SMMU0_SMMU0_RSCHD_FIFO_EMPTY31r, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000554, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_rschd_fifo_empty31_reg, + NULL, + NULL, + }, + { + "ept_flag", + SMMU0_SMMU0_EPT_FLAGr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000558, + (32/8), + 0, + 0, + 0, + 0, + 9, + g_smmu0_smmu0_ept_flag_reg, + NULL, + NULL, + }, + { + "ppu_soft_rst", + SMMU0_SMMU0_PPU_SOFT_RSTr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000055c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_ppu_soft_rst_reg, + NULL, + NULL, + }, + { + "smmu0_as_mac_age_fc_cnt", + SMMU0_SMMU0_SMMU0_AS_MAC_AGE_FC_CNTr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000800, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_as_mac_age_fc_cnt_reg, + NULL, + NULL, + }, + { + "smmu0_marc_se_parser_fc_cnt", + SMMU0_SMMU0_SMMU0_MARC_SE_PARSER_FC_CNTr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000804, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_marc_se_parser_fc_cnt_reg, + NULL, + NULL, + }, + { + "wr_arb_cpu_fc_cnt", + SMMU0_SMMU0_WR_ARB_CPU_FC_CNTr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000808, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_wr_arb_cpu_fc_cnt_reg, + NULL, + NULL, + }, + { + "smmu0_lpm_as_fc_cnt", + SMMU0_SMMU0_SMMU0_LPM_AS_FC_CNTr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000080c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_lpm_as_fc_cnt_reg, + NULL, + NULL, + }, + { + "lpm_as_smmu0_fc_cnt", + SMMU0_SMMU0_LPM_AS_SMMU0_FC_CNTr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000810, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_lpm_as_smmu0_fc_cnt_reg, + NULL, + NULL, + }, + { + "smmu0_etcam1_0_as_fc_cnt", + SMMU0_SMMU0_SMMU0_ETCAM1_0_AS_FC_CNTr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000814, + (32/8), + 0, + 1 + 1, + 0, + 4, + 1, + g_smmu0_smmu0_smmu0_etcam1_0_as_fc_cnt_reg, + NULL, + NULL, + }, + { + "as_etcam1_0_smmu0_fc_cnt", + SMMU0_SMMU0_AS_ETCAM1_0_SMMU0_FC_CNTr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000081c, + (32/8), + 0, + 1 + 1, + 0, + 4, + 1, + g_smmu0_smmu0_as_etcam1_0_smmu0_fc_cnt_reg, + NULL, + NULL, + }, + { + "smmu0_ppu_mcast_fc_cnt", + SMMU0_SMMU0_SMMU0_PPU_MCAST_FC_CNTr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000824, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_ppu_mcast_fc_cnt_reg, + NULL, + NULL, + }, + { + "ppu_smmu0_mcast_fc_cnt", + SMMU0_SMMU0_PPU_SMMU0_MCAST_FC_CNTr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000828, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_ppu_smmu0_mcast_fc_cnt_reg, + NULL, + NULL, + }, + { + "odma_smmu0_tdm_fc_rsp_fc_cnt", + SMMU0_SMMU0_ODMA_SMMU0_TDM_FC_RSP_FC_CNTr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000082c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_odma_smmu0_tdm_fc_rsp_fc_cnt_reg, + NULL, + NULL, + }, + { + "smmu0_odma_tdm_fc_key_fc_cnt", + SMMU0_SMMU0_SMMU0_ODMA_TDM_FC_KEY_FC_CNTr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000830, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_odma_tdm_fc_key_fc_cnt_reg, + NULL, + NULL, + }, + { + "smmu0_odma_fc_cnt", + SMMU0_SMMU0_SMMU0_ODMA_FC_CNTr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000834, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_odma_fc_cnt_reg, + NULL, + NULL, + }, + { + "smmu0_cfg_tab_rd_fc_cnt", + SMMU0_SMMU0_SMMU0_CFG_TAB_RD_FC_CNTr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000838, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_cfg_tab_rd_fc_cnt_reg, + NULL, + NULL, + }, + { + "smmu0_stat_fc15_0_cnt", + SMMU0_SMMU0_SMMU0_STAT_FC15_0_CNTr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000083c, + (32/8), + 0, + 15 + 1, + 0, + 4, + 1, + g_smmu0_smmu0_smmu0_stat_fc15_0_cnt_reg, + NULL, + NULL, + }, + { + "stat_smmu0_fc15_0_cnt", + SMMU0_SMMU0_STAT_SMMU0_FC15_0_CNTr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000087c, + (32/8), + 0, + 15 + 1, + 0, + 4, + 1, + g_smmu0_smmu0_stat_smmu0_fc15_0_cnt_reg, + NULL, + NULL, + }, + { + "smmu0_ppu_mex5_0_fc_cnt", + SMMU0_SMMU0_SMMU0_PPU_MEX5_0_FC_CNTr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000008bc, + (32/8), + 0, + 5 + 1, + 0, + 4, + 1, + g_smmu0_smmu0_smmu0_ppu_mex5_0_fc_cnt_reg, + NULL, + NULL, + }, + { + "ppu_smmu0_mex5_0_fc_cnt", + SMMU0_SMMU0_PPU_SMMU0_MEX5_0_FC_CNTr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000008d4, + (32/8), + 0, + 5 + 1, + 0, + 4, + 1, + g_smmu0_smmu0_ppu_smmu0_mex5_0_fc_cnt_reg, + NULL, + NULL, + }, + { + "as_smmu0_mac_age_req_cnt", + SMMU0_SMMU0_AS_SMMU0_MAC_AGE_REQ_CNTr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000008ec, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_as_smmu0_mac_age_req_cnt_reg, + NULL, + NULL, + }, + { + "se_parser_smmu0_marc_key_cnt", + SMMU0_SMMU0_SE_PARSER_SMMU0_MARC_KEY_CNTr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000008f0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_se_parser_smmu0_marc_key_cnt_reg, + NULL, + NULL, + }, + { + "cpu_ind_rdat_cnt", + SMMU0_SMMU0_CPU_IND_RDAT_CNTr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000008f4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_cpu_ind_rdat_cnt_reg, + NULL, + NULL, + }, + { + "cpu_ind_rd_req_cnt", + SMMU0_SMMU0_CPU_IND_RD_REQ_CNTr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000008f8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_cpu_ind_rd_req_cnt_reg, + NULL, + NULL, + }, + { + "cpu_ind_wr_req_cnt", + SMMU0_SMMU0_CPU_IND_WR_REQ_CNTr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000008fc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_cpu_ind_wr_req_cnt_reg, + NULL, + NULL, + }, + { + "smmu0_plcr_rsp0_cnt", + SMMU0_SMMU0_SMMU0_PLCR_RSP0_CNTr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000900, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_plcr_rsp0_cnt_reg, + NULL, + NULL, + }, + { + "plcr_smmu0_req0_cnt", + SMMU0_SMMU0_PLCR_SMMU0_REQ0_CNTr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000904, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_plcr_smmu0_req0_cnt_reg, + NULL, + NULL, + }, + { + "smmu0_lpm_as_rsp_cnt", + SMMU0_SMMU0_SMMU0_LPM_AS_RSP_CNTr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000908, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_lpm_as_rsp_cnt_reg, + NULL, + NULL, + }, + { + "lpm_as_smmu0_req_cnt", + SMMU0_SMMU0_LPM_AS_SMMU0_REQ_CNTr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000090c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_lpm_as_smmu0_req_cnt_reg, + NULL, + NULL, + }, + { + "smmu0_etcam1_0_as_rsp_cnt", + SMMU0_SMMU0_SMMU0_ETCAM1_0_AS_RSP_CNTr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000910, + (32/8), + 0, + 1 + 1, + 0, + 4, + 1, + g_smmu0_smmu0_smmu0_etcam1_0_as_rsp_cnt_reg, + NULL, + NULL, + }, + { + "etcam1_0_as_smmu0_req_cnt", + SMMU0_SMMU0_ETCAM1_0_AS_SMMU0_REQ_CNTr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000918, + (32/8), + 0, + 1 + 1, + 0, + 4, + 1, + g_smmu0_smmu0_etcam1_0_as_smmu0_req_cnt_reg, + NULL, + NULL, + }, + { + "smmu0_ppu_mcast_rsp_cnt", + SMMU0_SMMU0_SMMU0_PPU_MCAST_RSP_CNTr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000920, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_ppu_mcast_rsp_cnt_reg, + NULL, + NULL, + }, + { + "ppu_smmu0_mcast_key_cnt", + SMMU0_SMMU0_PPU_SMMU0_MCAST_KEY_CNTr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000924, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_ppu_smmu0_mcast_key_cnt_reg, + NULL, + NULL, + }, + { + "smmu0_odma_tdm_mc_rsp_cnt", + SMMU0_SMMU0_SMMU0_ODMA_TDM_MC_RSP_CNTr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000928, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_odma_tdm_mc_rsp_cnt_reg, + NULL, + NULL, + }, + { + "odma_smmu0_tdm_mc_key_cnt", + SMMU0_SMMU0_ODMA_SMMU0_TDM_MC_KEY_CNTr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000092c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_odma_smmu0_tdm_mc_key_cnt_reg, + NULL, + NULL, + }, + { + "smmu0_odma_rsp_cnt", + SMMU0_SMMU0_SMMU0_ODMA_RSP_CNTr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000930, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_odma_rsp_cnt_reg, + NULL, + NULL, + }, + { + "odma_smmu0_cmd_cnt", + SMMU0_SMMU0_ODMA_SMMU0_CMD_CNTr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000934, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_odma_smmu0_cmd_cnt_reg, + NULL, + NULL, + }, + { + "smmu0_cfg_tab_rdat_cnt", + SMMU0_SMMU0_SMMU0_CFG_TAB_RDAT_CNTr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000938, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_smmu0_cfg_tab_rdat_cnt_reg, + NULL, + NULL, + }, + { + "cfg_smmu0_tab_rd_cnt", + SMMU0_SMMU0_CFG_SMMU0_TAB_RD_CNTr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000093c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_cfg_smmu0_tab_rd_cnt_reg, + NULL, + NULL, + }, + { + "smmu0_stat_rsp15_0_cnt", + SMMU0_SMMU0_SMMU0_STAT_RSP15_0_CNTr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000940, + (32/8), + 0, + 15 + 1, + 0, + 4, + 1, + g_smmu0_smmu0_smmu0_stat_rsp15_0_cnt_reg, + NULL, + NULL, + }, + { + "stat_smmu0_req15_0_cnt", + SMMU0_SMMU0_STAT_SMMU0_REQ15_0_CNTr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000980, + (32/8), + 0, + 15 + 1, + 0, + 4, + 1, + g_smmu0_smmu0_stat_smmu0_req15_0_cnt_reg, + NULL, + NULL, + }, + { + "smmu0_ppu_mex5_0_rsp_cnt", + SMMU0_SMMU0_SMMU0_PPU_MEX5_0_RSP_CNTr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000009c0, + (32/8), + 0, + 5 + 1, + 0, + 4, + 1, + g_smmu0_smmu0_smmu0_ppu_mex5_0_rsp_cnt_reg, + NULL, + NULL, + }, + { + "ppu_smmu0_mex5_0_key_cnt", + SMMU0_SMMU0_PPU_SMMU0_MEX5_0_KEY_CNTr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000009d8, + (32/8), + 0, + 5 + 1, + 0, + 4, + 1, + g_smmu0_smmu0_ppu_smmu0_mex5_0_key_cnt_reg, + NULL, + NULL, + }, + { + "ftm_stat_smmu0_req0_cnt", + SMMU0_SMMU0_FTM_STAT_SMMU0_REQ0_CNTr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000009f0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_ftm_stat_smmu0_req0_cnt_reg, + NULL, + NULL, + }, + { + "ftm_stat_smmu0_req1_cnt", + SMMU0_SMMU0_FTM_STAT_SMMU0_REQ1_CNTr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000009f4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_ftm_stat_smmu0_req1_cnt_reg, + NULL, + NULL, + }, + { + "etm_stat_smmu0_req0_cnt", + SMMU0_SMMU0_ETM_STAT_SMMU0_REQ0_CNTr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000009f8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_etm_stat_smmu0_req0_cnt_reg, + NULL, + NULL, + }, + { + "etm_stat_smmu0_req1_cnt", + SMMU0_SMMU0_ETM_STAT_SMMU0_REQ1_CNTr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000009fc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_smmu0_smmu0_etm_stat_smmu0_req1_cnt_reg, + NULL, + NULL, + }, + { + "req_eram0_31_rd_cnt", + SMMU0_SMMU0_REQ_ERAM0_31_RD_CNTr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000a00, + (32/8), + 0, + 31 + 1, + 0, + 8, + 1, + g_smmu0_smmu0_req_eram0_31_rd_cnt_reg, + NULL, + NULL, + }, + { + "req_eram0_31_wr_cnt", + SMMU0_SMMU0_REQ_ERAM0_31_WR_CNTr, + SMMU0, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000a04, + (32/8), + 0, + 31 + 1, + 0, + 8, + 1, + g_smmu0_smmu0_req_eram0_31_wr_cnt_reg, + NULL, + NULL, + }, + { + "ddr_wdat1", + SE_SMMU1_DDR_WDAT1r, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000004, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_ddr_wdat1_reg, + NULL, + NULL, + }, + { + "ddr_wdat2", + SE_SMMU1_DDR_WDAT2r, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000008, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_ddr_wdat2_reg, + NULL, + NULL, + }, + { + "ddr_wdat3", + SE_SMMU1_DDR_WDAT3r, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000000c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_ddr_wdat3_reg, + NULL, + NULL, + }, + { + "ddr_wdat4", + SE_SMMU1_DDR_WDAT4r, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000010, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_ddr_wdat4_reg, + NULL, + NULL, + }, + { + "ddr_wdat5", + SE_SMMU1_DDR_WDAT5r, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000014, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_ddr_wdat5_reg, + NULL, + NULL, + }, + { + "ddr_wdat6", + SE_SMMU1_DDR_WDAT6r, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000018, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_ddr_wdat6_reg, + NULL, + NULL, + }, + { + "ddr_wdat7", + SE_SMMU1_DDR_WDAT7r, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000001c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_ddr_wdat7_reg, + NULL, + NULL, + }, + { + "ddr_wdat8", + SE_SMMU1_DDR_WDAT8r, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000020, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_ddr_wdat8_reg, + NULL, + NULL, + }, + { + "ddr_wdat9", + SE_SMMU1_DDR_WDAT9r, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000024, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_ddr_wdat9_reg, + NULL, + NULL, + }, + { + "ddr_wdat10", + SE_SMMU1_DDR_WDAT10r, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000028, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_ddr_wdat10_reg, + NULL, + NULL, + }, + { + "ddr_wdat11", + SE_SMMU1_DDR_WDAT11r, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000002c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_ddr_wdat11_reg, + NULL, + NULL, + }, + { + "ddr_wdat12", + SE_SMMU1_DDR_WDAT12r, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000030, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_ddr_wdat12_reg, + NULL, + NULL, + }, + { + "ddr_wdat13", + SE_SMMU1_DDR_WDAT13r, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000034, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_ddr_wdat13_reg, + NULL, + NULL, + }, + { + "ddr_wdat14", + SE_SMMU1_DDR_WDAT14r, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000038, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_ddr_wdat14_reg, + NULL, + NULL, + }, + { + "ddr_wdat15", + SE_SMMU1_DDR_WDAT15r, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000003c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_ddr_wdat15_reg, + NULL, + NULL, + }, + { + "cnt_stat_cache_en", + SE_SMMU1_CNT_STAT_CACHE_ENr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000040, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_cnt_stat_cache_en_reg, + NULL, + NULL, + }, + { + "cnt_stat_cache_clr", + SE_SMMU1_CNT_STAT_CACHE_CLRr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000044, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_cnt_stat_cache_clr_reg, + NULL, + NULL, + }, + { + "cnt_stat_cache_req_63_32", + SE_SMMU1_CNT_STAT_CACHE_REQ_63_32r, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000048, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_cnt_stat_cache_req_63_32_reg, + NULL, + NULL, + }, + { + "cnt_stat_cache_req_31_0", + SE_SMMU1_CNT_STAT_CACHE_REQ_31_0r, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000004c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_cnt_stat_cache_req_31_0_reg, + NULL, + NULL, + }, + { + "cnt_stat_cache_hit_63_32", + SE_SMMU1_CNT_STAT_CACHE_HIT_63_32r, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000050, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_cnt_stat_cache_hit_63_32_reg, + NULL, + NULL, + }, + { + "cnt_stat_cache_hit_31_0", + SE_SMMU1_CNT_STAT_CACHE_HIT_31_0r, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000054, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_cnt_stat_cache_hit_31_0_reg, + NULL, + NULL, + }, + { + "ddr_cmd0", + SE_SMMU1_DDR_CMD0r, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000060, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_se_smmu1_ddr_cmd0_reg, + NULL, + NULL, + }, + { + "info_addr", + SE_SMMU1_INFO_ADDRr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000064, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_info_addr_reg, + NULL, + NULL, + }, + { + "ddr_cmd1", + SE_SMMU1_DDR_CMD1r, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000068, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_se_smmu1_ddr_cmd1_reg, + NULL, + NULL, + }, + { + "clr_start_addr", + SE_SMMU1_CLR_START_ADDRr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000006c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_clr_start_addr_reg, + NULL, + NULL, + }, + { + "clr_end_addr", + SE_SMMU1_CLR_END_ADDRr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000070, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_clr_end_addr_reg, + NULL, + NULL, + }, + { + "clr_tbl_en", + SE_SMMU1_CLR_TBL_ENr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000074, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_se_smmu1_clr_tbl_en_reg, + NULL, + NULL, + }, + { + "debug_cnt_mode", + SE_SMMU1_DEBUG_CNT_MODEr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000084, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_se_smmu1_debug_cnt_mode_reg, + NULL, + NULL, + }, + { + "init_done", + SE_SMMU1_INIT_DONEr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000088, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_se_smmu1_init_done_reg, + NULL, + NULL, + }, + { + "cpu_rsp_rd_done", + SE_SMMU1_CPU_RSP_RD_DONEr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000008c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_cpu_rsp_rd_done_reg, + NULL, + NULL, + }, + { + "ksch_oam_sp_en", + SE_SMMU1_KSCH_OAM_SP_ENr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000090, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_ksch_oam_sp_en_reg, + NULL, + NULL, + }, + { + "cfg_cache_en", + SE_SMMU1_CFG_CACHE_ENr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000094, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_cfg_cache_en_reg, + NULL, + NULL, + }, + { + "cache_age_en", + SE_SMMU1_CACHE_AGE_ENr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000000b4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_cache_age_en_reg, + NULL, + NULL, + }, + { + "cpu_rdat0", + SE_SMMU1_CPU_RDAT0r, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000000c0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_cpu_rdat0_reg, + NULL, + NULL, + }, + { + "cpu_rdat1", + SE_SMMU1_CPU_RDAT1r, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000000c4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_cpu_rdat1_reg, + NULL, + NULL, + }, + { + "cpu_rdat2", + SE_SMMU1_CPU_RDAT2r, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000000c8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_cpu_rdat2_reg, + NULL, + NULL, + }, + { + "cpu_rdat3", + SE_SMMU1_CPU_RDAT3r, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000000cc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_cpu_rdat3_reg, + NULL, + NULL, + }, + { + "cpu_rdat4", + SE_SMMU1_CPU_RDAT4r, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000000d0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_cpu_rdat4_reg, + NULL, + NULL, + }, + { + "cpu_rdat5", + SE_SMMU1_CPU_RDAT5r, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000000d4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_cpu_rdat5_reg, + NULL, + NULL, + }, + { + "cpu_rdat6", + SE_SMMU1_CPU_RDAT6r, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000000d8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_cpu_rdat6_reg, + NULL, + NULL, + }, + { + "cpu_rdat7", + SE_SMMU1_CPU_RDAT7r, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000000dc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_cpu_rdat7_reg, + NULL, + NULL, + }, + { + "cpu_rdat8", + SE_SMMU1_CPU_RDAT8r, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000000e0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_cpu_rdat8_reg, + NULL, + NULL, + }, + { + "cpu_rdat9", + SE_SMMU1_CPU_RDAT9r, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000000e4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_cpu_rdat9_reg, + NULL, + NULL, + }, + { + "cpu_rdat10", + SE_SMMU1_CPU_RDAT10r, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000000e8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_cpu_rdat10_reg, + NULL, + NULL, + }, + { + "cpu_rdat11", + SE_SMMU1_CPU_RDAT11r, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000000ec, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_cpu_rdat11_reg, + NULL, + NULL, + }, + { + "cpu_rdat12", + SE_SMMU1_CPU_RDAT12r, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000000f0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_cpu_rdat12_reg, + NULL, + NULL, + }, + { + "cpu_rdat13", + SE_SMMU1_CPU_RDAT13r, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000000f4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_cpu_rdat13_reg, + NULL, + NULL, + }, + { + "cpu_rdat14", + SE_SMMU1_CPU_RDAT14r, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000000f8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_cpu_rdat14_reg, + NULL, + NULL, + }, + { + "cpu_rdat15", + SE_SMMU1_CPU_RDAT15r, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000000fc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_cpu_rdat15_reg, + NULL, + NULL, + }, + { + "ctrl_cpu_rd_rdy", + SE_SMMU1_CTRL_CPU_RD_RDYr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000100, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_ctrl_cpu_rd_rdy_reg, + NULL, + NULL, + }, + { + "cpu_warbi_rdy_cfg", + SE_SMMU1_CPU_WARBI_RDY_CFGr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000104, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_cpu_warbi_rdy_cfg_reg, + NULL, + NULL, + }, + { + "dir_arbi_cpu_rpful", + SE_SMMU1_DIR_ARBI_CPU_RPFULr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000108, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_se_smmu1_dir_arbi_cpu_rpful_reg, + NULL, + NULL, + }, + { + "dir_arbi_wpful", + SE_SMMU1_DIR_ARBI_WPFULr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000110, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_se_smmu1_dir_arbi_wpful_reg, + NULL, + NULL, + }, + { + "cfg_wr_arbi_pful0", + SE_SMMU1_CFG_WR_ARBI_PFUL0r, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000118, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_se_smmu1_cfg_wr_arbi_pful0_reg, + NULL, + NULL, + }, + { + "cfg_wr_arbi_pful1", + SE_SMMU1_CFG_WR_ARBI_PFUL1r, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000011c, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_se_smmu1_cfg_wr_arbi_pful1_reg, + NULL, + NULL, + }, + { + "smmu1_wdone_pful_cfg", + SE_SMMU1_SMMU1_WDONE_PFUL_CFGr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000124, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_smmu1_wdone_pful_cfg_reg, + NULL, + NULL, + }, + { + "stat_rate_cfg_cnt", + SE_SMMU1_STAT_RATE_CFG_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000128, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_stat_rate_cfg_cnt_reg, + NULL, + NULL, + }, + { + "ftm_rate_cfg_cnt", + SE_SMMU1_FTM_RATE_CFG_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000012c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_ftm_rate_cfg_cnt_reg, + NULL, + NULL, + }, + { + "etm_rate_cfg_cnt", + SE_SMMU1_ETM_RATE_CFG_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000130, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_etm_rate_cfg_cnt_reg, + NULL, + NULL, + }, + { + "dir_rate_cfg_cnt", + SE_SMMU1_DIR_RATE_CFG_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000134, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_dir_rate_cfg_cnt_reg, + NULL, + NULL, + }, + { + "hash_rate_cfg_cnt", + SE_SMMU1_HASH_RATE_CFG_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000138, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_hash_rate_cfg_cnt_reg, + NULL, + NULL, + }, + { + "ftm_tbl_cfg", + SE_SMMU1_FTM_TBL_CFGr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001c8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_ftm_tbl_cfg_reg, + NULL, + NULL, + }, + { + "lpm_v4_as_tbl_cfg", + SE_SMMU1_LPM_V4_AS_TBL_CFGr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001d0, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_se_smmu1_lpm_v4_as_tbl_cfg_reg, + NULL, + NULL, + }, + { + "lpm_v4_tbl_cfg", + SE_SMMU1_LPM_V4_TBL_CFGr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001d4, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_se_smmu1_lpm_v4_tbl_cfg_reg, + NULL, + NULL, + }, + { + "lpm_v6_tbl_cfg", + SE_SMMU1_LPM_V6_TBL_CFGr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001d8, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_se_smmu1_lpm_v6_tbl_cfg_reg, + NULL, + NULL, + }, + { + "lpm_v6_as_tbl_cfg", + SE_SMMU1_LPM_V6_AS_TBL_CFGr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001dc, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_se_smmu1_lpm_v6_as_tbl_cfg_reg, + NULL, + NULL, + }, + { + "dma_tbl_cfg", + SE_SMMU1_DMA_TBL_CFGr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001e0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_dma_tbl_cfg_reg, + NULL, + NULL, + }, + { + "oam_tbl_cfg", + SE_SMMU1_OAM_TBL_CFGr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001e4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_oam_tbl_cfg_reg, + NULL, + NULL, + }, + { + "ctrl_rpar_cpu_pful", + SE_SMMU1_CTRL_RPAR_CPU_PFULr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001e8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_ctrl_rpar_cpu_pful_reg, + NULL, + NULL, + }, + { + "cfg_ksch_dir_pful", + SE_SMMU1_CFG_KSCH_DIR_PFULr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001ec, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_cfg_ksch_dir_pful_reg, + NULL, + NULL, + }, + { + "cfg_ksch_hash_pful", + SE_SMMU1_CFG_KSCH_HASH_PFULr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001f0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_cfg_ksch_hash_pful_reg, + NULL, + NULL, + }, + { + "cfg_ksch_lpm_pful", + SE_SMMU1_CFG_KSCH_LPM_PFULr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001f4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_cfg_ksch_lpm_pful_reg, + NULL, + NULL, + }, + { + "cfg_ksch_lpm_as_pful", + SE_SMMU1_CFG_KSCH_LPM_AS_PFULr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001f8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_cfg_ksch_lpm_as_pful_reg, + NULL, + NULL, + }, + { + "cfg_ksch_stat_pful", + SE_SMMU1_CFG_KSCH_STAT_PFULr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001fc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_cfg_ksch_stat_pful_reg, + NULL, + NULL, + }, + { + "cfg_ksch_tm_pful", + SE_SMMU1_CFG_KSCH_TM_PFULr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000200, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_cfg_ksch_tm_pful_reg, + NULL, + NULL, + }, + { + "cfg_ksch_oam_pful", + SE_SMMU1_CFG_KSCH_OAM_PFULr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000204, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_cfg_ksch_oam_pful_reg, + NULL, + NULL, + }, + { + "cfg_ksch_dma_pful", + SE_SMMU1_CFG_KSCH_DMA_PFULr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000208, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_cfg_ksch_dma_pful_reg, + NULL, + NULL, + }, + { + "ctrl_wfifo_cfg", + SE_SMMU1_CTRL_WFIFO_CFGr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000230, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_ctrl_wfifo_cfg_reg, + NULL, + NULL, + }, + { + "rsch_hash_ptr_cfg", + SE_SMMU1_RSCH_HASH_PTR_CFGr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000240, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_rsch_hash_ptr_cfg_reg, + NULL, + NULL, + }, + { + "rsch_lpm_ptr_cfg", + SE_SMMU1_RSCH_LPM_PTR_CFGr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000244, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_rsch_lpm_ptr_cfg_reg, + NULL, + NULL, + }, + { + "rsch_lpm_as_ptr_cfg", + SE_SMMU1_RSCH_LPM_AS_PTR_CFGr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000248, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_rsch_lpm_as_ptr_cfg_reg, + NULL, + NULL, + }, + { + "rsch_stat_ptr_cfg", + SE_SMMU1_RSCH_STAT_PTR_CFGr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000024c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_rsch_stat_ptr_cfg_reg, + NULL, + NULL, + }, + { + "rsch_oam_ptr_cfg", + SE_SMMU1_RSCH_OAM_PTR_CFGr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000250, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_rsch_oam_ptr_cfg_reg, + NULL, + NULL, + }, + { + "rschd_fifo_pept_cfg", + SE_SMMU1_RSCHD_FIFO_PEPT_CFGr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000254, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_rschd_fifo_pept_cfg_reg, + NULL, + NULL, + }, + { + "dir_fifo_pful_cfg", + SE_SMMU1_DIR_FIFO_PFUL_CFGr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000258, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_dir_fifo_pful_cfg_reg, + NULL, + NULL, + }, + { + "hash_fifo_pful_cfg", + SE_SMMU1_HASH_FIFO_PFUL_CFGr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000025c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_hash_fifo_pful_cfg_reg, + NULL, + NULL, + }, + { + "lpm_fifo_pful_cfg", + SE_SMMU1_LPM_FIFO_PFUL_CFGr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000260, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_lpm_fifo_pful_cfg_reg, + NULL, + NULL, + }, + { + "lpm_as_fifo_pful_cfg", + SE_SMMU1_LPM_AS_FIFO_PFUL_CFGr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000264, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_lpm_as_fifo_pful_cfg_reg, + NULL, + NULL, + }, + { + "stat_fifo_pful_cfg", + SE_SMMU1_STAT_FIFO_PFUL_CFGr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000268, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_stat_fifo_pful_cfg_reg, + NULL, + NULL, + }, + { + "ftm_fifo_pful_cfg", + SE_SMMU1_FTM_FIFO_PFUL_CFGr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000026c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_ftm_fifo_pful_cfg_reg, + NULL, + NULL, + }, + { + "etm_fifo_pful_cfg", + SE_SMMU1_ETM_FIFO_PFUL_CFGr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000270, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_etm_fifo_pful_cfg_reg, + NULL, + NULL, + }, + { + "oam_fifo_pful_cfg", + SE_SMMU1_OAM_FIFO_PFUL_CFGr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000274, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_oam_fifo_pful_cfg_reg, + NULL, + NULL, + }, + { + "dma_fifo_pful_cfg", + SE_SMMU1_DMA_FIFO_PFUL_CFGr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000278, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_dma_fifo_pful_cfg_reg, + NULL, + NULL, + }, + { + "cache_rsp_rr_fifo_cfg", + SE_SMMU1_CACHE_RSP_RR_FIFO_CFGr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000027c, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_se_smmu1_cache_rsp_rr_fifo_cfg_reg, + NULL, + NULL, + }, + { + "ddr_rsp_rr_fifo_cfg", + SE_SMMU1_DDR_RSP_RR_FIFO_CFGr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000280, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_se_smmu1_ddr_rsp_rr_fifo_cfg_reg, + NULL, + NULL, + }, + { + "cpu_cahce_fifo_cfg", + SE_SMMU1_CPU_CAHCE_FIFO_CFGr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000284, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_se_smmu1_cpu_cahce_fifo_cfg_reg, + NULL, + NULL, + }, + { + "cache_rsp_fifo_cfg", + SE_SMMU1_CACHE_RSP_FIFO_CFGr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000028c, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_se_smmu1_cache_rsp_fifo_cfg_reg, + NULL, + NULL, + }, + { + "test_state", + SE_SMMU1_TEST_STATEr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000002c4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_test_state_reg, + NULL, + NULL, + }, + { + "cache_fifo_ept", + SE_SMMU1_CACHE_FIFO_EPTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000002f8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_cache_fifo_ept_reg, + NULL, + NULL, + }, + { + "rr_fifo_ept", + SE_SMMU1_RR_FIFO_EPTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000002fc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_rr_fifo_ept_reg, + NULL, + NULL, + }, + { + "wr_fifo_ept", + SE_SMMU1_WR_FIFO_EPTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000304, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_wr_fifo_ept_reg, + NULL, + NULL, + }, + { + "wdone_fifo_ept", + SE_SMMU1_WDONE_FIFO_EPTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000308, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_wdone_fifo_ept_reg, + NULL, + NULL, + }, + { + "kschd_fifo_ept0", + SE_SMMU1_KSCHD_FIFO_EPT0r, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000318, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_kschd_fifo_ept0_reg, + NULL, + NULL, + }, + { + "cash_fifo_ept", + SE_SMMU1_CASH_FIFO_EPTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000031c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_cash_fifo_ept_reg, + NULL, + NULL, + }, + { + "ctrl_fifo_ept", + SE_SMMU1_CTRL_FIFO_EPTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000320, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_ctrl_fifo_ept_reg, + NULL, + NULL, + }, + { + "smmu1_rschd_ept3", + SE_SMMU1_SMMU1_RSCHD_EPT3r, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000324, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_smmu1_rschd_ept3_reg, + NULL, + NULL, + }, + { + "smmu1_rschd_ept2", + SE_SMMU1_SMMU1_RSCHD_EPT2r, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000328, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_smmu1_rschd_ept2_reg, + NULL, + NULL, + }, + { + "smmu1_rschd_ept1", + SE_SMMU1_SMMU1_RSCHD_EPT1r, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000032c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_smmu1_rschd_ept1_reg, + NULL, + NULL, + }, + { + "smmu1_rschd_ept0", + SE_SMMU1_SMMU1_RSCHD_EPT0r, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000330, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_smmu1_rschd_ept0_reg, + NULL, + NULL, + }, + { + "cash0_ecc_err_addr", + SE_SMMU1_CASH0_ECC_ERR_ADDRr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000334, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_cash0_ecc_err_addr_reg, + NULL, + NULL, + }, + { + "arbi_cpu_wr_rdy", + SE_SMMU1_ARBI_CPU_WR_RDYr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000354, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_arbi_cpu_wr_rdy_reg, + NULL, + NULL, + }, + { + "smmu1_int_0_en", + SE_SMMU1_SMMU1_INT_0_ENr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000480, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_smmu1_int_0_en_reg, + NULL, + NULL, + }, + { + "smmu1_int_0_mask", + SE_SMMU1_SMMU1_INT_0_MASKr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000484, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_smmu1_int_0_mask_reg, + NULL, + NULL, + }, + { + "smmu1_int_1_en", + SE_SMMU1_SMMU1_INT_1_ENr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000488, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_smmu1_int_1_en_reg, + NULL, + NULL, + }, + { + "smmu1_int_1_mask", + SE_SMMU1_SMMU1_INT_1_MASKr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000048c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_smmu1_int_1_mask_reg, + NULL, + NULL, + }, + { + "smmu1_int_2_en", + SE_SMMU1_SMMU1_INT_2_ENr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000490, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_smmu1_int_2_en_reg, + NULL, + NULL, + }, + { + "smmu1_int_2_mask", + SE_SMMU1_SMMU1_INT_2_MASKr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000494, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_smmu1_int_2_mask_reg, + NULL, + NULL, + }, + { + "smmu1_int_3_en", + SE_SMMU1_SMMU1_INT_3_ENr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000498, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_smmu1_int_3_en_reg, + NULL, + NULL, + }, + { + "smmu1_int_3_mask", + SE_SMMU1_SMMU1_INT_3_MASKr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000049c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_smmu1_int_3_mask_reg, + NULL, + NULL, + }, + { + "smmu1_int_0_status", + SE_SMMU1_SMMU1_INT_0_STATUSr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000540, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_smmu1_int_0_status_reg, + NULL, + NULL, + }, + { + "smmu1_int_1_status", + SE_SMMU1_SMMU1_INT_1_STATUSr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000544, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_smmu1_int_1_status_reg, + NULL, + NULL, + }, + { + "smmu1_int_2_status", + SE_SMMU1_SMMU1_INT_2_STATUSr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000548, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_smmu1_int_2_status_reg, + NULL, + NULL, + }, + { + "smmu1_int_3_status", + SE_SMMU1_SMMU1_INT_3_STATUSr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000054c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_smmu1_int_3_status_reg, + NULL, + NULL, + }, + { + "smmu1_int_status", + SE_SMMU1_SMMU1_INT_STATUSr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000005a8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_smmu1_int_status_reg, + NULL, + NULL, + }, + { + "ctrl_to_cash7_0_fc_cnt", + SE_SMMU1_CTRL_TO_CASH7_0_FC_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000600, + (32/8), + 0, + 7 + 1, + 0, + 24, + 1, + g_se_smmu1_ctrl_to_cash7_0_fc_cnt_reg, + NULL, + NULL, + }, + { + "cash7_0_to_ctrl_req_cnt", + SE_SMMU1_CASH7_0_TO_CTRL_REQ_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000604, + (32/8), + 0, + 7 + 1, + 0, + 24, + 1, + g_se_smmu1_cash7_0_to_ctrl_req_cnt_reg, + NULL, + NULL, + }, + { + "rschd_to_cache7_fc_cnt", + SE_SMMU1_RSCHD_TO_CACHE7_FC_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000608, + (32/8), + 0, + 7 + 1, + 0, + 24, + 1, + g_se_smmu1_rschd_to_cache7_fc_cnt_reg, + NULL, + NULL, + }, + { + "cash7_to_cache_rsp_cnt", + SE_SMMU1_CASH7_TO_CACHE_RSP_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000060c, + (32/8), + 0, + 7 + 1, + 0, + 24, + 1, + g_se_smmu1_cash7_to_cache_rsp_cnt_reg, + NULL, + NULL, + }, + { + "cash7_to_ctrl_fc_cnt", + SE_SMMU1_CASH7_TO_CTRL_FC_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000610, + (32/8), + 0, + 7 + 1, + 0, + 24, + 1, + g_se_smmu1_cash7_to_ctrl_fc_cnt_reg, + NULL, + NULL, + }, + { + "ctrl_to_cash7_0_rsp_cnt", + SE_SMMU1_CTRL_TO_CASH7_0_RSP_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000614, + (32/8), + 0, + 7 + 1, + 0, + 24, + 1, + g_se_smmu1_ctrl_to_cash7_0_rsp_cnt_reg, + NULL, + NULL, + }, + { + "kschd_to_cache7_0_req_cnt", + SE_SMMU1_KSCHD_TO_CACHE7_0_REQ_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000006c0, + (32/8), + 0, + 7 + 1, + 0, + 4, + 1, + g_se_smmu1_kschd_to_cache7_0_req_cnt_reg, + NULL, + NULL, + }, + { + "cache7_0_to_kschd_fc_cnt", + SE_SMMU1_CACHE7_0_TO_KSCHD_FC_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000006e0, + (32/8), + 0, + 7 + 1, + 0, + 4, + 1, + g_se_smmu1_cache7_0_to_kschd_fc_cnt_reg, + NULL, + NULL, + }, + { + "dma_to_smmu1_rd_req_cnt", + SE_SMMU1_DMA_TO_SMMU1_RD_REQ_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000700, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_dma_to_smmu1_rd_req_cnt_reg, + NULL, + NULL, + }, + { + "oam_to_kschd_req_cnt", + SE_SMMU1_OAM_TO_KSCHD_REQ_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000704, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_oam_to_kschd_req_cnt_reg, + NULL, + NULL, + }, + { + "oam_rr_state_rsp_cnt", + SE_SMMU1_OAM_RR_STATE_RSP_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000708, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_oam_rr_state_rsp_cnt_reg, + NULL, + NULL, + }, + { + "oam_clash_info_cnt", + SE_SMMU1_OAM_CLASH_INFO_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000070c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_oam_clash_info_cnt_reg, + NULL, + NULL, + }, + { + "oam_to_rr_req_cnt", + SE_SMMU1_OAM_TO_RR_REQ_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000710, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_oam_to_rr_req_cnt_reg, + NULL, + NULL, + }, + { + "lpm_as_to_kschd_req_cnt", + SE_SMMU1_LPM_AS_TO_KSCHD_REQ_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000714, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_lpm_as_to_kschd_req_cnt_reg, + NULL, + NULL, + }, + { + "lpm_as_rr_state_rsp_cnt", + SE_SMMU1_LPM_AS_RR_STATE_RSP_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000718, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_lpm_as_rr_state_rsp_cnt_reg, + NULL, + NULL, + }, + { + "lpm_as_clash_info_cnt", + SE_SMMU1_LPM_AS_CLASH_INFO_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000071c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_lpm_as_clash_info_cnt_reg, + NULL, + NULL, + }, + { + "lpm_as_to_rr_req_cnt", + SE_SMMU1_LPM_AS_TO_RR_REQ_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000720, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_lpm_as_to_rr_req_cnt_reg, + NULL, + NULL, + }, + { + "lpm_to_kschd_req_cnt", + SE_SMMU1_LPM_TO_KSCHD_REQ_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000724, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_lpm_to_kschd_req_cnt_reg, + NULL, + NULL, + }, + { + "lpm_rr_state_rsp_cnt", + SE_SMMU1_LPM_RR_STATE_RSP_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000728, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_lpm_rr_state_rsp_cnt_reg, + NULL, + NULL, + }, + { + "lpm_clash_info_cnt", + SE_SMMU1_LPM_CLASH_INFO_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000072c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_lpm_clash_info_cnt_reg, + NULL, + NULL, + }, + { + "lpm_to_rr_req_cnt", + SE_SMMU1_LPM_TO_RR_REQ_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000730, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_lpm_to_rr_req_cnt_reg, + NULL, + NULL, + }, + { + "hash3_0_to_kschd_req_cnt", + SE_SMMU1_HASH3_0_TO_KSCHD_REQ_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000734, + (32/8), + 0, + 3 + 1, + 0, + 16, + 1, + g_se_smmu1_hash3_0_to_kschd_req_cnt_reg, + NULL, + NULL, + }, + { + "hash3_0_rr_state_rsp_cnt", + SE_SMMU1_HASH3_0_RR_STATE_RSP_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000738, + (32/8), + 0, + 3 + 1, + 0, + 16, + 1, + g_se_smmu1_hash3_0_rr_state_rsp_cnt_reg, + NULL, + NULL, + }, + { + "hash3_0_clash_info_cnt", + SE_SMMU1_HASH3_0_CLASH_INFO_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000073c, + (32/8), + 0, + 3 + 1, + 0, + 16, + 1, + g_se_smmu1_hash3_0_clash_info_cnt_reg, + NULL, + NULL, + }, + { + "hash3_0_to_rr_req_cnt", + SE_SMMU1_HASH3_0_TO_RR_REQ_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000740, + (32/8), + 0, + 3 + 1, + 0, + 16, + 1, + g_se_smmu1_hash3_0_to_rr_req_cnt_reg, + NULL, + NULL, + }, + { + "dir3_0_to_kschd_req_cnt", + SE_SMMU1_DIR3_0_TO_KSCHD_REQ_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000774, + (32/8), + 0, + 3 + 1, + 0, + 8, + 1, + g_se_smmu1_dir3_0_to_kschd_req_cnt_reg, + NULL, + NULL, + }, + { + "dir3_0_clash_info_cnt", + SE_SMMU1_DIR3_0_CLASH_INFO_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000778, + (32/8), + 0, + 3 + 1, + 0, + 8, + 1, + g_se_smmu1_dir3_0_clash_info_cnt_reg, + NULL, + NULL, + }, + { + "dir_tbl_wr_req_cnt", + SE_SMMU1_DIR_TBL_WR_REQ_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000794, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_dir_tbl_wr_req_cnt_reg, + NULL, + NULL, + }, + { + "warbi_to_dir_tbl_warbi_fc_cnt", + SE_SMMU1_WARBI_TO_DIR_TBL_WARBI_FC_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000798, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_warbi_to_dir_tbl_warbi_fc_cnt_reg, + NULL, + NULL, + }, + { + "dir3_0_to_bank_rr_req_cnt", + SE_SMMU1_DIR3_0_TO_BANK_RR_REQ_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000079c, + (32/8), + 0, + 3 + 1, + 0, + 4, + 1, + g_se_smmu1_dir3_0_to_bank_rr_req_cnt_reg, + NULL, + NULL, + }, + { + "kschd_to_dir3_0_fc_cnt", + SE_SMMU1_KSCHD_TO_DIR3_0_FC_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000007ac, + (32/8), + 0, + 3 + 1, + 0, + 4, + 1, + g_se_smmu1_kschd_to_dir3_0_fc_cnt_reg, + NULL, + NULL, + }, + { + "dir3_0_rr_state_rsp_cnt", + SE_SMMU1_DIR3_0_RR_STATE_RSP_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000007bc, + (32/8), + 0, + 3 + 1, + 0, + 4, + 1, + g_se_smmu1_dir3_0_rr_state_rsp_cnt_reg, + NULL, + NULL, + }, + { + "wr_done_to_warbi_fc_cnt", + SE_SMMU1_WR_DONE_TO_WARBI_FC_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000007cc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_wr_done_to_warbi_fc_cnt_reg, + NULL, + NULL, + }, + { + "wr_done_ptr_req_cnt", + SE_SMMU1_WR_DONE_PTR_REQ_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000007d0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_wr_done_ptr_req_cnt_reg, + NULL, + NULL, + }, + { + "ctrl7_0_to_warbi_fc_cnt", + SE_SMMU1_CTRL7_0_TO_WARBI_FC_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000007d4, + (32/8), + 0, + 7 + 1, + 0, + 4, + 1, + g_se_smmu1_ctrl7_0_to_warbi_fc_cnt_reg, + NULL, + NULL, + }, + { + "warbi_to_ctrl7_0_wr_req_cnt", + SE_SMMU1_WARBI_TO_CTRL7_0_WR_REQ_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000007f4, + (32/8), + 0, + 7 + 1, + 0, + 4, + 1, + g_se_smmu1_warbi_to_ctrl7_0_wr_req_cnt_reg, + NULL, + NULL, + }, + { + "warbi_to_cash7_0_wr_req_cnt", + SE_SMMU1_WARBI_TO_CASH7_0_WR_REQ_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000814, + (32/8), + 0, + 7 + 1, + 0, + 4, + 1, + g_se_smmu1_warbi_to_cash7_0_wr_req_cnt_reg, + NULL, + NULL, + }, + { + "warbi_to_cpu_wr_fc_cnt", + SE_SMMU1_WARBI_TO_CPU_WR_FC_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000834, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_warbi_to_cpu_wr_fc_cnt_reg, + NULL, + NULL, + }, + { + "cpu_wr_req_cnt", + SE_SMMU1_CPU_WR_REQ_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000838, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_cpu_wr_req_cnt_reg, + NULL, + NULL, + }, + { + "ctrl7_0_to_cpu_rd_rsp_cnt", + SE_SMMU1_CTRL7_0_TO_CPU_RD_RSP_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000083c, + (32/8), + 0, + 7 + 1, + 0, + 4, + 1, + g_se_smmu1_ctrl7_0_to_cpu_rd_rsp_cnt_reg, + NULL, + NULL, + }, + { + "cpu_to_ctrl7_0_rd_req_cnt", + SE_SMMU1_CPU_TO_CTRL7_0_RD_REQ_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000085c, + (32/8), + 0, + 7 + 1, + 0, + 4, + 1, + g_se_smmu1_cpu_to_ctrl7_0_rd_req_cnt_reg, + NULL, + NULL, + }, + { + "cpu_rd_dir_tbl_rsp_cnt", + SE_SMMU1_CPU_RD_DIR_TBL_RSP_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000087c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_cpu_rd_dir_tbl_rsp_cnt_reg, + NULL, + NULL, + }, + { + "cpu_to_dir_tbl_rd_wr_req_cnt", + SE_SMMU1_CPU_TO_DIR_TBL_RD_WR_REQ_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000880, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_cpu_to_dir_tbl_rd_wr_req_cnt_reg, + NULL, + NULL, + }, + { + "smmu1_to_mmu_7_0_rsp_fc_cnt", + SE_SMMU1_SMMU1_TO_MMU_7_0_RSP_FC_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000884, + (32/8), + 0, + 7 + 1, + 0, + 24, + 1, + g_se_smmu1_smmu1_to_mmu_7_0_rsp_fc_cnt_reg, + NULL, + NULL, + }, + { + "mmu_7_0_to_smmu1_rd_rsp_cnt", + SE_SMMU1_MMU_7_0_TO_SMMU1_RD_RSP_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000888, + (32/8), + 0, + 7 + 1, + 0, + 24, + 1, + g_se_smmu1_mmu_7_0_to_smmu1_rd_rsp_cnt_reg, + NULL, + NULL, + }, + { + "mmu_7_0_to_smmu1_rd_fc_cnt", + SE_SMMU1_MMU_7_0_TO_SMMU1_RD_FC_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000088c, + (32/8), + 0, + 7 + 1, + 0, + 24, + 1, + g_se_smmu1_mmu_7_0_to_smmu1_rd_fc_cnt_reg, + NULL, + NULL, + }, + { + "smmu1_to_mmu_7_rd_req_cnt", + SE_SMMU1_SMMU1_TO_MMU_7_RD_REQ_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000890, + (32/8), + 0, + 7 + 1, + 0, + 24, + 1, + g_se_smmu1_smmu1_to_mmu_7_rd_req_cnt_reg, + NULL, + NULL, + }, + { + "mmu_7_to_smmu1_wr_fc_cnt", + SE_SMMU1_MMU_7_TO_SMMU1_WR_FC_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000894, + (32/8), + 0, + 7 + 1, + 0, + 24, + 1, + g_se_smmu1_mmu_7_to_smmu1_wr_fc_cnt_reg, + NULL, + NULL, + }, + { + "smmu1_to_mmu_7_0_wr_req_cnt", + SE_SMMU1_SMMU1_TO_MMU_7_0_WR_REQ_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000898, + (32/8), + 0, + 7 + 1, + 0, + 24, + 1, + g_se_smmu1_smmu1_to_mmu_7_0_wr_req_cnt_reg, + NULL, + NULL, + }, + { + "se_to_smmu1_wr_rsp_fc_cnt", + SE_SMMU1_SE_TO_SMMU1_WR_RSP_FC_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000944, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_se_to_smmu1_wr_rsp_fc_cnt_reg, + NULL, + NULL, + }, + { + "smmu1_to_se_wr_rsp_cnt", + SE_SMMU1_SMMU1_TO_SE_WR_RSP_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000948, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_smmu1_to_se_wr_rsp_cnt_reg, + NULL, + NULL, + }, + { + "ddr7_0_wr_rsp_cnt", + SE_SMMU1_DDR7_0_WR_RSP_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000094c, + (32/8), + 0, + 7 + 1, + 0, + 4, + 1, + g_se_smmu1_ddr7_0_wr_rsp_cnt_reg, + NULL, + NULL, + }, + { + "smmu1_to_as_fc_cnt", + SE_SMMU1_SMMU1_TO_AS_FC_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000096c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_smmu1_to_as_fc_cnt_reg, + NULL, + NULL, + }, + { + "as_to_smmu1_wr_req_cnt", + SE_SMMU1_AS_TO_SMMU1_WR_REQ_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000970, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_as_to_smmu1_wr_req_cnt_reg, + NULL, + NULL, + }, + { + "smmu1_to_se_parser_fc_cnt", + SE_SMMU1_SMMU1_TO_SE_PARSER_FC_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000974, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_smmu1_to_se_parser_fc_cnt_reg, + NULL, + NULL, + }, + { + "se_parser_to_smmu1_req_cnt", + SE_SMMU1_SE_PARSER_TO_SMMU1_REQ_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000978, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_se_parser_to_smmu1_req_cnt_reg, + NULL, + NULL, + }, + { + "smmu1_to_etm_wr_fc_cnt", + SE_SMMU1_SMMU1_TO_ETM_WR_FC_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000097c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_smmu1_to_etm_wr_fc_cnt_reg, + NULL, + NULL, + }, + { + "etm_wr_req_cnt", + SE_SMMU1_ETM_WR_REQ_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000980, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_etm_wr_req_cnt_reg, + NULL, + NULL, + }, + { + "smmu1_to_ftm_wr_fc_cnt", + SE_SMMU1_SMMU1_TO_FTM_WR_FC_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000984, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_smmu1_to_ftm_wr_fc_cnt_reg, + NULL, + NULL, + }, + { + "ftm_wr_req_cnt", + SE_SMMU1_FTM_WR_REQ_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000988, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_ftm_wr_req_cnt_reg, + NULL, + NULL, + }, + { + "smmu1_to_state_wr_fc_cnt", + SE_SMMU1_SMMU1_TO_STATE_WR_FC_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000098c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_smmu1_to_state_wr_fc_cnt_reg, + NULL, + NULL, + }, + { + "state_wr_req_cnt", + SE_SMMU1_STATE_WR_REQ_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000990, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_state_wr_req_cnt_reg, + NULL, + NULL, + }, + { + "se_to_dma_rsp_cnt", + SE_SMMU1_SE_TO_DMA_RSP_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000994, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_se_to_dma_rsp_cnt_reg, + NULL, + NULL, + }, + { + "se_to_dma_fc_cnt", + SE_SMMU1_SE_TO_DMA_FC_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000998, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_se_to_dma_fc_cnt_reg, + NULL, + NULL, + }, + { + "oam_to_smmu1_fc_cnt", + SE_SMMU1_OAM_TO_SMMU1_FC_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000099c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_oam_to_smmu1_fc_cnt_reg, + NULL, + NULL, + }, + { + "smmu1_to_oam_rsp_cnt", + SE_SMMU1_SMMU1_TO_OAM_RSP_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009a0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_smmu1_to_oam_rsp_cnt_reg, + NULL, + NULL, + }, + { + "smmu1_to_oam_fc_cnt", + SE_SMMU1_SMMU1_TO_OAM_FC_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009a4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_smmu1_to_oam_fc_cnt_reg, + NULL, + NULL, + }, + { + "oam_to_smmu1_req_cnt", + SE_SMMU1_OAM_TO_SMMU1_REQ_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009a8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_oam_to_smmu1_req_cnt_reg, + NULL, + NULL, + }, + { + "smmu1_to_etm_rsp_cnt", + SE_SMMU1_SMMU1_TO_ETM_RSP_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009ac, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_smmu1_to_etm_rsp_cnt_reg, + NULL, + NULL, + }, + { + "smmu1_to_ftm_rsp_cnt", + SE_SMMU1_SMMU1_TO_FTM_RSP_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009b0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_smmu1_to_ftm_rsp_cnt_reg, + NULL, + NULL, + }, + { + "smmu1_to_etm_fc_cnt", + SE_SMMU1_SMMU1_TO_ETM_FC_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009b4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_smmu1_to_etm_fc_cnt_reg, + NULL, + NULL, + }, + { + "etm_to_smmu1_req_cnt", + SE_SMMU1_ETM_TO_SMMU1_REQ_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009b8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_etm_to_smmu1_req_cnt_reg, + NULL, + NULL, + }, + { + "smmu1_to_ftm_fc_cnt", + SE_SMMU1_SMMU1_TO_FTM_FC_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009bc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_smmu1_to_ftm_fc_cnt_reg, + NULL, + NULL, + }, + { + "ftm_to_smmu1_req_cnt", + SE_SMMU1_FTM_TO_SMMU1_REQ_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009c0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_ftm_to_smmu1_req_cnt_reg, + NULL, + NULL, + }, + { + "smmu1_to_stat_rsp_cnt", + SE_SMMU1_SMMU1_TO_STAT_RSP_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009c4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_smmu1_to_stat_rsp_cnt_reg, + NULL, + NULL, + }, + { + "smmu1_to_stat_fc_cnt", + SE_SMMU1_SMMU1_TO_STAT_FC_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009c8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_smmu1_to_stat_fc_cnt_reg, + NULL, + NULL, + }, + { + "stat_to_smmu1_req_cnt", + SE_SMMU1_STAT_TO_SMMU1_REQ_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009cc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_stat_to_smmu1_req_cnt_reg, + NULL, + NULL, + }, + { + "lpm_as_to_smmu1_fc_cnt", + SE_SMMU1_LPM_AS_TO_SMMU1_FC_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009d0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_lpm_as_to_smmu1_fc_cnt_reg, + NULL, + NULL, + }, + { + "lpm_to_smmu1_fc_cnt", + SE_SMMU1_LPM_TO_SMMU1_FC_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009d4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_lpm_to_smmu1_fc_cnt_reg, + NULL, + NULL, + }, + { + "smmu1_to_lpm_as_rsp_cnt", + SE_SMMU1_SMMU1_TO_LPM_AS_RSP_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009d8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_smmu1_to_lpm_as_rsp_cnt_reg, + NULL, + NULL, + }, + { + "smmu1_to_lpm_rsp_cnt", + SE_SMMU1_SMMU1_TO_LPM_RSP_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009dc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_smmu1_to_lpm_rsp_cnt_reg, + NULL, + NULL, + }, + { + "smmu1_to_lpm_as_fc_cnt", + SE_SMMU1_SMMU1_TO_LPM_AS_FC_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009e0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_smmu1_to_lpm_as_fc_cnt_reg, + NULL, + NULL, + }, + { + "smmu1_to_lpm_fc_cnt", + SE_SMMU1_SMMU1_TO_LPM_FC_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009e4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_smmu1_to_lpm_fc_cnt_reg, + NULL, + NULL, + }, + { + "lpm_as_to_smmu1_req_cnt", + SE_SMMU1_LPM_AS_TO_SMMU1_REQ_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009e8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_lpm_as_to_smmu1_req_cnt_reg, + NULL, + NULL, + }, + { + "lpm_to_smmu1_req_cnt", + SE_SMMU1_LPM_TO_SMMU1_REQ_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009ec, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_smmu1_lpm_to_smmu1_req_cnt_reg, + NULL, + NULL, + }, + { + "hash3_0_to_smmu1_fc_cnt", + SE_SMMU1_HASH3_0_TO_SMMU1_FC_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009f0, + (32/8), + 0, + 3 + 1, + 0, + 4, + 1, + g_se_smmu1_hash3_0_to_smmu1_fc_cnt_reg, + NULL, + NULL, + }, + { + "smmu1_to_hash3_0_rsp_cnt", + SE_SMMU1_SMMU1_TO_HASH3_0_RSP_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000a00, + (32/8), + 0, + 3 + 1, + 0, + 4, + 1, + g_se_smmu1_smmu1_to_hash3_0_rsp_cnt_reg, + NULL, + NULL, + }, + { + "smmu1_to_hash3_0_fc_cnt", + SE_SMMU1_SMMU1_TO_HASH3_0_FC_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000a10, + (32/8), + 0, + 3 + 1, + 0, + 4, + 1, + g_se_smmu1_smmu1_to_hash3_0_fc_cnt_reg, + NULL, + NULL, + }, + { + "hash3_0_to_smmu1_cnt", + SE_SMMU1_HASH3_0_TO_SMMU1_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000a20, + (32/8), + 0, + 3 + 1, + 0, + 4, + 1, + g_se_smmu1_hash3_0_to_smmu1_cnt_reg, + NULL, + NULL, + }, + { + "se_to_smmu1_dir3_0_rsp_fc_cnt", + SE_SMMU1_SE_TO_SMMU1_DIR3_0_RSP_FC_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000a30, + (32/8), + 0, + 3 + 1, + 0, + 4, + 1, + g_se_smmu1_se_to_smmu1_dir3_0_rsp_fc_cnt_reg, + NULL, + NULL, + }, + { + "smmu1_to_se_dir3_0_rsp_cnt", + SE_SMMU1_SMMU1_TO_SE_DIR3_0_RSP_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000a40, + (32/8), + 0, + 3 + 1, + 0, + 4, + 1, + g_se_smmu1_smmu1_to_se_dir3_0_rsp_cnt_reg, + NULL, + NULL, + }, + { + "smmu1_to_se_dir3_0_fc_cnt", + SE_SMMU1_SMMU1_TO_SE_DIR3_0_FC_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000a50, + (32/8), + 0, + 3 + 1, + 0, + 4, + 1, + g_se_smmu1_smmu1_to_se_dir3_0_fc_cnt_reg, + NULL, + NULL, + }, + { + "se_to_smmu1_dir3_0_cnt", + SE_SMMU1_SE_TO_SMMU1_DIR3_0_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000a60, + (32/8), + 0, + 3 + 1, + 0, + 4, + 1, + g_se_smmu1_se_to_smmu1_dir3_0_cnt_reg, + NULL, + NULL, + }, + { + "cache7_0_to_rschd_rsp_cnt", + SE_SMMU1_CACHE7_0_TO_RSCHD_RSP_CNTr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000a70, + (32/8), + 0, + 7 + 1, + 0, + 4, + 1, + g_se_smmu1_cache7_0_to_rschd_rsp_cnt_reg, + NULL, + NULL, + }, + { + "ddr_rw_addr", + SE_CMMU_DDR_RW_ADDRr, + SMMU1, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x00000000, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cmmu_ddr_rw_addr_reg, + NULL, + NULL, + }, + { + "ddr_rw_mode", + SE_CMMU_DDR_RW_MODEr, + SMMU1, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x00000004, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_se_cmmu_ddr_rw_mode_reg, + NULL, + NULL, + }, + { + "cp_cmd", + SE_CMMU_CP_CMDr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x00000018, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cmmu_cp_cmd_reg, + NULL, + NULL, + }, + { + "cpu_ind_rd_done", + SE_CMMU_CPU_IND_RD_DONEr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x0000001c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cmmu_cpu_ind_rd_done_reg, + NULL, + NULL, + }, + { + "cpu_ind_rdat0", + SE_CMMU_CPU_IND_RDAT0r, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x00000020, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cmmu_cpu_ind_rdat0_reg, + NULL, + NULL, + }, + { + "cpu_ind_rdat1", + SE_CMMU_CPU_IND_RDAT1r, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x00000024, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cmmu_cpu_ind_rdat1_reg, + NULL, + NULL, + }, + { + "cpu_ind_rdat2", + SE_CMMU_CPU_IND_RDAT2r, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x00000028, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cmmu_cpu_ind_rdat2_reg, + NULL, + NULL, + }, + { + "cpu_ind_rdat3", + SE_CMMU_CPU_IND_RDAT3r, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x0000002c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cmmu_cpu_ind_rdat3_reg, + NULL, + NULL, + }, + { + "cpu_ddr_fifo_almful", + SE_CMMU_CPU_DDR_FIFO_ALMFULr, + SMMU1, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x00000030, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cmmu_cpu_ddr_fifo_almful_reg, + NULL, + NULL, + }, + { + "debug_cnt_mode", + SE_CMMU_DEBUG_CNT_MODEr, + SMMU1, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x00000034, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_se_cmmu_debug_cnt_mode_reg, + NULL, + NULL, + }, + { + "cmmu_pful_cfg", + SE_CMMU_CMMU_PFUL_CFGr, + SMMU1, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x00000038, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_se_cmmu_cmmu_pful_cfg_reg, + NULL, + NULL, + }, + { + "cmmu_stat_pful_cfg", + SE_CMMU_CMMU_STAT_PFUL_CFGr, + SMMU1, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x0000003c, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_se_cmmu_cmmu_stat_pful_cfg_reg, + NULL, + NULL, + }, + { + "stat_overflow_mode", + SE_CMMU_STAT_OVERFLOW_MODEr, + SMMU1, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x00000040, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cmmu_stat_overflow_mode_reg, + NULL, + NULL, + }, + { + "cmmu_cp_fifo_pful", + SE_CMMU_CMMU_CP_FIFO_PFULr, + SMMU1, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x00000044, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cmmu_cmmu_cp_fifo_pful_reg, + NULL, + NULL, + }, + { + "ddr_wr_dat0", + SE_CMMU_DDR_WR_DAT0r, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x00000078, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cmmu_ddr_wr_dat0_reg, + NULL, + NULL, + }, + { + "ddr_wr_dat1", + SE_CMMU_DDR_WR_DAT1r, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x0000007c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cmmu_ddr_wr_dat1_reg, + NULL, + NULL, + }, + { + "cmmu_int_unmask_flag", + SE_CMMU_CMMU_INT_UNMASK_FLAGr, + SMMU1, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x00000080, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cmmu_cmmu_int_unmask_flag_reg, + NULL, + NULL, + }, + { + "cmmu_int_en", + SE_CMMU_CMMU_INT_ENr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x00000084, + (32/8), + 0, + 0, + 0, + 0, + 13, + g_se_cmmu_cmmu_int_en_reg, + NULL, + NULL, + }, + { + "cmmu_int_mask", + SE_CMMU_CMMU_INT_MASKr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x00000088, + (32/8), + 0, + 0, + 0, + 0, + 13, + g_se_cmmu_cmmu_int_mask_reg, + NULL, + NULL, + }, + { + "cmmu_int_status", + SE_CMMU_CMMU_INT_STATUSr, + SMMU1, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x0000008c, + (32/8), + 0, + 0, + 0, + 0, + 13, + g_se_cmmu_cmmu_int_status_reg, + NULL, + NULL, + }, + { + "stat_cmmu_req_cnt", + SE_CMMU_STAT_CMMU_REQ_CNTr, + SMMU1, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x00000400, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cmmu_stat_cmmu_req_cnt_reg, + NULL, + NULL, + }, + { + "cmmu_fc0_cnt", + SE_CMMU_CMMU_FC0_CNTr, + SMMU1, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x00000404, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cmmu_cmmu_fc0_cnt_reg, + NULL, + NULL, + }, + { + "cmmu_fc1_cnt", + SE_CMMU_CMMU_FC1_CNTr, + SMMU1, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x00000408, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cmmu_cmmu_fc1_cnt_reg, + NULL, + NULL, + }, + { + "cmmu_fc2_cnt", + SE_CMMU_CMMU_FC2_CNTr, + SMMU1, + DPP_REG_FLAG_INDIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x0000040c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_se_cmmu_cmmu_fc2_cnt_reg, + NULL, + NULL, + }, + { + "hash0_tbl0_cfg", + SMMU14K_SE_SMMU1_HASH0_TBL0_CFGr, + SMMU14K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000148, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_smmu14k_se_smmu1_hash0_tbl0_cfg_reg, + dpp_se_write, + dpp_se_read, + }, + { + "hash0_tbl1_cfg", + SMMU14K_SE_SMMU1_HASH0_TBL1_CFGr, + SMMU14K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000014c, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_smmu14k_se_smmu1_hash0_tbl1_cfg_reg, + dpp_se_write, + dpp_se_read, + }, + { + "hash0_tbl2_cfg", + SMMU14K_SE_SMMU1_HASH0_TBL2_CFGr, + SMMU14K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000150, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_smmu14k_se_smmu1_hash0_tbl2_cfg_reg, + dpp_se_write, + dpp_se_read, + }, + { + "hash0_tbl3_cfg", + SMMU14K_SE_SMMU1_HASH0_TBL3_CFGr, + SMMU14K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000154, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_smmu14k_se_smmu1_hash0_tbl3_cfg_reg, + dpp_se_write, + dpp_se_read, + }, + { + "hash0_tbl4_cfg", + SMMU14K_SE_SMMU1_HASH0_TBL4_CFGr, + SMMU14K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000158, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_smmu14k_se_smmu1_hash0_tbl4_cfg_reg, + dpp_se_write, + dpp_se_read, + }, + { + "hash0_tbl5_cfg", + SMMU14K_SE_SMMU1_HASH0_TBL5_CFGr, + SMMU14K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000015c, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_smmu14k_se_smmu1_hash0_tbl5_cfg_reg, + dpp_se_write, + dpp_se_read, + }, + { + "hash0_tbl6_cfg", + SMMU14K_SE_SMMU1_HASH0_TBL6_CFGr, + SMMU14K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000160, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_smmu14k_se_smmu1_hash0_tbl6_cfg_reg, + dpp_se_write, + dpp_se_read, + }, + { + "hash0_tbl7_cfg", + SMMU14K_SE_SMMU1_HASH0_TBL7_CFGr, + SMMU14K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000164, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_smmu14k_se_smmu1_hash0_tbl7_cfg_reg, + dpp_se_write, + dpp_se_read, + }, + { + "hash1_tbl0_cfg", + SMMU14K_SE_SMMU1_HASH1_TBL0_CFGr, + SMMU14K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000168, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_smmu14k_se_smmu1_hash1_tbl0_cfg_reg, + dpp_se_write, + dpp_se_read, + }, + { + "hash1_tbl1_cfg", + SMMU14K_SE_SMMU1_HASH1_TBL1_CFGr, + SMMU14K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000016c, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_smmu14k_se_smmu1_hash1_tbl1_cfg_reg, + dpp_se_write, + dpp_se_read, + }, + { + "hash1_tbl2_cfg", + SMMU14K_SE_SMMU1_HASH1_TBL2_CFGr, + SMMU14K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000170, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_smmu14k_se_smmu1_hash1_tbl2_cfg_reg, + dpp_se_write, + dpp_se_read, + }, + { + "hash1_tbl3_cfg", + SMMU14K_SE_SMMU1_HASH1_TBL3_CFGr, + SMMU14K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000174, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_smmu14k_se_smmu1_hash1_tbl3_cfg_reg, + dpp_se_write, + dpp_se_read, + }, + { + "hash1_tbl4_cfg", + SMMU14K_SE_SMMU1_HASH1_TBL4_CFGr, + SMMU14K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000178, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_smmu14k_se_smmu1_hash1_tbl4_cfg_reg, + dpp_se_write, + dpp_se_read, + }, + { + "hash1_tbl5_cfg", + SMMU14K_SE_SMMU1_HASH1_TBL5_CFGr, + SMMU14K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000017c, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_smmu14k_se_smmu1_hash1_tbl5_cfg_reg, + dpp_se_write, + dpp_se_read, + }, + { + "hash1_tbl6_cfg", + SMMU14K_SE_SMMU1_HASH1_TBL6_CFGr, + SMMU14K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000180, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_smmu14k_se_smmu1_hash1_tbl6_cfg_reg, + dpp_se_write, + dpp_se_read, + }, + { + "hash1_tbl7_cfg", + SMMU14K_SE_SMMU1_HASH1_TBL7_CFGr, + SMMU14K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000184, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_smmu14k_se_smmu1_hash1_tbl7_cfg_reg, + dpp_se_write, + dpp_se_read, + }, + { + "hash2_tbl0_cfg", + SMMU14K_SE_SMMU1_HASH2_TBL0_CFGr, + SMMU14K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000188, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_smmu14k_se_smmu1_hash2_tbl0_cfg_reg, + dpp_se_write, + dpp_se_read, + }, + { + "hash2_tbl1_cfg", + SMMU14K_SE_SMMU1_HASH2_TBL1_CFGr, + SMMU14K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000018c, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_smmu14k_se_smmu1_hash2_tbl1_cfg_reg, + dpp_se_write, + dpp_se_read, + }, + { + "hash2_tbl2_cfg", + SMMU14K_SE_SMMU1_HASH2_TBL2_CFGr, + SMMU14K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000190, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_smmu14k_se_smmu1_hash2_tbl2_cfg_reg, + dpp_se_write, + dpp_se_read, + }, + { + "hash2_tbl3_cfg", + SMMU14K_SE_SMMU1_HASH2_TBL3_CFGr, + SMMU14K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000194, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_smmu14k_se_smmu1_hash2_tbl3_cfg_reg, + dpp_se_write, + dpp_se_read, + }, + { + "hash2_tbl4_cfg", + SMMU14K_SE_SMMU1_HASH2_TBL4_CFGr, + SMMU14K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000198, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_smmu14k_se_smmu1_hash2_tbl4_cfg_reg, + dpp_se_write, + dpp_se_read, + }, + { + "hash2_tbl5_cfg", + SMMU14K_SE_SMMU1_HASH2_TBL5_CFGr, + SMMU14K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000019c, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_smmu14k_se_smmu1_hash2_tbl5_cfg_reg, + dpp_se_write, + dpp_se_read, + }, + { + "hash2_tbl6_cfg", + SMMU14K_SE_SMMU1_HASH2_TBL6_CFGr, + SMMU14K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001a0, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_smmu14k_se_smmu1_hash2_tbl6_cfg_reg, + dpp_se_write, + dpp_se_read, + }, + { + "hash2_tbl7_cfg", + SMMU14K_SE_SMMU1_HASH2_TBL7_CFGr, + SMMU14K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001a4, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_smmu14k_se_smmu1_hash2_tbl7_cfg_reg, + dpp_se_write, + dpp_se_read, + }, + { + "hash3_tbl0_cfg", + SMMU14K_SE_SMMU1_HASH3_TBL0_CFGr, + SMMU14K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001a8, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_smmu14k_se_smmu1_hash3_tbl0_cfg_reg, + dpp_se_write, + dpp_se_read, + }, + { + "hash3_tbl1_cfg", + SMMU14K_SE_SMMU1_HASH3_TBL1_CFGr, + SMMU14K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001ac, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_smmu14k_se_smmu1_hash3_tbl1_cfg_reg, + dpp_se_write, + dpp_se_read, + }, + { + "hash3_tbl2_cfg", + SMMU14K_SE_SMMU1_HASH3_TBL2_CFGr, + SMMU14K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001b0, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_smmu14k_se_smmu1_hash3_tbl2_cfg_reg, + dpp_se_write, + dpp_se_read, + }, + { + "hash3_tbl3_cfg", + SMMU14K_SE_SMMU1_HASH3_TBL3_CFGr, + SMMU14K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001b4, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_smmu14k_se_smmu1_hash3_tbl3_cfg_reg, + dpp_se_write, + dpp_se_read, + }, + { + "hash3_tbl4_cfg", + SMMU14K_SE_SMMU1_HASH3_TBL4_CFGr, + SMMU14K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001b8, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_smmu14k_se_smmu1_hash3_tbl4_cfg_reg, + dpp_se_write, + dpp_se_read, + }, + { + "hash3_tbl5_cfg", + SMMU14K_SE_SMMU1_HASH3_TBL5_CFGr, + SMMU14K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001bc, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_smmu14k_se_smmu1_hash3_tbl5_cfg_reg, + dpp_se_write, + dpp_se_read, + }, + { + "hash3_tbl6_cfg", + SMMU14K_SE_SMMU1_HASH3_TBL6_CFGr, + SMMU14K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001c0, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_smmu14k_se_smmu1_hash3_tbl6_cfg_reg, + dpp_se_write, + dpp_se_read, + }, + { + "hash3_tbl7_cfg", + SMMU14K_SE_SMMU1_HASH3_TBL7_CFGr, + SMMU14K, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001c4, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_smmu14k_se_smmu1_hash3_tbl7_cfg_reg, + dpp_se_write, + dpp_se_read, + }, + { + "cpu_ind_eram_wdat1", + STAT_STAT_CFG_CPU_IND_ERAM_WDAT1r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000004, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_cpu_ind_eram_wdat1_reg, + NULL, + NULL, + }, + { + "cpu_ind_eram_wdat2", + STAT_STAT_CFG_CPU_IND_ERAM_WDAT2r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000008, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_cpu_ind_eram_wdat2_reg, + NULL, + NULL, + }, + { + "cpu_ind_eram_wdat3", + STAT_STAT_CFG_CPU_IND_ERAM_WDAT3r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000000c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_cpu_ind_eram_wdat3_reg, + NULL, + NULL, + }, + { + "cpu_ind_eram_req_info", + STAT_STAT_CFG_CPU_IND_ERAM_REQ_INFOr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000010, + (32/8), + 0, + 0, + 0, + 0, + 5, + g_stat_stat_cfg_cpu_ind_eram_req_info_reg, + NULL, + NULL, + }, + { + "cpu_ind_eram_rd_done", + STAT_STAT_CFG_CPU_IND_ERAM_RD_DONEr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000014, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_cpu_ind_eram_rd_done_reg, + NULL, + NULL, + }, + { + "cpu_ind_eram_rdat0", + STAT_STAT_CFG_CPU_IND_ERAM_RDAT0r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000018, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_cpu_ind_eram_rdat0_reg, + NULL, + NULL, + }, + { + "cpu_ind_eram_rdat1", + STAT_STAT_CFG_CPU_IND_ERAM_RDAT1r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000001c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_cpu_ind_eram_rdat1_reg, + NULL, + NULL, + }, + { + "cpu_ind_eram_rdat2", + STAT_STAT_CFG_CPU_IND_ERAM_RDAT2r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000020, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_cpu_ind_eram_rdat2_reg, + NULL, + NULL, + }, + { + "cpu_ind_eram_rdat3", + STAT_STAT_CFG_CPU_IND_ERAM_RDAT3r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000024, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_cpu_ind_eram_rdat3_reg, + NULL, + NULL, + }, + { + "tm_alu_eram_cpu_rdy", + STAT_STAT_CFG_TM_ALU_ERAM_CPU_RDYr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000028, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_tm_alu_eram_cpu_rdy_reg, + NULL, + NULL, + }, + { + "oam_stat_cfg", + STAT_STAT_CFG_OAM_STAT_CFGr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000040, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_stat_stat_cfg_oam_stat_cfg_reg, + NULL, + NULL, + }, + { + "ftm_port_sel_cfg", + STAT_STAT_CFG_FTM_PORT_SEL_CFGr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000048, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_stat_stat_cfg_ftm_port_sel_cfg_reg, + NULL, + NULL, + }, + { + "oam_eram_base_addr", + STAT_STAT_CFG_OAM_ERAM_BASE_ADDRr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000058, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_oam_eram_base_addr_reg, + NULL, + NULL, + }, + { + "oam_lm_eram_base_addr", + STAT_STAT_CFG_OAM_LM_ERAM_BASE_ADDRr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000005c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_oam_lm_eram_base_addr_reg, + NULL, + NULL, + }, + { + "oam_ddr_base_addr", + STAT_STAT_CFG_OAM_DDR_BASE_ADDRr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000064, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_oam_ddr_base_addr_reg, + NULL, + NULL, + }, + { + "plcr0_schd_pful_cfg", + STAT_STAT_CFG_PLCR0_SCHD_PFUL_CFGr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000078, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_stat_stat_cfg_plcr0_schd_pful_cfg_reg, + NULL, + NULL, + }, + { + "oam_lm_ord_pful_cfg", + STAT_STAT_CFG_OAM_LM_ORD_PFUL_CFGr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000080, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_stat_stat_cfg_oam_lm_ord_pful_cfg_reg, + NULL, + NULL, + }, + { + "ddr_schd_pful_cfg", + STAT_STAT_CFG_DDR_SCHD_PFUL_CFGr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000084, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_stat_stat_cfg_ddr_schd_pful_cfg_reg, + NULL, + NULL, + }, + { + "eram_schd_pful_cfg", + STAT_STAT_CFG_ERAM_SCHD_PFUL_CFGr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000088, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_stat_stat_cfg_eram_schd_pful_cfg_reg, + NULL, + NULL, + }, + { + "eram_schd_pept_cfg", + STAT_STAT_CFG_ERAM_SCHD_PEPT_CFGr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000008c, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_stat_stat_cfg_eram_schd_pept_cfg_reg, + NULL, + NULL, + }, + { + "eram_schd_oam_pful_cfg", + STAT_STAT_CFG_ERAM_SCHD_OAM_PFUL_CFGr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000090, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_stat_stat_cfg_eram_schd_oam_pful_cfg_reg, + NULL, + NULL, + }, + { + "eram_schd_oam_pept_cfg", + STAT_STAT_CFG_ERAM_SCHD_OAM_PEPT_CFGr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000094, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_stat_stat_cfg_eram_schd_oam_pept_cfg_reg, + NULL, + NULL, + }, + { + "eram_schd_oam_lm_pful_cfg", + STAT_STAT_CFG_ERAM_SCHD_OAM_LM_PFUL_CFGr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000098, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_stat_stat_cfg_eram_schd_oam_lm_pful_cfg_reg, + NULL, + NULL, + }, + { + "eram_schd_oam_lm_pept_cfg", + STAT_STAT_CFG_ERAM_SCHD_OAM_LM_PEPT_CFGr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000009c, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_stat_stat_cfg_eram_schd_oam_lm_pept_cfg_reg, + NULL, + NULL, + }, + { + "rschd_pful_cfg", + STAT_STAT_CFG_RSCHD_PFUL_CFGr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000a0, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_stat_stat_cfg_rschd_pful_cfg_reg, + NULL, + NULL, + }, + { + "rschd_pept_cfg", + STAT_STAT_CFG_RSCHD_PEPT_CFGr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000a4, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_stat_stat_cfg_rschd_pept_cfg_reg, + NULL, + NULL, + }, + { + "rschd_plcr_pful_cfg", + STAT_STAT_CFG_RSCHD_PLCR_PFUL_CFGr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000a8, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_stat_stat_cfg_rschd_plcr_pful_cfg_reg, + NULL, + NULL, + }, + { + "rschd_plcr_pept_cfg", + STAT_STAT_CFG_RSCHD_PLCR_PEPT_CFGr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000ac, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_stat_stat_cfg_rschd_plcr_pept_cfg_reg, + NULL, + NULL, + }, + { + "rschd_plcr_info_pful_cfg", + STAT_STAT_CFG_RSCHD_PLCR_INFO_PFUL_CFGr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000b0, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_stat_stat_cfg_rschd_plcr_info_pful_cfg_reg, + NULL, + NULL, + }, + { + "alu_arb_cpu_pful_cfg", + STAT_STAT_CFG_ALU_ARB_CPU_PFUL_CFGr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000b4, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_stat_stat_cfg_alu_arb_cpu_pful_cfg_reg, + NULL, + NULL, + }, + { + "alu_arb_user_pful_cfg", + STAT_STAT_CFG_ALU_ARB_USER_PFUL_CFGr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000b8, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_stat_stat_cfg_alu_arb_user_pful_cfg_reg, + NULL, + NULL, + }, + { + "alu_arb_stat_pful_cfg", + STAT_STAT_CFG_ALU_ARB_STAT_PFUL_CFGr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000bc, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_stat_stat_cfg_alu_arb_stat_pful_cfg_reg, + NULL, + NULL, + }, + { + "cycmov_dat_pful_cfg", + STAT_STAT_CFG_CYCMOV_DAT_PFUL_CFGr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000c0, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_stat_stat_cfg_cycmov_dat_pful_cfg_reg, + NULL, + NULL, + }, + { + "ddr_opr_pful_cfg", + STAT_STAT_CFG_DDR_OPR_PFUL_CFGr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000c4, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_stat_stat_cfg_ddr_opr_pful_cfg_reg, + NULL, + NULL, + }, + { + "cycle_mov_pful_cfg", + STAT_STAT_CFG_CYCLE_MOV_PFUL_CFGr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000c8, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_stat_stat_cfg_cycle_mov_pful_cfg_reg, + NULL, + NULL, + }, + { + "cntovf_pful_cfg", + STAT_STAT_CFG_CNTOVF_PFUL_CFGr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000cc, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_stat_stat_cfg_cntovf_pful_cfg_reg, + NULL, + NULL, + }, + { + "eram_schd_plcr_pful_cfg", + STAT_STAT_CFG_ERAM_SCHD_PLCR_PFUL_CFGr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000d0, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_stat_stat_cfg_eram_schd_plcr_pful_cfg_reg, + NULL, + NULL, + }, + { + "eram_schd_plcr_pept_cfg", + STAT_STAT_CFG_ERAM_SCHD_PLCR_PEPT_CFGr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000d4, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_stat_stat_cfg_eram_schd_plcr_pept_cfg_reg, + NULL, + NULL, + }, + { + "debug_cnt_mode", + STAT_STAT_CFG_DEBUG_CNT_MODEr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000d8, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_stat_stat_cfg_debug_cnt_mode_reg, + NULL, + NULL, + }, + { + "tm_mov_period_cfg", + STAT_STAT_CFG_TM_MOV_PERIOD_CFGr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000dc, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_stat_stat_cfg_tm_mov_period_cfg_reg, + NULL, + NULL, + }, + { + "alu_ddr_cpu_req_pful_cfg", + STAT_STAT_CFG_ALU_DDR_CPU_REQ_PFUL_CFGr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000ec, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_stat_stat_cfg_alu_ddr_cpu_req_pful_cfg_reg, + NULL, + NULL, + }, + { + "cycmov_addr_pful_cfg", + STAT_STAT_CFG_CYCMOV_ADDR_PFUL_CFGr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000f0, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_stat_stat_cfg_cycmov_addr_pful_cfg_reg, + NULL, + NULL, + }, + { + "ord_ddr_plcr_fifo_empty", + STAT_STAT_CFG_ORD_DDR_PLCR_FIFO_EMPTYr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000100, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_stat_stat_cfg_ord_ddr_plcr_fifo_empty_reg, + NULL, + NULL, + }, + { + "tm_stat_fifo_empty", + STAT_STAT_CFG_TM_STAT_FIFO_EMPTYr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000104, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_tm_stat_fifo_empty_reg, + NULL, + NULL, + }, + { + "eram_schd_fifo_empty_0_1", + STAT_STAT_CFG_ERAM_SCHD_FIFO_EMPTY_0_1r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000108, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_stat_stat_cfg_eram_schd_fifo_empty_0_1_reg, + NULL, + NULL, + }, + { + "eram_schd_fifo_empty_2_3", + STAT_STAT_CFG_ERAM_SCHD_FIFO_EMPTY_2_3r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000010c, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_stat_stat_cfg_eram_schd_fifo_empty_2_3_reg, + NULL, + NULL, + }, + { + "eram_schd_fifo_empty_4_5", + STAT_STAT_CFG_ERAM_SCHD_FIFO_EMPTY_4_5r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000110, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_stat_stat_cfg_eram_schd_fifo_empty_4_5_reg, + NULL, + NULL, + }, + { + "eram_schd_fifo_empty_6_7", + STAT_STAT_CFG_ERAM_SCHD_FIFO_EMPTY_6_7r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000114, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_stat_stat_cfg_eram_schd_fifo_empty_6_7_reg, + NULL, + NULL, + }, + { + "eram_schd_fifo_empty_free_8", + STAT_STAT_CFG_ERAM_SCHD_FIFO_EMPTY_FREE_8r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000118, + (32/8), + 0, + 0, + 0, + 0, + 10, + g_stat_stat_cfg_eram_schd_fifo_empty_free_8_reg, + NULL, + NULL, + }, + { + "rschd_fifo_empty_0_3", + STAT_STAT_CFG_RSCHD_FIFO_EMPTY_0_3r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000011c, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_stat_stat_cfg_rschd_fifo_empty_0_3_reg, + NULL, + NULL, + }, + { + "rschd_fifo_empty_4_7", + STAT_STAT_CFG_RSCHD_FIFO_EMPTY_4_7r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000120, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_stat_stat_cfg_rschd_fifo_empty_4_7_reg, + NULL, + NULL, + }, + { + "rschd_fifo_empty_8_11", + STAT_STAT_CFG_RSCHD_FIFO_EMPTY_8_11r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000124, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_stat_stat_cfg_rschd_fifo_empty_8_11_reg, + NULL, + NULL, + }, + { + "rschd_fifo_empty_12_15", + STAT_STAT_CFG_RSCHD_FIFO_EMPTY_12_15r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000128, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_stat_stat_cfg_rschd_fifo_empty_12_15_reg, + NULL, + NULL, + }, + { + "rschd_fifo_empty_plcr_16_17", + STAT_STAT_CFG_RSCHD_FIFO_EMPTY_PLCR_16_17r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000012c, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_stat_stat_cfg_rschd_fifo_empty_plcr_16_17_reg, + NULL, + NULL, + }, + { + "stat_int_unmask_flag", + STAT_STAT_CFG_STAT_INT_UNMASK_FLAGr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000140, + (32/8), + 0, + 0, + 0, + 0, + 6, + g_stat_stat_cfg_stat_int_unmask_flag_reg, + NULL, + NULL, + }, + { + "stat_int0_en", + STAT_STAT_CFG_STAT_INT0_ENr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000144, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_stat_stat_cfg_stat_int0_en_reg, + NULL, + NULL, + }, + { + "stat_int0_mask", + STAT_STAT_CFG_STAT_INT0_MASKr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000148, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_stat_stat_cfg_stat_int0_mask_reg, + NULL, + NULL, + }, + { + "stat_int0_status", + STAT_STAT_CFG_STAT_INT0_STATUSr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000014c, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_stat_stat_cfg_stat_int0_status_reg, + NULL, + NULL, + }, + { + "stat_int1_en", + STAT_STAT_CFG_STAT_INT1_ENr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000150, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_stat_stat_cfg_stat_int1_en_reg, + NULL, + NULL, + }, + { + "stat_int1_mask", + STAT_STAT_CFG_STAT_INT1_MASKr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000154, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_stat_stat_cfg_stat_int1_mask_reg, + NULL, + NULL, + }, + { + "stat_int1_status", + STAT_STAT_CFG_STAT_INT1_STATUSr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000158, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_stat_stat_cfg_stat_int1_status_reg, + NULL, + NULL, + }, + { + "stat_int2_en", + STAT_STAT_CFG_STAT_INT2_ENr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000015c, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_stat_stat_cfg_stat_int2_en_reg, + NULL, + NULL, + }, + { + "stat_int2_mask", + STAT_STAT_CFG_STAT_INT2_MASKr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000160, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_stat_stat_cfg_stat_int2_mask_reg, + NULL, + NULL, + }, + { + "stat_int2_status", + STAT_STAT_CFG_STAT_INT2_STATUSr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000164, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_stat_stat_cfg_stat_int2_status_reg, + NULL, + NULL, + }, + { + "stat_int3_en", + STAT_STAT_CFG_STAT_INT3_ENr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000168, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_stat_stat_cfg_stat_int3_en_reg, + NULL, + NULL, + }, + { + "stat_int3_mask", + STAT_STAT_CFG_STAT_INT3_MASKr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000016c, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_stat_stat_cfg_stat_int3_mask_reg, + NULL, + NULL, + }, + { + "stat_int3_status", + STAT_STAT_CFG_STAT_INT3_STATUSr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000170, + (32/8), + 0, + 0, + 0, + 0, + 32, + g_stat_stat_cfg_stat_int3_status_reg, + NULL, + NULL, + }, + { + "stat_int4_en", + STAT_STAT_CFG_STAT_INT4_ENr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000174, + (32/8), + 0, + 0, + 0, + 0, + 19, + g_stat_stat_cfg_stat_int4_en_reg, + NULL, + NULL, + }, + { + "stat_int4_mask", + STAT_STAT_CFG_STAT_INT4_MASKr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000178, + (32/8), + 0, + 0, + 0, + 0, + 19, + g_stat_stat_cfg_stat_int4_mask_reg, + NULL, + NULL, + }, + { + "stat_int4_status", + STAT_STAT_CFG_STAT_INT4_STATUSr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000017c, + (32/8), + 0, + 0, + 0, + 0, + 19, + g_stat_stat_cfg_stat_int4_status_reg, + NULL, + NULL, + }, + { + "stat_int5_en", + STAT_STAT_CFG_STAT_INT5_ENr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000180, + (32/8), + 0, + 0, + 0, + 0, + 19, + g_stat_stat_cfg_stat_int5_en_reg, + NULL, + NULL, + }, + { + "stat_int5_mask", + STAT_STAT_CFG_STAT_INT5_MASKr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000184, + (32/8), + 0, + 0, + 0, + 0, + 19, + g_stat_stat_cfg_stat_int5_mask_reg, + NULL, + NULL, + }, + { + "stat_int5_status", + STAT_STAT_CFG_STAT_INT5_STATUSr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000188, + (32/8), + 0, + 0, + 0, + 0, + 19, + g_stat_stat_cfg_stat_int5_status_reg, + NULL, + NULL, + }, + { + "rschd_ecc_bypass", + STAT_STAT_CFG_RSCHD_ECC_BYPASSr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000198, + (32/8), + 0, + 0, + 0, + 0, + 19, + g_stat_stat_cfg_rschd_ecc_bypass_reg, + NULL, + NULL, + }, + { + "rschd_ecc_single_err", + STAT_STAT_CFG_RSCHD_ECC_SINGLE_ERRr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000019c, + (32/8), + 0, + 0, + 0, + 0, + 19, + g_stat_stat_cfg_rschd_ecc_single_err_reg, + NULL, + NULL, + }, + { + "rschd_ecc_double_err", + STAT_STAT_CFG_RSCHD_ECC_DOUBLE_ERRr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000001a0, + (32/8), + 0, + 0, + 0, + 0, + 19, + g_stat_stat_cfg_rschd_ecc_double_err_reg, + NULL, + NULL, + }, + { + "cpu_ind_ddr_wdat0", + STAT_STAT_CFG_CPU_IND_DDR_WDAT0r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000200, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_cpu_ind_ddr_wdat0_reg, + NULL, + NULL, + }, + { + "cpu_ind_ddr_wdat1", + STAT_STAT_CFG_CPU_IND_DDR_WDAT1r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000204, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_cpu_ind_ddr_wdat1_reg, + NULL, + NULL, + }, + { + "cpu_ind_ddr_wdat2", + STAT_STAT_CFG_CPU_IND_DDR_WDAT2r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000208, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_cpu_ind_ddr_wdat2_reg, + NULL, + NULL, + }, + { + "cpu_ind_ddr_wdat3", + STAT_STAT_CFG_CPU_IND_DDR_WDAT3r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000020c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_cpu_ind_ddr_wdat3_reg, + NULL, + NULL, + }, + { + "cpu_ind_ddr_wdat4", + STAT_STAT_CFG_CPU_IND_DDR_WDAT4r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000210, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_cpu_ind_ddr_wdat4_reg, + NULL, + NULL, + }, + { + "cpu_ind_ddr_wdat5", + STAT_STAT_CFG_CPU_IND_DDR_WDAT5r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000214, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_cpu_ind_ddr_wdat5_reg, + NULL, + NULL, + }, + { + "cpu_ind_ddr_wdat6", + STAT_STAT_CFG_CPU_IND_DDR_WDAT6r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000218, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_cpu_ind_ddr_wdat6_reg, + NULL, + NULL, + }, + { + "cpu_ind_ddr_wdat7", + STAT_STAT_CFG_CPU_IND_DDR_WDAT7r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000021c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_cpu_ind_ddr_wdat7_reg, + NULL, + NULL, + }, + { + "cpu_ind_ddr_wdat8", + STAT_STAT_CFG_CPU_IND_DDR_WDAT8r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000220, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_cpu_ind_ddr_wdat8_reg, + NULL, + NULL, + }, + { + "cpu_ind_ddr_wdat9", + STAT_STAT_CFG_CPU_IND_DDR_WDAT9r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000224, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_cpu_ind_ddr_wdat9_reg, + NULL, + NULL, + }, + { + "cpu_ind_ddr_wdat10", + STAT_STAT_CFG_CPU_IND_DDR_WDAT10r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000228, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_cpu_ind_ddr_wdat10_reg, + NULL, + NULL, + }, + { + "cpu_ind_ddr_wdat11", + STAT_STAT_CFG_CPU_IND_DDR_WDAT11r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000022c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_cpu_ind_ddr_wdat11_reg, + NULL, + NULL, + }, + { + "cpu_ind_ddr_wdat12", + STAT_STAT_CFG_CPU_IND_DDR_WDAT12r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000230, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_cpu_ind_ddr_wdat12_reg, + NULL, + NULL, + }, + { + "cpu_ind_ddr_wdat13", + STAT_STAT_CFG_CPU_IND_DDR_WDAT13r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000234, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_cpu_ind_ddr_wdat13_reg, + NULL, + NULL, + }, + { + "cpu_ind_ddr_wdat14", + STAT_STAT_CFG_CPU_IND_DDR_WDAT14r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000238, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_cpu_ind_ddr_wdat14_reg, + NULL, + NULL, + }, + { + "cpu_ind_ddr_wdat15", + STAT_STAT_CFG_CPU_IND_DDR_WDAT15r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000023c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_cpu_ind_ddr_wdat15_reg, + NULL, + NULL, + }, + { + "cpu_ind_ddr_req_info", + STAT_STAT_CFG_CPU_IND_DDR_REQ_INFOr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000240, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_stat_stat_cfg_cpu_ind_ddr_req_info_reg, + NULL, + NULL, + }, + { + "cpu_ind_ddr_rd_done", + STAT_STAT_CFG_CPU_IND_DDR_RD_DONEr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000244, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_cpu_ind_ddr_rd_done_reg, + NULL, + NULL, + }, + { + "cpu_ind_ddr_rdat0", + STAT_STAT_CFG_CPU_IND_DDR_RDAT0r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000248, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_cpu_ind_ddr_rdat0_reg, + NULL, + NULL, + }, + { + "cpu_ind_ddr_rdat1", + STAT_STAT_CFG_CPU_IND_DDR_RDAT1r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000024c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_cpu_ind_ddr_rdat1_reg, + NULL, + NULL, + }, + { + "cpu_ind_ddr_rdat2", + STAT_STAT_CFG_CPU_IND_DDR_RDAT2r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000250, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_cpu_ind_ddr_rdat2_reg, + NULL, + NULL, + }, + { + "cpu_ind_ddr_rdat3", + STAT_STAT_CFG_CPU_IND_DDR_RDAT3r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000254, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_cpu_ind_ddr_rdat3_reg, + NULL, + NULL, + }, + { + "cpu_ind_ddr_rdat4", + STAT_STAT_CFG_CPU_IND_DDR_RDAT4r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000258, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_cpu_ind_ddr_rdat4_reg, + NULL, + NULL, + }, + { + "cpu_ind_ddr_rdat5", + STAT_STAT_CFG_CPU_IND_DDR_RDAT5r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000025c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_cpu_ind_ddr_rdat5_reg, + NULL, + NULL, + }, + { + "cpu_ind_ddr_rdat6", + STAT_STAT_CFG_CPU_IND_DDR_RDAT6r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000260, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_cpu_ind_ddr_rdat6_reg, + NULL, + NULL, + }, + { + "cpu_ind_ddr_rdat7", + STAT_STAT_CFG_CPU_IND_DDR_RDAT7r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000264, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_cpu_ind_ddr_rdat7_reg, + NULL, + NULL, + }, + { + "cpu_ind_ddr_rdat8", + STAT_STAT_CFG_CPU_IND_DDR_RDAT8r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000268, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_cpu_ind_ddr_rdat8_reg, + NULL, + NULL, + }, + { + "cpu_ind_ddr_rdat9", + STAT_STAT_CFG_CPU_IND_DDR_RDAT9r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000026c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_cpu_ind_ddr_rdat9_reg, + NULL, + NULL, + }, + { + "cpu_ind_ddr_rdat10", + STAT_STAT_CFG_CPU_IND_DDR_RDAT10r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000270, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_cpu_ind_ddr_rdat10_reg, + NULL, + NULL, + }, + { + "cpu_ind_ddr_rdat11", + STAT_STAT_CFG_CPU_IND_DDR_RDAT11r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000274, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_cpu_ind_ddr_rdat11_reg, + NULL, + NULL, + }, + { + "cpu_ind_ddr_rdat12", + STAT_STAT_CFG_CPU_IND_DDR_RDAT12r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000278, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_cpu_ind_ddr_rdat12_reg, + NULL, + NULL, + }, + { + "cpu_ind_ddr_rdat13", + STAT_STAT_CFG_CPU_IND_DDR_RDAT13r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000027c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_cpu_ind_ddr_rdat13_reg, + NULL, + NULL, + }, + { + "cpu_ind_ddr_rdat14", + STAT_STAT_CFG_CPU_IND_DDR_RDAT14r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000280, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_cpu_ind_ddr_rdat14_reg, + NULL, + NULL, + }, + { + "cpu_ind_ddr_rdat15", + STAT_STAT_CFG_CPU_IND_DDR_RDAT15r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000284, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_cpu_ind_ddr_rdat15_reg, + NULL, + NULL, + }, + { + "tm_alu_ddr_cpu_rdy", + STAT_STAT_CFG_TM_ALU_DDR_CPU_RDYr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000288, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_tm_alu_ddr_cpu_rdy_reg, + NULL, + NULL, + }, + { + "ept_flag", + STAT_STAT_CFG_EPT_FLAGr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000003f8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_ept_flag_reg, + NULL, + NULL, + }, + { + "ppu_soft_rst", + STAT_STAT_CFG_PPU_SOFT_RSTr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000003fc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_ppu_soft_rst_reg, + NULL, + NULL, + }, + { + "stat_smmu0_fc15_0_cnt", + STAT_STAT_CFG_STAT_SMMU0_FC15_0_CNTr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000400, + (32/8), + 0, + 15 + 1, + 0, + 4, + 1, + g_stat_stat_cfg_stat_smmu0_fc15_0_cnt_reg, + NULL, + NULL, + }, + { + "smmu0_stat_fc15_0_cnt", + STAT_STAT_CFG_SMMU0_STAT_FC15_0_CNTr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000440, + (32/8), + 0, + 15 + 1, + 0, + 4, + 1, + g_stat_stat_cfg_smmu0_stat_fc15_0_cnt_reg, + NULL, + NULL, + }, + { + "smmu0_stat_rsp15_0_cnt", + STAT_STAT_CFG_SMMU0_STAT_RSP15_0_CNTr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000480, + (32/8), + 0, + 15 + 1, + 0, + 4, + 1, + g_stat_stat_cfg_smmu0_stat_rsp15_0_cnt_reg, + NULL, + NULL, + }, + { + "stat_smmu0_req15_0_cnt", + STAT_STAT_CFG_STAT_SMMU0_REQ15_0_CNTr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000004c0, + (32/8), + 0, + 15 + 1, + 0, + 4, + 1, + g_stat_stat_cfg_stat_smmu0_req15_0_cnt_reg, + NULL, + NULL, + }, + { + "ppu_stat_mec5_0_rsp_fc_cnt", + STAT_STAT_CFG_PPU_STAT_MEC5_0_RSP_FC_CNTr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000500, + (32/8), + 0, + 5 + 1, + 0, + 4, + 1, + g_stat_stat_cfg_ppu_stat_mec5_0_rsp_fc_cnt_reg, + NULL, + NULL, + }, + { + "stat_ppu_mec5_0_key_fc_cnt", + STAT_STAT_CFG_STAT_PPU_MEC5_0_KEY_FC_CNTr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000518, + (32/8), + 0, + 5 + 1, + 0, + 4, + 1, + g_stat_stat_cfg_stat_ppu_mec5_0_key_fc_cnt_reg, + NULL, + NULL, + }, + { + "stat_ppu_mec5_0_rsp_cnt", + STAT_STAT_CFG_STAT_PPU_MEC5_0_RSP_CNTr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000530, + (32/8), + 0, + 5 + 1, + 0, + 4, + 1, + g_stat_stat_cfg_stat_ppu_mec5_0_rsp_cnt_reg, + NULL, + NULL, + }, + { + "ppu_stat_mec5_0_key_cnt", + STAT_STAT_CFG_PPU_STAT_MEC5_0_KEY_CNTr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000548, + (32/8), + 0, + 5 + 1, + 0, + 4, + 1, + g_stat_stat_cfg_ppu_stat_mec5_0_key_cnt_reg, + NULL, + NULL, + }, + { + "ppu5_0_no_exist_opcd_ex_cnt", + STAT_STAT_CFG_PPU5_0_NO_EXIST_OPCD_EX_CNTr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000560, + (32/8), + 0, + 5 + 1, + 0, + 4, + 1, + g_stat_stat_cfg_ppu5_0_no_exist_opcd_ex_cnt_reg, + NULL, + NULL, + }, + { + "se_etm_stat_wr_fc_cnt", + STAT_STAT_CFG_SE_ETM_STAT_WR_FC_CNTr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000578, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_se_etm_stat_wr_fc_cnt_reg, + NULL, + NULL, + }, + { + "se_etm_stat_rd_fc_cnt", + STAT_STAT_CFG_SE_ETM_STAT_RD_FC_CNTr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000057c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_se_etm_stat_rd_fc_cnt_reg, + NULL, + NULL, + }, + { + "stat_etm_deq_fc_cnt", + STAT_STAT_CFG_STAT_ETM_DEQ_FC_CNTr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000580, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_stat_etm_deq_fc_cnt_reg, + NULL, + NULL, + }, + { + "stat_etm_enq_fc_cnt", + STAT_STAT_CFG_STAT_ETM_ENQ_FC_CNTr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000584, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_stat_etm_enq_fc_cnt_reg, + NULL, + NULL, + }, + { + "stat_oam_lm_fc_cnt", + STAT_STAT_CFG_STAT_OAM_LM_FC_CNTr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000588, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_stat_oam_lm_fc_cnt_reg, + NULL, + NULL, + }, + { + "oam_stat_lm_fc_cnt", + STAT_STAT_CFG_OAM_STAT_LM_FC_CNTr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000058c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_oam_stat_lm_fc_cnt_reg, + NULL, + NULL, + }, + { + "stat_oam_fc_cnt", + STAT_STAT_CFG_STAT_OAM_FC_CNTr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000590, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_stat_oam_fc_cnt_reg, + NULL, + NULL, + }, + { + "cmmu_stat_fc_cnt", + STAT_STAT_CFG_CMMU_STAT_FC_CNTr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000594, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_cmmu_stat_fc_cnt_reg, + NULL, + NULL, + }, + { + "stat_cmmu_req_cnt", + STAT_STAT_CFG_STAT_CMMU_REQ_CNTr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000598, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_stat_cmmu_req_cnt_reg, + NULL, + NULL, + }, + { + "smmu0_plcr_rsp0_cnt", + STAT_STAT_CFG_SMMU0_PLCR_RSP0_CNTr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000059c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_smmu0_plcr_rsp0_cnt_reg, + NULL, + NULL, + }, + { + "plcr_smmu0_req0_cnt", + STAT_STAT_CFG_PLCR_SMMU0_REQ0_CNTr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000005a0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_plcr_smmu0_req0_cnt_reg, + NULL, + NULL, + }, + { + "stat_oam_lm_rsp_cnt", + STAT_STAT_CFG_STAT_OAM_LM_RSP_CNTr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000005a4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_stat_oam_lm_rsp_cnt_reg, + NULL, + NULL, + }, + { + "oam_stat_lm_req_cnt", + STAT_STAT_CFG_OAM_STAT_LM_REQ_CNTr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000005a8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_oam_stat_lm_req_cnt_reg, + NULL, + NULL, + }, + { + "oam_stat_req_cnt", + STAT_STAT_CFG_OAM_STAT_REQ_CNTr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000005ac, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_oam_stat_req_cnt_reg, + NULL, + NULL, + }, + { + "se_etm_stat_rsp_cnt", + STAT_STAT_CFG_SE_ETM_STAT_RSP_CNTr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000005b0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_se_etm_stat_rsp_cnt_reg, + NULL, + NULL, + }, + { + "etm_stat_se_wr_req_cnt", + STAT_STAT_CFG_ETM_STAT_SE_WR_REQ_CNTr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000005b4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_etm_stat_se_wr_req_cnt_reg, + NULL, + NULL, + }, + { + "etm_stat_se_rd_req_cnt", + STAT_STAT_CFG_ETM_STAT_SE_RD_REQ_CNTr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000005b8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_etm_stat_se_rd_req_cnt_reg, + NULL, + NULL, + }, + { + "etm_stat_smmu0_req_cnt0", + STAT_STAT_CFG_ETM_STAT_SMMU0_REQ_CNT0r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000005bc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_etm_stat_smmu0_req_cnt0_reg, + NULL, + NULL, + }, + { + "etm_stat_smmu0_req_cnt1", + STAT_STAT_CFG_ETM_STAT_SMMU0_REQ_CNT1r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000005c0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_etm_stat_smmu0_req_cnt1_reg, + NULL, + NULL, + }, + { + "tm_stat_eram_cpu_rsp_cnt", + STAT_STAT_CFG_TM_STAT_ERAM_CPU_RSP_CNTr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000005c4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_tm_stat_eram_cpu_rsp_cnt_reg, + NULL, + NULL, + }, + { + "cpu_rd_eram_req_cnt", + STAT_STAT_CFG_CPU_RD_ERAM_REQ_CNTr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000005c8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_cpu_rd_eram_req_cnt_reg, + NULL, + NULL, + }, + { + "cpu_wr_eram_req_cnt", + STAT_STAT_CFG_CPU_WR_ERAM_REQ_CNTr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000005cc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_cpu_wr_eram_req_cnt_reg, + NULL, + NULL, + }, + { + "tm_stat_ddr_cpu_rsp_cnt", + STAT_STAT_CFG_TM_STAT_DDR_CPU_RSP_CNTr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000005d0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_tm_stat_ddr_cpu_rsp_cnt_reg, + NULL, + NULL, + }, + { + "cpu_rd_ddr_req_cnt", + STAT_STAT_CFG_CPU_RD_DDR_REQ_CNTr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000005d4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_cpu_rd_ddr_req_cnt_reg, + NULL, + NULL, + }, + { + "cpu_wr_ddr_req_cnt", + STAT_STAT_CFG_CPU_WR_DDR_REQ_CNTr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000005d8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_stat_cfg_cpu_wr_ddr_req_cnt_reg, + NULL, + NULL, + }, + { + "cpu_ind_wdat1", + STAT_ETCAM_CPU_IND_WDAT1r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000008, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_etcam_cpu_ind_wdat1_reg, + NULL, + NULL, + }, + { + "cpu_ind_wdat2", + STAT_ETCAM_CPU_IND_WDAT2r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x0000000c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_etcam_cpu_ind_wdat2_reg, + NULL, + NULL, + }, + { + "cpu_ind_wdat3", + STAT_ETCAM_CPU_IND_WDAT3r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000010, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_etcam_cpu_ind_wdat3_reg, + NULL, + NULL, + }, + { + "cpu_ind_wdat4", + STAT_ETCAM_CPU_IND_WDAT4r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000014, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_etcam_cpu_ind_wdat4_reg, + NULL, + NULL, + }, + { + "cpu_ind_wdat5", + STAT_ETCAM_CPU_IND_WDAT5r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000018, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_etcam_cpu_ind_wdat5_reg, + NULL, + NULL, + }, + { + "cpu_ind_wdat6", + STAT_ETCAM_CPU_IND_WDAT6r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x0000001c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_etcam_cpu_ind_wdat6_reg, + NULL, + NULL, + }, + { + "cpu_ind_wdat7", + STAT_ETCAM_CPU_IND_WDAT7r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000020, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_etcam_cpu_ind_wdat7_reg, + NULL, + NULL, + }, + { + "cpu_ind_wdat8", + STAT_ETCAM_CPU_IND_WDAT8r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000024, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_etcam_cpu_ind_wdat8_reg, + NULL, + NULL, + }, + { + "cpu_ind_wdat9", + STAT_ETCAM_CPU_IND_WDAT9r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000028, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_etcam_cpu_ind_wdat9_reg, + NULL, + NULL, + }, + { + "cpu_ind_wdat10", + STAT_ETCAM_CPU_IND_WDAT10r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x0000002c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_etcam_cpu_ind_wdat10_reg, + NULL, + NULL, + }, + { + "cpu_ind_wdat11", + STAT_ETCAM_CPU_IND_WDAT11r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000030, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_etcam_cpu_ind_wdat11_reg, + NULL, + NULL, + }, + { + "cpu_ind_wdat12", + STAT_ETCAM_CPU_IND_WDAT12r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000034, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_etcam_cpu_ind_wdat12_reg, + NULL, + NULL, + }, + { + "cpu_ind_wdat13", + STAT_ETCAM_CPU_IND_WDAT13r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000038, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_etcam_cpu_ind_wdat13_reg, + NULL, + NULL, + }, + { + "cpu_ind_wdat14", + STAT_ETCAM_CPU_IND_WDAT14r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x0000003c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_etcam_cpu_ind_wdat14_reg, + NULL, + NULL, + }, + { + "cpu_ind_wdat15", + STAT_ETCAM_CPU_IND_WDAT15r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000040, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_etcam_cpu_ind_wdat15_reg, + NULL, + NULL, + }, + { + "cpu_ind_wdat16", + STAT_ETCAM_CPU_IND_WDAT16r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000044, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_etcam_cpu_ind_wdat16_reg, + NULL, + NULL, + }, + { + "cpu_ind_wdat17", + STAT_ETCAM_CPU_IND_WDAT17r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000048, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_etcam_cpu_ind_wdat17_reg, + NULL, + NULL, + }, + { + "cpu_ind_wdat18", + STAT_ETCAM_CPU_IND_WDAT18r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x0000004c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_etcam_cpu_ind_wdat18_reg, + NULL, + NULL, + }, + { + "cpu_ind_wdat19", + STAT_ETCAM_CPU_IND_WDAT19r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000050, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_etcam_cpu_ind_wdat19_reg, + NULL, + NULL, + }, + { + "t_strwc_cfg", + STAT_ETCAM_T_STRWC_CFGr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000074, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_etcam_t_strwc_cfg_reg, + NULL, + NULL, + }, + { + "etcam_int_unmask_flag", + STAT_ETCAM_ETCAM_INT_UNMASK_FLAGr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000080, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_etcam_etcam_int_unmask_flag_reg, + NULL, + NULL, + }, + { + "etcam_int_en0", + STAT_ETCAM_ETCAM_INT_EN0r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000084, + (32/8), + 0, + 0, + 0, + 0, + 18, + g_stat_etcam_etcam_int_en0_reg, + NULL, + NULL, + }, + { + "etcam_int_mask0", + STAT_ETCAM_ETCAM_INT_MASK0r, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x0000008c, + (32/8), + 0, + 0, + 0, + 0, + 18, + g_stat_etcam_etcam_int_mask0_reg, + NULL, + NULL, + }, + { + "etcam_int_status", + STAT_ETCAM_ETCAM_INT_STATUSr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000094, + (32/8), + 0, + 0, + 0, + 0, + 18, + g_stat_etcam_etcam_int_status_reg, + NULL, + NULL, + }, + { + "int_tb_ini_ok", + STAT_ETCAM_INT_TB_INI_OKr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x000003f8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_etcam_int_tb_ini_ok_reg, + NULL, + NULL, + }, + { + "etcam_clk_en", + STAT_ETCAM_ETCAM_CLK_ENr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x000003fc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_etcam_etcam_clk_en_reg, + NULL, + NULL, + }, + { + "as_etcam_req0_cnt", + STAT_ETCAM_AS_ETCAM_REQ0_CNTr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000400, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_etcam_as_etcam_req0_cnt_reg, + NULL, + NULL, + }, + { + "as_etcam_req1_cnt", + STAT_ETCAM_AS_ETCAM_REQ1_CNTr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000404, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_etcam_as_etcam_req1_cnt_reg, + NULL, + NULL, + }, + { + "etcam_as_index0_cnt", + STAT_ETCAM_ETCAM_AS_INDEX0_CNTr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000408, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_etcam_etcam_as_index0_cnt_reg, + NULL, + NULL, + }, + { + "etcam_as_index1_cnt", + STAT_ETCAM_ETCAM_AS_INDEX1_CNTr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x0000040c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_etcam_etcam_as_index1_cnt_reg, + NULL, + NULL, + }, + { + "etcam_not_hit0_cnt", + STAT_ETCAM_ETCAM_NOT_HIT0_CNTr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000410, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_etcam_etcam_not_hit0_cnt_reg, + NULL, + NULL, + }, + { + "etcam_not_hit1_cnt", + STAT_ETCAM_ETCAM_NOT_HIT1_CNTr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000414, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_etcam_etcam_not_hit1_cnt_reg, + NULL, + NULL, + }, + { + "table_id_not_match_cnt", + STAT_ETCAM_TABLE_ID_NOT_MATCH_CNTr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000418, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_etcam_table_id_not_match_cnt_reg, + NULL, + NULL, + }, + { + "table_id_clash01_cnt", + STAT_ETCAM_TABLE_ID_CLASH01_CNTr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x0000041c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_etcam_table_id_clash01_cnt_reg, + NULL, + NULL, + }, + { + "etcam_cpu_fl", + STAT_ETCAM_ETCAM_CPU_FLr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x0000044c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_etcam_etcam_cpu_fl_reg, + NULL, + NULL, + }, + { + "etcam_arb_empty", + STAT_ETCAM_ETCAM_ARB_EMPTYr, + STAT, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000450, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_stat_etcam_etcam_arb_empty_reg, + NULL, + NULL, + }, + { + "cfg_finish_int_event0", + DTB_DTB_CFG_CFG_FINISH_INT_EVENT0r, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0000, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_cfg_finish_int_event0_reg, + NULL, + NULL, + }, + { + "cfg_finish_int_event1", + DTB_DTB_CFG_CFG_FINISH_INT_EVENT1r, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0004, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_cfg_finish_int_event1_reg, + NULL, + NULL, + }, + { + "cfg_finish_int_event2", + DTB_DTB_CFG_CFG_FINISH_INT_EVENT2r, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0008, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_cfg_finish_int_event2_reg, + NULL, + NULL, + }, + { + "cfg_finish_int_event3", + DTB_DTB_CFG_CFG_FINISH_INT_EVENT3r, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x000c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_cfg_finish_int_event3_reg, + NULL, + NULL, + }, + { + "cfg_finish_int_maks0", + DTB_DTB_CFG_CFG_FINISH_INT_MAKS0r, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0010, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_cfg_finish_int_maks0_reg, + NULL, + NULL, + }, + { + "cfg_finish_int_maks1", + DTB_DTB_CFG_CFG_FINISH_INT_MAKS1r, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0014, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_cfg_finish_int_maks1_reg, + NULL, + NULL, + }, + { + "cfg_finish_int_maks2", + DTB_DTB_CFG_CFG_FINISH_INT_MAKS2r, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0018, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_cfg_finish_int_maks2_reg, + NULL, + NULL, + }, + { + "cfg_finish_int_maks3", + DTB_DTB_CFG_CFG_FINISH_INT_MAKS3r, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x001c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_cfg_finish_int_maks3_reg, + NULL, + NULL, + }, + { + "cfg_finish_int_test0", + DTB_DTB_CFG_CFG_FINISH_INT_TEST0r, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0020, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_cfg_finish_int_test0_reg, + NULL, + NULL, + }, + { + "cfg_finish_int_test1", + DTB_DTB_CFG_CFG_FINISH_INT_TEST1r, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0024, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_cfg_finish_int_test1_reg, + NULL, + NULL, + }, + { + "cfg_finish_int_test2", + DTB_DTB_CFG_CFG_FINISH_INT_TEST2r, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0028, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_cfg_finish_int_test2_reg, + NULL, + NULL, + }, + { + "cfg_finish_int_test3", + DTB_DTB_CFG_CFG_FINISH_INT_TEST3r, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x002c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_cfg_finish_int_test3_reg, + NULL, + NULL, + }, + { + "cfg_dtb_int_to_riscv_sel", + DTB_DTB_CFG_CFG_DTB_INT_TO_RISCV_SELr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0090, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_cfg_dtb_int_to_riscv_sel_reg, + NULL, + NULL, + }, + { + "cfg_dtb_ep_int_msix_enable", + DTB_DTB_CFG_CFG_DTB_EP_INT_MSIX_ENABLEr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0094, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_cfg_dtb_ep_int_msix_enable_reg, + NULL, + NULL, + }, + { + "cfg_dtb_ep_doorbell_addr_h_0_15", + DTB_DTB_CFG_CFG_DTB_EP_DOORBELL_ADDR_H_0_15r, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0100, + (32/8), + 0, + 15 + 1, + 0, + 4, + 1, + g_dtb_dtb_cfg_cfg_dtb_ep_doorbell_addr_h_0_15_reg, + NULL, + NULL, + }, + { + "cfg_dtb_ep_doorbell_addr_l_0_15", + DTB_DTB_CFG_CFG_DTB_EP_DOORBELL_ADDR_L_0_15r, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0140, + (32/8), + 0, + 15 + 1, + 0, + 4, + 1, + g_dtb_dtb_cfg_cfg_dtb_ep_doorbell_addr_l_0_15_reg, + NULL, + NULL, + }, + { + "cfg_dtb_debug_mode_en", + DTB_DTB_CFG_CFG_DTB_DEBUG_MODE_ENr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0180, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_cfg_dtb_debug_mode_en_reg, + NULL, + NULL, + }, + { + "info_axi_last_rd_table_addr_high", + DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_ADDR_HIGHr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0184, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_info_axi_last_rd_table_addr_high_reg, + NULL, + NULL, + }, + { + "info_axi_last_rd_table_addr_low", + DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_ADDR_LOWr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0188, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_info_axi_last_rd_table_addr_low_reg, + NULL, + NULL, + }, + { + "info_axi_last_rd_table_len", + DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_LENr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x018c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_info_axi_last_rd_table_len_reg, + NULL, + NULL, + }, + { + "info_axi_last_rd_table_user", + DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_USERr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0190, + (32/8), + 0, + 0, + 0, + 0, + 5, + g_dtb_dtb_cfg_info_axi_last_rd_table_user_reg, + NULL, + NULL, + }, + { + "info_axi_last_rd_table_onload_cnt", + DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_ONLOAD_CNTr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0194, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_info_axi_last_rd_table_onload_cnt_reg, + NULL, + NULL, + }, + { + "cnt_axi_rd_table_resp_err", + DTB_DTB_CFG_CNT_AXI_RD_TABLE_RESP_ERRr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0198, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_cnt_axi_rd_table_resp_err_reg, + NULL, + NULL, + }, + { + "info_axi_last_rd_pd_addr_high", + DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_ADDR_HIGHr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01a0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_info_axi_last_rd_pd_addr_high_reg, + NULL, + NULL, + }, + { + "info_axi_last_rd_pd_addr_low", + DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_ADDR_LOWr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01a4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_info_axi_last_rd_pd_addr_low_reg, + NULL, + NULL, + }, + { + "info_axi_last_rd_pd_len", + DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_LENr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01a8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_info_axi_last_rd_pd_len_reg, + NULL, + NULL, + }, + { + "info_axi_last_rd_pd_user", + DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_USERr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01ac, + (32/8), + 0, + 0, + 0, + 0, + 5, + g_dtb_dtb_cfg_info_axi_last_rd_pd_user_reg, + NULL, + NULL, + }, + { + "info_axi_last_rd_pd_onload_cnt", + DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_ONLOAD_CNTr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01b0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_info_axi_last_rd_pd_onload_cnt_reg, + NULL, + NULL, + }, + { + "cnt_axi_rd_pd_resp_err", + DTB_DTB_CFG_CNT_AXI_RD_PD_RESP_ERRr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01b4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_cnt_axi_rd_pd_resp_err_reg, + NULL, + NULL, + }, + { + "info_axi_last_wr_ctrl_addr_high", + DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_ADDR_HIGHr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01b8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_info_axi_last_wr_ctrl_addr_high_reg, + NULL, + NULL, + }, + { + "info_axi_last_wr_ctrl_addr_low", + DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_ADDR_LOWr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01bc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_info_axi_last_wr_ctrl_addr_low_reg, + NULL, + NULL, + }, + { + "info_axi_last_wr_ctrl_len", + DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_LENr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01c0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_info_axi_last_wr_ctrl_len_reg, + NULL, + NULL, + }, + { + "info_axi_last_wr_ctrl_user", + DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_USERr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01c4, + (32/8), + 0, + 0, + 0, + 0, + 5, + g_dtb_dtb_cfg_info_axi_last_wr_ctrl_user_reg, + NULL, + NULL, + }, + { + "info_axi_last_wr_ctrl_onload_cnt", + DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_ONLOAD_CNTr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01c8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_info_axi_last_wr_ctrl_onload_cnt_reg, + NULL, + NULL, + }, + { + "cnt_axi_wr_ctrl_resp_err", + DTB_DTB_CFG_CNT_AXI_WR_CTRL_RESP_ERRr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01cc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_cnt_axi_wr_ctrl_resp_err_reg, + NULL, + NULL, + }, + { + "info_axi_last_wr_ddr_addr_high", + DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_ADDR_HIGHr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01d0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_info_axi_last_wr_ddr_addr_high_reg, + NULL, + NULL, + }, + { + "info_axi_last_wr_ddr_addr_low", + DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_ADDR_LOWr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01d4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_info_axi_last_wr_ddr_addr_low_reg, + NULL, + NULL, + }, + { + "info_axi_last_wr_ddr_len", + DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_LENr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01d8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_info_axi_last_wr_ddr_len_reg, + NULL, + NULL, + }, + { + "info_axi_last_wr_ddr_user", + DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_USERr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01dc, + (32/8), + 0, + 0, + 0, + 0, + 5, + g_dtb_dtb_cfg_info_axi_last_wr_ddr_user_reg, + NULL, + NULL, + }, + { + "info_axi_last_wr_ddr_onload_cnt", + DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_ONLOAD_CNTr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01e0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_info_axi_last_wr_ddr_onload_cnt_reg, + NULL, + NULL, + }, + { + "cnt_axi_wr_ddr_resp_err", + DTB_DTB_CFG_CNT_AXI_WR_DDR_RESP_ERRr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01e4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_cnt_axi_wr_ddr_resp_err_reg, + NULL, + NULL, + }, + { + "info_axi_last_wr_fin_addr_high", + DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_ADDR_HIGHr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01e8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_info_axi_last_wr_fin_addr_high_reg, + NULL, + NULL, + }, + { + "info_axi_last_wr_fin_addr_low", + DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_ADDR_LOWr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01ec, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_info_axi_last_wr_fin_addr_low_reg, + NULL, + NULL, + }, + { + "info_axi_last_wr_fin_len", + DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_LENr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01f0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_info_axi_last_wr_fin_len_reg, + NULL, + NULL, + }, + { + "info_axi_last_wr_fin_user", + DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_USERr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01f4, + (32/8), + 0, + 0, + 0, + 0, + 5, + g_dtb_dtb_cfg_info_axi_last_wr_fin_user_reg, + NULL, + NULL, + }, + { + "info_axi_last_wr_fin_onload_cnt", + DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_ONLOAD_CNTr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01f8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_info_axi_last_wr_fin_onload_cnt_reg, + NULL, + NULL, + }, + { + "cnt_axi_wr_fin_resp_err", + DTB_DTB_CFG_CNT_AXI_WR_FIN_RESP_ERRr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01fc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_cnt_axi_wr_fin_resp_err_reg, + NULL, + NULL, + }, + { + "cnt_dtb_wr_smmu0_table_high", + DTB_DTB_CFG_CNT_DTB_WR_SMMU0_TABLE_HIGHr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0200, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_cnt_dtb_wr_smmu0_table_high_reg, + NULL, + NULL, + }, + { + "cnt_dtb_wr_smmu0_table_low", + DTB_DTB_CFG_CNT_DTB_WR_SMMU0_TABLE_LOWr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0204, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_cnt_dtb_wr_smmu0_table_low_reg, + NULL, + NULL, + }, + { + "cnt_dtb_wr_smmu1_table_high", + DTB_DTB_CFG_CNT_DTB_WR_SMMU1_TABLE_HIGHr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0208, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_cnt_dtb_wr_smmu1_table_high_reg, + NULL, + NULL, + }, + { + "cnt_dtb_wr_smmu1_table_low", + DTB_DTB_CFG_CNT_DTB_WR_SMMU1_TABLE_LOWr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x020c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_cnt_dtb_wr_smmu1_table_low_reg, + NULL, + NULL, + }, + { + "cnt_dtb_wr_zcam_table_high", + DTB_DTB_CFG_CNT_DTB_WR_ZCAM_TABLE_HIGHr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0210, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_cnt_dtb_wr_zcam_table_high_reg, + NULL, + NULL, + }, + { + "cnt_dtb_wr_zcam_table_low", + DTB_DTB_CFG_CNT_DTB_WR_ZCAM_TABLE_LOWr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0214, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_cnt_dtb_wr_zcam_table_low_reg, + NULL, + NULL, + }, + { + "cnt_dtb_wr_etcam_table_high", + DTB_DTB_CFG_CNT_DTB_WR_ETCAM_TABLE_HIGHr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0218, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_cnt_dtb_wr_etcam_table_high_reg, + NULL, + NULL, + }, + { + "cnt_dtb_wr_etcam_table_low", + DTB_DTB_CFG_CNT_DTB_WR_ETCAM_TABLE_LOWr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x021c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_cnt_dtb_wr_etcam_table_low_reg, + NULL, + NULL, + }, + { + "cnt_dtb_wr_hash_table_high", + DTB_DTB_CFG_CNT_DTB_WR_HASH_TABLE_HIGHr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0220, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_cnt_dtb_wr_hash_table_high_reg, + NULL, + NULL, + }, + { + "cnt_dtb_wr_hash_table_low", + DTB_DTB_CFG_CNT_DTB_WR_HASH_TABLE_LOWr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0224, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_cnt_dtb_wr_hash_table_low_reg, + NULL, + NULL, + }, + { + "cnt_dtb_rd_smmu0_table_high", + DTB_DTB_CFG_CNT_DTB_RD_SMMU0_TABLE_HIGHr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0228, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_cnt_dtb_rd_smmu0_table_high_reg, + NULL, + NULL, + }, + { + "cnt_dtb_rd_smmu0_table_low", + DTB_DTB_CFG_CNT_DTB_RD_SMMU0_TABLE_LOWr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x022c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_cnt_dtb_rd_smmu0_table_low_reg, + NULL, + NULL, + }, + { + "cnt_dtb_rd_smmu1_table_high", + DTB_DTB_CFG_CNT_DTB_RD_SMMU1_TABLE_HIGHr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0230, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_cnt_dtb_rd_smmu1_table_high_reg, + NULL, + NULL, + }, + { + "cnt_dtb_rd_smmu1_table_low", + DTB_DTB_CFG_CNT_DTB_RD_SMMU1_TABLE_LOWr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0234, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_cnt_dtb_rd_smmu1_table_low_reg, + NULL, + NULL, + }, + { + "cnt_dtb_rd_zcam_table_high", + DTB_DTB_CFG_CNT_DTB_RD_ZCAM_TABLE_HIGHr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0238, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_cnt_dtb_rd_zcam_table_high_reg, + NULL, + NULL, + }, + { + "cnt_dtb_rd_zcam_table_low", + DTB_DTB_CFG_CNT_DTB_RD_ZCAM_TABLE_LOWr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x023c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_cnt_dtb_rd_zcam_table_low_reg, + NULL, + NULL, + }, + { + "cnt_dtb_rd_etcam_table_high", + DTB_DTB_CFG_CNT_DTB_RD_ETCAM_TABLE_HIGHr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0240, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_cnt_dtb_rd_etcam_table_high_reg, + NULL, + NULL, + }, + { + "cnt_dtb_rd_etcam_table_low", + DTB_DTB_CFG_CNT_DTB_RD_ETCAM_TABLE_LOWr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0244, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_cnt_dtb_rd_etcam_table_low_reg, + NULL, + NULL, + }, + { + "info_wr_ctrl_state", + DTB_DTB_CFG_INFO_WR_CTRL_STATEr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0248, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_info_wr_ctrl_state_reg, + NULL, + NULL, + }, + { + "info_rd_table_state", + DTB_DTB_CFG_INFO_RD_TABLE_STATEr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x024c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_info_rd_table_state_reg, + NULL, + NULL, + }, + { + "info_rd_pd_state", + DTB_DTB_CFG_INFO_RD_PD_STATEr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0250, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_info_rd_pd_state_reg, + NULL, + NULL, + }, + { + "info_dump_cmd_state", + DTB_DTB_CFG_INFO_DUMP_CMD_STATEr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0254, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_info_dump_cmd_state_reg, + NULL, + NULL, + }, + { + "info_wr_ddr_state", + DTB_DTB_CFG_INFO_WR_DDR_STATEr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0258, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_info_wr_ddr_state_reg, + NULL, + NULL, + }, + { + "cfg_dtb_debug_info_clr", + DTB_DTB_CFG_CFG_DTB_DEBUG_INFO_CLRr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x025c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_dtb_cfg_cfg_dtb_debug_info_clr_reg, + NULL, + NULL, + }, + { + "cfg_ddos_stat_dump_thrd_0_15", + DTB_DDOS_CFG_DDOS_STAT_DUMP_THRD_0_15r, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_DDOS_BASE_ADDR + 0x0000, + (32/8), + 0, + 15 + 1, + 0, + 4, + 1, + g_dtb_ddos_cfg_ddos_stat_dump_thrd_0_15_reg, + NULL, + NULL, + }, + { + "cfg_ddos_stat_dump_thrd_comp_en", + DTB_DDOS_CFG_DDOS_STAT_DUMP_THRD_COMP_ENr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_DDOS_BASE_ADDR + 0x0040, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_ddos_cfg_ddos_stat_dump_thrd_comp_en_reg, + NULL, + NULL, + }, + { + "cfg_ddos_dump_stat_num", + DTB_DDOS_CFG_DDOS_DUMP_STAT_NUMr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_DDOS_BASE_ADDR + 0x0044, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_ddos_cfg_ddos_dump_stat_num_reg, + NULL, + NULL, + }, + { + "cfg_ddos_even_hash_table_baddr", + DTB_DDOS_CFG_DDOS_EVEN_HASH_TABLE_BADDRr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_DDOS_BASE_ADDR + 0x0048, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_ddos_cfg_ddos_even_hash_table_baddr_reg, + NULL, + NULL, + }, + { + "cfg_ddos_odd_hash_table_baddr", + DTB_DDOS_CFG_DDOS_ODD_HASH_TABLE_BADDRr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_DDOS_BASE_ADDR + 0x004c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_ddos_cfg_ddos_odd_hash_table_baddr_reg, + NULL, + NULL, + }, + { + "cfg_ddos_stat_index_offset", + DTB_DDOS_CFG_DDOS_STAT_INDEX_OFFSETr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_DDOS_BASE_ADDR + 0x0050, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_ddos_cfg_ddos_stat_index_offset_reg, + NULL, + NULL, + }, + { + "cfg_ddos_ns_flag_cnt", + DTB_DDOS_CFG_DDOS_NS_FLAG_CNTr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_DDOS_BASE_ADDR + 0x0054, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_ddos_cfg_ddos_ns_flag_cnt_reg, + NULL, + NULL, + }, + { + "cfg_ddos_even_stat_table_baddr", + DTB_DDOS_CFG_DDOS_EVEN_STAT_TABLE_BADDRr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_DDOS_BASE_ADDR + 0x0058, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_ddos_cfg_ddos_even_stat_table_baddr_reg, + NULL, + NULL, + }, + { + "cfg_ddos_odd_stat_table_baddr", + DTB_DDOS_CFG_DDOS_ODD_STAT_TABLE_BADDRr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_DDOS_BASE_ADDR + 0x005c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_ddos_cfg_ddos_odd_stat_table_baddr_reg, + NULL, + NULL, + }, + { + "cfg_ddos_even_stat_dump_daddr_h", + DTB_DDOS_CFG_DDOS_EVEN_STAT_DUMP_DADDR_Hr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_DDOS_BASE_ADDR + 0x0060, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_ddos_cfg_ddos_even_stat_dump_daddr_h_reg, + NULL, + NULL, + }, + { + "cfg_ddos_even_stat_dump_daddr_l", + DTB_DDOS_CFG_DDOS_EVEN_STAT_DUMP_DADDR_Lr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_DDOS_BASE_ADDR + 0x0064, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_ddos_cfg_ddos_even_stat_dump_daddr_l_reg, + NULL, + NULL, + }, + { + "cfg_ddos_odd_stat_dump_daddr_h", + DTB_DDOS_CFG_DDOS_ODD_STAT_DUMP_DADDR_Hr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_DDOS_BASE_ADDR + 0x0068, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_ddos_cfg_ddos_odd_stat_dump_daddr_h_reg, + NULL, + NULL, + }, + { + "cfg_ddos_odd_stat_dump_daddr_l", + DTB_DDOS_CFG_DDOS_ODD_STAT_DUMP_DADDR_Lr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_DDOS_BASE_ADDR + 0x006c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_ddos_cfg_ddos_odd_stat_dump_daddr_l_reg, + NULL, + NULL, + }, + { + "cfg_ddos_work_mode_enable", + DTB_DDOS_CFG_DDOS_WORK_MODE_ENABLEr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_DDOS_BASE_ADDR + 0x0070, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_ddos_cfg_ddos_work_mode_enable_reg, + NULL, + NULL, + }, + { + "cfg_ddos_stat_table_len", + DTB_DDOS_CFG_DDOS_STAT_TABLE_LENr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_DDOS_BASE_ADDR + 0x0074, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_ddos_cfg_ddos_stat_table_len_reg, + NULL, + NULL, + }, + { + "cfg_ddos_hash_table_len", + DTB_DDOS_CFG_DDOS_HASH_TABLE_LENr, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_DDOS_BASE_ADDR + 0x0078, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_dtb_ddos_cfg_ddos_hash_table_len_reg, + NULL, + NULL, + }, + { + "traf_ctrl_ram0_0_255", + DTB_DTB_RAM_TRAF_CTRL_RAM0_0_255r, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_RAM_BASE_ADDR + 0x00000, + (32/8), + 0, + 255 + 1, + 0, + 4, + 1, + g_dtb_dtb_ram_traf_ctrl_ram0_0_255_reg, + NULL, + NULL, + }, + { + "traf_ctrl_ram1_0_255", + DTB_DTB_RAM_TRAF_CTRL_RAM1_0_255r, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_RAM_BASE_ADDR + 0x00400, + (32/8), + 0, + 255 + 1, + 0, + 4, + 1, + g_dtb_dtb_ram_traf_ctrl_ram1_0_255_reg, + NULL, + NULL, + }, + { + "traf_ctrl_ram2_0_255", + DTB_DTB_RAM_TRAF_CTRL_RAM2_0_255r, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_RAM_BASE_ADDR + 0x00800, + (32/8), + 0, + 255 + 1, + 0, + 4, + 1, + g_dtb_dtb_ram_traf_ctrl_ram2_0_255_reg, + NULL, + NULL, + }, + { + "traf_ctrl_ram3_0_255", + DTB_DTB_RAM_TRAF_CTRL_RAM3_0_255r, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_RAM_BASE_ADDR + 0x00c00, + (32/8), + 0, + 255 + 1, + 0, + 4, + 1, + g_dtb_dtb_ram_traf_ctrl_ram3_0_255_reg, + NULL, + NULL, + }, + { + "traf_ctrl_ram4_0_255", + DTB_DTB_RAM_TRAF_CTRL_RAM4_0_255r, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_RAM_BASE_ADDR + 0x01000, + (32/8), + 0, + 255 + 1, + 0, + 4, + 1, + g_dtb_dtb_ram_traf_ctrl_ram4_0_255_reg, + NULL, + NULL, + }, + { + "traf_ctrl_ram5_0_63", + DTB_DTB_RAM_TRAF_CTRL_RAM5_0_63r, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_RAM_BASE_ADDR + 0x01400, + (32/8), + 0, + 63 + 1, + 0, + 4, + 1, + g_dtb_dtb_ram_traf_ctrl_ram5_0_63_reg, + NULL, + NULL, + }, + { + "dump_pd_ram_0_2047", + DTB_DTB_RAM_DUMP_PD_RAM_0_2047r, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_RAM_BASE_ADDR + 0x02000, + (32/8), + 0, + 2047 + 1, + 0, + 4, + 1, + g_dtb_dtb_ram_dump_pd_ram_0_2047_reg, + NULL, + NULL, + }, + { + "rd_ctrl_ram_0_4095", + DTB_DTB_RAM_RD_CTRL_RAM_0_4095r, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_RAM_BASE_ADDR + 0x04000, + (32/8), + 0, + 4095 + 1, + 0, + 4, + 1, + g_dtb_dtb_ram_rd_ctrl_ram_0_4095_reg, + NULL, + NULL, + }, + { + "rd_table_ram_0_8191", + DTB_DTB_RAM_RD_TABLE_RAM_0_8191r, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_RAM_BASE_ADDR + 0x08000, + (32/8), + 0, + 8191 + 1, + 0, + 4, + 1, + g_dtb_dtb_ram_rd_table_ram_0_8191_reg, + NULL, + NULL, + }, + { + "dtb_cmd_man_ram_0_16383", + DTB_DTB_RAM_DTB_CMD_MAN_RAM_0_16383r, + DTB, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_DTB_BASE_ADDR + MODULE_DTB_RAM_BASE_ADDR + 0x10000, + (32/8), + 0, + 16383 + 1, + 0, + 4, + 1, + g_dtb_dtb_ram_dtb_cmd_man_ram_0_16383_reg, + NULL, + NULL, + }, + { + "cpu_trpg_ms_st", + TRPG_TRPG_RX_PORT_CPU_TRPG_MS_STr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0000, + (32/8), + DPP_TRPG_PORT_NUM, + 0, + DPP_TRPG_PORT_SPACE_SIZE, + 0, + 1, + g_trpg_trpg_rx_port_cpu_trpg_ms_st_reg, + NULL, + NULL, + }, + { + "cpu_trpg_ms_ind", + TRPG_TRPG_RX_PORT_CPU_TRPG_MS_INDr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0008, + (32/8), + DPP_TRPG_PORT_NUM, + 0, + DPP_TRPG_PORT_SPACE_SIZE, + 0, + 1, + g_trpg_trpg_rx_port_cpu_trpg_ms_ind_reg, + NULL, + NULL, + }, + { + "cpu_trpg_ms_slave_ind", + TRPG_TRPG_RX_PORT_CPU_TRPG_MS_SLAVE_INDr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x000c, + (32/8), + DPP_TRPG_PORT_NUM, + 0, + DPP_TRPG_PORT_SPACE_SIZE, + 0, + 1, + g_trpg_trpg_rx_port_cpu_trpg_ms_slave_ind_reg, + NULL, + NULL, + }, + { + "cpu_trpgrx_up_water_level", + TRPG_TRPG_RX_PORT_CPU_TRPGRX_UP_WATER_LEVELr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0020, + (32/8), + DPP_TRPG_PORT_NUM, + 0, + DPP_TRPG_PORT_SPACE_SIZE, + 0, + 1, + g_trpg_trpg_rx_port_cpu_trpgrx_up_water_level_reg, + NULL, + NULL, + }, + { + "cpu_trpgrx_low_water_level", + TRPG_TRPG_RX_PORT_CPU_TRPGRX_LOW_WATER_LEVELr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0024, + (32/8), + DPP_TRPG_PORT_NUM, + 0, + DPP_TRPG_PORT_SPACE_SIZE, + 0, + 1, + g_trpg_trpg_rx_port_cpu_trpgrx_low_water_level_reg, + NULL, + NULL, + }, + { + "cpu_trpg_ms_st", + TRPG_TRPG_TX_PORT_CPU_TRPG_MS_STr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x0000, + (32/8), + DPP_TRPG_PORT_NUM, + 0, + DPP_TRPG_PORT_SPACE_SIZE, + 0, + 1, + g_trpg_trpg_tx_port_cpu_trpg_ms_st_reg, + NULL, + NULL, + }, + { + "cpu_trpg_ms_ind", + TRPG_TRPG_TX_PORT_CPU_TRPG_MS_INDr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x0008, + (32/8), + DPP_TRPG_PORT_NUM, + 0, + DPP_TRPG_PORT_SPACE_SIZE, + 0, + 1, + g_trpg_trpg_tx_port_cpu_trpg_ms_ind_reg, + NULL, + NULL, + }, + { + "cpu_trpg_ms_slave_ind", + TRPG_TRPG_TX_PORT_CPU_TRPG_MS_SLAVE_INDr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x000c, + (32/8), + DPP_TRPG_PORT_NUM, + 0, + DPP_TRPG_PORT_SPACE_SIZE, + 0, + 1, + g_trpg_trpg_tx_port_cpu_trpg_ms_slave_ind_reg, + NULL, + NULL, + }, + { + "cpu_todtime_update_int_event", + TRPG_TRPG_TX_GLB_CPU_TODTIME_UPDATE_INT_EVENTr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_GLB_BASE_ADDR + 0x0004, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_trpg_trpg_tx_glb_cpu_todtime_update_int_event_reg, + NULL, + NULL, + }, + { + "cpu_todtime_update_int_test", + TRPG_TRPG_TX_GLB_CPU_TODTIME_UPDATE_INT_TESTr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_GLB_BASE_ADDR + 0x0008, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_trpg_trpg_tx_glb_cpu_todtime_update_int_test_reg, + NULL, + NULL, + }, + { + "cpu_todtime_update_int_addr", + TRPG_TRPG_TX_GLB_CPU_TODTIME_UPDATE_INT_ADDRr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_GLB_BASE_ADDR + 0x0014, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_trpg_trpg_tx_glb_cpu_todtime_update_int_addr_reg, + NULL, + NULL, + }, + { + "trpg_tx_todtime_ram", + TRPG_TRPG_TX_TODTIME_RAM_TRPG_TX_TODTIME_RAMr, + TRPG, + DPP_REG_FLAG_DIRECT, + DPP_REG_UNI_ARRAY, + SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_TODTIME_RAM_BASE_ADDR + 0x0000, + (32/8), + 0, + 4095 + 1, + 0, + 4, + 1, + g_trpg_trpg_tx_todtime_ram_trpg_tx_todtime_ram_reg, + NULL, + NULL, + }, + { + "cfg_tsn_test_reg", + TSN_TSN_PORT_CFG_TSN_TEST_REGr, + TSN, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x000, + (32/8), + DPP_TSN_PORT_NUM, + 0, + DPP_TSN_PORT_SPACE_SIZE, + 0, + 1, + g_tsn_tsn_port_cfg_tsn_test_reg_reg, + NULL, + NULL, + }, + { + "cfg_tsn_port_qbv_enable", + TSN_TSN_PORT_CFG_TSN_PORT_QBV_ENABLEr, + TSN, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x0004, + (32/8), + DPP_TSN_PORT_NUM, + 0, + DPP_TSN_PORT_SPACE_SIZE, + 0, + 1, + g_tsn_tsn_port_cfg_tsn_port_qbv_enable_reg, + NULL, + NULL, + }, + { + "cfg_tsn_phy_port_sel", + TSN_TSN_PORT_CFG_TSN_PHY_PORT_SELr, + TSN, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x0008, + (32/8), + DPP_TSN_PORT_NUM, + 0, + DPP_TSN_PORT_SPACE_SIZE, + 0, + 1, + g_tsn_tsn_port_cfg_tsn_phy_port_sel_reg, + NULL, + NULL, + }, + { + "cfg_tsn_port_time_sel", + TSN_TSN_PORT_CFG_TSN_PORT_TIME_SELr, + TSN, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x000c, + (32/8), + DPP_TSN_PORT_NUM, + 0, + DPP_TSN_PORT_SPACE_SIZE, + 0, + 1, + g_tsn_tsn_port_cfg_tsn_port_time_sel_reg, + NULL, + NULL, + }, + { + "cfg_tsn_clk_freq", + TSN_TSN_PORT_CFG_TSN_CLK_FREQr, + TSN, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x0014, + (32/8), + DPP_TSN_PORT_NUM, + 0, + DPP_TSN_PORT_SPACE_SIZE, + 0, + 2, + g_tsn_tsn_port_cfg_tsn_clk_freq_reg, + NULL, + NULL, + }, + { + "cfg_tsn_read_ram_n", + TSN_TSN_PORT_CFG_TSN_READ_RAM_Nr, + TSN, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x0018, + (32/8), + DPP_TSN_PORT_NUM, + 0, + DPP_TSN_PORT_SPACE_SIZE, + 0, + 3, + g_tsn_tsn_port_cfg_tsn_read_ram_n_reg, + NULL, + NULL, + }, + { + "cfg_tsn_exe_time", + TSN_TSN_PORT_CFG_TSN_EXE_TIMEr, + TSN, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x001c, + (32/8), + DPP_TSN_PORT_NUM, + 0, + DPP_TSN_PORT_SPACE_SIZE, + 0, + 1, + g_tsn_tsn_port_cfg_tsn_exe_time_reg, + NULL, + NULL, + }, + { + "cfg_tsn_port_itr_shift", + TSN_TSN_PORT_CFG_TSN_PORT_ITR_SHIFTr, + TSN, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x0020, + (32/8), + DPP_TSN_PORT_NUM, + 0, + DPP_TSN_PORT_SPACE_SIZE, + 0, + 1, + g_tsn_tsn_port_cfg_tsn_port_itr_shift_reg, + NULL, + NULL, + }, + { + "cfg_tsn_port_base_time_h", + TSN_TSN_PORT_CFG_TSN_PORT_BASE_TIME_Hr, + TSN, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x0024, + (32/8), + DPP_TSN_PORT_NUM, + 0, + DPP_TSN_PORT_SPACE_SIZE, + 0, + 1, + g_tsn_tsn_port_cfg_tsn_port_base_time_h_reg, + NULL, + NULL, + }, + { + "cfg_tsn_port_base_time_l", + TSN_TSN_PORT_CFG_TSN_PORT_BASE_TIME_Lr, + TSN, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x0028, + (32/8), + DPP_TSN_PORT_NUM, + 0, + DPP_TSN_PORT_SPACE_SIZE, + 0, + 1, + g_tsn_tsn_port_cfg_tsn_port_base_time_l_reg, + NULL, + NULL, + }, + { + "cfg_tsn_port_cycle_time_h", + TSN_TSN_PORT_CFG_TSN_PORT_CYCLE_TIME_Hr, + TSN, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x0030, + (32/8), + DPP_TSN_PORT_NUM, + 0, + DPP_TSN_PORT_SPACE_SIZE, + 0, + 1, + g_tsn_tsn_port_cfg_tsn_port_cycle_time_h_reg, + NULL, + NULL, + }, + { + "cfg_tsn_port_cycle_time_l", + TSN_TSN_PORT_CFG_TSN_PORT_CYCLE_TIME_Lr, + TSN, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x0034, + (32/8), + DPP_TSN_PORT_NUM, + 0, + DPP_TSN_PORT_SPACE_SIZE, + 0, + 1, + g_tsn_tsn_port_cfg_tsn_port_cycle_time_l_reg, + NULL, + NULL, + }, + { + "cfg_tsn_port_guard_band_time", + TSN_TSN_PORT_CFG_TSN_PORT_GUARD_BAND_TIMEr, + TSN, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x0040, + (32/8), + DPP_TSN_PORT_NUM, + 7 + 1, + DPP_TSN_PORT_SPACE_SIZE, + 4, + 1, + g_tsn_tsn_port_cfg_tsn_port_guard_band_time_reg, + NULL, + NULL, + }, + { + "cfg_tsn_port_default_gate_en", + TSN_TSN_PORT_CFG_TSN_PORT_DEFAULT_GATE_ENr, + TSN, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x0060, + (32/8), + DPP_TSN_PORT_NUM, + 0, + DPP_TSN_PORT_SPACE_SIZE, + 0, + 1, + g_tsn_tsn_port_cfg_tsn_port_default_gate_en_reg, + NULL, + NULL, + }, + { + "cfg_tsn_port_change_gate_en", + TSN_TSN_PORT_CFG_TSN_PORT_CHANGE_GATE_ENr, + TSN, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x0064, + (32/8), + DPP_TSN_PORT_NUM, + 0, + DPP_TSN_PORT_SPACE_SIZE, + 0, + 1, + g_tsn_tsn_port_cfg_tsn_port_change_gate_en_reg, + NULL, + NULL, + }, + { + "cfg_tsn_port_init_finish", + TSN_TSN_PORT_CFG_TSN_PORT_INIT_FINISHr, + TSN, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x0068, + (32/8), + DPP_TSN_PORT_NUM, + 0, + DPP_TSN_PORT_SPACE_SIZE, + 0, + 1, + g_tsn_tsn_port_cfg_tsn_port_init_finish_reg, + NULL, + NULL, + }, + { + "cfg_tsn_port_change_en", + TSN_TSN_PORT_CFG_TSN_PORT_CHANGE_ENr, + TSN, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x006c, + (32/8), + DPP_TSN_PORT_NUM, + 0, + DPP_TSN_PORT_SPACE_SIZE, + 0, + 1, + g_tsn_tsn_port_cfg_tsn_port_change_en_reg, + NULL, + NULL, + }, + { + "cfg_tsn_port_gcl_num0", + TSN_TSN_PORT_CFG_TSN_PORT_GCL_NUM0r, + TSN, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x0070, + (32/8), + DPP_TSN_PORT_NUM, + 0, + DPP_TSN_PORT_SPACE_SIZE, + 0, + 1, + g_tsn_tsn_port_cfg_tsn_port_gcl_num0_reg, + NULL, + NULL, + }, + { + "cfg_tsn_port_gcl_num1", + TSN_TSN_PORT_CFG_TSN_PORT_GCL_NUM1r, + TSN, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x0074, + (32/8), + DPP_TSN_PORT_NUM, + 0, + DPP_TSN_PORT_SPACE_SIZE, + 0, + 1, + g_tsn_tsn_port_cfg_tsn_port_gcl_num1_reg, + NULL, + NULL, + }, + { + "cfg_tsn_port_gcl_value0", + TSN_TSN_PORT_CFG_TSN_PORT_GCL_VALUE0r, + TSN, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x1000, + (32/8), + DPP_TSN_PORT_NUM, + 255 + 1, + DPP_TSN_PORT_SPACE_SIZE, + 4, + 2, + g_tsn_tsn_port_cfg_tsn_port_gcl_value0_reg, + NULL, + NULL, + }, + { + "cfg_tsn_port_gcl_value1", + TSN_TSN_PORT_CFG_TSN_PORT_GCL_VALUE1r, + TSN, + DPP_REG_FLAG_DIRECT, + DPP_REG_BIN_ARRAY, + SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x2000, + (32/8), + DPP_TSN_PORT_NUM, + 255 + 1, + DPP_TSN_PORT_SPACE_SIZE, + 4, + 2, + g_tsn_tsn_port_cfg_tsn_port_gcl_value1_reg, + NULL, + NULL, + }, + { + "cfg_epid_v_func_num", + AXI_AXI_CONV_CFG_EPID_V_FUNC_NUMr, + AXI, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_AXI_CONV_BASE_ADDR + 0x0010, + (32/8), + 0, + 0, + 0, + 0, + 5, + g_axi_axi_conv_cfg_epid_v_func_num_reg, + NULL, + NULL, + }, + { + "info_axim_rw_hsk_cnt", + AXI_AXI_CONV_INFO_AXIM_RW_HSK_CNTr, + AXI, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_AXI_CONV_BASE_ADDR + 0x0020, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_axi_axi_conv_info_axim_rw_hsk_cnt_reg, + NULL, + NULL, + }, + { + "info_axim_last_wr_id", + AXI_AXI_CONV_INFO_AXIM_LAST_WR_IDr, + AXI, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_AXI_CONV_BASE_ADDR + 0x0024, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_axi_axi_conv_info_axim_last_wr_id_reg, + NULL, + NULL, + }, + { + "info_axim_last_wr_addr_h", + AXI_AXI_CONV_INFO_AXIM_LAST_WR_ADDR_Hr, + AXI, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_AXI_CONV_BASE_ADDR + 0x0030, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_axi_axi_conv_info_axim_last_wr_addr_h_reg, + NULL, + NULL, + }, + { + "info_axim_last_wr_addr_l", + AXI_AXI_CONV_INFO_AXIM_LAST_WR_ADDR_Lr, + AXI, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_AXI_CONV_BASE_ADDR + 0x0034, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_axi_axi_conv_info_axim_last_wr_addr_l_reg, + NULL, + NULL, + }, + { + "cfg_debug_info_clr_en", + AXI_AXI_CONV_CFG_DEBUG_INFO_CLR_ENr, + AXI, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_AXI_CONV_BASE_ADDR + 0x0038, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_axi_axi_conv_cfg_debug_info_clr_en_reg, + NULL, + NULL, + }, + { + "pp1s_interrupt", + PTPTM_PTP_TOP_PP1S_INTERRUPTr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP0_BASE_ADDR + 0x0000, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_ptptm_ptp_top_pp1s_interrupt_reg, + NULL, + NULL, + }, + { + "pp1s_external_select", + PTPTM_PTP_TOP_PP1S_EXTERNAL_SELECTr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP0_BASE_ADDR + 0x0004, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptp_top_pp1s_external_select_reg, + NULL, + NULL, + }, + { + "pp1s_out_select", + PTPTM_PTP_TOP_PP1S_OUT_SELECTr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP0_BASE_ADDR + 0x0008, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptp_top_pp1s_out_select_reg, + NULL, + NULL, + }, + { + "test_pp1s_select", + PTPTM_PTP_TOP_TEST_PP1S_SELECTr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP0_BASE_ADDR + 0x000c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptp_top_test_pp1s_select_reg, + NULL, + NULL, + }, + { + "local_pp1s_en", + PTPTM_PTP_TOP_LOCAL_PP1S_ENr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP0_BASE_ADDR + 0x0010, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptp_top_local_pp1s_en_reg, + NULL, + NULL, + }, + { + "local_pp1s_adjust", + PTPTM_PTP_TOP_LOCAL_PP1S_ADJUSTr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP0_BASE_ADDR + 0x0014, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_ptptm_ptp_top_local_pp1s_adjust_reg, + NULL, + NULL, + }, + { + "local_pp1s_adjust_value", + PTPTM_PTP_TOP_LOCAL_PP1S_ADJUST_VALUEr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP0_BASE_ADDR + 0x0018, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptp_top_local_pp1s_adjust_value_reg, + NULL, + NULL, + }, + { + "pp1s_to_np_select", + PTPTM_PTP_TOP_PP1S_TO_NP_SELECTr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP0_BASE_ADDR + 0x001c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptp_top_pp1s_to_np_select_reg, + NULL, + NULL, + }, + { + "pd_u1_sel", + PTPTM_PTP_TOP_PD_U1_SELr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP0_BASE_ADDR + 0x0040, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_ptptm_ptp_top_pd_u1_sel_reg, + NULL, + NULL, + }, + { + "pd_u1_pd0_shift", + PTPTM_PTP_TOP_PD_U1_PD0_SHIFTr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP0_BASE_ADDR + 0x0044, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptp_top_pd_u1_pd0_shift_reg, + NULL, + NULL, + }, + { + "pd_u1_pd1_shift", + PTPTM_PTP_TOP_PD_U1_PD1_SHIFTr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP0_BASE_ADDR + 0x0048, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptp_top_pd_u1_pd1_shift_reg, + NULL, + NULL, + }, + { + "pd_u1_result", + PTPTM_PTP_TOP_PD_U1_RESULTr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP0_BASE_ADDR + 0x004c, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_ptptm_ptp_top_pd_u1_result_reg, + NULL, + NULL, + }, + { + "pd_u2_sel", + PTPTM_PTP_TOP_PD_U2_SELr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP0_BASE_ADDR + 0x0050, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_ptptm_ptp_top_pd_u2_sel_reg, + NULL, + NULL, + }, + { + "pd_u2_pd0_shift", + PTPTM_PTP_TOP_PD_U2_PD0_SHIFTr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP0_BASE_ADDR + 0x0054, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptp_top_pd_u2_pd0_shift_reg, + NULL, + NULL, + }, + { + "pd_u2_pd1_shift", + PTPTM_PTP_TOP_PD_U2_PD1_SHIFTr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP0_BASE_ADDR + 0x0058, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptp_top_pd_u2_pd1_shift_reg, + NULL, + NULL, + }, + { + "pd_u2_result", + PTPTM_PTP_TOP_PD_U2_RESULTr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP0_BASE_ADDR + 0x005c, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_ptptm_ptp_top_pd_u2_result_reg, + NULL, + NULL, + }, + { + "tsn_group_nanosecond_delay0", + PTPTM_PTP_TOP_TSN_GROUP_NANOSECOND_DELAY0r, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP0_BASE_ADDR + 0x0080, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptp_top_tsn_group_nanosecond_delay0_reg, + NULL, + NULL, + }, + { + "tsn_group_fracnanosecond_delay0", + PTPTM_PTP_TOP_TSN_GROUP_FRACNANOSECOND_DELAY0r, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP0_BASE_ADDR + 0x0084, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptp_top_tsn_group_fracnanosecond_delay0_reg, + NULL, + NULL, + }, + { + "tsn_group_nanosecond_delay1", + PTPTM_PTP_TOP_TSN_GROUP_NANOSECOND_DELAY1r, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP0_BASE_ADDR + 0x0088, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptp_top_tsn_group_nanosecond_delay1_reg, + NULL, + NULL, + }, + { + "tsn_group_fracnanosecond_delay1", + PTPTM_PTP_TOP_TSN_GROUP_FRACNANOSECOND_DELAY1r, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP0_BASE_ADDR + 0x008c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptp_top_tsn_group_fracnanosecond_delay1_reg, + NULL, + NULL, + }, + { + "tsn_group_nanosecond_delay2", + PTPTM_PTP_TOP_TSN_GROUP_NANOSECOND_DELAY2r, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP0_BASE_ADDR + 0x0090, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptp_top_tsn_group_nanosecond_delay2_reg, + NULL, + NULL, + }, + { + "tsn_group_fracnanosecond_delay2", + PTPTM_PTP_TOP_TSN_GROUP_FRACNANOSECOND_DELAY2r, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP0_BASE_ADDR + 0x0094, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptp_top_tsn_group_fracnanosecond_delay2_reg, + NULL, + NULL, + }, + { + "tsn_group_nanosecond_delay3", + PTPTM_PTP_TOP_TSN_GROUP_NANOSECOND_DELAY3r, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP0_BASE_ADDR + 0x0098, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptp_top_tsn_group_nanosecond_delay3_reg, + NULL, + NULL, + }, + { + "tsn_group_fracnanosecond_delay3", + PTPTM_PTP_TOP_TSN_GROUP_FRACNANOSECOND_DELAY3r, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP0_BASE_ADDR + 0x009c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptp_top_tsn_group_fracnanosecond_delay3_reg, + NULL, + NULL, + }, + { + "tsn_ptp1588_rdma_nanosecond_delay", + PTPTM_PTP_TOP_TSN_PTP1588_RDMA_NANOSECOND_DELAYr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP0_BASE_ADDR + 0x00a0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptp_top_tsn_ptp1588_rdma_nanosecond_delay_reg, + NULL, + NULL, + }, + { + "ptp1588_rdma_fracnanosecond_delay", + PTPTM_PTP_TOP_PTP1588_RDMA_FRACNANOSECOND_DELAYr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP0_BASE_ADDR + 0x00a4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptp_top_ptp1588_rdma_fracnanosecond_delay_reg, + NULL, + NULL, + }, + { + "ptp1588_np_nanosecond_delay", + PTPTM_PTP_TOP_PTP1588_NP_NANOSECOND_DELAYr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP0_BASE_ADDR + 0x00a8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptp_top_ptp1588_np_nanosecond_delay_reg, + NULL, + NULL, + }, + { + "ptp1588_np_fracnanosecond_delay", + PTPTM_PTP_TOP_PTP1588_NP_FRACNANOSECOND_DELAYr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP0_BASE_ADDR + 0x00ac, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptp_top_ptp1588_np_fracnanosecond_delay_reg, + NULL, + NULL, + }, + { + "time_sync_period", + PTPTM_PTP_TOP_TIME_SYNC_PERIODr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP0_BASE_ADDR + 0x00b0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptp_top_time_sync_period_reg, + NULL, + NULL, + }, + { + "module_id", + PTPTM_PTPTM_MODULE_IDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0000, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_module_id_reg, + NULL, + NULL, + }, + { + "module_version", + PTPTM_PTPTM_MODULE_VERSIONr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0008, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_ptptm_ptptm_module_version_reg, + NULL, + NULL, + }, + { + "module_date", + PTPTM_PTPTM_MODULE_DATEr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x000c, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_ptptm_ptptm_module_date_reg, + NULL, + NULL, + }, + { + "interrupt_status", + PTPTM_PTPTM_INTERRUPT_STATUSr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0010, + (32/8), + 0, + 0, + 0, + 0, + 5, + g_ptptm_ptptm_interrupt_status_reg, + NULL, + NULL, + }, + { + "interrupt_event", + PTPTM_PTPTM_INTERRUPT_EVENTr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0014, + (32/8), + 0, + 0, + 0, + 0, + 5, + g_ptptm_ptptm_interrupt_event_reg, + NULL, + NULL, + }, + { + "interrupt_mask", + PTPTM_PTPTM_INTERRUPT_MASKr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0018, + (32/8), + 0, + 0, + 0, + 0, + 5, + g_ptptm_ptptm_interrupt_mask_reg, + NULL, + NULL, + }, + { + "interrupt_test", + PTPTM_PTPTM_INTERRUPT_TESTr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x001c, + (32/8), + 0, + 0, + 0, + 0, + 5, + g_ptptm_ptptm_interrupt_test_reg, + NULL, + NULL, + }, + { + "hw_clock_cycle_integer", + PTPTM_PTPTM_HW_CLOCK_CYCLE_INTEGERr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0028, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_hw_clock_cycle_integer_reg, + NULL, + NULL, + }, + { + "hw_clock_cycle_fraction", + PTPTM_PTPTM_HW_CLOCK_CYCLE_FRACTIONr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x002c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_hw_clock_cycle_fraction_reg, + NULL, + NULL, + }, + { + "ptp_clock_cycle_integer", + PTPTM_PTPTM_PTP_CLOCK_CYCLE_INTEGERr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0030, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_ptp_clock_cycle_integer_reg, + NULL, + NULL, + }, + { + "ptp_clock_cycle_fraction", + PTPTM_PTPTM_PTP_CLOCK_CYCLE_FRACTIONr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0034, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_ptp_clock_cycle_fraction_reg, + NULL, + NULL, + }, + { + "ptp_configuration", + PTPTM_PTPTM_PTP_CONFIGURATIONr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0040, + (32/8), + 0, + 0, + 0, + 0, + 18, + g_ptptm_ptptm_ptp_configuration_reg, + NULL, + NULL, + }, + { + "timer_control", + PTPTM_PTPTM_TIMER_CONTROLr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0044, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_ptptm_ptptm_timer_control_reg, + NULL, + NULL, + }, + { + "pps_income_delay", + PTPTM_PTPTM_PPS_INCOME_DELAYr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0048, + (32/8), + 0, + 0, + 0, + 0, + 2, + g_ptptm_ptptm_pps_income_delay_reg, + NULL, + NULL, + }, + { + "clock_cycle_update", + PTPTM_PTPTM_CLOCK_CYCLE_UPDATEr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x004c, + (32/8), + 0, + 0, + 0, + 0, + 5, + g_ptptm_ptptm_clock_cycle_update_reg, + NULL, + NULL, + }, + { + "cycle_time_of_output_period_pulse_1", + PTPTM_PTPTM_CYCLE_TIME_OF_OUTPUT_PERIOD_PULSE_1r, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0050, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_cycle_time_of_output_period_pulse_1_reg, + NULL, + NULL, + }, + { + "cycle_time_of_output_period_pulse_2", + PTPTM_PTPTM_CYCLE_TIME_OF_OUTPUT_PERIOD_PULSE_2r, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0054, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_cycle_time_of_output_period_pulse_2_reg, + NULL, + NULL, + }, + { + "timer_latch_en", + PTPTM_PTPTM_TIMER_LATCH_ENr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0058, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_timer_latch_en_reg, + NULL, + NULL, + }, + { + "timer_latch_sel", + PTPTM_PTPTM_TIMER_LATCH_SELr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x005c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_timer_latch_sel_reg, + NULL, + NULL, + }, + { + "trigger_in_tod_nanosecond", + PTPTM_PTPTM_TRIGGER_IN_TOD_NANOSECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0060, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_trigger_in_tod_nanosecond_reg, + NULL, + NULL, + }, + { + "trigger_in_lower_tod_second", + PTPTM_PTPTM_TRIGGER_IN_LOWER_TOD_SECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0064, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_trigger_in_lower_tod_second_reg, + NULL, + NULL, + }, + { + "trigger_in_high_tod_second", + PTPTM_PTPTM_TRIGGER_IN_HIGH_TOD_SECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0068, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_trigger_in_high_tod_second_reg, + NULL, + NULL, + }, + { + "trigger_in_fracnanosecond", + PTPTM_PTPTM_TRIGGER_IN_FRACNANOSECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x006c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_trigger_in_fracnanosecond_reg, + NULL, + NULL, + }, + { + "trigger_in_hardware_time_low", + PTPTM_PTPTM_TRIGGER_IN_HARDWARE_TIME_LOWr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0070, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_trigger_in_hardware_time_low_reg, + NULL, + NULL, + }, + { + "trigger_in_hardware_time_high", + PTPTM_PTPTM_TRIGGER_IN_HARDWARE_TIME_HIGHr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0074, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_trigger_in_hardware_time_high_reg, + NULL, + NULL, + }, + { + "trigger_out_tod_nanosecond", + PTPTM_PTPTM_TRIGGER_OUT_TOD_NANOSECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0080, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_trigger_out_tod_nanosecond_reg, + NULL, + NULL, + }, + { + "trigger_out_lower_tod_second", + PTPTM_PTPTM_TRIGGER_OUT_LOWER_TOD_SECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0084, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_trigger_out_lower_tod_second_reg, + NULL, + NULL, + }, + { + "trigger_out_high_tod_second", + PTPTM_PTPTM_TRIGGER_OUT_HIGH_TOD_SECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0088, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_trigger_out_high_tod_second_reg, + NULL, + NULL, + }, + { + "trigger_out_hardware_time_low", + PTPTM_PTPTM_TRIGGER_OUT_HARDWARE_TIME_LOWr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0090, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_trigger_out_hardware_time_low_reg, + NULL, + NULL, + }, + { + "trigger_out_hardware_time_high", + PTPTM_PTPTM_TRIGGER_OUT_HARDWARE_TIME_HIGHr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0094, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_trigger_out_hardware_time_high_reg, + NULL, + NULL, + }, + { + "adjust_tod_nanosecond", + PTPTM_PTPTM_ADJUST_TOD_NANOSECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x00a0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_adjust_tod_nanosecond_reg, + NULL, + NULL, + }, + { + "adjust_lower_tod_second", + PTPTM_PTPTM_ADJUST_LOWER_TOD_SECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x00a4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_adjust_lower_tod_second_reg, + NULL, + NULL, + }, + { + "adjust_high_tod_second", + PTPTM_PTPTM_ADJUST_HIGH_TOD_SECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x00a8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_adjust_high_tod_second_reg, + NULL, + NULL, + }, + { + "adjust_fracnanosecond", + PTPTM_PTPTM_ADJUST_FRACNANOSECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x00ac, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_adjust_fracnanosecond_reg, + NULL, + NULL, + }, + { + "adjust_hardware_time_low", + PTPTM_PTPTM_ADJUST_HARDWARE_TIME_LOWr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x00b0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_adjust_hardware_time_low_reg, + NULL, + NULL, + }, + { + "adjust_hardware_time_high", + PTPTM_PTPTM_ADJUST_HARDWARE_TIME_HIGHr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x00b4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_adjust_hardware_time_high_reg, + NULL, + NULL, + }, + { + "latch_tod_nanosecond", + PTPTM_PTPTM_LATCH_TOD_NANOSECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x00c0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_latch_tod_nanosecond_reg, + NULL, + NULL, + }, + { + "latch_lower_tod_second", + PTPTM_PTPTM_LATCH_LOWER_TOD_SECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x00c4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_latch_lower_tod_second_reg, + NULL, + NULL, + }, + { + "latch_high_tod_second", + PTPTM_PTPTM_LATCH_HIGH_TOD_SECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x00c8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_latch_high_tod_second_reg, + NULL, + NULL, + }, + { + "latch_fracnanosecond", + PTPTM_PTPTM_LATCH_FRACNANOSECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x00cc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_latch_fracnanosecond_reg, + NULL, + NULL, + }, + { + "latch_hardware_time_low", + PTPTM_PTPTM_LATCH_HARDWARE_TIME_LOWr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x00d0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_latch_hardware_time_low_reg, + NULL, + NULL, + }, + { + "latch_hardware_time_high", + PTPTM_PTPTM_LATCH_HARDWARE_TIME_HIGHr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x00d4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_latch_hardware_time_high_reg, + NULL, + NULL, + }, + { + "real_tod_nanosecond", + PTPTM_PTPTM_REAL_TOD_NANOSECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x00e0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_real_tod_nanosecond_reg, + NULL, + NULL, + }, + { + "real_lower_tod_second", + PTPTM_PTPTM_REAL_LOWER_TOD_SECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x00e4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_real_lower_tod_second_reg, + NULL, + NULL, + }, + { + "real_high_tod_second", + PTPTM_PTPTM_REAL_HIGH_TOD_SECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x00e8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_real_high_tod_second_reg, + NULL, + NULL, + }, + { + "real_hardware_time_low", + PTPTM_PTPTM_REAL_HARDWARE_TIME_LOWr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x00f0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_real_hardware_time_low_reg, + NULL, + NULL, + }, + { + "real_hardware_time_high", + PTPTM_PTPTM_REAL_HARDWARE_TIME_HIGHr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x00f4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_real_hardware_time_high_reg, + NULL, + NULL, + }, + { + "ptp1588_event_message_port", + PTPTM_PTPTM_PTP1588_EVENT_MESSAGE_PORTr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0100, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_ptp1588_event_message_port_reg, + NULL, + NULL, + }, + { + "ptp1588_event_message_timestamp_low", + PTPTM_PTPTM_PTP1588_EVENT_MESSAGE_TIMESTAMP_LOWr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0104, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_ptp1588_event_message_timestamp_low_reg, + NULL, + NULL, + }, + { + "ptp1588_event_message_timestamp_high", + PTPTM_PTPTM_PTP1588_EVENT_MESSAGE_TIMESTAMP_HIGHr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0108, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_ptp1588_event_message_timestamp_high_reg, + NULL, + NULL, + }, + { + "ptp1588_event_message_fifo_status", + PTPTM_PTPTM_PTP1588_EVENT_MESSAGE_FIFO_STATUSr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x010c, + (32/8), + 0, + 0, + 0, + 0, + 3, + g_ptptm_ptptm_ptp1588_event_message_fifo_status_reg, + NULL, + NULL, + }, + { + "pp1s_latch_tod_nanosecond", + PTPTM_PTPTM_PP1S_LATCH_TOD_NANOSECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0120, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_pp1s_latch_tod_nanosecond_reg, + NULL, + NULL, + }, + { + "pp1s_latch_lower_tod_second", + PTPTM_PTPTM_PP1S_LATCH_LOWER_TOD_SECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0124, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_pp1s_latch_lower_tod_second_reg, + NULL, + NULL, + }, + { + "pp1s_latch_high_tod_second", + PTPTM_PTPTM_PP1S_LATCH_HIGH_TOD_SECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0128, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_pp1s_latch_high_tod_second_reg, + NULL, + NULL, + }, + { + "pp1s_latch_fracnanosecond", + PTPTM_PTPTM_PP1S_LATCH_FRACNANOSECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x012c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_pp1s_latch_fracnanosecond_reg, + NULL, + NULL, + }, + { + "tsn_time_configuration", + PTPTM_PTPTM_TSN_TIME_CONFIGURATIONr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0140, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_ptptm_ptptm_tsn_time_configuration_reg, + NULL, + NULL, + }, + { + "tsn_timer_control", + PTPTM_PTPTM_TSN_TIMER_CONTROLr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x00144, + (32/8), + 0, + 0, + 0, + 0, + 4, + g_ptptm_ptptm_tsn_timer_control_reg, + NULL, + NULL, + }, + { + "tsn0_clock_cycle_integer", + PTPTM_PTPTM_TSN0_CLOCK_CYCLE_INTEGERr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x00148, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_tsn0_clock_cycle_integer_reg, + NULL, + NULL, + }, + { + "tsn0_clock_cycle_fraction", + PTPTM_PTPTM_TSN0_CLOCK_CYCLE_FRACTIONr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x014c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_tsn0_clock_cycle_fraction_reg, + NULL, + NULL, + }, + { + "tsn1_clock_cycle_integer", + PTPTM_PTPTM_TSN1_CLOCK_CYCLE_INTEGERr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0150, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_tsn1_clock_cycle_integer_reg, + NULL, + NULL, + }, + { + "tsn1_clock_cycle_fraction", + PTPTM_PTPTM_TSN1_CLOCK_CYCLE_FRACTIONr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0154, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_tsn1_clock_cycle_fraction_reg, + NULL, + NULL, + }, + { + "tsn2_clock_cycle_integer", + PTPTM_PTPTM_TSN2_CLOCK_CYCLE_INTEGERr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0158, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_tsn2_clock_cycle_integer_reg, + NULL, + NULL, + }, + { + "tsn2_clock_cycle_fraction", + PTPTM_PTPTM_TSN2_CLOCK_CYCLE_FRACTIONr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x015c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_tsn2_clock_cycle_fraction_reg, + NULL, + NULL, + }, + { + "tsn3_clock_cycle_integer", + PTPTM_PTPTM_TSN3_CLOCK_CYCLE_INTEGERr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0160, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_tsn3_clock_cycle_integer_reg, + NULL, + NULL, + }, + { + "tsn3_clock_cycle_fraction", + PTPTM_PTPTM_TSN3_CLOCK_CYCLE_FRACTIONr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0164, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_tsn3_clock_cycle_fraction_reg, + NULL, + NULL, + }, + { + "tsn0_adjust_tod_nanosecond", + PTPTM_PTPTM_TSN0_ADJUST_TOD_NANOSECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0180, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_tsn0_adjust_tod_nanosecond_reg, + NULL, + NULL, + }, + { + "tsn0_adjust_lower_tod_second", + PTPTM_PTPTM_TSN0_ADJUST_LOWER_TOD_SECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0184, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_tsn0_adjust_lower_tod_second_reg, + NULL, + NULL, + }, + { + "tsn0_adjust_high_tod_second", + PTPTM_PTPTM_TSN0_ADJUST_HIGH_TOD_SECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0188, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_tsn0_adjust_high_tod_second_reg, + NULL, + NULL, + }, + { + "tsn0_adjust_fracnanosecond", + PTPTM_PTPTM_TSN0_ADJUST_FRACNANOSECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x018c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_tsn0_adjust_fracnanosecond_reg, + NULL, + NULL, + }, + { + "tsn1_adjust_tod_nanosecond", + PTPTM_PTPTM_TSN1_ADJUST_TOD_NANOSECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0190, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_tsn1_adjust_tod_nanosecond_reg, + NULL, + NULL, + }, + { + "tsn1_adjust_lower_tod_second", + PTPTM_PTPTM_TSN1_ADJUST_LOWER_TOD_SECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0194, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_tsn1_adjust_lower_tod_second_reg, + NULL, + NULL, + }, + { + "tsn1_adjust_high_tod_second", + PTPTM_PTPTM_TSN1_ADJUST_HIGH_TOD_SECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0198, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_tsn1_adjust_high_tod_second_reg, + NULL, + NULL, + }, + { + "tsn1_adjust_fracnanosecond", + PTPTM_PTPTM_TSN1_ADJUST_FRACNANOSECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x019c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_tsn1_adjust_fracnanosecond_reg, + NULL, + NULL, + }, + { + "tsn2_adjust_tod_nanosecond", + PTPTM_PTPTM_TSN2_ADJUST_TOD_NANOSECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x01a0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_tsn2_adjust_tod_nanosecond_reg, + NULL, + NULL, + }, + { + "tsn2_adjust_lower_tod_second", + PTPTM_PTPTM_TSN2_ADJUST_LOWER_TOD_SECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x01a4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_tsn2_adjust_lower_tod_second_reg, + NULL, + NULL, + }, + { + "tsn2_adjust_high_tod_second", + PTPTM_PTPTM_TSN2_ADJUST_HIGH_TOD_SECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x01a8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_tsn2_adjust_high_tod_second_reg, + NULL, + NULL, + }, + { + "tsn2_adjust_fracnanosecond", + PTPTM_PTPTM_TSN2_ADJUST_FRACNANOSECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x01ac, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_tsn2_adjust_fracnanosecond_reg, + NULL, + NULL, + }, + { + "tsn3_adjust_tod_nanosecond", + PTPTM_PTPTM_TSN3_ADJUST_TOD_NANOSECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x01b0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_tsn3_adjust_tod_nanosecond_reg, + NULL, + NULL, + }, + { + "tsn3_adjust_lower_tod_second", + PTPTM_PTPTM_TSN3_ADJUST_LOWER_TOD_SECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x01b4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_tsn3_adjust_lower_tod_second_reg, + NULL, + NULL, + }, + { + "tsn3_adjust_high_tod_second", + PTPTM_PTPTM_TSN3_ADJUST_HIGH_TOD_SECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x01b8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_tsn3_adjust_high_tod_second_reg, + NULL, + NULL, + }, + { + "tsn3_adjust_fracnanosecond", + PTPTM_PTPTM_TSN3_ADJUST_FRACNANOSECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x01bc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_tsn3_adjust_fracnanosecond_reg, + NULL, + NULL, + }, + { + "tsn0_latch_tod_nanosecond", + PTPTM_PTPTM_TSN0_LATCH_TOD_NANOSECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x01c0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_tsn0_latch_tod_nanosecond_reg, + NULL, + NULL, + }, + { + "tsn0_latch_lower_tod_second", + PTPTM_PTPTM_TSN0_LATCH_LOWER_TOD_SECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x01c4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_tsn0_latch_lower_tod_second_reg, + NULL, + NULL, + }, + { + "tsn0_latch_high_tod_second", + PTPTM_PTPTM_TSN0_LATCH_HIGH_TOD_SECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x01c8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_tsn0_latch_high_tod_second_reg, + NULL, + NULL, + }, + { + "tsn0_latch_fracnanosecond", + PTPTM_PTPTM_TSN0_LATCH_FRACNANOSECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x01cc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_tsn0_latch_fracnanosecond_reg, + NULL, + NULL, + }, + { + "tsn1_latch_tod_nanosecond", + PTPTM_PTPTM_TSN1_LATCH_TOD_NANOSECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x01d0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_tsn1_latch_tod_nanosecond_reg, + NULL, + NULL, + }, + { + "tsn1_latch_lower_tod_second", + PTPTM_PTPTM_TSN1_LATCH_LOWER_TOD_SECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x01d4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_tsn1_latch_lower_tod_second_reg, + NULL, + NULL, + }, + { + "tsn1_latch_high_tod_second", + PTPTM_PTPTM_TSN1_LATCH_HIGH_TOD_SECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x01d8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_tsn1_latch_high_tod_second_reg, + NULL, + NULL, + }, + { + "tsn1_latch_fracnanosecond", + PTPTM_PTPTM_TSN1_LATCH_FRACNANOSECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x01dc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_tsn1_latch_fracnanosecond_reg, + NULL, + NULL, + }, + { + "tsn2_latch_tod_nanosecond", + PTPTM_PTPTM_TSN2_LATCH_TOD_NANOSECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x01e0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_tsn2_latch_tod_nanosecond_reg, + NULL, + NULL, + }, + { + "tsn2_latch_lower_tod_second", + PTPTM_PTPTM_TSN2_LATCH_LOWER_TOD_SECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x01e4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_tsn2_latch_lower_tod_second_reg, + NULL, + NULL, + }, + { + "tsn2_latch_high_tod_second", + PTPTM_PTPTM_TSN2_LATCH_HIGH_TOD_SECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x01e8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_tsn2_latch_high_tod_second_reg, + NULL, + NULL, + }, + { + "tsn2_latch_fracnanosecond", + PTPTM_PTPTM_TSN2_LATCH_FRACNANOSECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x01ec, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_tsn2_latch_fracnanosecond_reg, + NULL, + NULL, + }, + { + "tsn3_latch_tod_nanosecond", + PTPTM_PTPTM_TSN3_LATCH_TOD_NANOSECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x01f0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_tsn3_latch_tod_nanosecond_reg, + NULL, + NULL, + }, + { + "tsn3_latch_lower_tod_second", + PTPTM_PTPTM_TSN3_LATCH_LOWER_TOD_SECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x01f4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_tsn3_latch_lower_tod_second_reg, + NULL, + NULL, + }, + { + "tsn3_latch_high_tod_second", + PTPTM_PTPTM_TSN3_LATCH_HIGH_TOD_SECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x01f8, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_tsn3_latch_high_tod_second_reg, + NULL, + NULL, + }, + { + "tsn3_latch_fracnanosecond", + PTPTM_PTPTM_TSN3_LATCH_FRACNANOSECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x01fc, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_tsn3_latch_fracnanosecond_reg, + NULL, + NULL, + }, + { + "pp1s_latch_tsn0_tod_nanosecond", + PTPTM_PTPTM_PP1S_LATCH_TSN0_TOD_NANOSECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0200, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_pp1s_latch_tsn0_tod_nanosecond_reg, + NULL, + NULL, + }, + { + "pp1s_latch_tsn0_lower_tod_second", + PTPTM_PTPTM_PP1S_LATCH_TSN0_LOWER_TOD_SECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0204, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_pp1s_latch_tsn0_lower_tod_second_reg, + NULL, + NULL, + }, + { + "pp1s_latch_tsn0_high_tod_second", + PTPTM_PTPTM_PP1S_LATCH_TSN0_HIGH_TOD_SECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0208, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_pp1s_latch_tsn0_high_tod_second_reg, + NULL, + NULL, + }, + { + "pp1s_latch_tsn0_fracnanosecond", + PTPTM_PTPTM_PP1S_LATCH_TSN0_FRACNANOSECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x020c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_pp1s_latch_tsn0_fracnanosecond_reg, + NULL, + NULL, + }, + { + "pp1s_latch_tsn1_tod_nanosecond", + PTPTM_PTPTM_PP1S_LATCH_TSN1_TOD_NANOSECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0210, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_pp1s_latch_tsn1_tod_nanosecond_reg, + NULL, + NULL, + }, + { + "pp1s_latch_tsn1_lower_tod_second", + PTPTM_PTPTM_PP1S_LATCH_TSN1_LOWER_TOD_SECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0214, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_pp1s_latch_tsn1_lower_tod_second_reg, + NULL, + NULL, + }, + { + "pp1s_latch_tsn1_high_tod_second", + PTPTM_PTPTM_PP1S_LATCH_TSN1_HIGH_TOD_SECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0218, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_pp1s_latch_tsn1_high_tod_second_reg, + NULL, + NULL, + }, + { + "pp1s_latch_tsn1_fracnanosecond", + PTPTM_PTPTM_PP1S_LATCH_TSN1_FRACNANOSECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x021c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_pp1s_latch_tsn1_fracnanosecond_reg, + NULL, + NULL, + }, + { + "pp1s_latch_tsn2_tod_nanosecond", + PTPTM_PTPTM_PP1S_LATCH_TSN2_TOD_NANOSECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0220, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_pp1s_latch_tsn2_tod_nanosecond_reg, + NULL, + NULL, + }, + { + "pp1s_latch_tsn2_lower_tod_second", + PTPTM_PTPTM_PP1S_LATCH_TSN2_LOWER_TOD_SECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0224, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_pp1s_latch_tsn2_lower_tod_second_reg, + NULL, + NULL, + }, + { + "pp1s_latch_tsn2_high_tod_second", + PTPTM_PTPTM_PP1S_LATCH_TSN2_HIGH_TOD_SECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0228, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_pp1s_latch_tsn2_high_tod_second_reg, + NULL, + NULL, + }, + { + "pp1s_latch_tsn2_fracnanosecond", + PTPTM_PTPTM_PP1S_LATCH_TSN2_FRACNANOSECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x022c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_pp1s_latch_tsn2_fracnanosecond_reg, + NULL, + NULL, + }, + { + "pp1s_latch_tsn3_tod_nanosecond", + PTPTM_PTPTM_PP1S_LATCH_TSN3_TOD_NANOSECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0230, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_pp1s_latch_tsn3_tod_nanosecond_reg, + NULL, + NULL, + }, + { + "pp1s_latch_tsn3_lower_tod_second", + PTPTM_PTPTM_PP1S_LATCH_TSN3_LOWER_TOD_SECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0234, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_pp1s_latch_tsn3_lower_tod_second_reg, + NULL, + NULL, + }, + { + "pp1s_latch_tsn3_high_tod_second", + PTPTM_PTPTM_PP1S_LATCH_TSN3_HIGH_TOD_SECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0238, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_pp1s_latch_tsn3_high_tod_second_reg, + NULL, + NULL, + }, + { + "pp1s_latch_tsn3_fracnanosecond", + PTPTM_PTPTM_PP1S_LATCH_TSN3_FRACNANOSECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x023c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_pp1s_latch_tsn3_fracnanosecond_reg, + NULL, + NULL, + }, + { + "tsn0_real_tod_nanosecond", + PTPTM_PTPTM_TSN0_REAL_TOD_NANOSECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0240, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_tsn0_real_tod_nanosecond_reg, + NULL, + NULL, + }, + { + "tsn0_real_lower_tod_second", + PTPTM_PTPTM_TSN0_REAL_LOWER_TOD_SECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0244, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_tsn0_real_lower_tod_second_reg, + NULL, + NULL, + }, + { + "tsn0_real_high_tod_second", + PTPTM_PTPTM_TSN0_REAL_HIGH_TOD_SECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0248, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_tsn0_real_high_tod_second_reg, + NULL, + NULL, + }, + { + "tsn1_real_tod_nanosecond", + PTPTM_PTPTM_TSN1_REAL_TOD_NANOSECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x024c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_tsn1_real_tod_nanosecond_reg, + NULL, + NULL, + }, + { + "tsn1_real_lower_tod_second", + PTPTM_PTPTM_TSN1_REAL_LOWER_TOD_SECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0250, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_tsn1_real_lower_tod_second_reg, + NULL, + NULL, + }, + { + "tsn1_real_high_tod_second", + PTPTM_PTPTM_TSN1_REAL_HIGH_TOD_SECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0254, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_tsn1_real_high_tod_second_reg, + NULL, + NULL, + }, + { + "tsn2_real_tod_nanosecond", + PTPTM_PTPTM_TSN2_REAL_TOD_NANOSECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0258, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_tsn2_real_tod_nanosecond_reg, + NULL, + NULL, + }, + { + "tsn2_real_lower_tod_second", + PTPTM_PTPTM_TSN2_REAL_LOWER_TOD_SECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x025c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_tsn2_real_lower_tod_second_reg, + NULL, + NULL, + }, + { + "tsn2_real_high_tod_second", + PTPTM_PTPTM_TSN2_REAL_HIGH_TOD_SECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0260, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_tsn2_real_high_tod_second_reg, + NULL, + NULL, + }, + { + "tsn3_real_tod_nanosecond", + PTPTM_PTPTM_TSN3_REAL_TOD_NANOSECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0264, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_tsn3_real_tod_nanosecond_reg, + NULL, + NULL, + }, + { + "tsn3_real_lower_tod_second", + PTPTM_PTPTM_TSN3_REAL_LOWER_TOD_SECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0268, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_tsn3_real_lower_tod_second_reg, + NULL, + NULL, + }, + { + "tsn3_real_high_tod_second", + PTPTM_PTPTM_TSN3_REAL_HIGH_TOD_SECONDr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x026c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_tsn3_real_high_tod_second_reg, + NULL, + NULL, + }, + { + "real_ptp_clock_cycle_integer", + PTPTM_PTPTM_REAL_PTP_CLOCK_CYCLE_INTEGERr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0280, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_real_ptp_clock_cycle_integer_reg, + NULL, + NULL, + }, + { + "real_ptp_clock_cycle_fraction", + PTPTM_PTPTM_REAL_PTP_CLOCK_CYCLE_FRACTIONr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0284, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_real_ptp_clock_cycle_fraction_reg, + NULL, + NULL, + }, + { + "real_tsn0_clock_cycle_integer", + PTPTM_PTPTM_REAL_TSN0_CLOCK_CYCLE_INTEGERr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0288, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_real_tsn0_clock_cycle_integer_reg, + NULL, + NULL, + }, + { + "real_tsn0_clock_cycle_fraction", + PTPTM_PTPTM_REAL_TSN0_CLOCK_CYCLE_FRACTIONr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x028c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_real_tsn0_clock_cycle_fraction_reg, + NULL, + NULL, + }, + { + "real_tsn1_clock_cycle_integer", + PTPTM_PTPTM_REAL_TSN1_CLOCK_CYCLE_INTEGERr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0290, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_real_tsn1_clock_cycle_integer_reg, + NULL, + NULL, + }, + { + "real_tsn1_clock_cycle_fraction", + PTPTM_PTPTM_REAL_TSN1_CLOCK_CYCLE_FRACTIONr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0294, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_real_tsn1_clock_cycle_fraction_reg, + NULL, + NULL, + }, + { + "real_tsn2_clock_cycle_integer", + PTPTM_PTPTM_REAL_TSN2_CLOCK_CYCLE_INTEGERr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x0298, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_real_tsn2_clock_cycle_integer_reg, + NULL, + NULL, + }, + { + "real_tsn2_clock_cycle_fraction", + PTPTM_PTPTM_REAL_TSN2_CLOCK_CYCLE_FRACTIONr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x029c, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_real_tsn2_clock_cycle_fraction_reg, + NULL, + NULL, + }, + { + "real_tsn3_clock_cycle_integer", + PTPTM_PTPTM_REAL_TSN3_CLOCK_CYCLE_INTEGERr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x02a0, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_real_tsn3_clock_cycle_integer_reg, + NULL, + NULL, + }, + { + "real_tsn3_clock_cycle_fraction", + PTPTM_PTPTM_REAL_TSN3_CLOCK_CYCLE_FRACTIONr, + PTPTM, + DPP_REG_FLAG_DIRECT, + DPP_REG_NUL_ARRAY, + SYS_PTP1_BASE_ADDR + 0x02a4, + (32/8), + 0, + 0, + 0, + 0, + 1, + g_ptptm_ptptm_real_tsn3_clock_cycle_fraction_reg, + NULL, + NULL, + }, +}; diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/table/Kbuild.include b/src/net/drivers/net/ethernet/dinghai/en_np/table/Kbuild.include new file mode 100644 index 0000000..9c4f663 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/table/Kbuild.include @@ -0,0 +1,4 @@ +cur_dir := en_np/table/ +subdirs := source/ +src_files += +include $(foreach subdir, $(subdirs), $(dinghai_root)/$(cur_dir)$(subdir)/Kbuild.include) \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_api.h b/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_api.h new file mode 100644 index 0000000..4ebda14 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_api.h @@ -0,0 +1,172 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_tbl_api.h +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : +* 完成日期 : 2014/01/27 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ + +#ifndef DPP_TBL_API_H +#define DPP_TBL_API_H + +#include "zxic_common.h" +#include "dpp_drv_eram.h" +#include "dpp_tbl_comm.h" + +#define EGR_FLAG_TPID ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, tpid) / sizeof(ZXIC_UINT32))) +#define EGR_FLAG_VHCA ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, vhca) / sizeof(ZXIC_UINT32))) +#define EGR_FLAG_UPLINK_PORT ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, uplink_port) / sizeof(ZXIC_UINT32))) +#define EGR_FLAG_RSS_HASH_FACTOR ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, rss_hash_factor) / sizeof(ZXIC_UINT32))) +#define EGR_FLAG_HASH_ALG ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, hash_alg) / sizeof(ZXIC_UINT32))) +#define EGR_FLAG_PANEL_ID ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, panel_id) / sizeof(ZXIC_UINT32))) +#define EGR_FLAG_LAG_ID ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, lag_id) / sizeof(ZXIC_UINT32))) +#define EGR_FLAG_PF_VQM_VFID ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, pf_vqm_vfid) / sizeof(ZXIC_UINT32))) +#define EGR_FLAG_MTU ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, mtu) / sizeof(ZXIC_UINT32))) +#define EGR_FLAG_HASH_SEARCH_INDEX ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, hash_search_index) / sizeof(ZXIC_UINT32))) +#define EGR_FLAG_PORT_BASE_QID ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, port_base_qid) / sizeof(ZXIC_UINT32))) +#define EGR_FLAG_FD_EN_OFF ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, fd_enable) / sizeof(ZXIC_UINT32))) +#define EGR_FLAG_TM_EN_OFF ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, tm_enable) / sizeof(ZXIC_UINT32))) +#define EGR_FLAG_INGRESS_METER_EN_OFF ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, ingress_meter_enable) / sizeof(ZXIC_UINT32))) +#define EGR_FLAG_EGRESS_METER_EN_OFF ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, egress_meter_enable) / sizeof(ZXIC_UINT32))) +#define EGR_FLAG_INGRESS_MODE ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, ingress_meter_mode) / sizeof(ZXIC_UINT32))) +#define EGR_FLAG_EGRESS_MODE ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, egress_meter_mode) / sizeof(ZXIC_UINT32))) +#define EGR_FLAG_VEPA_EN_OFF ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, vepa_enable) / sizeof(ZXIC_UINT32))) +#define EGR_FLAG_SPOOFCHK_EN_OFF ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, spoof_check_enable) / sizeof(ZXIC_UINT32))) +#define EGR_FLAG_INLINE_SEC_OFFLOAD ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, inline_sec_offload) / sizeof(ZXIC_UINT32))) +#define EGR_FLAG_OVS_EN_OFF ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, ovs_enable) / sizeof(ZXIC_UINT32))) +#define EGR_FLAG_LAG_EN_OFF ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, lag_enable) / sizeof(ZXIC_UINT32))) +#define EGR_FLAG_IS_PASSTHROUGH ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, is_passthrough) / sizeof(ZXIC_UINT32))) +#define EGR_FLAG_IS_VF ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, is_vf) / sizeof(ZXIC_UINT32))) +#define EGR_FLAG_VIRTION_VERSION ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, virtion_version) / sizeof(ZXIC_UINT32))) +#define EGR_FLAG_VIRTION_EN_OFF ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, virtio_enable) / sizeof(ZXIC_UINT32))) +#define EGR_FLAG_ACCELERATOR_OFFLOAD_FLAG ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, accelerator_offload_flag) / sizeof(ZXIC_UINT32))) +#define EGR_FLAG_IPV4_TCP_ASSEMBLE ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, lro_offload) / sizeof(ZXIC_UINT32))) +#define EGR_FLAG_IPV6_TCP_ASSEMBLE ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, lro_offload) / sizeof(ZXIC_UINT32))) +#define EGR_FLAG_IP_FRAGMENT_OFFLOAD ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, ip_fragment_offload) / sizeof(ZXIC_UINT32))) +#define EGR_FLAG_TCP_UDP_CHKSUM ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, tcp_udp_checksum_offload) / sizeof(ZXIC_UINT32))) +#define EGR_FLAG_IP_CHKSUM ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, ip_checksum_offload) / sizeof(ZXIC_UINT32))) +#define EGR_FLAG_OUTER_IP_CHECKSUM_OFFLOAD ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, outer_ip_checksum_offload) / sizeof(ZXIC_UINT32))) +#define EGR_FLAG_VPORT_IS_UP ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, is_up) / sizeof(ZXIC_UINT32))) +#define EGR_FLAG_IFF_ALLMULTI_EN_OFF ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, allmulticast_enable) / sizeof(ZXIC_UINT32))) +#define EGR_FLAG_HW_BOND_EN_OFF ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, hw_bond_enable) / sizeof(ZXIC_UINT32))) +#define EGR_FLAG_RDMA_OFFLOAD_EN_OFF ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, rdma_offload_enable) / sizeof(ZXIC_UINT32))) +#define EGR_FLAG_VLAN_FILTER_EN_OFF ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, vlan_filter_enable) / sizeof(ZXIC_UINT32))) +#define EGR_FLAG_VLAN_STRIP_OFFLOAD ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, vlan_strip_offload) / sizeof(ZXIC_UINT32))) +#define EGR_FLAG_QINQ_VLAN_STRIP_OFFLOAD ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, qinq_vlan_strip_offload) / sizeof(ZXIC_UINT32))) +#define EGR_FLAG_RSS_EN_OFF ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, rss_enable) / sizeof(ZXIC_UINT32))) +#define EGR_FLAG_MTU_OFFLOAD_EN_OFF ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, mtu_offload_enable) / sizeof(ZXIC_UINT32))) + +#define PANEL_FLAG_OVS_PF_VFID ((ZXIC_UINT32)(offsetof(ZXDH_PANEL_PORT_T, ovs_pf_vfid) / sizeof(ZXIC_UINT32))) +#define PANEL_FLAG_PF_MEMPORT_QID ((ZXIC_UINT32)(offsetof(ZXDH_PANEL_PORT_T, pf_memport_qid) / sizeof(ZXIC_UINT32))) +#define PANEL_FLAG_BOND_PF_VQM_VFID ((ZXIC_UINT32)(offsetof(ZXDH_PANEL_PORT_T, bond_pf_vqm_vfid) / sizeof(ZXIC_UINT32))) +#define PANEL_FLAG_IS_UP ((ZXIC_UINT32)(offsetof(ZXDH_PANEL_PORT_T, is_up) / sizeof(ZXIC_UINT32))) +#define PANEL_FLAG_BOND_LINK_UP ((ZXIC_UINT32)(offsetof(ZXDH_PANEL_PORT_T, bond_link_up) / sizeof(ZXIC_UINT32))) +#define PANEL_FLAG_HW_BOND_ENABLE ((ZXIC_UINT32)(offsetof(ZXDH_PANEL_PORT_T, hw_bond_enable) / sizeof(ZXIC_UINT32))) +#define PANEL_FLAG_MTU ((ZXIC_UINT32)(offsetof(ZXDH_PANEL_PORT_T, mtu) / sizeof(ZXIC_UINT32))) +#define PANEL_FLAG_MTU_OFFLOAD_ENABLE ((ZXIC_UINT32)(offsetof(ZXDH_PANEL_PORT_T, mtu_offload_enable) / sizeof(ZXIC_UINT32))) +#define PANEL_FLAG_TM_BASE_QUEUE ((ZXIC_UINT32)(offsetof(ZXDH_PANEL_PORT_T, tm_base_queue) / sizeof(ZXIC_UINT32))) +#define PANEL_FLAG_PTP_PORT_VFID ((ZXIC_UINT32)(offsetof(ZXDH_PANEL_PORT_T, ptp_port_vfid) / sizeof(ZXIC_UINT32))) +#define PANEL_FLAG_PF_VQM_VFID ((ZXIC_UINT32)(offsetof(ZXDH_PANEL_PORT_T, pf_vqm_vfid) / sizeof(ZXIC_UINT32))) +#define PANEL_FLAG_TM_SHAPE_ENABLE ((ZXIC_UINT32)(offsetof(ZXDH_PANEL_PORT_T, tm_shape_enable) / sizeof(ZXIC_UINT32))) +#define PANEL_FLAG_PTP_TC_ENABLE ((ZXIC_UINT32)(offsetof(ZXDH_PANEL_PORT_T, ptp_tc_enable) / sizeof(ZXIC_UINT32))) +#define PANEL_FLAG_TRUST_MODE ((ZXIC_UINT32)(offsetof(ZXDH_PANEL_PORT_T, trust_mode) / sizeof(ZXIC_UINT32))) + +ZXIC_UINT32 dpp_vport_create(DPP_PF_INFO_T* pf_info); +ZXIC_UINT32 dpp_vport_create_by_vqm_vfid(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 vqm_vfid); +ZXIC_UINT32 dpp_vport_delete(DPP_PF_INFO_T* pf_info); +ZXIC_UINT32 dpp_egr_port_attr_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 attr, ZXIC_UINT32 value); +ZXIC_UINT32 dpp_egr_port_attr_get(DPP_PF_INFO_T* pf_info, ZXDH_VPORT_T *port_attr_entry); +ZXIC_UINT32 dpp_rx_flow_hash_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 hash_mode); +ZXIC_UINT32 dpp_rx_flow_hash_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 *hash_mode); +ZXIC_UINT32 dpp_vport_hash_index_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 *hash_index); +ZXIC_UINT32 dpp_vport_hash_funcs_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 funcs); +ZXIC_UINT32 dpp_vport_rss_en_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 enable); +ZXIC_UINT32 dpp_vport_virtio_en_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 enable); +ZXIC_UINT32 dpp_vport_virtio_version_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 version); +ZXIC_UINT32 dpp_vport_vlan_filter_en_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 enable); +ZXIC_UINT32 dpp_vport_vlan_qinq_en_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 enable); +ZXIC_UINT32 dpp_vport_vlan_strip_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 enable); + +ZXIC_UINT32 dpp_vlan_filter_init(DPP_PF_INFO_T* pf_info); +ZXIC_UINT32 dpp_add_vlan_filter(DPP_PF_INFO_T* pf_info, ZXIC_UINT16 vlan_id); +ZXIC_UINT32 dpp_del_vlan_filter(DPP_PF_INFO_T* pf_info, ZXIC_UINT16 vlan_id); + +ZXIC_UINT32 dpp_vport_bond_pf(DPP_PF_INFO_T* pf_info); +ZXIC_UINT32 dpp_vport_unbond_pf(DPP_PF_INFO_T* pf_info); + +ZXIC_UINT32 dpp_rxfh_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 *queue_list, ZXIC_UINT32 queue_num); +ZXIC_UINT32 dpp_rxfh_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 *queue_list, ZXIC_UINT32 queue_num); +ZXIC_UINT32 dpp_rxfh_del(DPP_PF_INFO_T* pf_info); +ZXIC_UINT32 dpp_thash_key_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 *hash_key, ZXIC_UINT32 key_num); +ZXIC_UINT32 dpp_thash_key_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 *hash_key, ZXIC_UINT32 key_num); + +ZXIC_UINT32 dpp_add_mac(DPP_PF_INFO_T* pf_info, ZXIC_CONST ZXIC_VOID *mac); +ZXIC_UINT32 dpp_del_mac(DPP_PF_INFO_T* pf_info, ZXIC_CONST ZXIC_VOID *mac); +ZXIC_UINT32 dpp_unicast_mac_dump(DPP_PF_INFO_T* pf_info, MAC_VPORT_INFO *p_mac_arr, ZXIC_UINT32 *p_mac_num); +ZXIC_UINT32 dpp_unicast_all_mac_delete(DPP_PF_INFO_T* pf_info); +ZXIC_UINT32 dpp_unicast_all_mac_online_delete(DPP_PF_INFO_T* pf_info); + +ZXIC_UINT32 dpp_multi_mac_add_member(DPP_PF_INFO_T* pf_info, ZXIC_CONST ZXIC_VOID *mac); +ZXIC_UINT32 dpp_multi_mac_del_member(DPP_PF_INFO_T* pf_info, ZXIC_CONST ZXIC_VOID *mac); +ZXIC_UINT32 dpp_multicast_mac_dump(DPP_PF_INFO_T* pf_info, MAC_VPORT_INFO *p_mac_arr, ZXIC_UINT32 *p_mac_num); +ZXIC_UINT32 dpp_multicast_all_mac_delete(DPP_PF_INFO_T* pf_info); +ZXIC_UINT32 dpp_multicast_all_mac_online_delete(DPP_PF_INFO_T* pf_info); + +ZXIC_UINT32 dpp_ptp_port_vfid_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 ptp_port_vfid); +ZXIC_UINT32 dpp_ptp_tc_enable_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 ptp_tc_enable); + +ZXIC_UINT32 dpp_ipsec_enc_entry_add(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT8 *sip, ZXIC_UINT8 *dip, + ZXIC_UINT8 *sip_mask, ZXIC_UINT8 *dip_mask, ZXIC_UINT32 is_ipv4, ZXIC_UINT32 sa_id); +ZXIC_UINT32 dpp_ipsec_enc_entry_del(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index); + +ZXIC_UINT32 dpp_lag_group_create(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 lag_id); +ZXIC_UINT32 dpp_lag_group_delete(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 lag_id); +ZXIC_UINT32 dpp_lag_mode_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 lag_id, ZXIC_UINT8 mode); +ZXIC_UINT32 dpp_lag_group_hash_factor_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 lag_id, ZXIC_UINT8 factor); +ZXIC_UINT32 dpp_lag_group_member_add(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 lag_id, ZXIC_UINT8 panel_id); +ZXIC_UINT32 dpp_lag_group_member_del(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 lag_id, ZXIC_UINT8 panel_id); + +ZXIC_UINT32 dpp_panel_bond_vport(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 panel_id); +ZXIC_UINT32 dpp_panel_hardware_bond_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 panel_id, ZXIC_UINT8 enable); +ZXIC_UINT32 dpp_panel_bond_pf_vqm_vfid_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 panel_id, ZXIC_UINT16 vqm_vfid); +ZXIC_UINT32 dpp_panel_bond_pf_memport_qid_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 panel_id, ZXIC_UINT16 qid); +ZXIC_UINT32 dpp_panel_ovs_pf_vqm_vfid_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 panel_id, ZXIC_UINT16 vqm_vfid); +ZXIC_UINT32 dpp_panel_attr_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 panel_id, ZXIC_UINT32 attr, ZXIC_UINT32 value); + +ZXIC_UINT32 dpp_vport_uc_promisc_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 enable); +ZXIC_UINT32 dpp_vport_mc_promisc_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 enable); + +ZXIC_UINT32 dpp_stat_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_cnt); +ZXIC_UINT32 dpp_stat_cnt_get_128(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_pkB_cnt, ZXIC_UINT64 *p_pk_cnt); +ZXIC_UINT32 dpp_stat_mc_packet_rx_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_cnt); +ZXIC_UINT32 dpp_stat_bc_packet_rx_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_cnt); +ZXIC_UINT32 dpp_stat_1588_packet_rx_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_cnt); +ZXIC_UINT32 dpp_stat_1588_packet_tx_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_cnt); +ZXIC_UINT32 dpp_stat_1588_packet_drop_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_cnt); +ZXIC_UINT32 dpp_stat_1588_enc_packet_rx_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_cnt); +ZXIC_UINT32 dpp_stat_1588_enc_packet_tx_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_cnt); +ZXIC_UINT32 dpp_stat_spoof_packet_drop_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_cnt); +ZXIC_UINT32 dpp_stat_mcode_packet_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_cnt); +ZXIC_UINT32 dpp_stat_port_bc_packet_tx_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_cnt); +ZXIC_UINT32 dpp_stat_port_bc_packet_rx_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_cnt); +ZXIC_UINT32 dpp_stat_port_RDMA_packet_msg_tx_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_pkB_cnt, ZXIC_UINT64 *p_pk_cnt); +ZXIC_UINT32 dpp_stat_port_RDMA_packet_msg_rx_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_pkB_cnt, ZXIC_UINT64 *p_pk_cnt); +ZXIC_UINT32 dpp_stat_plcr_packet_drop_tx_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_pkB_cnt, ZXIC_UINT64 *p_pk_cnt); +ZXIC_UINT32 dpp_stat_plcr_packet_drop_rx_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_pkB_cnt, ZXIC_UINT64 *p_pk_cnt); +ZXIC_UINT32 dpp_stat_MTU_packet_msg_tx_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_pkB_cnt, ZXIC_UINT64 *p_pk_cnt); +ZXIC_UINT32 dpp_stat_MTU_packet_msg_rx_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_pkB_cnt, ZXIC_UINT64 *p_pk_cnt); + +ZXIC_UINT32 dpp_vport_vhca_id_add(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 vhca_id); +ZXIC_UINT32 dpp_vport_vhca_id_del(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 vhca_id); +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_bc.h b/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_bc.h new file mode 100644 index 0000000..01f42cc --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_bc.h @@ -0,0 +1,39 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_tbl_bc.h +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : +* 完成日期 : 2014/01/27 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ + +#ifndef DPP_TBL_BC_H +#define DPP_TBL_BC_H + +#include "zxic_common.h" +#include "dpp_type_api.h" + +#define BC_GROUP_NUM (4) +#define BC_MEMBER_NUM_IN_GROUP (64) + +typedef struct dpp_vport_bc_info_t +{ + ZXIC_UINT64 bc_bitmap[BC_GROUP_NUM]; +} DPP_VPORT_BC_INFO_T; + +typedef struct dpp_vport_bc_table_t +{ + DPP_VPORT_BC_INFO_T bc_info; +} DPP_VPORT_BC_TABLE_T; + +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_comm.h b/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_comm.h new file mode 100644 index 0000000..7e6852f --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_comm.h @@ -0,0 +1,79 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_tbl_comm.h +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : +* 完成日期 : 2014/01/27 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ + +#ifndef DPP_TBL_COMM_H +#define DPP_TBL_COMM_H + +#include "zxic_common.h" +#include "dpp_type_api.h" +#include "dpp_tbl_mc.h" +#include "dpp_tbl_mac.h" +#include "dpp_tbl_qid.h" +#include "dpp_tbl_port.h" +#include "dpp_tbl_bc.h" +#include "dpp_tbl_promisc.h" + +#define VF_ACTIVE(VPORT) ((VPORT & 0x0800) >> 11) +#define EPID(VPORT) ((VPORT & 0x7000) >> 12) +#define FUNC_NUM(VPORT) ((VPORT & 0x0700) >> 8) +#define VFUNC_NUM(VPORT) ((VPORT & 0x00FF)) + +#define PF_VQM_VFID_OFFSET (1152) +#define IS_PF(VPORT) (!VF_ACTIVE(VPORT)) +#define VQM_VFID(VPORT) (IS_PF(VPORT) ? \ + (PF_VQM_VFID_OFFSET + (EPID(VPORT) * 8) + FUNC_NUM(VPORT)) : \ + ((EPID(VPORT) * 256) + VFUNC_NUM(VPORT))) + +#define OWNER_PF_VQM_VFID(VPORT) (PF_VQM_VFID_OFFSET + (EPID(VPORT) * 8) + FUNC_NUM(VPORT)) +#define OWNER_PF_VPORT(VPORT) (((EPID(VPORT)) << 12) | ((FUNC_NUM(VPORT)) << 8)) + +#define VQM_VFID_MAX_NUM (2048) + +typedef struct dpp_vport_mgr_t +{ + DPP_VPORT_BC_TABLE_T bc_table; + DPP_VPORT_MC_TABLE_T mc_table; + DPP_VPORT_PROMISC_TABLE_T uc_promisc_table; + DPP_VPORT_PROMISC_TABLE_T mc_promisc_table; +} DPP_VPORT_MGR_T; + +typedef struct +{ + uint8_t addr[6]; + uint16_t vport; +}MAC_VPORT_INFO; + +typedef struct +{ + uint8_t mc_addr[6]; + uint16_t pf_flag; +}MC_PF_FLAG_MGR; + +ZXIC_UINT32 dpp_data_print(ZXIC_UINT8 *data, ZXIC_UINT32 len); +ZXIC_UINT32 dpp_vport_attr_value_show(ZXIC_VOID); +ZXIC_UINT32 dpp_vport_mgr_init(DPP_PF_INFO_T* pf_info); +ZXIC_UINT32 dpp_vport_mgr_release(DPP_PF_INFO_T* pf_info); +ZXIC_UINT32 dpp_vport_bc_table_get(DPP_PF_INFO_T* pf_info, DPP_VPORT_BC_TABLE_T** bc_table); +ZXIC_UINT32 dpp_vport_mc_table_get(DPP_PF_INFO_T* pf_info, DPP_VPORT_MC_TABLE_T** mc_table); +ZXIC_UINT32 dpp_vport_uc_promisc_table_get(DPP_PF_INFO_T* pf_info, DPP_VPORT_PROMISC_TABLE_T** promisc_table); +ZXIC_UINT32 dpp_vport_mc_promisc_table_get(DPP_PF_INFO_T* pf_info, DPP_VPORT_PROMISC_TABLE_T** promisc_table); +ZXIC_UINT32 dpp_vport_get_by_vqm_vfid(ZXIC_UINT16 pf_vport, ZXIC_UINT32 vqm_vfid, ZXIC_UINT16* vport); +ZXIC_UINT32 dpp_vport_get_by_mc_bitmap(ZXIC_UINT16 pf_vport, ZXIC_UINT32 group_id, ZXIC_UINT64 mc_bitmap, ZXIC_UINT16 vport[64], ZXIC_UINT32* vport_num); + +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_diag.h b/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_diag.h new file mode 100644 index 0000000..e2c609d --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_diag.h @@ -0,0 +1,56 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_tbl_diag.h +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : +* 完成日期 : 2014/01/27 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ + +#ifndef DPP_TBL_DIAG_H +#define DPP_TBL_DIAG_H + +#include "zxic_common.h" +#include "dpp_type_api.h" + +ZXIC_CONST ZXIC_CHAR* dpp_vport_table_attr_name_get(ZXIC_UINT32 attr); +ZXIC_CONST ZXIC_CHAR* dpp_vport_panel_table_attr_name_get(ZXIC_UINT32 attr); + +ZXIC_UINT32 diag_dpp_vport_mac_add(ZXIC_UINT16 slot, ZXIC_UINT16 vport, + ZXIC_UINT8 mac0, ZXIC_UINT8 mac1, ZXIC_UINT8 mac2, + ZXIC_UINT8 mac3, ZXIC_UINT8 mac4, ZXIC_UINT8 mac5); +ZXIC_UINT32 diag_dpp_vport_mac_del(ZXIC_UINT16 slot, ZXIC_UINT16 vport, + ZXIC_UINT8 mac0, ZXIC_UINT8 mac1, ZXIC_UINT8 mac2, + ZXIC_UINT8 mac3, ZXIC_UINT8 mac4, ZXIC_UINT8 mac5); +ZXIC_UINT32 diag_dpp_vport_mac_prt(ZXIC_UINT16 slot, ZXIC_UINT16 vport); +ZXIC_UINT32 diag_dpp_vport_mc_mac_add(ZXIC_UINT16 slot, ZXIC_UINT16 vport, + ZXIC_UINT8 mac0, ZXIC_UINT8 mac1, ZXIC_UINT8 mac2, + ZXIC_UINT8 mac3, ZXIC_UINT8 mac4, ZXIC_UINT8 mac5); +ZXIC_UINT32 diag_dpp_vport_mc_mac_del(ZXIC_UINT16 slot, ZXIC_UINT16 vport, + ZXIC_UINT8 mac0, ZXIC_UINT8 mac1, ZXIC_UINT8 mac2, + ZXIC_UINT8 mac3, ZXIC_UINT8 mac4, ZXIC_UINT8 mac5); +ZXIC_UINT32 diag_dpp_vport_mc_mac_prt(ZXIC_UINT16 slot, ZXIC_UINT16 vport); +ZXIC_UINT32 diag_dpp_vport_table_set(ZXIC_UINT16 slot, ZXIC_UINT16 vport, ZXIC_UINT32 attr, + ZXIC_UINT32 value); +ZXIC_UINT32 diag_dpp_vport_table_prt(ZXIC_UINT16 slot, ZXIC_UINT16 vport); +ZXIC_UINT32 diag_dpp_vport_panel_table_set(ZXIC_UINT16 slot, ZXIC_UINT16 vport, ZXIC_UINT8 panel_id, + ZXIC_UINT32 attr, ZXIC_UINT32 value); +ZXIC_UINT32 diag_dpp_vport_panel_table_prt(ZXIC_UINT16 slot, ZXIC_UINT16 vport, ZXIC_UINT8 panel_id); +ZXIC_UINT32 diag_dpp_vport_bc_table_set(ZXIC_UINT16 slot, ZXIC_UINT16 vport, ZXIC_UINT32 enable); +ZXIC_UINT32 diag_dpp_vport_bc_table_prt(ZXIC_UINT16 slot, ZXIC_UINT16 vport); +ZXIC_UINT32 diag_dpp_vport_uc_promisc_table_set(ZXIC_UINT16 slot, ZXIC_UINT16 vport, ZXIC_UINT32 enable); +ZXIC_UINT32 diag_dpp_vport_uc_promisc_table_prt(ZXIC_UINT16 slot, ZXIC_UINT16 vport); +ZXIC_UINT32 diag_dpp_vport_mc_promisc_table_set(ZXIC_UINT16 slot, ZXIC_UINT16 vport, ZXIC_UINT32 enable); +ZXIC_UINT32 diag_dpp_vport_mc_promisc_table_prt(ZXIC_UINT16 slot, ZXIC_UINT16 vport); + +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_ipsec.h b/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_ipsec.h new file mode 100644 index 0000000..b08438e --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_ipsec.h @@ -0,0 +1,26 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_tbl_ipsec.h +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : +* 完成日期 : 2014/01/27 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ + +#ifndef DPP_TBL_IPSEC_H +#define DPP_TBL_IPSEC_H + +#include "zxic_common.h" +#include "dpp_type_api.h" + +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_lag.h b/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_lag.h new file mode 100644 index 0000000..0238159 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_lag.h @@ -0,0 +1,29 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_tbl_lag.h +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : +* 完成日期 : 2014/01/27 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ + +#ifndef DPP_TBL_LAG_H +#define DPP_TBL_LAG_H + +#include "zxic_common.h" +#include "dpp_type_api.h" + +#define LAG_LACP_MODE (2) +#define LAG_STANDBY_MODE (1) + +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_mac.h b/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_mac.h new file mode 100644 index 0000000..1eeea0a --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_mac.h @@ -0,0 +1,26 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_tbl_mac.h +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : +* 完成日期 : 2014/01/27 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ + +#ifndef DPP_TBL_MAC_H +#define DPP_TBL_MAC_H + +#include "zxic_common.h" +#include "dpp_type_api.h" + +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_mc.h b/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_mc.h new file mode 100644 index 0000000..97a354b --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_mc.h @@ -0,0 +1,43 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_tbl_mc.h +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : +* 完成日期 : 2014/01/27 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ + +#ifndef DPP_TBL_MC_H +#define DPP_TBL_MC_H + +#include "zxic_common.h" +#include "dpp_type_api.h" + +#define MC_TABLE_SIZE (32) +#define MC_GROUP_NUM (4) +#define MC_MEMBER_NUM_IN_GROUP (64) + +typedef struct dpp_vport_mc_info_t +{ + ZXIC_UINT32 is_valid; + ZXIC_UINT8 mac[6]; + ZXIC_UINT32 mc_pf_enable; + ZXIC_UINT64 mc_bitmap[MC_GROUP_NUM]; +} DPP_VPORT_MC_INFO_T; + +typedef struct dpp_vport_mc_table_t +{ + DPP_VPORT_MC_INFO_T mc_info[MC_TABLE_SIZE]; +} DPP_VPORT_MC_TABLE_T; + +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_panel.h b/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_panel.h new file mode 100644 index 0000000..0936a09 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_panel.h @@ -0,0 +1,26 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_tbl_panel.h +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : +* 完成日期 : 2014/01/27 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ + +#ifndef DPP_TBL_PANEL_H +#define DPP_TBL_PANEL_H + +#include "zxic_common.h" +#include "dpp_type_api.h" + +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_port.h b/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_port.h new file mode 100644 index 0000000..af21260 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_port.h @@ -0,0 +1,26 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_tbl_port.h +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : +* 完成日期 : 2014/01/27 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ + +#ifndef DPP_TBL_PORT_H +#define DPP_TBL_PORT_H + +#include "zxic_common.h" +#include "dpp_type_api.h" + +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_promisc.h b/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_promisc.h new file mode 100644 index 0000000..e97a7c7 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_promisc.h @@ -0,0 +1,40 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_tbl_promisc.h +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : +* 完成日期 : 2014/01/27 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ + +#ifndef DPP_TBL_PROMISC_H +#define DPP_TBL_PROMISC_H + +#include "zxic_common.h" +#include "dpp_type_api.h" + +#define PROMISC_GROUP_NUM (4) +#define PROMISC_MEMBER_NUM_IN_GROUP (64) + +typedef struct dpp_vport_promisc_info_t +{ + ZXIC_UINT32 pf_enable; + ZXIC_UINT64 bitmap[PROMISC_GROUP_NUM]; +} DPP_VPORT_PROMISC_INFO_T; + +typedef struct dpp_vport_uc_promisc_table_t +{ + DPP_VPORT_PROMISC_INFO_T promisc_info; +} DPP_VPORT_PROMISC_TABLE_T; + +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_ptp.h b/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_ptp.h new file mode 100644 index 0000000..eca6ec5 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_ptp.h @@ -0,0 +1,26 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_tbl_port.h +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : +* 完成日期 : 2014/01/27 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ + +#ifndef DPP_TBL_PTP_H +#define DPP_TBL_PTP_H + +#include "zxic_common.h" +#include "dpp_type_api.h" + +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_qid.h b/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_qid.h new file mode 100644 index 0000000..b233da2 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_qid.h @@ -0,0 +1,28 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_tbl_qid.h +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : +* 完成日期 : 2014/01/27 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ + +#ifndef DPP_TBL_QID_H +#define DPP_TBL_QID_H + +#include "zxic_common.h" +#include "dpp_type_api.h" + +#define RSS_TO_VQID_GROUP_NUM (32) + +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_stat.h b/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_stat.h new file mode 100644 index 0000000..4a18728 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_stat.h @@ -0,0 +1,77 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_tbl_stat.h +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : +* 完成日期 : 2014/01/27 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ + +#ifndef DPP_TBL_STAT_H +#define DPP_TBL_STAT_H + +#include "zxic_common.h" +#include "dpp_type_api.h" + +#define DPP_STAT_MC_PACKET_RX_CNT_ERAM_BAADDR ((ZXIC_UINT32)(0x1A)) +#define DPP_STAT_MC_PACKET_RX_CNT_ERAM_DEPTH ((ZXIC_UINT32)(40)) + +#define DPP_STAT_BC_PACKET_RX_CNT_ERAM_BAADDR ((ZXIC_UINT32)(0x42)) +#define DPP_STAT_BC_PACKET_RX_CNT_ERAM_DEPTH ((ZXIC_UINT32)(40 * 1024)) + +#define DPP_STAT_1588_PACKET_RX_CNT_ERAM_BAADDR ((ZXIC_UINT32)(0xA042)) +#define DPP_STAT_1588_PACKET_RX_CNT_ERAM_DEPTH ((ZXIC_UINT32)(0x800)) + +#define DPP_STAT_1588_PACKET_TX_CNT_ERAM_BAADDR ((ZXIC_UINT32)(0xA842)) +#define DPP_STAT_1588_PACKET_TX_CNT_ERAM_DEPTH ((ZXIC_UINT32)(0x800)) + +#define DPP_STAT_1588_PACKET_DROP_CNT_ERAM_BAADDR ((ZXIC_UINT32)(0xB042)) +#define DPP_STAT_1588_PACKET_DROP_CNT_ERAM_DEPTH ((ZXIC_UINT32)(0x800)) + +#define DPP_STAT_1588_ENC_PACKET_RX_CNT_ERAM_BAADDR ((ZXIC_UINT32)(0xC042)) +#define DPP_STAT_1588_ENC_PACKET_RX_CNT_ERAM_DEPTH ((ZXIC_UINT32)(0x800)) + +#define DPP_STAT_1588_ENC_PACKET_TX_CNT_ERAM_BAADDR ((ZXIC_UINT32)(0xB842)) +#define DPP_STAT_1588_ENC_PACKET_TX_CNT_ERAM_DEPTH ((ZXIC_UINT32)(0x800)) + +#define DPP_STAT_SPOOF_PACKET_DROP_CNT_ERAM_BAADDR ((ZXIC_UINT32)(0xC842)) +#define DPP_STAT_SPOOF_PACKET_DROP_CNT_ERAM_DEPTH ((ZXIC_UINT32)(0x40)) + +#define DPP_STAT_MCODE_PACKET_CNT_ERAM_BAADDR ((ZXIC_UINT32)(0xC882)) +#define DPP_STAT_MCODE_PACKET_CNT_ERAM_DEPTH ((ZXIC_UINT32)(0x80)) + +#define DPP_STAT_PORT_BC_PACKET_TX_CNT_ERAM_BAADDR ((ZXIC_UINT32)(0xC902)) +#define DPP_STAT_PORT_BC_PACKET_TX_CNT_ERAM_DEPTH ((ZXIC_UINT32)(0x800)) + +#define DPP_STAT_PORT_BC_PACKET_RX_CNT_ERAM_BAADDR ((ZXIC_UINT32)(0xD102)) +#define DPP_STAT_PORT_BC_PACKET_RX_CNT_ERAM_DEPTH ((ZXIC_UINT32)(0x800)) + +#define DPP_STAT_PORT_RDMA_PACKET_TX_CNT_ERAM_BAADDR ((ZXIC_UINT32)(0x6C81)) // 128bit +#define DPP_STAT_PORT_RDMA_PACKET_TX_CNT_ERAM_DEPTH ((ZXIC_UINT32)(0x400)) + +#define DPP_STAT_PORT_RDMA_PACKET_RX_CNT_ERAM_BAADDR ((ZXIC_UINT32)(0x7081)) // 128bit +#define DPP_STAT_PORT_RDMA_PACKET_RX_CNT_ERAM_DEPTH ((ZXIC_UINT32)(0x400)) + +#define DPP_STAT_PLCR_PACKET_DROP_TX_CNT_ERAM_BAADDR ((ZXIC_UINT32)(0x7481)) +#define DPP_STAT_PLCR_PACKET_DROP_TX_CNT_ERAM_DEPTH ((ZXIC_UINT32)(0x800)) + +#define DPP_STAT_PLCR_PACKET_DROP_RX_CNT_ERAM_BAADDR ((ZXIC_UINT32)(0x7C81)) +#define DPP_STAT_PLCR_PACKET_DROP_RX_CNT_ERAM_DEPTH ((ZXIC_UINT32)(0x800)) + +#define DPP_STAT_MTU_PACKET_DROP_TX_CNT_ERAM_BAADDR ((ZXIC_UINT32)(0x8481)) // 128bit +#define DPP_STAT_MTU_PACKET_DROP_TX_CNT_ERAM_DEPTH ((ZXIC_UINT32)(0x500)) + +#define DPP_STAT_MTU_PACKET_DROP_RX_CNT_ERAM_BAADDR ((ZXIC_UINT32)(0x8981)) // 128bit +#define DPP_STAT_MTU_PACKET_DROP_RX_CNT_ERAM_DEPTH ((ZXIC_UINT32)(0x500)) + +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_tm.h b/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_tm.h new file mode 100644 index 0000000..88b215a --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_tm.h @@ -0,0 +1,45 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_tbl_tm.h +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : +* 完成日期 : 2014/01/27 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ + +#ifndef DPP_TBL_TM_H +#define DPP_TBL_TM_H + +#include "zxic_common.h" +#include "dpp_type_api.h" +#include "dpp_dev.h" + +#define TM_BASE_QUEUE_VALID (0x1000) +#define TRUST_MODE_VALID (0x10) +#define UP_VALID (0x10) +#define TC_VALID (0x10) +#define TM_SWITCH_ON (1) +#define TM_SWITCH_OFF (0) + +ZXIC_UINT32 dpp_tm_flowid_pport_table_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 port, ZXIC_UINT32 flow_id); +ZXIC_UINT32 dpp_tm_flowid_pport_table_del(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 port); +ZXIC_UINT32 dpp_tm_pport_trust_mode_table_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 port, ZXIC_UINT32 mode); +ZXIC_UINT32 dpp_tm_pport_trust_mode_table_del(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 port); +ZXIC_UINT32 dpp_tm_pport_dscp_map_table_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 port, ZXIC_UINT32 dscp_id, ZXIC_UINT32 up_id); +ZXIC_UINT32 dpp_tm_pport_dscp_map_table_del(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 port, ZXIC_UINT32 dscp_id); +ZXIC_UINT32 dpp_tm_pport_up_map_table_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 port, ZXIC_UINT32 up_id, ZXIC_UINT32 tc_id); +ZXIC_UINT32 dpp_tm_pport_up_map_table_del(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 port, ZXIC_UINT32 up_id); +ZXIC_UINT32 dpp_tm_pport_mcode_switch_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 port, ZXIC_UINT32 mode); +ZXIC_UINT32 dpp_tm_pport_mcode_switch_del(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 port); + +#endif \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_vlan.h b/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_vlan.h new file mode 100644 index 0000000..22950e1 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_vlan.h @@ -0,0 +1,29 @@ +/************************************************************** +* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司 +* 文件名称 : dpp_tbl_vlan.h +* 文件标识 : +* 内容摘要 : +* 其它说明 : +* 当前版本 : +* 作 者 : +* 完成日期 : 2014/01/27 +* DEPARTMENT: ASIC_FPGA_R&D_Dept +* MANUAL_PERCENT: 100% + +* 修改记录1: +* 修改日期: +* 版 本 号: +* 修 改 人: +* 修改内容: +***************************************************************/ + +#ifndef DPP_TBL_VLAN_H +#define DPP_TBL_VLAN_H + +#include "zxic_common.h" +#include "dpp_type_api.h" + +#define VLAN_GROUP_NUM (35) +#define VLAN_ID_NUM_IN_GROUP (120) + +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/table/source/Kbuild.include b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/Kbuild.include new file mode 100644 index 0000000..0560e3a --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/Kbuild.include @@ -0,0 +1,2 @@ +cur_dir := en_np/table/source/ +src_files += $(addprefix $(cur_dir),$(notdir $(wildcard $(dinghai_root)/$(cur_dir)*.c))) \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_bc.c b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_bc.c new file mode 100644 index 0000000..d313222 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_bc.c @@ -0,0 +1,196 @@ +#include "dpp_drv_init.h" +#include "dpp_drv_acl.h" +#include "dpp_drv_hash.h" +#include "dpp_drv_eram.h" +#include "dpp_drv_sdt.h" +#include "dpp_dev.h" +#include "dpp_dtb.h" +#include "dpp_hash.h" +#include "dpp_dtb_table.h" +#include "dpp_dtb_table_api.h" +#include "dpp_tbl_api.h" +#include "dpp_tbl_comm.h" +#include "dpp_tbl_bc.h" + +ZXIC_UINT32 dpp_vport_bc_info_add(DPP_PF_INFO_T* pf_info) +{ + ZXIC_UINT32 group_id = 0; + ZXIC_UINT32 vfunc_num = 0; + ZXIC_UINT32 rc = DPP_OK; + + DPP_VPORT_BC_TABLE_T* bc_table = NULL; + + ZXIC_COMM_CHECK_POINT(pf_info); + + rc = dpp_vport_bc_table_get(pf_info, &bc_table); + ZXIC_COMM_CHECK_RC(rc, "dpp_vport_bc_table_get"); + ZXIC_COMM_CHECK_POINT(bc_table); + + vfunc_num = VFUNC_NUM(pf_info->vport); + ZXIC_COMM_CHECK_INDEX(vfunc_num, 0, (BC_GROUP_NUM * BC_MEMBER_NUM_IN_GROUP) - 1); + + group_id = vfunc_num / BC_MEMBER_NUM_IN_GROUP; + ZXIC_COMM_CHECK_INDEX(group_id, 0, BC_GROUP_NUM - 1); + + bc_table->bc_info.bc_bitmap[group_id] |= ((ZXIC_UINT64)(1) << (BC_MEMBER_NUM_IN_GROUP - 1 - + (vfunc_num % BC_MEMBER_NUM_IN_GROUP))); + + return DPP_OK; +} + +ZXIC_UINT32 dpp_vport_bc_info_del(DPP_PF_INFO_T* pf_info) +{ + ZXIC_UINT32 group_id = 0; + ZXIC_UINT32 vfunc_num = 0; + ZXIC_UINT32 rc = DPP_OK; + + DPP_VPORT_BC_TABLE_T* bc_table = NULL; + + ZXIC_COMM_CHECK_POINT(pf_info); + + rc = dpp_vport_bc_table_get(pf_info, &bc_table); + ZXIC_COMM_CHECK_RC(rc, "dpp_vport_bc_table_get"); + ZXIC_COMM_CHECK_POINT(bc_table); + + vfunc_num = VFUNC_NUM(pf_info->vport); + ZXIC_COMM_CHECK_INDEX(vfunc_num, 0, (BC_GROUP_NUM * BC_MEMBER_NUM_IN_GROUP) - 1); + + group_id = vfunc_num / BC_MEMBER_NUM_IN_GROUP; + ZXIC_COMM_CHECK_INDEX(group_id, 0, BC_GROUP_NUM - 1); + + bc_table->bc_info.bc_bitmap[group_id] &= ~((ZXIC_UINT64)(1) << (BC_MEMBER_NUM_IN_GROUP - 1 - + (vfunc_num % BC_MEMBER_NUM_IN_GROUP))); + + return DPP_OK; +} + +ZXIC_UINT32 dpp_vport_bc_info_clear_all(DPP_PF_INFO_T* pf_info) +{ + ZXIC_UINT32 group_id = 0; + ZXIC_UINT32 rc = DPP_OK; + + DPP_VPORT_BC_TABLE_T* bc_table = NULL; + + ZXIC_COMM_CHECK_POINT(pf_info); + + rc = dpp_vport_bc_table_get(pf_info, &bc_table); + ZXIC_COMM_CHECK_RC(rc, "dpp_vport_bc_table_get"); + ZXIC_COMM_CHECK_POINT(bc_table); + + for (group_id = 0; group_id < BC_GROUP_NUM; group_id++) + { + bc_table->bc_info.bc_bitmap[group_id] = 0; + } + + return DPP_OK; +} + +ZXIC_UINT32 dpp_vport_bc_table_insert(DPP_PF_INFO_T* pf_info) +{ + DPP_DEV_T dev = {0}; + + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 group_id = 0; + ZXIC_UINT32 index = 0; + ZXIC_UINT32 sdt_no = ZXDH_SDT_BC_TABLE; + ZXIC_UINT32 queue = 0; + ZXIC_UINT32 rc = DPP_OK; + + ZXDH_BC_T bc_entry = {0}; + DPP_VPORT_BC_TABLE_T *bc_table = NULL; + + ZXIC_COMM_CHECK_POINT(pf_info); + + rc = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get"); + + rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue); + ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get"); + + rc = dpp_vport_bc_table_get(pf_info, &bc_table); + ZXIC_COMM_CHECK_RC(rc, "dpp_vport_bc_table_get"); + ZXIC_COMM_CHECK_POINT(bc_table); + + for (group_id = 0; group_id < BC_GROUP_NUM; group_id++) + { + index = (((OWNER_PF_VQM_VFID(pf_info->vport) - PF_VQM_VFID_OFFSET) << 2)| group_id); + bc_entry.hit_flag = 1; + bc_entry.bc_bitmap = bc_table->bc_info.bc_bitmap[group_id]; + + rc = dpp_apt_dtb_eram_insert(&dev, queue, sdt_no, index, &bc_entry); + ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_insert"); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u group_id: %u index: 0x%02x.\n", __FUNCTION__, + pf_info->slot, pf_info->vport, sdt_no, group_id, index); + ZXIC_COMM_PRINT("[%s] bc_bitmap: %02x %02x %02x %02x %02x %02x %02x %02x.\n", __FUNCTION__, + *((ZXIC_UINT8*)(&bc_entry.bc_bitmap) + 7), + *((ZXIC_UINT8*)(&bc_entry.bc_bitmap) + 6), + *((ZXIC_UINT8*)(&bc_entry.bc_bitmap) + 5), + *((ZXIC_UINT8*)(&bc_entry.bc_bitmap) + 4), + *((ZXIC_UINT8*)(&bc_entry.bc_bitmap) + 3), + *((ZXIC_UINT8*)(&bc_entry.bc_bitmap) + 2), + *((ZXIC_UINT8*)(&bc_entry.bc_bitmap) + 1), + *((ZXIC_UINT8*)(&bc_entry.bc_bitmap) + 0)); + } + + return DPP_OK; +} + +ZXIC_UINT32 dpp_vport_bond_pf(DPP_PF_INFO_T* pf_info) +{ + ZXIC_UINT32 rc = DPP_OK; + + ZXIC_COMM_CHECK_POINT(pf_info); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x start.\n", __FUNCTION__, + pf_info->slot, pf_info->vport); + + if (IS_PF(pf_info->vport)) + { + rc = dpp_vport_bc_info_clear_all(pf_info); + ZXIC_COMM_CHECK_RC(rc, "dpp_vport_bc_info_clear_all"); + } + else + { + rc = dpp_vport_bc_info_add(pf_info); + ZXIC_COMM_CHECK_RC(rc, "dpp_vport_bc_info_add"); + } + + rc = dpp_vport_bc_table_insert(pf_info); + ZXIC_COMM_CHECK_RC(rc, "dpp_vport_bc_table_insert"); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x success.\n", __FUNCTION__, + pf_info->slot, pf_info->vport); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_vport_bond_pf); + +ZXIC_UINT32 dpp_vport_unbond_pf(DPP_PF_INFO_T* pf_info) +{ + ZXIC_UINT32 rc = DPP_OK; + + ZXIC_COMM_CHECK_POINT(pf_info); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x start.\n", __FUNCTION__, + pf_info->slot, pf_info->vport); + + if (IS_PF(pf_info->vport)) + { + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x is pf, no vf to del.\n", __FUNCTION__, + pf_info->slot, pf_info->vport); + return DPP_ERR; + } + + rc = dpp_vport_bc_info_del(pf_info); + ZXIC_COMM_CHECK_RC(rc, "dpp_vport_bc_info_del"); + + rc = dpp_vport_bc_table_insert(pf_info); + ZXIC_COMM_CHECK_RC(rc, "dpp_vport_bc_table_insert"); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x success.\n", __FUNCTION__, + pf_info->slot, pf_info->vport); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_vport_unbond_pf); diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_comm.c b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_comm.c new file mode 100644 index 0000000..cc7cf33 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_comm.c @@ -0,0 +1,286 @@ +#include "dpp_drv_init.h" +#include "dpp_drv_acl.h" +#include "dpp_drv_hash.h" +#include "dpp_drv_eram.h" +#include "dpp_drv_sdt.h" +#include "dpp_dev.h" +#include "dpp_dtb.h" +#include "dpp_hash.h" +#include "dpp_dtb_table.h" +#include "dpp_dtb_table_api.h" +#include "dpp_tbl_mc.h" +#include "dpp_tbl_bc.h" +#include "dpp_tbl_promisc.h" +#include "dpp_tbl_comm.h" +#include "dpp_tbl_api.h" + +static DPP_VPORT_MGR_T g_vport_mgr[DPP_PCIE_SLOT_MAX][DPP_PCIE_CHANNEL_MAX] = {0}; + +ZXIC_UINT32 dpp_data_print(ZXIC_UINT8 *data, ZXIC_UINT32 len) +{ + ZXIC_UINT32 i = 0; + ZXIC_UINT32 loop_cnt = len / 16; + ZXIC_UINT32 last_line_len = len % 16; + + ZXIC_COMM_PRINT("-----------------------------------------------\n"); + for (i = 0; i < loop_cnt; i++) + { + ZXIC_COMM_PRINT("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", + *(data + (i * 16) + 0), *(data + (i * 16) + 1), *(data + (i * 16) + 2), *(data + (i * 16) + 3), + *(data + (i * 16) + 4), *(data + (i * 16) + 5), *(data + (i * 16) + 6), *(data + (i * 16) + 7), + *(data + (i * 16) + 8), *(data + (i * 16) + 9), *(data + (i * 16) + 10), *(data + (i * 16) + 11), + *(data + (i * 16) + 12), *(data + (i * 16) + 13), *(data + (i * 16) + 14), *(data + (i * 16) + 15)); + } + if (last_line_len != 0) + { + if (last_line_len == 1) + { + ZXIC_COMM_PRINT("%02x\n", *(data + (i * 16) + 0)); + } + else if (last_line_len == 2) + { + ZXIC_COMM_PRINT("%02x %02x\n", *(data + (i * 16) + 0), *(data + (i * 16) + 1)); + } + else if (last_line_len == 3) + { + ZXIC_COMM_PRINT("%02x %02x %02x\n", *(data + (i * 16) + 0), *(data + (i * 16) + 1), *(data + (i * 16) + 2)); + } + else if (last_line_len == 4) + { + ZXIC_COMM_PRINT("%02x %02x %02x %02x\n", + *(data + (i * 16) + 0), *(data + (i * 16) + 1), *(data + (i * 16) + 2), *(data + (i * 16) + 3)); + } + else if (last_line_len == 5) + { + ZXIC_COMM_PRINT("%02x %02x %02x %02x %02x\n", + *(data + (i * 16) + 0), *(data + (i * 16) + 1), *(data + (i * 16) + 2), *(data + (i * 16) + 3), + *(data + (i * 16) + 4)); + } + else if (last_line_len == 6) + { + ZXIC_COMM_PRINT("%02x %02x %02x %02x %02x %02x\n", + *(data + (i * 16) + 0), *(data + (i * 16) + 1), *(data + (i * 16) + 2), *(data + (i * 16) + 3), + *(data + (i * 16) + 4), *(data + (i * 16) + 5)); + } + else if (last_line_len == 7) + { + ZXIC_COMM_PRINT("%02x %02x %02x %02x %02x %02x %02x\n", + *(data + (i * 16) + 0), *(data + (i * 16) + 1), *(data + (i * 16) + 2), *(data + (i * 16) + 3), + *(data + (i * 16) + 4), *(data + (i * 16) + 5), *(data + (i * 16) + 6)); + } + else if (last_line_len == 8) + { + ZXIC_COMM_PRINT("%02x %02x %02x %02x %02x %02x %02x %02x\n", + *(data + (i * 16) + 0), *(data + (i * 16) + 1), *(data + (i * 16) + 2), *(data + (i * 16) + 3), + *(data + (i * 16) + 4), *(data + (i * 16) + 5), *(data + (i * 16) + 6), *(data + (i * 16) + 7)); + } + else if (last_line_len == 9) + { + ZXIC_COMM_PRINT("%02x %02x %02x %02x %02x %02x %02x %02x %02x\n", + *(data + (i * 16) + 0), *(data + (i * 16) + 1), *(data + (i * 16) + 2), *(data + (i * 16) + 3), + *(data + (i * 16) + 4), *(data + (i * 16) + 5), *(data + (i * 16) + 6), *(data + (i * 16) + 7), + *(data + (i * 16) + 8)); + } + else if (last_line_len == 10) + { + ZXIC_COMM_PRINT("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", + *(data + (i * 16) + 0), *(data + (i * 16) + 1), *(data + (i * 16) + 2), *(data + (i * 16) + 3), + *(data + (i * 16) + 4), *(data + (i * 16) + 5), *(data + (i * 16) + 6), *(data + (i * 16) + 7), + *(data + (i * 16) + 8), *(data + (i * 16) + 9)); + } + else if (last_line_len == 11) + { + ZXIC_COMM_PRINT("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", + *(data + (i * 16) + 0), *(data + (i * 16) + 1), *(data + (i * 16) + 2), *(data + (i * 16) + 3), + *(data + (i * 16) + 4), *(data + (i * 16) + 5), *(data + (i * 16) + 6), *(data + (i * 16) + 7), + *(data + (i * 16) + 8), *(data + (i * 16) + 9), *(data + (i * 16) + 10)); + } + else if (last_line_len == 12) + { + ZXIC_COMM_PRINT("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", + *(data + (i * 16) + 0), *(data + (i * 16) + 1), *(data + (i * 16) + 2), *(data + (i * 16) + 3), + *(data + (i * 16) + 4), *(data + (i * 16) + 5), *(data + (i * 16) + 6), *(data + (i * 16) + 7), + *(data + (i * 16) + 8), *(data + (i * 16) + 9), *(data + (i * 16) + 10), *(data + (i * 16) + 11)); + } + else if (last_line_len == 13) + { + ZXIC_COMM_PRINT("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", + *(data + (i * 16) + 0), *(data + (i * 16) + 1), *(data + (i * 16) + 2), *(data + (i * 16) + 3), + *(data + (i * 16) + 4), *(data + (i * 16) + 5), *(data + (i * 16) + 6), *(data + (i * 16) + 7), + *(data + (i * 16) + 8), *(data + (i * 16) + 9), *(data + (i * 16) + 10), *(data + (i * 16) + 11), + *(data + (i * 16) + 12)); + } + else if (last_line_len == 14) + { + ZXIC_COMM_PRINT("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", + *(data + (i * 16) + 0), *(data + (i * 16) + 1), *(data + (i * 16) + 2), *(data + (i * 16) + 3), + *(data + (i * 16) + 4), *(data + (i * 16) + 5), *(data + (i * 16) + 6), *(data + (i * 16) + 7), + *(data + (i * 16) + 8), *(data + (i * 16) + 9), *(data + (i * 16) + 10), *(data + (i * 16) + 11), + *(data + (i * 16) + 12), *(data + (i * 16) + 13)); + } + else if (last_line_len == 15) + { + ZXIC_COMM_PRINT("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", + *(data + (i * 16) + 0), *(data + (i * 16) + 1), *(data + (i * 16) + 2), *(data + (i * 16) + 3), + *(data + (i * 16) + 4), *(data + (i * 16) + 5), *(data + (i * 16) + 6), *(data + (i * 16) + 7), + *(data + (i * 16) + 8), *(data + (i * 16) + 9), *(data + (i * 16) + 10), *(data + (i * 16) + 11), + *(data + (i * 16) + 12), *(data + (i * 16) + 13), *(data + (i * 16) + 14)); + } + } + ZXIC_COMM_PRINT("-----------------------------------------------\n"); + + return DPP_OK; +} + +ZXIC_UINT32 dpp_vport_mgr_init(DPP_PF_INFO_T* pf_info) +{ + ZXIC_UINT16 slot = 0; + ZXIC_UINT16 channel_id = 0; + + ZXIC_COMM_CHECK_POINT(pf_info); + + slot = pf_info->slot; + ZXIC_COMM_CHECK_INDEX(slot, 0, DPP_PCIE_SLOT_MAX - 1); + + channel_id = DPP_PCIE_CHANNEL_ID(pf_info->vport); + ZXIC_COMM_CHECK_INDEX(channel_id, 0, DPP_PCIE_CHANNEL_MAX - 1); + + ZXIC_COMM_MEMSET(&g_vport_mgr[slot][channel_id], 0x00, sizeof(DPP_VPORT_MGR_T)); + + return DPP_OK; +} + +ZXIC_UINT32 dpp_vport_mgr_release(DPP_PF_INFO_T* pf_info) +{ + ZXIC_UINT16 slot = 0; + ZXIC_UINT16 channel_id = 0; + + ZXIC_COMM_CHECK_POINT(pf_info); + + slot = pf_info->slot; + ZXIC_COMM_CHECK_INDEX(slot, 0, DPP_PCIE_SLOT_MAX - 1); + + channel_id = DPP_PCIE_CHANNEL_ID(pf_info->vport); + ZXIC_COMM_CHECK_INDEX(channel_id, 0, DPP_PCIE_CHANNEL_MAX - 1); + + ZXIC_COMM_MEMSET(&g_vport_mgr[slot][channel_id], 0x00, sizeof(DPP_VPORT_MGR_T)); + + return DPP_OK; +} + +ZXIC_UINT32 dpp_vport_bc_table_get(DPP_PF_INFO_T* pf_info, DPP_VPORT_BC_TABLE_T** bc_table) +{ + ZXIC_UINT16 slot = 0; + ZXIC_UINT16 channel_id = 0; + + ZXIC_COMM_CHECK_POINT(pf_info); + ZXIC_COMM_CHECK_POINT(bc_table); + + slot = pf_info->slot; + ZXIC_COMM_CHECK_INDEX(slot, 0, DPP_PCIE_SLOT_MAX - 1); + + channel_id = DPP_PCIE_CHANNEL_ID(pf_info->vport); + ZXIC_COMM_CHECK_INDEX(channel_id, 0, DPP_PCIE_CHANNEL_MAX - 1); + + *bc_table = &g_vport_mgr[slot][channel_id].bc_table; + + return DPP_OK; +} + +ZXIC_UINT32 dpp_vport_mc_table_get(DPP_PF_INFO_T* pf_info, DPP_VPORT_MC_TABLE_T** mc_table) +{ + ZXIC_UINT16 slot = 0; + ZXIC_UINT16 channel_id = 0; + + ZXIC_COMM_CHECK_POINT(pf_info); + ZXIC_COMM_CHECK_POINT(mc_table); + + slot = pf_info->slot; + ZXIC_COMM_CHECK_INDEX(slot, 0, DPP_PCIE_SLOT_MAX - 1); + + channel_id = DPP_PCIE_CHANNEL_ID(pf_info->vport); + ZXIC_COMM_CHECK_INDEX(channel_id, 0, DPP_PCIE_CHANNEL_MAX - 1); + + *mc_table = &g_vport_mgr[slot][channel_id].mc_table; + + return DPP_OK; +} + +ZXIC_UINT32 dpp_vport_uc_promisc_table_get(DPP_PF_INFO_T* pf_info, DPP_VPORT_PROMISC_TABLE_T** promisc_table) +{ + ZXIC_UINT16 slot = 0; + ZXIC_UINT16 channel_id = 0; + + ZXIC_COMM_CHECK_POINT(pf_info); + ZXIC_COMM_CHECK_POINT(promisc_table); + + slot = pf_info->slot; + ZXIC_COMM_CHECK_INDEX(slot, 0, DPP_PCIE_SLOT_MAX - 1); + + channel_id = DPP_PCIE_CHANNEL_ID(pf_info->vport); + ZXIC_COMM_CHECK_INDEX(channel_id, 0, DPP_PCIE_CHANNEL_MAX - 1); + + *promisc_table = &g_vport_mgr[slot][channel_id].uc_promisc_table; + + return DPP_OK; +} + +ZXIC_UINT32 dpp_vport_mc_promisc_table_get(DPP_PF_INFO_T* pf_info, DPP_VPORT_PROMISC_TABLE_T** promisc_table) +{ + ZXIC_UINT16 slot = 0; + ZXIC_UINT16 channel_id = 0; + + ZXIC_COMM_CHECK_POINT(pf_info); + ZXIC_COMM_CHECK_POINT(promisc_table); + + slot = pf_info->slot; + ZXIC_COMM_CHECK_INDEX(slot, 0, DPP_PCIE_SLOT_MAX - 1); + + channel_id = DPP_PCIE_CHANNEL_ID(pf_info->vport); + ZXIC_COMM_CHECK_INDEX(channel_id, 0, DPP_PCIE_CHANNEL_MAX - 1); + + *promisc_table = &g_vport_mgr[slot][channel_id].mc_promisc_table; + + return DPP_OK; +} + +ZXIC_UINT32 dpp_vport_get_by_vqm_vfid(ZXIC_UINT16 pf_vport, ZXIC_UINT32 vqm_vfid, ZXIC_UINT16* vport) +{ + ZXIC_COMM_CHECK_POINT(vport); + + if (vqm_vfid >= PF_VQM_VFID_OFFSET) + { + *vport = pf_vport; + } + else + { + *vport = ((EPID(pf_vport) << 12) | 0x800 | (FUNC_NUM(pf_vport) << 8) | (vqm_vfid - (EPID(pf_vport) * 256))); + } + return DPP_OK; +} + +ZXIC_UINT32 dpp_vport_get_by_mc_bitmap(ZXIC_UINT16 pf_vport, ZXIC_UINT32 group_id, ZXIC_UINT64 mc_bitmap, + ZXIC_UINT16 vport[64], ZXIC_UINT32* p_vport_num) +{ + ZXIC_UINT32 i = 0; + + ZXIC_UINT32 vport_num = 0; + + ZXIC_COMM_CHECK_POINT(vport); + ZXIC_COMM_CHECK_POINT(p_vport_num); + + for (i = 0; i < MC_MEMBER_NUM_IN_GROUP; i++) + { + if ((mc_bitmap >> i) & 1) + { + vport[vport_num] = ((EPID(pf_vport) << 12) | 0x800 | (FUNC_NUM(pf_vport) << 8) | + ((group_id * MC_MEMBER_NUM_IN_GROUP) + MC_MEMBER_NUM_IN_GROUP - 1 - i)); + vport_num ++; + } + } + + *p_vport_num = vport_num; + + return DPP_OK; +} + diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_diag.c b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_diag.c new file mode 100644 index 0000000..e1cdbd3 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_diag.c @@ -0,0 +1,466 @@ +#include "dpp_tbl_api.h" +#include "dpp_tbl_comm.h" +#include "dpp_dtb.h" +#include "dpp_drv_sdt.h" + +ZXIC_CONST ZXIC_CHAR* g_vport_table_attr_name[] = { + "tpid","vhca","uplink_port","rss_hash_factor","hash_alg","panel_id","lag_id","pf_vqm_vfid","rsv3", + "mtu","port_base_qid","hash_search_index","rsv1","tm_enable","ingress_meter_enable","egress_meter_enable", + "ingress_meter_mode","egress_meter_mode","fd_enable","vepa_enable","spoof_check_enable","inline_sec_offload", + "ovs_enable","lag_enable","is_passthrough","is_vf","virtion_version","virtio_enable","accelerator_offload_flag", + "lro_offload","ip_fragment_offload","tcp_udp_checksum_offload","ip_checksum_offload","outer_ip_checksum_offload", + "is_up","allmulticast_enable","hw_bond_enable","rdma_offload_enable","vlan_filter_enable","vlan_strip_offload", + "qinq_vlan_strip_offload","rss_enable","mtu_offload_enable","hit_flag" +}; + +ZXIC_CONST ZXIC_CHAR* g_vport_panel_table_attr_name[] = { + "rsv7","ovs_pf_vfid","rsv6","pf_memport_qid","rsv5","bond_pf_vqm_vfid","rsv4","is_up","bond_link_up","hw_bond_enable", + "mtu","mtu_offload_enable","rsv3","tm_base_queue","ptp_port_vfid","rsv2","pf_vqm_vfid","tm_shape_enable","ptp_tc_enable", + "trust_mode","hit_flag" +}; + +ZXIC_CONST ZXIC_CHAR* dpp_vport_table_attr_name_get(ZXIC_UINT32 attr) +{ + if (attr >= (sizeof(ZXDH_VPORT_T) / sizeof(ZXIC_UINT32))) + { + return NULL; + } + + return g_vport_table_attr_name[attr]; +} + +ZXIC_CONST ZXIC_CHAR* dpp_vport_panel_table_attr_name_get(ZXIC_UINT32 attr) +{ + if (attr >= (sizeof(ZXDH_PANEL_PORT_T) / sizeof(ZXIC_UINT32))) + { + return NULL; + } + + return g_vport_panel_table_attr_name[attr]; +} + +ZXIC_UINT32 diag_dpp_vport_mac_add(ZXIC_UINT16 slot, ZXIC_UINT16 vport, + ZXIC_UINT8 mac0, ZXIC_UINT8 mac1, ZXIC_UINT8 mac2, + ZXIC_UINT8 mac3, ZXIC_UINT8 mac4, ZXIC_UINT8 mac5) +{ + DPP_PF_INFO_T pf_info = {slot, vport}; + + ZXIC_UINT8 mac[6]; + ZXIC_UINT32 rc = DPP_OK; + + mac[0] = mac0; + mac[1] = mac1; + mac[2] = mac2; + mac[3] = mac3; + mac[4] = mac4; + mac[5] = mac5; + + rc = dpp_add_mac(&pf_info, mac); + ZXIC_COMM_CHECK_RC(rc, "dpp_add_mac"); + + return DPP_OK; +} + +ZXIC_UINT32 diag_dpp_vport_mac_del(ZXIC_UINT16 slot, ZXIC_UINT16 vport, + ZXIC_UINT8 mac0, ZXIC_UINT8 mac1, ZXIC_UINT8 mac2, + ZXIC_UINT8 mac3, ZXIC_UINT8 mac4, ZXIC_UINT8 mac5) +{ + DPP_PF_INFO_T pf_info = {slot, vport}; + + ZXIC_UINT8 mac[6]; + ZXIC_UINT32 rc = DPP_OK; + + mac[0] = mac0; + mac[1] = mac1; + mac[2] = mac2; + mac[3] = mac3; + mac[4] = mac4; + mac[5] = mac5; + + rc = dpp_del_mac(&pf_info, mac); + ZXIC_COMM_CHECK_RC(rc, "dpp_del_mac"); + + return DPP_OK; +} + +ZXIC_UINT32 diag_dpp_vport_mac_prt(ZXIC_UINT16 slot, ZXIC_UINT16 vport) +{ + ZXIC_UINT32 mac_num = 0; + ZXIC_UINT32 i = 0; + ZXIC_UINT32 rc = DPP_OK; + + DPP_PF_INFO_T pf_info = {slot, vport}; + + MAC_VPORT_INFO *p_mac_arr = (MAC_VPORT_INFO *)ZXIC_COMM_MALLOC(DTB_DUMP_UNICAST_MAC_DUMP_NUM * + sizeof(MAC_VPORT_INFO)); + ZXIC_COMM_CHECK_POINT(p_mac_arr); + + rc = dpp_unicast_mac_dump(&pf_info, p_mac_arr, &mac_num); + ZXIC_COMM_CHECK_RC_MEMORY_FREE(rc, "dpp_unicast_mac_dump", p_mac_arr); + + ZXIC_COMM_PRINT("-----------------------------------------------\n"); + for (i = 0; i < mac_num; i++) + { + ZXIC_COMM_PRINT("slot: %u vport: 0x%04x mac: %02x:%02x:%02x:%02x:%02x:%02x\n", + slot, p_mac_arr[i].vport, + p_mac_arr[i].addr[0], p_mac_arr[i].addr[1], + p_mac_arr[i].addr[2], p_mac_arr[i].addr[3], + p_mac_arr[i].addr[4], p_mac_arr[i].addr[5]); + } + ZXIC_COMM_PRINT("-----------------------------------------------\n"); + + ZXIC_COMM_FREE(p_mac_arr); + + return DPP_OK; +} + +ZXIC_UINT32 diag_dpp_vport_mc_mac_add(ZXIC_UINT16 slot, ZXIC_UINT16 vport, + ZXIC_UINT8 mac0, ZXIC_UINT8 mac1, ZXIC_UINT8 mac2, + ZXIC_UINT8 mac3, ZXIC_UINT8 mac4, ZXIC_UINT8 mac5) +{ + DPP_PF_INFO_T pf_info = {slot, vport}; + + ZXIC_UINT8 mac[6]; + ZXIC_UINT32 rc = DPP_OK; + + mac[0] = mac0; + mac[1] = mac1; + mac[2] = mac2; + mac[3] = mac3; + mac[4] = mac4; + mac[5] = mac5; + + rc = dpp_multi_mac_add_member(&pf_info, mac); + ZXIC_COMM_CHECK_RC(rc, "dpp_multi_mac_add_member"); + + return DPP_OK; +} + +ZXIC_UINT32 diag_dpp_vport_mc_mac_del(ZXIC_UINT16 slot, ZXIC_UINT16 vport, + ZXIC_UINT8 mac0, ZXIC_UINT8 mac1, ZXIC_UINT8 mac2, + ZXIC_UINT8 mac3, ZXIC_UINT8 mac4, ZXIC_UINT8 mac5) +{ + DPP_PF_INFO_T pf_info = {slot, vport}; + + ZXIC_UINT8 mac[6]; + ZXIC_UINT32 rc = DPP_OK; + + mac[0] = mac0; + mac[1] = mac1; + mac[2] = mac2; + mac[3] = mac3; + mac[4] = mac4; + mac[5] = mac5; + + rc = dpp_multi_mac_del_member(&pf_info, mac); + ZXIC_COMM_CHECK_RC(rc, "dpp_multi_mac_del_member"); + + return DPP_OK; +} + +ZXIC_UINT32 diag_dpp_vport_mc_mac_prt(ZXIC_UINT16 slot, ZXIC_UINT16 vport) +{ + ZXIC_UINT32 mac_num = 0; + ZXIC_UINT32 i = 0; + ZXIC_UINT32 rc = DPP_OK; + + DPP_PF_INFO_T pf_info = {slot, vport}; + + MAC_VPORT_INFO *p_mac_arr = (MAC_VPORT_INFO *)ZXIC_COMM_MALLOC(DTB_DUMP_MULTICAST_MAC_DUMP_NUM * + sizeof(MAC_VPORT_INFO)); + ZXIC_COMM_CHECK_POINT(p_mac_arr); + + rc = dpp_multicast_mac_dump(&pf_info, p_mac_arr, &mac_num); + ZXIC_COMM_CHECK_RC_MEMORY_FREE(rc, "dpp_multicast_mac_dump", p_mac_arr); + + ZXIC_COMM_PRINT("-----------------------------------------------\n"); + for (i = 0; i < mac_num; i++) + { + ZXIC_COMM_PRINT("slot: %u vport: 0x%04x mac: %02x:%02x:%02x:%02x:%02x:%02x\n", + slot, p_mac_arr[i].vport, + p_mac_arr[i].addr[0], p_mac_arr[i].addr[1], + p_mac_arr[i].addr[2], p_mac_arr[i].addr[3], + p_mac_arr[i].addr[4], p_mac_arr[i].addr[5]); + } + ZXIC_COMM_PRINT("-----------------------------------------------\n"); + + ZXIC_COMM_FREE(p_mac_arr); + + return DPP_OK; +} + +ZXIC_UINT32 diag_dpp_vport_table_set(ZXIC_UINT16 slot, ZXIC_UINT16 vport, ZXIC_UINT32 attr, + ZXIC_UINT32 value) +{ + DPP_PF_INFO_T pf_info = {slot, vport}; + + ZXIC_UINT32 rc = DPP_OK; + + rc = dpp_egr_port_attr_set(&pf_info, attr, value); + ZXIC_COMM_CHECK_RC(rc, "dpp_egr_port_attr_set"); + + return DPP_OK; +} + +ZXIC_UINT32 diag_dpp_vport_table_prt(ZXIC_UINT16 slot, ZXIC_UINT16 vport) +{ + ZXDH_VPORT_T port_table = {0}; + DPP_PF_INFO_T pf_info = {slot, vport}; + + ZXIC_UINT32 rc = DPP_OK; + + rc = dpp_egr_port_attr_get(&pf_info, &port_table); + ZXIC_COMM_CHECK_RC(rc, "dpp_egr_port_attr_set"); + + ZXIC_COMM_PRINT("-----------------------------------------------\n"); + ZXIC_COMM_PRINT("hit_flag = %u\n", port_table.hit_flag); + ZXIC_COMM_PRINT("%02u mtu_offload_enable = %u\n", EGR_FLAG_MTU_OFFLOAD_EN_OFF, port_table.mtu_offload_enable); + ZXIC_COMM_PRINT("%02u rss_enable = %u\n", EGR_FLAG_RSS_EN_OFF, port_table.rss_enable); + ZXIC_COMM_PRINT("%02u qinq_vlan_strip_offload = %u\n", EGR_FLAG_QINQ_VLAN_STRIP_OFFLOAD, port_table.qinq_vlan_strip_offload); + ZXIC_COMM_PRINT("%02u vlan_strip_offload = %u\n", EGR_FLAG_VLAN_STRIP_OFFLOAD, port_table.vlan_strip_offload); + ZXIC_COMM_PRINT("%02u vlan_filter_enable = %u\n", EGR_FLAG_VLAN_FILTER_EN_OFF, port_table.vlan_filter_enable); + ZXIC_COMM_PRINT("%02u rdma_offload_enable = %u\n", EGR_FLAG_RDMA_OFFLOAD_EN_OFF, port_table.rdma_offload_enable); + ZXIC_COMM_PRINT("%02u hw_bond_enable = %u\n", EGR_FLAG_HW_BOND_EN_OFF, port_table.hw_bond_enable); + ZXIC_COMM_PRINT("%02u allmulticast_enable = %u\n", EGR_FLAG_IFF_ALLMULTI_EN_OFF, port_table.allmulticast_enable); + ZXIC_COMM_PRINT("%02u is_up = %u\n", EGR_FLAG_VPORT_IS_UP, port_table.is_up); + ZXIC_COMM_PRINT("%02u outer_ip_checksum_offload = %u\n", EGR_FLAG_OUTER_IP_CHECKSUM_OFFLOAD, port_table.outer_ip_checksum_offload); + ZXIC_COMM_PRINT("%02u ip_checksum_offload = %u\n", EGR_FLAG_IP_CHKSUM, port_table.ip_checksum_offload); + ZXIC_COMM_PRINT("%02u tcp_udp_checksum_offload = %u\n", EGR_FLAG_TCP_UDP_CHKSUM, port_table.tcp_udp_checksum_offload); + ZXIC_COMM_PRINT("%02u ip_fragment_offload = %u\n", EGR_FLAG_IP_FRAGMENT_OFFLOAD, port_table.ip_fragment_offload); + ZXIC_COMM_PRINT("%02u lro_offload = %u\n", EGR_FLAG_IPV6_TCP_ASSEMBLE, port_table.lro_offload); + ZXIC_COMM_PRINT("%02u lro_offload = %u\n", EGR_FLAG_IPV4_TCP_ASSEMBLE, port_table.lro_offload); + ZXIC_COMM_PRINT("%02u accelerator_offload_flag = %u\n", EGR_FLAG_ACCELERATOR_OFFLOAD_FLAG, port_table.accelerator_offload_flag); + ZXIC_COMM_PRINT("%02u virtio_enable = %u\n", EGR_FLAG_VIRTION_EN_OFF, port_table.virtio_enable); + ZXIC_COMM_PRINT("%02u virtion_version = %u\n", EGR_FLAG_VIRTION_VERSION, port_table.virtion_version); + ZXIC_COMM_PRINT("%02u is_vf = %u\n", EGR_FLAG_IS_VF, port_table.is_vf); + ZXIC_COMM_PRINT("%02u is_passthrough = %u\n", EGR_FLAG_IS_PASSTHROUGH, port_table.is_passthrough); + ZXIC_COMM_PRINT("%02u lag_enable = %u\n", EGR_FLAG_LAG_EN_OFF, port_table.lag_enable); + ZXIC_COMM_PRINT("%02u ovs_enable = %u\n", EGR_FLAG_OVS_EN_OFF, port_table.ovs_enable); + ZXIC_COMM_PRINT("%02u inline_sec_offload = %u\n", EGR_FLAG_INLINE_SEC_OFFLOAD, port_table.inline_sec_offload); + ZXIC_COMM_PRINT("%02u spoof_check_enable = %u\n", EGR_FLAG_SPOOFCHK_EN_OFF, port_table.spoof_check_enable); + ZXIC_COMM_PRINT("%02u vepa_enable = %u\n", EGR_FLAG_VEPA_EN_OFF, port_table.vepa_enable); + ZXIC_COMM_PRINT("%02u fd_enable = %u\n", EGR_FLAG_FD_EN_OFF, port_table.fd_enable); + ZXIC_COMM_PRINT("%02u egress_meter_mode = %u\n", EGR_FLAG_EGRESS_MODE, port_table.egress_meter_mode); + ZXIC_COMM_PRINT("%02u ingress_meter_mode = %u\n", EGR_FLAG_INGRESS_MODE, port_table.ingress_meter_mode); + ZXIC_COMM_PRINT("%02u egress_meter_enable = %u\n", EGR_FLAG_EGRESS_METER_EN_OFF, port_table.egress_meter_enable); + ZXIC_COMM_PRINT("%02u ingress_meter_enable = %u\n", EGR_FLAG_INGRESS_METER_EN_OFF, port_table.ingress_meter_enable); + ZXIC_COMM_PRINT("%02u tm_enable = %u\n", EGR_FLAG_TM_EN_OFF, port_table.tm_enable); + ZXIC_COMM_PRINT("%02u hash_search_index = %u\n", EGR_FLAG_HASH_SEARCH_INDEX, port_table.hash_search_index); + ZXIC_COMM_PRINT("%02u port_base_qid = %u\n", EGR_FLAG_PORT_BASE_QID, port_table.port_base_qid); + ZXIC_COMM_PRINT("%02u mtu = %u\n", EGR_FLAG_MTU, port_table.mtu); + ZXIC_COMM_PRINT("%02u pf_vqm_vfid = %u\n", EGR_FLAG_PF_VQM_VFID, port_table.pf_vqm_vfid); + ZXIC_COMM_PRINT("%02u lag_id = %u\n", EGR_FLAG_LAG_ID, port_table.lag_id); + ZXIC_COMM_PRINT("%02u panel_id = %u\n", EGR_FLAG_PANEL_ID, port_table.panel_id); + ZXIC_COMM_PRINT("%02u hash_alg = %u\n", EGR_FLAG_HASH_ALG, port_table.hash_alg); + ZXIC_COMM_PRINT("%02u rss_hash_factor = %u\n", EGR_FLAG_RSS_HASH_FACTOR, port_table.rss_hash_factor); + ZXIC_COMM_PRINT("%02u uplink_port = %u\n", EGR_FLAG_UPLINK_PORT, port_table.uplink_port); + ZXIC_COMM_PRINT("%02u vhca = %u\n", EGR_FLAG_VHCA, port_table.vhca); + ZXIC_COMM_PRINT("%02u tpid = %u\n", EGR_FLAG_TPID, port_table.tpid); + ZXIC_COMM_PRINT("-----------------------------------------------\n"); + + return DPP_OK; +} + +ZXIC_UINT32 diag_dpp_vport_panel_table_set(ZXIC_UINT16 slot, ZXIC_UINT16 vport, ZXIC_UINT8 panel_id, + ZXIC_UINT32 attr, ZXIC_UINT32 value) +{ + DPP_PF_INFO_T pf_info = {slot, vport}; + + ZXIC_UINT32 rc = DPP_OK; + + rc = dpp_panel_attr_set(&pf_info, panel_id, attr, value); + ZXIC_COMM_CHECK_RC(rc, "dpp_panel_attr_set"); + + return DPP_OK; +} + +ZXIC_UINT32 diag_dpp_vport_panel_table_prt(ZXIC_UINT16 slot, ZXIC_UINT16 vport, ZXIC_UINT8 panel_id) +{ + DPP_DEV_T dev = {0}; + ZXDH_PANEL_PORT_T panel_table = {0}; + DPP_PF_INFO_T pf_info = {slot, vport}; + + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 queue = 0; + ZXIC_UINT32 sdt_no = ZXDH_SDT_PANEL_PORT_ATTR_TABLE; + ZXIC_UINT32 rc = DPP_OK; + + rc = dpp_dev_get(dev_id, &pf_info, &dev); + ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get"); + + rc = dpp_dtb_queue_id_get(dev_id, &pf_info, &queue); + ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get"); + + rc = dpp_apt_dtb_eram_get(&dev, queue, sdt_no, panel_id, &panel_table); + ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_get"); + + ZXIC_COMM_PRINT("-----------------------------------------------\n"); + ZXIC_COMM_PRINT("hit_flag = %u\n", panel_table.hit_flag); + ZXIC_COMM_PRINT("%02u trust_mode = %u\n", PANEL_FLAG_TRUST_MODE, panel_table.trust_mode); + ZXIC_COMM_PRINT("%02u ptp_tc_enable = %u\n", PANEL_FLAG_PTP_TC_ENABLE, panel_table.ptp_tc_enable); + ZXIC_COMM_PRINT("%02u tm_shape_enable = %u\n", PANEL_FLAG_TM_SHAPE_ENABLE, panel_table.tm_shape_enable); + ZXIC_COMM_PRINT("%02u pf_vqm_vfid = %u\n", PANEL_FLAG_PF_VQM_VFID, panel_table.pf_vqm_vfid); + ZXIC_COMM_PRINT("%02u ptp_port_vfid = %u\n", PANEL_FLAG_PTP_PORT_VFID, panel_table.ptp_port_vfid); + ZXIC_COMM_PRINT("%02u tm_base_queue = %u\n", PANEL_FLAG_TM_BASE_QUEUE, panel_table.tm_base_queue); + ZXIC_COMM_PRINT("%02u mtu_offload_enable = %u\n", PANEL_FLAG_MTU_OFFLOAD_ENABLE, panel_table.mtu_offload_enable); + ZXIC_COMM_PRINT("%02u mtu = %u\n", PANEL_FLAG_MTU, panel_table.mtu); + ZXIC_COMM_PRINT("%02u hw_bond_enable = %u\n", PANEL_FLAG_HW_BOND_ENABLE, panel_table.hw_bond_enable); + ZXIC_COMM_PRINT("%02u bond_link_up = %u\n", PANEL_FLAG_BOND_LINK_UP, panel_table.bond_link_up); + ZXIC_COMM_PRINT("%02u is_up = %u\n", PANEL_FLAG_IS_UP, panel_table.is_up); + ZXIC_COMM_PRINT("%02u bond_pf_vqm_vfid = %u\n", PANEL_FLAG_BOND_PF_VQM_VFID, panel_table.bond_pf_vqm_vfid); + ZXIC_COMM_PRINT("%02u pf_memport_qid = %u\n", PANEL_FLAG_PF_MEMPORT_QID, panel_table.pf_memport_qid); + ZXIC_COMM_PRINT("%02u ovs_pf_vfid = %u\n", PANEL_FLAG_OVS_PF_VFID, panel_table.ovs_pf_vfid); + ZXIC_COMM_PRINT("-----------------------------------------------\n"); + + return DPP_OK; +} + +ZXIC_UINT32 diag_dpp_vport_bc_table_set(ZXIC_UINT16 slot, ZXIC_UINT16 vport, ZXIC_UINT32 enable) +{ + DPP_PF_INFO_T pf_info = {slot, vport}; + + ZXIC_UINT32 rc = DPP_OK; + + if (enable == 1) + { + rc = dpp_vport_bond_pf(&pf_info); + ZXIC_COMM_CHECK_RC(rc, "dpp_vport_bond_pf"); + } + else + { + rc = dpp_vport_unbond_pf(&pf_info); + ZXIC_COMM_CHECK_RC(rc, "dpp_vport_unbond_pf"); + } + + return DPP_OK; +} + +ZXIC_UINT32 diag_dpp_vport_bc_table_prt(ZXIC_UINT16 slot, ZXIC_UINT16 vport) +{ + DPP_DEV_T dev = {0}; + ZXDH_BC_T bc_table = {0}; + DPP_PF_INFO_T pf_info = {slot, vport}; + + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 queue = 0; + ZXIC_UINT32 sdt_no = ZXDH_SDT_BC_TABLE; + ZXIC_UINT32 group_id = 0; + ZXIC_UINT32 index = 0; + ZXIC_UINT32 i = 0; + ZXIC_UINT32 rc = DPP_OK; + + rc = dpp_dev_get(dev_id, &pf_info, &dev); + ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get"); + + rc = dpp_dtb_queue_id_get(dev_id, &pf_info, &queue); + ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get"); + + ZXIC_COMM_PRINT("-----------------------------------------------\n"); + for (group_id = 0; group_id < BC_GROUP_NUM; group_id++) + { + index = (((OWNER_PF_VQM_VFID(pf_info.vport) - PF_VQM_VFID_OFFSET) << 2)| group_id); + + rc = dpp_apt_dtb_eram_get(&dev, queue, sdt_no, index, &bc_table); + ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_get"); + + if (bc_table.hit_flag == 1) + { + for (i = 0; i < BC_MEMBER_NUM_IN_GROUP; i++) + { + if ((bc_table.bc_bitmap & ((ZXIC_UINT64)(1) << (BC_MEMBER_NUM_IN_GROUP - 1 - i))) != 0) + { + ZXIC_COMM_PRINT("vf %u enable\n", i + (group_id * BC_MEMBER_NUM_IN_GROUP)); + } + } + } + } + ZXIC_COMM_PRINT("-----------------------------------------------\n"); + + return DPP_OK; +} + +ZXIC_UINT32 diag_dpp_vport_promisc_table_prt(ZXIC_UINT16 slot, ZXIC_UINT16 vport, ZXIC_UINT32 sdt_no) +{ + DPP_DEV_T dev = {0}; + ZXDH_PROMISC_T promisc_table[4] = {0}; + DPP_PF_INFO_T pf_info = {slot, vport}; + + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 queue = 0; + ZXIC_UINT32 group_id = 0; + ZXIC_UINT32 index = 0; + ZXIC_UINT32 i = 0; + ZXIC_UINT32 rc = DPP_OK; + + rc = dpp_dev_get(dev_id, &pf_info, &dev); + ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get"); + + rc = dpp_dtb_queue_id_get(dev_id, &pf_info, &queue); + ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get"); + + ZXIC_COMM_PRINT("-----------------------------------------------\n"); + for (group_id = 0; group_id < BC_GROUP_NUM; group_id++) + { + index = (((OWNER_PF_VQM_VFID(pf_info.vport) - PF_VQM_VFID_OFFSET) << 2)| group_id); + + rc = dpp_apt_dtb_eram_get(&dev, queue, sdt_no, index, &promisc_table[group_id]); + ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_get"); + + if (promisc_table[group_id].hit_flag == 1) + { + for (i = 0; i < PROMISC_MEMBER_NUM_IN_GROUP; i++) + { + if ((promisc_table[group_id].bitmap & ((ZXIC_UINT64)(1) << (PROMISC_MEMBER_NUM_IN_GROUP - 1 - i))) != 0) + { + ZXIC_COMM_PRINT("vf %u enable\n", i + (group_id * PROMISC_MEMBER_NUM_IN_GROUP)); + } + } + } + } + if ((promisc_table[0].pf_enable == 1) && (promisc_table[1].pf_enable == 1) && + (promisc_table[2].pf_enable == 1) && (promisc_table[3].pf_enable == 1)) + { + ZXIC_COMM_PRINT("pf enable\n"); + } + ZXIC_COMM_PRINT("-----------------------------------------------\n"); + + return DPP_OK; +} + +ZXIC_UINT32 diag_dpp_vport_uc_promisc_table_set(ZXIC_UINT16 slot, ZXIC_UINT16 vport, ZXIC_UINT32 enable) +{ + DPP_PF_INFO_T pf_info = {slot, vport}; + + ZXIC_UINT32 rc = DPP_OK; + + rc = dpp_vport_uc_promisc_set(&pf_info, enable); + ZXIC_COMM_CHECK_RC(rc, "dpp_vport_uc_promisc_set"); + + return DPP_OK; +} + +ZXIC_UINT32 diag_dpp_vport_uc_promisc_table_prt(ZXIC_UINT16 slot, ZXIC_UINT16 vport) +{ + diag_dpp_vport_promisc_table_prt(slot, vport, ZXDH_SDT_UC_PROMISC_TABLE); + + return DPP_OK; +} + +ZXIC_UINT32 diag_dpp_vport_mc_promisc_table_set(ZXIC_UINT16 slot, ZXIC_UINT16 vport, ZXIC_UINT32 enable) +{ + DPP_PF_INFO_T pf_info = {slot, vport}; + + ZXIC_UINT32 rc = DPP_OK; + + rc = dpp_vport_mc_promisc_set(&pf_info, enable); + ZXIC_COMM_CHECK_RC(rc, "dpp_vport_mc_promisc_set"); + + return DPP_OK; +} + +ZXIC_UINT32 diag_dpp_vport_mc_promisc_table_prt(ZXIC_UINT16 slot, ZXIC_UINT16 vport) +{ + diag_dpp_vport_promisc_table_prt(slot, vport, ZXDH_SDT_MC_PROMISC_TABLE); + + return DPP_OK; +} diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_ipsec.c b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_ipsec.c new file mode 100644 index 0000000..05f5fef --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_ipsec.c @@ -0,0 +1,107 @@ +#include "dpp_drv_init.h" +#include "dpp_drv_acl.h" +#include "dpp_drv_hash.h" +#include "dpp_drv_eram.h" +#include "dpp_drv_sdt.h" +#include "dpp_dev.h" +#include "dpp_dtb.h" +#include "dpp_hash.h" +#include "dpp_dtb_table.h" +#include "dpp_dtb_table_api.h" +#include "dpp_tbl_comm.h" +#include "dpp_tbl_ipsec.h" + +ZXIC_UINT32 dpp_ipsec_enc_entry_add(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, + ZXIC_UINT8 *sip, ZXIC_UINT8 *dip, + ZXIC_UINT8 *sip_mask, ZXIC_UINT8 *dip_mask, + ZXIC_UINT32 is_ipv4, ZXIC_UINT32 sa_id) +{ + DPP_DEV_T dev = {0}; + + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 queue = 0; + + ZXIC_UINT32 sdt_no = ZXDH_SDT_IPSEC_ENC_TABLE; + ZXIC_UINT32 rc = DPP_OK; + + ZXDH_IPSEC_ENC_T ipsec_enc_entry = {0}; + + ZXIC_COMM_CHECK_POINT(pf_info); + ZXIC_COMM_CHECK_POINT(sip); + ZXIC_COMM_CHECK_POINT(dip); + ZXIC_COMM_CHECK_POINT(sip_mask); + ZXIC_COMM_CHECK_POINT(dip_mask); + + ZXIC_COMM_MEMSET(&ipsec_enc_entry, 0, sizeof(ZXDH_IPSEC_ENC_T)); + + ipsec_enc_entry.index = index; + + ZXIC_COMM_MEMCPY(ipsec_enc_entry.key.sip, sip, is_ipv4? 4 : 16); + ZXIC_COMM_MEMCPY(ipsec_enc_entry.key.dip, dip, is_ipv4? 4 : 16); + ZXIC_COMM_MEMCPY(ipsec_enc_entry.mask.sip, sip_mask, is_ipv4? 4 : 16); + ZXIC_COMM_MEMCPY(ipsec_enc_entry.mask.dip, dip_mask, is_ipv4? 4 : 16); + + ipsec_enc_entry.entry.sa_id = sa_id; + + rc = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get"); + + rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue); + ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get"); + + rc = dpp_apt_dtb_acl_entry_insert(&dev, queue, sdt_no, &ipsec_enc_entry); + ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_acl_entry_insert"); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u index: %u sa_id: %u is_ipv4: %u.\n", + __FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, index, sa_id, is_ipv4); + + ZXIC_COMM_PRINT("[%s] sip:\n", __FUNCTION__); + dpp_data_print(sip, is_ipv4? 4 : 16); + + ZXIC_COMM_PRINT("[%s] sip_mask:\n", __FUNCTION__); + dpp_data_print(sip_mask, is_ipv4? 4 : 16); + + ZXIC_COMM_PRINT("[%s] dip:\n", __FUNCTION__); + dpp_data_print(dip, is_ipv4? 4 : 16); + + ZXIC_COMM_PRINT("[%s] dip_mask:\n", __FUNCTION__); + dpp_data_print(dip_mask, is_ipv4? 4 : 16); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_ipsec_enc_entry_add); + +ZXIC_UINT32 dpp_ipsec_enc_entry_del(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index) +{ + DPP_DEV_T dev = {0}; + + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 queue = 0; + + ZXIC_UINT32 sdt_no = ZXDH_SDT_IPSEC_ENC_TABLE; + ZXIC_UINT32 rc = DPP_OK; + + ZXDH_IPSEC_ENC_T ipsec_enc_entry = {0}; + + ZXIC_COMM_CHECK_POINT(pf_info); + + ZXIC_COMM_MEMSET(&ipsec_enc_entry, 0, sizeof(ZXDH_IPSEC_ENC_T)); + ZXIC_COMM_MEMSET(&ipsec_enc_entry.mask, 0xFF, sizeof(ZXDH_IPSEC_ENC_MASK)); + + ipsec_enc_entry.index = index; + + rc = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get"); + + rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue); + ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get"); + + rc = dpp_apt_dtb_acl_entry_insert(&dev, queue, sdt_no, &ipsec_enc_entry); + ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_acl_entry_insert"); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u index: %u.\n", + __FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, index); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_ipsec_enc_entry_del); diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_lag.c b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_lag.c new file mode 100644 index 0000000..14bbfef --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_lag.c @@ -0,0 +1,253 @@ +#include "dpp_drv_init.h" +#include "dpp_drv_acl.h" +#include "dpp_drv_hash.h" +#include "dpp_drv_eram.h" +#include "dpp_drv_sdt.h" +#include "dpp_dev.h" +#include "dpp_dtb.h" +#include "dpp_hash.h" +#include "dpp_dtb_table.h" +#include "dpp_dtb_table_api.h" +#include "dpp_tbl_api.h" +#include "dpp_tbl_comm.h" +#include "dpp_tbl_port.h" +#include "dpp_tbl_lag.h" + +ZXIC_UINT32 dpp_lag_group_create(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 lag_id) +{ + DPP_DEV_T dev = {0}; + + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 queue = 0; + ZXIC_UINT32 sdt_no = ZXDH_SDT_LAG_TABLE; + ZXIC_UINT32 rc = DPP_OK; + + ZXDH_LAG_T lag_entry = {0}; + + ZXIC_COMM_CHECK_POINT(pf_info); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u lag_id: %u start.\n", __FUNCTION__, + pf_info->slot, pf_info->vport, sdt_no, lag_id); + + ZXIC_COMM_MEMSET(&lag_entry, 0, sizeof(ZXDH_LAG_T)); + + rc = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get"); + + rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue); + ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get"); + + lag_entry.hit_flag = 1; + lag_entry.bond_mode = LAG_LACP_MODE; + + rc = dpp_apt_dtb_eram_insert(&dev, queue, sdt_no, lag_id, &lag_entry); + ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_insert"); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u lag_id: %u success.\n", __FUNCTION__, + pf_info->slot, pf_info->vport, sdt_no, lag_id); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_lag_group_create); + +ZXIC_UINT32 dpp_lag_group_delete(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 lag_id) +{ + DPP_DEV_T dev = {0}; + + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 queue = 0; + ZXIC_UINT32 sdt_no = ZXDH_SDT_LAG_TABLE; + ZXIC_UINT32 rc = DPP_OK; + + ZXIC_COMM_CHECK_POINT(pf_info); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u lag_id: %u start.\n", __FUNCTION__, + pf_info->slot, pf_info->vport, sdt_no, lag_id); + + rc = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get"); + + rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue); + ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get"); + + rc = dpp_apt_dtb_eram_clear(&dev, queue, sdt_no, lag_id); + ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_clear"); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u lag_id: %u success.\n", __FUNCTION__, + pf_info->slot, pf_info->vport, sdt_no, lag_id); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_lag_group_delete); + +ZXIC_UINT32 dpp_lag_mode_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 lag_id, ZXIC_UINT8 mode) +{ + DPP_DEV_T dev = {0}; + + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 queue = 0; + ZXIC_UINT32 sdt_no = ZXDH_SDT_LAG_TABLE; + ZXIC_UINT32 rc = DPP_OK; + + ZXDH_LAG_T lag_entry = {0}; + + ZXIC_COMM_CHECK_POINT(pf_info); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u lag_id: %u mode: %u start.\n", __FUNCTION__, + pf_info->slot, pf_info->vport, sdt_no, lag_id, mode); + + ZXIC_COMM_CHECK_INDEX(mode, LAG_STANDBY_MODE, LAG_LACP_MODE); + + ZXIC_COMM_MEMSET(&lag_entry, 0, sizeof(ZXDH_LAG_T)); + + rc = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get"); + + rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue); + ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get"); + + rc = dpp_apt_dtb_eram_get(&dev, queue, sdt_no, lag_id, &lag_entry); + ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_get"); + + lag_entry.hit_flag = 1; + lag_entry.bond_mode = mode; + + rc = dpp_apt_dtb_eram_insert(&dev, queue, sdt_no, lag_id, &lag_entry); + ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_insert"); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u lag_id: %u mode: %u success.\n", __FUNCTION__, + pf_info->slot, pf_info->vport, sdt_no, lag_id, mode); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_lag_mode_set); + +ZXIC_UINT32 dpp_lag_group_hash_factor_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 lag_id, ZXIC_UINT8 factor) +{ + DPP_DEV_T dev = {0}; + + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 queue = 0; + ZXIC_UINT32 sdt_no = ZXDH_SDT_LAG_TABLE; + ZXIC_UINT32 rc = DPP_OK; + + ZXDH_LAG_T lag_entry = {0}; + + ZXIC_COMM_CHECK_POINT(pf_info); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u lag_id: %u factor: %u start.\n", __FUNCTION__, + pf_info->slot, pf_info->vport, sdt_no, lag_id, factor); + + ZXIC_COMM_MEMSET(&lag_entry, 0, sizeof(ZXDH_LAG_T)); + + rc = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get"); + + rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue); + ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get"); + + rc = dpp_apt_dtb_eram_get(&dev, queue, sdt_no, lag_id, &lag_entry); + ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_get"); + + lag_entry.hit_flag = 1; + lag_entry.hash_factor = factor; + + rc = dpp_apt_dtb_eram_insert(&dev, queue, sdt_no, lag_id, &lag_entry); + ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_insert"); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u lag_id: %u factor: %u success.\n", __FUNCTION__, + pf_info->slot, pf_info->vport, sdt_no, lag_id, factor); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_lag_group_hash_factor_set); + +ZXIC_UINT32 dpp_lag_group_member_add(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 lag_id, ZXIC_UINT8 panel_id) +{ + DPP_DEV_T dev = {0}; + + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 queue = 0; + ZXIC_UINT32 sdt_no = ZXDH_SDT_LAG_TABLE; + ZXIC_UINT32 rc = DPP_OK; + + ZXDH_LAG_T lag_entry = {0}; + + ZXIC_COMM_CHECK_POINT(pf_info); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u lag_id: %u panel_id: %u start.\n", __FUNCTION__, + pf_info->slot, pf_info->vport, sdt_no, lag_id, panel_id); + + ZXIC_COMM_MEMSET(&lag_entry, 0, sizeof(ZXDH_LAG_T)); + + rc = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get"); + + rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue); + ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get"); + + rc = dpp_apt_dtb_eram_get(&dev, queue, sdt_no, lag_id, &lag_entry); + ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_get"); + + lag_entry.hit_flag = 1; + + if ((lag_entry.member_bitmap & (1 << (15 - panel_id))) == 0) + { + lag_entry.member_bitmap |= (1 << (15 - panel_id)); + lag_entry.member_num++; + } + + rc = dpp_apt_dtb_eram_insert(&dev, queue, sdt_no, lag_id, &lag_entry); + ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_insert"); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u lag_id: %u panel_id: %u success.\n", __FUNCTION__, + pf_info->slot, pf_info->vport, sdt_no, lag_id, panel_id); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_lag_group_member_add); + +ZXIC_UINT32 dpp_lag_group_member_del(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 lag_id, ZXIC_UINT8 panel_id) +{ + DPP_DEV_T dev = {0}; + + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 queue = 0; + ZXIC_UINT32 sdt_no = ZXDH_SDT_LAG_TABLE; + ZXIC_UINT32 rc = DPP_OK; + + ZXDH_LAG_T lag_entry = {0}; + + ZXIC_COMM_CHECK_POINT(pf_info); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u lag_id: %u panel_id: %u start.\n", __FUNCTION__, + pf_info->slot, pf_info->vport, sdt_no, lag_id, panel_id); + + ZXIC_COMM_MEMSET(&lag_entry, 0, sizeof(ZXDH_LAG_T)); + + rc = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get"); + + rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue); + ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get"); + + rc = dpp_apt_dtb_eram_get(&dev, queue, sdt_no, lag_id, &lag_entry); + ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_get"); + + lag_entry.hit_flag = 1; + + if ((lag_entry.member_bitmap & (1 << (15 - panel_id))) != 0) + { + lag_entry.member_bitmap &= ~(1 << (15 - panel_id)); + lag_entry.member_num--; + } + + rc = dpp_apt_dtb_eram_insert(&dev, queue, sdt_no, lag_id, &lag_entry); + ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_insert"); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u lag_id: %u panel_id: %u success.\n", __FUNCTION__, + pf_info->slot, pf_info->vport, sdt_no, lag_id, panel_id); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_lag_group_member_del); diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_mac.c b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_mac.c new file mode 100644 index 0000000..ef2df77 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_mac.c @@ -0,0 +1,256 @@ +#include "dpp_drv_init.h" +#include "dpp_drv_acl.h" +#include "dpp_drv_hash.h" +#include "dpp_drv_eram.h" +#include "dpp_drv_sdt.h" +#include "dpp_dev.h" +#include "dpp_dtb.h" +#include "dpp_hash.h" +#include "dpp_dtb_table.h" +#include "dpp_dtb_table_api.h" +#include "dpp_tbl_comm.h" +#include "dpp_tbl_mac.h" +#include "dpp_tbl_api.h" + +ZXIC_VOID dpp_l2_entry_print(ZXDH_L2_ENTRY_T *l2_entry) +{ + ZXIC_COMM_TRACE_INFO("key--mac: %02x:%02x:%02x:%02x:%02x:%02x.\n", + l2_entry->key.dmac_addr[0], l2_entry->key.dmac_addr[1], + l2_entry->key.dmac_addr[2], l2_entry->key.dmac_addr[3], + l2_entry->key.dmac_addr[4], l2_entry->key.dmac_addr[5]); + ZXIC_COMM_TRACE_INFO("key--rsv: 0x%02x\n", l2_entry->key.rsv); + + ZXIC_COMM_TRACE_INFO("entry--vqm_vfid: 0x%02x\n", l2_entry->entry.vqm_vfid); + ZXIC_COMM_TRACE_INFO("entry--rsv: 0x%02x\n", l2_entry->entry.rsv); + ZXIC_COMM_TRACE_INFO("entry--hit_flag: 0x%02x\n", l2_entry->entry.hit_flag); +} + +ZXIC_UINT32 dpp_add_mac(DPP_PF_INFO_T* pf_info, ZXIC_CONST ZXIC_VOID *mac) +{ + DPP_DEV_T dev = {0}; + + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 queue = 0; + ZXIC_UINT32 sdt_no = 0; + ZXIC_UINT32 hash_index = 0; + ZXIC_UINT32 rc = DPP_OK; + + ZXDH_L2_ENTRY_T l2_entry = {0}; + + ZXIC_COMM_CHECK_POINT(pf_info); + ZXIC_COMM_CHECK_POINT(mac); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x start.\n", __FUNCTION__, pf_info->slot, pf_info->vport); + + ZXIC_COMM_MEMSET(&l2_entry, 0, sizeof(ZXDH_L2_ENTRY_T)); + + memmove(l2_entry.key.dmac_addr, mac, 6); + l2_entry.entry.vqm_vfid = VQM_VFID(pf_info->vport); + l2_entry.entry.hit_flag = 0x00; + + rc = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get"); + + rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue); + ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get"); + + rc = dpp_vport_hash_index_get(pf_info, &hash_index); + ZXIC_COMM_CHECK_RC(rc, "dpp_vport_hash_index_get"); + + sdt_no = ZXDH_SDT_L2_ENTRY_TABLE_PHYPORT0 + hash_index; + + rc = dpp_apt_dtb_hash_insert(&dev, queue, sdt_no, &l2_entry); + ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_hash_insert"); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u vqm_vfid: %u mac: %02x:%02x:%02x:%02x:%02x:%02x.\n", + __FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, + l2_entry.entry.vqm_vfid, + l2_entry.key.dmac_addr[0], l2_entry.key.dmac_addr[1], + l2_entry.key.dmac_addr[2], l2_entry.key.dmac_addr[3], + l2_entry.key.dmac_addr[4], l2_entry.key.dmac_addr[5]); + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x success.\n", __FUNCTION__, pf_info->slot, pf_info->vport); + return DPP_OK; +} +EXPORT_SYMBOL(dpp_add_mac); + +ZXIC_UINT32 dpp_del_mac(DPP_PF_INFO_T* pf_info, ZXIC_CONST ZXIC_VOID *mac) +{ + DPP_DEV_T dev = {0}; + + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 queue = 0; + ZXIC_UINT32 sdt_no = 0; + ZXIC_UINT32 hash_index = 0; + ZXIC_UINT32 rc = DPP_OK; + + ZXDH_L2_ENTRY_T l2_entry = {0}; + + ZXIC_COMM_CHECK_POINT(pf_info); + ZXIC_COMM_CHECK_POINT(mac); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x start.\n", __FUNCTION__, pf_info->slot, pf_info->vport); + + ZXIC_COMM_MEMSET(&l2_entry, 0, sizeof(ZXDH_L2_ENTRY_T)); + + memmove(l2_entry.key.dmac_addr, mac, 6); + + rc = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get"); + + rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue); + ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get"); + + rc = dpp_vport_hash_index_get(pf_info, &hash_index); + ZXIC_COMM_CHECK_RC(rc, "dpp_vport_hash_index_get"); + + sdt_no = ZXDH_SDT_L2_ENTRY_TABLE_PHYPORT0 + hash_index; + + rc = dpp_apt_dtb_hash_delete(&dev, queue, sdt_no, &l2_entry); + ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_hash_delete"); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u vqm_vfid: %u mac: %02x:%02x:%02x:%02x:%02x:%02x success.\n", + __FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, + l2_entry.entry.vqm_vfid, + l2_entry.key.dmac_addr[0], l2_entry.key.dmac_addr[1], + l2_entry.key.dmac_addr[2], l2_entry.key.dmac_addr[3], + l2_entry.key.dmac_addr[4], l2_entry.key.dmac_addr[5]); + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x success.\n", __FUNCTION__, pf_info->slot, pf_info->vport); + return DPP_OK; +} +EXPORT_SYMBOL(dpp_del_mac); + +ZXIC_UINT32 dpp_unicast_mac_dump(DPP_PF_INFO_T* pf_info, MAC_VPORT_INFO *p_mac_arr, ZXIC_UINT32 *p_mac_num) +{ + DPP_DEV_T dev = {0}; + + ZXIC_UINT32 rc = DPP_OK; + ZXIC_UINT32 index = 0; + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 queue_id = 0; + ZXIC_UINT32 hash_index = 0; + ZXIC_UINT32 sdt_no = 0; + ZXIC_UINT32 current_vqm_vfid = 0; + ZXIC_UINT16 current_vport = 0; + + ZXIC_UINT32 max_item_num = DTB_DUMP_UNICAST_MAC_DUMP_NUM; + ZXIC_UINT32 entryNum = 0; + ZXDH_L2_ENTRY_T *pL2DataArr = NULL; + ZXDH_L2_ENTRY_T *p_l2_temp_entry = NULL; + MAC_VPORT_INFO *p_temp_mac_info = NULL; + + ZXIC_COMM_CHECK_POINT(pf_info); + ZXIC_COMM_CHECK_POINT(p_mac_arr); + ZXIC_COMM_CHECK_POINT(p_mac_num); + + rc = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get"); + + rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue_id); + ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get"); + + rc = dpp_vport_hash_index_get(pf_info, &hash_index); + ZXIC_COMM_CHECK_RC(rc, "dpp_vport_hash_index_get"); + + sdt_no = ZXDH_SDT_L2_ENTRY_TABLE_PHYPORT0 + hash_index; + + pL2DataArr = (ZXDH_L2_ENTRY_T *)ZXIC_COMM_MALLOC(max_item_num * sizeof(ZXDH_L2_ENTRY_T)); + ZXIC_COMM_CHECK_POINT_NO_ASSERT(pL2DataArr); + + rc = dpp_apt_dtb_hash_table_unicast_mac_dump(&dev, queue_id, sdt_no, pL2DataArr, &entryNum); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_apt_dtb_hash_table_unicast_mac_dump", pL2DataArr); + + ZXIC_COMM_TRACE_INFO("unicast mac dump num:0x%x\n", entryNum); + + for(index = 0; index < entryNum; index ++) + { + p_l2_temp_entry = pL2DataArr + index; + p_temp_mac_info = p_mac_arr + index; + + ZXIC_COMM_TRACE_INFO("l2 entry index:0x%x\n", index); + dpp_l2_entry_print(p_l2_temp_entry); + + //从l2中获取mac地址给mac_info，再转换vport信息 + ZXIC_COMM_MEMCPY(p_temp_mac_info->addr, p_l2_temp_entry->key.dmac_addr, 6); + current_vqm_vfid = p_l2_temp_entry->entry.vqm_vfid; + + rc = dpp_vport_get_by_vqm_vfid(OWNER_PF_VPORT(pf_info->vport), current_vqm_vfid, ¤t_vport); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_vport_get_by_vqm_vfid", pL2DataArr); + p_temp_mac_info->vport = current_vport; + ZXIC_COMM_TRACE_INFO("current_vqm_vfid:0x%x --> current_vport:0x%x\n", current_vqm_vfid, current_vport); + } + + *p_mac_num = entryNum; + + ZXIC_COMM_FREE(pL2DataArr); + return DPP_OK; +} +EXPORT_SYMBOL(dpp_unicast_mac_dump); + +ZXIC_UINT32 dpp_unicast_all_mac_delete(DPP_PF_INFO_T* pf_info) +{ + DPP_DEV_T dev = {0}; + + ZXIC_UINT32 rc = DPP_OK; + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 queue_id = 0; + ZXIC_UINT32 sdt_no = 0; + ZXIC_UINT32 hash_index = 0; + + ZXIC_COMM_CHECK_POINT(pf_info); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x start.\n", __FUNCTION__, pf_info->slot, pf_info->vport); + + rc = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get"); + + rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue_id); + ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get"); + + rc = dpp_vport_hash_index_get(pf_info, &hash_index); + ZXIC_COMM_CHECK_RC(rc, "dpp_vport_hash_index_get"); + + sdt_no = ZXDH_SDT_L2_ENTRY_TABLE_PHYPORT0 + hash_index; + + rc = dpp_dtb_hash_offline_delete(&dev, queue_id, sdt_no); + ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_hash_offline_delete"); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x success.\n", __FUNCTION__, pf_info->slot, pf_info->vport); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_unicast_all_mac_delete); + +ZXIC_UINT32 dpp_unicast_all_mac_online_delete(DPP_PF_INFO_T* pf_info) +{ + DPP_DEV_T dev = {0}; + + ZXIC_UINT32 rc = DPP_OK; + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 queue_id = 0; + ZXIC_UINT32 sdt_no = 0; + ZXIC_UINT32 hash_index = 0; + + ZXIC_COMM_CHECK_POINT(pf_info); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x start.\n", __FUNCTION__, pf_info->slot, pf_info->vport); + + rc = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get"); + + rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue_id); + ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get"); + + rc = dpp_vport_hash_index_get(pf_info, &hash_index); + ZXIC_COMM_CHECK_RC(rc, "dpp_vport_hash_index_get"); + + sdt_no = ZXDH_SDT_L2_ENTRY_TABLE_PHYPORT0 + hash_index; + + rc = dpp_dtb_hash_online_delete(&dev, queue_id, sdt_no); + ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_hash_online_delete"); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x success.\n", __FUNCTION__, pf_info->slot, pf_info->vport); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_unicast_all_mac_online_delete); + diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_mc.c b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_mc.c new file mode 100644 index 0000000..d3d1423 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_mc.c @@ -0,0 +1,491 @@ +#include "dpp_drv_init.h" +#include "dpp_drv_acl.h" +#include "dpp_drv_hash.h" +#include "dpp_drv_eram.h" +#include "dpp_drv_sdt.h" +#include "dpp_dev.h" +#include "dpp_dtb.h" +#include "dpp_hash.h" +#include "dpp_dtb_table.h" +#include "dpp_dtb_table_api.h" +#include "dpp_tbl_comm.h" +#include "dpp_tbl_mc.h" +#include "dpp_tbl_bc.h" +#include "dpp_tbl_api.h" + +ZXIC_VOID dpp_mc_entry_print(ZXDH_MC_T *mc_entry) +{ + ZXIC_COMM_TRACE_INFO("key--mc_mac: %02x:%02x:%02x:%02x:%02x:%02x.\n", + mc_entry->key.mc_mac[0], mc_entry->key.mc_mac[1], + mc_entry->key.mc_mac[2], mc_entry->key.mc_mac[3], + mc_entry->key.mc_mac[4], mc_entry->key.mc_mac[5]); + ZXIC_COMM_TRACE_INFO("key--group_id: 0x%02x\n", mc_entry->key.group_id); + ZXIC_COMM_TRACE_INFO("key--rsv: 0x%02x\n", mc_entry->key.rsv); + + ZXIC_COMM_TRACE_INFO("entry--mc_bitmap: 0x%016llx\n", mc_entry->entry.mc_bitmap); + ZXIC_COMM_TRACE_INFO("entry--rsv2: 0x%02x\n", mc_entry->entry.rsv2); + ZXIC_COMM_TRACE_INFO("entry--rsv1: 0x%02x\n", mc_entry->entry.rsv1); + ZXIC_COMM_TRACE_INFO("entry--mc_pf_enable: 0x%02x\n", mc_entry->entry.mc_pf_enable); + ZXIC_COMM_TRACE_INFO("entry--hit_flag: 0x%02x\n", mc_entry->entry.hit_flag); +} + +ZXIC_UINT32 dpp_vport_mc_info_add(DPP_PF_INFO_T* pf_info, ZXIC_CONST ZXIC_VOID *mac) +{ + ZXIC_UINT32 index = 0; + ZXIC_UINT32 group_id = 0; + ZXIC_UINT32 vfunc_num = 0; + ZXIC_UINT32 rc = DPP_OK; + + DPP_VPORT_MC_TABLE_T* mc_table = NULL; + + ZXIC_COMM_CHECK_POINT(pf_info); + ZXIC_COMM_CHECK_POINT(mac); + + rc = dpp_vport_mc_table_get(pf_info, &mc_table); + ZXIC_COMM_CHECK_RC(rc, "dpp_vport_mc_table_get"); + ZXIC_COMM_CHECK_POINT(mc_table); + + vfunc_num = VFUNC_NUM(pf_info->vport); + ZXIC_COMM_CHECK_INDEX(vfunc_num, 0, (MC_GROUP_NUM * MC_MEMBER_NUM_IN_GROUP) - 1); + + group_id = vfunc_num / MC_MEMBER_NUM_IN_GROUP; + ZXIC_COMM_CHECK_INDEX(group_id, 0, MC_GROUP_NUM - 1); + + for (index = 0; index < MC_TABLE_SIZE; index++) + { + if (mc_table->mc_info[index].is_valid == 0) + { + continue; + } + if (ZXIC_COMM_MEMCMP(mc_table->mc_info[index].mac, mac, 6) == 0) + { + if (IS_PF(pf_info->vport)) + { + mc_table->mc_info[index].mc_pf_enable = 1; + } + else + { + mc_table->mc_info[index].mc_bitmap[group_id] |= ((ZXIC_UINT64)(1) << (MC_MEMBER_NUM_IN_GROUP - 1 - + (vfunc_num % MC_MEMBER_NUM_IN_GROUP))); + } + return DPP_OK; + } + } + + for (index = 0; index < MC_TABLE_SIZE; index++) + { + if (mc_table->mc_info[index].is_valid == 1) + { + continue; + } + mc_table->mc_info[index].is_valid = 1; + memmove(mc_table->mc_info[index].mac, mac, 6); + + if (IS_PF(pf_info->vport)) + { + mc_table->mc_info[index].mc_pf_enable = 1; + } + else + { + mc_table->mc_info[index].mc_bitmap[group_id] |= ((ZXIC_UINT64)(1) << (MC_MEMBER_NUM_IN_GROUP - 1 - + (vfunc_num % MC_MEMBER_NUM_IN_GROUP))); + } + + return DPP_OK; + } + + return DPP_RC_TABLE_RANGE_INVALID; +} + +ZXIC_UINT32 dpp_vport_mc_info_del(DPP_PF_INFO_T* pf_info, ZXIC_CONST ZXIC_VOID *mac) +{ + ZXIC_UINT32 index = 0; + ZXIC_UINT32 group_id = 0; + ZXIC_UINT32 vfunc_num = 0; + ZXIC_UINT32 rc = DPP_OK; + + DPP_VPORT_MC_TABLE_T* mc_table = NULL; + + ZXIC_COMM_CHECK_POINT(pf_info); + ZXIC_COMM_CHECK_POINT(mac); + + rc = dpp_vport_mc_table_get(pf_info, &mc_table); + ZXIC_COMM_CHECK_RC(rc, "dpp_vport_mc_table_get"); + ZXIC_COMM_CHECK_POINT(mc_table); + + vfunc_num = VFUNC_NUM(pf_info->vport); + ZXIC_COMM_CHECK_INDEX(vfunc_num, 0, (MC_GROUP_NUM * MC_MEMBER_NUM_IN_GROUP) - 1); + + group_id = vfunc_num / MC_MEMBER_NUM_IN_GROUP; + ZXIC_COMM_CHECK_INDEX(group_id, 0, MC_GROUP_NUM - 1); + + for (index = 0; index < MC_TABLE_SIZE; index++) + { + if (mc_table->mc_info[index].is_valid == 0) + { + continue; + } + if (ZXIC_COMM_MEMCMP(mc_table->mc_info[index].mac, mac, 6) == 0) + { + if (IS_PF(pf_info->vport)) + { + mc_table->mc_info[index].mc_pf_enable = 0; + } + else + { + mc_table->mc_info[index].mc_bitmap[group_id] &= ~((ZXIC_UINT64)(1) << (MC_MEMBER_NUM_IN_GROUP - 1 - + (vfunc_num % MC_MEMBER_NUM_IN_GROUP))); + } + + if ((mc_table->mc_info[index].mc_bitmap[0] == 0) && (mc_table->mc_info[index].mc_bitmap[1] == 0) && + (mc_table->mc_info[index].mc_bitmap[2] == 0) && (mc_table->mc_info[index].mc_bitmap[3] == 0) && + (mc_table->mc_info[index].mc_pf_enable == 0)) + { + mc_table->mc_info[index].is_valid = 0; + ZXIC_COMM_MEMSET(mc_table->mc_info[index].mac, 0x00, 6); + } + + return DPP_OK; + } + } + + return DPP_OK; +} + +ZXIC_UINT32 dpp_vport_mc_table_insert(DPP_PF_INFO_T* pf_info, ZXIC_CONST ZXIC_VOID *mac) +{ + DPP_DEV_T dev = {0}; + + ZXIC_UINT32 index = 0; + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 sdt_no = 0; + ZXIC_UINT32 queue = 0; + ZXIC_UINT32 group_id = 0; + ZXIC_UINT32 hash_index = 0; + ZXIC_UINT32 rc = DPP_OK; + + ZXDH_MC_T mc_entry = {0}; + DPP_VPORT_MC_TABLE_T* mc_table = NULL; + + ZXIC_COMM_CHECK_POINT(pf_info); + ZXIC_COMM_CHECK_POINT(mac); + + ZXIC_COMM_MEMSET(&mc_entry, 0, sizeof(ZXDH_MC_T)); + + rc = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get"); + + rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue); + ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get"); + + rc = dpp_vport_hash_index_get(pf_info, &hash_index); + ZXIC_COMM_CHECK_RC(rc, "dpp_vport_hash_index_get"); + + sdt_no = ZXDH_SDT_MC_TABLE_PHYPORT0 + hash_index; + + rc = dpp_vport_mc_table_get(pf_info, &mc_table); + ZXIC_COMM_CHECK_RC(rc, "dpp_vport_mc_table_get"); + ZXIC_COMM_CHECK_POINT(mc_table); + + for (index = 0; index < MC_TABLE_SIZE; index++) + { + if (mc_table->mc_info[index].is_valid == 0) + { + continue; + } + if (ZXIC_COMM_MEMCMP(mc_table->mc_info[index].mac, mac, 6) != 0) + { + continue; + } + for (group_id = 0; group_id < MC_GROUP_NUM; group_id++) + { + memmove(mc_entry.key.mc_mac, mac, 6); + mc_entry.key.group_id = group_id; + mc_entry.entry.hit_flag = 0x00; + mc_entry.entry.mc_pf_enable = mc_table->mc_info[index].mc_pf_enable; + mc_entry.entry.mc_bitmap = mc_table->mc_info[index].mc_bitmap[group_id]; + + rc = dpp_apt_dtb_hash_insert(&dev, queue, sdt_no, &mc_entry); + ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_hash_insert"); + + ZXIC_COMM_PRINT("[%s] slot %u vport: 0x%04x sdt_no: %u group_id: %u.\n", + __FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, group_id); + ZXIC_COMM_PRINT("[%s] mac: %02x:%02x:%02x:%02x:%02x:%02x.\n", __FUNCTION__, + mc_entry.key.mc_mac[0], mc_entry.key.mc_mac[1], + mc_entry.key.mc_mac[2], mc_entry.key.mc_mac[3], + mc_entry.key.mc_mac[4], mc_entry.key.mc_mac[5]); + ZXIC_COMM_PRINT("[%s] mc_bitmap: %02x %02x %02x %02x %02x %02x %02x %02x.\n", __FUNCTION__, + *((ZXIC_UINT8*)(&mc_entry.entry.mc_bitmap) + 7), + *((ZXIC_UINT8*)(&mc_entry.entry.mc_bitmap) + 6), + *((ZXIC_UINT8*)(&mc_entry.entry.mc_bitmap) + 5), + *((ZXIC_UINT8*)(&mc_entry.entry.mc_bitmap) + 4), + *((ZXIC_UINT8*)(&mc_entry.entry.mc_bitmap) + 3), + *((ZXIC_UINT8*)(&mc_entry.entry.mc_bitmap) + 2), + *((ZXIC_UINT8*)(&mc_entry.entry.mc_bitmap) + 1), + *((ZXIC_UINT8*)(&mc_entry.entry.mc_bitmap) + 0)); + } + return DPP_OK; + } + + for (group_id = 0; group_id < MC_GROUP_NUM; group_id++) + { + memmove(mc_entry.key.mc_mac, mac, 6); + mc_entry.key.group_id = group_id; + + rc = dpp_apt_dtb_hash_delete(&dev, queue, sdt_no, &mc_entry); + ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_hash_insert"); + + ZXIC_COMM_PRINT("[%s] delete mc table.\n", __FUNCTION__); + ZXIC_COMM_PRINT("[%s] slot %u vport: 0x%04x sdt_no: %u group_id: %u.\n", + __FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, group_id); + ZXIC_COMM_PRINT("[%s] mac: %02x:%02x:%02x:%02x:%02x:%02x.\n", __FUNCTION__, + mc_entry.key.mc_mac[0], mc_entry.key.mc_mac[1], + mc_entry.key.mc_mac[2], mc_entry.key.mc_mac[3], + mc_entry.key.mc_mac[4], mc_entry.key.mc_mac[5]); + } + + return DPP_OK; +} + +ZXIC_UINT32 dpp_multi_mac_add_member(DPP_PF_INFO_T* pf_info, ZXIC_CONST ZXIC_VOID *mac) +{ + ZXIC_UINT32 rc = DPP_OK; + + ZXIC_COMM_CHECK_POINT(pf_info); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x start.\n", __FUNCTION__, pf_info->slot, pf_info->vport); + + rc = dpp_vport_mc_info_add(pf_info, mac); + ZXIC_COMM_CHECK_RC(rc, "dpp_vport_mc_info_add"); + + rc = dpp_vport_mc_table_insert(pf_info, mac); + ZXIC_COMM_CHECK_RC(rc, "dpp_vport_mc_table_insert"); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x success.\n", __FUNCTION__, pf_info->slot, pf_info->vport); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_multi_mac_add_member); + +ZXIC_UINT32 dpp_multi_mac_del_member(DPP_PF_INFO_T* pf_info, ZXIC_CONST ZXIC_VOID *mac) +{ + ZXIC_UINT32 rc = DPP_OK; + + ZXIC_COMM_CHECK_POINT(pf_info); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x start.\n", __FUNCTION__, pf_info->slot, pf_info->vport); + + rc = dpp_vport_mc_info_del(pf_info, mac); + ZXIC_COMM_CHECK_RC(rc, "dpp_vport_mc_info_del"); + + rc = dpp_vport_mc_table_insert(pf_info, mac); + ZXIC_COMM_CHECK_RC(rc, "dpp_vport_mc_table_insert"); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x success.\n", __FUNCTION__, pf_info->slot, pf_info->vport); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_multi_mac_del_member); + +ZXIC_UINT32 dpp_mc_pf_flag_add(MC_PF_FLAG_MGR * p_flag_mgr, ZXIC_UINT32 index, ZXIC_UINT8 *mc_addr) +{ + ZXIC_COMM_MEMCPY(p_flag_mgr[index].mc_addr, mc_addr, 6); + p_flag_mgr[index].pf_flag = 1; + return DPP_OK; +} + +ZXIC_UINT32 dpp_mc_pf_flag_search(MC_PF_FLAG_MGR * p_flag_mgr, ZXIC_UINT8 *mc_addr) +{ + ZXIC_UINT32 index = 0; + + for(index = 0; index < MC_TABLE_SIZE; index ++) + { + if (ZXIC_COMM_MEMCMP(p_flag_mgr[index].mc_addr, mc_addr, 6) == 0) + { + break; + } + } + + if (index == MC_TABLE_SIZE) + { + ZXIC_COMM_TRACE_INFO("dpp_mc_pf_flag_search failed\n"); + return DPP_ERR; + } + + return DPP_OK; +} + +ZXIC_UINT32 dpp_multicast_mac_dump(DPP_PF_INFO_T* pf_info, MAC_VPORT_INFO *p_mac_arr, ZXIC_UINT32 *p_mac_num) +{ + DPP_DEV_T dev = {0}; + + ZXIC_UINT32 rc = DPP_OK; + ZXIC_UINT32 index = 0; + ZXIC_UINT32 mac_info_index = 0; + ZXIC_UINT32 num = 0; + + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 queue_id = 0; + ZXIC_UINT32 sdt_no = 0; + ZXIC_UINT32 hash_index = 0; + ZXIC_UINT32 current_group_id = 0; + ZXIC_UINT64 current_mc_bitmap = 0; + ZXIC_UINT32 current_mc_pf_enable = 0; + + ZXIC_UINT16 current_vport[64] = {0}; + ZXIC_UINT32 current_vport_num = 0; + + MC_PF_FLAG_MGR mc_pf_flag_mgr[MC_TABLE_SIZE] = {0}; + ZXIC_UINT32 pf_flag_count = 0; + + ZXIC_UINT32 max_item_num = DTB_DUMP_MULTICAST_MAC_DUMP_NUM; + ZXIC_UINT32 entryNum = 0; + + ZXDH_MC_T *pMcDataArr = NULL; + ZXDH_MC_T *p_mc_temp_entry = NULL; + MAC_VPORT_INFO *p_temp_mac_info = NULL; + + ZXIC_COMM_CHECK_POINT(pf_info); + ZXIC_COMM_CHECK_POINT(p_mac_arr); + ZXIC_COMM_CHECK_POINT(p_mac_num); + + rc = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get"); + + rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue_id); + ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get"); + + rc = dpp_vport_hash_index_get(pf_info, &hash_index); + ZXIC_COMM_CHECK_RC(rc, "dpp_vport_hash_index_get"); + + sdt_no = ZXDH_SDT_MC_TABLE_PHYPORT0 + hash_index; + + pMcDataArr = (ZXDH_MC_T *)ZXIC_COMM_MALLOC(max_item_num * sizeof(ZXDH_MC_T)); + ZXIC_COMM_CHECK_POINT_NO_ASSERT(pMcDataArr); + + rc = dpp_apt_dtb_hash_table_multicast_mac_dump(&dev, queue_id, sdt_no, pMcDataArr, &entryNum); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_apt_dtb_hash_table_multicast_mac_dump", pMcDataArr); + + ZXIC_COMM_TRACE_INFO("multicast mac dump num:0x%x\n", entryNum); + + for(index = 0; index < entryNum; index ++) + { + p_mc_temp_entry = pMcDataArr + index; + + ZXIC_COMM_TRACE_INFO("mc entry index:0x%x\n", index); + dpp_mc_entry_print(p_mc_temp_entry); + + // 从mc中获取mac地址给mac_info，再转换group_id 和 bitmap信息 + current_group_id = p_mc_temp_entry->key.group_id; + current_mc_bitmap = p_mc_temp_entry->entry.mc_bitmap; + current_mc_pf_enable = p_mc_temp_entry->entry.mc_pf_enable; + + if(current_mc_pf_enable) + { + p_temp_mac_info = p_mac_arr + mac_info_index; + if(dpp_mc_pf_flag_search(mc_pf_flag_mgr, p_mc_temp_entry->key.mc_mac)) + { + //没差中 + dpp_mc_pf_flag_add(mc_pf_flag_mgr, pf_flag_count, p_mc_temp_entry->key.mc_mac); + pf_flag_count++; + + ZXIC_COMM_MEMCPY(p_temp_mac_info->addr, p_mc_temp_entry->key.mc_mac, 6); + p_temp_mac_info->vport = OWNER_PF_VPORT(pf_info->vport); + + mac_info_index = mac_info_index + 1; + } + } + + rc = dpp_vport_get_by_mc_bitmap(OWNER_PF_VPORT(pf_info->vport), current_group_id, current_mc_bitmap, current_vport, ¤t_vport_num); + ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_vport_get_by_mc_bitmap", pMcDataArr); + + ZXIC_COMM_TRACE_INFO("index %d get vf num %d\n", index, current_vport_num); + + for(num = 0; num < current_vport_num; num++) + { + p_temp_mac_info = p_mac_arr + mac_info_index; + ZXIC_COMM_MEMCPY(p_temp_mac_info->addr, p_mc_temp_entry->key.mc_mac, 6); + p_temp_mac_info->vport = current_vport[num]; + mac_info_index = mac_info_index + 1; + } + ZXIC_COMM_TRACE_INFO("mac_info_index 0x%x\n", mac_info_index); + + } + + ZXIC_COMM_FREE(pMcDataArr); + + *p_mac_num = mac_info_index; + + ZXIC_COMM_TRACE_INFO("dump mac num: 0x%x\n", *p_mac_num); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_multicast_mac_dump); + +ZXIC_UINT32 dpp_multicast_all_mac_delete(DPP_PF_INFO_T* pf_info) +{ + DPP_DEV_T dev = {0}; + + ZXIC_UINT32 rc = DPP_OK; + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 queue_id = 0; + ZXIC_UINT32 sdt_no = 0; + ZXIC_UINT32 hash_index = 0; + + ZXIC_COMM_CHECK_POINT(pf_info); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x start.\n", __FUNCTION__, pf_info->slot, pf_info->vport); + + rc = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get"); + + rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue_id); + ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get"); + + rc = dpp_vport_hash_index_get(pf_info, &hash_index); + ZXIC_COMM_CHECK_RC(rc, "dpp_vport_hash_index_get"); + + sdt_no = ZXDH_SDT_MC_TABLE_PHYPORT0 + hash_index; + + rc = dpp_dtb_hash_offline_delete(&dev, queue_id, sdt_no); + ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_hash_offline_delete"); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x success.\n", __FUNCTION__, pf_info->slot, pf_info->vport); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_multicast_all_mac_delete); + +ZXIC_UINT32 dpp_multicast_all_mac_online_delete(DPP_PF_INFO_T* pf_info) +{ + DPP_DEV_T dev = {0}; + + ZXIC_UINT32 rc = DPP_OK; + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 queue_id = 0; + ZXIC_UINT32 sdt_no = 0; + ZXIC_UINT32 hash_index = 0; + + ZXIC_COMM_CHECK_POINT(pf_info); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x start.\n", __FUNCTION__, pf_info->slot, pf_info->vport); + + rc = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get"); + + rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue_id); + ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get"); + + rc = dpp_vport_hash_index_get(pf_info, &hash_index); + ZXIC_COMM_CHECK_RC(rc, "dpp_vport_hash_index_get"); + + sdt_no = ZXDH_SDT_MC_TABLE_PHYPORT0 + hash_index; + + rc = dpp_dtb_hash_online_delete(&dev, queue_id, sdt_no); + ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_hash_online_delete"); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x success.\n", __FUNCTION__, pf_info->slot, pf_info->vport); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_multicast_all_mac_online_delete); diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_panel.c b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_panel.c new file mode 100644 index 0000000..12f8c46 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_panel.c @@ -0,0 +1,135 @@ +#include "dpp_drv_init.h" +#include "dpp_drv_acl.h" +#include "dpp_drv_hash.h" +#include "dpp_drv_eram.h" +#include "dpp_drv_sdt.h" +#include "dpp_dev.h" +#include "dpp_dtb.h" +#include "dpp_hash.h" +#include "dpp_dtb_table.h" +#include "dpp_dtb_table_api.h" +#include "dpp_tbl_api.h" +#include "dpp_tbl_comm.h" +#include "dpp_tbl_port.h" +#include "dpp_tbl_panel.h" +#include "dpp_tbl_diag.h" + +ZXIC_UINT32 dpp_panel_bond_vport(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 panel_id) +{ + ZXIC_UINT32 rc = DPP_OK; + + ZXIC_COMM_CHECK_POINT(pf_info); + + rc = dpp_egr_port_attr_set(pf_info, EGR_FLAG_PANEL_ID, panel_id); + ZXIC_COMM_CHECK_RC(rc, "dpp_egr_port_attr_set"); + + rc = dpp_panel_attr_set(pf_info, panel_id, PANEL_FLAG_PF_VQM_VFID, OWNER_PF_VQM_VFID(pf_info->vport)); + ZXIC_COMM_CHECK_RC(rc, "dpp_panel_attr_set"); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_panel_bond_vport); + +ZXIC_UINT32 dpp_panel_hardware_bond_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 panel_id, ZXIC_UINT8 enable) +{ + ZXIC_UINT32 rc = DPP_OK; + ZXIC_UINT32 attr = PANEL_FLAG_HW_BOND_ENABLE; + + rc = dpp_panel_attr_set(pf_info, panel_id, attr, enable); + ZXIC_COMM_CHECK_RC(rc, "dpp_panel_attr_set"); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_panel_hardware_bond_set); + +ZXIC_UINT32 dpp_panel_bond_pf_vqm_vfid_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 panel_id, ZXIC_UINT16 vqm_vfid) +{ + ZXIC_UINT32 rc = DPP_OK; + ZXIC_UINT32 attr = PANEL_FLAG_BOND_PF_VQM_VFID; + + rc = dpp_panel_attr_set(pf_info, panel_id, attr, vqm_vfid); + ZXIC_COMM_CHECK_RC(rc, "dpp_panel_attr_set"); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_panel_bond_pf_vqm_vfid_set); + +ZXIC_UINT32 dpp_panel_bond_pf_memport_qid_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 panel_id, ZXIC_UINT16 qid) +{ + ZXIC_UINT32 rc = DPP_OK; + ZXIC_UINT32 attr = PANEL_FLAG_PF_MEMPORT_QID; + + rc = dpp_panel_attr_set(pf_info, panel_id, attr, qid); + ZXIC_COMM_CHECK_RC(rc, "dpp_panel_attr_set"); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_panel_bond_pf_memport_qid_set); + +ZXIC_UINT32 dpp_panel_ovs_pf_vqm_vfid_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 panel_id, ZXIC_UINT16 vqm_vfid) +{ + ZXIC_UINT32 rc = DPP_OK; + ZXIC_UINT32 attr = PANEL_FLAG_OVS_PF_VFID; + + rc = dpp_panel_attr_set(pf_info, panel_id, attr, vqm_vfid); + ZXIC_COMM_CHECK_RC(rc, "dpp_panel_attr_set"); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_panel_ovs_pf_vqm_vfid_set); + +ZXIC_UINT32 dpp_panel_attr_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 panel_id, ZXIC_UINT32 attr, ZXIC_UINT32 value) +{ + DPP_DEV_T dev = {0}; + + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 queue = 0; + ZXIC_UINT32 sdt_no = ZXDH_SDT_PANEL_PORT_ATTR_TABLE; + ZXIC_UINT32 rc = DPP_OK; + + ZXDH_PANEL_PORT_T panel_port = {0}; + + ZXIC_COMM_CHECK_POINT(pf_info); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u index: %u attr: %s(%u) value: %u start.\n", + __FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, panel_id, + dpp_vport_panel_table_attr_name_get(attr), attr, value); + + ZXIC_COMM_CHECK_INDEX(attr, 0, (ZXIC_UINT32)((sizeof(ZXDH_PANEL_PORT_T) / sizeof(ZXIC_UINT32)) - 1)); + + rc = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get"); + + rc = zxic_comm_mutex_lock(DEV_PCIE_MUTEX(&dev)); + ZXIC_COMM_CHECK_RC(rc, "zxic_comm_mutex_lock"); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u index: %u attr: %s(%u) value: %u lock.\n", + __FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, panel_id, + dpp_vport_panel_table_attr_name_get(attr), attr, value); + + rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue); + ZXIC_COMM_CHECK_RC_UNLOCK(rc, "dpp_dtb_queue_id_get", DEV_PCIE_MUTEX(&dev)); + + rc = dpp_apt_dtb_eram_get(&dev, queue, sdt_no, panel_id, &panel_port); + ZXIC_COMM_CHECK_RC_UNLOCK(rc, "dpp_apt_dtb_eram_get", DEV_PCIE_MUTEX(&dev)); + + panel_port.hit_flag = 1; + *((((ZXIC_UINT32 *)(&panel_port)) + attr)) = value; + + rc = dpp_apt_dtb_eram_insert(&dev, queue, sdt_no, panel_id, &panel_port); + ZXIC_COMM_CHECK_RC_UNLOCK(rc, "dpp_apt_dtb_eram_insert", DEV_PCIE_MUTEX(&dev)); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u index: %u attr: %s(%u) value: %u unlock.\n", + __FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, panel_id, + dpp_vport_panel_table_attr_name_get(attr), attr, value); + + rc = zxic_comm_mutex_unlock(DEV_PCIE_MUTEX(&dev)); + ZXIC_COMM_CHECK_RC(rc, "zxic_comm_mutex_unlock"); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u index: %u attr: %s(%u) value: %u success.\n", + __FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, panel_id, + dpp_vport_panel_table_attr_name_get(attr), attr, value); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_panel_attr_set); diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_port.c b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_port.c new file mode 100644 index 0000000..976499f --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_port.c @@ -0,0 +1,333 @@ +#include "dpp_drv_init.h" +#include "dpp_drv_acl.h" +#include "dpp_drv_hash.h" +#include "dpp_drv_eram.h" +#include "dpp_drv_sdt.h" +#include "dpp_dev.h" +#include "dpp_dtb.h" +#include "dpp_hash.h" +#include "dpp_dtb_table.h" +#include "dpp_dtb_table_api.h" +#include "dpp_tbl_api.h" +#include "dpp_tbl_comm.h" +#include "dpp_tbl_port.h" +#include "dpp_tbl_diag.h" + +ZXIC_UINT32 dpp_vport_create(DPP_PF_INFO_T* pf_info) +{ + ZXIC_UINT32 rc = DPP_OK; + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x start.\n", __FUNCTION__, pf_info->slot, pf_info->vport); + + rc = dpp_vport_create_by_vqm_vfid(pf_info, VQM_VFID(pf_info->vport)); + ZXIC_COMM_CHECK_RC(rc, "dpp_vport_create_by_vqm_vfid"); + + rc = dpp_egr_port_attr_set(pf_info, EGR_FLAG_IS_VF, !IS_PF(pf_info->vport)); + ZXIC_COMM_CHECK_RC(rc, "dpp_egr_port_attr_set"); + + rc = dpp_egr_port_attr_set(pf_info, EGR_FLAG_PF_VQM_VFID, OWNER_PF_VQM_VFID(pf_info->vport)); + ZXIC_COMM_CHECK_RC(rc, "dpp_egr_port_attr_set"); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x success.\n", __FUNCTION__, pf_info->slot, pf_info->vport); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_vport_create); + +ZXIC_UINT32 dpp_vport_create_by_vqm_vfid(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 vqm_vfid) +{ + DPP_DEV_T dev = {0}; + + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 queue = 0; + ZXIC_UINT32 sdt_no = ZXDH_SDT_VPORT_ATTR_TABLE; + ZXIC_UINT32 index = vqm_vfid; + ZXIC_UINT32 rc = DPP_OK; + + ZXDH_VPORT_T port_attr_entry = {0}; + + ZXIC_COMM_CHECK_POINT(pf_info); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u index: %u start.\n", __FUNCTION__, + pf_info->slot, pf_info->vport, sdt_no, index); + + ZXIC_COMM_MEMSET(&port_attr_entry, 0, sizeof(ZXDH_VPORT_T)); + + rc = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get"); + + rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue); + ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get"); + + port_attr_entry.hit_flag = 1; + + rc = dpp_apt_dtb_eram_insert(&dev, queue, sdt_no, index, &port_attr_entry); + ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_insert"); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u index: %u success.\n", __FUNCTION__, + pf_info->slot, pf_info->vport, sdt_no, index); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_vport_create_by_vqm_vfid); + +ZXIC_UINT32 dpp_vport_delete(DPP_PF_INFO_T* pf_info) +{ + DPP_DEV_T dev = {0}; + + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 queue = 0; + ZXIC_UINT32 sdt_no = ZXDH_SDT_VPORT_ATTR_TABLE; + ZXIC_UINT32 index = 0; + ZXIC_UINT32 rc = DPP_OK; + + ZXIC_COMM_CHECK_POINT(pf_info); + + index = VQM_VFID(pf_info->vport); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u index: %u start.\n", __FUNCTION__, + pf_info->slot, pf_info->vport, sdt_no, index); + + rc = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get"); + + rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue); + ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get"); + + rc = dpp_apt_dtb_eram_clear(&dev, queue, sdt_no, index); + ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_clear"); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u index: %u success.\n", __FUNCTION__, + pf_info->slot, pf_info->vport, sdt_no, index); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_vport_delete); + +ZXIC_UINT32 dpp_egr_port_attr_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 attr, ZXIC_UINT32 value) +{ + DPP_DEV_T dev = {0}; + + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 queue = 0; + ZXIC_UINT32 sdt_no = ZXDH_SDT_VPORT_ATTR_TABLE; + ZXIC_UINT32 index = 0; + ZXIC_UINT32 rc = DPP_OK; + + ZXDH_VPORT_T port_attr_entry = {0}; + + ZXIC_COMM_CHECK_POINT(pf_info); + + index = VQM_VFID(pf_info->vport); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u index: %u attr: %s(%u) value: %u start.\n", + __FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, index, + dpp_vport_table_attr_name_get(attr), attr, value); + + ZXIC_COMM_CHECK_INDEX(attr, 0, (ZXIC_UINT32)((sizeof(ZXDH_VPORT_T) / sizeof(ZXIC_UINT32)) - 1)); + + rc = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get"); + + rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue); + ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get"); + + rc = dpp_apt_dtb_eram_get(&dev, queue, sdt_no, index, &port_attr_entry); + ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_get"); + + port_attr_entry.hit_flag = 1; + *((((ZXIC_UINT32 *)(&port_attr_entry)) + attr)) = value; + + rc = dpp_apt_dtb_eram_insert(&dev, queue, sdt_no, index, &port_attr_entry); + ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_insert"); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u index: %u attr: %s(%u) value: %u success.\n", + __FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, index, + dpp_vport_table_attr_name_get(attr), attr, value); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_egr_port_attr_set); + +ZXIC_UINT32 dpp_egr_port_attr_get(DPP_PF_INFO_T* pf_info, ZXDH_VPORT_T *port_attr_entry) +{ + DPP_DEV_T dev = {0}; + + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 queue = 0; + ZXIC_UINT32 sdt_no = ZXDH_SDT_VPORT_ATTR_TABLE; + ZXIC_UINT32 index = 0; + ZXIC_UINT32 rc = DPP_OK; + + ZXIC_COMM_CHECK_POINT(pf_info); + ZXIC_COMM_CHECK_POINT(port_attr_entry); + + index = VQM_VFID(pf_info->vport); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x index: %u start.\n", + __FUNCTION__, pf_info->slot, pf_info->vport, index); + + rc = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get"); + + rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue); + ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get"); + + rc = dpp_apt_dtb_eram_get(&dev, queue, sdt_no, index, port_attr_entry); + ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_get"); + ZXIC_COMM_CHECK_INDEX_NOT_EQUAL(port_attr_entry->hit_flag, 1); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x index: %u success.\n", + __FUNCTION__, pf_info->slot, pf_info->vport, index); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_egr_port_attr_get); + +ZXIC_UINT32 dpp_rx_flow_hash_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 hash_mode) +{ + ZXIC_UINT32 rc = DPP_OK; + ZXIC_UINT32 attr = EGR_FLAG_RSS_HASH_FACTOR; + + rc = dpp_egr_port_attr_set(pf_info, attr, hash_mode & 0xff); + ZXIC_COMM_CHECK_RC(rc, "dpp_egr_port_attr_set"); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_rx_flow_hash_set); + +ZXIC_UINT32 dpp_rx_flow_hash_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 *hash_mode) +{ + ZXIC_UINT32 rc = DPP_OK; + + ZXDH_VPORT_T port_attr_entry = {0}; + + ZXIC_COMM_CHECK_POINT(pf_info); + ZXIC_COMM_CHECK_POINT(hash_mode); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x start.\n", + __FUNCTION__, pf_info->slot, pf_info->vport); + + rc = dpp_egr_port_attr_get(pf_info, &port_attr_entry); + ZXIC_COMM_CHECK_RC(rc, "dpp_egr_port_attr_get"); + + *hash_mode = port_attr_entry.rss_hash_factor; + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x factor: %u.\n", + __FUNCTION__, pf_info->slot, pf_info->vport, *hash_mode); + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x success.\n", + __FUNCTION__, pf_info->slot, pf_info->vport); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_rx_flow_hash_get); + +ZXIC_UINT32 dpp_vport_hash_index_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 *hash_index) +{ + ZXIC_UINT32 rc = DPP_OK; + + ZXDH_VPORT_T port_attr_entry = {0}; + + ZXIC_COMM_CHECK_POINT(pf_info); + ZXIC_COMM_CHECK_POINT(hash_index); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x start.\n", + __FUNCTION__, pf_info->slot, pf_info->vport); + + rc = dpp_egr_port_attr_get(pf_info, &port_attr_entry); + ZXIC_COMM_CHECK_RC(rc, "dpp_egr_port_attr_get"); + + *hash_index = port_attr_entry.hash_search_index; + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x hash_search_index: %u.\n", + __FUNCTION__, pf_info->slot, pf_info->vport, *hash_index); + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x success.\n", + __FUNCTION__, pf_info->slot, pf_info->vport); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_vport_hash_index_get); + +ZXIC_UINT32 dpp_vport_hash_funcs_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 funcs) +{ + ZXIC_UINT32 rc = DPP_OK; + ZXIC_UINT32 attr = EGR_FLAG_HASH_ALG; + + rc = dpp_egr_port_attr_set(pf_info, attr, funcs & 0x0f); + ZXIC_COMM_CHECK_RC(rc, "dpp_egr_port_attr_set"); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_vport_hash_funcs_set); + +ZXIC_UINT32 dpp_vport_rss_en_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 enable) +{ + ZXIC_UINT32 rc = DPP_OK; + ZXIC_UINT32 attr = EGR_FLAG_RSS_EN_OFF; + + rc = dpp_egr_port_attr_set(pf_info, attr, enable & 0x1); + ZXIC_COMM_CHECK_RC(rc, "dpp_egr_port_attr_set"); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_vport_rss_en_set); + +ZXIC_UINT32 dpp_vport_virtio_en_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 enable) +{ + ZXIC_UINT32 rc = DPP_OK; + ZXIC_UINT32 attr = EGR_FLAG_VIRTION_EN_OFF; + + rc = dpp_egr_port_attr_set(pf_info, attr, enable & 0x1); + ZXIC_COMM_CHECK_RC(rc, "dpp_egr_port_attr_set"); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_vport_virtio_en_set); + +ZXIC_UINT32 dpp_vport_virtio_version_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 version) +{ + ZXIC_UINT32 rc = DPP_OK; + ZXIC_UINT32 attr = EGR_FLAG_VIRTION_VERSION; + + rc = dpp_egr_port_attr_set(pf_info, attr, version & 0x3); + ZXIC_COMM_CHECK_RC(rc, "dpp_egr_port_attr_set"); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_vport_virtio_version_set); + +ZXIC_UINT32 dpp_vport_vlan_filter_en_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 enable) +{ + ZXIC_UINT32 rc = DPP_OK; + ZXIC_UINT32 attr = EGR_FLAG_VLAN_FILTER_EN_OFF; + + rc = dpp_egr_port_attr_set(pf_info, attr, enable & 0x1); + ZXIC_COMM_CHECK_RC(rc, "dpp_egr_port_attr_set"); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_vport_vlan_filter_en_set); + +ZXIC_UINT32 dpp_vport_vlan_qinq_en_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 enable) +{ + ZXIC_UINT32 rc = DPP_OK; + ZXIC_UINT32 attr = EGR_FLAG_QINQ_VLAN_STRIP_OFFLOAD; + + rc = dpp_egr_port_attr_set(pf_info, attr, enable & 0x1); + ZXIC_COMM_CHECK_RC(rc, "dpp_egr_port_attr_set"); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_vport_vlan_qinq_en_set); + +ZXIC_UINT32 dpp_vport_vlan_strip_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 enable) +{ + ZXIC_UINT32 rc = DPP_OK; + ZXIC_UINT32 attr = EGR_FLAG_VLAN_STRIP_OFFLOAD; + + rc = dpp_egr_port_attr_set(pf_info, attr, enable & 0x1); + ZXIC_COMM_CHECK_RC(rc, "dpp_egr_port_attr_set"); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_vport_vlan_strip_set); diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_promisc.c b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_promisc.c new file mode 100644 index 0000000..19878da --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_promisc.c @@ -0,0 +1,145 @@ +#include "dpp_drv_init.h" +#include "dpp_drv_acl.h" +#include "dpp_drv_hash.h" +#include "dpp_drv_eram.h" +#include "dpp_drv_sdt.h" +#include "dpp_dev.h" +#include "dpp_dtb.h" +#include "dpp_hash.h" +#include "dpp_dtb_table.h" +#include "dpp_dtb_table_api.h" +#include "dpp_tbl_api.h" +#include "dpp_tbl_comm.h" +#include "dpp_tbl_promisc.h" + +ZXIC_UINT32 dpp_vport_promisc_info_set(DPP_PF_INFO_T* pf_info, DPP_VPORT_PROMISC_TABLE_T* promisc_table, ZXIC_UINT32 enable) +{ + ZXIC_UINT32 group_id = 0; + ZXIC_UINT32 vfunc_num = 0; + ZXIC_UINT64 bitmap_mask = 0; + + ZXIC_COMM_CHECK_POINT(pf_info); + ZXIC_COMM_CHECK_POINT(promisc_table); + ZXIC_COMM_CHECK_INDEX(enable, 0, 1); + + vfunc_num = VFUNC_NUM(pf_info->vport); + ZXIC_COMM_CHECK_INDEX(vfunc_num, 0, (PROMISC_GROUP_NUM * PROMISC_MEMBER_NUM_IN_GROUP) - 1); + + group_id = vfunc_num / PROMISC_MEMBER_NUM_IN_GROUP; + ZXIC_COMM_CHECK_INDEX(group_id, 0, PROMISC_GROUP_NUM - 1); + + bitmap_mask = ((ZXIC_UINT64)(1) << (PROMISC_MEMBER_NUM_IN_GROUP - 1 - (vfunc_num % PROMISC_MEMBER_NUM_IN_GROUP))); + + if (IS_PF(pf_info->vport)) + { + promisc_table->promisc_info.pf_enable = enable; + } + else + { + promisc_table->promisc_info.bitmap[group_id] = (enable == 1) ? + (promisc_table->promisc_info.bitmap[group_id] | bitmap_mask) : + (promisc_table->promisc_info.bitmap[group_id] & ~bitmap_mask); + } + + return DPP_OK; +} + +ZXIC_UINT32 dpp_vport_promisc_table_insert(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 sdt_no, DPP_VPORT_PROMISC_TABLE_T* promisc_table) +{ + DPP_DEV_T dev = {0}; + + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 group_id = 0; + ZXIC_UINT32 index = 0; + ZXIC_UINT32 queue = 0; + ZXIC_UINT32 rc = DPP_OK; + + ZXDH_PROMISC_T promisc_entry = {0}; + + ZXIC_COMM_CHECK_POINT(pf_info); + ZXIC_COMM_CHECK_POINT(promisc_table); + + rc = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get"); + + rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue); + ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get"); + + for (group_id = 0; group_id < PROMISC_GROUP_NUM; group_id++) + { + index = (((OWNER_PF_VQM_VFID(pf_info->vport) - PF_VQM_VFID_OFFSET) << 2)| group_id); + promisc_entry.hit_flag = 1; + promisc_entry.pf_enable = promisc_table->promisc_info.pf_enable; + promisc_entry.bitmap = promisc_table->promisc_info.bitmap[group_id]; + + rc = dpp_apt_dtb_eram_insert(&dev, queue, sdt_no, index, &promisc_entry); + ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_insert"); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u group_id: %u index: 0x%02x.\n", + __FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, group_id, index); + ZXIC_COMM_PRINT("[%s] pf_enable: %u bitmap: %02x %02x %02x %02x %02x %02x %02x %02x.\n", __FUNCTION__, + promisc_entry.pf_enable, + *((ZXIC_UINT8*)(&promisc_entry.bitmap) + 7), + *((ZXIC_UINT8*)(&promisc_entry.bitmap) + 6), + *((ZXIC_UINT8*)(&promisc_entry.bitmap) + 5), + *((ZXIC_UINT8*)(&promisc_entry.bitmap) + 4), + *((ZXIC_UINT8*)(&promisc_entry.bitmap) + 3), + *((ZXIC_UINT8*)(&promisc_entry.bitmap) + 2), + *((ZXIC_UINT8*)(&promisc_entry.bitmap) + 1), + *((ZXIC_UINT8*)(&promisc_entry.bitmap) + 0)); + } + + return DPP_OK; +} + +ZXIC_UINT32 dpp_vport_uc_promisc_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 enable) +{ + ZXIC_UINT32 rc = DPP_OK; + DPP_VPORT_PROMISC_TABLE_T* promisc_table = NULL; + + ZXIC_COMM_CHECK_POINT(pf_info); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x enable: %u start.\n", + __FUNCTION__, pf_info->slot, pf_info->vport, enable); + + rc = dpp_vport_uc_promisc_table_get(pf_info, &promisc_table); + ZXIC_COMM_CHECK_RC(rc, "dpp_vport_uc_promisc_table_get"); + + rc = dpp_vport_promisc_info_set(pf_info, promisc_table, enable); + ZXIC_COMM_CHECK_RC(rc, "dpp_vport_promisc_info_set"); + + rc = dpp_vport_promisc_table_insert(pf_info, ZXDH_SDT_UC_PROMISC_TABLE, promisc_table); + ZXIC_COMM_CHECK_RC(rc, "dpp_vport_promisc_table_insert"); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x enable: %u success.\n", + __FUNCTION__, pf_info->slot, pf_info->vport, enable); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_vport_uc_promisc_set); + +ZXIC_UINT32 dpp_vport_mc_promisc_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 enable) +{ + ZXIC_UINT32 rc = DPP_OK; + DPP_VPORT_PROMISC_TABLE_T* promisc_table = NULL; + + ZXIC_COMM_CHECK_POINT(pf_info); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x enable: %u start.\n", + __FUNCTION__, pf_info->slot, pf_info->vport, enable); + + rc = dpp_vport_mc_promisc_table_get(pf_info, &promisc_table); + ZXIC_COMM_CHECK_RC(rc, "dpp_vport_mc_promisc_table_get"); + + rc = dpp_vport_promisc_info_set(pf_info, promisc_table, enable); + ZXIC_COMM_CHECK_RC(rc, "dpp_vport_promisc_info_set"); + + rc = dpp_vport_promisc_table_insert(pf_info, ZXDH_SDT_MC_PROMISC_TABLE, promisc_table); + ZXIC_COMM_CHECK_RC(rc, "dpp_vport_promisc_table_insert"); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x enable: %u success.\n", + __FUNCTION__, pf_info->slot, pf_info->vport, enable); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_vport_mc_promisc_set); diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_ptp.c b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_ptp.c new file mode 100644 index 0000000..0e09625 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_ptp.c @@ -0,0 +1,47 @@ +#include "dpp_drv_init.h" +#include "dpp_drv_acl.h" +#include "dpp_drv_hash.h" +#include "dpp_drv_eram.h" +#include "dpp_drv_sdt.h" +#include "dpp_dev.h" +#include "dpp_dtb.h" +#include "dpp_hash.h" +#include "dpp_dtb_table.h" +#include "dpp_dtb_table_api.h" +#include "dpp_tbl_api.h" +#include "dpp_tbl_comm.h" +#include "dpp_tbl_ptp.h" + +ZXIC_UINT32 dpp_ptp_port_vfid_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 ptp_port_vfid) +{ + ZXIC_UINT32 rc = DPP_OK; + ZXIC_UINT32 attr = PANEL_FLAG_PTP_PORT_VFID; + + ZXDH_VPORT_T port_attr_entry = {0}; + + rc = dpp_egr_port_attr_get(pf_info, &port_attr_entry); + ZXIC_COMM_CHECK_RC(rc, "dpp_egr_port_attr_get"); + + rc = dpp_panel_attr_set(pf_info, port_attr_entry.panel_id, attr, ptp_port_vfid); + ZXIC_COMM_CHECK_RC(rc, "dpp_panel_attr_set"); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_ptp_port_vfid_set); + +ZXIC_UINT32 dpp_ptp_tc_enable_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 ptp_tc_enable) +{ + ZXIC_UINT32 rc = DPP_OK; + ZXIC_UINT32 attr = PANEL_FLAG_PTP_TC_ENABLE; + + ZXDH_VPORT_T port_attr_entry = {0}; + + rc = dpp_egr_port_attr_get(pf_info, &port_attr_entry); + ZXIC_COMM_CHECK_RC(rc, "dpp_egr_port_attr_get"); + + rc = dpp_panel_attr_set(pf_info, port_attr_entry.panel_id, attr, ptp_tc_enable); + ZXIC_COMM_CHECK_RC(rc, "dpp_panel_attr_set"); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_ptp_tc_enable_set); diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_qid.c b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_qid.c new file mode 100644 index 0000000..85d797b --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_qid.c @@ -0,0 +1,208 @@ +#include "dpp_drv_init.h" +#include "dpp_drv_acl.h" +#include "dpp_drv_hash.h" +#include "dpp_drv_eram.h" +#include "dpp_drv_sdt.h" +#include "dpp_dev.h" +#include "dpp_ppu.h" +#include "dpp_dtb.h" +#include "dpp_hash.h" +#include "dpp_dtb_table.h" +#include "dpp_dtb_table_api.h" +#include "dpp_tbl_comm.h" +#include "dpp_tbl_qid.h" + +ZXIC_UINT32 dpp_rxfh_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 *queue_list, ZXIC_UINT32 queue_num) +{ + DPP_DEV_T dev = {0}; + + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 i = 0; + ZXIC_UINT32 queue = 0; + ZXIC_UINT32 group_id = 0; + ZXIC_UINT32 sdt_no = ZXDH_SDT_RSS_TO_VQID_TABLE; + ZXIC_UINT32 index = 0; + ZXIC_UINT32 rc = DPP_OK; + + ZXDH_RSS_TO_VQID_T rss_to_vqid_entry = {0}; + + ZXIC_COMM_CHECK_POINT(pf_info); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x start.\n", __FUNCTION__, pf_info->slot, pf_info->vport); + + ZXIC_COMM_CHECK_POINT(queue_list); + + rc = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get"); + + rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue); + ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get"); + + index = VQM_VFID(pf_info->vport) * RSS_TO_VQID_GROUP_NUM; + rss_to_vqid_entry.hit_flag = 1; + + for (group_id = 0; group_id < RSS_TO_VQID_GROUP_NUM; group_id++) + { + for (i = 0; i < 8; i++) + { + rss_to_vqid_entry.vqm_qid[i] = queue_list[((group_id * 8) + i) % queue_num]; + } + + rc = dpp_apt_dtb_eram_insert(&dev, queue, sdt_no, index + group_id, &rss_to_vqid_entry); + ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_insert"); + + ZXIC_COMM_TRACE_INFO("[%s] slot: %u vport: 0x%04x sdt_no: %u index: 0x%04x.\n", + __FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, index + group_id); + + ZXIC_COMM_TRACE_INFO("[%s] vqm_qid0: 0x%04x vqm_qid1: 0x%04x vqm_qid2: 0x%04x vqm_qid3: 0x%04x.\n", __FUNCTION__, + rss_to_vqid_entry.vqm_qid[0], rss_to_vqid_entry.vqm_qid[1], + rss_to_vqid_entry.vqm_qid[2], rss_to_vqid_entry.vqm_qid[3]); + ZXIC_COMM_TRACE_INFO("[%s] vqm_qid4: 0x%04x vqm_qid5: 0x%04x vqm_qid6: 0x%04x vqm_qid7: 0x%04x.\n", __FUNCTION__, + rss_to_vqid_entry.vqm_qid[4], rss_to_vqid_entry.vqm_qid[5], + rss_to_vqid_entry.vqm_qid[6], rss_to_vqid_entry.vqm_qid[7]); + } + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x success.\n", __FUNCTION__, pf_info->slot, pf_info->vport); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_rxfh_set); + +ZXIC_UINT32 dpp_rxfh_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 *queue_list, ZXIC_UINT32 queue_num) +{ + DPP_DEV_T dev = {0}; + + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 i = 0; + ZXIC_UINT32 queue = 0; + ZXIC_UINT32 group_id = 0; + ZXIC_UINT32 sdt_no = ZXDH_SDT_RSS_TO_VQID_TABLE; + ZXIC_UINT32 index = 0; + ZXIC_UINT32 rc = DPP_OK; + + ZXDH_RSS_TO_VQID_T rss_to_vqid_entry = {0}; + + ZXIC_COMM_CHECK_POINT(pf_info); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x start.\n", __FUNCTION__, pf_info->slot, pf_info->vport); + + ZXIC_COMM_CHECK_POINT(queue_list); + + rc = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get"); + + rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue); + ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get"); + + index = VQM_VFID(pf_info->vport) * RSS_TO_VQID_GROUP_NUM; + for (group_id = 0; group_id < RSS_TO_VQID_GROUP_NUM; group_id++) + { + rc = dpp_apt_dtb_eram_get(&dev, queue, sdt_no, index + group_id, &rss_to_vqid_entry); + ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_get"); + ZXIC_COMM_CHECK_INDEX_NOT_EQUAL(rss_to_vqid_entry.hit_flag, 1); + + for (i = 0; i < 8; i++) + { + queue_list[((group_id * 8) + i) % queue_num] = rss_to_vqid_entry.vqm_qid[i]; + } + } + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x success.\n", __FUNCTION__, pf_info->slot, pf_info->vport); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_rxfh_get); + +ZXIC_UINT32 dpp_rxfh_del(DPP_PF_INFO_T* pf_info) +{ + DPP_DEV_T dev = {0}; + + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 queue = 0; + ZXIC_UINT32 group_id = 0; + ZXIC_UINT32 sdt_no = ZXDH_SDT_RSS_TO_VQID_TABLE; + ZXIC_UINT32 index = 0; + ZXIC_UINT32 rc = DPP_OK; + + ZXIC_COMM_CHECK_POINT(pf_info); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x start.\n", __FUNCTION__, pf_info->slot, pf_info->vport); + + rc = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get"); + + rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue); + ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get"); + + index = VQM_VFID(pf_info->vport) * RSS_TO_VQID_GROUP_NUM; + for (group_id = 0; group_id < RSS_TO_VQID_GROUP_NUM; group_id++) + { + rc = dpp_apt_dtb_eram_clear(&dev, queue, sdt_no, index + group_id); + ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_clear"); + } + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x success.\n", __FUNCTION__, pf_info->slot, pf_info->vport); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_rxfh_del); + +ZXIC_UINT32 dpp_thash_key_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 *hash_key, ZXIC_UINT32 key_num) +{ + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 rc = DPP_OK; + + DPP_DEV_T dev = {0}; + DPP_PPU_PPU_COP_THASH_RSK_T *thash = (DPP_PPU_PPU_COP_THASH_RSK_T*)hash_key; + + ZXIC_COMM_CHECK_POINT(pf_info); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x start.\n", __FUNCTION__, pf_info->slot, pf_info->vport); + + ZXIC_COMM_CHECK_POINT(thash); + ZXIC_COMM_CHECK_INDEX_LOWER(key_num, (ZXIC_UINT32)sizeof(DPP_PPU_PPU_COP_THASH_RSK_T)); + + rc = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get"); + + rc = dpp_ppu_ppu_cop_thash_rsk_set(&dev, thash); + ZXIC_COMM_CHECK_RC(rc, "dpp_ppu_ppu_cop_thash_rsk_set"); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x hash_key:\n", __FUNCTION__, pf_info->slot, pf_info->vport); + dpp_data_print(hash_key, key_num); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x success.\n", __FUNCTION__, pf_info->slot, pf_info->vport); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_thash_key_set); + +ZXIC_UINT32 dpp_thash_key_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 *hash_key, ZXIC_UINT32 key_num) +{ + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 rc = DPP_OK; + + DPP_DEV_T dev = {0}; + DPP_PPU_PPU_COP_THASH_RSK_T *thash = (DPP_PPU_PPU_COP_THASH_RSK_T*)hash_key; + + ZXIC_COMM_CHECK_POINT(pf_info); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x start.\n", __FUNCTION__, pf_info->slot, pf_info->vport); + + ZXIC_COMM_CHECK_POINT(thash); + ZXIC_COMM_CHECK_INDEX_LOWER(key_num, (ZXIC_UINT32)sizeof(DPP_PPU_PPU_COP_THASH_RSK_T)); + + rc = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get"); + + rc = dpp_ppu_ppu_cop_thash_rsk_get(&dev, thash); + ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_ppu_ppu_cop_thash_rsk_get"); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x hash_key:\n", __FUNCTION__, pf_info->slot, pf_info->vport); + dpp_data_print(hash_key, key_num); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x success.\n", __FUNCTION__, pf_info->slot, pf_info->vport); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_thash_key_get); diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_stat.c b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_stat.c new file mode 100644 index 0000000..ec43525 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_stat.c @@ -0,0 +1,386 @@ +#include "dpp_drv_init.h" +#include "dpp_drv_acl.h" +#include "dpp_drv_hash.h" +#include "dpp_drv_eram.h" +#include "dpp_drv_sdt.h" +#include "dpp_dev.h" +#include "dpp_dtb.h" +#include "dpp_hash.h" +#include "dpp_dtb_table.h" +#include "dpp_dtb_table_api.h" +#include "dpp_stat_api.h" +#include "dpp_tbl_api.h" +#include "dpp_tbl_comm.h" +#include "dpp_tbl_stat.h" + +ZXIC_UINT32 dpp_stat_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_cnt) +{ + DPP_DEV_T dev = {0}; + + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 queue = 0; + ZXIC_UINT32 buff[2] = {0}; + ZXIC_UINT32 rc = DPP_OK; + + ZXIC_COMM_CHECK_POINT(pf_info); + + ZXIC_COMM_TRACE_INFO("[%s] slot: %u vport: 0x%04x index: %u mode: %u start.\n", __FUNCTION__, + pf_info->slot, pf_info->vport, index, mode); + + ZXIC_COMM_CHECK_POINT(p_cnt); + ZXIC_COMM_CHECK_INDEX(mode, STAT_RD_CLR_MODE_UNCLR, STAT_RD_CLR_MODE_CLR); + ZXIC_COMM_CHECK_INDEX(index, 0, ZXDH_STAT_PPU_ERAM_DEPTH - 1); + + rc = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get"); + + rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue); + ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get"); + + if (mode == STAT_RD_CLR_MODE_CLR) + { + rc = dpp_stat_ppu_cnt_get(&dev, STAT_64_MODE, index, STAT_RD_CLR_MODE_CLR, buff); + ZXIC_COMM_CHECK_RC(rc, "dpp_stat_ppu_cnt_get"); + } + else + { + rc = dpp_dtb_eram_stat_data_get(&dev, queue, ZXDH_STAT_PPU_ERAM_BAADDR, + ERAM128_TBL_64b, index, buff); + ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_eram_stat_data_get"); + } + + *p_cnt = ((ZXIC_UINT64)buff[0] << 32) | buff[1]; + + ZXIC_COMM_TRACE_INFO("[%s] slot: %u vport: 0x%04x index: %u mode: %u cnt: %llu success.\n", + __FUNCTION__, pf_info->slot, pf_info->vport, index, mode, *p_cnt); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_stat_cnt_get); + +ZXIC_UINT32 dpp_stat_cnt_get_128(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_pkB_cnt, ZXIC_UINT64 *p_pk_cnt) +{ + DPP_DEV_T dev = {0}; + + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 queue = 0; + ZXIC_UINT32 buff[4] = {0}; + ZXIC_UINT32 rc = DPP_OK; + + ZXIC_COMM_CHECK_POINT(pf_info); + + ZXIC_COMM_TRACE_INFO("[%s] slot: %u vport: 0x%04x index: %u mode: %u start.\n", __FUNCTION__, + pf_info->slot, pf_info->vport, index, mode); + + ZXIC_COMM_CHECK_POINT(p_pkB_cnt); + ZXIC_COMM_CHECK_POINT(p_pk_cnt); + ZXIC_COMM_CHECK_INDEX(mode, STAT_RD_CLR_MODE_UNCLR, STAT_RD_CLR_MODE_CLR); + ZXIC_COMM_CHECK_INDEX(index, 0, ((ZXDH_STAT_PPU_ERAM_DEPTH / 2) - 1)); + + rc = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get"); + + rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue); + ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get"); + + if (mode == STAT_RD_CLR_MODE_CLR) + { + rc = dpp_stat_ppu_cnt_get(&dev, STAT_128_MODE, index, STAT_RD_CLR_MODE_CLR, buff); + ZXIC_COMM_CHECK_RC(rc, "dpp_stat_ppu_cnt_get"); + } + else + { + rc = dpp_dtb_eram_stat_data_get(&dev, queue, ZXDH_STAT_PPU_ERAM_BAADDR, + ERAM128_TBL_128b, index, buff); + ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_eram_stat_data_get"); + } + + *p_pk_cnt = ((ZXIC_UINT64)buff[0] << 32) | buff[1]; + *p_pkB_cnt = ((ZXIC_UINT64)buff[2] << 32) | buff[3]; + + ZXIC_COMM_TRACE_INFO("[%s] slot: %u vport: 0x%04x index: %u mode: %u h64_cnt: %llu success.\n", __FUNCTION__, + pf_info->slot, pf_info->vport, index, mode, *p_pk_cnt); + ZXIC_COMM_TRACE_INFO("[%s] slot: %u vport: 0x%04x index: %u mode: %u l64_cnt: %llu success.\n", __FUNCTION__, + pf_info->slot, pf_info->vport, index, mode, *p_pkB_cnt); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_stat_cnt_get_128); + +ZXIC_UINT32 dpp_stat_mc_packet_rx_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_cnt) +{ + ZXIC_UINT32 rc = DPP_OK; + + ZXIC_COMM_CHECK_POINT(p_cnt); + ZXIC_COMM_CHECK_INDEX(index, 0, DPP_STAT_MC_PACKET_RX_CNT_ERAM_DEPTH - 1); + + rc = dpp_stat_cnt_get(pf_info, index + DPP_STAT_MC_PACKET_RX_CNT_ERAM_BAADDR, mode, p_cnt); + ZXIC_COMM_CHECK_RC(rc, "dpp_stat_cnt_get"); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x index: %u cnt: %llu success.\n", __FUNCTION__, + pf_info->slot, pf_info->vport, index, *p_cnt); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_stat_mc_packet_rx_cnt_get); + +ZXIC_UINT32 dpp_stat_bc_packet_rx_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_cnt) +{ + ZXIC_UINT32 rc = DPP_OK; + + ZXIC_COMM_CHECK_POINT(p_cnt); + ZXIC_COMM_CHECK_INDEX(index, 0, DPP_STAT_BC_PACKET_RX_CNT_ERAM_DEPTH - 1); + + rc = dpp_stat_cnt_get(pf_info, index + DPP_STAT_BC_PACKET_RX_CNT_ERAM_BAADDR, mode, p_cnt); + ZXIC_COMM_CHECK_RC(rc, "dpp_stat_cnt_get"); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x index: %u cnt: %llu success.\n", __FUNCTION__, + pf_info->slot, pf_info->vport, index, *p_cnt); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_stat_bc_packet_rx_cnt_get); + +ZXIC_UINT32 dpp_stat_1588_packet_rx_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_cnt) +{ + ZXIC_UINT32 rc = DPP_OK; + + ZXIC_COMM_CHECK_POINT(p_cnt); + ZXIC_COMM_CHECK_INDEX(index, 0, DPP_STAT_1588_PACKET_RX_CNT_ERAM_DEPTH - 1); + + rc = dpp_stat_cnt_get(pf_info, index + DPP_STAT_1588_PACKET_RX_CNT_ERAM_BAADDR, mode, p_cnt); + ZXIC_COMM_CHECK_RC(rc, "dpp_stat_cnt_get"); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x index: %u cnt: %llu success.\n", __FUNCTION__, + pf_info->slot, pf_info->vport, index, *p_cnt); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_stat_1588_packet_rx_cnt_get); + +ZXIC_UINT32 dpp_stat_1588_packet_tx_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_cnt) +{ + ZXIC_UINT32 rc = DPP_OK; + + ZXIC_COMM_CHECK_POINT(p_cnt); + ZXIC_COMM_CHECK_INDEX(index, 0, DPP_STAT_1588_PACKET_TX_CNT_ERAM_DEPTH - 1); + + rc = dpp_stat_cnt_get(pf_info, index + DPP_STAT_1588_PACKET_TX_CNT_ERAM_BAADDR, mode, p_cnt); + ZXIC_COMM_CHECK_RC(rc, "dpp_stat_cnt_get"); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x index: %u cnt: %llu success.\n", __FUNCTION__, + pf_info->slot, pf_info->vport, index, *p_cnt); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_stat_1588_packet_tx_cnt_get); + +ZXIC_UINT32 dpp_stat_1588_packet_drop_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_cnt) +{ + ZXIC_UINT32 rc = DPP_OK; + + ZXIC_COMM_CHECK_POINT(p_cnt); + ZXIC_COMM_CHECK_INDEX(index, 0, DPP_STAT_1588_PACKET_DROP_CNT_ERAM_DEPTH - 1); + + rc = dpp_stat_cnt_get(pf_info, index + DPP_STAT_1588_PACKET_DROP_CNT_ERAM_BAADDR, mode, p_cnt); + ZXIC_COMM_CHECK_RC(rc, "dpp_stat_cnt_get"); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x index: %u cnt: %llu success.\n", __FUNCTION__, + pf_info->slot, pf_info->vport, index, *p_cnt); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_stat_1588_packet_drop_cnt_get); + +ZXIC_UINT32 dpp_stat_1588_enc_packet_rx_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_cnt) +{ + ZXIC_UINT32 rc = DPP_OK; + + ZXIC_COMM_CHECK_POINT(p_cnt); + ZXIC_COMM_CHECK_INDEX(index, 0, DPP_STAT_1588_ENC_PACKET_RX_CNT_ERAM_DEPTH - 1); + + rc = dpp_stat_cnt_get(pf_info, index + DPP_STAT_1588_ENC_PACKET_RX_CNT_ERAM_BAADDR, mode, p_cnt); + ZXIC_COMM_CHECK_RC(rc, "dpp_stat_cnt_get"); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x index: %u cnt: %llu success.\n", __FUNCTION__, + pf_info->slot, pf_info->vport, index, *p_cnt); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_stat_1588_enc_packet_rx_cnt_get); + +ZXIC_UINT32 dpp_stat_1588_enc_packet_tx_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_cnt) +{ + ZXIC_UINT32 rc = DPP_OK; + + ZXIC_COMM_CHECK_POINT(p_cnt); + ZXIC_COMM_CHECK_INDEX(index, 0, DPP_STAT_1588_ENC_PACKET_TX_CNT_ERAM_DEPTH - 1); + + rc = dpp_stat_cnt_get(pf_info, index + DPP_STAT_1588_ENC_PACKET_TX_CNT_ERAM_BAADDR, mode, p_cnt); + ZXIC_COMM_CHECK_RC(rc, "dpp_stat_cnt_get"); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x index: %u cnt: %llu success.\n", __FUNCTION__, + pf_info->slot, pf_info->vport, index, *p_cnt); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_stat_1588_enc_packet_tx_cnt_get); + +ZXIC_UINT32 dpp_stat_spoof_packet_drop_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_cnt) +{ + ZXIC_UINT32 rc = DPP_OK; + + ZXIC_COMM_CHECK_POINT(p_cnt); + ZXIC_COMM_CHECK_INDEX(index, 0, DPP_STAT_SPOOF_PACKET_DROP_CNT_ERAM_DEPTH - 1); + + rc = dpp_stat_cnt_get(pf_info, index + DPP_STAT_SPOOF_PACKET_DROP_CNT_ERAM_BAADDR, mode, p_cnt); + ZXIC_COMM_CHECK_RC(rc, "dpp_stat_cnt_get"); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_stat_spoof_packet_drop_cnt_get); + +ZXIC_UINT32 dpp_stat_mcode_packet_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_cnt) +{ + ZXIC_UINT32 rc = DPP_OK; + + ZXIC_COMM_CHECK_POINT(p_cnt); + ZXIC_COMM_CHECK_INDEX(index, 0, DPP_STAT_MCODE_PACKET_CNT_ERAM_DEPTH - 1); + + rc = dpp_stat_cnt_get(pf_info, index + DPP_STAT_MCODE_PACKET_CNT_ERAM_BAADDR, mode, p_cnt); + ZXIC_COMM_CHECK_RC(rc, "dpp_stat_cnt_get"); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x index: %u cnt: %llu success.\n", __FUNCTION__, + pf_info->slot, pf_info->vport, index, *p_cnt); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_stat_mcode_packet_cnt_get); + +ZXIC_UINT32 dpp_stat_port_bc_packet_tx_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_cnt) +{ + ZXIC_UINT32 rc = DPP_OK; + + ZXIC_COMM_CHECK_POINT(p_cnt); + ZXIC_COMM_CHECK_INDEX(index, 0, DPP_STAT_PORT_BC_PACKET_TX_CNT_ERAM_DEPTH - 1); + + rc = dpp_stat_cnt_get(pf_info, index + DPP_STAT_PORT_BC_PACKET_TX_CNT_ERAM_BAADDR, mode, p_cnt); + ZXIC_COMM_CHECK_RC(rc, "dpp_stat_cnt_get"); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_stat_port_bc_packet_tx_cnt_get); + +ZXIC_UINT32 dpp_stat_port_bc_packet_rx_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_cnt) +{ + ZXIC_UINT32 rc = DPP_OK; + + ZXIC_COMM_CHECK_POINT(p_cnt); + ZXIC_COMM_CHECK_INDEX(index, 0, DPP_STAT_PORT_BC_PACKET_RX_CNT_ERAM_DEPTH - 1); + + rc = dpp_stat_cnt_get(pf_info, index + DPP_STAT_PORT_BC_PACKET_RX_CNT_ERAM_BAADDR, mode, p_cnt); + ZXIC_COMM_CHECK_RC(rc, "dpp_stat_cnt_get"); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_stat_port_bc_packet_rx_cnt_get); + +ZXIC_UINT32 dpp_stat_port_RDMA_packet_msg_tx_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_pkB_cnt, ZXIC_UINT64 *p_pk_cnt) +{ + ZXIC_UINT32 rc = DPP_OK; + + ZXIC_COMM_CHECK_POINT(p_pkB_cnt); + ZXIC_COMM_CHECK_POINT(p_pk_cnt); + ZXIC_COMM_CHECK_INDEX(index, 0, DPP_STAT_PORT_RDMA_PACKET_TX_CNT_ERAM_DEPTH - 1); + + rc = dpp_stat_cnt_get_128(pf_info, index + DPP_STAT_PORT_RDMA_PACKET_TX_CNT_ERAM_BAADDR, mode, p_pkB_cnt, p_pk_cnt); + ZXIC_COMM_CHECK_RC(rc, "dpp_stat_cnt_get_128"); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x index: %u h64_cnt: %llu success.\n", __FUNCTION__, + pf_info->slot, pf_info->vport, index, *p_pk_cnt); + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x index: %u l64_cnt: %llu success.\n", __FUNCTION__, + pf_info->slot, pf_info->vport, index, *p_pkB_cnt); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_stat_port_RDMA_packet_msg_tx_cnt_get); + +ZXIC_UINT32 dpp_stat_port_RDMA_packet_msg_rx_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_pkB_cnt, ZXIC_UINT64 *p_pk_cnt) +{ + ZXIC_UINT32 rc = DPP_OK; + + ZXIC_COMM_CHECK_POINT(p_pkB_cnt); + ZXIC_COMM_CHECK_POINT(p_pk_cnt); + ZXIC_COMM_CHECK_INDEX(index, 0, DPP_STAT_PORT_RDMA_PACKET_RX_CNT_ERAM_DEPTH - 1); + + rc = dpp_stat_cnt_get_128(pf_info, index + DPP_STAT_PORT_RDMA_PACKET_RX_CNT_ERAM_BAADDR, mode, p_pkB_cnt, p_pk_cnt); + ZXIC_COMM_CHECK_RC(rc, "dpp_stat_cnt_get_128"); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x index: %u h64_cnt: %llu success.\n", __FUNCTION__, + pf_info->slot, pf_info->vport, index, *p_pk_cnt); + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x index: %u l64_cnt: %llu success.\n", __FUNCTION__, + pf_info->slot, pf_info->vport, index, *p_pkB_cnt); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_stat_port_RDMA_packet_msg_rx_cnt_get); + +ZXIC_UINT32 dpp_stat_plcr_packet_drop_tx_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_pkB_cnt, ZXIC_UINT64 *p_pk_cnt) +{ + ZXIC_UINT32 rc = DPP_OK; + + ZXIC_COMM_CHECK_POINT(p_pkB_cnt); + ZXIC_COMM_CHECK_POINT(p_pk_cnt); + ZXIC_COMM_CHECK_INDEX(index, 0, DPP_STAT_PLCR_PACKET_DROP_TX_CNT_ERAM_DEPTH - 1); + + rc = dpp_stat_cnt_get_128(pf_info, index + DPP_STAT_PLCR_PACKET_DROP_TX_CNT_ERAM_BAADDR, mode, p_pkB_cnt, p_pk_cnt); + ZXIC_COMM_CHECK_RC(rc, "dpp_stat_cnt_get_128"); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_stat_plcr_packet_drop_tx_cnt_get); + +ZXIC_UINT32 dpp_stat_plcr_packet_drop_rx_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_pkB_cnt, ZXIC_UINT64 *p_pk_cnt) +{ + ZXIC_UINT32 rc = DPP_OK; + + ZXIC_COMM_CHECK_POINT(p_pkB_cnt); + ZXIC_COMM_CHECK_POINT(p_pk_cnt); + ZXIC_COMM_CHECK_INDEX(index, 0, DPP_STAT_PLCR_PACKET_DROP_RX_CNT_ERAM_DEPTH - 1); + + rc = dpp_stat_cnt_get_128(pf_info, index + DPP_STAT_PLCR_PACKET_DROP_RX_CNT_ERAM_BAADDR, mode, p_pkB_cnt, p_pk_cnt); + ZXIC_COMM_CHECK_RC(rc, "dpp_stat_cnt_get_128"); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_stat_plcr_packet_drop_rx_cnt_get); + +ZXIC_UINT32 dpp_stat_MTU_packet_msg_tx_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_pkB_cnt, ZXIC_UINT64 *p_pk_cnt) +{ + ZXIC_UINT32 rc = DPP_OK; + + ZXIC_COMM_CHECK_POINT(p_pkB_cnt); + ZXIC_COMM_CHECK_POINT(p_pk_cnt); + ZXIC_COMM_CHECK_INDEX(index, 0, DPP_STAT_MTU_PACKET_DROP_TX_CNT_ERAM_DEPTH - 1); + + rc = dpp_stat_cnt_get_128(pf_info, index + DPP_STAT_MTU_PACKET_DROP_TX_CNT_ERAM_BAADDR, mode, p_pkB_cnt, p_pk_cnt); + ZXIC_COMM_CHECK_RC(rc, "dpp_stat_cnt_get_128"); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_stat_MTU_packet_msg_tx_cnt_get); + +ZXIC_UINT32 dpp_stat_MTU_packet_msg_rx_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_pkB_cnt, ZXIC_UINT64 *p_pk_cnt) +{ + ZXIC_UINT32 rc = DPP_OK; + + ZXIC_COMM_CHECK_POINT(p_pkB_cnt); + ZXIC_COMM_CHECK_POINT(p_pk_cnt); + ZXIC_COMM_CHECK_INDEX(index, 0, DPP_STAT_MTU_PACKET_DROP_RX_CNT_ERAM_DEPTH - 1); + + rc = dpp_stat_cnt_get_128(pf_info, index + DPP_STAT_MTU_PACKET_DROP_RX_CNT_ERAM_BAADDR, mode, p_pkB_cnt, p_pk_cnt); + ZXIC_COMM_CHECK_RC(rc, "dpp_stat_cnt_get_128"); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_stat_MTU_packet_msg_rx_cnt_get); \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_tm.c b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_tm.c new file mode 100644 index 0000000..735d7ff --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_tm.c @@ -0,0 +1,175 @@ +#include "dpp_tbl_tm.h" +#include "dpp_dev.h" +#include "dpp_drv_sdt.h" +#include "dpp_drv_eram.h" +#include "dpp_drv_qos.h" +#include "dpp_dtb.h" +#include "dpp_apt_se_api.h" +#include "dpp_tbl_api.h" + +ZXIC_UINT32 dpp_tm_flowid_pport_table_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 port, ZXIC_UINT32 flow_id) +{ + ZXIC_UINT32 rc = DPP_OK; + ZXIC_UINT32 attr = PANEL_FLAG_TM_BASE_QUEUE; + + rc = dpp_panel_attr_set(pf_info, port, attr, flow_id); + ZXIC_COMM_CHECK_RC(rc, "dpp_panel_attr_set"); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_tm_flowid_pport_table_set); + +ZXIC_UINT32 dpp_tm_flowid_pport_table_del(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 port) +{ + ZXIC_UINT32 rc = DPP_OK; + + rc = dpp_tm_flowid_pport_table_set(pf_info, port, TM_BASE_QUEUE_VALID); + ZXIC_COMM_CHECK_RC(rc, "dpp_tm_flowid_pport_table_set"); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_tm_flowid_pport_table_del); + +ZXIC_UINT32 dpp_tm_pport_trust_mode_table_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 port, ZXIC_UINT32 mode) +{ + ZXIC_UINT32 rc = DPP_OK; + ZXIC_UINT32 attr = PANEL_FLAG_TRUST_MODE; + + rc = dpp_panel_attr_set(pf_info, port, attr, mode); + ZXIC_COMM_CHECK_RC(rc, "dpp_panel_attr_set"); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_tm_pport_trust_mode_table_set); + +ZXIC_UINT32 dpp_tm_pport_trust_mode_table_del(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 port) +{ + ZXIC_UINT32 rc = DPP_OK; + + rc = dpp_tm_pport_trust_mode_table_set(pf_info, port, TRUST_MODE_VALID); + ZXIC_COMM_CHECK_RC(rc, "dpp_tm_pport_trust_mode_table_set"); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_tm_pport_trust_mode_table_del); + +ZXIC_UINT32 dpp_tm_pport_dscp_map_table_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 port, ZXIC_UINT32 dscp_id, ZXIC_UINT32 up_id) +{ + DPP_DEV_T dev = {0}; + + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 queue = 0; + ZXIC_UINT32 sdt_no = ZXDH_SDT_DSCP_TO_UP_TABLE; + ZXIC_UINT32 index = 0x3ff & ((port << 6) | (dscp_id & 0x3f)); + ZXIC_UINT32 rc = DPP_OK; + + ZXDH_DSCP_TO_UP_T dscp_to_up = {0}; + + ZXIC_COMM_CHECK_POINT(pf_info); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u index: %u start.\n", + __FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, index); + + rc = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get"); + + rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue); + ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get"); + + // dpp_apt_dtb_eram_get(&dev, queue, sdt_no, index, &dscp_to_up); + + dscp_to_up.hit_flag = 1; + dscp_to_up.up = up_id; + + rc = dpp_apt_dtb_eram_insert(&dev, queue, sdt_no, index, &dscp_to_up); + ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_insert"); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u index: %u success.\n", + __FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, index); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_tm_pport_dscp_map_table_set); + +ZXIC_UINT32 dpp_tm_pport_dscp_map_table_del(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 port, ZXIC_UINT32 dscp_id) +{ + ZXIC_UINT32 rc = DPP_OK; + + rc = dpp_tm_pport_dscp_map_table_set(pf_info, port, dscp_id, UP_VALID); + ZXIC_COMM_CHECK_RC(rc, "dpp_tm_pport_dscp_map_table_set"); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_tm_pport_dscp_map_table_del); + +ZXIC_UINT32 dpp_tm_pport_up_map_table_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 port, ZXIC_UINT32 up_id, ZXIC_UINT32 tc_id) +{ + DPP_DEV_T dev = {0}; + + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 queue = 0; + ZXIC_UINT32 sdt_no = ZXDH_SDT_UP_TO_TC_TABLE; + ZXIC_UINT32 index = 0x7F & ((port << 3) | (up_id & 0x7)); + ZXIC_UINT32 rc = DPP_OK; + + ZXDH_UP_TO_TC_T up_to_tc = {0}; + + ZXIC_COMM_CHECK_POINT(pf_info); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u index: %u start.\n", + __FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, index); + + rc = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get"); + + rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue); + ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get"); + + // dpp_apt_dtb_eram_get(&dev, queue, sdt_no, index, &up_to_tc); + + up_to_tc.hit_flag = 1; + up_to_tc.tc = tc_id; + + rc = dpp_apt_dtb_eram_insert(&dev, queue, sdt_no, index, &up_to_tc); + ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_insert"); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u index: %u success.\n", + __FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, index); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_tm_pport_up_map_table_set); + +ZXIC_UINT32 dpp_tm_pport_up_map_table_del(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 port, ZXIC_UINT32 up_id) +{ + ZXIC_UINT32 rc = DPP_OK; + + rc = dpp_tm_pport_up_map_table_set(pf_info, port, up_id, TC_VALID); + ZXIC_COMM_CHECK_RC(rc, "dpp_tm_pport_dscp_map_table_set"); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_tm_pport_up_map_table_del); + +ZXIC_UINT32 dpp_tm_pport_mcode_switch_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 port, ZXIC_UINT32 mode) +{ + ZXIC_UINT32 rc = DPP_OK; + ZXIC_UINT32 attr = PANEL_FLAG_TM_SHAPE_ENABLE; + + rc = dpp_panel_attr_set(pf_info, port, attr, mode); + ZXIC_COMM_CHECK_RC(rc, "dpp_panel_attr_set"); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_tm_pport_mcode_switch_set); + +ZXIC_UINT32 dpp_tm_pport_mcode_switch_del(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 port) +{ + ZXIC_UINT32 rc = DPP_OK; + + rc = dpp_tm_pport_mcode_switch_set(pf_info, port, TM_SWITCH_OFF); + ZXIC_COMM_CHECK_RC(rc, "dpp_tm_pport_mcode_switch_set"); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_tm_pport_mcode_switch_del); diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_vhca.c b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_vhca.c new file mode 100644 index 0000000..ee81c05 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_vhca.c @@ -0,0 +1,81 @@ +#include "dpp_drv_init.h" +#include "dpp_drv_acl.h" +#include "dpp_drv_hash.h" +#include "dpp_drv_eram.h" +#include "dpp_drv_sdt.h" +#include "dpp_dev.h" +#include "dpp_dtb.h" +#include "dpp_hash.h" +#include "dpp_dtb_table.h" +#include "dpp_dtb_table_api.h" +#include "dpp_tbl_api.h" +#include "dpp_tbl_comm.h" +#include "dpp_tbl_port.h" + +// ZXIC_UINT32 dpp_vport_vhca_id_add(ZXIC_UINT16 vport, ZXIC_UINT32 vhca_id, ZXIC_UINT32 vqm_vfid) +ZXIC_UINT32 dpp_vport_vhca_id_add(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 vhca_id) +{ + ZXIC_UINT32 rc = DPP_OK; + DPP_DEV_T dev = {0}; + + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 queue = 0; + ZXIC_UINT32 sdt_no = ZXDH_SDT_VHCA_TABLE; + + ZXDH_VHCA_T vhca_entry = {0}; + + ZXIC_COMM_CHECK_POINT(pf_info); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u vhca_id: %u start.\n", __FUNCTION__, + pf_info->slot, pf_info->vport, sdt_no, vhca_id); + + ZXIC_COMM_MEMSET(&vhca_entry, 0, sizeof(ZXDH_VHCA_T)); + + rc = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get"); + + rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue); + ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get"); + + vhca_entry.valid = 1; + vhca_entry.vqm_vfid = VQM_VFID(pf_info->vport); + + rc = dpp_apt_dtb_eram_insert(&dev, queue, sdt_no, vhca_id, &vhca_entry); + ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_insert"); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u vhca_id: %u success.\n", __FUNCTION__, + pf_info->slot, pf_info->vport, sdt_no, vhca_id); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_vport_vhca_id_add); + +ZXIC_UINT32 dpp_vport_vhca_id_del(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 vhca_id) +{ + DPP_DEV_T dev = {0}; + + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 queue = 0; + ZXIC_UINT32 sdt_no = ZXDH_SDT_VHCA_TABLE; + ZXIC_UINT32 rc = DPP_OK; + + ZXIC_COMM_CHECK_POINT(pf_info); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u vhca_id: %u start.\n", __FUNCTION__, + pf_info->slot, pf_info->vport, sdt_no, vhca_id); + + rc = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get"); + + rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue); + ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get"); + + rc = dpp_apt_dtb_eram_clear(&dev, queue, sdt_no, vhca_id); + ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_clear"); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u vhca_id: %u success.\n", __FUNCTION__, + pf_info->slot, pf_info->vport, sdt_no, vhca_id); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_vport_vhca_id_del); \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_vlan.c b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_vlan.c new file mode 100644 index 0000000..6266bbf --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_vlan.c @@ -0,0 +1,152 @@ +#include "dpp_drv_init.h" +#include "dpp_drv_acl.h" +#include "dpp_drv_hash.h" +#include "dpp_drv_eram.h" +#include "dpp_drv_sdt.h" +#include "dpp_dev.h" +#include "dpp_dtb.h" +#include "dpp_hash.h" +#include "dpp_dtb_table.h" +#include "dpp_dtb_table_api.h" +#include "dpp_tbl_comm.h" +#include "dpp_tbl_vlan.h" + +ZXIC_UINT32 dpp_vlan_filter_init(DPP_PF_INFO_T* pf_info) +{ + DPP_DEV_T dev = {0}; + + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 queue = 0; + ZXIC_UINT32 sdt_no = ZXDH_SDT_VLAN_FILTER_TABLE; + ZXIC_UINT32 vlan_group_id = 0; + ZXIC_UINT32 index = 0; + ZXIC_UINT32 rc = DPP_OK; + + ZXDH_VLAN_FILTER_T vlan_filter_entry = {0}; + + ZXIC_COMM_CHECK_POINT(pf_info); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x start.\n", __FUNCTION__, + pf_info->slot, pf_info->vport); + + ZXIC_COMM_MEMSET(&vlan_filter_entry, 0, sizeof(ZXDH_VLAN_FILTER_T)); + + rc = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get"); + + rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue); + ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get"); + + vlan_filter_entry.hit_flag = 1; + + for (vlan_group_id = 0; vlan_group_id < VLAN_GROUP_NUM; vlan_group_id++) + { + index = ((vlan_group_id << 11) | (VQM_VFID(pf_info->vport))); + rc = dpp_apt_dtb_eram_insert(&dev, queue, sdt_no, index, &vlan_filter_entry); + ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_insert"); + } + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x success.\n", __FUNCTION__, + pf_info->slot, pf_info->vport); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_vlan_filter_init); + +ZXIC_UINT32 dpp_add_vlan_filter(DPP_PF_INFO_T* pf_info, ZXIC_UINT16 vlan_id) +{ + DPP_DEV_T dev = {0}; + + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 queue = 0; + ZXIC_UINT32 sdt_no = ZXDH_SDT_VLAN_FILTER_TABLE; + + ZXIC_UINT32 vlan_group_id = vlan_id / VLAN_ID_NUM_IN_GROUP; + ZXIC_UINT32 vlan_remainder = vlan_id % VLAN_ID_NUM_IN_GROUP; + + ZXIC_UINT32 index = 0; + ZXIC_UINT32 rc = DPP_OK; + + ZXDH_VLAN_FILTER_T vlan_filter_entry = {0}; + + ZXIC_COMM_CHECK_POINT(pf_info); + + index = ((vlan_group_id << 11) | (VQM_VFID(pf_info->vport))); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u index: 0x%04x group_id: %u vlan_id: %u start.\n", + __FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, index, vlan_group_id, vlan_id); + + ZXIC_COMM_MEMSET(&vlan_filter_entry, 0, sizeof(ZXDH_VLAN_FILTER_T)); + + ZXIC_COMM_CHECK_INDEX(vlan_id, 0, 4095); + + rc = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get"); + + rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue); + ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get"); + + rc = dpp_apt_dtb_eram_get(&dev, queue, sdt_no, index, &vlan_filter_entry); + ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_get"); + + vlan_filter_entry.hit_flag = 1; + vlan_filter_entry.vport_bitmap[vlan_remainder / 8] |= 1 << (7 - (vlan_remainder % 8)); + + rc = dpp_apt_dtb_eram_insert(&dev, queue, sdt_no, index, &vlan_filter_entry); + ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_insert"); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u index: 0x%04x group_id: %u vlan_id: %u success.\n", + __FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, index, vlan_group_id, vlan_id); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_add_vlan_filter); + +ZXIC_UINT32 dpp_del_vlan_filter(DPP_PF_INFO_T* pf_info, ZXIC_UINT16 vlan_id) +{ + DPP_DEV_T dev = {0}; + + ZXIC_UINT32 dev_id = 0; + ZXIC_UINT32 queue = 0; + ZXIC_UINT32 sdt_no = ZXDH_SDT_VLAN_FILTER_TABLE; + + ZXIC_UINT32 vlan_group_id = vlan_id / VLAN_ID_NUM_IN_GROUP; + ZXIC_UINT32 vlan_remainder = vlan_id % VLAN_ID_NUM_IN_GROUP; + + ZXIC_UINT32 index = 0; + ZXIC_UINT32 rc = DPP_OK; + + ZXDH_VLAN_FILTER_T vlan_filter_entry = {0}; + + ZXIC_COMM_CHECK_POINT(pf_info); + + index = ((vlan_group_id << 11) | (VQM_VFID(pf_info->vport))); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u index: 0x%04x group_id: %u vlan_id: %u start.\n", + __FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, index, vlan_group_id, vlan_id); + + ZXIC_COMM_MEMSET(&vlan_filter_entry, 0, sizeof(ZXDH_VLAN_FILTER_T)); + + ZXIC_COMM_CHECK_INDEX(vlan_id, 0, 4095); + + rc = dpp_dev_get(dev_id, pf_info, &dev); + ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get"); + + rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue); + ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get"); + + rc = dpp_apt_dtb_eram_get(&dev, queue, sdt_no, index, &vlan_filter_entry); + ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_get"); + + vlan_filter_entry.hit_flag = 1; + vlan_filter_entry.vport_bitmap[vlan_remainder / 8] &= ~(1 << (7 - (vlan_remainder % 8))); + + rc = dpp_apt_dtb_eram_insert(&dev, queue, sdt_no, index, &vlan_filter_entry); + ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_insert"); + + ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u index: 0x%04x group_id: %u vlan_id: %u success.\n", + __FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, index, vlan_group_id, vlan_id); + + return DPP_OK; +} +EXPORT_SYMBOL(dpp_del_vlan_filter); diff --git a/src/net/drivers/net/ethernet/dinghai/en_pf.c b/src/net/drivers/net/ethernet/dinghai/en_pf.c new file mode 100755 index 0000000..9b71b3d --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_pf.c @@ -0,0 +1,2275 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "en_pf.h" +#include "./en_pf/irq.h" +#include "./en_pf/eq.h" +#include "./en_pf/events.h" +#include "en_aux.h" +#include "en_sf.h" +#include "en_np/init/include/dpp_np_init.h" +#include "en_pf/msg_func.h" +#include "msg_common.h" + +#ifdef CONFIG_ZXDH_SF +#include +#endif + +#ifdef DRIVER_VERSION_VAL + #define DRV_VERSION DRIVER_VERSION_VAL +#else + #define DRV_VERSION "1.0-1" +#endif + +#define DRV_SUMMARY "ZTE(R) zxdh-net driver" + +const char zxdh_pf_driver_version[] = DRV_VERSION; +static const char zxdh_pf_driver_string[] = DRV_SUMMARY; +static const char zxdh_pf_copyright[] = "Copyright (c) 2022-23, ZTE Corporation."; + +MODULE_AUTHOR("ZTE Corporation"); +MODULE_DESCRIPTION(DRV_SUMMARY); +MODULE_VERSION(DRV_VERSION); +MODULE_LICENSE("Dual BSD/GPL"); + +uint32_t dh_debug_mask; +module_param_named(debug_mask, dh_debug_mask, uint, 0644); +MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0"); + +static const struct pci_device_id dh_pf_pci_table[] = { + { PCI_DEVICE(ZXDH_PF_VENDOR_ID, ZXDH_PF_DEVICE_ID), 0 }, + { PCI_DEVICE(ZXDH_PF_VENDOR_ID, ZXDH_VF_DEVICE_ID), 0 }, + { PCI_DEVICE(ZXDH_PF_BSI_VENDOR_ID, ZXDH_PF_DEVICE_ID), 0 }, + { PCI_DEVICE(ZXDH_PF_BSI_VENDOR_ID, ZXDH_VF_DEVICE_ID), 0 }, + { PCI_DEVICE(ZXDH_PF_VENDOR_ID, ZXDH_INICA_BOND_DEVICE_ID), 0 }, /* bond */ + { PCI_DEVICE(ZXDH_PF_VENDOR_ID, ZXDH_INICB_BOND_DEVICE_ID), 0 }, /* bond */ + { PCI_DEVICE(ZXDH_PF_VENDOR_ID, ZXDH_DPUA_BOND_DEVICE_ID), 0 }, /* bond */ + { PCI_DEVICE(ZXDH_PF_VENDOR_ID, ZXDH_INICA_UPF_BOND_DEVICE_ID), 0 }, /* bond */ + { PCI_DEVICE(ZXDH_PF_VENDOR_ID, ZXDH_PF_E310_DEVICE_ID), 0 }, + { PCI_DEVICE(ZXDH_PF_VENDOR_ID, ZXDH_VF_E310_DEVICE_ID), 0 }, + { PCI_DEVICE(ZXDH_PF_VENDOR_ID, ZXDH_PF_E312_DEVICE_ID), 0 }, + { PCI_DEVICE(ZXDH_PF_VENDOR_ID, ZXDH_VF_E312_DEVICE_ID), 0 }, + { PCI_DEVICE(ZXDH_PF_VENDOR_ID, ZXDH_PF_DPUB_NOF_DEVICE_ID), 0 }, + { PCI_DEVICE(ZXDH_PF_VENDOR_ID, ZXDH_PF_DPUB_PF_DEVICE_ID), 0 }, + { PCI_DEVICE(ZXDH_PF_VENDOR_ID, ZXDH_PF_DPUB_INITIATOR1_DEVICE_ID), 0 }, + { PCI_DEVICE(ZXDH_PF_VENDOR_ID, ZXDH_PF_DPUB_INITIATOR2_DEVICE_ID), 0 }, + { PCI_DEVICE(ZXDH_PF_VENDOR_ID, ZXDH_PF_DPUB_RDMA_DEVICE_ID), 0 }, + { PCI_DEVICE(ZXDH_PF_VENDOR_ID, ZXDH_VF_DPUB_RDMA_DEVICE_ID), 0 }, + { PCI_DEVICE(ZXDH_PF_VENDOR_ID, ZXDH_UPF_PF_I512_DEVICE_ID), 0 }, + { PCI_DEVICE(ZXDH_PF_VENDOR_ID, ZXDH_UPF_VF_I512_DEVICE_ID), 0 }, + { PCI_DEVICE(ZXDH_PF_VENDOR_ID, ZXDH_INICA_RDMA_PF_DEVICE_ID), 0 }, + { PCI_DEVICE(ZXDH_PF_VENDOR_ID, ZXDH_INICA_RDMA_VF_DEVICE_ID), 0 }, + { 0, } +}; + +MODULE_DEVICE_TABLE(pci, dh_pf_pci_table); + +extern struct devlink_ops dh_pf_devlink_ops; +extern struct dh_core_devlink_ops dh_pf_core_devlink_ops; + +#ifdef PTP_DRIVER_INTERFACE_EN +int zxdh_ptp_init(struct dh_core_dev *zxdev); +void zxdh_ptp_stop(struct dh_core_dev *zxdev); +#endif + +int32_t dh_pf_pci_init(struct dh_core_dev *dev) +{ + int32_t ret = 0; + struct zxdh_pf_device *pf_dev = NULL; + + pci_set_drvdata(dev->pdev, dev); + + ret = pci_enable_device(dev->pdev); + if (ret != 0) + { + LOG_ERR("pci_enable_device failed: %d\n", ret); + return -ENOMEM; + } + + ret = dma_set_mask_and_coherent(dev->device, DMA_BIT_MASK(64)); + if (ret != 0) + { + ret = dma_set_mask_and_coherent(dev->device, DMA_BIT_MASK(32)); + if (ret != 0) + { + LOG_ERR("dma_set_mask_and_coherent failed: %d\n", ret); + goto err_pci; + } + } + + ret = pci_request_selected_regions(dev->pdev, pci_select_bars(dev->pdev, IORESOURCE_MEM), "dh-pf"); + if (ret != 0) + { + LOG_ERR("pci_request_selected_regions failed: %d\n", ret); + goto err_pci; + } + + pci_enable_pcie_error_reporting(dev->pdev); + pci_set_master(dev->pdev); + ret = pci_save_state(dev->pdev); + if (ret != 0) + { + LOG_ERR("pci_save_state failed: %d\n", ret); + goto err_pci_save_state; + } + + pf_dev = dh_core_priv(dev); + pf_dev->pci_ioremap_addr[0] = (uint64_t)ioremap(pci_resource_start(dev->pdev, 0), pci_resource_len(dev->pdev, 0)); + if (pf_dev->pci_ioremap_addr[0] == 0) + { + ret = -1; + LOG_ERR("ioremap(0x%llx, 0x%llx) failed\n", pci_resource_start(dev->pdev, 0), pci_resource_len(dev->pdev, 0)); + goto err_pci_save_state; + } + + return 0; + +err_pci_save_state: + pci_disable_pcie_error_reporting(dev->pdev); + pci_release_selected_regions(dev->pdev, pci_select_bars(dev->pdev, IORESOURCE_MEM)); +err_pci: + pci_disable_device(dev->pdev); + return ret; +} + +void dh_pf_pci_close(struct dh_core_dev *dev) +{ + struct zxdh_pf_device *pf_dev = NULL; + + pf_dev = dh_core_priv(dev); + iounmap((void *)pf_dev->pci_ioremap_addr[0]); + pci_disable_pcie_error_reporting(dev->pdev); + pci_release_selected_regions(dev->pdev, pci_select_bars(dev->pdev, IORESOURCE_MEM)); + pci_disable_device(dev->pdev); + + return; +} + +int32_t zxdh_pf_pci_find_capability(struct pci_dev *pdev, uint8_t cfg_type, uint32_t ioresource_types, int32_t *bars) +{ + int32_t pos = 0; + uint8_t type = 0; + uint8_t bar = 0; + + for (pos = pci_find_capability(pdev, PCI_CAP_ID_VNDR); pos > 0; pos = pci_find_next_capability(pdev, pos, PCI_CAP_ID_VNDR)) + { + pci_read_config_byte(pdev, pos + offsetof(struct zxdh_pf_pci_cap, cfg_type), &type); + pci_read_config_byte(pdev, pos + offsetof(struct zxdh_pf_pci_cap, bar), &bar); + + /* ignore structures with reserved BAR values */ + if (bar > ZXDH_PF_MAX_BAR_VAL) + { + continue; + } + + if (type == cfg_type) + { + if (pci_resource_len(pdev, bar) && pci_resource_flags(pdev, bar) & ioresource_types) + { + *bars |= (1 << bar); + return pos; + } + } + } + + return 0; +} + +void __iomem *zxdh_pf_map_capability(struct dh_core_dev *dh_dev, int32_t off, + size_t minlen, uint32_t align, uint32_t start, + uint32_t size, size_t *len, resource_size_t *pa) +{ + struct pci_dev *pdev = dh_dev->pdev; + uint8_t bar = 0; + uint32_t offset = 0; + uint32_t length = 0; + void __iomem *p = NULL; + + pci_read_config_byte(pdev, off + offsetof(struct zxdh_pf_pci_cap, bar), &bar); + pci_read_config_dword(pdev, off + offsetof(struct zxdh_pf_pci_cap, offset), &offset); + pci_read_config_dword(pdev, off + offsetof(struct zxdh_pf_pci_cap, length), &length); + + if (length <= start) + { + LOG_ERR("bad capability len %u (>%u expected)\n", length, start); + return NULL; + } + + if (length - start < minlen) + { + LOG_ERR("bad capability len %u (>=%zu expected)\n", length, minlen); + return NULL; + } + + length -= start; + if (start + offset < offset) + { + LOG_ERR("map wrap-around %u+%u\n", start, offset); + return NULL; + } + + offset += start; + if (offset & (align - 1)) + { + LOG_ERR("offset %u not aligned to %u\n", offset, align); + return NULL; + } + + if (length > size) + { + length = size; + } + + if (len) + { + *len = length; + } + + if (minlen + offset < minlen || minlen + offset > pci_resource_len(pdev, bar)) + { + LOG_ERR("map custom queue %zu@%u " "out of range on bar %i length %lu\n", + minlen, offset, bar, (unsigned long)pci_resource_len(pdev, bar)); + return NULL; + } + + p = pci_iomap_range(pdev, bar, offset, length); + if (unlikely(p == NULL)) + { + LOG_ERR("unable to map custom queue %u@%u on bar %i\n", length, offset, bar); + } + else if (pa) + { + *pa = pci_resource_start(pdev, bar) + offset; + } + + return p; +} + +int32_t zxdh_pf_common_cfg_init(struct dh_core_dev *dh_dev) +{ + int32_t common = 0; + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + struct pci_dev *pdev = dh_dev->pdev; + + /* check for a common config: if not, use legacy mode (bar 0). */ + common = zxdh_pf_pci_find_capability(pdev, ZXDH_PCI_CAP_COMMON_CFG, IORESOURCE_IO | IORESOURCE_MEM, &pf_dev->modern_bars); + if (common == 0) + { + LOG_ERR("missing capabilities %i, leaving for legacy driver\n", common); + return -ENODEV; + } + + pf_dev->common = zxdh_pf_map_capability(dh_dev, common, + sizeof(struct zxdh_pf_pci_common_cfg), ZXDH_PF_ALIGN4, 0, + sizeof(struct zxdh_pf_pci_common_cfg), NULL, NULL); + if (unlikely(pf_dev->common == NULL)) + { + LOG_ERR("pf_dev->common is null\n"); + return -EINVAL; + } + + return 0; +} + +int32_t zxdh_pf_notify_cfg_init(struct dh_core_dev *dh_dev) +{ + int32_t notify = 0; + uint32_t notify_length = 0; + uint32_t notify_offset = 0; + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + struct pci_dev *pdev = dh_dev->pdev; + + /* If common is there, these should be too... */ + notify = zxdh_pf_pci_find_capability(pdev, ZXDH_PCI_CAP_NOTIFY_CFG, IORESOURCE_IO | IORESOURCE_MEM, &pf_dev->modern_bars); + if (notify == 0) + { + LOG_ERR("missing capabilities %i\n", notify); + return -EINVAL; + } + + pci_read_config_dword(pdev, notify + offsetof(struct zxdh_pf_pci_notify_cap, notify_off_multiplier), &pf_dev->notify_offset_multiplier); + pci_read_config_dword(pdev, notify + offsetof(struct zxdh_pf_pci_notify_cap, cap.length), ¬ify_length); + pci_read_config_dword(pdev, notify + offsetof(struct zxdh_pf_pci_notify_cap, cap.offset), ¬ify_offset); + + /* We don't know how many VQs we'll map, ahead of the time. + * If notify length is small, map it all now. Otherwise, map each VQ individually later. */ + if ((uint64_t)notify_length + (notify_offset % PAGE_SIZE) <= PAGE_SIZE) + { + pf_dev->notify_base = zxdh_pf_map_capability(dh_dev, notify, ZXDH_PF_MAP_MINLEN2, ZXDH_PF_ALIGN2, + 0, notify_length, &pf_dev->notify_len, &pf_dev->notify_pa); + if (unlikely(pf_dev->notify_base == NULL)) + { + LOG_ERR("pf_dev->notify_base is null\n"); + return -EINVAL; + } + } + else + { + pf_dev->notify_map_cap = notify; + } + + return 0; +} + +int32_t zxdh_pf_device_cfg_init(struct dh_core_dev *dh_dev) +{ + int32_t device = 0; + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + struct pci_dev *pdev = dh_dev->pdev; + + /* Device capability is only mandatory for devices that have device-specific configuration. */ + device = zxdh_pf_pci_find_capability(pdev, ZXDH_PCI_CAP_DEVICE_CFG, IORESOURCE_IO | IORESOURCE_MEM, &pf_dev->modern_bars); + + /* we don't know how much we should map, but PAGE_SIZE is more than enough for all existing devices. */ + if (device) + { + pf_dev->device = zxdh_pf_map_capability(dh_dev, device, 0, ZXDH_PF_ALIGN4, 0, PAGE_SIZE, &pf_dev->device_len, NULL); + if (unlikely(pf_dev->device == NULL)) + { + LOG_ERR("pf_dev->device is null\n"); + return -EINVAL; + } + } + return 0; +} + +void zxdh_pf_modern_cfg_uninit(struct dh_core_dev *dh_dev) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + struct pci_dev *pdev = dh_dev->pdev; + + if (pf_dev->device) + { + pci_iounmap(pdev, pf_dev->device); + } + if (pf_dev->notify_base) + { + pci_iounmap(pdev, pf_dev->notify_base); + } + pci_iounmap(pdev, pf_dev->common); +} + +int32_t zxdh_pf_modern_cfg_init(struct dh_core_dev *dh_dev) +{ + int32_t ret = 0; + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + struct pci_dev *pdev = dh_dev->pdev; + + ret = zxdh_pf_common_cfg_init(dh_dev); + if (ret != 0) + { + LOG_ERR("zxdh_pf_common_cfg_init failed: %d\n", ret); + return -EINVAL; + } + + ret = zxdh_pf_notify_cfg_init(dh_dev); + if (ret != 0) + { + LOG_ERR("zxdh_pf_notify_cfg_init failed: %d\n", ret); + goto err_map_notify; + } + + ret = zxdh_pf_device_cfg_init(dh_dev); + if (ret != 0) + { + LOG_ERR("zxdh_pf_device_cfg_init failed: %d\n", ret); + goto err_map_device; + } + + return 0; + +err_map_device: + if (pf_dev->notify_base) + { + pci_iounmap(pdev, pf_dev->notify_base); + } +err_map_notify: + pci_iounmap(pdev, pf_dev->common); + return -EINVAL; +} + +uint16_t zxdh_pf_get_queue_notify_off(struct dh_core_dev *dh_dev, uint16_t index) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + + iowrite16(index, &pf_dev->common->queue_select); + + return ioread16(&pf_dev->common->queue_notify_off); +} + +void __iomem * zxdh_pf_map_vq_notify(struct dh_core_dev *dh_dev, uint32_t index, resource_size_t *pa) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + uint16_t off = 0; + + off = zxdh_pf_get_queue_notify_off(dh_dev, index); + + if (pf_dev->notify_base) + { + /* offset should not wrap */ + if ((uint64_t)off * pf_dev->notify_offset_multiplier + 2 > pf_dev->notify_len) + { + LOG_ERR("bad notification offset %u (x %u) " "for queue %u > %zd", + off, pf_dev->notify_offset_multiplier, index, pf_dev->notify_len); + return NULL; + } + + if (pa) + { + *pa = pf_dev->notify_pa + off * pf_dev->notify_offset_multiplier; + } + + return pf_dev->notify_base + off * pf_dev->notify_offset_multiplier; + } + else + { + return zxdh_pf_map_capability(dh_dev, pf_dev->notify_map_cap, 2, 2, + off * pf_dev->notify_offset_multiplier, 2, NULL, pa); + } +} + +void zxdh_pf_unmap_vq_notify(struct dh_core_dev *dh_dev, void *priv) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + + if (!pf_dev->notify_base) + { + pci_iounmap(dh_dev->pdev, priv); + } +} + +void zxdh_pf_set_status(struct dh_core_dev *dh_dev, uint8_t status) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + + iowrite8(status, &pf_dev->common->device_status); + + return; +} + +uint8_t zxdh_pf_get_status(struct dh_core_dev *dh_dev) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + + return ioread8(&pf_dev->common->device_status); +} + +void zxdh_pf_get_vf_mac(struct dh_core_dev *dh_dev, uint8_t *mac, int32_t vf_id) +{ + uint32_t DEV_MAC_L = 0; + uint16_t DEV_MAC_H = 0; + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + + DEV_MAC_L = ioread32((const void __iomem *)(pf_dev->pf_sriov_cap_base + (pf_dev->sriov_bar_size) * vf_id + ZXDH_DEV_MAC_LOW_OFFSET)); + mac[0] = DEV_MAC_L & 0xff; + mac[1] = (DEV_MAC_L >> 8) & 0xff; + mac[2] = (DEV_MAC_L >> 16) & 0xff; + mac[3] = (DEV_MAC_L >> 24) & 0xff; + DEV_MAC_H = ioread16((const void __iomem *)(pf_dev->pf_sriov_cap_base + (pf_dev->sriov_bar_size) * vf_id + ZXDH_DEV_MAC_HIGH_OFFSET)); + mac[4] = DEV_MAC_H & 0xff; + mac[5] = (DEV_MAC_H >> 8) & 0xff; + return; +} + +void zxdh_pf_set_vf_mac(struct dh_core_dev *dh_dev, uint8_t *mac, int32_t vf_id) +{ + uint32_t DEV_MAC_L = 0; + uint16_t DEV_MAC_H = 0; + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + + DEV_MAC_L = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24); + DEV_MAC_H = mac[4] | (mac[5] << 8); + iowrite32(DEV_MAC_L, (void __iomem *)(pf_dev->pf_sriov_cap_base + (pf_dev->sriov_bar_size) * vf_id + ZXDH_DEV_MAC_LOW_OFFSET)); + iowrite16(DEV_MAC_H, (void __iomem *)(pf_dev->pf_sriov_cap_base + (pf_dev->sriov_bar_size) * vf_id + ZXDH_DEV_MAC_HIGH_OFFSET)); + return; +} + +void zxdh_set_mac(struct dh_core_dev *dh_dev, uint8_t *mac) +{ + uint32_t DEV_MAC_L = 0; + uint16_t DEV_MAC_H = 0; + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + + DEV_MAC_L = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24); + DEV_MAC_H = mac[4] | (mac[5] << 8); + iowrite32(DEV_MAC_L, (void __iomem *)(pf_dev->pci_ioremap_addr[0] + ZXDH_DEV_MAC_LOW_OFFSET)); + iowrite16(DEV_MAC_H, (void __iomem *)(pf_dev->pci_ioremap_addr[0] + ZXDH_DEV_MAC_HIGH_OFFSET)); + return; +} + +void zxdh_get_mac(struct dh_core_dev *dh_dev, uint8_t *mac) +{ + uint32_t DEV_MAC_L = 0; + uint16_t DEV_MAC_H = 0; + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + + DEV_MAC_L = ioread32((void __iomem *)(pf_dev->pci_ioremap_addr[0] + ZXDH_DEV_MAC_LOW_OFFSET)); + mac[0] = DEV_MAC_L & 0xff; + mac[1] = (DEV_MAC_L >> 8) & 0xff; + mac[2] = (DEV_MAC_L >> 16) & 0xff; + mac[3] = (DEV_MAC_L >> 24) & 0xff; + DEV_MAC_H = ioread16((void __iomem *)(pf_dev->pci_ioremap_addr[0] + ZXDH_DEV_MAC_HIGH_OFFSET)); + mac[4] = DEV_MAC_H & 0xff; + mac[5] = (DEV_MAC_H >> 8) & 0xff; + return; +} + +uint64_t zxdh_pf_get_features(struct dh_core_dev *dh_dev) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + uint64_t device_feature = 0; + + iowrite32(0, &pf_dev->common->device_feature_select); + device_feature = ioread32(&pf_dev->common->device_feature); + iowrite32(1, &pf_dev->common->device_feature_select); + device_feature |= ((uint64_t)ioread32(&pf_dev->common->device_feature) << 32); + + return device_feature; +} + +void zxdh_pf_set_features(struct dh_core_dev *dh_dev, uint64_t features) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + + iowrite32(0, &pf_dev->common->guest_feature_select); + iowrite32((uint32_t)features, &pf_dev->common->guest_feature); + iowrite32(1, &pf_dev->common->guest_feature_select); + iowrite32(features >> 32, &pf_dev->common->guest_feature); + + return; +} + +void zxdh_pf_set_queue_enable(struct dh_core_dev *dh_dev, uint16_t index, bool enable) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + + iowrite16(index, &pf_dev->common->queue_select); + iowrite16(enable, &pf_dev->common->queue_enable); +} + +uint32_t zxdh_pf_get_epbdf(struct dh_core_dev *dh_dev) +{ + struct pci_dev *pdev = dh_dev->pdev; + uint32_t domain = 0; + uint32_t bus = 0; + uint32_t devid = 0; + uint32_t function = 0; + uint32_t epbdf = 0; + + if (pdev == NULL) + { + LOG_ERR("err: pdev null, return epbdf data 0.\n"); + return 0; + } + + if(sscanf(pci_name(pdev), "%x:%x:%x.%u", &domain, &bus, &devid, &function) != 4) + { + LOG_ERR("failed to get pcie bus-info\n"); + return 0; + } + epbdf = BDF_ECAM(bus, devid, function); + + return epbdf; +} + +int zxdh_pf_get_pannel_port_num(struct dh_core_dev *dh_dev) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + + return pf_dev->pannel_port_num; +} + +uint16_t zxdh_pf_get_vport(struct dh_core_dev *dh_dev) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + + return pf_dev->vport; +} + +enum dh_coredev_type zxdh_pf_get_coredev_type(struct dh_core_dev *dh_dev) +{ + return dh_dev->coredev_type; +} + +uint16_t zxdh_pf_get_pcie_id(struct dh_core_dev *dh_dev) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + + return pf_dev->pcie_id; +} + +uint16_t zxdh_pf_get_slot_id(struct dh_core_dev *dh_dev) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + + return pf_dev->slot_id; +} + +bool zxdh_pf_is_bond(struct dh_core_dev *dh_dev) +{ + bool flags = false; + + if (!dh_core_is_pf(dh_dev)) + { + return false; + } + + if ((dh_dev->pdev->device == ZXDH_INICA_BOND_DEVICE_ID) + || (dh_dev->pdev->device == ZXDH_INICB_BOND_DEVICE_ID) + || (dh_dev->pdev->device == ZXDH_INICA_UPF_BOND_DEVICE_ID) + || (dh_dev->pdev->device == ZXDH_DPUA_BOND_DEVICE_ID)) + { + flags = true; + } + + return flags; +} + +bool zxdh_pf_is_upf(struct dh_core_dev *dh_dev) +{ + bool flags = false; + + if ((dh_dev->pdev->device == ZXDH_UPF_PF_I512_DEVICE_ID) + || (dh_dev->pdev->device == ZXDH_UPF_VF_I512_DEVICE_ID)) + { + flags = true; + } + + return flags; +} + +struct zxdh_vf_item *zxdh_pf_get_vf_item(struct dh_core_dev *dh_dev, uint16_t vf_idx) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + + if (dh_dev->coredev_type != DH_COREDEV_PF) + { + LOG_ERR("Invalid device\n"); + return ERR_PTR(-EINVAL); + } + + if (vf_idx >= ZXDH_VF_NUM_MAX) + { + LOG_ERR("vf idx(%u) out of range(0~255)\n", vf_idx); + return ERR_PTR(-EINVAL); + } + + if (pf_dev->vf_item == NULL) + { + LOG_ERR("vf_item is NULL\n"); + return ERR_PTR(-EINVAL); + } + + if (!pf_dev->vf_item[vf_idx].enable) + { + LOG_ERR("vf(%u) is disable\n", vf_idx); + return ERR_PTR(-EINVAL); + } + + return &(pf_dev->vf_item[vf_idx]); +} + +int32_t zxdh_pf_dpp_init(struct dh_core_dev *dh_dev) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + DPP_PF_INFO_T pf_info = {0}; + + pf_info.slot = pf_dev->slot_id; + pf_info.vport = pf_dev->vport; + return dpp_vport_register(&pf_info, dh_dev->pdev); +} + +int32_t zxdh_pf_dpp_uninit(struct dh_core_dev *dh_dev) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + DPP_PF_INFO_T pf_info = {0}; + + pf_info.slot = pf_dev->slot_id; + pf_info.vport = pf_dev->vport; + return dpp_vport_unregister(&pf_info); +} + +void zxdh_pf_ip6mac_lock_init(struct dh_core_dev *dh_dev) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + if (dh_dev->coredev_type == DH_COREDEV_PF) + { + spin_lock_init(&pf_dev->vf_ip6mac_lock); + } +} + +int32_t zxdh_init_ip6mac_tbl(struct dh_core_dev *dh_dev) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + struct zxdh_ipv6_mac_entry *ip6mac_entry_list = NULL; + unsigned int ip6mact_size = DEV_MULTICAST_MAX_NUM; + int i; + + pf_dev->ip6mac_tbl = kvzalloc(struct_size(pf_dev->ip6mac_tbl, hash_list, ip6mact_size), GFP_KERNEL); + if (!pf_dev->ip6mac_tbl) + { + LOG_ERR("kvzalloc ip6mac_tbl failed\n"); + return -ENOMEM; + } + + pf_dev->ip6mac_tbl->ip6mact_size = ip6mact_size; + + INIT_LIST_HEAD(&pf_dev->ip6mac_tbl->ip6mac_free_head); + + rwlock_init(&pf_dev->ip6mac_tbl->lock); + + for (i = 0; i < pf_dev->ip6mac_tbl->ip6mact_size; ++i) + INIT_LIST_HEAD(&pf_dev->ip6mac_tbl->hash_list[i]); + + ip6mac_entry_list = kvcalloc(pf_dev->ip6mac_tbl->ip6mact_size, sizeof(struct zxdh_ipv6_mac_entry), GFP_KERNEL); + if (!ip6mac_entry_list) { + kvfree(pf_dev->ip6mac_tbl); + LOG_ERR("kvcalloc ip6mac_entry_list failed\n"); + return -ENOMEM; + } + pf_dev->ip6mac_tbl->ip6mac_entry_list = (void *)ip6mac_entry_list; + + for (i = 0; i < pf_dev->ip6mac_tbl->ip6mact_size; i++) { + INIT_LIST_HEAD(&ip6mac_entry_list[i].list); + list_add_tail(&ip6mac_entry_list[i].list, &pf_dev->ip6mac_tbl->ip6mac_free_head); + } + + return 0; +} + +void zxdh_cleanup_ip6mac_tbl(struct dh_core_dev *dh_dev) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + struct zxdh_ipv6_mac_tbl *ip6mac_tbl = pf_dev->ip6mac_tbl; + + if (ip6mac_tbl) + { + if (ip6mac_tbl->ip6mac_entry_list) + { + kvfree(ip6mac_tbl->ip6mac_entry_list); + ip6mac_tbl->ip6mac_entry_list = NULL; + } + kvfree(ip6mac_tbl); + pf_dev->ip6mac_tbl = NULL; + } +} + +void zxdh_pf_initialized_init(struct dh_core_dev *dh_dev) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + + pf_dev->initialized_flags = 0; + spin_lock_init(&pf_dev->initialized_lock); +} + +void zxdh_pf_initialized_uninit(struct dh_core_dev *dh_dev) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + + pf_dev->initialized_flags = 0; +} + +struct pci_dev *zxdh_pf_get_pdev(struct dh_core_dev *dh_dev) +{ + return dh_dev->pdev; +} + +uint64_t zxdh_pf_get_bar_virt_addr(struct dh_core_dev *dh_dev, uint8_t bar_num) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + + return pf_dev->pci_ioremap_addr[bar_num]; +} + +int32_t zxdh_pf_msg_send_cmd(struct dh_core_dev *dh_dev, uint16_t module_id, void *msg, void *ack, bool is_sync) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + zxdh_reps_info *reps = (zxdh_reps_info *)(ack); + uint64_t vaddr = 0; + int32_t err = 0; + + vaddr = (uint64_t)ZXDH_BAR_MSG_BASE(pf_dev->pci_ioremap_addr[0]); + + err = zxdh_send_command(vaddr, pf_dev->pcie_id, module_id, msg, ack, TRUE); + if (err != 0) + { + LOG_ERR("zxdh_send_command failed, err=%d\n", err); + return -1; + } + + if (reps->flag != ZXDH_REPS_SUCC) + { + LOG_ERR("failed reps->flag: 0x%x\n", reps->flag); + return -1; + } + + return err; +} + +int32_t zxdh_pf_query_port(struct dh_core_dev *dh_dev) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + struct port_message_recv recv = {0}; + struct port_message_recv *recv_data = &recv; + struct zxdh_port_msg msg = {0}; + struct zxdh_port_msg *payload = &msg; + struct zxdh_pannle_port *pnlport, *recvport; + int32_t ret = 0, idx = 0; + + payload->pcie_id = zxdh_pf_get_pcie_id(dh_dev); + + ret = zxdh_pf_msg_send_cmd(dh_dev, MODULE_PHYPORT_QUERY, payload, recv_data, true); + if (ret != 0) + { + LOG_ERR("zxdh_pf_query_port send message failed \n"); + goto out; + } + + pf_dev->port_resource.pannel_num = recv_data->port_num; + + LOG_INFO("zxdh query port num: %u\n", (uint32_t)recv_data->port_num); + for (idx = 0; idx < recv_data->port_num; idx++) + { + if (idx >= ZXDH_PANNEL_PORT_MAX) + { + LOG_ERR("query port num from fw out of range. \n"); + continue; + } + + pnlport = &pf_dev->port_resource.port[idx]; + recvport = (struct zxdh_pannle_port *)((uint8_t *)&recv_data->data[idx]); + + pnlport->phyport = recvport->phyport; + pnlport->pannel_id = recvport->pannel_id; + pnlport->link_check_bit = recvport->link_check_bit; + pnlport->flags = 0; + + LOG_INFO("[%d] pannel %u, phyport %u link check bit %u\n", idx, + (uint32_t)pnlport->pannel_id, (uint32_t)pnlport->phyport, (uint32_t)pnlport->link_check_bit); + } + +out: + return ret; +} + +int32_t zxdh_pf_query_fwinfo(struct dh_core_dev *dh_dev) +{ + int32_t ret = 0; + + ret = zxdh_pf_query_port(dh_dev); + if (ret != 0) + { + return ret; + } + + return 0; +} + +uint16_t zxdh_pf_get_queue_num(struct dh_core_dev *dh_dev) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + uint16_t qnum = 0; + + qnum = ioread16(&pf_dev->common->num_queues); + + return qnum; +} + +uint16_t zxdh_pf_get_queue_size(struct dh_core_dev *dh_dev, uint16_t index) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + uint16_t queue_size = 0; + + iowrite16(index, &pf_dev->common->queue_select); + queue_size = ioread16(&pf_dev->common->queue_size); + + return queue_size; +} + +uint16_t zxdh_pf_get_queue_vector(struct dh_core_dev *dh_dev, uint16_t channel, struct list_head * eqs_list, uint16_t queue_index) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + struct zxdh_pf_pci_common_cfg __iomem *cfg = pf_dev->common; + struct dh_eq_vqs *eq_vqs = NULL; + struct dh_eq_vqs *n; + int32_t i = 0; + int32_t msix_vec = ZXDH_MSI_NO_VECTOR; + + iowrite16(queue_index, &cfg->queue_select); + + list_for_each_entry_safe(eq_vqs, n, eqs_list, list) + { + if (i++ == channel) + { + iowrite16(eq_vqs->vq_s.core.irq->index, &cfg->queue_msix_vector); + break; + } + } + + msix_vec = ioread16(&cfg->queue_msix_vector); + + /* Flush the write out to device */ + return msix_vec; +} + +void zxdh_pf_release_queue_vector(struct dh_core_dev *dh_dev, int32_t queue_index) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + struct zxdh_pf_pci_common_cfg __iomem *cfg = pf_dev->common; + + iowrite16(queue_index, &cfg->queue_select); + iowrite16(ZXDH_MSI_NO_VECTOR, &cfg->queue_msix_vector); +} + +void zxdh_pf_set_queue_size(struct dh_core_dev *dh_dev, uint32_t index, uint16_t size) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + + iowrite16(index, &pf_dev->common->queue_select); + iowrite16(size, &pf_dev->common->queue_size); +} + +void zxdh_pf_set_queue_address(struct dh_core_dev *dh_dev, uint32_t index, + uint64_t desc_addr, uint64_t driver_addr, uint64_t device_addr) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + + iowrite16(index, &pf_dev->common->queue_select); + iowrite32((uint32_t)desc_addr, &pf_dev->common->queue_desc_lo); + iowrite32(desc_addr>>32, &pf_dev->common->queue_desc_hi); + iowrite32((uint32_t)driver_addr, &pf_dev->common->queue_avail_lo); + iowrite32(driver_addr>>32, &pf_dev->common->queue_avail_hi); + iowrite32((uint32_t)device_addr, &pf_dev->common->queue_used_lo); + iowrite32(device_addr>>32, &pf_dev->common->queue_used_hi); +} + +int32_t zxdh_pf_get_vq_lock(struct dh_core_dev *dh_dev) +{ + int32_t i = 0; + int32_t val = 0; + int32_t wait_time = ZXDH_PF_WAIT_COUNT; + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + + for (i = 0; i < wait_time; i++) + { + val = ioread32((const void __iomem *)(pf_dev->pci_ioremap_addr[0] + VQM_HOST_BAR_OFFSET + LOCK_VQ_REG_OFFSET)); + udelay(ZXDH_PF_DELAY_US); + if (val & ZXDH_PF_LOCK_ENABLE_MASK) + { + break; + } + } + + if ((val & ZXDH_PF_LOCK_ENABLE_MASK) == 0) + { + LOG_INFO("get phy vq_id is busy\n"); + return -1; + } + + return 0; +} + +int32_t zxdh_pf_release_vq_lock(struct dh_core_dev *dh_dev) +{ + int32_t val = 0; + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + + val = ioread32((const void __iomem *)(pf_dev->pci_ioremap_addr[0] + VQM_HOST_BAR_OFFSET + LOCK_VQ_REG_OFFSET)); + if (val & ZXDH_PF_LOCK_ENABLE_MASK) + { + iowrite32(ZXDH_PF_RELEASE_LOCK_VAL, (void __iomem *)(pf_dev->pci_ioremap_addr[0] + VQM_HOST_BAR_OFFSET + LOCK_VQ_REG_OFFSET)); + return 0; + } + else + { + LOG_INFO("no lock need to be released\n"); + return -1; + } +} + +int32_t zxdh_pf_get_phy_vq(struct dh_core_dev *dh_dev, uint16_t index) +{ + int32_t phy_vq_reg = 0; + int32_t vq_reg_num = ZXDH_MAX_QUEUES_NUM / ZXDH_PHY_REG_BITS; + uint32_t val = 0; + uint32_t done = 0; + uint8_t queue_type = 0; + int32_t j = 0; + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + int32_t phy_index = 0; + + for (phy_vq_reg = 0; phy_vq_reg < vq_reg_num; phy_vq_reg++) + { + val = ioread32((const void __iomem *)(pf_dev->pci_ioremap_addr[0] + PHY_VQ_REG_OFFSET + phy_vq_reg * 4)); + + if (index % ZXDH_PF_POWER_INDEX2 == 0) + { + queue_type = ZXDH_PF_RQ_TYPE; + } + else + { + queue_type = ZXDH_PF_TQ_TYPE; + } + + for (j = queue_type; j < ZXDH_PHY_REG_BITS; j = j + ZXDH_PF_POWER_INDEX2) + { + if ((val & (ZXDH_PF_GET_PHY_INDEX_BIT << j)) == 0) + { + val |= (ZXDH_PF_GET_PHY_INDEX_BIT << j); + iowrite32(val, (void __iomem *)(pf_dev->pci_ioremap_addr[0] + PHY_VQ_REG_OFFSET + phy_vq_reg * 4)); + phy_index = phy_vq_reg * ZXDH_PHY_REG_BITS + j; + done = ZXDH_PF_GET_PHY_INDEX_DONE; + break; + } + } + + if (done == ZXDH_PF_GET_PHY_INDEX_DONE) + { + return phy_index; + } + } + + LOG_INFO("no availd phy_index\n"); + + return -1; +} + +int32_t zxdh_pf_release_phy_vq(struct dh_core_dev *dh_dev, uint32_t *phy_index, uint16_t total_qnum) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + uint16_t lch = 0; + uint16_t widx = 0; + uint16_t bidx = 0; + uint32_t val = 0; + + for (lch = 0; lch < total_qnum; lch++) + { + if (phy_index[lch] >= ZXDH_MAX_QUEUES_NUM) + { + continue; + } + + widx = phy_index[lch] / 32; //4byte -> 32bits + bidx = phy_index[lch] % 32; + + udelay(ZXDH_PF_DELAY_US); + val = ioread32((const void __iomem *)(pf_dev->pci_ioremap_addr[0] + PHY_VQ_REG_OFFSET + widx * 4)); + val &= ~(1 << bidx); + iowrite32(val, (void __iomem *)(pf_dev->pci_ioremap_addr[0] + PHY_VQ_REG_OFFSET + widx * 4)); + } + + return 0; +} + + +void zxdh_pf_update_link_info(struct dh_core_dev *dh_dev, struct link_info_struct *link_info_val) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + if(pf_dev->link_up && link_info_val->speed == SPEED_UNKNOWN) + { + LOG_INFO("pf_dev->link_up is %d and link_info_val->speed is %d, can't update pf info\n",pf_dev->link_up ,link_info_val->speed); + return; + } + pf_dev->speed = link_info_val->speed; + pf_dev->autoneg_enable = link_info_val->autoneg_enable; + pf_dev->supported_speed_modes = link_info_val->supported_speed_modes; + pf_dev->advertising_speed_modes = link_info_val->advertising_speed_modes; + pf_dev->duplex = link_info_val->duplex; +} + +int32_t zxdh_pf_get_drv_msg(struct dh_core_dev *dh_dev, uint8_t *drv_version, uint8_t *drv_version_len) +{ + *drv_version_len = sizeof(zxdh_pf_driver_version); + memcpy(drv_version, zxdh_pf_driver_version, *drv_version_len); + return 0; +} + +void zxdh_pf_set_vepa(struct dh_core_dev *dh_dev, bool setting) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + + pf_dev->vepa = setting; +} + +bool zxdh_pf_get_vepa(struct dh_core_dev *dh_dev) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + + return pf_dev->vepa; +} + +int32_t zxdh_pf_request_port(struct dh_core_dev *dh_dev, void *data) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + uint8_t port_num = pf_dev->port_resource.pannel_num; + struct zxdh_pannle_port *port; + struct zxdh_pannle_port *req_data = (struct zxdh_pannle_port *)data; + int32_t idx = 0; + + for (idx = 0; idx < port_num; idx++) + { + port = &pf_dev->port_resource.port[idx]; + if (!(port->flags & PORT_FLAGS_ALLOC_STAT)) + { + req_data->phyport = port->phyport; + req_data->pannel_id = port->pannel_id; + req_data->link_check_bit = port->link_check_bit; + port->flags |= PORT_FLAGS_ALLOC_STAT; + break; + } + } + + if (idx == port_num) + { + LOG_ERR("failed to obtain the panel information from the riscv, or this part is not released when the aux is removed\n"); + return -1; + } + + return 0; +} + +int32_t zxdh_pf_release_port(struct dh_core_dev *dh_dev, uint32_t pnl_id) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + uint8_t port_num = pf_dev->port_resource.pannel_num; + struct zxdh_pannle_port *port; + int32_t idx = 0; + + for (idx = 0; idx < port_num; idx++) + { + port = &pf_dev->port_resource.port[idx]; + if (pnl_id == port->pannel_id) + { + port->flags &= ~PORT_FLAGS_ALLOC_STAT; + break; + } + } + + return 0; +} + +void zxdh_pf_set_bond_num(struct dh_core_dev *dh_dev, bool add) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + + if (add) + { + pf_dev->bond_num++; + } + else + { + pf_dev->bond_num--; + } +} + +bool zxdh_pf_if_init(struct dh_core_dev *dh_dev) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + + if (pf_dev->bond_num == 0) + { + return true; + } + + return false; +} + +void zxdh_pf_set_init_comp_flag(struct dh_core_dev *dh_dev) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + + pf_dev->aux_comp_flag = ZXDH_AUX_COMP_FLAG; + return; +} + +struct zxdh_ipv6_mac_tbl * zxdh_pf_get_ip6mac_tbl(struct dh_core_dev *dh_dev) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + + return pf_dev->ip6mac_tbl; +} + +struct zxdh_en_sf_if en_sf_ops = +{ + .en_sf_map_vq_notify = zxdh_pf_map_vq_notify, + .en_sf_unmap_vq_notify = zxdh_pf_unmap_vq_notify, + .en_sf_set_status = zxdh_pf_set_status, + .en_sf_get_status = zxdh_pf_get_status, + .en_sf_get_features = zxdh_pf_get_features, + .en_sf_set_features = zxdh_pf_set_features, + .en_sf_set_vf_mac = zxdh_pf_set_vf_mac, + .en_sf_get_vf_mac = zxdh_pf_get_vf_mac, + .en_sf_set_mac = zxdh_set_mac, + .en_sf_get_mac = zxdh_get_mac, + .en_sf_set_queue_enable = zxdh_pf_set_queue_enable, + .en_sf_get_channels_num = zxdh_pf_get_vqs_channels_num, + .en_sf_get_queue_num = zxdh_pf_get_queue_num, + .en_sf_get_queue_size = zxdh_pf_get_queue_size, + .en_sf_get_queue_vector = zxdh_pf_get_queue_vector, + .en_sf_release_queue_vector = zxdh_pf_release_queue_vector, + .en_sf_set_queue_size = zxdh_pf_set_queue_size, + .en_sf_set_queue_address = zxdh_pf_set_queue_address, + .en_sf_vq_irqs_request = zxdh_pf_vq_irqs_request, + .en_sf_affinity_irqs_release = zxdh_pf_affinity_irqs_release, + .en_sf_switch_irq = zxdh_pf_switch_irq, + .en_sf_get_vq_lock = zxdh_pf_get_vq_lock, + .en_sf_release_vq_lock = zxdh_pf_release_vq_lock, + .en_sf_get_phy_vq = zxdh_pf_get_phy_vq, + .en_sf_release_phy_vq = zxdh_pf_release_phy_vq, + .en_sf_get_epbdf = zxdh_pf_get_epbdf, + .en_sf_get_vport = zxdh_pf_get_vport, + .en_sf_get_coredev_type = zxdh_pf_get_coredev_type, + .en_sf_get_pcie_id = zxdh_pf_get_pcie_id, + .en_sf_get_slot_id = zxdh_pf_get_slot_id, + .en_sf_is_bond = zxdh_pf_is_bond, + .en_sf_is_upf = zxdh_pf_is_upf, + .en_sf_get_pdev = zxdh_pf_get_pdev, + .en_sf_get_bar_virt_addr = zxdh_pf_get_bar_virt_addr, + .en_sf_msg_send_cmd = zxdh_pf_msg_send_cmd, + .en_sf_async_eq_enable = zxdh_pf_async_eq_enable, + .en_sf_get_vf_item = zxdh_pf_get_vf_item, + .en_sf_set_pf_link_up = zxdh_pf_set_pf_link_up, + .en_sf_get_pf_link_up = zxdh_pf_get_pf_link_up, + .en_sf_update_pf_link_info = zxdh_pf_update_link_info, + .en_sf_get_drv_msg = zxdh_pf_get_drv_msg, + .en_sf_get_vepa = zxdh_pf_get_vepa, + .en_sf_set_vepa = zxdh_pf_set_vepa, + .en_sf_set_bond_num = zxdh_pf_set_bond_num, + .en_sf_if_init = zxdh_pf_if_init, + .en_sf_request_port_info = zxdh_pf_request_port, + .en_sf_release_port_info = zxdh_pf_release_port, + .en_sf_get_link_info_from_vqm = zxdh_pf_get_link_info_from_vqm, + .en_sf_set_vf_link_info = zxdh_pf_set_vf_link_info, + .en_sf_set_pf_phy_port = zxdh_pf_set_pf_phy_port, + .en_sf_get_pf_phy_port = zxdh_pf_get_pf_phy_port, + .en_sf_set_init_comp_flag = zxdh_pf_set_init_comp_flag, + .en_sf_get_ip6mac_tbl = zxdh_pf_get_ip6mac_tbl, +}; + +void zxdh_adev_release(struct device *dev) +{ + +} + +static DEFINE_IDA(zxdh_adev_ida); + +int32_t zxdh_plug_aux_dev(struct dh_core_dev *dh_dev, int32_t idx) +{ + struct zxdh_auxiliary_device *adev = NULL; + struct zxdh_pf_device *pf_dev = NULL; + struct zxdh_en_sf_container *sf_con = NULL; + struct zxdh_pf_adev *pf_adevs_table = NULL; + int32_t ret = 0; + + pf_dev = dh_core_priv(dh_dev); + + if (idx >= pf_dev->adevs_num) + { + return 0; + } + + pf_adevs_table = &pf_dev->adevs_table[idx]; + if (pf_adevs_table->adev != NULL) + { + return 0; + } + + sf_con = kzalloc(sizeof(struct zxdh_en_sf_container), GFP_KERNEL); + + if (unlikely(sf_con == NULL)) + { + LOG_ERR("zxadev kzalloc is null\n"); + return -ENOMEM; + } + + pf_adevs_table->aux_idx = ida_alloc(&zxdh_adev_ida, GFP_KERNEL); + if (pf_adevs_table->aux_idx < 0) + { + LOG_ERR("failed to allocate device id for aux drvs\n"); + goto free_kzalloc; + } + + adev = &sf_con->adev; + + adev->id = pf_adevs_table->aux_idx; + adev->dev.parent = &dh_dev->pdev->dev; + adev->dev.release = zxdh_adev_release; + adev->name = ZXDH_PF_EN_SF_DEV_ID_NAME; + + pf_adevs_table->adev = adev; + sf_con->dh_dev = dh_dev; + sf_con->ops = &en_sf_ops; + + ret = zxdh_auxiliary_device_init(adev); + if (ret != 0) + { + LOG_ERR("zxdh_auxiliary_device_init failed: %d\n", ret); + goto free_ida_alloc; + } + + ret = zxdh_auxiliary_device_add(adev); + if (ret != 0) + { + LOG_ERR("zxdh_auxiliary_device_add failed: %d\n", ret); + goto release_aux_init; + } + + return 0; + +release_aux_init: + zxdh_auxiliary_device_uninit(adev); +free_ida_alloc: + ida_simple_remove(&zxdh_adev_ida, pf_adevs_table->aux_idx); + pf_adevs_table->aux_idx = -1; +free_kzalloc: + kfree(sf_con); + sf_con = NULL; + return ret; +} + +void zxdh_unplug_aux_dev(struct dh_core_dev *dh_dev, int32_t idx) +{ + struct zxdh_pf_device *pf_dev = NULL; + struct zxdh_en_sf_container *sf_con = NULL; + struct zxdh_pf_adev *pf_adevs_table = NULL; + + pf_dev = dh_core_priv(dh_dev); + if (idx >= pf_dev->adevs_num) + { + return; + } + + pf_adevs_table = &pf_dev->adevs_table[idx]; + if (!pf_adevs_table->adev) + { + return; + } + + sf_con = container_of(pf_adevs_table->adev, struct zxdh_en_sf_container, adev); + + zxdh_auxiliary_device_delete(pf_adevs_table->adev); + zxdh_auxiliary_device_uninit(pf_adevs_table->adev); + ida_simple_remove(&zxdh_adev_ida, pf_adevs_table->aux_idx); + pf_adevs_table->aux_idx = -1; + kfree(sf_con); + sf_con = NULL; + + return; +} + +int32_t dh_pf_vf_vport_get(struct dh_core_dev *dev, uint16_t vf_idx, uint16_t *vport) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dev); + uint16_t pcie_id = 0; + struct zxdh_pci_bar_msg in = {0}; + struct zxdh_msg_recviver_mem result = {0}; + uint8_t recv_buf[8] = {0}; + int32_t ret = 0; + + if (vport == NULL) + { + return BAR_MSG_ERR_NULL; + } + + pcie_id = FIND_VF_PCIE_ID(pf_dev->pcie_id, vf_idx); + + in.virt_addr = (uint64_t)ZXDH_BAR_MSG_BASE(pf_dev->pci_ioremap_addr[0]); + in.payload_addr = &pcie_id; + in.payload_len = sizeof(pcie_id); + in.src = MSG_CHAN_END_PF; + in.dst = MSG_CHAN_END_RISC; + in.event_id = MODULE_VPORT_GET; + in.src_pcieid = pf_dev->pcie_id; + + result.recv_buffer = recv_buf; + result.buffer_len = sizeof(recv_buf); + + ret = zxdh_bar_chan_sync_msg_send(&in, &result); + switch (ret) + { + case BAR_MSG_OK: + { + *vport = *(uint16_t *)(recv_buf + 4); + LOG_INFO("pf(0x%x) get vf(%u) vport(0x%x) success\n", pf_dev->pcie_id, vf_idx, *vport); + break; + } + default: + { + LOG_ERR("Failed to pf(0x%x) get vf(%u) vport, ret:%d.\n", pcie_id, vf_idx, ret); + break; + } + } + + return ret; +} + +int32_t dh_pf_vf_item_init(struct dh_core_dev *dev, uint16_t vf_idx) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dev); + struct zxdh_vf_item *vf_item = NULL; + + if (pf_dev->vf_item == NULL) + { + LOG_ERR("vf_item is NULL\n"); + return -EINVAL; + } + vf_item = &pf_dev->vf_item[vf_idx]; + vf_item->link_forced = false; + vf_item->vport = pf_dev->vf_item[0].vport + vf_idx; + vf_item->enable = true; + vf_item->spoofchk = true; + return 0; +} + +int32_t dh_pf_vf_item_uninit(struct dh_core_dev *dev, uint16_t vf_idx) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dev); + struct zxdh_vf_item *vf_item = NULL; + + if (pf_dev->vf_item == NULL) + { + LOG_ERR("vf_item is NULL\n"); + return -EINVAL; + } + vf_item = &pf_dev->vf_item[vf_idx]; + eth_zero_addr(vf_item->mac); + vf_item->pf_set_mac = false; + vf_item->enable = false; + vf_item->vlan = 0; + vf_item->qos = 0; + vf_item->spoofchk = false; + return 0; +} + +int32_t dh_pf_vf_enable(struct dh_core_dev *dev, int32_t num_vfs) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dev); + int32_t vf_idx = 0; + int32_t ret = 0; + + ret = dh_pf_vf_vport_get(dev, 0, &pf_dev->vf_item[0].vport); + if (ret != 0) + { + return ret; + } + + for (vf_idx = 0; vf_idx < num_vfs; vf_idx++) + { + ret = dh_pf_vf_item_init(dev, vf_idx); + if (ret != 0) + { + LOG_ERR("Failed to init vf(%d) item\n", vf_idx); + return ret; + } + } + + return ret; +} + +void dh_pf_vf_disable(struct dh_core_dev *dev, int32_t num_vfs) +{ + int32_t vf_idx = 0; + + for (vf_idx = 0; vf_idx < num_vfs; vf_idx++) + { + dh_pf_vf_item_uninit(dev, vf_idx); + } +} + +int32_t dh_pf_sriov_enable(struct pci_dev *pdev, int32_t num_vfs) +{ + struct dh_core_dev *dev = pci_get_drvdata(pdev); + int32_t pre_existing_vfs = pci_num_vf(pdev); + int32_t ret = 0; + + if ((pre_existing_vfs != 0) && (pre_existing_vfs == num_vfs)) + { + return 0; + } + + ret = dh_pf_vf_enable(dev, num_vfs); + if (ret != 0) + { + LOG_ERR("Failed to enable vf\n"); + return ret; + } + +#ifdef ZXDH_SRIOV_SYSFS_EN + ret = zxdh_create_vfs_sysfs(dev, num_vfs); + if (ret != 0) + { + LOG_ERR("zxdh_create_vfs_sysfs failed : %d\n", ret); + goto err_create_vfs_sysfs; + } +#endif + + ret = pci_enable_sriov(pdev, num_vfs); + if (ret != 0) + { + LOG_ERR("pci_enable_sriov failed : %d\n", ret); + goto err_pci_enable_sriov; + } + + return ret; + +err_pci_enable_sriov: +#ifdef ZXDH_SRIOV_SYSFS_EN + zxdh_sriov_sysfs_exit(dev); +err_create_vfs_sysfs: +#endif + dh_pf_vf_disable(dev, num_vfs); + + return ret; +} + +void dh_pf_sriov_disable(struct pci_dev *pdev) +{ + struct dh_core_dev *dev = pci_get_drvdata(pdev); + int32_t num_vfs = pci_num_vf(pdev); + + pci_disable_sriov(pdev); +#ifdef ZXDH_SRIOV_SYSFS_EN + zxdh_destroy_vfs_sysfs(dev, num_vfs); +#endif + dh_pf_vf_disable(dev, num_vfs); +} + +int32_t dh_pf_vf_item_create(struct dh_core_dev *dev) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dev); + + if (dev->coredev_type == DH_COREDEV_PF) + { + pf_dev->vf_item = kzalloc(sizeof(struct zxdh_vf_item) * ZXDH_VF_NUM_MAX, GFP_KERNEL); + if (pf_dev->vf_item == NULL) + { + LOG_ERR("pf_dev->vf_item kzalloc failed\n"); + return -ENOMEM; + } + } + + return 0; +} + +void dh_pf_vf_item_destroy(struct dh_core_dev *dev, bool disable_vf) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dev); + + if (dev->coredev_type == DH_COREDEV_PF) + { + if (disable_vf) + { + pci_disable_sriov(dev->pdev); + } + if (pf_dev->vf_item != NULL) + { + kfree(pf_dev->vf_item); + pf_dev->vf_item = NULL; + } + } +} + +int32_t dh_pf_pcie_id_get(struct dh_core_dev *dh_dev) +{ + int32_t pos = 0; + uint8_t type = 0; + uint16_t padding = 0; + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + struct pci_dev *pdev = dh_dev->pdev; + + if (dh_dev->coredev_type == DH_COREDEV_PF) + { + if (pdev->bus == NULL) + { + LOG_ERR("pdev->bus is NULL!\n"); + return -1; + } + pf_dev->slot_id = pdev->bus->number; + LOG_INFO("pf_dev->slot_id: %d\n", pf_dev->slot_id); + } + for (pos = pci_find_capability(pdev, PCI_CAP_ID_VNDR); pos > 0; pos = pci_find_next_capability(pdev, pos, PCI_CAP_ID_VNDR)) + { + pci_read_config_byte(pdev, pos + offsetof(struct zxdh_pf_pci_cap, cfg_type), &type); + + if (type == ZXDH_PCI_CAP_PCI_CFG) + { + pci_read_config_word(pdev, pos + offsetof(struct zxdh_pf_pci_cap, padding[0]), &padding); + pf_dev->pcie_id = padding; + LOG_INFO("pf_dev->pcie_id: 0x%x\n", pf_dev->pcie_id); + return 0; + } + } + + LOG_INFO("the pci_cap that meets the requirements is not matched\n"); + return -1; +} + +static uint64_t pci_size(uint64_t base, uint64_t maxbase, uint64_t mask) +{ + uint64_t size = mask & maxbase; + + if (!size) + return 0; + size = size & ~(size-1); + if (base == maxbase && ((base | (size - 1)) & mask) != mask) + return 0; + return size; +} + +int32_t zxdh_send_pxe_status_to_riscv(struct dh_core_dev *dh_dev) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + zxdh_cfg_np_msg msg = {0}; + uint64_t vaddr = 0; + int32_t err = 0; + + if (dh_dev->coredev_type != DH_COREDEV_PF) + { + return 0; + } + + msg.dev_id = 0; + msg.type = ZXDH_CFG_NPSDK_TYPE; + msg.operate_mode = ZXDH_STOP_PXE_MODE; + + vaddr = (uint64_t)ZXDH_BAR_MSG_BASE(pf_dev->pci_ioremap_addr[0]); + + err = zxdh_send_command(vaddr, pf_dev->pcie_id, MODULE_NPSDK, &msg, &msg, true); + if (err != 0) + { + LOG_ERR("send pxe status to config np failed: %d\n", err); + } + + return err; +} + +int32_t dh_pf_sriov_cap_cfg_init(struct dh_core_dev *dh_dev) +{ + int32_t pos = 0; + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + struct pci_dev *pdev = dh_dev->pdev; + uint32_t bar_address32 = 0; + uint64_t bar_address64 = 0; + uint64_t bar_size64 = 0; + uint32_t bar_size32 = 0; + uint64_t mask64 = 0; + uint32_t mem_type = 0; + uint16_t nr_virtfn = 0; + + if(dh_dev->coredev_type == DH_COREDEV_VF) + { + return 0; + } + + pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV); + if (pos == 0) + { + return 0; + } + pci_read_config_word(pdev, pos + PCI_SRIOV_TOTAL_VF, &nr_virtfn); + + if (nr_virtfn == 0) + { + return 0; + } + + pci_read_config_dword(pdev, pos + PCI_SRIOV_BAR, &bar_address32); + pci_write_config_dword(pdev, pos + PCI_SRIOV_BAR, ~0); + pci_read_config_dword(pdev, pos + PCI_SRIOV_BAR, &bar_size32); + pci_write_config_dword(pdev, pos + PCI_SRIOV_BAR, bar_address32); + + bar_size64 = bar_size32 & PCI_BASE_ADDRESS_MEM_MASK; + bar_address64 = bar_address32 & PCI_BASE_ADDRESS_MEM_MASK; + mask64 = (uint32_t)PCI_BASE_ADDRESS_MEM_MASK; + mem_type = bar_address32 & PCI_BASE_ADDRESS_MEM_TYPE_MASK; + + if(mem_type == PCI_BASE_ADDRESS_MEM_TYPE_64) + { + pci_read_config_dword(pdev, pos + PCI_SRIOV_BAR + 4, &bar_address32); + pci_write_config_dword(pdev, pos + PCI_SRIOV_BAR + 4, ~0); + pci_read_config_dword(pdev, pos + PCI_SRIOV_BAR + 4, &bar_size32); + pci_write_config_dword(pdev, pos + PCI_SRIOV_BAR + 4, bar_address32); + + bar_size64 |= ((uint64_t)bar_size32 << 32); + bar_address64 |= ((uint64_t)bar_address32 << 32); + mask64 |= ((uint64_t)~0 << 32); + } + + bar_size64 = pci_size(bar_address64, bar_size64, mask64); + if (!bar_size64) { + LOG_ERR( "reg 0x%x: invalid BAR (can't size)\n", pos); + } + + pf_dev->pf_sriov_cap_base = (void __iomem *)ioremap(bar_address64, bar_size64 * nr_virtfn); + + if (!pf_dev->pf_sriov_cap_base) + { + LOG_ERR("ioremap(0x%llx, 0x%llx) failed\n", bar_address64, bar_size64 * nr_virtfn); + return -1; + } + pf_dev->sriov_bar_size = bar_size64; + return 0; +} + +static uint8_t zxdh_pf_fwcap_readb(struct dh_core_dev *dh_dev, uint32_t offset) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + uint64_t vaddr = (uint64_t)ZXDH_BAR_FWCAP(pf_dev->pci_ioremap_addr[0]); + + return readb((const volatile void __iomem *)(vaddr + offset)); +} + +static bool zxdh_pf_is_ovs(struct dh_core_dev *dh_dev) +{ + uint8_t product = 0; + + product = zxdh_pf_fwcap_readb(dh_dev, ZXDH_PRODUCT_TYPE); + LOG_INFO("fwcap read product type: %d\n", (int32_t)product); + + if ((product == ZXDH_PRODUCT_OVS) + || (product == ZXDH_PRODUCT_NEO) + || (product == ZXDH_PRODUCT_EVB_EP0) + || (product == ZXDH_PRODUCT_EVB_EP0_EP4)) + { + return true; + } + + return false; +} + +static void zxdh_pf_set_pannel_port_num(struct dh_core_dev *dh_dev, int port_num) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + + pf_dev->pannel_port_num = port_num; + + return; +} + +static void zxdh_pf_request_pannel_port_num(struct dh_core_dev *dh_dev, int *port_num) +{ + *port_num = (int)zxdh_pf_fwcap_readb(dh_dev, ZXDH_PANNEL_PORT_NUM); +} + +static int32_t zxdh_pf_lag_init(struct dh_core_dev *dh_dev, int32_t *port_num) +{ + int port_num_default = 1; + + /* BOND PF && 非OVS场景，则产生异常 */ + if (zxdh_pf_is_bond(dh_dev) && !zxdh_pf_is_ovs(dh_dev)) + { + return -1; + } + + if (!dh_core_is_pf(dh_dev) || !zxdh_pf_is_bond(dh_dev) || !zxdh_pf_is_ovs(dh_dev)) + { + goto out; + } + + zxdh_pf_request_pannel_port_num(dh_dev, &port_num_default); + zxdh_pf_set_pannel_port_num(dh_dev, port_num_default); + zxdh_regitster_ldev(dh_dev); + + LOG_INFO("zxdh pf lag init finish(port num %d)\n", port_num_default); +out: + zxdh_pf_set_pannel_port_num(dh_dev, port_num_default); + *port_num = port_num_default; + return 0; +} + +static void zxdh_pf_lag_exit(struct dh_core_dev *dh_dev) +{ + zxdh_unregitster_ldev(dh_dev); +} + +int32_t dh_pf_adevs_table_init(struct dh_core_dev *dh_dev, int32_t nr) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + + pf_dev->adevs_table = kzalloc(sizeof(*(pf_dev->adevs_table)) * nr, GFP_KERNEL); + if (!pf_dev->adevs_table) + { + pf_dev->adevs_num = 0; + LOG_ERR("pf_dev->adevs_table kzalloc failed\n"); + return -ENOMEM; + } + + pf_dev->adevs_num = nr; + + return 0; +} + +void dh_pf_adevs_table_destroy(struct dh_core_dev *dh_dev) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + + if (dh_dev->coredev_type == DH_COREDEV_PF) + { + if (pf_dev->adevs_table != NULL) + { + kfree(pf_dev->adevs_table); + pf_dev->adevs_table = NULL; + pf_dev->adevs_num = 0; + } + } +} + +void zxdh_unplug_aux_dev_all(struct dh_core_dev *dh_dev) +{ + int32_t idx; + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + + for (idx = 0; idx < pf_dev->adevs_num; idx++) + { + zxdh_unplug_aux_dev(dh_dev, idx); + } +} + +static int32_t dh_pf_probe(struct pci_dev *pdev, const struct pci_device_id *id) +{ + struct dh_core_dev *dh_dev = NULL; + struct zxdh_pf_device *pf_dev = NULL; + struct devlink *devlink = NULL; + int32_t ret = 0; + int32_t idx = 0; + int32_t port_num = 0; + + LOG_INFO("pf level driver probe start\n"); + + devlink = zxdh_devlink_alloc(&pdev->dev, &dh_pf_devlink_ops, sizeof(struct zxdh_pf_device)); + if (devlink == NULL) + { + LOG_ERR("devlink alloc failed\n"); + return -ENOMEM; + } + + dh_dev = devlink_priv(devlink); + dh_dev->device = &pdev->dev; + dh_dev->pdev = pdev; + dh_dev->devlink_ops = &dh_pf_core_devlink_ops; + + pf_dev = dh_core_priv(dh_dev); + pf_dev->vepa = false; + + dh_dev->coredev_type = GET_COREDEV_TYPE(pdev); + LOG_INFO("%s device: %s\n", (dh_dev->coredev_type == DH_COREDEV_PF) ? "PF" : "VF", pci_name(pdev)); + + ret = dh_pf_pci_init(dh_dev); + if (ret != 0) + { + LOG_ERR("dh_pf_pci_init failed: %d\n", ret); + goto err_irq_table_init; + } + + ret = dh_pf_pcie_id_get(dh_dev); + if (ret != 0) + { + LOG_ERR("dh_pf_pcie_id_get failed: %d\n", ret); + goto err_pci; + } + + ret = dh_pf_vf_item_create(dh_dev); + if (ret != 0) + { + LOG_ERR("Failed to alloc vf item\n"); + goto err_pci; + } + + ret = dh_pf_irq_table_init(dh_dev); + if (ret != 0) + { + LOG_ERR("Failed to alloc IRQs\n"); + goto err_vf_item; + } + + ret = dh_pf_eq_table_init(dh_dev); + if (ret != 0) + { + LOG_ERR("Failed to alloc IRQs\n"); + goto err_eq_table_init; + } + + ret = dh_pf_events_init(dh_dev); + if (ret != 0) + { + LOG_ERR("failed to initialize events\n"); + goto err_events_init; + } + + ret = dh_pf_irq_table_create(dh_dev); + if (ret != 0) + { + LOG_ERR("Failed to alloc IRQs\n"); + goto err_irq_table_create; + } + + ret = dh_pf_eq_table_create(dh_dev); + if (ret != 0) + { + LOG_ERR("Failed to alloc EQs\n"); + goto err_eq_table_create; + } + + ret = dh_pf_sriov_cap_cfg_init(dh_dev); + if (ret != 0) + { + LOG_ERR("dh_pf_sriov_cap_cfg_init failed: %d\n", ret); + goto err_sriov_cap_init; + } + + ret = zxdh_pf_modern_cfg_init(dh_dev); + if (ret != 0) + { + LOG_ERR("zxdh_pf_modern_cfg_init failed: %d\n", ret); + goto err_cfg_init; + } + + ret = zxdh_send_pxe_status_to_riscv(dh_dev); + if (ret != 0) + { + LOG_ERR("zxdh_send_pxe_status_to_riscv failed: %d\n", ret); + goto err_send_pxe_status; + } + +#ifdef HAVE_DEVLINK_REGISTER_GET_1_PARAMS + zxdh_devlink_register(devlink); +#else + zxdh_devlink_register(devlink, &pdev->dev); +#endif + + zxdh_pf_initialized_init(dh_dev); + + ret = zxdh_pf_dpp_init(dh_dev); + if (ret != 0) + { + LOG_ERR("zxdh_pf_dpp_init failed: %d\n", ret); + goto err_dpp_init; + } + + ret = zxdh_pf_query_fwinfo(dh_dev); + if (ret != 0) + { + LOG_ERR("zxdh_pf_query_fwinfo failed: %d\n", ret); + goto err_query_fwinfo; + } + + ret = zxdh_pf_lag_init(dh_dev, &port_num); + if (ret != 0) + { + LOG_ERR("zxdh_pf_lag_init failed: %d\n", ret); + goto err_query_fwinfo; + } + + ret = dh_pf_adevs_table_init(dh_dev, port_num); + if (ret != 0) + { + LOG_ERR("dh_pf_adevs_table_init failed: %d\n", ret); + goto err_adevs_tbl_init; + } + + for (idx = 0; idx < port_num; idx++) + { + zxdh_plug_aux_dev(dh_dev, idx); + } + +#ifdef PTP_DRIVER_INTERFACE_EN + if (dh_dev->coredev_type == DH_COREDEV_PF) + { + ret = zxdh_ptp_init(dh_dev); + if (ret != 0) + { + LOG_ERR("zxdh_ptp_init failed: %d\n", ret); + goto err_ptp_init; + } + } +#endif + + if (!zxdh_pf_is_upf(dh_dev)) + { + ret = zxdh_tsn_init(dh_dev); + if (ret != 0) + { + LOG_ERR("zxdh_tsn_init failed: %d\n", ret); + goto err_tsn_init; + } + } + +#ifdef ZXDH_SRIOV_SYSFS_EN + ret = zxdh_sriov_sysfs_init(dh_dev); + if (ret != 0) + { + LOG_ERR("zxdh_sriov_sysfs_init failed: %d, vport = %x\n", ret, pf_dev->vport); + goto err_sriov_sysfs; + } +#endif + + zxdh_pf_ip6mac_lock_init(dh_dev); + + ret = zxdh_init_ip6mac_tbl(dh_dev); + if (ret != 0) + { + LOG_ERR("zxdh_init_ip6mac_tbl failed: %d, vport = %x\n", ret, pf_dev->vport); + goto err_tsn_init; + } + + LOG_INFO("pf level driver probe completed\n"); + + return 0; + +#ifdef ZXDH_SRIOV_SYSFS_EN +err_sriov_sysfs: +#endif +err_tsn_init: + if (!zxdh_pf_is_upf(dh_dev)) + { + zxdh_tsn_exit(dh_dev); + } +err_ptp_init: + zxdh_ptp_stop(dh_dev); +err_adevs_tbl_init: + zxdh_pf_lag_exit(dh_dev); +err_query_fwinfo: + zxdh_pf_dpp_uninit(dh_dev); +err_dpp_init: + zxdh_pf_initialized_uninit(dh_dev); + zxdh_devlink_unregister(devlink); +err_send_pxe_status: + zxdh_pf_modern_cfg_uninit(dh_dev); +err_cfg_init: + dh_pf_sriov_cap_cfg_uninit(dh_dev); +err_sriov_cap_init: + dh_pf_eq_table_destroy(dh_dev); +err_eq_table_create: + dh_pf_irq_table_destroy(dh_dev); +err_irq_table_create: + dh_pf_events_uninit(dh_dev); +err_events_init: + dh_eq_table_cleanup(dh_dev); +err_eq_table_init: + dh_irq_table_cleanup(dh_dev); +err_vf_item: + dh_pf_vf_item_destroy(dh_dev, true); +err_pci: + dh_pf_pci_close(dh_dev); +err_irq_table_init: + zxdh_devlink_free(devlink); + return ret; +} + +static void dh_pf_remove(struct pci_dev *pdev) +{ + struct dh_core_dev *dh_dev = pci_get_drvdata(pdev); + struct devlink *devlink = priv_to_devlink(dh_dev); + + LOG_INFO("pf level driver remove start\n"); + zxdh_cleanup_ip6mac_tbl(dh_dev); +#ifdef ZXDH_SRIOV_SYSFS_EN + zxdh_sriov_sysfs_exit(dh_dev); +#endif + if (!zxdh_pf_is_upf(dh_dev)) + { + zxdh_tsn_exit(dh_dev); + } +#ifdef PTP_DRIVER_INTERFACE_EN + if (dh_dev->coredev_type == DH_COREDEV_PF) + { + zxdh_ptp_stop(dh_dev); + } +#endif + zxdh_unplug_aux_dev_all(dh_dev); + dh_pf_adevs_table_destroy(dh_dev); + + zxdh_pf_lag_exit(dh_dev); + zxdh_pf_dpp_uninit(dh_dev); + zxdh_pf_initialized_uninit(dh_dev); + + zxdh_devlink_unregister(devlink); + zxdh_pf_modern_cfg_uninit(dh_dev); + dh_pf_sriov_cap_cfg_uninit(dh_dev); + dh_pf_eq_table_destroy(dh_dev); + dh_pf_irq_table_destroy(dh_dev); + dh_pf_events_uninit(dh_dev); + dh_eq_table_cleanup(dh_dev); + dh_irq_table_cleanup(dh_dev); + dh_pf_vf_item_destroy(dh_dev, true); + dh_pf_pci_close(dh_dev); + zxdh_devlink_free(devlink); + + pci_set_drvdata(pdev, NULL); + LOG_INFO("pf level driver remove completed\n"); + + return; +} + +static int32_t dh_pf_suspend(struct pci_dev *pdev, pm_message_t state) +{ + + return 0; +} + +static int32_t dh_pf_resume(struct pci_dev *pdev) +{ + + return 0; +} + +static void dh_pf_shutdown(struct pci_dev *pdev) +{ + struct dh_core_dev *dh_dev = pci_get_drvdata(pdev); + struct devlink *devlink = priv_to_devlink(dh_dev); + + LOG_INFO("pf level driver shutdown start\n"); + dh_pf_adevs_table_destroy(dh_dev); + + zxdh_pf_lag_exit(dh_dev); + zxdh_pf_dpp_uninit(dh_dev); + zxdh_pf_initialized_uninit(dh_dev); + + zxdh_devlink_unregister(devlink); + zxdh_pf_modern_cfg_uninit(dh_dev); + dh_pf_sriov_cap_cfg_uninit(dh_dev); + dh_pf_eq_table_destroy(dh_dev); + dh_pf_irq_table_destroy(dh_dev); + dh_pf_events_uninit(dh_dev); + dh_eq_table_cleanup(dh_dev); + dh_irq_table_cleanup(dh_dev); + dh_pf_vf_item_destroy(dh_dev, false); + dh_pf_pci_close(dh_dev); + zxdh_devlink_free(devlink); + + pci_set_drvdata(pdev, NULL); + LOG_INFO("pf level driver shutdown completed\n"); +} + +static pci_ers_result_t dh_pci_err_detected(struct pci_dev *pdev, + pci_channel_state_t state) +{ + return PCI_ERS_RESULT_NONE; +} + +static pci_ers_result_t dh_pf_pci_slot_reset(struct pci_dev *pdev) +{ + return PCI_ERS_RESULT_NONE; +} + +static void dh_pf_pci_resume(struct pci_dev *pdev) +{ + +} + +int32_t dh_pf_sriov_configure(struct pci_dev *pdev, int32_t num_vfs) +{ + struct dh_core_dev *dev = pci_get_drvdata(pdev); + struct zxdh_pf_device *pf_dev = dh_core_priv(dev); + int32_t ret = 0; + + if (dev->coredev_type != DH_COREDEV_PF) + { + LOG_ERR("This device is not capable of SR-IOV\n"); + return -EOPNOTSUPP; + } + + if (num_vfs > 0) + { + ret = dh_pf_sriov_enable(pdev, num_vfs); + if (ret != 0) + { + LOG_ERR("Failed to enable sriov, num_vfs:%d\n", num_vfs); + return ret; + } + } + else + { + dh_pf_sriov_disable(pdev); + } + + pf_dev->num_vfs = (uint16_t)num_vfs; + + return num_vfs; +} + +static const struct pci_error_handlers dh_pf_err_handler = { + .error_detected = dh_pci_err_detected, + .slot_reset = dh_pf_pci_slot_reset, + .resume = dh_pf_pci_resume +}; + +static struct pci_driver dh_pf_driver = { + .name = KBUILD_MODNAME, + .id_table = dh_pf_pci_table, + .probe = dh_pf_probe, + .remove = dh_pf_remove, + .suspend = dh_pf_suspend, + .resume = dh_pf_resume, + .shutdown = dh_pf_shutdown, + .err_handler = &dh_pf_err_handler, + .sriov_configure = dh_pf_sriov_configure, +}; + +static int32_t __init dh_pf_pci_init_module(void) +{ + int32_t ret = 0; + + LOG_INFO("%s - version %s\n", zxdh_pf_driver_string, zxdh_pf_driver_version); + LOG_INFO("%s\n", zxdh_pf_copyright); + + ret = pci_register_driver(&dh_pf_driver); + if (ret != 0) + { + LOG_ERR("pci_register_driver failed: %d\n", ret); + goto err_register_driver; + } + +#ifdef CONFIG_ZXDH_SF + ret = zxdh_en_sf_driver_register(); + if (ret != 0) + { + LOG_ERR("zxdh_en_sf_driver_register failed: %d\n", ret); + goto err_sf_driver_register; + } +#endif + + ret = dh_pf_msg_recv_func_register(); + if (ret != 0) + { + LOG_ERR("dh_pf_msg_recv_func_register failed: %d\n", ret); + goto err_msg_recv_func_registe; + } + + return 0; + +err_msg_recv_func_registe: +#ifdef CONFIG_ZXDH_SF + zxdh_en_sf_driver_unregister(); +err_sf_driver_register: +#endif + pci_unregister_driver(&dh_pf_driver); +err_register_driver: + return ret; +} + +static void dh_pf_pci_exit_module(void) +{ + LOG_INFO("%s - version %s\n", zxdh_pf_driver_string, zxdh_pf_driver_version); + LOG_INFO("%s\n", zxdh_pf_copyright); + + dh_pf_msg_recv_func_unregister(); + +#ifdef CONFIG_ZXDH_SF + zxdh_en_sf_driver_unregister(); +#endif + + pci_unregister_driver(&dh_pf_driver); + + return; +} + +module_init(dh_pf_pci_init_module); +module_exit(dh_pf_pci_exit_module); diff --git a/src/net/drivers/net/ethernet/dinghai/en_pf.h b/src/net/drivers/net/ethernet/dinghai/en_pf.h new file mode 100644 index 0000000..21d10d7 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_pf.h @@ -0,0 +1,179 @@ +#ifndef __ZXDH_EN_PF_H__ +#define __ZXDH_EN_PF_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include "plcr.h" +#include "en_tsn/zxdh_tsn.h" + +/* Common configuration */ +#define ZXDH_PCI_CAP_COMMON_CFG 1 +/* Notifications */ +#define ZXDH_PCI_CAP_NOTIFY_CFG 2 +/* ISR access */ +#define ZXDH_PCI_CAP_ISR_CFG 3 +/* Device specific configuration */ +#define ZXDH_PCI_CAP_DEVICE_CFG 4 +/* PCI configuration access */ +#define ZXDH_PCI_CAP_PCI_CFG 5 + +#define ZXDH_PF_MAX_BAR_VAL 0x5 +#define ZXDH_PF_ALIGN4 4 +#define ZXDH_PF_ALIGN2 2 +#define ZXDH_PF_MAP_MINLEN2 2 + +#define ZXDH_DEV_MAC_LOW_OFFSET 0x40 +#define ZXDH_DEV_MAC_HIGH_OFFSET 0x44 +#define ZXDH_DEV_SPEED_OFFSET 0x4c +#define ZXDH_DEV_DUPLEX_OFFSET 0x50 + +#define ZXDH_CFG_NPSDK_TYPE 7 +#define ZXDH_STOP_PXE_MODE 1 + +#define ZXDH_PANNEL_PORT_MAX (10) + +#define GET_COREDEV_TYPE(pdev) \ + ((pdev->device == ZXDH_VF_DEVICE_ID) || (pdev->device == ZXDH_VF_E310_DEVICE_ID) || \ + (pdev->device == ZXDH_VF_E312_DEVICE_ID) || (pdev->device == ZXDH_UPF_VF_I512_DEVICE_ID) || \ + (pdev->device == ZXDH_INICA_RDMA_VF_DEVICE_ID) || \ + (pdev->device == ZXDH_VF_DPUB_RDMA_DEVICE_ID)) ? \ + DH_COREDEV_VF : DH_COREDEV_PF \ + +#define ZXDH_AUX_COMP_FLAG 1 +#define ZXDH_AUX_COMP_FLAG_CHECK(pf_dev) \ + do { \ + if (pf_dev->aux_comp_flag != ZXDH_AUX_COMP_FLAG) \ + { \ + return; \ + } \ + } while (0) + +#define PORT_FLAGS_ALLOC_STAT (1 << 0) + + +struct dh_core_dev; + +struct zxdh_pf_adev { + struct zxdh_auxiliary_device *adev; + int32_t aux_idx; +}; + +struct zxdh_pannle_port +{ + uint8_t pannel_id; + uint8_t phyport; + uint8_t link_check_bit; + uint8_t flags; +} __attribute__((packed)); + +struct zxdh_port_resource +{ + uint8_t pannel_num; + uint8_t rsv[3]; + struct zxdh_pannle_port port[ZXDH_PANNEL_PORT_MAX]; +} __attribute__((packed)); + +struct zxdh_pf_device { + struct list_head virtqueues; + + struct zxdh_pf_pci_common_cfg __iomem *common; + /* Device-specific data (non-legacy mode) */ + /* Base of vq notifications (non-legacy mode). */ + void __iomem *device; + void __iomem *notify_base; + void __iomem *pf_sriov_cap_base; + /* Physical base of vq notifications */ + resource_size_t notify_pa; + /* Where to read and clear interrupt */ + uint8_t __iomem *isr; + /* So we can sanity-check accesses. */ + size_t notify_len; + size_t device_len; + /* Capability for when we need to map notifications per-vq. */ + int32_t notify_map_cap; + /* Multiply queue_notify_off by this value. (non-legacy mode). */ + uint32_t notify_offset_multiplier; + int32_t modern_bars; + + uint64_t pci_ioremap_addr[6]; + + uint32_t speed; + uint32_t autoneg_enable; + uint32_t supported_speed_modes; + uint32_t advertising_speed_modes; + uint8_t duplex; + + uint16_t pcie_id; + uint16_t slot_id; + uint16_t vport; + struct zxdh_vf_item *vf_item; + uint16_t num_vfs; + bool vepa; + uint8_t phy_port; + + bool link_up; + struct work_struct riscv_ready_work; + struct work_struct riscv2pf_msg_proc_work; + struct work_struct vf2pf_msg_proc_work; + struct work_struct link_info_irq_update_vf_bond_pf_work; + struct work_struct riscv_ext_pps_work; + struct work_struct riscv_local_pps_work; + + uint64_t sriov_bar_size; + + struct zxdh_plcr_table plcr_table; + struct zxdh_sriov_sysfs sriov; + struct zxdh_pf_adev *adevs_table; + int32_t adevs_num; + + struct zxdh_port_resource port_resource; + struct zxdh_lag *ldev; + int32_t pannel_port_num; + + uint32_t initialized_flags; + spinlock_t initialized_lock; + + /* initialization completion flag */ + uint8_t aux_comp_flag; + uint8_t bond_num; + struct zxdh_ptp_private *ptp; + struct zxdh_tsn_private *tsn; + struct zxdh_ipv6_mac_tbl *ip6mac_tbl; + spinlock_t vf_ip6mac_lock; +}; + +struct zxdh_ipv6_mac_entry { + spinlock_t lock; + refcount_t refcnt; + struct list_head list; + uint8_t ipv6_mac[ETH_ALEN]; +}; + +struct zxdh_ipv6_mac_tbl { + unsigned int ip6mact_size; + rwlock_t lock; + struct list_head ip6mac_free_head; + void *ip6mac_entry_list; + struct list_head hash_list[]; +}; + +#define IS_MSGQ_DEV(en_dev) if ((en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) && \ + ((!en_dev->ops->is_bond(en_dev->parent)) || \ + (en_dev->ops->is_bond(en_dev->parent) && en_dev->ops->if_init(en_dev->parent)))) +#define NEED_MSGQ(en_dev) if (en_dev->need_msgq) + +bool zxdh_pf_is_bond(struct dh_core_dev *dh_dev); +bool zxdh_pf_is_upf(struct dh_core_dev *dh_dev); +int32_t zxdh_pf_msg_send_cmd(struct dh_core_dev *dh_dev, uint16_t module_id, void *msg, void *ack, bool is_sync); +struct zxdh_vf_item *zxdh_pf_get_vf_item(struct dh_core_dev *dh_dev, uint16_t vf_idx); +int zxdh_pf_get_pannel_port_num(struct dh_core_dev *dh_dev); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/en_pf/devlink.c b/src/net/drivers/net/ethernet/dinghai/en_pf/devlink.c new file mode 100755 index 0000000..4875424 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_pf/devlink.c @@ -0,0 +1,132 @@ +#include +#include +#include "devlink.h" + + +struct devlink_ops dh_pf_devlink_ops = { + +}; + +enum { + DH_PF_PARAMS_MAX, +}; + +static int32_t __attribute__((unused)) sample_check(struct dh_core_dev *dev) +{ + return 1; +} + +enum dh_pf_devlink_param_id { + DH_PF_DEVLINK_PARAM_ID_BASE = DEVLINK_PARAM_GENERIC_ID_MAX, + DH_PF_DEVLINK_PARAM_ID_SAMPLE, +}; + + +static int32_t dh_devlink_sample_set(struct devlink *devlink, uint32_t id, + struct devlink_param_gset_ctx *ctx) +{ + struct dh_core_dev * __attribute__((unused)) dev = devlink_priv(devlink); + + return 0; +} + +static int32_t dh_devlink_sample_get(struct devlink *devlink, uint32_t id, + struct devlink_param_gset_ctx *ctx) +{ + struct dh_core_dev * __attribute__((unused)) dev = devlink_priv(devlink); + + return 0; +} + +#ifdef HAVE_DEVLINK_PARAM_REGISTER +static const struct devlink_params { + const char *name; + int32_t (*check)(struct dh_core_dev *dev); + struct devlink_param param; +} devlink_params[] = { + [DH_PF_PARAMS_MAX] = { .name = "sample", + .check = &sample_check, + .param = DEVLINK_PARAM_DRIVER(DH_PF_DEVLINK_PARAM_ID_SAMPLE, + "sample", DEVLINK_PARAM_TYPE_BOOL, + BIT(DEVLINK_PARAM_CMODE_RUNTIME),dh_devlink_sample_get, + dh_devlink_sample_set, + NULL), + } +}; + +static int32_t params_register(struct devlink *devlink) +{ + int32_t i = 0; + int32_t err = 0; + struct dh_core_dev *dh_dev = devlink_priv(devlink); + + for (i = 0; i < ARRAY_SIZE(devlink_params); i++) + { + if(devlink_params[i].check(dh_dev)) + { + err = devlink_param_register(devlink, &devlink_params[i].param); + if (err) + { + goto rollback; + } + } + } + + return 0; + +rollback: + if (i == 0) + { + return err; + } + + for (; i > 0; i--) + { + devlink_param_unregister(devlink, &devlink_params[i].param); + } + + return err; +} + +static int32_t params_unregister(struct devlink *devlink) +{ + int32_t i = 0; + + for (i = 0; i < ARRAY_SIZE(devlink_params); i++) + { + devlink_param_unregister(devlink, &devlink_params[i].param); + } + + return 0; +} +#else +static struct devlink_param devlink_params [] = { + [DH_PF_PARAMS_MAX] = DEVLINK_PARAM_DRIVER(DH_PF_DEVLINK_PARAM_ID_SAMPLE, + "sample", DEVLINK_PARAM_TYPE_BOOL, + BIT(DEVLINK_PARAM_CMODE_RUNTIME),dh_devlink_sample_get, + dh_devlink_sample_set, + NULL), +}; + +static int32_t params_register(struct devlink *devlink) +{ + struct dh_core_dev * __attribute__((unused)) dh_dev = devlink_priv(devlink); + int32_t err = 0; + + err = devlink_params_register(devlink, devlink_params, ARRAY_SIZE(devlink_params)); + + return err; +} +static int32_t params_unregister(struct devlink *devlink) +{ + devlink_params_unregister(devlink, devlink_params, ARRAY_SIZE(devlink_params)); + + return 0; +} +#endif + +struct dh_core_devlink_ops dh_pf_core_devlink_ops = { + .params_register = params_register, + .params_unregister = params_unregister +}; + diff --git a/src/net/drivers/net/ethernet/dinghai/en_pf/devlink.h b/src/net/drivers/net/ethernet/dinghai/en_pf/devlink.h new file mode 100755 index 0000000..116d09d --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_pf/devlink.h @@ -0,0 +1,16 @@ +#ifndef __ZXDH_DEVLINK_H__ +#define __ZXDH_DEVLINK_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + + + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_pf/en_rep.c b/src/net/drivers/net/ethernet/dinghai/en_pf/en_rep.c new file mode 100755 index 0000000..e69de29 diff --git a/src/net/drivers/net/ethernet/dinghai/en_pf/eq.c b/src/net/drivers/net/ethernet/dinghai/en_pf/eq.c new file mode 100755 index 0000000..ae2e6d1 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_pf/eq.c @@ -0,0 +1,455 @@ +#include +#include +#include +#include +#include +#include "irq.h" +#include "eq.h" +#include "../en_pf.h" + +extern irqreturn_t msix_extern_pps_irq_from_risc_handler(struct zxdh_pf_device *dev); +extern irqreturn_t msix_local_pps_irq_from_risc_handler(struct zxdh_pf_device *dev); +static int32_t create_async_eqs(struct dh_core_dev *dev); + + +int32_t dh_pf_eq_table_init(struct dh_core_dev *dev) +{ + struct dh_pf_eq_table *table_priv = NULL; + + table_priv = kvzalloc(sizeof(*table_priv), GFP_KERNEL); + if (unlikely(table_priv == NULL)) + { + LOG_ERR("dh_pf_eq_table kvzalloc failed\n"); + return -ENOMEM; + } + + dh_eq_table_init(dev, table_priv); + + return 0; +} + +uint16_t zxdh_pf_get_vqs_channels_num(struct dh_core_dev *dh_dev) +{ + if ((dh_dev->pdev->device == ZXDH_INICA_BOND_DEVICE_ID) + || (dh_dev->pdev->device == ZXDH_INICB_BOND_DEVICE_ID) + || (dh_dev->pdev->device == ZXDH_INICA_UPF_BOND_DEVICE_ID) + || (dh_dev->pdev->device == ZXDH_DPUA_BOND_DEVICE_ID)) + { + return ZXDH_BOND_VQS_CHANNELS_NUM; + } + + return ZXDH_VQS_CHANNELS_NUM; +} + +void zxdh_pf_switch_irq(struct dh_core_dev *dh_dev, int32_t i, int32_t op) +{ + if (op) + { + enable_irq(i); + return; + } + + disable_irq(i); + return; +} + +int32_t zxdh_pf_vq_irqs_request(struct dh_core_dev *dh_dev, struct dh_irq **vq_irqs, int32_t vq_channels) +{ + struct dh_irq_table *irq_table = &dh_dev->irq_table; + struct dh_pf_irq_table *pf_irq_table = irq_table->priv; + int32_t ret = 0; + int32_t vqs_irq_num = vq_channels; + + ret = dh_irq_affinity_irqs_request_auto(pf_irq_table->pf_vq_pool, vq_irqs, vqs_irq_num); + if (ret < vqs_irq_num) + { + LOG_ERR("the actual obtain irq_num %d < need request irq_num %d\n", ret, vqs_irq_num); + return -1; + } + + return ret; +} + +void zxdh_pf_affinity_irqs_release(struct dh_core_dev *dh_dev, struct dh_irq **vq_irqs, int32_t num_irqs) +{ + struct dh_irq_table *irq_table = &dh_dev->irq_table; + struct dh_pf_irq_table *pf_irq_table = irq_table->priv; + + dh_irq_affinity_irqs_release(pf_irq_table->pf_vq_pool, vq_irqs, num_irqs); +} + +static int32_t destroy_async_eq(struct dh_core_dev *dev) +{ + struct dh_eq_table *eq_table = &dev->eq_table; + struct zxdh_pf_device *pf_dev = dh_core_priv(dev); + struct msix_para in = {0}; + int32_t err = 0; + + in.vector_risc = ZXDH_PF_INVALID_MSIX_VEC; + in.vector_pfvf = ZXDH_PF_INVALID_MSIX_VEC; + in.vector_mpf = ZXDH_PF_INVALID_MSIX_VEC; + in.driver_type = MSG_CHAN_END_PF; + in.pdev = dev->pdev; + in.virt_addr = pf_dev->pci_ioremap_addr[0] + ZXDH_BAR_MSG_OFFSET; + in.pcie_id = pf_dev->pcie_id; + + mutex_lock(&eq_table->lock); + + err = zxdh_bar_enable_chan(&in, &pf_dev->vport); + if (err != 0) + { + LOG_ERR("zxdh_bar_disable_chan failed\n"); + } + + mutex_unlock(&eq_table->lock); + + return err; +} + +int32_t dh_pf_eq_table_create(struct dh_core_dev *dev) +{ + int32_t err = 0; + + err = create_async_eqs(dev); + if (err != 0) + { + LOG_ERR("Failed to create async EQs: %d\n", err); + return err; + } + + return 0; +} + +/*create eventq*/ +static int32_t create_async_eq(struct dh_core_dev *dev, struct dh_irq *riscv, struct dh_irq *pf) +{ + struct dh_eq_table *eq_table = &dev->eq_table; + struct zxdh_pf_device *pf_dev = dh_core_priv(dev); + struct msix_para in = {0}; + int ret = 0; + + in.vector_risc = riscv->index; + in.vector_pfvf = pf->index; + in.vector_mpf = ZXDH_PF_INVALID_MSIX_VEC; + in.driver_type = MSG_CHAN_END_PF; + in.pdev = dev->pdev; + in.virt_addr = pf_dev->pci_ioremap_addr[0] + ZXDH_BAR_MSG_OFFSET; + in.pcie_id = pf_dev->pcie_id; + + mutex_lock(&eq_table->lock); + + LOG_DEBUG("msix vector riscv: %d, pfvf: %d\n", riscv->index, pf->index); + ret = zxdh_bar_enable_chan(&in, &pf_dev->vport); + + mutex_unlock(&eq_table->lock); + + return ret; +} + +static int32_t dh_eq_async_riscv_int(struct notifier_block *nb, unsigned long action, void *data) +{ + struct dh_eq_async *eq_riscv_async = container_of(nb, struct dh_eq_async, irq_nb); + struct dh_core_dev *dev = (struct dh_core_dev *)eq_riscv_async->priv; + struct zxdh_pf_device *pf_dev = dh_core_priv(dev); + struct dh_eq_table *eq_table = &dev->eq_table; + struct dh_events *events = dev->events; + struct dh_event_nb *event_nb = NULL; + uint64_t virt_addr = 0; + int32_t event_type = 0; + uint16_t event_idx = 0; + uint16_t i = 0; + uint8_t src = MSG_CHAN_END_RISC; + uint8_t dst = MSG_CHAN_END_VF; + + if(dev->coredev_type == DH_COREDEV_PF) + { + dst = MSG_CHAN_END_PF; + } + + virt_addr = pf_dev->pci_ioremap_addr[0] + ZXDH_BAR_MSG_OFFSET; + event_idx = zxdh_get_event_id(virt_addr, src, dst); + event_type = dh_eq_event_type_get(event_idx); + LOG_INFO("------------- event_idx: %d, event_type: %d------------\n", event_idx, event_type); + + if(events == NULL) + { + LOG_ERR("riscv_irq trigger, events is null\n"); + return 0; + } + + for (i = 0; i < events->evt_num; i++) + { + event_nb = &events->notifiers[i]; + if (event_type == event_nb->nb.event_type) + { + LOG_INFO("en_pf async riscv irq_handler called\n"); + atomic_notifier_call_chain(&eq_table->nh[event_type], event_type, NULL); + return 0; + } + } + + return 0; +} + +static int32_t dh_eq_async_pf_int(struct notifier_block *nb, unsigned long action, void *data) +{ + struct dh_eq_async *eq_riscv_async = container_of(nb, struct dh_eq_async, irq_nb); + struct dh_core_dev *dev = (struct dh_core_dev *)eq_riscv_async->priv; + struct zxdh_pf_device *pf_dev = dh_core_priv(dev); + struct dh_eq_table *eq_table = &dev->eq_table; + struct dh_events *events = dev->events; + struct dh_event_nb *event_nb = NULL; + uint64_t virt_addr = 0; + int32_t event_type = 0; + uint16_t event_idx = 0; + uint16_t i = 0; + + if(dev->coredev_type == DH_COREDEV_VF) + { + return 0; + } + + virt_addr = pf_dev->pci_ioremap_addr[0] + ZXDH_BAR_MSG_OFFSET + ZXDH_BAR_PFVF_MSG_OFFSET; + event_idx = zxdh_get_event_id(virt_addr, MSG_CHAN_END_VF, MSG_CHAN_END_PF); + event_type = dh_eq_event_type_get(event_idx); + LOG_INFO("------------- event_idx: %d, event_type: %d------------\n", event_idx, event_type); + + for (i = 0; i < events->evt_num; i++) + { + event_nb = &events->notifiers[i]; + + if (event_type == event_nb->nb.event_type) + { + LOG_INFO("en_pf async pf/vf irq_handler called\n"); + atomic_notifier_call_chain(&eq_table->nh[event_type], event_type, NULL); + return 0; + } + } + + return 0; +} + +static int32_t dh_eq_async_link_info_int_bond_pf(struct notifier_block *nb, unsigned long action, void *data) +{ + struct dh_eq_async *eq_riscv_async = container_of(nb, struct dh_eq_async, irq_nb); + struct dh_core_dev *dev = (struct dh_core_dev *)eq_riscv_async->priv; + struct zxdh_pf_device *pf_dev = dh_core_priv(dev); + + if(!zxdh_pf_is_bond(dev)) + { + LOG_INFO("isn't bond_pf exit\n"); + return 0; + } + + zxdh_events_work_enqueue(dev, &pf_dev->link_info_irq_update_vf_bond_pf_work); + return 0; +} + +static int32_t dh_eq_async_extpps_int(struct notifier_block *nb, unsigned long action, void *data) +{ + struct dh_eq_async *eq_pps_async = container_of(nb, struct dh_eq_async, irq_nb); + struct dh_core_dev *dev = (struct dh_core_dev *)eq_pps_async->priv; + struct dh_eq_table *eq_table = &dev->eq_table; + + atomic_notifier_call_chain(&eq_table->nh[DH_EVENT_TYPE_NOTIFY_RISC_EXT_PPS], DH_EVENT_TYPE_NOTIFY_RISC_EXT_PPS, NULL); + return 0; +} + +static int32_t dh_eq_async_local_pps_int(struct notifier_block *nb, unsigned long action, void *data) +{ + struct dh_eq_async *eq_pps_async = container_of(nb, struct dh_eq_async, irq_nb); + struct dh_core_dev *dev = (struct dh_core_dev *)eq_pps_async->priv; + struct dh_eq_table *eq_table = &dev->eq_table; + + atomic_notifier_call_chain(&eq_table->nh[DH_EVENT_TYPE_NOTIFY_RISC_LOCAL_PPS], DH_EVENT_TYPE_NOTIFY_RISC_LOCAL_PPS, NULL); + return 0; +} + +static struct dh_pf_async_irq_table dh_pf_async_irq_tbl[] = +{ + {"link_info", dh_eq_async_link_info_int_bond_pf}, + {"riscv", dh_eq_async_riscv_int}, + {"pf", dh_eq_async_pf_int}, + {"expps", dh_eq_async_extpps_int}, + {"localpps", dh_eq_async_local_pps_int}, +}; + +static void cleanup_async_eq(struct dh_core_dev *dev, struct dh_eq_async *eq, const char *name) +{ + dh_eq_disable(dev, &eq->core, &eq->irq_nb); +} + +static void destroy_async_eqs(struct dh_core_dev *dev) +{ + struct dh_eq_table *table = &dev->eq_table; + struct dh_pf_eq_table *table_priv = table->priv; + int32_t tbl_size = ARRAY_SIZE(dh_pf_async_irq_tbl); + int32_t i = 0; + + for (i = 0; i < tbl_size; ++i) + { + cleanup_async_eq(dev, &table_priv->async_eq_tbl[i], dh_pf_async_irq_tbl[i].name); + } + destroy_async_eq(dev); + dh_irqs_release_vectors(table_priv->async_irq_tbl, tbl_size); +} + +void dh_pf_eq_table_destroy(struct dh_core_dev *dev) +{ + destroy_async_eqs(dev); +} + +static int32_t create_async_eqs(struct dh_core_dev *dev) +{ + struct dh_eq_table *table = &dev->eq_table; + struct dh_pf_eq_table *table_priv = table->priv; + struct dh_eq_param param = {}; + int32_t err = 0; + int32_t tbl_size = ARRAY_SIZE(dh_pf_async_irq_tbl); + int32_t i = 0; + int32_t j = 0; + int32_t k = 0; + + for (i = 0; i < tbl_size ; ++i) + { + table_priv->async_irq_tbl[i] = dh_pf_async_irq_request(dev); + if (IS_ERR(table_priv->async_irq_tbl[i])) + { + err = PTR_ERR(table_priv->async_irq_tbl[i]); + LOG_ERR("Failed to get async_irq_tbl[%d]\n", i); + goto err_async_irq_request; + } + } + + err = create_async_eq(dev, table_priv->async_irq_tbl[1], table_priv->async_irq_tbl[2]); + if (err != 0) + { + LOG_ERR("Failed to create async_eq\n"); + goto err_async_irq_request; + } + + param.nent = 10; + param.event_type = DH_EVENT_QUEUE_TYPE_RISCV; + for (j = 0; j < tbl_size; ++j) + { + param.irq = table_priv->async_irq_tbl[j], + err = setup_async_eq(dev, &table_priv->async_eq_tbl[j], ¶m,\ + dh_pf_async_irq_tbl[j].async_int, dh_pf_async_irq_tbl[j].name,\ + dev); + if (err != 0) + { + LOG_ERR("Failed to setup async_eq_tbl[%d]\n", j); + goto err_setup_async_eq; + } + } + + return 0; + +err_setup_async_eq: + for (k = 0; k < j; ++k) + { + cleanup_async_eq(dev, &table_priv->async_eq_tbl[j], dh_pf_async_irq_tbl[j].name); + } + destroy_async_eq(dev); +err_async_irq_request: + dh_irqs_release_vectors(table_priv->async_irq_tbl, i); + return err; +} + +int32_t zxdh_pf_async_eq_enable(struct dh_core_dev *dh_dev, \ + struct dh_eq_async *eq, const char *name, bool attach) +{ + struct dh_eq_table *table = &dh_dev->eq_table; + struct dh_pf_eq_table *table_priv = table->priv; + int32_t err = 0; + int32_t tbl_size = ARRAY_SIZE(dh_pf_async_irq_tbl); + int32_t i = 0; + + for (i = 0; i < tbl_size; ++i) + { + if(strcmp(dh_pf_async_irq_tbl[i].name, name) == 0) + { + eq->core.irq = table_priv->async_irq_tbl[i]; + break; + } + } + + if (i == tbl_size) + { + LOG_ERR("failed to find %s irq\n", name); + return -1; + } + + LOG_DEBUG("%s attach[%d] irq[%d]\n", name, attach, eq->core.irq->index); + if (attach) + { + err = dh_eq_enable(dh_dev, &eq->core, &eq->irq_nb); + if (err != 0) + { + LOG_WARN("failed to enable EQ %d\n", err); + } + } + else + { + dh_eq_disable(dh_dev, &eq->core, &eq->irq_nb); + } + + return err; +} + +void zxdh_pf_get_link_info_from_vqm(struct dh_core_dev *dh_dev, uint8_t *link_up) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + uint32_t dev_link_up = 0; + + dev_link_up = ioread32((void __iomem *)(pf_dev->pci_ioremap_addr[0] + ZXDH_DEV_MAC_HIGH_OFFSET)); + *link_up = (dev_link_up >> 16) & 0xff; + + LOG_INFO("dev pcieid:0x%x ******** link_up: %d ********\n", pf_dev->pcie_id, *link_up); + return; +} + +void zxdh_pf_set_vf_link_info(struct dh_core_dev *dh_dev, uint16_t vf_idx, uint8_t link_up) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + uint32_t dev_link_up = 0; + + dev_link_up = ioread32((void __iomem *)(pf_dev->pf_sriov_cap_base + (pf_dev->sriov_bar_size) * vf_idx + ZXDH_DEV_MAC_HIGH_OFFSET)); + dev_link_up = (dev_link_up & ~(0xFF << 16)) | ((uint32_t)(link_up) << 16); + iowrite32(dev_link_up, (void __iomem *)(pf_dev->pf_sriov_cap_base + (pf_dev->sriov_bar_size) * vf_idx + ZXDH_DEV_MAC_HIGH_OFFSET)); + + return; +} + +void zxdh_pf_set_pf_phy_port(struct dh_core_dev *dh_dev, uint8_t phy_port) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + pf_dev->phy_port = phy_port; + if (dh_dev->coredev_type == DH_COREDEV_PF) + { + if (pf_dev->tsn == NULL) + { + LOG_ERR("pf_dev->tsn is null\n"); + return; + } + pf_dev->tsn->phy_port_id = phy_port; + } +} + +uint8_t zxdh_pf_get_pf_phy_port(struct dh_core_dev *dh_dev) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + return pf_dev->phy_port; +} + +void zxdh_pf_set_pf_link_up(struct dh_core_dev *dh_dev, bool link_up) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + pf_dev->link_up = link_up; +} + +bool zxdh_pf_get_pf_link_up(struct dh_core_dev *dh_dev) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + return pf_dev->link_up; +} diff --git a/src/net/drivers/net/ethernet/dinghai/en_pf/eq.h b/src/net/drivers/net/ethernet/dinghai/en_pf/eq.h new file mode 100755 index 0000000..5c53635 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_pf/eq.h @@ -0,0 +1,53 @@ +#ifndef __ZXDH_PF_EQ_H__ +#define __ZXDH_PF_EQ_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include +#include + +#define ZXDH_PF_INVALID_MSIX_VEC 0xffff + +int32_t dh_pf_eq_table_create(struct dh_core_dev *dev); +void dh_pf_eq_table_destroy(struct dh_core_dev *dev); +int32_t dh_pf_eq_table_init(struct dh_core_dev *dev); +uint16_t zxdh_pf_get_vqs_channels_num(struct dh_core_dev *dh_dev); + +void zxdh_pf_switch_irq(struct dh_core_dev *dh_dev, int32_t i, int32_t op); +int32_t zxdh_pf_vq_irqs_request(struct dh_core_dev *dh_dev, struct dh_irq **vq_irqs, int32_t vq_channels); +void zxdh_pf_affinity_irqs_release(struct dh_core_dev *dh_dev, struct dh_irq **vq_irqs, int32_t num_irqs); +void zxdh_enable_irq(struct dh_core_dev *dh_dev, int32_t irq_index); + +int32_t zxdh_pf_async_eq_enable(struct dh_core_dev *dev, struct dh_eq_async *eq, const char *name, bool attach); +void zxdh_pf_set_pf_link_up(struct dh_core_dev *dh_dev, bool link_up); +bool zxdh_pf_get_pf_link_up(struct dh_core_dev *dh_dev); +void zxdh_pf_set_vf_link_info(struct dh_core_dev *dh_dev, uint16_t vf_idx, uint8_t link_up); +void zxdh_pf_get_link_info_from_vqm(struct dh_core_dev *dh_dev, uint8_t *link_up); +void zxdh_pf_set_pf_phy_port(struct dh_core_dev *dh_dev, uint8_t phy_port); +uint8_t zxdh_pf_get_pf_phy_port(struct dh_core_dev *dh_dev); + +#define ZXDH_PF_ASYNC_IRQ_NUM 5 +struct dh_pf_eq_table { + struct dh_irq **vq_irqs; + int32_t vq_irq_num; + struct list_head vqs_eqs_list; + struct dh_irq *async_irq_tbl[ZXDH_PF_ASYNC_IRQ_NUM]; + struct dh_eq_async async_eq_tbl[ZXDH_PF_ASYNC_IRQ_NUM]; +}; + +struct dh_pf_async_irq_table +{ + char name[64]; + notifier_fn_t async_int; +}; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/en_pf/events.c b/src/net/drivers/net/ethernet/dinghai/en_pf/events.c new file mode 100644 index 0000000..319132d --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_pf/events.c @@ -0,0 +1,318 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include "events.h" +#include "../en_pf.h" +#include "../msg_common.h" +#include "eq.h" + +static int32_t riscv2pf_notifier(struct notifier_block *, unsigned long, void *); +static int32_t riscv_ready_notifier(struct notifier_block *, unsigned long, void *); +static int32_t vf2pf_notifier(struct notifier_block *, unsigned long, void *); +static int32_t riscv_ext_pps_notifier(struct notifier_block *, unsigned long, void *); +static int32_t riscv_local_pps_notifier(struct notifier_block *nb, unsigned long type, void *data); + +extern irqreturn_t msix_extern_pps_irq_from_risc_handler(struct zxdh_pf_device *dev); +extern irqreturn_t msix_local_pps_irq_from_risc_handler(struct zxdh_pf_device *dev); + +static struct dh_nb pf_events[] = { + {.nb.notifier_call = riscv_ready_notifier, .event_type = DH_EVENT_TYPE_RISCV_READY}, + {.nb.notifier_call = vf2pf_notifier, .event_type = DH_EVENT_TYPE_NOTIFY_VF_TO_PF}, + {.nb.notifier_call = riscv_ext_pps_notifier, .event_type = DH_EVENT_TYPE_NOTIFY_RISC_EXT_PPS}, + {.nb.notifier_call = riscv_local_pps_notifier, .event_type = DH_EVENT_TYPE_NOTIFY_RISC_LOCAL_PPS}, + {.nb.notifier_call = riscv2pf_notifier, .event_type = DH_EVENT_TYPE_NOTIFY_ANY}, +}; + +static int32_t riscv2pf_notifier(struct notifier_block *nb, unsigned long type, void *data) +{ + struct dh_event_nb *event_nb = dh_nb_cof(nb, struct dh_event_nb, nb); + struct dh_core_dev *dh_dev = (struct dh_core_dev *)event_nb->ctx; + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + + zxdh_events_work_enqueue(dh_dev, &pf_dev->riscv2pf_msg_proc_work); + + return NOTIFY_OK; +} + +static int32_t riscv_ready_notifier(struct notifier_block *nb, unsigned long type, void *data) +{ + struct dh_event_nb *event_nb = dh_nb_cof(nb, struct dh_event_nb, nb); + struct dh_core_dev *dh_dev = (struct dh_core_dev *)event_nb->ctx; + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + + uint64_t virt_addr = pf_dev->pci_ioremap_addr[0] + ZXDH_BAR_MSG_OFFSET; + zxdh_bar_reset_valid(virt_addr); + zxdh_events_work_enqueue(dh_dev, &pf_dev->riscv_ready_work); + + return NOTIFY_OK; +} + +static int32_t vf2pf_notifier(struct notifier_block *nb, unsigned long type, void *data) +{ + struct dh_event_nb *event_nb = dh_nb_cof(nb, struct dh_event_nb, nb); + struct dh_core_dev *dh_dev = (struct dh_core_dev *)event_nb->ctx; + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + LOG_INFO("is called\n"); + + zxdh_events_work_enqueue(dh_dev, &pf_dev->vf2pf_msg_proc_work); + + return NOTIFY_OK; +} + +static int32_t riscv_ext_pps_notifier(struct notifier_block *nb, unsigned long type, void *data) +{ + struct dh_event_nb *event_nb = dh_nb_cof(nb, struct dh_event_nb, nb); + struct dh_core_dev *dh_dev = (struct dh_core_dev *)event_nb->ctx; + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + LOG_INFO("is called\n"); + + zxdh_events_work_enqueue(dh_dev, &pf_dev->riscv_ext_pps_work); + + return NOTIFY_OK; +} + +static int32_t riscv_local_pps_notifier(struct notifier_block *nb, unsigned long type, void *data) +{ + struct dh_event_nb *event_nb = dh_nb_cof(nb, struct dh_event_nb, nb); + struct dh_core_dev *dh_dev = (struct dh_core_dev *)event_nb->ctx; + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + LOG_INFO("is called\n"); + + zxdh_events_work_enqueue(dh_dev, &pf_dev->riscv_local_pps_work); + + return NOTIFY_OK; +} + +extern int32_t zxdh_plug_aux_dev(struct dh_core_dev *dh_dev); + +static void riscv2pf_msg_proc_work_handler(struct work_struct *_work) +{ + struct zxdh_pf_device *pf_dev = container_of(_work, struct zxdh_pf_device, riscv2pf_msg_proc_work); + + uint16_t src = MSG_CHAN_END_RISC; + uint16_t dst = MSG_CHAN_END_PF; + uint64_t virt_addr = pf_dev->pci_ioremap_addr[0] + ZXDH_BAR_MSG_OFFSET; + + ZXDH_AUX_COMP_FLAG_CHECK(pf_dev); + + zxdh_bar_irq_recv(src, dst, virt_addr, NULL); +} + +static void vf2pf_msg_proc_work_handler(struct work_struct *_work) +{ + struct zxdh_pf_device *pf_dev = container_of(_work, struct zxdh_pf_device, vf2pf_msg_proc_work); + + uint16_t src = MSG_CHAN_END_VF; + uint16_t dst = MSG_CHAN_END_PF; + uint64_t virt_addr = pf_dev->pci_ioremap_addr[0] + ZXDH_BAR_MSG_OFFSET + ZXDH_BAR_PFVF_MSG_OFFSET; + + ZXDH_AUX_COMP_FLAG_CHECK(pf_dev); + + zxdh_bar_irq_recv(src, dst, virt_addr, pf_dev); +} + +static void riscv_ready_work_handler(struct work_struct *_work) +{ + struct zxdh_pf_device *pf_dev = container_of(_work, struct zxdh_pf_device, riscv_ready_work); + struct dh_core_dev * dh_dev = container_of((void*)pf_dev, struct dh_core_dev, priv); + + ZXDH_AUX_COMP_FLAG_CHECK(pf_dev); + + zxdh_plug_aux_dev(dh_dev); +} + + +int32_t findFirstSetBit(uint8_t link_up_val) { + uint8_t i = 0; + for ( ; i < 8; i++) + { + if (link_up_val & (1 << i)) + { + return i; // 返回第一个设置位的位置 + } + } + return -1; // 没有找到 +} + +int32_t get_link_up_phyport(uint8_t link_up_val,struct zxdh_pf_device *pf_dev, uint8_t *phyport_val) +{ + int16_t first_link_up_idx = -1; + uint8_t port_num = pf_dev->port_resource.pannel_num; + struct zxdh_pannle_port *port; + int32_t idx = 0; + + first_link_up_idx = findFirstSetBit(link_up_val); + if(first_link_up_idx<0) + { + return -1; + } + //基于first_link_up_idx找到phyport值TODO:待完善 + for (idx = 0; idx < port_num; idx++) + { + port = &pf_dev->port_resource.port[idx]; + if (port->link_check_bit == first_link_up_idx) + { + *phyport_val = port->phyport; + LOG_INFO("first link_up idx %d <-> phyport 0x%x\n", first_link_up_idx, port->phyport); + return 0; + } + } + + return -1; +} + +static void link_info_irq_update_vf_bond_pf_work_handler(struct work_struct *_work) +{ + struct zxdh_pf_device *pf_dev = container_of(_work, struct zxdh_pf_device, link_info_irq_update_vf_bond_pf_work); + struct dh_core_dev * dh_dev = container_of((void*)pf_dev, struct dh_core_dev, priv); + struct zxdh_vf_item *vf_item = NULL; + int32_t err = 0; + uint16_t vf_idx = 0; + struct pci_dev *pdev = dh_dev->pdev; + uint16_t num_vfs = 0; + uint8_t link_up_val = 0; + uint8_t phyport_val = 0; + uint8_t link_info = 0; + uint16_t func_no = 0; + uint16_t pf_no = FIND_PF_ID(pf_dev->pcie_id); + union zxdh_msg msg = {0}; + + ZXDH_AUX_COMP_FLAG_CHECK(pf_dev); + + zxdh_pf_get_link_info_from_vqm(dh_dev, &link_up_val); + LOG_INFO("[pf_level] bond_pf pcie_id:0x%x read from VQM, val: 0x%x\n", pf_dev->pcie_id, link_up_val); + pf_dev->link_up = (link_up_val == 0) ? FALSE : TRUE; + + if(pf_dev->link_up) + { + if(get_link_up_phyport(link_up_val, pf_dev, &phyport_val)<0) + { + LOG_ERR("failed to get link up phyport\n"); + return; + } + link_up_val = 1; + } + + link_info = (phyport_val & 0x0F) << 4 | (link_up_val & 0x0F); + msg.payload.hdr_to_agt.op_code = AGENT_DEV_STATUS_NOTIFY; + msg.payload.hdr_to_agt.pcie_id = pf_dev->pcie_id; + num_vfs = pci_num_vf(pdev); + for (vf_idx = 0; vf_idx < num_vfs; vf_idx++) + { + vf_item = zxdh_pf_get_vf_item(dh_dev, vf_idx); + if(vf_item->link_forced == FALSE && vf_item->is_probed) + { + func_no = GET_FUNC_NO(pf_no, vf_idx); + msg.payload.pcie_msix_msg.func_no[msg.payload.pcie_msix_msg.num++] = func_no; + zxdh_pf_set_vf_link_info(dh_dev, vf_idx, link_info); + LOG_INFO("[pf_level] bond_pf pcie_id:0x%x write phyport[0x%x] and link_up[%d] to VF[%d] VQM[0x%x]\n", pf_dev->pcie_id, phyport_val, link_up_val, vf_idx, link_info); + } + } + LOG_INFO("vf num:%d\n",msg.payload.pcie_msix_msg.num); + if(msg.payload.pcie_msix_msg.num > 0) + { + err = zxdh_pf_msg_send_cmd(dh_dev, MODULE_MAC, &msg, &msg, true); + if (err != 0) + { + LOG_ERR("failed to update VF link info\n"); + } + } +} + +static void riscv_extern_pps_handler(struct work_struct *_work) +{ + struct zxdh_pf_device *pf_dev = container_of(_work, struct zxdh_pf_device, riscv_ext_pps_work); + + msix_extern_pps_irq_from_risc_handler(pf_dev); +} + +static void riscv_local_pps_handler(struct work_struct *_work) +{ + struct zxdh_pf_device *pf_dev = container_of(_work, struct zxdh_pf_device, riscv_local_pps_work); + + msix_local_pps_irq_from_risc_handler(pf_dev); +} + +int32_t dh_pf_events_init(struct dh_core_dev *dev) +{ + struct dh_events *events = NULL; + struct zxdh_pf_device *pf_dev = dh_core_priv(dev); + int32_t i = 0; + int32_t ret = 0; + uint32_t evt_num = ARRAY_SIZE(pf_events); + + if (pf_dev->bond_num != 0) + { + evt_num -= 1; + } + events = kzalloc((sizeof(*events) + evt_num * sizeof(struct dh_event_nb)), GFP_KERNEL); + if (unlikely(events == NULL)) + { + LOG_ERR("events kzalloc failed: %p\n", events); + ret = -ENOMEM; + goto err_events_kzalloc; + } + + events->evt_num = evt_num; + events->dev = dev; + dev->events = events; + events->wq = create_singlethread_workqueue("dh_pf_events"); + if (!events->wq) + { + LOG_ERR("events->wq create_singlethread_workqueue failed: %p\n", events->wq); + ret = -ENOMEM; + goto err_create_wq; + } + + INIT_WORK(&pf_dev->riscv_ready_work, riscv_ready_work_handler); + INIT_WORK(&pf_dev->riscv2pf_msg_proc_work, riscv2pf_msg_proc_work_handler); + INIT_WORK(&pf_dev->vf2pf_msg_proc_work, vf2pf_msg_proc_work_handler); + INIT_WORK(&pf_dev->link_info_irq_update_vf_bond_pf_work, link_info_irq_update_vf_bond_pf_work_handler); + INIT_WORK(&pf_dev->riscv_ext_pps_work, riscv_extern_pps_handler); + INIT_WORK(&pf_dev->riscv_local_pps_work, riscv_local_pps_handler); + + for (i = 0; i < evt_num; i++) + { + events->notifiers[i].nb = pf_events[i]; + events->notifiers[i].ctx = dev; + dh_eq_notifier_register(&dev->eq_table, &events->notifiers[i].nb); + } + + return 0; + +err_create_wq: + kfree(events); +err_events_kzalloc: + return ret; +} + +void dh_pf_events_uninit(struct dh_core_dev *dev) +{ + struct dh_events *events = dev->events; + int32_t i = 0; + + for (i = events->evt_num - 1; i >= 0 ; i--) + { + dh_eq_notifier_unregister(&dev->eq_table, &events->notifiers[i].nb); + } + + zxdh_events_cleanup(dev); + return; +} + + +void dh_pf_sriov_cap_cfg_uninit(struct dh_core_dev *dev) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dev); + if (dev->coredev_type == DH_COREDEV_PF && pf_dev->pf_sriov_cap_base != NULL) + { + iounmap((void *)pf_dev->pf_sriov_cap_base); + pf_dev->pf_sriov_cap_base = NULL; + } + return; +} \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_pf/events.h b/src/net/drivers/net/ethernet/dinghai/en_pf/events.h new file mode 100644 index 0000000..9905db9 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_pf/events.h @@ -0,0 +1,17 @@ +#ifndef __ZXDH_PF_EVENTS_H__ +#define __ZXDH_PF_EVENTS_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +int32_t dh_pf_events_init(struct dh_core_dev *dev); +void dh_pf_events_uninit(struct dh_core_dev *dev); +void dh_pf_sriov_cap_cfg_uninit(struct dh_core_dev *dev); + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/en_pf/irq.c b/src/net/drivers/net/ethernet/dinghai/en_pf/irq.c new file mode 100755 index 0000000..c6bcb9e --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_pf/irq.c @@ -0,0 +1,180 @@ +#include +#include +#include +#include "irq.h" +#include "eq.h" + +#define ZXDH_PF_ASYNC_IRQ_MIN_COMP 0 +#define ZXDH_PF_ASYNC_IRQ_MAX_COMP 19 + +#define ZXDH_PF_RDMA_IRQ_MIN 0 +#define ZXDH_PF_RDMA_IRQ_MAX 12 + +#define ZXDH_PF_COMP_IRQ_MIN_COMP 0 +#define ZXDH_PF_COMP_IRQ_MAX_COMP 1 + +#define ZXDH_PF_VQ_IRQ_MIN 0 +#define ZXDH_PF_VQ_IRQ_MAX 33 + + +struct dh_irq_range { + int32_t start; + int32_t size; +}; + +static struct dh_irq_range __attribute__((unused)) dh_get_pf_range(struct dh_core_dev *dev) +{ + struct dh_irq_range tmp = { + .start = 0, + .size = 0 + }; + + return tmp; +} + +static int32_t irq_pools_init(struct dh_core_dev *dev, int vq_n, int pf_async_vec) +{ + struct dh_irq_table *table = &dev->irq_table; + struct dh_pf_irq_table *pf_irq_table = (struct dh_pf_irq_table *)table->priv; + int32_t err = 0; + struct dh_irq_range irq_range; + + if(vq_n > 0) + { + irq_range.start = ZXDH_VQS_IRQ_START_IDX; + irq_range.size = vq_n; + + pf_irq_table->pf_vq_pool = irq_pool_alloc(dev, irq_range.start, + irq_range.size, "zxdh_pf_vq", + ZXDH_PF_VQ_IRQ_MIN, + ZXDH_PF_VQ_IRQ_MAX); + if (IS_ERR_OR_NULL(pf_irq_table->pf_vq_pool)) + { + LOG_ERR("pf_irq_table->pf_vq_pool irq_pool_alloc failed\n"); + return PTR_ERR(pf_irq_table->pf_vq_pool); + } + + pf_irq_table->pf_vq_pool->irqs_per_cpu = kcalloc(nr_cpu_ids, sizeof(u16), GFP_KERNEL); + if (unlikely(pf_irq_table->pf_vq_pool->irqs_per_cpu == NULL)) + { + LOG_ERR("pf_irq_table->pf_vq_pool->irqs_per_cpu kcalloc failed\n"); + err = -ENOMEM; + goto err_irqs_per_cpu; + } + } + + if (pf_async_vec > 0) + { + irq_range.start = 0; + irq_range.size = pf_async_vec; + pf_irq_table->pf_async_pool = irq_pool_alloc(dev, irq_range.start, irq_range.size, "zxdh_pf_async", + ZXDH_PF_ASYNC_IRQ_MIN_COMP, + ZXDH_PF_ASYNC_IRQ_MAX_COMP); + if (IS_ERR_OR_NULL(pf_irq_table->pf_async_pool)) + { + LOG_ERR("pf_irq_table->pf_async_pool irq_pool_alloc failed\n"); + err = PTR_ERR(pf_irq_table->pf_async_pool); + goto err_irqs_per_cpu; + } + } + + irq_range.start = ZXDH_RDMA_IRQ_START_IDX; + irq_range.size = ZXDH_RDMA_CHANNELS_NUM; + pf_irq_table->pf_rdma_pool = irq_pool_alloc(dev, irq_range.start, irq_range.size, "zxdh_pf_rdma", + ZXDH_PF_RDMA_IRQ_MIN, + ZXDH_PF_RDMA_IRQ_MAX); + if (IS_ERR_OR_NULL(pf_irq_table->pf_rdma_pool)) + { + LOG_ERR("pf_irq_table->pf_rdma_pool irq_pool_alloc failed\n"); + err = PTR_ERR(pf_irq_table->pf_rdma_pool); + goto err_pf_rdma; + } + + return 0; + +err_pf_rdma: + irq_pool_free(pf_irq_table->pf_async_pool); +err_irqs_per_cpu: + irq_pool_free(pf_irq_table->pf_vq_pool); + return err; +} + +static void irq_pools_destroy(struct dh_irq_table *table) +{ + struct dh_pf_irq_table* pf_irq_table = NULL; + + pf_irq_table = (struct dh_pf_irq_table*)table->priv; + pf_irq_table->pf_vq_pool ? irq_pool_free(pf_irq_table->pf_vq_pool) : 0; + pf_irq_table->pf_async_pool ? irq_pool_free(pf_irq_table->pf_async_pool) : 0; + pf_irq_table->pf_rdma_pool ? irq_pool_free(pf_irq_table->pf_rdma_pool) : 0; +} + +static int32_t zxdh_get_total_vec(struct dh_core_dev *dev) +{ + return ZXDH_VQS_CHANNELS_NUM + ZXDH_ASYNC_CHANNELS_NUM + ZXDH_RDMA_CHANNELS_NUM; +} + +int32_t dh_pf_irq_table_create(struct dh_core_dev *dev) +{ + int32_t total_vec = 0; + int32_t err = 0; + + total_vec = zxdh_get_total_vec(dev); + + total_vec = pci_alloc_irq_vectors(dev->pdev, total_vec, total_vec, PCI_IRQ_MSIX); + if (total_vec < 0) + { + LOG_ERR("pci_alloc_irq_vectors failed: %d\n", total_vec); + return total_vec; + } + + err = irq_pools_init(dev, ZXDH_VQS_CHANNELS_NUM, ZXDH_ASYNC_CHANNELS_NUM); + if (err != 0) + { + LOG_ERR("irq_pools_init failed: %d\n", err); + pci_free_irq_vectors(dev->pdev); + } + + return err; +} + +void dh_pf_irq_table_destroy(struct dh_core_dev *dev) +{ + struct dh_irq_table *table = &dev->irq_table; + + /* There are cases where IRQs still will be in used when we reaching + * to here. Hence, making sure all the irqs are released. + */ + irq_pools_destroy(table); + pci_free_irq_vectors(dev->pdev); +} + +struct dh_irq *dh_pf_async_irq_request(struct dh_core_dev *dev) +{ + struct dh_irq_table *table = &dev->irq_table; + struct dh_pf_irq_table* pf_irq_table; + + pf_irq_table = (struct dh_pf_irq_table*)table->priv; + + return pf_irq_table->pf_async_pool ? zxdh_get_irq_of_pool(dev, pf_irq_table->pf_async_pool) : NULL; +} + +/* irq_table API */ +int32_t dh_pf_irq_table_init(struct dh_core_dev *dev) +{ + struct dh_irq_table *irq_table; + struct dh_pf_irq_table* pf_irq_table = NULL; + + irq_table = &dev->irq_table; + + pf_irq_table = kvzalloc(sizeof(*pf_irq_table), GFP_KERNEL); + if (unlikely(pf_irq_table == NULL)) + { + LOG_ERR("pf_irq_table kvzalloc failed\n"); + return -ENOMEM; + } + + irq_table->priv = pf_irq_table; + + return 0; +} \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_pf/irq.h b/src/net/drivers/net/ethernet/dinghai/en_pf/irq.h new file mode 100755 index 0000000..6cacd5c --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_pf/irq.h @@ -0,0 +1,27 @@ +#ifndef __ZXDH_PF_IRQ_H__ +#define __ZXDH_PF_IRQ_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +struct dh_irq *dh_pf_async_irq_request(struct dh_core_dev *dev); +int32_t dh_pf_irq_table_create(struct dh_core_dev *dev); +void dh_pf_irq_table_destroy(struct dh_core_dev *dev); +int32_t dh_pf_irq_table_init(struct dh_core_dev *dev); + +struct dh_pf_irq_table { + struct dh_irq_pool *sf_comp_pool; + struct dh_irq_pool *pf_async_pool; + struct dh_irq_pool *pf_rdma_pool; + struct dh_irq_pool *pf_vq_pool; +}; + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_pf/msg_func.c b/src/net/drivers/net/ethernet/dinghai/en_pf/msg_func.c new file mode 100644 index 0000000..7ce3c32 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_pf/msg_func.c @@ -0,0 +1,1473 @@ +#include +#include +#include "../msg_common.h" +#include "../en_pf.h" +#include "../en_aux/en_cmd.h" +#include "../en_aux.h" +#include "../en_np/init/include/dpp_np_init.h" +#include "eq.h" +#include "msg_func.h" + +#define FUNC_NAME_SIZE_MAX 32 + +typedef uint32_t (*zxdh_vf_msg_func)(zxdh_msg_info *msg, zxdh_reps_info *reps, \ + DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev); + +typedef struct +{ + zxdh_msg_op_code op_code; + uint8_t proc_name[FUNC_NAME_SIZE_MAX]; + zxdh_vf_msg_func msg_proc; +} zxdh_vf_msg_proc; + +void zxdh_u32_array_print(uint32_t *array, uint16_t size) +{ + uint16_t i; + + for (i = 0; i < size; ++i) + { + printk(KERN_CONT "%u ", array[i]); + if ((i + 1) % 8 == 0) + { + printk(KERN_CONT "\n"); + } + } +} +EXPORT_SYMBOL(zxdh_u32_array_print); + +static void zxdh_vf_link_state_get_proc(zxdh_msg_info *msg, zxdh_reps_info *reps, \ + DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev) +{ + int vf_idx = msg->hdr.pcie_id & (0xff); + uint32_t dev_link_up_reg = 0; + uint8_t vf_link_up = 0; + + if(vf_item->link_forced) + { + vf_link_up = vf_item->link_up ? 1 : 0; + } + else + { + vf_link_up = pf_dev->link_up ? 1 : 0; + } + + dev_link_up_reg = ioread32((void __iomem *)(pf_dev->pf_sriov_cap_base + (pf_dev->sriov_bar_size) * vf_idx + ZXDH_DEV_MAC_HIGH_OFFSET)); + dev_link_up_reg = (dev_link_up_reg & ~(0xFF << 16)) | ((uint32_t)(vf_link_up) << 16); + iowrite32(dev_link_up_reg, (void __iomem *)(pf_dev->pf_sriov_cap_base + (pf_dev->sriov_bar_size) * vf_idx + ZXDH_DEV_MAC_HIGH_OFFSET)); + + LOG_INFO("vf[%d] link_forced is [%s], link state[%s] update ok.\n", vf_idx, vf_item->link_forced?"TRUE":"FALSE", (vf_link_up==1)?"UP":"DOWN"); + +} + +int32_t zxdh_vf_flush_mac(DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item) +{ + int32_t err = 0; + uint8_t i = 0; + uint8_t *addr = NULL; + + /* 删除此VF的所有单播mac地址 */ + for (i = 0; i < DEV_UNICAST_MAX_NUM; ++i) + { + addr = vf_item->vf_mac_info.unicast_mac[i]; + + if (!is_zero_ether_addr(addr)) /* mac不全为0 */ + { +#ifdef MAC_CONFIG_DEBUG + LOG_INFO("the deleted unicast mac is %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n",\ + addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]); +#endif /* MAC_CONFIG_DEBUG */ + + err = dpp_del_mac(pf_info, addr); + if (err != 0) + { + LOG_ERR("dpp_del_mac failed\n"); + return err; + } + } + } + + /* 删除此VF的所有组播mac地址 */ + for (i = 0; i < DEV_MULTICAST_MAX_NUM; ++i) + { + addr = vf_item->vf_mac_info.multicast_mac[i]; + + if (!is_zero_ether_addr(addr)) /* mac不全为0 */ + { +#ifdef MAC_CONFIG_DEBUG + LOG_INFO("the deleted multicasat mac is %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n",\ + addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]); +#endif /* MAC_CONFIG_DEBUG */ + + err = dpp_multi_mac_del_member(pf_info, addr); + if (err != 0) + { + LOG_ERR("dpp_multi_mac_del_member failed\n"); + return err; + } + } + } + + /* 将vf_mac_info结构体全部清零 */ + memset(&vf_item->vf_mac_info, 0, sizeof(vf_item->vf_mac_info)); + + return err; +} + +static uint32_t zxdh_vf_port_init(zxdh_msg_info *msg, zxdh_reps_info *reps, \ + DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev) +{ + uint32_t ret = 0; + uint8_t mac[6] = {0}; + + ret = dpp_vport_create(pf_info); + if (ret != 0) + { + LOG_ERR("dpp_vport_create failed, ret: %d\n", ret); + return ret; + } + + if (msg->vf_init_msg.is_upf) + { + ret = dpp_egr_port_attr_set(pf_info, EGR_FLAG_LAG_ID, 0); + if (ret != 0) + { + LOG_ERR("dpp_egr_port_attr_set panel_id %d failed: %d\n", pf_dev->phy_port, ret); + goto err_init; + } + + ret = dpp_egr_port_attr_set(pf_info, EGR_FLAG_LAG_EN_OFF, 1); + if (ret != 0) + { + LOG_ERR("dpp_egr_port_attr_set hash_search_idx %u failed: %d\n", msg->vf_init_msg.hash_search_idx, ret); + goto err_init; + } + } + else + { + ret = dpp_egr_port_attr_set(pf_info, EGR_FLAG_PANEL_ID, pf_dev->phy_port); + if (ret != 0) + { + LOG_ERR("dpp_egr_port_attr_set panel_id %d failed: %d\n", pf_dev->phy_port, ret); + goto err_init; + } + } + + ret = dpp_egr_port_attr_set(pf_info, EGR_FLAG_HASH_SEARCH_INDEX, msg->vf_init_msg.hash_search_idx); + if (ret != 0) + { + LOG_ERR("dpp_egr_port_attr_set hash_search_idx %u failed: %d\n", msg->vf_init_msg.hash_search_idx, ret); + goto err_init; + } + + ret = dpp_vport_bond_pf(pf_info); + if (ret != 0) + { + LOG_ERR("dpp_vport_bond_pf failed, ret: %d\n", ret); + goto err_init; + } + + ret = dpp_vport_rss_en_set(pf_info, msg->vf_init_msg.rss_enable); + if (ret != 0) + { + LOG_ERR("dpp_vport_rss_en_set failed, ret: %d\n", ret); + goto err_init; + } + + ret = dpp_vport_hash_funcs_set(pf_info, ZXDH_FUNC_TOP); + if (ret != 0) + { + LOG_ERR("dpp_vport_hash_funcs_set failed, ret: %d\n", ret); + goto err_init; + } + + ret = dpp_rx_flow_hash_set(pf_info, ZXDH_NET_RX_FLOW_HASH_SDFNT); + if (ret != 0) + { + LOG_ERR("dpp_rx_flow_hash_set failed, ret: %d\n", ret); + goto err_init; + } + + ret = dpp_egr_port_attr_set(pf_info, EGR_FLAG_VEPA_EN_OFF, (uint32_t)pf_dev->vepa); + if (ret != 0) + { + LOG_ERR("dpp_egr_port_attr_set vport(0x%x) %s mode failed: %d\n", msg->hdr.vport, pf_dev->vepa?"vepa":"veb", ret); + goto err_init; + } + LOG_INFO("Initialize vport(0x%x) to %s mode\n", msg->hdr.vport, pf_dev->vepa?"vepa":"veb"); + + ret = dpp_egr_port_attr_set(pf_info, EGR_FLAG_PORT_BASE_QID, msg->vf_init_msg.base_qid); + if (ret != 0) + { + LOG_ERR("set_base_qid %d failed: %d\n", msg->vf_init_msg.base_qid, ret); + goto err_init; + } + + ret = dpp_egr_port_attr_set(pf_info, EGR_FLAG_SPOOFCHK_EN_OFF, vf_item->spoofchk); + if (0 != ret) + { + LOG_ERR("dpp_egr_port_attr_set spookchk %s failed: %d\n", vf_item->spoofchk? "on":"off", ret); + goto err_init; + } + + ret = dpp_egr_port_attr_set(pf_info, EGR_FLAG_IPV4_TCP_ASSEMBLE, 1); + if (ret != 0) + { + LOG_ERR("dpp_egr_port_attr_set tcp assemble failed: %d\n", ret); + goto err_init; + } + + ret = dpp_egr_port_attr_set(pf_info, EGR_FLAG_IPV6_TCP_ASSEMBLE, 1); + if (ret != 0) + { + LOG_ERR("dpp_egr_port_attr_set tcp assemble failed: %d\n", ret); + goto err_init; + } + + ret = dpp_egr_port_attr_set(pf_info, EGR_FLAG_IP_CHKSUM, 1); + if (ret != 0) + { + LOG_ERR("dpp_egr_port_attr_set rx ip checksum failed: %d\n", ret); + goto err_init; + } + + ret = dpp_egr_port_attr_set(pf_info, EGR_FLAG_TCP_UDP_CHKSUM, 1); + if (ret != 0) + { + LOG_ERR("dpp_egr_port_attr_set rx l4 checksum failed: %d\n", ret); + goto err_init; + } + + ret = dpp_egr_port_attr_set(pf_info, EGR_FLAG_ACCELERATOR_OFFLOAD_FLAG, 1); + if (ret != 0) + { + LOG_ERR("dpp_egr_port_attr_set accelerator offload failed: %d\n", ret); + goto err_init; + } + + ret = dpp_egr_port_attr_set(pf_info, EGR_FLAG_OUTER_IP_CHECKSUM_OFFLOAD, 1); + if (ret != 0) + { + LOG_ERR("dpp_egr_port_attr_set vxlan outer ip checksum failed: %d\n", ret); + goto err_init; + } + ret = dpp_vport_vlan_filter_en_set(pf_info, 0); + if (ret != 0) + { + LOG_ERR("dpp_vport_vlan_filter_en_set failed, ret: %d\n", ret); + goto err_init; + } + + ret = dpp_vlan_filter_init(pf_info); + if (ret != 0) + { + LOG_ERR("dpp_vlan_filter_init failed: %d\n", ret); + goto err_init; + } + + ret = zxdh_vf_flush_mac(pf_info, vf_item); + if (ret != 0) + { + goto err_init; + } + + ether_addr_copy(mac, vf_item->mac); + if (is_zero_ether_addr(mac)) + { + get_random_bytes(mac, 6); + mac[0] &= 0xfe; + LOG_INFO("vf set random mac %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + } + LOG_INFO("zxdh_vf_port_init mac %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + ret = dpp_add_mac(pf_info, mac); + if (ret != 0) + { + LOG_ERR("dpp_add_mac failed, ret: %d\n", ret); + return ret; + } + + dpp_vport_uc_promisc_set(pf_info, 0); + dpp_vport_mc_promisc_set(pf_info, 0); + + ether_addr_copy(vf_item->vf_mac_info.unicast_mac[0], mac); + ether_addr_copy(reps->vf_init_msg.mac_addr, mac); + reps->vf_init_msg.phy_port = pf_dev->phy_port; + reps->vf_init_msg.link_up = pf_dev->link_up; + reps->vf_init_msg.speed = pf_dev->speed; + reps->vf_init_msg.duplex = pf_dev->duplex; + reps->vf_init_msg.autoneg_enable = pf_dev->autoneg_enable; + reps->vf_init_msg.sup_link_modes = pf_dev->supported_speed_modes; + reps->vf_init_msg.adv_link_modes = pf_dev->advertising_speed_modes; + + zxdh_vf_link_state_get_proc(msg, reps, pf_info, vf_item, pf_dev); + vf_item->is_probed = true; + return 0; + +err_init: + dpp_vport_delete(pf_info); + return ret; +} + +static uint32_t zxdh_vf_port_uninit(zxdh_msg_info *msg, zxdh_reps_info *reps, \ + DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev) +{ + int32_t ret = 0; + + dpp_vport_uc_promisc_set(pf_info, 0); + dpp_vport_mc_promisc_set(pf_info, 0); + + ret = zxdh_vf_flush_mac(pf_info, vf_item); + if (ret != 0) + { + LOG_ERR("zxdh_vf_flush_macf failed, ret: %d\n", ret); + return ret; + } + + ret = dpp_vport_unbond_pf(pf_info); + if (ret != 0) + { + LOG_ERR("dpp_vport_unbond_pf failed, ret: %d\n", ret); + return ret; + } + + ret = dpp_vport_delete(pf_info); + if (ret != 0) + { + LOG_ERR("dpp_vport_delete failed, ret: %d\n", ret); + return ret; + } + + ret = dpp_vport_unregister(pf_info); + if (ret != 0) + { + LOG_ERR("dpp_vport_unregister failed, ret: %d\n", ret); + return ret; + } + + vf_item->is_probed = false; + return ret; +} + +void zxdh_vf_item_mac_add(struct zxdh_vf_item *vf_item, uint8_t *mac_addr) +{ + uint8_t *addr = NULL; + uint8_t i = 0; + + if (is_unicast_ether_addr(mac_addr)) + { + for (i = 1; i < DEV_UNICAST_MAX_NUM; ++i) + { + addr = vf_item->vf_mac_info.unicast_mac[i]; + if (is_zero_ether_addr(addr)) /*查询没使用的数组*/ + { + /* 将此mac添加到zxdh_vf_item中 */ + memcpy(addr, mac_addr, ETH_ALEN); + break; + } + } + } + else + { + for (i = 0; i < DEV_MULTICAST_MAX_NUM; ++i) + { + addr = vf_item->vf_mac_info.multicast_mac[i]; + + if (is_zero_ether_addr(addr)) + { + /* 将此mac添加到zxdh_vf_item中 */ + memcpy(addr, mac_addr, ETH_ALEN); + break; + } + } + } + + return; +} + +void zxdh_vf_item_mac_del(struct zxdh_vf_item *vf_item, uint8_t *mac_addr) +{ + uint8_t i = 0; + uint8_t *addr = NULL; + + if (is_unicast_ether_addr(mac_addr)) + { + for (i = 1; i < DEV_UNICAST_MAX_NUM; ++i) + { + /* 获取此mac地址 */ + addr = vf_item->vf_mac_info.unicast_mac[i]; + + if (ether_addr_equal(addr, mac_addr))/* 查询到此mac */ + { +#ifdef MAC_CONFIG_DEBUG + LOG_INFO("the mac is %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n", \ + addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]); +#endif /* MAC_CONFIG_DEBUG */ + + /* 在地址数组中将此mac清空*/ + memset(addr, 0, ETH_ALEN); + break; + } + } + } + else + { + for (i = 0; i < DEV_MULTICAST_MAX_NUM; ++i) + { + addr = vf_item->vf_mac_info.multicast_mac[i]; + + if (ether_addr_equal(addr, mac_addr))/* 查询到此mac */ + { +#ifdef MAC_CONFIG_DEBUG + LOG_INFO("the mac is %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n", + addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]); +#endif /* MAC_CONFIG_DEBUG */ + + /* 在地址数组中将此mac清空 */ + memset(addr, 0, ETH_ALEN); + break; + } + } + } + + return; +} + +static uint32_t zxdh_vf_mac_add(zxdh_msg_info *msg, zxdh_reps_info *reps, \ + DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev) +{ + int32_t ret = 0; + + if (ether_addr_equal(vf_item->mac, msg->mac_addr_set_msg.mac_addr) || (vf_item->pf_set_mac && vf_item->trusted) || (vf_item->pf_set_mac == false)) + { + ether_addr_copy(vf_item->vf_mac_info.unicast_mac[0], msg->mac_addr_set_msg.mac_addr); + ether_addr_copy(vf_item->mac, msg->mac_addr_set_msg.mac_addr); + ret = dpp_add_mac(pf_info, msg->mac_addr_set_msg.mac_addr); + if (ret != 0) + { + LOG_ERR("dpp_add_mac failed, ret: %d\n", ret); + return ret; + } + } + else + { + LOG_ERR("zxdh_vf_mac_add failed, vf not Trusted\n"); + return -1; + } + + return ret; +} + +static uint32_t zxdh_vf_mac_del(zxdh_msg_info *msg, zxdh_reps_info *reps, \ + DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev) +{ + int32_t ret = 0; + uint8_t i = 0; + uint8_t *addr = NULL; + + if (msg->mac_addr_set_msg.mac_flag == true) + { + if ((vf_item->pf_set_mac && vf_item->trusted) || (vf_item->pf_set_mac == false)) + { + eth_zero_addr(vf_item->mac); + ret = dpp_del_mac(pf_info, msg->mac_addr_set_msg.mac_addr); + if (ret != 0) + { + LOG_ERR("dpp_del_mac failed, ret: %d\n", ret); + return ret; + } + } + else + { + LOG_ERR("zxdh_vf_mac_del failed, vf not Trusted\n"); + return -1; + } + } + + if(msg->mac_addr_set_msg.mac_addr == vf_item->vf_mac_info.unicast_mac[0]) + { + for (i = 1; i < DEV_UNICAST_MAX_NUM; ++i) + { + addr = vf_item->vf_mac_info.unicast_mac[i]; + if (is_zero_ether_addr(addr)) + { + memcpy(addr, vf_item->vf_mac_info.unicast_mac[0], ETH_ALEN); + break; + } + } + } + + return ret; +} + +static uint32_t zxdh_vf_filter_mac_add(zxdh_msg_info *msg, zxdh_reps_info *reps, \ + DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev) +{ + uint32_t err = 0; + +#ifdef MAC_CONFIG_DEBUG + /* 将获取到的mac地址配置到NP中 */ + LOG_INFO("msg->mac_addr_set_msg.mac_addr is %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n", \ + msg->mac_addr_set_msg.mac_addr[0], msg->mac_addr_set_msg.mac_addr[1], \ + msg->mac_addr_set_msg.mac_addr[2], msg->mac_addr_set_msg.mac_addr[3], \ + msg->mac_addr_set_msg.mac_addr[4], msg->mac_addr_set_msg.mac_addr[5]); +#endif /*MAC_CONFIG_DEBUG */ + + err = dpp_add_mac(pf_info, msg->mac_addr_set_msg.mac_addr); + if (err != 0) + { + LOG_ERR("dpp_add_mac failed \n"); + return err; + } + + /* 将此mac地址添加到zxdh_vf_item */ + zxdh_vf_item_mac_add(vf_item, msg->mac_addr_set_msg.mac_addr); + + return err; +} + +static uint32_t zxdh_vf_filter_mac_del(zxdh_msg_info *msg, zxdh_reps_info *reps, \ + DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev) +{ + uint32_t err = 0; + +#ifdef MAC_CONFIG_DEBUG + /* 将获取到的mac地址从NP中删除 */ + LOG_INFO("msg->mac_addr_set_msg.mac_addr is %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n", \ + msg->mac_addr_set_msg.mac_addr[0], msg->mac_addr_set_msg.mac_addr[1], \ + msg->mac_addr_set_msg.mac_addr[2], msg->mac_addr_set_msg.mac_addr[3], \ + msg->mac_addr_set_msg.mac_addr[4], msg->mac_addr_set_msg.mac_addr[5]); +#endif /* MAC_CONFIG_DEBUG */ + + err = dpp_del_mac(pf_info, msg->mac_addr_set_msg.mac_addr); + if (err != 0) + { + LOG_ERR("dpp_mac_del failed\n"); + return err; + } + + /* 将此mac从zxdh_vf_item中删除 */ + zxdh_vf_item_mac_del(vf_item, msg->mac_addr_set_msg.mac_addr); + + return err; +} + +static uint32_t zxdh_vf_multi_mac_add(zxdh_msg_info *msg, zxdh_reps_info *reps, \ + DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev) +{ + uint32_t err = 0; + +#ifdef MAC_CONFIG_DEBUG + /* 将此mac地址添加到np中 */ + LOG_INFO("msg->mac_addr_set_msg.mac_addr is %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n", \ + msg->mac_addr_set_msg.mac_addr[0], msg->mac_addr_set_msg.mac_addr[1], \ + msg->mac_addr_set_msg.mac_addr[2], msg->mac_addr_set_msg.mac_addr[3], \ + msg->mac_addr_set_msg.mac_addr[4], msg->mac_addr_set_msg.mac_addr[5]); +#endif /* MAC_CONFIG_DEBUG*/ + + err = dpp_multi_mac_add_member(pf_info, msg->mac_addr_set_msg.mac_addr); + if (err != 0) + { + if (err == DPP_RC_TABLE_RANGE_INVALID) + { + LOG_ERR("multicast mac is beyond 32\n"); + return DPP_RC_TABLE_RANGE_INVALID; + } + LOG_ERR("dpp_multi_mac_add_member failed %d\n", err); + return err; + } + + /* 将此mac添加到zxdh_vf_item中 */ + zxdh_vf_item_mac_add(vf_item, msg->mac_addr_set_msg.mac_addr); + + return err; +} + +static uint32_t zxdh_vf_multi_mac_del(zxdh_msg_info *msg, zxdh_reps_info *reps, \ + DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev) +{ + uint32_t err = 0; + +#ifdef MAC_CONFIG_DEBUG + LOG_INFO("msg->mac_addr_set_msg.mac_addr is %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n", \ + msg->mac_addr_set_msg.mac_addr[0], msg->mac_addr_set_msg.mac_addr[1], \ + msg->mac_addr_set_msg.mac_addr[2], msg->mac_addr_set_msg.mac_addr[3], \ + msg->mac_addr_set_msg.mac_addr[4], msg->mac_addr_set_msg.mac_addr[5]); +#endif /* MAC_CONFIG_DEBUG */ + + /* 将此组播mac地址从np中删除 */ + err = dpp_multi_mac_del_member(pf_info, msg->mac_addr_set_msg.mac_addr); + if (err != 0) + { + LOG_INFO("dpp_multi_mac_del_member failed %d\n", err); + return err; + } + + /* 将此mac从zxdh_vf_item中删除 */ + zxdh_vf_item_mac_del(vf_item, msg->mac_addr_set_msg.mac_addr); + + return err; +} + +static uint32_t zxdh_vf_all_mac_add(zxdh_msg_info *msg, zxdh_reps_info *reps, \ + DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev) +{ + /* 配置组播mac*/ + if (!is_unicast_ether_addr(msg->mac_addr_set_msg.mac_addr)) + { + return zxdh_vf_multi_mac_add(msg, reps, pf_info, vf_item, pf_dev); + } + + /* 配置本机mac*/ + if (msg->mac_addr_set_msg.filter_flag == UNFILTER_MAC) + { + return zxdh_vf_mac_add(msg, reps, pf_info, vf_item, pf_dev); + } + + /* 配置过滤用的单播mac*/ + return zxdh_vf_filter_mac_add(msg, reps, pf_info, vf_item, pf_dev); +} + +static uint32_t zxdh_vf_all_mac_del(zxdh_msg_info *msg, zxdh_reps_info *reps, \ + DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev) +{ + /* 删除组播mac */ + if (!is_unicast_ether_addr(msg->mac_addr_set_msg.mac_addr)) + { + return zxdh_vf_multi_mac_del(msg, reps, pf_info, vf_item, pf_dev); + } + + /* 删除本机mac */ + if (msg->mac_addr_set_msg.filter_flag == UNFILTER_MAC) + { + return zxdh_vf_mac_del(msg, reps, pf_info, vf_item, pf_dev); + } + + /* 删除过滤用的单播mac*/ + return zxdh_vf_filter_mac_del(msg, reps, pf_info, vf_item, pf_dev); +} + +static uint32_t zxdh_vf_ipv6_mac_add(zxdh_msg_info *msg, zxdh_reps_info *reps, \ + DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev) +{ + uint32_t err = 0; + + spin_lock_bh(&pf_dev->vf_ip6mac_lock); + + err = zxdh_vf_multi_mac_add(msg, reps, pf_info, vf_item, pf_dev); + if (err != 0) + { + LOG_ERR("zxdh_vf_multi_mac_add failed\n"); + } + + spin_unlock_bh(&pf_dev->vf_ip6mac_lock); + + return err; +} + +static uint32_t zxdh_vf_ipv6_mac_del(zxdh_msg_info *msg, zxdh_reps_info *reps, \ + DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev) +{ + uint32_t err = 0; + + spin_lock_bh(&pf_dev->vf_ip6mac_lock); + + err = zxdh_vf_multi_mac_del(msg, reps, pf_info, vf_item, pf_dev); + if (err != 0) + { + LOG_ERR("zxdh_vf_multi_mac_del failed\n"); + } + + spin_unlock_bh(&pf_dev->vf_ip6mac_lock); + + return err; +} + +static uint32_t zxdh_vf_mac_get(zxdh_msg_info *msg, zxdh_reps_info *reps, \ + DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev) +{ + ether_addr_copy(reps->vf_mac_addr_get_msg.mac_addr, vf_item->mac); + return 0; +} + +static uint32_t zxdh_vf_rss_state_set(zxdh_msg_info *msg, zxdh_reps_info *reps, \ + DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev) +{ + return dpp_vport_rss_en_set(pf_info, msg->rss_enable_msg.rss_enable); +} + +static uint32_t zxdh_vf_rxfh_set(zxdh_msg_info *msg, zxdh_reps_info *reps, \ + DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev) +{ + return dpp_rxfh_set(pf_info, msg->rxfh_set_msg.queue_map, ZXDH_INDIR_RQT_SIZE); +} + +static uint32_t zxdh_vf_rxfh_get(zxdh_msg_info *msg, zxdh_reps_info *reps, \ + DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev) +{ + uint32_t err = 0; + + err = dpp_rxfh_get(pf_info, reps->rxfh_get_msg.queue_map, ZXDH_INDIR_RQT_SIZE); + if (err != 0) + { + LOG_ERR("dpp_rxfh_get failed: %d\n", err); + return err; + } + + return 0; +} + +static uint32_t zxdh_vf_rxfh_del(zxdh_msg_info *msg, zxdh_reps_info *reps, \ + DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev) +{ + return dpp_rxfh_del(pf_info); +} + +static uint32_t zxdh_vf_thash_key_set(zxdh_msg_info *msg, zxdh_reps_info *reps, \ + DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev) +{ + return dpp_thash_key_set(pf_info, msg->thash_key_set_msg.key_map, ZXDH_NET_HASH_KEY_SIZE); +} + +static uint32_t zxdh_vf_thash_key_get(zxdh_msg_info *msg, zxdh_reps_info *reps, \ + DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev) +{ + return dpp_thash_key_get(pf_info, reps->thash_key_set_msg.key_map, ZXDH_NET_HASH_KEY_SIZE); +} + +static uint32_t zxdh_vf_hash_funcs_set(zxdh_msg_info *msg, zxdh_reps_info *reps, \ + DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev) +{ + return dpp_vport_hash_funcs_set(pf_info, msg->hfunc_set_msg.func); +} + +static uint32_t zxdh_vf_rx_flow_hash_set(zxdh_msg_info *msg, zxdh_reps_info *reps, \ + DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev) +{ + return dpp_rx_flow_hash_set(pf_info, msg->rx_flow_hash_set_msg.hash_mode); +} + +static uint32_t zxdh_vf_vlan_strip_set(zxdh_msg_info *msg, zxdh_reps_info *reps, \ + DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev) +{ + if (msg->vlan_strip_msg.flag == VLAN_STRIP_MSG_TYPE) + { + return dpp_vport_vlan_strip_set(pf_info, msg->vlan_strip_msg.enable); + } + else + { + return dpp_vport_vlan_qinq_en_set(pf_info, msg->vlan_strip_msg.enable); + } +} + +static uint32_t zxdh_vf_qinq_tpid_cfg(zxdh_msg_info *msg, zxdh_reps_info *reps, \ + DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev) +{ + return dpp_egr_port_attr_set(pf_info, EGR_FLAG_TPID, msg->tpid_cfg_msg.tpid); +} + +static uint32_t zxdh_vf_rx_flow_hash_get(zxdh_msg_info *msg, zxdh_reps_info *reps, \ + DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev) +{ + return dpp_rx_flow_hash_get(pf_info, &reps->rx_flow_hash_set_msg.hash_mode); +} + +static uint32_t zxdh_vf_port_attrs_set(zxdh_msg_info *msg, zxdh_reps_info *reps, \ + DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev) +{ + if (msg->port_attr_set_msg.mode == EGR_FLAG_TCP_UDP_CHKSUM) + { + dpp_egr_port_attr_set(pf_info, EGR_FLAG_IP_CHKSUM, msg->port_attr_set_msg.value); + } + + return dpp_egr_port_attr_set(pf_info, msg->port_attr_set_msg.mode, msg->port_attr_set_msg.value); +} + +static uint32_t zxdh_vf_port_attrs_get(zxdh_msg_info *msg, zxdh_reps_info *reps, \ + DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev) +{ + return dpp_egr_port_attr_get(pf_info, &reps->port_attr_get_msg.port_attr_entry); +} + +static uint32_t zxdh_vf_promisc_set(zxdh_msg_info *msg, zxdh_reps_info *reps, \ + DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev) +{ + uint32_t err = 0; + + if (!vf_item->trusted) + { + LOG_ERR("vf untrusted!\n"); + return 0; + } + + if (msg->promisc_set_msg.mode == ZXDH_PROMISC_MODE) + { + LOG_INFO("PROMISC_EN_SET: %d", msg->promisc_set_msg.value); + err = dpp_vport_uc_promisc_set(pf_info, msg->promisc_set_msg.value); + if (err != 0) + { + LOG_ERR("dpp_vport_uc_promisc_set failed: %d\n", err); + return err; + } + if (msg->promisc_set_msg.mc_follow != 0) + { + LOG_DEBUG("allmulti_follow\n"); + err = dpp_vport_mc_promisc_set(pf_info, msg->promisc_set_msg.value); + if (err != 0) + { + LOG_ERR("dpp_vport_mc_promisc_set failed: %d\n", err); + return err; + } + } + vf_item->promisc = msg->promisc_set_msg.value; + } + else if (msg->promisc_set_msg.mode == ZXDH_ALLMULTI_MODE) + { + LOG_INFO("ALLMULTI_EN_SET: %d", msg->promisc_set_msg.value); + err = dpp_vport_mc_promisc_set(pf_info, msg->promisc_set_msg.value); + if (err != 0) + { + LOG_ERR("dpp_vport_mc_promisc_set failed: %d\n", err); + return err; + } + vf_item->mc_promisc = msg->promisc_set_msg.value; + } + else + { + LOG_ERR("promisc_set_msg.mode[%d] error\n", msg->promisc_set_msg.mode); + return 1; + } + + return err; +} + +static uint32_t zxdh_vf_vlan_filter_set(zxdh_msg_info *msg, zxdh_reps_info *reps, \ + DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev) +{ + bool vf_vlan_filter_enable = msg->vlan_filter_set_msg.enable; + + return dpp_vport_vlan_filter_en_set(pf_info, vf_vlan_filter_enable); +} + +static uint32_t zxdh_vf_rx_vid_add(zxdh_msg_info *msg, zxdh_reps_info *reps, \ + DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev) +{ + uint16_t vid = msg->rx_vid_add_msg.vlan_id; + + return dpp_add_vlan_filter(pf_info, vid); +} + +static uint32_t zxdh_vf_rx_vid_del(zxdh_msg_info *msg, zxdh_reps_info *reps, \ + DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev) +{ + uint16_t vid = msg->rx_vid_del_msg.vlan_id; + + return dpp_del_vlan_filter(pf_info, vid); +} + +static uint32_t zxdh_vf_np_stats_get(zxdh_msg_info *msg, zxdh_reps_info *reps, \ + DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev) +{ + uint32_t vf_id = msg->hdr.vf_id; + + dpp_stat_port_bc_packet_rx_cnt_get(pf_info, vf_id, msg->np_stats_get_msg.clear_mode, + &reps->np_stats_msg.np_rx_broadcast); + dpp_stat_port_bc_packet_tx_cnt_get(pf_info, vf_id, msg->np_stats_get_msg.clear_mode, + &reps->np_stats_msg.np_tx_broadcast); + + dpp_stat_MTU_packet_msg_rx_cnt_get(pf_info, vf_id, msg->np_stats_get_msg.clear_mode, + &reps->np_stats_msg.np_rx_mtu_drop_bytes, &reps->np_stats_msg.np_rx_mtu_drop_pkts); + dpp_stat_MTU_packet_msg_tx_cnt_get(pf_info, vf_id, msg->np_stats_get_msg.clear_mode, + &reps->np_stats_msg.np_tx_mtu_drop_bytes, &reps->np_stats_msg.np_tx_mtu_drop_pkts); + + dpp_stat_plcr_packet_drop_rx_cnt_get(pf_info, vf_id, msg->np_stats_get_msg.clear_mode, + &reps->np_stats_msg.np_rx_plcr_drop_bytes, &reps->np_stats_msg.np_rx_plcr_drop_pkts); + dpp_stat_plcr_packet_drop_tx_cnt_get(pf_info, vf_id, msg->np_stats_get_msg.clear_mode, + &reps->np_stats_msg.np_tx_plcr_drop_bytes, &reps->np_stats_msg.np_tx_plcr_drop_pkts); + + return 0; +} + +static uint32_t zxdh_vf_rate_limit_set(zxdh_msg_info *msg, zxdh_reps_info *reps, \ + DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev) +{ + int32_t rtn; + uint16_t vport = msg->hdr.vport; + uint32_t flowid = msg->rate_limit_set_msg.flowid; + uint32_t car_type = msg->rate_limit_set_msg.car_type; + uint32_t max_rate = msg->rate_limit_set_msg.max_rate; + uint32_t min_rate = msg->rate_limit_set_msg.min_rate; + uint32_t is_packet = msg->rate_limit_set_msg.is_packet; + + PLCR_FUNC_DBG_ENTER(); + + rtn = zxdh_plcr_set_rate_limit(pf_dev, is_packet, car_type, vport, flowid, max_rate, min_rate); + reps->rate_limit_set_rsp.err_code = rtn; + + if (PLCR_REMOVE_RATE_LIMIT == rtn) + { + return 0; + } + else + { + return rtn; + } +} + +static uint32_t zxdh_vf_plcr_uninit(zxdh_msg_info *msg, zxdh_reps_info *reps, \ + DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev) +{ + uint16_t vport; + unsigned long flow_id; + E_PLCR_CAR_TYPE car_index; + struct xarray *xarray_flow; + struct zxdh_plcr_flow *flow = NULL; + + PLCR_FUNC_DBG_ENTER(); + + vport = msg->hdr.vport; + + //deal with car A's flowid + for(car_index=E_PLCR_CAR_A; car_index <= E_PLCR_CAR_B; car_index++) + { + xarray_flow = &(pf_dev->plcr_table.plcr_flows[car_index]); + xa_for_each_range(xarray_flow, flow_id, flow, 0, gaudPlcrCarxFlowIdNum[car_index]) + { + if(flow->vport == vport) + { + zxdh_plcr_remove_rate_limit(pf_dev, car_index, (uint32_t)flow_id); + + //clear vport mappings between car B and car C. + if(E_PLCR_CAR_B == car_index) + { + zxdh_plcr_clear_map(pf_dev, car_index, flow_id); + } + } + } + } + + zxdh_plcr_count_profiles(pf_dev); + + return 0; +} + +static uint32_t zxdh_vf_plcr_flowid_map(zxdh_msg_info *msg, zxdh_reps_info *reps, \ + DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev) +{ + int32_t rtn = 0; + uint32_t car_type = 0; + uint32_t flowid = 0; + uint32_t map_flowid = 0; + uint32_t map_sp = 0; + + /*提取消息中的参数字段*/ + car_type = msg->plcr_flowid_map_msg.car_type; + flowid = msg->plcr_flowid_map_msg.flowid; + map_flowid = msg->plcr_flowid_map_msg.map_flowid; + map_sp = msg->plcr_flowid_map_msg.sp; + + //前面的流程会判断是否需要进行映射，不会出现vf端口原来是非0group，现在会被group 0覆盖的情况 + PLCR_LOG_INFO("dpp_car_queue_map_set: pf_info->vport = 0x%x, car_type = %d, flowid = %d, map_flowid = %d\n", pf_info->vport, car_type, flowid, map_flowid); + rtn = dpp_car_queue_map_set(pf_info, car_type, flowid, map_flowid, map_sp); + PLCR_COMM_ASSERT(rtn); + + zxdh_plcr_stroe_map(pf_dev, car_type, flowid, map_flowid); + + return 0; +} + +static uint32_t zxdh_vf_plcr_mode_init(zxdh_msg_info *msg, zxdh_reps_info *reps, \ + DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev) +{ + int32_t rtn = 0; + + //set mode0 + rtn = zxdh_plcr_set_mode(pf_dev, msg->hdr.vport, E_RATE_LIMIT_MODE0); + + PLCR_COMM_ASSERT(rtn); + + return rtn; +} + +static uint32_t zxdh_vf_plcr_flow_init(zxdh_msg_info *msg, zxdh_reps_info *reps, \ + DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev) +{ + int rtn = 0; + uint32_t car_type; + uint32_t flowid; + uint32_t vf_idx; + uint32_t vport; + uint32_t vfid; + uint32_t map_flowid; + + car_type = msg->plcr_flow_init_msg.car_type; + flowid = msg->plcr_flow_init_msg.flowid; + pf_info->slot = pf_dev->slot_id; + pf_info->vport = pf_dev->vport; + + if (car_type == E_PLCR_CAR_C) + { + //对于carC flow的初始化，需检查目标group中num_vfs是否为0，确定其是否是本次移动前新建 + for (vf_idx = 0; vf_idx < pf_dev->num_vfs; vf_idx ++) + { + rtn = zxdh_plcr_get_vport_vfid(pf_dev, vf_idx, &vport, &vfid); + PLCR_COMM_ASSERT(rtn); + rtn = zxdh_plcr_get_next_map(pf_dev, E_PLCR_CAR_B, vfid * 2, &map_flowid); + PLCR_COMM_ASSERT(rtn); + if (!rtn && flowid == map_flowid) + { + PLCR_LOG_INFO("Group is currently being used by at least one VF\n"); + return 0; + } + } + } + PLCR_LOG_INFO("dpp_car_queue_cfg_set: vport = 0x%x, car_type = %d, flowid = %d, plcr_en = 0\n", + pf_dev->vport, car_type, flowid); + rtn = dpp_car_queue_cfg_set(pf_info, (uint32_t)car_type, flowid, DROP_DISABLE, PLCR_DISABLE, 0); + if (rtn) + PLCR_LOG_ERR("failed to call dpp_car_queue_cfg_set()\n"); + + return rtn; +} + +static uint32_t zxdh_vf_plcr_profile_id_add(zxdh_msg_info *msg, zxdh_reps_info *reps, \ + DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev) +{ + int32_t rtn = 0; + uint32_t car_type = 0; + uint16_t profile_id = 0; + + LOG_INFO("%s-%d:enter\n", __FUNCTION__, __LINE__); + /*1. 提取消息中的模板参数*/ + car_type = msg->vf_plcr_profile_id_add_msg.car_type; + + /*2. 申请新的profile*/ + rtn = zxdh_plcr_req_profile(pf_dev, car_type, &profile_id); + if (rtn) + { + LOG_ERR("%s-%d : failed !\n", __FUNCTION__, __LINE__); + return rtn; + } + + /*3. 返回消息*/ + reps->vf_plcr_profile_id_add_rsp.profile_id = profile_id; + + return 0; +} + +static uint32_t zxdh_vf_plcr_profile_id_delete(zxdh_msg_info *msg, zxdh_reps_info *reps, \ + DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev) +{ + int32_t rtn = 0; + uint32_t car_type = 0; + uint16_t profile_id = 0; + + LOG_INFO("%s-%d:enter\n", __FUNCTION__, __LINE__); + /*1. 提取消息中的模板参数*/ + car_type = msg->vf_plcr_profile_id_delete_msg.car_type; + profile_id = msg->vf_plcr_profile_id_delete_msg.profile_id; + + /*2. 限速模板使用计数-1：在下面的解除绑定zxdh_vf_plcr_queue_cfg_set()负责对使用计数-1*/ + + /*3. 释放限速模板资源*/ + rtn = zxdh_plcr_release_profile(pf_dev, car_type, profile_id); + if (rtn) + { + LOG_ERR("%s-%d : failed !\n", __FUNCTION__, __LINE__); + return rtn; + } + + /*4. 没有返回消息*/ + + return rtn; +} + +static uint32_t zxdh_vf_plcr_profile_cfg_set(zxdh_msg_info *msg, zxdh_reps_info *reps, \ + DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev) +{ + int32_t rtn = 0; + uint32_t car_type = 0; + uint32_t pkt_mode = 0; + uint16_t profile_id = 0; + uint32_t max_rate = 0; + uint32_t min_rate = 0; + struct xarray *xarray_profile = NULL; + struct zxdh_plcr_profile *plcr_profile = NULL; + union zxdh_plcr_profile_cfg profile_cfg; + + LOG_INFO("%s-%d:enter\n", __FUNCTION__, __LINE__); + /*1. 提取消息中的模板参数*/ + car_type = msg->vf_plcr_profile_cfg_set_msg.car_type; + pkt_mode = msg->vf_plcr_profile_cfg_set_msg.pkt_mode; + profile_id = msg->vf_plcr_profile_cfg_set_msg.profile_id; + + /*2. 校验外面的profile id和里面的profile id必须一致：限速模板联合体下包限速和字节限速结构体的前面2个成员是一样的（profile_id和pkt_sign）*/ + if(profile_id != msg->vf_plcr_profile_cfg_set_msg.profile_cfg.byte_profile_cfg.profile_id) + { + LOG_ERR("%s-%d : failed\n", __FUNCTION__, __LINE__); + return -EINVAL; + } + + /*3. 校验外面的pkt_mode和里面的pkt_sign必须一致：限速模板联合体下包限速和字节限速结构体的前面2个成员是一样的（profile_id和pkt_sign）*/ + if(pkt_mode != msg->vf_plcr_profile_cfg_set_msg.profile_cfg.byte_profile_cfg.pkt_sign) + { + LOG_ERR("%s-%d : failed\n", __FUNCTION__, __LINE__); + return -EINVAL; + } + + /*2. 获取profile*/ + xarray_profile = &(pf_dev->plcr_table.plcr_profiles[car_type]); + plcr_profile = xa_load(xarray_profile, profile_id); + + /*3. 包限速处理*/ + if(1 ==pkt_mode) + { + /*3.1 获取用户传递的字节限速模板参数*/ + profile_cfg.pkt_profile_cfg = msg->vf_plcr_profile_cfg_set_msg.profile_cfg.pkt_profile_cfg; + + /*3.2 包模式下直接使用限速模板里的包限速值*/ + max_rate = profile_cfg.pkt_profile_cfg.cir; + min_rate = profile_cfg.pkt_profile_cfg.cir; + + /*3.2 将限速模板的参数，配置到寄存器中去：包限速模板和字节限速模板前面2个成员profile_id和pkt_sign一样，保证了下面接口可以兼容包和字节限速配置*/ + rtn = zxdh_plcr_cfg_profile(pf_dev, car_type, &profile_cfg.byte_profile_cfg); + if (rtn) + { + LOG_ERR("%s-%d : failed\n", __FUNCTION__, __LINE__); + return -EINVAL; + } + } + /*4. 字节限速处理*/ + else + { + /*4.1 获取用户传递的字节限速模板参数*/ + profile_cfg.byte_profile_cfg = msg->vf_plcr_profile_cfg_set_msg.profile_cfg.byte_profile_cfg; + + /*4.2 将寄存器中的配置值，转换成用户限速值（单位：Mbit/s）*/ + max_rate = zxdh_plcr_reg_maxrate_user(profile_cfg.byte_profile_cfg.eir); + min_rate = zxdh_plcr_reg_maxrate_user(profile_cfg.byte_profile_cfg.cir); + + /*4.3 将限速模板的参数，配置到寄存器中去*/ + rtn = zxdh_plcr_cfg_profile(pf_dev, car_type, &profile_cfg.byte_profile_cfg); + if (rtn) + { + LOG_ERR("%s-%d : failed\n", __FUNCTION__, __LINE__); + return -EINVAL; + } + } + + /*5. 将限速模板参数保存到profile下面*/ + rtn = zxdh_plcr_store_profile(pf_dev, car_type, max_rate, min_rate, &profile_cfg.byte_profile_cfg); + if (rtn) + { + LOG_ERR("%s-%d : failed\n", __FUNCTION__, __LINE__); + return -EINVAL; + } + + /*6. 没有返回消息*/ + + return 0; +} + +static uint32_t zxdh_vf_plcr_profile_cfg_get(zxdh_msg_info *msg, zxdh_reps_info *reps, \ + DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev) +{ + int32_t rtn = 0; + uint32_t car_type = 0; + uint32_t pkt_mode = 0; + uint16_t profile_id = 0; + + LOG_INFO("%s-%d:enter\n", __FUNCTION__, __LINE__); + /*1. 提取消息中的模板参数*/ + car_type = msg->vf_plcr_profile_cfg_get_msg.car_type; + pkt_mode = msg->vf_plcr_profile_cfg_get_msg.pkt_mode; + profile_id = msg->vf_plcr_profile_cfg_get_msg.profile_id; + + /*2. 从寄存器中，获取限速模板的参数*/ + rtn = zxdh_plcr_get_profile(pf_dev, car_type, pkt_mode, profile_id, &reps->vf_plcr_profile_cfg_get_rsp.profile_cfg.byte_profile_cfg); + if (rtn) + { + LOG_ERR("%s-%d : failed to call zxdh_plcr_cfg_profile()\n", __FUNCTION__, __LINE__); + return rtn; + } + + /*3. 返回消息：上面已经填充好返回消息*/ + + return 0; +} + +static uint32_t zxdh_vf_plcr_queue_cfg_set(zxdh_msg_info *msg, zxdh_reps_info *reps, \ + DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev) +{ + int32_t rtn = 0; + uint32_t car_type = 0; + uint32_t drop_flag = 0; + uint32_t plcr_en = 0; + uint32_t flow_id = 0; + uint32_t profile_id = 0; + uint16_t vport = msg->hdr.vport; + struct xarray *xarray_profile = NULL; + struct zxdh_plcr_flow *plcr_flow = NULL; + struct zxdh_plcr_profile *plcr_profile = NULL; + + LOG_INFO("%s-%d:enter\n", __FUNCTION__, __LINE__); + LOG_INFO("%s-%d:vport = 0x%x\n", __FUNCTION__, __LINE__, vport); + + /*1. 提取消息中的模板参数*/ + car_type = msg->vf_plcr_queue_cfg_set_msg.car_type; + drop_flag = msg->vf_plcr_queue_cfg_set_msg.drop_flag; + plcr_en = msg->vf_plcr_queue_cfg_set_msg.plcr_en; + flow_id = msg->vf_plcr_queue_cfg_set_msg.flow_id; + profile_id = msg->vf_plcr_queue_cfg_set_msg.profile_id; + + /*2. 获取xarray中存储的profile*/ + xarray_profile = &(pf_dev->plcr_table.plcr_profiles[car_type]); + plcr_profile = xa_load(xarray_profile, profile_id); + if(NULL == plcr_profile) + { + LOG_ERR("%s-%d : failed\n", __FUNCTION__, __LINE__); + return -EINVAL; + } + + /*3. 绑定flow和profile*/ + if(PLCR_ENABLE == plcr_en) + { + /*3.1 申请flow结构体，并存储到xarray*/ + rtn = zxdh_plcr_req_flow(pf_dev, car_type, flow_id, &plcr_flow); + if (rtn) + { + LOG_ERR("%s-%d : kzalloc failed\n", __FUNCTION__, __LINE__); + return -EINVAL; + } + + /*3.2 更新flow信息*/ + zxdh_plcr_update_flow(plcr_flow, vport, plcr_profile->max_rate, plcr_profile->min_rate); + + /*3.3 更新flow信息*/ + plcr_flow->profile_id = profile_id; + + /*3.4 将flow与profile进行绑定*/ + rtn = dpp_car_queue_cfg_set(pf_info, car_type, flow_id, drop_flag, plcr_en, profile_id); + if (rtn) + { + LOG_ERR("%s-%d : failed to call dpp_car_queue_cfg_set()\n", __FUNCTION__, __LINE__); + + /*释放先前申请的flow*/ + zxdh_plcr_release_flow(pf_dev, car_type, flow_id); + return -EINVAL; + } + + /*3.4 模板使用计数+1*/ + zxdh_plcr_count_up_profile(pf_dev, car_type, profile_id); + } + /*4. 解除绑定flow和profile*/ + else + { + /*4.1 解除绑定flow与profile*/ + rtn = dpp_car_queue_cfg_set(pf_info, car_type, flow_id, drop_flag, plcr_en, profile_id); + if (rtn) + { + LOG_ERR("%s-%d : failed to call dpp_car_queue_cfg_set()\n", __FUNCTION__, __LINE__); + return -EINVAL; + } + + /*4.2 释放flow*/ + zxdh_plcr_release_flow(pf_dev, car_type, flow_id); + + /*4.3 模板使用计数-1*/ + zxdh_plcr_count_down_profile(pf_dev, car_type, profile_id); + } + + /*5. 没有返回消息*/ + + return 0; +} + +static uint32_t zxdh_vf_plcr_port_meter_stat_clr(zxdh_msg_info *msg, zxdh_reps_info *reps, \ + DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev) +{ + int32_t rtn = 0; + uint64_t pkB_cnt = 0; + uint64_t pk_cnt = 0; + + LOG_INFO("%s-%d:enter\n", __FUNCTION__, __LINE__); + /*1. dpp接口函数原型如下：mode = 1，表示读清零*/ + dpp_stat_plcr_packet_drop_tx_cnt_get(pf_info, msg->hdr.vf_id, 1, &pkB_cnt, &pk_cnt); + dpp_stat_plcr_packet_drop_rx_cnt_get(pf_info, msg->hdr.vf_id, 1, &pkB_cnt, &pk_cnt); + + /*2. 没有返回消息*/ + return rtn; +} + +static uint32_t zxdh_vf_plcr_port_meter_stat_get(zxdh_msg_info *msg, zxdh_reps_info *reps, \ + DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev) +{ + int32_t rtn = 0; + uint32_t direction = 0; + uint32_t is_clr = 0; + uint64_t *p_pkB_cnt = NULL; + uint64_t *p_pk_cnt = NULL; + + LOG_INFO("%s-%d:enter\n", __FUNCTION__, __LINE__); + /*1. 提取消息中的参数*/ + direction = msg->vf_plcr_port_meter_stat_get_msg.direction; + is_clr = msg->vf_plcr_port_meter_stat_get_msg.is_clr; + + /*2. 获取返回信息地址*/ + p_pkB_cnt = &(reps->vf_plcr_port_meter_stat_get_rsp.drop_pkB_cnt); + p_pk_cnt = &(reps->vf_plcr_port_meter_stat_get_rsp.drop_pk_cnt); + + /*2. 获取丢包统计*/ + if(1 == direction) + { + dpp_stat_plcr_packet_drop_tx_cnt_get(pf_info, msg->hdr.vf_id, is_clr, p_pkB_cnt, p_pk_cnt); + } + else + { + dpp_stat_plcr_packet_drop_rx_cnt_get(pf_info, msg->hdr.vf_id, is_clr, p_pkB_cnt, p_pk_cnt); + } + + /*3. 返回丢包统计值*/ + + return rtn; +} + +static uint32_t zxdh_vf_call_np_1588(zxdh_msg_info *msg, zxdh_reps_info *reps, \ + DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev) +{ + uint32_t vfid = msg->vf_1588_call_np.vfid; + uint32_t interface_num = msg->vf_1588_call_np.call_np_interface_num; + uint32_t opt = msg->vf_1588_call_np.ptp_tc_enable_opt; + + switch (interface_num) + { + case PTP_PORT_VFID_SET: + { + LOG_INFO("call dpp_ptp_port_vfid_set\n"); + dpp_ptp_port_vfid_set(pf_info, vfid); + break; + } + case PTP_TC_ENABLE_SET: + { + LOG_INFO("call dpp_ptp_tc_enable_set\n"); + dpp_ptp_tc_enable_set(pf_info, opt); + break; + } + default: + { + LOG_ERR("cannot found the interface_num %u\n", interface_num); + return -1; + } + } + + return 0; +} + +zxdh_vf_msg_proc vf_msg_proc[] = +{ + {ZXDH_VF_PORT_INIT, "vf_port_init", zxdh_vf_port_init}, + {ZXDH_VF_PORT_UNINIT, "vf_port_uninit", zxdh_vf_port_uninit}, + {ZXDH_MAC_ADD, "vf_all_mac_add", zxdh_vf_all_mac_add}, + {ZXDH_MAC_DEL, "vf_all_mac_del", zxdh_vf_all_mac_del}, + {ZXDH_IPV6_MAC_ADD, "vf_ipv6_mac_add", zxdh_vf_ipv6_mac_add}, + {ZXDH_IPV6_MAC_DEL, "vf_ipv6_mac_del", zxdh_vf_ipv6_mac_del}, + {ZXDH_MAC_GET, "vf_mac_get", zxdh_vf_mac_get}, + {ZXDH_RSS_EN_SET, "vf_rss_state_set", zxdh_vf_rss_state_set}, + {ZXDH_RXFH_SET, "vf_rxfh_set", zxdh_vf_rxfh_set}, + {ZXDH_RXFH_GET, "vf_rxfh_get", zxdh_vf_rxfh_get}, + {ZXDH_RXFH_DEL, "vf_rxfh_del", zxdh_vf_rxfh_del}, + {ZXDH_THASH_KEY_SET, "vf_thash_key_set", zxdh_vf_thash_key_set}, + {ZXDH_THASH_KEY_GET, "vf_thash_key_get", zxdh_vf_thash_key_get}, + {ZXDH_HASH_FUNC_SET, "vf_hash_funcs_set", zxdh_vf_hash_funcs_set}, + {ZXDH_RX_FLOW_HASH_SET, "vf_rx_flow_hash_set", zxdh_vf_rx_flow_hash_set}, + {ZXDH_RX_FLOW_HASH_GET, "vf_rx_flow_hash_get", zxdh_vf_rx_flow_hash_get}, + {ZXDH_PORT_ATTRS_SET, "vf_port_attrs_set", zxdh_vf_port_attrs_set}, + {ZXDH_PORT_ATTRS_GET, "vf_port_attrs_get", zxdh_vf_port_attrs_get}, + {ZXDH_PROMISC_SET, "vf_promisc_set", zxdh_vf_promisc_set}, + {ZXDH_VLAN_FILTER_SET, "vf_vlan_filter_set", zxdh_vf_vlan_filter_set}, + {ZXDH_VLAN_FILTER_ADD, "vf_rx_vid_add", zxdh_vf_rx_vid_add}, + {ZXDH_VLAN_FILTER_DEL, "vf_rx_vid_del", zxdh_vf_rx_vid_del}, + {ZXDH_GET_NP_STATS, "vf_np_stats_get", zxdh_vf_np_stats_get}, + {ZXDH_VF_RATE_LIMIT_SET, "vf_rate_limit_set", zxdh_vf_rate_limit_set}, + {ZXDH_PLCR_UNINIT, "vf_plcr_uninit", zxdh_vf_plcr_uninit}, + {ZXDH_MAP_PLCR_FLOWID, "vf_map_plcr_flowid", zxdh_vf_plcr_flowid_map}, + {ZXDH_PLCR_MODE_INIT, "vf_plcr_mode_init", zxdh_vf_plcr_mode_init}, + {ZXDH_PLCR_FLOW_INIT, "vf_plcr_flow_init", zxdh_vf_plcr_flow_init}, + {ZXDH_VLAN_OFFLOAD_SET, "vf_vlan_strip_set", zxdh_vf_vlan_strip_set}, + {ZXDH_SET_TPID, "vf_qinq_tpid_cfg", zxdh_vf_qinq_tpid_cfg}, + {ZXDH_PLCR_CAR_PROFILE_ID_ADD, "vf_plcr_profile_id_add", zxdh_vf_plcr_profile_id_add}, + {ZXDH_PLCR_CAR_PROFILE_ID_DELETE, "vf_plcr_profile_id_detele", zxdh_vf_plcr_profile_id_delete}, + {ZXDH_PLCR_CAR_PROFILE_CFG_SET, "vf_plcr_profile_cfg_set", zxdh_vf_plcr_profile_cfg_set}, + {ZXDH_PLCR_CAR_PROFILE_CFG_GET, "vf_plcr_profile_cfg_get", zxdh_vf_plcr_profile_cfg_get}, + {ZXDH_PLCR_CAR_QUEUE_CFG_SET, "vf_plcr_queue_cfg_set", zxdh_vf_plcr_queue_cfg_set}, + {ZXDH_PORT_METER_STAT_CLR, "vf_plcr_port_meter_stat_clr",zxdh_vf_plcr_port_meter_stat_clr}, + {ZXDH_PORT_METER_STAT_GET, "vf_plcr_port_meter_stat_get",zxdh_vf_plcr_port_meter_stat_get}, + {ZXDH_VF_1588_CALL_NP, "vf_1588_call_np", zxdh_vf_call_np_1588}, +}; + +int32_t dh_pf_msg_recv_func(void *pay_load, uint16_t len, void *reps_buffer, uint16_t *reps_len, void *dev) +{ + zxdh_msg_info *msg = (zxdh_msg_info *)pay_load; + zxdh_reps_info *reps = (zxdh_reps_info *)reps_buffer; + struct zxdh_pf_device *pf_dev = (struct zxdh_pf_device *)dev; + struct zxdh_vf_item *vf_item = NULL; + uint32_t ret = 0; + int32_t i = 0; + int32_t num = 0; + DPP_PF_INFO_T pf_info = {0}; + + if (pf_dev == NULL) + { + LOG_ERR("dev is NULL\n"); + return -1; + } + + LOG_DEBUG("vport: 0x%x\n", msg->hdr.vport); + pf_info.slot = pf_dev->slot_id; + pf_info.vport = msg->hdr.vport; + num = sizeof(vf_msg_proc)/sizeof(zxdh_vf_msg_proc); + vf_item = &pf_dev->vf_item[(msg->hdr.pcie_id & (0xff))]; + for (i = 0; i < num; i++) + { + *reps_len = sizeof(union zxdh_msg); + if (vf_msg_proc[i].op_code == msg->hdr.op_code) + { + LOG_INFO("%s is called", vf_msg_proc[i].proc_name); + ret = vf_msg_proc[i].msg_proc(msg, reps, &pf_info, vf_item, pf_dev); + if (ret != 0) + { + if (((msg->hdr.op_code == ZXDH_MAC_ADD)||(msg->hdr.op_code == ZXDH_IPV6_MAC_ADD)) && (ret == DPP_RC_TABLE_RANGE_INVALID)) + { + reps->flag = ZXDH_REPS_BEOND_MAC; + return -1; + } + reps->flag = ZXDH_REPS_FAIL; + LOG_ERR("%s failed, ret: %d\n", vf_msg_proc[i].proc_name, ret); + return -1; + } + + reps->flag = ZXDH_REPS_SUCC; + return 0; + } + } + + LOG_ERR("invalid op_code: [%u]\n", msg->hdr.op_code); + return -2; +} + +int32_t dh_pf_msg_recv_func_register(void) +{ + int32_t ret = 0; + + ret = zxdh_bar_chan_msg_recv_register(MODULE_VF_BAR_MSG_TO_PF, dh_pf_msg_recv_func); + if (ret != 0) + { + LOG_ERR("event_id[%d] register failed: %d\n", MODULE_VF_BAR_MSG_TO_PF, ret); + return ret; + } + + return ret; +} + +void dh_pf_msg_recv_func_unregister(void) +{ + zxdh_bar_chan_msg_recv_unregister(MODULE_VF_BAR_MSG_TO_PF); +} diff --git a/src/net/drivers/net/ethernet/dinghai/en_pf/msg_func.h b/src/net/drivers/net/ethernet/dinghai/en_pf/msg_func.h new file mode 100644 index 0000000..d54ccff --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_pf/msg_func.h @@ -0,0 +1,25 @@ +#ifndef __ZXDH_PF_MSG_FUNC_H__ +#define __ZXDH_PF_MSG_FUNC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +typedef enum +{ + PTP_PORT_VFID_SET, + PTP_TC_ENABLE_SET, + + MAX_VF_CALL_NP_NUM, +} vf_call_np_num; + +int32_t dh_pf_msg_recv_func_register(void); +void dh_pf_msg_recv_func_unregister(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __ZXDH_PF_MSG_FUNC_H__ */ diff --git a/src/net/drivers/net/ethernet/dinghai/en_pf/rdma.c b/src/net/drivers/net/ethernet/dinghai/en_pf/rdma.c new file mode 100755 index 0000000..e69de29 diff --git a/src/net/drivers/net/ethernet/dinghai/en_ptp/tod_driver.c b/src/net/drivers/net/ethernet/dinghai/en_ptp/tod_driver.c new file mode 100644 index 0000000..e58d6e8 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_ptp/tod_driver.c @@ -0,0 +1,437 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "tod_driver.h" +//#include "../msg_chan_driver/msg_chan_pub.h" +#include +#include "zxdh_ptp_common.h" + +static uint64_t virt_addr = 0; +static uint64_t pcie_id = 0; +static dev_t tod_device_no = 0; +static struct device *tod_device = NULL; +static struct file *tod_device_file = NULL; +static struct cdev *tod_device_cdev = NULL; +static struct class *tod_device_class = NULL; + +#define TOD_DEVICE_NAME "tod_device" + +int32_t tod_device_set_bar_virtual_addr(uint64_t virtaddr, uint16_t pcieid) +{ + virt_addr = virtaddr; + pcie_id = pcieid; + PTP_LOG_INFO("%s: bar msg virtaddr: 0x%llx\n", __FUNCTION__, virtaddr); + return 0; +} +EXPORT_SYMBOL(tod_device_set_bar_virtual_addr); + +static int32_t tod_device_sync_msg_send(uint8_t *req, uint32_t req_len, uint8_t *resp, uint32_t resp_len) +{ + int32_t result = 0; + uint32_t payload_len = 0; + struct zxdh_pci_bar_msg in = {0}; + struct zxdh_msg_recviver_mem out = {0}; + + if (req == NULL || req_len < 4) + { + PTP_LOG_ERR("%s: arg invalid, req: %px, req_len: %u.\n", __FUNCTION__, req, req_len); + return -EINVAL; + } + + out.buffer_len = 4 + 4 + resp_len; // 4B 消息头 + 4B result + resp_len实际应答消息 + out.recv_buffer = (uint8_t*)kmalloc(out.buffer_len, GFP_KERNEL); + if (out.recv_buffer == NULL) + { + PTP_LOG_ERR("%s: no space left on device.\n", __FUNCTION__); + return -ENOSPC; + } + memset(out.recv_buffer, 0, out.buffer_len); + + in.virt_addr = virt_addr; + in.event_id = MODULE_TOD; + in.src = MSG_CHAN_END_PF; + in.dst = MSG_CHAN_END_RISC; + in.payload_addr = req; + in.payload_len = req_len; + in.src_pcieid = pcie_id; + + if(zxdh_bar_chan_sync_msg_send(&in, &out) != BAR_MSG_OK) + { + kfree(out.recv_buffer); + PTP_LOG_ERR("%s: zxdh_bar_chan_sync_msg_send failed.\n", __FUNCTION__); + return -EINVAL; + } + + // 消息应答格式: header(4B) + payload(nB), payload最大2048 - 12 + // header格式: 0xFF(1B) + payload_len(2B) + rsv(1B) + // payload格式: result(4B) + msg((n - 4)B) + payload_len = *(uint16_t*)((uint8_t*)out.recv_buffer + 1); + if (payload_len < 4) + { + kfree(out.recv_buffer); + PTP_LOG_ERR("%s: payload_len: %u check failed.\n", __FUNCTION__, payload_len); + return -EINVAL; + } + + result = *(int32_t*)((uint8_t*)out.recv_buffer + 4); + if (result != 0) + { + kfree(out.recv_buffer); + PTP_LOG_ERR("%s: result: %d check failed.\n", __FUNCTION__, result); + return result; + } + + if (payload_len > 4 && resp != NULL) + { + memcpy(resp, out.recv_buffer + 8, (((payload_len - 4) > resp_len) ? resp_len : (payload_len - 4))); + } + + kfree(out.recv_buffer); + + return 0; +} + +static int tod_device_open(struct inode *inode, struct file *file) +{ + int32_t result = 0; + const char *device = "/dev/ttyAMA1"; + struct tod_device_msg msg; + + printk(KERN_INFO "%s.\n", __FUNCTION__); + + if (tod_device_file != NULL) + { + PTP_LOG_INFO("%s: device already open.\n", __FUNCTION__); + return 0; + } + + memset(&msg, 0x00, sizeof(struct tod_device_msg)); + msg.type = TOD_DEVICE_MSG_OPEN; + memcpy(msg.data, device, strlen(device) + 1); + + result = tod_device_sync_msg_send((uint8_t*)(&msg), sizeof(struct tod_device_msg), (uint8_t*)(&tod_device_file), sizeof(struct file*)); + if (result != 0) + { + tod_device_file = NULL; + printk(KERN_ERR "%s: tod_device_sync_msg_send failed, result: %d.\n", __FUNCTION__, result); + return -EINVAL; + } + PTP_LOG_INFO("%s: file %px open success.\n", __FUNCTION__, tod_device_file); + + return 0; +} + +static int tod_device_release(struct inode *inode, struct file *file) +{ + int32_t result = 0; + struct tod_device_msg msg; + + PTP_LOG_INFO("%s.\n", __FUNCTION__); + + if (tod_device_file == NULL) + { + PTP_LOG_ERR("%s: device already close.\n", __FUNCTION__); + return 0; + } + + memset(&msg, 0x00, sizeof(struct tod_device_msg)); + msg.type = TOD_DEVICE_MSG_CLOSE; + msg.file = tod_device_file; + + result = tod_device_sync_msg_send((uint8_t*)(&msg), sizeof(struct tod_device_msg), NULL, 0); + if (result != 0) + { + PTP_LOG_ERR("%s: tod_device_sync_msg_send failed, result: %d.\n", __FUNCTION__, result); + return -EINVAL; + } + PTP_LOG_INFO("%s: file %px close success.\n", __FUNCTION__, tod_device_file); + tod_device_file = NULL; + + return 0; +} + +static ssize_t tod_device_read(struct file *file, char *buf, size_t count, loff_t *f_pos) +{ + int32_t result = 0; + uint8_t *resp = NULL; + struct tod_device_msg msg; + + PTP_LOG_INFO("%s.\n", __FUNCTION__); + + if (tod_device_file == NULL) + { + PTP_LOG_ERR("%s: no such device.\n", __FUNCTION__); + return -ENODEV; + } + + if (count > (2048 - 12 - sizeof(int32_t) - sizeof(size_t))) // common bar: 2048 - 12, result: 4, count: 8. + { + PTP_LOG_ERR("%s: no space left on device.\n", __FUNCTION__); + return -ENOSPC; + } + + resp = (uint8_t*)kmalloc(sizeof(size_t) + count, GFP_KERNEL); + if (resp == NULL) + { + PTP_LOG_ERR("%s: no space left on device.\n", __FUNCTION__); + return -ENOSPC; + } + + memset(&msg, 0x00, sizeof(struct tod_device_msg)); + msg.type = TOD_DEVICE_MSG_READ; + msg.count = count; + msg.file = tod_device_file; + + result = tod_device_sync_msg_send((uint8_t*)(&msg), sizeof(struct tod_device_msg), resp, sizeof(size_t) + count); + if (result != 0) + { + kfree(resp); + PTP_LOG_ERR("%s: tod_device_sync_msg_send failed, result: %d.\n", __FUNCTION__, result); + return -EINVAL; + } + + count = *((size_t*)(resp)); + if (count > msg.count) + { + PTP_LOG_ERR("%s: no space left on device.\n", __FUNCTION__); + kfree(resp); + return -ENOSPC; + } + + result = copy_to_user(buf, resp + sizeof(size_t), count); + if (result != 0) + { + kfree(resp); + PTP_LOG_ERR("%s: copy_to_user failed, result: %d.\n", __FUNCTION__, result); + return -EINVAL; + } + + kfree(resp); + PTP_LOG_INFO("%s: file %px read %lu bytes success.\n", __FUNCTION__, tod_device_file, count); + + return count; +} + +static ssize_t tod_device_write(struct file *file, const char *buf, size_t count, loff_t *f_pos) +{ + int32_t result = 0; + struct tod_device_msg msg; + + PTP_LOG_INFO("%s.\n", __FUNCTION__); + + if (tod_device_file == NULL) + { + PTP_LOG_ERR("%s: no such device.\n", __FUNCTION__); + return -ENODEV; + } + + if (count > sizeof(msg.data)) + { + PTP_LOG_ERR("%s: no space left on device.\n", __FUNCTION__); + return -ENOSPC; + } + + memset(&msg, 0x00, sizeof(struct tod_device_msg)); + msg.type = TOD_DEVICE_MSG_WRITE; + msg.count = count; + msg.file = tod_device_file; + result = copy_from_user(msg.data, buf, count); + if (result != 0) + { + PTP_LOG_ERR("%s: copy_from_user failed, result: %d.\n", __FUNCTION__, result); + return -EINVAL; + } + + result = tod_device_sync_msg_send((uint8_t*)(&msg), sizeof(struct tod_device_msg), (uint8_t*)(&count), sizeof(size_t)); + if (result != 0) + { + PTP_LOG_ERR("%s: tod_device_sync_msg_send failed, result: %d.\n", __FUNCTION__, result); + return -EINVAL; + } + PTP_LOG_INFO("%s: file %px write %lu bytes success.\n", __FUNCTION__, tod_device_file, count); + + return count; +} + +static __poll_t tod_device_poll(struct file *file, struct poll_table_struct *wait) +{ + int32_t result = 0; + uint16_t poll_mask = 0; + struct tod_device_msg msg; + + PTP_LOG_INFO("%s.\n", __FUNCTION__); + + if (tod_device_file == NULL) + { + PTP_LOG_ERR("%s: no such device.\n", __FUNCTION__); + return POLLERR; + } + + memset(&msg, 0x00, sizeof(struct tod_device_msg)); + msg.type = TOD_DEVICE_MSG_POLL; + msg.file = tod_device_file; + + result = tod_device_sync_msg_send((uint8_t*)(&msg), sizeof(struct tod_device_msg), (uint8_t*)(&poll_mask), sizeof(uint16_t)); + if (result != 0) + { + PTP_LOG_ERR("%s: tod_device_sync_msg_send failed, result: %d.\n", __FUNCTION__, result); + return POLLERR; + } + PTP_LOG_INFO("%s: file %px poll mask 0x%04x success.\n", __FUNCTION__, tod_device_file, poll_mask); + + return poll_mask; +} + +static long tod_device_ioctl(struct file *file, uint32_t request, unsigned long args) +{ + int32_t result = 0; + uint8_t *resp = NULL; + struct tod_device_msg msg; + + PTP_LOG_INFO("%s.\n", __FUNCTION__); + + if (tod_device_file == NULL) + { + PTP_LOG_ERR("%s: no such device.\n", __FUNCTION__); + return -ENODEV; + } + + resp = (uint8_t*)kmalloc(sizeof(struct termios), GFP_KERNEL); + if (resp == NULL) + { + PTP_LOG_ERR("%s: no space left on device.\n", __FUNCTION__); + return -ENOSPC; + } + + memset(&msg, 0x00, sizeof(struct tod_device_msg)); + msg.type = TOD_DEVICE_MSG_IOCTL; + msg.file = tod_device_file; + msg.command = request; + + if ((struct termios*)args != NULL) + { + result = copy_from_user(msg.data, (uint8_t*)args, sizeof(struct termios)); + if (result != 0) + { + PTP_LOG_ERR("%s: copy_from_user failed, result: %d.\n", __FUNCTION__, result); + kfree(resp); + return -EINVAL; + } + } + + result = tod_device_sync_msg_send((uint8_t*)(&msg), sizeof(struct tod_device_msg), resp, sizeof(struct termios)); + if (result != 0) + { + kfree(resp); + PTP_LOG_ERR("%s: tod_device_sync_msg_send failed, result: %d.\n", __FUNCTION__, result); + return -EINVAL; + } + + if ((struct termios*)args != NULL) + { + result = copy_to_user((uint8_t*)args, resp, sizeof(struct termios)); + if (result != 0) + { + kfree(resp); + PTP_LOG_ERR("%s: copy_to_user failed, result: %d.\n", __FUNCTION__, result); + return -EINVAL; + } + } + + kfree(resp); + PTP_LOG_INFO("%s: file %px ioctl success.\n", __FUNCTION__, tod_device_file); + + return 0; +} + +struct file_operations tod_device_ops = { + .owner = THIS_MODULE, + .open = tod_device_open, + .release = tod_device_release, + .read = tod_device_read, + .write = tod_device_write, + .poll = tod_device_poll, + .unlocked_ioctl = tod_device_ioctl +}; + +static int32_t __init tod_device_init(void) +{ + int32_t result = 0; + + PTP_LOG_INFO("%s: start.\n", __FUNCTION__); + + result = alloc_chrdev_region(&tod_device_no, 0, 1, TOD_DEVICE_NAME); + if (result < 0) + { + PTP_LOG_ERR("%s: alloc_chrdev_region failed, result: %d.\n", __FUNCTION__, result); + return -EINVAL; + } + + tod_device_cdev = cdev_alloc(); + if (tod_device_cdev == NULL) + { + PTP_LOG_ERR("%s: cdev_alloc failed, result: %d.\n", __FUNCTION__, result); + unregister_chrdev_region(tod_device_no, 1); + return -EINVAL; + } + + cdev_init(tod_device_cdev, &tod_device_ops); + tod_device_cdev->owner = THIS_MODULE; + result = cdev_add(tod_device_cdev, tod_device_no, 1); + if (result != 0) + { + PTP_LOG_ERR("%s: cdev_add failed, result: %d.\n", __FUNCTION__, result); + unregister_chrdev_region(tod_device_no, 1); + return -EINVAL; + } + + tod_device_class = class_create(THIS_MODULE, TOD_DEVICE_NAME); + if (IS_ERR(tod_device_class)) + { + PTP_LOG_ERR("%s: class_create failed, err: %lu.\n", __FUNCTION__, PTR_ERR(tod_device_class)); + cdev_del(tod_device_cdev); + unregister_chrdev_region(tod_device_no, 1); + return -EINVAL; + } + + tod_device = device_create(tod_device_class, NULL, tod_device_no, NULL, TOD_DEVICE_NAME); + if (IS_ERR(tod_device)) + { + PTP_LOG_ERR("%s: device_create failed, err: %lu.\n", __FUNCTION__, PTR_ERR(tod_device)); + class_destroy(tod_device_class); + cdev_del(tod_device_cdev); + unregister_chrdev_region(tod_device_no, 1); + return -EINVAL; + } + + PTP_LOG_INFO("%s: success.\n", __FUNCTION__); + + return 0; +} + +static void __exit tod_device_exit(void) +{ + PTP_LOG_INFO("%s: start.\n", __FUNCTION__); + + device_destroy(tod_device_class, tod_device_no); + + class_destroy(tod_device_class); + + cdev_del(tod_device_cdev); + + unregister_chrdev_region(tod_device_no, 1); + + PTP_LOG_ERR("%s: success.\n", __FUNCTION__); +} + +module_init(tod_device_init); +module_exit(tod_device_exit); + +MODULE_LICENSE("GPL"); diff --git a/src/net/drivers/net/ethernet/dinghai/en_ptp/tod_driver.h b/src/net/drivers/net/ethernet/dinghai/en_ptp/tod_driver.h new file mode 100644 index 0000000..b02f70a --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_ptp/tod_driver.h @@ -0,0 +1,24 @@ +#ifndef _TOD_DRIVER_H_ +#define _TOD_DRIVER_H_ + +#include + +#define TOD_DEVICE_MSG_OPEN ((uint32_t)(0)) +#define TOD_DEVICE_MSG_CLOSE ((uint32_t)(1)) +#define TOD_DEVICE_MSG_READ ((uint32_t)(2)) +#define TOD_DEVICE_MSG_WRITE ((uint32_t)(3)) +#define TOD_DEVICE_MSG_POLL ((uint32_t)(4)) +#define TOD_DEVICE_MSG_IOCTL ((uint32_t)(5)) + +#define TOD_DEVICE_DATA_LEN ((uint32_t)(512)) + +struct tod_device_msg +{ + uint32_t type; + uint32_t command; + size_t count; + void* file; + uint8_t data[TOD_DEVICE_DATA_LEN]; +}; + +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/en_ptp/tod_driver_stub.c b/src/net/drivers/net/ethernet/dinghai/en_ptp/tod_driver_stub.c new file mode 100644 index 0000000..890efa5 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_ptp/tod_driver_stub.c @@ -0,0 +1,62 @@ +#include +//#include "../msg_chan_driver/msg_chan_pub.h" +#include +#if 0 +typedef uint16_t (*rsc_recv_func_ptr)(uint8_t *pay_load, uint16_t len, uint8_t *reps_buffer, uint16_t *reps_len); + +static rsc_recv_func_ptr g_riscv_event[100] = {0}; + +uint16_t RSC_MsgProRegister(uint8_t event_id, rsc_recv_func_ptr msg_pro_fun) +{ + if(100 <= event_id) + return 0; + g_riscv_event[event_id] = msg_pro_fun; + return 0; +} +EXPORT_SYMBOL(RSC_MsgProRegister); + +uint16_t RSC_MsgProUnregister(uint8_t event_id) +{ + if(100 <= event_id) + return 0; + g_riscv_event[event_id] = NULL; + return 0; +} +EXPORT_SYMBOL(RSC_MsgProUnregister); + + +// int zxdh_bar_chan_sync_msg_send(struct zxdh_pci_bar_msg *in, struct zxdh_msg_recviver_mem *result) +// { +// uint16_t reps_len = 0; +// uint8_t *reps_buffer = NULL; +// rsc_recv_func_ptr ptr = NULL; + +// reps_buffer = (uint8_t*)kmalloc(2048 - 12 + 4, GFP_KERNEL); +// if (reps_buffer == NULL) +// { +// printk(KERN_ERR "%s: no space left on device.\n", __FUNCTION__); +// return -ENOSPC; +// } +// memset(reps_buffer, 0x00, 2048 - 12 + 4); // 消息应答净荷长度最大2048 - 12, 再加上4B消息头 + +// ptr = g_riscv_event[in->event_id]; +// if (ptr(in->payload_addr, in->payload_len, reps_buffer + 4, &reps_len) != 0) +// { +// kfree(reps_buffer); +// printk(KERN_ERR "%s: rsc_recv_func_ptr failed.\n", __FUNCTION__); +// return -EINVAL; +// } + +// *(uint8_t*)reps_buffer = 0xFF; +// *(uint16_t*)((((uint8_t*)reps_buffer )+ 1)) = reps_len; + +// memcpy(result->recv_buffer, reps_buffer, result->buffer_len); + +// kfree(reps_buffer); + +// return 0; +// } +// EXPORT_SYMBOL(zxdh_bar_chan_sync_msg_send); + +MODULE_LICENSE("GPL"); +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/en_ptp/zxdh_ptp.c b/src/net/drivers/net/ethernet/dinghai/en_ptp/zxdh_ptp.c new file mode 100644 index 0000000..7724802 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_ptp/zxdh_ptp.c @@ -0,0 +1,1477 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "en_aux.h" +#include "zxdh_ptp.h" +#include "zxdh_ptp_regs.h" +#include "zxdh_ptp_common.h" + +#define ZXDH_PF_BAR0 0 + +char pps[3][15] = { + "pp1s_out", + "pp1s_1588", + "pp1s_external" +}; + +// all tsn timer name: tsn0 tsn1 tsn2 tsn3, so the return value is 0/1/2/3. +static int get_tsn_timer_no(char *clock_name) +{ + int ret; + int timer_no; + ret = sscanf(clock_name, "tsn%d", &timer_no); + if(ret != 1) + { + PTP_LOG_INFO(" tsn: %s get timer no fail!\n", clock_name); + return -1; + } + return timer_no; +} + +static uint32_t tsn_clock_cycle_integer_reg(int timer_no) +{ + if (0 == timer_no) + return TSN_CLOCK_CYCLE_INTEGER(0); + else if (1 == timer_no) + return TSN_CLOCK_CYCLE_INTEGER(1); + else if (2 == timer_no) + return TSN_CLOCK_CYCLE_INTEGER(2); + else if (3 == timer_no) + return TSN_CLOCK_CYCLE_INTEGER(3); + + return 0; +} + +static uint32_t tsn_clock_cycle_fraction_reg(int timer_no) +{ + if (0 == timer_no) + return TSN_CLOCK_CYCLE_FRACTION(0); + else if (1 == timer_no) + return TSN_CLOCK_CYCLE_FRACTION(1); + else if (2 == timer_no) + return TSN_CLOCK_CYCLE_FRACTION(2); + else if (3 == timer_no) + return TSN_CLOCK_CYCLE_FRACTION(3); + + return 0; +} + +#define GET_TSN_ADJUST_NANO_REG(tsn_no) \ + ({ \ + if (0 == tsn_no) \ + nano_sec_reg = TSN_ADJUST_NANO_SEC(0); \ + else if (1 == tsn_no) \ + nano_sec_reg = TSN_ADJUST_NANO_SEC(1); \ + else if (2 == tsn_no) \ + nano_sec_reg = TSN_ADJUST_NANO_SEC(2); \ + else if (3 == tsn_no) \ + nano_sec_reg = TSN_ADJUST_NANO_SEC(3); \ + }) + +#define GET_TSN_ADJUST_LOW_SEC_REG(tsn_no) \ + ({ \ + if (0 == tsn_no) \ + low_sec_reg = TSN_ADJUST_LOW_SECOND(0); \ + else if (1 == tsn_no) \ + low_sec_reg = TSN_ADJUST_LOW_SECOND(1); \ + else if (2 == tsn_no) \ + low_sec_reg = TSN_ADJUST_LOW_SECOND(2); \ + else if (3 == tsn_no) \ + low_sec_reg = TSN_ADJUST_LOW_SECOND(3); \ + }) + +#define GET_TSN_ADJUST_HIGH_SEC_REG(tsn_no) \ + ({ \ + if (0 == tsn_no) \ + high_sec_reg = TSN_ADJUST_HIGH_SECOND(0); \ + else if (1 == tsn_no) \ + high_sec_reg = TSN_ADJUST_HIGH_SECOND(1); \ + else if (2 == tsn_no) \ + high_sec_reg = TSN_ADJUST_HIGH_SECOND(2); \ + else if (3 == tsn_no) \ + high_sec_reg = TSN_ADJUST_HIGH_SECOND(3); \ + }) + +#define GET_TSN_ADJUST_FRAC_NANO_SEC_REG(tsn_no) \ + ({ \ + if (0 == tsn_no) \ + frac_nano_reg = TSN_ADJUST_FRAC_NANO_SEC(0); \ + else if (1 == tsn_no) \ + frac_nano_reg = TSN_ADJUST_FRAC_NANO_SEC(1); \ + else if (2 == tsn_no) \ + frac_nano_reg = TSN_ADJUST_FRAC_NANO_SEC(2); \ + else if (3 == tsn_no) \ + frac_nano_reg = TSN_ADJUST_FRAC_NANO_SEC(3); \ + }) + +#define GET_TSN_LATCH_NANO_REG(tsn_no) \ + ({ \ + if (0 == tsn_no) \ + nano_sec_reg = TSN_LATCH_NANO_SEC(0); \ + else if (1 == tsn_no) \ + nano_sec_reg = TSN_LATCH_NANO_SEC(1); \ + else if (2 == tsn_no) \ + nano_sec_reg = TSN_LATCH_NANO_SEC(2); \ + else if (3 == tsn_no) \ + nano_sec_reg = TSN_LATCH_NANO_SEC(3); \ + }) + +#define GET_TSN_LATCH_LOW_SEC_REG(tsn_no) \ + ({ \ + if (0 == tsn_no) \ + low_sec_reg = TSN_LATCH_LOW_SECOND(0); \ + else if (1 == tsn_no) \ + low_sec_reg = TSN_LATCH_LOW_SECOND(1); \ + else if (2 == tsn_no) \ + low_sec_reg = TSN_LATCH_LOW_SECOND(2); \ + else if (3 == tsn_no) \ + low_sec_reg = TSN_LATCH_LOW_SECOND(3); \ + }) + +#define GET_TSN_LATCH_HIGH_SEC_REG(tsn_no) \ + ({ \ + if (0 == tsn_no) \ + high_sec_reg = TSN_LATCH_HIGH_SECOND(0); \ + else if (1 == tsn_no) \ + high_sec_reg = TSN_LATCH_HIGH_SECOND(1); \ + else if (2 == tsn_no) \ + high_sec_reg = TSN_LATCH_HIGH_SECOND(2); \ + else if (3 == tsn_no) \ + high_sec_reg = TSN_LATCH_HIGH_SECOND(3); \ + }) + +#define GET_TSN_LATCH_FRAC_NANO_SEC_REG(tsn_no) \ + ({ \ + if (0 == tsn_no) \ + frac_nano_reg = TSN_LATCH_FRAC_NANO_SEC(0); \ + else if (1 == tsn_no) \ + frac_nano_reg = TSN_LATCH_FRAC_NANO_SEC(1); \ + else if (2 == tsn_no) \ + frac_nano_reg = TSN_LATCH_FRAC_NANO_SEC(2); \ + else if (3 == tsn_no) \ + frac_nano_reg = TSN_LATCH_FRAC_NANO_SEC(3); \ + }) + +#define GET_PPS_LATCH_TSN_NANO_REG(tsn_no) \ + ({ \ + if (1 == tsn_no) \ + nano_sec_reg = PPS_LATCH_TSN_NANO_SEC(0); \ + else if (2 == tsn_no) \ + nano_sec_reg = PPS_LATCH_TSN_NANO_SEC(1); \ + else if (3 == tsn_no) \ + nano_sec_reg = PPS_LATCH_TSN_NANO_SEC(2); \ + else if (4 == tsn_no) \ + nano_sec_reg = PPS_LATCH_TSN_NANO_SEC(3); \ + }) + +#define GET_PPS_LATCH_TSN_LOW_SEC_REG(tsn_no) \ + ({ \ + if (1 == tsn_no) \ + low_sec_reg = PPS_LATCH_TSN_LOW_SECOND(0); \ + else if (2 == tsn_no) \ + low_sec_reg = PPS_LATCH_TSN_LOW_SECOND(1); \ + else if (3 == tsn_no) \ + low_sec_reg = PPS_LATCH_TSN_LOW_SECOND(2); \ + else if (4 == tsn_no) \ + low_sec_reg = PPS_LATCH_TSN_LOW_SECOND(3); \ + }) + +#define GET_PPS_LATCH_TSN_HIGH_SEC_REG(tsn_no) \ + ({ \ + if (1 == tsn_no) \ + high_sec_reg = PPS_LATCH_TSN_HIGH_SECOND(0); \ + else if (2 == tsn_no) \ + high_sec_reg = PPS_LATCH_TSN_HIGH_SECOND(1); \ + else if (3 == tsn_no) \ + high_sec_reg = PPS_LATCH_TSN_HIGH_SECOND(2); \ + else if (4 == tsn_no) \ + high_sec_reg = PPS_LATCH_TSN_HIGH_SECOND(3); \ + }) + +#define GET_PPS_LATCH_TSN_FRAC_NANO_SEC_REG(tsn_no) \ + ({ \ + if (1 == tsn_no) \ + frac_nano_reg = PPS_LATCH_TSN_FRAC_NANO_SEC(0); \ + else if (2 == tsn_no) \ + frac_nano_reg = PPS_LATCH_TSN_FRAC_NANO_SEC(1); \ + else if (3 == tsn_no) \ + frac_nano_reg = PPS_LATCH_TSN_FRAC_NANO_SEC(2); \ + else if (4 == tsn_no) \ + frac_nano_reg = PPS_LATCH_TSN_FRAC_NANO_SEC(3); \ + }) + +enum reg_module +{ + PTP_TOP, + PTP_M, + PTP_S0, + PTP_S1, + PTP_S2, +}; + +static inline uint32_t zxdh_read_reg(uint64_t base_addr, uint32_t offset) +{ + return readl((const volatile void *)(base_addr + offset)); +} + +static inline void zxdh_write_reg(uint64_t base_addr, uint32_t offset, uint32_t val) +{ + writel(val, (volatile void *)(base_addr + offset)); +} + +static uint64_t zxdh_ptp_get_bar_addr(struct zxdh_ptp_private *adapter) +{ + struct zxdh_pf_device *pf_dev = adapter->pdev; + return pf_dev->pci_ioremap_addr[0]; +} + +static struct zxdh_ptp_private* zxdh_ptp_get_ptp_private(struct zxdh_en_device *en_dev) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(en_dev->parent->parent); + return pf_dev->ptp; +} +/** + * zx_ptp_adjfreq - adjust ptp cycle frequency + * @ptp: the ptp clock structure + * @ppb: parts per billion adjustment from base + * + */ +static int zx_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb) +{ + unsigned long flags; + int neg_adj = 0; + uint32_t cur_nano, cur_frac_nano; + uint64_t tmp_frac_nano; + uint64_t base_addr; + uint64_t bar_addr; + uint64_t freq_adj; + struct zxdh_ptp_private *adapter = container_of(ptp, struct zxdh_ptp_private, ptp_caps[0]); + + PTP_LOG_INFO("name: %s, ppb: %d\n", ptp->name, ppb); + + if (ppb == 0) + return 0; + + if (ppb < 0) + { + ppb = -ppb; + neg_adj = 1; + } + bar_addr = zxdh_ptp_get_bar_addr(adapter); + + base_addr = bar_addr + PTP_HOST_BAR_OFFSET + PTPM_OFFSET_WITH_TOP; + cur_nano = zxdh_read_reg(base_addr, PTP_CLOCK_CYCLE_INTEGER); + cur_frac_nano = zxdh_read_reg(base_addr, PTP_CLOCK_CYCLE_FRACTION); + + tmp_frac_nano = ((unsigned long long)cur_nano << 32) + cur_frac_nano; + + PTP_LOG_INFO("cur_nano: %u, cur_frac_nano: %u, tmp_frac_nano: 0x%llx\n", cur_nano, cur_frac_nano, + tmp_frac_nano); + + /* positive adjust */ + if (0 == neg_adj) + { + tmp_frac_nano += tmp_frac_nano * ppb / 1000000000; + } + else /* negative adjust */ + { + freq_adj = tmp_frac_nano * ppb / 1000000000; + if(tmp_frac_nano > freq_adj) + tmp_frac_nano -= freq_adj; + } + PTP_LOG_INFO("new tmp_frac_nano: 0x%llx\n", tmp_frac_nano); + cur_nano = (uint32_t)(tmp_frac_nano >> 32); + cur_frac_nano = tmp_frac_nano & 0xffffffff; + + PTP_LOG_INFO("cur_nano: %u, cur_frac_nano: %u\n", cur_nano, cur_frac_nano); + spin_lock_irqsave(&adapter->tmreg_lock, flags); + + zxdh_write_reg(base_addr, PTP_CLOCK_CYCLE_INTEGER, cur_nano); + zxdh_write_reg(base_addr, PTP_CLOCK_CYCLE_FRACTION, cur_frac_nano); + zxdh_write_reg(base_addr, CLOCK_CYCLE_UPDATE, 1); + + spin_unlock_irqrestore(&adapter->tmreg_lock, flags); + + return 0; +} + + +static int zxdh_ptp_adjtime(struct ptp_clock_info *ptp_clock, s64 delta) +{ + unsigned long flags; + uint32_t run_mode; + uint32_t reg_val; + uint64_t adjust; + // s32 rem; + uint64_t sec; + uint32_t nsec; + + uint64_t base_addr; + uint64_t bar_addr; + struct zxdh_ptp_private *adapter; + PTP_LOG_INFO("name: %s, delta: %lld\n", ptp_clock->name, delta); + + adapter = container_of(ptp_clock, struct zxdh_ptp_private, ptp_caps[0]); + bar_addr = zxdh_ptp_get_bar_addr(adapter); + + base_addr = bar_addr + PTP_HOST_BAR_OFFSET + PTPM_OFFSET_WITH_TOP; + + spin_lock_irqsave(&adapter->tmreg_lock, flags); + // timecounter_adjtime(&adapter->tc, delta); + + /* 1588 timer, update mode */ + if (delta > 0) + { + run_mode = INCRE_MODE; + adjust = delta; + } + else + { + run_mode = DECRE_MODE; + adjust = -delta; + } + + /* adjust value */ + sec = div_u64_rem(adjust, NSEC_PER_SEC, &nsec); + PTP_LOG_INFO("sec: %llu, nsec: %u\n", sec, nsec); + // nsec = rem; + zxdh_write_reg(base_addr, ADJUST_HIGH_TOD_SECOND, (uint32_t)(sec >> 32)); + zxdh_write_reg(base_addr, ADJUST_LOWER_TOD_SECOND, (uint32_t)(sec & 0xffffffff)); + zxdh_write_reg(base_addr, ADJUST_TOD_NANO_SECOND, nsec); + + reg_val = zxdh_read_reg(base_addr, PTP_CONFIGURATION); + reg_val &= ~(0x3 << 4); + reg_val |= run_mode << 4 | 1 << TIMER_1588_UPT_EN_BIT; + zxdh_write_reg(base_addr, PTP_CONFIGURATION, reg_val); + + /* enable adjust */ + zxdh_write_reg(base_addr, TIMER_CONTROL, 1 << 1); + + spin_unlock_irqrestore(&adapter->tmreg_lock, flags); + + return 0; +} + + +static int zxdh_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts) +{ + uint32_t ns; + uint64_t s; + uint32_t reg_val; + unsigned long flags; + + uint64_t base_addr; + struct zxdh_ptp_private *adapter = container_of(ptp, struct zxdh_ptp_private, ptp_caps[0]); + uint64_t bar_addr = zxdh_ptp_get_bar_addr(adapter); + PTP_LOG_INFO("name: %s\n", ptp->name); + + base_addr = bar_addr + PTP_HOST_BAR_OFFSET + PTPM_OFFSET_WITH_TOP; + + mutex_lock(&adapter->ptp_clk_mutex); + spin_lock_irqsave(&adapter->tmreg_lock, flags); + + // normal mode. + reg_val = zxdh_read_reg(base_addr, PTP_CONFIGURATION); + reg_val &= ~(0x3 << PPS_RUN_MODE_BIT); + reg_val |= NORMAL_MODE << PPS_RUN_MODE_BIT; + zxdh_write_reg(base_addr, PTP_CONFIGURATION, reg_val); + zxdh_write_reg(base_addr, TIMER_LACTH_SEL, 1 << LATCH_1588_TIMER); + zxdh_write_reg(base_addr, TIMER_LATCH_EN, 1); + + ns = zxdh_read_reg(base_addr, LATCH_TOD_NANO_SECOND); + s = zxdh_read_reg(base_addr, LATCH_LOWER_TOD_SECOND); + s |= (uint64_t)zxdh_read_reg(base_addr, LATCH_HIGH_TOD_SECOND) << 32; + + spin_unlock_irqrestore(&adapter->tmreg_lock, flags); + mutex_unlock(&adapter->ptp_clk_mutex); + + // *ts = ns_to_timespec64(ns); + ts->tv_sec = s; + ts->tv_nsec = ns; + PTP_LOG_INFO("kernel get clock time: %lld.%09ld\n", ts->tv_sec, ts->tv_nsec); + + return 0; +} + +static int zxdh_ptp_settime(struct ptp_clock_info *ptp, const struct timespec64 *ts) +{ + unsigned long flags; + uint32_t reg_val; + + uint64_t base_addr; + struct zxdh_ptp_private *adapter = container_of(ptp, struct zxdh_ptp_private, ptp_caps[0]); + + uint64_t bar_addr = zxdh_ptp_get_bar_addr(adapter); + PTP_LOG_INFO("name: %s, sec: %lld, nsec: %ld\n", ptp->name, ts->tv_sec, ts->tv_nsec); + + base_addr = bar_addr + PTP_HOST_BAR_OFFSET + PTPM_OFFSET_WITH_TOP; + + mutex_lock(&adapter->ptp_clk_mutex); + + spin_lock_irqsave(&adapter->tmreg_lock, flags); + + /* adjust value */ + zxdh_write_reg(base_addr, ADJUST_HIGH_TOD_SECOND, (uint32_t)(ts->tv_sec >> 32) & 0xffff); + zxdh_write_reg(base_addr, ADJUST_LOWER_TOD_SECOND, (uint32_t)(ts->tv_sec & 0xffffffff)); + zxdh_write_reg(base_addr, ADJUST_TOD_NANO_SECOND, ts->tv_nsec); + + /* 1588 timer, update mode */ + reg_val = zxdh_read_reg(base_addr, PTP_CONFIGURATION); + reg_val &= ~(0x3 << 4); + reg_val |= UPDATE_MODE << 4 | 1 << TIMER_1588_UPT_EN_BIT; + zxdh_write_reg(base_addr, PTP_CONFIGURATION, reg_val); + + /* enable adjust */ + zxdh_write_reg(base_addr, TIMER_CONTROL, 1 << 1); + + spin_unlock_irqrestore(&adapter->tmreg_lock, flags); + mutex_unlock(&adapter->ptp_clk_mutex); + + return 0; +} + +#if 0 +static int zxdh_ptp_enable_pps(struct zxdh_ptp_private *adapter, int on) +{ + uint32_t reg_val = 0; + uint64_t base_addr; + + uint64_t bar_addr = zxdh_ptp_get_bar_addr(adapter); + + base_addr = bar_addr + PTP_HOST_BAR_OFFSET + PTPM_OFFSET_WITH_TOP; + + // bit14 enable ptp pps output + reg_val = zxdh_read_reg(base_addr, PTP_CONFIGURATION); + reg_val &= ~(1 << 14); + reg_val |= on << 14; + zxdh_write_reg(base_addr, PTP_CONFIGURATION, reg_val); + return 0; +} +#endif +/** + * zxdh_ptp_enable + * @ptp: the ptp clock structure + * @rq: the requested feature to change + * @on: whether to enable or disable the feature + * + */ +static int zxdh_ptp_enable(struct ptp_clock_info *ptp, struct ptp_clock_request *rq, int on) +{ +#if 1 + PTP_LOG_INFO("name: %s, rq->type: %d\n", ptp->name, rq->type); +#else + struct zxdh_ptp_private *adapter = container_of(ptp, struct zxdh_ptp_private, ptp_caps[0]); + int ret = 0; + int pin = -1; + + switch (rq->type) + { + case PTP_CLK_REQ_PPS: + ret = zxdh_ptp_enable_pps(adapter, on); + return ret; + case PTP_CLK_REQ_EXTTS: + if (on) + { + // pin = ptp_find_pin(adapter->ptp_clock[0], PTP_PF_EXTTS, + // rq->extts.index); + // if (pin < 0) + // return -EBUSY; + if (rq->extts.index == 1 || rq->extts.index == 2) // 选择pps0 or pps1做为capture和中断源 + { + adapter->pps_channel = rq->extts.index; + zxdh_write_reg(adapter, PP1S_EXTERNAL_SEL, rq->extts.index - 1, PTP_TOP); + } + } + return 0; + + case PTP_CLK_REQ_PEROUT: + return 0; + } + return -EOPNOTSUPP; +#endif + return 0; +} + +static int zxdh_tsn_adjfreq(struct ptp_clock_info *ptp, s32 ppb) +{ + unsigned long flags; + int neg_adj = 0; + uint32_t cur_nano, cur_frac_nano; + uint64_t tmp_frac_nano; + int timer_no; + uint32_t integer_reg; + uint32_t fraction_reg; + uint64_t base_addr; + uint64_t bar_addr; + uint64_t freq_adj; + struct zxdh_ptp_private *adapter; + + PTP_LOG_INFO("name: %s, ppb: %d\n", ptp->name, ppb); + timer_no = get_tsn_timer_no(ptp->name); + PTP_CHECK_RANGE_WITH_RETURN(timer_no, TSN_TIMER_NAME_MIN_NO, TSN_TIMER_NAME_MAX_NO, -1); + + adapter = container_of(ptp, struct zxdh_ptp_private, ptp_caps[timer_no + 1]); + + bar_addr = zxdh_ptp_get_bar_addr(adapter); + base_addr = bar_addr + PTP_HOST_BAR_OFFSET + PTPM_OFFSET_WITH_TOP; + + if (ppb == 0) + return 0; + + if (ppb < 0) + { + ppb = -ppb; + neg_adj = 1; + } + + integer_reg = tsn_clock_cycle_integer_reg(timer_no); + fraction_reg = tsn_clock_cycle_fraction_reg(timer_no); + + cur_nano = zxdh_read_reg(base_addr, integer_reg); + cur_frac_nano = zxdh_read_reg(base_addr, fraction_reg); + + tmp_frac_nano = ((unsigned long long)cur_nano << 32) + cur_frac_nano; + + PTP_LOG_INFO("cur_nano: %u, cur_frac_nano: %u, tmp_frac_nano: 0x%llx\n", cur_nano, cur_frac_nano, + tmp_frac_nano); + + /* positive adjust */ + if (0 == neg_adj) + { + tmp_frac_nano += tmp_frac_nano * ppb / 1000000000; + } + else /* negative adjust */ + { + freq_adj = tmp_frac_nano * ppb / 1000000000; + if(tmp_frac_nano > freq_adj) + tmp_frac_nano -= freq_adj; + } + + PTP_LOG_INFO("new tmp_frac_nano: 0x%llx\n", tmp_frac_nano); + cur_nano = (uint32_t)(tmp_frac_nano >> 32); + cur_frac_nano = tmp_frac_nano & 0xffffffff; + + PTP_LOG_INFO("cur_nano: %u, cur_frac_nano: %u\n", cur_nano, cur_frac_nano); + spin_lock_irqsave(&adapter->tmreg_lock, flags); + + zxdh_write_reg(base_addr, integer_reg, cur_nano); + zxdh_write_reg(base_addr, fraction_reg, cur_frac_nano); + + zxdh_write_reg(base_addr, CLOCK_CYCLE_UPDATE, 1 << (timer_no + 1)); + + spin_unlock_irqrestore(&adapter->tmreg_lock, flags); + + return 0; +} + + +static int zxdh_tsn_adjtime(struct ptp_clock_info *ptp, s64 delta) +{ + unsigned long flags; + uint32_t run_mode; + uint32_t reg_val; + uint64_t adjust; + uint64_t sec; + uint32_t nsec; + int timer_no; + uint32_t nano_sec_reg; + uint32_t low_sec_reg; + uint32_t high_sec_reg; + int run_mode_bit_shift; + uint64_t base_addr; + uint64_t bar_addr; + struct zxdh_ptp_private *adapter; + + PTP_LOG_INFO("name: %s, delta: %lld\n", ptp->name, delta); + timer_no = get_tsn_timer_no(ptp->name); + PTP_CHECK_RANGE_WITH_RETURN(timer_no, TSN_TIMER_NAME_MIN_NO, TSN_TIMER_NAME_MAX_NO, -1); + + adapter = container_of(ptp, struct zxdh_ptp_private, ptp_caps[timer_no + 1]); + bar_addr = zxdh_ptp_get_bar_addr(adapter); + base_addr = bar_addr + PTP_HOST_BAR_OFFSET + PTPM_OFFSET_WITH_TOP; + + spin_lock_irqsave(&adapter->tmreg_lock, flags); + + /* 1588 timer, update mode */ + if (delta > 0) + { + run_mode = INCRE_MODE; + adjust = delta; + } + else + { + run_mode = DECRE_MODE; + adjust = -delta; + } + + GET_TSN_ADJUST_NANO_REG(timer_no); + GET_TSN_ADJUST_LOW_SEC_REG(timer_no); + GET_TSN_ADJUST_HIGH_SEC_REG(timer_no); + + /* adjust value */ + sec = div_u64_rem(adjust, NSEC_PER_SEC, &nsec); + + PTP_LOG_INFO("sec: %llu, nsec: %u\n", sec, nsec); + // nsec = rem; + zxdh_write_reg(base_addr, high_sec_reg, (uint32_t)(sec >> 32)); + zxdh_write_reg(base_addr, low_sec_reg, (uint32_t)(sec & 0xffffffff)); + zxdh_write_reg(base_addr, nano_sec_reg, nsec); + + run_mode_bit_shift = 4 + timer_no * 2; + reg_val = zxdh_read_reg(base_addr, TSN_TIME_CONFIGURATION); + reg_val &= ~(0x3 << run_mode_bit_shift); + reg_val |= run_mode << run_mode_bit_shift; + zxdh_write_reg(base_addr, TSN_TIME_CONFIGURATION, reg_val); + /* enable adjust */ + zxdh_write_reg(base_addr, TSN_TIMER_CONTROL, 1 << timer_no); + + spin_unlock_irqrestore(&adapter->tmreg_lock, flags); + + return 0; +} + + +static int zxdh_tsn_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts) +{ + uint32_t ns; + uint64_t s; + unsigned long flags; + int timer_no; + uint32_t reg_val; + int run_mode_bit_shift; + uint32_t nano_sec_reg; + uint32_t low_sec_reg; + uint32_t high_sec_reg; + uint64_t base_addr; + uint64_t bar_addr; + struct zxdh_ptp_private *adapter; + + PTP_LOG_INFO("name: %s\n", ptp->name); + timer_no = get_tsn_timer_no(ptp->name); + PTP_CHECK_RANGE_WITH_RETURN(timer_no, TSN_TIMER_NAME_MIN_NO, TSN_TIMER_NAME_MAX_NO, -1); + + adapter = container_of(ptp, struct zxdh_ptp_private, ptp_caps[timer_no + 1]); + bar_addr = zxdh_ptp_get_bar_addr(adapter); + base_addr = bar_addr + PTP_HOST_BAR_OFFSET + PTPM_OFFSET_WITH_TOP; + + mutex_lock(&adapter->ptp_clk_mutex); + + spin_lock_irqsave(&adapter->tmreg_lock, flags); + + // bit11~bit4, configure normal mode, should make sure bit15~bit12 enable + // first. + run_mode_bit_shift = 4 + timer_no * 2; + reg_val = zxdh_read_reg(base_addr, TSN_TIME_CONFIGURATION); + reg_val &= ~(0x3 << run_mode_bit_shift); + reg_val |= NORMAL_MODE << run_mode_bit_shift; + zxdh_write_reg(base_addr, TSN_TIME_CONFIGURATION, reg_val); + + // config latch one tsn timer + reg_val = 0; + reg_val = 1 << (timer_no + 2); + zxdh_write_reg(base_addr, TIMER_LACTH_SEL, reg_val); + + // enable latch + zxdh_write_reg(base_addr, TIMER_LATCH_EN, 1); + + GET_TSN_LATCH_NANO_REG(timer_no); + GET_TSN_LATCH_LOW_SEC_REG(timer_no); + GET_TSN_LATCH_HIGH_SEC_REG(timer_no); + + ns = zxdh_read_reg(base_addr, nano_sec_reg); + s = zxdh_read_reg(base_addr, low_sec_reg); + s |= (uint64_t)zxdh_read_reg(base_addr, high_sec_reg) << 32; + + spin_unlock_irqrestore(&adapter->tmreg_lock, flags); + mutex_unlock(&adapter->ptp_clk_mutex); + + // *ts = ns_to_timespec64(ns); + ts->tv_sec = s; + ts->tv_nsec = ns; + PTP_LOG_INFO("kernel get %s clock time: %lld.%09ld\n", ptp->name, ts->tv_sec, ts->tv_nsec); + + return 0; +} + +/** + * zxdh_tsn_settime + * @ptp: the ptp clock struct + * @ts: the timespec containing the new time + */ +static int zxdh_tsn_settime(struct ptp_clock_info *ptp, const struct timespec64 *ts) +{ + unsigned long flags; + uint32_t reg_val; + int timer_no; + int run_mode_bit_shift; + uint32_t nano_sec_reg; + uint32_t low_sec_reg; + uint32_t high_sec_reg; + uint64_t base_addr; + uint64_t bar_addr; + struct zxdh_ptp_private *adapter; + + PTP_LOG_INFO("name: %s, sec: %lld, nsec: %ld\n", ptp->name, ts->tv_sec, ts->tv_nsec); + timer_no = get_tsn_timer_no(ptp->name); + PTP_CHECK_RANGE_WITH_RETURN(timer_no, TSN_TIMER_NAME_MIN_NO, TSN_TIMER_NAME_MAX_NO, -1); + + adapter = container_of(ptp, struct zxdh_ptp_private, ptp_caps[timer_no + 1]); + bar_addr = zxdh_ptp_get_bar_addr(adapter); + base_addr = bar_addr + PTP_HOST_BAR_OFFSET + PTPM_OFFSET_WITH_TOP; + + mutex_lock(&adapter->ptp_clk_mutex); + + spin_lock_irqsave(&adapter->tmreg_lock, flags); + + GET_TSN_ADJUST_NANO_REG(timer_no); + GET_TSN_ADJUST_LOW_SEC_REG(timer_no); + GET_TSN_ADJUST_HIGH_SEC_REG(timer_no); + + /* adjust value */ + zxdh_write_reg(base_addr, high_sec_reg, (uint32_t)(ts->tv_sec >> 32)); + zxdh_write_reg(base_addr, low_sec_reg, (uint32_t)(ts->tv_sec & 0xffffffff)); + zxdh_write_reg(base_addr, nano_sec_reg, ts->tv_nsec); + + run_mode_bit_shift = 4 + timer_no * 2; + reg_val = zxdh_read_reg(base_addr, TSN_TIME_CONFIGURATION); + reg_val &= ~(0x3 << run_mode_bit_shift); + reg_val |= UPDATE_MODE << run_mode_bit_shift; + zxdh_write_reg(base_addr, TSN_TIME_CONFIGURATION, reg_val); + /* enable adjust */ + zxdh_write_reg(base_addr, TSN_TIMER_CONTROL, 1 << timer_no); + + spin_unlock_irqrestore(&adapter->tmreg_lock, flags); + mutex_unlock(&adapter->ptp_clk_mutex); + + return 0; +} +#if 0 +static int zxdh_tsn_enable_pps(struct zxdh_pf_device *pf_dev, int tsn_timer, int on) +{ + uint32_t reg_val = 0; + + uint64_t base_addr; + + uint64_t bar_addr = zxdh_ptp_get_bar_addr(adapter); + + base_addr = bar_addr + PTP_HOST_BAR_OFFSET + PTPM_OFFSET_WITH_TOP; + + // enable or disable tsn pps + reg_val = zxdh_read_reg(base_addr, TSN_TIME_CONFIGURATION); + reg_val &= ~(1 << (16 + tsn_timer)); + reg_val |= on << (16 + tsn_timer); + zxdh_write_reg(base_addr, TSN_TIME_CONFIGURATION, reg_val); + + // select tsn pps output from test_1pps + // reg_val = 0x4 + tsn_timer; + // zxdh_write_reg(base_addr, TEST_PP1S_SEL, reg_val, PTP_TOP); // + // 这里先不关联配置test_pps输出，单独用ioctl配置test_pps输出 + return 0; +} +#endif +/** + * zxdh_tsn_enable + * @ptp: the ptp clock structure + * @rq: the requested feature to change + * @on: whether to enable or disable the feature + * + */ +static int zxdh_tsn_enable(struct ptp_clock_info *ptp, struct ptp_clock_request *rq, int on) +{ +#if 1 + PTP_LOG_INFO("name: %s, tsn_no: %d, rq->type: %d\n", ptp->name, get_tsn_timer_no(ptp->name), + rq->type); +#else + int timer_no; + timer_no = get_tsn_timer_no(ptp->name); + PTP_CHECK_RANGE_WITH_RETURN(timer_no, TSN_TIMER_NAME_MIN_NO, TSN_TIMER_NAME_MAX_NO, -1); + + struct zxdh_ptp_private *adapter = container_of(ptp, struct zxdh_ptp_private, ptp_caps[timer_no + 1]); + struct zxdh_pf_device *pf_dev = container_of(adapter, struct zxdh_pf_device, ptp); + + int ret = 0; + int pin = -1; + + switch (rq->type) + { + case PTP_CLK_REQ_PPS: + ret = zxdh_tsn_enable_pps(pf_dev, timer_no, on); + return ret; + case PTP_CLK_REQ_EXTTS: + if (on) + { + // pin = ptp_find_pin(adapter->ptp_clock[timer_no+1], PTP_PF_EXTTS, + // rq->extts.index); + // if (pin < 0) + // return -EBUSY; + if (rq->extts.index == 1 || rq->extts.index == 2) // 选择pps0 or pps1做为capture和中断源 + { + adapter->pps_channel = rq->extts.index; + zxdh_write_reg(adapter, PP1S_EXTERNAL_SEL, rq->extts.index - 1, PTP_TOP); + } + } + return 0; + + case PTP_CLK_REQ_PEROUT: + return 0; + } + + return -EOPNOTSUPP; +#endif + return 0; +} + +/* This function handle the pps interrupt event. */ +irqreturn_t msix_extern_pps_irq_from_risc_handler(struct zxdh_pf_device *dev) +{ + uint32_t high_sec, low_sec, nsec; + struct ptp_clock_event event; + int i; + struct zxdh_pf_device *zxdev = dev; + struct zxdh_ptp_private *adapter; + uint64_t bar_addr = 0x0; + uint64_t base_addr = 0x0; + + __u32 pps_event; + __u32 clear_event; + __u32 pps_mask; + + uint32_t nano_sec_reg; + uint32_t low_sec_reg; + uint32_t high_sec_reg; + // PTP_LOG_INFO("irq: %d\n", irq); + + adapter = zxdev->ptp; + bar_addr = zxdh_ptp_get_bar_addr(adapter); + base_addr = bar_addr + PTP_HOST_BAR_OFFSET + PTPM_OFFSET_WITH_TOP; + pps_event = zxdh_read_reg(base_addr, INTERRUPT_EVENT); // 0x10 + pps_mask = zxdh_read_reg(base_addr, INTERRUPT_MASK); + PTP_LOG_INFO("bar_addr: 0x%llx, pps_event: 0x%x,pps_mask: 0x%x, capture_timer: %d\n",bar_addr, pps_event, pps_mask, zxdev->ptp->interrupt_capture_timer); + + // disable int + for(i = 0; i < PTPM_INTERRUPT_BIT_NUM; i++) + { + if(pps_event & (1 << i)) + zxdh_write_reg(base_addr, INTERRUPT_MASK, pps_mask & (~(1 << i))); + } + + // 清中断event + clear_event = pps_mask & pps_event; // 0x10 + zxdh_write_reg(base_addr, INTERRUPT_EVENT, clear_event); + + if(zxdev->ptp->interrupt_capture_timer > INTERRUPT_CAP_TIMER_MAX_NO) + { + PTP_LOG_INFO("capture_timer: %u out of range!\n", zxdev->ptp->interrupt_capture_timer); + return -1; + } + // 用status不如用event准 + if (pps_event & (1 << EXTERNAL_PPS_BIT)) // 外部PPS信号产生的中断，Capture模式抓到的TOD + { + // 1588 timer + if (zxdev->ptp->interrupt_capture_timer == 0) + { + nsec = zxdh_read_reg(base_addr, PPS_LATCH_TOD_NANO_SECOND); + low_sec = zxdh_read_reg(base_addr, PPS_LATCH_LOWER_TOD_SECOND); + high_sec = zxdh_read_reg(base_addr, PPS_LATCH_HIGH_TOD_SECOND); + } + else // tsn timer + { + GET_PPS_LATCH_TSN_HIGH_SEC_REG(zxdev->ptp->interrupt_capture_timer); + GET_PPS_LATCH_TSN_LOW_SEC_REG(zxdev->ptp->interrupt_capture_timer); + GET_PPS_LATCH_TSN_NANO_REG(zxdev->ptp->interrupt_capture_timer); + nsec = zxdh_read_reg(base_addr, nano_sec_reg); + low_sec = zxdh_read_reg(base_addr, low_sec_reg); + high_sec = zxdh_read_reg(base_addr, high_sec_reg); + } + } + else if (pps_event & (1 << TRIGGER_IN_BIT)) // trigger in信号捕捉的TOD + { + nsec = zxdh_read_reg(base_addr, TRIGGER_IN_TOD_NANO_SECOND); + low_sec = zxdh_read_reg(base_addr, TRIGGER_IN_LOWER_TOD_SECOND); + high_sec = zxdh_read_reg(base_addr, TRIGGER_IN_HIGH_TOD_SECOND); + } + else + { + PTP_LOG_INFO("unknown pps irq\n"); + nsec = 0; + low_sec = 0; + high_sec = 0; + } + + event.type = PTP_CLOCK_EXTTS; + event.index = 0; + event.timestamp = (((uint64_t)high_sec << 32) | low_sec) * 1000000000ULL + nsec; + PTP_LOG_INFO("nsec: %u, low_sec: %u, high_sec: %u\n", nsec, low_sec, high_sec); + PTP_LOG_INFO("capture_timer: %u, timestamp: %u.%09u\n", zxdev->ptp->interrupt_capture_timer, low_sec, + nsec); + ptp_clock_event(zxdev->ptp->ptp_clock[zxdev->ptp->interrupt_capture_timer], &event); + + // enable int + zxdh_write_reg(base_addr, INTERRUPT_MASK, pps_mask); + + return IRQ_HANDLED; +} +EXPORT_SYMBOL(msix_extern_pps_irq_from_risc_handler); + +irqreturn_t msix_local_pps_irq_from_risc_handler(struct zxdh_pf_device *dev) +{ + struct ptp_clock_event event; + __u32 reg_int; + struct zxdh_pf_device *zxdev = dev; + struct zxdh_ptp_private *adapter; + uint64_t bar_addr = 0x0; + uint64_t base_addr = 0x0; + + adapter = zxdev->ptp; + bar_addr = zxdh_ptp_get_bar_addr(adapter); + base_addr = bar_addr + PTP_HOST_BAR_OFFSET; + // PTP_LOG_INFO("irq: %d\n", irq); + event.type = PTP_CLOCK_PPS; + + /* adapter->ptp_clock[0]中创建pps, 用pps对应local_pps的中断 */ + if (!zxdev->ptp->ptp_clock[0]) + return IRQ_HANDLED; + + ptp_clock_event(zxdev->ptp->ptp_clock[0], &event); + + base_addr = bar_addr + PTP_HOST_BAR_OFFSET; + reg_int = zxdh_read_reg(base_addr, LOCAL_PPS_INTERRUPT); // 0x10 + PTP_LOG_INFO("bar_addr: 0x%llx, reg_int: 0x%x\n",bar_addr, reg_int); + reg_int |= 1 << 1; + zxdh_write_reg(base_addr, LOCAL_PPS_INTERRUPT, reg_int); + +#if 0 // only debug for local pps + uint64_t ns; + uint32_t s; + static uint64_t last_ns; + static uint32_t last_s; + + reg_val = zxdh_read_reg(adapter, PTP_CONFIGURATION, PTP_M); + reg_val &= ~(0x3 << 4); + reg_val |= NORMAL_MODE << 4; + zxdh_write_reg(adapter, PTP_CONFIGURATION, reg_val, PTP_M); + + // config latch 1588 timer + zxdh_write_reg(adapter, TIMER_LACTH_SEL, 1 << LATCH_1588_TIMER, PTP_M); + + // enable latch + zxdh_write_reg(adapter, TIMER_LATCH_EN, 1, PTP_M); + + + ns = zxdh_read_reg(adapter, LATCH_TOD_NANO_SECOND, PTP_M); + s = zxdh_read_reg(adapter, LATCH_LOWER_TOD_SECOND, PTP_M); + // hwts->s |= (uint64_t)zxdh_read_reg(adapter, LATCH_HIGH_TOD_SECOND, PTP_M) << 32; + + // ns += s * 1000000000ULL; + last_ns = ns; + last_s = s; + PTP_LOG_INFO("timestamp: cur:%llu.%09lu\n", low_sec*200, nsec); + +#endif + + return IRQ_HANDLED; +} +EXPORT_SYMBOL(msix_local_pps_irq_from_risc_handler); + +// for net_device driver get timestamp, param ptp get from get_tsn_clock +// function. hw timestamp only use 32 bit. +int get_pkt_timestamp(int32_t clock_no, struct zxdh_en_device *en_dev, struct time_stamps *ts, u32 *hwts) +{ + u32 nano_sec_reg; + u32 low_sec_reg; + u32 high_sec_reg; + int timer_no; + int run_mode_bit_shift; + u32 reg_val; + struct time_stamps temp_ts; + unsigned long flags; + uint64_t base_addr; + uint64_t bar_addr; + struct zxdh_ptp_private *adapter; + struct ptp_clock_info *ptp; + int phcidx; + + + if (NULL == en_dev || NULL == ts || NULL == hwts) + return -1; + + adapter = zxdh_ptp_get_ptp_private(en_dev); + for(phcidx = 0; phcidx < ZX_CLOCK_TIMER_NUM; phcidx++) + { + if(clock_no == ptp_clock_index(adapter->ptp_clock[phcidx])) + { + ptp = &adapter->ptp_caps[phcidx]; + break; + } + } + if(phcidx == ZX_CLOCK_TIMER_NUM) + { + PTP_LOG_ERR("get phcindex fail\n"); + return -1; + } + bar_addr = zxdh_ptp_get_bar_addr(adapter); + base_addr = bar_addr + PTP_HOST_BAR_OFFSET + PTPM_OFFSET_WITH_TOP; + + + PTP_LOG_INFO("ptp->name: %s, bar_addr: 0x%llx\n", ptp->name, bar_addr); + // first 80bit and second 80bit: both are 1588 timestamp + if (0 == strcmp(ptp->name, "ptp0")) + { + PTP_LOG_INFO("ptp0\n"); + spin_lock_irqsave(&adapter->tmreg_lock, flags); + + reg_val = zxdh_read_reg(base_addr, PTP_CONFIGURATION); + reg_val &= ~(0x3 << PPS_RUN_MODE_BIT); + reg_val |= NORMAL_MODE << PPS_RUN_MODE_BIT; + zxdh_write_reg(base_addr, PTP_CONFIGURATION, reg_val); + + // config latch 1588 timer and hw timer + zxdh_write_reg(base_addr, TIMER_LACTH_SEL, 1 << LATCH_1588_TIMER | 1 << LATCH_HW_TIMER); + + // enable latch + zxdh_write_reg(base_addr, TIMER_LATCH_EN, 1); + + temp_ts.ns = zxdh_read_reg(base_addr, LATCH_TOD_NANO_SECOND); + temp_ts.s = zxdh_read_reg(base_addr, LATCH_LOWER_TOD_SECOND); + temp_ts.s |= (u64)zxdh_read_reg(base_addr, LATCH_HIGH_TOD_SECOND) << 32; + + ts->ns = temp_ts.ns; + ts->s = temp_ts.s; + + ts++; + ts->ns = temp_ts.ns; + ts->s = temp_ts.s; + + *hwts = zxdh_read_reg(base_addr, LATCH_HARDWARE_TIME_LOW); + + spin_unlock_irqrestore(&adapter->tmreg_lock, flags); + // PTP_LOG_INFO("ts[]: 0x%x.%x, hwts: 0x%x\n", ts->s, ts->ns, *hwts); + } + else // first 80bit is 1588 timestamp, second 80bit is one tsn timestamp + { + timer_no = get_tsn_timer_no(ptp->name); + PTP_LOG_INFO("tsn: %d\n", timer_no); + PTP_CHECK_RANGE_WITH_RETURN(timer_no, TSN_TIMER_NAME_MIN_NO, TSN_TIMER_NAME_MAX_NO, -1); + + spin_lock_irqsave(&adapter->tmreg_lock, flags); + + reg_val = zxdh_read_reg(base_addr, PTP_CONFIGURATION); + reg_val &= ~(0x3 << PPS_RUN_MODE_BIT); + reg_val |= NORMAL_MODE << PPS_RUN_MODE_BIT; + zxdh_write_reg(base_addr, PTP_CONFIGURATION, reg_val); + + // bit11~bit4, configure normal mode, should make sure bit15~bit12 enable + // first. + run_mode_bit_shift = 4 + timer_no * 2; + reg_val = zxdh_read_reg(base_addr, TSN_TIME_CONFIGURATION); + reg_val &= ~(0x3 << run_mode_bit_shift); + reg_val |= NORMAL_MODE << run_mode_bit_shift; + zxdh_write_reg(base_addr, TSN_TIME_CONFIGURATION, reg_val); + + // config latch 1588 and one tsn timer and hw timer + zxdh_write_reg(base_addr, TIMER_LACTH_SEL, 1 << LATCH_1588_TIMER | 1 << LATCH_HW_TIMER | 1 << (timer_no + 2)); + + // enable latch + zxdh_write_reg(base_addr, TIMER_LATCH_EN, 1); + + // read 1588 timer + ts->ns = zxdh_read_reg(base_addr, LATCH_TOD_NANO_SECOND); + ts->s = zxdh_read_reg(base_addr, LATCH_LOWER_TOD_SECOND); + ts->s |= (u64)zxdh_read_reg(base_addr, LATCH_HIGH_TOD_SECOND) << 32; + + ts++; + + GET_TSN_LATCH_NANO_REG(timer_no); + GET_TSN_LATCH_LOW_SEC_REG(timer_no); + GET_TSN_LATCH_HIGH_SEC_REG(timer_no); + // read one tsn timer + ts->ns = zxdh_read_reg(base_addr, nano_sec_reg); + ts->s = zxdh_read_reg(base_addr, low_sec_reg); + ts->s |= (u64)zxdh_read_reg(base_addr, high_sec_reg) << 32; + + *hwts = zxdh_read_reg(base_addr, LATCH_HARDWARE_TIME_LOW); + + spin_unlock_irqrestore(&adapter->tmreg_lock, flags); + // PTP_LOG_INFO("ts[]: 0x%x.%x, hwts: 0x%x\n", ts->s, ts->ns, *hwts); + } + + return 0; +} +EXPORT_SYMBOL(get_pkt_timestamp); + +#define PTPS_NUMS 3 +int enable_write_ts_to_fifo(struct zxdh_en_device *en_dev, u32 enable, u32 mac_number) +{ + uint64_t base_addr; + uint64_t bar_addr; + struct zxdh_ptp_private *adapter; + + if (PTPS_NUMS <= mac_number) + { + PTP_LOG_ERR("mac number out of range\n"); + return -1; + } + + + if (NULL == en_dev) + return -1; + + adapter = zxdh_ptp_get_ptp_private(en_dev); + bar_addr = zxdh_ptp_get_bar_addr(adapter); + base_addr = bar_addr + PTPS_HOST_BAR_OFFSET; + + PTP_LOG_INFO("bar_addr: 0x%llx, enable: %u, mac: %u\n", bar_addr, enable, mac_number); + zxdh_write_reg(base_addr, PTPS_CONFIGURATION, enable); + + return 0; +} +EXPORT_SYMBOL(enable_write_ts_to_fifo); + +int get_event_ts_info(struct zxdh_en_device *en_dev, struct ptp_buff *p_tsInfo, u32 mac_number) +{ + u32 count; + int i; + uint64_t base_addr; + uint64_t bar_addr; + // enum reg_module ptps_module; + struct zxdh_ptp_private *adapter; + + if (PTPS_NUMS <= mac_number) + { + PTP_LOG_ERR("mac number out of range\n"); + return -1; + } + + if (NULL == en_dev || NULL == p_tsInfo) + { + PTP_LOG_ERR("input pointer null\n"); + return -1; + } + + adapter = zxdh_ptp_get_ptp_private(en_dev); + bar_addr = zxdh_ptp_get_bar_addr(adapter); + base_addr = bar_addr + PTPS_HOST_BAR_OFFSET; + + // the maximum count is 64 + count = zxdh_read_reg(base_addr, PTP1588_EVENT_MESSAGE_FIFO_STATUS) & 0xff; + // half is timestamp and half is match info(messageType, sourcePortIdentity, + // sequenceId) + if(count > PTP_ENCRYPTED_MESG_MAX_NUM) + { + PTP_LOG_ERR("encrypted ptp message out of range!\n"); + return -1; + } + count /= 2; + PTP_LOG_INFO("count: %d\n", count); + + for (i = 0; i < count; i++) + { + zxdh_write_reg(base_addr, PTPS_TIMER_CONTROL, 1); + // read timestamp + p_tsInfo->ptpRegInfo[i].cfVal[0] = zxdh_read_reg(base_addr, PTP1588_EVENT_MESSAGE_TS_LOW); + p_tsInfo->ptpRegInfo[i].cfVal[1] = zxdh_read_reg(base_addr, PTP1588_EVENT_MESSAGE_TS_HIGH); + + PTP_LOG_INFO("i: %d, low: 0x%x, high: 0x%x\n", i, p_tsInfo->ptpRegInfo[i].cfVal[0], p_tsInfo->ptpRegInfo[i].cfVal[1]); + zxdh_write_reg(base_addr, PTPS_TIMER_CONTROL, 1); + // read messageType, sourcePortIdentity, sequenceId + p_tsInfo->ptpRegInfo[i].matchInfo = zxdh_read_reg(base_addr, PTP1588_EVENT_MESSAGE_TS_LOW); + PTP_LOG_INFO("i: %d, matchInfo: 0x%x\n", i, p_tsInfo->ptpRegInfo[i].matchInfo); + } + p_tsInfo->cfCount = count; + PTP_LOG_INFO("success\n"); + return 0; +} +EXPORT_SYMBOL(get_event_ts_info); + +int32_t set_interrupt_capture_timer(struct zxdh_en_device *en_dev, uint32_t index) +{ + struct zxdh_ptp_private *adapter; + if (NULL == en_dev) + return -1; + + if(index > INTERRUPT_CAP_TIMER_MAX_NO) + { + PTP_LOG_INFO("capture_timer: %u out of range!\n", index); + return -1; + } + adapter = zxdh_ptp_get_ptp_private(en_dev); + adapter->interrupt_capture_timer = index; + PTP_LOG_INFO("index: %u\n",index); + PTP_LOG_INFO("pci_ioremap_addr[0]=0x%llx,pcie_id: 0x%x, vport: 0x%x, phy_port: %u\n",adapter->pdev->pci_ioremap_addr[0], adapter->pdev->pcie_id, adapter->pdev->vport, adapter->pdev->phy_port); + return 0; +} +EXPORT_SYMBOL(set_interrupt_capture_timer); + +int32_t zxdh_set_pps_selection(struct zxdh_en_device *en_dev, uint32_t pps_type, uint32_t selection) +{ + struct zxdh_ptp_private *adapter; + uint64_t base_addr; + uint64_t bar_addr; + if (NULL == en_dev) + return -1; + + if(pps_type > PP1S_EXTERNAL || selection > PP1S_TSN3) + return -1; + + adapter = zxdh_ptp_get_ptp_private(en_dev); + bar_addr = zxdh_ptp_get_bar_addr(adapter); + base_addr = bar_addr + PTP_HOST_BAR_OFFSET; + + PTP_LOG_INFO("pps_type: %s, selection: %u\n", pps[pps_type], selection); + + switch (pps_type) + { + case PP1S_OUT: + zxdh_write_reg(base_addr, PP1S_OUT_SEL, selection); + break; + case PP1S_TEST: + zxdh_write_reg(base_addr, TEST_PP1S_SEL, selection); + break; + case PP1S_EXTERNAL: + // zxdh_write_reg(adapter, PP1S_EXTERNAL_SEL, sel->config, PTP_TOP);// + // 这个用PTP_CLK_REQ_EXTTS来配置 + break; + default: + break; + } + + return 0; +} +EXPORT_SYMBOL(zxdh_set_pps_selection); + +int32_t zxdh_set_pd_detection(struct zxdh_en_device *en_dev, uint32_t pd_index, uint32_t pd_input1, uint32_t pd_input2) +{ + struct zxdh_ptp_private *adapter; + uint64_t base_addr; + uint32_t reg_val; + uint64_t bar_addr; + if (NULL == en_dev) + return -1; + + adapter = zxdh_ptp_get_ptp_private(en_dev); + bar_addr = zxdh_ptp_get_bar_addr(adapter); + base_addr = bar_addr + PTP_HOST_BAR_OFFSET; + + PTP_LOG_INFO("pd_index: %u, pd_input1: %u, pd_input2: %u\n", pd_index, pd_input1, pd_input2); + + // bit1~0: Pd_U1_Sel0 bit3~2: Pd_U1_Sel1. + reg_val = pd_input1 | pd_input2 << 3; + + if (PHASE_DETECTION1 == pd_index) + { + zxdh_write_reg(base_addr, PD_U1_SEL, reg_val); + } + else if(PHASE_DETECTION2 == pd_index) + { + zxdh_write_reg(base_addr, PD_U2_SEL, reg_val); + } + else + { + PTP_LOG_ERR("pd_index error\n"); + return -1; + } + + return 0; +} +EXPORT_SYMBOL(zxdh_set_pd_detection); + +int32_t zxdh_get_pd_value(struct zxdh_en_device *en_dev, uint32_t pd_index, uint32_t *pd_result) +{ + struct zxdh_ptp_private *adapter; + uint64_t base_addr; + uint64_t bar_addr; + if (NULL == en_dev) + return -1; + + adapter = zxdh_ptp_get_ptp_private(en_dev); + bar_addr = zxdh_ptp_get_bar_addr(adapter); + base_addr = bar_addr + PTP_HOST_BAR_OFFSET; + + if (PHASE_DETECTION1 == pd_index) + { + *pd_result = zxdh_read_reg(base_addr, PD_U1_RESULT); + } + else if(PHASE_DETECTION2 == pd_index) + { + *pd_result = zxdh_read_reg(base_addr, PD_U2_RESULT); + } + else + { + PTP_LOG_ERR("pd_index error\n"); + return -1; + } + PTP_LOG_INFO("pd_index: %u, pd_result: 0x%x\n", pd_index, *pd_result); + + return 0; +} +EXPORT_SYMBOL(zxdh_get_pd_value); + +int get_hw_timestamp(struct zxdh_en_device *en_dev, u32 *hwts) +{ + u32 reg_val; + unsigned long flags; + uint64_t base_addr; + uint64_t bar_addr; + struct zxdh_ptp_private *adapter; + + + if (NULL == en_dev || NULL == hwts) + return -1; + + adapter = zxdh_ptp_get_ptp_private(en_dev); + bar_addr = zxdh_ptp_get_bar_addr(adapter); + base_addr = bar_addr + PTP_HOST_BAR_OFFSET + PTPM_OFFSET_WITH_TOP; + + spin_lock_irqsave(&adapter->tmreg_lock, flags); + + + reg_val = zxdh_read_reg(base_addr, PTP_CONFIGURATION); + reg_val &= ~(0x3 << PPS_RUN_MODE_BIT); + reg_val |= NORMAL_MODE << PPS_RUN_MODE_BIT; + zxdh_write_reg(base_addr, PTP_CONFIGURATION, reg_val); + + // config latch hw timer + zxdh_write_reg(base_addr, TIMER_LACTH_SEL, 1 << LATCH_HW_TIMER); + + // enable latch + zxdh_write_reg(base_addr, TIMER_LATCH_EN, 1); + + *hwts = zxdh_read_reg(base_addr, LATCH_HARDWARE_TIME_LOW); + + + spin_unlock_irqrestore(&adapter->tmreg_lock, flags); + // PTP_LOG_INFO("ts[]: 0x%x.%x, hwts: 0x%x\n", ts->s, ts->ns, *hwts); + + return 0; +} +EXPORT_SYMBOL(get_hw_timestamp); + + +int zxdh_ptp_init(struct dh_core_dev *zxdev) +{ + struct zxdh_ptp_private *zxp; + int err = -ENOMEM; + int i; + + uint32_t reg; + uint64_t base_addr; + int size; + struct zxdh_pf_device *pf_dev = dh_core_priv(zxdev); + + base_addr = pf_dev->pci_ioremap_addr[0] + PTP_HOST_BAR_OFFSET; + + zxp = kzalloc(sizeof(*zxp), GFP_KERNEL); + if (!zxp) + { + PTP_LOG_ERR("zxp kzalloc failed\n"); + goto no_memory; + } + + err = -ENODEV; + + zxp->ptp_caps[0].owner = THIS_MODULE; + strlcpy(zxp->ptp_caps[0].name, "ptp0", sizeof(zxp->ptp_caps[0].name)); + + zxp->ptp_caps[0].max_adj = 999999999; + zxp->ptp_caps[0].n_alarm = 0; + zxp->ptp_caps[0].n_ext_ts = 0; // ptp_chardev.c: ptp_ioctl: if (req.extts.index >= ops->n_ext_ts) 需要改初值 + zxp->ptp_caps[0].n_per_out = 0; + zxp->ptp_caps[0].n_pins = 0; // + zxp->ptp_caps[0].pps = 1; + zxp->ptp_caps[0].adjfreq = zx_ptp_adjfreq; + zxp->ptp_caps[0].adjtime = zxdh_ptp_adjtime; + zxp->ptp_caps[0].gettime64 = zxdh_ptp_gettime; + zxp->ptp_caps[0].settime64 = zxdh_ptp_settime; + zxp->ptp_caps[0].enable = zxdh_ptp_enable; + + zxp->ptp_clock[0] = ptp_clock_register(&zxp->ptp_caps[0], &zxdev->pdev->dev); + if (IS_ERR(zxp->ptp_clock[0])) + { + zxp->ptp_clock[0] = NULL; + PTP_LOG_ERR("ptp_clock_register ptp0 failed\n"); + goto no_clock; + } + + for (i = 0; i < ZX_TSN_TIMER_NUM; i++) + { + zxp->ptp_caps[i+1].owner = THIS_MODULE; + size = snprintf(zxp->ptp_caps[i + 1].name, sizeof(zxp->ptp_caps[i+1].name), "tsn%d", i); + if(size >= sizeof(zxp->ptp_caps[i+1].name)) + zxp->ptp_caps[i + 1].name[sizeof(zxp->ptp_caps[i+1].name)-1] = '\0'; + + zxp->ptp_caps[i + 1].max_adj = 999999999; + zxp->ptp_caps[i + 1].n_alarm = 0; + zxp->ptp_caps[i + 1].n_ext_ts = 0; + zxp->ptp_caps[i + 1].n_per_out = 0; + zxp->ptp_caps[i + 1].n_pins = 0; + zxp->ptp_caps[i + 1].pps = 0; + zxp->ptp_caps[i + 1].adjfreq = zxdh_tsn_adjfreq; + zxp->ptp_caps[i + 1].adjtime = zxdh_tsn_adjtime; + zxp->ptp_caps[i + 1].gettime64 = zxdh_tsn_gettime; + zxp->ptp_caps[i + 1].settime64 = zxdh_tsn_settime; + zxp->ptp_caps[i + 1].enable = zxdh_tsn_enable; + zxp->ptp_clock[i + 1] = ptp_clock_register(&zxp->ptp_caps[i + 1], &zxdev->pdev->dev); + if (IS_ERR(zxp->ptp_clock[i + 1])) + { + zxp->ptp_clock[i + 1] = NULL; + PTP_LOG_ERR("ptp_clock_register tsn%d failed\n", i); + goto no_clock; + } + } + + spin_lock_init(&zxp->tmreg_lock); + mutex_init(&zxp->ptp_clk_mutex); + + pf_dev->ptp = zxp; + zxp->pdev = pf_dev; + + reg = zxdh_read_reg(base_addr + PTPM_OFFSET_WITH_TOP, PTP_CONFIGURATION); + reg |= 1 << 15; + zxdh_write_reg(base_addr + PTPM_OFFSET_WITH_TOP, PTP_CONFIGURATION, reg); + // enable four tsn timer and tsn pps enable + zxdh_write_reg(base_addr + PTPM_OFFSET_WITH_TOP, TSN_TIME_CONFIGURATION, 0xff000); + + // timesync delay + zxdh_write_reg(base_addr, TSN_GROUP_NANO_SEC_DELAY0, 0x1); + zxdh_write_reg(base_addr, TSN_GROUP_NANO_SEC_DELAY1, 0x1); + zxdh_write_reg(base_addr, TSN_GROUP_NANO_SEC_DELAY2, 0x1); + zxdh_write_reg(base_addr, TSN_GROUP_NANO_SEC_DELAY3, 0x1); + zxdh_write_reg(base_addr, PTP1588_NP_NANO_SEC_DELAY, 0x1); + zxdh_write_reg(base_addr, PTP1588_NVME_NANO_SEC_DELAY1, 0x13); + zxdh_write_reg(base_addr, PTP1588_NVME_NANO_SEC_DELAY2, 0x13); + zxdh_write_reg(base_addr, PTP1588_RDMA_NANO_SEC_DELAY, 0xC); + + return 0; + +no_clock: + kfree(zxp); +no_memory: + return err; +} +EXPORT_SYMBOL(zxdh_ptp_init); + +void zxdh_ptp_stop(struct dh_core_dev *zxdev) +{ + int i; + struct zxdh_pf_device *pf_dev = dh_core_priv(zxdev); + struct zxdh_ptp_private *zxp = pf_dev->ptp; + + if (NULL == zxp) + return; + + for (i = 0; i < ZX_CLOCK_TIMER_NUM; i++) + { + if (zxp->ptp_clock[i]) + ptp_clock_unregister(zxp->ptp_clock[i]); + } + + kfree(zxp); +} +EXPORT_SYMBOL(zxdh_ptp_stop); diff --git a/src/net/drivers/net/ethernet/dinghai/en_ptp/zxdh_ptp.h b/src/net/drivers/net/ethernet/dinghai/en_ptp/zxdh_ptp.h new file mode 100644 index 0000000..56d8155 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_ptp/zxdh_ptp.h @@ -0,0 +1,103 @@ +#ifndef _ZX_PTP_H +#define _ZX_PTP_H + +#include +#include "../en_pf.h" + +#define ZX_CLOCK_TIMER_NUM 5 // 1st: ptp, other: tsn +#define ZX_TSN_TIMER_NUM 4 + +#define PTP_REG_INFO_NUM 32 +#define PTP_ENCRYPTED_MESG_MAX_NUM 64 + +#define PTP_DRIVER_UNINIT 0 +#define PTP_DRIVER_INITED 1 + +#define PTP_HOST_BAR_OFFSET 0xc000 +#define PTPS_HOST_BAR_OFFSET 0x34000 + +#define PHASE_DETECTION1 1 +#define PHASE_DETECTION2 2 + +#define PTPM_INTERRUPT_BIT_NUM 5 + +#define TSN_TIMER_NAME_MIN_NO 0 +#define TSN_TIMER_NAME_MAX_NO 3 + +#define INTERRUPT_CAP_TIMER_MIN_NO 0 +#define INTERRUPT_CAP_TIMER_MAX_NO 4 +#define PTP_CHECK_RANGE_WITH_RETURN(val, min, max, ret) \ + do { \ + if(!(min <= val && val <= max)) \ + return ret; \ + }while(0) + +struct time_stamps +{ + u64 s; + u32 ns; +}; + +struct pkt_hw_ts +{ + struct time_stamps ts[2]; +}; + +enum +{ + PP1S_OUT, + PP1S_TEST, + PP1S_EXTERNAL, // maybe use PTP_CLK_REQ_EXTTS +}; + +typedef enum +{ + // PPS_OUT / TEST_PP1S / EXTERNAL_PP1S selection: + PP1S_REF0, + PP1S_REF1, + // PPS_OUT / TEST_PP1S selection: + PP1S_LOCAL, + PP1S_1588, + // TEST PP1S selection only: + PP1S_TSN0, + PP1S_TSN1, + PP1S_TSN2, + PP1S_TSN3 +}PPS_SELECT; + +struct zxdh_ptp_private { + // void __iomem *ptpm_regs; + // void __iomem *ptp_top_regs; + // void __iomem *ptps0_regs; + // void __iomem *ptps1_regs; + // void __iomem *ptps2_regs; + + struct mutex ptp_clk_mutex; + struct zxdh_pf_device *pdev; + struct ptp_clock *ptp_clock[ZX_CLOCK_TIMER_NUM]; + struct ptp_clock_info ptp_caps[ZX_CLOCK_TIMER_NUM]; + unsigned int pps_channel; // externel pps0/pps1 + unsigned int interrupt_capture_timer; + + spinlock_t tmreg_lock; + +}; + +struct ptp_reg_info +{ + uint32_t cfVal[2]; + uint32_t matchInfo; +}; + +struct ptp_buff +{ + uint32_t cfCount; + struct ptp_reg_info ptpRegInfo[PTP_REG_INFO_NUM]; +}; + +int zxdh_ptp_init(struct dh_core_dev *zxdev); +void zxdh_ptp_stop(struct dh_core_dev *zxdev); +irqreturn_t msix_extern_pps_irq_from_risc_handler(struct zxdh_pf_device *dev); +irqreturn_t msix_local_pps_irq_from_risc_handler(struct zxdh_pf_device *dev); + +#endif /* _ZX_PTP_H */ diff --git a/src/net/drivers/net/ethernet/dinghai/en_ptp/zxdh_ptp_common.h b/src/net/drivers/net/ethernet/dinghai/en_ptp/zxdh_ptp_common.h new file mode 100644 index 0000000..902e507 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_ptp/zxdh_ptp_common.h @@ -0,0 +1,12 @@ +#ifndef _ZX_PTP_COMMON_H +#define _ZX_PTP_COMMON_H + +#include + +#define PTP_LOG_ERR(fmt, arg...) DH_LOG_ERR(MODULE_PTP, fmt, ##arg); +#define PTP_LOG_INFO(fmt, arg...) DH_LOG_INFO(MODULE_PTP, fmt, ##arg); +#define PTP_LOG_DEBUG(fmt, arg...) DH_LOG_DEBUG(MODULE_PTP, fmt, ##arg); +#define PTP_LOG_WARN(fmt, arg...) DH_LOG_WARNING(MODULE_PTP, fmt, ##arg); + + +#endif \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_ptp/zxdh_ptp_regs.h b/src/net/drivers/net/ethernet/dinghai/en_ptp/zxdh_ptp_regs.h new file mode 100644 index 0000000..0103e92 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_ptp/zxdh_ptp_regs.h @@ -0,0 +1,460 @@ +#ifndef _ZX_REGS_H +#define _ZX_REGS_H + +/**************************** ptpm start **************************/ + +#define PTPM_OFFSET_WITH_TOP 0x4000 + +#define EXTERNAL_PPS_BIT 4 +#define TRIGGER_OUT_BIT 1 +#define TRIGGER_IN_BIT 0 +/* bit4: pps_in_status + 0: not receive pps + 1: receive pps */ +#define INTERRUPT_STATUS 0x00000010 +/* bit4: pps income event, writing 1 to the bit clearing it + 0: not receive pps + 1: receive pps */ +#define INTERRUPT_EVENT 0x00000014 +/* bit4: pps income event mask + 0: mask + 1: no mask */ +#define INTERRUPT_MASK 0x00000018 +/* bit4: trigger pps income event test + 0: not occur + 1: occur */ +#define INTERRUPT_TEST 0x0000001C + +/* adjust clock cycle, for 1588 and hw timer */ +#define PTP_CLOCK_CYCLE_INTEGER 0x00000030 +#define PTP_CLOCK_CYCLE_FRACTION 0x00000034 + +/* + BIT18: trig oe + 1: trig out + 0: trig in + bit17: hw timer update enable, used when timer run mode is update,increment or decrement + 0: update disable + 1: update enable + bit16: 1588 timer update enable, used when timer run mode is update,increment or decrement + 0: update disable + 1: update enable + bit15: 1588 and hw time timer enable + 0: timer disable + 1: timer enable + bit8: pps input select + 0: select internal pps + 1: select external pps + bit5:4 1588 tod and hw timer run mode + 0: normal + 1: update + 2: increment + 3: decrement + bit2: trigger out enable + 0:disable + 1:enable + bit1: trigger in enable + 0:disable + 1:enable + bit0: 1588 tod timer slave/capture mode + 0:capture mode, capture 1588 tod timer when input pps pulse + 1:slave mode, the timer make the input pps as reference +*/ +#define PTP_CONFIGURATION 0x00000040 + +#define PPS_TRIGGER_IN_BIT 1 +#define PPS_TRIGGER_OUT_BIT 2 +#define PPS_RUN_MODE_BIT 4 +#define PPS_INPUT_SEL_BIT 8 +#define TIMER_EN_BIT 15 +#define TIMER_1588_UPT_EN_BIT 16 +#define TIMER_HW_UPT_EN_BIT 17 +#define TRIG_OE 18 +enum timer_run_mode { + NORMAL_MODE, + UPDATE_MODE, + INCRE_MODE, + DECRE_MODE, +}; +/* bit1: adjust the 1588 tod and hw timer + 0: not adjust + 1: adjust the timer with add/sub/ or update + */ +#define TIMER_CONTROL 0x00000044 +#define ADJ_TIMER_BIT 1 + +/* + bit4: tsn3 clock cycle update enable + bit3: tsn2 clock cycle update enable + bit2: tsn1 clock cycle update enable + bit1: tsn0 clock cycle update enable + bit0: 1588 clock cycle update enable +*/ +#define CLOCK_CYCLE_UPDATE 0x0000004C + +/* bit31~16: nanosecond 0~0xffff + bit15~0 : frac nanosecond 0~0xffff */ +#define PPS_INCOME_DELAY 0x00000048 +/* bit0, 0:not latch, 1:latch the timer */ +#define TIMER_LATCH_EN 0x00000058 +/* bit5:0, select the latch timer + bit0: 1588 timer + bit1: hw timer + bit2: tsn0 timer + bit3: tsn1 timer + bit4: tsn2 timer + bit5: tsn3 tiemr */ +#define TIMER_LACTH_SEL 0x0000005C + +enum latch_timer_type { + LATCH_1588_TIMER, + LATCH_HW_TIMER, + LATCH_TSN0_TIMER, + LATCH_TSN1_TIMER, + LATCH_TSN2_TIMER, + LATCH_TSN3_TIMER, +}; + +// trigger in +#define TRIGGER_IN_TOD_NANO_SECOND 0x00000060 +#define TRIGGER_IN_LOWER_TOD_SECOND 0x00000064 +#define TRIGGER_IN_HIGH_TOD_SECOND 0x00000068 +#define TRIGGER_IN_FRAC_NANO_SECOND 0x0000006C + +#define TRIGGER_IN_HARDWARE_TIME_LOW 0x00000070 +#define TRIGGER_IN_HARDWARE_TIME_HIGH 0x00000074 + +// trigger out +#define TRIGGER_OUT_TOD_NANO_SECOND 0x00000080 +#define TRIGGER_OUT_LOWER_TOD_SECOND 0x00000084 +#define TRIGGER_OUT_HIGH_TOD_SECOND 0x00000088 +// #define TRIGGER_OUT_FRAC_NANO_SECOND 0x0000008C // none + +#define TRIGGER_OUT_HARDWARE_TIME_LOW 0x00000090 +#define TRIGGER_OUT_HARDWARE_TIME_HIGH 0x00000094 + + +/* adjust 1588 timer */ +#define ADJUST_TOD_NANO_SECOND 0x000000A0 +#define ADJUST_LOWER_TOD_SECOND 0x000000A4 +#define ADJUST_HIGH_TOD_SECOND 0x000000A8 +#define ADJUST_FRAC_NANO_SECOND 0x000000AC +/* adjust hardware timer */ +#define ADJUST_HARDWARE_TIME_LOW 0x000000B0 +#define ADJUST_HARDWARE_TIME_HIGH 0x000000B4 + +/* 1588 timer latched time */ +#define LATCH_TOD_NANO_SECOND 0x000000C0 +#define LATCH_LOWER_TOD_SECOND 0x000000C4 +#define LATCH_HIGH_TOD_SECOND 0x000000C8 +#define LATCH_FRAC_NANO_SECOND 0x000000CC +/* hw timer latched time */ +#define LATCH_HARDWARE_TIME_LOW 0x000000D0 +#define LATCH_HARDWARE_TIME_HIGH 0x000000D4 + +/* pps capture tod time*/ +#define PPS_LATCH_TOD_NANO_SECOND 0x00000120 +#define PPS_LATCH_LOWER_TOD_SECOND 0x00000124 +#define PPS_LATCH_HIGH_TOD_SECOND 0x00000128 +#define PPS_LATCH_FRAC_NANO_SECOND 0x0000012C + +/* bit19~16 tsn pps enable + bit19: tsn3 + bit18: tsn2 + bit17: tsn1 + bit16: tsn0 + bit15~12 tsn timer enable + bit15: tsn3 + bit14: tsn2 + bit13: tsn1 + bit12: tsn0 + bit11~10 tsn0 timer run mode + bit9~8 tsn1 timer run mode, + bit7~6 tsn2 timer run mode, + bit5~4 tsn3 timer run mode, + 0: normal + 1: update + 2: increment + 3: decrement + bit3~0: tsn timer slave/capture mode, 0 is capture mode, 1 is slave mode + bit3: tsn3 + bit2: tsn2 + bit1: tsn1 + bit0: tsn0 +*/ +#define TSN_TIME_CONFIGURATION 0x00000140 +/* + bit3: adjust tsn3 timer + bit2: adjust tsn2 timer + bit1: adjust tsn1 timer + bit0: adjust tsn0 timer +*/ +#define TSN_TIMER_CONTROL 0x00000144 +#define TSN0_ADJ_EN_BIT 0 +#define TSN1_ADJ_EN_BIT 1 +#define TSN2_ADJ_EN_BIT 2 +#define TSN3_ADJ_EN_BIT 3 + +/* adjust clock cycle, for four tsn timer */ +#define TSN0_CLOCK_CYCLE_INTEGER 0x00000148 +#define TSN0_CLOCK_CYCLE_FRACTION 0x0000014C +#define TSN1_CLOCK_CYCLE_INTEGER 0x00000150 +#define TSN1_CLOCK_CYCLE_FRACTION 0x00000154 +#define TSN2_CLOCK_CYCLE_INTEGER 0x00000158 +#define TSN2_CLOCK_CYCLE_FRACTION 0x0000015C +#define TSN3_CLOCK_CYCLE_INTEGER 0x00000160 +#define TSN3_CLOCK_CYCLE_FRACTION 0x00000164 + +#define TSN_CLOCK_CYCLE_INTEGER(tsn_no) TSN##tsn_no##_CLOCK_CYCLE_INTEGER +#define TSN_CLOCK_CYCLE_FRACTION(tsn_no) TSN##tsn_no##_CLOCK_CYCLE_FRACTION + +/* adjust tsn timer */ +#define TSN0_ADJUST_TOD_NANO_SECOND 0x00000180 +#define TSN0_ADJUST_LOWER_TOD_SECOND 0x00000184 +#define TSN0_ADJUST_HIGH_TOD_SECOND 0x00000188 +#define TSN0_ADJUST_FRAC_NANO_SECOND 0x0000018C + +#define TSN1_ADJUST_TOD_NANO_SECOND 0x00000190 +#define TSN1_ADJUST_LOWER_TOD_SECOND 0x00000194 +#define TSN1_ADJUST_HIGH_TOD_SECOND 0x00000198 +#define TSN1_ADJUST_FRAC_NANO_SECOND 0x0000019C + +#define TSN2_ADJUST_TOD_NANO_SECOND 0x000001A0 +#define TSN2_ADJUST_LOWER_TOD_SECOND 0x000001A4 +#define TSN2_ADJUST_HIGH_TOD_SECOND 0x000001A8 +#define TSN2_ADJUST_FRAC_NANO_SECOND 0x000001AC + +#define TSN3_ADJUST_TOD_NANO_SECOND 0x000001B0 +#define TSN3_ADJUST_LOWER_TOD_SECOND 0x000001B4 +#define TSN3_ADJUST_HIGH_TOD_SECOND 0x000001B8 +#define TSN3_ADJUST_FRAC_NANO_SECOND 0x000001BC + +#define TSN_ADJUST_NANO_SEC(tsn_no) TSN##tsn_no##_ADJUST_TOD_NANO_SECOND +#define TSN_ADJUST_LOW_SECOND(tsn_no) TSN##tsn_no##_ADJUST_LOWER_TOD_SECOND +#define TSN_ADJUST_HIGH_SECOND(tsn_no) TSN##tsn_no##_ADJUST_HIGH_TOD_SECOND +#define TSN_ADJUST_FRAC_NANO_SEC(tsn_no) TSN##tsn_no##_ADJUST_FRAC_NANO_SECOND + +/* tsn0 timer latched time */ +#define TSN0_LATCH_TOD_NANO_SECOND 0x000001C0 +#define TSN0_LATCH_LOWER_TOD_SECOND 0x000001C4 +#define TSN0_LATCH_HIGH_TOD_SECOND 0x000001C8 +#define TSN0_LATCH_FRAC_NANO_SECOND 0x000001CC +/* tsn1 timer latched time */ +#define TSN1_LATCH_TOD_NANO_SECOND 0x000001D0 +#define TSN1_LATCH_LOWER_TOD_SECOND 0x000001D4 +#define TSN1_LATCH_HIGH_TOD_SECOND 0x000001D8 +#define TSN1_LATCH_FRAC_NANO_SECOND 0x000001DC +/* tsn2 timer latched time */ +#define TSN2_LATCH_TOD_NANO_SECOND 0x000001E0 +#define TSN2_LATCH_LOWER_TOD_SECOND 0x000001E4 +#define TSN2_LATCH_HIGH_TOD_SECOND 0x000001E8 +#define TSN2_LATCH_FRAC_NANO_SECOND 0x000001EC +/* tsn3 timer latched time */ +#define TSN3_LATCH_TOD_NANO_SECOND 0x000001F0 +#define TSN3_LATCH_LOWER_TOD_SECOND 0x000001F4 +#define TSN3_LATCH_HIGH_TOD_SECOND 0x000001F8 +#define TSN3_LATCH_FRAC_NANO_SECOND 0x000001FC + +#define TSN_LATCH_NANO_SEC(tsn_no) TSN##tsn_no##_LATCH_TOD_NANO_SECOND +#define TSN_LATCH_LOW_SECOND(tsn_no) TSN##tsn_no##_LATCH_LOWER_TOD_SECOND +#define TSN_LATCH_HIGH_SECOND(tsn_no) TSN##tsn_no##_LATCH_HIGH_TOD_SECOND +#define TSN_LATCH_FRAC_NANO_SEC(tsn_no) TSN##tsn_no##_LATCH_FRAC_NANO_SECOND + +/* pps capture tsn0 time*/ +#define PPS_LATCH_TSN0_NANO_SECOND 0x00000200 +#define PPS_LATCH_TSN0_LOWER_SECOND 0x00000204 +#define PPS_LATCH_TSN0_HIGH_SECOND 0x00000208 +#define PPS_LATCH_TSN0_FRAC_NANO 0x0000020C +/* pps capture tsn1 time*/ +#define PPS_LATCH_TSN1_NANO_SECOND 0x00000210 +#define PPS_LATCH_TSN1_LOWER_SECOND 0x00000214 +#define PPS_LATCH_TSN1_HIGH_SECOND 0x00000218 +#define PPS_LATCH_TSN1_FRAC_NANO 0x0000021C +/* pps capture tsn2 time*/ +#define PPS_LATCH_TSN2_NANO_SECOND 0x00000220 +#define PPS_LATCH_TSN2_LOWER_SECOND 0x00000224 +#define PPS_LATCH_TSN2_HIGH_SECOND 0x00000228 +#define PPS_LATCH_TSN2_FRAC_NANO 0x0000022C +/* pps capture tsn3 time*/ +#define PPS_LATCH_TSN3_NANO_SECOND 0x00000230 +#define PPS_LATCH_TSN3_LOWER_SECOND 0x00000234 +#define PPS_LATCH_TSN3_HIGH_SECOND 0x00000238 +#define PPS_LATCH_TSN3_FRAC_NANO 0x0000023C + +#define PPS_LATCH_TSN_NANO_SEC(tsn_no) PPS_LATCH_TSN##tsn_no##_NANO_SECOND +#define PPS_LATCH_TSN_LOW_SECOND(tsn_no) PPS_LATCH_TSN##tsn_no##_LOWER_SECOND +#define PPS_LATCH_TSN_HIGH_SECOND(tsn_no) PPS_LATCH_TSN##tsn_no##_HIGH_SECOND +#define PPS_LATCH_TSN_FRAC_NANO_SEC(tsn_no) PPS_LATCH_TSN##tsn_no##_FRAC_NANO + +/**************************** ptpm end **************************/ + + +/**************************** ptp_top start **************************/ + +/* bit3: local pp1s status + 0: not generate local pp1s + 1: generate local pp1s + bit2: trigger local pp1s event test + 0: not occur + 1: occur + bit1: writing 1 to the bit clearing local pp1s status + 0: not clear + 1: clear + bit0: local pp1s event enable + 0: no enable + 1: enable */ +#define LOCAL_PPS_INTERRUPT 0x00000000 +// bit0: 0 ref0 1 ref1 +#define PP1S_EXTERNAL_SEL 0x00000004 +/* bit1~0: select pp1s out: + 00: pp1s ref0 + 01: pp1s ref1 + 10: local pp1s + 11: 1588 pp1s */ +#define PP1S_OUT_SEL 0x00000008 +/* bit2~0: select test pp1s: + 000: pp1s ref0 + 001: pp1s ref1 + 010: local pp1s + 011: 1588 pp1s + 100: tsn0 pp1s + 101: tsn1 pp1s + 110: tsn2 pp1s + 111: tsn3 pp1s */ +#define TEST_PP1S_SEL 0x0000000C + +#define LOCAL_PP1S_EN 0x00000010 // use local_pp1s need enable this reg +/* bit2~1: select local pp1s adjust reference + 00: pp1s ref0 + 01: pp1s ref1 + 10,11: 1588 pp1s + bit0: adjust local pp1s phase once */ +#define LOCAL_PP1S_ADJUST 0x00000014 +/* bit29~0: adjust local pp1s value, must below 10e9, 1bit is 1 nanosecond */ +#define LOCAL_PP1S_ADJUST_VALUE 0x00000018 + +/* bit5~3: Pd_U1_Sel1 + 000: pp1s ref0 + 001: pp1s ref1 + 010: local pp1s + 011: 1588 pp1s + 100: tsn0 pp1s + 101: tsn1 pp1s + 110: tsn2 pp1s + 111: tsn3 pp1s + bit2~0: Pd_U1_Sel0 + 000: pp1s ref0 + 001: pp1s ref1 + 010: local pp1s + 011: 1588 pp1s + 100: tsn0 pp1s + 101: tsn1 pp1s + 110: tsn2 pp1s + 111: tsn3 pp1s */ +#define PD_U1_SEL 0x00000040 +// bit29~0: phase detector module 1 select0 input pp1s shift value. +#define PD_U1_PD0_SHIFT 0x00000044 +// bit29~0: phase detector module 1 select1 input pp1s shift value. +#define PD_U1_PD1_SHIFT 0x00000048 + +/* bit30: Pd_U1_Result_sign + 1: positive + 0: negative + bit29: Pd_U1_Overflow: the interval between two pp1s pluse is greater than 0x1FFF_FFFF, 1 is overflow + bit28~0: phase detector module 1 resule value, must below 5*10e8, 1 bit is 1 nanosecond. */ +#define PD_U1_RESULT 0x0000004C + +/* bit5~3: Pd_U2_Sel1 + 000: pp1s ref0 + 001: pp1s ref1 + 010: local pp1s + 011: 1588 pp1s + 100: tsn0 pp1s + 101: tsn1 pp1s + 110: tsn2 pp1s + 111: tsn3 pp1s + bit2~0: Pd_U2_Sel0 + 000: pp1s ref0 + 001: pp1s ref1 + 010: local pp1s + 011: 1588 pp1s + 100: tsn0 pp1s + 101: tsn1 pp1s + 110: tsn2 pp1s + 111: tsn3 pp1s */ +#define PD_U2_SEL 0x00000050 +// bit29~0: phase detector module 2 select0 input pp1s shift value. +#define PD_U2_PD0_SHIFT 0x00000054 +// bit29~0: phase detector module 2 select1 input pp1s shift value. +#define PD_U2_PD1_SHIFT 0x00000058 +/* bit30: Pd_U2_Result_sign + 1: positive + 0: negative + bit29: Pd_U2_Overflow: the interval between two pp1s pluse is greater than 0x1FFF_FFFF, 1 is overflow + bit28~0: phase detector module 2 resule value, must below 5*10e8, 1 bit is 1 nanosecond. */ +#define PD_U2_RESULT 0x0000005C + +#define TSN_GROUP_NANO_SEC_DELAY0 0x00000080 +#define TSN_GROUP_FRAC_NANO_SEC_DELAY0 0x00000084 +#define TSN_GROUP_NANO_SEC_DELAY1 0x00000088 +#define TSN_GROUP_FRAC_NANO_SEC_DELAY1 0x0000008C +#define TSN_GROUP_NANO_SEC_DELAY2 0x00000090 +#define TSN_GROUP_FRAC_NANO_SEC_DELAY2 0x00000094 +#define TSN_GROUP_NANO_SEC_DELAY3 0x00000098 +#define TSN_GROUP_FRAC_NANO_SEC_DELAY3 0x0000009C +#define PTP1588_RDMA_NANO_SEC_DELAY 0x000000A0 +#define PTP1588_RDMA_FRAC_NANO_SEC_DELAY 0x000000A4 +#define PTP1588_NP_NANO_SEC_DELAY 0x000000A8 +#define PTP1588_NP_FRAC_NANO_SEC_DELAY 0x000000AC +#define PTP1588_NVME_NANO_SEC_DELAY1 0x000000C0 +#define PTP1588_NVME_FRAC_NANO_SEC_DELAY1 0x000000C4 +#define PTP1588_NVME_NANO_SEC_DELAY2 0x000000C8 +#define PTP1588_NVME_FRAC_NANO_SEC_DELAY2 0x000000CC + + +/**************************** ptp_top end **************************/ + + +/**************************** ptps start **************************/ +/* bit0: enable writing timestamps to the FIFO + 0: disable + 1: enable */ +#define PTPS_CONFIGURATION 0x00000020 + +/* bit0: PTP1588 FIFO read command + 0: not read + 1: read */ +#define PTPS_TIMER_CONTROL 0x00000024 + +/* bit15~0: integral nanosecond of sync Hardware Time compensaion, 1 bit is 1 nanosecond */ +#define SYNC_HW_TIME_COMPENSATION 0x00000038 + +/* 对于加密报文，先读 PTP event timestamps count，然后读时间戳和匹配信息，读时间戳和匹配信息之前，都要先配置TIMER_CONTROL. + 匹配信息是在PTP1588_EVENT_MESSAGE_TS_LOW里，具体对应关系: BIT[23:0]: messageType, sourcePortIdentity[3:0],sequenceId[15:0] */ +/* ptp1588 event message timestamp[31:0] */ +#define PTP1588_EVENT_MESSAGE_TS_LOW 0x00000084 +/* ptp1588 event message timestamp[63:32] */ +#define PTP1588_EVENT_MESSAGE_TS_HIGH 0x00000088 + +/* bit9: FIFO full + bit8: FIFO empty + bit7~0: PTP event timestamps count */ +#define PTP1588_EVENT_MESSAGE_FIFO_STATUS 0x0000008C + +struct event_ts_info +{ + u32 ts_low; + u32 ts_high; + unsigned char messageType; + unsigned char srcPortId; + short sequenceId; +}; + +#define EVENT_MESSAGE_MAX_NUM 32 + +/**************************** ptps end **************************/ + + + + +#endif /* _ZX_REGS_H */ diff --git a/src/net/drivers/net/ethernet/dinghai/en_sf.c b/src/net/drivers/net/ethernet/dinghai/en_sf.c new file mode 100644 index 0000000..3ef97ea --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_sf.c @@ -0,0 +1,781 @@ +#include +#include +#ifdef HAVE_DEV_PRINTK_OPS +#include +#endif +#include +#include +#include +#include +#include "en_aux.h" +#include "en_sf.h" +#include "./en_sf/eq.h" + +extern struct devlink_ops dh_sf_devlink_ops; +extern struct dh_core_devlink_ops dh_sf_core_devlink_ops; + +int32_t zxdh_sf_get_vq_lock(struct dh_core_dev *dh_dev) +{ + struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev); + int32_t ret = 0; + + ret= en_sf_dev->sf_ops->en_sf_get_vq_lock(dh_dev->parent); + if (ret != 0) + { + LOG_ERR("en_sf_get_vq_lock failed: %d\n", ret); + return ret; + } + + return 0; +} + +int32_t zxdh_sf_release_vq_lock(struct dh_core_dev *dh_dev) +{ + struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev); + int32_t ret = 0; + + ret= en_sf_dev->sf_ops->en_sf_release_vq_lock(dh_dev->parent); + if (ret != 0) + { + LOG_ERR("en_sf_release_vq_lock failed: %d\n", ret); + return ret; + } + + return 0; +} + +int32_t zxdh_sf_get_phy_vq(struct dh_core_dev *dh_dev, uint16_t index) +{ + struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev); + int32_t phy_index = 0; + + phy_index= en_sf_dev->sf_ops->en_sf_get_phy_vq(dh_dev->parent, index); + if (phy_index < 0) + { + LOG_ERR("en_sf_get_phy_vq failed: %d\n", phy_index); + } + + return phy_index; +} + +int32_t zxdh_sf_release_phy_vq(struct dh_core_dev *dh_dev, uint32_t *phy_index, uint16_t total_qnum) +{ + struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev); + int32_t ret = 0; + + ret= en_sf_dev->sf_ops->en_sf_release_phy_vq(dh_dev->parent, phy_index, total_qnum); + if (ret != 0) + { + LOG_ERR("en_sf_relaese_phy_vq failed: %d\n", ret); + return ret; + } + + return 0; +} + +bool zxdh_en_sf_is_bond(struct dh_core_dev *dh_dev) +{ + struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev); + + return en_sf_dev->sf_ops->en_sf_is_bond(dh_dev->parent); +} + +bool zxdh_en_sf_is_upf(struct dh_core_dev *dh_dev) +{ + struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev); + + return en_sf_dev->sf_ops->en_sf_is_upf(dh_dev->parent); +} + +int32_t zxdh_en_sf_get_phy_vq(struct dh_core_dev *dh_dev, uint16_t index) +{ + int32_t ret = 0; + int32_t phy_index = 0; + + ret = zxdh_sf_get_vq_lock(dh_dev); + if (ret < 0) + { + return ret; + } + + phy_index = zxdh_sf_get_phy_vq(dh_dev, index); + + ret = zxdh_sf_release_vq_lock(dh_dev); + if (ret < 0) + { + return ret; + } + + return phy_index; +} + +int32_t zxdh_en_sf_release_phy_vq(struct dh_core_dev *dh_dev, uint32_t *phy_index, uint16_t total_qnum) +{ + int32_t ret = 0; + + ret = zxdh_sf_get_vq_lock(dh_dev); + if (ret < 0) + { + return ret; + } + + zxdh_sf_release_phy_vq(dh_dev, phy_index, total_qnum); + + zxdh_sf_release_vq_lock(dh_dev); + + return ret; +} + +void zxdh_en_sf_set_status(struct dh_core_dev *dh_dev, uint8_t status) +{ + struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev); + + en_sf_dev->sf_ops->en_sf_set_status(dh_dev->parent, status); + + return; +} + +uint8_t zxdh_en_sf_get_status(struct dh_core_dev *dh_dev) +{ + struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev); + uint8_t status = 0; + + status = en_sf_dev->sf_ops->en_sf_get_status(dh_dev->parent); + + return status; +} + +void zxdh_en_sf_set_vf_mac(struct dh_core_dev *dh_dev, uint8_t *mac, int32_t vf_id) +{ + struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev); + + en_sf_dev->sf_ops->en_sf_set_vf_mac(dh_dev->parent, mac, vf_id); + + return; +} + +void zxdh_en_sf_get_vf_mac(struct dh_core_dev *dh_dev, uint8_t *mac, int32_t vf_id) +{ + struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev); + + en_sf_dev->sf_ops->en_sf_get_vf_mac(dh_dev->parent, mac, vf_id); + + return ; +} + +void zxdh_en_sf_set_mac(struct dh_core_dev *dh_dev, uint8_t *mac) +{ + struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev); + + en_sf_dev->sf_ops->en_sf_set_mac(dh_dev->parent, mac); + + return; +} + +void zxdh_en_sf_get_mac(struct dh_core_dev *dh_dev, uint8_t *mac) +{ + struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev); + + en_sf_dev->sf_ops->en_sf_get_mac(dh_dev->parent, mac); + + return ; +} + +uint64_t zxdh_en_sf_get_features(struct dh_core_dev *dh_dev) +{ + struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev); + uint64_t device_feature = 0; + + device_feature = en_sf_dev->sf_ops->en_sf_get_features(dh_dev->parent); + + return device_feature; +} + +void zxdh_en_sf_set_features(struct dh_core_dev *dh_dev, uint64_t features) +{ + struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev); + + en_sf_dev->sf_ops->en_sf_set_features(dh_dev->parent, features); + + return; +} + +uint16_t zxdh_en_sf_get_queue_num(struct dh_core_dev *dh_dev) +{ + struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev); + uint16_t qnum = 0; + + qnum = en_sf_dev->sf_ops->en_sf_get_queue_num(dh_dev->parent); + + return qnum; +} + +uint16_t zxdh_en_sf_get_queue_size(struct dh_core_dev *dh_dev, uint32_t index) +{ + struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev); + uint16_t queue_size = 0; + + queue_size = en_sf_dev->sf_ops->en_sf_get_queue_size(dh_dev->parent, index); + + return queue_size; +} + +struct pci_dev *zxdh_en_sf_get_pdev(struct dh_core_dev *dh_dev) +{ + struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev); + + return en_sf_dev->sf_ops->en_sf_get_pdev(dh_dev->parent); +} + +uint64_t zxdh_en_sf_get_bar_virt_addr(struct dh_core_dev *dh_dev, uint8_t bar_num) +{ + struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev); + + return en_sf_dev->sf_ops->en_sf_get_bar_virt_addr(dh_dev->parent, bar_num); +} + +int32_t zxdh_en_sf_msg_send_cmd(struct dh_core_dev *dh_dev, uint16_t module_id, void *msg, void *ack, bool is_sync) +{ + struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev); + + return en_sf_dev->sf_ops->en_sf_msg_send_cmd(dh_dev->parent, module_id, msg, ack, is_sync); +} + +int32_t zxdh_en_sf_async_eq_enable(struct dh_core_dev *dh_dev, struct dh_eq_async *eq, const char *name, bool attach) +{ + struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev); + + return en_sf_dev->sf_ops->en_sf_async_eq_enable(dh_dev->parent, eq, name, attach); +} + +void zxdh_en_sf_set_pf_link_up(struct dh_core_dev *dh_dev, bool link_up) +{ + struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev); + + en_sf_dev->sf_ops->en_sf_set_pf_link_up(dh_dev->parent, link_up); + return; +} + +bool zxdh_en_sf_get_pf_link_up(struct dh_core_dev *dh_dev) +{ + struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev); + + return en_sf_dev->sf_ops->en_sf_get_pf_link_up(dh_dev->parent); +} + +void zxdh_en_sf_update_pf_link_info(struct dh_core_dev *dh_dev, struct link_info_struct *link_info_val) +{ + struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev); + + en_sf_dev->sf_ops->en_sf_update_pf_link_info(dh_dev->parent, link_info_val); + return; +} + +int32_t zxdh_en_sf_get_pf_drv_msg(struct dh_core_dev *dh_dev, uint8_t *drv_version, uint8_t *drv_version_len) +{ + struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev); + + return en_sf_dev->sf_ops->en_sf_get_drv_msg(dh_dev, drv_version, drv_version_len); +} + +void zxdh_en_sf_set_vepa(struct dh_core_dev *dh_dev, bool setting) +{ + struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev); + + en_sf_dev->sf_ops->en_sf_set_vepa(dh_dev->parent, setting); + return; +} + +bool zxdh_en_sf_get_vepa(struct dh_core_dev *dh_dev) +{ + struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev); + + return en_sf_dev->sf_ops->en_sf_get_vepa(dh_dev->parent); +} + +void zxdh_en_sf_get_link_info_from_vqm(struct dh_core_dev *dh_dev, uint8_t *link_up) +{ + struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev); + + en_sf_dev->sf_ops->en_sf_get_link_info_from_vqm(dh_dev->parent, link_up); + return; +} + +void zxdh_en_sf_set_vf_link_info(struct dh_core_dev *dh_dev, uint16_t vf_idx, uint8_t link_up) +{ + struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev); + + en_sf_dev->sf_ops->en_sf_set_vf_link_info(dh_dev->parent, vf_idx, link_up); + return; +} + +void zxdh_en_sf_set_pf_phy_port(struct dh_core_dev *dh_dev, uint8_t phy_port) +{ + struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev); + + en_sf_dev->sf_ops->en_sf_set_pf_phy_port(dh_dev->parent, phy_port); + return; +} + +uint8_t zxdh_en_sf_get_pf_phy_port(struct dh_core_dev *dh_dev) +{ + struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev); + + return en_sf_dev->sf_ops->en_sf_get_pf_phy_port(dh_dev->parent); +} + +void zxdh_en_sf_set_rdma_netdev(struct dh_core_dev *dh_dev, void *data) +{ + struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev); + + en_sf_dev->netdev = data; + return; +} + +void *zxdh_en_sf_get_rdma_netdev(struct dh_core_dev *dh_dev) +{ + struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev); + + return en_sf_dev->netdev; +} + +struct zxdh_rdma_if rdma_ops = { + .get_rdma_netdev = zxdh_en_sf_get_rdma_netdev, +}; + +static int32_t zxdh_en_sf_request_port(struct dh_core_dev *dh_dev, void *data) +{ + struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev); + + return en_sf_dev->sf_ops->en_sf_request_port_info(dh_dev->parent, data); +} + +static int32_t zxdh_en_sf_release_port(struct dh_core_dev *dh_dev, uint32_t pnl_id) +{ + struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev); + + return en_sf_dev->sf_ops->en_sf_release_port_info(dh_dev->parent, pnl_id); +} + +static void zxdh_en_sf_set_bond_num(struct dh_core_dev *dh_dev, bool add) +{ + struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev); + + return en_sf_dev->sf_ops->en_sf_set_bond_num(dh_dev->parent, add); +} + +static bool zxdh_en_sf_if_init(struct dh_core_dev *dh_dev) +{ + struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev); + + return en_sf_dev->sf_ops->en_sf_if_init(dh_dev->parent); +} + +void zxdh_en_sf_set_init_comp_flag(struct dh_core_dev *dh_dev) +{ + struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev); + + en_sf_dev->sf_ops->en_sf_set_init_comp_flag(dh_dev->parent); + return; +} + +struct zxdh_ipv6_mac_tbl *zxdh_en_sf_get_ip6mac_tbl(struct dh_core_dev *dh_dev) +{ + struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev); + return en_sf_dev->sf_ops->en_sf_get_ip6mac_tbl(dh_dev->parent); +} + +struct zxdh_en_if en_ops = { + .get_channels_num = zxdh_en_sf_get_vqs_channels_num, + .create_vqs_channels = zxdh_en_sf_create_vqs_channels, + .destroy_vqs_channels = zxdh_en_sf_destroy_vqs_channels, + .switch_vqs_channel = zxdh_en_sf_switch_vqs_channel, + .vqs_channel_bind_handler = zxdh_en_sf_vqs_channel_bind_handler, + .vqs_channel_unbind_handler = zxdh_en_sf_vqs_channel_unbind_handler, + .vq_bind_channel = zxdh_en_sf_vq_bind_channel, + .vq_unbind_channel = zxdh_en_sf_vq_unbind_channel, + .vqs_bind_eqs = zxdh_en_sf_vqs_bind_eqs, + .vqs_unbind_eqs = zxdh_en_sf_vqs_unbind_eqs, + .vp_modern_map_vq_notify = zxdh_en_sf_map_vq_notify, + .vp_modern_unmap_vq_notify = zxdh_en_sf_unmap_vq_notify, + .activate_phy_vq = zxdh_en_sf_activate_phy_vq, + .get_phy_vq = zxdh_en_sf_get_phy_vq, + .release_phy_vq = zxdh_en_sf_release_phy_vq, + .set_status = zxdh_en_sf_set_status, + .get_status = zxdh_en_sf_get_status, + .set_vf_mac = zxdh_en_sf_set_vf_mac, + .get_vf_mac = zxdh_en_sf_get_vf_mac, + .set_mac = zxdh_en_sf_set_mac, + .get_mac = zxdh_en_sf_get_mac, + .get_features = zxdh_en_sf_get_features, + .set_features = zxdh_en_sf_set_features, + .get_queue_num = zxdh_en_sf_get_queue_num, + .get_queue_size = zxdh_en_sf_get_queue_size, + .set_queue_enable = zxdh_en_sf_set_queue_enable, + .get_epbdf = zxdh_en_sf_get_epbdf, + .get_vport = zxdh_en_sf_get_vport, + .get_pcie_id = zxdh_en_sf_get_pcie_id, + .get_slot_id = zxdh_en_sf_get_slot_id, + .is_bond = zxdh_en_sf_is_bond, + .is_upf = zxdh_en_sf_is_upf, + .get_coredev_type = zxdh_en_sf_get_coredev_type, + .get_pdev = zxdh_en_sf_get_pdev, + .get_bar_virt_addr = zxdh_en_sf_get_bar_virt_addr, + .msg_send_cmd = zxdh_en_sf_msg_send_cmd, + .async_eq_enable = zxdh_en_sf_async_eq_enable, + .get_vf_item = zxdh_en_sf_get_vf_item, + .set_pf_link_up = zxdh_en_sf_set_pf_link_up, + .get_pf_link_up = zxdh_en_sf_get_pf_link_up, + .update_pf_link_info = zxdh_en_sf_update_pf_link_info, + .get_pf_drv_msg = zxdh_en_sf_get_pf_drv_msg, + .set_vepa = zxdh_en_sf_set_vepa, + .get_vepa = zxdh_en_sf_get_vepa, + .get_link_info_from_vqm = zxdh_en_sf_get_link_info_from_vqm, + .set_vf_link_info = zxdh_en_sf_set_vf_link_info, + .request_port = zxdh_en_sf_request_port, + .release_port = zxdh_en_sf_release_port, + .set_bond_num = zxdh_en_sf_set_bond_num, + .if_init = zxdh_en_sf_if_init, + .set_pf_phy_port = zxdh_en_sf_set_pf_phy_port, + .set_rdma_netdev = zxdh_en_sf_set_rdma_netdev, + .get_pf_phy_port = zxdh_en_sf_get_pf_phy_port, + .set_init_comp_flag = zxdh_en_sf_set_init_comp_flag, + .get_ip6mac_tbl = zxdh_en_sf_get_ip6mac_tbl, +}; + +void zxdh_aux_adev_release(struct device *dev) +{ + +} + +int32_t zxdh_rdma_infos_request_reset(struct zxdh_rdma_dev_info *rdma_infos, enum zxdh_rdma_reset_type reset_type) +{ + return 0; +} + +static struct zxdh_rdma_dev_ops rdma_handle_ops = +{ + .request_reset = zxdh_rdma_infos_request_reset, +}; + +struct zxdh_rdma_dev_info *zxdh_rdma_infos_init(struct dh_core_dev *dh_dev, struct zxdh_auxiliary_device *adev) +{ + struct zxdh_en_container *en_container = container_of(adev, struct zxdh_en_container, adev); + struct zxdh_rdma_dev_info *rdma_infos = NULL; + + en_container->rdma_infos = kzalloc(sizeof(*en_container->rdma_infos), GFP_KERNEL); + if (unlikely(en_container->rdma_infos == NULL)) + { + LOG_ERR("en_container->rdma_infos kzalloc failed\n"); + return NULL; + } + + rdma_infos = en_container->rdma_infos; + rdma_infos->pdev = zxdh_en_sf_get_pdev(dh_dev); + rdma_infos->hw_addr = (uint8_t __iomem *)zxdh_en_sf_get_bar_virt_addr(dh_dev, 0); + rdma_infos->ver.major = ZXDH_MAJOR_VER; + rdma_infos->ver.minor = ZXDH_MINOR_VER; + rdma_infos->rdma_protocol = ZXDH_RDMA_PROTOCOL_IWARP; + rdma_infos->ops = &rdma_handle_ops; + rdma_infos->ftype = ZXDH_FUNCTION_TYPE_PF; + rdma_infos->vport_id = zxdh_en_sf_get_vport(dh_dev); + if (zxdh_en_sf_get_coredev_type(dh_dev) == DH_COREDEV_VF) + { + rdma_infos->ftype = ZXDH_FUNCTION_TYPE_VF; + } + + rdma_infos->msix_count = ZXDH_RDMA_CHANNELS_NUM; + rdma_infos->msix_entries.entry = ZXDH_RDMA_IRQ_START_IDX; + rdma_infos->msix_entries.vector = pci_irq_vector(rdma_infos->pdev, ZXDH_RDMA_IRQ_START_IDX); + + return rdma_infos; +} + +int32_t zxdh_net_adev_handle(struct dh_core_dev *dh_dev, struct zxdh_auxiliary_device *adev) +{ + struct zxdh_en_container *en_container = container_of(adev, struct zxdh_en_container, adev); + + adev->name = ZXDH_EN_DEV_ID_NAME; + adev->dev.parent = dh_dev->device; + en_container->rdma_infos = NULL; + en_container->ops = &en_ops; + + return 0; +} + +int32_t zxdh_rdma_adev_handle(struct dh_core_dev *dh_dev, struct zxdh_auxiliary_device *adev) +{ + struct zxdh_en_container *en_container = container_of(adev, struct zxdh_en_container, adev); + struct zxdh_rdma_dev_info *rdma_infos = NULL; + + adev->name = ZXDH_RDMA_DEV_NAME; + rdma_infos = zxdh_rdma_infos_init(dh_dev, adev); + if (unlikely(rdma_infos == NULL)) + { + LOG_ERR("zxdh_rdma_infos_init failed, return NULL\n"); + return -1; + } + rdma_infos->adev = adev; + adev->dev.parent = &rdma_infos->pdev->dev; + en_container->rdma_ops = &rdma_ops; + + return 0; +} + +struct zxdh_adev_handle_table zxdh_adev_handle_table[] = +{ + {NET_AUX_DEVICE, zxdh_net_adev_handle}, + {RDMA_AUX_DEVICE, zxdh_rdma_adev_handle}, +}; + +int32_t zxdh_adev_handle(struct dh_core_dev *dh_dev, struct zxdh_auxiliary_device *adev, enum AUX_DEVICE_TYPE adev_type) +{ + uint32_t i = 0; + int32_t ret = 0; + + for (i = 0; i < ARRAY_SIZE(zxdh_adev_handle_table); i++) + { + if((zxdh_adev_handle_table[i].adev_type == adev_type) && (zxdh_adev_handle_table[i].cb_fn)) + { + ret = zxdh_adev_handle_table[i].cb_fn(dh_dev, adev); + } + } + + return ret; +} + +static DEFINE_IDA(zxdh_aux_adev_ida); + +int32_t zxdh_aux_plug_aux_dev(struct dh_core_dev *dh_dev, enum AUX_DEVICE_TYPE adev_type) +{ + struct zxdh_auxiliary_device *adev = NULL; + struct zxdh_en_sf_device *en_sf_dev = NULL; + struct zxdh_en_container *en_container = NULL; + struct zxdh_rdma_dev_info *rdma_infos = NULL; + int32_t ret = 0; + en_sf_dev = dh_core_priv(dh_dev); + + en_container = kzalloc(sizeof(struct zxdh_en_container), GFP_KERNEL); + if (unlikely(en_container == NULL)) + { + LOG_ERR("sf_con kzalloc is null\n"); + return -ENOMEM; + } + + en_container->aux_id = ida_alloc(&zxdh_aux_adev_ida, GFP_KERNEL); + if (en_container->aux_id < 0) + { + LOG_ERR("failed to allocate device id for aux drvs\n"); + goto free_kzalloc; + } + + adev = &en_container->adev; + + adev->id = en_container->aux_id; + adev->dev.release = zxdh_aux_adev_release; + ret = zxdh_adev_handle(dh_dev, adev, adev_type); + if (ret != 0) + { + LOG_ERR("zxdh_adev_handle failed: %d\n", ret); + goto free_ida_alloc; + } + + if (en_sf_dev->aux_idx < 0) + goto free_rdma_infos_alloc; + en_sf_dev->adev[en_sf_dev->aux_idx] = adev; + en_sf_dev->aux_idx++; + + en_container->parent = dh_dev; + + ret = zxdh_auxiliary_device_init(adev); + if (ret != 0) + { + LOG_ERR("zxdh_auxiliary_device_init failed: %d\n", ret); + goto free_rdma_infos_alloc; + } + + ret = zxdh_auxiliary_device_add(adev); + if (ret != 0) + { + LOG_ERR("zxdh_auxiliary_device_add failed: %d\n", ret); + goto release_aux_init; + } + + return 0; + +release_aux_init: + zxdh_auxiliary_device_uninit(adev); +free_rdma_infos_alloc: + if (adev_type == RDMA_AUX_DEVICE) + { + kfree(rdma_infos); + rdma_infos = NULL; + } +free_ida_alloc: + ida_simple_remove(&zxdh_aux_adev_ida, en_container->aux_id); + en_container->aux_id = -1; +free_kzalloc: + kfree(en_container); + en_container = NULL; + return ret; +} + +void zxdh_aux_unplug_aux_dev(struct dh_core_dev *dh_dev) +{ + struct zxdh_en_sf_device *en_sf_dev = NULL; + struct zxdh_en_container *en_container = NULL; + int16_t i = 0; + + en_sf_dev = dh_core_priv(dh_dev); + for (i = en_sf_dev->aux_idx - 1; i >= 0; i--) + { + en_container = container_of(en_sf_dev->adev[i], struct zxdh_en_container, adev); + + zxdh_auxiliary_device_delete(en_sf_dev->adev[i]); + zxdh_auxiliary_device_uninit(en_sf_dev->adev[i]); + if (en_container->rdma_infos != NULL) + { + kfree(en_container->rdma_infos); + en_container->rdma_infos = NULL; + } + ida_simple_remove(&zxdh_aux_adev_ida, en_container->aux_id); + en_container->aux_id = -1; + kfree(en_container); + en_container = NULL; + } + + return; +} + +static int32_t zxdh_en_sf_dev_probe(struct zxdh_auxiliary_device *adev, const struct zxdh_auxiliary_device_id *id) +{ + int32_t err = 0; + struct zxdh_en_sf_container *sf_con = container_of(adev, struct zxdh_en_sf_container, adev); + struct dh_core_dev *dh_dev = NULL; + struct devlink *devlink = NULL; + struct zxdh_en_sf_device *en_sf_dev = NULL; + struct zxdh_en_sf_if *sf_ops = sf_con->ops; + + LOG_INFO("sf level driver probe start\n"); + + devlink = zxdh_devlink_alloc(&adev->dev, &dh_sf_devlink_ops, sizeof(struct zxdh_en_sf_device)); + if (devlink == NULL) + { + LOG_ERR("devlink alloc failed\n"); + return -ENOMEM; + } + + dh_dev = devlink_priv(devlink); + en_sf_dev = dh_core_priv(dh_dev); + dh_dev->parent = sf_con->dh_dev; + dh_dev->device = &adev->dev; + dh_dev->irq_table = dh_dev->parent->irq_table; + en_sf_dev->max_channels = sf_con->max_channels; + en_sf_dev->sf_ops = sf_ops; + en_sf_dev->aux_idx = 0; + sf_con->cdev = dh_dev; + dh_dev->devlink = devlink; + dh_dev->devlink_ops = &dh_sf_core_devlink_ops; + + err = dh_en_sf_eq_table_init(dh_dev); + if (err != 0) + { + LOG_ERR("Failed to alloc IRQs\n"); + goto err_eq_table_init; + } + + dh_en_sf_eq_table_create(dh_dev, sf_ops); + +#ifdef HAVE_DEVLINK_REGISTER_GET_1_PARAMS + zxdh_devlink_register(devlink); +#else + zxdh_devlink_register(devlink, &adev->dev); +#endif + + zxdh_aux_plug_aux_dev(dh_dev, NET_AUX_DEVICE); + zxdh_aux_plug_aux_dev(dh_dev, RDMA_AUX_DEVICE); + + LOG_INFO("sf level driver probe completed\n"); + + return 0; + +err_eq_table_init: + zxdh_devlink_free(devlink); + return err; +} + +static int32_t zxdh_en_sf_dev_remove(struct zxdh_auxiliary_device *adev) +{ + struct zxdh_en_sf_container *sf_con = container_of(adev, struct zxdh_en_sf_container, adev); + struct dh_core_dev *dh_dev = NULL; + struct devlink *devlink = NULL; + + LOG_INFO("sf level driver remove start\n"); + dh_dev = sf_con->cdev; + devlink = dh_dev->devlink; + + zxdh_aux_unplug_aux_dev(dh_dev); + zxdh_devlink_unregister(devlink); + dh_sf_eq_table_destroy(dh_dev); + dh_eq_table_cleanup(dh_dev); + zxdh_devlink_free(devlink); + LOG_INFO("sf level driver remove completed\n"); + + return 0; +} + +static void zxdh_en_sf_dev_shutdown(struct zxdh_auxiliary_device *adev) +{ + struct zxdh_en_sf_container *sf_con = container_of(adev, struct zxdh_en_sf_container, adev); + struct dh_core_dev *dh_dev = NULL; + struct devlink *devlink = NULL; + + LOG_INFO("sf level driver shutdown start\n"); +#ifdef CONFIG_ZXDH_SF + dh_dev = sf_con->cdev; + devlink = dh_dev->devlink; + + zxdh_devlink_unregister(devlink); + dh_sf_eq_table_destroy(dh_dev); + dh_eq_table_cleanup(dh_dev); + zxdh_devlink_free(devlink); +#endif + LOG_INFO("sf level driver shutdown completed\n"); +} + +static const struct zxdh_auxiliary_device_id zxdh_en_dev_id_table[] = { + { .name = ZXDH_PF_NAME "." ZXDH_PF_EN_SF_DEV_ID_NAME, }, + //{ .name = ZXDH_MPF_NAME "." ZXDH_MPF_EN_SF_DEV_ID_NAME, }, + { }, +}; + +MODULE_DEVICE_TABLE(zxdh_auxiliary, zxdh_en_dev_id_table); + +static struct zxdh_auxiliary_driver zxdh_en_sf_driver = { + .name = ZXDH_PF_EN_SF_DEV_ID_NAME, + .probe = zxdh_en_sf_dev_probe, + .remove = zxdh_en_sf_dev_remove, + .shutdown = zxdh_en_sf_dev_shutdown, + .id_table = zxdh_en_dev_id_table, +}; + +int32_t zxdh_en_sf_driver_register(void) +{ + int32_t err = 0; + + err = zxdh_auxiliary_driver_register(&zxdh_en_sf_driver); + if (err != 0) + { + goto err; + } + + return 0; + +err: + return err; +} + +void zxdh_en_sf_driver_unregister(void) +{ + zxdh_auxiliary_driver_unregister(&zxdh_en_sf_driver); +} diff --git a/src/net/drivers/net/ethernet/dinghai/en_sf.h b/src/net/drivers/net/ethernet/dinghai/en_sf.h new file mode 100644 index 0000000..028b951 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_sf.h @@ -0,0 +1,107 @@ +#ifndef __ZXDH_PF_EN_SF_H__ +#define __ZXDH_PF_EN_SF_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include +#include +#include + +#define ZXDH_MAJOR_VER 10 +#define ZXDH_MINOR_VER 1 +#define ZXDH_SF_ADEV_NUM 32 + +struct zxdh_rdma_dev_info; + +enum AUX_DEVICE_TYPE +{ + NET_AUX_DEVICE, + RDMA_AUX_DEVICE, +}; + +struct zxdh_adev_handle_table +{ + enum AUX_DEVICE_TYPE adev_type; + int32_t (*cb_fn)(struct dh_core_dev *dh_dev, struct zxdh_auxiliary_device *adev); +}; + +struct zxdh_ver_info +{ + uint16_t major; + uint16_t minor; + uint64_t support; +}; + +enum zxdh_function_type +{ + ZXDH_FUNCTION_TYPE_PF, + ZXDH_FUNCTION_TYPE_VF, +}; + +enum zxdh_rdma_protocol +{ + ZXDH_RDMA_PROTOCOL_IWARP = BIT(0), + ZXDH_RDMA_PROTOCOL_ROCEV2 = BIT(1), +}; + +struct zxdh_rdma_qos_params +{ + uint8_t reserve; +}; + +enum zxdh_rdma_reset_type +{ + ZXDH_RESET_MTU_CHANGE, + ZXDH_RESET_HW_ERROR, +}; + +struct zxdh_rdma_dev_ops +{ + int32_t (*request_reset)(struct zxdh_rdma_dev_info *rdma_infos, enum zxdh_rdma_reset_type reset_type); +}; + +/* auxiliary driver tailored information about the core PCI dev */ +struct zxdh_rdma_dev_info +{ + struct pci_dev *pdev; + struct zxdh_auxiliary_device *adev; + + uint8_t __iomem *hw_addr; + int32_t adev_info_id; + struct zxdh_ver_info ver; + + void *auxiliary_priv; + + enum zxdh_function_type ftype; + uint16_t vport_id; + /* Current active RDMA protocol */ + enum zxdh_rdma_protocol rdma_protocol; + + struct zxdh_rdma_qos_params qos_info; + + struct msix_entry msix_entries; + /* How many vectors are reserved for this device */ + uint16_t msix_count; + /* function pointers to be initialized by core PCI driver and called by auxiliary driver */ + struct zxdh_rdma_dev_ops *ops; +}; + +struct zxdh_en_sf_device { + int32_t max_channels; + struct zxdh_en_sf_if *sf_ops; + void *netdev; + + struct zxdh_auxiliary_device *adev[ZXDH_SF_ADEV_NUM]; + int32_t aux_idx; +}; + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_sf/devlink.c b/src/net/drivers/net/ethernet/dinghai/en_sf/devlink.c new file mode 100644 index 0000000..0a65b75 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_sf/devlink.c @@ -0,0 +1,131 @@ +#include +#include +#include "devlink.h" + + +struct devlink_ops dh_sf_devlink_ops = { + +}; + +enum { + DH_SF_PARAMS_MAX, +}; + +static int32_t __attribute__((unused)) sample_check(struct dh_core_dev *dev) +{ + return 1; +} + +enum dh_sf_devlink_param_id { + DH_SF_DEVLINK_PARAM_ID_BASE = DEVLINK_PARAM_GENERIC_ID_MAX, + DH_SF_DEVLINK_PARAM_ID_SAMPLE, +}; + + +static int32_t dh_devlink_sample_set(struct devlink *devlink, uint32_t id, + struct devlink_param_gset_ctx *ctx) +{ + struct dh_core_dev * __attribute__((unused)) dev = devlink_priv(devlink); + + return 0; +} + +static int32_t dh_devlink_sample_get(struct devlink *devlink, uint32_t id, + struct devlink_param_gset_ctx *ctx) +{ + struct dh_core_dev * __attribute__((unused)) dev = devlink_priv(devlink); + + return 0; +} + +#ifdef HAVE_DEVLINK_PARAM_REGISTER +static const struct devlink_params { + const char *name; + int32_t (*check)(struct dh_core_dev *dev); + struct devlink_param param; +} devlink_params[] = { + [DH_SF_PARAMS_MAX] = { .name = "sample", + .check = &sample_check, + .param = DEVLINK_PARAM_DRIVER(DH_SF_DEVLINK_PARAM_ID_SAMPLE, + "sample", DEVLINK_PARAM_TYPE_BOOL, + BIT(DEVLINK_PARAM_CMODE_RUNTIME),dh_devlink_sample_get, + dh_devlink_sample_set, + NULL), + } +}; + +static int32_t params_register(struct devlink *devlink) +{ + int32_t i = 0; + int32_t err = 0; + struct dh_core_dev *dh_dev = devlink_priv(devlink); + + for (i = 0; i < ARRAY_SIZE(devlink_params); i++) + { + if(devlink_params[i].check(dh_dev)) + { + err = devlink_param_register(devlink, &devlink_params[i].param); + if (err) + { + goto rollback; + } + } + } + + return 0; + +rollback: + if (i == 0) + { + return err; + } + + for (; i > 0; i--) + { + devlink_param_unregister(devlink, &devlink_params[i].param); + } + + return err; +} + +static int32_t params_unregister(struct devlink *devlink) +{ + int32_t i = 0; + + for (i = 0; i < ARRAY_SIZE(devlink_params); i++) + { + devlink_param_unregister(devlink, &devlink_params[i].param); + } + + return 0; +} +#else +static struct devlink_param devlink_params [] = { + [DH_SF_PARAMS_MAX] = DEVLINK_PARAM_DRIVER(DH_SF_DEVLINK_PARAM_ID_SAMPLE, + "sample", DEVLINK_PARAM_TYPE_BOOL, + BIT(DEVLINK_PARAM_CMODE_RUNTIME),dh_devlink_sample_get, + dh_devlink_sample_set, + NULL), +}; + +static int32_t params_register(struct devlink *devlink) +{ + struct dh_core_dev * __attribute__((unused)) dh_dev = devlink_priv(devlink); + int32_t err = 0; + + err = devlink_params_register(devlink, devlink_params, ARRAY_SIZE(devlink_params)); + + return err; +} +static int32_t params_unregister(struct devlink *devlink) +{ + devlink_params_unregister(devlink, devlink_params, ARRAY_SIZE(devlink_params)); + + return 0; +} +#endif + +struct dh_core_devlink_ops dh_sf_core_devlink_ops = { + .params_register = params_register, + .params_unregister = params_unregister +}; \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_sf/devlink.h b/src/net/drivers/net/ethernet/dinghai/en_sf/devlink.h new file mode 100644 index 0000000..6622934 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_sf/devlink.h @@ -0,0 +1,15 @@ +#ifndef __ZXDH_SF_DEVLINK_H__ +#define __ZXDH_SF_DEVLINK_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_sf/eq.c b/src/net/drivers/net/ethernet/dinghai/en_sf/eq.c new file mode 100644 index 0000000..1999aa4 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_sf/eq.c @@ -0,0 +1,391 @@ +#include +#include +#include +#include +#include +#include +#include "irq.h" +#include "eq.h" +#include "../en_sf.h" + + +static int32_t create_async_eqs(struct dh_core_dev *dev) +{ + return 0; +} + +int32_t dh_en_sf_eq_table_create(struct dh_core_dev *dev, struct zxdh_en_sf_if *ops) +{ + int32_t err; + + err = create_async_eqs(dev); + + return err; +} + +void dh_sf_eq_table_destroy(struct dh_core_dev *dev) +{ + return; +} + +void zxdh_set_queue_size(struct dh_core_dev *dh_dev, uint32_t index, uint16_t size) +{ + struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev); + + en_sf_dev->sf_ops->en_sf_set_queue_size(dh_dev->parent, index, size); +} + +void zxdh_queue_address(struct dh_core_dev *dh_dev, uint32_t index, + uint64_t desc_addr, uint64_t driver_addr, uint64_t device_addr) +{ + struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev); + + en_sf_dev->sf_ops->en_sf_set_queue_address(dh_dev->parent, index, desc_addr, driver_addr, device_addr); +} + +void zxdh_en_sf_activate_phy_vq(struct dh_core_dev *dh_dev, uint32_t phy_index, int32_t queue_size, uint64_t desc_addr, uint64_t avail_addr, uint64_t used_addr) +{ + zxdh_set_queue_size(dh_dev, phy_index, queue_size); + zxdh_queue_address(dh_dev, phy_index, desc_addr, avail_addr, used_addr); +} + +int32_t dh_en_sf_eq_table_init(struct dh_core_dev *dev) +{ + struct dh_eq_table *eq_table = &dev->eq_table; + struct dh_en_sf_eq_table *table_priv = NULL; + int32_t err = 0; + + table_priv = kvzalloc(sizeof(*table_priv), GFP_KERNEL); + if (unlikely(table_priv == NULL)) + { + LOG_ERR("dh_en_sf_eq_table kvzalloc failed\n"); + err = -ENOMEM; + goto err_table_priv; + } + dh_eq_table_init(dev, table_priv); + + return 0; + +err_table_priv: + kvfree(eq_table); + return err; +} + +static void vqs_irqs_release(struct dh_core_dev *dh_dev) +{ + struct dh_eq_table *table = &dh_dev->eq_table; + struct dh_en_sf_eq_table *sf_eq_table = table->priv; + struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev); + int32_t vqs_channel_num = 0; + + vqs_channel_num = zxdh_en_sf_get_vqs_channels_num(dh_dev); + + en_sf_dev->sf_ops->en_sf_affinity_irqs_release(dh_dev->parent, sf_eq_table->vq_irqs, vqs_channel_num); + + dh_irqs_release_vectors(sf_eq_table->vq_irqs, sf_eq_table->vq_irq_num); +} + +static void clean_vqs_eqs(struct dh_core_dev *dh_dev) +{ + struct dh_eq_table *table = &dh_dev->eq_table; + struct dh_en_sf_eq_table *sf_eq_table = table->priv; + struct dh_eq_vqs *eq; + struct dh_eq_vqs *n; + + list_for_each_entry_safe(eq, n, &sf_eq_table->vqs_eqs_list, list) + { + list_del(&eq->list); + kfree(eq); + } +} + +static void destroy_vqs_eqs(struct dh_core_dev *dh_dev, int32_t vqs_channel_num) +{ + struct dh_eq_table *table = &dh_dev->eq_table; + struct dh_en_sf_eq_table *sf_eq_table = table->priv; + struct dh_eq_vqs *eq; + struct dh_eq_vqs *n; + int32_t i = 0; + + list_for_each_entry_safe(eq, n, &sf_eq_table->vqs_eqs_list, list) + { + if (i <= vqs_channel_num) + { + dh_eq_disable(dh_dev, &eq->vq_s.core, &eq->vq_s.irq_nb); + } + i++; + } +} + +uint16_t zxdh_en_sf_get_vqs_channels_num(struct dh_core_dev *dh_dev) +{ + struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev); + uint16_t channels_num = 0; + + channels_num = en_sf_dev->sf_ops->en_sf_get_channels_num(dh_dev->parent); + + return channels_num; +} + +static int32_t create_map_eq(struct dh_core_dev *dev, struct dh_eq *eq, struct dh_eq_param *param) +{ + eq->irq = param->irq; + + return 0; +} + +void zxdh_en_sf_destroy_vqs_channels(struct dh_core_dev *dh_dev) +{ + struct dh_eq_table *table = &dh_dev->eq_table; + struct dh_en_sf_eq_table *sf_eq_table = table->priv; + + clean_vqs_eqs(dh_dev); + vqs_irqs_release(dh_dev); + kfree(sf_eq_table->vq_irqs); +} + +void zxdh_en_sf_switch_vqs_channel(struct dh_core_dev *dh_dev, int32_t channel, int32_t op) +{ + struct dh_eq_table *table = &dh_dev->eq_table; + struct dh_en_sf_eq_table *sf_eq_table = table->priv; + struct dh_irq *irq = sf_eq_table->vq_irqs[channel]; + struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev); + + en_sf_dev->sf_ops->en_sf_switch_irq(dh_dev->parent, irq->irqn, op); +} + +int32_t zxdh_en_sf_create_vqs_channels(struct dh_core_dev *dh_dev) +{ + struct dh_eq_table *table = &dh_dev->eq_table; + struct dh_en_sf_eq_table *sf_eq_table = table->priv; + struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev); + int32_t vqs_channel_num = 0; + int32_t i = 0; + struct dh_eq_vqs *eq_vqs = NULL; + int32_t err = 0; + + vqs_channel_num = zxdh_en_sf_get_vqs_channels_num(dh_dev); + + sf_eq_table->vq_irqs = kcalloc(vqs_channel_num, sizeof(*sf_eq_table->vq_irqs), GFP_KERNEL); + if (unlikely(sf_eq_table->vq_irqs == NULL)) + { + LOG_ERR("sf_eq_table->vq_irqs kcalloc null\n"); + return -ENOMEM; + } + + vqs_channel_num = en_sf_dev->sf_ops->en_sf_vq_irqs_request(dh_dev->parent, sf_eq_table->vq_irqs, vqs_channel_num); + if (vqs_channel_num < 0) + { + LOG_ERR("en_sf_vq_irqs_request failed: %d\n", vqs_channel_num); + kfree(sf_eq_table->vq_irqs); + return vqs_channel_num; + } + + sf_eq_table->vq_irq_num = vqs_channel_num; + + INIT_LIST_HEAD(&sf_eq_table->vqs_eqs_list); + + for (i = 0; i < vqs_channel_num; i++) + { + eq_vqs = kzalloc(sizeof(struct dh_eq_vqs), GFP_KERNEL); + if (unlikely(eq_vqs == NULL)) + { + LOG_ERR("eq_vqs %d kzalloc null\n", i); + err = -ENOMEM; + goto clean; + } + + INIT_LIST_HEAD(&eq_vqs->vqs); + + list_add_tail(&eq_vqs->list, &sf_eq_table->vqs_eqs_list); + } + + return vqs_channel_num; + +clean: + zxdh_en_sf_destroy_vqs_channels(dh_dev); + return err; +} + +void zxdh_en_sf_vqs_unbind_eqs(struct dh_core_dev *dh_dev, int32_t vqs_channel_num) +{ + struct dh_eq_table *table = &dh_dev->eq_table; + struct dh_en_sf_eq_table *sf_eq_table = table->priv; + struct dh_eq_vqs *eq; + struct dh_eq_vqs *n; + int32_t i = 0; + + list_for_each_entry_safe(eq, n, &sf_eq_table->vqs_eqs_list, list) + { + if (i++ <= vqs_channel_num) + { + list_del(&eq->vqs); + } + } + + return; +} + +int32_t zxdh_en_sf_vqs_bind_eqs(struct dh_core_dev *dh_dev, int32_t vqs_channel_num, struct list_head *vq_node) +{ + struct dh_eq_table *table = &dh_dev->eq_table; + struct dh_en_sf_eq_table *sf_eq_table = table->priv; + struct dh_eq_vqs *eq; + struct dh_eq_vqs *n; + int32_t i = 0; + + list_for_each_entry_safe(eq, n, &sf_eq_table->vqs_eqs_list, list) + { + if (i++ == vqs_channel_num) + { + list_add_tail(vq_node, &eq->vqs); + return 0; + } + } + + return -ENOENT; +} + +void __iomem *zxdh_en_sf_map_vq_notify(struct dh_core_dev *dh_dev, uint32_t index, resource_size_t *pa) +{ + struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev); + void __iomem *notify_addr = NULL; + + notify_addr = en_sf_dev->sf_ops->en_sf_map_vq_notify(dh_dev->parent, index, pa); + + return notify_addr; +} + +void zxdh_en_sf_unmap_vq_notify(struct dh_core_dev *dh_dev, void *priv) +{ + struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev); + + en_sf_dev->sf_ops->en_sf_unmap_vq_notify(dh_dev->parent, priv); +} + +void zxdh_en_sf_set_queue_enable(struct dh_core_dev *dh_dev, uint16_t index, bool enable) +{ + struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev); + + en_sf_dev->sf_ops->en_sf_set_queue_enable(dh_dev->parent, index, enable); +} + +uint16_t zxdh_en_sf_get_queue_vector(struct dh_core_dev *dh_dev, uint16_t channel, uint16_t queue_index) +{ + struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev); + struct dh_eq_table *table = &dh_dev->eq_table; + struct dh_en_sf_eq_table *sf_eq_table = table->priv; + int32_t msix_vec = ZXDH_MSI_NO_VECTOR; + + msix_vec = en_sf_dev->sf_ops->en_sf_get_queue_vector(dh_dev->parent, channel, &sf_eq_table->vqs_eqs_list, queue_index); + + return msix_vec; +} + +void zxdh_en_sf_vq_unbind_channel(struct dh_core_dev *dh_dev, int32_t queue_index) +{ + struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev); + + en_sf_dev->sf_ops->en_sf_release_queue_vector(dh_dev->parent, queue_index); +} + +int32_t zxdh_en_sf_vq_bind_channel(struct dh_core_dev *dh_dev, int32_t channel_num, int32_t queue_index) +{ + int32_t msix_vec = ZXDH_MSI_NO_VECTOR; + + msix_vec = zxdh_en_sf_get_queue_vector(dh_dev, channel_num, queue_index); + + if (msix_vec == ZXDH_MSI_NO_VECTOR) + { + return -EBUSY; + } + + return msix_vec; +} + +void zxdh_en_sf_vqs_channel_unbind_handler(struct dh_core_dev *dh_dev, int32_t vqs_channel_num) +{ + destroy_vqs_eqs(dh_dev, vqs_channel_num); + return; +} + +int32_t zxdh_en_sf_vqs_channel_bind_handler(struct dh_core_dev *dh_dev, int32_t vqs_channel_num, struct dh_vq_handler *handler) +{ + struct dh_eq_table *table = &dh_dev->eq_table; + struct dh_en_sf_eq_table *sf_eq_table = table->priv; + int32_t i = 0; + struct dh_eq_vqs *eq_vqs; + struct dh_eq_vqs *n; + int32_t err = 0; + + list_for_each_entry_safe(eq_vqs, n, &sf_eq_table->vqs_eqs_list, list) + { + if (i == vqs_channel_num) + { + struct dh_eq_param param = {}; + + eq_vqs->vq_s.irq_nb.notifier_call = handler->callback; + eq_vqs->vq_s.para = handler->para; + param = (struct dh_eq_param) { + .irq = sf_eq_table->vq_irqs[i], + .nent = 0, + }; + create_map_eq(dh_dev, &eq_vqs->vq_s.core, ¶m); + + err = dh_eq_enable(dh_dev, &eq_vqs->vq_s.core, &eq_vqs->vq_s.irq_nb); + if(err != 0) + { + LOG_ERR("dh_eq_enable failed: %d\n", err); + goto clean_eq; + } + return 0; + } + i++; + } + +clean_eq: + destroy_vqs_eqs(dh_dev, vqs_channel_num); + return err; +} + +uint32_t zxdh_en_sf_get_epbdf(struct dh_core_dev *dh_dev) +{ + struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev); + + return en_sf_dev->sf_ops->en_sf_get_epbdf(dh_dev->parent); +} + +uint16_t zxdh_en_sf_get_vport(struct dh_core_dev *dh_dev) +{ + struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev); + + return en_sf_dev->sf_ops->en_sf_get_vport(dh_dev->parent); +} + +enum dh_coredev_type zxdh_en_sf_get_coredev_type(struct dh_core_dev *dh_dev) +{ + struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev); + + return en_sf_dev->sf_ops->en_sf_get_coredev_type(dh_dev->parent); +} + +uint16_t zxdh_en_sf_get_pcie_id(struct dh_core_dev *dh_dev) +{ + struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev); + + return en_sf_dev->sf_ops->en_sf_get_pcie_id(dh_dev->parent); +} + +uint16_t zxdh_en_sf_get_slot_id(struct dh_core_dev *dh_dev) +{ + struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev); + + return en_sf_dev->sf_ops->en_sf_get_slot_id(dh_dev->parent); +} + +struct zxdh_vf_item *zxdh_en_sf_get_vf_item(struct dh_core_dev *dh_dev, uint16_t vf_idx) +{ + struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev); + + return en_sf_dev->sf_ops->en_sf_get_vf_item(dh_dev->parent, vf_idx); +} diff --git a/src/net/drivers/net/ethernet/dinghai/en_sf/eq.h b/src/net/drivers/net/ethernet/dinghai/en_sf/eq.h new file mode 100644 index 0000000..1f6127e --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_sf/eq.h @@ -0,0 +1,57 @@ +#ifndef __ZXDH_SF_EQ_H__ +#define __ZXDH_SF_EQ_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include +#include +#include + +void dh_en_sf_eq_table_destroy(struct dh_core_dev *dev); +int32_t dh_en_sf_eq_table_init(struct dh_core_dev *dev); +int32_t dh_en_sf_eq_table_create(struct dh_core_dev *dev, struct zxdh_en_sf_if *ops); +void dh_sf_eq_table_destroy(struct dh_core_dev *dev); + +uint16_t zxdh_en_sf_get_vqs_channels_num(struct dh_core_dev *dh_dev); +int32_t zxdh_en_sf_create_vqs_channels(struct dh_core_dev *dh_dev); +void zxdh_en_sf_destroy_vqs_channels(struct dh_core_dev *dh_dev); +void zxdh_en_sf_switch_vqs_channel(struct dh_core_dev *dh_dev, int32_t channel, int32_t op); +int32_t zxdh_en_sf_vqs_channel_bind_handler(struct dh_core_dev *dh_dev, int32_t vqs_channel_num, struct dh_vq_handler *handler); +void zxdh_en_sf_vqs_channel_unbind_handler(struct dh_core_dev *dh_dev, int32_t vqs_channel_num); +int32_t zxdh_en_sf_vq_bind_channel(struct dh_core_dev *dh_dev, int32_t channel_num, int32_t queue_index); +void zxdh_en_sf_vq_unbind_channel(struct dh_core_dev *dh_dev, int32_t queue_index); +int32_t zxdh_en_sf_vqs_bind_eqs(struct dh_core_dev *dh_dev, int32_t vqs_channel_num, struct list_head *vq_node); +void zxdh_en_sf_vqs_unbind_eqs(struct dh_core_dev *dh_dev, int32_t vqs_channel_num); +void __iomem *zxdh_en_sf_map_vq_notify(struct dh_core_dev *dh_dev, uint32_t index, resource_size_t *pa); +void zxdh_en_sf_unmap_vq_notify(struct dh_core_dev *dh_dev, void *priv); +void zxdh_en_sf_activate_phy_vq(struct dh_core_dev *dh_dev, uint32_t phy_index, int32_t queue_size, uint64_t desc_addr, uint64_t avail_addr, uint64_t used_addr); +void zxdh_en_sf_set_queue_enable(struct dh_core_dev *dh_dev, uint16_t index, bool enable); +uint32_t zxdh_en_sf_get_epbdf(struct dh_core_dev *dh_dev); +uint16_t zxdh_en_sf_get_vport(struct dh_core_dev *dh_dev); +uint16_t zxdh_en_sf_get_pcie_id(struct dh_core_dev *dh_dev); +uint16_t zxdh_en_sf_get_slot_id(struct dh_core_dev *dh_dev); +enum dh_coredev_type zxdh_en_sf_get_coredev_type(struct dh_core_dev *dh_dev); +void zxdh_en_sf_dpp_np_init(struct dh_core_dev *dh_dev, uint32_t vport); +struct pci_dev *zxdh_en_sf_get_pdev(struct dh_core_dev *dh_dev); +uint64_t zxdh_en_sf_get_bar_virt_addr(struct dh_core_dev *dh_dev, uint8_t bar_num); +int32_t zxdh_en_sf_do_cmd_exec(struct dh_core_dev *dh_dev, uint32_t dst, uint32_t id, uint32_t len, void *payload, void *ack); +struct zxdh_vf_item *zxdh_en_sf_get_vf_item(struct dh_core_dev *dh_dev, uint16_t vf_idx); + +struct dh_en_sf_eq_table { + struct dh_irq **vq_irqs; + struct dh_irq *async_irq; + struct dh_eq_async async_eq; + int32_t vq_irq_num; + struct list_head vqs_eqs_list; +}; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/en_sf/irq.c b/src/net/drivers/net/ethernet/dinghai/en_sf/irq.c new file mode 100644 index 0000000..3243540 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_sf/irq.c @@ -0,0 +1,5 @@ +#include +#include +#include +#include "irq.h" + diff --git a/src/net/drivers/net/ethernet/dinghai/en_sf/irq.h b/src/net/drivers/net/ethernet/dinghai/en_sf/irq.h new file mode 100644 index 0000000..250305b --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_sf/irq.h @@ -0,0 +1,24 @@ +#ifndef __ZXDH_PF_IRQ_H__ +#define __ZXDH_PF_IRQ_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +struct dh_irq* dh_pf_async_irq_request(struct dh_core_dev *dev); +int32_t dh_pf_irq_table_create(struct dh_core_dev *dev); +void dh_pf_irq_table_destroy(struct dh_core_dev *dev); +int32_t dh_pf_irq_table_init(struct dh_core_dev *dev); + +struct dh_en_sf_irq_table { + struct dh_irq_pool *sf_vq_pool; +}; + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/en_tsn/zxdh_tsn.c b/src/net/drivers/net/ethernet/dinghai/en_tsn/zxdh_tsn.c new file mode 100644 index 0000000..bc6ac94 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_tsn/zxdh_tsn.c @@ -0,0 +1,71 @@ +#include +#include +#include +#include "en_pf.h" +#include "zxdh_tsn.h" +#include "zxdh_tsn_reg.h" +#include "zxdh_tsn_comm.h" +#include "zxdh_tsn_ioctl.h" + +int32_t zxdh_tsn_init(struct dh_core_dev* dh_dev) +{ + struct zxdh_tsn_private* tsn = NULL; + struct zxdh_pf_device* pf_dev = NULL; + + ZXDH_TSN_COMM_CHECK_POINT(dh_dev); + ZXDH_TSN_COMM_CHECK_INDEX_EQUAL_RETURN_OK(dh_dev->coredev_type, DH_COREDEV_PF); + + pf_dev = dh_core_priv(dh_dev); + ZXDH_TSN_COMM_CHECK_POINT(pf_dev); + + tsn = kzalloc(sizeof(struct zxdh_tsn_private), GFP_KERNEL); + ZXDH_TSN_COMM_CHECK_POINT(tsn); + + pf_dev->tsn = tsn; + + memset(tsn, 0x00, sizeof(struct zxdh_tsn_private)); + + tsn->tsn_qbv_cap.ct_min = TSN_CYCLE_TIME_MIN; + tsn->tsn_qbv_cap.ct_max = TSN_CYCLE_TIME_MAX; + tsn->tsn_qbv_cap.it_min = TSN_INTERVAL_TIME_MIN; + tsn->tsn_qbv_cap.it_max = TSN_INTERVAL_TIME_MAX; + tsn->tsn_qbv_cap.gcl_num = TSN_PORT_GCL_NUM; + tsn->tsn_port_id.port_id = TSN_PORT_PORT_ID_DEF; + tsn->pci_ioremap_addr = pf_dev->pci_ioremap_addr[0]; + + spin_lock_init(&tsn->tsn_spin_lock); + + hrtimer_init(&tsn->tsn_qbv_change_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); + tsn->tsn_qbv_change_timer.function = zxdh_tsn_qbv_change_timer_callback; + + return TSN_OK; +} +EXPORT_SYMBOL(zxdh_tsn_init); + +void zxdh_tsn_exit(struct dh_core_dev* dh_dev) +{ + struct zxdh_tsn_private* tsn = NULL; + struct zxdh_pf_device* pf_dev = NULL; + + ZXDH_TSN_COMM_CHECK_POINT_RETURN_NONE(dh_dev); + ZXDH_TSN_COMM_CHECK_INDEX_EQUAL_RETURN_NONE(dh_dev->coredev_type, DH_COREDEV_PF); + + pf_dev = dh_core_priv(dh_dev); + ZXDH_TSN_COMM_CHECK_POINT_RETURN_NONE(pf_dev); + + tsn = pf_dev->tsn; + ZXDH_TSN_COMM_CHECK_POINT_RETURN_NONE(tsn); + + hrtimer_cancel(&tsn->tsn_qbv_change_timer); + + if (!IS_ERR_OR_NULL((void*)(tsn->tsn_reg_base_addr))) + { + tsn_port_disable_set(tsn); + tsn_port_phy_port_set(tsn, TSN_PORT_PORT_ID_DEF); + } + + kfree(tsn); +} +EXPORT_SYMBOL(zxdh_tsn_exit); + +MODULE_LICENSE("GPL"); diff --git a/src/net/drivers/net/ethernet/dinghai/en_tsn/zxdh_tsn.h b/src/net/drivers/net/ethernet/dinghai/en_tsn/zxdh_tsn.h new file mode 100644 index 0000000..077a483 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_tsn/zxdh_tsn.h @@ -0,0 +1,112 @@ +#ifndef __ZXDH_TSN_H__ +#define __ZXDH_TSN_H__ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include +#include +#include +#include + +#define TSN_PORT_RAM_NUM (2) +#define TSN_PORT_RAM_MAX (TSN_PORT_RAM_NUM -1) +#define TSN_PORT_GCL_NUM (250) +#define TSN_PORT_GCL_EXT_NUM (6) +#define TSN_PORT_GCL_MAX (TSN_PORT_GCL_NUM + TSN_PORT_GCL_EXT_NUM - 1) +#define TSN_PORT_QUEUE_NUM (8) +#define TSN_PORT_QUEUE_MAX (TSN_PORT_QUEUE_NUM - 1) +#define TSN_PORT_PORT_ID_NUM (4) +#define TSN_PORT_PORT_ID_MAX (TSN_PORT_PORT_ID_NUM - 1) +#define TSN_PORT_PORT_ID_DEF (15) +#define TSN_PORT_TIMER_ID_NUM (4) +#define TSN_PORT_TIMER_ID_MAX (TSN_PORT_TIMER_ID_NUM - 1) + +#define TSN_PORT_GATE_ENABLE (1) +#define TSN_PORT_GATE_DISABLE (0) +#define TSN_PORT_INIT_ENABLE (1) +#define TSN_PORT_INIT_DISABLE (0) +#define TSN_PORT_CHANGE_ENABLE (1) +#define TSN_PORT_CHANGE_DISABLE (0) + +#define TSN_PORT_GATE_IDLE (0) +#define TSN_PORT_GATE_RUNNING (1) +#define TSN_PORT_GATE_CHANGING (2) +#define TSN_PORT_GATE_PENDING (3) + +#define TSN_CYCLE_TIME_MIN (500000) +#define TSN_CYCLE_TIME_MAX (4000000000) +#define TSN_INTERVAL_TIME_MIN (1000) +#define TSN_INTERVAL_TIME_MAX (16000000) + +struct zxdh_tsn_port_id +{ + uint32_t port_id; +}; + +struct zxdh_tsn_timer_id +{ + uint32_t timer_id; +}; + +struct zxdh_tsn_qbv_cap +{ + uint64_t ct_min; + uint64_t ct_max; + uint32_t it_min; + uint32_t it_max; + uint32_t gcl_num; +}; + +struct zxdh_tsn_qbv_entry +{ + uint32_t gate_state; + uint32_t time_interval; +}; + +struct zxdh_tsn_qbv_basic +{ + uint64_t base_time; + uint64_t cycle_time; + uint32_t maxsdu[TSN_PORT_QUEUE_NUM]; + uint32_t guard_band_time[TSN_PORT_QUEUE_NUM]; + uint32_t control_list_length; + struct zxdh_tsn_qbv_entry control_list[TSN_PORT_GCL_NUM]; +}; + +struct zxdh_tsn_qbv_conf +{ + uint32_t enable; + struct zxdh_tsn_qbv_basic admin; +}; + +struct zxdh_tsn_qbv_status +{ + uint64_t current_time; + uint32_t current_status; + struct zxdh_tsn_qbv_basic oper; +}; + +struct zxdh_tsn_private +{ + uint32_t phy_port_id; + uint64_t pci_ioremap_addr; + uint64_t tsn_reg_base_addr; + + struct zxdh_tsn_port_id tsn_port_id; + struct zxdh_tsn_qbv_cap tsn_qbv_cap; + struct zxdh_tsn_qbv_conf tsn_qbv_conf[TSN_PORT_RAM_NUM]; + struct hrtimer tsn_qbv_change_timer; + + spinlock_t tsn_spin_lock; +}; + +int32_t zxdh_tsn_init(struct dh_core_dev* dh_dev); +void zxdh_tsn_exit(struct dh_core_dev* dh_dev); + +#ifdef __cplusplus +} +#endif + +#endif /* __ZXDH_TSN_H__ */ diff --git a/src/net/drivers/net/ethernet/dinghai/en_tsn/zxdh_tsn_comm.h b/src/net/drivers/net/ethernet/dinghai/en_tsn/zxdh_tsn_comm.h new file mode 100644 index 0000000..4a8e529 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_tsn/zxdh_tsn_comm.h @@ -0,0 +1,228 @@ +#ifndef __ZXDH_TSN_COMM_H__ +#define __ZXDH_TSN_COMM_H__ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include +#include "log.h" + +#ifndef TSN_OK +#define TSN_OK (0) +#endif + +#define ZXDH_TSN_COMM_CHECK_RC(rc)\ +do{\ + if(TSN_OK != (rc))\ + {\ + DH_LOG_ERR(MODULE_TSN, "[ErrorCode: %d] !\n", rc);\ + return rc;\ + }\ +}while(0) + +#define ZXDH_TSN_COMM_CHECK_RC_RETURN_NONE(rc)\ +do{\ + if(TSN_OK != (rc))\ + {\ + DH_LOG_ERR(MODULE_TSN, "[ErrorCode: %d] !\n", rc);\ + return;\ + }\ +}while(0) + +#define ZXDH_TSN_COMM_CHECK_RC_UNLOCK_RETURN_NONE(rc, lock)\ +do{\ + if(TSN_OK != (rc))\ + {\ + DH_LOG_ERR(MODULE_TSN, "[ErrorCode: %d] !\n", rc);\ + spin_unlock(lock);\ + return;\ + }\ +}while(0) + +#define ZXDH_TSN_COMM_CHECK_RC_UNLOCK_RETURN_VALUE(rc, lock, value)\ +do{\ + if(TSN_OK != (rc))\ + {\ + DH_LOG_ERR(MODULE_TSN, "[ErrorCode: %d] !\n", rc);\ + spin_unlock(lock);\ + return value;\ + }\ +}while(0) + +#define ZXDH_TSN_COMM_CHECK_RC_UNLOCKIRQ_MEMORY_FREE(rc, lock, flags, ptr)\ +do{\ + if(TSN_OK != (rc))\ + {\ + DH_LOG_ERR(MODULE_TSN, "[ErrorCode: %d] !\n", rc);\ + spin_unlock_irqrestore(lock, flags);\ + kfree(ptr);\ + return rc;\ + }\ +}while(0) + +#define ZXDH_TSN_COMM_CHECK_RC_UNLOCK_MEMORY_FREE_RETURN_NONE(rc, lock, ptr)\ +do{\ + if(TSN_OK != (rc))\ + {\ + DH_LOG_ERR(MODULE_TSN, "[ErrorCode: %d] !\n", rc);\ + spin_unlock(lock);\ + kfree(ptr);\ + return;\ + }\ +}while(0) + +#define ZXDH_TSN_COMM_CHECK_RC_UNLOCK_MEMORY_FREE_RETURN_VALUE(rc, lock, ptr, value)\ +do{\ + if(TSN_OK != (rc))\ + {\ + DH_LOG_ERR(MODULE_TSN, "[ErrorCode: %d] !\n", rc);\ + spin_unlock(lock);\ + kfree(ptr);\ + return value;\ + }\ +}while(0) + +#define ZXDH_TSN_COMM_CHECK_RC_MEMORY_FREE(rc, ptr)\ +do{\ + if(TSN_OK != (rc))\ + {\ + DH_LOG_ERR(MODULE_TSN, "[ErrorCode: %d] !\n", rc);\ + kfree(ptr);\ + return rc;\ + }\ +} while(0) + +#define ZXDH_TSN_COMM_CHECK_POINT(point)\ +do{\ + if(NULL == (point))\ + {\ + DH_LOG_ERR(MODULE_TSN, "[Error: POINT NULL] !\n");\ + return -EINVAL;\ + }\ +}while(0) + +#define ZXDH_TSN_COMM_CHECK_POINT_RETURN_NONE(point)\ +do{\ + if(NULL == (point))\ + {\ + DH_LOG_ERR(MODULE_TSN, "[Error: POINT NULL] !\n");\ + return;\ + }\ +}while(0) + +#define ZXDH_TSN_COMM_CHECK_POINT_RETURN_VALUE(point, value)\ +do{\ + if(NULL == (point))\ + {\ + DH_LOG_ERR(MODULE_TSN, "[Error: POINT NULL] !\n");\ + return value;\ + }\ +}while(0) + +#define ZXDH_TSN_COMM_CHECK_POINT_UNLOCK_RETURN_NONE(point, lock)\ +do{\ + if(NULL == (point))\ + {\ + DH_LOG_ERR(MODULE_TSN, "[Error: POINT NULL] !\n");\ + spin_unlock(lock);\ + return;\ + }\ +}while(0) + +#define ZXDH_TSN_COMM_CHECK_POINT_UNLOCK_RETURN_VALUE(point, lock, value)\ +do{\ + if(NULL == (point))\ + {\ + DH_LOG_ERR(MODULE_TSN, "[Error: POINT NULL] !\n");\ + spin_unlock(lock);\ + return value;\ + }\ +}while(0) + +#define ZXDH_TSN_COMM_CHECK_POINT_UNLOCK_MEMORY_FREE_RETURN_NONE(point, lock, ptr)\ +do{\ + if(NULL == (point))\ + {\ + DH_LOG_ERR(MODULE_TSN, "[Error: POINT NULL] !\n");\ + spin_unlock(lock);\ + kfree(ptr);\ + return;\ + }\ +}while(0) + +#define ZXDH_TSN_COMM_CHECK_INDEX(val, min, max)\ +do{\ + if(((val) < (min)) || ((val) > (max)))\ + {\ + DH_LOG_ERR(MODULE_TSN, "[Error: VALUE %u INVALID] [MIN %u MAX %u] !\n", val, min, max);\ + return -EINVAL;\ + }\ +}while(0) + +#define ZXDH_TSN_COMM_CHECK_INDEX_64(val, min, max)\ +do{\ + if(((val) < (min)) || ((val) > (max)))\ + {\ + DH_LOG_ERR(MODULE_TSN, "[Error: VALUE %llu INVALID] [MIN %llu MAX %llu] !\n", val, min, max);\ + return -EINVAL;\ + }\ +}while(0) + +#define ZXDH_TSN_COMM_CHECK_INDEX_MAX(val, max)\ +do{\ + if((val) > (max))\ + {\ + DH_LOG_ERR(MODULE_TSN, "[Error: VALUE %u INVALID] [MAX %u] !\n", val, max);\ + return -EINVAL;\ + }\ +}while(0) + +#define ZXDH_TSN_COMM_CHECK_INDEX_MAX_MEMORY_FREE(val, max, ptr)\ +do{\ + if((val) > (max))\ + {\ + DH_LOG_ERR(MODULE_TSN, "[Error: VALUE %u INVALID] [MAX %u] !\n", val, max);\ + kfree(ptr);\ + return -EINVAL;\ + }\ +}while(0) + +#define ZXDH_TSN_COMM_CHECK_INDEX_EQUAL(val, equal)\ +do{\ + if((val) != (equal))\ + {\ + DH_LOG_ERR(MODULE_TSN, "[Error: VALUE %u INVALID] [EQUAL %u] !\n", val, equal);\ + return -EINVAL;\ + }\ +}while(0) + +#define ZXDH_TSN_COMM_CHECK_INDEX_EQUAL_64(val, equal)\ +do{\ + if((val) != (equal))\ + {\ + DH_LOG_ERR(MODULE_TSN, "[Error: VALUE %llu INVALID] [EQUAL %llu] !\n", val, equal);\ + return -EINVAL;\ + }\ +}while(0) + +#define ZXDH_TSN_COMM_CHECK_INDEX_EQUAL_RETURN_OK(val, equal)\ +do{\ + if((val) != (equal))\ + {\ + return TSN_OK;\ + }\ +}while(0) + +#define ZXDH_TSN_COMM_CHECK_INDEX_EQUAL_RETURN_NONE(val, equal)\ +do{\ + if((val) != (equal))\ + {\ + return;\ + }\ +}while(0) + +#ifdef __cplusplus +} +#endif +#endif /* __ZXDH_TSN_COMM_H__ */ diff --git a/src/net/drivers/net/ethernet/dinghai/en_tsn/zxdh_tsn_ioctl.c b/src/net/drivers/net/ethernet/dinghai/en_tsn/zxdh_tsn_ioctl.c new file mode 100644 index 0000000..f11b5e0 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_tsn/zxdh_tsn_ioctl.c @@ -0,0 +1,695 @@ +#include +#include "log.h" +#include "en_pf.h" +#include "en_aux.h" +#include "zxdh_tsn.h" +#include "zxdh_tsn_reg.h" +#include "zxdh_tsn_ioctl.h" +#include "zxdh_tsn_comm.h" +#ifndef HAVE_IOPOLL_OPS +#include +#endif + +static int32_t zxdh_tsn_qbv_disable(struct zxdh_tsn_private* tsn) +{ + int32_t ret = 0; + + ret = tsn_port_disable_set(tsn); + ZXDH_TSN_COMM_CHECK_RC(ret); + + memset(tsn->tsn_qbv_conf, 0x00, sizeof(tsn->tsn_qbv_conf)); + + hrtimer_cancel(&tsn->tsn_qbv_change_timer); + + DH_LOG_INFO(MODULE_TSN, "tsn port id %u is disable.\n", tsn->tsn_port_id.port_id); + + return TSN_OK; +} + +static int32_t zxdh_tsn_port_id_set(struct zxdh_tsn_private* tsn, struct zxdh_tsn_msg* msg) +{ + int32_t ret = 0; + uint64_t reg_base_addr = 0; + struct zxdh_tsn_port_id* tsn_port_id = NULL; + + ZXDH_TSN_COMM_CHECK_INDEX_EQUAL(msg->len, (uint32_t)sizeof(struct zxdh_tsn_port_id)); + + tsn_port_id = (struct zxdh_tsn_port_id*)msg->data; + ZXDH_TSN_COMM_CHECK_POINT(tsn_port_id); + + ZXDH_TSN_COMM_CHECK_INDEX_MAX(tsn_port_id->port_id, TSN_PORT_PORT_ID_MAX); + + if (!IS_ERR_OR_NULL((void*)(tsn->tsn_reg_base_addr))) + { + ret = tsn_port_disable_set(tsn); + ZXDH_TSN_COMM_CHECK_RC(ret); + + ret = tsn_port_phy_port_set(tsn, TSN_PORT_PORT_ID_DEF); + ZXDH_TSN_COMM_CHECK_RC(ret); + } + + reg_base_addr = tsn->pci_ioremap_addr + TSN_PORT_REG_BAR_OFFSET + ((tsn_port_id->port_id) * TSN_PORT_REG_BAR_SIZE); + ret = tsn_write(reg_base_addr, TSN_PORT_PHY_PORT_SEL, tsn->phy_port_id); + ZXDH_TSN_COMM_CHECK_RC(ret); + + DH_LOG_INFO(MODULE_TSN, "tsn port id %u is bound to phy port id %u.\n", tsn_port_id->port_id, + tsn->phy_port_id); + tsn->tsn_reg_base_addr = reg_base_addr; + tsn->tsn_port_id.port_id = tsn_port_id->port_id; + + ret = zxdh_tsn_qbv_disable(tsn); + ZXDH_TSN_COMM_CHECK_RC(ret); + + return TSN_OK; +} + +static int32_t zxdh_tsn_port_id_get(struct zxdh_tsn_private* tsn, struct zxdh_tsn_msg* msg) +{ + struct zxdh_tsn_port_id tsn_port_id; + + ZXDH_TSN_COMM_CHECK_INDEX_EQUAL(msg->len, (uint32_t)sizeof(struct zxdh_tsn_port_id)); + + tsn_port_id.port_id = tsn->tsn_port_id.port_id; + + memcpy(msg->data, &tsn_port_id, sizeof(struct zxdh_tsn_port_id)); + + return TSN_OK; +} + +static int32_t zxdh_tsn_timer_id_set(struct zxdh_tsn_private* tsn, struct zxdh_tsn_msg* msg) +{ + int32_t ret = 0; + struct zxdh_tsn_timer_id* tsn_timer_id = NULL; + + ZXDH_TSN_COMM_CHECK_INDEX_EQUAL(msg->len, (uint32_t)sizeof(struct zxdh_tsn_timer_id)); + + tsn_timer_id = (struct zxdh_tsn_timer_id*)msg->data; + ZXDH_TSN_COMM_CHECK_POINT(tsn_timer_id); + + ZXDH_TSN_COMM_CHECK_INDEX_MAX(tsn_timer_id->timer_id, TSN_PORT_TIMER_ID_MAX); + + ret = tsn_port_timer_id_set(tsn, tsn_timer_id->timer_id); + ZXDH_TSN_COMM_CHECK_RC(ret); + + DH_LOG_INFO(MODULE_TSN, "tsn port id %u is bound to timer id %u.\n", tsn->tsn_port_id.port_id, + tsn_timer_id->timer_id); + + return TSN_OK; +} + +static int32_t zxdh_tsn_timer_id_get(struct zxdh_tsn_private* tsn, struct zxdh_tsn_msg* msg) +{ + int32_t ret = 0; + struct zxdh_tsn_timer_id tsn_timer_id; + + ZXDH_TSN_COMM_CHECK_INDEX_EQUAL(msg->len, (uint32_t)sizeof(struct zxdh_tsn_timer_id)); + + ret = tsn_port_timer_id_get(tsn, &tsn_timer_id.timer_id); + ZXDH_TSN_COMM_CHECK_RC(ret); + + memcpy(msg->data, &tsn_timer_id, sizeof(struct zxdh_tsn_timer_id)); + + return TSN_OK; +} + +static int32_t zxdh_tsn_qbv_conf_check(struct zxdh_tsn_private* tsn, struct zxdh_tsn_qbv_conf* tsn_qbv_conf) +{ + uint32_t index = 0; + uint64_t time_interval_sum = 0; + struct zxdh_tsn_qbv_basic* tsn_qbv_basic = &tsn_qbv_conf->admin; + struct zxdh_tsn_qbv_entry* tsn_qbv_entry = tsn_qbv_conf->admin.control_list; + + ZXDH_TSN_COMM_CHECK_INDEX_MAX(tsn_qbv_conf->enable, TSN_PORT_GATE_ENABLE); + + ZXDH_TSN_COMM_CHECK_INDEX_64(tsn_qbv_basic->cycle_time, tsn->tsn_qbv_cap.ct_min, tsn->tsn_qbv_cap.ct_max); + + ZXDH_TSN_COMM_CHECK_INDEX(tsn_qbv_basic->control_list_length, 1, tsn->tsn_qbv_cap.gcl_num); + + for (index = 0; index < tsn_qbv_basic->control_list_length; index++) + { + ZXDH_TSN_COMM_CHECK_INDEX(tsn_qbv_entry[index].time_interval, tsn->tsn_qbv_cap.it_min, tsn->tsn_qbv_cap.it_max); + time_interval_sum += tsn_qbv_entry[index].time_interval; + } + + ZXDH_TSN_COMM_CHECK_INDEX_EQUAL_64(tsn_qbv_basic->cycle_time, time_interval_sum); + + return TSN_OK; +} + +static int32_t zxdh_tsn_qbv_base_time_cal(struct zxdh_tsn_private* tsn, struct zxdh_tsn_qbv_conf* tsn_qbv_conf_oper, + struct zxdh_tsn_qbv_conf* tsn_qbv_conf_admin, + uint64_t real_tod_time, uint32_t status) +{ + uint64_t oper_base_time = 0; + uint64_t oper_cycle_time = 0; + uint64_t admin_base_time = 0; + uint64_t admin_cycle_time = 0; + uint64_t cycle_time_extension = 0; + + ZXDH_TSN_COMM_CHECK_POINT(tsn_qbv_conf_oper); + ZXDH_TSN_COMM_CHECK_POINT(tsn_qbv_conf_admin); + + oper_base_time = tsn_qbv_conf_oper->admin.base_time; + oper_cycle_time = tsn_qbv_conf_oper->admin.cycle_time; + + admin_base_time = tsn_qbv_conf_admin->admin.base_time; + admin_cycle_time = tsn_qbv_conf_admin->admin.cycle_time; + + if (real_tod_time >= admin_base_time) + { + admin_base_time += admin_cycle_time * (((real_tod_time - admin_base_time) / admin_cycle_time) + 1); + if ((admin_base_time - real_tod_time) < TSN_SOFT_RESERVED_TIME) + { + admin_base_time += TSN_RESERVED_TIME(admin_cycle_time); + } + DH_LOG_INFO(MODULE_TSN, "tsn port id %u admin_base_time change to %llu real_tod_time %llu diff %llu.\n", + tsn->tsn_port_id.port_id, admin_base_time, real_tod_time, admin_base_time - real_tod_time); + } + else if ((admin_base_time - real_tod_time) < TSN_SOFT_RESERVED_TIME) + { + admin_base_time += TSN_RESERVED_TIME(admin_cycle_time); + DH_LOG_INFO(MODULE_TSN, "tsn port id %u admin_base_time change to %llu real_tod_time %llu diff %llu.\n", + tsn->tsn_port_id.port_id, admin_base_time, real_tod_time, admin_base_time - real_tod_time); + } + + if (status != TSN_PORT_GATE_IDLE) + { + if (real_tod_time >= oper_base_time) + { + cycle_time_extension = (admin_base_time - oper_base_time) % oper_cycle_time; + if (cycle_time_extension < TSN_CYCLE_TIME_EXTENSION_MIN) + { + cycle_time_extension += oper_cycle_time; + } + DH_LOG_INFO(MODULE_TSN, "tsn port id %u cycle_time_extension %llu .\n", tsn->tsn_port_id.port_id, cycle_time_extension); + + if (cycle_time_extension < oper_cycle_time) + { + oper_base_time += oper_cycle_time * (((real_tod_time - oper_base_time) / oper_cycle_time) + 1); + if ((oper_base_time - real_tod_time) < TSN_SOFT_RESERVED_TIME) + { + oper_base_time += TSN_RESERVED_TIME(oper_cycle_time); + } + } + else + { + oper_base_time += oper_cycle_time * (((real_tod_time - oper_base_time) / oper_cycle_time) + 2); + if ((oper_base_time - oper_cycle_time - real_tod_time) < TSN_SOFT_RESERVED_TIME) + { + oper_base_time += TSN_RESERVED_TIME(oper_cycle_time); + } + } + DH_LOG_INFO(MODULE_TSN, "tsn port id %u oper_base_time change to %llu real_tod_time %llu diff %llu.\n", + tsn->tsn_port_id.port_id, oper_base_time, real_tod_time, oper_base_time - real_tod_time); + } + + if (oper_base_time > admin_base_time) + { + if (cycle_time_extension == oper_cycle_time) + { + admin_base_time += admin_cycle_time * (((oper_base_time - admin_base_time) / admin_cycle_time)); + } + else + { + admin_base_time += admin_cycle_time * (((oper_base_time - admin_base_time) / admin_cycle_time) + 1); + } + DH_LOG_INFO(MODULE_TSN, "tsn port id %u admin_base_time change to %llu oper_base_time %llu diff %llu.\n", + tsn->tsn_port_id.port_id, admin_base_time, oper_base_time, admin_base_time - oper_base_time); + } + } + + tsn_qbv_conf_admin->admin.base_time = admin_base_time; + + return TSN_OK; +} + +static int32_t zxdh_tsn_qbv_cycle_time_extension_cal(struct zxdh_tsn_private* tsn, struct zxdh_tsn_qbv_conf* tsn_qbv_conf_oper, + struct zxdh_tsn_qbv_conf* tsn_qbv_conf_admin, + uint64_t* cycle_time_extension) +{ + uint64_t admin_base_time = 0; + uint64_t oper_base_time = 0; + uint64_t oper_cycle_time = 0; + + ZXDH_TSN_COMM_CHECK_POINT(tsn_qbv_conf_oper); + ZXDH_TSN_COMM_CHECK_POINT(tsn_qbv_conf_admin); + ZXDH_TSN_COMM_CHECK_POINT(cycle_time_extension); + + oper_base_time = tsn_qbv_conf_oper->admin.base_time; + oper_cycle_time = tsn_qbv_conf_oper->admin.cycle_time; + + admin_base_time = tsn_qbv_conf_admin->admin.base_time; + + if ((admin_base_time > oper_base_time) && (oper_cycle_time != 0)) + { + oper_base_time += oper_cycle_time * ((admin_base_time - oper_base_time) / oper_cycle_time); + if (admin_base_time >= oper_base_time) + { + *cycle_time_extension = admin_base_time - oper_base_time; + if ((*cycle_time_extension) < TSN_CYCLE_TIME_EXTENSION_MIN) + { + *cycle_time_extension += oper_cycle_time; + } + DH_LOG_INFO(MODULE_TSN, "tsn port id %u cycle_time_extension %llu.\n", tsn->tsn_port_id.port_id, + *cycle_time_extension); + return TSN_OK; + } + } + + return -EINVAL; +} + +static int32_t zxdh_tsn_qbv_gate_status_get(struct zxdh_tsn_private* tsn, uint32_t* p_ram_n_idle, uint32_t* p_status) +{ + int32_t ret = 0; + uint32_t init_finish = 0; + uint32_t change_en = 0; + uint32_t ram_n = 0; + uint32_t status = 0; + uint32_t enable = 0; + uint64_t admin_base_time = 0; + uint64_t real_tod_time = 0; + uint64_t cycle_time_extension = 0; + + ret = tsn_port_status_get(tsn, &ram_n, &status); + ZXDH_TSN_COMM_CHECK_RC(ret); + + ret = tsn_port_init_finish_get(tsn, &init_finish); + ZXDH_TSN_COMM_CHECK_RC(ret); + + ret = tsn_port_change_en_get(tsn, &change_en); + ZXDH_TSN_COMM_CHECK_RC(ret); + + ret = tsn_port_enable_get(tsn, &enable); + ZXDH_TSN_COMM_CHECK_RC(ret); + + *p_ram_n_idle = (ram_n == 0)? 0 : ((ram_n == 1)? 1 : ((ram_n == 2)? 0 : 2)); + ZXDH_TSN_COMM_CHECK_INDEX_MAX(*p_ram_n_idle, TSN_PORT_RAM_MAX); + + if ((status == 0) && (init_finish == 0) && (change_en == 0) && (enable == TSN_PORT_GATE_DISABLE)) + { + *p_status = TSN_PORT_GATE_IDLE; + DH_LOG_INFO(MODULE_TSN, "tsn port id %u idle status %u init_finish %u change_en %u enable %u.\n", + tsn->tsn_port_id.port_id, status, init_finish, change_en, enable); + return TSN_OK; + } + + if (((status >= 3) && (status <= 8)) && (init_finish == 0) && (change_en == 0) && (enable == TSN_PORT_GATE_ENABLE)) + { + *p_status = TSN_PORT_GATE_RUNNING; + DH_LOG_INFO(MODULE_TSN, "tsn port id %u running status %u init_finish %u change_en %u enable %u.\n", + tsn->tsn_port_id.port_id, status, init_finish, change_en, enable); + return TSN_OK; + } + + if (((status >= 3) && (status <= 8)) && (init_finish == 0) && (change_en == 1) && (enable == TSN_PORT_GATE_ENABLE)) + { + admin_base_time = tsn->tsn_qbv_conf[*p_ram_n_idle].admin.base_time; + ret = zxdh_tsn_qbv_cycle_time_extension_cal(tsn, &tsn->tsn_qbv_conf[TSN_RAM_N_IN_SERVICE(*p_ram_n_idle)], + &tsn->tsn_qbv_conf[*p_ram_n_idle], &cycle_time_extension); + ZXDH_TSN_COMM_CHECK_RC(ret); + + ret = tsn_port_real_tod_time_get(tsn, &real_tod_time); + ZXDH_TSN_COMM_CHECK_RC(ret); + + if ((admin_base_time - cycle_time_extension - TSN_SOFT_RESERVED_TIME) > real_tod_time) + { + *p_status = TSN_PORT_GATE_CHANGING; + DH_LOG_INFO(MODULE_TSN, "tsn port id %u changing status %u init_finish %u change_en %u enable %u.\n", + tsn->tsn_port_id.port_id, status, init_finish, change_en, enable); + return TSN_OK; + } + } + + *p_status = TSN_PORT_GATE_PENDING; + DH_LOG_INFO(MODULE_TSN, "tsn port id %u pending status %u init_finish %u change_en %u enable %u.\n", + tsn->tsn_port_id.port_id, status, init_finish, change_en, enable); + return TSN_OK; +} + +static int32_t zxdh_tsn_qbv_basic_set(struct zxdh_tsn_private* tsn, struct zxdh_tsn_qbv_conf* tsn_qbv_conf, uint32_t ram_n_idle) +{ + int32_t ret = 0; + uint32_t index = 0; + + ret = tsn_port_default_gate_set(tsn, 0x00); + ZXDH_TSN_COMM_CHECK_RC(ret); + + ret = tsn_port_change_gate_set(tsn, 0xFF); + ZXDH_TSN_COMM_CHECK_RC(ret); + + for (index = 0; index < TSN_PORT_QUEUE_NUM; index++) + { + ret = tsn_port_guard_band_time_set(tsn, index, tsn_qbv_conf->admin.guard_band_time[index]); + ZXDH_TSN_COMM_CHECK_RC(ret); + } + + ret = tsn_port_gcl_num_set(tsn, ram_n_idle, tsn_qbv_conf->admin.control_list_length); + ZXDH_TSN_COMM_CHECK_RC(ret); + + for (index = 0; index < tsn_qbv_conf->admin.control_list_length; index++) + { + ret = tsn_port_gcl_control_set(tsn, ram_n_idle, index, tsn_qbv_conf->admin.control_list[index].gate_state, + tsn_qbv_conf->admin.control_list[index].time_interval); + ZXDH_TSN_COMM_CHECK_RC(ret); + } + + ret = tsn_port_enable_set(tsn, TSN_PORT_GATE_ENABLE); + ZXDH_TSN_COMM_CHECK_RC(ret); + + ret = tsn_port_cycle_time_set(tsn, tsn_qbv_conf->admin.cycle_time); + ZXDH_TSN_COMM_CHECK_RC(ret); + + ret = tsn_port_base_time_set(tsn, tsn_qbv_conf->admin.base_time); + ZXDH_TSN_COMM_CHECK_RC(ret); + + return TSN_OK; +} + +static int32_t zxdh_tsn_qbv_change_set(struct zxdh_tsn_private* tsn, struct zxdh_tsn_qbv_conf* tsn_qbv_conf, uint32_t ram_n_idle) +{ + int32_t ret = 0; + + ret = tsn_port_change_en_set(tsn, TSN_PORT_CHANGE_DISABLE); + ZXDH_TSN_COMM_CHECK_RC(ret); + + ret = zxdh_tsn_qbv_basic_set(tsn, tsn_qbv_conf, ram_n_idle); + ZXDH_TSN_COMM_CHECK_RC(ret); + + ret = tsn_port_change_en_set(tsn, TSN_PORT_CHANGE_ENABLE); + ZXDH_TSN_COMM_CHECK_RC(ret); + + return TSN_OK; +} + +static int32_t zxdh_tsn_qbv_set(struct zxdh_tsn_private* tsn, struct zxdh_tsn_msg* msg) +{ + int32_t ret = 0; + uint32_t ram_n_idle = 0; + uint32_t status = 0; + uint64_t cycle_time_extension = 0; + uint64_t real_tod_time = 0; + uint64_t expires_in_nanosecond = 0; + struct zxdh_tsn_qbv_conf* tsn_qbv_conf = NULL; + + ZXDH_TSN_COMM_CHECK_INDEX_EQUAL(msg->len, (uint32_t)sizeof(struct zxdh_tsn_qbv_conf)); + + tsn_qbv_conf = (struct zxdh_tsn_qbv_conf*)msg->data; + ZXDH_TSN_COMM_CHECK_POINT(tsn_qbv_conf); + + if (tsn_qbv_conf->enable == TSN_PORT_GATE_DISABLE) + { + ret = zxdh_tsn_qbv_disable(tsn); + ZXDH_TSN_COMM_CHECK_RC(ret); + return TSN_OK; + } + + ret = zxdh_tsn_qbv_conf_check(tsn, tsn_qbv_conf); + ZXDH_TSN_COMM_CHECK_RC(ret); + + ret = zxdh_tsn_qbv_gate_status_get(tsn, &ram_n_idle, &status); + ZXDH_TSN_COMM_CHECK_RC(ret); + + if (status == TSN_PORT_GATE_PENDING) + { + DH_LOG_ERR(MODULE_TSN, "tsn port id %u is pending.\n", tsn->tsn_port_id.port_id); + return -EBUSY; + } + + ret = tsn_port_real_tod_time_get(tsn, &real_tod_time); + ZXDH_TSN_COMM_CHECK_RC(ret); + + ret = zxdh_tsn_qbv_base_time_cal(tsn, &tsn->tsn_qbv_conf[TSN_RAM_N_IN_SERVICE(ram_n_idle)], tsn_qbv_conf, + real_tod_time, status); + ZXDH_TSN_COMM_CHECK_RC(ret); + + if (status == TSN_PORT_GATE_IDLE) + { + ret = zxdh_tsn_qbv_basic_set(tsn, tsn_qbv_conf, ram_n_idle); + ZXDH_TSN_COMM_CHECK_RC(ret); + + ret = tsn_port_init_finish_set(tsn, TSN_PORT_INIT_ENABLE); + ZXDH_TSN_COMM_CHECK_RC(ret); + + memcpy(&tsn->tsn_qbv_conf[ram_n_idle], tsn_qbv_conf, sizeof(struct zxdh_tsn_qbv_conf)); + + DH_LOG_INFO(MODULE_TSN, "tsn port id %u ram %u is enable.\n", tsn->tsn_port_id.port_id, ram_n_idle); + } + else + { + ret = zxdh_tsn_qbv_cycle_time_extension_cal(tsn, &tsn->tsn_qbv_conf[TSN_RAM_N_IN_SERVICE(ram_n_idle)], tsn_qbv_conf, + &cycle_time_extension); + ZXDH_TSN_COMM_CHECK_RC(ret); + + // if (cycle_time_extension < TSN_CYCLE_TIME_EXTENSION_MIN) + // { + // ret = zxdh_tsn_qbv_change_set(tsn, tsn_qbv_conf, ram_n_idle); + // ZXDH_TSN_COMM_CHECK_RC(ret); + + // memcpy(&tsn->tsn_qbv_conf[ram_n_idle], tsn_qbv_conf, sizeof(struct zxdh_tsn_qbv_conf)); + + // hrtimer_cancel(&tsn->tsn_qbv_change_timer); + + // DH_LOG_INFO(MODULE_TSN, "tsn port id %u ram %u is going to change.\n", tsn->tsn_port_id.port_id, ram_n_idle); + // } + // else + // { + memcpy(&tsn->tsn_qbv_conf[ram_n_idle], tsn_qbv_conf, sizeof(struct zxdh_tsn_qbv_conf)); + + expires_in_nanosecond = tsn->tsn_qbv_conf[ram_n_idle].admin.base_time - cycle_time_extension - + TSN_TIMER_RESERVED_TIME - real_tod_time; + hrtimer_start(&tsn->tsn_qbv_change_timer, ns_to_ktime(expires_in_nanosecond), HRTIMER_MODE_REL); + + DH_LOG_INFO(MODULE_TSN, "tsn port id %u timer wake up in %llu ns later.\n", tsn->tsn_port_id.port_id, expires_in_nanosecond); + // } + } + + return TSN_OK; +} + +static int32_t zxdh_tsn_qbv_status_get(struct zxdh_tsn_private* tsn, struct zxdh_tsn_msg* msg) +{ + int32_t ret = 0; + uint32_t ram_n_idle = 0; + struct zxdh_tsn_qbv_status* tsn_qbv_status; + + ZXDH_TSN_COMM_CHECK_INDEX_EQUAL(msg->len, (uint32_t)sizeof(struct zxdh_tsn_qbv_status)); + + tsn_qbv_status = (struct zxdh_tsn_qbv_status*)msg->data; + ZXDH_TSN_COMM_CHECK_POINT(tsn_qbv_status); + + ret = zxdh_tsn_qbv_gate_status_get(tsn, &ram_n_idle, &tsn_qbv_status->current_status); + ZXDH_TSN_COMM_CHECK_RC(ret); + + ret = tsn_port_real_tod_time_get(tsn, &tsn_qbv_status->current_time); + ZXDH_TSN_COMM_CHECK_RC(ret); + + memcpy(&tsn_qbv_status->oper, &tsn->tsn_qbv_conf[TSN_RAM_N_IN_SERVICE(ram_n_idle)].admin, sizeof(struct zxdh_tsn_qbv_basic)); + + return TSN_OK; +} + +static int32_t zxdh_tsn_qbv_cycle_time_extension_set(struct zxdh_tsn_private* tsn, struct zxdh_tsn_qbv_conf* tsn_qbv_conf, + uint64_t cycle_time_extension, uint32_t ram_n_idle) +{ + int32_t ret = 0; + uint32_t index = 0; + uint32_t gate_state = 0; + uint32_t change_gate_status = 0; + uint32_t time_interval = 0; + uint64_t real_tod_time = 0; + uint64_t cycle_time_reserved = 0; + + ret = tsn_port_real_tod_time_get(tsn, &real_tod_time); + ZXDH_TSN_COMM_CHECK_RC(ret); + + memcpy(tsn_qbv_conf, &tsn->tsn_qbv_conf[TSN_RAM_N_IN_SERVICE(ram_n_idle)], sizeof(struct zxdh_tsn_qbv_conf)); + + if (cycle_time_extension > tsn_qbv_conf->admin.cycle_time) + { + cycle_time_reserved = cycle_time_extension - tsn_qbv_conf->admin.cycle_time; + + for (index = 0; index < TSN_PORT_GCL_EXT_NUM; index++) + { + gate_state = tsn_qbv_conf->admin.control_list[index].gate_state; + time_interval = tsn_qbv_conf->admin.control_list[index].time_interval; + + ret = tsn_port_gcl_control_set(tsn, ram_n_idle, tsn_qbv_conf->admin.control_list_length + index, + gate_state, time_interval); + ZXDH_TSN_COMM_CHECK_RC(ret); + + if (cycle_time_reserved > time_interval) + { + cycle_time_reserved = cycle_time_reserved - time_interval; + continue; + } + break; + } + } + + tsn_qbv_conf->admin.base_time = tsn->tsn_qbv_conf[ram_n_idle].admin.base_time - cycle_time_extension + + TSN_HW_RESERVED_TIME; + tsn_qbv_conf->admin.cycle_time = cycle_time_extension - (2 * TSN_HW_RESERVED_TIME); + tsn_qbv_conf->admin.control_list[0].time_interval -= TSN_HW_RESERVED_TIME; + + ret = zxdh_tsn_qbv_change_set(tsn, tsn_qbv_conf, ram_n_idle); + ZXDH_TSN_COMM_CHECK_RC(ret); + + change_gate_status = tsn_qbv_conf->admin.control_list[0].gate_state; + ret = tsn_port_change_gate_set(tsn, change_gate_status); + ZXDH_TSN_COMM_CHECK_RC(ret); + + ret = tsn_port_gcl_num_set(tsn, ram_n_idle, tsn_qbv_conf->admin.control_list_length + index + 1); + ZXDH_TSN_COMM_CHECK_RC(ret); + + DH_LOG_INFO(MODULE_TSN, "tsn port id %u admin_base_time %llu real_tod_time %llu diff %llu.\n", tsn->tsn_port_id.port_id, + tsn_qbv_conf->admin.base_time, real_tod_time, tsn_qbv_conf->admin.base_time - real_tod_time); + DH_LOG_INFO(MODULE_TSN, "tsn port id %u ram %u is going to change in timer.\n", tsn->tsn_port_id.port_id, ram_n_idle); + + return TSN_OK; +} + +enum hrtimer_restart zxdh_tsn_qbv_change_timer_callback(struct hrtimer* t) +{ + int32_t ret = 0; + uint32_t change_en = 0; + uint32_t change_gate_status = 0; + uint32_t ram_n_idle = 0; + uint32_t status = 0; + uint64_t real_tod_time = 0; + uint64_t cycle_time_extension = 0; + struct zxdh_tsn_private* tsn = NULL; + struct zxdh_tsn_qbv_conf* tsn_qbv_conf = NULL; + + tsn = container_of(t, struct zxdh_tsn_private, tsn_qbv_change_timer); + ZXDH_TSN_COMM_CHECK_POINT_RETURN_VALUE(tsn, HRTIMER_NORESTART); + + spin_lock(&tsn->tsn_spin_lock); + + tsn_qbv_conf = kzalloc(sizeof(struct zxdh_tsn_qbv_conf), GFP_KERNEL); + ZXDH_TSN_COMM_CHECK_POINT_UNLOCK_RETURN_VALUE(tsn_qbv_conf, &tsn->tsn_spin_lock, HRTIMER_NORESTART); + + ret = zxdh_tsn_qbv_gate_status_get(tsn, &ram_n_idle, &status); + ZXDH_TSN_COMM_CHECK_RC_UNLOCK_MEMORY_FREE_RETURN_VALUE(ret, &tsn->tsn_spin_lock, tsn_qbv_conf, HRTIMER_NORESTART); + + ret = zxdh_tsn_qbv_cycle_time_extension_cal(tsn, &tsn->tsn_qbv_conf[TSN_RAM_N_IN_SERVICE(ram_n_idle)], + &tsn->tsn_qbv_conf[ram_n_idle], &cycle_time_extension); + ZXDH_TSN_COMM_CHECK_RC_UNLOCK_MEMORY_FREE_RETURN_VALUE(ret, &tsn->tsn_spin_lock, tsn_qbv_conf, HRTIMER_NORESTART); + + ret = zxdh_tsn_qbv_cycle_time_extension_set(tsn, tsn_qbv_conf, cycle_time_extension, ram_n_idle); + ZXDH_TSN_COMM_CHECK_RC_UNLOCK_MEMORY_FREE_RETURN_VALUE(ret, &tsn->tsn_spin_lock, tsn_qbv_conf, HRTIMER_NORESTART); + + ret = readx_poll_timeout_atomic(readl, ((const volatile void *)((tsn->tsn_reg_base_addr) + TSN_PORT_CHANGE_EN)), + change_en, (change_en == 0), 1, (TSN_TIMER_RESERVED_TIME * 2)); + ZXDH_TSN_COMM_CHECK_RC_UNLOCK_MEMORY_FREE_RETURN_VALUE(ret, &tsn->tsn_spin_lock, tsn_qbv_conf, HRTIMER_NORESTART); + + change_gate_status = tsn_qbv_conf->admin.control_list[tsn_qbv_conf->admin.control_list_length - 1].gate_state; + + ret = tsn_port_real_tod_time_get(tsn, &real_tod_time); + ZXDH_TSN_COMM_CHECK_RC_UNLOCK_MEMORY_FREE_RETURN_VALUE(ret, &tsn->tsn_spin_lock, tsn_qbv_conf, HRTIMER_NORESTART); + + memcpy(tsn_qbv_conf, &tsn->tsn_qbv_conf[ram_n_idle], sizeof(struct zxdh_tsn_qbv_conf)); + memcpy(&tsn->tsn_qbv_conf[ram_n_idle], &tsn->tsn_qbv_conf[TSN_RAM_N_IN_SERVICE(ram_n_idle)], sizeof(struct zxdh_tsn_qbv_conf)); + + ret = zxdh_tsn_qbv_gate_status_get(tsn, &ram_n_idle, &status); + ZXDH_TSN_COMM_CHECK_RC_UNLOCK_MEMORY_FREE_RETURN_VALUE(ret, &tsn->tsn_spin_lock, tsn_qbv_conf, HRTIMER_NORESTART); + + ret = zxdh_tsn_qbv_change_set(tsn, tsn_qbv_conf, ram_n_idle); + ZXDH_TSN_COMM_CHECK_RC_UNLOCK_MEMORY_FREE_RETURN_VALUE(ret, &tsn->tsn_spin_lock, tsn_qbv_conf, HRTIMER_NORESTART); + + ret = tsn_port_change_gate_set(tsn, change_gate_status); + ZXDH_TSN_COMM_CHECK_RC_UNLOCK_MEMORY_FREE_RETURN_VALUE(ret, &tsn->tsn_spin_lock, tsn_qbv_conf, HRTIMER_NORESTART); + + memcpy(&tsn->tsn_qbv_conf[ram_n_idle], tsn_qbv_conf, sizeof(struct zxdh_tsn_qbv_conf)); + + DH_LOG_INFO(MODULE_TSN, "tsn port id %u admin_base_time %llu real_tod_time %llu diff %llu.\n", tsn->tsn_port_id.port_id, + tsn_qbv_conf->admin.base_time, real_tod_time, tsn_qbv_conf->admin.base_time - real_tod_time); + + kfree(tsn_qbv_conf); + + spin_unlock(&tsn->tsn_spin_lock); + + DH_LOG_INFO(MODULE_TSN, "tsn port id %u ram %u is going to change in timer.\n", tsn->tsn_port_id.port_id, ram_n_idle); + + return HRTIMER_NORESTART; +} + +static struct zxdh_tsn_ioctl_table tsn_ioctl_table[] = +{ + {TSN_PORT_ID_SET, zxdh_tsn_port_id_set}, + {TSN_PORT_ID_GET, zxdh_tsn_port_id_get}, + {TSN_TIMER_ID_SET, zxdh_tsn_timer_id_set}, + {TSN_TIMER_ID_GET, zxdh_tsn_timer_id_get}, + {TSN_QBV_CONF_SET, zxdh_tsn_qbv_set}, + {TSN_QBV_STATUS_GET, zxdh_tsn_qbv_status_get}, +}; + +int32_t zxdh_en_tsn_func(struct net_device* netdev, struct ifreq* ifr) +{ + int32_t ret = 0; + uint32_t index = 0; + uint32_t table_size = 0; + uint64_t start_time = 0; + uint64_t end_time = 0; + unsigned long flags = 0; + struct zxdh_en_priv* en_priv = NULL; + struct zxdh_en_device* en_dev = NULL; + struct zxdh_pf_device* pf_dev = NULL; + struct zxdh_tsn_private* tsn = NULL; + struct zxdh_tsn_msg* msg = NULL; + + ZXDH_TSN_COMM_CHECK_POINT(netdev); + ZXDH_TSN_COMM_CHECK_POINT(ifr); + + en_priv = netdev_priv(netdev); + ZXDH_TSN_COMM_CHECK_POINT(en_priv); + + en_dev = &en_priv->edev; + ZXDH_TSN_COMM_CHECK_POINT(en_dev); + + pf_dev = dh_core_priv(en_dev->parent->parent); + ZXDH_TSN_COMM_CHECK_POINT(pf_dev); + + tsn = pf_dev->tsn; + ZXDH_TSN_COMM_CHECK_POINT(tsn); + + msg = kzalloc(sizeof(struct zxdh_tsn_msg), GFP_KERNEL); + ZXDH_TSN_COMM_CHECK_POINT(msg); + + ret = unlikely(copy_from_user(msg, ifr->ifr_ifru.ifru_data, sizeof(struct zxdh_tsn_msg))); + ZXDH_TSN_COMM_CHECK_RC_MEMORY_FREE(ret, msg); + + table_size = (uint32_t)(sizeof(tsn_ioctl_table) / sizeof(struct zxdh_tsn_ioctl_table)); + + for(index = 0; index < table_size; index++) + { + if((msg->cmd == tsn_ioctl_table[index].cmd) && (tsn_ioctl_table[index].func != NULL)) + { + spin_lock_irqsave(&tsn->tsn_spin_lock, flags); + + start_time = ktime_get_ns(); + + ret = tsn_ioctl_table[index].func(tsn, msg); + ZXDH_TSN_COMM_CHECK_RC_UNLOCKIRQ_MEMORY_FREE(ret, &tsn->tsn_spin_lock, flags, msg); + + end_time = ktime_get_ns(); + + spin_unlock_irqrestore(&tsn->tsn_spin_lock, flags); + + DH_LOG_INFO(MODULE_TSN, "tsn port id %u cmd %u total take up %lld ns.\n", tsn->tsn_port_id.port_id, + msg->cmd, end_time - start_time); + break; + } + } + + ZXDH_TSN_COMM_CHECK_INDEX_MAX_MEMORY_FREE(index, table_size - 1, msg); + + ret = unlikely(copy_to_user(ifr->ifr_ifru.ifru_data, msg, sizeof(struct zxdh_tsn_msg))); + ZXDH_TSN_COMM_CHECK_RC_MEMORY_FREE(ret, msg); + + kfree(msg); + + return TSN_OK; +} + +EXPORT_SYMBOL_GPL(zxdh_en_tsn_func); diff --git a/src/net/drivers/net/ethernet/dinghai/en_tsn/zxdh_tsn_ioctl.h b/src/net/drivers/net/ethernet/dinghai/en_tsn/zxdh_tsn_ioctl.h new file mode 100644 index 0000000..e7140be --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_tsn/zxdh_tsn_ioctl.h @@ -0,0 +1,48 @@ +#ifndef __ZXDH_TSN_IOCTL_H__ +#define __ZXDH_TSN_IOCTL_H__ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include +#include + +#define TSN_MSG_LEN (4096 - 8) + +#define TSN_PORT_ID_SET (0) +#define TSN_PORT_ID_GET (1) +#define TSN_TIMER_ID_SET (2) +#define TSN_TIMER_ID_GET (3) +#define TSN_QBV_CONF_SET (4) +#define TSN_QBV_STATUS_GET (5) + +#define TSN_SOFT_RESERVED_TIME (500000) +#define TSN_HW_RESERVED_TIME (200) +#define TSN_TIMER_RESERVED_TIME (300000) +#define TSN_RESERVED_TIME(CT) ((((CT) < TSN_SOFT_RESERVED_TIME)? \ + ((TSN_SOFT_RESERVED_TIME / (CT)) + 1) : 1) * (CT)) +#define TSN_RAM_N_IN_SERVICE(RAM_N_IDLE) ((~(RAM_N_IDLE)) & 1) + +#define TSN_CYCLE_TIME_EXTENSION_MIN (500000) + +struct zxdh_tsn_msg +{ + uint32_t cmd; + uint32_t len; + uint8_t data[TSN_MSG_LEN]; +}; + +struct zxdh_tsn_ioctl_table +{ + int32_t cmd; + int32_t (*func)(struct zxdh_tsn_private* tsn, struct zxdh_tsn_msg* msg); +}; + +enum hrtimer_restart zxdh_tsn_qbv_change_timer_callback(struct hrtimer* t); +int32_t zxdh_en_tsn_func(struct net_device* netdev, struct ifreq* ifr); + +#ifdef __cplusplus +} +#endif +#endif /* __ZXDH_TSN_IOCTL_H__ */ diff --git a/src/net/drivers/net/ethernet/dinghai/en_tsn/zxdh_tsn_reg.c b/src/net/drivers/net/ethernet/dinghai/en_tsn/zxdh_tsn_reg.c new file mode 100644 index 0000000..fc9ef4d --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_tsn/zxdh_tsn_reg.c @@ -0,0 +1,428 @@ +#include +#include "zxdh_tsn.h" +#include "zxdh_tsn_reg.h" +#include "zxdh_tsn_comm.h" + +int32_t tsn_read(uint64_t base_addr, uint32_t offset, uint32_t* p_val) +{ + if (IS_ERR_OR_NULL((void*)(base_addr))) + { + DH_LOG_ERR(MODULE_TSN, "base_addr 0x%llx invalid.\n", base_addr); + return -EINVAL; + } + + *p_val = readl((const volatile void *)(base_addr + offset)); + + return TSN_OK; +} + +int32_t tsn_write(uint64_t base_addr, uint32_t offset, uint32_t val) +{ + if (IS_ERR_OR_NULL((void*)(base_addr))) + { + DH_LOG_ERR(MODULE_TSN, "base_addr 0x%llx invalid.\n", base_addr); + return -EINVAL; + } + + writel(val, (volatile void *)(base_addr + offset)); + + return TSN_OK; +} + +int32_t tsn_reg_read(struct zxdh_tsn_private* tsn, uint32_t offset, uint32_t* p_val) +{ + int32_t ret = 0; + + ZXDH_TSN_COMM_CHECK_POINT(tsn); + ZXDH_TSN_COMM_CHECK_POINT(p_val); + + ret = tsn_read(tsn->tsn_reg_base_addr, offset, p_val); + ZXDH_TSN_COMM_CHECK_RC(ret); + + return TSN_OK; +} + +int32_t tsn_reg_write(struct zxdh_tsn_private* tsn, uint32_t offset, uint32_t val) +{ + int32_t ret = 0; + + ZXDH_TSN_COMM_CHECK_POINT(tsn); + + ret = tsn_write(tsn->tsn_reg_base_addr, offset, val); + ZXDH_TSN_COMM_CHECK_RC(ret); + + return TSN_OK; +} + +int32_t tsn_port_enable_set(struct zxdh_tsn_private* tsn, uint32_t enable) +{ + int32_t ret = 0; + + ret = tsn_reg_write(tsn, TSN_PORT_QBV_ENABLE, enable); + ZXDH_TSN_COMM_CHECK_RC(ret); + + return TSN_OK; +} + +int32_t tsn_port_enable_get(struct zxdh_tsn_private* tsn, uint32_t* p_enable) +{ + int32_t ret = 0; + + ret = tsn_reg_read(tsn, TSN_PORT_QBV_ENABLE, p_enable); + ZXDH_TSN_COMM_CHECK_RC(ret); + + return TSN_OK; +} + +int32_t tsn_port_phy_port_set(struct zxdh_tsn_private* tsn, uint32_t phy_port) +{ + int32_t ret = 0; + + ret = tsn_reg_write(tsn, TSN_PORT_PHY_PORT_SEL, phy_port); + ZXDH_TSN_COMM_CHECK_RC(ret); + + return TSN_OK; +} + +int32_t tsn_port_phy_port_get(struct zxdh_tsn_private* tsn, uint32_t* p_phy_port) +{ + int32_t ret = 0; + + ret = tsn_reg_read(tsn, TSN_PORT_PHY_PORT_SEL, p_phy_port); + ZXDH_TSN_COMM_CHECK_RC(ret); + + return TSN_OK; +} + +int32_t tsn_port_timer_id_set(struct zxdh_tsn_private* tsn, uint32_t timer_id) +{ + int32_t ret = 0; + + ret = tsn_reg_write(tsn, TSN_PORT_TIME_SEL, timer_id); + ZXDH_TSN_COMM_CHECK_RC(ret); + + return TSN_OK; +} + +int32_t tsn_port_timer_id_get(struct zxdh_tsn_private* tsn, uint32_t* p_time_id) +{ + int32_t ret = 0; + + ret = tsn_reg_read(tsn, TSN_PORT_TIME_SEL, p_time_id); + ZXDH_TSN_COMM_CHECK_RC(ret); + + return TSN_OK; +} + +int32_t tsn_port_status_get(struct zxdh_tsn_private* tsn, uint32_t* p_ram_n, uint32_t* p_status) +{ + int32_t ret = 0; + uint32_t val = 0; + + ZXDH_TSN_COMM_CHECK_POINT(p_ram_n); + ZXDH_TSN_COMM_CHECK_POINT(p_status); + + ret = tsn_reg_read(tsn, TSN_PORT_READ_RAM_N, &val); + ZXDH_TSN_COMM_CHECK_RC(ret); + + *p_ram_n = val & 0x3; + *p_status = (val & 0x3C) >> 2; + + return TSN_OK; +} + +int32_t tsn_port_base_time_l_set(struct zxdh_tsn_private* tsn, uint32_t base_time) +{ + int32_t ret = 0; + + ret = tsn_reg_write(tsn, TSN_PORT_BASE_TIME_L, base_time); + ZXDH_TSN_COMM_CHECK_RC(ret); + + return TSN_OK; +} + +int32_t tsn_port_base_time_h_set(struct zxdh_tsn_private* tsn, uint32_t base_time) +{ + int32_t ret = 0; + + ret = tsn_reg_write(tsn, TSN_PORT_BASE_TIME_H, base_time); + ZXDH_TSN_COMM_CHECK_RC(ret); + + return TSN_OK; +} + +int32_t tsn_port_base_time_set(struct zxdh_tsn_private* tsn, uint64_t base_time) +{ + int32_t ret = 0; + uint32_t base_time_l = (uint32_t)((base_time) & 0xffffffff); + uint32_t base_time_h = (uint32_t)((base_time >> 32) & 0xffffffff); + + ret = tsn_port_base_time_l_set(tsn, base_time_l); + ZXDH_TSN_COMM_CHECK_RC(ret); + + ret = tsn_port_base_time_h_set(tsn, base_time_h); + ZXDH_TSN_COMM_CHECK_RC(ret); + + return TSN_OK; +} + +int32_t tsn_port_base_time_get(struct zxdh_tsn_private* tsn, uint64_t* p_base_time) +{ + int32_t ret = 0; + uint32_t base_time_l = 0; + uint32_t base_time_h = 0; + + ZXDH_TSN_COMM_CHECK_POINT(p_base_time); + + ret = tsn_reg_read(tsn, TSN_PORT_BASE_TIME_L, &base_time_l); + ZXDH_TSN_COMM_CHECK_RC(ret); + + ret = tsn_reg_read(tsn, TSN_PORT_BASE_TIME_H, &base_time_h); + ZXDH_TSN_COMM_CHECK_RC(ret); + + *p_base_time = (uint64_t)((((uint64_t)(base_time_h)) << 32) | ((uint64_t)(base_time_l))); + + return TSN_OK; +} + +int32_t tsn_port_cycle_time_l_set(struct zxdh_tsn_private* tsn, uint32_t cycle_time) +{ + int32_t ret = 0; + + ret = tsn_reg_write(tsn, TSN_PORT_CYCLE_TIME_L, cycle_time); + ZXDH_TSN_COMM_CHECK_RC(ret); + + return TSN_OK; +} + +int32_t tsn_port_cycle_time_h_set(struct zxdh_tsn_private* tsn, uint32_t cycle_time) +{ + int32_t ret = 0; + + ret = tsn_reg_write(tsn, TSN_PORT_CYCLE_TIME_H, cycle_time); + ZXDH_TSN_COMM_CHECK_RC(ret); + + return TSN_OK; +} + +int32_t tsn_port_cycle_time_set(struct zxdh_tsn_private* tsn, uint64_t cycle_time) +{ + int32_t ret = 0; + uint32_t cycle_time_l = (uint32_t)((cycle_time) & 0x000fffff); + uint32_t cycle_time_h = (uint32_t)((cycle_time >> 20) & 0x000fffff); + + ret = tsn_port_cycle_time_l_set(tsn, cycle_time_l); + ZXDH_TSN_COMM_CHECK_RC(ret); + + ret = tsn_port_cycle_time_h_set(tsn, cycle_time_h); + ZXDH_TSN_COMM_CHECK_RC(ret); + + return TSN_OK; +} + +int32_t tsn_port_cycle_time_get(struct zxdh_tsn_private* tsn, uint64_t* p_cycle_time) +{ + int32_t ret = 0; + uint32_t cycle_time_l = 0; + uint32_t cycle_time_h = 0; + + ZXDH_TSN_COMM_CHECK_POINT(p_cycle_time); + + ret = tsn_reg_read(tsn, TSN_PORT_CYCLE_TIME_L, &cycle_time_l); + ZXDH_TSN_COMM_CHECK_RC(ret); + + ret = tsn_reg_read(tsn, TSN_PORT_CYCLE_TIME_H, &cycle_time_h); + ZXDH_TSN_COMM_CHECK_RC(ret); + + *p_cycle_time = (uint64_t)((((uint64_t)(cycle_time_h)) << 20) | ((uint64_t)(cycle_time_l))); + + return TSN_OK; +} + +int32_t tsn_port_guard_band_time_set(struct zxdh_tsn_private* tsn, uint32_t cos, uint32_t band_time) +{ + int32_t ret = 0; + + ZXDH_TSN_COMM_CHECK_INDEX_MAX(cos, TSN_PORT_QUEUE_MAX); + + ret = tsn_reg_write(tsn, TSN_PORT_GUARD_BAND_TIME + (cos * 4), band_time); + ZXDH_TSN_COMM_CHECK_RC(ret); + + return TSN_OK; +} + +int32_t tsn_port_guard_band_time_get(struct zxdh_tsn_private* tsn, uint32_t cos, uint32_t* p_band_time) +{ + int32_t ret = 0; + + ZXDH_TSN_COMM_CHECK_INDEX_MAX(cos, TSN_PORT_QUEUE_MAX); + + ret = tsn_reg_read(tsn, TSN_PORT_GUARD_BAND_TIME + (cos * 4), p_band_time); + ZXDH_TSN_COMM_CHECK_RC(ret); + + return TSN_OK; +} + +int32_t tsn_port_default_gate_set(struct zxdh_tsn_private* tsn, uint32_t gate_state) +{ + int32_t ret = 0; + + ret = tsn_reg_write(tsn, TSN_PORT_DEFAULT_GATE_EN, gate_state); + ZXDH_TSN_COMM_CHECK_RC(ret); + + return TSN_OK; +} + +int32_t tsn_port_default_gate_get(struct zxdh_tsn_private* tsn, uint32_t* p_gate_state) +{ + int32_t ret = 0; + + ret = tsn_reg_read(tsn, TSN_PORT_DEFAULT_GATE_EN, p_gate_state); + ZXDH_TSN_COMM_CHECK_RC(ret); + + return TSN_OK; +} + +int32_t tsn_port_change_gate_set(struct zxdh_tsn_private* tsn, uint32_t gate_state) +{ + int32_t ret = 0; + + ret = tsn_reg_write(tsn, TSN_PORT_CHANGE_GATE_EN, gate_state); + ZXDH_TSN_COMM_CHECK_RC(ret); + + return TSN_OK; +} + +int32_t tsn_port_init_finish_set(struct zxdh_tsn_private* tsn, uint32_t init_finish) +{ + int32_t ret = 0; + + ret = tsn_reg_write(tsn, TSN_PORT_INIT_FINISH, init_finish); + ZXDH_TSN_COMM_CHECK_RC(ret); + + return TSN_OK; +} + +int32_t tsn_port_init_finish_get(struct zxdh_tsn_private* tsn, uint32_t* p_init_finish) +{ + int32_t ret = 0; + + ret = tsn_reg_read(tsn, TSN_PORT_INIT_FINISH, p_init_finish); + ZXDH_TSN_COMM_CHECK_RC(ret); + + return TSN_OK; +} + +int32_t tsn_port_change_en_set(struct zxdh_tsn_private* tsn, uint32_t change_en) +{ + int32_t ret = 0; + + ret = tsn_reg_write(tsn, TSN_PORT_CHANGE_EN, change_en); + ZXDH_TSN_COMM_CHECK_RC(ret); + + return TSN_OK; +} + +int32_t tsn_port_change_en_get(struct zxdh_tsn_private* tsn, uint32_t* p_change_en) +{ + int32_t ret = 0; + + ret = tsn_reg_read(tsn, TSN_PORT_CHANGE_EN, p_change_en); + ZXDH_TSN_COMM_CHECK_RC(ret); + + return TSN_OK; +} + +int32_t tsn_port_gcl_num_set(struct zxdh_tsn_private* tsn, uint32_t ram_n, uint32_t gcl_num) +{ + int32_t ret = 0; + uint32_t tsn_port_gcl_num[TSN_PORT_RAM_NUM] = {TSN_PORT_GCL_NUM0, TSN_PORT_GCL_NUM1}; + + ZXDH_TSN_COMM_CHECK_INDEX_MAX(ram_n, TSN_PORT_RAM_MAX); + + ret = tsn_reg_write(tsn, tsn_port_gcl_num[ram_n], gcl_num); + ZXDH_TSN_COMM_CHECK_RC(ret); + + return TSN_OK; +} + +int32_t tsn_port_gcl_num_get(struct zxdh_tsn_private* tsn, uint32_t ram_n, uint32_t* p_gcl_num) +{ + int32_t ret = 0; + uint32_t tsn_port_gcl_num[TSN_PORT_RAM_NUM] = {TSN_PORT_GCL_NUM0, TSN_PORT_GCL_NUM1}; + + ZXDH_TSN_COMM_CHECK_INDEX_MAX(ram_n, TSN_PORT_RAM_MAX); + + ret = tsn_reg_read(tsn, tsn_port_gcl_num[ram_n], p_gcl_num); + ZXDH_TSN_COMM_CHECK_RC(ret); + + return TSN_OK; +} + +int32_t tsn_port_gcl_control_set(struct zxdh_tsn_private* tsn, uint32_t ram_n, uint32_t index, uint32_t gate_state, uint32_t internal) +{ + int32_t ret = 0; + uint32_t tsn_port_gcl_value[TSN_PORT_RAM_NUM] = {TSN_PORT_GCL_VALUE0, TSN_PORT_GCL_VALUE1}; + + ZXDH_TSN_COMM_CHECK_INDEX_MAX(ram_n, TSN_PORT_RAM_MAX); + ZXDH_TSN_COMM_CHECK_INDEX_MAX(index, TSN_PORT_GCL_MAX); + + ret = tsn_reg_write(tsn, tsn_port_gcl_value[ram_n] + (index * 4), (gate_state << 24) | internal); + ZXDH_TSN_COMM_CHECK_RC(ret); + + return TSN_OK; +} + +int32_t tsn_port_disable_set(struct zxdh_tsn_private* tsn) +{ + int32_t ret = 0; + + ret = tsn_port_enable_set(tsn, TSN_PORT_GATE_DISABLE); + ZXDH_TSN_COMM_CHECK_RC(ret); + + ret = tsn_port_init_finish_set(tsn, TSN_PORT_INIT_DISABLE); + ZXDH_TSN_COMM_CHECK_RC(ret); + + ret = tsn_port_change_en_set(tsn, TSN_PORT_CHANGE_DISABLE); + ZXDH_TSN_COMM_CHECK_RC(ret); + + return TSN_OK; +} + +int32_t tsn_port_real_tod_time_get(struct zxdh_tsn_private* tsn, uint64_t* p_tod_time) +{ + int32_t ret = 0; + uint32_t tsn_timer_id = 0; + uint32_t tod_second_h = 0; + uint32_t tod_second_l = 0; + uint32_t tod_nanosecond = 0; + + uint32_t tsn_real_tod_nanosecond_reg_offset[TSN_PORT_TIMER_ID_NUM] = { + TSN0_REAL_TOD_NANOSECOND, TSN1_REAL_TOD_NANOSECOND, TSN2_REAL_TOD_NANOSECOND, TSN3_REAL_TOD_NANOSECOND + }; + uint32_t tsn_real_high_tod_second_reg_offset[TSN_PORT_TIMER_ID_NUM] = { + TSN0_REAL_HIGH_TOD_SECOND, TSN1_REAL_HIGH_TOD_SECOND, TSN2_REAL_HIGH_TOD_SECOND, TSN3_REAL_HIGH_TOD_SECOND + }; + uint32_t tsn_real_lower_tod_second_reg_offset[TSN_PORT_TIMER_ID_NUM] = { + TSN0_REAL_LOWER_TOD_SECOND, TSN1_REAL_LOWER_TOD_SECOND, TSN2_REAL_LOWER_TOD_SECOND, TSN3_REAL_LOWER_TOD_SECOND + }; + + ZXDH_TSN_COMM_CHECK_POINT(p_tod_time); + + ret = tsn_port_timer_id_get(tsn, &tsn_timer_id); + ZXDH_TSN_COMM_CHECK_RC(ret); + ZXDH_TSN_COMM_CHECK_INDEX_MAX(tsn_timer_id, TSN_PORT_TIMER_ID_MAX); + + ret = tsn_read(tsn->pci_ioremap_addr + 0xC000, tsn_real_high_tod_second_reg_offset[tsn_timer_id], &tod_second_h); + ZXDH_TSN_COMM_CHECK_RC(ret); + + ret = tsn_read(tsn->pci_ioremap_addr + 0xC000, tsn_real_lower_tod_second_reg_offset[tsn_timer_id], &tod_second_l); + ZXDH_TSN_COMM_CHECK_RC(ret); + + ret = tsn_read(tsn->pci_ioremap_addr + 0xC000, tsn_real_tod_nanosecond_reg_offset[tsn_timer_id], &tod_nanosecond); + ZXDH_TSN_COMM_CHECK_RC(ret); + + *p_tod_time = ((((uint64_t)tod_second_h << 32) | (uint64_t)tod_second_l) * NSEC_PER_SEC) + tod_nanosecond; + + return TSN_OK; +} diff --git a/src/net/drivers/net/ethernet/dinghai/en_tsn/zxdh_tsn_reg.h b/src/net/drivers/net/ethernet/dinghai/en_tsn/zxdh_tsn_reg.h new file mode 100644 index 0000000..a884482 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/en_tsn/zxdh_tsn_reg.h @@ -0,0 +1,86 @@ +#ifndef __ZXDH_TSN_REG_H__ +#define __ZXDH_TSN_REG_H__ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include +#include + +#define TSN_PORT_REG_BAR_SIZE (0x4000) +#define TSN_PORT_REG_BAR_OFFSET (0x14000) + +#define TSN_PORT_QBV_ENABLE (0x0004) +#define TSN_PORT_PHY_PORT_SEL (0x0008) +#define TSN_PORT_TIME_SEL (0x000C) +#define TSN_PORT_CLK_FREQ (0x0014) +#define TSN_PORT_READ_RAM_N (0x0018) +#define TSN_PORT_EXE_TIME (0x001C) +#define TSN_PORT_ITR_SHIFT (0x0020) +#define TSN_PORT_BASE_TIME_H (0x0024) +#define TSN_PORT_BASE_TIME_L (0x0028) +#define TSN_PORT_CYCLE_TIME_H (0x0030) +#define TSN_PORT_CYCLE_TIME_L (0x0034) +#define TSN_PORT_GUARD_BAND_TIME (0x0040) +#define TSN_PORT_DEFAULT_GATE_EN (0x0060) +#define TSN_PORT_CHANGE_GATE_EN (0x0064) +#define TSN_PORT_INIT_FINISH (0x0068) +#define TSN_PORT_CHANGE_EN (0x006C) +#define TSN_PORT_GCL_NUM0 (0x0070) +#define TSN_PORT_GCL_NUM1 (0x0074) +#define TSN_PORT_GCL_VALUE0 (0x1000) +#define TSN_PORT_GCL_VALUE1 (0x2000) + +#define TSN0_REAL_TOD_NANOSECOND (0x4240) +#define TSN0_REAL_LOWER_TOD_SECOND (0x4244) +#define TSN0_REAL_HIGH_TOD_SECOND (0x4248) +#define TSN1_REAL_TOD_NANOSECOND (0x424C) +#define TSN1_REAL_LOWER_TOD_SECOND (0x4250) +#define TSN1_REAL_HIGH_TOD_SECOND (0x4254) +#define TSN2_REAL_TOD_NANOSECOND (0x4258) +#define TSN2_REAL_LOWER_TOD_SECOND (0x425C) +#define TSN2_REAL_HIGH_TOD_SECOND (0x4260) +#define TSN3_REAL_TOD_NANOSECOND (0x4264) +#define TSN3_REAL_LOWER_TOD_SECOND (0x4268) +#define TSN3_REAL_HIGH_TOD_SECOND (0x426C) + +int32_t tsn_read(uint64_t base_addr, uint32_t offset, uint32_t* p_val); +int32_t tsn_write(uint64_t base_addr, uint32_t offset, uint32_t val); +int32_t tsn_reg_read(struct zxdh_tsn_private* tsn, uint32_t offset, uint32_t* p_val); +int32_t tsn_reg_write(struct zxdh_tsn_private* tsn, uint32_t offset, uint32_t val); +int32_t tsn_port_enable_set(struct zxdh_tsn_private* tsn, uint32_t enable); +int32_t tsn_port_enable_get(struct zxdh_tsn_private* tsn, uint32_t* p_enable); +int32_t tsn_port_phy_port_set(struct zxdh_tsn_private* tsn, uint32_t phy_port); +int32_t tsn_port_phy_port_get(struct zxdh_tsn_private* tsn, uint32_t* p_phy_port); +int32_t tsn_port_timer_id_set(struct zxdh_tsn_private* tsn, uint32_t timer_id); +int32_t tsn_port_timer_id_get(struct zxdh_tsn_private* tsn, uint32_t* p_time_id); +int32_t tsn_port_status_get(struct zxdh_tsn_private* tsn, uint32_t* p_ram_n, uint32_t* p_status); +int32_t tsn_port_base_time_l_set(struct zxdh_tsn_private* tsn, uint32_t base_time); +int32_t tsn_port_base_time_h_set(struct zxdh_tsn_private* tsn, uint32_t base_time); +int32_t tsn_port_base_time_set(struct zxdh_tsn_private* tsn, uint64_t base_time); +int32_t tsn_port_base_time_get(struct zxdh_tsn_private* tsn, uint64_t* p_base_time); +int32_t tsn_port_cycle_time_l_set(struct zxdh_tsn_private* tsn, uint32_t cycle_time); +int32_t tsn_port_cycle_time_h_set(struct zxdh_tsn_private* tsn, uint32_t cycle_time); +int32_t tsn_port_cycle_time_set(struct zxdh_tsn_private* tsn, uint64_t cycle_time); +int32_t tsn_port_cycle_time_get(struct zxdh_tsn_private* tsn, uint64_t* p_cycle_time); +int32_t tsn_port_guard_band_time_set(struct zxdh_tsn_private* tsn, uint32_t cos, uint32_t band_time); +int32_t tsn_port_guard_band_time_get(struct zxdh_tsn_private* tsn, uint32_t cos, uint32_t* p_band_time); +int32_t tsn_port_default_gate_set(struct zxdh_tsn_private* tsn, uint32_t gate_state); +int32_t tsn_port_default_gate_get(struct zxdh_tsn_private* tsn, uint32_t* p_gate_state); +int32_t tsn_port_change_gate_set(struct zxdh_tsn_private* tsn, uint32_t gate_state); +int32_t tsn_port_init_finish_set(struct zxdh_tsn_private* tsn, uint32_t init_finish); +int32_t tsn_port_init_finish_get(struct zxdh_tsn_private* tsn, uint32_t* p_init_finish); +int32_t tsn_port_change_en_set(struct zxdh_tsn_private* tsn, uint32_t change_en); +int32_t tsn_port_change_en_get(struct zxdh_tsn_private* tsn, uint32_t* p_change_en); +int32_t tsn_port_gcl_num_set(struct zxdh_tsn_private* tsn, uint32_t ram_n, uint32_t gcl_num); +int32_t tsn_port_gcl_num_get(struct zxdh_tsn_private* tsn, uint32_t ram_n, uint32_t* p_gcl_num); +int32_t tsn_port_gcl_control_set(struct zxdh_tsn_private* tsn, uint32_t ram_n, uint32_t index, uint32_t gate_state, uint32_t internal); +int32_t tsn_port_disable_set(struct zxdh_tsn_private* tsn); +int32_t tsn_port_real_tod_time_get(struct zxdh_tsn_private* tsn, uint64_t* p_tod_time); + +#ifdef __cplusplus +} +#endif + +#endif /* __ZXDH_TSN_REG_H__ */ diff --git a/src/net/drivers/net/ethernet/dinghai/en_vf.c b/src/net/drivers/net/ethernet/dinghai/en_vf.c new file mode 100755 index 0000000..e69de29 diff --git a/src/net/drivers/net/ethernet/dinghai/eq.c b/src/net/drivers/net/ethernet/dinghai/eq.c new file mode 100755 index 0000000..be1cbb3 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/eq.c @@ -0,0 +1,108 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +int32_t dh_eq_enable(struct dh_core_dev *dev, struct dh_eq *eq, + struct notifier_block *nb) +{ + return dh_irq_attach_nb(eq->irq, nb); +} + +int32_t setup_async_eq(struct dh_core_dev *dev, struct dh_eq_async *eq, \ + struct dh_eq_param *param, notifier_fn_t dh_eq_async_int, \ + const char *name, void *priv) +{ + struct dh_eq *eq_core = NULL; + int32_t err = 0; + + eq->irq_nb.notifier_call = dh_eq_async_int; + eq->priv = priv; + spin_lock_init(&eq->lock);//unused + + eq_core = &eq->core; + eq_core->irq = param->irq; + + err = dh_eq_enable(dev, &eq->core, &eq->irq_nb); + if (err != 0) + { + LOG_WARN("failed to enable %s EQ %d\n", name, err); + } + + return err; +} + +void dh_eq_disable(struct dh_core_dev *dev, struct dh_eq *eq, + struct notifier_block *nb) +{ + dh_irq_detach_nb(eq->irq, nb); +} +//EXPORT_SYMBOL(dh_eq_disable); + + +void dh_eq_table_cleanup(struct dh_core_dev *dev) +{ + kvfree(dev->eq_table.priv); +} + +int32_t dh_inet6_addr_change_notifier_register(struct notifier_block *inet6_addr_change_notifier) +{ + return register_inet6addr_notifier(inet6_addr_change_notifier); +} + +int32_t dh_inet6_addr_change_notifier_unregister(struct notifier_block *inet6_addr_change_notifier) +{ + return unregister_inet6addr_notifier(inet6_addr_change_notifier); +} + +int32_t dh_eq_notifier_register(struct dh_eq_table *eqt, struct dh_nb *nb) +{ + return atomic_notifier_chain_register(&eqt->nh[nb->event_type], &nb->nb); +} +//EXPORT_SYMBOL(dh_eq_notifier_register); + + +int32_t dh_eq_notifier_unregister(struct dh_eq_table *eqt, struct dh_nb *nb) +{ + return atomic_notifier_chain_unregister(&eqt->nh[nb->event_type], &nb->nb); +} +//EXPORT_SYMBOL(dh_eq_notifier_unregister); + +void dh_eq_table_init(struct dh_core_dev *dev, void *table_priv) +{ + struct dh_eq_table *eq_table = &dev->eq_table; + int32_t i; + + eq_table->priv = table_priv; + + mutex_init(&eq_table->lock); + for (i = 0; i < DH_EVENT_TYPE_MAX; i++) + { + ATOMIC_INIT_NOTIFIER_HEAD(&eq_table->nh[i]); + } + + eq_table->irq_table = &dev->irq_table; +} + + +static uint16_t event_type_map[MSG_MODULE_NUM] = { + [MODULE_VF_BAR_MSG_TO_PF] = DH_EVENT_TYPE_NOTIFY_VF_TO_PF, + [MODULE_RISC_READY] = DH_EVENT_TYPE_RISCV_READY, + [MODULE_PF_BAR_MSG_TO_VF] = DH_EVENT_TYPE_NOTIFY_PF_TO_VF, + [MODULE_VIRTIO] = DH_EVENT_TYPE_NOTIFY_ANY, + [MODULE_DHTOOL] = DH_EVENT_TYPE_NOTIFY_RISCV_TO_AUX, + [MODULE_RESET_MSG] = DH_EVENT_TYPE_NOTIFY_ANY, + [MODULE_DEMO] = DH_EVENT_TYPE_NOTIFY_ANY, +}; + +uint16_t dh_eq_event_type_get(uint16_t event_id) +{ + return event_type_map[event_id]; +} +//EXPORT_SYMBOL(dh_eq_event_type_get); diff --git a/src/net/drivers/net/ethernet/dinghai/events.c b/src/net/drivers/net/ethernet/dinghai/events.c new file mode 100755 index 0000000..a551fd8 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/events.c @@ -0,0 +1,13 @@ +#include + +void zxdh_events_work_enqueue(struct dh_core_dev *dev, struct work_struct *work) +{ + queue_work(dev->events->wq, work); +} + +void zxdh_events_cleanup(struct dh_core_dev *dev) +{ + destroy_workqueue(dev->events->wq); + kfree(dev->events); +} + diff --git a/src/net/drivers/net/ethernet/dinghai/irq_affinity.c b/src/net/drivers/net/ethernet/dinghai/irq_affinity.c new file mode 100755 index 0000000..7b68fcf --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/irq_affinity.c @@ -0,0 +1,278 @@ +#include +#include +#include + + +static void cpu_put(struct dh_irq_pool *pool, int32_t cpu) +{ + pool->irqs_per_cpu[cpu]--; +} + +static void cpu_get(struct dh_irq_pool *pool, int32_t cpu) +{ + pool->irqs_per_cpu[cpu]++; +} + +/* Gets the least loaded CPU. e.g.: the CPU with least IRQs bound to it */ +static int32_t cpu_get_least_loaded(struct dh_irq_pool *pool, + const struct cpumask *req_mask) +{ + int32_t best_cpu = -1; + int32_t cpu; + + for_each_cpu_and(cpu, req_mask, cpu_online_mask) + { + /* CPU has zero IRQs on it. No need to search any more CPUs. */ + if (!pool->irqs_per_cpu[cpu]) + { + best_cpu = cpu; + break; + } + if (best_cpu < 0) + { + best_cpu = cpu; + } + if (pool->irqs_per_cpu[cpu] < pool->irqs_per_cpu[best_cpu]) + { + best_cpu = cpu; + } + } + + if (best_cpu == -1) + { + /* There isn't online CPUs in req_mask */ + LOG_ERR("NO online CPUs in req_mask (%*pbl)\n", cpumask_pr_args(req_mask)); + best_cpu = cpumask_first(cpu_online_mask); + } + pool->irqs_per_cpu[best_cpu]++; + + return best_cpu; +} + +/* Creating an IRQ from irq_pool */ +struct dh_irq *irq_pool_request_irq(struct dh_irq_pool *pool, const struct cpumask *req_mask) +{ + cpumask_var_t auto_mask; + struct dh_irq *irq = NULL; + u32 irq_index = 0; + int32_t err = 0; + + if (!zalloc_cpumask_var(&auto_mask, GFP_KERNEL)) + { + LOG_ERR("zalloc_cpumask_var failed, ERR_PTR(-ENOMEM)=0x%llx", (unsigned long long)ERR_PTR(-ENOMEM)); + return ERR_PTR(-ENOMEM); + } + + err = xa_alloc(&pool->irqs, &irq_index, NULL, pool->xa_num_irqs, GFP_KERNEL); + if (err) + { + if (err == -EBUSY) + { + err = -EUSERS; + } + LOG_ERR("xa_alloc failed, ERR_PTR(err)=0x%llx", (unsigned long long)ERR_PTR(err)); + return ERR_PTR(err); + } + + if (pool->irqs_per_cpu) + { + if (cpumask_weight(req_mask) > 1) + { + /* if req_mask contain more then one CPU, set the least loadad CPU + * of req_mask + */ + cpumask_set_cpu(cpu_get_least_loaded(pool, req_mask), auto_mask); + } + else + { + cpu_get(pool, cpumask_first(req_mask)); + } + } + + irq = dh_irq_alloc(pool, irq_index, cpumask_empty(auto_mask) ? req_mask : auto_mask); + if (IS_ERR_OR_NULL(irq)) + { + LOG_ERR("dh_irq_alloc failed, irq=%p\n", irq); + return irq; + } + free_cpumask_var(auto_mask); + + return irq; +} + +/* Looking for the IRQ with the smallest refcount that fits req_mask. + * If pool is sf_comp_pool, then we are looking for an IRQ with any of the + * requested CPUs in req_mask. + * for example: req_mask = 0xf, irq0_mask = 0x10, irq1_mask = 0x1. irq0_mask + * isn't subset of req_mask, so we will skip it. irq1_mask is subset of req_mask, + * we don't skip it. + * If pool is sf_ctrl_pool, then all IRQs have the same mask, so any IRQ will + * fit. And since mask is subset of itself, we will pass the first if bellow. + */ +static struct dh_irq *irq_pool_find_least_loaded(struct dh_irq_pool *pool, const struct cpumask *req_mask) +{ + int32_t start = pool->xa_num_irqs.min; + int32_t end = pool->xa_num_irqs.max; + struct dh_irq *irq = NULL; + struct dh_irq *iter; + int32_t irq_refcount = 0; + unsigned long index; + + lockdep_assert_held(&pool->lock); + xa_for_each_range(&pool->irqs, index, iter, start, end) + { + struct cpumask *iter_mask = dh_irq_get_affinity_mask(iter); + int32_t iter_refcount = dh_irq_read_locked(iter); + + if (!cpumask_subset(iter_mask, req_mask)) + { + /* skip IRQs with a mask which is not subset of req_mask */ + continue; + } + if (iter_refcount < pool->min_threshold) + { + /* If we found an IRQ with less than min_thres, return it */ + return iter; + } + if (!irq || iter_refcount < irq_refcount) + { + /* In case we won't find an IRQ with less than min_thres, + * keep a pointer to the least used IRQ + */ + irq_refcount = iter_refcount; + irq = iter; + } + } + + return irq; +} + +/** + * dh_irq_affinity_request - request an IRQ according to the given mask. + * @pool: IRQ pool to request from. + * @req_mask: cpumask requested for this IRQ. + * + * This function returns a pointer to IRQ, or ERR_PTR in case of error. + */ +struct dh_irq *dh_irq_affinity_request(struct dh_irq_pool *pool, const struct cpumask *req_mask) +{ + struct dh_irq *least_loaded_irq = NULL; + struct dh_irq *new_irq = NULL; + + mutex_lock(&pool->lock); + + least_loaded_irq = irq_pool_find_least_loaded(pool, req_mask); + if (least_loaded_irq && dh_irq_read_locked(least_loaded_irq) < pool->min_threshold) + { + LOG_ERR("least_loaded_irq error: pool->min_threshold=%d\r\n", pool->min_threshold); + goto out; + } + + /* We didn't find an IRQ with less than min_thres, try to allocate a new IRQ */ + new_irq = irq_pool_request_irq(pool, req_mask); + if (IS_ERR_OR_NULL(new_irq)) + { + if (!least_loaded_irq) + { + /* We failed to create an IRQ and we didn't find an IRQ */ + LOG_ERR("Didn't find a matching IRQ. err = %ld\n", PTR_ERR(new_irq)); + mutex_unlock(&pool->lock); + return new_irq; + } + /* We failed to create a new IRQ for the requested affinity, + * sharing existing IRQ. + */ + LOG_ERR("new_irq error\r\n"); + goto out; + } + + least_loaded_irq = new_irq; + goto unlock; + +out: + dh_irq_get_locked(least_loaded_irq); + if (dh_irq_read_locked(least_loaded_irq) > pool->max_threshold) + LOG_DEBUG("IRQ %u overloaded, pool_name: %s, %u EQs on this irq\n", + pci_irq_vector(pool->dev->pdev, dh_irq_get_index(least_loaded_irq)), + pool->name, dh_irq_read_locked(least_loaded_irq) / DH_EQ_REFS_PER_IRQ); +unlock: + mutex_unlock(&pool->lock); + return least_loaded_irq; +} + +void dh_irq_affinity_irqs_release(struct dh_irq_pool *pool, struct dh_irq **irqs, int32_t num_irqs) +{ + int32_t i; + + for (i = 0; i < num_irqs; i++) + { + int32_t cpu = cpumask_first(dh_irq_get_affinity_mask(irqs[i])); + + synchronize_irq(pci_irq_vector(pool->dev->pdev, dh_irq_get_index(irqs[i]))); + + if (pool->irqs_per_cpu) + { + cpu_put(pool, cpu); + } + } +} + +/** + * dh_irq_affinity_irqs_request_auto - request one or more IRQs for zxdh device. + * @pool: requesting the IRQs from the irqs pool. + * @num_irqs: number of IRQs to request. + * @irqs: an output array of IRQs pointers. + * + * Each IRQ is bounded to at most 1 CPU. + * This function is requesting IRQs according to the default assignment. + * The default assignment policy is: + * - in each iteration, request the least loaded IRQ which is not bound to any + * CPU of the previous IRQs requested. + * + * This function returns the number of IRQs requested, (which might be smaller than + * @nirqs), if successful, or a negative error code in case of an error. + */ +int32_t dh_irq_affinity_irqs_request_auto(struct dh_irq_pool *pool, struct dh_irq **irqs, int32_t num_irqs) +{ + cpumask_var_t req_mask; + struct dh_irq *irq = NULL; + int32_t i = 0; + + if (!zalloc_cpumask_var(&req_mask, GFP_KERNEL)) + { + LOG_ERR("zalloc_cpumask_var failed\n"); + return -ENOMEM; + } + + cpumask_copy(req_mask, cpu_online_mask); + for (i = 0; i < num_irqs; i++) + { + irq = irq_pool_request_irq(pool, req_mask); + if (IS_ERR_OR_NULL(irq)) + { + LOG_INFO("irq_pool_request_irq %d failed, req_mask=%p, irq=%p, break\n", i, req_mask, irq); + break; + } + + irqs[i] = irq; + if (i < (num_online_cpus() - 1)) + { + cpumask_clear_cpu(cpumask_first(dh_irq_get_affinity_mask(irq)), req_mask); + } + LOG_DEBUG("IRQ %u mapped to cpu %*pbl, %u EQs on this irq\n", + pci_irq_vector(pool->dev->pdev, dh_irq_get_index(irq)), + cpumask_pr_args(dh_irq_get_affinity_mask(irq)), + dh_irq_read_locked(irq) / DH_EQ_REFS_PER_IRQ); + } + + free_cpumask_var(req_mask); + if (i != num_irqs) + { + LOG_ERR("Failed to request %d irq_num, %d irq_num requested\n", num_irqs, i); + dh_irq_affinity_irqs_release(pool, irqs, i); + dh_irqs_release_vectors(irqs, i); + return PTR_ERR(irq); + } + + return i; +} \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/lag/lag.c b/src/net/drivers/net/ethernet/dinghai/lag/lag.c new file mode 100644 index 0000000..f1429fc --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/lag/lag.c @@ -0,0 +1,867 @@ +#include +#include +#include +#include +#include + +#include "lag.h" +#include "en_pf.h" +#include "dpp_tbl_api.h" + + +static DEFINE_SPINLOCK(lag_lock); +static DEFINE_MUTEX(zxdh_intf_mutex); + +void zxdh_dev_list_lock(void) +{ + mutex_lock(&zxdh_intf_mutex); +} + +void zxdh_dev_list_unlock(void) +{ + mutex_unlock(&zxdh_intf_mutex); +} + +int zxdh_dev_list_trylock(void) +{ + return mutex_trylock(&zxdh_intf_mutex); +} + +struct zxdh_lag *lag_get_ldev(struct dh_core_dev *dh_dev) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + + return pf_dev->ldev; +} + +void lag_set_ldev(struct dh_core_dev *dh_dev, struct zxdh_lag *ldev) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + + pf_dev->ldev = ldev; +} + +void ldev_kref_free(struct kref *ref) +{ + struct zxdh_lag *ldev = container_of(ref, struct zxdh_lag, ref); + + if (ldev->nb.notifier_call) + { + unregister_netdevice_notifier_net(&init_net, &ldev->nb); + } + + cancel_delayed_work_sync(&ldev->bond_work); + destroy_workqueue(ldev->wq); + + lag_set_ldev(ldev->parent, NULL); + kfree(ldev); + + LAG_LOG_INFO("pf lag device alloced memory free \n"); +} + +static void zxdh_queue_bond_work(struct zxdh_lag *ldev, unsigned long delay) +{ + queue_delayed_work(ldev->wq, &ldev->bond_work, delay); +} + +void lag_dev_release(struct dh_core_dev *dh_dev, struct zxdh_lag *ldev) +{ + int i; + struct dh_core_dev *parent; + + for (i = 0; i < ZXDH_MAX_PORTS; i++) + { + if (!ldev->lagfunc[i].dev) + { + continue; + } + + parent = ldev->lagfunc[i].dev->parent; + if (parent == dh_dev) + { + ldev->lagfunc[i].dev = NULL; + } + } +} + +/** + * lag_get_netdev_idx - get the index of netdev generated by en_aux + * @ldev: zxdh lag dev + * @ndev: netdev to search for + **/ +int32_t lag_get_netdev_idx(struct zxdh_lag *ldev, struct net_device *ndev) +{ + int i; + + for (i = 0; i < ZXDH_MAX_PORTS; i++) + { + if (ldev->lagfunc[i].netdev == ndev) + { + return i; + } + } + + return -ENOENT; +} + +void ldev_remove_netdev(struct dh_core_dev *dh_dev, struct net_device *netdev) +{ + int32_t index = 0; + struct zxdh_lag *ldev; + + ldev = lag_get_ldev(dh_dev->parent); + if (!ldev) + { + return; + } + + spin_lock(&lag_lock); + + index = lag_get_netdev_idx(ldev, netdev); + if (index < 0) + { + goto out; + } + + ldev->lagfunc[index].netdev = NULL; +out: + spin_unlock(&lag_lock); +} + +/** + * ldev_add_netdev - add net_device to lag dev + * @dev: zxdh core device + * @id: the index that joined to ldev + * @netdev: netdev to adding for + * @attr: some configs info from aux + **/ +static void ldev_add_netdev(struct dh_core_dev *dh_dev, + uint16_t id, struct net_device *netdev, struct zxdh_lag_attrs *attr) +{ + struct zxdh_lag *ldev; + + if (id >= ZXDH_MAX_PORTS) + { + LAG_LOG_ERR("%s: index[%hu] out of range. \n", netdev_name(netdev), id); + return; + } + + ldev = lag_get_ldev(dh_dev->parent); + + spin_lock(&lag_lock); + ldev->lagfunc[id].dev = dh_dev; + ldev->lagfunc[id].netdev = netdev; + ldev->lagfunc[id].attrs = *attr; + ldev->lagfunc[id].valid = true; + ldev->tracker.netdev_state[id].link_up = 0; + ldev->tracker.netdev_state[id].tx_enabled = 0; + ldev->lag_func_index++; + spin_unlock(&lag_lock); + + zxdh_queue_bond_work(ldev, 0); +} + +static bool zxdh_netdev_belongs(struct zxdh_lag *ldev, struct net_device *netdev) +{ + int32_t idx = 0; + + idx = lag_get_netdev_idx(ldev, netdev); + if (idx < 0) + { + return false; + } + + return true; +} + +/** + * handle_changeupper_event - handle change upper device event + * @ldev: zxdh lag dev + * @tracker: the tracker of zxdh lag dev + * @ndev: upper netdev + * @info: upper dev attribute passed from bonding + **/ +static int handle_changeupper_event(struct zxdh_lag *ldev, + struct lag_tracker *tracker, + struct net_device *ndev, + struct netdev_notifier_changeupper_info *info) +{ + struct net_device *upper = info->upper_dev, *ndev_tmp, *slave_dev; + struct netdev_lag_upper_info *lag_upper_info = NULL; + bool is_bonded = false; + bool mode_supported = false; + int changed = 0; + int bond_status = 0; + int num_slaves = 0; + int idx = 0; + + if (!netif_is_lag_master(upper)) + { + LAG_LOG_INFO("changeupper received, but not master. \n"); + return 0; + } + + if (strcmp("bondxi5", upper->name)) + { + slave_dev = netdev_notifier_info_to_dev((void *)info); + if (!zxdh_netdev_belongs(ldev, slave_dev)) + { + LAG_LOG_INFO("%s is not dinghai bond, ignore. \n", upper->name); + return 0; + } + } + + if (info->linking) + { + lag_upper_info = info->upper_info; + } + + rcu_read_lock(); + for_each_netdev_in_bond_rcu(upper, ndev_tmp) + { + idx = lag_get_netdev_idx(ldev, ndev_tmp); + if (idx >= 0) + { + bond_status |= (1 << idx); + } + + num_slaves++; + } + rcu_read_unlock(); + + ldev->slaves = bond_status; + + /* None of this lagdev's netdevs are slaves of this master. */ + if (!bond_status) + { + is_bonded = false; + goto out; + } + + if (lag_upper_info) + { + tracker->tx_type = lag_upper_info->tx_type; + tracker->hash_type = lag_upper_info->hash_type; + } + + LAG_LOG_INFO("lag tx type: %d [%d-active-backup %d-lacp], hash type %d. \n", + tracker->tx_type, NETDEV_LAG_TX_TYPE_ACTIVEBACKUP, NETDEV_LAG_TX_TYPE_HASH, tracker->hash_type); + + /* Lag mode must be activebackup or hash. */ + mode_supported = (tracker->tx_type == NETDEV_LAG_TX_TYPE_ACTIVEBACKUP) || + (tracker->tx_type == NETDEV_LAG_TX_TYPE_HASH); + + /* if slaves exist */ + is_bonded = !!bond_status && mode_supported; + +out: + if ((tracker->is_bonded != is_bonded)) + { + tracker->is_bonded = is_bonded; + changed = 1; + } + + LAG_LOG_INFO("master: %s slaves num: %d, mask: 0x%x, changed: %d, mode supported: %s\n", + upper->name, num_slaves, bond_status, changed, mode_supported ? "true" : "false"); + + return changed; +} + +/** + * handle_changelowerstate_event - handle changed lower device state event + * @ldev: zxdh lag dev + * @tracker: the tracker of zxdh lag dev + * @ndev: lower netdev + * @info: lower dev attribute passed from bonding + **/ +static int handle_changelowerstate_event(struct zxdh_lag *ldev, + struct lag_tracker *tracker, + struct net_device *ndev, + struct netdev_notifier_changelowerstate_info *info) +{ + struct netdev_lag_lower_state_info *lag_lower_info; + int idx; + + if (!netif_is_lag_port(ndev)) + { + return 0; + } + + idx = lag_get_netdev_idx(ldev, ndev); + if (idx < 0) + { + return 0; + } + + lag_lower_info = info->lower_state_info; + if (!lag_lower_info) + { + return 0; + } + + /* update netdev state from bonding */ + tracker->netdev_state[idx] = *lag_lower_info; + + LAG_LOG_INFO("%s: link up %u tx enable %u \n", ndev->name, + (uint32_t)lag_lower_info->link_up, (uint32_t)lag_lower_info->tx_enabled); + + return 1; +} + +bool lag_check_aux_netdev_ready(struct zxdh_lag *ldev) +{ + int ix = 0; + int lag_netdev_cnt = 0; + int lag_pannel_num = zxdh_pf_get_pannel_port_num(ldev->parent); + + for (ix = 0; ix < ZXDH_MAX_PORTS; ix++) + { + if (ldev->lagfunc[ix].netdev) + { + lag_netdev_cnt++; + } + } + + return (lag_pannel_num == lag_netdev_cnt) ? true : false; +} + +static int lag_netdev_event(struct notifier_block *this, unsigned long event, void *ptr) +{ + struct net_device *ndev = netdev_notifier_info_to_dev(ptr); + struct lag_tracker tracker; + struct zxdh_lag *ldev; + int changed = 0; + + if ((event != NETDEV_CHANGEUPPER) && (event != NETDEV_CHANGELOWERSTATE)) + { + return NOTIFY_DONE; + } + + ldev = container_of(this, struct zxdh_lag, nb); + if (!lag_check_aux_netdev_ready(ldev)) + { + return NOTIFY_DONE; + } + + LAG_LOG_INFO("received %s\n", netdev_cmd_to_name(event)); + + tracker = ldev->tracker; + + switch (event) + { + case NETDEV_CHANGEUPPER: + { + changed = handle_changeupper_event(ldev, &tracker, ndev, ptr); + break; + } + case NETDEV_CHANGELOWERSTATE: + { + changed = handle_changelowerstate_event(ldev, &tracker, ndev, ptr); + break; + } + } + + ldev->tracker = tracker; + + if (changed) + { + zxdh_queue_bond_work(ldev, 0); + } + + return NOTIFY_DONE; +} + +static int32_t lag_find_first_netdev_pf_info(struct zxdh_lag *ldev, DPP_PF_INFO_T *pf_info) +{ + int i; + struct lag_func *func; + + for (i = 0; i < ZXDH_MAX_PORTS; i++) + { + func = &ldev->lagfunc[i]; + + if (func->netdev) + { + pf_info->vport = func->attrs.vport; + pf_info->slot = func->attrs.slot_id; + return 0; + } + } + + return -EOPNOTSUPP; +} + +static int32_t zxdh_disable_lag(struct zxdh_lag *ldev) +{ + int i; + uint8_t phy_port = 0; + struct lag_func *func; + DPP_PF_INFO_T pf_info = {0}; + + for (i = 0; i < ZXDH_MAX_PORTS; i++) + { + func = &ldev->lagfunc[i]; + + if (!func->netdev) + { + continue; + } + + pf_info.slot = func->attrs.slot_id; + pf_info.vport = func->attrs.vport; + phy_port = func->attrs.phy_port; + + dpp_lag_group_member_del(&pf_info, ZXDH_LGA_ID, phy_port); + dpp_panel_attr_set(&pf_info, phy_port, PANEL_FLAG_BOND_LINK_UP, LAG_FLAGS_DISABLE); + } + + ldev->flags &= ~ZXDH_LAG_MODE_FLAGS; + LAG_LOG_INFO("zxdh lag disabled. vport 0x%hx lag id %d.\n", pf_info.vport, ZXDH_LGA_ID); + + return 0; +} + +static int32_t zxdh_lag_active_backup(struct zxdh_lag *ldev) +{ + int i; + bool porten = false; + uint8_t phy_port = ZXDH_ACTIVE_PHY_PORT_NA; + uint8_t active_phy_port = ZXDH_ACTIVE_PHY_PORT_NA; + int32_t err = 0; + struct lag_func *func; + struct lag_tracker *tracker = &ldev->tracker; + DPP_PF_INFO_T pf_info = {0}; + + err = lag_find_first_netdev_pf_info(ldev, &pf_info); + if (err != 0) + { + LAG_LOG_ERR("vport %d is incorrect\n", pf_info.vport); + return -EOPNOTSUPP; + } + + dpp_lag_mode_set(&pf_info, ZXDH_LGA_ID, LAG_MODE_ACTIVE_BACKUP); + + for (i = ZXDH_MAX_PORTS - 1; i >= 0; i--) + { + func = &ldev->lagfunc[i]; + + if (!func->netdev) + { + continue; + } + + phy_port = func->attrs.phy_port; + pf_info.slot = func->attrs.slot_id; + pf_info.vport = func->attrs.vport; + + dpp_lag_group_member_del(&pf_info, ZXDH_LGA_ID, phy_port); + dpp_panel_attr_set(&pf_info, phy_port, PANEL_FLAG_BOND_LINK_UP, LAG_FLAGS_DISABLE); + + porten = tracker->netdev_state[i].tx_enabled && tracker->netdev_state[i].link_up; + if (porten && (ldev->slaves & (1 << i))) + { + active_phy_port = phy_port; + LAG_LOG_INFO("[backup]: select acitve phyport %hu pannel port %hu \n", + active_phy_port, func->attrs.pannel_id); + } + + LAG_LOG_INFO("[backup]: phyport %hhu pannel port %hhu tx enable %d link up %d\n", + phy_port, func->attrs.pannel_id, + (int32_t)tracker->netdev_state[i].tx_enabled, + (int32_t)tracker->netdev_state[i].link_up); + } + + if (active_phy_port != ZXDH_ACTIVE_PHY_PORT_NA) + { + dpp_lag_group_member_add(&pf_info, ZXDH_LGA_ID, active_phy_port); + dpp_panel_attr_set(&pf_info, active_phy_port, PANEL_FLAG_BOND_LINK_UP, LAG_FLAGS_ENABLE); + } + + ldev->flags |= ZXDH_LAG_FLAG_BACKUP; + + return 0; +} + +uint32_t zxdh_covert_hash_type_2_np(uint32_t hash_type) +{ + uint32_t np_hash_type = 0; + + switch (hash_type) + { + case NETDEV_LAG_HASH_L2: + { + np_hash_type = ZXDH_NP_HASH_TYPE_L2; + break; + } + case NETDEV_LAG_HASH_L23: + { + np_hash_type = ZXDH_NP_HASH_TYPE_L23; + break; + } + case NETDEV_LAG_HASH_L34: + { + np_hash_type = ZXDH_NP_HASH_TYPE_L34; + break; + } + default: + { + np_hash_type = ZXDH_NP_HASH_TYPE_DEFAULT; + break; + } + } + + return np_hash_type; +} + +static int32_t zxdh_lag_lacp(struct zxdh_lag *ldev) +{ + int i; + bool porten = false; + uint8_t phy_port = 0; + uint8_t flags = 0; + uint32_t np_hash_type = 0; + int32_t err = 0; + struct lag_func *func; + struct lag_tracker *tracker = &ldev->tracker; + DPP_PF_INFO_T pf_info = {0}; + + err = lag_find_first_netdev_pf_info(ldev, &pf_info); + if (err != 0) + { + LAG_LOG_ERR("vport %d is incorrect\n", pf_info.vport); + return -EOPNOTSUPP; + } + +#if 0 + np_hash_type = zxdh_covert_hash_type_2_np((uint32_t)tracker->hash_type); +#else + /* 顾剑总要求，HASH模式直接写死Layer3+4 */ + np_hash_type = ZXDH_NP_HASH_TYPE_L34; +#endif + + dpp_lag_group_hash_factor_set(&pf_info, ZXDH_LGA_ID, (uint8_t)np_hash_type); + dpp_lag_mode_set(&pf_info, ZXDH_LGA_ID, LAG_MODE_802_3AD); + + for (i = 0; i < ZXDH_MAX_PORTS; i++) + { + func = &ldev->lagfunc[i]; + + if (!func->netdev) + { + continue; + } + + phy_port = func->attrs.phy_port; + pf_info.slot = func->attrs.slot_id; + pf_info.vport = func->attrs.vport; + + porten = tracker->netdev_state[i].tx_enabled && tracker->netdev_state[i].link_up; + if (porten && (ldev->slaves & (1 << i))) + { + dpp_lag_group_member_add(&pf_info, ZXDH_LGA_ID, phy_port); + dpp_panel_attr_set(&pf_info, phy_port, PANEL_FLAG_BOND_LINK_UP, LAG_FLAGS_ENABLE); + flags = LAG_FLAGS_ENABLE; + } + else + { + dpp_lag_group_member_del(&pf_info, ZXDH_LGA_ID, phy_port); + dpp_panel_attr_set(&pf_info, phy_port, PANEL_FLAG_BOND_LINK_UP, LAG_FLAGS_DISABLE); + flags = LAG_FLAGS_DISABLE; + } + + LAG_LOG_INFO("[lacp] %s, vport %hu, pannel port %hu, phy port %hu, slave mask 0x%x, tx enable %d, link up %d \n", + (flags == LAG_FLAGS_ENABLE) ? "enable" : "disable", pf_info.vport, + func->attrs.pannel_id, phy_port, ldev->slaves, + (int32_t)tracker->netdev_state[i].tx_enabled, + (int32_t)tracker->netdev_state[i].link_up); + } + + ldev->flags |= ZXDH_LAG_FLAG_HASH; + + return 0; +} + +static void zxdh_lagtracker_info(struct lag_tracker *tracker) +{ + const char *bond_tx_mode, *bonded, *hash_type; + + bonded = tracker->is_bonded ? "BONDED" : "UNBONDED"; + + switch (tracker->tx_type) + { + case NETDEV_LAG_TX_TYPE_HASH: + { + bond_tx_mode = "LACP"; + break; + } + case NETDEV_LAG_TX_TYPE_ACTIVEBACKUP: + { + bond_tx_mode = "ACTIVE-BACKUP"; + break; + } + default: + { + bond_tx_mode = "UNKOWN"; + } + } + + switch (tracker->hash_type) + { + case ZXDH_NP_HASH_TYPE_L2: + { + hash_type = "layer2"; + break; + } + case ZXDH_NP_HASH_TYPE_L23: + { + hash_type = "layer2+3"; + break; + } + case ZXDH_NP_HASH_TYPE_L34: + { + hash_type = "layer2+3"; + break; + } + default: + { + hash_type = "layer2"; + } + } + + LAG_LOG_INFO("%s: tx type: %s, hash type %s.\n", bonded, bond_tx_mode, hash_type); +} + +static void do_bond(struct zxdh_lag *ldev) +{ + bool do_bond; + struct lag_tracker *tracker = &ldev->tracker; + + zxdh_lagtracker_info(tracker); + + do_bond = tracker->is_bonded; + + if (do_bond && lag_is_backup(ldev)) + { + zxdh_lag_active_backup(ldev); + } + else if (do_bond && lag_is_hash(ldev)) + { + zxdh_lag_lacp(ldev); + } + else + { + zxdh_disable_lag(ldev); + } +} + +static void zxdh_do_bond_work(struct work_struct *work) +{ + struct delayed_work *delayed_work = to_delayed_work(work); + struct zxdh_lag *ldev = container_of(delayed_work, struct zxdh_lag, bond_work); + int status; + + status = zxdh_dev_list_trylock(); + if (!status) + { + zxdh_queue_bond_work(ldev, HZ); + return; + } + + do_bond(ldev); + zxdh_dev_list_unlock(); +} + +static struct zxdh_lag *lag_dev_alloc(struct dh_core_dev *dev) +{ + struct zxdh_lag *ldev; + + ldev = kzalloc(sizeof(*ldev), GFP_KERNEL); + if (!ldev) + { + return NULL; + } + + ldev->wq = create_singlethread_workqueue("zxdh_lag"); + if (!ldev->wq) + { + kfree(ldev); + return NULL; + } + + kref_init(&ldev->ref); + INIT_DELAYED_WORK(&ldev->bond_work, zxdh_do_bond_work); + + ldev->nb.notifier_call = lag_netdev_event; + if (register_netdevice_notifier_net(&init_net, &ldev->nb)) + { + ldev->nb.notifier_call = NULL; + LAG_LOG_ERR("Failed to register LAG netdev notifier\n"); + } + + ldev->parent = dev; + + return ldev; +} + +static int lag_dev_create(struct dh_core_dev *dh_dev) +{ + struct zxdh_lag *ldev = NULL; + static bool init_once = false; + + ldev = lag_get_ldev(dh_dev); + if (!ldev) + { + ldev = lag_dev_alloc(dh_dev); + if (!ldev) + { + LAG_LOG_ERR("Failed to alloc lag dev.\n"); + return 0; + } + } + + if (init_once) + { + get_ldev_kref(ldev); + } + init_once = true; + + lag_set_ldev(dh_dev, ldev); + + return 0; +} + +int32_t lag_dpp_pannel_init(struct zxdh_lag_attrs *attr) +{ + uint16_t pannel_id = attr->pannel_id; + uint16_t pf_id = (attr->pcie_id >> 8) & PCIE_ID_PF_INDEX_MASK; + uint16_t ep_id = (attr->pcie_id >> 12) & PCIE_ID_EP_INDEX_MASK; + uint16_t bond_vfid = ZXDH_PF_VFID(ep_id, pf_id); + uint16_t ovs_vfid = ZXDH_PF_VFID(ep_id, (pf_id + 1)); + uint8_t phy_port = attr->phy_port; + DPP_PF_INFO_T pf_info = {0}; + + pf_info.slot = attr->slot_id; + pf_info.vport = attr->vport; + dpp_panel_bond_vport(&pf_info, phy_port); + dpp_panel_bond_pf_vqm_vfid_set(&pf_info, phy_port, bond_vfid); + dpp_panel_bond_pf_memport_qid_set(&pf_info, phy_port, attr->qid[0]); + dpp_panel_ovs_pf_vqm_vfid_set(&pf_info, phy_port, ovs_vfid); + + dpp_panel_hardware_bond_set(&pf_info, phy_port, LAG_FLAGS_ENABLE); + dpp_egr_port_attr_set(&pf_info, EGR_FLAG_HW_BOND_EN_OFF, LAG_FLAGS_ENABLE); + + dpp_lag_group_create(&pf_info, ZXDH_LGA_ID); + + LAG_LOG_INFO("vport 0x%hx, pannel id %hu, phy port %hu, rx qid %hu tx qid %hu bond vfid %d, ovs vfid %d \n", + pf_info.vport, pannel_id, phy_port, attr->qid[0], attr->qid[1], bond_vfid, ovs_vfid); + + return 0; +} + +int32_t lag_dpp_pannel_release(struct zxdh_lag_attrs *attr) +{ + uint8_t phy_port = attr->phy_port; + DPP_PF_INFO_T pf_info = {0}; + + pf_info.slot = attr->slot_id; + pf_info.vport = attr->vport; + dpp_panel_hardware_bond_set(&pf_info, phy_port, LAG_FLAGS_DISABLE); + dpp_egr_port_attr_set(&pf_info, EGR_FLAG_HW_BOND_EN_OFF, LAG_FLAGS_DISABLE); + + return 0; +} + +int32_t lag_netdev_input_check(struct dh_core_dev *dh_dev, struct zxdh_lag_attrs *attr) +{ + struct zxdh_lag *ldev; + + if (!dh_core_is_pf(dh_dev->parent)) + { + LAG_LOG_ERR("dh_core_dev type PF needs to be used\n"); + return -EINVAL; + } + + ldev = lag_get_ldev(dh_dev->parent); + if (!ldev) + { + LAG_LOG_ERR("ldev can not be null\n"); + return -EINVAL; + } + + if (attr->pannel_id >= ZXDH_MAX_PORTS) + { + LAG_LOG_ERR("pannel id %hu out of range.\n", attr->pannel_id); + return -EINVAL; + } + + return 0; +} + +/** + * zxdh_regitster_ldev - create lagdev and add to dh core dev + * @dh_dev: zxdh lag dev + * the function called by pf driver + **/ +void zxdh_regitster_ldev(struct dh_core_dev *dh_dev) +{ + zxdh_dev_list_lock(); + lag_dev_create(dh_dev); + zxdh_dev_list_unlock(); +} + +void zxdh_unregitster_ldev(struct dh_core_dev *dh_dev) +{ + struct zxdh_lag *ldev; + + zxdh_dev_list_lock(); + ldev = lag_get_ldev(dh_dev); + if (!ldev) + { + zxdh_dev_list_unlock(); + return; + } + + lag_dev_release(dh_dev, ldev); + put_ldev_kref(ldev); + + zxdh_dev_list_unlock(); +} + +/** + * zxdh_ldev_add_netdev - add net device to lag device + * @dh_dev: sf core dev + * @ida: netdev idx + * @netdev: the net device which en aux created + * @attr: netdev info + * this function may called by en aux + **/ +int32_t zxdh_ldev_add_netdev(struct dh_core_dev *dh_dev, uint16_t ida, + struct net_device *netdev, struct zxdh_lag_attrs *attr) +{ + int32_t ret = 0; + + zxdh_dev_list_lock(); + ret = lag_netdev_input_check(dh_dev, attr); + if (ret != 0) + { + zxdh_dev_list_unlock(); + return -EINVAL; + } + + lag_dpp_pannel_init(attr); + ldev_add_netdev(dh_dev, ida, netdev, attr); + zxdh_dev_list_unlock(); + + return 0; +} +EXPORT_SYMBOL(zxdh_ldev_add_netdev); + +void zxdh_ldev_remove_netdev(struct dh_core_dev *dh_dev, struct net_device *netdev, struct zxdh_lag_attrs *attr) +{ + zxdh_dev_list_lock(); + + lag_dpp_pannel_release(attr); + ldev_remove_netdev(dh_dev, netdev); + zxdh_dev_list_unlock(); +} +EXPORT_SYMBOL(zxdh_ldev_remove_netdev); \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/lag/lag.h b/src/net/drivers/net/ethernet/dinghai/lag/lag.h new file mode 100644 index 0000000..df5db5b --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/lag/lag.h @@ -0,0 +1,120 @@ +#ifndef _ZXDH_ETH_LAG_H_ +#define _ZXDH_ETH_LAG_H_ + +#include +#include +#include +#include +#include + +#define LAG_LOG_ERR(fmt, arg...) DH_LOG_ERR(MODULE_LAG, fmt, ##arg); +#define LAG_LOG_INFO(fmt, arg...) DH_LOG_INFO(MODULE_LAG, fmt, ##arg); +#define LAG_LOG_DEBUG(fmt, arg...) DH_LOG_DEBUG(MODULE_LAG, fmt, ##arg); +#define LAG_LOG_WARN(fmt, arg...) DH_LOG_WARNING(MODULE_LAG, fmt, ##arg); + +/* max panel port */ +#define ZXDH_MAX_PORTS (6) + +#define ZXDH_LGA_ID (0) +#define ZXDH_ACTIVE_PHY_PORT_NA (0xFF) + +#define PCIE_ID_PF_INDEX_MASK (0x7) +#define PCIE_ID_EP_INDEX_MASK (0x7) + +enum +{ + ZXDH_LAG_FLAG_BACKUP = 1 << 0, + ZXDH_LAG_FLAG_HASH = 1 << 1, + ZXDH_LAG_FLAG_READY = 1 << 2, +}; + +#define ZXDH_LAG_MODE_FLAGS (ZXDH_LAG_FLAG_BACKUP | ZXDH_LAG_FLAG_HASH) + +enum +{ + LAG_FLAGS_DISABLE = 0, + LAG_FLAGS_ENABLE = 1, +}; + +enum +{ + LAG_MODE_ACTIVE_BACKUP = 1, + LAG_MODE_802_3AD = 2, +}; + +/* define hash type for NP SDK */ +enum +{ + ZXDH_NP_HASH_TYPE_DEFAULT = 0, + ZXDH_NP_HASH_TYPE_L2 = 1, + ZXDH_NP_HASH_TYPE_L23 = 2, + ZXDH_NP_HASH_TYPE_L34 = 4, +}; + +struct lag_func +{ + bool valid; + struct dh_core_dev *dev; + struct net_device *netdev; + struct zxdh_lag_attrs attrs; +}; + +struct lag_tracker +{ + enum netdev_lag_tx_type tx_type; + struct netdev_lag_lower_state_info netdev_state[ZXDH_MAX_PORTS]; + bool is_bonded; + enum netdev_lag_hash hash_type; + char master_name[IFNAMSIZ]; +}; + +struct zxdh_lag +{ + uint32_t flags; + uint32_t lag_func_index; + uint32_t slaves; + int32_t mode_changes_in_progress; + struct kref ref; + struct lag_func lagfunc[ZXDH_MAX_PORTS]; + struct workqueue_struct *wq; + struct delayed_work bond_work; + struct notifier_block nb; + struct lag_tracker tracker; + struct dh_core_dev *parent; + + struct zxdh_lag_if *ops; +}; + +static inline bool lag_is_ready(struct zxdh_lag *ldev) +{ + return true; +} + +static inline bool lag_is_backup(struct zxdh_lag *ldev) +{ + return ldev->tracker.tx_type == NETDEV_LAG_TX_TYPE_ACTIVEBACKUP ? true : false; +} + +static inline bool lag_is_hash(struct zxdh_lag *ldev) +{ + return ldev->tracker.tx_type == NETDEV_LAG_TX_TYPE_HASH ? true : false; +} + +static inline bool lag_is_port_invalid(struct zxdh_lag *ldev, uint32_t index) +{ + BUG_ON(index >= ZXDH_MAX_PORTS); + return !ldev->lagfunc[index].dev || !ldev->lagfunc[index].netdev; +} + +void ldev_kref_free(struct kref *ref); +static inline void get_ldev_kref(struct zxdh_lag *ldev) +{ + kref_get(&ldev->ref); +} + +static inline void put_ldev_kref(struct zxdh_lag *ldev) +{ + kref_put(&ldev->ref, ldev_kref_free); +} + +#endif /* _ZXDH_ETH_LAG_H_ */ \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/lag/lag_procfs.c b/src/net/drivers/net/ethernet/dinghai/lag/lag_procfs.c new file mode 100644 index 0000000..62ca8e5 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/lag/lag_procfs.c @@ -0,0 +1,62 @@ +#include +#include +#include + +#include "dh_procfs.h" +#include "lag.h" + +void *lag_info_seq_start(struct seq_file *seq, loff_t *pos) +{ + if (*pos == 0) + { + return SEQ_START_TOKEN; + } + + return NULL; +} + +void *lag_info_seq_next(struct seq_file *seq, void *v, loff_t *pos) +{ +#if 0 + struct test *tst = PDE_DATA(file_inode(seq->file)); + + ++*pos; + if (v == SEQ_START_TOKEN) + pr_info("%s first *pos = %u\n", __FUNCTION__, (uint32_t)*pos); + + pr_info("%s *pos = %u\n", __FUNCTION__, (uint32_t)*pos); + if (*pos < 5) + { + return tst; + } +#endif + return NULL; +} + +void lag_info_seq_stop(struct seq_file *seq, void *v) +{ + pr_info("%s \n", __FUNCTION__); +} + +int lag_info_seq_show(struct seq_file *seq, void *v) +{ +#if 0 + struct zxdh_lag *lag = PDE_DATA(file_inode(seq->file)); + + if (v == SEQ_START_TOKEN) + { + seq_printf(seq, "Port Mode: %u", tst->port); + seq_printf(seq, "Num Mode: %u", tst->age); + seq_printf(seq, "\n"); + } +#endif + return 0; +} + +struct seq_operations lag_info_seq_ops = +{ + .start = lag_info_seq_start, + .next = lag_info_seq_next, + .stop = lag_info_seq_stop, + .show = lag_info_seq_show, +}; \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/msg_common.h b/src/net/drivers/net/ethernet/dinghai/msg_common.h new file mode 100644 index 0000000..92110ea --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/msg_common.h @@ -0,0 +1,719 @@ +#ifndef __ZXDH_MSG_COMMON_H__ +#define __ZXDH_MSG_COMMON_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "en_np/table/include/dpp_tbl_api.h" +#include "en_aux/queue.h" +#include "en_pf.h" + +#define FW_VERSION_LEN 32 + +typedef enum +{ + ZXDH_NULL = 0, + + ZXDH_VF_PORT_INIT = 1, + ZXDH_VF_PORT_UNINIT = 2, + ZXDH_MAC_ADD = 3, + ZXDH_MAC_DEL = 4, + ZXDH_MAC_GET = 5, + + ZXDH_RSS_EN_SET = 7, + ZXDH_RXFH_SET = 8, + ZXDH_RXFH_GET = 9, + ZXDH_RXFH_DEL = 10, + ZXDH_THASH_KEY_SET = 11, + ZXDH_THASH_KEY_GET = 12, + ZXDH_HASH_FUNC_SET = 13, + ZXDH_HASH_FUNC_GET = 14, + ZXDH_RX_FLOW_HASH_SET = 15, + ZXDH_RX_FLOW_HASH_GET = 16, + + ZXDH_VLAN_FILTER_SET = 17, + ZXDH_VLAN_FILTER_ADD = 18, + ZXDH_VLAN_FILTER_DEL = 19, + ZXDH_VLAN_OFFLOAD_SET = 21, + + ZXDH_PORT_ATTRS_GET = 22, + ZXDH_SET_TPID = 23, + ZXDH_VXLAN_PORT = 24, + ZXDH_PORT_ATTRS_SET = 25, + ZXDH_PROMISC_SET = 26, + + /*sriov msg type*/ + ZXDH_SRIOV_RESET = 27, + + ZXDH_SET_VF_LINK_STATE = 28, + ZXDH_PF_SET_VF_VLAN = 29, + ZXDH_SET_VF_RESET = 30, + ZXDH_GET_NP_STATS = 31, + + ZXDH_VF_RATE_LIMIT_SET = 32, + ZXDH_PLCR_UNINIT = 33, + ZXDH_MAP_PLCR_FLOWID = 34, + ZXDH_PLCR_MODE_INIT = 35, + ZXDH_PLCR_FLOW_INIT = 36, + ZXDH_PLCR_CAR_PROFILE_ID_ADD = 37, + ZXDH_PLCR_CAR_PROFILE_ID_DELETE = 38, + ZXDH_PLCR_CAR_PROFILE_CFG_SET = 39, + ZXDH_PLCR_CAR_PROFILE_CFG_GET = 40, + ZXDH_PLCR_CAR_QUEUE_CFG_SET = 41, + ZXDH_PORT_METER_STAT_CLR = 42, + ZXDH_PORT_METER_STAT_GET = 43, + ZXDH_PF_GET_VF_QUEUE_INFO = 44, + + ZXDH_VF_1588_CALL_NP, + ZXDH_MSG_TYPE_CNT_MAX, + + ZXDH_IPV6_MAC_ADD, + ZXDH_IPV6_MAC_DEL, +} __attribute__((packed)) zxdh_msg_op_code; + +typedef struct +{ + zxdh_msg_op_code op_code; + uint16_t vport; + uint16_t vf_id; + uint16_t pcie_id; +} __attribute__((packed)) zxdh_msg_head_to_pf; + +typedef struct +{ + zxdh_msg_op_code op_code; + uint16_t dst_pcie_id; +} __attribute__((packed)) zxdh_msg_head_to_vf; + +typedef struct +{ + bool link_up; + bool is_upf; + uint16_t base_qid; + uint8_t mac_addr[ZXDH_MAC_NUM]; + uint32_t speed; + uint32_t autoneg_enable; + uint32_t sup_link_modes; + uint32_t adv_link_modes; + uint8_t hash_search_idx; + uint8_t duplex; + uint8_t phy_port; + uint8_t rss_enable; +} __attribute__((packed)) zxdh_vf_init_msg; + +typedef struct +{ + uint32_t vfid; + uint32_t call_np_interface_num; + uint32_t ptp_tc_enable_opt; +} __attribute__((packed)) zxdh_vf_1588_call_np; + +typedef struct +{ + uint8_t rss_enable; +} __attribute__((packed)) zxdh_rss_enable_msg; + +typedef struct +{ + bool enable; +#define VLAN_STRIP_MSG_TYPE 0 +#define QINQ_STRIP_MSG_TYPE 1 + uint8_t flag; +} __attribute__((packed)) zxdh_strip_enable_msg; + +typedef struct +{ + uint16_t vf_idx; + uint16_t vlan_id; + uint8_t qos; + uint8_t rsv; + uint16_t protocl; +} __attribute__((packed)) zxdh_set_vf_vlan_msg; + +typedef struct +{ + uint16_t tpid; +} __attribute__((packed)) zxdh_qinq_tpid_cfg_msg; + +typedef struct +{ + uint32_t queue_map[ZXDH_INDIR_RQT_SIZE]; +} __attribute__((packed)) zxdh_rxfh_set_msg; + +typedef struct +{ + uint8_t key_map[ZXDH_NET_HASH_KEY_SIZE]; +} __attribute__((packed)) zxdh_thash_key_set_msg; + +typedef struct +{ + uint8_t func; +} __attribute__((packed)) zxdh_hfunc_set_msg; + +typedef struct +{ + uint32_t hash_mode; +} __attribute__((packed)) zxdh_rx_flow_hash_set_msg; + +typedef struct +{ + bool mac_flag; + uint8_t filter_flag; /* 0xaa表示过滤，0Xff表示其他*/ + uint8_t mac_addr[ZXDH_MAC_NUM]; +} __attribute__((packed)) zxdh_mac_addr_msg; + +typedef struct +{ + uint8_t mac_addr[ZXDH_MAC_NUM]; +} __attribute__((packed)) zxdh_ipv6_mac_addr_msg; + +typedef struct +{ + uint32_t mode; + uint32_t value; + uint8_t allmulti_follow; +} __attribute__((packed)) zxdh_port_attr_set_msg; + +#define ZXDH_PROMISC_MODE 1 +#define ZXDH_ALLMULTI_MODE 2 +typedef struct +{ + uint8_t mode; + uint8_t value; + uint8_t mc_follow; +} __attribute__((packed)) zxdh_promisc_set_msg; + +typedef struct +{ + uint8_t rsv2; + uint16_t read_bytes; + uint8_t value; +}__attribute__((packed)) common_recv_msg; + +typedef struct +{ + uint8_t rsv2; + uint16_t read_bytes; + uint16_t queue_nums; + uint16_t phy_qidx[256]; +}__attribute__((packed)) common_vq_msg; + +typedef enum +{ + AGENT_MAC_STATS_GET = 10, + AGENT_MAC_STATS_CLEAR, + AGENT_MAC_PHYPORT_INIT, + AGENT_MAC_AUTONEG_SET, + AGENT_MAC_LINK_INFO_GET, + AGENT_MAC_LED_BLINK, + AGENT_MAC_FEC_MODE_SET, + AGENT_MAC_FEC_MODE_GET, + AGENT_MAC_FC_MODE_SET, + AGENT_MAC_FC_MODE_GET, + AGENT_MAC_MODULE_EEPROM_READ, + AGENT_VQM_DEVICE_STATS_GET, + AGENT_VQM_STATS_CLEAR, + AGENT_FLASH_FIR_VERSION_GET = 23, + AGENT_DEV_STATUS_NOTIFY, + AGENT_DEBUG_LLDP_ENABLE_SET, + AGENT_DEBUG_LLDP_ENABLE_GET, + AGENT_SSHD_START, + AGENT_SSHD_STOP, + AGENT_FLASH_MAC_READ, + AGENT_FLASH_MAC_WRITE, + AGENT_FLASH_MAC_ERASE, + AGENT_MAC_RECOVERY_CLK_SET, + AGENT_MAC_SYNCE_CLK_STATS_GET, + AGENT_MAC_PORT_TSTAMP_ENABLE_SET, + AGENT_MAC_PORT_TSTAMP_ENABLE_GET, + AGENT_MAC_PORT_TSTAMP_MODE_SET, + AGENT_MAC_PORT_TSTAMP_MODE_GET, + AGENT_MAC_PORT_DELAY_VALUE_GET, + AGENT_MAC_PORT_DELAY_VALUE_CLR, + AGENT_EP0_BUS_GET = 40, + AGENT_OS_TYPE_GET = 41, + AGENT_MAC_MSG_NUM_MAX, /* should be at last */ +} __attribute__((packed)) agent_msg_op_code; + +typedef struct +{ + agent_msg_op_code op_code; + uint8_t port_id; + uint8_t phyport; + uint8_t is_upf; + uint16_t vf_id; + uint16_t pcie_id; +} __attribute__((packed)) agent_msg_hdr; + +typedef struct +{ + uint8_t autoneg; + uint8_t link_state; + uint8_t blink_enable; + uint8_t duplex; + uint32_t speed_modes; + uint32_t speed; +} __attribute__((packed)) agent_mac_autoneg_msg; + +typedef struct +{ + uint64_t rx_total; + uint64_t tx_total; + uint64_t rx_bytes; + uint64_t tx_bytes; + uint64_t rx_error; + uint64_t tx_error; + uint64_t rx_drop; + uint64_t tx_drop; + uint64_t rx_multicast; + uint64_t tx_multicast; + uint64_t rx_broadcast; + uint64_t tx_broadcast; + uint64_t rx_size_64; + uint64_t rx_size_65_127; + uint64_t rx_size_128_255; + uint64_t rx_size_256_511; + uint64_t rx_size_512_1023; + uint64_t rx_size_1024_1518; + uint64_t rx_size_1519_mru; +} __attribute__((packed)) agent_stats; + +typedef struct +{ + uint64_t np_rx_broadcast; + uint64_t np_tx_broadcast; + uint64_t np_rx_mtu_drop_pkts; + uint64_t np_tx_mtu_drop_pkts; + uint64_t np_rx_mtu_drop_bytes; + uint64_t np_tx_mtu_drop_bytes; + uint64_t np_rx_plcr_drop_pkts; + uint64_t np_tx_plcr_drop_pkts; + uint64_t np_rx_plcr_drop_bytes; + uint64_t np_tx_plcr_drop_bytes; +}__attribute__((packed)) np_stats; + +typedef struct +{ + uint8_t fec_cfg; + uint8_t fec_cap; + uint8_t fec_link; +} __attribute__((packed)) agent_mac_fec_mode_msg; + +typedef struct +{ + uint8_t fc_mode; +} __attribute__((packed)) agent_mac_fc_mode_msg; + +typedef struct +{ + uint8_t index; +} __attribute__((packed)) agent_flash_read_msg; + +typedef struct +{ + uint8_t i2c_addr; + uint8_t bank; + uint8_t page; + uint8_t offset; + uint8_t length; + uint8_t data[128]; +} __attribute__((packed)) agent_mac_module_eeprom_msg; + +typedef struct +{ + bool is_link_force_set; + bool link_forced; + bool link_up; + uint32_t speed; + uint32_t autoneg_enable; + uint32_t supported_speed_modes; + uint32_t advertising_speed_modes; + uint8_t duplex; +} __attribute__((packed)) zxdh_link_state_msg; + +typedef struct +{ + bool enable; +} __attribute__((packed)) zxdh_vlan_filter_set_msg; + +typedef struct +{ + uint16_t vlan_id; +} __attribute__((packed)) zxdh_rx_vid_add_msg; + +typedef struct +{ + uint16_t vlan_id; +} __attribute__((packed)) zxdh_rx_vid_del_msg; + +typedef struct +{ + uint8_t type; + uint8_t field; + uint16_t pcie_id; + uint16_t write_bytes; + uint16_t rsv; +} __attribute__((packed)) zxdh_common_tbl_hdr; + +typedef struct +{ + uint8_t tmmng_type; + uint8_t dir; + uint16_t year; + uint8_t month; + uint8_t day; + uint8_t hour; + uint8_t min; + uint8_t sec; +} __attribute__((packed)) zxdh_cfg_time_msg; + +typedef struct +{ + uint16_t pcie_id; + uint16_t write_bytes; +} __attribute__((packed)) zxdh_common_time_hdr; + +typedef struct +{ + uint8_t clk_speed; + uint8_t clk_stats; +} __attribute__((packed)) zxdh_synce_clk_msg; + +typedef struct +{ + uint32_t tx_enable; + uint32_t rx_enable; + uint32_t tx_mode; + uint32_t rx_mode; +} __attribute__((packed)) zxdh_mac_tstamp_msg; + +typedef struct +{ + uint64_t min_delay; + uint64_t max_delay; +} __attribute__((packed)) zxdh_delay_statistics_val; + +typedef struct +{ + uint16_t pcieid; // 发送者自己的pcie id + uint16_t extern_pps_vector; // 外部pps中断向量 + uint16_t local_pps_vector; // local pps中断向量 +} __attribute__((packed)) zxdh_bar_msg_pps; + +typedef struct +{ + uint8_t dev_id; //用dbg module的id, 为0 + uint8_t type; //区分PXE下和正常的np配表流程, 0: PXE 7: 配np + uint8_t operate_mode; //区分PXE开始和结束, 0: 开始 1: 结束 + uint8_t pfNum; + uint32_t portNum[10]; + uint32_t evid[10]; + uint32_t qid[10]; +} __attribute__((packed)) zxdh_cfg_np_msg; + +#define MAX_HDR_LEN 8 + +typedef struct +{ + char ifname[IFNAMSIZ]; + uint8_t mac[ETH_ALEN]; + uint16_t pannel_id; + uint16_t ctl; + uint16_t rsv; +} __attribute__((packed)) zxdh_pf_cfg_mac_msg; + +#define MAX_VF_NUM 256 +typedef struct +{ + uint16_t num; + uint16_t func_no[MAX_VF_NUM]; +} __attribute__((packed)) agent_pcie_msix_msg; + +typedef struct +{ + bool lldp_enable; +} __attribute__((packed)) zxdh_lldp_enable_msg; + +typedef struct +{ + uint32_t flowid; + uint32_t car_type; + uint32_t is_packet; + uint32_t max_rate; + uint32_t min_rate; +} __attribute__((packed)) zxdh_rate_limit_set_msg; + +/*vf send message to pf to map flow id between CARS*/ +typedef struct +{ + uint32_t car_type; + uint32_t flowid; + uint32_t map_flowid; + uint32_t sp; +} __attribute__((packed)) zxdh_plcr_flowid_map_msg; + +typedef struct +{ + uint32_t car_type; + uint32_t flowid; + uint32_t profile_id; +} __attribute__((packed)) zxdh_plcr_flow_init_msg; + +typedef struct +{ + uint32_t vir_queue_start; + uint32_t vir_queue_num; +} __attribute__((packed)) zxdh_plcr_pf_get_vf_queue_info_msg; + +/*用户态QOS申请限速模板*/ +typedef struct +{ + uint8_t car_type; +} __attribute__((packed)) zxdh_vf_plcr_profile_id_add_msg; + +/*用户态QOS删除限速模板*/ +typedef struct +{ + uint8_t car_type; + uint8_t rsvd; + uint16_t profile_id; +} __attribute__((packed)) zxdh_vf_plcr_profile_id_delete_msg; + +/*用户态QOS配置限速模板*/ +typedef struct +{ + uint8_t car_type; + uint8_t pkt_mode; + uint16_t profile_id; + union zxdh_plcr_profile_cfg profile_cfg; +} __attribute__((packed)) zxdh_vf_plcr_profile_cfg_set_msg; + +/*用户态QOS获取限速模板*/ +typedef struct +{ + uint8_t car_type; + uint8_t pkt_mode; + uint16_t profile_id; +} __attribute__((packed)) zxdh_vf_plcr_profile_cfg_get_msg; + +/*用户态QOS绑定flow和profile*/ +typedef struct +{ + uint8_t car_type; + uint8_t drop_flag; + uint8_t plcr_en; + uint8_t rsvd; + uint16_t flow_id; + uint16_t profile_id; +} __attribute__((packed)) zxdh_vf_plcr_queue_cfg_set_msg; + +/*用户态QOS获取plcr丢包统计*/ +typedef struct +{ + uint8_t direction; //取值为1：获取tx方向的统计计数；取值为0：获取rx方向的统计计数 + uint8_t is_clr; //取值为1：读取之后，计数器清零，取值为0：读取之后，计数器不清零 +} __attribute__((packed)) zxdh_vf_plcr_port_meter_stat_get_msg; + +typedef struct +{ + uint32_t clear_mode; +} __attribute__((packed)) zxdh_np_stats_get_msg; + +struct zxdh_port_msg +{ + uint16_t pcie_id; + uint8_t rsv[2]; +} __attribute__((packed)); + +struct port_message_recv +{ + uint8_t hdr[4]; + uint8_t port_num; + uint8_t rsv[3]; + struct zxdh_pannle_port data[16]; +} __attribute__((packed)); + +typedef struct +{ + union + { + uint8_t len[MAX_HDR_LEN]; + zxdh_msg_head_to_pf hdr; + zxdh_msg_head_to_vf hdr_vf; + agent_msg_hdr hdr_to_agt; + zxdh_common_tbl_hdr hdr_to_cmn; + zxdh_common_time_hdr hdr_time_to_cmn; + }; /* should be no more than MAX_HDR_LEN */ + + union + { + zxdh_rss_enable_msg rss_enable_msg; + zxdh_rxfh_set_msg rxfh_set_msg; + zxdh_thash_key_set_msg thash_key_set_msg; + zxdh_hfunc_set_msg hfunc_set_msg; + zxdh_rx_flow_hash_set_msg rx_flow_hash_set_msg; + zxdh_mac_addr_msg mac_addr_set_msg; + zxdh_port_attr_set_msg port_attr_set_msg; + zxdh_promisc_set_msg promisc_set_msg; + zxdh_link_state_msg link_state_msg; + zxdh_vlan_filter_set_msg vlan_filter_set_msg; + zxdh_rx_vid_add_msg rx_vid_add_msg; + zxdh_rx_vid_del_msg rx_vid_del_msg; + agent_mac_autoneg_msg mac_set_msg; + agent_mac_fec_mode_msg mac_fec_mode_msg; + agent_mac_fc_mode_msg mac_fc_mode_msg; + agent_mac_module_eeprom_msg module_eeprom_msg; + agent_flash_read_msg flash_read_msg; + zxdh_vf_init_msg vf_init_msg; + zxdh_strip_enable_msg vlan_strip_msg; + zxdh_set_vf_vlan_msg vf_vlan_msg; + zxdh_qinq_tpid_cfg_msg tpid_cfg_msg; + zxdh_pf_cfg_mac_msg mac_cfg_msg; + zxdh_cfg_time_msg time_cfg_msg; + agent_pcie_msix_msg pcie_msix_msg; + zxdh_lldp_enable_msg lldp_msg; + zxdh_rate_limit_set_msg rate_limit_set_msg; + zxdh_plcr_flowid_map_msg plcr_flowid_map_msg; + zxdh_plcr_flow_init_msg plcr_flow_init_msg; + zxdh_plcr_pf_get_vf_queue_info_msg plcr_pf_get_vf_queue_info_msg; + /*用户态QOS申请限速模板*/ + zxdh_vf_plcr_profile_id_add_msg vf_plcr_profile_id_add_msg; + /*用户态QOS删除限速模板*/ + zxdh_vf_plcr_profile_id_delete_msg vf_plcr_profile_id_delete_msg; + /*用户态QOS配置限速模板*/ + zxdh_vf_plcr_profile_cfg_set_msg vf_plcr_profile_cfg_set_msg; + /*用户态QOS获取限速模板*/ + zxdh_vf_plcr_profile_cfg_get_msg vf_plcr_profile_cfg_get_msg; + /*用户态QOS绑定flow和profile*/ + zxdh_vf_plcr_queue_cfg_set_msg vf_plcr_queue_cfg_set_msg; + /*用户态QOS获取plcr丢包统计*/ + zxdh_vf_plcr_port_meter_stat_get_msg vf_plcr_port_meter_stat_get_msg; + zxdh_np_stats_get_msg np_stats_get_msg; + + zxdh_vf_1588_call_np vf_1588_call_np; + zxdh_synce_clk_msg synce_clk_recovery_port; + zxdh_mac_tstamp_msg mac_tstamp_msg; + zxdh_bar_msg_pps msg_pps; + uint16_t cmn_tbl_msg[257]; + }; +} zxdh_msg_info; + +typedef enum +{ + ZXDH_REPS_FAIL, + ZXDH_REPS_SUCC = 0xaa, + ZXDH_REPS_BEOND_MAC = 0xfe, +} __attribute__((packed)) zxdh_reps_flag; + +typedef struct +{ + uint8_t lldp_status; +} __attribute__((packed)) agent_debug_lldp_msg; + +typedef struct +{ + uint8_t firmware_version[FW_VERSION_LEN]; +} __attribute__((packed)) agent_flash_msg; + +typedef struct +{ + uint8_t mac[ETH_ALEN]; +} __attribute__((packed)) agent_flash_mac_read_msg; + +typedef struct +{ + uint32_t phy_queue_num; + uint16_t phy_rxq[16]; + uint16_t phy_txq[16]; +} __attribute__((packed)) zxdh_plcr_pf_get_vf_queue_info_rsp; + +typedef struct +{ + uint32_t err_code; +} __attribute__((packed)) zxdh_rate_limit_set_rsp; + +/*用户态QOS申请限速模板，返回模板profile_id*/ +typedef struct +{ + uint16_t profile_id; +} __attribute__((packed)) zxdh_vf_plcr_profile_id_add_rsp; + +/*用户态QOS获取限速模板，返回模板参数*/ +typedef struct +{ + union zxdh_plcr_profile_cfg profile_cfg; +} __attribute__((packed)) zxdh_vf_plcr_profile_cfg_get_rsp; + +/*用户态QOS获取丢包统计*/ +typedef struct +{ + uint64_t drop_pkB_cnt; //丢数据包：包数统计 + uint64_t drop_pk_cnt; //丢数据包：字节数计数 +} __attribute__((packed)) zxdh_vf_plcr_port_meter_stat_get_rsp; + +typedef struct +{ + uint8_t bus_info; //ep0的bus号 +} __attribute__((packed)) zxdh_ep0_bus_get_rsp; + +typedef struct +{ + uint8_t is_zios; //riscv是否为zios +} __attribute__((packed)) zxdh_os_type_get_rsp; + +typedef struct +{ + ZXDH_VPORT_T port_attr_entry; +} __attribute__((packed)) zxdh_port_attr_get_msg; + +typedef struct +{ + zxdh_reps_flag flag; + union + { + zxdh_thash_key_set_msg thash_key_set_msg; + zxdh_rx_flow_hash_set_msg rx_flow_hash_set_msg; + zxdh_link_state_msg link_state_msg; + agent_mac_autoneg_msg mac_set_msg; + agent_stats stats_msg; + np_stats np_stats_msg; + agent_mac_fec_mode_msg mac_fec_mode_msg; + agent_mac_fc_mode_msg mac_fc_mode_msg; + agent_mac_module_eeprom_msg module_eeprom_msg; + common_recv_msg cmn_recv_msg; + common_vq_msg cmn_vq_msg; + zxdh_mac_addr_msg vf_mac_addr_get_msg; + zxdh_vf_init_msg vf_init_msg; + agent_flash_msg flash_msg; + agent_flash_mac_read_msg flash_mac_read_msg; + agent_debug_lldp_msg debug_lldp_msg; + zxdh_plcr_pf_get_vf_queue_info_rsp plcr_pf_get_vf_queue_info_rsp; + zxdh_rate_limit_set_rsp rate_limit_set_rsp; + /*用户态QOS申请限速模板返回profile_id*/ + zxdh_vf_plcr_profile_id_add_rsp vf_plcr_profile_id_add_rsp; + /*用户态QOS获取限速模板*/ + zxdh_vf_plcr_profile_cfg_get_rsp vf_plcr_profile_cfg_get_rsp; + /*用户态QOS获取丢包统计*/ + zxdh_vf_plcr_port_meter_stat_get_rsp vf_plcr_port_meter_stat_get_rsp; + zxdh_synce_clk_msg synce_clk_recovery_port; + zxdh_mac_tstamp_msg mac_tstamp_msg; + zxdh_delay_statistics_val delay_statistics_val; + zxdh_ep0_bus_get_rsp ep0_bus_msg; + zxdh_os_type_get_rsp os_type_msg; + zxdh_port_attr_get_msg port_attr_get_msg; + zxdh_rxfh_set_msg rxfh_get_msg; + }; +} zxdh_reps_info; + +union zxdh_msg +{ + zxdh_msg_info payload; + zxdh_reps_info reps; +}; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/pci_irq.c b/src/net/drivers/net/ethernet/dinghai/pci_irq.c new file mode 100755 index 0000000..f1f9e7b --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/pci_irq.c @@ -0,0 +1,573 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DH_PF_IRQ_CTRL_NUM (1) + +#define DH_SFS_PER_CTRL_IRQ 64 +#define DH_IRQ_CTRL_SF_MAX 8 +/* min num of vectors for SFs to be enabled */ +#define DH_IRQ_VEC_COMP_BASE_SF 2 + +#define DH_EQ_SHARE_IRQ_MAX_COMP (8) +#define DH_EQ_SHARE_IRQ_MAX_CTRL (UINT_MAX) +#define DH_EQ_SHARE_IRQ_MIN_COMP (1) +#define DH_EQ_SHARE_IRQ_MIN_CTRL (4) + +static void irq_release(struct dh_irq *irq) +{ + struct dh_irq_pool *pool = irq->pool; + + xa_erase(&pool->irqs, irq->index); + /* free_irq requires that affinity_hint and rmap will be cleared + * before calling it. This is why there is asymmetry with set_rmap + * which should be called after alloc_irq but before request_irq. + */ + // irq_update_affinity_hint(irq->irqn, NULL); + irq_set_affinity_hint(irq->irqn, NULL); + free_cpumask_var(irq->mask); + free_irq(irq->irqn, &irq->nh); + kfree(irq); +} + +int32_t dh_irq_put(struct dh_irq *irq) +{ + struct dh_irq_pool *pool = irq->pool; + int32_t ret = 0; + + mutex_lock(&pool->lock); + irq->refcount--; + if (!irq->refcount) + { + irq_release(irq); + ret = 1; + } + mutex_unlock(&pool->lock); + + return ret; +} + +int32_t dh_irq_read_locked(struct dh_irq *irq) +{ + lockdep_assert_held(&irq->pool->lock); + + return irq->refcount; +} + +int32_t dh_irq_get_locked(struct dh_irq *irq) +{ + lockdep_assert_held(&irq->pool->lock); + if (WARN_ON_ONCE(!irq->refcount)) + { + return 0; + } + + irq->refcount++; + + return 1; +} + +static int32_t irq_get(struct dh_irq *irq) +{ + int32_t err = 0; + + mutex_lock(&irq->pool->lock); + err = dh_irq_get_locked(irq); + mutex_unlock(&irq->pool->lock); + + return err; +} + +static irqreturn_t irq_int_handler(int32_t irq, void *nh) +{ + atomic_notifier_call_chain(nh, 0, NULL); + + return IRQ_HANDLED; +} + +static void irq_set_name(struct dh_irq_pool *pool, char *name, int32_t vecidx) +{ + if (!strcmp(pool->name, "zxdh_pf_vq")) + { + int type = (vecidx - pool->xa_num_irqs.min) % 2; + snprintf(name, DH_MAX_IRQ_NAME, "vq_%s_%d", type ? "output" : "input", vecidx); + return; + } + else if (!strcmp(pool->name, "zxdh_pf_async")) + { + snprintf(name, DH_MAX_IRQ_NAME, "async_%d", vecidx); + return; + } + else if (!strcmp(pool->name, "zxdh_mpf_gdma")) + { + snprintf(name, DH_MAX_IRQ_NAME, "gdma_%d", vecidx); + return; + } +} + +struct dh_irq *dh_irq_alloc(struct dh_irq_pool *pool, int32_t i, const struct cpumask *affinity) +{ + struct dh_core_dev *dev = pool->dev; + char name[DH_MAX_IRQ_NAME] = {}; + struct dh_irq *irq = NULL; + int32_t err = 0; + int32_t num_cpu = 0; + int32_t cpu_loop = 0; + + irq = kzalloc(sizeof(*irq), GFP_KERNEL); + if (unlikely(irq == NULL)) + { + LOG_ERR("irq kzalloc failed\n"); + return ERR_PTR(-ENOMEM); + } + + irq->irqn = pci_irq_vector(dev->pdev, i); + irq_set_name(pool, name, i); + ATOMIC_INIT_NOTIFIER_HEAD(&irq->nh); + snprintf(irq->name, DH_MAX_IRQ_NAME, "%s@pci:%s", name, pci_name(dev->pdev)); + LOG_DEBUG("i=%d, irqn=%d, name=%s\r\n", i, irq->irqn, irq->name); + + err = request_irq(irq->irqn, irq_int_handler, 0, irq->name, &irq->nh); + if (err != 0) + { + LOG_ERR("Failed to request irq. err = %d\n", err); + goto err_req_irq; + } + + if (!zalloc_cpumask_var(&irq->mask, GFP_KERNEL)) + { + LOG_WARN("zalloc_cpumask_var failed\n"); + err = -ENOMEM; + goto err_cpumask; + } + + if (affinity != NULL) + { + cpumask_copy(irq->mask, affinity); + irq_set_affinity_hint(irq->irqn, irq->mask); + } + else + { + num_cpu = num_online_cpus(); + for (cpu_loop= 0; cpu_loop < num_cpu; cpu_loop++) + { + cpumask_set_cpu(cpu_loop, irq->mask); + } + irq_set_affinity_hint(irq->irqn, irq->mask); + } + + irq->pool = pool; + irq->refcount = 1; + irq->index = i; + err = xa_err(xa_store(&pool->irqs, irq->index, irq, GFP_KERNEL)); + if (err != 0) + { + LOG_ERR("Failed to alloc xa entry for irq(%u). err = %d\n", irq->index, err); + goto err_xa; + } + + return irq; + +err_xa: + irq_set_affinity_hint(irq->irqn, NULL); + free_cpumask_var(irq->mask); +err_cpumask: + free_irq(irq->irqn, &irq->nh); +err_req_irq: + kfree(irq); + return ERR_PTR(err); +} + +int32_t dh_irq_attach_nb(struct dh_irq *irq, struct notifier_block *nb) +{ + int32_t ret = 0; + + ret = irq_get(irq); + if (ret == 0) + { + return -ENOENT; + } + + ret = atomic_notifier_chain_register(&irq->nh, nb); + if (ret != 0) + { + dh_irq_put(irq); + } + + return ret; +} + +int32_t dh_irq_detach_nb(struct dh_irq *irq, struct notifier_block *nb) +{ + int32_t err = 0; + + err = atomic_notifier_chain_unregister(&irq->nh, nb); + dh_irq_put(irq); + + return err; +} + +struct cpumask *dh_irq_get_affinity_mask(struct dh_irq *irq) +{ + return irq->mask; +} + +int32_t dh_irq_get_index(struct dh_irq *irq) +{ + return irq->index; +} + +/* irq_pool API */ +static int32_t __attribute__((unused)) irq_pool_size_get(struct dh_irq_pool *pool) +{ + return pool->xa_num_irqs.max - pool->xa_num_irqs.min + 1; +} + +/* requesting an irq from a given pool according to given index */ +static struct dh_irq *irq_pool_request_vector(struct dh_irq_pool *pool, int32_t vecidx, + const struct cpumask *affinity, u8 exclude) +{ + struct dh_irq *irq = NULL; + + mutex_lock(&pool->lock); + irq = xa_load(&pool->irqs, vecidx); + if (irq != NULL) + { + if (exclude) + { + return ERR_PTR(-EEXIST); + } + dh_irq_get_locked(irq); + goto unlock; + } + + irq = dh_irq_alloc(pool, vecidx, affinity); +unlock: + mutex_unlock(&pool->lock); + return irq; +} + +/** + * dh_irqs_release - release one or more IRQs back to the system. + * @irqs: IRQs to be released. + * @nirqs: number of IRQs to be released. + */ +static void dh_irqs_release(struct dh_irq **irqs, int32_t nirqs) +{ + int32_t i; + + for (i = 0; i < nirqs; i++) + { + synchronize_irq(irqs[i]->irqn); + dh_irq_put(irqs[i]); + } +} + +/** + * dh_ctrl_irq_release - release a ctrl IRQ back to the system. + * @ctrl_irq: ctrl IRQ to be released. + */ +void dh_ctrl_irq_release(struct dh_irq *ctrl_irq) +{ + dh_irqs_release(&ctrl_irq, 1); +} + +/* get a irq from pool*/ +struct dh_irq *zxdh_get_irq_of_pool(struct dh_core_dev *dev, struct dh_irq_pool *pool) +{ + cpumask_var_t req_mask; + struct dh_irq *irq = NULL; + + if (!zalloc_cpumask_var(&req_mask, GFP_KERNEL)) + { + LOG_ERR("zalloc_cpumask_var failed\n"); + return ERR_PTR(-ENOMEM); + } + cpumask_copy(req_mask, cpu_online_mask); + + irq = dh_irq_affinity_request(pool, req_mask); + + free_cpumask_var(req_mask); + if (IS_ERR_OR_NULL(irq)) + { + LOG_ERR("irq=0x%llx dh_irq_affinity_request failed\n", (unsigned long long)irq); + } + + return irq; +} + +/** + * dh_irq_request - request an IRQ for zxdh PF/VF device. + * @pool: requesting the IRQ from the irqs pool. + * @vecidx: vector index of the IRQ. This argument is ignore if affinity is + * provided. + * @affinity: cpumask requested for this IRQ. + * + * This function returns a pointer to IRQ, or ERR_PTR in case of error. + */ +struct dh_irq *dh_irq_request(struct dh_irq_pool *pool, u16 vecidx, + const struct cpumask *affinity, u8 exclude) +{ + struct dh_irq *irq = NULL; + + irq = irq_pool_request_vector(pool, vecidx, affinity, exclude); + if (IS_ERR_OR_NULL(irq)) + return irq; + LOG_DEBUG("irq %u mapped to cpu %*pbl, %u EQs on this irq\n", + irq->irqn, cpumask_pr_args(affinity), + irq->refcount / DH_EQ_REFS_PER_IRQ); + + return irq; +} + +/** + * dh_irqs_release_vectors - release one or more IRQs back to the system. + * @irqs: IRQs to be released. + * @nirqs: number of IRQs to be released. + */ +void dh_irqs_release_vectors(struct dh_irq **irqs, int32_t nirqs) +{ + dh_irqs_release(irqs, nirqs); +} + +/** + * dh_irqs_request_vectors - request one or more IRQs for zxdh device. + * @pool: requesting the IRQs from the irqs pool. + * @cpus: CPUs array for binding the IRQs + * @nirqs: number of IRQs to request. + * @irqs: an output array of IRQs pointers. + * + * Each IRQ is bound to at most 1 CPU. + * This function is requests nirqs IRQs, starting from @vecidx. + * + * This function returns the number of IRQs requested, (which might be smaller than + * @nirqs), if successful, or a negative error code in case of an error. + */ +int32_t dh_irqs_request_vectors(struct dh_irq_pool *pool, uint16_t *cpus, int32_t nirqs, + struct dh_irq **irqs) +{ + cpumask_var_t req_mask; + struct dh_irq *irq = NULL; + int32_t i; + + if (!zalloc_cpumask_var(&req_mask, GFP_KERNEL)) + { + return -ENOMEM; + } + + for (i = 0; i < nirqs; i++) + { + cpumask_set_cpu(cpus[i], req_mask); + irq = dh_irq_request(pool, i, req_mask, 0); + if (IS_ERR_OR_NULL(irq)) + { + break; + } + cpumask_clear(req_mask); + irqs[i] = irq; + } + + free_cpumask_var(req_mask); + + return i ? i : PTR_ERR(irq); +} + +static int32_t req_mask_local_spread(int32_t i, int32_t node, + const struct cpumask *irqs_req_mask) +{ + int32_t cpu; + + if (node == NUMA_NO_NODE) + { + for_each_cpu_and(cpu, cpu_online_mask, irqs_req_mask) + { + if (i-- == 0) + { + return cpu; + } + } + } + else + { + /* NUMA first. */ + for_each_cpu_and(cpu, cpumask_of_node(node), irqs_req_mask) + { + if (cpu_online(cpu)) + { + if (i-- == 0) + { + return cpu; + } + } + } + + for_each_online_cpu(cpu) + { + /* Skip NUMA nodes, done above. */ + if (cpumask_test_cpu(cpu, cpumask_of_node(node))) + { + continue; + } + + if (i-- == 0) + { + return cpu; + } + } + } + WARN_ON(true); + + return cpumask_first(cpu_online_mask); +} + +/** + * dh_irqs_request_mask - request one or more IRQs for zxdh device. + * @pool: requesting the IRQs from the irqs pool. + * @irqs: an output array of IRQs pointers. + * @irqs_req_mask: cpumask requested for these IRQs. + * + * Each IRQ is bounded to at most 1 CPU. + * This function returns the number of IRQs requested, (which might be smaller than + * cpumask_weight(@irqs_req_mask)), if successful, or a negative error code in + * case of an error. + */ +int32_t dh_irqs_request_mask(struct dh_irq_pool *pool, struct dh_irq **irqs, + struct cpumask *irqs_req_mask) +{ + struct dh_irq *irq = NULL; + int32_t nirqs; + int32_t cpu; + int32_t i; + + /* Request an IRQ for each online CPU in the given mask */ + cpumask_and(irqs_req_mask, irqs_req_mask, cpu_online_mask); + nirqs = cpumask_weight(irqs_req_mask); + for (i = 0; i < nirqs; i++) + { + /* Iterate over the mask the caller provided in numa aware fashion. + * Local CPUs are requested first, followed by non-local ones. + */ + cpu = req_mask_local_spread(i, pool->dev->numa_node, irqs_req_mask); + + if (dh_irq_pool_is_sf_pool(pool)) + { + irq = dh_irq_affinity_request(pool, cpumask_of(cpu)); + } + else + { + irq = dh_irq_request(pool, i, cpumask_of(cpu), 0); + } + if (IS_ERR_OR_NULL(irq)) + { + if (i == 0) + { + return PTR_ERR(irq); + } + return i; + } + + irqs[i] = irq; + LOG_DEBUG("IRQ %u mapped to cpu %*pbl, %u EQs on this irq\n", + pci_irq_vector(pool->dev->pdev, dh_irq_get_index(irq)), + cpumask_pr_args(dh_irq_get_affinity_mask(irq)), + dh_irq_read_locked(irq) / DH_EQ_REFS_PER_IRQ); + } + + return i; +} + +struct dh_irq_pool *irq_pool_alloc(struct dh_core_dev *dev, int32_t start, + int32_t size, char *name, + u32 min_threshold, u32 max_threshold) +{ + struct dh_irq_pool *pool = kvzalloc(sizeof(*pool), GFP_KERNEL); + + if (unlikely(pool == NULL)) + { + LOG_ERR("pool kvzalloc failed\n"); + return ERR_PTR(-ENOMEM); + } + + pool->dev = dev; + mutex_init(&pool->lock); + xa_init_flags(&pool->irqs, XA_FLAGS_ALLOC); + pool->xa_num_irqs.min = start; + pool->xa_num_irqs.max = start + size - 1; + + if (name) + { + snprintf(pool->name, DH_MAX_IRQ_NAME - DH_MAX_IRQ_IDX_CHARS, "%s", name); + } + + pool->min_threshold = min_threshold * DH_EQ_REFS_PER_IRQ; + pool->max_threshold = max_threshold * DH_EQ_REFS_PER_IRQ; + + return pool; +} + +void irq_pool_free(struct dh_irq_pool *pool) +{ + struct dh_irq *irq = NULL; + unsigned long index; + uint32_t cpu; + + /* There are cases in which we are destrying the irq_table before + * freeing all the IRQs, fast teardown for example. Hence, free the irqs + * which might not have been freed. + */ + xa_for_each(&pool->irqs, index, irq) + { + irq_release(irq); + } + xa_destroy(&pool->irqs); + mutex_destroy(&pool->lock); + + if (pool->irqs_per_cpu) + { + for_each_online_cpu(cpu) + { + WARN_ON(pool->irqs_per_cpu[cpu]); + } + kfree(pool->irqs_per_cpu); + } + + kvfree(pool); +} + +void dh_irq_table_cleanup(struct dh_core_dev *dev) +{ + if (dh_core_is_sf(dev)) + { + return; + } + + kvfree(dev->irq_table.priv); +} + +void dh_irq_rename(struct dh_core_dev *dev, struct dh_irq *irq, const char *name) +{ + char *dst_name = irq->name; + + if (!name) + { + char default_name[DH_MAX_IRQ_NAME]; + + irq_set_name(irq->pool, default_name, irq->index); + snprintf(dst_name, DH_MAX_IRQ_NAME, "%s@pci:%s", default_name, pci_name(dev->pdev)); + } + else + { + snprintf(dst_name, DH_MAX_IRQ_NAME, "%s-%d", name, irq->index - DH_PF_IRQ_CTRL_NUM); + } +} diff --git a/src/net/drivers/net/ethernet/dinghai/plcr.c b/src/net/drivers/net/ethernet/dinghai/plcr.c new file mode 100644 index 0000000..8e6eaa8 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/plcr.c @@ -0,0 +1,2371 @@ +#include +#include +#include +#include +#include +#include +#include +#include "en_aux.h" +#include "en_ethtool/ethtool.h" +#include +#include +#include +#include "en_np/table/include/dpp_tbl_api.h" +#include "en_aux/events.h" +#include "en_aux/eq.h" +#include "en_aux/en_cmd.h" +#include "msg_common.h" +#include "en_pf.h" +#include +#include "en_aux/en_ioctl.h" +#ifdef TIME_STAMP_1588 +#include "en_aux/en_1588_pkt_proc.h" +#endif + +const uint32_t gaudPlcrCarxProfileNum[E_PLCR_CAR_NUM]={ + PLCR_CAR_A_PROFILE_RES_NUM, //一级CAR：512个限速模板 + PLCR_CAR_B_PROFILE_RES_NUM, //二级CAR：128个限速模板 + PLCR_CAR_C_PROFILE_RES_NUM, //三级CAR：32个限速模板 +}; + +const uint32_t gaudPlcrCarxFlowIdNum[E_PLCR_CAR_NUM]={ + PLCR_CAR_A_FLOWID_RES_NUM, //一级CAR：包含内核和dpdk的id + PLCR_CAR_B_FLOWID_RES_NUM, //二级CAR：前2304个分配给vf，后64个个分配给pf + PLCR_CAR_C_FLOWID_RES_NUM, //三级CAR +}; + +struct zxdh_plcr_cbs gat_carA_byte_rate_limit_cbs[] = +{ + {0, 500, 4*1024*1024}, + {500, 800, 10*1024*1024}, + {800, 1500, 12*1024*1024}, + {1500, 3000, 15*1024*1024}, + {3000, 12000, 20*1024*1024}, + {12000, 20000, 30*1024*1024}, + {20000, 500000, 50*1024*1024}, +}; + +struct zxdh_plcr_cbs gat_carB_byte_rate_limit_cbs[] = +{ + {0, 4000, 8*1024*1024}, + {4000, 8000, 16*1024*1024}, + {8000, 16000, 64*1024*1024}, + {16000, 500000, 128*1024*1024 - 1}, +}; + +static inline struct zxdh_en_device *pf_dev_get_edev(struct zxdh_pf_device *pf_dev) +{ + struct zxdh_auxiliary_device *adev = NULL; + struct zxdh_en_sf_container *sf_con = NULL; + struct zxdh_en_sf_device *en_sf_dev = NULL; + struct zxdh_en_priv *en_priv = NULL; + struct zxdh_en_device *en_dev = NULL; + + adev = pf_dev->adevs_table[0].adev; //sf adev + sf_con = container_of(adev, struct zxdh_en_sf_container, adev); + en_sf_dev = dh_core_priv(sf_con->cdev); //sf cdev + en_priv = en_sf_dev->adev[0]->dev.driver_data; //en adev + en_dev = &en_priv->edev; + + if (!en_dev->init_comp_flag) { + LOG_ERR("en_device not initialized!\n"); + return ERR_PTR(-ENODEV); + } + + return en_dev; +} + +uint32_t zxdh_plcr_get_cbs(E_PLCR_CAR_TYPE car_type, E_RATE_LIMIT_PKT_BYTE is_pkt_mode, uint32_t user_rate_limit, uint32_t *cbs) +{ + uint32_t num; + uint32_t index; + uint32_t flag; + struct zxdh_plcr_cbs *plcr_cbs; + + if (E_RATE_LIMIT_BYTE == is_pkt_mode) + { + if (E_PLCR_CAR_A == car_type) + { + num = sizeof(gat_carA_byte_rate_limit_cbs)/sizeof(struct zxdh_plcr_cbs); + plcr_cbs = &gat_carA_byte_rate_limit_cbs[0]; + } + else if (E_PLCR_CAR_B == car_type) + { + num = sizeof(gat_carB_byte_rate_limit_cbs)/sizeof(struct zxdh_plcr_cbs); + plcr_cbs = &gat_carB_byte_rate_limit_cbs[0]; + } + else if (E_PLCR_CAR_C == car_type) + { + //todo：需要遍历测试得到cbs + *cbs = 8*1024*1024; + return 0; + } + else + { + return -ERANGE; + } + + for(index=0,flag=0; index= plcr_cbs[index].min_rate) && (user_rate_limit < plcr_cbs[index].max_rate)) + { + *cbs = plcr_cbs[index].cbs; + flag = 1; + break; + } + } + if(0 == flag) + { + return -ERANGE; + } + } + else + { + //todo：包限速对应的cbs需要后续遍历测试得到 + return -ERANGE; + } + + return 0; +} + +/* +todo: +rsvd字段为1标识失败，为0标识成功 +修改原有的限速值，只用修改限速模板，不用再调用关联函数； +还有代码中在配置限速模板的时候引用+1了，会影响现有的流程的（结果可能没问题，需要考虑是不是将+1和-1更换位置）； +如果找到共享模板，在配置队列失败的时候会减一，加一和减一的位置不对称，会导致计数值不正确。 +*/ + +/* +函数功能：将用户输入的速率，转换成限速模板配置寄存器的格式 +入参： + ---max_rate : 单位是Mbit/s + +返回值：返回vqm中的发送队列号，发送队列号为奇数 +*/ +uint32_t zxdh_plcr_user_maxrate_2_reg(uint32_t user_max_rate) +{ + uint64_t reg_maxrate; + + PLCR_FUNC_DBG_ENTER(); + + reg_maxrate = ((uint64_t)user_max_rate * 1024 / PLCR_STEP_SIZE);//改为61kbps的倍数,单位由"Mbps"转化为"61Kbps" (uint32_t)(max_rate + 0.5)* 1000 / PLCR_STEP_SIZE + + reg_maxrate = (reg_maxrate < PLCR_MIN_RATE) ? PLCR_MIN_RATE : reg_maxrate; + reg_maxrate = (reg_maxrate > PLCR_MAX_RATE) ? PLCR_MAX_RATE : reg_maxrate; + + return (uint32_t)reg_maxrate; +} + +/* +函数功能：将寄存器中的配置值，转换成用户的限速值（） +将用户输入的速率，转换成限速模板配置寄存器的格式 +入参： + ---maxrate_cfg : 单位是61Kb/s +出参： + ---user_max_rate : 单位是Mbit/s + +返回值：返回vqm中的发送队列号，发送队列号为奇数 +*/ +uint32_t zxdh_plcr_reg_maxrate_user(uint32_t reg_maxrate) +{ + uint32_t user_max_rate; + + PLCR_FUNC_DBG_ENTER(); + + user_max_rate = reg_maxrate * PLCR_STEP_SIZE / 1024; + + return user_max_rate; +} + +/* +函数功能：查找是否有共享的限速模板 +入参： + ---pf_dev : pf设备结构体 + ---car_type : plcr CAR层级，取值：CAR_A，CAR_B，CAR_C + ---profile_cfg: 待查询的限速模板参数，可能是字节限速模板或者包限速模板 + ---profile_id : 保存查询到的限速模板的id + +返回值：0表示查询成功，其它值表示查询失败 +*/ +static int32_t zxdh_plcr_match_profile(struct zxdh_pf_device *pf_dev, + E_PLCR_CAR_TYPE car_type, + DPP_STAT_CAR_PROFILE_CFG_T *profile_cfg, + uint16_t *profile_id) +{ + struct xarray *xarray_profile = &(pf_dev->plcr_table.plcr_profiles[car_type]); + struct zxdh_plcr_profile *profile; + unsigned long index; + DPP_STAT_CAR_PKT_PROFILE_CFG_T *pkt_profile_cfg = (DPP_STAT_CAR_PKT_PROFILE_CFG_T *)(profile_cfg); + uint32_t profile_max_num = gaudPlcrCarxProfileNum[car_type]; + + PLCR_FUNC_DBG_ENTER(); + + /*遍历vf申请的某一级CAR所有限速模板，是否有指定速率的限速模板存在*/ + xa_for_each_range(xarray_profile, index, profile, 0, profile_max_num) + { + if(0 == profile->ref_cnt) + { + continue; + } + + /*包限速模板比较*/ + if (E_RATE_LIMIT_PACKET ==profile_cfg->pkt_sign) + { + if ((pkt_profile_cfg->pkt_sign == (((DPP_STAT_CAR_PKT_PROFILE_CFG_T *)(&profile->profile_cfg))->pkt_sign)) && + (pkt_profile_cfg->cir == (((DPP_STAT_CAR_PKT_PROFILE_CFG_T *)(&profile->profile_cfg))->cir)) && + (pkt_profile_cfg->cbs == (((DPP_STAT_CAR_PKT_PROFILE_CFG_T *)(&profile->profile_cfg))->cbs))) + { + *profile_id = profile->profile_id; + PLCR_LOG_INFO("profile_id = %d\n", *profile_id); + + return 0; + } + } + //字节限速模板比较 + else if (E_RATE_LIMIT_BYTE ==profile_cfg->pkt_sign) + { + if((profile->profile_cfg.pkt_sign == profile_cfg->pkt_sign) && + (profile->profile_cfg.cd == profile_cfg->cd) && /**< @brief CD算法标志/令牌桶算法标志 0:srtcm 1:trtcm 2:MEF10.1*/ + (profile->profile_cfg.cf == profile_cfg->cf) && /**< @brief CF溢出耦合标志，0:不溢出，1:溢出*/ + (profile->profile_cfg.cm == profile_cfg->cm) && /**< @brief CM色盲/色敏标志，0:色盲模式，1:色敏模式 */ + (profile->profile_cfg.cir == profile_cfg->cir) && /**< @brief C令牌桶添加速率(0~X, X Gbps/64kbps),最小值为64Kbps，步长为64Kbps*/ + (profile->profile_cfg.cbs == profile_cfg->cbs) && /**< @brief C桶桶深(XM),配置范围为0~XMByte-1，步长为1Byte*/ + (profile->profile_cfg.eir == profile_cfg->eir) && /**< @brief E令牌桶添加速率(0~X, XGbps/64kbps),最小值为64Kbps，步长为64Kbps*/ + (profile->profile_cfg.ebs == profile_cfg->ebs)) /**< @brief E桶桶深(XM),配置范围为0~XMByte-1，步长为1Byte*/ + { + *profile_id = profile->profile_id; + PLCR_LOG_INFO("profile_id = %d\n", *profile_id); + + return 0; + } + } + } + + /* 未搜索到匹配项*/ + return -ERANGE; +} + +/* +函数功能：为flowid申请一个xarray成员 +入参： + ---pf_dev : pf设备结构体 + ---car_type : plcr CAR层级，一级，二级或三级 + ---flow_id : 作为xarray的索引 +返回值：返回创建的zxdh_plcr_flow *指针 +*/ +int32_t zxdh_plcr_req_flow(struct zxdh_pf_device *pf_dev, + E_PLCR_CAR_TYPE car_type, + uint16_t flow_id, + struct zxdh_plcr_flow **flow) +{ + struct zxdh_plcr_flow *flow_old; + struct xarray *xarray_flow = &(pf_dev->plcr_table.plcr_flows[car_type]); + + PLCR_FUNC_DBG_ENTER(); + + /*1. malloc一个flow结构体*/ + *flow = kzalloc(sizeof(struct zxdh_plcr_flow), GFP_KERNEL); + if (unlikely(NULL == *flow)) + { + PLCR_LOG_ERR("failed to kzalloc \n"); + return -EINVAL; + } + + /*2. 存储到xarray*/ + flow_old = xa_store(xarray_flow, flow_id, *flow, GFP_KERNEL); + if (flow_old) + { + /* 正常情况下，这里应该都是空的*/ + kfree(flow_old); + } + + return 0; +} + +/* +函数功能：释放一个xarray下的flowid成员 +入参： + ---pf_dev : pf设备结构体 + ---car_type : plcr CAR层级，一级，二级或三级 + ---flow_id : 作为xarray的索引 +返回值：返回创建的zxdh_plcr_flow *指针 +*/ +int32_t zxdh_plcr_release_flow(struct zxdh_pf_device *pf_dev, + E_PLCR_CAR_TYPE car_type, + uint16_t flow_id) +{ + struct zxdh_plcr_flow *flow; + struct xarray *xarray_flow = &(pf_dev->plcr_table.plcr_flows[car_type]); + + PLCR_FUNC_DBG_ENTER(); + + /*1. 检查xarray里是否有该flow*/ + flow = xa_load(xarray_flow, flow_id); + if (NULL == flow) + { + PLCR_LOG_ERR("failed to release an invalid flow_id=%d\n", flow_id); + return EINVAL; + } + + /*2. 从xarray删除该成员*/ + xa_erase(xarray_flow, flow_id); + + /*3. 释放flow*/ + kfree(flow); + + return 0; +} + +/* +函数功能：更新flow的成员信息 +入参： + ---flow : xarray的成员 + ---vport : + ---max_rate : + ---min_rate : +返回值：无 +*/ +void zxdh_plcr_update_flow(struct zxdh_plcr_flow *flow, + uint16_t vport, + uint32_t max_rate, + uint32_t min_rate) +{ + flow->vport = vport; + flow->max_rate = max_rate; + flow->min_rate = min_rate; +} + +/* +函数功能：申请一个指定CAR的限速模板 +入参： + ---pf_dev : pf设备结构体 + ---car_type : plcr CAR层级，一级，二级或三级 + ---vport : vf端口号 + ---profile_id_out : 返回申请到的限速模板的profile_id +返回值：成功返回0，失败返回其它值 +*/ +int zxdh_plcr_req_profile(struct zxdh_pf_device *pf_dev, + E_PLCR_CAR_TYPE car_type, + uint16_t *profile_id_out) +{ + int rtn = 0; + struct zxdh_plcr_profile *profile; + struct zxdh_plcr_profile *profile_old; + struct xarray *xarray_profile = &(pf_dev->plcr_table.plcr_profiles[car_type]); + uint16_t profile_id = 0; + uint64_t cred_id = 0; + DPP_PF_INFO_T pf_info = {0}; + + pf_info.slot = pf_dev->slot_id; + pf_info.vport = pf_dev->vport; + + PLCR_FUNC_DBG_ENTER(); + + /*在指定的CAR申请一个新的限速模板*/ + rtn = dpp_car_profile_id_add(&pf_info, (uint32_t)car_type, &cred_id); + if (rtn) + { + /*判断消息交互是否正常*/ + PLCR_LOG_ERR("failed to request a new profile\n"); + return -EINVAL; + } + + /*判断riscv是否成功返回了有效的profile：bit[56 - 63]为0标识成功，为1标识失败*/ + if (0 != ((cred_id >> 56) & 0xFF)) + { + PLCR_LOG_ERR("failed to request a new profile\n"); + return -EINVAL; + } + + /*提取profile id*/ + profile_id = PROFILE_ID(cred_id); + *profile_id_out = profile_id; + PLCR_LOG_INFO("dpp_car_profile_id_add: pf_info.vport = 0x%x, car_type = %d, profile_id = %d, cred_id = 0x%llx\n", pf_info.vport, car_type, profile_id, cred_id); + + /*申请一个限速模板结构体，保存限速模板信息*/ + profile = kzalloc(sizeof(struct zxdh_plcr_profile), GFP_KERNEL); + if (unlikely(NULL == profile)) + { + dpp_car_profile_id_delete(&pf_info, (uint32_t)car_type, cred_id); + PLCR_LOG_ERR("failed to kzalloc profile\n"); + + return -EINVAL; + } + profile->ref_cnt = 0; + profile->max_rate = 0; + profile->min_rate = 0; + profile->cred_id = cred_id; + profile->profile_id = profile_id; + profile->vport = pf_dev->vport; + + /*将申请到的限速模板资源存储起来*/ + profile_old = xa_store(xarray_profile, profile_id, profile, GFP_KERNEL); + if (profile_old) //正常情况下，这里应该都是空的 + { + PLCR_LOG_ERR("failed to unreachable branch\n"); + kfree(profile_old); + } + + + return rtn; +} + +/* +函数功能：释放一个指定CAR的限速模板 +入参： + ---pf_dev : pf设备结构体 + ---car_type : plcr CAR层级，一级，二级或三级 + ---Profile_id : 限速模板的profile_id +返回值：成功返回0，失败返回其它值 +*/ +int zxdh_plcr_release_profile(struct zxdh_pf_device *pf_dev, + E_PLCR_CAR_TYPE car_type, + uint16_t profile_id) +{ + int rtn = 0; + struct xarray *xarray_profile = &(pf_dev->plcr_table.plcr_profiles[car_type]); + struct zxdh_plcr_profile *profile; + DPP_PF_INFO_T pf_info = {0}; + + PLCR_FUNC_DBG_ENTER(); + + /*判断是有是有效成员*/ + profile = xa_load(xarray_profile, profile_id); + if (NULL == profile) + { + PLCR_LOG_ERR("failed to release an invalid profile=%d\n", profile_id); + return EINVAL; + } + + /*如果引用计数为0，则可以释放所有资源*/ + if (0 == profile->ref_cnt) + { + pf_info.slot = pf_dev->slot_id; + pf_info.vport = profile->vport; + PLCR_LOG_INFO("dpp_car_profile_id_delete: pf_info.vport = 0x%x, car_type = %d, profile_id = %d, cred_id = 0x%llx\n", pf_info.vport, car_type, profile_id, profile->cred_id); + + /*归还限速模板资源（注意，引用计数为0表示没有关联的flow了）*/ + rtn = dpp_car_profile_id_delete(&pf_info, car_type, profile->cred_id); + if (rtn) + { + PLCR_LOG_ERR("failed to call dpp_car_profile_id_delete, car_type=%d,profile_id=%d)\n", car_type, profile_id); + rtn = EINVAL; + } + + /*删除xarray中的元素*/ + xa_erase(xarray_profile, profile_id); + + /*释放profile指针*/ + kfree(profile); + } + + /*如果引用计数不为0，就不释放任何资源*/ + return rtn; +} + +/* +函数功能：内核态使用的接口，根据car_type & is_byte_rate_limit & max_rate & min_rate 这4个参数生成限速模板配置参数 + 内核态下各限速场景使用的参数应该是固定的，我们自己根据这4个参数生成完整的结构体参数：DPP_STAT_CAR_PROFILE_CFG_T + 用户态的场景下，会通过消息直接传递过来，不需要组装 +入参： + ---is_pkt_mode: 包限速还是字节限速 + ---car_type : plcr CAR层级，一级，二级或三级 + ---is_byte_rate_limit : 是否是字节限速，为后续包限速预留参数，这个值传参的时候暂时固定为1， + 后续可能会有一个全局变量进行指示，会提供对应的接口来获取这个入参值进行传递 + ---max_rate : 用户指定的最大限速值 + ---min_rate : 用户指定的最小承诺速率 + ---profile_cfg : 返回值，填充好的限速模板参数 +返回值：成功返回0，失败返回其它值 +*/ +static int zxdh_plcr_gen_profile(struct zxdh_pf_device *pf_dev, + E_RATE_LIMIT_PKT_BYTE is_pkt_mode, + E_PLCR_CAR_TYPE car_type, + uint32_t max_rate, + uint32_t min_rate, + DPP_STAT_CAR_PROFILE_CFG_T *profile_cfg) +{ + int rtn = 0; + int pri = 0; + uint32_t cbs = 0; + uint32_t ebs = 0; + DPP_STAT_CAR_PKT_PROFILE_CFG_T *pkt_profile_cfg = (DPP_STAT_CAR_PKT_PROFILE_CFG_T *)(profile_cfg); + + PLCR_FUNC_DBG_ENTER(); + + //入参检测 + if ((E_RATE_LIMIT_PACKET == is_pkt_mode) && (E_PLCR_CAR_A != car_type)) + { + PLCR_LOG_ERR("failed and only CAR A supports packet rate limit\n"); + rtn = EINVAL; + } + + /*2. 重新生成参数*/ + + /*填充限速模板的参数，准备将这些参数配置到寄存器*/ + memset(profile_cfg, 0, sizeof(*profile_cfg)); + if (E_RATE_LIMIT_BYTE == is_pkt_mode) + { + profile_cfg->pkt_sign = E_RATE_LIMIT_BYTE; + profile_cfg->cf = 1; //溢出标志，默认使能 + + if (pf_dev->plcr_table.burst_size) + { + cbs = pf_dev->plcr_table.burst_size; + ebs = pf_dev->plcr_table.burst_size; + } + else + { + rtn = zxdh_plcr_get_cbs(car_type, E_RATE_LIMIT_BYTE, min_rate, &cbs); + PLCR_COMM_ASSERT(rtn); + rtn = zxdh_plcr_get_cbs(car_type, E_RATE_LIMIT_BYTE, max_rate, &ebs); + PLCR_COMM_ASSERT(rtn); + } + + profile_cfg->cbs = cbs; + profile_cfg->ebs = ebs; + profile_cfg->random_disc_c = 0; + profile_cfg->random_disc_e = 0; + + if (E_PLCR_CAR_A == car_type) + { + profile_cfg->cm = 0; //色盲模式 + profile_cfg->cd = 0; //0: srTCM，单速率；1：双速率 + profile_cfg->cir = zxdh_plcr_user_maxrate_2_reg(max_rate); + profile_cfg->eir = 0; + } + else if (E_PLCR_CAR_B == car_type) + { + profile_cfg->cm = 0; //色盲模式，todo：根据实际测试情况来调整 + profile_cfg->cd = 1; //0: srTCM，单速率；1：双速率 + profile_cfg->cir = zxdh_plcr_user_maxrate_2_reg(min_rate); + profile_cfg->eir = zxdh_plcr_user_maxrate_2_reg(max_rate); + } + else if (E_PLCR_CAR_C == car_type) + { + //todo：端口组限速，待调试确认 + profile_cfg->cm = 1; //色敏模式，todo：根据实际测试情况来调整 + profile_cfg->cd = 0; //0: srTCM，单速率；1：双速率 + profile_cfg->cir = zxdh_plcr_user_maxrate_2_reg(max_rate); + profile_cfg->eir = 0; + } + + for (pri = 0; pri < DPP_CAR_PRI_MAX; pri ++) + { + profile_cfg->c_pri[pri] = 0; + profile_cfg->e_green_pri[pri] = 0; + profile_cfg->e_yellow_pri[pri] = 0; + } + + PLCR_LOG_INFO("cir = 0x%x, eir = 0x%x, cbs = 0x%x, ebs = 0x%x\n", profile_cfg->cir, profile_cfg->eir, profile_cfg->cbs, profile_cfg->ebs); + } + else + { + pkt_profile_cfg->pkt_sign = E_RATE_LIMIT_PACKET; + pkt_profile_cfg->cbs = PLCR_CAR_PROFILE_GENERAL_CBS; + pkt_profile_cfg->cir = max_rate; + + PLCR_LOG_INFO("cir = 0x%x, cbs = 0x%x\n", pkt_profile_cfg->cir, pkt_profile_cfg->cbs); + } + + return rtn; +} + +/* +函数功能：更新限速模板参数 +入参： + ---profile_cfg: 限速模板参数结构体 + ---Profile_id : 限速模板的profile_id +返回值：无 +*/ +static void zxdh_plcr_update_profile(DPP_STAT_CAR_PROFILE_CFG_T *profile_cfg, u_int16_t profile_id) +{ + PLCR_FUNC_DBG_ENTER(); + + /*1. 重新生成参数*/ + profile_cfg->profile_id = profile_id; +} + +/* +函数功能：将限速模板参数，存储到profile下 +入参： + ---pf_dev : pf设备结构体 + ---car_type : plcr CAR层级，一级，二级或三级 + ---max_rate : 用户原始的限速速率，单位是Mbit/s + ---min_rate : 用户原始的限速速率，单位是Mbit/s + ---profile_cfg: 要存储到profile中的，限速模板参数 +返回值：成功返回0，失败返回其它值 +*/ +int zxdh_plcr_store_profile(struct zxdh_pf_device *pf_dev, + E_PLCR_CAR_TYPE car_type, + uint32_t user_max_rate, + uint32_t user_min_rate, + DPP_STAT_CAR_PROFILE_CFG_T *profile_cfg) +{ + int rtn = 0; + uint16_t profile_id; + struct zxdh_plcr_profile *profile; + struct xarray *xarray_profile = &(pf_dev->plcr_table.plcr_profiles[car_type]); + + PLCR_FUNC_DBG_ENTER(); + + /*1. 从限速模板结构体，获取profile_id*/ + profile_id = profile_cfg->profile_id; + + /*2. 从xarray获取profile*/ + profile = xa_load(xarray_profile, profile_id); + if (NULL == profile) + { + PLCR_LOG_ERR("failed to specify an invalid profile, profile_id=%d\n", profile_id); + return -EINVAL; + } + + /*3. 更新profile的参数*/ + profile->max_rate = user_max_rate; + profile->min_rate = user_min_rate; + + /*4. 将完整的限速模板参数，存储到profile结构体下*/ + memcpy(&profile->profile_cfg, profile_cfg, sizeof(DPP_STAT_CAR_PROFILE_CFG_T)); + + return rtn; +} + +/* +函数功能：将限速模板参数，配置到plcr寄存器中去 +入参： + ---pf_dev : pf设备结构体 + ---car_type : plcr CAR层级，一级，二级或三级 + ---profile_cfg: 要配置个plcr寄存器的限速模板参数 +返回值：成功返回0，失败返回其它值 +*/ +int zxdh_plcr_cfg_profile(struct zxdh_pf_device *pf_dev, + E_PLCR_CAR_TYPE car_type, + DPP_STAT_CAR_PROFILE_CFG_T *profile_cfg) +{ + int rtn = 0; + uint16_t profile_id = 0; + uint32_t pkt_sign = 0; + DPP_PF_INFO_T pf_info = {0}; + + pf_info.slot = pf_dev->slot_id; + pf_info.vport = pf_dev->vport; + + PLCR_FUNC_DBG_ENTER(); + + /*1. 根据限速模板参数，获取profile_id*/ + profile_id = profile_cfg->profile_id; + + /*2. 根据限速模板参数，获取包/字节模式*/ + pkt_sign = profile_cfg->pkt_sign; + + /*3. 将限速模板参数，配置到寄存器中去*/ + rtn = dpp_car_profile_cfg_set(&pf_info, (uint32_t)car_type, pkt_sign, profile_id, profile_cfg); + if (rtn) + { + PLCR_LOG_ERR("failed to configure the profile registers, car_type=%d,profile_id=%d\n", car_type, profile_id); + return -EINVAL; + } + PLCR_LOG_INFO("dpp_car_profile_cfg_set: pf_info.vport = 0x%x, car_type = %d, profile_id = %d, pkt_sign = %d\n", pf_info.vport, car_type, profile_id, pkt_sign); + + return rtn; +} + +/* +函数功能：获取寄存器中限速模板的参数 +入参： + ---pf_dev : pf设备结构体 + ---car_type : plcr CAR层级，一级，二级或三级 + ---profile_cfg: 要配置个plcr寄存器的限速模板参数 +返回值：成功返回0，失败返回其它值 +*/ +int zxdh_plcr_get_profile(struct zxdh_pf_device *pf_dev, + E_PLCR_CAR_TYPE car_type, + uint32_t pkt_sign, + uint16_t profile_id, + DPP_STAT_CAR_PROFILE_CFG_T *profile_cfg) +{ + int rtn = 0; + DPP_PF_INFO_T pf_info = {0}; + + pf_info.slot = pf_dev->slot_id; + pf_info.vport = pf_dev->vport; + + PLCR_FUNC_DBG_ENTER(); + + /*3. 将限速模板参数，配置到寄存器中去*/ + PLCR_LOG_INFO("dpp_car_profile_cfg_get: pf_info.vport = 0x%x, car_type = %d, profile_id = %d, pkt_sign = %d\n", pf_info.vport, car_type, profile_id, pkt_sign); + rtn = dpp_car_profile_cfg_get(&pf_info, car_type, pkt_sign, profile_id, profile_cfg); + if (rtn) + { + PLCR_LOG_ERR("failed to call dpp_car_profile_cfg_get(), car_type=%d,profile_id=%d\n", car_type, profile_id); + return -EINVAL; + } + + return rtn; +} + +/* +函数功能：配置指定CAR的限速模板：考虑plcr三级CAR能共享接口 +入参： + ---pf_dev : pf设备结构体 + ---car_type : plcr CAR层级，一级，二级或三级 + ---flowid : 指定CAR的flow编号 + ---profile_id : 申请到的指定CAR层级的profile资源的id +返回值：成功返回0，失败返回其它值 +*/ +static int zxdh_plcr_bind_flow_profile(struct zxdh_pf_device *pf_dev, + E_PLCR_CAR_TYPE car_type, + uint32_t flowid, + uint16_t profile_id) +{ + int rtn = 0; + struct zxdh_plcr_flow *plcr_flow; + struct xarray *xarray_flow = &(pf_dev->plcr_table.plcr_flows[car_type]); + DPP_PF_INFO_T pf_info = {0}; + + pf_info.slot = pf_dev->slot_id; + pf_info.vport = pf_dev->vport; + + PLCR_FUNC_DBG_ENTER(); + + /*1. 获取plcr*/ + plcr_flow = xa_load(xarray_flow, flowid); + if (NULL == plcr_flow) + { + PLCR_LOG_ERR("failed to xa_load an invalid element,car_type=%d,flowid=%d,profile_id=%d\n", car_type, flowid, profile_id); + return -EINVAL; + } + + /*2. 调用接口，将flow与profile进行绑定*/ + PLCR_LOG_INFO("dpp_car_queue_cfg_set: pf_info.vport = 0x%x, car_type = %d, flowid = %d, profile_id = %d\n", pf_info.vport, car_type, flowid, profile_id); + rtn = dpp_car_queue_cfg_set(&pf_info, (uint32_t)car_type, flowid, DROP_DISABLE, PLCR_ENABLE, profile_id); + if (rtn) + { + PLCR_LOG_ERR("failed to call dpp_car_queue_cfg_set(),car_type=%d,flowid=%d,profile_id=%d\n", car_type, flowid, profile_id); + return -EINVAL; + } + PLCR_LOG_INFO("Bind profile_%d to flow_%d complete\n", profile_id, flowid); + + /*3. 将profile_id更新到plcr中*/ + plcr_flow->profile_id = profile_id; + + return rtn; +} + +/* +函数功能：解除flow和profile之间的绑定 & 删除xarray中的元素 & 释放flow指针 +入参： + ---pf_dev : pf设备结构体 + ---car_type : plcr CAR层级，一级，二级或三级 + ---flowid : 指定CAR的flow编号 + ---profile_id : 申请到的指定CAR层级的profile资源的id +返回值：成功返回0，失败返回其它值 +*/ +int zxdh_plcr_unbind_flow_profile(struct zxdh_pf_device *pf_dev, + E_PLCR_CAR_TYPE car_type, + uint32_t flowid, + uint16_t profile_id) +{ + int rtn = 0; + struct zxdh_plcr_flow *plcr_flow; + struct xarray *xarray_flow = &(pf_dev->plcr_table.plcr_flows[car_type]); + DPP_PF_INFO_T pf_info = {0}; + + pf_info.slot = pf_dev->slot_id; + pf_info.vport = pf_dev->vport; + + PLCR_FUNC_DBG_ENTER(); + + /*1. 检查flow是否与profile是否已绑定*/ + plcr_flow = xa_load(xarray_flow, flowid); + if (NULL == plcr_flow) + { + PLCR_LOG_ERR("xa_load an invalid element, flowid=%d,profile_id=%d\n", flowid, profile_id); + return -EINVAL; + } + if (profile_id != plcr_flow->profile_id) + { + PLCR_LOG_ERR("xa_load an invalid element, profile_id=%d,plcr_flow->profile_id=%d\n", profile_id, plcr_flow->profile_id); + return -EINVAL; + } + + /*调用接口，将flow与profile进行解除绑定：配置flow，将其不要指向profile*/ + PLCR_LOG_INFO("dpp_car_queue_cfg_set: pf_info.vport = 0x%x, car_type = %d, flowid = %d, profile_id = %d\n", pf_info.vport, car_type, flowid, profile_id); + rtn = dpp_car_queue_cfg_set(&pf_info, (uint32_t)car_type, flowid, DROP_DISABLE, PLCR_DISABLE, profile_id); + if (rtn) + { + PLCR_LOG_ERR("failed to call dpp_car_queue_cfg_set(),car_type=%d,flowid=%d,profile_id=%d\n", car_type, flowid,profile_id); + return rtn; + } + + return rtn; +} + +int zxdh_plcr_count_up_profile(struct zxdh_pf_device *pf_dev, + E_PLCR_CAR_TYPE car_type, + uint16_t profile_id) +{ + int rtn = 0; + struct zxdh_plcr_profile *plcr_profile; + struct xarray *xarray_profile = &(pf_dev->plcr_table.plcr_profiles[car_type]); + + PLCR_FUNC_DBG_ENTER(); + + plcr_profile = xa_load(xarray_profile, profile_id); + if (NULL == plcr_profile) + { + PLCR_LOG_ERR("failed to load element form xarray_profile, car_type=%d,profile_id=%d\n", car_type, profile_id); + return -EINVAL; + } + + plcr_profile->ref_cnt++; + + return rtn; +} + +int zxdh_plcr_count_down_profile(struct zxdh_pf_device *pf_dev, + E_PLCR_CAR_TYPE car_type, + uint16_t profile_id) +{ + int rtn = 0; + struct zxdh_plcr_profile *plcr_profile; + struct xarray *xarray_profile = &(pf_dev->plcr_table.plcr_profiles[car_type]); + + PLCR_FUNC_DBG_ENTER(); + + plcr_profile = xa_load(xarray_profile, profile_id); + if (NULL == plcr_profile) + { + PLCR_LOG_ERR("failed to load element form xarray_profile, car_type=%d,profile_id=%d\n", car_type, profile_id); + return -EINVAL; + } + + //不能对计数为0的profile进行减操作 + if (0 == plcr_profile->ref_cnt) + { + PLCR_LOG_ERR("failed and plcr_profile->ref_cnt=0\n"); + return -EINVAL; + } + + plcr_profile->ref_cnt--; + + return rtn; +} + +static int zxdh_plcr_get_profile_by_flowid(struct zxdh_pf_device *pf_dev, + E_PLCR_CAR_TYPE car_type, + uint32_t flowid, + struct zxdh_plcr_profile **pplcr_profile) +{ + int rtn = 0; + uint16_t profile_id = 0; + struct zxdh_plcr_profile *plcr_profile; + struct zxdh_plcr_flow *plcr_flow; + struct xarray *xarray_profile = &(pf_dev->plcr_table.plcr_profiles[car_type]); + struct xarray *xarray_flow = &(pf_dev->plcr_table.plcr_flows[car_type]); + + PLCR_FUNC_DBG_ENTER(); + + plcr_flow = xa_load(xarray_flow, flowid); + if (NULL == plcr_flow) + { + PLCR_LOG_ERR("failed to load element form xarray_flow, car_type=%d,flowid=%d\n", car_type, flowid); + return -EINVAL; + } + profile_id = plcr_flow->profile_id; + + plcr_profile = xa_load(xarray_profile, profile_id); + if (NULL == plcr_profile) + { + PLCR_LOG_ERR("failed to load element form xarray_profile,car_type=%d,profile_id=%d\n", car_type, profile_id); + return -EINVAL; + } + + *pplcr_profile = plcr_profile; + + return rtn; +} + +/*******************************下面是新实现的代码*******************************/ +/* +函数功能：将car之间flowid的映射关系存储起来 + +入参： + --- +出参： + --- + +返回值：成功返回0，失败返回其它值 +*/ +int32_t zxdh_plcr_stroe_map(struct zxdh_pf_device *pf_dev, + E_PLCR_CAR_TYPE car_type, + uint32_t flowid, + uint32_t map_flowid) +{ int32_t rtn = 0; + + struct xarray *xarray_map = &(pf_dev->plcr_table.plcr_maps[car_type]); + if((E_PLCR_CAR_A == car_type) || (E_PLCR_CAR_B == car_type)) + { + xa_store(xarray_map, flowid, (void *)(uintptr_t)(FLOWID_2_XARRAY(map_flowid)), GFP_KERNEL); + } + + return rtn; +} + +int32_t zxdh_plcr_clear_map(struct zxdh_pf_device *pf_dev, + E_PLCR_CAR_TYPE car_type, + uint32_t flowid) +{ int32_t rtn = 0; + void * xarray_element; + + struct xarray *xarray_map = &(pf_dev->plcr_table.plcr_maps[car_type]); + if((E_PLCR_CAR_A == car_type) || (E_PLCR_CAR_B == car_type)) + { + xarray_element = xa_load(xarray_map, flowid); + if(NULL != xarray_element) + { + xa_erase(xarray_map, flowid); + } + } + + return rtn; +} + +/* +函数功能：指定前一级的flowid，查询下一级映射的flowid + +入参： + --- +出参： + --- + +返回值：成功返回0，失败返回其它值 +*/ +int32_t zxdh_plcr_get_next_map(struct zxdh_pf_device *pf_dev, + E_PLCR_CAR_TYPE car_type, + uint32_t flowid, + uint32_t *map_flowid) +{ + int32_t rtn = 0; + void * xarray_element; + + struct xarray *xarray_map = &(pf_dev->plcr_table.plcr_maps[car_type]); + if((E_PLCR_CAR_A == car_type) || (E_PLCR_CAR_B == car_type)) + { + xarray_element = xa_load(xarray_map, flowid); + if(NULL == xarray_element) + { + rtn = -EINVAL; + } + else + { + *map_flowid = XARRAY_2_FLOWID((uint32_t)(uintptr_t)xarray_element); + } + } + else + { + rtn = -ERANGE; + } + + return rtn; +} + +/* +函数功能：检查指定的car_type所在的三级car flowid链是否全都没有限速，如果是就进行资源清理 +入参： + ---pf_dev : 设备结构体 + ---vport : 标识vf端口 +场景说明： + 1. 为什么要引入这个接口？ + 新的方案引入了mode 0，mode 1，mode 2三种模式； + vport在三级car上有一条完整的flowid映射链； + 用户在解除某一级car指定flowid的限速之后，驱动程序需要检查这个链上是不是没有限速了，且car C是不是处于group 0，如果是这样的话就要切换到模式0； + 2. 切换到模式0的必要性 + 驱动程序中很多限速要需要先判断当前的限速模式； + 如果当前链上已经没有限速，且car C还是处于group 0，就必须切换回模式0，这也是从模式1和模式2切换回模式0的唯一途径 + 3. 在什么时候需要调用这个接口？ + 用户在解除某一级car指定flowid的限速之后，需要调用这个接口。 + 4.流程： + 3.1 如果是对car C的group解除限速，说明group是非0的，函数直接返回(废弃，因为有可能是将vf端口从非0group移动到group0) + 3.2 根据vport得到car B的flowid + 3.3 根据car B的flowid，查询得到car c的flowid + 3.4.1 如果car C的flowid处于group 0，就进行模式切换 + 3.4.2 如果car C的flowid不处于group 0，就不进行模式切换，函数返回 + 5.plcr_maps是否需要清除？ + 这个资源不需要清除：只有本函数会用到这个记录，且进行限速配置的时候会重新进行映射，且存储的成员不是动态分配的内存，没有必要清理资源； + +返回值：成功返回0，失败返回其它值 +*/ +int zxdh_plcr_check_release_flow_chain(struct zxdh_pf_device *pf_dev, uint16_t vport) +{ + int rtn = 0; + E_PLCR_CAR_TYPE car_type; + uint32_t flag1 = 0; + uint32_t flag2 = 0; + unsigned long flow_index; + uint32_t flowid_car_B; + uint32_t flowid_car_C; + struct zxdh_plcr_flow *flow; + struct xarray *xarray_flow; + + //统计car A和car B上是否有限速 + for(car_type = E_PLCR_CAR_A, flag1 = 0; car_type < E_PLCR_CAR_C; car_type++) + { + xarray_flow = &(pf_dev->plcr_table.plcr_flows[car_type]); + + xa_for_each_range(xarray_flow, flow_index, flow, 0, gaudPlcrCarxFlowIdNum[car_type]) + { + if(vport == flow->vport) + { + flag1 = 1; + break; + } + } + if(1 == flag1) + { + break; + } + } + + //检查是否处于group 0 + if(0 == flag1) + { + //如果是vf，就要检查group是否为0 + if (VF_ACTIVE(vport)) + { + flowid_car_B = VQM_VFID(vport) * 2; + rtn = zxdh_plcr_get_next_map(pf_dev, E_PLCR_CAR_B, flowid_car_B, &flowid_car_C); + PLCR_LOG_INFO("flowid_car_B = 0x%x\n", flowid_car_B); + PLCR_LOG_INFO("flowid_car_C = 0x%x\n", flowid_car_C); + PLCR_COMM_ASSERT(rtn); + + //4个EP * 8PF * 2收发方向，每个pf占32个car c flowid，前面2个映射到group 0 + if (0 == (flowid_car_C%(PLCR_CAR_C_FLOWIDS_PER_PF))) + { + flag2 = 1; + } + } + else + { + //如果是pf（队列限速），就没有car B和Car C + flag2 = 1; + } + + } + + if(0 != flag2) + { + //执行清理操作 + + //1.清理级间映射 + // for (index=0; indexplcr_table.plcr_flows[car_type]); + struct zxdh_plcr_flow *plcr_flow = xa_load(xarray_flowid, flowid); + struct zxdh_plcr_profile *profile_old = NULL; + + PLCR_FUNC_DBG_ENTER(); + + /*1. 如果二次修改的限速值和原来的一样，这个配置操作无意义，直接结束*/ + if (E_PLCR_CAR_A == car_type) + { + if (plcr_flow->max_rate == max_rate) + { + PLCR_LOG_ERR("failed and invalid max_rate=%d on flowid=%d\n", max_rate, flowid); + PLCR_COMM_ASSERT(PLCR_MODIFY_RATE_LIMIT_INVALID_OPERATION_ERR); + } + } + else if((E_PLCR_CAR_B == car_type) || (E_PLCR_CAR_C == car_type)) + { + if ((plcr_flow->max_rate == max_rate) && (plcr_flow->min_rate == min_rate)) + { + PLCR_LOG_ERR("failed and invalid max_rate=%d, min_rate=%d on flowid=%d\n", max_rate, min_rate, flowid); + PLCR_COMM_ASSERT(PLCR_MODIFY_RATE_LIMIT_INVALID_OPERATION_ERR); + } + } + + /*2. 根据新的限速值，生成限速模板参数*/ + rtn = zxdh_plcr_gen_profile(pf_dev, is_pkt_mode, car_type, max_rate, min_rate, &profile_cfg); + PLCR_COMM_ASSERT(rtn); + + /*3. 获取原来关联的限速模板*/ + rtn = zxdh_plcr_get_profile_by_flowid(pf_dev, car_type, flowid, &profile_old); + PLCR_COMM_ASSERT(rtn); + + /*3. 先查询有没有相同速率的限速模板*/ + rtn = zxdh_plcr_match_profile(pf_dev, car_type, &profile_cfg, &profile_id); + if (rtn) + { + /*3.1 没有找到能共享的限速模板*/ + + /*3.2 原来的模板不是共享模板：直接修改限速模板的限速值*/ + if (1 == profile_old->ref_cnt) + { + /*3.2.1 将profile_id更新到限速模板参数中去*/ + zxdh_plcr_update_profile(&profile_cfg, profile_old->profile_id); + + /*3.2.2 将限速模板的参数，配置到寄存器中去*/ + rtn = zxdh_plcr_cfg_profile(pf_dev, car_type, &profile_cfg); + PLCR_COMM_ASSERT(rtn); + + /*3.2.3 将限速模板配置参数，保存到zxdh_plcr_profile结构体*/ + rtn = zxdh_plcr_store_profile(pf_dev, car_type, max_rate, min_rate, &profile_cfg); + PLCR_COMM_ASSERT(rtn); + + /* 更新flow中记录的用户原始限速值，todo：是否使用bind函数，要考虑后期在哪里加锁*/ + zxdh_plcr_update_flow(plcr_flow, plcr_flow->vport, max_rate, min_rate); + + /*这种情况只修改限速模板的寄存器，flowid先前已经与profile绑定了*/ + return rtn; + } + + /*3.3 原来的限速模板是共享模板，所以要申请新的限速模板*/ + rtn = zxdh_plcr_req_profile(pf_dev, car_type, &profile_id); + PLCR_COMM_ASSERT(rtn); + + /*3.4 将profile_id更新到限速模板参数中去*/ + zxdh_plcr_update_profile(&profile_cfg, profile_id); + + /*3.5 将限速模板的参数，配置到寄存器中去*/ + rtn = zxdh_plcr_cfg_profile(pf_dev, car_type, &profile_cfg); + if (rtn) + { + PLCR_LOG_ERR("failed to call zxdh_plcr_cfg_profile()\n"); + goto err4; + } + + /*3.6 将限速模板配置参数，保存到zxdh_plcr_profile结构体*/ + rtn = zxdh_plcr_store_profile(pf_dev, car_type, max_rate, min_rate, &profile_cfg); + if (rtn) + { + PLCR_LOG_ERR("failed to call zxdh_plcr_store_profile()\n"); + goto err4; + } + + /*3.7 接下来的绑定流程，和下面是共享的*/ + } + /*4. 查询到共享的限速模板：直接进行绑定即可*/ + rtn = zxdh_plcr_bind_flow_profile(pf_dev, car_type, flowid, profile_id); + if (rtn) + { + PLCR_LOG_ERR("failed to call zxdh_plcr_bind_flow_profile()\n"); + goto err4; + } + + /*5. 更新flow中记录的用户原始限速值*/ + zxdh_plcr_update_flow(plcr_flow, plcr_flow->vport, max_rate, min_rate); + + /*6. 新模板使用计数+1*/ + rtn = zxdh_plcr_count_up_profile(pf_dev, car_type, profile_id); + if (rtn) + { + PLCR_LOG_ERR("failed to call zxdh_plcr_count_up_profile()\n"); + goto err4; + } + + /*7. 旧的计数模板-1*/ + rtn = zxdh_plcr_count_down_profile(pf_dev, car_type, profile_old->profile_id); + if (rtn) + { + PLCR_LOG_ERR("failed to call zxdh_plcr_count_up_profile()\n"); + goto err4; + } + + zxdh_plcr_release_profile(pf_dev, car_type, profile_old->profile_id); + + return rtn; + +err4: + zxdh_plcr_release_profile(pf_dev, car_type, profile_id); + return rtn; +} + +int zxdh_plcr_remove_rate_limit(struct zxdh_pf_device *pf_dev, + E_PLCR_CAR_TYPE car_type, + uint32_t flowid) +{ + int rtn = 0; + struct zxdh_plcr_profile *profile_old = NULL; + + PLCR_FUNC_DBG_ENTER(); + + PLCR_LOG_INFO("car_type=%d,flowid=%d\n",car_type,flowid); + + /* 获取原来关联的限速模板*/ + rtn = zxdh_plcr_get_profile_by_flowid(pf_dev, car_type, flowid, &profile_old); + PLCR_COMM_ASSERT(rtn); + + /*解除绑定*/ + rtn = zxdh_plcr_unbind_flow_profile(pf_dev, car_type, flowid, profile_old->profile_id); + //PLCR_COMM_ASSERT(rtn); + + /*限速模板引用计数 -1*/ + rtn = zxdh_plcr_count_down_profile(pf_dev, car_type, profile_old->profile_id); + //PLCR_COMM_ASSERT(rtn); + + /*释放限速模板：如果引用计数为0，归还模板资源 & 删除xarray元素 & 释放profile指针*/ + rtn = zxdh_plcr_release_profile(pf_dev, car_type, profile_old->profile_id); + //PLCR_COMM_ASSERT(rtn); + + /*释放掉flow*/ + rtn = zxdh_plcr_release_flow(pf_dev, car_type, flowid); + //PLCR_COMM_ASSERT(rtn); + + return rtn; +} + +void zxdh_plcr_count_profiles(struct zxdh_pf_device *pf_dev) +{ + struct zxdh_plcr_profile *profile; + unsigned long index; + uint32_t count = 0; + E_PLCR_CAR_TYPE car_type; + + PLCR_FUNC_DBG_ENTER(); + + for (car_type = E_PLCR_CAR_A; car_type < E_PLCR_CAR_NUM; car_type ++) + { + count = 0; + xa_for_each_range(&(pf_dev->plcr_table.plcr_profiles[car_type]), index, profile, 0, gaudPlcrCarxProfileNum[car_type]) + { + count++; + } + PLCR_LOG_INFO("car_type = %d, profiles_num = %d\n", car_type, count); + } +} + +int zxdh_plcr_set_rate_limit(struct zxdh_pf_device *pf_dev, + E_RATE_LIMIT_PKT_BYTE is_pkt_mode, + E_PLCR_CAR_TYPE car_type, + uint16_t vport, + uint32_t flowid, + uint32_t max_rate, + uint32_t min_rate) +{ + int rtn = 0; + struct xarray *xarray_flow = &(pf_dev->plcr_table.plcr_flows[car_type]); + struct zxdh_plcr_flow *flow = NULL; + + PLCR_FUNC_DBG_ENTER(); + + /*1. 判断该队列先前是否已经配置过限速值*/ + flow = xa_load(xarray_flow, flowid); + if (NULL == flow) + { + /*1.1 初次配置限速值*/ + rtn = zxdh_plcr_create_rate_limit(pf_dev, is_pkt_mode, car_type, vport, flowid, max_rate, min_rate); + PLCR_COMM_ASSERT(rtn); + } + else if ((max_rate != 0) || (min_rate != 0)) + { + /*1.2 修改限速值*/ + rtn = zxdh_plcr_modify_rate_limit(pf_dev, is_pkt_mode, car_type, flowid, max_rate, min_rate); + PLCR_COMM_ASSERT(rtn); + } + else + { + /*1.3.1 解除限速：即，第二次配置，且max_rate=0，表示用户要解除限速*/ + rtn = zxdh_plcr_remove_rate_limit(pf_dev, car_type, flowid); + PLCR_COMM_ASSERT(rtn); + + zxdh_plcr_check_release_flow_chain(pf_dev, vport); + + //不是错误码，用来标记是进行了解除限速的操作 + rtn = PLCR_REMOVE_RATE_LIMIT; + } + + zxdh_plcr_count_profiles(pf_dev); + + return rtn; +} + +E_RATE_LIMIT_MODE g_plcr_mode[PF_VQM_VFID_OFFSET + 32] = {0xff}; +int zxdh_plcr_set_mode(struct zxdh_pf_device *pf_dev, uint16_t vport, E_RATE_LIMIT_MODE mode) +{ + uint16_t vfid = VQM_VFID(vport); +#if 1 + g_plcr_mode[vfid] = mode; +#else + //todo：设置vf端口当前的模式 +#endif + PLCR_LOG_INFO("zxdh_plcr_set_mode():g_plcr_mode[%d]=%d\n", vfid, g_plcr_mode[vfid]); + + return 0; +} + +int zxdh_plcr_get_mode(struct zxdh_pf_device *pf_dev, uint16_t vport, E_RATE_LIMIT_MODE *mode) +{ + uint16_t vfid = VQM_VFID(vport); + +#if 1 + *mode = g_plcr_mode[vfid]; +#else + //todo：获取vf端口当前的模式 +#endif + PLCR_LOG_INFO("zxdh_plcr_get_mode():g_plcr_mode[%d]=%d\n", vfid, g_plcr_mode[vfid]); + + return 0; +} + +int zxdh_plcr_show_rate_limit_paras(zxdh_plcr_rate_limit_paras *rate_limit_paras) +{ + PLCR_LOG_INFO("rate_limit_paras->req_type = 0x%x\n", rate_limit_paras->req_type); + PLCR_LOG_INFO("rate_limit_paras->direction = 0x%x\n", rate_limit_paras->direction); + PLCR_LOG_INFO("rate_limit_paras->mode = 0x%x\n", rate_limit_paras->mode); + PLCR_LOG_INFO("rate_limit_paras->max_rate = 0x%x\n", rate_limit_paras->max_rate); + PLCR_LOG_INFO("rate_limit_paras->min_rate = 0x%x\n", rate_limit_paras->min_rate); + PLCR_LOG_INFO("rate_limit_paras->queue_id = 0x%x\n", rate_limit_paras->queue_id); + PLCR_LOG_INFO("rate_limit_paras->vf_idx = 0x%x\n", rate_limit_paras->vf_idx); + PLCR_LOG_INFO("rate_limit_paras->vfid = 0x%x\n", rate_limit_paras->vfid); + PLCR_LOG_INFO("rate_limit_paras->vport = 0x%x\n", rate_limit_paras->vport); + PLCR_LOG_INFO("rate_limit_paras->group_id = 0x%x\n", rate_limit_paras->group_id); + + return 0; +} + +int zxdh_plcr_check_req_type(struct zxdh_pf_device *pf_dev, E_RATE_LIMIT_MODE mode, zxdh_plcr_rate_limit_paras *rate_limit_paras, E_RATE_LIMIT_REQ_TYPE *req_type) +{ + PLCR_FUNC_DBG_ENTER(); + + //队列字节限速 + if ((rate_limit_paras->req_type == E_RATE_LIMIT_REQ_QUEUE_BYTE) && + (rate_limit_paras->mode == E_RATE_LIMIT_BYTE) && + ((rate_limit_paras->min_rate != PLCR_INVALID_PARAM) || (rate_limit_paras->max_rate != PLCR_INVALID_PARAM)) && + (rate_limit_paras->direction == E_RATE_LIMIT_TX) && + (rate_limit_paras->vf_idx == PLCR_INVALID_PARAM) && + (rate_limit_paras->group_id == PLCR_INVALID_PARAM) && + (rate_limit_paras->queue_id < PLCR_MAX_QUEUE_PAIRS)) + { + *req_type = E_RATE_LIMIT_REQ_QUEUE_BYTE; + + //mode2模式下不支持队列字节限速 + if(E_RATE_LIMIT_MODE2 == mode) + { + PLCR_LOG_ERR("E_RATE_LIMIT_REQ_QUEUE_BYTE is not supported under E_RATE_LIMIT_MODE2\n"); + return PLCR_GET_REQ_TYPE_INVALID_ERR; + } + + //端口组默认为0 + rate_limit_paras->group_id = 0; + + return 0; + } + //vf端口字节限速 + else if ((rate_limit_paras->req_type == E_RATE_LIMIT_REQ_VF_BYTE) && + (rate_limit_paras->mode == E_RATE_LIMIT_BYTE) && + ((rate_limit_paras->min_rate != PLCR_INVALID_PARAM) || (rate_limit_paras->max_rate != PLCR_INVALID_PARAM)) && + ((rate_limit_paras->direction == E_RATE_LIMIT_RX) || (rate_limit_paras->direction == E_RATE_LIMIT_TX)) && + (rate_limit_paras->group_id == PLCR_INVALID_PARAM) && + (rate_limit_paras->vf_idx != PLCR_INVALID_PARAM)) + { + + //端口组默认为0： + rate_limit_paras->group_id = 0; + + *req_type = E_RATE_LIMIT_REQ_VF_BYTE; + return 0; + } + //vf端口包限速 + else if ((rate_limit_paras->req_type == E_RATE_LIMIT_REQ_VF_PKT) && + (rate_limit_paras->mode == E_RATE_LIMIT_PACKET) && + ((rate_limit_paras->min_rate != PLCR_INVALID_PARAM) || (rate_limit_paras->max_rate != PLCR_INVALID_PARAM)) && + ((rate_limit_paras->direction == E_RATE_LIMIT_RX) || (rate_limit_paras->direction == E_RATE_LIMIT_TX)) && + (rate_limit_paras->group_id == PLCR_INVALID_PARAM) && + (rate_limit_paras->vf_idx != PLCR_INVALID_PARAM)) + { + *req_type = E_RATE_LIMIT_REQ_VF_PKT; + //mode1模式下不支持端口包限速 + if(E_RATE_LIMIT_MODE1 == mode) + { + PLCR_LOG_ERR("E_RATE_LIMIT_REQ_VF_PKT is not supported under E_RATE_LIMIT_MODE1\n"); + return PLCR_GET_REQ_TYPE_INVALID_ERR; + } + + //端口组默认为0 + rate_limit_paras->group_id = 0; + + return 0; + } + //端口组字节限速 + else if ((rate_limit_paras->req_type == E_RATE_LIMIT_REQ_VF_GROUP_BYTE) && + (rate_limit_paras->mode == E_RATE_LIMIT_BYTE) && + ((rate_limit_paras->min_rate != PLCR_INVALID_PARAM) || (rate_limit_paras->max_rate != PLCR_INVALID_PARAM)) && + ((rate_limit_paras->direction == E_RATE_LIMIT_RX) || (rate_limit_paras->direction == E_RATE_LIMIT_TX)) && + (rate_limit_paras->vf_idx == PLCR_INVALID_PARAM) && //不需要flowid级间映射，不需要vf_idx，不需要Vfid + (rate_limit_paras->group_id != PLCR_INVALID_PARAM)) + { + *req_type = E_RATE_LIMIT_REQ_VF_GROUP_BYTE; + return 0; + } + //移动vf端口组 + else if ((rate_limit_paras->req_type == E_RATE_LIMIT_REQ_MOVE_VF_GROUP) && + (rate_limit_paras->mode == PLCR_INVALID_PARAM) && + ((rate_limit_paras->min_rate == PLCR_INVALID_PARAM) && (rate_limit_paras->max_rate == PLCR_INVALID_PARAM)) && + ((rate_limit_paras->direction == E_RATE_LIMIT_RX) || (rate_limit_paras->direction == E_RATE_LIMIT_TX)) && + (rate_limit_paras->vf_idx != PLCR_INVALID_PARAM) && + (rate_limit_paras->group_id != PLCR_INVALID_PARAM)) + { + *req_type = E_RATE_LIMIT_REQ_MOVE_VF_GROUP; + return 0; + } + else + { + //将入参中的请求信息打印出来 + zxdh_plcr_show_rate_limit_paras(rate_limit_paras); + + return PLCR_GET_REQ_TYPE_INVALID_ERR; + } +} + +int32_t zxdh_pf_get_vf_queue_info(struct zxdh_pf_device *pf_dev, int32_t vf_idx, int32_t *phy_queue_num, int32_t *phy_rx_queue, int32_t *phy_tx_queue) +{ + int32_t rtn = 0; + int32_t i; + union zxdh_msg msg = {0}; + int32_t queue_pair_index; + int32_t queue_num; + int32_t queue_pair = 0; + struct dh_core_dev *dh_dev = container_of((void*)pf_dev, struct dh_core_dev, priv); + struct zxdh_en_device *en_dev; + + PLCR_FUNC_DBG_ENTER(); + + en_dev = pf_dev_get_edev(pf_dev); + if (IS_ERR(en_dev)) + return PTR_ERR(en_dev); + + msg.payload.hdr_vf.op_code = ZXDH_PF_GET_VF_QUEUE_INFO; + msg.payload.hdr_vf.dst_pcie_id = FIND_VF_PCIE_ID(pf_dev->pcie_id, vf_idx); + + for(queue_pair_index = 0; queue_pair_index < PLCR_MAX_QUEUE_PAIRS;) + { + msg.payload.plcr_pf_get_vf_queue_info_msg.vir_queue_start = queue_pair_index; + msg.payload.plcr_pf_get_vf_queue_info_msg.vir_queue_num = 16; + + //get rx&tx phy queue + PLCR_LOG_INFO("msg.payload.plcr_pf_get_vf_queue_info_msg.vir_queue_start = 0x%x\n", msg.payload.plcr_pf_get_vf_queue_info_msg.vir_queue_start); + PLCR_LOG_INFO("msg.payload.plcr_pf_get_vf_queue_info_msg.vir_queue_num = 0x%x\n", msg.payload.plcr_pf_get_vf_queue_info_msg.vir_queue_num); + rtn = zxdh_pf_msg_send_cmd(dh_dev, MODULE_PF_BAR_MSG_TO_VF, &msg, &msg, true); + PLCR_COMM_ASSERT(rtn); + + queue_num = msg.reps.plcr_pf_get_vf_queue_info_rsp.phy_queue_num; + for(i = 0; i < queue_num; i++) + { + phy_rx_queue[queue_pair_index*16 + i] = msg.reps.plcr_pf_get_vf_queue_info_rsp.phy_rxq[i]; + phy_tx_queue[queue_pair_index*16 + i] = msg.reps.plcr_pf_get_vf_queue_info_rsp.phy_txq[i]; + + PLCR_LOG_INFO("rxq: 0x%x - 0x%x\n", queue_pair_index*16 + i, phy_rx_queue[queue_pair_index*16 + i]); + PLCR_LOG_INFO("txq: 0x%x - 0x%x\n", queue_pair_index*16 + i, phy_tx_queue[queue_pair_index*16 + i]); + } + + queue_pair += queue_num; + + if(queue_num < 16) + { + *phy_queue_num = queue_pair; + + PLCR_LOG_INFO("phy_queue_num = 0x%x\n", *phy_queue_num); + + return rtn; + } + else + { + queue_pair_index += 16; + } + } + + return rtn; +} + +int zxdh_plcr_map_flowid(struct zxdh_pf_device *pf_dev, E_PLCR_CAR_TYPE car_type, uint32_t flowid, uint32_t map_flowid) +{ + int rtn = 0; + uint32_t map_sp = 0; //priority + union zxdh_msg msg = {0}; + DPP_PF_INFO_T pf_info = {0}; + struct dh_core_dev *dh_dev = container_of((void*)pf_dev, struct dh_core_dev, priv); + + PLCR_FUNC_DBG_ENTER(); + PLCR_LOG_INFO("car_type = 0x%x, flowid = 0x%x, map_flowid = 0x%x\n", car_type, flowid, map_flowid); + + if (dh_dev->coredev_type == DH_COREDEV_PF) + { + //前面的流程会判断是否需要进行映射，不会出现vf端口原来是非0group，现在会被group 0覆盖的情况 + PLCR_LOG_INFO("flowid=0x%x, map_flowid=0x%x\n", flowid, map_flowid); + pf_info.slot = pf_dev->slot_id; + pf_info.vport = pf_dev->vport; + PLCR_LOG_INFO("dpp_car_queue_map_set: pf_info.vport = 0x%x, car_type = %d, flowid = %d, map_flowid = %d\n", pf_info.vport, car_type, flowid, map_flowid); + rtn = dpp_car_queue_map_set(&pf_info, car_type, flowid, map_flowid, map_sp); + PLCR_COMM_ASSERT(rtn); + + rtn = zxdh_plcr_stroe_map(pf_dev, car_type, flowid, map_flowid); + } + else + { + msg.payload.hdr.op_code = ZXDH_MAP_PLCR_FLOWID; + msg.payload.hdr.vport = pf_dev->vport; + msg.payload.hdr.pcie_id = pf_dev->pcie_id; + msg.payload.hdr.vf_id = pf_dev->pcie_id & (0xff); + + msg.payload.plcr_flowid_map_msg.car_type = car_type; + msg.payload.plcr_flowid_map_msg.flowid = flowid; + msg.payload.plcr_flowid_map_msg.map_flowid = map_flowid; + msg.payload.plcr_flowid_map_msg.sp = map_sp; + PLCR_LOG_INFO("flowid=0x%x, map_flowid=0x%x\n", flowid, map_flowid); + + rtn = zxdh_pf_msg_send_cmd(dh_dev, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg, true); + PLCR_COMM_ASSERT(rtn); + } + + return rtn; +} + +int zxdh_plcr_mode_init(struct zxdh_pf_device *pf_dev) +{ + int32_t rtn = 0; + union zxdh_msg msg = {0}; + struct dh_core_dev *dh_dev = container_of((void*)pf_dev, struct dh_core_dev, priv); + DPP_PF_INFO_T pf_info = {0}; + + pf_info.slot = pf_dev->slot_id; + pf_info.vport = pf_dev->vport; + + PLCR_FUNC_DBG_ENTER(); + + if (dh_dev->coredev_type == DH_COREDEV_PF) + { + //set mode0 + rtn = zxdh_plcr_set_mode(pf_dev, pf_dev->vport, E_RATE_LIMIT_MODE0); + PLCR_COMM_ASSERT(rtn); + } + else if (dh_dev->coredev_type == DH_COREDEV_VF) + { + msg.payload.hdr.op_code = ZXDH_PLCR_MODE_INIT; + msg.payload.hdr.vport = pf_dev->vport; + msg.payload.hdr.pcie_id = pf_dev->pcie_id; + msg.payload.hdr.vf_id = pf_dev->pcie_id & (0xff); + + rtn = zxdh_pf_msg_send_cmd(dh_dev, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg, true); + PLCR_COMM_ASSERT(rtn); + } + + return rtn; +} + +int32_t zxdh_plcr_init(struct zxdh_en_priv *en_priv) +{ + int32_t rtn = 0; + struct zxdh_en_device *en_dev = &en_priv->edev; + struct dh_core_dev *dh_dev = en_dev->parent->parent; + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + + if (dh_dev->coredev_type == DH_COREDEV_PF) + { + xa_init(&pf_dev->plcr_table.plcr_profiles[E_PLCR_CAR_A]); + xa_init(&pf_dev->plcr_table.plcr_flows[E_PLCR_CAR_A]); + xa_init(&pf_dev->plcr_table.plcr_maps[E_PLCR_CAR_A]); + + xa_init(&pf_dev->plcr_table.plcr_profiles[E_PLCR_CAR_B]); + xa_init(&pf_dev->plcr_table.plcr_flows[E_PLCR_CAR_B]); + xa_init(&pf_dev->plcr_table.plcr_maps[E_PLCR_CAR_B]); + + xa_init(&pf_dev->plcr_table.plcr_profiles[E_PLCR_CAR_C]); + xa_init(&pf_dev->plcr_table.plcr_flows[E_PLCR_CAR_C]); + + pf_dev->plcr_table.burst_size = 0; + } + + //vf需要设置到mode0模式 + rtn = zxdh_plcr_mode_init(pf_dev); + PLCR_COMM_ASSERT(rtn); + + return rtn; +} +EXPORT_SYMBOL(zxdh_plcr_init); + +/*释放PF/VF*/ +int32_t zxdh_plcr_uninit(struct zxdh_en_priv *en_priv) +{ + int rtn = 0; + union zxdh_msg msg = {0}; + struct zxdh_en_device *en_dev = &en_priv->edev; + struct dh_core_dev *dh_dev = en_dev->parent->parent; + struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev); + + unsigned long flow_id; + E_PLCR_CAR_TYPE car_index; + struct xarray *xarray_flow; + struct xarray *xarray_profile; + struct zxdh_plcr_flow *flow = NULL; + + PLCR_FUNC_DBG_ENTER(); + + if (dh_dev->coredev_type == DH_COREDEV_PF) + { + for(car_index = E_PLCR_CAR_A; car_index <= E_PLCR_CAR_C; car_index ++) + { + xarray_flow = &(pf_dev->plcr_table.plcr_flows[car_index]); + xarray_profile = &(pf_dev->plcr_table.plcr_profiles[car_index]); + xa_for_each_range(xarray_flow, flow_id, flow, 0, gaudPlcrCarxFlowIdNum[car_index]) + { + zxdh_plcr_remove_rate_limit(pf_dev, car_index, flow_id); + + //clear all vport mappings between car B and car C. + if(E_PLCR_CAR_B == car_index) + { + zxdh_plcr_clear_map(pf_dev, car_index, flow_id); + } + } + xa_destroy(xarray_flow); + xa_destroy(xarray_profile); + } + } + else if (dh_dev->coredev_type == DH_COREDEV_VF) + { + //解除一二级flowid与profile之间的绑定关系，并释放profile + msg.payload.hdr.op_code = ZXDH_PLCR_UNINIT; + msg.payload.hdr.vport = pf_dev->vport; + msg.payload.hdr.pcie_id = pf_dev->pcie_id; + msg.payload.hdr.vf_id = pf_dev->pcie_id & (0xff); + + rtn = zxdh_pf_msg_send_cmd(dh_dev, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg, true); + PLCR_COMM_ASSERT(rtn); + } + return rtn; +} +EXPORT_SYMBOL(zxdh_plcr_uninit); + + + +/*******************************下面是新实现的代码*******************************/ +/* +函数功能：获取car A的flowid +入参： + --- + --- +场景： + ---1. 如果处于mode0模式，用户请求队列字节限速，则car A的flowid就是队列 + 这种场景下，pf和vf调用各自的钩子函数，所以通过en_dev直接获取队列信息 + ---2. 如果处于mode0模式，用户请求非队列字节限速，则car A的flowid就是vf端口 + ---3. 如果处于mode1模式，则不管用户是什么请求，没有必要获取car A的flowid，因为场景1已经进行了映射 + ---4. 如果处于mode2模式，则不管用户是什么请求，没有必要获取car A的flowid，因为场景2已经进行了映射 +返回值：成功返回0，失败返回其它值 +*/ +int zxdh_plcr_get_car_a_flowid(struct zxdh_pf_device *pf_dev, E_RATE_LIMIT_MODE mode, zxdh_plcr_rate_limit_paras *rate_limit_paras, zxdh_plcr_flowids *flowids) +{ + int rtn = 0; + uint32_t queue_pair_index; + struct zxdh_en_device *en_dev; + + PLCR_FUNC_DBG_ENTER(); + + PLCR_LOG_INFO("mode = %d, rate_limit_paras->req_type = %d\n", mode, rate_limit_paras->req_type); + + en_dev = pf_dev_get_edev(pf_dev); + if (IS_ERR(en_dev)) + return PTR_ERR(en_dev); + + if (PLCR_MAX_QUEUE_PAIRS < (en_dev->curr_queue_pairs)) + { + PLCR_COMM_ASSERT(PLCR_DEV_ALL_QID_2_FLOWID_QUEUE_PAIRS_OVERFLOW); + } + + PLCR_LOG_INFO("rate_limit_paras->req_type = 0x%x\n", rate_limit_paras->req_type); + + if (E_RATE_LIMIT_REQ_VF_GROUP_BYTE == rate_limit_paras->req_type) + { + PLCR_LOG_INFO("E_RATE_LIMIT_REQ_VF_GROUP_BYTE does not need car A flowid!\n"); + return 0; + } + else if ((((E_RATE_LIMIT_MODE0 == mode)) || ((E_RATE_LIMIT_MODE1 == mode))) && (E_RATE_LIMIT_REQ_QUEUE_BYTE == rate_limit_paras->req_type)) + { + //队列字节限速调用的是pf和vf各自的钩子，所以这里直接使用en_dev->curr_queue_pairs + for (queue_pair_index=0; queue_pair_index < en_dev->curr_queue_pairs; queue_pair_index++) + { + //rx + flowids->flowids_A[0][queue_pair_index] = en_dev->rq[queue_pair_index].vq->phy_index; + + //tx + flowids->flowids_A[1][queue_pair_index] = en_dev->sq[queue_pair_index].vq->phy_index; + + PLCR_LOG_INFO("flowids->flowids_A[0][%d] = 0x%x\n", queue_pair_index, flowids->flowids_A[0][queue_pair_index]); + PLCR_LOG_INFO("flowids->flowids_A[1][%d] = 0x%x\n", queue_pair_index, flowids->flowids_A[1][queue_pair_index]); + } + flowids->queue_pairs = en_dev->curr_queue_pairs; + + PLCR_LOG_INFO("flowids->queue_pairs = 0x%x\n", flowids->queue_pairs); + } + else if (((E_RATE_LIMIT_MODE0 == mode) && (E_RATE_LIMIT_REQ_QUEUE_BYTE != rate_limit_paras->req_type)) || + ((E_RATE_LIMIT_MODE2 == mode) && (E_RATE_LIMIT_REQ_VF_PKT == rate_limit_paras->req_type))) + { + flowids->flowid_A[0] = rate_limit_paras->vfid * 2 + PLCR_CAR_A_DPDK_FLOWID_OFFSET; + flowids->flowid_A[1] = rate_limit_paras->vfid * 2 + 1 + PLCR_CAR_A_DPDK_FLOWID_OFFSET; + PLCR_LOG_INFO("flowids->flowid_A[0] = 0x%x\n", flowids->flowid_A[0]); + PLCR_LOG_INFO("flowids->flowid_A[1] = 0x%x\n", flowids->flowid_A[1]); + } + else + { + PLCR_LOG_INFO("Car A's flowid is not needed!\n"); + return 0; + } + + return rtn; +} + +int zxdh_plcr_get_car_b_flowid(struct zxdh_pf_device *pf_dev, E_RATE_LIMIT_MODE mode, zxdh_plcr_rate_limit_paras *rate_limit_paras, zxdh_plcr_flowids *flowids) +{ + int rtn = 0; + + PLCR_FUNC_DBG_ENTER(); + + //pf队列字节限速不需要指定vf_idx，视作一个特殊vf端口，同样根据vqm_vfid分配flowid + //端口组字节限速的前提是先建立端口组，在后面流程会直接退出 + flowids->flowid_B[0] = rate_limit_paras->vfid * 2; + flowids->flowid_B[1] = rate_limit_paras->vfid * 2 + 1; + + PLCR_LOG_INFO("flowids->flowid_B[0] = 0x%x\n", flowids->flowid_B[0]); + PLCR_LOG_INFO("flowids->flowid_B[1] = 0x%x\n", flowids->flowid_B[1]); + + + return rtn; +} + +/* +函数功能：获取car c的flowid +资源分配： + ---car c有1024个flowid资源 + ---4个EP * 8个PF * 2个方向（接收和发送）= 64 + ---1024 / 64 = 16，即每个pf分配16个group + +背景描述： + ---除了队列限速，其它所有限速都是操作pf下的文件系统，en_priv对应的肯定是pf设备 + ---rate_limit_paras->vport，这个指向的是vf_idx对应的vf设备 + ---所以，我们需要通过en_priv获取ep和pf func num + +返回值：成功返回0，失败返回其它值 +*/ +int zxdh_plcr_get_car_c_flowid(struct zxdh_pf_device *pf_dev, E_RATE_LIMIT_MODE mode, zxdh_plcr_rate_limit_paras *rate_limit_paras, zxdh_plcr_flowids *flowids) +{ + uint16_t vport = 0; + uint32_t epid = 0; + uint32_t pf_num = 0; + + PLCR_FUNC_DBG_ENTER(); + + vport = pf_dev->vport; + PLCR_LOG_INFO("pf's info : vport = 0x%x\n0", vport); + + if(rate_limit_paras->group_id >= 16) + { + PLCR_LOG_ERR("group_id must be less than 16!\n"); + return -ERANGE; + } + + //用户设置vf的队列限速的时候，这里的vport是vf端口，不是pf端口 + //vf的vport和pf的vport一样，都包含了相同的epid和pf function + epid = EPID(vport); + pf_num = FUNC_NUM(vport); + PLCR_LOG_INFO("pf's info : epid = 0x%x, pf_num = 0x%x\n", epid, pf_num); + + //端口组要么是0，要么是用户指定（端口组字节限速，移动端口组） + flowids->flowid_C[0] = epid * PLCR_CAR_C_FLOWIDS_PER_EP + pf_num * PLCR_CAR_C_FLOWIDS_PER_PF + rate_limit_paras->group_id * 2; + flowids->flowid_C[1] = epid * PLCR_CAR_C_FLOWIDS_PER_EP + pf_num * PLCR_CAR_C_FLOWIDS_PER_PF + rate_limit_paras->group_id * 2 + 1; + + PLCR_LOG_INFO("flowids->flowid_C[0] = 0x%x\n", flowids->flowid_C[0]); + PLCR_LOG_INFO("flowids->flowid_C[1] = 0x%x\n", flowids->flowid_C[1]); + + return 0; +} + +/* +函数功能：获取对应的Vfi +入参： + ---vf_idx : pf内vf的编号，vf_idx是查找vport的索引，是中间工具，最终使用Vfid来定位vport + ---vfid : vport的Vfid +场景： + ---1. pf队列字节限速： 用户使用echo， 调用pf的钩子函数，走if分支， 不需要指定vf_idx，不需要Vfid（不需要进行级间映射） + ---2. vf队列字节限速： 用户命令使用echo， 调用vf的否子函数，走else分支， 不需要指定vf_idx + ---3. vf端口字节限速： 用户命令使用ip link，调用pf的钩子函数，走if分支， 需要指定vf_idx + ---3. vf端口字节限速： 后期会支持echo， 调用pf的钩子函数，走if分支， 需要指定vf_idx + ---4. vf端口包限速： 用户命令使用echo， 调用pf的钩子函数，走if分支， 需要指定vf_idx + ---5. vf端口组字节限速：用户命令使用echo， 调用pf的钩子函数，走if分支， 不需要指定vf_idx，不需要Vfid（不需要进行级间映射） + ---6. vf端口移动组： 用户命令使用echo， 调用pf的钩子函数，走if分支， 需要指定vf_idx +返回值：成功返回0，失败返回其它值 +*/ +int zxdh_plcr_get_vport_vfid(struct zxdh_pf_device *pf_dev, uint32_t vf_idx, uint32_t *vport, uint32_t *vfid) +{ + int32_t rtn = 0; + struct zxdh_vf_item *vf_item; + struct dh_core_dev *dh_dev = container_of((void*)pf_dev, struct dh_core_dev, priv); + + PLCR_FUNC_DBG_ENTER(); + + if (dh_dev->coredev_type == DH_COREDEV_PF) + { + PLCR_LOG_INFO("pf: pf_dev->vport = 0x%x, pf_dev->pcie_id = 0x%x\n", pf_dev->vport, pf_dev->pcie_id); + //场景中有不需要指定vf_idx的情况，不会生成vf_id + if (PLCR_INVALID_PARAM == vf_idx) + { + //pf队列限速和vf端口组字节限速，都不需要指定vf_idx + //但vf端口组字节限速必须要用到vport, pf队列也需分配一个carb flowid + *vport = pf_dev->vport; + *vfid = VQM_VFID(pf_dev->vport); + + PLCR_LOG_INFO("vf_idx is not specified! vport = %x, vfid = %x\n", pf_dev->vport, *vfid); + return rtn; + } + else + { + vf_item = &pf_dev->vf_item[vf_idx]; + if(ERR_PTR(-EINVAL) == vf_item) + { + return -EINVAL; + } + + *vport = vf_item->vport; + *vfid = VQM_VFID(vf_item->vport); + + PLCR_LOG_INFO("vf_idx = 0x%x, vf_item->vport = 0x%x, vfid = 0x%x\n", vf_idx, vf_item->vport, *vfid); + PLCR_LOG_INFO("mac address = %x %x %x %x %x %x\n", vf_item->mac[0],vf_item->mac[1],vf_item->mac[2],vf_item->mac[3],vf_item->mac[4],vf_item->mac[5]); + } + } + else + { + PLCR_LOG_INFO("vf: pf_dev->vport = 0x%x, pf_dev->pcie_id = 0x%x\n", pf_dev->vport, pf_dev->pcie_id); + + *vport = pf_dev->vport; + *vfid = VQM_VFID(pf_dev->vport); + + PLCR_LOG_INFO("vf_idx = 0x%x, pf_dev->vport = 0x%x, vfid = 0x%x\n", vf_idx, pf_dev->vport, *vfid); + } + + return rtn; +} + +int zxdh_plcr_get_cars_flowid(struct zxdh_pf_device *pf_dev, E_RATE_LIMIT_MODE mode, zxdh_plcr_rate_limit_paras *rate_limit_paras, zxdh_plcr_flowids *flowids) +{ + int rtn = 0; + + PLCR_FUNC_DBG_ENTER(); + + //init the pointer flowids with invalid value + memset(flowids, 0xff, sizeof(zxdh_plcr_flowids)); + + //get car A flowid + rtn = zxdh_plcr_get_car_a_flowid(pf_dev, mode, rate_limit_paras, flowids); + PLCR_COMM_ASSERT(rtn); + + //get car B flowid + rtn = zxdh_plcr_get_car_b_flowid(pf_dev, mode, rate_limit_paras, flowids); + PLCR_COMM_ASSERT(rtn); + + //get car C flowid + rtn = zxdh_plcr_get_car_c_flowid(pf_dev, mode, rate_limit_paras, flowids); + PLCR_COMM_ASSERT(rtn); + + return rtn; +} + +int zxdh_plcr_get_next_mode(struct zxdh_pf_device *pf_dev, zxdh_plcr_rate_limit_paras *rate_limit_paras, uint32_t *next_mode) +{ + int rtn = 0; + E_RATE_LIMIT_MODE cur_mode; + + //get vport current mode + rtn = zxdh_plcr_get_mode(pf_dev, rate_limit_paras->vport, &cur_mode); + PLCR_COMM_ASSERT(rtn); + + if(E_RATE_LIMIT_MODE0 == cur_mode) + { + if(E_RATE_LIMIT_REQ_QUEUE_BYTE == rate_limit_paras->req_type) + { + *next_mode = E_RATE_LIMIT_MODE1; + } + else + { + *next_mode = E_RATE_LIMIT_MODE2; + } + + return 0; + } + else + { + return -EINVAL; + } + + return rtn; +} + +int zxdh_plcr_init_flow(struct zxdh_pf_device *pf_dev, E_PLCR_CAR_TYPE car_type, uint32_t flowid) +{ + int rtn = 0; + uint32_t vf_idx; + uint32_t vport; + uint32_t vfid; + uint32_t map_flowid; + union zxdh_msg msg = {0}; + DPP_PF_INFO_T pf_info = {0}; + struct dh_core_dev *dh_dev = container_of((void*)pf_dev, struct dh_core_dev, priv); + + PLCR_FUNC_DBG_ENTER(); + + if (dh_dev->coredev_type == DH_COREDEV_PF) + { + if (car_type == E_PLCR_CAR_C) + { + //对于carC flow的初始化，需检查目标group中num_vfs是否为0，确定其是否是本次移动前新建 + for (vf_idx = 0; vf_idx < pf_dev->num_vfs; vf_idx ++) + { + rtn = zxdh_plcr_get_vport_vfid(pf_dev, vf_idx, &vport, &vfid); + PLCR_COMM_ASSERT(rtn); + rtn = zxdh_plcr_get_next_map(pf_dev, E_PLCR_CAR_B, vfid * 2, &map_flowid); + PLCR_COMM_ASSERT(rtn); + if (!rtn && flowid == map_flowid) + { + PLCR_LOG_INFO("Group is currently being used by at least one VF\n"); + return 0; + } + } + } + pf_info.slot = pf_dev->slot_id; + pf_info.vport = pf_dev->vport; + PLCR_LOG_INFO("dpp_car_queue_cfg_set: vport = 0x%x, car_type = %d, flowid = %d, plcr_en = 0\n", + pf_dev->vport, car_type, flowid); + rtn = dpp_car_queue_cfg_set(&pf_info, (uint32_t)car_type, flowid, DROP_DISABLE, PLCR_DISABLE, 0); + if (rtn) + PLCR_LOG_ERR("failed to call dpp_car_queue_cfg_set()\n"); + } + else + { + //针对vf队列限速的场景 + msg.payload.hdr.op_code = ZXDH_PLCR_FLOW_INIT; + msg.payload.hdr.vport = pf_dev->vport; + msg.payload.hdr.pcie_id = pf_dev->pcie_id; + msg.payload.hdr.vf_id = pf_dev->pcie_id & (0xff); + + msg.payload.plcr_flow_init_msg.car_type = car_type; + msg.payload.plcr_flow_init_msg.flowid = flowid; + + rtn = zxdh_pf_msg_send_cmd(dh_dev, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg, true); + PLCR_COMM_ASSERT(rtn); + } + + return rtn; +} + +/* +函数功能：根据不同的场景进行三级映射，下面枚举出所有场景。 + + 原始模式 限速请求 转换模式 映射 + + mode0 队列字节限速 mode1 (car A -> car B) & (car B -> car C) + mode0 端口字节限速 mode2 (car A -> car B) & (car B -> car C) + mode0 端口包限速 mode2 (car A -> car B) & (car B -> car C) + mode0 移动组 mode2 (car A -> car B) & (car B -> car C) + + mode1 队列字节限速 mode1 不需要 + mode1 端口字节限速 mode1 不需要 + mode1 移动组 mode1 (car B -> car C) + + mode2 端口包限速 mode2 不需要 + mode2 端口字节限速 mode2 不需要 + mode2 移动组 mode2 (car B -> car C) + + x 端口组字节限速 无端口，无模式 不需要映射，直接配置限速 +*/ +int zxdh_plcr_set_cars_map(struct zxdh_pf_device *pf_dev, zxdh_plcr_rate_limit_paras *rate_limit_paras, zxdh_plcr_flowids *flowids) +{ + int rtn = 0; + uint32_t flowid; + uint32_t map_flowid; + E_RATE_LIMIT_MODE mode; + E_RATE_LIMIT_REQ_TYPE req_type; + int queue_pair_index; + + PLCR_FUNC_DBG_ENTER(); + + //get vport and vfid + rtn = zxdh_plcr_get_vport_vfid(pf_dev, rate_limit_paras->vf_idx, &rate_limit_paras->vport, &rate_limit_paras->vfid); + PLCR_COMM_ASSERT(rtn); + + //get vport current mode + rtn = zxdh_plcr_get_mode(pf_dev, rate_limit_paras->vport, &mode); + PLCR_COMM_ASSERT(rtn); + + //get rate limit type + rtn = zxdh_plcr_check_req_type(pf_dev, mode, rate_limit_paras, &req_type); + PLCR_COMM_ASSERT(rtn); + + //获取三级car的flowid + rtn = zxdh_plcr_get_cars_flowid(pf_dev, mode, rate_limit_paras, flowids); + PLCR_COMM_ASSERT(rtn); + + if (E_RATE_LIMIT_MODE0 == mode) + { + if (E_RATE_LIMIT_REQ_QUEUE_BYTE == req_type) + { + for(queue_pair_index = 0; queue_pair_index < flowids->queue_pairs; queue_pair_index++) + { + //rxq：初始化flow，避免有复位前的配置遗留，将car A flowid映射到car B flowid + flowid = flowids->flowids_A[0][queue_pair_index]; + map_flowid = flowids->flowid_B[0]; + PLCR_LOG_INFO("car_type = 0x%x, flowid = 0x%x, map_flowid = 0x%x\n", E_PLCR_CAR_A, flowid, map_flowid); + + rtn = zxdh_plcr_init_flow(pf_dev, E_PLCR_CAR_A, flowid); + PLCR_COMM_ASSERT(rtn); + rtn = zxdh_plcr_map_flowid(pf_dev, E_PLCR_CAR_A, flowid, map_flowid); + PLCR_COMM_ASSERT(rtn); + + + //txq：初始化car A flow，映射到car B flowid + flowid = flowids->flowids_A[1][queue_pair_index]; + map_flowid = flowids->flowid_B[1]; + PLCR_LOG_INFO("car_type = 0x%x, flowid = 0x%x, map_flowid = 0x%x\n", E_PLCR_CAR_A, flowid, map_flowid); + + rtn = zxdh_plcr_init_flow(pf_dev, E_PLCR_CAR_A, flowid); + PLCR_COMM_ASSERT(rtn); + rtn = zxdh_plcr_map_flowid(pf_dev, E_PLCR_CAR_A, flowid, map_flowid); + PLCR_COMM_ASSERT(rtn); + } + } + else if ((E_RATE_LIMIT_REQ_VF_PKT == req_type) || (E_RATE_LIMIT_REQ_VF_BYTE == req_type) || (E_RATE_LIMIT_REQ_MOVE_VF_GROUP == req_type)) + { + //vfid's rx ：初始化car A flow，映射到car B flowid + flowid = flowids->flowid_A[0]; + map_flowid = flowids->flowid_B[0]; + PLCR_LOG_INFO("car_type = 0x%x, flowid = 0x%x, map_flowid = 0x%x\n", E_PLCR_CAR_A, flowid, map_flowid); + + rtn = zxdh_plcr_init_flow(pf_dev, E_PLCR_CAR_A, flowid); + PLCR_COMM_ASSERT(rtn); + rtn = zxdh_plcr_map_flowid(pf_dev, E_PLCR_CAR_A, flowid, map_flowid); + PLCR_COMM_ASSERT(rtn); + + + //vfid's tx ：初始化car A flow，映射到car B flowid + flowid = flowids->flowid_A[1]; + map_flowid = flowids->flowid_B[1]; + PLCR_LOG_INFO("car_type = 0x%x, flowid = 0x%x, map_flowid = 0x%x\n", E_PLCR_CAR_A, flowid, map_flowid); + + rtn = zxdh_plcr_init_flow(pf_dev, E_PLCR_CAR_A, flowid); + PLCR_COMM_ASSERT(rtn); + rtn = zxdh_plcr_map_flowid(pf_dev, E_PLCR_CAR_A, flowid, map_flowid); + PLCR_COMM_ASSERT(rtn); + } + } + + /* + 功能：car B的flowid映射到car C的flowid + 场景： + ---1.当前mode0模式，用户请求队列字节限速， 用户未指定group：group默认为0 + ---2.当前mode0模式，用户请求vf端口字节限速，用户未指定group：group默认为0 + ---3.当前mode0模式，用户请求vf端口包限速， 用户未指定group：group默认为0 + ---4.当前mode0模式，用户请求端口组字节限速， 用户指定group：不需要car B到car C的映射，直接设置限速 + + ---5.任意模式， 用户请求移动group， 用户指定group：按照用户指定的group + ---其它场景下：不需要进行映射 + */ + if (((E_RATE_LIMIT_MODE0 == mode) && (E_RATE_LIMIT_REQ_VF_GROUP_BYTE != req_type)) || (E_RATE_LIMIT_REQ_MOVE_VF_GROUP == req_type)) + { + //car B rx flowid is mapped to car C rx flowid + flowid = flowids->flowid_B[0]; + map_flowid = flowids->flowid_C[0]; + PLCR_LOG_INFO("car_type = 0x%x, flowid = 0x%x, map_flowid = 0x%x\n", E_PLCR_CAR_B, flowid, map_flowid); + + if (E_RATE_LIMIT_MODE0 == mode) + { + rtn = zxdh_plcr_init_flow(pf_dev, E_PLCR_CAR_B, flowid); + PLCR_COMM_ASSERT(rtn); + } + rtn = zxdh_plcr_init_flow(pf_dev, E_PLCR_CAR_C, map_flowid); + PLCR_COMM_ASSERT(rtn); + + rtn = zxdh_plcr_map_flowid(pf_dev, E_PLCR_CAR_B, flowid, map_flowid); + PLCR_COMM_ASSERT(rtn); + + + //car B tx flowid is mapped to car C tx flowid + flowid = flowids->flowid_B[1]; + map_flowid = flowids->flowid_C[1]; + PLCR_LOG_INFO("car_type = 0x%x, flowid = 0x%x, map_flowid = 0x%x\n", E_PLCR_CAR_B, flowid, map_flowid); + + if (E_RATE_LIMIT_MODE0 == mode) + { + rtn = zxdh_plcr_init_flow(pf_dev, E_PLCR_CAR_B, flowid); + PLCR_COMM_ASSERT(rtn); + } + rtn = zxdh_plcr_init_flow(pf_dev, E_PLCR_CAR_C, map_flowid); + PLCR_COMM_ASSERT(rtn); + + rtn = zxdh_plcr_map_flowid(pf_dev, E_PLCR_CAR_B, flowid, map_flowid); + PLCR_COMM_ASSERT(rtn); + PLCR_LOG_INFO("Successfull to map!\n"); + } + + return rtn; +} + +int zxdh_plcr_unified_set_rate_limit(struct zxdh_pf_device *pf_dev, + zxdh_plcr_rate_limit_paras *rate_limit_paras) +{ + int rtn = 0; + union zxdh_msg msg = {0}; + zxdh_plcr_flowids flowids; + uint32_t next_mode; + E_RATE_LIMIT_REQ_TYPE req_type; + uint32_t vport = 0; + uint32_t flowid = 0; + uint32_t car_type = 0; + uint32_t is_packet = 0; + uint32_t max_rate = 0; + uint32_t min_rate = 0; + struct dh_core_dev *dh_dev = container_of((void*)pf_dev, struct dh_core_dev, priv); + + PLCR_FUNC_DBG_ENTER(); + + //map car A's flowid to car B's flowid, car B's flowid to car C's flowid + rtn = zxdh_plcr_set_cars_map(pf_dev, rate_limit_paras, &flowids); + PLCR_COMM_ASSERT(rtn); + + req_type = rate_limit_paras->req_type; + + //移动vf端口组：不需要设置限速，只需要级间映射（上面已经完成映射） + if (E_RATE_LIMIT_REQ_MOVE_VF_GROUP == req_type) + { + PLCR_LOG_INFO("E_RATE_LIMIT_REQ_MOVE_VF_GROUP does not need set rate limit!\n\n"); + + return 0; + }//队列字节限速 + else if (E_RATE_LIMIT_REQ_QUEUE_BYTE == req_type) + { + if (E_RATE_LIMIT_RX == rate_limit_paras->direction) + { + flowid = flowids.flowids_A[0][rate_limit_paras->queue_id]; + } + else + { + flowid = flowids.flowids_A[1][rate_limit_paras->queue_id]; + } + + max_rate = rate_limit_paras->max_rate; + min_rate = 0; + car_type = E_PLCR_CAR_A; + is_packet = E_RATE_LIMIT_BYTE; + }//vf端口字节限速 + else if(E_RATE_LIMIT_REQ_VF_BYTE == req_type) + { + if (E_RATE_LIMIT_RX == rate_limit_paras->direction) + { + flowid = flowids.flowid_B[0]; + } + else + { + flowid = flowids.flowid_B[1]; + } + + max_rate = rate_limit_paras->max_rate; + min_rate = rate_limit_paras->min_rate; + car_type = E_PLCR_CAR_B; + is_packet = E_RATE_LIMIT_BYTE; + }//端口组字节限速 + else if(E_RATE_LIMIT_REQ_VF_GROUP_BYTE == req_type) + { + if (E_RATE_LIMIT_RX == rate_limit_paras->direction) + { + flowid = flowids.flowid_C[0]; + } + else + { + flowid = flowids.flowid_C[1]; + } + + max_rate = rate_limit_paras->max_rate; + min_rate = 0; + car_type = E_PLCR_CAR_C; + is_packet = E_RATE_LIMIT_BYTE; + } + else + { + return -EINVAL; + } + + + PLCR_LOG_INFO("flowid = 0x%x\n", flowid); + PLCR_LOG_INFO("car_type = 0x%x\n", car_type); + PLCR_LOG_INFO("is_packet = 0x%x\n", is_packet); + PLCR_LOG_INFO("max_rate = 0x%x\n", max_rate); + PLCR_LOG_INFO("min_rate = 0x%x\n", min_rate); + + vport = rate_limit_paras->vport; + + //set rate limit + if (dh_dev->coredev_type == DH_COREDEV_PF) + { + rtn = zxdh_plcr_set_rate_limit(pf_dev, is_packet, car_type, vport, flowid, max_rate, min_rate); + } + else if (dh_dev->coredev_type == DH_COREDEV_VF) + { + msg.payload.hdr.op_code = ZXDH_VF_RATE_LIMIT_SET; + msg.payload.hdr.vport = pf_dev->vport; + msg.payload.hdr.pcie_id = pf_dev->pcie_id; + msg.payload.hdr.vf_id = pf_dev->pcie_id & (0xff); + + msg.payload.rate_limit_set_msg.flowid = flowid; + msg.payload.rate_limit_set_msg.car_type = car_type; + msg.payload.rate_limit_set_msg.is_packet = is_packet; + msg.payload.rate_limit_set_msg.max_rate = max_rate; + msg.payload.rate_limit_set_msg.min_rate = min_rate; + + PLCR_LOG_INFO("msg.payload.rate_limit_set_msg.flowid = 0x%x\n", msg.payload.rate_limit_set_msg.flowid); + PLCR_LOG_INFO("msg.payload.rate_limit_set_msg.car_type = 0x%x\n", msg.payload.rate_limit_set_msg.car_type); + PLCR_LOG_INFO("msg.payload.rate_limit_set_msg.is_packet = 0x%x\n", msg.payload.rate_limit_set_msg.is_packet); + PLCR_LOG_INFO("msg.payload.rate_limit_set_msg.max_rate = 0x%x\n", msg.payload.rate_limit_set_msg.max_rate); + PLCR_LOG_INFO("msg.payload.rate_limit_set_msg.min_rate = 0x%x\n", msg.payload.rate_limit_set_msg.min_rate); + + rtn = zxdh_pf_msg_send_cmd(dh_dev, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg, true); + PLCR_COMM_ASSERT(rtn); + + rtn = msg.reps.rate_limit_set_rsp.err_code; + } + //0：限速设置成功 + //PLCR_REMOVE_RATE_LIMIT：解除限速成功 + //其它值：错误码 + PLCR_COMM_ASSERT((0 != rtn) && (PLCR_REMOVE_RATE_LIMIT != rtn)); + + /*************下面2种场景需要模式切换************* + * 1. mode 0 -> mode 1 + * 2. mode 0 -> mode 2 + * 一般情况下，vport处于mode 1或者mode 2保持不变，只有在解除限速的时候可能会跳转到mode 0 + ****************************************/ + if (0 == rtn) //解除限速的场景就不需要进行模式切换 + { + rtn = zxdh_plcr_get_next_mode(pf_dev, rate_limit_paras, &next_mode); + if(0 == rtn) + { + rtn = zxdh_plcr_set_mode(pf_dev, vport, next_mode); + PLCR_COMM_ASSERT(rtn); + } + } + + return 0; + +} +EXPORT_SYMBOL(zxdh_plcr_unified_set_rate_limit); + diff --git a/src/net/drivers/net/ethernet/dinghai/plcr.h b/src/net/drivers/net/ethernet/dinghai/plcr.h new file mode 100644 index 0000000..981f0fa --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/plcr.h @@ -0,0 +1,359 @@ +#ifndef __ZXDH_QOS_H__ +#define __ZXDH_QOS_H__ + +#ifdef __cplusplus +extern "C" { +#endif +#include +#include +#include +#include +#include +#include "dpp_drv_qos.h" +#include "en_sf.h" + +/* 注意：启用plcr会大幅度增加初始化时间 */ +// #define ZXDH_PLCR_OPEN +// #define ZXDH_SRIOV_SYSFS_EN +#ifdef ZXDH_PLCR_OPEN + #define ZXDH_PLCR_DEBUG +#endif + +/* +注意事项：将编码过程中的约定和需要关注的点列在这里 +1. vqm tx队列与CAR A的flow id映射关系：一一映射 + vqm队列编号 0 - 4096，其中偶数队列为接收队列，奇数队列为发送队列； + 所以，队列1,3,5,7,9等就是tx队列，它们对应的flow id就是1,3,5,7,9 + 这个映射转换，对应的接口是：static int zxdh_pf_qid_2_flowid(struct zxdh_en_device *en_dev, uint32_t qid) + + +2.需要增加一个释放限速模板的接口 + 释放限速模板（模板计数操作与释放操作独立，释放的时候判断计数不为0就不释放，这样就能保证共享模板不被释放，新申请的会被释放） + +3.dpp相关的接口，里面进行pf与vf的判断 + +4.错误打印，加上行号 + +5.找孙泽明确认pcie_id和port_id的格式，参考链接： + https://i.zte.com.cn/#/space/4e62cb2b730540ff8721c1a8552b2356/wiki/page/ff8178f1304e45dc9457e92ff196cce5/view + +6. 考虑如何加锁 + +7.如果用户只指定一个速率，iplink是如何获取到另外一个速率的？ +*/ + +#define DROP_ENABLE 1 +#define DROP_DISABLE 0 +#define PLCR_ENABLE 1 +#define PLCR_DISABLE 0 + +// #define DPP_CAR_PRI_MAX +#define PLCR_STEP_SIZE 61u +#define PLCR_MIN_RATE 1u +#define PLCR_MAX_RATE 6875908u + +#define TXQ_MAX_BYTE_RATE PLCR_MAX_RATE / 1000 * PLCR_STEP_SIZE +#define TXQ_MAX_PKT_RATE 0xFFFFFFFF //todo：不确定包限速最大限速值是多少 + +#define CRED_ID(vport, car_type, profile_id) ((vport & 0xffff) << 20) | ((car_type & 0xf) << 16) | (profile_id & 0x1FF); +#define PROFILE_ID(cred_id) ((cred_id & 0x1FF)) +#define VQM_QUEUE_PAIRS_MAX_NUM 2048 + +#define PLCR_CAR_A_PROFILE_RES_NUM 512 +#define PLCR_CAR_B_PROFILE_RES_NUM 128 +#define PLCR_CAR_C_PROFILE_RES_NUM 32 + +#define PLCR_CAR_A_FLOWID_RES_NUM 10240 +#define PLCR_CAR_B_FLOWID_RES_NUM 2368 // 2304 + 64 +#define PLCR_CAR_C_FLOWID_RES_NUM 1024 +#define PLCR_CAR_B_PF_DEFAULT_FLOWID 2048 + +#define PLCR_CAR_C_FLOWIDS_PER_EP 256 +#define PLCR_CAR_C_FLOWIDS_PER_PF 32 + +//todo:实际调试时确定这个cbs的值; +#define PLCR_CAR_PROFILE_GENERAL_CBS (14*1024*4) + +/********************************** definition of types **********************************/ +#define FLOWID_2_XARRAY(flowid) ((flowid + 1)*8) +#define XARRAY_2_FLOWID(flowid) ((flowid / 8)-1) + +#define PLCR_INVALID_PARAM 0xffffffff +#define PLCR_CAR_A_DPDK_FLOWID_OFFSET 8192 +#define PLCR_MAX_QUEUE_PAIRS 64 +#define PLCR_DEBUG + +#ifdef PLCR_DEBUG +#define PLCR_FUNC_DBG_ENTER()\ + LOG_INFO("%s-%d:enter !\n", __FUNCTION__, __LINE__) + +#define PLCR_LOG_INFO(fmt, arg...)\ + LOG_INFO("%s-%d: ", __FUNCTION__, __LINE__)\ + DH_LOG_INFO(MODULE_PF, fmt, ##arg) + +#define PLCR_LOG_ERR(fmt, arg...)\ + LOG_INFO("%s-%d: ", __FUNCTION__, __LINE__)\ + DH_LOG_ERR(MODULE_PF, fmt, ##arg) + +#define PLCR_COMM_ASSERT(rtn)\ + do{\ + if(0 != rtn)\ + {\ + PLCR_LOG_ERR("failed and rtn=0x%x\n", rtn)\ + return rtn;\ + }\ + }while(0) +#else +#define PLCR_FUNC_DBG_ENTER() + +#define PLCR_LOG_INFO(fmt, arg...) + +#define PLCR_LOG_ERR(fmt, arg...)\ + LOG_INFO("%s-%d: ", __FUNCTION__, __LINE__);\ + DH_LOG_ERR(MODULE_PF, fmt, ##arg) + +#define PLCR_COMM_ASSERT(rtn)\ + do{\ + if(0 != rtn)\ + {\ + return rtn;\ + }\ + }while(0) +#endif + +typedef enum +{ + PLCR_DEV_ALL_QID_2_FLOWID_QUEUE_PAIRS_OVERFLOW = 1, + PLCR_GET_REQ_TYPE_INVALID_ERR, + + PLCR_CREATE_RATE_LIMIT_INVALID_OPERATION_ERR, + PLCR_MODIFY_RATE_LIMIT_INVALID_OPERATION_ERR, + + PLCR_REMOVE_RATE_LIMIT, + + PLCR_ERROR_NUM +} E_PLCR_ERR_CODE; + +// Define the type of PLCR card +typedef enum{ + E_PLCR_CAR_A = 0, // PLCR card type A + E_PLCR_CAR_B = 1, // PLCR card type B + E_PLCR_CAR_C = 2, // PLCR card type C + E_PLCR_CAR_NUM = 3, // Number of PLCR card types +} E_PLCR_CAR_TYPE; + +// Define the union for PLCR profile configuration +union zxdh_plcr_profile_cfg +{ + DPP_STAT_CAR_PROFILE_CFG_T byte_profile_cfg; // Byte rate limit profile configuration + DPP_STAT_CAR_PKT_PROFILE_CFG_T pkt_profile_cfg; // Packet rate limit profile configuration +}; + +typedef enum { + E_RATE_LIMIT_MODE0 = 0, // mode 0:no limit + E_RATE_LIMIT_MODE1, // mode 1:queue is mapped to car A flowid + E_RATE_LIMIT_MODE2, // mode 2:vfid is mapped to car A flowid +} E_RATE_LIMIT_MODE; + +typedef enum { + E_RATE_LIMIT_REQ_QUEUE_BYTE = 0, // queue byte rate limit + E_RATE_LIMIT_REQ_VF_BYTE, // vf byte rate limit + E_RATE_LIMIT_REQ_VF_GROUP_BYTE, // vf group byte rate limit + E_RATE_LIMIT_REQ_VF_PKT, // vf packet rate limit + E_RATE_LIMIT_REQ_MOVE_VF_GROUP, //just to move vf to other group + E_RATE_LIMIT_REQ_TYPE_NUM, // +} E_RATE_LIMIT_REQ_TYPE; + +/* Define rate limit direction */ +typedef enum { + E_RATE_LIMIT_RX = 0, // Receive direction + E_RATE_LIMIT_TX, // Send direction +} E_RATE_LIMIT_DIRECTION; + +/* Define rate limit type */ +typedef enum { + E_RATE_LIMIT_BYTE = 0, // Byte rate limit + E_RATE_LIMIT_PACKET, // Packet rate limit +} E_RATE_LIMIT_PKT_BYTE; + +/* Define the structure for rate limit parameters */ +typedef struct { + E_RATE_LIMIT_REQ_TYPE req_type; // Limit scope + E_RATE_LIMIT_DIRECTION direction; // Limit direction + E_RATE_LIMIT_PKT_BYTE mode; // Limit mode + uint32_t max_rate; // Maximum rate limit + uint32_t min_rate; // Minimum rate limit + uint32_t queue_id; // Queue id + uint32_t vf_idx; // VF index in PF + uint32_t vfid; // VF id is global + uint32_t vport; // VF id is global + uint32_t group_id; // Group id +} zxdh_plcr_rate_limit_paras; + +typedef struct { + uint16_t queue_pairs; + uint16_t flowids_A[2][PLCR_MAX_QUEUE_PAIRS]; // flowid in car A + uint16_t flowid_A[2]; // flowid in car A + uint16_t flowid_B[2]; // flowid in car B + uint16_t flowid_C[2]; // flowid in car C +} zxdh_plcr_flowids; + +// Define the structure for PLCR profile +struct zxdh_plcr_profile +{ + uint16_t ref_cnt; // Reference count + uint16_t profile_id; // Profile ID + uint16_t vport; // Virtual port + uint32_t max_rate; // Maximum rate + uint32_t min_rate; // Minimum rate + uint64_t cred_id; // Credit ID + DPP_STAT_CAR_PROFILE_CFG_T profile_cfg; // Profile configuration +}; + +// Define the structure for PLCR flow +struct zxdh_plcr_flow +{ + uint16_t vport; // Virtual port + uint16_t vf_id; // VF ID + uint16_t profile_id; // Profile ID + uint16_t flowid; // flowid + uint16_t map_flowid; // net car's flowid + uint16_t next_flowid; // next car's flowid + uint32_t max_rate; // Maximum rate + uint32_t min_rate; // Minimum rate +}; + +struct dh_core_dev; +struct zxdh_pf_device; +struct zxdh_en_priv; + +typedef enum{ + ZXDH_GROUP_RX_RATE = 0, + ZXDH_GROUP_TX_RATE = 1, +}ZXDH_GROUP_DATA_TYPE; + +struct zxdh_group_obj +{ + struct zxdh_pf_device *pf_dev; + struct kobject kobj; + struct completion free_group_comp; + + struct list_head list; + int32_t group_id; + int32_t num_vfs; + uint32_t max_tx_rate; + uint32_t max_rx_rate; +}; + +struct zxdh_group_work { + struct work_struct work; + struct zxdh_group_obj *group_obj; +}; + +typedef enum{ + ZXDH_VF_MIN_RATE = 0, + ZXDH_VF_MAX_RATE = 1, +}ZXDH_VF_METER_DATA_TYPE; + +typedef enum{ + VF_METER_RX_BPS = 0, + VF_METER_RX_PPS = 1, + VF_METER_TX_BPS = 2, + VF_METER_TX_PPS = 3, + VF_METER_TYPE_NUM, +}ZXDH_VF_METER_TYPE; + +#define IS_TX_METER(meter_type) (meter_type == VF_METER_TX_BPS || meter_type == VF_METER_TX_PPS) +#define IS_PPS_METER(meter_type) (meter_type == VF_METER_RX_PPS || meter_type == VF_METER_TX_PPS) + +struct zxdh_vf_meter_obj +{ + struct zxdh_pf_device *pf_dev; + struct zxdh_vf_obj *vf_obj; + struct kobject kobj; + uint32_t meter_type; + uint32_t min_rate; + uint32_t max_rate; +}; + +struct zxdh_vf_meters +{ + struct kobject *kobj; + struct kobject *rx_obj; + struct kobject *tx_obj; + struct zxdh_vf_meter_obj xps[4]; +}; + +struct zxdh_vf_obj +{ + struct zxdh_pf_device *pf_dev; + struct kobject kobj; + uint16_t vport; + uint16_t vf_idx; + struct zxdh_group_obj *group; + struct zxdh_vf_meters *meters; +}; + +struct zxdh_sriov_sysfs +{ + struct kobject *sriov_obj; +#ifdef ZXDH_PLCR_DEBUG + struct kobj_attribute burst_attr; + struct kobj_attribute profile_attr; +#endif + struct kobject *groups_obj; + struct zxdh_group_obj *group_0; + struct list_head groups_head; + struct zxdh_vf_obj *vfs; +}; + +struct zxdh_plcr_table { + struct xarray plcr_profiles[E_PLCR_CAR_NUM]; // Array of PLCR profiles(index = prfile id) + struct xarray plcr_flows[E_PLCR_CAR_NUM]; // Array of PLCR flows(index = flowid) + struct xarray plcr_maps[E_PLCR_CAR_NUM]; // Array of PLCR flows mapping relationship + uint32_t burst_size; +}; + +struct zxdh_plcr_cbs +{ + uint32_t min_rate; + uint32_t max_rate; + uint32_t cbs; +}; +extern const uint32_t gaudPlcrCarxProfileNum[E_PLCR_CAR_NUM]; +extern const uint32_t gaudPlcrCarxFlowIdNum[E_PLCR_CAR_NUM]; +int zxdh_plcr_remove_rate_limit(struct zxdh_pf_device *pf_dev, E_PLCR_CAR_TYPE car_type, uint32_t flowid); +void zxdh_plcr_count_profiles(struct zxdh_pf_device *pf_dev); +int zxdh_plcr_set_rate_limit(struct zxdh_pf_device *pf_dev, E_RATE_LIMIT_PKT_BYTE is_pkt_mode, E_PLCR_CAR_TYPE car_type, uint16_t vport, uint32_t flowid, uint32_t max_rate, uint32_t min_rate); +int32_t zxdh_plcr_get_next_map(struct zxdh_pf_device *pf_dev, E_PLCR_CAR_TYPE car_type, uint32_t flowid, uint32_t *map_flowid); +int32_t zxdh_plcr_init(struct zxdh_en_priv *en_priv); +int32_t zxdh_plcr_uninit(struct zxdh_en_priv *en_priv); +int zxdh_plcr_get_vport_vfid(struct zxdh_pf_device *pf_dev, uint32_t vf_idx, uint32_t *vport, uint32_t *vfid); +int zxdh_plcr_req_profile(struct zxdh_pf_device *pf_dev, E_PLCR_CAR_TYPE car_type, uint16_t *profile_id_out); +int zxdh_plcr_release_profile(struct zxdh_pf_device *pf_dev, E_PLCR_CAR_TYPE car_type, uint16_t profile_id); +int zxdh_plcr_count_up_profile(struct zxdh_pf_device *pf_dev, E_PLCR_CAR_TYPE car_type, uint16_t profile_id); +int zxdh_plcr_count_down_profile(struct zxdh_pf_device *pf_dev, E_PLCR_CAR_TYPE car_type, uint16_t profile_id); +int zxdh_plcr_cfg_profile(struct zxdh_pf_device *pf_dev, E_PLCR_CAR_TYPE car_type, DPP_STAT_CAR_PROFILE_CFG_T *profile_cfg); +int zxdh_plcr_get_profile(struct zxdh_pf_device *pf_dev, E_PLCR_CAR_TYPE car_type, uint32_t pkt_sign, uint16_t profile_id, DPP_STAT_CAR_PROFILE_CFG_T *profile_cfg); +uint32_t zxdh_plcr_reg_maxrate_user(uint32_t reg_maxrate); +int32_t zxdh_plcr_req_flow(struct zxdh_pf_device *pf_dev, E_PLCR_CAR_TYPE car_type, uint16_t flow_id, struct zxdh_plcr_flow **flow); +int32_t zxdh_plcr_release_flow(struct zxdh_pf_device *pf_dev, E_PLCR_CAR_TYPE car_type, uint16_t flow_id); +void zxdh_plcr_update_flow(struct zxdh_plcr_flow *flow, uint16_t vport, uint32_t max_rate, uint32_t min_rate); +int zxdh_plcr_store_profile(struct zxdh_pf_device *pf_dev, E_PLCR_CAR_TYPE car_type, uint32_t user_max_rate, uint32_t user_min_rate, DPP_STAT_CAR_PROFILE_CFG_T *profile_cfg); +int32_t zxdh_plcr_stroe_map(struct zxdh_pf_device *pf_dev, E_PLCR_CAR_TYPE car_type, uint32_t flowid, uint32_t map_flowid); +int32_t zxdh_plcr_clear_map(struct zxdh_pf_device *pf_dev, E_PLCR_CAR_TYPE car_type, uint32_t flowid); +int zxdh_plcr_get_mode(struct zxdh_pf_device *pf_dev, uint16_t vport, E_RATE_LIMIT_MODE *mode); +int zxdh_plcr_set_mode(struct zxdh_pf_device *pf_dev, uint16_t vport, E_RATE_LIMIT_MODE mode); +int zxdh_plcr_unified_set_rate_limit(struct zxdh_pf_device *pf_dev, zxdh_plcr_rate_limit_paras *rate_limit_paras); + +int zxdh_vf_update_sysfs_group(struct zxdh_pf_device *pf_dev, struct zxdh_vf_obj *vf, int32_t group_id); +int zxdh_create_vfs_sysfs(struct dh_core_dev *dev, int32_t num_vfs); +void zxdh_destroy_vfs_sysfs(struct dh_core_dev *dev, int32_t num_vfs); +int zxdh_sriov_sysfs_init(struct dh_core_dev *dev); +void zxdh_sriov_sysfs_exit(struct dh_core_dev *dev); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/sriov_sysfs.c b/src/net/drivers/net/ethernet/dinghai/sriov_sysfs.c new file mode 100644 index 0000000..9c34f26 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/sriov_sysfs.c @@ -0,0 +1,1483 @@ +#include +#include +#include +#include +#include +#include "en_aux.h" +#include +#include "en_np/table/include/dpp_tbl_api.h" +#include "en_aux/en_cmd.h" +#include "msg_common.h" +#include "en_pf.h" +#include +#ifdef TIME_STAMP_1588 +#include "en_aux/en_1588_pkt_proc.h" +#endif +#include +#include +#include +#include +#include +#include + + +#define ZXDH_DEFAULT_VF_GROUP_ID 0 +#define ZXDH_MAX_VF_GROUP_OBJ_ID 255 +#define ZXDH_MAX_VF_GROUP_OBJ_NUM (ZXDH_MAX_VF_GROUP_OBJ_ID + 1) +#define ZXDH_MAX_VF_OBJ_ID 255 +#define ZXDH_MAX_VF_OBJ_NUM (ZXDH_MAX_VF_OBJ_ID + 1) + + +/************************************************ + * sriov attr： + * burst: WO，配置当前PF的流量突发尺寸 + * profile: RO，打印当前PF对三级car的profile占用情况 +************************************************/ + + +/************************************************ + * group attr： + * config: RO，打印当前vf端口组所有配置 + * max_rx_rate: WO，配置当前vf端口组最大接收速率 + * max_tx_rate: WO，配置当前vf端口组最大发送速率 +************************************************/ + + +/************************************************ + * vf attr： + * config: RO，打印当前vf所有配置 + * group: WO，指定当前vf端口所属group，默认group-0 + * meter + * rx + * bps + * max_rate: WO，配置当前vf端口接收方向字节限速 + * min_rate: WO，配置当前vf端口接收方向字节最小保障带宽 + * pkt_dropped: RO, 查询丢包数量/字节数 + * pps + * rate: WO，配置当前vf端口接收方向包限速 + * pkt_dropped: RO, 查询丢包数量/字节数 + * tx + * bps + * max_rate: WO，配置当前vf端口发送方向字节限速 + * max_rate: WO，配置当前vf端口发送方向字节最小保障带宽 + * pkt_dropped: RO, 查询丢包数量/字节数 + + * pps + * pps_rate: WO，配置当前vf端口发送方向包限速 + * pkt_dropped: RO, 查询丢包数量/字节数 +************************************************/ + + +struct zxdh_group_attribute { + struct attribute attr; + ssize_t (*show)(struct zxdh_group_obj *group, + struct zxdh_group_attribute *attr, char *buf); + ssize_t (*store)(struct zxdh_group_obj *group, + struct zxdh_group_attribute *attr, const char *buf, size_t count); +}; + +#define to_zxdh_group_attr(x) container_of(x, struct zxdh_group_attribute, attr) +#define to_zxdh_group_obj(x) container_of(x, struct zxdh_group_obj, kobj) + +struct zxdh_vf_attribute { + struct attribute attr; + ssize_t (*show)(struct zxdh_vf_obj *vf, + struct zxdh_vf_attribute *attr, char *buf); + ssize_t (*store)(struct zxdh_vf_obj *vf, + struct zxdh_vf_attribute *attr, const char *buf, size_t count); +}; + +#define to_zxdh_vf_attr(x) container_of(x, struct zxdh_vf_attribute, attr) +#define to_zxdh_vf_obj(x) container_of(x, struct zxdh_vf_obj, kobj) + +struct zxdh_vf_meter_attribute { + struct attribute attr; + ssize_t (*show)(struct zxdh_vf_meter_obj *xps, + struct zxdh_vf_meter_attribute *attr, char *buf); + ssize_t (*store)(struct zxdh_vf_meter_obj *xps, + struct zxdh_vf_meter_attribute *attr, const char *buf, size_t count); +}; + +#define to_zxdh_vf_meter_attr(x) container_of(x, struct zxdh_vf_meter_attribute, attr) +#define to_zxdh_vf_meter_obj(x) container_of(x, struct zxdh_vf_meter_obj, kobj) + +/* + * The default show function that must be passed to sysfs. This will be + * called by sysfs for whenever a show function is called by the user on a + * sysfs file associated with the kobjects we have registered. We need to + * transpose back from a "default" kobject to our custom struct foo_obj and + * then call the show function for that specific object. + */ +static ssize_t zxdh_group_attr_show(struct kobject *kobj, + struct attribute *attr, + char *buf) +{ + struct zxdh_group_attribute *attribute; + struct zxdh_group_obj *group; + + attribute = to_zxdh_group_attr(attr); + group = to_zxdh_group_obj(kobj); + + if (!attribute->show) + return -EIO; + + return attribute->show(group, attribute, buf); +} + +/* + * Just like the default show function above, but this one is for when the + * sysfs "store" is requested (when a value is written to a file.) + */ +static ssize_t zxdh_group_attr_store(struct kobject *kobj, + struct attribute *attr, + const char *buf, size_t len) +{ + struct zxdh_group_attribute *attribute; + struct zxdh_group_obj *group; + + attribute = to_zxdh_group_attr(attr); + group = to_zxdh_group_obj(kobj); + + if (!attribute->store) + return -EIO; + + return attribute->store(group, attribute, buf, len); +} + +static ssize_t zxdh_vf_attr_show(struct kobject *kobj, + struct attribute *attr, + char *buf) +{ + struct zxdh_vf_attribute *attribute; + struct zxdh_vf_obj *vf; + + attribute = to_zxdh_vf_attr(attr); + vf = to_zxdh_vf_obj(kobj); + + if (!attribute->show) + return -EIO; + + return attribute->show(vf, attribute, buf); +} + +static ssize_t zxdh_vf_attr_store(struct kobject *kobj, + struct attribute *attr, + const char *buf, size_t len) +{ + struct zxdh_vf_attribute *attribute; + struct zxdh_vf_obj *vf; + + attribute = to_zxdh_vf_attr(attr); + vf = to_zxdh_vf_obj(kobj); + + if (!attribute->store) + return -EIO; + + return attribute->store(vf, attribute, buf, len); +} + +static ssize_t zxdh_vf_meter_attr_show(struct kobject *kobj, + struct attribute *attr, + char *buf) +{ + struct zxdh_vf_meter_attribute *attribute; + struct zxdh_vf_meter_obj *xps; + + attribute = to_zxdh_vf_meter_attr(attr); + xps = to_zxdh_vf_meter_obj(kobj); + + if (!attribute->show) + return -EIO; + + return attribute->show(xps, attribute, buf); +} + +static ssize_t zxdh_vf_meter_attr_store(struct kobject *kobj, + struct attribute *attr, + const char *buf, size_t len) +{ + struct zxdh_vf_meter_attribute *attribute; + struct zxdh_vf_meter_obj *xps; + + attribute = to_zxdh_vf_meter_attr(attr); + xps = to_zxdh_vf_meter_obj(kobj); + + if (!attribute->store) + return -EIO; + + return attribute->store(xps, attribute, buf, len); +} + +/* Our custom sysfs_ops that we will associate with our ktype later on */ +static const struct sysfs_ops zxdh_group_sysfs_ops = { + .show = zxdh_group_attr_show, + .store = zxdh_group_attr_store, +}; + +static const struct sysfs_ops zxdh_vf_sysfs_ops = { + .show = zxdh_vf_attr_show, + .store = zxdh_vf_attr_store, +}; + +static const struct sysfs_ops zxdh_vf_meter_sysfs_ops = { + .show = zxdh_vf_meter_attr_show, + .store = zxdh_vf_meter_attr_store, +}; + +/* + * The release function for our object. This is REQUIRED by the kernel to + * have. We free the memory held in our object here. + * + * NEVER try to get away with just a "blank" release function to try to be + * smarter than the kernel. Turns out, no one ever is... + */ +/*static void zxdh_group_release(struct kobject *kobj) +{ + struct zxdh_group_obj *group; + + LOG_INFO("enter\n"); + group = to_zxdh_group_obj(kobj); + kfree(group); +} + +static void zxdh_vf_release(struct kobject *kobj) +{ + struct zxdh_vf_obj *vf; + + LOG_INFO("enter\n"); + vf = to_zxdh_vf_obj(kobj); + kfree(vf); +} + +static void zxdh_vf_meter_release(struct kobject *kobj) +{ + struct zxdh_vf_meter_obj *xps; + + LOG_INFO("enter\n"); + xps = to_zxdh_vf_meter_obj(kobj); + kfree(xps); +}*/ + +#define _sprintf(p, buf, format, arg...) \ + ((PAGE_SIZE - (int)(p - buf)) <= 0 ? 0 : \ + scnprintf(p, PAGE_SIZE - (int)(p - buf), format, ## arg)) + +#ifdef ZXDH_PLCR_DEBUG +static ssize_t zxdh_burst_show(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + struct zxdh_pf_device *pf_dev; + struct zxdh_sriov_sysfs *sriov; + + LOG_INFO("enter\n"); + sriov = container_of(attr, struct zxdh_sriov_sysfs, burst_attr); + pf_dev = container_of(sriov, struct zxdh_pf_device, sriov); + + return sysfs_emit(buf, + "the burst size = %d\n", pf_dev->plcr_table.burst_size); +} + +static ssize_t zxdh_burst_store(struct kobject *kobj, + struct kobj_attribute *attr, const char *buf, size_t count) +{ + int rtn = 0; + uint32_t burst; + struct zxdh_pf_device *pf_dev; + struct zxdh_sriov_sysfs *sriov; + + LOG_INFO("enter\n"); + sriov = container_of(attr, struct zxdh_sriov_sysfs, burst_attr); + pf_dev = container_of(sriov, struct zxdh_pf_device, sriov); + + rtn = kstrtoint(buf, 10, &burst); + if (rtn) + return rtn; + + /* When the burst changes, the rate limit of the specified flow needs + to be reconfigured to update its burst. + The scope of the burst includes the current PF and its associated VFs. + Write 0 to set the burst to the default value.*/ + + pf_dev->plcr_table.burst_size = burst; + + return count; +} + +static ssize_t zxdh_profile_stat_show(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + struct zxdh_sriov_sysfs *sriov = container_of(attr, struct zxdh_sriov_sysfs, profile_attr); + struct zxdh_pf_device *pf_dev = container_of(sriov, struct zxdh_pf_device, sriov); + struct zxdh_plcr_profile *profile; + unsigned long index; + uint32_t count = 0; + E_PLCR_CAR_TYPE car_type; + char *p = buf; + + LOG_INFO("enter\n"); + for (car_type = E_PLCR_CAR_A; car_type < E_PLCR_CAR_NUM; car_type ++) + { + count = 0; + xa_for_each_range(&(pf_dev->plcr_table.plcr_profiles[car_type]), index, + profile, 0, gaudPlcrCarxProfileNum[car_type]) + { + count++; + } + p += _sprintf(p, buf, "car_type = %d, profiles_num = %d\n", car_type, count); + } + return (ssize_t)(p - buf); +} +#endif + +#ifdef ZXDH_PLCR_OPEN +static uint16_t zxdh_group_to_flowid(struct zxdh_group_obj *group, int32_t data_type) +{ + uint16_t flowid; + uint16_t vport = group->pf_dev->vport; + int32_t group_id = group->group_id; + int32_t global_group_id; + + global_group_id = EPID(vport) * 128 + FUNC_NUM(vport) * 16 + group_id; + flowid = (data_type == ZXDH_GROUP_TX_RATE) ? + (global_group_id * 2 + 1) : (global_group_id * 2); + + return flowid; +} + +static uint16_t zxdh_vport_to_flowid(uint16_t vport, int32_t req_type, int32_t direction) +{ + uint16_t vfid; + uint16_t flowid; + + LOG_INFO("enter\n"); + vfid = VQM_VFID(vport); + if (req_type == E_RATE_LIMIT_BYTE) + { + flowid = direction ? (vfid * 2 + 1) : (vfid * 2); + } + else if (req_type == E_RATE_LIMIT_PACKET) + { + flowid = direction ? (vfid * 2 + 1) : (vfid * 2) + PLCR_CAR_A_DPDK_FLOWID_OFFSET; + } + + return flowid; +} + +static uint32_t zxdh_vf_meter_obj_to_flowid(struct zxdh_vf_meter_obj *xps) +{ + uint16_t vport; + uint16_t vfid; + uint16_t flowid; + + LOG_INFO("enter\n"); + vport = xps->vf_obj->vport; + vfid = VQM_VFID(vport); + flowid = IS_TX_METER(xps->meter_type) ? (vfid * 2 + 1) : (vfid * 2); + + return flowid; +} + +static int zxdh_set_vf_group_rate_limit(struct zxdh_group_obj *group, int32_t direction, uint32_t max_rate) +{ + int rtn = 0; + zxdh_plcr_rate_limit_paras rate_limit_paras; + + LOG_INFO("enter\n"); + + // en_priv = pf_dev_get_en_priv(group->pf_dev); + // if (IS_ERR(en_priv)) + // return PTR_ERR(en_priv); + + rate_limit_paras.req_type = E_RATE_LIMIT_REQ_VF_GROUP_BYTE; + rate_limit_paras.direction = direction; // rx:0, tx:1 + rate_limit_paras.mode = E_RATE_LIMIT_BYTE; + rate_limit_paras.max_rate = max_rate; + rate_limit_paras.min_rate = PLCR_INVALID_PARAM; + + rate_limit_paras.queue_id = PLCR_INVALID_PARAM; + rate_limit_paras.vf_idx = PLCR_INVALID_PARAM; + rate_limit_paras.vfid = PLCR_INVALID_PARAM; + rate_limit_paras.group_id = group->group_id; + + rtn = zxdh_plcr_unified_set_rate_limit(group->pf_dev, &rate_limit_paras); + PLCR_COMM_ASSERT(rtn); + + return rtn; +} + +static int zxdh_move_vf_to_group(struct zxdh_vf_obj *vf, struct zxdh_group_obj *group) +{ + int rtn = 0; + zxdh_plcr_rate_limit_paras rate_limit_paras; + + LOG_INFO("enter\n"); + rate_limit_paras.req_type = E_RATE_LIMIT_REQ_MOVE_VF_GROUP; + rate_limit_paras.direction = E_RATE_LIMIT_RX; + rate_limit_paras.mode = PLCR_INVALID_PARAM; + rate_limit_paras.max_rate = PLCR_INVALID_PARAM; + rate_limit_paras.min_rate = PLCR_INVALID_PARAM; + + rate_limit_paras.queue_id = PLCR_INVALID_PARAM; + rate_limit_paras.vf_idx = vf->vf_idx; + rate_limit_paras.vfid = PLCR_INVALID_PARAM; + rate_limit_paras.group_id = group->group_id; + + rtn = zxdh_plcr_unified_set_rate_limit(vf->pf_dev, &rate_limit_paras); + PLCR_COMM_ASSERT(rtn); + + rate_limit_paras.direction = E_RATE_LIMIT_TX; + rtn = zxdh_plcr_unified_set_rate_limit(vf->pf_dev, &rate_limit_paras); + PLCR_COMM_ASSERT(rtn); + // todo:由plcr代码处理 + // if (rtn) + // { + // PLCR_LOG_ERR("failed and rtn=0x%x\n", rtn) + + // rate_limit_paras.direction = E_RATE_LIMIT_RX; + // rate_limit_paras.group_id = vf->group->group_id; + // zxdh_plcr_unified_set_rate_limit(vf->pf_dev, &rate_limit_paras); + // } + + return rtn; +} +#endif + +static ssize_t zxdh_group_max_rate_store(struct zxdh_group_obj *group, + struct zxdh_group_attribute *attr, const char *buf, + size_t count, int32_t direction) +{ + int32_t max_rate; + // uint16_t flowid; + int rtn = 0; + LOG_INFO("enter\n"); + + if (group == group->pf_dev->sriov.group_0) + return -EINVAL; + + rtn = kstrtoint(buf, 10, &max_rate); + if (rtn < 0) + return -EINVAL; + LOG_INFO("max_%s_rate = %d\n", direction ? "tx" : "rx", max_rate); + + if ((direction ? group->max_tx_rate : group->max_rx_rate) == max_rate) + return -EINVAL; + + // flowid = zxdh_group_to_flowid(group, direction); + +#ifdef ZXDH_PLCR_OPEN + //调用限速统一接口，配置vf group限速 + rtn = zxdh_set_vf_group_rate_limit(group, direction, max_rate); + if (rtn) + return rtn; + + PLCR_LOG_INFO("The Max %s Rate of group%d has been set to %d Mbit/s\n", + direction ? "Tx" : "Rx", group->group_id, max_rate); +#endif + + if (direction == ZXDH_GROUP_TX_RATE) + group->max_tx_rate = max_rate; + else + group->max_rx_rate = max_rate; + + return rtn ? rtn : count; +} + +static ssize_t zxdh_group_max_rx_rate_show(struct zxdh_group_obj *group, + struct zxdh_group_attribute *attr, char *buf) +{ + + LOG_INFO("enter\n"); + return sysfs_emit(buf, + "usage: write to set VF group max rx rate\n"); +} + +static ssize_t zxdh_group_max_rx_rate_store(struct zxdh_group_obj *group, + struct zxdh_group_attribute *attr, const char *buf, size_t count) +{ + return zxdh_group_max_rate_store(group, attr, buf, count, ZXDH_GROUP_RX_RATE); +} + +/* + * The "max_tx_rate" file where the .max_tx_rate variable is read from and written to. + */ +static ssize_t zxdh_group_max_tx_rate_show(struct zxdh_group_obj *group, + struct zxdh_group_attribute *attr, char *buf) +{ + + LOG_INFO("enter\n"); + return sysfs_emit(buf, + "usage: write to set VF group max tx rate\n"); +} + +static ssize_t zxdh_group_max_tx_rate_store(struct zxdh_group_obj *group, + struct zxdh_group_attribute *attr, const char *buf, size_t count) +{ + return zxdh_group_max_rate_store(group, attr, buf, count, ZXDH_GROUP_TX_RATE); +} + +static ssize_t zxdh_group_config_show(struct zxdh_group_obj *group, + struct zxdh_group_attribute *attr, char *buf) +{ + //打印当前group配置信息 + char *p = buf; + uint16_t vf_idx; + int32_t num_vfs = group->pf_dev->num_vfs; + struct zxdh_vf_obj *vf; + + LOG_INFO("enter\n"); + // if (!mutex_trylock(&esw->state_lock)) + // return -EBUSY; + + p += _sprintf(p, buf, "GroupID : %d\n", group->group_id); + p += _sprintf(p, buf, "Num VFs : %d\n", group->num_vfs); + p += _sprintf(p, buf, "MaxTxRate : %d\n", group->max_tx_rate); + p += _sprintf(p, buf, "MaxRxRate : %d\n", group->max_rx_rate); + + if (group->num_vfs) + { + p += _sprintf(p, buf, "VFs : "); + for (vf_idx = 0; vf_idx < num_vfs; vf_idx ++) + { + vf = group->pf_dev->sriov.vfs + vf_idx; + if (vf->group == group) + p += _sprintf(p, buf, "VF%d ", vf_idx); + } + p += _sprintf(p, buf, "\n"); + } + + // mutex_unlock(&esw->state_lock); + + return (ssize_t)(p - buf); +} + +static ssize_t zxdh_group_config_store(struct zxdh_group_obj *group, + struct zxdh_group_attribute *attr, const char *buf, size_t count) +{ + LOG_INFO("enter\n"); + return -ENOTSUPP; +} + +static ssize_t zxdh_vf_config_show(struct zxdh_vf_obj *vf, + struct zxdh_vf_attribute *attr, char *buf) +{ + //打印当前vf配置信息 +#ifdef ZXDH_PLCR_OPEN + struct zxdh_pf_device *pf_dev = vf->pf_dev; + struct xarray *xa_bps_flow, *xa_pps_flow; + struct zxdh_plcr_flow *flow_bps_rx, *flow_bps_tx, *flow_pps_rx, *flow_pps_tx; + uint32_t id_bps_rx, id_bps_tx, id_pps_rx, id_pps_tx; + E_RATE_LIMIT_MODE mode; +#endif + char *p = buf; + + LOG_INFO("enter\n"); + // mutex_lock(&esw->state_lock); + +#ifdef ZXDH_PLCR_OPEN + xa_bps_flow = &(pf_dev->plcr_table.plcr_flows[E_PLCR_CAR_B]); + zxdh_plcr_get_mode(pf_dev, vf->vport, &mode); + + id_bps_rx = zxdh_vport_to_flowid(vf->vport, E_RATE_LIMIT_BYTE, E_RATE_LIMIT_RX); + id_bps_tx = zxdh_vport_to_flowid(vf->vport, E_RATE_LIMIT_BYTE, E_RATE_LIMIT_TX); + flow_bps_rx = xa_load(xa_bps_flow, id_bps_rx); + flow_bps_tx = xa_load(xa_bps_flow, id_bps_tx); +#endif + + p += _sprintf(p, buf, "VF : VF%d\n", vf->vf_idx); + p += _sprintf(p, buf, "RateGroup : %d\n", vf->group->group_id); +#ifdef ZXDH_PLCR_OPEN + p += _sprintf(p, buf, "VportQosMode: %d\n", mode); + + if (flow_bps_rx) + { + p += _sprintf(p, buf, "MinRxRate : %dMbit/s\n", flow_bps_rx->min_rate); + p += _sprintf(p, buf, "MaxRxRate : %dMbit/s\n", flow_bps_rx->max_rate); + } + + if (flow_bps_tx) + { + p += _sprintf(p, buf, "MinTxRate : %dMbit/s\n", flow_bps_tx->min_rate); + p += _sprintf(p, buf, "MaxTxRate : %dMbit/s\n", flow_bps_tx->max_rate); + } + // if (mode == E_RATE_LIMIT_MODE0) + // { + + // } + // else if (mode == E_RATE_LIMIT_MODE1) + // { + + // } + if (mode == E_RATE_LIMIT_MODE2) + { + xa_pps_flow = &(pf_dev->plcr_table.plcr_flows[E_PLCR_CAR_A]); + id_pps_rx = zxdh_vport_to_flowid(vf->vport, E_RATE_LIMIT_PACKET, E_RATE_LIMIT_RX); + id_pps_tx = zxdh_vport_to_flowid(vf->vport, E_RATE_LIMIT_PACKET, E_RATE_LIMIT_TX); + flow_pps_rx = xa_load(xa_pps_flow, id_pps_rx); + flow_pps_tx = xa_load(xa_pps_flow, id_pps_tx); + + if (flow_pps_rx) + p += _sprintf(p, buf, "MaxRxRate : %dPackets/s\n", flow_pps_rx->max_rate); + + if (flow_pps_tx) + p += _sprintf(p, buf, "MaxTxRate : %dPackets/s\n", flow_pps_tx->min_rate); + } + +#endif + + // mutex_unlock(&esw->state_lock); + + return (ssize_t)(p - buf); +} + +static ssize_t zxdh_vf_config_store(struct zxdh_vf_obj *vf, + struct zxdh_vf_attribute *attr, const char *buf, size_t count) +{ + LOG_INFO("enter\n"); + return -ENOTSUPP; +} + +static ssize_t zxdh_vf_group_show(struct zxdh_vf_obj *vf, + struct zxdh_vf_attribute *attr, char *buf) +{ + LOG_INFO("enter\n"); + + return sysfs_emit(buf, + "usage: write <0-%d> to set VF vport group\n", ZXDH_MAX_VF_GROUP_OBJ_ID); +} + +static ssize_t zxdh_vf_group_store(struct zxdh_vf_obj *vf, + struct zxdh_vf_attribute *attr, const char *buf, size_t count) +{ + int32_t group_id; + int rtn = 0; + LOG_INFO("enter\n"); + + rtn = kstrtoint(buf, 10, &group_id); + if (rtn < 0) + return -EINVAL; + LOG_INFO("group = %d\n", group_id); + + rtn = zxdh_vf_update_sysfs_group(vf->pf_dev, vf, group_id); + if (rtn) + { + LOG_ERR("zxdh_vf_update_sysfs_group failed\n"); + return rtn; + } + + PLCR_LOG_INFO("VF%d has been moved to group%d\n", vf-> vf_idx, group_id); + + return count; +} + +static ssize_t zxdh_vf_meter_rate_store(struct zxdh_vf_meter_obj *xps, + struct zxdh_vf_meter_attribute *attr, const char *buf, + size_t count, int32_t data_type) +{ +#ifdef ZXDH_PLCR_OPEN + struct zxdh_pf_device *pf_dev = xps->pf_dev; + struct xarray *xarray_flowid = &(pf_dev->plcr_table.plcr_flows[E_PLCR_CAR_B]); + struct zxdh_plcr_flow *plcr_flow; + zxdh_plcr_rate_limit_paras rate_limit_paras; + uint32_t flowid; + uint16_t vport; + const char *direction; +#endif + int32_t data; + int rtn = 0; + + LOG_INFO("enter\n"); + rtn = kstrtoint(buf, 10, &data); + if (rtn < 0) + return -EINVAL; + +#ifdef ZXDH_PLCR_OPEN + vport = xps->vf_obj->vport; + flowid = zxdh_vf_meter_obj_to_flowid(xps); + plcr_flow = xa_load(xarray_flowid, flowid); + + //调用限速统一接口，配置vf限速 + if (IS_PPS_METER(xps->meter_type)) + { + LOG_INFO("max_rate = %d Packets/s\n", data); + rate_limit_paras.req_type = E_RATE_LIMIT_REQ_VF_PKT; + rate_limit_paras.mode = E_RATE_LIMIT_PACKET; + rate_limit_paras.min_rate = 0; + rate_limit_paras.max_rate = data; + } + else + { + rate_limit_paras.req_type = E_RATE_LIMIT_REQ_VF_BYTE; + rate_limit_paras.mode = E_RATE_LIMIT_BYTE; + + if (data_type == ZXDH_VF_MIN_RATE) + { + LOG_INFO("min_rate = %d Mbit/s\n", data); + rate_limit_paras.min_rate = data; + if (plcr_flow) + rate_limit_paras.max_rate = plcr_flow->max_rate; + else + rate_limit_paras.max_rate = data; + } + else if (data_type == ZXDH_VF_MAX_RATE) + { + LOG_INFO("max_rate = %d Mbit/s\n", data); + if (plcr_flow) + rate_limit_paras.min_rate = plcr_flow->min_rate; + else + rate_limit_paras.min_rate = 0; + rate_limit_paras.max_rate = data; + } + else + return -EINVAL; + + if (rate_limit_paras.max_rate < rate_limit_paras.min_rate) + rate_limit_paras.max_rate = rate_limit_paras.min_rate; + } + + rate_limit_paras.direction = IS_TX_METER(xps->meter_type) ? E_RATE_LIMIT_TX : E_RATE_LIMIT_RX; + rate_limit_paras.queue_id = PLCR_INVALID_PARAM; + rate_limit_paras.vf_idx = xps->vf_obj->vf_idx; + rate_limit_paras.vfid = PLCR_INVALID_PARAM; + rate_limit_paras.group_id = PLCR_INVALID_PARAM; + + rtn = zxdh_plcr_unified_set_rate_limit(pf_dev, &rate_limit_paras); + PLCR_COMM_ASSERT(rtn); + + direction = IS_TX_METER(xps->meter_type) ? "Tx" : "Rx"; + if (IS_PPS_METER(xps->meter_type)) + { + PLCR_LOG_INFO( + "The Max %s Rate of VF%d has been set to %d Packets/s\n", + direction, xps->vf_obj->vf_idx, data); + } + else + { + PLCR_LOG_INFO( + "The Rate of VF%d has been set to: Min %s Rate: %d Mbit/s, Max %s Rate: %d Mbit/s\n", + xps->vf_obj->vf_idx, + direction, rate_limit_paras.min_rate, + direction, rate_limit_paras.max_rate); + } +#endif + + if (data_type == ZXDH_VF_MIN_RATE) + xps->min_rate = data; + else + xps->max_rate = data; + + return rtn ? rtn : count; +} + +static ssize_t zxdh_vf_meter_min_rate_show(struct zxdh_vf_meter_obj *xps, + struct zxdh_vf_meter_attribute *attr, char *buf) +{ + uint32_t meter_type = xps->meter_type; + LOG_INFO("enter\n"); + + return sysfs_emit(buf, + "usage: write to set VF %s min rate\n", + IS_TX_METER(meter_type) ? "tx" : "rx"); +} + +static ssize_t zxdh_vf_meter_min_rate_store(struct zxdh_vf_meter_obj *xps, + struct zxdh_vf_meter_attribute *attr, const char *buf, size_t count) +{ + return zxdh_vf_meter_rate_store(xps, attr, buf, count, ZXDH_VF_MIN_RATE); +} + +static ssize_t zxdh_vf_meter_max_rate_show(struct zxdh_vf_meter_obj *xps, + struct zxdh_vf_meter_attribute *attr, char *buf) +{ + uint32_t meter_type = xps->meter_type; + LOG_INFO("enter\n"); + + return sysfs_emit(buf, + "usage: write to set VF %s max rate\n", + IS_PPS_METER(meter_type) ? "Packets/s" : "Mbit/s", + IS_TX_METER(meter_type) ? "tx" : "rx"); +} + +static ssize_t zxdh_vf_meter_max_rate_store(struct zxdh_vf_meter_obj *xps, + struct zxdh_vf_meter_attribute *attr, const char *buf, size_t count) +{ + return zxdh_vf_meter_rate_store(xps, attr, buf, count, ZXDH_VF_MAX_RATE); +} + + +#define ZXDH_RATE_GROUP_ATTR(_name) \ + static struct zxdh_group_attribute zxdh_group_##_name = \ + __ATTR(_name, 0644, zxdh_group_##_name##_show, zxdh_group_##_name##_store) + +#define ZXDH_VF_ATTR(_name) \ + static struct zxdh_vf_attribute zxdh_vf_##_name = \ + __ATTR(_name, 0644, zxdh_vf_##_name##_show, zxdh_vf_##_name##_store) + +#define ZXDH_VF_METER_ATTR(_name) \ + static struct zxdh_vf_meter_attribute zxdh_vf_meter_##_name = \ + __ATTR(_name, 0644, zxdh_vf_meter_##_name##_show, zxdh_vf_meter_##_name##_store) + +/* Sysfs attributes cannot be world-writable. */ +ZXDH_RATE_GROUP_ATTR(max_tx_rate); +ZXDH_RATE_GROUP_ATTR(max_rx_rate); +ZXDH_RATE_GROUP_ATTR(config); +ZXDH_VF_ATTR(config); +ZXDH_VF_ATTR(group); +ZXDH_VF_METER_ATTR(min_rate); +ZXDH_VF_METER_ATTR(max_rate); + +// static struct zxdh_group_attribute zxdh_group_max_tx_rate __ro_after_init +// = __ATTR(max_tx_rate, 0200, NULL, zxdh_group_max_tx_rate_store); + +// static struct zxdh_group_attribute zxdh_group_config __ro_after_init +// = __ATTR(config, 0444, zxdh_group_config_show, NULL); + +// static struct zxdh_vf_attribute zxdh_vf_group __ro_after_init +// = __ATTR(group, 0644, zxdh_vf_group_show, zxdh_vf_group_store); + +/* + * Create a group of attributes so that we can create and destroy them all + * at once. + */ +static struct attribute *zxdh_group_default_attrs[] = { + &zxdh_group_max_tx_rate.attr, + &zxdh_group_max_rx_rate.attr, + &zxdh_group_config.attr, + NULL, /* need to NULL terminate the list of attributes */ +}; +ATTRIBUTE_GROUPS(zxdh_group_default); + +static struct attribute *zxdh_vf_default_attrs[] = { + &zxdh_vf_config.attr, + &zxdh_vf_group.attr, + NULL, +}; +ATTRIBUTE_GROUPS(zxdh_vf_default); + +static struct attribute *zxdh_vf_meter_bps_attrs[] = { + &zxdh_vf_meter_min_rate.attr, + &zxdh_vf_meter_max_rate.attr, + NULL, +}; +ATTRIBUTE_GROUPS(zxdh_vf_meter_bps); + +static struct attribute *zxdh_vf_meter_pps_attrs[] = { + &zxdh_vf_meter_max_rate.attr, + NULL, +}; +ATTRIBUTE_GROUPS(zxdh_vf_meter_pps); + +/* + * Our own ktype for our kobjects. Here we specify our sysfs ops, the + * release function, and the set of default attributes we want created + * whenever a kobject of this type is registered with the kernel. + */ +// static const struct kobj_type +static struct kobj_type zxdh_group_ktype = { + .sysfs_ops = &zxdh_group_sysfs_ops, + // .release = zxdh_group_release, + .default_groups = zxdh_group_default_groups, +}; + +// static const struct kobj_type +static struct kobj_type zxdh_vf_ktype = { + .sysfs_ops = &zxdh_vf_sysfs_ops, + // .release = zxdh_vf_release, + .default_groups = zxdh_vf_default_groups, +}; + +static struct kobj_type zxdh_vf_meter_bps_ktype = { + .sysfs_ops = &zxdh_vf_meter_sysfs_ops, + // .release = zxdh_vf_meter_release, + .default_groups = zxdh_vf_meter_bps_groups, +}; + +static struct kobj_type zxdh_vf_meter_pps_ktype = { + .sysfs_ops = &zxdh_vf_meter_sysfs_ops, + // .release = zxdh_vf_meter_release, + .default_groups = zxdh_vf_meter_pps_groups, +}; + +static struct zxdh_group_obj * +zxdh_create_group_obj(struct zxdh_pf_device *pf_dev, int32_t group_id) +{ + struct kobject *groups_obj = pf_dev->sriov.groups_obj; + struct zxdh_group_obj *group; + int rtn = 0; + + LOG_INFO("enter\n"); + /* allocate the memory for the whole object */ + group = kzalloc(sizeof(struct zxdh_group_obj), GFP_KERNEL); + if (!group) + return ERR_PTR(-ENOMEM); + + group->pf_dev = pf_dev; + group->group_id = group_id; + + rtn = kobject_init_and_add(&group->kobj, &zxdh_group_ktype, groups_obj, "group%d", group_id); + if (rtn) + { + LOG_INFO("create group-%d kobject failed\n", group_id); + kobject_put(&group->kobj); + kfree(group); + return ERR_PTR(rtn); + } + + /* We are always responsible for sending the uevent that the kobject + * was added to the system. + */ + kobject_uevent(&group->kobj, KOBJ_ADD); + + list_add_tail(&group->list, &pf_dev->sriov.groups_head); + + init_completion(&group->free_group_comp); + + return group; +} + +int zxdh_create_vf_obj(struct zxdh_pf_device *pf_dev, uint16_t vf_idx) +{ + struct zxdh_vf_obj *vf_obj; + int rtn; + + LOG_INFO("enter\n"); + + vf_obj = pf_dev->sriov.vfs + vf_idx; + vf_obj->pf_dev = pf_dev; + vf_obj->vport = pf_dev->vf_item[vf_idx].vport; + vf_obj->vf_idx = vf_idx; + vf_obj->group = pf_dev->sriov.group_0; + + LOG_INFO("p_sriov_obj = %p, vport = %d\n", pf_dev->sriov.sriov_obj, pf_dev->vport); + LOG_INFO("vf_idx = %d, vport = %d, group_id = %d\n",\ + pf_dev->sriov.vfs[vf_idx].vf_idx, pf_dev->sriov.vfs[vf_idx].vport, pf_dev->sriov.vfs[vf_idx].group->group_id); + + rtn = kobject_init_and_add(&vf_obj->kobj, &zxdh_vf_ktype, pf_dev->sriov.sriov_obj, + "vf%d", vf_idx); + if (rtn) + { + LOG_INFO("create vf-%d kobject failed\n", vf_idx); + kobject_put(&vf_obj->kobj); + return -ENOMEM; + } + + vf_obj->group->num_vfs ++; + + kobject_uevent(&vf_obj->kobj, KOBJ_ADD); + + return rtn; +} + +static void zxdh_destroy_group_obj_work(struct work_struct *work) +{ + struct zxdh_group_work *group_work = container_of(work, struct zxdh_group_work, work); + struct zxdh_group_obj *group_obj = group_work->group_obj; + + LOG_INFO("enter\n"); + kobject_put(&group_obj->kobj); + complete_all(&group_obj->free_group_comp); + kfree(group_work); +} + +void zxdh_destroy_group_obj(struct zxdh_group_obj *group_obj) +{ + struct zxdh_group_work *group_work; + + LOG_INFO("enter\n"); + group_work = kzalloc(sizeof *group_work, GFP_ATOMIC); + if (unlikely(NULL == group_work)) + { + kobject_put(&group_obj->kobj); + complete_all(&group_obj->free_group_comp); + + list_del(&group_obj->list); + return; + } + + INIT_WORK(&group_work->work, zxdh_destroy_group_obj_work); + group_work->group_obj = group_obj; + queue_work(system_wq, &group_work->work); + + list_del(&group_obj->list); +} + +void zxdh_destroy_vf_obj(struct zxdh_pf_device *pf_dev, uint16_t vf_idx) +{ + struct zxdh_vf_obj *vf_obj; + + LOG_INFO("enter\n"); + vf_obj = pf_dev->sriov.vfs + vf_idx; + kobject_put(&vf_obj->kobj); +} + + +/********************************************** +**********************************************/ + +static struct zxdh_group_obj * +zxdh_find_sysfs_group(struct zxdh_pf_device *pf_dev, int32_t group_id) +{ + struct zxdh_group_obj *group; + + list_for_each_entry(group, &pf_dev->sriov.groups_head, list) + { + if (group->group_id == group_id) + return group; + } + + return NULL; +} + +int zxdh_vf_update_sysfs_group(struct zxdh_pf_device *pf_dev, struct zxdh_vf_obj *vf, int32_t group_id) +{ + struct zxdh_group_obj *curr_group; + struct zxdh_group_obj *new_group; + int rtn = 0; +#ifdef ZXDH_PLCR_OPEN + struct xarray *xarray_flowid; + struct zxdh_plcr_flow *plcr_rx_flow; + struct zxdh_plcr_flow *plcr_tx_flow; + int16_t curr_rx_id; + int16_t curr_tx_id; +#endif + + // mutex_lock(&esw->state_lock); + + curr_group = vf->group; + if (curr_group && curr_group->group_id == group_id) + { + LOG_ERR("VF is already in the group%d\n", group_id); + goto out; + } + + if (group_id) + { + new_group = zxdh_find_sysfs_group(pf_dev, group_id); + if (!new_group) + { + new_group = zxdh_create_group_obj(pf_dev, group_id); + if (IS_ERR(new_group)) + { + rtn = PTR_ERR(new_group); + LOG_ERR("create new sysfs group-%d failed (%d)\n", group_id, rtn); + goto out; + } + } + } + else + { + new_group = pf_dev->sriov.group_0; + } + +#ifdef ZXDH_PLCR_OPEN + //调用限速统一接口，映射vf到目标group + rtn = zxdh_move_vf_to_group(vf, new_group); + if (rtn) + { + PLCR_LOG_ERR("failed and rtn=0x%x\n", rtn) + goto err_update; + } +#endif + + vf->group = new_group; + new_group->num_vfs++; + if (!curr_group) + goto out; + curr_group->num_vfs--; + + if (curr_group != pf_dev->sriov.group_0 && !curr_group->num_vfs) + { + zxdh_destroy_group_obj(curr_group); + +#ifdef ZXDH_PLCR_OPEN + //限速统一接口，移除当前carc flow限速 + curr_rx_id = zxdh_group_to_flowid(curr_group, ZXDH_GROUP_RX_RATE); + curr_tx_id = zxdh_group_to_flowid(curr_group, ZXDH_GROUP_TX_RATE); + + xarray_flowid = &(pf_dev->plcr_table.plcr_flows[E_PLCR_CAR_C]); + plcr_rx_flow = xa_load(xarray_flowid, curr_rx_id); + plcr_tx_flow = xa_load(xarray_flowid, curr_tx_id); + + if (xa_load(xarray_flowid, curr_rx_id)) + rtn = zxdh_set_vf_group_rate_limit(curr_group, ZXDH_GROUP_RX_RATE, 0); + if (xa_load(xarray_flowid, curr_rx_id)) + rtn = zxdh_set_vf_group_rate_limit(curr_group, ZXDH_GROUP_TX_RATE, 0); +#endif + + wait_for_completion(&curr_group->free_group_comp); + kfree(curr_group); + } + goto out; + +#ifdef ZXDH_PLCR_OPEN +err_update: + if (new_group != pf_dev->sriov.group_0 && !new_group->num_vfs) + { + zxdh_destroy_group_obj(new_group); + + wait_for_completion(&new_group->free_group_comp); + kfree(new_group); + } +#endif +out: + // mutex_unlock(&esw->state_lock); + return rtn; +} + +static int zxdh_creat_vf_meter_obj(struct zxdh_vf_obj *vf, + struct zxdh_vf_meters *meters, + uint32_t meter_type) +{ + struct zxdh_vf_meter_obj *xps; + struct kobject *parent; + struct kobj_type *ktype; + const char *name; + int rtn; + + if (meter_type >= VF_METER_TYPE_NUM) + return -EINVAL; + + xps = &meters->xps[meter_type]; + + if (IS_TX_METER(meter_type)) + parent = meters->tx_obj; + else + parent = meters->rx_obj; + + if (IS_PPS_METER(meter_type)) + { + ktype = &zxdh_vf_meter_pps_ktype; + name = "pps"; + } + else + { + ktype = &zxdh_vf_meter_bps_ktype; + name = "bps"; + } + + rtn = kobject_init_and_add(&xps->kobj, ktype, parent, name); + if (rtn) + { + kobject_put(&xps->kobj); + return rtn; + } + + xps->pf_dev = vf->pf_dev; + xps->vf_obj = vf; + xps->meter_type = meter_type; + + return 0; +} + +int zxdh_create_vf_meters_sysfs(struct zxdh_pf_device *pf_dev, uint16_t vf_idx) +{ + int rtn = 0; + struct zxdh_vf_obj *vf; + struct zxdh_vf_meters *meters; + + LOG_INFO("enter\n"); + + vf = pf_dev->sriov.vfs + vf_idx; + + meters = kzalloc(sizeof(struct zxdh_vf_meters), GFP_KERNEL); + if (!meters) + { + return -ENOMEM; + } + + meters->kobj = kobject_create_and_add("meters", &vf->kobj); + if (!meters->kobj) + { + rtn = -EINVAL; + goto err_vf_meters; + } + + meters->rx_obj = kobject_create_and_add("rx", meters->kobj); + if (!meters->rx_obj) + { + rtn = -EINVAL; + goto err_vf_meters; + } + + meters->tx_obj = kobject_create_and_add("tx", meters->kobj); + if (!meters->tx_obj) + { + rtn = -EINVAL; + goto err_vf_meters; + } + + rtn = zxdh_creat_vf_meter_obj(vf, meters, VF_METER_RX_BPS); + if (rtn) + goto err_vf_meters; + + rtn = zxdh_creat_vf_meter_obj(vf, meters, VF_METER_RX_PPS); + if (rtn) + goto err_put_xps_0; + + rtn = zxdh_creat_vf_meter_obj(vf, meters, VF_METER_TX_BPS); + if (rtn) + goto err_put_xps_1; + + rtn = zxdh_creat_vf_meter_obj(vf, meters, VF_METER_TX_PPS); + if (rtn) + goto err_put_xps_2; + + vf->meters = meters; + + return 0; + +err_put_xps_2: + kobject_put(&meters->xps[VF_METER_TX_BPS].kobj); +err_put_xps_1: + kobject_put(&meters->xps[VF_METER_RX_PPS].kobj); +err_put_xps_0: + kobject_put(&meters->xps[VF_METER_RX_BPS].kobj); +err_vf_meters: + kobject_put(meters->rx_obj); + kobject_put(meters->tx_obj); + kobject_put(meters->kobj); + + kfree(meters); + + return rtn; +} + +static void zxdh_destroy_vf_meters_sysfs(struct zxdh_pf_device *pf_dev, uint16_t vf_idx) +{ + struct zxdh_vf_obj *vf; + struct zxdh_vf_meters *meters; + uint32_t meter_type; + + LOG_INFO("enter\n"); + + vf = pf_dev->sriov.vfs + vf_idx; + meters = vf->meters; + if (!meters) + return; + + //限速统一接口，移除当前vf所有限速 todo:en层的vf remove应该已经执行了该操作 + + for (meter_type = 0; meter_type < 4; meter_type++) + kobject_put(&meters->xps[meter_type].kobj); + + kobject_put(meters->rx_obj); + kobject_put(meters->tx_obj); + kobject_put(meters->kobj); + + kfree(meters); +} + +int zxdh_create_vfs_sysfs(struct dh_core_dev *dev, int32_t num_vfs) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dev); + int rtn = 0; + uint16_t vf_idx; + + LOG_INFO("enter\n"); + pf_dev->sriov.vfs = kcalloc(num_vfs, sizeof(struct zxdh_vf_obj), GFP_KERNEL); + if (!pf_dev->sriov.vfs) + { + LOG_ERR("kcalloc vfs failed\n"); + return -ENOMEM; + } + + for (vf_idx = 0; vf_idx < num_vfs; vf_idx++) + { + rtn = zxdh_create_vf_obj(pf_dev, vf_idx); + if (rtn) + { + LOG_ERR("zxdh_create_vf_obj failed\n"); + goto err_vf; + } + + rtn = zxdh_create_vf_meters_sysfs(pf_dev, vf_idx); + if (rtn) + { + zxdh_destroy_vf_obj(pf_dev, vf_idx); + LOG_ERR("zxdh_create_vf_meters_sysfs failed\n"); + goto err_vf; + } + } + + return 0; + +err_vf: + for (; vf_idx > 0; --vf_idx) + { + zxdh_destroy_vf_meters_sysfs(pf_dev, vf_idx); + + zxdh_destroy_vf_obj(pf_dev, vf_idx); + } + + kfree(pf_dev->sriov.vfs); + pf_dev->sriov.vfs = NULL; + + return rtn; +} + +void zxdh_destroy_vfs_sysfs(struct dh_core_dev *dev, int32_t num_vfs) +{ + struct zxdh_pf_device *pf_dev = dh_core_priv(dev); + struct zxdh_vf_obj *vf; + uint16_t vf_idx; + + LOG_INFO("enter\n"); + if (!num_vfs || !pf_dev->sriov.vfs) + return; + + for (vf_idx = 0; vf_idx < num_vfs; vf_idx++) + { + vf = pf_dev->sriov.vfs + vf_idx; + + if (vf->group != pf_dev->sriov.group_0) + zxdh_vf_update_sysfs_group(pf_dev, vf, 0); + + zxdh_destroy_vf_meters_sysfs(pf_dev, vf_idx); + + zxdh_destroy_vf_obj(pf_dev, vf_idx); + } + kfree(pf_dev->sriov.vfs); + pf_dev->sriov.vfs = NULL; +} + +void zxdh_cleanup_sysfs_group(struct zxdh_pf_device *pf_dev) +{ + struct zxdh_group_obj *group, *tmp; + + LOG_INFO("enter\n"); + list_for_each_entry_safe(group, tmp, &pf_dev->sriov.groups_head, list) + { + list_del(&group->list); + kfree(group); + } +} + +#ifdef ZXDH_PLCR_DEBUG +int zxdh_sriov_attr_create(struct zxdh_pf_device *pf_dev) +{ + int rtn; + struct zxdh_sriov_sysfs *sriov = &pf_dev->sriov; + + LOG_INFO("enter\n"); + + sriov->burst_attr.attr.name = "burst"; + sriov->burst_attr.attr.mode = 0644; + sriov->burst_attr.show = zxdh_burst_show; + sriov->burst_attr.store = zxdh_burst_store; + rtn = sysfs_create_file(sriov->sriov_obj, &sriov->burst_attr.attr); + if (rtn) + { + LOG_ERR("burst sysfs_create_file failed!") + return rtn; + } + + sriov->profile_attr.attr.name = "profiles_stat"; + sriov->profile_attr.attr.mode = 0444; + sriov->profile_attr.show = zxdh_profile_stat_show; + sriov->profile_attr.store = NULL; + rtn = sysfs_create_file(sriov->sriov_obj, &sriov->profile_attr.attr); + if (rtn) + { + LOG_ERR("profiles_stat sysfs_create_file failed!") + goto err_profile_attr; + } + + return rtn; + +err_profile_attr: + sysfs_remove_file(sriov->sriov_obj, &sriov->burst_attr.attr); + return rtn; +} + +void zxdh_sriov_attr_remove(struct zxdh_pf_device *pf_dev) +{ + struct zxdh_sriov_sysfs *sriov = &pf_dev->sriov; + + LOG_INFO("enter\n"); + sysfs_remove_file(sriov->sriov_obj, &sriov->profile_attr.attr); + sysfs_remove_file(sriov->sriov_obj, &sriov->burst_attr.attr); +} +#endif + +int zxdh_sriov_sysfs_init(struct dh_core_dev *dev) +{ + struct device *device = dev->device; + struct zxdh_pf_device *pf_dev = dh_core_priv(dev); + int rtn = 0; + + if (dev->coredev_type != DH_COREDEV_PF) + return rtn; + + pf_dev->sriov.sriov_obj = kobject_create_and_add("sriov", &device->kobj); + if (!pf_dev->sriov.sriov_obj) + { + LOG_ERR("zxdh create sriov sysfs failed (%d)\n", -ENOMEM); + return -ENOMEM; + } + +#ifdef ZXDH_PLCR_DEBUG + rtn = zxdh_sriov_attr_create(pf_dev); + if (rtn) + { + LOG_ERR("zxdh_sriov_attr_create failed (%d)\n", rtn); + goto err_attr; + } +#endif + + pf_dev->sriov.groups_obj = kobject_create_and_add("groups", pf_dev->sriov.sriov_obj); + if (!pf_dev->sriov.groups_obj) + { + LOG_ERR("zxdh create groups sysfs failed (%d)\n", -ENOMEM); + rtn = -ENOMEM; + goto err_groups; + } + + INIT_LIST_HEAD(&pf_dev->sriov.groups_head); + pf_dev->sriov.group_0 = zxdh_create_group_obj(pf_dev, ZXDH_DEFAULT_VF_GROUP_ID); + if (IS_ERR(pf_dev->sriov.group_0)) + { + LOG_ERR("zxdh create rate group 0 failed (%ld)\n", PTR_ERR(pf_dev->sriov.group_0)); + rtn = PTR_ERR(pf_dev->sriov.group_0); + goto err_group0; + } + + LOG_INFO("p_sriov_obj = %p, vport = 0x%x\n", pf_dev->sriov.sriov_obj, pf_dev->vport); + + return rtn; + +err_group0: + kobject_put(pf_dev->sriov.groups_obj); + pf_dev->sriov.groups_obj = NULL; +err_groups: +#ifdef ZXDH_PLCR_DEBUG + zxdh_sriov_attr_remove(pf_dev); +err_attr: +#endif + kobject_put(pf_dev->sriov.sriov_obj); + pf_dev->sriov.sriov_obj = NULL; + + return rtn; +} + +void zxdh_sriov_sysfs_exit(struct dh_core_dev *dev) +{ + // struct device *device = &dev->pdev->dev; + struct zxdh_pf_device *pf_dev = dh_core_priv(dev); + + if (dev->coredev_type != DH_COREDEV_PF) + return; + + LOG_INFO("enter\n"); + zxdh_destroy_group_obj(pf_dev->sriov.group_0); + wait_for_completion(&pf_dev->sriov.group_0->free_group_comp); + kfree(pf_dev->sriov.group_0); + + zxdh_cleanup_sysfs_group(pf_dev); + + kobject_put(pf_dev->sriov.groups_obj); + pf_dev->sriov.groups_obj = NULL; +#ifdef ZXDH_PLCR_DEBUG + zxdh_sriov_attr_remove(pf_dev); +#endif + kobject_put(pf_dev->sriov.sriov_obj); + pf_dev->sriov.sriov_obj = NULL; +} diff --git a/src/net/drivers/net/ethernet/dinghai/wq.c b/src/net/drivers/net/ethernet/dinghai/wq.c new file mode 100755 index 0000000..e69de29 diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/bar_chan_user/normal_send_eg.c b/src/net/drivers/net/ethernet/dinghai/zf_mpf/bar_chan_user/normal_send_eg.c new file mode 100644 index 0000000..a25dab8 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/bar_chan_user/normal_send_eg.c @@ -0,0 +1,137 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define BAR_CHAN_PLOAD_SIZE (2036) +#define BAR_REPS_HDR_LEN (4) +#define DEVICE_FILE "/dev/bar_ioctl_dev" +#define BAR_IOCTL_CMD_NORMAL _IOW('a', 1, msg_entity_t) + +struct zxdh_pci_bar_msg +{ + uint64_t virt_addr; /**< 4k空间地址, 若src为MPF该参数不生效>**/ + void *payload_addr; /**< 消息净荷地址>**/ + uint16_t payload_len; /**< 消息净荷长度>**/ + uint16_t emec; /**< 消息紧急类型>**/ + uint16_t src; /**< 消息发送源，参考BAR_DRIVER_TYPE>**/ + uint16_t dst; /**< 消息接收者，参考BAR_DRIVER_TYPE>**/ + uint32_t module_id; /**< 事件id>**/ + uint16_t src_pcieid; /**< 源 pcie_id>**/ + uint16_t dst_pcieid; /**< 目的pcie_id>**/ +}; +struct zxdh_msg_recviver_mem +{ + void *recv_buffer; /**< 消息接收缓存>**/ + uint16_t buffer_len; /**< 消息缓存长度>**/ +}; + +struct zxdh_ioctl_send_paras +{ + uint16_t pload_len; + uint16_t src; + uint16_t dst; + uint16_t event_id; +}; + +struct zxdh_ioctl_recv_paras +{ + int ioctl_state; //ioctrl级别返回值 + int bar_state; //bar通道接口级别返回值 +}; + +typedef struct normal_msg_entity +{ + union ioctl_ctrl_hdr //私有消息控制头 + { + struct zxdh_ioctl_send_paras send_msg_hdr; //普通消息发送头 + struct zxdh_ioctl_recv_paras recv_msg_hdr; //普通消息发送头 + }hdr; + uint8_t pload[BAR_CHAN_PLOAD_SIZE + BAR_REPS_HDR_LEN]; +}msg_entity_t; + +struct zxdh_bar_reps_hdr +{ + uint8_t is_replied; + uint16_t reps_len; + uint8_t rsv; +}__attribute__((packed)); + +struct zxdh_bar_reps +{ + struct zxdh_bar_reps_hdr hdr; + uint8_t reps_data[BAR_CHAN_PLOAD_SIZE]; +}__attribute__((packed)); + +int zxdh_bar_chan_mpf_ioctl_msg_send(struct zxdh_pci_bar_msg *in, struct zxdh_msg_recviver_mem *result) +{ + int fd, ret; + struct normal_msg_entity entity = {0}; + struct zxdh_bar_reps *reps = NULL; + + entity.hdr.send_msg_hdr.pload_len = in->payload_len; + entity.hdr.send_msg_hdr.src = in->src; + entity.hdr.send_msg_hdr.dst = in->dst; + entity.hdr.send_msg_hdr.event_id = in->module_id; + + /* 用户态长度异常*/ + if (in->payload_len > BAR_CHAN_PLOAD_SIZE) + { + return -1; + } + /* 拷贝消息到iotcl结构体*/ + memcpy(entity.pload, in->payload_addr, in->payload_len); + + fd = open(DEVICE_FILE, O_RDWR); + if (fd < 0) { + perror("Failed to open the device."); + return 1; + } + + ret = ioctl(fd, BAR_IOCTL_CMD_NORMAL, &entity); + if (ret < 0) { + perror("IOCTL command failed."); + ret = 1; + goto out; + } + printf("reps: 0x%llx.\n", *(uint64_t*)entity.pload); + + /* ioctl通信异常*/ + if (entity.hdr.recv_msg_hdr.ioctl_state != 0) + { + //return IOCTL_ERR + printf("ioctl failed, state: %d\n", entity.hdr.recv_msg_hdr.ioctl_state); + ret = -1; + goto out; + } + + /* 调用bar通道内核态接口错误*/ + if (entity.hdr.recv_msg_hdr.bar_state != 0) + { + //return IOCTL_ERR + printf("bar send err, state: %d\n", entity.hdr.recv_msg_hdr.bar_state); + ret = entity.hdr.recv_msg_hdr.bar_state; + goto out; + } + + /* 判断返回的消息长度是否足够放下*/ + reps = (struct zxdh_bar_reps *)(entity.pload); + if (reps->hdr.reps_len + 4 > result->buffer_len) + { + printf("reps_len is %d, but buffer_len is%d.\n", reps->hdr.reps_len + 4, + result->buffer_len); + ret = -1; + goto out; + } + memcpy(result->recv_buffer, reps, reps->hdr.reps_len + 4); +out: + close(fd); + return 0; +} \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/bar_chan_user/pci_res_query_eg.c b/src/net/drivers/net/ethernet/dinghai/zf_mpf/bar_chan_user/pci_res_query_eg.c new file mode 100644 index 0000000..b7ca92e --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/bar_chan_user/pci_res_query_eg.c @@ -0,0 +1,214 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DEVICE_FILE "/dev/bar_ioctl_dev" +#define ZXDH_PF_DEV_NUM (40) +#define BAR_IOCTL_CMD_SINGLE_DEV _IOW('a', 2, pci_res_st) +#define BAR_IOCTL_CMD_ALL_DEV _IOW('a', 3, pci_res_st) +#define PF_PCIE_ID(pf_idx) (((pf_idx % 8) << 8) | (1 << 11) | ((pf_idx / 8) << 12)) + +struct zxdh_mpf_pci_res_item +{ + uint16_t device_id; + uint16_t pcie_id; + uint16_t bdf; + uint8_t link_state; + uint8_t dev_type; + uint16_t total_vfs; + uint16_t initial_vfs; + uint16_t num_vfs; + uint8_t vf_stride; + uint8_t first_vf_offset; + int res; + uint8_t pad[4]; //预留字段 +}; + +/* zf内核态和risc通信的约定结构体*/ +struct zxdh_mpf_pci_res_list +{ + uint16_t num; + uint16_t verno; //版本号 + int res; //0表示返回成功， 其他表示失败， 包括消息发送失败 + struct zxdh_mpf_pci_res_item pci_res_lis[ZXDH_PF_DEV_NUM]; +}; + +struct zxdh_mpf_query_pci_res_msg +{ + uint16_t pcie_id; + uint8_t dev_type; + uint8_t pad[5]; + struct zxdh_mpf_pci_res_list reply; +}; + +typedef struct zxdh_mpf_query_bar_msg +{ + int ioctl_state; + int bar_state; + struct zxdh_mpf_query_pci_res_msg pci_res_msg; +}pci_res_st; + +void print_pf_pci_res(struct zxdh_mpf_pci_res_item *item) +{ + printf("device_id: 0x%x.\n", item->device_id); + printf("link_state: %d.\n",item->link_state); + printf("pcie_id: 0x%x.\n",item->pcie_id); + printf("bdf: 0x%x.\n",item->bdf); + printf("dev_type: %d.\n",item->dev_type); + printf("total_vfs: %d.\n",item->total_vfs); + printf("initial_vfs: %d.\n",item->initial_vfs); + printf("num_vfs: %d.\n",item->num_vfs); + printf("vf_stride: %d.\n",item->vf_stride); + printf("first_vf_offset: %d.\n",item->first_vf_offset); + return; +} + +static int zxdh_get_dev_pci_resource(uint16_t pcie_id, struct zxdh_mpf_query_bar_msg *data, int cmd) +{ + int fd, ret; + struct zxdh_mpf_query_bar_msg msg = {0}; + + msg.pci_res_msg.pcie_id = pcie_id; + msg.pci_res_msg.dev_type = 8; + + fd = open(DEVICE_FILE, O_RDWR); + if (fd < 0) + { + perror("Failed to open the device."); + return 1; + } + + ret = ioctl(fd, cmd, &msg); + if (ret < 0) + { + perror("IOCTL command failed."); + ret = 1; + goto out; + } + + /* ioctl通信异常*/ + if (msg.ioctl_state != 0) + { + //return IOCTL_ERR + printf("ioctl failed, state: %d\n", msg.ioctl_state); + ret = -1; + goto out; + } + + /* 调用bar通道内核态接口错误*/ + if (msg.bar_state != 0) + { + //return IOCTL_ERR + printf("bar send err, state: %d\n", msg.bar_state); + ret = msg.bar_state; + goto out; + } + + *data = msg; +out: + close(fd); + return ret; +} + +int zxdh_get_dev_pci_resource_single(uint16_t pcie_id, struct zxdh_mpf_query_bar_msg *data) +{ + return zxdh_get_dev_pci_resource(pcie_id, data, BAR_IOCTL_CMD_SINGLE_DEV); +} + +int zxdh_get_dev_pci_resource_all(struct zxdh_mpf_query_bar_msg *data) +{ + return zxdh_get_dev_pci_resource(0, data, BAR_IOCTL_CMD_ALL_DEV); +} + +void test_pci_res_query_single(uint16_t pcie_id) +{ + int ret = 0; + struct zxdh_mpf_query_bar_msg data = {0}; + + printf("**************pcie_id: 0x%x**************.\n", pcie_id); + ret = zxdh_get_dev_pci_resource_single(pcie_id, &data); + if (ret != 0) + { + printf("ioctl msg failed, ret: %d.\n", ret); + return; + } + if (data.pci_res_msg.reply.res != 0) + { + printf("data.pci_res_msg.reply.res is %d.\n", data.pci_res_msg.reply.res); + return; + } + print_pf_pci_res(&data.pci_res_msg.reply.pci_res_lis[0]); + return; +} + +void test_pci_res_query_all() +{ + int pf_idx = 0; + int ret = 0; + uint16_t pcie_id = 0; + struct zxdh_mpf_query_bar_msg data = {0}; + + ret = zxdh_get_dev_pci_resource_all(&data); + if (ret != 0) + { + printf("ioctl msg failed, ret:%d.\n", ret); + } + + printf("res: %d.\n", data.pci_res_msg.reply.res); + printf("num: %d.\n", data.pci_res_msg.reply.num); + + for (pf_idx = 0; pf_idx < 40; pf_idx++) + { + printf("********%dth dev, ep:%d, pf: %d**********.\n", pf_idx, pf_idx / 8, pf_idx % 8); + + if (data.pci_res_msg.reply.pci_res_lis[pf_idx].res != 0) + { + printf("invalid res.\n"); + continue; + } + print_pf_pci_res(&data.pci_res_msg.reply.pci_res_lis[pf_idx]); + } +} + +int main(int argc, char *argv[]) +{ + uint16_t pcie_id = 0; + + if (argc < 2) + { + goto help; + } + if (strcmp(argv[1], "all") == 0) + { + test_pci_res_query_all(); + goto out; + } + else if(strcmp(argv[1], "dev") == 0) + { + if (argc < 3) + { + goto help; + } + pcie_id = strtol(argv[2],NULL, 16); + test_pci_res_query_single(pcie_id); + goto out; + } + else + { + goto help; + } + +help: + printf("./test all ------------------print all pci_dev resources.\n"); + printf("./test dev [pcie_id] --------print pci_dev resource.\n"); +out: + return 0; +} diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/cfg_sf.c b/src/net/drivers/net/ethernet/dinghai/zf_mpf/cfg_sf.c new file mode 100755 index 0000000..1927049 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/cfg_sf.c @@ -0,0 +1,53 @@ +#include +#include + +#include "cfg_sf.h" + +static int32_t zxdh_cfg_resume(struct zxdh_auxiliary_device *adev) +{ + return 0; +} + +static int32_t zxdh_cfg_suspend(struct zxdh_auxiliary_device *adev, pm_message_t state) +{ + return 0; +} + +static int32_t zxdh_cfg_probe(struct zxdh_auxiliary_device *adev, + const struct zxdh_auxiliary_device_id *id) +{ + struct cfg_sf_dev * __attribute__((unused)) cfg_sf_dev = container_of(adev, struct cfg_sf_dev, adev); + + return 0; +} + +static int32_t zxdh_cfg_remove(struct zxdh_auxiliary_device *adev) +{ + return 0; +} + +static const struct zxdh_auxiliary_device_id zxdh_cfg_id_table[] = { + { .name = ZXDH_EN_SF_NAME ".mpf_cfg", }, + {}, +}; + +//MODULE_DEVICE_TABLE(auxiliary_zxdh_id_table, zxdh_cfg_id_table); + +static struct zxdh_auxiliary_driver zxdh_cfg_driver = { + .name = "mpf_cfg", + .probe = zxdh_cfg_probe, + .remove = zxdh_cfg_remove, + .suspend = zxdh_cfg_suspend, + .resume = zxdh_cfg_resume, + .id_table = zxdh_cfg_id_table, +}; + +int32_t zxdh_mpf_sf_driver_register(void) +{ + return zxdh_auxiliary_driver_register(&zxdh_cfg_driver);; +} + +void zxdh_mpf_sf_driver_uregister(void) +{ + zxdh_auxiliary_driver_unregister(&zxdh_cfg_driver);; +} diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/cfg_sf.h b/src/net/drivers/net/ethernet/dinghai/zf_mpf/cfg_sf.h new file mode 100755 index 0000000..ec0fdd0 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/cfg_sf.h @@ -0,0 +1,30 @@ +#ifndef __ZXDH_MPF_CFG_SF_H__ +#define __ZXDH_MPF_CFG_SF_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +struct cfg_sf_ops { + +}; + +struct cfg_sf_dev { + struct zxdh_auxiliary_device adev; + struct dh_core_dev *dh_dev; + struct cfg_sf_ops *ops; +}; + +int32_t zxdh_mpf_sf_driver_register(void); +void zxdh_mpf_sf_driver_uregister(void); + + +#ifdef __cplusplus +} +#endif + + +#endif \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/devlink.c b/src/net/drivers/net/ethernet/dinghai/zf_mpf/devlink.c new file mode 100755 index 0000000..e89a752 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/devlink.c @@ -0,0 +1,130 @@ +#include +#include +#include "devlink.h" + +struct devlink_ops dh_mpf_devlink_ops = { + +}; + +enum { + DH_MPF_PARAMS_MAX, +}; + +static int32_t __attribute__((unused)) sample_check(struct dh_core_dev *dev) +{ + return 1; +} + +enum dh_mpf_devlink_param_id { + DH_MPF_DEVLINK_PARAM_ID_BASE = DEVLINK_PARAM_GENERIC_ID_MAX, + DH_MPF_DEVLINK_PARAM_ID_SAMPLE, +}; + + +static int32_t dh_devlink_sample_set(struct devlink *devlink, uint32_t id, + struct devlink_param_gset_ctx *ctx) +{ + struct dh_core_dev * __attribute__((unused)) dev = devlink_priv(devlink); + + return 0; +} + +static int32_t dh_devlink_sample_get(struct devlink *devlink, uint32_t id, + struct devlink_param_gset_ctx *ctx) +{ + struct dh_core_dev * __attribute__((unused)) dev = devlink_priv(devlink); + + return 0; +} + +#ifdef HAVE_DEVLINK_PARAM_REGISTER +static const struct devlink_params { + const char *name; + int32_t (*check)(struct dh_core_dev *dev); + struct devlink_param param; +} devlink_params[] = { + [DH_MPF_PARAMS_MAX] = { .name = "sample", + .check = &sample_check, + .param = DEVLINK_PARAM_DRIVER(DH_MPF_DEVLINK_PARAM_ID_SAMPLE, + "sample", DEVLINK_PARAM_TYPE_BOOL, + BIT(DEVLINK_PARAM_CMODE_RUNTIME),dh_devlink_sample_get, + dh_devlink_sample_set, + NULL), + } +}; + +static int32_t params_register(struct devlink *devlink) +{ + int32_t i = 0; + int32_t err = 0; + struct dh_core_dev *dh_dev = devlink_priv(devlink); + + for (i = 0; i < ARRAY_SIZE(devlink_params); i++) + { + if(devlink_params[i].check(dh_dev)) + { + err = devlink_param_register(devlink, &devlink_params[i].param); + if (err) + { + goto rollback; + } + } + } + + return 0; + +rollback: + if (i == 0) + { + return err; + } + + for (; i > 0; i--) + { + devlink_param_unregister(devlink, &devlink_params[i].param); + } + + return err; +} + +static int32_t params_unregister(struct devlink *devlink) +{ + int32_t i = 0; + + for (i = 0; i < ARRAY_SIZE(devlink_params); i++) + { + devlink_param_unregister(devlink, &devlink_params[i].param); + } + + return 0; +} +#else +static struct devlink_param devlink_params [] = { + [DH_MPF_PARAMS_MAX] = DEVLINK_PARAM_DRIVER(DH_MPF_DEVLINK_PARAM_ID_SAMPLE, + "sample", DEVLINK_PARAM_TYPE_BOOL, + BIT(DEVLINK_PARAM_CMODE_RUNTIME),dh_devlink_sample_get, + dh_devlink_sample_set, + NULL), +}; + +static int32_t params_register(struct devlink *devlink) +{ + struct dh_core_dev * __attribute__((unused)) dh_dev = devlink_priv(devlink); + int32_t err = 0; + + err = devlink_params_register(devlink, devlink_params, ARRAY_SIZE(devlink_params)); + + return err; +} +static int32_t params_unregister(struct devlink *devlink) +{ + devlink_params_unregister(devlink, devlink_params, ARRAY_SIZE(devlink_params)); + + return 0; +} +#endif + +struct dh_core_devlink_ops dh_mpf_core_devlink_ops = { + .params_register = params_register, + .params_unregister = params_unregister +}; diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/devlink.h b/src/net/drivers/net/ethernet/dinghai/zf_mpf/devlink.h new file mode 100755 index 0000000..a45fd10 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/devlink.h @@ -0,0 +1,16 @@ +#ifndef __ZXDH_MPF_DEVLINK_H__ +#define __ZXDH_MPF_DEVLINK_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + + + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/epc/Makefile b/src/net/drivers/net/ethernet/dinghai/zf_mpf/epc/Makefile new file mode 100644 index 0000000..ad4897b --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/epc/Makefile @@ -0,0 +1,11 @@ +KDIR=/home/ls/kernel-5.10.y + +obj-m += zte-epc.o +zte-epc-y += pcie-zte-zf-hdma.o pcie-zte-zf-epc.o virt-dma.o + + +all: + make -C $(KDIR) M=$(PWD) modules + +clean: + make -C $(KDIR) M=$(PWD) clean diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/epc/dmaengine.c b/src/net/drivers/net/ethernet/dinghai/zf_mpf/epc/dmaengine.c new file mode 100644 index 0000000..a768da4 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/epc/dmaengine.c @@ -0,0 +1,1636 @@ +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "dmaengine.h" + +static DEFINE_MUTEX(dma_list_mutex); +static DEFINE_IDA(dma_ida); +static LIST_HEAD(dma_device_list); +static long dmaengine_ref_count; + +/* --- debugfs implementation --- */ +#ifdef CONFIG_DEBUG_FS +#include + +static struct dentry *rootdir; + +static void zxdh_dmaengine_debug_register(struct dma_device *dma_dev) +{ + dma_dev->dbg_dev_root = debugfs_create_dir(dev_name(dma_dev->dev), + rootdir); + if (IS_ERR(dma_dev->dbg_dev_root)) + dma_dev->dbg_dev_root = NULL; +} + +static void zxdh_dmaengine_debug_unregister(struct dma_device *dma_dev) +{ + debugfs_remove_recursive(dma_dev->dbg_dev_root); + dma_dev->dbg_dev_root = NULL; +} + +static void zxdh_dmaengine_dbg_summary_show(struct seq_file *s, + struct dma_device *dma_dev) +{ + struct dma_chan *chan; + + list_for_each_entry(chan, &dma_dev->channels, device_node) { + if (chan->client_count) { + seq_printf(s, " %-13s| %s", dma_chan_name(chan), + chan->dbg_client_name ?: "in-use"); + + if (chan->router) + seq_printf(s, " (via router: %s)\n", + dev_name(chan->router->dev)); + else + seq_puts(s, "\n"); + } + } +} + +static int zxdh_dmaengine_summary_show(struct seq_file *s, void *data) +{ + struct dma_device *dma_dev = NULL; + + mutex_lock(&dma_list_mutex); + list_for_each_entry(dma_dev, &dma_device_list, global_node) { + seq_printf(s, "dma%d (%s): number of channels: %u\n", + dma_dev->dev_id, dev_name(dma_dev->dev), + dma_dev->chancnt); + + if (dma_dev->dbg_summary_show) + dma_dev->dbg_summary_show(s, dma_dev); + else + zxdh_dmaengine_dbg_summary_show(s, dma_dev); + + if (!list_is_last(&dma_dev->global_node, &dma_device_list)) + seq_puts(s, "\n"); + } + mutex_unlock(&dma_list_mutex); + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(dmaengine_summary); + +static void __init zxdh_dmaengine_debugfs_init(void) +{ + rootdir = debugfs_create_dir("dmaengine", NULL); + + /* /sys/kernel/debug/dmaengine/summary */ + debugfs_create_file("summary", 0444, rootdir, NULL, + &dmaengine_summary_fops); +} +#else +static inline void zxdh_dmaengine_debugfs_init(void) { } +static inline int zxdh_dmaengine_debug_register(struct dma_device *dma_dev) +{ + return 0; +} + +static inline void zxdh_dmaengine_debug_unregister(struct dma_device *dma_dev) { } +#endif /* DEBUG_FS */ + +/* --- sysfs implementation --- */ + +#define DMA_SLAVE_NAME "slave" + +/** + * zxdh_dev_to_dma_chan - convert a device pointer to its sysfs container object + * @dev: device node + * + * Must be called under dma_list_mutex. + */ +static struct dma_chan *zxdh_dev_to_dma_chan(struct device *dev) +{ + struct dma_chan_dev *chan_dev; + + chan_dev = container_of(dev, typeof(*chan_dev), device); + return chan_dev->chan; +} + +static ssize_t zxdh_memcpy_count_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct dma_chan *chan; + unsigned long count = 0; + int i; + int err; + + mutex_lock(&dma_list_mutex); + chan = zxdh_dev_to_dma_chan(dev); + if (chan) { + for_each_possible_cpu(i) + count += per_cpu_ptr(chan->local, i)->memcpy_count; + err = sprintf(buf, "%lu\n", count); + } else + err = -ENODEV; + mutex_unlock(&dma_list_mutex); + + return err; +} +static DEVICE_ATTR_RO(memcpy_count); + +static ssize_t zxdh_bytes_transferred_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct dma_chan *chan; + unsigned long count = 0; + int i; + int err; + + mutex_lock(&dma_list_mutex); + chan = zxdh_dev_to_dma_chan(dev); + if (chan) { + for_each_possible_cpu(i) + count += per_cpu_ptr(chan->local, i)->bytes_transferred; + err = sprintf(buf, "%lu\n", count); + } else + err = -ENODEV; + mutex_unlock(&dma_list_mutex); + + return err; +} +static DEVICE_ATTR_RO(bytes_transferred); + +static ssize_t zxdh_in_use_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct dma_chan *chan; + int err; + + mutex_lock(&dma_list_mutex); + chan = zxdh_dev_to_dma_chan(dev); + if (chan) + err = sprintf(buf, "%d\n", chan->client_count); + else + err = -ENODEV; + mutex_unlock(&dma_list_mutex); + + return err; +} +static DEVICE_ATTR_RO(in_use); + +static struct attribute *dma_dev_attrs[] = { + &dev_attr_memcpy_count.attr, + &dev_attr_bytes_transferred.attr, + &dev_attr_in_use.attr, + NULL, +}; +ATTRIBUTE_GROUPS(dma_dev); + +static void zxdh_chan_dev_release(struct device *dev) +{ + struct dma_chan_dev *chan_dev; + + chan_dev = container_of(dev, typeof(*chan_dev), device); + kfree(chan_dev); +} + +static struct class dma_devclass = { + .name = "dma", + .dev_groups = dma_dev_groups, + .dev_release = zxdh_chan_dev_release, +}; + +/* --- client and device registration --- */ + +/* enable iteration over all operation types */ +static dma_cap_mask_t dma_cap_mask_all; + +/** + * struct dma_chan_tbl_ent - tracks channel allocations per core/operation + * @chan: associated channel for this entry + */ +struct dma_chan_tbl_ent { + struct dma_chan *chan; +}; + +/* percpu lookup table for memory-to-memory offload providers */ +static struct dma_chan_tbl_ent __percpu *channel_table[DMA_TX_TYPE_END]; + +static int __init zxdh_dma_channel_table_init(void) +{ + enum dma_transaction_type cap; + int err = 0; + + bitmap_fill(dma_cap_mask_all.bits, DMA_TX_TYPE_END); + + /* 'interrupt', 'private', and 'slave' are channel capabilities, + * but are not associated with an operation so they do not need + * an entry in the channel_table + */ + clear_bit(DMA_INTERRUPT, dma_cap_mask_all.bits); + clear_bit(DMA_PRIVATE, dma_cap_mask_all.bits); + clear_bit(DMA_SLAVE, dma_cap_mask_all.bits); + + for_each_dma_cap_mask(cap, dma_cap_mask_all) { + channel_table[cap] = alloc_percpu(struct dma_chan_tbl_ent); + if (!channel_table[cap]) { + err = -ENOMEM; + break; + } + } + + if (err) { + pr_err("dmaengine zxdh_dma_channel_table_init failure: %d\n", err); + for_each_dma_cap_mask(cap, dma_cap_mask_all) + free_percpu(channel_table[cap]); + } + + return err; +} +arch_initcall(zxdh_dma_channel_table_init); + +/** + * zxdh_dma_chan_is_local - checks if the channel is in the same NUMA-node as the CPU + * @chan: DMA channel to test + * @cpu: CPU index which the channel should be close to + * + * Returns true if the channel is in the same NUMA-node as the CPU. + */ +static bool zxdh_dma_chan_is_local(struct dma_chan *chan, int cpu) +{ + int node = dev_to_node(chan->device->dev); + return node == NUMA_NO_NODE || + cpumask_test_cpu(cpu, cpumask_of_node(node)); +} + +/** + * zxdh_min_chan - finds the channel with min count and in the same NUMA-node as the CPU + * @cap: capability to match + * @cpu: CPU index which the channel should be close to + * + * If some channels are close to the given CPU, the one with the lowest + * reference count is returned. Otherwise, CPU is ignored and only the + * reference count is taken into account. + * + * Must be called under dma_list_mutex. + */ +static struct dma_chan *zxdh_min_chan(enum dma_transaction_type cap, int cpu) +{ + struct dma_device *device; + struct dma_chan *chan; + struct dma_chan *min = NULL; + struct dma_chan *localmin = NULL; + + list_for_each_entry(device, &dma_device_list, global_node) { + if (!dma_has_cap(cap, device->cap_mask) || + dma_has_cap(DMA_PRIVATE, device->cap_mask)) + continue; + list_for_each_entry(chan, &device->channels, device_node) { + if (!chan->client_count) + continue; + if (!min || chan->table_count < min->table_count) + min = chan; + + if (zxdh_dma_chan_is_local(chan, cpu)) + if (!localmin || + chan->table_count < localmin->table_count) + localmin = chan; + } + } + + chan = localmin ? localmin : min; + + if (chan) + chan->table_count++; + + return chan; +} + +/** + * zxdh_dma_channel_rebalance - redistribute the available channels + * + * Optimize for CPU isolation (each CPU gets a dedicated channel for an + * operation type) in the SMP case, and operation isolation (avoid + * multi-tasking channels) in the non-SMP case. + * + * Must be called under dma_list_mutex. + */ +static void zxdh_dma_channel_rebalance(void) +{ + struct dma_chan *chan; + struct dma_device *device; + int cpu; + int cap; + + /* undo the last distribution */ + for_each_dma_cap_mask(cap, dma_cap_mask_all) + for_each_possible_cpu(cpu) + per_cpu_ptr(channel_table[cap], cpu)->chan = NULL; + + list_for_each_entry(device, &dma_device_list, global_node) { + if (dma_has_cap(DMA_PRIVATE, device->cap_mask)) + continue; + list_for_each_entry(chan, &device->channels, device_node) + chan->table_count = 0; + } + + /* don't populate the channel_table if no clients are available */ + if (!dmaengine_ref_count) + return; + + /* redistribute available channels */ + for_each_dma_cap_mask(cap, dma_cap_mask_all) + for_each_online_cpu(cpu) { + chan = zxdh_min_chan(cap, cpu); + per_cpu_ptr(channel_table[cap], cpu)->chan = chan; + } +} + +static int zxdh_dma_device_satisfies_mask(struct dma_device *device, + const dma_cap_mask_t *want) +{ + dma_cap_mask_t has; + + bitmap_and(has.bits, want->bits, device->cap_mask.bits, + DMA_TX_TYPE_END); + return bitmap_equal(want->bits, has.bits, DMA_TX_TYPE_END); +} + +static struct module *zxdh_dma_chan_to_owner(struct dma_chan *chan) +{ + return chan->device->owner; +} + +/** + * zxdh_balance_ref_count - catch up the channel reference count + * @chan: channel to balance ->client_count versus dmaengine_ref_count + * + * Must be called under dma_list_mutex. + */ +static void zxdh_balance_ref_count(struct dma_chan *chan) +{ + struct module *owner = zxdh_dma_chan_to_owner(chan); + + while (chan->client_count < dmaengine_ref_count) { + __module_get(owner); + chan->client_count++; + } +} + +static void zxdh_dma_device_release(struct kref *ref) +{ + struct dma_device *device = container_of(ref, struct dma_device, ref); + + list_del_rcu(&device->global_node); + zxdh_dma_channel_rebalance(); + + if (device->device_release) + device->device_release(device); +} + +static void zxdh_dma_device_put(struct dma_device *device) +{ + lockdep_assert_held(&dma_list_mutex); + kref_put(&device->ref, zxdh_dma_device_release); +} + +/** + * zxdh_dma_chan_get - try to grab a DMA channel's parent driver module + * @chan: channel to grab + * + * Must be called under dma_list_mutex. + */ +static int zxdh_dma_chan_get(struct dma_chan *chan) +{ + struct module *owner = zxdh_dma_chan_to_owner(chan); + int ret; + + /* The channel is already in use, update client count */ + if (chan->client_count) { + __module_get(owner); + goto out; + } + + if (!try_module_get(owner)) + return -ENODEV; + + ret = kref_get_unless_zero(&chan->device->ref); + if (!ret) { + ret = -ENODEV; + goto module_put_out; + } + + /* allocate upon first client reference */ + if (chan->device->device_alloc_chan_resources) { + ret = chan->device->device_alloc_chan_resources(chan); + if (ret < 0) + goto err_out; + } + + if (!dma_has_cap(DMA_PRIVATE, chan->device->cap_mask)) + zxdh_balance_ref_count(chan); + +out: + chan->client_count++; + return 0; + +err_out: + zxdh_dma_device_put(chan->device); +module_put_out: + module_put(owner); + return ret; +} + +/** + * zxdh_dma_chan_put - drop a reference to a DMA channel's parent driver module + * @chan: channel to release + * + * Must be called under dma_list_mutex. + */ +static void zxdh_dma_chan_put(struct dma_chan *chan) +{ + /* This channel is not in use, bail out */ + if (!chan->client_count) + return; + + chan->client_count--; + + /* This channel is not in use anymore, free it */ + if (!chan->client_count && chan->device->device_free_chan_resources) { + /* Make sure all operations have completed */ + dmaengine_synchronize(chan); + chan->device->device_free_chan_resources(chan); + } + + /* If the channel is used via a DMA request router, free the mapping */ + if (chan->router && chan->router->route_free) { + chan->router->route_free(chan->router->dev, chan->route_data); + chan->router = NULL; + chan->route_data = NULL; + } + + zxdh_dma_device_put(chan->device); + module_put(zxdh_dma_chan_to_owner(chan)); +} + +enum dma_status zxdh_dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie) +{ + enum dma_status status; + unsigned long zxdh_dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000); + + dma_async_issue_pending(chan); + do { + status = dma_async_is_tx_complete(chan, cookie); + if (time_after_eq(jiffies, zxdh_dma_sync_wait_timeout)) { + dev_err(chan->device->dev, "%s: timeout!\n", __func__); + return DMA_ERROR; + } + if (status != DMA_IN_PROGRESS) + break; + cpu_relax(); + } while (1); + + return status; +} + + +/** + * zxdh_dma_find_channel - find a channel to carry out the operation + * @tx_type: transaction type + */ +struct dma_chan *zxdh_dma_find_channel(enum dma_transaction_type tx_type) +{ + return this_cpu_read(channel_table[tx_type]->chan); +} + + +/** + * zxdh_dma_issue_pending_all - flush all pending operations across all channels + */ +void zxdh_dma_issue_pending_all(void) +{ + struct dma_device *device; + struct dma_chan *chan; + + rcu_read_lock(); + list_for_each_entry_rcu(device, &dma_device_list, global_node) { + if (dma_has_cap(DMA_PRIVATE, device->cap_mask)) + continue; + list_for_each_entry(chan, &device->channels, device_node) + if (chan->client_count) + device->device_issue_pending(chan); + } + rcu_read_unlock(); +} + + +int zxdh_dma_get_slave_caps(struct dma_chan *chan, struct dma_slave_caps *caps) +{ + struct dma_device *device; + + if (!chan || !caps) + return -EINVAL; + + device = chan->device; + + /* check if the channel supports slave transactions */ + if (!(test_bit(DMA_SLAVE, device->cap_mask.bits) || + test_bit(DMA_CYCLIC, device->cap_mask.bits))) + return -ENXIO; + + /* + * Check whether it reports it uses the generic slave + * capabilities, if not, that means it doesn't support any + * kind of slave capabilities reporting. + */ + if (!device->directions) + return -ENXIO; + + caps->src_addr_widths = device->src_addr_widths; + caps->dst_addr_widths = device->dst_addr_widths; + caps->directions = device->directions; + caps->min_burst = device->min_burst; + caps->max_burst = device->max_burst; + caps->max_sg_burst = device->max_sg_burst; + caps->residue_granularity = device->residue_granularity; + caps->descriptor_reuse = device->descriptor_reuse; + caps->cmd_pause = !!device->device_pause; + caps->cmd_resume = !!device->device_resume; + caps->cmd_terminate = !!device->device_terminate_all; + + /* + * DMA engine device might be configured with non-uniformly + * distributed slave capabilities per device channels. In this + * case the corresponding driver may provide the device_caps + * callback to override the generic capabilities with + * channel-specific ones. + */ + if (device->device_caps) + device->device_caps(chan, caps); + + return 0; +} + + +static struct dma_chan *zxdh_private_candidate(const dma_cap_mask_t *mask, + struct dma_device *dev, + dma_filter_fn fn, void *fn_param) +{ + struct dma_chan *chan; + + if (mask && !zxdh_dma_device_satisfies_mask(dev, mask)) { + dev_dbg(dev->dev, "%s: wrong capabilities\n", __func__); + return NULL; + } + /* devices with multiple channels need special handling as we need to + * ensure that all channels are either private or public. + */ + if (dev->chancnt > 1 && !dma_has_cap(DMA_PRIVATE, dev->cap_mask)) + list_for_each_entry(chan, &dev->channels, device_node) { + /* some channels are already publicly allocated */ + if (chan->client_count) + return NULL; + } + + list_for_each_entry(chan, &dev->channels, device_node) { + if (chan->client_count) { + dev_dbg(dev->dev, "%s: %s busy\n", + __func__, dma_chan_name(chan)); + continue; + } + if (fn && !fn(chan, fn_param)) { + dev_dbg(dev->dev, "%s: %s filter said false\n", + __func__, dma_chan_name(chan)); + continue; + } + return chan; + } + + return NULL; +} + +static struct dma_chan *zxdh_find_candidate(struct dma_device *device, + const dma_cap_mask_t *mask, + dma_filter_fn fn, void *fn_param) +{ + struct dma_chan *chan = zxdh_private_candidate(mask, device, fn, fn_param); + int err; + + if (chan) { + /* Found a suitable channel, try to grab, prep, and return it. + * We first set DMA_PRIVATE to disable zxdh_balance_ref_count as this + * channel will not be published in the general-purpose + * allocator + */ + dma_cap_set(DMA_PRIVATE, device->cap_mask); + device->privatecnt++; + err = zxdh_dma_chan_get(chan); + + if (err) { + if (err == -ENODEV) { + dev_dbg(device->dev, "%s: %s module removed\n", + __func__, dma_chan_name(chan)); + list_del_rcu(&device->global_node); + } else + dev_dbg(device->dev, + "%s: failed to get %s: (%d)\n", + __func__, dma_chan_name(chan), err); + + if (--device->privatecnt == 0) + dma_cap_clear(DMA_PRIVATE, device->cap_mask); + + chan = ERR_PTR(err); + } + } + + return chan ? chan : ERR_PTR(-EPROBE_DEFER); +} + +/** + * zxdh_dma_get_slave_channel - try to get specific channel exclusively + * @chan: target channel + */ +struct dma_chan *zxdh_dma_get_slave_channel(struct dma_chan *chan) +{ + int err = -EBUSY; + + /* lock against __zxdh__zxdh_dma_request_channel */ + mutex_lock(&dma_list_mutex); + + if (chan->client_count == 0) { + struct dma_device *device = chan->device; + + dma_cap_set(DMA_PRIVATE, device->cap_mask); + device->privatecnt++; + err = zxdh_dma_chan_get(chan); + if (err) { + dev_dbg(chan->device->dev, + "%s: failed to get %s: (%d)\n", + __func__, dma_chan_name(chan), err); + chan = NULL; + if (--device->privatecnt == 0) + dma_cap_clear(DMA_PRIVATE, device->cap_mask); + } + } else + chan = NULL; + + mutex_unlock(&dma_list_mutex); + + + return chan; +} + + +struct dma_chan *zxdh_dma_get_any_slave_channel(struct dma_device *device) +{ + dma_cap_mask_t mask; + struct dma_chan *chan; + + dma_cap_zero(mask); + dma_cap_set(DMA_SLAVE, mask); + + /* lock against __zxdh__zxdh_dma_request_channel */ + mutex_lock(&dma_list_mutex); + + chan = zxdh_find_candidate(device, &mask, NULL, NULL); + + mutex_unlock(&dma_list_mutex); + + return IS_ERR(chan) ? NULL : chan; +} + + +/** + * __zxdh__zxdh_dma_request_channel - try to allocate an exclusive channel + * @mask: capabilities that the channel must satisfy + * @fn: optional callback to disposition available channels + * @fn_param: opaque parameter to pass to dma_filter_fn() + * @np: device node to look for DMA channels + * + * Returns pointer to appropriate DMA channel on success or NULL. + */ +struct dma_chan *__zxdh__zxdh_dma_request_channel(const dma_cap_mask_t *mask, + dma_filter_fn fn, void *fn_param, + struct device_node *np) +{ + struct dma_device *device, *_d; + struct dma_chan *chan = NULL; + + /* Find a channel */ + mutex_lock(&dma_list_mutex); + list_for_each_entry_safe(device, _d, &dma_device_list, global_node) { + /* Finds a DMA controller with matching device node */ + if (np && device->dev->of_node && np != device->dev->of_node) + continue; + + chan = zxdh_find_candidate(device, mask, fn, fn_param); + if (!IS_ERR(chan)) + break; + + chan = NULL; + } + mutex_unlock(&dma_list_mutex); + + pr_debug("%s: %s (%s)\n", + __func__, + chan ? "success" : "fail", + chan ? dma_chan_name(chan) : NULL); + + return chan; +} + + +static const struct dma_slave_map *zxdh_dma_filter_match(struct dma_device *device, + const char *name, + struct device *dev) +{ + int i; + + if (!device->filter.mapcnt) + return NULL; + + for (i = 0; i < device->filter.mapcnt; i++) { + const struct dma_slave_map *map = &device->filter.map[i]; + + if (!strcmp(map->devname, dev_name(dev)) && + !strcmp(map->slave, name)) + return map; + } + + return NULL; +} + +/** + * zxdh_dma_request_chan - try to allocate an exclusive slave channel + * @dev: pointer to client device structure + * @name: slave channel name + * + * Returns pointer to appropriate DMA channel on success or an error pointer. + */ +struct dma_chan *zxdh_dma_request_chan(struct device *dev, const char *name) +{ + struct dma_device *d, *_d; + struct dma_chan *chan = NULL; + + /* If device-tree is present get slave info from here */ + if (dev->of_node) + chan = of_dma_request_slave_channel(dev->of_node, name); + + /* If device was enumerated by ACPI get slave info from here */ + if (has_acpi_companion(dev) && !chan) + chan = acpi_dma_request_slave_chan_by_name(dev, name); + + if (PTR_ERR(chan) == -EPROBE_DEFER) + return chan; + + if (!IS_ERR_OR_NULL(chan)) + goto found; + + /* Try to find the channel via the DMA filter map(s) */ + mutex_lock(&dma_list_mutex); + list_for_each_entry_safe(d, _d, &dma_device_list, global_node) { + dma_cap_mask_t mask; + const struct dma_slave_map *map = zxdh_dma_filter_match(d, name, dev); + + if (!map) + continue; + + dma_cap_zero(mask); + dma_cap_set(DMA_SLAVE, mask); + + chan = zxdh_find_candidate(d, &mask, d->filter.fn, map->param); + if (!IS_ERR(chan)) + break; + } + mutex_unlock(&dma_list_mutex); + + if (IS_ERR(chan)) + return chan; + if (!chan) + return ERR_PTR(-EPROBE_DEFER); + +found: +#ifdef CONFIG_DEBUG_FS + chan->dbg_client_name = kasprintf(GFP_KERNEL, "%s:%s", dev_name(dev), + name); +#endif + + chan->name = kasprintf(GFP_KERNEL, "dma:%s", name); + if (!chan->name) + return chan; + chan->slave = dev; + + if (sysfs_create_link(&chan->dev->device.kobj, &dev->kobj, + DMA_SLAVE_NAME)) + dev_warn(dev, "Cannot create DMA %s symlink\n", DMA_SLAVE_NAME); + if (sysfs_create_link(&dev->kobj, &chan->dev->device.kobj, chan->name)) + dev_warn(dev, "Cannot create DMA %s symlink\n", chan->name); + + return chan; +} + + +/** + * zxdh_dma_request_chan_by_mask - allocate a channel satisfying certain capabilities + * @mask: capabilities that the channel must satisfy + * + * Returns pointer to appropriate DMA channel on success or an error pointer. + */ +struct dma_chan *zxdh_dma_request_chan_by_mask(const dma_cap_mask_t *mask) +{ + struct dma_chan *chan; + + if (!mask) + return ERR_PTR(-ENODEV); + + chan = __zxdh__zxdh_dma_request_channel(mask, NULL, NULL, NULL); + if (!chan) { + mutex_lock(&dma_list_mutex); + if (list_empty(&dma_device_list)) + chan = ERR_PTR(-EPROBE_DEFER); + else + chan = ERR_PTR(-ENODEV); + mutex_unlock(&dma_list_mutex); + } + + return chan; +} + + +void zxdh_dma_release_channel(struct dma_chan *chan) +{ + mutex_lock(&dma_list_mutex); + WARN_ONCE(chan->client_count != 1, + "chan reference count %d != 1\n", chan->client_count); + zxdh_dma_chan_put(chan); + /* drop PRIVATE cap enabled by __zxdh__zxdh_dma_request_channel() */ + if (--chan->device->privatecnt == 0) + dma_cap_clear(DMA_PRIVATE, chan->device->cap_mask); + + if (chan->slave) { + sysfs_remove_link(&chan->dev->device.kobj, DMA_SLAVE_NAME); + sysfs_remove_link(&chan->slave->kobj, chan->name); + kfree(chan->name); + chan->name = NULL; + chan->slave = NULL; + } + +#ifdef CONFIG_DEBUG_FS + kfree(chan->dbg_client_name); + chan->dbg_client_name = NULL; +#endif + mutex_unlock(&dma_list_mutex); +} + + +/** + * zxdh_dmaengine_get - register interest in dma_channels + */ +void zxdh_dmaengine_get(void) +{ + struct dma_device *device, *_d; + struct dma_chan *chan; + int err; + + mutex_lock(&dma_list_mutex); + dmaengine_ref_count++; + + /* try to grab channels */ + list_for_each_entry_safe(device, _d, &dma_device_list, global_node) { + if (dma_has_cap(DMA_PRIVATE, device->cap_mask)) + continue; + list_for_each_entry(chan, &device->channels, device_node) { + err = zxdh_dma_chan_get(chan); + if (err == -ENODEV) { + /* module removed before we could use it */ + list_del_rcu(&device->global_node); + break; + } else if (err) + dev_dbg(chan->device->dev, + "%s: failed to get %s: (%d)\n", + __func__, dma_chan_name(chan), err); + } + } + + /* if this is the first reference and there were channels + * waiting we need to rebalance to get those channels + * incorporated into the channel table + */ + if (dmaengine_ref_count == 1) + zxdh_dma_channel_rebalance(); + mutex_unlock(&dma_list_mutex); +} + + +/** + * zxdh_dmaengine_put - let DMA drivers be removed when ref_count == 0 + */ +void zxdh_dmaengine_put(void) +{ + struct dma_device *device, *_d; + struct dma_chan *chan; + + mutex_lock(&dma_list_mutex); + dmaengine_ref_count--; + BUG_ON(dmaengine_ref_count < 0); + /* drop channel references */ + list_for_each_entry_safe(device, _d, &dma_device_list, global_node) { + if (dma_has_cap(DMA_PRIVATE, device->cap_mask)) + continue; + list_for_each_entry(chan, &device->channels, device_node) + zxdh_dma_chan_put(chan); + } + mutex_unlock(&dma_list_mutex); +} + + +static bool zxdh_device_has_all_tx_types(struct dma_device *device) +{ + /* A device that satisfies this test has channels that will never cause + * an async_tx channel switch event as all possible operation types can + * be handled. + */ + #ifdef CONFIG_ASYNC_TX_DMA + if (!dma_has_cap(DMA_INTERRUPT, device->cap_mask)) + return false; + #endif + + #if IS_ENABLED(CONFIG_ASYNC_MEMCPY) + if (!dma_has_cap(DMA_MEMCPY, device->cap_mask)) + return false; + #endif + + #if IS_ENABLED(CONFIG_ASYNC_XOR) + if (!dma_has_cap(DMA_XOR, device->cap_mask)) + return false; + + #ifndef CONFIG_ASYNC_TX_DISABLE_XOR_VAL_DMA + if (!dma_has_cap(DMA_XOR_VAL, device->cap_mask)) + return false; + #endif + #endif + + #if IS_ENABLED(CONFIG_ASYNC_PQ) + if (!dma_has_cap(DMA_PQ, device->cap_mask)) + return false; + + #ifndef CONFIG_ASYNC_TX_DISABLE_PQ_VAL_DMA + if (!dma_has_cap(DMA_PQ_VAL, device->cap_mask)) + return false; + #endif + #endif + + return true; +} + +static int zxdh_get_dma_id(struct dma_device *device) +{ + int rc = ida_alloc(&dma_ida, GFP_KERNEL); + + if (rc < 0) + return rc; + device->dev_id = rc; + return 0; +} + +static int __zxdh_dma_async_device_channel_register(struct dma_device *device, + struct dma_chan *chan) +{ + int rc; + + chan->local = alloc_percpu(typeof(*chan->local)); + if (!chan->local) + return -ENOMEM; + chan->dev = kzalloc(sizeof(*chan->dev), GFP_KERNEL); + if (!chan->dev) { + rc = -ENOMEM; + goto err_free_local; + } + + /* + * When the chan_id is a negative value, we are dynamically adding + * the channel. Otherwise we are static enumerating. + */ + mutex_lock(&device->chan_mutex); + chan->chan_id = ida_alloc(&device->chan_ida, GFP_KERNEL); + mutex_unlock(&device->chan_mutex); + if (chan->chan_id < 0) { + pr_err("%s: unable to alloc ida for chan: %d\n", + __func__, chan->chan_id); + rc = chan->chan_id; + goto err_free_dev; + } + + chan->dev->device.class = &dma_devclass; + chan->dev->device.parent = device->dev; + chan->dev->chan = chan; + chan->dev->dev_id = device->dev_id; + dev_set_name(&chan->dev->device, "dma%dchan%d", + device->dev_id, chan->chan_id); + rc = device_register(&chan->dev->device); + if (rc) + goto err_out_ida; + chan->client_count = 0; + device->chancnt++; + + return 0; + + err_out_ida: + mutex_lock(&device->chan_mutex); + ida_free(&device->chan_ida, chan->chan_id); + mutex_unlock(&device->chan_mutex); + err_free_dev: + kfree(chan->dev); + err_free_local: + free_percpu(chan->local); + chan->local = NULL; + return rc; +} + +int zxdh_dma_async_device_channel_register(struct dma_device *device, + struct dma_chan *chan) +{ + int rc; + + rc = __zxdh_dma_async_device_channel_register(device, chan); + if (rc < 0) + return rc; + + zxdh_dma_channel_rebalance(); + return 0; +} + + +static void __zxdh__dma_async_device_channel_unregister(struct dma_device *device, + struct dma_chan *chan) +{ + WARN_ONCE(!device->device_release && chan->client_count, + "%s called while %d clients hold a reference\n", + __func__, chan->client_count); + mutex_lock(&dma_list_mutex); + device->chancnt--; + chan->dev->chan = NULL; + mutex_unlock(&dma_list_mutex); + mutex_lock(&device->chan_mutex); + ida_free(&device->chan_ida, chan->chan_id); + mutex_unlock(&device->chan_mutex); + device_unregister(&chan->dev->device); + free_percpu(chan->local); +} + +void zxdh_dma_async_device_channel_unregister(struct dma_device *device, + struct dma_chan *chan) +{ + __zxdh__dma_async_device_channel_unregister(device, chan); + zxdh_dma_channel_rebalance(); +} + + +/** + * dma_async_device_register - registers DMA devices found + * @device: pointer to &struct dma_device + * + * After calling this routine the structure should not be freed except in the + * device_release() callback which will be called after + * zxdh_dma_async_device_unregister() is called and no further references are taken. + */ +int zxdh_dma_async_device_register(struct dma_device *device) +{ + int rc = 0; + struct dma_chan* chan = NULL; + + DH_LOG_INFO(MODULE_MPF, "enter\n"); + + if (!device) + return -ENODEV; + + /* validate device routines */ + if (!device->dev) { + pr_err("DMAdevice must have dev\n"); + return -EIO; + } + + device->owner = device->dev->driver->owner; + + if (dma_has_cap(DMA_MEMCPY, device->cap_mask) && !device->device_prep_dma_memcpy) { + dev_err(device->dev, + "Device claims capability %s, but op is not defined\n", + "DMA_MEMCPY"); + return -EIO; + } + + if (dma_has_cap(DMA_MEMCPY_SG, device->cap_mask) && !device->device_prep_dma_memcpy_sg) { + dev_err(device->dev, + "Device claims capability %s, but op is not defined\n", + "DMA_MEMCPY_SG"); + return -EIO; + } + + if (dma_has_cap(DMA_XOR, device->cap_mask) && !device->device_prep_dma_xor) { + dev_err(device->dev, + "Device claims capability %s, but op is not defined\n", + "DMA_XOR"); + return -EIO; + } + + if (dma_has_cap(DMA_XOR_VAL, device->cap_mask) && !device->device_prep_dma_xor_val) { + dev_err(device->dev, + "Device claims capability %s, but op is not defined\n", + "DMA_XOR_VAL"); + return -EIO; + } + + if (dma_has_cap(DMA_PQ, device->cap_mask) && !device->device_prep_dma_pq) { + dev_err(device->dev, + "Device claims capability %s, but op is not defined\n", + "DMA_PQ"); + return -EIO; + } + + if (dma_has_cap(DMA_PQ_VAL, device->cap_mask) && !device->device_prep_dma_pq_val) { + dev_err(device->dev, + "Device claims capability %s, but op is not defined\n", + "DMA_PQ_VAL"); + return -EIO; + } + + if (dma_has_cap(DMA_MEMSET, device->cap_mask) && !device->device_prep_dma_memset) { + dev_err(device->dev, + "Device claims capability %s, but op is not defined\n", + "DMA_MEMSET"); + return -EIO; + } + + if (dma_has_cap(DMA_INTERRUPT, device->cap_mask) && !device->device_prep_dma_interrupt) { + dev_err(device->dev, + "Device claims capability %s, but op is not defined\n", + "DMA_INTERRUPT"); + return -EIO; + } + + if (dma_has_cap(DMA_CYCLIC, device->cap_mask) && !device->device_prep_dma_cyclic) { + dev_err(device->dev, + "Device claims capability %s, but op is not defined\n", + "DMA_CYCLIC"); + return -EIO; + } + + if (dma_has_cap(DMA_INTERLEAVE, device->cap_mask) && !device->device_prep_interleaved_dma) { + dev_err(device->dev, + "Device claims capability %s, but op is not defined\n", + "DMA_INTERLEAVE"); + return -EIO; + } + + + if (!device->device_tx_status) { + dev_err(device->dev, "Device tx_status is not defined\n"); + return -EIO; + } + + + if (!device->device_issue_pending) { + dev_err(device->dev, "Device issue_pending is not defined\n"); + return -EIO; + } + + if (!device->device_release) + dev_dbg(device->dev, + "WARN: Device release is not defined so it is not safe to unbind this driver while in use\n"); + + kref_init(&device->ref); + + /* note: this only matters in the + * CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=n case + */ + if (zxdh_device_has_all_tx_types(device)) + dma_cap_set(DMA_ASYNC_TX, device->cap_mask); + + rc = zxdh_get_dma_id(device); + if (rc != 0) + return rc; + + mutex_init(&device->chan_mutex); + ida_init(&device->chan_ida); + + /* represent channels in sysfs. Probably want devs too */ + list_for_each_entry(chan, &device->channels, device_node) { + rc = __zxdh_dma_async_device_channel_register(device, chan); + if (rc < 0) + goto err_out; + } + + mutex_lock(&dma_list_mutex); + /* take references on public channels */ + if (dmaengine_ref_count && !dma_has_cap(DMA_PRIVATE, device->cap_mask)) + list_for_each_entry(chan, &device->channels, device_node) { + /* if clients are already waiting for channels we need + * to take references on their behalf + */ + if (zxdh_dma_chan_get(chan) == -ENODEV) { + /* note we can only get here for the first + * channel as the remaining channels are + * guaranteed to get a reference + */ + rc = -ENODEV; + mutex_unlock(&dma_list_mutex); + goto err_out; + } + } + list_add_tail_rcu(&device->global_node, &dma_device_list); + if (dma_has_cap(DMA_PRIVATE, device->cap_mask)) + device->privatecnt++; /* Always private */ + zxdh_dma_channel_rebalance(); + mutex_unlock(&dma_list_mutex); + + zxdh_dmaengine_debug_register(device); + + return 0; + +err_out: + /* if we never registered a channel just release the idr */ + if (!device->chancnt) { + ida_free(&dma_ida, device->dev_id); + return rc; + } + + list_for_each_entry(chan, &device->channels, device_node) { + if (chan->local == NULL) + continue; + mutex_lock(&dma_list_mutex); + chan->dev->chan = NULL; + mutex_unlock(&dma_list_mutex); + device_unregister(&chan->dev->device); + free_percpu(chan->local); + } + return rc; +} + + +/** + * zxdh_dma_async_device_unregister - unregister a DMA device + * @device: pointer to &struct dma_device + * + * This routine is called by dma driver exit routines, dmaengine holds module + * references to prevent it being called while channels are in use. + */ +void zxdh_dma_async_device_unregister(struct dma_device *device) +{ + struct dma_chan *chan, *n; + + zxdh_dmaengine_debug_unregister(device); + + list_for_each_entry_safe(chan, n, &device->channels, device_node) + __zxdh__dma_async_device_channel_unregister(device, chan); + + mutex_lock(&dma_list_mutex); + /* + * setting DMA_PRIVATE ensures the device being torn down will not + * be used in the channel_table + */ + dma_cap_set(DMA_PRIVATE, device->cap_mask); + zxdh_dma_channel_rebalance(); + ida_free(&dma_ida, device->dev_id); + zxdh_dma_device_put(device); + mutex_unlock(&dma_list_mutex); +} + + +static void zxdh_dmam_device_release(struct device *dev, void *res) +{ + struct dma_device *device; + + device = *(struct dma_device **)res; + zxdh_dma_async_device_unregister(device); +} + +/** + * zxdh_dmaenginem_async_device_register - registers DMA devices found + * @device: pointer to &struct dma_device + * + * The operation is managed and will be undone on driver detach. + */ +int zxdh_dmaenginem_async_device_register(struct dma_device *device) +{ + void *p; + int ret; + + p = devres_alloc(zxdh_dmam_device_release, sizeof(void *), GFP_KERNEL); + if (!p) + return -ENOMEM; + + ret = dma_async_device_register(device); + if (!ret) { + *(struct dma_device **)p = device; + devres_add(device->dev, p); + } else { + devres_free(p); + } + + return ret; +} + + +struct zxdh_dmaengine_unmap_pool { + struct kmem_cache *cache; + const char *name; + mempool_t *pool; + size_t size; +}; + +#define __UNMAP_POOL(x) { .size = x, .name = "dmaengine-unmap-" __stringify(x) } +static struct zxdh_dmaengine_unmap_pool unmap_pool[] = { + __UNMAP_POOL(2), + #if IS_ENABLED(CONFIG_DMA_ENGINE_RAID) + __UNMAP_POOL(16), + __UNMAP_POOL(128), + __UNMAP_POOL(256), + #endif +}; + +static struct zxdh_dmaengine_unmap_pool *__zxdh_get_unmap_pool(int nr) +{ + int order = get_count_order(nr); + + switch (order) { + case 0 ... 1: + return &unmap_pool[0]; +#if IS_ENABLED(CONFIG_DMA_ENGINE_RAID) + case 2 ... 4: + return &unmap_pool[1]; + case 5 ... 7: + return &unmap_pool[2]; + case 8: + return &unmap_pool[3]; +#endif + default: + BUG(); + return NULL; + } +} + +static void zxdh_dmaengine_unmap(struct kref *kref) +{ + struct dmaengine_unmap_data *unmap = container_of(kref, typeof(*unmap), kref); + struct device *dev = unmap->dev; + int cnt, i; + + cnt = unmap->to_cnt; + for (i = 0; i < cnt; i++) + dma_unmap_page(dev, unmap->addr[i], unmap->len, + DMA_TO_DEVICE); + cnt += unmap->from_cnt; + for (; i < cnt; i++) + dma_unmap_page(dev, unmap->addr[i], unmap->len, + DMA_FROM_DEVICE); + cnt += unmap->bidi_cnt; + for (; i < cnt; i++) { + if (unmap->addr[i] == 0) + continue; + dma_unmap_page(dev, unmap->addr[i], unmap->len, + DMA_BIDIRECTIONAL); + } + cnt = unmap->map_cnt; + mempool_free(unmap, __zxdh_get_unmap_pool(cnt)->pool); +} + +void zxdh_dmaengine_unmap_put(struct dmaengine_unmap_data *unmap) +{ + if (unmap) + kref_put(&unmap->kref, zxdh_dmaengine_unmap); +} + + +static void zxdh_dmaengine_destroy_unmap_pool(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(unmap_pool); i++) { + struct zxdh_dmaengine_unmap_pool *p = &unmap_pool[i]; + + mempool_destroy(p->pool); + p->pool = NULL; + kmem_cache_destroy(p->cache); + p->cache = NULL; + } +} + +static int __init zxdh_dmaengine_init_unmap_pool(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(unmap_pool); i++) { + struct zxdh_dmaengine_unmap_pool *p = &unmap_pool[i]; + size_t size; + + size = sizeof(struct dmaengine_unmap_data) + + sizeof(dma_addr_t) * p->size; + + p->cache = kmem_cache_create(p->name, size, 0, + SLAB_HWCACHE_ALIGN, NULL); + if (!p->cache) + break; + p->pool = mempool_create_slab_pool(1, p->cache); + if (!p->pool) + break; + } + + if (i == ARRAY_SIZE(unmap_pool)) + return 0; + + zxdh_dmaengine_destroy_unmap_pool(); + return -ENOMEM; +} + +struct dmaengine_unmap_data * +zxdh_dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags) +{ + struct dmaengine_unmap_data *unmap; + + unmap = mempool_alloc(__zxdh_get_unmap_pool(nr)->pool, flags); + if (!unmap) + return NULL; + + memset(unmap, 0, sizeof(*unmap)); + kref_init(&unmap->kref); + unmap->dev = dev; + unmap->map_cnt = nr; + + return unmap; +} + + +void zxdh_dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx, + struct dma_chan *chan) +{ + tx->chan = chan; + #ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH + spin_lock_init(&tx->lock); + #endif +} + +static inline int zxdh_desc_check_and_set_metadata_mode( + struct dma_async_tx_descriptor *desc, enum dma_desc_metadata_mode mode) +{ + /* Make sure that the metadata mode is not mixed */ + if (!desc->desc_metadata_mode) { + if (dmaengine_is_metadata_mode_supported(desc->chan, mode)) + desc->desc_metadata_mode = mode; + else + return -ENOTSUPP; + } else if (desc->desc_metadata_mode != mode) { + return -EINVAL; + } + + return 0; +} + +int zxdh_dmaengine_desc_attach_metadata(struct dma_async_tx_descriptor *desc, + void *data, size_t len) +{ + int ret; + + if (!desc) + return -EINVAL; + + ret = zxdh_desc_check_and_set_metadata_mode(desc, DESC_METADATA_CLIENT); + if (ret) + return ret; + + if (!desc->metadata_ops || !desc->metadata_ops->attach) + return -ENOTSUPP; + + return desc->metadata_ops->attach(desc, data, len); +} + + +void *zxdh_dmaengine_desc_get_metadata_ptr(struct dma_async_tx_descriptor *desc, + size_t *payload_len, size_t *max_len) +{ + int ret; + + if (!desc) + return ERR_PTR(-EINVAL); + + ret = zxdh_desc_check_and_set_metadata_mode(desc, DESC_METADATA_ENGINE); + if (ret) + return ERR_PTR(ret); + + if (!desc->metadata_ops || !desc->metadata_ops->get_ptr) + return ERR_PTR(-ENOTSUPP); + + return desc->metadata_ops->get_ptr(desc, payload_len, max_len); +} + + +int zxdh_dmaengine_desc_set_metadata_len(struct dma_async_tx_descriptor *desc, + size_t payload_len) +{ + int ret; + + if (!desc) + return -EINVAL; + + ret = zxdh_desc_check_and_set_metadata_mode(desc, DESC_METADATA_ENGINE); + if (ret) + return ret; + + if (!desc->metadata_ops || !desc->metadata_ops->set_len) + return -ENOTSUPP; + + return desc->metadata_ops->set_len(desc, payload_len); +} + + +/** + * zxdh_dma_wait_for_async_tx - spin wait for a transaction to complete + * @tx: in-flight transaction to wait on + */ +enum dma_status +zxdh_dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx) +{ + unsigned long zxdh_dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000); + + if (!tx) + return DMA_COMPLETE; + + while (tx->cookie == -EBUSY) { + if (time_after_eq(jiffies, zxdh_dma_sync_wait_timeout)) { + dev_err(tx->chan->device->dev, + "%s timeout waiting for descriptor submission\n", + __func__); + return DMA_ERROR; + } + cpu_relax(); + } + return zxdh_dma_sync_wait(tx->chan, tx->cookie); +} + + +/** + * zxdh_dma_run_dependencies - process dependent operations on the target channel + * @tx: transaction with dependencies + * + * Helper routine for DMA drivers to process (start) dependent operations + * on their target channel. + */ +void zxdh_dma_run_dependencies(struct dma_async_tx_descriptor *tx) +{ + struct dma_async_tx_descriptor *dep = txd_next(tx); + struct dma_async_tx_descriptor *dep_next; + struct dma_chan *chan; + + if (!dep) + return; + + /* we'll submit tx->next now, so clear the link */ + txd_clear_next(tx); + chan = dep->chan; + + /* keep submitting up until a channel switch is detected + * in that case we will be called again as a result of + * processing the interrupt from async_tx_channel_switch + */ + for (; dep; dep = dep_next) { + txd_lock(dep); + txd_clear_parent(dep); + dep_next = txd_next(dep); + if (dep_next && dep_next->chan == chan) + txd_clear_next(dep); /* ->next will be submitted */ + else + dep_next = NULL; /* submit current dep and terminate */ + txd_unlock(dep); + + dep->tx_submit(dep); + } + + chan->device->device_issue_pending(chan); +} + + +static int __init zxdh_dma_bus_init(void) +{ + int err = zxdh_dmaengine_init_unmap_pool(); + + if (err) + return err; + + err = class_register(&dma_devclass); + if (!err) + zxdh_dmaengine_debugfs_init(); + + return err; +} +arch_initcall(zxdh_dma_bus_init); diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/epc/dmaengine.h b/src/net/drivers/net/ethernet/dinghai/zf_mpf/epc/dmaengine.h new file mode 100644 index 0000000..5fc8b18 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/epc/dmaengine.h @@ -0,0 +1,205 @@ +#ifndef ZXDH_DMAENGINE_H +#define ZXDH_DMAENGINE_H + +#include +#include + + +/** + * zxdh_dma_cookie_init - initialize the cookies for a DMA channel + * @chan: dma channel to initialize + */ +static inline void zxdh_dma_cookie_init(struct dma_chan *chan) +{ + chan->cookie = DMA_MIN_COOKIE; + chan->completed_cookie = DMA_MIN_COOKIE; +} + +/** + * zxdh_dma_cookie_assign - assign a DMA engine cookie to the descriptor + * @tx: descriptor needing cookie + * + * Assign a unique non-zero per-channel cookie to the descriptor. + * Note: caller is expected to hold a lock to prevent concurrency. + */ +static inline dma_cookie_t zxdh_dma_cookie_assign(struct dma_async_tx_descriptor *tx) +{ + struct dma_chan *chan = tx->chan; + dma_cookie_t cookie; + + cookie = chan->cookie + 1; + if (cookie < DMA_MIN_COOKIE) + cookie = DMA_MIN_COOKIE; + tx->cookie = chan->cookie = cookie; + + return cookie; +} + +/** + * zxdh_dma_cookie_complete - complete a descriptor + * @tx: descriptor to complete + * + * Mark this descriptor complete by updating the channels completed + * cookie marker. Zero the descriptors cookie to prevent accidental + * repeated completions. + * + * Note: caller is expected to hold a lock to prevent concurrency. + */ +static inline void zxdh_dma_cookie_complete(struct dma_async_tx_descriptor *tx) +{ + BUG_ON(tx->cookie < DMA_MIN_COOKIE); + tx->chan->completed_cookie = tx->cookie; + tx->cookie = 0; +} + +/** + * zxdh_dma_cookie_status - report cookie status + * @chan: dma channel + * @cookie: cookie we are interested in + * @state: dma_tx_state structure to return last/used cookies + * + * Report the status of the cookie, filling in the state structure if + * non-NULL. No locking is required. + */ +static inline enum dma_status zxdh_dma_cookie_status(struct dma_chan *chan, + dma_cookie_t cookie, struct dma_tx_state *state) +{ + dma_cookie_t used, complete; + + used = chan->cookie; + complete = chan->completed_cookie; + barrier(); + if (state) { + state->residue = 0; + state->in_flight_bytes = 0; + } + + if (complete <= used) { + if ((cookie <= complete) || (cookie > used)) + return DMA_COMPLETE; + } else { + if ((cookie <= complete) && (cookie > used)) + return DMA_COMPLETE; + } + return DMA_IN_PROGRESS; +} + +static inline void zxdh_dma_set_residue(struct dma_tx_state *state, u32 residue) +{ + if (state) + state->residue = residue; +} + +static inline void zxdh_dma_set_in_flight_bytes(struct dma_tx_state *state, + u32 in_flight_bytes) +{ + if (state) + state->in_flight_bytes = in_flight_bytes; +} + +struct zxdh_dmaengine_desc_callback { + dma_async_tx_callback callback; + dma_async_tx_callback_result callback_result; + void *callback_param; +}; + +/** + * zxdh_dmaengine_desc_get_callback - get the passed in callback function + * @tx: tx descriptor + * @cb: temp struct to hold the callback info + * + * Fill the passed in cb struct with what's available in the passed in + * tx descriptor struct + * No locking is required. + */ +static inline void +zxdh_dmaengine_desc_get_callback(struct dma_async_tx_descriptor *tx, + struct zxdh_dmaengine_desc_callback *cb) +{ + cb->callback = tx->callback; + cb->callback_result = tx->callback_result; + cb->callback_param = tx->callback_param; +} + +/** + * zxdh_dmaengine_desc_callback_invoke - call the callback function in cb struct + * @cb: temp struct that is holding the callback info + * @result: transaction result + * + * Call the callback function provided in the cb struct with the parameter + * in the cb struct. + * Locking is dependent on the driver. + */ +static inline void +zxdh_dmaengine_desc_callback_invoke(struct zxdh_dmaengine_desc_callback *cb, + const struct dmaengine_result *result) +{ + struct dmaengine_result dummy_result = { + .result = DMA_TRANS_NOERROR, + .residue = 0 + }; + + if (cb->callback_result) { + if (!result) + result = &dummy_result; + cb->callback_result(cb->callback_param, result); + } else if (cb->callback) { + cb->callback(cb->callback_param); + } +} + +/** + * zxdh_dmaengine_desc_get_callback_invoke - get the callback in tx descriptor and + * then immediately call the callback. + * @tx: dma async tx descriptor + * @result: transaction result + * + * Call zxdh_dmaengine_desc_get_callback() and zxdh_dmaengine_desc_callback_invoke() + * in a single function since no work is necessary in between for the driver. + * Locking is dependent on the driver. + */ +static inline void +zxdh_dmaengine_desc_get_callback_invoke(struct dma_async_tx_descriptor *tx, + const struct dmaengine_result *result) +{ + struct zxdh_dmaengine_desc_callback cb; + + zxdh_dmaengine_desc_get_callback(tx, &cb); + zxdh_dmaengine_desc_callback_invoke(&cb, result); +} + +/** + * zxdh_dmaengine_desc_callback_valid - verify the callback is valid in cb + * @cb: callback info struct + * + * Return a bool that verifies whether callback in cb is valid or not. + * No locking is required. + */ +static inline bool +zxdh_dmaengine_desc_callback_valid(struct zxdh_dmaengine_desc_callback *cb) +{ + return cb->callback || cb->callback_result; +} + +struct dma_chan *zxdh_dma_get_slave_channel(struct dma_chan *chan); +struct dma_chan *zxdh_dma_get_any_slave_channel(struct dma_device *device); +void zxdh_dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx, + struct dma_chan *chan); + +#ifdef CONFIG_DEBUG_FS +#include + +static inline struct dentry * +zxdh_zxdh_dmaengine_get_debugfs_root(struct dma_device *dma_dev) { + return dma_dev->dbg_dev_root; +} +#else +struct dentry; +static inline struct dentry * +zxdh_zxdh_dmaengine_get_debugfs_root(struct dma_device *dma_dev) +{ + return NULL; +} +#endif /* CONFIG_DEBUG_FS */ + +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/epc/pcie-zte-zf-epc.c b/src/net/drivers/net/ethernet/dinghai/zf_mpf/epc/pcie-zte-zf-epc.c new file mode 100644 index 0000000..7125e82 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/epc/pcie-zte-zf-epc.c @@ -0,0 +1,1647 @@ +#include "pcie-zte-zf-epc.h" +#include "pcie-zte-zf-hdma.h" + +struct pcie_zf_ep *zf_ep = NULL; + +// PRE_FUNC +#if 1 +int pcie_zf_read(void __iomem *addr, int size, u32 *val) +{ + *val = 0; + if (!IS_ALIGNED((unsigned long)addr, size)) + return PCIBIOS_BAD_REGISTER_NUMBER; + + if (size == 4) + *val = readl(addr); + else if (size == 2) + *val = readw(addr); + else if (size == 1) + *val = readb(addr); + else + return PCIBIOS_BAD_REGISTER_NUMBER; + + return PCIBIOS_SUCCESSFUL; +} +int pcie_zf_write(void __iomem *addr, int size, u32 val) +{ + if (!IS_ALIGNED((unsigned long)addr, size)) + return PCIBIOS_BAD_REGISTER_NUMBER; + + if (size == 4) + writel(val, addr); + else if (size == 2) + writew(val, addr); + else if (size == 1) + writeb(val, addr); + else + return PCIBIOS_BAD_REGISTER_NUMBER; + + return PCIBIOS_SUCCESSFUL; +} +u32 cfg_phy_rmw(u64 phy_addr, u32 value, u32 mask) +{ + u32 reg_val = 0; + void __iomem *virt_addr = NULL; + u64 tmp_addr = 0; + u64 offset = 0; + u64 size = 0; + int ret = 0; + + offset = phy_addr % PAGE_SIZE; + if (phy_addr < offset) + { + DH_LOG_ERR(MODULE_MPF, "data overflow! phy_addr=0x%llx, offset=0x%llx\n", phy_addr, offset); + return PCIBIOS_BAD_REGISTER_NUMBER; + } + else + { + tmp_addr = phy_addr - offset; + } + if (offset <= (PAGE_SIZE - 4)) + { + size = PAGE_SIZE; + } + else + { + size = 2 * PAGE_SIZE; + } + + virt_addr = ioremap(tmp_addr, size); + if (NULL == virt_addr) + { + DH_LOG_ERR(MODULE_MPF, "cfg_phy_rmw ioremap failed!\n"); + return PCIBIOS_BAD_REGISTER_NUMBER; + } + + ret = pcie_zf_read((virt_addr + offset), 4, ®_val); + if (ret) + goto err; + + reg_val &= (~mask); + reg_val |= (value & mask); + + ret = pcie_zf_write(virt_addr + offset, 4, reg_val); +err: + iounmap(virt_addr); + return ret; +} + +u8 pcie_zf_readb_dbi(struct pcie_dpu_ep *ep, u32 reg) +{ + u32 val = 0; + + pcie_zf_read(ep->dbi_base + reg, 0x1, &val); + + return val; +} + +u16 pcie_zf_readw_dbi(struct pcie_dpu_ep *ep, u32 reg) +{ + int ret; + u32 val; + + ret = pcie_zf_read(ep->dbi_base + reg, 0x2, &val); + if (ret) + DH_LOG_ERR(MODULE_MPF, "Read DBIw address failed\r\n"); + + return val; +} +u32 pcie_zf_readl_dbi(struct pcie_dpu_ep *ep, u32 reg) +{ + int ret = 0; + u32 val = 0; + + ret = pcie_zf_read(ep->dbi_base + reg, 0x4, &val); + if (ret) + DH_LOG_ERR(MODULE_MPF, "Read DBIl address failed\r\n"); + + return val; +} + +void pcie_zf_writeb_dbi(struct pcie_dpu_ep *ep, u32 reg, u32 val) +{ + pcie_zf_write(ep->dbi_base + reg, 0x1, val); +} + +void pcie_zf_writew_dbi(struct pcie_dpu_ep *ep, u32 reg, u32 val) +{ + int ret = 0; + + ret = pcie_zf_write(ep->dbi_base + reg, 0x2, val); + if (ret) + DH_LOG_ERR(MODULE_MPF, "Write DBI address failed\r\n"); +} +void pcie_zf_writel_dbi(struct pcie_dpu_ep *ep, u32 reg, u32 val) +{ + int ret = 0; + + ret = pcie_zf_write(ep->dbi_base + reg, 0x4, val); + if (ret) + DH_LOG_ERR(MODULE_MPF, "Write DBI address failed\r\n"); +} + +void pcie_zf_writeb_dbi2(struct pcie_dpu_ep *ep, u32 reg, u32 val) +{ + pcie_zf_write(ep->dbi_base + PCIE_DPU_EP_DBI2_OFFSET + reg, 0x1, val); +} + +void pcie_zf_writew_dbi2(struct pcie_dpu_ep *ep, u32 reg, u32 val) +{ + int ret = 0; + + ret = pcie_zf_write(ep->dbi_base + PCIE_DPU_EP_DBI2_OFFSET + reg, 0x2, val); + if (ret) + DH_LOG_ERR(MODULE_MPF, "Write DBI address failed\r\n"); +} +void pcie_zf_writel_dbi2(struct pcie_dpu_ep *ep, u32 reg, u32 val) +{ + int ret; + + ret = pcie_zf_write(ep->dbi_base + PCIE_DPU_EP_DBI2_OFFSET + reg, 0x4, val); + if (ret) + DH_LOG_ERR(MODULE_MPF, "Write DBI address failed\r\n"); +} +void pcie_zf_writel_atu(struct pcie_dpu_ep *ep, u32 reg, u32 val) +{ + int ret = 0; + + ret = pcie_zf_write(ep->atu_base + reg, 0x4, val); + if (ret) + DH_LOG_ERR(MODULE_MPF, "Write ATU address failed\r\n"); +} +static u32 pcie_zf_readl_atu(struct pcie_dpu_ep *ep, u32 reg) +{ + int ret = 0; + u32 val = 0; + + ret = pcie_zf_read(ep->atu_base + reg, 4, &val); + if (ret) + DH_LOG_ERR(MODULE_MPF, "Read ATU address failed\r\n"); + + return val; +} +static u64 zte_pcie_dma_atu_addr_remapping(u64 addr_input) +{ + u64 addr_output = 0; + // DMA and ATU地址重映射，将地址的bit12~18左移4位，设置bit15 = 0 + addr_output = (((addr_input & (0x7F << 12)) << 4) | (addr_input & 0xFFF)) & (~(1 << 15)); + + return addr_output; +} +static u32 pcie_zf_readl_ib_unroll(struct pcie_dpu_ep *ep, u32 index, u32 reg) +{ + u32 offset = zte_pcie_dma_atu_addr_remapping(PCIE_GET_ATU_INB_UNR_REG_OFFSET(index)); + + return pcie_zf_readl_atu(ep, offset + reg); +} +static void pcie_zf_writel_ib_unroll(struct pcie_dpu_ep *ep, u32 index, u32 reg, u32 val) +{ + u32 offset = zte_pcie_dma_atu_addr_remapping(PCIE_GET_ATU_INB_UNR_REG_OFFSET(index)); + + pcie_zf_writel_atu(ep, offset + reg, val); +} +static u32 pcie_zf_readl_ob_unroll(struct pcie_dpu_ep *ep, u32 index, u32 reg) +{ + u32 offset = zte_pcie_dma_atu_addr_remapping(PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index)); + + return pcie_zf_readl_atu(ep, offset + reg); +} +static void pcie_zf_writel_ob_unroll(struct pcie_dpu_ep *ep, u32 index, u32 reg, u32 val) +{ + u32 offset = zte_pcie_dma_atu_addr_remapping(PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index)); + + pcie_zf_writel_atu(ep, offset + reg, val); +} +static void pcie_zf_dbi_ro_wr_en(struct pcie_dpu_ep *ep) +{ + u64 reg = 0; + u32 val = 0; + + reg = PCIE_MISC_CONTROL_1_OFF; + val = pcie_zf_readl_dbi(ep, reg); + val |= PCIE_DBI_RO_WR_EN; + pcie_zf_writel_dbi(ep, reg, val); +} +static void pcie_zf_dbi_ro_wr_dis(struct pcie_dpu_ep *ep) +{ + u64 reg = 0; + u32 val = 0; + + reg = PCIE_MISC_CONTROL_1_OFF; + val = pcie_zf_readl_dbi(ep, reg); + val &= ~PCIE_DBI_RO_WR_EN; + pcie_zf_writel_dbi(ep, reg, val); +} +static void pcie_dpu_ep_sriov_enable(struct pcie_dpu_ep *ep, u64 sriov_ecap_offset) +{ + u32 val = pcie_zf_readl_dbi(ep, sriov_ecap_offset + PCIE_SRIOV_CTRL); + val |= PCIE_SRIOV_CTRL_VFE; + pcie_zf_writel_dbi(ep, sriov_ecap_offset + PCIE_SRIOV_CTRL, val); +} +static void pcie_dpu_ep_sriov_disable(struct pcie_dpu_ep *ep, u64 sriov_ecap_offset) +{ + u32 val = pcie_zf_readl_dbi(ep, sriov_ecap_offset + PCIE_SRIOV_CTRL); + val &= ~PCIE_SRIOV_CTRL_VFE; + pcie_zf_writel_dbi(ep, sriov_ecap_offset + PCIE_SRIOV_CTRL, val); +} +struct pcie_dpu_ep_func *pcie_dpu_ep_get_func_from_ep(struct pcie_dpu_ep *ep, u8 func_no, u8 vfunc_no) +{ + struct pcie_dpu_ep_func *ep_func = NULL; + + list_for_each_entry(ep_func, &ep->func_list, list) + { + if (ep_func->func_no == func_no && ep_func->vfunc_no == vfunc_no) + return ep_func; + } + + return NULL; +} +static u32 pcie_dpu_ep_func_select(u8 func_no, u8 vfunc_no) +{ + u32 func_offset = 0; + + if (isPF(func_no)) + { + func_offset = func_no & PCIE_DPU_EP_GET_PF_NO; + } + else + { + func_offset = (func_no & PCIE_DPU_EP_GET_PF_NO) + (vfunc_no << DBI_VF_CFG_OFFSET_BIT) + VF_ACT_BIT; + } + + return func_offset * PCIE_DPU_EP_FUNC_CFG_SIZE; +} +static u8 pcie_dpu_ep_find_next_cap(struct pcie_dpu_ep *ep, + u32 func_offset, u8 cap_ptr, u8 capid) +{ + u8 now_cap_id = 0, next_cap_ptr = 0; + u16 reg = 0; + + if (!cap_ptr) + return 0; + + reg = pcie_zf_readl_dbi(ep, func_offset + cap_ptr); + now_cap_id = (reg & 0x00ff); + + if (now_cap_id > PCI_CAP_ID_MAX) + return 0; + + if (now_cap_id == capid) + return cap_ptr; + + next_cap_ptr = (reg & 0xff00) >> 8; + return pcie_dpu_ep_find_next_cap(ep, func_offset, next_cap_ptr, capid); +} +static u8 pcie_dpu_ep_find_cap(struct pcie_dpu_ep *ep, u32 func_offset, u8 capid) +{ + u8 next_cap_ptr = 0; + u16 reg = 0; + + reg = pcie_zf_readl_dbi(ep, func_offset + PCI_CAPABILITY_LIST); + next_cap_ptr = (reg & 0x00ff); + + return pcie_dpu_ep_find_next_cap(ep, func_offset, next_cap_ptr, capid); +} +static int pcie_dpu_ep_find_extcap(struct pcie_dpu_ep *ep, u32 func_offset, u8 ext_cap_id, u8 vsecid) +{ + u32 now_cap_id = 0; + u32 vsec_id = 0; + u32 ext_cap_offset = PCIE_ECAP_POINTER_OFF; + + now_cap_id = pcie_zf_readl_dbi(ep, func_offset + ext_cap_offset); + if (now_cap_id == 0x0 || now_cap_id == 0xFFFF) + { + DH_LOG_ERR(MODULE_MPF, "pcie_zf_ep get extcap0 failed!\n"); + return -ENXIO; + } + + while (1) + { + if ((now_cap_id & 0xFFFF) == ext_cap_id) + { + if (ext_cap_id == PCIE_ECAP_VSEC_ID) + { + vsec_id = pcie_zf_readl_dbi(ep, func_offset + ext_cap_offset + 4); + if (vsec_id == vsecid) + { + break; + } + } + else + { + break; + } + } + + ext_cap_offset = (now_cap_id >> 20) & 0xFFF; + if (0x0 == ext_cap_offset) + { + DH_LOG_ERR(MODULE_MPF, "pcie_zf_ep find extcap failed\n"); + return -ENXIO; + } + + now_cap_id = pcie_zf_readl_dbi(ep, func_offset + ext_cap_offset); + } + + return ext_cap_offset; +} + +static int zf_atu_is_used(struct pcie_dpu_ep *ep, int ib_no) +{ + return (pcie_zf_readl_ib_unroll(ep, ib_no, PCIE_ATU_UNR_REGION_CTRL2) & PCIE_ATU_ENABLE) ? 1 : 0; +} + +static int zf_func_is_set_ib(struct pcie_dpu_ep *ep, u8 func_no, enum pci_barno bar, int ib_no) +{ + int func_val = 0, bar_val = 0; + int ctl1_val = pcie_zf_readl_ib_unroll(ep, ib_no, PCIE_ATU_UNR_REGION_CTRL1); + int ctl2_val = pcie_zf_readl_ib_unroll(ep, ib_no, PCIE_ATU_UNR_REGION_CTRL2); + + func_val = PCIE_ATU_FUNC_NUM(func_no & PCIE_DPU_EP_GET_PF_NO); + if ((ctl1_val & PCIE_ATU_FUNC_NUM_MASK) != func_val) + return 0; + + if (isPF(func_no)) + { + if (ctl2_val & PCIE_ATU_VFBAR_MATCH_MODE_ENABLE) + return 0; + } + else + { + if (!(ctl2_val & PCIE_ATU_VFBAR_MATCH_MODE_ENABLE)) + return 0; + } + bar_val = (bar << 8); + return ((ctl2_val & PCIE_ATU_BAR_NUM_MASK) == bar_val); +} + +static int pcie_zf_prog_inbound_atu(struct pcie_dpu_ep *ep, u8 func_no, int index, int bar, dma_addr_t dpu_addr, enum pcie_dpu_as_type as_type) +{ + int type = 0; + u32 retries = 0, val = 0; + int vf_flag = 0; + + dpu_addr = dpu_addr | ZF_PREFIX_ADDR; // dpu addr route + + if (!isPF(func_no)) + { + vf_flag = 1; + } + + pcie_zf_writel_ib_unroll(ep, index, PCIE_ATU_UNR_LOWER_TARGET, lower_32_bits(dpu_addr)); + pcie_zf_writel_ib_unroll(ep, index, PCIE_ATU_UNR_UPPER_TARGET, upper_32_bits(dpu_addr)); + + switch (as_type) + { + case PCIE_DPU_AS_MEM: + type = PCIE_ATU_TYPE_MEM; + break; + case PCIE_DPU_AS_IO: + if (vf_flag == 1) + { + return -EINVAL; + } + type = PCIE_ATU_TYPE_IO; + break; + default: + return -EINVAL; + } + + pcie_zf_writel_ib_unroll(ep, index, PCIE_ATU_UNR_REGION_CTRL1, type | PCIE_ATU_INCREASE_REGION_SIZE | PCIE_ATU_FUNC_NUM(func_no & PCIE_DPU_EP_GET_PF_NO)); + if (vf_flag) + { + pcie_zf_writel_ib_unroll(ep, index, PCIE_ATU_UNR_REGION_CTRL2, + PCIE_ATU_FUNC_NUM_MATCH_EN | + PCIE_ATU_ENABLE | + PCIE_ATU_VFBAR_MATCH_MODE_ENABLE | + PCIE_ATU_BAR_MODE_ENABLE | (bar << 8)); + } + else + { + pcie_zf_writel_ib_unroll(ep, index, PCIE_ATU_UNR_REGION_CTRL2, + PCIE_ATU_FUNC_NUM_MATCH_EN | + PCIE_ATU_ENABLE | + PCIE_ATU_BAR_MODE_ENABLE | (bar << 8)); + } + + /* + * Make sure ATU enable takes effect before any subsequent config + * and I/O accesses. + */ + for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) + { + val = pcie_zf_readl_ib_unroll(ep, index, PCIE_ATU_UNR_REGION_CTRL2); + if (val & PCIE_ATU_ENABLE) + return 0; + + mdelay((u32)LINK_WAIT_IATU); + } + DH_LOG_ERR(MODULE_MPF, "Inbound iATU is not being enabled\r\n"); + + return -EBUSY; +} + +static int pcie_dpu_ep_inbound_atu(struct pcie_dpu_ep *ep, u8 func_no, enum pci_barno bar, dma_addr_t dpu_addr, enum pcie_dpu_as_type as_type) +{ + int ret = 0, free_win = -1, atu_id = 0; + u32 vf_bar_off = 0; + u32 is_pf = 0; + u32 bar_to_atu_index = 0; + + if ((func_no & PCIE_DPU_EP_GET_PF_NO) >= PCIE_DPU_PF_NUMS) + { + DH_LOG_ERR(MODULE_MPF, "func_no is err!\n"); + return -EINVAL; + } + + is_pf = isPF(func_no); + if (!is_pf) + { + vf_bar_off = PCIE_VF_BARS_OFF; + } + + spin_lock(&ep->ib_window_lock); + for (atu_id = 0; atu_id < PCIE_DPU_IATU_NUM; atu_id++) + { + if (zf_func_is_set_ib(ep, func_no, bar, atu_id)) + { + free_win = atu_id; + break; + } + } + + if (-1 == free_win) + { + free_win = find_first_zero_bit(ep->ib_window_map, ep->num_ib_windows); + if (free_win >= ep->num_ib_windows) + { + spin_unlock(&ep->ib_window_lock); + DH_LOG_ERR(MODULE_MPF, "No free inbound window\r\n"); + return -EINVAL; + } + } + set_bit(free_win, ep->ib_window_map); + + ret = pcie_zf_prog_inbound_atu(ep, func_no, free_win, bar, dpu_addr, as_type); + spin_unlock(&ep->ib_window_lock); + if (ret < 0) + { + DH_LOG_ERR(MODULE_MPF, "Failed to program IB window\r\n"); + return ret; + } + DH_LOG_INFO(MODULE_MPF, "ep%d func%d bar%d set aitu%d\n", ep->ep_id, func_no, bar, free_win); + + bar_to_atu_index = (u32)bar + vf_bar_off; + if (bar_to_atu_index < (PCI_STD_NUM_BARS * 2 + 1)) + { + ep->bar_to_atu[func_no & PCIE_DPU_EP_GET_PF_NO][bar_to_atu_index] = free_win; + } + else + { + DH_LOG_ERR(MODULE_MPF, "error bar_to_atu index %d\r\n", bar_to_atu_index); + return -EINVAL; + } + + return 0; +} + +static void pcie_zf_prog_outbound_atu(struct pcie_dpu_ep *ep, u8 func_no, u8 vfunc_no, int index, int type, u64 dpu_addr, u64 host_addr, size_t size) +{ + u32 retries = 0, val = 0; + u64 limit_addr = 0; + u64 limit_addr_tmp = 0; + + if (size == 0) + { + DH_LOG_ERR(MODULE_MPF, "data error! dpu_addr=0x%llx, size=0x%lx\r\n", dpu_addr, size); + return; + } + else + { + limit_addr_tmp = ULLONG_MAX - size + 1; + if (dpu_addr > limit_addr_tmp) + { + DH_LOG_ERR(MODULE_MPF, "data overflow!\r\n"); + return; + } + limit_addr = dpu_addr + size - 1; + } + + pcie_zf_writel_ob_unroll(ep, index, PCIE_ATU_UNR_LOWER_BASE, lower_32_bits(dpu_addr)); + pcie_zf_writel_ob_unroll(ep, index, PCIE_ATU_UNR_UPPER_BASE, upper_32_bits(dpu_addr)); + pcie_zf_writel_ob_unroll(ep, index, PCIE_ATU_UNR_LOWER_LIMIT, lower_32_bits(limit_addr)); + pcie_zf_writel_ob_unroll(ep, index, PCIE_ATU_UNR_UPPER_LIMIT, upper_32_bits(limit_addr)); + pcie_zf_writel_ob_unroll(ep, index, PCIE_ATU_UNR_LOWER_TARGET, lower_32_bits(host_addr)); + pcie_zf_writel_ob_unroll(ep, index, PCIE_ATU_UNR_UPPER_TARGET, upper_32_bits(host_addr)); + pcie_zf_writel_ob_unroll(ep, index, PCIE_ATU_UNR_REGION_CTRL1, + type | PCIE_ATU_FUNC_NUM(func_no & PCIE_DPU_EP_GET_PF_NO)); + + if (type == 4 || type == 5) + { + pcie_zf_writel_ob_unroll(ep, index, PCIE_ATU_UNR_REGION_CTRL2, PCIE_ATU_ENABLE | PCIE_ATU_CFG_SHIFT_MODE | PCIE_ATU_DMA_BYPSS); + } + else + { + pcie_zf_writel_ob_unroll(ep, index, PCIE_ATU_UNR_REGION_CTRL2, PCIE_ATU_ENABLE | PCIE_ATU_DMA_BYPSS); + } + + if (isPF(func_no)) + { + pcie_zf_writel_ob_unroll(ep, index, PCIE_ATU_UNR_REGION_CTRL3, 0x0); + } + else + { + pcie_zf_writel_ob_unroll(ep, index, PCIE_ATU_UNR_REGION_CTRL3, PCIE_ATU_OB_VF_ACTIVE | vfunc_no); + } + + /* + * Make sure ATU enable takes effect before any subsequent config + * and I/O accesses. + */ + for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) + { + val = pcie_zf_readl_ob_unroll(ep, index, PCIE_ATU_UNR_REGION_CTRL2); + if (val & PCIE_ATU_ENABLE) + return; + + mdelay((u32)LINK_WAIT_IATU); + } + DH_LOG_ERR(MODULE_MPF, "Outbound iATU is not being enabled\r\n"); +} + +static int pcie_dpu_ep_outbound_atu(struct pcie_dpu_ep *ep, u8 func_no, u8 vfunc_no, phys_addr_t dpu_offset, u64 host_addr, size_t size) +{ + u32 free_win = 0; + + free_win = find_first_zero_bit(ep->ob_window_map, ep->num_ob_windows); + if (free_win >= ep->num_ob_windows) + { + DH_LOG_ERR(MODULE_MPF, "No free outbound window\r\n"); + return -EINVAL; + } + + pcie_zf_prog_outbound_atu(ep, func_no, vfunc_no, free_win, PCIE_ATU_TYPE_MEM, + dpu_offset, host_addr, size); + + set_bit(free_win, ep->ob_window_map); + ep->ob_src_addr[free_win] = dpu_offset; + + return 0; +} + +static void pcie_dpu_ep_reset_bar(struct pcie_dpu_ep *ep, u8 func_no, u8 vfunc_no, + enum pci_barno bar, int flags) +{ + int sriov_cap_offset = 0; + u32 reg = 0; + u32 func_offset = pcie_dpu_ep_func_select(func_no & PCIE_DPU_EP_GET_PF_NO, vfunc_no); + + if (isPF(func_no)) + { + reg = func_offset + (u32)(PCI_BASE_ADDRESS_0) + (u32)(PCIE_NEXT_BAR_OFFSET * bar); + pcie_zf_dbi_ro_wr_en(ep); + // pcie_zf_writel_dbi2(ep, reg, 0x0); + pcie_zf_writel_dbi(ep, reg, 0xc); + // pcie_zf_writel_dbi2(ep, reg + PCIE_NEXT_BAR_OFFSET, 0x0); + // pcie_zf_writel_dbi(ep, reg + PCIE_NEXT_BAR_OFFSET, 0x0); + pcie_zf_dbi_ro_wr_dis(ep); + } + else + { + sriov_cap_offset = pcie_dpu_ep_find_extcap(ep, func_offset, PCI_EXT_CAP_ID_SRIOV, 0); + if (sriov_cap_offset < 0) + { + DH_LOG_ERR(MODULE_MPF, "find_extcap failed!!\n"); + } + + reg = func_offset + (u32)sriov_cap_offset + (u32)(PCIE_SRIOV_ECAP_BAR0_OFFSET) + (u32)(bar * PCIE_NEXT_BAR_OFFSET); + pcie_zf_writel_dbi(ep, reg, 0xc); + pcie_zf_writel_dbi(ep, reg + PCIE_NEXT_BAR_OFFSET, 0x0); + + // reg = func_offset + sriov_cap_offset; + // pcie_dpu_ep_sriov_disable(ep, reg); + // pcie_zf_writel_dbi2(ep, reg + PCIE_SRIOV_ECAP_BAR0_OFFSET + bar * PCIE_NEXT_BAR_OFFSET, 0x0); + // pcie_zf_writel_dbi2(ep, reg + PCIE_SRIOV_ECAP_BAR0_OFFSET + (bar + 1) * PCIE_NEXT_BAR_OFFSET, 0x0); + // pcie_dpu_ep_sriov_enable(ep, reg); + } +} + +void pcie_zf_disable_atu(struct pcie_dpu_ep *ep, int index, + enum pcie_dpu_region_type type) +{ + u32 val = 0; + switch (type) + { + case PCIE_DPU_REGION_INBOUND: + val = pcie_zf_readl_ib_unroll(ep, index, PCIE_ATU_UNR_REGION_CTRL2); + val &= (u32)(~PCIE_ATU_ENABLE); + pcie_zf_writel_ib_unroll(ep, index, PCIE_ATU_UNR_REGION_CTRL2, val); + break; + case PCIE_DPU_REGION_OUTBOUND: + val = pcie_zf_readl_ob_unroll(ep, index, PCIE_ATU_UNR_REGION_CTRL2); + val &= (u32)(~PCIE_ATU_ENABLE); + pcie_zf_writel_ob_unroll(ep, index, PCIE_ATU_UNR_REGION_CTRL2, val); + break; + default: + return; + } +} + +static int pcie_zf_find_index(struct pcie_dpu_ep *ep, phys_addr_t dpu_offset, + u32 *atu_index) +{ + u32 index = 0; + + for (index = 0; index < ep->num_ob_windows; index++) + { + if (ep->ob_src_addr[index] != dpu_offset) + continue; + *atu_index = index; + return 0; + } + + return -EINVAL; +} +#endif + +// if ep is link up, return 1 +int pcie_zf_link_up(int ep_id) +{ + u32 val = 0; + + if (ep_id < 0 || ep_id >= PCIE_DPU_EP_NUM) + { + DH_LOG_ERR(MODULE_MPF, "pcie_zf_link_up:err ep_id!\n"); + return -1; + } + + val = readl(zf_ep->dpu_ep_array[ep_id]->dbi_base + PCIE_PORT_DEBUG1); + return ((val & PCIE_PORT_DEBUG1_ZTE_ZF_LINK_UP) && + (!(val & PCIE_PORT_DEBUG1_LINK_IN_TRAINING))); +} +EXPORT_SYMBOL_GPL(pcie_zf_link_up); + +void ep_power_reset(int ep_id) +{ + u64 csr_base_addr = 0; + + csr_base_addr = zf_ep->mpf_paddr + PCIE_DPU_MPF_CSR_ADDR(PCIE_DPU_EP_CSR_SIZE * ep_id); + cfg_phy_rmw(csr_base_addr + PCIE_DPU_EP_CSR_PRST_ADDR, 0x0, 0x2); + cfg_phy_rmw(csr_base_addr + PCIE_DPU_EP_CSR_PRST_ADDR, 0x2, 0x2); +} +EXPORT_SYMBOL_GPL(ep_power_reset); + +int ep_virtio_module_set(int ep_id, int pf_idx, int en) +{ + u64 csr_base_addr = 0; + + csr_base_addr = zf_ep->mpf_paddr + PCIE_DPU_MPF_CSR_ADDR(PCIE_DPU_EP_CSR_SIZE * ep_id); + if ((0 != en) & (1 != en)) + { + DH_LOG_ERR(MODULE_MPF, "err module!\n"); + return -EINVAL; + } + cfg_phy_rmw(csr_base_addr + PCIE_DPU_EP_CSR_VIRT_ADDR, en << pf_idx, 0x1 << pf_idx); + return 0; +} +EXPORT_SYMBOL_GPL(ep_virtio_module_set); + +static phys_addr_t ob_addr_set(int ep_id, phys_addr_t phys_addr) +{ + phys_addr_t rel_addr; + u64 addr_mask = 0xffff; + + rel_addr = (phys_addr & addr_mask) | ep_id << 16 | ((phys_addr & ~addr_mask) << EP_ID_LEN); + return rel_addr; +} + +int pcie_zte_epc_ob_read(struct pci_epc *epc, phys_addr_t phys_addr, unsigned int size, unsigned int *val) +{ + void __iomem *vaddr = NULL; + struct pcie_dpu_ep *dpu_dev = NULL; + + if (!epc) + { + DH_LOG_ERR(MODULE_MPF, "epc is NULL!\n"); + return -ENOMEM; + } + + if (phys_addr < zf_ep->mpf_paddr || phys_addr >= zf_ep->mpf_paddr + zf_ep->ob_size) + { + DH_LOG_ERR(MODULE_MPF, "err:phys_addr out of range!\n"); + return -ENOMEM; + } + + dpu_dev = epc_get_drvdata(epc); + vaddr = zf_ep->mpf_vaddr + ob_addr_set(dpu_dev->ep_id + 5, phys_addr - zf_ep->mpf_paddr); + + return pcie_zf_read(vaddr, size, val); +} +EXPORT_SYMBOL_GPL(pcie_zte_epc_ob_read); + +int pcie_zte_epc_ob_write(struct pci_epc *epc, phys_addr_t phys_addr, int size, int val) +{ + void __iomem *vaddr = NULL; + struct pcie_dpu_ep *dpu_dev = NULL; + + if (!epc) + { + DH_LOG_ERR(MODULE_MPF, "epc is NULL\n"); + return -ENOMEM; + } + + if (phys_addr < zf_ep->mpf_paddr || phys_addr >= zf_ep->mpf_paddr + zf_ep->ob_size) + { + DH_LOG_ERR(MODULE_MPF, "err:phys_addr out of range\n"); + return -ENOMEM; + } + + dpu_dev = epc_get_drvdata(epc); + + vaddr = zf_ep->mpf_vaddr + ob_addr_set(dpu_dev->ep_id + 5, phys_addr - zf_ep->mpf_paddr); + + return pcie_zf_write(vaddr, size, val); +} +EXPORT_SYMBOL_GPL(pcie_zte_epc_ob_write); + +/*################the ops of epc###################*/ +#if 1 +static int pcie_dpu_ep_write_header(struct pci_epc *epc, u8 func_no, u8 vfunc_no, + struct pci_epf_header *hdr) +{ + struct pcie_dpu_ep *ep = epc_get_drvdata(epc); + u32 func_offset = 0, sriov_offset = 0; + int sriov_cap_offset = 0; + int pf_no = func_no & PCIE_DPU_EP_GET_PF_NO; + + DH_LOG_INFO(MODULE_MPF, "func_no = 0x%x, vfunc_no = 0x%x\n", func_no, vfunc_no); + + pcie_zf_dbi_ro_wr_en(ep); + if (isPF(func_no)) + { + func_offset = pcie_dpu_ep_func_select(func_no, 0); + pcie_zf_writew_dbi(ep, func_offset + PCI_VENDOR_ID, hdr->vendorid); + pcie_zf_writew_dbi(ep, func_offset + PCI_DEVICE_ID, hdr->deviceid); + pcie_zf_writel_dbi(ep, func_offset + PCI_CLASS_REVISION, hdr->revid | hdr->progif_code << 8 | hdr->subclass_code << 16 | hdr->baseclass_code << 24); + pcie_zf_writew_dbi(ep, func_offset + PCI_SUBSYSTEM_VENDOR_ID, hdr->subsys_vendor_id); + pcie_zf_writew_dbi(ep, func_offset + PCI_SUBSYSTEM_ID, hdr->subsys_id); + } + else + { + func_offset = pcie_dpu_ep_func_select(pf_no, 0); + sriov_cap_offset = pcie_dpu_ep_find_extcap(ep, func_offset, PCI_EXT_CAP_ID_SRIOV, 0); + if (sriov_cap_offset < 0) + { + DH_LOG_ERR(MODULE_MPF, "find_extcap failed!!\n"); + } + sriov_offset = func_offset + (u32)sriov_cap_offset; + pcie_zf_writew_dbi(ep, sriov_offset + PCIE_SRIOV_ECAP_DEVICE_ID, hdr->deviceid); + } + pcie_zf_dbi_ro_wr_dis(ep); + + return 0; +} + +static int pcie_dpu_ep_set_pf_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, + struct pci_epf_bar *epf_bar) +{ + int ret = 0; + struct pcie_dpu_ep *ep = epc_get_drvdata(epc); + enum pci_barno barno = epf_bar->barno; + size_t size = epf_bar->size; + int flags = epf_bar->flags; + enum pcie_dpu_as_type as_type; + u32 reg = 0; + u32 func_offset = 0; + u64 dpu_addr = 0; + + dpu_addr = epf_bar->phys_addr | ZF_PREFIX_ADDR; + + if (!(flags & PCI_BASE_ADDRESS_SPACE)) + as_type = PCIE_DPU_AS_MEM; + else + as_type = PCIE_DPU_AS_IO; + + if (barno != BAR_4) + { + ret = pcie_dpu_ep_inbound_atu(ep, func_no, barno, dpu_addr, as_type); + if (ret) + return ret; + } + else + { + return 0; + } + + func_offset = pcie_dpu_ep_func_select(func_no, vfunc_no); + + if (barno != BAR_ROM) + { + reg = PCI_BASE_ADDRESS_0 + (4 * barno) + func_offset; + } + else + { + reg = PCI_ROM_ADDRESS + func_offset; + } + + if (size) + { + pcie_zf_dbi_ro_wr_en(ep); + + pcie_zf_writel_dbi2(ep, reg, 1); + pcie_zf_writel_dbi2(ep, reg, lower_32_bits(size - 1)); + pcie_zf_writel_dbi(ep, reg, flags | BIT(3)); + if (barno != BAR_ROM) + { + pcie_zf_writel_dbi2(ep, reg + PCIE_NEXT_BAR_OFFSET, upper_32_bits(size - 1)); + pcie_zf_writel_dbi(ep, reg + PCIE_NEXT_BAR_OFFSET, 0); + } + pcie_zf_dbi_ro_wr_dis(ep); + } + + return 0; +} + +static int pcie_dpu_ep_set_vf_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, + struct pci_epf_bar *epf_bar) +{ + int ret = 0; + struct pcie_dpu_ep *ep = epc_get_drvdata(epc); + enum pci_barno barno = epf_bar->barno; + int flags = epf_bar->flags; + u32 reg = 0; + u32 func_offset = 0; + int sriov_cap_offset = 0; + u32 pf_func_no = func_no & PCIE_DPU_EP_GET_PF_NO; + u64 dpu_addr = epf_bar->phys_addr | ZF_PREFIX_ADDR; + + if (flags & PCI_BASE_ADDRESS_SPACE) + { + DH_LOG_ERR(MODULE_MPF, "error:vf bar must be mem\n"); + return -EINVAL; + } + + DH_LOG_DEBUG(MODULE_MPF, "pf%x vf%x bar->flags:%d\n", pf_func_no, vfunc_no, flags); + + if (barno != BAR_4) + { + ret = pcie_dpu_ep_inbound_atu(ep, func_no, barno, + dpu_addr, PCIE_DPU_AS_MEM); + if (ret) + return ret; + } + else + { + return 0; + } + + func_offset = pcie_dpu_ep_func_select(pf_func_no, 0); + sriov_cap_offset = pcie_dpu_ep_find_extcap(ep, func_offset, PCI_EXT_CAP_ID_SRIOV, 0); + if (sriov_cap_offset < 0) + { + DH_LOG_ERR(MODULE_MPF, "find_extcap failed!!\n"); + return -ENXIO; + } + + reg = func_offset + sriov_cap_offset; + pcie_dpu_ep_sriov_disable(ep, reg); + if (epf_bar->size) + { + pcie_zf_writel_dbi2(ep, reg + PCIE_SRIOV_ECAP_BAR0_OFFSET + barno * PCIE_NEXT_BAR_OFFSET, 1); + pcie_zf_writel_dbi2(ep, reg + PCIE_SRIOV_ECAP_BAR0_OFFSET + barno * PCIE_NEXT_BAR_OFFSET, lower_32_bits(epf_bar->size - 1)); + pcie_zf_writel_dbi2(ep, reg + PCIE_SRIOV_ECAP_BAR0_OFFSET + (barno + 1) * PCIE_NEXT_BAR_OFFSET, upper_32_bits(epf_bar->size - 1)); + } + pcie_zf_dbi_ro_wr_en(ep); + pcie_zf_writel_dbi(ep, reg + PCIE_SRIOV_ECAP_BAR0_OFFSET + barno * PCIE_NEXT_BAR_OFFSET, epf_bar->flags | BIT(3)); + pcie_zf_dbi_ro_wr_dis(ep); + + pcie_dpu_ep_sriov_enable(ep, reg); + + return 0; +} + +static int pcie_dpu_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, struct pci_epf_bar *epf_bar) +{ + DH_LOG_DEBUG(MODULE_MPF, "func:0x%x vfunc:0x%x\n", func_no, vfunc_no); + if (isPF(func_no)) + { + return pcie_dpu_ep_set_pf_bar(epc, func_no, vfunc_no, epf_bar); + } + else if (vfunc_no == 0) + { + return pcie_dpu_ep_set_vf_bar(epc, func_no, vfunc_no, epf_bar); + } + + return 0; +} + +static void pcie_dpu_ep_clear_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, + bool clear_vf, struct pci_epf_bar *epf_bar) +{ + struct pcie_dpu_ep *ep = epc_get_drvdata(epc); + u32 vf_bar_off = 0; + enum pci_barno barno = epf_bar->barno; + int atu_index = 0; + u32 bar_to_atu_index = 0; + + if ((func_no & PCIE_DPU_EP_GET_PF_NO) >= PCIE_DPU_PF_NUMS) + { + DH_LOG_ERR(MODULE_MPF, "func_no is err!\n"); + return; + } + + if ((barno == BAR_4) || (!isPF(func_no) && !vfunc_no)) + { + return; + } + + if (!isPF(func_no)) + { + vf_bar_off = PCIE_VF_BARS_OFF; + } + + bar_to_atu_index = (u32)barno + vf_bar_off; + if (bar_to_atu_index < (PCI_STD_NUM_BARS * 2 + 1)) + { + atu_index = ep->bar_to_atu[func_no & PCIE_DPU_EP_GET_PF_NO][bar_to_atu_index]; + } + else + { + DH_LOG_ERR(MODULE_MPF, "error bar_to_atu index %d\r\n", bar_to_atu_index); + return; + } + + pcie_dpu_ep_reset_bar(ep, func_no, vfunc_no, barno, epf_bar->flags); + + pcie_zf_disable_atu(ep, atu_index, PCIE_DPU_REGION_INBOUND); + spin_lock(&ep->ib_window_lock); + clear_bit(atu_index, ep->ib_window_map); + spin_unlock(&ep->ib_window_lock); +} + +static int pcie_dpu_ep_map_addr(struct pci_epc *epc, u8 func_no, u8 vfunc_no, + phys_addr_t dpu_offset, u64 host_addr, size_t size) +{ + int ret = 0; + struct pcie_dpu_ep *ep = epc_get_drvdata(epc); + + DH_LOG_INFO(MODULE_MPF, "func_no = 0x%x, dpu_addr = 0x%llx, host_addr = 0x%llx\n", func_no, dpu_offset, host_addr); + ret = pcie_dpu_ep_outbound_atu(ep, func_no, vfunc_no, dpu_offset - zf_ep->mpf_paddr, host_addr, size); + if (ret) + { + DH_LOG_ERR(MODULE_MPF, "Failed to enable address\r\n"); + return ret; + } + + return 0; +} + +static void pcie_dpu_ep_unmap_addr(struct pci_epc *epc, u8 func_no, + u8 vfunc_no, phys_addr_t dpu_offset) +{ + int ret = 0; + u32 atu_index = 0; + struct pcie_dpu_ep *ep = epc_get_drvdata(epc); + + ret = pcie_zf_find_index(ep, dpu_offset - zf_ep->mpf_paddr, &atu_index); + if (ret < 0) + return; + + pcie_zf_disable_atu(ep, atu_index, PCIE_DPU_REGION_OUTBOUND); + clear_bit(atu_index, ep->ob_window_map); +} + +static int pcie_dpu_ep_set_msi(struct pci_epc *epc, u8 func_no, u8 vfunc_no, u8 interrupts) +{ + DH_LOG_ERR(MODULE_MPF, "error:pcie_dpu_ep can't set msi#\n"); + return -ESRCH; +} + +static int pcie_dpu_ep_get_msi(struct pci_epc *epc, u8 func_no, u8 vfunc_no) +{ + DH_LOG_ERR(MODULE_MPF, "error:pcie_dpu_ep can't get msi#\n"); + return -ESRCH; +} + +static int pcie_dpu_ep_set_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no, + u16 interrupts, enum pci_barno bir, u32 bar_offset) +{ + /* + * MSIX tables are fixed in BAR4 (mapped to PCIe IP), other configs + * will make MSIX unable to function. + */ + dev_warn(&epc->dev, "MSIX config is not supported by ZF epc\n"); + + return 0; +} + +int pcie_dpu_ep_get_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no) +{ + struct pcie_dpu_ep *dpu_dev = epc_get_drvdata(epc); + u32 val, reg; + u32 func_offset = 0; + struct pcie_dpu_ep_func *ep_func; + + ep_func = pcie_dpu_ep_get_func_from_ep(dpu_dev, func_no, vfunc_no); + if (!ep_func || !ep_func->msix_cap) + return -EINVAL; + + func_offset = pcie_dpu_ep_func_select(func_no, vfunc_no); + + reg = func_offset + ep_func->msix_cap + PCI_MSIX_FLAGS; + val = pcie_zf_readw_dbi(dpu_dev, reg); + if (!(val & PCI_MSIX_FLAGS_ENABLE)) + return -EINVAL; + + val &= PCI_MSIX_FLAGS_QSIZE; + + return val; +} + +int pcie_dpu_ep_raise_legacy_irq(struct pci_epc *epc, u8 func_no, u8 vfunc_no) +{ + DH_LOG_ERR(MODULE_MPF, "EP cannot trigger legacy IRQs\r\n"); + + return -EINVAL; +} + +int pcie_dpu_ep_raise_msi_irq(struct pci_epc *epc, u8 func_no, u8 vfunc_no, u8 interrupt_num) +{ + DH_LOG_ERR(MODULE_MPF, "EP cannot trigger msi IRQs\r\n"); + + return -EINVAL; +} + +int pcie_dpu_ep_raise_msix_irq(struct pci_epc *epc, u8 func_no, u8 vfunc_no, u8 interrupt_num) +{ + struct pcie_dpu_ep *dpu_dev = epc_get_drvdata(epc); + u32 msg_data = 0; + + // DH_LOG_INFO(MODULE_MPF, "func_no = 0x%x, vfunc_no = 0x%x, interrupt_num = 0x%x\n", func_no, vfunc_no, interrupt_num); + + if (isPF(func_no)) + { + msg_data = (func_no << PCIE_MSIX_DOORBELL_PF_SHIFT) | (interrupt_num); + } + else + { + msg_data = ((func_no & PCIE_DPU_EP_GET_PF_NO) << PCIE_MSIX_DOORBELL_PF_SHIFT) | + MSIX_DOORBELL_VF_ACTIVE | (vfunc_no << PCIE_MSIX_DOORBELL_VF_SHIFT) | + (interrupt_num); + } + + pcie_zf_writel_dbi(dpu_dev, PCIE_MSIX_DOORBELL, msg_data); + + return 0; +} + +static int pcie_dpu_ep_raise_irq(struct pci_epc *epc, u8 func_no, u8 vfunc_no, + enum pci_epc_irq_type type, u16 interrupt_num) +{ + switch (type) + { + case PCI_EPC_IRQ_LEGACY: + return pcie_dpu_ep_raise_legacy_irq(epc, func_no, vfunc_no); + case PCI_EPC_IRQ_MSI: + return pcie_dpu_ep_raise_msi_irq(epc, func_no, vfunc_no, interrupt_num - 1); + case PCI_EPC_IRQ_MSIX: + return pcie_dpu_ep_raise_msix_irq(epc, func_no, vfunc_no, interrupt_num - 1); + default: + DH_LOG_ERR(MODULE_MPF, "UNKNOWN IRQ type\r\n"); + } + return 0; +} + +static int pcie_dpu_ep_get_max_vfs(struct pci_epc *epc, u8 func_no) +{ + struct pcie_dpu_ep *dpu_dev = NULL; + u32 vf_total_num = 0; + + if (epc == NULL) + { + DH_LOG_ERR(MODULE_MPF, "epc is NULL!!!\n"); + return -EINVAL; + } + dpu_dev = epc_get_drvdata(epc); + vf_total_num = func_no & PCIE_DPU_EP_GET_PF_NO; + if (vf_total_num >= PCIE_DPU_PF_NUMS) + { + DH_LOG_ERR(MODULE_MPF, "error vf_total_num=%d\n", vf_total_num); + return -EINVAL; + } + + DH_LOG_INFO(MODULE_MPF, "get vf max_num:%d\n", dpu_dev->vf_total_num[vf_total_num]); + return dpu_dev->vf_total_num[vf_total_num]; +} + +static void pcie_dpu_ep_stop(struct pci_epc *epc) +{ + DH_LOG_INFO(MODULE_MPF, "%s\n", __func__); + return; +} + +static int pcie_dpu_ep_start(struct pci_epc *epc) +{ + DH_LOG_INFO(MODULE_MPF, "%s\n", __func__); + return 0; +} + +static const struct pci_epc_features pcie_zf_epc_features = { + .linkup_notifier = false, + .msi_capable = false, + .msix_capable = true, + .reserved_bar = PCIE_DPU_EP_REAERVED_BAR, + .bar_fixed_64bit = PCIE_DPU_EP_BAR_FIXED_64BIT, + .align = PCIE_DPU_EP_ALIGN, +}; + +static const struct pci_epc_features * +pcie_dpu_ep_get_features(struct pci_epc *epc, u8 func_no, u8 vfunc_no) +{ + return &pcie_zf_epc_features; +} + +static int pci_dpu_ep_get_port_id(struct pci_epc *epc, + enum pci_epc_port_id_type *id) +{ + struct pcie_dpu_ep *dpu_dev = epc_get_drvdata(epc); + + *id = dpu_dev->ep_id + 5; + return 0; +} + +static int pci_dpu_ep_calc_pfns(struct pci_epc *epc, phys_addr_t phys, + size_t n_pfns, unsigned long *pfn) +{ + enum pci_epc_port_id_type port = 0; + phys_addr_t offset = 0, base = zf_ep->mpf_paddr; + size_t i = 0; + + if (phys < base || + phys - base + (n_pfns << PAGE_SHIFT) > zf_ep->ob_size) + return -EINVAL; + + pci_dpu_ep_get_port_id(epc, &port); + + for (i = 0; i < n_pfns; i++) + { + offset = phys - base + (i << PAGE_SHIFT); + pfn[i] = (base + EP_DPU_PA(offset, port)) >> PAGE_SHIFT; + } + return 0; +} + +#endif + +static const struct pci_epc_ops epc_ops = { + .write_header = pcie_dpu_ep_write_header, + .set_bar = pcie_dpu_ep_set_bar, + .clear_bar = pcie_dpu_ep_clear_bar, + .map_addr = pcie_dpu_ep_map_addr, + .unmap_addr = pcie_dpu_ep_unmap_addr, + .set_msi = pcie_dpu_ep_set_msi, + .get_msi = pcie_dpu_ep_get_msi, + .set_msix = pcie_dpu_ep_set_msix, + .get_msix = pcie_dpu_ep_get_msix, + .raise_irq = pcie_dpu_ep_raise_irq, + .get_max_vfs = pcie_dpu_ep_get_max_vfs, + .start = pcie_dpu_ep_start, + .stop = pcie_dpu_ep_stop, + .get_features = pcie_dpu_ep_get_features, + .get_port_id = pci_dpu_ep_get_port_id, + .calc_pfns = pci_dpu_ep_calc_pfns, + .get_xdma_chan = zf_pcie_get_hdma_chan, +}; + +static void dpu_ep_default_set(int ep_id) +{ + u32 pf_idx = 0; + u32 func_offset = 0; + int sriov_cap_offset = 0; + u32 reg = 0; + struct pcie_dpu_ep *ep = zf_ep->dpu_ep_array[ep_id]; + + pcie_zf_dbi_ro_wr_en(ep); + for (pf_idx = 0; pf_idx < PCIE_DPU_PF_NUMS; ++pf_idx) + { + if (!(ep->permissible_pf_map & (0x1 << pf_idx))) + { + continue; + } + pcie_zf_writel_dbi(ep, pf_idx * PCIE_DPU_EP_FUNC_CFG_SIZE, PCIE_DPU_PF_INITIAL_ID); + pcie_zf_writel_dbi(ep, pf_idx * PCIE_DPU_EP_FUNC_CFG_SIZE + PCI_CLASS_REVISION, PCIE_DPU_PF_DEFAUTL_CLASSCODE); + pcie_zf_writel_dbi2(ep, pf_idx * PCIE_DPU_EP_FUNC_CFG_SIZE + PCI_ROM_ADDRESS, ZF_DISABLE); + + pcie_zf_writel_dbi2(ep, pf_idx * PCIE_DPU_EP_FUNC_CFG_SIZE + PCI_BASE_ADDRESS_4, ZF_ENABLE); + pcie_zf_writel_dbi2(ep, pf_idx * PCIE_DPU_EP_FUNC_CFG_SIZE + PCI_BASE_ADDRESS_4, lower_32_bits(BAR4_DEFAULT_SIZE - 1)); + pcie_zf_writel_dbi2(ep, pf_idx * PCIE_DPU_EP_FUNC_CFG_SIZE + PCI_BASE_ADDRESS_4 + PCIE_NEXT_BAR_OFFSET, upper_32_bits(BAR4_DEFAULT_SIZE - 1)); + pcie_zf_writel_dbi(ep, pf_idx * PCIE_DPU_EP_FUNC_CFG_SIZE + PCI_BASE_ADDRESS_4, PCIE_DEFAULT_BAR_FLAG); + + func_offset = pcie_dpu_ep_func_select(pf_idx, 0); + sriov_cap_offset = pcie_dpu_ep_find_extcap(ep, func_offset, PCI_EXT_CAP_ID_SRIOV, 0); + if (sriov_cap_offset < 0) + { + DH_LOG_ERR(MODULE_MPF, "find_extcap failed!!\n"); + return; + } + + reg = func_offset + sriov_cap_offset; + pcie_dpu_ep_sriov_disable(ep, reg); + pcie_zf_writel_dbi(ep, reg + PCIE_SRIOV_ECAP_BAR4_OFFSET, PCIE_DEFAULT_BAR_FLAG); + pcie_zf_writel_dbi2(ep, reg + PCIE_SRIOV_ECAP_BAR4_OFFSET, 0x1); + pcie_zf_writel_dbi2(ep, reg + PCIE_SRIOV_ECAP_BAR4_OFFSET, lower_32_bits(BAR4_DEFAULT_SIZE - 1)); + pcie_zf_writel_dbi2(ep, reg + PCIE_SRIOV_ECAP_BAR4_OFFSET + PCIE_NEXT_BAR_OFFSET, upper_32_bits(BAR4_DEFAULT_SIZE - 1)); + pcie_dpu_ep_sriov_enable(ep, reg); + } + pcie_zf_dbi_ro_wr_dis(ep); +} + +static int dpu_ep_iatu_init(struct device *dev, int id) +{ + int iatu_no = 0; + + zf_ep->dpu_ep_array[id]->num_ib_windows = PCIE_DPU_IATU_NUM; + zf_ep->dpu_ep_array[id]->num_ob_windows = PCIE_DPU_IATU_NUM; + zf_ep->dpu_ep_array[id]->ib_window_map = devm_kcalloc(dev, BITS_TO_LONGS(zf_ep->dpu_ep_array[id]->num_ib_windows), + sizeof(long), GFP_KERNEL); + if (!zf_ep->dpu_ep_array[id]->ib_window_map) + { + DH_LOG_ERR(MODULE_MPF, "get ib_map err\n"); + return -ENOMEM; + } + + zf_ep->dpu_ep_array[id]->ob_window_map = devm_kcalloc(dev, BITS_TO_LONGS(zf_ep->dpu_ep_array[id]->num_ob_windows), + sizeof(long), GFP_KERNEL); + if (!zf_ep->dpu_ep_array[id]->ob_window_map) + { + DH_LOG_ERR(MODULE_MPF, "get ob_map err\n"); + goto free_ib_map; + } + + zf_ep->dpu_ep_array[id]->ob_src_addr = devm_kcalloc(dev, zf_ep->dpu_ep_array[id]->num_ob_windows, sizeof(phys_addr_t), + GFP_KERNEL); + if (!zf_ep->dpu_ep_array[id]->ob_src_addr) + { + DH_LOG_ERR(MODULE_MPF, "get ob_src_addr err\n"); + goto free_ob_map; + } + + // 确定哪些inbound已经被使用 + for (iatu_no = 0; iatu_no < PCIE_DPU_IATU_NUM; iatu_no++) + { + if (zf_atu_is_used(zf_ep->dpu_ep_array[id], iatu_no)) + { + set_bit(iatu_no, zf_ep->dpu_ep_array[id]->ib_window_map); + } + } + + spin_lock_init(&zf_ep->dpu_ep_array[id]->ib_window_lock); + + return 0; + +free_ob_map: + devm_kfree(dev, zf_ep->dpu_ep_array[id]->ob_window_map); +free_ib_map: + devm_kfree(dev, zf_ep->dpu_ep_array[id]->ib_window_map); + return -ENOMEM; +} + +static int dpu_ep_func_list_init(struct device *dev, int id) +{ + u8 func_no = 0, vfunc_no = 0; + u8 vf_total_num = 0; + u32 func_offset = 0; + struct pcie_dpu_ep_func *ep_func = NULL; + + INIT_LIST_HEAD(&zf_ep->dpu_ep_array[id]->func_list); + for (func_no = 0; func_no < PCIE_DPU_PF_NUMS; ++func_no) + { + if (!(zf_ep->dpu_ep_array[id]->permissible_pf_map & (0x1 << func_no))) + { + continue; + } + ep_func = devm_kzalloc(dev, sizeof(*ep_func), GFP_KERNEL); + if (!ep_func) + { + return -ENOMEM; + } + + ep_func->func_no = func_no; + func_offset = pcie_dpu_ep_func_select(func_no, vfunc_no); + ep_func->msix_cap = pcie_dpu_ep_find_cap(zf_ep->dpu_ep_array[id], func_offset, PCI_CAP_ID_MSIX); + + list_add_tail(&ep_func->list, &zf_ep->dpu_ep_array[id]->func_list); + + vf_total_num = (u8)zf_ep->dpu_ep_array[id]->vf_total_num[func_no]; + for (vfunc_no = 0; vfunc_no < vf_total_num; ++vfunc_no) + { + ep_func = devm_kzalloc(dev, sizeof(*ep_func), GFP_KERNEL); + if (!ep_func) + { + return -ENOMEM; + } + + ep_func->func_no = PCIE_DPU_EP_FUNC_IS_VF | func_no; + ep_func->vfunc_no = vfunc_no; + func_offset = pcie_dpu_ep_func_select(ep_func->func_no, vfunc_no); + ep_func->msix_cap = pcie_dpu_ep_find_cap(zf_ep->dpu_ep_array[id], + func_offset, PCI_CAP_ID_MSIX); + + list_add_tail(&ep_func->list, &zf_ep->dpu_ep_array[id]->func_list); + } + } + + return 0; +} + +static int dpu_ep_vf_total_num_get(int id) +{ + int func_no = 0, func_offset = 0, sriov_cap_offset = 0, vf_total_num_addr = 0; + + for (func_no = 0; func_no < PCIE_DPU_PF_NUMS; ++func_no) + { + func_offset = pcie_dpu_ep_func_select(func_no, 0); + sriov_cap_offset = pcie_dpu_ep_find_extcap(zf_ep->dpu_ep_array[id], func_offset, PCI_EXT_CAP_ID_SRIOV, 0); + if (sriov_cap_offset < 0) + { + DH_LOG_ERR(MODULE_MPF, "find_extcap failed!!\n"); + return -ENXIO; + } + vf_total_num_addr = func_offset + sriov_cap_offset + PCIE_SRIOV_TOTAL_VFS; + zf_ep->dpu_ep_array[id]->vf_total_num[func_no] = pcie_zf_readw_dbi(zf_ep->dpu_ep_array[id], vf_total_num_addr); + } + + return 0; +} + +static int dpu_ep_get_permissible_pf(int id) +{ + int func_no = 0, func_offset = 0; + u32 func_id = 0; + + for (func_no = 0; func_no < PCIE_DPU_PF_NUMS; ++func_no) + { + func_offset = pcie_dpu_ep_func_select(func_no, 0); + func_id = pcie_zf_readl_dbi(zf_ep->dpu_ep_array[id], func_offset); + if (PCIE_DPU_PF_DEFAUTL_ID1 == func_id || PCIE_DPU_PF_DEFAUTL_ID2 == func_id || + PCIE_DPU_PF_DEFAUTL_ID3 == func_id || PCIE_DPU_PF_DEFAUTL_ID4 == func_id) + { + zf_ep->dpu_ep_array[id]->permissible_pf_map |= (0x1 << func_no); + } + } + + return 0; +} + +static void epc_dev_release(struct device *dev) +{ +} + +static int pci_zte_epc_dev_init_one(struct pci_dev *pdev, int id) +{ + struct pci_epc *epc = NULL; + struct device *dev = NULL; + struct device_node *np = NULL; + struct platform_device *zf_pdev = NULL; + struct platform_device *zf_pdev_dma = NULL; + char class_name[PCIE_DPU_EP_CLASS_NAME] = {0}; + int node = 0, i = 0; + int ret = -ENOMEM; + + snprintf(class_name, sizeof(class_name) - 1,"zf_epc_class%d", id); + zf_pdev = platform_device_register_simple(class_name, -1, NULL, 0); + if (!zf_pdev) + { + DH_LOG_ERR(MODULE_MPF, "Error platform_device_register zf_pdev failed\n"); + return ret; + } + + snprintf(class_name, sizeof(class_name) - 1,"zf_epc_dma_rd%d", id); + zf_pdev_dma = platform_device_register_simple(class_name, -1, NULL, 0); + if (!zf_pdev_dma) + { + DH_LOG_ERR(MODULE_MPF, "Error platform_device_register zf_pdev_dma failed\n"); + return ret; + } + + zf_pdev->dev.driver = pdev->dev.driver; + zf_pdev_dma->dev.driver = pdev->dev.driver; + + dev = &zf_pdev->dev; + np = dev->of_node; + epc = pci_epc_create(dev, &epc_ops); + if (IS_ERR_OR_NULL(epc)) + { + DH_LOG_ERR(MODULE_MPF, "Failed %ld to create epc device\n", PTR_ERR(epc)); + ret = -EPERM; + goto free_pdev; + } + + epc->dev.release = epc_dev_release; + epc->max_functions = PCIE_DPU_PF_NUMS; + epc->is_dpu_epc = 1; + + ret = pci_epc_mem_init(epc, zf_ep->mpf_paddr, zf_ep->ob_size, PAGE_SIZE); + if (ret < 0) + { + DH_LOG_ERR(MODULE_MPF, "ep%d failed to initialize the memory space\n", id); + goto free_epc; + } + + node = dev_to_node(dev); // 多核 + if (node == NUMA_NO_NODE) + set_dev_node(dev, first_memory_node); + + /*##################zf_dev init##################*/ + zf_ep->dpu_ep_array[id] = kzalloc_node(sizeof(struct pcie_dpu_ep), GFP_KERNEL, node); + if (!zf_ep->dpu_ep_array[id]) + { + DH_LOG_ERR(MODULE_MPF, "Error kzalloc node\n"); + ret = -ENOMEM; + goto free_epc_mem; + } + + zf_ep->dpu_ep_array[id]->ep_id = id; + zf_ep->dpu_ep_array[id]->epc = epc; + zf_ep->dpu_ep_array[id]->dbi_base = zf_ep->dbi_vaddr + PCIE_DPU_EP_DBI_SIZE * id; + zf_ep->dpu_ep_array[id]->atu_base = zf_ep->dpu_ep_array[id]->dbi_base + DEFAULT_DBI_ATU_OFFSET; + zf_ep->dpu_ep_array[id]->zf_pdev = zf_pdev; + zf_ep->dpu_ep_array[id]->zf_pdev_dma = zf_pdev_dma; + + dpu_ep_default_set(id); + + epc_set_drvdata(epc, zf_ep->dpu_ep_array[id]); + + dpu_ep_get_permissible_pf(id); + for (i = 0; i < PCIE_DPU_PF_NUMS; i++) + { + if (!(zf_ep->dpu_ep_array[id]->permissible_pf_map & (0x1 << i))) + { + DH_LOG_INFO(MODULE_MPF, "ep%d pf%d can't uesd\n", id, i); + set_bit(i, &epc->function_num_map); + } + } + + ret |= dpu_ep_iatu_init(&pdev->dev, id); + ret |= dpu_ep_vf_total_num_get(id); + ret |= dpu_ep_func_list_init(&pdev->dev, id); + + if (ret) + goto free_dpu_ep; + + return 0; + +free_dpu_ep: + kfree(zf_ep->dpu_ep_array[id]); +free_epc_mem: + pci_epc_mem_exit(epc); +free_epc: + pci_epc_destroy(epc); +free_pdev: + platform_device_unregister(zf_pdev); + platform_device_unregister(zf_pdev_dma); + return ret; +} + +static void pci_zte_epc_dev_free_one(struct pci_dev *pdev, int id) +{ + pcie_zf_dma_free(zf_ep->dpu_ep_array[id], pdev); + pci_epc_destroy(zf_ep->dpu_ep_array[id]->epc); + zf_ep->dpu_ep_array[id]->zf_pdev->dev.driver = NULL; + zf_ep->dpu_ep_array[id]->zf_pdev_dma->dev.driver = NULL; + platform_device_unregister(zf_ep->dpu_ep_array[id]->zf_pdev); + platform_device_unregister(zf_ep->dpu_ep_array[id]->zf_pdev_dma); + kfree(zf_ep->dpu_ep_array[id]); +} + +static int zf_dev_map(struct pci_dev *pdev) +{ + zf_ep->dbi_vaddr = ioremap(zf_ep->dbi_paddr, PCIE_DPU_EP_DBI_SIZE * PCIE_DPU_EP_NUM); + if (!zf_ep->dbi_vaddr) + { + pci_release_mem_regions(pdev); + return -ENODEV; + } + + zf_ep->mpf_vaddr = ioremap(zf_ep->mpf_paddr, pci_resource_len(pdev, BAR_0)); + if (!zf_ep->mpf_vaddr) + { + iounmap(zf_ep->dbi_vaddr); + pci_release_mem_regions(pdev); + return -ENODEV; + } + + return 0; +} + +static void zf_dev_unmap(struct pci_dev *pdev) +{ + if (zf_ep->dbi_vaddr) + iounmap(zf_ep->dbi_vaddr); + if (zf_ep->mpf_vaddr) + iounmap(zf_ep->mpf_vaddr); + pci_release_mem_regions(pdev); +} + +static int pci_zte_epc_dev_init(struct pci_dev *pdev, int num) +{ + int i = 0, j = 0, ret = 0; + + for (i = 0; i < num; i++) + { + ret = pci_zte_epc_dev_init_one(pdev, i); + if (zf_ep->dpu_ep_array[i] == NULL) + { + DH_LOG_ERR(MODULE_MPF, "pci_zte_epc_dev_init_one failed\n"); + for (j = 0; j < i; j++) + { + pci_zte_epc_dev_free_one(pdev, j); + } + return -ENODEV; + } + DH_LOG_INFO(MODULE_MPF, "pci_zte_epc_dev_init_ep%d success!\n", i); + + ret = pcie_zf_dma_init(zf_ep->dpu_ep_array[i], pdev); + if (ret) + { + DH_LOG_ERR(MODULE_MPF, "pcie_zf_dma_init failed\n"); + return ret; + } + } + + return ret; +} + +int pcie_zte_zf_epc_init(struct dh_core_dev *dh_dev, const struct pci_device_id *id) +{ + int ret = -ENXIO; + u32 val = 0; + + dh_dev->zf_ep = (struct pcie_zf_ep *)kzalloc(sizeof(struct pcie_zf_ep), GFP_KERNEL); + if (!dh_dev->zf_ep) + { + DH_LOG_ERR(MODULE_MPF, "kzalloc zf_ep err\n"); + return -ENODEV; + } + zf_ep = dh_dev->zf_ep; + + dh_dev->zf_ep->dpu_ep_array = kzalloc(PCIE_DPU_EP_NUM * sizeof(struct pcie_dpu_ep *), GFP_KERNEL); + if (!dh_dev->zf_ep->dpu_ep_array) + { + DH_LOG_ERR(MODULE_MPF, "kzalloc dpu_ep_array err\n"); + ret = -ENODEV; + goto free_zf_ep; + } + + dh_dev->zf_ep->dbi_paddr = pci_resource_start(dh_dev->pdev, BAR_2); + dh_dev->zf_ep->mpf_paddr = pci_resource_start(dh_dev->pdev, BAR_0); + dh_dev->zf_ep->ob_size = pci_resource_len(dh_dev->pdev, BAR_0) >> EP_ID_LEN; + dh_dev->zf_ep->dpu_ep_num = PCIE_DPU_EP_NUM; + ret = zf_dev_map(dh_dev->pdev); + if (ret) + { + DH_LOG_ERR(MODULE_MPF, "zf_dev_map err\n"); + goto free_dpu_ep_array; + } + + pcie_zf_read(dh_dev->zf_ep->dbi_vaddr, 4, &val); + if (val == 0x0 || val == 0xffffffff) + { + DH_LOG_ERR(MODULE_MPF, "the dbi_addr is err!\n"); + ret = -EINVAL; + goto free_dpu_ep_array; + } + + ret = pci_zte_epc_dev_init(dh_dev->pdev, PCIE_DPU_EP_NUM); + if (ret) + { + goto unmap; + } + + DH_LOG_INFO(MODULE_MPF, "INFO:the EP0~3 pci_dev created successed!\n"); + return ret; + +unmap: + zf_dev_unmap(dh_dev->pdev); +free_dpu_ep_array: + kfree(dh_dev->zf_ep->dpu_ep_array); +free_zf_ep: + kfree(dh_dev->zf_ep); + return ret; +} + +void pcie_zte_zf_epc_free(struct dh_core_dev *dh_dev) +{ + int ep_id = 0; + + DH_LOG_INFO(MODULE_MPF, "INFO===>TODO:removed can't finish!\n"); + + zf_dev_unmap(dh_dev->pdev); + for (ep_id = 0; ep_id < PCIE_DPU_EP_NUM; ep_id++) + { + pci_zte_epc_dev_free_one(dh_dev->pdev, ep_id); + } + kfree(dh_dev->zf_ep->dpu_ep_array); + kfree(dh_dev->zf_ep); + DH_LOG_INFO(MODULE_MPF, "the EP0~3 pci_dev removed successed!\n"); +} diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/epc/pcie-zte-zf-epc.h b/src/net/drivers/net/ethernet/dinghai/zf_mpf/epc/pcie-zte-zf-epc.h new file mode 100644 index 0000000..c275c1b --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/epc/pcie-zte-zf-epc.h @@ -0,0 +1,244 @@ +#ifndef __PCIE_ZTE_ZF_EPC_H +#define __PCIE_ZTE_ZF_EPC_H + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef _cplusplus +extern "C" { +#endif + +#define ZF_DISABLE 0x0 +#define ZF_ENABLE 0x1 + +// ZF INFO +#define PCI_VENDOR_ID_ZTE 0x1cf2 +#define PCIE_DPU_EP_CLASS_NAME 32 + +#define PCIE_DPU_EP_NUM 4 +#define EP_ID_LEN 4 +#define PCIE_DPU_PF_NUMS 8 +#define PCIE_DPU_IATU_NUM 41 +#define PCIE_VF_BARS_OFF 7 +#define PCIE_BAR0_ADDR_SET(off) (((off) & 0xFFFF) | (((off) & 0xFFFFFFFFFFFF0000) << EP_ID_LEN)) + +#define PCIE_DPU_PF_INITIAL_ID 0x000016c3 +#define PCIE_DPU_PF_DEFAUTL_ID1 0x10011af4 +#define PCIE_DPU_PF_DEFAUTL_ID2 0x80531cf2 +#define PCIE_DPU_PF_DEFAUTL_ID3 0x000016c3 +#define PCIE_DPU_PF_DEFAUTL_ID4 0x80331cf2 +#define PCIE_DPU_PF_DEFAUTL_CLASSCODE 0x02000000 + +// dpu func_no&addr set +#define PCIE_DPU_EP_FUNC_IS_VF BIT(7) +#define PCIE_DPU_EP_GET_PF_NO 0x7f +#define DBI_VF_CFG_OFFSET_BIT 4 +#define VF_ACT_BIT BIT(3) +#define isPF(func_no) ((func_no & PCIE_DPU_EP_FUNC_IS_VF) ? 0 : 1) + +#define ZF_PREFIX_ADDR 0x9000000000000000 +#define DEFAULT_DBI_ATU_OFFSET 0x6000000 +#define PCIE_DPU_EP_DBI_SIZE 0x8000000 +#define PCIE_DPU_EP_OUTBOUND_SIZE 0x40000000 +#define PCIE_DPU_EP_DBI2_OFFSET 0x2000000 +#define PCIE_DPU_MPF_CSR_OFFSET 0x14000 +#define PCIE_DPU_MPF_CSR_ADDR(offset) PCIE_BAR0_ADDR_SET(PCIE_DPU_MPF_CSR_OFFSET + offset) +#define PCIE_DPU_EP_FUNC_CFG_SIZE 0X1000 +#define PCIE_DPU_EP_CSR_SIZE 0x2000 +#define PCIE_DPU_EP_CSR_PRST_ADDR 0x448 +#define PCIE_DPU_EP_CSR_VIRT_ADDR 0x1200 +#define BAR4_DEFAULT_SIZE 0x10000 + +// epc features +#define PCIE_DPU_EP_REAERVED_BAR 0x30 +#define PCIE_DPU_EP_BAR_FIXED_64BIT 0x15 +#define PCIE_DPU_EP_ALIGN 0x1000 + +#define EP_ID_SHIFT 16 +#define EP_ADDR_MASK ((1 << EP_ID_SHIFT) - 1) +#define EP_DPU_PA(addr, ep_id) \ + ((addr & ~EP_ADDR_MASK) << EP_ID_LEN | (addr & EP_ADDR_MASK) | \ + ep_id << EP_ID_SHIFT) + +// PCIE Register +#if 1 +#define LINK_WAIT_MAX_RETRIES 10 +#define LINK_WAIT_USLEEP_MIN 90000 +#define LINK_WAIT_USLEEP_MAX 100000 +#define LINK_WAIT_MAX_IATU_RETRIES 0x10 +#define LINK_WAIT_IATU 10 + +// PCIE_PORT_DEBUG1 cap +#define PCIE_PORT_DEBUG1 0x72C +#define PCIE_PORT_DEBUG1_ZTE_ZF_LINK_UP BIT(4) +#define PCIE_PORT_DEBUG1_LINK_IN_TRAINING BIT(29) + +// PCIE CAP +#define PCIE_ECAP_POINTER_OFF 0x100 +#define PCIE_ECAP_VSEC_ID 0x0B + +#define PCIE_NEXT_BAR_OFFSET 0x4 +#define PCIE_DEFAULT_BAR_FLAG (BIT(3) | BIT(2)) +#define PCIE_SRIOV_ECAP_DEVICE_ID 0x1a +#define PCIE_SRIOV_ECAP_BAR0_OFFSET 0x24 +#define PCIE_SRIOV_ECAP_BAR4_OFFSET 0x34 +#define PCIE_SRIOV_CTRL 0x08 +#define PCIE_SRIOV_TOTAL_VFS 0x0e +#define PCIE_SRIOV_CTRL_VFE 0x01 + +#define PCIE_MSI_ADDR_LO 0x820 +#define PCIE_MSI_ADDR_HI 0x824 +#define PCIE_MSI_INTR0_ENABLE 0x828 +#define PCIE_MSI_INTR0_MASK 0x82C +#define PCIE_MSI_INTR0_STATUS 0x830 + +#define PCIE_PORT_MULTI_LANE_CTRL 0x8C0 +#define PORT_MLTI_UPCFG_SUPPORT BIT(7) + +/* ATU register*/ +#define PCIE_ATU_CR1 0x904 +#define PCIE_ATU_TYPE_MEM 0x0 +#define PCIE_ATU_TYPE_IO 0x2 +#define PCIE_ATU_FUNC_NUM(pf) ((pf) << 20) +#define PCIE_ATU_FUNC_NUM_MASK 0xF00000 +#define PCIE_ATU_BAR_NUM_MASK 0x700 +#define PCIE_ATU_ENABLE BIT(31) +#define PCIE_ATU_BAR_MODE_ENABLE BIT(30) +#define PCIE_ATU_CFG_SHIFT_MODE BIT(28) +#define PCIE_ATU_DMA_BYPSS BIT(27) +#define PCIE_ATU_FUNC_NUM_MATCH_EN BIT(19) +#define PCIE_ATU_VFBAR_MATCH_MODE_ENABLE BIT(26) +#define PCIE_ATU_VF_MATCH_ENABLE BIT(20) +#define PCIE_ATU_OB_VF_ACTIVE BIT(31) + +/*MSIX register*/ +#define MSIX_ADDRESS_MATCH_LOW_OFF 0x940 +#define MSI_ADDRESS_MATCH_EN BIT(0) +#define MSIX_ADDRESS_MATCH_HIGH_OFF 0x944 +#define MSIX_DOORBELL_OFF 0x948 +#define MSIX_DOORBELL_PF 24 +#define MSIX_DOORBELL_PF_MASK 0x1F +#define MSIX_DOORBELL_VF 16 +#define MSIX_DOORBELL_VF_MASK 0xFF +#define MSIX_DOORBELL_VF_ACTIVE BIT(15) +#define MSIX_DOORBELL_VECTOR 0 +#define MSIX_DOORBELL_VECTOR_MASK 0x7FF + +#define LINK_WAIT_DMA 20 + +#define PCIE_MISC_CONTROL_1_OFF 0x8BC +#define PCIE_DBI_RO_WR_EN BIT(0) + +#define PCIE_MSIX_DOORBELL 0x948 +#define PCIE_MSIX_DOORBELL_PF_SHIFT 24 +#define PCIE_MSIX_DOORBELL_VF_SHIFT 16 +#define MSIX_DOORBELL_VF_ACTIVE BIT(15) + +/* Register address builder */ +#define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region) ((region) << 9) +#define PCIE_GET_ATU_INB_UNR_REG_OFFSET(region) (((region) << 9) | BIT(8)) + +#define PCIE_ATU_UNR_REGION_CTRL1 0x00 +#define PCIE_ATU_UNR_REGION_CTRL2 0x04 +#define PCIE_ATU_UNR_LOWER_BASE 0x08 +#define PCIE_ATU_UNR_UPPER_BASE 0x0C +#define PCIE_ATU_UNR_LOWER_LIMIT 0x10 +#define PCIE_ATU_UNR_LOWER_TARGET 0x14 +#define PCIE_ATU_UNR_UPPER_TARGET 0x18 +#define PCIE_ATU_UNR_REGION_CTRL3 0x1c +#define PCIE_ATU_UNR_UPPER_LIMIT 0x20 +#define PCIE_ATU_INCREASE_REGION_SIZE BIT(13) + +#endif + +enum pcie_dpu_func_type { + PCIE_FUNC_TYPE_PF = 0, + PCIE_FUNC_TYPE_VF, + PCIE_FUNC_TYPE_NUM +}; + +enum pcie_dpu_as_type { + PCIE_DPU_AS_UNKNOWN, + PCIE_DPU_AS_MEM, + PCIE_DPU_AS_IO, +}; + +enum pcie_dpu_region_type { + PCIE_DPU_REGION_UNKNOWN, + PCIE_DPU_REGION_INBOUND, + PCIE_DPU_REGION_OUTBOUND, +}; + +struct pcie_dpu_ep_func { + struct list_head list; + u8 func_no; + u8 vfunc_no; + u8 msi_cap; /* MSI capability offset */ + u8 msix_cap; /* MSI-X capability offset */ +}; + +struct pcie_dpu_ep { + int ep_id; + int permissible_pf_map; + struct pci_epc *epc; + struct platform_device *zf_pdev; + struct platform_device *zf_pdev_dma; + struct dma_device *wr_dd; + struct dma_device *rd_dd; + + void __iomem *dbi_base; + void __iomem *atu_base; + + struct list_head func_list; + int bar_to_atu[PCIE_DPU_PF_NUMS][(PCI_STD_NUM_BARS * 2) + 1]; + int vf_total_num[PCIE_DPU_PF_NUMS]; + phys_addr_t *ob_src_addr; + unsigned long *ib_window_map; + unsigned long *ob_window_map; + spinlock_t ib_window_lock; + u32 num_ib_windows; + u32 num_ob_windows; +}; + +struct pcie_zf_ep { + unsigned long dbi_paddr; + unsigned long mpf_paddr; + unsigned long ob_size; + void __iomem *dbi_vaddr; + void __iomem *mpf_vaddr; + int dpu_ep_num; + struct pcie_dpu_ep **dpu_ep_array; + struct device_driver *dma_driver; +}; + +int pcie_zte_zf_epc_init(struct dh_core_dev *dh_dev, const struct pci_device_id *id); +int pcie_zf_dma_init(struct pcie_dpu_ep *dpu_dev, struct pci_dev *pdev); +void pcie_zte_zf_epc_free(struct dh_core_dev *dh_dev); +void pcie_zf_dma_free(struct pcie_dpu_ep *dpu_dev, struct pci_dev *pdev); +int zf_pcie_get_hdma_chan(struct pci_epc *epc, u8 func_no, u8 vfunc_no, struct dma_chan **rchan, struct dma_chan **wchan); +u32 cfg_phy_rmw(u64 phy_addr, u32 value, u32 mask); +int pcie_zte_epc_ob_read(struct pci_epc *epc, phys_addr_t phys_addr, unsigned int size, unsigned int *val); + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/epc/pcie-zte-zf-hdma.c b/src/net/drivers/net/ethernet/dinghai/zf_mpf/epc/pcie-zte-zf-hdma.c new file mode 100644 index 0000000..6ed82dd --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/epc/pcie-zte-zf-hdma.c @@ -0,0 +1,748 @@ +#include "pcie-zte-zf-hdma.h" + +static struct task_struct *callback_thread[PCIE_DPU_EP_NUM]; + +static int __attribute__((unused)) cfg_phy_write(u32 value, u64 PhyAddr) +{ + void __iomem *virt_addr = NULL; + u64 tmp_addr = 0; + u64 offset = 0; + u64 size = 0; + + offset = PhyAddr % 0x1000; + if (PhyAddr < offset) + { + DH_LOG_ERR(MODULE_MPF, "data overflow! PhyAddr=0x%llx, offset=0x%llx\n", PhyAddr, offset); + return PCIBIOS_BAD_REGISTER_NUMBER; + } + else + { + tmp_addr = PhyAddr - offset; + } + + if (offset <= (0x1000 - 4)) + { + size = 0x1000; + } + else + { + size = 2 * 0x1000; + } + + virt_addr = ioremap(tmp_addr, size); + if (NULL == virt_addr) + { + DH_LOG_ERR(MODULE_MPF, "cfg_write ioremap failed!\n"); + return PCIBIOS_BAD_REGISTER_NUMBER; + } + + writel(value, (virt_addr + offset)); + + iounmap(virt_addr); + return 0; +} + +static inline struct zf_hdma_chan *to_zf_hdma_chan(struct dma_chan *chan) +{ + return container_of(chan, struct zf_hdma_chan, zxdh_vc.chan); +} + +static u64 zte_pcie_dma_atu_addr_remapping(u64 addr_input) +{ + u64 addr_output = 0; + // DMA and ATU地址重映射，将地址的bit12~18左移4位，设置bit15 = 0 + addr_output = (((addr_input & (0x7F << 12)) << 4) | (addr_input & 0xFFF)) & (~(1UL << 15)); + + return addr_output; +} + +static inline void read_ch(struct zf_hdma_chan *zf_chan, u32 is_read, int offset, u32 *val) +{ + u64 register_offet = 0; + + void __iomem *addr = zf_chan->base_addr; + + register_offet = zte_pcie_dma_atu_addr_remapping(((u64)zf_chan->id * (u64)ZF_HDMA_PER_CHANNEL_SIZE)) + ((u64)is_read * (u64)ZF_HDMA_RDCH_OFFSET); + *val = readl(addr + register_offet + offset); +} + +static inline void write_ch(struct zf_hdma_chan *zf_chan, u32 is_read, int offset, u32 val) +{ + u64 register_off = 0; + void __iomem *addr = zf_chan->base_addr; + + register_off = zte_pcie_dma_atu_addr_remapping(((u64)zf_chan->id * (u64)ZF_HDMA_PER_CHANNEL_SIZE)) + ((u64)is_read * (u64)ZF_HDMA_RDCH_OFFSET); + writel(val, addr + register_off + offset); +} + +static inline void rmw_ch(struct zf_hdma_chan *zf_chan, u32 is_read, int offset, u32 val, u32 mask) +{ + u32 reg_val = 0; + + read_ch(zf_chan, is_read, offset, ®_val); + reg_val &= (~mask); + reg_val |= (val & mask); + write_ch(zf_chan, is_read, offset, reg_val); +} + +static int zf_hdma_alloc_chan_resources(struct dma_chan *chan) +{ + u32 is_read = 0; + // struct zf_hdma_chan *zf_chan = to_zf_hdma_chan(chan); + + if (chan->device->directions == BIT(DMA_MEM_TO_DEV)) + { + is_read = HDMA_RD; + } + else if (chan->device->directions == BIT(DMA_DEV_TO_MEM)) + { + is_read = HDMA_WR; + } + else + { + DH_LOG_ERR(MODULE_MPF, "err direct\n"); + return -EINVAL; + } + + /* 开启dma通道中断 */ + // rmw_ch(zf_chan, is_read, HDMA_INT_SETUP_OFF, 0x0 << HDMA_INT_MASK_BIT, HDMA_INT_MASK << HDMA_INT_MASK_BIT); + // rmw_ch(zf_chan, is_read, HDMA_INT_SETUP_OFF, 0x1 << HDMA_LSIE_BIT, HDMA_LSIE_MASK << HDMA_LSIE_BIT); + + return 0; +} + +static void zf_hdma_free_chan_resources(struct dma_chan *chan) +{ + u32 is_read = 0; + // struct zf_hdma_chan *zf_chan = to_zf_hdma_chan(chan); + + if (chan->device->directions == BIT(DMA_MEM_TO_DEV)) + { + is_read = HDMA_RD; + } + else if (chan->device->directions == BIT(DMA_DEV_TO_MEM)) + { + is_read = HDMA_WR; + } + else + { + DH_LOG_ERR(MODULE_MPF, "err direct\n"); + return; + } + + /* 释放dma通道中断 */ + // rmw_ch(zf_chan, is_read, HDMA_INT_SETUP_OFF, 0x7 << HDMA_INT_MASK_BIT, HDMA_INT_MASK << HDMA_INT_MASK_BIT); + // rmw_ch(zf_chan, is_read, HDMA_INT_SETUP_OFF, 0x0 << HDMA_LSIE_BIT, HDMA_LSIE_MASK << HDMA_LSIE_BIT); +} + +static int zf_hdma_device_config(struct dma_chan *chan, struct dma_slave_config *config) +{ + // struct zf_hdma_chan *zf_chan = to_zf_hdma_chan(chan); + // u32 is_read = HDMA_WR; + + return 0; +} + +static struct dma_async_tx_descriptor *zf_hdma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, size_t len, unsigned long flags) +{ + u32 is_read = HDMA_WR; + struct zf_hdma_sqe *sqe = NULL, *tem_sqe = NULL; + struct zf_hdma_tx *tx = NULL, *tem_tx = NULL; + struct dma_async_tx_descriptor *tx_desc = NULL; + struct zf_hdma_chan *zf_chan = to_zf_hdma_chan(chan); + int tx_num = 0; + + DH_LOG_DEBUG(MODULE_MPF, "enter\n"); + if (chan->device->directions == BIT(DMA_MEM_TO_DEV)) + { + is_read = HDMA_RD; + dest |= ZF_PREFIX_ADDR; + } + else if (chan->device->directions == BIT(DMA_DEV_TO_MEM)) + { + is_read = HDMA_WR; + src |= ZF_PREFIX_ADDR; + } + else + { + DH_LOG_ERR(MODULE_MPF, "err direct\n"); + return NULL; + } + + tem_sqe = zf_chan->sqe_list; + sqe = devm_kzalloc(&zf_chan->ep_pdev->dev, sizeof(struct zf_hdma_sqe), GFP_KERNEL); + if (!sqe) + { + DH_LOG_ERR(MODULE_MPF, "err alloc sqe\n"); + return NULL; + } + sqe->length = len; + sqe->src_addr = src; + sqe->dst_addr = dest; + + while (NULL != tem_sqe->next) + { + tem_sqe = tem_sqe->next; + } + tem_sqe->next = sqe; + + tx_desc = zxdh_vchan_tx_prep(&zf_chan->zxdh_vc, &zf_chan->zxdh_vd, flags); + tem_tx = zf_chan->tx_list; + tx = devm_kzalloc(&zf_chan->ep_pdev->dev, sizeof(struct zf_hdma_tx), GFP_KERNEL); + if (!tx) + { + DH_LOG_ERR(MODULE_MPF, "err alloc tx\n"); + devm_kfree(&zf_chan->ep_pdev->dev, sqe); + return NULL; + } + tx->tx_desc = tx_desc; + + while (NULL != tem_tx->next) + { + tem_tx = tem_tx->next; + tx_num++; + } + tx->tx_id = tx_num; + tem_tx->next = tx; + + return tx_desc; +} + +static int zf_hdma_terminate_all(struct dma_chan *chan) +{ + u32 is_read = HDMA_WR; + struct zf_hdma_chan *zf_chan = to_zf_hdma_chan(chan); + + if (chan->device->directions == BIT(DMA_MEM_TO_DEV)) + { + is_read = HDMA_RD; + } + + write_ch(zf_chan, is_read, HDMA_DOORBELL_OFF, HDMA_DOORBELL_STOP); + + return 0; +} + +static enum dma_status zf_hdma_tx_status(struct dma_chan *chan, dma_cookie_t cookie, struct dma_tx_state *txstate) +{ + return 0; +} + +static struct dma_async_tx_descriptor *zf_hdma_device_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, unsigned int len, enum dma_transfer_direction direction, unsigned long flags, void *context) +{ + struct zf_hdma_chan *zf_chan = to_zf_hdma_chan(chan); + u32 is_read = HDMA_WR; + + DH_LOG_INFO(MODULE_MPF, "enter\n"); + + if (chan->device->directions == BIT(DMA_MEM_TO_DEV)) + { + is_read = HDMA_RD; + } + else if (chan->device->directions == BIT(DMA_DEV_TO_MEM)) + { + is_read = HDMA_WR; + } + else + { + DH_LOG_ERR(MODULE_MPF, "err direct\n"); + return NULL; + } + + return zxdh_vchan_tx_prep(&zf_chan->zxdh_vc, &zf_chan->zxdh_vd, flags); +} + +static struct dma_async_tx_descriptor *zf_hdma_device_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t paddr, size_t len, size_t count, enum dma_transfer_direction direction, unsigned long flags) +{ + struct zf_hdma_chan *zf_chan = to_zf_hdma_chan(chan); + + return zxdh_vchan_tx_prep(&zf_chan->zxdh_vc, &zf_chan->zxdh_vd, flags); +} + +static void free_used_sqe(struct zf_hdma_chan *zf_chan) +{ + struct zf_hdma_sqe *temp = NULL; + + temp = zf_chan->sqe_list->next; + zf_chan->sqe_list->next = zf_chan->sqe_list->next->next; + + devm_kfree(&zf_chan->ep_pdev->dev, temp); +} + +static void zf_hdma_register_set(struct zf_hdma_chan *zf_chan, u32 is_read, struct zf_hdma_sqe *sqe) +{ + /* DMA Engine enable */ + write_ch(zf_chan, is_read, HDMA_EN_OFF, HDMA_EN); + + /* DMA transfer Size */ + write_ch(zf_chan, is_read, HDMA_XFERSIZE_OFF, (u32)sqe->length); + + /* DMA SAR & DAR */ + write_ch(zf_chan, is_read, HDMA_SAR_LOW_OFF, (sqe->src_addr & 0xffffffff)); + write_ch(zf_chan, is_read, HDMA_SAR_HIGH_OFF, ((sqe->src_addr >> 32) & 0xffffffff)); + write_ch(zf_chan, is_read, HDMA_DAR_LOW_OFF, (sqe->dst_addr & 0xffffffff)); + write_ch(zf_chan, is_read, HDMA_DAR_HIGH_OFF, ((sqe->dst_addr >> 32) & 0xffffffff)); + + /* func_no */ + write_ch(zf_chan, is_read, HDMA_FUNC_NUM_OFF, ((zf_chan->func_no & PCIE_DPU_EP_GET_PF_NO) | (zf_chan->vfunc_no << HDMA_FUNC_NUM_OFF_VF) | (!isPF(zf_chan->func_no) << HDMA_FUNC_NUM_OFF_VF_ENABLE))); + + /* DMA Doorbell */ + write_ch(zf_chan, is_read, HDMA_DOORBELL_OFF, HDMA_DOORBELL_START); + return; +} + +static void zf_hdma_issue_pending(struct dma_chan *chan) +{ + // u32 is_read = HDMA_WR; + unsigned long flags = 0; + struct zf_hdma_chan *zf_chan = NULL; + struct zf_hdma_tx *tx_temp = NULL; + + zf_chan = to_zf_hdma_chan(chan); + + tx_temp = zf_chan->tx_list->next; + while (tx_temp->next != NULL) + { + tx_temp = tx_temp->next; + } + + tx_temp->callback = tx_temp->tx_desc->callback; + tx_temp->callback_param = tx_temp->tx_desc->callback_param; + + spin_lock_irqsave(&zf_chan->zxdh_vc.lock, flags); + zxdh_vchan_issue_pending(&zf_chan->zxdh_vc); + spin_unlock_irqrestore(&zf_chan->zxdh_vc.lock, flags); + + return; +} + +static void free_used_tx(struct zf_hdma_chan *zf_chan) +{ + struct zf_hdma_tx *temp = NULL; + + temp = zf_chan->tx_list->next; + zf_chan->tx_list->next = zf_chan->tx_list->next->next; + + devm_kfree(&zf_chan->ep_pdev->dev, temp); +} + +int zf_hdma_wr_handler(void *data) +{ + u32 chan_status, chan_int_status; + struct pcie_dpu_ep *dpu_dev = data; + struct dma_chan *chan = NULL; + struct zf_hdma_chan *zf_chan = NULL; + struct zf_hdma_tx *zf_tx_desc = NULL; + + list_for_each_entry(chan, &dpu_dev->wr_dd->channels, device_node) + { + zf_chan = to_zf_hdma_chan(chan); + if (!zf_chan->tx_list->next || !zf_chan->tx_list->next->tx_desc || !zf_chan->tx_list->next->callback) + { + DH_LOG_INFO(MODULE_MPF, "wr_zf_chan%d is not used!\n", zf_chan->id); + continue; + } + else + { + zf_tx_desc = zf_chan->tx_list->next; + } + read_ch(zf_chan, HDMA_WR, HDMA_STATUS_OFF, &chan_status); + read_ch(zf_chan, HDMA_WR, HDMA_INT_STATUS_OFF, &chan_int_status); + + // if (((chan_status & HDMA_STATUS_OFF_STATUS) & HDMA_STATUS_STOPPED) && (chan_int_status & HDMA_STOP_INT_STATUS)) + // { + spin_lock(&zf_chan->zxdh_vc.lock); + zf_tx_desc->callback(zf_tx_desc->callback_param); + free_used_tx(zf_chan); + zf_chan->is_busy = HDMA_CHAN_IDLE; + spin_unlock(&zf_chan->zxdh_vc.lock); + break; + // } + } + + return 0; +} + +int zf_hdma_rd_handler(void *data) +{ + u32 chan_status = 0, chan_int_status = 0; + struct pcie_dpu_ep *dpu_dev = data; + struct dma_chan *chan = NULL; + struct zf_hdma_chan *zf_chan = NULL; + struct zf_hdma_tx *zf_tx_desc = NULL; + + list_for_each_entry(chan, &dpu_dev->rd_dd->channels, device_node) + { + zf_chan = to_zf_hdma_chan(chan); + if (!zf_chan->tx_list->next || !zf_chan->tx_list->next->tx_desc || !zf_chan->tx_list->next->callback) + { + DH_LOG_INFO(MODULE_MPF, "rd_zf_chan%d is not used!\n", zf_chan->id); + continue; + } + else + { + zf_tx_desc = zf_chan->tx_list->next; + } + read_ch(zf_chan, HDMA_RD, HDMA_STATUS_OFF, &chan_status); + read_ch(zf_chan, HDMA_RD, HDMA_INT_STATUS_OFF, &chan_int_status); + + // if (((chan_status & HDMA_STATUS_OFF_STATUS) & HDMA_STATUS_STOPPED) && (chan_int_status & HDMA_STOP_INT_STATUS)) + // { + spin_lock(&zf_chan->zxdh_vc.lock); + zf_tx_desc->callback(zf_tx_desc->callback_param); + free_used_tx(zf_chan); + zf_chan->is_busy = HDMA_CHAN_IDLE; + spin_unlock(&zf_chan->zxdh_vc.lock); + break; + // } + } + + return 0; +} + +static void zf_hdma_desc_free(struct zxdh_virt_dma_desc *zxdh_vd) +{ + dma_descriptor_unmap(&zxdh_vd->tx); +} + +static bool zf_dma_filter_fn(struct dma_chan *chan, void *node) +{ + unsigned long dev_node = (unsigned long)dev_to_node(&chan->dev->device); + return (dev_node == (unsigned long)node); +} + +struct dma_chan *zte_get_chan_for_dma(struct pci_epc *epc, u32 is_read) +{ + int node = 0; + dma_cap_mask_t dma_mask; + struct dma_chan *chan = NULL; + struct pcie_dpu_ep *ep = NULL; + + if (IS_ERR_OR_NULL(epc)) + { + DH_LOG_ERR(MODULE_MPF, "not found epc\n"); + return NULL; + } + + ep = epc_get_drvdata(epc); + if (!ep) + { + DH_LOG_ERR(MODULE_MPF, " not found ep\n"); + return NULL; + } + + if (is_read) + { + node = dev_to_node(ep->rd_dd->dev); + } + else + { + node = dev_to_node(ep->wr_dd->dev); + } + + dma_cap_zero(dma_mask); + dma_cap_set(DMA_MEMCPY, dma_mask); + chan = dma_request_channel(dma_mask, zf_dma_filter_fn, (void *)(unsigned long)node); + + return chan; +} +EXPORT_SYMBOL_GPL(zte_get_chan_for_dma); + +void zte_zf_pcie_set_pfvf_no(struct dma_chan *chan, u8 func_no, u8 vfunc_no) +{ + struct zf_hdma_chan *zf_chan = to_zf_hdma_chan(chan); + + DH_LOG_INFO(MODULE_MPF, "func_no = 0x%x, vfunc_no = 0x%x\n",func_no, vfunc_no); + + zf_chan->func_no = func_no; + zf_chan->vfunc_no = vfunc_no; +} +EXPORT_SYMBOL_GPL(zte_zf_pcie_set_pfvf_no); + +int zf_pcie_get_hdma_chan(struct pci_epc *epc, u8 func_no, u8 vfunc_no, + struct dma_chan **rchan, struct dma_chan **wchan) +{ + struct dma_chan *rch, *wch; + + wch = zte_get_chan_for_dma(epc, HDMA_WR); + if (IS_ERR_OR_NULL(wch)) + { + DH_LOG_ERR(MODULE_MPF, "failed to get write chan\n"); + return -EFAULT; + } + + rch = zte_get_chan_for_dma(epc, HDMA_RD); + if (IS_ERR_OR_NULL(rch)) + { + DH_LOG_ERR(MODULE_MPF, "failed to get read chan\n"); + dma_release_channel(rch); + return -EFAULT; + } + + zte_zf_pcie_set_pfvf_no(rch, func_no, vfunc_no); + zte_zf_pcie_set_pfvf_no(wch, func_no, vfunc_no); + + *rchan = rch; + *wchan = wch; + return 0; +} + +static int zf_hdma_virtual_channels_init(struct dma_device *dma_dev, struct pci_dev *pdev, void __iomem *addr) +{ + struct zf_hdma_chan *zf_chan = NULL; + u32 i = 0; + + INIT_LIST_HEAD(&dma_dev->channels); + + /* + * Register as many memcpy as we have physical channels, + * we won't always be able to use all but the code will have + * to cope with that situation. + */ + for (i = 0; i < (u32)ZF_HDMA_CHAN_NUM; i++) + { + zf_chan = devm_kzalloc(&pdev->dev, sizeof(*zf_chan), GFP_KERNEL); + if (!zf_chan) + { + // TODO free + return -ENOMEM; + } + zf_chan->sqe_list = devm_kzalloc(&pdev->dev, sizeof(struct zf_hdma_sqe), GFP_KERNEL); + if (!zf_chan->sqe_list) + { + // TODO free + return -ENOMEM; + } + zf_chan->tx_list = devm_kzalloc(&pdev->dev, sizeof(struct zf_hdma_tx), GFP_KERNEL); + if (!zf_chan->tx_list) + { + // TODO free + return -ENOMEM; + } + zf_chan->tx_list->tx_id = 0; + + zf_chan->id = i + ZF_HDMA_CHAN_FIRST_IDX; + zf_chan->ep_pdev = pdev; + zf_chan->base_addr = addr + ZF_HDMA_ADDR_OFFSET; + zf_chan->is_busy = HDMA_CHAN_IDLE; + + zf_chan->name = kasprintf(GFP_KERNEL, "chan%d", i); + if (!zf_chan->name) + return -ENOMEM; + + zf_chan->zxdh_vc.desc_free = zf_hdma_desc_free; + + zxdh_vchan_init(&zf_chan->zxdh_vc, dma_dev); + } + + return i; +} + +void zf_hdma_device_init(struct device *dev, struct dma_device *dd, u32 is_read) +{ + dd->device_alloc_chan_resources = zf_hdma_alloc_chan_resources; // 3,4,8,9 unneccessary + dd->device_free_chan_resources = zf_hdma_free_chan_resources; + dd->device_config = zf_hdma_device_config; + dd->device_tx_status = zf_hdma_tx_status; + dd->device_issue_pending = zf_hdma_issue_pending; // push pending transactions to hardware + dd->device_prep_dma_memcpy = zf_hdma_prep_dma_memcpy; + dd->device_terminate_all = zf_hdma_terminate_all; + dd->device_prep_slave_sg = zf_hdma_device_prep_slave_sg; // prepares a slave dma operation + dd->device_prep_dma_cyclic = zf_hdma_device_prep_dma_cyclic; // prepare a cyclic dma operation suitable for audio. The function takes a buffer of size buf_len. The callback function will be called after period_len bytes have been transferred. + + dd->chancnt = ZF_HDMA_CHAN_NUM; + dd->privatecnt = 0; + dd->copy_align = ZF_HDMA_ALIGN_SIZE; + dd->src_addr_widths = ZF_HDMA_DMA_BUSWIDTHS; + dd->dst_addr_widths = ZF_HDMA_DMA_BUSWIDTHS; + dd->residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT; + dd->dev = dev; + + if (is_read) + { + dd->directions = BIT(DMA_MEM_TO_DEV); + } + else + { + dd->directions = BIT(DMA_DEV_TO_MEM); + } + + dma_cap_zero(dd->cap_mask); + dma_cap_set(DMA_MEMCPY, dd->cap_mask); +} + +int callback_thread_function(void *data) +{ + u32 chan_status = 0; + struct pcie_dpu_ep *dpu_dev = data; + struct dma_chan *chan = NULL; + struct zf_hdma_chan *zf_chan = NULL; + struct zf_hdma_tx *zf_tx_desc = NULL; + + DH_LOG_INFO(MODULE_MPF, "enter!\n"); + + while (!kthread_should_stop()) + { + list_for_each_entry(chan, &dpu_dev->rd_dd->channels, device_node) + { + zf_chan = to_zf_hdma_chan(chan); + if (!zf_chan->tx_list->next || !zf_chan->tx_list->next->tx_desc || !zf_chan->tx_list->next->callback) + { + continue; + } + else + { + if ((zf_chan->sqe_list->next != NULL) && (zf_chan->is_busy == HDMA_CHAN_IDLE)) + { + zf_hdma_register_set(zf_chan, HDMA_RD, zf_chan->sqe_list->next); + zf_chan->is_busy = HDMA_CHAN_USED; + // DH_LOG_DEBUG(MODULE_MPF, "zf_chan->id:%d is_pending\n", zf_chan->id); + free_used_sqe(zf_chan); + } + + zf_tx_desc = zf_chan->tx_list->next; + // DH_LOG_DEBUG(MODULE_MPF, "rd_zf_chan%d is used!\n", zf_chan->id); + + read_ch(zf_chan, HDMA_RD, HDMA_STATUS_OFF, &chan_status); + + if ((chan_status & HDMA_STATUS_OFF_STATUS) == HDMA_STATUS_STOPPED && (zf_chan->is_busy == HDMA_CHAN_USED)) + { + spin_lock(&zf_chan->zxdh_vc.lock); + zf_tx_desc->callback(zf_tx_desc->callback_param); + free_used_tx(zf_chan); + spin_unlock(&zf_chan->zxdh_vc.lock); + zf_chan->is_busy = HDMA_CHAN_IDLE; + } + } + } + + list_for_each_entry(chan, &dpu_dev->wr_dd->channels, device_node) + { + zf_chan = to_zf_hdma_chan(chan); + if (!zf_chan->tx_list->next || !zf_chan->tx_list->next->tx_desc || !zf_chan->tx_list->next->callback) + { + continue; + } + else + { + if ((zf_chan->sqe_list->next != NULL) && (zf_chan->is_busy == HDMA_CHAN_IDLE)) + { + zf_hdma_register_set(zf_chan, HDMA_WR, zf_chan->sqe_list->next); + zf_chan->is_busy = HDMA_CHAN_USED; + // DH_LOG_DEBUG(MODULE_MPF, "zf_chan->id:%d is_pending\n", zf_chan->id); + free_used_sqe(zf_chan); + } + + zf_tx_desc = zf_chan->tx_list->next; + // DH_LOG_DEBUG(MODULE_MPF, "wr_zf_chan%d is used!\n", zf_chan->id); + read_ch(zf_chan, HDMA_WR, HDMA_STATUS_OFF, &chan_status); + + if ((chan_status & HDMA_STATUS_OFF_STATUS) == HDMA_STATUS_STOPPED && (zf_chan->is_busy == HDMA_CHAN_USED)) + { + spin_lock(&zf_chan->zxdh_vc.lock); + zf_tx_desc->callback(zf_tx_desc->callback_param); + free_used_tx(zf_chan); + spin_unlock(&zf_chan->zxdh_vc.lock); + zf_chan->is_busy = HDMA_CHAN_IDLE; + } + } + } + msleep(1); + } + + DH_LOG_INFO(MODULE_MPF, "Kernel thread is stopping\n"); + return 0; +} + +int pcie_zf_dma_init(struct pcie_dpu_ep *dpu_dev, struct pci_dev *pdev) +{ + int ret = 0; + int node = 0; + struct device *dev_wr = NULL, *dev_rd = NULL; + struct dma_device *wr_dd = NULL, *rd_dd = NULL; + + if (IS_ERR_OR_NULL(dpu_dev)) + { + DH_LOG_ERR(MODULE_MPF, "err input\n"); + return -ENOENT; + } + + dev_wr = &(dpu_dev->zf_pdev->dev); + dev_rd = &(dpu_dev->zf_pdev_dma->dev); + + node = dev_to_node(dev_wr); + + wr_dd = kzalloc_node(sizeof(struct dma_device), GFP_KERNEL, node); + if (!wr_dd) + { + DH_LOG_ERR(MODULE_MPF, "Error kzalloc node\n"); + return -ENODEV; + } + + rd_dd = kzalloc_node(sizeof(struct dma_device), GFP_KERNEL, node); + if (!rd_dd) + { + DH_LOG_ERR(MODULE_MPF, "Error kzalloc node\n"); + kfree(wr_dd); + return -ENODEV; + } + + zf_hdma_device_init(dev_wr, wr_dd, HDMA_WR); + zf_hdma_device_init(dev_rd, rd_dd, HDMA_RD); + + zf_hdma_virtual_channels_init(wr_dd, pdev, dpu_dev->dbi_base); + zf_hdma_virtual_channels_init(rd_dd, pdev, dpu_dev->dbi_base); + + ret = dma_async_device_register(wr_dd); + ret |= dma_async_device_register(rd_dd); + if (ret) + { + DH_LOG_ERR(MODULE_MPF, "dma_async_device_register failed\n"); + goto free_dma_device; + } + + dpu_dev->wr_dd = wr_dd; + dpu_dev->rd_dd = rd_dd; + DH_LOG_INFO(MODULE_MPF, "success!\n"); + + if (dpu_dev->ep_id >=0 && dpu_dev->ep_id < PCIE_DPU_EP_NUM) + { + callback_thread[dpu_dev->ep_id] = kthread_run(callback_thread_function, dpu_dev, "my_thread"); + if (callback_thread[dpu_dev->ep_id]) + { + DH_LOG_INFO(MODULE_MPF, "Thread created successfully\n"); + } + else + { + DH_LOG_ERR(MODULE_MPF, "Thread creation failed\n"); + } + } + + return 0; + +free_dma_device: + kfree(wr_dd); + kfree(rd_dd); + return ret; +} + +void pcie_zf_dma_free(struct pcie_dpu_ep *dpu_dev, struct pci_dev *pdev) +{ + + if (callback_thread[dpu_dev->ep_id]) + { + kthread_stop(callback_thread[dpu_dev->ep_id]); + DH_LOG_INFO(MODULE_MPF, "Thread created successfully\n"); + } + + if (dpu_dev->wr_dd) + { + dma_async_device_unregister(dpu_dev->wr_dd); + kfree(dpu_dev->wr_dd); + } + if (dpu_dev->rd_dd) + { + dma_async_device_unregister(dpu_dev->rd_dd); + kfree(dpu_dev->rd_dd); + } +} diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/epc/pcie-zte-zf-hdma.h b/src/net/drivers/net/ethernet/dinghai/zf_mpf/epc/pcie-zte-zf-hdma.h new file mode 100644 index 0000000..b958917 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/epc/pcie-zte-zf-hdma.h @@ -0,0 +1,159 @@ +#ifndef __PCIE_ZTE_ZF_HDMA_H +#define __PCIE_ZTE_ZF_HDMA_H + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "pcie-zte-zf-epc.h" +#include "virt-dma.h" + +#define ZF_HDMA_DRIVER_NAME "dh_hdma" +#define ZF_HDMA_ADDR_OFFSET (0x6800000) +#define ZF_HDMA_PER_CHANNEL_SIZE (0x200) +#define ZF_HDMA_RDCH_OFFSET (0x100) +#define HDMA_RD 1 +#define HDMA_WR 0 + +/* ZF HDMA init*/ +#define DPU_HDMA_CHAN_NUM (36) +#define ZF_HDMA_CHAN_FIRST_IDX (18) +#define ZF_HDMA_CHAN_NUM (DPU_HDMA_CHAN_NUM - ZF_HDMA_CHAN_FIRST_IDX) +#define ZF_HDMA_VIRT_CHAN_NUM ZF_HDMA_CHAN_NUM +#define ZF_HDMA_ALIGN_SIZE (1) +#define ZF_HDMA_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)) +#define ZF_HDMA_WAIT_SLEEP_TIMES (10) +#define ZF_HDMA_MAX_WAIT_TIMES (100) + +/* HDMA register*/ +#define HDMA_EN_OFF (0x0) +#define HDMA_DOORBELL_OFF (0x4) +#define HDMA_ELEM_PF_OFF (0x8) +#define HDMA_HANDSHAKE_OFF (0xc) +#define HDMA_LLP_LOW_OFF (0x10) +#define HDMA_LLP_HIGH_OFF (0x14) +#define HDMA_CYCLE_OFF (0x18) +#define HDMA_XFERSIZE_OFF (0x1c) +#define HDMA_XFERSIZE_OFF_COMPLETE (0x0) +#define HDMA_SAR_LOW_OFF (0x20) +#define HDMA_SAR_HIGH_OFF (0x24) +#define HDMA_DAR_LOW_OFF (0x28) +#define HDMA_DAR_HIGH_OFF (0x2c) +#define HDMA_WATERMARK_EN_OFF (0x30) +#define HDMA_CONTROL1_OFF (0x34) +#define HDMA_FUNC_NUM_OFF (0x38) +#define HDMA_FUNC_NUM_OFF_VF_ENABLE (16) +#define HDMA_FUNC_NUM_OFF_VF (17) +#define HDMA_QOS_OFF (0x3c) + +#define HDMA_STATUS_OFF (0x80) +#define HDMA_STATUS_OFF_STATUS (0x3) +#define HDMA_STATUS_STOPPED (0x3) +#define HDMA_INT_STATUS_OFF (0x84) +#define HDMA_STOP_INT_STATUS (0x1) +#define HDMA_INT_SETUP_OFF (0x88) +#define HDMA_INT_MASK_BIT (0x0) +#define HDMA_INT_MASK (0x7) +#define HDMA_LSIE_BIT (0x4) +#define HDMA_LSIE_MASK (0x1) +#define HDMA_INT_CLEAR_OFF (0x8c) +#define HDMA_MSI_STOP_LOW_OFF (0x90) +#define HDMA_MSI_STOP_HIGH_OFF (0x94) +#define HDMA_MSI_WATERMARK_LOW_OFF (0x98) +#define HDMA_MSI_WATERMARK_HIGH_OFF (0x9c) +#define HDMA_MSI_ABORT_LOW_OFF (0xa0) +#define HDMA_MSI_ABORT_HIGH_OFF (0xa4) +#define HDMA_MSI_MSI_MSGD_OFF (0xa8) + +/* HDMA register val*/ +#define HDMA_EN (BIT(0)) +#define HDMA_DOORBELL_STOP (BIT(1)) +#define HDMA_DOORBELL_START (BIT(0)) +#define HDMA_TRANSFER_DONE (0x3) + +/*LL module*/ +#define HDMA_LL_CONTROL_OFFSET 0x0 +#define HDMA_LL_SIZE_OFFSET 0x4 +#define HDMA_LL_SAR_LOW_OFFSET 0x8 +#define HDMA_LL_SAR_HIGH_OFFSET 0xc +#define HDMA_LL_DAR_LOW_OFFSET 0x10 +#define HDMA_LL_DAR_HIGH_OFFSET 0x14 +#define HDMA_LL_NEXT_ELEMENT 0x18 +#define HDMA_LL_LINK_CONTROL_OFFSET 0x0 +#define HDMA_LL_LINK_EMPTY_OFFSET 0x4 +#define HDMA_LL_LINK_POINTER_LOW_OFFSET 0x8 +#define HDMA_LL_LINK_POINTER_HIGH_OFFSET 0xc +#define HDMA_LL_DATA_CONTROL 0x1 +#define HDMA_LL_LINK_CONTROL 0x6 +#define HDMA_LL_PREFETCH 0x8 +#define PF_DEPTH 0x1f + +enum hdma_mode { + HDMA_MODE_LEGACY = 0, + HDMA_MODE_SLAVE, + HDMA_MODE_UNROLL +}; + +enum hdma_chan_status { + HDMA_CHAN_IDLE = 0, + HDMA_CHAN_USED, + HDMA_CHAN_UNDEFINE +}; + +struct zf_hdma_sqe { + size_t length; + dma_addr_t src_addr; + dma_addr_t dst_addr; + struct zf_hdma_sqe *next; +}; + +struct zf_hdma_tx { + int tx_id; + struct dma_async_tx_descriptor *tx_desc; + dma_async_tx_callback callback; + void *callback_param; + struct zf_hdma_tx *next; +}; + +struct hdma_ll_element { + size_t length; + dma_addr_t src_addr; + dma_addr_t dst_addr; +}; + +struct zf_hdma_chan { + u32 id; + struct list_head list; + const char *name; + struct pci_dev *ep_pdev; + struct zxdh_virt_dma_chan zxdh_vc; + struct zxdh_virt_dma_desc zxdh_vd; + void __iomem *base_addr; // 对应HDMA寄存器基址 + struct zf_hdma_sqe *sqe_list; + struct zf_hdma_tx *tx_list; + int is_busy; + u8 func_no; + u8 vfunc_no; +}; + +#endif \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/epc/virt-dma.c b/src/net/drivers/net/ethernet/dinghai/zf_mpf/epc/virt-dma.c new file mode 100644 index 0000000..98c516e --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/epc/virt-dma.c @@ -0,0 +1,135 @@ +#include +#include +#include +#include + +#include "virt-dma.h" + +static struct zxdh_virt_dma_desc *zxdh_to_virt_desc(struct dma_async_tx_descriptor *tx) +{ + return container_of(tx, struct zxdh_virt_dma_desc, tx); +} + +dma_cookie_t zxdh_vchan_tx_submit(struct dma_async_tx_descriptor *tx) +{ + struct zxdh_virt_dma_chan *zxdh_vc = zxdh_to_virt_chan(tx->chan); + struct zxdh_virt_dma_desc *zxdh_vd = zxdh_to_virt_desc(tx); + unsigned long flags; + dma_cookie_t cookie; + + spin_lock_irqsave(&zxdh_vc->lock, flags); + cookie = zxdh_dma_cookie_assign(tx); + + list_move_tail(&zxdh_vd->node, &zxdh_vc->desc_submitted); + spin_unlock_irqrestore(&zxdh_vc->lock, flags); + + pr_debug("%s vchan %p: txd %p[%x]: submitted\n", + __func__, zxdh_vc, zxdh_vd, cookie); + + return cookie; +} +EXPORT_SYMBOL_GPL(zxdh_vchan_tx_submit); + +/** + * zxdh_vchan_tx_desc_free - free a reusable descriptor + * @tx: the transfer + * + * This function frees a previously allocated reusable descriptor. The only + * other way is to clear the DMA_CTRL_REUSE flag and submit one last time the + * transfer. + * + * Returns 0 upon success + */ +int zxdh_vchan_tx_desc_free(struct dma_async_tx_descriptor *tx) +{ + struct zxdh_virt_dma_chan *zxdh_vc = zxdh_to_virt_chan(tx->chan); + struct zxdh_virt_dma_desc *zxdh_vd = zxdh_to_virt_desc(tx); + unsigned long flags; + + spin_lock_irqsave(&zxdh_vc->lock, flags); + list_del(&zxdh_vd->node); + spin_unlock_irqrestore(&zxdh_vc->lock, flags); + + pr_debug("%s vchan %p: txd %p[%x]: freeing\n", + __func__, zxdh_vc, zxdh_vd, zxdh_vd->tx.cookie); + + zxdh_vc->desc_free(zxdh_vd); + return 0; +} +EXPORT_SYMBOL_GPL(zxdh_vchan_tx_desc_free); + +struct zxdh_virt_dma_desc *zxdh_vchan_find_desc(struct zxdh_virt_dma_chan *zxdh_vc, + dma_cookie_t cookie) +{ + struct zxdh_virt_dma_desc *zxdh_vd; + + list_for_each_entry(zxdh_vd, &zxdh_vc->desc_issued, node) + if (zxdh_vd->tx.cookie == cookie) + return zxdh_vd; + + return NULL; +} +EXPORT_SYMBOL_GPL(zxdh_vchan_find_desc); + +/* + * This tasklet handles the completion of a DMA descriptor by + * calling its callback and freeing it. + */ +static void zxdh_vchan_complete(struct tasklet_struct *t) +{ + struct zxdh_virt_dma_chan *zxdh_vc = from_tasklet(zxdh_vc, t, task); + struct zxdh_virt_dma_desc *zxdh_vd, *_vd; + struct zxdh_dmaengine_desc_callback cb; + LIST_HEAD(head); + + spin_lock_irq(&zxdh_vc->lock); + list_splice_tail_init(&zxdh_vc->desc_completed, &head); + zxdh_vd = zxdh_vc->cyclic; + if (zxdh_vd) { + zxdh_vc->cyclic = NULL; + zxdh_dmaengine_desc_get_callback(&zxdh_vd->tx, &cb); + } else { + memset(&cb, 0, sizeof(cb)); + } + spin_unlock_irq(&zxdh_vc->lock); + + zxdh_dmaengine_desc_callback_invoke(&cb, &zxdh_vd->tx_result); + + list_for_each_entry_safe(zxdh_vd, _vd, &head, node) { + zxdh_dmaengine_desc_get_callback(&zxdh_vd->tx, &cb); + + list_del(&zxdh_vd->node); + zxdh_dmaengine_desc_callback_invoke(&cb, &zxdh_vd->tx_result); + zxdh_vchan_vdesc_fini(zxdh_vd); + } +} + +void zxdh_vchan_dma_desc_free_list(struct zxdh_virt_dma_chan *zxdh_vc, struct list_head *head) +{ + struct zxdh_virt_dma_desc *zxdh_vd, *_vd; + + list_for_each_entry_safe(zxdh_vd, _vd, head, node) { + list_del(&zxdh_vd->node); + zxdh_vchan_vdesc_fini(zxdh_vd); + } +} +EXPORT_SYMBOL_GPL(zxdh_vchan_dma_desc_free_list); + +void zxdh_vchan_init(struct zxdh_virt_dma_chan *zxdh_vc, struct dma_device *dmadev) +{ + zxdh_dma_cookie_init(&zxdh_vc->chan); + + spin_lock_init(&zxdh_vc->lock); + INIT_LIST_HEAD(&zxdh_vc->desc_allocated); + INIT_LIST_HEAD(&zxdh_vc->desc_submitted); + INIT_LIST_HEAD(&zxdh_vc->desc_issued); + INIT_LIST_HEAD(&zxdh_vc->desc_completed); + INIT_LIST_HEAD(&zxdh_vc->desc_terminated); + + tasklet_setup(&zxdh_vc->task, zxdh_vchan_complete); + + zxdh_vc->chan.device = dmadev; + list_add_tail(&zxdh_vc->chan.device_node, &dmadev->channels); +} +EXPORT_SYMBOL_GPL(zxdh_vchan_init); + diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/epc/virt-dma.h b/src/net/drivers/net/ethernet/dinghai/zf_mpf/epc/virt-dma.h new file mode 100644 index 0000000..eb1ff78 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/epc/virt-dma.h @@ -0,0 +1,221 @@ +#ifndef ZXDH_VIRT_DMA_H +#define ZXDH_VIRT_DMA_H + +#include +#include + +#include "dmaengine.h" + +struct zxdh_virt_dma_desc { + struct dma_async_tx_descriptor tx; + struct dmaengine_result tx_result; + /* protected by zxdh_vc.lock */ + struct list_head node; +}; + +struct zxdh_virt_dma_chan { + struct dma_chan chan; + struct tasklet_struct task; + void (*desc_free)(struct zxdh_virt_dma_desc *); + + spinlock_t lock; + + /* protected by zxdh_vc.lock */ + struct list_head desc_allocated; + struct list_head desc_submitted; + struct list_head desc_issued; + struct list_head desc_completed; + struct list_head desc_terminated; + + struct zxdh_virt_dma_desc *cyclic; +}; + +static inline struct zxdh_virt_dma_chan *zxdh_to_virt_chan(struct dma_chan *chan) +{ + return container_of(chan, struct zxdh_virt_dma_chan, chan); +} + +void zxdh_vchan_dma_desc_free_list(struct zxdh_virt_dma_chan *zxdh_vc, struct list_head *head); +void zxdh_vchan_init(struct zxdh_virt_dma_chan *zxdh_vc, struct dma_device *dmadev); +struct zxdh_virt_dma_desc *zxdh_vchan_find_desc(struct zxdh_virt_dma_chan *, dma_cookie_t); +extern dma_cookie_t zxdh_vchan_tx_submit(struct dma_async_tx_descriptor *); +extern int zxdh_vchan_tx_desc_free(struct dma_async_tx_descriptor *); + +/** + * zxdh_vchan_tx_prep - prepare a descriptor + * @zxdh_vc: virtual channel allocating this descriptor + * @zxdh_vd: virtual descriptor to prepare + * @tx_flags: flags argument passed in to prepare function + */ +static inline struct dma_async_tx_descriptor *zxdh_vchan_tx_prep(struct zxdh_virt_dma_chan *zxdh_vc, + struct zxdh_virt_dma_desc *zxdh_vd, unsigned long tx_flags) +{ + unsigned long flags; + + dma_async_tx_descriptor_init(&zxdh_vd->tx, &zxdh_vc->chan); + zxdh_vd->tx.flags = tx_flags; + zxdh_vd->tx.tx_submit = zxdh_vchan_tx_submit; + zxdh_vd->tx.desc_free = zxdh_vchan_tx_desc_free; + + zxdh_vd->tx_result.result = DMA_TRANS_NOERROR; + zxdh_vd->tx_result.residue = 0; + + spin_lock_irqsave(&zxdh_vc->lock, flags); + list_add_tail(&zxdh_vd->node, &zxdh_vc->desc_allocated); + spin_unlock_irqrestore(&zxdh_vc->lock, flags); + + return &zxdh_vd->tx; +} + +/** + * zxdh_vchan_issue_pending - move submitted descriptors to issued list + * @zxdh_vc: virtual channel to update + * + * zxdh_vc.lock must be held by caller + */ +static inline bool zxdh_vchan_issue_pending(struct zxdh_virt_dma_chan *zxdh_vc) +{ + list_splice_tail_init(&zxdh_vc->desc_submitted, &zxdh_vc->desc_issued); + return !list_empty(&zxdh_vc->desc_issued); +} + +/** + * zxdh_vchan_cookie_complete - report completion of a descriptor + * @zxdh_vd: virtual descriptor to update + * + * zxdh_vc.lock must be held by caller + */ +static inline void zxdh_vchan_cookie_complete(struct zxdh_virt_dma_desc *zxdh_vd) +{ + struct zxdh_virt_dma_chan *zxdh_vc = zxdh_to_virt_chan(zxdh_vd->tx.chan); + dma_cookie_t cookie; + + cookie = zxdh_vd->tx.cookie; + zxdh_dma_cookie_complete(&zxdh_vd->tx); + dev_vdbg(zxdh_vc->chan.device->dev, "txd %p[%x]: marked complete\n", + zxdh_vd, cookie); + list_add_tail(&zxdh_vd->node, &zxdh_vc->desc_completed); + + tasklet_schedule(&zxdh_vc->task); +} + +/** + * zxdh_vchan_vdesc_fini - Free or reuse a descriptor + * @zxdh_vd: virtual descriptor to free/reuse + */ +static inline void zxdh_vchan_vdesc_fini(struct zxdh_virt_dma_desc *zxdh_vd) +{ + struct zxdh_virt_dma_chan *zxdh_vc = zxdh_to_virt_chan(zxdh_vd->tx.chan); + + if (dmaengine_desc_test_reuse(&zxdh_vd->tx)) { + unsigned long flags; + + spin_lock_irqsave(&zxdh_vc->lock, flags); + list_add(&zxdh_vd->node, &zxdh_vc->desc_allocated); + spin_unlock_irqrestore(&zxdh_vc->lock, flags); + } else { + zxdh_vc->desc_free(zxdh_vd); + } +} + +/** + * zxdh_vchan_cyclic_callback - report the completion of a period + * @zxdh_vd: virtual descriptor + */ +static inline void zxdh_vchan_cyclic_callback(struct zxdh_virt_dma_desc *zxdh_vd) +{ + struct zxdh_virt_dma_chan *zxdh_vc = zxdh_to_virt_chan(zxdh_vd->tx.chan); + + zxdh_vc->cyclic = zxdh_vd; + tasklet_schedule(&zxdh_vc->task); +} + +/** + * zxdh_vchan_terminate_vdesc - Disable pending cyclic callback + * @zxdh_vd: virtual descriptor to be terminated + * + * zxdh_vc.lock must be held by caller + */ +static inline void zxdh_vchan_terminate_vdesc(struct zxdh_virt_dma_desc *zxdh_vd) +{ + struct zxdh_virt_dma_chan *zxdh_vc = zxdh_to_virt_chan(zxdh_vd->tx.chan); + + list_add_tail(&zxdh_vd->node, &zxdh_vc->desc_terminated); + + if (zxdh_vc->cyclic == zxdh_vd) + zxdh_vc->cyclic = NULL; +} + +/** + * zxdh_vchan_next_desc - peek at the next descriptor to be processed + * @zxdh_vc: virtual channel to obtain descriptor from + * + * zxdh_vc.lock must be held by caller + */ +static inline struct zxdh_virt_dma_desc *zxdh_vchan_next_desc(struct zxdh_virt_dma_chan *zxdh_vc) +{ + return list_first_entry_or_null(&zxdh_vc->desc_issued, + struct zxdh_virt_dma_desc, node); +} + +/** + * zxdh_vchan_get_all_descriptors - obtain all submitted and issued descriptors + * @zxdh_vc: virtual channel to get descriptors from + * @head: list of descriptors found + * + * zxdh_vc.lock must be held by caller + * + * Removes all submitted and issued descriptors from internal lists, and + * provides a list of all descriptors found + */ +static inline void zxdh_vchan_get_all_descriptors(struct zxdh_virt_dma_chan *zxdh_vc, + struct list_head *head) +{ + list_splice_tail_init(&zxdh_vc->desc_allocated, head); + list_splice_tail_init(&zxdh_vc->desc_submitted, head); + list_splice_tail_init(&zxdh_vc->desc_issued, head); + list_splice_tail_init(&zxdh_vc->desc_completed, head); + list_splice_tail_init(&zxdh_vc->desc_terminated, head); +} + +static inline void zxdh_vchan_free_chan_resources(struct zxdh_virt_dma_chan *zxdh_vc) +{ + struct zxdh_virt_dma_desc *zxdh_vd; + unsigned long flags; + LIST_HEAD(head); + + spin_lock_irqsave(&zxdh_vc->lock, flags); + zxdh_vchan_get_all_descriptors(zxdh_vc, &head); + list_for_each_entry(zxdh_vd, &head, node) + dmaengine_desc_clear_reuse(&zxdh_vd->tx); + spin_unlock_irqrestore(&zxdh_vc->lock, flags); + + zxdh_vchan_dma_desc_free_list(zxdh_vc, &head); +} + +/** + * zxdh_vchan_synchronize() - synchronize callback execution to the current context + * @zxdh_vc: virtual channel to synchronize + * + * Makes sure that all scheduled or active callbacks have finished running. For + * proper operation the caller has to ensure that no new callbacks are scheduled + * after the invocation of this function started. + * Free up the terminated cyclic descriptor to prevent memory leakage. + */ +static inline void zxdh_vchan_synchronize(struct zxdh_virt_dma_chan *zxdh_vc) +{ + LIST_HEAD(head); + unsigned long flags; + + tasklet_kill(&zxdh_vc->task); + + spin_lock_irqsave(&zxdh_vc->lock, flags); + + list_splice_tail_init(&zxdh_vc->desc_terminated, &head); + + spin_unlock_irqrestore(&zxdh_vc->lock, flags); + + zxdh_vchan_dma_desc_free_list(zxdh_vc, &head); +} + +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/epf/pcie-zte-zf-epf.c b/src/net/drivers/net/ethernet/dinghai/zf_mpf/epf/pcie-zte-zf-epf.c new file mode 100644 index 0000000..8297b93 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/epf/pcie-zte-zf-epf.c @@ -0,0 +1,1024 @@ +#include "pcie-zte-zf-epf.h" +#include "./../epc/pcie-zte-zf-epc.h" + +#define EPF_MDEV_OPS 1 +#define MDEV_FOPS 1 + +extern void *pci_epf_alloc_space(struct pci_epf *epf, size_t size, enum pci_barno bar, size_t align); +extern void pci_epf_free_space(struct pci_epf *epf, void *addr, enum pci_barno bar); +extern int ep_virtio_module_set(int ep_id, int pf_idx, int en); +extern int pcie_zte_epc_ob_read(struct pci_epc *epc, phys_addr_t phys_addr, unsigned int size, unsigned int *val); + +#if EPF_MDEV_OPS +static int pci_epf_dev_set_pf_bar(struct pci_epf *epf) +{ + int bar_no = 0, add = 0; + int ret = 0; + struct pci_epf_bar *epf_bar = NULL; + struct pci_epc *epc = epf->epc; + struct device *dev = &epf->dev; + struct pci_epf_mdev_dev *epf_mdev_dev = epf_get_drvdata(epf); + const struct pci_epc_features *epc_features = NULL; + + epc_features = epf_mdev_dev->epc_features; + + for (bar_no = 0; bar_no < PCI_STD_NUM_BARS; bar_no += add) + { + epf_bar = &epf->bar[bar_no]; + epf_bar->flags |= BIT(3); + add = (epf_bar->flags & PCI_BASE_ADDRESS_MEM_TYPE_64) ? 2 : 1; + if (!!(epc_features->reserved_bar & (1 << bar_no))) + continue; + + ret = pci_epc_set_bar(epc, epf->func_no, epf->vfunc_no, epf_bar); + if (ret) + { + dev_err(dev, "Failed to set BAR%d\n", bar_no); + } + } + + // set oprom bar + if (epf->header->pf_rom_size != 0) + { + epf->bar[BAR_ROM].phys_addr = page_to_phys(epf->header->pf_rom_page); + ret = pci_epc_set_bar(epc, epf->func_no, epf->vfunc_no, &epf->bar[BAR_ROM]); + if (ret) + { + dev_err(dev, "Failed to set BAR_ROM\n"); + } + } + + return 0; +} + +static int pci_epf_dev_set_vf_bar(struct pci_epf *epf) +{ + int bar_no = 0, add = 0; + int ret = 0; + struct pci_epf_bar *epf_bar; + struct pci_epc *epc = epf->epc; + struct device *dev = &epf->dev; + struct pci_epf_mdev_dev *epf_mdev_dev = epf_get_drvdata(epf); + const struct pci_epc_features *epc_features; + + epc_features = epf_mdev_dev->epc_features; + + for (bar_no = 0; bar_no < PCI_STD_NUM_BARS; bar_no += add) + { + epf_bar = &epf->epf_pf->vf_bar[bar_no]; + epf_bar->flags |= BIT(3); + add = (epf_bar->flags & PCI_BASE_ADDRESS_MEM_TYPE_64) ? 2 : 1; + if (!!(epc_features->reserved_bar & (1 << bar_no))) + continue; + + ret = pci_epc_set_bar(epc, epf->func_no, epf->vfunc_no, epf_bar); + if (ret) + { + dev_err(dev, "Failed to set BAR%d\n", bar_no); + } + } + return 0; +} + +// 根据epf来配置epc的bar、header、msi、msi-x +static int pci_epf_dev_core_init(struct pci_epf *epf) +{ + const struct pci_epc_features *epc_features; + struct device *dev = &epf->dev; + bool msix_capable = false; + int ret = 0; + + epc_features = pci_epc_get_features(epf->epc, epf->func_no, epf->vfunc_no); + if (epc_features) + { + msix_capable = epc_features->msix_capable; + } + + ret = pci_epc_write_header(epf->epc, epf->func_no, epf->vfunc_no, epf->header); + if (ret) + { + dev_err(dev, "Configuration header write failed\n"); + return ret; + } + + if (isPF(epf->func_no)) + { + ret = pci_epf_dev_set_pf_bar(epf); + } + else if (epf->vfunc_no == 0) + { + ret = pci_epf_dev_set_vf_bar(epf); + } + + return ret; +} + +static int get_vf_number(struct pci_epf *epf) +{ + struct pcie_dpu_ep *dpu_ep = epc_get_drvdata(epf->epc); + int vf_total_num = 0; + + if (!dpu_ep) + { + DH_LOG_ERR(MODULE_MPF, "epc is NULL!!!\n"); + return -EINVAL; + } + + vf_total_num = epf->func_no & PCIE_DPU_EP_GET_PF_NO; + if (vf_total_num >= PCIE_DPU_PF_NUMS) + { + DH_LOG_ERR(MODULE_MPF, "error vf_total_num=%d\n", vf_total_num); + return -EINVAL; + } + return dpu_ep->vf_total_num[vf_total_num]; +} + +// 填充pci_epf_bar结构体内容 +static int alloc_bar_space(struct pci_epf *epf) +{ + u16 bar_no = 0; + int vf_num = 0; + struct pci_epf_mdev_dev *epf_mdev_dev = NULL; + + if (!epf) + { + DH_LOG_ERR(MODULE_MPF, "epf is NULL!\n"); + return -EINVAL; + } + if (!epf->epc) + { + DH_LOG_ERR(MODULE_MPF, "epf->epc is NULL!\n"); + return -EINVAL; + } + + if (!epf->epc->ops->get_max_vfs) + { + DH_LOG_ERR(MODULE_MPF, "get_max_vfs is NULL!\n"); + return -EINVAL; + } + + epf_mdev_dev = epf_get_drvdata(epf); + vf_num = get_vf_number(epf); + + if (isPF(epf->func_no)) + { + epf->bar[BAR_0].size = epf->header->pf_bar0_size; + epf->bar[BAR_2].size = epf->header->pf_bar2_size; + epf->bar[BAR_4].size = epf->header->pf_bar4_size; + } + else + { + epf->epf_pf->vf_bar[4].size = epf->epf_pf->header->vf_bar4_size; + } + + // 申请物理空间 + for (bar_no = 0; bar_no < PCI_STD_NUM_BARS - 2; bar_no += 2) + { + epf->bar[bar_no].addr = pci_epf_alloc_space(epf, epf->bar[bar_no].size, bar_no, GFP_KERNEL); + if (!epf->bar[bar_no].addr) + { + DH_LOG_ERR(MODULE_MPF, "Don't have enough memory!\n"); + return -ENOMEM; + } + } + + for (bar_no = 0; bar_no < PCI_STD_NUM_BARS; bar_no += 2) + { + // PF的信息获取 + epf->bar[bar_no].barno = bar_no; + epf->bar[bar_no].flags |= PCI_BASE_ADDRESS_MEM_TYPE_64; + if (isPF(epf->func_no)) + { + // PF下的VF的信息获取 + epf->vf_bar[bar_no].barno = bar_no; + epf->vf_bar[bar_no].flags |= PCI_BASE_ADDRESS_MEM_TYPE_64; + } + } + + return 0; +} + +static void pci_epf_mdev_unbind(struct pci_epf *epf) +{ + int bar_no = 0; + struct pci_epc *epc = epf->epc; + + DH_LOG_ERR(MODULE_MPF, "pf = 0x%x, vf = 0x%x\n", epf->func_no, epf->vfunc_no); + if (epf->vfunc_no == 0) + { + for (bar_no = 0; bar_no < PCI_STD_NUM_BARS - 2; bar_no += 2) + { + pci_epf_free_space(epf, epf->bar[bar_no].addr, bar_no); + } + } + + if (isPF(epf->func_no)) + { + clear_bit(epf->func_no, &epc->function_num_map); + } +} + +static int pci_epf_mdev_bind(struct pci_epf *epf) +{ + int ret = 0; + struct pci_epf_mdev_dev *epf_mdev_dev = epf_get_drvdata(epf); + const struct pci_epc_features *epc_features = NULL; + struct pci_epc *epc = epf->epc; + bool linkup_notifier = false; + bool core_init_notifier = false; + + if (!epc) + { + DH_LOG_ERR(MODULE_MPF, "epc is NULL!!!\n"); + return -EINVAL; + } + + if (isPF(epf->func_no)) + { + epf->is_vf = PCI_EPF_SRIOV_PF; + } + else + { + epf->is_vf = PCI_EPF_SRIOV_VF; + } + + ret = alloc_bar_space(epf); + if (ret) + { + DH_LOG_ERR(MODULE_MPF, "Alloc bar sapce error!\n"); + return ret; + } + + epc_features = pci_epc_get_features(epc, epf->func_no, epf->vfunc_no); + if (!epc_features) + { + dev_err(&epf->dev, "epc_features not implemented\n"); + return -EOPNOTSUPP; + } + + linkup_notifier = epc_features->linkup_notifier; + core_init_notifier = epc_features->core_init_notifier; + epf_mdev_dev->epc_features = epc_features; + if (!core_init_notifier) + { + ret = pci_epf_dev_core_init(epf); + if (ret) + { + return ret; + } + } + + return 0; +} + +static const struct pci_epf_device_id pci_epf_dev_ids[] = { + { + .name = "pci-epf-mdev", + }, + {}, +}; + +static struct pci_epf_ops epf_mdev_ops = { + .unbind = pci_epf_mdev_unbind, + .bind = pci_epf_mdev_bind, +}; +#endif + +#if MDEV_FOPS +// sample_pci_mdev_dev_show +static ssize_t sample_pci_mdev_dev_show(struct device *dev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "This is pci-epf-mdev device\n"); +} +static DEVICE_ATTR_RO(sample_pci_mdev_dev); + +static struct attribute *pci_mdev_dev_attrs[] = { + &dev_attr_sample_pci_mdev_dev.attr, + NULL, +}; + +static const struct attribute_group pci_mdev_dev_group = { + .name = "pcie_mdev_dev", + .attrs = pci_mdev_dev_attrs, +}; + +static const struct attribute_group *pci_mdev_dev_groups[] = { + &pci_mdev_dev_group, + NULL, +}; + +// sample_mdev_dev_show +static ssize_t sample_mdev_dev_show(struct device *dev, struct device_attribute *attr, char *buf) +{ + if (mdev_from_dev(dev)) + return sprintf(buf, "This is MDEV %s\n", dev_name(dev)); + + return sprintf(buf, "\n"); +} + +static DEVICE_ATTR_RO(sample_mdev_dev); + +static struct attribute *mdev_dev_attrs[] = { + &dev_attr_sample_mdev_dev.attr, + NULL, +}; + +static const struct attribute_group mdev_dev_group = { + .name = "vendor", + .attrs = mdev_dev_attrs, +}; + +static const struct attribute_group *mdev_dev_groups[] = { + &mdev_dev_group, + NULL, +}; + +// name_show +++ device_api_show +static ssize_t name_show(struct mdev_type *mtype, + struct mdev_type_attribute *attr, char *buf) +{ + const char *name_str = {"ZTE epf mdev"}; + return sysfs_emit(buf, "%s\n", name_str); +} +static MDEV_TYPE_ATTR_RO(name); + +static ssize_t device_api_show(struct mdev_type *mtype, + struct mdev_type_attribute *attr, char *buf) +{ + return sprintf(buf, "%s\n", VFIO_DEVICE_API_PCI_STRING); +} + +static MDEV_TYPE_ATTR_RO(device_api); + +static struct attribute *mdev_types_attrs[] = { + &mdev_type_attr_name.attr, + &mdev_type_attr_device_api.attr, + NULL, +}; + +static struct attribute_group mdev_type_group = { + .name = "single", + .attrs = mdev_types_attrs, +}; + +static struct attribute_group *mdev_type_groups[] = { + &mdev_type_group, + NULL, +}; + +static int pci_mdev_create(struct mdev_device *mdev) +{ + struct mdev_state *mdev_state = NULL; + struct device *dev = mdev->type->parent->dev; + struct pci_epf *epf = container_of(dev, struct pci_epf, dev); + struct pci_epf_mdev_dev *epf_mdev_dev = epf_get_drvdata(epf); + int ret = 0; + + if (epf_mdev_dev->created_flag == 1) + { + DH_LOG_ERR(MODULE_MPF, "This mdev has been created!!!\n"); + return -EPERM; + } + + mdev_state = kzalloc(sizeof(struct mdev_state), GFP_KERNEL); + if (!mdev_state) + { + return -ENOMEM; + } + + mdev_state->irq_index = -1; + mdev_state->epf_mdev_dev = epf_mdev_dev; + mdev_state->mdev = mdev; + mutex_init(&mdev_state->ops_lock); + mutex_init(&mdev_state->ioeventfds_lock); + INIT_LIST_HEAD(&mdev_state->ioeventfds_list); + + mdev_set_drvdata(mdev, mdev_state); + + epf_mdev_dev->created_flag = 1; + + return ret; +} + +static int pci_mdev_remove(struct mdev_device *mdev) +{ + int ret = 0; + // int bar_no = 0; + struct mdev_state *mdev_state = NULL; + struct epf_mdev_ioeventfd *ioeventfd = NULL, *temp = NULL; + struct device *dev = NULL; + struct pci_epf *epf = NULL; + struct pci_epf_mdev_dev *epf_mdev_dev = NULL; + + mdev_state = mdev_get_drvdata(mdev); + if (!mdev_state) + { + DH_LOG_ERR(MODULE_MPF, "mdev_state NULL\n"); + return 0; + } + dev = mdev->type->parent->dev; + if (!dev) + { + DH_LOG_ERR(MODULE_MPF, "dev NULL\n"); + return 0; + } + epf = container_of(dev, struct pci_epf, dev); + epf_mdev_dev = epf_get_drvdata(epf); + if (epf_mdev_dev == NULL) + { + DH_LOG_ERR(MODULE_MPF, "epf_mdev_dev NULL\n"); + return 0; + } + + mutex_lock(&mdev_state->ioeventfds_lock); + list_for_each_entry_safe(ioeventfd, temp, &mdev_state->ioeventfds_list, next) + { + vfio_virqfd_disable(&ioeventfd->virqfd); + list_del(&ioeventfd->next); + mdev_state->ioeventfds_nr--; + kfree(ioeventfd); + } + mutex_unlock(&mdev_state->ioeventfds_lock); + mutex_destroy(&mdev_state->ioeventfds_lock); + mutex_destroy(&mdev_state->ops_lock); + kfree(mdev_state); // todo LJP + + epf_mdev_dev->created_flag = 0; + + return ret; +} + +static int pci_mdev_open(struct mdev_device *mdev) +{ + return 0; +} + +static void pci_mdev_close(struct mdev_device *mdev) +{ +} + +static ssize_t pci_mdev_read(struct mdev_device *mdev, char __user *buf, + size_t count, loff_t *ppos) +{ + int ret = 0; + + return ret; +} + +static ssize_t pci_mdev_write(struct mdev_device *mdev, const char __user *buf, + size_t count, loff_t *ppos) +{ + int ret = 0; + struct mdev_state *mdev_state = mdev_get_drvdata(mdev); + + if (!mdev_state) + { + DH_LOG_ERR(MODULE_MPF, "mdev_state is NULL!!!\n"); + return -EINVAL; + } + + return ret; +} + +static int pci_mdev_mmap(struct mdev_device *mdev, struct vm_area_struct *vma) +{ + struct device *dev = mdev->type->parent->dev; + struct pci_epf *epf = container_of(dev, struct pci_epf, dev); + struct pci_epc *epc = epf->epc; + // struct pci_epf_mdev_dev *epf_mdev_dev = epf_get_drvdata(epf); + int ret = 0; + int bar_no = vma->vm_pgoff; + + if (!epc) + { + DH_LOG_ERR(MODULE_MPF, "epc is NULL!!!\n"); + } + + if (vma->vm_end < vma->vm_start) + { + goto parameter_error; + } + + if (vma->vm_end - vma->vm_start > epf->bar[bar_no].size) + { + goto parameter_error; + } + + if ((vma->vm_flags & VM_SHARED) == 0) + { + goto parameter_error; + } + + ret = remap_vmalloc_range_partial(vma, vma->vm_start, epf->bar[bar_no].addr, 0, vma->vm_end - vma->vm_start); + + if (ret) + { + DH_LOG_ERR(MODULE_MPF, "remap_vmalloc_range_partial error!!!\n"); + } + + return ret; + +parameter_error: + DH_LOG_ERR(MODULE_MPF, "vm area parameter error!!!\n"); + return -EINVAL; +} + +#if 1 // ioctl +static int zte_get_device_info(struct mdev_device *mdev, struct vfio_device_info *dev_info) +{ + dev_info->flags = VFIO_DEVICE_FLAGS_PCI; + dev_info->num_regions = VFIO_PCI_NUM_REGIONS; + dev_info->num_irqs = VFIO_PCI_NUM_IRQS; + + return 0; +} + +static int zte_get_region_info(struct mdev_device *mdev, struct vfio_region_info *region_info) +{ + struct mdev_state *mdev_state = NULL; + struct device *dev = mdev->type->parent->dev; + struct pci_epf *epf = container_of(dev, struct pci_epf, dev); + int bar_no = 0; + int bar_size = 0; + + mdev_state = mdev_get_drvdata(mdev); + if (!mdev_state) + { + return -EINVAL; + } + + bar_no = region_info->index; + if (bar_no >= VFIO_PCI_BAR5_REGION_INDEX) + { + DH_LOG_ERR(MODULE_MPF, "bar index invaild!\n"); + return -EINVAL; + } + + mutex_lock(&mdev_state->ops_lock); + + if (bar_no == VFIO_PCI_BAR0_REGION_INDEX || bar_no == VFIO_PCI_BAR2_REGION_INDEX || bar_no == VFIO_PCI_BAR4_REGION_INDEX) + { + bar_size = epf->bar[bar_no].size; + } + else + { + DH_LOG_ERR(MODULE_MPF, "bar index invaild!\n"); + return -EINVAL; + } + + mdev_state->region_info[bar_no].size = bar_size; + + region_info->offset = (bar_no << 12); + region_info->size = bar_size; + region_info->flags = VFIO_REGION_INFO_FLAG_READ | VFIO_REGION_INFO_FLAG_WRITE; + mutex_unlock(&mdev_state->ops_lock); + return 0; +} + +static void __attribute__((unused)) epf_mdev_ioeventfd_thread(void *opaque, void *unused) +{ + // 打桩 +} + +int epf_mdev_ioeventfd_handler(void *opaque, void *unused) +{ + int ret = 0; + struct epf_mdev_ioeventfd *ioeventfd = opaque; + struct mdev_state *mdev_state = ioeventfd->mdev_state; + struct pci_epf_mdev_dev *epf_mdev_dev = mdev_state->epf_mdev_dev; + struct pci_epf *epf = epf_mdev_dev->epf; + struct pci_epc *epc = epf->epc; + enum pci_epc_irq_type irq_type = PCI_EPC_IRQ_MSIX; + + pci_epc_raise_irq(epc, epf->func_no, epf->vfunc_no, irq_type, ioeventfd->offset + 1); + return ret; +} + +#if 0 +int epf_mdev_ioeventfd_func(struct mdev_state *mdev_state, loff_t offset, u64 data, int count, int fd) +{ + int ret = 0; + struct epf_mdev_ioeventfd *ioeventfd = NULL, *temp = NULL; + +#ifndef iowrite64 + if (count == 8) + return -EINVAL; +#endif + + mutex_lock(&mdev_state->ioeventfds_lock); + list_for_each_entry_safe(ioeventfd, temp, &mdev_state->ioeventfds_list, next) + { + if (ioeventfd->offset == offset) + { + if (fd == -1 || data == 0) + { + vfio_virqfd_disable(&ioeventfd->virqfd); + list_del(&ioeventfd->next); + mdev_state->ioeventfds_nr--; + kfree(ioeventfd); + ret = 0; + } + else if (data == 1) + { + vfio_virqfd_disable(&ioeventfd->virqfd); + list_del(&ioeventfd->next); + mdev_state->ioeventfds_nr--; + kfree(ioeventfd); + goto eventfds_set; + } + else + { + ret = -EEXIST; + } + + goto out_unlock; + } + } + + if (fd < 0) + { + ret = -ENODEV; + goto out_unlock; + } + + if (mdev_state->ioeventfds_nr >= EPF_MDEV_IOEVENTFD_MAX) + { + ret = -ENOSPC; + goto out_unlock; + } + +eventfds_set: + ioeventfd = kzalloc(sizeof(*ioeventfd), GFP_KERNEL); + if (!ioeventfd) + { + ret = -ENOMEM; + goto out_unlock; + } + + ioeventfd->mdev_state = mdev_state; + ioeventfd->data = data; + ioeventfd->offset = offset; + ioeventfd->count = count; + + ret = vfio_virqfd_enable(ioeventfd, epf_mdev_ioeventfd_handler, + epf_mdev_ioeventfd_thread, NULL, + &ioeventfd->virqfd, fd); + if (ret) + { + kfree(ioeventfd); + goto out_unlock; + } + + list_add(&ioeventfd->next, &mdev_state->ioeventfds_list); + mdev_state->ioeventfds_nr++; + +out_unlock: + mutex_unlock(&mdev_state->ioeventfds_lock); + + return ret; +} +#endif + +static int device_get_info(struct mdev_device *mdev, struct mdev_state *mdev_state, unsigned long arg) +{ + unsigned long minsz = 0; + struct vfio_device_info info = {0}; + + minsz = offsetofend(struct vfio_device_info, num_irqs); + if (copy_from_user(&info, (void __user *)arg, minsz)) + { + return -EFAULT; + } + + if (info.argsz < minsz) + { + return -EINVAL; + } + + zte_get_device_info(mdev, &info); + + memcpy(&mdev_state->dev_info, &info, sizeof(info)); + if (copy_to_user((void __user *)arg, &info, minsz)) + return -EFAULT; + return 0; +} + +static int device_get_region_info(struct mdev_device *mdev, struct mdev_state *mdev_state, unsigned long arg) +{ + struct vfio_region_info info = {0}; + unsigned long minsz = 0; + int ret = 0; + + minsz = offsetofend(struct vfio_region_info, offset); + if (copy_from_user(&info, (void __user *)arg, minsz)) + return -EFAULT; + + if (info.argsz < minsz) + return -EINVAL; + + ret = zte_get_region_info(mdev, &info); + if (ret) + return ret; + + if (copy_to_user((void __user *)arg, &info, minsz)) + { + return -EFAULT; + } + + return 0; +} + +static int vfio_device_ioeventfd(struct mdev_device *mdev, struct mdev_state *mdev_state, unsigned long arg) +{ + struct vfio_device_ioeventfd ioeventfd = {0}; + int ret = 0; + int count = 0; + unsigned long minsz = 0; + struct pci_epf_mdev_dev *epf_mdev_dev = mdev_state->epf_mdev_dev; + struct pci_epf *epf = epf_mdev_dev->epf; + + minsz = offsetofend(struct vfio_device_ioeventfd, fd); + if (copy_from_user(&ioeventfd, (void __user *)arg, minsz)) + { + DH_LOG_ERR(MODULE_MPF, "copy from user failed! minsz=0x%lx\n", minsz); + return -EFAULT; + } + + DH_LOG_INFO(MODULE_MPF, "func = 0x%x, vfunc_no = 0x%x, offset = 0x%llx, data = 0x%llx, minsz=0x%lx\n", epf->func_no, epf->vfunc_no, ioeventfd.offset, ioeventfd.data, minsz); + if (ioeventfd.argsz < minsz) + { + return -EINVAL; + } + + if (ioeventfd.flags & ~VFIO_DEVICE_IOEVENTFD_SIZE_MASK) + { + return -EINVAL; + } + + count = ioeventfd.flags & VFIO_DEVICE_IOEVENTFD_SIZE_MASK; + + if (hweight8(count) != 1 || ioeventfd.fd < -1) + return -EINVAL; + + // ret = epf_mdev_ioeventfd_func(mdev_state, (loff_t)ioeventfd.offset, (u64)ioeventfd.data, count, (int)ioeventfd.fd); + DH_LOG_ERR(MODULE_MPF, "error: epf_mdev_ioeventfd_func not called!\n"); + return ret; +} + +static int vfio_outbound_set(struct mdev_device *mdev, struct mdev_state *mdev_state, unsigned long arg) +{ + int ret = 0; + struct pci_epf_mdev_dev *epf_mdev_dev = mdev_state->epf_mdev_dev; + struct pci_epf *epf = epf_mdev_dev->epf; + struct pci_epc *epc = epf->epc; + struct ioctl_ob_data ob = {0}; + void __iomem *dst_addr = NULL; + phys_addr_t dst_phys_addr = 0; + + if (copy_from_user(&ob, (void *)arg, sizeof(struct ioctl_ob_data))) + { + DH_LOG_ERR(MODULE_MPF, "err:copy_from_user failed!\n"); + return -EFAULT; + } + DH_LOG_INFO(MODULE_MPF, "ob->host = 0x%llx, ob->size = 0x%lxs\n", ob.host_addr, ob.size); + + dst_addr = pci_epc_mem_alloc_addr(epc, &dst_phys_addr, ob.size); + if (!dst_addr) + { + DH_LOG_ERR(MODULE_MPF, "Failed to allocate destination address\n"); + return -ENOMEM; + } + + ret = pci_epc_map_addr(epc, epf->func_no, epf->vfunc_no, dst_phys_addr, ob.host_addr, ob.size); + if (ret) + { + DH_LOG_ERR(MODULE_MPF, "pci_epc_map_addr err!!!\n"); + return ret; + } + ob.dpu_vaddr = (unsigned long long)dst_addr; + ob.dpu_paddr = dst_phys_addr; + if (copy_to_user((void *)arg, &ob, sizeof(struct ioctl_ob_data))) + { + DH_LOG_ERR(MODULE_MPF, "err:copy_to_user failed!\n"); + return -EFAULT; + } + + return 0; +} + +static int vfio_outbound_read(struct mdev_device *mdev, struct mdev_state *mdev_state, unsigned long arg) +{ + struct pci_epf_mdev_dev *epf_mdev_dev = mdev_state->epf_mdev_dev; + struct pci_epf *epf = epf_mdev_dev->epf; + struct pci_epc *epc = epf->epc; + struct pci_ob_rw_data ob_rw_data = {0}; + + if (copy_from_user(&ob_rw_data, (void *)arg, sizeof(struct pci_ob_rw_data))) + { + DH_LOG_ERR(MODULE_MPF, "err:copy_from_user failed!\n"); + return -EFAULT; + } + DH_LOG_INFO(MODULE_MPF, "ob_rw_data.phys_addr = 0x%llx, ob_rw_data.size = 0x%x\n", ob_rw_data.phys_addr, ob_rw_data.size); + + pcie_zte_epc_ob_read(epc, (phys_addr_t)ob_rw_data.phys_addr, ob_rw_data.size, &ob_rw_data.val); + + if (copy_to_user((void *)arg, &ob_rw_data, sizeof(struct pci_ob_rw_data))) + { + DH_LOG_ERR(MODULE_MPF, "err:copy_to_user failed!\n"); + return -EFAULT; + } + + return 0; +} + +static int vfio_outbound_clear(struct mdev_device *mdev, struct mdev_state *mdev_state, unsigned long arg) +{ + struct pci_epf_mdev_dev *epf_mdev_dev = mdev_state->epf_mdev_dev; + struct pci_epf *epf = epf_mdev_dev->epf; + struct pci_epc *epc = epf->epc; + struct ioctl_ob_data ob = {0}; + + if (copy_from_user(&ob, (void *)arg, sizeof(struct ioctl_ob_data))) + { + DH_LOG_ERR(MODULE_MPF, "err:copy_from_user failed!\n"); + return -EFAULT; + } + + pci_epc_unmap_addr(epc, epf->func_no, epf->vfunc_no, ob.dpu_vaddr); + pci_epc_mem_free_addr(epc, ob.dpu_paddr, (void *)ob.dpu_vaddr, ob.size); + + return 0; +} + +static int vfio_virtio_module_set(unsigned long arg) +{ + struct ioctl_virtio_data virtio_data = {0}; + + if (copy_from_user(&virtio_data, (void *)arg, sizeof(struct ioctl_virtio_data))) + { + DH_LOG_ERR(MODULE_MPF, "err:copy_from_user failed!\n"); + return -EFAULT; + } + + return ep_virtio_module_set(virtio_data.ep_id, virtio_data.pf_id, virtio_data.en); +} + +static long pci_mdev_ioctl(struct mdev_device *mdev, unsigned int cmd, unsigned long arg) +{ + int ret = 0; + struct mdev_state *mdev_state; + struct device *dev = NULL; + // struct pci_epf *epf = container_of(dev, struct pci_epf, dev); + // struct pci_epf_mdev_dev *epf_mdev_dev = epf_get_drvdata(epf); + + if (mdev == NULL) + { + DH_LOG_ERR(MODULE_MPF, "err: mdev is NULL!\n"); + return -EINVAL; + } + dev = mdev->type->parent->dev; + + mdev_state = mdev_get_drvdata(mdev); + if (!mdev_state) + return -ENODEV; + + switch (cmd) + { + case VFIO_DEVICE_GET_INFO: + return device_get_info(mdev, mdev_state, arg); + case VFIO_DEVICE_GET_REGION_INFO: + return device_get_region_info(mdev, mdev_state, arg); + case VFIO_DEVICE_IOEVENTFD: + return vfio_device_ioeventfd(mdev, mdev_state, arg); + case VFIO_OUTBOUND_SET: + return vfio_outbound_set(mdev, mdev_state, arg); + case VFIO_OUTBOUND_CLEAR: + return vfio_outbound_clear(mdev, mdev_state, arg); + case VFIO_POWER_RESET: + ep_power_reset(arg); + return 0; + case VFIO_VIRTIO_MODULE_SET: + return vfio_virtio_module_set(arg); + case VFIO_LINKUP: + return pcie_zf_link_up(arg); + case VFIO_OUTBOUND_READ: + return vfio_outbound_read(mdev, mdev_state, arg); + // case VFIO_EP4_LINKUP: + // return is_ep4_link_up(); + default: + DH_LOG_ERR(MODULE_MPF, "zte-pci-epf-mdev ioctl cmd error!\n"); + ret = -ENOTTY; + } + + return ret; +} +#endif + +static const struct mdev_parent_ops mdev_fops = { + .owner = THIS_MODULE, + .dev_attr_groups = pci_mdev_dev_groups, + .mdev_attr_groups = mdev_dev_groups, + .supported_type_groups = mdev_type_groups, + .create = pci_mdev_create, + .remove = pci_mdev_remove, + .open = pci_mdev_open, + .release = pci_mdev_close, + .read = pci_mdev_read, + .write = pci_mdev_write, + .mmap = pci_mdev_mmap, + .ioctl = pci_mdev_ioctl, +}; +#endif + +static int pci_epf_mdev_probe(struct pci_epf *epf) +{ + struct pci_epf_mdev_dev *epf_mdev_dev; + struct device *dev = &epf->dev; + int ret = 0; + + epf_mdev_dev = devm_kzalloc(dev, sizeof(*epf_mdev_dev), GFP_KERNEL); + if (!epf_mdev_dev) + return -ENOMEM; + + epf_mdev_dev->epf = epf; + epf->header = devm_kzalloc(dev, sizeof(struct pci_epf_header), GFP_KERNEL); + if (!epf->header) + { + ret = -ENOMEM; + goto err; + } + + epf_mdev_dev->created_flag = 0; + + // DMA一致性设置（未必有效，待查） + dev->coherent_dma_mask = ~((u64)0x0); + + epf_set_drvdata(epf, epf_mdev_dev); + + ret = mdev_register_device(dev, &mdev_fops); + if (ret) + { + DH_LOG_ERR(MODULE_MPF, "mdev_register_device failed %d\n", ret); + goto err; + } + + return 0; + +err: + devm_kfree(dev, epf->header); + devm_kfree(dev, epf_mdev_dev); + return ret; +} + +static int pci_epf_remove(struct pci_epf *epf) +{ + struct device *dev = &epf->dev; + struct pci_epf_mdev_dev *epf_mdev_dev = epf_get_drvdata(epf); + + mdev_unregister_device(&epf->dev); + if (epf->header) + { + devm_kfree(dev, epf->header); + } + if (epf_mdev_dev) + { + devm_kfree(dev, epf_mdev_dev); + } + + return 0; +} + +static struct pci_epf_driver pci_epf_mdev_driver = { + .driver.name = "pci-epf-mdev", + .probe = pci_epf_mdev_probe, + .remove = pci_epf_remove, + .id_table = pci_epf_dev_ids, + .ops = &epf_mdev_ops, + .owner = THIS_MODULE, +}; + +static int __init pci_epf_mdev_init(void) +{ + int ret = 0; + + ret = pci_epf_register_driver(&pci_epf_mdev_driver); + if (ret) + { + pr_err("Failed to register pci epf test driver --> %d\n", ret); + return ret; + } + + DH_LOG_ERR(MODULE_MPF, "zte_epf driver regist successful\n"); + return ret; +} +module_init(pci_epf_mdev_init); + +static void __exit pci_epf_mdev_exit(void) +{ + pci_epf_unregister_driver(&pci_epf_mdev_driver); +} +module_exit(pci_epf_mdev_exit); + +MODULE_DESCRIPTION("PCI EPF MDEV DRIVER"); +MODULE_AUTHOR("ZTE"); +MODULE_LICENSE("GPL v2"); diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/epf/pcie-zte-zf-epf.h b/src/net/drivers/net/ethernet/dinghai/zf_mpf/epf/pcie-zte-zf-epf.h new file mode 100644 index 0000000..8fdc09e --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/epf/pcie-zte-zf-epf.h @@ -0,0 +1,142 @@ +#ifndef __ZTE_EPF_H +#define __ZTE_EPF_H + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../epc/pcie-zte-zf-epc.h" + +#define EPF_MDEV_IOEVENTFD_MAX 20 + +/* ioctl cmd */ +#define VFIO_OUTBOUND_SET _IO(VFIO_TYPE, VFIO_BASE + 30) +#define VFIO_OUTBOUND_CLEAR _IO(VFIO_TYPE, VFIO_BASE + 31) +#define VFIO_POWER_RESET _IO(VFIO_TYPE, VFIO_BASE + 32) +#define VFIO_VIRTIO_MODULE_SET _IO(VFIO_TYPE, VFIO_BASE + 33) +#define VFIO_LINKUP _IO(VFIO_TYPE, VFIO_BASE + 34) +#define VFIO_OUTBOUND_READ _IO(VFIO_TYPE, VFIO_BASE + 35) +// #define VFIO_EP4_LINKUP _IO(VFIO_TYPE, VFIO_BASE + 35) + +extern int pcie_zf_link_up(int ep_id); +// extern int is_ep4_link_up(void); +extern void ep_power_reset(int ep_id); +extern int ep_virtio_module_set(int ep_id, int pf_id, int en); + +struct ioctl_virtio_data { + int ep_id; + int pf_id; + int en; +}; + +struct ioctl_ob_data { + unsigned long long dpu_paddr; + unsigned long long dpu_vaddr; + unsigned long long host_addr; + unsigned long size; +}; + +struct pci_epf_mdev_dev { + struct pci_epf *epf; + enum pci_barno epf_barno; + size_t msix_table_offset; + const struct pci_epc_features *epc_features; + int created_flag; // 0:Not created, 1:created + void *pf_bar_vaddr[PCI_STD_NUM_BARS + 1]; + void *vf_bar_vaddr[PCI_STD_NUM_BARS]; +}; + +struct epf_mdev_ioeventfd { + struct list_head next; + struct mdev_state *mdev_state; + struct virqfd *virqfd; + u64 data; + loff_t pos; + u64 offset; + int count; +}; + +struct mdev_region_info { + u64 start; + u64 phys_start; + u32 size; + u64 vfio_offset; + u32 argsz; +}; + +struct mdev_state { + int irq_fd; + struct eventfd_ctx *intx_evtfd; + struct eventfd_ctx *msi_evtfd; + struct eventfd_ctx *msix_evtfd; + int irq_index; + struct mutex ops_lock; + struct mdev_device *mdev; + struct mdev_region_info region_info[VFIO_PCI_NUM_REGIONS]; + u32 bar_mask[VFIO_PCI_NUM_REGIONS]; + struct list_head next; + struct vfio_device_info dev_info; + struct pci_epf_mdev_dev *epf_mdev_dev; + struct mutex ioeventfds_lock; + struct list_head ioeventfds_list; + int ioeventfds_nr; +}; + +// mdev_private struct +struct mdev_parent { + struct device *dev; + const struct mdev_parent_ops *ops; + struct kref ref; + struct list_head next; + struct kset *mdev_types_kset; + struct list_head type_list; + struct rw_semaphore unreg_sem; +}; + +struct mdev_type { + struct kobject kobj; + struct kobject *devices_kobj; + struct mdev_parent *parent; + struct list_head next; + unsigned int type_group_id; +}; +// mdev_private struct end + +struct pci_ob_rw_data { + unsigned long long phys_addr; + unsigned int size; + unsigned int val; +}; + +#endif \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/eq.c b/src/net/drivers/net/ethernet/dinghai/zf_mpf/eq.c new file mode 100755 index 0000000..88d012b --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/eq.c @@ -0,0 +1,502 @@ +#include +#include +#include +#include +#include +#include "irq.h" +#include "eq.h" +#include "zf_mpf.h" +#include "gdma.h" + +struct dh_mpf_eq_table { + struct dh_irq **comp_irqs; + struct dh_irq *async_risc_irq; + struct dh_irq *async_pf_irq; + struct dh_irq *async_irq1; + struct dh_irq *async_irq2; + struct dh_irq *async_irq3; + struct dh_irq *async_irq4; + struct dh_irq **gdma_irqs; + struct dh_eq_async async_risc_eq; + struct dh_eq_async async_pf_eq; + struct dh_eq_async async_eq1; + struct dh_eq_async async_eq2; + struct dh_eq_async async_eq3; + struct dh_eq_async async_eq4; + struct dh_eq_async gdma_eq[ZXDH_MPF_GDMA_IRQ_NUM]; +}; + +static int32_t create_async_eqs(struct dh_core_dev *dev); + +#ifdef CONFIG_ZF_GDMA +static int32_t create_gdma_eqs(struct dh_core_dev *dev); +void cleanup_gdma_eq(struct dh_core_dev *dev, struct dh_mpf_eq_table *table_priv, uint16_t num); +#endif + +static int32_t __attribute__((unused)) create_eq_map(struct dh_eq_param *param) +{ + int32_t err = 0; + + /* inform device*/ + return err; +} + +int32_t dh_mpf_eq_table_init(struct dh_core_dev *dev) +{ + struct dh_mpf_eq_table *table_priv = NULL; + + table_priv = kvzalloc(sizeof(*table_priv), GFP_KERNEL); + if (unlikely(table_priv == NULL)) + { + return -ENOMEM; + } + + dh_eq_table_init(dev, table_priv); + + return 0; +} + +/*todo*/ +int32_t dh_eq_get_comp_eqs(struct dh_core_dev *dev) +{ + return 0; +} + +static int32_t create_comp_eqs(struct dh_core_dev *dev) +{ + if (IS_ERR_OR_NULL(dev)) + { + dh_err(dev, "error dev\n"); + return PTR_ERR(dev); + } + + return 0; +} + +static int32_t destroy_async_eq(struct dh_core_dev *dev) +{ + struct dh_eq_table *eq_table = &dev->eq_table; + + mutex_lock(&eq_table->lock); + /*unmap inform device*/ + mutex_unlock(&eq_table->lock); + + return 0; +} + +static void cleanup_async_eq(struct dh_core_dev *dev, + struct dh_eq_async *eq, const char *name) +{ + dh_eq_disable(dev, &eq->core, &eq->irq_nb); +} + +static void destroy_async_eqs(struct dh_core_dev *dev) +{ + struct dh_eq_table *table = &dev->eq_table; + struct dh_mpf_eq_table *table_priv = table->priv; + + cleanup_async_eq(dev, &table_priv->async_risc_eq, "riscv"); + cleanup_async_eq(dev, &table_priv->async_pf_eq, "pf"); + cleanup_async_eq(dev, &table_priv->async_eq1, "eq1"); + cleanup_async_eq(dev, &table_priv->async_eq2, "eq2"); + cleanup_async_eq(dev, &table_priv->async_eq3, "eq3"); + cleanup_async_eq(dev, &table_priv->async_eq4, "eq4"); + destroy_async_eq(dev); + dh_irqs_release_vectors(&table_priv->async_risc_irq, 1); + dh_irqs_release_vectors(&table_priv->async_pf_irq, 1); + dh_irqs_release_vectors(&table_priv->async_irq1, 1); + dh_irqs_release_vectors(&table_priv->async_irq2, 1); + dh_irqs_release_vectors(&table_priv->async_irq3, 1); + dh_irqs_release_vectors(&table_priv->async_irq4, 1); +} + +void destroy_comp_eqs(struct dh_core_dev *dev) +{ + +} + +#ifdef CONFIG_ZF_GDMA +static void destroy_gdma_eqs(struct dh_core_dev *dev) +{ + struct dh_eq_table *eq_table = &dev->eq_table; + struct dh_mpf_eq_table *mpf_eq_table = eq_table->priv; + struct dh_irq_table *irq_table = &dev->irq_table; + struct dh_mpf_irq_table *mpf_irq_table = irq_table->priv; + + cleanup_gdma_eq(dev, mpf_eq_table, ZXDH_MPF_GDMA_IRQ_NUM); + + dh_irq_affinity_irqs_release(mpf_irq_table->mpf_gdma_pool, mpf_eq_table->gdma_irqs, ZXDH_MPF_GDMA_IRQ_NUM); + dh_irqs_release_vectors(mpf_eq_table->gdma_irqs, ZXDH_MPF_GDMA_IRQ_NUM); +} +#endif + +void dh_mpf_eq_table_destroy(struct dh_core_dev *dev) +{ + destroy_comp_eqs(dev); + destroy_async_eqs(dev); +#ifdef CONFIG_ZF_GDMA + destroy_gdma_eqs(dev); +#endif +} + +int32_t dh_mpf_eq_table_create(struct dh_core_dev *dev) +{ + int32_t err = 0; + + err = create_async_eqs(dev); + if (err != 0) + { + dh_err(dev, "Failed to create async EQs\n"); + goto err_async_eqs; + } + + err = create_comp_eqs(dev); + if (err != 0) + { + dh_err(dev, "Failed to create completion EQs\n"); + goto err_comp_eqs; + } + +#ifdef CONFIG_ZF_GDMA + err = create_gdma_eqs(dev); + if (err != 0) + { + dh_err(dev, "Failed to create gdma EQs\n"); + goto err_comp_eqs; + } +#endif + + return 0; + +err_comp_eqs: + destroy_async_eqs(dev); +err_async_eqs: + return err; +} + +/*create eventq*/ +static int32_t create_async_eq(struct dh_core_dev *dev, struct dh_irq *risc, struct dh_irq *pf) +{ + struct dh_eq_table *eq_table = &dev->eq_table; + struct dh_en_mpf_dev *mpf_dev = dh_core_priv(dev); + struct msix_para in = {0}; + int32_t err = 0; + + in.vector_risc = risc->index; + in.vector_pfvf = pf->index; + in.vector_mpf = 0xff; + in.driver_type = MSG_CHAN_END_PF;//TODO + in.pdev = dev->pdev; + in.virt_addr = mpf_dev->pci_ioremap_addr + ZXDH_BAR1_CHAN_OFFSET; + in.pcie_id = mpf_dev->pcie_id; + DH_LOG_INFO(MODULE_MPF, "pcie_id = 0x%x\n", mpf_dev->pcie_id); + + mutex_lock(&eq_table->lock); + + err = zxdh_bar_enable_chan(&in, &mpf_dev->vport); + + mutex_unlock(&eq_table->lock); + + return err; +} + +static int32_t dh_eq_async_riscv_int(struct notifier_block *nb, unsigned long action, void *data) +{ + struct dh_eq_async *eq_riscv_async = container_of(nb, struct dh_eq_async, irq_nb); + struct dh_core_dev *dev = (struct dh_core_dev *)eq_riscv_async->priv; + struct dh_eq_table *eq_table = &dev->eq_table; + + atomic_notifier_call_chain(&eq_table->nh[DH_EVENT_TYPE_NOTIFY_RISC_TO_MPF], DH_EVENT_TYPE_NOTIFY_RISC_TO_MPF, NULL); + + return 0; +} + +static int32_t dh_eq_async_mpf_int(struct notifier_block *nb, unsigned long action, void *data) +{ + struct dh_eq_async *eq_riscv_async = container_of(nb, struct dh_eq_async, irq_nb); + struct dh_core_dev *dev = (struct dh_core_dev *)eq_riscv_async->priv; + struct dh_eq_table *eq_table = &dev->eq_table; + + atomic_notifier_call_chain(&eq_table->nh[DH_EVENT_TYPE_NOTIFY_PF_TO_MPF], DH_EVENT_TYPE_NOTIFY_PF_TO_MPF, NULL); + + return 0; +} + +static int32_t dh_eq_async_int1(struct notifier_block *nb, unsigned long action, void *data) +{ + struct dh_eq_async *eq_riscv_async = container_of(nb, struct dh_eq_async, irq_nb); + struct dh_core_dev *dev = (struct dh_core_dev *)eq_riscv_async->priv; + struct dh_eq_table *eq_table = &dev->eq_table; + + atomic_notifier_call_chain(&eq_table->nh[DH_EVENT_TYPE_NOTIFY_1], DH_EVENT_TYPE_NOTIFY_1, dev); + + return 0; +} + +static int32_t dh_eq_async_int2(struct notifier_block *nb, unsigned long action, void *data) +{ + struct dh_eq_async *eq_riscv_async = container_of(nb, struct dh_eq_async, irq_nb); + struct dh_core_dev *dev = (struct dh_core_dev *)eq_riscv_async->priv; + struct dh_eq_table *eq_table = &dev->eq_table; + + atomic_notifier_call_chain(&eq_table->nh[DH_EVENT_TYPE_NOTIFY_2], DH_EVENT_TYPE_NOTIFY_2, dev); + + return 0; +} + +static int32_t dh_eq_async_int3(struct notifier_block *nb, unsigned long action, void *data) +{ + struct dh_eq_async *eq_riscv_async = container_of(nb, struct dh_eq_async, irq_nb); + struct dh_core_dev *dev = (struct dh_core_dev *)eq_riscv_async->priv; + struct dh_eq_table *eq_table = &dev->eq_table; + + atomic_notifier_call_chain(&eq_table->nh[DH_EVENT_TYPE_NOTIFY_3], DH_EVENT_TYPE_NOTIFY_3, dev); + + return 0; +} + +static int32_t dh_eq_async_int4(struct notifier_block *nb, unsigned long action, void *data) +{ + struct dh_eq_async *eq_riscv_async = container_of(nb, struct dh_eq_async, irq_nb); + struct dh_core_dev *dev = (struct dh_core_dev *)eq_riscv_async->priv; + struct dh_eq_table *eq_table = &dev->eq_table; + + atomic_notifier_call_chain(&eq_table->nh[DH_EVENT_TYPE_NOTIFY_4], DH_EVENT_TYPE_NOTIFY_4, dev); + + return 0; +} + +static int32_t create_async_eqs(struct dh_core_dev *dev) +{ + struct dh_eq_table *table = &dev->eq_table; + struct dh_mpf_eq_table *table_priv = table->priv; + struct dh_eq_param param = {}; + int32_t err = 0; + + dh_dbg(dev, "start\r\n"); + table_priv->async_risc_irq = dh_mpf_async_irq_request(dev); + if (IS_ERR_OR_NULL(table_priv->async_risc_irq)) + { + dh_err(dev, "Failed to get async_risc_irq\n"); + return PTR_ERR(table_priv->async_risc_irq); + } + + table_priv->async_pf_irq = dh_mpf_async_irq_request(dev); + if (IS_ERR_OR_NULL(table_priv->async_pf_irq)) + { + err = PTR_ERR(table_priv->async_pf_irq); + dh_err(dev, "Failed to get async_pf_irq\n"); + goto err_irq_request; + } + + table_priv->async_irq1 = dh_mpf_async_irq_request(dev); + if (IS_ERR_OR_NULL(table_priv->async_irq1)) + { + err = PTR_ERR(table_priv->async_irq1); + dh_err(dev, "Failed to get async_irq1\n"); + goto err_irq_request1; + } + + table_priv->async_irq2 = dh_mpf_async_irq_request(dev); + if (IS_ERR_OR_NULL(table_priv->async_irq2)) + { + err = PTR_ERR(table_priv->async_irq2); + dh_err(dev, "Failed to get async_irq2\n"); + goto err_irq_request2; + } + + table_priv->async_irq3 = dh_mpf_async_irq_request(dev); + if (IS_ERR_OR_NULL(table_priv->async_irq3)) + { + err = PTR_ERR(table_priv->async_irq3); + dh_err(dev, "Failed to get async_irq3\n"); + goto err_irq_request3; + } + + table_priv->async_irq4 = dh_mpf_async_irq_request(dev); + if (IS_ERR_OR_NULL(table_priv->async_irq4)) + { + err = PTR_ERR(table_priv->async_irq4); + dh_err(dev, "Failed to get async_irq4\n"); + goto err_irq_request4; + } + + err = create_async_eq(dev, table_priv->async_risc_irq, table_priv->async_pf_irq); + if (err != 0) + { + dh_err(dev, "Failed to create async_eq\n"); + goto err_create_async_eq; + } + + param = (struct dh_eq_param) { + .irq = table_priv->async_risc_irq, + .nent = 10, + .event_type = DH_EVENT_QUEUE_TYPE_RISCV /* used for inform dpu */ + }; + err = setup_async_eq(dev, &table_priv->async_risc_eq, ¶m, dh_eq_async_riscv_int, "riscv", dev); + if (err != 0) + { + dh_err(dev, "Failed to setup async_risc_eq\n"); + goto err_setup_async_risc_eq; + } + + param.irq = table_priv->async_pf_irq, + err = setup_async_eq(dev, &table_priv->async_pf_eq, ¶m, dh_eq_async_mpf_int, "pf", dev); + if (err != 0) + { + dh_err(dev, "Failed to setup async_pf_eq\n"); + goto err_setup_async_pf_eq; + } + + param.irq = table_priv->async_irq1, + err = setup_async_eq(dev, &table_priv->async_eq1, ¶m, dh_eq_async_int1, "irq1", dev); + if (err != 0) + { + dh_err(dev, "Failed to setup async_eq1\n"); + goto err_setup_async_eq1; + } + + param.irq = table_priv->async_irq2, + err = setup_async_eq(dev, &table_priv->async_eq2, ¶m, dh_eq_async_int2, "irq2", dev); + if (err != 0) + { + dh_err(dev, "Failed to setup async_eq1\n"); + goto err_setup_async_eq2; + } + + param.irq = table_priv->async_irq3, + err = setup_async_eq(dev, &table_priv->async_eq3, ¶m, dh_eq_async_int3, "irq3", dev); + if (err != 0) + { + dh_err(dev, "Failed to setup async_eq3\n"); + goto err_setup_async_eq3; + } + + param.irq = table_priv->async_irq4, + err = setup_async_eq(dev, &table_priv->async_eq4, ¶m, dh_eq_async_int4, "irq4", dev); + if (err != 0) + { + dh_err(dev, "Failed to setup async_eq4\n"); + goto err_setup_async_eq4; + } + + return 0; + +err_setup_async_eq4: + cleanup_async_eq(dev, &table_priv->async_eq3, "irq3"); +err_setup_async_eq3: + cleanup_async_eq(dev, &table_priv->async_eq2, "irq2"); +err_setup_async_eq2: + cleanup_async_eq(dev, &table_priv->async_eq1, "irq1"); +err_setup_async_eq1: + cleanup_async_eq(dev, &table_priv->async_pf_eq, "pf"); +err_setup_async_pf_eq: + cleanup_async_eq(dev, &table_priv->async_risc_eq, "riscv"); +err_setup_async_risc_eq: + destroy_async_eq(dev); +err_create_async_eq: + dh_irqs_release_vectors(&table_priv->async_irq4, 1); +err_irq_request4: + dh_irqs_release_vectors(&table_priv->async_irq3, 1); +err_irq_request3: + dh_irqs_release_vectors(&table_priv->async_irq2, 1); +err_irq_request2: + dh_irqs_release_vectors(&table_priv->async_irq1, 1); +err_irq_request1: + dh_irqs_release_vectors(&table_priv->async_pf_irq, 1); +err_irq_request: + dh_irqs_release_vectors(&table_priv->async_risc_irq, 1); + return err; +} + +#ifdef CONFIG_ZF_GDMA +void cleanup_gdma_eq(struct dh_core_dev *dev, struct dh_mpf_eq_table *table_priv, uint16_t num) +{ + uint16_t i = 0; + + for (i = 0; i < num; i++) + { + cleanup_async_eq(dev, &table_priv->gdma_eq[i], NULL); + } +} + +int32_t setup_gdma_eq(struct dh_core_dev *dev, struct dh_mpf_eq_table *table_priv, uint16_t gdma_irq_num) +{ + struct dh_en_mpf_dev *mpf_dev = dh_core_priv(dev); + struct zf_gdma_dev *gdev = mpf_dev->gdev; + struct dh_eq_param param = {}; + uint16_t i = 0; + int32_t ret = 0; + void *priv = NULL; + notifier_fn_t callback; + + if (gdma_irq_num > ZXDH_MPF_GDMA_IRQ_NUM) + { + dh_err(dev, "gdma_irq_num %d is invalid\n", gdma_irq_num); + return -1; + } + + for (i = 0; i < gdma_irq_num; i++) + { + if (i < ZF_GDMA_CHAN_NUM) + { + callback = zf_gdma_chan_irq_handle; + priv = &gdev->chan[i]; + } + else + { + callback = zf_gdma_err_irq_handle; + priv = dev; + } + + param.irq = table_priv->gdma_irqs[i]; + ret = setup_async_eq(dev, &table_priv->gdma_eq[i], ¶m, callback, "gdma", priv); + if (ret != 0) + { + LOG_ERR("Failed to setup gdma %d eq\n", i); + cleanup_gdma_eq(dev, table_priv, i); + return ret; + } + } + + return 0; +} + +static int32_t create_gdma_eqs(struct dh_core_dev *dev) +{ + struct dh_eq_table *eq_table = &dev->eq_table; + struct dh_mpf_eq_table *mpf_eq_table = eq_table->priv; + struct dh_irq_table *irq_table = &dev->irq_table; + struct dh_mpf_irq_table *mpf_irq_table = irq_table->priv; + int32_t ret = 0; + + mpf_eq_table->gdma_irqs = kcalloc(ZXDH_MPF_GDMA_IRQ_NUM, sizeof(struct dh_irq *), GFP_KERNEL); + if (unlikely(mpf_eq_table->gdma_irqs == NULL)) + { + LOG_ERR("Failed to alloc mpf_eq_table->gdma_irqs\n"); + return -ENOMEM; + } + + ret = dh_irq_affinity_irqs_request_auto(mpf_irq_table->mpf_gdma_pool, mpf_eq_table->gdma_irqs, ZXDH_MPF_GDMA_IRQ_NUM); + if (ret < 0) + { + dh_err(dev, "Failed to get gdma irq\n"); + goto err_gdma_irq; + } + + ret = setup_gdma_eq(dev, mpf_eq_table, ZXDH_MPF_GDMA_IRQ_NUM); + if (ret != 0) + { + goto err_gdma_eq; + } + + return 0; + +err_gdma_eq: + dh_irq_affinity_irqs_release(mpf_irq_table->mpf_gdma_pool, mpf_eq_table->gdma_irqs, ZXDH_MPF_GDMA_IRQ_NUM); + dh_irqs_release_vectors(mpf_eq_table->gdma_irqs, ZXDH_MPF_GDMA_IRQ_NUM); +err_gdma_irq: + kfree(mpf_eq_table->gdma_irqs); + return ret; +} +#endif \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/eq.h b/src/net/drivers/net/ethernet/dinghai/zf_mpf/eq.h new file mode 100755 index 0000000..4aaaaae --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/eq.h @@ -0,0 +1,19 @@ +#ifndef __ZXDH_MPF_EQ_H__ +#define __ZXDH_MPF_EQ_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +int32_t dh_mpf_eq_table_init(struct dh_core_dev *dev); + +int32_t dh_mpf_eq_table_create(struct dh_core_dev *dev); +void dh_mpf_eq_table_destroy(struct dh_core_dev *dev); + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/fuc_hotplug/fuc_hotplug.c b/src/net/drivers/net/ethernet/dinghai/zf_mpf/fuc_hotplug/fuc_hotplug.c new file mode 100644 index 0000000..77f0f3d --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/fuc_hotplug/fuc_hotplug.c @@ -0,0 +1,224 @@ +#include +#include "fuc_hotplug.h" +#include "fuc_hotplug_commom.h" + +extern int zxdh_bar_chan_sync_msg_send(struct zxdh_pci_bar_msg *in, struct zxdh_msg_recviver_mem *result); +extern int get_fuc_hp_ret(void); +extern int reset_fuc_hp_ret(void); +static int fuc_hotplug_trigger(u64 arg); +static int fuc_hotplug_get_pf_state(u64 arg); +static int ep_hotplug(u64 arg); + +static struct func_sel ioctl_func_sel[] = { + {FUC_HP_IOCTL_CMD0, fuc_hotplug_trigger }, + {FUC_HP_IOCTL_CMD1, fuc_hotplug_get_pf_state }, + {FUC_HP_IOCTL_CMD2, ep_hotplug }, +}; + +static int pcie_mt_send_msg(void *msg_info, u32 msg_size, void *resp_msg, u32 resp_size) +{ + struct zxdh_pci_bar_msg in = {0}; + struct zxdh_msg_recviver_mem result = {0}; + struct pci_dev *pdev = NULL; + void __iomem *bar_virt_addr = NULL; + u16 ret = 0, pcie_id = 0; + u64 bar_addr = 0; + + if (msg_info == NULL) + { + DH_LOG_ERR(MODULE_FUC_HP, "The msg_info is NULL\n"); + return -EINVAL; + } + + pdev = pci_get_device(FUC_HP_VENDOR_ID, FUC_HP_DEVICE_ID, NULL); + if (pdev == NULL) + { + DH_LOG_ERR(MODULE_FUC_HP, "Can not find devices: deviceID %x, VendorID: %x\n", FUC_HP_VENDOR_ID, FUC_HP_DEVICE_ID); + return -EINVAL; + } + + bar_addr = pci_resource_start(pdev, 0); + DH_LOG_INFO(MODULE_FUC_HP, "bar_addr->0x%llx\n", bar_addr); + bar_virt_addr = ioremap(bar_addr, FUC_HP_IOREMAP_SIZE); + + /* 填充用户参数in */ + in.virt_addr = (u64)bar_virt_addr + FUC_HP_BAR_MSG_OFFSET; /* 使用PF1的bar0偏移8k */ + in.payload_addr = msg_info; /* 消息静荷buffer地址 */ + in.payload_len = msg_size; /* 消息长度 */ + in.src = MSG_CHAN_END_PF; /* 从mpf通道下发 */ + in.dst = MSG_CHAN_END_RISC; /* 消息发到risc */ + in.event_id = FUC_HP_EVENT_ID; /* 调用PCIE的消息处理函数 */ + in.src_pcieid = pcie_id; + + result.buffer_len = BUF_SIZE; /* 用户准备一个存放消息回复的buffer, buffer长度 */ + result.recv_buffer = kmalloc(result.buffer_len, GFP_KERNEL); /* 消息回复buffer地址 */ + if (!result.recv_buffer) + { + DH_LOG_ERR(MODULE_FUC_HP, "Failed to allocate recv_buffer\n"); + return -EINVAL; + } + + memset(result.recv_buffer, 0, result.buffer_len); + + ret = zxdh_bar_chan_sync_msg_send(&in, &result); /* 发送同步消息 */ + + iounmap(bar_virt_addr); + + /* 如果接口返回值不为0，则说明消息失败 */ + if (ret != 0) + { + DH_LOG_ERR(MODULE_FUC_HP, "pcie send msg failed, ret:%d.\n", ret); + goto exit; + } + + /* 如果消息发送成功， 从recv_buffer + 1的位置往后两字节取回复数据长度， recv_buffer + 4的位置开始取数据内容 */ + if (*((u8 *)(result.recv_buffer + 4)) == 0x1) + { + memcpy(resp_msg, result.recv_buffer + 4, resp_size); + ret = 0; + } + else + { + DH_LOG_ERR(MODULE_FUC_HP, "pcie result failed!\n"); + ret = -EINVAL; + } + +exit: + kfree(result.recv_buffer); + result.recv_buffer = NULL; + return ret; +} + +static int fuc_hotplug_trigger(u64 arg) +{ + int ret = 0; + int resp_msg = 0; + struct fuc_hotplug_bar_msg fuc_hotplug_bar_msg = {0}; + + if (copy_from_user(&fuc_hotplug_bar_msg, (void __user *)arg, sizeof(struct fuc_hotplug_bar_msg))) + { + DH_LOG_ERR(MODULE_FUC_HP, "Can not copy from user\n"); + return -EFAULT; + } + + ret = pcie_mt_send_msg(&fuc_hotplug_bar_msg, sizeof(struct fuc_hotplug_bar_msg), &resp_msg, sizeof(int)); + if (ret != 0) + { + DH_LOG_ERR(MODULE_FUC_HP, "send failed\n"); + fuc_hotplug_bar_msg.cpl_chk = FUC_HP_RET_FAILED; + } + else + { + fuc_hotplug_bar_msg.cpl_chk = FUC_HP_RET_FINISH; + } + + if (copy_to_user((void __user *)arg, &fuc_hotplug_bar_msg, sizeof(struct fuc_hotplug_bar_msg))) + { + DH_LOG_ERR(MODULE_FUC_HP, "Can not copy to user\n"); + ret = -EFAULT; + } + + return ret; +} + +static int fuc_hotplug_get_pf_state(u64 arg) +{ + int ret = FUC_HP_OK; + struct get_pf_state_resp get_pf_state_resp = {0}; + struct get_pf_state_info get_pf_state_info = {0}; + + if (copy_from_user(&get_pf_state_info, (void __user *)arg, sizeof(struct get_pf_state_info))) + { + DH_LOG_ERR(MODULE_FUC_HP, "Can not copy from user\n"); + return -EFAULT; + } + + ret = pcie_mt_send_msg(&get_pf_state_info, sizeof(struct get_pf_state_info), (void *)&get_pf_state_resp, sizeof(struct get_pf_state_resp)); + if (ret) + { + DH_LOG_ERR(MODULE_FUC_HP, "Remote test failed\n"); + goto finish; + } + + if (get_pf_state_info.ep_no >= MAX_FUCTION_HOTPLUG_EP_NUMS) + { + DH_LOG_ERR(MODULE_FUC_HP, "Invalid ep_id\n"); + ret = -EINVAL; + goto finish; + } + + get_pf_state_info.cpl_chk = ( get_pf_state_resp.pf_state_of_ep[get_pf_state_info.ep_no] >> get_pf_state_info.pf_no) & 0x1; + if (copy_to_user((void __user *)arg, &get_pf_state_info, sizeof(struct get_pf_state_info))) + { + DH_LOG_ERR(MODULE_FUC_HP, "Can not copy to user\n"); + ret = -EFAULT; + } + + return ret; + +finish: + get_pf_state_info.cpl_chk = FUNCTION_INVALID_TYPE; + if (copy_to_user((void __user *)arg, &get_pf_state_info, sizeof(struct get_pf_state_info))) + { + DH_LOG_ERR(MODULE_FUC_HP, "Can not copy to user\n"); + ret = -EFAULT; + } + + return ret; +} + +static int ep_hotplug(u64 arg) +{ + int ret = FUC_HP_OK; + struct ep_hotplug_resp ep_hotplug_resp = {0}; + struct ep_hotplug_info ep_hotplug_info = {0}; + + if (copy_from_user(&ep_hotplug_info, (void __user *)arg, sizeof(struct ep_hotplug_info))) + { + DH_LOG_ERR(MODULE_FUC_HP, "Can not copy from user\n"); + return -EFAULT; + } + + ret = pcie_mt_send_msg(&ep_hotplug_info, sizeof(struct ep_hotplug_info), (void *)&ep_hotplug_resp, sizeof(struct ep_hotplug_resp)); + if (ret) + { + DH_LOG_ERR(MODULE_FUC_HP, "Remote test failed\n"); + goto finish; + } + + ep_hotplug_info.cpl_chk = FUC_HP_RET_FINISH; + if (copy_to_user((void __user *)arg, &ep_hotplug_info, sizeof(struct ep_hotplug_info))) + { + DH_LOG_ERR(MODULE_FUC_HP, "Can not copy to user\n"); + ret = -EFAULT; + } + + return ret; + +finish: + ep_hotplug_info.cpl_chk = FUC_HP_RET_FAILED; + if (copy_to_user((void __user *)arg, &ep_hotplug_info, sizeof(struct ep_hotplug_info))) + { + DH_LOG_ERR(MODULE_FUC_HP, "Can not copy to user\n"); + ret = -EFAULT; + } + + return ret; +} + + +long fuc_hp_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) +{ + u32 i = 0; + u32 ioctl_func_nums = sizeof(ioctl_func_sel) / sizeof(struct func_sel); + + for (i = 0; i < ioctl_func_nums; i++) + { + if (ioctl_func_sel[i].cmd == cmd) + { + return ioctl_func_sel[i].ioctl_func(arg); + } + } + + return -EINVAL; +} diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/fuc_hotplug/fuc_hotplug.h b/src/net/drivers/net/ethernet/dinghai/zf_mpf/fuc_hotplug/fuc_hotplug.h new file mode 100644 index 0000000..d2ec80b --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/fuc_hotplug/fuc_hotplug.h @@ -0,0 +1,62 @@ +#ifndef _FUC_HOTPLUG_H_ +#define _FUC_HOTPLUG_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define FUC_HP_EVENT_ID 44 +#define BUF_SIZE 0x1000 + +/* bar消息通道使用pf信息 */ +#define FUC_HP_BAR_MSG_OFFSET (0x2000) +#define FUC_HP_VENDOR_ID (0x1cf2) +#define FUC_HP_DEVICE_ID (0x8044) +#define FUC_HP_IOREMAP_SIZE (0x3000) + +#define FUC_HP_POLLING_SPAN 100 +#define FUC_HP_TIMEOUT_TH 3000 + +/* data type */ +typedef unsigned long long int u64; +typedef signed long long int s64; + +typedef unsigned int u32; +typedef signed int s32; + +typedef unsigned short int u16; +typedef signed short int s16; + +typedef unsigned char u8; +typedef signed char s8; + +struct func_sel { + unsigned int cmd; + int (*ioctl_func)(unsigned long long arg); +}; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/fuc_hotplug/fuc_hotplug_commom.h b/src/net/drivers/net/ethernet/dinghai/zf_mpf/fuc_hotplug/fuc_hotplug_commom.h new file mode 100644 index 0000000..c759a56 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/fuc_hotplug/fuc_hotplug_commom.h @@ -0,0 +1,79 @@ +#ifndef __FUC_HOTPLUG_COMMOM_H +#define __FUC_HOTPLUG_COMMOM_H + +#define ARG_START_NO 3 +#define ARG_TYPE_NO 1 +#define FUC_HP_OK 0 +#define FUC_HP_FAILED -1 + + +#define FUC_HP_IOCTL_TYPE '>' +#define FUC_HP_IOCTL_MAGIC 117 /* random */ +#define FUC_HP_IOCTL_CMD0 (_IO(FUC_HP_IOCTL_TYPE, FUC_HP_IOCTL_MAGIC + 0)) +#define FUC_HP_IOCTL_CMD1 (_IO(FUC_HP_IOCTL_TYPE, FUC_HP_IOCTL_MAGIC + 1)) +#define FUC_HP_IOCTL_CMD2 (_IO(FUC_HP_IOCTL_TYPE, FUC_HP_IOCTL_MAGIC + 2)) + +#define MIN_EP_ID 5 +#define MAX_FUCTION_HOTPLUG_EP_NUMS 4 + +#define FUC_HOTPLUG_MEMBER_NUMS 10 +struct fuc_hotplug_bar_msg { + unsigned int cmd; + unsigned int fuc_hotplug_info; + unsigned int timeout; + unsigned int cpl_chk; +}; + +#define FUC_HOTPLUG_TIMEOUT_NUMS 1 +struct fuc_hotplug_set_timeout { + unsigned int timeout; + unsigned int cpl_chk; +}; + +struct get_pf_state_info { + unsigned int cmd; + unsigned int ep_no; + unsigned int pf_no; + unsigned int cpl_chk; +}; + +struct get_pf_state_resp { + uint8_t check_cpl; + uint8_t pf_state_of_ep[MAX_FUCTION_HOTPLUG_EP_NUMS]; +}; + +#define EP_HOTPLUG_MEMBER_NUMS 4 +struct ep_hotplug_info { + unsigned int cmd; + unsigned int ops_type; + unsigned int ep_no; + unsigned int cpl_chk; +}; + +struct ep_hotplug_resp { + uint8_t check_cpl; +}; + + +typedef enum { + FUC_HP_RET_TIMEOUT = 0, + FUC_HP_RET_FINISH, + FUC_HP_RET_FAILED, + INVALID_FUC_HP_RETURE +} FUC_HP_RETURE; + +typedef enum { + FUNCTION_REMOVE = 1, + FUNCTION_INSERT, + FUNCTION_INVALID_TYPE, +} FUNCTION_HP_TYPE; + +typedef enum { + FUC_HP_BAR_MSG_CMD = 1, + USED_BY_HOST_HP, + GET_STATE_BAR_MSG_CMD, + EP_HP_BAR_MSG_CMD, + INVALID_CMD, +} HOTPLUG_CMD; + +#endif \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/fuc_hotplug/fuc_hotplug_ioctl.c b/src/net/drivers/net/ethernet/dinghai/zf_mpf/fuc_hotplug/fuc_hotplug_ioctl.c new file mode 100644 index 0000000..af486e0 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/fuc_hotplug/fuc_hotplug_ioctl.c @@ -0,0 +1,76 @@ +#include "fuc_hotplug_ioctl.h" +#include "fuc_hotplug_commom.h" + +static dev_t dev; +static struct cdev c_dev; +static struct class *cl; + +extern long fuc_hp_ioctl(struct file *filp, unsigned int cmd, unsigned long arg); + +static int fuc_hp_open(struct inode *inode, struct file *file) +{ + if (inode->i_private) + { + file->private_data = inode->i_private; + } + + return FUC_HP_OK; +} + +static int fuc_hp_dev_release(struct inode *i, struct file *f) +{ + DH_LOG_INFO(MODULE_FUC_HP, "fuc_hp device released!\n"); + return FUC_HP_OK; +} + +static struct file_operations fuc_hp_fops = +{ + .owner = THIS_MODULE, + .open = fuc_hp_open, + .release = fuc_hp_dev_release, + .unlocked_ioctl = fuc_hp_ioctl, +}; + +int zxdh_host_fuc_hotplug_driver_init(void) +{ + int ret = FUC_HP_OK; + + if (alloc_chrdev_region(&dev, 0, 1, DEVICE_NAME) < 0) + { + return -EBUSY; + } + + if ((cl = class_create(THIS_MODULE, CLASS_NAME)) == NULL) + { + unregister_chrdev_region(dev, 1); + return -ENOMEM; + } + + if (device_create(cl, NULL, dev, NULL, DEVICE_NAME) == NULL) + { + class_destroy(cl); + unregister_chrdev_region(dev, 1); + return -ENOMEM; + } + + cdev_init(&c_dev, &fuc_hp_fops); + + if (cdev_add(&c_dev, dev, 1) == FUC_HP_FAILED) + { + device_destroy(cl, dev); + class_destroy(cl); + unregister_chrdev_region(dev, 1); + return -ENOMEM; + } + DH_LOG_INFO(MODULE_FUC_HP, "fuction_hotplug device registered\n"); + return ret; +} + +void zxdh_host_fuc_hotplug_driver_exit(void) +{ + cdev_del(&c_dev); + device_destroy(cl, dev); + class_destroy(cl); + unregister_chrdev_region(dev, 1); + DH_LOG_INFO(MODULE_FUC_HP, "fuc_hp device unregistered\n"); +} \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/fuc_hotplug/fuc_hotplug_ioctl.h b/src/net/drivers/net/ethernet/dinghai/zf_mpf/fuc_hotplug/fuc_hotplug_ioctl.h new file mode 100644 index 0000000..58eb6e6 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/fuc_hotplug/fuc_hotplug_ioctl.h @@ -0,0 +1,20 @@ +#ifndef __DPU_FUC_HOTPLUG_IOCTL_H +#define __DPU_FUC_HOTPLUG_IOCTL_H + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DEVICE_NAME "fuc_hp_ioctl" +#define CLASS_NAME "fuc_hp_class" + +#endif \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/fuc_hotplug/fuc_hp_app/build.sh b/src/net/drivers/net/ethernet/dinghai/zf_mpf/fuc_hotplug/fuc_hp_app/build.sh new file mode 100755 index 0000000..724f8d5 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/fuc_hotplug/fuc_hp_app/build.sh @@ -0,0 +1,5 @@ +#!/bin/bash + +# 按需选择是否需要静态编译 +gcc fuc_hp_app.c -o dpu_hotplug +# gcc -static gcc fuc_hp_app.c -o dpu_hotplug diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/fuc_hotplug/fuc_hp_app/fuc_hp_app.c b/src/net/drivers/net/ethernet/dinghai/zf_mpf/fuc_hotplug/fuc_hp_app/fuc_hp_app.c new file mode 100644 index 0000000..940ad51 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/fuc_hotplug/fuc_hp_app/fuc_hp_app.c @@ -0,0 +1,271 @@ +#include "fuc_hp_app.h" +#include "../fuc_hotplug_commom.h" + +static int printf_usage(int argc, char *argv[]); +static int fuc_hp(int argc, char *argv[]); +static int ep_hp(int argc, char *argv[]); + +static int printf_usage(int argc, char *argv[]) +{ + printf("** dpu_hotplug -s fuc -e epid -p pfid -v vfid -o add/del -t time \n"); + printf("** -s 指定拔插场景,fuction级热插拔固定输入:fuc \n"); + printf("** -e 指定epid \n"); + printf("** -p 指定pfid \n"); + printf("** -v 指定vfid, vfid为0,表示pf \n"); + printf("** vfid > 0,表示vf,vfid_real = vfid - 1 \n"); + printf("** -o 指定插拔操作, add 插入,del 拔出 \n"); + printf("** -t 指定超时时间，单位:s \n"); + printf("** \n"); + printf("** dpu_hotplug -s ep -e epid -o add/del \n"); + printf("** -s 指定拔插场景,ep级热插拔固定输入:ep \n"); + printf("** -e 指定epid \n"); + printf("** -o 指定插拔操作, add 插入,del 拔出 \n"); + return FUC_HP_OK; +}; + +struct fuc_hp_app_input fuc_hp_app_input[] = { + /* ops_type ops_value*/ + {"-e", 0}, + {"-p", 0}, + {"-v", 0}, + {"-o", 0}, + {"-t", 0} +}; + +struct fuc_hp_app_input ep_hp_app_input[] = { + /* ops_type ops_value*/ + {"-e", 0}, + {"-o", 0}, +}; + +static int parse_fuc_hp_input(struct fuc_hotplug_bar_msg *fuc_hotplug_bar_msg) +{ + fuc_hotplug_bar_msg->fuc_hotplug_info = ((fuc_hp_app_input[EP_ID].input_value + MIN_EP_ID) << FUNC_HP_EP_ID_START_BIT) + | (fuc_hp_app_input[PF_ID].input_value << FUNC_HP_PF_ID_START_BIT); + + if (fuc_hp_app_input[VF_ID].input_value != 0) + { + fuc_hotplug_bar_msg->fuc_hotplug_info |= ((fuc_hp_app_input[2].input_value - 1) << FUNC_HP_VF_ID_START_BIT); + fuc_hotplug_bar_msg->fuc_hotplug_info |= (1 << FUNC_HP_FUNC_TYPE_START_BIT); + } + + if (fuc_hp_app_input[OPS_ID].input_value != 0) + { + fuc_hotplug_bar_msg->fuc_hotplug_info |= (fuc_hp_app_input[OPS_ID].input_value << FUNC_HP_SCENE_CODE_START_BIT); + } + else + { + return FUC_HP_FAILED; + } + + fuc_hotplug_bar_msg->timeout = fuc_hp_app_input[TIMEOUT_ID].input_value; + + printf("value:0x%x timeout:%ds\n", fuc_hotplug_bar_msg->fuc_hotplug_info, fuc_hotplug_bar_msg->timeout); + + return FUC_HP_OK; +} + +static int fuc_hp(int argc, char *argv[]) +{ + int ret = FUC_HP_OK; + int fd = 0; + int arg_no = ARG_START_NO; + int input_no = 0; + char *stop_at = NULL; + struct fuc_hotplug_bar_msg *fuc_hotplug_bar_msg = NULL; + + fuc_hotplug_bar_msg = malloc(sizeof(struct fuc_hotplug_bar_msg)); + + fuc_hotplug_bar_msg->fuc_hotplug_info = 0; + + if (argc != FUC_HOTPLUG_MEMBER_NUMS + ARG_START_NO) + { + printf("[%s]: Invalid argument count %d\n", __func__, argc); + printf_usage(argc, argv); + goto failed; + } + + while (arg_no < argc) + { + if (strcmp(argv[arg_no++], fuc_hp_app_input[input_no].input_type) == 0) + { + if (input_no == OPS_ID) + { + fuc_hp_app_input[input_no++].input_value = strcmp(argv[arg_no], "add") == 0 ? FUNCTION_INSERT : + strcmp(argv[arg_no], "del") == 0 ? FUNCTION_REMOVE : 0; + arg_no++; + } + else + { + fuc_hp_app_input[input_no++].input_value = strtoul(argv[arg_no++], &stop_at, 0); + } + } + else + { + printf("[%s]: Invalid input %s\n", __func__, fuc_hp_app_input[input_no].input_type); + printf_usage(argc, argv); + goto failed; + } + } + + ret = parse_fuc_hp_input(fuc_hotplug_bar_msg); + if(ret != FUC_HP_OK) + { + printf_usage(argc, argv); + goto failed; + } + + fuc_hotplug_bar_msg->cmd = FUC_HP_BAR_MSG_CMD; + + fd = open(FUC_HP_IOCTRL_DEV_NAME, O_RDWR, 0); + if (fd < 0) + { + printf("[%s]: Can not open %s \n", __func__, FUC_HP_IOCTRL_DEV_NAME); + goto failed; + } + + ret = ioctl(fd, FUC_HP_IOCTL_CMD0, fuc_hotplug_bar_msg); + if (ret) + { + printf("[%s]: ERR --> %d\n", __func__, ret); + goto finish; + } + + if (fuc_hotplug_bar_msg->cpl_chk == FUC_HP_RET_FINISH) + { + printf("[%s] fuction hotplug finish!!\n", __func__); + } + else if (fuc_hotplug_bar_msg->cpl_chk == FUC_HP_RET_FAILED) + { + printf("[%s] fuction hotplug failed!\n", __func__); + } + else + { + printf("[%s] fuction hotplug timeout!!!\n", __func__); + } + +finish: + free(fuc_hotplug_bar_msg); + fuc_hotplug_bar_msg = NULL; + close(fd); + return ret; + +failed: + free(fuc_hotplug_bar_msg); + fuc_hotplug_bar_msg = NULL; + return ret; +} + +static int ep_hp(int argc, char *argv[]) +{ + int ret = FUC_HP_OK; + int fd = 0; + int arg_no = ARG_START_NO; + int input_no = 0; + char *stop_at = NULL; + struct ep_hotplug_info *ep_hotplug_info = NULL; + + ep_hotplug_info = malloc(sizeof(struct ep_hotplug_info)); + + if (argc != EP_HOTPLUG_MEMBER_NUMS + ARG_START_NO) + { + printf("[%s]: Invalid argument count %d\n", __func__, argc); + printf_usage(argc, argv); + goto failed; + } + + while (arg_no < argc) + { + if (strcmp(argv[arg_no++], ep_hp_app_input[input_no].input_type) == 0) + { + if (input_no == E_OPS_ID) + { + ep_hp_app_input[input_no++].input_value = strcmp(argv[arg_no], "add") == 0 ? FUNCTION_INSERT : + strcmp(argv[arg_no], "del") == 0 ? FUNCTION_REMOVE : 0; + arg_no++; + } + else + { + ep_hp_app_input[input_no++].input_value = strtoul(argv[arg_no++], &stop_at, 0); + } + } + else + { + printf("[%s]: Invalid input %s\n", __func__, ep_hp_app_input[input_no].input_type); + printf_usage(argc, argv); + goto failed; + } + } + + ep_hotplug_info->cmd = EP_HP_BAR_MSG_CMD; + ep_hotplug_info->ep_no = ep_hp_app_input[E_EP_ID].input_value; + ep_hotplug_info->ops_type = ep_hp_app_input[E_OPS_ID].input_value; + + fd = open(FUC_HP_IOCTRL_DEV_NAME, O_RDWR, 0); + if (fd < 0) + { + printf("[%s]: Can not open %s \n", __func__, FUC_HP_IOCTRL_DEV_NAME); + goto failed; + } + + ret = ioctl(fd, FUC_HP_IOCTL_CMD2, ep_hotplug_info); + if (ret) + { + printf("[%s]: ERR --> %d\n", __func__, ret); + goto finish; + } + + if (ep_hotplug_info->cpl_chk == FUC_HP_RET_FINISH) + { + printf("[%s] ep hotplug finish!!\n", __func__); + } + else if (ep_hotplug_info->cpl_chk == FUC_HP_RET_FAILED) + { + printf("[%s] ep hotplug failed!\n", __func__); + } + else + { + printf("[%s] ep hotplug timeout!!!\n", __func__); + } + +finish: + free(ep_hotplug_info); + ep_hotplug_info = NULL; + close(fd); + return ret; + +failed: + free(ep_hotplug_info); + ep_hotplug_info = NULL; + return ret; +} + +int main(int argc, char *argv[]) +{ + int ret = 0; + int arg_no = ARG_TYPE_NO; + + if (argc < ARG_START_NO) + { + printf("[%s]: Invalid argument count %d\n", __func__, argc); + printf_usage(argc, argv); + ret = FUC_HP_FAILED; + goto failed; + } + + printf("start\n"); + if (strcmp(argv[arg_no++], "-s") == 0) + { + if (strcmp(argv[arg_no], "ep") == 0) + { + ret = ep_hp(argc, argv); + } + else if(strcmp(argv[arg_no], "fuc") == 0) + { + ret = fuc_hp(argc, argv); + } + } + +failed: + return ret; +} diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/fuc_hotplug/fuc_hp_app/fuc_hp_app.h b/src/net/drivers/net/ethernet/dinghai/zf_mpf/fuc_hotplug/fuc_hp_app/fuc_hp_app.h new file mode 100644 index 0000000..2770481 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/fuc_hotplug/fuc_hp_app/fuc_hp_app.h @@ -0,0 +1,51 @@ +#ifndef __DPMT_APP_H +#define __DPMT_APP_H + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "sys/ioctl.h" + +#define FUC_HP_IOCTRL_DEV_NAME "/dev/fuc_hp_ioctl" + + +#define FUNC_HP_SCENE_CODE_START_BIT 21 +#define FUNC_HP_FUNC_TYPE_START_BIT 20 +#define FUNC_HP_EP_ID_START_BIT 16 +#define FUNC_HP_PF_ID_START_BIT 12 +#define FUNC_HP_VF_ID_START_BIT 0 + +struct hp_app_func { + char *name; + int (*func)(int argc, char *argv[]); +}; + +struct fuc_hp_app_input { + char *input_type; + unsigned int input_value; +}; + +typedef enum { + EP_ID = 0, + PF_ID, + VF_ID, + OPS_ID, + TIMEOUT_ID, + INVALID_FUC_HP_INPUT +} FUC_HP_INPUT; + +typedef enum { + E_EP_ID = 0, + E_OPS_ID, + E_INVALID_FUC_HP_INPUT +} EP_HP_INPUT; + +#endif \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/gdma.c b/src/net/drivers/net/ethernet/dinghai/zf_mpf/gdma.c new file mode 100644 index 0000000..8335534 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/gdma.c @@ -0,0 +1,550 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "gdma.h" +#include "zf_mpf.h" + +/* + * User define: + * ep_id-bit[15:12] vfunc_num-bit[11:4] func_num-bit[3:1] vfunc_active-bit0 + * host ep_id:5~8 zf ep_id:9 + */ +#define ZF_GDMA_ZF_USER (0x9000) /* ep4 pf0 */ +#define ZF_GDMA_PF_NUM_SHIFT (1) +#define ZF_GDMA_VF_NUM_SHIFT (4) +#define ZF_GDMA_EP_ID_SHIFT (12) +#define ZF_GDMA_VF_EN (1) +#define ZF_GDMA_VF_MASK (1UL << 7) + +/* Register offset */ +#define ZF_GDMA_BASE_OFFSET (0x100000) +#define ZF_GDMA_CHAN_SHIFT (0x80) +#define ZF_GDMA_EXT_ADDR_OFFSET (0x218) +#define ZF_GDMA_SAR_LOW_OFFSET (0x200) +#define ZF_GDMA_DAR_LOW_OFFSET (0x204) +#define ZF_GDMA_SAR_HIGH_OFFSET (0x234) +#define ZF_GDMA_DAR_HIGH_OFFSET (0x238) +#define ZF_GDMA_XFERSIZE_OFFSET (0x208) +#define ZF_GDMA_CONTROL_OFFSET (0x230) +#define ZF_GDMA_TC_STATUS_OFFSET (0x0) +#define ZF_GDMA_STATUS_CLEAN_OFFSET (0x80) +#define ZF_GDMA_LINKADDR_LOW_OFFSET (0x21c) +#define ZF_GDMA_LINKADDR_HIGH_OFFSET (0x220) +#define ZF_GDMA_CHAN_CONTINUE_OFFSET (0x224) +#define ZF_GDMA_TC_CNT_OFFSET (0x23c) +#define ZF_GDMA_LLI_USER_OFFSET (0x228) +#define ZF_GDMA_PULSE_WIDTH_OFFSET (0x1ec) + +/* Control register */ +#define ZF_GDMA_CHAN_ENABLE (1UL) +#define ZF_GDMA_SOFT_CHAN (1UL << 1) +#define ZF_GDMA_TC_INTR_ENABLE (1UL << 4) +#define ZF_GDMA_ERR_INTR_ENABLE (1UL << 5) +#define ZF_GDMA_SBS_SHIFT (6) /* src burst size */ +#define ZF_GDMA_SBL_SHIFT (9) /* src burst length */ +#define ZF_GDMA_DBS_SHIFT (13) /* dest burst size */ +#define ZF_GDMA_BURST_SIZE_MIN (0x1) /* 1 byte */ +#define ZF_GDMA_BURST_SIZE_MEDIUM (0x4) /* 4 word */ +#define ZF_GDMA_BURST_SIZE_MAX (0x6) /* 16 word */ +#define ZF_GDMA_DEFAULT_BURST_LEN (0xf) /* 16 beats */ +#define ZF_GDMA_TC_CNT_ENABLE (1UL << 27) +#define ZF_GDMA_CHAN_FORCE_CLOSE (1UL << 31) + +/* TC count & Error interrupt status register */ +#define ZF_GDMA_SRC_LLI_ERR (1UL << 16) +#define ZF_GDMA_SRC_DATA_ERR (1UL << 17) +#define ZF_GDMA_DST_ADDR_ERR (1UL << 18) +#define ZF_GDMA_ERR_STATUS (1UL << 19) +#define ZF_GDMA_ERR_RPT_ENABLE (1UL << 20) +#define ZF_GDMA_TC_CNT_CLEAN (1) + +#define ZF_GDMA_ALIGN_SIZE (1) +#define ZF_GDMA_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)) +#define ZF_GDMA_BUFF_SIZE_MAX (0xfffff) + +#define LOW16_MASK (0xffff) +#define LOW32_MASK (0xffffffff) + +void gchan_irq_tasklet_process(unsigned long data); +static void zf_gdma_enqueue_buff(struct zf_gdma_chan *gchan); + +static struct zf_gdma_chan *to_zf_gdma_chan(struct dma_chan *chan) +{ + return container_of(chan, struct zf_gdma_chan, vc.chan); +} + +static struct zf_gdma_desc *to_zf_gdma_desc(struct zxdh_virt_dma_desc *vdesc) +{ + return container_of(vdesc, struct zf_gdma_desc, vd); +} + +static inline uint32_t zf_gdma_read_reg(struct zf_gdma_chan *gchan, uint16_t chan_id, uint32_t offset) +{ + uint64_t addr = chan_id * ZF_GDMA_CHAN_SHIFT + offset; + + return *(volatile uint32_t *)(gchan->gdev->base_addr + addr); +} + +static inline void zf_gdma_write_reg(struct zf_gdma_chan *gchan, uint16_t chan_id, uint32_t offset, uint32_t val) +{ + uint64_t addr = chan_id * ZF_GDMA_CHAN_SHIFT + offset; + + *(volatile uint32_t *)(gchan->gdev->base_addr + addr) = val; +} + +static inline void zf_gdma_user_get(struct zf_rbp_info *rbp_info, uint32_t *user) +{ + uint32_t pf_id = rbp_info->pfid; + + //host addr + if (rbp_info->host) + { + if ((pf_id & ZF_GDMA_VF_MASK) != 0) + { + pf_id &= ~ZF_GDMA_VF_MASK; + *user = (ZF_GDMA_VF_EN | (rbp_info->vfid << ZF_GDMA_VF_NUM_SHIFT)); + } + *user |= ((rbp_info->epid << ZF_GDMA_EP_ID_SHIFT) | (pf_id << ZF_GDMA_PF_NUM_SHIFT)); + } + else + { + *user = ZF_GDMA_ZF_USER; + } +} + +static inline void zf_gdma_cfg_get(uint32_t *val, uint8_t tc_enable) +{ + *val = (ZF_GDMA_CHAN_ENABLE | ZF_GDMA_SOFT_CHAN | + ZF_GDMA_TC_INTR_ENABLE | ZF_GDMA_ERR_INTR_ENABLE | + (ZF_GDMA_DEFAULT_BURST_LEN << ZF_GDMA_SBL_SHIFT) | + (ZF_GDMA_BURST_SIZE_MAX << ZF_GDMA_SBS_SHIFT) | + (ZF_GDMA_BURST_SIZE_MAX << ZF_GDMA_DBS_SHIFT)); + + if (tc_enable != 0) + { + *val |= ZF_GDMA_TC_CNT_ENABLE; + } +} + +static void zf_gdma_desc_free(struct zxdh_virt_dma_desc *vd) +{ + if (vd != NULL) + { + kfree(to_zf_gdma_desc(vd)); + } +} + +static int32_t zf_gdma_alloc_chan_resources(struct dma_chan *chan) +{ + return 0; +} + +static void zf_gdma_free_chan_resources(struct dma_chan *chan) +{ + +} + +static int32_t zf_gdma_device_config(struct dma_chan *chan, struct dma_slave_config *config) +{ + return 0; +} + +static struct dma_async_tx_descriptor *zf_gdma_prep_dma_memcpy(struct dma_chan *chan, + dma_addr_t dst, + dma_addr_t src, + size_t len, + unsigned long flags) +{ + struct zf_gdma_chan *gchan = NULL; + struct zf_gdma_desc *desc = NULL; + struct zf_dma_addr_rbp *srbp = NULL; + struct zf_dma_addr_rbp *drbp = NULL; + uint32_t src_user = 0; + uint32_t dst_user = 0; + unsigned long status = 0; + + if ((chan == NULL) || ((void *)dst == NULL) || ((void *)src == NULL)) + { + printk(KERN_ERR "%s:param is invalid\n", __func__); + return ERR_PTR(-EINVAL); + } + + gchan = to_zf_gdma_chan(chan); + srbp = (struct zf_dma_addr_rbp *)src; + drbp = (struct zf_dma_addr_rbp *)dst; + + desc = kzalloc(sizeof(struct zf_gdma_desc), GFP_KERNEL); + if (desc == NULL) + { + printk(KERN_ERR "%s: Failed to alloc gdma desc\n", __func__); + return ERR_PTR(-ENOMEM); + } + + zf_gdma_user_get(&srbp->rbp_info, &src_user); + zf_gdma_user_get(&drbp->rbp_info, &dst_user); + + desc->user = ((src_user & LOW16_MASK) | (dst_user << 16)); + desc->src = (uint64_t)(srbp->addr); + desc->dst = (uint64_t)(drbp->addr); + desc->len = (uint64_t)len; + desc->chan = gchan; + spin_lock_irqsave(&gchan->chan_lock, status); + list_add_tail(&desc->node, &gchan->desc_list); + spin_unlock_irqrestore(&gchan->chan_lock, status); + + return zxdh_vchan_tx_prep(&gchan->vc, &desc->vd, flags); +} + +static void zf_gdma_issue_pending(struct dma_chan *chan) +{ + struct zf_gdma_chan *gchan = NULL; + unsigned long flags = 0; + bool pending = false; + + if (chan == NULL) + return; + + gchan = to_zf_gdma_chan(chan); + + spin_lock_irqsave(&gchan->vc.lock, flags); + if (zxdh_vchan_issue_pending(&gchan->vc)) + { + pending = true; + } + spin_unlock_irqrestore(&gchan->vc.lock, flags); + + if (pending) + { + zf_gdma_enqueue_buff(gchan); + } + + return; +} + +static enum dma_status zf_gdma_tx_status(struct dma_chan *chan, dma_cookie_t cookie, struct dma_tx_state *state) +{ + return 0; +} + +static int32_t zf_gdma_terminate_all(struct dma_chan *chan) +{ + return 0; +} + +void zf_gdma_dev_init(struct device *dev, struct dma_device *dd) +{ + dd->device_alloc_chan_resources = zf_gdma_alloc_chan_resources; + dd->device_free_chan_resources = zf_gdma_free_chan_resources; + dd->device_config = zf_gdma_device_config; + dd->device_prep_dma_memcpy = zf_gdma_prep_dma_memcpy; + dd->device_issue_pending = zf_gdma_issue_pending; + dd->device_tx_status = zf_gdma_tx_status; + dd->device_terminate_all = zf_gdma_terminate_all; + + dd->chancnt = ZF_GDMA_CHAN_NUM; + dd->privatecnt = 0; + dd->copy_align = ZF_GDMA_ALIGN_SIZE; + dd->src_addr_widths = ZF_GDMA_DMA_BUSWIDTHS; + dd->dst_addr_widths = ZF_GDMA_DMA_BUSWIDTHS; + dd->residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT; + dd->dev = dev; + + dma_cap_zero(dd->cap_mask); + dma_cap_set(DMA_RBP, dd->cap_mask); +} + +static int32_t zf_gdma_virt_chan_init(struct zf_gdma_dev *gdev) +{ + struct zf_gdma_chan *gchan = NULL; + uint32_t val = 0; + uint16_t i = 0; + + INIT_LIST_HEAD(&gdev->dd->channels); + for (i = 0; i < ZF_GDMA_CHAN_NUM; i++) + { + gchan = &gdev->chan[i]; + gchan->status = GDMA_CHAN_IDLE; + gchan->chan_id = ZF_GDMA_CHAN_BASE + i; + gchan->gdev = gdev; + gchan->vc.desc_free = zf_gdma_desc_free; + tasklet_init(&gchan->task, gchan_irq_tasklet_process, (unsigned long)gchan); + + zxdh_vchan_init(&gchan->vc, gdev->dd); + spin_lock_init(&gchan->chan_lock); + INIT_LIST_HEAD(&gchan->desc_list); + + /* reset gdma channel */ + val = ZF_GDMA_CHAN_FORCE_CLOSE; + zf_gdma_write_reg(gchan, gchan->chan_id, ZF_GDMA_CONTROL_OFFSET, val); + + val = ZF_GDMA_ERR_RPT_ENABLE | ZF_GDMA_ERR_STATUS | ZF_GDMA_TC_CNT_CLEAN; + zf_gdma_write_reg(gchan, gchan->chan_id, ZF_GDMA_TC_CNT_OFFSET, val); + } + + /* Configure interrupt pulse width to 8 cycle */ + zf_gdma_write_reg(gchan, 0, ZF_GDMA_PULSE_WIDTH_OFFSET, 7); + + return 0; +} + +static int32_t zf_gdma_xmit_done(struct zf_gdma_chan *gchan) +{ + struct zxdh_virt_dma_desc *vdesc = NULL; + uint32_t widx = gchan->chan_id / 32; + uint32_t bidx = gchan->chan_id % 32; + uint32_t val = 0; + unsigned long flags = 0; + + val = zf_gdma_read_reg(gchan, 0, ZF_GDMA_TC_STATUS_OFFSET + (widx * sizeof(uint32_t))); + if ((val & (1UL << bidx)) == 0) + { + printk(KERN_ERR "%s:chan%d tc status error\n", __func__, gchan->chan_id); + spin_lock(&gchan->chan_lock); + gchan->status = GDMA_CHAN_ERR; + spin_unlock(&gchan->chan_lock); + return -1; + } + + pr_debug("chan%d transfer success\n", gchan->chan_id); + zf_gdma_write_reg(gchan, 0, ZF_GDMA_STATUS_CLEAN_OFFSET + (widx * sizeof(uint32_t)), 1 << bidx); + + spin_lock(&gchan->chan_lock); + if (gchan->desc == NULL) + { + printk(KERN_ERR "%s:chan%d descriptor missing\n", __func__, gchan->chan_id); + gchan->status = GDMA_CHAN_ERR; + spin_unlock(&gchan->chan_lock); + return -1; + } + + if (gchan->desc->len == 0) + { + list_del(&gchan->desc->node); + vdesc = &gchan->desc->vd; + gchan->desc = NULL; + + spin_lock_irqsave(&gchan->vc.lock, flags); + list_del(&vdesc->node); + zxdh_vchan_cookie_complete(vdesc); + spin_unlock_irqrestore(&gchan->vc.lock, flags); + } + gchan->status = GDMA_CHAN_IDLE; + spin_unlock(&gchan->chan_lock); + + return 0; +} + +static void zf_gdma_enqueue_buff(struct zf_gdma_chan *gchan) +{ + struct zf_gdma_desc *desc = NULL; + struct zxdh_virt_dma_desc *vdesc = NULL; + uint32_t val = 0; + uint64_t cur_len = 0; + unsigned long flags = 0; + + spin_lock_irqsave(&gchan->chan_lock, flags); + if (gchan->status != GDMA_CHAN_IDLE) + { + goto out; + } + spin_lock(&gchan->vc.lock); + vdesc = zxdh_vchan_next_desc(&gchan->vc); + spin_unlock(&gchan->vc.lock); + if (vdesc == NULL) + { + goto out; + } + gchan->status = GDMA_CHAN_BUSY; + spin_unlock_irqrestore(&gchan->chan_lock, flags); + + desc = to_zf_gdma_desc(vdesc); + gchan->desc = desc; + cur_len = (desc->len > ZF_GDMA_BUFF_SIZE_MAX) ? ZF_GDMA_BUFF_SIZE_MAX : desc->len; + + zf_gdma_write_reg(gchan, gchan->chan_id, ZF_GDMA_SAR_LOW_OFFSET, desc->src & LOW32_MASK); + zf_gdma_write_reg(gchan, gchan->chan_id, ZF_GDMA_SAR_HIGH_OFFSET, (desc->src >> 32) & LOW32_MASK); + + zf_gdma_write_reg(gchan, gchan->chan_id, ZF_GDMA_DAR_LOW_OFFSET, desc->dst & LOW32_MASK); + zf_gdma_write_reg(gchan, gchan->chan_id, ZF_GDMA_DAR_HIGH_OFFSET, (desc->dst >> 32) & LOW32_MASK); + + zf_gdma_write_reg(gchan, gchan->chan_id, ZF_GDMA_XFERSIZE_OFFSET, cur_len); + + zf_gdma_write_reg(gchan, gchan->chan_id, ZF_GDMA_EXT_ADDR_OFFSET, desc->user); + + zf_gdma_cfg_get(&val, 1); + zf_gdma_write_reg(gchan, gchan->chan_id, ZF_GDMA_CONTROL_OFFSET, val); + + desc->src += cur_len; + desc->dst += cur_len; + desc->len -= cur_len; + + return; + +out: + spin_unlock_irqrestore(&gchan->chan_lock, flags); +} + +static void zf_gdma_free_channels(struct zf_gdma_dev *gdev) +{ + struct zf_gdma_chan *gchan = NULL; + struct zf_gdma_desc *desc = NULL; + struct zf_gdma_desc *tmp = NULL; + uint16_t i = 0; + unsigned long flags = 0; + + for (i = 0; i < ZF_GDMA_CHAN_NUM; i++) + { + gchan = &gdev->chan[i]; + tasklet_kill(&gchan->task); + + spin_lock_irqsave(&gchan->chan_lock, flags); + spin_lock(&gchan->vc.lock); + list_for_each_entry_safe(desc, tmp, &gchan->desc_list, node) + { + list_del(&desc->vd.node); + list_del(&desc->node); + kfree(desc); + } + spin_unlock(&gchan->vc.lock); + spin_unlock_irqrestore(&gchan->chan_lock, flags); + } +} + +int32_t dh_zf_mpf_gdma_init(struct dh_core_dev *dh_dev) +{ + struct dh_en_mpf_dev *mpf_dev = dh_core_priv(dh_dev); + struct zf_gdma_dev *gdev = NULL; + struct device *dev = NULL; + int32_t node = 0; + int32_t ret = 0; + + if (dh_dev->pdev == NULL) + { + printk(KERN_ERR "%s: pdev is invalid\n", __func__); + return -ENODEV; + } + + if (mpf_dev->pci_ioremap_addr == 0) + { + printk(KERN_ERR "%s: pci_ioremap_addr is invalid\n", __func__); + return -ENAVAIL; + } + + gdev = kzalloc(sizeof(struct zf_gdma_dev), GFP_KERNEL); + if (gdev == NULL) + { + printk(KERN_ERR "%s: Failed to alloc gdev\n", __FUNCTION__); + return -ENOMEM; + } + mpf_dev->gdev = gdev; + + gdev->base_addr = mpf_dev->pci_ioremap_addr + ZF_GDMA_BASE_OFFSET; + gdev->pdev = dh_dev->pdev; + dev = &(dh_dev->pdev->dev); + node = dev_to_node(dev); + gdev->dd = kzalloc_node(sizeof(struct dma_device), GFP_KERNEL, node); + if (gdev->dd == NULL) + { + printk(KERN_ERR "%s: Failed to alloc dma_device\n", __FUNCTION__); + ret = -ENOMEM; + goto free_gdev; + } + + zf_gdma_dev_init(dev, gdev->dd); + zf_gdma_virt_chan_init(gdev); + + ret = dma_async_device_register(gdev->dd); + if (ret != 0) + { + printk(KERN_ERR "%s: Failed to register gdma device\n", __func__); + goto err_out; + } + + return 0; + +err_out: + zf_gdma_free_channels(gdev); + kfree(gdev->dd); +free_gdev: + kfree(gdev); + return ret; +} + +void dh_zf_mpf_gdma_uninit(struct dh_core_dev *dh_dev) +{ + struct dh_en_mpf_dev *mpf_dev = dh_core_priv(dh_dev); + struct zf_gdma_dev *gdev = NULL; + + if (mpf_dev->gdev == NULL) + { + printk(KERN_ERR "%s:gdev is invalid\n", __func__); + return; + } + gdev = mpf_dev->gdev; + + if (gdev->dd != NULL) + { + dma_async_device_unregister(gdev->dd); + kfree(gdev->dd); + } + zf_gdma_free_channels(gdev); + kfree(gdev); +} + +int32_t zf_gdma_err_irq_handle(struct notifier_block *nb, unsigned long action, void *data) +{ + pr_debug("%s is called\n", __func__); + + return 0; +} + +int32_t zf_gdma_chan_irq_handle(struct notifier_block *nb, unsigned long action, void *data) +{ + struct dh_eq_async *eq = container_of(nb, struct dh_eq_async, irq_nb); + struct zf_gdma_chan *gchan = NULL; + + if (eq->priv == NULL) + { + printk(KERN_ERR "%s:eq->priv is NULL\n", __func__); + return -1; + } + gchan = (struct zf_gdma_chan *)eq->priv; + tasklet_hi_schedule(&gchan->task); + + return 0; +} + +void gchan_irq_tasklet_process(unsigned long data) +{ + struct zf_gdma_chan *gchan = NULL; + + if (unlikely(data == 0)) + { + printk(KERN_ERR "%s:param is invalid\n", __func__); + return; + } + + gchan = (struct zf_gdma_chan *)data; + if (zf_gdma_xmit_done(gchan) != 0) + return; + + zf_gdma_enqueue_buff(gchan); +} \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/gdma.h b/src/net/drivers/net/ethernet/dinghai/zf_mpf/gdma.h new file mode 100644 index 0000000..303be03 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/gdma.h @@ -0,0 +1,67 @@ +#ifndef __GDMA_H +#define __GDMA_H + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "./epc/virt-dma.h" + +#define ZF_GDMA_CHAN_NUM (4) +#define ZF_GDMA_CHAN_BASE (58) + +enum zf_gdma_chan_status +{ + GDMA_CHAN_IDLE = 0, + GDMA_CHAN_BUSY, + GDMA_CHAN_ERR +}; + +struct zf_gdma_chan +{ + enum zf_gdma_chan_status status; + uint16_t chan_id; + + struct list_head desc_list; + spinlock_t chan_lock; + + struct zf_gdma_dev *gdev; + struct zxdh_virt_dma_chan vc; + struct zf_gdma_desc *desc; + struct tasklet_struct task; +}; + +struct zf_gdma_desc +{ + uint64_t src; /* src addr */ + uint64_t dst; + uint64_t len; + uint32_t user; + struct zxdh_virt_dma_desc vd; + struct list_head node; + struct zf_gdma_chan *chan; +}; + +struct zf_gdma_dev +{ + uint64_t base_addr; + struct dma_device *dd; + struct pci_dev *pdev; + struct zf_gdma_chan chan[ZF_GDMA_CHAN_NUM]; +}; + +int32_t dh_zf_mpf_gdma_init(struct dh_core_dev *dh_dev); +void dh_zf_mpf_gdma_uninit(struct dh_core_dev *dh_dev); +int32_t zf_gdma_err_irq_handle(struct notifier_block *nb, unsigned long action, void *data); +int32_t zf_gdma_chan_irq_handle(struct notifier_block *nb, unsigned long action, void *data); + +#endif \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/irq.c b/src/net/drivers/net/ethernet/dinghai/zf_mpf/irq.c new file mode 100755 index 0000000..9e957a7 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/irq.c @@ -0,0 +1,169 @@ +#include +#include +#include +#include "irq.h" + +static struct dh_irq_range zxdh_get_mpf_range(struct dh_core_dev *dev) +{ + struct dh_irq_range tmp = { + .start = 0, + .size = ZXDH_MPF_ASYNC_IRQ_NUM + }; + + return tmp; +} +static struct dh_irq_range zxdh_get_comp_mpf_range(struct dh_core_dev *dev) +{ + struct dh_irq_range tmp = { + .start = ZXDH_MPF_ASYNC_IRQ_NUM, + .size = ZXDH_MPF_COMP_IRQ_NUM + }; + + return tmp; +} + +static struct dh_irq_range zxdh_get_gdma_irq_range(struct dh_core_dev *dev) +{ + struct dh_irq_range tmp = { + .start = ZXDH_MPF_GDMA_MSIX_VEC_BASE, + .size = ZXDH_MPF_GDMA_IRQ_NUM + }; + + return tmp; +} + +static int32_t irq_pools_init(struct dh_core_dev *dev) +{ + struct dh_irq_table *table = &dev->irq_table; + int32_t err = 0; + struct dh_irq_range irq_range; + struct dh_mpf_irq_table * mpf_irq_table = table->priv; + + /* init mpf_pool */ + irq_range = zxdh_get_mpf_range(dev); + mpf_irq_table->mpf_async_pool = irq_pool_alloc(dev, irq_range.start, irq_range.size, "zxdh_mpf_msg", + ZXDH_MPF_ASYNC_IRQ_MIN_COMP, + ZXDH_MPF_ASYNC_IRQ_MAX_COMP); + if (IS_ERR_OR_NULL(mpf_irq_table->mpf_async_pool)) + { + return PTR_ERR(mpf_irq_table->mpf_async_pool); + } + + /* init sf_comp_pool */ + irq_range = zxdh_get_comp_mpf_range(dev); + mpf_irq_table->mpf_comp_pool = irq_pool_alloc(dev, irq_range.start, + irq_range.size, "zxdh_mpf_comp", + ZXDH_MPF_COMP_IRQ_MIN_COMP, + ZXDH_MPF_COMP_IRQ_MAX_COMP); + if (IS_ERR_OR_NULL(mpf_irq_table->mpf_comp_pool)) + { + err = PTR_ERR(mpf_irq_table->mpf_comp_pool); + goto err_mpf_comp; + } + + mpf_irq_table->mpf_comp_pool->irqs_per_cpu = kcalloc(nr_cpu_ids, sizeof(u16), GFP_KERNEL); + if (unlikely(mpf_irq_table->mpf_comp_pool->irqs_per_cpu == NULL)) + { + err = -ENOMEM; + goto err_irqs_per_cpu; + } + + /* init gdma_irq_pool */ + irq_range = zxdh_get_gdma_irq_range(dev); + mpf_irq_table->mpf_gdma_pool = irq_pool_alloc(dev, irq_range.start, irq_range.size, "zxdh_mpf_gdma", + ZXDH_MPF_GDMA_IRQ_MIN, + ZXDH_MPF_GDMA_IRQ_MAX); + if (IS_ERR_OR_NULL(mpf_irq_table->mpf_gdma_pool)) + { + err = PTR_ERR(mpf_irq_table->mpf_gdma_pool); + goto err_irqs_per_cpu; + } + + return 0; + +err_irqs_per_cpu: + irq_pool_free(mpf_irq_table->mpf_comp_pool); +err_mpf_comp: + irq_pool_free(mpf_irq_table->mpf_async_pool); + return err; +} + +static void irq_pools_destroy(struct dh_irq_table *table) +{ + struct dh_mpf_irq_table *mpf_irq_table = (struct dh_mpf_irq_table *)table->priv; + + irq_pool_free(mpf_irq_table->mpf_comp_pool); + irq_pool_free(mpf_irq_table->mpf_async_pool); + irq_pool_free(mpf_irq_table->mpf_gdma_pool); +} + +/*todo*/ +static int32_t zxdh_get_total_vec(struct dh_core_dev *dev) +{ + return ZXDH_ZF_MPF_IRQ_NUM_TOTAL; +} + +int32_t dh_mpf_irq_table_create(struct dh_core_dev *dev) +{ + int32_t total_vec = 0; + int32_t err = 0; + + total_vec = zxdh_get_total_vec(dev); + + total_vec = pci_alloc_irq_vectors(dev->pdev, total_vec, total_vec, PCI_IRQ_MSIX); + if (total_vec < 0) + { + dh_err(dev, "pci_alloc_irq_vectors failed: %d\n", total_vec); + return total_vec; + } + + err = irq_pools_init(dev); + if (err != 0) + { + pci_free_irq_vectors(dev->pdev); + } + + return err; +} + +void dh_mpf_irq_table_destroy(struct dh_core_dev *dev) +{ + struct dh_irq_table *table = &dev->irq_table; + + /* There are cases where IRQs still will be in used when we reaching + * to here. Hence, making sure all the irqs are released. + */ + irq_pools_destroy(table); + pci_free_irq_vectors(dev->pdev); +} + +struct dh_irq *dh_mpf_async_irq_request(struct dh_core_dev *dev) +{ + struct dh_irq_table *table = &dev->irq_table; + struct dh_mpf_irq_table *mpf_irq_table = (struct dh_mpf_irq_table *)table->priv; + + struct dh_irq *irq = zxdh_get_irq_of_pool(dev, mpf_irq_table->mpf_async_pool); + if (IS_ERR_OR_NULL(irq)) + dh_err(dev, "irq=0x%llx\r\n", (unsigned long long)irq); + dh_dbg(dev, "end\r\n"); + return irq; +} + +/* irq_table API */ +int32_t dh_mpf_irq_table_init(struct dh_core_dev *dev) +{ + struct dh_irq_table *irq_table; + struct dh_mpf_irq_table *mpf_irq_table = NULL; + + irq_table = &dev->irq_table; + + mpf_irq_table = kvzalloc(sizeof(*mpf_irq_table), GFP_KERNEL); + if (unlikely(mpf_irq_table == NULL)) + { + return -ENOMEM; + } + + irq_table->priv = mpf_irq_table; + + return 0; +} diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/irq.h b/src/net/drivers/net/ethernet/dinghai/zf_mpf/irq.h new file mode 100755 index 0000000..7cdb29b --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/irq.h @@ -0,0 +1,49 @@ +#ifndef __ZXDH_MPF_IRQ_H__ +#define __ZXDH_MPF_IRQ_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#include "gdma.h" + +#define ZXDH_MPF_ASYNC_IRQ_NUM 6 +#define ZXDH_MPF_ASYNC_IRQ_MIN_COMP 0 +#define ZXDH_MPF_ASYNC_IRQ_MAX_COMP 1 + +#define ZXDH_MPF_COMP_IRQ_NUM 1 +#define ZXDH_MPF_COMP_IRQ_MIN_COMP 0 +#define ZXDH_MPF_COMP_IRQ_MAX_COMP 1 + +#define ZXDH_MPF_GDMA_IRQ_NUM (ZF_GDMA_CHAN_NUM + 1) +#define ZXDH_MPF_GDMA_MSIX_VEC_BASE 10 +#define ZXDH_MPF_GDMA_IRQ_MIN 0 +#define ZXDH_MPF_GDMA_IRQ_MAX 1 + +/* async irq:<0-5> comp irq:<6> gdma irq:<10-14> */ +#define ZXDH_ZF_MPF_IRQ_NUM_TOTAL 16 + +struct dh_mpf_irq_table { + struct dh_irq_pool *mpf_comp_pool; + struct dh_irq_pool *mpf_async_pool; + struct dh_irq_pool *mpf_gdma_pool; +}; + +struct dh_irq_range { + int32_t start; + int32_t size; +}; + +struct dh_irq *dh_mpf_async_irq_request(struct dh_core_dev *dev); +void dh_mpf_irq_table_destroy(struct dh_core_dev *dev); +int32_t dh_mpf_irq_table_create(struct dh_core_dev *dev); +int32_t dh_mpf_irq_table_init(struct dh_core_dev *dev); + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/zf_chan_ioctl.c b/src/net/drivers/net/ethernet/dinghai/zf_mpf/zf_chan_ioctl.c new file mode 100644 index 0000000..a6dbf1b --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/zf_chan_ioctl.c @@ -0,0 +1,284 @@ +#include +#include +#include +#include +#include +#include "zf_chan_ioctl.h" + +static dev_t dev; +static struct cdev c_dev; +static struct class *cl; + +#define BAR_IOCTL_CMD_NORMAL _IOW('a', 1, msg_entity_t) +#define BAR_IOCTL_CMD_SINGLE_DEV _IOW('a', 2, pci_res_st) +#define BAR_IOCTL_CMD_ALL_DEV _IOW('a', 3, pci_res_st) + +struct zxdh_bar_ioctl_dev +{ + uint16_t pcie_id; + uint64_t bar0_base_virt_addr; + uint64_t is_valid; +}ioctl_dev = {0}; + +struct zxdh_bar_ioctl_dev *zxdh_get_bar_ioctl_dev(void) +{ + return &ioctl_dev; +} + +int zxdh_init_bar_ioctl_dev(struct dh_core_dev *core_dev) +{ + struct zxdh_bar_ioctl_dev *dev = zxdh_get_bar_ioctl_dev(); + struct dh_en_mpf_dev *mpf_dev = dh_core_priv(core_dev); + + dev->pcie_id = mpf_dev->pcie_id; + dev->bar0_base_virt_addr = mpf_dev->pci_ioremap_addr; + dev->is_valid = 1; + return 0; +} + +int (*ioctl_bar_chan_func)(unsigned int cmd, unsigned long arg); + +int bar_chan_common_sync_send(unsigned int cmd, unsigned long arg) +{ + int ret = 0; + struct normal_msg_entity *user_msg = NULL; + struct zxdh_ioctl_send_paras *send_paras = NULL; + struct zxdh_pci_bar_msg in = {0}; + struct zxdh_msg_recviver_mem result = {0}; + struct zxdh_bar_ioctl_dev *dev = zxdh_get_bar_ioctl_dev(); + + /* 按照既定的申请内存*/ + user_msg = kmalloc(sizeof(struct normal_msg_entity), GFP_KERNEL); + if (NULL == user_msg) + { + LOG_ERR("malloc failed.\n"); + return -1; + } + /* 初始化并且按照约定的大小从用户态拷贝数据，保证不拷贝到脏数据*/ + memset(user_msg, 0, sizeof(struct normal_msg_entity)); + if (copy_from_user(user_msg, (msg_entity_t __user *)arg, sizeof(struct normal_msg_entity))) + { + user_msg->hdr.recv_msg_hdr.ioctl_state = IOCTRL_ERR_MSG_GET; + goto out; + } + + send_paras = &user_msg->hdr.send_msg_hdr; + if (send_paras->pload_len > BAR_CHAN_PLOAD_SIZE) + { + user_msg->hdr.recv_msg_hdr.bar_state = IOCTRL_ERR_MSG_GET; + goto out; + } + + in.virt_addr = dev->bar0_base_virt_addr + ZXDH_BAR1_CHAN_OFFSET; + in.payload_addr = user_msg->pload; + in.payload_len = send_paras->pload_len; + in.src = MSG_CHAN_END_PF; + in.dst = MSG_CHAN_END_RISC; + in.event_id = send_paras->event_id; + in.src_pcieid = dev->pcie_id; + + /* pload直接透传上去*/ + result.buffer_len = sizeof(user_msg->pload); + result.recv_buffer = (void *)user_msg->pload; + + ret = zxdh_bar_chan_sync_msg_send(&in, &result); + if (ret != 0) + { + LOG_ERR("pcie send msg failed, ret:%d.\n", ret); + } + + user_msg->hdr.recv_msg_hdr.bar_state = ret; + user_msg->hdr.recv_msg_hdr.ioctl_state = 0; +out: + ret = copy_to_user((int *)arg, user_msg, sizeof(*user_msg)); + if (0 != ret) + { + /* msg may not reply to user, but we can locate by demsg*/ + LOG_ERR("reply ioctl msg failed, ret: %d.\n", ret); + } + /* free the user_msg_data*/ + if (NULL != user_msg) + { + kfree(user_msg); + } + return 0; +} + +static int remove_recv_hdr(uint8_t *buffer, size_t len) +{ + if (len <= BAR_REV_HDR_LEN) + { + return -1; + } + memmove(buffer, buffer + BAR_REV_HDR_LEN, len - BAR_REV_HDR_LEN); + + return 0; +} + +static char temp_recv_buf[BAR_CHAN_PLOAD_SIZE + BAR_REV_HDR_LEN] = {0}; +int bar_chan_pci_res_get(unsigned int cmd, unsigned long arg, uint16_t mode) +{ + int ret = 0; + struct zxdh_mpf_query_bar_msg *entity = NULL; + struct zxdh_pci_query_hdr query_hdr = {0}; + struct zxdh_pci_bar_msg in = {0}; + struct zxdh_msg_recviver_mem result = {0}; + struct zxdh_bar_ioctl_dev *dev = zxdh_get_bar_ioctl_dev(); + + entity = kmalloc(sizeof(*entity), GFP_KERNEL); + if (NULL == entity) + { + LOG_ERR("malloc failed.\n"); + return -1; + } + memset(entity, 0,sizeof(*entity)); + if (copy_from_user(entity, (pci_res_st __user *)arg, sizeof(*entity))) + { + entity->ioctl_state = IOCTRL_ERR_MSG_GET; + goto out; + } + + query_hdr.mode = mode; + query_hdr.pcie_id = entity->pci_res_msg.pcie_id; + + in.virt_addr = dev->bar0_base_virt_addr + ZXDH_BAR1_CHAN_OFFSET; + in.payload_addr = &query_hdr; + in.payload_len = sizeof(query_hdr); + in.src = MSG_CHAN_END_PF; + in.dst = MSG_CHAN_END_RISC; + in.event_id = MODULE_PCIE_RES_QUERY; + in.src_pcieid = dev->pcie_id; + + result.recv_buffer = temp_recv_buf; + result.buffer_len = sizeof(temp_recv_buf); + + ret = zxdh_bar_chan_sync_msg_send(&in, &result); + if (ret != 0) + { + LOG_ERR("pcie send msg failed, ret:%d.\n", ret); + goto out; + } + + ret = remove_recv_hdr(result.recv_buffer, result.buffer_len); + memcpy(&entity->pci_res_msg.reply, result.recv_buffer, sizeof(struct zxdh_mpf_pci_res_list)); + + entity->ioctl_state = 0; +out: + entity->bar_state = ret; + ret = copy_to_user((int *)arg, entity, sizeof(*entity)); + if (0 != ret) + { + LOG_ERR("reply tp user failed.\n"); + } + if (NULL != entity) + { + kfree(entity); + } + return 0; +} + +int bar_chan_pci_res_get_single(unsigned int cmd, unsigned long arg) +{ + return bar_chan_pci_res_get(cmd, arg, PCI_QUERY_TYPE_SINGLE); +} + +int bar_chan_pci_res_get_all(unsigned int cmd, unsigned long arg) +{ + return bar_chan_pci_res_get(cmd, arg, PCI_QUERY_TYPE_ALL); +} + +struct bar_chan_func_sel +{ + unsigned int cmd; + int (*ioctl_bar_chan_func)(unsigned int cmd, unsigned long arg); +}ioctl_func_arr[] = { + {BAR_IOCTL_CMD_NORMAL, bar_chan_common_sync_send}, + {BAR_IOCTL_CMD_SINGLE_DEV, bar_chan_pci_res_get_single}, + {BAR_IOCTL_CMD_ALL_DEV, bar_chan_pci_res_get_all}, +}; + +static long bar_msg_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) +{ + int i, ret = 0; + int ioctl_func_nums = sizeof(ioctl_func_arr)/sizeof(ioctl_func_arr[0]); + + for (i = 0; i < ioctl_func_nums; i++) + { + if (ioctl_func_arr[i].cmd == cmd) + { + ret = ioctl_func_arr[i].ioctl_bar_chan_func(cmd, arg); + break; + } + } + return 0; +} + +static struct file_operations fops = +{ + .owner = THIS_MODULE, + .unlocked_ioctl = bar_msg_ioctl, +}; + +int bar_msg_ioctl_init(void) +{ + int ret = 0; + + if (alloc_chrdev_region(&dev, 0, 1, DEVICE_NAME) < 0) + { + return -EBUSY; + } + + if ((cl = class_create(THIS_MODULE, DEVICE_NAME)) == NULL) + { + unregister_chrdev_region(dev, 1); + return -ENOMEM; + } + + if (device_create(cl, NULL, dev, NULL, DEVICE_NAME) == NULL) + { + class_destroy(cl); + unregister_chrdev_region(dev, 1); + return -ENOMEM; + } + + cdev_init(&c_dev, &fops); + if (cdev_add(&c_dev, dev, 1) == -1) + { + device_destroy(cl, dev); + class_destroy(cl); + unregister_chrdev_region(dev, 1); + return -ENOMEM; + } + + LOG_INFO("Custom device registered\n"); + return ret; +} + +void bar_msg_ioctl_exit(void) +{ + cdev_del(&c_dev); + device_destroy(cl, dev); + class_destroy(cl); + unregister_chrdev_region(dev, 1); + LOG_INFO("Custom device unregistered\n"); +} + + +int zxdh_bar_ioctl_msg_mdl_init(struct dh_core_dev *core_dev) +{ + int ret = 0; + + zxdh_init_bar_ioctl_dev(core_dev); + ret = bar_msg_ioctl_init(); + if (ret != 0) + { + LOG_ERR("custom init failed, ret:%d.\n", ret); + return -1; + } + return 0; +} + +void zxdh_bar_ioctl_msg_mdl_exit(struct dh_core_dev *core_dev) +{ + bar_msg_ioctl_exit(); +} diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/zf_chan_ioctl.h b/src/net/drivers/net/ethernet/dinghai/zf_mpf/zf_chan_ioctl.h new file mode 100644 index 0000000..9c34b23 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/zf_chan_ioctl.h @@ -0,0 +1,100 @@ +#ifndef _ZXDH_MSG_CHAN_IOCTL_H_ +#define _ZXDH_MSG_CHAN_IOCTL_H_ + +#ifdef __cplusplus +extern "C" { +#endif +#include "zf_mpf.h" + +#define DEVICE_NAME "bar_ioctl_dev" +#define BAR_CHAN_SIZE (1024 * 2) +#define BAR_CHAN_PLOAD_SIZE (BAR_CHAN_SIZE - 12) +#define BAR_REV_HDR_LEN (4) +#define ZXDH_PF_DEV_NUM (40) + +#define PCI_QUERY_TYPE_SINGLE (1) +#define PCI_QUERY_TYPE_ALL (2) + +struct zxdh_ioctl_send_paras +{ + uint16_t pload_len; + uint16_t src; + uint16_t dst; + uint16_t event_id; +}; + +struct zxdh_ioctl_recv_paras +{ + int ioctl_state; //ioctrl级别返回值 + int bar_state; //bar通道接口级别返回值 +}; + +enum { + IOCTRL_OK, + IOCTRL_ERR_MALLOC, + IOCTRL_ERR_MSG_GET, +}; + +typedef struct normal_msg_entity +{ + union ioctl_ctrl_hdr //私有消息控制头 + { + struct zxdh_ioctl_send_paras send_msg_hdr; //普通消息发送头 + struct zxdh_ioctl_recv_paras recv_msg_hdr; //普通消息发送头 + }hdr; + uint8_t pload[BAR_CHAN_PLOAD_SIZE + BAR_REV_HDR_LEN]; +}msg_entity_t; + +struct zxdh_mpf_pci_res_item +{ + uint16_t device_id; + uint16_t pcie_id; + uint16_t bdf; + uint8_t link_state; + uint8_t dev_type; + uint16_t total_vfs; + uint16_t initial_vfs; + uint16_t num_vfs; + uint8_t vf_stride; + uint8_t first_vf_offset; + uint8_t pad[8]; //预留字段 +}; + +/* zf内核态和risc通信的约定结构体*/ +struct zxdh_mpf_pci_res_list +{ + uint16_t num; + uint16_t verno; //版本号 + int res; //0表示返回成功， 其他表示失败， 包括消息发送失败 + struct zxdh_mpf_pci_res_item pci_res_lis[ZXDH_PF_DEV_NUM]; +}; + +struct zxdh_mpf_query_pci_res_msg +{ + uint16_t pcie_id; + uint8_t dev_type; + uint8_t pad[5]; + struct zxdh_mpf_pci_res_list reply; +}; + +typedef struct zxdh_mpf_query_bar_msg +{ + int ioctl_state; + int bar_state; + struct zxdh_mpf_query_pci_res_msg pci_res_msg; +}pci_res_st; + +struct zxdh_pci_query_hdr +{ + uint16_t mode; + uint16_t pcie_id; +}; + +int zxdh_bar_ioctl_msg_mdl_init(struct dh_core_dev *core_dev); +void zxdh_bar_ioctl_msg_mdl_exit(struct dh_core_dev *core_dev); + +#ifdef __cplusplus +} +#endif + +#endif /* _ZXDH_MSG_CHAN_IOCTL_H_ */ diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/zf_events.c b/src/net/drivers/net/ethernet/dinghai/zf_mpf/zf_events.c new file mode 100755 index 0000000..f393001 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/zf_events.c @@ -0,0 +1,192 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "zf_events.h" +#include "../en_mpf.h" + +static int32_t zf_riscv_notifier(struct notifier_block *nb, unsigned long type, void *data); +static int32_t zf_pf_notifier(struct notifier_block *nb, unsigned long type, void *data); +static int32_t irq1_notifier(struct notifier_block *nb, unsigned long type, void *data); +static int32_t fuc_hotplug_failed_notifier(struct notifier_block *nb, unsigned long type, void *data); +static int32_t fuc_hotplug_finish_notifier(struct notifier_block *nb, unsigned long type, void *data); +static int32_t irq4_notifier(struct notifier_block *nb, unsigned long type, void *data); +int get_fuc_hp_ret(void); +int finish_flag = 0; + +static struct dh_nb zf_mpf_events[] = { + {.nb.notifier_call = zf_riscv_notifier, .event_type = DH_EVENT_TYPE_NOTIFY_RISC_TO_MPF}, + {.nb.notifier_call = zf_pf_notifier, .event_type = DH_EVENT_TYPE_NOTIFY_PF_TO_MPF}, + {.nb.notifier_call = irq1_notifier, .event_type = DH_EVENT_TYPE_NOTIFY_1}, + {.nb.notifier_call = fuc_hotplug_failed_notifier, .event_type = DH_EVENT_TYPE_NOTIFY_2}, + {.nb.notifier_call = fuc_hotplug_finish_notifier, .event_type = DH_EVENT_TYPE_NOTIFY_3}, + {.nb.notifier_call = irq4_notifier, .event_type = DH_EVENT_TYPE_NOTIFY_4} +}; + +static int32_t zf_riscv_notifier(struct notifier_block *nb, unsigned long type, void *data) +{ + struct dh_event_nb *event_nb = dh_nb_cof(nb, struct dh_event_nb, nb); + struct dh_core_dev *dh_dev = (struct dh_core_dev *)event_nb->ctx; + struct dh_en_mpf_dev *mpf_dev = dh_core_priv(dh_dev); + + LOG_INFO("is called, type=%ld\n", type); + zxdh_events_work_enqueue(dh_dev, &mpf_dev->dh_np_sdk_from_risc); + + return NOTIFY_OK; +} + +static int32_t zf_pf_notifier(struct notifier_block *nb, unsigned long type, void *data) +{ + struct dh_event_nb *event_nb = dh_nb_cof(nb, struct dh_event_nb, nb); + struct dh_core_dev *dh_dev = (struct dh_core_dev *)event_nb->ctx; + struct dh_en_mpf_dev *mpf_dev = dh_core_priv(dh_dev); + + LOG_INFO("is called, type=%ld\n", type); + zxdh_events_work_enqueue(dh_dev, &mpf_dev->dh_np_sdk_from_pf); + + return NOTIFY_OK; +} + +static int32_t irq1_notifier(struct notifier_block *nb, unsigned long type, void *data) +{ + struct dh_event_nb *event_nb = dh_nb_cof(nb, struct dh_event_nb, nb); + struct dh_core_dev *dh_dev = (struct dh_core_dev *)event_nb->ctx; + struct dh_en_mpf_dev *mpf_dev = dh_core_priv(dh_dev); + + LOG_INFO("is called, ep_bdf=0x%x, pcie_id=%d\n", mpf_dev->ep_bdf, mpf_dev->pcie_id); + + return zf_hdma_wr_handler((void *)dh_dev->zf_ep->dpu_ep_array[0]); +} + +static int32_t fuc_hotplug_failed_notifier(struct notifier_block *nb, unsigned long type, void *data) +{ + finish_flag = FUC_HP_RET_FAILED; + LOG_ERR("hotplug failed\n"); + return NOTIFY_OK; +} +static int32_t fuc_hotplug_finish_notifier(struct notifier_block *nb, unsigned long type, void *data) +{ + finish_flag = FUC_HP_RET_FINISH; + LOG_INFO("hotplug success\n"); + return NOTIFY_OK; +} + +static int32_t irq4_notifier(struct notifier_block *nb, unsigned long type, void *data) +{ + struct dh_event_nb *event_nb = dh_nb_cof(nb, struct dh_event_nb, nb); + struct dh_core_dev *dh_dev = (struct dh_core_dev *)event_nb->ctx; + struct dh_en_mpf_dev *mpf_dev = dh_core_priv(dh_dev); + + LOG_INFO("is called, ep_bdf=0x%x, pcie_id=%d\n", mpf_dev->ep_bdf, mpf_dev->pcie_id); + + return NOTIFY_OK; +} + +static void zf_np_sdk_handler_from_risc(struct work_struct *p_work) +{ + struct dh_en_mpf_dev *mpf_dev = container_of(p_work, struct dh_en_mpf_dev, dh_np_sdk_from_risc); + + LOG_INFO("is called\n"); + zxdh_bar_irq_recv(MSG_CHAN_END_RISC, MSG_CHAN_END_MPF, mpf_dev->pci_ioremap_addr + ZXDH_BAR1_CHAN_OFFSET, NULL); + return; +} + +static void zf_np_sdk_handler_from_pf(struct work_struct *p_work) +{ + struct dh_en_mpf_dev *mpf_dev = container_of(p_work, struct dh_en_mpf_dev, dh_np_sdk_from_pf); + + LOG_INFO("is called\n"); + zxdh_bar_irq_recv(MSG_CHAN_END_PF, MSG_CHAN_END_MPF, mpf_dev->pci_ioremap_addr + ZXDH_BAR2_CHAN_OFFSET, NULL); + return; +} + +void zxdh_zf_events_start(struct dh_core_dev *dev) +{ + struct dh_events *events = dev->events; + int32_t i = 0; + int32_t err = 0; + + for (i = 0; i < ARRAY_SIZE(zf_mpf_events); i++) + { + events->notifiers[i].nb = zf_mpf_events[i]; + events->notifiers[i].ctx = dev; + err = dh_eq_notifier_register(&dev->eq_table, &events->notifiers[i].nb); + if (err != 0) + { + LOG_ERR("i: %d, err: %d.\n", i, err); + } + } +} + +void dh_zf_events_stop(struct dh_core_dev *dev) +{ + struct dh_events *events = dev->events; + int32_t i = 0; + + for (i = ARRAY_SIZE(zf_mpf_events) - 1; i >= 0 ; i--) + { + dh_eq_notifier_unregister(&dev->eq_table, &events->notifiers[i].nb); + } + + zxdh_events_cleanup(dev); +} + +int32_t dh_zf_mpf_events_init(struct dh_core_dev *dev) +{ + struct dh_events *events = NULL; + struct dh_en_mpf_dev *mpf_dev = dh_core_priv(dev); + int32_t ret = 0; + + events = kzalloc((sizeof(*events) + ARRAY_SIZE(zf_mpf_events) * sizeof(struct dh_event_nb)), GFP_KERNEL); + if (unlikely(events == NULL)) + { + LOG_ERR("events kzalloc failed: %p\n", events); + ret = -ENOMEM; + goto err_events_kzalloc; + } + + events->evt_num = ARRAY_SIZE(zf_mpf_events); + events->dev = dev; + dev->events = events; + events->wq = create_singlethread_workqueue("dh_zf_mpf_events"); + if (!events->wq) + { + LOG_ERR("events->wq create_singlethread_workqueue failed: %p\n", events->wq); + ret = -ENOMEM; + goto err_create_wq; + } + + INIT_WORK(&mpf_dev->dh_np_sdk_from_risc, zf_np_sdk_handler_from_risc); + INIT_WORK(&mpf_dev->dh_np_sdk_from_pf, zf_np_sdk_handler_from_pf); + + zxdh_zf_events_start(dev); + + return 0; + +err_create_wq: + kfree(events); +err_events_kzalloc: + return ret; +} + +void dh_zf_mpf_events_uninit(struct dh_core_dev *dev) +{ + return dh_zf_events_stop(dev); +} + +void reset_fuc_hp_ret(void) +{ + finish_flag = 0; + return; +} + +int get_fuc_hp_ret(void) +{ + return finish_flag; +} \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/zf_events.h b/src/net/drivers/net/ethernet/dinghai/zf_mpf/zf_events.h new file mode 100755 index 0000000..5ba057b --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/zf_events.h @@ -0,0 +1,24 @@ +#ifndef __ZXDH_ZF_MPF_EVENTS_H__ +#define __ZXDH_ZF_MPF_EVENTS_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include "epc/pcie-zte-zf-epc.h" +#include "fuc_hotplug/fuc_hotplug_commom.h" + +int32_t dh_zf_mpf_events_init(struct dh_core_dev *dev); +void zxdh_zf_events_start(struct dh_core_dev *dev); +int32_t dh_zf_mpf_events_init(struct dh_core_dev *dev); +void dh_zf_events_stop(struct dh_core_dev *dev); +void dh_zf_mpf_events_uninit(struct dh_core_dev *dev); +int zf_hdma_wr_handler(void *data); +int zf_hdma_rd_handler(void *data); + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/zf_mpf.c b/src/net/drivers/net/ethernet/dinghai/zf_mpf/zf_mpf.c new file mode 100755 index 0000000..8cbe1e4 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/zf_mpf.c @@ -0,0 +1,437 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "zf_events.h" +#include "eq.h" +#include "irq.h" +#include "cfg_sf.h" +#include "zf_mpf.h" +#include "gdma.h" + +#ifdef PCIE_ZF_EPC_OPEN +#include "epc/pcie-zte-zf-epc.h" +#endif + +#ifdef DRIVER_VERSION_VAL + #define DRV_VERSION DRIVER_VERSION_VAL +#else + #define DRV_VERSION "1.0-1" +#endif + +MODULE_LICENSE("Dual BSD/GPL"); +MODULE_VERSION(DRV_VERSION); + +uint32_t zf_dh_debug_mask; +module_param_named(debug_mask, zf_dh_debug_mask, uint, 0644); +MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0"); + +extern struct devlink_ops dh_mpf_devlink_ops; +extern struct dh_core_devlink_ops dh_mpf_core_devlink_ops; + +extern int zxdh_host_reset_driver_init(struct dh_core_dev *core_dev); +extern void zxdh_host_reset_driver_exit(struct dh_core_dev *core_dev); +extern int zxdh_host_fuc_hotplug_driver_init(void); +extern void zxdh_host_fuc_hotplug_driver_exit(void); +extern int zf_reset_finish_flag_init(struct dh_core_dev *dh_dev, unsigned long ep_mpf_paddr); +extern void zf_reset_finish_flag_exit(void); +extern int zxdh_bar_ioctl_msg_mdl_init(struct dh_core_dev *core_dev); +extern void zxdh_bar_ioctl_msg_mdl_exit(struct dh_core_dev *core_dev); + +static int32_t dh_zf_mpf_pci_init(struct dh_core_dev *dev) +{ + int32_t ret = 0; + struct dh_en_mpf_dev *mpf_dev = NULL; + + pci_set_drvdata(dev->pdev, dev); + + ret = pci_enable_device(dev->pdev); + if (ret) + { + dev_err(dev->device, "pci_enable_device failed: %d\n", ret); + return -ENOMEM; + } + + ret = dma_set_mask_and_coherent(dev->device, DMA_BIT_MASK(64)); + if (ret != 0) + { + ret = dma_set_mask_and_coherent(dev->device, DMA_BIT_MASK(32)); + if (ret != 0) + { + dev_err(dev->device, "dma_set_mask_and_coherent failed: %d\n", ret); + goto err_pci; + } + } + + ret = pci_request_selected_regions(dev->pdev, pci_select_bars(dev->pdev, IORESOURCE_MEM), "dh-mpf"); + if (ret != 0) + { + dev_err(dev->device, "pci_request_selected_regions failed: %d\n", ret); + goto err_pci; + } + + pci_enable_pcie_error_reporting(dev->pdev); + pci_set_master(dev->pdev); + ret = pci_save_state(dev->pdev); + if (ret != 0) + { + dev_err(dev->device, "pci_save_state failed: %d\n", ret); + goto err_pci_save_state; + } + + mpf_dev = dh_core_priv(dev); + mpf_dev->pci_ioremap_addr = (uint64_t)ioremap(pci_resource_start(dev->pdev, 0), pci_resource_len(dev->pdev, 0)); + LOG_INFO("pci_ioremap_addr=0x%llx, ioremap(0x%llx, 0x%llx)\n", mpf_dev->pci_ioremap_addr, pci_resource_start(dev->pdev, 0), pci_resource_len(dev->pdev, 0)); + if (mpf_dev->pci_ioremap_addr == 0) + { + ret = -1; + LOG_ERR("ioremap(0x%llx, 0x%llx) failed\n", pci_resource_start(dev->pdev, 0), pci_resource_len(dev->pdev, 0)); + goto err_pci_save_state; + } + + return 0; + +err_pci_save_state: + pci_disable_pcie_error_reporting(dev->pdev); + pci_release_selected_regions(dev->pdev, pci_select_bars(dev->pdev, IORESOURCE_MEM)); +err_pci: + pci_disable_device(dev->pdev); + return ret; +} + +static const struct pci_device_id dh_zf_mpf_pci_table[] = { + { PCI_DEVICE(ZXDH_MPF_VENDOR_ID, ZXDH_MPF_DEVICE_ID), 0 }, + { 0, } +}; + +MODULE_DEVICE_TABLE(pci, dh_zf_mpf_pci_table); + +void dh_zf_mpf_pci_close(struct dh_core_dev *dev) +{ + struct dh_en_mpf_dev *mpf_dev = NULL; + + mpf_dev = dh_core_priv(dev); + iounmap((void __iomem *)mpf_dev->pci_ioremap_addr); + pci_disable_pcie_error_reporting(dev->pdev); + pci_release_selected_regions(dev->pdev, pci_select_bars(dev->pdev, IORESOURCE_MEM)); + pci_disable_device(dev->pdev); + + return; +} + +int32_t dh_zf_mpf_pcie_id_get(struct dh_core_dev *dh_dev) +{ + u8 pos = 0; + uint8_t type = 0; + uint16_t padding = 0; + struct dh_en_mpf_dev *mpf_dev = dh_core_priv(dh_dev); + struct pci_dev *pdev = dh_dev->pdev; + + for (pos = pci_find_capability(pdev, PCI_CAP_ID_VNDR); pos > 0; pos = pci_find_next_capability(pdev, pos, PCI_CAP_ID_VNDR)) + { + pci_read_config_byte(pdev, pos + offsetof(struct zxdh_pf_pci_cap, cfg_type), &type); + + if (type == ZXDH_PCI_CAP_PCI_CFG) + { + pci_read_config_word(pdev, pos + offsetof(struct zxdh_pf_pci_cap, padding[0]), &padding); + mpf_dev->pcie_id = padding; + LOG_INFO("pf_dev->pcie_id: 0x%x\n", mpf_dev->pcie_id); + return 0; + } + } + return -1; +} + +static int32_t dh_zf_mpf_probe(struct pci_dev *pdev, const struct pci_device_id *id) +{ + struct dh_core_dev *dh_dev = NULL; + struct devlink *devlink = NULL; + int32_t err = 0; + + LOG_INFO("mpf driver start to probe\n"); + + devlink = zxdh_devlink_alloc(&pdev->dev, &dh_mpf_devlink_ops, sizeof(struct dh_en_mpf_dev)); + if (devlink == NULL) + { + dev_err(&pdev->dev, "devlink alloc failed\n"); + return -ENOMEM; + } + + dh_dev = devlink_priv(devlink); + dh_dev->device = &pdev->dev; + dh_dev->pdev = pdev; + dh_dev->devlink_ops = &dh_mpf_core_devlink_ops; + + err = dh_zf_mpf_pci_init(dh_dev); + if (err != 0) + { + dev_err(&pdev->dev, "%s failed: %d\n", __func__, err); + goto err_devlink_cleanup; + } + +#ifdef CONFIG_ZF_GDMA + err = dh_zf_mpf_gdma_init(dh_dev); + if (err != 0) + { + dh_err(dh_dev, "Failed to initialize gdma module\n"); + goto err_gdma_init; + } +#endif + + err = dh_zf_mpf_pcie_id_get(dh_dev); + if (err != 0) + { + dev_err(&pdev->dev, "dh_pf_pcie_id_get failed: %d\n", err); + goto err_pci; + } + + err = dh_mpf_irq_table_init(dh_dev); // dh_dev->irq_table.priv = kvzalloc(sizeof(struct dh_mpf_irq_table), GFP_KERNEL); + if (err != 0) + { + dh_err(dh_dev, "Failed to alloc IRQs\n"); + goto err_pci; + } + + err = dh_mpf_eq_table_init(dh_dev); + if (err != 0) + { + dh_err(dh_dev, "Failed to alloc IRQs\n"); + goto err_eq_table_init; + } + + err = dh_mpf_irq_table_create(dh_dev); + if (err != 0) + { + dh_err(dh_dev, "Failed to alloc IRQs\n"); + goto err_irq_table_create; + } + + err = dh_mpf_eq_table_create(dh_dev); + if (err != 0) + { + dh_err(dh_dev, "Failed to alloc EQs\n"); + goto err_eq_table_create; + } + +#ifdef PCIE_ZF_EPC_OPEN + err = pcie_zte_zf_epc_init(dh_dev, id); + if (err != 0) + { + dh_err(dh_dev, "failed to initialize epc\n"); + goto err_epc_init; + } +#endif + +#ifdef PCIE_ZF_RST_FINISH_FLAG_OPEN + err = zf_reset_finish_flag_init(dh_dev, dh_dev->zf_ep->mpf_paddr); + if (err != 0) + { + dh_err(dh_dev, "failed to initialize zf_reset_finish_flag_init\n"); + goto err_zf_reset_finish_flag_init_cleanup; + } +#endif + + err = dh_zf_mpf_events_init(dh_dev); + if (err != 0) + { + dh_err(dh_dev, "failed to initialize events\n"); + goto err_events_init_cleanup; + } + + err = zxdh_host_reset_driver_init(dh_dev); + if (err != 0) + { + LOG_ERR("zxdh_host_reset_driver_init failed: %d\n", err); + goto err_zf_host_reset; + } + + err = zxdh_bar_ioctl_msg_mdl_init(dh_dev); + if (err != 0) + { + LOG_ERR("zxdh_bar_ioctl_msg_mdl_init failed: %d\n", err); + goto err_zf_host_reset; + } + +#ifdef HAVE_DEVLINK_REGISTER_GET_1_PARAMS + zxdh_devlink_register(devlink); +#else + zxdh_devlink_register(devlink, &pdev->dev); +#endif + + LOG_INFO("mpf driver probe completed\n"); + return 0; + +err_zf_host_reset: + zxdh_host_reset_driver_exit(dh_dev); +err_events_init_cleanup: +#ifdef PCIE_ZF_RST_FINISH_FLAG_OPEN + zf_reset_finish_flag_exit(); +err_zf_reset_finish_flag_init_cleanup: +#endif +#ifdef PCIE_ZF_EPC_OPEN + pcie_zte_zf_epc_free(dh_dev); +err_epc_init: +#endif + dh_mpf_eq_table_destroy(dh_dev); +err_eq_table_create: + dh_mpf_irq_table_destroy(dh_dev); +err_irq_table_create: + dh_eq_table_cleanup(dh_dev); +err_eq_table_init: + dh_irq_table_cleanup(dh_dev); +err_pci: +#ifdef CONFIG_ZF_GDMA + dh_zf_mpf_gdma_uninit(dh_dev); +err_gdma_init: +#endif + dh_zf_mpf_pci_close(dh_dev); +err_devlink_cleanup: + zxdh_devlink_free(devlink); + return err; +} + +static void dh_zf_mpf_remove(struct pci_dev *pdev) +{ + struct dh_core_dev *dh_dev = pci_get_drvdata(pdev); + struct devlink *devlink = priv_to_devlink(dh_dev); + + LOG_INFO("mpf driver start to remove"); + +#ifdef PCIE_ZF_RST_FINISH_FLAG_OPEN + zf_reset_finish_flag_exit(); +#endif + zxdh_devlink_unregister(devlink); +#ifdef PCIE_ZF_EPC_OPEN + pcie_zte_zf_epc_free(dh_dev); +#endif + zxdh_bar_ioctl_msg_mdl_exit(dh_dev); + zxdh_host_reset_driver_exit(dh_dev); + dh_zf_mpf_events_uninit(dh_dev); + dh_mpf_eq_table_destroy(dh_dev); + dh_mpf_irq_table_destroy(dh_dev); + dh_eq_table_cleanup(dh_dev); + dh_irq_table_cleanup(dh_dev); +#ifdef CONFIG_ZF_GDMA + dh_zf_mpf_gdma_uninit(dh_dev); +#endif + dh_zf_mpf_pci_close(dh_dev); + zxdh_devlink_free(devlink); + + pci_set_drvdata(pdev, NULL); + + LOG_INFO("mpf driver remove completed\n"); +} + +static int32_t dh_zf_mpf_suspend(struct pci_dev *pdev, pm_message_t state) +{ + + return 0; +} + +static int32_t dh_zf_mpf_resume(struct pci_dev *pdev) +{ + + return 0; +} + +static void dh_zf_mpf_shutdown(struct pci_dev *pdev) +{ + dh_zf_mpf_remove(pdev); +} + +static pci_ers_result_t dh_pci_err_detected(struct pci_dev *pdev, + pci_channel_state_t state) +{ + return PCI_ERS_RESULT_NONE; +} + +static pci_ers_result_t dh_zf_mpf_pci_slot_reset(struct pci_dev *pdev) +{ + return PCI_ERS_RESULT_NONE; +} + +static void dh_zf_mpf_pci_resume(struct pci_dev *pdev) +{ + +} + +static const struct pci_error_handlers dh_zf_mpf_err_handler = { + .error_detected = dh_pci_err_detected, + .slot_reset = dh_zf_mpf_pci_slot_reset, + .resume = dh_zf_mpf_pci_resume +}; + +static struct pci_driver zf_dh_mpf_driver = { + .name = KBUILD_MODNAME, + .id_table = dh_zf_mpf_pci_table, + .probe = dh_zf_mpf_probe, + .remove = dh_zf_mpf_remove, + .suspend = dh_zf_mpf_suspend, + .resume = dh_zf_mpf_resume, + .shutdown = dh_zf_mpf_shutdown, + .err_handler = &dh_zf_mpf_err_handler, +}; + +static int32_t __init init(void) +{ + int32_t err = 0; + + err = pci_register_driver(&zf_dh_mpf_driver); + if (err != 0) + { + LOG_ERR("pci_register_driver failed: %d\n", err); + return err; + } + +#ifdef CONFIG_ZXDH_SF + err = zxdh_mpf_sf_driver_register(); + if (err != 0) + { + LOG_ERR("zxdh_en_sf_driver_register failed: %d\n", err); + goto err_sf; + } +#endif + + err = zxdh_host_fuc_hotplug_driver_init(); + if (err != 0){ + LOG_ERR("fuc_hotplug_driver_init failed: %d\n", err); + goto err_fuc_hotplug; + } + LOG_INFO("zxdh_mpf driver init success\n"); + + return 0; + +err_fuc_hotplug: + +#ifdef CONFIG_ZXDH_SF +err_sf: + pci_unregister_driver(&zf_dh_mpf_driver); +#endif + + return err; +} + +static void __exit cleanup(void) +{ +#ifdef CONFIG_ZXDH_SF + zxdh_mpf_sf_driver_uregister(); +#endif + zxdh_host_fuc_hotplug_driver_exit(); + pci_unregister_driver(&zf_dh_mpf_driver); + +#ifdef PCIE_ZF_RST_FINISH_FLAG_OPEN + zf_reset_finish_flag_exit(); +#endif + + LOG_INFO("zxdh_mpf driver remove success\n"); +} + +module_init(init); +module_exit(cleanup); diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/zf_mpf.h b/src/net/drivers/net/ethernet/dinghai/zf_mpf/zf_mpf.h new file mode 100755 index 0000000..34cd934 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/zf_mpf.h @@ -0,0 +1,36 @@ +#ifndef __ZXDH_ZF_MPF_H__ +#define __ZXDH_ZF_MPF_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include "gdma.h" + +#define ZXDH_MPF_VENDOR_ID 0x1cf2 +#define ZXDH_MPF_DEVICE_ID 0x8044 + +#define ZXDH_BAR1_CHAN_OFFSET 0x2000//0x7801000 +#define ZXDH_BAR2_CHAN_OFFSET 0x3000//0x7802000 +#define PCIE_ZF_RST_FINISH_FLAG_OPEN 1 + +struct dh_en_mpf_dev { + uint16_t ep_bdf; + uint16_t pcie_id; + uint16_t vport; + + uint64_t pci_ioremap_addr; + + struct work_struct dh_np_sdk_from_risc; + struct work_struct dh_np_sdk_from_pf; + + struct zf_gdma_dev *gdev; +}; + +#ifdef __cplusplus +} +#endif + +#endif /* __ZXDH_EN_MPF_H__ */ \ No newline at end of file diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/zf_reset_finish_flag.c b/src/net/drivers/net/ethernet/dinghai/zf_mpf/zf_reset_finish_flag.c new file mode 100755 index 0000000..0bd473a --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/zf_reset_finish_flag.c @@ -0,0 +1,95 @@ +#include +#include +#include +#include +#include +#include +#include +#include "epc/pcie-zte-zf-epc.h" + +#define FLAG_ID 0x1 +#define SYSFS_ZF_RESET_FINISH_FLAG_DIR "zf_reset_finish_flag" +#define ZF_RESET_FINISH_FLAG_MODE 0664 +#define ZF_RESET_FINISH_FLAG flag +#define NOTIFY_OFFEST (PCIE_DPU_MPF_CSR_ADDR(PCIE_DPU_EP_CSR_SIZE * PCIE_DPU_EP_NUM) + 4) +#define NOTIFY_VALUE (1 << 1) +#define NOTIFY_MASK (1 << 1) + +static char flag_data[PAGE_SIZE]; +static struct kobject *zf_reset_finish_flag_kobj = NULL; +unsigned long op_paddr = 0; + +static int notify_host_zf_reset_finished(void) +{ + int ret = 0; + + ret = cfg_phy_rmw(op_paddr + NOTIFY_OFFEST, NOTIFY_VALUE, NOTIFY_MASK); + + if (ret) { + printk(KERN_ERR "notify_host_zf_reset_finished, cfg_phy_rmw write failed!\n"); + } + + return ret; +} + +static ssize_t read_flag(struct kobject *kobj, struct kobj_attribute *attr, + char *buf) +{ + return snprintf(buf, PAGE_SIZE, "%s", flag_data); +} + +static ssize_t write_flag(struct kobject *kobj, struct kobj_attribute *attr, + const char *buf, size_t count) +{ + int size = 0; + unsigned long flag = 0; + char *end = NULL; + + size = snprintf(flag_data, PAGE_SIZE, "%s", buf); + flag = simple_strtoul(flag_data, &end, 16); + if (FLAG_ID == flag) + { + notify_host_zf_reset_finished(); + } + + return size; +} + +static struct kobj_attribute flag_attribute = + __ATTR(ZF_RESET_FINISH_FLAG, ZF_RESET_FINISH_FLAG_MODE, read_flag, write_flag); + +int zf_reset_finish_flag_init(struct dh_core_dev *dh_dev, unsigned long ep_mpf_paddr) +{ + int ret = 0; + + op_paddr = ep_mpf_paddr; + if (zf_reset_finish_flag_kobj == NULL) + { + zf_reset_finish_flag_kobj = kobject_create_and_add(SYSFS_ZF_RESET_FINISH_FLAG_DIR, kernel_kobj); + if (!zf_reset_finish_flag_kobj) + return -ENOMEM; + + ret = sysfs_create_file(zf_reset_finish_flag_kobj, &flag_attribute.attr); + if (ret) + { + kobject_put(zf_reset_finish_flag_kobj); + zf_reset_finish_flag_kobj = NULL; + } + } + else + { + dh_err(dh_dev, "zf_reset_finish_flag_kobj is not NULL!, can't create zf_reset_finish_flag!\n"); + ret = -EINVAL; + } + + return ret; +} + +void zf_reset_finish_flag_exit(void) +{ + if (zf_reset_finish_flag_kobj != NULL) { + sysfs_remove_file(zf_reset_finish_flag_kobj, &flag_attribute.attr); + kobject_put(zf_reset_finish_flag_kobj); + zf_reset_finish_flag_kobj = NULL; + } +} diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/zxdh_reset_zf.c b/src/net/drivers/net/ethernet/dinghai/zf_mpf/zxdh_reset_zf.c new file mode 100755 index 0000000..d8f8082 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/zxdh_reset_zf.c @@ -0,0 +1,242 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include "zf_mpf.h" + +#define ZXDH_SYSFS_DIR "zxdh_host_reset" +#define ZXDH_SYSFS_FILE_EP_CHECK_REGISTER "ep_check_register" +#define ZXDH_SYSFS_FILE_EP_RESET_INFO "ep_reset_info" + + +struct zxdh_reset_dev +{ + uint16_t pcie_id; + uint64_t bar0_base_virt_addr; + uint64_t is_valid; +}reset_dev = {0}; + +struct zxdh_reset_dev *zxdh_get_reset_dev(void) +{ + return &reset_dev; +} + +int zxdh_init_reset_dev(struct dh_core_dev *core_dev) +{ + struct zxdh_reset_dev *dev = zxdh_get_reset_dev(); + + struct dh_en_mpf_dev *mpf_dev = dh_core_priv(core_dev); + dev->bar0_base_virt_addr = mpf_dev->pci_ioremap_addr; + dev->is_valid = 1; + dev->pcie_id = mpf_dev->pcie_id; + return 0; +} + + +extern int zxdh_bar_chan_sync_msg_send(struct zxdh_pci_bar_msg *in, struct zxdh_msg_recviver_mem *result); +extern int zxdh_bar_chan_msg_recv_register(uint8_t event_id, zxdh_bar_chan_msg_recv_callback callback); +extern int zxdh_bar_chan_msg_recv_unregister(uint8_t event_id); + +enum e_reset_event +{ + EV_HOST_RESET = 0, + EV_ZF_RESET = 1, + EV_DINGHAI_RESET = 2, + EV_ZXDH_RESET_TEST = 3, + EV_MAX_RESET +}; + + +struct host_reset_ev_info +{ + int ep_no; +}; + +struct zxdh_reset_priv { + enum e_reset_event e_reset_event; + union + { + struct host_reset_ev_info host_reset_ev; + } ev_info; + struct work_struct work; +}; + +/* 本模块在ZF中insmod + +使用sysfs接口，主目录：/sys/zxdh_host_reset/，包含下述文件 +1、ep_check_register +功能：业务通知risc-v需要进行检测的ep +参数：16进制的字符串。例子：0xffffffff +字符串转为4个字节长度的数值，每个bit位代表一个ep。bit0~bit31代表ep0~ep31。 +当bit位设置为1时，表示该ep需要进行复位检测上报。 +当bit位设置为0时，表示该ep不需要进行复位检测上报。 +用户操作： +1）向 ep_check_register 写入 value + 含义：通知risc-v需要进行检测的ep +2）读取ep_check_register + 返回value，表示当前监测的ep +2、ep_reset_info +功能：ep复位后，业务通过这个文件查询 +参数：16进制的字符串。例子：0xffffffff +字符串转为4个字节长度的数值，每个bit位代表一个ep。bit0~bit31代表ep0~ep31。 +当bit位为1时，表示该ep发生了reset。 +当bit位为0时，表示该ep没有发生reset。 +用户操作： +1）读取ep_reset_info + 返回value，获取发生reset的ep信息 +2）向 ep_reset_info 写入 value + 将发生reset的ep信息清0 +*/ +unsigned int ep_check_register = 0; +unsigned int ep_reset_info = 0; + +struct kobject *kobj_zxdh_host_reset = NULL; + + +/*该函数被调用在sysfs文件被读时*/ +static ssize_t sysfs_show_ep_check_register(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + return sprintf(buf, "0x%08x", ep_check_register); +} + +/* 该函数被调用在sysfs文件被写时*/ +static ssize_t sysfs_store_ep_check_register(struct kobject *kobj, + struct kobj_attribute *attr,const char *buf, size_t count) +{ + uint16_t ret = 0; + + struct zxdh_pci_bar_msg in = {0}; + struct zxdh_msg_recviver_mem result = {0}; + uint8_t recv_buffer[20] = {0}; + uint16_t recv_buff_len = 20; + struct zxdh_reset_dev *dev = zxdh_get_reset_dev(); + sscanf(buf,"0x%x",&ep_check_register); + + in.virt_addr = dev->bar0_base_virt_addr + ZXDH_BAR1_CHAN_OFFSET; + in.payload_addr = &ep_check_register; + in.payload_len = sizeof(ep_check_register); + in.src = MSG_CHAN_END_PF;//MSG_CHAN_END_MPF; + in.dst = MSG_CHAN_END_RISC; + in.event_id = MODULE_RESET_MSG;/* 事件号 */ + in.src_pcieid = dev->pcie_id; + + result.recv_buffer = recv_buffer; + result.buffer_len = recv_buff_len; + + ret = zxdh_bar_chan_sync_msg_send(&in, &result); + if (ret) + { + pr_err(" '%s' zxdh_bar_chan_sync_msg_send failed.\n", __FUNCTION__); + } + return count; +} + +/*该函数被调用在sysfs文件被读时*/ +static ssize_t sysfs_show_ep_reset_info(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + return sprintf(buf, "0x%08x", ep_reset_info); +} + +/* 该函数被调用在sysfs文件被写时*/ +static ssize_t sysfs_store_ep_reset_info(struct kobject *kobj, + struct kobj_attribute *attr,const char *buf, size_t count) +{ + sscanf(buf,"0x%x",&ep_reset_info); + return count; +} + +/*使用__ATTR宏初始化zxdh_host_reset_attr结构体，该宏定义在include/linux/sysfs.h*/ +struct kobj_attribute zxdh_host_reset_attr_ep_check_register = __ATTR(ep_check_register, 0664, sysfs_show_ep_check_register, sysfs_store_ep_check_register); +struct kobj_attribute zxdh_host_reset_attr_ep_reset_info = __ATTR(ep_reset_info, 0664, sysfs_show_ep_reset_info, sysfs_store_ep_reset_info); + +int32_t zxdh_reset_zf_rec_risc(void *pay_load, uint16_t len, void *reps_buffer, uint16_t *reps_len, void *dev) +{ + struct zxdh_reset_priv *priv = NULL; + uint32_t ep_no = 0; + uint32_t ep_reset_info_tmp = ep_reset_info; + + if (pay_load && len && reps_buffer && reps_len) + { + pr_info("%s: para check ok ok ok.(%p, %x, %p, %p)\n", __func__, pay_load, len, reps_buffer, reps_len); + } + else + { + pr_err("%s: para error.(%p, %x, %p, %p)\n", __func__, pay_load, len, reps_buffer, reps_len); + return (uint16_t)-1; + } + + + priv = pay_load; + ep_no = priv->ev_info.host_reset_ev.ep_no; + + pr_info(" %s: received msg from RISC-V: event_id[%d] len 0x%x, ep_no=%u\n", __FUNCTION__, MODULE_RESET_MSG, len, ep_no); + + ep_reset_info |= 1 << ep_no; + pr_info(" %s: ep_reset_info 0x%08x -> 0x%08x\n", __FUNCTION__, ep_reset_info_tmp, ep_reset_info); + + return 0; +} + + +/*模块初始化函数*/ +int zxdh_host_reset_driver_init(struct dh_core_dev *core_dev) +{ + int32_t ret = 0; + /*创建一个目录在/sys下 */ + kobj_zxdh_host_reset = kobject_create_and_add(ZXDH_SYSFS_DIR,NULL); + + zxdh_init_reset_dev(core_dev); + + /*在ZXDH_SYSFS_DIR目录下创建文件*/ + if(sysfs_create_file(kobj_zxdh_host_reset,&zxdh_host_reset_attr_ep_check_register.attr)){ + pr_err(" 'ep_check_register' sysfs create failed.\n"); + goto error_sysfs; + } + + if(sysfs_create_file(kobj_zxdh_host_reset,&zxdh_host_reset_attr_ep_reset_info.attr)){ + pr_err(" 'ep_reset_info' sysfs create failed.\n"); + goto error_sysfs; + } + + ret = zxdh_bar_chan_msg_recv_register(MODULE_RESET_MSG, zxdh_reset_zf_rec_risc); + if (ret != 0) + { + pr_err(" zxdh_bar_chan_msg_recv_register: event_id[%d] register failed: %d\n", MODULE_RESET_MSG, ret); + //return ret; + } + + pr_info(" zxdh host reset module init ok.\n"); + return 0; + +error_sysfs: + zxdh_bar_chan_msg_recv_unregister(MODULE_RESET_MSG); + sysfs_remove_file(kernel_kobj, &zxdh_host_reset_attr_ep_reset_info.attr); + sysfs_remove_file(kernel_kobj, &zxdh_host_reset_attr_ep_check_register.attr); + kobject_put(kobj_zxdh_host_reset); + return -1; + +} + +/*模块退出函数*/ +void zxdh_host_reset_driver_exit(struct dh_core_dev *core_dev) +{ + zxdh_bar_chan_msg_recv_unregister(MODULE_RESET_MSG); + sysfs_remove_file(kernel_kobj, &zxdh_host_reset_attr_ep_reset_info.attr); + sysfs_remove_file(kernel_kobj, &zxdh_host_reset_attr_ep_check_register.attr); + kobject_put(kobj_zxdh_host_reset); + pr_info(" zxdh host reset module remove ok.\n"); +} +#if 0 +module_init(zxdh_host_reset_driver_init); +module_exit(zxdh_host_reset_driver_exit); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("zxdh"); +MODULE_DESCRIPTION("for zxdh host reset"); +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/zxdh_tools/zxdh_tools_ioctl.c b/src/net/drivers/net/ethernet/dinghai/zxdh_tools/zxdh_tools_ioctl.c new file mode 100755 index 0000000..ac88256 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/zxdh_tools/zxdh_tools_ioctl.c @@ -0,0 +1,476 @@ +#include +#include +#include "../en_aux.h" +#include "../cmd/msg_chan_priv.h" +#include "../en_aux/priv_queue.h" +#include "zxdh_tools_ioctl.h" + + +uint32_t user_event_pid = 0; + +/* Started by AICoder, pid:x7951lc26423ce61419e0a0a502a9b6cc494ddd1 */ +int32_t zxdh_tools_mark_event_info(struct net_device *netdev, struct ifreq *ifr) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + struct zxdh_tools_msg *msg = NULL; + struct zxdh_tools_reps tools_reps = {0}; + struct dhtool_dev_pcieid_get dev_pcieid_get = {0}; + + DHTOOLS_LOG_INFO("is called!\n"); + msg = (struct zxdh_tools_msg *)kzalloc(sizeof(struct zxdh_tools_msg), GFP_KERNEL); + if(msg == NULL) + { + DHTOOLS_LOG_ERR(" kzalloc msg failed!!!\n"); + return -1; + } + + if (copy_from_user(msg, ifr->ifr_ifru.ifru_data, sizeof(struct zxdh_tools_msg))) { + DHTOOLS_LOG_ERR("copy_from_user failed!!!\n"); + kfree(msg); + return -EFAULT; + } + + user_event_pid = msg->event_pid; + tools_reps.status = MSG_RECV_OK; + tools_reps.data[0] = msg->event_id; + + DHTOOLS_LOG_INFO("en_dev->pcie_id=0x%x\n", en_dev->pcie_id); + DHTOOLS_LOG_INFO("user_event_pid=%d\n", user_event_pid); + dev_pcieid_get.dev_pcieid = en_dev->pcie_id; + + if (unlikely(copy_to_user((void __user *)msg->msg_reps, &dev_pcieid_get, sizeof(struct dhtool_dev_pcieid_get)))) + { + DHTOOLS_LOG_ERR("copy_to_user failed!!!\n"); + kfree(msg); + return -EFAULT; + } + + if (unlikely(copy_to_user((void __user *)msg->tools_reps, &tools_reps, sizeof(struct zxdh_tools_reps)))) + { + DHTOOLS_LOG_ERR("copy_to_user failed!!!\n"); + kfree(msg); + return -EFAULT; + } + kfree(msg); + return 0; +} +/* Ended by AICoder, pid:x7951lc26423ce61419e0a0a502a9b6cc494ddd1 */ + +int32_t zxdh_tools_ioctl_barchan_send(struct net_device *netdev, struct ifreq *ifr) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + struct zxdh_tools_msg *msg = NULL; + uint8_t *payload_addr = NULL; + uint8_t *msg_reps = NULL; + uint16_t msg_reps_len = 0; + struct zxdh_tools_reps tools_reps = {0}; + struct zxdh_pci_bar_msg in = {0}; + struct zxdh_msg_recviver_mem result = {0}; + int32_t ret = 0; + + DHTOOLS_LOG_INFO("is called!\n"); + DHTOOLS_LOG_INFO("en_dev->pcie_id=0x%x\n", en_dev->pcie_id); + + msg = (struct zxdh_tools_msg *)kzalloc(sizeof(struct zxdh_tools_msg), GFP_KERNEL); + if(msg == NULL) + { + DHTOOLS_LOG_ERR("kzalloc msg failed!!!\n"); + return -1; + } + + if (copy_from_user(msg, ifr->ifr_ifru.ifru_data, sizeof(struct zxdh_tools_msg))) { + DHTOOLS_LOG_ERR("copy_from_user failed!!!\n"); + kfree(msg); + return -EFAULT; + } + + if(msg->payload_len == 0 || msg->payload_len > BAR_MSG_PAYLOAD_MAX_LEN) + { + DHTOOLS_LOG_ERR("send para ERR: invalid payload len: %d!\n", msg->payload_len); + kfree(msg); + return -1; + } + + payload_addr = vmalloc(msg->payload_len); + if(payload_addr == NULL) + { + DHTOOLS_LOG_ERR("vmalloc payload_addr failed!!!\n"); + kfree(msg); + return -1; + } + + if (copy_from_user(payload_addr, ifr->ifr_ifru.ifru_data + sizeof(struct zxdh_tools_msg), msg->payload_len)){ + DHTOOLS_LOG_ERR("copy_from_user failed!!!\n"); + vfree(payload_addr); + kfree(msg); + return -EFAULT; + } + +/*调试*/ +#if 0 + DHTOOLS_LOG_INFO("msg->payload_len = %u\n", msg->payload_len); + int i; + for(i = 0; i < msg->payload_len; i+=sizeof(uint32_t)) + { + DHTOOLS_LOG_INFO("*(uint32_t*)(payload_addr + %d) = %d\n", i, *(uint32_t*)(payload_addr + i)); + } +#endif + + in.virt_addr = (uint64_t)ZXDH_BAR_MSG_BASE(en_dev->ops->get_bar_virt_addr(en_dev->parent, 0)); + in.payload_addr = payload_addr; + in.payload_len = msg->payload_len; + in.src = MSG_CHAN_END_PF; + in.dst = msg->dst; + in.event_id = msg->event_id; + in.src_pcieid = en_dev->pcie_id; + in.dst_pcieid = msg->dst_pcieid; + + if(msg->msg_reps_len == 0 || msg->msg_reps_len > BAR_MSG_PAYLOAD_MAX_LEN) + { + DHTOOLS_LOG_ERR("send para ERR: invalid msg_reps_len: %d!\n", msg->msg_reps_len); + vfree(payload_addr); + kfree(msg); + return -1; + } + result.buffer_len = msg->msg_reps_len + REPS_HEADER_PAYLOAD_OFFSET; + result.recv_buffer = vmalloc(result.buffer_len); + if(result.recv_buffer == NULL) + { + DHTOOLS_LOG_ERR("vmalloc result.recv_buffer failed!!!\n"); + vfree(payload_addr); + kfree(msg); + return -1; + } + msg_reps = (uint8_t *)result.recv_buffer + REPS_HEADER_PAYLOAD_OFFSET; + msg_reps_len = msg->msg_reps_len; + + ret = zxdh_bar_chan_sync_msg_send(&in, &result); + if (ret != BAR_MSG_OK) + { + DHTOOLS_LOG_ERR("zxdh_bar_chan_sync_msg_send failed, ret=%d!!!\n", ret); + } + + tools_reps.bar_or_vq_chan_ret = ret; + tools_reps.status = MSG_RECV_OK; + tools_reps.data[0] = msg->event_id; + + /*调试*/ + //DHTOOLS_LOG_INFO("result.recv_buffer 8 bytes: 0x%llx\n", *(uint64_t *)result.recv_buffer); + + if (unlikely(copy_to_user((void __user *)msg->msg_reps, msg_reps, msg_reps_len))) + { + DHTOOLS_LOG_ERR("copy_to_user failed!!!\n"); + vfree(result.recv_buffer); + vfree(payload_addr); + kfree(msg); + return -EFAULT; + } + + if (unlikely(copy_to_user((void __user *)msg->tools_reps, &tools_reps, sizeof(struct zxdh_tools_reps)))) + { + DHTOOLS_LOG_ERR("copy_to_user failed!!!\n"); + vfree(result.recv_buffer); + vfree(payload_addr); + kfree(msg); + return -EFAULT; + } + + vfree(result.recv_buffer); + vfree(payload_addr); + kfree(msg); + return 0; +} + + +#ifdef ZXDH_MSGQ +int32_t zxdh_tools_ioctl_msgq_send(struct net_device *netdev, struct ifreq *ifr) +{ + struct zxdh_en_device *en_dev = NULL; + struct msgq_dev *msgq_dev = NULL; + struct msgq_pkt_info pkt_info = {0}; + struct zxdh_tools_msg *msg = NULL; + uint8_t *payload_addr = NULL; + struct zxdh_tools_reps tools_reps = {0}; + struct reps_info msg_reps = {0}; + int32_t ret = 0; + + CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n"); + CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n"); + + en_dev = netdev_priv(netdev); + if (en_dev == NULL) + { + LOG_ERR("en_dev is null!\n"); + return -1; + } + msgq_dev = (struct msgq_dev *)en_dev->msgq_dev; + if (msgq_dev == NULL) + { + LOG_ERR("msgq_dev null!\n"); + return -1; + } + + DHTOOLS_LOG_INFO("is called!\n"); + DHTOOLS_LOG_INFO("en_dev->pcie_id=0x%x\n", en_dev->pcie_id); + + msg = (struct zxdh_tools_msg *)kzalloc(sizeof(struct zxdh_tools_msg), GFP_KERNEL); + if(msg == NULL) + { + DHTOOLS_LOG_ERR("kzalloc msg failed!!!\n"); + return -1; + } + + if (copy_from_user(msg, ifr->ifr_ifru.ifru_data, sizeof(struct zxdh_tools_msg))) { + DHTOOLS_LOG_ERR("copy_from_user failed!!!\n"); + kfree(msg); + return -1; + } + + if(msg->payload_len == 0 || msg->payload_len > MAX_PACKET_LEN) + { + DHTOOLS_LOG_ERR("send para ERR: invalid payload len: %d!\n", msg->payload_len); + kfree(msg); + return -1; + } + + payload_addr = kzalloc(msg->payload_len + PRIV_HEADER_LEN, GFP_KERNEL); + if(payload_addr == NULL) + { + DHTOOLS_LOG_ERR("vmalloc payload_addr failed!!!\n"); + kfree(msg); + return -1; + } + + if (copy_from_user(payload_addr + PRIV_HEADER_LEN, ifr->ifr_ifru.ifru_data + sizeof(struct zxdh_tools_msg), msg->payload_len)){ + DHTOOLS_LOG_ERR("copy_from_user failed!!!\n"); + kfree(payload_addr); + kfree(msg); + return -1; + } + +/*调试*/ +#if 0 + DHTOOLS_LOG_INFO("msg->payload_len = %u\n", msg->payload_len); + int i; + for(i = 0; i < msg->payload_len; i+=sizeof(uint32_t)) + { + DHTOOLS_LOG_INFO("*(uint32_t*)(payload_addr + %d) = %d\n", i, *(uint32_t*)(payload_addr + i)); + } +#endif + + pkt_info.event_id = msg->event_id; + pkt_info.timeout_us = 400000; + pkt_info.is_async = msg->sync_or_async; + pkt_info.len = msg->payload_len + PRIV_HEADER_LEN; + pkt_info.addr = payload_addr; + DHTOOLS_LOG_INFO("data_len: %d\n", pkt_info.len); + + if(msg->msg_reps_len == 0 || msg->msg_reps_len > MAX_PACKET_LEN) + { + DHTOOLS_LOG_ERR("send para ERR: invalid msg_reps_len: %d!\n", msg->msg_reps_len); + kfree(payload_addr); + kfree(msg); + return -1; + } + msg_reps.len = msg->msg_reps_len; + msg_reps.addr = vmalloc(msg_reps.len); + if(msg_reps.addr == NULL) + { + DHTOOLS_LOG_ERR("vmalloc msg_reps.addr failed!!!\n"); + kfree(payload_addr); + kfree(msg); + return -1; + } + + ret = zxdh_msgq_send_cmd(msgq_dev, &pkt_info, &msg_reps); + if (ret != MSGQ_RET_OK) + { + DHTOOLS_LOG_ERR("zxdh_msgq_send_cmd failed: %d\n", ret); + } + + tools_reps.bar_or_vq_chan_ret = ret; + tools_reps.status = MSG_RECV_OK; + tools_reps.data[0] = msg->event_id; + + if (unlikely(copy_to_user((void __user *)msg->msg_reps, msg_reps.addr, msg_reps.len))) + { + DHTOOLS_LOG_ERR("copy_to_user failed!!!\n"); + goto err_ret; + } + + if (unlikely(copy_to_user((void __user *)msg->tools_reps, &tools_reps, sizeof(struct zxdh_tools_reps)))) + { + DHTOOLS_LOG_ERR("copy_to_user failed!!!\n"); + goto err_ret; + } + + vfree(msg_reps.addr); + kfree(msg); + return 0; + +err_ret: + vfree(msg_reps.addr); + kfree(msg); + return -1; +} +#endif + +int32_t dhtool_device_info_get(struct net_device *netdev, struct ifreq *ifr) +{ + struct zxdh_en_priv *en_priv = netdev_priv(netdev); + struct zxdh_en_device *en_dev = &en_priv->edev; + struct pci_dev *pdev = NULL; + struct pci_dev *swdsp_pdev = NULL; + struct pci_dev *swusp_pdev = NULL; + struct pci_dev *rp_pdev = NULL; + + struct zxdh_tools_msg *msg = NULL; + struct zxdh_tools_reps tools_reps = {0}; + struct dhtool_dev_info_get_reps dev_info_get = {0}; + int sscanf_ret = 0; + + DHTOOLS_LOG_INFO("is called!\n"); + msg = (struct zxdh_tools_msg *)kzalloc(sizeof(struct zxdh_tools_msg), GFP_KERNEL); + if(msg == NULL) + { + DHTOOLS_LOG_ERR(" kzalloc msg failed!!!\n"); + return -1; + } + + if (copy_from_user(msg, ifr->ifr_ifru.ifru_data, sizeof(struct zxdh_tools_msg))) { + DHTOOLS_LOG_ERR("copy_from_user failed!!!\n"); + kfree(msg); + return -EFAULT; + } + + tools_reps.status = MSG_RECV_OK; + + pdev = en_dev->ops->get_pdev(en_dev->parent); + if (!pdev){ + DHTOOLS_LOG_ERR("pdev is NULL\n"); + kfree(msg); + return -EINVAL; + } + + sscanf_ret = sscanf(pci_name(pdev), "%x:%x:%x.%u", &dev_info_get.dev_info.domain_no, &dev_info_get.dev_info.bus_no, \ + &dev_info_get.dev_info.device_no, &dev_info_get.dev_info.func_no); + if(sscanf_ret != 4){ + DHTOOLS_LOG_ERR("could not get dev domain_no、bus_no、device_no、func_no from pci_name(pdev)\n"); + kfree(msg); + return -1; + + } + DHTOOLS_LOG_INFO("dev_info, domain:bus:device.func = %04x:%02x:%02x.%x\n", dev_info_get.dev_info.domain_no, dev_info_get.dev_info.bus_no, \ + dev_info_get.dev_info.device_no, dev_info_get.dev_info.func_no); + + swdsp_pdev = pci_upstream_bridge(pdev); + if (!swdsp_pdev){ + DHTOOLS_LOG_ERR("swdsp_pdev is NULL\n"); + kfree(msg); + return -EINVAL; + } + + if(swdsp_pdev->device == SWITCH_DEVICE_ID && swdsp_pdev->vendor == SWITCH_VENDOR_ID){ + swusp_pdev = pci_upstream_bridge(swdsp_pdev); + if (!swusp_pdev){ + DHTOOLS_LOG_ERR("swusp_pdev is NULL\n"); + kfree(msg); + return -EINVAL; + } + + rp_pdev = pci_upstream_bridge(swusp_pdev); + if (!rp_pdev) + { + DHTOOLS_LOG_ERR("rp_pdev is NULL\n"); + kfree(msg); + return -EINVAL; + } + dev_info_get.switch_or_noswitch = SWITCH; + sscanf_ret = sscanf(pci_name(rp_pdev), "%x:%x:%x.%u", &dev_info_get.rp_info.domain_no, &dev_info_get.rp_info.bus_no, \ + &dev_info_get.rp_info.device_no, &dev_info_get.rp_info.func_no); + if(sscanf_ret != 4){ + DHTOOLS_LOG_ERR("could not get rp domain_no、bus_no、device_no、func_no from pci_name(rp_pdev)\n"); + kfree(msg); + return -1; + } + sscanf_ret = sscanf(pci_name(swusp_pdev), "%x:%x:%x.%u", &dev_info_get.swusp_info.domain_no, &dev_info_get.swusp_info.bus_no, \ + &dev_info_get.swusp_info.device_no, &dev_info_get.swusp_info.func_no); + if(sscanf_ret != 4){ + DHTOOLS_LOG_ERR("could not get swusp domain_no、bus_no、device_no、func_no from pci_name(swusp_pdev)\n"); + kfree(msg); + return -1; + } + } + else{ + dev_info_get.switch_or_noswitch = NO_SWITCH; + sscanf_ret = sscanf(pci_name(swdsp_pdev), "%x:%x:%x.%u", &dev_info_get.rp_info.domain_no, &dev_info_get.rp_info.bus_no, \ + &dev_info_get.rp_info.device_no, &dev_info_get.rp_info.func_no); + if(sscanf_ret != 4){ + DHTOOLS_LOG_ERR("could not get rp domain_no、bus_no、device_no、func_no from pci_name(swdsp_pdev)\n"); + kfree(msg); + return -1; + } + } + DHTOOLS_LOG_INFO("rp_info, domain:bus:device.func = %04x:%02x:%02x.%x\n", dev_info_get.rp_info.domain_no, dev_info_get.rp_info.bus_no, \ + dev_info_get.rp_info.device_no, dev_info_get.rp_info.func_no); + + if (unlikely(copy_to_user((void __user *)msg->msg_reps, &dev_info_get, sizeof(struct dhtool_dev_info_get_reps)))) + { + DHTOOLS_LOG_ERR("copy_to_user failed!!!\n"); + kfree(msg); + return -EFAULT; + } + + if (unlikely(copy_to_user((void __user *)msg->tools_reps, &tools_reps, sizeof(struct zxdh_tools_reps)))) + { + DHTOOLS_LOG_ERR("copy_to_user failed!!!\n"); + kfree(msg); + return -EFAULT; + } + kfree(msg); + return 0; +} + +struct zxdh_tools_ioctl_subcmd_info subcmd_table[] = { + {MSG_MARK_INFO, zxdh_tools_mark_event_info}, +#ifdef ZXDH_TOOLS_MSGQ + {MSG_SEND_TO_RISCV, zxdh_tools_ioctl_msgq_send}, +#else + {MSG_SEND_TO_RISCV, zxdh_tools_ioctl_barchan_send}, +#endif + {MSG_DEVICE_INFO_GET, dhtool_device_info_get}, +}; + +int32_t zxdh_tools_ioctl_dispatcher(struct net_device *netdev, struct ifreq *ifr) +{ + struct zxdh_tools_msg *msg = NULL; + int32_t ret = 0; + uint32_t i = 0; + + DHTOOLS_LOG_INFO("is called!\n"); + msg = (struct zxdh_tools_msg *)kzalloc(sizeof(struct zxdh_tools_msg), GFP_KERNEL); + if(msg == NULL) + { + DHTOOLS_LOG_ERR("kzalloc msg failed!!!\n"); + return -1; + } + + if (copy_from_user(msg, ifr->ifr_ifru.ifru_data, sizeof(struct zxdh_tools_msg))) { + DHTOOLS_LOG_ERR("copy_from_user failed!!!\n"); + kfree(msg); + return -EFAULT; + } + + for (i = 0; i < ARRAY_SIZE(subcmd_table); i++){ + if((subcmd_table[i].subcmd == msg->subcmd) && (subcmd_table[i].subcmd_callback)){ + ret = subcmd_table[i].subcmd_callback(netdev, ifr); + } + } + + kfree(msg); + return ret; +} + + diff --git a/src/net/drivers/net/ethernet/dinghai/zxdh_tools/zxdh_tools_ioctl.h b/src/net/drivers/net/ethernet/dinghai/zxdh_tools/zxdh_tools_ioctl.h new file mode 100755 index 0000000..0e1978b --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/zxdh_tools/zxdh_tools_ioctl.h @@ -0,0 +1,88 @@ +#ifndef ZXDH_TOOLS_IOCTL_H_ +#define ZXDH_TOOLS_IOCTL_H_ + +#include + +//#define ZXDH_TOOLS_MSGQ + +#define SWITCH_DEVICE_ID 0x1113 +#define SWITCH_VENDOR_ID 0x1556 +typedef enum +{ + MSG_MARK_INFO = 0, + MSG_SEND_TO_RISCV, + MSG_DEVICE_INFO_GET, + SUBCMD_NUM=10, +}MSG_SUBCMD; + + +typedef enum +{ + MSG_RECV_OK = 1, +}MSG_RESPONSE; + +typedef enum +{ + NO_SWITCH = 0, + SWITCH = 1, +}SWITCH_FLAG; + +struct zxdh_tools_msg +{ + uint32_t subcmd; //provider care + uint32_t event_pid; //provider care + void* tools_reps; //provider care + uint32_t event_id; //caller care + uint16_t dst; //caller care + uint16_t dst_pcieid; //caller care + void* msg_reps; //caller care + uint16_t msg_reps_len; //caller care + uint16_t sync_or_async; //caller care + uint16_t payload_len; //caller care + uint16_t reserved; //caller care + uint8_t payload[0]; +}__attribute__((packed)); + +struct zxdh_tools_reps +{ + uint32_t status; /* must be */ + int32_t bar_or_vq_chan_ret; + uint32_t data[15]; +}; + +struct zxdh_tools_ioctl_subcmd_info +{ + MSG_SUBCMD subcmd; + int32_t (*subcmd_callback)(struct net_device *netdev, struct ifreq *ifr); +}; + +struct dhtool_dev_pcieid_get +{ + uint32_t dev_pcieid; +}; +struct dhtool_dev_info +{ + uint32_t domain_no; + uint32_t bus_no; + uint32_t device_no; + uint32_t func_no; +}; + +struct dhtool_dev_info_get_reps +{ + SWITCH_FLAG switch_or_noswitch; + struct dhtool_dev_info dev_info; + struct dhtool_dev_info rp_info; + union + { + struct dhtool_dev_info swusp_info; + }; +}; + +int32_t zxdh_tools_ioctl_dispatcher(struct net_device *netdev, struct ifreq *ifr); + +#define DHTOOLS_LOG_ERR(fmt, arg...) DH_LOG_ERR(MODULE_DHTOOLS, fmt, ##arg); +#define DHTOOLS_LOG_INFO(fmt, arg...) DH_LOG_INFO(MODULE_DHTOOLS, fmt, ##arg); + + +#endif diff --git a/src/net/drivers/net/ethernet/dinghai/zxdh_tools/zxdh_tools_netlink.c b/src/net/drivers/net/ethernet/dinghai/zxdh_tools/zxdh_tools_netlink.c new file mode 100644 index 0000000..d17113b --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/zxdh_tools/zxdh_tools_netlink.c @@ -0,0 +1,178 @@ +#include +#include +#include +#include "../en_aux.h" +#include "zxdh_tools_ioctl.h" +#include "zxdh_tools_netlink.h" + + +int32_t zxdh_tools_genl_recv_doit(struct sk_buff *skb, struct genl_info *info); + /* operation definition */ +#if (LINUX_VERSION_CODE > KERNEL_VERSION(5, 10, 0)) +static struct nla_policy zxdh_tools_genl_policy[ZXDH_TOOLS_A_MAX + 1] = { + [ZXDH_TOOLS_A_MSG] = { .type = NLA_NUL_STRING }, +}; +#endif + +struct genl_ops zxdh_tools_gnl_ops[] = { + { + .cmd = ZXDH_TOOLS_C_ECHO, + .flags = 0, +#if (LINUX_VERSION_CODE > KERNEL_VERSION(5, 10, 0)) + .policy = zxdh_tools_genl_policy, +#endif + .doit = zxdh_tools_genl_recv_doit, + .dumpit = NULL, + } +}; + +static struct genl_family zxdh_tools_msg_family = { + .hdrsize = 0, + .name = ZXDH_TOOLS_NETLINK_NAME, + .version = 1, + .maxattr = ZXDH_TOOLS_A_MAX, + .ops = zxdh_tools_gnl_ops, + .n_ops = 1, +}; + +/* +* genl_msg_prepare_usr_msg : 构建netlink及gennetlink首部 +* @cmd : genl_ops的cmd +* @size : gen_netlink用户数据的长度（包括用户定义的首部） +*/ +int32_t zxdh_tools_genl_msg_prepare_usr_msg(u8 cmd, size_t size, uint32_t pid, struct sk_buff **skbp) +{ + struct sk_buff *skb; + DHTOOLS_LOG_INFO("is called!\n"); + /* create a new netlink msg */ + skb = genlmsg_new(size, GFP_KERNEL); + if (skb == NULL) + { + DHTOOLS_LOG_ERR("genlmsg_new failed!!!\n"); + return -ENOMEM; + } + /* Add a new netlink message to an skb */ + genlmsg_put(skb, pid, 0, &zxdh_tools_msg_family, 0, cmd); + *skbp = skb; + return 0; +} + +/* +* 添加用户数据，及添加一个netlink addribute +*@type : nlattr的type +*@len : nlattr中的len +*@data : 用户数据 +*/ +int32_t zxdh_tools_genl_msg_mk_usr_msg(struct sk_buff *skb, int type, void *data, int len) +{ + int rc; + DHTOOLS_LOG_INFO("is called!\n"); + /* add a netlink attribute to a socket buffer */ + if ((rc = nla_put(skb, type, len, data)) != 0) + { + DHTOOLS_LOG_ERR("nla_put failed, rc=%d!!!\n",rc); + return rc; + } + return 0; +} + +/** +* genl_msg_send_to_user - 通过generic netlink发送数据到netlink +* +* @data: 发送数据缓存 +* @len: 数据长度 单位：byte +* @pid: 发送到的客户端pid +*/ +int32_t zxdh_tools_genl_msg_send_to_user(void *data, uint16_t len, uint32_t pid) +{ + struct sk_buff *skb; + uint16_t size; + int rc; + + DHTOOLS_LOG_INFO("is called!\n"); + size = nla_total_size(len); /* total length of attribute including padding */ + rc = zxdh_tools_genl_msg_prepare_usr_msg(ZXDH_TOOLS_C_ECHO, size, pid, &skb); + if (rc) + { + DHTOOLS_LOG_ERR("zxdh_tools_genl_msg_prepare_usr_msg failed,rc=%d!!!\n", rc); + return rc; + } + + rc = zxdh_tools_genl_msg_mk_usr_msg(skb, ZXDH_TOOLS_A_MSG, data, len); + if (rc) + { + DHTOOLS_LOG_ERR("zxdh_tools_genl_msg_mk_usr_msg failed,rc=%d!!!\n", rc); + kfree_skb(skb); + return rc; + } + + rc = genlmsg_unicast(&init_net, skb, pid); + if (rc < 0) + { + DHTOOLS_LOG_ERR("genlmsg_unicast failed, rc=%d!!!\n", rc); + return rc; + } + DHTOOLS_LOG_INFO("genlmsg_unicast is called, and send msg to user success.\n"); + return 0; +} + +extern uint32_t user_event_pid; +int32_t zxdh_tools_sendto_user_netlink(void *pay_load, uint16_t len, void *reps_buffer, uint16_t *reps_len, void *dev) +{ + struct zxdh_en_device *en_dev = (struct zxdh_en_device *)dev; + int32_t ret = 0; + + DHTOOLS_LOG_INFO("is called!\n"); + if (en_dev == NULL) + { + DHTOOLS_LOG_ERR("dev is NULL\n"); + return -1; + } + + if ((pay_load == NULL) || (len == 0)) { + DHTOOLS_LOG_ERR("invalid para, pay_load = 0x%llx, len = %d\n", (uint64_t)pay_load, len); + return -1; + } + + DHTOOLS_LOG_INFO("en_dev->pcie_id=0x%x\n", en_dev->pcie_id); + DHTOOLS_LOG_INFO("user_event_pid=%d\n", user_event_pid); + DHTOOLS_LOG_INFO("pay_load = 0x%llx, payload_len = %d\n", (uint64_t)pay_load, len); + DHTOOLS_LOG_INFO("*(uint32_t *)pay_load(op_code)=%d\n", *(uint32_t *)pay_load); + + ret = zxdh_tools_genl_msg_send_to_user(pay_load, len, user_event_pid); + if (ret) + { + DHTOOLS_LOG_ERR("zxdh_tools_genl_msg_send_to_user failed, ret=%d!!!\n", ret); + return ret; + } + DHTOOLS_LOG_INFO("zxdh_tools_sendto_user_netlink end, send msg to user success.\n"); + return 0; +} + + +/* doit函数*/ +int32_t zxdh_tools_genl_recv_doit(struct sk_buff *skb, struct genl_info *info) +{ + DHTOOLS_LOG_INFO("is called!\n"); + return 0; +} + +int32_t zxdh_tools_netlink_register(void) +{ + int ret = 0; + ret = genl_register_family(&zxdh_tools_msg_family); + if(ret) + { + DHTOOLS_LOG_ERR("zxdh_tools_netlink_family register failed, ret=%d!!!\n", ret); + return 1; + } + + return 0; +} + + +void zxdh_tools_netlink_unregister(void) +{ + genl_unregister_family(&zxdh_tools_msg_family); +} + diff --git a/src/net/drivers/net/ethernet/dinghai/zxdh_tools/zxdh_tools_netlink.h b/src/net/drivers/net/ethernet/dinghai/zxdh_tools/zxdh_tools_netlink.h new file mode 100644 index 0000000..53f6825 --- /dev/null +++ b/src/net/drivers/net/ethernet/dinghai/zxdh_tools/zxdh_tools_netlink.h @@ -0,0 +1,53 @@ +#ifndef ZXDH_TOOLS_NETLINK_H_ +#define ZXDH_TOOLS_NETLINK_H_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NLA_DATA(na) ((void *)((char *)(na) + NLA_HDRLEN)) +#define ZXDH_TOOLS_NETLINK_NAME "tools_family" + +/* 属性类型*/ +enum { + ZXDH_TOOLS_A_UNSPEC, + ZXDH_TOOLS_A_MSG, + __ZXDH_TOOLS_A_MAX, +}; +#define ZXDH_TOOLS_A_MAX (__ZXDH_TOOLS_A_MAX - 1) + +/* 操作码*/ +enum { + ZXDH_TOOLS_C_UNSPEC, + ZXDH_TOOLS_C_ECHO, + __ZXDH_TOOLS_C_ECHO, +}; +#define ZXDH_TOOLS_C_MAX (__ZXDH_TOOLS_C_MAX - 1) + +typedef enum +{ + FWUPDATE = 27, +} event_op_code; + +struct zxdh_tools_recv_msg { + event_op_code op_code; + uint8_t status; +}; + + +int32_t zxdh_tools_sendto_user_netlink(void *pay_load, uint16_t len, void *reps_buffer, uint16_t *reps_len, void *dev); +int zxdh_tools_netlink_register(void); +void zxdh_tools_netlink_unregister(void); + + +#ifdef __cplusplus +} +#endif + + +#endif /* ZXDH_TOOLS_NETLINK_H_ */ + + + + diff --git a/src/net/drivers/pcie/zxdh_pcie/Makefile b/src/net/drivers/pcie/zxdh_pcie/Makefile new file mode 100644 index 0000000..9ce6b5c --- /dev/null +++ b/src/net/drivers/pcie/zxdh_pcie/Makefile @@ -0,0 +1,16 @@ +subdir-ccflags-y += -I$(src) +subdir-ccflags-y += -I$(CWD)/include/ +subdir-ccflags-y += -include $(CWD)/autoconf.h +ccflags-y += -Werror + + +ifeq ($(CONFIG_DRIVER_VERSION),) +EXTRA_CFLAGS += -DDRIVER_VERSION_VAL=\"1.0-1\" +$(info CONFIG_HPF_DRIVER_VERSION is null, EXTRA_CFLAGS=$(EXTRA_CFLAGS)) +else +EXTRA_CFLAGS += -DDRIVER_VERSION_VAL=\"$(CONFIG_DRIVER_VERSION)\" +$(info CONFIG_HPF_DRIVER_VERSION is not null, EXTRA_CFLAGS=$(EXTRA_CFLAGS)) +endif + +obj-$(CONFIG_DINGHAI_HPF) += zxdh_hpf.o +zxdh_hpf-y := zxdh_pcie.o function_hotplug.o pcie_msix.o pcie_common.o bar_msg.o \ No newline at end of file diff --git a/src/net/drivers/pcie/zxdh_pcie/bar_msg.c b/src/net/drivers/pcie/zxdh_pcie/bar_msg.c new file mode 100644 index 0000000..1aa187f --- /dev/null +++ b/src/net/drivers/pcie/zxdh_pcie/bar_msg.c @@ -0,0 +1,79 @@ +#include "bar_msg.h" +#include "pcie_common.h" + +int pcie_mt_send_msg(void *msg_info, u32 msg_size, void *resp_msg, u32 resp_size) +{ + struct zxdh_pci_bar_msg in = {0}; + struct zxdh_msg_recviver_mem result = {0}; + struct pci_dev *pdev = NULL; + void __iomem *bar_virt_addr = NULL; + u8 head_data = 0xFF; + u16 ret = 0; + u16 pcie_id = 0; + u64 bar_addr = 0; + + if (msg_info == NULL) + { + DH_LOG_ERR(MODULE_FUC_HP, "The msg_info is NULL\n"); + return -EINVAL; + } + + pdev = pci_get_device(HP_VENDOR_ID, HP_DEVICE_ID, NULL); + if (pdev == NULL) + { + DH_LOG_ERR(MODULE_FUC_HP, "Can not find devices: deviceID %x, VendorID: %x\n", HP_VENDOR_ID, HP_DEVICE_ID); + return -EINVAL; + } + + bar_addr = pci_resource_start(pdev, 0); + bar_virt_addr = ioremap(bar_addr, HP_IOREMAP_SIZE); + + /* 填充用户参数in */ + in.virt_addr = (u64)bar_virt_addr + HP_BAR_MSG_OFFSET; /* 使用PF1的bar0偏移8k */ + in.payload_addr = msg_info; /* 消息静荷buffer地址 */ + in.payload_len = msg_size; /* 消息长度 */ + in.src = MSG_CHAN_END_PF; /* 从mpf通道下发 */ + in.dst = MSG_CHAN_END_RISC; /* 消息发到risc */ + in.event_id = PCIE_FUNC_HP_EVENT_ID; /* 调用PCIE的消息处理函数 */ + in.src_pcieid = pcie_id; + + result.buffer_len = BUF_SIZE; /* 用户准备一个存放消息回复的buffer, buffer长度 */ + result.recv_buffer = kmalloc(result.buffer_len, GFP_KERNEL); /* 消息回复buffer地址 */ + if (!result.recv_buffer) + { + DH_LOG_ERR(MODULE_FUC_HP, "Failed to allocate recv_buffer\n"); + return -EINVAL; + } + memset(result.recv_buffer, 0, result.buffer_len); + + ret = zxdh_bar_chan_sync_msg_send(&in, &result); /* 发送同步消息 */ + + iounmap(bar_virt_addr); + bar_virt_addr = NULL; + + /* 如果接口返回值不为0，则说明消息失败 */ + if (ret != 0) + { + DH_LOG_ERR(MODULE_FUC_HP, "pcie mt send msg failed, ret:%d.\n", ret); + goto exit; + } + + /* 如果消息发送成功， 从recv_buffer + 1的位置往后两字节取回复数据长度， recv_buffer + 4的位置开始取数据内容 */ + head_data = *((u8 *)(result.recv_buffer + 4)); + if (head_data == 0x1) + { + DH_LOG_INFO(MODULE_FUC_HP, "pcie mt remote SUCCESS!\n"); + memcpy(resp_msg, result.recv_buffer + 4, resp_size); + ret = 0; + } + else + { + DH_LOG_ERR(MODULE_FUC_HP, "pcie mt test FAIL!\n"); + ret = -EINVAL; + } + +exit: + kfree(result.recv_buffer); + result.recv_buffer = NULL; + return ret; +} \ No newline at end of file diff --git a/src/net/drivers/pcie/zxdh_pcie/bar_msg.h b/src/net/drivers/pcie/zxdh_pcie/bar_msg.h new file mode 100644 index 0000000..91472a0 --- /dev/null +++ b/src/net/drivers/pcie/zxdh_pcie/bar_msg.h @@ -0,0 +1,165 @@ +#ifndef _ZXDH_MSG_CHAN_PUB_H_ +#define _ZXDH_MSG_CHAN_PUB_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include +#include +#include +#include +#include +#include +// #include + +#define PCIE_FUNC_HP_EVENT_ID 44 +#define BUF_SIZE 0x1000 + +/* bar消息通道使用pf信息 */ +#define HP_BAR_MSG_OFFSET 0x2000 +#define HP_VENDOR_ID 0x1cf2 +#define HP_DEVICE_ID 0x8031 +// #define HP_VENDOR_ID 0x16c3 +// #define HP_DEVICE_ID 0 +#define HP_IOREMAP_SIZE 0x3000 + +/* data type */ +typedef unsigned long long int u64; +typedef signed long long int s64; + +typedef unsigned int u32; +typedef signed int s32; + +typedef unsigned short int u16; +typedef signed short int s16; + +typedef unsigned char u8; +typedef signed char s8; + +/* printk level */ + + +/* + * The interface for communication among HOST, RISC-V and ZF drivers + * is as follows... + * + * A. COMMUNICATION THROUGH BAR CHANNEL + * + * + * B. COMMUNICATION THROUGH PKT CHANNEL + * + * Make sure you have allocated private queues and MSI-X interrupt for them. + * Then set callback of the vector with virtnet_poll_private(). + * Choose the proper paramaters and fill them in the zxdh_pkt_chan_msg_send(). + * Enjoying communicating with others whenever you want. + */ + +/* Value that the zxdh_pkt_chan_msg_send() can be returned */ +#define MSG_CHAN_RET_OK 0 +#define MSG_CHAN_RET_ERR_NULL_PTR (-1) +#define MSG_CHAN_RET_ERR_INVALID_PARA (-2) +#define MSG_CHAN_RET_ERR_NO_ENOUGH_MEM (-4) +#define MSG_CHAN_RET_ERR_CHANNEL_NOT_READY (-5) +#define MSG_CHAN_RET_ERR_CHAN_BUSY (-6) +#define MSG_CHAN_RET_ERR_CHAN_BROKEN (-7) +#define MSG_CHAN_RET_ERR_XMIT_FAIL (-8) +#define MSG_CHAN_RET_ERR_CALLBACK_OUT_OF_TIME (-9) +#define MSG_CHAN_RET_ERR_NO_PRIV_QUEUE (-10) +#define MSG_CHAN_RET_ERR_CALLBACK_FAIL (-11) +#define MSG_CHAN_RET_ERR_FREEPAGE_FAIL (-12) + +typedef enum { + TYPE_DEBUG = 0, + DST_RISCV, + DST_MPF, + DST_PF_OR_VF, + DST_ZF, + MSG_TYPE_NUM, +} MSG_TYPE; + +typedef enum BAR_DRIVER_TYPE { + MSG_CHAN_END_MPF = 0, + MSG_CHAN_END_PF, + MSG_CHAN_END_VF, + MSG_CHAN_END_RISC, + MSG_CHAN_END_ERR, +} BAR_DRIVER_TYPE; + +#define BDF_ECAM(bus, devid, func) ((bus & 0xff) << 8) | (func & 0x07) | ((devid & 0x1f) << 3) + +/* bar通道错误码 */ +typedef enum BAR_MSG_RTN { + BAR_MSG_OK = 0, + BAR_MSG_ERR_NULL, /* < 空指针 > */ + BAR_MSG_ERR_TYPE, /* < 消息类型异常 > */ + BAR_MSG_ERR_MODULE, /* < 模块ID异常 > */ + BAR_MSG_ERR_BODY_NULL, /* < 消息体异常 > */ + BAR_MSG_ERR_LEN, /* < 消息长度异常 > */ + BAR_MSG_ERR_TIME_OUT, /* < 消息超时 > */ + BAR_MSG_ERR_NOT_READY, /* < 消息发送条件异常，BUF不可以用> */ + BAR_MEG_ERR_NULL_FUNC, /* < 空的接收处理函数指针> */ + BAR_MSG_ERR_REPEAT_REGISTER, /* < 模块重复注册> */ + BAR_MSG_ERR_UNGISTER, /* < 重复解注册> */ + BAR_MSG_ERR_NULL_PARA, /* < 参数空指针> */ + BAR_MSG_ERR_REPSBUFF_LEN, /* < reps_buff长度异常> */ + BAR_MSG_ERR_MODULE_NOEXIST, /* < 查找不到该模块对应的消息处理函数> */ + BAR_MSG_ERR_VIRTADDR_NULL, /* < 发送接口传入参数中的虚拟地址为空> */ + BAR_MSG_ERR_REPLY, /* < seq_id匹配失败> */ + BAR_MSG_ERR_MSGID, /* < seq_id申请失败> */ + BAR_MSG_ERR_MPF_NOT_SCANED, /* < MPF通道不可用> */ + BAR_MSG_ERR_USR_RET_ERR, /* < 处理函数返回值错误> */ + BAR_MSG_ERR_ERR_PCIEID, /* < pcieID错误> */ + BAR_MSG_ERR_NOT_MATCH, +} BAR_MSG_RTN; + + + +/* msix消息参数结构体 */ +struct msix_para { + u16 vector_risc; + u16 vector_pfvf; + u16 vector_mpf; + u16 driver_type; + struct pci_dev *pdev; + u64 virt_addr; +}; + +struct zxdh_pci_bar_msg { + u64 virt_addr; /* < 4k空间地址, 若src为MPF该参数不生效> */ + void *payload_addr; /* < 消息净荷地址> */ + u16 payload_len; /* < 消息净荷长度> */ + u16 emec; /* < 消息紧急类型> */ + u16 src; /* < 消息发送源，参考BAR_DRIVER_TYPE> */ + u16 dst; /* < 消息接收者，参考BAR_DRIVER_TYPE> */ + u32 event_id; /* < 事件id> */ + u16 src_pcieid; /* < 源 pcie_id> */ + u16 dst_pcieid; /* < 目的pcie_id> */ +}; + +struct zxdh_msg_recviver_mem { + void *recv_buffer; /* < 消息接收缓存> */ + u16 buffer_len; /* < 消息缓存长度> */ +}; + +/* 消息处理函数，payload和len表示来的消息 */ +typedef int (*zxdh_bar_chan_msg_recv_callback)(void *pay_load, u16 len, void *reps_buffer, u16 *reps_len, void *dev); + +/* + * zxdh_bar_chan_sync_msg_send - 通过PCIE BAR空间发送同步消息 + * @in: 消息发送信息 + * @result: 消息结果反馈 + * @return: 0 成功，其他失败 + */ +int zxdh_bar_chan_sync_msg_send(struct zxdh_pci_bar_msg *in, struct zxdh_msg_recviver_mem *result); + +int pcie_mt_send_msg(void *msg_info, u32 msg_size, void *resp_msg, u32 resp_size); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/net/drivers/pcie/zxdh_pcie/function_hotplug.c b/src/net/drivers/pcie/zxdh_pcie/function_hotplug.c new file mode 100644 index 0000000..e7dbe25 --- /dev/null +++ b/src/net/drivers/pcie/zxdh_pcie/function_hotplug.c @@ -0,0 +1,461 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "bar_msg.h" +#include "function_hotplug.h" +#include "pcie_common.h" + +extern int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn); + +char bind_type_name[FUNCTION_HP_TYPE_COUNT][FILE_PATH_LEN] = {"unbind", "bind"}; + +static struct zte_dpu_id_info zte_dpu_id_info[] = { + /* name, device_id, vendor_id,*/ + {"virtio_blk", 0x1001, 0x1af4}, + {"nvme", 0x8053, 0x1cf2}, +}; + +int init_pf_hotplug_info() +{ + // pf_hotplug_info.cmd = 11; // TODO + + return 0; +} + +int remove_pci_dev(struct func_hotplug_req *hp_req) +{ + int ret = PCIE_SUCCESS; + struct pci_dev *pdev = NULL; + + DH_LOG_DEBUG(MODULE_FUC_HP,"domain=0x%x, bdf=0x%x\n", hp_req->domain, hp_req->bdf); + pdev = zxdh_get_pci_device(hp_req->domain, hp_req->bdf); + if (!pdev) + { + DH_LOG_DEBUG(MODULE_FUC_HP, "This device has removed\n"); + goto finish; + } + + pci_sriov_configure_simple(pdev, 0); + + pci_stop_and_remove_bus_device_locked(pdev); + + pdev = zxdh_get_pci_device(hp_req->domain, hp_req->bdf); + if (pdev) + { + DH_LOG_ERR(MODULE_FUC_HP, "remove fail! domain=0x%x, bdf=0x%x\n", hp_req->domain, hp_req->bdf); + ret = PCIE_FAILED; + } + +finish: + return ret; +} + +int all_ep_rescan(void) +{ + int ret = PCIE_SUCCESS; + int size = 0; + struct file *filp = NULL; + char filename[FILE_PATH_LEN] = {0}; + char date = '1'; + + size = snprintf(filename, FILE_PATH_LEN, "%s/%s", SYS_BUS_PCI_DIR, "rescan"); + if (size >= sizeof(filename)) + { + filename[sizeof(filename) - 1] = '\0'; + } + DH_LOG_INFO(MODULE_FUC_HP, "filename=%s\n", filename); + + filp = filp_open(filename, O_WRONLY, 0); + if (IS_ERR(filp)) + { + DH_LOG_ERR(MODULE_FUC_HP, "open file error\n"); + return PCIE_FAILED; + } + + kernel_write(filp, &date, sizeof(char), &filp->f_pos); + filp_close(filp, NULL); + + return ret; +} + +int rescan_pci_dev(struct func_hotplug_req *hp_req) +{ + int ret = PCIE_SUCCESS; + struct pci_dev *pdev = NULL; + + DH_LOG_DEBUG(MODULE_FUC_HP, "domain=0x%x, rescan bdf=0x%x\n", hp_req->domain, hp_req->bdf); + hp_req->bdf = hp_req->bdf & (~BDF_NO_FUNC_NO_MASK); + DH_LOG_DEBUG(MODULE_FUC_HP, "domain=0x%x, bdf=0x%x\n", hp_req->domain, hp_req->bdf); + + pdev = zxdh_get_pci_device(hp_req->domain, hp_req->bdf); + if (!pdev) + { + all_ep_rescan(); + } + else + { + pci_rescan_bus(pdev->bus); + } + + init_pf_state(); + + return ret; +} + +int vf_bind_unbind(struct func_hotplug_req *hp_req) +{ + int ret = PCIE_SUCCESS; + int size = 0; + struct file *filp = NULL; + char filename[FILE_PATH_LEN] = {0}; + char bdf[FILE_PATH_LEN] = {0}; + unsigned int scene_code = 0; + u32 bus_no = 0; + u32 device_no = 0; + u32 func_no = 0; + + memset(filename, 0, FILE_PATH_LEN); + + scene_code = SCENE_CODE_OF_FUNC_HP_INFO(hp_req->hotplug_info); + bus_no = (hp_req->bdf & BDF_NO_BUS_NO_MASK) >> BDF_B_START_BIT; + device_no = (hp_req->bdf & BDF_NO_DEV_NO_MASK) >> BDF_D_START_BIT; + func_no = (hp_req->bdf & BDF_NO_FUNC_NO_MASK) >> BDF_F_START_BIT; + size = snprintf(bdf, FILE_PATH_LEN, "%x:%x:%x.%x", hp_req->domain, bus_no, device_no, func_no); + if (size >= sizeof(bdf)) + { + bdf[sizeof(bdf) - 1] = '\0'; + } + DH_LOG_INFO(MODULE_FUC_HP, "scene_code=%d, bind_type_name=%s, bdf=%s\n", scene_code, bind_type_name[scene_code - FUNCTION_REMOVE], bdf); + + ret = parse_bdf(bdf); + if (ret != PCIE_SUCCESS) + { + DH_LOG_ERR(MODULE_FUC_HP, "%s: parse bdf fail\n", __func__); + return PCIE_FAILED; + } + + size = snprintf(filename, FILE_PATH_LEN, "%s/%s/%s/%s", PCI_DEVICES_DIR, bdf, PCI_PHYSFN_DRV_PATH, bind_type_name[scene_code - FUNCTION_REMOVE]); + if (size >= sizeof(filename)) + { + filename[sizeof(filename) - 1] = '\0'; + } + DH_LOG_INFO(MODULE_FUC_HP, "filename=%s\n", filename); + + filp = filp_open(filename, O_WRONLY, 0); + if (IS_ERR(filp)) + { + DH_LOG_ERR(MODULE_FUC_HP, "open file error\n"); + return PCIE_FAILED; + } + + kernel_write(filp, (unsigned char*)bdf, sizeof(bdf), &filp->f_pos); + filp_close(filp, NULL); + + return ret; +} + +static void print_func_hotplug_req(struct func_hotplug_req *func_hp_req) +{ + DH_LOG_DEBUG(MODULE_FUC_HP, "scene_code=0x%x, function_type=0x%x, ep_id=0x%x, pf_id=0x%x, vf_id=0x%x, domain=0x%x, bdf=0x%x\n", + SCENE_CODE_OF_FUNC_HP_INFO(func_hp_req->hotplug_info), FUNC_TYPE_OF_FUNC_HP_INFO(func_hp_req->hotplug_info), + EP_ID_OF_FUNC_HP_INFO(func_hp_req->hotplug_info), PF_ID_OF_FUNC_HP_INFO(func_hp_req->hotplug_info), + VF_ID_OF_FUNC_HP_INFO(func_hp_req->hotplug_info), func_hp_req->domain, func_hp_req->bdf); +} + +static void func_hp_info_decode(struct func_hotplug_req *hp_req, struct func_hotplug_info *hp_info) +{ + hp_info->scene_code = SCENE_CODE_OF_FUNC_HP_INFO(hp_req->hotplug_info); + hp_info->function_type = FUNC_TYPE_OF_FUNC_HP_INFO(hp_req->hotplug_info); + hp_info->ep_id = EP_ID_OF_FUNC_HP_INFO(hp_req->hotplug_info); + hp_info->pf_id = PF_ID_OF_FUNC_HP_INFO(hp_req->hotplug_info); + hp_info->vf_id = VF_ID_OF_FUNC_HP_INFO(hp_req->hotplug_info); + DH_LOG_DEBUG(MODULE_FUC_HP, "scene_code=0x%x, function_type=0x%x, ep_id=0x%x, pf_id=0x%x, vf_id=0x%x, hotplug_info=0x%x\n", + hp_info->scene_code, hp_info->function_type, + hp_info->ep_id, hp_info->pf_id, + hp_info->vf_id, hp_req->hotplug_info); +} + +static int func_remove(unsigned int function_type, struct func_hotplug_req *hp_req) +{ + int ret = PCIE_SUCCESS; + + if (function_type == PCIE_FUNC_TYPE_PF) + { + ret = init_pf_state(); + } + else if (function_type == PCIE_FUNC_TYPE_VF) + { + ret = vf_bind_unbind(hp_req); + } + else + { + DH_LOG_ERR(MODULE_FUC_HP, "error function_type=0x%x\n", function_type); + ret = PCIE_FAILED; + } + + return ret; +} + +static int func_insert(unsigned int function_type, struct func_hotplug_req *hp_req) +{ + int ret = PCIE_SUCCESS; + + if (function_type == PCIE_FUNC_TYPE_PF) + { + ret = rescan_pci_dev(hp_req); + } + else if (function_type == PCIE_FUNC_TYPE_VF) + { + ret = vf_bind_unbind(hp_req); + } + else + { + DH_LOG_ERR(MODULE_FUC_HP, "error function_type=0x%x\n", function_type); + ret = PCIE_FAILED; + } + + return ret; +} + +int func_hp(void) +{ + int ret = PCIE_SUCCESS; + struct pci_dev *hp_pdev = NULL; + struct func_hotplug_req hp_req = {0}; + struct func_hotplug_result hp_result = {0}; + struct func_hotplug_info hp_info = {0}; + void __iomem *bar_virt_addr = NULL; + u64 bar_addr = 0; + int resp_msg = 0; + + hp_pdev = pci_get_device(HP_VENDOR_ID, HP_DEVICE_ID, NULL); + if (IS_ERR_OR_NULL(hp_pdev)) + { + DH_LOG_ERR(MODULE_FUC_HP, "This hp device was not found. Please confirm the BDF\n"); + return PCIE_FAILED; + } + + bar_addr = pci_resource_start(hp_pdev, 0); + bar_virt_addr = (void __iomem *)ioremap(bar_addr, HP_IOREMAP_SIZE); + if (bar_virt_addr == NULL) + { + DH_LOG_ERR(MODULE_FUC_HP, "bar_virt_addr map failed\n"); + return PCIE_FAILED; + } + + memcpy(&hp_req, bar_virt_addr, sizeof(struct func_hotplug_req)); + func_hp_info_decode(&hp_req, &hp_info); + print_func_hotplug_req(&hp_req); + + switch (hp_info.scene_code) + { + case FUNCTION_REMOVE: + { + ret = func_remove(hp_info.function_type, &hp_req); + break; + } + case FUNCTION_INSERT: + { + ret = func_insert(hp_info.function_type, &hp_req); + break; + } + default: + { + DH_LOG_ERR(MODULE_FUC_HP, "error scene_code=0x%x\n", hp_info.scene_code); + ret = PCIE_FAILED; + } + } + + hp_result.cmd = PCIE_HOTPLUG_FINISH; + hp_result.hotplug_info = hp_req.hotplug_info; + hp_result.result = (ret == PCIE_SUCCESS) ? FUNC_HP_RESULT_SUCC : FUNC_HP_RESULT_FAIL; + + ret = pcie_mt_send_msg(&hp_result, sizeof(struct func_hotplug_result), &resp_msg, sizeof(int)); + if (ret) + { + DH_LOG_ERR(MODULE_FUC_HP, "send failed\n"); + } + + iounmap(bar_virt_addr); + bar_virt_addr = NULL; + return ret; +} + +int enable_vf(void) +{ + int pos = 0; + u16 total_vf_nums = 0; + int ret = PCIE_SUCCESS; + struct pci_dev *dev = NULL; + int i = 0; + int entry_num = sizeof(zte_dpu_id_info) / sizeof(struct zte_dpu_id_info); + + for(i = 0; i < entry_num; i++) + { + while ((dev = pci_get_device(zte_dpu_id_info[i].vendor_id, zte_dpu_id_info[i].device_id, dev)) != NULL) + { + pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV); + if (!pos) + { + continue; + } + pci_read_config_word(dev, (pos + PCI_SRIOV_TOTAL_VF), &total_vf_nums); + DH_LOG_DEBUG(MODULE_FUC_HP, "Total VFs: %d ", total_vf_nums); + pci_sriov_configure_simple(dev, total_vf_nums); + } + } + + return ret; +} + +int init_bdf(void) +{ + int ret = PCIE_SUCCESS; + int resp_msg = 0; + struct fuc_hotplug_bar_msg fuc_hotplug_bar_msg = {0}; + + fuc_hotplug_bar_msg.cmd = PCIE_HOTPLUG_START; + fuc_hotplug_bar_msg.fuc_hotplug_info = FUC_HOTPLUG_PF_INIT_FLAG; + + ret = hotplug_device_enable(1); + if (ret != 0) + { + DH_LOG_ERR(MODULE_FUC_HP, "enable hotplug device failed.\n"); + return ret; + } + + ret = pcie_mt_send_msg(&fuc_hotplug_bar_msg, sizeof(struct fuc_hotplug_bar_msg), &resp_msg, sizeof(int)); + if (ret != 0) + { + DH_LOG_ERR(MODULE_FUC_HP, "get dbf failed\n"); + } + + return PCIE_SUCCESS; +} + +int init_pf_state(void) +{ + u64 bar_addr = 0; + u8 ep_no = 0; + u8 pf_no = 0; + u32 mask_idx = 0; + struct func_hotplug_req hp_req = {0}; + struct func_hotplug_info hp_info = {0}; + struct func_hotplug_state func_hotplug_state = {0}; + u32 pf_state_mask = 0; + struct pci_dev *hp_pdev = NULL; + void __iomem *bar_virt_addr = NULL; + + hp_pdev = pci_get_device(HP_VENDOR_ID, HP_DEVICE_ID, NULL); + if (IS_ERR_OR_NULL(hp_pdev)) + { + DH_LOG_ERR(MODULE_FUC_HP, "This hp device was not found. Please confirm the BDF\n"); + return PCIE_FAILED; + } + + bar_addr = pci_resource_start(hp_pdev, 0); + bar_virt_addr = (void __iomem *)ioremap(bar_addr, HP_IOREMAP_SIZE); + if (bar_virt_addr == NULL) + { + DH_LOG_ERR(MODULE_FUC_HP, "bar_virt_addr map failed\n"); + return -ENOMEM; + } + + // 获取当前操作的pf + memcpy(&hp_req, bar_virt_addr, sizeof(struct func_hotplug_req)); + func_hp_info_decode(&hp_req, &hp_info); + + memcpy(&func_hotplug_state, bar_virt_addr + FUC_HOTPLUG_PF_STATE_FLAG_OFFSET, sizeof(struct func_hotplug_state)); + + pf_state_mask = func_hotplug_state.pf_state_mask | 0x1; + + for (mask_idx = 0; mask_idx < MAX_PF_NUMS; mask_idx++) + { + ep_no = mask_idx / MAX_PF_NUMS_OF_EP; + pf_no = mask_idx % MAX_PF_NUMS_OF_EP; + hp_req.domain = func_hotplug_state.domain[ep_no]; + hp_req.bdf = func_hotplug_state.bdf[ep_no]; + hp_req.bdf = hp_req.bdf + pf_no; + if (!((pf_state_mask >> mask_idx)& 0x1)) + { + // 修改当前操作的pf状态，恢复其它pf的状态 + if (hp_info.scene_code == FUNCTION_INSERT + && hp_info.function_type == PCIE_FUNC_TYPE_PF + && (hp_info.ep_id - 5) == ep_no + && hp_info.pf_id == pf_no) + { + continue; + } + remove_pci_dev(&hp_req); + DH_LOG_DEBUG(MODULE_FUC_HP, "domain: %x", hp_req.domain); + DH_LOG_DEBUG(MODULE_FUC_HP, "bdf: %x", hp_req.bdf); + } + } + + iounmap(bar_virt_addr); + bar_virt_addr = NULL; + return PCIE_SUCCESS; +} + +int hotplug_device_enable(int enable_flag) +{ + int ret = PCIE_SUCCESS; + struct pci_dev *hp_pdev = NULL; + + hp_pdev = pci_get_device(HP_VENDOR_ID, HP_DEVICE_ID, NULL); + if (IS_ERR_OR_NULL(hp_pdev)) + { + DH_LOG_ERR(MODULE_FUC_HP, "This hp device was not found. Please confirm the BDF\n"); + return PCIE_FAILED; + } + + if (enable_flag == 1) + { + ret = pci_enable_device(hp_pdev); + } + else if (enable_flag == 0) + { + pci_disable_device(hp_pdev); + } + if (ret != 0) + { + DH_LOG_ERR(MODULE_FUC_HP, "pci_enable_device failed: %d\n", ret); + return ret; + } + + return ret; +} + +irqreturn_t func_hp_msix_handler(int irq_no, void *data) +{ + pr_info("irq[%d] has been triggered\n", irq_no); + + return IRQ_WAKE_THREAD; +} + +irqreturn_t irq_handler2(int irq_no, void *data) +{ + pr_info("irq[%d] has been triggered\n", irq_no); + + return IRQ_WAKE_THREAD; +} + +irqreturn_t func_hp_msix_thread(int irq, void *data) +{ + func_hp(); + return IRQ_HANDLED; +} + +irqreturn_t irq_thread2(int irq, void *data) +{ + return IRQ_HANDLED; +} diff --git a/src/net/drivers/pcie/zxdh_pcie/function_hotplug.h b/src/net/drivers/pcie/zxdh_pcie/function_hotplug.h new file mode 100644 index 0000000..3040bf7 --- /dev/null +++ b/src/net/drivers/pcie/zxdh_pcie/function_hotplug.h @@ -0,0 +1,128 @@ +#ifndef _ZXDH_PF_HOT_PLUG_H_ +#define _ZXDH_PF_HOT_PLUG_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#define FUNC_HP_RESULT_SUCC 1 +#define FUNC_HP_RESULT_FAIL 2 + +#define FUNC_HP_SCENE_CODE_START_BIT 21 +#define FUNC_HP_FUNC_TYPE_START_BIT 20 +#define FUNC_HP_EP_ID_START_BIT 16 +#define FUNC_HP_PF_ID_START_BIT 12 +#define FUNC_HP_VF_ID_START_BIT 0 + +#define FUNC_HP_SCENE_CODE_MASK (0x7 << FUNC_HP_SCENE_CODE_START_BIT) +#define FUNC_HP_FUNC_TYPE_MASK (0x1 << FUNC_HP_FUNC_TYPE_START_BIT) +#define FUNC_HP_EP_ID_MASK (0xF << FUNC_HP_EP_ID_START_BIT) +#define FUNC_HP_PF_ID_MASK (0xF << FUNC_HP_PF_ID_START_BIT) +#define FUNC_HP_VF_ID_MASK (0xFFF << FUNC_HP_VF_ID_START_BIT) + +#define SCENE_CODE_OF_FUNC_HP_INFO(hotplug_info) ((hotplug_info & FUNC_HP_SCENE_CODE_MASK) >> FUNC_HP_SCENE_CODE_START_BIT) +#define FUNC_TYPE_OF_FUNC_HP_INFO(hotplug_info) ((hotplug_info & FUNC_HP_FUNC_TYPE_MASK) >> FUNC_HP_FUNC_TYPE_START_BIT) +#define EP_ID_OF_FUNC_HP_INFO(hotplug_info) ((hotplug_info & FUNC_HP_EP_ID_MASK) >> FUNC_HP_EP_ID_START_BIT) +#define PF_ID_OF_FUNC_HP_INFO(hotplug_info) ((hotplug_info & FUNC_HP_PF_ID_MASK) >> FUNC_HP_PF_ID_START_BIT) +#define VF_ID_OF_FUNC_HP_INFO(hotplug_info) ((hotplug_info & FUNC_HP_VF_ID_MASK) >> FUNC_HP_VF_ID_START_BIT) + +#define FUNCTION_HP_TYPE_COUNT 2 +#define MAX_EP_NUMS 4 +#define MAX_PF_NUMS_OF_EP 8 +#define MAX_PF_NUMS (MAX_PF_NUMS_OF_EP * MAX_EP_NUMS) + +#define FUC_HOTPLUG_PF_INIT_FLAG_OFFSET 0x10 +#define FUC_HOTPLUG_PF_STATE_FLAG_OFFSET 0x20 +#define FUC_HOTPLUG_PF_INIT_FLAG 0x450000 + +enum FUC_HOTPLUG_INFO_ { + PCIE_HOTPLUG_START = 1, + PCIE_HOTPLUG_FINISH, +}; + +enum zte_pcie_func_type { + PCIE_FUNC_TYPE_PF = 0, + PCIE_FUNC_TYPE_VF, + PCIE_FUNC_TYPE_NUM +}; + +typedef enum { + FUNCTION_REMOVE = 1, + FUNCTION_INSERT, +} FUNCTION_HP_TYPE; + +struct func_hotplug_info { + unsigned int reserved: 8; + unsigned int scene_code: 3; // 1-热拔；2-热插； + unsigned int function_type: 1; // pf-0;vf-1; + unsigned int ep_id: 4; // 5~9(对应ep0~4) + unsigned int pf_id: 4; // 0~7 + unsigned int vf_id: 12; // 0~127 +}; + +struct func_hotplug_req { + /* hotplug_info + bit[31:24]: reserved: + bit[23:21]: scene_code 1-热拔、2-热插 + bit[20]: function_type 0-PF、1-VF + bit[19:16]: ep_id 范围: 5~9(对应ep0~4) + bit[15:12]: pf_id 范围: 0~7 + bit[11:0]: vf_id 范围: 0~127 + */ + u32 hotplug_info; + u32 domain; + u32 bdf; +}; + +struct func_hotplug_result { + unsigned int cmd; + + /* hotplug_info + bit[31:24]: reserved: + bit[23:21]: scene_code 0-热拔、1-热插 + bit[20]: function_type 0-PF、1-VF + bit[19:16]: ep_id 范围: 5~9(对应ep0~4) + bit[15:12]: pf_id 范围: 0~7 + bit[11:0]: vf_id 范围: 0~127 + */ + u32 hotplug_info; + u32 result; +}; + +struct func_hotplug_state { + u32 pf_state_mask; + u32 domain[4]; + u32 bdf[4]; +}; + +struct zte_dpu_id_info { + char *name; + u16 device_id; + u16 vendor_id; +}; + +struct fuc_hotplug_bar_msg { + unsigned int cmd; + unsigned int fuc_hotplug_info; + unsigned int timeout; + unsigned int cpl_chk; +}; + +int init_pf_hotplug_info(void); +int remove_pci_dev(struct func_hotplug_req *hp_info); +int rescan_pci_dev(struct func_hotplug_req *hp_info); +int vf_bind_unbind(struct func_hotplug_req *hp_req); +int request_msix(void); +int free_msix(void); +int enable_vf(void); +int init_bdf(void); +int init_pf_state(void); +int hotplug_device_enable(int enable_flag); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/net/drivers/pcie/zxdh_pcie/pcie_common.c b/src/net/drivers/pcie/zxdh_pcie/pcie_common.c new file mode 100644 index 0000000..75eae38 --- /dev/null +++ b/src/net/drivers/pcie/zxdh_pcie/pcie_common.c @@ -0,0 +1,153 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pcie_common.h" + +struct pci_dev *zxdh_get_pci_device(u32 domain, u32 bdf) +{ + struct pci_bus *bus = NULL; + struct pci_dev *dev = NULL; + + bus = pci_find_bus(domain, (bdf >> 8)); + if (!bus) + { + DH_LOG_ERR(MODULE_FUC_HP, "Can not find this bus\n"); + return NULL; + } + + while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) + { + if (dev->bus == bus && PCI_SLOT(dev->devfn) == PCI_SLOT(bdf) && PCI_FUNC(dev->devfn) == PCI_FUNC(bdf)) + { + return dev; + } + } + + return NULL; +} + +int fill_domain_bdf_str(const char *token, char *dst_str, const int len) +{ + int ret = PCIE_SUCCESS; + int i = 0; + int j = 0; + + if (strlen(token) < len) + { + for (i = 0; i < (len - strlen(token)); ++i) + { + dst_str[i] = '0'; + } + for (j = i; j < len; ++j) + { + dst_str[j] = token[j - i]; + } + dst_str[j] = 0; + } + else if (strlen(token) > len) + { + DH_LOG_ERR(MODULE_FUC_HP, "error token, size=%ld\n", strlen(token)); + ret = PCIE_FAILED; + } + else + { + memcpy(dst_str, token, strlen(token) + 1); + } + + return ret; +} + +int parse_bdf(char *str) +{ + int ret = PCIE_SUCCESS; + int size = 0; + char *token = NULL; + struct domain_bdf domain_bdf = {0}; + char *tempString = kstrdup(str, GFP_KERNEL); + + memset(&domain_bdf, 0, sizeof(struct domain_bdf)); + + if (tempString == NULL) + { + DH_LOG_ERR(MODULE_FUC_HP, "tempString is NULL\n"); + return PCIE_FAILED; + } + + token = strsep(&tempString, ":"); + if (token == NULL) + { + DH_LOG_ERR(MODULE_FUC_HP, "strsep fail\n"); + goto failed; + } + ret = fill_domain_bdf_str(token, domain_bdf.domain, DOMAIN_LEN); + if (ret != PCIE_SUCCESS) + { + DH_LOG_ERR(MODULE_FUC_HP, "error domain, token=%s\n", token); + goto failed; + } + + token = strsep(&tempString, ":"); + if (token == NULL) + { + DH_LOG_ERR(MODULE_FUC_HP, "strsep fail\n"); + goto failed; + } + ret = fill_domain_bdf_str(token, domain_bdf.bus, BUS_LEN); + if (ret != PCIE_SUCCESS) + { + DH_LOG_ERR(MODULE_FUC_HP, "rror bus\n"); + goto failed; + } + + token = strsep(&tempString, "."); + if (token == NULL) + { + DH_LOG_ERR(MODULE_FUC_HP, "strsep fail\n"); + goto failed; + } + ret = fill_domain_bdf_str(token, domain_bdf.device, DEVICE_LEN); + if (ret != PCIE_SUCCESS) + { + DH_LOG_ERR(MODULE_FUC_HP, "error device\n"); + goto failed; + } + + token = strsep(&tempString, "."); + if (token == NULL) + { + DH_LOG_ERR(MODULE_FUC_HP, "strsep fail\n"); + goto failed; + } + ret = fill_domain_bdf_str(token, domain_bdf.func, FUNC_LEN); + if (ret != PCIE_SUCCESS) + { + DH_LOG_ERR(MODULE_FUC_HP,"error func\n"); + goto failed; + } + + size = snprintf(str, FILE_PATH_LEN, "%s:%s:%s.%s", domain_bdf.domain, domain_bdf.bus, domain_bdf.device, domain_bdf.func); + if (size >= FILE_PATH_LEN) + { + str[FILE_PATH_LEN - 1] = '\0'; + } + + kfree(tempString); + tempString = NULL; + + return PCIE_SUCCESS; + +failed: + kfree(tempString); + tempString = NULL; + DH_LOG_ERR(MODULE_FUC_HP, "Input format error, refer to '[domain]:[bus_no]:[dev_no].[func_no]'\n"); + return PCIE_FAILED; +} diff --git a/src/net/drivers/pcie/zxdh_pcie/pcie_common.h b/src/net/drivers/pcie/zxdh_pcie/pcie_common.h new file mode 100644 index 0000000..d4abaf4 --- /dev/null +++ b/src/net/drivers/pcie/zxdh_pcie/pcie_common.h @@ -0,0 +1,53 @@ +#ifndef _ZXDH_PCIE_COMMON_H_ +#define _ZXDH_PCIE_COMMON_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include +#include +#include +#include + +#define PCIE_SUCCESS 0 +#define PCIE_FAILED -1 + +#define KERNEL_VFIO_VFIO_TEST_NAME "/dev/vfio/vfio" +#define PCI_DEVICES_DIR "/sys/bus/pci/devices" +#define SYS_BUS_PCI_DIR "/sys/bus/pci" +#define PCI_PHYSFN_DRV_PATH "physfn/driver" +#define FILE_PATH_LEN 100 + +#define DOMAIN_LEN 4 +#define BUS_LEN 2 +#define DEVICE_LEN 2 +#define FUNC_LEN 1 + +#define BDF_NO_BUS_NO_MASK (0xFF << 8) +#define BDF_NO_DEV_NO_MASK (0x1F << 3) +#define BDF_NO_FUNC_NO_MASK (0x7 << 0) + +#define BDF_F_START_BIT 0 +#define BDF_D_START_BIT 3 +#define BDF_B_START_BIT 8 + +struct domain_bdf { + char domain[DOMAIN_LEN + 1]; + char bus[BUS_LEN + 1]; + char device[DEVICE_LEN + 1]; + char func[FUNC_LEN + 1]; +}; + +struct pci_dev *zxdh_get_pci_device(u32 domain, u32 bdf); +int fill_domain_bdf_str(const char *token, char *dst_str, const int len); +int parse_bdf(char *str); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/net/drivers/pcie/zxdh_pcie/pcie_msix.c b/src/net/drivers/pcie/zxdh_pcie/pcie_msix.c new file mode 100644 index 0000000..0aa5fbb --- /dev/null +++ b/src/net/drivers/pcie/zxdh_pcie/pcie_msix.c @@ -0,0 +1,88 @@ +#include +#include +#include +#include +#include +#include + +#include "bar_msg.h" +#include "pcie_msix.h" +#include "function_hotplug.h" +#include "pcie_common.h" + +extern irqreturn_t func_hp_msix_handler(int irq_no, void *data); +extern irqreturn_t irq_handler2(int irq_no, void *data); +extern irqreturn_t func_hp_msix_thread(int irq_no, void *data); +extern irqreturn_t irq_thread2(int irq_no, void *data); + +static struct msix_handler_info msix_handler_info_arr[] = { + /* irq_id, irq_handler irq_thread irq_name */ + {IRQ_NO_INIT_VALUE, func_hp_msix_handler, func_hp_msix_thread, "function_hotplug_msix"}, + {IRQ_NO_INIT_VALUE, irq_handler2, irq_thread2, "irq_thread2"}, +}; + +int request_msix(void) +{ + int ret = 0; + int i = 0; + int msix_nums = 0; + struct pci_dev *pdev = NULL; + + pdev = pci_get_device(HP_VENDOR_ID, HP_DEVICE_ID, pdev); + if (IS_ERR_OR_NULL(pdev)) + { + DH_LOG_ERR(MODULE_FUC_HP, "pci get device fail! deviceid=0x%x, vendorid=0x%x\n", HP_DEVICE_ID, HP_VENDOR_ID); + return -EINVAL; + } + + if (pci_enable_device(pdev)) + { + DH_LOG_ERR(MODULE_FUC_HP, "enbale dev failed\n"); + } + + msix_nums = sizeof(msix_handler_info_arr) / sizeof(struct msix_handler_info); + ret = pci_alloc_irq_vectors(pdev, msix_nums, msix_nums, PCI_IRQ_MSIX); + if (ret < 0) + { + DH_LOG_ERR(MODULE_FUC_HP, "Can not alloc msix irq vector msix_nums=%d, ret=%d\n", msix_nums, ret); + return ret; + } + + for (i = 0; i < msix_nums; ++i) + { + msix_handler_info_arr[i].irq_id = i; + + ret = pci_request_irq(pdev, i, msix_handler_info_arr[i].irq_handler_func, msix_handler_info_arr[i].irq_thread_func, + &msix_handler_info_arr[i].irq_id, "%s%d", msix_handler_info_arr[i].irq_name, i); + if (ret) + { + pci_free_irq_vectors(pdev); + DH_LOG_ERR(MODULE_FUC_HP, "request msix[%d] failed --> %d\n", i, ret); + } + } + + return ret; +} + +int free_msix(void) +{ + int msix_nums = 0; + int i = 0; + struct pci_dev *pdev = NULL; + + pdev = pci_get_device(HP_VENDOR_ID, HP_DEVICE_ID, pdev); + if (IS_ERR_OR_NULL(pdev)) + { + DH_LOG_WARNING(MODULE_FUC_HP, "pdev has released\n"); + return 0; + } + + msix_nums = sizeof(msix_handler_info_arr) / sizeof(struct msix_handler_info); + for (i = 0; i < msix_nums; ++i) + { + pci_free_irq(pdev, msix_handler_info_arr[i].irq_id, &msix_handler_info_arr[i].irq_id); + } + pci_free_irq_vectors(pdev); + + return 0; +} diff --git a/src/net/drivers/pcie/zxdh_pcie/pcie_msix.h b/src/net/drivers/pcie/zxdh_pcie/pcie_msix.h new file mode 100644 index 0000000..1ab4d87 --- /dev/null +++ b/src/net/drivers/pcie/zxdh_pcie/pcie_msix.h @@ -0,0 +1,29 @@ +#ifndef _ZXDH_PF_HOT_PLUG_H_ +#define _ZXDH_PF_HOT_PLUG_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include + +typedef irqreturn_t (*irq_handler)(int irq_no, void *data); +typedef irqreturn_t (*irq_thread)(int irq, void *data); + +#define IRQ_NO_INIT_VALUE (-1) +#define MSIX_NAME_LEN 30 +struct msix_handler_info { + int irq_id; + irq_handler irq_handler_func; + irq_thread irq_thread_func; + char irq_name[MSIX_NAME_LEN]; +}; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/net/drivers/pcie/zxdh_pcie/zxdh_pcie.c b/src/net/drivers/pcie/zxdh_pcie/zxdh_pcie.c new file mode 100644 index 0000000..7b590db --- /dev/null +++ b/src/net/drivers/pcie/zxdh_pcie/zxdh_pcie.c @@ -0,0 +1,167 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "bar_msg.h" +#include "function_hotplug.h" +#include "pcie_common.h" + +#ifdef DRIVER_VERSION_VAL + #define DRV_VERSION DRIVER_VERSION_VAL +#else + #define DRV_VERSION "1.0-1" +#endif + +int zxdh_pcie_init(void) +{ + int ret = 0; + + ret = init_pf_hotplug_info(); + if (ret != 0) + { + DH_LOG_ERR(MODULE_FUC_HP, "int pf hot plug info failed.\n"); + return ret; + } + + + ret = init_pf_state(); + if (ret != 0) + { + DH_LOG_ERR(MODULE_FUC_HP, "init_pf_state failed\n"); + return ret; + } + + ret = enable_vf(); + if (ret != 0) + { + DH_LOG_ERR(MODULE_FUC_HP, "enable_vf failed\n"); + return ret; + } + + DH_LOG_INFO(MODULE_FUC_HP, "zxdh pf hotplug module init success.\n"); + return ret; +} + +void zxdh_pcie_exit(void) +{ + free_msix(); + DH_LOG_INFO(MODULE_FUC_HP, "zxdh pcie remove success.\n"); +} + +static const struct pci_device_id dh_hpf_pci_table[] = { + { PCI_DEVICE(HP_VENDOR_ID, HP_DEVICE_ID), 0 }, + { 0, } +}; + +MODULE_DEVICE_TABLE(pci, dh_hpf_pci_table); + +static int32_t dh_hpf_probe(struct pci_dev *pdev, const struct pci_device_id *id) +{ + int32_t ret = 0; + + ret = init_bdf(); + if (ret != 0) + { + DH_LOG_ERR(MODULE_FUC_HP, "init_bdf failed.\n"); + } + + ret = request_msix(); + if(ret != 0) + { + DH_LOG_ERR(MODULE_FUC_HP, "request_msix failed\n"); + return ret; + } + DH_LOG_INFO(MODULE_FUC_HP,"hpf driver probe completed\n"); + return 0; +} + +static void dh_hpf_remove(struct pci_dev *pdev) +{ + zxdh_pcie_exit(); + DH_LOG_INFO(MODULE_FUC_HP,"hpf driver remove completed\n"); +} + + +static int32_t dh_hpf_suspend(struct pci_dev *pdev, pm_message_t state) +{ + return 0; +} + +static int32_t dh_hpf_resume(struct pci_dev *pdev) +{ + return 0; +} + +static void dh_hpf_shutdown(struct pci_dev *pdev) +{ + dh_hpf_remove(pdev); +} + +static pci_ers_result_t dh_pci_err_detected(struct pci_dev *pdev, + pci_channel_state_t state) +{ + return PCI_ERS_RESULT_NONE; +} + +static pci_ers_result_t dh_hpf_pci_slot_reset(struct pci_dev *pdev) +{ + return PCI_ERS_RESULT_NONE; +} + +static void dh_hpf_pci_resume(struct pci_dev *pdev) +{ + +} + +static const struct pci_error_handlers dh_hpf_err_handler = { + .error_detected = dh_pci_err_detected, + .slot_reset = dh_hpf_pci_slot_reset, + .resume = dh_hpf_pci_resume +}; + +static struct pci_driver dh_hpf_driver = { + .name = KBUILD_MODNAME, + .id_table = dh_hpf_pci_table, + .probe = dh_hpf_probe, + .remove = dh_hpf_remove, + .suspend = dh_hpf_suspend, + .resume = dh_hpf_resume, + .shutdown = dh_hpf_shutdown, + .err_handler = &dh_hpf_err_handler, +}; + +static int32_t __init init(void) +{ + int32_t err = 0; + + err = pci_register_driver(&dh_hpf_driver); + if (err != 0) + { + DH_LOG_ERR(MODULE_FUC_HP,"pci_register_driver failed: %d\n", err); + return err; + } + + zxdh_pcie_init(); + + DH_LOG_INFO(MODULE_FUC_HP,"zxdh_hpf driver init success\n"); + return err; +} + +static void __exit cleanup(void) +{ + pci_unregister_driver(&dh_hpf_driver); + DH_LOG_INFO(MODULE_FUC_HP,"zxdh_hpf driver remove success\n"); +} + +module_init(init); +module_exit(cleanup); +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("ZTE ZXDH HP"); +MODULE_VERSION(DRV_VERSION); diff --git a/src/net/include/linux/dinghai/auxiliary_bus.h b/src/net/include/linux/dinghai/auxiliary_bus.h new file mode 100755 index 0000000..6bb6509 --- /dev/null +++ b/src/net/include/linux/dinghai/auxiliary_bus.h @@ -0,0 +1,153 @@ + +#ifndef _AUXILIARY_BUS_H_ +#define _AUXILIARY_BUS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + + +#define ZXDH_AUXILIARY_NAME_SIZE 32 +#define ZXDH_AUXILIARY_MODULE_PREFIX "zxdh_auxiliary:" + +struct zxdh_auxiliary_device_id +{ + char name[ZXDH_AUXILIARY_NAME_SIZE]; + kernel_ulong_t driver_data; +}; + +struct zxdh_auxiliary_device { + struct device dev; + const char *name; + uint32_t id; +}; + +/** + * struct zxdh_auxiliary_driver - Definition of an auxiliary bus driver + * @probe: Called when a matching device is added to the bus. + * @remove: Called when device is removed from the bus. + * @shutdown: Called at shut-down time to quiesce the device. + * @suspend: Called to put the device to sleep mode. Usually to a power state. + * @resume: Called to bring a device from sleep mode. + * @name: Driver name. + * @driver: Core driver structure. + * @id_table: Table of devices this driver should match on the bus. + * + * Auxiliary drivers follow the standard driver model convention, where + * discovery/enumeration is handled by the core, and drivers provide probe() + * and remove() methods. They support power management and shutdown + * notifications using the standard conventions. + * + * Auxiliary drivers register themselves with the bus by calling + * zxdh_auxiliary_driver_register(). The id_table contains the match_names of + * auxiliary devices that a driver can bind with. + * + * .. code-block:: c + * + * static const struct zxdh_auxiliary_device_id my_auxiliary_id_table[] = { + * { .name = "foo_mod.foo_dev" }, + * {}, + * }; + * + * MODULE_DEVICE_TABLE(zxdh_auxiliary, my_auxiliary_id_table); + * + * struct zxdh_auxiliary_driver my_drv = { + * .name = "myauxiliarydrv", + * .id_table = my_auxiliary_id_table, + * .probe = my_drv_probe, + * .remove = my_drv_remove + * }; + */ +struct zxdh_auxiliary_driver { + int32_t (*probe)(struct zxdh_auxiliary_device *auxdev, const struct zxdh_auxiliary_device_id *id); + int32_t (*remove)(struct zxdh_auxiliary_device *auxdev); + void (*shutdown)(struct zxdh_auxiliary_device *auxdev); + int32_t (*suspend)(struct zxdh_auxiliary_device *auxdev, pm_message_t state); + int32_t (*resume)(struct zxdh_auxiliary_device *auxdev); + const char *name; + struct device_driver driver; + const struct zxdh_auxiliary_device_id *id_table; +}; + +static inline void *zxdh_auxiliary_get_drvdata(struct zxdh_auxiliary_device *auxdev) +{ + return dev_get_drvdata(&auxdev->dev); +} + +static inline void zxdh_auxiliary_set_drvdata(struct zxdh_auxiliary_device *auxdev, void *data) +{ + dev_set_drvdata(&auxdev->dev, data); +} + +static inline struct zxdh_auxiliary_device *zxdh_to_auxiliary_dev(struct device *dev) +{ + return container_of(dev, struct zxdh_auxiliary_device, dev); +} + +static inline struct zxdh_auxiliary_driver *zxdh_to_auxiliary_drv(struct device_driver *drv) +{ + return container_of(drv, struct zxdh_auxiliary_driver, driver); +} + +int32_t zxdh_auxiliary_device_init(struct zxdh_auxiliary_device *auxdev); +int32_t zxdh_aux_dev_add(struct zxdh_auxiliary_device *auxdev, const char *modname); +#define zxdh_auxiliary_device_add(auxdev) zxdh_aux_dev_add(auxdev, KBUILD_MODNAME) + +static inline void zxdh_auxiliary_device_uninit(struct zxdh_auxiliary_device *auxdev) +{ + put_device(&auxdev->dev); +} + +static inline void zxdh_auxiliary_device_delete(struct zxdh_auxiliary_device *auxdev) +{ + device_del(&auxdev->dev); +} + +int32_t zxdh_aux_drv_register(struct zxdh_auxiliary_driver *auxdrv, struct module *owner, + const char *modname); +#define zxdh_auxiliary_driver_register(auxdrv) \ + zxdh_aux_drv_register(auxdrv, THIS_MODULE, KBUILD_MODNAME) + +void zxdh_auxiliary_driver_unregister(struct zxdh_auxiliary_driver *auxdrv); + +/** + * module_auxiliary_driver() - Helper macro for registering an auxiliary driver + * @__auxiliary_driver: auxiliary driver struct + * + * Helper macro for auxiliary drivers which do not do anything special in + * module init/exit. This eliminates a lot of boilerplate. Each module may only + * use this macro once, and calling it replaces module_init() and module_exit() + * + * .. code-block:: c + * + * module_auxiliary_driver(my_drv); + */ +#define module_auxiliary_driver(__auxiliary_driver) \ + module_driver(__auxiliary_driver, zxdh_auxiliary_driver_register, zxdh_auxiliary_driver_unregister) + +#ifdef HAVE_LINUX_DEVICE_BUS_H +struct zxdh_auxiliary_device *zxdh_auxiliary_find_device(struct device *start, + const void *data, + int32_t (*match)(struct device *dev, const void *data)); +#else +#ifdef HAVE_BUS_FIND_DEVICE_GET_CONST +struct zxdh_auxiliary_device * +zxdh_auxiliary_find_device(struct device *start, + const void *data, + int32_t (*match)(struct device *dev, const void *data)); +#else +struct zxdh_auxiliary_device * +zxdh_auxiliary_find_device(struct device *start, + void *data, + int32_t (*match)(struct device *dev, void *data)); +#endif /* HAVE_BUS_FIND_DEVICE_GET_CONST */ +#endif /* HAVE_LINUX_DEVICE_BUS_H */ + +#ifdef __cplusplus +} +#endif + +#endif /* _AUXILIARY_BUS_H_ */ diff --git a/src/net/include/linux/dinghai/device.h b/src/net/include/linux/dinghai/device.h new file mode 100755 index 0000000..651a5ea --- /dev/null +++ b/src/net/include/linux/dinghai/device.h @@ -0,0 +1,155 @@ +#ifndef DINGHAI_DEVICE_H +#define DINGHAI_DEVICE_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* helper macros */ +#define __dh_nullp(typ) ((struct dh_ifc_##typ##_bits *)0) +#define __dh_bit_sz(typ, fld) sizeof(__dh_nullp(typ)->fld) +#define __dh_bit_off(typ, fld) (offsetof(struct dh_ifc_##typ##_bits, fld)) +#define __dh_16_off(typ, fld) (__dh_bit_off(typ, fld) / 16) +#define __dh_dw_off(typ, fld) (__dh_bit_off(typ, fld) / 32) +#define __dh_64_off(typ, fld) (__dh_bit_off(typ, fld) / 64) +#define __dh_16_bit_off(typ, fld) (16 - __dh_bit_sz(typ, fld) - (__dh_bit_off(typ, fld) & 0xf)) +#define __dh_dw_bit_off(typ, fld) (32 - __dh_bit_sz(typ, fld) - (__dh_bit_off(typ, fld) & 0x1f)) +#define __dh_mask(typ, fld) ((u32)((1ull << __dh_bit_sz(typ, fld)) - 1)) +#define __dh_dw_mask(typ, fld) (__dh_mask(typ, fld) << __dh_dw_bit_off(typ, fld)) +#define __dh_mask16(typ, fld) ((u16)((1ull << __dh_bit_sz(typ, fld)) - 1)) +#define __dh_16_mask(typ, fld) (__dh_mask16(typ, fld) << __dh_16_bit_off(typ, fld)) +#define __dh_st_sz_bits(typ) sizeof(struct dh_ifc_##typ##_bits) + +#define DH_FLD_SZ_BYTES(typ, fld) (__dh_bit_sz(typ, fld) / 8) +#define DH_ST_SZ_BYTES(typ) (sizeof(struct dh_ifc_##typ##_bits) / 8) +#define DH_ST_SZ_DW(typ) (sizeof(struct dh_ifc_##typ##_bits) / 32) +#define DH_ST_SZ_QW(typ) (sizeof(struct dh_ifc_##typ##_bits) / 64) +#define DH_UN_SZ_BYTES(typ) (sizeof(union dh_ifc_##typ##_bits) / 8) +#define DH_UN_SZ_DW(typ) (sizeof(union dh_ifc_##typ##_bits) / 32) +#define DH_BYTE_OFF(typ, fld) (__dh_bit_off(typ, fld) / 8) +#define DH_ADDR_OF(typ, p, fld) ((void *)((uint8_t *)(p) + DH_BYTE_OFF(typ, fld))) + +/* insert a value to a struct */ +#define DH_SET(typ, p, fld, v) do { \ + u32 _v = v; \ + BUILD_BUG_ON(__dh_st_sz_bits(typ) % 32); \ + *((__be32 *)(p) + __dh_dw_off(typ, fld)) = \ + cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __dh_dw_off(typ, fld))) & \ + (~__dh_dw_mask(typ, fld))) | (((_v) & __dh_mask(typ, fld)) \ + << __dh_dw_bit_off(typ, fld))); \ +} while (0) + +#define DH_ARRAY_SET(typ, p, fld, idx, v) do { \ + BUILD_BUG_ON(__dh_bit_off(typ, fld) % 32); \ + DH_SET(typ, p, fld[idx], v); \ +} while (0) + +#define DH_SET_TO_ONES(typ, p, fld) do { \ + BUILD_BUG_ON(__dh_st_sz_bits(typ) % 32); \ + *((__be32 *)(p) + __dh_dw_off(typ, fld)) = \ + cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __dh_dw_off(typ, fld))) & \ + (~__dh_dw_mask(typ, fld))) | ((__dh_mask(typ, fld)) \ + << __dh_dw_bit_off(typ, fld))); \ +} while (0) + +#define DH_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) + \ +__dh_dw_off(typ, fld))) >> __dh_dw_bit_off(typ, fld)) & \ +__dh_mask(typ, fld)) + +#define DH_GET_PR(typ, p, fld) ({ \ + u32 ___t = DH_GET(typ, p, fld); \ + pr_debug(#fld " = 0x%x\n", ___t); \ + ___t; \ +}) + +#define __DH_SET64(typ, p, fld, v) do { \ + BUILD_BUG_ON(__dh_bit_sz(typ, fld) != 64); \ + *((__be64 *)(p) + __dh_64_off(typ, fld)) = cpu_to_be64(v); \ +} while (0) + +#define DH_SET64(typ, p, fld, v) do { \ + BUILD_BUG_ON(__dh_bit_off(typ, fld) % 64); \ + __DH_SET64(typ, p, fld, v); \ +} while (0) + +#define DH_ARRAY_SET64(typ, p, fld, idx, v) do { \ + BUILD_BUG_ON(__dh_bit_off(typ, fld) % 64); \ + __DH_SET64(typ, p, fld[idx], v); \ +} while (0) + +#define DH_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __dh_64_off(typ, fld))) + +#define DH_GET64_PR(typ, p, fld) ({ \ + u64 ___t = DH_GET64(typ, p, fld); \ + pr_debug(#fld " = 0x%llx\n", ___t); \ + ___t; \ +}) + +#define DH_GET16(typ, p, fld) ((be16_to_cpu(*((__be16 *)(p) + \ +__dh_16_off(typ, fld))) >> __dh_16_bit_off(typ, fld)) & \ +__dh_mask16(typ, fld)) + +#define DH_SET16(typ, p, fld, v) do { \ + u16 _v = v; \ + BUILD_BUG_ON(__dh_st_sz_bits(typ) % 16); \ + *((__be16 *)(p) + __dh_16_off(typ, fld)) = \ + cpu_to_be16((be16_to_cpu(*((__be16 *)(p) + __dh_16_off(typ, fld))) & \ + (~__dh_16_mask(typ, fld))) | (((_v) & __dh_mask16(typ, fld)) \ + << __dh_16_bit_off(typ, fld))); \ +} while (0) + +/* Big endian getters */ +#define DH_GET64_BE(typ, p, fld) (*((__be64 *)(p) + \ + __dh_64_off(typ, fld))) + +#define DH_GET_BE(type_t, typ, p, fld) ({ \ + type_t tmp; \ + switch (sizeof(tmp)) { \ + case sizeof(u8): \ + tmp = (__force type_t)DH_GET(typ, p, fld); \ + break; \ + case sizeof(u16): \ + tmp = (__force type_t)cpu_to_be16(DH_GET(typ, p, fld)); \ + break; \ + case sizeof(u32): \ + tmp = (__force type_t)cpu_to_be32(DH_GET(typ, p, fld)); \ + break; \ + case sizeof(u64): \ + tmp = (__force type_t)DH_GET64_BE(typ, p, fld); \ + break; \ + } \ + tmp; \ + }) + +enum dh_cap_type { + DH_CAP_GENERAL = 0, +}; +/* GET Dev Caps macros */ +#define DH_CAP_GEN(mdev, cap) \ + DH_GET(cmd_hca_cap, mdev->caps.hca[DH_CAP_GENERAL]->cur, cap) + +#define DH_CAP_GEN_64(mdev, cap) \ + DH_GET64(cmd_hca_cap, mdev->caps.hca[DH_CAP_GENERAL]->cur, cap) + +#define DH_CAP_GEN_MAX(mdev, cap) \ + DH_GET(cmd_hca_cap, mdev->caps.hca[DH_CAP_GENERAL]->max, cap) + + + + +enum dh_event_queue_type { + DH_EVENT_QUEUE_TYPE_SAMPLE, + DH_EVENT_QUEUE_TYPE_RISCV +}; + +struct dh_mpf_priv { + +}; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/net/include/linux/dinghai/devlink.h b/src/net/include/linux/dinghai/devlink.h new file mode 100755 index 0000000..1801a58 --- /dev/null +++ b/src/net/include/linux/dinghai/devlink.h @@ -0,0 +1,32 @@ +#ifndef __ZXDH_DEVLINK_H__ +#define __ZXDH_DEVLINK_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +struct devlink *zxdh_devlink_alloc(struct device *dev, struct devlink_ops *dh_devlink_ops, size_t priv_size); +void zxdh_devlink_free(struct devlink *devlink); + +#ifdef HAVE_DEVLINK_REGISTER_GET_1_PARAMS +int32_t zxdh_devlink_register(struct devlink *devlink); +#else +int32_t zxdh_devlink_register(struct devlink *devlink, struct device *dev); +#endif + +void zxdh_devlink_unregister(struct devlink *devlink); + +static inline struct net *dh_core_net(struct dh_core_dev *dev) +{ + return devlink_net(priv_to_devlink(dev)); +} + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/src/net/include/linux/dinghai/dh_cmd.h b/src/net/include/linux/dinghai/dh_cmd.h new file mode 100644 index 0000000..29779fc --- /dev/null +++ b/src/net/include/linux/dinghai/dh_cmd.h @@ -0,0 +1,266 @@ +#ifndef _ZXDH_MSG_CHAN_PUB_H_ +#define _ZXDH_MSG_CHAN_PUB_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + + +#define INVALID_NUM 0xff +#define ZXDH_MPF_PCIEID 0x800 +#define ZXDH_NET_ACK_OK 0 +#define RISCV_MAC_OK 0xaa +#define BAR_MSG_REPS_OK 0xff +#define COMMON_TBL_OK 0xaa +#define RISCV_DEBUG_OK 0xaa +#define PCIEID_PF_ID_MASK (0x0700) +#define PCIEID_PF_ID_OFFSET (8) + +#define FIND_PF_PCIE_ID(value) ((value & 0xff00) | BIT(11)) +#define FIND_VF_PCIE_ID(pf_pcie_id, vf_id) ((pf_pcie_id & (~BIT(11))) | (vf_id)) +#define FIND_PF_ID(pf_pcie_id) ((pf_pcie_id & PCIEID_PF_ID_MASK) >> PCIEID_PF_ID_OFFSET) +#define GET_FUNC_NO(pf_no, vf_idx) ((pf_no & 0xF) | ((vf_idx & 0xFF) << 8)) + +#define PFVF_FLAG_OFFSET 11 // 用于判断pcie_id的第11位为0或1 + +typedef enum +{ + MODULE_DBG = 0, /* 中断测试*/ + MODULE_TBL, /* 资源表交互*/ + MODULE_MSIX, /* Msix配置*/ + MODULE_SDA, /* Sda消息*/ + MODULE_RDMA, /* Rdma调试*/ + MODULE_DEMO, /* 通路测试*/ + MODULE_SMMU, /* Smmu调试*/ + MODULE_MAC, /* MAC相关*/ + MODULE_VDPA, /* vdpa热迁移*/ + MODULE_VQM, /* vqm消息*/ + MODULE_MSGQ, + MODULE_VPORT_GET, /* 获取vport接口*/ + MODULE_BDF_GET, /* 获取bdf接口*/ + MODULE_RISC_READY, /* risc ready信号*/ + MODULE_REVERSE, /* 字节流取反*/ + MODULE_NVME, /* NVME调试*/ + MODULE_NPSDK, /* Np配表*/ + MODULE_TOD, /* UART通信*/ + MODULE_VF_BAR_MSG_TO_PF, /* VF发送给PF的消息 */ + MODULE_PF_BAR_MSG_TO_VF, /* PF发送给VF的消息 */ + MODULE_DEBUG = 20, /* 调用debug接口 */ + MODULE_PPS = 23, /*pps中断相关消息*/ + MODULE_VIRTIO = 25, + MODULE_FLASH = 32, /* 读取flash信息 */ + MODULE_OFFSET_GET = 33, + MODULE_CFG_MAC = 34, + MODULE_PHYPORT_QUERY = 37, /* BOND 获取phyport*/ + MODULE_DHTOOL = 39, /*dhtool，riscv发送给AUX层的消息，将其转发给user*/ + MODULE_RESET_MSG = 40, /* host复位消息的ID号 */ + MODULE_PF_TIMER_TO_RISC_MSG = 41, /* server rsicv time */ + MODULE_LOGIN_CTRL = 43, /* 控制riscv上sshd守护进程开启和关闭*/ + MODULE_PCIE_RES_QUERY = 52, /* pcie资源查询*/ + MSG_MODULE_NUM = 100, +} MSG_MODULE_ID; + + +/* 消息端*/ +typedef enum BAR_DRIVER_TYPE +{ + MSG_CHAN_END_MPF = 0, + MSG_CHAN_END_PF, + MSG_CHAN_END_VF, + MSG_CHAN_END_RISC, + MSG_CHAN_END_ERR, +} BAR_DRIVER_TYPE; + +#define BDF_ECAM(bus, devid, func) ((bus & 0xff) << 8) | (func & 0x07) | ((devid & 0x1f) << 3) + +/* bar通道错误码*/ +typedef enum BAR_MSG_RTN +{ + BAR_MSG_OK = 0, + BAR_MSG_ERR_NULL, /* 空指针*/ + BAR_MSG_ERR_TYPE, /* 消息类型异常 */ + BAR_MSG_ERR_MODULE , /* 模块ID异常 */ + BAR_MSG_ERR_BODY_NULL, /* 消息体异常 */ + BAR_MSG_ERR_LEN, /* 消息长度异常 */ + BAR_MSG_ERR_TIME_OUT, /* 消息发送超长 */ + BAR_MSG_ERR_NOT_READY, /* 消息发送条件异常，BUF不可以用*/ + BAR_MEG_ERR_NULL_FUNC, /* 空的接收处理函数指针*/ + BAR_MSG_ERR_REPEAT_REGISTER, /* 模块重复注册*/ + BAR_MSG_ERR_UNGISTER, /* 重复解注册*/ + BAR_MSG_ERR_NULL_PARA, /* 发送接口参数界结构体指针为空*/ + BAR_MSG_ERR_REPSBUFF_LEN, /* reps_buff的长度太短*/ + BAR_MSG_ERR_MODULE_NOEXIST, /*查找不到该模块对应的消息处理函数*/ + BAR_MSG_ERR_VIRTADDR_NULL, /*发送接口传入参数中的虚拟地址为空*/ + BAR_MSG_ERR_REPLY, /**< seq_id匹配失败>**/ + BAR_MSG_ERR_MSGID, /**< seq_id申请失败>**/ + BAR_MSG_ERR_MPF_NOT_SCANED, /**< MPF通道不可用>**/ + BAR_MSG_ERR_USR_RET_ERR, /**< 处理函数返回值错误>**/ + BAR_MSG_ERR_ERR_PCIEID, /**< pcieID错误>**/ + BAR_MSG_ERR_NOT_MATCH, +} BAR_MSG_RTN; + +enum pciebar_layout_type +{ + URI_VQM = 0, + URI_SPINLOCK = 1, + URI_FWCAP = 2, + URI_FWSHR = 3, + URI_DRS_SEC = 4, + URI_RSV = 5, + URI_CTRLCH = 6, + URI_1588 = 7, + URI_QBV = 8, + URI_MACPCS = 9, + URI_RDMA = 10, +/* DEBUG PF */ + URI_MNP = 11, + URI_MSPM = 12, + URI_MVQM = 13, + URI_MDPI = 14, + URI_NP = 15, +/* END DEBUG PF */ + URI_MAX, +}; + +typedef enum +{ + BAR_MSG_MSIX_FROM_VF = 0, + BAR_MSG_MSIX_FROM_MPF, + BAR_MSG_MSIX_FROM_RISCV, + BAR_MSG_MSIX_NUM_MAX +} bar_msg_msix_irq_type; + +/* msix消息参数结构体*/ +struct msix_para +{ + uint16_t vector_risc; + uint16_t vector_pfvf; + uint16_t vector_mpf; + uint16_t driver_type; + uint16_t pcie_id; + struct pci_dev *pdev; + uint64_t virt_addr; +}; + +struct bar_offset_params +{ + uint64_t virt_addr; + uint16_t pcie_id; + uint16_t type; +}; +struct bar_offset_res +{ + uint32_t bar_offset; + uint32_t bar_length; +}; + +struct zxdh_pci_bar_msg +{ + uint64_t virt_addr; /**< 4k空间地址, 若src为MPF该参数不生效>**/ + void *payload_addr; /**< 消息净荷地址>**/ + uint16_t payload_len; /**< 消息净荷长度>**/ + uint16_t emec; /**< 消息紧急类型>**/ + uint16_t src; /**< 消息发送源，参考BAR_DRIVER_TYPE>**/ + uint16_t dst; /**< 消息接收者，参考BAR_DRIVER_TYPE>**/ + uint32_t event_id; /**< 事件id>**/ + uint16_t src_pcieid; /**< 源 pcie_id>**/ + uint16_t dst_pcieid; /**< 目的pcie_id>**/ +}; + +struct link_info_struct +{ + uint32_t speed; + uint32_t autoneg_enable; + uint32_t supported_speed_modes; + uint32_t advertising_speed_modes; + uint8_t duplex; +}; + +struct zxdh_msg_recviver_mem +{ + void *recv_buffer; /**< 消息接收缓存>**/ + uint16_t buffer_len; /**< 消息缓存长度>**/ +}; + +/** + * zxdh_bar_chan_msg_recv_callback - 消息处理函数 + * @pay_load: 消息内容 + * @len: 消息长度 + * @reps_buffer: 回复消息 + * @reps_len: 回复消息长度 + * @dev: 私有数据 + */ +typedef int (*zxdh_bar_chan_msg_recv_callback)(void *pay_load, uint16_t len, void *reps_buffer, uint16_t *reps_len, void *dev); + +/** + * zxdh_bar_chan_sync_msg_send - 通过PCIE BAR空间发送同步消息 + * @in: 消息发送信息 + * @result: 消息结果反馈 + * @return: 0 成功，其他失败 + */ +int zxdh_bar_chan_sync_msg_send(struct zxdh_pci_bar_msg *in, struct zxdh_msg_recviver_mem *result); + +/** + * zxdh_bar_chan_msg_recv_register - PCIE BAR空间消息方式，注册消息接收回调 + * @event_id: 注册模块id + * @callback: 模块实现的接收处理函数指针 + * @return: 0 成功，其他失败 + * 在驱动初始化时调用 + */ +int zxdh_bar_chan_msg_recv_register(uint8_t event_id, zxdh_bar_chan_msg_recv_callback callback); + +/** + * zxdh_bar_chan_msg_recv_unregister - PCIE BAR空间消息方式，解注册消息接收回调 + * @event_id: 内核PCIE设备地址 + * @return:0 成功，其他失败 + * 在驱动卸载时需要调用 + */ +int zxdh_bar_chan_msg_recv_unregister(uint8_t event_id); + +/** + * zxdh_bar_enable_chan - 驱动使能通道函数 + * @_msix_para: msix中断配置信息 + * @pcie_id: 查询到的pcie_id + * @vport: 查询到的vport + * @return: 0 成功，其他失败 + */ +int zxdh_bar_enable_chan(struct msix_para *_msix_para, uint16_t *vport); + +/** + * zxdh_get_bar_offset - 获取指定模块的偏移值 + * @bar_offset_params: 输入参数 + * @bar_offset_res: 模块偏移和长度 + */ +int zxdh_get_bar_offset(struct bar_offset_params *paras, struct bar_offset_res *res); + +int32_t zxdh_send_command(uint64_t vaddr, uint16_t pcie_id, uint16_t module_id, \ + void *msg, void *ack ,bool is_sync_msg); + +int zxdh_bar_msg_chan_init(void); +int zxdh_bar_msg_chan_remove(void); + +/** + * zxdh_bar_reset_valid - 重置risc发来消息的valid + * @subchan_addr: 4k首地址 + * @return: 0 成功，其他失败 + */ +void zxdh_bar_reset_valid(uint64_t subchan_addr); + +/** + * zxdh_get_event_id - 获取risc发来消息的event_id + * @subchan_addr: 4k首地址 + * @return: event_id + */ +uint16_t zxdh_get_event_id(uint64_t subchan_addr, uint8_t src_type, uint8_t dst_type); + +int zxdh_bar_irq_recv(uint8_t src, uint8_t dst, uint64_t virt_addr, void *dev); +int32_t call_msg_recv_func_tbl(uint16_t event_id, void *pay_load, uint16_t len, void *reps_buffer, uint16_t *reps_len, void *dev); + +#ifdef __cplusplus +} +#endif + +#endif /* _ZXDH_MSG_CHAN_PUB_H_ */ diff --git a/src/net/include/linux/dinghai/dh_ifc.h b/src/net/include/linux/dinghai/dh_ifc.h new file mode 100755 index 0000000..0006aad --- /dev/null +++ b/src/net/include/linux/dinghai/dh_ifc.h @@ -0,0 +1,51 @@ +#ifndef DINGHAI_IFC_H +#define DINGHAI_IFC_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +struct dh_ifc_cmd_hca_cap_bits { + +}; +union dh_ifc_hca_cap_union_bits{ + +}; + +struct dh_ifc_mbox_in_bits { + uint8_t opcode[0x10]; + uint8_t uid[0x10]; + + uint8_t reserved_at_20[0x10]; + uint8_t op_mod[0x10]; + + uint8_t reserved_at_40[0x40]; +}; + +struct dh_ifc_mbox_out_bits { + uint8_t status[0x8]; + uint8_t reserved_at_8[0x18]; + + uint8_t syndrome[0x20]; + + uint8_t reserved_at_40[0x40]; +}; + +struct dh_ifc_query_hca_cap_out_bits { + uint8_t status[0x8]; + uint8_t reserved_at_8[0x18]; + + uint8_t syndrome[0x20]; + + uint8_t reserved_at_40[0x40]; + + union dh_ifc_hca_cap_union_bits capability; +}; + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/src/net/include/linux/dinghai/dinghai_irq.h b/src/net/include/linux/dinghai/dinghai_irq.h new file mode 100755 index 0000000..7caaa62 --- /dev/null +++ b/src/net/include/linux/dinghai/dinghai_irq.h @@ -0,0 +1,68 @@ +#ifndef __DINGHAI_IRQ_H__ +#define __DINGHAI_IRQ_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#define DH_COMP_EQS_PER_SF 8 + +struct dh_irq; + +int32_t dh_irq_table_init(struct dh_core_dev *dev); +void dh_irq_table_cleanup(struct dh_core_dev *dev); +int32_t dh_irq_table_create(struct dh_core_dev *dev); +void dh_irq_table_destroy(struct dh_core_dev *dev); +int32_t dh_irq_table_get_num_comp(struct dh_irq_table *table); +// int32_t dh_irq_table_get_sfs_vec(struct dh_irq_table *table); +// bool dh_irq_table_have_dedicated_sfs_irqs(struct dh_irq_table *table); + +void dh_irq_rename(struct dh_core_dev *dev, struct dh_irq *irq, + const char *name); +int32_t dh_get_default_msix_vec_count(struct dh_core_dev *dev, int32_t num_vfs); + + +void dh_ctrl_irq_release(struct dh_irq *ctrl_irq); +struct dh_irq *dh_irq_request(struct dh_irq_pool *pool, uint16_t vecidx, + const struct cpumask *affinity, uint8_t exclude); +int32_t dh_irqs_request_vectors(struct dh_irq_pool *pool, uint16_t *cpus, int32_t nirqs, + struct dh_irq **irqs); +void dh_irqs_release_vectors(struct dh_irq **irqs, int32_t nirqs); +int32_t dh_irqs_request_mask(struct dh_irq_pool *pool, struct dh_irq **irqs, + struct cpumask *irqs_req_mask); +int32_t dh_irq_attach_nb(struct dh_irq *irq, struct notifier_block *nb); +int32_t dh_irq_detach_nb(struct dh_irq *irq, struct notifier_block *nb); +struct cpumask *dh_irq_get_affinity_mask(struct dh_irq *irq); +int32_t dh_irq_get_index(struct dh_irq *irq); + +struct dh_irq_pool; +#ifdef CONFIG_ZXDH_SF + +int32_t dh_irq_affinity_irqs_request_auto(struct dh_irq_pool *pool, struct dh_irq **irqs, int32_t num_irqs); +struct dh_irq *dh_irq_affinity_request(struct dh_irq_pool *pool, + const struct cpumask *req_mask); +void dh_irq_affinity_irqs_release(struct dh_irq_pool *pool, struct dh_irq **irqs, int32_t num_irqs); +#else +static inline int32_t dh_irq_affinity_irqs_request_auto(struct dh_irq_pool *pool, struct dh_irq **irqs, int32_t num_irqs) +{ + return -EOPNOTSUPP; +} + +static inline struct dh_irq * +dh_irq_affinity_request(struct dh_irq_pool *pool, const struct cpumask *req_mask) +{ + return ERR_PTR(-EOPNOTSUPP); +} + +static inline void dh_irq_affinity_irqs_release(struct dh_irq_pool *pool, + struct dh_irq **irqs, int32_t num_irqs) {} +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/net/include/linux/dinghai/driver.h b/src/net/include/linux/dinghai/driver.h new file mode 100755 index 0000000..bfff65f --- /dev/null +++ b/src/net/include/linux/dinghai/driver.h @@ -0,0 +1,219 @@ +#ifndef __DINGHAI_DRIVER_H__ +#define __DINGHAI_DRIVER_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include +#include +#include + +struct dh_irq_table { + void *priv; +}; + +/*core dev*/ +enum dh_coredev_type { + DH_COREDEV_PF, + DH_COREDEV_VF, + DH_COREDEV_SF, + DH_COREDEV_MPF +}; + +typedef void (*zxdh_cmd_cbk_t)(int32_t status, void *context); + +struct dh_core_dev; + +struct dh_core_devlink_ops { + int32_t (*params_register)(struct devlink *devlink); + int32_t (*params_unregister)(struct devlink *devlink); +}; + +struct dh_core_dev { + struct device *device; /* pdev->dev or zxdh auxiliary device*/ + enum dh_coredev_type coredev_type; + struct pci_dev *pdev; /* parent pdev*/ + struct pcie_zf_ep *zf_ep; + struct dh_eq_table eq_table; + struct dh_irq_table irq_table; + struct dh_core_dev *parent; + struct dh_events *events; + int32_t numa_node; + struct devlink *devlink; + struct dh_core_devlink_ops *devlink_ops; + char priv[] __aligned(32); +}; + +#define VF_MAX_UNICAST_MAC 32 +#define VF_MAX_MULTICAST_MAC 32 +typedef struct +{ + uint8_t unicast_mac[VF_MAX_UNICAST_MAC][ETH_ALEN]; + uint8_t multicast_mac[VF_MAX_MULTICAST_MAC][ETH_ALEN]; +}device_mac; + +struct zxdh_vf_item { + uint8_t mac[6]; + uint16_t vlan; + uint8_t qos; + bool spoofchk; + bool trusted; + bool pf_set_mac; + bool link_forced; + bool link_up; + bool promisc; + bool mc_promisc; + bool enable; + uint32_t min_tx_rate; + uint32_t max_tx_rate; + uint16_t vport; + bool is_probed; + device_mac vf_mac_info; +}; + +static inline bool dh_core_is_pf(const struct dh_core_dev *dev) +{ + return dev->coredev_type == DH_COREDEV_PF; +} + +static inline bool dh_core_is_vf(const struct dh_core_dev *dev) +{ + return dev->coredev_type == DH_COREDEV_VF; +} + +static inline void *dh_core_priv(struct dh_core_dev *dh_coredev) +{ + BUG_ON(!dh_coredev); + return &dh_coredev->priv; +} + +int32_t zxdh_cmd_exec(struct dh_core_dev *dev, void *in, int32_t in_size, void *out, + int32_t out_size); + +#define zxdh_cmd_exec_inout(dev, ifc_cmd, in, out) \ + ({ \ + zxdh_cmd_exec(dev, in, DH_ST_SZ_BYTES(ifc_cmd##_in), out, \ + DH_ST_SZ_BYTES(ifc_cmd##_out)); \ + }) + +#define zxdh_cmd_exec_in(dev, ifc_cmd, in) \ + ({ \ + uint32_t _out[DH_ST_SZ_DW(ifc_cmd##_out)] = {}; \ + zxdh_cmd_exec_inout(dev, ifc_cmd, in, _out); \ + }) + +#define LOG_ERR(fmt, arg...) DH_LOG_ERR(MODULE_PF, fmt, ##arg); +#define LOG_INFO(fmt, arg...) DH_LOG_INFO(MODULE_PF, fmt, ##arg); +#define LOG_DEBUG(fmt, arg...) DH_LOG_DEBUG(MODULE_PF, fmt, ##arg); +#define LOG_WARN(fmt, arg...) DH_LOG_WARNING(MODULE_PF, fmt, ##arg); + +#define ZXDH_ADEV_NAME "dh_adev" +#define ZXDH_EN_SF_NAME "zxdh_en" +#define ZXDH_EN_DEV_ID_NAME "en_aux" +#define ZXDH_PF_EN_SF_DEV_ID_NAME "pf_en_sf" +#define ZXDH_EN_AUX_NAME "zxdh_en_aux" +#define ZXDH_PF_NAME "zxdh_pf" +#define ZXDH_MPF_EN_SF_DEV_ID_NAME "mpf_en_sf" +#define ZXDH_MPF_NAME "zxdh_mpf" +#define ZXDH_RDMA_DEV_NAME "rdma_aux" + + +#define ZXDH_PF_BSI_VENDOR_ID 0x16c3 +#define ZXDH_PF_VENDOR_ID 0x1cf2 +#define ZXDH_PF_DEVICE_ID 0x8040 +#define ZXDH_VF_DEVICE_ID 0x8041 +#define ZXDH_INICA_BOND_DEVICE_ID 0x8045 +#define ZXDH_INICB_BOND_DEVICE_ID 0x8063 +#define ZXDH_DPUA_BOND_DEVICE_ID 0x8047 +#define ZXDH_PF_DPUB_NOF_DEVICE_ID 0x804a +#define ZXDH_PF_DPUB_PF_DEVICE_ID 0x804b +#define ZXDH_PF_DPUB_INITIATOR1_DEVICE_ID 0x804c +#define ZXDH_PF_DPUB_INITIATOR2_DEVICE_ID 0x804d +#define ZXDH_PF_DPUB_RDMA_DEVICE_ID 0x806b +#define ZXDH_VF_DPUB_RDMA_DEVICE_ID 0x806c +#define ZXDH_PF_E310_DEVICE_ID 0x8061 +#define ZXDH_VF_E310_DEVICE_ID 0x8062 +#define ZXDH_PF_E312_DEVICE_ID 0x8049 +#define ZXDH_VF_E312_DEVICE_ID 0x8060 +#define ZXDH_UPF_PF_I512_DEVICE_ID 0x804e +#define ZXDH_UPF_VF_I512_DEVICE_ID 0x804f +#define ZXDH_INICA_RDMA_PF_DEVICE_ID 0x806d +#define ZXDH_INICA_RDMA_VF_DEVICE_ID 0x806e +#define ZXDH_INICA_UPF_BOND_DEVICE_ID 0x806f + +#define ZXDH_BAR_MSG_OFFSET 0x2000 +#define ZXDH_BAR_PFVF_MSG_OFFSET 0x1000 +#define ZXDH_BAR_MSG_BASE(vaddr) (ZXDH_BAR_MSG_OFFSET + vaddr) + +#define ZXDH_BAR_FWCAP(vaddr) (0x1000 + vaddr) +#define ZXDH_BOARD_TYPE (0X1) +#define ZXDH_PRODUCT_TYPE (0X2) +#define ZXDH_PANNEL_PORT_NUM (0X3) + + +enum +{ + ZXDH_DPU_A = 0, + ZXDH_DPU_B = 1, + ZXDH_INIC_A = 2, + ZXDH_INIC_B = 3, + ZXDH_STD_A = 4, + ZXDH_STD_B = 5, + ZXDH_EVB_EP0 = 6, + ZXDH_EVB_EP0_EP4 = 7, +}; + +/* Warning: Must be modified together with firmware */ +enum +{ + ZXDH_PRODUCT_STD = 0, + ZXDH_PRODUCT_DPI = 1, + ZXDH_PRODUCT_NEO = 2, + ZXDH_PRODUCT_OVS = 3, + ZXDH_PRODUCT_EVB_EP0 = 4, + ZXDH_PRODUCT_EVB_EP0_EP4 = 5, +}; + +#define ZXDH_VF_NUM_MAX 256 + +struct resource_range { + phys_addr_t base; + resource_size_t size; +}; + +struct dh_sf_dev { + struct zxdh_auxiliary_device adev; + struct dh_core_dev *parent_mdev; + struct dh_core_dev *mdev; + int32_t res_num; + struct resource_range *ranges; +}; + +struct zf_rbp_info +{ + bool host; /* true: host addr false: zf addr*/ + uint32_t pfid; /* bit7: 0-pf 1-vf */ + uint32_t vfid; + uint32_t epid; +}; + +struct zf_dma_addr_rbp +{ + dma_addr_t addr; /* src/dst addr */ + uint32_t flag; /* no support */ + struct zf_rbp_info rbp_info; +}; + +void zxdh_dev_list_lock(void); +void zxdh_dev_list_unlock(void); +int zxdh_dev_list_trylock(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/net/include/linux/dinghai/en_aux.h b/src/net/include/linux/dinghai/en_aux.h new file mode 100644 index 0000000..522f67e --- /dev/null +++ b/src/net/include/linux/dinghai/en_aux.h @@ -0,0 +1,69 @@ +#ifndef _EN_ZUX_H_ +#define _EN_ZUX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + + +struct eth_stats +{ + uint64_t rx_pkts; /* gorc */ + uint64_t rx_bytes; /* gorc */ + uint64_t rx_unicast; /* uprc */ + uint64_t rx_multicast; /* mprc */ + uint64_t rx_broadcast; /* bprc */ + uint64_t rx_discards; /* rdpc */ + uint64_t rx_errors; /* rupp */ + uint64_t tx_pkts; /* gorc */ + uint64_t tx_bytes; /* gotc */ + uint64_t tx_unicast; /* uptc */ + uint64_t tx_multicast; /* mptc */ + uint64_t tx_broadcast; /* bptc */ + uint64_t tx_discards; /* tdpc */ + uint64_t tx_errors; /* tepc */ + uint64_t rx_size_64; /* prc64 */ + uint64_t rx_size_127; /* prc127 */ + uint64_t rx_size_255; /* prc255 */ + uint64_t rx_size_511; /* prc511 */ + uint64_t rx_size_1023; /* prc1023 */ + uint64_t rx_size_1518; + uint64_t rx_size_1522; /* prc1522 */ + uint64_t rx_size_1548; + uint64_t rx_size_2047; + uint64_t rx_size_4095; + uint64_t rx_size_8191; + uint64_t rx_size_9215; + uint64_t rx_undersize; /* ruc */ + uint64_t rx_oversize; /* roc */ + uint64_t tx_size_64; /* ptc64 */ + uint64_t tx_size_127; /* ptc127 */ + uint64_t tx_size_255; /* ptc255 */ + uint64_t tx_size_511; /* ptc511 */ + uint64_t tx_size_1023; /* ptc1023 */ + uint64_t tx_size_1518; + uint64_t tx_size_1522; /* prc1522 */ + uint64_t tx_size_1548; + uint64_t tx_size_2047; + uint64_t tx_size_4095; + uint64_t tx_size_8191; + uint64_t tx_size_9215; + uint64_t tx_undersize; /* ruc */ + uint64_t tx_oversize; /* roc */ +}; + +struct zxdh_pf_eth_stats +{ + struct eth_stats eth_total_stat; + struct eth_stats mac0_stat; + struct eth_stats mac1_stat; + struct eth_stats mac2_stat; + struct eth_stats mac3_stat; +}; + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/net/include/linux/dinghai/en_sf.h b/src/net/include/linux/dinghai/en_sf.h new file mode 100755 index 0000000..5d8bee2 --- /dev/null +++ b/src/net/include/linux/dinghai/en_sf.h @@ -0,0 +1,83 @@ +#ifndef __ZXDH_EN_SF_H__ +#define __ZXDH_EN_SF_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +struct zxdh_en_sf_if { + int (*en_sf_vq_irqs_request)(struct dh_core_dev *dh_dev, struct dh_irq **vq_irqs, int vq_channels); + void (*en_sf_affinity_irqs_release)(struct dh_core_dev *dh_dev, struct dh_irq **irqs, int32_t num_irqs); + void __iomem * (*en_sf_map_vq_notify)(struct dh_core_dev *dh_dev, uint32_t index, resource_size_t *pa); + void (*en_sf_unmap_vq_notify)(struct dh_core_dev *dh_dev, void *priv); + void (*en_sf_set_status)(struct dh_core_dev *dh_dev, uint8_t status); + uint8_t (*en_sf_get_status)(struct dh_core_dev *dh_dev); + void (*en_sf_set_vf_mac)(struct dh_core_dev *dh_dev, uint8_t *mac, int32_t vf_id); + void (*en_sf_get_vf_mac)(struct dh_core_dev *dh_dev, uint8_t *mac, int32_t vf_id); + void (*en_sf_set_mac)(struct dh_core_dev *dh_dev, uint8_t *mac); + void (*en_sf_get_mac)(struct dh_core_dev *dh_dev, uint8_t *mac); + uint64_t (*en_sf_get_features)(struct dh_core_dev *dh_dev); + void (*en_sf_set_features)(struct dh_core_dev *dh_dev, uint64_t features); + void (*en_sf_set_queue_enable)(struct dh_core_dev *dh_dev, uint16_t index, bool enable); + uint16_t (*en_sf_get_channels_num)(struct dh_core_dev *dh_dev); + uint16_t (*en_sf_get_queue_num)(struct dh_core_dev *dh_dev); + uint16_t (*en_sf_get_queue_size)(struct dh_core_dev *dh_dev, uint16_t index); + uint16_t (*en_sf_get_queue_vector)(struct dh_core_dev *dh_dev, uint16_t channel, struct list_head *eqs_list, uint16_t queue_index); + void (*en_sf_release_queue_vector)(struct dh_core_dev *dh_dev, int32_t queue_index); + void (*en_sf_set_queue_size)(struct dh_core_dev *dh_dev, uint32_t index, uint16_t size); + void (*en_sf_set_queue_address)(struct dh_core_dev *dh_dev, uint32_t index, uint64_t desc_addr, uint64_t driver_addr, uint64_t device_addr); + void (*en_sf_switch_irq)(struct dh_core_dev *dh_dev, int32_t i, int32_t op); + int32_t (*en_sf_get_vq_lock)(struct dh_core_dev *dh_dev); + int32_t (*en_sf_release_vq_lock)(struct dh_core_dev *dh_dev); + int32_t (*en_sf_get_phy_vq)(struct dh_core_dev *dh_dev, uint16_t index); + int32_t (*en_sf_release_phy_vq)(struct dh_core_dev *dh_dev, uint32_t *phy_index, uint16_t total_qnum); + uint32_t (*en_sf_get_epbdf)(struct dh_core_dev *dh_dev); + uint16_t (*en_sf_get_vport)(struct dh_core_dev *dh_dev); + enum dh_coredev_type (*en_sf_get_coredev_type)(struct dh_core_dev *dh_dev); + uint16_t (*en_sf_get_pcie_id)(struct dh_core_dev *dh_dev); + uint16_t (*en_sf_get_slot_id)(struct dh_core_dev *dh_dev); + bool (*en_sf_is_bond)(struct dh_core_dev *dh_dev); + bool (*en_sf_is_upf)(struct dh_core_dev *dh_dev); + struct pci_dev * (*en_sf_get_pdev)(struct dh_core_dev *dh_dev); + uint64_t (*en_sf_get_bar_virt_addr)(struct dh_core_dev *dh_dev, uint8_t bar_num); + int32_t (*en_sf_msg_send_cmd)(struct dh_core_dev *dh_dev, uint16_t module_id, void *msg, void *ack, bool is_sync); + int32_t (*en_sf_async_eq_enable)(struct dh_core_dev *dh_dev, struct dh_eq_async *eq, const char *name, bool attach); + struct zxdh_vf_item *(*en_sf_get_vf_item)(struct dh_core_dev *dh_dev, uint16_t vf_idx); + void (*en_sf_set_pf_link_up)(struct dh_core_dev *dh_dev, bool link_up); + bool (*en_sf_get_pf_link_up)(struct dh_core_dev *dh_dev); + void (*en_sf_update_pf_link_info)(struct dh_core_dev *dh_dev, struct link_info_struct *link_info_val); + int32_t (*en_sf_get_drv_msg)(struct dh_core_dev *dh_dev, uint8_t *drv_version, uint8_t *drv_version_len); + void (*en_sf_set_vepa)(struct dh_core_dev *dh_dev, bool vepa); + bool (*en_sf_get_vepa)(struct dh_core_dev *dh_dev); + void (*en_sf_set_bond_num)(struct dh_core_dev *dh_dev, bool add); + bool (*en_sf_if_init)(struct dh_core_dev *dh_dev); + int32_t (*en_sf_request_port_info)(struct dh_core_dev *dh_dev, void *data); + int32_t (*en_sf_release_port_info)(struct dh_core_dev *dh_dev, uint32_t port_id); + void (*en_sf_get_link_info_from_vqm)(struct dh_core_dev *dh_dev, uint8_t *link_up); + void (*en_sf_set_vf_link_info)(struct dh_core_dev *dh_dev, uint16_t vf_idx, uint8_t link_up); + void (*en_sf_set_pf_phy_port)(struct dh_core_dev *dh_dev, uint8_t phy_port); + uint8_t (*en_sf_get_pf_phy_port)(struct dh_core_dev *dh_dev); + void (*en_sf_set_init_comp_flag)(struct dh_core_dev *dh_dev); + struct zxdh_ipv6_mac_tbl * (*en_sf_get_ip6mac_tbl)(struct dh_core_dev *dh_dev); +}; + +struct zxdh_en_sf_container { + struct zxdh_auxiliary_device adev; + struct dh_core_dev *dh_dev; + struct dh_core_dev *cdev; + struct zxdh_en_sf_if *ops; + int max_channels; +}; + +int32_t zxdh_en_sf_driver_register(void); +void zxdh_en_sf_driver_unregister(void); + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/net/include/linux/dinghai/eq.h b/src/net/include/linux/dinghai/eq.h new file mode 100755 index 0000000..ea3c9a0 --- /dev/null +++ b/src/net/include/linux/dinghai/eq.h @@ -0,0 +1,111 @@ +#ifndef __DINGHAI_EQ_H__ +#define __DINGHAI_EQ_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +struct dh_irq; + +#define INVALID_EVENT_TYPE 0 + +enum DH_EVENT_TYPE { + DH_EVENT_TYPE_RISCV_READY = 13, + DH_EVENT_TYPE_NOTIFY_ANY = 14, + DH_EVENT_TYPE_NOTIFY_RISC_TO_MPF = 15, + DH_EVENT_TYPE_NOTIFY_PF_TO_MPF = 16, + DH_EVENT_TYPE_NOTIFY_VF_TO_PF = 18, + DH_EVENT_TYPE_NOTIFY_PF_TO_VF = 19, + DH_EVENT_TYPE_NOTIFY_1 = 20, + DH_EVENT_TYPE_NOTIFY_2 = 21, + DH_EVENT_TYPE_NOTIFY_3 = 22, + DH_EVENT_TYPE_NOTIFY_4 = 23, + DH_EVENT_TYPE_NOTIFY_RISCV_TO_AUX = 24, + DH_EVENT_TYPE_NOTIFY_RISC_EXT_PPS = 25, + DH_EVENT_TYPE_NOTIFY_RISC_LOCAL_PPS = 26, + DH_EVENT_TYPE_MAX = 100, +}; + +/* eq core */ +struct dh_eq { + struct dh_core_dev *dev; + __be32 __iomem *doorbell; + uint32_t cons_index; + struct dh_irq *irq; /* interrupt core */ +}; + +/* asynchronous interrupt */ +struct dh_eq_async { + struct dh_eq core; + struct notifier_block irq_nb; /* interrupt: notification chain related to the event queue*/ + void *priv; + spinlock_t lock; /* To avoid irq EQ handle races with resiliency flows */ +}; + +struct dh_eq_param { + int32_t nent; /* queue depth */ + enum dh_event_queue_type event_type; + struct dh_irq *irq; /* interrupt associated with the event queue*/ +}; + +/* event type in the event queue */ +struct dh_nb { + struct notifier_block nb; + int32_t event_type; +}; + +struct dh_irq_table; + +struct dh_eq_table { + struct atomic_notifier_head nh[DH_EVENT_TYPE_MAX]; + struct mutex lock; + struct dh_irq_table *irq_table; + void *priv; +}; + +struct dh_eq_vq { + struct dh_eq core; + struct notifier_block irq_nb; + void *para; +}; + +struct dh_eq_vqs { + struct dh_eq_vq vq_s; + struct list_head vqs; + struct list_head list; +}; + +#define DH_NB_INIT(name, handler, event) do { \ + (name)->nb.notifier_call = handler; \ + (name)->event_type = DH_EVENT_TYPE_##event; \ +} while (0) + +void dh_eq_table_cleanup(struct dh_core_dev *dev); +void dh_eq_table_init(struct dh_core_dev *dev, void *table_priv); +int32_t setup_async_eq(struct dh_core_dev *dev, struct dh_eq_async *eq, + struct dh_eq_param *param, notifier_fn_t dh_eq_async_int, const char *name, void *priv); +int32_t dh_inet6_addr_change_notifier_register(struct notifier_block *inet6_addr_change_notifier); +int32_t dh_inet6_addr_change_notifier_unregister(struct notifier_block *inet6_addr_change_notifier); +int32_t dh_eq_notifier_register(struct dh_eq_table *eqt, struct dh_nb *nb); +void dh_eq_disable(struct dh_core_dev *dev, struct dh_eq *eq, struct notifier_block *nb); +int32_t dh_eq_enable(struct dh_core_dev *dev, struct dh_eq *eq, struct notifier_block *nb); +int32_t dh_eq_notifier_unregister(struct dh_eq_table *eqt, struct dh_nb *nb); +uint16_t dh_eq_event_type_get(uint16_t event_id); + +typedef int32_t (*zxdh_callchain_cbk_t)(struct notifier_block *nb, unsigned long action, void *data); + +struct dh_vq_handler { + zxdh_callchain_cbk_t callback; + void *para; +}; + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/net/include/linux/dinghai/events.h b/src/net/include/linux/dinghai/events.h new file mode 100755 index 0000000..550fce8 --- /dev/null +++ b/src/net/include/linux/dinghai/events.h @@ -0,0 +1,35 @@ +#ifndef __ZXDH_EVENTS_H__ +#define __ZXDH_EVENTS_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +struct dh_event_nb { + struct dh_nb nb; + void *ctx; +}; + +struct dh_events { + struct dh_core_dev *dev; + struct workqueue_struct *wq; + int32_t evt_num; + struct dh_event_nb notifiers[0]; +}; + +void zxdh_events_work_enqueue(struct dh_core_dev *dev, struct work_struct *work); +void zxdh_events_cleanup(struct dh_core_dev *dev); + +#define dh_nb_cof(ptr, type, member) \ + (container_of(container_of(ptr, struct dh_nb, nb), type, member)) + + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/src/net/include/linux/dinghai/helper.h b/src/net/include/linux/dinghai/helper.h new file mode 100755 index 0000000..249cc4c --- /dev/null +++ b/src/net/include/linux/dinghai/helper.h @@ -0,0 +1,81 @@ +#ifndef DINGHAI_HELPER_H +#define DINGHAI_HELPER_H + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef HAVE_DEV_PRINTK_OPS +#include +#endif +#include +#include + +extern uint32_t dh_debug_mask; +#define dh_dbg(__dev, format, ...) \ + dev_dbg((__dev)->device, "%s:%d:(pid %d): " format, \ + __func__, __LINE__, current->pid, \ + ##__VA_ARGS__) + +#define dh_dbg_once(__dev, format, ...) \ + dev_dbg_once((__dev)->device, \ + "%s:%d:(pid %d): " format, \ + __func__, __LINE__, current->pid, \ + ##__VA_ARGS__) + +#define dh_dbg_mask(__dev, mask, format, ...) \ +do { \ + if ((mask) & dh_debug_mask) \ + dh_dbg(__dev, format, ##__VA_ARGS__); \ +} while (0) + +#define dh_err(__dev, format, ...) \ + dev_err((__dev)->device, "%s:%d:(pid %d): " format, \ + __func__, __LINE__, current->pid, \ + ##__VA_ARGS__) + +#define dh_err_rl(__dev, format, ...) \ + dev_err_ratelimited((__dev)->device, \ + "%s:%d:(pid %d): " format, \ + __func__, __LINE__, current->pid, \ + ##__VA_ARGS__) + +#define dh_warn(__dev, format, ...) \ + dev_warn((__dev)->device, "%s:%d:(pid %d): " format, \ + __func__, __LINE__, current->pid, \ + ##__VA_ARGS__) + +#define dh_warn_once(__dev, format, ...) \ + dev_warn_once((__dev)->device, "%s:%d:(pid %d): " format, \ + __func__, __LINE__, current->pid, \ + ##__VA_ARGS__) + +#define dh_warn_rl(__dev, format, ...) \ + dev_warn_ratelimited((__dev)->device, \ + "%s:%d:(pid %d): " format, \ + __func__, __LINE__, current->pid, \ + ##__VA_ARGS__) + +#define dh_info(__dev, format, ...) \ + dev_info((__dev)->device, format, ##__VA_ARGS__) + +#define dh_info_rl(__dev, format, ...) \ + dev_info_ratelimited((__dev)->device, \ + "%s:%d:(pid %d): " format, \ + __func__, __LINE__, current->pid, \ + ##__VA_ARGS__) + +enum { + ZXDH_PCI_DEV_IS_VF = 1 << 0, +}; + +static inline bool dh_core_is_sf(const struct dh_core_dev *dev) +{ + return dev->coredev_type == DH_COREDEV_SF; +} + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/src/net/include/linux/dinghai/kcompat.h b/src/net/include/linux/dinghai/kcompat.h new file mode 100644 index 0000000..5429625 --- /dev/null +++ b/src/net/include/linux/dinghai/kcompat.h @@ -0,0 +1,7333 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright(c) 2013 - 2021 Intel Corporation. */ + +#ifndef _KCOMPAT_H_ +#define _KCOMPAT_H_ + +#ifndef LINUX_VERSION_CODE +#include +#else +#define KERNEL_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c)) +#endif +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifndef GCC_VERSION +#define GCC_VERSION (__GNUC__ * 10000 \ + + __GNUC_MINOR__ * 100 \ + + __GNUC_PATCHLEVEL__) +#endif /* GCC_VERSION */ + +/* Backport macros for controlling GCC diagnostics */ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,18,0) ) + +/* Compilers before gcc-4.6 do not understand "#pragma GCC diagnostic push" */ +#if GCC_VERSION >= 40600 +#define __diag_str1(s) #s +#define __diag_str(s) __diag_str1(s) +#define __diag(s) _Pragma(__diag_str(GCC diagnostic s)) +#else +#define __diag(s) +#endif /* GCC_VERSION >= 4.6 */ +#define __diag_push() __diag(push) +#define __diag_pop() __diag(pop) +#endif /* LINUX_VERSION < 4.18.0 */ + +#ifndef NSEC_PER_MSEC +#define NSEC_PER_MSEC 1000000L +#endif +#include +/* UTS_RELEASE is in a different header starting in kernel 2.6.18 */ +#ifndef UTS_RELEASE +/* utsrelease.h changed locations in 2.6.33 */ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,33) ) +#include +#else +#include +#endif +#endif + +/* NAPI enable/disable flags here */ +#define NAPI + +#ifdef DISABLE_NET_POLL_CONTROLLER +#undef CONFIG_NET_POLL_CONTROLLER +#endif + +/* generic boolean compatibility */ +#undef TRUE +#undef FALSE +#define TRUE true +#define FALSE false +#ifdef GCC_VERSION +#if ( GCC_VERSION < 3000 ) +#define _Bool char +#endif +#else +#define _Bool char +#endif + +#ifndef BIT +#define BIT(nr) (1UL << (nr)) +#endif + +#undef __always_unused +#define __always_unused __attribute__((__unused__)) + +#undef __maybe_unused +#define __maybe_unused __attribute__((__unused__)) + +/* kernels less than 2.4.14 don't have this */ +#ifndef ETH_P_8021Q +#define ETH_P_8021Q 0x8100 +#endif + +#ifndef module_param +#define module_param(v,t,p) MODULE_PARM(v, "i"); +#endif + +#ifndef DMA_64BIT_MASK +#define DMA_64BIT_MASK 0xffffffffffffffffULL +#endif + +#ifndef DMA_32BIT_MASK +#define DMA_32BIT_MASK 0x00000000ffffffffULL +#endif + +#ifndef PCI_CAP_ID_EXP +#define PCI_CAP_ID_EXP 0x10 +#endif + +#ifndef uninitialized_var +#define uninitialized_var(x) x = x +#endif + +#ifndef SET_NETDEV_DEV +#define SET_NETDEV_DEV(net, pdev) +#endif + +#if !defined(HAVE_FREE_NETDEV) && ( LINUX_VERSION_CODE < KERNEL_VERSION(3,1,0) ) +#define free_netdev(x) kfree(x) +#endif + +#ifdef HAVE_POLL_CONTROLLER +#define CONFIG_NET_POLL_CONTROLLER +#endif + +#ifndef SKB_DATAREF_SHIFT +/* if we do not have the infrastructure to detect if skb_header is cloned + just return false in all cases */ +#define skb_header_cloned(x) 0 +#endif + +#ifndef NETIF_F_GSO +#define gso_size tso_size +#define gso_segs tso_segs +#endif + +#ifndef NETIF_F_GRO +#define vlan_gro_receive(_napi, _vlgrp, _vlan, _skb) \ + vlan_hwaccel_receive_skb(_skb, _vlgrp, _vlan) +#define napi_gro_receive(_napi, _skb) netif_receive_skb(_skb) +#endif + +#ifndef NETIF_F_LRO +#define NETIF_F_LRO BIT(15) +#endif + +#ifndef NETIF_F_NTUPLE +#define NETIF_F_NTUPLE BIT(27) +#endif + +#ifndef NETIF_F_ALL_FCOE +#define NETIF_F_ALL_FCOE (NETIF_F_FCOE_CRC | NETIF_F_FCOE_MTU | \ + NETIF_F_FSO) +#endif + +#ifndef IPPROTO_SCTP +#define IPPROTO_SCTP 132 +#endif + +#ifndef IPPROTO_UDPLITE +#define IPPROTO_UDPLITE 136 +#endif + +#ifndef CHECKSUM_PARTIAL +#define CHECKSUM_PARTIAL CHECKSUM_HW +#define CHECKSUM_COMPLETE CHECKSUM_HW +#endif + +#ifndef unlikely +#define unlikely(_x) _x +#define likely(_x) _x +#endif + +#ifndef WARN_ON +#define WARN_ON(x) +#endif + +#ifndef PCI_DEVICE +#define PCI_DEVICE(vend,dev) \ + .vendor = (vend), .device = (dev), \ + .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID +#endif + +#ifndef node_online +#define node_online(node) ((node) == 0) +#endif + +// #ifndef cpu_online +// #define cpu_online(cpuid) test_bit((cpuid), &cpu_online_map) +// #endif + +#ifndef _LINUX_RANDOM_H +#include +#endif + +#ifndef BITS_PER_TYPE +#define BITS_PER_TYPE(type) (sizeof(type) * BITS_PER_BYTE) +#endif + +#ifndef BITS_TO_LONGS +#define BITS_TO_LONGS(bits) (((bits)+BITS_PER_LONG-1)/BITS_PER_LONG) +#endif + +#ifndef DECLARE_BITMAP +#define DECLARE_BITMAP(name,bits) long name[BITS_TO_LONGS(bits)] +#endif + +#ifndef VLAN_HLEN +#define VLAN_HLEN 4 +#endif + +#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS +#if defined(__i386__) || defined(__x86_64__) +#define CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS +#endif +#endif + +/* taken from 2.6.24 definition in linux/kernel.h */ +#ifndef IS_ALIGNED +#define IS_ALIGNED(x,a) (((x) % ((typeof(x))(a))) == 0) +#endif + +#ifdef IS_ENABLED +#undef IS_ENABLED +#undef __ARG_PLACEHOLDER_1 +#undef config_enabled +#undef _config_enabled +#undef __config_enabled +#undef ___config_enabled +#endif + +#define __ARG_PLACEHOLDER_1 0, +#define config_enabled(cfg) _config_enabled(cfg) +#define _config_enabled(value) __config_enabled(__ARG_PLACEHOLDER_##value) +#define __config_enabled(arg1_or_junk) ___config_enabled(arg1_or_junk 1, 0) +#define ___config_enabled(__ignored, val, ...) val + +#define IS_ENABLED(option) \ + (config_enabled(option) || config_enabled(option##_MODULE)) + +#if !defined(NETIF_F_HW_VLAN_TX) && !defined(NETIF_F_HW_VLAN_CTAG_TX) +struct _kc_vlan_ethhdr { + unsigned char h_dest[ETH_ALEN]; + unsigned char h_source[ETH_ALEN]; + __be16 h_vlan_proto; + __be16 h_vlan_TCI; + __be16 h_vlan_encapsulated_proto; +}; +#define vlan_ethhdr _kc_vlan_ethhdr +struct _kc_vlan_hdr { + __be16 h_vlan_TCI; + __be16 h_vlan_encapsulated_proto; +}; +#define vlan_hdr _kc_vlan_hdr +#define vlan_tx_tag_present(_skb) 0 +#define vlan_tx_tag_get(_skb) 0 +#endif /* NETIF_F_HW_VLAN_TX && NETIF_F_HW_VLAN_CTAG_TX */ + +#ifndef VLAN_PRIO_SHIFT +#define VLAN_PRIO_SHIFT 13 +#endif + +#ifndef PCI_EXP_LNKSTA_CLS_2_5GB +#define PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 +#endif + +#ifndef PCI_EXP_LNKSTA_CLS_5_0GB +#define PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 +#endif + +#ifndef PCI_EXP_LNKSTA_CLS_8_0GB +#define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 +#endif + +#ifndef PCI_EXP_LNKSTA_NLW_X1 +#define PCI_EXP_LNKSTA_NLW_X1 0x0010 +#endif + +#ifndef PCI_EXP_LNKSTA_NLW_X2 +#define PCI_EXP_LNKSTA_NLW_X2 0x0020 +#endif + +#ifndef PCI_EXP_LNKSTA_NLW_X4 +#define PCI_EXP_LNKSTA_NLW_X4 0x0040 +#endif + +#ifndef PCI_EXP_LNKSTA_NLW_X8 +#define PCI_EXP_LNKSTA_NLW_X8 0x0080 +#endif + +#ifndef __GFP_COLD +#define __GFP_COLD 0 +#endif + +#ifndef __GFP_COMP +#define __GFP_COMP 0 +#endif + +#ifndef IP_OFFSET +#define IP_OFFSET 0x1FFF /* "Fragment Offset" part */ +#endif + +#ifndef ETH_GSTRING_LEN +#define ETH_GSTRING_LEN 32 +#endif + +#ifndef ETHTOOL_GSTATS +#define ETHTOOL_GSTATS 0x1d +#undef ethtool_drvinfo +#define ethtool_drvinfo k_ethtool_drvinfo +struct k_ethtool_drvinfo { + u32 cmd; + char driver[32]; + char version[32]; + char fw_version[32]; + char bus_info[32]; + char reserved1[32]; + char reserved2[16]; + u32 n_stats; + u32 testinfo_len; + u32 eedump_len; + u32 regdump_len; +}; + +struct ethtool_stats { + u32 cmd; + u32 n_stats; + u64 data[0]; +}; +#endif /* ETHTOOL_GSTATS */ + +#ifndef ETHTOOL_GSTRINGS +#define ETHTOOL_GSTRINGS 0x1b +enum ethtool_stringset { + ETH_SS_TEST = 0, + ETH_SS_STATS, +}; +struct ethtool_gstrings { + u32 cmd; /* ETHTOOL_GSTRINGS */ + u32 string_set; /* string set id e.c. ETH_SS_TEST, etc*/ + u32 len; /* number of strings in the string set */ + u8 data[0]; +}; +#endif /* ETHTOOL_GSTRINGS */ + +#ifndef ETHTOOL_TEST +#define ETHTOOL_TEST 0x1a +enum ethtool_test_flags { + ETH_TEST_FL_OFFLINE = BIT(0), + ETH_TEST_FL_FAILED = BIT(1), +}; +struct ethtool_test { + u32 cmd; + u32 flags; + u32 reserved; + u32 len; + u64 data[0]; +}; +#endif /* ETHTOOL_TEST */ + +#ifndef ETHTOOL_GEEPROM +#define ETHTOOL_GEEPROM 0xb +#undef ETHTOOL_GREGS +struct ethtool_eeprom { + u32 cmd; + u32 magic; + u32 offset; + u32 len; + u8 data[0]; +}; + +struct ethtool_value { + u32 cmd; + u32 data; +}; +#endif /* ETHTOOL_GEEPROM */ + +#ifndef ETHTOOL_GLINK +#define ETHTOOL_GLINK 0xa +#endif /* ETHTOOL_GLINK */ + +#ifndef ETHTOOL_GWOL +#define ETHTOOL_GWOL 0x5 +#define ETHTOOL_SWOL 0x6 +#define SOPASS_MAX 6 +struct ethtool_wolinfo { + u32 cmd; + u32 supported; + u32 wolopts; + u8 sopass[SOPASS_MAX]; /* SecureOn(tm) password */ +}; +#endif /* ETHTOOL_GWOL */ + +#ifndef ETHTOOL_GREGS +#define ETHTOOL_GREGS 0x00000004 /* Get NIC registers */ +#define ethtool_regs _kc_ethtool_regs +/* for passing big chunks of data */ +struct _kc_ethtool_regs { + u32 cmd; + u32 version; /* driver-specific, indicates different chips/revs */ + u32 len; /* bytes */ + u8 data[0]; +}; +#endif /* ETHTOOL_GREGS */ + +#ifndef ETHTOOL_GMSGLVL +#define ETHTOOL_GMSGLVL 0x00000007 /* Get driver message level */ +#endif +#ifndef ETHTOOL_SMSGLVL +#define ETHTOOL_SMSGLVL 0x00000008 /* Set driver msg level, priv. */ +#endif +#ifndef ETHTOOL_NWAY_RST +#define ETHTOOL_NWAY_RST 0x00000009 /* Restart autonegotiation, priv */ +#endif +#ifndef ETHTOOL_GLINK +#define ETHTOOL_GLINK 0x0000000a /* Get link status */ +#endif +#ifndef ETHTOOL_GEEPROM +#define ETHTOOL_GEEPROM 0x0000000b /* Get EEPROM data */ +#endif +#ifndef ETHTOOL_SEEPROM +#define ETHTOOL_SEEPROM 0x0000000c /* Set EEPROM data */ +#endif +#ifndef ETHTOOL_GCOALESCE +#define ETHTOOL_GCOALESCE 0x0000000e /* Get coalesce config */ + +#define ethtool_coalesce _kc_ethtool_coalesce +struct _kc_ethtool_coalesce { + u32 cmd; + + u32 rx_coalesce_usecs; + + u32 rx_max_coalesced_frames; + + u32 rx_coalesce_usecs_irq; + u32 rx_max_coalesced_frames_irq; + + u32 tx_coalesce_usecs; + + u32 tx_max_coalesced_frames; + + u32 tx_coalesce_usecs_irq; + u32 tx_max_coalesced_frames_irq; + + u32 stats_block_coalesce_usecs; + + u32 use_adaptive_rx_coalesce; + u32 use_adaptive_tx_coalesce; + + u32 pkt_rate_low; + u32 rx_coalesce_usecs_low; + u32 rx_max_coalesced_frames_low; + u32 tx_coalesce_usecs_low; + u32 tx_max_coalesced_frames_low; + + u32 pkt_rate_high; + u32 rx_coalesce_usecs_high; + u32 rx_max_coalesced_frames_high; + u32 tx_coalesce_usecs_high; + u32 tx_max_coalesced_frames_high; + + u32 rate_sample_interval; +}; +#endif /* ETHTOOL_GCOALESCE */ + +#ifndef ETHTOOL_SCOALESCE +#define ETHTOOL_SCOALESCE 0x0000000f /* Set coalesce config. */ +#endif +#ifndef ETHTOOL_GRINGPARAM +#define ETHTOOL_GRINGPARAM 0x00000010 /* Get ring parameters */ + +#define ethtool_ringparam _kc_ethtool_ringparam +struct _kc_ethtool_ringparam { + u32 cmd; + + u32 rx_max_pending; + u32 rx_mini_max_pending; + u32 rx_jumbo_max_pending; + u32 tx_max_pending; + + u32 rx_pending; + u32 rx_mini_pending; + u32 rx_jumbo_pending; + u32 tx_pending; +}; +#endif /* ETHTOOL_GRINGPARAM */ + +#ifndef ETHTOOL_SRINGPARAM +#define ETHTOOL_SRINGPARAM 0x00000011 /* Set ring parameters, priv. */ +#endif +#ifndef ETHTOOL_GPAUSEPARAM +#define ETHTOOL_GPAUSEPARAM 0x00000012 /* Get pause parameters */ + +#define ethtool_pauseparam _kc_ethtool_pauseparam +struct _kc_ethtool_pauseparam { + u32 cmd; + u32 autoneg; + u32 rx_pause; + u32 tx_pause; +}; +#endif /* ETHTOOL_GPAUSEPARAM */ + +#ifndef ETHTOOL_SPAUSEPARAM +#define ETHTOOL_SPAUSEPARAM 0x00000013 /* Set pause parameters. */ +#endif +#ifndef ETHTOOL_GRXCSUM +#define ETHTOOL_GRXCSUM 0x00000014 /* Get RX hw csum enable (ethtool_value) */ +#endif +#ifndef ETHTOOL_SRXCSUM +#define ETHTOOL_SRXCSUM 0x00000015 /* Set RX hw csum enable (ethtool_value) */ +#endif +#ifndef ETHTOOL_GTXCSUM +#define ETHTOOL_GTXCSUM 0x00000016 /* Get TX hw csum enable (ethtool_value) */ +#endif +#ifndef ETHTOOL_STXCSUM +#define ETHTOOL_STXCSUM 0x00000017 /* Set TX hw csum enable (ethtool_value) */ +#endif +#ifndef ETHTOOL_GSG +#define ETHTOOL_GSG 0x00000018 /* Get scatter-gather enable + * (ethtool_value) */ +#endif +#ifndef ETHTOOL_SSG +#define ETHTOOL_SSG 0x00000019 /* Set scatter-gather enable + * (ethtool_value). */ +#endif +#ifndef ETHTOOL_TEST +#define ETHTOOL_TEST 0x0000001a /* execute NIC self-test, priv. */ +#endif +#ifndef ETHTOOL_GSTRINGS +#define ETHTOOL_GSTRINGS 0x0000001b /* get specified string set */ +#endif +#ifndef ETHTOOL_GSTATS +#define ETHTOOL_GSTATS 0x0000001d /* get NIC-specific statistics */ +#endif +#ifndef ETHTOOL_GTSO +#define ETHTOOL_GTSO 0x0000001e /* Get TSO enable (ethtool_value) */ +#endif +#ifndef ETHTOOL_STSO +#define ETHTOOL_STSO 0x0000001f /* Set TSO enable (ethtool_value) */ +#endif + +#ifndef ETHTOOL_BUSINFO_LEN +#define ETHTOOL_BUSINFO_LEN 32 +#endif + +#ifndef WAKE_FILTER +#define WAKE_FILTER BIT(7) +#endif + +#ifndef SPEED_2500 +#define SPEED_2500 2500 +#endif +#ifndef SPEED_5000 +#define SPEED_5000 5000 +#endif +#ifndef SPEED_14000 +#define SPEED_14000 14000 +#endif +#ifndef SPEED_25000 +#define SPEED_25000 25000 +#endif +#ifndef SPEED_50000 +#define SPEED_50000 50000 +#endif +#ifndef SPEED_56000 +#define SPEED_56000 56000 +#endif +#ifndef SPEED_100000 +#define SPEED_100000 100000 +#endif + +#ifndef RHEL_RELEASE_VERSION +#define RHEL_RELEASE_VERSION(a,b) (((a) << 8) + (b)) +#endif +#ifndef AX_RELEASE_VERSION +#define AX_RELEASE_VERSION(a,b) (((a) << 8) + (b)) +#endif + +#ifndef AX_RELEASE_CODE +#define AX_RELEASE_CODE 0 +#endif + +#if (AX_RELEASE_CODE && AX_RELEASE_CODE == AX_RELEASE_VERSION(3,0)) +#define RHEL_RELEASE_CODE RHEL_RELEASE_VERSION(5,0) +#elif (AX_RELEASE_CODE && AX_RELEASE_CODE == AX_RELEASE_VERSION(3,1)) +#define RHEL_RELEASE_CODE RHEL_RELEASE_VERSION(5,1) +#elif (AX_RELEASE_CODE && AX_RELEASE_CODE == AX_RELEASE_VERSION(3,2)) +#define RHEL_RELEASE_CODE RHEL_RELEASE_VERSION(5,3) +#endif + +#ifndef RHEL_RELEASE_CODE +/* NOTE: RHEL_RELEASE_* introduced in RHEL4.5 */ +#define RHEL_RELEASE_CODE 0 +#endif + +/* RHEL 7 didn't backport the parameter change in + * create_singlethread_workqueue. + * If/when RH corrects this we will want to tighten up the version check. + */ +#if (RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,0)) +#undef create_singlethread_workqueue +#define create_singlethread_workqueue(name) \ + alloc_ordered_workqueue("%s", WQ_MEM_RECLAIM, name) +#endif + +/* Ubuntu Release ABI is the 4th digit of their kernel version. You can find + * it in /usr/src/linux/$(uname -r)/include/generated/utsrelease.h for new + * enough versions of Ubuntu. Otherwise you can simply see it in the output of + * uname as the 4th digit of the kernel. The UTS_UBUNTU_RELEASE_ABI is not in + * the linux-source package, but in the linux-headers package. It begins to + * appear in later releases of 14.04 and 14.10. + * + * Ex: + * + * $uname -r + * 3.13.0-45-generic + * ABI is 45 + * + * + * $uname -r + * 3.16.0-23-generic + * ABI is 23 + */ +#ifndef UTS_UBUNTU_RELEASE_ABI +#define UTS_UBUNTU_RELEASE_ABI 0 +#define UBUNTU_VERSION_CODE 0 +#else +/* Ubuntu does not provide actual release version macro, so we use the kernel + * version plus the ABI to generate a unique version code specific to Ubuntu. + * In addition, we mask the lower 8 bits of LINUX_VERSION_CODE in order to + * ignore differences in sublevel which are not important since we have the + * ABI value. Otherwise, it becomes impossible to correlate ABI to version for + * ordering checks. + */ +#define UBUNTU_VERSION_CODE (((~0xFF & LINUX_VERSION_CODE) << 8) + \ + UTS_UBUNTU_RELEASE_ABI) + +#if UTS_UBUNTU_RELEASE_ABI > 255 +#error UTS_UBUNTU_RELEASE_ABI is too large... +#endif /* UTS_UBUNTU_RELEASE_ABI > 255 */ + +#if ( LINUX_VERSION_CODE <= KERNEL_VERSION(3,0,0) ) +/* Our version code scheme does not make sense for non 3.x or newer kernels, + * and we have no support in kcompat for this scenario. Thus, treat this as a + * non-Ubuntu kernel. Possibly might be better to error here. + */ +#define UTS_UBUNTU_RELEASE_ABI 0 +#define UBUNTU_VERSION_CODE 0 +#endif + +#endif + +/* Note that the 3rd digit is always zero, and will be ignored. This is + * because Ubuntu kernels are based on x.y.0-ABI values, and while their linux + * version codes are 3 digit, this 3rd digit is superseded by the ABI value. + */ +#define UBUNTU_VERSION(a,b,c,d) ((KERNEL_VERSION(a,b,0) << 8) + (d)) + +/* SuSE version macros are the same as Linux kernel version macro */ +#ifndef SLE_VERSION +#define SLE_VERSION(a,b,c) KERNEL_VERSION(a,b,c) +#endif +#define SLE_LOCALVERSION(a,b,c) KERNEL_VERSION(a,b,c) +#ifdef CONFIG_SUSE_KERNEL +#if ( LINUX_VERSION_CODE == KERNEL_VERSION(2,6,27) ) +/* SLES11 GA is 2.6.27 based */ +#define SLE_VERSION_CODE SLE_VERSION(11,0,0) +#elif ( LINUX_VERSION_CODE == KERNEL_VERSION(2,6,32) ) +/* SLES11 SP1 is 2.6.32 based */ +#define SLE_VERSION_CODE SLE_VERSION(11,1,0) +#elif ( LINUX_VERSION_CODE == KERNEL_VERSION(3,0,13) ) +/* SLES11 SP2 GA is 3.0.13-0.27 */ +#define SLE_VERSION_CODE SLE_VERSION(11,2,0) +#elif ((LINUX_VERSION_CODE == KERNEL_VERSION(3,0,76))) +/* SLES11 SP3 GA is 3.0.76-0.11 */ +#define SLE_VERSION_CODE SLE_VERSION(11,3,0) +#elif (LINUX_VERSION_CODE == KERNEL_VERSION(3,0,101)) + #if (SLE_LOCALVERSION_CODE < SLE_LOCALVERSION(0,8,0)) + /* some SLES11sp2 update kernels up to 3.0.101-0.7.x */ + #define SLE_VERSION_CODE SLE_VERSION(11,2,0) + #elif (SLE_LOCALVERSION_CODE < SLE_LOCALVERSION(63,0,0)) + /* most SLES11sp3 update kernels */ + #define SLE_VERSION_CODE SLE_VERSION(11,3,0) + #else + /* SLES11 SP4 GA (3.0.101-63) and update kernels 3.0.101-63+ */ + #define SLE_VERSION_CODE SLE_VERSION(11,4,0) + #endif +#elif (LINUX_VERSION_CODE == KERNEL_VERSION(3,12,28)) +/* SLES12 GA is 3.12.28-4 + * kernel updates 3.12.xx-<33 through 52>[.yy] */ +#define SLE_VERSION_CODE SLE_VERSION(12,0,0) +#elif (LINUX_VERSION_CODE == KERNEL_VERSION(3,12,49)) +/* SLES12 SP1 GA is 3.12.49-11 + * updates 3.12.xx-60.yy where xx={51..} */ +#define SLE_VERSION_CODE SLE_VERSION(12,1,0) +#elif ((LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,21) && \ + (LINUX_VERSION_CODE <= KERNEL_VERSION(4,4,59))) || \ + (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,74) && \ + LINUX_VERSION_CODE < KERNEL_VERSION(4,5,0) && \ + SLE_LOCALVERSION_CODE >= KERNEL_VERSION(92,0,0) && \ + SLE_LOCALVERSION_CODE < KERNEL_VERSION(93,0,0))) +/* SLES12 SP2 GA is 4.4.21-69. + * SLES12 SP2 updates before SLES12 SP3 are: 4.4.{21,38,49,59} + * SLES12 SP2 updates after SLES12 SP3 are: 4.4.{74,90,103,114,120} + * but they all use a SLE_LOCALVERSION_CODE matching 92.nn.y */ +#define SLE_VERSION_CODE SLE_VERSION(12,2,0) +#elif ((LINUX_VERSION_CODE == KERNEL_VERSION(4,4,73) || \ + LINUX_VERSION_CODE == KERNEL_VERSION(4,4,82) || \ + LINUX_VERSION_CODE == KERNEL_VERSION(4,4,92)) || \ + (LINUX_VERSION_CODE == KERNEL_VERSION(4,4,103) && \ + (SLE_LOCALVERSION_CODE == KERNEL_VERSION(6,33,0) || \ + SLE_LOCALVERSION_CODE == KERNEL_VERSION(6,38,0))) || \ + (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,114) && \ + LINUX_VERSION_CODE < KERNEL_VERSION(4,5,0) && \ + SLE_LOCALVERSION_CODE >= KERNEL_VERSION(94,0,0) && \ + SLE_LOCALVERSION_CODE < KERNEL_VERSION(95,0,0)) ) +/* SLES12 SP3 GM is 4.4.73-5 and update kernels are 4.4.82-6.3. + * SLES12 SP3 updates not conflicting with SP2 are: 4.4.{82,92} + * SLES12 SP3 updates conflicting with SP2 are: + * - 4.4.103-6.33.1, 4.4.103-6.38.1 + * - 4.4.{114,120}-94.nn.y */ +#define SLE_VERSION_CODE SLE_VERSION(12,3,0) +#elif (LINUX_VERSION_CODE == KERNEL_VERSION(4,12,14) && \ + (SLE_LOCALVERSION_CODE == KERNEL_VERSION(94,41,0) || \ + (SLE_LOCALVERSION_CODE >= KERNEL_VERSION(95,0,0) && \ + SLE_LOCALVERSION_CODE < KERNEL_VERSION(96,0,0)))) +/* SLES12 SP4 GM is 4.12.14-94.41 and update kernel is 4.12.14-95.x. */ +#define SLE_VERSION_CODE SLE_VERSION(12,4,0) +#elif (LINUX_VERSION_CODE == KERNEL_VERSION(4,12,14) && \ + (SLE_LOCALVERSION_CODE == KERNEL_VERSION(23,0,0) || \ + SLE_LOCALVERSION_CODE == KERNEL_VERSION(2,0,0) || \ + SLE_LOCALVERSION_CODE == KERNEL_VERSION(136,0,0) || \ + (SLE_LOCALVERSION_CODE >= KERNEL_VERSION(25,0,0) && \ + SLE_LOCALVERSION_CODE < KERNEL_VERSION(26,0,0)) || \ + (SLE_LOCALVERSION_CODE >= KERNEL_VERSION(150,0,0) && \ + SLE_LOCALVERSION_CODE < KERNEL_VERSION(151,0,0)))) +/* SLES15 Beta1 is 4.12.14-2 + * SLES15 GM is 4.12.14-23 and update kernel is 4.12.14-{25,136}, + * and 4.12.14-150.14. + */ +#define SLE_VERSION_CODE SLE_VERSION(15,0,0) +#elif (LINUX_VERSION_CODE == KERNEL_VERSION(4,12,14) && \ + SLE_LOCALVERSION_CODE >= KERNEL_VERSION(25,23,0)) +/* SLES15 SP1 Beta1 is 4.12.14-25.23 */ +#define SLE_VERSION_CODE SLE_VERSION(15,1,0) +#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(5,3,13)) +/* SLES15 SP2 Beta1 is 5.3.13 */ +#define SLE_VERSION_CODE SLE_VERSION(15,2,0) + +/* new SLES kernels must be added here with >= based on kernel + * the idea is to order from newest to oldest and just catch all + * of them using the >= + */ +#endif /* LINUX_VERSION_CODE == KERNEL_VERSION(x,y,z) */ +#endif /* CONFIG_SUSE_KERNEL */ +#ifndef SLE_VERSION_CODE +#define SLE_VERSION_CODE 0 +#endif /* SLE_VERSION_CODE */ +#ifndef SLE_LOCALVERSION_CODE +#define SLE_LOCALVERSION_CODE 0 +#endif /* SLE_LOCALVERSION_CODE */ + +/* + * ADQ depends on __TC_MQPRIO_MODE_MAX and related kernel code + * added around 4.15. Some distributions (e.g. Oracle Linux 7.7) + * have done a partial back-port of that to their kernels based + * on older mainline kernels that did not include all the necessary + * kernel enablement to support ADQ. + * Undefine __TC_MQPRIO_MODE_MAX for all OSV distributions with + * kernels based on mainline kernels older than 4.15 except for + * RHEL, SLES and Ubuntu which are known to have good back-ports. + */ +#if (!RHEL_RELEASE_CODE && !SLE_VERSION_CODE && !UBUNTU_VERSION_CODE) + #if (LINUX_VERSION_CODE < KERNEL_VERSION(4,15,0)) + #undef __TC_MQPRIO_MODE_MAX + #endif /* LINUX_VERSION_CODE == KERNEL_VERSION(4,15,0) */ +#endif /* if (NOT RHEL && NOT SLES && NOT UBUNTU) */ + +#ifdef __KLOCWORK__ +/* The following are not compiled into the binary driver; they are here + * only to tune Klocwork scans to workaround false-positive issues. + */ +#ifdef ARRAY_SIZE +#undef ARRAY_SIZE +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) +#endif + +#define memcpy(dest, src, len) memcpy_s(dest, len, src, len) +#define memset(dest, ch, len) memset_s(dest, len, ch, len) + +static inline int _kc_test_and_clear_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long old; + unsigned long flags = 0; + + _atomic_spin_lock_irqsave(p, flags); + old = *p; + *p = old & ~mask; + _atomic_spin_unlock_irqrestore(p, flags); + + return (old & mask) != 0; +} +#define test_and_clear_bit(nr, addr) _kc_test_and_clear_bit(nr, addr) + +static inline int _kc_test_and_set_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long old; + unsigned long flags = 0; + + _atomic_spin_lock_irqsave(p, flags); + old = *p; + *p = old | mask; + _atomic_spin_unlock_irqrestore(p, flags); + + return (old & mask) != 0; +} +#define test_and_set_bit(nr, addr) _kc_test_and_set_bit(nr, addr) + +#ifdef CONFIG_DYNAMIC_DEBUG +#undef dev_dbg +#define dev_dbg(dev, format, arg...) dev_printk(KERN_DEBUG, dev, format, ##arg) +#undef pr_debug +#define pr_debug(format, arg...) printk(KERN_DEBUG format, ##arg) +#endif /* CONFIG_DYNAMIC_DEBUG */ + +#undef hlist_for_each_entry_safe +#define hlist_for_each_entry_safe(pos, n, head, member) \ + for (n = NULL, pos = hlist_entry_safe((head)->first, typeof(*(pos)), \ + member); \ + pos; \ + pos = hlist_entry_safe((pos)->member.next, typeof(*(pos)), member)) + +#ifdef uninitialized_var +#undef uninitialized_var +#define uninitialized_var(x) x = *(&(x)) +#endif + +#ifdef WRITE_ONCE +#undef WRITE_ONCE +#define WRITE_ONCE(x, val) ((x) = (val)) +#endif /* WRITE_ONCE */ +#endif /* __KLOCWORK__ */ + +#include "kcompat_vfd.h" +struct vfd_objects *create_vfd_sysfs(struct pci_dev *pdev, int num_alloc_vfs); +void destroy_vfd_sysfs(struct pci_dev *pdev, struct vfd_objects *vfd_obj); + +/* Older versions of GCC will trigger -Wformat-nonliteral warnings for const + * char * strings. Unfortunately, the implementation of do_trace_printk does + * this, in order to add a storage attribute to the memory. This was fixed in + * GCC 5.1, but we still use older distributions built with GCC 4.x. + * + * The string pointer is only passed as a const char * to the __trace_bprintk + * function. Since that function has the __printf attribute, it will trigger + * the warnings. We can't remove the attribute, so instead we'll use the + * __diag macro to disable -Wformat-nonliteral around the call to + * __trace_bprintk. + */ +#if GCC_VERSION < 50100 +#define __trace_bprintk(ip, fmt, args...) ({ \ + int err; \ + __diag_push(); \ + __diag(ignored "-Wformat-nonliteral"); \ + err = __trace_bprintk(ip, fmt, ##args); \ + __diag_pop(); \ + err; \ +}) +#endif /* GCC_VERSION < 5.1.0 */ + +/* Newer kernels removed */ +#if ((LINUX_VERSION_CODE < KERNEL_VERSION(5,4,0)) && \ + (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(8,3))) +#define HAVE_PCI_ASPM_H +#endif + +/*****************************************************************************/ +/* 2.4.3 => 2.4.0 */ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,3) ) + +/**************************************/ +/* PCI DRIVER API */ + +#ifndef pci_set_dma_mask +#define pci_set_dma_mask _kc_pci_set_dma_mask +int _kc_pci_set_dma_mask(struct pci_dev *dev, dma_addr_t mask); +#endif + +#ifndef pci_request_regions +#define pci_request_regions _kc_pci_request_regions +int _kc_pci_request_regions(struct pci_dev *pdev, char *res_name); +#endif + +#ifndef pci_release_regions +#define pci_release_regions _kc_pci_release_regions +void _kc_pci_release_regions(struct pci_dev *pdev); +#endif + +/**************************************/ +/* NETWORK DRIVER API */ + +#ifndef alloc_etherdev +#define alloc_etherdev _kc_alloc_etherdev +struct net_device * _kc_alloc_etherdev(int sizeof_priv); +#endif + +#ifndef is_valid_ether_addr +#define is_valid_ether_addr _kc_is_valid_ether_addr +int _kc_is_valid_ether_addr(u8 *addr); +#endif + +/**************************************/ +#ifndef INIT_TQUEUE +#define INIT_TQUEUE(_tq, _routine, _data) \ + do { \ + INIT_LIST_HEAD(&(_tq)->list); \ + (_tq)->sync = 0; \ + (_tq)->routine = _routine; \ + (_tq)->data = _data; \ + } while (0) +#endif + +#endif /* 2.4.3 => 2.4.0 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,5) ) +/* Generic MII registers. */ +#define MII_BMCR 0x00 /* Basic mode control register */ +#define MII_BMSR 0x01 /* Basic mode status register */ +#define MII_PHYSID1 0x02 /* PHYS ID 1 */ +#define MII_PHYSID2 0x03 /* PHYS ID 2 */ +#define MII_ADVERTISE 0x04 /* Advertisement control reg */ +#define MII_LPA 0x05 /* Link partner ability reg */ +#define MII_EXPANSION 0x06 /* Expansion register */ +/* Basic mode control register. */ +#define BMCR_FULLDPLX 0x0100 /* Full duplex */ +#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */ +/* Basic mode status register. */ +#define BMSR_ERCAP 0x0001 /* Ext-reg capability */ +#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */ +#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */ +#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */ +#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */ +#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */ +/* Advertisement control register. */ +#define ADVERTISE_CSMA 0x0001 /* Only selector supported */ +#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ +#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ +#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ +#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ +#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \ + ADVERTISE_100HALF | ADVERTISE_100FULL) +/* Expansion register for auto-negotiation. */ +#define EXPANSION_ENABLENPAGE 0x0004 /* This enables npage words */ +#endif + +/*****************************************************************************/ +/* 2.4.6 => 2.4.3 */ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,6) ) + +#ifndef pci_set_power_state +#define pci_set_power_state _kc_pci_set_power_state +int _kc_pci_set_power_state(struct pci_dev *dev, int state); +#endif + +#ifndef pci_enable_wake +#define pci_enable_wake _kc_pci_enable_wake +int _kc_pci_enable_wake(struct pci_dev *pdev, u32 state, int enable); +#endif + +#ifndef pci_disable_device +#define pci_disable_device _kc_pci_disable_device +void _kc_pci_disable_device(struct pci_dev *pdev); +#endif + +/* PCI PM entry point syntax changed, so don't support suspend/resume */ +#undef CONFIG_PM + +#endif /* 2.4.6 => 2.4.3 */ + +/*****************************************************************************/ +/* 2.4.10 => 2.4.9 */ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,10) ) + +/**************************************/ +/* MODULE API */ + +#ifndef MODULE_LICENSE + #define MODULE_LICENSE(X) +#endif + +/**************************************/ +/* OTHER */ + +#undef min +#define min(x,y) ({ \ + const typeof(x) _x = (x); \ + const typeof(y) _y = (y); \ + (void) (&_x == &_y); \ + _x < _y ? _x : _y; }) + +#undef max +#define max(x,y) ({ \ + const typeof(x) _x = (x); \ + const typeof(y) _y = (y); \ + (void) (&_x == &_y); \ + _x > _y ? _x : _y; }) + +#define min_t(type,x,y) ({ \ + type _x = (x); \ + type _y = (y); \ + _x < _y ? _x : _y; }) + +#define max_t(type,x,y) ({ \ + type _x = (x); \ + type _y = (y); \ + _x > _y ? _x : _y; }) + +#ifndef list_for_each_safe +#define list_for_each_safe(pos, n, head) \ + for (pos = (head)->next, n = pos->next; pos != (head); \ + pos = n, n = pos->next) +#endif + +#ifndef ____cacheline_aligned_in_smp +#ifdef CONFIG_SMP +#define ____cacheline_aligned_in_smp ____cacheline_aligned +#else +#define ____cacheline_aligned_in_smp +#endif /* CONFIG_SMP */ +#endif + +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,8) ) +int _kc_snprintf(char * buf, size_t size, const char *fmt, ...); +#define snprintf(buf, size, fmt, args...) _kc_snprintf(buf, size, fmt, ##args) +int _kc_vsnprintf(char *buf, size_t size, const char *fmt, va_list args); +#define vsnprintf(buf, size, fmt, args) _kc_vsnprintf(buf, size, fmt, args) +#else /* 2.4.8 => 2.4.9 */ +int snprintf(char * buf, size_t size, const char *fmt, ...); +int vsnprintf(char *buf, size_t size, const char *fmt, va_list args); +#endif +#endif /* 2.4.10 -> 2.4.6 */ + + +/*****************************************************************************/ +/* 2.4.12 => 2.4.10 */ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,12) ) +#ifndef HAVE_NETIF_MSG +#define HAVE_NETIF_MSG 1 +enum { + NETIF_MSG_DRV = 0x0001, + NETIF_MSG_PROBE = 0x0002, + NETIF_MSG_LINK = 0x0004, + NETIF_MSG_TIMER = 0x0008, + NETIF_MSG_IFDOWN = 0x0010, + NETIF_MSG_IFUP = 0x0020, + NETIF_MSG_RX_ERR = 0x0040, + NETIF_MSG_TX_ERR = 0x0080, + NETIF_MSG_TX_QUEUED = 0x0100, + NETIF_MSG_INTR = 0x0200, + NETIF_MSG_TX_DONE = 0x0400, + NETIF_MSG_RX_STATUS = 0x0800, + NETIF_MSG_PKTDATA = 0x1000, + NETIF_MSG_HW = 0x2000, + NETIF_MSG_WOL = 0x4000, +}; + +#define netif_msg_drv(p) ((p)->msg_enable & NETIF_MSG_DRV) +#define netif_msg_probe(p) ((p)->msg_enable & NETIF_MSG_PROBE) +#define netif_msg_link(p) ((p)->msg_enable & NETIF_MSG_LINK) +#define netif_msg_timer(p) ((p)->msg_enable & NETIF_MSG_TIMER) +#define netif_msg_ifdown(p) ((p)->msg_enable & NETIF_MSG_IFDOWN) +#define netif_msg_ifup(p) ((p)->msg_enable & NETIF_MSG_IFUP) +#define netif_msg_rx_err(p) ((p)->msg_enable & NETIF_MSG_RX_ERR) +#define netif_msg_tx_err(p) ((p)->msg_enable & NETIF_MSG_TX_ERR) +#define netif_msg_tx_queued(p) ((p)->msg_enable & NETIF_MSG_TX_QUEUED) +#define netif_msg_intr(p) ((p)->msg_enable & NETIF_MSG_INTR) +#define netif_msg_tx_done(p) ((p)->msg_enable & NETIF_MSG_TX_DONE) +#define netif_msg_rx_status(p) ((p)->msg_enable & NETIF_MSG_RX_STATUS) +#define netif_msg_pktdata(p) ((p)->msg_enable & NETIF_MSG_PKTDATA) +#endif /* !HAVE_NETIF_MSG */ +#endif /* 2.4.12 => 2.4.10 */ + +/*****************************************************************************/ +/* 2.4.13 => 2.4.12 */ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,13) ) + +/**************************************/ +/* PCI DMA MAPPING */ + +#ifndef virt_to_page + #define virt_to_page(v) (mem_map + (virt_to_phys(v) >> PAGE_SHIFT)) +#endif + +#ifndef pci_map_page +#define pci_map_page _kc_pci_map_page +u64 _kc_pci_map_page(struct pci_dev *dev, struct page *page, unsigned long offset, size_t size, int direction); +#endif + +#ifndef pci_unmap_page +#define pci_unmap_page _kc_pci_unmap_page +void _kc_pci_unmap_page(struct pci_dev *dev, u64 dma_addr, size_t size, int direction); +#endif + +/* pci_set_dma_mask takes dma_addr_t, which is only 32-bits prior to 2.4.13 */ + +#undef DMA_32BIT_MASK +#define DMA_32BIT_MASK 0xffffffff +#undef DMA_64BIT_MASK +#define DMA_64BIT_MASK 0xffffffff + +/**************************************/ +/* OTHER */ + +#ifndef cpu_relax +#define cpu_relax() rep_nop() +#endif + +struct vlan_ethhdr { + unsigned char h_dest[ETH_ALEN]; + unsigned char h_source[ETH_ALEN]; + unsigned short h_vlan_proto; + unsigned short h_vlan_TCI; + unsigned short h_vlan_encapsulated_proto; +}; +#endif /* 2.4.13 => 2.4.12 */ + +/*****************************************************************************/ +/* 2.4.17 => 2.4.12 */ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,17) ) + +#ifndef __devexit_p + #define __devexit_p(x) &(x) +#endif + +#endif /* 2.4.17 => 2.4.13 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,18) ) +#define NETIF_MSG_HW 0x2000 +#define NETIF_MSG_WOL 0x4000 + +#ifndef netif_msg_hw +#define netif_msg_hw(p) ((p)->msg_enable & NETIF_MSG_HW) +#endif +#ifndef netif_msg_wol +#define netif_msg_wol(p) ((p)->msg_enable & NETIF_MSG_WOL) +#endif +#endif /* 2.4.18 */ + +/*****************************************************************************/ + +/*****************************************************************************/ +/* 2.4.20 => 2.4.19 */ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,20) ) + +/* we won't support NAPI on less than 2.4.20 */ +#ifdef NAPI +#undef NAPI +#endif + +#endif /* 2.4.20 => 2.4.19 */ + +/*****************************************************************************/ +/* 2.4.22 => 2.4.17 */ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,22) ) +#define pci_name(x) ((x)->slot_name) + +#ifndef SUPPORTED_10000baseT_Full +#define SUPPORTED_10000baseT_Full BIT(12) +#endif +#ifndef ADVERTISED_10000baseT_Full +#define ADVERTISED_10000baseT_Full BIT(12) +#endif +#endif + +/*****************************************************************************/ +/*****************************************************************************/ +/* 2.4.23 => 2.4.22 */ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,23) ) +/*****************************************************************************/ +#ifdef NAPI +#ifndef netif_poll_disable +#define netif_poll_disable(x) _kc_netif_poll_disable(x) +static inline void _kc_netif_poll_disable(struct net_device *netdev) +{ + while (test_and_set_bit(__LINK_STATE_RX_SCHED, &netdev->state)) { + /* No hurry */ + current->state = TASK_INTERRUPTIBLE; + schedule_timeout(1); + } +} +#endif +#ifndef netif_poll_enable +#define netif_poll_enable(x) _kc_netif_poll_enable(x) +static inline void _kc_netif_poll_enable(struct net_device *netdev) +{ + clear_bit(__LINK_STATE_RX_SCHED, &netdev->state); +} +#endif +#endif /* NAPI */ +#ifndef netif_tx_disable +#define netif_tx_disable(x) _kc_netif_tx_disable(x) +static inline void _kc_netif_tx_disable(struct net_device *dev) +{ + spin_lock_bh(&dev->xmit_lock); + netif_stop_queue(dev); + spin_unlock_bh(&dev->xmit_lock); +} +#endif +#else /* 2.4.23 => 2.4.22 */ +#define HAVE_SCTP +#endif /* 2.4.23 => 2.4.22 */ + +/*****************************************************************************/ +/* 2.6.4 => 2.6.0 */ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,25) || \ + ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) && \ + LINUX_VERSION_CODE < KERNEL_VERSION(2,6,4) ) ) +#define ETHTOOL_OPS_COMPAT +#endif /* 2.6.4 => 2.6.0 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,27) ) +#define __user +#endif /* < 2.4.27 */ + +/*****************************************************************************/ +/* 2.5.71 => 2.4.x */ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,5,71) ) +#define sk_protocol protocol +#define pci_get_device pci_find_device +#endif /* 2.5.70 => 2.4.x */ + +/*****************************************************************************/ +/* < 2.4.27 or 2.6.0 <= 2.6.5 */ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,27) || \ + ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) && \ + LINUX_VERSION_CODE < KERNEL_VERSION(2,6,5) ) ) + +#ifndef netif_msg_init +#define netif_msg_init _kc_netif_msg_init +static inline u32 _kc_netif_msg_init(int debug_value, int default_msg_enable_bits) +{ + /* use default */ + if (debug_value < 0 || debug_value >= (sizeof(u32) * 8)) + return default_msg_enable_bits; + if (debug_value == 0) /* no output */ + return 0; + /* set low N bits */ + return (1 << debug_value) -1; +} +#endif + +#endif /* < 2.4.27 or 2.6.0 <= 2.6.5 */ +/*****************************************************************************/ +#if (( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,27) ) || \ + (( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) ) && \ + ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,3) ))) +#define netdev_priv(x) x->priv +#endif + +/*****************************************************************************/ +/* <= 2.5.0 */ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) ) +#include +#undef pci_register_driver +#define pci_register_driver pci_module_init + +/* + * Most of the dma compat code is copied/modifed from the 2.4.37 + * /include/linux/libata-compat.h header file + */ +/* These definitions mirror those in pci.h, so they can be used + * interchangeably with their PCI_ counterparts */ +enum dma_data_direction { + DMA_BIDIRECTIONAL = 0, + DMA_TO_DEVICE = 1, + DMA_FROM_DEVICE = 2, + DMA_NONE = 3, +}; + +struct device { + struct pci_dev pdev; +}; + +static inline struct pci_dev *to_pci_dev (struct device *dev) +{ + return (struct pci_dev *) dev; +} +static inline struct device *pci_dev_to_dev(struct pci_dev *pdev) +{ + return (struct device *) pdev; +} +#define pdev_printk(lvl, pdev, fmt, args...) \ + printk("%s %s: " fmt, lvl, pci_name(pdev), ## args) +#define dev_err(dev, fmt, args...) \ + pdev_printk(KERN_ERR, to_pci_dev(dev), fmt, ## args) +#define dev_info(dev, fmt, args...) \ + pdev_printk(KERN_INFO, to_pci_dev(dev), fmt, ## args) +#define dev_warn(dev, fmt, args...) \ + pdev_printk(KERN_WARNING, to_pci_dev(dev), fmt, ## args) +#define dev_notice(dev, fmt, args...) \ + pdev_printk(KERN_NOTICE, to_pci_dev(dev), fmt, ## args) +#define dev_dbg(dev, fmt, args...) \ + pdev_printk(KERN_DEBUG, to_pci_dev(dev), fmt, ## args) + +/* NOTE: dangerous! we ignore the 'gfp' argument */ +#define dma_alloc_coherent(dev,sz,dma,gfp) \ + pci_alloc_consistent(to_pci_dev(dev),(sz),(dma)) +#define dma_free_coherent(dev,sz,addr,dma_addr) \ + pci_free_consistent(to_pci_dev(dev),(sz),(addr),(dma_addr)) + +#define dma_map_page(dev,a,b,c,d) \ + pci_map_page(to_pci_dev(dev),(a),(b),(c),(d)) +#define dma_unmap_page(dev,a,b,c) \ + pci_unmap_page(to_pci_dev(dev),(a),(b),(c)) + +#define dma_map_single(dev,a,b,c) \ + pci_map_single(to_pci_dev(dev),(a),(b),(c)) +#define dma_unmap_single(dev,a,b,c) \ + pci_unmap_single(to_pci_dev(dev),(a),(b),(c)) + +#define dma_map_sg(dev, sg, nents, dir) \ + pci_map_sg(to_pci_dev(dev), (sg), (nents), (dir) +#define dma_unmap_sg(dev, sg, nents, dir) \ + pci_unmap_sg(to_pci_dev(dev), (sg), (nents), (dir) + +#define dma_sync_single(dev,a,b,c) \ + pci_dma_sync_single(to_pci_dev(dev),(a),(b),(c)) + +/* for range just sync everything, that's all the pci API can do */ +#define dma_sync_single_range(dev,addr,off,sz,dir) \ + pci_dma_sync_single(to_pci_dev(dev),(addr),(off)+(sz),(dir)) + +#define dma_set_mask(dev,mask) \ + pci_set_dma_mask(to_pci_dev(dev),(mask)) + +/* hlist_* code - double linked lists */ +struct hlist_head { + struct hlist_node *first; +}; + +struct hlist_node { + struct hlist_node *next, **pprev; +}; + +static inline void __hlist_del(struct hlist_node *n) +{ + struct hlist_node *next = n->next; + struct hlist_node **pprev = n->pprev; + *pprev = next; + if (next) + next->pprev = pprev; +} + +static inline void hlist_del(struct hlist_node *n) +{ + __hlist_del(n); + n->next = NULL; + n->pprev = NULL; +} + +static inline void hlist_add_head(struct hlist_node *n, struct hlist_head *h) +{ + struct hlist_node *first = h->first; + n->next = first; + if (first) + first->pprev = &n->next; + h->first = n; + n->pprev = &h->first; +} + +static inline int hlist_empty(const struct hlist_head *h) +{ + return !h->first; +} +#define HLIST_HEAD_INIT { .first = NULL } +#define HLIST_HEAD(name) struct hlist_head name = { .first = NULL } +#define INIT_HLIST_HEAD(ptr) ((ptr)->first = NULL) +static inline void INIT_HLIST_NODE(struct hlist_node *h) +{ + h->next = NULL; + h->pprev = NULL; +} + +#ifndef might_sleep +#define might_sleep() +#endif +#else +static inline struct device *pci_dev_to_dev(struct pci_dev *pdev) +{ + return &pdev->dev; +} +#endif /* <= 2.5.0 */ + +/*****************************************************************************/ +/* 2.5.28 => 2.4.23 */ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,5,28) ) + +#include +#define work_struct tq_struct +#undef INIT_WORK +#define INIT_WORK(a,b) INIT_TQUEUE(a,(void (*)(void *))b,a) +#undef container_of +#define container_of list_entry +#define schedule_work schedule_task +#define flush_scheduled_work flush_scheduled_tasks +#define cancel_work_sync(x) flush_scheduled_work() + +#endif /* 2.5.28 => 2.4.17 */ + +/*****************************************************************************/ +/* 2.6.0 => 2.5.28 */ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ) +#ifndef read_barrier_depends +#define read_barrier_depends() rmb() +#endif + +#ifndef rcu_head +struct __kc_callback_head { + struct __kc_callback_head *next; + void (*func)(struct callback_head *head); +}; +#define rcu_head __kc_callback_head +#endif + +#undef get_cpu +#define get_cpu() smp_processor_id() +#undef put_cpu +#define put_cpu() do { } while(0) +#define MODULE_INFO(version, _version) +#ifndef CONFIG_E1000_DISABLE_PACKET_SPLIT +#define CONFIG_E1000_DISABLE_PACKET_SPLIT 1 +#endif +#ifndef CONFIG_IGB_DISABLE_PACKET_SPLIT +#define CONFIG_IGB_DISABLE_PACKET_SPLIT 1 +#endif +#ifndef CONFIG_IGC_DISABLE_PACKET_SPLIT +#define CONFIG_IGC_DISABLE_PACKET_SPLIT 1 +#endif + +#define dma_set_coherent_mask(dev,mask) 1 + +#undef dev_put +#define dev_put(dev) __dev_put(dev) + +#ifndef skb_fill_page_desc +#define skb_fill_page_desc _kc_skb_fill_page_desc +void _kc_skb_fill_page_desc(struct sk_buff *skb, int i, struct page *page, int off, int size); +#endif + +#undef ALIGN +#define ALIGN(x,a) (((x)+(a)-1)&~((a)-1)) + +#ifndef page_count +#define page_count(p) atomic_read(&(p)->count) +#endif + +#ifdef MAX_NUMNODES +#undef MAX_NUMNODES +#endif +#define MAX_NUMNODES 1 + +/* find_first_bit and find_next bit are not defined for most + * 2.4 kernels (except for the redhat 2.4.21 kernels + */ +#include +#define BITOP_WORD(nr) ((nr) / BITS_PER_LONG) +#undef find_next_bit +#define find_next_bit _kc_find_next_bit +unsigned long _kc_find_next_bit(const unsigned long *addr, unsigned long size, + unsigned long offset); +#define find_first_bit(addr, size) find_next_bit((addr), (size), 0) + +#ifndef netdev_name +static inline const char *_kc_netdev_name(const struct net_device *dev) +{ + if (strchr(dev->name, '%')) + return "(unregistered net_device)"; + return dev->name; +} +#define netdev_name(netdev) _kc_netdev_name(netdev) +#endif /* netdev_name */ + +#ifndef strlcpy +#define strlcpy _kc_strlcpy +size_t _kc_strlcpy(char *dest, const char *src, size_t size); +#endif /* strlcpy */ + +#ifndef do_div +#if BITS_PER_LONG == 64 +# define do_div(n,base) ({ \ + uint32_t __base = (base); \ + uint32_t __rem; \ + __rem = ((uint64_t)(n)) % __base; \ + (n) = ((uint64_t)(n)) / __base; \ + __rem; \ + }) +#elif BITS_PER_LONG == 32 +uint32_t _kc__div64_32(uint64_t *dividend, uint32_t divisor); +# define do_div(n,base) ({ \ + uint32_t __base = (base); \ + uint32_t __rem; \ + if (likely(((n) >> 32) == 0)) { \ + __rem = (uint32_t)(n) % __base; \ + (n) = (uint32_t)(n) / __base; \ + } else \ + __rem = _kc__div64_32(&(n), __base); \ + __rem; \ + }) +#else /* BITS_PER_LONG == ?? */ +# error do_div() does not yet support the C64 +#endif /* BITS_PER_LONG */ +#endif /* do_div */ + +#ifndef NSEC_PER_SEC +#define NSEC_PER_SEC 1000000000L +#endif + +#undef HAVE_I2C_SUPPORT +#else /* 2.6.0 */ + +#endif /* 2.6.0 => 2.5.28 */ +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,3) ) +#define dma_pool pci_pool +#define dma_pool_destroy pci_pool_destroy +#define dma_pool_alloc pci_pool_alloc +#define dma_pool_free pci_pool_free + +#define dma_pool_create(name,dev,size,align,allocation) \ + pci_pool_create((name),to_pci_dev(dev),(size),(align),(allocation)) +#endif /* < 2.6.3 */ + +/*****************************************************************************/ +/* 2.6.4 => 2.6.0 */ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,4) ) +#define MODULE_VERSION(_version) MODULE_INFO(version, _version) +#endif /* 2.6.4 => 2.6.0 */ + +/*****************************************************************************/ +/* 2.6.5 => 2.6.0 */ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,5) ) +#define dma_sync_single_for_cpu dma_sync_single +#define dma_sync_single_for_device dma_sync_single +#define dma_sync_single_range_for_cpu dma_sync_single_range +#define dma_sync_single_range_for_device dma_sync_single_range +#ifndef pci_dma_mapping_error +#define pci_dma_mapping_error _kc_pci_dma_mapping_error +static inline int _kc_pci_dma_mapping_error(dma_addr_t dma_addr) +{ + return dma_addr == 0; +} +#endif +#endif /* 2.6.5 => 2.6.0 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,4) ) +int _kc_scnprintf(char * buf, size_t size, const char *fmt, ...); +#define scnprintf(buf, size, fmt, args...) _kc_scnprintf(buf, size, fmt, ##args) +#endif /* < 2.6.4 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,6) ) +/* taken from 2.6 include/linux/bitmap.h */ +#undef bitmap_zero +#define bitmap_zero _kc_bitmap_zero +static inline void _kc_bitmap_zero(unsigned long *dst, int nbits) +{ + if (nbits <= BITS_PER_LONG) + *dst = 0UL; + else { + int len = BITS_TO_LONGS(nbits) * sizeof(unsigned long); + memset(dst, 0, len); + } +} +#define page_to_nid(x) 0 + +#endif /* < 2.6.6 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,7) ) +#undef if_mii +#define if_mii _kc_if_mii +static inline struct mii_ioctl_data *_kc_if_mii(struct ifreq *rq) +{ + return (struct mii_ioctl_data *) &rq->ifr_ifru; +} + +#ifndef __force +#define __force +#endif +#endif /* < 2.6.7 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,8) ) +#ifndef PCI_EXP_DEVCTL +#define PCI_EXP_DEVCTL 8 +#endif +#ifndef PCI_EXP_DEVCTL_CERE +#define PCI_EXP_DEVCTL_CERE 0x0001 +#endif +#define PCI_EXP_FLAGS 2 /* Capabilities register */ +#define PCI_EXP_FLAGS_VERS 0x000f /* Capability version */ +#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ +#define PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */ +#define PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */ +#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ +#define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */ +#define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */ +#define PCI_EXP_DEVCAP 4 /* Device capabilities */ +#define PCI_EXP_DEVSTA 10 /* Device Status */ +#define msleep(x) do { set_current_state(TASK_UNINTERRUPTIBLE); \ + schedule_timeout((x * HZ)/1000 + 2); \ + } while (0) + +#endif /* < 2.6.8 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,9)) +#include +#define __iomem + +#ifndef kcalloc +#define kcalloc(n, size, flags) _kc_kzalloc(((n) * (size)), flags) +void *_kc_kzalloc(size_t size, int flags); +#endif +#define MSEC_PER_SEC 1000L +static inline unsigned int _kc_jiffies_to_msecs(const unsigned long j) +{ +#if HZ <= MSEC_PER_SEC && !(MSEC_PER_SEC % HZ) + return (MSEC_PER_SEC / HZ) * j; +#elif HZ > MSEC_PER_SEC && !(HZ % MSEC_PER_SEC) + return (j + (HZ / MSEC_PER_SEC) - 1)/(HZ / MSEC_PER_SEC); +#else + return (j * MSEC_PER_SEC) / HZ; +#endif +} +static inline unsigned long _kc_msecs_to_jiffies(const unsigned int m) +{ + if (m > _kc_jiffies_to_msecs(MAX_JIFFY_OFFSET)) + return MAX_JIFFY_OFFSET; +#if HZ <= MSEC_PER_SEC && !(MSEC_PER_SEC % HZ) + return (m + (MSEC_PER_SEC / HZ) - 1) / (MSEC_PER_SEC / HZ); +#elif HZ > MSEC_PER_SEC && !(HZ % MSEC_PER_SEC) + return m * (HZ / MSEC_PER_SEC); +#else + return (m * HZ + MSEC_PER_SEC - 1) / MSEC_PER_SEC; +#endif +} + +#define msleep_interruptible _kc_msleep_interruptible +static inline unsigned long _kc_msleep_interruptible(unsigned int msecs) +{ + unsigned long timeout = _kc_msecs_to_jiffies(msecs) + 1; + + while (timeout && !signal_pending(current)) { + __set_current_state(TASK_INTERRUPTIBLE); + timeout = schedule_timeout(timeout); + } + return _kc_jiffies_to_msecs(timeout); +} + +/* Basic mode control register. */ +#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ + +#ifndef __le16 +#define __le16 u16 +#endif +#ifndef __le32 +#define __le32 u32 +#endif +#ifndef __le64 +#define __le64 u64 +#endif +#ifndef __be16 +#define __be16 u16 +#endif +#ifndef __be32 +#define __be32 u32 +#endif +#ifndef __be64 +#define __be64 u64 +#endif + +static inline struct vlan_ethhdr *vlan_eth_hdr(const struct sk_buff *skb) +{ + return (struct vlan_ethhdr *)skb->mac.raw; +} + +/* Wake-On-Lan options. */ +#define WAKE_PHY BIT(0) +#define WAKE_UCAST BIT(1) +#define WAKE_MCAST BIT(2) +#define WAKE_BCAST BIT(3) +#define WAKE_ARP BIT(4) +#define WAKE_MAGIC BIT(5) +#define WAKE_MAGICSECURE BIT(6) /* only meaningful if WAKE_MAGIC */ + +#define skb_header_pointer _kc_skb_header_pointer +static inline void *_kc_skb_header_pointer(const struct sk_buff *skb, + int offset, int len, void *buffer) +{ + int hlen = skb_headlen(skb); + + if (hlen - offset >= len) + return skb->data + offset; + +#ifdef MAX_SKB_FRAGS + if (skb_copy_bits(skb, offset, buffer, len) < 0) + return NULL; + + return buffer; +#else + return NULL; +#endif + +#ifndef NETDEV_TX_OK +#define NETDEV_TX_OK 0 +#endif +#ifndef NETDEV_TX_BUSY +#define NETDEV_TX_BUSY 1 +#endif +#ifndef NETDEV_TX_LOCKED +#define NETDEV_TX_LOCKED -1 +#endif +} + +#ifndef __bitwise +#define __bitwise +#endif +#endif /* < 2.6.9 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10) ) +#ifdef module_param_array_named +#undef module_param_array_named +#define module_param_array_named(name, array, type, nump, perm) \ + static struct kparam_array __param_arr_##name \ + = { ARRAY_SIZE(array), nump, param_set_##type, param_get_##type, \ + sizeof(array[0]), array }; \ + module_param_call(name, param_array_set, param_array_get, \ + &__param_arr_##name, perm) +#endif /* module_param_array_named */ +/* + * num_online is broken for all < 2.6.10 kernels. This is needed to support + * Node module parameter of ixgbe. + */ +#undef num_online_nodes +#define num_online_nodes(n) 1 +extern DECLARE_BITMAP(_kcompat_node_online_map, MAX_NUMNODES); +#undef node_online_map +#define node_online_map _kcompat_node_online_map +#define pci_get_class pci_find_class +#endif /* < 2.6.10 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) ) +#define PCI_D0 0 +#define PCI_D1 1 +#define PCI_D2 2 +#define PCI_D3hot 3 +#define PCI_D3cold 4 +typedef int pci_power_t; +#define pci_choose_state(pdev,state) state +#define PMSG_SUSPEND 3 +#define PCI_EXP_LNKCTL 16 + +#undef NETIF_F_LLTX + +#ifndef ARCH_HAS_PREFETCH +#define prefetch(X) +#endif + +#ifndef NET_IP_ALIGN +#define NET_IP_ALIGN 2 +#endif + +#define KC_USEC_PER_SEC 1000000L +#define usecs_to_jiffies _kc_usecs_to_jiffies +static inline unsigned int _kc_jiffies_to_usecs(const unsigned long j) +{ +#if HZ <= KC_USEC_PER_SEC && !(KC_USEC_PER_SEC % HZ) + return (KC_USEC_PER_SEC / HZ) * j; +#elif HZ > KC_USEC_PER_SEC && !(HZ % KC_USEC_PER_SEC) + return (j + (HZ / KC_USEC_PER_SEC) - 1)/(HZ / KC_USEC_PER_SEC); +#else + return (j * KC_USEC_PER_SEC) / HZ; +#endif +} +static inline unsigned long _kc_usecs_to_jiffies(const unsigned int m) +{ + if (m > _kc_jiffies_to_usecs(MAX_JIFFY_OFFSET)) + return MAX_JIFFY_OFFSET; +#if HZ <= KC_USEC_PER_SEC && !(KC_USEC_PER_SEC % HZ) + return (m + (KC_USEC_PER_SEC / HZ) - 1) / (KC_USEC_PER_SEC / HZ); +#elif HZ > KC_USEC_PER_SEC && !(HZ % KC_USEC_PER_SEC) + return m * (HZ / KC_USEC_PER_SEC); +#else + return (m * HZ + KC_USEC_PER_SEC - 1) / KC_USEC_PER_SEC; +#endif +} + +#define PCI_EXP_LNKCAP 12 /* Link Capabilities */ +#define PCI_EXP_LNKSTA 18 /* Link Status */ +#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ +#define PCI_EXP_SLTCTL 24 /* Slot Control */ +#define PCI_EXP_SLTSTA 26 /* Slot Status */ +#define PCI_EXP_RTCTL 28 /* Root Control */ +#define PCI_EXP_RTCAP 30 /* Root Capabilities */ +#define PCI_EXP_RTSTA 32 /* Root Status */ +#endif /* < 2.6.11 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,12) ) +#include +#define USE_REBOOT_NOTIFIER + +/* Generic MII registers. */ +#define MII_CTRL1000 0x09 /* 1000BASE-T control */ +#define MII_STAT1000 0x0a /* 1000BASE-T status */ +/* Advertisement control register. */ +#define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */ +#define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymmetric pause */ +/* Link partner ability register. */ +#define LPA_PAUSE_CAP 0x0400 /* Can pause */ +#define LPA_PAUSE_ASYM 0x0800 /* Can pause asymetrically */ +/* 1000BASE-T Control register */ +#define ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */ +#define ADVERTISE_1000HALF 0x0100 /* Advertise 1000BASE-T half duplex */ +/* 1000BASE-T Status register */ +#define LPA_1000LOCALRXOK 0x2000 /* Link partner local receiver status */ +#define LPA_1000REMRXOK 0x1000 /* Link partner remote receiver status */ + +#ifndef is_zero_ether_addr +#define is_zero_ether_addr _kc_is_zero_ether_addr +static inline int _kc_is_zero_ether_addr(const u8 *addr) +{ + return !(addr[0] | addr[1] | addr[2] | addr[3] | addr[4] | addr[5]); +} +#endif /* is_zero_ether_addr */ +#ifndef is_multicast_ether_addr +#define is_multicast_ether_addr _kc_is_multicast_ether_addr +static inline int _kc_is_multicast_ether_addr(const u8 *addr) +{ + return addr[0] & 0x01; +} +#endif /* is_multicast_ether_addr */ +#endif /* < 2.6.12 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,13) ) +#ifndef kstrdup +#define kstrdup _kc_kstrdup +char *_kc_kstrdup(const char *s, unsigned int gfp); +#endif +#endif /* < 2.6.13 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,14) ) +#define pm_message_t u32 +#ifndef kzalloc +#define kzalloc _kc_kzalloc +void *_kc_kzalloc(size_t size, int flags); +#endif + +/* Generic MII registers. */ +#define MII_ESTATUS 0x0f /* Extended Status */ +/* Basic mode status register. */ +#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */ +/* Extended status register. */ +#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */ +#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */ + +#define SUPPORTED_Pause BIT(13) +#define SUPPORTED_Asym_Pause BIT(14) +#define ADVERTISED_Pause BIT(13) +#define ADVERTISED_Asym_Pause BIT(14) + +#if (!(RHEL_RELEASE_CODE && \ + (RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(4,3)) && \ + (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(5,0)))) +#if ((LINUX_VERSION_CODE == KERNEL_VERSION(2,6,9)) && !defined(gfp_t)) +#define gfp_t unsigned +#else +typedef unsigned gfp_t; +#endif +#endif /* !RHEL4.3->RHEL5.0 */ + +#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,9) ) +#ifdef CONFIG_X86_64 +#define dma_sync_single_range_for_cpu(dev, addr, off, sz, dir) \ + dma_sync_single_for_cpu((dev), (addr), (off) + (sz), (dir)) +#define dma_sync_single_range_for_device(dev, addr, off, sz, dir) \ + dma_sync_single_for_device((dev), (addr), (off) + (sz), (dir)) +#endif +#endif +#endif /* < 2.6.14 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,15) ) +#ifndef kfree_rcu +/* this is placed here due to a lack of rcu_barrier in previous kernels */ +#define kfree_rcu(_ptr, _offset) kfree(_ptr) +#endif /* kfree_rcu */ +#ifndef vmalloc_node +#define vmalloc_node(a,b) vmalloc(a) +#endif /* vmalloc_node*/ + +#define setup_timer(_timer, _function, _data) \ +do { \ + (_timer)->function = _function; \ + (_timer)->data = _data; \ + init_timer(_timer); \ +} while (0) +#ifndef device_can_wakeup +#define device_can_wakeup(dev) (1) +#endif +#ifndef device_set_wakeup_enable +#define device_set_wakeup_enable(dev, val) do{}while(0) +#endif +#ifndef device_init_wakeup +#define device_init_wakeup(dev,val) do {} while (0) +#endif +static inline unsigned _kc_compare_ether_addr(const u8 *addr1, const u8 *addr2) +{ + const u16 *a = (const u16 *) addr1; + const u16 *b = (const u16 *) addr2; + + return ((a[0] ^ b[0]) | (a[1] ^ b[1]) | (a[2] ^ b[2])) != 0; +} +#undef compare_ether_addr +#define compare_ether_addr(addr1, addr2) _kc_compare_ether_addr(addr1, addr2) +#endif /* < 2.6.15 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,16) ) +#undef DEFINE_MUTEX +#define DEFINE_MUTEX(x) DECLARE_MUTEX(x) +#define mutex_lock(x) down_interruptible(x) +#define mutex_unlock(x) up(x) + +#ifndef ____cacheline_internodealigned_in_smp +#ifdef CONFIG_SMP +#define ____cacheline_internodealigned_in_smp ____cacheline_aligned_in_smp +#else +#define ____cacheline_internodealigned_in_smp +#endif /* CONFIG_SMP */ +#endif /* ____cacheline_internodealigned_in_smp */ +#undef HAVE_PCI_ERS +#else /* 2.6.16 and above */ +#undef HAVE_PCI_ERS +#define HAVE_PCI_ERS +#if ( SLE_VERSION_CODE && SLE_VERSION_CODE == SLE_VERSION(10,4,0) ) +#ifdef device_can_wakeup +#undef device_can_wakeup +#endif /* device_can_wakeup */ +#define device_can_wakeup(dev) 1 +#endif /* SLE_VERSION(10,4,0) */ +#endif /* < 2.6.16 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,17) ) +#ifndef dev_notice +#define dev_notice(dev, fmt, args...) \ + dev_printk(KERN_NOTICE, dev, fmt, ## args) +#endif + +#ifndef first_online_node +#define first_online_node 0 +#endif +#ifndef NET_SKB_PAD +#define NET_SKB_PAD 16 +#endif +#endif /* < 2.6.17 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) ) + +#ifndef IRQ_HANDLED +#define irqreturn_t void +#define IRQ_HANDLED +#define IRQ_NONE +#endif + +#ifndef IRQF_PROBE_SHARED +#ifdef SA_PROBEIRQ +#define IRQF_PROBE_SHARED SA_PROBEIRQ +#else +#define IRQF_PROBE_SHARED 0 +#endif +#endif + +#ifndef IRQF_SHARED +#define IRQF_SHARED SA_SHIRQ +#endif + +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) +#endif + +#ifndef skb_is_gso +#ifdef NETIF_F_TSO +#define skb_is_gso _kc_skb_is_gso +static inline int _kc_skb_is_gso(const struct sk_buff *skb) +{ + return skb_shinfo(skb)->gso_size; +} +#else +#define skb_is_gso(a) 0 +#endif +#endif + +#ifndef resource_size_t +#define resource_size_t unsigned long +#endif + +#ifdef skb_pad +#undef skb_pad +#endif +#define skb_pad(x,y) _kc_skb_pad(x, y) +int _kc_skb_pad(struct sk_buff *skb, int pad); +#ifdef skb_padto +#undef skb_padto +#endif +#define skb_padto(x,y) _kc_skb_padto(x, y) +static inline int _kc_skb_padto(struct sk_buff *skb, unsigned int len) +{ + unsigned int size = skb->len; + if(likely(size >= len)) + return 0; + return _kc_skb_pad(skb, len - size); +} + +#ifndef DECLARE_PCI_UNMAP_ADDR +#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \ + dma_addr_t ADDR_NAME +#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \ + u32 LEN_NAME +#define pci_unmap_addr(PTR, ADDR_NAME) \ + ((PTR)->ADDR_NAME) +#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \ + (((PTR)->ADDR_NAME) = (VAL)) +#define pci_unmap_len(PTR, LEN_NAME) \ + ((PTR)->LEN_NAME) +#define pci_unmap_len_set(PTR, LEN_NAME, VAL) \ + (((PTR)->LEN_NAME) = (VAL)) +#endif /* DECLARE_PCI_UNMAP_ADDR */ +#endif /* < 2.6.18 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) ) +enum pcie_link_width { + PCIE_LNK_WIDTH_RESRV = 0x00, + PCIE_LNK_X1 = 0x01, + PCIE_LNK_X2 = 0x02, + PCIE_LNK_X4 = 0x04, + PCIE_LNK_X8 = 0x08, + PCIE_LNK_X12 = 0x0C, + PCIE_LNK_X16 = 0x10, + PCIE_LNK_X32 = 0x20, + PCIE_LNK_WIDTH_UNKNOWN = 0xFF, +}; + +#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(5,0))) +#define i_private u.generic_ip +#endif /* >= RHEL 5.0 */ + +#ifndef DIV_ROUND_UP +#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d)) +#endif +#ifndef __ALIGN_MASK +#define __ALIGN_MASK(x, mask) (((x) + (mask)) & ~(mask)) +#endif +#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0) ) +#if (!((RHEL_RELEASE_CODE && \ + ((RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(4,4) && \ + RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(5,0)) || \ + (RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(5,0)))))) +typedef irqreturn_t (*irq_handler_t)(int, void*, struct pt_regs *); +#endif +#if (RHEL_RELEASE_CODE && RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(6,0)) +#undef CONFIG_INET_LRO +#undef CONFIG_INET_LRO_MODULE +#endif +typedef irqreturn_t (*new_handler_t)(int, void*); +static inline irqreturn_t _kc_request_irq(unsigned int irq, new_handler_t handler, unsigned long flags, const char *devname, void *dev_id) +#else /* 2.4.x */ +typedef void (*irq_handler_t)(int, void*, struct pt_regs *); +typedef void (*new_handler_t)(int, void*); +static inline int _kc_request_irq(unsigned int irq, new_handler_t handler, unsigned long flags, const char *devname, void *dev_id) +#endif /* >= 2.5.x */ +{ + irq_handler_t new_handler = (irq_handler_t) handler; + return request_irq(irq, new_handler, flags, devname, dev_id); +} + +#undef request_irq +#define request_irq(irq, handler, flags, devname, dev_id) _kc_request_irq((irq), (handler), (flags), (devname), (dev_id)) + +#define irq_handler_t new_handler_t + +#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,11) ) +#ifndef skb_checksum_help +static inline int __kc_skb_checksum_help(struct sk_buff *skb) +{ + return skb_checksum_help(skb, 0); +} +#define skb_checksum_help(skb) __kc_skb_checksum_help((skb)) +#endif +#endif /* < 2.6.19 && >= 2.6.11 */ + +/* pci_restore_state and pci_save_state handles MSI/PCIE from 2.6.19 */ +#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(5,4))) +#define PCIE_CONFIG_SPACE_LEN 256 +#define PCI_CONFIG_SPACE_LEN 64 +#define PCIE_LINK_STATUS 0x12 +#define pci_config_space_ich8lan() do {} while(0) +#undef pci_save_state +int _kc_pci_save_state(struct pci_dev *); +#define pci_save_state(pdev) _kc_pci_save_state(pdev) +#undef pci_restore_state +void _kc_pci_restore_state(struct pci_dev *); +#define pci_restore_state(pdev) _kc_pci_restore_state(pdev) +#endif /* !(RHEL_RELEASE_CODE >= RHEL 5.4) */ + +#ifdef HAVE_PCI_ERS +#undef free_netdev +void _kc_free_netdev(struct net_device *); +#define free_netdev(netdev) _kc_free_netdev(netdev) +#endif +static inline int pci_enable_pcie_error_reporting(struct pci_dev __always_unused *dev) +{ + return 0; +} +#define pci_disable_pcie_error_reporting(dev) do {} while (0) +#define pci_cleanup_aer_uncorrect_error_status(dev) do {} while (0) + +void *_kc_kmemdup(const void *src, size_t len, unsigned gfp); +#define kmemdup(src, len, gfp) _kc_kmemdup(src, len, gfp) +#ifndef bool +#define bool _Bool +#define true 1 +#define false 0 +#endif +#else /* 2.6.19 */ +#include +#include + +#define NEW_SKB_CSUM_HELP +#endif /* < 2.6.19 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) ) +#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,28) ) +#undef INIT_WORK +#define INIT_WORK(_work, _func) \ +do { \ + INIT_LIST_HEAD(&(_work)->entry); \ + (_work)->pending = 0; \ + (_work)->func = (void (*)(void *))_func; \ + (_work)->data = _work; \ + init_timer(&(_work)->timer); \ +} while (0) +#endif + +#ifndef PCI_VDEVICE +#define PCI_VDEVICE(ven, dev) \ + PCI_VENDOR_ID_##ven, (dev), \ + PCI_ANY_ID, PCI_ANY_ID, 0, 0 +#endif + +#ifndef PCI_VENDOR_ID_INTEL +#define PCI_VENDOR_ID_INTEL 0x8086 +#endif + +#ifndef round_jiffies +#define round_jiffies(x) x +#endif + +#define csum_offset csum + +#define HAVE_EARLY_VMALLOC_NODE +#define dev_to_node(dev) -1 +#undef set_dev_node +/* remove compiler warning with b=b, for unused variable */ +#define set_dev_node(a, b) do { (b) = (b); } while(0) + +#if (!(RHEL_RELEASE_CODE && \ + (((RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(4,7)) && \ + (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(5,0))) || \ + (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(5,6)))) && \ + !(SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(10,2,0))) +typedef __u16 __bitwise __sum16; +typedef __u32 __bitwise __wsum; +#endif + +#if (!(RHEL_RELEASE_CODE && \ + (((RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(4,7)) && \ + (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(5,0))) || \ + (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(5,4)))) && \ + !(SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(10,2,0))) +static inline __wsum csum_unfold(__sum16 n) +{ + return (__force __wsum)n; +} +#endif + +#else /* < 2.6.20 */ +#define HAVE_DEVICE_NUMA_NODE +#endif /* < 2.6.20 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21) ) +#define to_net_dev(class) container_of(class, struct net_device, class_dev) +#define NETDEV_CLASS_DEV +#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(5,5))) +#define vlan_group_get_device(vg, id) (vg->vlan_devices[id]) +#define vlan_group_set_device(vg, id, dev) \ + do { \ + if (vg) vg->vlan_devices[id] = dev; \ + } while (0) +#endif /* !(RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(5,5)) */ +#define pci_channel_offline(pdev) (pdev->error_state && \ + pdev->error_state != pci_channel_io_normal) +#define pci_request_selected_regions(pdev, bars, name) \ + pci_request_regions(pdev, name) +#define pci_release_selected_regions(pdev, bars) pci_release_regions(pdev); + +#ifndef __aligned +#define __aligned(x) __attribute__((aligned(x))) +#endif + +struct pci_dev *_kc_netdev_to_pdev(struct net_device *netdev); +#define netdev_to_dev(netdev) \ + pci_dev_to_dev(_kc_netdev_to_pdev(netdev)) +#define devm_kzalloc(dev, size, flags) kzalloc(size, flags) +#define devm_kfree(dev, p) kfree(p) +#else /* 2.6.21 */ +static inline struct device *netdev_to_dev(struct net_device *netdev) +{ + return &netdev->dev; +} + +#endif /* < 2.6.21 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22) ) +#define tcp_hdr(skb) (skb->h.th) +#define tcp_hdrlen(skb) (skb->h.th->doff << 2) +#define skb_transport_offset(skb) (skb->h.raw - skb->data) +#define skb_transport_header(skb) (skb->h.raw) +#define ipv6_hdr(skb) (skb->nh.ipv6h) +#define ip_hdr(skb) (skb->nh.iph) +#define skb_network_offset(skb) (skb->nh.raw - skb->data) +#define skb_network_header(skb) (skb->nh.raw) +#define skb_tail_pointer(skb) skb->tail +#define skb_reset_tail_pointer(skb) \ + do { \ + skb->tail = skb->data; \ + } while (0) +#define skb_set_tail_pointer(skb, offset) \ + do { \ + skb->tail = skb->data + offset; \ + } while (0) +#define skb_copy_to_linear_data(skb, from, len) \ + memcpy(skb->data, from, len) +#define skb_copy_to_linear_data_offset(skb, offset, from, len) \ + memcpy(skb->data + offset, from, len) +#define skb_network_header_len(skb) (skb->h.raw - skb->nh.raw) +#define pci_register_driver pci_module_init +#define skb_mac_header(skb) skb->mac.raw + +#ifdef NETIF_F_MULTI_QUEUE +#ifndef alloc_etherdev_mq +#define alloc_etherdev_mq(_a, _b) alloc_etherdev(_a) +#endif +#endif /* NETIF_F_MULTI_QUEUE */ + +#ifndef ETH_FCS_LEN +#define ETH_FCS_LEN 4 +#endif +#define cancel_work_sync(x) flush_scheduled_work() +#ifndef udp_hdr +#define udp_hdr _udp_hdr +static inline struct udphdr *_udp_hdr(const struct sk_buff *skb) +{ + return (struct udphdr *)skb_transport_header(skb); +} +#endif + +#ifdef cpu_to_be16 +#undef cpu_to_be16 +#endif +#define cpu_to_be16(x) __constant_htons(x) + +#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(5,1))) +enum { + DUMP_PREFIX_NONE, + DUMP_PREFIX_ADDRESS, + DUMP_PREFIX_OFFSET +}; +#endif /* !(RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(5,1)) */ +#ifndef hex_asc +#define hex_asc(x) "0123456789abcdef"[x] +#endif +#include +void _kc_print_hex_dump(const char *level, const char *prefix_str, + int prefix_type, int rowsize, int groupsize, + const void *buf, size_t len, bool ascii); +#define print_hex_dump(lvl, s, t, r, g, b, l, a) \ + _kc_print_hex_dump(lvl, s, t, r, g, b, l, a) +#ifndef ADVERTISED_2500baseX_Full +#define ADVERTISED_2500baseX_Full BIT(15) +#endif +#ifndef SUPPORTED_2500baseX_Full +#define SUPPORTED_2500baseX_Full BIT(15) +#endif + +#ifndef ETH_P_PAUSE +#define ETH_P_PAUSE 0x8808 +#endif + +static inline int compound_order(struct page *page) +{ + return 0; +} + +#define __must_be_array(a) 0 + +#ifndef SKB_WITH_OVERHEAD +#define SKB_WITH_OVERHEAD(X) \ + ((X) - SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) +#endif +#else /* 2.6.22 */ +#define ETH_TYPE_TRANS_SETS_DEV +#define HAVE_NETDEV_STATS_IN_NETDEV +#endif /* < 2.6.22 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE > KERNEL_VERSION(2,6,22) ) +#endif /* > 2.6.22 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) ) +#define netif_subqueue_stopped(_a, _b) 0 +#ifndef PTR_ALIGN +#define PTR_ALIGN(p, a) ((typeof(p))ALIGN((unsigned long)(p), (a))) +#endif + +#ifndef CONFIG_PM_SLEEP +#define CONFIG_PM_SLEEP CONFIG_PM +#endif + +#if ( LINUX_VERSION_CODE > KERNEL_VERSION(2,6,13) ) +#define HAVE_ETHTOOL_GET_PERM_ADDR +#endif /* 2.6.14 through 2.6.22 */ + +static inline int __kc_skb_cow_head(struct sk_buff *skb, unsigned int headroom) +{ + int delta = 0; + + if (headroom > (skb->data - skb->head)) + delta = headroom - (skb->data - skb->head); + + if (delta || skb_header_cloned(skb)) + return pskb_expand_head(skb, ALIGN(delta, NET_SKB_PAD), 0, + GFP_ATOMIC); + return 0; +} +#define skb_cow_head(s, h) __kc_skb_cow_head((s), (h)) +#endif /* < 2.6.23 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) ) +#ifndef ETH_FLAG_LRO +#define ETH_FLAG_LRO NETIF_F_LRO +#endif + +#ifndef ACCESS_ONCE +#define ACCESS_ONCE(x) (*(volatile typeof(x) *)&(x)) +#endif + +/* if GRO is supported then the napi struct must already exist */ +#ifndef NETIF_F_GRO +/* NAPI API changes in 2.6.24 break everything */ +struct napi_struct { + /* used to look up the real NAPI polling routine */ + int (*poll)(struct napi_struct *, int); + struct net_device *dev; + int weight; +}; +#endif + +#ifdef NAPI +int __kc_adapter_clean(struct net_device *, int *); +/* The following definitions are multi-queue aware, and thus we have a driver + * define list which determines which drivers support multiple queues, and + * thus need these stronger defines. If a driver does not support multi-queue + * functionality, you don't need to add it to this list. + */ +struct net_device *napi_to_poll_dev(const struct napi_struct *napi); + +static inline void __kc_mq_netif_napi_add(struct net_device *dev, struct napi_struct *napi, + int (*poll)(struct napi_struct *, int), int weight) +{ + struct net_device *poll_dev = napi_to_poll_dev(napi); + poll_dev->poll = __kc_adapter_clean; + poll_dev->priv = napi; + poll_dev->weight = weight; + set_bit(__LINK_STATE_RX_SCHED, &poll_dev->state); + set_bit(__LINK_STATE_START, &poll_dev->state); + dev_hold(poll_dev); + napi->poll = poll; + napi->weight = weight; + napi->dev = dev; +} +#define netif_napi_add __kc_mq_netif_napi_add + +static inline void __kc_mq_netif_napi_del(struct napi_struct *napi) +{ + struct net_device *poll_dev = napi_to_poll_dev(napi); + WARN_ON(!test_bit(__LINK_STATE_RX_SCHED, &poll_dev->state)); + dev_put(poll_dev); + memset(poll_dev, 0, sizeof(struct net_device)); +} + +#define netif_napi_del __kc_mq_netif_napi_del + +static inline bool __kc_mq_napi_schedule_prep(struct napi_struct *napi) +{ + return netif_running(napi->dev) && + netif_rx_schedule_prep(napi_to_poll_dev(napi)); +} +#define napi_schedule_prep __kc_mq_napi_schedule_prep + +static inline void __kc_mq_napi_schedule(struct napi_struct *napi) +{ + if (napi_schedule_prep(napi)) + __netif_rx_schedule(napi_to_poll_dev(napi)); +} +#define napi_schedule __kc_mq_napi_schedule + +#define napi_enable(_napi) netif_poll_enable(napi_to_poll_dev(_napi)) +#define napi_disable(_napi) netif_poll_disable(napi_to_poll_dev(_napi)) +#ifdef CONFIG_SMP +static inline void napi_synchronize(const struct napi_struct *n) +{ + struct net_device *dev = napi_to_poll_dev(n); + + while (test_bit(__LINK_STATE_RX_SCHED, &dev->state)) { + /* No hurry. */ + msleep(1); + } +} +#else +#define napi_synchronize(n) barrier() +#endif /* CONFIG_SMP */ +#define __napi_schedule(_napi) __netif_rx_schedule(napi_to_poll_dev(_napi)) +static inline void _kc_napi_complete(struct napi_struct *napi) +{ +#ifdef NETIF_F_GRO + napi_gro_flush(napi); +#endif + netif_rx_complete(napi_to_poll_dev(napi)); +} +#define napi_complete _kc_napi_complete +#else /* NAPI */ + +/* The following definitions are only used if we don't support NAPI at all. */ + +static inline __kc_netif_napi_add(struct net_device *dev, struct napi_struct *napi, + int (*poll)(struct napi_struct *, int), int weight) +{ + dev->poll = poll; + dev->weight = weight; + napi->poll = poll; + napi->weight = weight; + napi->dev = dev; +} +#define netif_napi_del(_a) do {} while (0) +#endif /* NAPI */ + +#undef dev_get_by_name +#define dev_get_by_name(_a, _b) dev_get_by_name(_b) +#define __netif_subqueue_stopped(_a, _b) netif_subqueue_stopped(_a, _b) +#ifndef DMA_BIT_MASK +#define DMA_BIT_MASK(n) (((n) == 64) ? DMA_64BIT_MASK : ((1ULL<<(n))-1)) +#endif + +#ifdef NETIF_F_TSO6 +#define skb_is_gso_v6 _kc_skb_is_gso_v6 +static inline int _kc_skb_is_gso_v6(const struct sk_buff *skb) +{ + return skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6; +} +#endif /* NETIF_F_TSO6 */ + +#ifndef KERN_CONT +#define KERN_CONT "" +#endif +#ifndef pr_err +#define pr_err(fmt, arg...) \ + printk(KERN_ERR fmt, ##arg) +#endif + +#ifndef rounddown_pow_of_two +#define rounddown_pow_of_two(n) \ + __builtin_constant_p(n) ? ( \ + (n == 1) ? 0 : \ + (1UL << ilog2(n))) : \ + (1UL << (fls_long(n) - 1)) +#endif + +#else /* < 2.6.24 */ +#define HAVE_ETHTOOL_GET_SSET_COUNT +#define HAVE_NETDEV_NAPI_LIST +#endif /* < 2.6.24 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE > KERNEL_VERSION(2,6,24) ) +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,2,0) ) +#define INCLUDE_PM_QOS_PARAMS_H +#include +#else /* >= 3.2.0 */ +#include +#endif /* else >= 3.2.0 */ +#endif /* > 2.6.24 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25) ) +#define PM_QOS_CPU_DMA_LATENCY 1 + +#if ( LINUX_VERSION_CODE > KERNEL_VERSION(2,6,18) ) +#include +#define PM_QOS_DEFAULT_VALUE INFINITE_LATENCY +#define pm_qos_add_requirement(pm_qos_class, name, value) \ + set_acceptable_latency(name, value) +#define pm_qos_remove_requirement(pm_qos_class, name) \ + remove_acceptable_latency(name) +#define pm_qos_update_requirement(pm_qos_class, name, value) \ + modify_acceptable_latency(name, value) +#else +#define PM_QOS_DEFAULT_VALUE -1 +#define pm_qos_add_requirement(pm_qos_class, name, value) +#define pm_qos_remove_requirement(pm_qos_class, name) +#define pm_qos_update_requirement(pm_qos_class, name, value) { \ + if (value != PM_QOS_DEFAULT_VALUE) { \ + printk(KERN_WARNING "%s: unable to set PM QoS requirement\n", \ + pci_name(adapter->pdev)); \ + } \ +} + +#endif /* > 2.6.18 */ + +#define pci_enable_device_mem(pdev) pci_enable_device(pdev) + +#ifndef DEFINE_PCI_DEVICE_TABLE +#define DEFINE_PCI_DEVICE_TABLE(_table) struct pci_device_id _table[] +#endif /* DEFINE_PCI_DEVICE_TABLE */ + +#ifndef strict_strtol +#define strict_strtol(s, b, r) _kc_strict_strtol(s, b, r) +static inline int _kc_strict_strtol(const char *buf, unsigned int base, long *res) +{ + /* adapted from strict_strtoul() in 2.6.25 */ + char *tail; + long val; + size_t len; + + *res = 0; + len = strlen(buf); + if (!len) + return -EINVAL; + val = simple_strtol(buf, &tail, base); + if (tail == buf) + return -EINVAL; + if ((*tail == '\0') || + ((len == (size_t)(tail - buf) + 1) && (*tail == '\n'))) { + *res = val; + return 0; + } + + return -EINVAL; +} +#endif + +#else /* < 2.6.25 */ + +#endif /* < 2.6.25 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26) ) +#ifndef clamp_t +#define clamp_t(type, val, min, max) ({ \ + type __val = (val); \ + type __min = (min); \ + type __max = (max); \ + __val = __val < __min ? __min : __val; \ + __val > __max ? __max : __val; }) +#endif /* clamp_t */ +#undef kzalloc_node +#define kzalloc_node(_size, _flags, _node) kzalloc(_size, _flags) + +void _kc_pci_disable_link_state(struct pci_dev *dev, int state); +#define pci_disable_link_state(p, s) _kc_pci_disable_link_state(p, s) +#else /* < 2.6.26 */ +#define NETDEV_CAN_SET_GSO_MAX_SIZE +#ifdef HAVE_PCI_ASPM_H +#include +#endif +#define HAVE_NETDEV_VLAN_FEATURES +#ifndef PCI_EXP_LNKCAP_ASPMS +#define PCI_EXP_LNKCAP_ASPMS 0x00000c00 /* ASPM Support */ +#endif /* PCI_EXP_LNKCAP_ASPMS */ +#endif /* < 2.6.26 */ +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27) ) +static inline void _kc_ethtool_cmd_speed_set(struct ethtool_cmd *ep, + __u32 speed) +{ + ep->speed = (__u16)speed; + /* ep->speed_hi = (__u16)(speed >> 16); */ +} +#define ethtool_cmd_speed_set _kc_ethtool_cmd_speed_set + +static inline __u32 _kc_ethtool_cmd_speed(struct ethtool_cmd *ep) +{ + /* no speed_hi before 2.6.27, and probably no need for it yet */ + return (__u32)ep->speed; +} +#define ethtool_cmd_speed _kc_ethtool_cmd_speed + +#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,15) ) +#if ((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23)) && defined(CONFIG_PM)) +#define ANCIENT_PM 1 +#elif ((LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,23)) && \ + (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)) && \ + defined(CONFIG_PM_SLEEP)) +#define NEWER_PM 1 +#endif +#if defined(ANCIENT_PM) || defined(NEWER_PM) +#undef device_set_wakeup_enable +#define device_set_wakeup_enable(dev, val) \ + do { \ + u16 pmc = 0; \ + int pm = pci_find_capability(adapter->pdev, PCI_CAP_ID_PM); \ + if (pm) { \ + pci_read_config_word(adapter->pdev, pm + PCI_PM_PMC, \ + &pmc); \ + } \ + (dev)->power.can_wakeup = !!(pmc >> 11); \ + (dev)->power.should_wakeup = (val && (pmc >> 11)); \ + } while (0) +#endif /* 2.6.15-2.6.22 and CONFIG_PM or 2.6.23-2.6.25 and CONFIG_PM_SLEEP */ +#endif /* 2.6.15 through 2.6.27 */ +#ifndef netif_napi_del +#define netif_napi_del(_a) do {} while (0) +#ifdef NAPI +#ifdef CONFIG_NETPOLL +#undef netif_napi_del +#define netif_napi_del(_a) list_del(&(_a)->dev_list); +#endif +#endif +#endif /* netif_napi_del */ +#ifdef dma_mapping_error +#undef dma_mapping_error +#endif +#define dma_mapping_error(dev, dma_addr) pci_dma_mapping_error(dma_addr) + +#ifdef CONFIG_NETDEVICES_MULTIQUEUE +#define HAVE_TX_MQ +#endif + +#ifndef DMA_ATTR_WEAK_ORDERING +#define DMA_ATTR_WEAK_ORDERING 0 +#endif + +#ifdef HAVE_TX_MQ +void _kc_netif_tx_stop_all_queues(struct net_device *); +void _kc_netif_tx_wake_all_queues(struct net_device *); +void _kc_netif_tx_start_all_queues(struct net_device *); +#define netif_tx_stop_all_queues(a) _kc_netif_tx_stop_all_queues(a) +#define netif_tx_wake_all_queues(a) _kc_netif_tx_wake_all_queues(a) +#define netif_tx_start_all_queues(a) _kc_netif_tx_start_all_queues(a) +#undef netif_stop_subqueue +#define netif_stop_subqueue(_ndev,_qi) do { \ + if (netif_is_multiqueue((_ndev))) \ + netif_stop_subqueue((_ndev), (_qi)); \ + else \ + netif_stop_queue((_ndev)); \ + } while (0) +#undef netif_start_subqueue +#define netif_start_subqueue(_ndev,_qi) do { \ + if (netif_is_multiqueue((_ndev))) \ + netif_start_subqueue((_ndev), (_qi)); \ + else \ + netif_start_queue((_ndev)); \ + } while (0) +#else /* HAVE_TX_MQ */ +#define netif_tx_stop_all_queues(a) netif_stop_queue(a) +#define netif_tx_wake_all_queues(a) netif_wake_queue(a) +#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,12) ) +#define netif_tx_start_all_queues(a) netif_start_queue(a) +#else +#define netif_tx_start_all_queues(a) do {} while (0) +#endif +#define netif_stop_subqueue(_ndev,_qi) netif_stop_queue((_ndev)) +#define netif_start_subqueue(_ndev,_qi) netif_start_queue((_ndev)) +#endif /* HAVE_TX_MQ */ +#ifndef NETIF_F_MULTI_QUEUE +#define NETIF_F_MULTI_QUEUE 0 +#define netif_is_multiqueue(a) 0 +#define netif_wake_subqueue(a, b) +#endif /* NETIF_F_MULTI_QUEUE */ + +#ifndef __WARN_printf +void __kc_warn_slowpath(const char *file, const int line, + const char *fmt, ...) __attribute__((format(printf, 3, 4))); +#define __WARN_printf(arg...) __kc_warn_slowpath(__FILE__, __LINE__, arg) +#endif /* __WARN_printf */ + +#ifndef WARN +#define WARN(condition, format...) ({ \ + int __ret_warn_on = !!(condition); \ + if (unlikely(__ret_warn_on)) \ + __WARN_printf(format); \ + unlikely(__ret_warn_on); \ +}) +#endif /* WARN */ +#undef HAVE_IXGBE_DEBUG_FS +#undef HAVE_IGB_DEBUG_FS +#define qdisc_reset_all_tx(a) +#else /* < 2.6.27 */ +#include +#define ethtool_cmd_speed_set _kc_ethtool_cmd_speed_set +static inline void _kc_ethtool_cmd_speed_set(struct ethtool_cmd *ep, + __u32 speed) +{ + ep->speed = (__u16)(speed & 0xFFFF); + ep->speed_hi = (__u16)(speed >> 16); +} +#define HAVE_TX_MQ +#define HAVE_NETDEV_SELECT_QUEUE +#ifdef CONFIG_DEBUG_FS +#define HAVE_IXGBE_DEBUG_FS +#define HAVE_IGB_DEBUG_FS +#endif /* CONFIG_DEBUG_FS */ +#endif /* < 2.6.27 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) ) +#define pci_ioremap_bar(pdev, bar) ioremap(pci_resource_start(pdev, bar), \ + pci_resource_len(pdev, bar)) +#define pci_wake_from_d3 _kc_pci_wake_from_d3 +#define pci_prepare_to_sleep _kc_pci_prepare_to_sleep +int _kc_pci_wake_from_d3(struct pci_dev *dev, bool enable); +int _kc_pci_prepare_to_sleep(struct pci_dev *dev); +#define netdev_alloc_page(a) alloc_page(GFP_ATOMIC) +#ifndef __skb_queue_head_init +static inline void __kc_skb_queue_head_init(struct sk_buff_head *list) +{ + list->prev = list->next = (struct sk_buff *)list; + list->qlen = 0; +} +#define __skb_queue_head_init(_q) __kc_skb_queue_head_init(_q) +#endif + +#define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */ +#define PCI_EXP_DEVCTL2 40 /* Device Control 2 */ + +#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */ +#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ + +#endif /* < 2.6.28 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29) ) +#ifndef swap +#define swap(a, b) \ + do { typeof(a) __tmp = (a); (a) = (b); (b) = __tmp; } while (0) +#endif +#define pci_request_selected_regions_exclusive(pdev, bars, name) \ + pci_request_selected_regions(pdev, bars, name) +#ifndef CONFIG_NR_CPUS +#define CONFIG_NR_CPUS 1 +#endif /* CONFIG_NR_CPUS */ +#ifndef pcie_aspm_enabled +#define pcie_aspm_enabled() (1) +#endif /* pcie_aspm_enabled */ + +#define PCI_EXP_SLTSTA_PDS 0x0040 /* Presence Detect State */ + +#ifndef PCI_EXP_LNKSTA_CLS +#define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */ +#endif +#ifndef PCI_EXP_LNKSTA_NLW +#define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */ +#endif + +#ifndef pci_clear_master +void _kc_pci_clear_master(struct pci_dev *dev); +#define pci_clear_master(dev) _kc_pci_clear_master(dev) +#endif + +#ifndef PCI_EXP_LNKCTL_ASPMC +#define PCI_EXP_LNKCTL_ASPMC 0x0003 /* ASPM Control */ +#endif + +#ifndef PCI_EXP_LNKCAP_MLW +#define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */ +#endif + +#else /* < 2.6.29 */ +#ifndef HAVE_NET_DEVICE_OPS +#define HAVE_NET_DEVICE_OPS +#endif +#ifdef CONFIG_DCB +#define HAVE_PFC_MODE_ENABLE +#endif /* CONFIG_DCB */ +#endif /* < 2.6.29 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30) ) +#define NO_PTP_SUPPORT +#define skb_rx_queue_recorded(a) false +#define skb_get_rx_queue(a) 0 +#define skb_record_rx_queue(a, b) do {} while (0) +#define skb_tx_hash(n, s) ___kc_skb_tx_hash((n), (s), (n)->real_num_tx_queues) +#ifndef CONFIG_PCI_IOV +#undef pci_enable_sriov +#define pci_enable_sriov(a, b) -ENOTSUPP +#undef pci_disable_sriov +#define pci_disable_sriov(a) do {} while (0) +#endif /* CONFIG_PCI_IOV */ +#ifndef pr_cont +#define pr_cont(fmt, ...) \ + printk(KERN_CONT fmt, ##__VA_ARGS__) +#endif /* pr_cont */ +static inline void _kc_synchronize_irq(unsigned int a) +{ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,5,28) ) + synchronize_irq(); +#else /* < 2.5.28 */ + synchronize_irq(a); +#endif /* < 2.5.28 */ +} +#undef synchronize_irq +#define synchronize_irq(a) _kc_synchronize_irq(a) + +#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ + +#ifdef nr_cpus_node +#undef nr_cpus_node +#define nr_cpus_node(node) cpumask_weight(cpumask_of_node(node)) +#endif + +#if (RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(5,5)) +#define HAVE_PCI_DEV_IS_VIRTFN_BIT +#endif /* RHEL >= 5.5 */ + +#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(5,5))) +static inline bool pci_is_root_bus(struct pci_bus *pbus) +{ + return !(pbus->parent); +} +#endif + +#else /* < 2.6.30 */ +#define HAVE_ASPM_QUIRKS +#define HAVE_PCI_DEV_IS_VIRTFN_BIT +#endif /* < 2.6.30 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,31) ) +#define ETH_P_1588 0x88F7 +#define ETH_P_FIP 0x8914 +#ifndef netdev_uc_count +#define netdev_uc_count(dev) ((dev)->uc_count) +#endif +#ifndef netdev_for_each_uc_addr +#define netdev_for_each_uc_addr(uclist, dev) \ + for (uclist = dev->uc_list; uclist; uclist = uclist->next) +#endif +#ifndef PORT_OTHER +#define PORT_OTHER 0xff +#endif +#ifndef MDIO_PHY_ID_PRTAD +#define MDIO_PHY_ID_PRTAD 0x03e0 +#endif +#ifndef MDIO_PHY_ID_DEVAD +#define MDIO_PHY_ID_DEVAD 0x001f +#endif +#ifndef skb_dst +#define skb_dst(s) ((s)->dst) +#endif + +#ifndef SUPPORTED_1000baseKX_Full +#define SUPPORTED_1000baseKX_Full BIT(17) +#endif +#ifndef SUPPORTED_10000baseKX4_Full +#define SUPPORTED_10000baseKX4_Full BIT(18) +#endif +#ifndef SUPPORTED_10000baseKR_Full +#define SUPPORTED_10000baseKR_Full BIT(19) +#endif + +#ifndef ADVERTISED_1000baseKX_Full +#define ADVERTISED_1000baseKX_Full BIT(17) +#endif +#ifndef ADVERTISED_10000baseKX4_Full +#define ADVERTISED_10000baseKX4_Full BIT(18) +#endif +#ifndef ADVERTISED_10000baseKR_Full +#define ADVERTISED_10000baseKR_Full BIT(19) +#endif + +static inline unsigned long dev_trans_start(struct net_device *dev) +{ + return dev->trans_start; +} +#else /* < 2.6.31 */ +#ifndef HAVE_NETDEV_STORAGE_ADDRESS +#define HAVE_NETDEV_STORAGE_ADDRESS +#endif +#ifndef HAVE_NETDEV_HW_ADDR +#define HAVE_NETDEV_HW_ADDR +#endif +#ifndef HAVE_TRANS_START_IN_QUEUE +#define HAVE_TRANS_START_IN_QUEUE +#endif +#ifndef HAVE_INCLUDE_LINUX_MDIO_H +#define HAVE_INCLUDE_LINUX_MDIO_H +#endif +#include +#endif /* < 2.6.31 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,32) ) +#undef netdev_tx_t +#define netdev_tx_t int +#if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE) +#ifndef NETIF_F_FCOE_MTU +#define NETIF_F_FCOE_MTU BIT(26) +#endif +#endif /* CONFIG_FCOE || CONFIG_FCOE_MODULE */ + +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ) +static inline int _kc_pm_runtime_get_sync() +{ + return 1; +} +#define pm_runtime_get_sync(dev) _kc_pm_runtime_get_sync() +#else /* 2.6.0 => 2.6.32 */ +static inline int _kc_pm_runtime_get_sync(struct device __always_unused *dev) +{ + return 1; +} +#ifndef pm_runtime_get_sync +#define pm_runtime_get_sync(dev) _kc_pm_runtime_get_sync(dev) +#endif +#endif /* 2.6.0 => 2.6.32 */ +#ifndef pm_runtime_put +#define pm_runtime_put(dev) do {} while (0) +#endif +#ifndef pm_runtime_put_sync +#define pm_runtime_put_sync(dev) do {} while (0) +#endif +#ifndef pm_runtime_resume +#define pm_runtime_resume(dev) do {} while (0) +#endif +#ifndef pm_schedule_suspend +#define pm_schedule_suspend(dev, t) do {} while (0) +#endif +#ifndef pm_runtime_set_suspended +#define pm_runtime_set_suspended(dev) do {} while (0) +#endif +#ifndef pm_runtime_disable +#define pm_runtime_disable(dev) do {} while (0) +#endif +#ifndef pm_runtime_put_noidle +#define pm_runtime_put_noidle(dev) do {} while (0) +#endif +#ifndef pm_runtime_set_active +#define pm_runtime_set_active(dev) do {} while (0) +#endif +#ifndef pm_runtime_enable +#define pm_runtime_enable(dev) do {} while (0) +#endif +#ifndef pm_runtime_get_noresume +#define pm_runtime_get_noresume(dev) do {} while (0) +#endif +#else /* < 2.6.32 */ +#if (RHEL_RELEASE_CODE && \ + (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,2)) && \ + (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7,0))) +#define HAVE_RHEL6_NET_DEVICE_EXTENDED +#endif /* RHEL >= 6.2 && RHEL < 7.0 */ +#if (RHEL_RELEASE_CODE && \ + (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,6)) && \ + (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7,0))) +#define HAVE_RHEL6_NET_DEVICE_OPS_EXT +#define HAVE_NDO_SET_FEATURES +#endif /* RHEL >= 6.6 && RHEL < 7.0 */ +#if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE) +#ifndef HAVE_NETDEV_OPS_FCOE_ENABLE +#define HAVE_NETDEV_OPS_FCOE_ENABLE +#endif +#endif /* CONFIG_FCOE || CONFIG_FCOE_MODULE */ +#ifdef CONFIG_DCB +#ifndef HAVE_DCBNL_OPS_GETAPP +#define HAVE_DCBNL_OPS_GETAPP +#endif +#endif /* CONFIG_DCB */ +#include +/* IOV bad DMA target work arounds require at least this kernel rev support */ +#define HAVE_PCIE_TYPE +#endif /* < 2.6.32 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,33) ) +#ifndef pci_pcie_cap +#define pci_pcie_cap(pdev) pci_find_capability(pdev, PCI_CAP_ID_EXP) +#endif +#ifndef IPV4_FLOW +#define IPV4_FLOW 0x10 +#endif /* IPV4_FLOW */ +#ifndef IPV6_FLOW +#define IPV6_FLOW 0x11 +#endif /* IPV6_FLOW */ +/* Features back-ported to RHEL6 or SLES11 SP1 after 2.6.32 */ +#if ( (RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,0)) || \ + (SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(11,1,0)) ) +#if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE) +#ifndef HAVE_NETDEV_OPS_FCOE_GETWWN +#define HAVE_NETDEV_OPS_FCOE_GETWWN +#endif +#endif /* CONFIG_FCOE || CONFIG_FCOE_MODULE */ +#endif /* RHEL6 or SLES11 SP1 */ +#ifndef __percpu +#define __percpu +#endif /* __percpu */ + +#ifndef PORT_DA +#define PORT_DA PORT_OTHER +#endif /* PORT_DA */ +#ifndef PORT_NONE +#define PORT_NONE PORT_OTHER +#endif + +#if ((RHEL_RELEASE_CODE && \ + (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,3)) && \ + (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7,0)))) +#if !defined(CONFIG_X86_32) && !defined(CONFIG_NEED_DMA_MAP_STATE) +#undef DEFINE_DMA_UNMAP_ADDR +#define DEFINE_DMA_UNMAP_ADDR(ADDR_NAME) dma_addr_t ADDR_NAME +#undef DEFINE_DMA_UNMAP_LEN +#define DEFINE_DMA_UNMAP_LEN(LEN_NAME) __u32 LEN_NAME +#undef dma_unmap_addr +#define dma_unmap_addr(PTR, ADDR_NAME) ((PTR)->ADDR_NAME) +#undef dma_unmap_addr_set +#define dma_unmap_addr_set(PTR, ADDR_NAME, VAL) (((PTR)->ADDR_NAME) = (VAL)) +#undef dma_unmap_len +#define dma_unmap_len(PTR, LEN_NAME) ((PTR)->LEN_NAME) +#undef dma_unmap_len_set +#define dma_unmap_len_set(PTR, LEN_NAME, VAL) (((PTR)->LEN_NAME) = (VAL)) +#endif /* CONFIG_X86_64 && !CONFIG_NEED_DMA_MAP_STATE */ +#endif /* RHEL_RELEASE_CODE */ + +#if (!(RHEL_RELEASE_CODE && \ + (((RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(5,8)) && \ + (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(6,0))) || \ + ((RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,1)) && \ + (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7,0)))))) +static inline bool pci_is_pcie(struct pci_dev *dev) +{ + return !!pci_pcie_cap(dev); +} +#endif /* RHEL_RELEASE_CODE */ + +#if (!(RHEL_RELEASE_CODE && \ + (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,2)))) +#define sk_tx_queue_get(_sk) (-1) +#define sk_tx_queue_set(_sk, _tx_queue) do {} while(0) +#endif /* !(RHEL >= 6.2) */ + +#if (RHEL_RELEASE_CODE && \ + (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,4)) && \ + (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7,0))) +#define HAVE_RHEL6_ETHTOOL_OPS_EXT_STRUCT +#define HAVE_ETHTOOL_GRXFHINDIR_SIZE +#define HAVE_ETHTOOL_SET_PHYS_ID +#define HAVE_ETHTOOL_GET_TS_INFO +#if (RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(6,5)) +#define HAVE_ETHTOOL_GSRSSH +#define HAVE_RHEL6_SRIOV_CONFIGURE +#define HAVE_RXFH_NONCONST +#endif /* RHEL > 6.5 */ +#endif /* RHEL >= 6.4 && RHEL < 7.0 */ + +#else /* < 2.6.33 */ +#if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE) +#ifndef HAVE_NETDEV_OPS_FCOE_GETWWN +#define HAVE_NETDEV_OPS_FCOE_GETWWN +#endif +#endif /* CONFIG_FCOE || CONFIG_FCOE_MODULE */ +#endif /* < 2.6.33 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,34) ) +#if (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(6,0)) +#ifndef pci_num_vf +#define pci_num_vf(pdev) _kc_pci_num_vf(pdev) +int _kc_pci_num_vf(struct pci_dev *dev); +#endif +#endif /* RHEL_RELEASE_CODE */ + +#ifndef dev_is_pci +#define dev_is_pci(d) ((d)->bus == &pci_bus_type) +#endif + +#ifndef ETH_FLAG_NTUPLE +#define ETH_FLAG_NTUPLE NETIF_F_NTUPLE +#endif + +#ifndef netdev_mc_count +#define netdev_mc_count(dev) ((dev)->mc_count) +#endif +#ifndef netdev_mc_empty +#define netdev_mc_empty(dev) (netdev_mc_count(dev) == 0) +#endif +#ifndef netdev_for_each_mc_addr +#define netdev_for_each_mc_addr(mclist, dev) \ + for (mclist = dev->mc_list; mclist; mclist = mclist->next) +#endif +#ifndef netdev_uc_count +#define netdev_uc_count(dev) ((dev)->uc.count) +#endif +#ifndef netdev_uc_empty +#define netdev_uc_empty(dev) (netdev_uc_count(dev) == 0) +#endif +#ifndef netdev_for_each_uc_addr +#define netdev_for_each_uc_addr(ha, dev) \ + list_for_each_entry(ha, &dev->uc.list, list) +#endif +#ifndef dma_set_coherent_mask +#define dma_set_coherent_mask(dev,mask) \ + pci_set_consistent_dma_mask(to_pci_dev(dev),(mask)) +#endif +#ifndef pci_dev_run_wake +#define pci_dev_run_wake(pdev) (0) +#endif + +/* netdev logging taken from include/linux/netdevice.h */ +#ifndef netdev_name +static inline const char *_kc_netdev_name(const struct net_device *dev) +{ + if (dev->reg_state != NETREG_REGISTERED) + return "(unregistered net_device)"; + return dev->name; +} +#define netdev_name(netdev) _kc_netdev_name(netdev) +#endif /* netdev_name */ + +#undef netdev_printk +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ) +#define netdev_printk(level, netdev, format, args...) \ +do { \ + struct pci_dev *pdev = _kc_netdev_to_pdev(netdev); \ + printk(level "%s: " format, pci_name(pdev), ##args); \ +} while(0) +#elif ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21) ) +#define netdev_printk(level, netdev, format, args...) \ +do { \ + struct pci_dev *pdev = _kc_netdev_to_pdev(netdev); \ + struct device *dev = pci_dev_to_dev(pdev); \ + dev_printk(level, dev, "%s: " format, \ + netdev_name(netdev), ##args); \ +} while(0) +#else /* 2.6.21 => 2.6.34 */ +#define netdev_printk(level, netdev, format, args...) \ + dev_printk(level, (netdev)->dev.parent, \ + "%s: " format, \ + netdev_name(netdev), ##args) +#endif /* <2.6.0 <2.6.21 <2.6.34 */ +#undef netdev_emerg +#define netdev_emerg(dev, format, args...) \ + netdev_printk(KERN_EMERG, dev, format, ##args) +#undef netdev_alert +#define netdev_alert(dev, format, args...) \ + netdev_printk(KERN_ALERT, dev, format, ##args) +#undef netdev_crit +#define netdev_crit(dev, format, args...) \ + netdev_printk(KERN_CRIT, dev, format, ##args) +#undef netdev_err +#define netdev_err(dev, format, args...) \ + netdev_printk(KERN_ERR, dev, format, ##args) +#undef netdev_warn +#define netdev_warn(dev, format, args...) \ + netdev_printk(KERN_WARNING, dev, format, ##args) +#undef netdev_notice +#define netdev_notice(dev, format, args...) \ + netdev_printk(KERN_NOTICE, dev, format, ##args) +#undef netdev_info +#define netdev_info(dev, format, args...) \ + netdev_printk(KERN_INFO, dev, format, ##args) +#undef netdev_dbg +#if defined(DEBUG) +#define netdev_dbg(__dev, format, args...) \ + netdev_printk(KERN_DEBUG, __dev, format, ##args) +#elif defined(CONFIG_DYNAMIC_DEBUG) +#define netdev_dbg(__dev, format, args...) \ +do { \ + dynamic_dev_dbg((__dev)->dev.parent, "%s: " format, \ + netdev_name(__dev), ##args); \ +} while (0) +#else /* DEBUG */ +#define netdev_dbg(__dev, format, args...) \ +({ \ + if (0) \ + netdev_printk(KERN_DEBUG, __dev, format, ##args); \ + 0; \ +}) +#endif /* DEBUG */ + +#undef netif_printk +#define netif_printk(priv, type, level, dev, fmt, args...) \ +do { \ + if (netif_msg_##type(priv)) \ + netdev_printk(level, (dev), fmt, ##args); \ +} while (0) + +#undef netif_emerg +#define netif_emerg(priv, type, dev, fmt, args...) \ + netif_level(emerg, priv, type, dev, fmt, ##args) +#undef netif_alert +#define netif_alert(priv, type, dev, fmt, args...) \ + netif_level(alert, priv, type, dev, fmt, ##args) +#undef netif_crit +#define netif_crit(priv, type, dev, fmt, args...) \ + netif_level(crit, priv, type, dev, fmt, ##args) +#undef netif_err +#define netif_err(priv, type, dev, fmt, args...) \ + netif_level(err, priv, type, dev, fmt, ##args) +#undef netif_warn +#define netif_warn(priv, type, dev, fmt, args...) \ + netif_level(warn, priv, type, dev, fmt, ##args) +#undef netif_notice +#define netif_notice(priv, type, dev, fmt, args...) \ + netif_level(notice, priv, type, dev, fmt, ##args) +#undef netif_info +#define netif_info(priv, type, dev, fmt, args...) \ + netif_level(info, priv, type, dev, fmt, ##args) +#undef netif_dbg +#define netif_dbg(priv, type, dev, fmt, args...) \ + netif_level(dbg, priv, type, dev, fmt, ##args) + +#ifdef SET_SYSTEM_SLEEP_PM_OPS +#define HAVE_SYSTEM_SLEEP_PM_OPS +#endif + +#ifndef for_each_set_bit +#define for_each_set_bit(bit, addr, size) \ + for ((bit) = find_first_bit((addr), (size)); \ + (bit) < (size); \ + (bit) = find_next_bit((addr), (size), (bit) + 1)) +#endif /* for_each_set_bit */ + +#ifndef DEFINE_DMA_UNMAP_ADDR +#define DEFINE_DMA_UNMAP_ADDR DECLARE_PCI_UNMAP_ADDR +#define DEFINE_DMA_UNMAP_LEN DECLARE_PCI_UNMAP_LEN +#define dma_unmap_addr pci_unmap_addr +#define dma_unmap_addr_set pci_unmap_addr_set +#define dma_unmap_len pci_unmap_len +#define dma_unmap_len_set pci_unmap_len_set +#endif /* DEFINE_DMA_UNMAP_ADDR */ + +#if (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(6,3)) +#ifdef IGB_HWMON +#ifdef CONFIG_DEBUG_LOCK_ALLOC +#define sysfs_attr_init(attr) \ + do { \ + static struct lock_class_key __key; \ + (attr)->key = &__key; \ + } while (0) +#else +#define sysfs_attr_init(attr) do {} while (0) +#endif /* CONFIG_DEBUG_LOCK_ALLOC */ +#endif /* IGB_HWMON */ +#endif /* RHEL_RELEASE_CODE */ + +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ) +static inline bool _kc_pm_runtime_suspended() +{ + return false; +} +#define pm_runtime_suspended(dev) _kc_pm_runtime_suspended() +#else /* 2.6.0 => 2.6.34 */ +static inline bool _kc_pm_runtime_suspended(struct device __always_unused *dev) +{ + return false; +} +#ifndef pm_runtime_suspended +#define pm_runtime_suspended(dev) _kc_pm_runtime_suspended(dev) +#endif +#endif /* 2.6.0 => 2.6.34 */ + +#ifndef pci_bus_speed +/* override pci_bus_speed introduced in 2.6.19 with an expanded enum type */ +enum _kc_pci_bus_speed { + _KC_PCIE_SPEED_2_5GT = 0x14, + _KC_PCIE_SPEED_5_0GT = 0x15, + _KC_PCIE_SPEED_8_0GT = 0x16, + _KC_PCI_SPEED_UNKNOWN = 0xff, +}; +#define pci_bus_speed _kc_pci_bus_speed +#define PCIE_SPEED_2_5GT _KC_PCIE_SPEED_2_5GT +#define PCIE_SPEED_5_0GT _KC_PCIE_SPEED_5_0GT +#define PCIE_SPEED_8_0GT _KC_PCIE_SPEED_8_0GT +#define PCI_SPEED_UNKNOWN _KC_PCI_SPEED_UNKNOWN +#endif /* pci_bus_speed */ + +#else /* < 2.6.34 */ +#define HAVE_SYSTEM_SLEEP_PM_OPS +#ifndef HAVE_SET_RX_MODE +#define HAVE_SET_RX_MODE +#endif + +#endif /* < 2.6.34 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35) ) +ssize_t _kc_simple_write_to_buffer(void *to, size_t available, loff_t *ppos, + const void __user *from, size_t count); +#define simple_write_to_buffer _kc_simple_write_to_buffer + +#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,4))) +static inline struct pci_dev *pci_physfn(struct pci_dev *dev) +{ +#ifdef HAVE_PCI_DEV_IS_VIRTFN_BIT +#ifdef CONFIG_PCI_IOV + if (dev->is_virtfn) + dev = dev->physfn; +#endif /* CONFIG_PCI_IOV */ +#endif /* HAVE_PCI_DEV_IS_VIRTFN_BIT */ + return dev; +} +#endif /* ! RHEL >= 6.4 */ + +#ifndef PCI_EXP_LNKSTA_NLW_SHIFT +#define PCI_EXP_LNKSTA_NLW_SHIFT 4 +#endif + +#ifndef numa_node_id +#define numa_node_id() 0 +#endif +#ifndef numa_mem_id +#define numa_mem_id numa_node_id +#endif +#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,0))) +#ifdef HAVE_TX_MQ +#include +#ifndef CONFIG_NETDEVICES_MULTIQUEUE +int _kc_netif_set_real_num_tx_queues(struct net_device *, unsigned int); +#else /* CONFIG_NETDEVICES_MULTI_QUEUE */ +static inline int _kc_netif_set_real_num_tx_queues(struct net_device *dev, + unsigned int txq) +{ + dev->egress_subqueue_count = txq; + return 0; +} +#endif /* CONFIG_NETDEVICES_MULTI_QUEUE */ +#else /* HAVE_TX_MQ */ +static inline int _kc_netif_set_real_num_tx_queues(struct net_device __always_unused *dev, + unsigned int __always_unused txq) +{ + return 0; +} +#endif /* HAVE_TX_MQ */ +#define netif_set_real_num_tx_queues(dev, txq) \ + _kc_netif_set_real_num_tx_queues(dev, txq) +#endif /* !(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,0)) */ +#ifndef ETH_FLAG_RXHASH +#define ETH_FLAG_RXHASH (1<<28) +#endif /* ETH_FLAG_RXHASH */ +#if (RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,0)) +#define HAVE_IRQ_AFFINITY_HINT +#endif +struct device_node; +#else /* < 2.6.35 */ +#define HAVE_STRUCT_DEVICE_OF_NODE +#define HAVE_PM_QOS_REQUEST_LIST +#define HAVE_IRQ_AFFINITY_HINT +#include +#endif /* < 2.6.35 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36) ) +int _kc_ethtool_op_set_flags(struct net_device *, u32, u32); +#define ethtool_op_set_flags _kc_ethtool_op_set_flags +u32 _kc_ethtool_op_get_flags(struct net_device *); +#define ethtool_op_get_flags _kc_ethtool_op_get_flags + +enum { + WQ_UNBOUND = 0, + WQ_RESCUER = 0, +}; + +#ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS +#ifdef NET_IP_ALIGN +#undef NET_IP_ALIGN +#endif +#define NET_IP_ALIGN 0 +#endif /* CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS */ + +#ifdef NET_SKB_PAD +#undef NET_SKB_PAD +#endif + +#if (L1_CACHE_BYTES > 32) +#define NET_SKB_PAD L1_CACHE_BYTES +#else +#define NET_SKB_PAD 32 +#endif + +static inline struct sk_buff *_kc_netdev_alloc_skb_ip_align(struct net_device *dev, + unsigned int length) +{ + struct sk_buff *skb; + + skb = alloc_skb(length + NET_SKB_PAD + NET_IP_ALIGN, GFP_ATOMIC); + if (skb) { +#if (NET_IP_ALIGN + NET_SKB_PAD) + skb_reserve(skb, NET_IP_ALIGN + NET_SKB_PAD); +#endif + skb->dev = dev; + } + return skb; +} + +#ifdef netdev_alloc_skb_ip_align +#undef netdev_alloc_skb_ip_align +#endif +#define netdev_alloc_skb_ip_align(n, l) _kc_netdev_alloc_skb_ip_align(n, l) + +#undef netif_level +#define netif_level(level, priv, type, dev, fmt, args...) \ +do { \ + if (netif_msg_##type(priv)) \ + netdev_##level(dev, fmt, ##args); \ +} while (0) + +#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,3))) +#undef usleep_range +#define usleep_range(min, max) msleep(DIV_ROUND_UP(min, 1000)) +#endif + +#define u64_stats_update_begin(a) do { } while(0) +#define u64_stats_update_end(a) do { } while(0) +#define u64_stats_fetch_begin(a) do { } while(0) +#define u64_stats_fetch_retry_bh(a,b) (0) +#define u64_stats_fetch_begin_bh(a) (0) + +#if (RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,1)) +#define HAVE_8021P_SUPPORT +#endif + +/* RHEL6.4 and SLES11sp2 backported skb_tx_timestamp */ +#if (!(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,4)) && \ + !(SLE_VERSION_CODE >= SLE_VERSION(11,2,0))) +static inline void skb_tx_timestamp(struct sk_buff __always_unused *skb) +{ + return; +} +#endif + +#else /* < 2.6.36 */ + +#define HAVE_PM_QOS_REQUEST_ACTIVE +#define HAVE_8021P_SUPPORT +#define HAVE_NDO_GET_STATS64 +#endif /* < 2.6.36 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,37) ) +#define HAVE_NON_CONST_PCI_DRIVER_NAME +#ifndef netif_set_real_num_tx_queues +static inline int _kc_netif_set_real_num_tx_queues(struct net_device *dev, + unsigned int txq) +{ + netif_set_real_num_tx_queues(dev, txq); + return 0; +} +#define netif_set_real_num_tx_queues(dev, txq) \ + _kc_netif_set_real_num_tx_queues(dev, txq) +#endif +#ifndef netif_set_real_num_rx_queues +static inline int __kc_netif_set_real_num_rx_queues(struct net_device __always_unused *dev, + unsigned int __always_unused rxq) +{ + return 0; +} +#define netif_set_real_num_rx_queues(dev, rxq) \ + __kc_netif_set_real_num_rx_queues((dev), (rxq)) +#endif +#ifndef ETHTOOL_RXNTUPLE_ACTION_CLEAR +#define ETHTOOL_RXNTUPLE_ACTION_CLEAR (-2) +#endif +#ifndef VLAN_N_VID +#define VLAN_N_VID VLAN_GROUP_ARRAY_LEN +#endif /* VLAN_N_VID */ +#ifndef ETH_FLAG_TXVLAN +#define ETH_FLAG_TXVLAN BIT(7) +#endif /* ETH_FLAG_TXVLAN */ +#ifndef ETH_FLAG_RXVLAN +#define ETH_FLAG_RXVLAN BIT(8) +#endif /* ETH_FLAG_RXVLAN */ + +#define WQ_MEM_RECLAIM WQ_RESCUER + +static inline void _kc_skb_checksum_none_assert(struct sk_buff *skb) +{ + WARN_ON(skb->ip_summed != CHECKSUM_NONE); +} +#define skb_checksum_none_assert(skb) _kc_skb_checksum_none_assert(skb) + +static inline void *_kc_vzalloc_node(unsigned long size, int node) +{ + void *addr = vmalloc_node(size, node); + if (addr) + memset(addr, 0, size); + return addr; +} +#define vzalloc_node(_size, _node) _kc_vzalloc_node(_size, _node) + +static inline void *_kc_vzalloc(unsigned long size) +{ + void *addr = vmalloc(size); + if (addr) + memset(addr, 0, size); + return addr; +} +#define vzalloc(_size) _kc_vzalloc(_size) + +#if (!(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(5,7)) || \ + (RHEL_RELEASE_CODE == RHEL_RELEASE_VERSION(6,0))) +static inline __be16 vlan_get_protocol(const struct sk_buff *skb) +{ + if (vlan_tx_tag_present(skb) || + skb->protocol != cpu_to_be16(ETH_P_8021Q)) + return skb->protocol; + + if (skb_headlen(skb) < sizeof(struct vlan_ethhdr)) + return 0; + + return ((struct vlan_ethhdr*)skb->data)->h_vlan_encapsulated_proto; +} +#endif /* !RHEL5.7+ || RHEL6.0 */ + +#ifdef HAVE_HW_TIME_STAMP +#define SKBTX_HW_TSTAMP BIT(0) +#define SKBTX_IN_PROGRESS BIT(2) +#define SKB_SHARED_TX_IS_UNION +#endif + +#ifndef device_wakeup_enable +#define device_wakeup_enable(dev) device_set_wakeup_enable(dev, true) +#endif + +#if ( LINUX_VERSION_CODE > KERNEL_VERSION(2,4,18) ) +#ifndef HAVE_VLAN_RX_REGISTER +#define HAVE_VLAN_RX_REGISTER +#endif +#endif /* > 2.4.18 */ +#endif /* < 2.6.37 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) ) +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22) ) +#define skb_checksum_start_offset(skb) skb_transport_offset(skb) +#else /* 2.6.22 -> 2.6.37 */ +static inline int _kc_skb_checksum_start_offset(const struct sk_buff *skb) +{ + return skb->csum_start - skb_headroom(skb); +} +#define skb_checksum_start_offset(skb) _kc_skb_checksum_start_offset(skb) +#endif /* 2.6.22 -> 2.6.37 */ +#if IS_ENABLED(CONFIG_DCB) +#ifndef IEEE_8021QAZ_MAX_TCS +#define IEEE_8021QAZ_MAX_TCS 8 +#endif +#ifndef DCB_CAP_DCBX_HOST +#define DCB_CAP_DCBX_HOST 0x01 +#endif +#ifndef DCB_CAP_DCBX_LLD_MANAGED +#define DCB_CAP_DCBX_LLD_MANAGED 0x02 +#endif +#ifndef DCB_CAP_DCBX_VER_CEE +#define DCB_CAP_DCBX_VER_CEE 0x04 +#endif +#ifndef DCB_CAP_DCBX_VER_IEEE +#define DCB_CAP_DCBX_VER_IEEE 0x08 +#endif +#ifndef DCB_CAP_DCBX_STATIC +#define DCB_CAP_DCBX_STATIC 0x10 +#endif +#endif /* CONFIG_DCB */ +#if (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,2)) +#define CONFIG_XPS +#endif /* RHEL_RELEASE_VERSION(6,2) */ +#endif /* < 2.6.38 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,39) ) +#ifndef TC_BITMASK +#define TC_BITMASK 15 +#endif +#ifndef NETIF_F_RXCSUM +#define NETIF_F_RXCSUM BIT(29) +#endif +#ifndef skb_queue_reverse_walk_safe +#define skb_queue_reverse_walk_safe(queue, skb, tmp) \ + for (skb = (queue)->prev, tmp = skb->prev; \ + skb != (struct sk_buff *)(queue); \ + skb = tmp, tmp = skb->prev) +#endif +#if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE) +#ifndef FCOE_MTU +#define FCOE_MTU 2158 +#endif +#endif +#if IS_ENABLED(CONFIG_DCB) +#ifndef IEEE_8021QAZ_APP_SEL_ETHERTYPE +#define IEEE_8021QAZ_APP_SEL_ETHERTYPE 1 +#endif +#endif +#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,4))) +#define kstrtoul(a, b, c) ((*(c)) = simple_strtoul((a), NULL, (b)), 0) +#define kstrtouint(a, b, c) ((*(c)) = simple_strtoul((a), NULL, (b)), 0) +#define kstrtou32(a, b, c) ((*(c)) = simple_strtoul((a), NULL, (b)), 0) +#endif /* !(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,4)) */ +#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(6,0))) +u16 ___kc_skb_tx_hash(struct net_device *, const struct sk_buff *, u16); +#define __skb_tx_hash(n, s, q) ___kc_skb_tx_hash((n), (s), (q)) +u8 _kc_netdev_get_num_tc(struct net_device *dev); +#define netdev_get_num_tc(dev) _kc_netdev_get_num_tc(dev) +int _kc_netdev_set_num_tc(struct net_device *dev, u8 num_tc); +#define netdev_set_num_tc(dev, tc) _kc_netdev_set_num_tc((dev), (tc)) +#define netdev_reset_tc(dev) _kc_netdev_set_num_tc((dev), 0) +#define netdev_set_tc_queue(dev, tc, cnt, off) do {} while (0) +u8 _kc_netdev_get_prio_tc_map(struct net_device *dev, u8 up); +#define netdev_get_prio_tc_map(dev, up) _kc_netdev_get_prio_tc_map(dev, up) +#define netdev_set_prio_tc_map(dev, up, tc) do {} while (0) +#else /* RHEL6.1 or greater */ +#ifndef HAVE_MQPRIO +#define HAVE_MQPRIO +#endif /* HAVE_MQPRIO */ +#if IS_ENABLED(CONFIG_DCB) +#ifndef HAVE_DCBNL_IEEE +#define HAVE_DCBNL_IEEE +#ifndef IEEE_8021QAZ_TSA_STRICT +#define IEEE_8021QAZ_TSA_STRICT 0 +#endif +#ifndef IEEE_8021QAZ_TSA_ETS +#define IEEE_8021QAZ_TSA_ETS 2 +#endif +#ifndef IEEE_8021QAZ_APP_SEL_ETHERTYPE +#define IEEE_8021QAZ_APP_SEL_ETHERTYPE 1 +#endif +#endif +#endif /* CONFIG_DCB */ +#endif /* !(RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(6,0)) */ + +#ifndef udp_csum +#define udp_csum __kc_udp_csum +static inline __wsum __kc_udp_csum(struct sk_buff *skb) +{ + __wsum csum = csum_partial(skb_transport_header(skb), + sizeof(struct udphdr), skb->csum); + + for (skb = skb_shinfo(skb)->frag_list; skb; skb = skb->next) { + csum = csum_add(csum, skb->csum); + } + return csum; +} +#endif /* udp_csum */ +#else /* < 2.6.39 */ +#if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE) +#ifndef HAVE_NETDEV_OPS_FCOE_DDP_TARGET +#define HAVE_NETDEV_OPS_FCOE_DDP_TARGET +#endif +#endif /* CONFIG_FCOE || CONFIG_FCOE_MODULE */ +#ifndef HAVE_MQPRIO +#define HAVE_MQPRIO +#endif +#ifndef HAVE_SETUP_TC +#define HAVE_SETUP_TC +#endif +#ifdef CONFIG_DCB +#ifndef HAVE_DCBNL_IEEE +#define HAVE_DCBNL_IEEE +#endif +#endif /* CONFIG_DCB */ +#ifndef HAVE_NDO_SET_FEATURES +#define HAVE_NDO_SET_FEATURES +#endif +#define HAVE_IRQ_AFFINITY_NOTIFY +#endif /* < 2.6.39 */ + +/*****************************************************************************/ +/* use < 2.6.40 because of a Fedora 15 kernel update where they + * updated the kernel version to 2.6.40.x and they back-ported 3.0 features + * like set_phys_id for ethtool. + */ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,40) ) +#ifdef ETHTOOL_GRXRINGS +#ifndef FLOW_EXT +#define FLOW_EXT 0x80000000 +union _kc_ethtool_flow_union { + struct ethtool_tcpip4_spec tcp_ip4_spec; + struct ethtool_usrip4_spec usr_ip4_spec; + __u8 hdata[60]; +}; +struct _kc_ethtool_flow_ext { + __be16 vlan_etype; + __be16 vlan_tci; + __be32 data[2]; +}; +struct _kc_ethtool_rx_flow_spec { + __u32 flow_type; + union _kc_ethtool_flow_union h_u; + struct _kc_ethtool_flow_ext h_ext; + union _kc_ethtool_flow_union m_u; + struct _kc_ethtool_flow_ext m_ext; + __u64 ring_cookie; + __u32 location; +}; +#define ethtool_rx_flow_spec _kc_ethtool_rx_flow_spec +#endif /* FLOW_EXT */ +#endif + +#define pci_disable_link_state_locked pci_disable_link_state + +#ifndef PCI_LTR_VALUE_MASK +#define PCI_LTR_VALUE_MASK 0x000003ff +#endif +#ifndef PCI_LTR_SCALE_MASK +#define PCI_LTR_SCALE_MASK 0x00001c00 +#endif +#ifndef PCI_LTR_SCALE_SHIFT +#define PCI_LTR_SCALE_SHIFT 10 +#endif + +#else /* < 2.6.40 */ +#define HAVE_ETHTOOL_SET_PHYS_ID +#endif /* < 2.6.40 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,0,0) ) +#define USE_LEGACY_PM_SUPPORT +#ifndef kfree_rcu +#define kfree_rcu(_ptr, _rcu_head) do { \ + void __kc_kfree_rcu(struct rcu_head *rcu_head) \ + { \ + void *ptr = container_of(rcu_head, \ + typeof(*_ptr), \ + _rcu_head); \ + kfree(ptr); \ + } \ + call_rcu(&(_ptr)->_rcu_head, __kc_kfree_rcu); \ +} while (0) +#define HAVE_KFREE_RCU_BARRIER +#endif /* kfree_rcu */ +#ifndef kstrtol_from_user +#define kstrtol_from_user(s, c, b, r) _kc_kstrtol_from_user(s, c, b, r) +static inline int _kc_kstrtol_from_user(const char __user *s, size_t count, + unsigned int base, long *res) +{ + /* sign, base 2 representation, newline, terminator */ + char buf[1 + sizeof(long) * 8 + 1 + 1]; + + count = min(count, sizeof(buf) - 1); + if (copy_from_user(buf, s, count)) + return -EFAULT; + buf[count] = '\0'; + return strict_strtol(buf, base, res); +} +#endif + +#if (RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(7,0) || \ + RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(5,7))) +/* 20000base_blah_full Supported and Advertised Registers */ +#define SUPPORTED_20000baseMLD2_Full BIT(21) +#define SUPPORTED_20000baseKR2_Full BIT(22) +#define ADVERTISED_20000baseMLD2_Full BIT(21) +#define ADVERTISED_20000baseKR2_Full BIT(22) +#endif /* RHEL_RELEASE_CODE */ +#endif /* < 3.0.0 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,1,0) ) +#ifndef __netdev_alloc_skb_ip_align +#define __netdev_alloc_skb_ip_align(d,l,_g) netdev_alloc_skb_ip_align(d,l) +#endif /* __netdev_alloc_skb_ip_align */ +#define dcb_ieee_setapp(dev, app) dcb_setapp(dev, app) +#define dcb_ieee_delapp(dev, app) 0 +#define dcb_ieee_getapp_mask(dev, app) (1 << app->priority) + +/* 1000BASE-T Control register */ +#define CTL1000_AS_MASTER 0x0800 +#define CTL1000_ENABLE_MASTER 0x1000 + +/* kernels less than 3.0.0 don't have this */ +#ifndef ETH_P_8021AD +#define ETH_P_8021AD 0x88A8 +#endif + +/* Stub definition for !CONFIG_OF is introduced later */ +#ifdef CONFIG_OF +static inline struct device_node * +pci_device_to_OF_node(struct pci_dev __maybe_unused *pdev) +{ +#ifdef HAVE_STRUCT_DEVICE_OF_NODE + return pdev ? pdev->dev.of_node : NULL; +#else + return NULL; +#endif /* !HAVE_STRUCT_DEVICE_OF_NODE */ +} +#endif /* CONFIG_OF */ +#else /* < 3.1.0 */ +#ifndef HAVE_DCBNL_IEEE_DELAPP +#define HAVE_DCBNL_IEEE_DELAPP +#endif +#endif /* < 3.1.0 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,2,0) ) +#ifndef dma_zalloc_coherent +#define dma_zalloc_coherent(d, s, h, f) _kc_dma_zalloc_coherent(d, s, h, f) +static inline void *_kc_dma_zalloc_coherent(struct device *dev, size_t size, + dma_addr_t *dma_handle, gfp_t flag) +{ + void *ret = dma_alloc_coherent(dev, size, dma_handle, flag); + if (ret) + memset(ret, 0, size); + return ret; +} +#endif +#ifdef ETHTOOL_GRXRINGS +#define HAVE_ETHTOOL_GET_RXNFC_VOID_RULE_LOCS +#endif /* ETHTOOL_GRXRINGS */ + +#ifndef skb_frag_size +#define skb_frag_size(frag) _kc_skb_frag_size(frag) +static inline unsigned int _kc_skb_frag_size(const skb_frag_t *frag) +{ + return frag->size; +} +#endif /* skb_frag_size */ + +#ifndef skb_frag_size_sub +#define skb_frag_size_sub(frag, delta) _kc_skb_frag_size_sub(frag, delta) +static inline void _kc_skb_frag_size_sub(skb_frag_t *frag, int delta) +{ + frag->size -= delta; +} +#endif /* skb_frag_size_sub */ + +#ifndef skb_frag_page +#define skb_frag_page(frag) _kc_skb_frag_page(frag) +static inline struct page *_kc_skb_frag_page(const skb_frag_t *frag) +{ + return frag->page; +} +#endif /* skb_frag_page */ + +#ifndef skb_frag_address +#define skb_frag_address(frag) _kc_skb_frag_address(frag) +static inline void *_kc_skb_frag_address(const skb_frag_t *frag) +{ + return page_address(skb_frag_page(frag)) + frag->page_offset; +} +#endif /* skb_frag_address */ + +#ifndef skb_frag_dma_map +#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) ) +#include +#endif +#define skb_frag_dma_map(dev,frag,offset,size,dir) \ + _kc_skb_frag_dma_map(dev,frag,offset,size,dir) +static inline dma_addr_t _kc_skb_frag_dma_map(struct device *dev, + const skb_frag_t *frag, + size_t offset, size_t size, + enum dma_data_direction dir) +{ + return dma_map_page(dev, skb_frag_page(frag), + frag->page_offset + offset, size, dir); +} +#endif /* skb_frag_dma_map */ + +#ifndef __skb_frag_unref +#define __skb_frag_unref(frag) __kc_skb_frag_unref(frag) +static inline void __kc_skb_frag_unref(skb_frag_t *frag) +{ + put_page(skb_frag_page(frag)); +} +#endif /* __skb_frag_unref */ + +#ifndef SPEED_UNKNOWN +#define SPEED_UNKNOWN -1 +#endif +#ifndef DUPLEX_UNKNOWN +#define DUPLEX_UNKNOWN 0xff +#endif +#if ((RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,3)) ||\ + (SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(11,3,0))) +#ifndef HAVE_PCI_DEV_FLAGS_ASSIGNED +#define HAVE_PCI_DEV_FLAGS_ASSIGNED +#endif +#endif +#else /* < 3.2.0 */ +#ifndef HAVE_PCI_DEV_FLAGS_ASSIGNED +#define HAVE_PCI_DEV_FLAGS_ASSIGNED +#define HAVE_VF_SPOOFCHK_CONFIGURE +#endif +#ifndef HAVE_SKB_L4_RXHASH +#define HAVE_SKB_L4_RXHASH +#endif +#define HAVE_IOMMU_PRESENT +#define HAVE_PM_QOS_REQUEST_LIST_NEW +#endif /* < 3.2.0 */ + +#if (RHEL_RELEASE_CODE && RHEL_RELEASE_CODE == RHEL_RELEASE_VERSION(6,2)) +#undef ixgbe_get_netdev_tc_txq +#define ixgbe_get_netdev_tc_txq(dev, tc) (&netdev_extended(dev)->qos_data.tc_to_txq[tc]) +#endif +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,3,0) ) +/* NOTE: the order of parameters to _kc_alloc_workqueue() is different than + * alloc_workqueue() to avoid compiler warning from -Wvarargs + */ +static inline struct workqueue_struct * __attribute__ ((format(printf, 3, 4))) +_kc_alloc_workqueue(__maybe_unused int flags, __maybe_unused int max_active, + const char *fmt, ...) +{ + struct workqueue_struct *wq; + va_list args, temp; + unsigned int len; + char *p; + + va_start(args, fmt); + va_copy(temp, args); + len = vsnprintf(NULL, 0, fmt, temp); + va_end(temp); + + p = kmalloc(len + 1, GFP_KERNEL); + if (!p) { + va_end(args); + return NULL; + } + + vsnprintf(p, len + 1, fmt, args); + va_end(args); +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36) ) + wq = create_workqueue(p); +#else + wq = alloc_workqueue(p, flags, max_active); +#endif + kfree(p); + + return wq; +} +#ifdef alloc_workqueue +#undef alloc_workqueue +#endif +#define alloc_workqueue(fmt, flags, max_active, args...) \ + _kc_alloc_workqueue(flags, max_active, fmt, ##args) + +#if !(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,5)) +typedef u32 netdev_features_t; +#endif +#undef PCI_EXP_TYPE_RC_EC +#define PCI_EXP_TYPE_RC_EC 0xa /* Root Complex Event Collector */ +#ifndef CONFIG_BQL +#define netdev_tx_completed_queue(_q, _p, _b) do {} while (0) +#define netdev_completed_queue(_n, _p, _b) do {} while (0) +#define netdev_tx_sent_queue(_q, _b) do {} while (0) +#define netdev_sent_queue(_n, _b) do {} while (0) +#define netdev_tx_reset_queue(_q) do {} while (0) +#define netdev_reset_queue(_n) do {} while (0) +#endif +#if (SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(11,3,0)) +#define HAVE_ETHTOOL_GRXFHINDIR_SIZE +#endif /* SLE_VERSION(11,3,0) */ +#define netif_xmit_stopped(_q) netif_tx_queue_stopped(_q) +#if !(SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(11,4,0)) +static inline int __kc_ipv6_skip_exthdr(const struct sk_buff *skb, int start, + u8 *nexthdrp, + __be16 __always_unused *frag_offp) +{ + return ipv6_skip_exthdr(skb, start, nexthdrp); +} +#undef ipv6_skip_exthdr +#define ipv6_skip_exthdr(a,b,c,d) __kc_ipv6_skip_exthdr((a), (b), (c), (d)) +#endif /* !SLES11sp4 or greater */ + +#if (!(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,4)) && \ + !(SLE_VERSION_CODE >= SLE_VERSION(11,3,0))) +static inline u32 ethtool_rxfh_indir_default(u32 index, u32 n_rx_rings) +{ + return index % n_rx_rings; +} +#endif + +#else /* ! < 3.3.0 */ +#define HAVE_ETHTOOL_GRXFHINDIR_SIZE +#define HAVE_INT_NDO_VLAN_RX_ADD_VID +#ifdef ETHTOOL_SRXNTUPLE +#undef ETHTOOL_SRXNTUPLE +#endif +#endif /* < 3.3.0 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,4,0) ) +#ifndef NETIF_F_RXFCS +#define NETIF_F_RXFCS 0 +#endif /* NETIF_F_RXFCS */ +#ifndef NETIF_F_RXALL +#define NETIF_F_RXALL 0 +#endif /* NETIF_F_RXALL */ + +#if !(SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(11,3,0)) +#define NUMTCS_RETURNS_U8 + +int _kc_simple_open(struct inode *inode, struct file *file); +#define simple_open _kc_simple_open +#endif /* !(SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(11,3,0)) */ + +#ifndef skb_add_rx_frag +#define skb_add_rx_frag _kc_skb_add_rx_frag +void _kc_skb_add_rx_frag(struct sk_buff * skb, int i, struct page *page, + int off, int size, unsigned int truesize); +#endif +#ifdef NET_ADDR_RANDOM +#define eth_hw_addr_random(N) do { \ + eth_random_addr(N->dev_addr); \ + N->addr_assign_type |= NET_ADDR_RANDOM; \ + } while (0) +#else /* NET_ADDR_RANDOM */ +#define eth_hw_addr_random(N) eth_random_addr(N->dev_addr) +#endif /* NET_ADDR_RANDOM */ + +#ifndef for_each_set_bit_from +#define for_each_set_bit_from(bit, addr, size) \ + for ((bit) = find_next_bit((addr), (size), (bit)); \ + (bit) < (size); \ + (bit) = find_next_bit((addr), (size), (bit) + 1)) +#endif /* for_each_set_bit_from */ + +#else /* < 3.4.0 */ +#include +#endif /* >= 3.4.0 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,0) ) || \ + ( RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,4) ) +#if !defined(NO_PTP_SUPPORT) && IS_ENABLED(CONFIG_PTP_1588_CLOCK) +#define HAVE_PTP_1588_CLOCK +#endif /* !NO_PTP_SUPPORT && IS_ENABLED(CONFIG_PTP_1588_CLOCK) */ +#endif /* >= 3.0.0 || RHEL_RELEASE > 6.4 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0) ) + +#ifndef SIZE_MAX +#define SIZE_MAX (~(size_t)0) +#endif + +#ifndef BITS_PER_LONG_LONG +#define BITS_PER_LONG_LONG 64 +#endif + +#ifndef ether_addr_equal +static inline bool __kc_ether_addr_equal(const u8 *addr1, const u8 *addr2) +{ + return !compare_ether_addr(addr1, addr2); +} +#define ether_addr_equal(_addr1, _addr2) __kc_ether_addr_equal((_addr1),(_addr2)) +#endif + +/* Definitions for !CONFIG_OF_NET are introduced in 3.10 */ +#ifdef CONFIG_OF_NET +static inline int of_get_phy_mode(struct device_node __always_unused *np) +{ + return -ENODEV; +} + +static inline const void * +of_get_mac_address(struct device_node __always_unused *np) +{ + return NULL; +} +#endif +#else +#include +#define HAVE_FDB_OPS +#define HAVE_ETHTOOL_GET_TS_INFO +#endif /* < 3.5.0 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,6,0) ) +#define PCI_EXP_LNKCAP2 44 /* Link Capability 2 */ + +#ifndef MDIO_EEE_100TX +#define MDIO_EEE_100TX 0x0002 /* 100TX EEE cap */ +#endif +#ifndef MDIO_EEE_1000T +#define MDIO_EEE_1000T 0x0004 /* 1000T EEE cap */ +#endif +#ifndef MDIO_EEE_10GT +#define MDIO_EEE_10GT 0x0008 /* 10GT EEE cap */ +#endif +#ifndef MDIO_EEE_1000KX +#define MDIO_EEE_1000KX 0x0010 /* 1000KX EEE cap */ +#endif +#ifndef MDIO_EEE_10GKX4 +#define MDIO_EEE_10GKX4 0x0020 /* 10G KX4 EEE cap */ +#endif +#ifndef MDIO_EEE_10GKR +#define MDIO_EEE_10GKR 0x0040 /* 10G KR EEE cap */ +#endif + +#ifndef __GFP_MEMALLOC +#define __GFP_MEMALLOC 0 +#endif + +#ifndef eth_broadcast_addr +#define eth_broadcast_addr _kc_eth_broadcast_addr +static inline void _kc_eth_broadcast_addr(u8 *addr) +{ + memset(addr, 0xff, ETH_ALEN); +} +#endif + +#ifndef eth_random_addr +#define eth_random_addr _kc_eth_random_addr +static inline void _kc_eth_random_addr(u8 *addr) +{ + get_random_bytes(addr, ETH_ALEN); + addr[0] &= 0xfe; /* clear multicast */ + addr[0] |= 0x02; /* set local assignment */ +} +#endif /* eth_random_addr */ + +#ifndef DMA_ATTR_SKIP_CPU_SYNC +#define DMA_ATTR_SKIP_CPU_SYNC 0 +#endif +#else /* < 3.6.0 */ +#define HAVE_STRUCT_PAGE_PFMEMALLOC +#endif /* < 3.6.0 */ + +/******************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,7,0) ) +#include +#ifndef ADVERTISED_40000baseKR4_Full +/* these defines were all added in one commit, so should be safe + * to trigger activiation on one define + */ +#define SUPPORTED_40000baseKR4_Full BIT(23) +#define SUPPORTED_40000baseCR4_Full BIT(24) +#define SUPPORTED_40000baseSR4_Full BIT(25) +#define SUPPORTED_40000baseLR4_Full BIT(26) +#define ADVERTISED_40000baseKR4_Full BIT(23) +#define ADVERTISED_40000baseCR4_Full BIT(24) +#define ADVERTISED_40000baseSR4_Full BIT(25) +#define ADVERTISED_40000baseLR4_Full BIT(26) +#endif + +#ifndef mmd_eee_cap_to_ethtool_sup_t +/** + * mmd_eee_cap_to_ethtool_sup_t + * @eee_cap: value of the MMD EEE Capability register + * + * A small helper function that translates MMD EEE Capability (3.20) bits + * to ethtool supported settings. + */ +static inline u32 __kc_mmd_eee_cap_to_ethtool_sup_t(u16 eee_cap) +{ + u32 supported = 0; + + if (eee_cap & MDIO_EEE_100TX) + supported |= SUPPORTED_100baseT_Full; + if (eee_cap & MDIO_EEE_1000T) + supported |= SUPPORTED_1000baseT_Full; + if (eee_cap & MDIO_EEE_10GT) + supported |= SUPPORTED_10000baseT_Full; + if (eee_cap & MDIO_EEE_1000KX) + supported |= SUPPORTED_1000baseKX_Full; + if (eee_cap & MDIO_EEE_10GKX4) + supported |= SUPPORTED_10000baseKX4_Full; + if (eee_cap & MDIO_EEE_10GKR) + supported |= SUPPORTED_10000baseKR_Full; + + return supported; +} +#define mmd_eee_cap_to_ethtool_sup_t(eee_cap) \ + __kc_mmd_eee_cap_to_ethtool_sup_t(eee_cap) +#endif /* mmd_eee_cap_to_ethtool_sup_t */ + +#ifndef mmd_eee_adv_to_ethtool_adv_t +/** + * mmd_eee_adv_to_ethtool_adv_t + * @eee_adv: value of the MMD EEE Advertisement/Link Partner Ability registers + * + * A small helper function that translates the MMD EEE Advertisement (7.60) + * and MMD EEE Link Partner Ability (7.61) bits to ethtool advertisement + * settings. + */ +static inline u32 __kc_mmd_eee_adv_to_ethtool_adv_t(u16 eee_adv) +{ + u32 adv = 0; + + if (eee_adv & MDIO_EEE_100TX) + adv |= ADVERTISED_100baseT_Full; + if (eee_adv & MDIO_EEE_1000T) + adv |= ADVERTISED_1000baseT_Full; + if (eee_adv & MDIO_EEE_10GT) + adv |= ADVERTISED_10000baseT_Full; + if (eee_adv & MDIO_EEE_1000KX) + adv |= ADVERTISED_1000baseKX_Full; + if (eee_adv & MDIO_EEE_10GKX4) + adv |= ADVERTISED_10000baseKX4_Full; + if (eee_adv & MDIO_EEE_10GKR) + adv |= ADVERTISED_10000baseKR_Full; + + return adv; +} + +#define mmd_eee_adv_to_ethtool_adv_t(eee_adv) \ + __kc_mmd_eee_adv_to_ethtool_adv_t(eee_adv) +#endif /* mmd_eee_adv_to_ethtool_adv_t */ + +#ifndef ethtool_adv_to_mmd_eee_adv_t +/** + * ethtool_adv_to_mmd_eee_adv_t + * @adv: the ethtool advertisement settings + * + * A small helper function that translates ethtool advertisement settings + * to EEE advertisements for the MMD EEE Advertisement (7.60) and + * MMD EEE Link Partner Ability (7.61) registers. + */ +static inline u16 __kc_ethtool_adv_to_mmd_eee_adv_t(u32 adv) +{ + u16 reg = 0; + + if (adv & ADVERTISED_100baseT_Full) + reg |= MDIO_EEE_100TX; + if (adv & ADVERTISED_1000baseT_Full) + reg |= MDIO_EEE_1000T; + if (adv & ADVERTISED_10000baseT_Full) + reg |= MDIO_EEE_10GT; + if (adv & ADVERTISED_1000baseKX_Full) + reg |= MDIO_EEE_1000KX; + if (adv & ADVERTISED_10000baseKX4_Full) + reg |= MDIO_EEE_10GKX4; + if (adv & ADVERTISED_10000baseKR_Full) + reg |= MDIO_EEE_10GKR; + + return reg; +} +#define ethtool_adv_to_mmd_eee_adv_t(adv) __kc_ethtool_adv_to_mmd_eee_adv_t(adv) +#endif /* ethtool_adv_to_mmd_eee_adv_t */ + +#ifndef pci_pcie_type +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) ) +static inline u8 pci_pcie_type(struct pci_dev *pdev) +{ + int pos; + u16 reg16; + + pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); + BUG_ON(!pos); + pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); + return (reg16 & PCI_EXP_FLAGS_TYPE) >> 4; +} +#else /* < 2.6.24 */ +#define pci_pcie_type(x) (x)->pcie_type +#endif /* < 2.6.24 */ +#endif /* pci_pcie_type */ + +#if ( ! ( RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,4) ) ) && \ + ( ! ( SLE_VERSION_CODE >= SLE_VERSION(11,3,0) ) ) && \ + ( LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,0) ) +#define ptp_clock_register(caps, args...) ptp_clock_register(caps) +#endif + +#ifndef pcie_capability_read_word +int __kc_pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val); +#define pcie_capability_read_word(d,p,v) __kc_pcie_capability_read_word(d,p,v) +#endif /* pcie_capability_read_word */ + +#ifndef pcie_capability_read_dword +int __kc_pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val); +#define pcie_capability_read_dword(d,p,v) __kc_pcie_capability_read_dword(d,p,v) +#endif + +#ifndef pcie_capability_write_word +int __kc_pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val); +#define pcie_capability_write_word(d,p,v) __kc_pcie_capability_write_word(d,p,v) +#endif /* pcie_capability_write_word */ + +#ifndef pcie_capability_clear_and_set_word +int __kc_pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, + u16 clear, u16 set); +#define pcie_capability_clear_and_set_word(d,p,c,s) \ + __kc_pcie_capability_clear_and_set_word(d,p,c,s) +#endif /* pcie_capability_clear_and_set_word */ + +#ifndef pcie_capability_clear_word +int __kc_pcie_capability_clear_word(struct pci_dev *dev, int pos, + u16 clear); +#define pcie_capability_clear_word(d, p, c) \ + __kc_pcie_capability_clear_word(d, p, c) +#endif /* pcie_capability_clear_word */ + +#ifndef PCI_EXP_LNKSTA2 +#define PCI_EXP_LNKSTA2 50 /* Link Status 2 */ +#endif + +#if (SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(11,3,0)) +#define USE_CONST_DEV_UC_CHAR +#define HAVE_NDO_FDB_ADD_NLATTR +#endif + +#if !(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,8)) +#define napi_gro_flush(_napi, _flush_old) napi_gro_flush(_napi) +#endif /* !RHEL6.8+ */ + +#if (RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,6)) +#include +#else + +#define DEFINE_HASHTABLE(name, bits) \ + struct hlist_head name[1 << (bits)] = \ + { [0 ... ((1 << (bits)) - 1)] = HLIST_HEAD_INIT } + +#define DECLARE_HASHTABLE(name, bits) \ + struct hlist_head name[1 << (bits)] + +#define HASH_SIZE(name) (ARRAY_SIZE(name)) +#define HASH_BITS(name) ilog2(HASH_SIZE(name)) + +/* Use hash_32 when possible to allow for fast 32bit hashing in 64bit kernels. */ +#define hash_min(val, bits) \ + (sizeof(val) <= 4 ? hash_32(val, bits) : hash_long(val, bits)) + +static inline void __hash_init(struct hlist_head *ht, unsigned int sz) +{ + unsigned int i; + + for (i = 0; i < sz; i++) + INIT_HLIST_HEAD(&ht[i]); +} + +#define hash_init(hashtable) __hash_init(hashtable, HASH_SIZE(hashtable)) + +#define hash_add(hashtable, node, key) \ + hlist_add_head(node, &hashtable[hash_min(key, HASH_BITS(hashtable))]) + +static inline bool hash_hashed(struct hlist_node *node) +{ + return !hlist_unhashed(node); +} + +static inline bool __hash_empty(struct hlist_head *ht, unsigned int sz) +{ + unsigned int i; + + for (i = 0; i < sz; i++) + if (!hlist_empty(&ht[i])) + return false; + + return true; +} + +#define hash_empty(hashtable) __hash_empty(hashtable, HASH_SIZE(hashtable)) + +static inline void hash_del(struct hlist_node *node) +{ + hlist_del_init(node); +} +#endif /* RHEL >= 6.6 */ + +/* We don't have @flags support prior to 3.7, so we'll simply ignore the flags + * parameter on these older kernels. + */ +#define __setup_timer(_timer, _fn, _data, _flags) \ + setup_timer((_timer), (_fn), (_data)) \ + +#if ( ! ( RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,7) ) ) && \ + ( ! ( SLE_VERSION_CODE >= SLE_VERSION(12,0,0) ) ) + +#ifndef mod_delayed_work +/** + * __mod_delayed_work - modify delay or queue delayed work + * @wq: workqueue to use + * @dwork: delayed work to queue + * @delay: number of jiffies to wait before queueing + * + * Return: %true if @dwork was pending and was rescheduled; + * %false if it wasn't pending + * + * Note: the dwork parameter was declared as a void* + * to avoid comptibility problems with early 2.6 kernels + * where struct delayed_work is not declared. Unlike the original + * implementation flags are not preserved and it shouldn't be + * used in the interrupt context. + */ +static inline bool __mod_delayed_work(struct workqueue_struct *wq, + void *dwork, + unsigned long delay) +{ + bool ret = cancel_delayed_work(dwork); + queue_delayed_work(wq, dwork, delay); + return ret; +} +#define mod_delayed_work(wq, dwork, delay) __mod_delayed_work(wq, dwork, delay) +#endif /* mod_delayed_work */ + +#endif /* !(RHEL >= 6.7) && !(SLE >= 12.0) */ +#else /* >= 3.7.0 */ +#include +#define HAVE_CONST_STRUCT_PCI_ERROR_HANDLERS +#define USE_CONST_DEV_UC_CHAR +#define HAVE_NDO_FDB_ADD_NLATTR +#endif /* >= 3.7.0 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,8,0) ) +#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,5)) && \ + !(SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(11,4,0))) +#ifndef pci_sriov_set_totalvfs +static inline int __kc_pci_sriov_set_totalvfs(struct pci_dev __always_unused *dev, u16 __always_unused numvfs) +{ + return 0; +} +#define pci_sriov_set_totalvfs(a, b) __kc_pci_sriov_set_totalvfs((a), (b)) +#endif +#endif /* !(RHEL_RELEASE_CODE >= 6.5 && SLE_VERSION_CODE >= 11.4) */ +#ifndef PCI_EXP_LNKCTL_ASPM_L0S +#define PCI_EXP_LNKCTL_ASPM_L0S 0x01 /* L0s Enable */ +#endif +#ifndef PCI_EXP_LNKCTL_ASPM_L1 +#define PCI_EXP_LNKCTL_ASPM_L1 0x02 /* L1 Enable */ +#endif +#define HAVE_CONFIG_HOTPLUG +/* Reserved Ethernet Addresses per IEEE 802.1Q */ +static const u8 eth_reserved_addr_base[ETH_ALEN] __aligned(2) = { + 0x01, 0x80, 0xc2, 0x00, 0x00, 0x00 }; + +#ifndef is_link_local_ether_addr +static inline bool __kc_is_link_local_ether_addr(const u8 *addr) +{ + __be16 *a = (__be16 *)addr; + static const __be16 *b = (const __be16 *)eth_reserved_addr_base; + static const __be16 m = cpu_to_be16(0xfff0); + + return ((a[0] ^ b[0]) | (a[1] ^ b[1]) | ((a[2] ^ b[2]) & m)) == 0; +} +#define is_link_local_ether_addr(addr) __kc_is_link_local_ether_addr(addr) +#endif /* is_link_local_ether_addr */ + +#ifndef FLOW_MAC_EXT +#define FLOW_MAC_EXT 0x40000000 +#endif /* FLOW_MAC_EXT */ + +#if (SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(11,4,0)) +#define HAVE_SRIOV_CONFIGURE +#endif + +#ifndef PCI_EXP_LNKCAP_SLS_2_5GB +#define PCI_EXP_LNKCAP_SLS_2_5GB 0x00000001 /* LNKCAP2 SLS Vector bit 0 */ +#endif + +#ifndef PCI_EXP_LNKCAP_SLS_5_0GB +#define PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002 /* LNKCAP2 SLS Vector bit 1 */ +#endif + +#undef PCI_EXP_LNKCAP2_SLS_2_5GB +#define PCI_EXP_LNKCAP2_SLS_2_5GB 0x00000002 /* Supported Speed 2.5GT/s */ + +#undef PCI_EXP_LNKCAP2_SLS_5_0GB +#define PCI_EXP_LNKCAP2_SLS_5_0GB 0x00000004 /* Supported Speed 5GT/s */ + +#undef PCI_EXP_LNKCAP2_SLS_8_0GB +#define PCI_EXP_LNKCAP2_SLS_8_0GB 0x00000008 /* Supported Speed 8GT/s */ + +#else /* >= 3.8.0 */ +#ifndef __devinit +#define __devinit +#endif + +#ifndef __devinitdata +#define __devinitdata +#endif + +#ifndef __devinitconst +#define __devinitconst +#endif + +#ifndef __devexit +#define __devexit +#endif + +#ifndef __devexit_p +#define __devexit_p +#endif + +#ifndef HAVE_ENCAP_CSUM_OFFLOAD +#define HAVE_ENCAP_CSUM_OFFLOAD +#endif + +#ifndef HAVE_GRE_ENCAP_OFFLOAD +#define HAVE_GRE_ENCAP_OFFLOAD +#endif + +#ifndef HAVE_SRIOV_CONFIGURE +#define HAVE_SRIOV_CONFIGURE +#endif + +#define HAVE_BRIDGE_ATTRIBS +#ifndef BRIDGE_MODE_VEB +#define BRIDGE_MODE_VEB 0 /* Default loopback mode */ +#endif /* BRIDGE_MODE_VEB */ +#ifndef BRIDGE_MODE_VEPA +#define BRIDGE_MODE_VEPA 1 /* 802.1Qbg defined VEPA mode */ +#endif /* BRIDGE_MODE_VEPA */ +#endif /* >= 3.8.0 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,9,0) ) + +#undef BUILD_BUG_ON +#ifdef __CHECKER__ +#define BUILD_BUG_ON(condition) (0) +#else /* __CHECKER__ */ +#ifndef __compiletime_warning +#if defined(__GNUC__) && ((__GNUC__ * 10000 + __GNUC_MINOR__ * 100) >= 40400) +#define __compiletime_warning(message) __attribute__((warning(message))) +#else /* __GNUC__ */ +#define __compiletime_warning(message) +#endif /* __GNUC__ */ +#endif /* __compiletime_warning */ +#ifndef __compiletime_error +#if defined(__GNUC__) && ((__GNUC__ * 10000 + __GNUC_MINOR__ * 100) >= 40400) +#define __compiletime_error(message) __attribute__((error(message))) +#define __compiletime_error_fallback(condition) do { } while (0) +#else /* __GNUC__ */ +#define __compiletime_error(message) +#define __compiletime_error_fallback(condition) \ + do { ((void)sizeof(char[1 - 2 * condition])); } while (0) +#endif /* __GNUC__ */ +#else /* __compiletime_error */ +#define __compiletime_error_fallback(condition) do { } while (0) +#endif /* __compiletime_error */ +#define __compiletime_assert(condition, msg, prefix, suffix) \ + do { \ + bool __cond = !(condition); \ + extern void prefix ## suffix(void) __compiletime_error(msg); \ + if (__cond) \ + prefix ## suffix(); \ + __compiletime_error_fallback(__cond); \ + } while (0) + +#define _compiletime_assert(condition, msg, prefix, suffix) \ + __compiletime_assert(condition, msg, prefix, suffix) +#define compiletime_assert(condition, msg) \ + _compiletime_assert(condition, msg, __compiletime_assert_, __LINE__) +#define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg) +#ifndef __OPTIMIZE__ +#define BUILD_BUG_ON(condition) ((void)sizeof(char[1 - 2*!!(condition)])) +#else /* __OPTIMIZE__ */ +#define BUILD_BUG_ON(condition) \ + BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition) +#endif /* __OPTIMIZE__ */ +#endif /* __CHECKER__ */ + +#undef hlist_entry +#define hlist_entry(ptr, type, member) container_of(ptr,type,member) + +#undef hlist_entry_safe +#define hlist_entry_safe(ptr, type, member) \ + ({ typeof(ptr) ____ptr = (ptr); \ + ____ptr ? hlist_entry(____ptr, type, member) : NULL; \ + }) + +#undef hlist_for_each_entry +#define hlist_for_each_entry(pos, head, member) \ + for (pos = hlist_entry_safe((head)->first, typeof(*(pos)), member); \ + pos; \ + pos = hlist_entry_safe((pos)->member.next, typeof(*(pos)), member)) + +#undef hlist_for_each_entry_safe +#define hlist_for_each_entry_safe(pos, n, head, member) \ + for (pos = hlist_entry_safe((head)->first, typeof(*pos), member); \ + pos && ({ n = pos->member.next; 1; }); \ + pos = hlist_entry_safe(n, typeof(*pos), member)) + +#undef hlist_for_each_entry_continue +#define hlist_for_each_entry_continue(pos, member) \ + for (pos = hlist_entry_safe((pos)->member.next, typeof(*(pos)), member);\ + pos; \ + pos = hlist_entry_safe((pos)->member.next, typeof(*(pos)), member)) + +#undef hlist_for_each_entry_from +#define hlist_for_each_entry_from(pos, member) \ + for (; pos; \ + pos = hlist_entry_safe((pos)->member.next, typeof(*(pos)), member)) + +#undef hash_for_each +#define hash_for_each(name, bkt, obj, member) \ + for ((bkt) = 0, obj = NULL; obj == NULL && (bkt) < HASH_SIZE(name);\ + (bkt)++)\ + hlist_for_each_entry(obj, &name[bkt], member) + +#undef hash_for_each_safe +#define hash_for_each_safe(name, bkt, tmp, obj, member) \ + for ((bkt) = 0, obj = NULL; obj == NULL && (bkt) < HASH_SIZE(name);\ + (bkt)++)\ + hlist_for_each_entry_safe(obj, tmp, &name[bkt], member) + +#undef hash_for_each_possible +#define hash_for_each_possible(name, obj, member, key) \ + hlist_for_each_entry(obj, &name[hash_min(key, HASH_BITS(name))], member) + +#undef hash_for_each_possible_safe +#define hash_for_each_possible_safe(name, obj, tmp, member, key) \ + hlist_for_each_entry_safe(obj, tmp,\ + &name[hash_min(key, HASH_BITS(name))], member) + +#ifdef CONFIG_XPS +int __kc_netif_set_xps_queue(struct net_device *, const struct cpumask *, u16); +#define netif_set_xps_queue(_dev, _mask, _idx) __kc_netif_set_xps_queue((_dev), (_mask), (_idx)) +#else /* CONFIG_XPS */ +#define netif_set_xps_queue(_dev, _mask, _idx) do {} while (0) +#endif /* CONFIG_XPS */ + +#ifdef HAVE_NETDEV_SELECT_QUEUE +#define _kc_hashrnd 0xd631614b /* not so random hash salt */ +u16 __kc_netdev_pick_tx(struct net_device *dev, struct sk_buff *skb); +#define __netdev_pick_tx __kc_netdev_pick_tx +#endif /* HAVE_NETDEV_SELECT_QUEUE */ +#else +#define HAVE_BRIDGE_FILTER +#define HAVE_FDB_DEL_NLATTR +#endif /* < 3.9.0 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,10,0) ) +#ifndef NAPI_POLL_WEIGHT +#define NAPI_POLL_WEIGHT 64 +#endif +#ifdef CONFIG_PCI_IOV +int __kc_pci_vfs_assigned(struct pci_dev *dev); +#else +static inline int __kc_pci_vfs_assigned(struct pci_dev __always_unused *dev) +{ + return 0; +} +#endif +#define pci_vfs_assigned(dev) __kc_pci_vfs_assigned(dev) + +#ifndef list_first_entry_or_null +#define list_first_entry_or_null(ptr, type, member) \ + (!list_empty(ptr) ? list_first_entry(ptr, type, member) : NULL) +#endif + +#ifndef VLAN_TX_COOKIE_MAGIC +static inline struct sk_buff *__kc__vlan_hwaccel_put_tag(struct sk_buff *skb, + u16 vlan_tci) +{ +#ifdef VLAN_TAG_PRESENT + vlan_tci |= VLAN_TAG_PRESENT; +#endif + skb->vlan_tci = vlan_tci; + return skb; +} +#define __vlan_hwaccel_put_tag(skb, vlan_proto, vlan_tci) \ + __kc__vlan_hwaccel_put_tag(skb, vlan_tci) +#endif + +#ifdef HAVE_FDB_OPS +#if defined(HAVE_NDO_FDB_ADD_NLATTR) +int __kc_ndo_dflt_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], + struct net_device *dev, + const unsigned char *addr, u16 flags); +#elif defined(USE_CONST_DEV_UC_CHAR) +int __kc_ndo_dflt_fdb_add(struct ndmsg *ndm, struct net_device *dev, + const unsigned char *addr, u16 flags); +#else +int __kc_ndo_dflt_fdb_add(struct ndmsg *ndm, struct net_device *dev, + unsigned char *addr, u16 flags); +#endif /* HAVE_NDO_FDB_ADD_NLATTR */ +#if defined(HAVE_FDB_DEL_NLATTR) +int __kc_ndo_dflt_fdb_del(struct ndmsg *ndm, struct nlattr *tb[], + struct net_device *dev, + const unsigned char *addr); +#elif defined(USE_CONST_DEV_UC_CHAR) +int __kc_ndo_dflt_fdb_del(struct ndmsg *ndm, struct net_device *dev, + const unsigned char *addr); +#else +int __kc_ndo_dflt_fdb_del(struct ndmsg *ndm, struct net_device *dev, + unsigned char *addr); +#endif /* HAVE_FDB_DEL_NLATTR */ +#define ndo_dflt_fdb_add __kc_ndo_dflt_fdb_add +#define ndo_dflt_fdb_del __kc_ndo_dflt_fdb_del +#endif /* HAVE_FDB_OPS */ + +#ifndef PCI_DEVID +#define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn)) +#endif + +/* The definitions for these functions when CONFIG_OF_NET is defined are + * pulled in from . For kernels older than 3.5 we already have + * backports for when CONFIG_OF_NET is true. These are separated and + * duplicated in order to cover all cases so that all kernels get either the + * real definitions (when CONFIG_OF_NET is defined) or the stub definitions + * (when CONFIG_OF_NET is not defined, or the kernel is too old to have real + * definitions). + */ +#ifndef CONFIG_OF_NET +static inline int of_get_phy_mode(struct device_node __always_unused *np) +{ + return -ENODEV; +} + +static inline const void * +of_get_mac_address(struct device_node __always_unused *np) +{ + return NULL; +} +#endif + +#else /* >= 3.10.0 */ +#define HAVE_ENCAP_TSO_OFFLOAD +#define USE_DEFAULT_FDB_DEL_DUMP +#define HAVE_SKB_INNER_NETWORK_HEADER + +#if (RHEL_RELEASE_CODE && \ + (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,0))) +#if (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(8,0)) +#define HAVE_RHEL7_PCI_DRIVER_RH +#if (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,2)) +#define HAVE_RHEL7_PCI_RESET_NOTIFY +#endif /* RHEL >= 7.2 */ +#if (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,3)) +#if (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7,5)) +#define HAVE_GENEVE_RX_OFFLOAD +#endif /* RHEL < 7.5 */ +#define HAVE_ETHTOOL_FLOW_UNION_IP6_SPEC +#define HAVE_RHEL7_NET_DEVICE_OPS_EXT +#if !defined(HAVE_UDP_ENC_TUNNEL) && IS_ENABLED(CONFIG_GENEVE) +#define HAVE_UDP_ENC_TUNNEL +#endif /* !HAVE_UDP_ENC_TUNNEL && CONFIG_GENEVE */ +#endif /* RHEL >= 7.3 */ + +/* new hooks added to net_device_ops_extended in RHEL7.4 */ +#if (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,4)) +#define HAVE_RHEL7_NETDEV_OPS_EXT_NDO_SET_VF_VLAN +#define HAVE_RHEL7_NETDEV_OPS_EXT_NDO_UDP_TUNNEL +#define HAVE_UDP_ENC_RX_OFFLOAD +#endif /* RHEL >= 7.4 */ +#else /* RHEL >= 8.0 */ +#define HAVE_TCF_BLOCK_CB_REGISTER_EXTACK +#define NO_NETDEV_BPF_PROG_ATTACHED +#define HAVE_NDO_SELECT_QUEUE_SB_DEV +#endif /* RHEL >= 8.0 */ +#endif /* RHEL >= 7.0 */ +#endif /* >= 3.10.0 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,11,0) ) +#define netdev_notifier_info_to_dev(ptr) ptr +#ifndef time_in_range64 +#define time_in_range64(a, b, c) \ + (time_after_eq64(a, b) && \ + time_before_eq64(a, c)) +#endif /* time_in_range64 */ +#if ((RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,6)) ||\ + (SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(11,4,0))) +#define HAVE_NDO_SET_VF_LINK_STATE +#endif +#if RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(7,2)) +#define HAVE_NDO_SELECT_QUEUE_ACCEL_FALLBACK +#endif +#else /* >= 3.11.0 */ +#define HAVE_NDO_SET_VF_LINK_STATE +#define HAVE_SKB_INNER_PROTOCOL +#define HAVE_MPLS_FEATURES +#endif /* >= 3.11.0 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,12,0) ) +int __kc_pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed, + enum pcie_link_width *width); +#ifndef pcie_get_minimum_link +#define pcie_get_minimum_link(_p, _s, _w) __kc_pcie_get_minimum_link(_p, _s, _w) +#endif + +#if (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(6,7)) +int _kc_pci_wait_for_pending_transaction(struct pci_dev *dev); +#define pci_wait_for_pending_transaction _kc_pci_wait_for_pending_transaction +#endif /* = 3.12.0 */ +#if ( SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(12,0,0)) +#define HAVE_NDO_SELECT_QUEUE_ACCEL_FALLBACK +#endif +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,8,0) ) +#define HAVE_VXLAN_RX_OFFLOAD +#if !defined(HAVE_UDP_ENC_TUNNEL) && IS_ENABLED(CONFIG_VXLAN) +#define HAVE_UDP_ENC_TUNNEL +#endif +#endif /* < 4.8.0 */ +#define HAVE_NDO_GET_PHYS_PORT_ID +#define HAVE_NETIF_SET_XPS_QUEUE_CONST_MASK +#endif /* >= 3.12.0 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,13,0) ) +#define dma_set_mask_and_coherent(_p, _m) __kc_dma_set_mask_and_coherent(_p, _m) +int __kc_dma_set_mask_and_coherent(struct device *dev, u64 mask); +#ifndef u64_stats_init +#define u64_stats_init(a) do { } while(0) +#endif +#undef BIT_ULL +#define BIT_ULL(n) (1ULL << (n)) + +#if (!(SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(12,0,0)) && \ + !(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,0))) +static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) +{ + dev = pci_physfn(dev); + if (pci_is_root_bus(dev->bus)) + return NULL; + + return dev->bus->self; +} +#endif + +#if (SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(12,1,0)) +#undef HAVE_STRUCT_PAGE_PFMEMALLOC +#define HAVE_DCBNL_OPS_SETAPP_RETURN_INT +#endif +#ifndef list_next_entry +#define list_next_entry(pos, member) \ + list_entry((pos)->member.next, typeof(*(pos)), member) +#endif +#ifndef list_prev_entry +#define list_prev_entry(pos, member) \ + list_entry((pos)->member.prev, typeof(*(pos)), member) +#endif + +#if ( LINUX_VERSION_CODE > KERNEL_VERSION(2,6,20) ) +#define devm_kcalloc(dev, cnt, size, flags) \ + devm_kzalloc(dev, cnt * size, flags) +#endif /* > 2.6.20 */ + +#if (!(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,2))) +#define list_last_entry(ptr, type, member) list_entry((ptr)->prev, type, member) +#endif + +#if (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7,0)) +bool _kc_pci_device_is_present(struct pci_dev *pdev); +#define pci_device_is_present _kc_pci_device_is_present +#endif /* = 3.13.0 */ +#define HAVE_VXLAN_CHECKS +#if (UBUNTU_VERSION_CODE && UBUNTU_VERSION_CODE >= UBUNTU_VERSION(3,13,0,24)) +#define HAVE_NDO_SELECT_QUEUE_ACCEL_FALLBACK +#else +#define HAVE_NDO_SELECT_QUEUE_ACCEL +#endif +#define HAVE_HWMON_DEVICE_REGISTER_WITH_GROUPS +#endif + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,14,0) ) + +#ifndef U16_MAX +#define U16_MAX ((u16)~0U) +#endif + +#ifndef U32_MAX +#define U32_MAX ((u32)~0U) +#endif + +#ifndef U64_MAX +#define U64_MAX ((u64)~0ULL) +#endif + +#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,2))) +#define dev_consume_skb_any(x) dev_kfree_skb_any(x) +#define dev_consume_skb_irq(x) dev_kfree_skb_irq(x) +#endif + +#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,0)) && \ + !(SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(12,0,0))) + +/* it isn't expected that this would be a #define unless we made it so */ +#ifndef skb_set_hash + +#define PKT_HASH_TYPE_NONE 0 +#define PKT_HASH_TYPE_L2 1 +#define PKT_HASH_TYPE_L3 2 +#define PKT_HASH_TYPE_L4 3 + +enum _kc_pkt_hash_types { + _KC_PKT_HASH_TYPE_NONE = PKT_HASH_TYPE_NONE, + _KC_PKT_HASH_TYPE_L2 = PKT_HASH_TYPE_L2, + _KC_PKT_HASH_TYPE_L3 = PKT_HASH_TYPE_L3, + _KC_PKT_HASH_TYPE_L4 = PKT_HASH_TYPE_L4, +}; +#define pkt_hash_types _kc_pkt_hash_types + +#define skb_set_hash __kc_skb_set_hash +static inline void __kc_skb_set_hash(struct sk_buff __maybe_unused *skb, + u32 __maybe_unused hash, + int __maybe_unused type) +{ +#ifdef HAVE_SKB_L4_RXHASH + skb->l4_rxhash = (type == PKT_HASH_TYPE_L4); +#endif +#ifdef NETIF_F_RXHASH + skb->rxhash = hash; +#endif +} +#endif /* !skb_set_hash */ + +#else /* RHEL_RELEASE_CODE >= 7.0 || SLE_VERSION_CODE >= 12.0 */ + +#if ((RHEL_RELEASE_CODE && RHEL_RELEASE_CODE <= RHEL_RELEASE_VERSION(7,0)) ||\ + (SLE_VERSION_CODE && SLE_VERSION_CODE <= SLE_VERSION(12,1,0))) +/* GPLv2 code taken from 5.10-rc2 kernel source include/linux/pci.h, Copyright + * original authors. + */ +static inline int pci_enable_msix_exact(struct pci_dev *dev, + struct msix_entry *entries, int nvec) +{ + int rc = pci_enable_msix_range(dev, entries, nvec, nvec); + if (rc < 0) + return rc; + return 0; +} +#endif /* <=EL7.0 || <=SLES 12.1 */ +#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,5))) +#ifndef HAVE_VXLAN_RX_OFFLOAD +#define HAVE_VXLAN_RX_OFFLOAD +#endif /* HAVE_VXLAN_RX_OFFLOAD */ +#endif + +#if !defined(HAVE_UDP_ENC_TUNNEL) && IS_ENABLED(CONFIG_VXLAN) +#define HAVE_UDP_ENC_TUNNEL +#endif + +#ifndef HAVE_VXLAN_CHECKS +#define HAVE_VXLAN_CHECKS +#endif /* HAVE_VXLAN_CHECKS */ +#endif /* !(RHEL_RELEASE_CODE >= 7.0 && SLE_VERSION_CODE >= 12.0) */ + +#if ((RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,3)) ||\ + (SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(12,0,0))) +#define HAVE_NDO_DFWD_OPS +#endif + +#ifndef pci_enable_msix_range +int __kc_pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, + int minvec, int maxvec); +#define pci_enable_msix_range __kc_pci_enable_msix_range +#endif + +#ifndef ether_addr_copy +#define ether_addr_copy __kc_ether_addr_copy +static inline void __kc_ether_addr_copy(u8 *dst, const u8 *src) +{ +#if defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS) + *(u32 *)dst = *(const u32 *)src; + *(u16 *)(dst + 4) = *(const u16 *)(src + 4); +#else + u16 *a = (u16 *)dst; + const u16 *b = (const u16 *)src; + + a[0] = b[0]; + a[1] = b[1]; + a[2] = b[2]; +#endif +} +#endif /* ether_addr_copy */ +int __kc_ipv6_find_hdr(const struct sk_buff *skb, unsigned int *offset, + int target, unsigned short *fragoff, int *flags); +#define ipv6_find_hdr(a, b, c, d, e) __kc_ipv6_find_hdr((a), (b), (c), (d), (e)) + +#ifndef OPTIMIZE_HIDE_VAR +#ifdef __GNUC__ +#define OPTIMIZER_HIDE_VAR(var) __asm__ ("" : "=r" (var) : "0" (var)) +#else +#include +#define OPTIMIZE_HIDE_VAR(var) barrier() +#endif +#endif + +#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(7,0)) && \ + !(SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(10,4,0))) +static inline __u32 skb_get_hash_raw(const struct sk_buff *skb) +{ +#ifdef NETIF_F_RXHASH + return skb->rxhash; +#else + return 0; +#endif /* NETIF_F_RXHASH */ +} +#endif /* !RHEL > 5.9 && !SLES >= 10.4 */ + +#if (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7,5)) +#define request_firmware_direct request_firmware +#endif /* !RHEL || RHEL < 7.5 */ + +#else /* >= 3.14.0 */ + +/* for ndo_dfwd_ ops add_station, del_station and _start_xmit */ +#ifndef HAVE_NDO_DFWD_OPS +#define HAVE_NDO_DFWD_OPS +#endif +#define HAVE_NDO_SELECT_QUEUE_ACCEL_FALLBACK +#endif /* 3.14.0 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,15,0) ) +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35) ) +#define HAVE_SKBUFF_RXHASH +#endif /* >= 2.6.35 */ +#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(7,1)) && \ + !(UBUNTU_VERSION_CODE && UBUNTU_VERSION_CODE >= UBUNTU_VERSION(3,13,0,30))) +#define u64_stats_fetch_begin_irq u64_stats_fetch_begin_bh +#define u64_stats_fetch_retry_irq u64_stats_fetch_retry_bh +#endif + +char *_kc_devm_kstrdup(struct device *dev, const char *s, gfp_t gfp); +#define devm_kstrdup(dev, s, gfp) _kc_devm_kstrdup(dev, s, gfp) + +#else /* >= 3.15.0 */ +#define HAVE_NET_GET_RANDOM_ONCE +#define HAVE_PTP_1588_CLOCK_PINS +#define HAVE_NETDEV_PORT +#endif /* 3.15.0 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,16,0) ) +#ifndef smp_mb__before_atomic +#define smp_mb__before_atomic() smp_mb() +#define smp_mb__after_atomic() smp_mb() +#endif +#ifndef __dev_uc_sync +#ifdef HAVE_SET_RX_MODE +#ifdef NETDEV_HW_ADDR_T_UNICAST +int __kc_hw_addr_sync_dev(struct netdev_hw_addr_list *list, + struct net_device *dev, + int (*sync)(struct net_device *, const unsigned char *), + int (*unsync)(struct net_device *, const unsigned char *)); +void __kc_hw_addr_unsync_dev(struct netdev_hw_addr_list *list, + struct net_device *dev, + int (*unsync)(struct net_device *, const unsigned char *)); +#endif +#ifndef NETDEV_HW_ADDR_T_MULTICAST +int __kc_dev_addr_sync_dev(struct dev_addr_list **list, int *count, + struct net_device *dev, + int (*sync)(struct net_device *, const unsigned char *), + int (*unsync)(struct net_device *, const unsigned char *)); +void __kc_dev_addr_unsync_dev(struct dev_addr_list **list, int *count, + struct net_device *dev, + int (*unsync)(struct net_device *, const unsigned char *)); +#endif +#endif /* HAVE_SET_RX_MODE */ + +static inline int __kc_dev_uc_sync(struct net_device __maybe_unused *dev, + int __maybe_unused (*sync)(struct net_device *, const unsigned char *), + int __maybe_unused (*unsync)(struct net_device *, const unsigned char *)) +{ +#ifdef NETDEV_HW_ADDR_T_UNICAST + return __kc_hw_addr_sync_dev(&dev->uc, dev, sync, unsync); +#elif defined(HAVE_SET_RX_MODE) + return __kc_dev_addr_sync_dev(&dev->uc_list, &dev->uc_count, + dev, sync, unsync); +#else + return 0; +#endif +} +#define __dev_uc_sync __kc_dev_uc_sync + +static inline void __kc_dev_uc_unsync(struct net_device __maybe_unused *dev, + int __maybe_unused (*unsync)(struct net_device *, const unsigned char *)) +{ +#ifdef HAVE_SET_RX_MODE +#ifdef NETDEV_HW_ADDR_T_UNICAST + __kc_hw_addr_unsync_dev(&dev->uc, dev, unsync); +#else /* NETDEV_HW_ADDR_T_MULTICAST */ + __kc_dev_addr_unsync_dev(&dev->uc_list, &dev->uc_count, dev, unsync); +#endif /* NETDEV_HW_ADDR_T_UNICAST */ +#endif /* HAVE_SET_RX_MODE */ +} +#define __dev_uc_unsync __kc_dev_uc_unsync + +static inline int __kc_dev_mc_sync(struct net_device __maybe_unused *dev, + int __maybe_unused (*sync)(struct net_device *, const unsigned char *), + int __maybe_unused (*unsync)(struct net_device *, const unsigned char *)) +{ +#ifdef NETDEV_HW_ADDR_T_MULTICAST + return __kc_hw_addr_sync_dev(&dev->mc, dev, sync, unsync); +#elif defined(HAVE_SET_RX_MODE) + return __kc_dev_addr_sync_dev(&dev->mc_list, &dev->mc_count, + dev, sync, unsync); +#else + return 0; +#endif + +} +#define __dev_mc_sync __kc_dev_mc_sync + +static inline void __kc_dev_mc_unsync(struct net_device __maybe_unused *dev, + int __maybe_unused (*unsync)(struct net_device *, const unsigned char *)) +{ +#ifdef HAVE_SET_RX_MODE +#ifdef NETDEV_HW_ADDR_T_MULTICAST + __kc_hw_addr_unsync_dev(&dev->mc, dev, unsync); +#else /* NETDEV_HW_ADDR_T_MULTICAST */ + __kc_dev_addr_unsync_dev(&dev->mc_list, &dev->mc_count, dev, unsync); +#endif /* NETDEV_HW_ADDR_T_MULTICAST */ +#endif /* HAVE_SET_RX_MODE */ +} +#define __dev_mc_unsync __kc_dev_mc_unsync +#endif /* __dev_uc_sync */ + +#if RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(7,1)) +#define HAVE_NDO_SET_VF_MIN_MAX_TX_RATE +#endif + +#ifndef NETIF_F_GSO_UDP_TUNNEL_CSUM +/* if someone backports this, hopefully they backport as a #define. + * declare it as zero on older kernels so that if it get's or'd in + * it won't effect anything, therefore preventing core driver changes + */ +#define NETIF_F_GSO_UDP_TUNNEL_CSUM 0 +#define SKB_GSO_UDP_TUNNEL_CSUM 0 +#endif +void *__kc_devm_kmemdup(struct device *dev, const void *src, size_t len, + gfp_t gfp); +#define devm_kmemdup __kc_devm_kmemdup + +#else +#if ( ( LINUX_VERSION_CODE < KERNEL_VERSION(4,13,0) ) && \ + ! ( SLE_VERSION_CODE && ( SLE_VERSION_CODE >= SLE_VERSION(12,4,0)) ) ) +#define HAVE_PCI_ERROR_HANDLER_RESET_NOTIFY +#endif /* >= 3.16.0 && < 4.13.0 && !(SLES >= 12sp4) */ +#define HAVE_NDO_SET_VF_MIN_MAX_TX_RATE +#endif /* 3.16.0 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,17,0) ) +#if !(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,8) && \ + RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7,0)) && \ + !(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,2)) +#ifndef timespec64 +#define timespec64 timespec +static inline struct timespec64 timespec_to_timespec64(const struct timespec ts) +{ + return ts; +} +static inline struct timespec timespec64_to_timespec(const struct timespec64 ts64) +{ + return ts64; +} +#define timespec64_equal timespec_equal +#define timespec64_compare timespec_compare +#define set_normalized_timespec64 set_normalized_timespec +#define timespec64_add_safe timespec_add_safe +#define timespec64_add timespec_add +#define timespec64_sub timespec_sub +#define timespec64_valid timespec_valid +#define timespec64_valid_strict timespec_valid_strict +#define timespec64_to_ns timespec_to_ns +#define ns_to_timespec64 ns_to_timespec +#define ktime_to_timespec64 ktime_to_timespec +#define ktime_get_ts64 ktime_get_ts +#define ktime_get_real_ts64 ktime_get_real_ts +#define timespec64_add_ns timespec_add_ns +#endif /* timespec64 */ +#endif /* !(RHEL6.8= RHEL_RELEASE_VERSION(6,8) && \ + RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7,0)) +static inline void ktime_get_real_ts64(struct timespec64 *ts) +{ + *ts = ktime_to_timespec64(ktime_get_real()); +} + +static inline void ktime_get_ts64(struct timespec64 *ts) +{ + *ts = ktime_to_timespec64(ktime_get()); +} +#endif + +#if !(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,4)) +#define hlist_add_behind(_a, _b) hlist_add_after(_b, _a) +#endif + +#if (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7,5)) +#endif /* RHEL_RELEASE_CODE < RHEL7.5 */ + +#if RHEL_RELEASE_CODE && \ + RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(6,3) && \ + RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7,3) +static inline u64 ktime_get_ns(void) +{ + return ktime_to_ns(ktime_get()); +} + +static inline u64 ktime_get_real_ns(void) +{ + return ktime_to_ns(ktime_get_real()); +} + +static inline u64 ktime_get_boot_ns(void) +{ + return ktime_to_ns(ktime_get_boottime()); +} +#endif /* RHEL < 7.3 */ + +#else +#define HAVE_DCBNL_OPS_SETAPP_RETURN_INT +#include +#define HAVE_RHASHTABLE +#endif /* 3.17.0 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,18,0) ) +#ifndef NO_PTP_SUPPORT +#include +struct sk_buff *__kc_skb_clone_sk(struct sk_buff *skb); +void __kc_skb_complete_tx_timestamp(struct sk_buff *skb, + struct skb_shared_hwtstamps *hwtstamps); +#define skb_clone_sk __kc_skb_clone_sk +#define skb_complete_tx_timestamp __kc_skb_complete_tx_timestamp +#endif +#if (!(RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8,2)))) +u32 __kc_eth_get_headlen(const struct net_device *dev, unsigned char *data, + unsigned int max_len); +#else +unsigned int __kc_eth_get_headlen(unsigned char *data, unsigned int max_len); +#endif /* !RHEL >= 8.2 */ + +#define eth_get_headlen __kc_eth_get_headlen +#ifndef ETH_P_XDSA +#define ETH_P_XDSA 0x00F8 +#endif +/* RHEL 7.1 backported csum_level, but SLES 12 and 12-SP1 did not */ +#if RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,1)) +#define HAVE_SKBUFF_CSUM_LEVEL +#endif /* >= RH 7.1 */ + +/* RHEL 7.3 backported xmit_more */ +#if (RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,3)) +#define HAVE_SKB_XMIT_MORE +#endif /* >= RH 7.3 */ + +#undef GENMASK +#define GENMASK(h, l) \ + (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) +#undef GENMASK_ULL +#define GENMASK_ULL(h, l) \ + (((~0ULL) << (l)) & (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h)))) + +#else /* 3.18.0 */ +#define HAVE_SKBUFF_CSUM_LEVEL +#define HAVE_SKB_XMIT_MORE +#define HAVE_SKB_INNER_PROTOCOL_TYPE +#endif /* 3.18.0 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,18,4) ) +#else +#define HAVE_NDO_FEATURES_CHECK +#endif /* 3.18.4 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,18,13) ) +#ifndef WRITE_ONCE +#define WRITE_ONCE(x, val) ({ ACCESS_ONCE(x) = (val); }) +#endif +#endif /* 3.18.13 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,19,0) ) +/* netdev_phys_port_id renamed to netdev_phys_item_id */ +#define netdev_phys_item_id netdev_phys_port_id + +static inline void _kc_napi_complete_done(struct napi_struct *napi, + int __always_unused work_done) { + napi_complete(napi); +} +/* don't use our backport if the distro kernels already have it */ +#if (SLE_VERSION_CODE && (SLE_VERSION_CODE < SLE_VERSION(12,3,0))) || \ + (RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7,5))) +#define napi_complete_done _kc_napi_complete_done +#endif + +int _kc_bitmap_print_to_pagebuf(bool list, char *buf, + const unsigned long *maskp, int nmaskbits); +#define bitmap_print_to_pagebuf _kc_bitmap_print_to_pagebuf + +#ifndef NETDEV_RSS_KEY_LEN +#define NETDEV_RSS_KEY_LEN (13 * 4) +#endif +#if (!(RHEL_RELEASE_CODE && \ + ((RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,7) && RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7,0)) || \ + (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,2))))) +#define netdev_rss_key_fill(buffer, len) __kc_netdev_rss_key_fill(buffer, len) +#endif /* RHEL_RELEASE_CODE */ +void __kc_netdev_rss_key_fill(void *buffer, size_t len); +#define SPEED_20000 20000 +#define SPEED_40000 40000 +#ifndef dma_rmb +#define dma_rmb() rmb() +#endif +#ifndef dev_alloc_pages +#ifndef NUMA_NO_NODE +#define NUMA_NO_NODE -1 +#endif +#define dev_alloc_pages(_order) alloc_pages_node(NUMA_NO_NODE, (GFP_ATOMIC | __GFP_COLD | __GFP_COMP | __GFP_MEMALLOC), (_order)) +#endif +#ifndef dev_alloc_page +#define dev_alloc_page() dev_alloc_pages(0) +#endif +#if !defined(eth_skb_pad) && !defined(skb_put_padto) +/** + * __kc_skb_put_padto - increase size and pad an skbuff up to a minimal size + * @skb: buffer to pad + * @len: minimal length + * + * Pads up a buffer to ensure the trailing bytes exist and are + * blanked. If the buffer already contains sufficient data it + * is untouched. Otherwise it is extended. Returns zero on + * success. The skb is freed on error. + */ +static inline int __kc_skb_put_padto(struct sk_buff *skb, unsigned int len) +{ + unsigned int size = skb->len; + + if (unlikely(size < len)) { + len -= size; + if (skb_pad(skb, len)) + return -ENOMEM; + __skb_put(skb, len); + } + return 0; +} +#define skb_put_padto(skb, len) __kc_skb_put_padto(skb, len) + +static inline int __kc_eth_skb_pad(struct sk_buff *skb) +{ + return __kc_skb_put_padto(skb, ETH_ZLEN); +} +#define eth_skb_pad(skb) __kc_eth_skb_pad(skb) +#endif /* eth_skb_pad && skb_put_padto */ + +#ifndef SKB_ALLOC_NAPI +/* RHEL 7.2 backported napi_alloc_skb and friends */ +static inline struct sk_buff *__kc_napi_alloc_skb(struct napi_struct *napi, unsigned int length) +{ + return netdev_alloc_skb_ip_align(napi->dev, length); +} +#define napi_alloc_skb(napi,len) __kc_napi_alloc_skb(napi,len) +#define __napi_alloc_skb(napi,len,mask) __kc_napi_alloc_skb(napi,len) +#endif /* SKB_ALLOC_NAPI */ +#define HAVE_CONFIG_PM_RUNTIME +#if (RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(6,7)) && \ + (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7,0))) +#define HAVE_RXFH_HASHFUNC +#endif /* 6.7 < RHEL < 7.0 */ +#if RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(7,1)) +#define HAVE_RXFH_HASHFUNC +#define NDO_DFLT_BRIDGE_GETLINK_HAS_BRFLAGS +#endif /* RHEL > 7.1 */ +#ifndef napi_schedule_irqoff +#define napi_schedule_irqoff napi_schedule +#endif +#ifndef READ_ONCE +#define READ_ONCE(_x) ACCESS_ONCE(_x) +#endif +#if RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(7,2)) +#define HAVE_NDO_FDB_ADD_VID +#endif +#ifndef ETH_MODULE_SFF_8636 +#define ETH_MODULE_SFF_8636 0x3 +#endif +#ifndef ETH_MODULE_SFF_8636_LEN +#define ETH_MODULE_SFF_8636_LEN 256 +#endif +#ifndef ETH_MODULE_SFF_8436 +#define ETH_MODULE_SFF_8436 0x4 +#endif +#ifndef ETH_MODULE_SFF_8436_LEN +#define ETH_MODULE_SFF_8436_LEN 256 +#endif +#ifndef writel_relaxed +#define writel_relaxed writel +#endif +#else /* 3.19.0 */ +#define HAVE_NDO_FDB_ADD_VID +#define HAVE_RXFH_HASHFUNC +#define NDO_DFLT_BRIDGE_GETLINK_HAS_BRFLAGS +#endif /* 3.19.0 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,20,0) ) +/* vlan_tx_xx functions got renamed to skb_vlan */ +#ifndef skb_vlan_tag_get +#define skb_vlan_tag_get vlan_tx_tag_get +#endif +#ifndef skb_vlan_tag_present +#define skb_vlan_tag_present vlan_tx_tag_present +#endif +#if RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(7,1)) +#define HAVE_INCLUDE_LINUX_TIMECOUNTER_H +#endif +#if RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(7,2)) +#define HAVE_NDO_BRIDGE_SET_DEL_LINK_FLAGS +#endif +#else +#define HAVE_INCLUDE_LINUX_TIMECOUNTER_H +#define HAVE_NDO_BRIDGE_SET_DEL_LINK_FLAGS +#endif /* 3.20.0 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) ) +/* Definition for CONFIG_OF was introduced earlier */ +#if !defined(CONFIG_OF) && \ + !(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(7,2)) +static inline struct device_node * +pci_device_to_OF_node(const struct pci_dev __always_unused *pdev) { return NULL; } +#else /* !CONFIG_OF && RHEL < 7.3 */ +#define HAVE_DDP_PROFILE_UPLOAD_SUPPORT +#endif /* !CONFIG_OF && RHEL < 7.3 */ +#else /* < 4.0 */ +#define HAVE_DDP_PROFILE_UPLOAD_SUPPORT +#endif /* < 4.0 */ + +/*****************************************************************************/ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,1,0) ) +#ifndef NO_PTP_SUPPORT +#ifdef HAVE_INCLUDE_LINUX_TIMECOUNTER_H +#include +#else +#include +#endif +static inline void __kc_timecounter_adjtime(struct timecounter *tc, s64 delta) +{ + tc->nsec += delta; +} + +static inline struct net_device * +of_find_net_device_by_node(struct device_node __always_unused *np) +{ + return NULL; +} + +#define timecounter_adjtime __kc_timecounter_adjtime +#endif +#if ((RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,2))) || \ + (SLE_VERSION_CODE && (SLE_VERSION_CODE >= SLE_VERSION(12,2,0)))) +#define HAVE_NDO_SET_VF_RSS_QUERY_EN +#endif +#if RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(7,2)) +#define HAVE_NDO_BRIDGE_GETLINK_NLFLAGS +#define HAVE_RHEL7_EXTENDED_NDO_SET_TX_MAXRATE +#define HAVE_NDO_SET_TX_MAXRATE +#endif +#if !((RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(6,8) && RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7,0)) && \ + (RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(7,2)) && \ + (SLE_VERSION_CODE > SLE_VERSION(12,1,0))) +unsigned int _kc_cpumask_local_spread(unsigned int i, int node); +#define cpumask_local_spread _kc_cpumask_local_spread +#endif +#ifdef HAVE_RHASHTABLE +#define rhashtable_loopup_fast(ht, key, params) \ + do { \ + (void)params; \ + rhashtable_lookup((ht), (key)); \ + } while (0) + +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,19,0) ) +#define rhashtable_insert_fast(ht, obj, params) \ + do { \ + (void)params; \ + rhashtable_insert((ht), (obj), GFP_KERNEL); \ + } while (0) + +#define rhashtable_remove_fast(ht, obj, params) \ + do { \ + (void)params; \ + rhashtable_remove((ht), (obj), GFP_KERNEL); \ + } while (0) + +#else /* >= 3,19,0 */ +#define rhashtable_insert_fast(ht, obj, params) \ + do { \ + (void)params; \ + rhashtable_insert((ht), (obj)); \ + } while (0) + +#define rhashtable_remove_fast(ht, obj, params) \ + do { \ + (void)params; \ + rhashtable_remove((ht), (obj)); \ + } while (0) + +#endif /* 3,19,0 */ +#endif /* HAVE_RHASHTABLE */ +#else /* >= 4,1,0 */ +#define HAVE_NDO_GET_PHYS_PORT_NAME +#define HAVE_PTP_CLOCK_INFO_GETTIME64 +#define HAVE_NDO_BRIDGE_GETLINK_NLFLAGS +#define HAVE_PASSTHRU_FEATURES_CHECK +#define HAVE_NDO_SET_VF_RSS_QUERY_EN +#define HAVE_NDO_SET_TX_MAXRATE +#endif /* 4,1,0 */ + +/*****************************************************************************/ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,1,9)) +#if (!(RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(7,2)) && \ + !((SLE_VERSION_CODE == SLE_VERSION(11,3,0)) && \ + (SLE_LOCALVERSION_CODE >= SLE_LOCALVERSION(0,47,71))) && \ + !((SLE_VERSION_CODE == SLE_VERSION(11,4,0)) && \ + (SLE_LOCALVERSION_CODE >= SLE_LOCALVERSION(65,0,0))) && \ + !(SLE_VERSION_CODE >= SLE_VERSION(12,1,0))) +static inline bool page_is_pfmemalloc(struct page __maybe_unused *page) +{ +#ifdef HAVE_STRUCT_PAGE_PFMEMALLOC + return page->pfmemalloc; +#else + return false; +#endif +} +#endif /* !RHEL7.2+ && !SLES11sp3(3.0.101-0.47.71+ update) && !SLES11sp4(3.0.101-65+ update) & !SLES12sp1+ */ +#else +#undef HAVE_STRUCT_PAGE_PFMEMALLOC +#endif /* 4.1.9 */ + +/*****************************************************************************/ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,2,0)) +#if (!(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,2)) && \ + !(SLE_VERSION_CODE >= SLE_VERSION(12,1,0))) +#define ETHTOOL_RX_FLOW_SPEC_RING 0x00000000FFFFFFFFULL +#define ETHTOOL_RX_FLOW_SPEC_RING_VF 0x000000FF00000000ULL +#define ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF 32 +static inline __u64 ethtool_get_flow_spec_ring(__u64 ring_cookie) +{ + return ETHTOOL_RX_FLOW_SPEC_RING & ring_cookie; +}; + +static inline __u64 ethtool_get_flow_spec_ring_vf(__u64 ring_cookie) +{ + return (ETHTOOL_RX_FLOW_SPEC_RING_VF & ring_cookie) >> + ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF; +}; +#endif /* ! RHEL >= 7.2 && ! SLES >= 12.1 */ +#if (RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,4)) +#define HAVE_NDO_DFLT_BRIDGE_GETLINK_VLAN_SUPPORT +#endif + +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,27)) +#if (!((RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,8) && \ + RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7,0)) || \ + RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,2))) +static inline bool pci_ari_enabled(struct pci_bus *bus) +{ + return bus->self && bus->self->ari_enabled; +} +#if (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,2)) +#define HAVE_VF_STATS +#endif /* (RHEL7.2+) */ +#endif /* !(RHEL6.8+ || RHEL7.2+) */ +#else +static inline bool pci_ari_enabled(struct pci_bus *bus) +{ + return false; +} +#endif /* 2.6.27 */ +#else +#define HAVE_NDO_DFLT_BRIDGE_GETLINK_VLAN_SUPPORT +#define HAVE_VF_STATS +#endif /* 4.2.0 */ + +/*****************************************************************************/ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,3,0)) +#if (!(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,4)) && \ + !(SLE_VERSION_CODE >= SLE_VERSION(12,2,0))) +/** + * _kc_flow_dissector_key_ipv4_addrs: + * @src: source ip address + * @dst: destination ip address + */ +struct _kc_flow_dissector_key_ipv4_addrs { + __be32 src; + __be32 dst; +}; + +/** + * _kc_flow_dissector_key_ipv6_addrs: + * @src: source ip address + * @dst: destination ip address + */ +struct _kc_flow_dissector_key_ipv6_addrs { + struct in6_addr src; + struct in6_addr dst; +}; + +/** + * _kc_flow_dissector_key_addrs: + * @v4addrs: IPv4 addresses + * @v6addrs: IPv6 addresses + */ +struct _kc_flow_dissector_key_addrs { + union { + struct _kc_flow_dissector_key_ipv4_addrs v4addrs; + struct _kc_flow_dissector_key_ipv6_addrs v6addrs; + }; +}; + +/** + * _kc_flow_dissector_key_tp_ports: + * @ports: port numbers of Transport header + * src: source port number + * dst: destination port number + */ +struct _kc_flow_dissector_key_ports { + union { + __be32 ports; + struct { + __be16 src; + __be16 dst; + }; + }; +}; + +/** + * _kc_flow_dissector_key_basic: + * @n_proto: Network header protocol (eg. IPv4/IPv6) + * @ip_proto: Transport header protocol (eg. TCP/UDP) + * @padding: padding for alignment + */ +struct _kc_flow_dissector_key_basic { + __be16 n_proto; + u8 ip_proto; + u8 padding; +}; + +struct _kc_flow_keys { + struct _kc_flow_dissector_key_basic basic; + struct _kc_flow_dissector_key_ports ports; + struct _kc_flow_dissector_key_addrs addrs; +}; + +/* These are all the include files for kernels inside this #ifdef block that + * have any reference to the in kernel definition of struct flow_keys. The + * reason for putting them here is to make 100% sure that these files do not get + * included after re-defining flow_keys to _kc_flow_keys. This is done to + * prevent any possible ABI issues that this structure re-definition could case. + */ +#if ((LINUX_VERSION_CODE >= KERNEL_VERSION(3,3,0) && \ + LINUX_VERSION_CODE < KERNEL_VERSION(4,2,0)) || \ + RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,7) || \ + SLE_VERSION_CODE >= SLE_VERSION(11,4,0)) +#include +#endif /* (>= 3.3.0 && < 4.2.0) || >= RHEL 6.7 || >= SLE 11.4 */ +#if (LINUX_VERSION_CODE == KERNEL_VERSION(4,2,0)) +#include +#endif /* 4.2.0 */ +#include +#include +#include +#include + +#define flow_keys _kc_flow_keys +bool +_kc_skb_flow_dissect_flow_keys(const struct sk_buff *skb, + struct flow_keys *flow, + unsigned int __always_unused flags); +#define skb_flow_dissect_flow_keys _kc_skb_flow_dissect_flow_keys +#endif /* ! >= RHEL 7.4 && ! >= SLES 12.2 */ + +#if ((RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,3)) || \ + (SLE_VERSION_CODE >= SLE_VERSION(12,2,0))) +#include +#endif /* >= RHEL7.3 || >= SLE12sp2 */ +#else /* >= 4.3.0 */ +#include +#endif /* 4.3.0 */ + +/*****************************************************************************/ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,4,0)) +#if (RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,3)) +#define HAVE_NDO_SET_VF_TRUST +#endif /* (RHEL_RELEASE >= 7.3) */ +#ifndef CONFIG_64BIT +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,3,0)) +#include /* 32-bit readq/writeq */ +#else /* 3.3.0 => 4.3.x */ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)) +#include +#endif /* 2.6.26 => 3.3.0 */ +#ifndef readq +static inline __u64 readq(const volatile void __iomem *addr) +{ + const volatile u32 __iomem *p = addr; + u32 low, high; + + low = readl(p); + high = readl(p + 1); + + return low + ((u64)high << 32); +} +#define readq readq +#endif + +#ifndef writeq +static inline void writeq(__u64 val, volatile void __iomem *addr) +{ + writel(val, addr); + writel(val >> 32, addr + 4); +} +#define writeq writeq +#endif +#endif /* < 3.3.0 */ +#endif /* !CONFIG_64BIT */ +#else /* < 4.4.0 */ +#define HAVE_NDO_SET_VF_TRUST + +#ifndef CONFIG_64BIT +#include /* 32-bit readq/writeq */ +#endif /* !CONFIG_64BIT */ +#endif /* 4.4.0 */ + +/*****************************************************************************/ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,5,0)) +/* protect against a likely backport */ +#ifndef NETIF_F_CSUM_MASK +#define NETIF_F_CSUM_MASK NETIF_F_ALL_CSUM +#endif /* NETIF_F_CSUM_MASK */ +#if (!(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,3))) +#define eth_platform_get_mac_address _kc_eth_platform_get_mac_address +int _kc_eth_platform_get_mac_address(struct device *dev __maybe_unused, + u8 *mac_addr __maybe_unused); +#endif /* !(RHEL_RELEASE >= 7.3) */ +#else /* 4.5.0 */ +#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,8,0) ) +#define HAVE_GENEVE_RX_OFFLOAD +#if !defined(HAVE_UDP_ENC_TUNNEL) && IS_ENABLED(CONFIG_GENEVE) +#define HAVE_UDP_ENC_TUNNEL +#endif +#endif /* < 4.8.0 */ +#define HAVE_NETIF_NAPI_ADD_CALLS_NAPI_HASH_ADD +#define HAVE_NETDEV_UPPER_INFO +#endif /* 4.5.0 */ + +/*****************************************************************************/ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)) +#if !(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(7,3)) +static inline unsigned char *skb_checksum_start(const struct sk_buff *skb) +{ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,22)) + return skb->head + skb->csum_start; +#else /* < 2.6.22 */ + return skb_transport_header(skb); +#endif +} +#endif + +#if !(UBUNTU_VERSION_CODE && \ + UBUNTU_VERSION_CODE >= UBUNTU_VERSION(4,4,0,21)) && \ + !(RHEL_RELEASE_CODE && \ + (RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(7,2))) && \ + !(SLE_VERSION_CODE && (SLE_VERSION_CODE >= SLE_VERSION(12,3,0))) +static inline void napi_consume_skb(struct sk_buff *skb, + int __always_unused budget) +{ + dev_consume_skb_any(skb); +} + +#endif /* UBUNTU 4,4,0,21, RHEL 7.2, SLES12 SP3 */ +#if !(SLE_VERSION_CODE && (SLE_VERSION_CODE >= SLE_VERSION(12,3,0))) && \ + !(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,4)) +static inline void csum_replace_by_diff(__sum16 *sum, __wsum diff) +{ + * sum = csum_fold(csum_add(diff, ~csum_unfold(*sum))); +} +#endif +#if !(RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(7,2))) && \ + !(SLE_VERSION_CODE && (SLE_VERSION_CODE > SLE_VERSION(12,3,0))) +static inline void page_ref_inc(struct page *page) +{ + get_page(page); +} +#else +#define HAVE_PAGE_COUNT_BULK_UPDATE +#endif +#ifndef IPV4_USER_FLOW +#define IPV4_USER_FLOW 0x0d /* spec only (usr_ip4_spec) */ +#endif + +#if (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,4)) +#define HAVE_TC_SETUP_CLSFLOWER +#define HAVE_TC_FLOWER_ENC +#endif + +#if ((RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,7)) || \ + (SLE_VERSION_CODE >= SLE_VERSION(12,2,0))) +#define HAVE_TC_SETUP_CLSU32 +#endif + +#if (SLE_VERSION_CODE >= SLE_VERSION(12,2,0)) +#define HAVE_TC_SETUP_CLSFLOWER +#endif + +#else /* >= 4.6.0 */ +#define HAVE_PAGE_COUNT_BULK_UPDATE +#define HAVE_ETHTOOL_FLOW_UNION_IP6_SPEC +#define HAVE_PTP_CROSSTIMESTAMP +#define HAVE_TC_SETUP_CLSFLOWER +#define HAVE_TC_SETUP_CLSU32 +#endif /* 4.6.0 */ + +/*****************************************************************************/ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,7,0)) +#if ((SLE_VERSION_CODE >= SLE_VERSION(12,3,0)) ||\ + (RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,4))) +#define HAVE_NETIF_TRANS_UPDATE +#endif /* SLES12sp3+ || RHEL7.4+ */ +#if ((RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,3)) ||\ + (SLE_VERSION_CODE >= SLE_VERSION(12,3,0))) +#define HAVE_ETHTOOL_25G_BITS +#define HAVE_ETHTOOL_50G_BITS +#define HAVE_ETHTOOL_100G_BITS +#endif /* RHEL7.3+ || SLES12sp3+ */ +#else /* 4.7.0 */ +#define HAVE_NETIF_TRANS_UPDATE +#define HAVE_ETHTOOL_CONVERT_U32_AND_LINK_MODE +#define HAVE_ETHTOOL_25G_BITS +#define HAVE_ETHTOOL_50G_BITS +#define HAVE_ETHTOOL_100G_BITS +#define HAVE_TCF_MIRRED_REDIRECT +#endif /* 4.7.0 */ + +/*****************************************************************************/ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,8,0)) +#if !(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,4)) +enum udp_parsable_tunnel_type { + UDP_TUNNEL_TYPE_VXLAN, + UDP_TUNNEL_TYPE_GENEVE, +}; +struct udp_tunnel_info { + unsigned short type; + sa_family_t sa_family; + __be16 port; +}; +#endif + +#if (RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,5)) +#define HAVE_TCF_EXTS_TO_LIST +#endif + +#if (UBUNTU_VERSION_CODE && UBUNTU_VERSION_CODE < UBUNTU_VERSION(4,8,0,0)) +#define tc_no_actions(_exts) true +#define tc_for_each_action(_a, _exts) while (0) +#endif +#if !(SLE_VERSION_CODE && (SLE_VERSION_CODE >= SLE_VERSION(12,3,0))) &&\ + !(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,4)) +static inline int +#ifdef HAVE_NON_CONST_PCI_DRIVER_NAME +pci_request_io_regions(struct pci_dev *pdev, char *name) +#else +pci_request_io_regions(struct pci_dev *pdev, const char *name) +#endif +{ + return pci_request_selected_regions(pdev, + pci_select_bars(pdev, IORESOURCE_IO), name); +} + +static inline void +pci_release_io_regions(struct pci_dev *pdev) +{ + return pci_release_selected_regions(pdev, + pci_select_bars(pdev, IORESOURCE_IO)); +} + +static inline int +#ifdef HAVE_NON_CONST_PCI_DRIVER_NAME +pci_request_mem_regions(struct pci_dev *pdev, char *name) +#else +pci_request_mem_regions(struct pci_dev *pdev, const char *name) +#endif +{ + return pci_request_selected_regions(pdev, + pci_select_bars(pdev, IORESOURCE_MEM), name); +} + +static inline void +pci_release_mem_regions(struct pci_dev *pdev) +{ + return pci_release_selected_regions(pdev, + pci_select_bars(pdev, IORESOURCE_MEM)); +} +#endif /* !SLE_VERSION(12,3,0) */ +#if ((RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,4)) ||\ + (SLE_VERSION_CODE >= SLE_VERSION(12,3,0))) +#define HAVE_ETHTOOL_NEW_50G_BITS +#endif /* RHEL7.4+ || SLES12sp3+ */ +#else +#define HAVE_UDP_ENC_RX_OFFLOAD +#define HAVE_TCF_EXTS_TO_LIST +#define HAVE_ETHTOOL_NEW_50G_BITS +#endif /* 4.8.0 */ + +/*****************************************************************************/ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,9,0)) +#ifdef HAVE_TC_SETUP_CLSFLOWER +#if (!(RHEL_RELEASE_CODE) && !(SLE_VERSION_CODE) || \ + (SLE_VERSION_CODE && (SLE_VERSION_CODE < SLE_VERSION(12,3,0)))) +#define HAVE_TC_FLOWER_VLAN_IN_TAGS +#endif /* !RHEL_RELEASE_CODE && !SLE_VERSION_CODE || = RHEL_RELEASE_VERSION(7,4)) +#define HAVE_ETHTOOL_NEW_1G_BITS +#define HAVE_ETHTOOL_NEW_10G_BITS +#endif /* RHEL7.4+ */ +#if (!(SLE_VERSION_CODE) && !(RHEL_RELEASE_CODE)) || \ + SLE_VERSION_CODE && (SLE_VERSION_CODE <= SLE_VERSION(12,3,0)) || \ + RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE <= RHEL_RELEASE_VERSION(7,5)) +#define time_is_before_jiffies64(a) time_after64(get_jiffies_64(), a) +#endif /* !SLE_VERSION_CODE && !RHEL_RELEASE_CODE || (SLES <= 12.3.0) || (RHEL <= 7.5) */ +#if (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7,4)) +static inline void bitmap_from_u64(unsigned long *dst, u64 mask) +{ + dst[0] = mask & ULONG_MAX; + + if (sizeof(mask) > sizeof(unsigned long)) + dst[1] = mask >> 32; +} +#endif /* = RHEL_RELEASE_VERSION(7,4)) && \ + !(SLE_VERSION_CODE >= SLE_VERSION(12,3,0)) && \ + !(UBUNTU_VERSION_CODE >= UBUNTU_VERSION(4,13,0,16))) +static inline bool eth_type_vlan(__be16 ethertype) +{ + switch (ethertype) { + case htons(ETH_P_8021Q): +#ifdef ETH_P_8021AD + case htons(ETH_P_8021AD): +#endif + return true; + default: + return false; + } +} +#endif /* Linux < 4.9 || RHEL < 7.4 || SLES < 12.3 || Ubuntu < 4.3.0-16 */ +#else /* >=4.9 */ +#define HAVE_FLOW_DISSECTOR_KEY_VLAN_PRIO +#define HAVE_ETHTOOL_NEW_1G_BITS +#define HAVE_ETHTOOL_NEW_10G_BITS +#endif /* KERNEL_VERSION(4.9.0) */ + +/*****************************************************************************/ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,10,0)) +/* SLES 12.3 and RHEL 7.5 backported this interface */ +#if (!SLE_VERSION_CODE && !RHEL_RELEASE_CODE) || \ + (SLE_VERSION_CODE && (SLE_VERSION_CODE < SLE_VERSION(12,3,0))) || \ + (RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7,5))) +static inline bool _kc_napi_complete_done2(struct napi_struct *napi, + int __always_unused work_done) +{ + /* it was really hard to get napi_complete_done to be safe to call + * recursively without running into our own kcompat, so just use + * napi_complete + */ + napi_complete(napi); + + /* true means that the stack is telling the driver to go-ahead and + * re-enable interrupts + */ + return true; +} + +#ifdef napi_complete_done +#undef napi_complete_done +#endif +#define napi_complete_done _kc_napi_complete_done2 +#endif /* sles and rhel exclusion for < 4.10 */ +#if (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,4)) +#define HAVE_DEV_WALK_API +#define HAVE_ETHTOOL_NEW_2500MB_BITS +#define HAVE_ETHTOOL_5G_BITS +#endif /* RHEL7.4+ */ +#if (SLE_VERSION_CODE && (SLE_VERSION_CODE == SLE_VERSION(12,3,0))) +#define HAVE_STRUCT_DMA_ATTRS +#endif /* (SLES == 12.3.0) */ +#if (SLE_VERSION_CODE && (SLE_VERSION_CODE >= SLE_VERSION(12,3,0))) +#define HAVE_NETDEVICE_MIN_MAX_MTU +#endif /* (SLES >= 12.3.0) */ +#if (RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,5))) +#define HAVE_STRUCT_DMA_ATTRS +#define HAVE_RHEL7_EXTENDED_MIN_MAX_MTU +#define HAVE_NETDEVICE_MIN_MAX_MTU +#endif +#if (!(SLE_VERSION_CODE && (SLE_VERSION_CODE >= SLE_VERSION(12,3,0))) && \ + !(RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,5)))) +#ifndef dma_map_page_attrs +#define dma_map_page_attrs __kc_dma_map_page_attrs +static inline dma_addr_t __kc_dma_map_page_attrs(struct device *dev, + struct page *page, + size_t offset, size_t size, + enum dma_data_direction dir, + unsigned long __always_unused attrs) +{ + return dma_map_page(dev, page, offset, size, dir); +} +#endif + +#ifndef dma_unmap_page_attrs +#define dma_unmap_page_attrs __kc_dma_unmap_page_attrs +static inline void __kc_dma_unmap_page_attrs(struct device *dev, + dma_addr_t addr, size_t size, + enum dma_data_direction dir, + unsigned long __always_unused attrs) +{ + dma_unmap_page(dev, addr, size, dir); +} +#endif + +static inline void __page_frag_cache_drain(struct page *page, + unsigned int count) +{ +#ifdef HAVE_PAGE_COUNT_BULK_UPDATE + if (!page_ref_sub_and_test(page, count)) + return; + + init_page_count(page); +#else + BUG_ON(count > 1); + if (!count) + return; +#endif + __free_pages(page, compound_order(page)); +} +#endif /* !SLE_VERSION(12,3,0) && !RHEL_VERSION(7,5) */ +#if ((SLE_VERSION_CODE && (SLE_VERSION_CODE > SLE_VERSION(12,3,0))) ||\ + (RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,5))) +#define HAVE_SWIOTLB_SKIP_CPU_SYNC +#endif + +#if ((SLE_VERSION_CODE && (SLE_VERSION_CODE < SLE_VERSION(15,0,0))) ||\ + (RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE <= RHEL_RELEASE_VERSION(7,4)))) +#define page_frag_free __free_page_frag +#endif +#ifndef ETH_MIN_MTU +#define ETH_MIN_MTU 68 +#endif /* ETH_MIN_MTU */ +#else /* >= 4.10 */ +#define HAVE_TC_FLOWER_ENC +#define HAVE_NETDEVICE_MIN_MAX_MTU +#define HAVE_SWIOTLB_SKIP_CPU_SYNC +#define HAVE_NETDEV_TC_RESETS_XPS +#define HAVE_XPS_QOS_SUPPORT +#define HAVE_DEV_WALK_API +#define HAVE_ETHTOOL_NEW_2500MB_BITS +#define HAVE_ETHTOOL_5G_BITS +/* kernel 4.10 onwards, as part of busy_poll rewrite, new state were added + * which is part of NAPI:state. If NAPI:state=NAPI_STATE_IN_BUSY_POLL, + * it means napi_poll is invoked in busy_poll context + */ +#define HAVE_NAPI_STATE_IN_BUSY_POLL +#define HAVE_TCF_MIRRED_EGRESS_REDIRECT +#endif /* 4.10.0 */ + +/*****************************************************************************/ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,11,0)) +#ifdef CONFIG_NET_RX_BUSY_POLL +#define HAVE_NDO_BUSY_POLL +#endif /* CONFIG_NET_RX_BUSY_POLL */ +#if ((SLE_VERSION_CODE && (SLE_VERSION_CODE >= SLE_VERSION(12,3,0))) || \ + (RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,5)))) +#define HAVE_VOID_NDO_GET_STATS64 +#endif /* (SLES >= 12.3.0) && (RHEL >= 7.5) */ + +static inline void _kc_dev_kfree_skb_irq(struct sk_buff *skb) +{ + if (!skb) + return; + dev_kfree_skb_irq(skb); +} + +#undef dev_kfree_skb_irq +#define dev_kfree_skb_irq _kc_dev_kfree_skb_irq + +static inline void _kc_dev_consume_skb_irq(struct sk_buff *skb) +{ + if (!skb) + return; + dev_consume_skb_irq(skb); +} + +#undef dev_consume_skb_irq +#define dev_consume_skb_irq _kc_dev_consume_skb_irq + +static inline void _kc_dev_kfree_skb_any(struct sk_buff *skb) +{ + if (!skb) + return; + dev_kfree_skb_any(skb); +} + +#undef dev_kfree_skb_any +#define dev_kfree_skb_any _kc_dev_kfree_skb_any + +static inline void _kc_dev_consume_skb_any(struct sk_buff *skb) +{ + if (!skb) + return; + dev_consume_skb_any(skb); +} + +#undef dev_consume_skb_any +#define dev_consume_skb_any _kc_dev_consume_skb_any + +#else /* > 4.11 */ +#define HAVE_VOID_NDO_GET_STATS64 +#define HAVE_VM_OPS_FAULT_NO_VMA +#endif /* 4.11.0 */ + +/*****************************************************************************/ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,12,0)) +#if (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,7) && \ + RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(8,0)) +/* The RHEL 7.7+ NL_SET_ERR_MSG_MOD triggers unused parameter warnings */ +#undef NL_SET_ERR_MSG_MOD +#endif +#ifndef NL_SET_ERR_MSG_MOD +#define NL_SET_ERR_MSG_MOD(extack, msg) \ + do { \ + uninitialized_var(extack); \ + pr_err(KBUILD_MODNAME ": " msg); \ + } while (0) +#endif /* !NL_SET_ERR_MSG_MOD */ +#endif /* 4.12 */ + +/*****************************************************************************/ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,13,0)) +#if ((SLE_VERSION_CODE && (SLE_VERSION_CODE > SLE_VERSION(12,3,0))) || \ + (RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,5))) +#define HAVE_TCF_EXTS_HAS_ACTION +#endif +#define PCI_EXP_LNKCAP_SLS_8_0GB 0x00000003 /* LNKCAP2 SLS Vector bit 2 */ +#if (SLE_VERSION_CODE && (SLE_VERSION_CODE >= SLE_VERSION(12,4,0))) +#define HAVE_PCI_ERROR_HANDLER_RESET_PREPARE +#endif /* SLES >= 12sp4 */ +#if (!(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,5)) && \ + !(SLE_VERSION_CODE >= SLE_VERSION(12,4,0))) +#define UUID_SIZE 16 +typedef struct { + __u8 b[UUID_SIZE]; +} uuid_t; +#define UUID_INIT(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7) \ +((uuid_t) \ +{{ ((a) >> 24) & 0xff, ((a) >> 16) & 0xff, ((a) >> 8) & 0xff, (a) & 0xff, \ + ((b) >> 8) & 0xff, (b) & 0xff, \ + ((c) >> 8) & 0xff, (c) & 0xff, \ + (d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) }}) + +static inline bool uuid_equal(const uuid_t *u1, const uuid_t *u2) +{ + return memcmp(u1, u2, sizeof(uuid_t)) == 0; +} +#else +#define HAVE_METADATA_PORT_INFO +#endif /* !(RHEL >= 7.5) && !(SLES >= 12.4) */ +#else /* > 4.13 */ +#define HAVE_METADATA_PORT_INFO +#define HAVE_HWTSTAMP_FILTER_NTP_ALL +#define HAVE_NDO_SETUP_TC_CHAIN_INDEX +#define HAVE_PCI_ERROR_HANDLER_RESET_PREPARE +#define HAVE_PTP_CLOCK_DO_AUX_WORK +#endif /* 4.13.0 */ + +/*****************************************************************************/ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,14,0)) +#ifdef ETHTOOL_GLINKSETTINGS +#ifndef ethtool_link_ksettings_del_link_mode +#define ethtool_link_ksettings_del_link_mode(ptr, name, mode) \ + __clear_bit(ETHTOOL_LINK_MODE_ ## mode ## _BIT, (ptr)->link_modes.name) +#endif +#endif /* ETHTOOL_GLINKSETTINGS */ +#if (SLE_VERSION_CODE && (SLE_VERSION_CODE >= SLE_VERSION(12,4,0))) +#define HAVE_NDO_SETUP_TC_REMOVE_TC_TO_NETDEV +#endif + +#if (RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,5))) +#define HAVE_NDO_SETUP_TC_REMOVE_TC_TO_NETDEV +#define HAVE_RHEL7_NETDEV_OPS_EXT_NDO_SETUP_TC +#endif + +#define TIMER_DATA_TYPE unsigned long +#define TIMER_FUNC_TYPE void (*)(TIMER_DATA_TYPE) + +#define timer_setup(timer, callback, flags) \ + __setup_timer((timer), (TIMER_FUNC_TYPE)(callback), \ + (TIMER_DATA_TYPE)(timer), (flags)) + +#define from_timer(var, callback_timer, timer_fieldname) \ + container_of(callback_timer, typeof(*var), timer_fieldname) + +#ifndef xdp_do_flush_map +#define xdp_do_flush_map() do {} while (0) +#endif +struct _kc_xdp_buff { + void *data; + void *data_end; + void *data_hard_start; +}; +#define xdp_buff _kc_xdp_buff +struct _kc_bpf_prog { +}; +#define bpf_prog _kc_bpf_prog +#ifndef DIV_ROUND_DOWN_ULL +#define DIV_ROUND_DOWN_ULL(ll, d) \ + ({ unsigned long long _tmp = (ll); do_div(_tmp, d); _tmp; }) +#endif /* DIV_ROUND_DOWN_ULL */ +#else /* > 4.14 */ +#define HAVE_XDP_SUPPORT +#define HAVE_NDO_SETUP_TC_REMOVE_TC_TO_NETDEV +#define HAVE_TCF_EXTS_HAS_ACTION +#endif /* 4.14.0 */ + +/*****************************************************************************/ +#ifndef ETHTOOL_GLINKSETTINGS + +#define __ETHTOOL_LINK_MODE_MASK_NBITS 32 +#define ETHTOOL_LINK_MASK_SIZE BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS) + +/** + * struct ethtool_link_ksettings + * @link_modes: supported and advertising, single item arrays + * @link_modes.supported: bitmask of supported link speeds + * @link_modes.advertising: bitmask of currently advertised speeds + * @base: base link details + * @base.speed: current link speed + * @base.port: current port type + * @base.duplex: current duplex mode + * @base.autoneg: current autonegotiation settings + * + * This struct and the following macros provide a way to support the old + * ethtool get/set_settings API on older kernels, but in the style of the new + * GLINKSETTINGS API. In this way, the same code can be used to support both + * APIs as seemlessly as possible. + * + * It should be noted the old API only has support up to the first 32 bits. + */ +struct ethtool_link_ksettings { + struct { + u32 speed; + u8 port; + u8 duplex; + u8 autoneg; + } base; + struct { + unsigned long supported[ETHTOOL_LINK_MASK_SIZE]; + unsigned long advertising[ETHTOOL_LINK_MASK_SIZE]; + } link_modes; +}; + +#define ETHTOOL_LINK_NAME_advertising(mode) ADVERTISED_ ## mode +#define ETHTOOL_LINK_NAME_supported(mode) SUPPORTED_ ## mode +#define ETHTOOL_LINK_NAME(name) ETHTOOL_LINK_NAME_ ## name +#define ETHTOOL_LINK_CONVERT(name, mode) ETHTOOL_LINK_NAME(name)(mode) + +/** + * ethtool_link_ksettings_zero_link_mode + * @ptr: ptr to ksettings struct + * @name: supported or advertising + */ +#define ethtool_link_ksettings_zero_link_mode(ptr, name)\ + (*((ptr)->link_modes.name) = 0x0) + +/** + * ethtool_link_ksettings_add_link_mode + * @ptr: ptr to ksettings struct + * @name: supported or advertising + * @mode: link mode to add + */ +#define ethtool_link_ksettings_add_link_mode(ptr, name, mode)\ + (*((ptr)->link_modes.name) |= (typeof(*((ptr)->link_modes.name)))ETHTOOL_LINK_CONVERT(name, mode)) + +/** + * ethtool_link_ksettings_del_link_mode + * @ptr: ptr to ksettings struct + * @name: supported or advertising + * @mode: link mode to delete + */ +#define ethtool_link_ksettings_del_link_mode(ptr, name, mode)\ + (*((ptr)->link_modes.name) &= ~(typeof(*((ptr)->link_modes.name)))ETHTOOL_LINK_CONVERT(name, mode)) + +/** + * ethtool_link_ksettings_test_link_mode + * @ptr: ptr to ksettings struct + * @name: supported or advertising + * @mode: link mode to add + */ +#define ethtool_link_ksettings_test_link_mode(ptr, name, mode)\ + (!!(*((ptr)->link_modes.name) & ETHTOOL_LINK_CONVERT(name, mode))) + +/** + * _kc_ethtool_ksettings_to_cmd - Convert ethtool_link_ksettings to ethtool_cmd + * @ks: ethtool_link_ksettings struct + * @cmd: ethtool_cmd struct + * + * Convert an ethtool_link_ksettings structure into the older ethtool_cmd + * structure. We provide this in kcompat.h so that drivers can easily + * implement the older .{get|set}_settings as wrappers around the new api. + * Hence, we keep it prefixed with _kc_ to make it clear this isn't actually + * a real function in the kernel. + */ +static inline void +_kc_ethtool_ksettings_to_cmd(struct ethtool_link_ksettings *ks, + struct ethtool_cmd *cmd) +{ + cmd->supported = (u32)ks->link_modes.supported[0]; + cmd->advertising = (u32)ks->link_modes.advertising[0]; + ethtool_cmd_speed_set(cmd, ks->base.speed); + cmd->duplex = ks->base.duplex; + cmd->autoneg = ks->base.autoneg; + cmd->port = ks->base.port; +} + +#endif /* !ETHTOOL_GLINKSETTINGS */ + +/*****************************************************************************/ +#if ((LINUX_VERSION_CODE < KERNEL_VERSION(4,14,0)) || \ + (SLE_VERSION_CODE && (SLE_VERSION_CODE <= SLE_VERSION(12,3,0))) || \ + (RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE <= RHEL_RELEASE_VERSION(7,5)))) +#define phy_speed_to_str _kc_phy_speed_to_str +const char *_kc_phy_speed_to_str(int speed); +#else /* (LINUX >= 4.14.0) || (SLES > 12.3.0) || (RHEL > 7.5) */ +#include +#endif /* (LINUX < 4.14.0) || (SLES <= 12.3.0) || (RHEL <= 7.5) */ + +/*****************************************************************************/ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,15,0)) +#if ((RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,6))) || \ + (SLE_VERSION_CODE && (SLE_VERSION_CODE >= SLE_VERSION(15,1,0)))) +#define HAVE_TC_CB_AND_SETUP_QDISC_MQPRIO +#define HAVE_TCF_BLOCK +#else /* RHEL >= 7.6 || SLES >= 15.1 */ +#define TC_SETUP_QDISC_MQPRIO TC_SETUP_MQPRIO +#endif /* !(RHEL >= 7.6) && !(SLES >= 15.1) */ +void _kc_ethtool_intersect_link_masks(struct ethtool_link_ksettings *dst, + struct ethtool_link_ksettings *src); +#define ethtool_intersect_link_masks _kc_ethtool_intersect_link_masks +#else /* >= 4.15 */ +#define HAVE_NDO_BPF +#define HAVE_XDP_BUFF_DATA_META +#define HAVE_TC_CB_AND_SETUP_QDISC_MQPRIO +#define HAVE_TCF_BLOCK +#endif /* 4.15.0 */ + +/*****************************************************************************/ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,16,0)) +#if (!(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,7)) && \ + !(SLE_VERSION_CODE >= SLE_VERSION(12,4,0) && \ + SLE_VERSION_CODE < SLE_VERSION(15,0,0)) && \ + !(SLE_VERSION_CODE >= SLE_VERSION(15,1,0))) +/* The return value of the strscpy() and strlcpy() functions is different. + * This could be potentially hazard for the future. + * To avoid this the void result is forced. + * So it is not possible use this function with the return value. + * Return value is required in kernel 4.3 through 4.15 + */ +#define strscpy(...) (void)(strlcpy(__VA_ARGS__)) +#endif /* !RHEL >= 7.7 && !SLES12sp4+ && !SLES15sp1+ */ + +#define pci_printk(level, pdev, fmt, arg...) \ + dev_printk(level, &(pdev)->dev, fmt, ##arg) +#define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg) +#define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg) +#define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg) +#define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg) +#define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg) +#define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg) +#define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg) +#define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg) + +#ifndef array_index_nospec +static inline unsigned long _kc_array_index_mask_nospec(unsigned long index, + unsigned long size) +{ + /* + * Always calculate and emit the mask even if the compiler + * thinks the mask is not needed. The compiler does not take + * into account the value of @index under speculation. + */ + OPTIMIZER_HIDE_VAR(index); + return ~(long)(index | (size - 1UL - index)) >> (BITS_PER_LONG - 1); +} + +#define array_index_nospec(index, size) \ +({ \ + typeof(index) _i = (index); \ + typeof(size) _s = (size); \ + unsigned long _mask = _kc_array_index_mask_nospec(_i, _s); \ + \ + BUILD_BUG_ON(sizeof(_i) > sizeof(long)); \ + BUILD_BUG_ON(sizeof(_s) > sizeof(long)); \ + \ + (typeof(_i)) (_i & _mask); \ +}) +#endif /* array_index_nospec */ +#if (!(RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,6))) && \ + !(SLE_VERSION_CODE && (SLE_VERSION_CODE >= SLE_VERSION(15,1,0)))) +#ifdef HAVE_TC_CB_AND_SETUP_QDISC_MQPRIO +#include +static inline bool +tc_cls_can_offload_and_chain0(const struct net_device *dev, + struct tc_cls_common_offload *common) +{ + if (!tc_can_offload(dev)) + return false; + if (common->chain_index) + return false; + + return true; +} +#endif /* HAVE_TC_CB_AND_SETUP_QDISC_MQPRIO */ +#endif /* !(RHEL >= 7.6) && !(SLES >= 15.1) */ +#ifndef sizeof_field +#define sizeof_field(TYPE, MEMBER) (sizeof((((TYPE *)0)->MEMBER))) +#endif /* sizeof_field */ +#if !(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8,0)) && \ + !(SLE_VERSION_CODE >= SLE_VERSION(12,5,0) && \ + SLE_VERSION_CODE < SLE_VERSION(15,0,0) || \ + SLE_VERSION_CODE >= SLE_VERSION(15,1,0)) +/* + * Copy bitmap and clear tail bits in last word. + */ +static inline void +bitmap_copy_clear_tail(unsigned long *dst, const unsigned long *src, unsigned int nbits) +{ + bitmap_copy(dst, src, nbits); + if (nbits % BITS_PER_LONG) + dst[nbits / BITS_PER_LONG] &= BITMAP_LAST_WORD_MASK(nbits); +} + +/* + * On 32-bit systems bitmaps are represented as u32 arrays internally, and + * therefore conversion is not needed when copying data from/to arrays of u32. + */ +#if BITS_PER_LONG == 64 +void bitmap_from_arr32(unsigned long *bitmap, const u32 *buf, unsigned int nbits); +#else +#define bitmap_from_arr32(bitmap, buf, nbits) \ + bitmap_copy_clear_tail((unsigned long *) (bitmap), \ + (const unsigned long *) (buf), (nbits)) +#endif /* BITS_PER_LONG == 64 */ +#endif /* !(RHEL >= 8.0) && !(SLES >= 12.5 && SLES < 15.0 || SLES >= 15.1) */ +#else /* >= 4.16 */ +#include +#define HAVE_XDP_BUFF_RXQ +#define HAVE_TC_FLOWER_OFFLOAD_COMMON_EXTACK +#define HAVE_TCF_MIRRED_DEV +#define HAVE_VF_STATS_DROPPED +#endif /* 4.16.0 */ + +/*****************************************************************************/ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,17,0)) +#include +#include +#define PCIE_SPEED_16_0GT 0x17 +#define PCI_EXP_LNKCAP_SLS_16_0GB 0x00000004 /* LNKCAP2 SLS Vector bit 3 */ +#define PCI_EXP_LNKSTA_CLS_16_0GB 0x0004 /* Current Link Speed 16.0GT/s */ +#define PCI_EXP_LNKCAP2_SLS_16_0GB 0x00000010 /* Supported Speed 16GT/s */ +void _kc_pcie_print_link_status(struct pci_dev *dev); +#define pcie_print_link_status _kc_pcie_print_link_status +#else /* >= 4.17.0 */ +#define HAVE_XDP_BUFF_IN_XDP_H +#endif /* 4.17.0 */ + +/*****************************************************************************/ +#if IS_ENABLED(CONFIG_NET_DEVLINK) && \ + (LINUX_VERSION_CODE < KERNEL_VERSION(5,9,0)) +#include +#if ((LINUX_VERSION_CODE < KERNEL_VERSION(4,18,0)) && \ + (SLE_VERSION_CODE < SLE_VERSION(15,1,0)) && \ + (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7,7))) +enum devlink_port_flavour { + DEVLINK_PORT_FLAVOUR_PHYSICAL, + DEVLINK_PORT_FLAVOUR_CPU, + DEVLINK_PORT_FLAVOUR_DSA, + DEVLINK_PORT_FLAVOUR_PCI_PF, + DEVLINK_PORT_FLAVOUR_PCI_VF, +}; +#endif /* <4.18.0 && +#ifndef macvlan_supports_dest_filter +#define macvlan_supports_dest_filter _kc_macvlan_supports_dest_filter +static inline bool _kc_macvlan_supports_dest_filter(struct net_device *dev) +{ + struct macvlan_dev *macvlan = netdev_priv(dev); + + return macvlan->mode == MACVLAN_MODE_PRIVATE || + macvlan->mode == MACVLAN_MODE_VEPA || + macvlan->mode == MACVLAN_MODE_BRIDGE; +} +#endif + +#if (!SLE_VERSION_CODE || (SLE_VERSION_CODE < SLE_VERSION(15,1,0))) +#ifndef macvlan_accel_priv +#define macvlan_accel_priv _kc_macvlan_accel_priv +static inline void *_kc_macvlan_accel_priv(struct net_device *dev) +{ + struct macvlan_dev *macvlan = netdev_priv(dev); + + return macvlan->fwd_priv; +} +#endif + +#ifndef macvlan_release_l2fw_offload +#define macvlan_release_l2fw_offload _kc_macvlan_release_l2fw_offload +static inline int _kc_macvlan_release_l2fw_offload(struct net_device *dev) +{ + struct macvlan_dev *macvlan = netdev_priv(dev); + + macvlan->fwd_priv = NULL; + return dev_uc_add(macvlan->lowerdev, dev->dev_addr); +} +#endif +#endif /* !SLES || SLES < 15.1 */ +#endif /* NETIF_F_HW_L2FW_DOFFLOAD */ +#include "kcompat_overflow.h" + +#if (SLE_VERSION_CODE < SLE_VERSION(15,1,0)) +#define firmware_request_nowarn request_firmware_direct + +#if (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7,7)) +#if IS_ENABLED(CONFIG_NET_DEVLINK) && !defined(devlink_port_attrs_set) +static inline void +_kc_devlink_port_attrs_set(struct devlink_port *devlink_port, + struct _kc_devlink_port_attrs *attrs) +{ + if (attrs->split) + devlink_port_split_set(devlink_port, attrs->phys.port_number); +} + +#define devlink_port_attrs_set _kc_devlink_port_attrs_set +#endif /* CONFIG_NET_DEVLINK && !devlink_port_attrs_set */ +#endif /* +#include +#define HAVE_XDP_FRAME_STRUCT +#define HAVE_XDP_SOCK +#define HAVE_NDO_XDP_XMIT_BULK_AND_FLAGS +#define NO_NDO_XDP_FLUSH +#define HAVE_AF_XDP_SUPPORT +#endif /* 4.18.0 */ + +/*****************************************************************************/ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,19,0)) +#if (RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8,0)) && \ + (RHEL_RELEASE_CODE <= RHEL_RELEASE_VERSION(8,2))) +#define HAVE_DEVLINK_REGIONS +#endif /* RHEL >= 8.0 && RHEL <= 8.2 */ +#define bitmap_alloc(nbits, flags) \ + kmalloc_array(BITS_TO_LONGS(nbits), sizeof(unsigned long), flags) +#define bitmap_zalloc(nbits, flags) bitmap_alloc(nbits, ((flags) | __GFP_ZERO)) +#define bitmap_free(bitmap) kfree(bitmap) +#ifdef ETHTOOL_GLINKSETTINGS +#define ethtool_ks_clear(ptr, name) \ + ethtool_link_ksettings_zero_link_mode(ptr, name) +#define ethtool_ks_add_mode(ptr, name, mode) \ + ethtool_link_ksettings_add_link_mode(ptr, name, mode) +#define ethtool_ks_del_mode(ptr, name, mode) \ + ethtool_link_ksettings_del_link_mode(ptr, name, mode) +#define ethtool_ks_test(ptr, name, mode) \ + ethtool_link_ksettings_test_link_mode(ptr, name, mode) +#endif /* ETHTOOL_GLINKSETTINGS */ +#define HAVE_NETPOLL_CONTROLLER +#define REQUIRE_PCI_CLEANUP_AER_ERROR_STATUS +#if (SLE_VERSION_CODE && (SLE_VERSION_CODE >= SLE_VERSION(15,1,0))) +#define HAVE_TCF_MIRRED_DEV +#define HAVE_NDO_SELECT_QUEUE_SB_DEV +#define HAVE_TCF_BLOCK_CB_REGISTER_EXTACK +#endif +#if ((RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8,0)) ||\ + (SLE_VERSION_CODE >= SLE_VERSION(15,1,0))) +#define HAVE_TCF_EXTS_FOR_EACH_ACTION +#undef HAVE_TCF_EXTS_TO_LIST +#endif /* RHEL8.0+ */ + +static inline void __kc_metadata_dst_free(void *md_dst) +{ + kfree(md_dst); +} + +#define metadata_dst_free(md_dst) __kc_metadata_dst_free(md_dst) +#elif (LINUX_VERSION_CODE > KERNEL_VERSION(4,19,0)) +#define HAVE_TCF_BLOCK_CB_REGISTER_EXTACK +#define NO_NETDEV_BPF_PROG_ATTACHED +#define HAVE_NDO_SELECT_QUEUE_SB_DEV +#define HAVE_NETDEV_SB_DEV +#undef HAVE_TCF_EXTS_TO_LIST +#define HAVE_TCF_EXTS_FOR_EACH_ACTION +#define HAVE_TCF_VLAN_TPID +#define HAVE_RHASHTABLE_TYPES +#define HAVE_DEVLINK_REGIONS +#define HAVE_DEVLINK_PARAMS +#define HAVE_UDP_TUNNEL_OPS +#define HAVE_IOPOLL_OPS +#define HAVE_DEV_PRINTK_OPS +#else /* = 4.19.0 */ +static inline int __sysfs_emit(char *buf, const char *fmt, ...) +{ + int ret; + va_list args; + + if (WARN(!buf || offset_in_page(buf), + "invalid sysfs_emit: buf:%p\n", buf)) + return 0; + + va_start(args, fmt); + ret = vscnprintf(buf, PAGE_SIZE, fmt, args); + va_end(args); + return ret; +} +#define sysfs_emit __sysfs_emit +#endif /* 4.19.0 */ + +/*****************************************************************************/ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,20,0)) +#define HAVE_XDP_UMEM_PROPS +#ifdef HAVE_AF_XDP_SUPPORT +#ifndef napi_if_scheduled_mark_missed +static inline bool __kc_napi_if_scheduled_mark_missed(struct napi_struct *n) +{ + unsigned long val, new; + + do { + val = READ_ONCE(n->state); + if (val & NAPIF_STATE_DISABLE) + return true; + + if (!(val & NAPIF_STATE_SCHED)) + return false; + + new = val | NAPIF_STATE_MISSED; + } while (cmpxchg(&n->state, val, new) != val); + + return true; +} + +#define napi_if_scheduled_mark_missed __kc_napi_if_scheduled_mark_missed +#endif /* !napi_if_scheduled_mark_missed */ +#endif /* HAVE_AF_XDP_SUPPORT */ +#if (RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8,0))) +#define HAVE_DEVLINK_ESWITCH_OPS_EXTACK +#endif /* RHEL >= 8.0 */ +#if ((SLE_VERSION_CODE >= SLE_VERSION(12,5,0) && \ + SLE_VERSION_CODE < SLE_VERSION(15,0,0)) || \ + (SLE_VERSION_CODE >= SLE_VERSION(15,1,0))) +#define HAVE_DEVLINK_ESWITCH_OPS_EXTACK +#endif /* SLE == 12sp5 || SLE >= 15sp1 */ +#else /* >= 4.20.0 */ +#define HAVE_DEVLINK_ESWITCH_OPS_EXTACK +#define HAVE_AF_XDP_ZC_SUPPORT +#define HAVE_VXLAN_TYPE +#define HAVE_ETF_SUPPORT /* Earliest TxTime First */ +#endif /* 4.20.0 */ + +/*****************************************************************************/ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5,0,0)) +#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(8,0))) +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,12,0)) +#define NETLINK_MAX_COOKIE_LEN 20 +struct netlink_ext_ack { + const char *_msg; + const struct nlattr *bad_attr; + u8 cookie[NETLINK_MAX_COOKIE_LEN]; + u8 cookie_len; +}; + +#endif /* < 4.12 */ +static inline int _kc_dev_open(struct net_device *netdev, + struct netlink_ext_ack __always_unused *extack) +{ + return dev_open(netdev); +} + +#define dev_open _kc_dev_open + +static inline int +_kc_dev_change_flags(struct net_device *netdev, unsigned int flags, + struct netlink_ext_ack __always_unused *extack) +{ + return dev_change_flags(netdev, flags); +} + +#define dev_change_flags _kc_dev_change_flags +#endif /* !(RHEL_RELEASE_CODE && RHEL > RHEL(8,0)) */ +#if (RHEL_RELEASE_CODE && \ + (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,7) && \ + RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(8,0)) || \ + (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8,1))) +#define HAVE_PTP_SYS_OFFSET_EXTENDED_IOCTL +#else /* RHEL >= 7.7 && RHEL < 8.0 || RHEL >= 8.1 */ +struct ptp_system_timestamp { + struct timespec64 pre_ts; + struct timespec64 post_ts; +}; + +static inline void +ptp_read_system_prets(struct ptp_system_timestamp __always_unused *sts) +{ + ; +} + +static inline void +ptp_read_system_postts(struct ptp_system_timestamp __always_unused *sts) +{ + ; +} +#endif /* !(RHEL >= 7.7 && RHEL != 8.0) */ +#if (RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8,1))) +#define HAVE_NDO_BRIDGE_SETLINK_EXTACK +#endif /* RHEL 8.1 */ +#if (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8,2)) +#define HAVE_TC_INDIR_BLOCK +#endif /* RHEL 8.2 */ +#else /* >= 5.0.0 */ +#define HAVE_PTP_SYS_OFFSET_EXTENDED_IOCTL +#define HAVE_NDO_BRIDGE_SETLINK_EXTACK +#define HAVE_DMA_ALLOC_COHERENT_ZEROES_MEM +#define HAVE_GENEVE_TYPE +#define HAVE_TC_INDIR_BLOCK +#endif /* 5.0.0 */ + +/*****************************************************************************/ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5,1,0)) +#if (RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8,1))) +#define HAVE_TC_FLOW_RULE_INFRASTRUCTURE +#define HAVE_NDO_FDB_ADD_EXTACK +#define HAVE_DEVLINK_INFO_GET +#define HAVE_DEVLINK_FLASH_UPDATE +#else /* RHEL < 8.1 */ +#ifdef HAVE_TC_SETUP_CLSFLOWER +#include + +struct flow_match { + struct flow_dissector *dissector; + void *mask; + void *key; +}; + +struct flow_match_basic { + struct flow_dissector_key_basic *key, *mask; +}; + +struct flow_match_control { + struct flow_dissector_key_control *key, *mask; +}; + +struct flow_match_eth_addrs { + struct flow_dissector_key_eth_addrs *key, *mask; +}; + +#ifdef HAVE_TC_FLOWER_ENC +struct flow_match_enc_keyid { + struct flow_dissector_key_keyid *key, *mask; +}; +#endif + +#ifndef HAVE_TC_FLOWER_VLAN_IN_TAGS +struct flow_match_vlan { + struct flow_dissector_key_vlan *key, *mask; +}; +#endif + +struct flow_match_ipv4_addrs { + struct flow_dissector_key_ipv4_addrs *key, *mask; +}; + +struct flow_match_ipv6_addrs { + struct flow_dissector_key_ipv6_addrs *key, *mask; +}; + +struct flow_match_ports { + struct flow_dissector_key_ports *key, *mask; +}; + +struct flow_rule { + struct flow_match match; +#if 0 + /* In 5.1+ kernels, action is a member of struct flow_rule but is + * not compatible with how we kcompat tc_cls_flower_offload_flow_rule + * below. By not declaring it here, any driver that attempts to use + * action as an element of struct flow_rule will fail to compile + * instead of silently trying to access memory that shouldn't be. + */ + struct flow_action action; +#endif +}; + +void flow_rule_match_basic(const struct flow_rule *rule, + struct flow_match_basic *out); +void flow_rule_match_control(const struct flow_rule *rule, + struct flow_match_control *out); +void flow_rule_match_eth_addrs(const struct flow_rule *rule, + struct flow_match_eth_addrs *out); +#ifndef HAVE_TC_FLOWER_VLAN_IN_TAGS +void flow_rule_match_vlan(const struct flow_rule *rule, + struct flow_match_vlan *out); +#endif +void flow_rule_match_ipv4_addrs(const struct flow_rule *rule, + struct flow_match_ipv4_addrs *out); +void flow_rule_match_ipv6_addrs(const struct flow_rule *rule, + struct flow_match_ipv6_addrs *out); +void flow_rule_match_ports(const struct flow_rule *rule, + struct flow_match_ports *out); +#ifdef HAVE_TC_FLOWER_ENC +void flow_rule_match_enc_ports(const struct flow_rule *rule, + struct flow_match_ports *out); +void flow_rule_match_enc_control(const struct flow_rule *rule, + struct flow_match_control *out); +void flow_rule_match_enc_ipv4_addrs(const struct flow_rule *rule, + struct flow_match_ipv4_addrs *out); +void flow_rule_match_enc_ipv6_addrs(const struct flow_rule *rule, + struct flow_match_ipv6_addrs *out); +void flow_rule_match_enc_keyid(const struct flow_rule *rule, + struct flow_match_enc_keyid *out); +#endif + +static inline struct flow_rule * +tc_cls_flower_offload_flow_rule(struct tc_cls_flower_offload *tc_flow_cmd) +{ + return (struct flow_rule *)&tc_flow_cmd->dissector; +} + +static inline bool flow_rule_match_key(const struct flow_rule *rule, + enum flow_dissector_key_id key) +{ + return dissector_uses_key(rule->match.dissector, key); +} +#endif /* HAVE_TC_SETUP_CLSFLOWER */ + +#endif /* RHEL < 8.1 */ + +#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8,1))) +#define devlink_params_publish(devlink) do { } while (0) +#define devlink_params_unpublish(devlink) do { } while (0) +#endif + +#else /* >= 5.1.0 */ +#define HAVE_NDO_FDB_ADD_EXTACK +#define NO_XDP_QUERY_XSK_UMEM +#define HAVE_AF_XDP_NETDEV_UMEM +#define HAVE_TC_FLOW_RULE_INFRASTRUCTURE +#define HAVE_TC_FLOWER_ENC_IP +#define HAVE_DEVLINK_INFO_GET +#define HAVE_DEVLINK_FLASH_UPDATE +#define HAVE_DEVLINK_PORT_PARAMS +#endif /* 5.1.0 */ + +/*****************************************************************************/ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5,2,0)) +#if (defined HAVE_SKB_XMIT_MORE) && \ +(!(RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8,2)))) +#define netdev_xmit_more() (skb->xmit_more) +#else +#define netdev_xmit_more() (0) +#endif + +#if (!(RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8,2)))) +#ifndef eth_get_headlen +static inline u32 +__kc_eth_get_headlen(const struct net_device __always_unused *dev, void *data, + unsigned int len) +{ + return eth_get_headlen(data, len); +} + +#define eth_get_headlen(dev, data, len) __kc_eth_get_headlen(dev, data, len) +#endif /* !eth_get_headlen */ +#endif /* !RHEL >= 8.2 */ + +#ifndef mmiowb +#ifdef CONFIG_IA64 +#define mmiowb() asm volatile ("mf.a" ::: "memory") +#else +#define mmiowb() +#endif +#endif /* mmiowb */ + +#if (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(8,2)) +#if IS_ENABLED(CONFIG_NET_DEVLINK) && !defined(devlink_port_attrs_set) +static inline void +_kc_devlink_port_attrs_set(struct devlink_port *devlink_port, + struct _kc_devlink_port_attrs *attrs) +{ + devlink_port_attrs_set(devlink_port, attrs->flavour, + attrs->phys.port_number, attrs->split, + attrs->phys.split_subport_number); +} + +#define devlink_port_attrs_set _kc_devlink_port_attrs_set +#endif /* CONFIG_NET_DEVLINK && !devlink_port_attrs_set */ +#endif /* RHEL_RELEASE_VERSION(8,1)) +#define HAVE_NDO_GET_DEVLINK_PORT +#endif /* RHEL > 8.1 */ + +#else /* >= 5.2.0 */ +#define HAVE_NDO_SELECT_QUEUE_FALLBACK_REMOVED +#define SPIN_UNLOCK_IMPLIES_MMIOWB +#define HAVE_NDO_GET_DEVLINK_PORT +#endif /* 5.2.0 */ + +/*****************************************************************************/ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5,3,0)) +#if (!(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8,2))) +#define flow_block_offload tc_block_offload +#define flow_block_command tc_block_command +#define flow_cls_offload tc_cls_flower_offload +#define flow_block_binder_type tcf_block_binder_type +#define flow_cls_common_offload tc_cls_common_offload +#define flow_cls_offload_flow_rule tc_cls_flower_offload_flow_rule +#define FLOW_CLS_REPLACE TC_CLSFLOWER_REPLACE +#define FLOW_CLS_DESTROY TC_CLSFLOWER_DESTROY +#define FLOW_CLS_STATS TC_CLSFLOWER_STATS +#define FLOW_CLS_TMPLT_CREATE TC_CLSFLOWER_TMPLT_CREATE +#define FLOW_CLS_TMPLT_DESTROY TC_CLSFLOWER_TMPLT_DESTROY +#define FLOW_BLOCK_BINDER_TYPE_CLSACT_INGRESS \ + TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS +#define FLOW_BLOCK_BIND TC_BLOCK_BIND +#define FLOW_BLOCK_UNBIND TC_BLOCK_UNBIND + +#ifdef HAVE_TC_CB_AND_SETUP_QDISC_MQPRIO +#include + +int _kc_flow_block_cb_setup_simple(struct flow_block_offload *f, + struct list_head *driver_list, + tc_setup_cb_t *cb, + void *cb_ident, void *cb_priv, + bool ingress_only); + +#define flow_block_cb_setup_simple(f, driver_list, cb, cb_ident, cb_priv, \ + ingress_only) \ + _kc_flow_block_cb_setup_simple(f, driver_list, cb, cb_ident, cb_priv, \ + ingress_only) +#endif /* HAVE_TC_CB_AND_SETUP_QDISC_MQPRIO */ +#else /* RHEL >= 8.2 */ +#define HAVE_FLOW_BLOCK_API +#define HAVE_DEVLINK_PORT_ATTR_PCI_VF +#endif /* RHEL >= 8.2 */ + +#ifndef ETH_P_LLDP +#define ETH_P_LLDP 0x88CC +#endif /* !ETH_P_LLDP */ + +#if (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(8,2)) +#if IS_ENABLED(CONFIG_NET_DEVLINK) +static inline void +devlink_flash_update_begin_notify(struct devlink __always_unused *devlink) +{ +} + +static inline void +devlink_flash_update_end_notify(struct devlink __always_unused *devlink) +{ +} + +static inline void +devlink_flash_update_status_notify(struct devlink __always_unused *devlink, + const char __always_unused *status_msg, + const char __always_unused *component, + unsigned long __always_unused done, + unsigned long __always_unused total) +{ +} +#endif /* CONFIG_NET_DEVLINK */ +#endif /* = 5.3.0 */ +#define XSK_UMEM_RETURNS_XDP_DESC +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5,8,0)) +#define HAVE_XSK_UMEM_HAS_ADDRS +#endif /* < 5.8.0*/ +#define HAVE_FLOW_BLOCK_API +#define HAVE_DEVLINK_PORT_ATTR_PCI_VF +#if IS_ENABLED(CONFIG_DIMLIB) +#define HAVE_CONFIG_DIMLIB +#endif +#endif /* 5.3.0 */ + +/*****************************************************************************/ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5,4,0)) +#if (!(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8,2)) && \ + !(SLE_VERSION_CODE >= SLE_VERSION(15,2,0))) +static inline unsigned int skb_frag_off(const skb_frag_t *frag) +{ + return frag->page_offset; +} + +static inline void skb_frag_off_add(skb_frag_t *frag, int delta) +{ + frag->page_offset += delta; +} +#define __flow_indr_block_cb_register __tc_indr_block_cb_register +#define __flow_indr_block_cb_unregister __tc_indr_block_cb_unregister +#endif /* !(RHEL >= 8.2) && !(SLES >= 15sp2) */ +#if (SLE_VERSION_CODE >= SLE_VERSION(15,2,0)) +#define HAVE_NDO_XSK_WAKEUP +#endif /* SLES15sp2 */ +#else /* >= 5.4.0 */ +#define HAVE_NDO_XSK_WAKEUP +#endif /* 5.4.0 */ + +/*****************************************************************************/ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5,5,0)) +static inline unsigned long _kc_bitmap_get_value8(const unsigned long *map, + unsigned long start) +{ + const size_t index = BIT_WORD(start); + const unsigned long offset = start % BITS_PER_LONG; + + return (map[index] >> offset) & 0xFF; +} +#define bitmap_get_value8 _kc_bitmap_get_value8 + +static inline void _kc_bitmap_set_value8(unsigned long *map, + unsigned long value, + unsigned long start) +{ + const size_t index = BIT_WORD(start); + const unsigned long offset = start % BITS_PER_LONG; + + map[index] &= ~(0xFFUL << offset); + map[index] |= value << offset; +} +#define bitmap_set_value8 _kc_bitmap_set_value8 + +#endif /* 5.5.0 */ + +/*****************************************************************************/ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5,6,0)) +#ifdef HAVE_AF_XDP_SUPPORT +#define xsk_umem_release_addr xsk_umem_discard_addr +#define xsk_umem_release_addr_rq xsk_umem_discard_addr_rq +#endif /* HAVE_AF_XDP_SUPPORT */ +#if (RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8,3))) +#define HAVE_TX_TIMEOUT_TXQUEUE +#endif +#else /* >= 5.6.0 */ +#define HAVE_TX_TIMEOUT_TXQUEUE +#endif /* 5.6.0 */ + +/*****************************************************************************/ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5,7,0)) +u64 _kc_pci_get_dsn(struct pci_dev *dev); +#define pci_get_dsn(dev) _kc_pci_get_dsn(dev) +#if !(SLE_VERSION_CODE > SLE_VERSION(15,2,0)) && \ + !((LINUX_VERSION_CODE == KERNEL_VERSION(5,3,18)) && \ + (SLE_LOCALVERSION_CODE >= KERNEL_VERSION(14,0,0))) && \ + !(RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8,3))) +#define pci_aer_clear_nonfatal_status pci_cleanup_aer_uncorrect_error_status +#endif + +#define cpu_latency_qos_update_request pm_qos_update_request +#define cpu_latency_qos_add_request(arg1, arg2) pm_qos_add_request(arg1, PM_QOS_CPU_DMA_LATENCY, arg2) +#define cpu_latency_qos_remove_request pm_qos_remove_request + +#ifndef DEVLINK_INFO_VERSION_GENERIC_FW_BUNDLE_ID +#define DEVLINK_INFO_VERSION_GENERIC_FW_BUNDLE_ID "fw.bundle_id" +#endif + +#ifdef HAVE_DEVLINK_REGIONS +#if IS_ENABLED(CONFIG_NET_DEVLINK) +struct devlink_region_ops { + const char *name; + void (*destructor)(const void *data); +}; + +#ifndef devlink_region_create +static inline struct devlink_region * +_kc_devlink_region_create(struct devlink *devlink, + const struct devlink_region_ops *ops, + u32 region_max_snapshots, u64 region_size) +{ + return devlink_region_create(devlink, ops->name, region_max_snapshots, + region_size); +} + +#define devlink_region_create _kc_devlink_region_create +#endif /* devlink_region_create */ +#endif /* CONFIG_NET_DEVLINK */ +#define HAVE_DEVLINK_SNAPSHOT_CREATE_DESTRUCTOR +#endif /* HAVE_DEVLINK_REGIONS */ +#else /* >= 5.7.0 */ +#define HAVE_DEVLINK_REGION_OPS_SNAPSHOT +#define HAVE_ETHTOOL_COALESCE_PARAMS_SUPPORT +#endif /* 5.7.0 */ + +/*****************************************************************************/ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5,8,0)) +#if !(RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8,4))) +#define xdp_convert_buff_to_frame convert_to_xdp_frame +#endif /* (RHEL < 8.4) */ +#define flex_array_size(p, member, count) \ + array_size(count, sizeof(*(p)->member) + __must_be_array((p)->member)) +#ifdef HAVE_AF_XDP_ZC_SUPPORT +#ifndef xsk_umem_get_rx_frame_size +static inline u32 _xsk_umem_get_rx_frame_size(struct xdp_umem *umem) +{ + return umem->chunk_size_nohr - XDP_PACKET_HEADROOM; +} + +#define xsk_umem_get_rx_frame_size _xsk_umem_get_rx_frame_size +#endif /* xsk_umem_get_rx_frame_size */ +#endif /* HAVE_AF_XDP_ZC_SUPPORT */ +#else /* >= 5.8.0 */ +#define HAVE_TC_FLOW_INDIR_DEV +#define HAVE_TC_FLOW_INDIR_BLOCK_CLEANUP +#define HAVE_XDP_BUFF_FRAME_SZ +#define HAVE_MEM_TYPE_XSK_BUFF_POOL +#endif /* 5.8.0 */ +#if (RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8,3))) +#define HAVE_TC_FLOW_INDIR_DEV +#endif + +/*****************************************************************************/ +#if (RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8,4))) +#if IS_ENABLED(CONFIG_NET_DEVLINK) && !defined(devlink_port_attrs_set) +#undef devlink_port_attrs +#define devlink_port_attrs_set devlink_port_attrs_set +#endif /* CONFIG_NET_DEVLINK && !devlink_port_attrs_set */ +#endif /* (RHEL >= 8.4) */ + +/*****************************************************************************/ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5,9,0)) +#if IS_ENABLED(CONFIG_NET_DEVLINK) && !defined(devlink_port_attrs_set) +static inline void +_kc_devlink_port_attrs_set(struct devlink_port *devlink_port, + struct _kc_devlink_port_attrs *attrs) +{ + devlink_port_attrs_set(devlink_port, attrs->flavour, + attrs->phys.port_number, attrs->split, + attrs->phys.split_subport_number, + attrs->switch_id.id, attrs->switch_id.id_len); +} + +#define devlink_port_attrs_set _kc_devlink_port_attrs_set +#endif /* CONFIG_NET_DEVLINK && !devlink_port_attrs_set */ +#define HAVE_XDP_QUERY_PROG +#else /* >= 5.9.0 */ +#define HAVE_FLOW_INDIR_BLOCK_QDISC +#define HAVE_UDP_TUNNEL_NIC_INFO +#endif /* 5.9.0 */ + +/*****************************************************************************/ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5,10,0)) +struct devlink_flash_update_params { + const char *file_name; + const char *component; + u32 overwrite_mask; +}; + +#ifndef DEVLINK_FLASH_OVERWRITE_SETTINGS +#define DEVLINK_FLASH_OVERWRITE_SETTINGS BIT(0) +#endif + +#ifndef DEVLINK_FLASH_OVERWRITE_IDENTIFIERS +#define DEVLINK_FLASH_OVERWRITE_IDENTIFIERS BIT(1) +#endif + +#if IS_ENABLED(CONFIG_NET_DEVLINK) +#include +static inline void +devlink_flash_update_timeout_notify(struct devlink *devlink, + const char *status_msg, + const char *component, + unsigned long __always_unused timeout) +{ + devlink_flash_update_status_notify(devlink, status_msg, component, 0, 0); +} +#endif /* CONFIG_NET_DEVLINK */ + +#if !(RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8,4))) +static inline void net_prefetch(void *p) +{ + prefetch(p); +#if L1_CACHE_BYTES < 128 + prefetch((u8 *)p + L1_CACHE_BYTES); +#endif +} +#endif /* (RHEL < 8.4) */ + +#define XDP_SETUP_XSK_POOL XDP_SETUP_XSK_UMEM +#define xsk_get_pool_from_qid xdp_get_umem_from_qid +#define xsk_pool_get_rx_frame_size xsk_umem_get_rx_frame_size +#define xsk_pool_set_rxq_info xsk_buff_set_rxq_info +#define xsk_pool_dma_unmap xsk_buff_dma_unmap +#define xsk_pool_dma_map xsk_buff_dma_map +#define xsk_tx_peek_desc xsk_umem_consume_tx +#define xsk_tx_release xsk_umem_consume_tx_done +#define xsk_tx_completed xsk_umem_complete_tx +#define xsk_uses_need_wakeup xsk_umem_uses_need_wakeup +#ifdef HAVE_MEM_TYPE_XSK_BUFF_POOL +#include +static inline void +_kc_xsk_buff_dma_sync_for_cpu(struct xdp_buff *xdp, + void __always_unused *pool) +{ + xsk_buff_dma_sync_for_cpu(xdp); +} + +#define xsk_buff_dma_sync_for_cpu(xdp, pool) \ + _kc_xsk_buff_dma_sync_for_cpu(xdp, pool) +#endif /* HAVE_MEM_TYPE_XSK_BUFF_POOL */ +#else /* >= 5.10.0 */ +#define HAVE_DEVLINK_REGION_OPS_SNAPSHOT_OPS +#define HAVE_DEVLINK_FLASH_UPDATE_PARAMS +#define HAVE_NETDEV_BPF_XSK_POOL +#endif /* 5.10.0 */ + +/*****************************************************************************/ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5,11,0)) +#ifdef HAVE_XDP_BUFF_RXQ +#include +static inline int +_kc_xdp_rxq_info_reg(struct xdp_rxq_info *xdp_rxq, struct net_device *dev, + u32 queue_index, unsigned int __always_unused napi_id) +{ + return xdp_rxq_info_reg(xdp_rxq, dev, queue_index); +} + +#define xdp_rxq_info_reg(xdp_rxq, dev, queue_index, napi_id) \ + _kc_xdp_rxq_info_reg(xdp_rxq, dev, queue_index, napi_id) +#endif /* HAVE_XDP_BUFF_RXQ */ +#define HAVE_DEVLINK_FLASH_UPDATE_BEGIN_END_NOTIFY +#else /* >= 5.11.0 */ +#define HAVE_DEVLINK_FLASH_UPDATE_PARAMS_FW +#endif /* 5.11.0 */ + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5,13,0)) +#define HAVE_ETHTOOL_GET_MODULE_EEPROM_BY_PAGE +#endif + +#endif /* _KCOMPAT_H_ */ diff --git a/src/net/include/linux/dinghai/kcompat_vfd.h b/src/net/include/linux/dinghai/kcompat_vfd.h new file mode 100644 index 0000000..a0c6c7b --- /dev/null +++ b/src/net/include/linux/dinghai/kcompat_vfd.h @@ -0,0 +1,189 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright(c) 2013 - 2021 Intel Corporation. */ + +#ifndef _KCOMPAT_VFD_H_ +#define _KCOMPAT_VFD_H_ + +#define VFD_PROMISC_OFF 0x00 +#define VFD_PROMISC_UNICAST 0x01 +#define VFD_PROMISC_MULTICAST 0x02 + +#define VFD_LINKSTATE_OFF 0x00 +#define VFD_LINKSTATE_ON 0x01 +#define VFD_LINKSTATE_AUTO 0x02 + +#define VFD_EGRESS_MIRROR_OFF -1 +#define VFD_INGRESS_MIRROR_OFF -1 + +#define VFD_QUEUE_TYPE_RSS 0x00 +#define VFD_QUEUE_TYPE_QOS 0x01 + +#define VFD_NUM_TC 0x8 + +/** + * struct vfd_objects - VF-d kobjects information struct + * @num_vfs: number of VFs allocated + * @sriov_kobj: pointer to the top sriov kobject + * @vf_kobj: array of pointer to each VF's kobjects + */ +struct vfd_objects { + int num_vfs; + struct kobject *sriov_kobj; + struct vfd_vf_obj *vfs; + struct vfd_qos_objects *qos; +}; + +/** + * struct vfd_vf_obj - VF-d VF kobjects information struct + * @vf_kobj: pointer to VF qos kobject + * @vf_qos_kobj: pointer to VF kobject + * @vf_tc_kobj: pointer to VF TC kobjects + */ +struct vfd_vf_obj { + struct kobject *vf_qos_kobj; + struct kobject *vf_kobj; + struct kobject *vf_tc_kobjs[VFD_NUM_TC]; +}; + +/** + * struct vfd_qos_objects - VF-d qos kobjects information struct + * @qos_kobj: pointer to PF qos kobject + * @pf_qos_kobj: pointer to PF TC kobjects + */ +struct vfd_qos_objects { + struct kobject *qos_kobj; + struct kobject *pf_qos_kobjs[VFD_NUM_TC]; +}; + +struct vfd_macaddr { + u8 mac[ETH_ALEN]; + struct list_head list; +}; + +#define VFD_LINK_SPEED_2_5GB_SHIFT 0x0 +#define VFD_LINK_SPEED_100MB_SHIFT 0x1 +#define VFD_LINK_SPEED_1GB_SHIFT 0x2 +#define VFD_LINK_SPEED_10GB_SHIFT 0x3 +#define VFD_LINK_SPEED_40GB_SHIFT 0x4 +#define VFD_LINK_SPEED_20GB_SHIFT 0x5 +#define VFD_LINK_SPEED_25GB_SHIFT 0x6 +#define VFD_LINK_SPEED_5GB_SHIFT 0x7 + + +enum vfd_link_speed { + VFD_LINK_SPEED_UNKNOWN = 0, + VFD_LINK_SPEED_100MB = BIT(VFD_LINK_SPEED_100MB_SHIFT), + VFD_LINK_SPEED_1GB = BIT(VFD_LINK_SPEED_1GB_SHIFT), + VFD_LINK_SPEED_2_5GB = BIT(VFD_LINK_SPEED_2_5GB_SHIFT), + VFD_LINK_SPEED_5GB = BIT(VFD_LINK_SPEED_5GB_SHIFT), + VFD_LINK_SPEED_10GB = BIT(VFD_LINK_SPEED_10GB_SHIFT), + VFD_LINK_SPEED_40GB = BIT(VFD_LINK_SPEED_40GB_SHIFT), + VFD_LINK_SPEED_20GB = BIT(VFD_LINK_SPEED_20GB_SHIFT), + VFD_LINK_SPEED_25GB = BIT(VFD_LINK_SPEED_25GB_SHIFT), +}; + +struct vfd_ops { + int (*get_trunk)(struct pci_dev *pdev, int vf_id, unsigned long *buff); + int (*set_trunk)(struct pci_dev *pdev, int vf_id, + const unsigned long *buff); + int (*get_vlan_mirror)(struct pci_dev *pdev, int vf_id, + unsigned long *buff); + int (*set_vlan_mirror)(struct pci_dev *pdev, int vf_id, + const unsigned long *buff); + int (*get_egress_mirror)(struct pci_dev *pdev, int vf_id, int *data); + int (*set_egress_mirror)(struct pci_dev *pdev, int vf_id, + const int data); + int (*get_ingress_mirror)(struct pci_dev *pdev, int vf_id, int *data); + int (*set_ingress_mirror)(struct pci_dev *pdev, int vf_id, + const int data); + int (*get_mac_anti_spoof)(struct pci_dev *pdev, int vf_id, bool *data); + int (*set_mac_anti_spoof)(struct pci_dev *pdev, int vf_id, + const bool data); + int (*get_vlan_anti_spoof)(struct pci_dev *pdev, int vf_id, bool *data); + int (*set_vlan_anti_spoof)(struct pci_dev *pdev, int vf_id, + const bool data); + int (*get_allow_untagged)(struct pci_dev *pdev, int vf_id, bool *data); + int (*set_allow_untagged)(struct pci_dev *pdev, int vf_id, + const bool data); + int (*get_loopback)(struct pci_dev *pdev, int vf_id, bool *data); + int (*set_loopback)(struct pci_dev *pdev, int vf_id, const bool data); + int (*get_mac)(struct pci_dev *pdev, int vf_id, u8 *macaddr); + int (*set_mac)(struct pci_dev *pdev, int vf_id, const u8 *macaddr); + int (*get_mac_list)(struct pci_dev *pdev, int vf_id, + struct list_head *mac_list); + int (*add_macs_to_list)(struct pci_dev *pdev, int vf_id, + struct list_head *mac_list); + int (*rem_macs_from_list)(struct pci_dev *pdev, int vf_id, + struct list_head *mac_list); + int (*get_promisc)(struct pci_dev *pdev, int vf_id, u8 *data); + int (*set_promisc)(struct pci_dev *pdev, int vf_id, const u8 data); + int (*get_vlan_strip)(struct pci_dev *pdev, int vf_id, bool *data); + int (*set_vlan_strip)(struct pci_dev *pdev, int vf_id, const bool data); + int (*get_link_state)(struct pci_dev *pdev, int vf_id, bool *enabled, + enum vfd_link_speed *link_speed); + int (*set_link_state)(struct pci_dev *pdev, int vf_id, const u8 data); + int (*get_max_tx_rate)(struct pci_dev *pdev, int vf_id, + unsigned int *max_tx_rate); + int (*set_max_tx_rate)(struct pci_dev *pdev, int vf_id, + unsigned int *max_tx_rate); + int (*get_min_tx_rate)(struct kobject *, + struct kobj_attribute *, char *); + int (*set_min_tx_rate)(struct kobject *, struct kobj_attribute *, + const char *, size_t); + int (*get_spoofcheck)(struct kobject *, + struct kobj_attribute *, char *); + int (*set_spoofcheck)(struct kobject *, struct kobj_attribute *, + const char *, size_t); + int (*get_trust)(struct kobject *, + struct kobj_attribute *, char *); + int (*set_trust)(struct kobject *, struct kobj_attribute *, + const char *, size_t); + int (*get_vf_enable)(struct pci_dev *pdev, int vf_id, bool *data); + int (*set_vf_enable)(struct pci_dev *pdev, int vf_id, const bool data); + int (*get_rx_bytes) (struct pci_dev *pdev, int vf_id, u64 *data); + int (*get_rx_dropped)(struct pci_dev *pdev, int vf_id, u64 *data); + int (*get_rx_packets)(struct pci_dev *pdev, int vf_id, u64 *data); + int (*get_tx_bytes) (struct pci_dev *pdev, int vf_id, u64 *data); + int (*get_tx_dropped)(struct pci_dev *pdev, int vf_id, u64 *data); + int (*get_tx_packets)(struct pci_dev *pdev, int vf_id, u64 *data); + int (*get_tx_spoofed)(struct pci_dev *pdev, int vf_id, u64 *data); + int (*get_tx_errors)(struct pci_dev *pdev, int vf_id, u64 *data); + int (*reset_stats)(struct pci_dev *pdev, int vf_id); + int (*set_vf_bw_share)(struct pci_dev *pdev, int vf_id, u8 bw_share); + int (*get_vf_bw_share)(struct pci_dev *pdev, int vf_id, u8 *bw_share); + int (*set_pf_qos_apply)(struct pci_dev *pdev); + int (*get_pf_ingress_mirror)(struct pci_dev *pdev, int *data); + int (*set_pf_ingress_mirror)(struct pci_dev *pdev, const int data); + int (*get_pf_egress_mirror)(struct pci_dev *pdev, int *data); + int (*set_pf_egress_mirror)(struct pci_dev *pdev, const int data); + int (*get_pf_tpid)(struct pci_dev *pdev, u16 *data); + int (*set_pf_tpid)(struct pci_dev *pdev, const u16 data); + int (*get_num_queues)(struct pci_dev *pdev, int vf_id, int *num_queues); + int (*set_num_queues)(struct pci_dev *pdev, int vf_id, const int num_queues); + int (*get_trust_state)(struct pci_dev *pdev, int vf_id, bool *data); + int (*set_trust_state)(struct pci_dev *pdev, int vf_id, bool data); + int (*get_queue_type)(struct pci_dev *pdev, int vf_id, u8 *data); + int (*set_queue_type)(struct pci_dev *pdev, int vf_id, const u8 data); + int (*get_allow_bcast)(struct pci_dev *pdev, int vf_id, bool *data); + int (*set_allow_bcast)(struct pci_dev *pdev, int vf_id, const bool data); + int (*get_pf_qos_tc_max_bw)(struct pci_dev *pdev, int tc, u16 *req_bw); + int (*set_pf_qos_tc_max_bw)(struct pci_dev *pdev, int tc, u16 req_bw); + int (*get_pf_qos_tc_lsp)(struct pci_dev *pdev, int tc, bool *on); + int (*set_pf_qos_tc_lsp)(struct pci_dev *pdev, int tc, bool on); + int (*get_pf_qos_tc_priority)(struct pci_dev *pdev, int tc, + char *tc_bitmap); + int (*set_pf_qos_tc_priority)(struct pci_dev *pdev, int tc, + char tc_bitmap); + int (*get_vf_qos_tc_share)(struct pci_dev *pdev, int vf_id, int tc, + u8 *share); + int (*set_vf_qos_tc_share)(struct pci_dev *pdev, int vf_id, int tc, + u8 share); + int (*get_vf_max_tc_tx_rate)(struct pci_dev *pdev, int vf_id, int tc, + int *rate); + int (*set_vf_max_tc_tx_rate)(struct pci_dev *pdev, int vf_id, int tc, + int rate); +}; + +extern const struct vfd_ops *vfd_ops; + +#endif /* _KCOMPAT_VFD_H_ */ diff --git a/src/net/include/linux/dinghai/lag.h b/src/net/include/linux/dinghai/lag.h new file mode 100644 index 0000000..819297f --- /dev/null +++ b/src/net/include/linux/dinghai/lag.h @@ -0,0 +1,26 @@ +#ifndef __DINGHAI_LAG_H__ +#define __DINGHAI_LAG_H__ + +#include +#include + +#define ZXDH_PF_VFID(ep, pf) (1152 + ep * 8 + pf) + +struct zxdh_lag_attrs +{ + uint16_t pannel_id; + uint16_t vport; + uint32_t qid[2]; + uint16_t slot_id; + uint16_t pcie_id; + uint8_t phy_port; + uint8_t rsv; +}; + +void zxdh_regitster_ldev(struct dh_core_dev *dh_devs); +void zxdh_unregitster_ldev(struct dh_core_dev *dh_dev); + +int32_t zxdh_ldev_add_netdev(struct dh_core_dev *dev, uint16_t ida, struct net_device *netdev, struct zxdh_lag_attrs *attr); +void zxdh_ldev_remove_netdev(struct dh_core_dev *dh_dev, struct net_device *netdev, struct zxdh_lag_attrs *attr); + +#endif /* __DINGHAI_LAG_H__ */ \ No newline at end of file diff --git a/src/net/include/linux/dinghai/log.h b/src/net/include/linux/dinghai/log.h new file mode 100644 index 0000000..9d8bfbe --- /dev/null +++ b/src/net/include/linux/dinghai/log.h @@ -0,0 +1,39 @@ +#ifndef __KERNEL_LOG_H__ +#define __KERNEL_LOG_H__ + +#include +#include + +#define MODULE_CMD "zxdh_cmd" +#define MODULE_NP "zxdh_np" +#define MODULE_PF "zxdh_pf" +#define MODULE_PTP "zxdh_ptp" +#define MODULE_TSN "zxdh_tsn" +#define MODULE_LAG "zxdh_lag" +#define MODULE_DHTOOLS "zxdh_tool" +#define MODULE_SEC "zxdh_sec" +#define MODULE_MPF "zxdh_mpf" +#define MODULE_FUC_HP "zxdh_func_hp" + +#define DH_LOG_EMERG(module, fmt, arg...) \ + printk(KERN_EMERG "[%s][%s][%d] "fmt"", module, __func__, __LINE__, ##arg); + +#define DH_LOG_ALERT(module, fmt, arg...) \ + printk(KERN_ALERT "[%s][%s][%d] "fmt"", module, __func__, __LINE__, ##arg); + +#define DH_LOG_CRIT(module, fmt, arg...) \ + printk(KERN_CRIT "[%s][%s][%d] "fmt"", module, __func__, __LINE__, ##arg); + +#define DH_LOG_ERR(module, fmt, arg...) \ + printk(KERN_ERR "[%s][%s][%d] "fmt"", module, __func__, __LINE__, ##arg); + +#define DH_LOG_WARNING(module, fmt, arg...) \ + printk(KERN_WARNING "[%s][%s][%d] "fmt"", module, __func__, __LINE__, ##arg); + +#define DH_LOG_INFO(module, fmt, arg...) \ + printk(KERN_INFO "[%s][%s][%d] "fmt"", module, __func__, __LINE__, ##arg); + +#define DH_LOG_DEBUG(module, fmt, arg...) \ + printk(KERN_DEBUG "[%s][%s][%d] "fmt"", module, __func__, __LINE__, ##arg); + +#endif /* __KERNEL_LOG_H__ */ diff --git a/src/net/include/linux/dinghai/pci_irq.h b/src/net/include/linux/dinghai/pci_irq.h new file mode 100755 index 0000000..4ffb05d --- /dev/null +++ b/src/net/include/linux/dinghai/pci_irq.h @@ -0,0 +1,70 @@ +#ifndef DINGHAI_PCI_IRQ_H +#define DINGHAI_PCI_IRQ_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#define DH_MAX_IRQ_NAME 100 +#define DH_FW_RESERVED_EQS 16 +/* max irq_index is 2047, so four chars */ +#define DH_MAX_IRQ_IDX_CHARS (4) +#define DH_EQ_REFS_PER_IRQ (2) + +#define ZXDH_VQS_CHANNELS_NUM (64+2) +#define ZXDH_BOND_VQS_CHANNELS_NUM 3 +#define ZXDH_ASYNC_CHANNELS_NUM 38 +#define ZXDH_RDMA_CHANNELS_NUM 24 +#define ZXDH_RDMA_IRQ_START_IDX 38 +#define ZXDH_VQS_IRQ_START_IDX 62 + +struct dh_irq; + +struct dh_irq_pool { + char name[DH_MAX_IRQ_NAME]; + struct xa_limit xa_num_irqs; + struct mutex lock; /* sync IRQs creations */ + struct xarray irqs; + uint32_t max_threshold; + uint32_t min_threshold; + uint16_t *irqs_per_cpu; + struct dh_core_dev *dev; +}; + +static inline bool dh_irq_pool_is_sf_pool(struct dh_irq_pool *pool) +{ + return !strncmp("dh_mpf_sf", pool->name, strlen("dh_mpf_sf")); +} + +struct dh_irq *zxdh_get_irq_of_pool(struct dh_core_dev *dev, struct dh_irq_pool *pool); + +struct dh_irq *dh_irq_alloc(struct dh_irq_pool *pool, int32_t i, + const struct cpumask *affinity); + +int32_t dh_irq_read_locked(struct dh_irq *irq); +int32_t dh_irq_get_locked(struct dh_irq *irq); +int32_t dh_irq_put(struct dh_irq *irq); + +void irq_pool_free(struct dh_irq_pool *pool); +struct dh_irq_pool * +irq_pool_alloc(struct dh_core_dev *dev, int32_t start, int32_t size, char *name, + uint32_t min_threshold, uint32_t max_threshold); + +struct dh_irq { + struct atomic_notifier_head nh; /* notification chain invoked when an interruption is triggered. the invocation environment is the atomic context */ + cpumask_var_t mask; /* interrupt affinity */ + char name[DH_MAX_IRQ_NAME]; /* interrupt name */ + struct dh_irq_pool *pool; /* interrupt pool */ + int32_t refcount; + uint32_t index; /* interrupt vec index */ + int32_t irqn; /* interrupt number */ +}; + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/src/net/include/linux/dinghai/queue.h b/src/net/include/linux/dinghai/queue.h new file mode 100644 index 0000000..29cce9e --- /dev/null +++ b/src/net/include/linux/dinghai/queue.h @@ -0,0 +1,78 @@ +#ifndef __DINGHAI_QUEUE_H__ +#define __DINGHAI_QUEUE_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Vector value used to disable MSI for queue */ +#define ZXDH_MSI_NO_VECTOR 0xffff + +/* Status byte for guest to report progress, and synchronize features */ +/* We have seen device and processed generic fields */ +#define ZXDH_CONFIG_S_ACKNOWLEDGE 1 +/* We have found a driver for the device. */ +#define ZXDH_CONFIG_S_DRIVER 2 +/* Driver has used its parts of the config, and is happy */ +#define ZXDH_CONFIG_S_DRIVER_OK 4 +/* Driver has finished configuring features */ +#define ZXDH_CONFIG_S_FEATURES_OK 8 +/* Device entered invalid state, driver must reset it */ +#define ZXDH_CONFIG_S_NEEDS_RESET 0x40 +/* We've given up on this device */ +#define ZXDH_CONFIG_S_FAILED 0x80 + + +/* This is the PCI capability header: */ +struct zxdh_pf_pci_cap +{ + __u8 cap_vndr; /* Generic PCI field: PCI_CAP_ID_VNDR */ + __u8 cap_next; /* Generic PCI field: next ptr. */ + __u8 cap_len; /* Generic PCI field: capability length */ + __u8 cfg_type; /* Identifies the structure. */ + __u8 bar; /* Where to find it. */ + __u8 id; /* Multiple capabilities of the same type */ + __u8 padding[2]; /* Pad to full dword. */ + __le32 offset; /* Offset within bar. */ + __le32 length; /* Length of the structure, in bytes. */ +}; + +/* Fields in ZXDH_PF_PCI_CAP_COMMON_CFG: */ +struct zxdh_pf_pci_common_cfg +{ + /* About the whole device. */ + __le32 device_feature_select; /* read-write */ + __le32 device_feature; /* read-only */ + __le32 guest_feature_select; /* read-write */ + __le32 guest_feature; /* read-write */ + __le16 msix_config; /* read-write */ + __le16 num_queues; /* read-only */ + __u8 device_status; /* read-write */ + __u8 config_generation; /* read-only */ + + /* About a specific virtqueue. */ + __le16 queue_select; /* read-write */ + __le16 queue_size; /* read-write, power of 2. */ + __le16 queue_msix_vector; /* read-write */ + __le16 queue_enable; /* read-write */ + __le16 queue_notify_off; /* read-only */ + __le32 queue_desc_lo; /* read-write */ + __le32 queue_desc_hi; /* read-write */ + __le32 queue_avail_lo; /* read-write */ + __le32 queue_avail_hi; /* read-write */ + __le32 queue_used_lo; /* read-write */ + __le32 queue_used_hi; /* read-write */ +}; + +struct zxdh_pf_pci_notify_cap +{ + struct zxdh_pf_pci_cap cap; + __le32 notify_off_multiplier; /* Multiplier for queue_notify_off. */ +}; + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/net/include/linux/types.h b/src/net/include/linux/types.h new file mode 100755 index 0000000..0553b4e --- /dev/null +++ b/src/net/include/linux/types.h @@ -0,0 +1,5 @@ +#ifndef _COMPAT_LINUX_TYPES_H +#define _COMPAT_LINUX_TYPES_H 1 +#include_next + +#endif \ No newline at end of file diff --git a/src/net/pci.updates b/src/net/pci.updates new file mode 100644 index 0000000..f9fd22e --- /dev/null +++ b/src/net/pci.updates @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: GPL-2.0-only +# Copyright (C) 1999 - 2023 ZTE Corporation + +# updates for the system pci.ids file +# +# IMPORTANT! Entries in this list must be sorted as they +# would appear in the system pci.ids file. Entries +# are sorted by ven, dev, subven, subdev +# (numerical order). +# + +# Vendors, devices and subsystems. Please keep sorted. + +# Syntax: +# vendor vendor_name +# device device_name <-- single tab +# subvendor subdevice subsystem_name <-- two tabs + +1111 Santa Cruz Operation + 1041 MPF Ethernet Controller +16c3 Synopsys, Inc. + 8040 PF BSI Ethernet Controller + 8041 VF BSI Ethernet Controller Virtual Function +1cf2 ZTE Corporation + 8040 NEO X510 SRIOV PF Ethernet Controller + 8041 NEO X510 SRIOV VF Ethernet Controller Virtual Function + 8042 NX I512 VDPA VF Ethernet Controller Virtual Function + 8044 NEO X510 MPF Ethernet Controller + 8045 NX I512 BOND PF Ethernet Controller + 8046 NX I512 OVS PF Ethernet Controller + 8047 NEO X510 BOND PF Ethernet Controller + 8048 NEO X510 OVS PF Ethernet Controller + 8049 NX E312 SRIOV PF Ethernet Controller + 8060 NX E312 SRIOV VF Ethernet Controller Virtual Function + 8061 NX E310 SRIOV PF Ethernet Controller + 8062 NX E310 SRIOV VF Ethernet Controller Virtual Function + 8063 NX I510 BOND PF Ethernet Controller + 8064 NX I510 OVS PF Ethernet Controller + 8065 NX I510 VDPA VF Ethernet Controller Virtual Function + 8066 NX I511 BOND PF Ethernet Controller + 8067 NX I511 OVS PF Ethernet Controller + 8068 NX I511 VDPA VF Ethernet Controller Virtual Function + + diff --git a/src/net/scripts/.gitignore b/src/net/scripts/.gitignore new file mode 100644 index 0000000..a6c1131 --- /dev/null +++ b/src/net/scripts/.gitignore @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-only +bin2c +kallsyms +unifdef +recordmcount +sorttable +asn1_compiler +extract-cert +sign-file +insert-sys-cert +/module.lds diff --git a/src/net/scripts/Kbuild.include b/src/net/scripts/Kbuild.include new file mode 100644 index 0000000..0d6e118 --- /dev/null +++ b/src/net/scripts/Kbuild.include @@ -0,0 +1,328 @@ +# SPDX-License-Identifier: GPL-2.0 +#### +# kbuild: Generic definitions + +# Convenient variables +comma := , +quote := " +squote := ' +empty := +space := $(empty) $(empty) +space_escape := _-_SPACE_-_ +pound := \# + +### +# Name of target with a '.' as filename prefix. foo/bar.o => foo/.bar.o +dot-target = $(dir $@).$(notdir $@) + +### +# The temporary file to save gcc -MMD generated dependencies must not +# contain a comma +depfile = $(subst $(comma),_,$(dot-target).d) + +### +# filename of target with directory and extension stripped +basetarget = $(basename $(notdir $@)) + +### +# real prerequisites without phony targets +real-prereqs = $(filter-out $(PHONY), $^) + +### +# Escape single quote for use in echo statements +escsq = $(subst $(squote),'\$(squote)',$1) + +### +# Quote a string to pass it to C files. foo => '"foo"' +stringify = $(squote)$(quote)$1$(quote)$(squote) + +### +# Easy method for doing a status message + kecho := : + quiet_kecho := echo +silent_kecho := : +kecho := $($(quiet)kecho) + +### +# filechk is used to check if the content of a generated file is updated. +# Sample usage: +# +# filechk_sample = echo $(KERNELRELEASE) +# version.h: FORCE +# $(call filechk,sample) +# +# The rule defined shall write to stdout the content of the new file. +# The existing file will be compared with the new one. +# - If no file exist it is created +# - If the content differ the new file is used +# - If they are equal no change, and no timestamp update +define filechk + $(Q)set -e; \ + mkdir -p $(dir $@); \ + trap "rm -f $(dot-target).tmp" EXIT; \ + { $(filechk_$(1)); } > $(dot-target).tmp; \ + if [ ! -r $@ ] || ! cmp -s $@ $(dot-target).tmp; then \ + $(kecho) ' UPD $@'; \ + mv -f $(dot-target).tmp $@; \ + fi +endef + +###### +# gcc support functions +# See documentation in Documentation/kbuild/makefiles.rst + +# cc-cross-prefix +# Usage: CROSS_COMPILE := $(call cc-cross-prefix, m68k-linux-gnu- m68k-linux-) +# Return first where a gcc is found in PATH. +# If no gcc found in PATH with listed prefixes return nothing +# +# Note: '2>/dev/null' is here to force Make to invoke a shell. Otherwise, it +# would try to directly execute the shell builtin 'command'. This workaround +# should be kept for a long time since this issue was fixed only after the +# GNU Make 4.2.1 release. +cc-cross-prefix = $(firstword $(foreach c, $(1), \ + $(if $(shell command -v -- $(c)gcc 2>/dev/null), $(c)))) + +# output directory for tests below +TMPOUT = $(if $(KBUILD_EXTMOD),$(firstword $(KBUILD_EXTMOD))/).tmp_$$$$ + +# try-run +# Usage: option = $(call try-run, $(CC)...-o "$$TMP",option-ok,otherwise) +# Exit code chooses option. "$$TMP" serves as a temporary file and is +# automatically cleaned up. +try-run = $(shell set -e; \ + TMP=$(TMPOUT)/tmp; \ + TMPO=$(TMPOUT)/tmp.o; \ + mkdir -p $(TMPOUT); \ + trap "rm -rf $(TMPOUT)" EXIT; \ + if ($(1)) >/dev/null 2>&1; \ + then echo "$(2)"; \ + else echo "$(3)"; \ + fi) + +# as-option +# Usage: cflags-y += $(call as-option,-Wa$(comma)-isa=foo,) + +as-option = $(call try-run,\ + $(CC) $(KBUILD_CFLAGS) $(1) -c -x assembler /dev/null -o "$$TMP",$(1),$(2)) + +# as-instr +# Usage: cflags-y += $(call as-instr,instr,option1,option2) + +as-instr = $(call try-run,\ + printf "%b\n" "$(1)" | $(CC) $(KBUILD_AFLAGS) -c -x assembler -o "$$TMP" -,$(2),$(3)) + +# __cc-option +# Usage: MY_CFLAGS += $(call __cc-option,$(CC),$(MY_CFLAGS),-march=winchip-c6,-march=i586) +__cc-option = $(call try-run,\ + $(1) -Werror $(2) $(3) -c -x c /dev/null -o "$$TMP",$(3),$(4)) + +# cc-option +# Usage: cflags-y += $(call cc-option,-march=winchip-c6,-march=i586) + +cc-option = $(call __cc-option, $(CC),\ + $(KBUILD_CPPFLAGS) $(KBUILD_CFLAGS),$(1),$(2)) + +# cc-option-yn +# Usage: flag := $(call cc-option-yn,-march=winchip-c6) +cc-option-yn = $(call try-run,\ + $(CC) -Werror $(KBUILD_CPPFLAGS) $(KBUILD_CFLAGS) $(1) -c -x c /dev/null -o "$$TMP",y,n) + +# cc-disable-warning +# Usage: cflags-y += $(call cc-disable-warning,unused-but-set-variable) +cc-disable-warning = $(call try-run,\ + $(CC) -Werror $(KBUILD_CPPFLAGS) $(KBUILD_CFLAGS) -W$(strip $(1)) -c -x c /dev/null -o "$$TMP",-Wno-$(strip $(1))) + +# cc-ifversion +# Usage: EXTRA_CFLAGS += $(call cc-ifversion, -lt, 0402, -O1) +cc-ifversion = $(shell [ $(CONFIG_GCC_VERSION)0 $(1) $(2)000 ] && echo $(3) || echo $(4)) + +# ld-option +# Usage: KBUILD_LDFLAGS += $(call ld-option, -X, -Y) +ld-option = $(call try-run, $(LD) $(KBUILD_LDFLAGS) $(1) -v,$(1),$(2),$(3)) + +# ld-version +# Note this is mainly for HJ Lu's 3 number binutil versions +ld-version = $(shell $(LD) --version | $(srctree)/scripts/ld-version.sh) + +# ld-ifversion +# Usage: $(call ld-ifversion, -ge, 22252, y) +ld-ifversion = $(shell [ $(ld-version) $(1) $(2) ] && echo $(3) || echo $(4)) + +###### + +### +# Shorthand for $(Q)$(MAKE) -f scripts/Makefile.build obj= +# Usage: +# $(Q)$(MAKE) $(build)=dir +build := -f $(srctree)/scripts/Makefile.build obj + +### +# Shorthand for $(Q)$(MAKE) -f scripts/Makefile.dtbinst obj= +# Usage: +# $(Q)$(MAKE) $(dtbinst)=dir +dtbinst := -f $(srctree)/scripts/Makefile.dtbinst obj + +### +# Shorthand for $(Q)$(MAKE) -f scripts/Makefile.clean obj= +# Usage: +# $(Q)$(MAKE) $(clean)=dir +clean := -f $(srctree)/scripts/Makefile.clean obj + +# echo command. +# Short version is used, if $(quiet) equals `quiet_', otherwise full one. +echo-cmd = $(if $($(quiet)cmd_$(1)),\ + echo ' $(call escsq,$($(quiet)cmd_$(1)))$(echo-why)';) + +# sink stdout for 'make -s' + redirect := + quiet_redirect := +silent_redirect := exec >/dev/null; + +# printing commands +cmd = @set -e; $(echo-cmd) $($(quiet)redirect) $(cmd_$(1)) + +### +# if_changed - execute command if any prerequisite is newer than +# target, or command line has changed +# if_changed_dep - as if_changed, but uses fixdep to reveal dependencies +# including used config symbols +# if_changed_rule - as if_changed but execute rule instead +# See Documentation/kbuild/makefiles.rst for more info + +ifneq ($(KBUILD_NOCMDDEP),1) +# Check if both commands are the same including their order. Result is empty +# string if equal. User may override this check using make KBUILD_NOCMDDEP=1 +cmd-check = $(filter-out $(subst $(space),$(space_escape),$(strip $(cmd_$@))), \ + $(subst $(space),$(space_escape),$(strip $(cmd_$1)))) +else +cmd-check = $(if $(strip $(cmd_$@)),,1) +endif + +# Replace >$< with >$$< to preserve $ when reloading the .cmd file +# (needed for make) +# Replace >#< with >$(pound)< to avoid starting a comment in the .cmd file +# (needed for make) +# Replace >'< with >'\''< to be able to enclose the whole string in '...' +# (needed for the shell) +make-cmd = $(call escsq,$(subst $(pound),$$(pound),$(subst $$,$$$$,$(cmd_$(1))))) + +# Find any prerequisites that are newer than target or that do not exist. +# (This is not true for now; $? should contain any non-existent prerequisites, +# but it does not work as expected when .SECONDARY is present. This seems a bug +# of GNU Make.) +# PHONY targets skipped in both cases. +newer-prereqs = $(filter-out $(PHONY),$?) + +# Execute command if command has changed or prerequisite(s) are updated. +if_changed = $(if $(newer-prereqs)$(cmd-check), \ + $(cmd); \ + printf '%s\n' 'cmd_$@ := $(make-cmd)' > $(dot-target).cmd, @:) + +# Execute the command and also postprocess generated .d dependencies file. +if_changed_dep = $(if $(newer-prereqs)$(cmd-check),$(cmd_and_fixdep),@:) + +cmd_and_fixdep = \ + $(cmd); \ + scripts/basic/fixdep $(depfile) $@ '$(make-cmd)' > $(dot-target).cmd;\ + rm -f $(depfile) + +# Usage: $(call if_changed_rule,foo) +# Will check if $(cmd_foo) or any of the prerequisites changed, +# and if so will execute $(rule_foo). +if_changed_rule = $(if $(newer-prereqs)$(cmd-check),$(rule_$(1)),@:) + +### +# why - tell why a target got built +# enabled by make V=2 +# Output (listed in the order they are checked): +# (1) - due to target is PHONY +# (2) - due to target missing +# (3) - due to: file1.h file2.h +# (4) - due to command line change +# (5) - due to missing .cmd file +# (6) - due to target not in $(targets) +# (1) PHONY targets are always build +# (2) No target, so we better build it +# (3) Prerequisite is newer than target +# (4) The command line stored in the file named dir/.target.cmd +# differed from actual command line. This happens when compiler +# options changes +# (5) No dir/.target.cmd file (used to store command line) +# (6) No dir/.target.cmd file and target not listed in $(targets) +# This is a good hint that there is a bug in the kbuild file +ifeq ($(KBUILD_VERBOSE),2) +why = \ + $(if $(filter $@, $(PHONY)),- due to target is PHONY, \ + $(if $(wildcard $@), \ + $(if $(newer-prereqs),- due to: $(newer-prereqs), \ + $(if $(cmd-check), \ + $(if $(cmd_$@),- due to command line change, \ + $(if $(filter $@, $(targets)), \ + - due to missing .cmd file, \ + - due to $(notdir $@) not in $$(targets) \ + ) \ + ) \ + ) \ + ), \ + - due to target missing \ + ) \ + ) + +echo-why = $(call escsq, $(strip $(why))) +endif + +############################################################################### +# +# When a Kconfig string contains a filename, it is suitable for +# passing to shell commands. It is surrounded by double-quotes, and +# any double-quotes or backslashes within it are escaped by +# backslashes. +# +# This is no use for dependencies or $(wildcard). We need to strip the +# surrounding quotes and the escaping from quotes and backslashes, and +# we *do* need to escape any spaces in the string. So, for example: +# +# Usage: $(eval $(call config_filename,FOO)) +# +# Defines FOO_FILENAME based on the contents of the CONFIG_FOO option, +# transformed as described above to be suitable for use within the +# makefile. +# +# Also, if the filename is a relative filename and exists in the source +# tree but not the build tree, define FOO_SRCPREFIX as $(srctree)/ to +# be prefixed to *both* command invocation and dependencies. +# +# Note: We also print the filenames in the quiet_cmd_foo text, and +# perhaps ought to have a version specially escaped for that purpose. +# But it's only cosmetic, and $(patsubst "%",%,$(CONFIG_FOO)) is good +# enough. It'll strip the quotes in the common case where there's no +# space and it's a simple filename, and it'll retain the quotes when +# there's a space. There are some esoteric cases in which it'll print +# the wrong thing, but we don't really care. The actual dependencies +# and commands *do* get it right, with various combinations of single +# and double quotes, backslashes and spaces in the filenames. +# +############################################################################### +# +define config_filename +ifneq ($$(CONFIG_$(1)),"") +$(1)_FILENAME := $$(subst \\,\,$$(subst \$$(quote),$$(quote),$$(subst $$(space_escape),\$$(space),$$(patsubst "%",%,$$(subst $$(space),$$(space_escape),$$(CONFIG_$(1))))))) +ifneq ($$(patsubst /%,%,$$(firstword $$($(1)_FILENAME))),$$(firstword $$($(1)_FILENAME))) +else +ifeq ($$(wildcard $$($(1)_FILENAME)),) +ifneq ($$(wildcard $$(srctree)/$$($(1)_FILENAME)),) +$(1)_SRCPREFIX := $(srctree)/ +endif +endif +endif +endif +endef +# +############################################################################### + +# delete partially updated (i.e. corrupted) files on error +.DELETE_ON_ERROR: + +# do not delete intermediate files automatically +.SECONDARY: diff --git a/src/net/scripts/Kconfig.include b/src/net/scripts/Kconfig.include new file mode 100644 index 0000000..a5fe72c --- /dev/null +++ b/src/net/scripts/Kconfig.include @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0-only +# Kconfig helper macros + +# Convenient variables +comma := , +quote := " +squote := ' +empty := +space := $(empty) $(empty) +dollar := $ +right_paren := ) +left_paren := ( + +# $(if-success,,,) +# Return if exits with 0, otherwise. +if-success = $(shell,{ $(1); } >/dev/null 2>&1 && echo "$(2)" || echo "$(3)") + +# $(success,) +# Return y if exits with 0, n otherwise +success = $(if-success,$(1),y,n) + +# $(failure,) +# Return n if exits with 0, y otherwise +failure = $(if-success,$(1),n,y) + +# $(cc-option,) +# Return y if the compiler supports , n otherwise +cc-option = $(success,mkdir .tmp_$$$$; trap "rm -rf .tmp_$$$$" EXIT; $(CC) -Werror $(CLANG_FLAGS) $(1) -c -x c /dev/null -o .tmp_$$$$/tmp.o) + +# $(ld-option,) +# Return y if the linker supports , n otherwise +ld-option = $(success,$(LD) -v $(1)) + +# $(as-instr,) +# Return y if the assembler supports , n otherwise +as-instr = $(success,printf "%b\n" "$(1)" | $(CC) $(CLANG_FLAGS) -c -x assembler -o /dev/null -) + +# check if $(CC) and $(LD) exist +$(error-if,$(failure,command -v $(CC)),compiler '$(CC)' not found) +$(error-if,$(failure,command -v $(LD)),linker '$(LD)' not found) + +# Fail if the linker is gold as it's not capable of linking the kernel proper +$(error-if,$(success, $(LD) -v | grep -q gold), gold linker '$(LD)' not supported) + +# machine bit flags +# $(m32-flag): -m32 if the compiler supports it, or an empty string otherwise. +# $(m64-flag): -m64 if the compiler supports it, or an empty string otherwise. +cc-option-bit = $(if-success,$(CC) -Werror $(1) -E -x c /dev/null -o /dev/null,$(1)) +m32-flag := $(cc-option-bit,-m32) +m64-flag := $(cc-option-bit,-m64) diff --git a/src/net/scripts/Lindent b/src/net/scripts/Lindent new file mode 100755 index 0000000..1688c44 --- /dev/null +++ b/src/net/scripts/Lindent @@ -0,0 +1,26 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0 + +PARAM="-npro -kr -i8 -ts8 -sob -l80 -ss -ncs -cp1" + +RES=`indent --version | cut -d' ' -f3` +if [ "$RES" = "" ]; then + exit 1 +fi +V1=`echo $RES | cut -d'.' -f1` +V2=`echo $RES | cut -d'.' -f2` +V3=`echo $RES | cut -d'.' -f3` + +if [ $V1 -gt 2 ]; then + PARAM="$PARAM -il0" +elif [ $V1 -eq 2 ]; then + if [ $V2 -gt 2 ]; then + PARAM="$PARAM -il0" + elif [ $V2 -eq 2 ]; then + if [ $V3 -ge 10 ]; then + PARAM="$PARAM -il0" + fi + fi +fi + +indent $PARAM "$@" diff --git a/src/net/scripts/Makefile b/src/net/scripts/Makefile new file mode 100644 index 0000000..399ebfb --- /dev/null +++ b/src/net/scripts/Makefile @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: GPL-2.0 +### +# scripts contains sources for various helper programs used throughout +# the kernel for the build process. + +CRYPTO_LIBS = $(shell pkg-config --libs libcrypto 2> /dev/null || echo -lcrypto) +CRYPTO_CFLAGS = $(shell pkg-config --cflags libcrypto 2> /dev/null) + +hostprogs-always-$(CONFIG_BUILD_BIN2C) += bin2c +hostprogs-always-$(CONFIG_KALLSYMS) += kallsyms +hostprogs-always-$(BUILD_C_RECORDMCOUNT) += recordmcount +hostprogs-always-$(CONFIG_BUILDTIME_TABLE_SORT) += sorttable +hostprogs-always-$(CONFIG_ASN1) += asn1_compiler +hostprogs-always-$(CONFIG_MODULE_SIG_FORMAT) += sign-file +hostprogs-always-$(CONFIG_SYSTEM_TRUSTED_KEYRING) += extract-cert +hostprogs-always-$(CONFIG_SYSTEM_EXTRA_CERTIFICATE) += insert-sys-cert +hostprogs-always-$(CONFIG_SYSTEM_REVOCATION_LIST) += extract-cert + +HOSTCFLAGS_sorttable.o = -I$(srctree)/tools/include +HOSTLDLIBS_sorttable = -lpthread +HOSTCFLAGS_asn1_compiler.o = -I$(srctree)/include +HOSTCFLAGS_sign-file.o = $(CRYPTO_CFLAGS) +HOSTLDLIBS_sign-file = $(CRYPTO_LIBS) +HOSTCFLAGS_extract-cert.o = $(CRYPTO_CFLAGS) +HOSTLDLIBS_extract-cert = $(CRYPTO_LIBS) + +ifdef CONFIG_UNWINDER_ORC +ifneq ($(filter loongarch loongarch64, $(ARCH)),) +HOSTCFLAGS_sorttable.o += -I$(srctree)/tools/arch/loongarch/include +HOSTCFLAGS_sorttable.o += -DUNWINDER_ORC_ENABLED +HOSTLDLIBS_sorttable = -lpthread +else +ifeq ($(ARCH),x86_64) +ARCH := x86 +endif +HOSTCFLAGS_sorttable.o += -I$(srctree)/tools/arch/x86/include +HOSTCFLAGS_sorttable.o += -DUNWINDER_ORC_ENABLED +endif +endif + +ifdef CONFIG_BUILDTIME_MCOUNT_SORT +HOSTCFLAGS_sorttable.o += -DMCOUNT_SORT_ENABLED +endif + +# The following programs are only built on demand +hostprogs += unifdef + +# The module linker script is preprocessed on demand +targets += module.lds + +subdir-$(CONFIG_GCC_PLUGINS) += gcc-plugins +subdir-$(CONFIG_MODVERSIONS) += genksyms +subdir-$(CONFIG_SECURITY_SELINUX) += selinux + +# Let clean descend into subdirs +subdir- += basic dtc gdb kconfig mod diff --git a/src/net/scripts/Makefile.asm-generic b/src/net/scripts/Makefile.asm-generic new file mode 100644 index 0000000..82ad63d --- /dev/null +++ b/src/net/scripts/Makefile.asm-generic @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: GPL-2.0 +# include/asm-generic contains a lot of files that are used +# verbatim by several architectures. +# +# This Makefile reads the file arch/$(SRCARCH)/include/(uapi/)/asm/Kbuild +# and for each file listed in this file with generic-y creates +# a small wrapper file in arch/$(SRCARCH)/include/generated/(uapi/)/asm. + +PHONY := all +all: + +src := $(subst /generated,,$(obj)) +-include $(src)/Kbuild + +# $(generic)/Kbuild lists mandatory-y. Exclude um since it is a special case. +ifneq ($(SRCARCH),um) +include $(generic)/Kbuild +endif + +include scripts/Kbuild.include + +redundant := $(filter $(mandatory-y) $(generated-y), $(generic-y)) +redundant += $(foreach f, $(generic-y), $(if $(wildcard $(srctree)/$(src)/$(f)),$(f))) +redundant := $(sort $(redundant)) +$(if $(redundant),\ + $(warning redundant generic-y found in $(src)/Kbuild: $(redundant))) + +# If arch does not implement mandatory headers, fallback to asm-generic ones. +mandatory-y := $(filter-out $(generated-y), $(mandatory-y)) +generic-y += $(foreach f, $(mandatory-y), $(if $(wildcard $(srctree)/$(src)/$(f)),,$(f))) + +generic-y := $(addprefix $(obj)/, $(generic-y)) +generated-y := $(addprefix $(obj)/, $(generated-y)) + +# Remove stale wrappers when the corresponding files are removed from generic-y +old-headers := $(wildcard $(obj)/*.h) +unwanted := $(filter-out $(generic-y) $(generated-y),$(old-headers)) + +quiet_cmd_wrap = WRAP $@ + cmd_wrap = echo "\#include " > $@ + +quiet_cmd_remove = REMOVE $(unwanted) + cmd_remove = rm -f $(unwanted) + +all: $(generic-y) + $(if $(unwanted),$(call cmd,remove)) + @: + +$(obj)/%.h: + $(call cmd,wrap) + +# Create output directory. Skip it if at least one old header exists +# since we know the output directory already exists. +ifeq ($(old-headers),) +$(shell mkdir -p $(obj)) +endif + +.PHONY: $(PHONY) diff --git a/src/net/scripts/Makefile.build b/src/net/scripts/Makefile.build new file mode 100644 index 0000000..17e8b20 --- /dev/null +++ b/src/net/scripts/Makefile.build @@ -0,0 +1,533 @@ +# SPDX-License-Identifier: GPL-2.0 +# ========================================================================== +# Building +# ========================================================================== + +src := $(obj) + +PHONY := __build +__build: + +# Init all relevant variables used in kbuild files so +# 1) they have correct type +# 2) they do not inherit any value from the environment +obj-y := +obj-m := +lib-y := +lib-m := +always := +always-y := +always-m := +targets := +subdir-y := +subdir-m := +EXTRA_AFLAGS := +EXTRA_CFLAGS := +EXTRA_CPPFLAGS := +EXTRA_LDFLAGS := +asflags-y := +ccflags-y := +cppflags-y := +ldflags-y := + +subdir-asflags-y := +subdir-ccflags-y := + +# Read auto.conf if it exists, otherwise ignore +-include include/config/auto.conf + +include scripts/Kbuild.include + +# The filename Kbuild has precedence over Makefile +kbuild-dir := $(if $(filter /%,$(src)),$(src),$(srctree)/$(src)) +kbuild-file := $(if $(wildcard $(kbuild-dir)/Kbuild),$(kbuild-dir)/Kbuild,$(kbuild-dir)/Makefile) +include $(kbuild-file) + +include scripts/Makefile.lib + +# Do not include hostprogs rules unless needed. +# $(sort ...) is used here to remove duplicated words and excessive spaces. +hostprogs := $(sort $(hostprogs)) +ifneq ($(hostprogs),) +include scripts/Makefile.host +endif + +# Do not include userprogs rules unless needed. +# $(sort ...) is used here to remove duplicated words and excessive spaces. +userprogs := $(sort $(userprogs)) +ifneq ($(userprogs),) +include scripts/Makefile.userprogs +endif + +ifndef obj +$(warning kbuild: Makefile.build is included improperly) +endif + +ifeq ($(need-modorder),) +ifneq ($(obj-m),) +$(warning $(patsubst %.o,'%.ko',$(obj-m)) will not be built even though obj-m is specified.) +$(warning You cannot use subdir-y/m to visit a module Makefile. Use obj-y/m instead.) +endif +endif + +# =========================================================================== + +# subdir-builtin and subdir-modorder may contain duplications. Use $(sort ...) +subdir-builtin := $(sort $(filter %/built-in.a, $(real-obj-y))) +subdir-modorder := $(sort $(filter %/modules.order, $(obj-m))) + +targets-for-builtin := $(extra-y) + +ifneq ($(strip $(lib-y) $(lib-m) $(lib-)),) +targets-for-builtin += $(obj)/lib.a +endif + +ifdef need-builtin +targets-for-builtin += $(obj)/built-in.a +endif + +targets-for-modules := $(patsubst %.o, %.mod, $(filter %.o, $(obj-m))) + +ifdef need-modorder +targets-for-modules += $(obj)/modules.order +endif + +targets += $(targets-for-builtin) $(targets-for-modules) + +# Linus' kernel sanity checking tool +ifeq ($(KBUILD_CHECKSRC),1) + quiet_cmd_checksrc = CHECK $< + cmd_checksrc = $(CHECK) $(CHECKFLAGS) $(c_flags) $< +else ifeq ($(KBUILD_CHECKSRC),2) + quiet_cmd_force_checksrc = CHECK $< + cmd_force_checksrc = $(CHECK) $(CHECKFLAGS) $(c_flags) $< +endif + +ifneq ($(KBUILD_EXTRA_WARN),) + cmd_checkdoc = $(srctree)/scripts/kernel-doc -none $< +endif + +# Compile C sources (.c) +# --------------------------------------------------------------------------- + +quiet_cmd_cc_s_c = CC $(quiet_modtag) $@ + cmd_cc_s_c = $(CC) $(filter-out $(DEBUG_CFLAGS), $(c_flags)) -fverbose-asm -S -o $@ $< + +$(obj)/%.s: $(src)/%.c FORCE + $(call if_changed_dep,cc_s_c) + +quiet_cmd_cpp_i_c = CPP $(quiet_modtag) $@ +cmd_cpp_i_c = $(CPP) $(c_flags) -o $@ $< + +$(obj)/%.i: $(src)/%.c FORCE + $(call if_changed_dep,cpp_i_c) + +# These mirror gensymtypes_S and co below, keep them in synch. +cmd_gensymtypes_c = \ + $(CPP) -D__GENKSYMS__ $(c_flags) $< | \ + scripts/genksyms/genksyms $(if $(1), -T $(2)) \ + $(patsubst y,-R,$(CONFIG_MODULE_REL_CRCS)) \ + $(if $(KBUILD_PRESERVE),-p) \ + -r $(firstword $(wildcard $(2:.symtypes=.symref) /dev/null)) + +quiet_cmd_cc_symtypes_c = SYM $(quiet_modtag) $@ +cmd_cc_symtypes_c = \ + $(call cmd_gensymtypes_c,true,$@) >/dev/null; \ + test -s $@ || rm -f $@ + +$(obj)/%.symtypes : $(src)/%.c FORCE + $(call cmd,cc_symtypes_c) + +# LLVM assembly +# Generate .ll files from .c +quiet_cmd_cc_ll_c = CC $(quiet_modtag) $@ + cmd_cc_ll_c = $(CC) $(c_flags) -emit-llvm -S -o $@ $< + +$(obj)/%.ll: $(src)/%.c FORCE + $(call if_changed_dep,cc_ll_c) + +# C (.c) files +# The C file is compiled and updated dependency information is generated. +# (See cmd_cc_o_c + relevant part of rule_cc_o_c) + +quiet_cmd_cc_o_c = CC $(quiet_modtag) $@ + cmd_cc_o_c = $(CC) $(c_flags) -c -o $@ $< + +ifdef CONFIG_MODVERSIONS +# When module versioning is enabled the following steps are executed: +# o compile a .o from .c +# o if .o doesn't contain a __ksymtab version, i.e. does +# not export symbols, it's done. +# o otherwise, we calculate symbol versions using the good old +# genksyms on the preprocessed source and postprocess them in a way +# that they are usable as a linker script +# o generate .tmp_.o from .o using the linker to +# replace the unresolved symbols __crc_exported_symbol with +# the actual value of the checksum generated by genksyms +# o remove .tmp_.o to .o + +cmd_modversions_c = \ + if $(OBJDUMP) -h $@ | grep -q __ksymtab; then \ + $(call cmd_gensymtypes_c,$(KBUILD_SYMTYPES),$(@:.o=.symtypes)) \ + > $(@D)/.tmp_$(@F:.o=.ver); \ + \ + $(LD) $(KBUILD_LDFLAGS) -r -o $(@D)/.tmp_$(@F) $@ \ + -T $(@D)/.tmp_$(@F:.o=.ver); \ + mv -f $(@D)/.tmp_$(@F) $@; \ + rm -f $(@D)/.tmp_$(@F:.o=.ver); \ + fi +endif + +ifdef CONFIG_FTRACE_MCOUNT_RECORD +ifndef CC_USING_RECORD_MCOUNT +# compiler will not generate __mcount_loc use recordmcount or recordmcount.pl +ifdef BUILD_C_RECORDMCOUNT +ifeq ("$(origin RECORDMCOUNT_WARN)", "command line") + RECORDMCOUNT_FLAGS = -w +endif +# Due to recursion, we must skip empty.o. +# The empty.o file is created in the make process in order to determine +# the target endianness and word size. It is made before all other C +# files, including recordmcount. +sub_cmd_record_mcount = \ + if [ $(@) != "scripts/mod/empty.o" ]; then \ + $(objtree)/scripts/recordmcount $(RECORDMCOUNT_FLAGS) "$(@)"; \ + fi; +recordmcount_source := $(srctree)/scripts/recordmcount.c \ + $(srctree)/scripts/recordmcount.h +else +sub_cmd_record_mcount = perl $(srctree)/scripts/recordmcount.pl "$(ARCH)" \ + "$(if $(CONFIG_CPU_BIG_ENDIAN),big,little)" \ + "$(if $(CONFIG_64BIT),64,32)" \ + "$(OBJDUMP)" "$(OBJCOPY)" "$(CC) $(KBUILD_CPPFLAGS) $(KBUILD_CFLAGS)" \ + "$(LD) $(KBUILD_LDFLAGS)" "$(NM)" "$(RM)" "$(MV)" \ + "$(if $(part-of-module),1,0)" "$(@)"; +recordmcount_source := $(srctree)/scripts/recordmcount.pl +endif # BUILD_C_RECORDMCOUNT +cmd_record_mcount = $(if $(findstring $(strip $(CC_FLAGS_FTRACE)),$(_c_flags)), \ + $(sub_cmd_record_mcount)) +endif # CC_USING_RECORD_MCOUNT +endif # CONFIG_FTRACE_MCOUNT_RECORD + +ifdef CONFIG_STACK_VALIDATION +ifneq ($(SKIP_STACK_VALIDATION),1) + +__objtool_obj := $(objtree)/tools/objtool/objtool + +objtool_args = $(if $(CONFIG_UNWINDER_ORC),orc generate,check) + +objtool_args += $(if $(part-of-module), --module,) + +ifndef CONFIG_FRAME_POINTER +objtool_args += --no-fp +endif +ifdef CONFIG_GCOV_KERNEL +objtool_args += --no-unreachable +endif +ifdef CONFIG_RETPOLINE + objtool_args += --retpoline +endif +ifdef CONFIG_RETHUNK + objtool_args += --rethunk +endif +ifdef CONFIG_X86_SMAP + objtool_args += --uaccess +endif +ifdef CONFIG_SLS + objtool_args += --sls +endif + +# 'OBJECT_FILES_NON_STANDARD := y': skip objtool checking for a directory +# 'OBJECT_FILES_NON_STANDARD_foo.o := 'y': skip objtool checking for a file +# 'OBJECT_FILES_NON_STANDARD_foo.o := 'n': override directory skip for a file +cmd_objtool = $(if $(patsubst y%,, \ + $(OBJECT_FILES_NON_STANDARD_$(basetarget).o)$(OBJECT_FILES_NON_STANDARD)n), \ + $(__objtool_obj) $(objtool_args) $@) +objtool_obj = $(if $(patsubst y%,, \ + $(OBJECT_FILES_NON_STANDARD_$(basetarget).o)$(OBJECT_FILES_NON_STANDARD)n), \ + $(__objtool_obj)) + +endif # SKIP_STACK_VALIDATION +endif # CONFIG_STACK_VALIDATION + +# Rebuild all objects when objtool changes, or is enabled/disabled. +objtool_dep = $(objtool_obj) \ + $(wildcard include/config/orc/unwinder.h \ + include/config/stack/validation.h) + +ifdef CONFIG_TRIM_UNUSED_KSYMS +cmd_gen_ksymdeps = \ + $(CONFIG_SHELL) $(srctree)/scripts/gen_ksymdeps.sh $@ >> $(dot-target).cmd + +# List module undefined symbols +undefined_syms = $(NM) $< | $(AWK) '$$1 == "U" { printf("%s%s", x++ ? " " : "", $$2) }'; +endif + +define rule_cc_o_c + $(call cmd_and_fixdep,cc_o_c) + $(call cmd,gen_ksymdeps) + $(call cmd,checksrc) + $(call cmd,checkdoc) + $(call cmd,objtool) + $(call cmd,modversions_c) + $(call cmd,record_mcount) +endef + +define rule_as_o_S + $(call cmd_and_fixdep,as_o_S) + $(call cmd,gen_ksymdeps) + $(call cmd,objtool) + $(call cmd,modversions_S) +endef + +# Built-in and composite module parts +.SECONDEXPANSION: +$(obj)/%.o: $(src)/%.c $(recordmcount_source) $$(objtool_dep) FORCE + $(call if_changed_rule,cc_o_c) + $(call cmd,force_checksrc) + +cmd_mod = { \ + echo $(if $($*-objs)$($*-y)$($*-m), $(addprefix $(obj)/, $($*-objs) $($*-y) $($*-m)), $(@:.mod=.o)); \ + $(undefined_syms) echo; \ + } > $@ + +$(obj)/%.mod: $(obj)/%.o FORCE + $(call if_changed,mod) + +quiet_cmd_cc_lst_c = MKLST $@ + cmd_cc_lst_c = $(CC) $(c_flags) -g -c -o $*.o $< && \ + $(CONFIG_SHELL) $(srctree)/scripts/makelst $*.o \ + System.map $(OBJDUMP) > $@ + +$(obj)/%.lst: $(src)/%.c FORCE + $(call if_changed_dep,cc_lst_c) + +# Compile assembler sources (.S) +# --------------------------------------------------------------------------- + +# .S file exports must have their C prototypes defined in asm/asm-prototypes.h +# or a file that it includes, in order to get versioned symbols. We build a +# dummy C file that includes asm-prototypes and the EXPORT_SYMBOL lines from +# the .S file (with trailing ';'), and run genksyms on that, to extract vers. +# +# This is convoluted. The .S file must first be preprocessed to run guards and +# expand names, then the resulting exports must be constructed into plain +# EXPORT_SYMBOL(symbol); to build our dummy C file, and that gets preprocessed +# to make the genksyms input. +# +# These mirror gensymtypes_c and co above, keep them in synch. +cmd_gensymtypes_S = \ + { echo "\#include " ; \ + echo "\#include " ; \ + $(CPP) $(a_flags) $< | \ + grep "\<___EXPORT_SYMBOL\>" | \ + sed 's/.*___EXPORT_SYMBOL[[:space:]]*\([a-zA-Z0-9_]*\)[[:space:]]*,.*/EXPORT_SYMBOL(\1);/' ; } | \ + $(CPP) -D__GENKSYMS__ $(c_flags) -xc - | \ + scripts/genksyms/genksyms $(if $(1), -T $(2)) \ + $(patsubst y,-R,$(CONFIG_MODULE_REL_CRCS)) \ + $(if $(KBUILD_PRESERVE),-p) \ + -r $(firstword $(wildcard $(2:.symtypes=.symref) /dev/null)) + +quiet_cmd_cc_symtypes_S = SYM $(quiet_modtag) $@ +cmd_cc_symtypes_S = \ + $(call cmd_gensymtypes_S,true,$@) >/dev/null; \ + test -s $@ || rm -f $@ + +$(obj)/%.symtypes : $(src)/%.S FORCE + $(call cmd,cc_symtypes_S) + + +quiet_cmd_cpp_s_S = CPP $(quiet_modtag) $@ +cmd_cpp_s_S = $(CPP) $(a_flags) -o $@ $< + +$(obj)/%.s: $(src)/%.S FORCE + $(call if_changed_dep,cpp_s_S) + +quiet_cmd_as_o_S = AS $(quiet_modtag) $@ + cmd_as_o_S = $(CC) $(a_flags) -c -o $@ $< + +ifdef CONFIG_ASM_MODVERSIONS + +# versioning matches the C process described above, with difference that +# we parse asm-prototypes.h C header to get function definitions. + +cmd_modversions_S = \ + if $(OBJDUMP) -h $@ | grep -q __ksymtab; then \ + $(call cmd_gensymtypes_S,$(KBUILD_SYMTYPES),$(@:.o=.symtypes)) \ + > $(@D)/.tmp_$(@F:.o=.ver); \ + \ + $(LD) $(KBUILD_LDFLAGS) -r -o $(@D)/.tmp_$(@F) $@ \ + -T $(@D)/.tmp_$(@F:.o=.ver); \ + mv -f $(@D)/.tmp_$(@F) $@; \ + rm -f $(@D)/.tmp_$(@F:.o=.ver); \ + fi +endif + +$(obj)/%.o: $(src)/%.S $$(objtool_dep) FORCE + $(call if_changed_rule,as_o_S) + +targets += $(filter-out $(subdir-builtin), $(real-obj-y)) +targets += $(filter-out $(subdir-modorder), $(real-obj-m)) +targets += $(lib-y) $(always-y) $(MAKECMDGOALS) + +# Linker scripts preprocessor (.lds.S -> .lds) +# --------------------------------------------------------------------------- +quiet_cmd_cpp_lds_S = LDS $@ + cmd_cpp_lds_S = $(CPP) $(cpp_flags) -P -U$(ARCH) \ + -D__ASSEMBLY__ -DLINKER_SCRIPT -o $@ $< + +$(obj)/%.lds: $(src)/%.lds.S FORCE + $(call if_changed_dep,cpp_lds_S) + +# ASN.1 grammar +# --------------------------------------------------------------------------- +quiet_cmd_asn1_compiler = ASN.1 $(basename $@).[ch] + cmd_asn1_compiler = $(objtree)/scripts/asn1_compiler $< \ + $(basename $@).c $(basename $@).h + +$(obj)/%.asn1.c $(obj)/%.asn1.h: $(src)/%.asn1 $(objtree)/scripts/asn1_compiler + $(call cmd,asn1_compiler) + +# Build the compiled-in targets +# --------------------------------------------------------------------------- + +# To build objects in subdirs, we need to descend into the directories +$(subdir-builtin): $(obj)/%/built-in.a: $(obj)/% ; +$(subdir-modorder): $(obj)/%/modules.order: $(obj)/% ; + +# +# Rule to compile a set of .o files into one .a file (without symbol table) +# + +quiet_cmd_ar_builtin = AR $@ + cmd_ar_builtin = rm -f $@; $(AR) cDPrST $@ $(real-prereqs) + +$(obj)/built-in.a: $(real-obj-y) FORCE + $(call if_changed,ar_builtin) + +# +# Rule to create modules.order file +# +# Create commands to either record .ko file or cat modules.order from +# a subdirectory +# Add $(obj-m) as the prerequisite to avoid updating the timestamp of +# modules.order unless contained modules are updated. + +cmd_modules_order = { $(foreach m, $(real-prereqs), \ + $(if $(filter %/modules.order, $m), cat $m, echo $(patsubst %.o,%.ko,$m));) :; } \ + | $(AWK) '!x[$$0]++' - > $@ + +$(obj)/modules.order: $(obj-m) FORCE + $(call if_changed,modules_order) + +# +# Rule to compile a set of .o files into one .a file (with symbol table) +# +$(obj)/lib.a: $(lib-y) FORCE + $(call if_changed,ar) + +# NOTE: +# Do not replace $(filter %.o,^) with $(real-prereqs). When a single object +# module is turned into a multi object module, $^ will contain header file +# dependencies recorded in the .*.cmd file. +quiet_cmd_link_multi-m = LD [M] $@ + cmd_link_multi-m = $(LD) $(ld_flags) -r -o $@ $(filter %.o,$^) + +$(multi-used-m): FORCE + $(call if_changed,link_multi-m) +$(call multi_depend, $(multi-used-m), .o, -objs -y -m) + +targets += $(multi-used-m) +targets := $(filter-out $(PHONY), $(targets)) + +# Add intermediate targets: +# When building objects with specific suffix patterns, add intermediate +# targets that the final targets are derived from. +intermediate_targets = $(foreach sfx, $(2), \ + $(patsubst %$(strip $(1)),%$(sfx), \ + $(filter %$(strip $(1)), $(targets)))) +# %.asn1.o <- %.asn1.[ch] <- %.asn1 +# %.dtb.o <- %.dtb.S <- %.dtb <- %.dts +# %.lex.o <- %.lex.c <- %.l +# %.tab.o <- %.tab.[ch] <- %.y +targets += $(call intermediate_targets, .asn1.o, .asn1.c .asn1.h) \ + $(call intermediate_targets, .dtb.o, .dtb.S .dtb) \ + $(call intermediate_targets, .lex.o, .lex.c) \ + $(call intermediate_targets, .tab.o, .tab.c .tab.h) + +# Build +# --------------------------------------------------------------------------- + +ifdef single-build + +KBUILD_SINGLE_TARGETS := $(filter $(obj)/%, $(KBUILD_SINGLE_TARGETS)) + +curdir-single := $(sort $(foreach x, $(KBUILD_SINGLE_TARGETS), \ + $(if $(filter $(x) $(basename $(x)).o, $(targets)), $(x)))) + +# Handle single targets without any rule: show "Nothing to be done for ..." or +# "No rule to make target ..." depending on whether the target exists. +unknown-single := $(filter-out $(addsuffix /%, $(subdir-ym)), \ + $(filter-out $(curdir-single), $(KBUILD_SINGLE_TARGETS))) + +single-subdirs := $(foreach d, $(subdir-ym), \ + $(if $(filter $(d)/%, $(KBUILD_SINGLE_TARGETS)), $(d))) + +__build: $(curdir-single) $(single-subdirs) +ifneq ($(unknown-single),) + $(Q)$(MAKE) -f /dev/null $(unknown-single) +endif + @: + +ifeq ($(curdir-single),) +# Nothing to do in this directory. Do not include any .*.cmd file for speed-up +targets := +else +targets += $(curdir-single) +endif + +else + +__build: $(if $(KBUILD_BUILTIN), $(targets-for-builtin)) \ + $(if $(KBUILD_MODULES), $(targets-for-modules)) \ + $(subdir-ym) $(always-y) + @: + +endif + +# Descending +# --------------------------------------------------------------------------- + +PHONY += $(subdir-ym) +$(subdir-ym): + $(Q)$(MAKE) $(build)=$@ \ + $(if $(filter $@/, $(KBUILD_SINGLE_TARGETS)),single-build=) \ + need-builtin=$(if $(filter $@/built-in.a, $(subdir-builtin)),1) \ + need-modorder=$(if $(filter $@/modules.order, $(subdir-modorder)),1) + +# Add FORCE to the prequisites of a target to force it to be always rebuilt. +# --------------------------------------------------------------------------- + +PHONY += FORCE + +FORCE: + +# Read all saved command lines and dependencies for the $(targets) we +# may be building above, using $(if_changed{,_dep}). As an +# optimization, we don't need to read them if the target does not +# exist, we will rebuild anyway in that case. + +existing-targets := $(wildcard $(sort $(targets))) + +-include $(foreach f,$(existing-targets),$(dir $(f)).$(notdir $(f)).cmd) + +# Create directories for object files if they do not exist +obj-dirs := $(sort $(patsubst %/,%, $(dir $(targets)))) +# If targets exist, their directories apparently exist. Skip mkdir. +existing-dirs := $(sort $(patsubst %/,%, $(dir $(existing-targets)))) +obj-dirs := $(strip $(filter-out $(existing-dirs), $(obj-dirs))) +ifneq ($(obj-dirs),) +$(shell mkdir -p $(obj-dirs)) +endif + +.PHONY: $(PHONY) diff --git a/src/net/scripts/Makefile.clean b/src/net/scripts/Makefile.clean new file mode 100644 index 0000000..d9e0cea --- /dev/null +++ b/src/net/scripts/Makefile.clean @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: GPL-2.0 +# ========================================================================== +# Cleaning up +# ========================================================================== + +src := $(obj) + +PHONY := __clean +__clean: + +include scripts/Kbuild.include + +# The filename Kbuild has precedence over Makefile +kbuild-dir := $(if $(filter /%,$(src)),$(src),$(srctree)/$(src)) +include $(if $(wildcard $(kbuild-dir)/Kbuild), $(kbuild-dir)/Kbuild, $(kbuild-dir)/Makefile) + +# Figure out what we need to build from the various variables +# ========================================================================== + +subdir-ymn := $(sort $(subdir-y) $(subdir-m) $(subdir-) \ + $(patsubst %/,%, $(filter %/, $(obj-y) $(obj-m) $(obj-)))) + +# Add subdir path + +subdir-ymn := $(addprefix $(obj)/,$(subdir-ymn)) + +# build a list of files to remove, usually relative to the current +# directory + +__clean-files := \ + $(clean-files) $(targets) $(hostprogs) $(userprogs) \ + $(extra-y) $(extra-m) $(extra-) \ + $(always-y) $(always-m) $(always-) \ + $(hostprogs-always-y) $(hostprogs-always-m) $(hostprogs-always-) \ + $(userprogs-always-y) $(userprogs-always-m) $(userprogs-always-) + +# deprecated +__clean-files += $(always) $(hostprogs-y) $(hostprogs-m) $(hostprogs-) + +__clean-files := $(filter-out $(no-clean-files), $(__clean-files)) + +# clean-files is given relative to the current directory, unless it +# starts with $(objtree)/ (which means "./", so do not add "./" unless +# you want to delete a file from the toplevel object directory). + +__clean-files := $(wildcard \ + $(addprefix $(obj)/, $(filter-out $(objtree)/%, $(__clean-files))) \ + $(filter $(objtree)/%, $(__clean-files))) + +# ========================================================================== + +quiet_cmd_clean = CLEAN $(obj) + cmd_clean = rm -rf $(__clean-files) + +__clean: $(subdir-ymn) +ifneq ($(strip $(__clean-files)),) + $(call cmd,clean) +endif + @: + + +# =========================================================================== +# Generic stuff +# =========================================================================== + +# Descending +# --------------------------------------------------------------------------- + +PHONY += $(subdir-ymn) +$(subdir-ymn): + $(Q)$(MAKE) $(clean)=$@ + +.PHONY: $(PHONY) diff --git a/src/net/scripts/Makefile.dtbinst b/src/net/scripts/Makefile.dtbinst new file mode 100644 index 0000000..50d580d --- /dev/null +++ b/src/net/scripts/Makefile.dtbinst @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: GPL-2.0 +# ========================================================================== +# Installing dtb files +# +# Installs all dtb files listed in $(dtb-y) either in the +# INSTALL_DTBS_PATH directory or the default location: +# +# $INSTALL_PATH/dtbs/$KERNELRELEASE +# ========================================================================== + +src := $(obj) + +PHONY := __dtbs_install +__dtbs_install: + +include include/config/auto.conf +include scripts/Kbuild.include +include $(src)/Makefile + +dtbs := $(addprefix $(dst)/, $(dtb-y) $(if $(CONFIG_OF_ALL_DTBS),$(dtb-))) +subdirs := $(addprefix $(obj)/, $(subdir-y) $(subdir-m)) + +__dtbs_install: $(dtbs) $(subdirs) + @: + +quiet_cmd_dtb_install = INSTALL $@ + cmd_dtb_install = install -D $< $@ + +$(dst)/%.dtb: $(obj)/%.dtb + $(call cmd,dtb_install) + +PHONY += $(subdirs) +$(subdirs): + $(Q)$(MAKE) $(dtbinst)=$@ dst=$(patsubst $(obj)/%,$(dst)/%,$@) + +.PHONY: $(PHONY) diff --git a/src/net/scripts/Makefile.extrawarn b/src/net/scripts/Makefile.extrawarn new file mode 100644 index 0000000..23d3967 --- /dev/null +++ b/src/net/scripts/Makefile.extrawarn @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: GPL-2.0 +# ========================================================================== +# make W=... settings +# +# There are three warning groups enabled by W=1, W=2, W=3. +# They are independent, and can be combined like W=12 or W=123. +# ========================================================================== + +KBUILD_CFLAGS += $(call cc-disable-warning, packed-not-aligned) + +# backward compatibility +KBUILD_EXTRA_WARN ?= $(KBUILD_ENABLE_EXTRA_GCC_CHECKS) + +ifeq ("$(origin W)", "command line") + KBUILD_EXTRA_WARN := $(W) +endif + +export KBUILD_EXTRA_WARN + +# +# W=1 - warnings which may be relevant and do not occur too often +# +ifneq ($(findstring 1, $(KBUILD_EXTRA_WARN)),) + +KBUILD_CFLAGS += -Wextra -Wunused -Wno-unused-parameter +KBUILD_CFLAGS += -Wmissing-declarations +KBUILD_CFLAGS += -Wmissing-format-attribute +KBUILD_CFLAGS += -Wmissing-prototypes +KBUILD_CFLAGS += -Wold-style-definition +KBUILD_CFLAGS += -Wmissing-include-dirs +KBUILD_CFLAGS += $(call cc-option, -Wunused-but-set-variable) +KBUILD_CFLAGS += $(call cc-option, -Wunused-const-variable) +KBUILD_CFLAGS += $(call cc-option, -Wpacked-not-aligned) +KBUILD_CFLAGS += $(call cc-option, -Wstringop-truncation) +# The following turn off the warnings enabled by -Wextra +KBUILD_CFLAGS += -Wno-missing-field-initializers +KBUILD_CFLAGS += -Wno-sign-compare +KBUILD_CFLAGS += -Wno-type-limits + +KBUILD_CPPFLAGS += -DKBUILD_EXTRA_WARN1 + +else + +# Some diagnostics enabled by default are noisy. +# Suppress them by using -Wno... except for W=1. + +ifdef CONFIG_CC_IS_CLANG +KBUILD_CFLAGS += -Wno-initializer-overrides +KBUILD_CFLAGS += -Wno-format +KBUILD_CFLAGS += -Wno-sign-compare +KBUILD_CFLAGS += -Wno-format-zero-length +KBUILD_CFLAGS += $(call cc-disable-warning, pointer-to-enum-cast) +KBUILD_CFLAGS += -Wno-tautological-constant-out-of-range-compare +KBUILD_CFLAGS += $(call cc-disable-warning, unaligned-access) +endif + +endif + +# +# W=2 - warnings which occur quite often but may still be relevant +# +ifneq ($(findstring 2, $(KBUILD_EXTRA_WARN)),) + +KBUILD_CFLAGS += -Wdisabled-optimization +KBUILD_CFLAGS += -Wnested-externs +KBUILD_CFLAGS += -Wshadow +KBUILD_CFLAGS += $(call cc-option, -Wlogical-op) +KBUILD_CFLAGS += -Wmissing-field-initializers +KBUILD_CFLAGS += -Wtype-limits +KBUILD_CFLAGS += $(call cc-option, -Wmaybe-uninitialized) +KBUILD_CFLAGS += $(call cc-option, -Wunused-macros) + +KBUILD_CPPFLAGS += -DKBUILD_EXTRA_WARN2 + +endif + +# +# W=3 - more obscure warnings, can most likely be ignored +# +ifneq ($(findstring 3, $(KBUILD_EXTRA_WARN)),) + +KBUILD_CFLAGS += -Wbad-function-cast +KBUILD_CFLAGS += -Wcast-align +KBUILD_CFLAGS += -Wcast-qual +KBUILD_CFLAGS += -Wconversion +KBUILD_CFLAGS += -Wpacked +KBUILD_CFLAGS += -Wpadded +KBUILD_CFLAGS += -Wpointer-arith +KBUILD_CFLAGS += -Wredundant-decls +KBUILD_CFLAGS += -Wsign-compare +KBUILD_CFLAGS += -Wswitch-default +KBUILD_CFLAGS += $(call cc-option, -Wpacked-bitfield-compat) + +KBUILD_CPPFLAGS += -DKBUILD_EXTRA_WARN3 + +endif diff --git a/src/net/scripts/Makefile.gcc-plugins b/src/net/scripts/Makefile.gcc-plugins new file mode 100644 index 0000000..4aad284 --- /dev/null +++ b/src/net/scripts/Makefile.gcc-plugins @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: GPL-2.0 + +gcc-plugin-$(CONFIG_GCC_PLUGIN_CYC_COMPLEXITY) += cyc_complexity_plugin.so + +gcc-plugin-$(CONFIG_GCC_PLUGIN_LATENT_ENTROPY) += latent_entropy_plugin.so +gcc-plugin-cflags-$(CONFIG_GCC_PLUGIN_LATENT_ENTROPY) \ + += -DLATENT_ENTROPY_PLUGIN +ifdef CONFIG_GCC_PLUGIN_LATENT_ENTROPY + DISABLE_LATENT_ENTROPY_PLUGIN += -fplugin-arg-latent_entropy_plugin-disable +endif +export DISABLE_LATENT_ENTROPY_PLUGIN + +gcc-plugin-$(CONFIG_GCC_PLUGIN_SANCOV) += sancov_plugin.so + +gcc-plugin-$(CONFIG_GCC_PLUGIN_STRUCTLEAK) += structleak_plugin.so +gcc-plugin-cflags-$(CONFIG_GCC_PLUGIN_STRUCTLEAK_VERBOSE) \ + += -fplugin-arg-structleak_plugin-verbose +gcc-plugin-cflags-$(CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF) \ + += -fplugin-arg-structleak_plugin-byref +gcc-plugin-cflags-$(CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF_ALL) \ + += -fplugin-arg-structleak_plugin-byref-all +ifdef CONFIG_GCC_PLUGIN_STRUCTLEAK + DISABLE_STRUCTLEAK_PLUGIN += -fplugin-arg-structleak_plugin-disable +endif +export DISABLE_STRUCTLEAK_PLUGIN +gcc-plugin-cflags-$(CONFIG_GCC_PLUGIN_STRUCTLEAK) \ + += -DSTRUCTLEAK_PLUGIN + +gcc-plugin-$(CONFIG_GCC_PLUGIN_RANDSTRUCT) += randomize_layout_plugin.so +gcc-plugin-cflags-$(CONFIG_GCC_PLUGIN_RANDSTRUCT) \ + += -DRANDSTRUCT_PLUGIN +gcc-plugin-cflags-$(CONFIG_GCC_PLUGIN_RANDSTRUCT_PERFORMANCE) \ + += -fplugin-arg-randomize_layout_plugin-performance-mode + +gcc-plugin-$(CONFIG_GCC_PLUGIN_STACKLEAK) += stackleak_plugin.so +gcc-plugin-cflags-$(CONFIG_GCC_PLUGIN_STACKLEAK) \ + += -DSTACKLEAK_PLUGIN +gcc-plugin-cflags-$(CONFIG_GCC_PLUGIN_STACKLEAK) \ + += -fplugin-arg-stackleak_plugin-track-min-size=$(CONFIG_STACKLEAK_TRACK_MIN_SIZE) +gcc-plugin-cflags-$(CONFIG_GCC_PLUGIN_STACKLEAK) \ + += -fplugin-arg-stackleak_plugin-arch=$(SRCARCH) +ifdef CONFIG_GCC_PLUGIN_STACKLEAK + DISABLE_STACKLEAK_PLUGIN += -fplugin-arg-stackleak_plugin-disable +endif +export DISABLE_STACKLEAK_PLUGIN + +gcc-plugin-$(CONFIG_GCC_PLUGIN_ARM_SSP_PER_TASK) += arm_ssp_per_task_plugin.so +ifdef CONFIG_GCC_PLUGIN_ARM_SSP_PER_TASK + DISABLE_ARM_SSP_PER_TASK_PLUGIN += -fplugin-arg-arm_ssp_per_task_plugin-disable +endif +export DISABLE_ARM_SSP_PER_TASK_PLUGIN + +# All the plugin CFLAGS are collected here in case a build target needs to +# filter them out of the KBUILD_CFLAGS. +GCC_PLUGINS_CFLAGS := $(strip $(addprefix -fplugin=$(objtree)/scripts/gcc-plugins/, $(gcc-plugin-y)) $(gcc-plugin-cflags-y)) +# The sancov_plugin.so is included via CFLAGS_KCOV, so it is removed here. +GCC_PLUGINS_CFLAGS := $(filter-out %/sancov_plugin.so, $(GCC_PLUGINS_CFLAGS)) +export GCC_PLUGINS_CFLAGS + +# Add the flags to the build! +KBUILD_CFLAGS += $(GCC_PLUGINS_CFLAGS) + +# All enabled GCC plugins are collected here for building below. +GCC_PLUGIN := $(gcc-plugin-y) +export GCC_PLUGIN diff --git a/src/net/scripts/Makefile.headersinst b/src/net/scripts/Makefile.headersinst new file mode 100644 index 0000000..708fbd0 --- /dev/null +++ b/src/net/scripts/Makefile.headersinst @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: GPL-2.0 +# ========================================================================== +# Installing headers +# +# All headers under include/uapi, include/generated/uapi, +# arch//include/uapi and arch//include/generated/uapi are +# exported. +# They are preprocessed to remove __KERNEL__ section of the file. +# +# ========================================================================== + +PHONY := __headers +__headers: + +include scripts/Kbuild.include + +src := $(srctree)/$(obj) +gen := $(objtree)/$(subst include/,include/generated/,$(obj)) +dst := usr/include + +-include $(src)/Kbuild + +# $(filter %/, ...) is a workaround for GNU Make <= 4.2.1, where +# $(wildcard $(src)/*/) contains not only directories but also regular files. +src-subdirs := $(patsubst $(src)/%/,%,$(filter %/, $(wildcard $(src)/*/))) +gen-subdirs := $(patsubst $(gen)/%/,%,$(filter %/, $(wildcard $(gen)/*/))) +all-subdirs := $(sort $(src-subdirs) $(gen-subdirs)) + +src-headers := $(if $(src-subdirs), $(shell cd $(src) && find $(src-subdirs) -name '*.h')) +src-headers := $(filter-out $(no-export-headers), $(src-headers)) +gen-headers := $(if $(gen-subdirs), $(shell cd $(gen) && find $(gen-subdirs) -name '*.h')) +gen-headers := $(filter-out $(no-export-headers), $(gen-headers)) + +# If the same header is exported from source and generated directories, +# the former takes precedence, but this should be warned. +duplicated := $(filter $(gen-headers), $(src-headers)) +$(if $(duplicated), $(warning duplicated header export: $(duplicated))) + +gen-headers := $(filter-out $(duplicated), $(gen-headers)) + +# Add dst path prefix +all-subdirs := $(addprefix $(dst)/, $(all-subdirs)) +src-headers := $(addprefix $(dst)/, $(src-headers)) +gen-headers := $(addprefix $(dst)/, $(gen-headers)) +all-headers := $(src-headers) $(gen-headers) + +# Work out what needs to be removed +old-subdirs := $(wildcard $(all-subdirs)) +old-headers := $(if $(old-subdirs),$(shell find $(old-subdirs) -name '*.h')) +unwanted := $(filter-out $(all-headers), $(old-headers)) + +# Create directories +existing-dirs := $(sort $(dir $(old-headers))) +wanted-dirs := $(sort $(dir $(all-headers))) +new-dirs := $(filter-out $(existing-dirs), $(wanted-dirs)) +$(if $(new-dirs), $(shell mkdir -p $(new-dirs))) + +# Rules +quiet_cmd_install = HDRINST $@ + cmd_install = $(CONFIG_SHELL) $(srctree)/scripts/headers_install.sh $< $@ + +$(src-headers): $(dst)/%.h: $(src)/%.h $(srctree)/scripts/headers_install.sh FORCE + $(call if_changed,install) + +$(gen-headers): $(dst)/%.h: $(gen)/%.h $(srctree)/scripts/headers_install.sh FORCE + $(call if_changed,install) + +quiet_cmd_remove = REMOVE $(unwanted) + cmd_remove = rm -f $(unwanted) + +__headers: $(all-headers) +ifneq ($(unwanted),) + $(call cmd,remove) +endif + @: + +existing-headers := $(filter $(old-headers), $(all-headers)) + +-include $(foreach f,$(existing-headers),$(dir $(f)).$(notdir $(f)).cmd) + +PHONY += FORCE +FORCE: + +.PHONY: $(PHONY) diff --git a/src/net/scripts/Makefile.host b/src/net/scripts/Makefile.host new file mode 100644 index 0000000..278b4d6 --- /dev/null +++ b/src/net/scripts/Makefile.host @@ -0,0 +1,132 @@ +# SPDX-License-Identifier: GPL-2.0 + +# LEX +# --------------------------------------------------------------------------- +quiet_cmd_flex = LEX $@ + cmd_flex = $(LEX) -o$@ -L $< + +$(obj)/%.lex.c: $(src)/%.l FORCE + $(call if_changed,flex) + +# YACC +# --------------------------------------------------------------------------- +quiet_cmd_bison = YACC $(basename $@).[ch] + cmd_bison = $(YACC) -o $(basename $@).c --defines=$(basename $@).h -t -l $< + +$(obj)/%.tab.c $(obj)/%.tab.h: $(src)/%.y FORCE + $(call if_changed,bison) + +# ========================================================================== +# Building binaries on the host system +# Binaries are used during the compilation of the kernel, for example +# to preprocess a data file. +# +# Both C and C++ are supported, but preferred language is C for such utilities. +# +# Sample syntax (see Documentation/kbuild/makefiles.rst for reference) +# hostprogs := bin2hex +# Will compile bin2hex.c and create an executable named bin2hex +# +# hostprogs := lxdialog +# lxdialog-objs := checklist.o lxdialog.o +# Will compile lxdialog.c and checklist.c, and then link the executable +# lxdialog, based on checklist.o and lxdialog.o +# +# hostprogs := qconf +# qconf-cxxobjs := qconf.o +# qconf-objs := menu.o +# Will compile qconf as a C++ program, and menu as a C program. +# They are linked as C++ code to the executable qconf + +# C code +# Executables compiled from a single .c file +host-csingle := $(foreach m,$(hostprogs), \ + $(if $($(m)-objs)$($(m)-cxxobjs),,$(m))) + +# C executables linked based on several .o files +host-cmulti := $(foreach m,$(hostprogs),\ + $(if $($(m)-cxxobjs),,$(if $($(m)-objs),$(m)))) + +# Object (.o) files compiled from .c files +host-cobjs := $(sort $(foreach m,$(hostprogs),$($(m)-objs))) + +# C++ code +# C++ executables compiled from at least one .cc file +# and zero or more .c files +host-cxxmulti := $(foreach m,$(hostprogs),$(if $($(m)-cxxobjs),$(m))) + +# C++ Object (.o) files compiled from .cc files +host-cxxobjs := $(sort $(foreach m,$(host-cxxmulti),$($(m)-cxxobjs))) + +host-csingle := $(addprefix $(obj)/,$(host-csingle)) +host-cmulti := $(addprefix $(obj)/,$(host-cmulti)) +host-cobjs := $(addprefix $(obj)/,$(host-cobjs)) +host-cxxmulti := $(addprefix $(obj)/,$(host-cxxmulti)) +host-cxxobjs := $(addprefix $(obj)/,$(host-cxxobjs)) + +##### +# Handle options to gcc. Support building with separate output directory + +_hostc_flags = $(KBUILD_HOSTCFLAGS) $(HOST_EXTRACFLAGS) \ + $(HOSTCFLAGS_$(target-stem).o) +_hostcxx_flags = $(KBUILD_HOSTCXXFLAGS) $(HOST_EXTRACXXFLAGS) \ + $(HOSTCXXFLAGS_$(target-stem).o) + +# $(objtree)/$(obj) for including generated headers from checkin source files +ifeq ($(KBUILD_EXTMOD),) +ifdef building_out_of_srctree +_hostc_flags += -I $(objtree)/$(obj) +_hostcxx_flags += -I $(objtree)/$(obj) +endif +endif + +hostc_flags = -Wp,-MMD,$(depfile) $(_hostc_flags) +hostcxx_flags = -Wp,-MMD,$(depfile) $(_hostcxx_flags) + +##### +# Compile programs on the host + +# Create executable from a single .c file +# host-csingle -> Executable +quiet_cmd_host-csingle = HOSTCC $@ + cmd_host-csingle = $(HOSTCC) $(hostc_flags) $(KBUILD_HOSTLDFLAGS) -o $@ $< \ + $(KBUILD_HOSTLDLIBS) $(HOSTLDLIBS_$(target-stem)) +$(host-csingle): $(obj)/%: $(src)/%.c FORCE + $(call if_changed_dep,host-csingle) + +# Link an executable based on list of .o files, all plain c +# host-cmulti -> executable +quiet_cmd_host-cmulti = HOSTLD $@ + cmd_host-cmulti = $(HOSTCC) $(KBUILD_HOSTLDFLAGS) -o $@ \ + $(addprefix $(obj)/, $($(target-stem)-objs)) \ + $(KBUILD_HOSTLDLIBS) $(HOSTLDLIBS_$(target-stem)) +$(host-cmulti): FORCE + $(call if_changed,host-cmulti) +$(call multi_depend, $(host-cmulti), , -objs) + +# Create .o file from a single .c file +# host-cobjs -> .o +quiet_cmd_host-cobjs = HOSTCC $@ + cmd_host-cobjs = $(HOSTCC) $(hostc_flags) -c -o $@ $< +$(host-cobjs): $(obj)/%.o: $(src)/%.c FORCE + $(call if_changed_dep,host-cobjs) + +# Link an executable based on list of .o files, a mixture of .c and .cc +# host-cxxmulti -> executable +quiet_cmd_host-cxxmulti = HOSTLD $@ + cmd_host-cxxmulti = $(HOSTCXX) $(KBUILD_HOSTLDFLAGS) -o $@ \ + $(foreach o,objs cxxobjs,\ + $(addprefix $(obj)/, $($(target-stem)-$(o)))) \ + $(KBUILD_HOSTLDLIBS) $(HOSTLDLIBS_$(target-stem)) +$(host-cxxmulti): FORCE + $(call if_changed,host-cxxmulti) +$(call multi_depend, $(host-cxxmulti), , -objs -cxxobjs) + +# Create .o file from a single .cc (C++) file +quiet_cmd_host-cxxobjs = HOSTCXX $@ + cmd_host-cxxobjs = $(HOSTCXX) $(hostcxx_flags) -c -o $@ $< +$(host-cxxobjs): $(obj)/%.o: $(src)/%.cc FORCE + $(call if_changed_dep,host-cxxobjs) + +targets += $(host-csingle) $(host-cmulti) $(host-cobjs) \ + $(host-cxxmulti) $(host-cxxobjs) diff --git a/src/net/scripts/Makefile.kasan b/src/net/scripts/Makefile.kasan new file mode 100644 index 0000000..127012f --- /dev/null +++ b/src/net/scripts/Makefile.kasan @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: GPL-2.0 +CFLAGS_KASAN_NOSANITIZE := -fno-builtin +KASAN_SHADOW_OFFSET ?= $(CONFIG_KASAN_SHADOW_OFFSET) + +cc-param = $(call cc-option, -mllvm -$(1), $(call cc-option, --param $(1))) + +ifdef CONFIG_KASAN_GENERIC + +ifdef CONFIG_KASAN_INLINE + call_threshold := 10000 +else + call_threshold := 0 +endif + +CFLAGS_KASAN_MINIMAL := -fsanitize=kernel-address + +# -fasan-shadow-offset fails without -fsanitize +CFLAGS_KASAN_SHADOW := $(call cc-option, -fsanitize=kernel-address \ + -fasan-shadow-offset=$(KASAN_SHADOW_OFFSET), \ + $(call cc-option, -fsanitize=kernel-address \ + -mllvm -asan-mapping-offset=$(KASAN_SHADOW_OFFSET))) + +ifeq ($(strip $(CFLAGS_KASAN_SHADOW)),) + CFLAGS_KASAN := $(CFLAGS_KASAN_MINIMAL) +else + # Now add all the compiler specific options that are valid standalone + CFLAGS_KASAN := $(CFLAGS_KASAN_SHADOW) \ + $(call cc-param,asan-globals=1) \ + $(call cc-param,asan-instrumentation-with-call-threshold=$(call_threshold)) \ + $(call cc-param,asan-stack=$(CONFIG_KASAN_STACK)) \ + $(call cc-param,asan-instrument-allocas=1) +endif + +endif # CONFIG_KASAN_GENERIC + +ifdef CONFIG_KASAN_SW_TAGS + +ifdef CONFIG_KASAN_INLINE + instrumentation_flags := $(call cc-param,hwasan-mapping-offset=$(KASAN_SHADOW_OFFSET)) +else + instrumentation_flags := $(call cc-param,hwasan-instrument-with-calls=1) +endif + +CFLAGS_KASAN := -fsanitize=kernel-hwaddress \ + $(call cc-param,hwasan-instrument-stack=$(CONFIG_KASAN_STACK)) \ + $(call cc-param,hwasan-use-short-granules=0) \ + $(instrumentation_flags) + +endif # CONFIG_KASAN_SW_TAGS + +export CFLAGS_KASAN CFLAGS_KASAN_NOSANITIZE diff --git a/src/net/scripts/Makefile.kcov b/src/net/scripts/Makefile.kcov new file mode 100644 index 0000000..67e8cfe --- /dev/null +++ b/src/net/scripts/Makefile.kcov @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-only +kcov-flags-$(CONFIG_CC_HAS_SANCOV_TRACE_PC) += -fsanitize-coverage=trace-pc +kcov-flags-$(CONFIG_KCOV_ENABLE_COMPARISONS) += -fsanitize-coverage=trace-cmp +kcov-flags-$(CONFIG_GCC_PLUGIN_SANCOV) += -fplugin=$(objtree)/scripts/gcc-plugins/sancov_plugin.so + +export CFLAGS_KCOV := $(kcov-flags-y) diff --git a/src/net/scripts/Makefile.kcsan b/src/net/scripts/Makefile.kcsan new file mode 100644 index 0000000..37cb504 --- /dev/null +++ b/src/net/scripts/Makefile.kcsan @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0 +# GCC and Clang accept backend options differently. Do not wrap in cc-option, +# because Clang accepts "--param" even if it is unused. +ifdef CONFIG_CC_IS_CLANG +cc-param = -mllvm -$(1) +else +cc-param = --param $(1) +endif + +# Keep most options here optional, to allow enabling more compilers if absence +# of some options does not break KCSAN nor causes false positive reports. +export CFLAGS_KCSAN := -fsanitize=thread \ + $(call cc-option,$(call cc-param,tsan-instrument-func-entry-exit=0) -fno-optimize-sibling-calls) \ + $(call cc-option,$(call cc-param,tsan-compound-read-before-write=1),$(call cc-option,$(call cc-param,tsan-instrument-read-before-write=1))) \ + $(call cc-param,tsan-distinguish-volatile=1) diff --git a/src/net/scripts/Makefile.lib b/src/net/scripts/Makefile.lib new file mode 100644 index 0000000..9413370 --- /dev/null +++ b/src/net/scripts/Makefile.lib @@ -0,0 +1,478 @@ +# SPDX-License-Identifier: GPL-2.0 +# Backward compatibility +asflags-y += $(EXTRA_AFLAGS) +ccflags-y += $(EXTRA_CFLAGS) +cppflags-y += $(EXTRA_CPPFLAGS) +ldflags-y += $(EXTRA_LDFLAGS) +ifneq ($(always),) +$(warning 'always' is deprecated. Please use 'always-y' instead) +always-y += $(always) +endif +ifneq ($(hostprogs-y),) +$(warning 'hostprogs-y' is deprecated. Please use 'hostprogs' instead) +hostprogs += $(hostprogs-y) +endif +ifneq ($(hostprogs-m),) +$(warning 'hostprogs-m' is deprecated. Please use 'hostprogs' instead) +hostprogs += $(hostprogs-m) +endif + +# flags that take effect in current and sub directories +KBUILD_AFLAGS += $(subdir-asflags-y) +KBUILD_CFLAGS += $(subdir-ccflags-y) + +# Figure out what we need to build from the various variables +# =========================================================================== + +# When an object is listed to be built compiled-in and modular, +# only build the compiled-in version +obj-m := $(filter-out $(obj-y),$(obj-m)) + +# Libraries are always collected in one lib file. +# Filter out objects already built-in +lib-y := $(filter-out $(obj-y), $(sort $(lib-y) $(lib-m))) + +# Subdirectories we need to descend into +subdir-ym := $(sort $(subdir-y) $(subdir-m) \ + $(patsubst %/,%, $(filter %/, $(obj-y) $(obj-m)))) + +# Handle objects in subdirs: +# - If we encounter foo/ in $(obj-y), replace it by foo/built-in.a and +# foo/modules.order +# - If we encounter foo/ in $(obj-m), replace it by foo/modules.order +# +# Generate modules.order to determine modorder. Unfortunately, we don't have +# information about ordering between -y and -m subdirs. Just put -y's first. + +ifdef need-modorder +obj-m := $(patsubst %/,%/modules.order, $(filter %/, $(obj-y)) $(obj-m)) +else +obj-m := $(filter-out %/, $(obj-m)) +endif + +ifdef need-builtin +obj-y := $(patsubst %/, %/built-in.a, $(obj-y)) +else +obj-y := $(filter-out %/, $(obj-y)) +endif + +# If $(foo-objs), $(foo-y), $(foo-m), or $(foo-) exists, foo.o is a composite object +multi-used-y := $(sort $(foreach m,$(obj-y), $(if $(strip $($(m:.o=-objs)) $($(m:.o=-y)) $($(m:.o=-))), $(m)))) +multi-used-m := $(sort $(foreach m,$(obj-m), $(if $(strip $($(m:.o=-objs)) $($(m:.o=-y)) $($(m:.o=-m)) $($(m:.o=-))), $(m)))) +multi-used := $(multi-used-y) $(multi-used-m) + +# Replace multi-part objects by their individual parts, +# including built-in.a from subdirectories +real-obj-y := $(foreach m, $(obj-y), $(if $(strip $($(m:.o=-objs)) $($(m:.o=-y)) $($(m:.o=-))),$($(m:.o=-objs)) $($(m:.o=-y)),$(m))) +real-obj-m := $(foreach m, $(obj-m), $(if $(strip $($(m:.o=-objs)) $($(m:.o=-y)) $($(m:.o=-m)) $($(m:.o=-))),$($(m:.o=-objs)) $($(m:.o=-y)) $($(m:.o=-m)),$(m))) + +always-y += $(always-m) + +# hostprogs-always-y += foo +# ... is a shorthand for +# hostprogs += foo +# always-y += foo +hostprogs += $(hostprogs-always-y) $(hostprogs-always-m) +always-y += $(hostprogs-always-y) $(hostprogs-always-m) + +# userprogs-always-y is likewise. +userprogs += $(userprogs-always-y) $(userprogs-always-m) +always-y += $(userprogs-always-y) $(userprogs-always-m) + +# DTB +# If CONFIG_OF_ALL_DTBS is enabled, all DT blobs are built +extra-y += $(dtb-y) +extra-$(CONFIG_OF_ALL_DTBS) += $(dtb-) + +ifneq ($(CHECK_DTBS),) +extra-y += $(patsubst %.dtb,%.dt.yaml, $(dtb-y)) +extra-$(CONFIG_OF_ALL_DTBS) += $(patsubst %.dtb,%.dt.yaml, $(dtb-)) +endif + +# Add subdir path + +extra-y := $(addprefix $(obj)/,$(extra-y)) +always-y := $(addprefix $(obj)/,$(always-y)) +targets := $(addprefix $(obj)/,$(targets)) +obj-m := $(addprefix $(obj)/,$(obj-m)) +lib-y := $(addprefix $(obj)/,$(lib-y)) +real-obj-y := $(addprefix $(obj)/,$(real-obj-y)) +real-obj-m := $(addprefix $(obj)/,$(real-obj-m)) +multi-used-m := $(addprefix $(obj)/,$(multi-used-m)) +subdir-ym := $(addprefix $(obj)/,$(subdir-ym)) + +# Finds the multi-part object the current object will be linked into. +# If the object belongs to two or more multi-part objects, list them all. +modname-multi = $(sort $(foreach m,$(multi-used),\ + $(if $(filter $*.o, $($(m:.o=-objs)) $($(m:.o=-y)) $($(m:.o=-m))),$(m:.o=)))) + +__modname = $(if $(modname-multi),$(modname-multi),$(basetarget)) + +modname = $(subst $(space),:,$(__modname)) +modfile = $(addprefix $(obj)/,$(__modname)) + +# target with $(obj)/ and its suffix stripped +target-stem = $(basename $(patsubst $(obj)/%,%,$@)) + +# These flags are needed for modversions and compiling, so we define them here +# $(modname_flags) defines KBUILD_MODNAME as the name of the module it will +# end up in (or would, if it gets compiled in) +name-fix = $(call stringify,$(subst $(comma),_,$(subst -,_,$1))) +basename_flags = -DKBUILD_BASENAME=$(call name-fix,$(basetarget)) +modname_flags = -DKBUILD_MODNAME=$(call name-fix,$(modname)) +modfile_flags = -DKBUILD_MODFILE=$(call stringify,$(modfile)) + +_c_flags = $(filter-out $(CFLAGS_REMOVE_$(target-stem).o), \ + $(filter-out $(ccflags-remove-y), \ + $(KBUILD_CPPFLAGS) $(KBUILD_CFLAGS) $(ccflags-y)) \ + $(CFLAGS_$(target-stem).o)) +_a_flags = $(filter-out $(AFLAGS_REMOVE_$(target-stem).o), \ + $(filter-out $(asflags-remove-y), \ + $(KBUILD_CPPFLAGS) $(KBUILD_AFLAGS) $(asflags-y)) \ + $(AFLAGS_$(target-stem).o)) +_cpp_flags = $(KBUILD_CPPFLAGS) $(cppflags-y) $(CPPFLAGS_$(target-stem).lds) + +# +# Enable gcov profiling flags for a file, directory or for all files depending +# on variables GCOV_PROFILE_obj.o, GCOV_PROFILE and CONFIG_GCOV_PROFILE_ALL +# (in this order) +# +ifeq ($(CONFIG_GCOV_KERNEL),y) +_c_flags += $(if $(patsubst n%,, \ + $(GCOV_PROFILE_$(basetarget).o)$(GCOV_PROFILE)$(CONFIG_GCOV_PROFILE_ALL)), \ + $(CFLAGS_GCOV)) +endif + +# +# Enable address sanitizer flags for kernel except some files or directories +# we don't want to check (depends on variables KASAN_SANITIZE_obj.o, KASAN_SANITIZE) +# +ifeq ($(CONFIG_KASAN),y) +_c_flags += $(if $(patsubst n%,, \ + $(KASAN_SANITIZE_$(basetarget).o)$(KASAN_SANITIZE)y), \ + $(CFLAGS_KASAN), $(CFLAGS_KASAN_NOSANITIZE)) +endif + +ifeq ($(CONFIG_UBSAN),y) +_c_flags += $(if $(patsubst n%,, \ + $(UBSAN_SANITIZE_$(basetarget).o)$(UBSAN_SANITIZE)$(CONFIG_UBSAN_SANITIZE_ALL)), \ + $(CFLAGS_UBSAN)) +endif + +ifeq ($(CONFIG_KCOV),y) +_c_flags += $(if $(patsubst n%,, \ + $(KCOV_INSTRUMENT_$(basetarget).o)$(KCOV_INSTRUMENT)$(CONFIG_KCOV_INSTRUMENT_ALL)), \ + $(CFLAGS_KCOV)) +endif + +# +# Enable KCSAN flags except some files or directories we don't want to check +# (depends on variables KCSAN_SANITIZE_obj.o, KCSAN_SANITIZE) +# +ifeq ($(CONFIG_KCSAN),y) +_c_flags += $(if $(patsubst n%,, \ + $(KCSAN_SANITIZE_$(basetarget).o)$(KCSAN_SANITIZE)y), \ + $(CFLAGS_KCSAN)) +endif + +# $(srctree)/$(src) for including checkin headers from generated source files +# $(objtree)/$(obj) for including generated headers from checkin source files +ifeq ($(KBUILD_EXTMOD),) +ifdef building_out_of_srctree +_c_flags += -I $(srctree)/$(src) -I $(objtree)/$(obj) +_a_flags += -I $(srctree)/$(src) -I $(objtree)/$(obj) +_cpp_flags += -I $(srctree)/$(src) -I $(objtree)/$(obj) +endif +endif + +part-of-module = $(if $(filter $(basename $@).o, $(real-obj-m)),y) +quiet_modtag = $(if $(part-of-module),[M], ) + +modkern_cflags = \ + $(if $(part-of-module), \ + $(KBUILD_CFLAGS_MODULE) $(CFLAGS_MODULE), \ + $(KBUILD_CFLAGS_KERNEL) $(CFLAGS_KERNEL) $(modfile_flags)) + +modkern_aflags = $(if $(part-of-module), \ + $(KBUILD_AFLAGS_MODULE) $(AFLAGS_MODULE), \ + $(KBUILD_AFLAGS_KERNEL) $(AFLAGS_KERNEL)) + +c_flags = -Wp,-MMD,$(depfile) $(NOSTDINC_FLAGS) $(LINUXINCLUDE) \ + -include $(srctree)/include/linux/compiler_types.h \ + $(_c_flags) $(modkern_cflags) \ + $(basename_flags) $(modname_flags) + +a_flags = -Wp,-MMD,$(depfile) $(NOSTDINC_FLAGS) $(LINUXINCLUDE) \ + $(_a_flags) $(modkern_aflags) + +cpp_flags = -Wp,-MMD,$(depfile) $(NOSTDINC_FLAGS) $(LINUXINCLUDE) \ + $(_cpp_flags) + +ld_flags = $(KBUILD_LDFLAGS) $(ldflags-y) $(LDFLAGS_$(@F)) + +DTC_INCLUDE := $(srctree)/scripts/dtc/include-prefixes + +dtc_cpp_flags = -Wp,-MMD,$(depfile).pre.tmp -nostdinc \ + $(addprefix -I,$(DTC_INCLUDE)) \ + -undef -D__DTS__ + +# Useful for describing the dependency of composite objects +# Usage: +# $(call multi_depend, multi_used_targets, suffix_to_remove, suffix_to_add) +define multi_depend +$(foreach m, $(notdir $1), \ + $(eval $(obj)/$m: \ + $(addprefix $(obj)/, $(foreach s, $3, $($(m:%$(strip $2)=%$(s))))))) +endef + +quiet_cmd_copy = COPY $@ + cmd_copy = cp $< $@ + +# Shipped files +# =========================================================================== + +quiet_cmd_shipped = SHIPPED $@ +cmd_shipped = cat $< > $@ + +$(obj)/%: $(src)/%_shipped + $(call cmd,shipped) + +# Commands useful for building a boot image +# =========================================================================== +# +# Use as following: +# +# target: source(s) FORCE +# $(if_changed,ld/objcopy/gzip) +# +# and add target to extra-y so that we know we have to +# read in the saved command line + +# Linking +# --------------------------------------------------------------------------- + +quiet_cmd_ld = LD $@ + cmd_ld = $(LD) $(ld_flags) $(real-prereqs) -o $@ + +# Archive +# --------------------------------------------------------------------------- + +quiet_cmd_ar = AR $@ + cmd_ar = rm -f $@; $(AR) cDPrsT $@ $(real-prereqs) + +# Objcopy +# --------------------------------------------------------------------------- + +quiet_cmd_objcopy = OBJCOPY $@ +cmd_objcopy = $(OBJCOPY) $(OBJCOPYFLAGS) $(OBJCOPYFLAGS_$(@F)) $< $@ + +# Gzip +# --------------------------------------------------------------------------- + +quiet_cmd_gzip = GZIP $@ + cmd_gzip = cat $(real-prereqs) | $(KGZIP) -n -f -9 > $@ + +# DTC +# --------------------------------------------------------------------------- +DTC ?= $(objtree)/scripts/dtc/dtc +DTC_FLAGS += -Wno-interrupt_provider + +# Disable noisy checks by default +ifeq ($(findstring 1,$(KBUILD_EXTRA_WARN)),) +DTC_FLAGS += -Wno-unit_address_vs_reg \ + -Wno-unit_address_format \ + -Wno-avoid_unnecessary_addr_size \ + -Wno-alias_paths \ + -Wno-graph_child_address \ + -Wno-simple_bus_reg \ + -Wno-unique_unit_address \ + -Wno-pci_device_reg +endif + +ifneq ($(findstring 2,$(KBUILD_EXTRA_WARN)),) +DTC_FLAGS += -Wnode_name_chars_strict \ + -Wproperty_name_chars_strict \ + -Winterrupt_provider +endif + +DTC_FLAGS += $(DTC_FLAGS_$(basetarget)) + +# Generate an assembly file to wrap the output of the device tree compiler +quiet_cmd_dt_S_dtb= DTB $@ +cmd_dt_S_dtb= \ +{ \ + echo '\#include '; \ + echo '.section .dtb.init.rodata,"a"'; \ + echo '.balign STRUCT_ALIGNMENT'; \ + echo '.global __dtb_$(subst -,_,$(*F))_begin'; \ + echo '__dtb_$(subst -,_,$(*F))_begin:'; \ + echo '.incbin "$<" '; \ + echo '__dtb_$(subst -,_,$(*F))_end:'; \ + echo '.global __dtb_$(subst -,_,$(*F))_end'; \ + echo '.balign STRUCT_ALIGNMENT'; \ +} > $@ + +$(obj)/%.dtb.S: $(obj)/%.dtb FORCE + $(call if_changed,dt_S_dtb) + +quiet_cmd_dtc = DTC $@ +cmd_dtc = $(HOSTCC) -E $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \ + $(DTC) -O $(patsubst .%,%,$(suffix $@)) -o $@ -b 0 \ + $(addprefix -i,$(dir $<) $(DTC_INCLUDE)) $(DTC_FLAGS) \ + -d $(depfile).dtc.tmp $(dtc-tmp) ; \ + cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile) + +$(obj)/%.dtb: $(src)/%.dts $(DTC) FORCE + $(call if_changed_dep,dtc) + +DT_CHECKER ?= dt-validate +DT_BINDING_DIR := Documentation/devicetree/bindings +# DT_TMP_SCHEMA may be overridden from Documentation/devicetree/bindings/Makefile +DT_TMP_SCHEMA ?= $(objtree)/$(DT_BINDING_DIR)/processed-schema.json + +quiet_cmd_dtb_check = CHECK $@ + cmd_dtb_check = $(DT_CHECKER) -u $(srctree)/$(DT_BINDING_DIR) -p $(DT_TMP_SCHEMA) $@ + +define rule_dtc + $(call cmd_and_fixdep,dtc) + $(call cmd,dtb_check) +endef + +$(obj)/%.dt.yaml: $(src)/%.dts $(DTC) $(DT_TMP_SCHEMA) FORCE + $(call if_changed_rule,dtc,yaml) + +dtc-tmp = $(subst $(comma),_,$(dot-target).dts.tmp) + +# Bzip2 +# --------------------------------------------------------------------------- + +# Bzip2 and LZMA do not include size in file... so we have to fake that; +# append the size as a 32-bit littleendian number as gzip does. +size_append = printf $(shell \ +dec_size=0; \ +for F in $(real-prereqs); do \ + fsize=$$($(CONFIG_SHELL) $(srctree)/scripts/file-size.sh $$F); \ + dec_size=$$(expr $$dec_size + $$fsize); \ +done; \ +printf "%08x\n" $$dec_size | \ + sed 's/\(..\)/\1 /g' | { \ + read ch0 ch1 ch2 ch3; \ + for ch in $$ch3 $$ch2 $$ch1 $$ch0; do \ + printf '%s%03o' '\\' $$((0x$$ch)); \ + done; \ + } \ +) + +quiet_cmd_bzip2 = BZIP2 $@ + cmd_bzip2 = { cat $(real-prereqs) | $(KBZIP2) -9; $(size_append); } > $@ + +# Lzma +# --------------------------------------------------------------------------- + +quiet_cmd_lzma = LZMA $@ + cmd_lzma = { cat $(real-prereqs) | $(LZMA) -9; $(size_append); } > $@ + +quiet_cmd_lzo = LZO $@ + cmd_lzo = { cat $(real-prereqs) | $(KLZOP) -9; $(size_append); } > $@ + +quiet_cmd_lz4 = LZ4 $@ + cmd_lz4 = { cat $(real-prereqs) | $(LZ4) -l -c1 stdin stdout; \ + $(size_append); } > $@ + +# U-Boot mkimage +# --------------------------------------------------------------------------- + +MKIMAGE := $(srctree)/scripts/mkuboot.sh + +# SRCARCH just happens to match slightly more than ARCH (on sparc), so reduces +# the number of overrides in arch makefiles +UIMAGE_ARCH ?= $(SRCARCH) +UIMAGE_COMPRESSION ?= $(if $(2),$(2),none) +UIMAGE_OPTS-y ?= +UIMAGE_TYPE ?= kernel +UIMAGE_LOADADDR ?= arch_must_set_this +UIMAGE_ENTRYADDR ?= $(UIMAGE_LOADADDR) +UIMAGE_NAME ?= 'Linux-$(KERNELRELEASE)' + +quiet_cmd_uimage = UIMAGE $@ + cmd_uimage = $(BASH) $(MKIMAGE) -A $(UIMAGE_ARCH) -O linux \ + -C $(UIMAGE_COMPRESSION) $(UIMAGE_OPTS-y) \ + -T $(UIMAGE_TYPE) \ + -a $(UIMAGE_LOADADDR) -e $(UIMAGE_ENTRYADDR) \ + -n $(UIMAGE_NAME) -d $< $@ + +# XZ +# --------------------------------------------------------------------------- +# Use xzkern to compress the kernel image and xzmisc to compress other things. +# +# xzkern uses a big LZMA2 dictionary since it doesn't increase memory usage +# of the kernel decompressor. A BCJ filter is used if it is available for +# the target architecture. xzkern also appends uncompressed size of the data +# using size_append. The .xz format has the size information available at +# the end of the file too, but it's in more complex format and it's good to +# avoid changing the part of the boot code that reads the uncompressed size. +# Note that the bytes added by size_append will make the xz tool think that +# the file is corrupt. This is expected. +# +# xzmisc doesn't use size_append, so it can be used to create normal .xz +# files. xzmisc uses smaller LZMA2 dictionary than xzkern, because a very +# big dictionary would increase the memory usage too much in the multi-call +# decompression mode. A BCJ filter isn't used either. +quiet_cmd_xzkern = XZKERN $@ + cmd_xzkern = { cat $(real-prereqs) | sh $(srctree)/scripts/xz_wrap.sh; \ + $(size_append); } > $@ + +quiet_cmd_xzmisc = XZMISC $@ + cmd_xzmisc = cat $(real-prereqs) | $(XZ) --check=crc32 --lzma2=dict=1MiB > $@ + +# ZSTD +# --------------------------------------------------------------------------- +# Appends the uncompressed size of the data using size_append. The .zst +# format has the size information available at the beginning of the file too, +# but it's in a more complex format and it's good to avoid changing the part +# of the boot code that reads the uncompressed size. +# +# Note that the bytes added by size_append will make the zstd tool think that +# the file is corrupt. This is expected. +# +# zstd uses a maximum window size of 8 MB. zstd22 uses a maximum window size of +# 128 MB. zstd22 is used for kernel compression because it is decompressed in a +# single pass, so zstd doesn't need to allocate a window buffer. When streaming +# decompression is used, like initramfs decompression, zstd22 should likely not +# be used because it would require zstd to allocate a 128 MB buffer. + +quiet_cmd_zstd = ZSTD $@ + cmd_zstd = { cat $(real-prereqs) | $(ZSTD) -19; $(size_append); } > $@ + +quiet_cmd_zstd22 = ZSTD22 $@ + cmd_zstd22 = { cat $(real-prereqs) | $(ZSTD) -22 --ultra; $(size_append); } > $@ + +# ASM offsets +# --------------------------------------------------------------------------- + +# Default sed regexp - multiline due to syntax constraints +# +# Use [:space:] because LLVM's integrated assembler inserts around +# the .ascii directive whereas GCC keeps the as-is. +define sed-offsets + 's:^[[:space:]]*\.ascii[[:space:]]*"\(.*\)".*:\1:; \ + /^->/{s:->#\(.*\):/* \1 */:; \ + s:^->\([^ ]*\) [\$$#]*\([^ ]*\) \(.*\):#define \1 \2 /* \3 */:; \ + s:->::; p;}' +endef + +# Use filechk to avoid rebuilds when a header changes, but the resulting file +# does not +define filechk_offsets + echo "#ifndef $2"; \ + echo "#define $2"; \ + echo "/*"; \ + echo " * DO NOT MODIFY."; \ + echo " *"; \ + echo " * This file was generated by Kbuild"; \ + echo " */"; \ + echo ""; \ + sed -ne $(sed-offsets) < $<; \ + echo ""; \ + echo "#endif" +endef diff --git a/src/net/scripts/Makefile.modfinal b/src/net/scripts/Makefile.modfinal new file mode 100644 index 0000000..ae01baf --- /dev/null +++ b/src/net/scripts/Makefile.modfinal @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: GPL-2.0-only +# =========================================================================== +# Module final link +# =========================================================================== + +PHONY := __modfinal +__modfinal: + +include $(srctree)/scripts/Kbuild.include + +# for c_flags +include $(srctree)/scripts/Makefile.lib + +# find all modules listed in modules.order +modules := $(sort $(shell cat $(MODORDER))) + +__modfinal: $(modules) + @: + +# modname and part-of-module are set to make c_flags define proper module flags +modname = $(notdir $(@:.mod.o=)) +part-of-module = y + +quiet_cmd_cc_o_c = CC [M] $@ + cmd_cc_o_c = $(CC) $(c_flags) -c -o $@ $< + +%.mod.o: %.mod.c FORCE + $(call if_changed_dep,cc_o_c) + +ARCH_POSTLINK := $(wildcard $(srctree)/arch/$(SRCARCH)/Makefile.postlink) + +quiet_cmd_ld_ko_o = LD [M] $@ + cmd_ld_ko_o = \ + $(LD) -r $(KBUILD_LDFLAGS) \ + $(KBUILD_LDFLAGS_MODULE) $(LDFLAGS_MODULE) \ + -T scripts/module.lds -o $@ $(filter %.o, $^); \ + $(if $(ARCH_POSTLINK), $(MAKE) -f $(ARCH_POSTLINK) $@, true) + +$(modules): %.ko: %.o %.mod.o scripts/module.lds FORCE + +$(call if_changed,ld_ko_o) + +targets += $(modules) $(modules:.ko=.mod.o) + +# Add FORCE to the prequisites of a target to force it to be always rebuilt. +# --------------------------------------------------------------------------- + +PHONY += FORCE +FORCE: + +# Read all saved command lines and dependencies for the $(targets) we +# may be building above, using $(if_changed{,_dep}). As an +# optimization, we don't need to read them if the target does not +# exist, we will rebuild anyway in that case. + +existing-targets := $(wildcard $(sort $(targets))) + +-include $(foreach f,$(existing-targets),$(dir $(f)).$(notdir $(f)).cmd) + +.PHONY: $(PHONY) diff --git a/src/net/scripts/Makefile.modinst b/src/net/scripts/Makefile.modinst new file mode 100644 index 0000000..5a4579e --- /dev/null +++ b/src/net/scripts/Makefile.modinst @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: GPL-2.0 +# ========================================================================== +# Installing modules +# ========================================================================== + +PHONY := __modinst +__modinst: + +include scripts/Kbuild.include + +modules := $(sort $(shell cat $(if $(KBUILD_EXTMOD),$(KBUILD_EXTMOD)/)modules.order)) + +PHONY += $(modules) +__modinst: $(modules) + @: + +# Don't stop modules_install if we can't sign external modules. +quiet_cmd_modules_install = INSTALL $@ + cmd_modules_install = \ + mkdir -p $(2) ; \ + cp $@ $(2) ; \ + $(mod_strip_cmd) $(2)/$(notdir $@) ; \ + $(mod_sign_cmd) $(2)/$(notdir $@) $(patsubst %,|| true,$(KBUILD_EXTMOD)) ; \ + $(mod_compress_cmd) $(2)/$(notdir $@) + +# Modules built outside the kernel source tree go into extra by default +INSTALL_MOD_DIR ?= extra +ext-mod-dir = $(INSTALL_MOD_DIR)$(subst $(patsubst %/,%,$(KBUILD_EXTMOD)),,$(@D)) + +modinst_dir = $(if $(KBUILD_EXTMOD),$(ext-mod-dir),kernel/$(@D)) + +$(modules): + $(call cmd,modules_install,$(MODLIB)/$(modinst_dir)) + +.PHONY: $(PHONY) diff --git a/src/net/scripts/Makefile.modpost b/src/net/scripts/Makefile.modpost new file mode 100644 index 0000000..12a87be --- /dev/null +++ b/src/net/scripts/Makefile.modpost @@ -0,0 +1,142 @@ +# SPDX-License-Identifier: GPL-2.0 +# =========================================================================== +# Module versions +# =========================================================================== +# +# Stage one of module building created the following: +# a) The individual .o files used for the module +# b) A .o file which is the .o files above linked together +# c) A .mod file, listing the name of the preliminary .o file, +# plus all .o files +# d) modules.order, which lists all the modules + +# Stage 2 is handled by this file and does the following +# 1) Find all modules listed in modules.order +# 2) modpost is then used to +# 3) create one .mod.c file pr. module +# 4) create one Module.symvers file with CRC for all exported symbols + +# Step 3 is used to place certain information in the module's ELF +# section, including information such as: +# Version magic (see include/linux/vermagic.h for full details) +# - Kernel release +# - SMP is CONFIG_SMP +# - PREEMPT is CONFIG_PREEMPT[_RT] +# - GCC Version +# Module info +# - Module version (MODULE_VERSION) +# - Module alias'es (MODULE_ALIAS) +# - Module license (MODULE_LICENSE) +# - See include/linux/module.h for more details + +# Step 4 is solely used to allow module versioning in external modules, +# where the CRC of each module is retrieved from the Module.symvers file. + +# KBUILD_MODPOST_WARN can be set to avoid error out in case of undefined +# symbols in the final module linking stage +# KBUILD_MODPOST_NOFINAL can be set to skip the final link of modules. +# This is solely useful to speed up test compiles + +PHONY := __modpost +__modpost: + +include include/config/auto.conf +include scripts/Kbuild.include + +MODPOST = scripts/mod/modpost \ + $(if $(CONFIG_MODVERSIONS),-m) \ + $(if $(CONFIG_MODULE_SRCVERSION_ALL),-a) \ + $(if $(CONFIG_SECTION_MISMATCH_WARN_ONLY),,-E) \ + $(if $(KBUILD_MODPOST_WARN),-w) \ + -o $@ + +ifdef MODPOST_VMLINUX + +quiet_cmd_modpost = MODPOST $@ + cmd_modpost = $(MODPOST) $< + +vmlinux.symvers: vmlinux.o + $(call cmd,modpost) + +__modpost: vmlinux.symvers + +else + +ifeq ($(KBUILD_EXTMOD),) + +input-symdump := vmlinux.symvers +output-symdump := modules-only.symvers + +quiet_cmd_cat = GEN $@ + cmd_cat = cat $(real-prereqs) > $@ + +ifneq ($(wildcard vmlinux.symvers),) + +__modpost: Module.symvers +Module.symvers: vmlinux.symvers modules-only.symvers FORCE + $(call if_changed,cat) + +targets += Module.symvers + +endif + +else + +# set src + obj - they may be used in the modules's Makefile +obj := $(KBUILD_EXTMOD) +src := $(obj) + +# Include the module's Makefile to find KBUILD_EXTRA_SYMBOLS +include $(if $(wildcard $(KBUILD_EXTMOD)/Kbuild), \ + $(KBUILD_EXTMOD)/Kbuild, $(KBUILD_EXTMOD)/Makefile) + +# modpost option for external modules +MODPOST += -e + +input-symdump := Module.symvers $(KBUILD_EXTRA_SYMBOLS) +output-symdump := $(KBUILD_EXTMOD)/Module.symvers + +endif + +# modpost options for modules (both in-kernel and external) +MODPOST += \ + $(addprefix -i ,$(wildcard $(input-symdump))) \ + $(if $(KBUILD_NSDEPS),-d $(MODULES_NSDEPS)) \ + $(if $(CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS)$(KBUILD_NSDEPS),-N) + +# 'make -i -k' ignores compile errors, and builds as many modules as possible. +ifneq ($(findstring i,$(filter-out --%,$(MAKEFLAGS))),) +MODPOST += -n +endif + +# Clear VPATH to not search for *.symvers in $(srctree). Check only $(objtree). +VPATH := +$(input-symdump): + @echo >&2 'WARNING: Symbol version dump "$@" is missing.' + @echo >&2 ' Modules may not have dependencies or modversions.' + +# Read out modules.order to pass in modpost. +# Otherwise, allmodconfig would fail with "Argument list too long". +quiet_cmd_modpost = MODPOST $@ + cmd_modpost = sed 's/ko$$/o/' $< | $(MODPOST) -T - + +$(output-symdump): $(MODORDER) $(input-symdump) FORCE + $(call if_changed,modpost) + +targets += $(output-symdump) + +__modpost: $(output-symdump) +ifneq ($(KBUILD_MODPOST_NOFINAL),1) + $(Q)$(MAKE) -f $(srctree)/scripts/Makefile.modfinal +endif + +PHONY += FORCE +FORCE: + +existing-targets := $(wildcard $(sort $(targets))) + +-include $(foreach f,$(existing-targets),$(dir $(f)).$(notdir $(f)).cmd) + +endif + +.PHONY: $(PHONY) diff --git a/src/net/scripts/Makefile.modsign b/src/net/scripts/Makefile.modsign new file mode 100644 index 0000000..d7325ce --- /dev/null +++ b/src/net/scripts/Makefile.modsign @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: GPL-2.0 +# ========================================================================== +# Signing modules +# ========================================================================== + +PHONY := __modsign +__modsign: + +include scripts/Kbuild.include + +modules := $(sort $(shell cat modules.order)) + +PHONY += $(modules) +__modsign: $(modules) + @: + +quiet_cmd_sign_ko = SIGN [M] $(2)/$(notdir $@) + cmd_sign_ko = $(mod_sign_cmd) $(2)/$(notdir $@) + +# Modules built outside the kernel source tree go into extra by default +INSTALL_MOD_DIR ?= extra +ext-mod-dir = $(INSTALL_MOD_DIR)$(subst $(patsubst %/,%,$(KBUILD_EXTMOD)),,$(@D)) + +modinst_dir = $(if $(KBUILD_EXTMOD),$(ext-mod-dir),kernel/$(@D)) + +$(modules): + $(call cmd,sign_ko,$(MODLIB)/$(modinst_dir)) + +.PHONY: $(PHONY) diff --git a/src/net/scripts/Makefile.package b/src/net/scripts/Makefile.package new file mode 100644 index 0000000..f952fb6 --- /dev/null +++ b/src/net/scripts/Makefile.package @@ -0,0 +1,161 @@ +# SPDX-License-Identifier: GPL-2.0-only +# Makefile for the different targets used to generate full packages of a kernel + +include $(srctree)/scripts/Kbuild.include + +# RPM target +# --------------------------------------------------------------------------- +# The rpm target generates two rpm files: +# /usr/src/packages/SRPMS/kernel-2.6.7rc2-1.src.rpm +# /usr/src/packages/RPMS/i386/kernel-2.6.7rc2-1..rpm +# The src.rpm files includes all source for the kernel being built +# The .rpm includes kernel configuration, modules etc. +# +# Process to create the rpm files +# a) clean the kernel +# b) Generate .spec file +# c) Build a tar ball, using symlink to make kernel version +# first entry in the path +# d) and pack the result to a tar.gz file +# e) generate the rpm files, based on kernel.spec +# - Use /. to avoid tar packing just the symlink + +# Note that the rpm-pkg target cannot be used with KBUILD_OUTPUT, +# but the binrpm-pkg target can; for some reason O= gets ignored. + +# Remove hyphens since they have special meaning in RPM filenames +KERNELPATH := kernel-$(subst -,_,$(KERNELRELEASE)) +KDEB_SOURCENAME ?= linux-$(KERNELRELEASE) +KBUILD_PKG_ROOTCMD ?="fakeroot -u" +export KDEB_SOURCENAME +# Include only those top-level files that are needed by make, plus the GPL copy +TAR_CONTENT := $(KBUILD_ALLDIRS) .config .scmversion Makefile \ + Kbuild Kconfig COPYING $(wildcard localversion*) +MKSPEC := $(srctree)/scripts/package/mkspec + +quiet_cmd_src_tar = TAR $(2).tar.gz + cmd_src_tar = \ +if test "$(objtree)" != "$(srctree)"; then \ + echo >&2; \ + echo >&2 " ERROR:"; \ + echo >&2 " Building source tarball is not possible outside the"; \ + echo >&2 " kernel source tree. Don't set KBUILD_OUTPUT, or use the"; \ + echo >&2 " binrpm-pkg or bindeb-pkg target instead."; \ + echo >&2; \ + false; \ +fi ; \ +$(srctree)/scripts/setlocalversion --save-scmversion; \ +tar -I $(KGZIP) -c $(RCS_TAR_IGNORE) -f $(2).tar.gz \ + --transform 's:^:$(2)/:S' $(TAR_CONTENT) $(3); \ +rm -f $(objtree)/.scmversion + +# rpm-pkg +# --------------------------------------------------------------------------- +PHONY += rpm-pkg +rpm-pkg: + $(MAKE) clean + $(CONFIG_SHELL) $(MKSPEC) >$(objtree)/kernel.spec + $(call cmd,src_tar,$(KERNELPATH),kernel.spec) + +rpmbuild $(RPMOPTS) --target $(UTS_MACHINE) -ta $(KERNELPATH).tar.gz \ + --define='_smp_mflags %{nil}' + +# binrpm-pkg +# --------------------------------------------------------------------------- +PHONY += binrpm-pkg +binrpm-pkg: + $(MAKE) -f $(srctree)/Makefile + $(CONFIG_SHELL) $(MKSPEC) prebuilt > $(objtree)/binkernel.spec + +rpmbuild $(RPMOPTS) --define "_builddir $(objtree)" --target \ + $(UTS_MACHINE) -bb $(objtree)/binkernel.spec + +PHONY += deb-pkg +deb-pkg: + $(MAKE) clean + $(CONFIG_SHELL) $(srctree)/scripts/package/mkdebian + $(call cmd,src_tar,$(KDEB_SOURCENAME)) + origversion=$$(dpkg-parsechangelog -SVersion |sed 's/-[^-]*$$//');\ + mv $(KDEB_SOURCENAME).tar.gz ../$(KDEB_SOURCENAME)_$${origversion}.orig.tar.gz + +dpkg-buildpackage -r$(KBUILD_PKG_ROOTCMD) -a$$(cat debian/arch) $(DPKG_FLAGS) -i.git -us -uc + +PHONY += bindeb-pkg +bindeb-pkg: + $(CONFIG_SHELL) $(srctree)/scripts/package/mkdebian + +dpkg-buildpackage -r$(KBUILD_PKG_ROOTCMD) -a$$(cat debian/arch) $(DPKG_FLAGS) -b -nc -uc + +PHONY += intdeb-pkg +intdeb-pkg: + +$(CONFIG_SHELL) $(srctree)/scripts/package/builddeb + +# snap-pkg +# --------------------------------------------------------------------------- +PHONY += snap-pkg +snap-pkg: + rm -rf $(objtree)/snap + mkdir $(objtree)/snap + $(MAKE) clean + $(call cmd,src_tar,$(KERNELPATH)) + sed "s@KERNELRELEASE@$(KERNELRELEASE)@; \ + s@SRCTREE@$(shell realpath $(KERNELPATH).tar.gz)@" \ + $(srctree)/scripts/package/snapcraft.template > \ + $(objtree)/snap/snapcraft.yaml + cd $(objtree)/snap && \ + snapcraft --target-arch=$(UTS_MACHINE) + +# tarball targets +# --------------------------------------------------------------------------- +tar-pkgs := dir-pkg tar-pkg targz-pkg tarbz2-pkg tarxz-pkg +PHONY += $(tar-pkgs) +$(tar-pkgs): + $(MAKE) -f $(srctree)/Makefile + +$(CONFIG_SHELL) $(srctree)/scripts/package/buildtar $@ + +# perf-pkg - generate a source tarball with perf source +# --------------------------------------------------------------------------- + +perf-tar=perf-$(KERNELVERSION) + +quiet_cmd_perf_tar = TAR + cmd_perf_tar = \ +git --git-dir=$(srctree)/.git archive --prefix=$(perf-tar)/ \ + HEAD^{tree} $$(cd $(srctree); \ + echo $$(cat tools/perf/MANIFEST)) \ + -o $(perf-tar).tar; \ +mkdir -p $(perf-tar); \ +git --git-dir=$(srctree)/.git rev-parse HEAD > $(perf-tar)/HEAD; \ +(cd $(srctree)/tools/perf; \ +util/PERF-VERSION-GEN $(CURDIR)/$(perf-tar)/); \ +tar rf $(perf-tar).tar $(perf-tar)/HEAD $(perf-tar)/PERF-VERSION-FILE; \ +rm -r $(perf-tar); \ +$(if $(findstring tar-src,$@),, \ +$(if $(findstring bz2,$@),$(KBZIP2), \ +$(if $(findstring gz,$@),$(KGZIP), \ +$(if $(findstring xz,$@),$(XZ), \ +$(error unknown target $@)))) \ + -f -9 $(perf-tar).tar) + +perf-tar-pkgs := perf-tar-src-pkg perf-targz-src-pkg perf-tarbz2-src-pkg perf-tarxz-src-pkg +PHONY += $(perf-tar-pkgs) +$(perf-tar-pkgs): + $(call cmd,perf_tar) + +# Help text displayed when executing 'make help' +# --------------------------------------------------------------------------- +PHONY += help +help: + @echo ' rpm-pkg - Build both source and binary RPM kernel packages' + @echo ' binrpm-pkg - Build only the binary kernel RPM package' + @echo ' deb-pkg - Build both source and binary deb kernel packages' + @echo ' bindeb-pkg - Build only the binary kernel deb package' + @echo ' snap-pkg - Build only the binary kernel snap package' + @echo ' (will connect to external hosts)' + @echo ' dir-pkg - Build the kernel as a plain directory structure' + @echo ' tar-pkg - Build the kernel as an uncompressed tarball' + @echo ' targz-pkg - Build the kernel as a gzip compressed tarball' + @echo ' tarbz2-pkg - Build the kernel as a bzip2 compressed tarball' + @echo ' tarxz-pkg - Build the kernel as a xz compressed tarball' + @echo ' perf-tar-src-pkg - Build $(perf-tar).tar source tarball' + @echo ' perf-targz-src-pkg - Build $(perf-tar).tar.gz source tarball' + @echo ' perf-tarbz2-src-pkg - Build $(perf-tar).tar.bz2 source tarball' + @echo ' perf-tarxz-src-pkg - Build $(perf-tar).tar.xz source tarball' + +.PHONY: $(PHONY) diff --git a/src/net/scripts/Makefile.ubsan b/src/net/scripts/Makefile.ubsan new file mode 100644 index 0000000..6f61aa4 --- /dev/null +++ b/src/net/scripts/Makefile.ubsan @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0 + +# Enable available and selected UBSAN features. +ubsan-cflags-$(CONFIG_UBSAN_ALIGNMENT) += -fsanitize=alignment +ubsan-cflags-$(CONFIG_UBSAN_ONLY_BOUNDS) += -fsanitize=bounds +ubsan-cflags-$(CONFIG_UBSAN_ARRAY_BOUNDS) += -fsanitize=array-bounds +ubsan-cflags-$(CONFIG_UBSAN_LOCAL_BOUNDS) += -fsanitize=local-bounds +ubsan-cflags-$(CONFIG_UBSAN_SHIFT) += -fsanitize=shift +ubsan-cflags-$(CONFIG_UBSAN_DIV_ZERO) += -fsanitize=integer-divide-by-zero +ubsan-cflags-$(CONFIG_UBSAN_UNREACHABLE) += -fsanitize=unreachable +ubsan-cflags-$(CONFIG_UBSAN_BOOL) += -fsanitize=bool +ubsan-cflags-$(CONFIG_UBSAN_ENUM) += -fsanitize=enum +ubsan-cflags-$(CONFIG_UBSAN_TRAP) += -fsanitize-undefined-trap-on-error + +export CFLAGS_UBSAN := $(ubsan-cflags-y) \ No newline at end of file diff --git a/src/net/scripts/Makefile.userprogs b/src/net/scripts/Makefile.userprogs new file mode 100644 index 0000000..fb41529 --- /dev/null +++ b/src/net/scripts/Makefile.userprogs @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Build userspace programs for the target system +# + +# Executables compiled from a single .c file +user-csingle := $(foreach m, $(userprogs), $(if $($(m)-objs),,$(m))) + +# Executables linked based on several .o files +user-cmulti := $(foreach m, $(userprogs), $(if $($(m)-objs),$(m))) + +# Objects compiled from .c files +user-cobjs := $(sort $(foreach m, $(userprogs), $($(m)-objs))) + +user-csingle := $(addprefix $(obj)/, $(user-csingle)) +user-cmulti := $(addprefix $(obj)/, $(user-cmulti)) +user-cobjs := $(addprefix $(obj)/, $(user-cobjs)) + +user_ccflags = -Wp,-MMD,$(depfile) $(KBUILD_USERCFLAGS) $(userccflags) \ + $($(target-stem)-userccflags) +user_ldflags = $(KBUILD_USERLDFLAGS) $(userldflags) $($(target-stem)-userldflags) + +# Create an executable from a single .c file +quiet_cmd_user_cc_c = CC [U] $@ + cmd_user_cc_c = $(CC) $(user_ccflags) $(user_ldflags) -o $@ $< \ + $($(target-stem)-userldlibs) +$(user-csingle): $(obj)/%: $(src)/%.c FORCE + $(call if_changed_dep,user_cc_c) + +# Link an executable based on list of .o files +quiet_cmd_user_ld = LD [U] $@ + cmd_user_ld = $(CC) $(user_ldflags) -o $@ \ + $(addprefix $(obj)/, $($(target-stem)-objs)) \ + $($(target-stem)-userldlibs) +$(user-cmulti): FORCE + $(call if_changed,user_ld) +$(call multi_depend, $(user-cmulti), , -objs) + +# Create .o file from a .c file +quiet_cmd_user_cc_o_c = CC [U] $@ + cmd_user_cc_o_c = $(CC) $(user_ccflags) -c -o $@ $< +$(user-cobjs): $(obj)/%.o: $(src)/%.c FORCE + $(call if_changed_dep,user_cc_o_c) + +targets += $(user-csingle) $(user-cmulti) $(user-cobjs) diff --git a/src/net/scripts/adjust_autoksyms.sh b/src/net/scripts/adjust_autoksyms.sh new file mode 100755 index 0000000..2b366d9 --- /dev/null +++ b/src/net/scripts/adjust_autoksyms.sh @@ -0,0 +1,76 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0-only + +# Script to update include/generated/autoksyms.h and dependency files +# +# Copyright: (C) 2016 Linaro Limited +# Created by: Nicolas Pitre, January 2016 +# + +# Update the include/generated/autoksyms.h file. +# +# For each symbol being added or removed, the corresponding dependency +# file's timestamp is updated to force a rebuild of the affected source +# file. All arguments passed to this script are assumed to be a command +# to be exec'd to trigger a rebuild of those files. + +set -e + +cur_ksyms_file="include/generated/autoksyms.h" +new_ksyms_file="include/generated/autoksyms.h.tmpnew" + +info() { + if [ "$quiet" != "silent_" ]; then + printf " %-7s %s\n" "$1" "$2" + fi +} + +info "CHK" "$cur_ksyms_file" + +# Use "make V=1" to debug this script. +case "$KBUILD_VERBOSE" in +*1*) + set -x + ;; +esac + +# We need access to CONFIG_ symbols +. include/config/auto.conf + +# Generate a new symbol list file +$CONFIG_SHELL $srctree/scripts/gen_autoksyms.sh "$new_ksyms_file" + +# Extract changes between old and new list and touch corresponding +# dependency files. +changed=$( +count=0 +sort "$cur_ksyms_file" "$new_ksyms_file" | uniq -u | +sed -n 's/^#define __KSYM_\(.*\) 1/\1/p' | tr "A-Z_" "a-z/" | +while read sympath; do + if [ -z "$sympath" ]; then continue; fi + depfile="include/ksym/${sympath}.h" + mkdir -p "$(dirname "$depfile")" + touch "$depfile" + # Filesystems with coarse time precision may create timestamps + # equal to the one from a file that was very recently built and that + # needs to be rebuild. Let's guard against that by making sure our + # dep files are always newer than the first file we created here. + while [ ! "$depfile" -nt "$new_ksyms_file" ]; do + touch "$depfile" + done + echo $((count += 1)) +done | tail -1 ) +changed=${changed:-0} + +if [ $changed -gt 0 ]; then + # Replace the old list with tne new one + old=$(grep -c "^#define __KSYM_" "$cur_ksyms_file" || true) + new=$(grep -c "^#define __KSYM_" "$new_ksyms_file" || true) + info "KSYMS" "symbols: before=$old, after=$new, changed=$changed" + info "UPD" "$cur_ksyms_file" + mv -f "$new_ksyms_file" "$cur_ksyms_file" + # Then trigger a rebuild of affected source files + exec $@ +else + rm -f "$new_ksyms_file" +fi diff --git a/src/net/scripts/asn1_compiler.c b/src/net/scripts/asn1_compiler.c new file mode 100644 index 0000000..adabd41 --- /dev/null +++ b/src/net/scripts/asn1_compiler.c @@ -0,0 +1,1611 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* Simplified ASN.1 notation parser + * + * Copyright (C) 2012 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +enum token_type { + DIRECTIVE_ABSENT, + DIRECTIVE_ALL, + DIRECTIVE_ANY, + DIRECTIVE_APPLICATION, + DIRECTIVE_AUTOMATIC, + DIRECTIVE_BEGIN, + DIRECTIVE_BIT, + DIRECTIVE_BMPString, + DIRECTIVE_BOOLEAN, + DIRECTIVE_BY, + DIRECTIVE_CHARACTER, + DIRECTIVE_CHOICE, + DIRECTIVE_CLASS, + DIRECTIVE_COMPONENT, + DIRECTIVE_COMPONENTS, + DIRECTIVE_CONSTRAINED, + DIRECTIVE_CONTAINING, + DIRECTIVE_DEFAULT, + DIRECTIVE_DEFINED, + DIRECTIVE_DEFINITIONS, + DIRECTIVE_EMBEDDED, + DIRECTIVE_ENCODED, + DIRECTIVE_ENCODING_CONTROL, + DIRECTIVE_END, + DIRECTIVE_ENUMERATED, + DIRECTIVE_EXCEPT, + DIRECTIVE_EXPLICIT, + DIRECTIVE_EXPORTS, + DIRECTIVE_EXTENSIBILITY, + DIRECTIVE_EXTERNAL, + DIRECTIVE_FALSE, + DIRECTIVE_FROM, + DIRECTIVE_GeneralString, + DIRECTIVE_GeneralizedTime, + DIRECTIVE_GraphicString, + DIRECTIVE_IA5String, + DIRECTIVE_IDENTIFIER, + DIRECTIVE_IMPLICIT, + DIRECTIVE_IMPLIED, + DIRECTIVE_IMPORTS, + DIRECTIVE_INCLUDES, + DIRECTIVE_INSTANCE, + DIRECTIVE_INSTRUCTIONS, + DIRECTIVE_INTEGER, + DIRECTIVE_INTERSECTION, + DIRECTIVE_ISO646String, + DIRECTIVE_MAX, + DIRECTIVE_MIN, + DIRECTIVE_MINUS_INFINITY, + DIRECTIVE_NULL, + DIRECTIVE_NumericString, + DIRECTIVE_OBJECT, + DIRECTIVE_OCTET, + DIRECTIVE_OF, + DIRECTIVE_OPTIONAL, + DIRECTIVE_ObjectDescriptor, + DIRECTIVE_PATTERN, + DIRECTIVE_PDV, + DIRECTIVE_PLUS_INFINITY, + DIRECTIVE_PRESENT, + DIRECTIVE_PRIVATE, + DIRECTIVE_PrintableString, + DIRECTIVE_REAL, + DIRECTIVE_RELATIVE_OID, + DIRECTIVE_SEQUENCE, + DIRECTIVE_SET, + DIRECTIVE_SIZE, + DIRECTIVE_STRING, + DIRECTIVE_SYNTAX, + DIRECTIVE_T61String, + DIRECTIVE_TAGS, + DIRECTIVE_TRUE, + DIRECTIVE_TeletexString, + DIRECTIVE_UNION, + DIRECTIVE_UNIQUE, + DIRECTIVE_UNIVERSAL, + DIRECTIVE_UTCTime, + DIRECTIVE_UTF8String, + DIRECTIVE_UniversalString, + DIRECTIVE_VideotexString, + DIRECTIVE_VisibleString, + DIRECTIVE_WITH, + NR__DIRECTIVES, + TOKEN_ASSIGNMENT = NR__DIRECTIVES, + TOKEN_OPEN_CURLY, + TOKEN_CLOSE_CURLY, + TOKEN_OPEN_SQUARE, + TOKEN_CLOSE_SQUARE, + TOKEN_OPEN_ACTION, + TOKEN_CLOSE_ACTION, + TOKEN_COMMA, + TOKEN_NUMBER, + TOKEN_TYPE_NAME, + TOKEN_ELEMENT_NAME, + NR__TOKENS +}; + +static const unsigned char token_to_tag[NR__TOKENS] = { + /* EOC goes first */ + [DIRECTIVE_BOOLEAN] = ASN1_BOOL, + [DIRECTIVE_INTEGER] = ASN1_INT, + [DIRECTIVE_BIT] = ASN1_BTS, + [DIRECTIVE_OCTET] = ASN1_OTS, + [DIRECTIVE_NULL] = ASN1_NULL, + [DIRECTIVE_OBJECT] = ASN1_OID, + [DIRECTIVE_ObjectDescriptor] = ASN1_ODE, + [DIRECTIVE_EXTERNAL] = ASN1_EXT, + [DIRECTIVE_REAL] = ASN1_REAL, + [DIRECTIVE_ENUMERATED] = ASN1_ENUM, + [DIRECTIVE_EMBEDDED] = 0, + [DIRECTIVE_UTF8String] = ASN1_UTF8STR, + [DIRECTIVE_RELATIVE_OID] = ASN1_RELOID, + /* 14 */ + /* 15 */ + [DIRECTIVE_SEQUENCE] = ASN1_SEQ, + [DIRECTIVE_SET] = ASN1_SET, + [DIRECTIVE_NumericString] = ASN1_NUMSTR, + [DIRECTIVE_PrintableString] = ASN1_PRNSTR, + [DIRECTIVE_T61String] = ASN1_TEXSTR, + [DIRECTIVE_TeletexString] = ASN1_TEXSTR, + [DIRECTIVE_VideotexString] = ASN1_VIDSTR, + [DIRECTIVE_IA5String] = ASN1_IA5STR, + [DIRECTIVE_UTCTime] = ASN1_UNITIM, + [DIRECTIVE_GeneralizedTime] = ASN1_GENTIM, + [DIRECTIVE_GraphicString] = ASN1_GRASTR, + [DIRECTIVE_VisibleString] = ASN1_VISSTR, + [DIRECTIVE_GeneralString] = ASN1_GENSTR, + [DIRECTIVE_UniversalString] = ASN1_UNITIM, + [DIRECTIVE_CHARACTER] = ASN1_CHRSTR, + [DIRECTIVE_BMPString] = ASN1_BMPSTR, +}; + +static const char asn1_classes[4][5] = { + [ASN1_UNIV] = "UNIV", + [ASN1_APPL] = "APPL", + [ASN1_CONT] = "CONT", + [ASN1_PRIV] = "PRIV" +}; + +static const char asn1_methods[2][5] = { + [ASN1_UNIV] = "PRIM", + [ASN1_APPL] = "CONS" +}; + +static const char *const asn1_universal_tags[32] = { + "EOC", + "BOOL", + "INT", + "BTS", + "OTS", + "NULL", + "OID", + "ODE", + "EXT", + "REAL", + "ENUM", + "EPDV", + "UTF8STR", + "RELOID", + NULL, /* 14 */ + NULL, /* 15 */ + "SEQ", + "SET", + "NUMSTR", + "PRNSTR", + "TEXSTR", + "VIDSTR", + "IA5STR", + "UNITIM", + "GENTIM", + "GRASTR", + "VISSTR", + "GENSTR", + "UNISTR", + "CHRSTR", + "BMPSTR", + NULL /* 31 */ +}; + +static const char *filename; +static const char *grammar_name; +static const char *outputname; +static const char *headername; + +static const char *const directives[NR__DIRECTIVES] = { +#define _(X) [DIRECTIVE_##X] = #X + _(ABSENT), + _(ALL), + _(ANY), + _(APPLICATION), + _(AUTOMATIC), + _(BEGIN), + _(BIT), + _(BMPString), + _(BOOLEAN), + _(BY), + _(CHARACTER), + _(CHOICE), + _(CLASS), + _(COMPONENT), + _(COMPONENTS), + _(CONSTRAINED), + _(CONTAINING), + _(DEFAULT), + _(DEFINED), + _(DEFINITIONS), + _(EMBEDDED), + _(ENCODED), + [DIRECTIVE_ENCODING_CONTROL] = "ENCODING-CONTROL", + _(END), + _(ENUMERATED), + _(EXCEPT), + _(EXPLICIT), + _(EXPORTS), + _(EXTENSIBILITY), + _(EXTERNAL), + _(FALSE), + _(FROM), + _(GeneralString), + _(GeneralizedTime), + _(GraphicString), + _(IA5String), + _(IDENTIFIER), + _(IMPLICIT), + _(IMPLIED), + _(IMPORTS), + _(INCLUDES), + _(INSTANCE), + _(INSTRUCTIONS), + _(INTEGER), + _(INTERSECTION), + _(ISO646String), + _(MAX), + _(MIN), + [DIRECTIVE_MINUS_INFINITY] = "MINUS-INFINITY", + [DIRECTIVE_NULL] = "NULL", + _(NumericString), + _(OBJECT), + _(OCTET), + _(OF), + _(OPTIONAL), + _(ObjectDescriptor), + _(PATTERN), + _(PDV), + [DIRECTIVE_PLUS_INFINITY] = "PLUS-INFINITY", + _(PRESENT), + _(PRIVATE), + _(PrintableString), + _(REAL), + [DIRECTIVE_RELATIVE_OID] = "RELATIVE-OID", + _(SEQUENCE), + _(SET), + _(SIZE), + _(STRING), + _(SYNTAX), + _(T61String), + _(TAGS), + _(TRUE), + _(TeletexString), + _(UNION), + _(UNIQUE), + _(UNIVERSAL), + _(UTCTime), + _(UTF8String), + _(UniversalString), + _(VideotexString), + _(VisibleString), + _(WITH) +}; + +struct action { + struct action *next; + char *name; + unsigned char index; +}; + +static struct action *action_list; +static unsigned nr_actions; + +struct token { + unsigned short line; + enum token_type token_type : 8; + unsigned char size; + struct action *action; + char *content; + struct type *type; +}; + +static struct token *token_list; +static unsigned nr_tokens; +static bool verbose_opt; +static bool debug_opt; + +#define verbose(fmt, ...) do { if (verbose_opt) printf(fmt, ## __VA_ARGS__); } while (0) +#define debug(fmt, ...) do { if (debug_opt) printf(fmt, ## __VA_ARGS__); } while (0) + +static int directive_compare(const void *_key, const void *_pdir) +{ + const struct token *token = _key; + const char *const *pdir = _pdir, *dir = *pdir; + size_t dlen, clen; + int val; + + dlen = strlen(dir); + clen = (dlen < token->size) ? dlen : token->size; + + //debug("cmp(%s,%s) = ", token->content, dir); + + val = memcmp(token->content, dir, clen); + if (val != 0) { + //debug("%d [cmp]\n", val); + return val; + } + + if (dlen == token->size) { + //debug("0\n"); + return 0; + } + //debug("%d\n", (int)dlen - (int)token->size); + return dlen - token->size; /* shorter -> negative */ +} + +/* + * Tokenise an ASN.1 grammar + */ +static void tokenise(char *buffer, char *end) +{ + struct token *tokens; + char *line, *nl, *start, *p, *q; + unsigned tix, lineno; + + /* Assume we're going to have half as many tokens as we have + * characters + */ + token_list = tokens = calloc((end - buffer) / 2, sizeof(struct token)); + if (!tokens) { + perror(NULL); + exit(1); + } + tix = 0; + + lineno = 0; + while (buffer < end) { + /* First of all, break out a line */ + lineno++; + line = buffer; + nl = memchr(line, '\n', end - buffer); + if (!nl) { + buffer = nl = end; + } else { + buffer = nl + 1; + *nl = '\0'; + } + + /* Remove "--" comments */ + p = line; + next_comment: + while ((p = memchr(p, '-', nl - p))) { + if (p[1] == '-') { + /* Found a comment; see if there's a terminator */ + q = p + 2; + while ((q = memchr(q, '-', nl - q))) { + if (q[1] == '-') { + /* There is - excise the comment */ + q += 2; + memmove(p, q, nl - q); + goto next_comment; + } + q++; + } + *p = '\0'; + nl = p; + break; + } else { + p++; + } + } + + p = line; + while (p < nl) { + /* Skip white space */ + while (p < nl && isspace(*p)) + *(p++) = 0; + if (p >= nl) + break; + + tokens[tix].line = lineno; + start = p; + + /* Handle string tokens */ + if (isalpha(*p)) { + const char **dir; + + /* Can be a directive, type name or element + * name. Find the end of the name. + */ + q = p + 1; + while (q < nl && (isalnum(*q) || *q == '-' || *q == '_')) + q++; + tokens[tix].size = q - p; + p = q; + + tokens[tix].content = malloc(tokens[tix].size + 1); + if (!tokens[tix].content) { + perror(NULL); + exit(1); + } + memcpy(tokens[tix].content, start, tokens[tix].size); + tokens[tix].content[tokens[tix].size] = 0; + + /* If it begins with a lowercase letter then + * it's an element name + */ + if (islower(tokens[tix].content[0])) { + tokens[tix++].token_type = TOKEN_ELEMENT_NAME; + continue; + } + + /* Otherwise we need to search the directive + * table + */ + dir = bsearch(&tokens[tix], directives, + sizeof(directives) / sizeof(directives[1]), + sizeof(directives[1]), + directive_compare); + if (dir) { + tokens[tix++].token_type = dir - directives; + continue; + } + + tokens[tix++].token_type = TOKEN_TYPE_NAME; + continue; + } + + /* Handle numbers */ + if (isdigit(*p)) { + /* Find the end of the number */ + q = p + 1; + while (q < nl && (isdigit(*q))) + q++; + tokens[tix].size = q - p; + p = q; + tokens[tix].content = malloc(tokens[tix].size + 1); + if (!tokens[tix].content) { + perror(NULL); + exit(1); + } + memcpy(tokens[tix].content, start, tokens[tix].size); + tokens[tix].content[tokens[tix].size] = 0; + tokens[tix++].token_type = TOKEN_NUMBER; + continue; + } + + if (nl - p >= 3) { + if (memcmp(p, "::=", 3) == 0) { + p += 3; + tokens[tix].size = 3; + tokens[tix].content = "::="; + tokens[tix++].token_type = TOKEN_ASSIGNMENT; + continue; + } + } + + if (nl - p >= 2) { + if (memcmp(p, "({", 2) == 0) { + p += 2; + tokens[tix].size = 2; + tokens[tix].content = "({"; + tokens[tix++].token_type = TOKEN_OPEN_ACTION; + continue; + } + if (memcmp(p, "})", 2) == 0) { + p += 2; + tokens[tix].size = 2; + tokens[tix].content = "})"; + tokens[tix++].token_type = TOKEN_CLOSE_ACTION; + continue; + } + } + + if (nl - p >= 1) { + tokens[tix].size = 1; + switch (*p) { + case '{': + p += 1; + tokens[tix].content = "{"; + tokens[tix++].token_type = TOKEN_OPEN_CURLY; + continue; + case '}': + p += 1; + tokens[tix].content = "}"; + tokens[tix++].token_type = TOKEN_CLOSE_CURLY; + continue; + case '[': + p += 1; + tokens[tix].content = "["; + tokens[tix++].token_type = TOKEN_OPEN_SQUARE; + continue; + case ']': + p += 1; + tokens[tix].content = "]"; + tokens[tix++].token_type = TOKEN_CLOSE_SQUARE; + continue; + case ',': + p += 1; + tokens[tix].content = ","; + tokens[tix++].token_type = TOKEN_COMMA; + continue; + default: + break; + } + } + + fprintf(stderr, "%s:%u: Unknown character in grammar: '%c'\n", + filename, lineno, *p); + exit(1); + } + } + + nr_tokens = tix; + verbose("Extracted %u tokens\n", nr_tokens); + +#if 0 + { + int n; + for (n = 0; n < nr_tokens; n++) + debug("Token %3u: '%s'\n", n, token_list[n].content); + } +#endif +} + +static void build_type_list(void); +static void parse(void); +static void dump_elements(void); +static void render(FILE *out, FILE *hdr); + +/* + * + */ +int main(int argc, char **argv) +{ + struct stat st; + ssize_t readlen; + FILE *out, *hdr; + char *buffer, *p; + char *kbuild_verbose; + int fd; + + kbuild_verbose = getenv("KBUILD_VERBOSE"); + if (kbuild_verbose) + verbose_opt = atoi(kbuild_verbose); + + while (argc > 4) { + if (strcmp(argv[1], "-v") == 0) + verbose_opt = true; + else if (strcmp(argv[1], "-d") == 0) + debug_opt = true; + else + break; + memmove(&argv[1], &argv[2], (argc - 2) * sizeof(char *)); + argc--; + } + + if (argc != 4) { + fprintf(stderr, "Format: %s [-v] [-d] \n", + argv[0]); + exit(2); + } + + filename = argv[1]; + outputname = argv[2]; + headername = argv[3]; + + fd = open(filename, O_RDONLY); + if (fd < 0) { + perror(filename); + exit(1); + } + + if (fstat(fd, &st) < 0) { + perror(filename); + exit(1); + } + + if (!(buffer = malloc(st.st_size + 1))) { + perror(NULL); + exit(1); + } + + if ((readlen = read(fd, buffer, st.st_size)) < 0) { + perror(filename); + exit(1); + } + + if (close(fd) < 0) { + perror(filename); + exit(1); + } + + if (readlen != st.st_size) { + fprintf(stderr, "%s: Short read\n", filename); + exit(1); + } + + p = strrchr(argv[1], '/'); + p = p ? p + 1 : argv[1]; + grammar_name = strdup(p); + if (!p) { + perror(NULL); + exit(1); + } + p = strchr(grammar_name, '.'); + if (p) + *p = '\0'; + + buffer[readlen] = 0; + tokenise(buffer, buffer + readlen); + build_type_list(); + parse(); + dump_elements(); + + out = fopen(outputname, "w"); + if (!out) { + perror(outputname); + exit(1); + } + + hdr = fopen(headername, "w"); + if (!hdr) { + perror(headername); + exit(1); + } + + render(out, hdr); + + if (fclose(out) < 0) { + perror(outputname); + exit(1); + } + + if (fclose(hdr) < 0) { + perror(headername); + exit(1); + } + + return 0; +} + +enum compound { + NOT_COMPOUND, + SET, + SET_OF, + SEQUENCE, + SEQUENCE_OF, + CHOICE, + ANY, + TYPE_REF, + TAG_OVERRIDE +}; + +struct element { + struct type *type_def; + struct token *name; + struct token *type; + struct action *action; + struct element *children; + struct element *next; + struct element *render_next; + struct element *list_next; + uint8_t n_elements; + enum compound compound : 8; + enum asn1_class class : 8; + enum asn1_method method : 8; + uint8_t tag; + unsigned entry_index; + unsigned flags; +#define ELEMENT_IMPLICIT 0x0001 +#define ELEMENT_EXPLICIT 0x0002 +#define ELEMENT_TAG_SPECIFIED 0x0004 +#define ELEMENT_RENDERED 0x0008 +#define ELEMENT_SKIPPABLE 0x0010 +#define ELEMENT_CONDITIONAL 0x0020 +}; + +struct type { + struct token *name; + struct token *def; + struct element *element; + unsigned ref_count; + unsigned flags; +#define TYPE_STOP_MARKER 0x0001 +#define TYPE_BEGIN 0x0002 +}; + +static struct type *type_list; +static struct type **type_index; +static unsigned nr_types; + +static int type_index_compare(const void *_a, const void *_b) +{ + const struct type *const *a = _a, *const *b = _b; + + if ((*a)->name->size != (*b)->name->size) + return (*a)->name->size - (*b)->name->size; + else + return memcmp((*a)->name->content, (*b)->name->content, + (*a)->name->size); +} + +static int type_finder(const void *_key, const void *_ti) +{ + const struct token *token = _key; + const struct type *const *ti = _ti; + const struct type *type = *ti; + + if (token->size != type->name->size) + return token->size - type->name->size; + else + return memcmp(token->content, type->name->content, + token->size); +} + +/* + * Build up a list of types and a sorted index to that list. + */ +static void build_type_list(void) +{ + struct type *types; + unsigned nr, t, n; + + nr = 0; + for (n = 0; n < nr_tokens - 1; n++) + if (token_list[n + 0].token_type == TOKEN_TYPE_NAME && + token_list[n + 1].token_type == TOKEN_ASSIGNMENT) + nr++; + + if (nr == 0) { + fprintf(stderr, "%s: No defined types\n", filename); + exit(1); + } + + nr_types = nr; + types = type_list = calloc(nr + 1, sizeof(type_list[0])); + if (!type_list) { + perror(NULL); + exit(1); + } + type_index = calloc(nr, sizeof(type_index[0])); + if (!type_index) { + perror(NULL); + exit(1); + } + + t = 0; + types[t].flags |= TYPE_BEGIN; + for (n = 0; n < nr_tokens - 1; n++) { + if (token_list[n + 0].token_type == TOKEN_TYPE_NAME && + token_list[n + 1].token_type == TOKEN_ASSIGNMENT) { + types[t].name = &token_list[n]; + type_index[t] = &types[t]; + t++; + } + } + types[t].name = &token_list[n + 1]; + types[t].flags |= TYPE_STOP_MARKER; + + qsort(type_index, nr, sizeof(type_index[0]), type_index_compare); + + verbose("Extracted %u types\n", nr_types); +#if 0 + for (n = 0; n < nr_types; n++) { + struct type *type = type_index[n]; + debug("- %*.*s\n", type->name->content); + } +#endif +} + +static struct element *parse_type(struct token **_cursor, struct token *stop, + struct token *name); + +/* + * Parse the token stream + */ +static void parse(void) +{ + struct token *cursor; + struct type *type; + + /* Parse one type definition statement at a time */ + type = type_list; + do { + cursor = type->name; + + if (cursor[0].token_type != TOKEN_TYPE_NAME || + cursor[1].token_type != TOKEN_ASSIGNMENT) + abort(); + cursor += 2; + + type->element = parse_type(&cursor, type[1].name, NULL); + type->element->type_def = type; + + if (cursor != type[1].name) { + fprintf(stderr, "%s:%d: Parse error at token '%s'\n", + filename, cursor->line, cursor->content); + exit(1); + } + + } while (type++, !(type->flags & TYPE_STOP_MARKER)); + + verbose("Extracted %u actions\n", nr_actions); +} + +static struct element *element_list; + +static struct element *alloc_elem(struct token *type) +{ + struct element *e = calloc(1, sizeof(*e)); + if (!e) { + perror(NULL); + exit(1); + } + e->list_next = element_list; + element_list = e; + return e; +} + +static struct element *parse_compound(struct token **_cursor, struct token *end, + int alternates); + +/* + * Parse one type definition statement + */ +static struct element *parse_type(struct token **_cursor, struct token *end, + struct token *name) +{ + struct element *top, *element; + struct action *action, **ppaction; + struct token *cursor = *_cursor; + struct type **ref; + char *p; + int labelled = 0, implicit = 0; + + top = element = alloc_elem(cursor); + element->class = ASN1_UNIV; + element->method = ASN1_PRIM; + element->tag = token_to_tag[cursor->token_type]; + element->name = name; + + /* Extract the tag value if one given */ + if (cursor->token_type == TOKEN_OPEN_SQUARE) { + cursor++; + if (cursor >= end) + goto overrun_error; + switch (cursor->token_type) { + case DIRECTIVE_UNIVERSAL: + element->class = ASN1_UNIV; + cursor++; + break; + case DIRECTIVE_APPLICATION: + element->class = ASN1_APPL; + cursor++; + break; + case TOKEN_NUMBER: + element->class = ASN1_CONT; + break; + case DIRECTIVE_PRIVATE: + element->class = ASN1_PRIV; + cursor++; + break; + default: + fprintf(stderr, "%s:%d: Unrecognised tag class token '%s'\n", + filename, cursor->line, cursor->content); + exit(1); + } + + if (cursor >= end) + goto overrun_error; + if (cursor->token_type != TOKEN_NUMBER) { + fprintf(stderr, "%s:%d: Missing tag number '%s'\n", + filename, cursor->line, cursor->content); + exit(1); + } + + element->tag &= ~0x1f; + element->tag |= strtoul(cursor->content, &p, 10); + element->flags |= ELEMENT_TAG_SPECIFIED; + if (p - cursor->content != cursor->size) + abort(); + cursor++; + + if (cursor >= end) + goto overrun_error; + if (cursor->token_type != TOKEN_CLOSE_SQUARE) { + fprintf(stderr, "%s:%d: Missing closing square bracket '%s'\n", + filename, cursor->line, cursor->content); + exit(1); + } + cursor++; + if (cursor >= end) + goto overrun_error; + labelled = 1; + } + + /* Handle implicit and explicit markers */ + if (cursor->token_type == DIRECTIVE_IMPLICIT) { + element->flags |= ELEMENT_IMPLICIT; + implicit = 1; + cursor++; + if (cursor >= end) + goto overrun_error; + } else if (cursor->token_type == DIRECTIVE_EXPLICIT) { + element->flags |= ELEMENT_EXPLICIT; + cursor++; + if (cursor >= end) + goto overrun_error; + } + + if (labelled) { + if (!implicit) + element->method |= ASN1_CONS; + element->compound = implicit ? TAG_OVERRIDE : SEQUENCE; + element->children = alloc_elem(cursor); + element = element->children; + element->class = ASN1_UNIV; + element->method = ASN1_PRIM; + element->tag = token_to_tag[cursor->token_type]; + element->name = name; + } + + /* Extract the type we're expecting here */ + element->type = cursor; + switch (cursor->token_type) { + case DIRECTIVE_ANY: + element->compound = ANY; + cursor++; + break; + + case DIRECTIVE_NULL: + case DIRECTIVE_BOOLEAN: + case DIRECTIVE_ENUMERATED: + case DIRECTIVE_INTEGER: + element->compound = NOT_COMPOUND; + cursor++; + break; + + case DIRECTIVE_EXTERNAL: + element->method = ASN1_CONS; + + case DIRECTIVE_BMPString: + case DIRECTIVE_GeneralString: + case DIRECTIVE_GraphicString: + case DIRECTIVE_IA5String: + case DIRECTIVE_ISO646String: + case DIRECTIVE_NumericString: + case DIRECTIVE_PrintableString: + case DIRECTIVE_T61String: + case DIRECTIVE_TeletexString: + case DIRECTIVE_UniversalString: + case DIRECTIVE_UTF8String: + case DIRECTIVE_VideotexString: + case DIRECTIVE_VisibleString: + case DIRECTIVE_ObjectDescriptor: + case DIRECTIVE_GeneralizedTime: + case DIRECTIVE_UTCTime: + element->compound = NOT_COMPOUND; + cursor++; + break; + + case DIRECTIVE_BIT: + case DIRECTIVE_OCTET: + element->compound = NOT_COMPOUND; + cursor++; + if (cursor >= end) + goto overrun_error; + if (cursor->token_type != DIRECTIVE_STRING) + goto parse_error; + cursor++; + break; + + case DIRECTIVE_OBJECT: + element->compound = NOT_COMPOUND; + cursor++; + if (cursor >= end) + goto overrun_error; + if (cursor->token_type != DIRECTIVE_IDENTIFIER) + goto parse_error; + cursor++; + break; + + case TOKEN_TYPE_NAME: + element->compound = TYPE_REF; + ref = bsearch(cursor, type_index, nr_types, sizeof(type_index[0]), + type_finder); + if (!ref) { + fprintf(stderr, "%s:%d: Type '%s' undefined\n", + filename, cursor->line, cursor->content); + exit(1); + } + cursor->type = *ref; + (*ref)->ref_count++; + cursor++; + break; + + case DIRECTIVE_CHOICE: + element->compound = CHOICE; + cursor++; + element->children = parse_compound(&cursor, end, 1); + break; + + case DIRECTIVE_SEQUENCE: + element->compound = SEQUENCE; + element->method = ASN1_CONS; + cursor++; + if (cursor >= end) + goto overrun_error; + if (cursor->token_type == DIRECTIVE_OF) { + element->compound = SEQUENCE_OF; + cursor++; + if (cursor >= end) + goto overrun_error; + element->children = parse_type(&cursor, end, NULL); + } else { + element->children = parse_compound(&cursor, end, 0); + } + break; + + case DIRECTIVE_SET: + element->compound = SET; + element->method = ASN1_CONS; + cursor++; + if (cursor >= end) + goto overrun_error; + if (cursor->token_type == DIRECTIVE_OF) { + element->compound = SET_OF; + cursor++; + if (cursor >= end) + goto parse_error; + element->children = parse_type(&cursor, end, NULL); + } else { + element->children = parse_compound(&cursor, end, 1); + } + break; + + default: + fprintf(stderr, "%s:%d: Token '%s' does not introduce a type\n", + filename, cursor->line, cursor->content); + exit(1); + } + + /* Handle elements that are optional */ + if (cursor < end && (cursor->token_type == DIRECTIVE_OPTIONAL || + cursor->token_type == DIRECTIVE_DEFAULT) + ) { + cursor++; + top->flags |= ELEMENT_SKIPPABLE; + } + + if (cursor < end && cursor->token_type == TOKEN_OPEN_ACTION) { + cursor++; + if (cursor >= end) + goto overrun_error; + if (cursor->token_type != TOKEN_ELEMENT_NAME) { + fprintf(stderr, "%s:%d: Token '%s' is not an action function name\n", + filename, cursor->line, cursor->content); + exit(1); + } + + action = malloc(sizeof(struct action)); + if (!action) { + perror(NULL); + exit(1); + } + action->index = 0; + action->name = cursor->content; + + for (ppaction = &action_list; + *ppaction; + ppaction = &(*ppaction)->next + ) { + int cmp = strcmp(action->name, (*ppaction)->name); + if (cmp == 0) { + free(action); + action = *ppaction; + goto found; + } + if (cmp < 0) { + action->next = *ppaction; + *ppaction = action; + nr_actions++; + goto found; + } + } + action->next = NULL; + *ppaction = action; + nr_actions++; + found: + + element->action = action; + cursor->action = action; + cursor++; + if (cursor >= end) + goto overrun_error; + if (cursor->token_type != TOKEN_CLOSE_ACTION) { + fprintf(stderr, "%s:%d: Missing close action, got '%s'\n", + filename, cursor->line, cursor->content); + exit(1); + } + cursor++; + } + + *_cursor = cursor; + return top; + +parse_error: + fprintf(stderr, "%s:%d: Unexpected token '%s'\n", + filename, cursor->line, cursor->content); + exit(1); + +overrun_error: + fprintf(stderr, "%s: Unexpectedly hit EOF\n", filename); + exit(1); +} + +/* + * Parse a compound type list + */ +static struct element *parse_compound(struct token **_cursor, struct token *end, + int alternates) +{ + struct element *children, **child_p = &children, *element; + struct token *cursor = *_cursor, *name; + + if (cursor->token_type != TOKEN_OPEN_CURLY) { + fprintf(stderr, "%s:%d: Expected compound to start with brace not '%s'\n", + filename, cursor->line, cursor->content); + exit(1); + } + cursor++; + if (cursor >= end) + goto overrun_error; + + if (cursor->token_type == TOKEN_OPEN_CURLY) { + fprintf(stderr, "%s:%d: Empty compound\n", + filename, cursor->line); + exit(1); + } + + for (;;) { + name = NULL; + if (cursor->token_type == TOKEN_ELEMENT_NAME) { + name = cursor; + cursor++; + if (cursor >= end) + goto overrun_error; + } + + element = parse_type(&cursor, end, name); + if (alternates) + element->flags |= ELEMENT_SKIPPABLE | ELEMENT_CONDITIONAL; + + *child_p = element; + child_p = &element->next; + + if (cursor >= end) + goto overrun_error; + if (cursor->token_type != TOKEN_COMMA) + break; + cursor++; + if (cursor >= end) + goto overrun_error; + } + + children->flags &= ~ELEMENT_CONDITIONAL; + + if (cursor->token_type != TOKEN_CLOSE_CURLY) { + fprintf(stderr, "%s:%d: Expected compound closure, got '%s'\n", + filename, cursor->line, cursor->content); + exit(1); + } + cursor++; + + *_cursor = cursor; + return children; + +overrun_error: + fprintf(stderr, "%s: Unexpectedly hit EOF\n", filename); + exit(1); +} + +static void dump_element(const struct element *e, int level) +{ + const struct element *c; + const struct type *t = e->type_def; + const char *name = e->name ? e->name->content : "."; + const char *tname = t && t->name ? t->name->content : "."; + char tag[32]; + + if (e->class == 0 && e->method == 0 && e->tag == 0) + strcpy(tag, "<...>"); + else if (e->class == ASN1_UNIV) + sprintf(tag, "%s %s %s", + asn1_classes[e->class], + asn1_methods[e->method], + asn1_universal_tags[e->tag]); + else + sprintf(tag, "%s %s %u", + asn1_classes[e->class], + asn1_methods[e->method], + e->tag); + + printf("%c%c%c%c%c %c %*s[*] \e[33m%s\e[m %s %s \e[35m%s\e[m\n", + e->flags & ELEMENT_IMPLICIT ? 'I' : '-', + e->flags & ELEMENT_EXPLICIT ? 'E' : '-', + e->flags & ELEMENT_TAG_SPECIFIED ? 'T' : '-', + e->flags & ELEMENT_SKIPPABLE ? 'S' : '-', + e->flags & ELEMENT_CONDITIONAL ? 'C' : '-', + "-tTqQcaro"[e->compound], + level, "", + tag, + tname, + name, + e->action ? e->action->name : ""); + if (e->compound == TYPE_REF) + dump_element(e->type->type->element, level + 3); + else + for (c = e->children; c; c = c->next) + dump_element(c, level + 3); +} + +static void dump_elements(void) +{ + if (debug_opt) + dump_element(type_list[0].element, 0); +} + +static void render_element(FILE *out, struct element *e, struct element *tag); +static void render_out_of_line_list(FILE *out); + +static int nr_entries; +static int render_depth = 1; +static struct element *render_list, **render_list_p = &render_list; + +__attribute__((format(printf, 2, 3))) +static void render_opcode(FILE *out, const char *fmt, ...) +{ + va_list va; + + if (out) { + fprintf(out, "\t[%4d] =%*s", nr_entries, render_depth, ""); + va_start(va, fmt); + vfprintf(out, fmt, va); + va_end(va); + } + nr_entries++; +} + +__attribute__((format(printf, 2, 3))) +static void render_more(FILE *out, const char *fmt, ...) +{ + va_list va; + + if (out) { + va_start(va, fmt); + vfprintf(out, fmt, va); + va_end(va); + } +} + +/* + * Render the grammar into a state machine definition. + */ +static void render(FILE *out, FILE *hdr) +{ + struct element *e; + struct action *action; + struct type *root; + int index; + + fprintf(hdr, "/*\n"); + fprintf(hdr, " * Automatically generated by asn1_compiler. Do not edit\n"); + fprintf(hdr, " *\n"); + fprintf(hdr, " * ASN.1 parser for %s\n", grammar_name); + fprintf(hdr, " */\n"); + fprintf(hdr, "#include \n"); + fprintf(hdr, "\n"); + fprintf(hdr, "extern const struct asn1_decoder %s_decoder;\n", grammar_name); + if (ferror(hdr)) { + perror(headername); + exit(1); + } + + fprintf(out, "/*\n"); + fprintf(out, " * Automatically generated by asn1_compiler. Do not edit\n"); + fprintf(out, " *\n"); + fprintf(out, " * ASN.1 parser for %s\n", grammar_name); + fprintf(out, " */\n"); + fprintf(out, "#include \n"); + fprintf(out, "#include \"%s.asn1.h\"\n", grammar_name); + fprintf(out, "\n"); + if (ferror(out)) { + perror(outputname); + exit(1); + } + + /* Tabulate the action functions we might have to call */ + fprintf(hdr, "\n"); + index = 0; + for (action = action_list; action; action = action->next) { + action->index = index++; + fprintf(hdr, + "extern int %s(void *, size_t, unsigned char," + " const void *, size_t);\n", + action->name); + } + fprintf(hdr, "\n"); + + fprintf(out, "enum %s_actions {\n", grammar_name); + for (action = action_list; action; action = action->next) + fprintf(out, "\tACT_%s = %u,\n", + action->name, action->index); + fprintf(out, "\tNR__%s_actions = %u\n", grammar_name, nr_actions); + fprintf(out, "};\n"); + + fprintf(out, "\n"); + fprintf(out, "static const asn1_action_t %s_action_table[NR__%s_actions] = {\n", + grammar_name, grammar_name); + for (action = action_list; action; action = action->next) + fprintf(out, "\t[%4u] = %s,\n", action->index, action->name); + fprintf(out, "};\n"); + + if (ferror(out)) { + perror(outputname); + exit(1); + } + + /* We do two passes - the first one calculates all the offsets */ + verbose("Pass 1\n"); + nr_entries = 0; + root = &type_list[0]; + render_element(NULL, root->element, NULL); + render_opcode(NULL, "ASN1_OP_COMPLETE,\n"); + render_out_of_line_list(NULL); + + for (e = element_list; e; e = e->list_next) + e->flags &= ~ELEMENT_RENDERED; + + /* And then we actually render */ + verbose("Pass 2\n"); + fprintf(out, "\n"); + fprintf(out, "static const unsigned char %s_machine[] = {\n", + grammar_name); + + nr_entries = 0; + root = &type_list[0]; + render_element(out, root->element, NULL); + render_opcode(out, "ASN1_OP_COMPLETE,\n"); + render_out_of_line_list(out); + + fprintf(out, "};\n"); + + fprintf(out, "\n"); + fprintf(out, "const struct asn1_decoder %s_decoder = {\n", grammar_name); + fprintf(out, "\t.machine = %s_machine,\n", grammar_name); + fprintf(out, "\t.machlen = sizeof(%s_machine),\n", grammar_name); + fprintf(out, "\t.actions = %s_action_table,\n", grammar_name); + fprintf(out, "};\n"); +} + +/* + * Render the out-of-line elements + */ +static void render_out_of_line_list(FILE *out) +{ + struct element *e, *ce; + const char *act; + int entry; + + while ((e = render_list)) { + render_list = e->render_next; + if (!render_list) + render_list_p = &render_list; + + render_more(out, "\n"); + e->entry_index = entry = nr_entries; + render_depth++; + for (ce = e->children; ce; ce = ce->next) + render_element(out, ce, NULL); + render_depth--; + + act = e->action ? "_ACT" : ""; + switch (e->compound) { + case SEQUENCE: + render_opcode(out, "ASN1_OP_END_SEQ%s,\n", act); + break; + case SEQUENCE_OF: + render_opcode(out, "ASN1_OP_END_SEQ_OF%s,\n", act); + render_opcode(out, "_jump_target(%u),\n", entry); + break; + case SET: + render_opcode(out, "ASN1_OP_END_SET%s,\n", act); + break; + case SET_OF: + render_opcode(out, "ASN1_OP_END_SET_OF%s,\n", act); + render_opcode(out, "_jump_target(%u),\n", entry); + break; + default: + break; + } + if (e->action) + render_opcode(out, "_action(ACT_%s),\n", + e->action->name); + render_opcode(out, "ASN1_OP_RETURN,\n"); + } +} + +/* + * Render an element. + */ +static void render_element(FILE *out, struct element *e, struct element *tag) +{ + struct element *ec, *x; + const char *cond, *act; + int entry, skippable = 0, outofline = 0; + + if (e->flags & ELEMENT_SKIPPABLE || + (tag && tag->flags & ELEMENT_SKIPPABLE)) + skippable = 1; + + if ((e->type_def && e->type_def->ref_count > 1) || + skippable) + outofline = 1; + + if (e->type_def && out) { + render_more(out, "\t// %s\n", e->type_def->name->content); + } + + /* Render the operation */ + cond = (e->flags & ELEMENT_CONDITIONAL || + (tag && tag->flags & ELEMENT_CONDITIONAL)) ? "COND_" : ""; + act = e->action ? "_ACT" : ""; + switch (e->compound) { + case ANY: + render_opcode(out, "ASN1_OP_%sMATCH_ANY%s%s,", + cond, act, skippable ? "_OR_SKIP" : ""); + if (e->name) + render_more(out, "\t\t// %s", e->name->content); + render_more(out, "\n"); + goto dont_render_tag; + + case TAG_OVERRIDE: + render_element(out, e->children, e); + return; + + case SEQUENCE: + case SEQUENCE_OF: + case SET: + case SET_OF: + render_opcode(out, "ASN1_OP_%sMATCH%s%s,", + cond, + outofline ? "_JUMP" : "", + skippable ? "_OR_SKIP" : ""); + break; + + case CHOICE: + goto dont_render_tag; + + case TYPE_REF: + if (e->class == ASN1_UNIV && e->method == ASN1_PRIM && e->tag == 0) + goto dont_render_tag; + default: + render_opcode(out, "ASN1_OP_%sMATCH%s%s,", + cond, act, + skippable ? "_OR_SKIP" : ""); + break; + } + + x = tag ?: e; + if (x->name) + render_more(out, "\t\t// %s", x->name->content); + render_more(out, "\n"); + + /* Render the tag */ + if (!tag || !(tag->flags & ELEMENT_TAG_SPECIFIED)) + tag = e; + + if (tag->class == ASN1_UNIV && + tag->tag != 14 && + tag->tag != 15 && + tag->tag != 31) + render_opcode(out, "_tag(%s, %s, %s),\n", + asn1_classes[tag->class], + asn1_methods[tag->method | e->method], + asn1_universal_tags[tag->tag]); + else + render_opcode(out, "_tagn(%s, %s, %2u),\n", + asn1_classes[tag->class], + asn1_methods[tag->method | e->method], + tag->tag); + tag = NULL; +dont_render_tag: + + /* Deal with compound types */ + switch (e->compound) { + case TYPE_REF: + render_element(out, e->type->type->element, tag); + if (e->action) + render_opcode(out, "ASN1_OP_%sACT,\n", + skippable ? "MAYBE_" : ""); + break; + + case SEQUENCE: + if (outofline) { + /* Render out-of-line for multiple use or + * skipability */ + render_opcode(out, "_jump_target(%u),", e->entry_index); + if (e->type_def && e->type_def->name) + render_more(out, "\t\t// --> %s", + e->type_def->name->content); + render_more(out, "\n"); + if (!(e->flags & ELEMENT_RENDERED)) { + e->flags |= ELEMENT_RENDERED; + *render_list_p = e; + render_list_p = &e->render_next; + } + return; + } else { + /* Render inline for single use */ + render_depth++; + for (ec = e->children; ec; ec = ec->next) + render_element(out, ec, NULL); + render_depth--; + render_opcode(out, "ASN1_OP_END_SEQ%s,\n", act); + } + break; + + case SEQUENCE_OF: + case SET_OF: + if (outofline) { + /* Render out-of-line for multiple use or + * skipability */ + render_opcode(out, "_jump_target(%u),", e->entry_index); + if (e->type_def && e->type_def->name) + render_more(out, "\t\t// --> %s", + e->type_def->name->content); + render_more(out, "\n"); + if (!(e->flags & ELEMENT_RENDERED)) { + e->flags |= ELEMENT_RENDERED; + *render_list_p = e; + render_list_p = &e->render_next; + } + return; + } else { + /* Render inline for single use */ + entry = nr_entries; + render_depth++; + render_element(out, e->children, NULL); + render_depth--; + if (e->compound == SEQUENCE_OF) + render_opcode(out, "ASN1_OP_END_SEQ_OF%s,\n", act); + else + render_opcode(out, "ASN1_OP_END_SET_OF%s,\n", act); + render_opcode(out, "_jump_target(%u),\n", entry); + } + break; + + case SET: + /* I can't think of a nice way to do SET support without having + * a stack of bitmasks to make sure no element is repeated. + * The bitmask has also to be checked that no non-optional + * elements are left out whilst not preventing optional + * elements from being left out. + */ + fprintf(stderr, "The ASN.1 SET type is not currently supported.\n"); + exit(1); + + case CHOICE: + for (ec = e->children; ec; ec = ec->next) + render_element(out, ec, ec); + if (!skippable) + render_opcode(out, "ASN1_OP_COND_FAIL,\n"); + if (e->action) + render_opcode(out, "ASN1_OP_ACT,\n"); + break; + + default: + break; + } + + if (e->action) + render_opcode(out, "_action(ACT_%s),\n", e->action->name); +} diff --git a/src/net/scripts/atomic/atomic-tbl.sh b/src/net/scripts/atomic/atomic-tbl.sh new file mode 100755 index 0000000..81d5c32 --- /dev/null +++ b/src/net/scripts/atomic/atomic-tbl.sh @@ -0,0 +1,186 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0 +# helpers for dealing with atomics.tbl + +#meta_in(meta, match) +meta_in() +{ + case "$1" in + [$2]) return 0;; + esac + + return 1 +} + +#meta_has_ret(meta) +meta_has_ret() +{ + meta_in "$1" "bBiIfFlR" +} + +#meta_has_acquire(meta) +meta_has_acquire() +{ + meta_in "$1" "BFIlR" +} + +#meta_has_release(meta) +meta_has_release() +{ + meta_in "$1" "BFIRs" +} + +#meta_has_relaxed(meta) +meta_has_relaxed() +{ + meta_in "$1" "BFIR" +} + +#find_fallback_template(pfx, name, sfx, order) +find_fallback_template() +{ + local pfx="$1"; shift + local name="$1"; shift + local sfx="$1"; shift + local order="$1"; shift + + local base="" + local file="" + + # We may have fallbacks for a specific case (e.g. read_acquire()), or + # an entire class, e.g. *inc*(). + # + # Start at the most specific, and fall back to the most general. Once + # we find a specific fallback, don't bother looking for more. + for base in "${pfx}${name}${sfx}${order}" "${name}"; do + file="${ATOMICDIR}/fallbacks/${base}" + + if [ -f "${file}" ]; then + printf "${file}" + break + fi + done +} + +#gen_ret_type(meta, int) +gen_ret_type() { + local meta="$1"; shift + local int="$1"; shift + + case "${meta}" in + [sv]) printf "void";; + [bB]) printf "bool";; + [aiIfFlR]) printf "${int}";; + esac +} + +#gen_ret_stmt(meta) +gen_ret_stmt() +{ + if meta_has_ret "${meta}"; then + printf "return "; + fi +} + +# gen_param_name(arg) +gen_param_name() +{ + # strip off the leading 'c' for 'cv' + local name="${1#c}" + printf "${name#*:}" +} + +# gen_param_type(arg, int, atomic) +gen_param_type() +{ + local type="${1%%:*}"; shift + local int="$1"; shift + local atomic="$1"; shift + + case "${type}" in + i) type="${int} ";; + p) type="${int} *";; + v) type="${atomic}_t *";; + cv) type="const ${atomic}_t *";; + esac + + printf "${type}" +} + +#gen_param(arg, int, atomic) +gen_param() +{ + local arg="$1"; shift + local int="$1"; shift + local atomic="$1"; shift + local name="$(gen_param_name "${arg}")" + local type="$(gen_param_type "${arg}" "${int}" "${atomic}")" + + printf "${type}${name}" +} + +#gen_params(int, atomic, arg...) +gen_params() +{ + local int="$1"; shift + local atomic="$1"; shift + + while [ "$#" -gt 0 ]; do + gen_param "$1" "${int}" "${atomic}" + [ "$#" -gt 1 ] && printf ", " + shift; + done +} + +#gen_args(arg...) +gen_args() +{ + while [ "$#" -gt 0 ]; do + printf "$(gen_param_name "$1")" + [ "$#" -gt 1 ] && printf ", " + shift; + done +} + +#gen_proto_order_variants(meta, pfx, name, sfx, ...) +gen_proto_order_variants() +{ + local meta="$1"; shift + local pfx="$1"; shift + local name="$1"; shift + local sfx="$1"; shift + + gen_proto_order_variant "${meta}" "${pfx}" "${name}" "${sfx}" "" "$@" + + if meta_has_acquire "${meta}"; then + gen_proto_order_variant "${meta}" "${pfx}" "${name}" "${sfx}" "_acquire" "$@" + fi + if meta_has_release "${meta}"; then + gen_proto_order_variant "${meta}" "${pfx}" "${name}" "${sfx}" "_release" "$@" + fi + if meta_has_relaxed "${meta}"; then + gen_proto_order_variant "${meta}" "${pfx}" "${name}" "${sfx}" "_relaxed" "$@" + fi +} + +#gen_proto_variants(meta, name, ...) +gen_proto_variants() +{ + local meta="$1"; shift + local name="$1"; shift + local pfx="" + local sfx="" + + meta_in "${meta}" "fF" && pfx="fetch_" + meta_in "${meta}" "R" && sfx="_return" + + gen_proto_order_variants "${meta}" "${pfx}" "${name}" "${sfx}" "$@" +} + +#gen_proto(meta, ...) +gen_proto() { + local meta="$1"; shift + for m in $(echo "${meta}" | grep -o .); do + gen_proto_variants "${m}" "$@" + done +} diff --git a/src/net/scripts/atomic/atomics.tbl b/src/net/scripts/atomic/atomics.tbl new file mode 100755 index 0000000..fbee2f6 --- /dev/null +++ b/src/net/scripts/atomic/atomics.tbl @@ -0,0 +1,41 @@ +# name meta args... +# +# Where meta contains a string of variants to generate. +# Upper-case implies _{acquire,release,relaxed} variants. +# Valid meta values are: +# * B/b - bool: returns bool +# * v - void: returns void +# * I/i - int: returns base type +# * R - return: returns base type (has _return variants) +# * F/f - fetch: returns base type (has fetch_ variants) +# * l - load: returns base type (has _acquire order variant) +# * s - store: returns void (has _release order variant) +# +# Where args contains list of type[:name], where type is: +# * cv - const pointer to atomic base type (atomic_t/atomic64_t/atomic_long_t) +# * v - pointer to atomic base type (atomic_t/atomic64_t/atomic_long_t) +# * i - base type (int/s64/long) +# * p - pointer to base type (int/s64/long) +# +read l cv +set s v i +add vRF i v +sub vRF i v +inc vRF v +dec vRF v +and vF i v +andnot vF i v +or vF i v +xor vF i v +xchg I v i +cmpxchg I v i:old i:new +try_cmpxchg B v p:old i:new +sub_and_test b i v +dec_and_test b v +inc_and_test b v +add_negative b i v +add_unless fb v i:a i:u +inc_not_zero b v +inc_unless_negative b v +dec_unless_positive b v +dec_if_positive i v diff --git a/src/net/scripts/atomic/check-atomics.sh b/src/net/scripts/atomic/check-atomics.sh new file mode 100755 index 0000000..82748d4 --- /dev/null +++ b/src/net/scripts/atomic/check-atomics.sh @@ -0,0 +1,34 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0 +# +# Check if atomic headers are up-to-date + +ATOMICDIR=$(dirname $0) +ATOMICTBL=${ATOMICDIR}/atomics.tbl +LINUXDIR=${ATOMICDIR}/../.. + +echo '' | sha1sum - > /dev/null 2>&1 +if [ $? -ne 0 ]; then + printf "sha1sum not available, skipping atomic header checks.\n" + exit 0 +fi + +cat < 0)) + return false; + } while (!${arch}${atomic}_try_cmpxchg(v, &c, c - 1)); + + return true; +} +EOF diff --git a/src/net/scripts/atomic/fallbacks/fence b/src/net/scripts/atomic/fallbacks/fence new file mode 100755 index 0000000..3764fc8 --- /dev/null +++ b/src/net/scripts/atomic/fallbacks/fence @@ -0,0 +1,11 @@ +cat <counter); +} +EOF diff --git a/src/net/scripts/atomic/fallbacks/release b/src/net/scripts/atomic/fallbacks/release new file mode 100755 index 0000000..f8906d5 --- /dev/null +++ b/src/net/scripts/atomic/fallbacks/release @@ -0,0 +1,8 @@ +cat <counter, i); +} +EOF diff --git a/src/net/scripts/atomic/fallbacks/sub_and_test b/src/net/scripts/atomic/fallbacks/sub_and_test new file mode 100755 index 0000000..c580f4c --- /dev/null +++ b/src/net/scripts/atomic/fallbacks/sub_and_test @@ -0,0 +1,16 @@ +cat < + +EOF + +for xchg in "${ARCH}xchg" "${ARCH}cmpxchg" "${ARCH}cmpxchg64"; do + gen_xchg_fallbacks "${xchg}" +done + +gen_try_cmpxchg_fallbacks + +grep '^[a-z]' "$1" | while read name meta args; do + gen_proto "${meta}" "${name}" "${ARCH}" "atomic" "int" ${args} +done + +cat < +#endif + +EOF + +grep '^[a-z]' "$1" | while read name meta args; do + gen_proto "${meta}" "${name}" "${ARCH}" "atomic64" "s64" ${args} +done + +cat < +#include +#include + +EOF + +grep '^[a-z]' "$1" | while read name meta args; do + gen_proto "${meta}" "${name}" "atomic" "int" ${args} +done + +grep '^[a-z]' "$1" | while read name meta args; do + gen_proto "${meta}" "${name}" "atomic64" "s64" ${args} +done + +for xchg in "xchg" "cmpxchg" "cmpxchg64" "try_cmpxchg"; do + for order in "" "_acquire" "_release" "_relaxed"; do + gen_optional_xchg "${xchg}" "${order}" + done +done + +for xchg in "cmpxchg_local" "cmpxchg64_local" "sync_cmpxchg"; do + gen_xchg "${xchg}" "" + printf "\n" +done + +gen_xchg "cmpxchg_double" "2 * " + +printf "\n\n" + +gen_xchg "cmpxchg_double_local" "2 * " + +cat < +#include + +#ifdef CONFIG_64BIT +typedef atomic64_t atomic_long_t; +#define ATOMIC_LONG_INIT(i) ATOMIC64_INIT(i) +#define atomic_long_cond_read_acquire atomic64_cond_read_acquire +#define atomic_long_cond_read_relaxed atomic64_cond_read_relaxed +#else +typedef atomic_t atomic_long_t; +#define ATOMIC_LONG_INIT(i) ATOMIC_INIT(i) +#define atomic_long_cond_read_acquire atomic_cond_read_acquire +#define atomic_long_cond_read_relaxed atomic_cond_read_relaxed +#endif + +#ifdef CONFIG_64BIT + +EOF + +grep '^[a-z]' "$1" | while read name meta args; do + gen_proto "${meta}" "${name}" "atomic64" "s64" ${args} +done + +cat < ${LINUXDIR}/include/${header} + HASH="$(sha1sum ${LINUXDIR}/include/${header})" + HASH="${HASH%% *}" + printf "// %s\n" "${HASH}" >> ${LINUXDIR}/include/${header} +done diff --git a/src/net/scripts/basic/.gitignore b/src/net/scripts/basic/.gitignore new file mode 100644 index 0000000..98ae1f5 --- /dev/null +++ b/src/net/scripts/basic/.gitignore @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +fixdep diff --git a/src/net/scripts/basic/Makefile b/src/net/scripts/basic/Makefile new file mode 100644 index 0000000..eeb6a38 --- /dev/null +++ b/src/net/scripts/basic/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# fixdep: used to generate dependency information during build process + +hostprogs-always-y += fixdep diff --git a/src/net/scripts/basic/fixdep.c b/src/net/scripts/basic/fixdep.c new file mode 100644 index 0000000..d985405 --- /dev/null +++ b/src/net/scripts/basic/fixdep.c @@ -0,0 +1,404 @@ +/* + * "Optimize" a list of dependencies as spit out by gcc -MD + * for the kernel build + * =========================================================================== + * + * Author Kai Germaschewski + * Copyright 2002 by Kai Germaschewski + * + * This software may be used and distributed according to the terms + * of the GNU General Public License, incorporated herein by reference. + * + * + * Introduction: + * + * gcc produces a very nice and correct list of dependencies which + * tells make when to remake a file. + * + * To use this list as-is however has the drawback that virtually + * every file in the kernel includes autoconf.h. + * + * If the user re-runs make *config, autoconf.h will be + * regenerated. make notices that and will rebuild every file which + * includes autoconf.h, i.e. basically all files. This is extremely + * annoying if the user just changed CONFIG_HIS_DRIVER from n to m. + * + * So we play the same trick that "mkdep" played before. We replace + * the dependency on autoconf.h by a dependency on every config + * option which is mentioned in any of the listed prerequisites. + * + * kconfig populates a tree in include/config/ with an empty file + * for each config symbol and when the configuration is updated + * the files representing changed config options are touched + * which then let make pick up the changes and the files that use + * the config symbols are rebuilt. + * + * So if the user changes his CONFIG_HIS_DRIVER option, only the objects + * which depend on "include/config/his/driver.h" will be rebuilt, + * so most likely only his driver ;-) + * + * The idea above dates, by the way, back to Michael E Chastain, AFAIK. + * + * So to get dependencies right, there are two issues: + * o if any of the files the compiler read changed, we need to rebuild + * o if the command line given to the compile the file changed, we + * better rebuild as well. + * + * The former is handled by using the -MD output, the later by saving + * the command line used to compile the old object and comparing it + * to the one we would now use. + * + * Again, also this idea is pretty old and has been discussed on + * kbuild-devel a long time ago. I don't have a sensibly working + * internet connection right now, so I rather don't mention names + * without double checking. + * + * This code here has been based partially based on mkdep.c, which + * says the following about its history: + * + * Copyright abandoned, Michael Chastain, . + * This is a C version of syncdep.pl by Werner Almesberger. + * + * + * It is invoked as + * + * fixdep + * + * and will read the dependency file + * + * The transformed dependency snipped is written to stdout. + * + * It first generates a line + * + * cmd_ = + * + * and then basically copies the ..d file to stdout, in the + * process filtering out the dependency on autoconf.h and adding + * dependencies on include/config/my/option.h for every + * CONFIG_MY_OPTION encountered in any of the prerequisites. + * + * We don't even try to really parse the header files, but + * merely grep, i.e. if CONFIG_FOO is mentioned in a comment, it will + * be picked up as well. It's not a problem with respect to + * correctness, since that can only give too many dependencies, thus + * we cannot miss a rebuild. Since people tend to not mention totally + * unrelated CONFIG_ options all over the place, it's not an + * efficiency problem either. + * + * (Note: it'd be easy to port over the complete mkdep state machine, + * but I don't think the added complexity is worth it) + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static void usage(void) +{ + fprintf(stderr, "Usage: fixdep \n"); + exit(1); +} + +/* + * In the intended usage of this program, the stdout is redirected to .*.cmd + * files. The return value of printf() and putchar() must be checked to catch + * any error, e.g. "No space left on device". + */ +static void xprintf(const char *format, ...) +{ + va_list ap; + int ret; + + va_start(ap, format); + ret = vprintf(format, ap); + if (ret < 0) { + perror("fixdep"); + exit(1); + } + va_end(ap); +} + +static void xputchar(int c) +{ + int ret; + + ret = putchar(c); + if (ret == EOF) { + perror("fixdep"); + exit(1); + } +} + +/* + * Print out a dependency path from a symbol name + */ +static void print_dep(const char *m, int slen, const char *dir) +{ + int c, prev_c = '/', i; + + xprintf(" $(wildcard %s/", dir); + for (i = 0; i < slen; i++) { + c = m[i]; + if (c == '_') + c = '/'; + else + c = tolower(c); + if (c != '/' || prev_c != '/') + xputchar(c); + prev_c = c; + } + xprintf(".h) \\\n"); +} + +struct item { + struct item *next; + unsigned int len; + unsigned int hash; + char name[]; +}; + +#define HASHSZ 256 +static struct item *hashtab[HASHSZ]; + +static unsigned int strhash(const char *str, unsigned int sz) +{ + /* fnv32 hash */ + unsigned int i, hash = 2166136261U; + + for (i = 0; i < sz; i++) + hash = (hash ^ str[i]) * 0x01000193; + return hash; +} + +/* + * Lookup a value in the configuration string. + */ +static int is_defined_config(const char *name, int len, unsigned int hash) +{ + struct item *aux; + + for (aux = hashtab[hash % HASHSZ]; aux; aux = aux->next) { + if (aux->hash == hash && aux->len == len && + memcmp(aux->name, name, len) == 0) + return 1; + } + return 0; +} + +/* + * Add a new value to the configuration string. + */ +static void define_config(const char *name, int len, unsigned int hash) +{ + struct item *aux = malloc(sizeof(*aux) + len); + + if (!aux) { + perror("fixdep:malloc"); + exit(1); + } + memcpy(aux->name, name, len); + aux->len = len; + aux->hash = hash; + aux->next = hashtab[hash % HASHSZ]; + hashtab[hash % HASHSZ] = aux; +} + +/* + * Record the use of a CONFIG_* word. + */ +static void use_config(const char *m, int slen) +{ + unsigned int hash = strhash(m, slen); + + if (is_defined_config(m, slen, hash)) + return; + + define_config(m, slen, hash); + print_dep(m, slen, "include/config"); +} + +/* test if s ends in sub */ +static int str_ends_with(const char *s, int slen, const char *sub) +{ + int sublen = strlen(sub); + + if (sublen > slen) + return 0; + + return !memcmp(s + slen - sublen, sub, sublen); +} + +static void parse_config_file(const char *p) +{ + const char *q, *r; + const char *start = p; + + while ((p = strstr(p, "CONFIG_"))) { + if (p > start && (isalnum(p[-1]) || p[-1] == '_')) { + p += 7; + continue; + } + p += 7; + q = p; + while (isalnum(*q) || *q == '_') + q++; + if (str_ends_with(p, q - p, "_MODULE")) + r = q - 7; + else + r = q; + if (r > p) + use_config(p, r - p); + p = q; + } +} + +static void *read_file(const char *filename) +{ + struct stat st; + int fd; + char *buf; + + fd = open(filename, O_RDONLY); + if (fd < 0) { + fprintf(stderr, "fixdep: error opening file: "); + perror(filename); + exit(2); + } + if (fstat(fd, &st) < 0) { + fprintf(stderr, "fixdep: error fstat'ing file: "); + perror(filename); + exit(2); + } + buf = malloc(st.st_size + 1); + if (!buf) { + perror("fixdep: malloc"); + exit(2); + } + if (read(fd, buf, st.st_size) != st.st_size) { + perror("fixdep: read"); + exit(2); + } + buf[st.st_size] = '\0'; + close(fd); + + return buf; +} + +/* Ignore certain dependencies */ +static int is_ignored_file(const char *s, int len) +{ + return str_ends_with(s, len, "include/generated/autoconf.h") || + str_ends_with(s, len, "include/generated/autoksyms.h"); +} + +/* + * Important: The below generated source_foo.o and deps_foo.o variable + * assignments are parsed not only by make, but also by the rather simple + * parser in scripts/mod/sumversion.c. + */ +static void parse_dep_file(char *m, const char *target) +{ + char *p; + int is_last, is_target; + int saw_any_target = 0; + int is_first_dep = 0; + void *buf; + + while (1) { + /* Skip any "white space" */ + while (*m == ' ' || *m == '\\' || *m == '\n') + m++; + + if (!*m) + break; + + /* Find next "white space" */ + p = m; + while (*p && *p != ' ' && *p != '\\' && *p != '\n') + p++; + is_last = (*p == '\0'); + /* Is the token we found a target name? */ + is_target = (*(p-1) == ':'); + /* Don't write any target names into the dependency file */ + if (is_target) { + /* The /next/ file is the first dependency */ + is_first_dep = 1; + } else if (!is_ignored_file(m, p - m)) { + *p = '\0'; + + /* + * Do not list the source file as dependency, so that + * kbuild is not confused if a .c file is rewritten + * into .S or vice versa. Storing it in source_* is + * needed for modpost to compute srcversions. + */ + if (is_first_dep) { + /* + * If processing the concatenation of multiple + * dependency files, only process the first + * target name, which will be the original + * source name, and ignore any other target + * names, which will be intermediate temporary + * files. + */ + if (!saw_any_target) { + saw_any_target = 1; + xprintf("source_%s := %s\n\n", + target, m); + xprintf("deps_%s := \\\n", target); + } + is_first_dep = 0; + } else { + xprintf(" %s \\\n", m); + } + + buf = read_file(m); + parse_config_file(buf); + free(buf); + } + + if (is_last) + break; + + /* + * Start searching for next token immediately after the first + * "whitespace" character that follows this token. + */ + m = p + 1; + } + + if (!saw_any_target) { + fprintf(stderr, "fixdep: parse error; no targets found\n"); + exit(1); + } + + xprintf("\n%s: $(deps_%s)\n\n", target, target); + xprintf("$(deps_%s):\n", target); +} + +int main(int argc, char *argv[]) +{ + const char *depfile, *target, *cmdline; + void *buf; + + if (argc != 4) + usage(); + + depfile = argv[1]; + target = argv[2]; + cmdline = argv[3]; + + xprintf("cmd_%s := %s\n\n", target, cmdline); + + buf = read_file(depfile); + parse_dep_file(buf, target); + free(buf); + + return 0; +} diff --git a/src/net/scripts/bin2c.c b/src/net/scripts/bin2c.c new file mode 100644 index 0000000..c3d7eef --- /dev/null +++ b/src/net/scripts/bin2c.c @@ -0,0 +1,36 @@ +/* + * Unloved program to convert a binary on stdin to a C include on stdout + * + * Jan 1999 Matt Mackall + * + * This software may be used and distributed according to the terms + * of the GNU General Public License, incorporated herein by reference. + */ + +#include + +int main(int argc, char *argv[]) +{ + int ch, total = 0; + + if (argc > 1) + printf("const char %s[] %s=\n", + argv[1], argc > 2 ? argv[2] : ""); + + do { + printf("\t\""); + while ((ch = getchar()) != EOF) { + total++; + printf("\\x%02x", ch); + if (total % 16 == 0) + break; + } + printf("\"\n"); + } while (ch != EOF); + + if (argc > 1) + printf("\t;\n\n#include \n\nconst size_t %s_size = %d;\n", + argv[1], total); + + return 0; +} diff --git a/src/net/scripts/bloat-o-meter b/src/net/scripts/bloat-o-meter new file mode 100755 index 0000000..dcd8d87 --- /dev/null +++ b/src/net/scripts/bloat-o-meter @@ -0,0 +1,104 @@ +#!/usr/bin/env python3 +# +# Copyright 2004 Matt Mackall +# +# inspired by perl Bloat-O-Meter (c) 1997 by Andi Kleen +# +# This software may be used and distributed according to the terms +# of the GNU General Public License, incorporated herein by reference. + +import sys, os, re +from signal import signal, SIGPIPE, SIG_DFL + +signal(SIGPIPE, SIG_DFL) + +if len(sys.argv) < 3: + sys.stderr.write("usage: %s [option] file1 file2\n" % sys.argv[0]) + sys.stderr.write("The options are:\n") + sys.stderr.write("-c categorize output based on symbol type\n") + sys.stderr.write("-d Show delta of Data Section\n") + sys.stderr.write("-t Show delta of text Section\n") + sys.exit(-1) + +re_NUMBER = re.compile(r'\.[0-9]+') + +def getsizes(file, format): + sym = {} + with os.popen("nm --size-sort " + file) as f: + for line in f: + if line.startswith("\n") or ":" in line: + continue + size, type, name = line.split() + if type in format: + # strip generated symbols + if name.startswith("__mod_"): continue + if name.startswith("__se_sys"): continue + if name.startswith("__se_compat_sys"): continue + if name.startswith("__addressable_"): continue + if name == "linux_banner": continue + # statics and some other optimizations adds random .NUMBER + name = re_NUMBER.sub('', name) + sym[name] = sym.get(name, 0) + int(size, 16) + return sym + +def calc(oldfile, newfile, format): + old = getsizes(oldfile, format) + new = getsizes(newfile, format) + grow, shrink, add, remove, up, down = 0, 0, 0, 0, 0, 0 + delta, common = [], {} + otot, ntot = 0, 0 + + for a in old: + if a in new: + common[a] = 1 + + for name in old: + otot += old[name] + if name not in common: + remove += 1 + down += old[name] + delta.append((-old[name], name)) + + for name in new: + ntot += new[name] + if name not in common: + add += 1 + up += new[name] + delta.append((new[name], name)) + + for name in common: + d = new.get(name, 0) - old.get(name, 0) + if d>0: grow, up = grow+1, up+d + if d<0: shrink, down = shrink+1, down-d + delta.append((d, name)) + + delta.sort() + delta.reverse() + return grow, shrink, add, remove, up, down, delta, old, new, otot, ntot + +def print_result(symboltype, symbolformat, argc): + grow, shrink, add, remove, up, down, delta, old, new, otot, ntot = \ + calc(sys.argv[argc - 1], sys.argv[argc], symbolformat) + + print("add/remove: %s/%s grow/shrink: %s/%s up/down: %s/%s (%s)" % \ + (add, remove, grow, shrink, up, -down, up-down)) + print("%-40s %7s %7s %+7s" % (symboltype, "old", "new", "delta")) + for d, n in delta: + if d: print("%-40s %7s %7s %+7d" % (n, old.get(n,"-"), new.get(n,"-"), d)) + + if otot: + percent = (ntot - otot) * 100.0 / otot + else: + percent = 0 + print("Total: Before=%d, After=%d, chg %+.2f%%" % (otot, ntot, percent)) + +if sys.argv[1] == "-c": + print_result("Function", "tT", 3) + print_result("Data", "dDbB", 3) + print_result("RO Data", "rR", 3) +elif sys.argv[1] == "-d": + print_result("Data", "dDbBrR", 3) +elif sys.argv[1] == "-t": + print_result("Function", "tT", 3) +else: + print_result("Function", "tTdDbBrR", 2) diff --git a/src/net/scripts/bootgraph.pl b/src/net/scripts/bootgraph.pl new file mode 100755 index 0000000..79c9032 --- /dev/null +++ b/src/net/scripts/bootgraph.pl @@ -0,0 +1,224 @@ +#!/usr/bin/env perl +# SPDX-License-Identifier: GPL-2.0-only + +# Copyright 2008, Intel Corporation +# +# This file is part of the Linux kernel +# +# Authors: +# Arjan van de Ven + + +# +# This script turns a dmesg output into a SVG graphic that shows which +# functions take how much time. You can view SVG graphics with various +# programs, including Inkscape, The Gimp and Firefox. +# +# +# For this script to work, the kernel needs to be compiled with the +# CONFIG_PRINTK_TIME configuration option enabled, and with +# "initcall_debug" passed on the kernel command line. +# +# usage: +# dmesg | perl scripts/bootgraph.pl > output.svg +# + +use strict; +use Getopt::Long; +my $header = 0; + +sub help { + my $text = << "EOM"; +Usage: +1) dmesg | perl scripts/bootgraph.pl [OPTION] > output.svg +2) perl scripts/bootgraph.pl -h + +Options: + -header Insert kernel version and date +EOM + my $std=shift; + if ($std == 1) { + print STDERR $text; + } else { + print $text; + } + exit; +} + +GetOptions( + 'h|help' =>\&help, + 'header' =>\$header +); + +my %start; +my %end; +my %type; +my $done = 0; +my $maxtime = 0; +my $firsttime = 99999; +my $count = 0; +my %pids; +my %pidctr; + +my $headerstep = 20; +my $xheader = 15; +my $yheader = 25; +my $cyheader = 0; + +while (<>) { + my $line = $_; + if ($line =~ /([0-9\.]+)\] calling ([a-zA-Z0-9\_\.]+)\+/) { + my $func = $2; + if ($done == 0) { + $start{$func} = $1; + $type{$func} = 0; + if ($1 < $firsttime) { + $firsttime = $1; + } + } + if ($line =~ /\@ ([0-9]+)/) { + $pids{$func} = $1; + } + $count = $count + 1; + } + + if ($line =~ /([0-9\.]+)\] async_waiting @ ([0-9]+)/) { + my $pid = $2; + my $func; + if (!defined($pidctr{$pid})) { + $func = "wait_" . $pid . "_1"; + $pidctr{$pid} = 1; + } else { + $pidctr{$pid} = $pidctr{$pid} + 1; + $func = "wait_" . $pid . "_" . $pidctr{$pid}; + } + if ($done == 0) { + $start{$func} = $1; + $type{$func} = 1; + if ($1 < $firsttime) { + $firsttime = $1; + } + } + $pids{$func} = $pid; + $count = $count + 1; + } + + if ($line =~ /([0-9\.]+)\] initcall ([a-zA-Z0-9\_\.]+)\+.*returned/) { + if ($done == 0) { + $end{$2} = $1; + $maxtime = $1; + } + } + + if ($line =~ /([0-9\.]+)\] async_continuing @ ([0-9]+)/) { + my $pid = $2; + my $func = "wait_" . $pid . "_" . $pidctr{$pid}; + $end{$func} = $1; + $maxtime = $1; + } + if ($line =~ /Write protecting the/) { + $done = 1; + } + if ($line =~ /Freeing unused kernel memory/) { + $done = 1; + } +} + +if ($count == 0) { + print STDERR < \n"; +print "\n"; + + +if ($header) { + my $version = `uname -a`; + my $date = `date`; + print "Kernel version: $version\n"; + $cyheader = $yheader+$headerstep; + print "Date: $date\n"; +} + +my @styles; + +$styles[0] = "fill:rgb(0,0,255);fill-opacity:0.5;stroke-width:1;stroke:rgb(0,0,0)"; +$styles[1] = "fill:rgb(0,255,0);fill-opacity:0.5;stroke-width:1;stroke:rgb(0,0,0)"; +$styles[2] = "fill:rgb(255,0,20);fill-opacity:0.5;stroke-width:1;stroke:rgb(0,0,0)"; +$styles[3] = "fill:rgb(255,255,20);fill-opacity:0.5;stroke-width:1;stroke:rgb(0,0,0)"; +$styles[4] = "fill:rgb(255,0,255);fill-opacity:0.5;stroke-width:1;stroke:rgb(0,0,0)"; +$styles[5] = "fill:rgb(0,255,255);fill-opacity:0.5;stroke-width:1;stroke:rgb(0,0,0)"; +$styles[6] = "fill:rgb(0,128,255);fill-opacity:0.5;stroke-width:1;stroke:rgb(0,0,0)"; +$styles[7] = "fill:rgb(0,255,128);fill-opacity:0.5;stroke-width:1;stroke:rgb(0,0,0)"; +$styles[8] = "fill:rgb(255,0,128);fill-opacity:0.5;stroke-width:1;stroke:rgb(0,0,0)"; +$styles[9] = "fill:rgb(255,255,128);fill-opacity:0.5;stroke-width:1;stroke:rgb(0,0,0)"; +$styles[10] = "fill:rgb(255,128,255);fill-opacity:0.5;stroke-width:1;stroke:rgb(0,0,0)"; +$styles[11] = "fill:rgb(128,255,255);fill-opacity:0.5;stroke-width:1;stroke:rgb(0,0,0)"; + +my $style_wait = "fill:rgb(128,128,128);fill-opacity:0.5;stroke-width:0;stroke:rgb(0,0,0)"; + +my $mult = 1950.0 / ($maxtime - $firsttime); +my $threshold2 = ($maxtime - $firsttime) / 120.0; +my $threshold = $threshold2/10; +my $stylecounter = 0; +my %rows; +my $rowscount = 1; +my @initcalls = sort { $start{$a} <=> $start{$b} } keys(%start); + +foreach my $key (@initcalls) { + my $duration = $end{$key} - $start{$key}; + + if ($duration >= $threshold) { + my ($s, $s2, $s3, $e, $w, $y, $y2, $style); + my $pid = $pids{$key}; + + if (!defined($rows{$pid})) { + $rows{$pid} = $rowscount; + $rowscount = $rowscount + 1; + } + $s = ($start{$key} - $firsttime) * $mult; + $s2 = $s + 6; + $s3 = $s + 1; + $e = ($end{$key} - $firsttime) * $mult; + $w = $e - $s; + + $y = $rows{$pid} * 150; + $y2 = $y + 4; + + $style = $styles[$stylecounter]; + $stylecounter = $stylecounter + 1; + if ($stylecounter > 11) { + $stylecounter = 0; + }; + + if ($type{$key} == 1) { + $y = $y + 15; + print "\n"; + } else { + print "\n"; + if ($duration >= $threshold2) { + print "$key\n"; + } else { + print "$key\n"; + } + } + } +} + + +# print the time line on top +my $time = $firsttime; +my $step = ($maxtime - $firsttime) / 15; +while ($time < $maxtime) { + my $s3 = ($time - $firsttime) * $mult; + my $tm = int($time * 100) / 100.0; + print "$tm\n"; + $time = $time + $step; +} + +print "\n"; diff --git a/src/net/scripts/bpf_helpers_doc.py b/src/net/scripts/bpf_helpers_doc.py new file mode 100755 index 0000000..8b82974 --- /dev/null +++ b/src/net/scripts/bpf_helpers_doc.py @@ -0,0 +1,611 @@ +#!/usr/bin/env python3 +# SPDX-License-Identifier: GPL-2.0-only +# +# Copyright (C) 2018-2019 Netronome Systems, Inc. + +# In case user attempts to run with Python 2. +from __future__ import print_function + +import argparse +import re +import sys, os + +class NoHelperFound(BaseException): + pass + +class ParsingError(BaseException): + def __init__(self, line='', reader=None): + if reader: + BaseException.__init__(self, + 'Error at file offset %d, parsing line: %s' % + (reader.tell(), line)) + else: + BaseException.__init__(self, 'Error parsing line: %s' % line) + +class Helper(object): + """ + An object representing the description of an eBPF helper function. + @proto: function prototype of the helper function + @desc: textual description of the helper function + @ret: description of the return value of the helper function + """ + def __init__(self, proto='', desc='', ret=''): + self.proto = proto + self.desc = desc + self.ret = ret + + def proto_break_down(self): + """ + Break down helper function protocol into smaller chunks: return type, + name, distincts arguments. + """ + arg_re = re.compile('((\w+ )*?(\w+|...))( (\**)(\w+))?$') + res = {} + proto_re = re.compile('(.+) (\**)(\w+)\(((([^,]+)(, )?){1,5})\)$') + + capture = proto_re.match(self.proto) + res['ret_type'] = capture.group(1) + res['ret_star'] = capture.group(2) + res['name'] = capture.group(3) + res['args'] = [] + + args = capture.group(4).split(', ') + for a in args: + capture = arg_re.match(a) + res['args'].append({ + 'type' : capture.group(1), + 'star' : capture.group(5), + 'name' : capture.group(6) + }) + + return res + +class HeaderParser(object): + """ + An object used to parse a file in order to extract the documentation of a + list of eBPF helper functions. All the helpers that can be retrieved are + stored as Helper object, in the self.helpers() array. + @filename: name of file to parse, usually include/uapi/linux/bpf.h in the + kernel tree + """ + def __init__(self, filename): + self.reader = open(filename, 'r') + self.line = '' + self.helpers = [] + + def parse_helper(self): + proto = self.parse_proto() + desc = self.parse_desc() + ret = self.parse_ret() + return Helper(proto=proto, desc=desc, ret=ret) + + def parse_proto(self): + # Argument can be of shape: + # - "void" + # - "type name" + # - "type *name" + # - Same as above, with "const" and/or "struct" in front of type + # - "..." (undefined number of arguments, for bpf_trace_printk()) + # There is at least one term ("void"), and at most five arguments. + p = re.compile(' \* ?((.+) \**\w+\((((const )?(struct )?(\w+|\.\.\.)( \**\w+)?)(, )?){1,5}\))$') + capture = p.match(self.line) + if not capture: + raise NoHelperFound + self.line = self.reader.readline() + return capture.group(1) + + def parse_desc(self): + p = re.compile(' \* ?(?:\t| {5,8})Description$') + capture = p.match(self.line) + if not capture: + # Helper can have empty description and we might be parsing another + # attribute: return but do not consume. + return '' + # Description can be several lines, some of them possibly empty, and it + # stops when another subsection title is met. + desc = '' + while True: + self.line = self.reader.readline() + if self.line == ' *\n': + desc += '\n' + else: + p = re.compile(' \* ?(?:\t| {5,8})(?:\t| {8})(.*)') + capture = p.match(self.line) + if capture: + desc += capture.group(1) + '\n' + else: + break + return desc + + def parse_ret(self): + p = re.compile(' \* ?(?:\t| {5,8})Return$') + capture = p.match(self.line) + if not capture: + # Helper can have empty retval and we might be parsing another + # attribute: return but do not consume. + return '' + # Return value description can be several lines, some of them possibly + # empty, and it stops when another subsection title is met. + ret = '' + while True: + self.line = self.reader.readline() + if self.line == ' *\n': + ret += '\n' + else: + p = re.compile(' \* ?(?:\t| {5,8})(?:\t| {8})(.*)') + capture = p.match(self.line) + if capture: + ret += capture.group(1) + '\n' + else: + break + return ret + + def run(self): + # Advance to start of helper function descriptions. + offset = self.reader.read().find('* Start of BPF helper function descriptions:') + if offset == -1: + raise Exception('Could not find start of eBPF helper descriptions list') + self.reader.seek(offset) + self.reader.readline() + self.reader.readline() + self.line = self.reader.readline() + + while True: + try: + helper = self.parse_helper() + self.helpers.append(helper) + except NoHelperFound: + break + + self.reader.close() + +############################################################################### + +class Printer(object): + """ + A generic class for printers. Printers should be created with an array of + Helper objects, and implement a way to print them in the desired fashion. + @helpers: array of Helper objects to print to standard output + """ + def __init__(self, helpers): + self.helpers = helpers + + def print_header(self): + pass + + def print_footer(self): + pass + + def print_one(self, helper): + pass + + def print_all(self): + self.print_header() + for helper in self.helpers: + self.print_one(helper) + self.print_footer() + +class PrinterRST(Printer): + """ + A printer for dumping collected information about helpers as a ReStructured + Text page compatible with the rst2man program, which can be used to + generate a manual page for the helpers. + @helpers: array of Helper objects to print to standard output + """ + def print_header(self): + header = '''\ +.. Copyright (C) All BPF authors and contributors from 2014 to present. +.. See git log include/uapi/linux/bpf.h in kernel tree for details. +.. +.. %%%LICENSE_START(VERBATIM) +.. Permission is granted to make and distribute verbatim copies of this +.. manual provided the copyright notice and this permission notice are +.. preserved on all copies. +.. +.. Permission is granted to copy and distribute modified versions of this +.. manual under the conditions for verbatim copying, provided that the +.. entire resulting derived work is distributed under the terms of a +.. permission notice identical to this one. +.. +.. Since the Linux kernel and libraries are constantly changing, this +.. manual page may be incorrect or out-of-date. The author(s) assume no +.. responsibility for errors or omissions, or for damages resulting from +.. the use of the information contained herein. The author(s) may not +.. have taken the same level of care in the production of this manual, +.. which is licensed free of charge, as they might when working +.. professionally. +.. +.. Formatted or processed versions of this manual, if unaccompanied by +.. the source, must acknowledge the copyright and authors of this work. +.. %%%LICENSE_END +.. +.. Please do not edit this file. It was generated from the documentation +.. located in file include/uapi/linux/bpf.h of the Linux kernel sources +.. (helpers description), and from scripts/bpf_helpers_doc.py in the same +.. repository (header and footer). + +=========== +BPF-HELPERS +=========== +------------------------------------------------------------------------------- +list of eBPF helper functions +------------------------------------------------------------------------------- + +:Manual section: 7 + +DESCRIPTION +=========== + +The extended Berkeley Packet Filter (eBPF) subsystem consists in programs +written in a pseudo-assembly language, then attached to one of the several +kernel hooks and run in reaction of specific events. This framework differs +from the older, "classic" BPF (or "cBPF") in several aspects, one of them being +the ability to call special functions (or "helpers") from within a program. +These functions are restricted to a white-list of helpers defined in the +kernel. + +These helpers are used by eBPF programs to interact with the system, or with +the context in which they work. For instance, they can be used to print +debugging messages, to get the time since the system was booted, to interact +with eBPF maps, or to manipulate network packets. Since there are several eBPF +program types, and that they do not run in the same context, each program type +can only call a subset of those helpers. + +Due to eBPF conventions, a helper can not have more than five arguments. + +Internally, eBPF programs call directly into the compiled helper functions +without requiring any foreign-function interface. As a result, calling helpers +introduces no overhead, thus offering excellent performance. + +This document is an attempt to list and document the helpers available to eBPF +developers. They are sorted by chronological order (the oldest helpers in the +kernel at the top). + +HELPERS +======= +''' + print(header) + + def print_footer(self): + footer = ''' +EXAMPLES +======== + +Example usage for most of the eBPF helpers listed in this manual page are +available within the Linux kernel sources, at the following locations: + +* *samples/bpf/* +* *tools/testing/selftests/bpf/* + +LICENSE +======= + +eBPF programs can have an associated license, passed along with the bytecode +instructions to the kernel when the programs are loaded. The format for that +string is identical to the one in use for kernel modules (Dual licenses, such +as "Dual BSD/GPL", may be used). Some helper functions are only accessible to +programs that are compatible with the GNU Privacy License (GPL). + +In order to use such helpers, the eBPF program must be loaded with the correct +license string passed (via **attr**) to the **bpf**\ () system call, and this +generally translates into the C source code of the program containing a line +similar to the following: + +:: + + char ____license[] __attribute__((section("license"), used)) = "GPL"; + +IMPLEMENTATION +============== + +This manual page is an effort to document the existing eBPF helper functions. +But as of this writing, the BPF sub-system is under heavy development. New eBPF +program or map types are added, along with new helper functions. Some helpers +are occasionally made available for additional program types. So in spite of +the efforts of the community, this page might not be up-to-date. If you want to +check by yourself what helper functions exist in your kernel, or what types of +programs they can support, here are some files among the kernel tree that you +may be interested in: + +* *include/uapi/linux/bpf.h* is the main BPF header. It contains the full list + of all helper functions, as well as many other BPF definitions including most + of the flags, structs or constants used by the helpers. +* *net/core/filter.c* contains the definition of most network-related helper + functions, and the list of program types from which they can be used. +* *kernel/trace/bpf_trace.c* is the equivalent for most tracing program-related + helpers. +* *kernel/bpf/verifier.c* contains the functions used to check that valid types + of eBPF maps are used with a given helper function. +* *kernel/bpf/* directory contains other files in which additional helpers are + defined (for cgroups, sockmaps, etc.). +* The bpftool utility can be used to probe the availability of helper functions + on the system (as well as supported program and map types, and a number of + other parameters). To do so, run **bpftool feature probe** (see + **bpftool-feature**\ (8) for details). Add the **unprivileged** keyword to + list features available to unprivileged users. + +Compatibility between helper functions and program types can generally be found +in the files where helper functions are defined. Look for the **struct +bpf_func_proto** objects and for functions returning them: these functions +contain a list of helpers that a given program type can call. Note that the +**default:** label of the **switch ... case** used to filter helpers can call +other functions, themselves allowing access to additional helpers. The +requirement for GPL license is also in those **struct bpf_func_proto**. + +Compatibility between helper functions and map types can be found in the +**check_map_func_compatibility**\ () function in file *kernel/bpf/verifier.c*. + +Helper functions that invalidate the checks on **data** and **data_end** +pointers for network processing are listed in function +**bpf_helper_changes_pkt_data**\ () in file *net/core/filter.c*. + +SEE ALSO +======== + +**bpf**\ (2), +**bpftool**\ (8), +**cgroups**\ (7), +**ip**\ (8), +**perf_event_open**\ (2), +**sendmsg**\ (2), +**socket**\ (7), +**tc-bpf**\ (8)''' + print(footer) + + def print_proto(self, helper): + """ + Format function protocol with bold and italics markers. This makes RST + file less readable, but gives nice results in the manual page. + """ + proto = helper.proto_break_down() + + print('**%s %s%s(' % (proto['ret_type'], + proto['ret_star'].replace('*', '\\*'), + proto['name']), + end='') + + comma = '' + for a in proto['args']: + one_arg = '{}{}'.format(comma, a['type']) + if a['name']: + if a['star']: + one_arg += ' {}**\ '.format(a['star'].replace('*', '\\*')) + else: + one_arg += '** ' + one_arg += '*{}*\\ **'.format(a['name']) + comma = ', ' + print(one_arg, end='') + + print(')**') + + def print_one(self, helper): + self.print_proto(helper) + + if (helper.desc): + print('\tDescription') + # Do not strip all newline characters: formatted code at the end of + # a section must be followed by a blank line. + for line in re.sub('\n$', '', helper.desc, count=1).split('\n'): + print('{}{}'.format('\t\t' if line else '', line)) + + if (helper.ret): + print('\tReturn') + for line in helper.ret.rstrip().split('\n'): + print('{}{}'.format('\t\t' if line else '', line)) + + print('') + +class PrinterHelpers(Printer): + """ + A printer for dumping collected information about helpers as C header to + be included from BPF program. + @helpers: array of Helper objects to print to standard output + """ + + type_fwds = [ + 'struct bpf_fib_lookup', + 'struct bpf_sk_lookup', + 'struct bpf_perf_event_data', + 'struct bpf_perf_event_value', + 'struct bpf_pidns_info', + 'struct bpf_redir_neigh', + 'struct bpf_sock', + 'struct bpf_sock_addr', + 'struct bpf_sock_ops', + 'struct bpf_sock_tuple', + 'struct bpf_spin_lock', + 'struct bpf_sysctl', + 'struct bpf_tcp_sock', + 'struct bpf_tunnel_key', + 'struct bpf_xfrm_state', + 'struct linux_binprm', + 'struct pt_regs', + 'struct sk_reuseport_md', + 'struct sockaddr', + 'struct tcphdr', + 'struct seq_file', + 'struct tcp6_sock', + 'struct tcp_sock', + 'struct tcp_timewait_sock', + 'struct tcp_request_sock', + 'struct udp6_sock', + 'struct task_struct', + + 'struct __sk_buff', + 'struct sk_msg_md', + 'struct xdp_md', + 'struct path', + 'struct btf_ptr', + 'struct inode', + ] + known_types = { + '...', + 'void', + 'const void', + 'char', + 'const char', + 'int', + 'long', + 'unsigned long', + + '__be16', + '__be32', + '__wsum', + + 'struct bpf_fib_lookup', + 'struct bpf_perf_event_data', + 'struct bpf_perf_event_value', + 'struct bpf_pidns_info', + 'struct bpf_redir_neigh', + 'struct bpf_sk_lookup', + 'struct bpf_sock', + 'struct bpf_sock_addr', + 'struct bpf_sock_ops', + 'struct bpf_sock_tuple', + 'struct bpf_spin_lock', + 'struct bpf_sysctl', + 'struct bpf_tcp_sock', + 'struct bpf_tunnel_key', + 'struct bpf_xfrm_state', + 'struct linux_binprm', + 'struct pt_regs', + 'struct sk_reuseport_md', + 'struct sockaddr', + 'struct tcphdr', + 'struct seq_file', + 'struct tcp6_sock', + 'struct tcp_sock', + 'struct tcp_timewait_sock', + 'struct tcp_request_sock', + 'struct udp6_sock', + 'struct task_struct', + 'struct path', + 'struct btf_ptr', + 'struct inode', + } + mapped_types = { + 'u8': '__u8', + 'u16': '__u16', + 'u32': '__u32', + 'u64': '__u64', + 's8': '__s8', + 's16': '__s16', + 's32': '__s32', + 's64': '__s64', + 'size_t': 'unsigned long', + 'struct bpf_map': 'void', + 'struct sk_buff': 'struct __sk_buff', + 'const struct sk_buff': 'const struct __sk_buff', + 'struct sk_msg_buff': 'struct sk_msg_md', + 'struct xdp_buff': 'struct xdp_md', + } + # Helpers overloaded for different context types. + overloaded_helpers = [ + 'bpf_get_socket_cookie', + 'bpf_sk_assign', + ] + + def print_header(self): + header = '''\ +/* This is auto-generated file. See bpf_helpers_doc.py for details. */ + +/* Forward declarations of BPF structs */''' + + print(header) + for fwd in self.type_fwds: + print('%s;' % fwd) + print('') + + def print_footer(self): + footer = '' + print(footer) + + def map_type(self, t): + if t in self.known_types: + return t + if t in self.mapped_types: + return self.mapped_types[t] + print("Unrecognized type '%s', please add it to known types!" % t, + file=sys.stderr) + sys.exit(1) + + seen_helpers = set() + + def print_one(self, helper): + proto = helper.proto_break_down() + + if proto['name'] in self.seen_helpers: + return + self.seen_helpers.add(proto['name']) + + print('/*') + print(" * %s" % proto['name']) + print(" *") + if (helper.desc): + # Do not strip all newline characters: formatted code at the end of + # a section must be followed by a blank line. + for line in re.sub('\n$', '', helper.desc, count=1).split('\n'): + print(' *{}{}'.format(' \t' if line else '', line)) + + if (helper.ret): + print(' *') + print(' * Returns') + for line in helper.ret.rstrip().split('\n'): + print(' *{}{}'.format(' \t' if line else '', line)) + + print(' */') + print('static %s %s(*%s)(' % (self.map_type(proto['ret_type']), + proto['ret_star'], proto['name']), end='') + comma = '' + for i, a in enumerate(proto['args']): + t = a['type'] + n = a['name'] + if proto['name'] in self.overloaded_helpers and i == 0: + t = 'void' + n = 'ctx' + one_arg = '{}{}'.format(comma, self.map_type(t)) + if n: + if a['star']: + one_arg += ' {}'.format(a['star']) + else: + one_arg += ' ' + one_arg += '{}'.format(n) + comma = ', ' + print(one_arg, end='') + + print(') = (void *) %d;' % len(self.seen_helpers)) + print('') + +############################################################################### + +# If script is launched from scripts/ from kernel tree and can access +# ../include/uapi/linux/bpf.h, use it as a default name for the file to parse, +# otherwise the --filename argument will be required from the command line. +script = os.path.abspath(sys.argv[0]) +linuxRoot = os.path.dirname(os.path.dirname(script)) +bpfh = os.path.join(linuxRoot, 'include/uapi/linux/bpf.h') + +argParser = argparse.ArgumentParser(description=""" +Parse eBPF header file and generate documentation for eBPF helper functions. +The RST-formatted output produced can be turned into a manual page with the +rst2man utility. +""") +argParser.add_argument('--header', action='store_true', + help='generate C header file') +if (os.path.isfile(bpfh)): + argParser.add_argument('--filename', help='path to include/uapi/linux/bpf.h', + default=bpfh) +else: + argParser.add_argument('--filename', help='path to include/uapi/linux/bpf.h') +args = argParser.parse_args() + +# Parse file. +headerParser = HeaderParser(args.filename) +headerParser.run() + +# Print formatted output to standard output. +if args.header: + printer = PrinterHelpers(headerParser.helpers) +else: + printer = PrinterRST(headerParser.helpers) +printer.print_all() diff --git a/src/net/scripts/cc-can-link.sh b/src/net/scripts/cc-can-link.sh new file mode 100755 index 0000000..6efcead --- /dev/null +++ b/src/net/scripts/cc-can-link.sh @@ -0,0 +1,11 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0 + +cat << "END" | $@ -x c - -o /dev/null >/dev/null 2>&1 +#include +int main(void) +{ + printf(""); + return 0; +} +END diff --git a/src/net/scripts/check-sysctl-docs b/src/net/scripts/check-sysctl-docs new file mode 100755 index 0000000..8bcb9e2 --- /dev/null +++ b/src/net/scripts/check-sysctl-docs @@ -0,0 +1,181 @@ +#!/usr/bin/gawk -f +# SPDX-License-Identifier: GPL-2.0 + +# Script to check sysctl documentation against source files +# +# Copyright (c) 2020 Stephen Kitt + +# Example invocation: +# scripts/check-sysctl-docs -vtable="kernel" \ +# Documentation/admin-guide/sysctl/kernel.rst \ +# $(git grep -l register_sysctl_) +# +# Specify -vdebug=1 to see debugging information + +BEGIN { + if (!table) { + print "Please specify the table to look for using the table variable" > "/dev/stderr" + exit 1 + } +} + +# The following globals are used: +# children: maps ctl_table names and procnames to child ctl_table names +# documented: maps documented entries (each key is an entry) +# entries: maps ctl_table names and procnames to counts (so +# enumerating the subkeys for a given ctl_table lists its +# procnames) +# files: maps procnames to source file names +# paths: maps ctl_path names to paths +# curpath: the name of the current ctl_path struct +# curtable: the name of the current ctl_table struct +# curentry: the name of the current proc entry (procname when parsing +# a ctl_table, constructed path when parsing a ctl_path) + + +# Remove punctuation from the given value +function trimpunct(value) { + while (value ~ /^["&]/) { + value = substr(value, 2) + } + while (value ~ /[]["&,}]$/) { + value = substr(value, 1, length(value) - 1) + } + return value +} + +# Print the information for the given entry +function printentry(entry) { + seen[entry]++ + printf "* %s from %s", entry, file[entry] + if (documented[entry]) { + printf " (documented)" + } + print "" +} + + +# Stage 1: build the list of documented entries +FNR == NR && /^=+$/ { + if (prevline ~ /Documentation for/) { + # This is the main title + next + } + + # The previous line is a section title, parse it + $0 = prevline + if (debug) print "Parsing " $0 + inbrackets = 0 + for (i = 1; i <= NF; i++) { + if (length($i) == 0) { + continue + } + if (!inbrackets && substr($i, 1, 1) == "(") { + inbrackets = 1 + } + if (!inbrackets) { + token = trimpunct($i) + if (length(token) > 0 && token != "and") { + if (debug) print trimpunct($i) + documented[trimpunct($i)]++ + } + } + if (inbrackets && substr($i, length($i), 1) == ")") { + inbrackets = 0 + } + } +} + +FNR == NR { + prevline = $0 + next +} + + +# Stage 2: process each file and find all sysctl tables +BEGINFILE { + delete children + delete entries + delete paths + curpath = "" + curtable = "" + curentry = "" + if (debug) print "Processing file " FILENAME +} + +/^static struct ctl_path/ { + match($0, /static struct ctl_path ([^][]+)/, tables) + curpath = tables[1] + if (debug) print "Processing path " curpath +} + +/^static struct ctl_table/ { + match($0, /static struct ctl_table ([^][]+)/, tables) + curtable = tables[1] + if (debug) print "Processing table " curtable +} + +/^};$/ { + curpath = "" + curtable = "" + curentry = "" +} + +curpath && /\.procname[\t ]*=[\t ]*".+"/ { + match($0, /.procname[\t ]*=[\t ]*"([^"]+)"/, names) + if (curentry) { + curentry = curentry "/" names[1] + } else { + curentry = names[1] + } + if (debug) print "Setting path " curpath " to " curentry + paths[curpath] = curentry +} + +curtable && /\.procname[\t ]*=[\t ]*".+"/ { + match($0, /.procname[\t ]*=[\t ]*"([^"]+)"/, names) + curentry = names[1] + if (debug) print "Adding entry " curentry " to table " curtable + entries[curtable][curentry]++ + file[curentry] = FILENAME +} + +/\.child[\t ]*=/ { + child = trimpunct($NF) + if (debug) print "Linking child " child " to table " curtable " entry " curentry + children[curtable][curentry] = child +} + +/register_sysctl_table\(.*\)/ { + match($0, /register_sysctl_table\(([^)]+)\)/, tables) + if (debug) print "Registering table " tables[1] + if (children[tables[1]][table]) { + for (entry in entries[children[tables[1]][table]]) { + printentry(entry) + } + } +} + +/register_sysctl_paths\(.*\)/ { + match($0, /register_sysctl_paths\(([^)]+), ([^)]+)\)/, tables) + if (debug) print "Attaching table " tables[2] " to path " tables[1] + if (paths[tables[1]] == table) { + for (entry in entries[tables[2]]) { + printentry(entry) + } + } + split(paths[tables[1]], components, "/") + if (length(components) > 1 && components[1] == table) { + # Count the first subdirectory as seen + seen[components[2]]++ + } +} + + +END { + for (entry in documented) { + if (!seen[entry]) { + print "No implementation for " entry + } + } +} diff --git a/src/net/scripts/check_extable.sh b/src/net/scripts/check_extable.sh new file mode 100755 index 0000000..93af93c --- /dev/null +++ b/src/net/scripts/check_extable.sh @@ -0,0 +1,147 @@ +#! /bin/bash +# SPDX-License-Identifier: GPL-2.0 +# (c) 2015, Quentin Casasnovas + +obj=$1 + +file ${obj} | grep -q ELF || (echo "${obj} is not and ELF file." 1>&2 ; exit 0) + +# Bail out early if there isn't an __ex_table section in this object file. +objdump -hj __ex_table ${obj} 2> /dev/null > /dev/null +[ $? -ne 0 ] && exit 0 + +white_list=.text,.fixup + +suspicious_relocs=$(objdump -rj __ex_table ${obj} | tail -n +6 | + grep -v $(eval echo -e{${white_list}}) | awk '{print $3}') + +# No suspicious relocs in __ex_table, jobs a good'un +[ -z "${suspicious_relocs}" ] && exit 0 + + +# After this point, something is seriously wrong since we just found out we +# have some relocations in __ex_table which point to sections which aren't +# white listed. If you're adding a new section in the Linux kernel, and +# you're expecting this section to contain code which can fault (i.e. the +# __ex_table relocation to your new section is expected), simply add your +# new section to the white_list variable above. If not, you're probably +# doing something wrong and the rest of this code is just trying to print +# you more information about it. + +function find_section_offset_from_symbol() +{ + eval $(objdump -t ${obj} | grep ${1} | sed 's/\([0-9a-f]\+\) .\{7\} \([^ \t]\+\).*/section="\2"; section_offset="0x\1" /') + + # addr2line takes addresses in hexadecimal... + section_offset=$(printf "0x%016x" $(( ${section_offset} + $2 )) ) +} + +function find_symbol_and_offset_from_reloc() +{ + # Extract symbol and offset from the objdump output + eval $(echo $reloc | sed 's/\([^+]\+\)+\?\(0x[0-9a-f]\+\)\?/symbol="\1"; symbol_offset="\2"/') + + # When the relocation points to the begining of a symbol or section, it + # won't print the offset since it is zero. + if [ -z "${symbol_offset}" ]; then + symbol_offset=0x0 + fi +} + +function find_alt_replacement_target() +{ + # The target of the .altinstr_replacement is the relocation just before + # the .altinstr_replacement one. + eval $(objdump -rj .altinstructions ${obj} | grep -B1 "${section}+${section_offset}" | head -n1 | awk '{print $3}' | + sed 's/\([^+]\+\)+\(0x[0-9a-f]\+\)/alt_target_section="\1"; alt_target_offset="\2"/') +} + +function handle_alt_replacement_reloc() +{ + # This will define alt_target_section and alt_target_section_offset + find_alt_replacement_target ${section} ${section_offset} + + echo "Error: found a reference to .altinstr_replacement in __ex_table:" + addr2line -fip -j ${alt_target_section} -e ${obj} ${alt_target_offset} | awk '{print "\t" $0}' + + error=true +} + +function is_executable_section() +{ + objdump -hwj ${section} ${obj} | grep -q CODE + return $? +} + +function handle_suspicious_generic_reloc() +{ + if is_executable_section ${section}; then + # We've got a relocation to a non white listed _executable_ + # section, print a warning so the developper adds the section to + # the white list or fix his code. We try to pretty-print the file + # and line number where that relocation was added. + echo "Warning: found a reference to section \"${section}\" in __ex_table:" + addr2line -fip -j ${section} -e ${obj} ${section_offset} | awk '{print "\t" $0}' + else + # Something is definitively wrong here since we've got a relocation + # to a non-executable section, there's no way this would ever be + # running in the kernel. + echo "Error: found a reference to non-executable section \"${section}\" in __ex_table at offset ${section_offset}" + error=true + fi +} + +function handle_suspicious_reloc() +{ + case "${section}" in + ".altinstr_replacement") + handle_alt_replacement_reloc ${section} ${section_offset} + ;; + *) + handle_suspicious_generic_reloc ${section} ${section_offset} + ;; + esac +} + +function diagnose() +{ + + for reloc in ${suspicious_relocs}; do + # Let's find out where the target of the relocation in __ex_table + # is, this will define ${symbol} and ${symbol_offset} + find_symbol_and_offset_from_reloc ${reloc} + + # When there's a global symbol at the place of the relocation, + # objdump will use it instead of giving us a section+offset, so + # let's find out which section is this symbol in and the total + # offset withing that section. + find_section_offset_from_symbol ${symbol} ${symbol_offset} + + # In this case objdump was presenting us with a reloc to a symbol + # rather than a section. Now that we've got the actual section, + # we can skip it if it's in the white_list. + if [ -z "$( echo $section | grep -v $(eval echo -e{${white_list}}))" ]; then + continue; + fi + + # Will either print a warning if the relocation happens to be in a + # section we do not know but has executable bit set, or error out. + handle_suspicious_reloc + done +} + +function check_debug_info() { + objdump -hj .debug_info ${obj} 2> /dev/null > /dev/null || + echo -e "${obj} does not contain debug information, the addr2line output will be limited.\n" \ + "Recompile ${obj} with CONFIG_DEBUG_INFO to get a more useful output." +} + +check_debug_info + +diagnose + +if [ "${error}" ]; then + exit 1 +fi + +exit 0 diff --git a/src/net/scripts/checkincludes.pl b/src/net/scripts/checkincludes.pl new file mode 100755 index 0000000..b514a95 --- /dev/null +++ b/src/net/scripts/checkincludes.pl @@ -0,0 +1,98 @@ +#!/usr/bin/env perl +# SPDX-License-Identifier: GPL-2.0 +# +# checkincludes: find/remove files included more than once +# +# Copyright abandoned, 2000, Niels Kristian Bech Jensen . +# Copyright 2009 Luis R. Rodriguez +# +# This script checks for duplicate includes. It also has support +# to remove them in place. Note that this will not take into +# consideration macros so you should run this only if you know +# you do have real dups and do not have them under #ifdef's. You +# could also just review the results. + +use strict; + +sub usage { + print "Usage: checkincludes.pl [-r]\n"; + print "By default we just warn of duplicates\n"; + print "To remove duplicated includes in place use -r\n"; + exit 1; +} + +my $remove = 0; + +if ($#ARGV < 0) { + usage(); +} + +if ($#ARGV >= 1) { + if ($ARGV[0] =~ /^-/) { + if ($ARGV[0] eq "-r") { + $remove = 1; + shift; + } else { + usage(); + } + } +} + +my $dup_counter = 0; + +foreach my $file (@ARGV) { + open(my $f, '<', $file) + or die "Cannot open $file: $!.\n"; + + my %includedfiles = (); + my @file_lines = (); + + while (<$f>) { + if (m/^\s*#\s*include\s*[<"](\S*)[>"]/o) { + ++$includedfiles{$1}; + } + push(@file_lines, $_); + } + + close($f); + + if (!$remove) { + foreach my $filename (keys %includedfiles) { + if ($includedfiles{$filename} > 1) { + print "$file: $filename is included more than once.\n"; + ++$dup_counter; + } + } + next; + } + + open($f, '>', $file) + or die("Cannot write to $file: $!"); + + my $dups = 0; + foreach (@file_lines) { + if (m/^\s*#\s*include\s*[<"](\S*)[>"]/o) { + foreach my $filename (keys %includedfiles) { + if ($1 eq $filename) { + if ($includedfiles{$filename} > 1) { + $includedfiles{$filename}--; + $dups++; + ++$dup_counter; + } else { + print {$f} $_; + } + } + } + } else { + print {$f} $_; + } + } + if ($dups > 0) { + print "$file: removed $dups duplicate includes\n"; + } + close($f); +} + +if ($dup_counter == 0) { + print "No duplicate includes found.\n"; +} diff --git a/src/net/scripts/checkkconfigsymbols.py b/src/net/scripts/checkkconfigsymbols.py new file mode 100755 index 0000000..1548f9c --- /dev/null +++ b/src/net/scripts/checkkconfigsymbols.py @@ -0,0 +1,476 @@ +#!/usr/bin/env python3 +# SPDX-License-Identifier: GPL-2.0-only + +"""Find Kconfig symbols that are referenced but not defined.""" + +# (c) 2014-2017 Valentin Rothberg +# (c) 2014 Stefan Hengelein +# + + +import argparse +import difflib +import os +import re +import signal +import subprocess +import sys +from multiprocessing import Pool, cpu_count + + +# regex expressions +OPERATORS = r"&|\(|\)|\||\!" +SYMBOL = r"(?:\w*[A-Z0-9]\w*){2,}" +DEF = r"^\s*(?:menu){,1}config\s+(" + SYMBOL + r")\s*" +EXPR = r"(?:" + OPERATORS + r"|\s|" + SYMBOL + r")+" +DEFAULT = r"default\s+.*?(?:if\s.+){,1}" +STMT = r"^\s*(?:if|select|imply|depends\s+on|(?:" + DEFAULT + r"))\s+" + EXPR +SOURCE_SYMBOL = r"(?:\W|\b)+[D]{,1}CONFIG_(" + SYMBOL + r")" + +# regex objects +REGEX_FILE_KCONFIG = re.compile(r".*Kconfig[\.\w+\-]*$") +REGEX_SYMBOL = re.compile(r'(?!\B)' + SYMBOL + r'(?!\B)') +REGEX_SOURCE_SYMBOL = re.compile(SOURCE_SYMBOL) +REGEX_KCONFIG_DEF = re.compile(DEF) +REGEX_KCONFIG_EXPR = re.compile(EXPR) +REGEX_KCONFIG_STMT = re.compile(STMT) +REGEX_KCONFIG_HELP = re.compile(r"^\s+help\s*$") +REGEX_FILTER_SYMBOLS = re.compile(r"[A-Za-z0-9]$") +REGEX_NUMERIC = re.compile(r"0[xX][0-9a-fA-F]+|[0-9]+") +REGEX_QUOTES = re.compile("(\"(.*?)\")") + + +def parse_options(): + """The user interface of this module.""" + usage = "Run this tool to detect Kconfig symbols that are referenced but " \ + "not defined in Kconfig. If no option is specified, " \ + "checkkconfigsymbols defaults to check your current tree. " \ + "Please note that specifying commits will 'git reset --hard\' " \ + "your current tree! You may save uncommitted changes to avoid " \ + "losing data." + + parser = argparse.ArgumentParser(description=usage) + + parser.add_argument('-c', '--commit', dest='commit', action='store', + default="", + help="check if the specified commit (hash) introduces " + "undefined Kconfig symbols") + + parser.add_argument('-d', '--diff', dest='diff', action='store', + default="", + help="diff undefined symbols between two commits " + "(e.g., -d commmit1..commit2)") + + parser.add_argument('-f', '--find', dest='find', action='store_true', + default=False, + help="find and show commits that may cause symbols to be " + "missing (required to run with --diff)") + + parser.add_argument('-i', '--ignore', dest='ignore', action='store', + default="", + help="ignore files matching this Python regex " + "(e.g., -i '.*defconfig')") + + parser.add_argument('-s', '--sim', dest='sim', action='store', default="", + help="print a list of max. 10 string-similar symbols") + + parser.add_argument('--force', dest='force', action='store_true', + default=False, + help="reset current Git tree even when it's dirty") + + parser.add_argument('--no-color', dest='color', action='store_false', + default=True, + help="don't print colored output (default when not " + "outputting to a terminal)") + + args = parser.parse_args() + + if args.commit and args.diff: + sys.exit("Please specify only one option at once.") + + if args.diff and not re.match(r"^[\w\-\.\^]+\.\.[\w\-\.\^]+$", args.diff): + sys.exit("Please specify valid input in the following format: " + "\'commit1..commit2\'") + + if args.commit or args.diff: + if not args.force and tree_is_dirty(): + sys.exit("The current Git tree is dirty (see 'git status'). " + "Running this script may\ndelete important data since it " + "calls 'git reset --hard' for some performance\nreasons. " + " Please run this script in a clean Git tree or pass " + "'--force' if you\nwant to ignore this warning and " + "continue.") + + if args.commit: + args.find = False + + if args.ignore: + try: + re.match(args.ignore, "this/is/just/a/test.c") + except: + sys.exit("Please specify a valid Python regex.") + + return args + + +def main(): + """Main function of this module.""" + args = parse_options() + + global COLOR + COLOR = args.color and sys.stdout.isatty() + + if args.sim and not args.commit and not args.diff: + sims = find_sims(args.sim, args.ignore) + if sims: + print("%s: %s" % (yel("Similar symbols"), ', '.join(sims))) + else: + print("%s: no similar symbols found" % yel("Similar symbols")) + sys.exit(0) + + # dictionary of (un)defined symbols + defined = {} + undefined = {} + + if args.commit or args.diff: + head = get_head() + + # get commit range + commit_a = None + commit_b = None + if args.commit: + commit_a = args.commit + "~" + commit_b = args.commit + elif args.diff: + split = args.diff.split("..") + commit_a = split[0] + commit_b = split[1] + undefined_a = {} + undefined_b = {} + + # get undefined items before the commit + reset(commit_a) + undefined_a, _ = check_symbols(args.ignore) + + # get undefined items for the commit + reset(commit_b) + undefined_b, defined = check_symbols(args.ignore) + + # report cases that are present for the commit but not before + for symbol in sorted(undefined_b): + # symbol has not been undefined before + if symbol not in undefined_a: + files = sorted(undefined_b.get(symbol)) + undefined[symbol] = files + # check if there are new files that reference the undefined symbol + else: + files = sorted(undefined_b.get(symbol) - + undefined_a.get(symbol)) + if files: + undefined[symbol] = files + + # reset to head + reset(head) + + # default to check the entire tree + else: + undefined, defined = check_symbols(args.ignore) + + # now print the output + for symbol in sorted(undefined): + print(red(symbol)) + + files = sorted(undefined.get(symbol)) + print("%s: %s" % (yel("Referencing files"), ", ".join(files))) + + sims = find_sims(symbol, args.ignore, defined) + sims_out = yel("Similar symbols") + if sims: + print("%s: %s" % (sims_out, ', '.join(sims))) + else: + print("%s: %s" % (sims_out, "no similar symbols found")) + + if args.find: + print("%s:" % yel("Commits changing symbol")) + commits = find_commits(symbol, args.diff) + if commits: + for commit in commits: + commit = commit.split(" ", 1) + print("\t- %s (\"%s\")" % (yel(commit[0]), commit[1])) + else: + print("\t- no commit found") + print() # new line + + +def reset(commit): + """Reset current git tree to %commit.""" + execute(["git", "reset", "--hard", commit]) + + +def yel(string): + """ + Color %string yellow. + """ + return "\033[33m%s\033[0m" % string if COLOR else string + + +def red(string): + """ + Color %string red. + """ + return "\033[31m%s\033[0m" % string if COLOR else string + + +def execute(cmd): + """Execute %cmd and return stdout. Exit in case of error.""" + try: + stdout = subprocess.check_output(cmd, stderr=subprocess.STDOUT, shell=False) + stdout = stdout.decode(errors='replace') + except subprocess.CalledProcessError as fail: + exit(fail) + return stdout + + +def find_commits(symbol, diff): + """Find commits changing %symbol in the given range of %diff.""" + commits = execute(["git", "log", "--pretty=oneline", + "--abbrev-commit", "-G", + symbol, diff]) + return [x for x in commits.split("\n") if x] + + +def tree_is_dirty(): + """Return true if the current working tree is dirty (i.e., if any file has + been added, deleted, modified, renamed or copied but not committed).""" + stdout = execute(["git", "status", "--porcelain"]) + for line in stdout: + if re.findall(r"[URMADC]{1}", line[:2]): + return True + return False + + +def get_head(): + """Return commit hash of current HEAD.""" + stdout = execute(["git", "rev-parse", "HEAD"]) + return stdout.strip('\n') + + +def partition(lst, size): + """Partition list @lst into eveni-sized lists of size @size.""" + return [lst[i::size] for i in range(size)] + + +def init_worker(): + """Set signal handler to ignore SIGINT.""" + signal.signal(signal.SIGINT, signal.SIG_IGN) + + +def find_sims(symbol, ignore, defined=[]): + """Return a list of max. ten Kconfig symbols that are string-similar to + @symbol.""" + if defined: + return difflib.get_close_matches(symbol, set(defined), 10) + + pool = Pool(cpu_count(), init_worker) + kfiles = [] + for gitfile in get_files(): + if REGEX_FILE_KCONFIG.match(gitfile): + kfiles.append(gitfile) + + arglist = [] + for part in partition(kfiles, cpu_count()): + arglist.append((part, ignore)) + + for res in pool.map(parse_kconfig_files, arglist): + defined.extend(res[0]) + + return difflib.get_close_matches(symbol, set(defined), 10) + + +def get_files(): + """Return a list of all files in the current git directory.""" + # use 'git ls-files' to get the worklist + stdout = execute(["git", "ls-files"]) + if len(stdout) > 0 and stdout[-1] == "\n": + stdout = stdout[:-1] + + files = [] + for gitfile in stdout.rsplit("\n"): + if ".git" in gitfile or "ChangeLog" in gitfile or \ + ".log" in gitfile or os.path.isdir(gitfile) or \ + gitfile.startswith("tools/"): + continue + files.append(gitfile) + return files + + +def check_symbols(ignore): + """Find undefined Kconfig symbols and return a dict with the symbol as key + and a list of referencing files as value. Files matching %ignore are not + checked for undefined symbols.""" + pool = Pool(cpu_count(), init_worker) + try: + return check_symbols_helper(pool, ignore) + except KeyboardInterrupt: + pool.terminate() + pool.join() + sys.exit(1) + + +def check_symbols_helper(pool, ignore): + """Helper method for check_symbols(). Used to catch keyboard interrupts in + check_symbols() in order to properly terminate running worker processes.""" + source_files = [] + kconfig_files = [] + defined_symbols = [] + referenced_symbols = dict() # {file: [symbols]} + + for gitfile in get_files(): + if REGEX_FILE_KCONFIG.match(gitfile): + kconfig_files.append(gitfile) + else: + if ignore and not re.match(ignore, gitfile): + continue + # add source files that do not match the ignore pattern + source_files.append(gitfile) + + # parse source files + arglist = partition(source_files, cpu_count()) + for res in pool.map(parse_source_files, arglist): + referenced_symbols.update(res) + + # parse kconfig files + arglist = [] + for part in partition(kconfig_files, cpu_count()): + arglist.append((part, ignore)) + for res in pool.map(parse_kconfig_files, arglist): + defined_symbols.extend(res[0]) + referenced_symbols.update(res[1]) + defined_symbols = set(defined_symbols) + + # inverse mapping of referenced_symbols to dict(symbol: [files]) + inv_map = dict() + for _file, symbols in referenced_symbols.items(): + for symbol in symbols: + inv_map[symbol] = inv_map.get(symbol, set()) + inv_map[symbol].add(_file) + referenced_symbols = inv_map + + undefined = {} # {symbol: [files]} + for symbol in sorted(referenced_symbols): + # filter some false positives + if symbol == "FOO" or symbol == "BAR" or \ + symbol == "FOO_BAR" or symbol == "XXX": + continue + if symbol not in defined_symbols: + if symbol.endswith("_MODULE"): + # avoid false positives for kernel modules + if symbol[:-len("_MODULE")] in defined_symbols: + continue + undefined[symbol] = referenced_symbols.get(symbol) + return undefined, defined_symbols + + +def parse_source_files(source_files): + """Parse each source file in @source_files and return dictionary with source + files as keys and lists of references Kconfig symbols as values.""" + referenced_symbols = dict() + for sfile in source_files: + referenced_symbols[sfile] = parse_source_file(sfile) + return referenced_symbols + + +def parse_source_file(sfile): + """Parse @sfile and return a list of referenced Kconfig symbols.""" + lines = [] + references = [] + + if not os.path.exists(sfile): + return references + + with open(sfile, "r", encoding='utf-8', errors='replace') as stream: + lines = stream.readlines() + + for line in lines: + if "CONFIG_" not in line: + continue + symbols = REGEX_SOURCE_SYMBOL.findall(line) + for symbol in symbols: + if not REGEX_FILTER_SYMBOLS.search(symbol): + continue + references.append(symbol) + + return references + + +def get_symbols_in_line(line): + """Return mentioned Kconfig symbols in @line.""" + return REGEX_SYMBOL.findall(line) + + +def parse_kconfig_files(args): + """Parse kconfig files and return tuple of defined and references Kconfig + symbols. Note, @args is a tuple of a list of files and the @ignore + pattern.""" + kconfig_files = args[0] + ignore = args[1] + defined_symbols = [] + referenced_symbols = dict() + + for kfile in kconfig_files: + defined, references = parse_kconfig_file(kfile) + defined_symbols.extend(defined) + if ignore and re.match(ignore, kfile): + # do not collect references for files that match the ignore pattern + continue + referenced_symbols[kfile] = references + return (defined_symbols, referenced_symbols) + + +def parse_kconfig_file(kfile): + """Parse @kfile and update symbol definitions and references.""" + lines = [] + defined = [] + references = [] + skip = False + + if not os.path.exists(kfile): + return defined, references + + with open(kfile, "r", encoding='utf-8', errors='replace') as stream: + lines = stream.readlines() + + for i in range(len(lines)): + line = lines[i] + line = line.strip('\n') + line = line.split("#")[0] # ignore comments + + if REGEX_KCONFIG_DEF.match(line): + symbol_def = REGEX_KCONFIG_DEF.findall(line) + defined.append(symbol_def[0]) + skip = False + elif REGEX_KCONFIG_HELP.match(line): + skip = True + elif skip: + # ignore content of help messages + pass + elif REGEX_KCONFIG_STMT.match(line): + line = REGEX_QUOTES.sub("", line) + symbols = get_symbols_in_line(line) + # multi-line statements + while line.endswith("\\"): + i += 1 + line = lines[i] + line = line.strip('\n') + symbols.extend(get_symbols_in_line(line)) + for symbol in set(symbols): + if REGEX_NUMERIC.match(symbol): + # ignore numeric values + continue + references.append(symbol) + + return defined, references + + +if __name__ == "__main__": + main() diff --git a/src/net/scripts/checkpatch.pl b/src/net/scripts/checkpatch.pl new file mode 100755 index 0000000..0ad235e --- /dev/null +++ b/src/net/scripts/checkpatch.pl @@ -0,0 +1,7092 @@ +#!/usr/bin/env perl +# SPDX-License-Identifier: GPL-2.0 +# +# (c) 2001, Dave Jones. (the file handling bit) +# (c) 2005, Joel Schopp (the ugly bit) +# (c) 2007,2008, Andy Whitcroft (new conditions, test suite) +# (c) 2008-2010 Andy Whitcroft +# (c) 2010-2018 Joe Perches + +use strict; +use warnings; +use POSIX; +use File::Basename; +use Cwd 'abs_path'; +use Term::ANSIColor qw(:constants); +use Encode qw(decode encode); + +my $P = $0; +my $D = dirname(abs_path($P)); + +my $V = '0.32'; + +use Getopt::Long qw(:config no_auto_abbrev); + +my $quiet = 0; +my $tree = 1; +my $chk_signoff = 1; +my $chk_patch = 1; +my $tst_only; +my $emacs = 0; +my $terse = 0; +my $showfile = 0; +my $file = 0; +my $git = 0; +my %git_commits = (); +my $check = 0; +my $check_orig = 0; +my $summary = 1; +my $mailback = 0; +my $summary_file = 0; +my $show_types = 0; +my $list_types = 0; +my $fix = 0; +my $fix_inplace = 0; +my $root; +my $gitroot = $ENV{'GIT_DIR'}; +$gitroot = ".git" if !defined($gitroot); +my %debug; +my %camelcase = (); +my %use_type = (); +my @use = (); +my %ignore_type = (); +my @ignore = (); +my $help = 0; +my $configuration_file = ".checkpatch.conf"; +my $max_line_length = 100; +my $ignore_perl_version = 0; +my $minimum_perl_version = 5.10.0; +my $min_conf_desc_length = 4; +my $spelling_file = "$D/spelling.txt"; +my $codespell = 0; +my $codespellfile = "/usr/share/codespell/dictionary.txt"; +my $conststructsfile = "$D/const_structs.checkpatch"; +my $typedefsfile; +my $color = "auto"; +my $allow_c99_comments = 1; # Can be overridden by --ignore C99_COMMENT_TOLERANCE +# git output parsing needs US English output, so first set backtick child process LANGUAGE +my $git_command ='export LANGUAGE=en_US.UTF-8; git'; +my $tabsize = 8; +my ${CONFIG_} = "CONFIG_"; + +sub help { + my ($exitcode) = @_; + + print << "EOM"; +Usage: $P [OPTION]... [FILE]... +Version: $V + +Options: + -q, --quiet quiet + --no-tree run without a kernel tree + --no-signoff do not check for 'Signed-off-by' line + --patch treat FILE as patchfile (default) + --emacs emacs compile window format + --terse one line per report + --showfile emit diffed file position, not input file position + -g, --git treat FILE as a single commit or git revision range + single git commit with: + + ^ + ~n + multiple git commits with: + .. + ... + - + git merges are ignored + -f, --file treat FILE as regular source file + --subjective, --strict enable more subjective tests + --list-types list the possible message types + --types TYPE(,TYPE2...) show only these comma separated message types + --ignore TYPE(,TYPE2...) ignore various comma separated message types + --show-types show the specific message type in the output + --max-line-length=n set the maximum line length, (default $max_line_length) + if exceeded, warn on patches + requires --strict for use with --file + --min-conf-desc-length=n set the min description length, if shorter, warn + --tab-size=n set the number of spaces for tab (default $tabsize) + --root=PATH PATH to the kernel tree root + --no-summary suppress the per-file summary + --mailback only produce a report in case of warnings/errors + --summary-file include the filename in summary + --debug KEY=[0|1] turn on/off debugging of KEY, where KEY is one of + 'values', 'possible', 'type', and 'attr' (default + is all off) + --test-only=WORD report only warnings/errors containing WORD + literally + --fix EXPERIMENTAL - may create horrible results + If correctable single-line errors exist, create + ".EXPERIMENTAL-checkpatch-fixes" + with potential errors corrected to the preferred + checkpatch style + --fix-inplace EXPERIMENTAL - may create horrible results + Is the same as --fix, but overwrites the input + file. It's your fault if there's no backup or git + --ignore-perl-version override checking of perl version. expect + runtime errors. + --codespell Use the codespell dictionary for spelling/typos + (default:/usr/share/codespell/dictionary.txt) + --codespellfile Use this codespell dictionary + --typedefsfile Read additional types from this file + --color[=WHEN] Use colors 'always', 'never', or only when output + is a terminal ('auto'). Default is 'auto'. + --kconfig-prefix=WORD use WORD as a prefix for Kconfig symbols (default + ${CONFIG_}) + -h, --help, --version display this help and exit + +When FILE is - read standard input. +EOM + + exit($exitcode); +} + +sub uniq { + my %seen; + return grep { !$seen{$_}++ } @_; +} + +sub list_types { + my ($exitcode) = @_; + + my $count = 0; + + local $/ = undef; + + open(my $script, '<', abs_path($P)) or + die "$P: Can't read '$P' $!\n"; + + my $text = <$script>; + close($script); + + my @types = (); + # Also catch when type or level is passed through a variable + for ($text =~ /(?:(?:\bCHK|\bWARN|\bERROR|&\{\$msg_level})\s*\(|\$msg_type\s*=)\s*"([^"]+)"/g) { + push (@types, $_); + } + @types = sort(uniq(@types)); + print("#\tMessage type\n\n"); + foreach my $type (@types) { + print(++$count . "\t" . $type . "\n"); + } + + exit($exitcode); +} + +my $conf = which_conf($configuration_file); +if (-f $conf) { + my @conf_args; + open(my $conffile, '<', "$conf") + or warn "$P: Can't find a readable $configuration_file file $!\n"; + + while (<$conffile>) { + my $line = $_; + + $line =~ s/\s*\n?$//g; + $line =~ s/^\s*//g; + $line =~ s/\s+/ /g; + + next if ($line =~ m/^\s*#/); + next if ($line =~ m/^\s*$/); + + my @words = split(" ", $line); + foreach my $word (@words) { + last if ($word =~ m/^#/); + push (@conf_args, $word); + } + } + close($conffile); + unshift(@ARGV, @conf_args) if @conf_args; +} + +# Perl's Getopt::Long allows options to take optional arguments after a space. +# Prevent --color by itself from consuming other arguments +foreach (@ARGV) { + if ($_ eq "--color" || $_ eq "-color") { + $_ = "--color=$color"; + } +} + +GetOptions( + 'q|quiet+' => \$quiet, + 'tree!' => \$tree, + 'signoff!' => \$chk_signoff, + 'patch!' => \$chk_patch, + 'emacs!' => \$emacs, + 'terse!' => \$terse, + 'showfile!' => \$showfile, + 'f|file!' => \$file, + 'g|git!' => \$git, + 'subjective!' => \$check, + 'strict!' => \$check, + 'ignore=s' => \@ignore, + 'types=s' => \@use, + 'show-types!' => \$show_types, + 'list-types!' => \$list_types, + 'max-line-length=i' => \$max_line_length, + 'min-conf-desc-length=i' => \$min_conf_desc_length, + 'tab-size=i' => \$tabsize, + 'root=s' => \$root, + 'summary!' => \$summary, + 'mailback!' => \$mailback, + 'summary-file!' => \$summary_file, + 'fix!' => \$fix, + 'fix-inplace!' => \$fix_inplace, + 'ignore-perl-version!' => \$ignore_perl_version, + 'debug=s' => \%debug, + 'test-only=s' => \$tst_only, + 'codespell!' => \$codespell, + 'codespellfile=s' => \$codespellfile, + 'typedefsfile=s' => \$typedefsfile, + 'color=s' => \$color, + 'no-color' => \$color, #keep old behaviors of -nocolor + 'nocolor' => \$color, #keep old behaviors of -nocolor + 'kconfig-prefix=s' => \${CONFIG_}, + 'h|help' => \$help, + 'version' => \$help +) or help(1); + +help(0) if ($help); + +list_types(0) if ($list_types); + +$fix = 1 if ($fix_inplace); +$check_orig = $check; + +die "$P: --git cannot be used with --file or --fix\n" if ($git && ($file || $fix)); + +my $exit = 0; + +my $perl_version_ok = 1; +if ($^V && $^V lt $minimum_perl_version) { + $perl_version_ok = 0; + printf "$P: requires at least perl version %vd\n", $minimum_perl_version; + exit(1) if (!$ignore_perl_version); +} + +#if no filenames are given, push '-' to read patch from stdin +if ($#ARGV < 0) { + push(@ARGV, '-'); +} + +if ($color =~ /^[01]$/) { + $color = !$color; +} elsif ($color =~ /^always$/i) { + $color = 1; +} elsif ($color =~ /^never$/i) { + $color = 0; +} elsif ($color =~ /^auto$/i) { + $color = (-t STDOUT); +} else { + die "$P: Invalid color mode: $color\n"; +} + +# skip TAB size 1 to avoid additional checks on $tabsize - 1 +die "$P: Invalid TAB size: $tabsize\n" if ($tabsize < 2); + +sub hash_save_array_words { + my ($hashRef, $arrayRef) = @_; + + my @array = split(/,/, join(',', @$arrayRef)); + foreach my $word (@array) { + $word =~ s/\s*\n?$//g; + $word =~ s/^\s*//g; + $word =~ s/\s+/ /g; + $word =~ tr/[a-z]/[A-Z]/; + + next if ($word =~ m/^\s*#/); + next if ($word =~ m/^\s*$/); + + $hashRef->{$word}++; + } +} + +sub hash_show_words { + my ($hashRef, $prefix) = @_; + + if (keys %$hashRef) { + print "\nNOTE: $prefix message types:"; + foreach my $word (sort keys %$hashRef) { + print " $word"; + } + print "\n"; + } +} + +hash_save_array_words(\%ignore_type, \@ignore); +hash_save_array_words(\%use_type, \@use); + +my $dbg_values = 0; +my $dbg_possible = 0; +my $dbg_type = 0; +my $dbg_attr = 0; +for my $key (keys %debug) { + ## no critic + eval "\${dbg_$key} = '$debug{$key}';"; + die "$@" if ($@); +} + +my $rpt_cleaners = 0; + +if ($terse) { + $emacs = 1; + $quiet++; +} + +if ($tree) { + if (defined $root) { + if (!top_of_kernel_tree($root)) { + die "$P: $root: --root does not point at a valid tree\n"; + } + } else { + if (top_of_kernel_tree('.')) { + $root = '.'; + } elsif ($0 =~ m@(.*)/scripts/[^/]*$@ && + top_of_kernel_tree($1)) { + $root = $1; + } + } + + if (!defined $root) { + print "Must be run from the top-level dir. of a kernel tree\n"; + exit(2); + } +} + +my $emitted_corrupt = 0; + +our $Ident = qr{ + [A-Za-z_][A-Za-z\d_]* + (?:\s*\#\#\s*[A-Za-z_][A-Za-z\d_]*)* + }x; +our $Storage = qr{extern|static|asmlinkage}; +our $Sparse = qr{ + __user| + __kernel| + __force| + __iomem| + __must_check| + __kprobes| + __ref| + __refconst| + __refdata| + __rcu| + __private + }x; +our $InitAttributePrefix = qr{__(?:mem|cpu|dev|net_|)}; +our $InitAttributeData = qr{$InitAttributePrefix(?:initdata\b)}; +our $InitAttributeConst = qr{$InitAttributePrefix(?:initconst\b)}; +our $InitAttributeInit = qr{$InitAttributePrefix(?:init\b)}; +our $InitAttribute = qr{$InitAttributeData|$InitAttributeConst|$InitAttributeInit}; + +# Notes to $Attribute: +# We need \b after 'init' otherwise 'initconst' will cause a false positive in a check +our $Attribute = qr{ + const| + __percpu| + __nocast| + __safe| + __bitwise| + __packed__| + __packed2__| + __naked| + __maybe_unused| + __always_unused| + __noreturn| + __used| + __cold| + __pure| + __noclone| + __deprecated| + __read_mostly| + __ro_after_init| + __kprobes| + $InitAttribute| + ____cacheline_aligned| + ____cacheline_aligned_in_smp| + ____cacheline_internodealigned_in_smp| + __weak + }x; +our $Modifier; +our $Inline = qr{inline|__always_inline|noinline|__inline|__inline__}; +our $Member = qr{->$Ident|\.$Ident|\[[^]]*\]}; +our $Lval = qr{$Ident(?:$Member)*}; + +our $Int_type = qr{(?i)llu|ull|ll|lu|ul|l|u}; +our $Binary = qr{(?i)0b[01]+$Int_type?}; +our $Hex = qr{(?i)0x[0-9a-f]+$Int_type?}; +our $Int = qr{[0-9]+$Int_type?}; +our $Octal = qr{0[0-7]+$Int_type?}; +our $String = qr{"[X\t]*"}; +our $Float_hex = qr{(?i)0x[0-9a-f]+p-?[0-9]+[fl]?}; +our $Float_dec = qr{(?i)(?:[0-9]+\.[0-9]*|[0-9]*\.[0-9]+)(?:e-?[0-9]+)?[fl]?}; +our $Float_int = qr{(?i)[0-9]+e-?[0-9]+[fl]?}; +our $Float = qr{$Float_hex|$Float_dec|$Float_int}; +our $Constant = qr{$Float|$Binary|$Octal|$Hex|$Int}; +our $Assignment = qr{\*\=|/=|%=|\+=|-=|<<=|>>=|&=|\^=|\|=|=}; +our $Compare = qr{<=|>=|==|!=|<|(?}; +our $Arithmetic = qr{\+|-|\*|\/|%}; +our $Operators = qr{ + <=|>=|==|!=| + =>|->|<<|>>|<|>|!|~| + &&|\|\||,|\^|\+\+|--|&|\||$Arithmetic + }x; + +our $c90_Keywords = qr{do|for|while|if|else|return|goto|continue|switch|default|case|break}x; + +our $BasicType; +our $NonptrType; +our $NonptrTypeMisordered; +our $NonptrTypeWithAttr; +our $Type; +our $TypeMisordered; +our $Declare; +our $DeclareMisordered; + +our $NON_ASCII_UTF8 = qr{ + [\xC2-\xDF][\x80-\xBF] # non-overlong 2-byte + | \xE0[\xA0-\xBF][\x80-\xBF] # excluding overlongs + | [\xE1-\xEC\xEE\xEF][\x80-\xBF]{2} # straight 3-byte + | \xED[\x80-\x9F][\x80-\xBF] # excluding surrogates + | \xF0[\x90-\xBF][\x80-\xBF]{2} # planes 1-3 + | [\xF1-\xF3][\x80-\xBF]{3} # planes 4-15 + | \xF4[\x80-\x8F][\x80-\xBF]{2} # plane 16 +}x; + +our $UTF8 = qr{ + [\x09\x0A\x0D\x20-\x7E] # ASCII + | $NON_ASCII_UTF8 +}x; + +our $typeC99Typedefs = qr{(?:__)?(?:[us]_?)?int_?(?:8|16|32|64)_t}; +our $typeOtherOSTypedefs = qr{(?x: + u_(?:char|short|int|long) | # bsd + u(?:nchar|short|int|long) # sysv +)}; +our $typeKernelTypedefs = qr{(?x: + (?:__)?(?:u|s|be|le)(?:8|16|32|64)| + atomic_t +)}; +our $typeTypedefs = qr{(?x: + $typeC99Typedefs\b| + $typeOtherOSTypedefs\b| + $typeKernelTypedefs\b +)}; + +our $zero_initializer = qr{(?:(?:0[xX])?0+$Int_type?|NULL|false)\b}; + +our $logFunctions = qr{(?x: + printk(?:_ratelimited|_once|_deferred_once|_deferred|)| + (?:[a-z0-9]+_){1,2}(?:printk|emerg|alert|crit|err|warning|warn|notice|info|debug|dbg|vdbg|devel|cont|WARN)(?:_ratelimited|_once|)| + TP_printk| + WARN(?:_RATELIMIT|_ONCE|)| + panic| + MODULE_[A-Z_]+| + seq_vprintf|seq_printf|seq_puts +)}; + +our $allocFunctions = qr{(?x: + (?:(?:devm_)? + (?:kv|k|v)[czm]alloc(?:_node|_array)? | + kstrdup(?:_const)? | + kmemdup(?:_nul)?) | + (?:\w+)?alloc_skb(?:_ip_align)? | + # dev_alloc_skb/netdev_alloc_skb, et al + dma_alloc_coherent +)}; + +our $signature_tags = qr{(?xi: + Signed-off-by:| + Co-developed-by:| + Acked-by:| + Tested-by:| + Reviewed-by:| + Reported-by:| + Suggested-by:| + To:| + Cc: +)}; + +our @typeListMisordered = ( + qr{char\s+(?:un)?signed}, + qr{int\s+(?:(?:un)?signed\s+)?short\s}, + qr{int\s+short(?:\s+(?:un)?signed)}, + qr{short\s+int(?:\s+(?:un)?signed)}, + qr{(?:un)?signed\s+int\s+short}, + qr{short\s+(?:un)?signed}, + qr{long\s+int\s+(?:un)?signed}, + qr{int\s+long\s+(?:un)?signed}, + qr{long\s+(?:un)?signed\s+int}, + qr{int\s+(?:un)?signed\s+long}, + qr{int\s+(?:un)?signed}, + qr{int\s+long\s+long\s+(?:un)?signed}, + qr{long\s+long\s+int\s+(?:un)?signed}, + qr{long\s+long\s+(?:un)?signed\s+int}, + qr{long\s+long\s+(?:un)?signed}, + qr{long\s+(?:un)?signed}, +); + +our @typeList = ( + qr{void}, + qr{(?:(?:un)?signed\s+)?char}, + qr{(?:(?:un)?signed\s+)?short\s+int}, + qr{(?:(?:un)?signed\s+)?short}, + qr{(?:(?:un)?signed\s+)?int}, + qr{(?:(?:un)?signed\s+)?long\s+int}, + qr{(?:(?:un)?signed\s+)?long\s+long\s+int}, + qr{(?:(?:un)?signed\s+)?long\s+long}, + qr{(?:(?:un)?signed\s+)?long}, + qr{(?:un)?signed}, + qr{float}, + qr{double}, + qr{bool}, + qr{struct\s+$Ident}, + qr{union\s+$Ident}, + qr{enum\s+$Ident}, + qr{${Ident}_t}, + qr{${Ident}_handler}, + qr{${Ident}_handler_fn}, + @typeListMisordered, +); + +our $C90_int_types = qr{(?x: + long\s+long\s+int\s+(?:un)?signed| + long\s+long\s+(?:un)?signed\s+int| + long\s+long\s+(?:un)?signed| + (?:(?:un)?signed\s+)?long\s+long\s+int| + (?:(?:un)?signed\s+)?long\s+long| + int\s+long\s+long\s+(?:un)?signed| + int\s+(?:(?:un)?signed\s+)?long\s+long| + + long\s+int\s+(?:un)?signed| + long\s+(?:un)?signed\s+int| + long\s+(?:un)?signed| + (?:(?:un)?signed\s+)?long\s+int| + (?:(?:un)?signed\s+)?long| + int\s+long\s+(?:un)?signed| + int\s+(?:(?:un)?signed\s+)?long| + + int\s+(?:un)?signed| + (?:(?:un)?signed\s+)?int +)}; + +our @typeListFile = (); +our @typeListWithAttr = ( + @typeList, + qr{struct\s+$InitAttribute\s+$Ident}, + qr{union\s+$InitAttribute\s+$Ident}, +); + +our @modifierList = ( + qr{fastcall}, +); +our @modifierListFile = (); + +our @mode_permission_funcs = ( + ["module_param", 3], + ["module_param_(?:array|named|string)", 4], + ["module_param_array_named", 5], + ["debugfs_create_(?:file|u8|u16|u32|u64|x8|x16|x32|x64|size_t|atomic_t|bool|blob|regset32|u32_array)", 2], + ["proc_create(?:_data|)", 2], + ["(?:CLASS|DEVICE|SENSOR|SENSOR_DEVICE|IIO_DEVICE)_ATTR", 2], + ["IIO_DEV_ATTR_[A-Z_]+", 1], + ["SENSOR_(?:DEVICE_|)ATTR_2", 2], + ["SENSOR_TEMPLATE(?:_2|)", 3], + ["__ATTR", 2], +); + +my $word_pattern = '\b[A-Z]?[a-z]{2,}\b'; + +#Create a search pattern for all these functions to speed up a loop below +our $mode_perms_search = ""; +foreach my $entry (@mode_permission_funcs) { + $mode_perms_search .= '|' if ($mode_perms_search ne ""); + $mode_perms_search .= $entry->[0]; +} +$mode_perms_search = "(?:${mode_perms_search})"; + +our %deprecated_apis = ( + "synchronize_rcu_bh" => "synchronize_rcu", + "synchronize_rcu_bh_expedited" => "synchronize_rcu_expedited", + "call_rcu_bh" => "call_rcu", + "rcu_barrier_bh" => "rcu_barrier", + "synchronize_sched" => "synchronize_rcu", + "synchronize_sched_expedited" => "synchronize_rcu_expedited", + "call_rcu_sched" => "call_rcu", + "rcu_barrier_sched" => "rcu_barrier", + "get_state_synchronize_sched" => "get_state_synchronize_rcu", + "cond_synchronize_sched" => "cond_synchronize_rcu", +); + +#Create a search pattern for all these strings to speed up a loop below +our $deprecated_apis_search = ""; +foreach my $entry (keys %deprecated_apis) { + $deprecated_apis_search .= '|' if ($deprecated_apis_search ne ""); + $deprecated_apis_search .= $entry; +} +$deprecated_apis_search = "(?:${deprecated_apis_search})"; + +our $mode_perms_world_writable = qr{ + S_IWUGO | + S_IWOTH | + S_IRWXUGO | + S_IALLUGO | + 0[0-7][0-7][2367] +}x; + +our %mode_permission_string_types = ( + "S_IRWXU" => 0700, + "S_IRUSR" => 0400, + "S_IWUSR" => 0200, + "S_IXUSR" => 0100, + "S_IRWXG" => 0070, + "S_IRGRP" => 0040, + "S_IWGRP" => 0020, + "S_IXGRP" => 0010, + "S_IRWXO" => 0007, + "S_IROTH" => 0004, + "S_IWOTH" => 0002, + "S_IXOTH" => 0001, + "S_IRWXUGO" => 0777, + "S_IRUGO" => 0444, + "S_IWUGO" => 0222, + "S_IXUGO" => 0111, +); + +#Create a search pattern for all these strings to speed up a loop below +our $mode_perms_string_search = ""; +foreach my $entry (keys %mode_permission_string_types) { + $mode_perms_string_search .= '|' if ($mode_perms_string_search ne ""); + $mode_perms_string_search .= $entry; +} +our $single_mode_perms_string_search = "(?:${mode_perms_string_search})"; +our $multi_mode_perms_string_search = qr{ + ${single_mode_perms_string_search} + (?:\s*\|\s*${single_mode_perms_string_search})* +}x; + +sub perms_to_octal { + my ($string) = @_; + + return trim($string) if ($string =~ /^\s*0[0-7]{3,3}\s*$/); + + my $val = ""; + my $oval = ""; + my $to = 0; + my $curpos = 0; + my $lastpos = 0; + while ($string =~ /\b(($single_mode_perms_string_search)\b(?:\s*\|\s*)?\s*)/g) { + $curpos = pos($string); + my $match = $2; + my $omatch = $1; + last if ($lastpos > 0 && ($curpos - length($omatch) != $lastpos)); + $lastpos = $curpos; + $to |= $mode_permission_string_types{$match}; + $val .= '\s*\|\s*' if ($val ne ""); + $val .= $match; + $oval .= $omatch; + } + $oval =~ s/^\s*\|\s*//; + $oval =~ s/\s*\|\s*$//; + return sprintf("%04o", $to); +} + +our $allowed_asm_includes = qr{(?x: + irq| + memory| + time| + reboot +)}; +# memory.h: ARM has a custom one + +# Load common spelling mistakes and build regular expression list. +my $misspellings; +my %spelling_fix; + +if (open(my $spelling, '<', $spelling_file)) { + while (<$spelling>) { + my $line = $_; + + $line =~ s/\s*\n?$//g; + $line =~ s/^\s*//g; + + next if ($line =~ m/^\s*#/); + next if ($line =~ m/^\s*$/); + + my ($suspect, $fix) = split(/\|\|/, $line); + + $spelling_fix{$suspect} = $fix; + } + close($spelling); +} else { + warn "No typos will be found - file '$spelling_file': $!\n"; +} + +if ($codespell) { + if (open(my $spelling, '<', $codespellfile)) { + while (<$spelling>) { + my $line = $_; + + $line =~ s/\s*\n?$//g; + $line =~ s/^\s*//g; + + next if ($line =~ m/^\s*#/); + next if ($line =~ m/^\s*$/); + next if ($line =~ m/, disabled/i); + + $line =~ s/,.*$//; + + my ($suspect, $fix) = split(/->/, $line); + + $spelling_fix{$suspect} = $fix; + } + close($spelling); + } else { + warn "No codespell typos will be found - file '$codespellfile': $!\n"; + } +} + +$misspellings = join("|", sort keys %spelling_fix) if keys %spelling_fix; + +sub read_words { + my ($wordsRef, $file) = @_; + + if (open(my $words, '<', $file)) { + while (<$words>) { + my $line = $_; + + $line =~ s/\s*\n?$//g; + $line =~ s/^\s*//g; + + next if ($line =~ m/^\s*#/); + next if ($line =~ m/^\s*$/); + if ($line =~ /\s/) { + print("$file: '$line' invalid - ignored\n"); + next; + } + + $$wordsRef .= '|' if (defined $$wordsRef); + $$wordsRef .= $line; + } + close($file); + return 1; + } + + return 0; +} + +my $const_structs; +if (show_type("CONST_STRUCT")) { + read_words(\$const_structs, $conststructsfile) + or warn "No structs that should be const will be found - file '$conststructsfile': $!\n"; +} + +if (defined($typedefsfile)) { + my $typeOtherTypedefs; + read_words(\$typeOtherTypedefs, $typedefsfile) + or warn "No additional types will be considered - file '$typedefsfile': $!\n"; + $typeTypedefs .= '|' . $typeOtherTypedefs if (defined $typeOtherTypedefs); +} + +sub build_types { + my $mods = "(?x: \n" . join("|\n ", (@modifierList, @modifierListFile)) . "\n)"; + my $all = "(?x: \n" . join("|\n ", (@typeList, @typeListFile)) . "\n)"; + my $Misordered = "(?x: \n" . join("|\n ", @typeListMisordered) . "\n)"; + my $allWithAttr = "(?x: \n" . join("|\n ", @typeListWithAttr) . "\n)"; + $Modifier = qr{(?:$Attribute|$Sparse|$mods)}; + $BasicType = qr{ + (?:$typeTypedefs\b)| + (?:${all}\b) + }x; + $NonptrType = qr{ + (?:$Modifier\s+|const\s+)* + (?: + (?:typeof|__typeof__)\s*\([^\)]*\)| + (?:$typeTypedefs\b)| + (?:${all}\b) + ) + (?:\s+$Modifier|\s+const)* + }x; + $NonptrTypeMisordered = qr{ + (?:$Modifier\s+|const\s+)* + (?: + (?:${Misordered}\b) + ) + (?:\s+$Modifier|\s+const)* + }x; + $NonptrTypeWithAttr = qr{ + (?:$Modifier\s+|const\s+)* + (?: + (?:typeof|__typeof__)\s*\([^\)]*\)| + (?:$typeTypedefs\b)| + (?:${allWithAttr}\b) + ) + (?:\s+$Modifier|\s+const)* + }x; + $Type = qr{ + $NonptrType + (?:(?:\s|\*|\[\])+\s*const|(?:\s|\*\s*(?:const\s*)?|\[\])+|(?:\s*\[\s*\])+){0,4} + (?:\s+$Inline|\s+$Modifier)* + }x; + $TypeMisordered = qr{ + $NonptrTypeMisordered + (?:(?:\s|\*|\[\])+\s*const|(?:\s|\*\s*(?:const\s*)?|\[\])+|(?:\s*\[\s*\])+){0,4} + (?:\s+$Inline|\s+$Modifier)* + }x; + $Declare = qr{(?:$Storage\s+(?:$Inline\s+)?)?$Type}; + $DeclareMisordered = qr{(?:$Storage\s+(?:$Inline\s+)?)?$TypeMisordered}; +} +build_types(); + +our $Typecast = qr{\s*(\(\s*$NonptrType\s*\)){0,1}\s*}; + +# Using $balanced_parens, $LvalOrFunc, or $FuncArg +# requires at least perl version v5.10.0 +# Any use must be runtime checked with $^V + +our $balanced_parens = qr/(\((?:[^\(\)]++|(?-1))*\))/; +our $LvalOrFunc = qr{((?:[\&\*]\s*)?$Lval)\s*($balanced_parens{0,1})\s*}; +our $FuncArg = qr{$Typecast{0,1}($LvalOrFunc|$Constant|$String)}; + +our $declaration_macros = qr{(?x: + (?:$Storage\s+)?(?:[A-Z_][A-Z0-9]*_){0,2}(?:DEFINE|DECLARE)(?:_[A-Z0-9]+){1,6}\s*\(| + (?:$Storage\s+)?[HLP]?LIST_HEAD\s*\(| + (?:SKCIPHER_REQUEST|SHASH_DESC|AHASH_REQUEST)_ON_STACK\s*\( +)}; + +sub deparenthesize { + my ($string) = @_; + return "" if (!defined($string)); + + while ($string =~ /^\s*\(.*\)\s*$/) { + $string =~ s@^\s*\(\s*@@; + $string =~ s@\s*\)\s*$@@; + } + + $string =~ s@\s+@ @g; + + return $string; +} + +sub seed_camelcase_file { + my ($file) = @_; + + return if (!(-f $file)); + + local $/; + + open(my $include_file, '<', "$file") + or warn "$P: Can't read '$file' $!\n"; + my $text = <$include_file>; + close($include_file); + + my @lines = split('\n', $text); + + foreach my $line (@lines) { + next if ($line !~ /(?:[A-Z][a-z]|[a-z][A-Z])/); + if ($line =~ /^[ \t]*(?:#[ \t]*define|typedef\s+$Type)\s+(\w*(?:[A-Z][a-z]|[a-z][A-Z])\w*)/) { + $camelcase{$1} = 1; + } elsif ($line =~ /^\s*$Declare\s+(\w*(?:[A-Z][a-z]|[a-z][A-Z])\w*)\s*[\(\[,;]/) { + $camelcase{$1} = 1; + } elsif ($line =~ /^\s*(?:union|struct|enum)\s+(\w*(?:[A-Z][a-z]|[a-z][A-Z])\w*)\s*[;\{]/) { + $camelcase{$1} = 1; + } + } +} + +our %maintained_status = (); + +sub is_maintained_obsolete { + my ($filename) = @_; + + return 0 if (!$tree || !(-e "$root/scripts/get_maintainer.pl")); + + if (!exists($maintained_status{$filename})) { + $maintained_status{$filename} = `perl $root/scripts/get_maintainer.pl --status --nom --nol --nogit --nogit-fallback -f $filename 2>&1`; + } + + return $maintained_status{$filename} =~ /obsolete/i; +} + +sub is_SPDX_License_valid { + my ($license) = @_; + + return 1 if (!$tree || which("python") eq "" || !(-e "$root/scripts/spdxcheck.py") || !(-e "$gitroot")); + + my $root_path = abs_path($root); + my $status = `cd "$root_path"; echo "$license" | python scripts/spdxcheck.py -`; + return 0 if ($status ne ""); + return 1; +} + +my $camelcase_seeded = 0; +sub seed_camelcase_includes { + return if ($camelcase_seeded); + + my $files; + my $camelcase_cache = ""; + my @include_files = (); + + $camelcase_seeded = 1; + + if (-e "$gitroot") { + my $git_last_include_commit = `${git_command} log --no-merges --pretty=format:"%h%n" -1 -- include`; + chomp $git_last_include_commit; + $camelcase_cache = ".checkpatch-camelcase.git.$git_last_include_commit"; + } else { + my $last_mod_date = 0; + $files = `find $root/include -name "*.h"`; + @include_files = split('\n', $files); + foreach my $file (@include_files) { + my $date = POSIX::strftime("%Y%m%d%H%M", + localtime((stat $file)[9])); + $last_mod_date = $date if ($last_mod_date < $date); + } + $camelcase_cache = ".checkpatch-camelcase.date.$last_mod_date"; + } + + if ($camelcase_cache ne "" && -f $camelcase_cache) { + open(my $camelcase_file, '<', "$camelcase_cache") + or warn "$P: Can't read '$camelcase_cache' $!\n"; + while (<$camelcase_file>) { + chomp; + $camelcase{$_} = 1; + } + close($camelcase_file); + + return; + } + + if (-e "$gitroot") { + $files = `${git_command} ls-files "include/*.h"`; + @include_files = split('\n', $files); + } + + foreach my $file (@include_files) { + seed_camelcase_file($file); + } + + if ($camelcase_cache ne "") { + unlink glob ".checkpatch-camelcase.*"; + open(my $camelcase_file, '>', "$camelcase_cache") + or warn "$P: Can't write '$camelcase_cache' $!\n"; + foreach (sort { lc($a) cmp lc($b) } keys(%camelcase)) { + print $camelcase_file ("$_\n"); + } + close($camelcase_file); + } +} + +sub git_is_single_file { + my ($filename) = @_; + + return 0 if ((which("git") eq "") || !(-e "$gitroot")); + + my $output = `${git_command} ls-files -- $filename 2>/dev/null`; + my $count = $output =~ tr/\n//; + return $count eq 1 && $output =~ m{^${filename}$}; +} + +sub git_commit_info { + my ($commit, $id, $desc) = @_; + + return ($id, $desc) if ((which("git") eq "") || !(-e "$gitroot")); + + my $output = `${git_command} log --no-color --format='%H %s' -1 $commit 2>&1`; + $output =~ s/^\s*//gm; + my @lines = split("\n", $output); + + return ($id, $desc) if ($#lines < 0); + + if ($lines[0] =~ /^error: short SHA1 $commit is ambiguous/) { +# Maybe one day convert this block of bash into something that returns +# all matching commit ids, but it's very slow... +# +# echo "checking commits $1..." +# git rev-list --remotes | grep -i "^$1" | +# while read line ; do +# git log --format='%H %s' -1 $line | +# echo "commit $(cut -c 1-12,41-)" +# done + } elsif ($lines[0] =~ /^fatal: ambiguous argument '$commit': unknown revision or path not in the working tree\./) { + $id = undef; + } else { + $id = substr($lines[0], 0, 12); + $desc = substr($lines[0], 41); + } + + return ($id, $desc); +} + +$chk_signoff = 0 if ($file); + +my @rawlines = (); +my @lines = (); +my @fixed = (); +my @fixed_inserted = (); +my @fixed_deleted = (); +my $fixlinenr = -1; + +# If input is git commits, extract all commits from the commit expressions. +# For example, HEAD-3 means we need check 'HEAD, HEAD~1, HEAD~2'. +die "$P: No git repository found\n" if ($git && !-e "$gitroot"); + +if ($git) { + my @commits = (); + foreach my $commit_expr (@ARGV) { + my $git_range; + if ($commit_expr =~ m/^(.*)-(\d+)$/) { + $git_range = "-$2 $1"; + } elsif ($commit_expr =~ m/\.\./) { + $git_range = "$commit_expr"; + } else { + $git_range = "-1 $commit_expr"; + } + my $lines = `${git_command} log --no-color --no-merges --pretty=format:'%H %s' $git_range`; + foreach my $line (split(/\n/, $lines)) { + $line =~ /^([0-9a-fA-F]{40,40}) (.*)$/; + next if (!defined($1) || !defined($2)); + my $sha1 = $1; + my $subject = $2; + unshift(@commits, $sha1); + $git_commits{$sha1} = $subject; + } + } + die "$P: no git commits after extraction!\n" if (@commits == 0); + @ARGV = @commits; +} + +my $vname; +$allow_c99_comments = !defined $ignore_type{"C99_COMMENT_TOLERANCE"}; +for my $filename (@ARGV) { + my $FILE; + my $is_git_file = git_is_single_file($filename); + my $oldfile = $file; + $file = 1 if ($is_git_file); + if ($git) { + open($FILE, '-|', "git format-patch -M --stdout -1 $filename") || + die "$P: $filename: git format-patch failed - $!\n"; + } elsif ($file) { + open($FILE, '-|', "diff -u /dev/null $filename") || + die "$P: $filename: diff failed - $!\n"; + } elsif ($filename eq '-') { + open($FILE, '<&STDIN'); + } else { + open($FILE, '<', "$filename") || + die "$P: $filename: open failed - $!\n"; + } + if ($filename eq '-') { + $vname = 'Your patch'; + } elsif ($git) { + $vname = "Commit " . substr($filename, 0, 12) . ' ("' . $git_commits{$filename} . '")'; + } else { + $vname = $filename; + } + while (<$FILE>) { + chomp; + push(@rawlines, $_); + $vname = qq("$1") if ($filename eq '-' && $_ =~ m/^Subject:\s+(.+)/i); + } + close($FILE); + + if ($#ARGV > 0 && $quiet == 0) { + print '-' x length($vname) . "\n"; + print "$vname\n"; + print '-' x length($vname) . "\n"; + } + + if (!process($filename)) { + $exit = 1; + } + @rawlines = (); + @lines = (); + @fixed = (); + @fixed_inserted = (); + @fixed_deleted = (); + $fixlinenr = -1; + @modifierListFile = (); + @typeListFile = (); + build_types(); + $file = $oldfile if ($is_git_file); +} + +if (!$quiet) { + hash_show_words(\%use_type, "Used"); + hash_show_words(\%ignore_type, "Ignored"); + + if (!$perl_version_ok) { + print << "EOM" + +NOTE: perl $^V is not modern enough to detect all possible issues. + An upgrade to at least perl $minimum_perl_version is suggested. +EOM + } + if ($exit) { + print << "EOM" + +NOTE: If any of the errors are false positives, please report + them to the maintainer, see CHECKPATCH in MAINTAINERS. +EOM + } +} + +exit($exit); + +sub top_of_kernel_tree { + my ($root) = @_; + + my @tree_check = ( + "COPYING", "CREDITS", "Kbuild", "MAINTAINERS", "Makefile", + "README", "Documentation", "arch", "include", "drivers", + "fs", "init", "ipc", "kernel", "lib", "scripts", + ); + + foreach my $check (@tree_check) { + if (! -e $root . '/' . $check) { + return 0; + } + } + return 1; +} + +sub parse_email { + my ($formatted_email) = @_; + + my $name = ""; + my $name_comment = ""; + my $address = ""; + my $comment = ""; + + if ($formatted_email =~ /^(.*)<(\S+\@\S+)>(.*)$/) { + $name = $1; + $address = $2; + $comment = $3 if defined $3; + } elsif ($formatted_email =~ /^\s*<(\S+\@\S+)>(.*)$/) { + $address = $1; + $comment = $2 if defined $2; + } elsif ($formatted_email =~ /(\S+\@\S+)(.*)$/) { + $address = $1; + $comment = $2 if defined $2; + $formatted_email =~ s/\Q$address\E.*$//; + $name = $formatted_email; + $name = trim($name); + $name =~ s/^\"|\"$//g; + # If there's a name left after stripping spaces and + # leading quotes, and the address doesn't have both + # leading and trailing angle brackets, the address + # is invalid. ie: + # "joe smith joe@smith.com" bad + # "joe smith ]+>$/) { + $name = ""; + $address = ""; + $comment = ""; + } + } + + $comment = trim($comment); + $name = trim($name); + $name =~ s/^\"|\"$//g; + if ($name =~ s/(\s*\([^\)]+\))\s*//) { + $name_comment = trim($1); + } + $address = trim($address); + $address =~ s/^\<|\>$//g; + + if ($name =~ /[^\w \-]/i) { ##has "must quote" chars + $name =~ s/(?"; + } + $formatted_email .= "$comment"; + return $formatted_email; +} + +sub reformat_email { + my ($email) = @_; + + my ($email_name, $name_comment, $email_address, $comment) = parse_email($email); + return format_email($email_name, $name_comment, $email_address, $comment); +} + +sub same_email_addresses { + my ($email1, $email2, $match_comment) = @_; + + my ($email1_name, $name1_comment, $email1_address, $comment1) = parse_email($email1); + my ($email2_name, $name2_comment, $email2_address, $comment2) = parse_email($email2); + + if ($match_comment != 1) { + return $email1_name eq $email2_name && + $email1_address eq $email2_address; + } + return $email1_name eq $email2_name && + $email1_address eq $email2_address && + $name1_comment eq $name2_comment && + $comment1 eq $comment2; +} + +sub which { + my ($bin) = @_; + + foreach my $path (split(/:/, $ENV{PATH})) { + if (-e "$path/$bin") { + return "$path/$bin"; + } + } + + return ""; +} + +sub which_conf { + my ($conf) = @_; + + foreach my $path (split(/:/, ".:$ENV{HOME}:.scripts")) { + if (-e "$path/$conf") { + return "$path/$conf"; + } + } + + return ""; +} + +sub expand_tabs { + my ($str) = @_; + + my $res = ''; + my $n = 0; + for my $c (split(//, $str)) { + if ($c eq "\t") { + $res .= ' '; + $n++; + for (; ($n % $tabsize) != 0; $n++) { + $res .= ' '; + } + next; + } + $res .= $c; + $n++; + } + + return $res; +} +sub copy_spacing { + (my $res = shift) =~ tr/\t/ /c; + return $res; +} + +sub line_stats { + my ($line) = @_; + + # Drop the diff line leader and expand tabs + $line =~ s/^.//; + $line = expand_tabs($line); + + # Pick the indent from the front of the line. + my ($white) = ($line =~ /^(\s*)/); + + return (length($line), length($white)); +} + +my $sanitise_quote = ''; + +sub sanitise_line_reset { + my ($in_comment) = @_; + + if ($in_comment) { + $sanitise_quote = '*/'; + } else { + $sanitise_quote = ''; + } +} +sub sanitise_line { + my ($line) = @_; + + my $res = ''; + my $l = ''; + + my $qlen = 0; + my $off = 0; + my $c; + + # Always copy over the diff marker. + $res = substr($line, 0, 1); + + for ($off = 1; $off < length($line); $off++) { + $c = substr($line, $off, 1); + + # Comments we are whacking completely including the begin + # and end, all to $;. + if ($sanitise_quote eq '' && substr($line, $off, 2) eq '/*') { + $sanitise_quote = '*/'; + + substr($res, $off, 2, "$;$;"); + $off++; + next; + } + if ($sanitise_quote eq '*/' && substr($line, $off, 2) eq '*/') { + $sanitise_quote = ''; + substr($res, $off, 2, "$;$;"); + $off++; + next; + } + if ($sanitise_quote eq '' && substr($line, $off, 2) eq '//') { + $sanitise_quote = '//'; + + substr($res, $off, 2, $sanitise_quote); + $off++; + next; + } + + # A \ in a string means ignore the next character. + if (($sanitise_quote eq "'" || $sanitise_quote eq '"') && + $c eq "\\") { + substr($res, $off, 2, 'XX'); + $off++; + next; + } + # Regular quotes. + if ($c eq "'" || $c eq '"') { + if ($sanitise_quote eq '') { + $sanitise_quote = $c; + + substr($res, $off, 1, $c); + next; + } elsif ($sanitise_quote eq $c) { + $sanitise_quote = ''; + } + } + + #print "c<$c> SQ<$sanitise_quote>\n"; + if ($off != 0 && $sanitise_quote eq '*/' && $c ne "\t") { + substr($res, $off, 1, $;); + } elsif ($off != 0 && $sanitise_quote eq '//' && $c ne "\t") { + substr($res, $off, 1, $;); + } elsif ($off != 0 && $sanitise_quote && $c ne "\t") { + substr($res, $off, 1, 'X'); + } else { + substr($res, $off, 1, $c); + } + } + + if ($sanitise_quote eq '//') { + $sanitise_quote = ''; + } + + # The pathname on a #include may be surrounded by '<' and '>'. + if ($res =~ /^.\s*\#\s*include\s+\<(.*)\>/) { + my $clean = 'X' x length($1); + $res =~ s@\<.*\>@<$clean>@; + + # The whole of a #error is a string. + } elsif ($res =~ /^.\s*\#\s*(?:error|warning)\s+(.*)\b/) { + my $clean = 'X' x length($1); + $res =~ s@(\#\s*(?:error|warning)\s+).*@$1$clean@; + } + + if ($allow_c99_comments && $res =~ m@(//.*$)@) { + my $match = $1; + $res =~ s/\Q$match\E/"$;" x length($match)/e; + } + + return $res; +} + +sub get_quoted_string { + my ($line, $rawline) = @_; + + return "" if (!defined($line) || !defined($rawline)); + return "" if ($line !~ m/($String)/g); + return substr($rawline, $-[0], $+[0] - $-[0]); +} + +sub ctx_statement_block { + my ($linenr, $remain, $off) = @_; + my $line = $linenr - 1; + my $blk = ''; + my $soff = $off; + my $coff = $off - 1; + my $coff_set = 0; + + my $loff = 0; + + my $type = ''; + my $level = 0; + my @stack = (); + my $p; + my $c; + my $len = 0; + + my $remainder; + while (1) { + @stack = (['', 0]) if ($#stack == -1); + + #warn "CSB: blk<$blk> remain<$remain>\n"; + # If we are about to drop off the end, pull in more + # context. + if ($off >= $len) { + for (; $remain > 0; $line++) { + last if (!defined $lines[$line]); + next if ($lines[$line] =~ /^-/); + $remain--; + $loff = $len; + $blk .= $lines[$line] . "\n"; + $len = length($blk); + $line++; + last; + } + # Bail if there is no further context. + #warn "CSB: blk<$blk> off<$off> len<$len>\n"; + if ($off >= $len) { + last; + } + if ($level == 0 && substr($blk, $off) =~ /^.\s*#\s*define/) { + $level++; + $type = '#'; + } + } + $p = $c; + $c = substr($blk, $off, 1); + $remainder = substr($blk, $off); + + #warn "CSB: c<$c> type<$type> level<$level> remainder<$remainder> coff_set<$coff_set>\n"; + + # Handle nested #if/#else. + if ($remainder =~ /^#\s*(?:ifndef|ifdef|if)\s/) { + push(@stack, [ $type, $level ]); + } elsif ($remainder =~ /^#\s*(?:else|elif)\b/) { + ($type, $level) = @{$stack[$#stack - 1]}; + } elsif ($remainder =~ /^#\s*endif\b/) { + ($type, $level) = @{pop(@stack)}; + } + + # Statement ends at the ';' or a close '}' at the + # outermost level. + if ($level == 0 && $c eq ';') { + last; + } + + # An else is really a conditional as long as its not else if + if ($level == 0 && $coff_set == 0 && + (!defined($p) || $p =~ /(?:\s|\}|\+)/) && + $remainder =~ /^(else)(?:\s|{)/ && + $remainder !~ /^else\s+if\b/) { + $coff = $off + length($1) - 1; + $coff_set = 1; + #warn "CSB: mark coff<$coff> soff<$soff> 1<$1>\n"; + #warn "[" . substr($blk, $soff, $coff - $soff + 1) . "]\n"; + } + + if (($type eq '' || $type eq '(') && $c eq '(') { + $level++; + $type = '('; + } + if ($type eq '(' && $c eq ')') { + $level--; + $type = ($level != 0)? '(' : ''; + + if ($level == 0 && $coff < $soff) { + $coff = $off; + $coff_set = 1; + #warn "CSB: mark coff<$coff>\n"; + } + } + if (($type eq '' || $type eq '{') && $c eq '{') { + $level++; + $type = '{'; + } + if ($type eq '{' && $c eq '}') { + $level--; + $type = ($level != 0)? '{' : ''; + + if ($level == 0) { + if (substr($blk, $off + 1, 1) eq ';') { + $off++; + } + last; + } + } + # Preprocessor commands end at the newline unless escaped. + if ($type eq '#' && $c eq "\n" && $p ne "\\") { + $level--; + $type = ''; + $off++; + last; + } + $off++; + } + # We are truly at the end, so shuffle to the next line. + if ($off == $len) { + $loff = $len + 1; + $line++; + $remain--; + } + + my $statement = substr($blk, $soff, $off - $soff + 1); + my $condition = substr($blk, $soff, $coff - $soff + 1); + + #warn "STATEMENT<$statement>\n"; + #warn "CONDITION<$condition>\n"; + + #print "coff<$coff> soff<$off> loff<$loff>\n"; + + return ($statement, $condition, + $line, $remain + 1, $off - $loff + 1, $level); +} + +sub statement_lines { + my ($stmt) = @_; + + # Strip the diff line prefixes and rip blank lines at start and end. + $stmt =~ s/(^|\n)./$1/g; + $stmt =~ s/^\s*//; + $stmt =~ s/\s*$//; + + my @stmt_lines = ($stmt =~ /\n/g); + + return $#stmt_lines + 2; +} + +sub statement_rawlines { + my ($stmt) = @_; + + my @stmt_lines = ($stmt =~ /\n/g); + + return $#stmt_lines + 2; +} + +sub statement_block_size { + my ($stmt) = @_; + + $stmt =~ s/(^|\n)./$1/g; + $stmt =~ s/^\s*{//; + $stmt =~ s/}\s*$//; + $stmt =~ s/^\s*//; + $stmt =~ s/\s*$//; + + my @stmt_lines = ($stmt =~ /\n/g); + my @stmt_statements = ($stmt =~ /;/g); + + my $stmt_lines = $#stmt_lines + 2; + my $stmt_statements = $#stmt_statements + 1; + + if ($stmt_lines > $stmt_statements) { + return $stmt_lines; + } else { + return $stmt_statements; + } +} + +sub ctx_statement_full { + my ($linenr, $remain, $off) = @_; + my ($statement, $condition, $level); + + my (@chunks); + + # Grab the first conditional/block pair. + ($statement, $condition, $linenr, $remain, $off, $level) = + ctx_statement_block($linenr, $remain, $off); + #print "F: c<$condition> s<$statement> remain<$remain>\n"; + push(@chunks, [ $condition, $statement ]); + if (!($remain > 0 && $condition =~ /^\s*(?:\n[+-])?\s*(?:if|else|do)\b/s)) { + return ($level, $linenr, @chunks); + } + + # Pull in the following conditional/block pairs and see if they + # could continue the statement. + for (;;) { + ($statement, $condition, $linenr, $remain, $off, $level) = + ctx_statement_block($linenr, $remain, $off); + #print "C: c<$condition> s<$statement> remain<$remain>\n"; + last if (!($remain > 0 && $condition =~ /^(?:\s*\n[+-])*\s*(?:else|do)\b/s)); + #print "C: push\n"; + push(@chunks, [ $condition, $statement ]); + } + + return ($level, $linenr, @chunks); +} + +sub ctx_block_get { + my ($linenr, $remain, $outer, $open, $close, $off) = @_; + my $line; + my $start = $linenr - 1; + my $blk = ''; + my @o; + my @c; + my @res = (); + + my $level = 0; + my @stack = ($level); + for ($line = $start; $remain > 0; $line++) { + next if ($rawlines[$line] =~ /^-/); + $remain--; + + $blk .= $rawlines[$line]; + + # Handle nested #if/#else. + if ($lines[$line] =~ /^.\s*#\s*(?:ifndef|ifdef|if)\s/) { + push(@stack, $level); + } elsif ($lines[$line] =~ /^.\s*#\s*(?:else|elif)\b/) { + $level = $stack[$#stack - 1]; + } elsif ($lines[$line] =~ /^.\s*#\s*endif\b/) { + $level = pop(@stack); + } + + foreach my $c (split(//, $lines[$line])) { + ##print "C<$c>L<$level><$open$close>O<$off>\n"; + if ($off > 0) { + $off--; + next; + } + + if ($c eq $close && $level > 0) { + $level--; + last if ($level == 0); + } elsif ($c eq $open) { + $level++; + } + } + + if (!$outer || $level <= 1) { + push(@res, $rawlines[$line]); + } + + last if ($level == 0); + } + + return ($level, @res); +} +sub ctx_block_outer { + my ($linenr, $remain) = @_; + + my ($level, @r) = ctx_block_get($linenr, $remain, 1, '{', '}', 0); + return @r; +} +sub ctx_block { + my ($linenr, $remain) = @_; + + my ($level, @r) = ctx_block_get($linenr, $remain, 0, '{', '}', 0); + return @r; +} +sub ctx_statement { + my ($linenr, $remain, $off) = @_; + + my ($level, @r) = ctx_block_get($linenr, $remain, 0, '(', ')', $off); + return @r; +} +sub ctx_block_level { + my ($linenr, $remain) = @_; + + return ctx_block_get($linenr, $remain, 0, '{', '}', 0); +} +sub ctx_statement_level { + my ($linenr, $remain, $off) = @_; + + return ctx_block_get($linenr, $remain, 0, '(', ')', $off); +} + +sub ctx_locate_comment { + my ($first_line, $end_line) = @_; + + # If c99 comment on the current line, or the line before or after + my ($current_comment) = ($rawlines[$end_line - 1] =~ m@^\+.*(//.*$)@); + return $current_comment if (defined $current_comment); + ($current_comment) = ($rawlines[$end_line - 2] =~ m@^[\+ ].*(//.*$)@); + return $current_comment if (defined $current_comment); + ($current_comment) = ($rawlines[$end_line] =~ m@^[\+ ].*(//.*$)@); + return $current_comment if (defined $current_comment); + + # Catch a comment on the end of the line itself. + ($current_comment) = ($rawlines[$end_line - 1] =~ m@.*(/\*.*\*/)\s*(?:\\\s*)?$@); + return $current_comment if (defined $current_comment); + + # Look through the context and try and figure out if there is a + # comment. + my $in_comment = 0; + $current_comment = ''; + for (my $linenr = $first_line; $linenr < $end_line; $linenr++) { + my $line = $rawlines[$linenr - 1]; + #warn " $line\n"; + if ($linenr == $first_line and $line =~ m@^.\s*\*@) { + $in_comment = 1; + } + if ($line =~ m@/\*@) { + $in_comment = 1; + } + if (!$in_comment && $current_comment ne '') { + $current_comment = ''; + } + $current_comment .= $line . "\n" if ($in_comment); + if ($line =~ m@\*/@) { + $in_comment = 0; + } + } + + chomp($current_comment); + return($current_comment); +} +sub ctx_has_comment { + my ($first_line, $end_line) = @_; + my $cmt = ctx_locate_comment($first_line, $end_line); + + ##print "LINE: $rawlines[$end_line - 1 ]\n"; + ##print "CMMT: $cmt\n"; + + return ($cmt ne ''); +} + +sub raw_line { + my ($linenr, $cnt) = @_; + + my $offset = $linenr - 1; + $cnt++; + + my $line; + while ($cnt) { + $line = $rawlines[$offset++]; + next if (defined($line) && $line =~ /^-/); + $cnt--; + } + + return $line; +} + +sub get_stat_real { + my ($linenr, $lc) = @_; + + my $stat_real = raw_line($linenr, 0); + for (my $count = $linenr + 1; $count <= $lc; $count++) { + $stat_real = $stat_real . "\n" . raw_line($count, 0); + } + + return $stat_real; +} + +sub get_stat_here { + my ($linenr, $cnt, $here) = @_; + + my $herectx = $here . "\n"; + for (my $n = 0; $n < $cnt; $n++) { + $herectx .= raw_line($linenr, $n) . "\n"; + } + + return $herectx; +} + +sub cat_vet { + my ($vet) = @_; + my ($res, $coded); + + $res = ''; + while ($vet =~ /([^[:cntrl:]]*)([[:cntrl:]]|$)/g) { + $res .= $1; + if ($2 ne '') { + $coded = sprintf("^%c", unpack('C', $2) + 64); + $res .= $coded; + } + } + $res =~ s/$/\$/; + + return $res; +} + +my $av_preprocessor = 0; +my $av_pending; +my @av_paren_type; +my $av_pend_colon; + +sub annotate_reset { + $av_preprocessor = 0; + $av_pending = '_'; + @av_paren_type = ('E'); + $av_pend_colon = 'O'; +} + +sub annotate_values { + my ($stream, $type) = @_; + + my $res; + my $var = '_' x length($stream); + my $cur = $stream; + + print "$stream\n" if ($dbg_values > 1); + + while (length($cur)) { + @av_paren_type = ('E') if ($#av_paren_type < 0); + print " <" . join('', @av_paren_type) . + "> <$type> <$av_pending>" if ($dbg_values > 1); + if ($cur =~ /^(\s+)/o) { + print "WS($1)\n" if ($dbg_values > 1); + if ($1 =~ /\n/ && $av_preprocessor) { + $type = pop(@av_paren_type); + $av_preprocessor = 0; + } + + } elsif ($cur =~ /^(\(\s*$Type\s*)\)/ && $av_pending eq '_') { + print "CAST($1)\n" if ($dbg_values > 1); + push(@av_paren_type, $type); + $type = 'c'; + + } elsif ($cur =~ /^($Type)\s*(?:$Ident|,|\)|\(|\s*$)/) { + print "DECLARE($1)\n" if ($dbg_values > 1); + $type = 'T'; + + } elsif ($cur =~ /^($Modifier)\s*/) { + print "MODIFIER($1)\n" if ($dbg_values > 1); + $type = 'T'; + + } elsif ($cur =~ /^(\#\s*define\s*$Ident)(\(?)/o) { + print "DEFINE($1,$2)\n" if ($dbg_values > 1); + $av_preprocessor = 1; + push(@av_paren_type, $type); + if ($2 ne '') { + $av_pending = 'N'; + } + $type = 'E'; + + } elsif ($cur =~ /^(\#\s*(?:undef\s*$Ident|include\b))/o) { + print "UNDEF($1)\n" if ($dbg_values > 1); + $av_preprocessor = 1; + push(@av_paren_type, $type); + + } elsif ($cur =~ /^(\#\s*(?:ifdef|ifndef|if))/o) { + print "PRE_START($1)\n" if ($dbg_values > 1); + $av_preprocessor = 1; + + push(@av_paren_type, $type); + push(@av_paren_type, $type); + $type = 'E'; + + } elsif ($cur =~ /^(\#\s*(?:else|elif))/o) { + print "PRE_RESTART($1)\n" if ($dbg_values > 1); + $av_preprocessor = 1; + + push(@av_paren_type, $av_paren_type[$#av_paren_type]); + + $type = 'E'; + + } elsif ($cur =~ /^(\#\s*(?:endif))/o) { + print "PRE_END($1)\n" if ($dbg_values > 1); + + $av_preprocessor = 1; + + # Assume all arms of the conditional end as this + # one does, and continue as if the #endif was not here. + pop(@av_paren_type); + push(@av_paren_type, $type); + $type = 'E'; + + } elsif ($cur =~ /^(\\\n)/o) { + print "PRECONT($1)\n" if ($dbg_values > 1); + + } elsif ($cur =~ /^(__attribute__)\s*\(?/o) { + print "ATTR($1)\n" if ($dbg_values > 1); + $av_pending = $type; + $type = 'N'; + + } elsif ($cur =~ /^(sizeof)\s*(\()?/o) { + print "SIZEOF($1)\n" if ($dbg_values > 1); + if (defined $2) { + $av_pending = 'V'; + } + $type = 'N'; + + } elsif ($cur =~ /^(if|while|for)\b/o) { + print "COND($1)\n" if ($dbg_values > 1); + $av_pending = 'E'; + $type = 'N'; + + } elsif ($cur =~/^(case)/o) { + print "CASE($1)\n" if ($dbg_values > 1); + $av_pend_colon = 'C'; + $type = 'N'; + + } elsif ($cur =~/^(return|else|goto|typeof|__typeof__)\b/o) { + print "KEYWORD($1)\n" if ($dbg_values > 1); + $type = 'N'; + + } elsif ($cur =~ /^(\()/o) { + print "PAREN('$1')\n" if ($dbg_values > 1); + push(@av_paren_type, $av_pending); + $av_pending = '_'; + $type = 'N'; + + } elsif ($cur =~ /^(\))/o) { + my $new_type = pop(@av_paren_type); + if ($new_type ne '_') { + $type = $new_type; + print "PAREN('$1') -> $type\n" + if ($dbg_values > 1); + } else { + print "PAREN('$1')\n" if ($dbg_values > 1); + } + + } elsif ($cur =~ /^($Ident)\s*\(/o) { + print "FUNC($1)\n" if ($dbg_values > 1); + $type = 'V'; + $av_pending = 'V'; + + } elsif ($cur =~ /^($Ident\s*):(?:\s*\d+\s*(,|=|;))?/) { + if (defined $2 && $type eq 'C' || $type eq 'T') { + $av_pend_colon = 'B'; + } elsif ($type eq 'E') { + $av_pend_colon = 'L'; + } + print "IDENT_COLON($1,$type>$av_pend_colon)\n" if ($dbg_values > 1); + $type = 'V'; + + } elsif ($cur =~ /^($Ident|$Constant)/o) { + print "IDENT($1)\n" if ($dbg_values > 1); + $type = 'V'; + + } elsif ($cur =~ /^($Assignment)/o) { + print "ASSIGN($1)\n" if ($dbg_values > 1); + $type = 'N'; + + } elsif ($cur =~/^(;|{|})/) { + print "END($1)\n" if ($dbg_values > 1); + $type = 'E'; + $av_pend_colon = 'O'; + + } elsif ($cur =~/^(,)/) { + print "COMMA($1)\n" if ($dbg_values > 1); + $type = 'C'; + + } elsif ($cur =~ /^(\?)/o) { + print "QUESTION($1)\n" if ($dbg_values > 1); + $type = 'N'; + + } elsif ($cur =~ /^(:)/o) { + print "COLON($1,$av_pend_colon)\n" if ($dbg_values > 1); + + substr($var, length($res), 1, $av_pend_colon); + if ($av_pend_colon eq 'C' || $av_pend_colon eq 'L') { + $type = 'E'; + } else { + $type = 'N'; + } + $av_pend_colon = 'O'; + + } elsif ($cur =~ /^(\[)/o) { + print "CLOSE($1)\n" if ($dbg_values > 1); + $type = 'N'; + + } elsif ($cur =~ /^(-(?![->])|\+(?!\+)|\*|\&\&|\&)/o) { + my $variant; + + print "OPV($1)\n" if ($dbg_values > 1); + if ($type eq 'V') { + $variant = 'B'; + } else { + $variant = 'U'; + } + + substr($var, length($res), 1, $variant); + $type = 'N'; + + } elsif ($cur =~ /^($Operators)/o) { + print "OP($1)\n" if ($dbg_values > 1); + if ($1 ne '++' && $1 ne '--') { + $type = 'N'; + } + + } elsif ($cur =~ /(^.)/o) { + print "C($1)\n" if ($dbg_values > 1); + } + if (defined $1) { + $cur = substr($cur, length($1)); + $res .= $type x length($1); + } + } + + return ($res, $var); +} + +sub possible { + my ($possible, $line) = @_; + my $notPermitted = qr{(?: + ^(?: + $Modifier| + $Storage| + $Type| + DEFINE_\S+ + )$| + ^(?: + goto| + return| + case| + else| + asm|__asm__| + do| + \#| + \#\#| + )(?:\s|$)| + ^(?:typedef|struct|enum)\b + )}x; + warn "CHECK<$possible> ($line)\n" if ($dbg_possible > 2); + if ($possible !~ $notPermitted) { + # Check for modifiers. + $possible =~ s/\s*$Storage\s*//g; + $possible =~ s/\s*$Sparse\s*//g; + if ($possible =~ /^\s*$/) { + + } elsif ($possible =~ /\s/) { + $possible =~ s/\s*$Type\s*//g; + for my $modifier (split(' ', $possible)) { + if ($modifier !~ $notPermitted) { + warn "MODIFIER: $modifier ($possible) ($line)\n" if ($dbg_possible); + push(@modifierListFile, $modifier); + } + } + + } else { + warn "POSSIBLE: $possible ($line)\n" if ($dbg_possible); + push(@typeListFile, $possible); + } + build_types(); + } else { + warn "NOTPOSS: $possible ($line)\n" if ($dbg_possible > 1); + } +} + +my $prefix = ''; + +sub show_type { + my ($type) = @_; + + $type =~ tr/[a-z]/[A-Z]/; + + return defined $use_type{$type} if (scalar keys %use_type > 0); + + return !defined $ignore_type{$type}; +} + +sub report { + my ($level, $type, $msg) = @_; + + if (!show_type($type) || + (defined $tst_only && $msg !~ /\Q$tst_only\E/)) { + return 0; + } + my $output = ''; + if ($color) { + if ($level eq 'ERROR') { + $output .= RED; + } elsif ($level eq 'WARNING') { + $output .= YELLOW; + } else { + $output .= GREEN; + } + } + $output .= $prefix . $level . ':'; + if ($show_types) { + $output .= BLUE if ($color); + $output .= "$type:"; + } + $output .= RESET if ($color); + $output .= ' ' . $msg . "\n"; + + if ($showfile) { + my @lines = split("\n", $output, -1); + splice(@lines, 1, 1); + $output = join("\n", @lines); + } + $output = (split('\n', $output))[0] . "\n" if ($terse); + + push(our @report, $output); + + return 1; +} + +sub report_dump { + our @report; +} + +sub fixup_current_range { + my ($lineRef, $offset, $length) = @_; + + if ($$lineRef =~ /^\@\@ -\d+,\d+ \+(\d+),(\d+) \@\@/) { + my $o = $1; + my $l = $2; + my $no = $o + $offset; + my $nl = $l + $length; + $$lineRef =~ s/\+$o,$l \@\@/\+$no,$nl \@\@/; + } +} + +sub fix_inserted_deleted_lines { + my ($linesRef, $insertedRef, $deletedRef) = @_; + + my $range_last_linenr = 0; + my $delta_offset = 0; + + my $old_linenr = 0; + my $new_linenr = 0; + + my $next_insert = 0; + my $next_delete = 0; + + my @lines = (); + + my $inserted = @{$insertedRef}[$next_insert++]; + my $deleted = @{$deletedRef}[$next_delete++]; + + foreach my $old_line (@{$linesRef}) { + my $save_line = 1; + my $line = $old_line; #don't modify the array + if ($line =~ /^(?:\+\+\+|\-\-\-)\s+\S+/) { #new filename + $delta_offset = 0; + } elsif ($line =~ /^\@\@ -\d+,\d+ \+\d+,\d+ \@\@/) { #new hunk + $range_last_linenr = $new_linenr; + fixup_current_range(\$line, $delta_offset, 0); + } + + while (defined($deleted) && ${$deleted}{'LINENR'} == $old_linenr) { + $deleted = @{$deletedRef}[$next_delete++]; + $save_line = 0; + fixup_current_range(\$lines[$range_last_linenr], $delta_offset--, -1); + } + + while (defined($inserted) && ${$inserted}{'LINENR'} == $old_linenr) { + push(@lines, ${$inserted}{'LINE'}); + $inserted = @{$insertedRef}[$next_insert++]; + $new_linenr++; + fixup_current_range(\$lines[$range_last_linenr], $delta_offset++, 1); + } + + if ($save_line) { + push(@lines, $line); + $new_linenr++; + } + + $old_linenr++; + } + + return @lines; +} + +sub fix_insert_line { + my ($linenr, $line) = @_; + + my $inserted = { + LINENR => $linenr, + LINE => $line, + }; + push(@fixed_inserted, $inserted); +} + +sub fix_delete_line { + my ($linenr, $line) = @_; + + my $deleted = { + LINENR => $linenr, + LINE => $line, + }; + + push(@fixed_deleted, $deleted); +} + +sub ERROR { + my ($type, $msg) = @_; + + if (report("ERROR", $type, $msg)) { + our $clean = 0; + our $cnt_error++; + return 1; + } + return 0; +} +sub WARN { + my ($type, $msg) = @_; + + if (report("WARNING", $type, $msg)) { + our $clean = 0; + our $cnt_warn++; + return 1; + } + return 0; +} +sub CHK { + my ($type, $msg) = @_; + + if ($check && report("CHECK", $type, $msg)) { + our $clean = 0; + our $cnt_chk++; + return 1; + } + return 0; +} + +sub check_absolute_file { + my ($absolute, $herecurr) = @_; + my $file = $absolute; + + ##print "absolute<$absolute>\n"; + + # See if any suffix of this path is a path within the tree. + while ($file =~ s@^[^/]*/@@) { + if (-f "$root/$file") { + ##print "file<$file>\n"; + last; + } + } + if (! -f _) { + return 0; + } + + # It is, so see if the prefix is acceptable. + my $prefix = $absolute; + substr($prefix, -length($file)) = ''; + + ##print "prefix<$prefix>\n"; + if ($prefix ne ".../") { + WARN("USE_RELATIVE_PATH", + "use relative pathname instead of absolute in changelog text\n" . $herecurr); + } +} + +sub trim { + my ($string) = @_; + + $string =~ s/^\s+|\s+$//g; + + return $string; +} + +sub ltrim { + my ($string) = @_; + + $string =~ s/^\s+//; + + return $string; +} + +sub rtrim { + my ($string) = @_; + + $string =~ s/\s+$//; + + return $string; +} + +sub string_find_replace { + my ($string, $find, $replace) = @_; + + $string =~ s/$find/$replace/g; + + return $string; +} + +sub tabify { + my ($leading) = @_; + + my $source_indent = $tabsize; + my $max_spaces_before_tab = $source_indent - 1; + my $spaces_to_tab = " " x $source_indent; + + #convert leading spaces to tabs + 1 while $leading =~ s@^([\t]*)$spaces_to_tab@$1\t@g; + #Remove spaces before a tab + 1 while $leading =~ s@^([\t]*)( {1,$max_spaces_before_tab})\t@$1\t@g; + + return "$leading"; +} + +sub pos_last_openparen { + my ($line) = @_; + + my $pos = 0; + + my $opens = $line =~ tr/\(/\(/; + my $closes = $line =~ tr/\)/\)/; + + my $last_openparen = 0; + + if (($opens == 0) || ($closes >= $opens)) { + return -1; + } + + my $len = length($line); + + for ($pos = 0; $pos < $len; $pos++) { + my $string = substr($line, $pos); + if ($string =~ /^($FuncArg|$balanced_parens)/) { + $pos += length($1) - 1; + } elsif (substr($line, $pos, 1) eq '(') { + $last_openparen = $pos; + } elsif (index($string, '(') == -1) { + last; + } + } + + return length(expand_tabs(substr($line, 0, $last_openparen))) + 1; +} + +sub get_raw_comment { + my ($line, $rawline) = @_; + my $comment = ''; + + for my $i (0 .. (length($line) - 1)) { + if (substr($line, $i, 1) eq "$;") { + $comment .= substr($rawline, $i, 1); + } + } + + return $comment; +} + +sub process { + my $filename = shift; + + my $linenr=0; + my $prevline=""; + my $prevrawline=""; + my $stashline=""; + my $stashrawline=""; + + my $length; + my $indent; + my $previndent=0; + my $stashindent=0; + + our $clean = 1; + my $signoff = 0; + my $author = ''; + my $authorsignoff = 0; + my $author_sob = ''; + my $is_patch = 0; + my $is_binding_patch = -1; + my $in_header_lines = $file ? 0 : 1; + my $in_commit_log = 0; #Scanning lines before patch + my $has_patch_separator = 0; #Found a --- line + my $has_commit_log = 0; #Encountered lines before patch + my $commit_log_lines = 0; #Number of commit log lines + my $commit_log_possible_stack_dump = 0; + my $commit_log_long_line = 0; + my $commit_log_has_diff = 0; + my $reported_maintainer_file = 0; + my $non_utf8_charset = 0; + + my $last_blank_line = 0; + my $last_coalesced_string_linenr = -1; + + our @report = (); + our $cnt_lines = 0; + our $cnt_error = 0; + our $cnt_warn = 0; + our $cnt_chk = 0; + + # Trace the real file/line as we go. + my $realfile = ''; + my $realline = 0; + my $realcnt = 0; + my $here = ''; + my $context_function; #undef'd unless there's a known function + my $in_comment = 0; + my $comment_edge = 0; + my $first_line = 0; + my $p1_prefix = ''; + + my $prev_values = 'E'; + + # suppression flags + my %suppress_ifbraces; + my %suppress_whiletrailers; + my %suppress_export; + my $suppress_statement = 0; + + my %signatures = (); + + # Pre-scan the patch sanitizing the lines. + # Pre-scan the patch looking for any __setup documentation. + # + my @setup_docs = (); + my $setup_docs = 0; + + my $camelcase_file_seeded = 0; + + my $checklicenseline = 1; + + sanitise_line_reset(); + my $line; + foreach my $rawline (@rawlines) { + $linenr++; + $line = $rawline; + + push(@fixed, $rawline) if ($fix); + + if ($rawline=~/^\+\+\+\s+(\S+)/) { + $setup_docs = 0; + if ($1 =~ m@Documentation/admin-guide/kernel-parameters.txt$@) { + $setup_docs = 1; + } + #next; + } + if ($rawline =~ /^\@\@ -\d+(?:,\d+)? \+(\d+)(,(\d+))? \@\@/) { + $realline=$1-1; + if (defined $2) { + $realcnt=$3+1; + } else { + $realcnt=1+1; + } + $in_comment = 0; + + # Guestimate if this is a continuing comment. Run + # the context looking for a comment "edge". If this + # edge is a close comment then we must be in a comment + # at context start. + my $edge; + my $cnt = $realcnt; + for (my $ln = $linenr + 1; $cnt > 0; $ln++) { + next if (defined $rawlines[$ln - 1] && + $rawlines[$ln - 1] =~ /^-/); + $cnt--; + #print "RAW<$rawlines[$ln - 1]>\n"; + last if (!defined $rawlines[$ln - 1]); + if ($rawlines[$ln - 1] =~ m@(/\*|\*/)@ && + $rawlines[$ln - 1] !~ m@"[^"]*(?:/\*|\*/)[^"]*"@) { + ($edge) = $1; + last; + } + } + if (defined $edge && $edge eq '*/') { + $in_comment = 1; + } + + # Guestimate if this is a continuing comment. If this + # is the start of a diff block and this line starts + # ' *' then it is very likely a comment. + if (!defined $edge && + $rawlines[$linenr] =~ m@^.\s*(?:\*\*+| \*)(?:\s|$)@) + { + $in_comment = 1; + } + + ##print "COMMENT:$in_comment edge<$edge> $rawline\n"; + sanitise_line_reset($in_comment); + + } elsif ($realcnt && $rawline =~ /^(?:\+| |$)/) { + # Standardise the strings and chars within the input to + # simplify matching -- only bother with positive lines. + $line = sanitise_line($rawline); + } + push(@lines, $line); + + if ($realcnt > 1) { + $realcnt-- if ($line =~ /^(?:\+| |$)/); + } else { + $realcnt = 0; + } + + #print "==>$rawline\n"; + #print "-->$line\n"; + + if ($setup_docs && $line =~ /^\+/) { + push(@setup_docs, $line); + } + } + + $prefix = ''; + + $realcnt = 0; + $linenr = 0; + $fixlinenr = -1; + foreach my $line (@lines) { + $linenr++; + $fixlinenr++; + my $sline = $line; #copy of $line + $sline =~ s/$;/ /g; #with comments as spaces + + my $rawline = $rawlines[$linenr - 1]; + my $raw_comment = get_raw_comment($line, $rawline); + +# check if it's a mode change, rename or start of a patch + if (!$in_commit_log && + ($line =~ /^ mode change [0-7]+ => [0-7]+ \S+\s*$/ || + ($line =~ /^rename (?:from|to) \S+\s*$/ || + $line =~ /^diff --git a\/[\w\/\.\_\-]+ b\/\S+\s*$/))) { + $is_patch = 1; + } + +#extract the line range in the file after the patch is applied + if (!$in_commit_log && + $line =~ /^\@\@ -\d+(?:,\d+)? \+(\d+)(,(\d+))? \@\@(.*)/) { + my $context = $4; + $is_patch = 1; + $first_line = $linenr + 1; + $realline=$1-1; + if (defined $2) { + $realcnt=$3+1; + } else { + $realcnt=1+1; + } + annotate_reset(); + $prev_values = 'E'; + + %suppress_ifbraces = (); + %suppress_whiletrailers = (); + %suppress_export = (); + $suppress_statement = 0; + if ($context =~ /\b(\w+)\s*\(/) { + $context_function = $1; + } else { + undef $context_function; + } + next; + +# track the line number as we move through the hunk, note that +# new versions of GNU diff omit the leading space on completely +# blank context lines so we need to count that too. + } elsif ($line =~ /^( |\+|$)/) { + $realline++; + $realcnt-- if ($realcnt != 0); + + # Measure the line length and indent. + ($length, $indent) = line_stats($rawline); + + # Track the previous line. + ($prevline, $stashline) = ($stashline, $line); + ($previndent, $stashindent) = ($stashindent, $indent); + ($prevrawline, $stashrawline) = ($stashrawline, $rawline); + + #warn "line<$line>\n"; + + } elsif ($realcnt == 1) { + $realcnt--; + } + + my $hunk_line = ($realcnt != 0); + + $here = "#$linenr: " if (!$file); + $here = "#$realline: " if ($file); + + my $found_file = 0; + # extract the filename as it passes + if ($line =~ /^diff --git.*?(\S+)$/) { + $realfile = $1; + $realfile =~ s@^([^/]*)/@@ if (!$file); + $in_commit_log = 0; + $found_file = 1; + } elsif ($line =~ /^\+\+\+\s+(\S+)/) { + $realfile = $1; + $realfile =~ s@^([^/]*)/@@ if (!$file); + $in_commit_log = 0; + + $p1_prefix = $1; + if (!$file && $tree && $p1_prefix ne '' && + -e "$root/$p1_prefix") { + WARN("PATCH_PREFIX", + "patch prefix '$p1_prefix' exists, appears to be a -p0 patch\n"); + } + + if ($realfile =~ m@^include/asm/@) { + ERROR("MODIFIED_INCLUDE_ASM", + "do not modify files in include/asm, change architecture specific files in include/asm-\n" . "$here$rawline\n"); + } + $found_file = 1; + } + +#make up the handle for any error we report on this line + if ($showfile) { + $prefix = "$realfile:$realline: " + } elsif ($emacs) { + if ($file) { + $prefix = "$filename:$realline: "; + } else { + $prefix = "$filename:$linenr: "; + } + } + + if ($found_file) { + if (is_maintained_obsolete($realfile)) { + WARN("OBSOLETE", + "$realfile is marked as 'obsolete' in the MAINTAINERS hierarchy. No unnecessary modifications please.\n"); + } + if ($realfile =~ m@^(?:drivers/net/|net/|drivers/staging/)@) { + $check = 1; + } else { + $check = $check_orig; + } + $checklicenseline = 1; + + if ($realfile !~ /^MAINTAINERS/) { + my $last_binding_patch = $is_binding_patch; + + $is_binding_patch = () = $realfile =~ m@^(?:Documentation/devicetree/|include/dt-bindings/)@; + + if (($last_binding_patch != -1) && + ($last_binding_patch ^ $is_binding_patch)) { + WARN("DT_SPLIT_BINDING_PATCH", + "DT binding docs and includes should be a separate patch. See: Documentation/devicetree/bindings/submitting-patches.rst\n"); + } + } + + next; + } + + $here .= "FILE: $realfile:$realline:" if ($realcnt != 0); + + my $hereline = "$here\n$rawline\n"; + my $herecurr = "$here\n$rawline\n"; + my $hereprev = "$here\n$prevrawline\n$rawline\n"; + + $cnt_lines++ if ($realcnt != 0); + +# Verify the existence of a commit log if appropriate +# 2 is used because a $signature is counted in $commit_log_lines + if ($in_commit_log) { + if ($line !~ /^\s*$/) { + $commit_log_lines++; #could be a $signature + } + } elsif ($has_commit_log && $commit_log_lines < 2) { + WARN("COMMIT_MESSAGE", + "Missing commit description - Add an appropriate one\n"); + $commit_log_lines = 2; #warn only once + } + +# Check if the commit log has what seems like a diff which can confuse patch + if ($in_commit_log && !$commit_log_has_diff && + (($line =~ m@^\s+diff\b.*a/([\w/]+)@ && + $line =~ m@^\s+diff\b.*a/[\w/]+\s+b/$1\b@) || + $line =~ m@^\s*(?:\-\-\-\s+a/|\+\+\+\s+b/)@ || + $line =~ m/^\s*\@\@ \-\d+,\d+ \+\d+,\d+ \@\@/)) { + ERROR("DIFF_IN_COMMIT_MSG", + "Avoid using diff content in the commit message - patch(1) might not work\n" . $herecurr); + $commit_log_has_diff = 1; + } + +# Check for incorrect file permissions + if ($line =~ /^new (file )?mode.*[7531]\d{0,2}$/) { + my $permhere = $here . "FILE: $realfile\n"; + if ($realfile !~ m@scripts/@ && + $realfile !~ /\.(py|pl|awk|sh)$/) { + ERROR("EXECUTE_PERMISSIONS", + "do not set execute permissions for source files\n" . $permhere); + } + } + +# Check the patch for a From: + if (decode("MIME-Header", $line) =~ /^From:\s*(.*)/) { + $author = $1; + my $curline = $linenr; + while(defined($rawlines[$curline]) && ($rawlines[$curline++] =~ /^[ \t]\s*(.*)/)) { + $author .= $1; + } + $author = encode("utf8", $author) if ($line =~ /=\?utf-8\?/i); + $author =~ s/"//g; + $author = reformat_email($author); + } + +# Check the patch for a signoff: + if ($line =~ /^\s*signed-off-by:\s*(.*)/i) { + $signoff++; + $in_commit_log = 0; + if ($author ne '' && $authorsignoff != 1) { + if (same_email_addresses($1, $author, 1)) { + $authorsignoff = 1; + } else { + my $ctx = $1; + my ($email_name, $email_comment, $email_address, $comment1) = parse_email($ctx); + my ($author_name, $author_comment, $author_address, $comment2) = parse_email($author); + + if ($email_address eq $author_address && $email_name eq $author_name) { + $author_sob = $ctx; + $authorsignoff = 2; + } elsif ($email_address eq $author_address) { + $author_sob = $ctx; + $authorsignoff = 3; + } elsif ($email_name eq $author_name) { + $author_sob = $ctx; + $authorsignoff = 4; + + my $address1 = $email_address; + my $address2 = $author_address; + + if ($address1 =~ /(\S+)\+\S+(\@.*)/) { + $address1 = "$1$2"; + } + if ($address2 =~ /(\S+)\+\S+(\@.*)/) { + $address2 = "$1$2"; + } + if ($address1 eq $address2) { + $authorsignoff = 5; + } + } + } + } + } + +# Check for patch separator + if ($line =~ /^---$/) { + $has_patch_separator = 1; + $in_commit_log = 0; + } + +# Check if MAINTAINERS is being updated. If so, there's probably no need to +# emit the "does MAINTAINERS need updating?" message on file add/move/delete + if ($line =~ /^\s*MAINTAINERS\s*\|/) { + $reported_maintainer_file = 1; + } + +# Check signature styles + if (!$in_header_lines && + $line =~ /^(\s*)([a-z0-9_-]+by:|$signature_tags)(\s*)(.*)/i) { + my $space_before = $1; + my $sign_off = $2; + my $space_after = $3; + my $email = $4; + my $ucfirst_sign_off = ucfirst(lc($sign_off)); + + if ($sign_off !~ /$signature_tags/) { + WARN("BAD_SIGN_OFF", + "Non-standard signature: $sign_off\n" . $herecurr); + } + if (defined $space_before && $space_before ne "") { + if (WARN("BAD_SIGN_OFF", + "Do not use whitespace before $ucfirst_sign_off\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] = + "$ucfirst_sign_off $email"; + } + } + if ($sign_off =~ /-by:$/i && $sign_off ne $ucfirst_sign_off) { + if (WARN("BAD_SIGN_OFF", + "'$ucfirst_sign_off' is the preferred signature form\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] = + "$ucfirst_sign_off $email"; + } + + } + if (!defined $space_after || $space_after ne " ") { + if (WARN("BAD_SIGN_OFF", + "Use a single space after $ucfirst_sign_off\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] = + "$ucfirst_sign_off $email"; + } + } + + my ($email_name, $name_comment, $email_address, $comment) = parse_email($email); + my $suggested_email = format_email(($email_name, $name_comment, $email_address, $comment)); + if ($suggested_email eq "") { + ERROR("BAD_SIGN_OFF", + "Unrecognized email address: '$email'\n" . $herecurr); + } else { + my $dequoted = $suggested_email; + $dequoted =~ s/^"//; + $dequoted =~ s/" \]/) || + $line =~ /^(?:\s+\w+:\s+[0-9a-fA-F]+){3,3}/ || + $line =~ /^\s*\#\d+\s*\[[0-9a-fA-F]+\]\s*\w+ at [0-9a-fA-F]+/) { + # stack dump address styles + $commit_log_possible_stack_dump = 1; + } + +# Check for line lengths > 75 in commit log, warn once + if ($in_commit_log && !$commit_log_long_line && + length($line) > 75 && + !($line =~ /^\s*[a-zA-Z0-9_\/\.]+\s+\|\s+\d+/ || + # file delta changes + $line =~ /^\s*(?:[\w\.\-]+\/)++[\w\.\-]+:/ || + # filename then : + $line =~ /^\s*(?:Fixes:|Link:)/i || + # A Fixes: or Link: line + $commit_log_possible_stack_dump)) { + WARN("COMMIT_LOG_LONG_LINE", + "Possible unwrapped commit description (prefer a maximum 75 chars per line)\n" . $herecurr); + $commit_log_long_line = 1; + } + +# Reset possible stack dump if a blank line is found + if ($in_commit_log && $commit_log_possible_stack_dump && + $line =~ /^\s*$/) { + $commit_log_possible_stack_dump = 0; + } + +# Check for git id commit length and improperly formed commit descriptions + if ($in_commit_log && !$commit_log_possible_stack_dump && + $line !~ /^\s*(?:Link|Patchwork|http|https|BugLink|base-commit):/i && + $line !~ /^This reverts commit [0-9a-f]{7,40}/ && + ($line =~ /\bcommit\s+[0-9a-f]{5,}\b/i || + ($line =~ /(?:\s|^)[0-9a-f]{12,40}(?:[\s"'\(\[]|$)/i && + $line !~ /[\<\[][0-9a-f]{12,40}[\>\]]/i && + $line !~ /\bfixes:\s*[0-9a-f]{12,40}/i))) { + my $init_char = "c"; + my $orig_commit = ""; + my $short = 1; + my $long = 0; + my $case = 1; + my $space = 1; + my $hasdesc = 0; + my $hasparens = 0; + my $id = '0123456789ab'; + my $orig_desc = "commit description"; + my $description = ""; + + if ($line =~ /\b(c)ommit\s+([0-9a-f]{5,})\b/i) { + $init_char = $1; + $orig_commit = lc($2); + } elsif ($line =~ /\b([0-9a-f]{12,40})\b/i) { + $orig_commit = lc($1); + } + + $short = 0 if ($line =~ /\bcommit\s+[0-9a-f]{12,40}/i); + $long = 1 if ($line =~ /\bcommit\s+[0-9a-f]{41,}/i); + $space = 0 if ($line =~ /\bcommit [0-9a-f]/i); + $case = 0 if ($line =~ /\b[Cc]ommit\s+[0-9a-f]{5,40}[^A-F]/); + if ($line =~ /\bcommit\s+[0-9a-f]{5,}\s+\("([^"]+)"\)/i) { + $orig_desc = $1; + $hasparens = 1; + } elsif ($line =~ /\bcommit\s+[0-9a-f]{5,}\s*$/i && + defined $rawlines[$linenr] && + $rawlines[$linenr] =~ /^\s*\("([^"]+)"\)/) { + $orig_desc = $1; + $hasparens = 1; + } elsif ($line =~ /\bcommit\s+[0-9a-f]{5,}\s+\("[^"]+$/i && + defined $rawlines[$linenr] && + $rawlines[$linenr] =~ /^\s*[^"]+"\)/) { + $line =~ /\bcommit\s+[0-9a-f]{5,}\s+\("([^"]+)$/i; + $orig_desc = $1; + $rawlines[$linenr] =~ /^\s*([^"]+)"\)/; + $orig_desc .= " " . $1; + $hasparens = 1; + } + + ($id, $description) = git_commit_info($orig_commit, + $id, $orig_desc); + + if (defined($id) && + ($short || $long || $space || $case || ($orig_desc ne $description) || !$hasparens)) { + ERROR("GIT_COMMIT_ID", + "Please use git commit description style 'commit <12+ chars of sha1> (\"\")' - ie: '${init_char}ommit $id (\"$description\")'\n" . $herecurr); + } + } + +# Check for added, moved or deleted files + if (!$reported_maintainer_file && !$in_commit_log && + ($line =~ /^(?:new|deleted) file mode\s*\d+\s*$/ || + $line =~ /^rename (?:from|to) [\w\/\.\-]+\s*$/ || + ($line =~ /\{\s*([\w\/\.\-]*)\s*\=\>\s*([\w\/\.\-]*)\s*\}/ && + (defined($1) || defined($2))))) { + $is_patch = 1; + $reported_maintainer_file = 1; + WARN("FILE_PATH_CHANGES", + "added, moved or deleted file(s), does MAINTAINERS need updating?\n" . $herecurr); + } + +# Check for adding new DT bindings not in schema format + if (!$in_commit_log && + ($line =~ /^new file mode\s*\d+\s*$/) && + ($realfile =~ m@^Documentation/devicetree/bindings/.*\.txt$@)) { + WARN("DT_SCHEMA_BINDING_PATCH", + "DT bindings should be in DT schema format. See: Documentation/devicetree/writing-schema.rst\n"); + } + +# Check for wrappage within a valid hunk of the file + if ($realcnt != 0 && $line !~ m{^(?:\+|-| |\\ No newline|$)}) { + ERROR("CORRUPTED_PATCH", + "patch seems to be corrupt (line wrapped?)\n" . + $herecurr) if (!$emitted_corrupt++); + } + +# UTF-8 regex found at http://www.w3.org/International/questions/qa-forms-utf-8.en.php + if (($realfile =~ /^$/ || $line =~ /^\+/) && + $rawline !~ m/^$UTF8*$/) { + my ($utf8_prefix) = ($rawline =~ /^($UTF8*)/); + + my $blank = copy_spacing($rawline); + my $ptr = substr($blank, 0, length($utf8_prefix)) . "^"; + my $hereptr = "$hereline$ptr\n"; + + CHK("INVALID_UTF8", + "Invalid UTF-8, patch and commit message should be encoded in UTF-8\n" . $hereptr); + } + +# Check if it's the start of a commit log +# (not a header line and we haven't seen the patch filename) + if ($in_header_lines && $realfile =~ /^$/ && + !($rawline =~ /^\s+(?:\S|$)/ || + $rawline =~ /^(?:commit\b|from\b|[\w-]+:)/i)) { + $in_header_lines = 0; + $in_commit_log = 1; + $has_commit_log = 1; + } + +# Check if there is UTF-8 in a commit log when a mail header has explicitly +# declined it, i.e defined some charset where it is missing. + if ($in_header_lines && + $rawline =~ /^Content-Type:.+charset="(.+)".*$/ && + $1 !~ /utf-8/i) { + $non_utf8_charset = 1; + } + + if ($in_commit_log && $non_utf8_charset && $realfile =~ /^$/ && + $rawline =~ /$NON_ASCII_UTF8/) { + WARN("UTF8_BEFORE_PATCH", + "8-bit UTF-8 used in possible commit log\n" . $herecurr); + } + +# Check for absolute kernel paths in commit message + if ($tree && $in_commit_log) { + while ($line =~ m{(?:^|\s)(/\S*)}g) { + my $file = $1; + + if ($file =~ m{^(.*?)(?::\d+)+:?$} && + check_absolute_file($1, $herecurr)) { + # + } else { + check_absolute_file($file, $herecurr); + } + } + } + +# Check for various typo / spelling mistakes + if (defined($misspellings) && + ($in_commit_log || $line =~ /^(?:\+|Subject:)/i)) { + while ($rawline =~ /(?:^|[^a-z@])($misspellings)(?:\b|$|[^a-z@])/gi) { + my $typo = $1; + my $typo_fix = $spelling_fix{lc($typo)}; + $typo_fix = ucfirst($typo_fix) if ($typo =~ /^[A-Z]/); + $typo_fix = uc($typo_fix) if ($typo =~ /^[A-Z]+$/); + my $msg_level = \&WARN; + $msg_level = \&CHK if ($file); + if (&{$msg_level}("TYPO_SPELLING", + "'$typo' may be misspelled - perhaps '$typo_fix'?\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/(^|[^A-Za-z@])($typo)($|[^A-Za-z@])/$1$typo_fix$3/; + } + } + } + +# check for invalid commit id + if ($in_commit_log && $line =~ /(^fixes:|\bcommit)\s+([0-9a-f]{6,40})\b/i) { + my $id; + my $description; + ($id, $description) = git_commit_info($2, undef, undef); + if (!defined($id)) { + WARN("UNKNOWN_COMMIT_ID", + "Unknown commit id '$2', maybe rebased or not pulled?\n" . $herecurr); + } + } + +# check for repeated words separated by a single space + if ($rawline =~ /^\+/ || $in_commit_log) { + while ($rawline =~ /\b($word_pattern) (?=($word_pattern))/g) { + + my $first = $1; + my $second = $2; + + if ($first =~ /(?:struct|union|enum)/) { + pos($rawline) += length($first) + length($second) + 1; + next; + } + + next if ($first ne $second); + next if ($first eq 'long'); + + if (WARN("REPEATED_WORD", + "Possible repeated word: '$first'\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\b$first $second\b/$first/; + } + } + + # if it's a repeated word on consecutive lines in a comment block + if ($prevline =~ /$;+\s*$/ && + $prevrawline =~ /($word_pattern)\s*$/) { + my $last_word = $1; + if ($rawline =~ /^\+\s*\*\s*$last_word /) { + if (WARN("REPEATED_WORD", + "Possible repeated word: '$last_word'\n" . $hereprev) && + $fix) { + $fixed[$fixlinenr] =~ s/(\+\s*\*\s*)$last_word /$1/; + } + } + } + } + +# ignore non-hunk lines and lines being removed + next if (!$hunk_line || $line =~ /^-/); + +#trailing whitespace + if ($line =~ /^\+.*\015/) { + my $herevet = "$here\n" . cat_vet($rawline) . "\n"; + if (ERROR("DOS_LINE_ENDINGS", + "DOS line endings\n" . $herevet) && + $fix) { + $fixed[$fixlinenr] =~ s/[\s\015]+$//; + } + } elsif ($rawline =~ /^\+.*\S\s+$/ || $rawline =~ /^\+\s+$/) { + my $herevet = "$here\n" . cat_vet($rawline) . "\n"; + if (ERROR("TRAILING_WHITESPACE", + "trailing whitespace\n" . $herevet) && + $fix) { + $fixed[$fixlinenr] =~ s/\s+$//; + } + + $rpt_cleaners = 1; + } + +# Check for FSF mailing addresses. + if ($rawline =~ /\bwrite to the Free/i || + $rawline =~ /\b675\s+Mass\s+Ave/i || + $rawline =~ /\b59\s+Temple\s+Pl/i || + $rawline =~ /\b51\s+Franklin\s+St/i) { + my $herevet = "$here\n" . cat_vet($rawline) . "\n"; + my $msg_level = \&ERROR; + $msg_level = \&CHK if ($file); + &{$msg_level}("FSF_MAILING_ADDRESS", + "Do not include the paragraph about writing to the Free Software Foundation's mailing address from the sample GPL notice. The FSF has changed addresses in the past, and may do so again. Linux already includes a copy of the GPL.\n" . $herevet) + } + +# check for Kconfig help text having a real description +# Only applies when adding the entry originally, after that we do not have +# sufficient context to determine whether it is indeed long enough. + if ($realfile =~ /Kconfig/ && + # 'choice' is usually the last thing on the line (though + # Kconfig supports named choices), so use a word boundary + # (\b) rather than a whitespace character (\s) + $line =~ /^\+\s*(?:config|menuconfig|choice)\b/) { + my $length = 0; + my $cnt = $realcnt; + my $ln = $linenr + 1; + my $f; + my $is_start = 0; + my $is_end = 0; + for (; $cnt > 0 && defined $lines[$ln - 1]; $ln++) { + $f = $lines[$ln - 1]; + $cnt-- if ($lines[$ln - 1] !~ /^-/); + $is_end = $lines[$ln - 1] =~ /^\+/; + + next if ($f =~ /^-/); + last if (!$file && $f =~ /^\@\@/); + + if ($lines[$ln - 1] =~ /^\+\s*(?:bool|tristate|prompt)\s*["']/) { + $is_start = 1; + } elsif ($lines[$ln - 1] =~ /^\+\s*(?:---)?help(?:---)?$/) { + $length = -1; + } + + $f =~ s/^.//; + $f =~ s/#.*//; + $f =~ s/^\s+//; + next if ($f =~ /^$/); + + # This only checks context lines in the patch + # and so hopefully shouldn't trigger false + # positives, even though some of these are + # common words in help texts + if ($f =~ /^\s*(?:config|menuconfig|choice|endchoice| + if|endif|menu|endmenu|source)\b/x) { + $is_end = 1; + last; + } + $length++; + } + if ($is_start && $is_end && $length < $min_conf_desc_length) { + WARN("CONFIG_DESCRIPTION", + "please write a paragraph that describes the config symbol fully\n" . $herecurr); + } + #print "is_start<$is_start> is_end<$is_end> length<$length>\n"; + } + +# check MAINTAINERS entries + if ($realfile =~ /^MAINTAINERS$/) { +# check MAINTAINERS entries for the right form + if ($rawline =~ /^\+[A-Z]:/ && + $rawline !~ /^\+[A-Z]:\t\S/) { + if (WARN("MAINTAINERS_STYLE", + "MAINTAINERS entries use one tab after TYPE:\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/^(\+[A-Z]):\s*/$1:\t/; + } + } +# check MAINTAINERS entries for the right ordering too + my $preferred_order = 'MRLSWQBCPTFXNK'; + if ($rawline =~ /^\+[A-Z]:/ && + $prevrawline =~ /^[\+ ][A-Z]:/) { + $rawline =~ /^\+([A-Z]):\s*(.*)/; + my $cur = $1; + my $curval = $2; + $prevrawline =~ /^[\+ ]([A-Z]):\s*(.*)/; + my $prev = $1; + my $prevval = $2; + my $curindex = index($preferred_order, $cur); + my $previndex = index($preferred_order, $prev); + if ($curindex < 0) { + WARN("MAINTAINERS_STYLE", + "Unknown MAINTAINERS entry type: '$cur'\n" . $herecurr); + } else { + if ($previndex >= 0 && $curindex < $previndex) { + WARN("MAINTAINERS_STYLE", + "Misordered MAINTAINERS entry - list '$cur:' before '$prev:'\n" . $hereprev); + } elsif ((($prev eq 'F' && $cur eq 'F') || + ($prev eq 'X' && $cur eq 'X')) && + ($prevval cmp $curval) > 0) { + WARN("MAINTAINERS_STYLE", + "Misordered MAINTAINERS entry - list file patterns in alphabetic order\n" . $hereprev); + } + } + } + } + +# discourage the use of boolean for type definition attributes of Kconfig options + if ($realfile =~ /Kconfig/ && + $line =~ /^\+\s*\bboolean\b/) { + WARN("CONFIG_TYPE_BOOLEAN", + "Use of boolean is deprecated, please use bool instead.\n" . $herecurr); + } + + if (($realfile =~ /Makefile.*/ || $realfile =~ /Kbuild.*/) && + ($line =~ /\+(EXTRA_[A-Z]+FLAGS).*/)) { + my $flag = $1; + my $replacement = { + 'EXTRA_AFLAGS' => 'asflags-y', + 'EXTRA_CFLAGS' => 'ccflags-y', + 'EXTRA_CPPFLAGS' => 'cppflags-y', + 'EXTRA_LDFLAGS' => 'ldflags-y', + }; + + WARN("DEPRECATED_VARIABLE", + "Use of $flag is deprecated, please use \`$replacement->{$flag} instead.\n" . $herecurr) if ($replacement->{$flag}); + } + +# check for DT compatible documentation + if (defined $root && + (($realfile =~ /\.dtsi?$/ && $line =~ /^\+\s*compatible\s*=\s*\"/) || + ($realfile =~ /\.[ch]$/ && $line =~ /^\+.*\.compatible\s*=\s*\"/))) { + + my @compats = $rawline =~ /\"([a-zA-Z0-9\-\,\.\+_]+)\"/g; + + my $dt_path = $root . "/Documentation/devicetree/bindings/"; + my $vp_file = $dt_path . "vendor-prefixes.yaml"; + + foreach my $compat (@compats) { + my $compat2 = $compat; + $compat2 =~ s/\,[a-zA-Z0-9]*\-/\,<\.\*>\-/; + my $compat3 = $compat; + $compat3 =~ s/\,([a-z]*)[0-9]*\-/\,$1<\.\*>\-/; + `grep -Erq "$compat|$compat2|$compat3" $dt_path`; + if ( $? >> 8 ) { + WARN("UNDOCUMENTED_DT_STRING", + "DT compatible string \"$compat\" appears un-documented -- check $dt_path\n" . $herecurr); + } + + next if $compat !~ /^([a-zA-Z0-9\-]+)\,/; + my $vendor = $1; + `grep -Eq "\\"\\^\Q$vendor\E,\\.\\*\\":" $vp_file`; + if ( $? >> 8 ) { + WARN("UNDOCUMENTED_DT_STRING", + "DT compatible string vendor \"$vendor\" appears un-documented -- check $vp_file\n" . $herecurr); + } + } + } + +# check for using SPDX license tag at beginning of files + if ($realline == $checklicenseline) { + if ($rawline =~ /^[ \+]\s*\#\!\s*\//) { + $checklicenseline = 2; + } elsif ($rawline =~ /^\+/) { + my $comment = ""; + if ($realfile =~ /\.(h|s|S)$/) { + $comment = '/*'; + } elsif ($realfile =~ /\.(c|dts|dtsi)$/) { + $comment = '//'; + } elsif (($checklicenseline == 2) || $realfile =~ /\.(sh|pl|py|awk|tc|yaml)$/) { + $comment = '#'; + } elsif ($realfile =~ /\.rst$/) { + $comment = '..'; + } + +# check SPDX comment style for .[chsS] files + if ($realfile =~ /\.[chsS]$/ && + $rawline =~ /SPDX-License-Identifier:/ && + $rawline !~ m@^\+\s*\Q$comment\E\s*@) { + WARN("SPDX_LICENSE_TAG", + "Improper SPDX comment style for '$realfile', please use '$comment' instead\n" . $herecurr); + } + + if ($comment !~ /^$/ && + $rawline !~ m@^\+\Q$comment\E SPDX-License-Identifier: @) { + WARN("SPDX_LICENSE_TAG", + "Missing or malformed SPDX-License-Identifier tag in line $checklicenseline\n" . $herecurr); + } elsif ($rawline =~ /(SPDX-License-Identifier: .*)/) { + my $spdx_license = $1; + if (!is_SPDX_License_valid($spdx_license)) { + WARN("SPDX_LICENSE_TAG", + "'$spdx_license' is not supported in LICENSES/...\n" . $herecurr); + } + if ($realfile =~ m@^Documentation/devicetree/bindings/@ && + not $spdx_license =~ /GPL-2\.0.*BSD-2-Clause/) { + my $msg_level = \&WARN; + $msg_level = \&CHK if ($file); + if (&{$msg_level}("SPDX_LICENSE_TAG", + + "DT binding documents should be licensed (GPL-2.0-only OR BSD-2-Clause)\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/SPDX-License-Identifier: .*/SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)/; + } + } + } + } + } + +# check for embedded filenames + if ($rawline =~ /^\+.*\Q$realfile\E/) { + WARN("EMBEDDED_FILENAME", + "It's generally not useful to have the filename in the file\n" . $herecurr); + } + +# check we are in a valid source file if not then ignore this hunk + next if ($realfile !~ /\.(h|c|s|S|sh|dtsi|dts)$/); + +# check for using SPDX-License-Identifier on the wrong line number + if ($realline != $checklicenseline && + $rawline =~ /\bSPDX-License-Identifier:/ && + substr($line, @-, @+ - @-) eq "$;" x (@+ - @-)) { + WARN("SPDX_LICENSE_TAG", + "Misplaced SPDX-License-Identifier tag - use line $checklicenseline instead\n" . $herecurr); + } + +# line length limit (with some exclusions) +# +# There are a few types of lines that may extend beyond $max_line_length: +# logging functions like pr_info that end in a string +# lines with a single string +# #defines that are a single string +# lines with an RFC3986 like URL +# +# There are 3 different line length message types: +# LONG_LINE_COMMENT a comment starts before but extends beyond $max_line_length +# LONG_LINE_STRING a string starts before but extends beyond $max_line_length +# LONG_LINE all other lines longer than $max_line_length +# +# if LONG_LINE is ignored, the other 2 types are also ignored +# + + if ($line =~ /^\+/ && $length > $max_line_length) { + my $msg_type = "LONG_LINE"; + + # Check the allowed long line types first + + # logging functions that end in a string that starts + # before $max_line_length + if ($line =~ /^\+\s*$logFunctions\s*\(\s*(?:(?:KERN_\S+\s*|[^"]*))?($String\s*(?:|,|\)\s*;)\s*)$/ && + length(expand_tabs(substr($line, 1, length($line) - length($1) - 1))) <= $max_line_length) { + $msg_type = ""; + + # lines with only strings (w/ possible termination) + # #defines with only strings + } elsif ($line =~ /^\+\s*$String\s*(?:\s*|,|\)\s*;)\s*$/ || + $line =~ /^\+\s*#\s*define\s+\w+\s+$String$/) { + $msg_type = ""; + + # More special cases + } elsif ($line =~ /^\+.*\bEFI_GUID\s*\(/ || + $line =~ /^\+\s*(?:\w+)?\s*DEFINE_PER_CPU/) { + $msg_type = ""; + + # URL ($rawline is used in case the URL is in a comment) + } elsif ($rawline =~ /^\+.*\b[a-z][\w\.\+\-]*:\/\/\S+/i) { + $msg_type = ""; + + # Otherwise set the alternate message types + + # a comment starts before $max_line_length + } elsif ($line =~ /($;[\s$;]*)$/ && + length(expand_tabs(substr($line, 1, length($line) - length($1) - 1))) <= $max_line_length) { + $msg_type = "LONG_LINE_COMMENT" + + # a quoted string starts before $max_line_length + } elsif ($sline =~ /\s*($String(?:\s*(?:\\|,\s*|\)\s*;\s*))?)$/ && + length(expand_tabs(substr($line, 1, length($line) - length($1) - 1))) <= $max_line_length) { + $msg_type = "LONG_LINE_STRING" + } + + if ($msg_type ne "" && + (show_type("LONG_LINE") || show_type($msg_type))) { + my $msg_level = \&WARN; + $msg_level = \&CHK if ($file); + &{$msg_level}($msg_type, + "line length of $length exceeds $max_line_length columns\n" . $herecurr); + } + } + +# check for adding lines without a newline. + if ($line =~ /^\+/ && defined $lines[$linenr] && $lines[$linenr] =~ /^\\ No newline at end of file/) { + WARN("MISSING_EOF_NEWLINE", + "adding a line without newline at end of file\n" . $herecurr); + } + +# check we are in a valid source file C or perl if not then ignore this hunk + next if ($realfile !~ /\.(h|c|pl|dtsi|dts)$/); + +# at the beginning of a line any tabs must come first and anything +# more than $tabsize must use tabs. + if ($rawline =~ /^\+\s* \t\s*\S/ || + $rawline =~ /^\+\s* \s*/) { + my $herevet = "$here\n" . cat_vet($rawline) . "\n"; + $rpt_cleaners = 1; + if (ERROR("CODE_INDENT", + "code indent should use tabs where possible\n" . $herevet) && + $fix) { + $fixed[$fixlinenr] =~ s/^\+([ \t]+)/"\+" . tabify($1)/e; + } + } + +# check for space before tabs. + if ($rawline =~ /^\+/ && $rawline =~ / \t/) { + my $herevet = "$here\n" . cat_vet($rawline) . "\n"; + if (WARN("SPACE_BEFORE_TAB", + "please, no space before tabs\n" . $herevet) && + $fix) { + while ($fixed[$fixlinenr] =~ + s/(^\+.*) {$tabsize,$tabsize}\t/$1\t\t/) {} + while ($fixed[$fixlinenr] =~ + s/(^\+.*) +\t/$1\t/) {} + } + } + +# check for assignments on the start of a line + if ($sline =~ /^\+\s+($Assignment)[^=]/) { + CHK("ASSIGNMENT_CONTINUATIONS", + "Assignment operator '$1' should be on the previous line\n" . $hereprev); + } + +# check for && or || at the start of a line + if ($rawline =~ /^\+\s*(&&|\|\|)/) { + CHK("LOGICAL_CONTINUATIONS", + "Logical continuations should be on the previous line\n" . $hereprev); + } + +# check indentation starts on a tab stop + if ($perl_version_ok && + $sline =~ /^\+\t+( +)(?:$c90_Keywords\b|\{\s*$|\}\s*(?:else\b|while\b|\s*$)|$Declare\s*$Ident\s*[;=])/) { + my $indent = length($1); + if ($indent % $tabsize) { + if (WARN("TABSTOP", + "Statements should start on a tabstop\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s@(^\+\t+) +@$1 . "\t" x ($indent/$tabsize)@e; + } + } + } + +# check multi-line statement indentation matches previous line + if ($perl_version_ok && + $prevline =~ /^\+([ \t]*)((?:$c90_Keywords(?:\s+if)\s*)|(?:$Declare\s*)?(?:$Ident|\(\s*\*\s*$Ident\s*\))\s*|(?:\*\s*)*$Lval\s*=\s*$Ident\s*)\(.*(\&\&|\|\||,)\s*$/) { + $prevline =~ /^\+(\t*)(.*)$/; + my $oldindent = $1; + my $rest = $2; + + my $pos = pos_last_openparen($rest); + if ($pos >= 0) { + $line =~ /^(\+| )([ \t]*)/; + my $newindent = $2; + + my $goodtabindent = $oldindent . + "\t" x ($pos / $tabsize) . + " " x ($pos % $tabsize); + my $goodspaceindent = $oldindent . " " x $pos; + + if ($newindent ne $goodtabindent && + $newindent ne $goodspaceindent) { + + if (CHK("PARENTHESIS_ALIGNMENT", + "Alignment should match open parenthesis\n" . $hereprev) && + $fix && $line =~ /^\+/) { + $fixed[$fixlinenr] =~ + s/^\+[ \t]*/\+$goodtabindent/; + } + } + } + } + +# check for space after cast like "(int) foo" or "(struct foo) bar" +# avoid checking a few false positives: +# "sizeof(<type>)" or "__alignof__(<type>)" +# function pointer declarations like "(*foo)(int) = bar;" +# structure definitions like "(struct foo) { 0 };" +# multiline macros that define functions +# known attributes or the __attribute__ keyword + if ($line =~ /^\+(.*)\(\s*$Type\s*\)([ \t]++)((?![={]|\\$|$Attribute|__attribute__))/ && + (!defined($1) || $1 !~ /\b(?:sizeof|__alignof__)\s*$/)) { + if (CHK("SPACING", + "No space is necessary after a cast\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ + s/(\(\s*$Type\s*\))[ \t]+/$1/; + } + } + +# Block comment styles +# Networking with an initial /* + if ($realfile =~ m@^(drivers/net/|net/)@ && + $prevrawline =~ /^\+[ \t]*\/\*[ \t]*$/ && + $rawline =~ /^\+[ \t]*\*/ && + $realline > 3) { # Do not warn about the initial copyright comment block after SPDX-License-Identifier + WARN("NETWORKING_BLOCK_COMMENT_STYLE", + "networking block comments don't use an empty /* line, use /* Comment...\n" . $hereprev); + } + +# Block comments use * on subsequent lines + if ($prevline =~ /$;[ \t]*$/ && #ends in comment + $prevrawline =~ /^\+.*?\/\*/ && #starting /* + $prevrawline !~ /\*\/[ \t]*$/ && #no trailing */ + $rawline =~ /^\+/ && #line is new + $rawline !~ /^\+[ \t]*\*/) { #no leading * + WARN("BLOCK_COMMENT_STYLE", + "Block comments use * on subsequent lines\n" . $hereprev); + } + +# Block comments use */ on trailing lines + if ($rawline !~ m@^\+[ \t]*\*/[ \t]*$@ && #trailing */ + $rawline !~ m@^\+.*/\*.*\*/[ \t]*$@ && #inline /*...*/ + $rawline !~ m@^\+.*\*{2,}/[ \t]*$@ && #trailing **/ + $rawline =~ m@^\+[ \t]*.+\*\/[ \t]*$@) { #non blank */ + WARN("BLOCK_COMMENT_STYLE", + "Block comments use a trailing */ on a separate line\n" . $herecurr); + } + +# Block comment * alignment + if ($prevline =~ /$;[ \t]*$/ && #ends in comment + $line =~ /^\+[ \t]*$;/ && #leading comment + $rawline =~ /^\+[ \t]*\*/ && #leading * + (($prevrawline =~ /^\+.*?\/\*/ && #leading /* + $prevrawline !~ /\*\/[ \t]*$/) || #no trailing */ + $prevrawline =~ /^\+[ \t]*\*/)) { #leading * + my $oldindent; + $prevrawline =~ m@^\+([ \t]*/?)\*@; + if (defined($1)) { + $oldindent = expand_tabs($1); + } else { + $prevrawline =~ m@^\+(.*/?)\*@; + $oldindent = expand_tabs($1); + } + $rawline =~ m@^\+([ \t]*)\*@; + my $newindent = $1; + $newindent = expand_tabs($newindent); + if (length($oldindent) ne length($newindent)) { + WARN("BLOCK_COMMENT_STYLE", + "Block comments should align the * on each line\n" . $hereprev); + } + } + +# check for missing blank lines after struct/union declarations +# with exceptions for various attributes and macros + if ($prevline =~ /^[\+ ]};?\s*$/ && + $line =~ /^\+/ && + !($line =~ /^\+\s*$/ || + $line =~ /^\+\s*EXPORT_SYMBOL/ || + $line =~ /^\+\s*MODULE_/i || + $line =~ /^\+\s*\#\s*(?:end|elif|else)/ || + $line =~ /^\+[a-z_]*init/ || + $line =~ /^\+\s*(?:static\s+)?[A-Z_]*ATTR/ || + $line =~ /^\+\s*DECLARE/ || + $line =~ /^\+\s*builtin_[\w_]*driver/ || + $line =~ /^\+\s*__setup/)) { + if (CHK("LINE_SPACING", + "Please use a blank line after function/struct/union/enum declarations\n" . $hereprev) && + $fix) { + fix_insert_line($fixlinenr, "\+"); + } + } + +# check for multiple consecutive blank lines + if ($prevline =~ /^[\+ ]\s*$/ && + $line =~ /^\+\s*$/ && + $last_blank_line != ($linenr - 1)) { + if (CHK("LINE_SPACING", + "Please don't use multiple blank lines\n" . $hereprev) && + $fix) { + fix_delete_line($fixlinenr, $rawline); + } + + $last_blank_line = $linenr; + } + +# check for missing blank lines after declarations + if ($sline =~ /^\+\s+\S/ && #Not at char 1 + # actual declarations + ($prevline =~ /^\+\s+$Declare\s*$Ident\s*[=,;:\[]/ || + # function pointer declarations + $prevline =~ /^\+\s+$Declare\s*\(\s*\*\s*$Ident\s*\)\s*[=,;:\[\(]/ || + # foo bar; where foo is some local typedef or #define + $prevline =~ /^\+\s+$Ident(?:\s+|\s*\*\s*)$Ident\s*[=,;\[]/ || + # known declaration macros + $prevline =~ /^\+\s+$declaration_macros/) && + # for "else if" which can look like "$Ident $Ident" + !($prevline =~ /^\+\s+$c90_Keywords\b/ || + # other possible extensions of declaration lines + $prevline =~ /(?:$Compare|$Assignment|$Operators)\s*$/ || + # not starting a section or a macro "\" extended line + $prevline =~ /(?:\{\s*|\\)$/) && + # looks like a declaration + !($sline =~ /^\+\s+$Declare\s*$Ident\s*[=,;:\[]/ || + # function pointer declarations + $sline =~ /^\+\s+$Declare\s*\(\s*\*\s*$Ident\s*\)\s*[=,;:\[\(]/ || + # foo bar; where foo is some local typedef or #define + $sline =~ /^\+\s+$Ident(?:\s+|\s*\*\s*)$Ident\s*[=,;\[]/ || + # known declaration macros + $sline =~ /^\+\s+$declaration_macros/ || + # start of struct or union or enum + $sline =~ /^\+\s+(?:static\s+)?(?:const\s+)?(?:union|struct|enum|typedef)\b/ || + # start or end of block or continuation of declaration + $sline =~ /^\+\s+(?:$|[\{\}\.\#\"\?\:\(\[])/ || + # bitfield continuation + $sline =~ /^\+\s+$Ident\s*:\s*\d+\s*[,;]/ || + # other possible extensions of declaration lines + $sline =~ /^\+\s+\(?\s*(?:$Compare|$Assignment|$Operators)/) && + # indentation of previous and current line are the same + (($prevline =~ /\+(\s+)\S/) && $sline =~ /^\+$1\S/)) { + if (WARN("LINE_SPACING", + "Missing a blank line after declarations\n" . $hereprev) && + $fix) { + fix_insert_line($fixlinenr, "\+"); + } + } + +# check for spaces at the beginning of a line. +# Exceptions: +# 1) within comments +# 2) indented preprocessor commands +# 3) hanging labels + if ($rawline =~ /^\+ / && $line !~ /^\+ *(?:$;|#|$Ident:)/) { + my $herevet = "$here\n" . cat_vet($rawline) . "\n"; + if (WARN("LEADING_SPACE", + "please, no spaces at the start of a line\n" . $herevet) && + $fix) { + $fixed[$fixlinenr] =~ s/^\+([ \t]+)/"\+" . tabify($1)/e; + } + } + +# check we are in a valid C source file if not then ignore this hunk + next if ($realfile !~ /\.(h|c)$/); + +# check for unusual line ending [ or ( + if ($line =~ /^\+.*([\[\(])\s*$/) { + CHK("OPEN_ENDED_LINE", + "Lines should not end with a '$1'\n" . $herecurr); + } + +# check if this appears to be the start function declaration, save the name + if ($sline =~ /^\+\{\s*$/ && + $prevline =~ /^\+(?:(?:(?:$Storage|$Inline)\s*)*\s*$Type\s*)?($Ident)\(/) { + $context_function = $1; + } + +# check if this appears to be the end of function declaration + if ($sline =~ /^\+\}\s*$/) { + undef $context_function; + } + +# check indentation of any line with a bare else +# (but not if it is a multiple line "if (foo) return bar; else return baz;") +# if the previous line is a break or return and is indented 1 tab more... + if ($sline =~ /^\+([\t]+)(?:}[ \t]*)?else(?:[ \t]*{)?\s*$/) { + my $tabs = length($1) + 1; + if ($prevline =~ /^\+\t{$tabs,$tabs}break\b/ || + ($prevline =~ /^\+\t{$tabs,$tabs}return\b/ && + defined $lines[$linenr] && + $lines[$linenr] !~ /^[ \+]\t{$tabs,$tabs}return/)) { + WARN("UNNECESSARY_ELSE", + "else is not generally useful after a break or return\n" . $hereprev); + } + } + +# check indentation of a line with a break; +# if the previous line is a goto or return and is indented the same # of tabs + if ($sline =~ /^\+([\t]+)break\s*;\s*$/) { + my $tabs = $1; + if ($prevline =~ /^\+$tabs(?:goto|return)\b/) { + WARN("UNNECESSARY_BREAK", + "break is not useful after a goto or return\n" . $hereprev); + } + } + +# check for RCS/CVS revision markers + if ($rawline =~ /^\+.*\$(Revision|Log|Id)(?:\$|)/) { + WARN("CVS_KEYWORD", + "CVS style keyword markers, these will _not_ be updated\n". $herecurr); + } + +# check for old HOTPLUG __dev<foo> section markings + if ($line =~ /\b(__dev(init|exit)(data|const|))\b/) { + WARN("HOTPLUG_SECTION", + "Using $1 is unnecessary\n" . $herecurr); + } + +# Check for potential 'bare' types + my ($stat, $cond, $line_nr_next, $remain_next, $off_next, + $realline_next); +#print "LINE<$line>\n"; + if ($linenr > $suppress_statement && + $realcnt && $sline =~ /.\s*\S/) { + ($stat, $cond, $line_nr_next, $remain_next, $off_next) = + ctx_statement_block($linenr, $realcnt, 0); + $stat =~ s/\n./\n /g; + $cond =~ s/\n./\n /g; + +#print "linenr<$linenr> <$stat>\n"; + # If this statement has no statement boundaries within + # it there is no point in retrying a statement scan + # until we hit end of it. + my $frag = $stat; $frag =~ s/;+\s*$//; + if ($frag !~ /(?:{|;)/) { +#print "skip<$line_nr_next>\n"; + $suppress_statement = $line_nr_next; + } + + # Find the real next line. + $realline_next = $line_nr_next; + if (defined $realline_next && + (!defined $lines[$realline_next - 1] || + substr($lines[$realline_next - 1], $off_next) =~ /^\s*$/)) { + $realline_next++; + } + + my $s = $stat; + $s =~ s/{.*$//s; + + # Ignore goto labels. + if ($s =~ /$Ident:\*$/s) { + + # Ignore functions being called + } elsif ($s =~ /^.\s*$Ident\s*\(/s) { + + } elsif ($s =~ /^.\s*else\b/s) { + + # declarations always start with types + } elsif ($prev_values eq 'E' && $s =~ /^.\s*(?:$Storage\s+)?(?:$Inline\s+)?(?:const\s+)?((?:\s*$Ident)+?)\b(?:\s+$Sparse)?\s*\**\s*(?:$Ident|\(\*[^\)]*\))(?:\s*$Modifier)?\s*(?:;|=|,|\()/s) { + my $type = $1; + $type =~ s/\s+/ /g; + possible($type, "A:" . $s); + + # definitions in global scope can only start with types + } elsif ($s =~ /^.(?:$Storage\s+)?(?:$Inline\s+)?(?:const\s+)?($Ident)\b\s*(?!:)/s) { + possible($1, "B:" . $s); + } + + # any (foo ... *) is a pointer cast, and foo is a type + while ($s =~ /\(($Ident)(?:\s+$Sparse)*[\s\*]+\s*\)/sg) { + possible($1, "C:" . $s); + } + + # Check for any sort of function declaration. + # int foo(something bar, other baz); + # void (*store_gdt)(x86_descr_ptr *); + if ($prev_values eq 'E' && $s =~ /^(.(?:typedef\s*)?(?:(?:$Storage|$Inline)\s*)*\s*$Type\s*(?:\b$Ident|\(\*\s*$Ident\))\s*)\(/s) { + my ($name_len) = length($1); + + my $ctx = $s; + substr($ctx, 0, $name_len + 1, ''); + $ctx =~ s/\)[^\)]*$//; + + for my $arg (split(/\s*,\s*/, $ctx)) { + if ($arg =~ /^(?:const\s+)?($Ident)(?:\s+$Sparse)*\s*\**\s*(:?\b$Ident)?$/s || $arg =~ /^($Ident)$/s) { + + possible($1, "D:" . $s); + } + } + } + + } + +# +# Checks which may be anchored in the context. +# + +# Check for switch () and associated case and default +# statements should be at the same indent. + if ($line=~/\bswitch\s*\(.*\)/) { + my $err = ''; + my $sep = ''; + my @ctx = ctx_block_outer($linenr, $realcnt); + shift(@ctx); + for my $ctx (@ctx) { + my ($clen, $cindent) = line_stats($ctx); + if ($ctx =~ /^\+\s*(case\s+|default:)/ && + $indent != $cindent) { + $err .= "$sep$ctx\n"; + $sep = ''; + } else { + $sep = "[...]\n"; + } + } + if ($err ne '') { + ERROR("SWITCH_CASE_INDENT_LEVEL", + "switch and case should be at the same indent\n$hereline$err"); + } + } + +# if/while/etc brace do not go on next line, unless defining a do while loop, +# or if that brace on the next line is for something else + if ($line =~ /(.*)\b((?:if|while|for|switch|(?:[a-z_]+|)for_each[a-z_]+)\s*\(|do\b|else\b)/ && $line !~ /^.\s*\#/) { + my $pre_ctx = "$1$2"; + + my ($level, @ctx) = ctx_statement_level($linenr, $realcnt, 0); + + if ($line =~ /^\+\t{6,}/) { + WARN("DEEP_INDENTATION", + "Too many leading tabs - consider code refactoring\n" . $herecurr); + } + + my $ctx_cnt = $realcnt - $#ctx - 1; + my $ctx = join("\n", @ctx); + + my $ctx_ln = $linenr; + my $ctx_skip = $realcnt; + + while ($ctx_skip > $ctx_cnt || ($ctx_skip == $ctx_cnt && + defined $lines[$ctx_ln - 1] && + $lines[$ctx_ln - 1] =~ /^-/)) { + ##print "SKIP<$ctx_skip> CNT<$ctx_cnt>\n"; + $ctx_skip-- if (!defined $lines[$ctx_ln - 1] || $lines[$ctx_ln - 1] !~ /^-/); + $ctx_ln++; + } + + #print "realcnt<$realcnt> ctx_cnt<$ctx_cnt>\n"; + #print "pre<$pre_ctx>\nline<$line>\nctx<$ctx>\nnext<$lines[$ctx_ln - 1]>\n"; + + if ($ctx !~ /{\s*/ && defined($lines[$ctx_ln - 1]) && $lines[$ctx_ln - 1] =~ /^\+\s*{/) { + ERROR("OPEN_BRACE", + "that open brace { should be on the previous line\n" . + "$here\n$ctx\n$rawlines[$ctx_ln - 1]\n"); + } + if ($level == 0 && $pre_ctx !~ /}\s*while\s*\($/ && + $ctx =~ /\)\s*\;\s*$/ && + defined $lines[$ctx_ln - 1]) + { + my ($nlength, $nindent) = line_stats($lines[$ctx_ln - 1]); + if ($nindent > $indent) { + WARN("TRAILING_SEMICOLON", + "trailing semicolon indicates no statements, indent implies otherwise\n" . + "$here\n$ctx\n$rawlines[$ctx_ln - 1]\n"); + } + } + } + +# Check relative indent for conditionals and blocks. + if ($line =~ /\b(?:(?:if|while|for|(?:[a-z_]+|)for_each[a-z_]+)\s*\(|(?:do|else)\b)/ && $line !~ /^.\s*#/ && $line !~ /\}\s*while\s*/) { + ($stat, $cond, $line_nr_next, $remain_next, $off_next) = + ctx_statement_block($linenr, $realcnt, 0) + if (!defined $stat); + my ($s, $c) = ($stat, $cond); + + substr($s, 0, length($c), ''); + + # remove inline comments + $s =~ s/$;/ /g; + $c =~ s/$;/ /g; + + # Find out how long the conditional actually is. + my @newlines = ($c =~ /\n/gs); + my $cond_lines = 1 + $#newlines; + + # Make sure we remove the line prefixes as we have + # none on the first line, and are going to readd them + # where necessary. + $s =~ s/\n./\n/gs; + while ($s =~ /\n\s+\\\n/) { + $cond_lines += $s =~ s/\n\s+\\\n/\n/g; + } + + # We want to check the first line inside the block + # starting at the end of the conditional, so remove: + # 1) any blank line termination + # 2) any opening brace { on end of the line + # 3) any do (...) { + my $continuation = 0; + my $check = 0; + $s =~ s/^.*\bdo\b//; + $s =~ s/^\s*{//; + if ($s =~ s/^\s*\\//) { + $continuation = 1; + } + if ($s =~ s/^\s*?\n//) { + $check = 1; + $cond_lines++; + } + + # Also ignore a loop construct at the end of a + # preprocessor statement. + if (($prevline =~ /^.\s*#\s*define\s/ || + $prevline =~ /\\\s*$/) && $continuation == 0) { + $check = 0; + } + + my $cond_ptr = -1; + $continuation = 0; + while ($cond_ptr != $cond_lines) { + $cond_ptr = $cond_lines; + + # If we see an #else/#elif then the code + # is not linear. + if ($s =~ /^\s*\#\s*(?:else|elif)/) { + $check = 0; + } + + # Ignore: + # 1) blank lines, they should be at 0, + # 2) preprocessor lines, and + # 3) labels. + if ($continuation || + $s =~ /^\s*?\n/ || + $s =~ /^\s*#\s*?/ || + $s =~ /^\s*$Ident\s*:/) { + $continuation = ($s =~ /^.*?\\\n/) ? 1 : 0; + if ($s =~ s/^.*?\n//) { + $cond_lines++; + } + } + } + + my (undef, $sindent) = line_stats("+" . $s); + my $stat_real = raw_line($linenr, $cond_lines); + + # Check if either of these lines are modified, else + # this is not this patch's fault. + if (!defined($stat_real) || + $stat !~ /^\+/ && $stat_real !~ /^\+/) { + $check = 0; + } + if (defined($stat_real) && $cond_lines > 1) { + $stat_real = "[...]\n$stat_real"; + } + + #print "line<$line> prevline<$prevline> indent<$indent> sindent<$sindent> check<$check> continuation<$continuation> s<$s> cond_lines<$cond_lines> stat_real<$stat_real> stat<$stat>\n"; + + if ($check && $s ne '' && + (($sindent % $tabsize) != 0 || + ($sindent < $indent) || + ($sindent == $indent && + ($s !~ /^\s*(?:\}|\{|else\b)/)) || + ($sindent > $indent + $tabsize))) { + WARN("SUSPECT_CODE_INDENT", + "suspect code indent for conditional statements ($indent, $sindent)\n" . $herecurr . "$stat_real\n"); + } + } + + # Track the 'values' across context and added lines. + my $opline = $line; $opline =~ s/^./ /; + my ($curr_values, $curr_vars) = + annotate_values($opline . "\n", $prev_values); + $curr_values = $prev_values . $curr_values; + if ($dbg_values) { + my $outline = $opline; $outline =~ s/\t/ /g; + print "$linenr > .$outline\n"; + print "$linenr > $curr_values\n"; + print "$linenr > $curr_vars\n"; + } + $prev_values = substr($curr_values, -1); + +#ignore lines not being added + next if ($line =~ /^[^\+]/); + +# check for self assignments used to avoid compiler warnings +# e.g.: int foo = foo, *bar = NULL; +# struct foo bar = *(&(bar)); + if ($line =~ /^\+\s*(?:$Declare)?([A-Za-z_][A-Za-z\d_]*)\s*=/) { + my $var = $1; + if ($line =~ /^\+\s*(?:$Declare)?$var\s*=\s*(?:$var|\*\s*\(?\s*&\s*\(?\s*$var\s*\)?\s*\)?)\s*[;,]/) { + WARN("SELF_ASSIGNMENT", + "Do not use self-assignments to avoid compiler warnings\n" . $herecurr); + } + } + +# check for dereferences that span multiple lines + if ($prevline =~ /^\+.*$Lval\s*(?:\.|->)\s*$/ && + $line =~ /^\+\s*(?!\#\s*(?!define\s+|if))\s*$Lval/) { + $prevline =~ /($Lval\s*(?:\.|->))\s*$/; + my $ref = $1; + $line =~ /^.\s*($Lval)/; + $ref .= $1; + $ref =~ s/\s//g; + WARN("MULTILINE_DEREFERENCE", + "Avoid multiple line dereference - prefer '$ref'\n" . $hereprev); + } + +# check for declarations of signed or unsigned without int + while ($line =~ m{\b($Declare)\s*(?!char\b|short\b|int\b|long\b)\s*($Ident)?\s*[=,;\[\)\(]}g) { + my $type = $1; + my $var = $2; + $var = "" if (!defined $var); + if ($type =~ /^(?:(?:$Storage|$Inline|$Attribute)\s+)*((?:un)?signed)((?:\s*\*)*)\s*$/) { + my $sign = $1; + my $pointer = $2; + + $pointer = "" if (!defined $pointer); + + if (WARN("UNSPECIFIED_INT", + "Prefer '" . trim($sign) . " int" . rtrim($pointer) . "' to bare use of '$sign" . rtrim($pointer) . "'\n" . $herecurr) && + $fix) { + my $decl = trim($sign) . " int "; + my $comp_pointer = $pointer; + $comp_pointer =~ s/\s//g; + $decl .= $comp_pointer; + $decl = rtrim($decl) if ($var eq ""); + $fixed[$fixlinenr] =~ s@\b$sign\s*\Q$pointer\E\s*$var\b@$decl$var@; + } + } + } + +# TEST: allow direct testing of the type matcher. + if ($dbg_type) { + if ($line =~ /^.\s*$Declare\s*$/) { + ERROR("TEST_TYPE", + "TEST: is type\n" . $herecurr); + } elsif ($dbg_type > 1 && $line =~ /^.+($Declare)/) { + ERROR("TEST_NOT_TYPE", + "TEST: is not type ($1 is)\n". $herecurr); + } + next; + } +# TEST: allow direct testing of the attribute matcher. + if ($dbg_attr) { + if ($line =~ /^.\s*$Modifier\s*$/) { + ERROR("TEST_ATTR", + "TEST: is attr\n" . $herecurr); + } elsif ($dbg_attr > 1 && $line =~ /^.+($Modifier)/) { + ERROR("TEST_NOT_ATTR", + "TEST: is not attr ($1 is)\n". $herecurr); + } + next; + } + +# check for initialisation to aggregates open brace on the next line + if ($line =~ /^.\s*{/ && + $prevline =~ /(?:^|[^=])=\s*$/) { + if (ERROR("OPEN_BRACE", + "that open brace { should be on the previous line\n" . $hereprev) && + $fix && $prevline =~ /^\+/ && $line =~ /^\+/) { + fix_delete_line($fixlinenr - 1, $prevrawline); + fix_delete_line($fixlinenr, $rawline); + my $fixedline = $prevrawline; + $fixedline =~ s/\s*=\s*$/ = {/; + fix_insert_line($fixlinenr, $fixedline); + $fixedline = $line; + $fixedline =~ s/^(.\s*)\{\s*/$1/; + fix_insert_line($fixlinenr, $fixedline); + } + } + +# +# Checks which are anchored on the added line. +# + +# check for malformed paths in #include statements (uses RAW line) + if ($rawline =~ m{^.\s*\#\s*include\s+[<"](.*)[">]}) { + my $path = $1; + if ($path =~ m{//}) { + ERROR("MALFORMED_INCLUDE", + "malformed #include filename\n" . $herecurr); + } + if ($path =~ "^uapi/" && $realfile =~ m@\binclude/uapi/@) { + ERROR("UAPI_INCLUDE", + "No #include in ...include/uapi/... should use a uapi/ path prefix\n" . $herecurr); + } + } + +# no C99 // comments + if ($line =~ m{//}) { + if (ERROR("C99_COMMENTS", + "do not use C99 // comments\n" . $herecurr) && + $fix) { + my $line = $fixed[$fixlinenr]; + if ($line =~ /\/\/(.*)$/) { + my $comment = trim($1); + $fixed[$fixlinenr] =~ s@\/\/(.*)$@/\* $comment \*/@; + } + } + } + # Remove C99 comments. + $line =~ s@//.*@@; + $opline =~ s@//.*@@; + +# EXPORT_SYMBOL should immediately follow the thing it is exporting, consider +# the whole statement. +#print "APW <$lines[$realline_next - 1]>\n"; + if (defined $realline_next && + exists $lines[$realline_next - 1] && + !defined $suppress_export{$realline_next} && + ($lines[$realline_next - 1] =~ /EXPORT_SYMBOL.*\((.*)\)/ || + $lines[$realline_next - 1] =~ /EXPORT_UNUSED_SYMBOL.*\((.*)\)/)) { + # Handle definitions which produce identifiers with + # a prefix: + # XXX(foo); + # EXPORT_SYMBOL(something_foo); + my $name = $1; + if ($stat =~ /^(?:.\s*}\s*\n)?.([A-Z_]+)\s*\(\s*($Ident)/ && + $name =~ /^${Ident}_$2/) { +#print "FOO C name<$name>\n"; + $suppress_export{$realline_next} = 1; + + } elsif ($stat !~ /(?: + \n.}\s*$| + ^.DEFINE_$Ident\(\Q$name\E\)| + ^.DECLARE_$Ident\(\Q$name\E\)| + ^.LIST_HEAD\(\Q$name\E\)| + ^.(?:$Storage\s+)?$Type\s*\(\s*\*\s*\Q$name\E\s*\)\s*\(| + \b\Q$name\E(?:\s+$Attribute)*\s*(?:;|=|\[|\() + )/x) { +#print "FOO A<$lines[$realline_next - 1]> stat<$stat> name<$name>\n"; + $suppress_export{$realline_next} = 2; + } else { + $suppress_export{$realline_next} = 1; + } + } + if (!defined $suppress_export{$linenr} && + $prevline =~ /^.\s*$/ && + ($line =~ /EXPORT_SYMBOL.*\((.*)\)/ || + $line =~ /EXPORT_UNUSED_SYMBOL.*\((.*)\)/)) { +#print "FOO B <$lines[$linenr - 1]>\n"; + $suppress_export{$linenr} = 2; + } + if (defined $suppress_export{$linenr} && + $suppress_export{$linenr} == 2) { + WARN("EXPORT_SYMBOL", + "EXPORT_SYMBOL(foo); should immediately follow its function/variable\n" . $herecurr); + } + +# check for global initialisers. + if ($line =~ /^\+$Type\s*$Ident(?:\s+$Modifier)*\s*=\s*($zero_initializer)\s*;/) { + if (ERROR("GLOBAL_INITIALISERS", + "do not initialise globals to $1\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/(^.$Type\s*$Ident(?:\s+$Modifier)*)\s*=\s*$zero_initializer\s*;/$1;/; + } + } +# check for static initialisers. + if ($line =~ /^\+.*\bstatic\s.*=\s*($zero_initializer)\s*;/) { + if (ERROR("INITIALISED_STATIC", + "do not initialise statics to $1\n" . + $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/(\bstatic\s.*?)\s*=\s*$zero_initializer\s*;/$1;/; + } + } + +# check for misordered declarations of char/short/int/long with signed/unsigned + while ($sline =~ m{(\b$TypeMisordered\b)}g) { + my $tmp = trim($1); + WARN("MISORDERED_TYPE", + "type '$tmp' should be specified in [[un]signed] [short|int|long|long long] order\n" . $herecurr); + } + +# check for unnecessary <signed> int declarations of short/long/long long + while ($sline =~ m{\b($TypeMisordered(\s*\*)*|$C90_int_types)\b}g) { + my $type = trim($1); + next if ($type !~ /\bint\b/); + next if ($type !~ /\b(?:short|long\s+long|long)\b/); + my $new_type = $type; + $new_type =~ s/\b\s*int\s*\b/ /; + $new_type =~ s/\b\s*(?:un)?signed\b\s*/ /; + $new_type =~ s/^const\s+//; + $new_type = "unsigned $new_type" if ($type =~ /\bunsigned\b/); + $new_type = "const $new_type" if ($type =~ /^const\b/); + $new_type =~ s/\s+/ /g; + $new_type = trim($new_type); + if (WARN("UNNECESSARY_INT", + "Prefer '$new_type' over '$type' as the int is unnecessary\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\b\Q$type\E\b/$new_type/; + } + } + +# check for static const char * arrays. + if ($line =~ /\bstatic\s+const\s+char\s*\*\s*(\w+)\s*\[\s*\]\s*=\s*/) { + WARN("STATIC_CONST_CHAR_ARRAY", + "static const char * array should probably be static const char * const\n" . + $herecurr); + } + +# check for initialized const char arrays that should be static const + if ($line =~ /^\+\s*const\s+(char|unsigned\s+char|_*u8|(?:[us]_)?int8_t)\s+\w+\s*\[\s*(?:\w+\s*)?\]\s*=\s*"/) { + if (WARN("STATIC_CONST_CHAR_ARRAY", + "const array should probably be static const\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/(^.\s*)const\b/${1}static const/; + } + } + +# check for static char foo[] = "bar" declarations. + if ($line =~ /\bstatic\s+char\s+(\w+)\s*\[\s*\]\s*=\s*"/) { + WARN("STATIC_CONST_CHAR_ARRAY", + "static char array declaration should probably be static const char\n" . + $herecurr); + } + +# check for const <foo> const where <foo> is not a pointer or array type + if ($sline =~ /\bconst\s+($BasicType)\s+const\b/) { + my $found = $1; + if ($sline =~ /\bconst\s+\Q$found\E\s+const\b\s*\*/) { + WARN("CONST_CONST", + "'const $found const *' should probably be 'const $found * const'\n" . $herecurr); + } elsif ($sline !~ /\bconst\s+\Q$found\E\s+const\s+\w+\s*\[/) { + WARN("CONST_CONST", + "'const $found const' should probably be 'const $found'\n" . $herecurr); + } + } + +# check for non-global char *foo[] = {"bar", ...} declarations. + if ($line =~ /^.\s+(?:static\s+|const\s+)?char\s+\*\s*\w+\s*\[\s*\]\s*=\s*\{/) { + WARN("STATIC_CONST_CHAR_ARRAY", + "char * array declaration might be better as static const\n" . + $herecurr); + } + +# check for sizeof(foo)/sizeof(foo[0]) that could be ARRAY_SIZE(foo) + if ($line =~ m@\bsizeof\s*\(\s*($Lval)\s*\)@) { + my $array = $1; + if ($line =~ m@\b(sizeof\s*\(\s*\Q$array\E\s*\)\s*/\s*sizeof\s*\(\s*\Q$array\E\s*\[\s*0\s*\]\s*\))@) { + my $array_div = $1; + if (WARN("ARRAY_SIZE", + "Prefer ARRAY_SIZE($array)\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\Q$array_div\E/ARRAY_SIZE($array)/; + } + } + } + +# check for function declarations without arguments like "int foo()" + if ($line =~ /(\b$Type\s*$Ident)\s*\(\s*\)/) { + if (ERROR("FUNCTION_WITHOUT_ARGS", + "Bad function definition - $1() should probably be $1(void)\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/(\b($Type)\s+($Ident))\s*\(\s*\)/$2 $3(void)/; + } + } + +# check for new typedefs, only function parameters and sparse annotations +# make sense. + if ($line =~ /\btypedef\s/ && + $line !~ /\btypedef\s+$Type\s*\(\s*\*?$Ident\s*\)\s*\(/ && + $line !~ /\btypedef\s+$Type\s+$Ident\s*\(/ && + $line !~ /\b$typeTypedefs\b/ && + $line !~ /\b__bitwise\b/) { + WARN("NEW_TYPEDEFS", + "do not add new typedefs\n" . $herecurr); + } + +# * goes on variable not on type + # (char*[ const]) + while ($line =~ m{(\($NonptrType(\s*(?:$Modifier\b\s*|\*\s*)+)\))}g) { + #print "AA<$1>\n"; + my ($ident, $from, $to) = ($1, $2, $2); + + # Should start with a space. + $to =~ s/^(\S)/ $1/; + # Should not end with a space. + $to =~ s/\s+$//; + # '*'s should not have spaces between. + while ($to =~ s/\*\s+\*/\*\*/) { + } + +## print "1: from<$from> to<$to> ident<$ident>\n"; + if ($from ne $to) { + if (ERROR("POINTER_LOCATION", + "\"(foo$from)\" should be \"(foo$to)\"\n" . $herecurr) && + $fix) { + my $sub_from = $ident; + my $sub_to = $ident; + $sub_to =~ s/\Q$from\E/$to/; + $fixed[$fixlinenr] =~ + s@\Q$sub_from\E@$sub_to@; + } + } + } + while ($line =~ m{(\b$NonptrType(\s*(?:$Modifier\b\s*|\*\s*)+)($Ident))}g) { + #print "BB<$1>\n"; + my ($match, $from, $to, $ident) = ($1, $2, $2, $3); + + # Should start with a space. + $to =~ s/^(\S)/ $1/; + # Should not end with a space. + $to =~ s/\s+$//; + # '*'s should not have spaces between. + while ($to =~ s/\*\s+\*/\*\*/) { + } + # Modifiers should have spaces. + $to =~ s/(\b$Modifier$)/$1 /; + +## print "2: from<$from> to<$to> ident<$ident>\n"; + if ($from ne $to && $ident !~ /^$Modifier$/) { + if (ERROR("POINTER_LOCATION", + "\"foo${from}bar\" should be \"foo${to}bar\"\n" . $herecurr) && + $fix) { + + my $sub_from = $match; + my $sub_to = $match; + $sub_to =~ s/\Q$from\E/$to/; + $fixed[$fixlinenr] =~ + s@\Q$sub_from\E@$sub_to@; + } + } + } + +# avoid BUG() or BUG_ON() + if ($line =~ /\b(?:BUG|BUG_ON)\b/) { + my $msg_level = \&WARN; + $msg_level = \&CHK if ($file); + &{$msg_level}("AVOID_BUG", + "Avoid crashing the kernel - try using WARN_ON & recovery code rather than BUG() or BUG_ON()\n" . $herecurr); + } + +# avoid LINUX_VERSION_CODE + if ($line =~ /\bLINUX_VERSION_CODE\b/) { + WARN("LINUX_VERSION_CODE", + "LINUX_VERSION_CODE should be avoided, code should be for the version to which it is merged\n" . $herecurr); + } + +# check for uses of printk_ratelimit + if ($line =~ /\bprintk_ratelimit\s*\(/) { + WARN("PRINTK_RATELIMITED", + "Prefer printk_ratelimited or pr_<level>_ratelimited to printk_ratelimit\n" . $herecurr); + } + +# printk should use KERN_* levels + if ($line =~ /\bprintk\s*\(\s*(?!KERN_[A-Z]+\b)/) { + WARN("PRINTK_WITHOUT_KERN_LEVEL", + "printk() should include KERN_<LEVEL> facility level\n" . $herecurr); + } + + if ($line =~ /\bprintk\s*\(\s*KERN_([A-Z]+)/) { + my $orig = $1; + my $level = lc($orig); + $level = "warn" if ($level eq "warning"); + my $level2 = $level; + $level2 = "dbg" if ($level eq "debug"); + WARN("PREFER_PR_LEVEL", + "Prefer [subsystem eg: netdev]_$level2([subsystem]dev, ... then dev_$level2(dev, ... then pr_$level(... to printk(KERN_$orig ...\n" . $herecurr); + } + + if ($line =~ /\bdev_printk\s*\(\s*KERN_([A-Z]+)/) { + my $orig = $1; + my $level = lc($orig); + $level = "warn" if ($level eq "warning"); + $level = "dbg" if ($level eq "debug"); + WARN("PREFER_DEV_LEVEL", + "Prefer dev_$level(... to dev_printk(KERN_$orig, ...\n" . $herecurr); + } + +# trace_printk should not be used in production code. + if ($line =~ /\b(trace_printk|trace_puts|ftrace_vprintk)\s*\(/) { + WARN("TRACE_PRINTK", + "Do not use $1() in production code (this can be ignored if built only with a debug config option)\n" . $herecurr); + } + +# ENOSYS means "bad syscall nr" and nothing else. This will have a small +# number of false positives, but assembly files are not checked, so at +# least the arch entry code will not trigger this warning. + if ($line =~ /\bENOSYS\b/) { + WARN("ENOSYS", + "ENOSYS means 'invalid syscall nr' and nothing else\n" . $herecurr); + } + +# ENOTSUPP is not a standard error code and should be avoided in new patches. +# Folks usually mean EOPNOTSUPP (also called ENOTSUP), when they type ENOTSUPP. +# Similarly to ENOSYS warning a small number of false positives is expected. + if (!$file && $line =~ /\bENOTSUPP\b/) { + if (WARN("ENOTSUPP", + "ENOTSUPP is not a SUSV4 error code, prefer EOPNOTSUPP\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\bENOTSUPP\b/EOPNOTSUPP/; + } + } + +# function brace can't be on same line, except for #defines of do while, +# or if closed on same line + if ($perl_version_ok && + $sline =~ /$Type\s*$Ident\s*$balanced_parens\s*\{/ && + $sline !~ /\#\s*define\b.*do\s*\{/ && + $sline !~ /}/) { + if (ERROR("OPEN_BRACE", + "open brace '{' following function definitions go on the next line\n" . $herecurr) && + $fix) { + fix_delete_line($fixlinenr, $rawline); + my $fixed_line = $rawline; + $fixed_line =~ /(^..*$Type\s*$Ident\(.*\)\s*)\{(.*)$/; + my $line1 = $1; + my $line2 = $2; + fix_insert_line($fixlinenr, ltrim($line1)); + fix_insert_line($fixlinenr, "\+{"); + if ($line2 !~ /^\s*$/) { + fix_insert_line($fixlinenr, "\+\t" . trim($line2)); + } + } + } + +# open braces for enum, union and struct go on the same line. + if ($line =~ /^.\s*{/ && + $prevline =~ /^.\s*(?:typedef\s+)?(enum|union|struct)(?:\s+$Ident)?\s*$/) { + if (ERROR("OPEN_BRACE", + "open brace '{' following $1 go on the same line\n" . $hereprev) && + $fix && $prevline =~ /^\+/ && $line =~ /^\+/) { + fix_delete_line($fixlinenr - 1, $prevrawline); + fix_delete_line($fixlinenr, $rawline); + my $fixedline = rtrim($prevrawline) . " {"; + fix_insert_line($fixlinenr, $fixedline); + $fixedline = $rawline; + $fixedline =~ s/^(.\s*)\{\s*/$1\t/; + if ($fixedline !~ /^\+\s*$/) { + fix_insert_line($fixlinenr, $fixedline); + } + } + } + +# missing space after union, struct or enum definition + if ($line =~ /^.\s*(?:typedef\s+)?(enum|union|struct)(?:\s+$Ident){1,2}[=\{]/) { + if (WARN("SPACING", + "missing space after $1 definition\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ + s/^(.\s*(?:typedef\s+)?(?:enum|union|struct)(?:\s+$Ident){1,2})([=\{])/$1 $2/; + } + } + +# Function pointer declarations +# check spacing between type, funcptr, and args +# canonical declaration is "type (*funcptr)(args...)" + if ($line =~ /^.\s*($Declare)\((\s*)\*(\s*)($Ident)(\s*)\)(\s*)\(/) { + my $declare = $1; + my $pre_pointer_space = $2; + my $post_pointer_space = $3; + my $funcname = $4; + my $post_funcname_space = $5; + my $pre_args_space = $6; + +# the $Declare variable will capture all spaces after the type +# so check it for a missing trailing missing space but pointer return types +# don't need a space so don't warn for those. + my $post_declare_space = ""; + if ($declare =~ /(\s+)$/) { + $post_declare_space = $1; + $declare = rtrim($declare); + } + if ($declare !~ /\*$/ && $post_declare_space =~ /^$/) { + WARN("SPACING", + "missing space after return type\n" . $herecurr); + $post_declare_space = " "; + } + +# unnecessary space "type (*funcptr)(args...)" +# This test is not currently implemented because these declarations are +# equivalent to +# int foo(int bar, ...) +# and this is form shouldn't/doesn't generate a checkpatch warning. +# +# elsif ($declare =~ /\s{2,}$/) { +# WARN("SPACING", +# "Multiple spaces after return type\n" . $herecurr); +# } + +# unnecessary space "type ( *funcptr)(args...)" + if (defined $pre_pointer_space && + $pre_pointer_space =~ /^\s/) { + WARN("SPACING", + "Unnecessary space after function pointer open parenthesis\n" . $herecurr); + } + +# unnecessary space "type (* funcptr)(args...)" + if (defined $post_pointer_space && + $post_pointer_space =~ /^\s/) { + WARN("SPACING", + "Unnecessary space before function pointer name\n" . $herecurr); + } + +# unnecessary space "type (*funcptr )(args...)" + if (defined $post_funcname_space && + $post_funcname_space =~ /^\s/) { + WARN("SPACING", + "Unnecessary space after function pointer name\n" . $herecurr); + } + +# unnecessary space "type (*funcptr) (args...)" + if (defined $pre_args_space && + $pre_args_space =~ /^\s/) { + WARN("SPACING", + "Unnecessary space before function pointer arguments\n" . $herecurr); + } + + if (show_type("SPACING") && $fix) { + $fixed[$fixlinenr] =~ + s/^(.\s*)$Declare\s*\(\s*\*\s*$Ident\s*\)\s*\(/$1 . $declare . $post_declare_space . '(*' . $funcname . ')('/ex; + } + } + +# check for spacing round square brackets; allowed: +# 1. with a type on the left -- int [] a; +# 2. at the beginning of a line for slice initialisers -- [0...10] = 5, +# 3. inside a curly brace -- = { [0...10] = 5 } + while ($line =~ /(.*?\s)\[/g) { + my ($where, $prefix) = ($-[1], $1); + if ($prefix !~ /$Type\s+$/ && + ($where != 0 || $prefix !~ /^.\s+$/) && + $prefix !~ /[{,:]\s+$/) { + if (ERROR("BRACKET_SPACE", + "space prohibited before open square bracket '['\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ + s/^(\+.*?)\s+\[/$1\[/; + } + } + } + +# check for spaces between functions and their parentheses. + while ($line =~ /($Ident)\s+\(/g) { + my $name = $1; + my $ctx_before = substr($line, 0, $-[1]); + my $ctx = "$ctx_before$name"; + + # Ignore those directives where spaces _are_ permitted. + if ($name =~ /^(?: + if|for|while|switch|return|case| + volatile|__volatile__| + __attribute__|format|__extension__| + asm|__asm__)$/x) + { + # cpp #define statements have non-optional spaces, ie + # if there is a space between the name and the open + # parenthesis it is simply not a parameter group. + } elsif ($ctx_before =~ /^.\s*\#\s*define\s*$/) { + + # cpp #elif statement condition may start with a ( + } elsif ($ctx =~ /^.\s*\#\s*elif\s*$/) { + + # If this whole things ends with a type its most + # likely a typedef for a function. + } elsif ($ctx =~ /$Type$/) { + + } else { + if (WARN("SPACING", + "space prohibited between function name and open parenthesis '('\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ + s/\b$name\s+\(/$name\(/; + } + } + } + +# Check operator spacing. + if (!($line=~/\#\s*include/)) { + my $fixed_line = ""; + my $line_fixed = 0; + + my $ops = qr{ + <<=|>>=|<=|>=|==|!=| + \+=|-=|\*=|\/=|%=|\^=|\|=|&=| + =>|->|<<|>>|<|>|=|!|~| + &&|\|\||,|\^|\+\+|--|&|\||\+|-|\*|\/|%| + \?:|\?|: + }x; + my @elements = split(/($ops|;)/, $opline); + +## print("element count: <" . $#elements . ">\n"); +## foreach my $el (@elements) { +## print("el: <$el>\n"); +## } + + my @fix_elements = (); + my $off = 0; + + foreach my $el (@elements) { + push(@fix_elements, substr($rawline, $off, length($el))); + $off += length($el); + } + + $off = 0; + + my $blank = copy_spacing($opline); + my $last_after = -1; + + for (my $n = 0; $n < $#elements; $n += 2) { + + my $good = $fix_elements[$n] . $fix_elements[$n + 1]; + +## print("n: <$n> good: <$good>\n"); + + $off += length($elements[$n]); + + # Pick up the preceding and succeeding characters. + my $ca = substr($opline, 0, $off); + my $cc = ''; + if (length($opline) >= ($off + length($elements[$n + 1]))) { + $cc = substr($opline, $off + length($elements[$n + 1])); + } + my $cb = "$ca$;$cc"; + + my $a = ''; + $a = 'V' if ($elements[$n] ne ''); + $a = 'W' if ($elements[$n] =~ /\s$/); + $a = 'C' if ($elements[$n] =~ /$;$/); + $a = 'B' if ($elements[$n] =~ /(\[|\()$/); + $a = 'O' if ($elements[$n] eq ''); + $a = 'E' if ($ca =~ /^\s*$/); + + my $op = $elements[$n + 1]; + + my $c = ''; + if (defined $elements[$n + 2]) { + $c = 'V' if ($elements[$n + 2] ne ''); + $c = 'W' if ($elements[$n + 2] =~ /^\s/); + $c = 'C' if ($elements[$n + 2] =~ /^$;/); + $c = 'B' if ($elements[$n + 2] =~ /^(\)|\]|;)/); + $c = 'O' if ($elements[$n + 2] eq ''); + $c = 'E' if ($elements[$n + 2] =~ /^\s*\\$/); + } else { + $c = 'E'; + } + + my $ctx = "${a}x${c}"; + + my $at = "(ctx:$ctx)"; + + my $ptr = substr($blank, 0, $off) . "^"; + my $hereptr = "$hereline$ptr\n"; + + # Pull out the value of this operator. + my $op_type = substr($curr_values, $off + 1, 1); + + # Get the full operator variant. + my $opv = $op . substr($curr_vars, $off, 1); + + # Ignore operators passed as parameters. + if ($op_type ne 'V' && + $ca =~ /\s$/ && $cc =~ /^\s*[,\)]/) { + +# # Ignore comments +# } elsif ($op =~ /^$;+$/) { + + # ; should have either the end of line or a space or \ after it + } elsif ($op eq ';') { + if ($ctx !~ /.x[WEBC]/ && + $cc !~ /^\\/ && $cc !~ /^;/) { + if (ERROR("SPACING", + "space required after that '$op' $at\n" . $hereptr)) { + $good = $fix_elements[$n] . trim($fix_elements[$n + 1]) . " "; + $line_fixed = 1; + } + } + + # // is a comment + } elsif ($op eq '//') { + + # : when part of a bitfield + } elsif ($opv eq ':B') { + # skip the bitfield test for now + + # No spaces for: + # -> + } elsif ($op eq '->') { + if ($ctx =~ /Wx.|.xW/) { + if (ERROR("SPACING", + "spaces prohibited around that '$op' $at\n" . $hereptr)) { + $good = rtrim($fix_elements[$n]) . trim($fix_elements[$n + 1]); + if (defined $fix_elements[$n + 2]) { + $fix_elements[$n + 2] =~ s/^\s+//; + } + $line_fixed = 1; + } + } + + # , must not have a space before and must have a space on the right. + } elsif ($op eq ',') { + my $rtrim_before = 0; + my $space_after = 0; + if ($ctx =~ /Wx./) { + if (ERROR("SPACING", + "space prohibited before that '$op' $at\n" . $hereptr)) { + $line_fixed = 1; + $rtrim_before = 1; + } + } + if ($ctx !~ /.x[WEC]/ && $cc !~ /^}/) { + if (ERROR("SPACING", + "space required after that '$op' $at\n" . $hereptr)) { + $line_fixed = 1; + $last_after = $n; + $space_after = 1; + } + } + if ($rtrim_before || $space_after) { + if ($rtrim_before) { + $good = rtrim($fix_elements[$n]) . trim($fix_elements[$n + 1]); + } else { + $good = $fix_elements[$n] . trim($fix_elements[$n + 1]); + } + if ($space_after) { + $good .= " "; + } + } + + # '*' as part of a type definition -- reported already. + } elsif ($opv eq '*_') { + #warn "'*' is part of type\n"; + + # unary operators should have a space before and + # none after. May be left adjacent to another + # unary operator, or a cast + } elsif ($op eq '!' || $op eq '~' || + $opv eq '*U' || $opv eq '-U' || + $opv eq '&U' || $opv eq '&&U') { + if ($ctx !~ /[WEBC]x./ && $ca !~ /(?:\)|!|~|\*|-|\&|\||\+\+|\-\-|\{)$/) { + if (ERROR("SPACING", + "space required before that '$op' $at\n" . $hereptr)) { + if ($n != $last_after + 2) { + $good = $fix_elements[$n] . " " . ltrim($fix_elements[$n + 1]); + $line_fixed = 1; + } + } + } + if ($op eq '*' && $cc =~/\s*$Modifier\b/) { + # A unary '*' may be const + + } elsif ($ctx =~ /.xW/) { + if (ERROR("SPACING", + "space prohibited after that '$op' $at\n" . $hereptr)) { + $good = $fix_elements[$n] . rtrim($fix_elements[$n + 1]); + if (defined $fix_elements[$n + 2]) { + $fix_elements[$n + 2] =~ s/^\s+//; + } + $line_fixed = 1; + } + } + + # unary ++ and unary -- are allowed no space on one side. + } elsif ($op eq '++' or $op eq '--') { + if ($ctx !~ /[WEOBC]x[^W]/ && $ctx !~ /[^W]x[WOBEC]/) { + if (ERROR("SPACING", + "space required one side of that '$op' $at\n" . $hereptr)) { + $good = $fix_elements[$n] . trim($fix_elements[$n + 1]) . " "; + $line_fixed = 1; + } + } + if ($ctx =~ /Wx[BE]/ || + ($ctx =~ /Wx./ && $cc =~ /^;/)) { + if (ERROR("SPACING", + "space prohibited before that '$op' $at\n" . $hereptr)) { + $good = rtrim($fix_elements[$n]) . trim($fix_elements[$n + 1]); + $line_fixed = 1; + } + } + if ($ctx =~ /ExW/) { + if (ERROR("SPACING", + "space prohibited after that '$op' $at\n" . $hereptr)) { + $good = $fix_elements[$n] . trim($fix_elements[$n + 1]); + if (defined $fix_elements[$n + 2]) { + $fix_elements[$n + 2] =~ s/^\s+//; + } + $line_fixed = 1; + } + } + + # << and >> may either have or not have spaces both sides + } elsif ($op eq '<<' or $op eq '>>' or + $op eq '&' or $op eq '^' or $op eq '|' or + $op eq '+' or $op eq '-' or + $op eq '*' or $op eq '/' or + $op eq '%') + { + if ($check) { + if (defined $fix_elements[$n + 2] && $ctx !~ /[EW]x[EW]/) { + if (CHK("SPACING", + "spaces preferred around that '$op' $at\n" . $hereptr)) { + $good = rtrim($fix_elements[$n]) . " " . trim($fix_elements[$n + 1]) . " "; + $fix_elements[$n + 2] =~ s/^\s+//; + $line_fixed = 1; + } + } elsif (!defined $fix_elements[$n + 2] && $ctx !~ /Wx[OE]/) { + if (CHK("SPACING", + "space preferred before that '$op' $at\n" . $hereptr)) { + $good = rtrim($fix_elements[$n]) . " " . trim($fix_elements[$n + 1]); + $line_fixed = 1; + } + } + } elsif ($ctx =~ /Wx[^WCE]|[^WCE]xW/) { + if (ERROR("SPACING", + "need consistent spacing around '$op' $at\n" . $hereptr)) { + $good = rtrim($fix_elements[$n]) . " " . trim($fix_elements[$n + 1]) . " "; + if (defined $fix_elements[$n + 2]) { + $fix_elements[$n + 2] =~ s/^\s+//; + } + $line_fixed = 1; + } + } + + # A colon needs no spaces before when it is + # terminating a case value or a label. + } elsif ($opv eq ':C' || $opv eq ':L') { + if ($ctx =~ /Wx./) { + if (ERROR("SPACING", + "space prohibited before that '$op' $at\n" . $hereptr)) { + $good = rtrim($fix_elements[$n]) . trim($fix_elements[$n + 1]); + $line_fixed = 1; + } + } + + # All the others need spaces both sides. + } elsif ($ctx !~ /[EWC]x[CWE]/) { + my $ok = 0; + + # Ignore email addresses <foo@bar> + if (($op eq '<' && + $cc =~ /^\S+\@\S+>/) || + ($op eq '>' && + $ca =~ /<\S+\@\S+$/)) + { + $ok = 1; + } + + # for asm volatile statements + # ignore a colon with another + # colon immediately before or after + if (($op eq ':') && + ($ca =~ /:$/ || $cc =~ /^:/)) { + $ok = 1; + } + + # messages are ERROR, but ?: are CHK + if ($ok == 0) { + my $msg_level = \&ERROR; + $msg_level = \&CHK if (($op eq '?:' || $op eq '?' || $op eq ':') && $ctx =~ /VxV/); + + if (&{$msg_level}("SPACING", + "spaces required around that '$op' $at\n" . $hereptr)) { + $good = rtrim($fix_elements[$n]) . " " . trim($fix_elements[$n + 1]) . " "; + if (defined $fix_elements[$n + 2]) { + $fix_elements[$n + 2] =~ s/^\s+//; + } + $line_fixed = 1; + } + } + } + $off += length($elements[$n + 1]); + +## print("n: <$n> GOOD: <$good>\n"); + + $fixed_line = $fixed_line . $good; + } + + if (($#elements % 2) == 0) { + $fixed_line = $fixed_line . $fix_elements[$#elements]; + } + + if ($fix && $line_fixed && $fixed_line ne $fixed[$fixlinenr]) { + $fixed[$fixlinenr] = $fixed_line; + } + + + } + +# check for whitespace before a non-naked semicolon + if ($line =~ /^\+.*\S\s+;\s*$/) { + if (WARN("SPACING", + "space prohibited before semicolon\n" . $herecurr) && + $fix) { + 1 while $fixed[$fixlinenr] =~ + s/^(\+.*\S)\s+;/$1;/; + } + } + +# check for multiple assignments + if ($line =~ /^.\s*$Lval\s*=\s*$Lval\s*=(?!=)/) { + CHK("MULTIPLE_ASSIGNMENTS", + "multiple assignments should be avoided\n" . $herecurr); + } + +## # check for multiple declarations, allowing for a function declaration +## # continuation. +## if ($line =~ /^.\s*$Type\s+$Ident(?:\s*=[^,{]*)?\s*,\s*$Ident.*/ && +## $line !~ /^.\s*$Type\s+$Ident(?:\s*=[^,{]*)?\s*,\s*$Type\s*$Ident.*/) { +## +## # Remove any bracketed sections to ensure we do not +## # falsly report the parameters of functions. +## my $ln = $line; +## while ($ln =~ s/\([^\(\)]*\)//g) { +## } +## if ($ln =~ /,/) { +## WARN("MULTIPLE_DECLARATION", +## "declaring multiple variables together should be avoided\n" . $herecurr); +## } +## } + +#need space before brace following if, while, etc + if (($line =~ /\(.*\)\{/ && $line !~ /\($Type\)\{/) || + $line =~ /\b(?:else|do)\{/) { + if (ERROR("SPACING", + "space required before the open brace '{'\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/^(\+.*(?:do|else|\)))\{/$1 {/; + } + } + +## # check for blank lines before declarations +## if ($line =~ /^.\t+$Type\s+$Ident(?:\s*=.*)?;/ && +## $prevrawline =~ /^.\s*$/) { +## WARN("SPACING", +## "No blank lines before declarations\n" . $hereprev); +## } +## + +# closing brace should have a space following it when it has anything +# on the line + if ($line =~ /}(?!(?:,|;|\)|\}))\S/) { + if (ERROR("SPACING", + "space required after that close brace '}'\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ + s/}((?!(?:,|;|\)))\S)/} $1/; + } + } + +# check spacing on square brackets + if ($line =~ /\[\s/ && $line !~ /\[\s*$/) { + if (ERROR("SPACING", + "space prohibited after that open square bracket '['\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ + s/\[\s+/\[/; + } + } + if ($line =~ /\s\]/) { + if (ERROR("SPACING", + "space prohibited before that close square bracket ']'\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ + s/\s+\]/\]/; + } + } + +# check spacing on parentheses + if ($line =~ /\(\s/ && $line !~ /\(\s*(?:\\)?$/ && + $line !~ /for\s*\(\s+;/) { + if (ERROR("SPACING", + "space prohibited after that open parenthesis '('\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ + s/\(\s+/\(/; + } + } + if ($line =~ /(\s+)\)/ && $line !~ /^.\s*\)/ && + $line !~ /for\s*\(.*;\s+\)/ && + $line !~ /:\s+\)/) { + if (ERROR("SPACING", + "space prohibited before that close parenthesis ')'\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ + s/\s+\)/\)/; + } + } + +# check unnecessary parentheses around addressof/dereference single $Lvals +# ie: &(foo->bar) should be &foo->bar and *(foo->bar) should be *foo->bar + + while ($line =~ /(?:[^&]&\s*|\*)\(\s*($Ident\s*(?:$Member\s*)+)\s*\)/g) { + my $var = $1; + if (CHK("UNNECESSARY_PARENTHESES", + "Unnecessary parentheses around $var\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\(\s*\Q$var\E\s*\)/$var/; + } + } + +# check for unnecessary parentheses around function pointer uses +# ie: (foo->bar)(); should be foo->bar(); +# but not "if (foo->bar) (" to avoid some false positives + if ($line =~ /(\bif\s*|)(\(\s*$Ident\s*(?:$Member\s*)+\))[ \t]*\(/ && $1 !~ /^if/) { + my $var = $2; + if (CHK("UNNECESSARY_PARENTHESES", + "Unnecessary parentheses around function pointer $var\n" . $herecurr) && + $fix) { + my $var2 = deparenthesize($var); + $var2 =~ s/\s//g; + $fixed[$fixlinenr] =~ s/\Q$var\E/$var2/; + } + } + +# check for unnecessary parentheses around comparisons in if uses +# when !drivers/staging or command-line uses --strict + if (($realfile !~ m@^(?:drivers/staging/)@ || $check_orig) && + $perl_version_ok && defined($stat) && + $stat =~ /(^.\s*if\s*($balanced_parens))/) { + my $if_stat = $1; + my $test = substr($2, 1, -1); + my $herectx; + while ($test =~ /(?:^|[^\w\&\!\~])+\s*\(\s*([\&\!\~]?\s*$Lval\s*(?:$Compare\s*$FuncArg)?)\s*\)/g) { + my $match = $1; + # avoid parentheses around potential macro args + next if ($match =~ /^\s*\w+\s*$/); + if (!defined($herectx)) { + $herectx = $here . "\n"; + my $cnt = statement_rawlines($if_stat); + for (my $n = 0; $n < $cnt; $n++) { + my $rl = raw_line($linenr, $n); + $herectx .= $rl . "\n"; + last if $rl =~ /^[ \+].*\{/; + } + } + CHK("UNNECESSARY_PARENTHESES", + "Unnecessary parentheses around '$match'\n" . $herectx); + } + } + +#goto labels aren't indented, allow a single space however + if ($line=~/^.\s+[A-Za-z\d_]+:(?![0-9]+)/ and + !($line=~/^. [A-Za-z\d_]+:/) and !($line=~/^.\s+default:/)) { + if (WARN("INDENTED_LABEL", + "labels should not be indented\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ + s/^(.)\s+/$1/; + } + } + +# check if a statement with a comma should be two statements like: +# foo = bar(), /* comma should be semicolon */ +# bar = baz(); + if (defined($stat) && + $stat =~ /^\+\s*(?:$Lval\s*$Assignment\s*)?$FuncArg\s*,\s*(?:$Lval\s*$Assignment\s*)?$FuncArg\s*;\s*$/) { + my $cnt = statement_rawlines($stat); + my $herectx = get_stat_here($linenr, $cnt, $here); + WARN("SUSPECT_COMMA_SEMICOLON", + "Possible comma where semicolon could be used\n" . $herectx); + } + +# return is not a function + if (defined($stat) && $stat =~ /^.\s*return(\s*)\(/s) { + my $spacing = $1; + if ($perl_version_ok && + $stat =~ /^.\s*return\s*($balanced_parens)\s*;\s*$/) { + my $value = $1; + $value = deparenthesize($value); + if ($value =~ m/^\s*$FuncArg\s*(?:\?|$)/) { + ERROR("RETURN_PARENTHESES", + "return is not a function, parentheses are not required\n" . $herecurr); + } + } elsif ($spacing !~ /\s+/) { + ERROR("SPACING", + "space required before the open parenthesis '('\n" . $herecurr); + } + } + +# unnecessary return in a void function +# at end-of-function, with the previous line a single leading tab, then return; +# and the line before that not a goto label target like "out:" + if ($sline =~ /^[ \+]}\s*$/ && + $prevline =~ /^\+\treturn\s*;\s*$/ && + $linenr >= 3 && + $lines[$linenr - 3] =~ /^[ +]/ && + $lines[$linenr - 3] !~ /^[ +]\s*$Ident\s*:/) { + WARN("RETURN_VOID", + "void function return statements are not generally useful\n" . $hereprev); + } + +# if statements using unnecessary parentheses - ie: if ((foo == bar)) + if ($perl_version_ok && + $line =~ /\bif\s*((?:\(\s*){2,})/) { + my $openparens = $1; + my $count = $openparens =~ tr@\(@\(@; + my $msg = ""; + if ($line =~ /\bif\s*(?:\(\s*){$count,$count}$LvalOrFunc\s*($Compare)\s*$LvalOrFunc(?:\s*\)){$count,$count}/) { + my $comp = $4; #Not $1 because of $LvalOrFunc + $msg = " - maybe == should be = ?" if ($comp eq "=="); + WARN("UNNECESSARY_PARENTHESES", + "Unnecessary parentheses$msg\n" . $herecurr); + } + } + +# comparisons with a constant or upper case identifier on the left +# avoid cases like "foo + BAR < baz" +# only fix matches surrounded by parentheses to avoid incorrect +# conversions like "FOO < baz() + 5" being "misfixed" to "baz() > FOO + 5" + if ($perl_version_ok && + $line =~ /^\+(.*)\b($Constant|[A-Z_][A-Z0-9_]*)\s*($Compare)\s*($LvalOrFunc)/) { + my $lead = $1; + my $const = $2; + my $comp = $3; + my $to = $4; + my $newcomp = $comp; + if ($lead !~ /(?:$Operators|\.)\s*$/ && + $to !~ /^(?:Constant|[A-Z_][A-Z0-9_]*)$/ && + WARN("CONSTANT_COMPARISON", + "Comparisons should place the constant on the right side of the test\n" . $herecurr) && + $fix) { + if ($comp eq "<") { + $newcomp = ">"; + } elsif ($comp eq "<=") { + $newcomp = ">="; + } elsif ($comp eq ">") { + $newcomp = "<"; + } elsif ($comp eq ">=") { + $newcomp = "<="; + } + $fixed[$fixlinenr] =~ s/\(\s*\Q$const\E\s*$Compare\s*\Q$to\E\s*\)/($to $newcomp $const)/; + } + } + +# Return of what appears to be an errno should normally be negative + if ($sline =~ /\breturn(?:\s*\(+\s*|\s+)(E[A-Z]+)(?:\s*\)+\s*|\s*)[;:,]/) { + my $name = $1; + if ($name ne 'EOF' && $name ne 'ERROR') { + WARN("USE_NEGATIVE_ERRNO", + "return of an errno should typically be negative (ie: return -$1)\n" . $herecurr); + } + } + +# Need a space before open parenthesis after if, while etc + if ($line =~ /\b(if|while|for|switch)\(/) { + if (ERROR("SPACING", + "space required before the open parenthesis '('\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ + s/\b(if|while|for|switch)\(/$1 \(/; + } + } + +# Check for illegal assignment in if conditional -- and check for trailing +# statements after the conditional. + if ($line =~ /do\s*(?!{)/) { + ($stat, $cond, $line_nr_next, $remain_next, $off_next) = + ctx_statement_block($linenr, $realcnt, 0) + if (!defined $stat); + my ($stat_next) = ctx_statement_block($line_nr_next, + $remain_next, $off_next); + $stat_next =~ s/\n./\n /g; + ##print "stat<$stat> stat_next<$stat_next>\n"; + + if ($stat_next =~ /^\s*while\b/) { + # If the statement carries leading newlines, + # then count those as offsets. + my ($whitespace) = + ($stat_next =~ /^((?:\s*\n[+-])*\s*)/s); + my $offset = + statement_rawlines($whitespace) - 1; + + $suppress_whiletrailers{$line_nr_next + + $offset} = 1; + } + } + if (!defined $suppress_whiletrailers{$linenr} && + defined($stat) && defined($cond) && + $line =~ /\b(?:if|while|for)\s*\(/ && $line !~ /^.\s*#/) { + my ($s, $c) = ($stat, $cond); + + if ($c =~ /\bif\s*\(.*[^<>!=]=[^=].*/s) { + if (ERROR("ASSIGN_IN_IF", + "do not use assignment in if condition\n" . $herecurr) && + $fix && $perl_version_ok) { + if ($rawline =~ /^\+(\s+)if\s*\(\s*(\!)?\s*\(\s*(($Lval)\s*=\s*$LvalOrFunc)\s*\)\s*(?:($Compare)\s*($FuncArg))?\s*\)\s*(\{)?\s*$/) { + my $space = $1; + my $not = $2; + my $statement = $3; + my $assigned = $4; + my $test = $8; + my $against = $9; + my $brace = $15; + fix_delete_line($fixlinenr, $rawline); + fix_insert_line($fixlinenr, "$space$statement;"); + my $newline = "${space}if ("; + $newline .= '!' if defined($not); + $newline .= '(' if (defined $not && defined($test) && defined($against)); + $newline .= "$assigned"; + $newline .= " $test $against" if (defined($test) && defined($against)); + $newline .= ')' if (defined $not && defined($test) && defined($against)); + $newline .= ')'; + $newline .= " {" if (defined($brace)); + fix_insert_line($fixlinenr + 1, $newline); + } + } + } + + # Find out what is on the end of the line after the + # conditional. + substr($s, 0, length($c), ''); + $s =~ s/\n.*//g; + $s =~ s/$;//g; # Remove any comments + if (length($c) && $s !~ /^\s*{?\s*\\*\s*$/ && + $c !~ /}\s*while\s*/) + { + # Find out how long the conditional actually is. + my @newlines = ($c =~ /\n/gs); + my $cond_lines = 1 + $#newlines; + my $stat_real = ''; + + $stat_real = raw_line($linenr, $cond_lines) + . "\n" if ($cond_lines); + if (defined($stat_real) && $cond_lines > 1) { + $stat_real = "[...]\n$stat_real"; + } + + ERROR("TRAILING_STATEMENTS", + "trailing statements should be on next line\n" . $herecurr . $stat_real); + } + } + +# Check for bitwise tests written as boolean + if ($line =~ / + (?: + (?:\[|\(|\&\&|\|\|) + \s*0[xX][0-9]+\s* + (?:\&\&|\|\|) + | + (?:\&\&|\|\|) + \s*0[xX][0-9]+\s* + (?:\&\&|\|\||\)|\]) + )/x) + { + WARN("HEXADECIMAL_BOOLEAN_TEST", + "boolean test with hexadecimal, perhaps just 1 \& or \|?\n" . $herecurr); + } + +# if and else should not have general statements after it + if ($line =~ /^.\s*(?:}\s*)?else\b(.*)/) { + my $s = $1; + $s =~ s/$;//g; # Remove any comments + if ($s !~ /^\s*(?:\sif|(?:{|)\s*\\?\s*$)/) { + ERROR("TRAILING_STATEMENTS", + "trailing statements should be on next line\n" . $herecurr); + } + } +# if should not continue a brace + if ($line =~ /}\s*if\b/) { + ERROR("TRAILING_STATEMENTS", + "trailing statements should be on next line (or did you mean 'else if'?)\n" . + $herecurr); + } +# case and default should not have general statements after them + if ($line =~ /^.\s*(?:case\s*.*|default\s*):/g && + $line !~ /\G(?: + (?:\s*$;*)(?:\s*{)?(?:\s*$;*)(?:\s*\\)?\s*$| + \s*return\s+ + )/xg) + { + ERROR("TRAILING_STATEMENTS", + "trailing statements should be on next line\n" . $herecurr); + } + + # Check for }<nl>else {, these must be at the same + # indent level to be relevant to each other. + if ($prevline=~/}\s*$/ and $line=~/^.\s*else\s*/ && + $previndent == $indent) { + if (ERROR("ELSE_AFTER_BRACE", + "else should follow close brace '}'\n" . $hereprev) && + $fix && $prevline =~ /^\+/ && $line =~ /^\+/) { + fix_delete_line($fixlinenr - 1, $prevrawline); + fix_delete_line($fixlinenr, $rawline); + my $fixedline = $prevrawline; + $fixedline =~ s/}\s*$//; + if ($fixedline !~ /^\+\s*$/) { + fix_insert_line($fixlinenr, $fixedline); + } + $fixedline = $rawline; + $fixedline =~ s/^(.\s*)else/$1} else/; + fix_insert_line($fixlinenr, $fixedline); + } + } + + if ($prevline=~/}\s*$/ and $line=~/^.\s*while\s*/ && + $previndent == $indent) { + my ($s, $c) = ctx_statement_block($linenr, $realcnt, 0); + + # Find out what is on the end of the line after the + # conditional. + substr($s, 0, length($c), ''); + $s =~ s/\n.*//g; + + if ($s =~ /^\s*;/) { + if (ERROR("WHILE_AFTER_BRACE", + "while should follow close brace '}'\n" . $hereprev) && + $fix && $prevline =~ /^\+/ && $line =~ /^\+/) { + fix_delete_line($fixlinenr - 1, $prevrawline); + fix_delete_line($fixlinenr, $rawline); + my $fixedline = $prevrawline; + my $trailing = $rawline; + $trailing =~ s/^\+//; + $trailing = trim($trailing); + $fixedline =~ s/}\s*$/} $trailing/; + fix_insert_line($fixlinenr, $fixedline); + } + } + } + +#Specific variable tests + while ($line =~ m{($Constant|$Lval)}g) { + my $var = $1; + +#CamelCase + if ($var !~ /^$Constant$/ && + $var =~ /[A-Z][a-z]|[a-z][A-Z]/ && +#Ignore Page<foo> variants + $var !~ /^(?:Clear|Set|TestClear|TestSet|)Page[A-Z]/ && +#Ignore SI style variants like nS, mV and dB +#(ie: max_uV, regulator_min_uA_show, RANGE_mA_VALUE) + $var !~ /^(?:[a-z0-9_]*|[A-Z0-9_]*)?_?[a-z][A-Z](?:_[a-z0-9_]+|_[A-Z0-9_]+)?$/ && +#Ignore some three character SI units explicitly, like MiB and KHz + $var !~ /^(?:[a-z_]*?)_?(?:[KMGT]iB|[KMGT]?Hz)(?:_[a-z_]+)?$/) { + while ($var =~ m{($Ident)}g) { + my $word = $1; + next if ($word !~ /[A-Z][a-z]|[a-z][A-Z]/); + if ($check) { + seed_camelcase_includes(); + if (!$file && !$camelcase_file_seeded) { + seed_camelcase_file($realfile); + $camelcase_file_seeded = 1; + } + } + if (!defined $camelcase{$word}) { + $camelcase{$word} = 1; + CHK("CAMELCASE", + "Avoid CamelCase: <$word>\n" . $herecurr); + } + } + } + } + +#no spaces allowed after \ in define + if ($line =~ /\#\s*define.*\\\s+$/) { + if (WARN("WHITESPACE_AFTER_LINE_CONTINUATION", + "Whitespace after \\ makes next lines useless\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\s+$//; + } + } + +# warn if <asm/foo.h> is #included and <linux/foo.h> is available and includes +# itself <asm/foo.h> (uses RAW line) + if ($tree && $rawline =~ m{^.\s*\#\s*include\s*\<asm\/(.*)\.h\>}) { + my $file = "$1.h"; + my $checkfile = "include/linux/$file"; + if (-f "$root/$checkfile" && + $realfile ne $checkfile && + $1 !~ /$allowed_asm_includes/) + { + my $asminclude = `grep -Ec "#include\\s+<asm/$file>" $root/$checkfile`; + if ($asminclude > 0) { + if ($realfile =~ m{^arch/}) { + CHK("ARCH_INCLUDE_LINUX", + "Consider using #include <linux/$file> instead of <asm/$file>\n" . $herecurr); + } else { + WARN("INCLUDE_LINUX", + "Use #include <linux/$file> instead of <asm/$file>\n" . $herecurr); + } + } + } + } + +# multi-statement macros should be enclosed in a do while loop, grab the +# first statement and ensure its the whole macro if its not enclosed +# in a known good container + if ($realfile !~ m@/vmlinux.lds.h$@ && + $line =~ /^.\s*\#\s*define\s*$Ident(\()?/) { + my $ln = $linenr; + my $cnt = $realcnt; + my ($off, $dstat, $dcond, $rest); + my $ctx = ''; + my $has_flow_statement = 0; + my $has_arg_concat = 0; + ($dstat, $dcond, $ln, $cnt, $off) = + ctx_statement_block($linenr, $realcnt, 0); + $ctx = $dstat; + #print "dstat<$dstat> dcond<$dcond> cnt<$cnt> off<$off>\n"; + #print "LINE<$lines[$ln-1]> len<" . length($lines[$ln-1]) . "\n"; + + $has_flow_statement = 1 if ($ctx =~ /\b(goto|return)\b/); + $has_arg_concat = 1 if ($ctx =~ /\#\#/ && $ctx !~ /\#\#\s*(?:__VA_ARGS__|args)\b/); + + $dstat =~ s/^.\s*\#\s*define\s+$Ident(\([^\)]*\))?\s*//; + my $define_args = $1; + my $define_stmt = $dstat; + my @def_args = (); + + if (defined $define_args && $define_args ne "") { + $define_args = substr($define_args, 1, length($define_args) - 2); + $define_args =~ s/\s*//g; + $define_args =~ s/\\\+?//g; + @def_args = split(",", $define_args); + } + + $dstat =~ s/$;//g; + $dstat =~ s/\\\n.//g; + $dstat =~ s/^\s*//s; + $dstat =~ s/\s*$//s; + + # Flatten any parentheses and braces + while ($dstat =~ s/\([^\(\)]*\)/1u/ || + $dstat =~ s/\{[^\{\}]*\}/1u/ || + $dstat =~ s/.\[[^\[\]]*\]/1u/) + { + } + + # Flatten any obvious string concatenation. + while ($dstat =~ s/($String)\s*$Ident/$1/ || + $dstat =~ s/$Ident\s*($String)/$1/) + { + } + + # Make asm volatile uses seem like a generic function + $dstat =~ s/\b_*asm_*\s+_*volatile_*\b/asm_volatile/g; + + my $exceptions = qr{ + $Declare| + module_param_named| + MODULE_PARM_DESC| + DECLARE_PER_CPU| + DEFINE_PER_CPU| + __typeof__\(| + union| + struct| + \.$Ident\s*=\s*| + ^\"|\"$| + ^\[ + }x; + #print "REST<$rest> dstat<$dstat> ctx<$ctx>\n"; + + $ctx =~ s/\n*$//; + my $stmt_cnt = statement_rawlines($ctx); + my $herectx = get_stat_here($linenr, $stmt_cnt, $here); + + if ($dstat ne '' && + $dstat !~ /^(?:$Ident|-?$Constant),$/ && # 10, // foo(), + $dstat !~ /^(?:$Ident|-?$Constant);$/ && # foo(); + $dstat !~ /^[!~-]?(?:$Lval|$Constant)$/ && # 10 // foo() // !foo // ~foo // -foo // foo->bar // foo.bar->baz + $dstat !~ /^'X'$/ && $dstat !~ /^'XX'$/ && # character constants + $dstat !~ /$exceptions/ && + $dstat !~ /^\.$Ident\s*=/ && # .foo = + $dstat !~ /^(?:\#\s*$Ident|\#\s*$Constant)\s*$/ && # stringification #foo + $dstat !~ /^do\s*$Constant\s*while\s*$Constant;?$/ && # do {...} while (...); // do {...} while (...) + $dstat !~ /^while\s*$Constant\s*$Constant\s*$/ && # while (...) {...} + $dstat !~ /^for\s*$Constant$/ && # for (...) + $dstat !~ /^for\s*$Constant\s+(?:$Ident|-?$Constant)$/ && # for (...) bar() + $dstat !~ /^do\s*{/ && # do {... + $dstat !~ /^\(\{/ && # ({... + $ctx !~ /^.\s*#\s*define\s+TRACE_(?:SYSTEM|INCLUDE_FILE|INCLUDE_PATH)\b/) + { + if ($dstat =~ /^\s*if\b/) { + ERROR("MULTISTATEMENT_MACRO_USE_DO_WHILE", + "Macros starting with if should be enclosed by a do - while loop to avoid possible if/else logic defects\n" . "$herectx"); + } elsif ($dstat =~ /;/) { + ERROR("MULTISTATEMENT_MACRO_USE_DO_WHILE", + "Macros with multiple statements should be enclosed in a do - while loop\n" . "$herectx"); + } else { + ERROR("COMPLEX_MACRO", + "Macros with complex values should be enclosed in parentheses\n" . "$herectx"); + } + + } + + # Make $define_stmt single line, comment-free, etc + my @stmt_array = split('\n', $define_stmt); + my $first = 1; + $define_stmt = ""; + foreach my $l (@stmt_array) { + $l =~ s/\\$//; + if ($first) { + $define_stmt = $l; + $first = 0; + } elsif ($l =~ /^[\+ ]/) { + $define_stmt .= substr($l, 1); + } + } + $define_stmt =~ s/$;//g; + $define_stmt =~ s/\s+/ /g; + $define_stmt = trim($define_stmt); + +# check if any macro arguments are reused (ignore '...' and 'type') + foreach my $arg (@def_args) { + next if ($arg =~ /\.\.\./); + next if ($arg =~ /^type$/i); + my $tmp_stmt = $define_stmt; + $tmp_stmt =~ s/\b(sizeof|typeof|__typeof__|__builtin\w+|typecheck\s*\(\s*$Type\s*,|\#+)\s*\(*\s*$arg\s*\)*\b//g; + $tmp_stmt =~ s/\#+\s*$arg\b//g; + $tmp_stmt =~ s/\b$arg\s*\#\#//g; + my $use_cnt = () = $tmp_stmt =~ /\b$arg\b/g; + if ($use_cnt > 1) { + CHK("MACRO_ARG_REUSE", + "Macro argument reuse '$arg' - possible side-effects?\n" . "$herectx"); + } +# check if any macro arguments may have other precedence issues + if ($tmp_stmt =~ m/($Operators)?\s*\b$arg\b\s*($Operators)?/m && + ((defined($1) && $1 ne ',') || + (defined($2) && $2 ne ','))) { + CHK("MACRO_ARG_PRECEDENCE", + "Macro argument '$arg' may be better as '($arg)' to avoid precedence issues\n" . "$herectx"); + } + } + +# check for macros with flow control, but without ## concatenation +# ## concatenation is commonly a macro that defines a function so ignore those + if ($has_flow_statement && !$has_arg_concat) { + my $cnt = statement_rawlines($ctx); + my $herectx = get_stat_here($linenr, $cnt, $here); + + WARN("MACRO_WITH_FLOW_CONTROL", + "Macros with flow control statements should be avoided\n" . "$herectx"); + } + +# check for line continuations outside of #defines, preprocessor #, and asm + + } else { + if ($prevline !~ /^..*\\$/ && + $line !~ /^\+\s*\#.*\\$/ && # preprocessor + $line !~ /^\+.*\b(__asm__|asm)\b.*\\$/ && # asm + $line =~ /^\+.*\\$/) { + WARN("LINE_CONTINUATIONS", + "Avoid unnecessary line continuations\n" . $herecurr); + } + } + +# do {} while (0) macro tests: +# single-statement macros do not need to be enclosed in do while (0) loop, +# macro should not end with a semicolon + if ($perl_version_ok && + $realfile !~ m@/vmlinux.lds.h$@ && + $line =~ /^.\s*\#\s*define\s+$Ident(\()?/) { + my $ln = $linenr; + my $cnt = $realcnt; + my ($off, $dstat, $dcond, $rest); + my $ctx = ''; + ($dstat, $dcond, $ln, $cnt, $off) = + ctx_statement_block($linenr, $realcnt, 0); + $ctx = $dstat; + + $dstat =~ s/\\\n.//g; + $dstat =~ s/$;/ /g; + + if ($dstat =~ /^\+\s*#\s*define\s+$Ident\s*${balanced_parens}\s*do\s*{(.*)\s*}\s*while\s*\(\s*0\s*\)\s*([;\s]*)\s*$/) { + my $stmts = $2; + my $semis = $3; + + $ctx =~ s/\n*$//; + my $cnt = statement_rawlines($ctx); + my $herectx = get_stat_here($linenr, $cnt, $here); + + if (($stmts =~ tr/;/;/) == 1 && + $stmts !~ /^\s*(if|while|for|switch)\b/) { + WARN("SINGLE_STATEMENT_DO_WHILE_MACRO", + "Single statement macros should not use a do {} while (0) loop\n" . "$herectx"); + } + if (defined $semis && $semis ne "") { + WARN("DO_WHILE_MACRO_WITH_TRAILING_SEMICOLON", + "do {} while (0) macros should not be semicolon terminated\n" . "$herectx"); + } + } elsif ($dstat =~ /^\+\s*#\s*define\s+$Ident.*;\s*$/) { + $ctx =~ s/\n*$//; + my $cnt = statement_rawlines($ctx); + my $herectx = get_stat_here($linenr, $cnt, $here); + + WARN("TRAILING_SEMICOLON", + "macros should not use a trailing semicolon\n" . "$herectx"); + } + } + +# check for redundant bracing round if etc + if ($line =~ /(^.*)\bif\b/ && $1 !~ /else\s*$/) { + my ($level, $endln, @chunks) = + ctx_statement_full($linenr, $realcnt, 1); + #print "chunks<$#chunks> linenr<$linenr> endln<$endln> level<$level>\n"; + #print "APW: <<$chunks[1][0]>><<$chunks[1][1]>>\n"; + if ($#chunks > 0 && $level == 0) { + my @allowed = (); + my $allow = 0; + my $seen = 0; + my $herectx = $here . "\n"; + my $ln = $linenr - 1; + for my $chunk (@chunks) { + my ($cond, $block) = @{$chunk}; + + # If the condition carries leading newlines, then count those as offsets. + my ($whitespace) = ($cond =~ /^((?:\s*\n[+-])*\s*)/s); + my $offset = statement_rawlines($whitespace) - 1; + + $allowed[$allow] = 0; + #print "COND<$cond> whitespace<$whitespace> offset<$offset>\n"; + + # We have looked at and allowed this specific line. + $suppress_ifbraces{$ln + $offset} = 1; + + $herectx .= "$rawlines[$ln + $offset]\n[...]\n"; + $ln += statement_rawlines($block) - 1; + + substr($block, 0, length($cond), ''); + + $seen++ if ($block =~ /^\s*{/); + + #print "cond<$cond> block<$block> allowed<$allowed[$allow]>\n"; + if (statement_lines($cond) > 1) { + #print "APW: ALLOWED: cond<$cond>\n"; + $allowed[$allow] = 1; + } + if ($block =~/\b(?:if|for|while)\b/) { + #print "APW: ALLOWED: block<$block>\n"; + $allowed[$allow] = 1; + } + if (statement_block_size($block) > 1) { + #print "APW: ALLOWED: lines block<$block>\n"; + $allowed[$allow] = 1; + } + $allow++; + } + if ($seen) { + my $sum_allowed = 0; + foreach (@allowed) { + $sum_allowed += $_; + } + if ($sum_allowed == 0) { + WARN("BRACES", + "braces {} are not necessary for any arm of this statement\n" . $herectx); + } elsif ($sum_allowed != $allow && + $seen != $allow) { + CHK("BRACES", + "braces {} should be used on all arms of this statement\n" . $herectx); + } + } + } + } + if (!defined $suppress_ifbraces{$linenr - 1} && + $line =~ /\b(if|while|for|else)\b/) { + my $allowed = 0; + + # Check the pre-context. + if (substr($line, 0, $-[0]) =~ /(\}\s*)$/) { + #print "APW: ALLOWED: pre<$1>\n"; + $allowed = 1; + } + + my ($level, $endln, @chunks) = + ctx_statement_full($linenr, $realcnt, $-[0]); + + # Check the condition. + my ($cond, $block) = @{$chunks[0]}; + #print "CHECKING<$linenr> cond<$cond> block<$block>\n"; + if (defined $cond) { + substr($block, 0, length($cond), ''); + } + if (statement_lines($cond) > 1) { + #print "APW: ALLOWED: cond<$cond>\n"; + $allowed = 1; + } + if ($block =~/\b(?:if|for|while)\b/) { + #print "APW: ALLOWED: block<$block>\n"; + $allowed = 1; + } + if (statement_block_size($block) > 1) { + #print "APW: ALLOWED: lines block<$block>\n"; + $allowed = 1; + } + # Check the post-context. + if (defined $chunks[1]) { + my ($cond, $block) = @{$chunks[1]}; + if (defined $cond) { + substr($block, 0, length($cond), ''); + } + if ($block =~ /^\s*\{/) { + #print "APW: ALLOWED: chunk-1 block<$block>\n"; + $allowed = 1; + } + } + if ($level == 0 && $block =~ /^\s*\{/ && !$allowed) { + my $cnt = statement_rawlines($block); + my $herectx = get_stat_here($linenr, $cnt, $here); + + WARN("BRACES", + "braces {} are not necessary for single statement blocks\n" . $herectx); + } + } + +# check for single line unbalanced braces + if ($sline =~ /^.\s*\}\s*else\s*$/ || + $sline =~ /^.\s*else\s*\{\s*$/) { + CHK("BRACES", "Unbalanced braces around else statement\n" . $herecurr); + } + +# check for unnecessary blank lines around braces + if (($line =~ /^.\s*}\s*$/ && $prevrawline =~ /^.\s*$/)) { + if (CHK("BRACES", + "Blank lines aren't necessary before a close brace '}'\n" . $hereprev) && + $fix && $prevrawline =~ /^\+/) { + fix_delete_line($fixlinenr - 1, $prevrawline); + } + } + if (($rawline =~ /^.\s*$/ && $prevline =~ /^..*{\s*$/)) { + if (CHK("BRACES", + "Blank lines aren't necessary after an open brace '{'\n" . $hereprev) && + $fix) { + fix_delete_line($fixlinenr, $rawline); + } + } + +# no volatiles please + my $asm_volatile = qr{\b(__asm__|asm)\s+(__volatile__|volatile)\b}; + if ($line =~ /\bvolatile\b/ && $line !~ /$asm_volatile/) { + WARN("VOLATILE", + "Use of volatile is usually wrong: see Documentation/process/volatile-considered-harmful.rst\n" . $herecurr); + } + +# Check for user-visible strings broken across lines, which breaks the ability +# to grep for the string. Make exceptions when the previous string ends in a +# newline (multiple lines in one string constant) or '\t', '\r', ';', or '{' +# (common in inline assembly) or is a octal \123 or hexadecimal \xaf value + if ($line =~ /^\+\s*$String/ && + $prevline =~ /"\s*$/ && + $prevrawline !~ /(?:\\(?:[ntr]|[0-7]{1,3}|x[0-9a-fA-F]{1,2})|;\s*|\{\s*)"\s*$/) { + if (WARN("SPLIT_STRING", + "quoted string split across lines\n" . $hereprev) && + $fix && + $prevrawline =~ /^\+.*"\s*$/ && + $last_coalesced_string_linenr != $linenr - 1) { + my $extracted_string = get_quoted_string($line, $rawline); + my $comma_close = ""; + if ($rawline =~ /\Q$extracted_string\E(\s*\)\s*;\s*$|\s*,\s*)/) { + $comma_close = $1; + } + + fix_delete_line($fixlinenr - 1, $prevrawline); + fix_delete_line($fixlinenr, $rawline); + my $fixedline = $prevrawline; + $fixedline =~ s/"\s*$//; + $fixedline .= substr($extracted_string, 1) . trim($comma_close); + fix_insert_line($fixlinenr - 1, $fixedline); + $fixedline = $rawline; + $fixedline =~ s/\Q$extracted_string\E\Q$comma_close\E//; + if ($fixedline !~ /\+\s*$/) { + fix_insert_line($fixlinenr, $fixedline); + } + $last_coalesced_string_linenr = $linenr; + } + } + +# check for missing a space in a string concatenation + if ($prevrawline =~ /[^\\]\w"$/ && $rawline =~ /^\+[\t ]+"\w/) { + WARN('MISSING_SPACE', + "break quoted strings at a space character\n" . $hereprev); + } + +# check for an embedded function name in a string when the function is known +# This does not work very well for -f --file checking as it depends on patch +# context providing the function name or a single line form for in-file +# function declarations + if ($line =~ /^\+.*$String/ && + defined($context_function) && + get_quoted_string($line, $rawline) =~ /\b$context_function\b/ && + length(get_quoted_string($line, $rawline)) != (length($context_function) + 2)) { + WARN("EMBEDDED_FUNCTION_NAME", + "Prefer using '\"%s...\", __func__' to using '$context_function', this function's name, in a string\n" . $herecurr); + } + +# check for spaces before a quoted newline + if ($rawline =~ /^.*\".*\s\\n/) { + if (WARN("QUOTED_WHITESPACE_BEFORE_NEWLINE", + "unnecessary whitespace before a quoted newline\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/^(\+.*\".*)\s+\\n/$1\\n/; + } + + } + +# concatenated string without spaces between elements + if ($line =~ /$String[A-Za-z0-9_]/ || $line =~ /[A-Za-z0-9_]$String/) { + if (CHK("CONCATENATED_STRING", + "Concatenated strings should use spaces between elements\n" . $herecurr) && + $fix) { + while ($line =~ /($String)/g) { + my $extracted_string = substr($rawline, $-[0], $+[0] - $-[0]); + $fixed[$fixlinenr] =~ s/\Q$extracted_string\E([A-Za-z0-9_])/$extracted_string $1/; + $fixed[$fixlinenr] =~ s/([A-Za-z0-9_])\Q$extracted_string\E/$1 $extracted_string/; + } + } + } + +# uncoalesced string fragments + if ($line =~ /$String\s*"/) { + if (WARN("STRING_FRAGMENTS", + "Consecutive strings are generally better as a single string\n" . $herecurr) && + $fix) { + while ($line =~ /($String)(?=\s*")/g) { + my $extracted_string = substr($rawline, $-[0], $+[0] - $-[0]); + $fixed[$fixlinenr] =~ s/\Q$extracted_string\E\s*"/substr($extracted_string, 0, -1)/e; + } + } + } + +# check for non-standard and hex prefixed decimal printf formats + my $show_L = 1; #don't show the same defect twice + my $show_Z = 1; + while ($line =~ /(?:^|")([X\t]*)(?:"|$)/g) { + my $string = substr($rawline, $-[1], $+[1] - $-[1]); + $string =~ s/%%/__/g; + # check for %L + if ($show_L && $string =~ /%[\*\d\.\$]*L([diouxX])/) { + WARN("PRINTF_L", + "\%L$1 is non-standard C, use %ll$1\n" . $herecurr); + $show_L = 0; + } + # check for %Z + if ($show_Z && $string =~ /%[\*\d\.\$]*Z([diouxX])/) { + WARN("PRINTF_Z", + "%Z$1 is non-standard C, use %z$1\n" . $herecurr); + $show_Z = 0; + } + # check for 0x<decimal> + if ($string =~ /0x%[\*\d\.\$\Llzth]*[diou]/) { + ERROR("PRINTF_0XDECIMAL", + "Prefixing 0x with decimal output is defective\n" . $herecurr); + } + } + +# check for line continuations in quoted strings with odd counts of " + if ($rawline =~ /\\$/ && $sline =~ tr/"/"/ % 2) { + WARN("LINE_CONTINUATIONS", + "Avoid line continuations in quoted strings\n" . $herecurr); + } + +# warn about #if 0 + if ($line =~ /^.\s*\#\s*if\s+0\b/) { + WARN("IF_0", + "Consider removing the code enclosed by this #if 0 and its #endif\n" . $herecurr); + } + +# warn about #if 1 + if ($line =~ /^.\s*\#\s*if\s+1\b/) { + WARN("IF_1", + "Consider removing the #if 1 and its #endif\n" . $herecurr); + } + +# check for needless "if (<foo>) fn(<foo>)" uses + if ($prevline =~ /\bif\s*\(\s*($Lval)\s*\)/) { + my $tested = quotemeta($1); + my $expr = '\s*\(\s*' . $tested . '\s*\)\s*;'; + if ($line =~ /\b(kfree|usb_free_urb|debugfs_remove(?:_recursive)?|(?:kmem_cache|mempool|dma_pool)_destroy)$expr/) { + my $func = $1; + if (WARN('NEEDLESS_IF', + "$func(NULL) is safe and this check is probably not required\n" . $hereprev) && + $fix) { + my $do_fix = 1; + my $leading_tabs = ""; + my $new_leading_tabs = ""; + if ($lines[$linenr - 2] =~ /^\+(\t*)if\s*\(\s*$tested\s*\)\s*$/) { + $leading_tabs = $1; + } else { + $do_fix = 0; + } + if ($lines[$linenr - 1] =~ /^\+(\t+)$func\s*\(\s*$tested\s*\)\s*;\s*$/) { + $new_leading_tabs = $1; + if (length($leading_tabs) + 1 ne length($new_leading_tabs)) { + $do_fix = 0; + } + } else { + $do_fix = 0; + } + if ($do_fix) { + fix_delete_line($fixlinenr - 1, $prevrawline); + $fixed[$fixlinenr] =~ s/^\+$new_leading_tabs/\+$leading_tabs/; + } + } + } + } + +# check for unnecessary "Out of Memory" messages + if ($line =~ /^\+.*\b$logFunctions\s*\(/ && + $prevline =~ /^[ \+]\s*if\s*\(\s*(\!\s*|NULL\s*==\s*)?($Lval)(\s*==\s*NULL\s*)?\s*\)/ && + (defined $1 || defined $3) && + $linenr > 3) { + my $testval = $2; + my $testline = $lines[$linenr - 3]; + + my ($s, $c) = ctx_statement_block($linenr - 3, $realcnt, 0); +# print("line: <$line>\nprevline: <$prevline>\ns: <$s>\nc: <$c>\n\n\n"); + + if ($s =~ /(?:^|\n)[ \+]\s*(?:$Type\s*)?\Q$testval\E\s*=\s*(?:\([^\)]*\)\s*)?\s*$allocFunctions\s*\(/ && + $s !~ /\b__GFP_NOWARN\b/ ) { + WARN("OOM_MESSAGE", + "Possible unnecessary 'out of memory' message\n" . $hereprev); + } + } + +# check for logging functions with KERN_<LEVEL> + if ($line !~ /printk(?:_ratelimited|_once)?\s*\(/ && + $line =~ /\b$logFunctions\s*\(.*\b(KERN_[A-Z]+)\b/) { + my $level = $1; + if (WARN("UNNECESSARY_KERN_LEVEL", + "Possible unnecessary $level\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\s*$level\s*//; + } + } + +# check for logging continuations + if ($line =~ /\bprintk\s*\(\s*KERN_CONT\b|\bpr_cont\s*\(/) { + WARN("LOGGING_CONTINUATION", + "Avoid logging continuation uses where feasible\n" . $herecurr); + } + +# check for mask then right shift without a parentheses + if ($perl_version_ok && + $line =~ /$LvalOrFunc\s*\&\s*($LvalOrFunc)\s*>>/ && + $4 !~ /^\&/) { # $LvalOrFunc may be &foo, ignore if so + WARN("MASK_THEN_SHIFT", + "Possible precedence defect with mask then right shift - may need parentheses\n" . $herecurr); + } + +# check for pointer comparisons to NULL + if ($perl_version_ok) { + while ($line =~ /\b$LvalOrFunc\s*(==|\!=)\s*NULL\b/g) { + my $val = $1; + my $equal = "!"; + $equal = "" if ($4 eq "!="); + if (CHK("COMPARISON_TO_NULL", + "Comparison to NULL could be written \"${equal}${val}\"\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\b\Q$val\E\s*(?:==|\!=)\s*NULL\b/$equal$val/; + } + } + } + +# check for bad placement of section $InitAttribute (e.g.: __initdata) + if ($line =~ /(\b$InitAttribute\b)/) { + my $attr = $1; + if ($line =~ /^\+\s*static\s+(?:const\s+)?(?:$attr\s+)?($NonptrTypeWithAttr)\s+(?:$attr\s+)?($Ident(?:\[[^]]*\])?)\s*[=;]/) { + my $ptr = $1; + my $var = $2; + if ((($ptr =~ /\b(union|struct)\s+$attr\b/ && + ERROR("MISPLACED_INIT", + "$attr should be placed after $var\n" . $herecurr)) || + ($ptr !~ /\b(union|struct)\s+$attr\b/ && + WARN("MISPLACED_INIT", + "$attr should be placed after $var\n" . $herecurr))) && + $fix) { + $fixed[$fixlinenr] =~ s/(\bstatic\s+(?:const\s+)?)(?:$attr\s+)?($NonptrTypeWithAttr)\s+(?:$attr\s+)?($Ident(?:\[[^]]*\])?)\s*([=;])\s*/"$1" . trim(string_find_replace($2, "\\s*$attr\\s*", " ")) . " " . trim(string_find_replace($3, "\\s*$attr\\s*", "")) . " $attr" . ("$4" eq ";" ? ";" : " = ")/e; + } + } + } + +# check for $InitAttributeData (ie: __initdata) with const + if ($line =~ /\bconst\b/ && $line =~ /($InitAttributeData)/) { + my $attr = $1; + $attr =~ /($InitAttributePrefix)(.*)/; + my $attr_prefix = $1; + my $attr_type = $2; + if (ERROR("INIT_ATTRIBUTE", + "Use of const init definition must use ${attr_prefix}initconst\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ + s/$InitAttributeData/${attr_prefix}initconst/; + } + } + +# check for $InitAttributeConst (ie: __initconst) without const + if ($line !~ /\bconst\b/ && $line =~ /($InitAttributeConst)/) { + my $attr = $1; + if (ERROR("INIT_ATTRIBUTE", + "Use of $attr requires a separate use of const\n" . $herecurr) && + $fix) { + my $lead = $fixed[$fixlinenr] =~ + /(^\+\s*(?:static\s+))/; + $lead = rtrim($1); + $lead = "$lead " if ($lead !~ /^\+$/); + $lead = "${lead}const "; + $fixed[$fixlinenr] =~ s/(^\+\s*(?:static\s+))/$lead/; + } + } + +# check for __read_mostly with const non-pointer (should just be const) + if ($line =~ /\b__read_mostly\b/ && + $line =~ /($Type)\s*$Ident/ && $1 !~ /\*\s*$/ && $1 =~ /\bconst\b/) { + if (ERROR("CONST_READ_MOSTLY", + "Invalid use of __read_mostly with const type\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\s+__read_mostly\b//; + } + } + +# don't use __constant_<foo> functions outside of include/uapi/ + if ($realfile !~ m@^include/uapi/@ && + $line =~ /(__constant_(?:htons|ntohs|[bl]e(?:16|32|64)_to_cpu|cpu_to_[bl]e(?:16|32|64)))\s*\(/) { + my $constant_func = $1; + my $func = $constant_func; + $func =~ s/^__constant_//; + if (WARN("CONSTANT_CONVERSION", + "$constant_func should be $func\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\b$constant_func\b/$func/g; + } + } + +# prefer usleep_range over udelay + if ($line =~ /\budelay\s*\(\s*(\d+)\s*\)/) { + my $delay = $1; + # ignore udelay's < 10, however + if (! ($delay < 10) ) { + CHK("USLEEP_RANGE", + "usleep_range is preferred over udelay; see Documentation/timers/timers-howto.rst\n" . $herecurr); + } + if ($delay > 2000) { + WARN("LONG_UDELAY", + "long udelay - prefer mdelay; see arch/arm/include/asm/delay.h\n" . $herecurr); + } + } + +# warn about unexpectedly long msleep's + if ($line =~ /\bmsleep\s*\((\d+)\);/) { + if ($1 < 20) { + WARN("MSLEEP", + "msleep < 20ms can sleep for up to 20ms; see Documentation/timers/timers-howto.rst\n" . $herecurr); + } + } + +# check for comparisons of jiffies + if ($line =~ /\bjiffies\s*$Compare|$Compare\s*jiffies\b/) { + WARN("JIFFIES_COMPARISON", + "Comparing jiffies is almost always wrong; prefer time_after, time_before and friends\n" . $herecurr); + } + +# check for comparisons of get_jiffies_64() + if ($line =~ /\bget_jiffies_64\s*\(\s*\)\s*$Compare|$Compare\s*get_jiffies_64\s*\(\s*\)/) { + WARN("JIFFIES_COMPARISON", + "Comparing get_jiffies_64() is almost always wrong; prefer time_after64, time_before64 and friends\n" . $herecurr); + } + +# warn about #ifdefs in C files +# if ($line =~ /^.\s*\#\s*if(|n)def/ && ($realfile =~ /\.c$/)) { +# print "#ifdef in C files should be avoided\n"; +# print "$herecurr"; +# $clean = 0; +# } + +# warn about spacing in #ifdefs + if ($line =~ /^.\s*\#\s*(ifdef|ifndef|elif)\s\s+/) { + if (ERROR("SPACING", + "exactly one space required after that #$1\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ + s/^(.\s*\#\s*(ifdef|ifndef|elif))\s{2,}/$1 /; + } + + } + +# check for spinlock_t definitions without a comment. + if ($line =~ /^.\s*(struct\s+mutex|spinlock_t)\s+\S+;/ || + $line =~ /^.\s*(DEFINE_MUTEX)\s*\(/) { + my $which = $1; + if (!ctx_has_comment($first_line, $linenr)) { + CHK("UNCOMMENTED_DEFINITION", + "$1 definition without comment\n" . $herecurr); + } + } +# check for memory barriers without a comment. + + my $barriers = qr{ + mb| + rmb| + wmb + }x; + my $barrier_stems = qr{ + mb__before_atomic| + mb__after_atomic| + store_release| + load_acquire| + store_mb| + (?:$barriers) + }x; + my $all_barriers = qr{ + (?:$barriers)| + smp_(?:$barrier_stems)| + virt_(?:$barrier_stems) + }x; + + if ($line =~ /\b(?:$all_barriers)\s*\(/) { + if (!ctx_has_comment($first_line, $linenr)) { + WARN("MEMORY_BARRIER", + "memory barrier without comment\n" . $herecurr); + } + } + + my $underscore_smp_barriers = qr{__smp_(?:$barrier_stems)}x; + + if ($realfile !~ m@^include/asm-generic/@ && + $realfile !~ m@/barrier\.h$@ && + $line =~ m/\b(?:$underscore_smp_barriers)\s*\(/ && + $line !~ m/^.\s*\#\s*define\s+(?:$underscore_smp_barriers)\s*\(/) { + WARN("MEMORY_BARRIER", + "__smp memory barriers shouldn't be used outside barrier.h and asm-generic\n" . $herecurr); + } + +# check for waitqueue_active without a comment. + if ($line =~ /\bwaitqueue_active\s*\(/) { + if (!ctx_has_comment($first_line, $linenr)) { + WARN("WAITQUEUE_ACTIVE", + "waitqueue_active without comment\n" . $herecurr); + } + } + +# check for data_race without a comment. + if ($line =~ /\bdata_race\s*\(/) { + if (!ctx_has_comment($first_line, $linenr)) { + WARN("DATA_RACE", + "data_race without comment\n" . $herecurr); + } + } + +# check of hardware specific defines + if ($line =~ m@^.\s*\#\s*if.*\b(__i386__|__powerpc64__|__sun__|__s390x__)\b@ && $realfile !~ m@include/asm-@) { + CHK("ARCH_DEFINES", + "architecture specific defines should be avoided\n" . $herecurr); + } + +# check that the storage class is not after a type + if ($line =~ /\b($Type)\s+($Storage)\b/) { + WARN("STORAGE_CLASS", + "storage class '$2' should be located before type '$1'\n" . $herecurr); + } +# Check that the storage class is at the beginning of a declaration + if ($line =~ /\b$Storage\b/ && + $line !~ /^.\s*$Storage/ && + $line =~ /^.\s*(.+?)\$Storage\s/ && + $1 !~ /[\,\)]\s*$/) { + WARN("STORAGE_CLASS", + "storage class should be at the beginning of the declaration\n" . $herecurr); + } + +# check the location of the inline attribute, that it is between +# storage class and type. + if ($line =~ /\b$Type\s+$Inline\b/ || + $line =~ /\b$Inline\s+$Storage\b/) { + ERROR("INLINE_LOCATION", + "inline keyword should sit between storage class and type\n" . $herecurr); + } + +# Check for __inline__ and __inline, prefer inline + if ($realfile !~ m@\binclude/uapi/@ && + $line =~ /\b(__inline__|__inline)\b/) { + if (WARN("INLINE", + "plain inline is preferred over $1\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\b(__inline__|__inline)\b/inline/; + + } + } + +# Check for __attribute__ packed, prefer __packed + if ($realfile !~ m@\binclude/uapi/@ && + $line =~ /\b__attribute__\s*\(\s*\(.*\bpacked\b/) { + WARN("PREFER_PACKED", + "__packed is preferred over __attribute__((packed))\n" . $herecurr); + } + +# Check for __attribute__ aligned, prefer __aligned + if ($realfile !~ m@\binclude/uapi/@ && + $line =~ /\b__attribute__\s*\(\s*\(.*aligned/) { + WARN("PREFER_ALIGNED", + "__aligned(size) is preferred over __attribute__((aligned(size)))\n" . $herecurr); + } + +# Check for __attribute__ section, prefer __section + if ($realfile !~ m@\binclude/uapi/@ && + $line =~ /\b__attribute__\s*\(\s*\(.*_*section_*\s*\(\s*("[^"]*")/) { + my $old = substr($rawline, $-[1], $+[1] - $-[1]); + my $new = substr($old, 1, -1); + if (WARN("PREFER_SECTION", + "__section($new) is preferred over __attribute__((section($old)))\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\b__attribute__\s*\(\s*\(\s*_*section_*\s*\(\s*\Q$old\E\s*\)\s*\)\s*\)/__section($new)/; + } + } + +# Check for __attribute__ format(printf, prefer __printf + if ($realfile !~ m@\binclude/uapi/@ && + $line =~ /\b__attribute__\s*\(\s*\(\s*format\s*\(\s*printf/) { + if (WARN("PREFER_PRINTF", + "__printf(string-index, first-to-check) is preferred over __attribute__((format(printf, string-index, first-to-check)))\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\b__attribute__\s*\(\s*\(\s*format\s*\(\s*printf\s*,\s*(.*)\)\s*\)\s*\)/"__printf(" . trim($1) . ")"/ex; + + } + } + +# Check for __attribute__ format(scanf, prefer __scanf + if ($realfile !~ m@\binclude/uapi/@ && + $line =~ /\b__attribute__\s*\(\s*\(\s*format\s*\(\s*scanf\b/) { + if (WARN("PREFER_SCANF", + "__scanf(string-index, first-to-check) is preferred over __attribute__((format(scanf, string-index, first-to-check)))\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\b__attribute__\s*\(\s*\(\s*format\s*\(\s*scanf\s*,\s*(.*)\)\s*\)\s*\)/"__scanf(" . trim($1) . ")"/ex; + } + } + +# Check for __attribute__ weak, or __weak declarations (may have link issues) + if ($perl_version_ok && + $line =~ /(?:$Declare|$DeclareMisordered)\s*$Ident\s*$balanced_parens\s*(?:$Attribute)?\s*;/ && + ($line =~ /\b__attribute__\s*\(\s*\(.*\bweak\b/ || + $line =~ /\b__weak\b/)) { + ERROR("WEAK_DECLARATION", + "Using weak declarations can have unintended link defects\n" . $herecurr); + } + +# check for c99 types like uint8_t used outside of uapi/ and tools/ + if ($realfile !~ m@\binclude/uapi/@ && + $realfile !~ m@\btools/@ && + $line =~ /\b($Declare)\s*$Ident\s*[=;,\[]/) { + my $type = $1; + if ($type =~ /\b($typeC99Typedefs)\b/) { + $type = $1; + my $kernel_type = 'u'; + $kernel_type = 's' if ($type =~ /^_*[si]/); + $type =~ /(\d+)/; + $kernel_type .= $1; + if (CHK("PREFER_KERNEL_TYPES", + "Prefer kernel type '$kernel_type' over '$type'\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\b$type\b/$kernel_type/; + } + } + } + +# check for cast of C90 native int or longer types constants + if ($line =~ /(\(\s*$C90_int_types\s*\)\s*)($Constant)\b/) { + my $cast = $1; + my $const = $2; + if (WARN("TYPECAST_INT_CONSTANT", + "Unnecessary typecast of c90 int constant\n" . $herecurr) && + $fix) { + my $suffix = ""; + my $newconst = $const; + $newconst =~ s/${Int_type}$//; + $suffix .= 'U' if ($cast =~ /\bunsigned\b/); + if ($cast =~ /\blong\s+long\b/) { + $suffix .= 'LL'; + } elsif ($cast =~ /\blong\b/) { + $suffix .= 'L'; + } + $fixed[$fixlinenr] =~ s/\Q$cast\E$const\b/$newconst$suffix/; + } + } + +# check for sizeof(&) + if ($line =~ /\bsizeof\s*\(\s*\&/) { + WARN("SIZEOF_ADDRESS", + "sizeof(& should be avoided\n" . $herecurr); + } + +# check for sizeof without parenthesis + if ($line =~ /\bsizeof\s+((?:\*\s*|)$Lval|$Type(?:\s+$Lval|))/) { + if (WARN("SIZEOF_PARENTHESIS", + "sizeof $1 should be sizeof($1)\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\bsizeof\s+((?:\*\s*|)$Lval|$Type(?:\s+$Lval|))/"sizeof(" . trim($1) . ")"/ex; + } + } + +# check for struct spinlock declarations + if ($line =~ /^.\s*\bstruct\s+spinlock\s+\w+\s*;/) { + WARN("USE_SPINLOCK_T", + "struct spinlock should be spinlock_t\n" . $herecurr); + } + +# check for seq_printf uses that could be seq_puts + if ($sline =~ /\bseq_printf\s*\(.*"\s*\)\s*;\s*$/) { + my $fmt = get_quoted_string($line, $rawline); + $fmt =~ s/%%//g; + if ($fmt !~ /%/) { + if (WARN("PREFER_SEQ_PUTS", + "Prefer seq_puts to seq_printf\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\bseq_printf\b/seq_puts/; + } + } + } + +# check for vsprintf extension %p<foo> misuses + if ($perl_version_ok && + defined $stat && + $stat =~ /^\+(?![^\{]*\{\s*).*\b(\w+)\s*\(.*$String\s*,/s && + $1 !~ /^_*volatile_*$/) { + my $stat_real; + + my $lc = $stat =~ tr@\n@@; + $lc = $lc + $linenr; + for (my $count = $linenr; $count <= $lc; $count++) { + my $specifier; + my $extension; + my $qualifier; + my $bad_specifier = ""; + my $fmt = get_quoted_string($lines[$count - 1], raw_line($count, 0)); + $fmt =~ s/%%//g; + + while ($fmt =~ /(\%[\*\d\.]*p(\w)(\w*))/g) { + $specifier = $1; + $extension = $2; + $qualifier = $3; + if ($extension !~ /[SsBKRraEehMmIiUDdgVCbGNOxtf]/ || + ($extension eq "f" && + defined $qualifier && $qualifier !~ /^w/)) { + $bad_specifier = $specifier; + last; + } + if ($extension eq "x" && !defined($stat_real)) { + if (!defined($stat_real)) { + $stat_real = get_stat_real($linenr, $lc); + } + WARN("VSPRINTF_SPECIFIER_PX", + "Using vsprintf specifier '\%px' potentially exposes the kernel memory layout, if you don't really need the address please consider using '\%p'.\n" . "$here\n$stat_real\n"); + } + } + if ($bad_specifier ne "") { + my $stat_real = get_stat_real($linenr, $lc); + my $ext_type = "Invalid"; + my $use = ""; + if ($bad_specifier =~ /p[Ff]/) { + $use = " - use %pS instead"; + $use =~ s/pS/ps/ if ($bad_specifier =~ /pf/); + } + + WARN("VSPRINTF_POINTER_EXTENSION", + "$ext_type vsprintf pointer extension '$bad_specifier'$use\n" . "$here\n$stat_real\n"); + } + } + } + +# Check for misused memsets + if ($perl_version_ok && + defined $stat && + $stat =~ /^\+(?:.*?)\bmemset\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\,\s*$FuncArg\s*\)/) { + + my $ms_addr = $2; + my $ms_val = $7; + my $ms_size = $12; + + if ($ms_size =~ /^(0x|)0$/i) { + ERROR("MEMSET", + "memset to 0's uses 0 as the 2nd argument, not the 3rd\n" . "$here\n$stat\n"); + } elsif ($ms_size =~ /^(0x|)1$/i) { + WARN("MEMSET", + "single byte memset is suspicious. Swapped 2nd/3rd argument?\n" . "$here\n$stat\n"); + } + } + +# Check for memcpy(foo, bar, ETH_ALEN) that could be ether_addr_copy(foo, bar) +# if ($perl_version_ok && +# defined $stat && +# $stat =~ /^\+(?:.*?)\bmemcpy\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\,\s*ETH_ALEN\s*\)/) { +# if (WARN("PREFER_ETHER_ADDR_COPY", +# "Prefer ether_addr_copy() over memcpy() if the Ethernet addresses are __aligned(2)\n" . "$here\n$stat\n") && +# $fix) { +# $fixed[$fixlinenr] =~ s/\bmemcpy\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\,\s*ETH_ALEN\s*\)/ether_addr_copy($2, $7)/; +# } +# } + +# Check for memcmp(foo, bar, ETH_ALEN) that could be ether_addr_equal*(foo, bar) +# if ($perl_version_ok && +# defined $stat && +# $stat =~ /^\+(?:.*?)\bmemcmp\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\,\s*ETH_ALEN\s*\)/) { +# WARN("PREFER_ETHER_ADDR_EQUAL", +# "Prefer ether_addr_equal() or ether_addr_equal_unaligned() over memcmp()\n" . "$here\n$stat\n") +# } + +# check for memset(foo, 0x0, ETH_ALEN) that could be eth_zero_addr +# check for memset(foo, 0xFF, ETH_ALEN) that could be eth_broadcast_addr +# if ($perl_version_ok && +# defined $stat && +# $stat =~ /^\+(?:.*?)\bmemset\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\,\s*ETH_ALEN\s*\)/) { +# +# my $ms_val = $7; +# +# if ($ms_val =~ /^(?:0x|)0+$/i) { +# if (WARN("PREFER_ETH_ZERO_ADDR", +# "Prefer eth_zero_addr over memset()\n" . "$here\n$stat\n") && +# $fix) { +# $fixed[$fixlinenr] =~ s/\bmemset\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*,\s*ETH_ALEN\s*\)/eth_zero_addr($2)/; +# } +# } elsif ($ms_val =~ /^(?:0xff|255)$/i) { +# if (WARN("PREFER_ETH_BROADCAST_ADDR", +# "Prefer eth_broadcast_addr() over memset()\n" . "$here\n$stat\n") && +# $fix) { +# $fixed[$fixlinenr] =~ s/\bmemset\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*,\s*ETH_ALEN\s*\)/eth_broadcast_addr($2)/; +# } +# } +# } + +# typecasts on min/max could be min_t/max_t + if ($perl_version_ok && + defined $stat && + $stat =~ /^\+(?:.*?)\b(min|max)\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\)/) { + if (defined $2 || defined $7) { + my $call = $1; + my $cast1 = deparenthesize($2); + my $arg1 = $3; + my $cast2 = deparenthesize($7); + my $arg2 = $8; + my $cast; + + if ($cast1 ne "" && $cast2 ne "" && $cast1 ne $cast2) { + $cast = "$cast1 or $cast2"; + } elsif ($cast1 ne "") { + $cast = $cast1; + } else { + $cast = $cast2; + } + WARN("MINMAX", + "$call() should probably be ${call}_t($cast, $arg1, $arg2)\n" . "$here\n$stat\n"); + } + } + +# check usleep_range arguments + if ($perl_version_ok && + defined $stat && + $stat =~ /^\+(?:.*?)\busleep_range\s*\(\s*($FuncArg)\s*,\s*($FuncArg)\s*\)/) { + my $min = $1; + my $max = $7; + if ($min eq $max) { + WARN("USLEEP_RANGE", + "usleep_range should not use min == max args; see Documentation/timers/timers-howto.rst\n" . "$here\n$stat\n"); + } elsif ($min =~ /^\d+$/ && $max =~ /^\d+$/ && + $min > $max) { + WARN("USLEEP_RANGE", + "usleep_range args reversed, use min then max; see Documentation/timers/timers-howto.rst\n" . "$here\n$stat\n"); + } + } + +# check for naked sscanf + if ($perl_version_ok && + defined $stat && + $line =~ /\bsscanf\b/ && + ($stat !~ /$Ident\s*=\s*sscanf\s*$balanced_parens/ && + $stat !~ /\bsscanf\s*$balanced_parens\s*(?:$Compare)/ && + $stat !~ /(?:$Compare)\s*\bsscanf\s*$balanced_parens/)) { + my $lc = $stat =~ tr@\n@@; + $lc = $lc + $linenr; + my $stat_real = get_stat_real($linenr, $lc); + WARN("NAKED_SSCANF", + "unchecked sscanf return value\n" . "$here\n$stat_real\n"); + } + +# check for simple sscanf that should be kstrto<foo> + if ($perl_version_ok && + defined $stat && + $line =~ /\bsscanf\b/) { + my $lc = $stat =~ tr@\n@@; + $lc = $lc + $linenr; + my $stat_real = get_stat_real($linenr, $lc); + if ($stat_real =~ /\bsscanf\b\s*\(\s*$FuncArg\s*,\s*("[^"]+")/) { + my $format = $6; + my $count = $format =~ tr@%@%@; + if ($count == 1 && + $format =~ /^"\%(?i:ll[udxi]|[udxi]ll|ll|[hl]h?[udxi]|[udxi][hl]h?|[hl]h?|[udxi])"$/) { + WARN("SSCANF_TO_KSTRTO", + "Prefer kstrto<type> to single variable sscanf\n" . "$here\n$stat_real\n"); + } + } + } + +# check for new externs in .h files. + if ($realfile =~ /\.h$/ && + $line =~ /^\+\s*(extern\s+)$Type\s*$Ident\s*\(/s) { + if (CHK("AVOID_EXTERNS", + "extern prototypes should be avoided in .h files\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/(.*)\bextern\b\s*(.*)/$1$2/; + } + } + +# check for new externs in .c files. + if ($realfile =~ /\.c$/ && defined $stat && + $stat =~ /^.\s*(?:extern\s+)?$Type\s+($Ident)(\s*)\(/s) + { + my $function_name = $1; + my $paren_space = $2; + + my $s = $stat; + if (defined $cond) { + substr($s, 0, length($cond), ''); + } + if ($s =~ /^\s*;/) + { + WARN("AVOID_EXTERNS", + "externs should be avoided in .c files\n" . $herecurr); + } + + if ($paren_space =~ /\n/) { + WARN("FUNCTION_ARGUMENTS", + "arguments for function declarations should follow identifier\n" . $herecurr); + } + + } elsif ($realfile =~ /\.c$/ && defined $stat && + $stat =~ /^.\s*extern\s+/) + { + WARN("AVOID_EXTERNS", + "externs should be avoided in .c files\n" . $herecurr); + } + +# check for function declarations that have arguments without identifier names + if (defined $stat && + $stat =~ /^.\s*(?:extern\s+)?$Type\s*(?:$Ident|\(\s*\*\s*$Ident\s*\))\s*\(\s*([^{]+)\s*\)\s*;/s && + $1 ne "void") { + my $args = trim($1); + while ($args =~ m/\s*($Type\s*(?:$Ident|\(\s*\*\s*$Ident?\s*\)\s*$balanced_parens)?)/g) { + my $arg = trim($1); + if ($arg =~ /^$Type$/ && $arg !~ /enum\s+$Ident$/) { + WARN("FUNCTION_ARGUMENTS", + "function definition argument '$arg' should also have an identifier name\n" . $herecurr); + } + } + } + +# check for function definitions + if ($perl_version_ok && + defined $stat && + $stat =~ /^.\s*(?:$Storage\s+)?$Type\s*($Ident)\s*$balanced_parens\s*{/s) { + $context_function = $1; + +# check for multiline function definition with misplaced open brace + my $ok = 0; + my $cnt = statement_rawlines($stat); + my $herectx = $here . "\n"; + for (my $n = 0; $n < $cnt; $n++) { + my $rl = raw_line($linenr, $n); + $herectx .= $rl . "\n"; + $ok = 1 if ($rl =~ /^[ \+]\{/); + $ok = 1 if ($rl =~ /\{/ && $n == 0); + last if $rl =~ /^[ \+].*\{/; + } + if (!$ok) { + ERROR("OPEN_BRACE", + "open brace '{' following function definitions go on the next line\n" . $herectx); + } + } + +# checks for new __setup's + if ($rawline =~ /\b__setup\("([^"]*)"/) { + my $name = $1; + + if (!grep(/$name/, @setup_docs)) { + CHK("UNDOCUMENTED_SETUP", + "__setup appears un-documented -- check Documentation/admin-guide/kernel-parameters.txt\n" . $herecurr); + } + } + +# check for pointless casting of alloc functions + if ($line =~ /\*\s*\)\s*$allocFunctions\b/) { + WARN("UNNECESSARY_CASTS", + "unnecessary cast may hide bugs, see http://c-faq.com/malloc/mallocnocast.html\n" . $herecurr); + } + +# alloc style +# p = alloc(sizeof(struct foo), ...) should be p = alloc(sizeof(*p), ...) + if ($perl_version_ok && + $line =~ /\b($Lval)\s*\=\s*(?:$balanced_parens)?\s*((?:kv|k|v)[mz]alloc(?:_node)?)\s*\(\s*(sizeof\s*\(\s*struct\s+$Lval\s*\))/) { + CHK("ALLOC_SIZEOF_STRUCT", + "Prefer $3(sizeof(*$1)...) over $3($4...)\n" . $herecurr); + } + +# check for k[mz]alloc with multiplies that could be kmalloc_array/kcalloc + if ($perl_version_ok && + defined $stat && + $stat =~ /^\+\s*($Lval)\s*\=\s*(?:$balanced_parens)?\s*(k[mz]alloc)\s*\(\s*($FuncArg)\s*\*\s*($FuncArg)\s*,/) { + my $oldfunc = $3; + my $a1 = $4; + my $a2 = $10; + my $newfunc = "kmalloc_array"; + $newfunc = "kcalloc" if ($oldfunc eq "kzalloc"); + my $r1 = $a1; + my $r2 = $a2; + if ($a1 =~ /^sizeof\s*\S/) { + $r1 = $a2; + $r2 = $a1; + } + if ($r1 !~ /^sizeof\b/ && $r2 =~ /^sizeof\s*\S/ && + !($r1 =~ /^$Constant$/ || $r1 =~ /^[A-Z_][A-Z0-9_]*$/)) { + my $cnt = statement_rawlines($stat); + my $herectx = get_stat_here($linenr, $cnt, $here); + + if (WARN("ALLOC_WITH_MULTIPLY", + "Prefer $newfunc over $oldfunc with multiply\n" . $herectx) && + $cnt == 1 && + $fix) { + $fixed[$fixlinenr] =~ s/\b($Lval)\s*\=\s*(?:$balanced_parens)?\s*(k[mz]alloc)\s*\(\s*($FuncArg)\s*\*\s*($FuncArg)/$1 . ' = ' . "$newfunc(" . trim($r1) . ', ' . trim($r2)/e; + } + } + } + +# check for krealloc arg reuse + if ($perl_version_ok && + $line =~ /\b($Lval)\s*\=\s*(?:$balanced_parens)?\s*krealloc\s*\(\s*($Lval)\s*,/ && + $1 eq $3) { + WARN("KREALLOC_ARG_REUSE", + "Reusing the krealloc arg is almost always a bug\n" . $herecurr); + } + +# check for alloc argument mismatch + if ($line =~ /\b(kcalloc|kmalloc_array)\s*\(\s*sizeof\b/) { + WARN("ALLOC_ARRAY_ARGS", + "$1 uses number as first arg, sizeof is generally wrong\n" . $herecurr); + } + +# check for multiple semicolons + if ($line =~ /;\s*;\s*$/) { + if (WARN("ONE_SEMICOLON", + "Statements terminations use 1 semicolon\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/(\s*;\s*){2,}$/;/g; + } + } + +# check for #defines like: 1 << <digit> that could be BIT(digit), it is not exported to uapi + if ($realfile !~ m@^include/uapi/@ && + $line =~ /#\s*define\s+\w+\s+\(?\s*1\s*([ulUL]*)\s*\<\<\s*(?:\d+|$Ident)\s*\)?/) { + my $ull = ""; + $ull = "_ULL" if (defined($1) && $1 =~ /ll/i); + if (CHK("BIT_MACRO", + "Prefer using the BIT$ull macro\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\(?\s*1\s*[ulUL]*\s*<<\s*(\d+|$Ident)\s*\)?/BIT${ull}($1)/; + } + } + +# check for IS_ENABLED() without CONFIG_<FOO> ($rawline for comments too) + if ($rawline =~ /\bIS_ENABLED\s*\(\s*(\w+)\s*\)/ && $1 !~ /^${CONFIG_}/) { + WARN("IS_ENABLED_CONFIG", + "IS_ENABLED($1) is normally used as IS_ENABLED(${CONFIG_}$1)\n" . $herecurr); + } + +# check for #if defined CONFIG_<FOO> || defined CONFIG_<FOO>_MODULE + if ($line =~ /^\+\s*#\s*if\s+defined(?:\s*\(?\s*|\s+)(${CONFIG_}[A-Z_]+)\s*\)?\s*\|\|\s*defined(?:\s*\(?\s*|\s+)\1_MODULE\s*\)?\s*$/) { + my $config = $1; + if (WARN("PREFER_IS_ENABLED", + "Prefer IS_ENABLED(<FOO>) to ${CONFIG_}<FOO> || ${CONFIG_}<FOO>_MODULE\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] = "\+#if IS_ENABLED($config)"; + } + } + +# check for /* fallthrough */ like comment, prefer fallthrough; + my @fallthroughs = ( + 'fallthrough', + '@fallthrough@', + 'lint -fallthrough[ \t]*', + 'intentional(?:ly)?[ \t]*fall(?:(?:s | |-)[Tt]|t)hr(?:ough|u|ew)', + '(?:else,?\s*)?FALL(?:S | |-)?THR(?:OUGH|U|EW)[ \t.!]*(?:-[^\n\r]*)?', + 'Fall(?:(?:s | |-)[Tt]|t)hr(?:ough|u|ew)[ \t.!]*(?:-[^\n\r]*)?', + 'fall(?:s | |-)?thr(?:ough|u|ew)[ \t.!]*(?:-[^\n\r]*)?', + ); + if ($raw_comment ne '') { + foreach my $ft (@fallthroughs) { + if ($raw_comment =~ /$ft/) { + my $msg_level = \&WARN; + $msg_level = \&CHK if ($file); + &{$msg_level}("PREFER_FALLTHROUGH", + "Prefer 'fallthrough;' over fallthrough comment\n" . $herecurr); + last; + } + } + } + +# check for switch/default statements without a break; + if ($perl_version_ok && + defined $stat && + $stat =~ /^\+[$;\s]*(?:case[$;\s]+\w+[$;\s]*:[$;\s]*|)*[$;\s]*\bdefault[$;\s]*:[$;\s]*;/g) { + my $cnt = statement_rawlines($stat); + my $herectx = get_stat_here($linenr, $cnt, $here); + + WARN("DEFAULT_NO_BREAK", + "switch default: should use break\n" . $herectx); + } + +# check for gcc specific __FUNCTION__ + if ($line =~ /\b__FUNCTION__\b/) { + if (WARN("USE_FUNC", + "__func__ should be used instead of gcc specific __FUNCTION__\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\b__FUNCTION__\b/__func__/g; + } + } + +# check for uses of __DATE__, __TIME__, __TIMESTAMP__ + while ($line =~ /\b(__(?:DATE|TIME|TIMESTAMP)__)\b/g) { + ERROR("DATE_TIME", + "Use of the '$1' macro makes the build non-deterministic\n" . $herecurr); + } + +# check for use of yield() + if ($line =~ /\byield\s*\(\s*\)/) { + WARN("YIELD", + "Using yield() is generally wrong. See yield() kernel-doc (sched/core.c)\n" . $herecurr); + } + +# check for comparisons against true and false + if ($line =~ /\+\s*(.*?)\b(true|false|$Lval)\s*(==|\!=)\s*(true|false|$Lval)\b(.*)$/i) { + my $lead = $1; + my $arg = $2; + my $test = $3; + my $otype = $4; + my $trail = $5; + my $op = "!"; + + ($arg, $otype) = ($otype, $arg) if ($arg =~ /^(?:true|false)$/i); + + my $type = lc($otype); + if ($type =~ /^(?:true|false)$/) { + if (("$test" eq "==" && "$type" eq "true") || + ("$test" eq "!=" && "$type" eq "false")) { + $op = ""; + } + + CHK("BOOL_COMPARISON", + "Using comparison to $otype is error prone\n" . $herecurr); + +## maybe suggesting a correct construct would better +## "Using comparison to $otype is error prone. Perhaps use '${lead}${op}${arg}${trail}'\n" . $herecurr); + + } + } + +# check for semaphores initialized locked + if ($line =~ /^.\s*sema_init.+,\W?0\W?\)/) { + WARN("CONSIDER_COMPLETION", + "consider using a completion\n" . $herecurr); + } + +# recommend kstrto* over simple_strto* and strict_strto* + if ($line =~ /\b((simple|strict)_(strto(l|ll|ul|ull)))\s*\(/) { + WARN("CONSIDER_KSTRTO", + "$1 is obsolete, use k$3 instead\n" . $herecurr); + } + +# check for __initcall(), use device_initcall() explicitly or more appropriate function please + if ($line =~ /^.\s*__initcall\s*\(/) { + WARN("USE_DEVICE_INITCALL", + "please use device_initcall() or more appropriate function instead of __initcall() (see include/linux/init.h)\n" . $herecurr); + } + +# check for spin_is_locked(), suggest lockdep instead + if ($line =~ /\bspin_is_locked\(/) { + WARN("USE_LOCKDEP", + "Where possible, use lockdep_assert_held instead of assertions based on spin_is_locked\n" . $herecurr); + } + +# check for deprecated apis + if ($line =~ /\b($deprecated_apis_search)\b\s*\(/) { + my $deprecated_api = $1; + my $new_api = $deprecated_apis{$deprecated_api}; + WARN("DEPRECATED_API", + "Deprecated use of '$deprecated_api', prefer '$new_api' instead\n" . $herecurr); + } + +# check for various structs that are normally const (ops, kgdb, device_tree) +# and avoid what seem like struct definitions 'struct foo {' + if (defined($const_structs) && + $line !~ /\bconst\b/ && + $line =~ /\bstruct\s+($const_structs)\b(?!\s*\{)/) { + WARN("CONST_STRUCT", + "struct $1 should normally be const\n" . $herecurr); + } + +# use of NR_CPUS is usually wrong +# ignore definitions of NR_CPUS and usage to define arrays as likely right + if ($line =~ /\bNR_CPUS\b/ && + $line !~ /^.\s*\s*#\s*if\b.*\bNR_CPUS\b/ && + $line !~ /^.\s*\s*#\s*define\b.*\bNR_CPUS\b/ && + $line !~ /^.\s*$Declare\s.*\[[^\]]*NR_CPUS[^\]]*\]/ && + $line !~ /\[[^\]]*\.\.\.[^\]]*NR_CPUS[^\]]*\]/ && + $line !~ /\[[^\]]*NR_CPUS[^\]]*\.\.\.[^\]]*\]/) + { + WARN("NR_CPUS", + "usage of NR_CPUS is often wrong - consider using cpu_possible(), num_possible_cpus(), for_each_possible_cpu(), etc\n" . $herecurr); + } + +# Use of __ARCH_HAS_<FOO> or ARCH_HAVE_<BAR> is wrong. + if ($line =~ /\+\s*#\s*define\s+((?:__)?ARCH_(?:HAS|HAVE)\w*)\b/) { + ERROR("DEFINE_ARCH_HAS", + "#define of '$1' is wrong - use Kconfig variables or standard guards instead\n" . $herecurr); + } + +# likely/unlikely comparisons similar to "(likely(foo) > 0)" + if ($perl_version_ok && + $line =~ /\b((?:un)?likely)\s*\(\s*$FuncArg\s*\)\s*$Compare/) { + WARN("LIKELY_MISUSE", + "Using $1 should generally have parentheses around the comparison\n" . $herecurr); + } + +# nested likely/unlikely calls + if ($line =~ /\b(?:(?:un)?likely)\s*\(\s*!?\s*(IS_ERR(?:_OR_NULL|_VALUE)?|WARN)/) { + WARN("LIKELY_MISUSE", + "nested (un)?likely() calls, $1 already uses unlikely() internally\n" . $herecurr); + } + +# whine mightly about in_atomic + if ($line =~ /\bin_atomic\s*\(/) { + if ($realfile =~ m@^drivers/@) { + ERROR("IN_ATOMIC", + "do not use in_atomic in drivers\n" . $herecurr); + } elsif ($realfile !~ m@^kernel/@) { + WARN("IN_ATOMIC", + "use of in_atomic() is incorrect outside core kernel code\n" . $herecurr); + } + } + +# check for mutex_trylock_recursive usage + if ($line =~ /mutex_trylock_recursive/) { + ERROR("LOCKING", + "recursive locking is bad, do not use this ever.\n" . $herecurr); + } + +# check for lockdep_set_novalidate_class + if ($line =~ /^.\s*lockdep_set_novalidate_class\s*\(/ || + $line =~ /__lockdep_no_validate__\s*\)/ ) { + if ($realfile !~ m@^kernel/lockdep@ && + $realfile !~ m@^include/linux/lockdep@ && + $realfile !~ m@^drivers/base/core@) { + ERROR("LOCKDEP", + "lockdep_no_validate class is reserved for device->mutex.\n" . $herecurr); + } + } + + if ($line =~ /debugfs_create_\w+.*\b$mode_perms_world_writable\b/ || + $line =~ /DEVICE_ATTR.*\b$mode_perms_world_writable\b/) { + WARN("EXPORTED_WORLD_WRITABLE", + "Exporting world writable files is usually an error. Consider more restrictive permissions.\n" . $herecurr); + } + +# check for DEVICE_ATTR uses that could be DEVICE_ATTR_<FOO> +# and whether or not function naming is typical and if +# DEVICE_ATTR permissions uses are unusual too + if ($perl_version_ok && + defined $stat && + $stat =~ /\bDEVICE_ATTR\s*\(\s*(\w+)\s*,\s*\(?\s*(\s*(?:${multi_mode_perms_string_search}|0[0-7]{3,3})\s*)\s*\)?\s*,\s*(\w+)\s*,\s*(\w+)\s*\)/) { + my $var = $1; + my $perms = $2; + my $show = $3; + my $store = $4; + my $octal_perms = perms_to_octal($perms); + if ($show =~ /^${var}_show$/ && + $store =~ /^${var}_store$/ && + $octal_perms eq "0644") { + if (WARN("DEVICE_ATTR_RW", + "Use DEVICE_ATTR_RW\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\bDEVICE_ATTR\s*\(\s*$var\s*,\s*\Q$perms\E\s*,\s*$show\s*,\s*$store\s*\)/DEVICE_ATTR_RW(${var})/; + } + } elsif ($show =~ /^${var}_show$/ && + $store =~ /^NULL$/ && + $octal_perms eq "0444") { + if (WARN("DEVICE_ATTR_RO", + "Use DEVICE_ATTR_RO\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\bDEVICE_ATTR\s*\(\s*$var\s*,\s*\Q$perms\E\s*,\s*$show\s*,\s*NULL\s*\)/DEVICE_ATTR_RO(${var})/; + } + } elsif ($show =~ /^NULL$/ && + $store =~ /^${var}_store$/ && + $octal_perms eq "0200") { + if (WARN("DEVICE_ATTR_WO", + "Use DEVICE_ATTR_WO\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\bDEVICE_ATTR\s*\(\s*$var\s*,\s*\Q$perms\E\s*,\s*NULL\s*,\s*$store\s*\)/DEVICE_ATTR_WO(${var})/; + } + } elsif ($octal_perms eq "0644" || + $octal_perms eq "0444" || + $octal_perms eq "0200") { + my $newshow = "$show"; + $newshow = "${var}_show" if ($show ne "NULL" && $show ne "${var}_show"); + my $newstore = $store; + $newstore = "${var}_store" if ($store ne "NULL" && $store ne "${var}_store"); + my $rename = ""; + if ($show ne $newshow) { + $rename .= " '$show' to '$newshow'"; + } + if ($store ne $newstore) { + $rename .= " '$store' to '$newstore'"; + } + WARN("DEVICE_ATTR_FUNCTIONS", + "Consider renaming function(s)$rename\n" . $herecurr); + } else { + WARN("DEVICE_ATTR_PERMS", + "DEVICE_ATTR unusual permissions '$perms' used\n" . $herecurr); + } + } + +# Mode permission misuses where it seems decimal should be octal +# This uses a shortcut match to avoid unnecessary uses of a slow foreach loop +# o Ignore module_param*(...) uses with a decimal 0 permission as that has a +# specific definition of not visible in sysfs. +# o Ignore proc_create*(...) uses with a decimal 0 permission as that means +# use the default permissions + if ($perl_version_ok && + defined $stat && + $line =~ /$mode_perms_search/) { + foreach my $entry (@mode_permission_funcs) { + my $func = $entry->[0]; + my $arg_pos = $entry->[1]; + + my $lc = $stat =~ tr@\n@@; + $lc = $lc + $linenr; + my $stat_real = get_stat_real($linenr, $lc); + + my $skip_args = ""; + if ($arg_pos > 1) { + $arg_pos--; + $skip_args = "(?:\\s*$FuncArg\\s*,\\s*){$arg_pos,$arg_pos}"; + } + my $test = "\\b$func\\s*\\(${skip_args}($FuncArg(?:\\|\\s*$FuncArg)*)\\s*[,\\)]"; + if ($stat =~ /$test/) { + my $val = $1; + $val = $6 if ($skip_args ne ""); + if (!($func =~ /^(?:module_param|proc_create)/ && $val eq "0") && + (($val =~ /^$Int$/ && $val !~ /^$Octal$/) || + ($val =~ /^$Octal$/ && length($val) ne 4))) { + ERROR("NON_OCTAL_PERMISSIONS", + "Use 4 digit octal (0777) not decimal permissions\n" . "$here\n" . $stat_real); + } + if ($val =~ /^$Octal$/ && (oct($val) & 02)) { + ERROR("EXPORTED_WORLD_WRITABLE", + "Exporting writable files is usually an error. Consider more restrictive permissions.\n" . "$here\n" . $stat_real); + } + } + } + } + +# check for uses of S_<PERMS> that could be octal for readability + while ($line =~ m{\b($multi_mode_perms_string_search)\b}g) { + my $oval = $1; + my $octal = perms_to_octal($oval); + if (WARN("SYMBOLIC_PERMS", + "Symbolic permissions '$oval' are not preferred. Consider using octal permissions '$octal'.\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\Q$oval\E/$octal/; + } + } + +# validate content of MODULE_LICENSE against list from include/linux/module.h + if ($line =~ /\bMODULE_LICENSE\s*\(\s*($String)\s*\)/) { + my $extracted_string = get_quoted_string($line, $rawline); + my $valid_licenses = qr{ + GPL| + GPL\ v2| + GPL\ and\ additional\ rights| + Dual\ BSD/GPL| + Dual\ MIT/GPL| + Dual\ MPL/GPL| + Proprietary + }x; + if ($extracted_string !~ /^"(?:$valid_licenses)"$/x) { + WARN("MODULE_LICENSE", + "unknown module license " . $extracted_string . "\n" . $herecurr); + } + } + +# check for sysctl duplicate constants + if ($line =~ /\.extra[12]\s*=\s*&(zero|one|int_max)\b/) { + WARN("DUPLICATED_SYSCTL_CONST", + "duplicated sysctl range checking value '$1', consider using the shared one in include/linux/sysctl.h\n" . $herecurr); + } + } + + # If we have no input at all, then there is nothing to report on + # so just keep quiet. + if ($#rawlines == -1) { + exit(0); + } + + # In mailback mode only produce a report in the negative, for + # things that appear to be patches. + if ($mailback && ($clean == 1 || !$is_patch)) { + exit(0); + } + + # This is not a patch, and we are are in 'no-patch' mode so + # just keep quiet. + if (!$chk_patch && !$is_patch) { + exit(0); + } + + if (!$is_patch && $filename !~ /cover-letter\.patch$/) { + ERROR("NOT_UNIFIED_DIFF", + "Does not appear to be a unified-diff format patch\n"); + } + if ($is_patch && $has_commit_log && $chk_signoff) { + if ($signoff == 0) { + ERROR("MISSING_SIGN_OFF", + "Missing Signed-off-by: line(s)\n"); + } elsif ($authorsignoff != 1) { + # authorsignoff values: + # 0 -> missing sign off + # 1 -> sign off identical + # 2 -> names and addresses match, comments mismatch + # 3 -> addresses match, names different + # 4 -> names match, addresses different + # 5 -> names match, addresses excluding subaddress details (refer RFC 5233) match + + my $sob_msg = "'From: $author' != 'Signed-off-by: $author_sob'"; + + if ($authorsignoff == 0) { + ERROR("NO_AUTHOR_SIGN_OFF", + "Missing Signed-off-by: line by nominal patch author '$author'\n"); + } elsif ($authorsignoff == 2) { + CHK("FROM_SIGN_OFF_MISMATCH", + "From:/Signed-off-by: email comments mismatch: $sob_msg\n"); + } elsif ($authorsignoff == 3) { + WARN("FROM_SIGN_OFF_MISMATCH", + "From:/Signed-off-by: email name mismatch: $sob_msg\n"); + } elsif ($authorsignoff == 4) { + WARN("FROM_SIGN_OFF_MISMATCH", + "From:/Signed-off-by: email address mismatch: $sob_msg\n"); + } elsif ($authorsignoff == 5) { + WARN("FROM_SIGN_OFF_MISMATCH", + "From:/Signed-off-by: email subaddress mismatch: $sob_msg\n"); + } + } + } + + print report_dump(); + if ($summary && !($clean == 1 && $quiet == 1)) { + print "$filename " if ($summary_file); + print "total: $cnt_error errors, $cnt_warn warnings, " . + (($check)? "$cnt_chk checks, " : "") . + "$cnt_lines lines checked\n"; + } + + if ($quiet == 0) { + # If there were any defects found and not already fixing them + if (!$clean and !$fix) { + print << "EOM" + +NOTE: For some of the reported defects, checkpatch may be able to + mechanically convert to the typical style using --fix or --fix-inplace. +EOM + } + # If there were whitespace errors which cleanpatch can fix + # then suggest that. + if ($rpt_cleaners) { + $rpt_cleaners = 0; + print << "EOM" + +NOTE: Whitespace errors detected. + You may wish to use scripts/cleanpatch or scripts/cleanfile +EOM + } + } + + if ($clean == 0 && $fix && + ("@rawlines" ne "@fixed" || + $#fixed_inserted >= 0 || $#fixed_deleted >= 0)) { + my $newfile = $filename; + $newfile .= ".EXPERIMENTAL-checkpatch-fixes" if (!$fix_inplace); + my $linecount = 0; + my $f; + + @fixed = fix_inserted_deleted_lines(\@fixed, \@fixed_inserted, \@fixed_deleted); + + open($f, '>', $newfile) + or die "$P: Can't open $newfile for write\n"; + foreach my $fixed_line (@fixed) { + $linecount++; + if ($file) { + if ($linecount > 3) { + $fixed_line =~ s/^\+//; + print $f $fixed_line . "\n"; + } + } else { + print $f $fixed_line . "\n"; + } + } + close($f); + + if (!$quiet) { + print << "EOM"; + +Wrote EXPERIMENTAL --fix correction(s) to '$newfile' + +Do _NOT_ trust the results written to this file. +Do _NOT_ submit these changes without inspecting them for correctness. + +This EXPERIMENTAL file is simply a convenience to help rewrite patches. +No warranties, expressed or implied... +EOM + } + } + + if ($quiet == 0) { + print "\n"; + if ($clean == 1) { + print "$vname has no obvious style problems and is ready for submission.\n"; + } else { + print "$vname has style problems, please review.\n"; + } + } + return $clean; +} diff --git a/src/net/scripts/checkstack.pl b/src/net/scripts/checkstack.pl new file mode 100755 index 0000000..d2c3858 --- /dev/null +++ b/src/net/scripts/checkstack.pl @@ -0,0 +1,201 @@ +#!/usr/bin/env perl +# SPDX-License-Identifier: GPL-2.0 + +# Check the stack usage of functions +# +# Copyright Joern Engel <joern@lazybastard.org> +# Inspired by Linus Torvalds +# Original idea maybe from Keith Owens +# s390 port and big speedup by Arnd Bergmann <arnd@bergmann-dalldorf.de> +# Mips port by Juan Quintela <quintela@mandrakesoft.com> +# IA64 port via Andreas Dilger +# Arm port by Holger Schurig +# sh64 port by Paul Mundt +# Random bits by Matt Mackall <mpm@selenic.com> +# M68k port by Geert Uytterhoeven and Andreas Schwab +# AArch64, PARISC ports by Kyle McMartin +# sparc port by Martin Habets <errandir_news@mph.eclipse.co.uk> +# ppc64le port by Breno Leitao <leitao@debian.org> +# +# Usage: +# objdump -d vmlinux | scripts/checkstack.pl [arch] +# +# TODO : Port to all architectures (one regex per arch) + +use strict; + +# check for arch +# +# $re is used for two matches: +# $& (whole re) matches the complete objdump line with the stack growth +# $1 (first bracket) matches the size of the stack growth +# +# $dre is similar, but for dynamic stack redutions: +# $& (whole re) matches the complete objdump line with the stack growth +# $1 (first bracket) matches the dynamic amount of the stack growth +# +# $sub: subroutine for special handling to check stack usage. +# +# use anything else and feel the pain ;) +my (@stack, $re, $dre, $sub, $x, $xs, $funcre, $min_stack); +{ + my $arch = shift; + if ($arch eq "") { + $arch = `uname -m`; + chomp($arch); + } + + $min_stack = shift; + if ($min_stack eq "" || $min_stack !~ /^\d+$/) { + $min_stack = 100; + } + + $x = "[0-9a-f]"; # hex character + $xs = "[0-9a-f ]"; # hex character or space + $funcre = qr/^$x* <(.*)>:$/; + if ($arch =~ '^(aarch|arm)64$') { + #ffffffc0006325cc: a9bb7bfd stp x29, x30, [sp, #-80]! + #a110: d11643ff sub sp, sp, #0x590 + $re = qr/^.*stp.*sp, \#-([0-9]{1,8})\]\!/o; + $dre = qr/^.*sub.*sp, sp, #(0x$x{1,8})/o; + } elsif ($arch eq 'arm') { + #c0008ffc: e24dd064 sub sp, sp, #100 ; 0x64 + $re = qr/.*sub.*sp, sp, #([0-9]{1,4})/o; + $sub = \&arm_push_handling; + } elsif ($arch =~ /^x86(_64)?$/ || $arch =~ /^i[3456]86$/) { + #c0105234: 81 ec ac 05 00 00 sub $0x5ac,%esp + # or + # 2f60: 48 81 ec e8 05 00 00 sub $0x5e8,%rsp + $re = qr/^.*[as][du][db] \$(0x$x{1,8}),\%(e|r)sp$/o; + $dre = qr/^.*[as][du][db] (%.*),\%(e|r)sp$/o; + } elsif ($arch eq 'ia64') { + #e0000000044011fc: 01 0f fc 8c adds r12=-384,r12 + $re = qr/.*adds.*r12=-(([0-9]{2}|[3-9])[0-9]{2}),r12/o; + } elsif ($arch eq 'm68k') { + # 2b6c: 4e56 fb70 linkw %fp,#-1168 + # 1df770: defc ffe4 addaw #-28,%sp + $re = qr/.*(?:linkw %fp,|addaw )#-([0-9]{1,4})(?:,%sp)?$/o; + } elsif ($arch eq 'mips64') { + #8800402c: 67bdfff0 daddiu sp,sp,-16 + $re = qr/.*daddiu.*sp,sp,-(([0-9]{2}|[3-9])[0-9]{2})/o; + } elsif ($arch eq 'mips') { + #88003254: 27bdffe0 addiu sp,sp,-32 + $re = qr/.*addiu.*sp,sp,-(([0-9]{2}|[3-9])[0-9]{2})/o; + } elsif ($arch eq 'nios2') { + #25a8: defffb04 addi sp,sp,-20 + $re = qr/.*addi.*sp,sp,-(([0-9]{2}|[3-9])[0-9]{2})/o; + } elsif ($arch eq 'openrisc') { + # c000043c: 9c 21 fe f0 l.addi r1,r1,-272 + $re = qr/.*l\.addi.*r1,r1,-(([0-9]{2}|[3-9])[0-9]{2})/o; + } elsif ($arch eq 'parisc' || $arch eq 'parisc64') { + $re = qr/.*ldo ($x{1,8})\(sp\),sp/o; + } elsif ($arch eq 'powerpc' || $arch =~ /^ppc(64)?(le)?$/ ) { + # powerpc : 94 21 ff 30 stwu r1,-208(r1) + # ppc64(le) : 81 ff 21 f8 stdu r1,-128(r1) + $re = qr/.*st[dw]u.*r1,-($x{1,8})\(r1\)/o; + } elsif ($arch =~ /^s390x?$/) { + # 11160: a7 fb ff 60 aghi %r15,-160 + # or + # 100092: e3 f0 ff c8 ff 71 lay %r15,-56(%r15) + $re = qr/.*(?:lay|ag?hi).*\%r15,-(([0-9]{2}|[3-9])[0-9]{2}) + (?:\(\%r15\))?$/ox; + } elsif ($arch =~ /^sh64$/) { + #XXX: we only check for the immediate case presently, + # though we will want to check for the movi/sub + # pair for larger users. -- PFM. + #a00048e0: d4fc40f0 addi.l r15,-240,r15 + $re = qr/.*addi\.l.*r15,-(([0-9]{2}|[3-9])[0-9]{2}),r15/o; + } elsif ($arch eq 'sparc' || $arch eq 'sparc64') { + # f0019d10: 9d e3 bf 90 save %sp, -112, %sp + $re = qr/.*save.*%sp, -(([0-9]{2}|[3-9])[0-9]{2}), %sp/o; + } else { + print("wrong or unknown architecture \"$arch\"\n"); + exit + } +} + +# +# To count stack usage of push {*, fp, ip, lr, pc} instruction in ARM, +# if FRAME POINTER is enabled. +# e.g. c01f0d48: e92ddff0 push {r4, r5, r6, r7, r8, r9, sl, fp, ip, lr, pc} +# +sub arm_push_handling { + my $regex = qr/.*push.*fp, ip, lr, pc}/o; + my $size = 0; + my $line_arg = shift; + + if ($line_arg =~ m/$regex/) { + $size = $line_arg =~ tr/,//; + $size = ($size + 1) * 4; + } + + return $size; +} + +# +# main() +# +my ($func, $file, $lastslash, $total_size, $addr, $intro); + +$total_size = 0; + +while (my $line = <STDIN>) { + if ($line =~ m/$funcre/) { + $func = $1; + next if $line !~ m/^($xs*)/; + if ($total_size > $min_stack) { + push @stack, "$intro$total_size\n"; + } + + $addr = $1; + $addr =~ s/ /0/g; + $addr = "0x$addr"; + + $intro = "$addr $func [$file]:"; + my $padlen = 56 - length($intro); + while ($padlen > 0) { + $intro .= ' '; + $padlen -= 8; + } + + $total_size = 0; + } + elsif ($line =~ m/(.*):\s*file format/) { + $file = $1; + $file =~ s/\.ko//; + $lastslash = rindex($file, "/"); + if ($lastslash != -1) { + $file = substr($file, $lastslash + 1); + } + } + elsif ($line =~ m/$re/) { + my $size = $1; + $size = hex($size) if ($size =~ /^0x/); + + if ($size > 0xf0000000) { + $size = - $size; + $size += 0x80000000; + $size += 0x80000000; + } + next if ($size > 0x10000000); + + $total_size += $size; + } + elsif (defined $dre && $line =~ m/$dre/) { + my $size = $1; + + $size = hex($size) if ($size =~ /^0x/); + $total_size += $size; + } + elsif (defined $sub) { + my $size = &$sub($line); + + $total_size += $size; + } +} +if ($total_size > $min_stack) { + push @stack, "$intro$total_size\n"; +} + +# Sort output by size (last field) +print sort { ($b =~ /:\t*(\d+)$/)[0] <=> ($a =~ /:\t*(\d+)$/)[0] } @stack; diff --git a/src/net/scripts/checksyscalls.sh b/src/net/scripts/checksyscalls.sh new file mode 100755 index 0000000..b760995 --- /dev/null +++ b/src/net/scripts/checksyscalls.sh @@ -0,0 +1,269 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0 +# +# Check if current architecture are missing any function calls compared +# to i386. +# i386 define a number of legacy system calls that are i386 specific +# and listed below so they are ignored. +# +# Usage: +# checksyscalls.sh gcc gcc-options +# + +ignore_list() { +cat << EOF +#include <asm/types.h> +#include <asm/unistd.h> + +/* *at */ +#define __IGNORE_open /* openat */ +#define __IGNORE_link /* linkat */ +#define __IGNORE_unlink /* unlinkat */ +#define __IGNORE_mknod /* mknodat */ +#define __IGNORE_chmod /* fchmodat */ +#define __IGNORE_chown /* fchownat */ +#define __IGNORE_mkdir /* mkdirat */ +#define __IGNORE_rmdir /* unlinkat */ +#define __IGNORE_lchown /* fchownat */ +#define __IGNORE_access /* faccessat */ +#define __IGNORE_rename /* renameat2 */ +#define __IGNORE_readlink /* readlinkat */ +#define __IGNORE_symlink /* symlinkat */ +#define __IGNORE_utimes /* futimesat */ +#define __IGNORE_stat /* fstatat */ +#define __IGNORE_lstat /* fstatat */ +#define __IGNORE_stat64 /* fstatat64 */ +#define __IGNORE_lstat64 /* fstatat64 */ + +#ifndef __ARCH_WANT_SET_GET_RLIMIT +#define __IGNORE_getrlimit /* getrlimit */ +#define __IGNORE_setrlimit /* setrlimit */ +#endif + +#ifndef __ARCH_WANT_MEMFD_SECRET +#define __IGNORE_memfd_secret +#endif + +/* Missing flags argument */ +#define __IGNORE_renameat /* renameat2 */ + +/* CLOEXEC flag */ +#define __IGNORE_pipe /* pipe2 */ +#define __IGNORE_dup2 /* dup3 */ +#define __IGNORE_epoll_create /* epoll_create1 */ +#define __IGNORE_inotify_init /* inotify_init1 */ +#define __IGNORE_eventfd /* eventfd2 */ +#define __IGNORE_signalfd /* signalfd4 */ + +/* MMU */ +#ifndef CONFIG_MMU +#define __IGNORE_madvise +#define __IGNORE_mbind +#define __IGNORE_mincore +#define __IGNORE_mlock +#define __IGNORE_mlockall +#define __IGNORE_munlock +#define __IGNORE_munlockall +#define __IGNORE_mprotect +#define __IGNORE_msync +#define __IGNORE_migrate_pages +#define __IGNORE_move_pages +#define __IGNORE_remap_file_pages +#define __IGNORE_get_mempolicy +#define __IGNORE_set_mempolicy +#define __IGNORE_swapoff +#define __IGNORE_swapon +#endif + +/* System calls for 32-bit kernels only */ +#if BITS_PER_LONG == 64 +#define __IGNORE_sendfile64 +#define __IGNORE_ftruncate64 +#define __IGNORE_truncate64 +#define __IGNORE_stat64 +#define __IGNORE_lstat64 +#define __IGNORE_fstat64 +#define __IGNORE_fcntl64 +#define __IGNORE_fadvise64_64 +#define __IGNORE_fstatat64 +#define __IGNORE_fstatfs64 +#define __IGNORE_statfs64 +#define __IGNORE_llseek +#define __IGNORE_mmap2 +#define __IGNORE_clock_gettime64 +#define __IGNORE_clock_settime64 +#define __IGNORE_clock_adjtime64 +#define __IGNORE_clock_getres_time64 +#define __IGNORE_clock_nanosleep_time64 +#define __IGNORE_timer_gettime64 +#define __IGNORE_timer_settime64 +#define __IGNORE_timerfd_gettime64 +#define __IGNORE_timerfd_settime64 +#define __IGNORE_utimensat_time64 +#define __IGNORE_pselect6_time64 +#define __IGNORE_ppoll_time64 +#define __IGNORE_io_pgetevents_time64 +#define __IGNORE_recvmmsg_time64 +#define __IGNORE_mq_timedsend_time64 +#define __IGNORE_mq_timedreceive_time64 +#define __IGNORE_semtimedop_time64 +#define __IGNORE_rt_sigtimedwait_time64 +#define __IGNORE_futex_time64 +#define __IGNORE_sched_rr_get_interval_time64 +#else +#define __IGNORE_sendfile +#define __IGNORE_ftruncate +#define __IGNORE_truncate +#define __IGNORE_stat +#define __IGNORE_lstat +#define __IGNORE_fstat +#define __IGNORE_fcntl +#define __IGNORE_fadvise64 +#define __IGNORE_newfstatat +#define __IGNORE_fstatfs +#define __IGNORE_statfs +#define __IGNORE_lseek +#define __IGNORE_mmap +#define __IGNORE_clock_gettime +#define __IGNORE_clock_settime +#define __IGNORE_clock_adjtime +#define __IGNORE_clock_getres +#define __IGNORE_clock_nanosleep +#define __IGNORE_timer_gettime +#define __IGNORE_timer_settime +#define __IGNORE_timerfd_gettime +#define __IGNORE_timerfd_settime +#define __IGNORE_utimensat +#define __IGNORE_pselect6 +#define __IGNORE_ppoll +#define __IGNORE_io_pgetevents +#define __IGNORE_recvmmsg +#define __IGNORE_mq_timedsend +#define __IGNORE_mq_timedreceive +#define __IGNORE_semtimedop +#define __IGNORE_rt_sigtimedwait +#define __IGNORE_futex +#define __IGNORE_sched_rr_get_interval +#define __IGNORE_gettimeofday +#define __IGNORE_settimeofday +#define __IGNORE_wait4 +#define __IGNORE_adjtimex +#define __IGNORE_nanosleep +#define __IGNORE_io_getevents +#define __IGNORE_recvmmsg +#endif + +/* i386-specific or historical system calls */ +#define __IGNORE_break +#define __IGNORE_stty +#define __IGNORE_gtty +#define __IGNORE_ftime +#define __IGNORE_prof +#define __IGNORE_lock +#define __IGNORE_mpx +#define __IGNORE_ulimit +#define __IGNORE_profil +#define __IGNORE_ioperm +#define __IGNORE_iopl +#define __IGNORE_idle +#define __IGNORE_modify_ldt +#define __IGNORE_ugetrlimit +#define __IGNORE_vm86 +#define __IGNORE_vm86old +#define __IGNORE_set_thread_area +#define __IGNORE_get_thread_area +#define __IGNORE_madvise1 +#define __IGNORE_oldstat +#define __IGNORE_oldfstat +#define __IGNORE_oldlstat +#define __IGNORE_oldolduname +#define __IGNORE_olduname +#define __IGNORE_umount +#define __IGNORE_waitpid +#define __IGNORE_stime +#define __IGNORE_nice +#define __IGNORE_signal +#define __IGNORE_sigaction +#define __IGNORE_sgetmask +#define __IGNORE_sigsuspend +#define __IGNORE_sigpending +#define __IGNORE_ssetmask +#define __IGNORE_readdir +#define __IGNORE_socketcall +#define __IGNORE_ipc +#define __IGNORE_sigreturn +#define __IGNORE_sigprocmask +#define __IGNORE_bdflush +#define __IGNORE__llseek +#define __IGNORE__newselect +#define __IGNORE_create_module +#define __IGNORE_query_module +#define __IGNORE_get_kernel_syms +#define __IGNORE_sysfs +#define __IGNORE_uselib +#define __IGNORE__sysctl +#define __IGNORE_arch_prctl +#define __IGNORE_nfsservctl + +/* ... including the "new" 32-bit uid syscalls */ +#define __IGNORE_lchown32 +#define __IGNORE_getuid32 +#define __IGNORE_getgid32 +#define __IGNORE_geteuid32 +#define __IGNORE_getegid32 +#define __IGNORE_setreuid32 +#define __IGNORE_setregid32 +#define __IGNORE_getgroups32 +#define __IGNORE_setgroups32 +#define __IGNORE_fchown32 +#define __IGNORE_setresuid32 +#define __IGNORE_getresuid32 +#define __IGNORE_setresgid32 +#define __IGNORE_getresgid32 +#define __IGNORE_chown32 +#define __IGNORE_setuid32 +#define __IGNORE_setgid32 +#define __IGNORE_setfsuid32 +#define __IGNORE_setfsgid32 + +/* these can be expressed using other calls */ +#define __IGNORE_alarm /* setitimer */ +#define __IGNORE_creat /* open */ +#define __IGNORE_fork /* clone */ +#define __IGNORE_futimesat /* utimensat */ +#define __IGNORE_getpgrp /* getpgid */ +#define __IGNORE_getdents /* getdents64 */ +#define __IGNORE_pause /* sigsuspend */ +#define __IGNORE_poll /* ppoll */ +#define __IGNORE_select /* pselect6 */ +#define __IGNORE_epoll_wait /* epoll_pwait */ +#define __IGNORE_time /* gettimeofday */ +#define __IGNORE_uname /* newuname */ +#define __IGNORE_ustat /* statfs */ +#define __IGNORE_utime /* utimes */ +#define __IGNORE_vfork /* clone */ + +/* sync_file_range had a stupid ABI. Allow sync_file_range2 instead */ +#ifdef __NR_sync_file_range2 +#define __IGNORE_sync_file_range +#endif + +/* Unmerged syscalls for AFS, STREAMS, etc. */ +#define __IGNORE_afs_syscall +#define __IGNORE_getpmsg +#define __IGNORE_putpmsg +#define __IGNORE_vserver +EOF +} + +syscall_list() { + grep '^[0-9]' "$1" | sort -n | + while read nr abi name entry ; do + echo "#if !defined(__NR_${name}) && !defined(__IGNORE_${name})" + echo "#warning syscall ${name} not implemented" + echo "#endif" + done +} + +(ignore_list && syscall_list $(dirname $0)/../arch/x86/entry/syscalls/syscall_32.tbl) | \ +$* -E -x c - > /dev/null diff --git a/src/net/scripts/checkversion.pl b/src/net/scripts/checkversion.pl new file mode 100755 index 0000000..f67b125 --- /dev/null +++ b/src/net/scripts/checkversion.pl @@ -0,0 +1,72 @@ +#! /usr/bin/env perl +# SPDX-License-Identifier: GPL-2.0 +# +# checkversion find uses of LINUX_VERSION_CODE or KERNEL_VERSION +# without including <linux/version.h>, or cases of +# including <linux/version.h> that don't need it. +# Copyright (C) 2003, Randy Dunlap <rdunlap@xenotime.net> + +use strict; + +$| = 1; + +my $debugging; + +foreach my $file (@ARGV) { + next if $file =~ "include/linux/version\.h"; + # Open this file. + open( my $f, '<', $file ) + or die "Can't open $file: $!\n"; + + # Initialize variables. + my ($fInComment, $fInString, $fUseVersion); + my $iLinuxVersion = 0; + + while (<$f>) { + # Strip comments. + $fInComment && (s+^.*?\*/+ +o ? ($fInComment = 0) : next); + m+/\*+o && (s+/\*.*?\*/+ +go, (s+/\*.*$+ +o && ($fInComment = 1))); + + # Pick up definitions. + if ( m/^\s*#/o ) { + $iLinuxVersion = $. if m/^\s*#\s*include\s*"linux\/version\.h"/o; + } + + # Strip strings. + $fInString && (s+^.*?"+ +o ? ($fInString = 0) : next); + m+"+o && (s+".*?"+ +go, (s+".*$+ +o && ($fInString = 1))); + + # Pick up definitions. + if ( m/^\s*#/o ) { + $iLinuxVersion = $. if m/^\s*#\s*include\s*<linux\/version\.h>/o; + } + + # Look for uses: LINUX_VERSION_CODE, KERNEL_VERSION, UTS_RELEASE + if (($_ =~ /LINUX_VERSION_CODE/) || ($_ =~ /\WKERNEL_VERSION/)) { + $fUseVersion = 1; + last if $iLinuxVersion; + } + } + + # Report used version IDs without include? + if ($fUseVersion && ! $iLinuxVersion) { + print "$file: $.: need linux/version.h\n"; + } + + # Report superfluous includes. + if ($iLinuxVersion && ! $fUseVersion) { + print "$file: $iLinuxVersion linux/version.h not needed.\n"; + } + + # debug: report OK results: + if ($debugging) { + if ($iLinuxVersion && $fUseVersion) { + print "$file: version use is OK ($iLinuxVersion)\n"; + } + if (! $iLinuxVersion && ! $fUseVersion) { + print "$file: version use is OK (none)\n"; + } + } + + close($f); +} diff --git a/src/net/scripts/clang-tools/gen_compile_commands.py b/src/net/scripts/clang-tools/gen_compile_commands.py new file mode 100755 index 0000000..8bf55bb --- /dev/null +++ b/src/net/scripts/clang-tools/gen_compile_commands.py @@ -0,0 +1,237 @@ +#!/usr/bin/env python3 +# SPDX-License-Identifier: GPL-2.0 +# +# Copyright (C) Google LLC, 2018 +# +# Author: Tom Roeder <tmroeder@google.com> +# +"""A tool for generating compile_commands.json in the Linux kernel.""" + +import argparse +import json +import logging +import os +import re +import subprocess +import sys + +_DEFAULT_OUTPUT = 'compile_commands.json' +_DEFAULT_LOG_LEVEL = 'WARNING' + +_FILENAME_PATTERN = r'^\..*\.cmd$' +_LINE_PATTERN = r'^cmd_[^ ]*\.o := (.* )([^ ]*\.c)$' +_VALID_LOG_LEVELS = ['DEBUG', 'INFO', 'WARNING', 'ERROR', 'CRITICAL'] + + +def parse_arguments(): + """Sets up and parses command-line arguments. + + Returns: + log_level: A logging level to filter log output. + directory: The work directory where the objects were built. + ar: Command used for parsing .a archives. + output: Where to write the compile-commands JSON file. + paths: The list of files/directories to handle to find .cmd files. + """ + usage = 'Creates a compile_commands.json database from kernel .cmd files' + parser = argparse.ArgumentParser(description=usage) + + directory_help = ('specify the output directory used for the kernel build ' + '(defaults to the working directory)') + parser.add_argument('-d', '--directory', type=str, default='.', + help=directory_help) + + output_help = ('path to the output command database (defaults to ' + + _DEFAULT_OUTPUT + ')') + parser.add_argument('-o', '--output', type=str, default=_DEFAULT_OUTPUT, + help=output_help) + + log_level_help = ('the level of log messages to produce (defaults to ' + + _DEFAULT_LOG_LEVEL + ')') + parser.add_argument('--log_level', choices=_VALID_LOG_LEVELS, + default=_DEFAULT_LOG_LEVEL, help=log_level_help) + + ar_help = 'command used for parsing .a archives' + parser.add_argument('-a', '--ar', type=str, default='llvm-ar', help=ar_help) + + paths_help = ('directories to search or files to parse ' + '(files should be *.o, *.a, or modules.order). ' + 'If nothing is specified, the current directory is searched') + parser.add_argument('paths', type=str, nargs='*', help=paths_help) + + args = parser.parse_args() + + return (args.log_level, + os.path.abspath(args.directory), + args.output, + args.ar, + args.paths if len(args.paths) > 0 else [args.directory]) + + +def cmdfiles_in_dir(directory): + """Generate the iterator of .cmd files found under the directory. + + Walk under the given directory, and yield every .cmd file found. + + Args: + directory: The directory to search for .cmd files. + + Yields: + The path to a .cmd file. + """ + + filename_matcher = re.compile(_FILENAME_PATTERN) + + for dirpath, _, filenames in os.walk(directory): + for filename in filenames: + if filename_matcher.match(filename): + yield os.path.join(dirpath, filename) + + +def to_cmdfile(path): + """Return the path of .cmd file used for the given build artifact + + Args: + Path: file path + + Returns: + The path to .cmd file + """ + dir, base = os.path.split(path) + return os.path.join(dir, '.' + base + '.cmd') + + +def cmdfiles_for_o(obj): + """Generate the iterator of .cmd files associated with the object + + Yield the .cmd file used to build the given object + + Args: + obj: The object path + + Yields: + The path to .cmd file + """ + yield to_cmdfile(obj) + + +def cmdfiles_for_a(archive, ar): + """Generate the iterator of .cmd files associated with the archive. + + Parse the given archive, and yield every .cmd file used to build it. + + Args: + archive: The archive to parse + + Yields: + The path to every .cmd file found + """ + for obj in subprocess.check_output([ar, '-t', archive]).decode().split(): + yield to_cmdfile(obj) + + +def cmdfiles_for_modorder(modorder): + """Generate the iterator of .cmd files associated with the modules.order. + + Parse the given modules.order, and yield every .cmd file used to build the + contained modules. + + Args: + modorder: The modules.order file to parse + + Yields: + The path to every .cmd file found + """ + with open(modorder) as f: + for line in f: + ko = line.rstrip() + base, ext = os.path.splitext(ko) + if ext != '.ko': + sys.exit('{}: module path must end with .ko'.format(ko)) + mod = base + '.mod' + # The first line of *.mod lists the objects that compose the module. + with open(mod) as m: + for obj in m.readline().split(): + yield to_cmdfile(obj) + + +def process_line(root_directory, command_prefix, file_path): + """Extracts information from a .cmd line and creates an entry from it. + + Args: + root_directory: The directory that was searched for .cmd files. Usually + used directly in the "directory" entry in compile_commands.json. + command_prefix: The extracted command line, up to the last element. + file_path: The .c file from the end of the extracted command. + Usually relative to root_directory, but sometimes absolute. + + Returns: + An entry to append to compile_commands. + + Raises: + ValueError: Could not find the extracted file based on file_path and + root_directory or file_directory. + """ + # The .cmd files are intended to be included directly by Make, so they + # escape the pound sign '#', either as '\#' or '$(pound)' (depending on the + # kernel version). The compile_commands.json file is not interepreted + # by Make, so this code replaces the escaped version with '#'. + prefix = command_prefix.replace('\#', '#').replace('$(pound)', '#') + + # Use os.path.abspath() to normalize the path resolving '.' and '..' . + abs_path = os.path.abspath(os.path.join(root_directory, file_path)) + if not os.path.exists(abs_path): + raise ValueError('File %s not found' % abs_path) + return { + 'directory': root_directory, + 'file': abs_path, + 'command': prefix + file_path, + } + + +def main(): + """Walks through the directory and finds and parses .cmd files.""" + log_level, directory, output, ar, paths = parse_arguments() + + level = getattr(logging, log_level) + logging.basicConfig(format='%(levelname)s: %(message)s', level=level) + + line_matcher = re.compile(_LINE_PATTERN) + + compile_commands = [] + + for path in paths: + # If 'path' is a directory, handle all .cmd files under it. + # Otherwise, handle .cmd files associated with the file. + # Most of built-in objects are linked via archives (built-in.a or lib.a) + # but some objects are linked to vmlinux directly. + # Modules are listed in modules.order. + if os.path.isdir(path): + cmdfiles = cmdfiles_in_dir(path) + elif path.endswith('.o'): + cmdfiles = cmdfiles_for_o(path) + elif path.endswith('.a'): + cmdfiles = cmdfiles_for_a(path, ar) + elif path.endswith('modules.order'): + cmdfiles = cmdfiles_for_modorder(path) + else: + sys.exit('{}: unknown file type'.format(path)) + + for cmdfile in cmdfiles: + with open(cmdfile, 'rt') as f: + result = line_matcher.match(f.readline()) + if result: + try: + entry = process_line(directory, result.group(1), + result.group(2)) + compile_commands.append(entry) + except ValueError as err: + logging.info('Could not add line from %s: %s', + cmdfile, err) + + with open(output, 'wt') as f: + json.dump(compile_commands, f, indent=2, sort_keys=True) + + +if __name__ == '__main__': + main() diff --git a/src/net/scripts/clang-tools/run-clang-tools.py b/src/net/scripts/clang-tools/run-clang-tools.py new file mode 100755 index 0000000..f754415 --- /dev/null +++ b/src/net/scripts/clang-tools/run-clang-tools.py @@ -0,0 +1,74 @@ +#!/usr/bin/env python3 +# SPDX-License-Identifier: GPL-2.0 +# +# Copyright (C) Google LLC, 2020 +# +# Author: Nathan Huckleberry <nhuck@google.com> +# +"""A helper routine run clang-tidy and the clang static-analyzer on +compile_commands.json. +""" + +import argparse +import json +import multiprocessing +import os +import subprocess +import sys + + +def parse_arguments(): + """Set up and parses command-line arguments. + Returns: + args: Dict of parsed args + Has keys: [path, type] + """ + usage = """Run clang-tidy or the clang static-analyzer on a + compilation database.""" + parser = argparse.ArgumentParser(description=usage) + + type_help = "Type of analysis to be performed" + parser.add_argument("type", + choices=["clang-tidy", "clang-analyzer"], + help=type_help) + path_help = "Path to the compilation database to parse" + parser.add_argument("path", type=str, help=path_help) + + return parser.parse_args() + + +def init(l, a): + global lock + global args + lock = l + args = a + + +def run_analysis(entry): + # Disable all checks, then re-enable the ones we want + checks = "-checks=-*," + if args.type == "clang-tidy": + checks += "linuxkernel-*" + else: + checks += "clang-analyzer-*" + p = subprocess.run(["clang-tidy", "-p", args.path, checks, entry["file"]], + stdout=subprocess.PIPE, + stderr=subprocess.STDOUT, + cwd=entry["directory"]) + with lock: + sys.stderr.buffer.write(p.stdout) + + +def main(): + args = parse_arguments() + + lock = multiprocessing.Lock() + pool = multiprocessing.Pool(initializer=init, initargs=(lock, args)) + # Read JSON data into the datastore variable + with open(args.path, "r") as f: + datastore = json.load(f) + pool.map(run_analysis, datastore) + + +if __name__ == "__main__": + main() diff --git a/src/net/scripts/clang-version.sh b/src/net/scripts/clang-version.sh new file mode 100755 index 0000000..6fabf06 --- /dev/null +++ b/src/net/scripts/clang-version.sh @@ -0,0 +1,19 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0 +# +# clang-version clang-command +# +# Print the compiler version of `clang-command' in a 5 or 6-digit form +# such as `50001' for clang-5.0.1 etc. + +compiler="$*" + +if ! ( $compiler --version | grep -q clang) ; then + echo 0 + exit 1 +fi + +MAJOR=$(echo __clang_major__ | $compiler -E -x c - | tail -n 1) +MINOR=$(echo __clang_minor__ | $compiler -E -x c - | tail -n 1) +PATCHLEVEL=$(echo __clang_patchlevel__ | $compiler -E -x c - | tail -n 1) +printf "%d%02d%02d\\n" $MAJOR $MINOR $PATCHLEVEL diff --git a/src/net/scripts/cleanfile b/src/net/scripts/cleanfile new file mode 100755 index 0000000..c00c69b --- /dev/null +++ b/src/net/scripts/cleanfile @@ -0,0 +1,178 @@ +#!/usr/bin/env perl +# SPDX-License-Identifier: GPL-2.0 +# +# Clean a text file -- or directory of text files -- of stealth whitespace. +# WARNING: this can be a highly destructive operation. Use with caution. +# + +use warnings; +use bytes; +use File::Basename; + +# Default options +$max_width = 79; + +# Clean up space-tab sequences, either by removing spaces or +# replacing them with tabs. +sub clean_space_tabs($) +{ + no bytes; # Tab alignment depends on characters + + my($li) = @_; + my($lo) = ''; + my $pos = 0; + my $nsp = 0; + my($i, $c); + + for ($i = 0; $i < length($li); $i++) { + $c = substr($li, $i, 1); + if ($c eq "\t") { + my $npos = ($pos+$nsp+8) & ~7; + my $ntab = ($npos >> 3) - ($pos >> 3); + $lo .= "\t" x $ntab; + $pos = $npos; + $nsp = 0; + } elsif ($c eq "\n" || $c eq "\r") { + $lo .= " " x $nsp; + $pos += $nsp; + $nsp = 0; + $lo .= $c; + $pos = 0; + } elsif ($c eq " ") { + $nsp++; + } else { + $lo .= " " x $nsp; + $pos += $nsp; + $nsp = 0; + $lo .= $c; + $pos++; + } + } + $lo .= " " x $nsp; + return $lo; +} + +# Compute the visual width of a string +sub strwidth($) { + no bytes; # Tab alignment depends on characters + + my($li) = @_; + my($c, $i); + my $pos = 0; + my $mlen = 0; + + for ($i = 0; $i < length($li); $i++) { + $c = substr($li,$i,1); + if ($c eq "\t") { + $pos = ($pos+8) & ~7; + } elsif ($c eq "\n") { + $mlen = $pos if ($pos > $mlen); + $pos = 0; + } else { + $pos++; + } + } + + $mlen = $pos if ($pos > $mlen); + return $mlen; +} + +$name = basename($0); + +@files = (); + +while (defined($a = shift(@ARGV))) { + if ($a =~ /^-/) { + if ($a eq '-width' || $a eq '-w') { + $max_width = shift(@ARGV)+0; + } else { + print STDERR "Usage: $name [-width #] files...\n"; + exit 1; + } + } else { + push(@files, $a); + } +} + +foreach $f ( @files ) { + print STDERR "$name: $f\n"; + + if (! -f $f) { + print STDERR "$f: not a file\n"; + next; + } + + if (!open(FILE, '+<', $f)) { + print STDERR "$name: Cannot open file: $f: $!\n"; + next; + } + + binmode FILE; + + # First, verify that it is not a binary file; consider any file + # with a zero byte to be a binary file. Is there any better, or + # additional, heuristic that should be applied? + $is_binary = 0; + + while (read(FILE, $data, 65536) > 0) { + if ($data =~ /\0/) { + $is_binary = 1; + last; + } + } + + if ($is_binary) { + print STDERR "$name: $f: binary file\n"; + next; + } + + seek(FILE, 0, 0); + + $in_bytes = 0; + $out_bytes = 0; + $blank_bytes = 0; + + @blanks = (); + @lines = (); + $lineno = 0; + + while ( defined($line = <FILE>) ) { + $lineno++; + $in_bytes += length($line); + $line =~ s/[ \t\r]*$//; # Remove trailing spaces + $line = clean_space_tabs($line); + + if ( $line eq "\n" ) { + push(@blanks, $line); + $blank_bytes += length($line); + } else { + push(@lines, @blanks); + $out_bytes += $blank_bytes; + push(@lines, $line); + $out_bytes += length($line); + @blanks = (); + $blank_bytes = 0; + } + + $l_width = strwidth($line); + if ($max_width && $l_width > $max_width) { + print STDERR + "$f:$lineno: line exceeds $max_width characters ($l_width)\n"; + } + } + + # Any blanks at the end of the file are discarded + + if ($in_bytes != $out_bytes) { + # Only write to the file if changed + seek(FILE, 0, 0); + print FILE @lines; + + if ( !defined($where = tell(FILE)) || + !truncate(FILE, $where) ) { + die "$name: Failed to truncate modified file: $f: $!\n"; + } + } + + close(FILE); +} diff --git a/src/net/scripts/cleanpatch b/src/net/scripts/cleanpatch new file mode 100755 index 0000000..9f17552 --- /dev/null +++ b/src/net/scripts/cleanpatch @@ -0,0 +1,260 @@ +#!/usr/bin/env perl +# SPDX-License-Identifier: GPL-2.0 +# +# Clean a patch file -- or directory of patch files -- of stealth whitespace. +# WARNING: this can be a highly destructive operation. Use with caution. +# + +use warnings; +use bytes; +use File::Basename; + +# Default options +$max_width = 79; + +# Clean up space-tab sequences, either by removing spaces or +# replacing them with tabs. +sub clean_space_tabs($) +{ + no bytes; # Tab alignment depends on characters + + my($li) = @_; + my($lo) = ''; + my $pos = 0; + my $nsp = 0; + my($i, $c); + + for ($i = 0; $i < length($li); $i++) { + $c = substr($li, $i, 1); + if ($c eq "\t") { + my $npos = ($pos+$nsp+8) & ~7; + my $ntab = ($npos >> 3) - ($pos >> 3); + $lo .= "\t" x $ntab; + $pos = $npos; + $nsp = 0; + } elsif ($c eq "\n" || $c eq "\r") { + $lo .= " " x $nsp; + $pos += $nsp; + $nsp = 0; + $lo .= $c; + $pos = 0; + } elsif ($c eq " ") { + $nsp++; + } else { + $lo .= " " x $nsp; + $pos += $nsp; + $nsp = 0; + $lo .= $c; + $pos++; + } + } + $lo .= " " x $nsp; + return $lo; +} + +# Compute the visual width of a string +sub strwidth($) { + no bytes; # Tab alignment depends on characters + + my($li) = @_; + my($c, $i); + my $pos = 0; + my $mlen = 0; + + for ($i = 0; $i < length($li); $i++) { + $c = substr($li,$i,1); + if ($c eq "\t") { + $pos = ($pos+8) & ~7; + } elsif ($c eq "\n") { + $mlen = $pos if ($pos > $mlen); + $pos = 0; + } else { + $pos++; + } + } + + $mlen = $pos if ($pos > $mlen); + return $mlen; +} + +$name = basename($0); + +@files = (); + +while (defined($a = shift(@ARGV))) { + if ($a =~ /^-/) { + if ($a eq '-width' || $a eq '-w') { + $max_width = shift(@ARGV)+0; + } else { + print STDERR "Usage: $name [-width #] files...\n"; + exit 1; + } + } else { + push(@files, $a); + } +} + +foreach $f ( @files ) { + print STDERR "$name: $f\n"; + + if (! -f $f) { + print STDERR "$f: not a file\n"; + next; + } + + if (!open(FILE, '+<', $f)) { + print STDERR "$name: Cannot open file: $f: $!\n"; + next; + } + + binmode FILE; + + # First, verify that it is not a binary file; consider any file + # with a zero byte to be a binary file. Is there any better, or + # additional, heuristic that should be applied? + $is_binary = 0; + + while (read(FILE, $data, 65536) > 0) { + if ($data =~ /\0/) { + $is_binary = 1; + last; + } + } + + if ($is_binary) { + print STDERR "$name: $f: binary file\n"; + next; + } + + seek(FILE, 0, 0); + + $in_bytes = 0; + $out_bytes = 0; + $lineno = 0; + + @lines = (); + + $in_hunk = 0; + $err = 0; + + while ( defined($line = <FILE>) ) { + $lineno++; + $in_bytes += length($line); + + if (!$in_hunk) { + if ($line =~ + /^\@\@\s+\-([0-9]+),([0-9]+)\s+\+([0-9]+),([0-9]+)\s\@\@/) { + $minus_lines = $2; + $plus_lines = $4; + if ($minus_lines || $plus_lines) { + $in_hunk = 1; + @hunk_lines = ($line); + } + } else { + push(@lines, $line); + $out_bytes += length($line); + } + } else { + # We're in a hunk + + if ($line =~ /^\+/) { + $plus_lines--; + + $text = substr($line, 1); + $text =~ s/[ \t\r]*$//; # Remove trailing spaces + $text = clean_space_tabs($text); + + $l_width = strwidth($text); + if ($max_width && $l_width > $max_width) { + print STDERR + "$f:$lineno: adds line exceeds $max_width ", + "characters ($l_width)\n"; + } + + push(@hunk_lines, '+'.$text); + } elsif ($line =~ /^\-/) { + $minus_lines--; + push(@hunk_lines, $line); + } elsif ($line =~ /^ /) { + $plus_lines--; + $minus_lines--; + push(@hunk_lines, $line); + } else { + print STDERR "$name: $f: malformed patch\n"; + $err = 1; + last; + } + + if ($plus_lines < 0 || $minus_lines < 0) { + print STDERR "$name: $f: malformed patch\n"; + $err = 1; + last; + } elsif ($plus_lines == 0 && $minus_lines == 0) { + # End of a hunk. Process this hunk. + my $i; + my $l; + my @h = (); + my $adj = 0; + my $done = 0; + + for ($i = scalar(@hunk_lines)-1; $i > 0; $i--) { + $l = $hunk_lines[$i]; + if (!$done && $l eq "+\n") { + $adj++; # Skip this line + } elsif ($l =~ /^[ +]/) { + $done = 1; + unshift(@h, $l); + } else { + unshift(@h, $l); + } + } + + $l = $hunk_lines[0]; # Hunk header + undef @hunk_lines; # Free memory + + if ($adj) { + die unless + ($l =~ /^\@\@\s+\-([0-9]+),([0-9]+)\s+\+([0-9]+),([0-9]+)\s\@\@(.*)$/); + my $mstart = $1; + my $mlin = $2; + my $pstart = $3; + my $plin = $4; + my $tail = $5; # doesn't include the final newline + + $l = sprintf("@@ -%d,%d +%d,%d @@%s\n", + $mstart, $mlin, $pstart, $plin-$adj, + $tail); + } + unshift(@h, $l); + + # Transfer to the output array + foreach $l (@h) { + $out_bytes += length($l); + push(@lines, $l); + } + + $in_hunk = 0; + } + } + } + + if ($in_hunk) { + print STDERR "$name: $f: malformed patch\n"; + $err = 1; + } + + if (!$err) { + if ($in_bytes != $out_bytes) { + # Only write to the file if changed + seek(FILE, 0, 0); + print FILE @lines; + + if ( !defined($where = tell(FILE)) || + !truncate(FILE, $where) ) { + die "$name: Failed to truncate modified file: $f: $!\n"; + } + } + } + + close(FILE); +} diff --git a/src/net/scripts/coccicheck b/src/net/scripts/coccicheck new file mode 100755 index 0000000..209bb04 --- /dev/null +++ b/src/net/scripts/coccicheck @@ -0,0 +1,273 @@ +#!/bin/bash +# SPDX-License-Identifier: GPL-2.0 +# Linux kernel coccicheck +# +# Read Documentation/dev-tools/coccinelle.rst +# +# This script requires at least spatch +# version 1.0.0-rc11. + +DIR="$(dirname $(readlink -f $0))/.." +SPATCH="`which ${SPATCH:=spatch}`" + +if [ ! -x "$SPATCH" ]; then + echo 'spatch is part of the Coccinelle project and is available at http://coccinelle.lip6.fr/' + exit 1 +fi + +SPATCH_VERSION=$($SPATCH --version | head -1 | awk '{print $3}') +SPATCH_VERSION_NUM=$(echo $SPATCH_VERSION | ${DIR}/scripts/ld-version.sh) + +USE_JOBS="no" +$SPATCH --help | grep "\-\-jobs" > /dev/null && USE_JOBS="yes" + +# The verbosity may be set by the environmental parameter V= +# as for example with 'make V=1 coccicheck' + +if [ -n "$V" -a "$V" != "0" ]; then + VERBOSE="$V" +else + VERBOSE=0 +fi + +FLAGS="--very-quiet" + +# You can use SPFLAGS to append extra arguments to coccicheck or override any +# heuristics done in this file as Coccinelle accepts the last options when +# options conflict. +# +# A good example for use of SPFLAGS is if you want to debug your cocci script, +# you can for instance use the following: +# +# $ export COCCI=scripts/coccinelle/misc/irqf_oneshot.cocci +# $ make coccicheck MODE=report DEBUG_FILE="all.err" SPFLAGS="--profile --show-trying" M=./drivers/mfd/arizona-irq.c +# +# "--show-trying" should show you what rule is being processed as it goes to +# stdout, you do not need a debug file for that. The profile output will be +# be sent to stdout, if you provide a DEBUG_FILE the profiling data can be +# inspected there. +# +# --profile will not output if --very-quiet is used, so avoid it. +echo $SPFLAGS | egrep -e "--profile|--show-trying" 2>&1 > /dev/null +if [ $? -eq 0 ]; then + FLAGS="--quiet" +fi + +# spatch only allows include directories with the syntax "-I include" +# while gcc also allows "-Iinclude" and "-include include" +COCCIINCLUDE=${LINUXINCLUDE//-I/-I } +COCCIINCLUDE=${COCCIINCLUDE// -include/ --include} + +if [ "$C" = "1" -o "$C" = "2" ]; then + ONLINE=1 + + # Take only the last argument, which is the C file to test + shift $(( $# - 1 )) + OPTIONS="$COCCIINCLUDE $1" + + # No need to parallelize Coccinelle since this mode takes one input file. + NPROC=1 +else + ONLINE=0 + if [ "$KBUILD_EXTMOD" = "" ] ; then + OPTIONS="--dir $srctree $COCCIINCLUDE" + else + OPTIONS="--dir $KBUILD_EXTMOD $COCCIINCLUDE" + fi + + # Use only one thread per core by default if hyperthreading is enabled + THREADS_PER_CORE=$(lscpu | grep "Thread(s) per core: " | tr -cd "[:digit:]") + if [ -z "$J" ]; then + NPROC=$(getconf _NPROCESSORS_ONLN) + if [ $THREADS_PER_CORE -gt 1 -a $NPROC -gt 4 ] ; then + NPROC=$((NPROC/2)) + fi + else + NPROC="$J" + fi +fi + +if [ "$KBUILD_EXTMOD" != "" ] ; then + OPTIONS="--patch $srctree $OPTIONS" +fi + +# You can override by using SPFLAGS +if [ "$USE_JOBS" = "no" ]; then + trap kill_running SIGTERM SIGINT + declare -a SPATCH_PID +elif [ "$NPROC" != "1" ]; then + # Using 0 should work as well, refer to _SC_NPROCESSORS_ONLN use on + # https://github.com/rdicosmo/parmap/blob/master/setcore_stubs.c + OPTIONS="$OPTIONS --jobs $NPROC --chunksize 1" +fi + +if [ "$MODE" = "" ] ; then + if [ "$ONLINE" = "0" ] ; then + echo 'You have not explicitly specified the mode to use. Using default "report" mode.' + echo 'Available modes are the following: patch, report, context, org, chain' + echo 'You can specify the mode with "make coccicheck MODE=<mode>"' + echo 'Note however that some modes are not implemented by some semantic patches.' + fi + MODE="report" +fi + +if [ "$MODE" = "chain" ] ; then + if [ "$ONLINE" = "0" ] ; then + echo 'You have selected the "chain" mode.' + echo 'All available modes will be tried (in that order): patch, report, context, org' + fi +elif [ "$MODE" = "report" -o "$MODE" = "org" ] ; then + FLAGS="--no-show-diff $FLAGS" +fi + +if [ "$ONLINE" = "0" ] ; then + echo '' + echo 'Please check for false positives in the output before submitting a patch.' + echo 'When using "patch" mode, carefully review the patch before submitting it.' + echo '' +fi + +run_cmd_parmap() { + if [ $VERBOSE -ne 0 ] ; then + echo "Running ($NPROC in parallel): $@" + fi + if [ "$DEBUG_FILE" != "/dev/null" -a "$DEBUG_FILE" != "" ]; then + echo $@>>$DEBUG_FILE + $@ 2>>$DEBUG_FILE + else + echo $@ + $@ 2>&1 + fi + + err=$? + if [[ $err -ne 0 ]]; then + echo "coccicheck failed" + exit $err + fi +} + +run_cmd_old() { + local i + if [ $VERBOSE -ne 0 ] ; then + echo "Running ($NPROC in parallel): $@" + fi + for i in $(seq 0 $(( NPROC - 1)) ); do + eval "$@ --max $NPROC --index $i &" + SPATCH_PID[$i]=$! + if [ $VERBOSE -eq 2 ] ; then + echo "${SPATCH_PID[$i]} running" + fi + done + wait +} + +run_cmd() { + if [ "$USE_JOBS" = "yes" ]; then + run_cmd_parmap $@ + else + run_cmd_old $@ + fi +} + +kill_running() { + for i in $(seq 0 $(( NPROC - 1 )) ); do + if [ $VERBOSE -eq 2 ] ; then + echo "Killing ${SPATCH_PID[$i]}" + fi + kill ${SPATCH_PID[$i]} 2>/dev/null + done +} + +# You can override heuristics with SPFLAGS, these must always go last +OPTIONS="$OPTIONS $SPFLAGS" + +coccinelle () { + COCCI="$1" + + OPT=`grep "Options:" $COCCI | cut -d':' -f2` + REQ=`grep "Requires:" $COCCI | cut -d':' -f2 | sed "s| ||"` + REQ_NUM=$(echo $REQ | ${DIR}/scripts/ld-version.sh) + if [ "$REQ_NUM" != "0" ] ; then + if [ "$SPATCH_VERSION_NUM" -lt "$REQ_NUM" ] ; then + echo "Skipping coccinelle SmPL patch: $COCCI" + echo "You have coccinelle: $SPATCH_VERSION" + echo "This SmPL patch requires: $REQ" + return + fi + fi + +# The option '--parse-cocci' can be used to syntactically check the SmPL files. +# +# $SPATCH -D $MODE $FLAGS -parse_cocci $COCCI $OPT > /dev/null + + if [ $VERBOSE -ne 0 -a $ONLINE -eq 0 ] ; then + + FILE=${COCCI#$srctree/} + + echo "Processing `basename $COCCI`" + echo "with option(s) \"$OPT\"" + echo '' + echo 'Message example to submit a patch:' + + sed -ne 's|^///||p' $COCCI + + if [ "$MODE" = "patch" ] ; then + echo ' The semantic patch that makes this change is available' + elif [ "$MODE" = "report" ] ; then + echo ' The semantic patch that makes this report is available' + elif [ "$MODE" = "context" ] ; then + echo ' The semantic patch that spots this code is available' + elif [ "$MODE" = "org" ] ; then + echo ' The semantic patch that makes this Org report is available' + else + echo ' The semantic patch that makes this output is available' + fi + echo " in $FILE." + echo '' + echo ' More information about semantic patching is available at' + echo ' http://coccinelle.lip6.fr/' + echo '' + + if [ "`sed -ne 's|^//#||p' $COCCI`" ] ; then + echo 'Semantic patch information:' + sed -ne 's|^//#||p' $COCCI + echo '' + fi + fi + + if [ "$MODE" = "chain" ] ; then + run_cmd $SPATCH -D patch \ + $FLAGS --cocci-file $COCCI $OPT $OPTIONS || \ + run_cmd $SPATCH -D report \ + $FLAGS --cocci-file $COCCI $OPT $OPTIONS --no-show-diff || \ + run_cmd $SPATCH -D context \ + $FLAGS --cocci-file $COCCI $OPT $OPTIONS || \ + run_cmd $SPATCH -D org \ + $FLAGS --cocci-file $COCCI $OPT $OPTIONS --no-show-diff || exit 1 + elif [ "$MODE" = "rep+ctxt" ] ; then + run_cmd $SPATCH -D report \ + $FLAGS --cocci-file $COCCI $OPT $OPTIONS --no-show-diff && \ + run_cmd $SPATCH -D context \ + $FLAGS --cocci-file $COCCI $OPT $OPTIONS || exit 1 + else + run_cmd $SPATCH -D $MODE $FLAGS --cocci-file $COCCI $OPT $OPTIONS || exit 1 + fi + +} + +if [ "$DEBUG_FILE" != "/dev/null" -a "$DEBUG_FILE" != "" ]; then + if [ -f $DEBUG_FILE ]; then + echo "Debug file $DEBUG_FILE exists, bailing" + exit + fi +else + DEBUG_FILE="/dev/null" +fi + +if [ "$COCCI" = "" ] ; then + for f in `find $srctree/scripts/coccinelle/ -name '*.cocci' -type f | sort`; do + coccinelle $f + done +else + coccinelle $COCCI +fi diff --git a/src/net/scripts/coccinelle/api/alloc/alloc_cast.cocci b/src/net/scripts/coccinelle/api/alloc/alloc_cast.cocci new file mode 100644 index 0000000..f6f0ccd --- /dev/null +++ b/src/net/scripts/coccinelle/api/alloc/alloc_cast.cocci @@ -0,0 +1,123 @@ +// SPDX-License-Identifier: GPL-2.0-only +/// Remove casting the values returned by memory allocation functions +/// like kmalloc, kzalloc, kmem_cache_alloc, kmem_cache_zalloc etc. +/// +//# This makes an effort to find cases of casting of values returned by +//# kmalloc, kzalloc, kcalloc, kmem_cache_alloc, kmem_cache_zalloc, +//# kmem_cache_alloc_node, kmalloc_node and kzalloc_node and removes +//# the casting as it is not required. The result in the patch case may +//# need some reformatting. +// +// Confidence: High +// Copyright: (C) 2014 Himangi Saraogi +// Copyright: (C) 2017 Himanshu Jha +// Comments: +// Options: --no-includes --include-headers +// + +virtual context +virtual patch +virtual org +virtual report + +@initialize:python@ +@@ +import re +pattern = '__' +m = re.compile(pattern) + +@r1 depends on context || patch@ +type T; +@@ + + (T *) + \(kmalloc\|kzalloc\|kcalloc\|kmem_cache_alloc\|kmem_cache_zalloc\| + kmem_cache_alloc_node\|kmalloc_node\|kzalloc_node\|vmalloc\|vzalloc\| + dma_alloc_coherent\|devm_kmalloc\|devm_kzalloc\| + kvmalloc\|kvzalloc\|kvmalloc_node\|kvzalloc_node\|pci_alloc_consistent\| + pci_zalloc_consistent\|kmem_alloc\|kmem_zalloc\|kmem_zone_alloc\| + kmem_zone_zalloc\|vmalloc_node\|vzalloc_node\)(...) + +//---------------------------------------------------------- +// For context mode +//---------------------------------------------------------- + +@script:python depends on context@ +t << r1.T; +@@ + +if m.search(t) != None: + cocci.include_match(False) + +@depends on context && r1@ +type r1.T; +@@ + +* (T *) + \(kmalloc\|kzalloc\|kcalloc\|kmem_cache_alloc\|kmem_cache_zalloc\| + kmem_cache_alloc_node\|kmalloc_node\|kzalloc_node\|vmalloc\|vzalloc\| + dma_alloc_coherent\|devm_kmalloc\|devm_kzalloc\| + kvmalloc\|kvzalloc\|kvmalloc_node\|kvzalloc_node\|pci_alloc_consistent\| + pci_zalloc_consistent\|kmem_alloc\|kmem_zalloc\|kmem_zone_alloc\| + kmem_zone_zalloc\|vmalloc_node\|vzalloc_node\)(...) + +//---------------------------------------------------------- +// For patch mode +//---------------------------------------------------------- + +@script:python depends on patch@ +t << r1.T; +@@ + +if m.search(t) != None: + cocci.include_match(False) + +@depends on patch && r1@ +type r1.T; +@@ + +- (T *) + \(kmalloc\|kzalloc\|kcalloc\|kmem_cache_alloc\|kmem_cache_zalloc\| + kmem_cache_alloc_node\|kmalloc_node\|kzalloc_node\|vmalloc\|vzalloc\| + dma_alloc_coherent\|devm_kmalloc\|devm_kzalloc\| + kvmalloc\|kvzalloc\|kvmalloc_node\|kvzalloc_node\|pci_alloc_consistent\| + pci_zalloc_consistent\|kmem_alloc\|kmem_zalloc\|kmem_zone_alloc\| + kmem_zone_zalloc\|vmalloc_node\|vzalloc_node\)(...) + +//---------------------------------------------------------- +// For org and report mode +//---------------------------------------------------------- + +@r2 depends on org || report@ +type T; +position p; +@@ + + (T@p *) + \(kmalloc\|kzalloc\|kcalloc\|kmem_cache_alloc\|kmem_cache_zalloc\| + kmem_cache_alloc_node\|kmalloc_node\|kzalloc_node\|vmalloc\|vzalloc\| + dma_alloc_coherent\|devm_kmalloc\|devm_kzalloc\| + kvmalloc\|kvzalloc\|kvmalloc_node\|kvzalloc_node\|pci_alloc_consistent\| + pci_zalloc_consistent\|kmem_alloc\|kmem_zalloc\|kmem_zone_alloc\| + kmem_zone_zalloc\|vmalloc_node\|vzalloc_node\)(...) + +@script:python depends on org@ +p << r2.p; +t << r2.T; +@@ + +if m.search(t) != None: + cocci.include_match(False) +else: + coccilib.org.print_safe_todo(p[0], t) + +@script:python depends on report@ +p << r2.p; +t << r2.T; +@@ + +if m.search(t) != None: + cocci.include_match(False) +else: + msg="WARNING: casting value returned by memory allocation function to (%s *) is useless." % (t) + coccilib.report.print_report(p[0], msg) diff --git a/src/net/scripts/coccinelle/api/alloc/pool_zalloc-simple.cocci b/src/net/scripts/coccinelle/api/alloc/pool_zalloc-simple.cocci new file mode 100644 index 0000000..9c61a23 --- /dev/null +++ b/src/net/scripts/coccinelle/api/alloc/pool_zalloc-simple.cocci @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0-only +/// +/// Use *_pool_zalloc rather than *_pool_alloc followed by memset with 0 +/// +// Copyright: (C) 2015 Intel Corp. +// Options: --no-includes --include-headers +// +// Keywords: dma_pool_zalloc, pci_pool_zalloc +// + +virtual context +virtual patch +virtual org +virtual report + +//---------------------------------------------------------- +// For context mode +//---------------------------------------------------------- + +@depends on context@ +expression x; +statement S; +@@ + +* x = \(dma_pool_alloc\|pci_pool_alloc\)(...); + if ((x==NULL) || ...) S +* memset(x,0, ...); + +//---------------------------------------------------------- +// For patch mode +//---------------------------------------------------------- + +@depends on patch@ +expression x; +expression a,b,c; +statement S; +@@ + +- x = dma_pool_alloc(a,b,c); ++ x = dma_pool_zalloc(a,b,c); + if ((x==NULL) || ...) S +- memset(x,0,...); + +@depends on patch@ +expression x; +expression a,b,c; +statement S; +@@ + +- x = pci_pool_alloc(a,b,c); ++ x = pci_pool_zalloc(a,b,c); + if ((x==NULL) || ...) S +- memset(x,0,...); + +//---------------------------------------------------------- +// For org and report mode +//---------------------------------------------------------- + +@r depends on org || report@ +expression x; +expression a,b,c; +statement S; +position p; +@@ + + x = @p\(dma_pool_alloc\|pci_pool_alloc\)(a,b,c); + if ((x==NULL) || ...) S + memset(x,0, ...); + +@script:python depends on org@ +p << r.p; +x << r.x; +@@ + +msg="%s" % (x) +msg_safe=msg.replace("[","@(").replace("]",")") +coccilib.org.print_todo(p[0], msg_safe) + +@script:python depends on report@ +p << r.p; +x << r.x; +@@ + +msg="WARNING: *_pool_zalloc should be used for %s, instead of *_pool_alloc/memset" % (x) +coccilib.report.print_report(p[0], msg) diff --git a/src/net/scripts/coccinelle/api/alloc/zalloc-simple.cocci b/src/net/scripts/coccinelle/api/alloc/zalloc-simple.cocci new file mode 100644 index 0000000..b3d0c3c --- /dev/null +++ b/src/net/scripts/coccinelle/api/alloc/zalloc-simple.cocci @@ -0,0 +1,411 @@ +// SPDX-License-Identifier: GPL-2.0-only +/// +/// Use zeroing allocator rather than allocator followed by memset with 0 +/// +/// This considers some simple cases that are common and easy to validate +/// Note in particular that there are no ...s in the rule, so all of the +/// matched code has to be contiguous +/// +// Confidence: High +// Copyright: (C) 2009-2010 Julia Lawall, Nicolas Palix, DIKU. +// Copyright: (C) 2009-2010 Gilles Muller, INRIA/LiP6. +// Copyright: (C) 2017 Himanshu Jha +// URL: http://coccinelle.lip6.fr/rules/kzalloc.html +// Options: --no-includes --include-headers +// +// Keywords: kmalloc, kzalloc +// Version min: < 2.6.12 kmalloc +// Version min: 2.6.14 kzalloc +// + +virtual context +virtual patch +virtual org +virtual report + +//---------------------------------------------------------- +// For context mode +//---------------------------------------------------------- + +@depends on context@ +type T, T2; +expression x; +expression E1; +statement S; +@@ + +* x = (T)\(kmalloc(E1, ...)\|vmalloc(E1)\|dma_alloc_coherent(...,E1,...)\| + kmalloc_node(E1, ...)\|kmem_cache_alloc(...)\|kmem_alloc(E1, ...)\| + devm_kmalloc(...,E1,...)\|kvmalloc(E1, ...)\|kvmalloc_node(E1,...)\); + if ((x==NULL) || ...) S +* memset((T2)x,0,E1); + +//---------------------------------------------------------- +// For patch mode +//---------------------------------------------------------- + +@depends on patch@ +type T, T2; +expression x; +expression E1,E2,E3,E4; +statement S; +@@ + +( +- x = kmalloc(E1,E2); ++ x = kzalloc(E1,E2); +| +- x = (T *)kmalloc(E1,E2); ++ x = kzalloc(E1,E2); +| +- x = (T)kmalloc(E1,E2); ++ x = (T)kzalloc(E1,E2); +| +- x = vmalloc(E1); ++ x = vzalloc(E1); +| +- x = (T *)vmalloc(E1); ++ x = vzalloc(E1); +| +- x = (T)vmalloc(E1); ++ x = (T)vzalloc(E1); +| +- x = kmalloc_node(E1,E2,E3); ++ x = kzalloc_node(E1,E2,E3); +| +- x = (T *)kmalloc_node(E1,E2,E3); ++ x = kzalloc_node(E1,E2,E3); +| +- x = (T)kmalloc_node(E1,E2,E3); ++ x = (T)kzalloc_node(E1,E2,E3); +| +- x = kmem_cache_alloc(E3,E4); ++ x = kmem_cache_zalloc(E3,E4); +| +- x = (T *)kmem_cache_alloc(E3,E4); ++ x = kmem_cache_zalloc(E3,E4); +| +- x = (T)kmem_cache_alloc(E3,E4); ++ x = (T)kmem_cache_zalloc(E3,E4); +| +- x = kmem_alloc(E1,E2); ++ x = kmem_zalloc(E1,E2); +| +- x = (T *)kmem_alloc(E1,E2); ++ x = kmem_zalloc(E1,E2); +| +- x = (T)kmem_alloc(E1,E2); ++ x = (T)kmem_zalloc(E1,E2); +| +- x = devm_kmalloc(E2,E1,E3); ++ x = devm_kzalloc(E2,E1,E3); +| +- x = (T *)devm_kmalloc(E2,E1,E3); ++ x = devm_kzalloc(E2,E1,E3); +| +- x = (T)devm_kmalloc(E2,E1,E3); ++ x = (T)devm_kzalloc(E2,E1,E3); +| +- x = kvmalloc(E1,E2); ++ x = kvzalloc(E1,E2); +| +- x = (T *)kvmalloc(E1,E2); ++ x = kvzalloc(E1,E2); +| +- x = (T)kvmalloc(E1,E2); ++ x = (T)kvzalloc(E1,E2); +| +- x = kvmalloc_node(E1,E2,E3); ++ x = kvzalloc_node(E1,E2,E3); +| +- x = (T *)kvmalloc_node(E1,E2,E3); ++ x = kvzalloc_node(E1,E2,E3); +| +- x = (T)kvmalloc_node(E1,E2,E3); ++ x = (T)kvzalloc_node(E1,E2,E3); +) + if ((x==NULL) || ...) S +- memset((T2)x,0,E1); + +@depends on patch@ +type T, T2; +expression x; +expression E1,E2,E3,E4; +statement S; +@@ + x = (T)dma_alloc_coherent(E1, E2, E3, E4); + if ((x==NULL) || ...) S +- memset((T2)x, 0, E2); + +//---------------------------------------------------------- +// For org mode +//---------------------------------------------------------- + +@r depends on org || report@ +type T, T2; +expression x; +expression E1,E2; +statement S; +position p; +@@ + + x = (T)kmalloc@p(E1,E2); + if ((x==NULL) || ...) S + memset((T2)x,0,E1); + +@script:python depends on org@ +p << r.p; +x << r.x; +@@ + +msg="%s" % (x) +msg_safe=msg.replace("[","@(").replace("]",")") +coccilib.org.print_todo(p[0], msg_safe) + +@script:python depends on report@ +p << r.p; +x << r.x; +@@ + +msg="WARNING: kzalloc should be used for %s, instead of kmalloc/memset" % (x) +coccilib.report.print_report(p[0], msg) + +//----------------------------------------------------------------- +@r1 depends on org || report@ +type T, T2; +expression x; +expression E1; +statement S; +position p; +@@ + + x = (T)vmalloc@p(E1); + if ((x==NULL) || ...) S + memset((T2)x,0,E1); + +@script:python depends on org@ +p << r1.p; +x << r1.x; +@@ + +msg="%s" % (x) +msg_safe=msg.replace("[","@(").replace("]",")") +coccilib.org.print_todo(p[0], msg_safe) + +@script:python depends on report@ +p << r1.p; +x << r1.x; +@@ + +msg="WARNING: vzalloc should be used for %s, instead of vmalloc/memset" % (x) +coccilib.report.print_report(p[0], msg) + +//----------------------------------------------------------------- +@r2 depends on org || report@ +type T, T2; +expression x; +expression E1,E2,E3,E4; +statement S; +position p; +@@ + + x = (T)dma_alloc_coherent@p(E1,E2,E3,E4); + if ((x==NULL) || ...) S + memset((T2)x,0,E2); + +@script:python depends on org@ +p << r2.p; +x << r2.x; +@@ + +msg="%s" % (x) +msg_safe=msg.replace("[","@(").replace("]",")") +coccilib.org.print_todo(p[0], msg_safe) + +@script:python depends on report@ +p << r2.p; +x << r2.x; +@@ + +msg="WARNING: dma_alloc_coherent used in %s already zeroes out memory, so memset is not needed" % (x) +coccilib.report.print_report(p[0], msg) + +//----------------------------------------------------------------- +@r3 depends on org || report@ +type T, T2; +expression x; +expression E1,E2,E3; +statement S; +position p; +@@ + + x = (T)kmalloc_node@p(E1,E2,E3); + if ((x==NULL) || ...) S + memset((T2)x,0,E1); + +@script:python depends on org@ +p << r3.p; +x << r3.x; +@@ + +msg="%s" % (x) +msg_safe=msg.replace("[","@(").replace("]",")") +coccilib.org.print_todo(p[0], msg_safe) + +@script:python depends on report@ +p << r3.p; +x << r3.x; +@@ + +msg="WARNING: kzalloc_node should be used for %s, instead of kmalloc_node/memset" % (x) +coccilib.report.print_report(p[0], msg) + +//----------------------------------------------------------------- +@r4 depends on org || report@ +type T, T2; +expression x; +expression E1,E2,E3; +statement S; +position p; +@@ + + x = (T)kmem_cache_alloc@p(E2,E3); + if ((x==NULL) || ...) S + memset((T2)x,0,E1); + +@script:python depends on org@ +p << r4.p; +x << r4.x; +@@ + +msg="%s" % (x) +msg_safe=msg.replace("[","@(").replace("]",")") +coccilib.org.print_todo(p[0], msg_safe) + +@script:python depends on report@ +p << r4.p; +x << r4.x; +@@ + +msg="WARNING: kmem_cache_zalloc should be used for %s, instead of kmem_cache_alloc/memset" % (x) +coccilib.report.print_report(p[0], msg) + +//----------------------------------------------------------------- +@r5 depends on org || report@ +type T, T2; +expression x; +expression E1,E2; +statement S; +position p; +@@ + + x = (T)kmem_alloc@p(E1,E2); + if ((x==NULL) || ...) S + memset((T2)x,0,E1); + +@script:python depends on org@ +p << r5.p; +x << r5.x; +@@ + +msg="%s" % (x) +msg_safe=msg.replace("[","@(").replace("]",")") +coccilib.org.print_todo(p[0], msg_safe) + +@script:python depends on report@ +p << r5.p; +x << r5.x; +@@ + +msg="WARNING: kmem_zalloc should be used for %s, instead of kmem_alloc/memset" % (x) +coccilib.report.print_report(p[0], msg) + +//----------------------------------------------------------------- +@r6 depends on org || report@ +type T, T2; +expression x; +expression E1,E2,E3; +statement S; +position p; +@@ + + x = (T)devm_kmalloc@p(E2,E1,E3); + if ((x==NULL) || ...) S + memset((T2)x,0,E1); + +@script:python depends on org@ +p << r6.p; +x << r6.x; +@@ + +msg="%s" % (x) +msg_safe=msg.replace("[","@(").replace("]",")") +coccilib.org.print_todo(p[0], msg_safe) + +@script:python depends on report@ +p << r6.p; +x << r6.x; +@@ + +msg="WARNING: devm_kzalloc should be used for %s, instead of devm_kmalloc/memset" % (x) +coccilib.report.print_report(p[0], msg) + +//----------------------------------------------------------------- +@r7 depends on org || report@ +type T, T2; +expression x; +expression E1,E2; +statement S; +position p; +@@ + + x = (T)kvmalloc@p(E1,E2); + if ((x==NULL) || ...) S + memset((T2)x,0,E1); + +@script:python depends on org@ +p << r7.p; +x << r7.x; +@@ + +msg="%s" % (x) +msg_safe=msg.replace("[","@(").replace("]",")") +coccilib.org.print_todo(p[0], msg_safe) + +@script:python depends on report@ +p << r7.p; +x << r7.x; +@@ + +msg="WARNING: kvzalloc should be used for %s, instead of kvmalloc/memset" % (x) +coccilib.report.print_report(p[0], msg) + +//----------------------------------------------------------------- +@r9 depends on org || report@ +type T, T2; +expression x; +expression E1,E2,E3; +statement S; +position p; +@@ + + x = (T)kvmalloc_node@p(E1,E2,E3); + if ((x==NULL) || ...) S + memset((T2)x,0,E1); + +@script:python depends on org@ +p << r9.p; +x << r9.x; +@@ + +msg="%s" % (x) +msg_safe=msg.replace("[","@(").replace("]",")") +coccilib.org.print_todo(p[0], msg_safe) + +@script:python depends on report@ +p << r9.p; +x << r9.x; +@@ + +msg="WARNING: kvzalloc_node should be used for %s, instead of kvmalloc_node/memset" % (x) +coccilib.report.print_report(p[0], msg) diff --git a/src/net/scripts/coccinelle/api/atomic_as_refcounter.cocci b/src/net/scripts/coccinelle/api/atomic_as_refcounter.cocci new file mode 100644 index 0000000..0f78d94 --- /dev/null +++ b/src/net/scripts/coccinelle/api/atomic_as_refcounter.cocci @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Check if refcount_t type and API should be used +// instead of atomic_t type when dealing with refcounters +// +// Copyright (c) 2016-2017, Elena Reshetova, Intel Corporation +// +// Confidence: Moderate +// URL: http://coccinelle.lip6.fr/ +// Options: --include-headers --very-quiet + +virtual report + +@r1 exists@ +identifier a, x; +position p1, p2; +identifier fname =~ ".*free.*"; +identifier fname2 =~ ".*destroy.*"; +identifier fname3 =~ ".*del.*"; +identifier fname4 =~ ".*queue_work.*"; +identifier fname5 =~ ".*schedule_work.*"; +identifier fname6 =~ ".*call_rcu.*"; + +@@ + +( + atomic_dec_and_test@p1(&(a)->x) +| + atomic_dec_and_lock@p1(&(a)->x, ...) +| + atomic_long_dec_and_lock@p1(&(a)->x, ...) +| + atomic_long_dec_and_test@p1(&(a)->x) +| + atomic64_dec_and_test@p1(&(a)->x) +| + local_dec_and_test@p1(&(a)->x) +) +... +( + fname@p2(a, ...); +| + fname2@p2(...); +| + fname3@p2(...); +| + fname4@p2(...); +| + fname5@p2(...); +| + fname6@p2(...); +) + + +@script:python depends on report@ +p1 << r1.p1; +p2 << r1.p2; +@@ +msg = "atomic_dec_and_test variation before object free at line %s." +coccilib.report.print_report(p1[0], msg % (p2[0].line)) + +@r4 exists@ +identifier a, x, y; +position p1, p2; +identifier fname =~ ".*free.*"; + +@@ + +( + atomic_dec_and_test@p1(&(a)->x) +| + atomic_dec_and_lock@p1(&(a)->x, ...) +| + atomic_long_dec_and_lock@p1(&(a)->x, ...) +| + atomic_long_dec_and_test@p1(&(a)->x) +| + atomic64_dec_and_test@p1(&(a)->x) +| + local_dec_and_test@p1(&(a)->x) +) +... +y=a +... +fname@p2(y, ...); + + +@script:python depends on report@ +p1 << r4.p1; +p2 << r4.p2; +@@ +msg = "atomic_dec_and_test variation before object free at line %s." +coccilib.report.print_report(p1[0], msg % (p2[0].line)) + +@r2 exists@ +identifier a, x; +position p1; +@@ + +( +atomic_add_unless(&(a)->x,-1,1)@p1 +| +atomic_long_add_unless(&(a)->x,-1,1)@p1 +| +atomic64_add_unless(&(a)->x,-1,1)@p1 +) + +@script:python depends on report@ +p1 << r2.p1; +@@ +msg = "atomic_add_unless" +coccilib.report.print_report(p1[0], msg) + +@r3 exists@ +identifier x; +position p1; +@@ + +( +x = atomic_add_return@p1(-1, ...); +| +x = atomic_long_add_return@p1(-1, ...); +| +x = atomic64_add_return@p1(-1, ...); +) + +@script:python depends on report@ +p1 << r3.p1; +@@ +msg = "x = atomic_add_return(-1, ...)" +coccilib.report.print_report(p1[0], msg) diff --git a/src/net/scripts/coccinelle/api/check_bq27xxx_data.cocci b/src/net/scripts/coccinelle/api/check_bq27xxx_data.cocci new file mode 100644 index 0000000..fae539e --- /dev/null +++ b/src/net/scripts/coccinelle/api/check_bq27xxx_data.cocci @@ -0,0 +1,162 @@ +// SPDX-License-Identifier: GPL-2.0-only +/// Detect BQ27XXX_DATA structures with identical registers, dm registers or +/// properties. +//# Doesn't unfold macros used in register or property fields. +//# Requires OCaml scripting +/// +// Confidence: High +// Copyright: (C) 2017 Julia Lawall, Inria/LIP6, +// URL: http://coccinelle.lip6.fr/ +// Requires: 1.0.7 +// Keywords: BQ27XXX_DATA + +virtual report + +@initialize:ocaml@ +@@ + +let print_report p msg = + let p = List.hd p in + Printf.printf "%s:%d:%d-%d: %s" p.file p.line p.col p.col_end msg + +@str depends on report@ +type t; +identifier i,i1,i2; +expression e1,e2; +@@ + +t i[] = { + ..., + [e1] = BQ27XXX_DATA(i1,...), + ..., + [e2] = BQ27XXX_DATA(i2,...), + ..., +}; + +@script:ocaml tocheck@ +i1 << str.i1; +i2 << str.i2; +i1regs; i2regs; +i1dmregs; i2dmregs; +i1props; i2props; +@@ + +if not(i1 = i2) +then + begin + i1regs := make_ident (i1 ^ "_regs"); + i2regs := make_ident (i2 ^ "_regs"); + i1dmregs := make_ident (i1 ^ "_dm_regs"); + i2dmregs := make_ident (i2 ^ "_dm_regs"); + i1props := make_ident (i1 ^ "_props"); + i2props := make_ident (i2 ^ "_props") + end + +(* ---------------------------------------------------------------- *) + +@getregs1@ +typedef u8; +identifier tocheck.i1regs; +initializer list i1regs_vals; +position p1; +@@ + +u8 i1regs@p1[...] = { i1regs_vals, }; + +@getregs2@ +identifier tocheck.i2regs; +initializer list i2regs_vals; +position p2; +@@ + +u8 i2regs@p2[...] = { i2regs_vals, }; + +@script:ocaml@ +(_,i1regs_vals) << getregs1.i1regs_vals; +(_,i2regs_vals) << getregs2.i2regs_vals; +i1regs << tocheck.i1regs; +i2regs << tocheck.i2regs; +p1 << getregs1.p1; +p2 << getregs2.p2; +@@ + +if i1regs < i2regs && + List.sort compare i1regs_vals = List.sort compare i2regs_vals +then + let msg = + Printf.sprintf + "WARNING %s and %s (line %d) are identical\n" + i1regs i2regs (List.hd p2).line in + print_report p1 msg + +(* ---------------------------------------------------------------- *) + +@getdmregs1@ +identifier tocheck.i1dmregs; +initializer list i1dmregs_vals; +position p1; +@@ + +struct bq27xxx_dm_reg i1dmregs@p1[] = { i1dmregs_vals, }; + +@getdmregs2@ +identifier tocheck.i2dmregs; +initializer list i2dmregs_vals; +position p2; +@@ + +struct bq27xxx_dm_reg i2dmregs@p2[] = { i2dmregs_vals, }; + +@script:ocaml@ +(_,i1dmregs_vals) << getdmregs1.i1dmregs_vals; +(_,i2dmregs_vals) << getdmregs2.i2dmregs_vals; +i1dmregs << tocheck.i1dmregs; +i2dmregs << tocheck.i2dmregs; +p1 << getdmregs1.p1; +p2 << getdmregs2.p2; +@@ + +if i1dmregs < i2dmregs && + List.sort compare i1dmregs_vals = List.sort compare i2dmregs_vals +then + let msg = + Printf.sprintf + "WARNING %s and %s (line %d) are identical\n" + i1dmregs i2dmregs (List.hd p2).line in + print_report p1 msg + +(* ---------------------------------------------------------------- *) + +@getprops1@ +identifier tocheck.i1props; +initializer list[n1] i1props_vals; +position p1; +@@ + +enum power_supply_property i1props@p1[] = { i1props_vals, }; + +@getprops2@ +identifier tocheck.i2props; +initializer list[n2] i2props_vals; +position p2; +@@ + +enum power_supply_property i2props@p2[] = { i2props_vals, }; + +@script:ocaml@ +(_,i1props_vals) << getprops1.i1props_vals; +(_,i2props_vals) << getprops2.i2props_vals; +i1props << tocheck.i1props; +i2props << tocheck.i2props; +p1 << getprops1.p1; +p2 << getprops2.p2; +@@ + +if i1props < i2props && + List.sort compare i1props_vals = List.sort compare i2props_vals +then + let msg = + Printf.sprintf + "WARNING %s and %s (line %d) are identical\n" + i1props i2props (List.hd p2).line in + print_report p1 msg diff --git a/src/net/scripts/coccinelle/api/d_find_alias.cocci b/src/net/scripts/coccinelle/api/d_find_alias.cocci new file mode 100644 index 0000000..47e0501 --- /dev/null +++ b/src/net/scripts/coccinelle/api/d_find_alias.cocci @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0 +/// Make sure calls to d_find_alias() have a corresponding call to dput(). +// +// Keywords: d_find_alias, dput +// +// Confidence: Moderate +// URL: http://coccinelle.lip6.fr/ +// Options: --include-headers + +virtual context +virtual org +virtual patch +virtual report + +@r exists@ +local idexpression struct dentry *dent; +expression E, E1; +statement S1, S2; +position p1, p2; +@@ +( + if (!(dent@p1 = d_find_alias(...))) S1 +| + dent@p1 = d_find_alias(...) +) + +<...when != dput(dent) + when != if (...) { <+... dput(dent) ...+> } + when != true !dent || ... + when != dent = E + when != E = dent +if (!dent || ...) S2 +...> +( + return <+...dent...+>; +| + return @p2 ...; +| + dent@p2 = E1; +| + E1 = dent; +) + +@depends on context@ +local idexpression struct dentry *r.dent; +position r.p1,r.p2; +@@ +* dent@p1 = ... + ... +( +* return@p2 ...; +| +* dent@p2 +) + + +@script:python depends on org@ +p1 << r.p1; +p2 << r.p2; +@@ +cocci.print_main("Missing call to dput()",p1) +cocci.print_secs("",p2) + +@depends on patch@ +local idexpression struct dentry *r.dent; +position r.p2; +@@ +( ++ dput(dent); + return @p2 ...; +| ++ dput(dent); + dent@p2 = ...; +) + +@script:python depends on report@ +p1 << r.p1; +p2 << r.p2; +@@ +msg = "Missing call to dput() at line %s." +coccilib.report.print_report(p1[0], msg % (p2[0].line)) diff --git a/src/net/scripts/coccinelle/api/debugfs/debugfs_simple_attr.cocci b/src/net/scripts/coccinelle/api/debugfs/debugfs_simple_attr.cocci new file mode 100644 index 0000000..7c31231 --- /dev/null +++ b/src/net/scripts/coccinelle/api/debugfs/debugfs_simple_attr.cocci @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: GPL-2.0 +/// Use DEFINE_DEBUGFS_ATTRIBUTE rather than DEFINE_SIMPLE_ATTRIBUTE +/// for debugfs files. +/// +//# Rationale: DEFINE_SIMPLE_ATTRIBUTE + debugfs_create_file() +//# imposes some significant overhead as compared to +//# DEFINE_DEBUGFS_ATTRIBUTE + debugfs_create_file_unsafe(). +// +// Copyright (C): 2016 Nicolai Stange +// Options: --no-includes +// + +virtual context +virtual patch +virtual org +virtual report + +@dsa@ +declarer name DEFINE_SIMPLE_ATTRIBUTE; +identifier dsa_fops; +expression dsa_get, dsa_set, dsa_fmt; +position p; +@@ +DEFINE_SIMPLE_ATTRIBUTE@p(dsa_fops, dsa_get, dsa_set, dsa_fmt); + +@dcf@ +expression name, mode, parent, data; +identifier dsa.dsa_fops; +@@ +debugfs_create_file(name, mode, parent, data, &dsa_fops) + + +@context_dsa depends on context && dcf@ +declarer name DEFINE_DEBUGFS_ATTRIBUTE; +identifier dsa.dsa_fops; +expression dsa.dsa_get, dsa.dsa_set, dsa.dsa_fmt; +@@ +* DEFINE_SIMPLE_ATTRIBUTE(dsa_fops, dsa_get, dsa_set, dsa_fmt); + + +@patch_dcf depends on patch expression@ +expression name, mode, parent, data; +identifier dsa.dsa_fops; +@@ +- debugfs_create_file(name, mode, parent, data, &dsa_fops) ++ debugfs_create_file_unsafe(name, mode, parent, data, &dsa_fops) + +@patch_dsa depends on patch_dcf && patch@ +identifier dsa.dsa_fops; +expression dsa.dsa_get, dsa.dsa_set, dsa.dsa_fmt; +@@ +- DEFINE_SIMPLE_ATTRIBUTE(dsa_fops, dsa_get, dsa_set, dsa_fmt); ++ DEFINE_DEBUGFS_ATTRIBUTE(dsa_fops, dsa_get, dsa_set, dsa_fmt); + + +@script:python depends on org && dcf@ +fops << dsa.dsa_fops; +p << dsa.p; +@@ +msg="%s should be defined with DEFINE_DEBUGFS_ATTRIBUTE" % (fops) +coccilib.org.print_todo(p[0], msg) + +@script:python depends on report && dcf@ +fops << dsa.dsa_fops; +p << dsa.p; +@@ +msg="WARNING: %s should be defined with DEFINE_DEBUGFS_ATTRIBUTE" % (fops) +coccilib.report.print_report(p[0], msg) diff --git a/src/net/scripts/coccinelle/api/device_attr_show.cocci b/src/net/scripts/coccinelle/api/device_attr_show.cocci new file mode 100644 index 0000000..a28dc06 --- /dev/null +++ b/src/net/scripts/coccinelle/api/device_attr_show.cocci @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0-only +/// +/// From Documentation/filesystems/sysfs.rst: +/// show() must not use snprintf() when formatting the value to be +/// returned to user space. If you can guarantee that an overflow +/// will never happen you can use sprintf() otherwise you must use +/// scnprintf(). +/// +// Confidence: High +// Copyright: (C) 2020 Denis Efremov ISPRAS +// Options: --no-includes --include-headers +// + +virtual report +virtual org +virtual context +virtual patch + +@r depends on !patch@ +identifier show, dev, attr, buf; +position p; +@@ + +ssize_t show(struct device *dev, struct device_attribute *attr, char *buf) +{ + <... +* return snprintf@p(...); + ...> +} + +@rp depends on patch@ +identifier show, dev, attr, buf; +@@ + +ssize_t show(struct device *dev, struct device_attribute *attr, char *buf) +{ + <... + return +- snprintf ++ scnprintf + (...); + ...> +} + +@script: python depends on report@ +p << r.p; +@@ + +coccilib.report.print_report(p[0], "WARNING: use scnprintf or sprintf") + +@script: python depends on org@ +p << r.p; +@@ + +coccilib.org.print_todo(p[0], "WARNING: use scnprintf or sprintf") diff --git a/src/net/scripts/coccinelle/api/err_cast.cocci b/src/net/scripts/coccinelle/api/err_cast.cocci new file mode 100644 index 0000000..0e661c8 --- /dev/null +++ b/src/net/scripts/coccinelle/api/err_cast.cocci @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0-only +/// +/// Use ERR_CAST inlined function instead of ERR_PTR(PTR_ERR(...)) +/// +// Confidence: High +// Copyright: (C) 2009, 2010 Nicolas Palix, DIKU. +// Copyright: (C) 2009, 2010 Julia Lawall, DIKU. +// Copyright: (C) 2009, 2010 Gilles Muller, INRIA/LiP6. +// URL: http://coccinelle.lip6.fr/ +// Options: +// +// Keywords: ERR_PTR, PTR_ERR, ERR_CAST +// Version min: 2.6.25 +// + +virtual context +virtual patch +virtual org +virtual report + + +@ depends on context && !patch && !org && !report@ +expression x; +@@ + +* ERR_PTR(PTR_ERR(x)) + +@ depends on !context && patch && !org && !report @ +expression x; +@@ + +- ERR_PTR(PTR_ERR(x)) ++ ERR_CAST(x) + +@r depends on !context && !patch && (org || report)@ +expression x; +position p; +@@ + + ERR_PTR@p(PTR_ERR(x)) + +@script:python depends on org@ +p << r.p; +x << r.x; +@@ + +msg="WARNING ERR_CAST can be used with %s" % (x) +msg_safe=msg.replace("[","@(").replace("]",")") +coccilib.org.print_todo(p[0], msg_safe) + +@script:python depends on report@ +p << r.p; +x << r.x; +@@ + +msg="WARNING: ERR_CAST can be used with %s" % (x) +coccilib.report.print_report(p[0], msg) diff --git a/src/net/scripts/coccinelle/api/kfree_mismatch.cocci b/src/net/scripts/coccinelle/api/kfree_mismatch.cocci new file mode 100644 index 0000000..d46a9b3 --- /dev/null +++ b/src/net/scripts/coccinelle/api/kfree_mismatch.cocci @@ -0,0 +1,228 @@ +// SPDX-License-Identifier: GPL-2.0-only +/// +/// Check that kvmalloc'ed memory is freed by kfree functions, +/// vmalloc'ed by vfree functions and kvmalloc'ed by kvfree +/// functions. +/// +// Confidence: High +// Copyright: (C) 2020 Denis Efremov ISPRAS +// Options: --no-includes --include-headers +// + +virtual patch +virtual report +virtual org +virtual context + +@alloc@ +expression E, E1; +position kok, vok; +@@ + +( + if (...) { + ... + E = \(kmalloc\|kzalloc\|krealloc\|kcalloc\| + kmalloc_node\|kzalloc_node\|kmalloc_array\| + kmalloc_array_node\|kcalloc_node\)(...)@kok + ... + } else { + ... + E = \(vmalloc\|vzalloc\|vmalloc_user\|vmalloc_node\| + vzalloc_node\|vmalloc_exec\|vmalloc_32\| + vmalloc_32_user\|__vmalloc\|__vmalloc_node_range\| + __vmalloc_node\)(...)@vok + ... + } +| + E = \(kmalloc\|kzalloc\|krealloc\|kcalloc\|kmalloc_node\|kzalloc_node\| + kmalloc_array\|kmalloc_array_node\|kcalloc_node\)(...)@kok + ... when != E = E1 + when any + if (E == NULL) { + ... + E = \(vmalloc\|vzalloc\|vmalloc_user\|vmalloc_node\| + vzalloc_node\|vmalloc_exec\|vmalloc_32\| + vmalloc_32_user\|__vmalloc\|__vmalloc_node_range\| + __vmalloc_node\)(...)@vok + ... + } +) + +@free@ +expression E; +position fok; +@@ + + E = \(kvmalloc\|kvzalloc\|kvcalloc\|kvzalloc_node\|kvmalloc_node\| + kvmalloc_array\)(...) + ... + kvfree(E)@fok + +@vfree depends on !patch@ +expression E; +position a != alloc.kok; +position f != free.fok; +@@ + +* E = \(kmalloc\|kzalloc\|krealloc\|kcalloc\|kmalloc_node\| +* kzalloc_node\|kmalloc_array\|kmalloc_array_node\| +* kcalloc_node\)(...)@a + ... when != if (...) { ... E = \(vmalloc\|vzalloc\|vmalloc_user\|vmalloc_node\|vzalloc_node\|vmalloc_exec\|vmalloc_32\|vmalloc_32_user\|__vmalloc\|__vmalloc_node_range\|__vmalloc_node\)(...); ... } + when != is_vmalloc_addr(E) + when any +* \(vfree\|vfree_atomic\|kvfree\)(E)@f + +@depends on patch exists@ +expression E; +position a != alloc.kok; +position f != free.fok; +@@ + + E = \(kmalloc\|kzalloc\|krealloc\|kcalloc\|kmalloc_node\| + kzalloc_node\|kmalloc_array\|kmalloc_array_node\| + kcalloc_node\)(...)@a + ... when != if (...) { ... E = \(vmalloc\|vzalloc\|vmalloc_user\|vmalloc_node\|vzalloc_node\|vmalloc_exec\|vmalloc_32\|vmalloc_32_user\|__vmalloc\|__vmalloc_node_range\|__vmalloc_node\)(...); ... } + when != is_vmalloc_addr(E) + when any +- \(vfree\|vfree_atomic\|kvfree\)(E)@f ++ kfree(E) + +@kfree depends on !patch@ +expression E; +position a != alloc.vok; +position f != free.fok; +@@ + +* E = \(vmalloc\|vzalloc\|vmalloc_user\|vmalloc_node\|vzalloc_node\| +* vmalloc_exec\|vmalloc_32\|vmalloc_32_user\|__vmalloc\| +* __vmalloc_node_range\|__vmalloc_node\)(...)@a + ... when != is_vmalloc_addr(E) + when any +* \(kfree\|kfree_sensitive\|kvfree\)(E)@f + +@depends on patch exists@ +expression E; +position a != alloc.vok; +position f != free.fok; +@@ + + E = \(vmalloc\|vzalloc\|vmalloc_user\|vmalloc_node\|vzalloc_node\| + vmalloc_exec\|vmalloc_32\|vmalloc_32_user\|__vmalloc\| + __vmalloc_node_range\|__vmalloc_node\)(...)@a + ... when != is_vmalloc_addr(E) + when any +- \(kfree\|kvfree\)(E)@f ++ vfree(E) + +@kvfree depends on !patch@ +expression E; +position a, f; +@@ + +* E = \(kvmalloc\|kvzalloc\|kvcalloc\|kvzalloc_node\|kvmalloc_node\| +* kvmalloc_array\)(...)@a + ... when != is_vmalloc_addr(E) + when any +* \(kfree\|kfree_sensitive\|vfree\|vfree_atomic\)(E)@f + +@depends on patch exists@ +expression E; +@@ + + E = \(kvmalloc\|kvzalloc\|kvcalloc\|kvzalloc_node\|kvmalloc_node\| + kvmalloc_array\)(...) + ... when != is_vmalloc_addr(E) + when any +- \(kfree\|vfree\)(E) ++ kvfree(E) + +@kvfree_switch depends on !patch@ +expression alloc.E; +position f; +@@ + + ... when != is_vmalloc_addr(E) + when any +* \(kfree\|kfree_sensitive\|vfree\|vfree_atomic\)(E)@f + +@depends on patch exists@ +expression alloc.E; +position f; +@@ + + ... when != is_vmalloc_addr(E) + when any +( +- \(kfree\|vfree\)(E)@f ++ kvfree(E) +| +- kfree_sensitive(E)@f ++ kvfree_sensitive(E) +) + +@script: python depends on report@ +a << vfree.a; +f << vfree.f; +@@ + +msg = "WARNING kmalloc is used to allocate this memory at line %s" % (a[0].line) +coccilib.report.print_report(f[0], msg) + +@script: python depends on org@ +a << vfree.a; +f << vfree.f; +@@ + +msg = "WARNING kmalloc is used to allocate this memory at line %s" % (a[0].line) +coccilib.org.print_todo(f[0], msg) + +@script: python depends on report@ +a << kfree.a; +f << kfree.f; +@@ + +msg = "WARNING vmalloc is used to allocate this memory at line %s" % (a[0].line) +coccilib.report.print_report(f[0], msg) + +@script: python depends on org@ +a << kfree.a; +f << kfree.f; +@@ + +msg = "WARNING vmalloc is used to allocate this memory at line %s" % (a[0].line) +coccilib.org.print_todo(f[0], msg) + +@script: python depends on report@ +a << kvfree.a; +f << kvfree.f; +@@ + +msg = "WARNING kvmalloc is used to allocate this memory at line %s" % (a[0].line) +coccilib.report.print_report(f[0], msg) + +@script: python depends on org@ +a << kvfree.a; +f << kvfree.f; +@@ + +msg = "WARNING kvmalloc is used to allocate this memory at line %s" % (a[0].line) +coccilib.org.print_todo(f[0], msg) + +@script: python depends on report@ +ka << alloc.kok; +va << alloc.vok; +f << kvfree_switch.f; +@@ + +msg = "WARNING kmalloc (line %s) && vmalloc (line %s) are used to allocate this memory" % (ka[0].line, va[0].line) +coccilib.report.print_report(f[0], msg) + +@script: python depends on org@ +ka << alloc.kok; +va << alloc.vok; +f << kvfree_switch.f; +@@ + +msg = "WARNING kmalloc (line %s) && vmalloc (line %s) are used to allocate this memory" % (ka[0].line, va[0].line) +coccilib.org.print_todo(f[0], msg) diff --git a/src/net/scripts/coccinelle/api/kfree_sensitive.cocci b/src/net/scripts/coccinelle/api/kfree_sensitive.cocci new file mode 100644 index 0000000..8d980eb --- /dev/null +++ b/src/net/scripts/coccinelle/api/kfree_sensitive.cocci @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0-only +/// +/// Use kfree_sensitive, kvfree_sensitive rather than memset or +/// memzero_explicit followed by kfree. +/// +// Confidence: High +// Copyright: (C) 2020 Denis Efremov ISPRAS +// Options: --no-includes --include-headers +// +// Keywords: kfree_sensitive, kvfree_sensitive +// + +virtual context +virtual patch +virtual org +virtual report + +@initialize:python@ +@@ +# kmalloc_oob_in_memset uses memset to explicitly trigger out-of-bounds access +filter = frozenset(['kmalloc_oob_in_memset', + 'kfree_sensitive', 'kvfree_sensitive']) + +def relevant(p): + return not (filter & {el.current_element for el in p}) + +@cond@ +position ok; +@@ + +if (...) + \(memset@ok\|memzero_explicit@ok\)(...); + +@r depends on !patch forall@ +expression E; +position p : script:python() { relevant(p) }; +position m != cond.ok; +type T; +@@ + +( +* memset@m((T)E, 0, ...); +| +* memzero_explicit@m((T)E, ...); +) + ... when != E + when strict +* \(kfree\|vfree\|kvfree\)(E)@p; + +@rp_memzero depends on patch@ +expression E, size; +position p : script:python() { relevant(p) }; +position m != cond.ok; +type T; +@@ + +- memzero_explicit@m((T)E, size); + ... when != E + when strict +( +- kfree(E)@p; ++ kfree_sensitive(E); +| +- \(vfree\|kvfree\)(E)@p; ++ kvfree_sensitive(E, size); +) + +@rp_memset depends on patch@ +expression E, size; +position p : script:python() { relevant(p) }; +position m != cond.ok; +type T; +@@ + +- memset@m((T)E, 0, size); + ... when != E + when strict +( +- kfree(E)@p; ++ kfree_sensitive(E); +| +- \(vfree\|kvfree\)(E)@p; ++ kvfree_sensitive(E, size); +) + +@script:python depends on report@ +p << r.p; +m << r.m; +@@ + +msg = "WARNING opportunity for kfree_sensitive/kvfree_sensitive (memset at line %s)" +coccilib.report.print_report(p[0], msg % (m[0].line)) + +@script:python depends on org@ +p << r.p; +m << r.m; +@@ + +msg = "WARNING opportunity for kfree_sensitive/kvfree_sensitive (memset at line %s)" +coccilib.org.print_todo(p[0], msg % (m[0].line)) diff --git a/src/net/scripts/coccinelle/api/kobj_to_dev.cocci b/src/net/scripts/coccinelle/api/kobj_to_dev.cocci new file mode 100644 index 0000000..cd5d31c --- /dev/null +++ b/src/net/scripts/coccinelle/api/kobj_to_dev.cocci @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0-only +/// +/// Use kobj_to_dev() instead of container_of() +/// +// Confidence: High +// Copyright: (C) 2020 Denis Efremov ISPRAS +// Options: --no-includes --include-headers +// +// Keywords: kobj_to_dev, container_of +// + +virtual context +virtual report +virtual org +virtual patch + + +@r depends on !patch@ +expression ptr; +symbol kobj; +position p; +@@ + +* container_of(ptr, struct device, kobj)@p + + +@depends on patch@ +expression ptr; +@@ + +- container_of(ptr, struct device, kobj) ++ kobj_to_dev(ptr) + + +@script:python depends on report@ +p << r.p; +@@ + +coccilib.report.print_report(p[0], "WARNING opportunity for kobj_to_dev()") + +@script:python depends on org@ +p << r.p; +@@ + +coccilib.org.print_todo(p[0], "WARNING opportunity for kobj_to_dev()") diff --git a/src/net/scripts/coccinelle/api/kstrdup.cocci b/src/net/scripts/coccinelle/api/kstrdup.cocci new file mode 100644 index 0000000..3c6dc54 --- /dev/null +++ b/src/net/scripts/coccinelle/api/kstrdup.cocci @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0-only +/// Use kstrdup rather than duplicating its implementation +/// +// Confidence: High +// Copyright: (C) 2010-2012 Nicolas Palix. +// Copyright: (C) 2010-2012 Julia Lawall, INRIA/LIP6. +// Copyright: (C) 2010-2012 Gilles Muller, INRIA/LiP6. +// URL: http://coccinelle.lip6.fr/ +// Comments: +// Options: --no-includes --include-headers + +virtual patch +virtual context +virtual org +virtual report + +@depends on patch@ +expression from,to; +expression flag,E1,E2; +statement S; +@@ + +- to = kmalloc(strlen(from) + 1,flag); ++ to = kstrdup(from, flag); + ... when != \(from = E1 \| to = E1 \) + if (to==NULL || ...) S + ... when != \(from = E2 \| to = E2 \) +- strcpy(to, from); + +@depends on patch@ +expression x,from,to; +expression flag,E1,E2,E3; +statement S; +@@ + +- x = strlen(from) + 1; + ... when != \( x = E1 \| from = E1 \) +- to = \(kmalloc\|kzalloc\)(x,flag); ++ to = kstrdup(from, flag); + ... when != \(x = E2 \| from = E2 \| to = E2 \) + if (to==NULL || ...) S + ... when != \(x = E3 \| from = E3 \| to = E3 \) +- memcpy(to, from, x); + +// --------------------------------------------------------------------- + +@r1 depends on !patch exists@ +expression from,to; +expression flag,E1,E2; +statement S; +position p1,p2; +@@ + +* to = kmalloc@p1(strlen(from) + 1,flag); + ... when != \(from = E1 \| to = E1 \) + if (to==NULL || ...) S + ... when != \(from = E2 \| to = E2 \) +* strcpy@p2(to, from); + +@r2 depends on !patch exists@ +expression x,from,to; +expression flag,E1,E2,E3; +statement S; +position p1,p2; +@@ + +* x = strlen(from) + 1; + ... when != \( x = E1 \| from = E1 \) +* to = \(kmalloc@p1\|kzalloc@p1\)(x,flag); + ... when != \(x = E2 \| from = E2 \| to = E2 \) + if (to==NULL || ...) S + ... when != \(x = E3 \| from = E3 \| to = E3 \) +* memcpy@p2(to, from, x); + +@script:python depends on org@ +p1 << r1.p1; +p2 << r1.p2; +@@ + +cocci.print_main("WARNING opportunity for kstrdup",p1) +cocci.print_secs("strcpy",p2) + +@script:python depends on org@ +p1 << r2.p1; +p2 << r2.p2; +@@ + +cocci.print_main("WARNING opportunity for kstrdup",p1) +cocci.print_secs("memcpy",p2) + +@script:python depends on report@ +p1 << r1.p1; +p2 << r1.p2; +@@ + +msg = "WARNING opportunity for kstrdup (strcpy on line %s)" % (p2[0].line) +coccilib.report.print_report(p1[0], msg) + +@script:python depends on report@ +p1 << r2.p1; +p2 << r2.p2; +@@ + +msg = "WARNING opportunity for kstrdup (memcpy on line %s)" % (p2[0].line) +coccilib.report.print_report(p1[0], msg) diff --git a/src/net/scripts/coccinelle/api/kvmalloc.cocci b/src/net/scripts/coccinelle/api/kvmalloc.cocci new file mode 100644 index 0000000..c30dab7 --- /dev/null +++ b/src/net/scripts/coccinelle/api/kvmalloc.cocci @@ -0,0 +1,256 @@ +// SPDX-License-Identifier: GPL-2.0-only +/// +/// Find if/else condition with kmalloc/vmalloc calls. +/// Suggest to use kvmalloc instead. Same for kvfree. +/// +// Confidence: High +// Copyright: (C) 2020 Denis Efremov ISPRAS +// Options: --no-includes --include-headers +// + +virtual patch +virtual report +virtual org +virtual context + +@initialize:python@ +@@ +filter = frozenset(['kvfree']) + +def relevant(p): + return not (filter & {el.current_element for el in p}) + +@kvmalloc depends on !patch@ +expression E, E1, size; +identifier flags; +binary operator cmp = {<=, <, ==, >, >=}; +identifier x; +type T; +position p; +@@ + +( +* if (size cmp E1 || ...)@p { + ... +* E = \(kmalloc\|kzalloc\|kcalloc\|kmalloc_node\|kzalloc_node\| +* kmalloc_array\|kmalloc_array_node\|kcalloc_node\) +* (..., size, \(flags\|GFP_KERNEL\|\(GFP_KERNEL\|flags\)|__GFP_NOWARN\), ...) + ... + } else { + ... +* E = \(vmalloc\|vzalloc\|vmalloc_node\|vzalloc_node\)(..., size, ...) + ... + } +| +* E = \(kmalloc\|kzalloc\|kcalloc\|kmalloc_node\|kzalloc_node\| +* kmalloc_array\|kmalloc_array_node\|kcalloc_node\) +* (..., size, \(flags\|GFP_KERNEL\|\(GFP_KERNEL\|flags\)|__GFP_NOWARN\), ...) + ... when != E = E1 + when != size = E1 + when any +* if (E == NULL)@p { + ... +* E = \(vmalloc\|vzalloc\|vmalloc_node\|vzalloc_node\)(..., size, ...) + ... + } +| +* T x = \(kmalloc\|kzalloc\|kcalloc\|kmalloc_node\|kzalloc_node\| +* kmalloc_array\|kmalloc_array_node\|kcalloc_node\) +* (..., size, \(flags\|GFP_KERNEL\|\(GFP_KERNEL\|flags\)|__GFP_NOWARN\), ...); + ... when != x = E1 + when != size = E1 + when any +* if (x == NULL)@p { + ... +* x = \(vmalloc\|vzalloc\|vmalloc_node\|vzalloc_node\)(..., size, ...) + ... + } +) + +@kvfree depends on !patch@ +expression E; +position p : script:python() { relevant(p) }; +@@ + +* if (is_vmalloc_addr(E))@p { + ... +* vfree(E) + ... + } else { + ... when != krealloc(E, ...) + when any +* \(kfree\|kzfree\)(E) + ... + } + +@depends on patch@ +expression E, E1, size, node; +binary operator cmp = {<=, <, ==, >, >=}; +identifier flags, x; +type T; +@@ + +( +- if (size cmp E1) +- E = kmalloc(size, flags); +- else +- E = vmalloc(size); ++ E = kvmalloc(size, flags); +| +- if (size cmp E1) +- E = kmalloc(size, \(GFP_KERNEL\|GFP_KERNEL|__GFP_NOWARN\)); +- else +- E = vmalloc(size); ++ E = kvmalloc(size, GFP_KERNEL); +| +- E = kmalloc(size, flags | __GFP_NOWARN); +- if (E == NULL) +- E = vmalloc(size); ++ E = kvmalloc(size, flags); +| +- E = kmalloc(size, \(GFP_KERNEL\|GFP_KERNEL|__GFP_NOWARN\)); +- if (E == NULL) +- E = vmalloc(size); ++ E = kvmalloc(size, GFP_KERNEL); +| +- T x = kmalloc(size, flags | __GFP_NOWARN); +- if (x == NULL) +- x = vmalloc(size); ++ T x = kvmalloc(size, flags); +| +- T x = kmalloc(size, \(GFP_KERNEL\|GFP_KERNEL|__GFP_NOWARN\)); +- if (x == NULL) +- x = vmalloc(size); ++ T x = kvmalloc(size, GFP_KERNEL); +| +- if (size cmp E1) +- E = kzalloc(size, flags); +- else +- E = vzalloc(size); ++ E = kvzalloc(size, flags); +| +- if (size cmp E1) +- E = kzalloc(size, \(GFP_KERNEL\|GFP_KERNEL|__GFP_NOWARN\)); +- else +- E = vzalloc(size); ++ E = kvzalloc(size, GFP_KERNEL); +| +- E = kzalloc(size, flags | __GFP_NOWARN); +- if (E == NULL) +- E = vzalloc(size); ++ E = kvzalloc(size, flags); +| +- E = kzalloc(size, \(GFP_KERNEL\|GFP_KERNEL|__GFP_NOWARN\)); +- if (E == NULL) +- E = vzalloc(size); ++ E = kvzalloc(size, GFP_KERNEL); +| +- T x = kzalloc(size, flags | __GFP_NOWARN); +- if (x == NULL) +- x = vzalloc(size); ++ T x = kvzalloc(size, flags); +| +- T x = kzalloc(size, \(GFP_KERNEL\|GFP_KERNEL|__GFP_NOWARN\)); +- if (x == NULL) +- x = vzalloc(size); ++ T x = kvzalloc(size, GFP_KERNEL); +| +- if (size cmp E1) +- E = kmalloc_node(size, flags, node); +- else +- E = vmalloc_node(size, node); ++ E = kvmalloc_node(size, flags, node); +| +- if (size cmp E1) +- E = kmalloc_node(size, \(GFP_KERNEL\|GFP_KERNEL|__GFP_NOWARN\), node); +- else +- E = vmalloc_node(size, node); ++ E = kvmalloc_node(size, GFP_KERNEL, node); +| +- E = kmalloc_node(size, flags | __GFP_NOWARN, node); +- if (E == NULL) +- E = vmalloc_node(size, node); ++ E = kvmalloc_node(size, flags, node); +| +- E = kmalloc_node(size, \(GFP_KERNEL\|GFP_KERNEL|__GFP_NOWARN\), node); +- if (E == NULL) +- E = vmalloc_node(size, node); ++ E = kvmalloc_node(size, GFP_KERNEL, node); +| +- T x = kmalloc_node(size, flags | __GFP_NOWARN, node); +- if (x == NULL) +- x = vmalloc_node(size, node); ++ T x = kvmalloc_node(size, flags, node); +| +- T x = kmalloc_node(size, \(GFP_KERNEL\|GFP_KERNEL|__GFP_NOWARN\), node); +- if (x == NULL) +- x = vmalloc_node(size, node); ++ T x = kvmalloc_node(size, GFP_KERNEL, node); +| +- if (size cmp E1) +- E = kvzalloc_node(size, flags, node); +- else +- E = vzalloc_node(size, node); ++ E = kvzalloc_node(size, flags, node); +| +- if (size cmp E1) +- E = kvzalloc_node(size, \(GFP_KERNEL\|GFP_KERNEL|__GFP_NOWARN\), node); +- else +- E = vzalloc_node(size, node); ++ E = kvzalloc_node(size, GFP_KERNEL, node); +| +- E = kvzalloc_node(size, flags | __GFP_NOWARN, node); +- if (E == NULL) +- E = vzalloc_node(size, node); ++ E = kvzalloc_node(size, flags, node); +| +- E = kvzalloc_node(size, \(GFP_KERNEL\|GFP_KERNEL|__GFP_NOWARN\), node); +- if (E == NULL) +- E = vzalloc_node(size, node); ++ E = kvzalloc_node(size, GFP_KERNEL, node); +| +- T x = kvzalloc_node(size, flags | __GFP_NOWARN, node); +- if (x == NULL) +- x = vzalloc_node(size, node); ++ T x = kvzalloc_node(size, flags, node); +| +- T x = kvzalloc_node(size, \(GFP_KERNEL\|GFP_KERNEL|__GFP_NOWARN\), node); +- if (x == NULL) +- x = vzalloc_node(size, node); ++ T x = kvzalloc_node(size, GFP_KERNEL, node); +) + +@depends on patch@ +expression E; +position p : script:python() { relevant(p) }; +@@ + +- if (is_vmalloc_addr(E))@p +- vfree(E); +- else +- kfree(E); ++ kvfree(E); + +@script: python depends on report@ +p << kvmalloc.p; +@@ + +coccilib.report.print_report(p[0], "WARNING opportunity for kvmalloc") + +@script: python depends on org@ +p << kvmalloc.p; +@@ + +coccilib.org.print_todo(p[0], "WARNING opportunity for kvmalloc") + +@script: python depends on report@ +p << kvfree.p; +@@ + +coccilib.report.print_report(p[0], "WARNING opportunity for kvfree") + +@script: python depends on org@ +p << kvfree.p; +@@ + +coccilib.org.print_todo(p[0], "WARNING opportunity for kvfree") diff --git a/src/net/scripts/coccinelle/api/memdup.cocci b/src/net/scripts/coccinelle/api/memdup.cocci new file mode 100644 index 0000000..30b15df --- /dev/null +++ b/src/net/scripts/coccinelle/api/memdup.cocci @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0-only +/// Use kmemdup rather than duplicating its implementation +/// +// Confidence: High +// Copyright: (C) 2010-2012 Nicolas Palix. +// Copyright: (C) 2010-2012 Julia Lawall, INRIA/LIP6. +// Copyright: (C) 2010-2012 Gilles Muller, INRIA/LiP6. +// URL: http://coccinelle.lip6.fr/ +// Comments: +// Options: --no-includes --include-headers + +virtual patch +virtual context +virtual org +virtual report + +@r1@ +expression from,to; +expression flag; +position p; +@@ + + to = \(kmalloc@p\|kzalloc@p\)(strlen(from) + 1,flag); + +@r2@ +expression x,from,to; +expression flag,E1; +position p; +@@ + + x = strlen(from) + 1; + ... when != \( x = E1 \| from = E1 \) + to = \(kmalloc@p\|kzalloc@p\)(x,flag); + +@depends on patch@ +expression from,to,size,flag; +position p != {r1.p,r2.p}; +statement S; +@@ + +- to = \(kmalloc@p\|kzalloc@p\)(size,flag); ++ to = kmemdup(from,size,flag); + if (to==NULL || ...) S +- memcpy(to, from, size); + +@r depends on !patch@ +expression from,to,size,flag; +position p != {r1.p,r2.p}; +statement S; +@@ + +* to = \(kmalloc@p\|kzalloc@p\)(size,flag); + if (to==NULL || ...) S +* memcpy(to, from, size); + +@script:python depends on org@ +p << r.p; +@@ + +coccilib.org.print_todo(p[0], "WARNING opportunity for kmemdup") + +@script:python depends on report@ +p << r.p; +@@ + +coccilib.report.print_report(p[0], "WARNING opportunity for kmemdup") diff --git a/src/net/scripts/coccinelle/api/memdup_user.cocci b/src/net/scripts/coccinelle/api/memdup_user.cocci new file mode 100644 index 0000000..e01e951 --- /dev/null +++ b/src/net/scripts/coccinelle/api/memdup_user.cocci @@ -0,0 +1,119 @@ +// SPDX-License-Identifier: GPL-2.0-only +/// Use memdup_user rather than duplicating its implementation +/// This is a little bit restricted to reduce false positives +/// +// Confidence: High +// Copyright: (C) 2010-2012 Nicolas Palix. +// Copyright: (C) 2010-2012 Julia Lawall, INRIA/LIP6. +// Copyright: (C) 2010-2012 Gilles Muller, INRIA/LiP6. +// URL: http://coccinelle.lip6.fr/ +// Comments: +// Options: --no-includes --include-headers + +virtual patch +virtual context +virtual org +virtual report + +@initialize:python@ +@@ +filter = frozenset(['memdup_user', 'vmemdup_user']) + +def relevant(p): + return not (filter & {el.current_element for el in p}) + +@depends on patch@ +expression from,to,size; +identifier l1,l2; +position p : script:python() { relevant(p) }; +@@ + +- to = \(kmalloc@p\|kzalloc@p\) +- (size,\(GFP_KERNEL\|GFP_USER\| +- \(GFP_KERNEL\|GFP_USER\)|__GFP_NOWARN\)); ++ to = memdup_user(from,size); + if ( +- to==NULL ++ IS_ERR(to) + || ...) { + <+... when != goto l1; +- -ENOMEM ++ PTR_ERR(to) + ...+> + } +- if (copy_from_user(to, from, size) != 0) { +- <+... when != goto l2; +- -EFAULT +- ...+> +- } + +@depends on patch@ +expression from,to,size; +identifier l1,l2; +position p : script:python() { relevant(p) }; +@@ + +- to = \(kvmalloc@p\|kvzalloc@p\)(size,\(GFP_KERNEL\|GFP_USER\)); ++ to = vmemdup_user(from,size); + if ( +- to==NULL ++ IS_ERR(to) + || ...) { + <+... when != goto l1; +- -ENOMEM ++ PTR_ERR(to) + ...+> + } +- if (copy_from_user(to, from, size) != 0) { +- <+... when != goto l2; +- -EFAULT +- ...+> +- } + +@r depends on !patch@ +expression from,to,size; +position p : script:python() { relevant(p) }; +statement S1,S2; +@@ + +* to = \(kmalloc@p\|kzalloc@p\) + (size,\(GFP_KERNEL\|GFP_USER\| + \(GFP_KERNEL\|GFP_USER\)|__GFP_NOWARN\)); + if (to==NULL || ...) S1 + if (copy_from_user(to, from, size) != 0) + S2 + +@rv depends on !patch@ +expression from,to,size; +position p : script:python() { relevant(p) }; +statement S1,S2; +@@ + +* to = \(kvmalloc@p\|kvzalloc@p\)(size,\(GFP_KERNEL\|GFP_USER\)); + if (to==NULL || ...) S1 + if (copy_from_user(to, from, size) != 0) + S2 + +@script:python depends on org@ +p << r.p; +@@ + +coccilib.org.print_todo(p[0], "WARNING opportunity for memdup_user") + +@script:python depends on report@ +p << r.p; +@@ + +coccilib.report.print_report(p[0], "WARNING opportunity for memdup_user") + +@script:python depends on org@ +p << rv.p; +@@ + +coccilib.org.print_todo(p[0], "WARNING opportunity for vmemdup_user") + +@script:python depends on report@ +p << rv.p; +@@ + +coccilib.report.print_report(p[0], "WARNING opportunity for vmemdup_user") diff --git a/src/net/scripts/coccinelle/api/platform_get_irq.cocci b/src/net/scripts/coccinelle/api/platform_get_irq.cocci new file mode 100644 index 0000000..06b6a95 --- /dev/null +++ b/src/net/scripts/coccinelle/api/platform_get_irq.cocci @@ -0,0 +1,102 @@ +// SPDX-License-Identifier: GPL-2.0 +/// Remove dev_err() messages after platform_get_irq*() failures +// +// Confidence: Medium +// Options: --include-headers + +virtual patch +virtual context +virtual org +virtual report + +@depends on context@ +expression ret; +struct platform_device *E; +@@ + +ret = +( +platform_get_irq +| +platform_get_irq_byname +)(E, ...); + +if ( \( ret < 0 \| ret <= 0 \) ) +{ +( +if (ret != -EPROBE_DEFER) +{ ... +*dev_err(...); +... } +| +... +*dev_err(...); +) +... +} + +@depends on patch@ +expression ret; +struct platform_device *E; +@@ + +ret = +( +platform_get_irq +| +platform_get_irq_byname +)(E, ...); + +if ( \( ret < 0 \| ret <= 0 \) ) +{ +( +-if (ret != -EPROBE_DEFER) +-{ ... +-dev_err(...); +-... } +| +... +-dev_err(...); +) +... +} + +@r depends on org || report@ +position p1; +expression ret; +struct platform_device *E; +@@ + +ret = +( +platform_get_irq +| +platform_get_irq_byname +)(E, ...); + +if ( \( ret < 0 \| ret <= 0 \) ) +{ +( +if (ret != -EPROBE_DEFER) +{ ... +dev_err@p1(...); +... } +| +... +dev_err@p1(...); +) +... +} + +@script:python depends on org@ +p1 << r.p1; +@@ + +cocci.print_main(p1) + +@script:python depends on report@ +p1 << r.p1; +@@ + +msg = "line %s is redundant because platform_get_irq() already prints an error" % (p1[0].line) +coccilib.report.print_report(p1[0],msg) diff --git a/src/net/scripts/coccinelle/api/platform_no_drv_owner.cocci b/src/net/scripts/coccinelle/api/platform_no_drv_owner.cocci new file mode 100644 index 0000000..8fa050e --- /dev/null +++ b/src/net/scripts/coccinelle/api/platform_no_drv_owner.cocci @@ -0,0 +1,180 @@ +// SPDX-License-Identifier: GPL-2.0-only +/// Remove .owner field if calls are used which set it automatically +/// +// Confidence: High +// Copyright: (C) 2014 Wolfram Sang. + +virtual patch +virtual context +virtual org +virtual report + +@match1@ +declarer name module_i2c_driver; +declarer name module_platform_driver; +declarer name module_platform_driver_probe; +identifier __driver; +@@ +( + module_i2c_driver(__driver); +| + module_platform_driver(__driver); +| + module_platform_driver_probe(__driver, ...); +) + +@fix1 depends on match1 && patch && !context && !org && !report@ +identifier match1.__driver; +@@ + static struct platform_driver __driver = { + .driver = { +- .owner = THIS_MODULE, + } + }; + +@fix1_i2c depends on match1 && patch && !context && !org && !report@ +identifier match1.__driver; +@@ + static struct i2c_driver __driver = { + .driver = { +- .owner = THIS_MODULE, + } + }; + +@match2@ +identifier __driver; +@@ +( + platform_driver_register(&__driver) +| + platform_driver_probe(&__driver, ...) +| + platform_create_bundle(&__driver, ...) +| + i2c_add_driver(&__driver) +) + +@fix2 depends on match2 && patch && !context && !org && !report@ +identifier match2.__driver; +@@ + static struct platform_driver __driver = { + .driver = { +- .owner = THIS_MODULE, + } + }; + +@fix2_i2c depends on match2 && patch && !context && !org && !report@ +identifier match2.__driver; +@@ + static struct i2c_driver __driver = { + .driver = { +- .owner = THIS_MODULE, + } + }; + +// ---------------------------------------------------------------------------- + +@fix1_context depends on match1 && !patch && (context || org || report)@ +identifier match1.__driver; +position j0; +@@ + + static struct platform_driver __driver = { + .driver = { +* .owner@j0 = THIS_MODULE, + } + }; + +@fix1_i2c_context depends on match1 && !patch && (context || org || report)@ +identifier match1.__driver; +position j0; +@@ + + static struct i2c_driver __driver = { + .driver = { +* .owner@j0 = THIS_MODULE, + } + }; + +@fix2_context depends on match2 && !patch && (context || org || report)@ +identifier match2.__driver; +position j0; +@@ + + static struct platform_driver __driver = { + .driver = { +* .owner@j0 = THIS_MODULE, + } + }; + +@fix2_i2c_context depends on match2 && !patch && (context || org || report)@ +identifier match2.__driver; +position j0; +@@ + + static struct i2c_driver __driver = { + .driver = { +* .owner@j0 = THIS_MODULE, + } + }; + +// ---------------------------------------------------------------------------- + +@script:python fix1_org depends on org@ +j0 << fix1_context.j0; +@@ + +msg = "No need to set .owner here. The core will do it." +coccilib.org.print_todo(j0[0], msg) + +@script:python fix1_i2c_org depends on org@ +j0 << fix1_i2c_context.j0; +@@ + +msg = "No need to set .owner here. The core will do it." +coccilib.org.print_todo(j0[0], msg) + +@script:python fix2_org depends on org@ +j0 << fix2_context.j0; +@@ + +msg = "No need to set .owner here. The core will do it." +coccilib.org.print_todo(j0[0], msg) + +@script:python fix2_i2c_org depends on org@ +j0 << fix2_i2c_context.j0; +@@ + +msg = "No need to set .owner here. The core will do it." +coccilib.org.print_todo(j0[0], msg) + +// ---------------------------------------------------------------------------- + +@script:python fix1_report depends on report@ +j0 << fix1_context.j0; +@@ + +msg = "No need to set .owner here. The core will do it." +coccilib.report.print_report(j0[0], msg) + +@script:python fix1_i2c_report depends on report@ +j0 << fix1_i2c_context.j0; +@@ + +msg = "No need to set .owner here. The core will do it." +coccilib.report.print_report(j0[0], msg) + +@script:python fix2_report depends on report@ +j0 << fix2_context.j0; +@@ + +msg = "No need to set .owner here. The core will do it." +coccilib.report.print_report(j0[0], msg) + +@script:python fix2_i2c_report depends on report@ +j0 << fix2_i2c_context.j0; +@@ + +msg = "No need to set .owner here. The core will do it." +coccilib.report.print_report(j0[0], msg) + diff --git a/src/net/scripts/coccinelle/api/pm_runtime.cocci b/src/net/scripts/coccinelle/api/pm_runtime.cocci new file mode 100644 index 0000000..1ccce3f --- /dev/null +++ b/src/net/scripts/coccinelle/api/pm_runtime.cocci @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: GPL-2.0-only +/// Make sure pm_runtime_* calls does not use unnecessary IS_ERR_VALUE +/// +// Keywords: pm_runtime +// Confidence: Medium +// Copyright (C) 2013 Texas Instruments Incorporated - +// URL: http://coccinelle.lip6.fr/ +// Options: --include-headers + +virtual patch +virtual context +virtual org +virtual report + +//---------------------------------------------------------- +// Detection +//---------------------------------------------------------- + +@runtime_bad_err_handle exists@ +expression ret; +position p; +@@ +( +ret@p = \(pm_runtime_idle\| + pm_runtime_suspend\| + pm_runtime_autosuspend\| + pm_runtime_resume\| + pm_request_idle\| + pm_request_resume\| + pm_request_autosuspend\| + pm_runtime_get\| + pm_runtime_get_sync\| + pm_runtime_put\| + pm_runtime_put_autosuspend\| + pm_runtime_put_sync\| + pm_runtime_put_sync_suspend\| + pm_runtime_put_sync_autosuspend\| + pm_runtime_set_active\| + pm_schedule_suspend\| + pm_runtime_barrier\| + pm_generic_runtime_suspend\| + pm_generic_runtime_resume\)(...); +... +IS_ERR_VALUE(ret) +... +) + +//---------------------------------------------------------- +// For context mode +//---------------------------------------------------------- + +@depends on context@ +identifier pm_runtime_api; +expression ret; +position runtime_bad_err_handle.p; +@@ +( +ret@p = pm_runtime_api(...); +... +* IS_ERR_VALUE(ret) +... +) + +//---------------------------------------------------------- +// For patch mode +//---------------------------------------------------------- + +@depends on patch@ +identifier pm_runtime_api; +expression ret; +position runtime_bad_err_handle.p; +@@ +( +ret@p = pm_runtime_api(...); +... +- IS_ERR_VALUE(ret) ++ ret < 0 +... +) + +//---------------------------------------------------------- +// For org and report mode +//---------------------------------------------------------- + +@r depends on (org || report) exists@ +position p1, p2; +identifier pm_runtime_api; +expression ret; +position runtime_bad_err_handle.p; +@@ +( +ret@p = pm_runtime_api@p1(...); +... +IS_ERR_VALUE@p2(ret) +... +) + +@script:python depends on org@ +p1 << r.p1; +p2 << r.p2; +pm_runtime_api << r.pm_runtime_api; +@@ + +cocci.print_main(pm_runtime_api,p1) +cocci.print_secs("IS_ERR_VALUE",p2) + +@script:python depends on report@ +p1 << r.p1; +p2 << r.p2; +pm_runtime_api << r.pm_runtime_api; +@@ + +msg = "%s returns < 0 as error. Unecessary IS_ERR_VALUE at line %s" % (pm_runtime_api, p2[0].line) +coccilib.report.print_report(p1[0],msg) diff --git a/src/net/scripts/coccinelle/api/ptr_ret.cocci b/src/net/scripts/coccinelle/api/ptr_ret.cocci new file mode 100644 index 0000000..e76cd5d --- /dev/null +++ b/src/net/scripts/coccinelle/api/ptr_ret.cocci @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: GPL-2.0-only +/// +/// Use PTR_ERR_OR_ZERO rather than if(IS_ERR(...)) + PTR_ERR +/// +// Confidence: High +// Copyright: (C) 2012 Julia Lawall, INRIA/LIP6. +// Copyright: (C) 2012 Gilles Muller, INRIA/LiP6. +// URL: http://coccinelle.lip6.fr/ +// Options: --no-includes --include-headers +// +// Keywords: ERR_PTR, PTR_ERR, PTR_ERR_OR_ZERO +// Version min: 2.6.39 +// + +virtual context +virtual patch +virtual org +virtual report + +@depends on patch@ +expression ptr; +@@ + +- if (IS_ERR(ptr)) return PTR_ERR(ptr); else return 0; ++ return PTR_ERR_OR_ZERO(ptr); + +@depends on patch@ +expression ptr; +@@ + +- if (IS_ERR(ptr)) return PTR_ERR(ptr); return 0; ++ return PTR_ERR_OR_ZERO(ptr); + +@depends on patch@ +expression ptr; +@@ + +- (IS_ERR(ptr) ? PTR_ERR(ptr) : 0) ++ PTR_ERR_OR_ZERO(ptr) + +@r1 depends on !patch@ +expression ptr; +position p1; +@@ + +* if@p1 (IS_ERR(ptr)) return PTR_ERR(ptr); else return 0; + +@r2 depends on !patch@ +expression ptr; +position p2; +@@ + +* if@p2 (IS_ERR(ptr)) return PTR_ERR(ptr); return 0; + +@r3 depends on !patch@ +expression ptr; +position p3; +@@ + +* IS_ERR@p3(ptr) ? PTR_ERR(ptr) : 0 + +@script:python depends on org@ +p << r1.p1; +@@ + +coccilib.org.print_todo(p[0], "WARNING: PTR_ERR_OR_ZERO can be used") + + +@script:python depends on org@ +p << r2.p2; +@@ + +coccilib.org.print_todo(p[0], "WARNING: PTR_ERR_OR_ZERO can be used") + +@script:python depends on org@ +p << r3.p3; +@@ + +coccilib.org.print_todo(p[0], "WARNING: PTR_ERR_OR_ZERO can be used") + +@script:python depends on report@ +p << r1.p1; +@@ + +coccilib.report.print_report(p[0], "WARNING: PTR_ERR_OR_ZERO can be used") + +@script:python depends on report@ +p << r2.p2; +@@ + +coccilib.report.print_report(p[0], "WARNING: PTR_ERR_OR_ZERO can be used") + +@script:python depends on report@ +p << r3.p3; +@@ + +coccilib.report.print_report(p[0], "WARNING: PTR_ERR_OR_ZERO can be used") diff --git a/src/net/scripts/coccinelle/api/resource_size.cocci b/src/net/scripts/coccinelle/api/resource_size.cocci new file mode 100644 index 0000000..a9a571a --- /dev/null +++ b/src/net/scripts/coccinelle/api/resource_size.cocci @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: GPL-2.0-only +/// +/// Use resource_size function on resource object +/// instead of explicit computation. +/// +// Confidence: High +// Copyright: (C) 2009, 2010 Nicolas Palix, DIKU. +// Copyright: (C) 2009, 2010 Julia Lawall, DIKU. +// Copyright: (C) 2009, 2010 Gilles Muller, INRIA/LiP6. +// URL: http://coccinelle.lip6.fr/ +// Options: +// +// Keywords: resource_size +// Version min: 2.6.27 resource_size +// + +virtual context +virtual patch +virtual org +virtual report + +//---------------------------------------------------------- +// For context mode +//---------------------------------------------------------- + +@r_context depends on context && !patch && !org@ +struct resource *res; +@@ + +* (res->end - res->start) + 1 + +//---------------------------------------------------------- +// For patch mode +//---------------------------------------------------------- + +@r_patch depends on !context && patch && !org@ +struct resource *res; +@@ + +- (res->end - res->start) + 1 ++ resource_size(res) + +//---------------------------------------------------------- +// For org mode +//---------------------------------------------------------- + + +@r_org depends on !context && !patch && (org || report)@ +struct resource *res; +position p; +@@ + + (res->end@p - res->start) + 1 + +@rbad_org depends on !context && !patch && (org || report)@ +struct resource *res; +position p != r_org.p; +@@ + + res->end@p - res->start + +@script:python depends on org@ +p << r_org.p; +x << r_org.res; +@@ + +msg="ERROR with %s" % (x) +msg_safe=msg.replace("[","@(").replace("]",")") +coccilib.org.print_todo(p[0], msg_safe) + +@script:python depends on report@ +p << r_org.p; +x << r_org.res; +@@ + +msg="ERROR: Missing resource_size with %s" % (x) +coccilib.report.print_report(p[0], msg) + +@script:python depends on org@ +p << rbad_org.p; +x << rbad_org.res; +@@ + +msg="WARNING with %s" % (x) +msg_safe=msg.replace("[","@(").replace("]",")") +coccilib.org.print_todo(p[0], msg_safe) + +@script:python depends on report@ +p << rbad_org.p; +x << rbad_org.res; +@@ + +msg="WARNING: Suspicious code. resource_size is maybe missing with %s" % (x) +coccilib.report.print_report(p[0], msg) diff --git a/src/net/scripts/coccinelle/api/simple_open.cocci b/src/net/scripts/coccinelle/api/simple_open.cocci new file mode 100644 index 0000000..c121876 --- /dev/null +++ b/src/net/scripts/coccinelle/api/simple_open.cocci @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0 +/// Remove an open coded simple_open() function +/// and replace file operations references to the function +/// with simple_open() instead. +/// +// Confidence: High +// Comments: +// Options: --no-includes --include-headers + +virtual patch +virtual report + +@ open depends on patch @ +identifier open_f != simple_open; +identifier i, f; +@@ +-int open_f(struct inode *i, struct file *f) +-{ +( +-if (i->i_private) +-f->private_data = i->i_private; +| +-f->private_data = i->i_private; +) +-return 0; +-} + +@ has_open depends on open @ +identifier fops; +identifier open.open_f; +@@ +struct file_operations fops = { +..., +-.open = open_f, ++.open = simple_open, +... +}; + +@ openr depends on report @ +identifier open_f != simple_open; +identifier i, f; +position p; +@@ +int open_f@p(struct inode *i, struct file *f) +{ +( +if (i->i_private) +f->private_data = i->i_private; +| +f->private_data = i->i_private; +) +return 0; +} + +@ has_openr depends on openr @ +identifier fops; +identifier openr.open_f; +position p; +@@ +struct file_operations fops = { +..., +.open = open_f@p, +... +}; + +@script:python@ +pf << openr.p; +ps << has_openr.p; +@@ + +coccilib.report.print_report(pf[0],"WARNING opportunity for simple_open, see also structure on line %s"%(ps[0].line)) diff --git a/src/net/scripts/coccinelle/api/stream_open.cocci b/src/net/scripts/coccinelle/api/stream_open.cocci new file mode 100644 index 0000000..df00d66 --- /dev/null +++ b/src/net/scripts/coccinelle/api/stream_open.cocci @@ -0,0 +1,370 @@ +// SPDX-License-Identifier: GPL-2.0 +// Author: Kirill Smelkov (kirr@nexedi.com) +// +// Search for stream-like files that are using nonseekable_open and convert +// them to stream_open. A stream-like file is a file that does not use ppos in +// its read and write. Rationale for the conversion is to avoid deadlock in +// between read and write. + +virtual report +virtual patch +virtual explain // explain decisions in the patch (SPFLAGS="-D explain") + +// stream-like reader & writer - ones that do not depend on f_pos. +@ stream_reader @ +identifier readstream, ppos; +identifier f, buf, len; +type loff_t; +@@ + ssize_t readstream(struct file *f, char *buf, size_t len, loff_t *ppos) + { + ... when != ppos + } + +@ stream_writer @ +identifier writestream, ppos; +identifier f, buf, len; +type loff_t; +@@ + ssize_t writestream(struct file *f, const char *buf, size_t len, loff_t *ppos) + { + ... when != ppos + } + + +// a function that blocks +@ blocks @ +identifier block_f; +identifier wait =~ "^wait_.*"; +@@ + block_f(...) { + ... when exists + wait(...) + ... when exists + } + +// stream_reader that can block inside. +// +// XXX wait_* can be called not directly from current function (e.g. func -> f -> g -> wait()) +// XXX currently reader_blocks supports only direct and 1-level indirect cases. +@ reader_blocks_direct @ +identifier stream_reader.readstream; +identifier wait =~ "^wait_.*"; +@@ + readstream(...) + { + ... when exists + wait(...) + ... when exists + } + +@ reader_blocks_1 @ +identifier stream_reader.readstream; +identifier blocks.block_f; +@@ + readstream(...) + { + ... when exists + block_f(...) + ... when exists + } + +@ reader_blocks depends on reader_blocks_direct || reader_blocks_1 @ +identifier stream_reader.readstream; +@@ + readstream(...) { + ... + } + + +// file_operations + whether they have _any_ .read, .write, .llseek ... at all. +// +// XXX add support for file_operations xxx[N] = ... (sound/core/pcm_native.c) +@ fops0 @ +identifier fops; +@@ + struct file_operations fops = { + ... + }; + +@ has_read @ +identifier fops0.fops; +identifier read_f; +@@ + struct file_operations fops = { + .read = read_f, + }; + +@ has_read_iter @ +identifier fops0.fops; +identifier read_iter_f; +@@ + struct file_operations fops = { + .read_iter = read_iter_f, + }; + +@ has_write @ +identifier fops0.fops; +identifier write_f; +@@ + struct file_operations fops = { + .write = write_f, + }; + +@ has_write_iter @ +identifier fops0.fops; +identifier write_iter_f; +@@ + struct file_operations fops = { + .write_iter = write_iter_f, + }; + +@ has_llseek @ +identifier fops0.fops; +identifier llseek_f; +@@ + struct file_operations fops = { + .llseek = llseek_f, + }; + +@ has_no_llseek @ +identifier fops0.fops; +@@ + struct file_operations fops = { + .llseek = no_llseek, + }; + +@ has_noop_llseek @ +identifier fops0.fops; +@@ + struct file_operations fops = { + .llseek = noop_llseek, + }; + +@ has_mmap @ +identifier fops0.fops; +identifier mmap_f; +@@ + struct file_operations fops = { + .mmap = mmap_f, + }; + +@ has_copy_file_range @ +identifier fops0.fops; +identifier copy_file_range_f; +@@ + struct file_operations fops = { + .copy_file_range = copy_file_range_f, + }; + +@ has_remap_file_range @ +identifier fops0.fops; +identifier remap_file_range_f; +@@ + struct file_operations fops = { + .remap_file_range = remap_file_range_f, + }; + +@ has_splice_read @ +identifier fops0.fops; +identifier splice_read_f; +@@ + struct file_operations fops = { + .splice_read = splice_read_f, + }; + +@ has_splice_write @ +identifier fops0.fops; +identifier splice_write_f; +@@ + struct file_operations fops = { + .splice_write = splice_write_f, + }; + + +// file_operations that is candidate for stream_open conversion - it does not +// use mmap and other methods that assume @offset access to file. +// +// XXX for simplicity require no .{read/write}_iter and no .splice_{read/write} for now. +// XXX maybe_steam.fops cannot be used in other rules - it gives "bad rule maybe_stream or bad variable fops". +@ maybe_stream depends on (!has_llseek || has_no_llseek || has_noop_llseek) && !has_mmap && !has_copy_file_range && !has_remap_file_range && !has_read_iter && !has_write_iter && !has_splice_read && !has_splice_write @ +identifier fops0.fops; +@@ + struct file_operations fops = { + }; + + +// ---- conversions ---- + +// XXX .open = nonseekable_open -> .open = stream_open +// XXX .open = func -> openfunc -> nonseekable_open + +// read & write +// +// if both are used in the same file_operations together with an opener - +// under that conditions we can use stream_open instead of nonseekable_open. +@ fops_rw depends on maybe_stream @ +identifier fops0.fops, openfunc; +identifier stream_reader.readstream; +identifier stream_writer.writestream; +@@ + struct file_operations fops = { + .open = openfunc, + .read = readstream, + .write = writestream, + }; + +@ report_rw depends on report @ +identifier fops_rw.openfunc; +position p1; +@@ + openfunc(...) { + <... + nonseekable_open@p1 + ...> + } + +@ script:python depends on report && reader_blocks @ +fops << fops0.fops; +p << report_rw.p1; +@@ +coccilib.report.print_report(p[0], + "ERROR: %s: .read() can deadlock .write(); change nonseekable_open -> stream_open to fix." % (fops,)) + +@ script:python depends on report && !reader_blocks @ +fops << fops0.fops; +p << report_rw.p1; +@@ +coccilib.report.print_report(p[0], + "WARNING: %s: .read() and .write() have stream semantic; safe to change nonseekable_open -> stream_open." % (fops,)) + + +@ explain_rw_deadlocked depends on explain && reader_blocks @ +identifier fops_rw.openfunc; +@@ + openfunc(...) { + <... +- nonseekable_open ++ nonseekable_open /* read & write (was deadlock) */ + ...> + } + + +@ explain_rw_nodeadlock depends on explain && !reader_blocks @ +identifier fops_rw.openfunc; +@@ + openfunc(...) { + <... +- nonseekable_open ++ nonseekable_open /* read & write (no direct deadlock) */ + ...> + } + +@ patch_rw depends on patch @ +identifier fops_rw.openfunc; +@@ + openfunc(...) { + <... +- nonseekable_open ++ stream_open + ...> + } + + +// read, but not write +@ fops_r depends on maybe_stream && !has_write @ +identifier fops0.fops, openfunc; +identifier stream_reader.readstream; +@@ + struct file_operations fops = { + .open = openfunc, + .read = readstream, + }; + +@ report_r depends on report @ +identifier fops_r.openfunc; +position p1; +@@ + openfunc(...) { + <... + nonseekable_open@p1 + ...> + } + +@ script:python depends on report @ +fops << fops0.fops; +p << report_r.p1; +@@ +coccilib.report.print_report(p[0], + "WARNING: %s: .read() has stream semantic; safe to change nonseekable_open -> stream_open." % (fops,)) + +@ explain_r depends on explain @ +identifier fops_r.openfunc; +@@ + openfunc(...) { + <... +- nonseekable_open ++ nonseekable_open /* read only */ + ...> + } + +@ patch_r depends on patch @ +identifier fops_r.openfunc; +@@ + openfunc(...) { + <... +- nonseekable_open ++ stream_open + ...> + } + + +// write, but not read +@ fops_w depends on maybe_stream && !has_read @ +identifier fops0.fops, openfunc; +identifier stream_writer.writestream; +@@ + struct file_operations fops = { + .open = openfunc, + .write = writestream, + }; + +@ report_w depends on report @ +identifier fops_w.openfunc; +position p1; +@@ + openfunc(...) { + <... + nonseekable_open@p1 + ...> + } + +@ script:python depends on report @ +fops << fops0.fops; +p << report_w.p1; +@@ +coccilib.report.print_report(p[0], + "WARNING: %s: .write() has stream semantic; safe to change nonseekable_open -> stream_open." % (fops,)) + +@ explain_w depends on explain @ +identifier fops_w.openfunc; +@@ + openfunc(...) { + <... +- nonseekable_open ++ nonseekable_open /* write only */ + ...> + } + +@ patch_w depends on patch @ +identifier fops_w.openfunc; +@@ + openfunc(...) { + <... +- nonseekable_open ++ stream_open + ...> + } + + +// no read, no write - don't change anything diff --git a/src/net/scripts/coccinelle/api/vma_pages.cocci b/src/net/scripts/coccinelle/api/vma_pages.cocci new file mode 100644 index 0000000..10511b9 --- /dev/null +++ b/src/net/scripts/coccinelle/api/vma_pages.cocci @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0 +/// +/// Use vma_pages function on vma object instead of explicit computation. +/// +// Confidence: High +// Keywords: vma_pages vma +// Comment: Based on resource_size.cocci + +virtual context +virtual patch +virtual org +virtual report + +//---------------------------------------------------------- +// For context mode +//---------------------------------------------------------- + +@r_context depends on context && !patch && !org && !report@ +struct vm_area_struct *vma; +@@ + +* (vma->vm_end - vma->vm_start) >> PAGE_SHIFT + +//---------------------------------------------------------- +// For patch mode +//---------------------------------------------------------- + +@r_patch depends on !context && patch && !org && !report@ +struct vm_area_struct *vma; +@@ + +- ((vma->vm_end - vma->vm_start) >> PAGE_SHIFT) ++ vma_pages(vma) + +//---------------------------------------------------------- +// For org mode +//---------------------------------------------------------- + +@r_org depends on !context && !patch && (org || report)@ +struct vm_area_struct *vma; +position p; +@@ + + (vma->vm_end@p - vma->vm_start) >> PAGE_SHIFT + +@script:python depends on report@ +p << r_org.p; +x << r_org.vma; +@@ + +msg="WARNING: Consider using vma_pages helper on %s" % (x) +coccilib.report.print_report(p[0], msg) + +@script:python depends on org@ +p << r_org.p; +x << r_org.vma; +@@ + +msg="WARNING: Consider using vma_pages helper on %s" % (x) +msg_safe=msg.replace("[","@(").replace("]",")") +coccilib.org.print_todo(p[0], msg_safe) diff --git a/src/net/scripts/coccinelle/free/clk_put.cocci b/src/net/scripts/coccinelle/free/clk_put.cocci new file mode 100644 index 0000000..7237b49 --- /dev/null +++ b/src/net/scripts/coccinelle/free/clk_put.cocci @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: GPL-2.0-only +/// Find missing clk_puts. +/// +//# This only signals a missing clk_put when there is a clk_put later +//# in the same function. +//# False positives can be due to loops. +// +// Confidence: Moderate +// Copyright: (C) 2012 Julia Lawall, INRIA/LIP6. +// Copyright: (C) 2012 Gilles Muller, INRIA/LiP6. +// URL: http://coccinelle.lip6.fr/ +// Comments: +// Options: + +virtual context +virtual org +virtual report + +@clk@ +expression e; +statement S,S1; +int ret; +position p1,p2,p3; +@@ + +e = clk_get@p1(...) +... when != clk_put(e) +if (<+...e...+>) S +... when any + when != clk_put(e) + when != if (...) { ... clk_put(e); ... } +( + if (ret == 0) S1 +| +if (...) + { ... + return 0; } +| +if (...) + { ... + return <+...e...+>; } +| +*if@p2 (...) + { ... when != clk_put(e) + when forall + return@p3 ...; } +) +... when any +clk_put(e); + +@script:python depends on org@ +p1 << clk.p1; +p2 << clk.p2; +p3 << clk.p3; +@@ + +cocci.print_main("clk_get",p1) +cocci.print_secs("if",p2) +cocci.print_secs("needed clk_put",p3) + +@script:python depends on report@ +p1 << clk.p1; +p2 << clk.p2; +p3 << clk.p3; +@@ + +msg = "ERROR: missing clk_put; clk_get on line %s and execution via conditional on line %s" % (p1[0].line,p2[0].line) +coccilib.report.print_report(p3[0],msg) diff --git a/src/net/scripts/coccinelle/free/devm_free.cocci b/src/net/scripts/coccinelle/free/devm_free.cocci new file mode 100644 index 0000000..da80050 --- /dev/null +++ b/src/net/scripts/coccinelle/free/devm_free.cocci @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: GPL-2.0-only +/// Find uses of standard freeing functons on values allocated using devm_ +/// functions. Values allocated using the devm_functions are freed when +/// the device is detached, and thus the use of the standard freeing +/// function would cause a double free. +/// See Documentation/driver-api/driver-model/devres.rst for more information. +/// +/// A difficulty of detecting this problem is that the standard freeing +/// function might be called from a different function than the one +/// containing the allocation function. It is thus necessary to make the +/// connection between the allocation function and the freeing function. +/// Here this is done using the specific argument text, which is prone to +/// false positives. There is no rule for the request_region and +/// request_mem_region variants because this heuristic seems to be a bit +/// less reliable in these cases. +/// +// Confidence: Moderate +// Copyright: (C) 2011 Julia Lawall, INRIA/LIP6. +// Copyright: (C) 2011 Gilles Muller, INRIA/LiP6. +// URL: http://coccinelle.lip6.fr/ +// Comments: +// Options: --no-includes --include-headers + +virtual org +virtual report +virtual context + +@r depends on context || org || report@ +expression x; +@@ + +( + x = devm_kmalloc(...) +| + x = devm_kvasprintf(...) +| + x = devm_kasprintf(...) +| + x = devm_kzalloc(...) +| + x = devm_kmalloc_array(...) +| + x = devm_kcalloc(...) +| + x = devm_kstrdup(...) +| + x = devm_kmemdup(...) +| + x = devm_get_free_pages(...) +| + x = devm_request_irq(...) +| + x = devm_ioremap(...) +| + x = devm_ioport_map(...) +) + +@safe depends on context || org || report exists@ +expression x; +position p; +@@ + +( + x = kmalloc(...) +| + x = kvasprintf(...) +| + x = kasprintf(...) +| + x = kzalloc(...) +| + x = kmalloc_array(...) +| + x = kcalloc(...) +| + x = kstrdup(...) +| + x = kmemdup(...) +| + x = get_free_pages(...) +| + x = request_irq(...) +| + x = ioremap(...) +| + x = ioport_map(...) +) +... +( + kfree@p(x) +| + kfree_sensitive@p(x) +| + krealloc@p(x, ...) +| + free_pages@p(x, ...) +| + free_page@p(x) +| + free_irq@p(x) +| + iounmap@p(x) +| + ioport_unmap@p(x) +) + +@pb@ +expression r.x; +position p != safe.p; +@@ + +( +* kfree@p(x) +| +* kfree_sensitive@p(x) +| +* krealloc@p(x, ...) +| +* free_pages@p(x, ...) +| +* free_page@p(x) +| +* free_irq@p(x) +| +* iounmap@p(x) +| +* ioport_unmap@p(x) +) + +@script:python depends on org@ +p << pb.p; +@@ + +msg="WARNING: invalid free of devm_ allocated data" +coccilib.org.print_todo(p[0], msg) + +@script:python depends on report@ +p << pb.p; +@@ + +msg="WARNING: invalid free of devm_ allocated data" +coccilib.report.print_report(p[0], msg) + diff --git a/src/net/scripts/coccinelle/free/ifnullfree.cocci b/src/net/scripts/coccinelle/free/ifnullfree.cocci new file mode 100644 index 0000000..285b92d --- /dev/null +++ b/src/net/scripts/coccinelle/free/ifnullfree.cocci @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0-only +/// NULL check before some freeing functions is not needed. +/// +/// Based on checkpatch warning +/// "kfree(NULL) is safe this check is probably not required" +/// and kfreeaddr.cocci by Julia Lawall. +/// +// Copyright: (C) 2014 Fabian Frederick. +// Comments: - +// Options: --no-includes --include-headers + +virtual patch +virtual org +virtual report +virtual context + +@r2 depends on patch@ +expression E; +@@ +- if (E != NULL) +( + kfree(E); +| + kvfree(E); +| + kfree_sensitive(E); +| + kvfree_sensitive(E, ...); +| + vfree(E); +| + debugfs_remove(E); +| + debugfs_remove_recursive(E); +| + usb_free_urb(E); +| + kmem_cache_destroy(E); +| + mempool_destroy(E); +| + dma_pool_destroy(E); +) + +@r depends on context || report || org @ +expression E; +position p; +@@ + +* if (E != NULL) +* \(kfree@p\|kvfree@p\|kfree_sensitive@p\|kvfree_sensitive@p\|vfree@p\| +* debugfs_remove@p\|debugfs_remove_recursive@p\| +* usb_free_urb@p\|kmem_cache_destroy@p\|mempool_destroy@p\| +* dma_pool_destroy@p\)(E, ...); + +@script:python depends on org@ +p << r.p; +@@ + +cocci.print_main("NULL check before that freeing function is not needed", p) + +@script:python depends on report@ +p << r.p; +@@ + +msg = "WARNING: NULL check before some freeing functions is not needed." +coccilib.report.print_report(p[0], msg) diff --git a/src/net/scripts/coccinelle/free/iounmap.cocci b/src/net/scripts/coccinelle/free/iounmap.cocci new file mode 100644 index 0000000..63b81d0 --- /dev/null +++ b/src/net/scripts/coccinelle/free/iounmap.cocci @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: GPL-2.0-only +/// Find missing iounmaps. +/// +//# This only signals a missing iounmap when there is an iounmap later +//# in the same function. +//# False positives can be due to loops. +// +// Confidence: Moderate +// Copyright: (C) 2012 Julia Lawall, INRIA/LIP6. +// Copyright: (C) 2012 Gilles Muller, INRIA/LiP6. +// URL: http://coccinelle.lip6.fr/ +// Comments: +// Options: + +virtual context +virtual org +virtual report + +@iom@ +expression e; +statement S,S1; +int ret; +position p1,p2,p3; +@@ + +e = \(ioremap@p1\)(...) +... when != iounmap(e) +if (<+...e...+>) S +... when any + when != iounmap(e) + when != if (...) { ... iounmap(e); ... } +( + if (ret == 0) S1 +| +if (...) + { ... + return 0; } +| +if (...) + { ... + return <+...e...+>; } +| +*if@p2 (...) + { ... when != iounmap(e) + when forall + return@p3 ...; } +) +... when any +iounmap(e); + +@script:python depends on org@ +p1 << iom.p1; +p2 << iom.p2; +p3 << iom.p3; +@@ + +cocci.print_main("ioremap",p1) +cocci.print_secs("if",p2) +cocci.print_secs("needed iounmap",p3) + +@script:python depends on report@ +p1 << iom.p1; +p2 << iom.p2; +p3 << iom.p3; +@@ + +msg = "ERROR: missing iounmap; ioremap on line %s and execution via conditional on line %s" % (p1[0].line,p2[0].line) +coccilib.report.print_report(p3[0],msg) diff --git a/src/net/scripts/coccinelle/free/kfree.cocci b/src/net/scripts/coccinelle/free/kfree.cocci new file mode 100644 index 0000000..1685683 --- /dev/null +++ b/src/net/scripts/coccinelle/free/kfree.cocci @@ -0,0 +1,134 @@ +// SPDX-License-Identifier: GPL-2.0-only +/// Find a use after free. +//# Values of variables may imply that some +//# execution paths are not possible, resulting in false positives. +//# Another source of false positives are macros such as +//# SCTP_DBG_OBJCNT_DEC that do not actually evaluate their argument +/// +// Confidence: Moderate +// Copyright: (C) 2010-2012 Nicolas Palix. +// Copyright: (C) 2010-2012 Julia Lawall, INRIA/LIP6. +// Copyright: (C) 2010-2012 Gilles Muller, INRIA/LiP6. +// URL: http://coccinelle.lip6.fr/ +// Comments: +// Options: --no-includes --include-headers + +virtual org +virtual report + +@free@ +expression E; +position p1; +@@ + +( +* kfree@p1(E) +| +* kfree_sensitive@p1(E) +) + +@print expression@ +constant char [] c; +expression free.E,E2; +type T; +position p; +identifier f; +@@ + +( + f(...,c,...,(T)E@p,...) +| + E@p == E2 +| + E@p != E2 +| + E2 == E@p +| + E2 != E@p +| + !E@p +| + E@p || ... +) + +@sz@ +expression free.E; +position p; +@@ + + sizeof(<+...E@p...+>) + +@loop exists@ +expression E; +identifier l; +position ok; +@@ + +while (1) { ... +( +* kfree@ok(E) +| +* kfree_sensitive@ok(E) +) + ... when != break; + when != goto l; + when forall +} + +@r exists@ +expression free.E, subE<=free.E, E2; +expression E1; +iterator iter; +statement S; +position free.p1!=loop.ok,p2!={print.p,sz.p}; +@@ + +( +* kfree@p1(E,...) +| +* kfree_sensitive@p1(E,...) +) +... +( + iter(...,subE,...) S // no use +| + list_remove_head(E1,subE,...) +| + subE = E2 +| + subE++ +| + ++subE +| + --subE +| + subE-- +| + &subE +| + BUG(...) +| + BUG_ON(...) +| + return_VALUE(...) +| + return_ACPI_STATUS(...) +| + E@p2 // bad use +) + +@script:python depends on org@ +p1 << free.p1; +p2 << r.p2; +@@ + +cocci.print_main("kfree",p1) +cocci.print_secs("ref",p2) + +@script:python depends on report@ +p1 << free.p1; +p2 << r.p2; +@@ + +msg = "ERROR: reference preceded by free on line %s" % (p1[0].line) +coccilib.report.print_report(p2[0],msg) diff --git a/src/net/scripts/coccinelle/free/kfreeaddr.cocci b/src/net/scripts/coccinelle/free/kfreeaddr.cocci new file mode 100644 index 0000000..142af63 --- /dev/null +++ b/src/net/scripts/coccinelle/free/kfreeaddr.cocci @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0-only +/// Free of a structure field +/// +// Confidence: High +// Copyright: (C) 2013 Julia Lawall, INRIA/LIP6. +// URL: http://coccinelle.lip6.fr/ +// Comments: +// Options: --no-includes --include-headers + +virtual org +virtual report +virtual context + +@r depends on context || report || org @ +expression e; +identifier f; +position p; +@@ + +( +* kfree@p(&e->f) +| +* kfree_sensitive@p(&e->f) +) + +@script:python depends on org@ +p << r.p; +@@ + +cocci.print_main("kfree",p) + +@script:python depends on report@ +p << r.p; +@@ + +msg = "ERROR: invalid free of structure field" +coccilib.report.print_report(p[0],msg) diff --git a/src/net/scripts/coccinelle/free/pci_free_consistent.cocci b/src/net/scripts/coccinelle/free/pci_free_consistent.cocci new file mode 100644 index 0000000..d51e925 --- /dev/null +++ b/src/net/scripts/coccinelle/free/pci_free_consistent.cocci @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0-only +/// Find missing pci_free_consistent for every pci_alloc_consistent. +/// +// Confidence: Moderate +// Copyright: (C) 2013 Petr Strnad. +// URL: http://coccinelle.lip6.fr/ +// Keywords: pci_free_consistent, pci_alloc_consistent +// Options: --no-includes --include-headers + +virtual report +virtual org + +@search@ +local idexpression id; +expression x,y,z,e; +position p1,p2; +type T; +@@ + +id = pci_alloc_consistent@p1(x,y,&z) +... when != e = id +if (id == NULL || ...) { ... return ...; } +... when != pci_free_consistent(x,y,id,z) + when != if (id) { ... pci_free_consistent(x,y,id,z) ... } + when != if (y) { ... pci_free_consistent(x,y,id,z) ... } + when != e = (T)id + when exists +( +return 0; +| +return 1; +| +return id; +| +return@p2 ...; +) + +@script:python depends on report@ +p1 << search.p1; +p2 << search.p2; +@@ + +msg = "ERROR: missing pci_free_consistent; pci_alloc_consistent on line %s and return without freeing on line %s" % (p1[0].line,p2[0].line) +coccilib.report.print_report(p2[0],msg) + +@script:python depends on org@ +p1 << search.p1; +p2 << search.p2; +@@ + +msg = "ERROR: missing pci_free_consistent; pci_alloc_consistent on line %s and return without freeing on line %s" % (p1[0].line,p2[0].line) +cocci.print_main(msg,p1) +cocci.print_secs("",p2) diff --git a/src/net/scripts/coccinelle/free/put_device.cocci b/src/net/scripts/coccinelle/free/put_device.cocci new file mode 100644 index 0000000..1209213 --- /dev/null +++ b/src/net/scripts/coccinelle/free/put_device.cocci @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0 +/// Find missing put_device for every of_find_device_by_node. +/// +// Confidence: Moderate +// Copyright: (C) 2018-2019 Wen Yang, ZTE. +// Comments: +// Options: --no-includes --include-headers + +virtual report +virtual org + +@search exists@ +local idexpression id; +expression x,e,e1; +position p1,p2; +type T,T1,T2,T3; +@@ + +id = of_find_device_by_node@p1(x) +... when != e = id +if (id == NULL || ...) { ... return ...; } +... when != put_device(&id->dev) + when != platform_device_put(id) + when != of_dev_put(id) + when != if (id) { ... put_device(&id->dev) ... } + when != e1 = (T)id + when != e1 = (T)(&id->dev) + when != e1 = get_device(&id->dev) + when != e1 = (T1)platform_get_drvdata(id) +( + return +( id +| (T2)dev_get_drvdata(&id->dev) +| (T3)platform_get_drvdata(id) +| &id->dev +); +| return@p2 ...; +) + +@script:python depends on report@ +p1 << search.p1; +p2 << search.p2; +@@ + +coccilib.report.print_report(p2[0], + "ERROR: missing put_device; call of_find_device_by_node on line " + + p1[0].line + + ", but without a corresponding object release within this function.") + +@script:python depends on org@ +p1 << search.p1; +p2 << search.p2; +@@ + +cocci.print_main("of_find_device_by_node", p1) +cocci.print_secs("needed put_device", p2) diff --git a/src/net/scripts/coccinelle/iterators/device_node_continue.cocci b/src/net/scripts/coccinelle/iterators/device_node_continue.cocci new file mode 100644 index 0000000..f8cd14d --- /dev/null +++ b/src/net/scripts/coccinelle/iterators/device_node_continue.cocci @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: GPL-2.0-only +/// Device node iterators put the previous value of the index variable, so an +/// explicit put causes a double put. +/// +// Confidence: High +// Copyright: (C) 2015 Julia Lawall, Inria. +// URL: http://coccinelle.lip6.fr/ +// Options: --no-includes --include-headers +// Requires: 1.0.4 +// Keywords: for_each_child_of_node, etc. + +// This uses a conjunction, which requires at least coccinelle >= 1.0.4 + +virtual patch +virtual context +virtual org +virtual report + +@r exists@ +expression e1,e2; +local idexpression n; +iterator name for_each_node_by_name, for_each_node_by_type, +for_each_compatible_node, for_each_matching_node, +for_each_matching_node_and_match, for_each_child_of_node, +for_each_available_child_of_node, for_each_node_with_property; +iterator i; +position p1,p2; +statement S; +@@ + +( +( +for_each_node_by_name(n,e1) S +| +for_each_node_by_type(n,e1) S +| +for_each_compatible_node(n,e1,e2) S +| +for_each_matching_node(n,e1) S +| +for_each_matching_node_and_match(n,e1,e2) S +| +for_each_child_of_node(e1,n) S +| +for_each_available_child_of_node(e1,n) S +| +for_each_node_with_property(n,e1) S +) +& +i@p1(...) { + ... when != of_node_get(n) + when any + of_node_put@p2(n); + ... when any +} +) + +@s exists@ +local idexpression r.n; +statement S; +position r.p1,r.p2; +iterator i; +@@ + + of_node_put@p2(n); + ... when any + i@p1(..., n, ...) + S + +@t depends on s && patch && !context && !org && !report@ +local idexpression n; +position r.p2; +@@ + +- of_node_put@p2(n); + +// ---------------------------------------------------------------------------- + +@t_context depends on s && !patch && (context || org || report)@ +local idexpression n; +position r.p2; +position j0; +@@ + +* of_node_put@j0@p2(n); + +// ---------------------------------------------------------------------------- + +@script:python t_org depends on org@ +j0 << t_context.j0; +@@ + +msg = "ERROR: probable double put." +coccilib.org.print_todo(j0[0], msg) + +// ---------------------------------------------------------------------------- + +@script:python t_report depends on report@ +j0 << t_context.j0; +@@ + +msg = "ERROR: probable double put." +coccilib.report.print_report(j0[0], msg) + diff --git a/src/net/scripts/coccinelle/iterators/fen.cocci b/src/net/scripts/coccinelle/iterators/fen.cocci new file mode 100644 index 0000000..b69f966 --- /dev/null +++ b/src/net/scripts/coccinelle/iterators/fen.cocci @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: GPL-2.0-only +/// These iterators only exit normally when the loop cursor is NULL, so there +/// is no point to call of_node_put on the final value. +/// +// Confidence: High +// Copyright: (C) 2010-2012 Nicolas Palix. +// Copyright: (C) 2010-2012 Julia Lawall, INRIA/LIP6. +// Copyright: (C) 2010-2012 Gilles Muller, INRIA/LiP6. +// URL: http://coccinelle.lip6.fr/ +// Comments: +// Options: --no-includes --include-headers + +virtual patch +virtual context +virtual org +virtual report + +@depends on patch@ +iterator name for_each_node_by_name; +expression np,E; +identifier l; +@@ + +for_each_node_by_name(np,...) { + ... when != break; + when != goto l; +} +... when != np = E +- of_node_put(np); + +@depends on patch@ +iterator name for_each_node_by_type; +expression np,E; +identifier l; +@@ + +for_each_node_by_type(np,...) { + ... when != break; + when != goto l; +} +... when != np = E +- of_node_put(np); + +@depends on patch@ +iterator name for_each_compatible_node; +expression np,E; +identifier l; +@@ + +for_each_compatible_node(np,...) { + ... when != break; + when != goto l; +} +... when != np = E +- of_node_put(np); + +@depends on patch@ +iterator name for_each_matching_node; +expression np,E; +identifier l; +@@ + +for_each_matching_node(np,...) { + ... when != break; + when != goto l; +} +... when != np = E +- of_node_put(np); + +// ---------------------------------------------------------------------- + +@r depends on !patch forall@ +//iterator name for_each_node_by_name; +//iterator name for_each_node_by_type; +//iterator name for_each_compatible_node; +//iterator name for_each_matching_node; +expression np,E; +identifier l; +position p1,p2; +@@ + +( +*for_each_node_by_name@p1(np,...) +{ + ... when != break; + when != goto l; +} +| +*for_each_node_by_type@p1(np,...) +{ + ... when != break; + when != goto l; +} +| +*for_each_compatible_node@p1(np,...) +{ + ... when != break; + when != goto l; +} +| +*for_each_matching_node@p1(np,...) +{ + ... when != break; + when != goto l; +} +) +... when != np = E +* of_node_put@p2(np); + +@script:python depends on org@ +p1 << r.p1; +p2 << r.p2; +@@ + +cocci.print_main("unneeded of_node_put",p2) +cocci.print_secs("iterator",p1) + +@script:python depends on report@ +p1 << r.p1; +p2 << r.p2; +@@ + +msg = "ERROR: of_node_put not needed after iterator on line %s" % (p1[0].line) +coccilib.report.print_report(p2[0], msg) diff --git a/src/net/scripts/coccinelle/iterators/for_each_child.cocci b/src/net/scripts/coccinelle/iterators/for_each_child.cocci new file mode 100644 index 0000000..bc39461 --- /dev/null +++ b/src/net/scripts/coccinelle/iterators/for_each_child.cocci @@ -0,0 +1,358 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Adds missing of_node_put() before return/break/goto statement within a for_each iterator for child nodes. +//# False positives can be due to function calls within the for_each +//# loop that may encapsulate an of_node_put. +/// +// Confidence: High +// Copyright: (C) 2020 Sumera Priyadarsini +// URL: http://coccinelle.lip6.fr +// Options: --no-includes --include-headers + +virtual patch +virtual context +virtual org +virtual report + +@r@ +local idexpression n; +expression e1,e2; +iterator name for_each_node_by_name, for_each_node_by_type, +for_each_compatible_node, for_each_matching_node, +for_each_matching_node_and_match, for_each_child_of_node, +for_each_available_child_of_node, for_each_node_with_property; +iterator i; +statement S; +expression list [n1] es; +@@ + +( +( +for_each_node_by_name(n,e1) S +| +for_each_node_by_type(n,e1) S +| +for_each_compatible_node(n,e1,e2) S +| +for_each_matching_node(n,e1) S +| +for_each_matching_node_and_match(n,e1,e2) S +| +for_each_child_of_node(e1,n) S +| +for_each_available_child_of_node(e1,n) S +| +for_each_node_with_property(n,e1) S +) +& +i(es,n,...) S +) + +@ruleone depends on patch && !context && !org && !report@ + +local idexpression r.n; +iterator r.i,i1; +expression e; +expression list [r.n1] es; +statement S; +@@ + + i(es,n,...) { + ... +( + of_node_put(n); +| + e = n +| + return n; +| + i1(...,n,...) S +| +- return of_node_get(n); ++ return n; +| ++ of_node_put(n); +? return ...; +) + ... when any + } + +@ruletwo depends on patch && !context && !org && !report@ + +local idexpression r.n; +iterator r.i,i1,i2; +expression e,e1; +expression list [r.n1] es; +statement S,S2; +@@ + + i(es,n,...) { + ... +( + of_node_put(n); +| + e = n +| + i1(...,n,...) S +| ++ of_node_put(n); +? break; +) + ... when any + } +... when != n + when strict + when forall +( + n = e1; +| +?i2(...,n,...) S2 +) + +@rulethree depends on patch && !context && !org && !report exists@ + +local idexpression r.n; +iterator r.i,i1,i2; +expression e,e1; +identifier l; +expression list [r.n1] es; +statement S,S2; +@@ + + i(es,n,...) { + ... +( + of_node_put(n); +| + e = n +| + i1(...,n,...) S +| ++ of_node_put(n); +? goto l; +) + ... when any + } +... when exists +l: ... when != n + when strict + when forall +( + n = e1; +| +?i2(...,n,...) S2 +) + +// ---------------------------------------------------------------------------- + +@ruleone_context depends on !patch && (context || org || report) exists@ +statement S; +expression e; +expression list[r.n1] es; +iterator r.i, i1; +local idexpression r.n; +position j0, j1; +@@ + + i@j0(es,n,...) { + ... +( + of_node_put(n); +| + e = n +| + return n; +| + i1(...,n,...) S +| + return @j1 ...; +) + ... when any + } + +@ruleone_disj depends on !patch && (context || org || report)@ +expression list[r.n1] es; +iterator r.i; +local idexpression r.n; +position ruleone_context.j0, ruleone_context.j1; +@@ + +* i@j0(es,n,...) { + ... +*return @j1...; + ... when any + } + +@ruletwo_context depends on !patch && (context || org || report) exists@ +statement S, S2; +expression e, e1; +expression list[r.n1] es; +iterator r.i, i1, i2; +local idexpression r.n; +position j0, j2; +@@ + + i@j0(es,n,...) { + ... +( + of_node_put(n); +| + e = n +| + i1(...,n,...) S +| + break@j2; +) + ... when any + } +... when != n + when strict + when forall +( + n = e1; +| +?i2(...,n,...) S2 +) + +@ruletwo_disj depends on !patch && (context || org || report)@ +statement S2; +expression e1; +expression list[r.n1] es; +iterator r.i, i2; +local idexpression r.n; +position ruletwo_context.j0, ruletwo_context.j2; +@@ + +* i@j0(es,n,...) { + ... +*break @j2; + ... when any + } +... when != n + when strict + when forall +( + n = e1; +| +?i2(...,n,...) S2 +) + +@rulethree_context depends on !patch && (context || org || report) exists@ +identifier l; +statement S,S2; +expression e, e1; +expression list[r.n1] es; +iterator r.i, i1, i2; +local idexpression r.n; +position j0, j3; +@@ + + i@j0(es,n,...) { + ... +( + of_node_put(n); +| + e = n +| + i1(...,n,...) S +| + goto l@j3; +) + ... when any + } +... when exists +l: +... when != n + when strict + when forall +( + n = e1; +| +?i2(...,n,...) S2 +) + +@rulethree_disj depends on !patch && (context || org || report) exists@ +identifier l; +statement S2; +expression e1; +expression list[r.n1] es; +iterator r.i, i2; +local idexpression r.n; +position rulethree_context.j0, rulethree_context.j3; +@@ + +* i@j0(es,n,...) { + ... +*goto l@j3; + ... when any + } +... when exists + l: + ... when != n + when strict + when forall +( + n = e1; +| +?i2(...,n,...) S2 +) + +// ---------------------------------------------------------------------------- + +@script:python ruleone_org depends on org@ +i << r.i; +j0 << ruleone_context.j0; +j1 << ruleone_context. j1; +@@ + +msg = "WARNING: Function \"%s\" should have of_node_put() before return " % (i) +coccilib.org.print_safe_todo(j0[0], msg) +coccilib.org.print_link(j1[0], "") + +@script:python ruletwo_org depends on org@ +i << r.i; +j0 << ruletwo_context.j0; +j2 << ruletwo_context.j2; +@@ + +msg = "WARNING: Function \"%s\" should have of_node_put() before break " % (i) +coccilib.org.print_safe_todo(j0[0], msg) +coccilib.org.print_link(j2[0], "") + +@script:python rulethree_org depends on org@ +i << r.i; +j0 << rulethree_context.j0; +j3 << rulethree_context.j3; +@@ + +msg = "WARNING: Function \"%s\" should have of_node_put() before goto " % (i) +coccilib.org.print_safe_todo(j0[0], msg) +coccilib.org.print_link(j3[0], "") + +// ---------------------------------------------------------------------------- + +@script:python ruleone_report depends on report@ +i << r.i; +j0 << ruleone_context.j0; +j1 << ruleone_context.j1; +@@ + +msg = "WARNING: Function \"%s\" should have of_node_put() before return around line %s." % (i, j1[0].line) +coccilib.report.print_report(j0[0], msg) + +@script:python ruletwo_report depends on report@ +i << r.i; +j0 << ruletwo_context.j0; +j2 << ruletwo_context.j2; +@@ + +msg = "WARNING: Function \"%s\" should have of_node_put() before break around line %s." % (i,j2[0].line) +coccilib.report.print_report(j0[0], msg) + +@script:python rulethree_report depends on report@ +i << r.i; +j0 << rulethree_context.j0; +j3 << rulethree_context.j3; +@@ + +msg = "WARNING: Function \"%s\" should have of_node_put() before goto around lines %s." % (i,j3[0].line) +coccilib.report.print_report(j0[0], msg) diff --git a/src/net/scripts/coccinelle/iterators/itnull.cocci b/src/net/scripts/coccinelle/iterators/itnull.cocci new file mode 100644 index 0000000..9b362b9 --- /dev/null +++ b/src/net/scripts/coccinelle/iterators/itnull.cocci @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: GPL-2.0-only +/// Many iterators have the property that the first argument is always bound +/// to a real list element, never NULL. +//# False positives arise for some iterators that do not have this property, +//# or in cases when the loop cursor is reassigned. The latter should only +//# happen when the matched code is on the way to a loop exit (break, goto, +//# or return). +/// +// Confidence: Moderate +// Copyright: (C) 2010-2012 Nicolas Palix. +// Copyright: (C) 2010-2012 Julia Lawall, INRIA/LIP6. +// Copyright: (C) 2010-2012 Gilles Muller, INRIA/LiP6. +// URL: http://coccinelle.lip6.fr/ +// Comments: +// Options: --no-includes --include-headers + +virtual patch +virtual context +virtual org +virtual report + +@depends on patch@ +iterator I; +expression x,E,E1,E2; +statement S,S1,S2; +@@ + +I(x,...) { <... +( +- if (x == NULL && ...) S +| +- if (x != NULL || ...) + S +| +- (x == NULL) || + E +| +- (x != NULL) && + E +| +- (x == NULL && ...) ? E1 : + E2 +| +- (x != NULL || ...) ? + E1 +- : E2 +| +- if (x == NULL && ...) S1 else + S2 +| +- if (x != NULL || ...) + S1 +- else S2 +| ++ BAD( + x == NULL ++ ) +| ++ BAD( + x != NULL ++ ) +) + ...> } + +@r depends on !patch exists@ +iterator I; +expression x,E; +position p1,p2; +@@ + +*I@p1(x,...) +{ ... when != x = E +( +* x@p2 == NULL +| +* x@p2 != NULL +) + ... when any +} + +@script:python depends on org@ +p1 << r.p1; +p2 << r.p2; +@@ + +cocci.print_main("iterator-bound variable",p1) +cocci.print_secs("useless NULL test",p2) + +@script:python depends on report@ +p1 << r.p1; +p2 << r.p2; +@@ + +msg = "ERROR: iterator variable bound on line %s cannot be NULL" % (p1[0].line) +coccilib.report.print_report(p2[0], msg) diff --git a/src/net/scripts/coccinelle/iterators/list_entry_update.cocci b/src/net/scripts/coccinelle/iterators/list_entry_update.cocci new file mode 100644 index 0000000..d62e8a1 --- /dev/null +++ b/src/net/scripts/coccinelle/iterators/list_entry_update.cocci @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0-only +/// list_for_each_entry uses its first argument to get from one element of +/// the list to the next, so it is usually not a good idea to reassign it. +/// The first rule finds such a reassignment and the second rule checks +/// that there is a path from the reassignment back to the top of the loop. +/// +// Confidence: High +// Copyright: (C) 2010 Nicolas Palix, DIKU. +// Copyright: (C) 2010 Julia Lawall, DIKU. +// Copyright: (C) 2010 Gilles Muller, INRIA/LiP6. +// URL: http://coccinelle.lip6.fr/ +// Comments: +// Options: --no-includes --include-headers + +virtual context +virtual org +virtual report + +@r exists@ +iterator name list_for_each_entry; +expression x,E; +position p1,p2; +@@ + +list_for_each_entry@p1(x,...) { <... x =@p2 E ...> } + +@depends on context && !org && !report@ +expression x,E; +position r.p1,r.p2; +statement S; +@@ + +*x =@p2 E +... +list_for_each_entry@p1(x,...) S + +// ------------------------------------------------------------------------ + +@back depends on (org || report) && !context exists@ +expression x,E; +position r.p1,r.p2; +statement S; +@@ + +x =@p2 E +... +list_for_each_entry@p1(x,...) S + +@script:python depends on back && org@ +p1 << r.p1; +p2 << r.p2; +@@ + +cocci.print_main("iterator",p1) +cocci.print_secs("update",p2) + +@script:python depends on back && report@ +p1 << r.p1; +p2 << r.p2; +@@ + +msg = "iterator with update on line %s" % (p2[0].line) +coccilib.report.print_report(p1[0],msg) diff --git a/src/net/scripts/coccinelle/iterators/use_after_iter.cocci b/src/net/scripts/coccinelle/iterators/use_after_iter.cocci new file mode 100644 index 0000000..9be48b5 --- /dev/null +++ b/src/net/scripts/coccinelle/iterators/use_after_iter.cocci @@ -0,0 +1,151 @@ +// SPDX-License-Identifier: GPL-2.0-only +/// If list_for_each_entry, etc complete a traversal of the list, the iterator +/// variable ends up pointing to an address at an offset from the list head, +/// and not a meaningful structure. Thus this value should not be used after +/// the end of the iterator. +//#False positives arise when there is a goto in the iterator and the +//#reported reference is at the label of this goto. Some flag tests +//#may also cause a report to be a false positive. +/// +// Confidence: Moderate +// Copyright: (C) 2012 Julia Lawall, INRIA/LIP6. +// Copyright: (C) 2012 Gilles Muller, INRIA/LIP6. +// URL: http://coccinelle.lip6.fr/ +// Comments: +// Options: --no-includes --include-headers + +virtual context +virtual org +virtual report + +@r exists@ +identifier c,member; +expression E,x; +iterator name list_for_each_entry; +iterator name list_for_each_entry_reverse; +iterator name list_for_each_entry_continue; +iterator name list_for_each_entry_continue_reverse; +iterator name list_for_each_entry_from; +iterator name list_for_each_entry_safe; +iterator name list_for_each_entry_safe_continue; +iterator name list_for_each_entry_safe_from; +iterator name list_for_each_entry_safe_reverse; +iterator name hlist_for_each_entry; +iterator name hlist_for_each_entry_continue; +iterator name hlist_for_each_entry_from; +iterator name hlist_for_each_entry_safe; +statement S; +position p1,p2; +type T; +@@ + +( +list_for_each_entry@p1(c,...,member) { ... when != break; + when forall + when strict +} +| +list_for_each_entry_reverse@p1(c,...,member) { ... when != break; + when forall + when strict +} +| +list_for_each_entry_continue@p1(c,...,member) { ... when != break; + when forall + when strict +} +| +list_for_each_entry_continue_reverse@p1(c,...,member) { ... when != break; + when forall + when strict +} +| +list_for_each_entry_from@p1(c,...,member) { ... when != break; + when forall + when strict +} +| +list_for_each_entry_safe@p1(c,...,member) { ... when != break; + when forall + when strict +} +| +list_for_each_entry_safe_continue@p1(c,...,member) { ... when != break; + when forall + when strict +} +| +list_for_each_entry_safe_from@p1(c,...,member) { ... when != break; + when forall + when strict +} +| +list_for_each_entry_safe_reverse@p1(c,...,member) { ... when != break; + when forall + when strict +} +) +... +( +list_for_each_entry(c,...) S +| +list_for_each_entry_reverse(c,...) S +| +list_for_each_entry_continue(c,...) S +| +list_for_each_entry_continue_reverse(c,...) S +| +list_for_each_entry_from(c,...) S +| +list_for_each_entry_safe(c,...) S +| +list_for_each_entry_safe(x,c,...) S +| +list_for_each_entry_safe_continue(c,...) S +| +list_for_each_entry_safe_continue(x,c,...) S +| +list_for_each_entry_safe_from(c,...) S +| +list_for_each_entry_safe_from(x,c,...) S +| +list_for_each_entry_safe_reverse(c,...) S +| +list_for_each_entry_safe_reverse(x,c,...) S +| +hlist_for_each_entry(c,...) S +| +hlist_for_each_entry_continue(c,...) S +| +hlist_for_each_entry_from(c,...) S +| +hlist_for_each_entry_safe(c,...) S +| +list_remove_head(x,c,...) +| +sizeof(<+...c...+>) +| + &c->member +| +T c; +| +c = E +| +*c@p2 +) + +@script:python depends on org@ +p1 << r.p1; +p2 << r.p2; +@@ + +cocci.print_main("invalid iterator index reference",p2) +cocci.print_secs("iterator",p1) + +@script:python depends on report@ +p1 << r.p1; +p2 << r.p2; +@@ + +msg = "ERROR: invalid reference to the index variable of the iterator on line %s" % (p1[0].line) +coccilib.report.print_report(p2[0], msg) diff --git a/src/net/scripts/coccinelle/locks/call_kern.cocci b/src/net/scripts/coccinelle/locks/call_kern.cocci new file mode 100644 index 0000000..5ca0d81 --- /dev/null +++ b/src/net/scripts/coccinelle/locks/call_kern.cocci @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: GPL-2.0-only +/// Find functions that refer to GFP_KERNEL but are called with locks held. +//# The proposed change of converting the GFP_KERNEL is not necessarily the +//# correct one. It may be desired to unlock the lock, or to not call the +//# function under the lock in the first place. +/// +// Confidence: Moderate +// Copyright: (C) 2012 Nicolas Palix. +// Copyright: (C) 2012 Julia Lawall, INRIA/LIP6. +// Copyright: (C) 2012 Gilles Muller, INRIA/LiP6. +// URL: http://coccinelle.lip6.fr/ +// Comments: +// Options: --no-includes --include-headers + +virtual patch +virtual context +virtual org +virtual report + +@gfp exists@ +identifier fn; +position p; +@@ + +fn(...) { + ... when != read_unlock_irq(...) + when != write_unlock_irq(...) + when != read_unlock_irqrestore(...) + when != write_unlock_irqrestore(...) + when != spin_unlock(...) + when != spin_unlock_irq(...) + when != spin_unlock_irqrestore(...) + when != local_irq_enable(...) + when any + GFP_KERNEL@p + ... when any +} + +@locked exists@ +identifier gfp.fn; +position p1,p2; +@@ + +( +read_lock_irq@p1 +| +write_lock_irq@p1 +| +read_lock_irqsave@p1 +| +write_lock_irqsave@p1 +| +spin_lock@p1 +| +spin_trylock@p1 +| +spin_lock_irq@p1 +| +spin_lock_irqsave@p1 +| +local_irq_disable@p1 +) + (...) +... when != read_unlock_irq(...) + when != write_unlock_irq(...) + when != read_unlock_irqrestore(...) + when != write_unlock_irqrestore(...) + when != spin_unlock(...) + when != spin_unlock_irq(...) + when != spin_unlock_irqrestore(...) + when != local_irq_enable(...) +fn@p2(...) + +@depends on locked && patch@ +position gfp.p; +@@ + +- GFP_KERNEL@p ++ GFP_ATOMIC + +@depends on locked && !patch@ +position gfp.p; +@@ + +* GFP_KERNEL@p + +@script:python depends on !patch && org@ +p << gfp.p; +fn << gfp.fn; +p1 << locked.p1; +p2 << locked.p2; +@@ + +cocci.print_main("lock",p1) +cocci.print_secs("call",p2) +cocci.print_secs("GFP_KERNEL",p) + +@script:python depends on !patch && report@ +p << gfp.p; +fn << gfp.fn; +p1 << locked.p1; +p2 << locked.p2; +@@ + +msg = "ERROR: function %s called on line %s inside lock on line %s but uses GFP_KERNEL" % (fn,p2[0].line,p1[0].line) +coccilib.report.print_report(p[0], msg) diff --git a/src/net/scripts/coccinelle/locks/double_lock.cocci b/src/net/scripts/coccinelle/locks/double_lock.cocci new file mode 100644 index 0000000..9e88a57 --- /dev/null +++ b/src/net/scripts/coccinelle/locks/double_lock.cocci @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: GPL-2.0-only +/// Find double locks. False positives may occur when some paths cannot +/// occur at execution, due to the values of variables, and when there is +/// an intervening function call that releases the lock. +/// +// Confidence: Moderate +// Copyright: (C) 2010 Nicolas Palix, DIKU. +// Copyright: (C) 2010 Julia Lawall, DIKU. +// Copyright: (C) 2010 Gilles Muller, INRIA/LiP6. +// URL: http://coccinelle.lip6.fr/ +// Comments: +// Options: --no-includes --include-headers + +virtual org +virtual report + +@locked@ +position p1; +expression E1; +position p; +@@ + +( +mutex_lock@p1 +| +mutex_trylock@p1 +| +spin_lock@p1 +| +spin_trylock@p1 +| +read_lock@p1 +| +read_trylock@p1 +| +write_lock@p1 +| +write_trylock@p1 +) (E1@p,...); + +@balanced@ +position p1 != locked.p1; +position locked.p; +identifier lock,unlock; +expression x <= locked.E1; +expression E,locked.E1; +expression E2; +@@ + +if (E) { + <+... when != E1 + lock(E1@p,...) + ...+> +} +... when != E1 + when != \(x = E2\|&x\) + when forall +if (E) { + <+... when != E1 + unlock@p1(E1,...) + ...+> +} + +@r depends on !balanced exists@ +expression x <= locked.E1; +expression locked.E1; +expression E2; +identifier lock; +position locked.p,p1,p2; +@@ + +lock@p1 (E1@p,...); +... when != E1 + when != \(x = E2\|&x\) +lock@p2 (E1,...); + +@script:python depends on org@ +p1 << r.p1; +p2 << r.p2; +lock << r.lock; +@@ + +cocci.print_main(lock,p1) +cocci.print_secs("second lock",p2) + +@script:python depends on report@ +p1 << r.p1; +p2 << r.p2; +lock << r.lock; +@@ + +msg = "second lock on line %s" % (p2[0].line) +coccilib.report.print_report(p1[0],msg) diff --git a/src/net/scripts/coccinelle/locks/flags.cocci b/src/net/scripts/coccinelle/locks/flags.cocci new file mode 100644 index 0000000..7f990cd --- /dev/null +++ b/src/net/scripts/coccinelle/locks/flags.cocci @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0-only +/// Find nested lock+irqsave functions that use the same flags variables +/// +// Confidence: High +// Copyright: (C) 2010-2012 Nicolas Palix. +// Copyright: (C) 2010-2012 Julia Lawall, INRIA/LIP6. +// Copyright: (C) 2010-2012 Gilles Muller, INRIA/LiP6. +// URL: http://coccinelle.lip6.fr/ +// Comments: +// Options: --no-includes --include-headers + +virtual context +virtual org +virtual report + +@r exists@ +expression lock1,lock2,flags; +position p1,p2; +@@ + +( +spin_lock_irqsave@p1(lock1,flags) +| +read_lock_irqsave@p1(lock1,flags) +| +write_lock_irqsave@p1(lock1,flags) +) +... when != flags +( +spin_lock_irqsave(lock1,flags) +| +read_lock_irqsave(lock1,flags) +| +write_lock_irqsave(lock1,flags) +| +spin_lock_irqsave@p2(lock2,flags) +| +read_lock_irqsave@p2(lock2,flags) +| +write_lock_irqsave@p2(lock2,flags) +) + +@d exists@ +expression f <= r.flags; +expression lock1,lock2,flags; +position r.p1, r.p2; +@@ + +( +*spin_lock_irqsave@p1(lock1,flags) +| +*read_lock_irqsave@p1(lock1,flags) +| +*write_lock_irqsave@p1(lock1,flags) +) +... when != f +( +*spin_lock_irqsave@p2(lock2,flags) +| +*read_lock_irqsave@p2(lock2,flags) +| +*write_lock_irqsave@p2(lock2,flags) +) + +// ---------------------------------------------------------------------- + +@script:python depends on d && org@ +p1 << r.p1; +p2 << r.p2; +@@ + +cocci.print_main("original lock",p1) +cocci.print_secs("nested lock+irqsave that reuses flags",p2) + +@script:python depends on d && report@ +p1 << r.p1; +p2 << r.p2; +@@ + +msg="ERROR: nested lock+irqsave that reuses flags from line %s." % (p1[0].line) +coccilib.report.print_report(p2[0], msg) diff --git a/src/net/scripts/coccinelle/locks/mini_lock.cocci b/src/net/scripts/coccinelle/locks/mini_lock.cocci new file mode 100644 index 0000000..c3ad098 --- /dev/null +++ b/src/net/scripts/coccinelle/locks/mini_lock.cocci @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0-only +/// Find missing unlocks. This semantic match considers the specific case +/// where the unlock is missing from an if branch, and there is a lock +/// before the if and an unlock after the if. False positives are due to +/// cases where the if branch represents a case where the function is +/// supposed to exit with the lock held, or where there is some preceding +/// function call that releases the lock. +/// +// Confidence: Moderate +// Copyright: (C) 2010-2012 Nicolas Palix. +// Copyright: (C) 2010-2012 Julia Lawall, INRIA/LIP6. +// Copyright: (C) 2010-2012 Gilles Muller, INRIA/LiP6. +// URL: http://coccinelle.lip6.fr/ +// Comments: +// Options: --no-includes --include-headers + +virtual context +virtual org +virtual report + +@prelocked@ +position p1,p; +expression E1; +@@ + +( +mutex_lock@p1 +| +mutex_trylock@p1 +| +spin_lock@p1 +| +spin_trylock@p1 +| +read_lock@p1 +| +read_trylock@p1 +| +write_lock@p1 +| +write_trylock@p1 +| +read_lock_irq@p1 +| +write_lock_irq@p1 +| +read_lock_irqsave@p1 +| +write_lock_irqsave@p1 +| +spin_lock_irq@p1 +| +spin_lock_irqsave@p1 +) (E1@p,...); + +@looped@ +position r; +@@ + +for(...;...;...) { <+... return@r ...; ...+> } + +@err exists@ +expression E1; +position prelocked.p; +position up != prelocked.p1; +position r!=looped.r; +identifier lock,unlock; +@@ + +*lock(E1@p,...); +... when != E1 + when any +if (...) { + ... when != E1 +* return@r ...; +} +... when != E1 + when any +*unlock@up(E1,...); + +@script:python depends on org@ +p << prelocked.p1; +lock << err.lock; +unlock << err.unlock; +p2 << err.r; +@@ + +cocci.print_main(lock,p) +cocci.print_secs(unlock,p2) + +@script:python depends on report@ +p << prelocked.p1; +lock << err.lock; +unlock << err.unlock; +p2 << err.r; +@@ + +msg = "preceding lock on line %s" % (p[0].line) +coccilib.report.print_report(p2[0],msg) diff --git a/src/net/scripts/coccinelle/misc/add_namespace.cocci b/src/net/scripts/coccinelle/misc/add_namespace.cocci new file mode 100644 index 0000000..cbf1614 --- /dev/null +++ b/src/net/scripts/coccinelle/misc/add_namespace.cocci @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0-only +// +/// Adds missing MODULE_IMPORT_NS statements to source files +/// +/// This script is usually called from scripts/nsdeps with -D ns=<namespace> to +/// add a missing namespace tag to a module source file. +/// + +virtual nsdeps +virtual report + +@has_ns_import@ +declarer name MODULE_IMPORT_NS; +identifier virtual.ns; +@@ +MODULE_IMPORT_NS(ns); + +// Add missing imports, but only adjacent to a MODULE_LICENSE statement. +// That ensures we are adding it only to the main module source file. +@do_import depends on !has_ns_import && nsdeps@ +declarer name MODULE_LICENSE; +expression license; +identifier virtual.ns; +@@ +MODULE_LICENSE(license); ++ MODULE_IMPORT_NS(ns); + +// Dummy rule for report mode that would otherwise be empty and make spatch +// fail ("No rules apply.") +@script:python depends on report@ +@@ diff --git a/src/net/scripts/coccinelle/misc/array_size.cocci b/src/net/scripts/coccinelle/misc/array_size.cocci new file mode 100644 index 0000000..4d25187 --- /dev/null +++ b/src/net/scripts/coccinelle/misc/array_size.cocci @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0-only +/// Use ARRAY_SIZE instead of dividing sizeof array with sizeof an element +/// +//# This makes an effort to find cases where ARRAY_SIZE can be used such as +//# where there is a division of sizeof the array by the sizeof its first +//# element or by any indexed element or the element type. It replaces the +//# division of the two sizeofs by ARRAY_SIZE. +// +// Confidence: High +// Copyright: (C) 2014 Himangi Saraogi. +// Comments: +// Options: --no-includes --include-headers + +virtual patch +virtual context +virtual org +virtual report + +@i@ +@@ + +#include <linux/kernel.h> + +//---------------------------------------------------------- +// For context mode +//---------------------------------------------------------- + +@depends on i&&context@ +type T; +T[] E; +@@ +( +* (sizeof(E)/sizeof(*E)) +| +* (sizeof(E)/sizeof(E[...])) +| +* (sizeof(E)/sizeof(T)) +) + +//---------------------------------------------------------- +// For patch mode +//---------------------------------------------------------- + +@depends on i&&patch@ +type T; +T[] E; +@@ +( +- (sizeof(E)/sizeof(*E)) ++ ARRAY_SIZE(E) +| +- (sizeof(E)/sizeof(E[...])) ++ ARRAY_SIZE(E) +| +- (sizeof(E)/sizeof(T)) ++ ARRAY_SIZE(E) +) + +//---------------------------------------------------------- +// For org and report mode +//---------------------------------------------------------- + +@r depends on (org || report)@ +type T; +T[] E; +position p; +@@ +( + (sizeof(E)@p /sizeof(*E)) +| + (sizeof(E)@p /sizeof(E[...])) +| + (sizeof(E)@p /sizeof(T)) +) + +@script:python depends on org@ +p << r.p; +@@ + +coccilib.org.print_todo(p[0], "WARNING should use ARRAY_SIZE") + +@script:python depends on report@ +p << r.p; +@@ + +msg="WARNING: Use ARRAY_SIZE" +coccilib.report.print_report(p[0], msg) + diff --git a/src/net/scripts/coccinelle/misc/array_size_dup.cocci b/src/net/scripts/coccinelle/misc/array_size_dup.cocci new file mode 100644 index 0000000..fbc2ba1 --- /dev/null +++ b/src/net/scripts/coccinelle/misc/array_size_dup.cocci @@ -0,0 +1,209 @@ +// SPDX-License-Identifier: GPL-2.0-only +/// +/// Check for array_size(), array3_size(), struct_size() duplicates. +/// These patterns are detected: +/// 1. An opencoded expression is used before array_size() to compute the same size +/// 2. An opencoded expression is used after array_size() to compute the same size +/// From security point of view only first case is relevant. These functions +/// perform arithmetic overflow check. Thus, if we use an opencoded expression +/// before a call to the *_size() function we can miss an overflow. +/// +// Confidence: High +// Copyright: (C) 2020 Denis Efremov ISPRAS +// Options: --no-includes --include-headers --no-loops + +virtual context +virtual report +virtual org + +@as@ +expression E1, E2; +@@ + +array_size(E1, E2) + +@as_next@ +expression subE1 <= as.E1; +expression subE2 <= as.E2; +expression as.E1, as.E2, E3; +assignment operator aop; +position p1, p2; +@@ + +* E1 * E2@p1 + ... when != \(subE1\|subE2\) aop E3 + when != &\(subE1\|subE2\) +* array_size(E1, E2)@p2 + +@script:python depends on report@ +p1 << as_next.p1; +p2 << as_next.p2; +@@ + +msg = "WARNING: array_size is used later (line %s) to compute the same size" % (p2[0].line) +coccilib.report.print_report(p1[0], msg) + +@script:python depends on org@ +p1 << as_next.p1; +p2 << as_next.p2; +@@ + +msg = "WARNING: array_size is used later (line %s) to compute the same size" % (p2[0].line) +coccilib.org.print_todo(p1[0], msg) + +@as_prev@ +expression subE1 <= as.E1; +expression subE2 <= as.E2; +expression as.E1, as.E2, E3; +assignment operator aop; +position p1, p2; +@@ + +* array_size(E1, E2)@p1 + ... when != \(subE1\|subE2\) aop E3 + when != &\(subE1\|subE2\) +* E1 * E2@p2 + +@script:python depends on report@ +p1 << as_prev.p1; +p2 << as_prev.p2; +@@ + +msg = "WARNING: array_size is already used (line %s) to compute the same size" % (p1[0].line) +coccilib.report.print_report(p2[0], msg) + +@script:python depends on org@ +p1 << as_prev.p1; +p2 << as_prev.p2; +@@ + +msg = "WARNING: array_size is already used (line %s) to compute the same size" % (p1[0].line) +coccilib.org.print_todo(p2[0], msg) + +@as3@ +expression E1, E2, E3; +@@ + +array3_size(E1, E2, E3) + +@as3_next@ +expression subE1 <= as3.E1; +expression subE2 <= as3.E2; +expression subE3 <= as3.E3; +expression as3.E1, as3.E2, as3.E3, E4; +assignment operator aop; +position p1, p2; +@@ + +* E1 * E2 * E3@p1 + ... when != \(subE1\|subE2\|subE3\) aop E4 + when != &\(subE1\|subE2\|subE3\) +* array3_size(E1, E2, E3)@p2 + +@script:python depends on report@ +p1 << as3_next.p1; +p2 << as3_next.p2; +@@ + +msg = "WARNING: array3_size is used later (line %s) to compute the same size" % (p2[0].line) +coccilib.report.print_report(p1[0], msg) + +@script:python depends on org@ +p1 << as3_next.p1; +p2 << as3_next.p2; +@@ + +msg = "WARNING: array3_size is used later (line %s) to compute the same size" % (p2[0].line) +coccilib.org.print_todo(p1[0], msg) + +@as3_prev@ +expression subE1 <= as3.E1; +expression subE2 <= as3.E2; +expression subE3 <= as3.E3; +expression as3.E1, as3.E2, as3.E3, E4; +assignment operator aop; +position p1, p2; +@@ + +* array3_size(E1, E2, E3)@p1 + ... when != \(subE1\|subE2\|subE3\) aop E4 + when != &\(subE1\|subE2\|subE3\) +* E1 * E2 * E3@p2 + +@script:python depends on report@ +p1 << as3_prev.p1; +p2 << as3_prev.p2; +@@ + +msg = "WARNING: array3_size is already used (line %s) to compute the same size" % (p1[0].line) +coccilib.report.print_report(p2[0], msg) + +@script:python depends on org@ +p1 << as3_prev.p1; +p2 << as3_prev.p2; +@@ + +msg = "WARNING: array3_size is already used (line %s) to compute the same size" % (p1[0].line) +coccilib.org.print_todo(p2[0], msg) + +@ss@ +expression E1, E2, E3; +@@ + +struct_size(E1, E2, E3) + +@ss_next@ +expression subE3 <= ss.E3; +expression ss.E1, ss.E2, ss.E3, E4; +assignment operator aop; +position p1, p2; +@@ + +* E1 * E2 + E3@p1 + ... when != subE3 aop E4 + when != &subE3 +* struct_size(E1, E2, E3)@p2 + +@script:python depends on report@ +p1 << ss_next.p1; +p2 << ss_next.p2; +@@ + +msg = "WARNING: struct_size is used later (line %s) to compute the same size" % (p2[0].line) +coccilib.report.print_report(p1[0], msg) + +@script:python depends on org@ +p1 << ss_next.p1; +p2 << ss_next.p2; +@@ + +msg = "WARNING: struct_size is used later (line %s) to compute the same size" % (p2[0].line) +coccilib.org.print_todo(p1[0], msg) + +@ss_prev@ +expression subE3 <= ss.E3; +expression ss.E1, ss.E2, ss.E3, E4; +assignment operator aop; +position p1, p2; +@@ + +* struct_size(E1, E2, E3)@p1 + ... when != subE3 aop E4 + when != &subE3 +* E1 * E2 + E3@p2 + +@script:python depends on report@ +p1 << ss_prev.p1; +p2 << ss_prev.p2; +@@ + +msg = "WARNING: struct_size is already used (line %s) to compute the same size" % (p1[0].line) +coccilib.report.print_report(p2[0], msg) + +@script:python depends on org@ +p1 << ss_prev.p1; +p2 << ss_prev.p2; +@@ + +msg = "WARNING: struct_size is already used (line %s) to compute the same size" % (p1[0].line) +coccilib.org.print_todo(p2[0], msg) diff --git a/src/net/scripts/coccinelle/misc/badty.cocci b/src/net/scripts/coccinelle/misc/badty.cocci new file mode 100644 index 0000000..ed3e0b8 --- /dev/null +++ b/src/net/scripts/coccinelle/misc/badty.cocci @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0-only +/// Correct the size argument to alloc functions +/// +//# This makes an effort to find cases where the argument to sizeof is wrong +//# in memory allocation functions by checking the type of the allocated memory +//# when it is a double pointer and ensuring the sizeof argument takes a pointer +//# to the the memory being allocated. There are false positives in cases the +//# sizeof argument is not used in constructing the return value. The result +//# may need some reformatting. +// +// Confidence: Moderate +// Copyright: (C) 2014 Himangi Saraogi. +// Comments: +// Options: + +virtual patch +virtual context +virtual org +virtual report + +//---------------------------------------------------------- +// For context mode +//---------------------------------------------------------- + +@depends on context disable sizeof_type_expr@ +type T; +T **x; +@@ + + x = + <+...sizeof( +* T + )...+> + +//---------------------------------------------------------- +// For patch mode +//---------------------------------------------------------- + +@depends on patch disable sizeof_type_expr@ +type T; +T **x; +@@ + + x = + <+...sizeof( +- T ++ *x + )...+> + +//---------------------------------------------------------- +// For org and report mode +//---------------------------------------------------------- + +@r depends on (org || report) disable sizeof_type_expr@ +type T; +T **x; +position p; +@@ + + x = + <+...sizeof( + T@p + )...+> + +@script:python depends on org@ +p << r.p; +@@ + +coccilib.org.print_todo(p[0], "WARNING sizeof argument should be pointer type, not structure type") + +@script:python depends on report@ +p << r.p; +@@ + +msg="WARNING: Use correct pointer type argument for sizeof" +coccilib.report.print_report(p[0], msg) + diff --git a/src/net/scripts/coccinelle/misc/boolconv.cocci b/src/net/scripts/coccinelle/misc/boolconv.cocci new file mode 100644 index 0000000..392994e --- /dev/null +++ b/src/net/scripts/coccinelle/misc/boolconv.cocci @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: GPL-2.0-only +/// Remove unneeded conversion to bool +/// +//# Relational and logical operators evaluate to bool, +//# explicit conversion is overly verbose and unneeded. +// +// Copyright: (C) 2016 Andrew F. Davis <afd@ti.com> + +virtual patch +virtual context +virtual org +virtual report + +//---------------------------------------------------------- +// For patch mode +//---------------------------------------------------------- + +@depends on patch@ +expression A, B; +symbol true, false; +@@ + +( + A == B +| + A != B +| + A > B +| + A < B +| + A >= B +| + A <= B +| + A && B +| + A || B +) +- ? true : false + +//---------------------------------------------------------- +// For context mode +//---------------------------------------------------------- + +@r depends on !patch@ +expression A, B; +symbol true, false; +position p; +@@ + +( + A == B +| + A != B +| + A > B +| + A < B +| + A >= B +| + A <= B +| + A && B +| + A || B +) +* ? true : false@p + +//---------------------------------------------------------- +// For org mode +//---------------------------------------------------------- + +@script:python depends on r&&org@ +p << r.p; +@@ + +msg = "WARNING: conversion to bool not needed here" +coccilib.org.print_todo(p[0], msg) + +//---------------------------------------------------------- +// For report mode +//---------------------------------------------------------- + +@script:python depends on r&&report@ +p << r.p; +@@ + +msg = "WARNING: conversion to bool not needed here" +coccilib.report.print_report(p[0], msg) diff --git a/src/net/scripts/coccinelle/misc/boolinit.cocci b/src/net/scripts/coccinelle/misc/boolinit.cocci new file mode 100644 index 0000000..fed6126 --- /dev/null +++ b/src/net/scripts/coccinelle/misc/boolinit.cocci @@ -0,0 +1,195 @@ +// SPDX-License-Identifier: GPL-2.0-only +/// Bool initializations should use true and false. Bool tests don't need +/// comparisons. Based on contributions from Joe Perches, Rusty Russell +/// and Bruce W Allan. +/// +// Confidence: High +// Copyright: (C) 2012 Julia Lawall, INRIA/LIP6. +// Copyright: (C) 2012 Gilles Muller, INRIA/LiP6. +// URL: http://coccinelle.lip6.fr/ +// Options: --include-headers + +virtual patch +virtual context +virtual org +virtual report + +@boolok@ +symbol true,false; +@@ +( +true +| +false +) + +@depends on patch@ +bool t; +@@ + +( +- t == true ++ t +| +- true == t ++ t +| +- t != true ++ !t +| +- true != t ++ !t +| +- t == false ++ !t +| +- false == t ++ !t +| +- t != false ++ t +| +- false != t ++ t +) + +@depends on patch disable is_zero, isnt_zero@ +bool t; +@@ + +( +- t == 1 ++ t +| +- t != 1 ++ !t +| +- t == 0 ++ !t +| +- t != 0 ++ t +) + +@depends on patch && boolok@ +bool b; +@@ +( + b = +- 0 ++ false +| + b = +- 1 ++ true +) + +// --------------------------------------------------------------------- + +@r1 depends on !patch@ +bool t; +position p; +@@ + +( +* t@p == true +| +* true == t@p +| +* t@p != true +| +* true != t@p +| +* t@p == false +| +* false == t@p +| +* t@p != false +| +* false != t@p +) + +@r2 depends on !patch disable is_zero, isnt_zero@ +bool t; +position p; +@@ + +( +* t@p == 1 +| +* t@p != 1 +| +* t@p == 0 +| +* t@p != 0 +) + +@r3 depends on !patch && boolok@ +bool b; +position p1; +@@ +( +*b@p1 = 0 +| +*b@p1 = 1 +) + +@r4 depends on !patch@ +bool b; +position p2; +identifier i; +constant c != {0,1}; +@@ +( + b = i +| +*b@p2 = c +) + +@script:python depends on org@ +p << r1.p; +@@ + +cocci.print_main("WARNING: Comparison to bool",p) + +@script:python depends on org@ +p << r2.p; +@@ + +cocci.print_main("WARNING: Comparison of 0/1 to bool variable",p) + +@script:python depends on org@ +p1 << r3.p1; +@@ + +cocci.print_main("WARNING: Assignment of 0/1 to bool variable",p1) + +@script:python depends on org@ +p2 << r4.p2; +@@ + +cocci.print_main("ERROR: Assignment of non-0/1 constant to bool variable",p2) + +@script:python depends on report@ +p << r1.p; +@@ + +coccilib.report.print_report(p[0],"WARNING: Comparison to bool") + +@script:python depends on report@ +p << r2.p; +@@ + +coccilib.report.print_report(p[0],"WARNING: Comparison of 0/1 to bool variable") + +@script:python depends on report@ +p1 << r3.p1; +@@ + +coccilib.report.print_report(p1[0],"WARNING: Assignment of 0/1 to bool variable") + +@script:python depends on report@ +p2 << r4.p2; +@@ + +coccilib.report.print_report(p2[0],"ERROR: Assignment of non-0/1 constant to bool variable") diff --git a/src/net/scripts/coccinelle/misc/boolreturn.cocci b/src/net/scripts/coccinelle/misc/boolreturn.cocci new file mode 100644 index 0000000..29d2bf4 --- /dev/null +++ b/src/net/scripts/coccinelle/misc/boolreturn.cocci @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0 +/// Return statements in functions returning bool should use +/// true/false instead of 1/0. +// +// Confidence: High +// Options: --no-includes --include-headers + +virtual patch +virtual report +virtual context + +@r1 depends on patch@ +identifier fn; +typedef bool; +symbol false; +symbol true; +@@ + +bool fn ( ... ) +{ +<... +return +( +- 0 ++ false +| +- 1 ++ true +) + ; +...> +} + +@r2 depends on report || context@ +identifier fn; +position p; +@@ + +bool fn ( ... ) +{ +<... +return +( +* 0@p +| +* 1@p +) + ; +...> +} + + +@script:python depends on report@ +p << r2.p; +fn << r2.fn; +@@ + +msg = "WARNING: return of 0/1 in function '%s' with return type bool" % fn +coccilib.report.print_report(p[0], msg) diff --git a/src/net/scripts/coccinelle/misc/bugon.cocci b/src/net/scripts/coccinelle/misc/bugon.cocci new file mode 100644 index 0000000..8d595c3 --- /dev/null +++ b/src/net/scripts/coccinelle/misc/bugon.cocci @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0-only +/// Use BUG_ON instead of a if condition followed by BUG. +/// +//# This makes an effort to find cases where BUG() follows an if +//# condition on an expression and replaces the if condition and BUG() +//# with a BUG_ON having the conditional expression of the if statement +//# as argument. +// +// Confidence: High +// Copyright: (C) 2014 Himangi Saraogi. +// Comments: +// Options: --no-includes --include-headers + +virtual patch +virtual context +virtual org +virtual report + +//---------------------------------------------------------- +// For context mode +//---------------------------------------------------------- + +@depends on context@ +expression e; +@@ + +*if (e) BUG(); + +//---------------------------------------------------------- +// For patch mode +//---------------------------------------------------------- + +@depends on patch@ +expression e; +@@ + +-if (e) BUG(); ++BUG_ON(e); + +//---------------------------------------------------------- +// For org and report mode +//---------------------------------------------------------- + +@r depends on (org || report)@ +expression e; +position p; +@@ + + if (e) BUG@p (); + +@script:python depends on org@ +p << r.p; +@@ + +coccilib.org.print_todo(p[0], "WARNING use BUG_ON") + +@script:python depends on report@ +p << r.p; +@@ + +msg="WARNING: Use BUG_ON instead of if condition followed by BUG.\nPlease make sure the condition has no side effects (see conditional BUG_ON definition in include/asm-generic/bug.h)" +coccilib.report.print_report(p[0], msg) + diff --git a/src/net/scripts/coccinelle/misc/cond_no_effect.cocci b/src/net/scripts/coccinelle/misc/cond_no_effect.cocci new file mode 100644 index 0000000..91d16a8 --- /dev/null +++ b/src/net/scripts/coccinelle/misc/cond_no_effect.cocci @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: GPL-2.0-only +///Find conditions where if and else branch are functionally +// identical. +// +// There can be false positives in cases where the positional +// information is used (as with lockdep) or where the identity +// is a placeholder for not yet handled cases. +// Unfortunately there also seems to be a tendency to use +// the last if else/else as a "default behavior" - which some +// might consider a legitimate coding pattern. From discussion +// on kernelnewbies though it seems that this is not really an +// accepted pattern and if at all it would need to be commented +// +// In the Linux kernel it does not seem to actually report +// false positives except for those that were documented as +// being intentional. +// the two known cases are: +// arch/sh/kernel/traps_64.c:read_opcode() +// } else if ((pc & 1) == 0) { +// /* SHcompact */ +// /* TODO : provide handling for this. We don't really support +// user-mode SHcompact yet, and for a kernel fault, this would +// have to come from a module built for SHcompact. */ +// return -EFAULT; +// } else { +// /* misaligned */ +// return -EFAULT; +// } +// fs/kernfs/file.c:kernfs_fop_open() +// * Both paths of the branch look the same. They're supposed to +// * look that way and give @of->mutex different static lockdep keys. +// */ +// if (has_mmap) +// mutex_init(&of->mutex); +// else +// mutex_init(&of->mutex); +// +// All other cases look like bugs or at least lack of documentation +// +// Confidence: Moderate +// Copyright: (C) 2016 Nicholas Mc Guire, OSADL. +// Comments: +// Options: --no-includes --include-headers + +virtual org +virtual report + +@cond@ +statement S1; +position p; +@@ + +* if@p (...) S1 else S1 + +@script:python depends on org@ +p << cond.p; +@@ + +cocci.print_main("WARNING: possible condition with no effect (if == else)",p) + +@script:python depends on report@ +p << cond.p; +@@ + +coccilib.report.print_report(p[0],"WARNING: possible condition with no effect (if == else)") diff --git a/src/net/scripts/coccinelle/misc/cstptr.cocci b/src/net/scripts/coccinelle/misc/cstptr.cocci new file mode 100644 index 0000000..c52e3c8 --- /dev/null +++ b/src/net/scripts/coccinelle/misc/cstptr.cocci @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0-only +/// PTR_ERR should be applied before its argument is reassigned, typically +/// to NULL +/// +// Confidence: High +// Copyright: (C) 2012 Julia Lawall, INRIA/LIP6. +// Copyright: (C) 2012 Gilles Muller, INRIA/LiP6. +// URL: http://coccinelle.lip6.fr/ +// Comments: +// Options: --no-includes --include-headers + +virtual org +virtual report +virtual context + +@r exists@ +expression e,e1; +constant c; +position p1,p2; +@@ + +*e@p1 = c +... when != e = e1 + when != &e + when != true IS_ERR(e) +*PTR_ERR@p2(e) + +@script:python depends on org@ +p1 << r.p1; +p2 << r.p2; +@@ + +cocci.print_main("PTR_ERR",p2) +cocci.print_secs("assignment",p1) + +@script:python depends on report@ +p1 << r.p1; +p2 << r.p2; +@@ + +msg = "ERROR: PTR_ERR applied after initialization to constant on line %s" % (p1[0].line) +coccilib.report.print_report(p2[0],msg) diff --git a/src/net/scripts/coccinelle/misc/doubleinit.cocci b/src/net/scripts/coccinelle/misc/doubleinit.cocci new file mode 100644 index 0000000..2f80d3a --- /dev/null +++ b/src/net/scripts/coccinelle/misc/doubleinit.cocci @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0-only +/// Find duplicate field initializations. This has a high rate of false +/// positives due to #ifdefs, which Coccinelle is not aware of in a structure +/// initialization. +/// +// Confidence: Low +// Copyright: (C) 2010-2012 Nicolas Palix. +// Copyright: (C) 2010-2012 Julia Lawall, INRIA/LIP6. +// Copyright: (C) 2010-2012 Gilles Muller, INRIA/LiP6. +// URL: http://coccinelle.lip6.fr/ +// Comments: requires at least Coccinelle 0.2.4, lex or parse error otherwise +// Options: --no-includes --include-headers + +virtual org +virtual report + +@r@ +identifier I, s, fld; +position p0,p; +expression E; +@@ + +struct I s =@p0 { ..., .fld@p = E, ...}; + +@s@ +identifier I, s, r.fld; +position r.p0,p; +expression E; +@@ + +struct I s =@p0 { ..., .fld@p = E, ...}; + +@script:python depends on org@ +p0 << r.p0; +fld << r.fld; +ps << s.p; +pr << r.p; +@@ + +if int(ps[0].line) < int(pr[0].line) or (int(ps[0].line) == int(pr[0].line) and int(ps[0].column) < int(pr[0].column)): + cocci.print_main(fld,p0) + cocci.print_secs("s",ps) + cocci.print_secs("r",pr) + +@script:python depends on report@ +p0 << r.p0; +fld << r.fld; +ps << s.p; +pr << r.p; +@@ + +if int(ps[0].line) < int(pr[0].line) or (int(ps[0].line) == int(pr[0].line) and int(ps[0].column) < int(pr[0].column)): + msg = "%s: first occurrence line %s, second occurrence line %s" % (fld,ps[0].line,pr[0].line) + coccilib.report.print_report(p0[0],msg) diff --git a/src/net/scripts/coccinelle/misc/excluded_middle.cocci b/src/net/scripts/coccinelle/misc/excluded_middle.cocci new file mode 100644 index 0000000..ab28393 --- /dev/null +++ b/src/net/scripts/coccinelle/misc/excluded_middle.cocci @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0-only +/// +/// Condition !A || A && B is equivalent to !A || B. +/// +// Confidence: High +// Copyright: (C) 2020 Denis Efremov ISPRAS +// Options: --no-includes --include-headers + +virtual patch +virtual context +virtual org +virtual report + +@r depends on !patch@ +expression A, B; +position p; +@@ + +* !A || (A &&@p B) + +@depends on patch@ +expression A, B; +@@ + + !A || +- (A && B) ++ B + +@script:python depends on report@ +p << r.p; +@@ + +coccilib.report.print_report(p[0], "WARNING !A || A && B is equivalent to !A || B") + +@script:python depends on org@ +p << r.p; +@@ + +coccilib.org.print_todo(p[0], "WARNING !A || A && B is equivalent to !A || B") diff --git a/src/net/scripts/coccinelle/misc/flexible_array.cocci b/src/net/scripts/coccinelle/misc/flexible_array.cocci new file mode 100644 index 0000000..947fbaf --- /dev/null +++ b/src/net/scripts/coccinelle/misc/flexible_array.cocci @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0-only +/// +/// Zero-length and one-element arrays are deprecated, see +/// Documentation/process/deprecated.rst +/// Flexible-array members should be used instead. +/// +// +// Confidence: High +// Copyright: (C) 2020 Denis Efremov ISPRAS. +// Comments: +// Options: --no-includes --include-headers + +virtual context +virtual report +virtual org +virtual patch + +@initialize:python@ +@@ +def relevant(positions): + for p in positions: + if "uapi" in p.file: + return False + return True + +@r depends on !patch@ +identifier name, array; +type T; +position p : script:python() { relevant(p) }; +@@ + +( + struct name { + ... +* T array@p[\(0\|1\)]; + }; +| + struct { + ... +* T array@p[\(0\|1\)]; + }; +| + union name { + ... +* T array@p[\(0\|1\)]; + }; +| + union { + ... +* T array@p[\(0\|1\)]; + }; +) + +@depends on patch@ +identifier name, array; +type T; +position p : script:python() { relevant(p) }; +@@ + +( + struct name { + ... + T array@p[ +- 0 + ]; + }; +| + struct { + ... + T array@p[ +- 0 + ]; + }; +) + +@script: python depends on report@ +p << r.p; +@@ + +msg = "WARNING use flexible-array member instead (https://www.kernel.org/doc/html/latest/process/deprecated.html#zero-length-and-one-element-arrays)" +coccilib.report.print_report(p[0], msg) + +@script: python depends on org@ +p << r.p; +@@ + +msg = "WARNING use flexible-array member instead (https://www.kernel.org/doc/html/latest/process/deprecated.html#zero-length-and-one-element-arrays)" +coccilib.org.print_todo(p[0], msg) diff --git a/src/net/scripts/coccinelle/misc/ifaddr.cocci b/src/net/scripts/coccinelle/misc/ifaddr.cocci new file mode 100644 index 0000000..fc92e8f --- /dev/null +++ b/src/net/scripts/coccinelle/misc/ifaddr.cocci @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0-only +/// The address of a variable or field is likely always to be non-zero. +/// +// Confidence: High +// Copyright: (C) 2012 Julia Lawall, INRIA/LIP6. +// Copyright: (C) 2012 Gilles Muller, INRIA/LiP6. +// URL: http://coccinelle.lip6.fr/ +// Comments: +// Options: --no-includes --include-headers + +virtual org +virtual report +virtual context + +@r@ +expression x; +statement S1,S2; +position p; +@@ + +*if@p (&x) + S1 else S2 + +@script:python depends on org@ +p << r.p; +@@ + +cocci.print_main("test of a variable/field address",p) + +@script:python depends on report@ +p << r.p; +@@ + +msg = "ERROR: test of a variable/field address" +coccilib.report.print_report(p[0],msg) diff --git a/src/net/scripts/coccinelle/misc/ifcol.cocci b/src/net/scripts/coccinelle/misc/ifcol.cocci new file mode 100644 index 0000000..da0351e --- /dev/null +++ b/src/net/scripts/coccinelle/misc/ifcol.cocci @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0-only +/// Find confusingly indented code in or after an if. An if branch should +/// be indented. The code following an if should not be indented. +/// Sometimes, code after an if that is indented is actually intended to be +/// part of the if branch. +/// +//# This has a high rate of false positives, because Coccinelle's column +//# calculation does not distinguish between spaces and tabs, so code that +//# is not visually aligned may be considered to be in the same column. +// +// Confidence: Low +// Copyright: (C) 2010 Nicolas Palix, DIKU. +// Copyright: (C) 2010 Julia Lawall, DIKU. +// Copyright: (C) 2010 Gilles Muller, INRIA/LiP6. +// URL: http://coccinelle.lip6.fr/ +// Comments: +// Options: --no-includes --include-headers + +virtual org +virtual report + +@r disable braces4@ +position p1,p2; +statement S1,S2; +@@ + +( +if (...) { ... } +| +if (...) S1@p1 S2@p2 +) + +@script:python depends on org@ +p1 << r.p1; +p2 << r.p2; +@@ + +if (p1[0].column == p2[0].column): + cocci.print_main("branch",p1) + cocci.print_secs("after",p2) + +@script:python depends on report@ +p1 << r.p1; +p2 << r.p2; +@@ + +if (p1[0].column == p2[0].column): + msg = "code aligned with following code on line %s" % (p2[0].line) + coccilib.report.print_report(p1[0],msg) diff --git a/src/net/scripts/coccinelle/misc/irqf_oneshot.cocci b/src/net/scripts/coccinelle/misc/irqf_oneshot.cocci new file mode 100644 index 0000000..7b48287 --- /dev/null +++ b/src/net/scripts/coccinelle/misc/irqf_oneshot.cocci @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0 +/// Since commit 1c6c69525b40 ("genirq: Reject bogus threaded irq requests") +/// threaded IRQs without a primary handler need to be requested with +/// IRQF_ONESHOT, otherwise the request will fail. +/// +/// So pass the IRQF_ONESHOT flag in this case. +/// +// +// Confidence: Moderate +// Comments: +// Options: --no-includes + +virtual patch +virtual context +virtual org +virtual report + +@r1@ +expression dev, irq, thread_fn; +position p; +@@ +( +request_threaded_irq@p(irq, NULL, thread_fn, +( +IRQF_ONESHOT | ... +| +IRQF_ONESHOT +) +, ...) +| +devm_request_threaded_irq@p(dev, irq, NULL, thread_fn, +( +IRQF_ONESHOT | ... +| +IRQF_ONESHOT +) +, ...) +) + +@r2@ +expression dev, irq, thread_fn, flags, e; +position p != r1.p; +@@ +( +flags = IRQF_ONESHOT | ... +| +flags |= IRQF_ONESHOT | ... +) +... when != flags = e +( +request_threaded_irq@p(irq, NULL, thread_fn, flags, ...); +| +devm_request_threaded_irq@p(dev, irq, NULL, thread_fn, flags, ...); +) + +@depends on patch@ +expression dev, irq, thread_fn, flags; +position p != {r1.p,r2.p}; +@@ +( +request_threaded_irq@p(irq, NULL, thread_fn, +( +-0 ++IRQF_ONESHOT +| +-flags ++flags | IRQF_ONESHOT +) +, ...) +| +devm_request_threaded_irq@p(dev, irq, NULL, thread_fn, +( +-0 ++IRQF_ONESHOT +| +-flags ++flags | IRQF_ONESHOT +) +, ...) +) + +@depends on context@ +expression dev, irq; +position p != {r1.p,r2.p}; +@@ +( +*request_threaded_irq@p(irq, NULL, ...) +| +*devm_request_threaded_irq@p(dev, irq, NULL, ...) +) + + +@match depends on report || org@ +expression dev, irq; +position p != {r1.p,r2.p}; +@@ +( +request_threaded_irq@p(irq, NULL, ...) +| +devm_request_threaded_irq@p(dev, irq, NULL, ...) +) + +@script:python depends on org@ +p << match.p; +@@ +msg = "ERROR: Threaded IRQ with no primary handler requested without IRQF_ONESHOT" +coccilib.org.print_todo(p[0],msg) + +@script:python depends on report@ +p << match.p; +@@ +msg = "ERROR: Threaded IRQ with no primary handler requested without IRQF_ONESHOT" +coccilib.report.print_report(p[0],msg) diff --git a/src/net/scripts/coccinelle/misc/newline_in_nl_msg.cocci b/src/net/scripts/coccinelle/misc/newline_in_nl_msg.cocci new file mode 100644 index 0000000..c175886 --- /dev/null +++ b/src/net/scripts/coccinelle/misc/newline_in_nl_msg.cocci @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0-only +/// +/// Catch strings ending in newline with GENL_SET_ERR_MSG, NL_SET_ERR_MSG, +/// NL_SET_ERR_MSG_MOD. +/// +// Confidence: Very High +// Copyright: (C) 2020 Intel Corporation +// URL: http://coccinelle.lip6.fr/ +// Options: --no-includes --include-headers + +virtual context +virtual org +virtual report + +@r depends on context || org || report@ +expression e; +constant m; +position p; +@@ + \(GENL_SET_ERR_MSG\|NL_SET_ERR_MSG\|NL_SET_ERR_MSG_MOD\)(e,m@p) + +@script:python@ +m << r.m; +@@ + +if not m.endswith("\\n\""): + cocci.include_match(False) + +@r1 depends on r@ +identifier fname; +expression r.e; +constant r.m; +position r.p; +@@ + fname(e,m@p) + +//---------------------------------------------------------- +// For context mode +//---------------------------------------------------------- + +@depends on context && r@ +identifier r1.fname; +expression r.e; +constant r.m; +@@ +* fname(e,m) + +//---------------------------------------------------------- +// For org mode +//---------------------------------------------------------- + +@script:python depends on org@ +fname << r1.fname; +m << r.m; +p << r.p; +@@ + +if m.endswith("\\n\""): + msg="WARNING avoid newline at end of message in %s" % (fname) + msg_safe=msg.replace("[","@(").replace("]",")") + coccilib.org.print_todo(p[0], msg_safe) + +//---------------------------------------------------------- +// For report mode +//---------------------------------------------------------- + +@script:python depends on report@ +fname << r1.fname; +m << r.m; +p << r.p; +@@ + +if m.endswith("\\n\""): + msg="WARNING avoid newline at end of message in %s" % (fname) + coccilib.report.print_report(p[0], msg) diff --git a/src/net/scripts/coccinelle/misc/noderef.cocci b/src/net/scripts/coccinelle/misc/noderef.cocci new file mode 100644 index 0000000..72de62a --- /dev/null +++ b/src/net/scripts/coccinelle/misc/noderef.cocci @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0-only +/// sizeof when applied to a pointer typed expression gives the size of +/// the pointer +/// +// Confidence: High +// Copyright: (C) 2012 Julia Lawall, INRIA/LIP6. +// Copyright: (C) 2012 Gilles Muller, INRIA/LiP6. +// URL: http://coccinelle.lip6.fr/ +// Comments: +// Options: --no-includes --include-headers + +virtual org +virtual report +virtual context +virtual patch + +@depends on patch@ +expression *x; +expression f; +expression i; +type T; +@@ + +( +x = <+... sizeof( +- x ++ *x + ) ...+> +| +f(...,(T)(x),...,sizeof( +- x ++ *x + ),...) +| +f(...,sizeof( +- x ++ *x + ),...,(T)(x),...) +| +f(...,(T)(x),...,i*sizeof( +- x ++ *x + ),...) +| +f(...,i*sizeof( +- x ++ *x + ),...,(T)(x),...) +) + +@r depends on !patch@ +expression *x; +expression f; +expression i; +position p; +type T; +@@ + +( +*x = <+... sizeof@p(x) ...+> +| +*f(...,(T)(x),...,sizeof@p(x),...) +| +*f(...,sizeof@p(x),...,(T)(x),...) +| +*f(...,(T)(x),...,i*sizeof@p(x),...) +| +*f(...,i*sizeof@p(x),...,(T)(x),...) +) + +@script:python depends on org@ +p << r.p; +@@ + +cocci.print_main("application of sizeof to pointer",p) + +@script:python depends on report@ +p << r.p; +@@ + +msg = "ERROR: application of sizeof to pointer" +coccilib.report.print_report(p[0],msg) diff --git a/src/net/scripts/coccinelle/misc/of_table.cocci b/src/net/scripts/coccinelle/misc/of_table.cocci new file mode 100644 index 0000000..4693ea7 --- /dev/null +++ b/src/net/scripts/coccinelle/misc/of_table.cocci @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: GPL-2.0 +/// Make sure (of/i2c/platform)_device_id tables are NULL terminated +// +// Keywords: of_table i2c_table platform_table +// Confidence: Medium +// Options: --include-headers + +virtual patch +virtual context +virtual org +virtual report + +@depends on context@ +identifier var, arr; +expression E; +@@ +( +struct \(of_device_id \| i2c_device_id \| platform_device_id\) arr[] = { + ..., + { + .var = E, +* } +}; +| +struct \(of_device_id \| i2c_device_id \| platform_device_id\) arr[] = { + ..., +* { ..., E, ... }, +}; +) + +@depends on patch@ +identifier var, arr; +expression E; +@@ +( +struct \(of_device_id \| i2c_device_id \| platform_device_id\) arr[] = { + ..., + { + .var = E, +- } ++ }, ++ { } +}; +| +struct \(of_device_id \| i2c_device_id \| platform_device_id\) arr[] = { + ..., + { ..., E, ... }, ++ { }, +}; +) + +@r depends on org || report@ +position p1; +identifier var, arr; +expression E; +@@ +( +struct \(of_device_id \| i2c_device_id \| platform_device_id\) arr[] = { + ..., + { + .var = E, + } + @p1 +}; +| +struct \(of_device_id \| i2c_device_id \| platform_device_id\) arr[] = { + ..., + { ..., E, ... } + @p1 +}; +) + +@script:python depends on org@ +p1 << r.p1; +arr << r.arr; +@@ + +cocci.print_main(arr,p1) + +@script:python depends on report@ +p1 << r.p1; +arr << r.arr; +@@ + +msg = "%s is not NULL terminated at line %s" % (arr, p1[0].line) +coccilib.report.print_report(p1[0],msg) diff --git a/src/net/scripts/coccinelle/misc/orplus.cocci b/src/net/scripts/coccinelle/misc/orplus.cocci new file mode 100644 index 0000000..52203dc --- /dev/null +++ b/src/net/scripts/coccinelle/misc/orplus.cocci @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0-only +/// Check for constants that are added but are used elsewhere as bitmasks +/// The results should be checked manually to ensure that the nonzero +/// bits in the two constants are actually disjoint. +/// +// Confidence: Moderate +// Copyright: (C) 2013 Julia Lawall, INRIA/LIP6. +// Copyright: (C) 2013 Gilles Muller, INRIA/LIP6. +// URL: http://coccinelle.lip6.fr/ +// Comments: +// Options: --no-includes --include-headers + +virtual org +virtual report +virtual context + +@r@ +constant c,c1; +identifier i,i1; +position p; +@@ + +( + c1 + c - 1 +| + c1@i1 +@p c@i +) + +@s@ +constant r.c, r.c1; +identifier i; +expression e; +@@ + +( +e | c@i +| +e & c@i +| +e |= c@i +| +e &= c@i +| +e | c1@i +| +e & c1@i +| +e |= c1@i +| +e &= c1@i +) + +@depends on s@ +position r.p; +constant c1,c2; +@@ + +* c1 +@p c2 + +@script:python depends on s && org@ +p << r.p; +@@ + +cocci.print_main("sum of probable bitmasks, consider |",p) + +@script:python depends on s && report@ +p << r.p; +@@ + +msg = "WARNING: sum of probable bitmasks, consider |" +coccilib.report.print_report(p[0],msg) diff --git a/src/net/scripts/coccinelle/misc/returnvar.cocci b/src/net/scripts/coccinelle/misc/returnvar.cocci new file mode 100644 index 0000000..ce0d9ee --- /dev/null +++ b/src/net/scripts/coccinelle/misc/returnvar.cocci @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0-only +/// +/// Remove unneeded variable used to store return value. +/// +// Confidence: Moderate +// Copyright: (C) 2012 Peter Senna Tschudin, INRIA/LIP6. +// URL: http://coccinelle.lip6.fr/ +// Comments: Comments on code can be deleted if near code that is removed. +// "when strict" can be removed to get more hits, but adds false +// positives +// Options: --no-includes --include-headers + +virtual patch +virtual report +virtual context +virtual org + +@depends on patch@ +type T; +constant C; +identifier ret; +@@ +- T ret = C; +... when != ret + when strict +return +- ret ++ C +; + +@depends on context@ +type T; +constant C; +identifier ret; +@@ +* T ret = C; +... when != ret + when strict +* return ret; + +@r1 depends on report || org@ +type T; +constant C; +identifier ret; +position p1, p2; +@@ +T ret@p1 = C; +... when != ret + when strict +return ret@p2; + +@script:python depends on report@ +p1 << r1.p1; +p2 << r1.p2; +C << r1.C; +ret << r1.ret; +@@ +coccilib.report.print_report(p1[0], "Unneeded variable: \"" + ret + "\". Return \"" + C + "\" on line " + p2[0].line) + +@script:python depends on org@ +p1 << r1.p1; +p2 << r1.p2; +C << r1.C; +ret << r1.ret; +@@ +cocci.print_main("unneeded \"" + ret + "\" variable", p1) +cocci.print_sec("return " + C + " here", p2) diff --git a/src/net/scripts/coccinelle/misc/semicolon.cocci b/src/net/scripts/coccinelle/misc/semicolon.cocci new file mode 100644 index 0000000..a53edb0 --- /dev/null +++ b/src/net/scripts/coccinelle/misc/semicolon.cocci @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: GPL-2.0-only +/// +/// Remove unneeded semicolon. +/// +// Confidence: Moderate +// Copyright: (C) 2012 Peter Senna Tschudin, INRIA/LIP6. +// URL: http://coccinelle.lip6.fr/ +// Comments: Some false positives on empty default cases in switch statements. +// Options: --no-includes --include-headers + +virtual patch +virtual report +virtual context +virtual org + +@r_default@ +position p; +@@ +switch (...) +{ +default: ...;@p +} + +@r_case@ +position p; +@@ +( +switch (...) +{ +case ...:;@p +} +| +switch (...) +{ +case ...:... +case ...:;@p +} +| +switch (...) +{ +case ...:... +case ...: +case ...:;@p +} +) + +@r1@ +statement S; +position p1; +position p != {r_default.p, r_case.p}; +identifier label; +@@ +( +label:; +| +S@p1;@p +) + +@script:python@ +p << r1.p; +p1 << r1.p1; +@@ +if p[0].line != p1[0].line_end: + cocci.include_match(False) + +@depends on patch@ +position r1.p; +@@ +-;@p + +@script:python depends on report@ +p << r1.p; +@@ +coccilib.report.print_report(p[0],"Unneeded semicolon") + +@depends on context@ +position r1.p; +@@ +*;@p + +@script:python depends on org@ +p << r1.p; +@@ +cocci.print_main("Unneeded semicolon",p) diff --git a/src/net/scripts/coccinelle/misc/uninitialized_var.cocci b/src/net/scripts/coccinelle/misc/uninitialized_var.cocci new file mode 100644 index 0000000..8fa845c --- /dev/null +++ b/src/net/scripts/coccinelle/misc/uninitialized_var.cocci @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0-only +/// +/// Please, don't reintroduce uninitialized_var(). +/// From Documentation/process/deprecated.rst: +/// For any compiler warnings about uninitialized variables, just add +/// an initializer. Using warning-silencing tricks is dangerous as it +/// papers over real bugs (or can in the future), and suppresses unrelated +/// compiler warnings (e.g. "unused variable"). If the compiler thinks it +/// is uninitialized, either simply initialize the variable or make compiler +/// changes. Keep in mind that in most cases, if an initialization is +/// obviously redundant, the compiler's dead-store elimination pass will make +/// sure there are no needless variable writes. +/// +// Confidence: High +// Copyright: (C) 2020 Denis Efremov ISPRAS +// Options: --no-includes --include-headers +// + +virtual context +virtual report +virtual org + +@r@ +identifier var; +type T; +position p; +@@ + +( +* T var =@p var; +| +* T var =@p *(&(var)); +| +* var =@p var +| +* var =@p *(&(var)) +) + +@script:python depends on report@ +p << r.p; +@@ + +coccilib.report.print_report(p[0], + "WARNING this kind of initialization is deprecated (https://www.kernel.org/doc/html/latest/process/deprecated.html#uninitialized-var)") + +@script:python depends on org@ +p << r.p; +@@ + +coccilib.org.print_todo(p[0], + "WARNING this kind of initialization is deprecated (https://www.kernel.org/doc/html/latest/process/deprecated.html#uninitialized-var)") diff --git a/src/net/scripts/coccinelle/misc/warn.cocci b/src/net/scripts/coccinelle/misc/warn.cocci new file mode 100644 index 0000000..e379661 --- /dev/null +++ b/src/net/scripts/coccinelle/misc/warn.cocci @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: GPL-2.0-only +/// Use WARN(1,...) rather than printk followed by WARN_ON(1) +/// +// Confidence: High +// Copyright: (C) 2012 Julia Lawall, INRIA/LIP6. +// Copyright: (C) 2012 Gilles Muller, INRIA/LiP6. +// URL: http://coccinelle.lip6.fr/ +// Comments: +// Options: --no-includes --include-headers + +virtual patch +virtual context +virtual org +virtual report + +@bad1@ +position p; +@@ + +printk(...); +printk@p(...); +WARN_ON(1); + +@r1 depends on context || report || org@ +position p != bad1.p; +@@ + + printk@p(...); +*WARN_ON(1); + +@script:python depends on org@ +p << r1.p; +@@ + +cocci.print_main("printk + WARN_ON can be just WARN",p) + +@script:python depends on report@ +p << r1.p; +@@ + +msg = "SUGGESTION: printk + WARN_ON can be just WARN" +coccilib.report.print_report(p[0],msg) + +@ok1 depends on patch@ +expression list es; +position p != bad1.p; +@@ + +-printk@p( ++WARN(1, + es); +-WARN_ON(1); + +@depends on patch@ +expression list ok1.es; +@@ + +if (...) +- { + WARN(1,es); +- } + +// -------------------------------------------------------------------- + +@bad2@ +position p; +@@ + +printk(...); +printk@p(...); +WARN_ON_ONCE(1); + +@r2 depends on context || report || org@ +position p != bad1.p; +@@ + + printk@p(...); +*WARN_ON_ONCE(1); + +@script:python depends on org@ +p << r2.p; +@@ + +cocci.print_main("printk + WARN_ON_ONCE can be just WARN_ONCE",p) + +@script:python depends on report@ +p << r2.p; +@@ + +msg = "SUGGESTION: printk + WARN_ON_ONCE can be just WARN_ONCE" +coccilib.report.print_report(p[0],msg) + +@ok2 depends on patch@ +expression list es; +position p != bad2.p; +@@ + +-printk@p( ++WARN_ONCE(1, + es); +-WARN_ON_ONCE(1); + +@depends on patch@ +expression list ok2.es; +@@ + +if (...) +- { + WARN_ONCE(1,es); +- } diff --git a/src/net/scripts/coccinelle/null/badzero.cocci b/src/net/scripts/coccinelle/null/badzero.cocci new file mode 100644 index 0000000..882dd65 --- /dev/null +++ b/src/net/scripts/coccinelle/null/badzero.cocci @@ -0,0 +1,239 @@ +// SPDX-License-Identifier: GPL-2.0-only +/// Compare pointer-typed values to NULL rather than 0 +/// +//# This makes an effort to choose between !x and x == NULL. !x is used +//# if it has previously been used with the function used to initialize x. +//# This relies on type information. More type information can be obtained +//# using the option -all_includes and the option -I to specify an +//# include path. +// +// Confidence: High +// Copyright: (C) 2012 Julia Lawall, INRIA/LIP6. +// Copyright: (C) 2012 Gilles Muller, INRIA/LiP6. +// URL: http://coccinelle.lip6.fr/ +// Requires: 1.0.0 +// Options: + +virtual patch +virtual context +virtual org +virtual report + +@initialize:ocaml@ +@@ +let negtable = Hashtbl.create 101 + +@depends on patch@ +expression *E; +identifier f; +@@ + +( + (E = f(...)) == +- 0 ++ NULL +| + (E = f(...)) != +- 0 ++ NULL +| +- 0 ++ NULL + == (E = f(...)) +| +- 0 ++ NULL + != (E = f(...)) +) + + +@t1 depends on !patch@ +expression *E; +identifier f; +position p; +@@ + +( + (E = f(...)) == +* 0@p +| + (E = f(...)) != +* 0@p +| +* 0@p + == (E = f(...)) +| +* 0@p + != (E = f(...)) +) + +@script:python depends on org@ +p << t1.p; +@@ + +coccilib.org.print_todo(p[0], "WARNING comparing pointer to 0") + +@script:python depends on report@ +p << t1.p; +@@ + +coccilib.report.print_report(p[0], "WARNING comparing pointer to 0") + +// Tests of returned values + +@s@ +identifier f; +expression E,E1; +@@ + + E = f(...) + ... when != E = E1 + !E + +@script:ocaml depends on s@ +f << s.f; +@@ + +try let _ = Hashtbl.find negtable f in () +with Not_found -> Hashtbl.add negtable f () + +@ r disable is_zero,isnt_zero exists @ +expression *E; +identifier f; +@@ + +E = f(...) +... +(E == 0 +|E != 0 +|0 == E +|0 != E +) + +@script:ocaml@ +f << r.f; +@@ + +try let _ = Hashtbl.find negtable f in () +with Not_found -> include_match false + +// This rule may lead to inconsistent path problems, if E is defined in two +// places +@ depends on patch disable is_zero,isnt_zero @ +expression *E; +expression E1; +identifier r.f; +@@ + +E = f(...) +<... +( +- E == 0 ++ !E +| +- E != 0 ++ E +| +- 0 == E ++ !E +| +- 0 != E ++ E +) +...> +?E = E1 + +@t2 depends on !patch disable is_zero,isnt_zero @ +expression *E; +expression E1; +identifier r.f; +position p1; +position p2; +@@ + +E = f(...) +<... +( +* E == 0@p1 +| +* E != 0@p2 +| +* 0@p1 == E +| +* 0@p1 != E +) +...> +?E = E1 + +@script:python depends on org@ +p << t2.p1; +@@ + +coccilib.org.print_todo(p[0], "WARNING comparing pointer to 0, suggest !E") + +@script:python depends on org@ +p << t2.p2; +@@ + +coccilib.org.print_todo(p[0], "WARNING comparing pointer to 0") + +@script:python depends on report@ +p << t2.p1; +@@ + +coccilib.report.print_report(p[0], "WARNING comparing pointer to 0, suggest !E") + +@script:python depends on report@ +p << t2.p2; +@@ + +coccilib.report.print_report(p[0], "WARNING comparing pointer to 0") + +@ depends on patch disable is_zero,isnt_zero @ +expression *E; +@@ + +( + E == +- 0 ++ NULL +| + E != +- 0 ++ NULL +| +- 0 ++ NULL + == E +| +- 0 ++ NULL + != E +) + +@ t3 depends on !patch disable is_zero,isnt_zero @ +expression *E; +position p; +@@ + +( +* E == 0@p +| +* E != 0@p +| +* 0@p == E +| +* 0@p != E +) + +@script:python depends on org@ +p << t3.p; +@@ + +coccilib.org.print_todo(p[0], "WARNING comparing pointer to 0") + +@script:python depends on report@ +p << t3.p; +@@ + +coccilib.report.print_report(p[0], "WARNING comparing pointer to 0") diff --git a/src/net/scripts/coccinelle/null/deref_null.cocci b/src/net/scripts/coccinelle/null/deref_null.cocci new file mode 100644 index 0000000..98f1e7f --- /dev/null +++ b/src/net/scripts/coccinelle/null/deref_null.cocci @@ -0,0 +1,283 @@ +// SPDX-License-Identifier: GPL-2.0-only +/// +/// A variable is dereferenced under a NULL test. +/// Even though it is known to be NULL. +/// +// Confidence: Moderate +// Copyright: (C) 2010 Nicolas Palix, DIKU. +// Copyright: (C) 2010 Julia Lawall, DIKU. +// Copyright: (C) 2010 Gilles Muller, INRIA/LiP6. +// URL: http://coccinelle.lip6.fr/ +// Comments: -I ... -all_includes can give more complete results +// Options: + +virtual context +virtual org +virtual report + +// The following two rules are separate, because both can match a single +// expression in different ways +@pr1 expression@ +expression E; +identifier f; +position p1; +@@ + + (E != NULL && ...) ? <+...E->f@p1...+> : ... + +@pr2 expression@ +expression E; +identifier f; +position p2; +@@ + +( + (E != NULL) && ... && <+...E->f@p2...+> +| + (E == NULL) || ... || <+...E->f@p2...+> +| + sizeof(<+...E->f@p2...+>) +) + +@ifm@ +expression *E; +statement S1,S2; +position p1; +@@ + +if@p1 ((E == NULL && ...) || ...) S1 else S2 + +// For org and report modes + +@r depends on !context && (org || report) exists@ +expression subE <= ifm.E; +expression *ifm.E; +expression E1,E2; +identifier f; +statement S1,S2,S3,S4; +iterator iter; +position p!={pr1.p1,pr2.p2}; +position ifm.p1; +@@ + +if@p1 ((E == NULL && ...) || ...) +{ + ... when != if (...) S1 else S2 +( + iter(subE,...) S4 // no use +| + list_remove_head(E2,subE,...) +| + subE = E1 +| + for(subE = E1;...;...) S4 +| + subE++ +| + ++subE +| + --subE +| + subE-- +| + &subE +| + E->f@p // bad use +) + ... when any + return ...; +} +else S3 + +@script:python depends on !context && !org && report@ +p << r.p; +p1 << ifm.p1; +x << ifm.E; +@@ + +msg="ERROR: %s is NULL but dereferenced." % (x) +coccilib.report.print_report(p[0], msg) +cocci.include_match(False) + +@script:python depends on !context && org && !report@ +p << r.p; +p1 << ifm.p1; +x << ifm.E; +@@ + +msg="ERROR: %s is NULL but dereferenced." % (x) +msg_safe=msg.replace("[","@(").replace("]",")") +cocci.print_main(msg_safe,p) +cocci.include_match(False) + +@s depends on !context && (org || report) exists@ +expression subE <= ifm.E; +expression *ifm.E; +expression E1,E2; +identifier f; +statement S1,S2,S3,S4; +iterator iter; +position p!={pr1.p1,pr2.p2}; +position ifm.p1; +@@ + +if@p1 ((E == NULL && ...) || ...) +{ + ... when != if (...) S1 else S2 +( + iter(subE,...) S4 // no use +| + list_remove_head(E2,subE,...) +| + subE = E1 +| + for(subE = E1;...;...) S4 +| + subE++ +| + ++subE +| + --subE +| + subE-- +| + &subE +| + E->f@p // bad use +) + ... when any +} +else S3 + +@script:python depends on !context && !org && report@ +p << s.p; +p1 << ifm.p1; +x << ifm.E; +@@ + +msg="ERROR: %s is NULL but dereferenced." % (x) +coccilib.report.print_report(p[0], msg) + +@script:python depends on !context && org && !report@ +p << s.p; +p1 << ifm.p1; +x << ifm.E; +@@ + +msg="ERROR: %s is NULL but dereferenced." % (x) +msg_safe=msg.replace("[","@(").replace("]",")") +cocci.print_main(msg_safe,p) + +// For context mode + +@depends on context && !org && !report exists@ +expression subE <= ifm.E; +expression *ifm.E; +expression E1,E2; +identifier f; +statement S1,S2,S3,S4; +iterator iter; +position p!={pr1.p1,pr2.p2}; +position ifm.p1; +@@ + +if@p1 ((E == NULL && ...) || ...) +{ + ... when != if (...) S1 else S2 +( + iter(subE,...) S4 // no use +| + list_remove_head(E2,subE,...) +| + subE = E1 +| + for(subE = E1;...;...) S4 +| + subE++ +| + ++subE +| + --subE +| + subE-- +| + &subE +| +* E->f@p // bad use +) + ... when any + return ...; +} +else S3 + +// The following three rules are duplicates of ifm, pr1 and pr2 respectively. +// It is need because the previous rule as already made a "change". + +@pr11 depends on context && !org && !report expression@ +expression E; +identifier f; +position p1; +@@ + + (E != NULL && ...) ? <+...E->f@p1...+> : ... + +@pr12 depends on context && !org && !report expression@ +expression E; +identifier f; +position p2; +@@ + +( + (E != NULL) && ... && <+...E->f@p2...+> +| + (E == NULL) || ... || <+...E->f@p2...+> +| + sizeof(<+...E->f@p2...+>) +) + +@ifm1 depends on context && !org && !report@ +expression *E; +statement S1,S2; +position p1; +@@ + +if@p1 ((E == NULL && ...) || ...) S1 else S2 + +@depends on context && !org && !report exists@ +expression subE <= ifm1.E; +expression *ifm1.E; +expression E1,E2; +identifier f; +statement S1,S2,S3,S4; +iterator iter; +position p!={pr11.p1,pr12.p2}; +position ifm1.p1; +@@ + +if@p1 ((E == NULL && ...) || ...) +{ + ... when != if (...) S1 else S2 +( + iter(subE,...) S4 // no use +| + list_remove_head(E2,subE,...) +| + subE = E1 +| + for(subE = E1;...;...) S4 +| + subE++ +| + ++subE +| + --subE +| + subE-- +| + &subE +| +* E->f@p // bad use +) + ... when any +} +else S3 diff --git a/src/net/scripts/coccinelle/null/eno.cocci b/src/net/scripts/coccinelle/null/eno.cocci new file mode 100644 index 0000000..81584ff --- /dev/null +++ b/src/net/scripts/coccinelle/null/eno.cocci @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0-only +/// The various basic memory allocation functions don't return ERR_PTR +/// +// Confidence: High +// Copyright: (C) 2010-2012 Nicolas Palix. +// Copyright: (C) 2010-2012 Julia Lawall, INRIA/LIP6. +// Copyright: (C) 2010-2012 Gilles Muller, INRIA/LiP6. +// URL: http://coccinelle.lip6.fr/ +// Comments: +// Options: --no-includes --include-headers + +virtual patch +virtual context +virtual org +virtual report + +@depends on patch@ +expression x,E; +@@ + +x = \(kmalloc\|kzalloc\|kcalloc\|kmem_cache_alloc\|kmem_cache_zalloc\|kmem_cache_alloc_node\|kmalloc_node\|kzalloc_node\)(...) +... when != x = E +- IS_ERR(x) ++ !x + +@r depends on !patch exists@ +expression x,E; +position p1,p2; +@@ + +*x = \(kmalloc@p1\|kzalloc@p1\|kcalloc@p1\|kmem_cache_alloc@p1\|kmem_cache_zalloc@p1\|kmem_cache_alloc_node@p1\|kmalloc_node@p1\|kzalloc_node@p1\)(...) +... when != x = E +* IS_ERR@p2(x) + +@script:python depends on org@ +p1 << r.p1; +p2 << r.p2; +@@ + +cocci.print_main("alloc call",p1) +cocci.print_secs("IS_ERR that should be NULL tests",p2) + +@script:python depends on report@ +p1 << r.p1; +p2 << r.p2; +@@ + +msg = "ERROR: allocation function on line %s returns NULL not ERR_PTR on failure" % (p1[0].line) +coccilib.report.print_report(p2[0], msg) diff --git a/src/net/scripts/coccinelle/null/kmerr.cocci b/src/net/scripts/coccinelle/null/kmerr.cocci new file mode 100644 index 0000000..d0e004d --- /dev/null +++ b/src/net/scripts/coccinelle/null/kmerr.cocci @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0-only +/// This semantic patch looks for kmalloc etc that are not followed by a +/// NULL check. It only gives a report in the case where there is some +/// error handling code later in the function, which may be helpful +/// in determining what the error handling code for the call to kmalloc etc +/// should be. +/// +// Confidence: High +// Copyright: (C) 2010 Nicolas Palix, DIKU. +// Copyright: (C) 2010 Julia Lawall, DIKU. +// Copyright: (C) 2010 Gilles Muller, INRIA/LiP6. +// URL: http://coccinelle.lip6.fr/ +// Comments: +// Options: --no-includes --include-headers + +virtual context +virtual org +virtual report + +@withtest@ +expression x; +position p; +identifier f,fld; +@@ + +x@p = f(...); +... when != x->fld +\(x == NULL \| x != NULL\) + +@fixed depends on context && !org && !report@ +expression x,x1; +position p1 != withtest.p; +statement S; +position any withtest.p; +identifier f; +@@ + +*x@p1 = \(kmalloc\|kzalloc\|kcalloc\)(...); +... +*x1@p = f(...); +if (!x1) S + +// ------------------------------------------------------------------------ + +@rfixed depends on (org || report) && !context exists@ +expression x,x1; +position p1 != withtest.p; +position p2; +statement S; +position any withtest.p; +identifier f; +@@ + +x@p1 = \(kmalloc\|kzalloc\|kcalloc\)(...); +... +x1@p = f@p2(...); +if (!x1) S + +@script:python depends on org@ +p1 << rfixed.p1; +p2 << rfixed.p2; +@@ + +cocci.print_main("alloc call",p1) +cocci.print_secs("possible model",p2) + +@script:python depends on report@ +p1 << rfixed.p1; +p2 << rfixed.p2; +@@ + +msg = "alloc with no test, possible model on line %s" % (p2[0].line) +coccilib.report.print_report(p1[0],msg) diff --git a/src/net/scripts/coccinelle/tests/doublebitand.cocci b/src/net/scripts/coccinelle/tests/doublebitand.cocci new file mode 100644 index 0000000..0f0b94e --- /dev/null +++ b/src/net/scripts/coccinelle/tests/doublebitand.cocci @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0-only +/// Find bit operations that include the same argument more than once +//# One source of false positives is when the argument performs a side +//# effect. Another source of false positives is when a neutral value +//# such as 0 for | is used to indicate no information, to maintain the +//# same structure as other similar expressions +/// +// Confidence: Moderate +// Copyright: (C) 2010 Nicolas Palix, DIKU. +// Copyright: (C) 2010 Julia Lawall, DIKU. +// Copyright: (C) 2010 Gilles Muller, INRIA/LiP6. +// URL: http://coccinelle.lip6.fr/ +// Comments: +// Options: --no-includes --include-headers + +virtual context +virtual org +virtual report + +@r expression@ +expression E; +position p; +@@ + +( +* E@p + & ... & E +| +* E@p + | ... | E +| +* E@p + & ... & !E +| +* E@p + | ... | !E +| +* !E@p + & ... & E +| +* !E@p + | ... | E +) + +@script:python depends on org@ +p << r.p; +@@ + +cocci.print_main("duplicated argument to & or |",p) + +@script:python depends on report@ +p << r.p; +@@ + +coccilib.report.print_report(p[0],"duplicated argument to & or |") diff --git a/src/net/scripts/coccinelle/tests/doubletest.cocci b/src/net/scripts/coccinelle/tests/doubletest.cocci new file mode 100644 index 0000000..b35519c --- /dev/null +++ b/src/net/scripts/coccinelle/tests/doubletest.cocci @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0-only +/// Find &&/|| operations that include the same argument more than once +//# A common source of false positives is when the expression, or +//# another expresssion in the same && or || operation, performs a +//# side effect. +/// +// Confidence: Moderate +// Copyright: (C) 2010 Nicolas Palix, DIKU. +// Copyright: (C) 2010 Julia Lawall, DIKU. +// Copyright: (C) 2010 Gilles Muller, INRIA/LiP6. +// URL: http://coccinelle.lip6.fr/ +// Comments: +// Options: --no-includes --include-headers + +virtual context +virtual org +virtual report + +@r expression@ +expression E; +position p; +@@ + +( + E@p || ... || E +| + E@p && ... && E +) + +@bad@ +expression r.E,e1,e2,fn; +position r.p; +assignment operator op; +@@ + +( +E@p +& + <+... \(fn(...)\|e1 op e2\|e1++\|e1--\|++e1\|--e1\) ...+> +) + +@depends on context && !bad@ +expression r.E; +position r.p; +@@ + +*E@p + +@script:python depends on org && !bad@ +p << r.p; +@@ + +cocci.print_main("duplicated argument to && or ||",p) + +@script:python depends on report && !bad@ +p << r.p; +@@ + +coccilib.report.print_report(p[0],"duplicated argument to && or ||") diff --git a/src/net/scripts/coccinelle/tests/odd_ptr_err.cocci b/src/net/scripts/coccinelle/tests/odd_ptr_err.cocci new file mode 100644 index 0000000..11d4e2b --- /dev/null +++ b/src/net/scripts/coccinelle/tests/odd_ptr_err.cocci @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: GPL-2.0-only +/// PTR_ERR should access the value just tested by IS_ERR +//# There can be false positives in the patch case, where it is the call to +//# IS_ERR that is wrong. +/// +// Confidence: High +// Copyright: (C) 2012, 2015 Julia Lawall, INRIA. +// Copyright: (C) 2012, 2015 Gilles Muller, INRIA. +// URL: http://coccinelle.lip6.fr/ +// Options: --no-includes --include-headers + +virtual patch +virtual context +virtual org +virtual report + +@ok1 exists@ +expression x,e; +position p; +@@ + +if (IS_ERR(x=e) || ...) { + <... + PTR_ERR@p(x) + ...> +} + +@ok2 exists@ +expression x,e1,e2; +position p; +@@ + +if (IS_ERR(x) || ...) { + <... +( + PTR_ERR@p(\(e1 ? e2 : x\|e1 ? x : e2\)) +| + PTR_ERR@p(x) +) + ...> +} + +@r1 depends on patch && !context && !org && !report exists@ +expression x,y; +position p != {ok1.p,ok2.p}; +@@ + +if (IS_ERR(x) || ...) { + ... when any + when != IS_ERR(...) +( + PTR_ERR(x) +| + PTR_ERR@p( +- y ++ x + ) +) + ... when any +} + +// ---------------------------------------------------------------------------- + +@r1_context depends on !patch && (context || org || report) exists@ +position p != {ok1.p,ok2.p}; +expression x, y; +position j0, j1; +@@ + +if (IS_ERR@j0(x) || ...) { + ... when any + when != IS_ERR(...) +( + PTR_ERR(x) +| + PTR_ERR@j1@p( + y + ) +) + ... when any +} + +@r1_disj depends on !patch && (context || org || report) exists@ +position p != {ok1.p,ok2.p}; +expression x, y; +position r1_context.j0, r1_context.j1; +@@ + +* if (IS_ERR@j0(x) || ...) { + ... when any + when != IS_ERR(...) +* PTR_ERR@j1@p( + y + ) + ... when any +} + +// ---------------------------------------------------------------------------- + +@script:python r1_org depends on org@ +j0 << r1_context.j0; +j1 << r1_context.j1; +@@ + +msg = "inconsistent IS_ERR and PTR_ERR" +coccilib.org.print_todo(j0[0], msg) +coccilib.org.print_link(j1[0], "") + +// ---------------------------------------------------------------------------- + +@script:python r1_report depends on report@ +j0 << r1_context.j0; +j1 << r1_context.j1; +@@ + +msg = "inconsistent IS_ERR and PTR_ERR on line %s." % (j1[0].line) +coccilib.report.print_report(j0[0], msg) + diff --git a/src/net/scripts/coccinelle/tests/unsigned_lesser_than_zero.cocci b/src/net/scripts/coccinelle/tests/unsigned_lesser_than_zero.cocci new file mode 100644 index 0000000..91e286a --- /dev/null +++ b/src/net/scripts/coccinelle/tests/unsigned_lesser_than_zero.cocci @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0-only +/// Unsigned expressions cannot be lesser than zero. Presence of +/// comparisons 'unsigned (<|<=|>|>=) 0' often indicates a bug, +/// usually wrong type of variable. +/// +/// To reduce number of false positives following tests have been added: +/// - parts of range checks are skipped, eg. "if (u < 0 || u > 15) ...", +/// developers prefer to keep such code, +/// - comparisons "<= 0" and "> 0" are performed only on results of +/// signed functions/macros, +/// - hardcoded list of signed functions/macros with always non-negative +/// result is used to avoid false positives difficult to detect by other ways +/// +// Confidence: Average +// Copyright: (C) 2015 Andrzej Hajda, Samsung Electronics Co., Ltd. +// URL: http://coccinelle.lip6.fr/ +// Options: --all-includes + +virtual context +virtual org +virtual report + +@r_cmp@ +position p; +typedef bool, u8, u16, u32, u64; +{unsigned char, unsigned short, unsigned int, unsigned long, unsigned long long, + size_t, bool, u8, u16, u32, u64} v; +expression e; +@@ + + \( v = e \| &v \) + ... + (\( v@p < 0 \| v@p <= 0 \| v@p >= 0 \| v@p > 0 \)) + +@r@ +position r_cmp.p; +typedef s8, s16, s32, s64; +{char, short, int, long, long long, ssize_t, s8, s16, s32, s64} vs; +expression c, e, v; +identifier f !~ "^(ata_id_queue_depth|btrfs_copy_from_user|dma_map_sg|dma_map_sg_attrs|fls|fls64|gameport_time|get_write_extents|nla_len|ntoh24|of_flat_dt_match|of_get_child_count|uart_circ_chars_pending|[A-Z0-9_]+)$"; +@@ + +( + v = f(...)@vs; + ... when != v = e; +* (\( v@p <=@e 0 \| v@p >@e 0 \)) + ... when any +| +( + (\( v@p < 0 \| v@p <= 0 \)) || ... || (\( v >= c \| v > c \)) +| + (\( v >= c \| v > c \)) || ... || (\( v@p < 0 \| v@p <= 0 \)) +| + (\( v@p >= 0 \| v@p > 0 \)) && ... && (\( v < c \| v <= c \)) +| + ((\( v < c \| v <= c \) && ... && \( v@p >= 0 \| v@p > 0 \))) +| +* (\( v@p <@e 0 \| v@p >=@e 0 \)) +) +) + +@script:python depends on org@ +p << r_cmp.p; +e << r.e; +@@ + +msg = "WARNING: Unsigned expression compared with zero: %s" % (e) +coccilib.org.print_todo(p[0], msg) + +@script:python depends on report@ +p << r_cmp.p; +e << r.e; +@@ + +msg = "WARNING: Unsigned expression compared with zero: %s" % (e) +coccilib.report.print_report(p[0], msg) diff --git a/src/net/scripts/config b/src/net/scripts/config new file mode 100755 index 0000000..8c8d7c3 --- /dev/null +++ b/src/net/scripts/config @@ -0,0 +1,229 @@ +#!/usr/bin/env bash +# SPDX-License-Identifier: GPL-2.0 +# Manipulate options in a .config file from the command line + +myname=${0##*/} + +# If no prefix forced, use the default CONFIG_ +CONFIG_="${CONFIG_-CONFIG_}" + +# We use an uncommon delimiter for sed substitutions +SED_DELIM=$(echo -en "\001") + +usage() { + cat >&2 <<EOL +Manipulate options in a .config file from the command line. +Usage: +$myname options command ... +commands: + --enable|-e option Enable option + --disable|-d option Disable option + --module|-m option Turn option into a module + --set-str option string + Set option to "string" + --set-val option value + Set option to value + --undefine|-u option Undefine option + --state|-s option Print state of option (n,y,m,undef) + + --enable-after|-E beforeopt option + Enable option directly after other option + --disable-after|-D beforeopt option + Disable option directly after other option + --module-after|-M beforeopt option + Turn option into module directly after other option + + commands can be repeated multiple times + +options: + --file config-file .config file to change (default .config) + --keep-case|-k Keep next symbols' case (dont' upper-case it) + +$myname doesn't check the validity of the .config file. This is done at next +make time. + +By default, $myname will upper-case the given symbol. Use --keep-case to keep +the case of all following symbols unchanged. + +$myname uses 'CONFIG_' as the default symbol prefix. Set the environment +variable CONFIG_ to the prefix to use. Eg.: CONFIG_="FOO_" $myname ... +EOL + exit 1 +} + +checkarg() { + ARG="$1" + if [ "$ARG" = "" ] ; then + usage + fi + case "$ARG" in + ${CONFIG_}*) + ARG="${ARG/${CONFIG_}/}" + ;; + esac + if [ "$MUNGE_CASE" = "yes" ] ; then + ARG="`echo $ARG | tr a-z A-Z`" + fi +} + +txt_append() { + local anchor="$1" + local insert="$2" + local infile="$3" + local tmpfile="$infile.swp" + + # sed append cmd: 'a\' + newline + text + newline + cmd="$(printf "a\\%b$insert" "\n")" + + sed -e "/$anchor/$cmd" "$infile" >"$tmpfile" + # replace original file with the edited one + mv "$tmpfile" "$infile" +} + +txt_subst() { + local before="$1" + local after="$2" + local infile="$3" + local tmpfile="$infile.swp" + + sed -e "s$SED_DELIM$before$SED_DELIM$after$SED_DELIM" "$infile" >"$tmpfile" + # replace original file with the edited one + mv "$tmpfile" "$infile" +} + +txt_delete() { + local text="$1" + local infile="$2" + local tmpfile="$infile.swp" + + sed -e "/$text/d" "$infile" >"$tmpfile" + # replace original file with the edited one + mv "$tmpfile" "$infile" +} + +set_var() { + local name=$1 new=$2 before=$3 + + name_re="^($name=|# $name is not set)" + before_re="^($before=|# $before is not set)" + if test -n "$before" && grep -Eq "$before_re" "$FN"; then + txt_append "^$before=" "$new" "$FN" + txt_append "^# $before is not set" "$new" "$FN" + elif grep -Eq "$name_re" "$FN"; then + txt_subst "^$name=.*" "$new" "$FN" + txt_subst "^# $name is not set" "$new" "$FN" + else + echo "$new" >>"$FN" + fi +} + +undef_var() { + local name=$1 + + txt_delete "^$name=" "$FN" + txt_delete "^# $name is not set" "$FN" +} + +if [ "$1" = "--file" ]; then + FN="$2" + if [ "$FN" = "" ] ; then + usage + fi + shift 2 +else + FN=.config +fi + +if [ "$1" = "" ] ; then + usage +fi + +MUNGE_CASE=yes +while [ "$1" != "" ] ; do + CMD="$1" + shift + case "$CMD" in + --keep-case|-k) + MUNGE_CASE=no + continue + ;; + --refresh) + ;; + --*-after|-E|-D|-M) + checkarg "$1" + A=$ARG + checkarg "$2" + B=$ARG + shift 2 + ;; + -*) + checkarg "$1" + shift + ;; + esac + case "$CMD" in + --enable|-e) + set_var "${CONFIG_}$ARG" "${CONFIG_}$ARG=y" + ;; + + --disable|-d) + set_var "${CONFIG_}$ARG" "# ${CONFIG_}$ARG is not set" + ;; + + --module|-m) + set_var "${CONFIG_}$ARG" "${CONFIG_}$ARG=m" + ;; + + --set-str) + # sed swallows one level of escaping, so we need double-escaping + set_var "${CONFIG_}$ARG" "${CONFIG_}$ARG=\"${1//\"/\\\\\"}\"" + shift + ;; + + --set-val) + set_var "${CONFIG_}$ARG" "${CONFIG_}$ARG=$1" + shift + ;; + --undefine|-u) + undef_var "${CONFIG_}$ARG" + ;; + + --state|-s) + if grep -q "# ${CONFIG_}$ARG is not set" $FN ; then + echo n + else + V="$(grep "^${CONFIG_}$ARG=" $FN)" + if [ $? != 0 ] ; then + echo undef + else + V="${V/#${CONFIG_}$ARG=/}" + V="${V/#\"/}" + V="${V/%\"/}" + V="${V//\\\"/\"}" + echo "${V}" + fi + fi + ;; + + --enable-after|-E) + set_var "${CONFIG_}$B" "${CONFIG_}$B=y" "${CONFIG_}$A" + ;; + + --disable-after|-D) + set_var "${CONFIG_}$B" "# ${CONFIG_}$B is not set" "${CONFIG_}$A" + ;; + + --module-after|-M) + set_var "${CONFIG_}$B" "${CONFIG_}$B=m" "${CONFIG_}$A" + ;; + + # undocumented because it ignores --file (fixme) + --refresh) + yes "" | make oldconfig + ;; + + *) + usage + ;; + esac +done diff --git a/src/net/scripts/const_structs.checkpatch b/src/net/scripts/const_structs.checkpatch new file mode 100644 index 0000000..1aae4f4 --- /dev/null +++ b/src/net/scripts/const_structs.checkpatch @@ -0,0 +1,68 @@ +acpi_dock_ops +address_space_operations +backlight_ops +block_device_operations +clk_ops +comedi_lrange +component_ops +dentry_operations +dev_pm_ops +dma_map_ops +driver_info +drm_connector_funcs +drm_encoder_funcs +drm_encoder_helper_funcs +ethtool_ops +extent_io_ops +file_lock_operations +file_operations +hv_ops +ide_dma_ops +ide_port_ops +inode_operations +intel_dvo_dev_ops +irq_domain_ops +item_operations +iwl_cfg +iwl_ops +kgdb_arch +kgdb_io +kset_uevent_ops +lock_manager_operations +machine_desc +microcode_ops +mlxsw_reg_info +mtrr_ops +neigh_ops +net_device_ops +nlmsvc_binding +nvkm_device_chip +of_device_id +pci_raw_ops +phy_ops +pinctrl_ops +pinmux_ops +pipe_buf_operations +platform_hibernation_ops +platform_suspend_ops +proto_ops +regmap_access_table +regulator_ops +rpc_pipe_ops +rtc_class_ops +sd_desc +seq_operations +sirfsoc_padmux +snd_ac97_build_ops +snd_soc_component_driver +soc_pcmcia_socket_ops +stacktrace_ops +sysfs_ops +tty_operations +uart_ops +usb_mon_operations +v4l2_ctrl_ops +v4l2_ioctl_ops +vm_operations_struct +wacom_features +wd_ops diff --git a/src/net/scripts/decode_stacktrace.sh b/src/net/scripts/decode_stacktrace.sh new file mode 100755 index 0000000..9039834 --- /dev/null +++ b/src/net/scripts/decode_stacktrace.sh @@ -0,0 +1,225 @@ +#!/bin/bash +# SPDX-License-Identifier: GPL-2.0 +# (c) 2014, Sasha Levin <sasha.levin@oracle.com> +#set -x + +if [[ $# < 1 ]]; then + echo "Usage:" + echo " $0 -r <release> | <vmlinux> [base path] [modules path]" + exit 1 +fi + +if [[ $1 == "-r" ]] ; then + vmlinux="" + basepath="auto" + modpath="" + release=$2 + + for fn in {,/usr/lib/debug}/boot/vmlinux-$release{,.debug} /lib/modules/$release{,/build}/vmlinux ; do + if [ -e "$fn" ] ; then + vmlinux=$fn + break + fi + done + + if [[ $vmlinux == "" ]] ; then + echo "ERROR! vmlinux image for release $release is not found" >&2 + exit 2 + fi +else + vmlinux=$1 + basepath=${2-auto} + modpath=$3 + release="" +fi + +declare -A cache +declare -A modcache + +find_module() { + if [[ "$modpath" != "" ]] ; then + for fn in $(find "$modpath" -name "${module//_/[-_]}.ko*") ; do + if readelf -WS "$fn" | grep -qwF .debug_line ; then + echo $fn + return + fi + done + return 1 + fi + + modpath=$(dirname "$vmlinux") + find_module && return + + if [[ $release == "" ]] ; then + release=$(gdb -ex 'print init_uts_ns.name.release' -ex 'quit' -quiet -batch "$vmlinux" | sed -n 's/\$1 = "\(.*\)".*/\1/p') + fi + + for dn in {/usr/lib/debug,}/lib/modules/$release ; do + if [ -e "$dn" ] ; then + modpath="$dn" + find_module && return + fi + done + + modpath="" + return 1 +} + +parse_symbol() { + # The structure of symbol at this point is: + # ([name]+[offset]/[total length]) + # + # For example: + # do_basic_setup+0x9c/0xbf + + if [[ $module == "" ]] ; then + local objfile=$vmlinux + elif [[ "${modcache[$module]+isset}" == "isset" ]]; then + local objfile=${modcache[$module]} + else + local objfile=$(find_module) + if [[ $objfile == "" ]] ; then + echo "WARNING! Modules path isn't set, but is needed to parse this symbol" >&2 + return + fi + modcache[$module]=$objfile + fi + + # Remove the englobing parenthesis + symbol=${symbol#\(} + symbol=${symbol%\)} + + # Strip segment + local segment + if [[ $symbol == *:* ]] ; then + segment=${symbol%%:*}: + symbol=${symbol#*:} + fi + + # Strip the symbol name so that we could look it up + local name=${symbol%+*} + + # Use 'nm vmlinux' to figure out the base address of said symbol. + # It's actually faster to call it every time than to load it + # all into bash. + if [[ "${cache[$module,$name]+isset}" == "isset" ]]; then + local base_addr=${cache[$module,$name]} + else + local base_addr=$(nm "$objfile" | awk '$3 == "'$name'" && ($2 == "t" || $2 == "T") {print $1; exit}') + if [[ $base_addr == "" ]] ; then + # address not found + return + fi + cache[$module,$name]="$base_addr" + fi + # Let's start doing the math to get the exact address into the + # symbol. First, strip out the symbol total length. + local expr=${symbol%/*} + + # Now, replace the symbol name with the base address we found + # before. + expr=${expr/$name/0x$base_addr} + + # Evaluate it to find the actual address + expr=$((expr)) + local address=$(printf "%x\n" "$expr") + + # Pass it to addr2line to get filename and line number + # Could get more than one result + if [[ "${cache[$module,$address]+isset}" == "isset" ]]; then + local code=${cache[$module,$address]} + else + local code=$(${CROSS_COMPILE}addr2line -i -e "$objfile" "$address") + cache[$module,$address]=$code + fi + + # addr2line doesn't return a proper error code if it fails, so + # we detect it using the value it prints so that we could preserve + # the offset/size into the function and bail out + if [[ $code == "??:0" ]]; then + return + fi + + # Strip out the base of the path on each line + code=$(while read -r line; do echo "${line#$basepath/}"; done <<< "$code") + + # In the case of inlines, move everything to same line + code=${code//$'\n'/' '} + + # Replace old address with pretty line numbers + symbol="$segment$name ($code)" +} + +decode_code() { + local scripts=`dirname "${BASH_SOURCE[0]}"` + + echo "$1" | $scripts/decodecode +} + +handle_line() { + local words + + # Tokenize + read -a words <<<"$1" + + # Remove hex numbers. Do it ourselves until it happens in the + # kernel + + # We need to know the index of the last element before we + # remove elements because arrays are sparse + local last=$(( ${#words[@]} - 1 )) + + for i in "${!words[@]}"; do + # Remove the address + if [[ ${words[$i]} =~ \[\<([^]]+)\>\] ]]; then + unset words[$i] + fi + + # Format timestamps with tabs + if [[ ${words[$i]} == \[ && ${words[$i+1]} == *\] ]]; then + unset words[$i] + words[$i+1]=$(printf "[%13s\n" "${words[$i+1]}") + fi + done + + if [[ ${words[$last]} =~ \[([^]]+)\] ]]; then + module=${words[$last]} + module=${module#\[} + module=${module%\]} + symbol=${words[$last-1]} + unset words[$last-1] + else + # The symbol is the last element, process it + symbol=${words[$last]} + module= + fi + + unset words[$last] + parse_symbol # modifies $symbol + + # Add up the line number to the symbol + echo "${words[@]}" "$symbol $module" +} + +if [[ $basepath == "auto" ]] ; then + module="" + symbol="kernel_init+0x0/0x0" + parse_symbol + basepath=${symbol#kernel_init (} + basepath=${basepath%/init/main.c:*)} +fi + +while read line; do + # Let's see if we have an address in the line + if [[ $line =~ \[\<([^]]+)\>\] ]] || + [[ $line =~ [^+\ ]+\+0x[0-9a-f]+/0x[0-9a-f]+ ]]; then + # Translate address to line numbers + handle_line "$line" + # Is it a code line? + elif [[ $line == *Code:* ]]; then + decode_code "$line" + else + # Nothing special in this line, show it as is + echo "$line" + fi +done diff --git a/src/net/scripts/decodecode b/src/net/scripts/decodecode new file mode 100755 index 0000000..31d884e --- /dev/null +++ b/src/net/scripts/decodecode @@ -0,0 +1,147 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0 +# Disassemble the Code: line in Linux oopses +# usage: decodecode < oops.file +# +# options: set env. variable AFLAGS=options to pass options to "as"; +# e.g., to decode an i386 oops on an x86_64 system, use: +# AFLAGS=--32 decodecode < 386.oops +# PC=hex - the PC (program counter) the oops points to + +cleanup() { + rm -f $T $T.s $T.o $T.oo $T.aa $T.dis + exit 1 +} + +die() { + echo "$@" + exit 1 +} + +trap cleanup EXIT + +T=`mktemp` || die "cannot create temp file" +code= +cont= + +while read i ; do + +case "$i" in +*Code:*) + code=$i + cont=yes + ;; +*) + [ -n "$cont" ] && { + xdump="$(echo $i | grep '^[[:xdigit:]<>[:space:]]\+$')" + if [ -n "$xdump" ]; then + code="$code $xdump" + else + cont= + fi + } + ;; +esac + +done + +if [ -z "$code" ]; then + rm $T + exit +fi + +echo $code +code=`echo $code | sed -e 's/.*Code: //'` + +width=`expr index "$code" ' '` +width=$((($width-1)/2)) +case $width in +1) type=byte ;; +2) type=2byte ;; +4) type=4byte ;; +esac + +if [ -z "$ARCH" ]; then + case `uname -m` in + aarch64*) ARCH=arm64 ;; + arm*) ARCH=arm ;; + esac +fi + +# Params: (tmp_file, pc_sub) +disas() { + t=$1 + pc_sub=$2 + + ${CROSS_COMPILE}as $AFLAGS -o $t.o $t.s > /dev/null 2>&1 + + if [ "$ARCH" = "arm" ]; then + if [ $width -eq 2 ]; then + OBJDUMPFLAGS="-M force-thumb" + fi + + ${CROSS_COMPILE}strip $t.o + fi + + if [ "$ARCH" = "arm64" ]; then + if [ $width -eq 4 ]; then + type=inst + fi + + ${CROSS_COMPILE}strip $t.o + fi + + if [ $pc_sub -ne 0 ]; then + if [ $PC ]; then + adj_vma=$(( $PC - $pc_sub )) + OBJDUMPFLAGS="$OBJDUMPFLAGS --adjust-vma=$adj_vma" + fi + fi + + ${CROSS_COMPILE}objdump $OBJDUMPFLAGS -S $t.o | \ + grep -v "/tmp\|Disassembly\|\.text\|^$" > $t.dis 2>&1 +} + +marker=`expr index "$code" "\<"` +if [ $marker -eq 0 ]; then + marker=`expr index "$code" "\("` +fi + + +touch $T.oo +if [ $marker -ne 0 ]; then + # 2 opcode bytes and a single space + pc_sub=$(( $marker / 3 )) + echo All code >> $T.oo + echo ======== >> $T.oo + beforemark=`echo "$code"` + echo -n " .$type 0x" > $T.s + echo $beforemark | sed -e 's/ /,0x/g; s/[<>()]//g' >> $T.s + disas $T $pc_sub + cat $T.dis >> $T.oo + rm -f $T.o $T.s $T.dis + +# and fix code at-and-after marker + code=`echo "$code" | cut -c$((${marker} + 1))-` +fi +echo Code starting with the faulting instruction > $T.aa +echo =========================================== >> $T.aa +code=`echo $code | sed -e 's/ [<(]/ /;s/[>)] / /;s/ /,0x/g; s/[>)]$//'` +echo -n " .$type 0x" > $T.s +echo $code >> $T.s +disas $T 0 +cat $T.dis >> $T.aa + +# (lines of whole $T.oo) - (lines of $T.aa, i.e. "Code starting") + 3, +# i.e. the title + the "===..=" line (sed is counting from 1, 0 address is +# special) +faultlinenum=$(( $(wc -l $T.oo | cut -d" " -f1) - \ + $(wc -l $T.aa | cut -d" " -f1) + 3)) + +faultline=`cat $T.dis | head -1 | cut -d":" -f2-` +faultline=`echo "$faultline" | sed -e 's/\[/\\\[/g; s/\]/\\\]/g'` + +cat $T.oo | sed -e "${faultlinenum}s/^\([^:]*:\)\(.*\)/\1\*\2\t\t<-- trapping instruction/" +echo +cat $T.aa +cleanup diff --git a/src/net/scripts/depmod.sh b/src/net/scripts/depmod.sh new file mode 100755 index 0000000..3643b4f --- /dev/null +++ b/src/net/scripts/depmod.sh @@ -0,0 +1,55 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0 +# +# A depmod wrapper used by the toplevel Makefile + +if test $# -ne 2; then + echo "Usage: $0 /sbin/depmod <kernelrelease>" >&2 + exit 1 +fi +DEPMOD=$1 +KERNELRELEASE=$2 + +if ! test -r System.map ; then + echo "Warning: modules_install: missing 'System.map' file. Skipping depmod." >&2 + exit 0 +fi + +# legacy behavior: "depmod" in /sbin, no /sbin in PATH +PATH="$PATH:/sbin" +if [ -z $(command -v $DEPMOD) ]; then + echo "Warning: 'make modules_install' requires $DEPMOD. Please install it." >&2 + echo "This is probably in the kmod package." >&2 + exit 0 +fi + +# older versions of depmod require the version string to start with three +# numbers, so we cheat with a symlink here +depmod_hack_needed=true +tmp_dir=$(mktemp -d ${TMPDIR:-/tmp}/depmod.XXXXXX) +mkdir -p "$tmp_dir/lib/modules/$KERNELRELEASE" +if "$DEPMOD" -b "$tmp_dir" $KERNELRELEASE 2>/dev/null; then + if test -e "$tmp_dir/lib/modules/$KERNELRELEASE/modules.dep" -o \ + -e "$tmp_dir/lib/modules/$KERNELRELEASE/modules.dep.bin"; then + depmod_hack_needed=false + fi +fi +rm -rf "$tmp_dir" +if $depmod_hack_needed; then + symlink="$INSTALL_MOD_PATH/lib/modules/99.98.$KERNELRELEASE" + ln -s "$KERNELRELEASE" "$symlink" + KERNELRELEASE=99.98.$KERNELRELEASE +fi + +set -- -ae -F System.map +if test -n "$INSTALL_MOD_PATH"; then + set -- "$@" -b "$INSTALL_MOD_PATH" +fi +"$DEPMOD" "$@" "$KERNELRELEASE" +ret=$? + +if $depmod_hack_needed; then + rm -f "$symlink" +fi + +exit $ret diff --git a/src/net/scripts/dev-needs.sh b/src/net/scripts/dev-needs.sh new file mode 100755 index 0000000..454cc30 --- /dev/null +++ b/src/net/scripts/dev-needs.sh @@ -0,0 +1,315 @@ +#! /bin/sh +# SPDX-License-Identifier: GPL-2.0 +# Copyright (c) 2020, Google LLC. All rights reserved. +# Author: Saravana Kannan <saravanak@google.com> + +function help() { + cat << EOF +Usage: $(basename $0) [-c|-d|-m|-f] [filter options] <list of devices> + +This script needs to be run on the target device once it has booted to a +shell. + +The script takes as input a list of one or more device directories under +/sys/devices and then lists the probe dependency chain (suppliers and +parents) of these devices. It does a breadth first search of the dependency +chain, so the last entry in the output is close to the root of the +dependency chain. + +By default it lists the full path to the devices under /sys/devices. + +It also takes an optional modifier flag as the first parameter to change +what information is listed in the output. If the requested information is +not available, the device name is printed. + + -c lists the compatible string of the dependencies + -d lists the driver name of the dependencies that have probed + -m lists the module name of the dependencies that have a module + -f list the firmware node path of the dependencies + -g list the dependencies as edges and nodes for graphviz + -t list the dependencies as edges for tsort + +The filter options provide a way to filter out some dependencies: + --allow-no-driver By default dependencies that don't have a driver + attached are ignored. This is to avoid following + device links to "class" devices that are created + when the consumer probes (as in, not a probe + dependency). If you want to follow these links + anyway, use this flag. + + --exclude-devlinks Don't follow device links when tracking probe + dependencies. + + --exclude-parents Don't follow parent devices when tracking probe + dependencies. + +EOF +} + +function dev_to_detail() { + local i=0 + while [ $i -lt ${#OUT_LIST[@]} ] + do + local C=${OUT_LIST[i]} + local S=${OUT_LIST[i+1]} + local D="'$(detail_chosen $C $S)'" + if [ ! -z "$D" ] + then + # This weirdness is needed to work with toybox when + # using the -t option. + printf '%05u\t%s\n' ${i} "$D" | tr -d \' + fi + i=$((i+2)) + done +} + +function already_seen() { + local i=0 + while [ $i -lt ${#OUT_LIST[@]} ] + do + if [ "$1" = "${OUT_LIST[$i]}" ] + then + # if-statement treats 0 (no-error) as true + return 0 + fi + i=$(($i+2)) + done + + # if-statement treats 1 (error) as false + return 1 +} + +# Return 0 (no-error/true) if parent was added +function add_parent() { + + if [ ${ALLOW_PARENTS} -eq 0 ] + then + return 1 + fi + + local CON=$1 + # $CON could be a symlink path. So, we need to find the real path and + # then go up one level to find the real parent. + local PARENT=$(realpath $CON/..) + + while [ ! -e ${PARENT}/driver ] + do + if [ "$PARENT" = "/sys/devices" ] + then + return 1 + fi + PARENT=$(realpath $PARENT/..) + done + + CONSUMERS+=($PARENT) + OUT_LIST+=(${CON} ${PARENT}) + return 0 +} + +# Return 0 (no-error/true) if one or more suppliers were added +function add_suppliers() { + local CON=$1 + local RET=1 + + if [ ${ALLOW_DEVLINKS} -eq 0 ] + then + return 1 + fi + + SUPPLIER_LINKS=$(ls -1d $CON/supplier:* 2>/dev/null) + for SL in $SUPPLIER_LINKS; + do + SYNC_STATE=$(cat $SL/sync_state_only) + + # sync_state_only links are proxy dependencies. + # They can also have cycles. So, don't follow them. + if [ "$SYNC_STATE" != '0' ] + then + continue + fi + + SUPPLIER=$(realpath $SL/supplier) + + if [ ! -e $SUPPLIER/driver -a ${ALLOW_NO_DRIVER} -eq 0 ] + then + continue + fi + + CONSUMERS+=($SUPPLIER) + OUT_LIST+=(${CON} ${SUPPLIER}) + RET=0 + done + + return $RET +} + +function detail_compat() { + f=$1/of_node/compatible + if [ -e $f ] + then + echo -n $(cat $f) + else + echo -n $1 + fi +} + +function detail_module() { + f=$1/driver/module + if [ -e $f ] + then + echo -n $(basename $(realpath $f)) + else + echo -n $1 + fi +} + +function detail_driver() { + f=$1/driver + if [ -e $f ] + then + echo -n $(basename $(realpath $f)) + else + echo -n $1 + fi +} + +function detail_fwnode() { + f=$1/firmware_node + if [ ! -e $f ] + then + f=$1/of_node + fi + + if [ -e $f ] + then + echo -n $(realpath $f) + else + echo -n $1 + fi +} + +function detail_graphviz() { + if [ "$2" != "ROOT" ] + then + echo -n "\"$(basename $2)\"->\"$(basename $1)\"" + else + echo -n "\"$(basename $1)\"" + fi +} + +function detail_tsort() { + echo -n "\"$2\" \"$1\"" +} + +function detail_device() { echo -n $1; } + +alias detail=detail_device +ALLOW_NO_DRIVER=0 +ALLOW_DEVLINKS=1 +ALLOW_PARENTS=1 + +while [ $# -gt 0 ] +do + ARG=$1 + case $ARG in + --help) + help + exit 0 + ;; + -c) + alias detail=detail_compat + ;; + -m) + alias detail=detail_module + ;; + -d) + alias detail=detail_driver + ;; + -f) + alias detail=detail_fwnode + ;; + -g) + alias detail=detail_graphviz + ;; + -t) + alias detail=detail_tsort + ;; + --allow-no-driver) + ALLOW_NO_DRIVER=1 + ;; + --exclude-devlinks) + ALLOW_DEVLINKS=0 + ;; + --exclude-parents) + ALLOW_PARENTS=0 + ;; + *) + # Stop at the first argument that's not an option. + break + ;; + esac + shift +done + +function detail_chosen() { + detail $1 $2 +} + +if [ $# -eq 0 ] +then + help + exit 1 +fi + +CONSUMERS=($@) +OUT_LIST=() + +# Do a breadth first, non-recursive tracking of suppliers. The parent is also +# considered a "supplier" as a device can't probe without its parent. +i=0 +while [ $i -lt ${#CONSUMERS[@]} ] +do + CONSUMER=$(realpath ${CONSUMERS[$i]}) + i=$(($i+1)) + + if already_seen ${CONSUMER} + then + continue + fi + + # If this is not a device with a driver, we don't care about its + # suppliers. + if [ ! -e ${CONSUMER}/driver -a ${ALLOW_NO_DRIVER} -eq 0 ] + then + continue + fi + + ROOT=1 + + # Add suppliers to CONSUMERS list and output the consumer details. + # + # We don't need to worry about a cycle in the dependency chain causing + # infinite loops. That's because the kernel doesn't allow cycles in + # device links unless it's a sync_state_only device link. And we ignore + # sync_state_only device links inside add_suppliers. + if add_suppliers ${CONSUMER} + then + ROOT=0 + fi + + if add_parent ${CONSUMER} + then + ROOT=0 + fi + + if [ $ROOT -eq 1 ] + then + OUT_LIST+=(${CONSUMER} "ROOT") + fi +done + +# Can NOT combine sort and uniq using sort -suk2 because stable sort in toybox +# isn't really stable. +dev_to_detail | sort -k2 -k1 | uniq -f 1 | sort | cut -f2- + +exit 0 diff --git a/src/net/scripts/diffconfig b/src/net/scripts/diffconfig new file mode 100755 index 0000000..d5da5fa --- /dev/null +++ b/src/net/scripts/diffconfig @@ -0,0 +1,132 @@ +#!/usr/bin/env python3 +# SPDX-License-Identifier: GPL-2.0 +# +# diffconfig - a tool to compare .config files. +# +# originally written in 2006 by Matt Mackall +# (at least, this was in his bloatwatch source code) +# last worked on 2008 by Tim Bird +# + +import sys, os + +def usage(): + print("""Usage: diffconfig [-h] [-m] [<config1> <config2>] + +Diffconfig is a simple utility for comparing two .config files. +Using standard diff to compare .config files often includes extraneous and +distracting information. This utility produces sorted output with only the +changes in configuration values between the two files. + +Added and removed items are shown with a leading plus or minus, respectively. +Changed items show the old and new values on a single line. + +If -m is specified, then output will be in "merge" style, which has the +changed and new values in kernel config option format. + +If no config files are specified, .config and .config.old are used. + +Example usage: + $ diffconfig .config config-with-some-changes +-EXT2_FS_XATTR n + CRAMFS n -> y + EXT2_FS y -> n + LOG_BUF_SHIFT 14 -> 16 + PRINTK_TIME n -> y +""") + sys.exit(0) + +# returns a dictionary of name/value pairs for config items in the file +def readconfig(config_file): + d = {} + for line in config_file: + line = line[:-1] + if line[:7] == "CONFIG_": + name, val = line[7:].split("=", 1) + d[name] = val + if line[-11:] == " is not set": + d[line[9:-11]] = "n" + return d + +def print_config(op, config, value, new_value): + global merge_style + + if merge_style: + if new_value: + if new_value=="n": + print("# CONFIG_%s is not set" % config) + else: + print("CONFIG_%s=%s" % (config, new_value)) + else: + if op=="-": + print("-%s %s" % (config, value)) + elif op=="+": + print("+%s %s" % (config, new_value)) + else: + print(" %s %s -> %s" % (config, value, new_value)) + +def main(): + global merge_style + + # parse command line args + if ("-h" in sys.argv or "--help" in sys.argv): + usage() + + merge_style = 0 + if "-m" in sys.argv: + merge_style = 1 + sys.argv.remove("-m") + + argc = len(sys.argv) + if not (argc==1 or argc == 3): + print("Error: incorrect number of arguments or unrecognized option") + usage() + + if argc == 1: + # if no filenames given, assume .config and .config.old + build_dir="" + if "KBUILD_OUTPUT" in os.environ: + build_dir = os.environ["KBUILD_OUTPUT"]+"/" + configa_filename = build_dir + ".config.old" + configb_filename = build_dir + ".config" + else: + configa_filename = sys.argv[1] + configb_filename = sys.argv[2] + + try: + a = readconfig(open(configa_filename)) + b = readconfig(open(configb_filename)) + except (IOError): + e = sys.exc_info()[1] + print("I/O error[%s]: %s\n" % (e.args[0],e.args[1])) + usage() + + # print items in a but not b (accumulate, sort and print) + old = [] + for config in a: + if config not in b: + old.append(config) + old.sort() + for config in old: + print_config("-", config, a[config], None) + del a[config] + + # print items that changed (accumulate, sort, and print) + changed = [] + for config in a: + if a[config] != b[config]: + changed.append(config) + else: + del b[config] + changed.sort() + for config in changed: + print_config("->", config, a[config], b[config]) + del b[config] + + # now print items in b but not in a + # (items from b that were in a were removed above) + new = sorted(b.keys()) + for config in new: + print_config("+", config, None, b[config]) + +main() diff --git a/src/net/scripts/documentation-file-ref-check b/src/net/scripts/documentation-file-ref-check new file mode 100755 index 0000000..c71832b --- /dev/null +++ b/src/net/scripts/documentation-file-ref-check @@ -0,0 +1,241 @@ +#!/usr/bin/env perl +# SPDX-License-Identifier: GPL-2.0 +# +# Treewide grep for references to files under Documentation, and report +# non-existing files in stderr. + +use warnings; +use strict; +use Getopt::Long qw(:config no_auto_abbrev); + +# NOTE: only add things here when the file was gone, but the text wants +# to mention a past documentation file, for example, to give credits for +# the original work. +my %false_positives = ( + "Documentation/scsi/scsi_mid_low_api.rst" => "Documentation/Configure.help", + "drivers/vhost/vhost.c" => "Documentation/virtual/lguest/lguest.c", +); + +my $scriptname = $0; +$scriptname =~ s,.*/([^/]+/),$1,; + +# Parse arguments +my $help = 0; +my $fix = 0; +my $warn = 0; + +if (! -d ".git") { + printf "Warning: can't check if file exists, as this is not a git tree\n"; + exit 0; +} + +GetOptions( + 'fix' => \$fix, + 'warn' => \$warn, + 'h|help|usage' => \$help, +); + +if ($help != 0) { + print "$scriptname [--help] [--fix]\n"; + exit -1; +} + +# Step 1: find broken references +print "Finding broken references. This may take a while... " if ($fix); + +my %broken_ref; + +my $doc_fix = 0; + +open IN, "git grep ':doc:\`' Documentation/|" + or die "Failed to run git grep"; +while (<IN>) { + next if (!m,^([^:]+):.*\:doc\:\`([^\`]+)\`,); + next if (m,sphinx/,); + + my $file = $1; + my $d = $1; + my $doc_ref = $2; + + my $f = $doc_ref; + + $d =~ s,(.*/).*,$1,; + $f =~ s,.*\<([^\>]+)\>,$1,; + + if ($f =~ m,^/,) { + $f = "$f.rst"; + $f =~ s,^/,Documentation/,; + } else { + $f = "$d$f.rst"; + } + + next if (grep -e, glob("$f")); + + if ($fix && !$doc_fix) { + print STDERR "\nWARNING: Currently, can't fix broken :doc:`` fields\n"; + } + $doc_fix++; + + print STDERR "$file: :doc:`$doc_ref`\n"; +} +close IN; + +open IN, "git grep 'Documentation/'|" + or die "Failed to run git grep"; +while (<IN>) { + next if (!m/^([^:]+):(.*)/); + + my $f = $1; + my $ln = $2; + + # On linux-next, discard the Next/ directory + next if ($f =~ m,^Next/,); + + # Makefiles and scripts contain nasty expressions to parse docs + next if ($f =~ m/Makefile/ || $f =~ m/\.sh$/); + + # Skip this script + next if ($f eq $scriptname); + + # Ignore the dir where documentation will be built + next if ($ln =~ m,\b(\S*)Documentation/output,); + + if ($ln =~ m,\b(\S*)(Documentation/[A-Za-z0-9\_\.\,\~/\*\[\]\?+-]*)(.*),) { + my $prefix = $1; + my $ref = $2; + my $base = $2; + my $extra = $3; + + # some file references are like: + # /usr/src/linux/Documentation/DMA-{API,mapping}.txt + # For now, ignore them + next if ($extra =~ m/^{/); + + # Remove footnotes at the end like: + # Documentation/devicetree/dt-object-internal.txt[1] + $ref =~ s/(txt|rst)\[\d+]$/$1/; + + # Remove ending ']' without any '[' + $ref =~ s/\].*// if (!($ref =~ m/\[/)); + + # Remove puntuation marks at the end + $ref =~ s/[\,\.]+$//; + + my $fulref = "$prefix$ref"; + + $fulref =~ s/^(\<file|ref)://; + $fulref =~ s/^[\'\`]+//; + $fulref =~ s,^\$\(.*\)/,,; + $base =~ s,.*/,,; + + # Remove URL false-positives + next if ($fulref =~ m/^http/); + + # Remove sched-pelt false-positive + next if ($fulref =~ m,^Documentation/scheduler/sched-pelt$,); + + # Discard some build examples from Documentation/target/tcm_mod_builder.rst + next if ($fulref =~ m,mnt/sdb/lio-core-2.6.git/Documentation/target,); + + # Check if exists, evaluating wildcards + next if (grep -e, glob("$ref $fulref")); + + # Accept relative Documentation patches for tools/ + if ($f =~ m/tools/) { + my $path = $f; + $path =~ s,(.*)/.*,$1,; + next if (grep -e, glob("$path/$ref $path/../$ref $path/$fulref")); + } + + # Discard known false-positives + if (defined($false_positives{$f})) { + next if ($false_positives{$f} eq $fulref); + } + + if ($fix) { + if (!($ref =~ m/(scripts|Kconfig|Kbuild)/)) { + $broken_ref{$ref}++; + } + } elsif ($warn) { + print STDERR "Warning: $f references a file that doesn't exist: $fulref\n"; + } else { + print STDERR "$f: $fulref\n"; + } + } +} +close IN; + +exit 0 if (!$fix); + +# Step 2: Seek for file name alternatives +print "Auto-fixing broken references. Please double-check the results\n"; + +foreach my $ref (keys %broken_ref) { + my $new =$ref; + + my $basedir = "."; + # On translations, only seek inside the translations directory + $basedir = $1 if ($ref =~ m,(Documentation/translations/[^/]+),); + + # get just the basename + $new =~ s,.*/,,; + + my $f=""; + + # usual reason for breakage: DT file moved around + if ($ref =~ /devicetree/) { + # usual reason for breakage: DT file renamed to .yaml + if (!$f) { + my $new_ref = $ref; + $new_ref =~ s/\.txt$/.yaml/; + $f=$new_ref if (-f $new_ref); + } + + if (!$f) { + my $search = $new; + $search =~ s,^.*/,,; + $f = qx(find Documentation/devicetree/ -iname "*$search*") if ($search); + if (!$f) { + # Manufacturer name may have changed + $search =~ s/^.*,//; + $f = qx(find Documentation/devicetree/ -iname "*$search*") if ($search); + } + } + } + + # usual reason for breakage: file renamed to .rst + if (!$f) { + $new =~ s/\.txt$/.rst/; + $f=qx(find $basedir -iname $new) if ($new); + } + + # usual reason for breakage: use dash or underline + if (!$f) { + $new =~ s/[-_]/[-_]/g; + $f=qx(find $basedir -iname $new) if ($new); + } + + # Wild guess: seek for the same name on another place + if (!$f) { + $f = qx(find $basedir -iname $new) if ($new); + } + + my @find = split /\s+/, $f; + + if (!$f) { + print STDERR "ERROR: Didn't find a replacement for $ref\n"; + } elsif (scalar(@find) > 1) { + print STDERR "WARNING: Won't auto-replace, as found multiple files close to $ref:\n"; + foreach my $j (@find) { + $j =~ s,^./,,; + print STDERR " $j\n"; + } + } else { + $f = $find[0]; + $f =~ s,^./,,; + print "INFO: Replacing $ref to $f\n"; + foreach my $j (qx(git grep -l $ref)) { + qx(sed "s\@$ref\@$f\@g" -i $j); + } + } +} diff --git a/src/net/scripts/dtc/.gitignore b/src/net/scripts/dtc/.gitignore new file mode 100644 index 0000000..b814e60 --- /dev/null +++ b/src/net/scripts/dtc/.gitignore @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +dtc diff --git a/src/net/scripts/dtc/Makefile b/src/net/scripts/dtc/Makefile new file mode 100644 index 0000000..f1d2017 --- /dev/null +++ b/src/net/scripts/dtc/Makefile @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: GPL-2.0 +# scripts/dtc makefile + +hostprogs-always-$(CONFIG_DTC) += dtc +hostprogs-always-$(CHECK_DT_BINDING) += dtc + +dtc-objs := dtc.o flattree.o fstree.o data.o livetree.o treesource.o \ + srcpos.o checks.o util.o +dtc-objs += dtc-lexer.lex.o dtc-parser.tab.o + +# Source files need to get at the userspace version of libfdt_env.h to compile +HOST_EXTRACFLAGS += -I $(srctree)/$(src)/libfdt + +ifeq ($(shell pkg-config --exists yaml-0.1 2>/dev/null && echo yes),) +ifneq ($(CHECK_DT_BINDING)$(CHECK_DTBS),) +$(error dtc needs libyaml for DT schema validation support. \ + Install the necessary libyaml development package.) +endif +HOST_EXTRACFLAGS += -DNO_YAML +else +dtc-objs += yamltree.o +# To include <yaml.h> installed in a non-default path +HOSTCFLAGS_yamltree.o := $(shell pkg-config --cflags yaml-0.1) +# To link libyaml installed in a non-default path +HOSTLDLIBS_dtc := $(shell pkg-config --libs yaml-0.1) +endif + +# Generated files need one more search path to include headers in source tree +HOSTCFLAGS_dtc-lexer.lex.o := -I $(srctree)/$(src) +HOSTCFLAGS_dtc-parser.tab.o := -I $(srctree)/$(src) + +# dependencies on generated files need to be listed explicitly +$(obj)/dtc-lexer.lex.o: $(obj)/dtc-parser.tab.h diff --git a/src/net/scripts/dtc/checks.c b/src/net/scripts/dtc/checks.c new file mode 100644 index 0000000..17cb689 --- /dev/null +++ b/src/net/scripts/dtc/checks.c @@ -0,0 +1,1953 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (C) Copyright David Gibson <dwg@au1.ibm.com>, IBM Corporation. 2007. + */ + +#include "dtc.h" +#include "srcpos.h" + +#ifdef TRACE_CHECKS +#define TRACE(c, ...) \ + do { \ + fprintf(stderr, "=== %s: ", (c)->name); \ + fprintf(stderr, __VA_ARGS__); \ + fprintf(stderr, "\n"); \ + } while (0) +#else +#define TRACE(c, fmt, ...) do { } while (0) +#endif + +enum checkstatus { + UNCHECKED = 0, + PREREQ, + PASSED, + FAILED, +}; + +struct check; + +typedef void (*check_fn)(struct check *c, struct dt_info *dti, struct node *node); + +struct check { + const char *name; + check_fn fn; + void *data; + bool warn, error; + enum checkstatus status; + bool inprogress; + int num_prereqs; + struct check **prereq; +}; + +#define CHECK_ENTRY(nm_, fn_, d_, w_, e_, ...) \ + static struct check *nm_##_prereqs[] = { __VA_ARGS__ }; \ + static struct check nm_ = { \ + .name = #nm_, \ + .fn = (fn_), \ + .data = (d_), \ + .warn = (w_), \ + .error = (e_), \ + .status = UNCHECKED, \ + .num_prereqs = ARRAY_SIZE(nm_##_prereqs), \ + .prereq = nm_##_prereqs, \ + }; +#define WARNING(nm_, fn_, d_, ...) \ + CHECK_ENTRY(nm_, fn_, d_, true, false, __VA_ARGS__) +#define ERROR(nm_, fn_, d_, ...) \ + CHECK_ENTRY(nm_, fn_, d_, false, true, __VA_ARGS__) +#define CHECK(nm_, fn_, d_, ...) \ + CHECK_ENTRY(nm_, fn_, d_, false, false, __VA_ARGS__) + +static inline void PRINTF(5, 6) check_msg(struct check *c, struct dt_info *dti, + struct node *node, + struct property *prop, + const char *fmt, ...) +{ + va_list ap; + char *str = NULL; + struct srcpos *pos = NULL; + char *file_str; + + if (!(c->warn && (quiet < 1)) && !(c->error && (quiet < 2))) + return; + + if (prop && prop->srcpos) + pos = prop->srcpos; + else if (node && node->srcpos) + pos = node->srcpos; + + if (pos) { + file_str = srcpos_string(pos); + xasprintf(&str, "%s", file_str); + free(file_str); + } else if (streq(dti->outname, "-")) { + xasprintf(&str, "<stdout>"); + } else { + xasprintf(&str, "%s", dti->outname); + } + + xasprintf_append(&str, ": %s (%s): ", + (c->error) ? "ERROR" : "Warning", c->name); + + if (node) { + if (prop) + xasprintf_append(&str, "%s:%s: ", node->fullpath, prop->name); + else + xasprintf_append(&str, "%s: ", node->fullpath); + } + + va_start(ap, fmt); + xavsprintf_append(&str, fmt, ap); + va_end(ap); + + xasprintf_append(&str, "\n"); + + if (!prop && pos) { + pos = node->srcpos; + while (pos->next) { + pos = pos->next; + + file_str = srcpos_string(pos); + xasprintf_append(&str, " also defined at %s\n", file_str); + free(file_str); + } + } + + fputs(str, stderr); +} + +#define FAIL(c, dti, node, ...) \ + do { \ + TRACE((c), "\t\tFAILED at %s:%d", __FILE__, __LINE__); \ + (c)->status = FAILED; \ + check_msg((c), dti, node, NULL, __VA_ARGS__); \ + } while (0) + +#define FAIL_PROP(c, dti, node, prop, ...) \ + do { \ + TRACE((c), "\t\tFAILED at %s:%d", __FILE__, __LINE__); \ + (c)->status = FAILED; \ + check_msg((c), dti, node, prop, __VA_ARGS__); \ + } while (0) + + +static void check_nodes_props(struct check *c, struct dt_info *dti, struct node *node) +{ + struct node *child; + + TRACE(c, "%s", node->fullpath); + if (c->fn) + c->fn(c, dti, node); + + for_each_child(node, child) + check_nodes_props(c, dti, child); +} + +static bool run_check(struct check *c, struct dt_info *dti) +{ + struct node *dt = dti->dt; + bool error = false; + int i; + + assert(!c->inprogress); + + if (c->status != UNCHECKED) + goto out; + + c->inprogress = true; + + for (i = 0; i < c->num_prereqs; i++) { + struct check *prq = c->prereq[i]; + error = error || run_check(prq, dti); + if (prq->status != PASSED) { + c->status = PREREQ; + check_msg(c, dti, NULL, NULL, "Failed prerequisite '%s'", + c->prereq[i]->name); + } + } + + if (c->status != UNCHECKED) + goto out; + + check_nodes_props(c, dti, dt); + + if (c->status == UNCHECKED) + c->status = PASSED; + + TRACE(c, "\tCompleted, status %d", c->status); + +out: + c->inprogress = false; + if ((c->status != PASSED) && (c->error)) + error = true; + return error; +} + +/* + * Utility check functions + */ + +/* A check which always fails, for testing purposes only */ +static inline void check_always_fail(struct check *c, struct dt_info *dti, + struct node *node) +{ + FAIL(c, dti, node, "always_fail check"); +} +CHECK(always_fail, check_always_fail, NULL); + +static void check_is_string(struct check *c, struct dt_info *dti, + struct node *node) +{ + struct property *prop; + char *propname = c->data; + + prop = get_property(node, propname); + if (!prop) + return; /* Not present, assumed ok */ + + if (!data_is_one_string(prop->val)) + FAIL_PROP(c, dti, node, prop, "property is not a string"); +} +#define WARNING_IF_NOT_STRING(nm, propname) \ + WARNING(nm, check_is_string, (propname)) +#define ERROR_IF_NOT_STRING(nm, propname) \ + ERROR(nm, check_is_string, (propname)) + +static void check_is_string_list(struct check *c, struct dt_info *dti, + struct node *node) +{ + int rem, l; + struct property *prop; + char *propname = c->data; + char *str; + + prop = get_property(node, propname); + if (!prop) + return; /* Not present, assumed ok */ + + str = prop->val.val; + rem = prop->val.len; + while (rem > 0) { + l = strnlen(str, rem); + if (l == rem) { + FAIL_PROP(c, dti, node, prop, "property is not a string list"); + break; + } + rem -= l + 1; + str += l + 1; + } +} +#define WARNING_IF_NOT_STRING_LIST(nm, propname) \ + WARNING(nm, check_is_string_list, (propname)) +#define ERROR_IF_NOT_STRING_LIST(nm, propname) \ + ERROR(nm, check_is_string_list, (propname)) + +static void check_is_cell(struct check *c, struct dt_info *dti, + struct node *node) +{ + struct property *prop; + char *propname = c->data; + + prop = get_property(node, propname); + if (!prop) + return; /* Not present, assumed ok */ + + if (prop->val.len != sizeof(cell_t)) + FAIL_PROP(c, dti, node, prop, "property is not a single cell"); +} +#define WARNING_IF_NOT_CELL(nm, propname) \ + WARNING(nm, check_is_cell, (propname)) +#define ERROR_IF_NOT_CELL(nm, propname) \ + ERROR(nm, check_is_cell, (propname)) + +/* + * Structural check functions + */ + +static void check_duplicate_node_names(struct check *c, struct dt_info *dti, + struct node *node) +{ + struct node *child, *child2; + + for_each_child(node, child) + for (child2 = child->next_sibling; + child2; + child2 = child2->next_sibling) + if (streq(child->name, child2->name)) + FAIL(c, dti, child2, "Duplicate node name"); +} +ERROR(duplicate_node_names, check_duplicate_node_names, NULL); + +static void check_duplicate_property_names(struct check *c, struct dt_info *dti, + struct node *node) +{ + struct property *prop, *prop2; + + for_each_property(node, prop) { + for (prop2 = prop->next; prop2; prop2 = prop2->next) { + if (prop2->deleted) + continue; + if (streq(prop->name, prop2->name)) + FAIL_PROP(c, dti, node, prop, "Duplicate property name"); + } + } +} +ERROR(duplicate_property_names, check_duplicate_property_names, NULL); + +#define LOWERCASE "abcdefghijklmnopqrstuvwxyz" +#define UPPERCASE "ABCDEFGHIJKLMNOPQRSTUVWXYZ" +#define DIGITS "0123456789" +#define PROPNODECHARS LOWERCASE UPPERCASE DIGITS ",._+*#?-" +#define PROPNODECHARSSTRICT LOWERCASE UPPERCASE DIGITS ",-" + +static void check_node_name_chars(struct check *c, struct dt_info *dti, + struct node *node) +{ + int n = strspn(node->name, c->data); + + if (n < strlen(node->name)) + FAIL(c, dti, node, "Bad character '%c' in node name", + node->name[n]); +} +ERROR(node_name_chars, check_node_name_chars, PROPNODECHARS "@"); + +static void check_node_name_chars_strict(struct check *c, struct dt_info *dti, + struct node *node) +{ + int n = strspn(node->name, c->data); + + if (n < node->basenamelen) + FAIL(c, dti, node, "Character '%c' not recommended in node name", + node->name[n]); +} +CHECK(node_name_chars_strict, check_node_name_chars_strict, PROPNODECHARSSTRICT); + +static void check_node_name_format(struct check *c, struct dt_info *dti, + struct node *node) +{ + if (strchr(get_unitname(node), '@')) + FAIL(c, dti, node, "multiple '@' characters in node name"); +} +ERROR(node_name_format, check_node_name_format, NULL, &node_name_chars); + +static void check_unit_address_vs_reg(struct check *c, struct dt_info *dti, + struct node *node) +{ + const char *unitname = get_unitname(node); + struct property *prop = get_property(node, "reg"); + + if (get_subnode(node, "__overlay__")) { + /* HACK: Overlay fragments are a special case */ + return; + } + + if (!prop) { + prop = get_property(node, "ranges"); + if (prop && !prop->val.len) + prop = NULL; + } + + if (prop) { + if (!unitname[0]) + FAIL(c, dti, node, "node has a reg or ranges property, but no unit name"); + } else { + if (unitname[0]) + FAIL(c, dti, node, "node has a unit name, but no reg or ranges property"); + } +} +WARNING(unit_address_vs_reg, check_unit_address_vs_reg, NULL); + +static void check_property_name_chars(struct check *c, struct dt_info *dti, + struct node *node) +{ + struct property *prop; + + for_each_property(node, prop) { + int n = strspn(prop->name, c->data); + + if (n < strlen(prop->name)) + FAIL_PROP(c, dti, node, prop, "Bad character '%c' in property name", + prop->name[n]); + } +} +ERROR(property_name_chars, check_property_name_chars, PROPNODECHARS); + +static void check_property_name_chars_strict(struct check *c, + struct dt_info *dti, + struct node *node) +{ + struct property *prop; + + for_each_property(node, prop) { + const char *name = prop->name; + int n = strspn(name, c->data); + + if (n == strlen(prop->name)) + continue; + + /* Certain names are whitelisted */ + if (streq(name, "device_type")) + continue; + + /* + * # is only allowed at the beginning of property names not counting + * the vendor prefix. + */ + if (name[n] == '#' && ((n == 0) || (name[n-1] == ','))) { + name += n + 1; + n = strspn(name, c->data); + } + if (n < strlen(name)) + FAIL_PROP(c, dti, node, prop, "Character '%c' not recommended in property name", + name[n]); + } +} +CHECK(property_name_chars_strict, check_property_name_chars_strict, PROPNODECHARSSTRICT); + +#define DESCLABEL_FMT "%s%s%s%s%s" +#define DESCLABEL_ARGS(node,prop,mark) \ + ((mark) ? "value of " : ""), \ + ((prop) ? "'" : ""), \ + ((prop) ? (prop)->name : ""), \ + ((prop) ? "' in " : ""), (node)->fullpath + +static void check_duplicate_label(struct check *c, struct dt_info *dti, + const char *label, struct node *node, + struct property *prop, struct marker *mark) +{ + struct node *dt = dti->dt; + struct node *othernode = NULL; + struct property *otherprop = NULL; + struct marker *othermark = NULL; + + othernode = get_node_by_label(dt, label); + + if (!othernode) + otherprop = get_property_by_label(dt, label, &othernode); + if (!othernode) + othermark = get_marker_label(dt, label, &othernode, + &otherprop); + + if (!othernode) + return; + + if ((othernode != node) || (otherprop != prop) || (othermark != mark)) + FAIL(c, dti, node, "Duplicate label '%s' on " DESCLABEL_FMT + " and " DESCLABEL_FMT, + label, DESCLABEL_ARGS(node, prop, mark), + DESCLABEL_ARGS(othernode, otherprop, othermark)); +} + +static void check_duplicate_label_node(struct check *c, struct dt_info *dti, + struct node *node) +{ + struct label *l; + struct property *prop; + + for_each_label(node->labels, l) + check_duplicate_label(c, dti, l->label, node, NULL, NULL); + + for_each_property(node, prop) { + struct marker *m = prop->val.markers; + + for_each_label(prop->labels, l) + check_duplicate_label(c, dti, l->label, node, prop, NULL); + + for_each_marker_of_type(m, LABEL) + check_duplicate_label(c, dti, m->ref, node, prop, m); + } +} +ERROR(duplicate_label, check_duplicate_label_node, NULL); + +static cell_t check_phandle_prop(struct check *c, struct dt_info *dti, + struct node *node, const char *propname) +{ + struct node *root = dti->dt; + struct property *prop; + struct marker *m; + cell_t phandle; + + prop = get_property(node, propname); + if (!prop) + return 0; + + if (prop->val.len != sizeof(cell_t)) { + FAIL_PROP(c, dti, node, prop, "bad length (%d) %s property", + prop->val.len, prop->name); + return 0; + } + + m = prop->val.markers; + for_each_marker_of_type(m, REF_PHANDLE) { + assert(m->offset == 0); + if (node != get_node_by_ref(root, m->ref)) + /* "Set this node's phandle equal to some + * other node's phandle". That's nonsensical + * by construction. */ { + FAIL(c, dti, node, "%s is a reference to another node", + prop->name); + } + /* But setting this node's phandle equal to its own + * phandle is allowed - that means allocate a unique + * phandle for this node, even if it's not otherwise + * referenced. The value will be filled in later, so + * we treat it as having no phandle data for now. */ + return 0; + } + + phandle = propval_cell(prop); + + if ((phandle == 0) || (phandle == -1)) { + FAIL_PROP(c, dti, node, prop, "bad value (0x%x) in %s property", + phandle, prop->name); + return 0; + } + + return phandle; +} + +static void check_explicit_phandles(struct check *c, struct dt_info *dti, + struct node *node) +{ + struct node *root = dti->dt; + struct node *other; + cell_t phandle, linux_phandle; + + /* Nothing should have assigned phandles yet */ + assert(!node->phandle); + + phandle = check_phandle_prop(c, dti, node, "phandle"); + + linux_phandle = check_phandle_prop(c, dti, node, "linux,phandle"); + + if (!phandle && !linux_phandle) + /* No valid phandles; nothing further to check */ + return; + + if (linux_phandle && phandle && (phandle != linux_phandle)) + FAIL(c, dti, node, "mismatching 'phandle' and 'linux,phandle'" + " properties"); + + if (linux_phandle && !phandle) + phandle = linux_phandle; + + other = get_node_by_phandle(root, phandle); + if (other && (other != node)) { + FAIL(c, dti, node, "duplicated phandle 0x%x (seen before at %s)", + phandle, other->fullpath); + return; + } + + node->phandle = phandle; +} +ERROR(explicit_phandles, check_explicit_phandles, NULL); + +static void check_name_properties(struct check *c, struct dt_info *dti, + struct node *node) +{ + struct property **pp, *prop = NULL; + + for (pp = &node->proplist; *pp; pp = &((*pp)->next)) + if (streq((*pp)->name, "name")) { + prop = *pp; + break; + } + + if (!prop) + return; /* No name property, that's fine */ + + if ((prop->val.len != node->basenamelen+1) + || (memcmp(prop->val.val, node->name, node->basenamelen) != 0)) { + FAIL(c, dti, node, "\"name\" property is incorrect (\"%s\" instead" + " of base node name)", prop->val.val); + } else { + /* The name property is correct, and therefore redundant. + * Delete it */ + *pp = prop->next; + free(prop->name); + data_free(prop->val); + free(prop); + } +} +ERROR_IF_NOT_STRING(name_is_string, "name"); +ERROR(name_properties, check_name_properties, NULL, &name_is_string); + +/* + * Reference fixup functions + */ + +static void fixup_phandle_references(struct check *c, struct dt_info *dti, + struct node *node) +{ + struct node *dt = dti->dt; + struct property *prop; + + for_each_property(node, prop) { + struct marker *m = prop->val.markers; + struct node *refnode; + cell_t phandle; + + for_each_marker_of_type(m, REF_PHANDLE) { + assert(m->offset + sizeof(cell_t) <= prop->val.len); + + refnode = get_node_by_ref(dt, m->ref); + if (! refnode) { + if (!(dti->dtsflags & DTSF_PLUGIN)) + FAIL(c, dti, node, "Reference to non-existent node or " + "label \"%s\"\n", m->ref); + else /* mark the entry as unresolved */ + *((fdt32_t *)(prop->val.val + m->offset)) = + cpu_to_fdt32(0xffffffff); + continue; + } + + phandle = get_node_phandle(dt, refnode); + *((fdt32_t *)(prop->val.val + m->offset)) = cpu_to_fdt32(phandle); + + reference_node(refnode); + } + } +} +ERROR(phandle_references, fixup_phandle_references, NULL, + &duplicate_node_names, &explicit_phandles); + +static void fixup_path_references(struct check *c, struct dt_info *dti, + struct node *node) +{ + struct node *dt = dti->dt; + struct property *prop; + + for_each_property(node, prop) { + struct marker *m = prop->val.markers; + struct node *refnode; + char *path; + + for_each_marker_of_type(m, REF_PATH) { + assert(m->offset <= prop->val.len); + + refnode = get_node_by_ref(dt, m->ref); + if (!refnode) { + FAIL(c, dti, node, "Reference to non-existent node or label \"%s\"\n", + m->ref); + continue; + } + + path = refnode->fullpath; + prop->val = data_insert_at_marker(prop->val, m, path, + strlen(path) + 1); + + reference_node(refnode); + } + } +} +ERROR(path_references, fixup_path_references, NULL, &duplicate_node_names); + +static void fixup_omit_unused_nodes(struct check *c, struct dt_info *dti, + struct node *node) +{ + if (generate_symbols && node->labels) + return; + if (node->omit_if_unused && !node->is_referenced) + delete_node(node); +} +ERROR(omit_unused_nodes, fixup_omit_unused_nodes, NULL, &phandle_references, &path_references); + +/* + * Semantic checks + */ +WARNING_IF_NOT_CELL(address_cells_is_cell, "#address-cells"); +WARNING_IF_NOT_CELL(size_cells_is_cell, "#size-cells"); +WARNING_IF_NOT_CELL(interrupt_cells_is_cell, "#interrupt-cells"); + +WARNING_IF_NOT_STRING(device_type_is_string, "device_type"); +WARNING_IF_NOT_STRING(model_is_string, "model"); +WARNING_IF_NOT_STRING(status_is_string, "status"); +WARNING_IF_NOT_STRING(label_is_string, "label"); + +WARNING_IF_NOT_STRING_LIST(compatible_is_string_list, "compatible"); + +static void check_names_is_string_list(struct check *c, struct dt_info *dti, + struct node *node) +{ + struct property *prop; + + for_each_property(node, prop) { + const char *s = strrchr(prop->name, '-'); + if (!s || !streq(s, "-names")) + continue; + + c->data = prop->name; + check_is_string_list(c, dti, node); + } +} +WARNING(names_is_string_list, check_names_is_string_list, NULL); + +static void check_alias_paths(struct check *c, struct dt_info *dti, + struct node *node) +{ + struct property *prop; + + if (!streq(node->name, "aliases")) + return; + + for_each_property(node, prop) { + if (streq(prop->name, "phandle") + || streq(prop->name, "linux,phandle")) { + continue; + } + + if (!prop->val.val || !get_node_by_path(dti->dt, prop->val.val)) { + FAIL_PROP(c, dti, node, prop, "aliases property is not a valid node (%s)", + prop->val.val); + continue; + } + if (strspn(prop->name, LOWERCASE DIGITS "-") != strlen(prop->name)) + FAIL(c, dti, node, "aliases property name must include only lowercase and '-'"); + } +} +WARNING(alias_paths, check_alias_paths, NULL); + +static void fixup_addr_size_cells(struct check *c, struct dt_info *dti, + struct node *node) +{ + struct property *prop; + + node->addr_cells = -1; + node->size_cells = -1; + + prop = get_property(node, "#address-cells"); + if (prop) + node->addr_cells = propval_cell(prop); + + prop = get_property(node, "#size-cells"); + if (prop) + node->size_cells = propval_cell(prop); +} +WARNING(addr_size_cells, fixup_addr_size_cells, NULL, + &address_cells_is_cell, &size_cells_is_cell); + +#define node_addr_cells(n) \ + (((n)->addr_cells == -1) ? 2 : (n)->addr_cells) +#define node_size_cells(n) \ + (((n)->size_cells == -1) ? 1 : (n)->size_cells) + +static void check_reg_format(struct check *c, struct dt_info *dti, + struct node *node) +{ + struct property *prop; + int addr_cells, size_cells, entrylen; + + prop = get_property(node, "reg"); + if (!prop) + return; /* No "reg", that's fine */ + + if (!node->parent) { + FAIL(c, dti, node, "Root node has a \"reg\" property"); + return; + } + + if (prop->val.len == 0) + FAIL_PROP(c, dti, node, prop, "property is empty"); + + addr_cells = node_addr_cells(node->parent); + size_cells = node_size_cells(node->parent); + entrylen = (addr_cells + size_cells) * sizeof(cell_t); + + if (!entrylen || (prop->val.len % entrylen) != 0) + FAIL_PROP(c, dti, node, prop, "property has invalid length (%d bytes) " + "(#address-cells == %d, #size-cells == %d)", + prop->val.len, addr_cells, size_cells); +} +WARNING(reg_format, check_reg_format, NULL, &addr_size_cells); + +static void check_ranges_format(struct check *c, struct dt_info *dti, + struct node *node) +{ + struct property *prop; + int c_addr_cells, p_addr_cells, c_size_cells, p_size_cells, entrylen; + const char *ranges = c->data; + + prop = get_property(node, ranges); + if (!prop) + return; + + if (!node->parent) { + FAIL_PROP(c, dti, node, prop, "Root node has a \"%s\" property", + ranges); + return; + } + + p_addr_cells = node_addr_cells(node->parent); + p_size_cells = node_size_cells(node->parent); + c_addr_cells = node_addr_cells(node); + c_size_cells = node_size_cells(node); + entrylen = (p_addr_cells + c_addr_cells + c_size_cells) * sizeof(cell_t); + + if (prop->val.len == 0) { + if (p_addr_cells != c_addr_cells) + FAIL_PROP(c, dti, node, prop, "empty \"%s\" property but its " + "#address-cells (%d) differs from %s (%d)", + ranges, c_addr_cells, node->parent->fullpath, + p_addr_cells); + if (p_size_cells != c_size_cells) + FAIL_PROP(c, dti, node, prop, "empty \"%s\" property but its " + "#size-cells (%d) differs from %s (%d)", + ranges, c_size_cells, node->parent->fullpath, + p_size_cells); + } else if ((prop->val.len % entrylen) != 0) { + FAIL_PROP(c, dti, node, prop, "\"%s\" property has invalid length (%d bytes) " + "(parent #address-cells == %d, child #address-cells == %d, " + "#size-cells == %d)", ranges, prop->val.len, + p_addr_cells, c_addr_cells, c_size_cells); + } +} +WARNING(ranges_format, check_ranges_format, "ranges", &addr_size_cells); +WARNING(dma_ranges_format, check_ranges_format, "dma-ranges", &addr_size_cells); + +static const struct bus_type pci_bus = { + .name = "PCI", +}; + +static void check_pci_bridge(struct check *c, struct dt_info *dti, struct node *node) +{ + struct property *prop; + cell_t *cells; + + prop = get_property(node, "device_type"); + if (!prop || !streq(prop->val.val, "pci")) + return; + + node->bus = &pci_bus; + + if (!strprefixeq(node->name, node->basenamelen, "pci") && + !strprefixeq(node->name, node->basenamelen, "pcie")) + FAIL(c, dti, node, "node name is not \"pci\" or \"pcie\""); + + prop = get_property(node, "ranges"); + if (!prop) + FAIL(c, dti, node, "missing ranges for PCI bridge (or not a bridge)"); + + if (node_addr_cells(node) != 3) + FAIL(c, dti, node, "incorrect #address-cells for PCI bridge"); + if (node_size_cells(node) != 2) + FAIL(c, dti, node, "incorrect #size-cells for PCI bridge"); + + prop = get_property(node, "bus-range"); + if (!prop) + return; + + if (prop->val.len != (sizeof(cell_t) * 2)) { + FAIL_PROP(c, dti, node, prop, "value must be 2 cells"); + return; + } + cells = (cell_t *)prop->val.val; + if (fdt32_to_cpu(cells[0]) > fdt32_to_cpu(cells[1])) + FAIL_PROP(c, dti, node, prop, "1st cell must be less than or equal to 2nd cell"); + if (fdt32_to_cpu(cells[1]) > 0xff) + FAIL_PROP(c, dti, node, prop, "maximum bus number must be less than 256"); +} +WARNING(pci_bridge, check_pci_bridge, NULL, + &device_type_is_string, &addr_size_cells); + +static void check_pci_device_bus_num(struct check *c, struct dt_info *dti, struct node *node) +{ + struct property *prop; + unsigned int bus_num, min_bus, max_bus; + cell_t *cells; + + if (!node->parent || (node->parent->bus != &pci_bus)) + return; + + prop = get_property(node, "reg"); + if (!prop) + return; + + cells = (cell_t *)prop->val.val; + bus_num = (fdt32_to_cpu(cells[0]) & 0x00ff0000) >> 16; + + prop = get_property(node->parent, "bus-range"); + if (!prop) { + min_bus = max_bus = 0; + } else { + cells = (cell_t *)prop->val.val; + min_bus = fdt32_to_cpu(cells[0]); + max_bus = fdt32_to_cpu(cells[0]); + } + if ((bus_num < min_bus) || (bus_num > max_bus)) + FAIL_PROP(c, dti, node, prop, "PCI bus number %d out of range, expected (%d - %d)", + bus_num, min_bus, max_bus); +} +WARNING(pci_device_bus_num, check_pci_device_bus_num, NULL, ®_format, &pci_bridge); + +static void check_pci_device_reg(struct check *c, struct dt_info *dti, struct node *node) +{ + struct property *prop; + const char *unitname = get_unitname(node); + char unit_addr[5]; + unsigned int dev, func, reg; + cell_t *cells; + + if (!node->parent || (node->parent->bus != &pci_bus)) + return; + + prop = get_property(node, "reg"); + if (!prop) + return; + + cells = (cell_t *)prop->val.val; + if (cells[1] || cells[2]) + FAIL_PROP(c, dti, node, prop, "PCI reg config space address cells 2 and 3 must be 0"); + + reg = fdt32_to_cpu(cells[0]); + dev = (reg & 0xf800) >> 11; + func = (reg & 0x700) >> 8; + + if (reg & 0xff000000) + FAIL_PROP(c, dti, node, prop, "PCI reg address is not configuration space"); + if (reg & 0x000000ff) + FAIL_PROP(c, dti, node, prop, "PCI reg config space address register number must be 0"); + + if (func == 0) { + snprintf(unit_addr, sizeof(unit_addr), "%x", dev); + if (streq(unitname, unit_addr)) + return; + } + + snprintf(unit_addr, sizeof(unit_addr), "%x,%x", dev, func); + if (streq(unitname, unit_addr)) + return; + + FAIL(c, dti, node, "PCI unit address format error, expected \"%s\"", + unit_addr); +} +WARNING(pci_device_reg, check_pci_device_reg, NULL, ®_format, &pci_bridge); + +static const struct bus_type simple_bus = { + .name = "simple-bus", +}; + +static bool node_is_compatible(struct node *node, const char *compat) +{ + struct property *prop; + const char *str, *end; + + prop = get_property(node, "compatible"); + if (!prop) + return false; + + for (str = prop->val.val, end = str + prop->val.len; str < end; + str += strnlen(str, end - str) + 1) { + if (streq(str, compat)) + return true; + } + return false; +} + +static void check_simple_bus_bridge(struct check *c, struct dt_info *dti, struct node *node) +{ + if (node_is_compatible(node, "simple-bus")) + node->bus = &simple_bus; +} +WARNING(simple_bus_bridge, check_simple_bus_bridge, NULL, + &addr_size_cells, &compatible_is_string_list); + +static void check_simple_bus_reg(struct check *c, struct dt_info *dti, struct node *node) +{ + struct property *prop; + const char *unitname = get_unitname(node); + char unit_addr[17]; + unsigned int size; + uint64_t reg = 0; + cell_t *cells = NULL; + + if (!node->parent || (node->parent->bus != &simple_bus)) + return; + + prop = get_property(node, "reg"); + if (prop) + cells = (cell_t *)prop->val.val; + else { + prop = get_property(node, "ranges"); + if (prop && prop->val.len) + /* skip of child address */ + cells = ((cell_t *)prop->val.val) + node_addr_cells(node); + } + + if (!cells) { + if (node->parent->parent && !(node->bus == &simple_bus)) + FAIL(c, dti, node, "missing or empty reg/ranges property"); + return; + } + + size = node_addr_cells(node->parent); + while (size--) + reg = (reg << 32) | fdt32_to_cpu(*(cells++)); + + snprintf(unit_addr, sizeof(unit_addr), "%"PRIx64, reg); + if (!streq(unitname, unit_addr)) + FAIL(c, dti, node, "simple-bus unit address format error, expected \"%s\"", + unit_addr); +} +WARNING(simple_bus_reg, check_simple_bus_reg, NULL, ®_format, &simple_bus_bridge); + +static const struct bus_type i2c_bus = { + .name = "i2c-bus", +}; + +static void check_i2c_bus_bridge(struct check *c, struct dt_info *dti, struct node *node) +{ + if (strprefixeq(node->name, node->basenamelen, "i2c-bus") || + strprefixeq(node->name, node->basenamelen, "i2c-arb")) { + node->bus = &i2c_bus; + } else if (strprefixeq(node->name, node->basenamelen, "i2c")) { + struct node *child; + for_each_child(node, child) { + if (strprefixeq(child->name, node->basenamelen, "i2c-bus")) + return; + } + node->bus = &i2c_bus; + } else + return; + + if (!node->children) + return; + + if (node_addr_cells(node) != 1) + FAIL(c, dti, node, "incorrect #address-cells for I2C bus"); + if (node_size_cells(node) != 0) + FAIL(c, dti, node, "incorrect #size-cells for I2C bus"); + +} +WARNING(i2c_bus_bridge, check_i2c_bus_bridge, NULL, &addr_size_cells); + +#define I2C_OWN_SLAVE_ADDRESS (1U << 30) +#define I2C_TEN_BIT_ADDRESS (1U << 31) + +static void check_i2c_bus_reg(struct check *c, struct dt_info *dti, struct node *node) +{ + struct property *prop; + const char *unitname = get_unitname(node); + char unit_addr[17]; + uint32_t reg = 0; + int len; + cell_t *cells = NULL; + + if (!node->parent || (node->parent->bus != &i2c_bus)) + return; + + prop = get_property(node, "reg"); + if (prop) + cells = (cell_t *)prop->val.val; + + if (!cells) { + FAIL(c, dti, node, "missing or empty reg property"); + return; + } + + reg = fdt32_to_cpu(*cells); + /* Ignore I2C_OWN_SLAVE_ADDRESS */ + reg &= ~I2C_OWN_SLAVE_ADDRESS; + snprintf(unit_addr, sizeof(unit_addr), "%x", reg); + if (!streq(unitname, unit_addr)) + FAIL(c, dti, node, "I2C bus unit address format error, expected \"%s\"", + unit_addr); + + for (len = prop->val.len; len > 0; len -= 4) { + reg = fdt32_to_cpu(*(cells++)); + /* Ignore I2C_OWN_SLAVE_ADDRESS */ + reg &= ~I2C_OWN_SLAVE_ADDRESS; + + if ((reg & I2C_TEN_BIT_ADDRESS) && ((reg & ~I2C_TEN_BIT_ADDRESS) > 0x3ff)) + FAIL_PROP(c, dti, node, prop, "I2C address must be less than 10-bits, got \"0x%x\"", + reg); + else if (reg > 0x7f) + FAIL_PROP(c, dti, node, prop, "I2C address must be less than 7-bits, got \"0x%x\". Set I2C_TEN_BIT_ADDRESS for 10 bit addresses or fix the property", + reg); + } +} +WARNING(i2c_bus_reg, check_i2c_bus_reg, NULL, ®_format, &i2c_bus_bridge); + +static const struct bus_type spi_bus = { + .name = "spi-bus", +}; + +static void check_spi_bus_bridge(struct check *c, struct dt_info *dti, struct node *node) +{ + int spi_addr_cells = 1; + + if (strprefixeq(node->name, node->basenamelen, "spi")) { + node->bus = &spi_bus; + } else { + /* Try to detect SPI buses which don't have proper node name */ + struct node *child; + + if (node_addr_cells(node) != 1 || node_size_cells(node) != 0) + return; + + for_each_child(node, child) { + struct property *prop; + for_each_property(child, prop) { + if (strprefixeq(prop->name, 4, "spi-")) { + node->bus = &spi_bus; + break; + } + } + if (node->bus == &spi_bus) + break; + } + + if (node->bus == &spi_bus && get_property(node, "reg")) + FAIL(c, dti, node, "node name for SPI buses should be 'spi'"); + } + if (node->bus != &spi_bus || !node->children) + return; + + if (get_property(node, "spi-slave")) + spi_addr_cells = 0; + if (node_addr_cells(node) != spi_addr_cells) + FAIL(c, dti, node, "incorrect #address-cells for SPI bus"); + if (node_size_cells(node) != 0) + FAIL(c, dti, node, "incorrect #size-cells for SPI bus"); + +} +WARNING(spi_bus_bridge, check_spi_bus_bridge, NULL, &addr_size_cells); + +static void check_spi_bus_reg(struct check *c, struct dt_info *dti, struct node *node) +{ + struct property *prop; + const char *unitname = get_unitname(node); + char unit_addr[9]; + uint32_t reg = 0; + cell_t *cells = NULL; + + if (!node->parent || (node->parent->bus != &spi_bus)) + return; + + if (get_property(node->parent, "spi-slave")) + return; + + prop = get_property(node, "reg"); + if (prop) + cells = (cell_t *)prop->val.val; + + if (!cells) { + FAIL(c, dti, node, "missing or empty reg property"); + return; + } + + reg = fdt32_to_cpu(*cells); + snprintf(unit_addr, sizeof(unit_addr), "%x", reg); + if (!streq(unitname, unit_addr)) + FAIL(c, dti, node, "SPI bus unit address format error, expected \"%s\"", + unit_addr); +} +WARNING(spi_bus_reg, check_spi_bus_reg, NULL, ®_format, &spi_bus_bridge); + +static void check_unit_address_format(struct check *c, struct dt_info *dti, + struct node *node) +{ + const char *unitname = get_unitname(node); + + if (node->parent && node->parent->bus) + return; + + if (!unitname[0]) + return; + + if (!strncmp(unitname, "0x", 2)) { + FAIL(c, dti, node, "unit name should not have leading \"0x\""); + /* skip over 0x for next test */ + unitname += 2; + } + if (unitname[0] == '0' && isxdigit(unitname[1])) + FAIL(c, dti, node, "unit name should not have leading 0s"); +} +WARNING(unit_address_format, check_unit_address_format, NULL, + &node_name_format, &pci_bridge, &simple_bus_bridge); + +/* + * Style checks + */ +static void check_avoid_default_addr_size(struct check *c, struct dt_info *dti, + struct node *node) +{ + struct property *reg, *ranges; + + if (!node->parent) + return; /* Ignore root node */ + + reg = get_property(node, "reg"); + ranges = get_property(node, "ranges"); + + if (!reg && !ranges) + return; + + if (node->parent->addr_cells == -1) + FAIL(c, dti, node, "Relying on default #address-cells value"); + + if (node->parent->size_cells == -1) + FAIL(c, dti, node, "Relying on default #size-cells value"); +} +WARNING(avoid_default_addr_size, check_avoid_default_addr_size, NULL, + &addr_size_cells); + +static void check_avoid_unnecessary_addr_size(struct check *c, struct dt_info *dti, + struct node *node) +{ + struct property *prop; + struct node *child; + bool has_reg = false; + + if (!node->parent || node->addr_cells < 0 || node->size_cells < 0) + return; + + if (get_property(node, "ranges") || !node->children) + return; + + for_each_child(node, child) { + prop = get_property(child, "reg"); + if (prop) + has_reg = true; + } + + if (!has_reg) + FAIL(c, dti, node, "unnecessary #address-cells/#size-cells without \"ranges\" or child \"reg\" property"); +} +WARNING(avoid_unnecessary_addr_size, check_avoid_unnecessary_addr_size, NULL, &avoid_default_addr_size); + +static bool node_is_disabled(struct node *node) +{ + struct property *prop; + + prop = get_property(node, "status"); + if (prop) { + char *str = prop->val.val; + if (streq("disabled", str)) + return true; + } + + return false; +} + +static void check_unique_unit_address_common(struct check *c, + struct dt_info *dti, + struct node *node, + bool disable_check) +{ + struct node *childa; + + if (node->addr_cells < 0 || node->size_cells < 0) + return; + + if (!node->children) + return; + + for_each_child(node, childa) { + struct node *childb; + const char *addr_a = get_unitname(childa); + + if (!strlen(addr_a)) + continue; + + if (disable_check && node_is_disabled(childa)) + continue; + + for_each_child(node, childb) { + const char *addr_b = get_unitname(childb); + if (childa == childb) + break; + + if (disable_check && node_is_disabled(childb)) + continue; + + if (streq(addr_a, addr_b)) + FAIL(c, dti, childb, "duplicate unit-address (also used in node %s)", childa->fullpath); + } + } +} + +static void check_unique_unit_address(struct check *c, struct dt_info *dti, + struct node *node) +{ + check_unique_unit_address_common(c, dti, node, false); +} +WARNING(unique_unit_address, check_unique_unit_address, NULL, &avoid_default_addr_size); + +static void check_unique_unit_address_if_enabled(struct check *c, struct dt_info *dti, + struct node *node) +{ + check_unique_unit_address_common(c, dti, node, true); +} +CHECK_ENTRY(unique_unit_address_if_enabled, check_unique_unit_address_if_enabled, + NULL, false, false, &avoid_default_addr_size); + +static void check_obsolete_chosen_interrupt_controller(struct check *c, + struct dt_info *dti, + struct node *node) +{ + struct node *dt = dti->dt; + struct node *chosen; + struct property *prop; + + if (node != dt) + return; + + + chosen = get_node_by_path(dt, "/chosen"); + if (!chosen) + return; + + prop = get_property(chosen, "interrupt-controller"); + if (prop) + FAIL_PROP(c, dti, node, prop, + "/chosen has obsolete \"interrupt-controller\" property"); +} +WARNING(obsolete_chosen_interrupt_controller, + check_obsolete_chosen_interrupt_controller, NULL); + +static void check_chosen_node_is_root(struct check *c, struct dt_info *dti, + struct node *node) +{ + if (!streq(node->name, "chosen")) + return; + + if (node->parent != dti->dt) + FAIL(c, dti, node, "chosen node must be at root node"); +} +WARNING(chosen_node_is_root, check_chosen_node_is_root, NULL); + +static void check_chosen_node_bootargs(struct check *c, struct dt_info *dti, + struct node *node) +{ + struct property *prop; + + if (!streq(node->name, "chosen")) + return; + + prop = get_property(node, "bootargs"); + if (!prop) + return; + + c->data = prop->name; + check_is_string(c, dti, node); +} +WARNING(chosen_node_bootargs, check_chosen_node_bootargs, NULL); + +static void check_chosen_node_stdout_path(struct check *c, struct dt_info *dti, + struct node *node) +{ + struct property *prop; + + if (!streq(node->name, "chosen")) + return; + + prop = get_property(node, "stdout-path"); + if (!prop) { + prop = get_property(node, "linux,stdout-path"); + if (!prop) + return; + FAIL_PROP(c, dti, node, prop, "Use 'stdout-path' instead"); + } + + c->data = prop->name; + check_is_string(c, dti, node); +} +WARNING(chosen_node_stdout_path, check_chosen_node_stdout_path, NULL); + +struct provider { + const char *prop_name; + const char *cell_name; + bool optional; +}; + +static void check_property_phandle_args(struct check *c, + struct dt_info *dti, + struct node *node, + struct property *prop, + const struct provider *provider) +{ + struct node *root = dti->dt; + int cell, cellsize = 0; + + if (prop->val.len % sizeof(cell_t)) { + FAIL_PROP(c, dti, node, prop, + "property size (%d) is invalid, expected multiple of %zu", + prop->val.len, sizeof(cell_t)); + return; + } + + for (cell = 0; cell < prop->val.len / sizeof(cell_t); cell += cellsize + 1) { + struct node *provider_node; + struct property *cellprop; + int phandle; + + phandle = propval_cell_n(prop, cell); + /* + * Some bindings use a cell value 0 or -1 to skip over optional + * entries when each index position has a specific definition. + */ + if (phandle == 0 || phandle == -1) { + /* Give up if this is an overlay with external references */ + if (dti->dtsflags & DTSF_PLUGIN) + break; + + cellsize = 0; + continue; + } + + /* If we have markers, verify the current cell is a phandle */ + if (prop->val.markers) { + struct marker *m = prop->val.markers; + for_each_marker_of_type(m, REF_PHANDLE) { + if (m->offset == (cell * sizeof(cell_t))) + break; + } + if (!m) + FAIL_PROP(c, dti, node, prop, + "cell %d is not a phandle reference", + cell); + } + + provider_node = get_node_by_phandle(root, phandle); + if (!provider_node) { + FAIL_PROP(c, dti, node, prop, + "Could not get phandle node for (cell %d)", + cell); + break; + } + + cellprop = get_property(provider_node, provider->cell_name); + if (cellprop) { + cellsize = propval_cell(cellprop); + } else if (provider->optional) { + cellsize = 0; + } else { + FAIL(c, dti, node, "Missing property '%s' in node %s or bad phandle (referred from %s[%d])", + provider->cell_name, + provider_node->fullpath, + prop->name, cell); + break; + } + + if (prop->val.len < ((cell + cellsize + 1) * sizeof(cell_t))) { + FAIL_PROP(c, dti, node, prop, + "property size (%d) too small for cell size %d", + prop->val.len, cellsize); + } + } +} + +static void check_provider_cells_property(struct check *c, + struct dt_info *dti, + struct node *node) +{ + struct provider *provider = c->data; + struct property *prop; + + prop = get_property(node, provider->prop_name); + if (!prop) + return; + + check_property_phandle_args(c, dti, node, prop, provider); +} +#define WARNING_PROPERTY_PHANDLE_CELLS(nm, propname, cells_name, ...) \ + static struct provider nm##_provider = { (propname), (cells_name), __VA_ARGS__ }; \ + WARNING(nm##_property, check_provider_cells_property, &nm##_provider, &phandle_references); + +WARNING_PROPERTY_PHANDLE_CELLS(clocks, "clocks", "#clock-cells"); +WARNING_PROPERTY_PHANDLE_CELLS(cooling_device, "cooling-device", "#cooling-cells"); +WARNING_PROPERTY_PHANDLE_CELLS(dmas, "dmas", "#dma-cells"); +WARNING_PROPERTY_PHANDLE_CELLS(hwlocks, "hwlocks", "#hwlock-cells"); +WARNING_PROPERTY_PHANDLE_CELLS(interrupts_extended, "interrupts-extended", "#interrupt-cells"); +WARNING_PROPERTY_PHANDLE_CELLS(io_channels, "io-channels", "#io-channel-cells"); +WARNING_PROPERTY_PHANDLE_CELLS(iommus, "iommus", "#iommu-cells"); +WARNING_PROPERTY_PHANDLE_CELLS(mboxes, "mboxes", "#mbox-cells"); +WARNING_PROPERTY_PHANDLE_CELLS(msi_parent, "msi-parent", "#msi-cells", true); +WARNING_PROPERTY_PHANDLE_CELLS(mux_controls, "mux-controls", "#mux-control-cells"); +WARNING_PROPERTY_PHANDLE_CELLS(phys, "phys", "#phy-cells"); +WARNING_PROPERTY_PHANDLE_CELLS(power_domains, "power-domains", "#power-domain-cells"); +WARNING_PROPERTY_PHANDLE_CELLS(pwms, "pwms", "#pwm-cells"); +WARNING_PROPERTY_PHANDLE_CELLS(resets, "resets", "#reset-cells"); +WARNING_PROPERTY_PHANDLE_CELLS(sound_dai, "sound-dai", "#sound-dai-cells"); +WARNING_PROPERTY_PHANDLE_CELLS(thermal_sensors, "thermal-sensors", "#thermal-sensor-cells"); + +static bool prop_is_gpio(struct property *prop) +{ + char *str; + + /* + * *-gpios and *-gpio can appear in property names, + * so skip over any false matches (only one known ATM) + */ + if (strstr(prop->name, "nr-gpio")) + return false; + + str = strrchr(prop->name, '-'); + if (str) + str++; + else + str = prop->name; + if (!(streq(str, "gpios") || streq(str, "gpio"))) + return false; + + return true; +} + +static void check_gpios_property(struct check *c, + struct dt_info *dti, + struct node *node) +{ + struct property *prop; + + /* Skip GPIO hog nodes which have 'gpios' property */ + if (get_property(node, "gpio-hog")) + return; + + for_each_property(node, prop) { + struct provider provider; + + if (!prop_is_gpio(prop)) + continue; + + provider.prop_name = prop->name; + provider.cell_name = "#gpio-cells"; + provider.optional = false; + check_property_phandle_args(c, dti, node, prop, &provider); + } + +} +WARNING(gpios_property, check_gpios_property, NULL, &phandle_references); + +static void check_deprecated_gpio_property(struct check *c, + struct dt_info *dti, + struct node *node) +{ + struct property *prop; + + for_each_property(node, prop) { + char *str; + + if (!prop_is_gpio(prop)) + continue; + + str = strstr(prop->name, "gpio"); + if (!streq(str, "gpio")) + continue; + + FAIL_PROP(c, dti, node, prop, + "'[*-]gpio' is deprecated, use '[*-]gpios' instead"); + } + +} +CHECK(deprecated_gpio_property, check_deprecated_gpio_property, NULL); + +static bool node_is_interrupt_provider(struct node *node) +{ + struct property *prop; + + prop = get_property(node, "interrupt-controller"); + if (prop) + return true; + + prop = get_property(node, "interrupt-map"); + if (prop) + return true; + + return false; +} + +static void check_interrupt_provider(struct check *c, + struct dt_info *dti, + struct node *node) +{ + struct property *prop; + + if (!node_is_interrupt_provider(node)) + return; + + prop = get_property(node, "#interrupt-cells"); + if (!prop) + FAIL(c, dti, node, + "Missing #interrupt-cells in interrupt provider"); + + prop = get_property(node, "#address-cells"); + if (!prop) + FAIL(c, dti, node, + "Missing #address-cells in interrupt provider"); +} +WARNING(interrupt_provider, check_interrupt_provider, NULL); + +static void check_interrupts_property(struct check *c, + struct dt_info *dti, + struct node *node) +{ + struct node *root = dti->dt; + struct node *irq_node = NULL, *parent = node; + struct property *irq_prop, *prop = NULL; + int irq_cells, phandle; + + irq_prop = get_property(node, "interrupts"); + if (!irq_prop) + return; + + if (irq_prop->val.len % sizeof(cell_t)) + FAIL_PROP(c, dti, node, irq_prop, "size (%d) is invalid, expected multiple of %zu", + irq_prop->val.len, sizeof(cell_t)); + + while (parent && !prop) { + if (parent != node && node_is_interrupt_provider(parent)) { + irq_node = parent; + break; + } + + prop = get_property(parent, "interrupt-parent"); + if (prop) { + phandle = propval_cell(prop); + if ((phandle == 0) || (phandle == -1)) { + /* Give up if this is an overlay with + * external references */ + if (dti->dtsflags & DTSF_PLUGIN) + return; + FAIL_PROP(c, dti, parent, prop, "Invalid phandle"); + continue; + } + + irq_node = get_node_by_phandle(root, phandle); + if (!irq_node) { + FAIL_PROP(c, dti, parent, prop, "Bad phandle"); + return; + } + if (!node_is_interrupt_provider(irq_node)) + FAIL(c, dti, irq_node, + "Missing interrupt-controller or interrupt-map property"); + + break; + } + + parent = parent->parent; + } + + if (!irq_node) { + FAIL(c, dti, node, "Missing interrupt-parent"); + return; + } + + prop = get_property(irq_node, "#interrupt-cells"); + if (!prop) { + /* We warn about that already in another test. */ + return; + } + + irq_cells = propval_cell(prop); + if (irq_prop->val.len % (irq_cells * sizeof(cell_t))) { + FAIL_PROP(c, dti, node, prop, + "size is (%d), expected multiple of %d", + irq_prop->val.len, (int)(irq_cells * sizeof(cell_t))); + } +} +WARNING(interrupts_property, check_interrupts_property, &phandle_references); + +static const struct bus_type graph_port_bus = { + .name = "graph-port", +}; + +static const struct bus_type graph_ports_bus = { + .name = "graph-ports", +}; + +static void check_graph_nodes(struct check *c, struct dt_info *dti, + struct node *node) +{ + struct node *child; + + for_each_child(node, child) { + if (!(strprefixeq(child->name, child->basenamelen, "endpoint") || + get_property(child, "remote-endpoint"))) + continue; + + node->bus = &graph_port_bus; + + /* The parent of 'port' nodes can be either 'ports' or a device */ + if (!node->parent->bus && + (streq(node->parent->name, "ports") || get_property(node, "reg"))) + node->parent->bus = &graph_ports_bus; + + break; + } + +} +WARNING(graph_nodes, check_graph_nodes, NULL); + +static void check_graph_child_address(struct check *c, struct dt_info *dti, + struct node *node) +{ + int cnt = 0; + struct node *child; + + if (node->bus != &graph_ports_bus && node->bus != &graph_port_bus) + return; + + for_each_child(node, child) { + struct property *prop = get_property(child, "reg"); + + /* No error if we have any non-zero unit address */ + if (prop && propval_cell(prop) != 0) + return; + + cnt++; + } + + if (cnt == 1 && node->addr_cells != -1) + FAIL(c, dti, node, "graph node has single child node '%s', #address-cells/#size-cells are not necessary", + node->children->name); +} +WARNING(graph_child_address, check_graph_child_address, NULL, &graph_nodes); + +static void check_graph_reg(struct check *c, struct dt_info *dti, + struct node *node) +{ + char unit_addr[9]; + const char *unitname = get_unitname(node); + struct property *prop; + + prop = get_property(node, "reg"); + if (!prop || !unitname) + return; + + if (!(prop->val.val && prop->val.len == sizeof(cell_t))) { + FAIL(c, dti, node, "graph node malformed 'reg' property"); + return; + } + + snprintf(unit_addr, sizeof(unit_addr), "%x", propval_cell(prop)); + if (!streq(unitname, unit_addr)) + FAIL(c, dti, node, "graph node unit address error, expected \"%s\"", + unit_addr); + + if (node->parent->addr_cells != 1) + FAIL_PROP(c, dti, node, get_property(node, "#address-cells"), + "graph node '#address-cells' is %d, must be 1", + node->parent->addr_cells); + if (node->parent->size_cells != 0) + FAIL_PROP(c, dti, node, get_property(node, "#size-cells"), + "graph node '#size-cells' is %d, must be 0", + node->parent->size_cells); +} + +static void check_graph_port(struct check *c, struct dt_info *dti, + struct node *node) +{ + if (node->bus != &graph_port_bus) + return; + + if (!strprefixeq(node->name, node->basenamelen, "port")) + FAIL(c, dti, node, "graph port node name should be 'port'"); + + check_graph_reg(c, dti, node); +} +WARNING(graph_port, check_graph_port, NULL, &graph_nodes); + +static struct node *get_remote_endpoint(struct check *c, struct dt_info *dti, + struct node *endpoint) +{ + int phandle; + struct node *node; + struct property *prop; + + prop = get_property(endpoint, "remote-endpoint"); + if (!prop) + return NULL; + + phandle = propval_cell(prop); + /* Give up if this is an overlay with external references */ + if (phandle == 0 || phandle == -1) + return NULL; + + node = get_node_by_phandle(dti->dt, phandle); + if (!node) + FAIL_PROP(c, dti, endpoint, prop, "graph phandle is not valid"); + + return node; +} + +static void check_graph_endpoint(struct check *c, struct dt_info *dti, + struct node *node) +{ + struct node *remote_node; + + if (!node->parent || node->parent->bus != &graph_port_bus) + return; + + if (!strprefixeq(node->name, node->basenamelen, "endpoint")) + FAIL(c, dti, node, "graph endpoint node name should be 'endpoint'"); + + check_graph_reg(c, dti, node); + + remote_node = get_remote_endpoint(c, dti, node); + if (!remote_node) + return; + + if (get_remote_endpoint(c, dti, remote_node) != node) + FAIL(c, dti, node, "graph connection to node '%s' is not bidirectional", + remote_node->fullpath); +} +WARNING(graph_endpoint, check_graph_endpoint, NULL, &graph_nodes); + +static struct check *check_table[] = { + &duplicate_node_names, &duplicate_property_names, + &node_name_chars, &node_name_format, &property_name_chars, + &name_is_string, &name_properties, + + &duplicate_label, + + &explicit_phandles, + &phandle_references, &path_references, + &omit_unused_nodes, + + &address_cells_is_cell, &size_cells_is_cell, &interrupt_cells_is_cell, + &device_type_is_string, &model_is_string, &status_is_string, + &label_is_string, + + &compatible_is_string_list, &names_is_string_list, + + &property_name_chars_strict, + &node_name_chars_strict, + + &addr_size_cells, ®_format, &ranges_format, &dma_ranges_format, + + &unit_address_vs_reg, + &unit_address_format, + + &pci_bridge, + &pci_device_reg, + &pci_device_bus_num, + + &simple_bus_bridge, + &simple_bus_reg, + + &i2c_bus_bridge, + &i2c_bus_reg, + + &spi_bus_bridge, + &spi_bus_reg, + + &avoid_default_addr_size, + &avoid_unnecessary_addr_size, + &unique_unit_address, + &unique_unit_address_if_enabled, + &obsolete_chosen_interrupt_controller, + &chosen_node_is_root, &chosen_node_bootargs, &chosen_node_stdout_path, + + &clocks_property, + &cooling_device_property, + &dmas_property, + &hwlocks_property, + &interrupts_extended_property, + &io_channels_property, + &iommus_property, + &mboxes_property, + &msi_parent_property, + &mux_controls_property, + &phys_property, + &power_domains_property, + &pwms_property, + &resets_property, + &sound_dai_property, + &thermal_sensors_property, + + &deprecated_gpio_property, + &gpios_property, + &interrupts_property, + &interrupt_provider, + + &alias_paths, + + &graph_nodes, &graph_child_address, &graph_port, &graph_endpoint, + + &always_fail, +}; + +static void enable_warning_error(struct check *c, bool warn, bool error) +{ + int i; + + /* Raising level, also raise it for prereqs */ + if ((warn && !c->warn) || (error && !c->error)) + for (i = 0; i < c->num_prereqs; i++) + enable_warning_error(c->prereq[i], warn, error); + + c->warn = c->warn || warn; + c->error = c->error || error; +} + +static void disable_warning_error(struct check *c, bool warn, bool error) +{ + int i; + + /* Lowering level, also lower it for things this is the prereq + * for */ + if ((warn && c->warn) || (error && c->error)) { + for (i = 0; i < ARRAY_SIZE(check_table); i++) { + struct check *cc = check_table[i]; + int j; + + for (j = 0; j < cc->num_prereqs; j++) + if (cc->prereq[j] == c) + disable_warning_error(cc, warn, error); + } + } + + c->warn = c->warn && !warn; + c->error = c->error && !error; +} + +void parse_checks_option(bool warn, bool error, const char *arg) +{ + int i; + const char *name = arg; + bool enable = true; + + if ((strncmp(arg, "no-", 3) == 0) + || (strncmp(arg, "no_", 3) == 0)) { + name = arg + 3; + enable = false; + } + + for (i = 0; i < ARRAY_SIZE(check_table); i++) { + struct check *c = check_table[i]; + + if (streq(c->name, name)) { + if (enable) + enable_warning_error(c, warn, error); + else + disable_warning_error(c, warn, error); + return; + } + } + + die("Unrecognized check name \"%s\"\n", name); +} + +void process_checks(bool force, struct dt_info *dti) +{ + int i; + int error = 0; + + for (i = 0; i < ARRAY_SIZE(check_table); i++) { + struct check *c = check_table[i]; + + if (c->warn || c->error) + error = error || run_check(c, dti); + } + + if (error) { + if (!force) { + fprintf(stderr, "ERROR: Input tree has errors, aborting " + "(use -f to force output)\n"); + exit(2); + } else if (quiet < 3) { + fprintf(stderr, "Warning: Input tree has errors, " + "output forced\n"); + } + } +} diff --git a/src/net/scripts/dtc/data.c b/src/net/scripts/dtc/data.c new file mode 100644 index 0000000..0a43b6d --- /dev/null +++ b/src/net/scripts/dtc/data.c @@ -0,0 +1,256 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (C) Copyright David Gibson <dwg@au1.ibm.com>, IBM Corporation. 2005. + */ + +#include "dtc.h" + +void data_free(struct data d) +{ + struct marker *m, *nm; + + m = d.markers; + while (m) { + nm = m->next; + free(m->ref); + free(m); + m = nm; + } + + if (d.val) + free(d.val); +} + +struct data data_grow_for(struct data d, int xlen) +{ + struct data nd; + int newsize; + + if (xlen == 0) + return d; + + nd = d; + + newsize = xlen; + + while ((d.len + xlen) > newsize) + newsize *= 2; + + nd.val = xrealloc(d.val, newsize); + + return nd; +} + +struct data data_copy_mem(const char *mem, int len) +{ + struct data d; + + d = data_grow_for(empty_data, len); + + d.len = len; + memcpy(d.val, mem, len); + + return d; +} + +struct data data_copy_escape_string(const char *s, int len) +{ + int i = 0; + struct data d; + char *q; + + d = data_add_marker(empty_data, TYPE_STRING, NULL); + d = data_grow_for(d, len + 1); + + q = d.val; + while (i < len) { + char c = s[i++]; + + if (c == '\\') + c = get_escape_char(s, &i); + + q[d.len++] = c; + } + + q[d.len++] = '\0'; + return d; +} + +struct data data_copy_file(FILE *f, size_t maxlen) +{ + struct data d = empty_data; + + d = data_add_marker(d, TYPE_NONE, NULL); + while (!feof(f) && (d.len < maxlen)) { + size_t chunksize, ret; + + if (maxlen == -1) + chunksize = 4096; + else + chunksize = maxlen - d.len; + + d = data_grow_for(d, chunksize); + ret = fread(d.val + d.len, 1, chunksize, f); + + if (ferror(f)) + die("Error reading file into data: %s", strerror(errno)); + + if (d.len + ret < d.len) + die("Overflow reading file into data\n"); + + d.len += ret; + } + + return d; +} + +struct data data_append_data(struct data d, const void *p, int len) +{ + d = data_grow_for(d, len); + memcpy(d.val + d.len, p, len); + d.len += len; + return d; +} + +struct data data_insert_at_marker(struct data d, struct marker *m, + const void *p, int len) +{ + d = data_grow_for(d, len); + memmove(d.val + m->offset + len, d.val + m->offset, d.len - m->offset); + memcpy(d.val + m->offset, p, len); + d.len += len; + + /* Adjust all markers after the one we're inserting at */ + m = m->next; + for_each_marker(m) + m->offset += len; + return d; +} + +static struct data data_append_markers(struct data d, struct marker *m) +{ + struct marker **mp = &d.markers; + + /* Find the end of the markerlist */ + while (*mp) + mp = &((*mp)->next); + *mp = m; + return d; +} + +struct data data_merge(struct data d1, struct data d2) +{ + struct data d; + struct marker *m2 = d2.markers; + + d = data_append_markers(data_append_data(d1, d2.val, d2.len), m2); + + /* Adjust for the length of d1 */ + for_each_marker(m2) + m2->offset += d1.len; + + d2.markers = NULL; /* So data_free() doesn't clobber them */ + data_free(d2); + + return d; +} + +struct data data_append_integer(struct data d, uint64_t value, int bits) +{ + uint8_t value_8; + fdt16_t value_16; + fdt32_t value_32; + fdt64_t value_64; + + switch (bits) { + case 8: + value_8 = value; + return data_append_data(d, &value_8, 1); + + case 16: + value_16 = cpu_to_fdt16(value); + return data_append_data(d, &value_16, 2); + + case 32: + value_32 = cpu_to_fdt32(value); + return data_append_data(d, &value_32, 4); + + case 64: + value_64 = cpu_to_fdt64(value); + return data_append_data(d, &value_64, 8); + + default: + die("Invalid literal size (%d)\n", bits); + } +} + +struct data data_append_re(struct data d, uint64_t address, uint64_t size) +{ + struct fdt_reserve_entry re; + + re.address = cpu_to_fdt64(address); + re.size = cpu_to_fdt64(size); + + return data_append_data(d, &re, sizeof(re)); +} + +struct data data_append_cell(struct data d, cell_t word) +{ + return data_append_integer(d, word, sizeof(word) * 8); +} + +struct data data_append_addr(struct data d, uint64_t addr) +{ + return data_append_integer(d, addr, sizeof(addr) * 8); +} + +struct data data_append_byte(struct data d, uint8_t byte) +{ + return data_append_data(d, &byte, 1); +} + +struct data data_append_zeroes(struct data d, int len) +{ + d = data_grow_for(d, len); + + memset(d.val + d.len, 0, len); + d.len += len; + return d; +} + +struct data data_append_align(struct data d, int align) +{ + int newlen = ALIGN(d.len, align); + return data_append_zeroes(d, newlen - d.len); +} + +struct data data_add_marker(struct data d, enum markertype type, char *ref) +{ + struct marker *m; + + m = xmalloc(sizeof(*m)); + m->offset = d.len; + m->type = type; + m->ref = ref; + m->next = NULL; + + return data_append_markers(d, m); +} + +bool data_is_one_string(struct data d) +{ + int i; + int len = d.len; + + if (len == 0) + return false; + + for (i = 0; i < len-1; i++) + if (d.val[i] == '\0') + return false; + + if (d.val[len-1] != '\0') + return false; + + return true; +} diff --git a/src/net/scripts/dtc/dt_to_config b/src/net/scripts/dtc/dt_to_config new file mode 100755 index 0000000..299d1c2 --- /dev/null +++ b/src/net/scripts/dtc/dt_to_config @@ -0,0 +1,1212 @@ +#!/usr/bin/env perl +# SPDX-License-Identifier: GPL-2.0-only + +# Copyright 2016 by Frank Rowand +# Copyright 2016 by Gaurav Minocha +# + +use strict 'refs'; +use strict subs; + +use Getopt::Long; + +$VUFX = "160610a"; + +$script_name = $0; +$script_name =~ s|^.*/||; + + +# ----- constants for print_flags() + +# Position in string $pr_flags. Range of 0..($num_pr_flags - 1). +$pr_flag_pos_mcompatible = 0; +$pr_flag_pos_driver = 1; +$pr_flag_pos_mdriver = 2; +$pr_flag_pos_config = 3; +$pr_flag_pos_mconfig = 4; +$pr_flag_pos_node_not_enabled = 5; +$pr_flag_pos_white_list = 6; +$pr_flag_pos_hard_coded = 7; +$pr_flag_pos_config_hard_coded = 8; +$pr_flag_pos_config_none = 9; +$pr_flag_pos_config_m = 10; +$pr_flag_pos_config_y = 11; +$pr_flag_pos_config_test_fail = 12; + +$num_pr_flags = $pr_flag_pos_config_test_fail + 1; + +# flags in @pr_flag_value must be unique values to allow simple regular +# expessions to work for --include_flags and --exclude_flags. +# Convention: use upper case letters for potential issues or problems. + +@pr_flag_value = ('M', 'd', 'D', 'c', 'C', 'E', 'W', 'H', 'x', 'n', 'm', 'y', 'F'); + +@pr_flag_help = ( + "multiple compatibles found for this node", + "driver found for this compatible", + "multiple drivers found for this compatible", + "kernel config found for this driver", + "multiple config options found for this driver", + "node is not enabled", + "compatible is white listed", + "matching driver and/or kernel config is hard coded", + "kernel config hard coded in Makefile", + "one or more kernel config file options is not set", + "one or more kernel config file options is set to 'm'", + "one or more kernel config file options is set to 'y'", + "one of more kernel config file options fails to have correct value" +); + + +# ----- + +%driver_config = (); # driver config array, indexed by driver source file +%driver_count = (); # driver_cnt, indexed by compatible +%compat_driver = (); # compatible driver array, indexed by compatible +%existing_config = (); # existing config symbols present in given config file + # expected values are: "y", "m", a decimal number, a + # hex number, or a string + +# ----- magic compatibles, do not have a driver +# +# Will not search for drivers for these compatibles. + +%compat_white_list = ( + 'none' => '1', + 'pci' => '1', + 'simple-bus' => '1', +); + +# Will not search for drivers for these compatibles. +# +# These compatibles have a very large number of false positives. +# +# 'hardcoded_no_driver' is a magic value. Other code knows this +# magic value. Do not use 'no_driver' here! +# +# Revisit each 'hardcoded_no_driver' to see how the compatible +# is used. Are there drivers that can be provided? + +%driver_hard_code_list = ( + 'cache' => ['hardcoded_no_driver'], + 'eeprom' => ['hardcoded_no_driver'], + 'gpio' => ['hardcoded_no_driver'], + 'gpio-keys' => ['drivers/input/keyboard/gpio_keys.c'], + 'i2c-gpio' => ['drivers/i2c/busses/i2c-gpio.c'], + 'isa' => ['arch/mips/mti-malta/malta-dt.c', + 'arch/x86/kernel/devicetree.c'], + 'led' => ['hardcoded_no_driver'], + 'm25p32' => ['hardcoded_no_driver'], + 'm25p64' => ['hardcoded_no_driver'], + 'm25p80' => ['hardcoded_no_driver'], + 'mtd-ram' => ['drivers/mtd/maps/physmap_of.c'], + 'pwm-backlight' => ['drivers/video/backlight/pwm_bl.c'], + 'spidev' => ['hardcoded_no_driver'], + 'syscon' => ['drivers/mfd/syscon.c'], + 'tlv320aic23' => ['hardcoded_no_driver'], + 'wm8731' => ['hardcoded_no_driver'], +); + +# Use these config options instead of searching makefiles + +%driver_config_hard_code_list = ( + + # this one needed even if %driver_hard_code_list is empty + 'no_driver' => ['no_config'], + 'hardcoded_no_driver' => ['no_config'], + + # drivers/usb/host/ehci-ppc-of.c + # drivers/usb/host/ehci-xilinx-of.c + # are included from: + # drivers/usb/host/ehci-hcd.c + # thus the search of Makefile for the included .c files is incorrect + # ehci-hcd.c wraps the includes with ifdef CONFIG_USB_EHCI_HCD_..._OF + # + # similar model for ohci-hcd.c (but no ohci-xilinx-of.c) + # + # similarly, uhci-hcd.c includes uhci-platform.c + + 'drivers/usb/host/ehci-ppc-of.c' => ['CONFIG_USB_EHCI_HCD', + 'CONFIG_USB_EHCI_HCD_PPC_OF'], + 'drivers/usb/host/ohci-ppc-of.c' => ['CONFIG_USB_OHCI_HCD', + 'CONFIG_USB_OHCI_HCD_PPC_OF'], + + 'drivers/usb/host/ehci-xilinx-of.c' => ['CONFIG_USB_EHCI_HCD', + 'CONFIG_USB_EHCI_HCD_XILINX'], + + 'drivers/usb/host/uhci-platform.c' => ['CONFIG_USB_UHCI_HCD', + 'CONFIG_USB_UHCI_PLATFORM'], + + # scan_makefile will find only one of these config options: + # ifneq ($(CONFIG_SOC_IMX6)$(CONFIG_SOC_LS1021A),) + 'arch/arm/mach-imx/platsmp.c' => ['CONFIG_SOC_IMX6 && CONFIG_SMP', + 'CONFIG_SOC_LS1021A && CONFIG_SMP'], +); + + +# 'virt/kvm/arm/.*' are controlled by makefiles in other directories, +# using relative paths, such as 'KVM := ../../../virt/kvm'. Do not +# add complexity to find_kconfig() to deal with this. There is a long +# term intent to change the kvm related makefiles to the normal kernel +# style. After that is done, this entry can be removed from the +# black_list_driver. + +@black_list_driver = ( + # kvm no longer a problem after commit 503a62862e8f in 4.7-rc1 + # 'virt/kvm/arm/.*', +); + + +sub usage() +{ + print +" +Usage: $script_name [options] device-tree... + + device_tree is: dts_file | dtb_file | proc_device-tree + + +Valid options: + -c FILE Read kernel config options from FILE + --config FILE synonym for 'c' + --config-format config file friendly output format + --exclude-flag FLAG exclude entries with a matching flag + -h Display this message and exit + --help synonym for 'h' + --black-list-driver use driver black list + --white-list-config use config white list + --white-list-driver use driver white list + --include-flag FLAG include only entries with a matching flag + --include-suspect include only entries with an uppercase flag + --short-name do not show the path portion of the node name + --show-lists report of white and black lists + --version Display program version and exit + + + Report driver source files that match the compatibles in the device + tree file and the kernel config options that enable the driver source + files. + + This program must be run in the root directory of a Linux kernel + source tree. + + The default format is a report that is intended to be easily human + scannable. + + An alternate format can be selected by --config-format. This will + create output that can easily be edited to create a fragment that can + be appended to the existing kernel config file. Each entry consists of + multiple lines. The first line reports flags, the node path, compatible + value, driver file matching the compatible, configuration options, and + current values of the configuration options. For each configuration + option, the following lines report the current value and the value that + is required for the driver file to be included in the kernel. + + If a large number of drivers or config options is listed for a node, + and the '$pr_flag_value[$pr_flag_pos_hard_coded]' flag is set consider using --white-list-config and/or + --white-list-driver. If the white list option suppresses the correct + entry please report that as a bug. + + CAUTION: + This program uses heuristics to guess which driver(s) support each + compatible string and which config option(s) enables the driver(s). + Do not believe that the reported information is fully correct. + This program is intended to aid the process of determining the + proper kernel configuration for a device tree, but this is not + a fully automated process -- human involvement may still be + required! + + The driver match heuristic used is to search for source files + containing the compatible string enclosed in quotes. + + This program might not be able to find all drivers matching a + compatible string. + + Some makefiles are overly clever. This program was not made + complex enough to handle them. If no config option is listed + for a driver, look at the makefile for the driver source file. + Even if a config option is listed for a driver, some other + available config options may not be listed. + + FLAG values: +"; + + for ($k = 0; $k < $num_pr_flags; $k++) { + printf " %s %s\n", $pr_flag_value[$k], $pr_flag_help[$k]; + } + + print +" + Upper case letters indicate potential issues or problems. + + The flag: + +"; + + $k = $pr_flag_pos_hard_coded; + printf " %s %s\n", $pr_flag_value[$k], $pr_flag_help[$k]; + + print +" + will be set if the config or driver is in the white lists, even if + --white-list-config and --white-list-driver are not specified. + This is a hint that 1) many of these reported lines are likely to + be incorrect, and 2) using those options will reduce the number of + drivers and/or config options reported. + + --white-list-config and --white-list-driver may not be accurate if this + program is not well maintained. Use them with appropriate skepticism. + Use the --show-lists option to report the values in the list. + + Return value: + 0 if no error + 1 error processing command line + 2 unable to open or read kernel config file + 3 unable to open or process input device tree file(s) + + EXAMPLES: + + dt_to_config arch/arm/boot/dts/my_dts_file.dts + + Basic report. + + dt_to_config \\ + --config \${KBUILD_OUTPUT}/.config \\ + arch/\${ARCH}/boot/dts/my_dts_file.dts + + Full report, with config file issues noted. + + dt_to_config --include-suspect \\ + --config \${KBUILD_OUTPUT}/.config \\ + arch/\${ARCH}/boot/dts/my_dts_file.dts + + Report of node / compatible string / driver tuples that should + be further investigated. A node may have multiple compatible + strings. A compatible string may be matched by multiple drivers. + A driver may have config file issues noted. The compatible string + and/or driver may be in the white lists. + + dt_to_config --include-suspect --config-format \\ + --config ${KBUILD_OUTPUT}/.config \\ + arch/\${ARCH}/boot/dts/my_dts_file.dts + + Report of node / compatible string / driver tuples that should + be further investigated. The report can be edited to uncomment + the config options to select the desired tuple for a given node. + A node may have multiple compatible strings. A compatible string + may be matched by multiple drivers. A driver may have config file + issues noted. The compatible string and/or driver may be in the + white lists. + +"; +} + +sub set_flag() +{ + # pr_flags_ref is a reference to $pr_flags + + my $pr_flags_ref = shift; + my $pos = shift; + + substr $$pr_flags_ref, $pos, 1, $pr_flag_value[$pos]; + + return $pr_flags; +} + +sub print_flags() +{ + # return 1 if anything printed, else 0 + + # some fields of pn_arg_ref might not be used in this function, but + # extract all of them anyway. + my $pn_arg_ref = shift; + + my $compat = $pn_arg_ref->{compat}; + my $compatible_cnt = $pn_arg_ref->{compatible_cnt}; + my $config = $pn_arg_ref->{config}; + my $config_cnt = $pn_arg_ref->{config_cnt}; + my $driver = $pn_arg_ref->{driver}; + my $driver_cnt = $pn_arg_ref->{driver_cnt}; + my $full_node = $pn_arg_ref->{full_node}; + my $node = $pn_arg_ref->{node}; + my $node_enabled = $pn_arg_ref->{node_enabled}; + my $white_list = $pn_arg_ref->{white_list}; + + my $pr_flags = '-' x $num_pr_flags; + + + # ----- set flags in $pr_flags + + if ($compatible_cnt > 1) { + &set_flag(\$pr_flags, $pr_flag_pos_mcompatible); + } + + if ($config_cnt > 1) { + &set_flag(\$pr_flags, $pr_flag_pos_mconfig); + } + + if ($driver_cnt >= 1) { + &set_flag(\$pr_flags, $pr_flag_pos_driver); + } + + if ($driver_cnt > 1) { + &set_flag(\$pr_flags, $pr_flag_pos_mdriver); + } + + # These strings are the same way the linux kernel tests. + # The ePapr lists of values is slightly different. + if (!( + ($node_enabled eq "") || + ($node_enabled eq "ok") || + ($node_enabled eq "okay") + )) { + &set_flag(\$pr_flags, $pr_flag_pos_node_not_enabled); + } + + if ($white_list) { + &set_flag(\$pr_flags, $pr_flag_pos_white_list); + } + + if (exists($driver_hard_code_list{$compat}) || + (exists($driver_config_hard_code_list{$driver}) && + ($driver ne "no_driver"))) { + &set_flag(\$pr_flags, $pr_flag_pos_hard_coded); + } + + my @configs = split(' && ', $config); + for $configs (@configs) { + $not = $configs =~ /^!/; + $configs =~ s/^!//; + + if (($configs ne "no_config") && ($configs ne "no_makefile")) { + &set_flag(\$pr_flags, $pr_flag_pos_config); + } + + if (($config_cnt >= 1) && + ($configs !~ /CONFIG_/) && + (($configs ne "no_config") && ($configs ne "no_makefile"))) { + &set_flag(\$pr_flags, $pr_flag_pos_config_hard_coded); + } + + my $existing_config = $existing_config{$configs}; + if ($existing_config eq "m") { + &set_flag(\$pr_flags, $pr_flag_pos_config_m); + # Possible fail, depends on whether built in or + # module is desired. + &set_flag(\$pr_flags, $pr_flag_pos_config_test_fail); + } elsif ($existing_config eq "y") { + &set_flag(\$pr_flags, $pr_flag_pos_config_y); + if ($not) { + &set_flag(\$pr_flags, $pr_flag_pos_config_test_fail); + } + } elsif (($config_file) && ($configs =~ /CONFIG_/)) { + &set_flag(\$pr_flags, $pr_flag_pos_config_none); + if (!$not) { + &set_flag(\$pr_flags, $pr_flag_pos_config_test_fail); + } + } + } + + # ----- include / exclude filters + + if ($include_flag_pattern && ($pr_flags !~ m/$include_flag_pattern/)) { + return 0; + } + + if ($exclude_flag_pattern && ($pr_flags =~ m/$exclude_flag_pattern/)) { + return 0; + } + + if ($config_format) { + print "# "; + } + print "$pr_flags : "; + + return 1; +} + + +sub print_node() +{ + # return number of lines printed + + # some fields of pn_arg_ref might not be used in this function, but + # extract all of them anyway. + my $pn_arg_ref = shift; + + my $compat = $pn_arg_ref->{compat}; + my $compatible_cnt = $pn_arg_ref->{compatible_cnt}; + my $config = $pn_arg_ref->{config}; + my $config_cnt = $pn_arg_ref->{config_cnt}; + my $driver = $pn_arg_ref->{driver}; + my $driver_cnt = $pn_arg_ref->{driver_cnt}; + my $full_node = $pn_arg_ref->{full_node}; + my $node = $pn_arg_ref->{node}; + my $node_enabled = $pn_arg_ref->{node_enabled}; + my $white_list = $pn_arg_ref->{white_list}; + + my $separator; + + if (! &print_flags($pn_arg_ref)) { + return 0; + } + + + if ($short_name) { + print "$node"; + } else { + print "$full_node"; + } + print " : $compat : $driver : $config : "; + + my @configs = split(' && ', $config); + + if ($config_file) { + for $configs (@configs) { + $configs =~ s/^!//; + my $existing_config = $existing_config{$configs}; + if (!$existing_config) { + # check for /-m/, /-y/, or /-objs/ + if ($configs !~ /CONFIG_/) { + $existing_config = "x"; + }; + }; + if ($existing_config) { + print "$separator", "$existing_config"; + $separator = ", "; + } else { + print "$separator", "n"; + $separator = ", "; + } + } + } else { + print "none"; + } + + print "\n"; + + if ($config_format) { + for $configs (@configs) { + $not = $configs =~ /^!/; + $configs =~ s/^!//; + my $existing_config = $existing_config{$configs}; + + if ($not) { + if ($configs !~ /CONFIG_/) { + print "# $configs\n"; + } elsif ($existing_config eq "m") { + print "# $configs is m\n"; + print "# $configs=n\n"; + } elsif ($existing_config eq "y") { + print "# $configs is set\n"; + print "# $configs=n\n"; + } else { + print "# $configs is not set\n"; + print "# $configs=n\n"; + } + + } else { + if ($configs !~ /CONFIG_/) { + print "# $configs\n"; + } elsif ($existing_config eq "m") { + print "# $configs is m\n"; + print "# $configs=y\n"; + } elsif ($existing_config eq "y") { + print "# $configs is set\n"; + print "# $configs=y\n"; + } else { + print "# $configs is not set\n"; + print "# $configs=y\n"; + } + } + } + } + + return 1; +} + + +sub scan_makefile +{ + my $pn_arg_ref = shift; + my $driver = shift; + + # ----- Find Kconfig symbols that enable driver + + my ($dir, $base) = $driver =~ m{(.*)/(.*).c}; + + my $makefile = $dir . "/Makefile"; + if (! -r $makefile) { + $makefile = $dir . "/Kbuild"; + } + if (! -r $makefile) { + my $config; + + $config = 'no_makefile'; + push @{ $driver_config{$driver} }, $config; + return; + } + + if (!open(MAKEFILE_FILE, "<", "$makefile")) { + return; + } + + my $line; + my @config; + my @if_config; + my @make_var; + + NEXT_LINE: + while ($next_line = <MAKEFILE_FILE>) { + my $config; + my $if_config; + my $ifdef; + my $ifeq; + my $ifndef; + my $ifneq; + my $ifdef_config; + my $ifeq_config; + my $ifndef_config; + my $ifneq_config; + + chomp($next_line); + $line = $line . $next_line; + if ($next_line =~ /\\$/) { + $line =~ s/\\$/ /; + next NEXT_LINE; + } + if ($line =~ /^\s*#/) { + $line = ""; + next NEXT_LINE; + } + + # ----- condition ... else ... endif + + if ($line =~ /^([ ]\s*|)else\b/) { + $if_config = "!" . pop @if_config; + $if_config =~ s/^!!//; + push @if_config, $if_config; + $line =~ s/^([ ]\s*|)else\b//; + } + + ($null, $ifeq_config, $ifeq_config_val ) = $line =~ /^([ ]\s*|)ifeq\b.*\b(CONFIG_[A-Za-z0-9_]*)(.*)/; + ($null, $ifneq_config, $ifneq_config_val) = $line =~ /^([ ]\s*|)ifneq\b.*\b(CONFIG_[A-Za-z0-9_]*)(.*)/; + ($null, $ifdef_config) = $line =~ /^([ ]\s*|)ifdef\b.*\b(CONFIG_[A-Za-z0-9_]*)/; + ($null, $ifndef_config) = $line =~ /^([ ]\s*|)ifndef\b.*\b(CONFIG_[A-Za-z0-9_]*)/; + + ($null, $ifeq) = $line =~ /^([ ]\s*|)ifeq\b\s*(.*)/; + ($null, $ifneq) = $line =~ /^([ ]\s*|)ifneq\b\s*(.*)/; + ($null, $ifdef) = $line =~ /^([ ]\s*|)ifdef\b\s*(.*)/; + ($null, $ifndef) = $line =~ /^([ ]\s*|)ifndef\b\s*(.*)/; + + # Order of tests is important. Prefer "CONFIG_*" regex match over + # less specific regex match. + if ($ifdef_config) { + $if_config = $ifdef_config; + } elsif ($ifeq_config) { + if ($ifeq_config_val =~ /y/) { + $if_config = $ifeq_config; + } else { + $if_config = "!" . $ifeq_config; + } + } elsif ($ifndef_config) { + $if_config = "!" . $ifndef_config; + } elsif ($ifneq_config) { + if ($ifneq_config_val =~ /y/) { + $if_config = "!" . $ifneq_config; + } else { + $if_config = $ifneq_config; + } + } elsif ($ifdef) { + $if_config = $ifdef; + } elsif ($ifeq) { + $if_config = $ifeq; + } elsif ($ifndef) { + $if_config = "!" . $ifndef; + } elsif ($ifneq) { + $if_config = "!" . $ifneq; + } else { + $if_config = ""; + } + $if_config =~ s/^!!//; + + if ($if_config) { + push @if_config, $if_config; + $line = ""; + next NEXT_LINE; + } + + if ($line =~ /^([ ]\s*|)endif\b/) { + pop @if_config; + $line = ""; + next NEXT_LINE; + } + + # ----- simple CONFIG_* = *.[co] or xxx [+:?]*= *.[co] + # Most makefiles select on *.o, but + # arch/powerpc/boot/Makefile selects on *.c + + ($config) = $line =~ /(CONFIG_[A-Za-z0-9_]+).*\b$base.[co]\b/; + + # ----- match a make variable instead of *.[co] + # Recursively expanded variables are not handled. + + if (!$config) { + my $make_var; + ($make_var) = $line =~ /\s*(\S+?)\s*[+:\?]*=.*\b$base.[co]\b/; + if ($make_var) { + if ($make_var =~ /[a-zA-Z0-9]+-[ym]/) { + $config = $make_var; + } elsif ($make_var =~ /[a-zA-Z0-9]+-objs/) { + $config = $make_var; + } else { + push @make_var, $make_var; + } + } + } + + if (!$config) { + for $make_var (@make_var) { + ($config) = $line =~ /(CONFIG_[A-Za-z0-9_]+).*\b$make_var\b/; + last if ($config); + } + } + + if (!$config) { + for $make_var (@make_var) { + ($config) = $line =~ /\s*(\S+?)\s*[+:\?]*=.*\b$make_var\b/; + last if ($config); + } + } + + # ----- next if no config found + + if (!$config) { + $line = ""; + next NEXT_LINE; + } + + for $if_config (@if_config) { + $config = $if_config . " && " . $config; + } + + push @{ $driver_config{$driver} }, $config; + + $line = ""; + } + + close(MAKEFILE_FILE); + +} + + +sub find_kconfig +{ + my $pn_arg_ref = shift; + my $driver = shift; + + my $lines_printed = 0; + my @configs; + + if (!@{ $driver_config{$driver} }) { + &scan_makefile($pn_arg_ref, $driver); + if (!@{ $driver_config{$driver} }) { + push @{ $driver_config{$driver} }, "no_config"; + } + } + + @configs = @{ $driver_config{$driver} }; + + $$pn_arg_ref{config_cnt} = $#configs + 1; + for my $config (@configs) { + $$pn_arg_ref{config} = $config; + $lines_printed += &print_node($pn_arg_ref); + } + + return $lines_printed; +} + + +sub handle_compatible() +{ + my $full_node = shift; + my $node = shift; + my $compatible = shift; + my $node_enabled = shift; + + my $compat; + my $lines_printed = 0; + my %pn_arg = (); + + return if (!$node or !$compatible); + + # Do not process compatible property of root node, + # it is used to match board, not to bind a driver. + return if ($node eq "/"); + + $pn_arg{full_node} = $full_node; + $pn_arg{node} = $node; + $pn_arg{node_enabled} = $node_enabled; + + my @compatibles = split('", "', $compatible); + + $compatibles[0] =~ s/^"//; + $compatibles[$#compatibles] =~ s/"$//; + + $pn_arg{compatible_cnt} = $#compatibles + 1; + + COMPAT: + for $compat (@compatibles) { + + $pn_arg{compat} = $compat; + $pn_arg{driver_cnt} = 0; + $pn_arg{white_list} = 0; + + if (exists($compat_white_list{$compat})) { + $pn_arg{white_list} = 1; + $pn_arg{driver} = "no_driver"; + $pn_arg{config_cnt} = 1; + $pn_arg{config} = "no_config"; + $lines_printed += &print_node(\%pn_arg); + next COMPAT; + } + + # ----- if compat previously seen, use cached info + + if (exists($compat_driver{$compat})) { + for my $driver (@{ $compat_driver{$compat} }) { + $pn_arg{driver} = $driver; + $pn_arg{driver_cnt} = $driver_count{$compat}; + $pn_arg{config_cnt} = $#{ $driver_config{$driver}} + 1; + + for my $config (@{ $driver_config{$driver} }) { + $pn_arg{config} = $config; + $lines_printed += &print_node(\%pn_arg); + } + + if (!@{ $driver_config{$driver} }) { + # no config cached yet + # $driver in %driver_hard_code_list + # but not %driver_config_hard_code_list + $lines_printed += &find_kconfig(\%pn_arg, $driver); + } + } + next COMPAT; + } + + + # ----- Find drivers (source files that contain compatible) + + # this will miss arch/sparc/include/asm/parport.h + # It is better to move the compatible out of the .h + # than to add *.h. to the files list, because *.h generates + # a lot of false negatives. + my $files = '"*.c"'; + my $drivers = `git grep -l '"$compat"' -- $files`; + chomp($drivers); + if ($drivers eq "") { + $pn_arg{driver} = "no_driver"; + $pn_arg{config_cnt} = 1; + $pn_arg{config} = "no_config"; + push @{ $compat_driver{$compat} }, "no_driver"; + $lines_printed += &print_node(\%pn_arg); + next COMPAT; + } + + my @drivers = split("\n", $drivers); + $driver_count{$compat} = $#drivers + 1; + $pn_arg{driver_cnt} = $#drivers + 1; + + DRIVER: + for my $driver (@drivers) { + push @{ $compat_driver{$compat} }, $driver; + $pn_arg{driver} = $driver; + + # ----- if driver previously seen, use cached info + + $pn_arg{config_cnt} = $#{ $driver_config{$driver} } + 1; + for my $config (@{ $driver_config{$driver} }) { + $pn_arg{config} = $config; + $lines_printed += &print_node(\%pn_arg); + } + if (@{ $driver_config{$driver} }) { + next DRIVER; + } + + if ($black_list_driver) { + for $black (@black_list_driver) { + next DRIVER if ($driver =~ /^$black$/); + } + } + + + # ----- Find Kconfig symbols that enable driver + + $lines_printed += &find_kconfig(\%pn_arg, $driver); + + } + } + + # White space (line) between nodes for readability. + # Each node may report several compatibles. + # For each compatible, multiple drivers may be reported. + # For each driver, multiple CONFIG_ options may be reported. + if ($lines_printed) { + print "\n"; + } +} + +sub read_dts() +{ + my $file = shift; + + my $compatible = ""; + my $line; + my $node = ""; + my $node_enabled = ""; + + if (! -r $file) { + print STDERR "file '$file' is not readable or does not exist\n"; + exit 3; + } + + if (!open(DT_FILE, "-|", "$dtx_diff $file")) { + print STDERR "\n"; + print STDERR "shell command failed:\n"; + print STDERR " $dtx_diff $file\n"; + print STDERR "\n"; + exit 3; + } + + FILE: + while ($line = <DT_FILE>) { + chomp($line); + + if ($line =~ /{/) { + + &handle_compatible($full_node, $node, $compatible, + $node_enabled); + + while ($end_node_count-- > 0) { + pop @full_node; + }; + $end_node_count = 0; + $full_node = @full_node[-1]; + + $node = $line; + $node =~ s/^\s*(.*)\s+\{.*/$1/; + $node =~ s/.*: //; + if ($node eq '/' ) { + $full_node = '/'; + } elsif ($full_node ne '/') { + $full_node = $full_node . '/' . $node; + } else { + $full_node = '/' . $node; + } + push @full_node, $full_node; + + $compatible = ""; + $node_enabled = ""; + next FILE; + } + + if ($line =~ /}/) { + $end_node_count++; + } + + if ($line =~ /(\s+|^)status =/) { + $node_enabled = $line; + $node_enabled =~ s/^\t*//; + $node_enabled =~ s/^status = "//; + $node_enabled =~ s/";$//; + next FILE; + } + + if ($line =~ /(\s+|^)compatible =/) { + # Extract all compatible entries for this device + # White space matching here and in handle_compatible() is + # precise, because input format is the output of dtc, + # which is invoked by dtx_diff. + $compatible = $line; + $compatible =~ s/^\t*//; + $compatible =~ s/^compatible = //; + $compatible =~ s/;$//; + } + } + + &handle_compatible($full_node, $node, $compatible, $node_enabled); + + close(DT_FILE); +} + + +sub read_config_file() +{ + if (! -r $config_file) { + print STDERR "file '$config_file' is not readable or does not exist\n"; + exit 2; + } + + if (!open(CONFIG_FILE, "<", "$config_file")) { + print STDERR "open $config_file failed\n"; + exit 2; + } + + my @line; + + LINE: + while ($line = <CONFIG_FILE>) { + chomp($line); + next LINE if ($line =~ /^\s*#/); + next LINE if ($line =~ /^\s*$/); + @line = split /=/, $line; + $existing_config{@line[0]} = @line[1]; + } + + close(CONFIG_FILE); +} + + +sub cmd_line_err() +{ + my $msg = shift; + + print STDERR "\n"; + print STDERR " ERROR processing command line options\n"; + print STDERR " $msg\n" if ($msg ne ""); + print STDERR "\n"; + print STDERR " For help, type '$script_name --help'\n"; + print STDERR "\n"; +} + + +# ----------------------------------------------------------------------------- +# program entry point + +Getopt::Long::Configure("no_ignore_case", "bundling"); + +if (!GetOptions( + "c=s" => \$config_file, + "config=s" => \$config_file, + "config-format" => \$config_format, + "exclude-flag=s" => \@exclude_flag, + "h" => \$help, + "help" => \$help, + "black-list-driver" => \$black_list_driver, + "white-list-config" => \$white_list_config, + "white-list-driver" => \$white_list_driver, + "include-flag=s" => \@include_flag, + "include-suspect" => \$include_suspect, + "short-name" => \$short_name, + "show-lists" => \$show_lists, + "version" => \$version, + )) { + + &cmd_line_err(); + + exit 1; +} + + +my $exit_after_messages = 0; + +if ($version) { + print STDERR "\n$script_name $VUFX\n\n"; + $exit_after_messages = 1; +} + + +if ($help) { + &usage; + $exit_after_messages = 1; +} + + +if ($show_lists) { + + print "\n"; + print "These compatibles are hard coded to have no driver.\n"; + print "\n"; + for my $compat (sort keys %compat_white_list) { + print " $compat\n"; + } + + + print "\n\n"; + print "The driver for these compatibles is hard coded (white list).\n"; + print "\n"; + my $max_compat_len = 0; + for my $compat (sort keys %driver_hard_code_list) { + if (length $compat > $max_compat_len) { + $max_compat_len = length $compat; + } + } + for my $compat (sort keys %driver_hard_code_list) { + if (($driver ne "hardcoded_no_driver") && ($driver ne "no_driver")) { + my $first = 1; + for my $driver (@{ $driver_hard_code_list{$compat} }) { + if ($first) { + print " $compat"; + print " " x ($max_compat_len - length $compat); + $first = 0; + } else { + print " ", " " x $max_compat_len; + } + print " $driver\n"; + } + } + } + + + print "\n\n"; + print "The configuration option for these drivers is hard coded (white list).\n"; + print "\n"; + my $max_driver_len = 0; + for my $driver (sort keys %driver_config_hard_code_list) { + if (length $driver > $max_driver_len) { + $max_driver_len = length $driver; + } + } + for my $driver (sort keys %driver_config_hard_code_list) { + if (($driver ne "hardcoded_no_driver") && ($driver ne "no_driver")) { + my $first = 1; + for my $config (@{ $driver_config_hard_code_list{$driver} }) { + if ($first) { + print " $driver"; + print " " x ($max_driver_len - length $driver); + $first = 0; + } else { + print " ", " " x $max_driver_len; + } + print " $config\n"; + } + } + } + + + print "\n\n"; + print "These drivers are black listed.\n"; + print "\n"; + for my $driver (@black_list_driver) { + print " $driver\n"; + } + + print "\n"; + + $exit_after_messages = 1; +} + + +if ($exit_after_messages) { + exit 0; +} + + +$exclude_flag_pattern = "["; +for my $exclude_flag (@exclude_flag) { + $exclude_flag_pattern = $exclude_flag_pattern . $exclude_flag; +} +$exclude_flag_pattern = $exclude_flag_pattern . "]"; +# clean up if empty +$exclude_flag_pattern =~ s/^\[\]$//; + + +$include_flag_pattern = "["; +for my $include_flag (@include_flag) { + $include_flag_pattern = $include_flag_pattern . $include_flag; +} +$include_flag_pattern = $include_flag_pattern . "]"; +# clean up if empty +$include_flag_pattern =~ s/^\[\]$//; + + +if ($exclude_flag_pattern) { + my $found = 0; + for $pr_flag_value (@pr_flag_value) { + if ($exclude_flag_pattern =~ m/$pr_flag_value/) { + $found = 1; + } + } + if (!$found) { + &cmd_line_err("invalid value for FLAG in --exclude-flag\n"); + exit 1 + } +} + +if ($include_flag_pattern) { + my $found = 0; + for $pr_flag_value (@pr_flag_value) { + if ($include_flag_pattern =~ m/$pr_flag_value/) { + $found = 1; + } + } + if (!$found) { + &cmd_line_err("invalid value for FLAG in --include-flag\n"); + exit 1 + } +} + +if ($include_suspect) { + $include_flag_pattern =~ s/\[//; + $include_flag_pattern =~ s/\]//; + $include_flag_pattern = "[" . $include_flag_pattern . "A-Z]"; +} + +if ($exclude_flag_pattern =~ m/$include_flag_pattern/) { + &cmd_line_err("the same flag appears in both --exclude-flag and --include-flag or --include-suspect\n"); + exit 1 +} + + +# ($#ARGV < 0) is valid for --help, --version +if ($#ARGV < 0) { + &cmd_line_err("device-tree... is required"); + exit 1 +} + + +if ($config_file) { + &read_config_file(); +} + + +# avoid pushing duplicates for this value +$driver = "hardcoded_no_driver"; +for $config ( @{ $driver_config_hard_code_list{$driver} } ) { + push @{ $driver_config{$driver} }, $config; +} + +if ($white_list_driver) { + for my $compat (keys %driver_hard_code_list) { + for my $driver (@{ $driver_hard_code_list{$compat} }) { + push @{ $compat_driver{$compat} }, $driver; + if ($driver ne "hardcoded_no_driver") { + $driver_count{$compat} = scalar @{ $compat_driver{$compat} }; + } + } + } +} + +if ($white_list_config) { + for my $driver (keys %driver_config_hard_code_list) { + if ($driver ne "hardcoded_no_driver") { + for $config ( @{ $driver_config_hard_code_list{$driver} } ) { + push @{ $driver_config{$driver} }, $config; + } + } + } +} + +if (-x "scripts/dtc/dtx_diff") { + $dtx_diff = "scripts/dtc/dtx_diff"; +} else { + + print STDERR "\n"; + print STDERR "$script_name must be run from the root directory of a Linux kernel tree\n"; + print STDERR "\n"; + exit 3; +} + +for $file (@ARGV) { + &read_dts($file); +} diff --git a/src/net/scripts/dtc/dtc-lexer.l b/src/net/scripts/dtc/dtc-lexer.l new file mode 100644 index 0000000..b3b7270 --- /dev/null +++ b/src/net/scripts/dtc/dtc-lexer.l @@ -0,0 +1,297 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * (C) Copyright David Gibson <dwg@au1.ibm.com>, IBM Corporation. 2005. + */ + +%option noyywrap nounput noinput never-interactive + +%x BYTESTRING +%x PROPNODENAME +%s V1 + +PROPNODECHAR [a-zA-Z0-9,._+*#?@-] +PATHCHAR ({PROPNODECHAR}|[/]) +LABEL [a-zA-Z_][a-zA-Z0-9_]* +STRING \"([^\\"]|\\.)*\" +CHAR_LITERAL '([^']|\\')*' +WS [[:space:]] +COMMENT "/*"([^*]|\*+[^*/])*\*+"/" +LINECOMMENT "//".*\n + +%{ +#include "dtc.h" +#include "srcpos.h" +#include "dtc-parser.tab.h" + +extern bool treesource_error; + +/* CAUTION: this will stop working if we ever use yyless() or yyunput() */ +#define YY_USER_ACTION \ + { \ + srcpos_update(&yylloc, yytext, yyleng); \ + } + +/*#define LEXDEBUG 1*/ + +#ifdef LEXDEBUG +#define DPRINT(fmt, ...) fprintf(stderr, fmt, ##__VA_ARGS__) +#else +#define DPRINT(fmt, ...) do { } while (0) +#endif + +static int dts_version = 1; + +#define BEGIN_DEFAULT() DPRINT("<V1>\n"); \ + BEGIN(V1); \ + +static void push_input_file(const char *filename); +static bool pop_input_file(void); +static void PRINTF(1, 2) lexical_error(const char *fmt, ...); + +%} + +%% +<*>"/include/"{WS}*{STRING} { + char *name = strchr(yytext, '\"') + 1; + yytext[yyleng-1] = '\0'; + push_input_file(name); + } + +<*>^"#"(line)?[ \t]+[0-9]+[ \t]+{STRING}([ \t]+[0-9]+)? { + char *line, *fnstart, *fnend; + struct data fn; + /* skip text before line # */ + line = yytext; + while (!isdigit((unsigned char)*line)) + line++; + + /* regexp ensures that first and list " + * in the whole yytext are those at + * beginning and end of the filename string */ + fnstart = memchr(yytext, '"', yyleng); + for (fnend = yytext + yyleng - 1; + *fnend != '"'; fnend--) + ; + assert(fnstart && fnend && (fnend > fnstart)); + + fn = data_copy_escape_string(fnstart + 1, + fnend - fnstart - 1); + + /* Don't allow nuls in filenames */ + if (memchr(fn.val, '\0', fn.len - 1)) + lexical_error("nul in line number directive"); + + /* -1 since #line is the number of the next line */ + srcpos_set_line(xstrdup(fn.val), atoi(line) - 1); + data_free(fn); + } + +<*><<EOF>> { + if (!pop_input_file()) { + yyterminate(); + } + } + +<*>{STRING} { + DPRINT("String: %s\n", yytext); + yylval.data = data_copy_escape_string(yytext+1, + yyleng-2); + return DT_STRING; + } + +<*>"/dts-v1/" { + DPRINT("Keyword: /dts-v1/\n"); + dts_version = 1; + BEGIN_DEFAULT(); + return DT_V1; + } + +<*>"/plugin/" { + DPRINT("Keyword: /plugin/\n"); + return DT_PLUGIN; + } + +<*>"/memreserve/" { + DPRINT("Keyword: /memreserve/\n"); + BEGIN_DEFAULT(); + return DT_MEMRESERVE; + } + +<*>"/bits/" { + DPRINT("Keyword: /bits/\n"); + BEGIN_DEFAULT(); + return DT_BITS; + } + +<*>"/delete-property/" { + DPRINT("Keyword: /delete-property/\n"); + DPRINT("<PROPNODENAME>\n"); + BEGIN(PROPNODENAME); + return DT_DEL_PROP; + } + +<*>"/delete-node/" { + DPRINT("Keyword: /delete-node/\n"); + DPRINT("<PROPNODENAME>\n"); + BEGIN(PROPNODENAME); + return DT_DEL_NODE; + } + +<*>"/omit-if-no-ref/" { + DPRINT("Keyword: /omit-if-no-ref/\n"); + DPRINT("<PROPNODENAME>\n"); + BEGIN(PROPNODENAME); + return DT_OMIT_NO_REF; + } + +<*>{LABEL}: { + DPRINT("Label: %s\n", yytext); + yylval.labelref = xstrdup(yytext); + yylval.labelref[yyleng-1] = '\0'; + return DT_LABEL; + } + +<V1>([0-9]+|0[xX][0-9a-fA-F]+)(U|L|UL|LL|ULL)? { + char *e; + DPRINT("Integer Literal: '%s'\n", yytext); + + errno = 0; + yylval.integer = strtoull(yytext, &e, 0); + + if (*e && e[strspn(e, "UL")]) { + lexical_error("Bad integer literal '%s'", + yytext); + } + + if (errno == ERANGE) + lexical_error("Integer literal '%s' out of range", + yytext); + else + /* ERANGE is the only strtoull error triggerable + * by strings matching the pattern */ + assert(errno == 0); + return DT_LITERAL; + } + +<*>{CHAR_LITERAL} { + struct data d; + DPRINT("Character literal: %s\n", yytext); + + d = data_copy_escape_string(yytext+1, yyleng-2); + if (d.len == 1) { + lexical_error("Empty character literal"); + yylval.integer = 0; + } else { + yylval.integer = (unsigned char)d.val[0]; + + if (d.len > 2) + lexical_error("Character literal has %d" + " characters instead of 1", + d.len - 1); + } + + data_free(d); + return DT_CHAR_LITERAL; + } + +<*>\&{LABEL} { /* label reference */ + DPRINT("Ref: %s\n", yytext+1); + yylval.labelref = xstrdup(yytext+1); + return DT_LABEL_REF; + } + +<*>"&{/"{PATHCHAR}*\} { /* new-style path reference */ + yytext[yyleng-1] = '\0'; + DPRINT("Ref: %s\n", yytext+2); + yylval.labelref = xstrdup(yytext+2); + return DT_PATH_REF; + } + +<BYTESTRING>[0-9a-fA-F]{2} { + yylval.byte = strtol(yytext, NULL, 16); + DPRINT("Byte: %02x\n", (int)yylval.byte); + return DT_BYTE; + } + +<BYTESTRING>"]" { + DPRINT("/BYTESTRING\n"); + BEGIN_DEFAULT(); + return ']'; + } + +<PROPNODENAME>\\?{PROPNODECHAR}+ { + DPRINT("PropNodeName: %s\n", yytext); + yylval.propnodename = xstrdup((yytext[0] == '\\') ? + yytext + 1 : yytext); + BEGIN_DEFAULT(); + return DT_PROPNODENAME; + } + +"/incbin/" { + DPRINT("Binary Include\n"); + return DT_INCBIN; + } + +<*>{WS}+ /* eat whitespace */ +<*>{COMMENT}+ /* eat C-style comments */ +<*>{LINECOMMENT}+ /* eat C++-style comments */ + +<*>"<<" { return DT_LSHIFT; }; +<*>">>" { return DT_RSHIFT; }; +<*>"<=" { return DT_LE; }; +<*>">=" { return DT_GE; }; +<*>"==" { return DT_EQ; }; +<*>"!=" { return DT_NE; }; +<*>"&&" { return DT_AND; }; +<*>"||" { return DT_OR; }; + +<*>. { + DPRINT("Char: %c (\\x%02x)\n", yytext[0], + (unsigned)yytext[0]); + if (yytext[0] == '[') { + DPRINT("<BYTESTRING>\n"); + BEGIN(BYTESTRING); + } + if ((yytext[0] == '{') + || (yytext[0] == ';')) { + DPRINT("<PROPNODENAME>\n"); + BEGIN(PROPNODENAME); + } + return yytext[0]; + } + +%% + +static void push_input_file(const char *filename) +{ + assert(filename); + + srcfile_push(filename); + + yyin = current_srcfile->f; + + yypush_buffer_state(yy_create_buffer(yyin, YY_BUF_SIZE)); +} + + +static bool pop_input_file(void) +{ + if (srcfile_pop() == 0) + return false; + + yypop_buffer_state(); + yyin = current_srcfile->f; + + return true; +} + +static void lexical_error(const char *fmt, ...) +{ + va_list ap; + + va_start(ap, fmt); + srcpos_verror(&yylloc, "Lexical error", fmt, ap); + va_end(ap); + + treesource_error = true; +} diff --git a/src/net/scripts/dtc/dtc-parser.y b/src/net/scripts/dtc/dtc-parser.y new file mode 100644 index 0000000..a0316a3 --- /dev/null +++ b/src/net/scripts/dtc/dtc-parser.y @@ -0,0 +1,576 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (C) Copyright David Gibson <dwg@au1.ibm.com>, IBM Corporation. 2005. + */ +%locations + +%{ +#include <stdio.h> +#include <inttypes.h> + +#include "dtc.h" +#include "srcpos.h" + +extern int yylex(void); +extern void yyerror(char const *s); +#define ERROR(loc, ...) \ + do { \ + srcpos_error((loc), "Error", __VA_ARGS__); \ + treesource_error = true; \ + } while (0) + +#define YYERROR_CALL(msg) yyerror(msg) + +extern struct dt_info *parser_output; +extern bool treesource_error; +%} + +%union { + char *propnodename; + char *labelref; + uint8_t byte; + struct data data; + + struct { + struct data data; + int bits; + } array; + + struct property *prop; + struct property *proplist; + struct node *node; + struct node *nodelist; + struct reserve_info *re; + uint64_t integer; + unsigned int flags; +} + +%token DT_V1 +%token DT_PLUGIN +%token DT_MEMRESERVE +%token DT_LSHIFT DT_RSHIFT DT_LE DT_GE DT_EQ DT_NE DT_AND DT_OR +%token DT_BITS +%token DT_DEL_PROP +%token DT_DEL_NODE +%token DT_OMIT_NO_REF +%token <propnodename> DT_PROPNODENAME +%token <integer> DT_LITERAL +%token <integer> DT_CHAR_LITERAL +%token <byte> DT_BYTE +%token <data> DT_STRING +%token <labelref> DT_LABEL +%token <labelref> DT_LABEL_REF +%token <labelref> DT_PATH_REF +%token DT_INCBIN + +%type <data> propdata +%type <data> propdataprefix +%type <flags> header +%type <flags> headers +%type <re> memreserve +%type <re> memreserves +%type <array> arrayprefix +%type <data> bytestring +%type <prop> propdef +%type <proplist> proplist +%type <labelref> dt_ref + +%type <node> devicetree +%type <node> nodedef +%type <node> subnode +%type <nodelist> subnodes + +%type <integer> integer_prim +%type <integer> integer_unary +%type <integer> integer_mul +%type <integer> integer_add +%type <integer> integer_shift +%type <integer> integer_rela +%type <integer> integer_eq +%type <integer> integer_bitand +%type <integer> integer_bitxor +%type <integer> integer_bitor +%type <integer> integer_and +%type <integer> integer_or +%type <integer> integer_trinary +%type <integer> integer_expr + +%% + +sourcefile: + headers memreserves devicetree + { + parser_output = build_dt_info($1, $2, $3, + guess_boot_cpuid($3)); + } + ; + +header: + DT_V1 ';' + { + $$ = DTSF_V1; + } + | DT_V1 ';' DT_PLUGIN ';' + { + $$ = DTSF_V1 | DTSF_PLUGIN; + } + ; + +headers: + header + | header headers + { + if ($2 != $1) + ERROR(&@2, "Header flags don't match earlier ones"); + $$ = $1; + } + ; + +memreserves: + /* empty */ + { + $$ = NULL; + } + | memreserve memreserves + { + $$ = chain_reserve_entry($1, $2); + } + ; + +memreserve: + DT_MEMRESERVE integer_prim integer_prim ';' + { + $$ = build_reserve_entry($2, $3); + } + | DT_LABEL memreserve + { + add_label(&$2->labels, $1); + $$ = $2; + } + ; + +dt_ref: DT_LABEL_REF | DT_PATH_REF; + +devicetree: + '/' nodedef + { + $$ = name_node($2, ""); + } + | devicetree '/' nodedef + { + $$ = merge_nodes($1, $3); + } + | dt_ref nodedef + { + /* + * We rely on the rule being always: + * versioninfo plugindecl memreserves devicetree + * so $-1 is what we want (plugindecl) + */ + if (!($<flags>-1 & DTSF_PLUGIN)) + ERROR(&@2, "Label or path %s not found", $1); + $$ = add_orphan_node( + name_node(build_node(NULL, NULL, NULL), + ""), + $2, $1); + } + | devicetree DT_LABEL dt_ref nodedef + { + struct node *target = get_node_by_ref($1, $3); + + if (target) { + add_label(&target->labels, $2); + merge_nodes(target, $4); + } else + ERROR(&@3, "Label or path %s not found", $3); + $$ = $1; + } + | devicetree DT_PATH_REF nodedef + { + /* + * We rely on the rule being always: + * versioninfo plugindecl memreserves devicetree + * so $-1 is what we want (plugindecl) + */ + if ($<flags>-1 & DTSF_PLUGIN) { + add_orphan_node($1, $3, $2); + } else { + struct node *target = get_node_by_ref($1, $2); + + if (target) + merge_nodes(target, $3); + else + ERROR(&@2, "Label or path %s not found", $2); + } + $$ = $1; + } + | devicetree DT_LABEL_REF nodedef + { + struct node *target = get_node_by_ref($1, $2); + + if (target) { + merge_nodes(target, $3); + } else { + /* + * We rely on the rule being always: + * versioninfo plugindecl memreserves devicetree + * so $-1 is what we want (plugindecl) + */ + if ($<flags>-1 & DTSF_PLUGIN) + add_orphan_node($1, $3, $2); + else + ERROR(&@2, "Label or path %s not found", $2); + } + $$ = $1; + } + | devicetree DT_DEL_NODE dt_ref ';' + { + struct node *target = get_node_by_ref($1, $3); + + if (target) + delete_node(target); + else + ERROR(&@3, "Label or path %s not found", $3); + + + $$ = $1; + } + | devicetree DT_OMIT_NO_REF dt_ref ';' + { + struct node *target = get_node_by_ref($1, $3); + + if (target) + omit_node_if_unused(target); + else + ERROR(&@3, "Label or path %s not found", $3); + + + $$ = $1; + } + ; + +nodedef: + '{' proplist subnodes '}' ';' + { + $$ = build_node($2, $3, &@$); + } + ; + +proplist: + /* empty */ + { + $$ = NULL; + } + | proplist propdef + { + $$ = chain_property($2, $1); + } + ; + +propdef: + DT_PROPNODENAME '=' propdata ';' + { + $$ = build_property($1, $3, &@$); + } + | DT_PROPNODENAME ';' + { + $$ = build_property($1, empty_data, &@$); + } + | DT_DEL_PROP DT_PROPNODENAME ';' + { + $$ = build_property_delete($2); + } + | DT_LABEL propdef + { + add_label(&$2->labels, $1); + $$ = $2; + } + ; + +propdata: + propdataprefix DT_STRING + { + $$ = data_merge($1, $2); + } + | propdataprefix arrayprefix '>' + { + $$ = data_merge($1, $2.data); + } + | propdataprefix '[' bytestring ']' + { + $$ = data_merge($1, $3); + } + | propdataprefix dt_ref + { + $1 = data_add_marker($1, TYPE_STRING, $2); + $$ = data_add_marker($1, REF_PATH, $2); + } + | propdataprefix DT_INCBIN '(' DT_STRING ',' integer_prim ',' integer_prim ')' + { + FILE *f = srcfile_relative_open($4.val, NULL); + struct data d; + + if ($6 != 0) + if (fseek(f, $6, SEEK_SET) != 0) + die("Couldn't seek to offset %llu in \"%s\": %s", + (unsigned long long)$6, $4.val, + strerror(errno)); + + d = data_copy_file(f, $8); + + $$ = data_merge($1, d); + fclose(f); + } + | propdataprefix DT_INCBIN '(' DT_STRING ')' + { + FILE *f = srcfile_relative_open($4.val, NULL); + struct data d = empty_data; + + d = data_copy_file(f, -1); + + $$ = data_merge($1, d); + fclose(f); + } + | propdata DT_LABEL + { + $$ = data_add_marker($1, LABEL, $2); + } + ; + +propdataprefix: + /* empty */ + { + $$ = empty_data; + } + | propdata ',' + { + $$ = $1; + } + | propdataprefix DT_LABEL + { + $$ = data_add_marker($1, LABEL, $2); + } + ; + +arrayprefix: + DT_BITS DT_LITERAL '<' + { + unsigned long long bits; + enum markertype type = TYPE_UINT32; + + bits = $2; + + switch (bits) { + case 8: type = TYPE_UINT8; break; + case 16: type = TYPE_UINT16; break; + case 32: type = TYPE_UINT32; break; + case 64: type = TYPE_UINT64; break; + default: + ERROR(&@2, "Array elements must be" + " 8, 16, 32 or 64-bits"); + bits = 32; + } + + $$.data = data_add_marker(empty_data, type, NULL); + $$.bits = bits; + } + | '<' + { + $$.data = data_add_marker(empty_data, TYPE_UINT32, NULL); + $$.bits = 32; + } + | arrayprefix integer_prim + { + if ($1.bits < 64) { + uint64_t mask = (1ULL << $1.bits) - 1; + /* + * Bits above mask must either be all zero + * (positive within range of mask) or all one + * (negative and sign-extended). The second + * condition is true if when we set all bits + * within the mask to one (i.e. | in the + * mask), all bits are one. + */ + if (($2 > mask) && (($2 | mask) != -1ULL)) + ERROR(&@2, "Value out of range for" + " %d-bit array element", $1.bits); + } + + $$.data = data_append_integer($1.data, $2, $1.bits); + } + | arrayprefix dt_ref + { + uint64_t val = ~0ULL >> (64 - $1.bits); + + if ($1.bits == 32) + $1.data = data_add_marker($1.data, + REF_PHANDLE, + $2); + else + ERROR(&@2, "References are only allowed in " + "arrays with 32-bit elements."); + + $$.data = data_append_integer($1.data, val, $1.bits); + } + | arrayprefix DT_LABEL + { + $$.data = data_add_marker($1.data, LABEL, $2); + } + ; + +integer_prim: + DT_LITERAL + | DT_CHAR_LITERAL + | '(' integer_expr ')' + { + $$ = $2; + } + ; + +integer_expr: + integer_trinary + ; + +integer_trinary: + integer_or + | integer_or '?' integer_expr ':' integer_trinary { $$ = $1 ? $3 : $5; } + ; + +integer_or: + integer_and + | integer_or DT_OR integer_and { $$ = $1 || $3; } + ; + +integer_and: + integer_bitor + | integer_and DT_AND integer_bitor { $$ = $1 && $3; } + ; + +integer_bitor: + integer_bitxor + | integer_bitor '|' integer_bitxor { $$ = $1 | $3; } + ; + +integer_bitxor: + integer_bitand + | integer_bitxor '^' integer_bitand { $$ = $1 ^ $3; } + ; + +integer_bitand: + integer_eq + | integer_bitand '&' integer_eq { $$ = $1 & $3; } + ; + +integer_eq: + integer_rela + | integer_eq DT_EQ integer_rela { $$ = $1 == $3; } + | integer_eq DT_NE integer_rela { $$ = $1 != $3; } + ; + +integer_rela: + integer_shift + | integer_rela '<' integer_shift { $$ = $1 < $3; } + | integer_rela '>' integer_shift { $$ = $1 > $3; } + | integer_rela DT_LE integer_shift { $$ = $1 <= $3; } + | integer_rela DT_GE integer_shift { $$ = $1 >= $3; } + ; + +integer_shift: + integer_shift DT_LSHIFT integer_add { $$ = ($3 < 64) ? ($1 << $3) : 0; } + | integer_shift DT_RSHIFT integer_add { $$ = ($3 < 64) ? ($1 >> $3) : 0; } + | integer_add + ; + +integer_add: + integer_add '+' integer_mul { $$ = $1 + $3; } + | integer_add '-' integer_mul { $$ = $1 - $3; } + | integer_mul + ; + +integer_mul: + integer_mul '*' integer_unary { $$ = $1 * $3; } + | integer_mul '/' integer_unary + { + if ($3 != 0) { + $$ = $1 / $3; + } else { + ERROR(&@$, "Division by zero"); + $$ = 0; + } + } + | integer_mul '%' integer_unary + { + if ($3 != 0) { + $$ = $1 % $3; + } else { + ERROR(&@$, "Division by zero"); + $$ = 0; + } + } + | integer_unary + ; + +integer_unary: + integer_prim + | '-' integer_unary { $$ = -$2; } + | '~' integer_unary { $$ = ~$2; } + | '!' integer_unary { $$ = !$2; } + ; + +bytestring: + /* empty */ + { + $$ = data_add_marker(empty_data, TYPE_UINT8, NULL); + } + | bytestring DT_BYTE + { + $$ = data_append_byte($1, $2); + } + | bytestring DT_LABEL + { + $$ = data_add_marker($1, LABEL, $2); + } + ; + +subnodes: + /* empty */ + { + $$ = NULL; + } + | subnode subnodes + { + $$ = chain_node($1, $2); + } + | subnode propdef + { + ERROR(&@2, "Properties must precede subnodes"); + YYERROR; + } + ; + +subnode: + DT_PROPNODENAME nodedef + { + $$ = name_node($2, $1); + } + | DT_DEL_NODE DT_PROPNODENAME ';' + { + $$ = name_node(build_node_delete(&@$), $2); + } + | DT_OMIT_NO_REF subnode + { + $$ = omit_node_if_unused($2); + } + | DT_LABEL subnode + { + add_label(&$2->labels, $1); + $$ = $2; + } + ; + +%% + +void yyerror(char const *s) +{ + ERROR(&yylloc, "%s", s); +} diff --git a/src/net/scripts/dtc/dtc.c b/src/net/scripts/dtc/dtc.c new file mode 100644 index 0000000..bdb3f59 --- /dev/null +++ b/src/net/scripts/dtc/dtc.c @@ -0,0 +1,369 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (C) Copyright David Gibson <dwg@au1.ibm.com>, IBM Corporation. 2005. + */ + +#include <sys/stat.h> + +#include "dtc.h" +#include "srcpos.h" + +/* + * Command line options + */ +int quiet; /* Level of quietness */ +int reservenum; /* Number of memory reservation slots */ +int minsize; /* Minimum blob size */ +int padsize; /* Additional padding to blob */ +int alignsize; /* Additional padding to blob accroding to the alignsize */ +int phandle_format = PHANDLE_EPAPR; /* Use linux,phandle or phandle properties */ +int generate_symbols; /* enable symbols & fixup support */ +int generate_fixups; /* suppress generation of fixups on symbol support */ +int auto_label_aliases; /* auto generate labels -> aliases */ +int annotate; /* Level of annotation: 1 for input source location + >1 for full input source location. */ + +static int is_power_of_2(int x) +{ + return (x > 0) && ((x & (x - 1)) == 0); +} + +static void fill_fullpaths(struct node *tree, const char *prefix) +{ + struct node *child; + const char *unit; + + tree->fullpath = join_path(prefix, tree->name); + + unit = strchr(tree->name, '@'); + if (unit) + tree->basenamelen = unit - tree->name; + else + tree->basenamelen = strlen(tree->name); + + for_each_child(tree, child) + fill_fullpaths(child, tree->fullpath); +} + +/* Usage related data. */ +static const char usage_synopsis[] = "dtc [options] <input file>"; +static const char usage_short_opts[] = "qI:O:o:V:d:R:S:p:a:fb:i:H:sW:E:@AThv"; +static struct option const usage_long_opts[] = { + {"quiet", no_argument, NULL, 'q'}, + {"in-format", a_argument, NULL, 'I'}, + {"out", a_argument, NULL, 'o'}, + {"out-format", a_argument, NULL, 'O'}, + {"out-version", a_argument, NULL, 'V'}, + {"out-dependency", a_argument, NULL, 'd'}, + {"reserve", a_argument, NULL, 'R'}, + {"space", a_argument, NULL, 'S'}, + {"pad", a_argument, NULL, 'p'}, + {"align", a_argument, NULL, 'a'}, + {"boot-cpu", a_argument, NULL, 'b'}, + {"force", no_argument, NULL, 'f'}, + {"include", a_argument, NULL, 'i'}, + {"sort", no_argument, NULL, 's'}, + {"phandle", a_argument, NULL, 'H'}, + {"warning", a_argument, NULL, 'W'}, + {"error", a_argument, NULL, 'E'}, + {"symbols", no_argument, NULL, '@'}, + {"auto-alias", no_argument, NULL, 'A'}, + {"annotate", no_argument, NULL, 'T'}, + {"help", no_argument, NULL, 'h'}, + {"version", no_argument, NULL, 'v'}, + {NULL, no_argument, NULL, 0x0}, +}; +static const char * const usage_opts_help[] = { + "\n\tQuiet: -q suppress warnings, -qq errors, -qqq all", + "\n\tInput formats are:\n" + "\t\tdts - device tree source text\n" + "\t\tdtb - device tree blob\n" + "\t\tfs - /proc/device-tree style directory", + "\n\tOutput file", + "\n\tOutput formats are:\n" + "\t\tdts - device tree source text\n" + "\t\tdtb - device tree blob\n" +#ifndef NO_YAML + "\t\tyaml - device tree encoded as YAML\n" +#endif + "\t\tasm - assembler source", + "\n\tBlob version to produce, defaults to "stringify(DEFAULT_FDT_VERSION)" (for dtb and asm output)", + "\n\tOutput dependency file", + "\n\tMake space for <number> reserve map entries (for dtb and asm output)", + "\n\tMake the blob at least <bytes> long (extra space)", + "\n\tAdd padding to the blob of <bytes> long (extra space)", + "\n\tMake the blob align to the <bytes> (extra space)", + "\n\tSet the physical boot cpu", + "\n\tTry to produce output even if the input tree has errors", + "\n\tAdd a path to search for include files", + "\n\tSort nodes and properties before outputting (useful for comparing trees)", + "\n\tValid phandle formats are:\n" + "\t\tlegacy - \"linux,phandle\" properties only\n" + "\t\tepapr - \"phandle\" properties only\n" + "\t\tboth - Both \"linux,phandle\" and \"phandle\" properties", + "\n\tEnable/disable warnings (prefix with \"no-\")", + "\n\tEnable/disable errors (prefix with \"no-\")", + "\n\tEnable generation of symbols", + "\n\tEnable auto-alias of labels", + "\n\tAnnotate output .dts with input source file and line (-T -T for more details)", + "\n\tPrint this help and exit", + "\n\tPrint version and exit", + NULL, +}; + +static const char *guess_type_by_name(const char *fname, const char *fallback) +{ + const char *s; + + s = strrchr(fname, '.'); + if (s == NULL) + return fallback; + if (!strcasecmp(s, ".dts")) + return "dts"; + if (!strcasecmp(s, ".yaml")) + return "yaml"; + if (!strcasecmp(s, ".dtb")) + return "dtb"; + return fallback; +} + +static const char *guess_input_format(const char *fname, const char *fallback) +{ + struct stat statbuf; + fdt32_t magic; + FILE *f; + + if (stat(fname, &statbuf) != 0) + return fallback; + + if (S_ISDIR(statbuf.st_mode)) + return "fs"; + + if (!S_ISREG(statbuf.st_mode)) + return fallback; + + f = fopen(fname, "r"); + if (f == NULL) + return fallback; + if (fread(&magic, 4, 1, f) != 1) { + fclose(f); + return fallback; + } + fclose(f); + + if (fdt32_to_cpu(magic) == FDT_MAGIC) + return "dtb"; + + return guess_type_by_name(fname, fallback); +} + +int main(int argc, char *argv[]) +{ + struct dt_info *dti; + const char *inform = NULL; + const char *outform = NULL; + const char *outname = "-"; + const char *depname = NULL; + bool force = false, sort = false; + const char *arg; + int opt; + FILE *outf = NULL; + int outversion = DEFAULT_FDT_VERSION; + long long cmdline_boot_cpuid = -1; + + quiet = 0; + reservenum = 0; + minsize = 0; + padsize = 0; + alignsize = 0; + + while ((opt = util_getopt_long()) != EOF) { + switch (opt) { + case 'I': + inform = optarg; + break; + case 'O': + outform = optarg; + break; + case 'o': + outname = optarg; + break; + case 'V': + outversion = strtol(optarg, NULL, 0); + break; + case 'd': + depname = optarg; + break; + case 'R': + reservenum = strtol(optarg, NULL, 0); + break; + case 'S': + minsize = strtol(optarg, NULL, 0); + break; + case 'p': + padsize = strtol(optarg, NULL, 0); + break; + case 'a': + alignsize = strtol(optarg, NULL, 0); + if (!is_power_of_2(alignsize)) + die("Invalid argument \"%d\" to -a option\n", + alignsize); + break; + case 'f': + force = true; + break; + case 'q': + quiet++; + break; + case 'b': + cmdline_boot_cpuid = strtoll(optarg, NULL, 0); + break; + case 'i': + srcfile_add_search_path(optarg); + break; + case 'v': + util_version(); + case 'H': + if (streq(optarg, "legacy")) + phandle_format = PHANDLE_LEGACY; + else if (streq(optarg, "epapr")) + phandle_format = PHANDLE_EPAPR; + else if (streq(optarg, "both")) + phandle_format = PHANDLE_BOTH; + else + die("Invalid argument \"%s\" to -H option\n", + optarg); + break; + + case 's': + sort = true; + break; + + case 'W': + parse_checks_option(true, false, optarg); + break; + + case 'E': + parse_checks_option(false, true, optarg); + break; + + case '@': + generate_symbols = 1; + break; + case 'A': + auto_label_aliases = 1; + break; + case 'T': + annotate++; + break; + + case 'h': + usage(NULL); + default: + usage("unknown option"); + } + } + + if (argc > (optind+1)) + usage("missing files"); + else if (argc < (optind+1)) + arg = "-"; + else + arg = argv[optind]; + + /* minsize and padsize are mutually exclusive */ + if (minsize && padsize) + die("Can't set both -p and -S\n"); + + if (depname) { + depfile = fopen(depname, "w"); + if (!depfile) + die("Couldn't open dependency file %s: %s\n", depname, + strerror(errno)); + fprintf(depfile, "%s:", outname); + } + + if (inform == NULL) + inform = guess_input_format(arg, "dts"); + if (outform == NULL) { + outform = guess_type_by_name(outname, NULL); + if (outform == NULL) { + if (streq(inform, "dts")) + outform = "dtb"; + else + outform = "dts"; + } + } + if (annotate && (!streq(inform, "dts") || !streq(outform, "dts"))) + die("--annotate requires -I dts -O dts\n"); + if (streq(inform, "dts")) + dti = dt_from_source(arg); + else if (streq(inform, "fs")) + dti = dt_from_fs(arg); + else if(streq(inform, "dtb")) + dti = dt_from_blob(arg); + else + die("Unknown input format \"%s\"\n", inform); + + dti->outname = outname; + + if (depfile) { + fputc('\n', depfile); + fclose(depfile); + } + + if (cmdline_boot_cpuid != -1) + dti->boot_cpuid_phys = cmdline_boot_cpuid; + + fill_fullpaths(dti->dt, ""); + + /* on a plugin, generate by default */ + if (dti->dtsflags & DTSF_PLUGIN) { + generate_fixups = 1; + } + + process_checks(force, dti); + + if (auto_label_aliases) + generate_label_tree(dti, "aliases", false); + + if (generate_symbols) + generate_label_tree(dti, "__symbols__", true); + + if (generate_fixups) { + generate_fixups_tree(dti, "__fixups__"); + generate_local_fixups_tree(dti, "__local_fixups__"); + } + + if (sort) + sort_tree(dti); + + if (streq(outname, "-")) { + outf = stdout; + } else { + outf = fopen(outname, "wb"); + if (! outf) + die("Couldn't open output file %s: %s\n", + outname, strerror(errno)); + } + + if (streq(outform, "dts")) { + dt_to_source(outf, dti); +#ifndef NO_YAML + } else if (streq(outform, "yaml")) { + if (!streq(inform, "dts")) + die("YAML output format requires dts input format\n"); + dt_to_yaml(outf, dti); +#endif + } else if (streq(outform, "dtb")) { + dt_to_blob(outf, dti, outversion); + } else if (streq(outform, "asm")) { + dt_to_asm(outf, dti, outversion); + } else if (streq(outform, "null")) { + /* do nothing */ + } else { + die("Unknown output format \"%s\"\n", outform); + } + + exit(0); +} diff --git a/src/net/scripts/dtc/dtc.h b/src/net/scripts/dtc/dtc.h new file mode 100644 index 0000000..a08f415 --- /dev/null +++ b/src/net/scripts/dtc/dtc.h @@ -0,0 +1,332 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef DTC_H +#define DTC_H + +/* + * (C) Copyright David Gibson <dwg@au1.ibm.com>, IBM Corporation. 2005. + */ + +#include <stdio.h> +#include <string.h> +#include <stdlib.h> +#include <stdint.h> +#include <stdbool.h> +#include <stdarg.h> +#include <assert.h> +#include <ctype.h> +#include <errno.h> +#include <unistd.h> +#include <inttypes.h> + +#include <libfdt_env.h> +#include <fdt.h> + +#include "util.h" + +#ifdef DEBUG +#define debug(...) printf(__VA_ARGS__) +#else +#define debug(...) +#endif + +#define DEFAULT_FDT_VERSION 17 + +/* + * Command line options + */ +extern int quiet; /* Level of quietness */ +extern int reservenum; /* Number of memory reservation slots */ +extern int minsize; /* Minimum blob size */ +extern int padsize; /* Additional padding to blob */ +extern int alignsize; /* Additional padding to blob accroding to the alignsize */ +extern int phandle_format; /* Use linux,phandle or phandle properties */ +extern int generate_symbols; /* generate symbols for nodes with labels */ +extern int generate_fixups; /* generate fixups */ +extern int auto_label_aliases; /* auto generate labels -> aliases */ +extern int annotate; /* annotate .dts with input source location */ + +#define PHANDLE_LEGACY 0x1 +#define PHANDLE_EPAPR 0x2 +#define PHANDLE_BOTH 0x3 + +typedef uint32_t cell_t; + +static inline uint16_t dtb_ld16(const void *p) +{ + const uint8_t *bp = (const uint8_t *)p; + + return ((uint16_t)bp[0] << 8) + | bp[1]; +} + +static inline uint32_t dtb_ld32(const void *p) +{ + const uint8_t *bp = (const uint8_t *)p; + + return ((uint32_t)bp[0] << 24) + | ((uint32_t)bp[1] << 16) + | ((uint32_t)bp[2] << 8) + | bp[3]; +} + +static inline uint64_t dtb_ld64(const void *p) +{ + const uint8_t *bp = (const uint8_t *)p; + + return ((uint64_t)bp[0] << 56) + | ((uint64_t)bp[1] << 48) + | ((uint64_t)bp[2] << 40) + | ((uint64_t)bp[3] << 32) + | ((uint64_t)bp[4] << 24) + | ((uint64_t)bp[5] << 16) + | ((uint64_t)bp[6] << 8) + | bp[7]; +} + +#define streq(a, b) (strcmp((a), (b)) == 0) +#define strstarts(s, prefix) (strncmp((s), (prefix), strlen(prefix)) == 0) +#define strprefixeq(a, n, b) (strlen(b) == (n) && (memcmp(a, b, n) == 0)) + +#define ALIGN(x, a) (((x) + (a) - 1) & ~((a) - 1)) + +/* Data blobs */ +enum markertype { + TYPE_NONE, + REF_PHANDLE, + REF_PATH, + LABEL, + TYPE_UINT8, + TYPE_UINT16, + TYPE_UINT32, + TYPE_UINT64, + TYPE_STRING, +}; +extern const char *markername(enum markertype markertype); + +struct marker { + enum markertype type; + int offset; + char *ref; + struct marker *next; +}; + +struct data { + int len; + char *val; + struct marker *markers; +}; + + +#define empty_data ((struct data){ 0 /* all .members = 0 or NULL */ }) + +#define for_each_marker(m) \ + for (; (m); (m) = (m)->next) +#define for_each_marker_of_type(m, t) \ + for_each_marker(m) \ + if ((m)->type == (t)) + +size_t type_marker_length(struct marker *m); + +void data_free(struct data d); + +struct data data_grow_for(struct data d, int xlen); + +struct data data_copy_mem(const char *mem, int len); +struct data data_copy_escape_string(const char *s, int len); +struct data data_copy_file(FILE *f, size_t len); + +struct data data_append_data(struct data d, const void *p, int len); +struct data data_insert_at_marker(struct data d, struct marker *m, + const void *p, int len); +struct data data_merge(struct data d1, struct data d2); +struct data data_append_cell(struct data d, cell_t word); +struct data data_append_integer(struct data d, uint64_t word, int bits); +struct data data_append_re(struct data d, uint64_t address, uint64_t size); +struct data data_append_addr(struct data d, uint64_t addr); +struct data data_append_byte(struct data d, uint8_t byte); +struct data data_append_zeroes(struct data d, int len); +struct data data_append_align(struct data d, int align); + +struct data data_add_marker(struct data d, enum markertype type, char *ref); + +bool data_is_one_string(struct data d); + +/* DT constraints */ + +#define MAX_PROPNAME_LEN 31 +#define MAX_NODENAME_LEN 31 + +/* Live trees */ +struct label { + bool deleted; + char *label; + struct label *next; +}; + +struct bus_type { + const char *name; +}; + +struct property { + bool deleted; + char *name; + struct data val; + + struct property *next; + + struct label *labels; + struct srcpos *srcpos; +}; + +struct node { + bool deleted; + char *name; + struct property *proplist; + struct node *children; + + struct node *parent; + struct node *next_sibling; + + char *fullpath; + int basenamelen; + + cell_t phandle; + int addr_cells, size_cells; + + struct label *labels; + const struct bus_type *bus; + struct srcpos *srcpos; + + bool omit_if_unused, is_referenced; +}; + +#define for_each_label_withdel(l0, l) \ + for ((l) = (l0); (l); (l) = (l)->next) + +#define for_each_label(l0, l) \ + for_each_label_withdel(l0, l) \ + if (!(l)->deleted) + +#define for_each_property_withdel(n, p) \ + for ((p) = (n)->proplist; (p); (p) = (p)->next) + +#define for_each_property(n, p) \ + for_each_property_withdel(n, p) \ + if (!(p)->deleted) + +#define for_each_child_withdel(n, c) \ + for ((c) = (n)->children; (c); (c) = (c)->next_sibling) + +#define for_each_child(n, c) \ + for_each_child_withdel(n, c) \ + if (!(c)->deleted) + +void add_label(struct label **labels, char *label); +void delete_labels(struct label **labels); + +struct property *build_property(char *name, struct data val, + struct srcpos *srcpos); +struct property *build_property_delete(char *name); +struct property *chain_property(struct property *first, struct property *list); +struct property *reverse_properties(struct property *first); + +struct node *build_node(struct property *proplist, struct node *children, + struct srcpos *srcpos); +struct node *build_node_delete(struct srcpos *srcpos); +struct node *name_node(struct node *node, char *name); +struct node *omit_node_if_unused(struct node *node); +struct node *reference_node(struct node *node); +struct node *chain_node(struct node *first, struct node *list); +struct node *merge_nodes(struct node *old_node, struct node *new_node); +struct node *add_orphan_node(struct node *old_node, struct node *new_node, char *ref); + +void add_property(struct node *node, struct property *prop); +void delete_property_by_name(struct node *node, char *name); +void delete_property(struct property *prop); +void add_child(struct node *parent, struct node *child); +void delete_node_by_name(struct node *parent, char *name); +void delete_node(struct node *node); +void append_to_property(struct node *node, + char *name, const void *data, int len, + enum markertype type); + +const char *get_unitname(struct node *node); +struct property *get_property(struct node *node, const char *propname); +cell_t propval_cell(struct property *prop); +cell_t propval_cell_n(struct property *prop, int n); +struct property *get_property_by_label(struct node *tree, const char *label, + struct node **node); +struct marker *get_marker_label(struct node *tree, const char *label, + struct node **node, struct property **prop); +struct node *get_subnode(struct node *node, const char *nodename); +struct node *get_node_by_path(struct node *tree, const char *path); +struct node *get_node_by_label(struct node *tree, const char *label); +struct node *get_node_by_phandle(struct node *tree, cell_t phandle); +struct node *get_node_by_ref(struct node *tree, const char *ref); +cell_t get_node_phandle(struct node *root, struct node *node); + +uint32_t guess_boot_cpuid(struct node *tree); + +/* Boot info (tree plus memreserve information */ + +struct reserve_info { + uint64_t address, size; + + struct reserve_info *next; + + struct label *labels; +}; + +struct reserve_info *build_reserve_entry(uint64_t start, uint64_t len); +struct reserve_info *chain_reserve_entry(struct reserve_info *first, + struct reserve_info *list); +struct reserve_info *add_reserve_entry(struct reserve_info *list, + struct reserve_info *new); + + +struct dt_info { + unsigned int dtsflags; + struct reserve_info *reservelist; + uint32_t boot_cpuid_phys; + struct node *dt; /* the device tree */ + const char *outname; /* filename being written to, "-" for stdout */ +}; + +/* DTS version flags definitions */ +#define DTSF_V1 0x0001 /* /dts-v1/ */ +#define DTSF_PLUGIN 0x0002 /* /plugin/ */ + +struct dt_info *build_dt_info(unsigned int dtsflags, + struct reserve_info *reservelist, + struct node *tree, uint32_t boot_cpuid_phys); +void sort_tree(struct dt_info *dti); +void generate_label_tree(struct dt_info *dti, char *name, bool allocph); +void generate_fixups_tree(struct dt_info *dti, char *name); +void generate_local_fixups_tree(struct dt_info *dti, char *name); + +/* Checks */ + +void parse_checks_option(bool warn, bool error, const char *arg); +void process_checks(bool force, struct dt_info *dti); + +/* Flattened trees */ + +void dt_to_blob(FILE *f, struct dt_info *dti, int version); +void dt_to_asm(FILE *f, struct dt_info *dti, int version); + +struct dt_info *dt_from_blob(const char *fname); + +/* Tree source */ + +void dt_to_source(FILE *f, struct dt_info *dti); +struct dt_info *dt_from_source(const char *f); + +/* YAML source */ + +void dt_to_yaml(FILE *f, struct dt_info *dti); + +/* FS trees */ + +struct dt_info *dt_from_fs(const char *dirname); + +#endif /* DTC_H */ diff --git a/src/net/scripts/dtc/dtx_diff b/src/net/scripts/dtc/dtx_diff new file mode 100755 index 0000000..f2bbde4 --- /dev/null +++ b/src/net/scripts/dtc/dtx_diff @@ -0,0 +1,361 @@ +#! /bin/bash +# SPDX-License-Identifier: GPL-2.0-only + +# Copyright (C) 2015 Frank Rowand +# + + +usage() { + + # use spaces instead of tabs in the usage message + cat >&2 <<eod + +Usage: + + `basename $0` DTx + decompile DTx + + `basename $0` DTx_1 DTx_2 + diff DTx_1 and DTx_2 + + + --annotate synonym for -T + --color synonym for -c (requires diff with --color support) + -c enable colored output + -f print full dts in diff (--unified=99999) + -h synonym for --help + -help synonym for --help + --help print this message and exit + -s SRCTREE linux kernel source tree is at path SRCTREE + (default is current directory) + -S linux kernel source tree is at root of current git repo + -T annotate output .dts with input source file and line + (-T -T for more details) + -u unsorted, do not sort DTx + + +Each DTx is processed by the dtc compiler to produce a sorted dts source +file. If DTx is a dts source file then it is pre-processed in the same +manner as done for the compile of the dts source file in the Linux kernel +build system ('#include' and '/include/' directives are processed). + +If two DTx are provided, the resulting dts source files are diffed. + +If DTx is a directory, it is treated as a DT subtree, such as + /proc/device-tree. + +If DTx contains the binary blob magic value in the first four bytes, + it is treated as a binary blob (aka .dtb or FDT). + +Otherwise DTx is treated as a dts source file (aka .dts). + + If this script is not run from the root of the linux source tree, + and DTx utilizes '#include' or '/include/' then the path of the + linux source tree can be provided by '-s SRCTREE' or '-S' so that + include paths will be set properly. + + The shell variable \${ARCH} must provide the architecture containing + the dts source file for include paths to be set properly for '#include' + or '/include/' to be processed. + + If DTx_1 and DTx_2 are in different architectures, then this script + may not work since \${ARCH} is part of the include path. The following + workaround can be used: + + `basename $0` ARCH=arch_of_dtx_1 DTx_1 >tmp_dtx_1.dts + `basename $0` ARCH=arch_of_dtx_2 DTx_2 >tmp_dtx_2.dts + `basename $0` tmp_dtx_1.dts tmp_dtx_2.dts + rm tmp_dtx_1.dts tmp_dtx_2.dts + + If DTx_1 and DTx_2 are in different directories, then this script will + add the path of DTx_1 and DTx_2 to the include paths. If DTx_2 includes + a local file that exists in both the path of DTx_1 and DTx_2 then the + file in the path of DTx_1 will incorrectly be included. Possible + workaround: + + `basename $0` DTx_1 >tmp_dtx_1.dts + `basename $0` DTx_2 >tmp_dtx_2.dts + `basename $0` tmp_dtx_1.dts tmp_dtx_2.dts + rm tmp_dtx_1.dts tmp_dtx_2.dts + +eod +} + + +compile_to_dts() { + + dtx="$1" + dtc_include="$2" + + if [ -d "${dtx}" ] ; then + + # ----- input is file tree + + if ( ! ${DTC} -I fs ${dtx} ) ; then + exit 3 + fi + + elif [ -f "${dtx}" ] && [ -r "${dtx}" ] ; then + + magic=`hexdump -n 4 -e '/1 "%02x"' ${dtx}` + if [ "${magic}" = "d00dfeed" ] ; then + + # ----- input is FDT (binary blob) + + if ( ! ${DTC} -I dtb ${dtx} ) ; then + exit 3 + fi + + return + + fi + + # ----- input is DTS (source) + + if ( cpp ${cpp_flags} -x assembler-with-cpp ${dtx} \ + | ${DTC} ${dtc_include} -I dts ) ; then + return + fi + + echo "" >&2 + echo "Possible hints to resolve the above error:" >&2 + echo " (hints might not fix the problem)" >&2 + + hint_given=0 + + if [ "${ARCH}" = "" ] ; then + hint_given=1 + echo "" >&2 + echo " shell variable \$ARCH not set" >&2 + fi + + dtx_arch=`echo "/${dtx}" | sed -e 's|.*/arch/||' -e 's|/.*||'` + + if [ "${dtx_arch}" != "" -a "${dtx_arch}" != "${ARCH}" ] ; then + hint_given=1 + echo "" >&2 + echo " architecture ${dtx_arch} is in file path," >&2 + echo " but does not match shell variable \$ARCH" >&2 + echo " >>\$ARCH<< is: >>${ARCH}<<" >&2 + fi + + if [ ! -d ${srctree}/arch/${ARCH} ] ; then + hint_given=1 + echo "" >&2 + echo " ${srctree}/arch/${ARCH}/ does not exist" >&2 + echo " Is \$ARCH='${ARCH}' correct?" >&2 + echo " Possible fix: use '-s' option" >&2 + + git_root=`git rev-parse --show-toplevel 2>/dev/null` + if [ -d ${git_root}/arch/ ] ; then + echo " Possible fix: use '-S' option" >&2 + fi + fi + + if [ $hint_given = 0 ] ; then + echo "" >&2 + echo " No hints available." >&2 + fi + + echo "" >&2 + + exit 3 + + else + echo "" >&2 + echo "ERROR: ${dtx} does not exist or is not readable" >&2 + echo "" >&2 + exit 2 + fi + +} + + +# ----- start of script + +annotate="" +cmd_diff=0 +diff_flags="-u" +diff_color="" +dtx_file_1="" +dtx_file_2="" +dtc_sort="-s" +help=0 +srctree="" + + +while [ $# -gt 0 ] ; do + + case $1 in + + -c | --color ) + if diff --color /dev/null /dev/null 2>/dev/null ; then + diff_color="--color=always" + fi + shift + ;; + + -f ) + diff_flags="--unified=999999" + shift + ;; + + -h | -help | --help ) + help=1 + shift + ;; + + -s ) + srctree="$2" + shift 2 + ;; + + -S ) + git_root=`git rev-parse --show-toplevel 2>/dev/null` + srctree="${git_root}" + shift + ;; + + -T | --annotate ) + if [ "${annotate}" = "" ] ; then + annotate="-T" + elif [ "${annotate}" = "-T" ] ; then + annotate="-T -T" + fi + shift + ;; + -u ) + dtc_sort="" + shift + ;; + + *) + if [ "${dtx_file_1}" = "" ] ; then + dtx_file_1="$1" + elif [ "${dtx_file_2}" = "" ] ; then + dtx_file_2="$1" + else + echo "" >&2 + echo "ERROR: Unexpected parameter: $1" >&2 + echo "" >&2 + exit 2 + fi + shift + ;; + + esac + +done + +if [ "${srctree}" = "" ] ; then + srctree="." +fi + +if [ "${dtx_file_2}" != "" ]; then + cmd_diff=1 +fi + +if (( ${help} )) ; then + usage + exit 1 +fi + +# this must follow check for ${help} +if [ "${dtx_file_1}" = "" ]; then + echo "" >&2 + echo "ERROR: parameter DTx required" >&2 + echo "" >&2 + exit 2 +fi + + +# ----- prefer dtc from linux kernel, allow fallback to dtc in $PATH + +if [ "${KBUILD_OUTPUT:0:2}" = ".." ] ; then + __KBUILD_OUTPUT="${srctree}/${KBUILD_OUTPUT}" +elif [ "${KBUILD_OUTPUT}" = "" ] ; then + __KBUILD_OUTPUT="." +else + __KBUILD_OUTPUT="${KBUILD_OUTPUT}" +fi + +DTC="${__KBUILD_OUTPUT}/scripts/dtc/dtc" + +if [ ! -x ${DTC} ] ; then + __DTC="dtc" + if grep -q "^CONFIG_DTC=y" ${__KBUILD_OUTPUT}/.config 2>/dev/null; then + make_command=' + make scripts' + else + make_command=' + Enable CONFIG_DTC in the kernel configuration + make scripts' + fi + if ( ! which ${__DTC} >/dev/null ) ; then + + # use spaces instead of tabs in the error message + cat >&2 <<eod + +ERROR: unable to find a 'dtc' program + + Preferred 'dtc' (built from Linux kernel source tree) was not found or + is not executable. + + 'dtc' is: ${DTC} + + If it does not exist, create it from the root of the Linux source tree: +${make_command} + + If not at the root of the Linux kernel source tree -s SRCTREE or -S + may need to be specified to find 'dtc'. + + If 'O=\${dir}' is specified in your Linux builds, this script requires + 'export KBUILD_OUTPUT=\${dir}' or add \${dir}/scripts/dtc to \$PATH + before running. + + If \${KBUILD_OUTPUT} is a relative path, then '-s SRCDIR', -S, or run + this script from the root of the Linux kernel source tree is required. + + Fallback '${__DTC}' was also not in \${PATH} or is not executable. + +eod + exit 2 + fi + DTC=${__DTC} +fi + + +# ----- cpp and dtc flags same as for linux source tree build of .dtb files, +# plus directories of the dtx file(s) + +dtx_path_1_dtc_include="-i `dirname ${dtx_file_1}`" + +dtx_path_2_dtc_include="" +if (( ${cmd_diff} )) ; then + dtx_path_2_dtc_include="-i `dirname ${dtx_file_2}`" +fi + +cpp_flags="\ + -nostdinc \ + -I${srctree}/scripts/dtc/include-prefixes \ + -undef -D__DTS__" + +DTC="\ + ${DTC} \ + -i ${srctree}/scripts/dtc/include-prefixes \ + -O dts -qq -f ${dtc_sort} ${annotate} -o -" + + +# ----- do the diff or decompile + +if (( ${cmd_diff} )) ; then + + diff ${diff_flags} ${diff_color} --label "${dtx_file_1}" --label "${dtx_file_2}" \ + <(compile_to_dts "${dtx_file_1}" "${dtx_path_1_dtc_include}") \ + <(compile_to_dts "${dtx_file_2}" "${dtx_path_2_dtc_include}") + +else + + compile_to_dts "${dtx_file_1}" "${dtx_path_1_dtc_include}" + +fi diff --git a/src/net/scripts/dtc/fdtdump.c b/src/net/scripts/dtc/fdtdump.c new file mode 100644 index 0000000..7d460a5 --- /dev/null +++ b/src/net/scripts/dtc/fdtdump.c @@ -0,0 +1,163 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * fdtdump.c - Contributed by Pantelis Antoniou <pantelis.antoniou AT gmail.com> + */ + +#include <stdint.h> +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <ctype.h> + +#include <fdt.h> +#include <libfdt_env.h> + +#include "util.h" + +#define ALIGN(x, a) (((x) + ((a) - 1)) & ~((a) - 1)) +#define PALIGN(p, a) ((void *)(ALIGN((unsigned long)(p), (a)))) +#define GET_CELL(p) (p += 4, *((const uint32_t *)(p-4))) + +static void print_data(const char *data, int len) +{ + int i; + const char *p = data; + + /* no data, don't print */ + if (len == 0) + return; + + if (util_is_printable_string(data, len)) { + printf(" = \"%s\"", (const char *)data); + } else if ((len % 4) == 0) { + printf(" = <"); + for (i = 0; i < len; i += 4) + printf("0x%08x%s", fdt32_to_cpu(GET_CELL(p)), + i < (len - 4) ? " " : ""); + printf(">"); + } else { + printf(" = ["); + for (i = 0; i < len; i++) + printf("%02x%s", *p++, i < len - 1 ? " " : ""); + printf("]"); + } +} + +static void dump_blob(void *blob) +{ + struct fdt_header *bph = blob; + uint32_t off_mem_rsvmap = fdt32_to_cpu(bph->off_mem_rsvmap); + uint32_t off_dt = fdt32_to_cpu(bph->off_dt_struct); + uint32_t off_str = fdt32_to_cpu(bph->off_dt_strings); + struct fdt_reserve_entry *p_rsvmap = + (struct fdt_reserve_entry *)((char *)blob + off_mem_rsvmap); + const char *p_struct = (const char *)blob + off_dt; + const char *p_strings = (const char *)blob + off_str; + uint32_t version = fdt32_to_cpu(bph->version); + uint32_t totalsize = fdt32_to_cpu(bph->totalsize); + uint32_t tag; + const char *p, *s, *t; + int depth, sz, shift; + int i; + uint64_t addr, size; + + depth = 0; + shift = 4; + + printf("/dts-v1/;\n"); + printf("// magic:\t\t0x%x\n", fdt32_to_cpu(bph->magic)); + printf("// totalsize:\t\t0x%x (%d)\n", totalsize, totalsize); + printf("// off_dt_struct:\t0x%x\n", off_dt); + printf("// off_dt_strings:\t0x%x\n", off_str); + printf("// off_mem_rsvmap:\t0x%x\n", off_mem_rsvmap); + printf("// version:\t\t%d\n", version); + printf("// last_comp_version:\t%d\n", + fdt32_to_cpu(bph->last_comp_version)); + if (version >= 2) + printf("// boot_cpuid_phys:\t0x%x\n", + fdt32_to_cpu(bph->boot_cpuid_phys)); + + if (version >= 3) + printf("// size_dt_strings:\t0x%x\n", + fdt32_to_cpu(bph->size_dt_strings)); + if (version >= 17) + printf("// size_dt_struct:\t0x%x\n", + fdt32_to_cpu(bph->size_dt_struct)); + printf("\n"); + + for (i = 0; ; i++) { + addr = fdt64_to_cpu(p_rsvmap[i].address); + size = fdt64_to_cpu(p_rsvmap[i].size); + if (addr == 0 && size == 0) + break; + + printf("/memreserve/ %llx %llx;\n", + (unsigned long long)addr, (unsigned long long)size); + } + + p = p_struct; + while ((tag = fdt32_to_cpu(GET_CELL(p))) != FDT_END) { + + /* printf("tag: 0x%08x (%d)\n", tag, p - p_struct); */ + + if (tag == FDT_BEGIN_NODE) { + s = p; + p = PALIGN(p + strlen(s) + 1, 4); + + if (*s == '\0') + s = "/"; + + printf("%*s%s {\n", depth * shift, "", s); + + depth++; + continue; + } + + if (tag == FDT_END_NODE) { + depth--; + + printf("%*s};\n", depth * shift, ""); + continue; + } + + if (tag == FDT_NOP) { + printf("%*s// [NOP]\n", depth * shift, ""); + continue; + } + + if (tag != FDT_PROP) { + fprintf(stderr, "%*s ** Unknown tag 0x%08x\n", depth * shift, "", tag); + break; + } + sz = fdt32_to_cpu(GET_CELL(p)); + s = p_strings + fdt32_to_cpu(GET_CELL(p)); + if (version < 16 && sz >= 8) + p = PALIGN(p, 8); + t = p; + + p = PALIGN(p + sz, 4); + + printf("%*s%s", depth * shift, "", s); + print_data(t, sz); + printf(";\n"); + } +} + + +int main(int argc, char *argv[]) +{ + char *buf; + + if (argc < 2) { + fprintf(stderr, "supply input filename\n"); + return 5; + } + + buf = utilfdt_read(argv[1]); + if (buf) + dump_blob(buf); + else + return 10; + + return 0; +} diff --git a/src/net/scripts/dtc/fdtget.c b/src/net/scripts/dtc/fdtget.c new file mode 100644 index 0000000..c922f82 --- /dev/null +++ b/src/net/scripts/dtc/fdtget.c @@ -0,0 +1,352 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2011 The Chromium OS Authors. All rights reserved. + * + * Portions from U-Boot cmd_fdt.c (C) Copyright 2007 + * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com + * Based on code written by: + * Pantelis Antoniou <pantelis.antoniou@gmail.com> and + * Matthew McClintock <msm@freescale.com> + */ + +#include <assert.h> +#include <ctype.h> +#include <getopt.h> +#include <stdio.h> +#include <stdlib.h> +#include <string.h> + +#include <libfdt.h> + +#include "util.h" + +enum display_mode { + MODE_SHOW_VALUE, /* show values for node properties */ + MODE_LIST_PROPS, /* list the properties for a node */ + MODE_LIST_SUBNODES, /* list the subnodes of a node */ +}; + +/* Holds information which controls our output and options */ +struct display_info { + int type; /* data type (s/i/u/x or 0 for default) */ + int size; /* data size (1/2/4) */ + enum display_mode mode; /* display mode that we are using */ + const char *default_val; /* default value if node/property not found */ +}; + +static void report_error(const char *where, int err) +{ + fprintf(stderr, "Error at '%s': %s\n", where, fdt_strerror(err)); +} + +/** + * Displays data of a given length according to selected options + * + * If a specific data type is provided in disp, then this is used. Otherwise + * we try to guess the data type / size from the contents. + * + * @param disp Display information / options + * @param data Data to display + * @param len Maximum length of buffer + * @return 0 if ok, -1 if data does not match format + */ +static int show_data(struct display_info *disp, const char *data, int len) +{ + int i, size; + const uint8_t *p = (const uint8_t *)data; + const char *s; + int value; + int is_string; + char fmt[3]; + + /* no data, don't print */ + if (len == 0) + return 0; + + is_string = (disp->type) == 's' || + (!disp->type && util_is_printable_string(data, len)); + if (is_string) { + if (data[len - 1] != '\0') { + fprintf(stderr, "Unterminated string\n"); + return -1; + } + for (s = data; s - data < len; s += strlen(s) + 1) { + if (s != data) + printf(" "); + printf("%s", (const char *)s); + } + return 0; + } + size = disp->size; + if (size == -1) { + size = (len % 4) == 0 ? 4 : 1; + } else if (len % size) { + fprintf(stderr, "Property length must be a multiple of " + "selected data size\n"); + return -1; + } + fmt[0] = '%'; + fmt[1] = disp->type ? disp->type : 'd'; + fmt[2] = '\0'; + for (i = 0; i < len; i += size, p += size) { + if (i) + printf(" "); + value = size == 4 ? fdt32_to_cpu(*(const uint32_t *)p) : + size == 2 ? (*p << 8) | p[1] : *p; + printf(fmt, value); + } + return 0; +} + +/** + * List all properties in a node, one per line. + * + * @param blob FDT blob + * @param node Node to display + * @return 0 if ok, or FDT_ERR... if not. + */ +static int list_properties(const void *blob, int node) +{ + const struct fdt_property *data; + const char *name; + int prop; + + prop = fdt_first_property_offset(blob, node); + do { + /* Stop silently when there are no more properties */ + if (prop < 0) + return prop == -FDT_ERR_NOTFOUND ? 0 : prop; + data = fdt_get_property_by_offset(blob, prop, NULL); + name = fdt_string(blob, fdt32_to_cpu(data->nameoff)); + if (name) + puts(name); + prop = fdt_next_property_offset(blob, prop); + } while (1); +} + +#define MAX_LEVEL 32 /* how deeply nested we will go */ + +/** + * List all subnodes in a node, one per line + * + * @param blob FDT blob + * @param node Node to display + * @return 0 if ok, or FDT_ERR... if not. + */ +static int list_subnodes(const void *blob, int node) +{ + int nextoffset; /* next node offset from libfdt */ + uint32_t tag; /* current tag */ + int level = 0; /* keep track of nesting level */ + const char *pathp; + int depth = 1; /* the assumed depth of this node */ + + while (level >= 0) { + tag = fdt_next_tag(blob, node, &nextoffset); + switch (tag) { + case FDT_BEGIN_NODE: + pathp = fdt_get_name(blob, node, NULL); + if (level <= depth) { + if (pathp == NULL) + pathp = "/* NULL pointer error */"; + if (*pathp == '\0') + pathp = "/"; /* root is nameless */ + if (level == 1) + puts(pathp); + } + level++; + if (level >= MAX_LEVEL) { + printf("Nested too deep, aborting.\n"); + return 1; + } + break; + case FDT_END_NODE: + level--; + if (level == 0) + level = -1; /* exit the loop */ + break; + case FDT_END: + return 1; + case FDT_PROP: + break; + default: + if (level <= depth) + printf("Unknown tag 0x%08X\n", tag); + return 1; + } + node = nextoffset; + } + return 0; +} + +/** + * Show the data for a given node (and perhaps property) according to the + * display option provided. + * + * @param blob FDT blob + * @param disp Display information / options + * @param node Node to display + * @param property Name of property to display, or NULL if none + * @return 0 if ok, -ve on error + */ +static int show_data_for_item(const void *blob, struct display_info *disp, + int node, const char *property) +{ + const void *value = NULL; + int len, err = 0; + + switch (disp->mode) { + case MODE_LIST_PROPS: + err = list_properties(blob, node); + break; + + case MODE_LIST_SUBNODES: + err = list_subnodes(blob, node); + break; + + default: + assert(property); + value = fdt_getprop(blob, node, property, &len); + if (value) { + if (show_data(disp, value, len)) + err = -1; + else + printf("\n"); + } else if (disp->default_val) { + puts(disp->default_val); + } else { + report_error(property, len); + err = -1; + } + break; + } + + return err; +} + +/** + * Run the main fdtget operation, given a filename and valid arguments + * + * @param disp Display information / options + * @param filename Filename of blob file + * @param arg List of arguments to process + * @param arg_count Number of arguments + * @param return 0 if ok, -ve on error + */ +static int do_fdtget(struct display_info *disp, const char *filename, + char **arg, int arg_count, int args_per_step) +{ + char *blob; + const char *prop; + int i, node; + + blob = utilfdt_read(filename); + if (!blob) + return -1; + + for (i = 0; i + args_per_step <= arg_count; i += args_per_step) { + node = fdt_path_offset(blob, arg[i]); + if (node < 0) { + if (disp->default_val) { + puts(disp->default_val); + continue; + } else { + report_error(arg[i], node); + return -1; + } + } + prop = args_per_step == 1 ? NULL : arg[i + 1]; + + if (show_data_for_item(blob, disp, node, prop)) + return -1; + } + return 0; +} + +static const char *usage_msg = + "fdtget - read values from device tree\n" + "\n" + "Each value is printed on a new line.\n\n" + "Usage:\n" + " fdtget <options> <dt file> [<node> <property>]...\n" + " fdtget -p <options> <dt file> [<node> ]...\n" + "Options:\n" + "\t-t <type>\tType of data\n" + "\t-p\t\tList properties for each node\n" + "\t-l\t\tList subnodes for each node\n" + "\t-d\t\tDefault value to display when the property is " + "missing\n" + "\t-h\t\tPrint this help\n\n" + USAGE_TYPE_MSG; + +static void usage(const char *msg) +{ + if (msg) + fprintf(stderr, "Error: %s\n\n", msg); + + fprintf(stderr, "%s", usage_msg); + exit(2); +} + +int main(int argc, char *argv[]) +{ + char *filename = NULL; + struct display_info disp; + int args_per_step = 2; + + /* set defaults */ + memset(&disp, '\0', sizeof(disp)); + disp.size = -1; + disp.mode = MODE_SHOW_VALUE; + for (;;) { + int c = getopt(argc, argv, "d:hlpt:"); + if (c == -1) + break; + + switch (c) { + case 'h': + case '?': + usage(NULL); + + case 't': + if (utilfdt_decode_type(optarg, &disp.type, + &disp.size)) + usage("Invalid type string"); + break; + + case 'p': + disp.mode = MODE_LIST_PROPS; + args_per_step = 1; + break; + + case 'l': + disp.mode = MODE_LIST_SUBNODES; + args_per_step = 1; + break; + + case 'd': + disp.default_val = optarg; + break; + } + } + + if (optind < argc) + filename = argv[optind++]; + if (!filename) + usage("Missing filename"); + + argv += optind; + argc -= optind; + + /* Allow no arguments, and silently succeed */ + if (!argc) + return 0; + + /* Check for node, property arguments */ + if (args_per_step == 2 && (argc % 2)) + usage("Must have an even number of arguments"); + + if (do_fdtget(&disp, filename, argv, argc, args_per_step)) + return 1; + return 0; +} diff --git a/src/net/scripts/dtc/fdtput.c b/src/net/scripts/dtc/fdtput.c new file mode 100644 index 0000000..a363c3c --- /dev/null +++ b/src/net/scripts/dtc/fdtput.c @@ -0,0 +1,348 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2011 The Chromium OS Authors. All rights reserved. + */ + +#include <assert.h> +#include <ctype.h> +#include <getopt.h> +#include <stdio.h> +#include <stdlib.h> +#include <string.h> + +#include <libfdt.h> + +#include "util.h" + +/* These are the operations we support */ +enum oper_type { + OPER_WRITE_PROP, /* Write a property in a node */ + OPER_CREATE_NODE, /* Create a new node */ +}; + +struct display_info { + enum oper_type oper; /* operation to perform */ + int type; /* data type (s/i/u/x or 0 for default) */ + int size; /* data size (1/2/4) */ + int verbose; /* verbose output */ + int auto_path; /* automatically create all path components */ +}; + + +/** + * Report an error with a particular node. + * + * @param name Node name to report error on + * @param namelen Length of node name, or -1 to use entire string + * @param err Error number to report (-FDT_ERR_...) + */ +static void report_error(const char *name, int namelen, int err) +{ + if (namelen == -1) + namelen = strlen(name); + fprintf(stderr, "Error at '%1.*s': %s\n", namelen, name, + fdt_strerror(err)); +} + +/** + * Encode a series of arguments in a property value. + * + * @param disp Display information / options + * @param arg List of arguments from command line + * @param arg_count Number of arguments (may be 0) + * @param valuep Returns buffer containing value + * @param *value_len Returns length of value encoded + */ +static int encode_value(struct display_info *disp, char **arg, int arg_count, + char **valuep, int *value_len) +{ + char *value = NULL; /* holding area for value */ + int value_size = 0; /* size of holding area */ + char *ptr; /* pointer to current value position */ + int len; /* length of this cell/string/byte */ + int ival; + int upto; /* the number of bytes we have written to buf */ + char fmt[3]; + + upto = 0; + + if (disp->verbose) + fprintf(stderr, "Decoding value:\n"); + + fmt[0] = '%'; + fmt[1] = disp->type ? disp->type : 'd'; + fmt[2] = '\0'; + for (; arg_count > 0; arg++, arg_count--, upto += len) { + /* assume integer unless told otherwise */ + if (disp->type == 's') + len = strlen(*arg) + 1; + else + len = disp->size == -1 ? 4 : disp->size; + + /* enlarge our value buffer by a suitable margin if needed */ + if (upto + len > value_size) { + value_size = (upto + len) + 500; + value = realloc(value, value_size); + if (!value) { + fprintf(stderr, "Out of mmory: cannot alloc " + "%d bytes\n", value_size); + return -1; + } + } + + ptr = value + upto; + if (disp->type == 's') { + memcpy(ptr, *arg, len); + if (disp->verbose) + fprintf(stderr, "\tstring: '%s'\n", ptr); + } else { + int *iptr = (int *)ptr; + sscanf(*arg, fmt, &ival); + if (len == 4) + *iptr = cpu_to_fdt32(ival); + else + *ptr = (uint8_t)ival; + if (disp->verbose) { + fprintf(stderr, "\t%s: %d\n", + disp->size == 1 ? "byte" : + disp->size == 2 ? "short" : "int", + ival); + } + } + } + *value_len = upto; + *valuep = value; + if (disp->verbose) + fprintf(stderr, "Value size %d\n", upto); + return 0; +} + +static int store_key_value(void *blob, const char *node_name, + const char *property, const char *buf, int len) +{ + int node; + int err; + + node = fdt_path_offset(blob, node_name); + if (node < 0) { + report_error(node_name, -1, node); + return -1; + } + + err = fdt_setprop(blob, node, property, buf, len); + if (err) { + report_error(property, -1, err); + return -1; + } + return 0; +} + +/** + * Create paths as needed for all components of a path + * + * Any components of the path that do not exist are created. Errors are + * reported. + * + * @param blob FDT blob to write into + * @param in_path Path to process + * @return 0 if ok, -1 on error + */ +static int create_paths(void *blob, const char *in_path) +{ + const char *path = in_path; + const char *sep; + int node, offset = 0; + + /* skip leading '/' */ + while (*path == '/') + path++; + + for (sep = path; *sep; path = sep + 1, offset = node) { + /* equivalent to strchrnul(), but it requires _GNU_SOURCE */ + sep = strchr(path, '/'); + if (!sep) + sep = path + strlen(path); + + node = fdt_subnode_offset_namelen(blob, offset, path, + sep - path); + if (node == -FDT_ERR_NOTFOUND) { + node = fdt_add_subnode_namelen(blob, offset, path, + sep - path); + } + if (node < 0) { + report_error(path, sep - path, node); + return -1; + } + } + + return 0; +} + +/** + * Create a new node in the fdt. + * + * This will overwrite the node_name string. Any error is reported. + * + * TODO: Perhaps create fdt_path_offset_namelen() so we don't need to do this. + * + * @param blob FDT blob to write into + * @param node_name Name of node to create + * @return new node offset if found, or -1 on failure + */ +static int create_node(void *blob, const char *node_name) +{ + int node = 0; + char *p; + + p = strrchr(node_name, '/'); + if (!p) { + report_error(node_name, -1, -FDT_ERR_BADPATH); + return -1; + } + *p = '\0'; + + if (p > node_name) { + node = fdt_path_offset(blob, node_name); + if (node < 0) { + report_error(node_name, -1, node); + return -1; + } + } + + node = fdt_add_subnode(blob, node, p + 1); + if (node < 0) { + report_error(p + 1, -1, node); + return -1; + } + + return 0; +} + +static int do_fdtput(struct display_info *disp, const char *filename, + char **arg, int arg_count) +{ + char *value; + char *blob; + int len, ret = 0; + + blob = utilfdt_read(filename); + if (!blob) + return -1; + + switch (disp->oper) { + case OPER_WRITE_PROP: + /* + * Convert the arguments into a single binary value, then + * store them into the property. + */ + assert(arg_count >= 2); + if (disp->auto_path && create_paths(blob, *arg)) + return -1; + if (encode_value(disp, arg + 2, arg_count - 2, &value, &len) || + store_key_value(blob, *arg, arg[1], value, len)) + ret = -1; + break; + case OPER_CREATE_NODE: + for (; ret >= 0 && arg_count--; arg++) { + if (disp->auto_path) + ret = create_paths(blob, *arg); + else + ret = create_node(blob, *arg); + } + break; + } + if (ret >= 0) + ret = utilfdt_write(filename, blob); + + free(blob); + return ret; +} + +static const char *usage_msg = + "fdtput - write a property value to a device tree\n" + "\n" + "The command line arguments are joined together into a single value.\n" + "\n" + "Usage:\n" + " fdtput <options> <dt file> <node> <property> [<value>...]\n" + " fdtput -c <options> <dt file> [<node>...]\n" + "Options:\n" + "\t-c\t\tCreate nodes if they don't already exist\n" + "\t-p\t\tAutomatically create nodes as needed for the node path\n" + "\t-t <type>\tType of data\n" + "\t-v\t\tVerbose: display each value decoded from command line\n" + "\t-h\t\tPrint this help\n\n" + USAGE_TYPE_MSG; + +static void usage(const char *msg) +{ + if (msg) + fprintf(stderr, "Error: %s\n\n", msg); + + fprintf(stderr, "%s", usage_msg); + exit(2); +} + +int main(int argc, char *argv[]) +{ + struct display_info disp; + char *filename = NULL; + + memset(&disp, '\0', sizeof(disp)); + disp.size = -1; + disp.oper = OPER_WRITE_PROP; + for (;;) { + int c = getopt(argc, argv, "chpt:v"); + if (c == -1) + break; + + /* + * TODO: add options to: + * - delete property + * - delete node (optionally recursively) + * - rename node + * - pack fdt before writing + * - set amount of free space when writing + * - expand fdt if value doesn't fit + */ + switch (c) { + case 'c': + disp.oper = OPER_CREATE_NODE; + break; + case 'h': + case '?': + usage(NULL); + case 'p': + disp.auto_path = 1; + break; + case 't': + if (utilfdt_decode_type(optarg, &disp.type, + &disp.size)) + usage("Invalid type string"); + break; + + case 'v': + disp.verbose = 1; + break; + } + } + + if (optind < argc) + filename = argv[optind++]; + if (!filename) + usage("Missing filename"); + + argv += optind; + argc -= optind; + + if (disp.oper == OPER_WRITE_PROP) { + if (argc < 1) + usage("Missing node"); + if (argc < 2) + usage("Missing property"); + } + + if (do_fdtput(&disp, filename, argv, argc)) + return 1; + return 0; +} diff --git a/src/net/scripts/dtc/flattree.c b/src/net/scripts/dtc/flattree.c new file mode 100644 index 0000000..07f10d2 --- /dev/null +++ b/src/net/scripts/dtc/flattree.c @@ -0,0 +1,925 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (C) Copyright David Gibson <dwg@au1.ibm.com>, IBM Corporation. 2005. + */ + +#include "dtc.h" +#include "srcpos.h" + +#define FTF_FULLPATH 0x1 +#define FTF_VARALIGN 0x2 +#define FTF_NAMEPROPS 0x4 +#define FTF_BOOTCPUID 0x8 +#define FTF_STRTABSIZE 0x10 +#define FTF_STRUCTSIZE 0x20 +#define FTF_NOPS 0x40 + +static struct version_info { + int version; + int last_comp_version; + int hdr_size; + int flags; +} version_table[] = { + {1, 1, FDT_V1_SIZE, + FTF_FULLPATH|FTF_VARALIGN|FTF_NAMEPROPS}, + {2, 1, FDT_V2_SIZE, + FTF_FULLPATH|FTF_VARALIGN|FTF_NAMEPROPS|FTF_BOOTCPUID}, + {3, 1, FDT_V3_SIZE, + FTF_FULLPATH|FTF_VARALIGN|FTF_NAMEPROPS|FTF_BOOTCPUID|FTF_STRTABSIZE}, + {16, 16, FDT_V3_SIZE, + FTF_BOOTCPUID|FTF_STRTABSIZE|FTF_NOPS}, + {17, 16, FDT_V17_SIZE, + FTF_BOOTCPUID|FTF_STRTABSIZE|FTF_STRUCTSIZE|FTF_NOPS}, +}; + +struct emitter { + void (*cell)(void *, cell_t); + void (*string)(void *, const char *, int); + void (*align)(void *, int); + void (*data)(void *, struct data); + void (*beginnode)(void *, struct label *labels); + void (*endnode)(void *, struct label *labels); + void (*property)(void *, struct label *labels); +}; + +static void bin_emit_cell(void *e, cell_t val) +{ + struct data *dtbuf = e; + + *dtbuf = data_append_cell(*dtbuf, val); +} + +static void bin_emit_string(void *e, const char *str, int len) +{ + struct data *dtbuf = e; + + if (len == 0) + len = strlen(str); + + *dtbuf = data_append_data(*dtbuf, str, len); + *dtbuf = data_append_byte(*dtbuf, '\0'); +} + +static void bin_emit_align(void *e, int a) +{ + struct data *dtbuf = e; + + *dtbuf = data_append_align(*dtbuf, a); +} + +static void bin_emit_data(void *e, struct data d) +{ + struct data *dtbuf = e; + + *dtbuf = data_append_data(*dtbuf, d.val, d.len); +} + +static void bin_emit_beginnode(void *e, struct label *labels) +{ + bin_emit_cell(e, FDT_BEGIN_NODE); +} + +static void bin_emit_endnode(void *e, struct label *labels) +{ + bin_emit_cell(e, FDT_END_NODE); +} + +static void bin_emit_property(void *e, struct label *labels) +{ + bin_emit_cell(e, FDT_PROP); +} + +static struct emitter bin_emitter = { + .cell = bin_emit_cell, + .string = bin_emit_string, + .align = bin_emit_align, + .data = bin_emit_data, + .beginnode = bin_emit_beginnode, + .endnode = bin_emit_endnode, + .property = bin_emit_property, +}; + +static void emit_label(FILE *f, const char *prefix, const char *label) +{ + fprintf(f, "\t.globl\t%s_%s\n", prefix, label); + fprintf(f, "%s_%s:\n", prefix, label); + fprintf(f, "_%s_%s:\n", prefix, label); +} + +static void emit_offset_label(FILE *f, const char *label, int offset) +{ + fprintf(f, "\t.globl\t%s\n", label); + fprintf(f, "%s\t= . + %d\n", label, offset); +} + +#define ASM_EMIT_BELONG(f, fmt, ...) \ + { \ + fprintf((f), "\t.byte\t((" fmt ") >> 24) & 0xff\n", __VA_ARGS__); \ + fprintf((f), "\t.byte\t((" fmt ") >> 16) & 0xff\n", __VA_ARGS__); \ + fprintf((f), "\t.byte\t((" fmt ") >> 8) & 0xff\n", __VA_ARGS__); \ + fprintf((f), "\t.byte\t(" fmt ") & 0xff\n", __VA_ARGS__); \ + } + +static void asm_emit_cell(void *e, cell_t val) +{ + FILE *f = e; + + fprintf(f, "\t.byte 0x%02x; .byte 0x%02x; .byte 0x%02x; .byte 0x%02x\n", + (val >> 24) & 0xff, (val >> 16) & 0xff, + (val >> 8) & 0xff, val & 0xff); +} + +static void asm_emit_string(void *e, const char *str, int len) +{ + FILE *f = e; + + if (len != 0) + fprintf(f, "\t.string\t\"%.*s\"\n", len, str); + else + fprintf(f, "\t.string\t\"%s\"\n", str); +} + +static void asm_emit_align(void *e, int a) +{ + FILE *f = e; + + fprintf(f, "\t.balign\t%d, 0\n", a); +} + +static void asm_emit_data(void *e, struct data d) +{ + FILE *f = e; + int off = 0; + struct marker *m = d.markers; + + for_each_marker_of_type(m, LABEL) + emit_offset_label(f, m->ref, m->offset); + + while ((d.len - off) >= sizeof(uint32_t)) { + asm_emit_cell(e, dtb_ld32(d.val + off)); + off += sizeof(uint32_t); + } + + while ((d.len - off) >= 1) { + fprintf(f, "\t.byte\t0x%hhx\n", d.val[off]); + off += 1; + } + + assert(off == d.len); +} + +static void asm_emit_beginnode(void *e, struct label *labels) +{ + FILE *f = e; + struct label *l; + + for_each_label(labels, l) { + fprintf(f, "\t.globl\t%s\n", l->label); + fprintf(f, "%s:\n", l->label); + } + fprintf(f, "\t/* FDT_BEGIN_NODE */\n"); + asm_emit_cell(e, FDT_BEGIN_NODE); +} + +static void asm_emit_endnode(void *e, struct label *labels) +{ + FILE *f = e; + struct label *l; + + fprintf(f, "\t/* FDT_END_NODE */\n"); + asm_emit_cell(e, FDT_END_NODE); + for_each_label(labels, l) { + fprintf(f, "\t.globl\t%s_end\n", l->label); + fprintf(f, "%s_end:\n", l->label); + } +} + +static void asm_emit_property(void *e, struct label *labels) +{ + FILE *f = e; + struct label *l; + + for_each_label(labels, l) { + fprintf(f, "\t.globl\t%s\n", l->label); + fprintf(f, "%s:\n", l->label); + } + fprintf(f, "\t/* FDT_PROP */\n"); + asm_emit_cell(e, FDT_PROP); +} + +static struct emitter asm_emitter = { + .cell = asm_emit_cell, + .string = asm_emit_string, + .align = asm_emit_align, + .data = asm_emit_data, + .beginnode = asm_emit_beginnode, + .endnode = asm_emit_endnode, + .property = asm_emit_property, +}; + +static int stringtable_insert(struct data *d, const char *str) +{ + int i; + + /* FIXME: do this more efficiently? */ + + for (i = 0; i < d->len; i++) { + if (streq(str, d->val + i)) + return i; + } + + *d = data_append_data(*d, str, strlen(str)+1); + return i; +} + +static void flatten_tree(struct node *tree, struct emitter *emit, + void *etarget, struct data *strbuf, + struct version_info *vi) +{ + struct property *prop; + struct node *child; + bool seen_name_prop = false; + + if (tree->deleted) + return; + + emit->beginnode(etarget, tree->labels); + + if (vi->flags & FTF_FULLPATH) + emit->string(etarget, tree->fullpath, 0); + else + emit->string(etarget, tree->name, 0); + + emit->align(etarget, sizeof(cell_t)); + + for_each_property(tree, prop) { + int nameoff; + + if (streq(prop->name, "name")) + seen_name_prop = true; + + nameoff = stringtable_insert(strbuf, prop->name); + + emit->property(etarget, prop->labels); + emit->cell(etarget, prop->val.len); + emit->cell(etarget, nameoff); + + if ((vi->flags & FTF_VARALIGN) && (prop->val.len >= 8)) + emit->align(etarget, 8); + + emit->data(etarget, prop->val); + emit->align(etarget, sizeof(cell_t)); + } + + if ((vi->flags & FTF_NAMEPROPS) && !seen_name_prop) { + emit->property(etarget, NULL); + emit->cell(etarget, tree->basenamelen+1); + emit->cell(etarget, stringtable_insert(strbuf, "name")); + + if ((vi->flags & FTF_VARALIGN) && ((tree->basenamelen+1) >= 8)) + emit->align(etarget, 8); + + emit->string(etarget, tree->name, tree->basenamelen); + emit->align(etarget, sizeof(cell_t)); + } + + for_each_child(tree, child) { + flatten_tree(child, emit, etarget, strbuf, vi); + } + + emit->endnode(etarget, tree->labels); +} + +static struct data flatten_reserve_list(struct reserve_info *reservelist, + struct version_info *vi) +{ + struct reserve_info *re; + struct data d = empty_data; + int j; + + for (re = reservelist; re; re = re->next) { + d = data_append_re(d, re->address, re->size); + } + /* + * Add additional reserved slots if the user asked for them. + */ + for (j = 0; j < reservenum; j++) { + d = data_append_re(d, 0, 0); + } + + return d; +} + +static void make_fdt_header(struct fdt_header *fdt, + struct version_info *vi, + int reservesize, int dtsize, int strsize, + int boot_cpuid_phys) +{ + int reserve_off; + + reservesize += sizeof(struct fdt_reserve_entry); + + memset(fdt, 0xff, sizeof(*fdt)); + + fdt->magic = cpu_to_fdt32(FDT_MAGIC); + fdt->version = cpu_to_fdt32(vi->version); + fdt->last_comp_version = cpu_to_fdt32(vi->last_comp_version); + + /* Reserve map should be doubleword aligned */ + reserve_off = ALIGN(vi->hdr_size, 8); + + fdt->off_mem_rsvmap = cpu_to_fdt32(reserve_off); + fdt->off_dt_struct = cpu_to_fdt32(reserve_off + reservesize); + fdt->off_dt_strings = cpu_to_fdt32(reserve_off + reservesize + + dtsize); + fdt->totalsize = cpu_to_fdt32(reserve_off + reservesize + dtsize + strsize); + + if (vi->flags & FTF_BOOTCPUID) + fdt->boot_cpuid_phys = cpu_to_fdt32(boot_cpuid_phys); + if (vi->flags & FTF_STRTABSIZE) + fdt->size_dt_strings = cpu_to_fdt32(strsize); + if (vi->flags & FTF_STRUCTSIZE) + fdt->size_dt_struct = cpu_to_fdt32(dtsize); +} + +void dt_to_blob(FILE *f, struct dt_info *dti, int version) +{ + struct version_info *vi = NULL; + int i; + struct data blob = empty_data; + struct data reservebuf = empty_data; + struct data dtbuf = empty_data; + struct data strbuf = empty_data; + struct fdt_header fdt; + int padlen = 0; + + for (i = 0; i < ARRAY_SIZE(version_table); i++) { + if (version_table[i].version == version) + vi = &version_table[i]; + } + if (!vi) + die("Unknown device tree blob version %d\n", version); + + flatten_tree(dti->dt, &bin_emitter, &dtbuf, &strbuf, vi); + bin_emit_cell(&dtbuf, FDT_END); + + reservebuf = flatten_reserve_list(dti->reservelist, vi); + + /* Make header */ + make_fdt_header(&fdt, vi, reservebuf.len, dtbuf.len, strbuf.len, + dti->boot_cpuid_phys); + + /* + * If the user asked for more space than is used, adjust the totalsize. + */ + if (minsize > 0) { + padlen = minsize - fdt32_to_cpu(fdt.totalsize); + if (padlen < 0) { + padlen = 0; + if (quiet < 1) + fprintf(stderr, + "Warning: blob size %"PRIu32" >= minimum size %d\n", + fdt32_to_cpu(fdt.totalsize), minsize); + } + } + + if (padsize > 0) + padlen = padsize; + + if (alignsize > 0) + padlen = ALIGN(fdt32_to_cpu(fdt.totalsize) + padlen, alignsize) + - fdt32_to_cpu(fdt.totalsize); + + if (padlen > 0) { + int tsize = fdt32_to_cpu(fdt.totalsize); + tsize += padlen; + fdt.totalsize = cpu_to_fdt32(tsize); + } + + /* + * Assemble the blob: start with the header, add with alignment + * the reserve buffer, add the reserve map terminating zeroes, + * the device tree itself, and finally the strings. + */ + blob = data_append_data(blob, &fdt, vi->hdr_size); + blob = data_append_align(blob, 8); + blob = data_merge(blob, reservebuf); + blob = data_append_zeroes(blob, sizeof(struct fdt_reserve_entry)); + blob = data_merge(blob, dtbuf); + blob = data_merge(blob, strbuf); + + /* + * If the user asked for more space than is used, pad out the blob. + */ + if (padlen > 0) + blob = data_append_zeroes(blob, padlen); + + if (fwrite(blob.val, blob.len, 1, f) != 1) { + if (ferror(f)) + die("Error writing device tree blob: %s\n", + strerror(errno)); + else + die("Short write on device tree blob\n"); + } + + /* + * data_merge() frees the right-hand element so only the blob + * remains to be freed. + */ + data_free(blob); +} + +static void dump_stringtable_asm(FILE *f, struct data strbuf) +{ + const char *p; + int len; + + p = strbuf.val; + + while (p < (strbuf.val + strbuf.len)) { + len = strlen(p); + fprintf(f, "\t.string \"%s\"\n", p); + p += len+1; + } +} + +void dt_to_asm(FILE *f, struct dt_info *dti, int version) +{ + struct version_info *vi = NULL; + int i; + struct data strbuf = empty_data; + struct reserve_info *re; + const char *symprefix = "dt"; + + for (i = 0; i < ARRAY_SIZE(version_table); i++) { + if (version_table[i].version == version) + vi = &version_table[i]; + } + if (!vi) + die("Unknown device tree blob version %d\n", version); + + fprintf(f, "/* autogenerated by dtc, do not edit */\n\n"); + + emit_label(f, symprefix, "blob_start"); + emit_label(f, symprefix, "header"); + fprintf(f, "\t/* magic */\n"); + asm_emit_cell(f, FDT_MAGIC); + fprintf(f, "\t/* totalsize */\n"); + ASM_EMIT_BELONG(f, "_%s_blob_abs_end - _%s_blob_start", + symprefix, symprefix); + fprintf(f, "\t/* off_dt_struct */\n"); + ASM_EMIT_BELONG(f, "_%s_struct_start - _%s_blob_start", + symprefix, symprefix); + fprintf(f, "\t/* off_dt_strings */\n"); + ASM_EMIT_BELONG(f, "_%s_strings_start - _%s_blob_start", + symprefix, symprefix); + fprintf(f, "\t/* off_mem_rsvmap */\n"); + ASM_EMIT_BELONG(f, "_%s_reserve_map - _%s_blob_start", + symprefix, symprefix); + fprintf(f, "\t/* version */\n"); + asm_emit_cell(f, vi->version); + fprintf(f, "\t/* last_comp_version */\n"); + asm_emit_cell(f, vi->last_comp_version); + + if (vi->flags & FTF_BOOTCPUID) { + fprintf(f, "\t/* boot_cpuid_phys */\n"); + asm_emit_cell(f, dti->boot_cpuid_phys); + } + + if (vi->flags & FTF_STRTABSIZE) { + fprintf(f, "\t/* size_dt_strings */\n"); + ASM_EMIT_BELONG(f, "_%s_strings_end - _%s_strings_start", + symprefix, symprefix); + } + + if (vi->flags & FTF_STRUCTSIZE) { + fprintf(f, "\t/* size_dt_struct */\n"); + ASM_EMIT_BELONG(f, "_%s_struct_end - _%s_struct_start", + symprefix, symprefix); + } + + /* + * Reserve map entries. + * Align the reserve map to a doubleword boundary. + * Each entry is an (address, size) pair of u64 values. + * Always supply a zero-sized temination entry. + */ + asm_emit_align(f, 8); + emit_label(f, symprefix, "reserve_map"); + + fprintf(f, "/* Memory reserve map from source file */\n"); + + /* + * Use .long on high and low halves of u64s to avoid .quad + * as it appears .quad isn't available in some assemblers. + */ + for (re = dti->reservelist; re; re = re->next) { + struct label *l; + + for_each_label(re->labels, l) { + fprintf(f, "\t.globl\t%s\n", l->label); + fprintf(f, "%s:\n", l->label); + } + ASM_EMIT_BELONG(f, "0x%08x", (unsigned int)(re->address >> 32)); + ASM_EMIT_BELONG(f, "0x%08x", + (unsigned int)(re->address & 0xffffffff)); + ASM_EMIT_BELONG(f, "0x%08x", (unsigned int)(re->size >> 32)); + ASM_EMIT_BELONG(f, "0x%08x", (unsigned int)(re->size & 0xffffffff)); + } + for (i = 0; i < reservenum; i++) { + fprintf(f, "\t.long\t0, 0\n\t.long\t0, 0\n"); + } + + fprintf(f, "\t.long\t0, 0\n\t.long\t0, 0\n"); + + emit_label(f, symprefix, "struct_start"); + flatten_tree(dti->dt, &asm_emitter, f, &strbuf, vi); + + fprintf(f, "\t/* FDT_END */\n"); + asm_emit_cell(f, FDT_END); + emit_label(f, symprefix, "struct_end"); + + emit_label(f, symprefix, "strings_start"); + dump_stringtable_asm(f, strbuf); + emit_label(f, symprefix, "strings_end"); + + emit_label(f, symprefix, "blob_end"); + + /* + * If the user asked for more space than is used, pad it out. + */ + if (minsize > 0) { + fprintf(f, "\t.space\t%d - (_%s_blob_end - _%s_blob_start), 0\n", + minsize, symprefix, symprefix); + } + if (padsize > 0) { + fprintf(f, "\t.space\t%d, 0\n", padsize); + } + if (alignsize > 0) + asm_emit_align(f, alignsize); + emit_label(f, symprefix, "blob_abs_end"); + + data_free(strbuf); +} + +struct inbuf { + char *base, *limit, *ptr; +}; + +static void inbuf_init(struct inbuf *inb, void *base, void *limit) +{ + inb->base = base; + inb->limit = limit; + inb->ptr = inb->base; +} + +static void flat_read_chunk(struct inbuf *inb, void *p, int len) +{ + if ((inb->ptr + len) > inb->limit) + die("Premature end of data parsing flat device tree\n"); + + memcpy(p, inb->ptr, len); + + inb->ptr += len; +} + +static uint32_t flat_read_word(struct inbuf *inb) +{ + fdt32_t val; + + assert(((inb->ptr - inb->base) % sizeof(val)) == 0); + + flat_read_chunk(inb, &val, sizeof(val)); + + return fdt32_to_cpu(val); +} + +static void flat_realign(struct inbuf *inb, int align) +{ + int off = inb->ptr - inb->base; + + inb->ptr = inb->base + ALIGN(off, align); + if (inb->ptr > inb->limit) + die("Premature end of data parsing flat device tree\n"); +} + +static char *flat_read_string(struct inbuf *inb) +{ + int len = 0; + const char *p = inb->ptr; + char *str; + + do { + if (p >= inb->limit) + die("Premature end of data parsing flat device tree\n"); + len++; + } while ((*p++) != '\0'); + + str = xstrdup(inb->ptr); + + inb->ptr += len; + + flat_realign(inb, sizeof(uint32_t)); + + return str; +} + +static struct data flat_read_data(struct inbuf *inb, int len) +{ + struct data d = empty_data; + + if (len == 0) + return empty_data; + + d = data_grow_for(d, len); + d.len = len; + + flat_read_chunk(inb, d.val, len); + + flat_realign(inb, sizeof(uint32_t)); + + return d; +} + +static char *flat_read_stringtable(struct inbuf *inb, int offset) +{ + const char *p; + + p = inb->base + offset; + while (1) { + if (p >= inb->limit || p < inb->base) + die("String offset %d overruns string table\n", + offset); + + if (*p == '\0') + break; + + p++; + } + + return xstrdup(inb->base + offset); +} + +static struct property *flat_read_property(struct inbuf *dtbuf, + struct inbuf *strbuf, int flags) +{ + uint32_t proplen, stroff; + char *name; + struct data val; + + proplen = flat_read_word(dtbuf); + stroff = flat_read_word(dtbuf); + + name = flat_read_stringtable(strbuf, stroff); + + if ((flags & FTF_VARALIGN) && (proplen >= 8)) + flat_realign(dtbuf, 8); + + val = flat_read_data(dtbuf, proplen); + + return build_property(name, val, NULL); +} + + +static struct reserve_info *flat_read_mem_reserve(struct inbuf *inb) +{ + struct reserve_info *reservelist = NULL; + struct reserve_info *new; + struct fdt_reserve_entry re; + + /* + * Each entry is a pair of u64 (addr, size) values for 4 cell_t's. + * List terminates at an entry with size equal to zero. + * + * First pass, count entries. + */ + while (1) { + uint64_t address, size; + + flat_read_chunk(inb, &re, sizeof(re)); + address = fdt64_to_cpu(re.address); + size = fdt64_to_cpu(re.size); + if (size == 0) + break; + + new = build_reserve_entry(address, size); + reservelist = add_reserve_entry(reservelist, new); + } + + return reservelist; +} + + +static char *nodename_from_path(const char *ppath, const char *cpath) +{ + int plen; + + plen = strlen(ppath); + + if (!strstarts(cpath, ppath)) + die("Path \"%s\" is not valid as a child of \"%s\"\n", + cpath, ppath); + + /* root node is a special case */ + if (!streq(ppath, "/")) + plen++; + + return xstrdup(cpath + plen); +} + +static struct node *unflatten_tree(struct inbuf *dtbuf, + struct inbuf *strbuf, + const char *parent_flatname, int flags) +{ + struct node *node; + char *flatname; + uint32_t val; + + node = build_node(NULL, NULL, NULL); + + flatname = flat_read_string(dtbuf); + + if (flags & FTF_FULLPATH) + node->name = nodename_from_path(parent_flatname, flatname); + else + node->name = flatname; + + do { + struct property *prop; + struct node *child; + + val = flat_read_word(dtbuf); + switch (val) { + case FDT_PROP: + if (node->children) + fprintf(stderr, "Warning: Flat tree input has " + "subnodes preceding a property.\n"); + prop = flat_read_property(dtbuf, strbuf, flags); + add_property(node, prop); + break; + + case FDT_BEGIN_NODE: + child = unflatten_tree(dtbuf,strbuf, flatname, flags); + add_child(node, child); + break; + + case FDT_END_NODE: + break; + + case FDT_END: + die("Premature FDT_END in device tree blob\n"); + break; + + case FDT_NOP: + if (!(flags & FTF_NOPS)) + fprintf(stderr, "Warning: NOP tag found in flat tree" + " version <16\n"); + + /* Ignore */ + break; + + default: + die("Invalid opcode word %08x in device tree blob\n", + val); + } + } while (val != FDT_END_NODE); + + if (node->name != flatname) { + free(flatname); + } + + return node; +} + + +struct dt_info *dt_from_blob(const char *fname) +{ + FILE *f; + fdt32_t magic_buf, totalsize_buf; + uint32_t magic, totalsize, version, size_dt, boot_cpuid_phys; + uint32_t off_dt, off_str, off_mem_rsvmap; + int rc; + char *blob; + struct fdt_header *fdt; + char *p; + struct inbuf dtbuf, strbuf; + struct inbuf memresvbuf; + int sizeleft; + struct reserve_info *reservelist; + struct node *tree; + uint32_t val; + int flags = 0; + + f = srcfile_relative_open(fname, NULL); + + rc = fread(&magic_buf, sizeof(magic_buf), 1, f); + if (ferror(f)) + die("Error reading DT blob magic number: %s\n", + strerror(errno)); + if (rc < 1) { + if (feof(f)) + die("EOF reading DT blob magic number\n"); + else + die("Mysterious short read reading magic number\n"); + } + + magic = fdt32_to_cpu(magic_buf); + if (magic != FDT_MAGIC) + die("Blob has incorrect magic number\n"); + + rc = fread(&totalsize_buf, sizeof(totalsize_buf), 1, f); + if (ferror(f)) + die("Error reading DT blob size: %s\n", strerror(errno)); + if (rc < 1) { + if (feof(f)) + die("EOF reading DT blob size\n"); + else + die("Mysterious short read reading blob size\n"); + } + + totalsize = fdt32_to_cpu(totalsize_buf); + if (totalsize < FDT_V1_SIZE) + die("DT blob size (%d) is too small\n", totalsize); + + blob = xmalloc(totalsize); + + fdt = (struct fdt_header *)blob; + fdt->magic = cpu_to_fdt32(magic); + fdt->totalsize = cpu_to_fdt32(totalsize); + + sizeleft = totalsize - sizeof(magic) - sizeof(totalsize); + p = blob + sizeof(magic) + sizeof(totalsize); + + while (sizeleft) { + if (feof(f)) + die("EOF before reading %d bytes of DT blob\n", + totalsize); + + rc = fread(p, 1, sizeleft, f); + if (ferror(f)) + die("Error reading DT blob: %s\n", + strerror(errno)); + + sizeleft -= rc; + p += rc; + } + + off_dt = fdt32_to_cpu(fdt->off_dt_struct); + off_str = fdt32_to_cpu(fdt->off_dt_strings); + off_mem_rsvmap = fdt32_to_cpu(fdt->off_mem_rsvmap); + version = fdt32_to_cpu(fdt->version); + boot_cpuid_phys = fdt32_to_cpu(fdt->boot_cpuid_phys); + + if (off_mem_rsvmap >= totalsize) + die("Mem Reserve structure offset exceeds total size\n"); + + if (off_dt >= totalsize) + die("DT structure offset exceeds total size\n"); + + if (off_str > totalsize) + die("String table offset exceeds total size\n"); + + if (version >= 3) { + uint32_t size_str = fdt32_to_cpu(fdt->size_dt_strings); + if ((off_str+size_str < off_str) || (off_str+size_str > totalsize)) + die("String table extends past total size\n"); + inbuf_init(&strbuf, blob + off_str, blob + off_str + size_str); + } else { + inbuf_init(&strbuf, blob + off_str, blob + totalsize); + } + + if (version >= 17) { + size_dt = fdt32_to_cpu(fdt->size_dt_struct); + if ((off_dt+size_dt < off_dt) || (off_dt+size_dt > totalsize)) + die("Structure block extends past total size\n"); + } + + if (version < 16) { + flags |= FTF_FULLPATH | FTF_NAMEPROPS | FTF_VARALIGN; + } else { + flags |= FTF_NOPS; + } + + inbuf_init(&memresvbuf, + blob + off_mem_rsvmap, blob + totalsize); + inbuf_init(&dtbuf, blob + off_dt, blob + totalsize); + + reservelist = flat_read_mem_reserve(&memresvbuf); + + val = flat_read_word(&dtbuf); + + if (val != FDT_BEGIN_NODE) + die("Device tree blob doesn't begin with FDT_BEGIN_NODE (begins with 0x%08x)\n", val); + + tree = unflatten_tree(&dtbuf, &strbuf, "", flags); + + val = flat_read_word(&dtbuf); + if (val != FDT_END) + die("Device tree blob doesn't end with FDT_END\n"); + + free(blob); + + fclose(f); + + return build_dt_info(DTSF_V1, reservelist, tree, boot_cpuid_phys); +} diff --git a/src/net/scripts/dtc/fstree.c b/src/net/scripts/dtc/fstree.c new file mode 100644 index 0000000..5e59594 --- /dev/null +++ b/src/net/scripts/dtc/fstree.c @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (C) Copyright David Gibson <dwg@au1.ibm.com>, IBM Corporation. 2005. + */ + +#include "dtc.h" + +#include <dirent.h> +#include <sys/stat.h> + +static struct node *read_fstree(const char *dirname) +{ + DIR *d; + struct dirent *de; + struct stat st; + struct node *tree; + + d = opendir(dirname); + if (!d) + die("Couldn't opendir() \"%s\": %s\n", dirname, strerror(errno)); + + tree = build_node(NULL, NULL, NULL); + + while ((de = readdir(d)) != NULL) { + char *tmpname; + + if (streq(de->d_name, ".") + || streq(de->d_name, "..")) + continue; + + tmpname = join_path(dirname, de->d_name); + + if (stat(tmpname, &st) < 0) + die("stat(%s): %s\n", tmpname, strerror(errno)); + + if (S_ISREG(st.st_mode)) { + struct property *prop; + FILE *pfile; + + pfile = fopen(tmpname, "rb"); + if (! pfile) { + fprintf(stderr, + "WARNING: Cannot open %s: %s\n", + tmpname, strerror(errno)); + } else { + prop = build_property(xstrdup(de->d_name), + data_copy_file(pfile, + st.st_size), + NULL); + add_property(tree, prop); + fclose(pfile); + } + } else if (S_ISDIR(st.st_mode)) { + struct node *newchild; + + newchild = read_fstree(tmpname); + newchild = name_node(newchild, xstrdup(de->d_name)); + add_child(tree, newchild); + } + + free(tmpname); + } + + closedir(d); + return tree; +} + +struct dt_info *dt_from_fs(const char *dirname) +{ + struct node *tree; + + tree = read_fstree(dirname); + tree = name_node(tree, ""); + + return build_dt_info(DTSF_V1, NULL, tree, guess_boot_cpuid(tree)); +} diff --git a/src/net/scripts/dtc/libfdt/fdt.c b/src/net/scripts/dtc/libfdt/fdt.c new file mode 100644 index 0000000..6cf2fa0 --- /dev/null +++ b/src/net/scripts/dtc/libfdt/fdt.c @@ -0,0 +1,327 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * libfdt - Flat Device Tree manipulation + * Copyright (C) 2006 David Gibson, IBM Corporation. + */ +#include "libfdt_env.h" + +#include <fdt.h> +#include <libfdt.h> + +#include "libfdt_internal.h" + +/* + * Minimal sanity check for a read-only tree. fdt_ro_probe_() checks + * that the given buffer contains what appears to be a flattened + * device tree with sane information in its header. + */ +int32_t fdt_ro_probe_(const void *fdt) +{ + uint32_t totalsize = fdt_totalsize(fdt); + + if (can_assume(VALID_DTB)) + return totalsize; + + if (fdt_magic(fdt) == FDT_MAGIC) { + /* Complete tree */ + if (!can_assume(LATEST)) { + if (fdt_version(fdt) < FDT_FIRST_SUPPORTED_VERSION) + return -FDT_ERR_BADVERSION; + if (fdt_last_comp_version(fdt) > + FDT_LAST_SUPPORTED_VERSION) + return -FDT_ERR_BADVERSION; + } + } else if (fdt_magic(fdt) == FDT_SW_MAGIC) { + /* Unfinished sequential-write blob */ + if (!can_assume(VALID_INPUT) && fdt_size_dt_struct(fdt) == 0) + return -FDT_ERR_BADSTATE; + } else { + return -FDT_ERR_BADMAGIC; + } + + if (totalsize < INT32_MAX) + return totalsize; + else + return -FDT_ERR_TRUNCATED; +} + +static int check_off_(uint32_t hdrsize, uint32_t totalsize, uint32_t off) +{ + return (off >= hdrsize) && (off <= totalsize); +} + +static int check_block_(uint32_t hdrsize, uint32_t totalsize, + uint32_t base, uint32_t size) +{ + if (!check_off_(hdrsize, totalsize, base)) + return 0; /* block start out of bounds */ + if ((base + size) < base) + return 0; /* overflow */ + if (!check_off_(hdrsize, totalsize, base + size)) + return 0; /* block end out of bounds */ + return 1; +} + +size_t fdt_header_size_(uint32_t version) +{ + if (version <= 1) + return FDT_V1_SIZE; + else if (version <= 2) + return FDT_V2_SIZE; + else if (version <= 3) + return FDT_V3_SIZE; + else if (version <= 16) + return FDT_V16_SIZE; + else + return FDT_V17_SIZE; +} + +size_t fdt_header_size(const void *fdt) +{ + return can_assume(LATEST) ? FDT_V17_SIZE : + fdt_header_size_(fdt_version(fdt)); +} + +int fdt_check_header(const void *fdt) +{ + size_t hdrsize; + + if (fdt_magic(fdt) != FDT_MAGIC) + return -FDT_ERR_BADMAGIC; + if (!can_assume(LATEST)) { + if ((fdt_version(fdt) < FDT_FIRST_SUPPORTED_VERSION) + || (fdt_last_comp_version(fdt) > + FDT_LAST_SUPPORTED_VERSION)) + return -FDT_ERR_BADVERSION; + if (fdt_version(fdt) < fdt_last_comp_version(fdt)) + return -FDT_ERR_BADVERSION; + } + hdrsize = fdt_header_size(fdt); + if (!can_assume(VALID_DTB)) { + + if ((fdt_totalsize(fdt) < hdrsize) + || (fdt_totalsize(fdt) > INT_MAX)) + return -FDT_ERR_TRUNCATED; + + /* Bounds check memrsv block */ + if (!check_off_(hdrsize, fdt_totalsize(fdt), + fdt_off_mem_rsvmap(fdt))) + return -FDT_ERR_TRUNCATED; + } + + if (!can_assume(VALID_DTB)) { + /* Bounds check structure block */ + if (!can_assume(LATEST) && fdt_version(fdt) < 17) { + if (!check_off_(hdrsize, fdt_totalsize(fdt), + fdt_off_dt_struct(fdt))) + return -FDT_ERR_TRUNCATED; + } else { + if (!check_block_(hdrsize, fdt_totalsize(fdt), + fdt_off_dt_struct(fdt), + fdt_size_dt_struct(fdt))) + return -FDT_ERR_TRUNCATED; + } + + /* Bounds check strings block */ + if (!check_block_(hdrsize, fdt_totalsize(fdt), + fdt_off_dt_strings(fdt), + fdt_size_dt_strings(fdt))) + return -FDT_ERR_TRUNCATED; + } + + return 0; +} + +const void *fdt_offset_ptr(const void *fdt, int offset, unsigned int len) +{ + unsigned int uoffset = offset; + unsigned int absoffset = offset + fdt_off_dt_struct(fdt); + + if (offset < 0) + return NULL; + + if (!can_assume(VALID_INPUT)) + if ((absoffset < uoffset) + || ((absoffset + len) < absoffset) + || (absoffset + len) > fdt_totalsize(fdt)) + return NULL; + + if (can_assume(LATEST) || fdt_version(fdt) >= 0x11) + if (((uoffset + len) < uoffset) + || ((offset + len) > fdt_size_dt_struct(fdt))) + return NULL; + + return fdt_offset_ptr_(fdt, offset); +} + +uint32_t fdt_next_tag(const void *fdt, int startoffset, int *nextoffset) +{ + const fdt32_t *tagp, *lenp; + uint32_t tag; + int offset = startoffset; + const char *p; + + *nextoffset = -FDT_ERR_TRUNCATED; + tagp = fdt_offset_ptr(fdt, offset, FDT_TAGSIZE); + if (!can_assume(VALID_DTB) && !tagp) + return FDT_END; /* premature end */ + tag = fdt32_to_cpu(*tagp); + offset += FDT_TAGSIZE; + + *nextoffset = -FDT_ERR_BADSTRUCTURE; + switch (tag) { + case FDT_BEGIN_NODE: + /* skip name */ + do { + p = fdt_offset_ptr(fdt, offset++, 1); + } while (p && (*p != '\0')); + if (!can_assume(VALID_DTB) && !p) + return FDT_END; /* premature end */ + break; + + case FDT_PROP: + lenp = fdt_offset_ptr(fdt, offset, sizeof(*lenp)); + if (!can_assume(VALID_DTB) && !lenp) + return FDT_END; /* premature end */ + /* skip-name offset, length and value */ + offset += sizeof(struct fdt_property) - FDT_TAGSIZE + + fdt32_to_cpu(*lenp); + if (!can_assume(LATEST) && + fdt_version(fdt) < 0x10 && fdt32_to_cpu(*lenp) >= 8 && + ((offset - fdt32_to_cpu(*lenp)) % 8) != 0) + offset += 4; + break; + + case FDT_END: + case FDT_END_NODE: + case FDT_NOP: + break; + + default: + return FDT_END; + } + + if (!fdt_offset_ptr(fdt, startoffset, offset - startoffset)) + return FDT_END; /* premature end */ + + *nextoffset = FDT_TAGALIGN(offset); + return tag; +} + +int fdt_check_node_offset_(const void *fdt, int offset) +{ + if (!can_assume(VALID_INPUT) + && ((offset < 0) || (offset % FDT_TAGSIZE))) + return -FDT_ERR_BADOFFSET; + + if (fdt_next_tag(fdt, offset, &offset) != FDT_BEGIN_NODE) + return -FDT_ERR_BADOFFSET; + + return offset; +} + +int fdt_check_prop_offset_(const void *fdt, int offset) +{ + if (!can_assume(VALID_INPUT) + && ((offset < 0) || (offset % FDT_TAGSIZE))) + return -FDT_ERR_BADOFFSET; + + if (fdt_next_tag(fdt, offset, &offset) != FDT_PROP) + return -FDT_ERR_BADOFFSET; + + return offset; +} + +int fdt_next_node(const void *fdt, int offset, int *depth) +{ + int nextoffset = 0; + uint32_t tag; + + if (offset >= 0) + if ((nextoffset = fdt_check_node_offset_(fdt, offset)) < 0) + return nextoffset; + + do { + offset = nextoffset; + tag = fdt_next_tag(fdt, offset, &nextoffset); + + switch (tag) { + case FDT_PROP: + case FDT_NOP: + break; + + case FDT_BEGIN_NODE: + if (depth) + (*depth)++; + break; + + case FDT_END_NODE: + if (depth && ((--(*depth)) < 0)) + return nextoffset; + break; + + case FDT_END: + if ((nextoffset >= 0) + || ((nextoffset == -FDT_ERR_TRUNCATED) && !depth)) + return -FDT_ERR_NOTFOUND; + else + return nextoffset; + } + } while (tag != FDT_BEGIN_NODE); + + return offset; +} + +int fdt_first_subnode(const void *fdt, int offset) +{ + int depth = 0; + + offset = fdt_next_node(fdt, offset, &depth); + if (offset < 0 || depth != 1) + return -FDT_ERR_NOTFOUND; + + return offset; +} + +int fdt_next_subnode(const void *fdt, int offset) +{ + int depth = 1; + + /* + * With respect to the parent, the depth of the next subnode will be + * the same as the last. + */ + do { + offset = fdt_next_node(fdt, offset, &depth); + if (offset < 0 || depth < 1) + return -FDT_ERR_NOTFOUND; + } while (depth > 1); + + return offset; +} + +const char *fdt_find_string_(const char *strtab, int tabsize, const char *s) +{ + int len = strlen(s) + 1; + const char *last = strtab + tabsize - len; + const char *p; + + for (p = strtab; p <= last; p++) + if (memcmp(p, s, len) == 0) + return p; + return NULL; +} + +int fdt_move(const void *fdt, void *buf, int bufsize) +{ + if (!can_assume(VALID_INPUT) && bufsize < 0) + return -FDT_ERR_NOSPACE; + + FDT_RO_PROBE(fdt); + + if (fdt_totalsize(fdt) > (unsigned int)bufsize) + return -FDT_ERR_NOSPACE; + + memmove(buf, fdt, fdt_totalsize(fdt)); + return 0; +} diff --git a/src/net/scripts/dtc/libfdt/fdt.h b/src/net/scripts/dtc/libfdt/fdt.h new file mode 100644 index 0000000..f2e6880 --- /dev/null +++ b/src/net/scripts/dtc/libfdt/fdt.h @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) */ +#ifndef FDT_H +#define FDT_H +/* + * libfdt - Flat Device Tree manipulation + * Copyright (C) 2006 David Gibson, IBM Corporation. + * Copyright 2012 Kim Phillips, Freescale Semiconductor. + */ + +#ifndef __ASSEMBLY__ + +struct fdt_header { + fdt32_t magic; /* magic word FDT_MAGIC */ + fdt32_t totalsize; /* total size of DT block */ + fdt32_t off_dt_struct; /* offset to structure */ + fdt32_t off_dt_strings; /* offset to strings */ + fdt32_t off_mem_rsvmap; /* offset to memory reserve map */ + fdt32_t version; /* format version */ + fdt32_t last_comp_version; /* last compatible version */ + + /* version 2 fields below */ + fdt32_t boot_cpuid_phys; /* Which physical CPU id we're + booting on */ + /* version 3 fields below */ + fdt32_t size_dt_strings; /* size of the strings block */ + + /* version 17 fields below */ + fdt32_t size_dt_struct; /* size of the structure block */ +}; + +struct fdt_reserve_entry { + fdt64_t address; + fdt64_t size; +}; + +struct fdt_node_header { + fdt32_t tag; + char name[0]; +}; + +struct fdt_property { + fdt32_t tag; + fdt32_t len; + fdt32_t nameoff; + char data[0]; +}; + +#endif /* !__ASSEMBLY */ + +#define FDT_MAGIC 0xd00dfeed /* 4: version, 4: total size */ +#define FDT_TAGSIZE sizeof(fdt32_t) + +#define FDT_BEGIN_NODE 0x1 /* Start node: full name */ +#define FDT_END_NODE 0x2 /* End node */ +#define FDT_PROP 0x3 /* Property: name off, + size, content */ +#define FDT_NOP 0x4 /* nop */ +#define FDT_END 0x9 + +#define FDT_V1_SIZE (7*sizeof(fdt32_t)) +#define FDT_V2_SIZE (FDT_V1_SIZE + sizeof(fdt32_t)) +#define FDT_V3_SIZE (FDT_V2_SIZE + sizeof(fdt32_t)) +#define FDT_V16_SIZE FDT_V3_SIZE +#define FDT_V17_SIZE (FDT_V16_SIZE + sizeof(fdt32_t)) + +#endif /* FDT_H */ diff --git a/src/net/scripts/dtc/libfdt/fdt_addresses.c b/src/net/scripts/dtc/libfdt/fdt_addresses.c new file mode 100644 index 0000000..9a82cd0 --- /dev/null +++ b/src/net/scripts/dtc/libfdt/fdt_addresses.c @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * libfdt - Flat Device Tree manipulation + * Copyright (C) 2014 David Gibson <david@gibson.dropbear.id.au> + * Copyright (C) 2018 embedded brains GmbH + */ +#include "libfdt_env.h" + +#include <fdt.h> +#include <libfdt.h> + +#include "libfdt_internal.h" + +static int fdt_cells(const void *fdt, int nodeoffset, const char *name) +{ + const fdt32_t *c; + uint32_t val; + int len; + + c = fdt_getprop(fdt, nodeoffset, name, &len); + if (!c) + return len; + + if (len != sizeof(*c)) + return -FDT_ERR_BADNCELLS; + + val = fdt32_to_cpu(*c); + if (val > FDT_MAX_NCELLS) + return -FDT_ERR_BADNCELLS; + + return (int)val; +} + +int fdt_address_cells(const void *fdt, int nodeoffset) +{ + int val; + + val = fdt_cells(fdt, nodeoffset, "#address-cells"); + if (val == 0) + return -FDT_ERR_BADNCELLS; + if (val == -FDT_ERR_NOTFOUND) + return 2; + return val; +} + +int fdt_size_cells(const void *fdt, int nodeoffset) +{ + int val; + + val = fdt_cells(fdt, nodeoffset, "#size-cells"); + if (val == -FDT_ERR_NOTFOUND) + return 1; + return val; +} + +/* This function assumes that [address|size]_cells is 1 or 2 */ +int fdt_appendprop_addrrange(void *fdt, int parent, int nodeoffset, + const char *name, uint64_t addr, uint64_t size) +{ + int addr_cells, size_cells, ret; + uint8_t data[sizeof(fdt64_t) * 2], *prop; + + ret = fdt_address_cells(fdt, parent); + if (ret < 0) + return ret; + addr_cells = ret; + + ret = fdt_size_cells(fdt, parent); + if (ret < 0) + return ret; + size_cells = ret; + + /* check validity of address */ + prop = data; + if (addr_cells == 1) { + if ((addr > UINT32_MAX) || ((UINT32_MAX + 1 - addr) < size)) + return -FDT_ERR_BADVALUE; + + fdt32_st(prop, (uint32_t)addr); + } else if (addr_cells == 2) { + fdt64_st(prop, addr); + } else { + return -FDT_ERR_BADNCELLS; + } + + /* check validity of size */ + prop += addr_cells * sizeof(fdt32_t); + if (size_cells == 1) { + if (size > UINT32_MAX) + return -FDT_ERR_BADVALUE; + + fdt32_st(prop, (uint32_t)size); + } else if (size_cells == 2) { + fdt64_st(prop, size); + } else { + return -FDT_ERR_BADNCELLS; + } + + return fdt_appendprop(fdt, nodeoffset, name, data, + (addr_cells + size_cells) * sizeof(fdt32_t)); +} diff --git a/src/net/scripts/dtc/libfdt/fdt_empty_tree.c b/src/net/scripts/dtc/libfdt/fdt_empty_tree.c new file mode 100644 index 0000000..49d54d4 --- /dev/null +++ b/src/net/scripts/dtc/libfdt/fdt_empty_tree.c @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * libfdt - Flat Device Tree manipulation + * Copyright (C) 2012 David Gibson, IBM Corporation. + */ +#include "libfdt_env.h" + +#include <fdt.h> +#include <libfdt.h> + +#include "libfdt_internal.h" + +int fdt_create_empty_tree(void *buf, int bufsize) +{ + int err; + + err = fdt_create(buf, bufsize); + if (err) + return err; + + err = fdt_finish_reservemap(buf); + if (err) + return err; + + err = fdt_begin_node(buf, ""); + if (err) + return err; + + err = fdt_end_node(buf); + if (err) + return err; + + err = fdt_finish(buf); + if (err) + return err; + + return fdt_open_into(buf, buf, bufsize); +} diff --git a/src/net/scripts/dtc/libfdt/fdt_overlay.c b/src/net/scripts/dtc/libfdt/fdt_overlay.c new file mode 100644 index 0000000..d217e79 --- /dev/null +++ b/src/net/scripts/dtc/libfdt/fdt_overlay.c @@ -0,0 +1,882 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * libfdt - Flat Device Tree manipulation + * Copyright (C) 2016 Free Electrons + * Copyright (C) 2016 NextThing Co. + */ +#include "libfdt_env.h" + +#include <fdt.h> +#include <libfdt.h> + +#include "libfdt_internal.h" + +/** + * overlay_get_target_phandle - retrieves the target phandle of a fragment + * @fdto: pointer to the device tree overlay blob + * @fragment: node offset of the fragment in the overlay + * + * overlay_get_target_phandle() retrieves the target phandle of an + * overlay fragment when that fragment uses a phandle (target + * property) instead of a path (target-path property). + * + * returns: + * the phandle pointed by the target property + * 0, if the phandle was not found + * -1, if the phandle was malformed + */ +static uint32_t overlay_get_target_phandle(const void *fdto, int fragment) +{ + const fdt32_t *val; + int len; + + val = fdt_getprop(fdto, fragment, "target", &len); + if (!val) + return 0; + + if ((len != sizeof(*val)) || (fdt32_to_cpu(*val) == (uint32_t)-1)) + return (uint32_t)-1; + + return fdt32_to_cpu(*val); +} + +/** + * overlay_get_target - retrieves the offset of a fragment's target + * @fdt: Base device tree blob + * @fdto: Device tree overlay blob + * @fragment: node offset of the fragment in the overlay + * @pathp: pointer which receives the path of the target (or NULL) + * + * overlay_get_target() retrieves the target offset in the base + * device tree of a fragment, no matter how the actual targeting is + * done (through a phandle or a path) + * + * returns: + * the targeted node offset in the base device tree + * Negative error code on error + */ +static int overlay_get_target(const void *fdt, const void *fdto, + int fragment, char const **pathp) +{ + uint32_t phandle; + const char *path = NULL; + int path_len = 0, ret; + + /* Try first to do a phandle based lookup */ + phandle = overlay_get_target_phandle(fdto, fragment); + if (phandle == (uint32_t)-1) + return -FDT_ERR_BADPHANDLE; + + /* no phandle, try path */ + if (!phandle) { + /* And then a path based lookup */ + path = fdt_getprop(fdto, fragment, "target-path", &path_len); + if (path) + ret = fdt_path_offset(fdt, path); + else + ret = path_len; + } else + ret = fdt_node_offset_by_phandle(fdt, phandle); + + /* + * If we haven't found either a target or a + * target-path property in a node that contains a + * __overlay__ subnode (we wouldn't be called + * otherwise), consider it a improperly written + * overlay + */ + if (ret < 0 && path_len == -FDT_ERR_NOTFOUND) + ret = -FDT_ERR_BADOVERLAY; + + /* return on error */ + if (ret < 0) + return ret; + + /* return pointer to path (if available) */ + if (pathp) + *pathp = path ? path : NULL; + + return ret; +} + +/** + * overlay_phandle_add_offset - Increases a phandle by an offset + * @fdt: Base device tree blob + * @node: Device tree overlay blob + * @name: Name of the property to modify (phandle or linux,phandle) + * @delta: offset to apply + * + * overlay_phandle_add_offset() increments a node phandle by a given + * offset. + * + * returns: + * 0 on success. + * Negative error code on error + */ +static int overlay_phandle_add_offset(void *fdt, int node, + const char *name, uint32_t delta) +{ + const fdt32_t *val; + uint32_t adj_val; + int len; + + val = fdt_getprop(fdt, node, name, &len); + if (!val) + return len; + + if (len != sizeof(*val)) + return -FDT_ERR_BADPHANDLE; + + adj_val = fdt32_to_cpu(*val); + if ((adj_val + delta) < adj_val) + return -FDT_ERR_NOPHANDLES; + + adj_val += delta; + if (adj_val == (uint32_t)-1) + return -FDT_ERR_NOPHANDLES; + + return fdt_setprop_inplace_u32(fdt, node, name, adj_val); +} + +/** + * overlay_adjust_node_phandles - Offsets the phandles of a node + * @fdto: Device tree overlay blob + * @node: Offset of the node we want to adjust + * @delta: Offset to shift the phandles of + * + * overlay_adjust_node_phandles() adds a constant to all the phandles + * of a given node. This is mainly use as part of the overlay + * application process, when we want to update all the overlay + * phandles to not conflict with the overlays of the base device tree. + * + * returns: + * 0 on success + * Negative error code on failure + */ +static int overlay_adjust_node_phandles(void *fdto, int node, + uint32_t delta) +{ + int child; + int ret; + + ret = overlay_phandle_add_offset(fdto, node, "phandle", delta); + if (ret && ret != -FDT_ERR_NOTFOUND) + return ret; + + ret = overlay_phandle_add_offset(fdto, node, "linux,phandle", delta); + if (ret && ret != -FDT_ERR_NOTFOUND) + return ret; + + fdt_for_each_subnode(child, fdto, node) { + ret = overlay_adjust_node_phandles(fdto, child, delta); + if (ret) + return ret; + } + + return 0; +} + +/** + * overlay_adjust_local_phandles - Adjust the phandles of a whole overlay + * @fdto: Device tree overlay blob + * @delta: Offset to shift the phandles of + * + * overlay_adjust_local_phandles() adds a constant to all the + * phandles of an overlay. This is mainly use as part of the overlay + * application process, when we want to update all the overlay + * phandles to not conflict with the overlays of the base device tree. + * + * returns: + * 0 on success + * Negative error code on failure + */ +static int overlay_adjust_local_phandles(void *fdto, uint32_t delta) +{ + /* + * Start adjusting the phandles from the overlay root + */ + return overlay_adjust_node_phandles(fdto, 0, delta); +} + +/** + * overlay_update_local_node_references - Adjust the overlay references + * @fdto: Device tree overlay blob + * @tree_node: Node offset of the node to operate on + * @fixup_node: Node offset of the matching local fixups node + * @delta: Offset to shift the phandles of + * + * overlay_update_local_nodes_references() update the phandles + * pointing to a node within the device tree overlay by adding a + * constant delta. + * + * This is mainly used as part of a device tree application process, + * where you want the device tree overlays phandles to not conflict + * with the ones from the base device tree before merging them. + * + * returns: + * 0 on success + * Negative error code on failure + */ +static int overlay_update_local_node_references(void *fdto, + int tree_node, + int fixup_node, + uint32_t delta) +{ + int fixup_prop; + int fixup_child; + int ret; + + fdt_for_each_property_offset(fixup_prop, fdto, fixup_node) { + const fdt32_t *fixup_val; + const char *tree_val; + const char *name; + int fixup_len; + int tree_len; + int i; + + fixup_val = fdt_getprop_by_offset(fdto, fixup_prop, + &name, &fixup_len); + if (!fixup_val) + return fixup_len; + + if (fixup_len % sizeof(uint32_t)) + return -FDT_ERR_BADOVERLAY; + fixup_len /= sizeof(uint32_t); + + tree_val = fdt_getprop(fdto, tree_node, name, &tree_len); + if (!tree_val) { + if (tree_len == -FDT_ERR_NOTFOUND) + return -FDT_ERR_BADOVERLAY; + + return tree_len; + } + + for (i = 0; i < fixup_len; i++) { + fdt32_t adj_val; + uint32_t poffset; + + poffset = fdt32_to_cpu(fixup_val[i]); + + /* + * phandles to fixup can be unaligned. + * + * Use a memcpy for the architectures that do + * not support unaligned accesses. + */ + memcpy(&adj_val, tree_val + poffset, sizeof(adj_val)); + + adj_val = cpu_to_fdt32(fdt32_to_cpu(adj_val) + delta); + + ret = fdt_setprop_inplace_namelen_partial(fdto, + tree_node, + name, + strlen(name), + poffset, + &adj_val, + sizeof(adj_val)); + if (ret == -FDT_ERR_NOSPACE) + return -FDT_ERR_BADOVERLAY; + + if (ret) + return ret; + } + } + + fdt_for_each_subnode(fixup_child, fdto, fixup_node) { + const char *fixup_child_name = fdt_get_name(fdto, fixup_child, + NULL); + int tree_child; + + tree_child = fdt_subnode_offset(fdto, tree_node, + fixup_child_name); + if (tree_child == -FDT_ERR_NOTFOUND) + return -FDT_ERR_BADOVERLAY; + if (tree_child < 0) + return tree_child; + + ret = overlay_update_local_node_references(fdto, + tree_child, + fixup_child, + delta); + if (ret) + return ret; + } + + return 0; +} + +/** + * overlay_update_local_references - Adjust the overlay references + * @fdto: Device tree overlay blob + * @delta: Offset to shift the phandles of + * + * overlay_update_local_references() update all the phandles pointing + * to a node within the device tree overlay by adding a constant + * delta to not conflict with the base overlay. + * + * This is mainly used as part of a device tree application process, + * where you want the device tree overlays phandles to not conflict + * with the ones from the base device tree before merging them. + * + * returns: + * 0 on success + * Negative error code on failure + */ +static int overlay_update_local_references(void *fdto, uint32_t delta) +{ + int fixups; + + fixups = fdt_path_offset(fdto, "/__local_fixups__"); + if (fixups < 0) { + /* There's no local phandles to adjust, bail out */ + if (fixups == -FDT_ERR_NOTFOUND) + return 0; + + return fixups; + } + + /* + * Update our local references from the root of the tree + */ + return overlay_update_local_node_references(fdto, 0, fixups, + delta); +} + +/** + * overlay_fixup_one_phandle - Set an overlay phandle to the base one + * @fdt: Base Device Tree blob + * @fdto: Device tree overlay blob + * @symbols_off: Node offset of the symbols node in the base device tree + * @path: Path to a node holding a phandle in the overlay + * @path_len: number of path characters to consider + * @name: Name of the property holding the phandle reference in the overlay + * @name_len: number of name characters to consider + * @poffset: Offset within the overlay property where the phandle is stored + * @label: Label of the node referenced by the phandle + * + * overlay_fixup_one_phandle() resolves an overlay phandle pointing to + * a node in the base device tree. + * + * This is part of the device tree overlay application process, when + * you want all the phandles in the overlay to point to the actual + * base dt nodes. + * + * returns: + * 0 on success + * Negative error code on failure + */ +static int overlay_fixup_one_phandle(void *fdt, void *fdto, + int symbols_off, + const char *path, uint32_t path_len, + const char *name, uint32_t name_len, + int poffset, const char *label) +{ + const char *symbol_path; + uint32_t phandle; + fdt32_t phandle_prop; + int symbol_off, fixup_off; + int prop_len; + + if (symbols_off < 0) + return symbols_off; + + symbol_path = fdt_getprop(fdt, symbols_off, label, + &prop_len); + if (!symbol_path) + return prop_len; + + symbol_off = fdt_path_offset(fdt, symbol_path); + if (symbol_off < 0) + return symbol_off; + + phandle = fdt_get_phandle(fdt, symbol_off); + if (!phandle) + return -FDT_ERR_NOTFOUND; + + fixup_off = fdt_path_offset_namelen(fdto, path, path_len); + if (fixup_off == -FDT_ERR_NOTFOUND) + return -FDT_ERR_BADOVERLAY; + if (fixup_off < 0) + return fixup_off; + + phandle_prop = cpu_to_fdt32(phandle); + return fdt_setprop_inplace_namelen_partial(fdto, fixup_off, + name, name_len, poffset, + &phandle_prop, + sizeof(phandle_prop)); +}; + +/** + * overlay_fixup_phandle - Set an overlay phandle to the base one + * @fdt: Base Device Tree blob + * @fdto: Device tree overlay blob + * @symbols_off: Node offset of the symbols node in the base device tree + * @property: Property offset in the overlay holding the list of fixups + * + * overlay_fixup_phandle() resolves all the overlay phandles pointed + * to in a __fixups__ property, and updates them to match the phandles + * in use in the base device tree. + * + * This is part of the device tree overlay application process, when + * you want all the phandles in the overlay to point to the actual + * base dt nodes. + * + * returns: + * 0 on success + * Negative error code on failure + */ +static int overlay_fixup_phandle(void *fdt, void *fdto, int symbols_off, + int property) +{ + const char *value; + const char *label; + int len; + + value = fdt_getprop_by_offset(fdto, property, + &label, &len); + if (!value) { + if (len == -FDT_ERR_NOTFOUND) + return -FDT_ERR_INTERNAL; + + return len; + } + + do { + const char *path, *name, *fixup_end; + const char *fixup_str = value; + uint32_t path_len, name_len; + uint32_t fixup_len; + char *sep, *endptr; + int poffset, ret; + + fixup_end = memchr(value, '\0', len); + if (!fixup_end) + return -FDT_ERR_BADOVERLAY; + fixup_len = fixup_end - fixup_str; + + len -= fixup_len + 1; + value += fixup_len + 1; + + path = fixup_str; + sep = memchr(fixup_str, ':', fixup_len); + if (!sep || *sep != ':') + return -FDT_ERR_BADOVERLAY; + + path_len = sep - path; + if (path_len == (fixup_len - 1)) + return -FDT_ERR_BADOVERLAY; + + fixup_len -= path_len + 1; + name = sep + 1; + sep = memchr(name, ':', fixup_len); + if (!sep || *sep != ':') + return -FDT_ERR_BADOVERLAY; + + name_len = sep - name; + if (!name_len) + return -FDT_ERR_BADOVERLAY; + + poffset = strtoul(sep + 1, &endptr, 10); + if ((*endptr != '\0') || (endptr <= (sep + 1))) + return -FDT_ERR_BADOVERLAY; + + ret = overlay_fixup_one_phandle(fdt, fdto, symbols_off, + path, path_len, name, name_len, + poffset, label); + if (ret) + return ret; + } while (len > 0); + + return 0; +} + +/** + * overlay_fixup_phandles - Resolve the overlay phandles to the base + * device tree + * @fdt: Base Device Tree blob + * @fdto: Device tree overlay blob + * + * overlay_fixup_phandles() resolves all the overlay phandles pointing + * to nodes in the base device tree. + * + * This is one of the steps of the device tree overlay application + * process, when you want all the phandles in the overlay to point to + * the actual base dt nodes. + * + * returns: + * 0 on success + * Negative error code on failure + */ +static int overlay_fixup_phandles(void *fdt, void *fdto) +{ + int fixups_off, symbols_off; + int property; + + /* We can have overlays without any fixups */ + fixups_off = fdt_path_offset(fdto, "/__fixups__"); + if (fixups_off == -FDT_ERR_NOTFOUND) + return 0; /* nothing to do */ + if (fixups_off < 0) + return fixups_off; + + /* And base DTs without symbols */ + symbols_off = fdt_path_offset(fdt, "/__symbols__"); + if ((symbols_off < 0 && (symbols_off != -FDT_ERR_NOTFOUND))) + return symbols_off; + + fdt_for_each_property_offset(property, fdto, fixups_off) { + int ret; + + ret = overlay_fixup_phandle(fdt, fdto, symbols_off, property); + if (ret) + return ret; + } + + return 0; +} + +/** + * overlay_apply_node - Merges a node into the base device tree + * @fdt: Base Device Tree blob + * @target: Node offset in the base device tree to apply the fragment to + * @fdto: Device tree overlay blob + * @node: Node offset in the overlay holding the changes to merge + * + * overlay_apply_node() merges a node into a target base device tree + * node pointed. + * + * This is part of the final step in the device tree overlay + * application process, when all the phandles have been adjusted and + * resolved and you just have to merge overlay into the base device + * tree. + * + * returns: + * 0 on success + * Negative error code on failure + */ +static int overlay_apply_node(void *fdt, int target, + void *fdto, int node) +{ + int property; + int subnode; + + fdt_for_each_property_offset(property, fdto, node) { + const char *name; + const void *prop; + int prop_len; + int ret; + + prop = fdt_getprop_by_offset(fdto, property, &name, + &prop_len); + if (prop_len == -FDT_ERR_NOTFOUND) + return -FDT_ERR_INTERNAL; + if (prop_len < 0) + return prop_len; + + ret = fdt_setprop(fdt, target, name, prop, prop_len); + if (ret) + return ret; + } + + fdt_for_each_subnode(subnode, fdto, node) { + const char *name = fdt_get_name(fdto, subnode, NULL); + int nnode; + int ret; + + nnode = fdt_add_subnode(fdt, target, name); + if (nnode == -FDT_ERR_EXISTS) { + nnode = fdt_subnode_offset(fdt, target, name); + if (nnode == -FDT_ERR_NOTFOUND) + return -FDT_ERR_INTERNAL; + } + + if (nnode < 0) + return nnode; + + ret = overlay_apply_node(fdt, nnode, fdto, subnode); + if (ret) + return ret; + } + + return 0; +} + +/** + * overlay_merge - Merge an overlay into its base device tree + * @fdt: Base Device Tree blob + * @fdto: Device tree overlay blob + * + * overlay_merge() merges an overlay into its base device tree. + * + * This is the next to last step in the device tree overlay application + * process, when all the phandles have been adjusted and resolved and + * you just have to merge overlay into the base device tree. + * + * returns: + * 0 on success + * Negative error code on failure + */ +static int overlay_merge(void *fdt, void *fdto) +{ + int fragment; + + fdt_for_each_subnode(fragment, fdto, 0) { + int overlay; + int target; + int ret; + + /* + * Each fragments will have an __overlay__ node. If + * they don't, it's not supposed to be merged + */ + overlay = fdt_subnode_offset(fdto, fragment, "__overlay__"); + if (overlay == -FDT_ERR_NOTFOUND) + continue; + + if (overlay < 0) + return overlay; + + target = overlay_get_target(fdt, fdto, fragment, NULL); + if (target < 0) + return target; + + ret = overlay_apply_node(fdt, target, fdto, overlay); + if (ret) + return ret; + } + + return 0; +} + +static int get_path_len(const void *fdt, int nodeoffset) +{ + int len = 0, namelen; + const char *name; + + FDT_RO_PROBE(fdt); + + for (;;) { + name = fdt_get_name(fdt, nodeoffset, &namelen); + if (!name) + return namelen; + + /* root? we're done */ + if (namelen == 0) + break; + + nodeoffset = fdt_parent_offset(fdt, nodeoffset); + if (nodeoffset < 0) + return nodeoffset; + len += namelen + 1; + } + + /* in case of root pretend it's "/" */ + if (len == 0) + len++; + return len; +} + +/** + * overlay_symbol_update - Update the symbols of base tree after a merge + * @fdt: Base Device Tree blob + * @fdto: Device tree overlay blob + * + * overlay_symbol_update() updates the symbols of the base tree with the + * symbols of the applied overlay + * + * This is the last step in the device tree overlay application + * process, allowing the reference of overlay symbols by subsequent + * overlay operations. + * + * returns: + * 0 on success + * Negative error code on failure + */ +static int overlay_symbol_update(void *fdt, void *fdto) +{ + int root_sym, ov_sym, prop, path_len, fragment, target; + int len, frag_name_len, ret, rel_path_len; + const char *s, *e; + const char *path; + const char *name; + const char *frag_name; + const char *rel_path; + const char *target_path; + char *buf; + void *p; + + ov_sym = fdt_subnode_offset(fdto, 0, "__symbols__"); + + /* if no overlay symbols exist no problem */ + if (ov_sym < 0) + return 0; + + root_sym = fdt_subnode_offset(fdt, 0, "__symbols__"); + + /* it no root symbols exist we should create them */ + if (root_sym == -FDT_ERR_NOTFOUND) + root_sym = fdt_add_subnode(fdt, 0, "__symbols__"); + + /* any error is fatal now */ + if (root_sym < 0) + return root_sym; + + /* iterate over each overlay symbol */ + fdt_for_each_property_offset(prop, fdto, ov_sym) { + path = fdt_getprop_by_offset(fdto, prop, &name, &path_len); + if (!path) + return path_len; + + /* verify it's a string property (terminated by a single \0) */ + if (path_len < 1 || memchr(path, '\0', path_len) != &path[path_len - 1]) + return -FDT_ERR_BADVALUE; + + /* keep end marker to avoid strlen() */ + e = path + path_len; + + if (*path != '/') + return -FDT_ERR_BADVALUE; + + /* get fragment name first */ + s = strchr(path + 1, '/'); + if (!s) { + /* Symbol refers to something that won't end + * up in the target tree */ + continue; + } + + frag_name = path + 1; + frag_name_len = s - path - 1; + + /* verify format; safe since "s" lies in \0 terminated prop */ + len = sizeof("/__overlay__/") - 1; + if ((e - s) > len && (memcmp(s, "/__overlay__/", len) == 0)) { + /* /<fragment-name>/__overlay__/<relative-subnode-path> */ + rel_path = s + len; + rel_path_len = e - rel_path - 1; + } else if ((e - s) == len + && (memcmp(s, "/__overlay__", len - 1) == 0)) { + /* /<fragment-name>/__overlay__ */ + rel_path = ""; + rel_path_len = 0; + } else { + /* Symbol refers to something that won't end + * up in the target tree */ + continue; + } + + /* find the fragment index in which the symbol lies */ + ret = fdt_subnode_offset_namelen(fdto, 0, frag_name, + frag_name_len); + /* not found? */ + if (ret < 0) + return -FDT_ERR_BADOVERLAY; + fragment = ret; + + /* an __overlay__ subnode must exist */ + ret = fdt_subnode_offset(fdto, fragment, "__overlay__"); + if (ret < 0) + return -FDT_ERR_BADOVERLAY; + + /* get the target of the fragment */ + ret = overlay_get_target(fdt, fdto, fragment, &target_path); + if (ret < 0) + return ret; + target = ret; + + /* if we have a target path use */ + if (!target_path) { + ret = get_path_len(fdt, target); + if (ret < 0) + return ret; + len = ret; + } else { + len = strlen(target_path); + } + + ret = fdt_setprop_placeholder(fdt, root_sym, name, + len + (len > 1) + rel_path_len + 1, &p); + if (ret < 0) + return ret; + + if (!target_path) { + /* again in case setprop_placeholder changed it */ + ret = overlay_get_target(fdt, fdto, fragment, &target_path); + if (ret < 0) + return ret; + target = ret; + } + + buf = p; + if (len > 1) { /* target is not root */ + if (!target_path) { + ret = fdt_get_path(fdt, target, buf, len + 1); + if (ret < 0) + return ret; + } else + memcpy(buf, target_path, len + 1); + + } else + len--; + + buf[len] = '/'; + memcpy(buf + len + 1, rel_path, rel_path_len); + buf[len + 1 + rel_path_len] = '\0'; + } + + return 0; +} + +int fdt_overlay_apply(void *fdt, void *fdto) +{ + uint32_t delta; + int ret; + + FDT_RO_PROBE(fdt); + FDT_RO_PROBE(fdto); + + ret = fdt_find_max_phandle(fdt, &delta); + if (ret) + goto err; + + ret = overlay_adjust_local_phandles(fdto, delta); + if (ret) + goto err; + + ret = overlay_update_local_references(fdto, delta); + if (ret) + goto err; + + ret = overlay_fixup_phandles(fdt, fdto); + if (ret) + goto err; + + ret = overlay_merge(fdt, fdto); + if (ret) + goto err; + + ret = overlay_symbol_update(fdt, fdto); + if (ret) + goto err; + + /* + * The overlay has been damaged, erase its magic. + */ + fdt_set_magic(fdto, ~0); + + return 0; + +err: + /* + * The overlay might have been damaged, erase its magic. + */ + fdt_set_magic(fdto, ~0); + + /* + * The base device tree might have been damaged, erase its + * magic. + */ + fdt_set_magic(fdt, ~0); + + return ret; +} diff --git a/src/net/scripts/dtc/libfdt/fdt_ro.c b/src/net/scripts/dtc/libfdt/fdt_ro.c new file mode 100644 index 0000000..91cc6fe --- /dev/null +++ b/src/net/scripts/dtc/libfdt/fdt_ro.c @@ -0,0 +1,859 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * libfdt - Flat Device Tree manipulation + * Copyright (C) 2006 David Gibson, IBM Corporation. + */ +#include "libfdt_env.h" + +#include <fdt.h> +#include <libfdt.h> + +#include "libfdt_internal.h" + +static int fdt_nodename_eq_(const void *fdt, int offset, + const char *s, int len) +{ + int olen; + const char *p = fdt_get_name(fdt, offset, &olen); + + if (!p || olen < len) + /* short match */ + return 0; + + if (memcmp(p, s, len) != 0) + return 0; + + if (p[len] == '\0') + return 1; + else if (!memchr(s, '@', len) && (p[len] == '@')) + return 1; + else + return 0; +} + +const char *fdt_get_string(const void *fdt, int stroffset, int *lenp) +{ + int32_t totalsize; + uint32_t absoffset; + size_t len; + int err; + const char *s, *n; + + if (can_assume(VALID_INPUT)) { + s = (const char *)fdt + fdt_off_dt_strings(fdt) + stroffset; + + if (lenp) + *lenp = strlen(s); + return s; + } + totalsize = fdt_ro_probe_(fdt); + err = totalsize; + if (totalsize < 0) + goto fail; + + err = -FDT_ERR_BADOFFSET; + absoffset = stroffset + fdt_off_dt_strings(fdt); + if (absoffset >= (unsigned)totalsize) + goto fail; + len = totalsize - absoffset; + + if (fdt_magic(fdt) == FDT_MAGIC) { + if (stroffset < 0) + goto fail; + if (can_assume(LATEST) || fdt_version(fdt) >= 17) { + if ((unsigned)stroffset >= fdt_size_dt_strings(fdt)) + goto fail; + if ((fdt_size_dt_strings(fdt) - stroffset) < len) + len = fdt_size_dt_strings(fdt) - stroffset; + } + } else if (fdt_magic(fdt) == FDT_SW_MAGIC) { + unsigned int sw_stroffset = -stroffset; + + if ((stroffset >= 0) || + (sw_stroffset > fdt_size_dt_strings(fdt))) + goto fail; + if (sw_stroffset < len) + len = sw_stroffset; + } else { + err = -FDT_ERR_INTERNAL; + goto fail; + } + + s = (const char *)fdt + absoffset; + n = memchr(s, '\0', len); + if (!n) { + /* missing terminating NULL */ + err = -FDT_ERR_TRUNCATED; + goto fail; + } + + if (lenp) + *lenp = n - s; + return s; + +fail: + if (lenp) + *lenp = err; + return NULL; +} + +const char *fdt_string(const void *fdt, int stroffset) +{ + return fdt_get_string(fdt, stroffset, NULL); +} + +static int fdt_string_eq_(const void *fdt, int stroffset, + const char *s, int len) +{ + int slen; + const char *p = fdt_get_string(fdt, stroffset, &slen); + + return p && (slen == len) && (memcmp(p, s, len) == 0); +} + +int fdt_find_max_phandle(const void *fdt, uint32_t *phandle) +{ + uint32_t max = 0; + int offset = -1; + + while (true) { + uint32_t value; + + offset = fdt_next_node(fdt, offset, NULL); + if (offset < 0) { + if (offset == -FDT_ERR_NOTFOUND) + break; + + return offset; + } + + value = fdt_get_phandle(fdt, offset); + + if (value > max) + max = value; + } + + if (phandle) + *phandle = max; + + return 0; +} + +int fdt_generate_phandle(const void *fdt, uint32_t *phandle) +{ + uint32_t max; + int err; + + err = fdt_find_max_phandle(fdt, &max); + if (err < 0) + return err; + + if (max == FDT_MAX_PHANDLE) + return -FDT_ERR_NOPHANDLES; + + if (phandle) + *phandle = max + 1; + + return 0; +} + +static const struct fdt_reserve_entry *fdt_mem_rsv(const void *fdt, int n) +{ + unsigned int offset = n * sizeof(struct fdt_reserve_entry); + unsigned int absoffset = fdt_off_mem_rsvmap(fdt) + offset; + + if (!can_assume(VALID_INPUT)) { + if (absoffset < fdt_off_mem_rsvmap(fdt)) + return NULL; + if (absoffset > fdt_totalsize(fdt) - + sizeof(struct fdt_reserve_entry)) + return NULL; + } + return fdt_mem_rsv_(fdt, n); +} + +int fdt_get_mem_rsv(const void *fdt, int n, uint64_t *address, uint64_t *size) +{ + const struct fdt_reserve_entry *re; + + FDT_RO_PROBE(fdt); + re = fdt_mem_rsv(fdt, n); + if (!can_assume(VALID_INPUT) && !re) + return -FDT_ERR_BADOFFSET; + + *address = fdt64_ld(&re->address); + *size = fdt64_ld(&re->size); + return 0; +} + +int fdt_num_mem_rsv(const void *fdt) +{ + int i; + const struct fdt_reserve_entry *re; + + for (i = 0; (re = fdt_mem_rsv(fdt, i)) != NULL; i++) { + if (fdt64_ld(&re->size) == 0) + return i; + } + return -FDT_ERR_TRUNCATED; +} + +static int nextprop_(const void *fdt, int offset) +{ + uint32_t tag; + int nextoffset; + + do { + tag = fdt_next_tag(fdt, offset, &nextoffset); + + switch (tag) { + case FDT_END: + if (nextoffset >= 0) + return -FDT_ERR_BADSTRUCTURE; + else + return nextoffset; + + case FDT_PROP: + return offset; + } + offset = nextoffset; + } while (tag == FDT_NOP); + + return -FDT_ERR_NOTFOUND; +} + +int fdt_subnode_offset_namelen(const void *fdt, int offset, + const char *name, int namelen) +{ + int depth; + + FDT_RO_PROBE(fdt); + + for (depth = 0; + (offset >= 0) && (depth >= 0); + offset = fdt_next_node(fdt, offset, &depth)) + if ((depth == 1) + && fdt_nodename_eq_(fdt, offset, name, namelen)) + return offset; + + if (depth < 0) + return -FDT_ERR_NOTFOUND; + return offset; /* error */ +} + +int fdt_subnode_offset(const void *fdt, int parentoffset, + const char *name) +{ + return fdt_subnode_offset_namelen(fdt, parentoffset, name, strlen(name)); +} + +int fdt_path_offset_namelen(const void *fdt, const char *path, int namelen) +{ + const char *end = path + namelen; + const char *p = path; + int offset = 0; + + FDT_RO_PROBE(fdt); + + /* see if we have an alias */ + if (*path != '/') { + const char *q = memchr(path, '/', end - p); + + if (!q) + q = end; + + p = fdt_get_alias_namelen(fdt, p, q - p); + if (!p) + return -FDT_ERR_BADPATH; + offset = fdt_path_offset(fdt, p); + + p = q; + } + + while (p < end) { + const char *q; + + while (*p == '/') { + p++; + if (p == end) + return offset; + } + q = memchr(p, '/', end - p); + if (! q) + q = end; + + offset = fdt_subnode_offset_namelen(fdt, offset, p, q-p); + if (offset < 0) + return offset; + + p = q; + } + + return offset; +} + +int fdt_path_offset(const void *fdt, const char *path) +{ + return fdt_path_offset_namelen(fdt, path, strlen(path)); +} + +const char *fdt_get_name(const void *fdt, int nodeoffset, int *len) +{ + const struct fdt_node_header *nh = fdt_offset_ptr_(fdt, nodeoffset); + const char *nameptr; + int err; + + if (((err = fdt_ro_probe_(fdt)) < 0) + || ((err = fdt_check_node_offset_(fdt, nodeoffset)) < 0)) + goto fail; + + nameptr = nh->name; + + if (!can_assume(LATEST) && fdt_version(fdt) < 0x10) { + /* + * For old FDT versions, match the naming conventions of V16: + * give only the leaf name (after all /). The actual tree + * contents are loosely checked. + */ + const char *leaf; + leaf = strrchr(nameptr, '/'); + if (leaf == NULL) { + err = -FDT_ERR_BADSTRUCTURE; + goto fail; + } + nameptr = leaf+1; + } + + if (len) + *len = strlen(nameptr); + + return nameptr; + + fail: + if (len) + *len = err; + return NULL; +} + +int fdt_first_property_offset(const void *fdt, int nodeoffset) +{ + int offset; + + if ((offset = fdt_check_node_offset_(fdt, nodeoffset)) < 0) + return offset; + + return nextprop_(fdt, offset); +} + +int fdt_next_property_offset(const void *fdt, int offset) +{ + if ((offset = fdt_check_prop_offset_(fdt, offset)) < 0) + return offset; + + return nextprop_(fdt, offset); +} + +static const struct fdt_property *fdt_get_property_by_offset_(const void *fdt, + int offset, + int *lenp) +{ + int err; + const struct fdt_property *prop; + + if (!can_assume(VALID_INPUT) && + (err = fdt_check_prop_offset_(fdt, offset)) < 0) { + if (lenp) + *lenp = err; + return NULL; + } + + prop = fdt_offset_ptr_(fdt, offset); + + if (lenp) + *lenp = fdt32_ld(&prop->len); + + return prop; +} + +const struct fdt_property *fdt_get_property_by_offset(const void *fdt, + int offset, + int *lenp) +{ + /* Prior to version 16, properties may need realignment + * and this API does not work. fdt_getprop_*() will, however. */ + + if (!can_assume(LATEST) && fdt_version(fdt) < 0x10) { + if (lenp) + *lenp = -FDT_ERR_BADVERSION; + return NULL; + } + + return fdt_get_property_by_offset_(fdt, offset, lenp); +} + +static const struct fdt_property *fdt_get_property_namelen_(const void *fdt, + int offset, + const char *name, + int namelen, + int *lenp, + int *poffset) +{ + for (offset = fdt_first_property_offset(fdt, offset); + (offset >= 0); + (offset = fdt_next_property_offset(fdt, offset))) { + const struct fdt_property *prop; + + prop = fdt_get_property_by_offset_(fdt, offset, lenp); + if (!can_assume(LIBFDT_FLAWLESS) && !prop) { + offset = -FDT_ERR_INTERNAL; + break; + } + if (fdt_string_eq_(fdt, fdt32_ld(&prop->nameoff), + name, namelen)) { + if (poffset) + *poffset = offset; + return prop; + } + } + + if (lenp) + *lenp = offset; + return NULL; +} + + +const struct fdt_property *fdt_get_property_namelen(const void *fdt, + int offset, + const char *name, + int namelen, int *lenp) +{ + /* Prior to version 16, properties may need realignment + * and this API does not work. fdt_getprop_*() will, however. */ + if (!can_assume(LATEST) && fdt_version(fdt) < 0x10) { + if (lenp) + *lenp = -FDT_ERR_BADVERSION; + return NULL; + } + + return fdt_get_property_namelen_(fdt, offset, name, namelen, lenp, + NULL); +} + + +const struct fdt_property *fdt_get_property(const void *fdt, + int nodeoffset, + const char *name, int *lenp) +{ + return fdt_get_property_namelen(fdt, nodeoffset, name, + strlen(name), lenp); +} + +const void *fdt_getprop_namelen(const void *fdt, int nodeoffset, + const char *name, int namelen, int *lenp) +{ + int poffset; + const struct fdt_property *prop; + + prop = fdt_get_property_namelen_(fdt, nodeoffset, name, namelen, lenp, + &poffset); + if (!prop) + return NULL; + + /* Handle realignment */ + if (!can_assume(LATEST) && fdt_version(fdt) < 0x10 && + (poffset + sizeof(*prop)) % 8 && fdt32_ld(&prop->len) >= 8) + return prop->data + 4; + return prop->data; +} + +const void *fdt_getprop_by_offset(const void *fdt, int offset, + const char **namep, int *lenp) +{ + const struct fdt_property *prop; + + prop = fdt_get_property_by_offset_(fdt, offset, lenp); + if (!prop) + return NULL; + if (namep) { + const char *name; + int namelen; + + if (!can_assume(VALID_INPUT)) { + name = fdt_get_string(fdt, fdt32_ld(&prop->nameoff), + &namelen); + if (!name) { + if (lenp) + *lenp = namelen; + return NULL; + } + *namep = name; + } else { + *namep = fdt_string(fdt, fdt32_ld(&prop->nameoff)); + } + } + + /* Handle realignment */ + if (!can_assume(LATEST) && fdt_version(fdt) < 0x10 && + (offset + sizeof(*prop)) % 8 && fdt32_ld(&prop->len) >= 8) + return prop->data + 4; + return prop->data; +} + +const void *fdt_getprop(const void *fdt, int nodeoffset, + const char *name, int *lenp) +{ + return fdt_getprop_namelen(fdt, nodeoffset, name, strlen(name), lenp); +} + +uint32_t fdt_get_phandle(const void *fdt, int nodeoffset) +{ + const fdt32_t *php; + int len; + + /* FIXME: This is a bit sub-optimal, since we potentially scan + * over all the properties twice. */ + php = fdt_getprop(fdt, nodeoffset, "phandle", &len); + if (!php || (len != sizeof(*php))) { + php = fdt_getprop(fdt, nodeoffset, "linux,phandle", &len); + if (!php || (len != sizeof(*php))) + return 0; + } + + return fdt32_ld(php); +} + +const char *fdt_get_alias_namelen(const void *fdt, + const char *name, int namelen) +{ + int aliasoffset; + + aliasoffset = fdt_path_offset(fdt, "/aliases"); + if (aliasoffset < 0) + return NULL; + + return fdt_getprop_namelen(fdt, aliasoffset, name, namelen, NULL); +} + +const char *fdt_get_alias(const void *fdt, const char *name) +{ + return fdt_get_alias_namelen(fdt, name, strlen(name)); +} + +int fdt_get_path(const void *fdt, int nodeoffset, char *buf, int buflen) +{ + int pdepth = 0, p = 0; + int offset, depth, namelen; + const char *name; + + FDT_RO_PROBE(fdt); + + if (buflen < 2) + return -FDT_ERR_NOSPACE; + + for (offset = 0, depth = 0; + (offset >= 0) && (offset <= nodeoffset); + offset = fdt_next_node(fdt, offset, &depth)) { + while (pdepth > depth) { + do { + p--; + } while (buf[p-1] != '/'); + pdepth--; + } + + if (pdepth >= depth) { + name = fdt_get_name(fdt, offset, &namelen); + if (!name) + return namelen; + if ((p + namelen + 1) <= buflen) { + memcpy(buf + p, name, namelen); + p += namelen; + buf[p++] = '/'; + pdepth++; + } + } + + if (offset == nodeoffset) { + if (pdepth < (depth + 1)) + return -FDT_ERR_NOSPACE; + + if (p > 1) /* special case so that root path is "/", not "" */ + p--; + buf[p] = '\0'; + return 0; + } + } + + if ((offset == -FDT_ERR_NOTFOUND) || (offset >= 0)) + return -FDT_ERR_BADOFFSET; + else if (offset == -FDT_ERR_BADOFFSET) + return -FDT_ERR_BADSTRUCTURE; + + return offset; /* error from fdt_next_node() */ +} + +int fdt_supernode_atdepth_offset(const void *fdt, int nodeoffset, + int supernodedepth, int *nodedepth) +{ + int offset, depth; + int supernodeoffset = -FDT_ERR_INTERNAL; + + FDT_RO_PROBE(fdt); + + if (supernodedepth < 0) + return -FDT_ERR_NOTFOUND; + + for (offset = 0, depth = 0; + (offset >= 0) && (offset <= nodeoffset); + offset = fdt_next_node(fdt, offset, &depth)) { + if (depth == supernodedepth) + supernodeoffset = offset; + + if (offset == nodeoffset) { + if (nodedepth) + *nodedepth = depth; + + if (supernodedepth > depth) + return -FDT_ERR_NOTFOUND; + else + return supernodeoffset; + } + } + + if (!can_assume(VALID_INPUT)) { + if ((offset == -FDT_ERR_NOTFOUND) || (offset >= 0)) + return -FDT_ERR_BADOFFSET; + else if (offset == -FDT_ERR_BADOFFSET) + return -FDT_ERR_BADSTRUCTURE; + } + + return offset; /* error from fdt_next_node() */ +} + +int fdt_node_depth(const void *fdt, int nodeoffset) +{ + int nodedepth; + int err; + + err = fdt_supernode_atdepth_offset(fdt, nodeoffset, 0, &nodedepth); + if (err) + return (can_assume(LIBFDT_FLAWLESS) || err < 0) ? err : + -FDT_ERR_INTERNAL; + return nodedepth; +} + +int fdt_parent_offset(const void *fdt, int nodeoffset) +{ + int nodedepth = fdt_node_depth(fdt, nodeoffset); + + if (nodedepth < 0) + return nodedepth; + return fdt_supernode_atdepth_offset(fdt, nodeoffset, + nodedepth - 1, NULL); +} + +int fdt_node_offset_by_prop_value(const void *fdt, int startoffset, + const char *propname, + const void *propval, int proplen) +{ + int offset; + const void *val; + int len; + + FDT_RO_PROBE(fdt); + + /* FIXME: The algorithm here is pretty horrible: we scan each + * property of a node in fdt_getprop(), then if that didn't + * find what we want, we scan over them again making our way + * to the next node. Still it's the easiest to implement + * approach; performance can come later. */ + for (offset = fdt_next_node(fdt, startoffset, NULL); + offset >= 0; + offset = fdt_next_node(fdt, offset, NULL)) { + val = fdt_getprop(fdt, offset, propname, &len); + if (val && (len == proplen) + && (memcmp(val, propval, len) == 0)) + return offset; + } + + return offset; /* error from fdt_next_node() */ +} + +int fdt_node_offset_by_phandle(const void *fdt, uint32_t phandle) +{ + int offset; + + if ((phandle == 0) || (phandle == ~0U)) + return -FDT_ERR_BADPHANDLE; + + FDT_RO_PROBE(fdt); + + /* FIXME: The algorithm here is pretty horrible: we + * potentially scan each property of a node in + * fdt_get_phandle(), then if that didn't find what + * we want, we scan over them again making our way to the next + * node. Still it's the easiest to implement approach; + * performance can come later. */ + for (offset = fdt_next_node(fdt, -1, NULL); + offset >= 0; + offset = fdt_next_node(fdt, offset, NULL)) { + if (fdt_get_phandle(fdt, offset) == phandle) + return offset; + } + + return offset; /* error from fdt_next_node() */ +} + +int fdt_stringlist_contains(const char *strlist, int listlen, const char *str) +{ + int len = strlen(str); + const char *p; + + while (listlen >= len) { + if (memcmp(str, strlist, len+1) == 0) + return 1; + p = memchr(strlist, '\0', listlen); + if (!p) + return 0; /* malformed strlist.. */ + listlen -= (p-strlist) + 1; + strlist = p + 1; + } + return 0; +} + +int fdt_stringlist_count(const void *fdt, int nodeoffset, const char *property) +{ + const char *list, *end; + int length, count = 0; + + list = fdt_getprop(fdt, nodeoffset, property, &length); + if (!list) + return length; + + end = list + length; + + while (list < end) { + length = strnlen(list, end - list) + 1; + + /* Abort if the last string isn't properly NUL-terminated. */ + if (list + length > end) + return -FDT_ERR_BADVALUE; + + list += length; + count++; + } + + return count; +} + +int fdt_stringlist_search(const void *fdt, int nodeoffset, const char *property, + const char *string) +{ + int length, len, idx = 0; + const char *list, *end; + + list = fdt_getprop(fdt, nodeoffset, property, &length); + if (!list) + return length; + + len = strlen(string) + 1; + end = list + length; + + while (list < end) { + length = strnlen(list, end - list) + 1; + + /* Abort if the last string isn't properly NUL-terminated. */ + if (list + length > end) + return -FDT_ERR_BADVALUE; + + if (length == len && memcmp(list, string, length) == 0) + return idx; + + list += length; + idx++; + } + + return -FDT_ERR_NOTFOUND; +} + +const char *fdt_stringlist_get(const void *fdt, int nodeoffset, + const char *property, int idx, + int *lenp) +{ + const char *list, *end; + int length; + + list = fdt_getprop(fdt, nodeoffset, property, &length); + if (!list) { + if (lenp) + *lenp = length; + + return NULL; + } + + end = list + length; + + while (list < end) { + length = strnlen(list, end - list) + 1; + + /* Abort if the last string isn't properly NUL-terminated. */ + if (list + length > end) { + if (lenp) + *lenp = -FDT_ERR_BADVALUE; + + return NULL; + } + + if (idx == 0) { + if (lenp) + *lenp = length - 1; + + return list; + } + + list += length; + idx--; + } + + if (lenp) + *lenp = -FDT_ERR_NOTFOUND; + + return NULL; +} + +int fdt_node_check_compatible(const void *fdt, int nodeoffset, + const char *compatible) +{ + const void *prop; + int len; + + prop = fdt_getprop(fdt, nodeoffset, "compatible", &len); + if (!prop) + return len; + + return !fdt_stringlist_contains(prop, len, compatible); +} + +int fdt_node_offset_by_compatible(const void *fdt, int startoffset, + const char *compatible) +{ + int offset, err; + + FDT_RO_PROBE(fdt); + + /* FIXME: The algorithm here is pretty horrible: we scan each + * property of a node in fdt_node_check_compatible(), then if + * that didn't find what we want, we scan over them again + * making our way to the next node. Still it's the easiest to + * implement approach; performance can come later. */ + for (offset = fdt_next_node(fdt, startoffset, NULL); + offset >= 0; + offset = fdt_next_node(fdt, offset, NULL)) { + err = fdt_node_check_compatible(fdt, offset, compatible); + if ((err < 0) && (err != -FDT_ERR_NOTFOUND)) + return err; + else if (err == 0) + return offset; + } + + return offset; /* error from fdt_next_node() */ +} diff --git a/src/net/scripts/dtc/libfdt/fdt_rw.c b/src/net/scripts/dtc/libfdt/fdt_rw.c new file mode 100644 index 0000000..68887b9 --- /dev/null +++ b/src/net/scripts/dtc/libfdt/fdt_rw.c @@ -0,0 +1,492 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * libfdt - Flat Device Tree manipulation + * Copyright (C) 2006 David Gibson, IBM Corporation. + */ +#include "libfdt_env.h" + +#include <fdt.h> +#include <libfdt.h> + +#include "libfdt_internal.h" + +static int fdt_blocks_misordered_(const void *fdt, + int mem_rsv_size, int struct_size) +{ + return (fdt_off_mem_rsvmap(fdt) < FDT_ALIGN(sizeof(struct fdt_header), 8)) + || (fdt_off_dt_struct(fdt) < + (fdt_off_mem_rsvmap(fdt) + mem_rsv_size)) + || (fdt_off_dt_strings(fdt) < + (fdt_off_dt_struct(fdt) + struct_size)) + || (fdt_totalsize(fdt) < + (fdt_off_dt_strings(fdt) + fdt_size_dt_strings(fdt))); +} + +static int fdt_rw_probe_(void *fdt) +{ + if (can_assume(VALID_DTB)) + return 0; + FDT_RO_PROBE(fdt); + + if (!can_assume(LATEST) && fdt_version(fdt) < 17) + return -FDT_ERR_BADVERSION; + if (fdt_blocks_misordered_(fdt, sizeof(struct fdt_reserve_entry), + fdt_size_dt_struct(fdt))) + return -FDT_ERR_BADLAYOUT; + if (!can_assume(LATEST) && fdt_version(fdt) > 17) + fdt_set_version(fdt, 17); + + return 0; +} + +#define FDT_RW_PROBE(fdt) \ + { \ + int err_; \ + if ((err_ = fdt_rw_probe_(fdt)) != 0) \ + return err_; \ + } + +static inline unsigned int fdt_data_size_(void *fdt) +{ + return fdt_off_dt_strings(fdt) + fdt_size_dt_strings(fdt); +} + +static int fdt_splice_(void *fdt, void *splicepoint, int oldlen, int newlen) +{ + char *p = splicepoint; + unsigned int dsize = fdt_data_size_(fdt); + size_t soff = p - (char *)fdt; + + if ((oldlen < 0) || (soff + oldlen < soff) || (soff + oldlen > dsize)) + return -FDT_ERR_BADOFFSET; + if ((p < (char *)fdt) || (dsize + newlen < (unsigned)oldlen)) + return -FDT_ERR_BADOFFSET; + if (dsize - oldlen + newlen > fdt_totalsize(fdt)) + return -FDT_ERR_NOSPACE; + memmove(p + newlen, p + oldlen, ((char *)fdt + dsize) - (p + oldlen)); + return 0; +} + +static int fdt_splice_mem_rsv_(void *fdt, struct fdt_reserve_entry *p, + int oldn, int newn) +{ + int delta = (newn - oldn) * sizeof(*p); + int err; + err = fdt_splice_(fdt, p, oldn * sizeof(*p), newn * sizeof(*p)); + if (err) + return err; + fdt_set_off_dt_struct(fdt, fdt_off_dt_struct(fdt) + delta); + fdt_set_off_dt_strings(fdt, fdt_off_dt_strings(fdt) + delta); + return 0; +} + +static int fdt_splice_struct_(void *fdt, void *p, + int oldlen, int newlen) +{ + int delta = newlen - oldlen; + int err; + + if ((err = fdt_splice_(fdt, p, oldlen, newlen))) + return err; + + fdt_set_size_dt_struct(fdt, fdt_size_dt_struct(fdt) + delta); + fdt_set_off_dt_strings(fdt, fdt_off_dt_strings(fdt) + delta); + return 0; +} + +/* Must only be used to roll back in case of error */ +static void fdt_del_last_string_(void *fdt, const char *s) +{ + int newlen = strlen(s) + 1; + + fdt_set_size_dt_strings(fdt, fdt_size_dt_strings(fdt) - newlen); +} + +static int fdt_splice_string_(void *fdt, int newlen) +{ + void *p = (char *)fdt + + fdt_off_dt_strings(fdt) + fdt_size_dt_strings(fdt); + int err; + + if ((err = fdt_splice_(fdt, p, 0, newlen))) + return err; + + fdt_set_size_dt_strings(fdt, fdt_size_dt_strings(fdt) + newlen); + return 0; +} + +/** + * fdt_find_add_string_() - Find or allocate a string + * + * @fdt: pointer to the device tree to check/adjust + * @s: string to find/add + * @allocated: Set to 0 if the string was found, 1 if not found and so + * allocated. Ignored if can_assume(NO_ROLLBACK) + * @return offset of string in the string table (whether found or added) + */ +static int fdt_find_add_string_(void *fdt, const char *s, int *allocated) +{ + char *strtab = (char *)fdt + fdt_off_dt_strings(fdt); + const char *p; + char *new; + int len = strlen(s) + 1; + int err; + + if (!can_assume(NO_ROLLBACK)) + *allocated = 0; + + p = fdt_find_string_(strtab, fdt_size_dt_strings(fdt), s); + if (p) + /* found it */ + return (p - strtab); + + new = strtab + fdt_size_dt_strings(fdt); + err = fdt_splice_string_(fdt, len); + if (err) + return err; + + if (!can_assume(NO_ROLLBACK)) + *allocated = 1; + + memcpy(new, s, len); + return (new - strtab); +} + +int fdt_add_mem_rsv(void *fdt, uint64_t address, uint64_t size) +{ + struct fdt_reserve_entry *re; + int err; + + FDT_RW_PROBE(fdt); + + re = fdt_mem_rsv_w_(fdt, fdt_num_mem_rsv(fdt)); + err = fdt_splice_mem_rsv_(fdt, re, 0, 1); + if (err) + return err; + + re->address = cpu_to_fdt64(address); + re->size = cpu_to_fdt64(size); + return 0; +} + +int fdt_del_mem_rsv(void *fdt, int n) +{ + struct fdt_reserve_entry *re = fdt_mem_rsv_w_(fdt, n); + + FDT_RW_PROBE(fdt); + + if (n >= fdt_num_mem_rsv(fdt)) + return -FDT_ERR_NOTFOUND; + + return fdt_splice_mem_rsv_(fdt, re, 1, 0); +} + +static int fdt_resize_property_(void *fdt, int nodeoffset, const char *name, + int len, struct fdt_property **prop) +{ + int oldlen; + int err; + + *prop = fdt_get_property_w(fdt, nodeoffset, name, &oldlen); + if (!*prop) + return oldlen; + + if ((err = fdt_splice_struct_(fdt, (*prop)->data, FDT_TAGALIGN(oldlen), + FDT_TAGALIGN(len)))) + return err; + + (*prop)->len = cpu_to_fdt32(len); + return 0; +} + +static int fdt_add_property_(void *fdt, int nodeoffset, const char *name, + int len, struct fdt_property **prop) +{ + int proplen; + int nextoffset; + int namestroff; + int err; + int allocated; + + if ((nextoffset = fdt_check_node_offset_(fdt, nodeoffset)) < 0) + return nextoffset; + + namestroff = fdt_find_add_string_(fdt, name, &allocated); + if (namestroff < 0) + return namestroff; + + *prop = fdt_offset_ptr_w_(fdt, nextoffset); + proplen = sizeof(**prop) + FDT_TAGALIGN(len); + + err = fdt_splice_struct_(fdt, *prop, 0, proplen); + if (err) { + /* Delete the string if we failed to add it */ + if (!can_assume(NO_ROLLBACK) && allocated) + fdt_del_last_string_(fdt, name); + return err; + } + + (*prop)->tag = cpu_to_fdt32(FDT_PROP); + (*prop)->nameoff = cpu_to_fdt32(namestroff); + (*prop)->len = cpu_to_fdt32(len); + return 0; +} + +int fdt_set_name(void *fdt, int nodeoffset, const char *name) +{ + char *namep; + int oldlen, newlen; + int err; + + FDT_RW_PROBE(fdt); + + namep = (char *)(uintptr_t)fdt_get_name(fdt, nodeoffset, &oldlen); + if (!namep) + return oldlen; + + newlen = strlen(name); + + err = fdt_splice_struct_(fdt, namep, FDT_TAGALIGN(oldlen+1), + FDT_TAGALIGN(newlen+1)); + if (err) + return err; + + memcpy(namep, name, newlen+1); + return 0; +} + +int fdt_setprop_placeholder(void *fdt, int nodeoffset, const char *name, + int len, void **prop_data) +{ + struct fdt_property *prop; + int err; + + FDT_RW_PROBE(fdt); + + err = fdt_resize_property_(fdt, nodeoffset, name, len, &prop); + if (err == -FDT_ERR_NOTFOUND) + err = fdt_add_property_(fdt, nodeoffset, name, len, &prop); + if (err) + return err; + + *prop_data = prop->data; + return 0; +} + +int fdt_setprop(void *fdt, int nodeoffset, const char *name, + const void *val, int len) +{ + void *prop_data; + int err; + + err = fdt_setprop_placeholder(fdt, nodeoffset, name, len, &prop_data); + if (err) + return err; + + if (len) + memcpy(prop_data, val, len); + return 0; +} + +int fdt_appendprop(void *fdt, int nodeoffset, const char *name, + const void *val, int len) +{ + struct fdt_property *prop; + int err, oldlen, newlen; + + FDT_RW_PROBE(fdt); + + prop = fdt_get_property_w(fdt, nodeoffset, name, &oldlen); + if (prop) { + newlen = len + oldlen; + err = fdt_splice_struct_(fdt, prop->data, + FDT_TAGALIGN(oldlen), + FDT_TAGALIGN(newlen)); + if (err) + return err; + prop->len = cpu_to_fdt32(newlen); + memcpy(prop->data + oldlen, val, len); + } else { + err = fdt_add_property_(fdt, nodeoffset, name, len, &prop); + if (err) + return err; + memcpy(prop->data, val, len); + } + return 0; +} + +int fdt_delprop(void *fdt, int nodeoffset, const char *name) +{ + struct fdt_property *prop; + int len, proplen; + + FDT_RW_PROBE(fdt); + + prop = fdt_get_property_w(fdt, nodeoffset, name, &len); + if (!prop) + return len; + + proplen = sizeof(*prop) + FDT_TAGALIGN(len); + return fdt_splice_struct_(fdt, prop, proplen, 0); +} + +int fdt_add_subnode_namelen(void *fdt, int parentoffset, + const char *name, int namelen) +{ + struct fdt_node_header *nh; + int offset, nextoffset; + int nodelen; + int err; + uint32_t tag; + fdt32_t *endtag; + + FDT_RW_PROBE(fdt); + + offset = fdt_subnode_offset_namelen(fdt, parentoffset, name, namelen); + if (offset >= 0) + return -FDT_ERR_EXISTS; + else if (offset != -FDT_ERR_NOTFOUND) + return offset; + + /* Try to place the new node after the parent's properties */ + fdt_next_tag(fdt, parentoffset, &nextoffset); /* skip the BEGIN_NODE */ + do { + offset = nextoffset; + tag = fdt_next_tag(fdt, offset, &nextoffset); + } while ((tag == FDT_PROP) || (tag == FDT_NOP)); + + nh = fdt_offset_ptr_w_(fdt, offset); + nodelen = sizeof(*nh) + FDT_TAGALIGN(namelen+1) + FDT_TAGSIZE; + + err = fdt_splice_struct_(fdt, nh, 0, nodelen); + if (err) + return err; + + nh->tag = cpu_to_fdt32(FDT_BEGIN_NODE); + memset(nh->name, 0, FDT_TAGALIGN(namelen+1)); + memcpy(nh->name, name, namelen); + endtag = (fdt32_t *)((char *)nh + nodelen - FDT_TAGSIZE); + *endtag = cpu_to_fdt32(FDT_END_NODE); + + return offset; +} + +int fdt_add_subnode(void *fdt, int parentoffset, const char *name) +{ + return fdt_add_subnode_namelen(fdt, parentoffset, name, strlen(name)); +} + +int fdt_del_node(void *fdt, int nodeoffset) +{ + int endoffset; + + FDT_RW_PROBE(fdt); + + endoffset = fdt_node_end_offset_(fdt, nodeoffset); + if (endoffset < 0) + return endoffset; + + return fdt_splice_struct_(fdt, fdt_offset_ptr_w_(fdt, nodeoffset), + endoffset - nodeoffset, 0); +} + +static void fdt_packblocks_(const char *old, char *new, + int mem_rsv_size, int struct_size) +{ + int mem_rsv_off, struct_off, strings_off; + + mem_rsv_off = FDT_ALIGN(sizeof(struct fdt_header), 8); + struct_off = mem_rsv_off + mem_rsv_size; + strings_off = struct_off + struct_size; + + memmove(new + mem_rsv_off, old + fdt_off_mem_rsvmap(old), mem_rsv_size); + fdt_set_off_mem_rsvmap(new, mem_rsv_off); + + memmove(new + struct_off, old + fdt_off_dt_struct(old), struct_size); + fdt_set_off_dt_struct(new, struct_off); + fdt_set_size_dt_struct(new, struct_size); + + memmove(new + strings_off, old + fdt_off_dt_strings(old), + fdt_size_dt_strings(old)); + fdt_set_off_dt_strings(new, strings_off); + fdt_set_size_dt_strings(new, fdt_size_dt_strings(old)); +} + +int fdt_open_into(const void *fdt, void *buf, int bufsize) +{ + int err; + int mem_rsv_size, struct_size; + int newsize; + const char *fdtstart = fdt; + const char *fdtend = fdtstart + fdt_totalsize(fdt); + char *tmp; + + FDT_RO_PROBE(fdt); + + mem_rsv_size = (fdt_num_mem_rsv(fdt)+1) + * sizeof(struct fdt_reserve_entry); + + if (can_assume(LATEST) || fdt_version(fdt) >= 17) { + struct_size = fdt_size_dt_struct(fdt); + } else { + struct_size = 0; + while (fdt_next_tag(fdt, struct_size, &struct_size) != FDT_END) + ; + if (struct_size < 0) + return struct_size; + } + + if (can_assume(LIBFDT_ORDER) || + !fdt_blocks_misordered_(fdt, mem_rsv_size, struct_size)) { + /* no further work necessary */ + err = fdt_move(fdt, buf, bufsize); + if (err) + return err; + fdt_set_version(buf, 17); + fdt_set_size_dt_struct(buf, struct_size); + fdt_set_totalsize(buf, bufsize); + return 0; + } + + /* Need to reorder */ + newsize = FDT_ALIGN(sizeof(struct fdt_header), 8) + mem_rsv_size + + struct_size + fdt_size_dt_strings(fdt); + + if (bufsize < newsize) + return -FDT_ERR_NOSPACE; + + /* First attempt to build converted tree at beginning of buffer */ + tmp = buf; + /* But if that overlaps with the old tree... */ + if (((tmp + newsize) > fdtstart) && (tmp < fdtend)) { + /* Try right after the old tree instead */ + tmp = (char *)(uintptr_t)fdtend; + if ((tmp + newsize) > ((char *)buf + bufsize)) + return -FDT_ERR_NOSPACE; + } + + fdt_packblocks_(fdt, tmp, mem_rsv_size, struct_size); + memmove(buf, tmp, newsize); + + fdt_set_magic(buf, FDT_MAGIC); + fdt_set_totalsize(buf, bufsize); + fdt_set_version(buf, 17); + fdt_set_last_comp_version(buf, 16); + fdt_set_boot_cpuid_phys(buf, fdt_boot_cpuid_phys(fdt)); + + return 0; +} + +int fdt_pack(void *fdt) +{ + int mem_rsv_size; + + FDT_RW_PROBE(fdt); + + mem_rsv_size = (fdt_num_mem_rsv(fdt)+1) + * sizeof(struct fdt_reserve_entry); + fdt_packblocks_(fdt, fdt, mem_rsv_size, fdt_size_dt_struct(fdt)); + fdt_set_totalsize(fdt, fdt_data_size_(fdt)); + + return 0; +} diff --git a/src/net/scripts/dtc/libfdt/fdt_strerror.c b/src/net/scripts/dtc/libfdt/fdt_strerror.c new file mode 100644 index 0000000..b435693 --- /dev/null +++ b/src/net/scripts/dtc/libfdt/fdt_strerror.c @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * libfdt - Flat Device Tree manipulation + * Copyright (C) 2006 David Gibson, IBM Corporation. + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "libfdt_env.h" + +#include <fdt.h> +#include <libfdt.h> + +#include "libfdt_internal.h" + +struct fdt_errtabent { + const char *str; +}; + +#define FDT_ERRTABENT(val) \ + [(val)] = { .str = #val, } + +static struct fdt_errtabent fdt_errtable[] = { + FDT_ERRTABENT(FDT_ERR_NOTFOUND), + FDT_ERRTABENT(FDT_ERR_EXISTS), + FDT_ERRTABENT(FDT_ERR_NOSPACE), + + FDT_ERRTABENT(FDT_ERR_BADOFFSET), + FDT_ERRTABENT(FDT_ERR_BADPATH), + FDT_ERRTABENT(FDT_ERR_BADPHANDLE), + FDT_ERRTABENT(FDT_ERR_BADSTATE), + + FDT_ERRTABENT(FDT_ERR_TRUNCATED), + FDT_ERRTABENT(FDT_ERR_BADMAGIC), + FDT_ERRTABENT(FDT_ERR_BADVERSION), + FDT_ERRTABENT(FDT_ERR_BADSTRUCTURE), + FDT_ERRTABENT(FDT_ERR_BADLAYOUT), + FDT_ERRTABENT(FDT_ERR_INTERNAL), + FDT_ERRTABENT(FDT_ERR_BADNCELLS), + FDT_ERRTABENT(FDT_ERR_BADVALUE), + FDT_ERRTABENT(FDT_ERR_BADOVERLAY), + FDT_ERRTABENT(FDT_ERR_NOPHANDLES), + FDT_ERRTABENT(FDT_ERR_BADFLAGS), +}; +#define FDT_ERRTABSIZE ((int)(sizeof(fdt_errtable) / sizeof(fdt_errtable[0]))) + +const char *fdt_strerror(int errval) +{ + if (errval > 0) + return "<valid offset/length>"; + else if (errval == 0) + return "<no error>"; + else if (-errval < FDT_ERRTABSIZE) { + const char *s = fdt_errtable[-errval].str; + + if (s) + return s; + } + + return "<unknown error>"; +} diff --git a/src/net/scripts/dtc/libfdt/fdt_sw.c b/src/net/scripts/dtc/libfdt/fdt_sw.c new file mode 100644 index 0000000..68b543c --- /dev/null +++ b/src/net/scripts/dtc/libfdt/fdt_sw.c @@ -0,0 +1,384 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * libfdt - Flat Device Tree manipulation + * Copyright (C) 2006 David Gibson, IBM Corporation. + */ +#include "libfdt_env.h" + +#include <fdt.h> +#include <libfdt.h> + +#include "libfdt_internal.h" + +static int fdt_sw_probe_(void *fdt) +{ + if (!can_assume(VALID_INPUT)) { + if (fdt_magic(fdt) == FDT_MAGIC) + return -FDT_ERR_BADSTATE; + else if (fdt_magic(fdt) != FDT_SW_MAGIC) + return -FDT_ERR_BADMAGIC; + } + + return 0; +} + +#define FDT_SW_PROBE(fdt) \ + { \ + int err; \ + if ((err = fdt_sw_probe_(fdt)) != 0) \ + return err; \ + } + +/* 'memrsv' state: Initial state after fdt_create() + * + * Allowed functions: + * fdt_add_reservemap_entry() + * fdt_finish_reservemap() [moves to 'struct' state] + */ +static int fdt_sw_probe_memrsv_(void *fdt) +{ + int err = fdt_sw_probe_(fdt); + if (err) + return err; + + if (!can_assume(VALID_INPUT) && fdt_off_dt_strings(fdt) != 0) + return -FDT_ERR_BADSTATE; + return 0; +} + +#define FDT_SW_PROBE_MEMRSV(fdt) \ + { \ + int err; \ + if ((err = fdt_sw_probe_memrsv_(fdt)) != 0) \ + return err; \ + } + +/* 'struct' state: Enter this state after fdt_finish_reservemap() + * + * Allowed functions: + * fdt_begin_node() + * fdt_end_node() + * fdt_property*() + * fdt_finish() [moves to 'complete' state] + */ +static int fdt_sw_probe_struct_(void *fdt) +{ + int err = fdt_sw_probe_(fdt); + if (err) + return err; + + if (!can_assume(VALID_INPUT) && + fdt_off_dt_strings(fdt) != fdt_totalsize(fdt)) + return -FDT_ERR_BADSTATE; + return 0; +} + +#define FDT_SW_PROBE_STRUCT(fdt) \ + { \ + int err; \ + if ((err = fdt_sw_probe_struct_(fdt)) != 0) \ + return err; \ + } + +static inline uint32_t sw_flags(void *fdt) +{ + /* assert: (fdt_magic(fdt) == FDT_SW_MAGIC) */ + return fdt_last_comp_version(fdt); +} + +/* 'complete' state: Enter this state after fdt_finish() + * + * Allowed functions: none + */ + +static void *fdt_grab_space_(void *fdt, size_t len) +{ + unsigned int offset = fdt_size_dt_struct(fdt); + unsigned int spaceleft; + + spaceleft = fdt_totalsize(fdt) - fdt_off_dt_struct(fdt) + - fdt_size_dt_strings(fdt); + + if ((offset + len < offset) || (offset + len > spaceleft)) + return NULL; + + fdt_set_size_dt_struct(fdt, offset + len); + return fdt_offset_ptr_w_(fdt, offset); +} + +int fdt_create_with_flags(void *buf, int bufsize, uint32_t flags) +{ + const int hdrsize = FDT_ALIGN(sizeof(struct fdt_header), + sizeof(struct fdt_reserve_entry)); + void *fdt = buf; + + if (bufsize < hdrsize) + return -FDT_ERR_NOSPACE; + + if (flags & ~FDT_CREATE_FLAGS_ALL) + return -FDT_ERR_BADFLAGS; + + memset(buf, 0, bufsize); + + /* + * magic and last_comp_version keep intermediate state during the fdt + * creation process, which is replaced with the proper FDT format by + * fdt_finish(). + * + * flags should be accessed with sw_flags(). + */ + fdt_set_magic(fdt, FDT_SW_MAGIC); + fdt_set_version(fdt, FDT_LAST_SUPPORTED_VERSION); + fdt_set_last_comp_version(fdt, flags); + + fdt_set_totalsize(fdt, bufsize); + + fdt_set_off_mem_rsvmap(fdt, hdrsize); + fdt_set_off_dt_struct(fdt, fdt_off_mem_rsvmap(fdt)); + fdt_set_off_dt_strings(fdt, 0); + + return 0; +} + +int fdt_create(void *buf, int bufsize) +{ + return fdt_create_with_flags(buf, bufsize, 0); +} + +int fdt_resize(void *fdt, void *buf, int bufsize) +{ + size_t headsize, tailsize; + char *oldtail, *newtail; + + FDT_SW_PROBE(fdt); + + if (bufsize < 0) + return -FDT_ERR_NOSPACE; + + headsize = fdt_off_dt_struct(fdt) + fdt_size_dt_struct(fdt); + tailsize = fdt_size_dt_strings(fdt); + + if (!can_assume(VALID_DTB) && + headsize + tailsize > fdt_totalsize(fdt)) + return -FDT_ERR_INTERNAL; + + if ((headsize + tailsize) > (unsigned)bufsize) + return -FDT_ERR_NOSPACE; + + oldtail = (char *)fdt + fdt_totalsize(fdt) - tailsize; + newtail = (char *)buf + bufsize - tailsize; + + /* Two cases to avoid clobbering data if the old and new + * buffers partially overlap */ + if (buf <= fdt) { + memmove(buf, fdt, headsize); + memmove(newtail, oldtail, tailsize); + } else { + memmove(newtail, oldtail, tailsize); + memmove(buf, fdt, headsize); + } + + fdt_set_totalsize(buf, bufsize); + if (fdt_off_dt_strings(buf)) + fdt_set_off_dt_strings(buf, bufsize); + + return 0; +} + +int fdt_add_reservemap_entry(void *fdt, uint64_t addr, uint64_t size) +{ + struct fdt_reserve_entry *re; + int offset; + + FDT_SW_PROBE_MEMRSV(fdt); + + offset = fdt_off_dt_struct(fdt); + if ((offset + sizeof(*re)) > fdt_totalsize(fdt)) + return -FDT_ERR_NOSPACE; + + re = (struct fdt_reserve_entry *)((char *)fdt + offset); + re->address = cpu_to_fdt64(addr); + re->size = cpu_to_fdt64(size); + + fdt_set_off_dt_struct(fdt, offset + sizeof(*re)); + + return 0; +} + +int fdt_finish_reservemap(void *fdt) +{ + int err = fdt_add_reservemap_entry(fdt, 0, 0); + + if (err) + return err; + + fdt_set_off_dt_strings(fdt, fdt_totalsize(fdt)); + return 0; +} + +int fdt_begin_node(void *fdt, const char *name) +{ + struct fdt_node_header *nh; + int namelen; + + FDT_SW_PROBE_STRUCT(fdt); + + namelen = strlen(name) + 1; + nh = fdt_grab_space_(fdt, sizeof(*nh) + FDT_TAGALIGN(namelen)); + if (! nh) + return -FDT_ERR_NOSPACE; + + nh->tag = cpu_to_fdt32(FDT_BEGIN_NODE); + memcpy(nh->name, name, namelen); + return 0; +} + +int fdt_end_node(void *fdt) +{ + fdt32_t *en; + + FDT_SW_PROBE_STRUCT(fdt); + + en = fdt_grab_space_(fdt, FDT_TAGSIZE); + if (! en) + return -FDT_ERR_NOSPACE; + + *en = cpu_to_fdt32(FDT_END_NODE); + return 0; +} + +static int fdt_add_string_(void *fdt, const char *s) +{ + char *strtab = (char *)fdt + fdt_totalsize(fdt); + unsigned int strtabsize = fdt_size_dt_strings(fdt); + unsigned int len = strlen(s) + 1; + unsigned int struct_top, offset; + + offset = strtabsize + len; + struct_top = fdt_off_dt_struct(fdt) + fdt_size_dt_struct(fdt); + if (fdt_totalsize(fdt) - offset < struct_top) + return 0; /* no more room :( */ + + memcpy(strtab - offset, s, len); + fdt_set_size_dt_strings(fdt, strtabsize + len); + return -offset; +} + +/* Must only be used to roll back in case of error */ +static void fdt_del_last_string_(void *fdt, const char *s) +{ + int strtabsize = fdt_size_dt_strings(fdt); + int len = strlen(s) + 1; + + fdt_set_size_dt_strings(fdt, strtabsize - len); +} + +static int fdt_find_add_string_(void *fdt, const char *s, int *allocated) +{ + char *strtab = (char *)fdt + fdt_totalsize(fdt); + int strtabsize = fdt_size_dt_strings(fdt); + const char *p; + + *allocated = 0; + + p = fdt_find_string_(strtab - strtabsize, strtabsize, s); + if (p) + return p - strtab; + + *allocated = 1; + + return fdt_add_string_(fdt, s); +} + +int fdt_property_placeholder(void *fdt, const char *name, int len, void **valp) +{ + struct fdt_property *prop; + int nameoff; + int allocated; + + FDT_SW_PROBE_STRUCT(fdt); + + /* String de-duplication can be slow, _NO_NAME_DEDUP skips it */ + if (sw_flags(fdt) & FDT_CREATE_FLAG_NO_NAME_DEDUP) { + allocated = 1; + nameoff = fdt_add_string_(fdt, name); + } else { + nameoff = fdt_find_add_string_(fdt, name, &allocated); + } + if (nameoff == 0) + return -FDT_ERR_NOSPACE; + + prop = fdt_grab_space_(fdt, sizeof(*prop) + FDT_TAGALIGN(len)); + if (! prop) { + if (allocated) + fdt_del_last_string_(fdt, name); + return -FDT_ERR_NOSPACE; + } + + prop->tag = cpu_to_fdt32(FDT_PROP); + prop->nameoff = cpu_to_fdt32(nameoff); + prop->len = cpu_to_fdt32(len); + *valp = prop->data; + return 0; +} + +int fdt_property(void *fdt, const char *name, const void *val, int len) +{ + void *ptr; + int ret; + + ret = fdt_property_placeholder(fdt, name, len, &ptr); + if (ret) + return ret; + memcpy(ptr, val, len); + return 0; +} + +int fdt_finish(void *fdt) +{ + char *p = (char *)fdt; + fdt32_t *end; + int oldstroffset, newstroffset; + uint32_t tag; + int offset, nextoffset; + + FDT_SW_PROBE_STRUCT(fdt); + + /* Add terminator */ + end = fdt_grab_space_(fdt, sizeof(*end)); + if (! end) + return -FDT_ERR_NOSPACE; + *end = cpu_to_fdt32(FDT_END); + + /* Relocate the string table */ + oldstroffset = fdt_totalsize(fdt) - fdt_size_dt_strings(fdt); + newstroffset = fdt_off_dt_struct(fdt) + fdt_size_dt_struct(fdt); + memmove(p + newstroffset, p + oldstroffset, fdt_size_dt_strings(fdt)); + fdt_set_off_dt_strings(fdt, newstroffset); + + /* Walk the structure, correcting string offsets */ + offset = 0; + while ((tag = fdt_next_tag(fdt, offset, &nextoffset)) != FDT_END) { + if (tag == FDT_PROP) { + struct fdt_property *prop = + fdt_offset_ptr_w_(fdt, offset); + int nameoff; + + nameoff = fdt32_to_cpu(prop->nameoff); + nameoff += fdt_size_dt_strings(fdt); + prop->nameoff = cpu_to_fdt32(nameoff); + } + offset = nextoffset; + } + if (nextoffset < 0) + return nextoffset; + + /* Finally, adjust the header */ + fdt_set_totalsize(fdt, newstroffset + fdt_size_dt_strings(fdt)); + + /* And fix up fields that were keeping intermediate state. */ + fdt_set_last_comp_version(fdt, FDT_FIRST_SUPPORTED_VERSION); + fdt_set_magic(fdt, FDT_MAGIC); + + return 0; +} diff --git a/src/net/scripts/dtc/libfdt/fdt_wip.c b/src/net/scripts/dtc/libfdt/fdt_wip.c new file mode 100644 index 0000000..c2d7566 --- /dev/null +++ b/src/net/scripts/dtc/libfdt/fdt_wip.c @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * libfdt - Flat Device Tree manipulation + * Copyright (C) 2006 David Gibson, IBM Corporation. + */ +#include "libfdt_env.h" + +#include <fdt.h> +#include <libfdt.h> + +#include "libfdt_internal.h" + +int fdt_setprop_inplace_namelen_partial(void *fdt, int nodeoffset, + const char *name, int namelen, + uint32_t idx, const void *val, + int len) +{ + void *propval; + int proplen; + + propval = fdt_getprop_namelen_w(fdt, nodeoffset, name, namelen, + &proplen); + if (!propval) + return proplen; + + if ((unsigned)proplen < (len + idx)) + return -FDT_ERR_NOSPACE; + + memcpy((char *)propval + idx, val, len); + return 0; +} + +int fdt_setprop_inplace(void *fdt, int nodeoffset, const char *name, + const void *val, int len) +{ + const void *propval; + int proplen; + + propval = fdt_getprop(fdt, nodeoffset, name, &proplen); + if (!propval) + return proplen; + + if (proplen != len) + return -FDT_ERR_NOSPACE; + + return fdt_setprop_inplace_namelen_partial(fdt, nodeoffset, name, + strlen(name), 0, + val, len); +} + +static void fdt_nop_region_(void *start, int len) +{ + fdt32_t *p; + + for (p = start; (char *)p < ((char *)start + len); p++) + *p = cpu_to_fdt32(FDT_NOP); +} + +int fdt_nop_property(void *fdt, int nodeoffset, const char *name) +{ + struct fdt_property *prop; + int len; + + prop = fdt_get_property_w(fdt, nodeoffset, name, &len); + if (!prop) + return len; + + fdt_nop_region_(prop, len + sizeof(*prop)); + + return 0; +} + +int fdt_node_end_offset_(void *fdt, int offset) +{ + int depth = 0; + + while ((offset >= 0) && (depth >= 0)) + offset = fdt_next_node(fdt, offset, &depth); + + return offset; +} + +int fdt_nop_node(void *fdt, int nodeoffset) +{ + int endoffset; + + endoffset = fdt_node_end_offset_(fdt, nodeoffset); + if (endoffset < 0) + return endoffset; + + fdt_nop_region_(fdt_offset_ptr_w(fdt, nodeoffset, 0), + endoffset - nodeoffset); + return 0; +} diff --git a/src/net/scripts/dtc/libfdt/libfdt.h b/src/net/scripts/dtc/libfdt/libfdt.h new file mode 100644 index 0000000..fe49b5d --- /dev/null +++ b/src/net/scripts/dtc/libfdt/libfdt.h @@ -0,0 +1,2080 @@ +/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) */ +#ifndef LIBFDT_H +#define LIBFDT_H +/* + * libfdt - Flat Device Tree manipulation + * Copyright (C) 2006 David Gibson, IBM Corporation. + */ + +#include "libfdt_env.h" +#include "fdt.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define FDT_FIRST_SUPPORTED_VERSION 0x02 +#define FDT_LAST_SUPPORTED_VERSION 0x11 + +/* Error codes: informative error codes */ +#define FDT_ERR_NOTFOUND 1 + /* FDT_ERR_NOTFOUND: The requested node or property does not exist */ +#define FDT_ERR_EXISTS 2 + /* FDT_ERR_EXISTS: Attempted to create a node or property which + * already exists */ +#define FDT_ERR_NOSPACE 3 + /* FDT_ERR_NOSPACE: Operation needed to expand the device + * tree, but its buffer did not have sufficient space to + * contain the expanded tree. Use fdt_open_into() to move the + * device tree to a buffer with more space. */ + +/* Error codes: codes for bad parameters */ +#define FDT_ERR_BADOFFSET 4 + /* FDT_ERR_BADOFFSET: Function was passed a structure block + * offset which is out-of-bounds, or which points to an + * unsuitable part of the structure for the operation. */ +#define FDT_ERR_BADPATH 5 + /* FDT_ERR_BADPATH: Function was passed a badly formatted path + * (e.g. missing a leading / for a function which requires an + * absolute path) */ +#define FDT_ERR_BADPHANDLE 6 + /* FDT_ERR_BADPHANDLE: Function was passed an invalid phandle. + * This can be caused either by an invalid phandle property + * length, or the phandle value was either 0 or -1, which are + * not permitted. */ +#define FDT_ERR_BADSTATE 7 + /* FDT_ERR_BADSTATE: Function was passed an incomplete device + * tree created by the sequential-write functions, which is + * not sufficiently complete for the requested operation. */ + +/* Error codes: codes for bad device tree blobs */ +#define FDT_ERR_TRUNCATED 8 + /* FDT_ERR_TRUNCATED: FDT or a sub-block is improperly + * terminated (overflows, goes outside allowed bounds, or + * isn't properly terminated). */ +#define FDT_ERR_BADMAGIC 9 + /* FDT_ERR_BADMAGIC: Given "device tree" appears not to be a + * device tree at all - it is missing the flattened device + * tree magic number. */ +#define FDT_ERR_BADVERSION 10 + /* FDT_ERR_BADVERSION: Given device tree has a version which + * can't be handled by the requested operation. For + * read-write functions, this may mean that fdt_open_into() is + * required to convert the tree to the expected version. */ +#define FDT_ERR_BADSTRUCTURE 11 + /* FDT_ERR_BADSTRUCTURE: Given device tree has a corrupt + * structure block or other serious error (e.g. misnested + * nodes, or subnodes preceding properties). */ +#define FDT_ERR_BADLAYOUT 12 + /* FDT_ERR_BADLAYOUT: For read-write functions, the given + * device tree has it's sub-blocks in an order that the + * function can't handle (memory reserve map, then structure, + * then strings). Use fdt_open_into() to reorganize the tree + * into a form suitable for the read-write operations. */ + +/* "Can't happen" error indicating a bug in libfdt */ +#define FDT_ERR_INTERNAL 13 + /* FDT_ERR_INTERNAL: libfdt has failed an internal assertion. + * Should never be returned, if it is, it indicates a bug in + * libfdt itself. */ + +/* Errors in device tree content */ +#define FDT_ERR_BADNCELLS 14 + /* FDT_ERR_BADNCELLS: Device tree has a #address-cells, #size-cells + * or similar property with a bad format or value */ + +#define FDT_ERR_BADVALUE 15 + /* FDT_ERR_BADVALUE: Device tree has a property with an unexpected + * value. For example: a property expected to contain a string list + * is not NUL-terminated within the length of its value. */ + +#define FDT_ERR_BADOVERLAY 16 + /* FDT_ERR_BADOVERLAY: The device tree overlay, while + * correctly structured, cannot be applied due to some + * unexpected or missing value, property or node. */ + +#define FDT_ERR_NOPHANDLES 17 + /* FDT_ERR_NOPHANDLES: The device tree doesn't have any + * phandle available anymore without causing an overflow */ + +#define FDT_ERR_BADFLAGS 18 + /* FDT_ERR_BADFLAGS: The function was passed a flags field that + * contains invalid flags or an invalid combination of flags. */ + +#define FDT_ERR_MAX 18 + +/* constants */ +#define FDT_MAX_PHANDLE 0xfffffffe + /* Valid values for phandles range from 1 to 2^32-2. */ + +/**********************************************************************/ +/* Low-level functions (you probably don't need these) */ +/**********************************************************************/ + +#ifndef SWIG /* This function is not useful in Python */ +const void *fdt_offset_ptr(const void *fdt, int offset, unsigned int checklen); +#endif +static inline void *fdt_offset_ptr_w(void *fdt, int offset, int checklen) +{ + return (void *)(uintptr_t)fdt_offset_ptr(fdt, offset, checklen); +} + +uint32_t fdt_next_tag(const void *fdt, int offset, int *nextoffset); + +/* + * Alignment helpers: + * These helpers access words from a device tree blob. They're + * built to work even with unaligned pointers on platforms (ike + * ARM) that don't like unaligned loads and stores + */ + +static inline uint32_t fdt32_ld(const fdt32_t *p) +{ + const uint8_t *bp = (const uint8_t *)p; + + return ((uint32_t)bp[0] << 24) + | ((uint32_t)bp[1] << 16) + | ((uint32_t)bp[2] << 8) + | bp[3]; +} + +static inline void fdt32_st(void *property, uint32_t value) +{ + uint8_t *bp = (uint8_t *)property; + + bp[0] = value >> 24; + bp[1] = (value >> 16) & 0xff; + bp[2] = (value >> 8) & 0xff; + bp[3] = value & 0xff; +} + +static inline uint64_t fdt64_ld(const fdt64_t *p) +{ + const uint8_t *bp = (const uint8_t *)p; + + return ((uint64_t)bp[0] << 56) + | ((uint64_t)bp[1] << 48) + | ((uint64_t)bp[2] << 40) + | ((uint64_t)bp[3] << 32) + | ((uint64_t)bp[4] << 24) + | ((uint64_t)bp[5] << 16) + | ((uint64_t)bp[6] << 8) + | bp[7]; +} + +static inline void fdt64_st(void *property, uint64_t value) +{ + uint8_t *bp = (uint8_t *)property; + + bp[0] = value >> 56; + bp[1] = (value >> 48) & 0xff; + bp[2] = (value >> 40) & 0xff; + bp[3] = (value >> 32) & 0xff; + bp[4] = (value >> 24) & 0xff; + bp[5] = (value >> 16) & 0xff; + bp[6] = (value >> 8) & 0xff; + bp[7] = value & 0xff; +} + +/**********************************************************************/ +/* Traversal functions */ +/**********************************************************************/ + +int fdt_next_node(const void *fdt, int offset, int *depth); + +/** + * fdt_first_subnode() - get offset of first direct subnode + * + * @fdt: FDT blob + * @offset: Offset of node to check + * @return offset of first subnode, or -FDT_ERR_NOTFOUND if there is none + */ +int fdt_first_subnode(const void *fdt, int offset); + +/** + * fdt_next_subnode() - get offset of next direct subnode + * + * After first calling fdt_first_subnode(), call this function repeatedly to + * get direct subnodes of a parent node. + * + * @fdt: FDT blob + * @offset: Offset of previous subnode + * @return offset of next subnode, or -FDT_ERR_NOTFOUND if there are no more + * subnodes + */ +int fdt_next_subnode(const void *fdt, int offset); + +/** + * fdt_for_each_subnode - iterate over all subnodes of a parent + * + * @node: child node (int, lvalue) + * @fdt: FDT blob (const void *) + * @parent: parent node (int) + * + * This is actually a wrapper around a for loop and would be used like so: + * + * fdt_for_each_subnode(node, fdt, parent) { + * Use node + * ... + * } + * + * if ((node < 0) && (node != -FDT_ERR_NOTFOUND)) { + * Error handling + * } + * + * Note that this is implemented as a macro and @node is used as + * iterator in the loop. The parent variable be constant or even a + * literal. + * + */ +#define fdt_for_each_subnode(node, fdt, parent) \ + for (node = fdt_first_subnode(fdt, parent); \ + node >= 0; \ + node = fdt_next_subnode(fdt, node)) + +/**********************************************************************/ +/* General functions */ +/**********************************************************************/ +#define fdt_get_header(fdt, field) \ + (fdt32_ld(&((const struct fdt_header *)(fdt))->field)) +#define fdt_magic(fdt) (fdt_get_header(fdt, magic)) +#define fdt_totalsize(fdt) (fdt_get_header(fdt, totalsize)) +#define fdt_off_dt_struct(fdt) (fdt_get_header(fdt, off_dt_struct)) +#define fdt_off_dt_strings(fdt) (fdt_get_header(fdt, off_dt_strings)) +#define fdt_off_mem_rsvmap(fdt) (fdt_get_header(fdt, off_mem_rsvmap)) +#define fdt_version(fdt) (fdt_get_header(fdt, version)) +#define fdt_last_comp_version(fdt) (fdt_get_header(fdt, last_comp_version)) +#define fdt_boot_cpuid_phys(fdt) (fdt_get_header(fdt, boot_cpuid_phys)) +#define fdt_size_dt_strings(fdt) (fdt_get_header(fdt, size_dt_strings)) +#define fdt_size_dt_struct(fdt) (fdt_get_header(fdt, size_dt_struct)) + +#define fdt_set_hdr_(name) \ + static inline void fdt_set_##name(void *fdt, uint32_t val) \ + { \ + struct fdt_header *fdth = (struct fdt_header *)fdt; \ + fdth->name = cpu_to_fdt32(val); \ + } +fdt_set_hdr_(magic); +fdt_set_hdr_(totalsize); +fdt_set_hdr_(off_dt_struct); +fdt_set_hdr_(off_dt_strings); +fdt_set_hdr_(off_mem_rsvmap); +fdt_set_hdr_(version); +fdt_set_hdr_(last_comp_version); +fdt_set_hdr_(boot_cpuid_phys); +fdt_set_hdr_(size_dt_strings); +fdt_set_hdr_(size_dt_struct); +#undef fdt_set_hdr_ + +/** + * fdt_header_size - return the size of the tree's header + * @fdt: pointer to a flattened device tree + */ +size_t fdt_header_size(const void *fdt); + +/** + * fdt_header_size_ - internal function which takes a version number + */ +size_t fdt_header_size_(uint32_t version); + +/** + * fdt_check_header - sanity check a device tree header + + * @fdt: pointer to data which might be a flattened device tree + * + * fdt_check_header() checks that the given buffer contains what + * appears to be a flattened device tree, and that the header contains + * valid information (to the extent that can be determined from the + * header alone). + * + * returns: + * 0, if the buffer appears to contain a valid device tree + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_TRUNCATED, standard meanings, as above + */ +int fdt_check_header(const void *fdt); + +/** + * fdt_move - move a device tree around in memory + * @fdt: pointer to the device tree to move + * @buf: pointer to memory where the device is to be moved + * @bufsize: size of the memory space at buf + * + * fdt_move() relocates, if possible, the device tree blob located at + * fdt to the buffer at buf of size bufsize. The buffer may overlap + * with the existing device tree blob at fdt. Therefore, + * fdt_move(fdt, fdt, fdt_totalsize(fdt)) + * should always succeed. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, bufsize is insufficient to contain the device tree + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, standard meanings + */ +int fdt_move(const void *fdt, void *buf, int bufsize); + +/**********************************************************************/ +/* Read-only functions */ +/**********************************************************************/ + +int fdt_check_full(const void *fdt, size_t bufsize); + +/** + * fdt_get_string - retrieve a string from the strings block of a device tree + * @fdt: pointer to the device tree blob + * @stroffset: offset of the string within the strings block (native endian) + * @lenp: optional pointer to return the string's length + * + * fdt_get_string() retrieves a pointer to a single string from the + * strings block of the device tree blob at fdt, and optionally also + * returns the string's length in *lenp. + * + * returns: + * a pointer to the string, on success + * NULL, if stroffset is out of bounds, or doesn't point to a valid string + */ +const char *fdt_get_string(const void *fdt, int stroffset, int *lenp); + +/** + * fdt_string - retrieve a string from the strings block of a device tree + * @fdt: pointer to the device tree blob + * @stroffset: offset of the string within the strings block (native endian) + * + * fdt_string() retrieves a pointer to a single string from the + * strings block of the device tree blob at fdt. + * + * returns: + * a pointer to the string, on success + * NULL, if stroffset is out of bounds, or doesn't point to a valid string + */ +const char *fdt_string(const void *fdt, int stroffset); + +/** + * fdt_find_max_phandle - find and return the highest phandle in a tree + * @fdt: pointer to the device tree blob + * @phandle: return location for the highest phandle value found in the tree + * + * fdt_find_max_phandle() finds the highest phandle value in the given device + * tree. The value returned in @phandle is only valid if the function returns + * success. + * + * returns: + * 0 on success or a negative error code on failure + */ +int fdt_find_max_phandle(const void *fdt, uint32_t *phandle); + +/** + * fdt_get_max_phandle - retrieves the highest phandle in a tree + * @fdt: pointer to the device tree blob + * + * fdt_get_max_phandle retrieves the highest phandle in the given + * device tree. This will ignore badly formatted phandles, or phandles + * with a value of 0 or -1. + * + * This function is deprecated in favour of fdt_find_max_phandle(). + * + * returns: + * the highest phandle on success + * 0, if no phandle was found in the device tree + * -1, if an error occurred + */ +static inline uint32_t fdt_get_max_phandle(const void *fdt) +{ + uint32_t phandle; + int err; + + err = fdt_find_max_phandle(fdt, &phandle); + if (err < 0) + return (uint32_t)-1; + + return phandle; +} + +/** + * fdt_generate_phandle - return a new, unused phandle for a device tree blob + * @fdt: pointer to the device tree blob + * @phandle: return location for the new phandle + * + * Walks the device tree blob and looks for the highest phandle value. On + * success, the new, unused phandle value (one higher than the previously + * highest phandle value in the device tree blob) will be returned in the + * @phandle parameter. + * + * Returns: + * 0 on success or a negative error-code on failure + */ +int fdt_generate_phandle(const void *fdt, uint32_t *phandle); + +/** + * fdt_num_mem_rsv - retrieve the number of memory reserve map entries + * @fdt: pointer to the device tree blob + * + * Returns the number of entries in the device tree blob's memory + * reservation map. This does not include the terminating 0,0 entry + * or any other (0,0) entries reserved for expansion. + * + * returns: + * the number of entries + */ +int fdt_num_mem_rsv(const void *fdt); + +/** + * fdt_get_mem_rsv - retrieve one memory reserve map entry + * @fdt: pointer to the device tree blob + * @address, @size: pointers to 64-bit variables + * + * On success, *address and *size will contain the address and size of + * the n-th reserve map entry from the device tree blob, in + * native-endian format. + * + * returns: + * 0, on success + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, standard meanings + */ +int fdt_get_mem_rsv(const void *fdt, int n, uint64_t *address, uint64_t *size); + +/** + * fdt_subnode_offset_namelen - find a subnode based on substring + * @fdt: pointer to the device tree blob + * @parentoffset: structure block offset of a node + * @name: name of the subnode to locate + * @namelen: number of characters of name to consider + * + * Identical to fdt_subnode_offset(), but only examine the first + * namelen characters of name for matching the subnode name. This is + * useful for finding subnodes based on a portion of a larger string, + * such as a full path. + */ +#ifndef SWIG /* Not available in Python */ +int fdt_subnode_offset_namelen(const void *fdt, int parentoffset, + const char *name, int namelen); +#endif +/** + * fdt_subnode_offset - find a subnode of a given node + * @fdt: pointer to the device tree blob + * @parentoffset: structure block offset of a node + * @name: name of the subnode to locate + * + * fdt_subnode_offset() finds a subnode of the node at structure block + * offset parentoffset with the given name. name may include a unit + * address, in which case fdt_subnode_offset() will find the subnode + * with that unit address, or the unit address may be omitted, in + * which case fdt_subnode_offset() will find an arbitrary subnode + * whose name excluding unit address matches the given name. + * + * returns: + * structure block offset of the requested subnode (>=0), on success + * -FDT_ERR_NOTFOUND, if the requested subnode does not exist + * -FDT_ERR_BADOFFSET, if parentoffset did not point to an FDT_BEGIN_NODE + * tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings. + */ +int fdt_subnode_offset(const void *fdt, int parentoffset, const char *name); + +/** + * fdt_path_offset_namelen - find a tree node by its full path + * @fdt: pointer to the device tree blob + * @path: full path of the node to locate + * @namelen: number of characters of path to consider + * + * Identical to fdt_path_offset(), but only consider the first namelen + * characters of path as the path name. + */ +#ifndef SWIG /* Not available in Python */ +int fdt_path_offset_namelen(const void *fdt, const char *path, int namelen); +#endif + +/** + * fdt_path_offset - find a tree node by its full path + * @fdt: pointer to the device tree blob + * @path: full path of the node to locate + * + * fdt_path_offset() finds a node of a given path in the device tree. + * Each path component may omit the unit address portion, but the + * results of this are undefined if any such path component is + * ambiguous (that is if there are multiple nodes at the relevant + * level matching the given component, differentiated only by unit + * address). + * + * returns: + * structure block offset of the node with the requested path (>=0), on + * success + * -FDT_ERR_BADPATH, given path does not begin with '/' or is invalid + * -FDT_ERR_NOTFOUND, if the requested node does not exist + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings. + */ +int fdt_path_offset(const void *fdt, const char *path); + +/** + * fdt_get_name - retrieve the name of a given node + * @fdt: pointer to the device tree blob + * @nodeoffset: structure block offset of the starting node + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_get_name() retrieves the name (including unit address) of the + * device tree node at structure block offset nodeoffset. If lenp is + * non-NULL, the length of this name is also returned, in the integer + * pointed to by lenp. + * + * returns: + * pointer to the node's name, on success + * If lenp is non-NULL, *lenp contains the length of that name + * (>=0) + * NULL, on error + * if lenp is non-NULL *lenp contains an error code (<0): + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE + * tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, standard meanings + */ +const char *fdt_get_name(const void *fdt, int nodeoffset, int *lenp); + +/** + * fdt_first_property_offset - find the offset of a node's first property + * @fdt: pointer to the device tree blob + * @nodeoffset: structure block offset of a node + * + * fdt_first_property_offset() finds the first property of the node at + * the given structure block offset. + * + * returns: + * structure block offset of the property (>=0), on success + * -FDT_ERR_NOTFOUND, if the requested node has no properties + * -FDT_ERR_BADOFFSET, if nodeoffset did not point to an FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings. + */ +int fdt_first_property_offset(const void *fdt, int nodeoffset); + +/** + * fdt_next_property_offset - step through a node's properties + * @fdt: pointer to the device tree blob + * @offset: structure block offset of a property + * + * fdt_next_property_offset() finds the property immediately after the + * one at the given structure block offset. This will be a property + * of the same node as the given property. + * + * returns: + * structure block offset of the next property (>=0), on success + * -FDT_ERR_NOTFOUND, if the given property is the last in its node + * -FDT_ERR_BADOFFSET, if nodeoffset did not point to an FDT_PROP tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings. + */ +int fdt_next_property_offset(const void *fdt, int offset); + +/** + * fdt_for_each_property_offset - iterate over all properties of a node + * + * @property_offset: property offset (int, lvalue) + * @fdt: FDT blob (const void *) + * @node: node offset (int) + * + * This is actually a wrapper around a for loop and would be used like so: + * + * fdt_for_each_property_offset(property, fdt, node) { + * Use property + * ... + * } + * + * if ((property < 0) && (property != -FDT_ERR_NOTFOUND)) { + * Error handling + * } + * + * Note that this is implemented as a macro and property is used as + * iterator in the loop. The node variable can be constant or even a + * literal. + */ +#define fdt_for_each_property_offset(property, fdt, node) \ + for (property = fdt_first_property_offset(fdt, node); \ + property >= 0; \ + property = fdt_next_property_offset(fdt, property)) + +/** + * fdt_get_property_by_offset - retrieve the property at a given offset + * @fdt: pointer to the device tree blob + * @offset: offset of the property to retrieve + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_get_property_by_offset() retrieves a pointer to the + * fdt_property structure within the device tree blob at the given + * offset. If lenp is non-NULL, the length of the property value is + * also returned, in the integer pointed to by lenp. + * + * Note that this code only works on device tree versions >= 16. fdt_getprop() + * works on all versions. + * + * returns: + * pointer to the structure representing the property + * if lenp is non-NULL, *lenp contains the length of the property + * value (>=0) + * NULL, on error + * if lenp is non-NULL, *lenp contains an error code (<0): + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_PROP tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +const struct fdt_property *fdt_get_property_by_offset(const void *fdt, + int offset, + int *lenp); + +/** + * fdt_get_property_namelen - find a property based on substring + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to find + * @name: name of the property to find + * @namelen: number of characters of name to consider + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * Identical to fdt_get_property(), but only examine the first namelen + * characters of name for matching the property name. + */ +#ifndef SWIG /* Not available in Python */ +const struct fdt_property *fdt_get_property_namelen(const void *fdt, + int nodeoffset, + const char *name, + int namelen, int *lenp); +#endif + +/** + * fdt_get_property - find a given property in a given node + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to find + * @name: name of the property to find + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_get_property() retrieves a pointer to the fdt_property + * structure within the device tree blob corresponding to the property + * named 'name' of the node at offset nodeoffset. If lenp is + * non-NULL, the length of the property value is also returned, in the + * integer pointed to by lenp. + * + * returns: + * pointer to the structure representing the property + * if lenp is non-NULL, *lenp contains the length of the property + * value (>=0) + * NULL, on error + * if lenp is non-NULL, *lenp contains an error code (<0): + * -FDT_ERR_NOTFOUND, node does not have named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE + * tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +const struct fdt_property *fdt_get_property(const void *fdt, int nodeoffset, + const char *name, int *lenp); +static inline struct fdt_property *fdt_get_property_w(void *fdt, int nodeoffset, + const char *name, + int *lenp) +{ + return (struct fdt_property *)(uintptr_t) + fdt_get_property(fdt, nodeoffset, name, lenp); +} + +/** + * fdt_getprop_by_offset - retrieve the value of a property at a given offset + * @fdt: pointer to the device tree blob + * @offset: offset of the property to read + * @namep: pointer to a string variable (will be overwritten) or NULL + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_getprop_by_offset() retrieves a pointer to the value of the + * property at structure block offset 'offset' (this will be a pointer + * to within the device blob itself, not a copy of the value). If + * lenp is non-NULL, the length of the property value is also + * returned, in the integer pointed to by lenp. If namep is non-NULL, + * the property's namne will also be returned in the char * pointed to + * by namep (this will be a pointer to within the device tree's string + * block, not a new copy of the name). + * + * returns: + * pointer to the property's value + * if lenp is non-NULL, *lenp contains the length of the property + * value (>=0) + * if namep is non-NULL *namep contiains a pointer to the property + * name. + * NULL, on error + * if lenp is non-NULL, *lenp contains an error code (<0): + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_PROP tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +#ifndef SWIG /* This function is not useful in Python */ +const void *fdt_getprop_by_offset(const void *fdt, int offset, + const char **namep, int *lenp); +#endif + +/** + * fdt_getprop_namelen - get property value based on substring + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to find + * @name: name of the property to find + * @namelen: number of characters of name to consider + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * Identical to fdt_getprop(), but only examine the first namelen + * characters of name for matching the property name. + */ +#ifndef SWIG /* Not available in Python */ +const void *fdt_getprop_namelen(const void *fdt, int nodeoffset, + const char *name, int namelen, int *lenp); +static inline void *fdt_getprop_namelen_w(void *fdt, int nodeoffset, + const char *name, int namelen, + int *lenp) +{ + return (void *)(uintptr_t)fdt_getprop_namelen(fdt, nodeoffset, name, + namelen, lenp); +} +#endif + +/** + * fdt_getprop - retrieve the value of a given property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to find + * @name: name of the property to find + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_getprop() retrieves a pointer to the value of the property + * named 'name' of the node at offset nodeoffset (this will be a + * pointer to within the device blob itself, not a copy of the value). + * If lenp is non-NULL, the length of the property value is also + * returned, in the integer pointed to by lenp. + * + * returns: + * pointer to the property's value + * if lenp is non-NULL, *lenp contains the length of the property + * value (>=0) + * NULL, on error + * if lenp is non-NULL, *lenp contains an error code (<0): + * -FDT_ERR_NOTFOUND, node does not have named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE + * tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +const void *fdt_getprop(const void *fdt, int nodeoffset, + const char *name, int *lenp); +static inline void *fdt_getprop_w(void *fdt, int nodeoffset, + const char *name, int *lenp) +{ + return (void *)(uintptr_t)fdt_getprop(fdt, nodeoffset, name, lenp); +} + +/** + * fdt_get_phandle - retrieve the phandle of a given node + * @fdt: pointer to the device tree blob + * @nodeoffset: structure block offset of the node + * + * fdt_get_phandle() retrieves the phandle of the device tree node at + * structure block offset nodeoffset. + * + * returns: + * the phandle of the node at nodeoffset, on success (!= 0, != -1) + * 0, if the node has no phandle, or another error occurs + */ +uint32_t fdt_get_phandle(const void *fdt, int nodeoffset); + +/** + * fdt_get_alias_namelen - get alias based on substring + * @fdt: pointer to the device tree blob + * @name: name of the alias th look up + * @namelen: number of characters of name to consider + * + * Identical to fdt_get_alias(), but only examine the first namelen + * characters of name for matching the alias name. + */ +#ifndef SWIG /* Not available in Python */ +const char *fdt_get_alias_namelen(const void *fdt, + const char *name, int namelen); +#endif + +/** + * fdt_get_alias - retrieve the path referenced by a given alias + * @fdt: pointer to the device tree blob + * @name: name of the alias th look up + * + * fdt_get_alias() retrieves the value of a given alias. That is, the + * value of the property named 'name' in the node /aliases. + * + * returns: + * a pointer to the expansion of the alias named 'name', if it exists + * NULL, if the given alias or the /aliases node does not exist + */ +const char *fdt_get_alias(const void *fdt, const char *name); + +/** + * fdt_get_path - determine the full path of a node + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose path to find + * @buf: character buffer to contain the returned path (will be overwritten) + * @buflen: size of the character buffer at buf + * + * fdt_get_path() computes the full path of the node at offset + * nodeoffset, and records that path in the buffer at buf. + * + * NOTE: This function is expensive, as it must scan the device tree + * structure from the start to nodeoffset. + * + * returns: + * 0, on success + * buf contains the absolute path of the node at + * nodeoffset, as a NUL-terminated string. + * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_NOSPACE, the path of the given node is longer than (bufsize-1) + * characters and will not fit in the given buffer. + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_get_path(const void *fdt, int nodeoffset, char *buf, int buflen); + +/** + * fdt_supernode_atdepth_offset - find a specific ancestor of a node + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose parent to find + * @supernodedepth: depth of the ancestor to find + * @nodedepth: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_supernode_atdepth_offset() finds an ancestor of the given node + * at a specific depth from the root (where the root itself has depth + * 0, its immediate subnodes depth 1 and so forth). So + * fdt_supernode_atdepth_offset(fdt, nodeoffset, 0, NULL); + * will always return 0, the offset of the root node. If the node at + * nodeoffset has depth D, then: + * fdt_supernode_atdepth_offset(fdt, nodeoffset, D, NULL); + * will return nodeoffset itself. + * + * NOTE: This function is expensive, as it must scan the device tree + * structure from the start to nodeoffset. + * + * returns: + * structure block offset of the node at node offset's ancestor + * of depth supernodedepth (>=0), on success + * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_NOTFOUND, supernodedepth was greater than the depth of + * nodeoffset + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_supernode_atdepth_offset(const void *fdt, int nodeoffset, + int supernodedepth, int *nodedepth); + +/** + * fdt_node_depth - find the depth of a given node + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose parent to find + * + * fdt_node_depth() finds the depth of a given node. The root node + * has depth 0, its immediate subnodes depth 1 and so forth. + * + * NOTE: This function is expensive, as it must scan the device tree + * structure from the start to nodeoffset. + * + * returns: + * depth of the node at nodeoffset (>=0), on success + * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_node_depth(const void *fdt, int nodeoffset); + +/** + * fdt_parent_offset - find the parent of a given node + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose parent to find + * + * fdt_parent_offset() locates the parent node of a given node (that + * is, it finds the offset of the node which contains the node at + * nodeoffset as a subnode). + * + * NOTE: This function is expensive, as it must scan the device tree + * structure from the start to nodeoffset, *twice*. + * + * returns: + * structure block offset of the parent of the node at nodeoffset + * (>=0), on success + * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_parent_offset(const void *fdt, int nodeoffset); + +/** + * fdt_node_offset_by_prop_value - find nodes with a given property value + * @fdt: pointer to the device tree blob + * @startoffset: only find nodes after this offset + * @propname: property name to check + * @propval: property value to search for + * @proplen: length of the value in propval + * + * fdt_node_offset_by_prop_value() returns the offset of the first + * node after startoffset, which has a property named propname whose + * value is of length proplen and has value equal to propval; or if + * startoffset is -1, the very first such node in the tree. + * + * To iterate through all nodes matching the criterion, the following + * idiom can be used: + * offset = fdt_node_offset_by_prop_value(fdt, -1, propname, + * propval, proplen); + * while (offset != -FDT_ERR_NOTFOUND) { + * // other code here + * offset = fdt_node_offset_by_prop_value(fdt, offset, propname, + * propval, proplen); + * } + * + * Note the -1 in the first call to the function, if 0 is used here + * instead, the function will never locate the root node, even if it + * matches the criterion. + * + * returns: + * structure block offset of the located node (>= 0, >startoffset), + * on success + * -FDT_ERR_NOTFOUND, no node matching the criterion exists in the + * tree after startoffset + * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_node_offset_by_prop_value(const void *fdt, int startoffset, + const char *propname, + const void *propval, int proplen); + +/** + * fdt_node_offset_by_phandle - find the node with a given phandle + * @fdt: pointer to the device tree blob + * @phandle: phandle value + * + * fdt_node_offset_by_phandle() returns the offset of the node + * which has the given phandle value. If there is more than one node + * in the tree with the given phandle (an invalid tree), results are + * undefined. + * + * returns: + * structure block offset of the located node (>= 0), on success + * -FDT_ERR_NOTFOUND, no node with that phandle exists + * -FDT_ERR_BADPHANDLE, given phandle value was invalid (0 or -1) + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_node_offset_by_phandle(const void *fdt, uint32_t phandle); + +/** + * fdt_node_check_compatible: check a node's compatible property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of a tree node + * @compatible: string to match against + * + * + * fdt_node_check_compatible() returns 0 if the given node contains a + * 'compatible' property with the given string as one of its elements, + * it returns non-zero otherwise, or on error. + * + * returns: + * 0, if the node has a 'compatible' property listing the given string + * 1, if the node has a 'compatible' property, but it does not list + * the given string + * -FDT_ERR_NOTFOUND, if the given node has no 'compatible' property + * -FDT_ERR_BADOFFSET, if nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_node_check_compatible(const void *fdt, int nodeoffset, + const char *compatible); + +/** + * fdt_node_offset_by_compatible - find nodes with a given 'compatible' value + * @fdt: pointer to the device tree blob + * @startoffset: only find nodes after this offset + * @compatible: 'compatible' string to match against + * + * fdt_node_offset_by_compatible() returns the offset of the first + * node after startoffset, which has a 'compatible' property which + * lists the given compatible string; or if startoffset is -1, the + * very first such node in the tree. + * + * To iterate through all nodes matching the criterion, the following + * idiom can be used: + * offset = fdt_node_offset_by_compatible(fdt, -1, compatible); + * while (offset != -FDT_ERR_NOTFOUND) { + * // other code here + * offset = fdt_node_offset_by_compatible(fdt, offset, compatible); + * } + * + * Note the -1 in the first call to the function, if 0 is used here + * instead, the function will never locate the root node, even if it + * matches the criterion. + * + * returns: + * structure block offset of the located node (>= 0, >startoffset), + * on success + * -FDT_ERR_NOTFOUND, no node matching the criterion exists in the + * tree after startoffset + * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_node_offset_by_compatible(const void *fdt, int startoffset, + const char *compatible); + +/** + * fdt_stringlist_contains - check a string list property for a string + * @strlist: Property containing a list of strings to check + * @listlen: Length of property + * @str: String to search for + * + * This is a utility function provided for convenience. The list contains + * one or more strings, each terminated by \0, as is found in a device tree + * "compatible" property. + * + * @return: 1 if the string is found in the list, 0 not found, or invalid list + */ +int fdt_stringlist_contains(const char *strlist, int listlen, const char *str); + +/** + * fdt_stringlist_count - count the number of strings in a string list + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of a tree node + * @property: name of the property containing the string list + * @return: + * the number of strings in the given property + * -FDT_ERR_BADVALUE if the property value is not NUL-terminated + * -FDT_ERR_NOTFOUND if the property does not exist + */ +int fdt_stringlist_count(const void *fdt, int nodeoffset, const char *property); + +/** + * fdt_stringlist_search - find a string in a string list and return its index + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of a tree node + * @property: name of the property containing the string list + * @string: string to look up in the string list + * + * Note that it is possible for this function to succeed on property values + * that are not NUL-terminated. That's because the function will stop after + * finding the first occurrence of @string. This can for example happen with + * small-valued cell properties, such as #address-cells, when searching for + * the empty string. + * + * @return: + * the index of the string in the list of strings + * -FDT_ERR_BADVALUE if the property value is not NUL-terminated + * -FDT_ERR_NOTFOUND if the property does not exist or does not contain + * the given string + */ +int fdt_stringlist_search(const void *fdt, int nodeoffset, const char *property, + const char *string); + +/** + * fdt_stringlist_get() - obtain the string at a given index in a string list + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of a tree node + * @property: name of the property containing the string list + * @index: index of the string to return + * @lenp: return location for the string length or an error code on failure + * + * Note that this will successfully extract strings from properties with + * non-NUL-terminated values. For example on small-valued cell properties + * this function will return the empty string. + * + * If non-NULL, the length of the string (on success) or a negative error-code + * (on failure) will be stored in the integer pointer to by lenp. + * + * @return: + * A pointer to the string at the given index in the string list or NULL on + * failure. On success the length of the string will be stored in the memory + * location pointed to by the lenp parameter, if non-NULL. On failure one of + * the following negative error codes will be returned in the lenp parameter + * (if non-NULL): + * -FDT_ERR_BADVALUE if the property value is not NUL-terminated + * -FDT_ERR_NOTFOUND if the property does not exist + */ +const char *fdt_stringlist_get(const void *fdt, int nodeoffset, + const char *property, int index, + int *lenp); + +/**********************************************************************/ +/* Read-only functions (addressing related) */ +/**********************************************************************/ + +/** + * FDT_MAX_NCELLS - maximum value for #address-cells and #size-cells + * + * This is the maximum value for #address-cells, #size-cells and + * similar properties that will be processed by libfdt. IEE1275 + * requires that OF implementations handle values up to 4. + * Implementations may support larger values, but in practice higher + * values aren't used. + */ +#define FDT_MAX_NCELLS 4 + +/** + * fdt_address_cells - retrieve address size for a bus represented in the tree + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node to find the address size for + * + * When the node has a valid #address-cells property, returns its value. + * + * returns: + * 0 <= n < FDT_MAX_NCELLS, on success + * 2, if the node has no #address-cells property + * -FDT_ERR_BADNCELLS, if the node has a badly formatted or invalid + * #address-cells property + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_address_cells(const void *fdt, int nodeoffset); + +/** + * fdt_size_cells - retrieve address range size for a bus represented in the + * tree + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node to find the address range size for + * + * When the node has a valid #size-cells property, returns its value. + * + * returns: + * 0 <= n < FDT_MAX_NCELLS, on success + * 1, if the node has no #size-cells property + * -FDT_ERR_BADNCELLS, if the node has a badly formatted or invalid + * #size-cells property + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_size_cells(const void *fdt, int nodeoffset); + + +/**********************************************************************/ +/* Write-in-place functions */ +/**********************************************************************/ + +/** + * fdt_setprop_inplace_namelen_partial - change a property's value, + * but not its size + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @namelen: number of characters of name to consider + * @idx: index of the property to change in the array + * @val: pointer to data to replace the property value with + * @len: length of the property value + * + * Identical to fdt_setprop_inplace(), but modifies the given property + * starting from the given index, and using only the first characters + * of the name. It is useful when you want to manipulate only one value of + * an array and you have a string that doesn't end with \0. + */ +#ifndef SWIG /* Not available in Python */ +int fdt_setprop_inplace_namelen_partial(void *fdt, int nodeoffset, + const char *name, int namelen, + uint32_t idx, const void *val, + int len); +#endif + +/** + * fdt_setprop_inplace - change a property's value, but not its size + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: pointer to data to replace the property value with + * @len: length of the property value + * + * fdt_setprop_inplace() replaces the value of a given property with + * the data in val, of length len. This function cannot change the + * size of a property, and so will only work if len is equal to the + * current length of the property. + * + * This function will alter only the bytes in the blob which contain + * the given property value, and will not alter or move any other part + * of the tree. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, if len is not equal to the property's current length + * -FDT_ERR_NOTFOUND, node does not have the named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +#ifndef SWIG /* Not available in Python */ +int fdt_setprop_inplace(void *fdt, int nodeoffset, const char *name, + const void *val, int len); +#endif + +/** + * fdt_setprop_inplace_u32 - change the value of a 32-bit integer property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 32-bit integer value to replace the property with + * + * fdt_setprop_inplace_u32() replaces the value of a given property + * with the 32-bit integer value in val, converting val to big-endian + * if necessary. This function cannot change the size of a property, + * and so will only work if the property already exists and has length + * 4. + * + * This function will alter only the bytes in the blob which contain + * the given property value, and will not alter or move any other part + * of the tree. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, if the property's length is not equal to 4 + * -FDT_ERR_NOTFOUND, node does not have the named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_setprop_inplace_u32(void *fdt, int nodeoffset, + const char *name, uint32_t val) +{ + fdt32_t tmp = cpu_to_fdt32(val); + return fdt_setprop_inplace(fdt, nodeoffset, name, &tmp, sizeof(tmp)); +} + +/** + * fdt_setprop_inplace_u64 - change the value of a 64-bit integer property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 64-bit integer value to replace the property with + * + * fdt_setprop_inplace_u64() replaces the value of a given property + * with the 64-bit integer value in val, converting val to big-endian + * if necessary. This function cannot change the size of a property, + * and so will only work if the property already exists and has length + * 8. + * + * This function will alter only the bytes in the blob which contain + * the given property value, and will not alter or move any other part + * of the tree. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, if the property's length is not equal to 8 + * -FDT_ERR_NOTFOUND, node does not have the named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_setprop_inplace_u64(void *fdt, int nodeoffset, + const char *name, uint64_t val) +{ + fdt64_t tmp = cpu_to_fdt64(val); + return fdt_setprop_inplace(fdt, nodeoffset, name, &tmp, sizeof(tmp)); +} + +/** + * fdt_setprop_inplace_cell - change the value of a single-cell property + * + * This is an alternative name for fdt_setprop_inplace_u32() + */ +static inline int fdt_setprop_inplace_cell(void *fdt, int nodeoffset, + const char *name, uint32_t val) +{ + return fdt_setprop_inplace_u32(fdt, nodeoffset, name, val); +} + +/** + * fdt_nop_property - replace a property with nop tags + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to nop + * @name: name of the property to nop + * + * fdt_nop_property() will replace a given property's representation + * in the blob with FDT_NOP tags, effectively removing it from the + * tree. + * + * This function will alter only the bytes in the blob which contain + * the property, and will not alter or move any other part of the + * tree. + * + * returns: + * 0, on success + * -FDT_ERR_NOTFOUND, node does not have the named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_nop_property(void *fdt, int nodeoffset, const char *name); + +/** + * fdt_nop_node - replace a node (subtree) with nop tags + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node to nop + * + * fdt_nop_node() will replace a given node's representation in the + * blob, including all its subnodes, if any, with FDT_NOP tags, + * effectively removing it from the tree. + * + * This function will alter only the bytes in the blob which contain + * the node and its properties and subnodes, and will not alter or + * move any other part of the tree. + * + * returns: + * 0, on success + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_nop_node(void *fdt, int nodeoffset); + +/**********************************************************************/ +/* Sequential write functions */ +/**********************************************************************/ + +/* fdt_create_with_flags flags */ +#define FDT_CREATE_FLAG_NO_NAME_DEDUP 0x1 + /* FDT_CREATE_FLAG_NO_NAME_DEDUP: Do not try to de-duplicate property + * names in the fdt. This can result in faster creation times, but + * a larger fdt. */ + +#define FDT_CREATE_FLAGS_ALL (FDT_CREATE_FLAG_NO_NAME_DEDUP) + +/** + * fdt_create_with_flags - begin creation of a new fdt + * @fdt: pointer to memory allocated where fdt will be created + * @bufsize: size of the memory space at fdt + * @flags: a valid combination of FDT_CREATE_FLAG_ flags, or 0. + * + * fdt_create_with_flags() begins the process of creating a new fdt with + * the sequential write interface. + * + * fdt creation process must end with fdt_finished() to produce a valid fdt. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, bufsize is insufficient for a minimal fdt + * -FDT_ERR_BADFLAGS, flags is not valid + */ +int fdt_create_with_flags(void *buf, int bufsize, uint32_t flags); + +/** + * fdt_create - begin creation of a new fdt + * @fdt: pointer to memory allocated where fdt will be created + * @bufsize: size of the memory space at fdt + * + * fdt_create() is equivalent to fdt_create_with_flags() with flags=0. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, bufsize is insufficient for a minimal fdt + */ +int fdt_create(void *buf, int bufsize); + +int fdt_resize(void *fdt, void *buf, int bufsize); +int fdt_add_reservemap_entry(void *fdt, uint64_t addr, uint64_t size); +int fdt_finish_reservemap(void *fdt); +int fdt_begin_node(void *fdt, const char *name); +int fdt_property(void *fdt, const char *name, const void *val, int len); +static inline int fdt_property_u32(void *fdt, const char *name, uint32_t val) +{ + fdt32_t tmp = cpu_to_fdt32(val); + return fdt_property(fdt, name, &tmp, sizeof(tmp)); +} +static inline int fdt_property_u64(void *fdt, const char *name, uint64_t val) +{ + fdt64_t tmp = cpu_to_fdt64(val); + return fdt_property(fdt, name, &tmp, sizeof(tmp)); +} + +#ifndef SWIG /* Not available in Python */ +static inline int fdt_property_cell(void *fdt, const char *name, uint32_t val) +{ + return fdt_property_u32(fdt, name, val); +} +#endif + +/** + * fdt_property_placeholder - add a new property and return a ptr to its value + * + * @fdt: pointer to the device tree blob + * @name: name of property to add + * @len: length of property value in bytes + * @valp: returns a pointer to where where the value should be placed + * + * returns: + * 0, on success + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_NOSPACE, standard meanings + */ +int fdt_property_placeholder(void *fdt, const char *name, int len, void **valp); + +#define fdt_property_string(fdt, name, str) \ + fdt_property(fdt, name, str, strlen(str)+1) +int fdt_end_node(void *fdt); +int fdt_finish(void *fdt); + +/**********************************************************************/ +/* Read-write functions */ +/**********************************************************************/ + +int fdt_create_empty_tree(void *buf, int bufsize); +int fdt_open_into(const void *fdt, void *buf, int bufsize); +int fdt_pack(void *fdt); + +/** + * fdt_add_mem_rsv - add one memory reserve map entry + * @fdt: pointer to the device tree blob + * @address, @size: 64-bit values (native endian) + * + * Adds a reserve map entry to the given blob reserving a region at + * address address of length size. + * + * This function will insert data into the reserve map and will + * therefore change the indexes of some entries in the table. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new reservation entry + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_add_mem_rsv(void *fdt, uint64_t address, uint64_t size); + +/** + * fdt_del_mem_rsv - remove a memory reserve map entry + * @fdt: pointer to the device tree blob + * @n: entry to remove + * + * fdt_del_mem_rsv() removes the n-th memory reserve map entry from + * the blob. + * + * This function will delete data from the reservation table and will + * therefore change the indexes of some entries in the table. + * + * returns: + * 0, on success + * -FDT_ERR_NOTFOUND, there is no entry of the given index (i.e. there + * are less than n+1 reserve map entries) + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_del_mem_rsv(void *fdt, int n); + +/** + * fdt_set_name - change the name of a given node + * @fdt: pointer to the device tree blob + * @nodeoffset: structure block offset of a node + * @name: name to give the node + * + * fdt_set_name() replaces the name (including unit address, if any) + * of the given node with the given string. NOTE: this function can't + * efficiently check if the new name is unique amongst the given + * node's siblings; results are undefined if this function is invoked + * with a name equal to one of the given node's siblings. + * + * This function may insert or delete data from the blob, and will + * therefore change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob + * to contain the new name + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, standard meanings + */ +int fdt_set_name(void *fdt, int nodeoffset, const char *name); + +/** + * fdt_setprop - create or change a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: pointer to data to set the property value to + * @len: length of the property value + * + * fdt_setprop() sets the value of the named property in the given + * node to the given value and length, creating the property if it + * does not already exist. + * + * This function may insert or delete data from the blob, and will + * therefore change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_setprop(void *fdt, int nodeoffset, const char *name, + const void *val, int len); + +/** + * fdt_setprop_placeholder - allocate space for a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @len: length of the property value + * @prop_data: return pointer to property data + * + * fdt_setprop_placeholer() allocates the named property in the given node. + * If the property exists it is resized. In either case a pointer to the + * property data is returned. + * + * This function may insert or delete data from the blob, and will + * therefore change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_setprop_placeholder(void *fdt, int nodeoffset, const char *name, + int len, void **prop_data); + +/** + * fdt_setprop_u32 - set a property to a 32-bit integer + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 32-bit integer value for the property (native endian) + * + * fdt_setprop_u32() sets the value of the named property in the given + * node to the given 32-bit integer value (converting to big-endian if + * necessary), or creates a new property with that value if it does + * not already exist. + * + * This function may insert or delete data from the blob, and will + * therefore change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_setprop_u32(void *fdt, int nodeoffset, const char *name, + uint32_t val) +{ + fdt32_t tmp = cpu_to_fdt32(val); + return fdt_setprop(fdt, nodeoffset, name, &tmp, sizeof(tmp)); +} + +/** + * fdt_setprop_u64 - set a property to a 64-bit integer + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 64-bit integer value for the property (native endian) + * + * fdt_setprop_u64() sets the value of the named property in the given + * node to the given 64-bit integer value (converting to big-endian if + * necessary), or creates a new property with that value if it does + * not already exist. + * + * This function may insert or delete data from the blob, and will + * therefore change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_setprop_u64(void *fdt, int nodeoffset, const char *name, + uint64_t val) +{ + fdt64_t tmp = cpu_to_fdt64(val); + return fdt_setprop(fdt, nodeoffset, name, &tmp, sizeof(tmp)); +} + +/** + * fdt_setprop_cell - set a property to a single cell value + * + * This is an alternative name for fdt_setprop_u32() + */ +static inline int fdt_setprop_cell(void *fdt, int nodeoffset, const char *name, + uint32_t val) +{ + return fdt_setprop_u32(fdt, nodeoffset, name, val); +} + +/** + * fdt_setprop_string - set a property to a string value + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @str: string value for the property + * + * fdt_setprop_string() sets the value of the named property in the + * given node to the given string value (using the length of the + * string to determine the new length of the property), or creates a + * new property with that value if it does not already exist. + * + * This function may insert or delete data from the blob, and will + * therefore change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +#define fdt_setprop_string(fdt, nodeoffset, name, str) \ + fdt_setprop((fdt), (nodeoffset), (name), (str), strlen(str)+1) + + +/** + * fdt_setprop_empty - set a property to an empty value + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * + * fdt_setprop_empty() sets the value of the named property in the + * given node to an empty (zero length) value, or creates a new empty + * property if it does not already exist. + * + * This function may insert or delete data from the blob, and will + * therefore change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +#define fdt_setprop_empty(fdt, nodeoffset, name) \ + fdt_setprop((fdt), (nodeoffset), (name), NULL, 0) + +/** + * fdt_appendprop - append to or create a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to append to + * @val: pointer to data to append to the property value + * @len: length of the data to append to the property value + * + * fdt_appendprop() appends the value to the named property in the + * given node, creating the property if it does not already exist. + * + * This function may insert data into the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_appendprop(void *fdt, int nodeoffset, const char *name, + const void *val, int len); + +/** + * fdt_appendprop_u32 - append a 32-bit integer value to a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 32-bit integer value to append to the property (native endian) + * + * fdt_appendprop_u32() appends the given 32-bit integer value + * (converting to big-endian if necessary) to the value of the named + * property in the given node, or creates a new property with that + * value if it does not already exist. + * + * This function may insert data into the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_appendprop_u32(void *fdt, int nodeoffset, + const char *name, uint32_t val) +{ + fdt32_t tmp = cpu_to_fdt32(val); + return fdt_appendprop(fdt, nodeoffset, name, &tmp, sizeof(tmp)); +} + +/** + * fdt_appendprop_u64 - append a 64-bit integer value to a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 64-bit integer value to append to the property (native endian) + * + * fdt_appendprop_u64() appends the given 64-bit integer value + * (converting to big-endian if necessary) to the value of the named + * property in the given node, or creates a new property with that + * value if it does not already exist. + * + * This function may insert data into the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_appendprop_u64(void *fdt, int nodeoffset, + const char *name, uint64_t val) +{ + fdt64_t tmp = cpu_to_fdt64(val); + return fdt_appendprop(fdt, nodeoffset, name, &tmp, sizeof(tmp)); +} + +/** + * fdt_appendprop_cell - append a single cell value to a property + * + * This is an alternative name for fdt_appendprop_u32() + */ +static inline int fdt_appendprop_cell(void *fdt, int nodeoffset, + const char *name, uint32_t val) +{ + return fdt_appendprop_u32(fdt, nodeoffset, name, val); +} + +/** + * fdt_appendprop_string - append a string to a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @str: string value to append to the property + * + * fdt_appendprop_string() appends the given string to the value of + * the named property in the given node, or creates a new property + * with that value if it does not already exist. + * + * This function may insert data into the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +#define fdt_appendprop_string(fdt, nodeoffset, name, str) \ + fdt_appendprop((fdt), (nodeoffset), (name), (str), strlen(str)+1) + +/** + * fdt_appendprop_addrrange - append a address range property + * @fdt: pointer to the device tree blob + * @parent: offset of the parent node + * @nodeoffset: offset of the node to add a property at + * @name: name of property + * @addr: start address of a given range + * @size: size of a given range + * + * fdt_appendprop_addrrange() appends an address range value (start + * address and size) to the value of the named property in the given + * node, or creates a new property with that value if it does not + * already exist. + * If "name" is not specified, a default "reg" is used. + * Cell sizes are determined by parent's #address-cells and #size-cells. + * + * This function may insert data into the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADNCELLS, if the node has a badly formatted or invalid + * #address-cells property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADVALUE, addr or size doesn't fit to respective cells size + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain a new property + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_appendprop_addrrange(void *fdt, int parent, int nodeoffset, + const char *name, uint64_t addr, uint64_t size); + +/** + * fdt_delprop - delete a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to nop + * @name: name of the property to nop + * + * fdt_del_property() will delete the given property. + * + * This function will delete data from the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOTFOUND, node does not have the named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_delprop(void *fdt, int nodeoffset, const char *name); + +/** + * fdt_add_subnode_namelen - creates a new node based on substring + * @fdt: pointer to the device tree blob + * @parentoffset: structure block offset of a node + * @name: name of the subnode to locate + * @namelen: number of characters of name to consider + * + * Identical to fdt_add_subnode(), but use only the first namelen + * characters of name as the name of the new node. This is useful for + * creating subnodes based on a portion of a larger string, such as a + * full path. + */ +#ifndef SWIG /* Not available in Python */ +int fdt_add_subnode_namelen(void *fdt, int parentoffset, + const char *name, int namelen); +#endif + +/** + * fdt_add_subnode - creates a new node + * @fdt: pointer to the device tree blob + * @parentoffset: structure block offset of a node + * @name: name of the subnode to locate + * + * fdt_add_subnode() creates a new node as a subnode of the node at + * structure block offset parentoffset, with the given name (which + * should include the unit address, if any). + * + * This function will insert data into the blob, and will therefore + * change the offsets of some existing nodes. + + * returns: + * structure block offset of the created nodeequested subnode (>=0), on + * success + * -FDT_ERR_NOTFOUND, if the requested subnode does not exist + * -FDT_ERR_BADOFFSET, if parentoffset did not point to an FDT_BEGIN_NODE + * tag + * -FDT_ERR_EXISTS, if the node at parentoffset already has a subnode of + * the given name + * -FDT_ERR_NOSPACE, if there is insufficient free space in the + * blob to contain the new node + * -FDT_ERR_NOSPACE + * -FDT_ERR_BADLAYOUT + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings. + */ +int fdt_add_subnode(void *fdt, int parentoffset, const char *name); + +/** + * fdt_del_node - delete a node (subtree) + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node to nop + * + * fdt_del_node() will remove the given node, including all its + * subnodes if any, from the blob. + * + * This function will delete data from the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_del_node(void *fdt, int nodeoffset); + +/** + * fdt_overlay_apply - Applies a DT overlay on a base DT + * @fdt: pointer to the base device tree blob + * @fdto: pointer to the device tree overlay blob + * + * fdt_overlay_apply() will apply the given device tree overlay on the + * given base device tree. + * + * Expect the base device tree to be modified, even if the function + * returns an error. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there's not enough space in the base device tree + * -FDT_ERR_NOTFOUND, the overlay points to some inexistant nodes or + * properties in the base DT + * -FDT_ERR_BADPHANDLE, + * -FDT_ERR_BADOVERLAY, + * -FDT_ERR_NOPHANDLES, + * -FDT_ERR_INTERNAL, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADOFFSET, + * -FDT_ERR_BADPATH, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_overlay_apply(void *fdt, void *fdto); + +/**********************************************************************/ +/* Debugging / informational functions */ +/**********************************************************************/ + +const char *fdt_strerror(int errval); + +#ifdef __cplusplus +} +#endif + +#endif /* LIBFDT_H */ diff --git a/src/net/scripts/dtc/libfdt/libfdt_env.h b/src/net/scripts/dtc/libfdt/libfdt_env.h new file mode 100644 index 0000000..73b6d40 --- /dev/null +++ b/src/net/scripts/dtc/libfdt/libfdt_env.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) */ +#ifndef LIBFDT_ENV_H +#define LIBFDT_ENV_H +/* + * libfdt - Flat Device Tree manipulation + * Copyright (C) 2006 David Gibson, IBM Corporation. + * Copyright 2012 Kim Phillips, Freescale Semiconductor. + */ + +#include <stdbool.h> +#include <stddef.h> +#include <stdint.h> +#include <stdlib.h> +#include <string.h> +#include <limits.h> + +#ifdef __CHECKER__ +#define FDT_FORCE __attribute__((force)) +#define FDT_BITWISE __attribute__((bitwise)) +#else +#define FDT_FORCE +#define FDT_BITWISE +#endif + +typedef uint16_t FDT_BITWISE fdt16_t; +typedef uint32_t FDT_BITWISE fdt32_t; +typedef uint64_t FDT_BITWISE fdt64_t; + +#define EXTRACT_BYTE(x, n) ((unsigned long long)((uint8_t *)&x)[n]) +#define CPU_TO_FDT16(x) ((EXTRACT_BYTE(x, 0) << 8) | EXTRACT_BYTE(x, 1)) +#define CPU_TO_FDT32(x) ((EXTRACT_BYTE(x, 0) << 24) | (EXTRACT_BYTE(x, 1) << 16) | \ + (EXTRACT_BYTE(x, 2) << 8) | EXTRACT_BYTE(x, 3)) +#define CPU_TO_FDT64(x) ((EXTRACT_BYTE(x, 0) << 56) | (EXTRACT_BYTE(x, 1) << 48) | \ + (EXTRACT_BYTE(x, 2) << 40) | (EXTRACT_BYTE(x, 3) << 32) | \ + (EXTRACT_BYTE(x, 4) << 24) | (EXTRACT_BYTE(x, 5) << 16) | \ + (EXTRACT_BYTE(x, 6) << 8) | EXTRACT_BYTE(x, 7)) + +static inline uint16_t fdt16_to_cpu(fdt16_t x) +{ + return (FDT_FORCE uint16_t)CPU_TO_FDT16(x); +} +static inline fdt16_t cpu_to_fdt16(uint16_t x) +{ + return (FDT_FORCE fdt16_t)CPU_TO_FDT16(x); +} + +static inline uint32_t fdt32_to_cpu(fdt32_t x) +{ + return (FDT_FORCE uint32_t)CPU_TO_FDT32(x); +} +static inline fdt32_t cpu_to_fdt32(uint32_t x) +{ + return (FDT_FORCE fdt32_t)CPU_TO_FDT32(x); +} + +static inline uint64_t fdt64_to_cpu(fdt64_t x) +{ + return (FDT_FORCE uint64_t)CPU_TO_FDT64(x); +} +static inline fdt64_t cpu_to_fdt64(uint64_t x) +{ + return (FDT_FORCE fdt64_t)CPU_TO_FDT64(x); +} +#undef CPU_TO_FDT64 +#undef CPU_TO_FDT32 +#undef CPU_TO_FDT16 +#undef EXTRACT_BYTE + +#ifdef __APPLE__ +#include <AvailabilityMacros.h> + +/* strnlen() is not available on Mac OS < 10.7 */ +# if !defined(MAC_OS_X_VERSION_10_7) || (MAC_OS_X_VERSION_MAX_ALLOWED < \ + MAC_OS_X_VERSION_10_7) + +#define strnlen fdt_strnlen + +/* + * fdt_strnlen: returns the length of a string or max_count - which ever is + * smallest. + * Input 1 string: the string whose size is to be determined + * Input 2 max_count: the maximum value returned by this function + * Output: length of the string or max_count (the smallest of the two) + */ +static inline size_t fdt_strnlen(const char *string, size_t max_count) +{ + const char *p = memchr(string, 0, max_count); + return p ? p - string : max_count; +} + +#endif /* !defined(MAC_OS_X_VERSION_10_7) || (MAC_OS_X_VERSION_MAX_ALLOWED < + MAC_OS_X_VERSION_10_7) */ + +#endif /* __APPLE__ */ + +#endif /* LIBFDT_ENV_H */ diff --git a/src/net/scripts/dtc/libfdt/libfdt_internal.h b/src/net/scripts/dtc/libfdt/libfdt_internal.h new file mode 100644 index 0000000..d4e0bd4 --- /dev/null +++ b/src/net/scripts/dtc/libfdt/libfdt_internal.h @@ -0,0 +1,173 @@ +/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) */ +#ifndef LIBFDT_INTERNAL_H +#define LIBFDT_INTERNAL_H +/* + * libfdt - Flat Device Tree manipulation + * Copyright (C) 2006 David Gibson, IBM Corporation. + */ +#include <fdt.h> + +#define FDT_ALIGN(x, a) (((x) + (a) - 1) & ~((a) - 1)) +#define FDT_TAGALIGN(x) (FDT_ALIGN((x), FDT_TAGSIZE)) + +int32_t fdt_ro_probe_(const void *fdt); +#define FDT_RO_PROBE(fdt) \ + { \ + int32_t totalsize_; \ + if ((totalsize_ = fdt_ro_probe_(fdt)) < 0) \ + return totalsize_; \ + } + +int fdt_check_node_offset_(const void *fdt, int offset); +int fdt_check_prop_offset_(const void *fdt, int offset); +const char *fdt_find_string_(const char *strtab, int tabsize, const char *s); +int fdt_node_end_offset_(void *fdt, int nodeoffset); + +static inline const void *fdt_offset_ptr_(const void *fdt, int offset) +{ + return (const char *)fdt + fdt_off_dt_struct(fdt) + offset; +} + +static inline void *fdt_offset_ptr_w_(void *fdt, int offset) +{ + return (void *)(uintptr_t)fdt_offset_ptr_(fdt, offset); +} + +static inline const struct fdt_reserve_entry *fdt_mem_rsv_(const void *fdt, int n) +{ + const struct fdt_reserve_entry *rsv_table = + (const struct fdt_reserve_entry *) + ((const char *)fdt + fdt_off_mem_rsvmap(fdt)); + + return rsv_table + n; +} +static inline struct fdt_reserve_entry *fdt_mem_rsv_w_(void *fdt, int n) +{ + return (void *)(uintptr_t)fdt_mem_rsv_(fdt, n); +} + +#define FDT_SW_MAGIC (~FDT_MAGIC) + +/**********************************************************************/ +/* Checking controls */ +/**********************************************************************/ + +#ifndef FDT_ASSUME_MASK +#define FDT_ASSUME_MASK 0 +#endif + +/* + * Defines assumptions which can be enabled. Each of these can be enabled + * individually. For maximum safety, don't enable any assumptions! + * + * For minimal code size and no safety, use ASSUME_PERFECT at your own risk. + * You should have another method of validating the device tree, such as a + * signature or hash check before using libfdt. + * + * For situations where security is not a concern it may be safe to enable + * ASSUME_SANE. + */ +enum { + /* + * This does essentially no checks. Only the latest device-tree + * version is correctly handled. Inconsistencies or errors in the device + * tree may cause undefined behaviour or crashes. Invalid parameters + * passed to libfdt may do the same. + * + * If an error occurs when modifying the tree it may leave the tree in + * an intermediate (but valid) state. As an example, adding a property + * where there is insufficient space may result in the property name + * being added to the string table even though the property itself is + * not added to the struct section. + * + * Only use this if you have a fully validated device tree with + * the latest supported version and wish to minimise code size. + */ + ASSUME_PERFECT = 0xff, + + /* + * This assumes that the device tree is sane. i.e. header metadata + * and basic hierarchy are correct. + * + * With this assumption enabled, normal device trees produced by libfdt + * and the compiler should be handled safely. Malicious device trees and + * complete garbage may cause libfdt to behave badly or crash. Truncated + * device trees (e.g. those only partially loaded) can also cause + * problems. + * + * Note: Only checks that relate exclusively to the device tree itself + * (not the parameters passed to libfdt) are disabled by this + * assumption. This includes checking headers, tags and the like. + */ + ASSUME_VALID_DTB = 1 << 0, + + /* + * This builds on ASSUME_VALID_DTB and further assumes that libfdt + * functions are called with valid parameters, i.e. not trigger + * FDT_ERR_BADOFFSET or offsets that are out of bounds. It disables any + * extensive checking of parameters and the device tree, making various + * assumptions about correctness. + * + * It doesn't make sense to enable this assumption unless + * ASSUME_VALID_DTB is also enabled. + */ + ASSUME_VALID_INPUT = 1 << 1, + + /* + * This disables checks for device-tree version and removes all code + * which handles older versions. + * + * Only enable this if you know you have a device tree with the latest + * version. + */ + ASSUME_LATEST = 1 << 2, + + /* + * This assumes that it is OK for a failed addition to the device tree, + * due to lack of space or some other problem, to skip any rollback + * steps (such as dropping the property name from the string table). + * This is safe to enable in most circumstances, even though it may + * leave the tree in a sub-optimal state. + */ + ASSUME_NO_ROLLBACK = 1 << 3, + + /* + * This assumes that the device tree components appear in a 'convenient' + * order, i.e. the memory reservation block first, then the structure + * block and finally the string block. + * + * This order is not specified by the device-tree specification, + * but is expected by libfdt. The device-tree compiler always created + * device trees with this order. + * + * This assumption disables a check in fdt_open_into() and removes the + * ability to fix the problem there. This is safe if you know that the + * device tree is correctly ordered. See fdt_blocks_misordered_(). + */ + ASSUME_LIBFDT_ORDER = 1 << 4, + + /* + * This assumes that libfdt itself does not have any internal bugs. It + * drops certain checks that should never be needed unless libfdt has an + * undiscovered bug. + * + * This can generally be considered safe to enable. + */ + ASSUME_LIBFDT_FLAWLESS = 1 << 5, +}; + +/** + * can_assume_() - check if a particular assumption is enabled + * + * @mask: Mask to check (ASSUME_...) + * @return true if that assumption is enabled, else false + */ +static inline bool can_assume_(int mask) +{ + return FDT_ASSUME_MASK & mask; +} + +/** helper macros for checking assumptions */ +#define can_assume(_assume) can_assume_(ASSUME_ ## _assume) + +#endif /* LIBFDT_INTERNAL_H */ diff --git a/src/net/scripts/dtc/livetree.c b/src/net/scripts/dtc/livetree.c new file mode 100644 index 0000000..032df58 --- /dev/null +++ b/src/net/scripts/dtc/livetree.c @@ -0,0 +1,1032 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (C) Copyright David Gibson <dwg@au1.ibm.com>, IBM Corporation. 2005. + */ + +#include "dtc.h" +#include "srcpos.h" + +/* + * Tree building functions + */ + +void add_label(struct label **labels, char *label) +{ + struct label *new; + + /* Make sure the label isn't already there */ + for_each_label_withdel(*labels, new) + if (streq(new->label, label)) { + new->deleted = 0; + return; + } + + new = xmalloc(sizeof(*new)); + memset(new, 0, sizeof(*new)); + new->label = label; + new->next = *labels; + *labels = new; +} + +void delete_labels(struct label **labels) +{ + struct label *label; + + for_each_label(*labels, label) + label->deleted = 1; +} + +struct property *build_property(char *name, struct data val, + struct srcpos *srcpos) +{ + struct property *new = xmalloc(sizeof(*new)); + + memset(new, 0, sizeof(*new)); + + new->name = name; + new->val = val; + new->srcpos = srcpos_copy(srcpos); + + return new; +} + +struct property *build_property_delete(char *name) +{ + struct property *new = xmalloc(sizeof(*new)); + + memset(new, 0, sizeof(*new)); + + new->name = name; + new->deleted = 1; + + return new; +} + +struct property *chain_property(struct property *first, struct property *list) +{ + assert(first->next == NULL); + + first->next = list; + return first; +} + +struct property *reverse_properties(struct property *first) +{ + struct property *p = first; + struct property *head = NULL; + struct property *next; + + while (p) { + next = p->next; + p->next = head; + head = p; + p = next; + } + return head; +} + +struct node *build_node(struct property *proplist, struct node *children, + struct srcpos *srcpos) +{ + struct node *new = xmalloc(sizeof(*new)); + struct node *child; + + memset(new, 0, sizeof(*new)); + + new->proplist = reverse_properties(proplist); + new->children = children; + new->srcpos = srcpos_copy(srcpos); + + for_each_child(new, child) { + child->parent = new; + } + + return new; +} + +struct node *build_node_delete(struct srcpos *srcpos) +{ + struct node *new = xmalloc(sizeof(*new)); + + memset(new, 0, sizeof(*new)); + + new->deleted = 1; + new->srcpos = srcpos_copy(srcpos); + + return new; +} + +struct node *name_node(struct node *node, char *name) +{ + assert(node->name == NULL); + + node->name = name; + + return node; +} + +struct node *omit_node_if_unused(struct node *node) +{ + node->omit_if_unused = 1; + + return node; +} + +struct node *reference_node(struct node *node) +{ + node->is_referenced = 1; + + return node; +} + +struct node *merge_nodes(struct node *old_node, struct node *new_node) +{ + struct property *new_prop, *old_prop; + struct node *new_child, *old_child; + struct label *l; + + old_node->deleted = 0; + + /* Add new node labels to old node */ + for_each_label_withdel(new_node->labels, l) + add_label(&old_node->labels, l->label); + + /* Move properties from the new node to the old node. If there + * is a collision, replace the old value with the new */ + while (new_node->proplist) { + /* Pop the property off the list */ + new_prop = new_node->proplist; + new_node->proplist = new_prop->next; + new_prop->next = NULL; + + if (new_prop->deleted) { + delete_property_by_name(old_node, new_prop->name); + free(new_prop); + continue; + } + + /* Look for a collision, set new value if there is */ + for_each_property_withdel(old_node, old_prop) { + if (streq(old_prop->name, new_prop->name)) { + /* Add new labels to old property */ + for_each_label_withdel(new_prop->labels, l) + add_label(&old_prop->labels, l->label); + + old_prop->val = new_prop->val; + old_prop->deleted = 0; + free(old_prop->srcpos); + old_prop->srcpos = new_prop->srcpos; + free(new_prop); + new_prop = NULL; + break; + } + } + + /* if no collision occurred, add property to the old node. */ + if (new_prop) + add_property(old_node, new_prop); + } + + /* Move the override child nodes into the primary node. If + * there is a collision, then merge the nodes. */ + while (new_node->children) { + /* Pop the child node off the list */ + new_child = new_node->children; + new_node->children = new_child->next_sibling; + new_child->parent = NULL; + new_child->next_sibling = NULL; + + if (new_child->deleted) { + delete_node_by_name(old_node, new_child->name); + free(new_child); + continue; + } + + /* Search for a collision. Merge if there is */ + for_each_child_withdel(old_node, old_child) { + if (streq(old_child->name, new_child->name)) { + merge_nodes(old_child, new_child); + new_child = NULL; + break; + } + } + + /* if no collision occurred, add child to the old node. */ + if (new_child) + add_child(old_node, new_child); + } + + old_node->srcpos = srcpos_extend(old_node->srcpos, new_node->srcpos); + + /* The new node contents are now merged into the old node. Free + * the new node. */ + free(new_node); + + return old_node; +} + +struct node * add_orphan_node(struct node *dt, struct node *new_node, char *ref) +{ + static unsigned int next_orphan_fragment = 0; + struct node *node; + struct property *p; + struct data d = empty_data; + char *name; + + if (ref[0] == '/') { + d = data_add_marker(d, TYPE_STRING, ref); + d = data_append_data(d, ref, strlen(ref) + 1); + + p = build_property("target-path", d, NULL); + } else { + d = data_add_marker(d, REF_PHANDLE, ref); + d = data_append_integer(d, 0xffffffff, 32); + + p = build_property("target", d, NULL); + } + + xasprintf(&name, "fragment@%u", + next_orphan_fragment++); + name_node(new_node, "__overlay__"); + node = build_node(p, new_node, NULL); + name_node(node, name); + + add_child(dt, node); + return dt; +} + +struct node *chain_node(struct node *first, struct node *list) +{ + assert(first->next_sibling == NULL); + + first->next_sibling = list; + return first; +} + +void add_property(struct node *node, struct property *prop) +{ + struct property **p; + + prop->next = NULL; + + p = &node->proplist; + while (*p) + p = &((*p)->next); + + *p = prop; +} + +void delete_property_by_name(struct node *node, char *name) +{ + struct property *prop = node->proplist; + + while (prop) { + if (streq(prop->name, name)) { + delete_property(prop); + return; + } + prop = prop->next; + } +} + +void delete_property(struct property *prop) +{ + prop->deleted = 1; + delete_labels(&prop->labels); +} + +void add_child(struct node *parent, struct node *child) +{ + struct node **p; + + child->next_sibling = NULL; + child->parent = parent; + + p = &parent->children; + while (*p) + p = &((*p)->next_sibling); + + *p = child; +} + +void delete_node_by_name(struct node *parent, char *name) +{ + struct node *node = parent->children; + + while (node) { + if (streq(node->name, name)) { + delete_node(node); + return; + } + node = node->next_sibling; + } +} + +void delete_node(struct node *node) +{ + struct property *prop; + struct node *child; + + node->deleted = 1; + for_each_child(node, child) + delete_node(child); + for_each_property(node, prop) + delete_property(prop); + delete_labels(&node->labels); +} + +void append_to_property(struct node *node, + char *name, const void *data, int len, + enum markertype type) +{ + struct data d; + struct property *p; + + p = get_property(node, name); + if (p) { + d = data_add_marker(p->val, type, name); + d = data_append_data(d, data, len); + p->val = d; + } else { + d = data_add_marker(empty_data, type, name); + d = data_append_data(d, data, len); + p = build_property(name, d, NULL); + add_property(node, p); + } +} + +struct reserve_info *build_reserve_entry(uint64_t address, uint64_t size) +{ + struct reserve_info *new = xmalloc(sizeof(*new)); + + memset(new, 0, sizeof(*new)); + + new->address = address; + new->size = size; + + return new; +} + +struct reserve_info *chain_reserve_entry(struct reserve_info *first, + struct reserve_info *list) +{ + assert(first->next == NULL); + + first->next = list; + return first; +} + +struct reserve_info *add_reserve_entry(struct reserve_info *list, + struct reserve_info *new) +{ + struct reserve_info *last; + + new->next = NULL; + + if (! list) + return new; + + for (last = list; last->next; last = last->next) + ; + + last->next = new; + + return list; +} + +struct dt_info *build_dt_info(unsigned int dtsflags, + struct reserve_info *reservelist, + struct node *tree, uint32_t boot_cpuid_phys) +{ + struct dt_info *dti; + + dti = xmalloc(sizeof(*dti)); + dti->dtsflags = dtsflags; + dti->reservelist = reservelist; + dti->dt = tree; + dti->boot_cpuid_phys = boot_cpuid_phys; + + return dti; +} + +/* + * Tree accessor functions + */ + +const char *get_unitname(struct node *node) +{ + if (node->name[node->basenamelen] == '\0') + return ""; + else + return node->name + node->basenamelen + 1; +} + +struct property *get_property(struct node *node, const char *propname) +{ + struct property *prop; + + for_each_property(node, prop) + if (streq(prop->name, propname)) + return prop; + + return NULL; +} + +cell_t propval_cell(struct property *prop) +{ + assert(prop->val.len == sizeof(cell_t)); + return fdt32_to_cpu(*((fdt32_t *)prop->val.val)); +} + +cell_t propval_cell_n(struct property *prop, int n) +{ + assert(prop->val.len / sizeof(cell_t) >= n); + return fdt32_to_cpu(*((fdt32_t *)prop->val.val + n)); +} + +struct property *get_property_by_label(struct node *tree, const char *label, + struct node **node) +{ + struct property *prop; + struct node *c; + + *node = tree; + + for_each_property(tree, prop) { + struct label *l; + + for_each_label(prop->labels, l) + if (streq(l->label, label)) + return prop; + } + + for_each_child(tree, c) { + prop = get_property_by_label(c, label, node); + if (prop) + return prop; + } + + *node = NULL; + return NULL; +} + +struct marker *get_marker_label(struct node *tree, const char *label, + struct node **node, struct property **prop) +{ + struct marker *m; + struct property *p; + struct node *c; + + *node = tree; + + for_each_property(tree, p) { + *prop = p; + m = p->val.markers; + for_each_marker_of_type(m, LABEL) + if (streq(m->ref, label)) + return m; + } + + for_each_child(tree, c) { + m = get_marker_label(c, label, node, prop); + if (m) + return m; + } + + *prop = NULL; + *node = NULL; + return NULL; +} + +struct node *get_subnode(struct node *node, const char *nodename) +{ + struct node *child; + + for_each_child(node, child) + if (streq(child->name, nodename)) + return child; + + return NULL; +} + +struct node *get_node_by_path(struct node *tree, const char *path) +{ + const char *p; + struct node *child; + + if (!path || ! (*path)) { + if (tree->deleted) + return NULL; + return tree; + } + + while (path[0] == '/') + path++; + + p = strchr(path, '/'); + + for_each_child(tree, child) { + if (p && strprefixeq(path, p - path, child->name)) + return get_node_by_path(child, p+1); + else if (!p && streq(path, child->name)) + return child; + } + + return NULL; +} + +struct node *get_node_by_label(struct node *tree, const char *label) +{ + struct node *child, *node; + struct label *l; + + assert(label && (strlen(label) > 0)); + + for_each_label(tree->labels, l) + if (streq(l->label, label)) + return tree; + + for_each_child(tree, child) { + node = get_node_by_label(child, label); + if (node) + return node; + } + + return NULL; +} + +struct node *get_node_by_phandle(struct node *tree, cell_t phandle) +{ + struct node *child, *node; + + if ((phandle == 0) || (phandle == -1)) { + assert(generate_fixups); + return NULL; + } + + if (tree->phandle == phandle) { + if (tree->deleted) + return NULL; + return tree; + } + + for_each_child(tree, child) { + node = get_node_by_phandle(child, phandle); + if (node) + return node; + } + + return NULL; +} + +struct node *get_node_by_ref(struct node *tree, const char *ref) +{ + if (streq(ref, "/")) + return tree; + else if (ref[0] == '/') + return get_node_by_path(tree, ref); + else + return get_node_by_label(tree, ref); +} + +cell_t get_node_phandle(struct node *root, struct node *node) +{ + static cell_t phandle = 1; /* FIXME: ick, static local */ + struct data d = empty_data; + + if ((node->phandle != 0) && (node->phandle != -1)) + return node->phandle; + + while (get_node_by_phandle(root, phandle)) + phandle++; + + node->phandle = phandle; + + d = data_add_marker(d, TYPE_UINT32, NULL); + d = data_append_cell(d, phandle); + + if (!get_property(node, "linux,phandle") + && (phandle_format & PHANDLE_LEGACY)) + add_property(node, build_property("linux,phandle", d, NULL)); + + if (!get_property(node, "phandle") + && (phandle_format & PHANDLE_EPAPR)) + add_property(node, build_property("phandle", d, NULL)); + + /* If the node *does* have a phandle property, we must + * be dealing with a self-referencing phandle, which will be + * fixed up momentarily in the caller */ + + return node->phandle; +} + +uint32_t guess_boot_cpuid(struct node *tree) +{ + struct node *cpus, *bootcpu; + struct property *reg; + + cpus = get_node_by_path(tree, "/cpus"); + if (!cpus) + return 0; + + + bootcpu = cpus->children; + if (!bootcpu) + return 0; + + reg = get_property(bootcpu, "reg"); + if (!reg || (reg->val.len != sizeof(uint32_t))) + return 0; + + /* FIXME: Sanity check node? */ + + return propval_cell(reg); +} + +static int cmp_reserve_info(const void *ax, const void *bx) +{ + const struct reserve_info *a, *b; + + a = *((const struct reserve_info * const *)ax); + b = *((const struct reserve_info * const *)bx); + + if (a->address < b->address) + return -1; + else if (a->address > b->address) + return 1; + else if (a->size < b->size) + return -1; + else if (a->size > b->size) + return 1; + else + return 0; +} + +static void sort_reserve_entries(struct dt_info *dti) +{ + struct reserve_info *ri, **tbl; + int n = 0, i = 0; + + for (ri = dti->reservelist; + ri; + ri = ri->next) + n++; + + if (n == 0) + return; + + tbl = xmalloc(n * sizeof(*tbl)); + + for (ri = dti->reservelist; + ri; + ri = ri->next) + tbl[i++] = ri; + + qsort(tbl, n, sizeof(*tbl), cmp_reserve_info); + + dti->reservelist = tbl[0]; + for (i = 0; i < (n-1); i++) + tbl[i]->next = tbl[i+1]; + tbl[n-1]->next = NULL; + + free(tbl); +} + +static int cmp_prop(const void *ax, const void *bx) +{ + const struct property *a, *b; + + a = *((const struct property * const *)ax); + b = *((const struct property * const *)bx); + + return strcmp(a->name, b->name); +} + +static void sort_properties(struct node *node) +{ + int n = 0, i = 0; + struct property *prop, **tbl; + + for_each_property_withdel(node, prop) + n++; + + if (n == 0) + return; + + tbl = xmalloc(n * sizeof(*tbl)); + + for_each_property_withdel(node, prop) + tbl[i++] = prop; + + qsort(tbl, n, sizeof(*tbl), cmp_prop); + + node->proplist = tbl[0]; + for (i = 0; i < (n-1); i++) + tbl[i]->next = tbl[i+1]; + tbl[n-1]->next = NULL; + + free(tbl); +} + +static int cmp_subnode(const void *ax, const void *bx) +{ + const struct node *a, *b; + + a = *((const struct node * const *)ax); + b = *((const struct node * const *)bx); + + return strcmp(a->name, b->name); +} + +static void sort_subnodes(struct node *node) +{ + int n = 0, i = 0; + struct node *subnode, **tbl; + + for_each_child_withdel(node, subnode) + n++; + + if (n == 0) + return; + + tbl = xmalloc(n * sizeof(*tbl)); + + for_each_child_withdel(node, subnode) + tbl[i++] = subnode; + + qsort(tbl, n, sizeof(*tbl), cmp_subnode); + + node->children = tbl[0]; + for (i = 0; i < (n-1); i++) + tbl[i]->next_sibling = tbl[i+1]; + tbl[n-1]->next_sibling = NULL; + + free(tbl); +} + +static void sort_node(struct node *node) +{ + struct node *c; + + sort_properties(node); + sort_subnodes(node); + for_each_child_withdel(node, c) + sort_node(c); +} + +void sort_tree(struct dt_info *dti) +{ + sort_reserve_entries(dti); + sort_node(dti->dt); +} + +/* utility helper to avoid code duplication */ +static struct node *build_and_name_child_node(struct node *parent, char *name) +{ + struct node *node; + + node = build_node(NULL, NULL, NULL); + name_node(node, xstrdup(name)); + add_child(parent, node); + + return node; +} + +static struct node *build_root_node(struct node *dt, char *name) +{ + struct node *an; + + an = get_subnode(dt, name); + if (!an) + an = build_and_name_child_node(dt, name); + + if (!an) + die("Could not build root node /%s\n", name); + + return an; +} + +static bool any_label_tree(struct dt_info *dti, struct node *node) +{ + struct node *c; + + if (node->labels) + return true; + + for_each_child(node, c) + if (any_label_tree(dti, c)) + return true; + + return false; +} + +static void generate_label_tree_internal(struct dt_info *dti, + struct node *an, struct node *node, + bool allocph) +{ + struct node *dt = dti->dt; + struct node *c; + struct property *p; + struct label *l; + + /* if there are labels */ + if (node->labels) { + + /* now add the label in the node */ + for_each_label(node->labels, l) { + + /* check whether the label already exists */ + p = get_property(an, l->label); + if (p) { + fprintf(stderr, "WARNING: label %s already" + " exists in /%s", l->label, + an->name); + continue; + } + + /* insert it */ + p = build_property(l->label, + data_copy_escape_string(node->fullpath, + strlen(node->fullpath)), + NULL); + add_property(an, p); + } + + /* force allocation of a phandle for this node */ + if (allocph) + (void)get_node_phandle(dt, node); + } + + for_each_child(node, c) + generate_label_tree_internal(dti, an, c, allocph); +} + +static bool any_fixup_tree(struct dt_info *dti, struct node *node) +{ + struct node *c; + struct property *prop; + struct marker *m; + + for_each_property(node, prop) { + m = prop->val.markers; + for_each_marker_of_type(m, REF_PHANDLE) { + if (!get_node_by_ref(dti->dt, m->ref)) + return true; + } + } + + for_each_child(node, c) { + if (any_fixup_tree(dti, c)) + return true; + } + + return false; +} + +static void add_fixup_entry(struct dt_info *dti, struct node *fn, + struct node *node, struct property *prop, + struct marker *m) +{ + char *entry; + + /* m->ref can only be a REF_PHANDLE, but check anyway */ + assert(m->type == REF_PHANDLE); + + /* there shouldn't be any ':' in the arguments */ + if (strchr(node->fullpath, ':') || strchr(prop->name, ':')) + die("arguments should not contain ':'\n"); + + xasprintf(&entry, "%s:%s:%u", + node->fullpath, prop->name, m->offset); + append_to_property(fn, m->ref, entry, strlen(entry) + 1, TYPE_STRING); + + free(entry); +} + +static void generate_fixups_tree_internal(struct dt_info *dti, + struct node *fn, + struct node *node) +{ + struct node *dt = dti->dt; + struct node *c; + struct property *prop; + struct marker *m; + struct node *refnode; + + for_each_property(node, prop) { + m = prop->val.markers; + for_each_marker_of_type(m, REF_PHANDLE) { + refnode = get_node_by_ref(dt, m->ref); + if (!refnode) + add_fixup_entry(dti, fn, node, prop, m); + } + } + + for_each_child(node, c) + generate_fixups_tree_internal(dti, fn, c); +} + +static bool any_local_fixup_tree(struct dt_info *dti, struct node *node) +{ + struct node *c; + struct property *prop; + struct marker *m; + + for_each_property(node, prop) { + m = prop->val.markers; + for_each_marker_of_type(m, REF_PHANDLE) { + if (get_node_by_ref(dti->dt, m->ref)) + return true; + } + } + + for_each_child(node, c) { + if (any_local_fixup_tree(dti, c)) + return true; + } + + return false; +} + +static void add_local_fixup_entry(struct dt_info *dti, + struct node *lfn, struct node *node, + struct property *prop, struct marker *m, + struct node *refnode) +{ + struct node *wn, *nwn; /* local fixup node, walk node, new */ + fdt32_t value_32; + char **compp; + int i, depth; + + /* walk back retrieving depth */ + depth = 0; + for (wn = node; wn; wn = wn->parent) + depth++; + + /* allocate name array */ + compp = xmalloc(sizeof(*compp) * depth); + + /* store names in the array */ + for (wn = node, i = depth - 1; wn; wn = wn->parent, i--) + compp[i] = wn->name; + + /* walk the path components creating nodes if they don't exist */ + for (wn = lfn, i = 1; i < depth; i++, wn = nwn) { + /* if no node exists, create it */ + nwn = get_subnode(wn, compp[i]); + if (!nwn) + nwn = build_and_name_child_node(wn, compp[i]); + } + + free(compp); + + value_32 = cpu_to_fdt32(m->offset); + append_to_property(wn, prop->name, &value_32, sizeof(value_32), TYPE_UINT32); +} + +static void generate_local_fixups_tree_internal(struct dt_info *dti, + struct node *lfn, + struct node *node) +{ + struct node *dt = dti->dt; + struct node *c; + struct property *prop; + struct marker *m; + struct node *refnode; + + for_each_property(node, prop) { + m = prop->val.markers; + for_each_marker_of_type(m, REF_PHANDLE) { + refnode = get_node_by_ref(dt, m->ref); + if (refnode) + add_local_fixup_entry(dti, lfn, node, prop, m, refnode); + } + } + + for_each_child(node, c) + generate_local_fixups_tree_internal(dti, lfn, c); +} + +void generate_label_tree(struct dt_info *dti, char *name, bool allocph) +{ + if (!any_label_tree(dti, dti->dt)) + return; + generate_label_tree_internal(dti, build_root_node(dti->dt, name), + dti->dt, allocph); +} + +void generate_fixups_tree(struct dt_info *dti, char *name) +{ + if (!any_fixup_tree(dti, dti->dt)) + return; + generate_fixups_tree_internal(dti, build_root_node(dti->dt, name), + dti->dt); +} + +void generate_local_fixups_tree(struct dt_info *dti, char *name) +{ + if (!any_local_fixup_tree(dti, dti->dt)) + return; + generate_local_fixups_tree_internal(dti, build_root_node(dti->dt, name), + dti->dt); +} diff --git a/src/net/scripts/dtc/srcpos.c b/src/net/scripts/dtc/srcpos.c new file mode 100644 index 0000000..f5205fb --- /dev/null +++ b/src/net/scripts/dtc/srcpos.c @@ -0,0 +1,406 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2007 Jon Loeliger, Freescale Semiconductor, Inc. + */ + +#define _GNU_SOURCE + +#include <stdio.h> + +#include "dtc.h" +#include "srcpos.h" + +/* A node in our list of directories to search for source/include files */ +struct search_path { + struct search_path *next; /* next node in list, NULL for end */ + const char *dirname; /* name of directory to search */ +}; + +/* This is the list of directories that we search for source files */ +static struct search_path *search_path_head, **search_path_tail; + +/* Detect infinite include recursion. */ +#define MAX_SRCFILE_DEPTH (100) +static int srcfile_depth; /* = 0 */ + +static char *get_dirname(const char *path) +{ + const char *slash = strrchr(path, '/'); + + if (slash) { + int len = slash - path; + char *dir = xmalloc(len + 1); + + memcpy(dir, path, len); + dir[len] = '\0'; + return dir; + } + return NULL; +} + +FILE *depfile; /* = NULL */ +struct srcfile_state *current_srcfile; /* = NULL */ +static char *initial_path; /* = NULL */ +static int initial_pathlen; /* = 0 */ +static bool initial_cpp = true; + +static void set_initial_path(char *fname) +{ + int i, len = strlen(fname); + + xasprintf(&initial_path, "%s", fname); + initial_pathlen = 0; + for (i = 0; i != len; i++) + if (initial_path[i] == '/') + initial_pathlen++; +} + +static char *shorten_to_initial_path(char *fname) +{ + char *p1, *p2, *prevslash1 = NULL; + int slashes = 0; + + for (p1 = fname, p2 = initial_path; *p1 && *p2; p1++, p2++) { + if (*p1 != *p2) + break; + if (*p1 == '/') { + prevslash1 = p1; + slashes++; + } + } + p1 = prevslash1 + 1; + if (prevslash1) { + int diff = initial_pathlen - slashes, i, j; + int restlen = strlen(fname) - (p1 - fname); + char *res; + + res = xmalloc((3 * diff) + restlen + 1); + for (i = 0, j = 0; i != diff; i++) { + res[j++] = '.'; + res[j++] = '.'; + res[j++] = '/'; + } + strcpy(res + j, p1); + return res; + } + return NULL; +} + +/** + * Try to open a file in a given directory. + * + * If the filename is an absolute path, then dirname is ignored. If it is a + * relative path, then we look in that directory for the file. + * + * @param dirname Directory to look in, or NULL for none + * @param fname Filename to look for + * @param fp Set to NULL if file did not open + * @return allocated filename on success (caller must free), NULL on failure + */ +static char *try_open(const char *dirname, const char *fname, FILE **fp) +{ + char *fullname; + + if (!dirname || fname[0] == '/') + fullname = xstrdup(fname); + else + fullname = join_path(dirname, fname); + + *fp = fopen(fullname, "rb"); + if (!*fp) { + free(fullname); + fullname = NULL; + } + + return fullname; +} + +/** + * Open a file for read access + * + * If it is a relative filename, we search the full search path for it. + * + * @param fname Filename to open + * @param fp Returns pointer to opened FILE, or NULL on failure + * @return pointer to allocated filename, which caller must free + */ +static char *fopen_any_on_path(const char *fname, FILE **fp) +{ + const char *cur_dir = NULL; + struct search_path *node; + char *fullname; + + /* Try current directory first */ + assert(fp); + if (current_srcfile) + cur_dir = current_srcfile->dir; + fullname = try_open(cur_dir, fname, fp); + + /* Failing that, try each search path in turn */ + for (node = search_path_head; !*fp && node; node = node->next) + fullname = try_open(node->dirname, fname, fp); + + return fullname; +} + +FILE *srcfile_relative_open(const char *fname, char **fullnamep) +{ + FILE *f; + char *fullname; + + if (streq(fname, "-")) { + f = stdin; + fullname = xstrdup("<stdin>"); + } else { + fullname = fopen_any_on_path(fname, &f); + if (!f) + die("Couldn't open \"%s\": %s\n", fname, + strerror(errno)); + } + + if (depfile) + fprintf(depfile, " %s", fullname); + + if (fullnamep) + *fullnamep = fullname; + else + free(fullname); + + return f; +} + +void srcfile_push(const char *fname) +{ + struct srcfile_state *srcfile; + + if (srcfile_depth++ >= MAX_SRCFILE_DEPTH) + die("Includes nested too deeply"); + + srcfile = xmalloc(sizeof(*srcfile)); + + srcfile->f = srcfile_relative_open(fname, &srcfile->name); + srcfile->dir = get_dirname(srcfile->name); + srcfile->prev = current_srcfile; + + srcfile->lineno = 1; + srcfile->colno = 1; + + current_srcfile = srcfile; + + if (srcfile_depth == 1) + set_initial_path(srcfile->name); +} + +bool srcfile_pop(void) +{ + struct srcfile_state *srcfile = current_srcfile; + + assert(srcfile); + + current_srcfile = srcfile->prev; + + if (fclose(srcfile->f)) + die("Error closing \"%s\": %s\n", srcfile->name, + strerror(errno)); + + /* FIXME: We allow the srcfile_state structure to leak, + * because it could still be referenced from a location + * variable being carried through the parser somewhere. To + * fix this we could either allocate all the files from a + * table, or use a pool allocator. */ + + return current_srcfile ? true : false; +} + +void srcfile_add_search_path(const char *dirname) +{ + struct search_path *node; + + /* Create the node */ + node = xmalloc(sizeof(*node)); + node->next = NULL; + node->dirname = xstrdup(dirname); + + /* Add to the end of our list */ + if (search_path_tail) + *search_path_tail = node; + else + search_path_head = node; + search_path_tail = &node->next; +} + +void srcpos_update(struct srcpos *pos, const char *text, int len) +{ + int i; + + pos->file = current_srcfile; + + pos->first_line = current_srcfile->lineno; + pos->first_column = current_srcfile->colno; + + for (i = 0; i < len; i++) + if (text[i] == '\n') { + current_srcfile->lineno++; + current_srcfile->colno = 1; + } else { + current_srcfile->colno++; + } + + pos->last_line = current_srcfile->lineno; + pos->last_column = current_srcfile->colno; +} + +struct srcpos * +srcpos_copy(struct srcpos *pos) +{ + struct srcpos *pos_new; + struct srcfile_state *srcfile_state; + + if (!pos) + return NULL; + + pos_new = xmalloc(sizeof(struct srcpos)); + assert(pos->next == NULL); + memcpy(pos_new, pos, sizeof(struct srcpos)); + + /* allocate without free */ + srcfile_state = xmalloc(sizeof(struct srcfile_state)); + memcpy(srcfile_state, pos->file, sizeof(struct srcfile_state)); + pos_new->file = srcfile_state; + + return pos_new; +} + +struct srcpos *srcpos_extend(struct srcpos *pos, struct srcpos *newtail) +{ + struct srcpos *p; + + if (!pos) + return newtail; + + for (p = pos; p->next != NULL; p = p->next); + p->next = newtail; + return pos; +} + +char * +srcpos_string(struct srcpos *pos) +{ + const char *fname = "<no-file>"; + char *pos_str; + + if (pos->file && pos->file->name) + fname = pos->file->name; + + + if (pos->first_line != pos->last_line) + xasprintf(&pos_str, "%s:%d.%d-%d.%d", fname, + pos->first_line, pos->first_column, + pos->last_line, pos->last_column); + else if (pos->first_column != pos->last_column) + xasprintf(&pos_str, "%s:%d.%d-%d", fname, + pos->first_line, pos->first_column, + pos->last_column); + else + xasprintf(&pos_str, "%s:%d.%d", fname, + pos->first_line, pos->first_column); + + return pos_str; +} + +static char * +srcpos_string_comment(struct srcpos *pos, bool first_line, int level) +{ + char *pos_str, *fname, *first, *rest; + bool fresh_fname = false; + + if (!pos) { + if (level > 1) { + xasprintf(&pos_str, "<no-file>:<no-line>"); + return pos_str; + } else { + return NULL; + } + } + + if (!pos->file) + fname = "<no-file>"; + else if (!pos->file->name) + fname = "<no-filename>"; + else if (level > 1) + fname = pos->file->name; + else { + fname = shorten_to_initial_path(pos->file->name); + if (fname) + fresh_fname = true; + else + fname = pos->file->name; + } + + if (level > 1) + xasprintf(&first, "%s:%d:%d-%d:%d", fname, + pos->first_line, pos->first_column, + pos->last_line, pos->last_column); + else + xasprintf(&first, "%s:%d", fname, + first_line ? pos->first_line : pos->last_line); + + if (fresh_fname) + free(fname); + + if (pos->next != NULL) { + rest = srcpos_string_comment(pos->next, first_line, level); + xasprintf(&pos_str, "%s, %s", first, rest); + free(first); + free(rest); + } else { + pos_str = first; + } + + return pos_str; +} + +char *srcpos_string_first(struct srcpos *pos, int level) +{ + return srcpos_string_comment(pos, true, level); +} + +char *srcpos_string_last(struct srcpos *pos, int level) +{ + return srcpos_string_comment(pos, false, level); +} + +void srcpos_verror(struct srcpos *pos, const char *prefix, + const char *fmt, va_list va) +{ + char *srcstr; + + srcstr = srcpos_string(pos); + + fprintf(stderr, "%s: %s ", prefix, srcstr); + vfprintf(stderr, fmt, va); + fprintf(stderr, "\n"); + + free(srcstr); +} + +void srcpos_error(struct srcpos *pos, const char *prefix, + const char *fmt, ...) +{ + va_list va; + + va_start(va, fmt); + srcpos_verror(pos, prefix, fmt, va); + va_end(va); +} + +void srcpos_set_line(char *f, int l) +{ + current_srcfile->name = f; + current_srcfile->lineno = l; + + if (initial_cpp) { + initial_cpp = false; + set_initial_path(f); + } +} diff --git a/src/net/scripts/dtc/srcpos.h b/src/net/scripts/dtc/srcpos.h new file mode 100644 index 0000000..4318d7a --- /dev/null +++ b/src/net/scripts/dtc/srcpos.h @@ -0,0 +1,103 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright 2007 Jon Loeliger, Freescale Semiconductor, Inc. + */ + +#ifndef SRCPOS_H +#define SRCPOS_H + +#include <stdio.h> +#include <stdbool.h> +#include "util.h" + +struct srcfile_state { + FILE *f; + char *name; + char *dir; + int lineno, colno; + struct srcfile_state *prev; +}; + +extern FILE *depfile; /* = NULL */ +extern struct srcfile_state *current_srcfile; /* = NULL */ + +/** + * Open a source file. + * + * If the source file is a relative pathname, then it is searched for in the + * current directory (the directory of the last source file read) and after + * that in the search path. + * + * We work through the search path in order from the first path specified to + * the last. + * + * If the file is not found, then this function does not return, but calls + * die(). + * + * @param fname Filename to search + * @param fullnamep If non-NULL, it is set to the allocated filename of the + * file that was opened. The caller is then responsible + * for freeing the pointer. + * @return pointer to opened FILE + */ +FILE *srcfile_relative_open(const char *fname, char **fullnamep); + +void srcfile_push(const char *fname); +bool srcfile_pop(void); + +/** + * Add a new directory to the search path for input files + * + * The new path is added at the end of the list. + * + * @param dirname Directory to add + */ +void srcfile_add_search_path(const char *dirname); + +struct srcpos { + int first_line; + int first_column; + int last_line; + int last_column; + struct srcfile_state *file; + struct srcpos *next; +}; + +#define YYLTYPE struct srcpos + +#define YYLLOC_DEFAULT(Current, Rhs, N) \ + do { \ + if (N) { \ + (Current).first_line = YYRHSLOC(Rhs, 1).first_line; \ + (Current).first_column = YYRHSLOC(Rhs, 1).first_column; \ + (Current).last_line = YYRHSLOC(Rhs, N).last_line; \ + (Current).last_column = YYRHSLOC (Rhs, N).last_column; \ + (Current).file = YYRHSLOC(Rhs, N).file; \ + } else { \ + (Current).first_line = (Current).last_line = \ + YYRHSLOC(Rhs, 0).last_line; \ + (Current).first_column = (Current).last_column = \ + YYRHSLOC(Rhs, 0).last_column; \ + (Current).file = YYRHSLOC (Rhs, 0).file; \ + } \ + (Current).next = NULL; \ + } while (0) + + +extern void srcpos_update(struct srcpos *pos, const char *text, int len); +extern struct srcpos *srcpos_copy(struct srcpos *pos); +extern struct srcpos *srcpos_extend(struct srcpos *new_srcpos, + struct srcpos *old_srcpos); +extern char *srcpos_string(struct srcpos *pos); +extern char *srcpos_string_first(struct srcpos *pos, int level); +extern char *srcpos_string_last(struct srcpos *pos, int level); + + +extern void PRINTF(3, 0) srcpos_verror(struct srcpos *pos, const char *prefix, + const char *fmt, va_list va); +extern void PRINTF(3, 4) srcpos_error(struct srcpos *pos, const char *prefix, + const char *fmt, ...); + +extern void srcpos_set_line(char *f, int l); + +#endif /* SRCPOS_H */ diff --git a/src/net/scripts/dtc/treesource.c b/src/net/scripts/dtc/treesource.c new file mode 100644 index 0000000..061ba8c --- /dev/null +++ b/src/net/scripts/dtc/treesource.c @@ -0,0 +1,345 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (C) Copyright David Gibson <dwg@au1.ibm.com>, IBM Corporation. 2005. + */ + +#include "dtc.h" +#include "srcpos.h" + +extern FILE *yyin; +extern int yyparse(void); +extern YYLTYPE yylloc; + +struct dt_info *parser_output; +bool treesource_error; + +struct dt_info *dt_from_source(const char *fname) +{ + parser_output = NULL; + treesource_error = false; + + srcfile_push(fname); + yyin = current_srcfile->f; + yylloc.file = current_srcfile; + + if (yyparse() != 0) + die("Unable to parse input tree\n"); + + if (treesource_error) + die("Syntax error parsing input tree\n"); + + return parser_output; +} + +static void write_prefix(FILE *f, int level) +{ + int i; + + for (i = 0; i < level; i++) + fputc('\t', f); +} + +static bool isstring(char c) +{ + return (isprint((unsigned char)c) + || (c == '\0') + || strchr("\a\b\t\n\v\f\r", c)); +} + +static void write_propval_string(FILE *f, const char *s, size_t len) +{ + const char *end = s + len - 1; + + if (!len) + return; + + assert(*end == '\0'); + + fprintf(f, "\""); + while (s < end) { + char c = *s++; + switch (c) { + case '\a': + fprintf(f, "\\a"); + break; + case '\b': + fprintf(f, "\\b"); + break; + case '\t': + fprintf(f, "\\t"); + break; + case '\n': + fprintf(f, "\\n"); + break; + case '\v': + fprintf(f, "\\v"); + break; + case '\f': + fprintf(f, "\\f"); + break; + case '\r': + fprintf(f, "\\r"); + break; + case '\\': + fprintf(f, "\\\\"); + break; + case '\"': + fprintf(f, "\\\""); + break; + case '\0': + fprintf(f, "\\0"); + break; + default: + if (isprint((unsigned char)c)) + fprintf(f, "%c", c); + else + fprintf(f, "\\x%02"PRIx8, c); + } + } + fprintf(f, "\""); +} + +static void write_propval_int(FILE *f, const char *p, size_t len, size_t width) +{ + const char *end = p + len; + assert(len % width == 0); + + for (; p < end; p += width) { + switch (width) { + case 1: + fprintf(f, "%02"PRIx8, *(const uint8_t*)p); + break; + case 2: + fprintf(f, "0x%02"PRIx16, dtb_ld16(p)); + break; + case 4: + fprintf(f, "0x%02"PRIx32, dtb_ld32(p)); + break; + case 8: + fprintf(f, "0x%02"PRIx64, dtb_ld64(p)); + break; + } + if (p + width < end) + fputc(' ', f); + } +} + +static bool has_data_type_information(struct marker *m) +{ + return m->type >= TYPE_UINT8; +} + +static struct marker *next_type_marker(struct marker *m) +{ + while (m && !has_data_type_information(m)) + m = m->next; + return m; +} + +size_t type_marker_length(struct marker *m) +{ + struct marker *next = next_type_marker(m->next); + + if (next) + return next->offset - m->offset; + return 0; +} + +static const char *delim_start[] = { + [TYPE_UINT8] = "[", + [TYPE_UINT16] = "/bits/ 16 <", + [TYPE_UINT32] = "<", + [TYPE_UINT64] = "/bits/ 64 <", + [TYPE_STRING] = "", +}; +static const char *delim_end[] = { + [TYPE_UINT8] = "]", + [TYPE_UINT16] = ">", + [TYPE_UINT32] = ">", + [TYPE_UINT64] = ">", + [TYPE_STRING] = "", +}; + +static enum markertype guess_value_type(struct property *prop) +{ + int len = prop->val.len; + const char *p = prop->val.val; + struct marker *m = prop->val.markers; + int nnotstring = 0, nnul = 0; + int nnotstringlbl = 0, nnotcelllbl = 0; + int i; + + for (i = 0; i < len; i++) { + if (! isstring(p[i])) + nnotstring++; + if (p[i] == '\0') + nnul++; + } + + for_each_marker_of_type(m, LABEL) { + if ((m->offset > 0) && (prop->val.val[m->offset - 1] != '\0')) + nnotstringlbl++; + if ((m->offset % sizeof(cell_t)) != 0) + nnotcelllbl++; + } + + if ((p[len-1] == '\0') && (nnotstring == 0) && (nnul <= (len-nnul)) + && (nnotstringlbl == 0)) { + return TYPE_STRING; + } else if (((len % sizeof(cell_t)) == 0) && (nnotcelllbl == 0)) { + return TYPE_UINT32; + } + + return TYPE_UINT8; +} + +static void write_propval(FILE *f, struct property *prop) +{ + size_t len = prop->val.len; + struct marker *m = prop->val.markers; + struct marker dummy_marker; + enum markertype emit_type = TYPE_NONE; + char *srcstr; + + if (len == 0) { + fprintf(f, ";"); + if (annotate) { + srcstr = srcpos_string_first(prop->srcpos, annotate); + if (srcstr) { + fprintf(f, " /* %s */", srcstr); + free(srcstr); + } + } + fprintf(f, "\n"); + return; + } + + fprintf(f, " ="); + + if (!next_type_marker(m)) { + /* data type information missing, need to guess */ + dummy_marker.type = guess_value_type(prop); + dummy_marker.next = prop->val.markers; + dummy_marker.offset = 0; + dummy_marker.ref = NULL; + m = &dummy_marker; + } + + for_each_marker(m) { + size_t chunk_len = (m->next ? m->next->offset : len) - m->offset; + size_t data_len = type_marker_length(m) ? : len - m->offset; + const char *p = &prop->val.val[m->offset]; + + if (has_data_type_information(m)) { + emit_type = m->type; + fprintf(f, " %s", delim_start[emit_type]); + } else if (m->type == LABEL) + fprintf(f, " %s:", m->ref); + else if (m->offset) + fputc(' ', f); + + if (emit_type == TYPE_NONE) { + assert(chunk_len == 0); + continue; + } + + switch(emit_type) { + case TYPE_UINT16: + write_propval_int(f, p, chunk_len, 2); + break; + case TYPE_UINT32: + write_propval_int(f, p, chunk_len, 4); + break; + case TYPE_UINT64: + write_propval_int(f, p, chunk_len, 8); + break; + case TYPE_STRING: + write_propval_string(f, p, chunk_len); + break; + default: + write_propval_int(f, p, chunk_len, 1); + } + + if (chunk_len == data_len) { + size_t pos = m->offset + chunk_len; + fprintf(f, pos == len ? "%s" : "%s,", + delim_end[emit_type] ? : ""); + emit_type = TYPE_NONE; + } + } + fprintf(f, ";"); + if (annotate) { + srcstr = srcpos_string_first(prop->srcpos, annotate); + if (srcstr) { + fprintf(f, " /* %s */", srcstr); + free(srcstr); + } + } + fprintf(f, "\n"); +} + +static void write_tree_source_node(FILE *f, struct node *tree, int level) +{ + struct property *prop; + struct node *child; + struct label *l; + char *srcstr; + + write_prefix(f, level); + for_each_label(tree->labels, l) + fprintf(f, "%s: ", l->label); + if (tree->name && (*tree->name)) + fprintf(f, "%s {", tree->name); + else + fprintf(f, "/ {"); + + if (annotate) { + srcstr = srcpos_string_first(tree->srcpos, annotate); + if (srcstr) { + fprintf(f, " /* %s */", srcstr); + free(srcstr); + } + } + fprintf(f, "\n"); + + for_each_property(tree, prop) { + write_prefix(f, level+1); + for_each_label(prop->labels, l) + fprintf(f, "%s: ", l->label); + fprintf(f, "%s", prop->name); + write_propval(f, prop); + } + for_each_child(tree, child) { + fprintf(f, "\n"); + write_tree_source_node(f, child, level+1); + } + write_prefix(f, level); + fprintf(f, "};"); + if (annotate) { + srcstr = srcpos_string_last(tree->srcpos, annotate); + if (srcstr) { + fprintf(f, " /* %s */", srcstr); + free(srcstr); + } + } + fprintf(f, "\n"); +} + +void dt_to_source(FILE *f, struct dt_info *dti) +{ + struct reserve_info *re; + + fprintf(f, "/dts-v1/;\n\n"); + + for (re = dti->reservelist; re; re = re->next) { + struct label *l; + + for_each_label(re->labels, l) + fprintf(f, "%s: ", l->label); + fprintf(f, "/memreserve/\t0x%016llx 0x%016llx;\n", + (unsigned long long)re->address, + (unsigned long long)re->size); + } + + write_tree_source_node(f, dti->dt, 0); +} diff --git a/src/net/scripts/dtc/update-dtc-source.sh b/src/net/scripts/dtc/update-dtc-source.sh new file mode 100755 index 0000000..bc704e2 --- /dev/null +++ b/src/net/scripts/dtc/update-dtc-source.sh @@ -0,0 +1,79 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0 +# Simple script to update the version of DTC carried by the Linux kernel +# +# This script assumes that the dtc and the linux git trees are in the +# same directory. After building dtc in the dtc directory, it copies the +# source files and generated source file(s) into the scripts/dtc directory +# in the kernel and creates a git commit updating them to the new +# version. +# +# Usage: from the top level Linux source tree, run: +# $ ./scripts/dtc/update-dtc-source.sh +# +# The script will change into the dtc tree, build and test dtc, copy the +# relevant files into the kernel tree and create a git commit. The commit +# message will need to be modified to reflect the version of DTC being +# imported +# +# TODO: +# This script is pretty basic, but it is seldom used so a few manual tasks +# aren't a big deal. If anyone is interested in making it more robust, the +# the following would be nice: +# * Actually fail to complete if any testcase fails. +# - The dtc "make check" target needs to return a failure +# * Extract the version number from the dtc repo for the commit message +# * Build dtc in the kernel tree +# * run 'make check" on dtc built from the kernel tree + +set -ev + +DTC_UPSTREAM_PATH=`pwd`/../dtc +DTC_LINUX_PATH=`pwd`/scripts/dtc + +DTC_SOURCE="checks.c data.c dtc.c dtc.h flattree.c fstree.c livetree.c srcpos.c \ + srcpos.h treesource.c util.c util.h version_gen.h yamltree.c \ + dtc-lexer.l dtc-parser.y" +LIBFDT_SOURCE="fdt.c fdt.h fdt_addresses.c fdt_empty_tree.c \ + fdt_overlay.c fdt_ro.c fdt_rw.c fdt_strerror.c fdt_sw.c \ + fdt_wip.c libfdt.h libfdt_env.h libfdt_internal.h" + +get_last_dtc_version() { + git log --oneline scripts/dtc/ | grep 'upstream' | head -1 | sed -e 's/^.* \(.*\)/\1/' +} + +last_dtc_ver=$(get_last_dtc_version) + +# Build DTC +cd $DTC_UPSTREAM_PATH +make clean +make check +dtc_version=$(git describe HEAD) +dtc_log=$(git log --oneline ${last_dtc_ver}..) + + +# Copy the files into the Linux tree +cd $DTC_LINUX_PATH +for f in $DTC_SOURCE; do + cp ${DTC_UPSTREAM_PATH}/${f} ${f} + git add ${f} +done +for f in $LIBFDT_SOURCE; do + cp ${DTC_UPSTREAM_PATH}/libfdt/${f} libfdt/${f} + git add libfdt/${f} +done + +sed -i -- 's/#include <libfdt_env.h>/#include "libfdt_env.h"/g' ./libfdt/libfdt.h +sed -i -- 's/#include <fdt.h>/#include "fdt.h"/g' ./libfdt/libfdt.h +git add ./libfdt/libfdt.h + +commit_msg=$(cat << EOF +scripts/dtc: Update to upstream version ${dtc_version} + +This adds the following commits from upstream: + +${dtc_log} +EOF +) + +git commit -e -v -s -m "${commit_msg}" diff --git a/src/net/scripts/dtc/util.c b/src/net/scripts/dtc/util.c new file mode 100644 index 0000000..40274fb --- /dev/null +++ b/src/net/scripts/dtc/util.c @@ -0,0 +1,468 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2011 The Chromium Authors, All Rights Reserved. + * Copyright 2008 Jon Loeliger, Freescale Semiconductor, Inc. + * + * util_is_printable_string contributed by + * Pantelis Antoniou <pantelis.antoniou AT gmail.com> + */ + +#include <ctype.h> +#include <stdio.h> +#include <stdlib.h> +#include <stdarg.h> +#include <string.h> +#include <assert.h> +#include <inttypes.h> + +#include <errno.h> +#include <fcntl.h> +#include <unistd.h> + +#include "libfdt.h" +#include "util.h" +#include "version_gen.h" + +char *xstrdup(const char *s) +{ + int len = strlen(s) + 1; + char *d = xmalloc(len); + + memcpy(d, s, len); + + return d; +} + +int xavsprintf_append(char **strp, const char *fmt, va_list ap) +{ + int n, size = 0; /* start with 128 bytes */ + char *p; + va_list ap_copy; + + p = *strp; + if (p) + size = strlen(p); + + va_copy(ap_copy, ap); + n = vsnprintf(NULL, 0, fmt, ap_copy) + 1; + va_end(ap_copy); + + p = xrealloc(p, size + n); + + n = vsnprintf(p + size, n, fmt, ap); + + *strp = p; + return strlen(p); +} + +int xasprintf_append(char **strp, const char *fmt, ...) +{ + int n; + va_list ap; + + va_start(ap, fmt); + n = xavsprintf_append(strp, fmt, ap); + va_end(ap); + + return n; +} + +int xasprintf(char **strp, const char *fmt, ...) +{ + int n; + va_list ap; + + *strp = NULL; + + va_start(ap, fmt); + n = xavsprintf_append(strp, fmt, ap); + va_end(ap); + + return n; +} + +char *join_path(const char *path, const char *name) +{ + int lenp = strlen(path); + int lenn = strlen(name); + int len; + int needslash = 1; + char *str; + + len = lenp + lenn + 2; + if ((lenp > 0) && (path[lenp-1] == '/')) { + needslash = 0; + len--; + } + + str = xmalloc(len); + memcpy(str, path, lenp); + if (needslash) { + str[lenp] = '/'; + lenp++; + } + memcpy(str+lenp, name, lenn+1); + return str; +} + +bool util_is_printable_string(const void *data, int len) +{ + const char *s = data; + const char *ss, *se; + + /* zero length is not */ + if (len == 0) + return 0; + + /* must terminate with zero */ + if (s[len - 1] != '\0') + return 0; + + se = s + len; + + while (s < se) { + ss = s; + while (s < se && *s && isprint((unsigned char)*s)) + s++; + + /* not zero, or not done yet */ + if (*s != '\0' || s == ss) + return 0; + + s++; + } + + return 1; +} + +/* + * Parse a octal encoded character starting at index i in string s. The + * resulting character will be returned and the index i will be updated to + * point at the character directly after the end of the encoding, this may be + * the '\0' terminator of the string. + */ +static char get_oct_char(const char *s, int *i) +{ + char x[4]; + char *endx; + long val; + + x[3] = '\0'; + strncpy(x, s + *i, 3); + + val = strtol(x, &endx, 8); + + assert(endx > x); + + (*i) += endx - x; + return val; +} + +/* + * Parse a hexadecimal encoded character starting at index i in string s. The + * resulting character will be returned and the index i will be updated to + * point at the character directly after the end of the encoding, this may be + * the '\0' terminator of the string. + */ +static char get_hex_char(const char *s, int *i) +{ + char x[3]; + char *endx; + long val; + + x[2] = '\0'; + strncpy(x, s + *i, 2); + + val = strtol(x, &endx, 16); + if (!(endx > x)) + die("\\x used with no following hex digits\n"); + + (*i) += endx - x; + return val; +} + +char get_escape_char(const char *s, int *i) +{ + char c = s[*i]; + int j = *i + 1; + char val; + + switch (c) { + case 'a': + val = '\a'; + break; + case 'b': + val = '\b'; + break; + case 't': + val = '\t'; + break; + case 'n': + val = '\n'; + break; + case 'v': + val = '\v'; + break; + case 'f': + val = '\f'; + break; + case 'r': + val = '\r'; + break; + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + j--; /* need to re-read the first digit as + * part of the octal value */ + val = get_oct_char(s, &j); + break; + case 'x': + val = get_hex_char(s, &j); + break; + default: + val = c; + } + + (*i) = j; + return val; +} + +int utilfdt_read_err(const char *filename, char **buffp, size_t *len) +{ + int fd = 0; /* assume stdin */ + char *buf = NULL; + size_t bufsize = 1024, offset = 0; + int ret = 0; + + *buffp = NULL; + if (strcmp(filename, "-") != 0) { + fd = open(filename, O_RDONLY); + if (fd < 0) + return errno; + } + + /* Loop until we have read everything */ + buf = xmalloc(bufsize); + do { + /* Expand the buffer to hold the next chunk */ + if (offset == bufsize) { + bufsize *= 2; + buf = xrealloc(buf, bufsize); + } + + ret = read(fd, &buf[offset], bufsize - offset); + if (ret < 0) { + ret = errno; + break; + } + offset += ret; + } while (ret != 0); + + /* Clean up, including closing stdin; return errno on error */ + close(fd); + if (ret) + free(buf); + else + *buffp = buf; + if (len) + *len = bufsize; + return ret; +} + +char *utilfdt_read(const char *filename, size_t *len) +{ + char *buff; + int ret = utilfdt_read_err(filename, &buff, len); + + if (ret) { + fprintf(stderr, "Couldn't open blob from '%s': %s\n", filename, + strerror(ret)); + return NULL; + } + /* Successful read */ + return buff; +} + +int utilfdt_write_err(const char *filename, const void *blob) +{ + int fd = 1; /* assume stdout */ + int totalsize; + int offset; + int ret = 0; + const char *ptr = blob; + + if (strcmp(filename, "-") != 0) { + fd = open(filename, O_WRONLY | O_CREAT | O_TRUNC, 0666); + if (fd < 0) + return errno; + } + + totalsize = fdt_totalsize(blob); + offset = 0; + + while (offset < totalsize) { + ret = write(fd, ptr + offset, totalsize - offset); + if (ret < 0) { + ret = -errno; + break; + } + offset += ret; + } + /* Close the file/stdin; return errno on error */ + if (fd != 1) + close(fd); + return ret < 0 ? -ret : 0; +} + + +int utilfdt_write(const char *filename, const void *blob) +{ + int ret = utilfdt_write_err(filename, blob); + + if (ret) { + fprintf(stderr, "Couldn't write blob to '%s': %s\n", filename, + strerror(ret)); + } + return ret ? -1 : 0; +} + +int utilfdt_decode_type(const char *fmt, int *type, int *size) +{ + int qualifier = 0; + + if (!*fmt) + return -1; + + /* get the conversion qualifier */ + *size = -1; + if (strchr("hlLb", *fmt)) { + qualifier = *fmt++; + if (qualifier == *fmt) { + switch (*fmt++) { +/* TODO: case 'l': qualifier = 'L'; break;*/ + case 'h': + qualifier = 'b'; + break; + } + } + } + + /* we should now have a type */ + if ((*fmt == '\0') || !strchr("iuxs", *fmt)) + return -1; + + /* convert qualifier (bhL) to byte size */ + if (*fmt != 's') + *size = qualifier == 'b' ? 1 : + qualifier == 'h' ? 2 : + qualifier == 'l' ? 4 : -1; + *type = *fmt++; + + /* that should be it! */ + if (*fmt) + return -1; + return 0; +} + +void utilfdt_print_data(const char *data, int len) +{ + int i; + const char *s; + + /* no data, don't print */ + if (len == 0) + return; + + if (util_is_printable_string(data, len)) { + printf(" = "); + + s = data; + do { + printf("\"%s\"", s); + s += strlen(s) + 1; + if (s < data + len) + printf(", "); + } while (s < data + len); + + } else if ((len % 4) == 0) { + const fdt32_t *cell = (const fdt32_t *)data; + + printf(" = <"); + for (i = 0, len /= 4; i < len; i++) + printf("0x%08" PRIx32 "%s", fdt32_to_cpu(cell[i]), + i < (len - 1) ? " " : ""); + printf(">"); + } else { + const unsigned char *p = (const unsigned char *)data; + printf(" = ["); + for (i = 0; i < len; i++) + printf("%02x%s", *p++, i < len - 1 ? " " : ""); + printf("]"); + } +} + +void NORETURN util_version(void) +{ + printf("Version: %s\n", DTC_VERSION); + exit(0); +} + +void NORETURN util_usage(const char *errmsg, const char *synopsis, + const char *short_opts, + struct option const long_opts[], + const char * const opts_help[]) +{ + FILE *fp = errmsg ? stderr : stdout; + const char a_arg[] = "<arg>"; + size_t a_arg_len = strlen(a_arg) + 1; + size_t i; + int optlen; + + fprintf(fp, + "Usage: %s\n" + "\n" + "Options: -[%s]\n", synopsis, short_opts); + + /* prescan the --long opt length to auto-align */ + optlen = 0; + for (i = 0; long_opts[i].name; ++i) { + /* +1 is for space between --opt and help text */ + int l = strlen(long_opts[i].name) + 1; + if (long_opts[i].has_arg == a_argument) + l += a_arg_len; + if (optlen < l) + optlen = l; + } + + for (i = 0; long_opts[i].name; ++i) { + /* helps when adding new applets or options */ + assert(opts_help[i] != NULL); + + /* first output the short flag if it has one */ + if (long_opts[i].val > '~') + fprintf(fp, " "); + else + fprintf(fp, " -%c, ", long_opts[i].val); + + /* then the long flag */ + if (long_opts[i].has_arg == no_argument) + fprintf(fp, "--%-*s", optlen, long_opts[i].name); + else + fprintf(fp, "--%s %s%*s", long_opts[i].name, a_arg, + (int)(optlen - strlen(long_opts[i].name) - a_arg_len), ""); + + /* finally the help text */ + fprintf(fp, "%s\n", opts_help[i]); + } + + if (errmsg) { + fprintf(fp, "\nError: %s\n", errmsg); + exit(EXIT_FAILURE); + } else + exit(EXIT_SUCCESS); +} diff --git a/src/net/scripts/dtc/util.h b/src/net/scripts/dtc/util.h new file mode 100644 index 0000000..a771b46 --- /dev/null +++ b/src/net/scripts/dtc/util.h @@ -0,0 +1,247 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef UTIL_H +#define UTIL_H + +#include <stdlib.h> +#include <stdarg.h> +#include <stdbool.h> +#include <getopt.h> + +/* + * Copyright 2011 The Chromium Authors, All Rights Reserved. + * Copyright 2008 Jon Loeliger, Freescale Semiconductor, Inc. + */ + +#ifdef __GNUC__ +#ifdef __clang__ +#define PRINTF(i, j) __attribute__((format (printf, i, j))) +#else +#define PRINTF(i, j) __attribute__((format (gnu_printf, i, j))) +#endif +#define NORETURN __attribute__((noreturn)) +#else +#define PRINTF(i, j) +#define NORETURN +#endif + +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) + +#define stringify(s) stringify_(s) +#define stringify_(s) #s + +static inline void NORETURN PRINTF(1, 2) die(const char *str, ...) +{ + va_list ap; + + va_start(ap, str); + fprintf(stderr, "FATAL ERROR: "); + vfprintf(stderr, str, ap); + va_end(ap); + exit(1); +} + +static inline void *xmalloc(size_t len) +{ + void *new = malloc(len); + + if (!new) + die("malloc() failed\n"); + + return new; +} + +static inline void *xrealloc(void *p, size_t len) +{ + void *new = realloc(p, len); + + if (!new) + die("realloc() failed (len=%zd)\n", len); + + return new; +} + +extern char *xstrdup(const char *s); + +extern int PRINTF(2, 3) xasprintf(char **strp, const char *fmt, ...); +extern int PRINTF(2, 3) xasprintf_append(char **strp, const char *fmt, ...); +extern int xavsprintf_append(char **strp, const char *fmt, va_list ap); +extern char *join_path(const char *path, const char *name); + +/** + * Check a property of a given length to see if it is all printable and + * has a valid terminator. The property can contain either a single string, + * or multiple strings each of non-zero length. + * + * @param data The string to check + * @param len The string length including terminator + * @return 1 if a valid printable string, 0 if not + */ +bool util_is_printable_string(const void *data, int len); + +/* + * Parse an escaped character starting at index i in string s. The resulting + * character will be returned and the index i will be updated to point at the + * character directly after the end of the encoding, this may be the '\0' + * terminator of the string. + */ +char get_escape_char(const char *s, int *i); + +/** + * Read a device tree file into a buffer. This will report any errors on + * stderr. + * + * @param filename The filename to read, or - for stdin + * @param len If non-NULL, the amount of data we managed to read + * @return Pointer to allocated buffer containing fdt, or NULL on error + */ +char *utilfdt_read(const char *filename, size_t *len); + +/** + * Read a device tree file into a buffer. Does not report errors, but only + * returns them. The value returned can be passed to strerror() to obtain + * an error message for the user. + * + * @param filename The filename to read, or - for stdin + * @param buffp Returns pointer to buffer containing fdt + * @param len If non-NULL, the amount of data we managed to read + * @return 0 if ok, else an errno value representing the error + */ +int utilfdt_read_err(const char *filename, char **buffp, size_t *len); + +/** + * Write a device tree buffer to a file. This will report any errors on + * stderr. + * + * @param filename The filename to write, or - for stdout + * @param blob Pointer to buffer containing fdt + * @return 0 if ok, -1 on error + */ +int utilfdt_write(const char *filename, const void *blob); + +/** + * Write a device tree buffer to a file. Does not report errors, but only + * returns them. The value returned can be passed to strerror() to obtain + * an error message for the user. + * + * @param filename The filename to write, or - for stdout + * @param blob Pointer to buffer containing fdt + * @return 0 if ok, else an errno value representing the error + */ +int utilfdt_write_err(const char *filename, const void *blob); + +/** + * Decode a data type string. The purpose of this string + * + * The string consists of an optional character followed by the type: + * Modifier characters: + * hh or b 1 byte + * h 2 byte + * l 4 byte, default + * + * Type character: + * s string + * i signed integer + * u unsigned integer + * x hex + * + * TODO: Implement ll modifier (8 bytes) + * TODO: Implement o type (octal) + * + * @param fmt Format string to process + * @param type Returns type found(s/d/u/x), or 0 if none + * @param size Returns size found(1,2,4,8) or 4 if none + * @return 0 if ok, -1 on error (no type given, or other invalid format) + */ +int utilfdt_decode_type(const char *fmt, int *type, int *size); + +/* + * This is a usage message fragment for the -t option. It is the format + * supported by utilfdt_decode_type. + */ + +#define USAGE_TYPE_MSG \ + "<type>\ts=string, i=int, u=unsigned, x=hex\n" \ + "\tOptional modifier prefix:\n" \ + "\t\thh or b=byte, h=2 byte, l=4 byte (default)"; + +/** + * Print property data in a readable format to stdout + * + * Properties that look like strings will be printed as strings. Otherwise + * the data will be displayed either as cells (if len is a multiple of 4 + * bytes) or bytes. + * + * If len is 0 then this function does nothing. + * + * @param data Pointers to property data + * @param len Length of property data + */ +void utilfdt_print_data(const char *data, int len); + +/** + * Show source version and exit + */ +void NORETURN util_version(void); + +/** + * Show usage and exit + * + * This helps standardize the output of various utils. You most likely want + * to use the usage() helper below rather than call this. + * + * @param errmsg If non-NULL, an error message to display + * @param synopsis The initial example usage text (and possible examples) + * @param short_opts The string of short options + * @param long_opts The structure of long options + * @param opts_help An array of help strings (should align with long_opts) + */ +void NORETURN util_usage(const char *errmsg, const char *synopsis, + const char *short_opts, + struct option const long_opts[], + const char * const opts_help[]); + +/** + * Show usage and exit + * + * If you name all your usage variables with usage_xxx, then you can call this + * help macro rather than expanding all arguments yourself. + * + * @param errmsg If non-NULL, an error message to display + */ +#define usage(errmsg) \ + util_usage(errmsg, usage_synopsis, usage_short_opts, \ + usage_long_opts, usage_opts_help) + +/** + * Call getopt_long() with standard options + * + * Since all util code runs getopt in the same way, provide a helper. + */ +#define util_getopt_long() getopt_long(argc, argv, usage_short_opts, \ + usage_long_opts, NULL) + +/* Helper for aligning long_opts array */ +#define a_argument required_argument + +/* Helper for usage_short_opts string constant */ +#define USAGE_COMMON_SHORT_OPTS "hV" + +/* Helper for usage_long_opts option array */ +#define USAGE_COMMON_LONG_OPTS \ + {"help", no_argument, NULL, 'h'}, \ + {"version", no_argument, NULL, 'V'}, \ + {NULL, no_argument, NULL, 0x0} + +/* Helper for usage_opts_help array */ +#define USAGE_COMMON_OPTS_HELP \ + "Print this help and exit", \ + "Print version and exit", \ + NULL + +/* Helper for getopt case statements */ +#define case_USAGE_COMMON_FLAGS \ + case 'h': usage(NULL); \ + case 'V': util_version(); \ + case '?': usage("unknown option"); + +#endif /* UTIL_H */ diff --git a/src/net/scripts/dtc/version_gen.h b/src/net/scripts/dtc/version_gen.h new file mode 100644 index 0000000..054cdd0 --- /dev/null +++ b/src/net/scripts/dtc/version_gen.h @@ -0,0 +1 @@ +#define DTC_VERSION "DTC 1.6.0-gcbca977e" diff --git a/src/net/scripts/dtc/yamltree.c b/src/net/scripts/dtc/yamltree.c new file mode 100644 index 0000000..4e93c12 --- /dev/null +++ b/src/net/scripts/dtc/yamltree.c @@ -0,0 +1,233 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (C) Copyright Linaro, Ltd. 2018 + * (C) Copyright Arm Holdings. 2017 + * (C) Copyright David Gibson <dwg@au1.ibm.com>, IBM Corporation. 2005. + */ + +#include <stdlib.h> +#include <yaml.h> +#include "dtc.h" +#include "srcpos.h" + +char *yaml_error_name[] = { + [YAML_NO_ERROR] = "no error", + [YAML_MEMORY_ERROR] = "memory error", + [YAML_READER_ERROR] = "reader error", + [YAML_SCANNER_ERROR] = "scanner error", + [YAML_PARSER_ERROR] = "parser error", + [YAML_COMPOSER_ERROR] = "composer error", + [YAML_WRITER_ERROR] = "writer error", + [YAML_EMITTER_ERROR] = "emitter error", +}; + +#define yaml_emitter_emit_or_die(emitter, event) ( \ +{ \ + if (!yaml_emitter_emit(emitter, event)) \ + die("yaml '%s': %s in %s, line %i\n", \ + yaml_error_name[(emitter)->error], \ + (emitter)->problem, __func__, __LINE__); \ +}) + +static void yaml_propval_int(yaml_emitter_t *emitter, struct marker *markers, char *data, int len, int width) +{ + yaml_event_t event; + void *tag; + int off, start_offset = markers->offset; + + switch(width) { + case 1: tag = "!u8"; break; + case 2: tag = "!u16"; break; + case 4: tag = "!u32"; break; + case 8: tag = "!u64"; break; + default: + die("Invalid width %i", width); + } + assert(len % width == 0); + + yaml_sequence_start_event_initialize(&event, NULL, + (yaml_char_t *)tag, width == 4, YAML_FLOW_SEQUENCE_STYLE); + yaml_emitter_emit_or_die(emitter, &event); + + for (off = 0; off < len; off += width) { + char buf[32]; + struct marker *m; + bool is_phandle = false; + + switch(width) { + case 1: + sprintf(buf, "0x%"PRIx8, *(uint8_t*)(data + off)); + break; + case 2: + sprintf(buf, "0x%"PRIx16, dtb_ld16(data + off)); + break; + case 4: + sprintf(buf, "0x%"PRIx32, dtb_ld32(data + off)); + m = markers; + is_phandle = false; + for_each_marker_of_type(m, REF_PHANDLE) { + if (m->offset == (start_offset + off)) { + is_phandle = true; + break; + } + } + break; + case 8: + sprintf(buf, "0x%"PRIx64, dtb_ld64(data + off)); + break; + } + + if (is_phandle) + yaml_scalar_event_initialize(&event, NULL, + (yaml_char_t*)"!phandle", (yaml_char_t *)buf, + strlen(buf), 0, 0, YAML_PLAIN_SCALAR_STYLE); + else + yaml_scalar_event_initialize(&event, NULL, + (yaml_char_t*)YAML_INT_TAG, (yaml_char_t *)buf, + strlen(buf), 1, 1, YAML_PLAIN_SCALAR_STYLE); + yaml_emitter_emit_or_die(emitter, &event); + } + + yaml_sequence_end_event_initialize(&event); + yaml_emitter_emit_or_die(emitter, &event); +} + +static void yaml_propval_string(yaml_emitter_t *emitter, char *str, int len) +{ + yaml_event_t event; + int i; + + assert(str[len-1] == '\0'); + + /* Make sure the entire string is in the lower 7-bit ascii range */ + for (i = 0; i < len; i++) + assert(isascii(str[i])); + + yaml_scalar_event_initialize(&event, NULL, + (yaml_char_t *)YAML_STR_TAG, (yaml_char_t*)str, + len-1, 0, 1, YAML_DOUBLE_QUOTED_SCALAR_STYLE); + yaml_emitter_emit_or_die(emitter, &event); +} + +static void yaml_propval(yaml_emitter_t *emitter, struct property *prop) +{ + yaml_event_t event; + int len = prop->val.len; + struct marker *m = prop->val.markers; + + /* Emit the property name */ + yaml_scalar_event_initialize(&event, NULL, + (yaml_char_t *)YAML_STR_TAG, (yaml_char_t*)prop->name, + strlen(prop->name), 1, 1, YAML_PLAIN_SCALAR_STYLE); + yaml_emitter_emit_or_die(emitter, &event); + + /* Boolean properties are easiest to deal with. Length is zero, so just emit 'true' */ + if (len == 0) { + yaml_scalar_event_initialize(&event, NULL, + (yaml_char_t *)YAML_BOOL_TAG, + (yaml_char_t*)"true", + strlen("true"), 1, 0, YAML_PLAIN_SCALAR_STYLE); + yaml_emitter_emit_or_die(emitter, &event); + return; + } + + if (!m) + die("No markers present in property '%s' value\n", prop->name); + + yaml_sequence_start_event_initialize(&event, NULL, + (yaml_char_t *)YAML_SEQ_TAG, 1, YAML_FLOW_SEQUENCE_STYLE); + yaml_emitter_emit_or_die(emitter, &event); + + for_each_marker(m) { + int chunk_len; + char *data = &prop->val.val[m->offset]; + + if (m->type < TYPE_UINT8) + continue; + + chunk_len = type_marker_length(m) ? : len; + assert(chunk_len > 0); + len -= chunk_len; + + switch(m->type) { + case TYPE_UINT16: + yaml_propval_int(emitter, m, data, chunk_len, 2); + break; + case TYPE_UINT32: + yaml_propval_int(emitter, m, data, chunk_len, 4); + break; + case TYPE_UINT64: + yaml_propval_int(emitter, m, data, chunk_len, 8); + break; + case TYPE_STRING: + yaml_propval_string(emitter, data, chunk_len); + break; + default: + yaml_propval_int(emitter, m, data, chunk_len, 1); + break; + } + } + + yaml_sequence_end_event_initialize(&event); + yaml_emitter_emit_or_die(emitter, &event); +} + + +static void yaml_tree(struct node *tree, yaml_emitter_t *emitter) +{ + struct property *prop; + struct node *child; + yaml_event_t event; + + if (tree->deleted) + return; + + yaml_mapping_start_event_initialize(&event, NULL, + (yaml_char_t *)YAML_MAP_TAG, 1, YAML_ANY_MAPPING_STYLE); + yaml_emitter_emit_or_die(emitter, &event); + + for_each_property(tree, prop) + yaml_propval(emitter, prop); + + /* Loop over all the children, emitting them into the map */ + for_each_child(tree, child) { + yaml_scalar_event_initialize(&event, NULL, + (yaml_char_t *)YAML_STR_TAG, (yaml_char_t*)child->name, + strlen(child->name), 1, 0, YAML_PLAIN_SCALAR_STYLE); + yaml_emitter_emit_or_die(emitter, &event); + yaml_tree(child, emitter); + } + + yaml_mapping_end_event_initialize(&event); + yaml_emitter_emit_or_die(emitter, &event); +} + +void dt_to_yaml(FILE *f, struct dt_info *dti) +{ + yaml_emitter_t emitter; + yaml_event_t event; + + yaml_emitter_initialize(&emitter); + yaml_emitter_set_output_file(&emitter, f); + yaml_stream_start_event_initialize(&event, YAML_UTF8_ENCODING); + yaml_emitter_emit_or_die(&emitter, &event); + + yaml_document_start_event_initialize(&event, NULL, NULL, NULL, 0); + yaml_emitter_emit_or_die(&emitter, &event); + + yaml_sequence_start_event_initialize(&event, NULL, (yaml_char_t *)YAML_SEQ_TAG, 1, YAML_ANY_SEQUENCE_STYLE); + yaml_emitter_emit_or_die(&emitter, &event); + + yaml_tree(dti->dt, &emitter); + + yaml_sequence_end_event_initialize(&event); + yaml_emitter_emit_or_die(&emitter, &event); + + yaml_document_end_event_initialize(&event, 0); + yaml_emitter_emit_or_die(&emitter, &event); + + yaml_stream_end_event_initialize(&event); + yaml_emitter_emit_or_die(&emitter, &event); + + yaml_emitter_delete(&emitter); +} diff --git a/src/net/scripts/dummy-tools/gcc b/src/net/scripts/dummy-tools/gcc new file mode 100755 index 0000000..0d0589c --- /dev/null +++ b/src/net/scripts/dummy-tools/gcc @@ -0,0 +1,92 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0-only +# +# Staring v4.18, Kconfig evaluates compiler capabilities, and hides CONFIG +# options your compiler does not support. This works well if you configure and +# build the kernel on the same host machine. +# +# It is inconvenient if you prepare the .config that is carried to a different +# build environment (typically this happens when you package the kernel for +# distros) because using a different compiler potentially produces different +# CONFIG options than the real build environment. So, you probably want to make +# as many options visible as possible. In other words, you need to create a +# super-set of CONFIG options that cover any build environment. If some of the +# CONFIG options turned out to be unsupported on the build machine, they are +# automatically disabled by the nature of Kconfig. +# +# However, it is not feasible to get a full-featured compiler for every arch. +# Hence these dummy toolchains to make all compiler tests pass. +# +# Usage: +# +# From the top directory of the source tree, run +# +# $ make CROSS_COMPILE=scripts/dummy-tools/ oldconfig +# +# Most of compiler features are tested by cc-option, which simply checks the +# exit code of $(CC). This script does nothing and just exits with 0 in most +# cases. So, $(cc-option, ...) is evaluated as 'y'. +# +# This scripts caters to more checks; handle --version and pre-process __GNUC__ +# etc. to pretend to be GCC, and also do right things to satisfy some scripts. + +# Check if the first parameter appears in the rest. Succeeds if found. +# This helper is useful if a particular option was passed to this script. +# Typically used like this: +# arg_contain <word-you-are-searching-for> "$@" +arg_contain () +{ + search="$1" + shift + + while [ $# -gt 0 ] + do + if [ "$search" = "$1" ]; then + return 0 + fi + shift + done + + return 1 +} + +# To set CONFIG_CC_IS_GCC=y +if arg_contain --version "$@"; then + echo "gcc (scripts/dummy-tools/gcc)" + exit 0 +fi + +if arg_contain -E "$@"; then + # For scripts/gcc-version.sh; This emulates GCC 20.0.0 + if arg_contain - "$@"; then + sed 's/^__GNUC__$/20/; s/^__GNUC_MINOR__$/0/; s/^__GNUC_PATCHLEVEL__$/0/' + exit 0 + else + echo "no input files" >&2 + exit 1 + fi +fi + +if arg_contain -S "$@"; then + # For scripts/gcc-x86-*-has-stack-protector.sh + if arg_contain -fstack-protector "$@"; then + echo "%gs" + exit 0 + fi +fi + +# To set GCC_PLUGINS +if arg_contain -print-file-name=plugin "$@"; then + plugin_dir=$(mktemp -d) + + mkdir -p $plugin_dir/include + touch $plugin_dir/include/plugin-version.h + + echo $plugin_dir + exit 0 +fi + +# inverted return value +if arg_contain -D__SIZEOF_INT128__=0 "$@"; then + exit 1 +fi diff --git a/src/net/scripts/dummy-tools/ld b/src/net/scripts/dummy-tools/ld new file mode 100755 index 0000000..f682330 --- /dev/null +++ b/src/net/scripts/dummy-tools/ld @@ -0,0 +1,30 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0-only + +# Dummy script that always succeeds. + +# Check if the first parameter appears in the rest. Succeeds if found. +# This helper is useful if a particular option was passed to this script. +# Typically used like this: +# arg_contain <word-you-are-searching-for> "$@" +arg_contain () +{ + search="$1" + shift + + while [ $# -gt 0 ] + do + if [ "$search" = "$1" ]; then + return 0 + fi + shift + done + + return 1 +} + +if arg_contain --version "$@" || arg_contain -v "$@"; then + progname=$(basename $0) + echo "GNU $progname (scripts/dummy-tools/$progname) 2.50" + exit 0 +fi diff --git a/src/net/scripts/dummy-tools/nm b/src/net/scripts/dummy-tools/nm new file mode 120000 index 0000000..c0648b3 --- /dev/null +++ b/src/net/scripts/dummy-tools/nm @@ -0,0 +1 @@ +ld \ No newline at end of file diff --git a/src/net/scripts/dummy-tools/objcopy b/src/net/scripts/dummy-tools/objcopy new file mode 120000 index 0000000..c0648b3 --- /dev/null +++ b/src/net/scripts/dummy-tools/objcopy @@ -0,0 +1 @@ +ld \ No newline at end of file diff --git a/src/net/scripts/export_report.pl b/src/net/scripts/export_report.pl new file mode 100755 index 0000000..feb3d55 --- /dev/null +++ b/src/net/scripts/export_report.pl @@ -0,0 +1,186 @@ +#!/usr/bin/env perl +# SPDX-License-Identifier: GPL-2.0-only +# +# (C) Copyright IBM Corporation 2006. +# Author : Ram Pai (linuxram@us.ibm.com) +# +# Usage: export_report.pl -k Module.symvers [-o report_file ] -f *.mod.c +# + +use warnings; +use Getopt::Std; +use strict; + +sub numerically { + my $no1 = (split /\s+/, $a)[1]; + my $no2 = (split /\s+/, $b)[1]; + return $no1 <=> $no2; +} + +sub alphabetically { + my ($module1, $value1) = @{$a}; + my ($module2, $value2) = @{$b}; + return $value1 <=> $value2 || $module2 cmp $module1; +} + +sub print_depends_on { + my ($href) = @_; + print "\n"; + for my $mod (sort keys %$href) { + my $list = $href->{$mod}; + print "\t$mod:\n"; + foreach my $sym (sort numerically @{$list}) { + my ($symbol, $no) = split /\s+/, $sym; + printf("\t\t%-25s\n", $symbol); + } + print "\n"; + } + print "\n"; + print "~"x80 , "\n"; +} + +sub usage { + print "Usage: @_ -h -k Module.symvers [ -o outputfile ] \n", + "\t-f: treat all the non-option argument as .mod.c files. ", + "Recommend using this as the last option\n", + "\t-h: print detailed help\n", + "\t-k: the path to Module.symvers file. By default uses ", + "the file from the current directory\n", + "\t-o outputfile: output the report to outputfile\n"; + exit 0; +} + +sub collectcfiles { + my @file; + open my $fh, '< modules.order' or die "cannot open modules.order: $!\n"; + while (<$fh>) { + s/\.ko$/.mod.c/; + push (@file, $_) + } + close($fh); + chomp @file; + return @file; +} + +my (%SYMBOL, %MODULE, %opt, @allcfiles); + +if (not getopts('hk:o:f',\%opt) or defined $opt{'h'}) { + usage($0); +} + +if (defined $opt{'f'}) { + @allcfiles = @ARGV; +} else { + @allcfiles = collectcfiles(); +} + +if (not defined $opt{'k'}) { + $opt{'k'} = "Module.symvers"; +} + +open (my $module_symvers, '<', $opt{'k'}) + or die "Sorry, cannot open $opt{'k'}: $!\n"; + +if (defined $opt{'o'}) { + open (my $out, '>', $opt{'o'}) + or die "Sorry, cannot open $opt{'o'} $!\n"; + + select $out; +} + +# +# collect all the symbols and their attributes from the +# Module.symvers file +# +while ( <$module_symvers> ) { + chomp; + my (undef, $symbol, $module, $gpl, $namespace) = split('\t'); + $SYMBOL { $symbol } = [ $module , "0" , $symbol, $gpl]; +} +close($module_symvers); + +# +# collect the usage count of each symbol. +# +my $modversion_warnings = 0; + +foreach my $thismod (@allcfiles) { + my $module; + + unless (open ($module, '<', $thismod)) { + warn "Sorry, cannot open $thismod: $!\n"; + next; + } + + my $state=0; + while ( <$module> ) { + chomp; + if ($state == 0) { + $state = 1 if ($_ =~ /static const struct modversion_info/); + next; + } + if ($state == 1) { + $state = 2 if ($_ =~ /__attribute__\(\(section\("__versions"\)\)\)/); + next; + } + if ($state == 2) { + if ( $_ !~ /0x[0-9a-f]+,/ ) { + next; + } + my $sym = (split /([,"])/,)[4]; + my ($module, $value, $symbol, $gpl) = @{$SYMBOL{$sym}}; + $SYMBOL{ $sym } = [ $module, $value+1, $symbol, $gpl]; + push(@{$MODULE{$thismod}} , $sym); + } + } + if ($state != 2) { + warn "WARNING:$thismod is not built with CONFIG_MODVERSIONS enabled\n"; + $modversion_warnings++; + } + close($module); +} + +print "\tThis file reports the exported symbols usage patterns by in-tree\n", + "\t\t\t\tmodules\n"; +printf("%s\n\n\n","x"x80); +printf("\t\t\t\tINDEX\n\n\n"); +printf("SECTION 1: Usage counts of all exported symbols\n"); +printf("SECTION 2: List of modules and the exported symbols they use\n"); +printf("%s\n\n\n","x"x80); +printf("SECTION 1:\tThe exported symbols and their usage count\n\n"); +printf("%-25s\t%-25s\t%-5s\t%-25s\n", "Symbol", "Module", "Usage count", + "export type"); + +# +# print the list of unused exported symbols +# +foreach my $list (sort alphabetically values(%SYMBOL)) { + my ($module, $value, $symbol, $gpl) = @{$list}; + printf("%-25s\t%-25s\t%-10s\t", $symbol, $module, $value); + if (defined $gpl) { + printf("%-25s\n",$gpl); + } else { + printf("\n"); + } +} +printf("%s\n\n\n","x"x80); + +printf("SECTION 2:\n\tThis section reports export-symbol-usage of in-kernel +modules. Each module lists the modules, and the symbols from that module that +it uses. Each listed symbol reports the number of modules using it\n"); + +print "\nNOTE: Got $modversion_warnings CONFIG_MODVERSIONS warnings\n\n" + if $modversion_warnings; + +print "~"x80 , "\n"; +for my $thismod (sort keys %MODULE) { + my $list = $MODULE{$thismod}; + my %depends; + $thismod =~ s/\.mod\.c/.ko/; + print "\t\t\t$thismod\n"; + foreach my $symbol (@{$list}) { + my ($module, $value, undef, $gpl) = @{$SYMBOL{$symbol}}; + push (@{$depends{"$module"}}, "$symbol $value"); + } + print_depends_on(\%depends); +} diff --git a/src/net/scripts/extract-cert.c b/src/net/scripts/extract-cert.c new file mode 100644 index 0000000..3bc48c7 --- /dev/null +++ b/src/net/scripts/extract-cert.c @@ -0,0 +1,162 @@ +/* Extract X.509 certificate in DER form from PKCS#11 or PEM. + * + * Copyright © 2014-2015 Red Hat, Inc. All Rights Reserved. + * Copyright © 2015 Intel Corporation. + * + * Authors: David Howells <dhowells@redhat.com> + * David Woodhouse <dwmw2@infradead.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public License + * as published by the Free Software Foundation; either version 2.1 + * of the licence, or (at your option) any later version. + */ +#define _GNU_SOURCE +#include <stdio.h> +#include <stdlib.h> +#include <stdint.h> +#include <stdbool.h> +#include <string.h> +#include <err.h> +#include <openssl/bio.h> +#include <openssl/pem.h> +#include <openssl/err.h> +#include <openssl/engine.h> + +#define PKEY_ID_PKCS7 2 + +static __attribute__((noreturn)) +void format(void) +{ + fprintf(stderr, + "Usage: scripts/extract-cert <source> <dest>\n"); + exit(2); +} + +static void display_openssl_errors(int l) +{ + const char *file; + char buf[120]; + int e, line; + + if (ERR_peek_error() == 0) + return; + fprintf(stderr, "At main.c:%d:\n", l); + + while ((e = ERR_get_error_line(&file, &line))) { + ERR_error_string(e, buf); + fprintf(stderr, "- SSL %s: %s:%d\n", buf, file, line); + } +} + +static void drain_openssl_errors(void) +{ + const char *file; + int line; + + if (ERR_peek_error() == 0) + return; + while (ERR_get_error_line(&file, &line)) {} +} + +#define ERR(cond, fmt, ...) \ + do { \ + bool __cond = (cond); \ + display_openssl_errors(__LINE__); \ + if (__cond) { \ + err(1, fmt, ## __VA_ARGS__); \ + } \ + } while(0) + +static const char *key_pass; +static BIO *wb; +static char *cert_dst; +static int kbuild_verbose; + +static void write_cert(X509 *x509) +{ + char buf[200]; + + if (!wb) { + wb = BIO_new_file(cert_dst, "wb"); + ERR(!wb, "%s", cert_dst); + } + X509_NAME_oneline(X509_get_subject_name(x509), buf, sizeof(buf)); + ERR(!i2d_X509_bio(wb, x509), "%s", cert_dst); + if (kbuild_verbose) + fprintf(stderr, "Extracted cert: %s\n", buf); +} + +int main(int argc, char **argv) +{ + char *cert_src; + + OpenSSL_add_all_algorithms(); + ERR_load_crypto_strings(); + ERR_clear_error(); + + kbuild_verbose = atoi(getenv("KBUILD_VERBOSE")?:"0"); + + key_pass = getenv("KBUILD_SIGN_PIN"); + + if (argc != 3) + format(); + + cert_src = argv[1]; + cert_dst = argv[2]; + + if (!cert_src[0]) { + /* Invoked with no input; create empty file */ + FILE *f = fopen(cert_dst, "wb"); + ERR(!f, "%s", cert_dst); + fclose(f); + exit(0); + } else if (!strncmp(cert_src, "pkcs11:", 7)) { + ENGINE *e; + struct { + const char *cert_id; + X509 *cert; + } parms; + + parms.cert_id = cert_src; + parms.cert = NULL; + + ENGINE_load_builtin_engines(); + drain_openssl_errors(); + e = ENGINE_by_id("pkcs11"); + ERR(!e, "Load PKCS#11 ENGINE"); + if (ENGINE_init(e)) + drain_openssl_errors(); + else + ERR(1, "ENGINE_init"); + if (key_pass) + ERR(!ENGINE_ctrl_cmd_string(e, "PIN", key_pass, 0), "Set PKCS#11 PIN"); + ENGINE_ctrl_cmd(e, "LOAD_CERT_CTRL", 0, &parms, NULL, 1); + ERR(!parms.cert, "Get X.509 from PKCS#11"); + write_cert(parms.cert); + } else { + BIO *b; + X509 *x509; + + b = BIO_new_file(cert_src, "rb"); + ERR(!b, "%s", cert_src); + + while (1) { + x509 = PEM_read_bio_X509(b, NULL, NULL, NULL); + if (wb && !x509) { + unsigned long err = ERR_peek_last_error(); + if (ERR_GET_LIB(err) == ERR_LIB_PEM && + ERR_GET_REASON(err) == PEM_R_NO_START_LINE) { + ERR_clear_error(); + break; + } + } + ERR(!x509, "%s", cert_src); + write_cert(x509); + } + } + + BIO_free(wb); + + return 0; +} diff --git a/src/net/scripts/extract-ikconfig b/src/net/scripts/extract-ikconfig new file mode 100755 index 0000000..3b42f25 --- /dev/null +++ b/src/net/scripts/extract-ikconfig @@ -0,0 +1,68 @@ +#!/bin/sh +# ---------------------------------------------------------------------- +# extract-ikconfig - Extract the .config file from a kernel image +# +# This will only work when the kernel was compiled with CONFIG_IKCONFIG. +# +# The obscure use of the "tr" filter is to work around older versions of +# "grep" that report the byte offset of the line instead of the pattern. +# +# (c) 2009,2010 Dick Streefland <dick@streefland.net> +# Licensed under the terms of the GNU General Public License. +# ---------------------------------------------------------------------- + +cf1='IKCFG_ST\037\213\010' +cf2='0123456789' + +dump_config() +{ + if pos=`tr "$cf1\n$cf2" "\n$cf2=" < "$1" | grep -abo "^$cf2"` + then + pos=${pos%%:*} + tail -c+$(($pos+8)) "$1" | zcat > $tmp1 2> /dev/null + if [ $? != 1 ] + then # exit status must be 0 or 2 (trailing garbage warning) + cat $tmp1 + exit 0 + fi + fi +} + +try_decompress() +{ + for pos in `tr "$1\n$2" "\n$2=" < "$img" | grep -abo "^$2"` + do + pos=${pos%%:*} + tail -c+$pos "$img" | $3 > $tmp2 2> /dev/null + dump_config $tmp2 + done +} + +# Check invocation: +me=${0##*/} +img=$1 +if [ $# -ne 1 -o ! -s "$img" ] +then + echo "Usage: $me <kernel-image>" >&2 + exit 2 +fi + +# Prepare temp files: +tmp1=/tmp/ikconfig$$.1 +tmp2=/tmp/ikconfig$$.2 +trap "rm -f $tmp1 $tmp2" 0 + +# Initial attempt for uncompressed images or objects: +dump_config "$img" + +# That didn't work, so retry after decompression. +try_decompress '\037\213\010' xy gunzip +try_decompress '\3757zXZ\000' abcde unxz +try_decompress 'BZh' xy bunzip2 +try_decompress '\135\0\0\0' xxx unlzma +try_decompress '\211\114\132' xy 'lzop -d' +try_decompress '\002\041\114\030' xyy 'lz4 -d -l' + +# Bail out: +echo "$me: Cannot find kernel config." >&2 +exit 1 diff --git a/src/net/scripts/extract-module-sig.pl b/src/net/scripts/extract-module-sig.pl new file mode 100755 index 0000000..36a2f59 --- /dev/null +++ b/src/net/scripts/extract-module-sig.pl @@ -0,0 +1,138 @@ +#!/usr/bin/env perl +# SPDX-License-Identifier: GPL-2.0 +# +# extract-mod-sig <part> <module-file> +# +# Reads the module file and writes out some or all of the signature +# section to stdout. Part is the bit to be written and is one of: +# +# -0: The unsigned module, no signature data at all +# -a: All of the signature data, including magic number +# -d: Just the descriptor values as a sequence of numbers +# -n: Just the signer's name +# -k: Just the key ID +# -s: Just the crypto signature or PKCS#7 message +# +use warnings; +use strict; + +die "Format: $0 -[0adnks] module-file >out\n" + if ($#ARGV != 1); + +my $part = $ARGV[0]; +my $modfile = $ARGV[1]; + +my $magic_number = "~Module signature appended~\n"; + +# +# Read the module contents +# +open FD, "<$modfile" || die $modfile; +binmode(FD); +my @st = stat(FD); +die "$modfile" unless (@st); +my $buf = ""; +my $len = sysread(FD, $buf, $st[7]); +die "$modfile" unless (defined($len)); +die "Short read on $modfile\n" unless ($len == $st[7]); +close(FD) || die $modfile; + +print STDERR "Read ", $len, " bytes from module file\n"; + +die "The file is too short to have a sig magic number and descriptor\n" + if ($len < 12 + length($magic_number)); + +# +# Check for the magic number and extract the information block +# +my $p = $len - length($magic_number); +my $raw_magic = substr($buf, $p); + +die "Magic number not found at $len\n" + if ($raw_magic ne $magic_number); +print STDERR "Found magic number at $len\n"; + +$p -= 12; +my $raw_info = substr($buf, $p, 12); + +my @info = unpack("CCCCCxxxN", $raw_info); +my ($algo, $hash, $id_type, $name_len, $kid_len, $sig_len) = @info; + +if ($id_type == 0) { + print STDERR "Found PGP key identifier\n"; +} elsif ($id_type == 1) { + print STDERR "Found X.509 cert identifier\n"; +} elsif ($id_type == 2) { + print STDERR "Found PKCS#7/CMS encapsulation\n"; +} else { + print STDERR "Found unsupported identifier type $id_type\n"; +} + +# +# Extract the three pieces of info data +# +die "Insufficient name+kid+sig data in file\n" + unless ($p >= $name_len + $kid_len + $sig_len); + +$p -= $sig_len; +my $raw_sig = substr($buf, $p, $sig_len); +$p -= $kid_len; +my $raw_kid = substr($buf, $p, $kid_len); +$p -= $name_len; +my $raw_name = substr($buf, $p, $name_len); + +my $module_len = $p; + +if ($sig_len > 0) { + print STDERR "Found $sig_len bytes of signature ["; + my $n = $sig_len > 16 ? 16 : $sig_len; + foreach my $i (unpack("C" x $n, substr($raw_sig, 0, $n))) { + printf STDERR "%02x", $i; + } + print STDERR "]\n"; +} + +if ($kid_len > 0) { + print STDERR "Found $kid_len bytes of key identifier ["; + my $n = $kid_len > 16 ? 16 : $kid_len; + foreach my $i (unpack("C" x $n, substr($raw_kid, 0, $n))) { + printf STDERR "%02x", $i; + } + print STDERR "]\n"; +} + +if ($name_len > 0) { + print STDERR "Found $name_len bytes of signer's name [$raw_name]\n"; +} + +# +# Produce the requested output +# +if ($part eq "-0") { + # The unsigned module, no signature data at all + binmode(STDOUT); + print substr($buf, 0, $module_len); +} elsif ($part eq "-a") { + # All of the signature data, including magic number + binmode(STDOUT); + print substr($buf, $module_len); +} elsif ($part eq "-d") { + # Just the descriptor values as a sequence of numbers + print join(" ", @info), "\n"; +} elsif ($part eq "-n") { + # Just the signer's name + print STDERR "No signer's name for PKCS#7 message type sig\n" + if ($id_type == 2); + binmode(STDOUT); + print $raw_name; +} elsif ($part eq "-k") { + # Just the key identifier + print STDERR "No key ID for PKCS#7 message type sig\n" + if ($id_type == 2); + binmode(STDOUT); + print $raw_kid; +} elsif ($part eq "-s") { + # Just the crypto signature or PKCS#7 message + binmode(STDOUT); + print $raw_sig; +} diff --git a/src/net/scripts/extract-sys-certs.pl b/src/net/scripts/extract-sys-certs.pl new file mode 100755 index 0000000..fa8ab15 --- /dev/null +++ b/src/net/scripts/extract-sys-certs.pl @@ -0,0 +1,159 @@ +#!/usr/bin/env perl +# SPDX-License-Identifier: GPL-2.0 +# +use warnings; +use strict; +use Math::BigInt; +use Fcntl "SEEK_SET"; + +die "Format: $0 [-s <systemmap-file>] <vmlinux-file> <keyring-file>\n" + if ($#ARGV != 1 && $#ARGV != 3 || + $#ARGV == 3 && $ARGV[0] ne "-s"); + +my $sysmap = ""; +if ($#ARGV == 3) { + shift; + $sysmap = $ARGV[0]; + shift; +} + +my $vmlinux = $ARGV[0]; +my $keyring = $ARGV[1]; + +# +# Parse the vmlinux section table +# +open FD, "objdump -h $vmlinux |" || die $vmlinux; +my @lines = <FD>; +close(FD) || die $vmlinux; + +my @sections = (); + +foreach my $line (@lines) { + chomp($line); + if ($line =~ /\s*([0-9]+)\s+(\S+)\s+([0-9a-f]+)\s+([0-9a-f]+)\s+([0-9a-f]+)\s+([0-9a-f]+)\s+2[*][*]([0-9]+)/ + ) { + my $seg = $1; + my $name = $2; + my $len = Math::BigInt->new("0x" . $3); + my $vma = Math::BigInt->new("0x" . $4); + my $lma = Math::BigInt->new("0x" . $5); + my $foff = Math::BigInt->new("0x" . $6); + my $align = 2 ** $7; + + push @sections, { name => $name, + vma => $vma, + len => $len, + foff => $foff }; + } +} + +print "Have $#sections sections\n"; + +# +# Try and parse the vmlinux symbol table. If the vmlinux file has been created +# from a vmlinuz file with extract-vmlinux then the symbol table will be empty. +# +open FD, "nm $vmlinux 2>/dev/null |" || die $vmlinux; +@lines = <FD>; +close(FD) || die $vmlinux; + +my %symbols = (); +my $nr_symbols = 0; + +sub parse_symbols(@) { + foreach my $line (@_) { + chomp($line); + if ($line =~ /([0-9a-f]+)\s([a-zA-Z])\s(\S+)/ + ) { + my $addr = "0x" . $1; + my $type = $2; + my $name = $3; + + $symbols{$name} = $addr; + $nr_symbols++; + } + } +} +parse_symbols(@lines); + +if ($nr_symbols == 0 && $sysmap ne "") { + print "No symbols in vmlinux, trying $sysmap\n"; + + open FD, "<$sysmap" || die $sysmap; + @lines = <FD>; + close(FD) || die $sysmap; + parse_symbols(@lines); +} + +die "No symbols available\n" + if ($nr_symbols == 0); + +print "Have $nr_symbols symbols\n"; + +die "Can't find system certificate list" + unless (exists($symbols{"__cert_list_start"}) && + exists($symbols{"system_certificate_list_size"})); + +my $start = Math::BigInt->new($symbols{"__cert_list_start"}); +my $end; +my $size; +my $size_sym = Math::BigInt->new($symbols{"system_certificate_list_size"}); + +open FD, "<$vmlinux" || die $vmlinux; +binmode(FD); + +my $s = undef; +foreach my $sec (@sections) { + my $s_name = $sec->{name}; + my $s_vma = $sec->{vma}; + my $s_len = $sec->{len}; + my $s_foff = $sec->{foff}; + my $s_vend = $s_vma + $s_len; + + next unless ($start >= $s_vma); + next if ($start >= $s_vend); + + die "Certificate list size was not found on the same section\n" + if ($size_sym < $s_vma || $size_sym > $s_vend); + + die "Cert object in multiple sections: ", $s_name, " and ", $s->{name}, "\n" + if ($s); + + my $size_off = $size_sym -$s_vma + $s_foff; + my $packed; + die $vmlinux if (!defined(sysseek(FD, $size_off, SEEK_SET))); + sysread(FD, $packed, 8); + $size = unpack 'L!', $packed; + $end = $start + $size; + + printf "Have %u bytes of certs at VMA 0x%x\n", $size, $start; + + die "Cert object partially overflows section $s_name\n" + if ($end > $s_vend); + + $s = $sec; +} + +die "Cert object not inside a section\n" + unless ($s); + +print "Certificate list in section ", $s->{name}, "\n"; + +my $foff = $start - $s->{vma} + $s->{foff}; + +printf "Certificate list at file offset 0x%x\n", $foff; + +die $vmlinux if (!defined(sysseek(FD, $foff, SEEK_SET))); +my $buf = ""; +my $len = sysread(FD, $buf, $size); +die "$vmlinux" if (!defined($len)); +die "Short read on $vmlinux\n" if ($len != $size); +close(FD) || die $vmlinux; + +open FD, ">$keyring" || die $keyring; +binmode(FD); +$len = syswrite(FD, $buf, $size); +die "$keyring" if (!defined($len)); +die "Short write on $keyring\n" if ($len != $size); +close(FD) || die $keyring; diff --git a/src/net/scripts/extract-vmlinux b/src/net/scripts/extract-vmlinux new file mode 100755 index 0000000..8995cd3 --- /dev/null +++ b/src/net/scripts/extract-vmlinux @@ -0,0 +1,64 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0-only +# ---------------------------------------------------------------------- +# extract-vmlinux - Extract uncompressed vmlinux from a kernel image +# +# Inspired from extract-ikconfig +# (c) 2009,2010 Dick Streefland <dick@streefland.net> +# +# (c) 2011 Corentin Chary <corentin.chary@gmail.com> +# +# ---------------------------------------------------------------------- + +check_vmlinux() +{ + # Use readelf to check if it's a valid ELF + # TODO: find a better to way to check that it's really vmlinux + # and not just an elf + readelf -h $1 > /dev/null 2>&1 || return 1 + + cat $1 + exit 0 +} + +try_decompress() +{ + # The obscure use of the "tr" filter is to work around older versions of + # "grep" that report the byte offset of the line instead of the pattern. + + # Try to find the header ($1) and decompress from here + for pos in `tr "$1\n$2" "\n$2=" < "$img" | grep -abo "^$2"` + do + pos=${pos%%:*} + tail -c+$pos "$img" | $3 > $tmp 2> /dev/null + check_vmlinux $tmp + done +} + +# Check invocation: +me=${0##*/} +img=$1 +if [ $# -ne 1 -o ! -s "$img" ] +then + echo "Usage: $me <kernel-image>" >&2 + exit 2 +fi + +# Prepare temp files: +tmp=$(mktemp /tmp/vmlinux-XXX) +trap "rm -f $tmp" 0 + +# That didn't work, so retry after decompression. +try_decompress '\037\213\010' xy gunzip +try_decompress '\3757zXZ\000' abcde unxz +try_decompress 'BZh' xy bunzip2 +try_decompress '\135\0\0\0' xxx unlzma +try_decompress '\211\114\132' xy 'lzop -d' +try_decompress '\002!L\030' xxx 'lz4 -d' +try_decompress '(\265/\375' xxx unzstd + +# Finally check for uncompressed images or objects: +check_vmlinux $img + +# Bail out: +echo "$me: Cannot find vmlinux." >&2 diff --git a/src/net/scripts/extract_xc3028.pl b/src/net/scripts/extract_xc3028.pl new file mode 100755 index 0000000..e1c9af2 --- /dev/null +++ b/src/net/scripts/extract_xc3028.pl @@ -0,0 +1,1717 @@ +#!/usr/bin/env perl +# SPDX-License-Identifier: GPL-2.0-only + +# Copyright (c) Mauro Carvalho Chehab <mchehab@kernel.org> +# +# In order to use, you need to: +# 1) Download the windows driver with something like: +# Version 2.4 +# wget http://www.twinhan.com/files/AW/BDA T/20080303_V1.0.6.7.zip +# or wget http://www.stefanringel.de/pub/20080303_V1.0.6.7.zip +# Version 2.7 +# wget http://www.steventoth.net/linux/xc5000/HVR-12x0-14x0-17x0_1_25_25271_WHQL.zip +# 2) Extract the files from the zip into the current dir: +# unzip -j 20080303_V1.0.6.7.zip 20080303_v1.0.6.7/UDXTTM6000.sys +# unzip -j HVR-12x0-14x0-17x0_1_25_25271_WHQL.zip Driver85/hcw85bda.sys +# 3) run the script: +# ./extract_xc3028.pl +# 4) copy the generated files: +# cp xc3028-v24.fw /lib/firmware +# cp xc3028-v27.fw /lib/firmware + +#use strict; +use IO::Handle; + +my $debug=0; + +sub verify ($$) +{ + my ($filename, $hash) = @_; + my ($testhash); + + if (system("which md5sum > /dev/null 2>&1")) { + die "This firmware requires the md5sum command - see http://www.gnu.org/software/coreutils/\n"; + } + + open(CMD, "md5sum ".$filename."|"); + $testhash = <CMD>; + $testhash =~ /([a-zA-Z0-9]*)/; + $testhash = $1; + close CMD; + die "Hash of extracted file does not match (found $testhash, expected $hash!\n" if ($testhash ne $hash); +} + +sub get_hunk ($$) +{ + my ($offset, $length) = @_; + my ($chunklength, $buf, $rcount, $out); + + sysseek(INFILE, $offset, SEEK_SET); + while ($length > 0) { + # Calc chunk size + $chunklength = 2048; + $chunklength = $length if ($chunklength > $length); + + $rcount = sysread(INFILE, $buf, $chunklength); + die "Ran out of data\n" if ($rcount != $chunklength); + $out .= $buf; + $length -= $rcount; + } + return $out; +} + +sub write_le16($) +{ + my $val = shift; + my $msb = ($val >> 8) &0xff; + my $lsb = $val & 0xff; + + syswrite(OUTFILE, chr($lsb).chr($msb)); +} + +sub write_le32($) +{ + my $val = shift; + my $l3 = ($val >> 24) & 0xff; + my $l2 = ($val >> 16) & 0xff; + my $l1 = ($val >> 8) & 0xff; + my $l0 = $val & 0xff; + + syswrite(OUTFILE, chr($l0).chr($l1).chr($l2).chr($l3)); +} + +sub write_le64($$) +{ + my $msb_val = shift; + my $lsb_val = shift; + my $l7 = ($msb_val >> 24) & 0xff; + my $l6 = ($msb_val >> 16) & 0xff; + my $l5 = ($msb_val >> 8) & 0xff; + my $l4 = $msb_val & 0xff; + + my $l3 = ($lsb_val >> 24) & 0xff; + my $l2 = ($lsb_val >> 16) & 0xff; + my $l1 = ($lsb_val >> 8) & 0xff; + my $l0 = $lsb_val & 0xff; + + syswrite(OUTFILE, + chr($l0).chr($l1).chr($l2).chr($l3). + chr($l4).chr($l5).chr($l6).chr($l7)); +} + +sub write_hunk($$) +{ + my ($offset, $length) = @_; + my $out = get_hunk($offset, $length); + + printf "(len %d) ",$length if ($debug); + + for (my $i=0;$i<$length;$i++) { + printf "%02x ",ord(substr($out,$i,1)) if ($debug); + } + printf "\n" if ($debug); + + syswrite(OUTFILE, $out); +} + +sub write_hunk_fix_endian($$) +{ + my ($offset, $length) = @_; + my $out = get_hunk($offset, $length); + + printf "(len_fix %d) ",$length if ($debug); + + for (my $i=0;$i<$length;$i++) { + printf "%02x ",ord(substr($out,$i,1)) if ($debug); + } + printf "\n" if ($debug); + + my $i=0; + while ($i<$length) { + my $size = ord(substr($out,$i,1))*256+ord(substr($out,$i+1,1)); + syswrite(OUTFILE, substr($out,$i+1,1)); + syswrite(OUTFILE, substr($out,$i,1)); + $i+=2; + if ($size>0 && $size <0x8000) { + for (my $j=0;$j<$size;$j++) { + syswrite(OUTFILE, substr($out,$j+$i,1)); + } + $i+=$size; + } + } +} + +sub main_firmware_24($$$$) +{ + my $out; + my $j=0; + my $outfile = shift; + my $name = shift; + my $version = shift; + my $nr_desc = shift; + + for ($j = length($name); $j <32; $j++) { + $name = $name.chr(0); + } + + open OUTFILE, ">$outfile"; + syswrite(OUTFILE, $name); + write_le16($version); + write_le16($nr_desc); + + # + # Firmware 0, type: BASE FW F8MHZ (0x00000003), id: (0000000000000000), size: 6635 + # + + write_le32(0x00000003); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le32(6635); # Size + write_hunk_fix_endian(257752, 6635); + + # + # Firmware 1, type: BASE FW F8MHZ MTS (0x00000007), id: (0000000000000000), size: 6635 + # + + write_le32(0x00000007); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le32(6635); # Size + write_hunk_fix_endian(264392, 6635); + + # + # Firmware 2, type: BASE FW FM (0x00000401), id: (0000000000000000), size: 6525 + # + + write_le32(0x00000401); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le32(6525); # Size + write_hunk_fix_endian(271040, 6525); + + # + # Firmware 3, type: BASE FW FM INPUT1 (0x00000c01), id: (0000000000000000), size: 6539 + # + + write_le32(0x00000c01); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le32(6539); # Size + write_hunk_fix_endian(277568, 6539); + + # + # Firmware 4, type: BASE FW (0x00000001), id: (0000000000000000), size: 6633 + # + + write_le32(0x00000001); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le32(6633); # Size + write_hunk_fix_endian(284120, 6633); + + # + # Firmware 5, type: BASE FW MTS (0x00000005), id: (0000000000000000), size: 6617 + # + + write_le32(0x00000005); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le32(6617); # Size + write_hunk_fix_endian(290760, 6617); + + # + # Firmware 6, type: STD FW (0x00000000), id: PAL/BG A2/A (0000000100000007), size: 161 + # + + write_le32(0x00000000); # Type + write_le64(0x00000001, 0x00000007); # ID + write_le32(161); # Size + write_hunk_fix_endian(297384, 161); + + # + # Firmware 7, type: STD FW MTS (0x00000004), id: PAL/BG A2/A (0000000100000007), size: 169 + # + + write_le32(0x00000004); # Type + write_le64(0x00000001, 0x00000007); # ID + write_le32(169); # Size + write_hunk_fix_endian(297552, 169); + + # + # Firmware 8, type: STD FW (0x00000000), id: PAL/BG A2/B (0000000200000007), size: 161 + # + + write_le32(0x00000000); # Type + write_le64(0x00000002, 0x00000007); # ID + write_le32(161); # Size + write_hunk_fix_endian(297728, 161); + + # + # Firmware 9, type: STD FW MTS (0x00000004), id: PAL/BG A2/B (0000000200000007), size: 169 + # + + write_le32(0x00000004); # Type + write_le64(0x00000002, 0x00000007); # ID + write_le32(169); # Size + write_hunk_fix_endian(297896, 169); + + # + # Firmware 10, type: STD FW (0x00000000), id: PAL/BG NICAM/A (0000000400000007), size: 161 + # + + write_le32(0x00000000); # Type + write_le64(0x00000004, 0x00000007); # ID + write_le32(161); # Size + write_hunk_fix_endian(298072, 161); + + # + # Firmware 11, type: STD FW MTS (0x00000004), id: PAL/BG NICAM/A (0000000400000007), size: 169 + # + + write_le32(0x00000004); # Type + write_le64(0x00000004, 0x00000007); # ID + write_le32(169); # Size + write_hunk_fix_endian(298240, 169); + + # + # Firmware 12, type: STD FW (0x00000000), id: PAL/BG NICAM/B (0000000800000007), size: 161 + # + + write_le32(0x00000000); # Type + write_le64(0x00000008, 0x00000007); # ID + write_le32(161); # Size + write_hunk_fix_endian(298416, 161); + + # + # Firmware 13, type: STD FW MTS (0x00000004), id: PAL/BG NICAM/B (0000000800000007), size: 169 + # + + write_le32(0x00000004); # Type + write_le64(0x00000008, 0x00000007); # ID + write_le32(169); # Size + write_hunk_fix_endian(298584, 169); + + # + # Firmware 14, type: STD FW (0x00000000), id: PAL/DK A2 (00000003000000e0), size: 161 + # + + write_le32(0x00000000); # Type + write_le64(0x00000003, 0x000000e0); # ID + write_le32(161); # Size + write_hunk_fix_endian(298760, 161); + + # + # Firmware 15, type: STD FW MTS (0x00000004), id: PAL/DK A2 (00000003000000e0), size: 169 + # + + write_le32(0x00000004); # Type + write_le64(0x00000003, 0x000000e0); # ID + write_le32(169); # Size + write_hunk_fix_endian(298928, 169); + + # + # Firmware 16, type: STD FW (0x00000000), id: PAL/DK NICAM (0000000c000000e0), size: 161 + # + + write_le32(0x00000000); # Type + write_le64(0x0000000c, 0x000000e0); # ID + write_le32(161); # Size + write_hunk_fix_endian(299104, 161); + + # + # Firmware 17, type: STD FW MTS (0x00000004), id: PAL/DK NICAM (0000000c000000e0), size: 169 + # + + write_le32(0x00000004); # Type + write_le64(0x0000000c, 0x000000e0); # ID + write_le32(169); # Size + write_hunk_fix_endian(299272, 169); + + # + # Firmware 18, type: STD FW (0x00000000), id: SECAM/K1 (0000000000200000), size: 161 + # + + write_le32(0x00000000); # Type + write_le64(0x00000000, 0x00200000); # ID + write_le32(161); # Size + write_hunk_fix_endian(299448, 161); + + # + # Firmware 19, type: STD FW MTS (0x00000004), id: SECAM/K1 (0000000000200000), size: 169 + # + + write_le32(0x00000004); # Type + write_le64(0x00000000, 0x00200000); # ID + write_le32(169); # Size + write_hunk_fix_endian(299616, 169); + + # + # Firmware 20, type: STD FW (0x00000000), id: SECAM/K3 (0000000004000000), size: 161 + # + + write_le32(0x00000000); # Type + write_le64(0x00000000, 0x04000000); # ID + write_le32(161); # Size + write_hunk_fix_endian(299792, 161); + + # + # Firmware 21, type: STD FW MTS (0x00000004), id: SECAM/K3 (0000000004000000), size: 169 + # + + write_le32(0x00000004); # Type + write_le64(0x00000000, 0x04000000); # ID + write_le32(169); # Size + write_hunk_fix_endian(299960, 169); + + # + # Firmware 22, type: STD FW D2633 DTV6 ATSC (0x00010030), id: (0000000000000000), size: 149 + # + + write_le32(0x00010030); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le32(149); # Size + write_hunk_fix_endian(300136, 149); + + # + # Firmware 23, type: STD FW D2620 DTV6 QAM (0x00000068), id: (0000000000000000), size: 149 + # + + write_le32(0x00000068); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le32(149); # Size + write_hunk_fix_endian(300296, 149); + + # + # Firmware 24, type: STD FW D2633 DTV6 QAM (0x00000070), id: (0000000000000000), size: 149 + # + + write_le32(0x00000070); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le32(149); # Size + write_hunk_fix_endian(300448, 149); + + # + # Firmware 25, type: STD FW D2620 DTV7 (0x00000088), id: (0000000000000000), size: 149 + # + + write_le32(0x00000088); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le32(149); # Size + write_hunk_fix_endian(300608, 149); + + # + # Firmware 26, type: STD FW D2633 DTV7 (0x00000090), id: (0000000000000000), size: 149 + # + + write_le32(0x00000090); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le32(149); # Size + write_hunk_fix_endian(300760, 149); + + # + # Firmware 27, type: STD FW D2620 DTV78 (0x00000108), id: (0000000000000000), size: 149 + # + + write_le32(0x00000108); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le32(149); # Size + write_hunk_fix_endian(300920, 149); + + # + # Firmware 28, type: STD FW D2633 DTV78 (0x00000110), id: (0000000000000000), size: 149 + # + + write_le32(0x00000110); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le32(149); # Size + write_hunk_fix_endian(301072, 149); + + # + # Firmware 29, type: STD FW D2620 DTV8 (0x00000208), id: (0000000000000000), size: 149 + # + + write_le32(0x00000208); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le32(149); # Size + write_hunk_fix_endian(301232, 149); + + # + # Firmware 30, type: STD FW D2633 DTV8 (0x00000210), id: (0000000000000000), size: 149 + # + + write_le32(0x00000210); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le32(149); # Size + write_hunk_fix_endian(301384, 149); + + # + # Firmware 31, type: STD FW FM (0x00000400), id: (0000000000000000), size: 135 + # + + write_le32(0x00000400); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le32(135); # Size + write_hunk_fix_endian(301554, 135); + + # + # Firmware 32, type: STD FW (0x00000000), id: PAL/I (0000000000000010), size: 161 + # + + write_le32(0x00000000); # Type + write_le64(0x00000000, 0x00000010); # ID + write_le32(161); # Size + write_hunk_fix_endian(301688, 161); + + # + # Firmware 33, type: STD FW MTS (0x00000004), id: PAL/I (0000000000000010), size: 169 + # + + write_le32(0x00000004); # Type + write_le64(0x00000000, 0x00000010); # ID + write_le32(169); # Size + write_hunk_fix_endian(301856, 169); + + # + # Firmware 34, type: STD FW (0x00000000), id: SECAM/L AM (0000001000400000), size: 169 + # + + # + # Firmware 35, type: STD FW (0x00000000), id: SECAM/L NICAM (0000000c00400000), size: 161 + # + + write_le32(0x00000000); # Type + write_le64(0x0000000c, 0x00400000); # ID + write_le32(161); # Size + write_hunk_fix_endian(302032, 161); + + # + # Firmware 36, type: STD FW (0x00000000), id: SECAM/Lc (0000000000800000), size: 161 + # + + write_le32(0x00000000); # Type + write_le64(0x00000000, 0x00800000); # ID + write_le32(161); # Size + write_hunk_fix_endian(302200, 161); + + # + # Firmware 37, type: STD FW (0x00000000), id: NTSC/M Kr (0000000000008000), size: 161 + # + + write_le32(0x00000000); # Type + write_le64(0x00000000, 0x00008000); # ID + write_le32(161); # Size + write_hunk_fix_endian(302368, 161); + + # + # Firmware 38, type: STD FW LCD (0x00001000), id: NTSC/M Kr (0000000000008000), size: 161 + # + + write_le32(0x00001000); # Type + write_le64(0x00000000, 0x00008000); # ID + write_le32(161); # Size + write_hunk_fix_endian(302536, 161); + + # + # Firmware 39, type: STD FW LCD NOGD (0x00003000), id: NTSC/M Kr (0000000000008000), size: 161 + # + + write_le32(0x00003000); # Type + write_le64(0x00000000, 0x00008000); # ID + write_le32(161); # Size + write_hunk_fix_endian(302704, 161); + + # + # Firmware 40, type: STD FW MTS (0x00000004), id: NTSC/M Kr (0000000000008000), size: 169 + # + + write_le32(0x00000004); # Type + write_le64(0x00000000, 0x00008000); # ID + write_le32(169); # Size + write_hunk_fix_endian(302872, 169); + + # + # Firmware 41, type: STD FW (0x00000000), id: NTSC PAL/M PAL/N (000000000000b700), size: 161 + # + + write_le32(0x00000000); # Type + write_le64(0x00000000, 0x0000b700); # ID + write_le32(161); # Size + write_hunk_fix_endian(303048, 161); + + # + # Firmware 42, type: STD FW LCD (0x00001000), id: NTSC PAL/M PAL/N (000000000000b700), size: 161 + # + + write_le32(0x00001000); # Type + write_le64(0x00000000, 0x0000b700); # ID + write_le32(161); # Size + write_hunk_fix_endian(303216, 161); + + # + # Firmware 43, type: STD FW LCD NOGD (0x00003000), id: NTSC PAL/M PAL/N (000000000000b700), size: 161 + # + + write_le32(0x00003000); # Type + write_le64(0x00000000, 0x0000b700); # ID + write_le32(161); # Size + write_hunk_fix_endian(303384, 161); + + # + # Firmware 44, type: STD FW (0x00000000), id: NTSC/M Jp (0000000000002000), size: 161 + # + + write_le32(0x00000000); # Type + write_le64(0x00000000, 0x00002000); # ID + write_le32(161); # Size + write_hunk_fix_endian(303552, 161); + + # + # Firmware 45, type: STD FW MTS (0x00000004), id: NTSC PAL/M PAL/N (000000000000b700), size: 169 + # + + write_le32(0x00000004); # Type + write_le64(0x00000000, 0x0000b700); # ID + write_le32(169); # Size + write_hunk_fix_endian(303720, 169); + + # + # Firmware 46, type: STD FW MTS LCD (0x00001004), id: NTSC PAL/M PAL/N (000000000000b700), size: 169 + # + + write_le32(0x00001004); # Type + write_le64(0x00000000, 0x0000b700); # ID + write_le32(169); # Size + write_hunk_fix_endian(303896, 169); + + # + # Firmware 47, type: STD FW MTS LCD NOGD (0x00003004), id: NTSC PAL/M PAL/N (000000000000b700), size: 169 + # + + write_le32(0x00003004); # Type + write_le64(0x00000000, 0x0000b700); # ID + write_le32(169); # Size + write_hunk_fix_endian(304072, 169); + + # + # Firmware 48, type: SCODE FW HAS IF (0x60000000), IF = 3.28 MHz id: (0000000000000000), size: 192 + # + + write_le32(0x60000000); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le16(3280); # IF + write_le32(192); # Size + write_hunk(309048, 192); + + # + # Firmware 49, type: SCODE FW HAS IF (0x60000000), IF = 3.30 MHz id: (0000000000000000), size: 192 + # + +# write_le32(0x60000000); # Type +# write_le64(0x00000000, 0x00000000); # ID +# write_le16(3300); # IF +# write_le32(192); # Size +# write_hunk(304440, 192); + + # + # Firmware 50, type: SCODE FW HAS IF (0x60000000), IF = 3.44 MHz id: (0000000000000000), size: 192 + # + + write_le32(0x60000000); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le16(3440); # IF + write_le32(192); # Size + write_hunk(309432, 192); + + # + # Firmware 51, type: SCODE FW HAS IF (0x60000000), IF = 3.46 MHz id: (0000000000000000), size: 192 + # + + write_le32(0x60000000); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le16(3460); # IF + write_le32(192); # Size + write_hunk(309624, 192); + + # + # Firmware 52, type: SCODE FW DTV6 ATSC OREN36 HAS IF (0x60210020), IF = 3.80 MHz id: (0000000000000000), size: 192 + # + + write_le32(0x60210020); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le16(3800); # IF + write_le32(192); # Size + write_hunk(306936, 192); + + # + # Firmware 53, type: SCODE FW HAS IF (0x60000000), IF = 4.00 MHz id: (0000000000000000), size: 192 + # + + write_le32(0x60000000); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le16(4000); # IF + write_le32(192); # Size + write_hunk(309240, 192); + + # + # Firmware 54, type: SCODE FW DTV6 ATSC TOYOTA388 HAS IF (0x60410020), IF = 4.08 MHz id: (0000000000000000), size: 192 + # + + write_le32(0x60410020); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le16(4080); # IF + write_le32(192); # Size + write_hunk(307128, 192); + + # + # Firmware 55, type: SCODE FW HAS IF (0x60000000), IF = 4.20 MHz id: (0000000000000000), size: 192 + # + + write_le32(0x60000000); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le16(4200); # IF + write_le32(192); # Size + write_hunk(308856, 192); + + # + # Firmware 56, type: SCODE FW MONO HAS IF (0x60008000), IF = 4.32 MHz id: NTSC/M Kr (0000000000008000), size: 192 + # + + write_le32(0x60008000); # Type + write_le64(0x00000000, 0x00008000); # ID + write_le16(4320); # IF + write_le32(192); # Size + write_hunk(305208, 192); + + # + # Firmware 57, type: SCODE FW HAS IF (0x60000000), IF = 4.45 MHz id: (0000000000000000), size: 192 + # + + write_le32(0x60000000); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le16(4450); # IF + write_le32(192); # Size + write_hunk(309816, 192); + + # + # Firmware 58, type: SCODE FW MTS LCD NOGD MONO IF HAS IF (0x6002b004), IF = 4.50 MHz id: NTSC PAL/M PAL/N (000000000000b700), size: 192 + # + + write_le32(0x6002b004); # Type + write_le64(0x00000000, 0x0000b700); # ID + write_le16(4500); # IF + write_le32(192); # Size + write_hunk(304824, 192); + + # + # Firmware 59, type: SCODE FW LCD NOGD IF HAS IF (0x60023000), IF = 4.60 MHz id: NTSC/M Kr (0000000000008000), size: 192 + # + + write_le32(0x60023000); # Type + write_le64(0x00000000, 0x00008000); # ID + write_le16(4600); # IF + write_le32(192); # Size + write_hunk(305016, 192); + + # + # Firmware 60, type: SCODE FW DTV6 QAM DTV7 DTV78 DTV8 ZARLINK456 HAS IF (0x620003e0), IF = 4.76 MHz id: (0000000000000000), size: 192 + # + + write_le32(0x620003e0); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le16(4760); # IF + write_le32(192); # Size + write_hunk(304440, 192); + + # + # Firmware 61, type: SCODE FW HAS IF (0x60000000), IF = 4.94 MHz id: (0000000000000000), size: 192 + # + + write_le32(0x60000000); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le16(4940); # IF + write_le32(192); # Size + write_hunk(308664, 192); + + # + # Firmware 62, type: SCODE FW HAS IF (0x60000000), IF = 5.26 MHz id: (0000000000000000), size: 192 + # + + write_le32(0x60000000); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le16(5260); # IF + write_le32(192); # Size + write_hunk(307704, 192); + + # + # Firmware 63, type: SCODE FW MONO HAS IF (0x60008000), IF = 5.32 MHz id: PAL/BG A2 NICAM (0000000f00000007), size: 192 + # + + write_le32(0x60008000); # Type + write_le64(0x0000000f, 0x00000007); # ID + write_le16(5320); # IF + write_le32(192); # Size + write_hunk(307896, 192); + + # + # Firmware 64, type: SCODE FW DTV7 DTV78 DTV8 DIBCOM52 CHINA HAS IF (0x65000380), IF = 5.40 MHz id: (0000000000000000), size: 192 + # + + write_le32(0x65000380); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le16(5400); # IF + write_le32(192); # Size + write_hunk(304248, 192); + + # + # Firmware 65, type: SCODE FW DTV6 ATSC OREN538 HAS IF (0x60110020), IF = 5.58 MHz id: (0000000000000000), size: 192 + # + + write_le32(0x60110020); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le16(5580); # IF + write_le32(192); # Size + write_hunk(306744, 192); + + # + # Firmware 66, type: SCODE FW HAS IF (0x60000000), IF = 5.64 MHz id: PAL/BG A2 (0000000300000007), size: 192 + # + + write_le32(0x60000000); # Type + write_le64(0x00000003, 0x00000007); # ID + write_le16(5640); # IF + write_le32(192); # Size + write_hunk(305592, 192); + + # + # Firmware 67, type: SCODE FW HAS IF (0x60000000), IF = 5.74 MHz id: PAL/BG NICAM (0000000c00000007), size: 192 + # + + write_le32(0x60000000); # Type + write_le64(0x0000000c, 0x00000007); # ID + write_le16(5740); # IF + write_le32(192); # Size + write_hunk(305784, 192); + + # + # Firmware 68, type: SCODE FW HAS IF (0x60000000), IF = 5.90 MHz id: (0000000000000000), size: 192 + # + + write_le32(0x60000000); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le16(5900); # IF + write_le32(192); # Size + write_hunk(307512, 192); + + # + # Firmware 69, type: SCODE FW MONO HAS IF (0x60008000), IF = 6.00 MHz id: PAL/DK PAL/I SECAM/K3 SECAM/L SECAM/Lc NICAM (0000000c04c000f0), size: 192 + # + + write_le32(0x60008000); # Type + write_le64(0x0000000c, 0x04c000f0); # ID + write_le16(6000); # IF + write_le32(192); # Size + write_hunk(305576, 192); + + # + # Firmware 70, type: SCODE FW DTV6 QAM ATSC LG60 F6MHZ HAS IF (0x68050060), IF = 6.20 MHz id: (0000000000000000), size: 192 + # + + write_le32(0x68050060); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le16(6200); # IF + write_le32(192); # Size + write_hunk(306552, 192); + + # + # Firmware 71, type: SCODE FW HAS IF (0x60000000), IF = 6.24 MHz id: PAL/I (0000000000000010), size: 192 + # + + write_le32(0x60000000); # Type + write_le64(0x00000000, 0x00000010); # ID + write_le16(6240); # IF + write_le32(192); # Size + write_hunk(305400, 192); + + # + # Firmware 72, type: SCODE FW MONO HAS IF (0x60008000), IF = 6.32 MHz id: SECAM/K1 (0000000000200000), size: 192 + # + + write_le32(0x60008000); # Type + write_le64(0x00000000, 0x00200000); # ID + write_le16(6320); # IF + write_le32(192); # Size + write_hunk(308472, 192); + + # + # Firmware 73, type: SCODE FW HAS IF (0x60000000), IF = 6.34 MHz id: SECAM/K1 (0000000000200000), size: 192 + # + + write_le32(0x60000000); # Type + write_le64(0x00000000, 0x00200000); # ID + write_le16(6340); # IF + write_le32(192); # Size + write_hunk(306360, 192); + + # + # Firmware 74, type: SCODE FW MONO HAS IF (0x60008000), IF = 6.50 MHz id: PAL/DK SECAM/K3 SECAM/L NICAM (0000000c044000e0), size: 192 + # + + write_le32(0x60008000); # Type + write_le64(0x0000000c, 0x044000e0); # ID + write_le16(6500); # IF + write_le32(192); # Size + write_hunk(308280, 192); + + # + # Firmware 75, type: SCODE FW DTV6 ATSC ATI638 HAS IF (0x60090020), IF = 6.58 MHz id: (0000000000000000), size: 192 + # + + write_le32(0x60090020); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le16(6580); # IF + write_le32(192); # Size + write_hunk(304632, 192); + + # + # Firmware 76, type: SCODE FW HAS IF (0x60000000), IF = 6.60 MHz id: PAL/DK A2 (00000003000000e0), size: 192 + # + + write_le32(0x60000000); # Type + write_le64(0x00000003, 0x000000e0); # ID + write_le16(6600); # IF + write_le32(192); # Size + write_hunk(306168, 192); + + # + # Firmware 77, type: SCODE FW MONO HAS IF (0x60008000), IF = 6.68 MHz id: PAL/DK A2 (00000003000000e0), size: 192 + # + + write_le32(0x60008000); # Type + write_le64(0x00000003, 0x000000e0); # ID + write_le16(6680); # IF + write_le32(192); # Size + write_hunk(308088, 192); + + # + # Firmware 78, type: SCODE FW DTV6 ATSC TOYOTA794 HAS IF (0x60810020), IF = 8.14 MHz id: (0000000000000000), size: 192 + # + + write_le32(0x60810020); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le16(8140); # IF + write_le32(192); # Size + write_hunk(307320, 192); + + # + # Firmware 79, type: SCODE FW HAS IF (0x60000000), IF = 8.20 MHz id: (0000000000000000), size: 192 + # + +# write_le32(0x60000000); # Type +# write_le64(0x00000000, 0x00000000); # ID +# write_le16(8200); # IF +# write_le32(192); # Size +# write_hunk(308088, 192); +} + +sub main_firmware_27($$$$) +{ + my $out; + my $j=0; + my $outfile = shift; + my $name = shift; + my $version = shift; + my $nr_desc = shift; + + for ($j = length($name); $j <32; $j++) { + $name = $name.chr(0); + } + + open OUTFILE, ">$outfile"; + syswrite(OUTFILE, $name); + write_le16($version); + write_le16($nr_desc); + + # + # Firmware 0, type: BASE FW F8MHZ (0x00000003), id: (0000000000000000), size: 8718 + # + + write_le32(0x00000003); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le32(8718); # Size + write_hunk_fix_endian(813432, 8718); + + # + # Firmware 1, type: BASE FW F8MHZ MTS (0x00000007), id: (0000000000000000), size: 8712 + # + + write_le32(0x00000007); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le32(8712); # Size + write_hunk_fix_endian(822152, 8712); + + # + # Firmware 2, type: BASE FW FM (0x00000401), id: (0000000000000000), size: 8562 + # + + write_le32(0x00000401); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le32(8562); # Size + write_hunk_fix_endian(830872, 8562); + + # + # Firmware 3, type: BASE FW FM INPUT1 (0x00000c01), id: (0000000000000000), size: 8576 + # + + write_le32(0x00000c01); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le32(8576); # Size + write_hunk_fix_endian(839440, 8576); + + # + # Firmware 4, type: BASE FW (0x00000001), id: (0000000000000000), size: 8706 + # + + write_le32(0x00000001); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le32(8706); # Size + write_hunk_fix_endian(848024, 8706); + + # + # Firmware 5, type: BASE FW MTS (0x00000005), id: (0000000000000000), size: 8682 + # + + write_le32(0x00000005); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le32(8682); # Size + write_hunk_fix_endian(856736, 8682); + + # + # Firmware 6, type: STD FW (0x00000000), id: PAL/BG A2/A (0000000100000007), size: 161 + # + + write_le32(0x00000000); # Type + write_le64(0x00000001, 0x00000007); # ID + write_le32(161); # Size + write_hunk_fix_endian(865424, 161); + + # + # Firmware 7, type: STD FW MTS (0x00000004), id: PAL/BG A2/A (0000000100000007), size: 169 + # + + write_le32(0x00000004); # Type + write_le64(0x00000001, 0x00000007); # ID + write_le32(169); # Size + write_hunk_fix_endian(865592, 169); + + # + # Firmware 8, type: STD FW (0x00000000), id: PAL/BG A2/B (0000000200000007), size: 161 + # + + write_le32(0x00000000); # Type + write_le64(0x00000002, 0x00000007); # ID + write_le32(161); # Size + write_hunk_fix_endian(865424, 161); + + # + # Firmware 9, type: STD FW MTS (0x00000004), id: PAL/BG A2/B (0000000200000007), size: 169 + # + + write_le32(0x00000004); # Type + write_le64(0x00000002, 0x00000007); # ID + write_le32(169); # Size + write_hunk_fix_endian(865592, 169); + + # + # Firmware 10, type: STD FW (0x00000000), id: PAL/BG NICAM/A (0000000400000007), size: 161 + # + + write_le32(0x00000000); # Type + write_le64(0x00000004, 0x00000007); # ID + write_le32(161); # Size + write_hunk_fix_endian(866112, 161); + + # + # Firmware 11, type: STD FW MTS (0x00000004), id: PAL/BG NICAM/A (0000000400000007), size: 169 + # + + write_le32(0x00000004); # Type + write_le64(0x00000004, 0x00000007); # ID + write_le32(169); # Size + write_hunk_fix_endian(866280, 169); + + # + # Firmware 12, type: STD FW (0x00000000), id: PAL/BG NICAM/B (0000000800000007), size: 161 + # + + write_le32(0x00000000); # Type + write_le64(0x00000008, 0x00000007); # ID + write_le32(161); # Size + write_hunk_fix_endian(866112, 161); + + # + # Firmware 13, type: STD FW MTS (0x00000004), id: PAL/BG NICAM/B (0000000800000007), size: 169 + # + + write_le32(0x00000004); # Type + write_le64(0x00000008, 0x00000007); # ID + write_le32(169); # Size + write_hunk_fix_endian(866280, 169); + + # + # Firmware 14, type: STD FW (0x00000000), id: PAL/DK A2 (00000003000000e0), size: 161 + # + + write_le32(0x00000000); # Type + write_le64(0x00000003, 0x000000e0); # ID + write_le32(161); # Size + write_hunk_fix_endian(866800, 161); + + # + # Firmware 15, type: STD FW MTS (0x00000004), id: PAL/DK A2 (00000003000000e0), size: 169 + # + + write_le32(0x00000004); # Type + write_le64(0x00000003, 0x000000e0); # ID + write_le32(169); # Size + write_hunk_fix_endian(866968, 169); + + # + # Firmware 16, type: STD FW (0x00000000), id: PAL/DK NICAM (0000000c000000e0), size: 161 + # + + write_le32(0x00000000); # Type + write_le64(0x0000000c, 0x000000e0); # ID + write_le32(161); # Size + write_hunk_fix_endian(867144, 161); + + # + # Firmware 17, type: STD FW MTS (0x00000004), id: PAL/DK NICAM (0000000c000000e0), size: 169 + # + + write_le32(0x00000004); # Type + write_le64(0x0000000c, 0x000000e0); # ID + write_le32(169); # Size + write_hunk_fix_endian(867312, 169); + + # + # Firmware 18, type: STD FW (0x00000000), id: SECAM/K1 (0000000000200000), size: 161 + # + + write_le32(0x00000000); # Type + write_le64(0x00000000, 0x00200000); # ID + write_le32(161); # Size + write_hunk_fix_endian(867488, 161); + + # + # Firmware 19, type: STD FW MTS (0x00000004), id: SECAM/K1 (0000000000200000), size: 169 + # + + write_le32(0x00000004); # Type + write_le64(0x00000000, 0x00200000); # ID + write_le32(169); # Size + write_hunk_fix_endian(867656, 169); + + # + # Firmware 20, type: STD FW (0x00000000), id: SECAM/K3 (0000000004000000), size: 161 + # + + write_le32(0x00000000); # Type + write_le64(0x00000000, 0x04000000); # ID + write_le32(161); # Size + write_hunk_fix_endian(867832, 161); + + # + # Firmware 21, type: STD FW MTS (0x00000004), id: SECAM/K3 (0000000004000000), size: 169 + # + + write_le32(0x00000004); # Type + write_le64(0x00000000, 0x04000000); # ID + write_le32(169); # Size + write_hunk_fix_endian(868000, 169); + + # + # Firmware 22, type: STD FW D2633 DTV6 ATSC (0x00010030), id: (0000000000000000), size: 149 + # + + write_le32(0x00010030); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le32(149); # Size + write_hunk_fix_endian(868176, 149); + + # + # Firmware 23, type: STD FW D2620 DTV6 QAM (0x00000068), id: (0000000000000000), size: 149 + # + + write_le32(0x00000068); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le32(149); # Size + write_hunk_fix_endian(868336, 149); + + # + # Firmware 24, type: STD FW D2633 DTV6 QAM (0x00000070), id: (0000000000000000), size: 149 + # + + write_le32(0x00000070); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le32(149); # Size + write_hunk_fix_endian(868488, 149); + + # + # Firmware 25, type: STD FW D2620 DTV7 (0x00000088), id: (0000000000000000), size: 149 + # + + write_le32(0x00000088); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le32(149); # Size + write_hunk_fix_endian(868648, 149); + + # + # Firmware 26, type: STD FW D2633 DTV7 (0x00000090), id: (0000000000000000), size: 149 + # + + write_le32(0x00000090); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le32(149); # Size + write_hunk_fix_endian(868800, 149); + + # + # Firmware 27, type: STD FW D2620 DTV78 (0x00000108), id: (0000000000000000), size: 149 + # + + write_le32(0x00000108); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le32(149); # Size + write_hunk_fix_endian(868960, 149); + + # + # Firmware 28, type: STD FW D2633 DTV78 (0x00000110), id: (0000000000000000), size: 149 + # + + write_le32(0x00000110); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le32(149); # Size + write_hunk_fix_endian(869112, 149); + + # + # Firmware 29, type: STD FW D2620 DTV8 (0x00000208), id: (0000000000000000), size: 149 + # + + write_le32(0x00000208); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le32(149); # Size + write_hunk_fix_endian(868648, 149); + + # + # Firmware 30, type: STD FW D2633 DTV8 (0x00000210), id: (0000000000000000), size: 149 + # + + write_le32(0x00000210); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le32(149); # Size + write_hunk_fix_endian(868800, 149); + + # + # Firmware 31, type: STD FW FM (0x00000400), id: (0000000000000000), size: 135 + # + + write_le32(0x00000400); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le32(135); # Size + write_hunk_fix_endian(869584, 135); + + # + # Firmware 32, type: STD FW (0x00000000), id: PAL/I (0000000000000010), size: 161 + # + + write_le32(0x00000000); # Type + write_le64(0x00000000, 0x00000010); # ID + write_le32(161); # Size + write_hunk_fix_endian(869728, 161); + + # + # Firmware 33, type: STD FW MTS (0x00000004), id: PAL/I (0000000000000010), size: 169 + # + + write_le32(0x00000004); # Type + write_le64(0x00000000, 0x00000010); # ID + write_le32(169); # Size + write_hunk_fix_endian(869896, 169); + + # + # Firmware 34, type: STD FW (0x00000000), id: SECAM/L AM (0000001000400000), size: 169 + # + + write_le32(0x00000000); # Type + write_le64(0x00000010, 0x00400000); # ID + write_le32(169); # Size + write_hunk_fix_endian(870072, 169); + + # + # Firmware 35, type: STD FW (0x00000000), id: SECAM/L NICAM (0000000c00400000), size: 161 + # + + write_le32(0x00000000); # Type + write_le64(0x0000000c, 0x00400000); # ID + write_le32(161); # Size + write_hunk_fix_endian(870248, 161); + + # + # Firmware 36, type: STD FW (0x00000000), id: SECAM/Lc (0000000000800000), size: 161 + # + + write_le32(0x00000000); # Type + write_le64(0x00000000, 0x00800000); # ID + write_le32(161); # Size + write_hunk_fix_endian(870416, 161); + + # + # Firmware 37, type: STD FW (0x00000000), id: NTSC/M Kr (0000000000008000), size: 161 + # + + write_le32(0x00000000); # Type + write_le64(0x00000000, 0x00008000); # ID + write_le32(161); # Size + write_hunk_fix_endian(870584, 161); + + # + # Firmware 38, type: STD FW LCD (0x00001000), id: NTSC/M Kr (0000000000008000), size: 161 + # + + write_le32(0x00001000); # Type + write_le64(0x00000000, 0x00008000); # ID + write_le32(161); # Size + write_hunk_fix_endian(870752, 161); + + # + # Firmware 39, type: STD FW LCD NOGD (0x00003000), id: NTSC/M Kr (0000000000008000), size: 161 + # + + write_le32(0x00003000); # Type + write_le64(0x00000000, 0x00008000); # ID + write_le32(161); # Size + write_hunk_fix_endian(870920, 161); + + # + # Firmware 40, type: STD FW MTS (0x00000004), id: NTSC/M Kr (0000000000008000), size: 169 + # + + write_le32(0x00000004); # Type + write_le64(0x00000000, 0x00008000); # ID + write_le32(169); # Size + write_hunk_fix_endian(871088, 169); + + # + # Firmware 41, type: STD FW (0x00000000), id: NTSC PAL/M PAL/N (000000000000b700), size: 161 + # + + write_le32(0x00000000); # Type + write_le64(0x00000000, 0x0000b700); # ID + write_le32(161); # Size + write_hunk_fix_endian(871264, 161); + + # + # Firmware 42, type: STD FW LCD (0x00001000), id: NTSC PAL/M PAL/N (000000000000b700), size: 161 + # + + write_le32(0x00001000); # Type + write_le64(0x00000000, 0x0000b700); # ID + write_le32(161); # Size + write_hunk_fix_endian(871432, 161); + + # + # Firmware 43, type: STD FW LCD NOGD (0x00003000), id: NTSC PAL/M PAL/N (000000000000b700), size: 161 + # + + write_le32(0x00003000); # Type + write_le64(0x00000000, 0x0000b700); # ID + write_le32(161); # Size + write_hunk_fix_endian(871600, 161); + + # + # Firmware 44, type: STD FW (0x00000000), id: NTSC/M Jp (0000000000002000), size: 161 + # + + write_le32(0x00000000); # Type + write_le64(0x00000000, 0x00002000); # ID + write_le32(161); # Size + write_hunk_fix_endian(871264, 161); + + # + # Firmware 45, type: STD FW MTS (0x00000004), id: NTSC PAL/M PAL/N (000000000000b700), size: 169 + # + + write_le32(0x00000004); # Type + write_le64(0x00000000, 0x0000b700); # ID + write_le32(169); # Size + write_hunk_fix_endian(871936, 169); + + # + # Firmware 46, type: STD FW MTS LCD (0x00001004), id: NTSC PAL/M PAL/N (000000000000b700), size: 169 + # + + write_le32(0x00001004); # Type + write_le64(0x00000000, 0x0000b700); # ID + write_le32(169); # Size + write_hunk_fix_endian(872112, 169); + + # + # Firmware 47, type: STD FW MTS LCD NOGD (0x00003004), id: NTSC PAL/M PAL/N (000000000000b700), size: 169 + # + + write_le32(0x00003004); # Type + write_le64(0x00000000, 0x0000b700); # ID + write_le32(169); # Size + write_hunk_fix_endian(872288, 169); + + # + # Firmware 48, type: SCODE FW HAS IF (0x60000000), IF = 3.28 MHz id: (0000000000000000), size: 192 + # + + write_le32(0x60000000); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le16(3280); # IF + write_le32(192); # Size + write_hunk(811896, 192); + + # + # Firmware 49, type: SCODE FW HAS IF (0x60000000), IF = 3.30 MHz id: (0000000000000000), size: 192 + # + + write_le32(0x60000000); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le16(3300); # IF + write_le32(192); # Size + write_hunk(813048, 192); + + # + # Firmware 50, type: SCODE FW HAS IF (0x60000000), IF = 3.44 MHz id: (0000000000000000), size: 192 + # + + write_le32(0x60000000); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le16(3440); # IF + write_le32(192); # Size + write_hunk(812280, 192); + + # + # Firmware 51, type: SCODE FW HAS IF (0x60000000), IF = 3.46 MHz id: (0000000000000000), size: 192 + # + + write_le32(0x60000000); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le16(3460); # IF + write_le32(192); # Size + write_hunk(812472, 192); + + # + # Firmware 52, type: SCODE FW DTV6 ATSC OREN36 HAS IF (0x60210020), IF = 3.80 MHz id: (0000000000000000), size: 192 + # + + write_le32(0x60210020); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le16(3800); # IF + write_le32(192); # Size + write_hunk(809784, 192); + + # + # Firmware 53, type: SCODE FW HAS IF (0x60000000), IF = 4.00 MHz id: (0000000000000000), size: 192 + # + + write_le32(0x60000000); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le16(4000); # IF + write_le32(192); # Size + write_hunk(812088, 192); + + # + # Firmware 54, type: SCODE FW DTV6 ATSC TOYOTA388 HAS IF (0x60410020), IF = 4.08 MHz id: (0000000000000000), size: 192 + # + + write_le32(0x60410020); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le16(4080); # IF + write_le32(192); # Size + write_hunk(809976, 192); + + # + # Firmware 55, type: SCODE FW HAS IF (0x60000000), IF = 4.20 MHz id: (0000000000000000), size: 192 + # + + write_le32(0x60000000); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le16(4200); # IF + write_le32(192); # Size + write_hunk(811704, 192); + + # + # Firmware 56, type: SCODE FW MONO HAS IF (0x60008000), IF = 4.32 MHz id: NTSC/M Kr (0000000000008000), size: 192 + # + + write_le32(0x60008000); # Type + write_le64(0x00000000, 0x00008000); # ID + write_le16(4320); # IF + write_le32(192); # Size + write_hunk(808056, 192); + + # + # Firmware 57, type: SCODE FW HAS IF (0x60000000), IF = 4.45 MHz id: (0000000000000000), size: 192 + # + + write_le32(0x60000000); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le16(4450); # IF + write_le32(192); # Size + write_hunk(812664, 192); + + # + # Firmware 58, type: SCODE FW MTS LCD NOGD MONO IF HAS IF (0x6002b004), IF = 4.50 MHz id: NTSC PAL/M PAL/N (000000000000b700), size: 192 + # + + write_le32(0x6002b004); # Type + write_le64(0x00000000, 0x0000b700); # ID + write_le16(4500); # IF + write_le32(192); # Size + write_hunk(807672, 192); + + # + # Firmware 59, type: SCODE FW LCD NOGD IF HAS IF (0x60023000), IF = 4.60 MHz id: NTSC/M Kr (0000000000008000), size: 192 + # + + write_le32(0x60023000); # Type + write_le64(0x00000000, 0x00008000); # ID + write_le16(4600); # IF + write_le32(192); # Size + write_hunk(807864, 192); + + # + # Firmware 60, type: SCODE FW DTV6 QAM DTV7 DTV78 DTV8 ZARLINK456 HAS IF (0x620003e0), IF = 4.76 MHz id: (0000000000000000), size: 192 + # + + write_le32(0x620003e0); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le16(4760); # IF + write_le32(192); # Size + write_hunk(807288, 192); + + # + # Firmware 61, type: SCODE FW HAS IF (0x60000000), IF = 4.94 MHz id: (0000000000000000), size: 192 + # + + write_le32(0x60000000); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le16(4940); # IF + write_le32(192); # Size + write_hunk(811512, 192); + + # + # Firmware 62, type: SCODE FW HAS IF (0x60000000), IF = 5.26 MHz id: (0000000000000000), size: 192 + # + + write_le32(0x60000000); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le16(5260); # IF + write_le32(192); # Size + write_hunk(810552, 192); + + # + # Firmware 63, type: SCODE FW MONO HAS IF (0x60008000), IF = 5.32 MHz id: PAL/BG A2 NICAM (0000000f00000007), size: 192 + # + + write_le32(0x60008000); # Type + write_le64(0x0000000f, 0x00000007); # ID + write_le16(5320); # IF + write_le32(192); # Size + write_hunk(810744, 192); + + # + # Firmware 64, type: SCODE FW DTV7 DTV78 DTV8 DIBCOM52 CHINA HAS IF (0x65000380), IF = 5.40 MHz id: (0000000000000000), size: 192 + # + + write_le32(0x65000380); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le16(5400); # IF + write_le32(192); # Size + write_hunk(807096, 192); + + # + # Firmware 65, type: SCODE FW DTV6 ATSC OREN538 HAS IF (0x60110020), IF = 5.58 MHz id: (0000000000000000), size: 192 + # + + write_le32(0x60110020); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le16(5580); # IF + write_le32(192); # Size + write_hunk(809592, 192); + + # + # Firmware 66, type: SCODE FW HAS IF (0x60000000), IF = 5.64 MHz id: PAL/BG A2 (0000000300000007), size: 192 + # + + write_le32(0x60000000); # Type + write_le64(0x00000003, 0x00000007); # ID + write_le16(5640); # IF + write_le32(192); # Size + write_hunk(808440, 192); + + # + # Firmware 67, type: SCODE FW HAS IF (0x60000000), IF = 5.74 MHz id: PAL/BG NICAM (0000000c00000007), size: 192 + # + + write_le32(0x60000000); # Type + write_le64(0x0000000c, 0x00000007); # ID + write_le16(5740); # IF + write_le32(192); # Size + write_hunk(808632, 192); + + # + # Firmware 68, type: SCODE FW HAS IF (0x60000000), IF = 5.90 MHz id: (0000000000000000), size: 192 + # + + write_le32(0x60000000); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le16(5900); # IF + write_le32(192); # Size + write_hunk(810360, 192); + + # + # Firmware 69, type: SCODE FW MONO HAS IF (0x60008000), IF = 6.00 MHz id: PAL/DK PAL/I SECAM/K3 SECAM/L SECAM/Lc NICAM (0000000c04c000f0), size: 192 + # + + write_le32(0x60008000); # Type + write_le64(0x0000000c, 0x04c000f0); # ID + write_le16(6000); # IF + write_le32(192); # Size + write_hunk(808824, 192); + + # + # Firmware 70, type: SCODE FW DTV6 QAM ATSC LG60 F6MHZ HAS IF (0x68050060), IF = 6.20 MHz id: (0000000000000000), size: 192 + # + + write_le32(0x68050060); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le16(6200); # IF + write_le32(192); # Size + write_hunk(809400, 192); + + # + # Firmware 71, type: SCODE FW HAS IF (0x60000000), IF = 6.24 MHz id: PAL/I (0000000000000010), size: 192 + # + + write_le32(0x60000000); # Type + write_le64(0x00000000, 0x00000010); # ID + write_le16(6240); # IF + write_le32(192); # Size + write_hunk(808248, 192); + + # + # Firmware 72, type: SCODE FW MONO HAS IF (0x60008000), IF = 6.32 MHz id: SECAM/K1 (0000000000200000), size: 192 + # + + write_le32(0x60008000); # Type + write_le64(0x00000000, 0x00200000); # ID + write_le16(6320); # IF + write_le32(192); # Size + write_hunk(811320, 192); + + # + # Firmware 73, type: SCODE FW HAS IF (0x60000000), IF = 6.34 MHz id: SECAM/K1 (0000000000200000), size: 192 + # + + write_le32(0x60000000); # Type + write_le64(0x00000000, 0x00200000); # ID + write_le16(6340); # IF + write_le32(192); # Size + write_hunk(809208, 192); + + # + # Firmware 74, type: SCODE FW MONO HAS IF (0x60008000), IF = 6.50 MHz id: PAL/DK SECAM/K3 SECAM/L NICAM (0000000c044000e0), size: 192 + # + + write_le32(0x60008000); # Type + write_le64(0x0000000c, 0x044000e0); # ID + write_le16(6500); # IF + write_le32(192); # Size + write_hunk(811128, 192); + + # + # Firmware 75, type: SCODE FW DTV6 ATSC ATI638 HAS IF (0x60090020), IF = 6.58 MHz id: (0000000000000000), size: 192 + # + + write_le32(0x60090020); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le16(6580); # IF + write_le32(192); # Size + write_hunk(807480, 192); + + # + # Firmware 76, type: SCODE FW HAS IF (0x60000000), IF = 6.60 MHz id: PAL/DK A2 (00000003000000e0), size: 192 + # + + write_le32(0x60000000); # Type + write_le64(0x00000003, 0x000000e0); # ID + write_le16(6600); # IF + write_le32(192); # Size + write_hunk(809016, 192); + + # + # Firmware 77, type: SCODE FW MONO HAS IF (0x60008000), IF = 6.68 MHz id: PAL/DK A2 (00000003000000e0), size: 192 + # + + write_le32(0x60008000); # Type + write_le64(0x00000003, 0x000000e0); # ID + write_le16(6680); # IF + write_le32(192); # Size + write_hunk(810936, 192); + + # + # Firmware 78, type: SCODE FW DTV6 ATSC TOYOTA794 HAS IF (0x60810020), IF = 8.14 MHz id: (0000000000000000), size: 192 + # + + write_le32(0x60810020); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le16(8140); # IF + write_le32(192); # Size + write_hunk(810168, 192); + + # + # Firmware 79, type: SCODE FW HAS IF (0x60000000), IF = 8.20 MHz id: (0000000000000000), size: 192 + # + + write_le32(0x60000000); # Type + write_le64(0x00000000, 0x00000000); # ID + write_le16(8200); # IF + write_le32(192); # Size + write_hunk(812856, 192); +} + + +sub extract_firmware { + my $sourcefile_24 = "UDXTTM6000.sys"; + my $hash_24 = "cb9deb5508a5e150af2880f5b0066d78"; + my $outfile_24 = "xc3028-v24.fw"; + my $name_24 = "xc2028 firmware"; + my $version_24 = 516; + my $nr_desc_24 = 77; + my $out; + + my $sourcefile_27 = "hcw85bda.sys"; + my $hash_27 = "0e44dbf63bb0169d57446aec21881ff2"; + my $outfile_27 = "xc3028-v27.fw"; + my $name_27 = "xc2028 firmware"; + my $version_27 = 519; + my $nr_desc_27 = 80; + my $out; + + if (-e $sourcefile_24) { + verify($sourcefile_24, $hash_24); + + open INFILE, "<$sourcefile_24"; + main_firmware_24($outfile_24, $name_24, $version_24, $nr_desc_24); + close INFILE; + } + + if (-e $sourcefile_27) { + verify($sourcefile_27, $hash_27); + + open INFILE, "<$sourcefile_27"; + main_firmware_27($outfile_27, $name_27, $version_27, $nr_desc_27); + close INFILE; + } +} + +extract_firmware; +printf "Firmwares generated.\n"; diff --git a/src/net/scripts/faddr2line b/src/net/scripts/faddr2line new file mode 100755 index 0000000..94ed98d --- /dev/null +++ b/src/net/scripts/faddr2line @@ -0,0 +1,289 @@ +#!/bin/bash +# SPDX-License-Identifier: GPL-2.0 +# +# Translate stack dump function offsets. +# +# addr2line doesn't work with KASLR addresses. This works similarly to +# addr2line, but instead takes the 'func+0x123' format as input: +# +# $ ./scripts/faddr2line ~/k/vmlinux meminfo_proc_show+0x5/0x568 +# meminfo_proc_show+0x5/0x568: +# meminfo_proc_show at fs/proc/meminfo.c:27 +# +# If the address is part of an inlined function, the full inline call chain is +# printed: +# +# $ ./scripts/faddr2line ~/k/vmlinux native_write_msr+0x6/0x27 +# native_write_msr+0x6/0x27: +# arch_static_branch at arch/x86/include/asm/msr.h:121 +# (inlined by) static_key_false at include/linux/jump_label.h:125 +# (inlined by) native_write_msr at arch/x86/include/asm/msr.h:125 +# +# The function size after the '/' in the input is optional, but recommended. +# It's used to help disambiguate any duplicate symbol names, which can occur +# rarely. If the size is omitted for a duplicate symbol then it's possible for +# multiple code sites to be printed: +# +# $ ./scripts/faddr2line ~/k/vmlinux raw_ioctl+0x5 +# raw_ioctl+0x5/0x20: +# raw_ioctl at drivers/char/raw.c:122 +# +# raw_ioctl+0x5/0xb1: +# raw_ioctl at net/ipv4/raw.c:876 +# +# Multiple addresses can be specified on a single command line: +# +# $ ./scripts/faddr2line ~/k/vmlinux type_show+0x10/45 free_reserved_area+0x90 +# type_show+0x10/0x2d: +# type_show at drivers/video/backlight/backlight.c:213 +# +# free_reserved_area+0x90/0x123: +# free_reserved_area at mm/page_alloc.c:6429 (discriminator 2) + + +set -o errexit +set -o nounset + +usage() { + echo "usage: faddr2line [--list] <object file> <func+offset> <func+offset>..." >&2 + exit 1 +} + +warn() { + echo "$1" >&2 +} + +die() { + echo "ERROR: $1" >&2 + exit 1 +} + +READELF="${CROSS_COMPILE:-}readelf" +ADDR2LINE="${CROSS_COMPILE:-}addr2line" +AWK="awk" + +command -v ${AWK} >/dev/null 2>&1 || die "${AWK} isn't installed" +command -v ${READELF} >/dev/null 2>&1 || die "${READELF} isn't installed" +command -v ${ADDR2LINE} >/dev/null 2>&1 || die "${ADDR2LINE} isn't installed" + +# Try to figure out the source directory prefix so we can remove it from the +# addr2line output. HACK ALERT: This assumes that start_kernel() is in +# init/main.c! This only works for vmlinux. Otherwise it falls back to +# printing the absolute path. +find_dir_prefix() { + local objfile=$1 + + local start_kernel_addr=$(${READELF} --symbols --wide $objfile | ${AWK} '$8 == "start_kernel" {printf "0x%s", $2}') + [[ -z $start_kernel_addr ]] && return + + local file_line=$(${ADDR2LINE} -e $objfile $start_kernel_addr) + [[ -z $file_line ]] && return + + local prefix=${file_line%init/main.c:*} + if [[ -z $prefix ]] || [[ $prefix = $file_line ]]; then + return + fi + + DIR_PREFIX=$prefix + return 0 +} + +__faddr2line() { + local objfile=$1 + local func_addr=$2 + local dir_prefix=$3 + local print_warnings=$4 + + local sym_name=${func_addr%+*} + local func_offset=${func_addr#*+} + func_offset=${func_offset%/*} + local user_size= + local file_type + local is_vmlinux=0 + [[ $func_addr =~ "/" ]] && user_size=${func_addr#*/} + + if [[ -z $sym_name ]] || [[ -z $func_offset ]] || [[ $sym_name = $func_addr ]]; then + warn "bad func+offset $func_addr" + DONE=1 + return + fi + + # vmlinux uses absolute addresses in the section table rather than + # section offsets. + local file_type=$(${READELF} --file-header $objfile | + ${AWK} '$1 == "Type:" { print $2; exit }') + [[ $file_type = "EXEC" ]] && is_vmlinux=1 + + # Go through each of the object's symbols which match the func name. + # In rare cases there might be duplicates, in which case we print all + # matches. + while read line; do + local fields=($line) + local sym_addr=0x${fields[1]} + local sym_elf_size=${fields[2]} + local sym_sec=${fields[6]} + local sec_size + local sec_name + + # Get the section size: + sec_size=$(${READELF} --section-headers --wide $objfile | + sed 's/\[ /\[/' | + ${AWK} -v sec=$sym_sec '$1 == "[" sec "]" { print "0x" $6; exit }') + + if [[ -z $sec_size ]]; then + warn "bad section size: section: $sym_sec" + DONE=1 + return + fi + + # Get the section name: + sec_name=$(${READELF} --section-headers --wide $objfile | + sed 's/\[ /\[/' | + ${AWK} -v sec=$sym_sec '$1 == "[" sec "]" { print $2; exit }') + + if [[ -z $sec_name ]]; then + warn "bad section name: section: $sym_sec" + DONE=1 + return + fi + + # Calculate the symbol size. + # + # Unfortunately we can't use the ELF size, because kallsyms + # also includes the padding bytes in its size calculation. For + # kallsyms, the size calculation is the distance between the + # symbol and the next symbol in a sorted list. + local sym_size + local cur_sym_addr + local found=0 + while read line; do + local fields=($line) + cur_sym_addr=0x${fields[1]} + local cur_sym_elf_size=${fields[2]} + local cur_sym_name=${fields[7]:-} + + if [[ $cur_sym_addr = $sym_addr ]] && + [[ $cur_sym_elf_size = $sym_elf_size ]] && + [[ $cur_sym_name = $sym_name ]]; then + found=1 + continue + fi + + if [[ $found = 1 ]]; then + sym_size=$(($cur_sym_addr - $sym_addr)) + [[ $sym_size -lt $sym_elf_size ]] && continue; + found=2 + break + fi + done < <(${READELF} --symbols --wide $objfile | ${AWK} -v sec=$sym_sec '$7 == sec' | sort --key=2) + + if [[ $found = 0 ]]; then + warn "can't find symbol: sym_name: $sym_name sym_sec: $sym_sec sym_addr: $sym_addr sym_elf_size: $sym_elf_size" + DONE=1 + return + fi + + # If nothing was found after the symbol, assume it's the last + # symbol in the section. + [[ $found = 1 ]] && sym_size=$(($sec_size - $sym_addr)) + + if [[ -z $sym_size ]] || [[ $sym_size -le 0 ]]; then + warn "bad symbol size: sym_addr: $sym_addr cur_sym_addr: $cur_sym_addr" + DONE=1 + return + fi + + sym_size=0x$(printf %x $sym_size) + + # Calculate the address from user-supplied offset: + local addr=$(($sym_addr + $func_offset)) + if [[ -z $addr ]] || [[ $addr = 0 ]]; then + warn "bad address: $sym_addr + $func_offset" + DONE=1 + return + fi + addr=0x$(printf %x $addr) + + # If the user provided a size, make sure it matches the symbol's size: + if [[ -n $user_size ]] && [[ $user_size -ne $sym_size ]]; then + [[ $print_warnings = 1 ]] && + echo "skipping $sym_name address at $addr due to size mismatch ($user_size != $sym_size)" + continue; + fi + + # Make sure the provided offset is within the symbol's range: + if [[ $func_offset -gt $sym_size ]]; then + [[ $print_warnings = 1 ]] && + echo "skipping $sym_name address at $addr due to size mismatch ($func_offset > $sym_size)" + continue + fi + + # In case of duplicates or multiple addresses specified on the + # cmdline, separate multiple entries with a blank line: + [[ $FIRST = 0 ]] && echo + FIRST=0 + + echo "$sym_name+$func_offset/$sym_size:" + + # Pass section address to addr2line and strip absolute paths + # from the output: + local args="--functions --pretty-print --inlines --exe=$objfile" + [[ $is_vmlinux = 0 ]] && args="$args --section=$sec_name" + local output=$(${ADDR2LINE} $args $addr | sed "s; $dir_prefix\(\./\)*; ;") + [[ -z $output ]] && continue + + # Default output (non --list): + if [[ $LIST = 0 ]]; then + echo "$output" | while read -r line + do + echo $line + done + DONE=1; + continue + fi + + # For --list, show each line with its corresponding source code: + echo "$output" | while read -r line + do + echo + echo $line + n=$(echo $line | sed 's/.*:\([0-9]\+\).*/\1/g') + n1=$[$n-5] + n2=$[$n+5] + f=$(echo $line | sed 's/.*at \(.\+\):.*/\1/g') + ${AWK} 'NR>=strtonum("'$n1'") && NR<=strtonum("'$n2'") { if (NR=='$n') printf(">%d<", NR); else printf(" %d ", NR); printf("\t%s\n", $0)}' $f + done + + DONE=1 + + done < <(${READELF} --symbols --wide $objfile | ${AWK} -v fn=$sym_name '$4 == "FUNC" && $8 == fn') +} + +[[ $# -lt 2 ]] && usage + +objfile=$1 + +LIST=0 +[[ "$objfile" == "--list" ]] && LIST=1 && shift && objfile=$1 + +[[ ! -f $objfile ]] && die "can't find objfile $objfile" +shift + +DIR_PREFIX=supercalifragilisticexpialidocious +find_dir_prefix $objfile + +FIRST=1 +while [[ $# -gt 0 ]]; do + func_addr=$1 + shift + + # print any matches found + DONE=0 + __faddr2line $objfile $func_addr $DIR_PREFIX 0 + + # if no match was found, print warnings + if [[ $DONE = 0 ]]; then + __faddr2line $objfile $func_addr $DIR_PREFIX 1 + warn "no match for $func_addr" + fi +done diff --git a/src/net/scripts/file-size.sh b/src/net/scripts/file-size.sh new file mode 100755 index 0000000..7eb7423 --- /dev/null +++ b/src/net/scripts/file-size.sh @@ -0,0 +1,4 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0 +set -- $(ls -dn "$1") +printf '%s\n' "$5" diff --git a/src/net/scripts/find-unused-docs.sh b/src/net/scripts/find-unused-docs.sh new file mode 100755 index 0000000..ee6a50e --- /dev/null +++ b/src/net/scripts/find-unused-docs.sh @@ -0,0 +1,62 @@ +#!/bin/bash +# (c) 2017, Jonathan Corbet <corbet@lwn.net> +# sayli karnik <karniksayli1995@gmail.com> +# +# This script detects files with kernel-doc comments for exported functions +# that are not included in documentation. +# +# usage: Run 'scripts/find-unused-docs.sh directory' from top level of kernel +# tree. +# +# example: $scripts/find-unused-docs.sh drivers/scsi +# +# Licensed under the terms of the GNU GPL License + +if ! [ -d "Documentation" ]; then + echo "Run from top level of kernel tree" + exit 1 +fi + +if [ "$#" -ne 1 ]; then + echo "Usage: scripts/find-unused-docs.sh directory" + exit 1 +fi + +if ! [ -d "$1" ]; then + echo "Directory $1 doesn't exist" + exit 1 +fi + +cd "$( dirname "${BASH_SOURCE[0]}" )" +cd .. + +cd Documentation/ + +echo "The following files contain kerneldoc comments for exported functions \ +that are not used in the formatted documentation" + +# FILES INCLUDED + +files_included=($(grep -rHR ".. kernel-doc" --include \*.rst | cut -d " " -f 3)) + +declare -A FILES_INCLUDED + +for each in "${files_included[@]}"; do + FILES_INCLUDED[$each]="$each" + done + +cd .. + +# FILES NOT INCLUDED + +for file in `find $1 -name '*.c'`; do + + if [[ ${FILES_INCLUDED[$file]+_} ]]; then + continue; + fi + str=$(scripts/kernel-doc -export "$file" 2>/dev/null) + if [[ -n "$str" ]]; then + echo "$file" + fi + done + diff --git a/src/net/scripts/gcc-goto.sh b/src/net/scripts/gcc-goto.sh new file mode 100755 index 0000000..8b980fb --- /dev/null +++ b/src/net/scripts/gcc-goto.sh @@ -0,0 +1,22 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0 +# Test for gcc 'asm goto' support +# Copyright (C) 2010, Jason Baron <jbaron@redhat.com> + +cat << "END" | $@ -x c - -fno-PIE -c -o /dev/null +int main(void) +{ +#if defined(__arm__) || defined(__aarch64__) + /* + * Not related to asm goto, but used by jump label + * and broken on some ARM GCC versions (see GCC Bug 48637). + */ + static struct { int dummy; int state; } tp; + asm (".long %c0" :: "i" (&tp.state)); +#endif + +entry: + asm goto ("" :::: entry); + return 0; +} +END diff --git a/src/net/scripts/gcc-ld b/src/net/scripts/gcc-ld new file mode 100755 index 0000000..997b818 --- /dev/null +++ b/src/net/scripts/gcc-ld @@ -0,0 +1,30 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0 +# run gcc with ld options +# used as a wrapper to execute link time optimizations +# yes virginia, this is not pretty + +ARGS="-nostdlib" + +while [ "$1" != "" ] ; do + case "$1" in + -save-temps|-m32|-m64) N="$1" ;; + -r) N="$1" ;; + -[Wg]*) N="$1" ;; + -[olv]|-[Ofd]*|-nostdlib) N="$1" ;; + --end-group|--start-group) + N="-Wl,$1" ;; + -[RTFGhIezcbyYu]*|\ +--script|--defsym|-init|-Map|--oformat|-rpath|\ +-rpath-link|--sort-section|--section-start|-Tbss|-Tdata|-Ttext|\ +--version-script|--dynamic-list|--version-exports-symbol|--wrap|-m) + A="$1" ; shift ; N="-Wl,$A,$1" ;; + -[m]*) N="$1" ;; + -*) N="-Wl,$1" ;; + *) N="$1" ;; + esac + ARGS="$ARGS $N" + shift +done + +exec $CC $ARGS diff --git a/src/net/scripts/gcc-plugins/.gitignore b/src/net/scripts/gcc-plugins/.gitignore new file mode 100644 index 0000000..b04e0f0 --- /dev/null +++ b/src/net/scripts/gcc-plugins/.gitignore @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +randomize_layout_seed.h diff --git a/src/net/scripts/gcc-plugins/Kconfig b/src/net/scripts/gcc-plugins/Kconfig new file mode 100644 index 0000000..ab9eb4c --- /dev/null +++ b/src/net/scripts/gcc-plugins/Kconfig @@ -0,0 +1,107 @@ +# SPDX-License-Identifier: GPL-2.0-only +config HAVE_GCC_PLUGINS + bool + help + An arch should select this symbol if it supports building with + GCC plugins. + +menuconfig GCC_PLUGINS + bool "GCC plugins" + depends on HAVE_GCC_PLUGINS + depends on CC_IS_GCC + depends on $(success,test -e $(shell,$(CC) -print-file-name=plugin)/include/plugin-version.h) + default y + help + GCC plugins are loadable modules that provide extra features to the + compiler. They are useful for runtime instrumentation and static analysis. + + See Documentation/kbuild/gcc-plugins.rst for details. + +if GCC_PLUGINS + +config GCC_PLUGIN_CYC_COMPLEXITY + bool "Compute the cyclomatic complexity of a function" if EXPERT + depends on !COMPILE_TEST # too noisy + help + The complexity M of a function's control flow graph is defined as: + M = E - N + 2P + where + + E = the number of edges + N = the number of nodes + P = the number of connected components (exit nodes). + + Enabling this plugin reports the complexity to stderr during the + build. It mainly serves as a simple example of how to create a + gcc plugin for the kernel. + +config GCC_PLUGIN_SANCOV + bool + help + This plugin inserts a __sanitizer_cov_trace_pc() call at the start of + basic blocks. It supports all gcc versions with plugin support (from + gcc-4.5 on). It is based on the commit "Add fuzzing coverage support" + by Dmitry Vyukov <dvyukov@google.com>. + +config GCC_PLUGIN_LATENT_ENTROPY + bool "Generate some entropy during boot and runtime" + help + By saying Y here the kernel will instrument some kernel code to + extract some entropy from both original and artificially created + program state. This will help especially embedded systems where + there is little 'natural' source of entropy normally. The cost + is some slowdown of the boot process (about 0.5%) and fork and + irq processing. + + Note that entropy extracted this way is not cryptographically + secure! + + This plugin was ported from grsecurity/PaX. More information at: + * https://grsecurity.net/ + * https://pax.grsecurity.net/ + +config GCC_PLUGIN_RANDSTRUCT + bool "Randomize layout of sensitive kernel structures" + select MODVERSIONS if MODULES + help + If you say Y here, the layouts of structures that are entirely + function pointers (and have not been manually annotated with + __no_randomize_layout), or structures that have been explicitly + marked with __randomize_layout, will be randomized at compile-time. + This can introduce the requirement of an additional information + exposure vulnerability for exploits targeting these structure + types. + + Enabling this feature will introduce some performance impact, + slightly increase memory usage, and prevent the use of forensic + tools like Volatility against the system (unless the kernel + source tree isn't cleaned after kernel installation). + + The seed used for compilation is located at + scripts/gcc-plugins/randomize_layout_seed.h. It remains after + a make clean to allow for external modules to be compiled with + the existing seed and will be removed by a make mrproper or + make distclean. + + Note that the implementation requires gcc 4.7 or newer. + + This plugin was ported from grsecurity/PaX. More information at: + * https://grsecurity.net/ + * https://pax.grsecurity.net/ + +config GCC_PLUGIN_RANDSTRUCT_PERFORMANCE + bool "Use cacheline-aware structure randomization" + depends on GCC_PLUGIN_RANDSTRUCT + depends on !COMPILE_TEST # do not reduce test coverage + help + If you say Y here, the RANDSTRUCT randomization will make a + best effort at restricting randomization to cacheline-sized + groups of elements. It will further not randomize bitfields + in structures. This reduces the performance hit of RANDSTRUCT + at the cost of weakened randomization. + +config GCC_PLUGIN_ARM_SSP_PER_TASK + bool + depends on GCC_PLUGINS && ARM + +endif diff --git a/src/net/scripts/gcc-plugins/Makefile b/src/net/scripts/gcc-plugins/Makefile new file mode 100644 index 0000000..b5487cc --- /dev/null +++ b/src/net/scripts/gcc-plugins/Makefile @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: GPL-2.0 + +$(obj)/randomize_layout_plugin.so: $(objtree)/$(obj)/randomize_layout_seed.h +quiet_cmd_create_randomize_layout_seed = GENSEED $@ +cmd_create_randomize_layout_seed = \ + $(CONFIG_SHELL) $(srctree)/$(src)/gen-random-seed.sh $@ $(objtree)/include/generated/randomize_layout_hash.h +$(objtree)/$(obj)/randomize_layout_seed.h: FORCE + $(call if_changed,create_randomize_layout_seed) +targets += randomize_layout_seed.h randomize_layout_hash.h + +# Build rules for plugins +# +# No extra code is needed for single-file plugins. +# For multi-file plugins, use *-objs syntax to list the objects. +# +# If the plugin foo.so is compiled from foo.c and foo2.c, you can do: +# +# foo-objs := foo.o foo2.o + +always-y += $(GCC_PLUGIN) + +GCC_PLUGINS_DIR = $(shell $(CC) -print-file-name=plugin) + +plugin_cxxflags = -Wp,-MMD,$(depfile) $(KBUILD_HOSTCXXFLAGS) -fPIC \ + -I $(GCC_PLUGINS_DIR)/include -I $(obj) -std=gnu++11 \ + -fno-rtti -fno-exceptions -fasynchronous-unwind-tables \ + -ggdb -Wno-narrowing -Wno-unused-variable \ + -Wno-format-diag + +plugin_ldflags = -shared + +plugin-single := $(foreach m, $(GCC_PLUGIN), $(if $($(m:%.so=%-objs)),,$(m))) +plugin-multi := $(filter-out $(plugin-single), $(GCC_PLUGIN)) +plugin-objs := $(sort $(foreach m, $(plugin-multi), $($(m:%.so=%-objs)))) + +targets += $(plugin-single) $(plugin-multi) $(plugin-objs) +clean-files += *.so + +plugin-single := $(addprefix $(obj)/, $(plugin-single)) +plugin-multi := $(addprefix $(obj)/, $(plugin-multi)) +plugin-objs := $(addprefix $(obj)/, $(plugin-objs)) + +quiet_cmd_plugin_cxx_so_c = HOSTCXX $@ + cmd_plugin_cxx_so_c = $(HOSTCXX) $(plugin_cxxflags) $(plugin_ldflags) -o $@ $< + +$(plugin-single): $(obj)/%.so: $(src)/%.c FORCE + $(call if_changed_dep,plugin_cxx_so_c) + +quiet_cmd_plugin_ld_so_o = HOSTLD $@ + cmd_plugin_ld_so_o = $(HOSTCXX) $(plugin_ldflags) -o $@ \ + $(addprefix $(obj)/, $($(target-stem)-objs)) + +$(plugin-multi): FORCE + $(call if_changed,plugin_ld_so_o) +$(foreach m, $(notdir $(plugin-multi)), $(eval $(obj)/$m: $(addprefix $(obj)/, $($(m:%.so=%-objs))))) + +quiet_cmd_plugin_cxx_o_c = HOSTCXX $@ + cmd_plugin_cxx_o_c = $(HOSTCXX) $(plugin_cxxflags) -c -o $@ $< + +$(plugin-objs): $(obj)/%.o: $(src)/%.c FORCE + $(call if_changed_dep,plugin_cxx_o_c) diff --git a/src/net/scripts/gcc-plugins/arm_ssp_per_task_plugin.c b/src/net/scripts/gcc-plugins/arm_ssp_per_task_plugin.c new file mode 100644 index 0000000..8c1af9b --- /dev/null +++ b/src/net/scripts/gcc-plugins/arm_ssp_per_task_plugin.c @@ -0,0 +1,122 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include "gcc-common.h" + +__visible int plugin_is_GPL_compatible; + +static unsigned int sp_mask, canary_offset; + +static unsigned int arm_pertask_ssp_rtl_execute(void) +{ + rtx_insn *insn; + + for (insn = get_insns(); insn; insn = NEXT_INSN(insn)) { + const char *sym; + rtx body; + rtx mask, masked_sp; + + /* + * Find a SET insn involving a SYMBOL_REF to __stack_chk_guard + */ + if (!INSN_P(insn)) + continue; + body = PATTERN(insn); + if (GET_CODE(body) != SET || + GET_CODE(SET_SRC(body)) != SYMBOL_REF) + continue; + sym = XSTR(SET_SRC(body), 0); + if (strcmp(sym, "__stack_chk_guard")) + continue; + + /* + * Replace the source of the SET insn with an expression that + * produces the address of the copy of the stack canary value + * stored in struct thread_info + */ + mask = GEN_INT(sext_hwi(sp_mask, GET_MODE_PRECISION(Pmode))); + masked_sp = gen_reg_rtx(Pmode); + + emit_insn_before(gen_rtx_set(masked_sp, + gen_rtx_AND(Pmode, + stack_pointer_rtx, + mask)), + insn); + + SET_SRC(body) = gen_rtx_PLUS(Pmode, masked_sp, + GEN_INT(canary_offset)); + } + return 0; +} + +#define PASS_NAME arm_pertask_ssp_rtl + +#define NO_GATE +#include "gcc-generate-rtl-pass.h" + +#if BUILDING_GCC_VERSION >= 9000 +static bool no(void) +{ + return false; +} + +static void arm_pertask_ssp_start_unit(void *gcc_data, void *user_data) +{ + targetm.have_stack_protect_combined_set = no; + targetm.have_stack_protect_combined_test = no; +} +#endif + +__visible int plugin_init(struct plugin_name_args *plugin_info, + struct plugin_gcc_version *version) +{ + const char * const plugin_name = plugin_info->base_name; + const int argc = plugin_info->argc; + const struct plugin_argument *argv = plugin_info->argv; + int tso = 0; + int i; + + if (!plugin_default_version_check(version, &gcc_version)) { + error(G_("incompatible gcc/plugin versions")); + return 1; + } + + for (i = 0; i < argc; ++i) { + if (!strcmp(argv[i].key, "disable")) + return 0; + + /* all remaining options require a value */ + if (!argv[i].value) { + error(G_("no value supplied for option '-fplugin-arg-%s-%s'"), + plugin_name, argv[i].key); + return 1; + } + + if (!strcmp(argv[i].key, "tso")) { + tso = atoi(argv[i].value); + continue; + } + + if (!strcmp(argv[i].key, "offset")) { + canary_offset = atoi(argv[i].value); + continue; + } + error(G_("unknown option '-fplugin-arg-%s-%s'"), + plugin_name, argv[i].key); + return 1; + } + + /* create the mask that produces the base of the stack */ + sp_mask = ~((1U << (12 + tso)) - 1); + + PASS_INFO(arm_pertask_ssp_rtl, "expand", 1, PASS_POS_INSERT_AFTER); + + register_callback(plugin_info->base_name, PLUGIN_PASS_MANAGER_SETUP, + NULL, &arm_pertask_ssp_rtl_pass_info); + +#if BUILDING_GCC_VERSION >= 9000 + register_callback(plugin_info->base_name, PLUGIN_START_UNIT, + arm_pertask_ssp_start_unit, NULL); +#endif + + return 0; +} diff --git a/src/net/scripts/gcc-plugins/cyc_complexity_plugin.c b/src/net/scripts/gcc-plugins/cyc_complexity_plugin.c new file mode 100644 index 0000000..73124c2 --- /dev/null +++ b/src/net/scripts/gcc-plugins/cyc_complexity_plugin.c @@ -0,0 +1,69 @@ +/* + * Copyright 2011-2016 by Emese Revfy <re.emese@gmail.com> + * Licensed under the GPL v2, or (at your option) v3 + * + * Homepage: + * https://github.com/ephox-gcc-plugins/cyclomatic_complexity + * + * https://en.wikipedia.org/wiki/Cyclomatic_complexity + * The complexity M is then defined as: + * M = E - N + 2P + * where + * + * E = the number of edges of the graph + * N = the number of nodes of the graph + * P = the number of connected components (exit nodes). + * + * Usage (4.5 - 5): + * $ make clean; make run + */ + +#include "gcc-common.h" + +__visible int plugin_is_GPL_compatible; + +static struct plugin_info cyc_complexity_plugin_info = { + .version = "20160225", + .help = "Cyclomatic Complexity\n", +}; + +static unsigned int cyc_complexity_execute(void) +{ + int complexity; + expanded_location xloc; + + /* M = E - N + 2P */ + complexity = n_edges_for_fn(cfun) - n_basic_blocks_for_fn(cfun) + 2; + + xloc = expand_location(DECL_SOURCE_LOCATION(current_function_decl)); + fprintf(stderr, "Cyclomatic Complexity %d %s:%s\n", complexity, + xloc.file, DECL_NAME_POINTER(current_function_decl)); + + return 0; +} + +#define PASS_NAME cyc_complexity + +#define NO_GATE +#define TODO_FLAGS_FINISH TODO_dump_func + +#include "gcc-generate-gimple-pass.h" + +__visible int plugin_init(struct plugin_name_args *plugin_info, struct plugin_gcc_version *version) +{ + const char * const plugin_name = plugin_info->base_name; + + PASS_INFO(cyc_complexity, "ssa", 1, PASS_POS_INSERT_AFTER); + + if (!plugin_default_version_check(version, &gcc_version)) { + error(G_("incompatible gcc/plugin versions")); + return 1; + } + + register_callback(plugin_name, PLUGIN_INFO, NULL, + &cyc_complexity_plugin_info); + register_callback(plugin_name, PLUGIN_PASS_MANAGER_SETUP, NULL, + &cyc_complexity_pass_info); + + return 0; +} diff --git a/src/net/scripts/gcc-plugins/gcc-common.h b/src/net/scripts/gcc-plugins/gcc-common.h new file mode 100644 index 0000000..9ad76b7 --- /dev/null +++ b/src/net/scripts/gcc-plugins/gcc-common.h @@ -0,0 +1,980 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef GCC_COMMON_H_INCLUDED +#define GCC_COMMON_H_INCLUDED + +#include "bversion.h" +#if BUILDING_GCC_VERSION >= 6000 +#include "gcc-plugin.h" +#else +#include "plugin.h" +#endif +#include "plugin-version.h" +#include "config.h" +#include "system.h" +#include "coretypes.h" +#include "tm.h" +#include "line-map.h" +#include "input.h" +#include "tree.h" + +#include "tree-inline.h" +#include "version.h" +#include "rtl.h" +#include "tm_p.h" +#include "flags.h" +#include "hard-reg-set.h" +#include "output.h" +#include "except.h" +#include "function.h" +#include "toplev.h" +#if BUILDING_GCC_VERSION >= 5000 +#include "expr.h" +#endif +#include "basic-block.h" +#include "intl.h" +#include "ggc.h" +#include "timevar.h" + +#if BUILDING_GCC_VERSION < 10000 +#include "params.h" +#endif + +#if BUILDING_GCC_VERSION <= 4009 +#include "pointer-set.h" +#else +#include "hash-map.h" +#endif + +#if BUILDING_GCC_VERSION >= 7000 +#include "memmodel.h" +#endif +#include "emit-rtl.h" +#include "debug.h" +#include "target.h" +#include "langhooks.h" +#include "cfgloop.h" +#include "cgraph.h" +#include "opts.h" + +#if BUILDING_GCC_VERSION == 4005 +#include <sys/mman.h> +#endif + +#if BUILDING_GCC_VERSION >= 4007 +#include "tree-pretty-print.h" +#include "gimple-pretty-print.h" +#endif + +#if BUILDING_GCC_VERSION >= 4006 +/* + * The c-family headers were moved into a subdirectory in GCC version + * 4.7, but most plugin-building users of GCC 4.6 are using the Debian + * or Ubuntu package, which has an out-of-tree patch to move this to the + * same location as found in 4.7 and later: + * https://sources.debian.net/src/gcc-4.6/4.6.3-14/debian/patches/pr45078.diff/ + */ +#include "c-family/c-common.h" +#else +#include "c-common.h" +#endif + +#if BUILDING_GCC_VERSION <= 4008 +#include "tree-flow.h" +#else +#include "tree-cfgcleanup.h" +#include "tree-ssa-operands.h" +#include "tree-into-ssa.h" +#endif + +#if BUILDING_GCC_VERSION >= 4008 +#include "is-a.h" +#endif + +#include "diagnostic.h" +#include "tree-dump.h" +#include "tree-pass.h" +#if BUILDING_GCC_VERSION >= 4009 +#include "pass_manager.h" +#endif +#include "predict.h" +#include "ipa-utils.h" + +#if BUILDING_GCC_VERSION >= 8000 +#include "stringpool.h" +#endif + +#if BUILDING_GCC_VERSION >= 4009 +#include "attribs.h" +#include "varasm.h" +#include "stor-layout.h" +#include "internal-fn.h" +#include "gimple-expr.h" +#include "gimple-fold.h" +#include "context.h" +#include "tree-ssa-alias.h" +#include "tree-ssa.h" +#include "stringpool.h" +#if BUILDING_GCC_VERSION >= 7000 +#include "tree-vrp.h" +#endif +#include "tree-ssanames.h" +#include "print-tree.h" +#include "tree-eh.h" +#include "stmt.h" +#include "gimplify.h" +#endif + +#include "gimple.h" + +#if BUILDING_GCC_VERSION >= 4009 +#include "tree-ssa-operands.h" +#include "tree-phinodes.h" +#include "tree-cfg.h" +#include "gimple-iterator.h" +#include "gimple-ssa.h" +#include "ssa-iterators.h" +#endif + +#if BUILDING_GCC_VERSION >= 5000 +#include "builtins.h" +#endif + +/* missing from basic_block.h... */ +void debug_dominance_info(enum cdi_direction dir); +void debug_dominance_tree(enum cdi_direction dir, basic_block root); + +#if BUILDING_GCC_VERSION == 4006 +void debug_gimple_stmt(gimple); +void debug_gimple_seq(gimple_seq); +void print_gimple_seq(FILE *, gimple_seq, int, int); +void print_gimple_stmt(FILE *, gimple, int, int); +void print_gimple_expr(FILE *, gimple, int, int); +void dump_gimple_stmt(pretty_printer *, gimple, int, int); +#endif + +#ifndef __unused +#define __unused __attribute__((__unused__)) +#endif +#ifndef __visible +#define __visible __attribute__((visibility("default"))) +#endif + +#define DECL_NAME_POINTER(node) IDENTIFIER_POINTER(DECL_NAME(node)) +#define DECL_NAME_LENGTH(node) IDENTIFIER_LENGTH(DECL_NAME(node)) +#define TYPE_NAME_POINTER(node) IDENTIFIER_POINTER(TYPE_NAME(node)) +#define TYPE_NAME_LENGTH(node) IDENTIFIER_LENGTH(TYPE_NAME(node)) + +/* should come from c-tree.h if only it were installed for gcc 4.5... */ +#define C_TYPE_FIELDS_READONLY(TYPE) TREE_LANG_FLAG_1(TYPE) + +static inline tree build_const_char_string(int len, const char *str) +{ + tree cstr, elem, index, type; + + cstr = build_string(len, str); + elem = build_type_variant(char_type_node, 1, 0); + index = build_index_type(size_int(len - 1)); + type = build_array_type(elem, index); + TREE_TYPE(cstr) = type; + TREE_CONSTANT(cstr) = 1; + TREE_READONLY(cstr) = 1; + TREE_STATIC(cstr) = 1; + return cstr; +} + +#define PASS_INFO(NAME, REF, ID, POS) \ +struct register_pass_info NAME##_pass_info = { \ + .pass = make_##NAME##_pass(), \ + .reference_pass_name = REF, \ + .ref_pass_instance_number = ID, \ + .pos_op = POS, \ +} + +#if BUILDING_GCC_VERSION == 4005 +#define FOR_EACH_LOCAL_DECL(FUN, I, D) \ + for (tree vars = (FUN)->local_decls, (I) = 0; \ + vars && ((D) = TREE_VALUE(vars)); \ + vars = TREE_CHAIN(vars), (I)++) +#define DECL_CHAIN(NODE) (TREE_CHAIN(DECL_MINIMAL_CHECK(NODE))) +#define FOR_EACH_VEC_ELT(T, V, I, P) \ + for (I = 0; VEC_iterate(T, (V), (I), (P)); ++(I)) +#define TODO_rebuild_cgraph_edges 0 +#define SCOPE_FILE_SCOPE_P(EXP) (!(EXP)) + +#ifndef O_BINARY +#define O_BINARY 0 +#endif + +typedef struct varpool_node *varpool_node_ptr; + +static inline bool gimple_call_builtin_p(gimple stmt, enum built_in_function code) +{ + tree fndecl; + + if (!is_gimple_call(stmt)) + return false; + fndecl = gimple_call_fndecl(stmt); + if (!fndecl || DECL_BUILT_IN_CLASS(fndecl) != BUILT_IN_NORMAL) + return false; + return DECL_FUNCTION_CODE(fndecl) == code; +} + +static inline bool is_simple_builtin(tree decl) +{ + if (decl && DECL_BUILT_IN_CLASS(decl) != BUILT_IN_NORMAL) + return false; + + switch (DECL_FUNCTION_CODE(decl)) { + /* Builtins that expand to constants. */ + case BUILT_IN_CONSTANT_P: + case BUILT_IN_EXPECT: + case BUILT_IN_OBJECT_SIZE: + case BUILT_IN_UNREACHABLE: + /* Simple register moves or loads from stack. */ + case BUILT_IN_RETURN_ADDRESS: + case BUILT_IN_EXTRACT_RETURN_ADDR: + case BUILT_IN_FROB_RETURN_ADDR: + case BUILT_IN_RETURN: + case BUILT_IN_AGGREGATE_INCOMING_ADDRESS: + case BUILT_IN_FRAME_ADDRESS: + case BUILT_IN_VA_END: + case BUILT_IN_STACK_SAVE: + case BUILT_IN_STACK_RESTORE: + /* Exception state returns or moves registers around. */ + case BUILT_IN_EH_FILTER: + case BUILT_IN_EH_POINTER: + case BUILT_IN_EH_COPY_VALUES: + return true; + + default: + return false; + } +} + +static inline void add_local_decl(struct function *fun, tree d) +{ + gcc_assert(TREE_CODE(d) == VAR_DECL); + fun->local_decls = tree_cons(NULL_TREE, d, fun->local_decls); +} +#endif + +#if BUILDING_GCC_VERSION <= 4006 +#define ANY_RETURN_P(rtx) (GET_CODE(rtx) == RETURN) +#define C_DECL_REGISTER(EXP) DECL_LANG_FLAG_4(EXP) +#define EDGE_PRESERVE 0ULL +#define HOST_WIDE_INT_PRINT_HEX_PURE "%" HOST_WIDE_INT_PRINT "x" +#define flag_fat_lto_objects true + +#define get_random_seed(noinit) ({ \ + unsigned HOST_WIDE_INT seed; \ + sscanf(get_random_seed(noinit), "%" HOST_WIDE_INT_PRINT "x", &seed); \ + seed * seed; }) + +#define int_const_binop(code, arg1, arg2) \ + int_const_binop((code), (arg1), (arg2), 0) + +static inline bool gimple_clobber_p(gimple s __unused) +{ + return false; +} + +static inline bool gimple_asm_clobbers_memory_p(const_gimple stmt) +{ + unsigned i; + + for (i = 0; i < gimple_asm_nclobbers(stmt); i++) { + tree op = gimple_asm_clobber_op(stmt, i); + + if (!strcmp(TREE_STRING_POINTER(TREE_VALUE(op)), "memory")) + return true; + } + + return false; +} + +static inline tree builtin_decl_implicit(enum built_in_function fncode) +{ + return implicit_built_in_decls[fncode]; +} + +static inline int ipa_reverse_postorder(struct cgraph_node **order) +{ + return cgraph_postorder(order); +} + +static inline struct cgraph_node *cgraph_create_node(tree decl) +{ + return cgraph_node(decl); +} + +static inline struct cgraph_node *cgraph_get_create_node(tree decl) +{ + struct cgraph_node *node = cgraph_get_node(decl); + + return node ? node : cgraph_node(decl); +} + +static inline bool cgraph_function_with_gimple_body_p(struct cgraph_node *node) +{ + return node->analyzed && !node->thunk.thunk_p && !node->alias; +} + +static inline struct cgraph_node *cgraph_first_function_with_gimple_body(void) +{ + struct cgraph_node *node; + + for (node = cgraph_nodes; node; node = node->next) + if (cgraph_function_with_gimple_body_p(node)) + return node; + return NULL; +} + +static inline struct cgraph_node *cgraph_next_function_with_gimple_body(struct cgraph_node *node) +{ + for (node = node->next; node; node = node->next) + if (cgraph_function_with_gimple_body_p(node)) + return node; + return NULL; +} + +static inline bool cgraph_for_node_and_aliases(cgraph_node_ptr node, bool (*callback)(cgraph_node_ptr, void *), void *data, bool include_overwritable) +{ + cgraph_node_ptr alias; + + if (callback(node, data)) + return true; + + for (alias = node->same_body; alias; alias = alias->next) { + if (include_overwritable || cgraph_function_body_availability(alias) > AVAIL_OVERWRITABLE) + if (cgraph_for_node_and_aliases(alias, callback, data, include_overwritable)) + return true; + } + + return false; +} + +#define FOR_EACH_FUNCTION_WITH_GIMPLE_BODY(node) \ + for ((node) = cgraph_first_function_with_gimple_body(); (node); \ + (node) = cgraph_next_function_with_gimple_body(node)) + +static inline void varpool_add_new_variable(tree decl) +{ + varpool_finalize_decl(decl); +} +#endif + +#if BUILDING_GCC_VERSION <= 4007 +#define FOR_EACH_FUNCTION(node) \ + for (node = cgraph_nodes; node; node = node->next) +#define FOR_EACH_VARIABLE(node) \ + for (node = varpool_nodes; node; node = node->next) +#define PROP_loops 0 +#define NODE_SYMBOL(node) (node) +#define NODE_DECL(node) (node)->decl +#define INSN_LOCATION(INSN) RTL_LOCATION(INSN) +#define vNULL NULL + +static inline int bb_loop_depth(const_basic_block bb) +{ + return bb->loop_father ? loop_depth(bb->loop_father) : 0; +} + +static inline bool gimple_store_p(gimple gs) +{ + tree lhs = gimple_get_lhs(gs); + + return lhs && !is_gimple_reg(lhs); +} + +static inline void gimple_init_singleton(gimple g __unused) +{ +} +#endif + +#if BUILDING_GCC_VERSION == 4007 || BUILDING_GCC_VERSION == 4008 +static inline struct cgraph_node *cgraph_alias_target(struct cgraph_node *n) +{ + return cgraph_alias_aliased_node(n); +} +#endif + +#if BUILDING_GCC_VERSION <= 4008 +#define ENTRY_BLOCK_PTR_FOR_FN(FN) ENTRY_BLOCK_PTR_FOR_FUNCTION(FN) +#define EXIT_BLOCK_PTR_FOR_FN(FN) EXIT_BLOCK_PTR_FOR_FUNCTION(FN) +#define basic_block_info_for_fn(FN) ((FN)->cfg->x_basic_block_info) +#define n_basic_blocks_for_fn(FN) ((FN)->cfg->x_n_basic_blocks) +#define n_edges_for_fn(FN) ((FN)->cfg->x_n_edges) +#define last_basic_block_for_fn(FN) ((FN)->cfg->x_last_basic_block) +#define label_to_block_map_for_fn(FN) ((FN)->cfg->x_label_to_block_map) +#define profile_status_for_fn(FN) ((FN)->cfg->x_profile_status) +#define BASIC_BLOCK_FOR_FN(FN, N) BASIC_BLOCK_FOR_FUNCTION((FN), (N)) +#define NODE_IMPLICIT_ALIAS(node) (node)->same_body_alias +#define VAR_P(NODE) (TREE_CODE(NODE) == VAR_DECL) + +static inline bool tree_fits_shwi_p(const_tree t) +{ + if (t == NULL_TREE || TREE_CODE(t) != INTEGER_CST) + return false; + + if (TREE_INT_CST_HIGH(t) == 0 && (HOST_WIDE_INT)TREE_INT_CST_LOW(t) >= 0) + return true; + + if (TREE_INT_CST_HIGH(t) == -1 && (HOST_WIDE_INT)TREE_INT_CST_LOW(t) < 0 && !TYPE_UNSIGNED(TREE_TYPE(t))) + return true; + + return false; +} + +static inline bool tree_fits_uhwi_p(const_tree t) +{ + if (t == NULL_TREE || TREE_CODE(t) != INTEGER_CST) + return false; + + return TREE_INT_CST_HIGH(t) == 0; +} + +static inline HOST_WIDE_INT tree_to_shwi(const_tree t) +{ + gcc_assert(tree_fits_shwi_p(t)); + return TREE_INT_CST_LOW(t); +} + +static inline unsigned HOST_WIDE_INT tree_to_uhwi(const_tree t) +{ + gcc_assert(tree_fits_uhwi_p(t)); + return TREE_INT_CST_LOW(t); +} + +static inline const char *get_tree_code_name(enum tree_code code) +{ + gcc_assert(code < MAX_TREE_CODES); + return tree_code_name[code]; +} + +#define ipa_remove_stmt_references(cnode, stmt) + +typedef union gimple_statement_d gasm; +typedef union gimple_statement_d gassign; +typedef union gimple_statement_d gcall; +typedef union gimple_statement_d gcond; +typedef union gimple_statement_d gdebug; +typedef union gimple_statement_d ggoto; +typedef union gimple_statement_d gphi; +typedef union gimple_statement_d greturn; + +static inline gasm *as_a_gasm(gimple stmt) +{ + return stmt; +} + +static inline const gasm *as_a_const_gasm(const_gimple stmt) +{ + return stmt; +} + +static inline gassign *as_a_gassign(gimple stmt) +{ + return stmt; +} + +static inline const gassign *as_a_const_gassign(const_gimple stmt) +{ + return stmt; +} + +static inline gcall *as_a_gcall(gimple stmt) +{ + return stmt; +} + +static inline const gcall *as_a_const_gcall(const_gimple stmt) +{ + return stmt; +} + +static inline gcond *as_a_gcond(gimple stmt) +{ + return stmt; +} + +static inline const gcond *as_a_const_gcond(const_gimple stmt) +{ + return stmt; +} + +static inline gdebug *as_a_gdebug(gimple stmt) +{ + return stmt; +} + +static inline const gdebug *as_a_const_gdebug(const_gimple stmt) +{ + return stmt; +} + +static inline ggoto *as_a_ggoto(gimple stmt) +{ + return stmt; +} + +static inline const ggoto *as_a_const_ggoto(const_gimple stmt) +{ + return stmt; +} + +static inline gphi *as_a_gphi(gimple stmt) +{ + return stmt; +} + +static inline const gphi *as_a_const_gphi(const_gimple stmt) +{ + return stmt; +} + +static inline greturn *as_a_greturn(gimple stmt) +{ + return stmt; +} + +static inline const greturn *as_a_const_greturn(const_gimple stmt) +{ + return stmt; +} +#endif + +#if BUILDING_GCC_VERSION == 4008 +#define NODE_SYMBOL(node) (&(node)->symbol) +#define NODE_DECL(node) (node)->symbol.decl +#endif + +#if BUILDING_GCC_VERSION >= 4008 +#define add_referenced_var(var) +#define mark_sym_for_renaming(var) +#define varpool_mark_needed_node(node) +#define create_var_ann(var) +#define TODO_dump_func 0 +#define TODO_dump_cgraph 0 +#endif + +#if BUILDING_GCC_VERSION <= 4009 +#define TODO_verify_il 0 +#define AVAIL_INTERPOSABLE AVAIL_OVERWRITABLE + +#define section_name_prefix LTO_SECTION_NAME_PREFIX +#define fatal_error(loc, gmsgid, ...) fatal_error((gmsgid), __VA_ARGS__) + +rtx emit_move_insn(rtx x, rtx y); + +typedef struct rtx_def rtx_insn; + +static inline const char *get_decl_section_name(const_tree decl) +{ + if (DECL_SECTION_NAME(decl) == NULL_TREE) + return NULL; + + return TREE_STRING_POINTER(DECL_SECTION_NAME(decl)); +} + +static inline void set_decl_section_name(tree node, const char *value) +{ + if (value) + DECL_SECTION_NAME(node) = build_string(strlen(value) + 1, value); + else + DECL_SECTION_NAME(node) = NULL; +} +#endif + +#if BUILDING_GCC_VERSION == 4009 +typedef struct gimple_statement_asm gasm; +typedef struct gimple_statement_base gassign; +typedef struct gimple_statement_call gcall; +typedef struct gimple_statement_base gcond; +typedef struct gimple_statement_base gdebug; +typedef struct gimple_statement_base ggoto; +typedef struct gimple_statement_phi gphi; +typedef struct gimple_statement_base greturn; + +static inline gasm *as_a_gasm(gimple stmt) +{ + return as_a<gasm>(stmt); +} + +static inline const gasm *as_a_const_gasm(const_gimple stmt) +{ + return as_a<const gasm>(stmt); +} + +static inline gassign *as_a_gassign(gimple stmt) +{ + return stmt; +} + +static inline const gassign *as_a_const_gassign(const_gimple stmt) +{ + return stmt; +} + +static inline gcall *as_a_gcall(gimple stmt) +{ + return as_a<gcall>(stmt); +} + +static inline const gcall *as_a_const_gcall(const_gimple stmt) +{ + return as_a<const gcall>(stmt); +} + +static inline gcond *as_a_gcond(gimple stmt) +{ + return stmt; +} + +static inline const gcond *as_a_const_gcond(const_gimple stmt) +{ + return stmt; +} + +static inline gdebug *as_a_gdebug(gimple stmt) +{ + return stmt; +} + +static inline const gdebug *as_a_const_gdebug(const_gimple stmt) +{ + return stmt; +} + +static inline ggoto *as_a_ggoto(gimple stmt) +{ + return stmt; +} + +static inline const ggoto *as_a_const_ggoto(const_gimple stmt) +{ + return stmt; +} + +static inline gphi *as_a_gphi(gimple stmt) +{ + return as_a<gphi>(stmt); +} + +static inline const gphi *as_a_const_gphi(const_gimple stmt) +{ + return as_a<const gphi>(stmt); +} + +static inline greturn *as_a_greturn(gimple stmt) +{ + return stmt; +} + +static inline const greturn *as_a_const_greturn(const_gimple stmt) +{ + return stmt; +} +#endif + +#if BUILDING_GCC_VERSION >= 4009 +#define TODO_ggc_collect 0 +#define NODE_SYMBOL(node) (node) +#define NODE_DECL(node) (node)->decl +#define cgraph_node_name(node) (node)->name() +#define NODE_IMPLICIT_ALIAS(node) (node)->cpp_implicit_alias + +static inline opt_pass *get_pass_for_id(int id) +{ + return g->get_passes()->get_pass_for_id(id); +} +#endif + +#if BUILDING_GCC_VERSION >= 5000 && BUILDING_GCC_VERSION < 6000 +/* gimple related */ +template <> +template <> +inline bool is_a_helper<const gassign *>::test(const_gimple gs) +{ + return gs->code == GIMPLE_ASSIGN; +} +#endif + +#if BUILDING_GCC_VERSION >= 5000 +#define TODO_verify_ssa TODO_verify_il +#define TODO_verify_flow TODO_verify_il +#define TODO_verify_stmts TODO_verify_il +#define TODO_verify_rtl_sharing TODO_verify_il + +#define INSN_DELETED_P(insn) (insn)->deleted() + +static inline const char *get_decl_section_name(const_tree decl) +{ + return DECL_SECTION_NAME(decl); +} + +/* symtab/cgraph related */ +#define debug_cgraph_node(node) (node)->debug() +#define cgraph_get_node(decl) cgraph_node::get(decl) +#define cgraph_get_create_node(decl) cgraph_node::get_create(decl) +#define cgraph_create_node(decl) cgraph_node::create(decl) +#define cgraph_n_nodes symtab->cgraph_count +#define cgraph_max_uid symtab->cgraph_max_uid +#define varpool_get_node(decl) varpool_node::get(decl) +#define dump_varpool_node(file, node) (node)->dump(file) + +#if BUILDING_GCC_VERSION >= 8000 +#define cgraph_create_edge(caller, callee, call_stmt, count, freq) \ + (caller)->create_edge((callee), (call_stmt), (count)) + +#define cgraph_create_edge_including_clones(caller, callee, \ + old_call_stmt, call_stmt, count, freq, reason) \ + (caller)->create_edge_including_clones((callee), \ + (old_call_stmt), (call_stmt), (count), (reason)) +#else +#define cgraph_create_edge(caller, callee, call_stmt, count, freq) \ + (caller)->create_edge((callee), (call_stmt), (count), (freq)) + +#define cgraph_create_edge_including_clones(caller, callee, \ + old_call_stmt, call_stmt, count, freq, reason) \ + (caller)->create_edge_including_clones((callee), \ + (old_call_stmt), (call_stmt), (count), (freq), (reason)) +#endif + +typedef struct cgraph_node *cgraph_node_ptr; +typedef struct cgraph_edge *cgraph_edge_p; +typedef struct varpool_node *varpool_node_ptr; + +static inline void change_decl_assembler_name(tree decl, tree name) +{ + symtab->change_decl_assembler_name(decl, name); +} + +static inline void varpool_finalize_decl(tree decl) +{ + varpool_node::finalize_decl(decl); +} + +static inline void varpool_add_new_variable(tree decl) +{ + varpool_node::add(decl); +} + +static inline unsigned int rebuild_cgraph_edges(void) +{ + return cgraph_edge::rebuild_edges(); +} + +static inline cgraph_node_ptr cgraph_function_node(cgraph_node_ptr node, enum availability *availability) +{ + return node->function_symbol(availability); +} + +static inline cgraph_node_ptr cgraph_function_or_thunk_node(cgraph_node_ptr node, enum availability *availability = NULL) +{ + return node->ultimate_alias_target(availability); +} + +static inline bool cgraph_only_called_directly_p(cgraph_node_ptr node) +{ + return node->only_called_directly_p(); +} + +static inline enum availability cgraph_function_body_availability(cgraph_node_ptr node) +{ + return node->get_availability(); +} + +static inline cgraph_node_ptr cgraph_alias_target(cgraph_node_ptr node) +{ + return node->get_alias_target(); +} + +static inline bool cgraph_for_node_and_aliases(cgraph_node_ptr node, bool (*callback)(cgraph_node_ptr, void *), void *data, bool include_overwritable) +{ + return node->call_for_symbol_thunks_and_aliases(callback, data, include_overwritable); +} + +static inline struct cgraph_node_hook_list *cgraph_add_function_insertion_hook(cgraph_node_hook hook, void *data) +{ + return symtab->add_cgraph_insertion_hook(hook, data); +} + +static inline void cgraph_remove_function_insertion_hook(struct cgraph_node_hook_list *entry) +{ + symtab->remove_cgraph_insertion_hook(entry); +} + +static inline struct cgraph_node_hook_list *cgraph_add_node_removal_hook(cgraph_node_hook hook, void *data) +{ + return symtab->add_cgraph_removal_hook(hook, data); +} + +static inline void cgraph_remove_node_removal_hook(struct cgraph_node_hook_list *entry) +{ + symtab->remove_cgraph_removal_hook(entry); +} + +static inline struct cgraph_2node_hook_list *cgraph_add_node_duplication_hook(cgraph_2node_hook hook, void *data) +{ + return symtab->add_cgraph_duplication_hook(hook, data); +} + +static inline void cgraph_remove_node_duplication_hook(struct cgraph_2node_hook_list *entry) +{ + symtab->remove_cgraph_duplication_hook(entry); +} + +static inline void cgraph_call_node_duplication_hooks(cgraph_node_ptr node, cgraph_node_ptr node2) +{ + symtab->call_cgraph_duplication_hooks(node, node2); +} + +static inline void cgraph_call_edge_duplication_hooks(cgraph_edge *cs1, cgraph_edge *cs2) +{ + symtab->call_edge_duplication_hooks(cs1, cs2); +} + +#if BUILDING_GCC_VERSION >= 6000 +typedef gimple *gimple_ptr; +typedef const gimple *const_gimple_ptr; +#define gimple gimple_ptr +#define const_gimple const_gimple_ptr +#undef CONST_CAST_GIMPLE +#define CONST_CAST_GIMPLE(X) CONST_CAST(gimple, (X)) +#endif + +/* gimple related */ +static inline gimple gimple_build_assign_with_ops(enum tree_code subcode, tree lhs, tree op1, tree op2 MEM_STAT_DECL) +{ + return gimple_build_assign(lhs, subcode, op1, op2 PASS_MEM_STAT); +} + +#if BUILDING_GCC_VERSION < 10000 +template <> +template <> +inline bool is_a_helper<const ggoto *>::test(const_gimple gs) +{ + return gs->code == GIMPLE_GOTO; +} + +template <> +template <> +inline bool is_a_helper<const greturn *>::test(const_gimple gs) +{ + return gs->code == GIMPLE_RETURN; +} +#endif + +static inline gasm *as_a_gasm(gimple stmt) +{ + return as_a<gasm *>(stmt); +} + +static inline const gasm *as_a_const_gasm(const_gimple stmt) +{ + return as_a<const gasm *>(stmt); +} + +static inline gassign *as_a_gassign(gimple stmt) +{ + return as_a<gassign *>(stmt); +} + +static inline const gassign *as_a_const_gassign(const_gimple stmt) +{ + return as_a<const gassign *>(stmt); +} + +static inline gcall *as_a_gcall(gimple stmt) +{ + return as_a<gcall *>(stmt); +} + +static inline const gcall *as_a_const_gcall(const_gimple stmt) +{ + return as_a<const gcall *>(stmt); +} + +static inline ggoto *as_a_ggoto(gimple stmt) +{ + return as_a<ggoto *>(stmt); +} + +static inline const ggoto *as_a_const_ggoto(const_gimple stmt) +{ + return as_a<const ggoto *>(stmt); +} + +static inline gphi *as_a_gphi(gimple stmt) +{ + return as_a<gphi *>(stmt); +} + +static inline const gphi *as_a_const_gphi(const_gimple stmt) +{ + return as_a<const gphi *>(stmt); +} + +static inline greturn *as_a_greturn(gimple stmt) +{ + return as_a<greturn *>(stmt); +} + +static inline const greturn *as_a_const_greturn(const_gimple stmt) +{ + return as_a<const greturn *>(stmt); +} + +/* IPA/LTO related */ +#define ipa_ref_list_referring_iterate(L, I, P) \ + (L)->referring.iterate((I), &(P)) +#define ipa_ref_list_reference_iterate(L, I, P) \ + (L)->reference.iterate((I), &(P)) + +static inline cgraph_node_ptr ipa_ref_referring_node(struct ipa_ref *ref) +{ + return dyn_cast<cgraph_node_ptr>(ref->referring); +} + +static inline void ipa_remove_stmt_references(symtab_node *referring_node, gimple stmt) +{ + referring_node->remove_stmt_references(stmt); +} +#endif + +#if BUILDING_GCC_VERSION < 6000 +#define get_inner_reference(exp, pbitsize, pbitpos, poffset, pmode, punsignedp, preversep, pvolatilep, keep_aligning) \ + get_inner_reference(exp, pbitsize, pbitpos, poffset, pmode, punsignedp, pvolatilep, keep_aligning) +#define gen_rtx_set(ARG0, ARG1) gen_rtx_SET(VOIDmode, (ARG0), (ARG1)) +#endif + +#if BUILDING_GCC_VERSION >= 6000 +#define gen_rtx_set(ARG0, ARG1) gen_rtx_SET((ARG0), (ARG1)) +#endif + +#ifdef __cplusplus +static inline void debug_tree(const_tree t) +{ + debug_tree(CONST_CAST_TREE(t)); +} + +static inline void debug_gimple_stmt(const_gimple s) +{ + debug_gimple_stmt(CONST_CAST_GIMPLE(s)); +} +#else +#define debug_tree(t) debug_tree(CONST_CAST_TREE(t)) +#define debug_gimple_stmt(s) debug_gimple_stmt(CONST_CAST_GIMPLE(s)) +#endif + +#if BUILDING_GCC_VERSION >= 7000 +#define get_inner_reference(exp, pbitsize, pbitpos, poffset, pmode, punsignedp, preversep, pvolatilep, keep_aligning) \ + get_inner_reference(exp, pbitsize, pbitpos, poffset, pmode, punsignedp, preversep, pvolatilep) +#endif + +#if BUILDING_GCC_VERSION < 7000 +#define SET_DECL_ALIGN(decl, align) DECL_ALIGN(decl) = (align) +#define SET_DECL_MODE(decl, mode) DECL_MODE(decl) = (mode) +#endif + +#endif diff --git a/src/net/scripts/gcc-plugins/gcc-generate-gimple-pass.h b/src/net/scripts/gcc-plugins/gcc-generate-gimple-pass.h new file mode 100644 index 0000000..f20797e --- /dev/null +++ b/src/net/scripts/gcc-plugins/gcc-generate-gimple-pass.h @@ -0,0 +1,176 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Generator for GIMPLE pass related boilerplate code/data + * + * Supports gcc 4.5-6 + * + * Usage: + * + * 1. before inclusion define PASS_NAME + * 2. before inclusion define NO_* for unimplemented callbacks + * NO_GATE + * NO_EXECUTE + * 3. before inclusion define PROPERTIES_* and TODO_FLAGS_* to override + * the default 0 values + * 4. for convenience, all the above will be undefined after inclusion! + * 5. the only exported name is make_PASS_NAME_pass() to register with gcc + */ + +#ifndef PASS_NAME +#error at least PASS_NAME must be defined +#else +#define __GCC_PLUGIN_STRINGIFY(n) #n +#define _GCC_PLUGIN_STRINGIFY(n) __GCC_PLUGIN_STRINGIFY(n) +#define _GCC_PLUGIN_CONCAT2(x, y) x ## y +#define _GCC_PLUGIN_CONCAT3(x, y, z) x ## y ## z + +#define __PASS_NAME_PASS_DATA(n) _GCC_PLUGIN_CONCAT2(n, _pass_data) +#define _PASS_NAME_PASS_DATA __PASS_NAME_PASS_DATA(PASS_NAME) + +#define __PASS_NAME_PASS(n) _GCC_PLUGIN_CONCAT2(n, _pass) +#define _PASS_NAME_PASS __PASS_NAME_PASS(PASS_NAME) + +#define _PASS_NAME_NAME _GCC_PLUGIN_STRINGIFY(PASS_NAME) + +#define __MAKE_PASS_NAME_PASS(n) _GCC_PLUGIN_CONCAT3(make_, n, _pass) +#define _MAKE_PASS_NAME_PASS __MAKE_PASS_NAME_PASS(PASS_NAME) + +#ifdef NO_GATE +#define _GATE NULL +#define _HAS_GATE false +#else +#define __GATE(n) _GCC_PLUGIN_CONCAT2(n, _gate) +#define _GATE __GATE(PASS_NAME) +#define _HAS_GATE true +#endif + +#ifdef NO_EXECUTE +#define _EXECUTE NULL +#define _HAS_EXECUTE false +#else +#define __EXECUTE(n) _GCC_PLUGIN_CONCAT2(n, _execute) +#define _EXECUTE __EXECUTE(PASS_NAME) +#define _HAS_EXECUTE true +#endif + +#ifndef PROPERTIES_REQUIRED +#define PROPERTIES_REQUIRED 0 +#endif + +#ifndef PROPERTIES_PROVIDED +#define PROPERTIES_PROVIDED 0 +#endif + +#ifndef PROPERTIES_DESTROYED +#define PROPERTIES_DESTROYED 0 +#endif + +#ifndef TODO_FLAGS_START +#define TODO_FLAGS_START 0 +#endif + +#ifndef TODO_FLAGS_FINISH +#define TODO_FLAGS_FINISH 0 +#endif + +#if BUILDING_GCC_VERSION >= 4009 +namespace { +static const pass_data _PASS_NAME_PASS_DATA = { +#else +static struct gimple_opt_pass _PASS_NAME_PASS = { + .pass = { +#endif + .type = GIMPLE_PASS, + .name = _PASS_NAME_NAME, +#if BUILDING_GCC_VERSION >= 4008 + .optinfo_flags = OPTGROUP_NONE, +#endif +#if BUILDING_GCC_VERSION >= 5000 +#elif BUILDING_GCC_VERSION == 4009 + .has_gate = _HAS_GATE, + .has_execute = _HAS_EXECUTE, +#else + .gate = _GATE, + .execute = _EXECUTE, + .sub = NULL, + .next = NULL, + .static_pass_number = 0, +#endif + .tv_id = TV_NONE, + .properties_required = PROPERTIES_REQUIRED, + .properties_provided = PROPERTIES_PROVIDED, + .properties_destroyed = PROPERTIES_DESTROYED, + .todo_flags_start = TODO_FLAGS_START, + .todo_flags_finish = TODO_FLAGS_FINISH, +#if BUILDING_GCC_VERSION < 4009 + } +#endif +}; + +#if BUILDING_GCC_VERSION >= 4009 +class _PASS_NAME_PASS : public gimple_opt_pass { +public: + _PASS_NAME_PASS() : gimple_opt_pass(_PASS_NAME_PASS_DATA, g) {} + +#ifndef NO_GATE +#if BUILDING_GCC_VERSION >= 5000 + virtual bool gate(function *) { return _GATE(); } +#else + virtual bool gate(void) { return _GATE(); } +#endif +#endif + + virtual opt_pass * clone () { return new _PASS_NAME_PASS(); } + +#ifndef NO_EXECUTE +#if BUILDING_GCC_VERSION >= 5000 + virtual unsigned int execute(function *) { return _EXECUTE(); } +#else + virtual unsigned int execute(void) { return _EXECUTE(); } +#endif +#endif +}; +} + +opt_pass *_MAKE_PASS_NAME_PASS(void) +{ + return new _PASS_NAME_PASS(); +} +#else +struct opt_pass *_MAKE_PASS_NAME_PASS(void) +{ + return &_PASS_NAME_PASS.pass; +} +#endif + +/* clean up user provided defines */ +#undef PASS_NAME +#undef NO_GATE +#undef NO_EXECUTE + +#undef PROPERTIES_DESTROYED +#undef PROPERTIES_PROVIDED +#undef PROPERTIES_REQUIRED +#undef TODO_FLAGS_FINISH +#undef TODO_FLAGS_START + +/* clean up generated defines */ +#undef _EXECUTE +#undef __EXECUTE +#undef _GATE +#undef __GATE +#undef _GCC_PLUGIN_CONCAT2 +#undef _GCC_PLUGIN_CONCAT3 +#undef _GCC_PLUGIN_STRINGIFY +#undef __GCC_PLUGIN_STRINGIFY +#undef _HAS_EXECUTE +#undef _HAS_GATE +#undef _MAKE_PASS_NAME_PASS +#undef __MAKE_PASS_NAME_PASS +#undef _PASS_NAME_NAME +#undef _PASS_NAME_PASS +#undef __PASS_NAME_PASS +#undef _PASS_NAME_PASS_DATA +#undef __PASS_NAME_PASS_DATA + +#endif /* PASS_NAME */ diff --git a/src/net/scripts/gcc-plugins/gcc-generate-ipa-pass.h b/src/net/scripts/gcc-plugins/gcc-generate-ipa-pass.h new file mode 100644 index 0000000..92bb4f3 --- /dev/null +++ b/src/net/scripts/gcc-plugins/gcc-generate-ipa-pass.h @@ -0,0 +1,290 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Generator for IPA pass related boilerplate code/data + * + * Supports gcc 4.5-6 + * + * Usage: + * + * 1. before inclusion define PASS_NAME + * 2. before inclusion define NO_* for unimplemented callbacks + * NO_GENERATE_SUMMARY + * NO_READ_SUMMARY + * NO_WRITE_SUMMARY + * NO_READ_OPTIMIZATION_SUMMARY + * NO_WRITE_OPTIMIZATION_SUMMARY + * NO_STMT_FIXUP + * NO_FUNCTION_TRANSFORM + * NO_VARIABLE_TRANSFORM + * NO_GATE + * NO_EXECUTE + * 3. before inclusion define PROPERTIES_* and *TODO_FLAGS_* to override + * the default 0 values + * 4. for convenience, all the above will be undefined after inclusion! + * 5. the only exported name is make_PASS_NAME_pass() to register with gcc + */ + +#ifndef PASS_NAME +#error at least PASS_NAME must be defined +#else +#define __GCC_PLUGIN_STRINGIFY(n) #n +#define _GCC_PLUGIN_STRINGIFY(n) __GCC_PLUGIN_STRINGIFY(n) +#define _GCC_PLUGIN_CONCAT2(x, y) x ## y +#define _GCC_PLUGIN_CONCAT3(x, y, z) x ## y ## z + +#define __PASS_NAME_PASS_DATA(n) _GCC_PLUGIN_CONCAT2(n, _pass_data) +#define _PASS_NAME_PASS_DATA __PASS_NAME_PASS_DATA(PASS_NAME) + +#define __PASS_NAME_PASS(n) _GCC_PLUGIN_CONCAT2(n, _pass) +#define _PASS_NAME_PASS __PASS_NAME_PASS(PASS_NAME) + +#define _PASS_NAME_NAME _GCC_PLUGIN_STRINGIFY(PASS_NAME) + +#define __MAKE_PASS_NAME_PASS(n) _GCC_PLUGIN_CONCAT3(make_, n, _pass) +#define _MAKE_PASS_NAME_PASS __MAKE_PASS_NAME_PASS(PASS_NAME) + +#ifdef NO_GENERATE_SUMMARY +#define _GENERATE_SUMMARY NULL +#else +#define __GENERATE_SUMMARY(n) _GCC_PLUGIN_CONCAT2(n, _generate_summary) +#define _GENERATE_SUMMARY __GENERATE_SUMMARY(PASS_NAME) +#endif + +#ifdef NO_READ_SUMMARY +#define _READ_SUMMARY NULL +#else +#define __READ_SUMMARY(n) _GCC_PLUGIN_CONCAT2(n, _read_summary) +#define _READ_SUMMARY __READ_SUMMARY(PASS_NAME) +#endif + +#ifdef NO_WRITE_SUMMARY +#define _WRITE_SUMMARY NULL +#else +#define __WRITE_SUMMARY(n) _GCC_PLUGIN_CONCAT2(n, _write_summary) +#define _WRITE_SUMMARY __WRITE_SUMMARY(PASS_NAME) +#endif + +#ifdef NO_READ_OPTIMIZATION_SUMMARY +#define _READ_OPTIMIZATION_SUMMARY NULL +#else +#define __READ_OPTIMIZATION_SUMMARY(n) _GCC_PLUGIN_CONCAT2(n, _read_optimization_summary) +#define _READ_OPTIMIZATION_SUMMARY __READ_OPTIMIZATION_SUMMARY(PASS_NAME) +#endif + +#ifdef NO_WRITE_OPTIMIZATION_SUMMARY +#define _WRITE_OPTIMIZATION_SUMMARY NULL +#else +#define __WRITE_OPTIMIZATION_SUMMARY(n) _GCC_PLUGIN_CONCAT2(n, _write_optimization_summary) +#define _WRITE_OPTIMIZATION_SUMMARY __WRITE_OPTIMIZATION_SUMMARY(PASS_NAME) +#endif + +#ifdef NO_STMT_FIXUP +#define _STMT_FIXUP NULL +#else +#define __STMT_FIXUP(n) _GCC_PLUGIN_CONCAT2(n, _stmt_fixup) +#define _STMT_FIXUP __STMT_FIXUP(PASS_NAME) +#endif + +#ifdef NO_FUNCTION_TRANSFORM +#define _FUNCTION_TRANSFORM NULL +#else +#define __FUNCTION_TRANSFORM(n) _GCC_PLUGIN_CONCAT2(n, _function_transform) +#define _FUNCTION_TRANSFORM __FUNCTION_TRANSFORM(PASS_NAME) +#endif + +#ifdef NO_VARIABLE_TRANSFORM +#define _VARIABLE_TRANSFORM NULL +#else +#define __VARIABLE_TRANSFORM(n) _GCC_PLUGIN_CONCAT2(n, _variable_transform) +#define _VARIABLE_TRANSFORM __VARIABLE_TRANSFORM(PASS_NAME) +#endif + +#ifdef NO_GATE +#define _GATE NULL +#define _HAS_GATE false +#else +#define __GATE(n) _GCC_PLUGIN_CONCAT2(n, _gate) +#define _GATE __GATE(PASS_NAME) +#define _HAS_GATE true +#endif + +#ifdef NO_EXECUTE +#define _EXECUTE NULL +#define _HAS_EXECUTE false +#else +#define __EXECUTE(n) _GCC_PLUGIN_CONCAT2(n, _execute) +#define _EXECUTE __EXECUTE(PASS_NAME) +#define _HAS_EXECUTE true +#endif + +#ifndef PROPERTIES_REQUIRED +#define PROPERTIES_REQUIRED 0 +#endif + +#ifndef PROPERTIES_PROVIDED +#define PROPERTIES_PROVIDED 0 +#endif + +#ifndef PROPERTIES_DESTROYED +#define PROPERTIES_DESTROYED 0 +#endif + +#ifndef TODO_FLAGS_START +#define TODO_FLAGS_START 0 +#endif + +#ifndef TODO_FLAGS_FINISH +#define TODO_FLAGS_FINISH 0 +#endif + +#ifndef FUNCTION_TRANSFORM_TODO_FLAGS_START +#define FUNCTION_TRANSFORM_TODO_FLAGS_START 0 +#endif + +#if BUILDING_GCC_VERSION >= 4009 +namespace { +static const pass_data _PASS_NAME_PASS_DATA = { +#else +static struct ipa_opt_pass_d _PASS_NAME_PASS = { + .pass = { +#endif + .type = IPA_PASS, + .name = _PASS_NAME_NAME, +#if BUILDING_GCC_VERSION >= 4008 + .optinfo_flags = OPTGROUP_NONE, +#endif +#if BUILDING_GCC_VERSION >= 5000 +#elif BUILDING_GCC_VERSION == 4009 + .has_gate = _HAS_GATE, + .has_execute = _HAS_EXECUTE, +#else + .gate = _GATE, + .execute = _EXECUTE, + .sub = NULL, + .next = NULL, + .static_pass_number = 0, +#endif + .tv_id = TV_NONE, + .properties_required = PROPERTIES_REQUIRED, + .properties_provided = PROPERTIES_PROVIDED, + .properties_destroyed = PROPERTIES_DESTROYED, + .todo_flags_start = TODO_FLAGS_START, + .todo_flags_finish = TODO_FLAGS_FINISH, +#if BUILDING_GCC_VERSION < 4009 + }, + .generate_summary = _GENERATE_SUMMARY, + .write_summary = _WRITE_SUMMARY, + .read_summary = _READ_SUMMARY, +#if BUILDING_GCC_VERSION >= 4006 + .write_optimization_summary = _WRITE_OPTIMIZATION_SUMMARY, + .read_optimization_summary = _READ_OPTIMIZATION_SUMMARY, +#endif + .stmt_fixup = _STMT_FIXUP, + .function_transform_todo_flags_start = FUNCTION_TRANSFORM_TODO_FLAGS_START, + .function_transform = _FUNCTION_TRANSFORM, + .variable_transform = _VARIABLE_TRANSFORM, +#endif +}; + +#if BUILDING_GCC_VERSION >= 4009 +class _PASS_NAME_PASS : public ipa_opt_pass_d { +public: + _PASS_NAME_PASS() : ipa_opt_pass_d(_PASS_NAME_PASS_DATA, + g, + _GENERATE_SUMMARY, + _WRITE_SUMMARY, + _READ_SUMMARY, + _WRITE_OPTIMIZATION_SUMMARY, + _READ_OPTIMIZATION_SUMMARY, + _STMT_FIXUP, + FUNCTION_TRANSFORM_TODO_FLAGS_START, + _FUNCTION_TRANSFORM, + _VARIABLE_TRANSFORM) {} + +#ifndef NO_GATE +#if BUILDING_GCC_VERSION >= 5000 + virtual bool gate(function *) { return _GATE(); } +#else + virtual bool gate(void) { return _GATE(); } +#endif +#endif + + virtual opt_pass *clone() { return new _PASS_NAME_PASS(); } + +#ifndef NO_EXECUTE +#if BUILDING_GCC_VERSION >= 5000 + virtual unsigned int execute(function *) { return _EXECUTE(); } +#else + virtual unsigned int execute(void) { return _EXECUTE(); } +#endif +#endif +}; +} + +opt_pass *_MAKE_PASS_NAME_PASS(void) +{ + return new _PASS_NAME_PASS(); +} +#else +struct opt_pass *_MAKE_PASS_NAME_PASS(void) +{ + return &_PASS_NAME_PASS.pass; +} +#endif + +/* clean up user provided defines */ +#undef PASS_NAME +#undef NO_GENERATE_SUMMARY +#undef NO_WRITE_SUMMARY +#undef NO_READ_SUMMARY +#undef NO_WRITE_OPTIMIZATION_SUMMARY +#undef NO_READ_OPTIMIZATION_SUMMARY +#undef NO_STMT_FIXUP +#undef NO_FUNCTION_TRANSFORM +#undef NO_VARIABLE_TRANSFORM +#undef NO_GATE +#undef NO_EXECUTE + +#undef FUNCTION_TRANSFORM_TODO_FLAGS_START +#undef PROPERTIES_DESTROYED +#undef PROPERTIES_PROVIDED +#undef PROPERTIES_REQUIRED +#undef TODO_FLAGS_FINISH +#undef TODO_FLAGS_START + +/* clean up generated defines */ +#undef _EXECUTE +#undef __EXECUTE +#undef _FUNCTION_TRANSFORM +#undef __FUNCTION_TRANSFORM +#undef _GATE +#undef __GATE +#undef _GCC_PLUGIN_CONCAT2 +#undef _GCC_PLUGIN_CONCAT3 +#undef _GCC_PLUGIN_STRINGIFY +#undef __GCC_PLUGIN_STRINGIFY +#undef _GENERATE_SUMMARY +#undef __GENERATE_SUMMARY +#undef _HAS_EXECUTE +#undef _HAS_GATE +#undef _MAKE_PASS_NAME_PASS +#undef __MAKE_PASS_NAME_PASS +#undef _PASS_NAME_NAME +#undef _PASS_NAME_PASS +#undef __PASS_NAME_PASS +#undef _PASS_NAME_PASS_DATA +#undef __PASS_NAME_PASS_DATA +#undef _READ_OPTIMIZATION_SUMMARY +#undef __READ_OPTIMIZATION_SUMMARY +#undef _READ_SUMMARY +#undef __READ_SUMMARY +#undef _STMT_FIXUP +#undef __STMT_FIXUP +#undef _VARIABLE_TRANSFORM +#undef __VARIABLE_TRANSFORM +#undef _WRITE_OPTIMIZATION_SUMMARY +#undef __WRITE_OPTIMIZATION_SUMMARY +#undef _WRITE_SUMMARY +#undef __WRITE_SUMMARY + +#endif /* PASS_NAME */ diff --git a/src/net/scripts/gcc-plugins/gcc-generate-rtl-pass.h b/src/net/scripts/gcc-plugins/gcc-generate-rtl-pass.h new file mode 100644 index 0000000..d69cd80 --- /dev/null +++ b/src/net/scripts/gcc-plugins/gcc-generate-rtl-pass.h @@ -0,0 +1,176 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Generator for RTL pass related boilerplate code/data + * + * Supports gcc 4.5-6 + * + * Usage: + * + * 1. before inclusion define PASS_NAME + * 2. before inclusion define NO_* for unimplemented callbacks + * NO_GATE + * NO_EXECUTE + * 3. before inclusion define PROPERTIES_* and TODO_FLAGS_* to override + * the default 0 values + * 4. for convenience, all the above will be undefined after inclusion! + * 5. the only exported name is make_PASS_NAME_pass() to register with gcc + */ + +#ifndef PASS_NAME +#error at least PASS_NAME must be defined +#else +#define __GCC_PLUGIN_STRINGIFY(n) #n +#define _GCC_PLUGIN_STRINGIFY(n) __GCC_PLUGIN_STRINGIFY(n) +#define _GCC_PLUGIN_CONCAT2(x, y) x ## y +#define _GCC_PLUGIN_CONCAT3(x, y, z) x ## y ## z + +#define __PASS_NAME_PASS_DATA(n) _GCC_PLUGIN_CONCAT2(n, _pass_data) +#define _PASS_NAME_PASS_DATA __PASS_NAME_PASS_DATA(PASS_NAME) + +#define __PASS_NAME_PASS(n) _GCC_PLUGIN_CONCAT2(n, _pass) +#define _PASS_NAME_PASS __PASS_NAME_PASS(PASS_NAME) + +#define _PASS_NAME_NAME _GCC_PLUGIN_STRINGIFY(PASS_NAME) + +#define __MAKE_PASS_NAME_PASS(n) _GCC_PLUGIN_CONCAT3(make_, n, _pass) +#define _MAKE_PASS_NAME_PASS __MAKE_PASS_NAME_PASS(PASS_NAME) + +#ifdef NO_GATE +#define _GATE NULL +#define _HAS_GATE false +#else +#define __GATE(n) _GCC_PLUGIN_CONCAT2(n, _gate) +#define _GATE __GATE(PASS_NAME) +#define _HAS_GATE true +#endif + +#ifdef NO_EXECUTE +#define _EXECUTE NULL +#define _HAS_EXECUTE false +#else +#define __EXECUTE(n) _GCC_PLUGIN_CONCAT2(n, _execute) +#define _EXECUTE __EXECUTE(PASS_NAME) +#define _HAS_EXECUTE true +#endif + +#ifndef PROPERTIES_REQUIRED +#define PROPERTIES_REQUIRED 0 +#endif + +#ifndef PROPERTIES_PROVIDED +#define PROPERTIES_PROVIDED 0 +#endif + +#ifndef PROPERTIES_DESTROYED +#define PROPERTIES_DESTROYED 0 +#endif + +#ifndef TODO_FLAGS_START +#define TODO_FLAGS_START 0 +#endif + +#ifndef TODO_FLAGS_FINISH +#define TODO_FLAGS_FINISH 0 +#endif + +#if BUILDING_GCC_VERSION >= 4009 +namespace { +static const pass_data _PASS_NAME_PASS_DATA = { +#else +static struct rtl_opt_pass _PASS_NAME_PASS = { + .pass = { +#endif + .type = RTL_PASS, + .name = _PASS_NAME_NAME, +#if BUILDING_GCC_VERSION >= 4008 + .optinfo_flags = OPTGROUP_NONE, +#endif +#if BUILDING_GCC_VERSION >= 5000 +#elif BUILDING_GCC_VERSION == 4009 + .has_gate = _HAS_GATE, + .has_execute = _HAS_EXECUTE, +#else + .gate = _GATE, + .execute = _EXECUTE, + .sub = NULL, + .next = NULL, + .static_pass_number = 0, +#endif + .tv_id = TV_NONE, + .properties_required = PROPERTIES_REQUIRED, + .properties_provided = PROPERTIES_PROVIDED, + .properties_destroyed = PROPERTIES_DESTROYED, + .todo_flags_start = TODO_FLAGS_START, + .todo_flags_finish = TODO_FLAGS_FINISH, +#if BUILDING_GCC_VERSION < 4009 + } +#endif +}; + +#if BUILDING_GCC_VERSION >= 4009 +class _PASS_NAME_PASS : public rtl_opt_pass { +public: + _PASS_NAME_PASS() : rtl_opt_pass(_PASS_NAME_PASS_DATA, g) {} + +#ifndef NO_GATE +#if BUILDING_GCC_VERSION >= 5000 + virtual bool gate(function *) { return _GATE(); } +#else + virtual bool gate(void) { return _GATE(); } +#endif +#endif + + virtual opt_pass *clone() { return new _PASS_NAME_PASS(); } + +#ifndef NO_EXECUTE +#if BUILDING_GCC_VERSION >= 5000 + virtual unsigned int execute(function *) { return _EXECUTE(); } +#else + virtual unsigned int execute(void) { return _EXECUTE(); } +#endif +#endif +}; +} + +opt_pass *_MAKE_PASS_NAME_PASS(void) +{ + return new _PASS_NAME_PASS(); +} +#else +struct opt_pass *_MAKE_PASS_NAME_PASS(void) +{ + return &_PASS_NAME_PASS.pass; +} +#endif + +/* clean up user provided defines */ +#undef PASS_NAME +#undef NO_GATE +#undef NO_EXECUTE + +#undef PROPERTIES_DESTROYED +#undef PROPERTIES_PROVIDED +#undef PROPERTIES_REQUIRED +#undef TODO_FLAGS_FINISH +#undef TODO_FLAGS_START + +/* clean up generated defines */ +#undef _EXECUTE +#undef __EXECUTE +#undef _GATE +#undef __GATE +#undef _GCC_PLUGIN_CONCAT2 +#undef _GCC_PLUGIN_CONCAT3 +#undef _GCC_PLUGIN_STRINGIFY +#undef __GCC_PLUGIN_STRINGIFY +#undef _HAS_EXECUTE +#undef _HAS_GATE +#undef _MAKE_PASS_NAME_PASS +#undef __MAKE_PASS_NAME_PASS +#undef _PASS_NAME_NAME +#undef _PASS_NAME_PASS +#undef __PASS_NAME_PASS +#undef _PASS_NAME_PASS_DATA +#undef __PASS_NAME_PASS_DATA + +#endif /* PASS_NAME */ diff --git a/src/net/scripts/gcc-plugins/gcc-generate-simple_ipa-pass.h b/src/net/scripts/gcc-plugins/gcc-generate-simple_ipa-pass.h new file mode 100644 index 0000000..06800bc --- /dev/null +++ b/src/net/scripts/gcc-plugins/gcc-generate-simple_ipa-pass.h @@ -0,0 +1,176 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Generator for SIMPLE_IPA pass related boilerplate code/data + * + * Supports gcc 4.5-6 + * + * Usage: + * + * 1. before inclusion define PASS_NAME + * 2. before inclusion define NO_* for unimplemented callbacks + * NO_GATE + * NO_EXECUTE + * 3. before inclusion define PROPERTIES_* and TODO_FLAGS_* to override + * the default 0 values + * 4. for convenience, all the above will be undefined after inclusion! + * 5. the only exported name is make_PASS_NAME_pass() to register with gcc + */ + +#ifndef PASS_NAME +#error at least PASS_NAME must be defined +#else +#define __GCC_PLUGIN_STRINGIFY(n) #n +#define _GCC_PLUGIN_STRINGIFY(n) __GCC_PLUGIN_STRINGIFY(n) +#define _GCC_PLUGIN_CONCAT2(x, y) x ## y +#define _GCC_PLUGIN_CONCAT3(x, y, z) x ## y ## z + +#define __PASS_NAME_PASS_DATA(n) _GCC_PLUGIN_CONCAT2(n, _pass_data) +#define _PASS_NAME_PASS_DATA __PASS_NAME_PASS_DATA(PASS_NAME) + +#define __PASS_NAME_PASS(n) _GCC_PLUGIN_CONCAT2(n, _pass) +#define _PASS_NAME_PASS __PASS_NAME_PASS(PASS_NAME) + +#define _PASS_NAME_NAME _GCC_PLUGIN_STRINGIFY(PASS_NAME) + +#define __MAKE_PASS_NAME_PASS(n) _GCC_PLUGIN_CONCAT3(make_, n, _pass) +#define _MAKE_PASS_NAME_PASS __MAKE_PASS_NAME_PASS(PASS_NAME) + +#ifdef NO_GATE +#define _GATE NULL +#define _HAS_GATE false +#else +#define __GATE(n) _GCC_PLUGIN_CONCAT2(n, _gate) +#define _GATE __GATE(PASS_NAME) +#define _HAS_GATE true +#endif + +#ifdef NO_EXECUTE +#define _EXECUTE NULL +#define _HAS_EXECUTE false +#else +#define __EXECUTE(n) _GCC_PLUGIN_CONCAT2(n, _execute) +#define _EXECUTE __EXECUTE(PASS_NAME) +#define _HAS_EXECUTE true +#endif + +#ifndef PROPERTIES_REQUIRED +#define PROPERTIES_REQUIRED 0 +#endif + +#ifndef PROPERTIES_PROVIDED +#define PROPERTIES_PROVIDED 0 +#endif + +#ifndef PROPERTIES_DESTROYED +#define PROPERTIES_DESTROYED 0 +#endif + +#ifndef TODO_FLAGS_START +#define TODO_FLAGS_START 0 +#endif + +#ifndef TODO_FLAGS_FINISH +#define TODO_FLAGS_FINISH 0 +#endif + +#if BUILDING_GCC_VERSION >= 4009 +namespace { +static const pass_data _PASS_NAME_PASS_DATA = { +#else +static struct simple_ipa_opt_pass _PASS_NAME_PASS = { + .pass = { +#endif + .type = SIMPLE_IPA_PASS, + .name = _PASS_NAME_NAME, +#if BUILDING_GCC_VERSION >= 4008 + .optinfo_flags = OPTGROUP_NONE, +#endif +#if BUILDING_GCC_VERSION >= 5000 +#elif BUILDING_GCC_VERSION == 4009 + .has_gate = _HAS_GATE, + .has_execute = _HAS_EXECUTE, +#else + .gate = _GATE, + .execute = _EXECUTE, + .sub = NULL, + .next = NULL, + .static_pass_number = 0, +#endif + .tv_id = TV_NONE, + .properties_required = PROPERTIES_REQUIRED, + .properties_provided = PROPERTIES_PROVIDED, + .properties_destroyed = PROPERTIES_DESTROYED, + .todo_flags_start = TODO_FLAGS_START, + .todo_flags_finish = TODO_FLAGS_FINISH, +#if BUILDING_GCC_VERSION < 4009 + } +#endif +}; + +#if BUILDING_GCC_VERSION >= 4009 +class _PASS_NAME_PASS : public simple_ipa_opt_pass { +public: + _PASS_NAME_PASS() : simple_ipa_opt_pass(_PASS_NAME_PASS_DATA, g) {} + +#ifndef NO_GATE +#if BUILDING_GCC_VERSION >= 5000 + virtual bool gate(function *) { return _GATE(); } +#else + virtual bool gate(void) { return _GATE(); } +#endif +#endif + + virtual opt_pass *clone() { return new _PASS_NAME_PASS(); } + +#ifndef NO_EXECUTE +#if BUILDING_GCC_VERSION >= 5000 + virtual unsigned int execute(function *) { return _EXECUTE(); } +#else + virtual unsigned int execute(void) { return _EXECUTE(); } +#endif +#endif +}; +} + +opt_pass *_MAKE_PASS_NAME_PASS(void) +{ + return new _PASS_NAME_PASS(); +} +#else +struct opt_pass *_MAKE_PASS_NAME_PASS(void) +{ + return &_PASS_NAME_PASS.pass; +} +#endif + +/* clean up user provided defines */ +#undef PASS_NAME +#undef NO_GATE +#undef NO_EXECUTE + +#undef PROPERTIES_DESTROYED +#undef PROPERTIES_PROVIDED +#undef PROPERTIES_REQUIRED +#undef TODO_FLAGS_FINISH +#undef TODO_FLAGS_START + +/* clean up generated defines */ +#undef _EXECUTE +#undef __EXECUTE +#undef _GATE +#undef __GATE +#undef _GCC_PLUGIN_CONCAT2 +#undef _GCC_PLUGIN_CONCAT3 +#undef _GCC_PLUGIN_STRINGIFY +#undef __GCC_PLUGIN_STRINGIFY +#undef _HAS_EXECUTE +#undef _HAS_GATE +#undef _MAKE_PASS_NAME_PASS +#undef __MAKE_PASS_NAME_PASS +#undef _PASS_NAME_NAME +#undef _PASS_NAME_PASS +#undef __PASS_NAME_PASS +#undef _PASS_NAME_PASS_DATA +#undef __PASS_NAME_PASS_DATA + +#endif /* PASS_NAME */ diff --git a/src/net/scripts/gcc-plugins/gen-random-seed.sh b/src/net/scripts/gcc-plugins/gen-random-seed.sh new file mode 100644 index 0000000..68af5cc --- /dev/null +++ b/src/net/scripts/gcc-plugins/gen-random-seed.sh @@ -0,0 +1,9 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0 + +if [ ! -f "$1" ]; then + SEED=`od -A n -t x8 -N 32 /dev/urandom | tr -d ' \n'` + echo "const char *randstruct_seed = \"$SEED\";" > "$1" + HASH=`echo -n "$SEED" | sha256sum | cut -d" " -f1 | tr -d ' \n'` + echo "#define RANDSTRUCT_HASHED_SEED \"$HASH\"" > "$2" +fi diff --git a/src/net/scripts/gcc-plugins/latent_entropy_plugin.c b/src/net/scripts/gcc-plugins/latent_entropy_plugin.c new file mode 100644 index 0000000..c84bef1 --- /dev/null +++ b/src/net/scripts/gcc-plugins/latent_entropy_plugin.c @@ -0,0 +1,638 @@ +/* + * Copyright 2012-2016 by the PaX Team <pageexec@freemail.hu> + * Copyright 2016 by Emese Revfy <re.emese@gmail.com> + * Licensed under the GPL v2 + * + * Note: the choice of the license means that the compilation process is + * NOT 'eligible' as defined by gcc's library exception to the GPL v3, + * but for the kernel it doesn't matter since it doesn't link against + * any of the gcc libraries + * + * This gcc plugin helps generate a little bit of entropy from program state, + * used throughout the uptime of the kernel. Here is an instrumentation example: + * + * before: + * void __latent_entropy test(int argc, char *argv[]) + * { + * if (argc <= 1) + * printf("%s: no command arguments :(\n", *argv); + * else + * printf("%s: %d command arguments!\n", *argv, args - 1); + * } + * + * after: + * void __latent_entropy test(int argc, char *argv[]) + * { + * // latent_entropy_execute() 1. + * unsigned long local_entropy; + * // init_local_entropy() 1. + * void *local_entropy_frameaddr; + * // init_local_entropy() 3. + * unsigned long tmp_latent_entropy; + * + * // init_local_entropy() 2. + * local_entropy_frameaddr = __builtin_frame_address(0); + * local_entropy = (unsigned long) local_entropy_frameaddr; + * + * // init_local_entropy() 4. + * tmp_latent_entropy = latent_entropy; + * // init_local_entropy() 5. + * local_entropy ^= tmp_latent_entropy; + * + * // latent_entropy_execute() 3. + * if (argc <= 1) { + * // perturb_local_entropy() + * local_entropy += 4623067384293424948; + * printf("%s: no command arguments :(\n", *argv); + * // perturb_local_entropy() + * } else { + * local_entropy ^= 3896280633962944730; + * printf("%s: %d command arguments!\n", *argv, args - 1); + * } + * + * // latent_entropy_execute() 4. + * tmp_latent_entropy = rol(tmp_latent_entropy, local_entropy); + * latent_entropy = tmp_latent_entropy; + * } + * + * TODO: + * - add ipa pass to identify not explicitly marked candidate functions + * - mix in more program state (function arguments/return values, + * loop variables, etc) + * - more instrumentation control via attribute parameters + * + * BUGS: + * - none known + * + * Options: + * -fplugin-arg-latent_entropy_plugin-disable + * + * Attribute: __attribute__((latent_entropy)) + * The latent_entropy gcc attribute can be only on functions and variables. + * If it is on a function then the plugin will instrument it. If the attribute + * is on a variable then the plugin will initialize it with a random value. + * The variable must be an integer, an integer array type or a structure + * with integer fields. + */ + +#include "gcc-common.h" + +__visible int plugin_is_GPL_compatible; + +static GTY(()) tree latent_entropy_decl; + +static struct plugin_info latent_entropy_plugin_info = { + .version = "201606141920vanilla", + .help = "disable\tturn off latent entropy instrumentation\n", +}; + +static unsigned HOST_WIDE_INT deterministic_seed; +static unsigned HOST_WIDE_INT rnd_buf[32]; +static size_t rnd_idx = ARRAY_SIZE(rnd_buf); +static int urandom_fd = -1; + +static unsigned HOST_WIDE_INT get_random_const(void) +{ + if (deterministic_seed) { + unsigned HOST_WIDE_INT w = deterministic_seed; + w ^= w << 13; + w ^= w >> 7; + w ^= w << 17; + deterministic_seed = w; + return deterministic_seed; + } + + if (urandom_fd < 0) { + urandom_fd = open("/dev/urandom", O_RDONLY); + gcc_assert(urandom_fd >= 0); + } + if (rnd_idx >= ARRAY_SIZE(rnd_buf)) { + gcc_assert(read(urandom_fd, rnd_buf, sizeof(rnd_buf)) == sizeof(rnd_buf)); + rnd_idx = 0; + } + return rnd_buf[rnd_idx++]; +} + +static tree tree_get_random_const(tree type) +{ + unsigned long long mask; + + mask = 1ULL << (TREE_INT_CST_LOW(TYPE_SIZE(type)) - 1); + mask = 2 * (mask - 1) + 1; + + if (TYPE_UNSIGNED(type)) + return build_int_cstu(type, mask & get_random_const()); + return build_int_cst(type, mask & get_random_const()); +} + +static tree handle_latent_entropy_attribute(tree *node, tree name, + tree args __unused, + int flags __unused, + bool *no_add_attrs) +{ + tree type; +#if BUILDING_GCC_VERSION <= 4007 + VEC(constructor_elt, gc) *vals; +#else + vec<constructor_elt, va_gc> *vals; +#endif + + switch (TREE_CODE(*node)) { + default: + *no_add_attrs = true; + error("%qE attribute only applies to functions and variables", + name); + break; + + case VAR_DECL: + if (DECL_INITIAL(*node)) { + *no_add_attrs = true; + error("variable %qD with %qE attribute must not be initialized", + *node, name); + break; + } + + if (!TREE_STATIC(*node)) { + *no_add_attrs = true; + error("variable %qD with %qE attribute must not be local", + *node, name); + break; + } + + type = TREE_TYPE(*node); + switch (TREE_CODE(type)) { + default: + *no_add_attrs = true; + error("variable %qD with %qE attribute must be an integer or a fixed length integer array type or a fixed sized structure with integer fields", + *node, name); + break; + + case RECORD_TYPE: { + tree fld, lst = TYPE_FIELDS(type); + unsigned int nelt = 0; + + for (fld = lst; fld; nelt++, fld = TREE_CHAIN(fld)) { + tree fieldtype; + + fieldtype = TREE_TYPE(fld); + if (TREE_CODE(fieldtype) == INTEGER_TYPE) + continue; + + *no_add_attrs = true; + error("structure variable %qD with %qE attribute has a non-integer field %qE", + *node, name, fld); + break; + } + + if (fld) + break; + +#if BUILDING_GCC_VERSION <= 4007 + vals = VEC_alloc(constructor_elt, gc, nelt); +#else + vec_alloc(vals, nelt); +#endif + + for (fld = lst; fld; fld = TREE_CHAIN(fld)) { + tree random_const, fld_t = TREE_TYPE(fld); + + random_const = tree_get_random_const(fld_t); + CONSTRUCTOR_APPEND_ELT(vals, fld, random_const); + } + + /* Initialize the fields with random constants */ + DECL_INITIAL(*node) = build_constructor(type, vals); + break; + } + + /* Initialize the variable with a random constant */ + case INTEGER_TYPE: + DECL_INITIAL(*node) = tree_get_random_const(type); + break; + + case ARRAY_TYPE: { + tree elt_type, array_size, elt_size; + unsigned int i, nelt; + HOST_WIDE_INT array_size_int, elt_size_int; + + elt_type = TREE_TYPE(type); + elt_size = TYPE_SIZE_UNIT(TREE_TYPE(type)); + array_size = TYPE_SIZE_UNIT(type); + + if (TREE_CODE(elt_type) != INTEGER_TYPE || !array_size + || TREE_CODE(array_size) != INTEGER_CST) { + *no_add_attrs = true; + error("array variable %qD with %qE attribute must be a fixed length integer array type", + *node, name); + break; + } + + array_size_int = TREE_INT_CST_LOW(array_size); + elt_size_int = TREE_INT_CST_LOW(elt_size); + nelt = array_size_int / elt_size_int; + +#if BUILDING_GCC_VERSION <= 4007 + vals = VEC_alloc(constructor_elt, gc, nelt); +#else + vec_alloc(vals, nelt); +#endif + + for (i = 0; i < nelt; i++) { + tree cst = size_int(i); + tree rand_cst = tree_get_random_const(elt_type); + + CONSTRUCTOR_APPEND_ELT(vals, cst, rand_cst); + } + + /* + * Initialize the elements of the array with random + * constants + */ + DECL_INITIAL(*node) = build_constructor(type, vals); + break; + } + } + break; + + case FUNCTION_DECL: + break; + } + + return NULL_TREE; +} + +static struct attribute_spec latent_entropy_attr = { }; + +static void register_attributes(void *event_data __unused, void *data __unused) +{ + latent_entropy_attr.name = "latent_entropy"; + latent_entropy_attr.decl_required = true; + latent_entropy_attr.handler = handle_latent_entropy_attribute; + + register_attribute(&latent_entropy_attr); +} + +static bool latent_entropy_gate(void) +{ + tree list; + + /* don't bother with noreturn functions for now */ + if (TREE_THIS_VOLATILE(current_function_decl)) + return false; + + /* gcc-4.5 doesn't discover some trivial noreturn functions */ + if (EDGE_COUNT(EXIT_BLOCK_PTR_FOR_FN(cfun)->preds) == 0) + return false; + + list = DECL_ATTRIBUTES(current_function_decl); + return lookup_attribute("latent_entropy", list) != NULL_TREE; +} + +static tree create_var(tree type, const char *name) +{ + tree var; + + var = create_tmp_var(type, name); + add_referenced_var(var); + mark_sym_for_renaming(var); + return var; +} + +/* + * Set up the next operation and its constant operand to use in the latent + * entropy PRNG. When RHS is specified, the request is for perturbing the + * local latent entropy variable, otherwise it is for perturbing the global + * latent entropy variable where the two operands are already given by the + * local and global latent entropy variables themselves. + * + * The operation is one of add/xor/rol when instrumenting the local entropy + * variable and one of add/xor when perturbing the global entropy variable. + * Rotation is not used for the latter case because it would transmit less + * entropy to the global variable than the other two operations. + */ +static enum tree_code get_op(tree *rhs) +{ + static enum tree_code op; + unsigned HOST_WIDE_INT random_const; + + random_const = get_random_const(); + + switch (op) { + case BIT_XOR_EXPR: + op = PLUS_EXPR; + break; + + case PLUS_EXPR: + if (rhs) { + op = LROTATE_EXPR; + /* + * This code limits the value of random_const to + * the size of a long for the rotation + */ + random_const %= TYPE_PRECISION(long_unsigned_type_node); + break; + } + + case LROTATE_EXPR: + default: + op = BIT_XOR_EXPR; + break; + } + if (rhs) + *rhs = build_int_cstu(long_unsigned_type_node, random_const); + return op; +} + +static gimple create_assign(enum tree_code code, tree lhs, tree op1, + tree op2) +{ + return gimple_build_assign_with_ops(code, lhs, op1, op2); +} + +static void perturb_local_entropy(basic_block bb, tree local_entropy) +{ + gimple_stmt_iterator gsi; + gimple assign; + tree rhs; + enum tree_code op; + + op = get_op(&rhs); + assign = create_assign(op, local_entropy, local_entropy, rhs); + gsi = gsi_after_labels(bb); + gsi_insert_before(&gsi, assign, GSI_NEW_STMT); + update_stmt(assign); +} + +static void __perturb_latent_entropy(gimple_stmt_iterator *gsi, + tree local_entropy) +{ + gimple assign; + tree temp; + enum tree_code op; + + /* 1. create temporary copy of latent_entropy */ + temp = create_var(long_unsigned_type_node, "temp_latent_entropy"); + + /* 2. read... */ + add_referenced_var(latent_entropy_decl); + mark_sym_for_renaming(latent_entropy_decl); + assign = gimple_build_assign(temp, latent_entropy_decl); + gsi_insert_before(gsi, assign, GSI_NEW_STMT); + update_stmt(assign); + + /* 3. ...modify... */ + op = get_op(NULL); + assign = create_assign(op, temp, temp, local_entropy); + gsi_insert_after(gsi, assign, GSI_NEW_STMT); + update_stmt(assign); + + /* 4. ...write latent_entropy */ + assign = gimple_build_assign(latent_entropy_decl, temp); + gsi_insert_after(gsi, assign, GSI_NEW_STMT); + update_stmt(assign); +} + +static bool handle_tail_calls(basic_block bb, tree local_entropy) +{ + gimple_stmt_iterator gsi; + + for (gsi = gsi_start_bb(bb); !gsi_end_p(gsi); gsi_next(&gsi)) { + gcall *call; + gimple stmt = gsi_stmt(gsi); + + if (!is_gimple_call(stmt)) + continue; + + call = as_a_gcall(stmt); + if (!gimple_call_tail_p(call)) + continue; + + __perturb_latent_entropy(&gsi, local_entropy); + return true; + } + + return false; +} + +static void perturb_latent_entropy(tree local_entropy) +{ + edge_iterator ei; + edge e, last_bb_e; + basic_block last_bb; + + gcc_assert(single_pred_p(EXIT_BLOCK_PTR_FOR_FN(cfun))); + last_bb_e = single_pred_edge(EXIT_BLOCK_PTR_FOR_FN(cfun)); + + FOR_EACH_EDGE(e, ei, last_bb_e->src->preds) { + if (ENTRY_BLOCK_PTR_FOR_FN(cfun) == e->src) + continue; + if (EXIT_BLOCK_PTR_FOR_FN(cfun) == e->src) + continue; + + handle_tail_calls(e->src, local_entropy); + } + + last_bb = single_pred(EXIT_BLOCK_PTR_FOR_FN(cfun)); + if (!handle_tail_calls(last_bb, local_entropy)) { + gimple_stmt_iterator gsi = gsi_last_bb(last_bb); + + __perturb_latent_entropy(&gsi, local_entropy); + } +} + +static void init_local_entropy(basic_block bb, tree local_entropy) +{ + gimple assign, call; + tree frame_addr, rand_const, tmp, fndecl, udi_frame_addr; + enum tree_code op; + unsigned HOST_WIDE_INT rand_cst; + gimple_stmt_iterator gsi = gsi_after_labels(bb); + + /* 1. create local_entropy_frameaddr */ + frame_addr = create_var(ptr_type_node, "local_entropy_frameaddr"); + + /* 2. local_entropy_frameaddr = __builtin_frame_address() */ + fndecl = builtin_decl_implicit(BUILT_IN_FRAME_ADDRESS); + call = gimple_build_call(fndecl, 1, integer_zero_node); + gimple_call_set_lhs(call, frame_addr); + gsi_insert_before(&gsi, call, GSI_NEW_STMT); + update_stmt(call); + + udi_frame_addr = fold_convert(long_unsigned_type_node, frame_addr); + assign = gimple_build_assign(local_entropy, udi_frame_addr); + gsi_insert_after(&gsi, assign, GSI_NEW_STMT); + update_stmt(assign); + + /* 3. create temporary copy of latent_entropy */ + tmp = create_var(long_unsigned_type_node, "temp_latent_entropy"); + + /* 4. read the global entropy variable into local entropy */ + add_referenced_var(latent_entropy_decl); + mark_sym_for_renaming(latent_entropy_decl); + assign = gimple_build_assign(tmp, latent_entropy_decl); + gsi_insert_after(&gsi, assign, GSI_NEW_STMT); + update_stmt(assign); + + /* 5. mix local_entropy_frameaddr into local entropy */ + assign = create_assign(BIT_XOR_EXPR, local_entropy, local_entropy, tmp); + gsi_insert_after(&gsi, assign, GSI_NEW_STMT); + update_stmt(assign); + + rand_cst = get_random_const(); + rand_const = build_int_cstu(long_unsigned_type_node, rand_cst); + op = get_op(NULL); + assign = create_assign(op, local_entropy, local_entropy, rand_const); + gsi_insert_after(&gsi, assign, GSI_NEW_STMT); + update_stmt(assign); +} + +static bool create_latent_entropy_decl(void) +{ + varpool_node_ptr node; + + if (latent_entropy_decl != NULL_TREE) + return true; + + FOR_EACH_VARIABLE(node) { + tree name, var = NODE_DECL(node); + + if (DECL_NAME_LENGTH(var) < sizeof("latent_entropy") - 1) + continue; + + name = DECL_NAME(var); + if (strcmp(IDENTIFIER_POINTER(name), "latent_entropy")) + continue; + + latent_entropy_decl = var; + break; + } + + return latent_entropy_decl != NULL_TREE; +} + +static unsigned int latent_entropy_execute(void) +{ + basic_block bb; + tree local_entropy; + + if (!create_latent_entropy_decl()) + return 0; + + /* prepare for step 2 below */ + gcc_assert(single_succ_p(ENTRY_BLOCK_PTR_FOR_FN(cfun))); + bb = single_succ(ENTRY_BLOCK_PTR_FOR_FN(cfun)); + if (!single_pred_p(bb)) { + split_edge(single_succ_edge(ENTRY_BLOCK_PTR_FOR_FN(cfun))); + gcc_assert(single_succ_p(ENTRY_BLOCK_PTR_FOR_FN(cfun))); + bb = single_succ(ENTRY_BLOCK_PTR_FOR_FN(cfun)); + } + + /* 1. create the local entropy variable */ + local_entropy = create_var(long_unsigned_type_node, "local_entropy"); + + /* 2. initialize the local entropy variable */ + init_local_entropy(bb, local_entropy); + + bb = bb->next_bb; + + /* + * 3. instrument each BB with an operation on the + * local entropy variable + */ + while (bb != EXIT_BLOCK_PTR_FOR_FN(cfun)) { + perturb_local_entropy(bb, local_entropy); + bb = bb->next_bb; + }; + + /* 4. mix local entropy into the global entropy variable */ + perturb_latent_entropy(local_entropy); + return 0; +} + +static void latent_entropy_start_unit(void *gcc_data __unused, + void *user_data __unused) +{ + tree type, id; + int quals; + + if (in_lto_p) + return; + + /* extern volatile unsigned long latent_entropy */ + quals = TYPE_QUALS(long_unsigned_type_node) | TYPE_QUAL_VOLATILE; + type = build_qualified_type(long_unsigned_type_node, quals); + id = get_identifier("latent_entropy"); + latent_entropy_decl = build_decl(UNKNOWN_LOCATION, VAR_DECL, id, type); + + TREE_STATIC(latent_entropy_decl) = 1; + TREE_PUBLIC(latent_entropy_decl) = 1; + TREE_USED(latent_entropy_decl) = 1; + DECL_PRESERVE_P(latent_entropy_decl) = 1; + TREE_THIS_VOLATILE(latent_entropy_decl) = 1; + DECL_EXTERNAL(latent_entropy_decl) = 1; + DECL_ARTIFICIAL(latent_entropy_decl) = 1; + lang_hooks.decls.pushdecl(latent_entropy_decl); +} + +#define PASS_NAME latent_entropy +#define PROPERTIES_REQUIRED PROP_gimple_leh | PROP_cfg +#define TODO_FLAGS_FINISH TODO_verify_ssa | TODO_verify_stmts | TODO_dump_func \ + | TODO_update_ssa +#include "gcc-generate-gimple-pass.h" + +__visible int plugin_init(struct plugin_name_args *plugin_info, + struct plugin_gcc_version *version) +{ + bool enabled = true; + const char * const plugin_name = plugin_info->base_name; + const int argc = plugin_info->argc; + const struct plugin_argument * const argv = plugin_info->argv; + int i; + + /* + * Call get_random_seed() with noinit=true, so that this returns + * 0 in the case where no seed has been passed via -frandom-seed. + */ + deterministic_seed = get_random_seed(true); + + static const struct ggc_root_tab gt_ggc_r_gt_latent_entropy[] = { + { + .base = &latent_entropy_decl, + .nelt = 1, + .stride = sizeof(latent_entropy_decl), + .cb = >_ggc_mx_tree_node, + .pchw = >_pch_nx_tree_node + }, + LAST_GGC_ROOT_TAB + }; + + PASS_INFO(latent_entropy, "optimized", 1, PASS_POS_INSERT_BEFORE); + + if (!plugin_default_version_check(version, &gcc_version)) { + error(G_("incompatible gcc/plugin versions")); + return 1; + } + + for (i = 0; i < argc; ++i) { + if (!(strcmp(argv[i].key, "disable"))) { + enabled = false; + continue; + } + error(G_("unknown option '-fplugin-arg-%s-%s'"), plugin_name, argv[i].key); + } + + register_callback(plugin_name, PLUGIN_INFO, NULL, + &latent_entropy_plugin_info); + if (enabled) { + register_callback(plugin_name, PLUGIN_START_UNIT, + &latent_entropy_start_unit, NULL); + register_callback(plugin_name, PLUGIN_REGISTER_GGC_ROOTS, + NULL, (void *)>_ggc_r_gt_latent_entropy); + register_callback(plugin_name, PLUGIN_PASS_MANAGER_SETUP, NULL, + &latent_entropy_pass_info); + } + register_callback(plugin_name, PLUGIN_ATTRIBUTES, register_attributes, + NULL); + + return 0; +} diff --git a/src/net/scripts/gcc-plugins/randomize_layout_plugin.c b/src/net/scripts/gcc-plugins/randomize_layout_plugin.c new file mode 100644 index 0000000..bd29e4e --- /dev/null +++ b/src/net/scripts/gcc-plugins/randomize_layout_plugin.c @@ -0,0 +1,992 @@ +/* + * Copyright 2014-2016 by Open Source Security, Inc., Brad Spengler <spender@grsecurity.net> + * and PaX Team <pageexec@freemail.hu> + * Licensed under the GPL v2 + * + * Note: the choice of the license means that the compilation process is + * NOT 'eligible' as defined by gcc's library exception to the GPL v3, + * but for the kernel it doesn't matter since it doesn't link against + * any of the gcc libraries + * + * Usage: + * $ # for 4.5/4.6/C based 4.7 + * $ gcc -I`gcc -print-file-name=plugin`/include -I`gcc -print-file-name=plugin`/include/c-family -fPIC -shared -O2 -o randomize_layout_plugin.so randomize_layout_plugin.c + * $ # for C++ based 4.7/4.8+ + * $ g++ -I`g++ -print-file-name=plugin`/include -I`g++ -print-file-name=plugin`/include/c-family -fPIC -shared -O2 -o randomize_layout_plugin.so randomize_layout_plugin.c + * $ gcc -fplugin=./randomize_layout_plugin.so test.c -O2 + */ + +#include "gcc-common.h" +#include "randomize_layout_seed.h" + +#if BUILDING_GCC_MAJOR < 4 || (BUILDING_GCC_MAJOR == 4 && BUILDING_GCC_MINOR < 7) +#error "The RANDSTRUCT plugin requires GCC 4.7 or newer." +#endif + +#define ORIG_TYPE_NAME(node) \ + (TYPE_NAME(TYPE_MAIN_VARIANT(node)) != NULL_TREE ? ((const unsigned char *)IDENTIFIER_POINTER(TYPE_NAME(TYPE_MAIN_VARIANT(node)))) : (const unsigned char *)"anonymous") + +#define INFORM(loc, msg, ...) inform(loc, "randstruct: " msg, ##__VA_ARGS__) +#define MISMATCH(loc, how, ...) INFORM(loc, "casting between randomized structure pointer types (" how "): %qT and %qT\n", __VA_ARGS__) + +__visible int plugin_is_GPL_compatible; + +static int performance_mode; + +static struct plugin_info randomize_layout_plugin_info = { + .version = "201402201816vanilla", + .help = "disable\t\t\tdo not activate plugin\n" + "performance-mode\tenable cacheline-aware layout randomization\n" +}; + +struct whitelist_entry { + const char *pathname; + const char *lhs; + const char *rhs; +}; + +static const struct whitelist_entry whitelist[] = { + /* NIU overloads mapping with page struct */ + { "drivers/net/ethernet/sun/niu.c", "page", "address_space" }, + /* unix_skb_parms via UNIXCB() buffer */ + { "net/unix/af_unix.c", "unix_skb_parms", "char" }, + /* big_key payload.data struct splashing */ + { "security/keys/big_key.c", "path", "void *" }, + /* walk struct security_hook_heads as an array of struct hlist_head */ + { "security/security.c", "hlist_head", "security_hook_heads" }, + { } +}; + +/* from old Linux dcache.h */ +static inline unsigned long +partial_name_hash(unsigned long c, unsigned long prevhash) +{ + return (prevhash + (c << 4) + (c >> 4)) * 11; +} +static inline unsigned int +name_hash(const unsigned char *name) +{ + unsigned long hash = 0; + unsigned int len = strlen((const char *)name); + while (len--) + hash = partial_name_hash(*name++, hash); + return (unsigned int)hash; +} + +static tree handle_randomize_layout_attr(tree *node, tree name, tree args, int flags, bool *no_add_attrs) +{ + tree type; + + *no_add_attrs = true; + if (TREE_CODE(*node) == FUNCTION_DECL) { + error("%qE attribute does not apply to functions (%qF)", name, *node); + return NULL_TREE; + } + + if (TREE_CODE(*node) == PARM_DECL) { + error("%qE attribute does not apply to function parameters (%qD)", name, *node); + return NULL_TREE; + } + + if (TREE_CODE(*node) == VAR_DECL) { + error("%qE attribute does not apply to variables (%qD)", name, *node); + return NULL_TREE; + } + + if (TYPE_P(*node)) { + type = *node; + } else { + gcc_assert(TREE_CODE(*node) == TYPE_DECL); + type = TREE_TYPE(*node); + } + + if (TREE_CODE(type) != RECORD_TYPE) { + error("%qE attribute used on %qT applies to struct types only", name, type); + return NULL_TREE; + } + + if (lookup_attribute(IDENTIFIER_POINTER(name), TYPE_ATTRIBUTES(type))) { + error("%qE attribute is already applied to the type %qT", name, type); + return NULL_TREE; + } + + *no_add_attrs = false; + + return NULL_TREE; +} + +/* set on complete types that we don't need to inspect further at all */ +static tree handle_randomize_considered_attr(tree *node, tree name, tree args, int flags, bool *no_add_attrs) +{ + *no_add_attrs = false; + return NULL_TREE; +} + +/* + * set on types that we've performed a shuffle on, to prevent re-shuffling + * this does not preclude us from inspecting its fields for potential shuffles + */ +static tree handle_randomize_performed_attr(tree *node, tree name, tree args, int flags, bool *no_add_attrs) +{ + *no_add_attrs = false; + return NULL_TREE; +} + +/* + * 64bit variant of Bob Jenkins' public domain PRNG + * 256 bits of internal state + */ + +typedef unsigned long long u64; + +typedef struct ranctx { u64 a; u64 b; u64 c; u64 d; } ranctx; + +#define rot(x,k) (((x)<<(k))|((x)>>(64-(k)))) +static u64 ranval(ranctx *x) { + u64 e = x->a - rot(x->b, 7); + x->a = x->b ^ rot(x->c, 13); + x->b = x->c + rot(x->d, 37); + x->c = x->d + e; + x->d = e + x->a; + return x->d; +} + +static void raninit(ranctx *x, u64 *seed) { + int i; + + x->a = seed[0]; + x->b = seed[1]; + x->c = seed[2]; + x->d = seed[3]; + + for (i=0; i < 30; ++i) + (void)ranval(x); +} + +static u64 shuffle_seed[4]; + +struct partition_group { + tree tree_start; + unsigned long start; + unsigned long length; +}; + +static void partition_struct(tree *fields, unsigned long length, struct partition_group *size_groups, unsigned long *num_groups) +{ + unsigned long i; + unsigned long accum_size = 0; + unsigned long accum_length = 0; + unsigned long group_idx = 0; + + gcc_assert(length < INT_MAX); + + memset(size_groups, 0, sizeof(struct partition_group) * length); + + for (i = 0; i < length; i++) { + if (size_groups[group_idx].tree_start == NULL_TREE) { + size_groups[group_idx].tree_start = fields[i]; + size_groups[group_idx].start = i; + accum_length = 0; + accum_size = 0; + } + accum_size += (unsigned long)int_size_in_bytes(TREE_TYPE(fields[i])); + accum_length++; + if (accum_size >= 64) { + size_groups[group_idx].length = accum_length; + accum_length = 0; + group_idx++; + } + } + + if (size_groups[group_idx].tree_start != NULL_TREE && + !size_groups[group_idx].length) { + size_groups[group_idx].length = accum_length; + group_idx++; + } + + *num_groups = group_idx; +} + +static void performance_shuffle(tree *newtree, unsigned long length, ranctx *prng_state) +{ + unsigned long i, x; + struct partition_group size_group[length]; + unsigned long num_groups = 0; + unsigned long randnum; + + partition_struct(newtree, length, (struct partition_group *)&size_group, &num_groups); + for (i = num_groups - 1; i > 0; i--) { + struct partition_group tmp; + randnum = ranval(prng_state) % (i + 1); + tmp = size_group[i]; + size_group[i] = size_group[randnum]; + size_group[randnum] = tmp; + } + + for (x = 0; x < num_groups; x++) { + for (i = size_group[x].start + size_group[x].length - 1; i > size_group[x].start; i--) { + tree tmp; + if (DECL_BIT_FIELD_TYPE(newtree[i])) + continue; + randnum = ranval(prng_state) % (i + 1); + // we could handle this case differently if desired + if (DECL_BIT_FIELD_TYPE(newtree[randnum])) + continue; + tmp = newtree[i]; + newtree[i] = newtree[randnum]; + newtree[randnum] = tmp; + } + } +} + +static void full_shuffle(tree *newtree, unsigned long length, ranctx *prng_state) +{ + unsigned long i, randnum; + + for (i = length - 1; i > 0; i--) { + tree tmp; + randnum = ranval(prng_state) % (i + 1); + tmp = newtree[i]; + newtree[i] = newtree[randnum]; + newtree[randnum] = tmp; + } +} + +/* modern in-place Fisher-Yates shuffle */ +static void shuffle(const_tree type, tree *newtree, unsigned long length) +{ + unsigned long i; + u64 seed[4]; + ranctx prng_state; + const unsigned char *structname; + + if (length == 0) + return; + + gcc_assert(TREE_CODE(type) == RECORD_TYPE); + + structname = ORIG_TYPE_NAME(type); + +#ifdef __DEBUG_PLUGIN + fprintf(stderr, "Shuffling struct %s %p\n", (const char *)structname, type); +#ifdef __DEBUG_VERBOSE + debug_tree((tree)type); +#endif +#endif + + for (i = 0; i < 4; i++) { + seed[i] = shuffle_seed[i]; + seed[i] ^= name_hash(structname); + } + + raninit(&prng_state, (u64 *)&seed); + + if (performance_mode) + performance_shuffle(newtree, length, &prng_state); + else + full_shuffle(newtree, length, &prng_state); +} + +static bool is_flexible_array(const_tree field) +{ + const_tree fieldtype; + const_tree typesize; + const_tree elemtype; + const_tree elemsize; + + fieldtype = TREE_TYPE(field); + typesize = TYPE_SIZE(fieldtype); + + if (TREE_CODE(fieldtype) != ARRAY_TYPE) + return false; + + elemtype = TREE_TYPE(fieldtype); + elemsize = TYPE_SIZE(elemtype); + + /* size of type is represented in bits */ + + if (typesize == NULL_TREE && TYPE_DOMAIN(fieldtype) != NULL_TREE && + TYPE_MAX_VALUE(TYPE_DOMAIN(fieldtype)) == NULL_TREE) + return true; + + if (typesize != NULL_TREE && + (TREE_CONSTANT(typesize) && (!tree_to_uhwi(typesize) || + tree_to_uhwi(typesize) == tree_to_uhwi(elemsize)))) + return true; + + return false; +} + +static int relayout_struct(tree type) +{ + unsigned long num_fields = (unsigned long)list_length(TYPE_FIELDS(type)); + unsigned long shuffle_length = num_fields; + tree field; + tree newtree[num_fields]; + unsigned long i; + tree list; + tree variant; + tree main_variant; + expanded_location xloc; + bool has_flexarray = false; + + if (TYPE_FIELDS(type) == NULL_TREE) + return 0; + + if (num_fields < 2) + return 0; + + gcc_assert(TREE_CODE(type) == RECORD_TYPE); + + gcc_assert(num_fields < INT_MAX); + + if (lookup_attribute("randomize_performed", TYPE_ATTRIBUTES(type)) || + lookup_attribute("no_randomize_layout", TYPE_ATTRIBUTES(TYPE_MAIN_VARIANT(type)))) + return 0; + + /* Workaround for 3rd-party VirtualBox source that we can't modify ourselves */ + if (!strcmp((const char *)ORIG_TYPE_NAME(type), "INTNETTRUNKFACTORY") || + !strcmp((const char *)ORIG_TYPE_NAME(type), "RAWPCIFACTORY")) + return 0; + + /* throw out any structs in uapi */ + xloc = expand_location(DECL_SOURCE_LOCATION(TYPE_FIELDS(type))); + + if (strstr(xloc.file, "/uapi/")) + error(G_("attempted to randomize userland API struct %s"), ORIG_TYPE_NAME(type)); + + for (field = TYPE_FIELDS(type), i = 0; field; field = TREE_CHAIN(field), i++) { + gcc_assert(TREE_CODE(field) == FIELD_DECL); + newtree[i] = field; + } + + /* + * enforce that we don't randomize the layout of the last + * element of a struct if it's a 0 or 1-length array + * or a proper flexible array + */ + if (is_flexible_array(newtree[num_fields - 1])) { + has_flexarray = true; + shuffle_length--; + } + + shuffle(type, (tree *)newtree, shuffle_length); + + /* + * set up a bogus anonymous struct field designed to error out on unnamed struct initializers + * as gcc provides no other way to detect such code + */ + list = make_node(FIELD_DECL); + TREE_CHAIN(list) = newtree[0]; + TREE_TYPE(list) = void_type_node; + DECL_SIZE(list) = bitsize_zero_node; + DECL_NONADDRESSABLE_P(list) = 1; + DECL_FIELD_BIT_OFFSET(list) = bitsize_zero_node; + DECL_SIZE_UNIT(list) = size_zero_node; + DECL_FIELD_OFFSET(list) = size_zero_node; + DECL_CONTEXT(list) = type; + // to satisfy the constify plugin + TREE_READONLY(list) = 1; + + for (i = 0; i < num_fields - 1; i++) + TREE_CHAIN(newtree[i]) = newtree[i+1]; + TREE_CHAIN(newtree[num_fields - 1]) = NULL_TREE; + + main_variant = TYPE_MAIN_VARIANT(type); + for (variant = main_variant; variant; variant = TYPE_NEXT_VARIANT(variant)) { + TYPE_FIELDS(variant) = list; + TYPE_ATTRIBUTES(variant) = copy_list(TYPE_ATTRIBUTES(variant)); + TYPE_ATTRIBUTES(variant) = tree_cons(get_identifier("randomize_performed"), NULL_TREE, TYPE_ATTRIBUTES(variant)); + TYPE_ATTRIBUTES(variant) = tree_cons(get_identifier("designated_init"), NULL_TREE, TYPE_ATTRIBUTES(variant)); + if (has_flexarray) + TYPE_ATTRIBUTES(type) = tree_cons(get_identifier("has_flexarray"), NULL_TREE, TYPE_ATTRIBUTES(type)); + } + + /* + * force a re-layout of the main variant + * the TYPE_SIZE for all variants will be recomputed + * by finalize_type_size() + */ + TYPE_SIZE(main_variant) = NULL_TREE; + layout_type(main_variant); + gcc_assert(TYPE_SIZE(main_variant) != NULL_TREE); + + return 1; +} + +/* from constify plugin */ +static const_tree get_field_type(const_tree field) +{ + return strip_array_types(TREE_TYPE(field)); +} + +/* from constify plugin */ +static bool is_fptr(const_tree fieldtype) +{ + if (TREE_CODE(fieldtype) != POINTER_TYPE) + return false; + + return TREE_CODE(TREE_TYPE(fieldtype)) == FUNCTION_TYPE; +} + +/* derived from constify plugin */ +static int is_pure_ops_struct(const_tree node) +{ + const_tree field; + + gcc_assert(TREE_CODE(node) == RECORD_TYPE || TREE_CODE(node) == UNION_TYPE); + + for (field = TYPE_FIELDS(node); field; field = TREE_CHAIN(field)) { + const_tree fieldtype = get_field_type(field); + enum tree_code code = TREE_CODE(fieldtype); + + if (node == fieldtype) + continue; + + if (code == RECORD_TYPE || code == UNION_TYPE) { + if (!is_pure_ops_struct(fieldtype)) + return 0; + continue; + } + + if (!is_fptr(fieldtype)) + return 0; + } + + return 1; +} + +static void randomize_type(tree type) +{ + tree variant; + + gcc_assert(TREE_CODE(type) == RECORD_TYPE); + + if (lookup_attribute("randomize_considered", TYPE_ATTRIBUTES(type))) + return; + + if (lookup_attribute("randomize_layout", TYPE_ATTRIBUTES(TYPE_MAIN_VARIANT(type))) || is_pure_ops_struct(type)) + relayout_struct(type); + + for (variant = TYPE_MAIN_VARIANT(type); variant; variant = TYPE_NEXT_VARIANT(variant)) { + TYPE_ATTRIBUTES(type) = copy_list(TYPE_ATTRIBUTES(type)); + TYPE_ATTRIBUTES(type) = tree_cons(get_identifier("randomize_considered"), NULL_TREE, TYPE_ATTRIBUTES(type)); + } +#ifdef __DEBUG_PLUGIN + fprintf(stderr, "Marking randomize_considered on struct %s\n", ORIG_TYPE_NAME(type)); +#ifdef __DEBUG_VERBOSE + debug_tree(type); +#endif +#endif +} + +static void update_decl_size(tree decl) +{ + tree lastval, lastidx, field, init, type, flexsize; + unsigned HOST_WIDE_INT len; + + type = TREE_TYPE(decl); + + if (!lookup_attribute("has_flexarray", TYPE_ATTRIBUTES(type))) + return; + + init = DECL_INITIAL(decl); + if (init == NULL_TREE || init == error_mark_node) + return; + + if (TREE_CODE(init) != CONSTRUCTOR) + return; + + len = CONSTRUCTOR_NELTS(init); + if (!len) + return; + + lastval = CONSTRUCTOR_ELT(init, CONSTRUCTOR_NELTS(init) - 1)->value; + lastidx = CONSTRUCTOR_ELT(init, CONSTRUCTOR_NELTS(init) - 1)->index; + + for (field = TYPE_FIELDS(TREE_TYPE(decl)); TREE_CHAIN(field); field = TREE_CHAIN(field)) + ; + + if (lastidx != field) + return; + + if (TREE_CODE(lastval) != STRING_CST) { + error("Only string constants are supported as initializers " + "for randomized structures with flexible arrays"); + return; + } + + flexsize = bitsize_int(TREE_STRING_LENGTH(lastval) * + tree_to_uhwi(TYPE_SIZE(TREE_TYPE(TREE_TYPE(lastval))))); + + DECL_SIZE(decl) = size_binop(PLUS_EXPR, TYPE_SIZE(type), flexsize); + + return; +} + + +static void randomize_layout_finish_decl(void *event_data, void *data) +{ + tree decl = (tree)event_data; + tree type; + + if (decl == NULL_TREE || decl == error_mark_node) + return; + + type = TREE_TYPE(decl); + + if (TREE_CODE(decl) != VAR_DECL) + return; + + if (TREE_CODE(type) != RECORD_TYPE && TREE_CODE(type) != UNION_TYPE) + return; + + if (!lookup_attribute("randomize_performed", TYPE_ATTRIBUTES(type))) + return; + + DECL_SIZE(decl) = 0; + DECL_SIZE_UNIT(decl) = 0; + SET_DECL_ALIGN(decl, 0); + SET_DECL_MODE (decl, VOIDmode); + SET_DECL_RTL(decl, 0); + update_decl_size(decl); + layout_decl(decl, 0); +} + +static void finish_type(void *event_data, void *data) +{ + tree type = (tree)event_data; + + if (type == NULL_TREE || type == error_mark_node) + return; + + if (TREE_CODE(type) != RECORD_TYPE) + return; + + if (TYPE_FIELDS(type) == NULL_TREE) + return; + + if (lookup_attribute("randomize_considered", TYPE_ATTRIBUTES(type))) + return; + +#ifdef __DEBUG_PLUGIN + fprintf(stderr, "Calling randomize_type on %s\n", ORIG_TYPE_NAME(type)); +#endif +#ifdef __DEBUG_VERBOSE + debug_tree(type); +#endif + randomize_type(type); + + return; +} + +static struct attribute_spec randomize_layout_attr = { }; +static struct attribute_spec no_randomize_layout_attr = { }; +static struct attribute_spec randomize_considered_attr = { }; +static struct attribute_spec randomize_performed_attr = { }; + +static void register_attributes(void *event_data, void *data) +{ + randomize_layout_attr.name = "randomize_layout"; + randomize_layout_attr.type_required = true; + randomize_layout_attr.handler = handle_randomize_layout_attr; +#if BUILDING_GCC_VERSION >= 4007 + randomize_layout_attr.affects_type_identity = true; +#endif + + no_randomize_layout_attr.name = "no_randomize_layout"; + no_randomize_layout_attr.type_required = true; + no_randomize_layout_attr.handler = handle_randomize_layout_attr; +#if BUILDING_GCC_VERSION >= 4007 + no_randomize_layout_attr.affects_type_identity = true; +#endif + + randomize_considered_attr.name = "randomize_considered"; + randomize_considered_attr.type_required = true; + randomize_considered_attr.handler = handle_randomize_considered_attr; + + randomize_performed_attr.name = "randomize_performed"; + randomize_performed_attr.type_required = true; + randomize_performed_attr.handler = handle_randomize_performed_attr; + + register_attribute(&randomize_layout_attr); + register_attribute(&no_randomize_layout_attr); + register_attribute(&randomize_considered_attr); + register_attribute(&randomize_performed_attr); +} + +static void check_bad_casts_in_constructor(tree var, tree init) +{ + unsigned HOST_WIDE_INT idx; + tree field, val; + tree field_type, val_type; + + FOR_EACH_CONSTRUCTOR_ELT(CONSTRUCTOR_ELTS(init), idx, field, val) { + if (TREE_CODE(val) == CONSTRUCTOR) { + check_bad_casts_in_constructor(var, val); + continue; + } + + /* pipacs' plugin creates franken-arrays that differ from those produced by + normal code which all have valid 'field' trees. work around this */ + if (field == NULL_TREE) + continue; + field_type = TREE_TYPE(field); + val_type = TREE_TYPE(val); + + if (TREE_CODE(field_type) != POINTER_TYPE || TREE_CODE(val_type) != POINTER_TYPE) + continue; + + if (field_type == val_type) + continue; + + field_type = TYPE_MAIN_VARIANT(strip_array_types(TYPE_MAIN_VARIANT(TREE_TYPE(field_type)))); + val_type = TYPE_MAIN_VARIANT(strip_array_types(TYPE_MAIN_VARIANT(TREE_TYPE(val_type)))); + + if (field_type == void_type_node) + continue; + if (field_type == val_type) + continue; + if (TREE_CODE(val_type) != RECORD_TYPE) + continue; + + if (!lookup_attribute("randomize_performed", TYPE_ATTRIBUTES(val_type))) + continue; + MISMATCH(DECL_SOURCE_LOCATION(var), "constructor\n", TYPE_MAIN_VARIANT(field_type), TYPE_MAIN_VARIANT(val_type)); + } +} + +/* derived from the constify plugin */ +static void check_global_variables(void *event_data, void *data) +{ + struct varpool_node *node; + tree init; + + FOR_EACH_VARIABLE(node) { + tree var = NODE_DECL(node); + init = DECL_INITIAL(var); + if (init == NULL_TREE) + continue; + + if (TREE_CODE(init) != CONSTRUCTOR) + continue; + + check_bad_casts_in_constructor(var, init); + } +} + +static bool dominated_by_is_err(const_tree rhs, basic_block bb) +{ + basic_block dom; + gimple dom_stmt; + gimple call_stmt; + const_tree dom_lhs; + const_tree poss_is_err_cond; + const_tree poss_is_err_func; + const_tree is_err_arg; + + dom = get_immediate_dominator(CDI_DOMINATORS, bb); + if (!dom) + return false; + + dom_stmt = last_stmt(dom); + if (!dom_stmt) + return false; + + if (gimple_code(dom_stmt) != GIMPLE_COND) + return false; + + if (gimple_cond_code(dom_stmt) != NE_EXPR) + return false; + + if (!integer_zerop(gimple_cond_rhs(dom_stmt))) + return false; + + poss_is_err_cond = gimple_cond_lhs(dom_stmt); + + if (TREE_CODE(poss_is_err_cond) != SSA_NAME) + return false; + + call_stmt = SSA_NAME_DEF_STMT(poss_is_err_cond); + + if (gimple_code(call_stmt) != GIMPLE_CALL) + return false; + + dom_lhs = gimple_get_lhs(call_stmt); + poss_is_err_func = gimple_call_fndecl(call_stmt); + if (!poss_is_err_func) + return false; + if (dom_lhs != poss_is_err_cond) + return false; + if (strcmp(DECL_NAME_POINTER(poss_is_err_func), "IS_ERR")) + return false; + + is_err_arg = gimple_call_arg(call_stmt, 0); + if (!is_err_arg) + return false; + + if (is_err_arg != rhs) + return false; + + return true; +} + +static void handle_local_var_initializers(void) +{ + tree var; + unsigned int i; + + FOR_EACH_LOCAL_DECL(cfun, i, var) { + tree init = DECL_INITIAL(var); + if (!init) + continue; + if (TREE_CODE(init) != CONSTRUCTOR) + continue; + check_bad_casts_in_constructor(var, init); + } +} + +static bool type_name_eq(gimple stmt, const_tree type_tree, const char *wanted_name) +{ + const char *type_name; + + if (type_tree == NULL_TREE) + return false; + + switch (TREE_CODE(type_tree)) { + case RECORD_TYPE: + type_name = TYPE_NAME_POINTER(type_tree); + break; + case INTEGER_TYPE: + if (TYPE_PRECISION(type_tree) == CHAR_TYPE_SIZE) + type_name = "char"; + else { + INFORM(gimple_location(stmt), "found non-char INTEGER_TYPE cast comparison: %qT\n", type_tree); + debug_tree(type_tree); + return false; + } + break; + case POINTER_TYPE: + if (TREE_CODE(TREE_TYPE(type_tree)) == VOID_TYPE) { + type_name = "void *"; + break; + } else { + INFORM(gimple_location(stmt), "found non-void POINTER_TYPE cast comparison %qT\n", type_tree); + debug_tree(type_tree); + return false; + } + default: + INFORM(gimple_location(stmt), "unhandled cast comparison: %qT\n", type_tree); + debug_tree(type_tree); + return false; + } + + return strcmp(type_name, wanted_name) == 0; +} + +static bool whitelisted_cast(gimple stmt, const_tree lhs_tree, const_tree rhs_tree) +{ + const struct whitelist_entry *entry; + expanded_location xloc = expand_location(gimple_location(stmt)); + + for (entry = whitelist; entry->pathname; entry++) { + if (!strstr(xloc.file, entry->pathname)) + continue; + + if (type_name_eq(stmt, lhs_tree, entry->lhs) && type_name_eq(stmt, rhs_tree, entry->rhs)) + return true; + } + + return false; +} + +/* + * iterate over all statements to find "bad" casts: + * those where the address of the start of a structure is cast + * to a pointer of a structure of a different type, or a + * structure pointer type is cast to a different structure pointer type + */ +static unsigned int find_bad_casts_execute(void) +{ + basic_block bb; + + handle_local_var_initializers(); + + FOR_EACH_BB_FN(bb, cfun) { + gimple_stmt_iterator gsi; + + for (gsi = gsi_start_bb(bb); !gsi_end_p(gsi); gsi_next(&gsi)) { + gimple stmt; + const_tree lhs; + const_tree lhs_type; + const_tree rhs1; + const_tree rhs_type; + const_tree ptr_lhs_type; + const_tree ptr_rhs_type; + const_tree op0; + const_tree op0_type; + enum tree_code rhs_code; + + stmt = gsi_stmt(gsi); + +#ifdef __DEBUG_PLUGIN +#ifdef __DEBUG_VERBOSE + debug_gimple_stmt(stmt); + debug_tree(gimple_get_lhs(stmt)); +#endif +#endif + + if (gimple_code(stmt) != GIMPLE_ASSIGN) + continue; + +#ifdef __DEBUG_PLUGIN +#ifdef __DEBUG_VERBOSE + debug_tree(gimple_assign_rhs1(stmt)); +#endif +#endif + + + rhs_code = gimple_assign_rhs_code(stmt); + + if (rhs_code != ADDR_EXPR && rhs_code != SSA_NAME) + continue; + + lhs = gimple_get_lhs(stmt); + lhs_type = TREE_TYPE(lhs); + rhs1 = gimple_assign_rhs1(stmt); + rhs_type = TREE_TYPE(rhs1); + + if (TREE_CODE(rhs_type) != POINTER_TYPE || + TREE_CODE(lhs_type) != POINTER_TYPE) + continue; + + ptr_lhs_type = TYPE_MAIN_VARIANT(strip_array_types(TYPE_MAIN_VARIANT(TREE_TYPE(lhs_type)))); + ptr_rhs_type = TYPE_MAIN_VARIANT(strip_array_types(TYPE_MAIN_VARIANT(TREE_TYPE(rhs_type)))); + + if (ptr_rhs_type == void_type_node) + continue; + + if (ptr_lhs_type == void_type_node) + continue; + + if (dominated_by_is_err(rhs1, bb)) + continue; + + if (TREE_CODE(ptr_rhs_type) != RECORD_TYPE) { +#ifndef __DEBUG_PLUGIN + if (lookup_attribute("randomize_performed", TYPE_ATTRIBUTES(ptr_lhs_type))) +#endif + { + if (!whitelisted_cast(stmt, ptr_lhs_type, ptr_rhs_type)) + MISMATCH(gimple_location(stmt), "rhs", ptr_lhs_type, ptr_rhs_type); + } + continue; + } + + if (rhs_code == SSA_NAME && ptr_lhs_type == ptr_rhs_type) + continue; + + if (rhs_code == ADDR_EXPR) { + op0 = TREE_OPERAND(rhs1, 0); + + if (op0 == NULL_TREE) + continue; + + if (TREE_CODE(op0) != VAR_DECL) + continue; + + op0_type = TYPE_MAIN_VARIANT(strip_array_types(TYPE_MAIN_VARIANT(TREE_TYPE(op0)))); + if (op0_type == ptr_lhs_type) + continue; + +#ifndef __DEBUG_PLUGIN + if (lookup_attribute("randomize_performed", TYPE_ATTRIBUTES(op0_type))) +#endif + { + if (!whitelisted_cast(stmt, ptr_lhs_type, op0_type)) + MISMATCH(gimple_location(stmt), "op0", ptr_lhs_type, op0_type); + } + } else { + const_tree ssa_name_var = SSA_NAME_VAR(rhs1); + /* skip bogus type casts introduced by container_of */ + if (ssa_name_var != NULL_TREE && DECL_NAME(ssa_name_var) && + !strcmp((const char *)DECL_NAME_POINTER(ssa_name_var), "__mptr")) + continue; +#ifndef __DEBUG_PLUGIN + if (lookup_attribute("randomize_performed", TYPE_ATTRIBUTES(ptr_rhs_type))) +#endif + { + if (!whitelisted_cast(stmt, ptr_lhs_type, ptr_rhs_type)) + MISMATCH(gimple_location(stmt), "ssa", ptr_lhs_type, ptr_rhs_type); + } + } + + } + } + return 0; +} + +#define PASS_NAME find_bad_casts +#define NO_GATE +#define TODO_FLAGS_FINISH TODO_dump_func +#include "gcc-generate-gimple-pass.h" + +__visible int plugin_init(struct plugin_name_args *plugin_info, struct plugin_gcc_version *version) +{ + int i; + const char * const plugin_name = plugin_info->base_name; + const int argc = plugin_info->argc; + const struct plugin_argument * const argv = plugin_info->argv; + bool enable = true; + int obtained_seed = 0; + struct register_pass_info find_bad_casts_pass_info; + + find_bad_casts_pass_info.pass = make_find_bad_casts_pass(); + find_bad_casts_pass_info.reference_pass_name = "ssa"; + find_bad_casts_pass_info.ref_pass_instance_number = 1; + find_bad_casts_pass_info.pos_op = PASS_POS_INSERT_AFTER; + + if (!plugin_default_version_check(version, &gcc_version)) { + error(G_("incompatible gcc/plugin versions")); + return 1; + } + + if (strncmp(lang_hooks.name, "GNU C", 5) && !strncmp(lang_hooks.name, "GNU C+", 6)) { + inform(UNKNOWN_LOCATION, G_("%s supports C only, not %s"), plugin_name, lang_hooks.name); + enable = false; + } + + for (i = 0; i < argc; ++i) { + if (!strcmp(argv[i].key, "disable")) { + enable = false; + continue; + } + if (!strcmp(argv[i].key, "performance-mode")) { + performance_mode = 1; + continue; + } + error(G_("unknown option '-fplugin-arg-%s-%s'"), plugin_name, argv[i].key); + } + + if (strlen(randstruct_seed) != 64) { + error(G_("invalid seed value supplied for %s plugin"), plugin_name); + return 1; + } + obtained_seed = sscanf(randstruct_seed, "%016llx%016llx%016llx%016llx", + &shuffle_seed[0], &shuffle_seed[1], &shuffle_seed[2], &shuffle_seed[3]); + if (obtained_seed != 4) { + error(G_("Invalid seed supplied for %s plugin"), plugin_name); + return 1; + } + + register_callback(plugin_name, PLUGIN_INFO, NULL, &randomize_layout_plugin_info); + if (enable) { + register_callback(plugin_name, PLUGIN_ALL_IPA_PASSES_START, check_global_variables, NULL); + register_callback(plugin_name, PLUGIN_PASS_MANAGER_SETUP, NULL, &find_bad_casts_pass_info); + register_callback(plugin_name, PLUGIN_FINISH_TYPE, finish_type, NULL); + register_callback(plugin_name, PLUGIN_FINISH_DECL, randomize_layout_finish_decl, NULL); + } + register_callback(plugin_name, PLUGIN_ATTRIBUTES, register_attributes, NULL); + + return 0; +} diff --git a/src/net/scripts/gcc-plugins/sancov_plugin.c b/src/net/scripts/gcc-plugins/sancov_plugin.c new file mode 100644 index 0000000..caff4a6 --- /dev/null +++ b/src/net/scripts/gcc-plugins/sancov_plugin.c @@ -0,0 +1,140 @@ +/* + * Copyright 2011-2016 by Emese Revfy <re.emese@gmail.com> + * Licensed under the GPL v2, or (at your option) v3 + * + * Homepage: + * https://github.com/ephox-gcc-plugins/sancov + * + * This plugin inserts a __sanitizer_cov_trace_pc() call at the start of basic blocks. + * It supports all gcc versions with plugin support (from gcc-4.5 on). + * It is based on the commit "Add fuzzing coverage support" by Dmitry Vyukov <dvyukov@google.com>. + * + * You can read about it more here: + * https://gcc.gnu.org/viewcvs/gcc?limit_changes=0&view=revision&revision=231296 + * https://lwn.net/Articles/674854/ + * https://github.com/google/syzkaller + * https://lwn.net/Articles/677764/ + * + * Usage: + * make run + */ + +#include "gcc-common.h" + +__visible int plugin_is_GPL_compatible; + +tree sancov_fndecl; + +static struct plugin_info sancov_plugin_info = { + .version = "20160402", + .help = "sancov plugin\n", +}; + +static unsigned int sancov_execute(void) +{ + basic_block bb; + + /* Remove this line when this plugin and kcov will be in the kernel. + if (!strcmp(DECL_NAME_POINTER(current_function_decl), DECL_NAME_POINTER(sancov_fndecl))) + return 0; + */ + + FOR_EACH_BB_FN(bb, cfun) { + const_gimple stmt; + gcall *gcall; + gimple_stmt_iterator gsi = gsi_after_labels(bb); + + if (gsi_end_p(gsi)) + continue; + + stmt = gsi_stmt(gsi); + gcall = as_a_gcall(gimple_build_call(sancov_fndecl, 0)); + gimple_set_location(gcall, gimple_location(stmt)); + gsi_insert_before(&gsi, gcall, GSI_SAME_STMT); + } + return 0; +} + +#define PASS_NAME sancov + +#define NO_GATE +#define TODO_FLAGS_FINISH TODO_dump_func | TODO_verify_stmts | TODO_update_ssa_no_phi | TODO_verify_flow + +#include "gcc-generate-gimple-pass.h" + +static void sancov_start_unit(void __unused *gcc_data, void __unused *user_data) +{ + tree leaf_attr, nothrow_attr; + tree BT_FN_VOID = build_function_type_list(void_type_node, NULL_TREE); + + sancov_fndecl = build_fn_decl("__sanitizer_cov_trace_pc", BT_FN_VOID); + + DECL_ASSEMBLER_NAME(sancov_fndecl); + TREE_PUBLIC(sancov_fndecl) = 1; + DECL_EXTERNAL(sancov_fndecl) = 1; + DECL_ARTIFICIAL(sancov_fndecl) = 1; + DECL_PRESERVE_P(sancov_fndecl) = 1; + DECL_UNINLINABLE(sancov_fndecl) = 1; + TREE_USED(sancov_fndecl) = 1; + + nothrow_attr = tree_cons(get_identifier("nothrow"), NULL, NULL); + decl_attributes(&sancov_fndecl, nothrow_attr, 0); + gcc_assert(TREE_NOTHROW(sancov_fndecl)); +#if BUILDING_GCC_VERSION > 4005 + leaf_attr = tree_cons(get_identifier("leaf"), NULL, NULL); + decl_attributes(&sancov_fndecl, leaf_attr, 0); +#endif +} + +__visible int plugin_init(struct plugin_name_args *plugin_info, struct plugin_gcc_version *version) +{ + int i; + const char * const plugin_name = plugin_info->base_name; + const int argc = plugin_info->argc; + const struct plugin_argument * const argv = plugin_info->argv; + bool enable = true; + + static const struct ggc_root_tab gt_ggc_r_gt_sancov[] = { + { + .base = &sancov_fndecl, + .nelt = 1, + .stride = sizeof(sancov_fndecl), + .cb = >_ggc_mx_tree_node, + .pchw = >_pch_nx_tree_node + }, + LAST_GGC_ROOT_TAB + }; + + /* BBs can be split afterwards?? */ +#if BUILDING_GCC_VERSION >= 4009 + PASS_INFO(sancov, "asan", 0, PASS_POS_INSERT_BEFORE); +#else + PASS_INFO(sancov, "nrv", 1, PASS_POS_INSERT_BEFORE); +#endif + + if (!plugin_default_version_check(version, &gcc_version)) { + error(G_("incompatible gcc/plugin versions")); + return 1; + } + + for (i = 0; i < argc; ++i) { + if (!strcmp(argv[i].key, "no-sancov")) { + enable = false; + continue; + } + error(G_("unknown option '-fplugin-arg-%s-%s'"), plugin_name, argv[i].key); + } + + register_callback(plugin_name, PLUGIN_INFO, NULL, &sancov_plugin_info); + + if (!enable) + return 0; + +#if BUILDING_GCC_VERSION < 6000 + register_callback(plugin_name, PLUGIN_START_UNIT, &sancov_start_unit, NULL); + register_callback(plugin_name, PLUGIN_REGISTER_GGC_ROOTS, NULL, (void *)>_ggc_r_gt_sancov); + register_callback(plugin_name, PLUGIN_PASS_MANAGER_SETUP, NULL, &sancov_pass_info); +#endif + + return 0; +} diff --git a/src/net/scripts/gcc-plugins/stackleak_plugin.c b/src/net/scripts/gcc-plugins/stackleak_plugin.c new file mode 100644 index 0000000..dacd697 --- /dev/null +++ b/src/net/scripts/gcc-plugins/stackleak_plugin.c @@ -0,0 +1,631 @@ +/* + * Copyright 2011-2017 by the PaX Team <pageexec@freemail.hu> + * Modified by Alexander Popov <alex.popov@linux.com> + * Licensed under the GPL v2 + * + * Note: the choice of the license means that the compilation process is + * NOT 'eligible' as defined by gcc's library exception to the GPL v3, + * but for the kernel it doesn't matter since it doesn't link against + * any of the gcc libraries + * + * This gcc plugin is needed for tracking the lowest border of the kernel stack. + * It instruments the kernel code inserting stackleak_track_stack() calls: + * - after alloca(); + * - for the functions with a stack frame size greater than or equal + * to the "track-min-size" plugin parameter. + * + * This plugin is ported from grsecurity/PaX. For more information see: + * https://grsecurity.net/ + * https://pax.grsecurity.net/ + * + * Debugging: + * - use fprintf() to stderr, debug_generic_expr(), debug_gimple_stmt(), + * print_rtl_single() and debug_rtx(); + * - add "-fdump-tree-all -fdump-rtl-all" to the plugin CFLAGS in + * Makefile.gcc-plugins to see the verbose dumps of the gcc passes; + * - use gcc -E to understand the preprocessing shenanigans; + * - use gcc with enabled CFG/GIMPLE/SSA verification (--enable-checking). + */ + +#include "gcc-common.h" + +__visible int plugin_is_GPL_compatible; + +static int track_frame_size = -1; +static bool build_for_x86 = false; +static const char track_function[] = "stackleak_track_stack"; +static bool disable = false; +static bool verbose = false; + +/* + * Mark these global variables (roots) for gcc garbage collector since + * they point to the garbage-collected memory. + */ +static GTY(()) tree track_function_decl; + +static struct plugin_info stackleak_plugin_info = { + .version = "201707101337", + .help = "track-min-size=nn\ttrack stack for functions with a stack frame size >= nn bytes\n" + "arch=target_arch\tspecify target build arch\n" + "disable\t\tdo not activate the plugin\n" + "verbose\t\tprint info about the instrumentation\n" +}; + +static void add_stack_tracking_gcall(gimple_stmt_iterator *gsi, bool after) +{ + gimple stmt; + gcall *gimple_call; + cgraph_node_ptr node; + basic_block bb; + + /* Insert calling stackleak_track_stack() */ + stmt = gimple_build_call(track_function_decl, 0); + gimple_call = as_a_gcall(stmt); + if (after) + gsi_insert_after(gsi, gimple_call, GSI_CONTINUE_LINKING); + else + gsi_insert_before(gsi, gimple_call, GSI_SAME_STMT); + + /* Update the cgraph */ + bb = gimple_bb(gimple_call); + node = cgraph_get_create_node(track_function_decl); + gcc_assert(node); + cgraph_create_edge(cgraph_get_node(current_function_decl), node, + gimple_call, bb->count, + compute_call_stmt_bb_frequency(current_function_decl, bb)); +} + +static bool is_alloca(gimple stmt) +{ + if (gimple_call_builtin_p(stmt, BUILT_IN_ALLOCA)) + return true; + +#if BUILDING_GCC_VERSION >= 4007 + if (gimple_call_builtin_p(stmt, BUILT_IN_ALLOCA_WITH_ALIGN)) + return true; +#endif + + return false; +} + +static tree get_current_stack_pointer_decl(void) +{ + varpool_node_ptr node; + + FOR_EACH_VARIABLE(node) { + tree var = NODE_DECL(node); + tree name = DECL_NAME(var); + + if (DECL_NAME_LENGTH(var) != sizeof("current_stack_pointer") - 1) + continue; + + if (strcmp(IDENTIFIER_POINTER(name), "current_stack_pointer")) + continue; + + return var; + } + + if (verbose) { + fprintf(stderr, "stackleak: missing current_stack_pointer in %s()\n", + DECL_NAME_POINTER(current_function_decl)); + } + return NULL_TREE; +} + +static void add_stack_tracking_gasm(gimple_stmt_iterator *gsi, bool after) +{ + gasm *asm_call = NULL; + tree sp_decl, input; + vec<tree, va_gc> *inputs = NULL; + + /* 'no_caller_saved_registers' is currently supported only for x86 */ + gcc_assert(build_for_x86); + + /* + * Insert calling stackleak_track_stack() in asm: + * asm volatile("call stackleak_track_stack" + * :: "r" (current_stack_pointer)) + * Use ASM_CALL_CONSTRAINT trick from arch/x86/include/asm/asm.h. + * This constraint is taken into account during gcc shrink-wrapping + * optimization. It is needed to be sure that stackleak_track_stack() + * call is inserted after the prologue of the containing function, + * when the stack frame is prepared. + */ + sp_decl = get_current_stack_pointer_decl(); + if (sp_decl == NULL_TREE) { + add_stack_tracking_gcall(gsi, after); + return; + } + input = build_tree_list(NULL_TREE, build_const_char_string(2, "r")); + input = chainon(NULL_TREE, build_tree_list(input, sp_decl)); + vec_safe_push(inputs, input); + asm_call = gimple_build_asm_vec("call stackleak_track_stack", + inputs, NULL, NULL, NULL); + gimple_asm_set_volatile(asm_call, true); + if (after) + gsi_insert_after(gsi, asm_call, GSI_CONTINUE_LINKING); + else + gsi_insert_before(gsi, asm_call, GSI_SAME_STMT); + update_stmt(asm_call); +} + +static void add_stack_tracking(gimple_stmt_iterator *gsi, bool after) +{ + /* + * The 'no_caller_saved_registers' attribute is used for + * stackleak_track_stack(). If the compiler supports this attribute for + * the target arch, we can add calling stackleak_track_stack() in asm. + * That improves performance: we avoid useless operations with the + * caller-saved registers in the functions from which we will remove + * stackleak_track_stack() call during the stackleak_cleanup pass. + */ + if (lookup_attribute_spec(get_identifier("no_caller_saved_registers"))) + add_stack_tracking_gasm(gsi, after); + else + add_stack_tracking_gcall(gsi, after); +} + +/* + * Work with the GIMPLE representation of the code. Insert the + * stackleak_track_stack() call after alloca() and into the beginning + * of the function if it is not instrumented. + */ +static unsigned int stackleak_instrument_execute(void) +{ + basic_block bb, entry_bb; + bool prologue_instrumented = false, is_leaf = true; + gimple_stmt_iterator gsi = { 0 }; + + /* + * ENTRY_BLOCK_PTR is a basic block which represents possible entry + * point of a function. This block does not contain any code and + * has a CFG edge to its successor. + */ + gcc_assert(single_succ_p(ENTRY_BLOCK_PTR_FOR_FN(cfun))); + entry_bb = single_succ(ENTRY_BLOCK_PTR_FOR_FN(cfun)); + + /* + * Loop through the GIMPLE statements in each of cfun basic blocks. + * cfun is a global variable which represents the function that is + * currently processed. + */ + FOR_EACH_BB_FN(bb, cfun) { + for (gsi = gsi_start_bb(bb); !gsi_end_p(gsi); gsi_next(&gsi)) { + gimple stmt; + + stmt = gsi_stmt(gsi); + + /* Leaf function is a function which makes no calls */ + if (is_gimple_call(stmt)) + is_leaf = false; + + if (!is_alloca(stmt)) + continue; + + if (verbose) { + fprintf(stderr, "stackleak: be careful, alloca() in %s()\n", + DECL_NAME_POINTER(current_function_decl)); + } + + /* Insert stackleak_track_stack() call after alloca() */ + add_stack_tracking(&gsi, true); + if (bb == entry_bb) + prologue_instrumented = true; + } + } + + if (prologue_instrumented) + return 0; + + /* + * Special cases to skip the instrumentation. + * + * Taking the address of static inline functions materializes them, + * but we mustn't instrument some of them as the resulting stack + * alignment required by the function call ABI will break other + * assumptions regarding the expected (but not otherwise enforced) + * register clobbering ABI. + * + * Case in point: native_save_fl on amd64 when optimized for size + * clobbers rdx if it were instrumented here. + * + * TODO: any more special cases? + */ + if (is_leaf && + !TREE_PUBLIC(current_function_decl) && + DECL_DECLARED_INLINE_P(current_function_decl)) { + return 0; + } + + if (is_leaf && + !strncmp(IDENTIFIER_POINTER(DECL_NAME(current_function_decl)), + "_paravirt_", 10)) { + return 0; + } + + /* Insert stackleak_track_stack() call at the function beginning */ + bb = entry_bb; + if (!single_pred_p(bb)) { + /* gcc_assert(bb_loop_depth(bb) || + (bb->flags & BB_IRREDUCIBLE_LOOP)); */ + split_edge(single_succ_edge(ENTRY_BLOCK_PTR_FOR_FN(cfun))); + gcc_assert(single_succ_p(ENTRY_BLOCK_PTR_FOR_FN(cfun))); + bb = single_succ(ENTRY_BLOCK_PTR_FOR_FN(cfun)); + } + gsi = gsi_after_labels(bb); + add_stack_tracking(&gsi, false); + + return 0; +} + +static bool large_stack_frame(void) +{ +#if BUILDING_GCC_VERSION >= 8000 + return maybe_ge(get_frame_size(), track_frame_size); +#else + return (get_frame_size() >= track_frame_size); +#endif +} + +static void remove_stack_tracking_gcall(void) +{ + rtx_insn *insn, *next; + + /* + * Find stackleak_track_stack() calls. Loop through the chain of insns, + * which is an RTL representation of the code for a function. + * + * The example of a matching insn: + * (call_insn 8 4 10 2 (call (mem (symbol_ref ("stackleak_track_stack") + * [flags 0x41] <function_decl 0x7f7cd3302a80 stackleak_track_stack>) + * [0 stackleak_track_stack S1 A8]) (0)) 675 {*call} (expr_list + * (symbol_ref ("stackleak_track_stack") [flags 0x41] <function_decl + * 0x7f7cd3302a80 stackleak_track_stack>) (expr_list (0) (nil))) (nil)) + */ + for (insn = get_insns(); insn; insn = next) { + rtx body; + + next = NEXT_INSN(insn); + + /* Check the expression code of the insn */ + if (!CALL_P(insn)) + continue; + + /* + * Check the expression code of the insn body, which is an RTL + * Expression (RTX) describing the side effect performed by + * that insn. + */ + body = PATTERN(insn); + + if (GET_CODE(body) == PARALLEL) + body = XVECEXP(body, 0, 0); + + if (GET_CODE(body) != CALL) + continue; + + /* + * Check the first operand of the call expression. It should + * be a mem RTX describing the needed subroutine with a + * symbol_ref RTX. + */ + body = XEXP(body, 0); + if (GET_CODE(body) != MEM) + continue; + + body = XEXP(body, 0); + if (GET_CODE(body) != SYMBOL_REF) + continue; + + if (SYMBOL_REF_DECL(body) != track_function_decl) + continue; + + /* Delete the stackleak_track_stack() call */ + delete_insn_and_edges(insn); +#if BUILDING_GCC_VERSION >= 4007 && BUILDING_GCC_VERSION < 8000 + if (GET_CODE(next) == NOTE && + NOTE_KIND(next) == NOTE_INSN_CALL_ARG_LOCATION) { + insn = next; + next = NEXT_INSN(insn); + delete_insn_and_edges(insn); + } +#endif + } +} + +static bool remove_stack_tracking_gasm(void) +{ + bool removed = false; + rtx_insn *insn, *next; + + /* 'no_caller_saved_registers' is currently supported only for x86 */ + gcc_assert(build_for_x86); + + /* + * Find stackleak_track_stack() asm calls. Loop through the chain of + * insns, which is an RTL representation of the code for a function. + * + * The example of a matching insn: + * (insn 11 5 12 2 (parallel [ (asm_operands/v + * ("call stackleak_track_stack") ("") 0 + * [ (reg/v:DI 7 sp [ current_stack_pointer ]) ] + * [ (asm_input:DI ("r")) ] []) + * (clobber (reg:CC 17 flags)) ]) -1 (nil)) + */ + for (insn = get_insns(); insn; insn = next) { + rtx body; + + next = NEXT_INSN(insn); + + /* Check the expression code of the insn */ + if (!NONJUMP_INSN_P(insn)) + continue; + + /* + * Check the expression code of the insn body, which is an RTL + * Expression (RTX) describing the side effect performed by + * that insn. + */ + body = PATTERN(insn); + + if (GET_CODE(body) != PARALLEL) + continue; + + body = XVECEXP(body, 0, 0); + + if (GET_CODE(body) != ASM_OPERANDS) + continue; + + if (strcmp(ASM_OPERANDS_TEMPLATE(body), + "call stackleak_track_stack")) { + continue; + } + + delete_insn_and_edges(insn); + gcc_assert(!removed); + removed = true; + } + + return removed; +} + +/* + * Work with the RTL representation of the code. + * Remove the unneeded stackleak_track_stack() calls from the functions + * which don't call alloca() and don't have a large enough stack frame size. + */ +static unsigned int stackleak_cleanup_execute(void) +{ + const char *fn = DECL_NAME_POINTER(current_function_decl); + bool removed = false; + + /* + * Leave stack tracking in functions that call alloca(). + * Additional case: + * gcc before version 7 called allocate_dynamic_stack_space() from + * expand_stack_vars() for runtime alignment of constant-sized stack + * variables. That caused cfun->calls_alloca to be set for functions + * that in fact don't use alloca(). + * For more info see gcc commit 7072df0aae0c59ae437e. + * Let's leave such functions instrumented as well. + */ + if (cfun->calls_alloca) { + if (verbose) + fprintf(stderr, "stackleak: instrument %s(): calls_alloca\n", fn); + return 0; + } + + /* Leave stack tracking in functions with large stack frame */ + if (large_stack_frame()) { + if (verbose) + fprintf(stderr, "stackleak: instrument %s()\n", fn); + return 0; + } + + if (lookup_attribute_spec(get_identifier("no_caller_saved_registers"))) + removed = remove_stack_tracking_gasm(); + + if (!removed) + remove_stack_tracking_gcall(); + + return 0; +} + +/* + * STRING_CST may or may not be NUL terminated: + * https://gcc.gnu.org/onlinedocs/gccint/Constant-expressions.html + */ +static inline bool string_equal(tree node, const char *string, int length) +{ + if (TREE_STRING_LENGTH(node) < length) + return false; + if (TREE_STRING_LENGTH(node) > length + 1) + return false; + if (TREE_STRING_LENGTH(node) == length + 1 && + TREE_STRING_POINTER(node)[length] != '\0') + return false; + return !memcmp(TREE_STRING_POINTER(node), string, length); +} +#define STRING_EQUAL(node, str) string_equal(node, str, strlen(str)) + +static bool stackleak_gate(void) +{ + tree section; + + section = lookup_attribute("section", + DECL_ATTRIBUTES(current_function_decl)); + if (section && TREE_VALUE(section)) { + section = TREE_VALUE(TREE_VALUE(section)); + + if (STRING_EQUAL(section, ".init.text")) + return false; + if (STRING_EQUAL(section, ".devinit.text")) + return false; + if (STRING_EQUAL(section, ".cpuinit.text")) + return false; + if (STRING_EQUAL(section, ".meminit.text")) + return false; + } + + return track_frame_size >= 0; +} + +/* Build the function declaration for stackleak_track_stack() */ +static void stackleak_start_unit(void *gcc_data __unused, + void *user_data __unused) +{ + tree fntype; + + /* void stackleak_track_stack(void) */ + fntype = build_function_type_list(void_type_node, NULL_TREE); + track_function_decl = build_fn_decl(track_function, fntype); + DECL_ASSEMBLER_NAME(track_function_decl); /* for LTO */ + TREE_PUBLIC(track_function_decl) = 1; + TREE_USED(track_function_decl) = 1; + DECL_EXTERNAL(track_function_decl) = 1; + DECL_ARTIFICIAL(track_function_decl) = 1; + DECL_PRESERVE_P(track_function_decl) = 1; +} + +/* + * Pass gate function is a predicate function that gets executed before the + * corresponding pass. If the return value is 'true' the pass gets executed, + * otherwise, it is skipped. + */ +static bool stackleak_instrument_gate(void) +{ + return stackleak_gate(); +} + +#define PASS_NAME stackleak_instrument +#define PROPERTIES_REQUIRED PROP_gimple_leh | PROP_cfg +#define TODO_FLAGS_START TODO_verify_ssa | TODO_verify_flow | TODO_verify_stmts +#define TODO_FLAGS_FINISH TODO_verify_ssa | TODO_verify_stmts | TODO_dump_func \ + | TODO_update_ssa | TODO_rebuild_cgraph_edges +#include "gcc-generate-gimple-pass.h" + +static bool stackleak_cleanup_gate(void) +{ + return stackleak_gate(); +} + +#define PASS_NAME stackleak_cleanup +#define TODO_FLAGS_FINISH TODO_dump_func +#include "gcc-generate-rtl-pass.h" + +/* + * Every gcc plugin exports a plugin_init() function that is called right + * after the plugin is loaded. This function is responsible for registering + * the plugin callbacks and doing other required initialization. + */ +__visible int plugin_init(struct plugin_name_args *plugin_info, + struct plugin_gcc_version *version) +{ + const char * const plugin_name = plugin_info->base_name; + const int argc = plugin_info->argc; + const struct plugin_argument * const argv = plugin_info->argv; + int i = 0; + + /* Extra GGC root tables describing our GTY-ed data */ + static const struct ggc_root_tab gt_ggc_r_gt_stackleak[] = { + { + .base = &track_function_decl, + .nelt = 1, + .stride = sizeof(track_function_decl), + .cb = >_ggc_mx_tree_node, + .pchw = >_pch_nx_tree_node + }, + LAST_GGC_ROOT_TAB + }; + + /* + * The stackleak_instrument pass should be executed before the + * "optimized" pass, which is the control flow graph cleanup that is + * performed just before expanding gcc trees to the RTL. In former + * versions of the plugin this new pass was inserted before the + * "tree_profile" pass, which is currently called "profile". + */ + PASS_INFO(stackleak_instrument, "optimized", 1, + PASS_POS_INSERT_BEFORE); + + /* + * The stackleak_cleanup pass should be executed before the "*free_cfg" + * pass. It's the moment when the stack frame size is already final, + * function prologues and epilogues are generated, and the + * machine-dependent code transformations are not done. + */ + PASS_INFO(stackleak_cleanup, "*free_cfg", 1, PASS_POS_INSERT_BEFORE); + + if (!plugin_default_version_check(version, &gcc_version)) { + error(G_("incompatible gcc/plugin versions")); + return 1; + } + + /* Parse the plugin arguments */ + for (i = 0; i < argc; i++) { + if (!strcmp(argv[i].key, "track-min-size")) { + if (!argv[i].value) { + error(G_("no value supplied for option '-fplugin-arg-%s-%s'"), + plugin_name, argv[i].key); + return 1; + } + + track_frame_size = atoi(argv[i].value); + if (track_frame_size < 0) { + error(G_("invalid option argument '-fplugin-arg-%s-%s=%s'"), + plugin_name, argv[i].key, argv[i].value); + return 1; + } + } else if (!strcmp(argv[i].key, "arch")) { + if (!argv[i].value) { + error(G_("no value supplied for option '-fplugin-arg-%s-%s'"), + plugin_name, argv[i].key); + return 1; + } + + if (!strcmp(argv[i].value, "x86")) + build_for_x86 = true; + } else if (!strcmp(argv[i].key, "disable")) { + disable = true; + } else if (!strcmp(argv[i].key, "verbose")) { + verbose = true; + } else { + error(G_("unknown option '-fplugin-arg-%s-%s'"), + plugin_name, argv[i].key); + return 1; + } + } + + if (disable) { + if (verbose) + fprintf(stderr, "stackleak: disabled for this translation unit\n"); + return 0; + } + + /* Give the information about the plugin */ + register_callback(plugin_name, PLUGIN_INFO, NULL, + &stackleak_plugin_info); + + /* Register to be called before processing a translation unit */ + register_callback(plugin_name, PLUGIN_START_UNIT, + &stackleak_start_unit, NULL); + + /* Register an extra GCC garbage collector (GGC) root table */ + register_callback(plugin_name, PLUGIN_REGISTER_GGC_ROOTS, NULL, + (void *)>_ggc_r_gt_stackleak); + + /* + * Hook into the Pass Manager to register new gcc passes. + * + * The stack frame size info is available only at the last RTL pass, + * when it's too late to insert complex code like a function call. + * So we register two gcc passes to instrument every function at first + * and remove the unneeded instrumentation later. + */ + register_callback(plugin_name, PLUGIN_PASS_MANAGER_SETUP, NULL, + &stackleak_instrument_pass_info); + register_callback(plugin_name, PLUGIN_PASS_MANAGER_SETUP, NULL, + &stackleak_cleanup_pass_info); + + return 0; +} diff --git a/src/net/scripts/gcc-plugins/structleak_plugin.c b/src/net/scripts/gcc-plugins/structleak_plugin.c new file mode 100644 index 0000000..b9ef2e1 --- /dev/null +++ b/src/net/scripts/gcc-plugins/structleak_plugin.c @@ -0,0 +1,264 @@ +/* + * Copyright 2013-2017 by PaX Team <pageexec@freemail.hu> + * Licensed under the GPL v2 + * + * Note: the choice of the license means that the compilation process is + * NOT 'eligible' as defined by gcc's library exception to the GPL v3, + * but for the kernel it doesn't matter since it doesn't link against + * any of the gcc libraries + * + * gcc plugin to forcibly initialize certain local variables that could + * otherwise leak kernel stack to userland if they aren't properly initialized + * by later code + * + * Homepage: https://pax.grsecurity.net/ + * + * Options: + * -fplugin-arg-structleak_plugin-disable + * -fplugin-arg-structleak_plugin-verbose + * -fplugin-arg-structleak_plugin-byref + * -fplugin-arg-structleak_plugin-byref-all + * + * Usage: + * $ # for 4.5/4.6/C based 4.7 + * $ gcc -I`gcc -print-file-name=plugin`/include -I`gcc -print-file-name=plugin`/include/c-family -fPIC -shared -O2 -o structleak_plugin.so structleak_plugin.c + * $ # for C++ based 4.7/4.8+ + * $ g++ -I`g++ -print-file-name=plugin`/include -I`g++ -print-file-name=plugin`/include/c-family -fPIC -shared -O2 -o structleak_plugin.so structleak_plugin.c + * $ gcc -fplugin=./structleak_plugin.so test.c -O2 + * + * TODO: eliminate redundant initializers + */ + +#include "gcc-common.h" + +/* unused C type flag in all versions 4.5-6 */ +#define TYPE_USERSPACE(TYPE) TYPE_LANG_FLAG_5(TYPE) + +__visible int plugin_is_GPL_compatible; + +static struct plugin_info structleak_plugin_info = { + .version = "20190125vanilla", + .help = "disable\tdo not activate plugin\n" + "byref\tinit structs passed by reference\n" + "byref-all\tinit anything passed by reference\n" + "verbose\tprint all initialized variables\n", +}; + +#define BYREF_STRUCT 1 +#define BYREF_ALL 2 + +static bool verbose; +static int byref; + +static tree handle_user_attribute(tree *node, tree name, tree args, int flags, bool *no_add_attrs) +{ + *no_add_attrs = true; + + /* check for types? for now accept everything linux has to offer */ + if (TREE_CODE(*node) != FIELD_DECL) + return NULL_TREE; + + *no_add_attrs = false; + return NULL_TREE; +} + +static struct attribute_spec user_attr = { }; + +static void register_attributes(void *event_data, void *data) +{ + user_attr.name = "user"; + user_attr.handler = handle_user_attribute; +#if BUILDING_GCC_VERSION >= 4007 + user_attr.affects_type_identity = true; +#endif + + register_attribute(&user_attr); +} + +static tree get_field_type(tree field) +{ + return strip_array_types(TREE_TYPE(field)); +} + +static bool is_userspace_type(tree type) +{ + tree field; + + for (field = TYPE_FIELDS(type); field; field = TREE_CHAIN(field)) { + tree fieldtype = get_field_type(field); + enum tree_code code = TREE_CODE(fieldtype); + + if (code == RECORD_TYPE || code == UNION_TYPE) + if (is_userspace_type(fieldtype)) + return true; + + if (lookup_attribute("user", DECL_ATTRIBUTES(field))) + return true; + } + return false; +} + +static void finish_type(void *event_data, void *data) +{ + tree type = (tree)event_data; + + if (type == NULL_TREE || type == error_mark_node) + return; + +#if BUILDING_GCC_VERSION >= 5000 + if (TREE_CODE(type) == ENUMERAL_TYPE) + return; +#endif + + if (TYPE_USERSPACE(type)) + return; + + if (is_userspace_type(type)) + TYPE_USERSPACE(type) = 1; +} + +static void initialize(tree var) +{ + basic_block bb; + gimple_stmt_iterator gsi; + tree initializer; + gimple init_stmt; + tree type; + + /* this is the original entry bb before the forced split */ + bb = single_succ(ENTRY_BLOCK_PTR_FOR_FN(cfun)); + + /* first check if variable is already initialized, warn otherwise */ + for (gsi = gsi_start_bb(bb); !gsi_end_p(gsi); gsi_next(&gsi)) { + gimple stmt = gsi_stmt(gsi); + tree rhs1; + + /* we're looking for an assignment of a single rhs... */ + if (!gimple_assign_single_p(stmt)) + continue; + rhs1 = gimple_assign_rhs1(stmt); +#if BUILDING_GCC_VERSION >= 4007 + /* ... of a non-clobbering expression... */ + if (TREE_CLOBBER_P(rhs1)) + continue; +#endif + /* ... to our variable... */ + if (gimple_get_lhs(stmt) != var) + continue; + /* if it's an initializer then we're good */ + if (TREE_CODE(rhs1) == CONSTRUCTOR) + return; + } + + /* these aren't the 0days you're looking for */ + if (verbose) + inform(DECL_SOURCE_LOCATION(var), + "%s variable will be forcibly initialized", + (byref && TREE_ADDRESSABLE(var)) ? "byref" + : "userspace"); + + /* build the initializer expression */ + type = TREE_TYPE(var); + if (AGGREGATE_TYPE_P(type)) + initializer = build_constructor(type, NULL); + else + initializer = fold_convert(type, integer_zero_node); + + /* build the initializer stmt */ + init_stmt = gimple_build_assign(var, initializer); + gsi = gsi_after_labels(single_succ(ENTRY_BLOCK_PTR_FOR_FN(cfun))); + gsi_insert_before(&gsi, init_stmt, GSI_NEW_STMT); + update_stmt(init_stmt); +} + +static unsigned int structleak_execute(void) +{ + basic_block bb; + unsigned int ret = 0; + tree var; + unsigned int i; + + /* split the first bb where we can put the forced initializers */ + gcc_assert(single_succ_p(ENTRY_BLOCK_PTR_FOR_FN(cfun))); + bb = single_succ(ENTRY_BLOCK_PTR_FOR_FN(cfun)); + if (!single_pred_p(bb)) { + split_edge(single_succ_edge(ENTRY_BLOCK_PTR_FOR_FN(cfun))); + gcc_assert(single_succ_p(ENTRY_BLOCK_PTR_FOR_FN(cfun))); + } + + /* enumerate all local variables and forcibly initialize our targets */ + FOR_EACH_LOCAL_DECL(cfun, i, var) { + tree type = TREE_TYPE(var); + + gcc_assert(DECL_P(var)); + if (!auto_var_in_fn_p(var, current_function_decl)) + continue; + + /* only care about structure types unless byref-all */ + if (byref != BYREF_ALL && TREE_CODE(type) != RECORD_TYPE && TREE_CODE(type) != UNION_TYPE) + continue; + + /* if the type is of interest, examine the variable */ + if (TYPE_USERSPACE(type) || + (byref && TREE_ADDRESSABLE(var))) + initialize(var); + } + + return ret; +} + +#define PASS_NAME structleak +#define NO_GATE +#define PROPERTIES_REQUIRED PROP_cfg +#define TODO_FLAGS_FINISH TODO_verify_il | TODO_verify_ssa | TODO_verify_stmts | TODO_dump_func | TODO_remove_unused_locals | TODO_update_ssa | TODO_ggc_collect | TODO_verify_flow +#include "gcc-generate-gimple-pass.h" + +__visible int plugin_init(struct plugin_name_args *plugin_info, struct plugin_gcc_version *version) +{ + int i; + const char * const plugin_name = plugin_info->base_name; + const int argc = plugin_info->argc; + const struct plugin_argument * const argv = plugin_info->argv; + bool enable = true; + + PASS_INFO(structleak, "early_optimizations", 1, PASS_POS_INSERT_BEFORE); + + if (!plugin_default_version_check(version, &gcc_version)) { + error(G_("incompatible gcc/plugin versions")); + return 1; + } + + if (strncmp(lang_hooks.name, "GNU C", 5) && !strncmp(lang_hooks.name, "GNU C+", 6)) { + inform(UNKNOWN_LOCATION, G_("%s supports C only, not %s"), plugin_name, lang_hooks.name); + enable = false; + } + + for (i = 0; i < argc; ++i) { + if (!strcmp(argv[i].key, "disable")) { + enable = false; + continue; + } + if (!strcmp(argv[i].key, "verbose")) { + verbose = true; + continue; + } + if (!strcmp(argv[i].key, "byref")) { + byref = BYREF_STRUCT; + continue; + } + if (!strcmp(argv[i].key, "byref-all")) { + byref = BYREF_ALL; + continue; + } + error(G_("unknown option '-fplugin-arg-%s-%s'"), plugin_name, argv[i].key); + } + + register_callback(plugin_name, PLUGIN_INFO, NULL, &structleak_plugin_info); + if (enable) { + register_callback(plugin_name, PLUGIN_PASS_MANAGER_SETUP, NULL, &structleak_pass_info); + register_callback(plugin_name, PLUGIN_FINISH_TYPE, finish_type, NULL); + } + register_callback(plugin_name, PLUGIN_ATTRIBUTES, register_attributes, NULL); + + return 0; +} diff --git a/src/net/scripts/gcc-version.sh b/src/net/scripts/gcc-version.sh new file mode 100755 index 0000000..ae35343 --- /dev/null +++ b/src/net/scripts/gcc-version.sh @@ -0,0 +1,20 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0 +# +# gcc-version gcc-command +# +# Print the gcc version of `gcc-command' in a 5 or 6-digit form +# such as `29503' for gcc-2.95.3, `30301' for gcc-3.3.1, etc. + +compiler="$*" + +if [ ${#compiler} -eq 0 ]; then + echo "Error: No compiler specified." >&2 + printf "Usage:\n\t$0 <gcc-command>\n" >&2 + exit 1 +fi + +MAJOR=$(echo __GNUC__ | $compiler -E -x c - | tail -n 1) +MINOR=$(echo __GNUC_MINOR__ | $compiler -E -x c - | tail -n 1) +PATCHLEVEL=$(echo __GNUC_PATCHLEVEL__ | $compiler -E -x c - | tail -n 1) +printf "%d%02d%02d\\n" $MAJOR $MINOR $PATCHLEVEL diff --git a/src/net/scripts/gcc-x86_32-has-stack-protector.sh b/src/net/scripts/gcc-x86_32-has-stack-protector.sh new file mode 100755 index 0000000..f5c1194 --- /dev/null +++ b/src/net/scripts/gcc-x86_32-has-stack-protector.sh @@ -0,0 +1,4 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0 + +echo "int foo(void) { char X[200]; return 3; }" | $* -S -x c -c -m32 -O0 -fstack-protector - -o - 2> /dev/null | grep -q "%gs" diff --git a/src/net/scripts/gcc-x86_64-has-stack-protector.sh b/src/net/scripts/gcc-x86_64-has-stack-protector.sh new file mode 100755 index 0000000..75e4e22 --- /dev/null +++ b/src/net/scripts/gcc-x86_64-has-stack-protector.sh @@ -0,0 +1,4 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0 + +echo "int foo(void) { char X[200]; return 3; }" | $* -S -x c -c -m64 -O0 -mcmodel=kernel -fno-PIE -fstack-protector - -o - 2> /dev/null | grep -q "%gs" diff --git a/src/net/scripts/gdb/Makefile b/src/net/scripts/gdb/Makefile new file mode 100644 index 0000000..3fca193 --- /dev/null +++ b/src/net/scripts/gdb/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +subdir-y := linux diff --git a/src/net/scripts/gdb/linux/.gitignore b/src/net/scripts/gdb/linux/.gitignore new file mode 100644 index 0000000..43234cb --- /dev/null +++ b/src/net/scripts/gdb/linux/.gitignore @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only +*.pyc +*.pyo +constants.py diff --git a/src/net/scripts/gdb/linux/Makefile b/src/net/scripts/gdb/linux/Makefile new file mode 100644 index 0000000..1247550 --- /dev/null +++ b/src/net/scripts/gdb/linux/Makefile @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: GPL-2.0 + +ifdef building_out_of_srctree + +symlinks := $(patsubst $(srctree)/$(src)/%,%,$(wildcard $(srctree)/$(src)/*.py)) + +quiet_cmd_symlink = SYMLINK $@ + cmd_symlink = ln -fsn $(patsubst $(obj)/%,$(abspath $(srctree))/$(src)/%,$@) $@ + +extra-y += $(symlinks) +$(addprefix $(obj)/, $(symlinks)): FORCE + $(call if_changed,symlink) + +endif + +quiet_cmd_gen_constants_py = GEN $@ + cmd_gen_constants_py = \ + $(CPP) -E -x c -P $(c_flags) $< > $@ ;\ + sed -i '1,/<!-- end-c-headers -->/d;' $@ + +extra-y += constants.py +$(obj)/constants.py: $(src)/constants.py.in FORCE + $(call if_changed_dep,gen_constants_py) + +clean-files := *.pyc *.pyo diff --git a/src/net/scripts/gdb/linux/__init__.py b/src/net/scripts/gdb/linux/__init__.py new file mode 100644 index 0000000..4680fb1 --- /dev/null +++ b/src/net/scripts/gdb/linux/__init__.py @@ -0,0 +1 @@ +# nothing to do for the initialization of this package diff --git a/src/net/scripts/gdb/linux/clk.py b/src/net/scripts/gdb/linux/clk.py new file mode 100644 index 0000000..061aecf --- /dev/null +++ b/src/net/scripts/gdb/linux/clk.py @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Copyright (c) NXP 2019 + +import gdb +import sys + +from linux import utils, lists, constants + +clk_core_type = utils.CachedType("struct clk_core") + + +def clk_core_for_each_child(hlist_head): + return lists.hlist_for_each_entry(hlist_head, + clk_core_type.get_type().pointer(), "child_node") + + +class LxClkSummary(gdb.Command): + """Print clk tree summary + +Output is a subset of /sys/kernel/debug/clk/clk_summary + +No calls are made during printing, instead a (c) if printed after values which +are cached and potentially out of date""" + + def __init__(self): + super(LxClkSummary, self).__init__("lx-clk-summary", gdb.COMMAND_DATA) + + def show_subtree(self, clk, level): + gdb.write("%*s%-*s %7d %8d %8d %11lu%s\n" % ( + level * 3 + 1, "", + 30 - level * 3, + clk['name'].string(), + clk['enable_count'], + clk['prepare_count'], + clk['protect_count'], + clk['rate'], + '(c)' if clk['flags'] & constants.LX_CLK_GET_RATE_NOCACHE else ' ')) + + for child in clk_core_for_each_child(clk['children']): + self.show_subtree(child, level + 1) + + def invoke(self, arg, from_tty): + gdb.write(" enable prepare protect \n") + gdb.write(" clock count count count rate \n") + gdb.write("------------------------------------------------------------------------\n") + for clk in clk_core_for_each_child(gdb.parse_and_eval("clk_root_list")): + self.show_subtree(clk, 0) + for clk in clk_core_for_each_child(gdb.parse_and_eval("clk_orphan_list")): + self.show_subtree(clk, 0) + + +LxClkSummary() + + +class LxClkCoreLookup(gdb.Function): + """Find struct clk_core by name""" + + def __init__(self): + super(LxClkCoreLookup, self).__init__("lx_clk_core_lookup") + + def lookup_hlist(self, hlist_head, name): + for child in clk_core_for_each_child(hlist_head): + if child['name'].string() == name: + return child + result = self.lookup_hlist(child['children'], name) + if result: + return result + + def invoke(self, name): + name = name.string() + return (self.lookup_hlist(gdb.parse_and_eval("clk_root_list"), name) or + self.lookup_hlist(gdb.parse_and_eval("clk_orphan_list"), name)) + + +LxClkCoreLookup() diff --git a/src/net/scripts/gdb/linux/config.py b/src/net/scripts/gdb/linux/config.py new file mode 100644 index 0000000..8843ab3 --- /dev/null +++ b/src/net/scripts/gdb/linux/config.py @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Copyright 2019 Google LLC. + +import gdb +import zlib + +from linux import utils + + +class LxConfigDump(gdb.Command): + """Output kernel config to the filename specified as the command + argument. Equivalent to 'zcat /proc/config.gz > config.txt' on + a running target""" + + def __init__(self): + super(LxConfigDump, self).__init__("lx-configdump", gdb.COMMAND_DATA, + gdb.COMPLETE_FILENAME) + + def invoke(self, arg, from_tty): + if len(arg) == 0: + filename = "config.txt" + else: + filename = arg + + try: + py_config_ptr = gdb.parse_and_eval("&kernel_config_data") + py_config_ptr_end = gdb.parse_and_eval("&kernel_config_data_end") + py_config_size = py_config_ptr_end - py_config_ptr + except gdb.error as e: + raise gdb.GdbError("Can't find config, enable CONFIG_IKCONFIG?") + + inf = gdb.inferiors()[0] + zconfig_buf = utils.read_memoryview(inf, py_config_ptr, + py_config_size).tobytes() + + config_buf = zlib.decompress(zconfig_buf, 16) + with open(filename, 'wb') as f: + f.write(config_buf) + + gdb.write("Dumped config to " + filename + "\n") + + +LxConfigDump() diff --git a/src/net/scripts/gdb/linux/constants.py.in b/src/net/scripts/gdb/linux/constants.py.in new file mode 100644 index 0000000..2efbec6 --- /dev/null +++ b/src/net/scripts/gdb/linux/constants.py.in @@ -0,0 +1,77 @@ +/* + * gdb helper commands and functions for Linux kernel debugging + * + * Kernel constants derived from include files. + * + * Copyright (c) 2016 Linaro Ltd + * + * Authors: + * Kieran Bingham <kieran.bingham@linaro.org> + * + * This work is licensed under the terms of the GNU GPL version 2. + * + */ + +#include <linux/clk-provider.h> +#include <linux/fs.h> +#include <linux/hrtimer.h> +#include <linux/mount.h> +#include <linux/of_fdt.h> +#include <linux/threads.h> + +/* We need to stringify expanded macros so that they can be parsed */ + +#define STRING(x) #x +#define XSTRING(x) STRING(x) + +#define LX_VALUE(x) LX_##x = x +#define LX_GDBPARSED(x) LX_##x = gdb.parse_and_eval(XSTRING(x)) + +/* + * IS_ENABLED generates (a || b) which is not compatible with python + * We can only switch on configuration items we know are available + * Therefore - IS_BUILTIN() is more appropriate + */ +#define LX_CONFIG(x) LX_##x = IS_BUILTIN(x) + +/* The build system will take care of deleting everything above this marker */ +<!-- end-c-headers --> + +import gdb + +/* linux/clk-provider.h */ +if IS_BUILTIN(CONFIG_COMMON_CLK): + LX_GDBPARSED(CLK_GET_RATE_NOCACHE) + +/* linux/fs.h */ +LX_VALUE(SB_RDONLY) +LX_VALUE(SB_SYNCHRONOUS) +LX_VALUE(SB_MANDLOCK) +LX_VALUE(SB_DIRSYNC) +LX_VALUE(SB_NOATIME) +LX_VALUE(SB_NODIRATIME) + +/* linux/htimer.h */ +LX_GDBPARSED(hrtimer_resolution) + +/* linux/mount.h */ +LX_VALUE(MNT_NOSUID) +LX_VALUE(MNT_NODEV) +LX_VALUE(MNT_NOEXEC) +LX_VALUE(MNT_NOATIME) +LX_VALUE(MNT_NODIRATIME) +LX_VALUE(MNT_RELATIME) + +/* linux/threads.h */ +LX_VALUE(NR_CPUS) + +/* linux/of_fdt.h> */ +LX_VALUE(OF_DT_HEADER) + +/* Kernel Configs */ +LX_CONFIG(CONFIG_GENERIC_CLOCKEVENTS) +LX_CONFIG(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST) +LX_CONFIG(CONFIG_HIGH_RES_TIMERS) +LX_CONFIG(CONFIG_NR_CPUS) +LX_CONFIG(CONFIG_OF) +LX_CONFIG(CONFIG_TICK_ONESHOT) diff --git a/src/net/scripts/gdb/linux/cpus.py b/src/net/scripts/gdb/linux/cpus.py new file mode 100644 index 0000000..008e62f --- /dev/null +++ b/src/net/scripts/gdb/linux/cpus.py @@ -0,0 +1,174 @@ +# +# gdb helper commands and functions for Linux kernel debugging +# +# per-cpu tools +# +# Copyright (c) Siemens AG, 2011-2013 +# +# Authors: +# Jan Kiszka <jan.kiszka@siemens.com> +# +# This work is licensed under the terms of the GNU GPL version 2. +# + +import gdb + +from linux import tasks, utils + + +MAX_CPUS = 4096 + + +def get_current_cpu(): + if utils.get_gdbserver_type() == utils.GDBSERVER_QEMU: + return gdb.selected_thread().num - 1 + elif utils.get_gdbserver_type() == utils.GDBSERVER_KGDB: + tid = gdb.selected_thread().ptid[2] + if tid > (0x100000000 - MAX_CPUS - 2): + return 0x100000000 - tid - 2 + else: + return tasks.get_thread_info(tasks.get_task_by_pid(tid))['cpu'] + else: + raise gdb.GdbError("Sorry, obtaining the current CPU is not yet " + "supported with this gdb server.") + + +def per_cpu(var_ptr, cpu): + if cpu == -1: + cpu = get_current_cpu() + if utils.is_target_arch("sparc:v9"): + offset = gdb.parse_and_eval( + "trap_block[{0}].__per_cpu_base".format(str(cpu))) + else: + try: + offset = gdb.parse_and_eval( + "__per_cpu_offset[{0}]".format(str(cpu))) + except gdb.error: + # !CONFIG_SMP case + offset = 0 + pointer = var_ptr.cast(utils.get_long_type()) + offset + return pointer.cast(var_ptr.type).dereference() + + +cpu_mask = {} + + +def cpu_mask_invalidate(event): + global cpu_mask + cpu_mask = {} + gdb.events.stop.disconnect(cpu_mask_invalidate) + if hasattr(gdb.events, 'new_objfile'): + gdb.events.new_objfile.disconnect(cpu_mask_invalidate) + + +def cpu_list(mask_name): + global cpu_mask + mask = None + if mask_name in cpu_mask: + mask = cpu_mask[mask_name] + if mask is None: + mask = gdb.parse_and_eval(mask_name + ".bits") + if hasattr(gdb, 'events'): + cpu_mask[mask_name] = mask + gdb.events.stop.connect(cpu_mask_invalidate) + if hasattr(gdb.events, 'new_objfile'): + gdb.events.new_objfile.connect(cpu_mask_invalidate) + bits_per_entry = mask[0].type.sizeof * 8 + num_entries = mask.type.sizeof * 8 / bits_per_entry + entry = -1 + bits = 0 + + while True: + while bits == 0: + entry += 1 + if entry == num_entries: + return + bits = mask[entry] + if bits != 0: + bit = 0 + break + + while bits & 1 == 0: + bits >>= 1 + bit += 1 + + cpu = entry * bits_per_entry + bit + + bits >>= 1 + bit += 1 + + yield int(cpu) + + +def each_online_cpu(): + for cpu in cpu_list("__cpu_online_mask"): + yield cpu + + +def each_present_cpu(): + for cpu in cpu_list("__cpu_present_mask"): + yield cpu + + +def each_possible_cpu(): + for cpu in cpu_list("__cpu_possible_mask"): + yield cpu + + +def each_active_cpu(): + for cpu in cpu_list("__cpu_active_mask"): + yield cpu + + +class LxCpus(gdb.Command): + """List CPU status arrays + +Displays the known state of each CPU based on the kernel masks +and can help identify the state of hotplugged CPUs""" + + def __init__(self): + super(LxCpus, self).__init__("lx-cpus", gdb.COMMAND_DATA) + + def invoke(self, arg, from_tty): + gdb.write("Possible CPUs : {}\n".format(list(each_possible_cpu()))) + gdb.write("Present CPUs : {}\n".format(list(each_present_cpu()))) + gdb.write("Online CPUs : {}\n".format(list(each_online_cpu()))) + gdb.write("Active CPUs : {}\n".format(list(each_active_cpu()))) + + +LxCpus() + + +class PerCpu(gdb.Function): + """Return per-cpu variable. + +$lx_per_cpu("VAR"[, CPU]): Return the per-cpu variable called VAR for the +given CPU number. If CPU is omitted, the CPU of the current context is used. +Note that VAR has to be quoted as string.""" + + def __init__(self): + super(PerCpu, self).__init__("lx_per_cpu") + + def invoke(self, var_name, cpu=-1): + var_ptr = gdb.parse_and_eval("&" + var_name.string()) + return per_cpu(var_ptr, cpu) + + +PerCpu() + + +class LxCurrentFunc(gdb.Function): + """Return current task. + +$lx_current([CPU]): Return the per-cpu task variable for the given CPU +number. If CPU is omitted, the CPU of the current context is used.""" + + def __init__(self): + super(LxCurrentFunc, self).__init__("lx_current") + + def invoke(self, cpu=-1): + var_ptr = gdb.parse_and_eval("¤t_task") + return per_cpu(var_ptr, cpu).dereference() + + +LxCurrentFunc() diff --git a/src/net/scripts/gdb/linux/device.py b/src/net/scripts/gdb/linux/device.py new file mode 100644 index 0000000..16376c5 --- /dev/null +++ b/src/net/scripts/gdb/linux/device.py @@ -0,0 +1,182 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Copyright (c) NXP 2019 + +import gdb + +from linux.utils import CachedType +from linux.utils import container_of +from linux.lists import list_for_each_entry + + +device_private_type = CachedType('struct device_private') +device_type = CachedType('struct device') + +subsys_private_type = CachedType('struct subsys_private') +kobject_type = CachedType('struct kobject') +kset_type = CachedType('struct kset') + +bus_type = CachedType('struct bus_type') +class_type = CachedType('struct class') + + +def dev_name(dev): + dev_init_name = dev['init_name'] + if dev_init_name: + return dev_init_name.string() + return dev['kobj']['name'].string() + + +def kset_for_each_object(kset): + return list_for_each_entry(kset['list'], + kobject_type.get_type().pointer(), "entry") + + +def for_each_bus(): + for kobj in kset_for_each_object(gdb.parse_and_eval('bus_kset')): + subsys = container_of(kobj, kset_type.get_type().pointer(), 'kobj') + subsys_priv = container_of(subsys, subsys_private_type.get_type().pointer(), 'subsys') + yield subsys_priv['bus'] + + +def for_each_class(): + for kobj in kset_for_each_object(gdb.parse_and_eval('class_kset')): + subsys = container_of(kobj, kset_type.get_type().pointer(), 'kobj') + subsys_priv = container_of(subsys, subsys_private_type.get_type().pointer(), 'subsys') + yield subsys_priv['class'] + + +def get_bus_by_name(name): + for item in for_each_bus(): + if item['name'].string() == name: + return item + raise gdb.GdbError("Can't find bus type {!r}".format(name)) + + +def get_class_by_name(name): + for item in for_each_class(): + if item['name'].string() == name: + return item + raise gdb.GdbError("Can't find device class {!r}".format(name)) + + +klist_type = CachedType('struct klist') +klist_node_type = CachedType('struct klist_node') + + +def klist_for_each(klist): + return list_for_each_entry(klist['k_list'], + klist_node_type.get_type().pointer(), 'n_node') + + +def bus_for_each_device(bus): + for kn in klist_for_each(bus['p']['klist_devices']): + dp = container_of(kn, device_private_type.get_type().pointer(), 'knode_bus') + yield dp['device'] + + +def class_for_each_device(cls): + for kn in klist_for_each(cls['p']['klist_devices']): + dp = container_of(kn, device_private_type.get_type().pointer(), 'knode_class') + yield dp['device'] + + +def device_for_each_child(dev): + for kn in klist_for_each(dev['p']['klist_children']): + dp = container_of(kn, device_private_type.get_type().pointer(), 'knode_parent') + yield dp['device'] + + +def _show_device(dev, level=0, recursive=False): + gdb.write('{}dev {}:\t{}\n'.format('\t' * level, dev_name(dev), dev)) + if recursive: + for child in device_for_each_child(dev): + _show_device(child, level + 1, recursive) + + +class LxDeviceListBus(gdb.Command): + '''Print devices on a bus (or all buses if not specified)''' + + def __init__(self): + super(LxDeviceListBus, self).__init__('lx-device-list-bus', gdb.COMMAND_DATA) + + def invoke(self, arg, from_tty): + if not arg: + for bus in for_each_bus(): + gdb.write('bus {}:\t{}\n'.format(bus['name'].string(), bus)) + for dev in bus_for_each_device(bus): + _show_device(dev, level=1) + else: + bus = get_bus_by_name(arg) + if not bus: + raise gdb.GdbError("Can't find bus {!r}".format(arg)) + for dev in bus_for_each_device(bus): + _show_device(dev) + + +class LxDeviceListClass(gdb.Command): + '''Print devices in a class (or all classes if not specified)''' + + def __init__(self): + super(LxDeviceListClass, self).__init__('lx-device-list-class', gdb.COMMAND_DATA) + + def invoke(self, arg, from_tty): + if not arg: + for cls in for_each_class(): + gdb.write("class {}:\t{}\n".format(cls['name'].string(), cls)) + for dev in class_for_each_device(cls): + _show_device(dev, level=1) + else: + cls = get_class_by_name(arg) + for dev in class_for_each_device(cls): + _show_device(dev) + + +class LxDeviceListTree(gdb.Command): + '''Print a device and its children recursively''' + + def __init__(self): + super(LxDeviceListTree, self).__init__('lx-device-list-tree', gdb.COMMAND_DATA) + + def invoke(self, arg, from_tty): + if not arg: + raise gdb.GdbError('Please provide pointer to struct device') + dev = gdb.parse_and_eval(arg) + if dev.type != device_type.get_type().pointer(): + raise gdb.GdbError('Please provide pointer to struct device') + _show_device(dev, level=0, recursive=True) + + +class LxDeviceFindByBusName(gdb.Function): + '''Find struct device by bus and name (both strings)''' + + def __init__(self): + super(LxDeviceFindByBusName, self).__init__('lx_device_find_by_bus_name') + + def invoke(self, bus, name): + name = name.string() + bus = get_bus_by_name(bus.string()) + for dev in bus_for_each_device(bus): + if dev_name(dev) == name: + return dev + + +class LxDeviceFindByClassName(gdb.Function): + '''Find struct device by class and name (both strings)''' + + def __init__(self): + super(LxDeviceFindByClassName, self).__init__('lx_device_find_by_class_name') + + def invoke(self, cls, name): + name = name.string() + cls = get_class_by_name(cls.string()) + for dev in class_for_each_device(cls): + if dev_name(dev) == name: + return dev + + +LxDeviceListBus() +LxDeviceListClass() +LxDeviceListTree() +LxDeviceFindByBusName() +LxDeviceFindByClassName() diff --git a/src/net/scripts/gdb/linux/dmesg.py b/src/net/scripts/gdb/linux/dmesg.py new file mode 100644 index 0000000..a92c55b --- /dev/null +++ b/src/net/scripts/gdb/linux/dmesg.py @@ -0,0 +1,154 @@ +# +# gdb helper commands and functions for Linux kernel debugging +# +# kernel log buffer dump +# +# Copyright (c) Siemens AG, 2011, 2012 +# +# Authors: +# Jan Kiszka <jan.kiszka@siemens.com> +# +# This work is licensed under the terms of the GNU GPL version 2. +# + +import gdb +import sys + +from linux import utils + +printk_info_type = utils.CachedType("struct printk_info") +prb_data_blk_lpos_type = utils.CachedType("struct prb_data_blk_lpos") +prb_desc_type = utils.CachedType("struct prb_desc") +prb_desc_ring_type = utils.CachedType("struct prb_desc_ring") +prb_data_ring_type = utils.CachedType("struct prb_data_ring") +printk_ringbuffer_type = utils.CachedType("struct printk_ringbuffer") +atomic_long_type = utils.CachedType("atomic_long_t") + +class LxDmesg(gdb.Command): + """Print Linux kernel log buffer.""" + + def __init__(self): + super(LxDmesg, self).__init__("lx-dmesg", gdb.COMMAND_DATA) + + def invoke(self, arg, from_tty): + inf = gdb.inferiors()[0] + + # read in prb structure + prb_addr = int(str(gdb.parse_and_eval("(void *)'printk.c'::prb")).split()[0], 16) + sz = printk_ringbuffer_type.get_type().sizeof + prb = utils.read_memoryview(inf, prb_addr, sz).tobytes() + + # read in descriptor ring structure + off = printk_ringbuffer_type.get_type()['desc_ring'].bitpos // 8 + addr = prb_addr + off + sz = prb_desc_ring_type.get_type().sizeof + desc_ring = utils.read_memoryview(inf, addr, sz).tobytes() + + # read in descriptor array + off = prb_desc_ring_type.get_type()['count_bits'].bitpos // 8 + desc_ring_count = 1 << utils.read_u32(desc_ring, off) + desc_sz = prb_desc_type.get_type().sizeof + off = prb_desc_ring_type.get_type()['descs'].bitpos // 8 + addr = utils.read_ulong(desc_ring, off) + descs = utils.read_memoryview(inf, addr, desc_sz * desc_ring_count).tobytes() + + # read in info array + info_sz = printk_info_type.get_type().sizeof + off = prb_desc_ring_type.get_type()['infos'].bitpos // 8 + addr = utils.read_ulong(desc_ring, off) + infos = utils.read_memoryview(inf, addr, info_sz * desc_ring_count).tobytes() + + # read in text data ring structure + off = printk_ringbuffer_type.get_type()['text_data_ring'].bitpos // 8 + addr = prb_addr + off + sz = prb_data_ring_type.get_type().sizeof + text_data_ring = utils.read_memoryview(inf, addr, sz).tobytes() + + # read in text data + off = prb_data_ring_type.get_type()['size_bits'].bitpos // 8 + text_data_sz = 1 << utils.read_u32(text_data_ring, off) + off = prb_data_ring_type.get_type()['data'].bitpos // 8 + addr = utils.read_ulong(text_data_ring, off) + text_data = utils.read_memoryview(inf, addr, text_data_sz).tobytes() + + counter_off = atomic_long_type.get_type()['counter'].bitpos // 8 + + sv_off = prb_desc_type.get_type()['state_var'].bitpos // 8 + + off = prb_desc_type.get_type()['text_blk_lpos'].bitpos // 8 + begin_off = off + (prb_data_blk_lpos_type.get_type()['begin'].bitpos // 8) + next_off = off + (prb_data_blk_lpos_type.get_type()['next'].bitpos // 8) + + ts_off = printk_info_type.get_type()['ts_nsec'].bitpos // 8 + len_off = printk_info_type.get_type()['text_len'].bitpos // 8 + + # definitions from kernel/printk/printk_ringbuffer.h + desc_committed = 1 + desc_finalized = 2 + desc_sv_bits = utils.get_long_type().sizeof * 8 + desc_flags_shift = desc_sv_bits - 2 + desc_flags_mask = 3 << desc_flags_shift + desc_id_mask = ~desc_flags_mask + + # read in tail and head descriptor ids + off = prb_desc_ring_type.get_type()['tail_id'].bitpos // 8 + tail_id = utils.read_u64(desc_ring, off + counter_off) + off = prb_desc_ring_type.get_type()['head_id'].bitpos // 8 + head_id = utils.read_u64(desc_ring, off + counter_off) + + did = tail_id + while True: + ind = did % desc_ring_count + desc_off = desc_sz * ind + info_off = info_sz * ind + + # skip non-committed record + state = 3 & (utils.read_u64(descs, desc_off + sv_off + + counter_off) >> desc_flags_shift) + if state != desc_committed and state != desc_finalized: + if did == head_id: + break + did = (did + 1) & desc_id_mask + continue + + begin = utils.read_ulong(descs, desc_off + begin_off) % text_data_sz + end = utils.read_ulong(descs, desc_off + next_off) % text_data_sz + + # handle data-less record + if begin & 1 == 1: + text = "" + else: + # handle wrapping data block + if begin > end: + begin = 0 + + # skip over descriptor id + text_start = begin + utils.get_long_type().sizeof + + text_len = utils.read_u16(infos, info_off + len_off) + + # handle truncated message + if end - text_start < text_len: + text_len = end - text_start + + text = text_data[text_start:text_start + text_len].decode( + encoding='utf8', errors='replace') + + time_stamp = utils.read_u64(infos, info_off + ts_off) + + for line in text.splitlines(): + msg = u"[{time:12.6f}] {line}\n".format( + time=time_stamp / 1000000000.0, + line=line) + # With python2 gdb.write will attempt to convert unicode to + # ascii and might fail so pass an utf8-encoded str instead. + if sys.hexversion < 0x03000000: + msg = msg.encode(encoding='utf8', errors='replace') + gdb.write(msg) + + if did == head_id: + break + did = (did + 1) & desc_id_mask + + +LxDmesg() diff --git a/src/net/scripts/gdb/linux/genpd.py b/src/net/scripts/gdb/linux/genpd.py new file mode 100644 index 0000000..39cd1ab --- /dev/null +++ b/src/net/scripts/gdb/linux/genpd.py @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Copyright (c) NXP 2019 + +import gdb +import sys + +from linux.utils import CachedType +from linux.lists import list_for_each_entry + +generic_pm_domain_type = CachedType('struct generic_pm_domain') +pm_domain_data_type = CachedType('struct pm_domain_data') +device_link_type = CachedType('struct device_link') + + +def kobject_get_path(kobj): + path = kobj['name'].string() + parent = kobj['parent'] + if parent: + path = kobject_get_path(parent) + '/' + path + return path + + +def rtpm_status_str(dev): + if dev['power']['runtime_error']: + return 'error' + if dev['power']['disable_depth']: + return 'unsupported' + _RPM_STATUS_LOOKUP = [ + "active", + "resuming", + "suspended", + "suspending" + ] + return _RPM_STATUS_LOOKUP[dev['power']['runtime_status']] + + +class LxGenPDSummary(gdb.Command): + '''Print genpd summary + +Output is similar to /sys/kernel/debug/pm_genpd/pm_genpd_summary''' + + def __init__(self): + super(LxGenPDSummary, self).__init__('lx-genpd-summary', gdb.COMMAND_DATA) + + def summary_one(self, genpd): + if genpd['status'] == 0: + status_string = 'on' + else: + status_string = 'off-{}'.format(genpd['state_idx']) + + child_names = [] + for link in list_for_each_entry( + genpd['parent_links'], + device_link_type.get_type().pointer(), + 'parent_node'): + child_names.append(link['child']['name']) + + gdb.write('%-30s %-15s %s\n' % ( + genpd['name'].string(), + status_string, + ', '.join(child_names))) + + # Print devices in domain + for pm_data in list_for_each_entry(genpd['dev_list'], + pm_domain_data_type.get_type().pointer(), + 'list_node'): + dev = pm_data['dev'] + kobj_path = kobject_get_path(dev['kobj']) + gdb.write(' %-50s %s\n' % (kobj_path, rtpm_status_str(dev))) + + def invoke(self, arg, from_tty): + gdb.write('domain status children\n'); + gdb.write(' /device runtime status\n'); + gdb.write('----------------------------------------------------------------------\n'); + for genpd in list_for_each_entry( + gdb.parse_and_eval('&gpd_list'), + generic_pm_domain_type.get_type().pointer(), + 'gpd_list_node'): + self.summary_one(genpd) + + +LxGenPDSummary() diff --git a/src/net/scripts/gdb/linux/lists.py b/src/net/scripts/gdb/linux/lists.py new file mode 100644 index 0000000..c487ddf --- /dev/null +++ b/src/net/scripts/gdb/linux/lists.py @@ -0,0 +1,131 @@ +# +# gdb helper commands and functions for Linux kernel debugging +# +# list tools +# +# Copyright (c) Thiebaud Weksteen, 2015 +# +# Authors: +# Thiebaud Weksteen <thiebaud@weksteen.fr> +# +# This work is licensed under the terms of the GNU GPL version 2. +# + +import gdb + +from linux import utils + +list_head = utils.CachedType("struct list_head") +hlist_head = utils.CachedType("struct hlist_head") +hlist_node = utils.CachedType("struct hlist_node") + + +def list_for_each(head): + if head.type == list_head.get_type().pointer(): + head = head.dereference() + elif head.type != list_head.get_type(): + raise TypeError("Must be struct list_head not {}" + .format(head.type)) + + node = head['next'].dereference() + while node.address != head.address: + yield node.address + node = node['next'].dereference() + + +def list_for_each_entry(head, gdbtype, member): + for node in list_for_each(head): + yield utils.container_of(node, gdbtype, member) + + +def hlist_for_each(head): + if head.type == hlist_head.get_type().pointer(): + head = head.dereference() + elif head.type != hlist_head.get_type(): + raise TypeError("Must be struct hlist_head not {}" + .format(head.type)) + + node = head['first'].dereference() + while node.address: + yield node.address + node = node['next'].dereference() + + +def hlist_for_each_entry(head, gdbtype, member): + for node in hlist_for_each(head): + yield utils.container_of(node, gdbtype, member) + + +def list_check(head): + nb = 0 + if (head.type == list_head.get_type().pointer()): + head = head.dereference() + elif (head.type != list_head.get_type()): + raise gdb.GdbError('argument must be of type (struct list_head [*])') + c = head + try: + gdb.write("Starting with: {}\n".format(c)) + except gdb.MemoryError: + gdb.write('head is not accessible\n') + return + while True: + p = c['prev'].dereference() + n = c['next'].dereference() + try: + if p['next'] != c.address: + gdb.write('prev.next != current: ' + 'current@{current_addr}={current} ' + 'prev@{p_addr}={p}\n'.format( + current_addr=c.address, + current=c, + p_addr=p.address, + p=p, + )) + return + except gdb.MemoryError: + gdb.write('prev is not accessible: ' + 'current@{current_addr}={current}\n'.format( + current_addr=c.address, + current=c + )) + return + try: + if n['prev'] != c.address: + gdb.write('next.prev != current: ' + 'current@{current_addr}={current} ' + 'next@{n_addr}={n}\n'.format( + current_addr=c.address, + current=c, + n_addr=n.address, + n=n, + )) + return + except gdb.MemoryError: + gdb.write('next is not accessible: ' + 'current@{current_addr}={current}\n'.format( + current_addr=c.address, + current=c + )) + return + c = n + nb += 1 + if c == head: + gdb.write("list is consistent: {} node(s)\n".format(nb)) + return + + +class LxListChk(gdb.Command): + """Verify a list consistency""" + + def __init__(self): + super(LxListChk, self).__init__("lx-list-check", gdb.COMMAND_DATA, + gdb.COMPLETE_EXPRESSION) + + def invoke(self, arg, from_tty): + argv = gdb.string_to_argv(arg) + if len(argv) != 1: + raise gdb.GdbError("lx-list-check takes one argument") + list_check(gdb.parse_and_eval(argv[0])) + + +LxListChk() diff --git a/src/net/scripts/gdb/linux/modules.py b/src/net/scripts/gdb/linux/modules.py new file mode 100644 index 0000000..441b232 --- /dev/null +++ b/src/net/scripts/gdb/linux/modules.py @@ -0,0 +1,95 @@ +# +# gdb helper commands and functions for Linux kernel debugging +# +# module tools +# +# Copyright (c) Siemens AG, 2013 +# +# Authors: +# Jan Kiszka <jan.kiszka@siemens.com> +# +# This work is licensed under the terms of the GNU GPL version 2. +# + +import gdb + +from linux import cpus, utils, lists + + +module_type = utils.CachedType("struct module") + + +def module_list(): + global module_type + modules = utils.gdb_eval_or_none("modules") + if modules is None: + return + + module_ptr_type = module_type.get_type().pointer() + + for module in lists.list_for_each_entry(modules, module_ptr_type, "list"): + yield module + + +def find_module_by_name(name): + for module in module_list(): + if module['name'].string() == name: + return module + return None + + +class LxModule(gdb.Function): + """Find module by name and return the module variable. + +$lx_module("MODULE"): Given the name MODULE, iterate over all loaded modules +of the target and return that module variable which MODULE matches.""" + + def __init__(self): + super(LxModule, self).__init__("lx_module") + + def invoke(self, mod_name): + mod_name = mod_name.string() + module = find_module_by_name(mod_name) + if module: + return module.dereference() + else: + raise gdb.GdbError("Unable to find MODULE " + mod_name) + + +LxModule() + + +class LxLsmod(gdb.Command): + """List currently loaded modules.""" + + _module_use_type = utils.CachedType("struct module_use") + + def __init__(self): + super(LxLsmod, self).__init__("lx-lsmod", gdb.COMMAND_DATA) + + def invoke(self, arg, from_tty): + gdb.write( + "Address{0} Module Size Used by\n".format( + " " if utils.get_long_type().sizeof == 8 else "")) + + for module in module_list(): + layout = module['core_layout'] + gdb.write("{address} {name:<19} {size:>8} {ref}".format( + address=str(layout['base']).split()[0], + name=module['name'].string(), + size=str(layout['size']), + ref=str(module['refcnt']['counter'] - 1))) + + t = self._module_use_type.get_type().pointer() + first = True + sources = module['source_list'] + for use in lists.list_for_each_entry(sources, t, "source_list"): + gdb.write("{separator}{name}".format( + separator=" " if first else ",", + name=use['source']['name'].string())) + first = False + + gdb.write("\n") + + +LxLsmod() diff --git a/src/net/scripts/gdb/linux/proc.py b/src/net/scripts/gdb/linux/proc.py new file mode 100644 index 0000000..09cd871 --- /dev/null +++ b/src/net/scripts/gdb/linux/proc.py @@ -0,0 +1,275 @@ +# +# gdb helper commands and functions for Linux kernel debugging +# +# Kernel proc information reader +# +# Copyright (c) 2016 Linaro Ltd +# +# Authors: +# Kieran Bingham <kieran.bingham@linaro.org> +# +# This work is licensed under the terms of the GNU GPL version 2. +# + +import gdb +from linux import constants +from linux import utils +from linux import tasks +from linux import lists +from struct import * + + +class LxCmdLine(gdb.Command): + """ Report the Linux Commandline used in the current kernel. + Equivalent to cat /proc/cmdline on a running target""" + + def __init__(self): + super(LxCmdLine, self).__init__("lx-cmdline", gdb.COMMAND_DATA) + + def invoke(self, arg, from_tty): + gdb.write(gdb.parse_and_eval("saved_command_line").string() + "\n") + + +LxCmdLine() + + +class LxVersion(gdb.Command): + """ Report the Linux Version of the current kernel. + Equivalent to cat /proc/version on a running target""" + + def __init__(self): + super(LxVersion, self).__init__("lx-version", gdb.COMMAND_DATA) + + def invoke(self, arg, from_tty): + # linux_banner should contain a newline + gdb.write(gdb.parse_and_eval("(char *)linux_banner").string()) + + +LxVersion() + + +# Resource Structure Printers +# /proc/iomem +# /proc/ioports + +def get_resources(resource, depth): + while resource: + yield resource, depth + + child = resource['child'] + if child: + for res, deep in get_resources(child, depth + 1): + yield res, deep + + resource = resource['sibling'] + + +def show_lx_resources(resource_str): + resource = gdb.parse_and_eval(resource_str) + width = 4 if resource['end'] < 0x10000 else 8 + # Iterate straight to the first child + for res, depth in get_resources(resource['child'], 0): + start = int(res['start']) + end = int(res['end']) + gdb.write(" " * depth * 2 + + "{0:0{1}x}-".format(start, width) + + "{0:0{1}x} : ".format(end, width) + + res['name'].string() + "\n") + + +class LxIOMem(gdb.Command): + """Identify the IO memory resource locations defined by the kernel + +Equivalent to cat /proc/iomem on a running target""" + + def __init__(self): + super(LxIOMem, self).__init__("lx-iomem", gdb.COMMAND_DATA) + + def invoke(self, arg, from_tty): + return show_lx_resources("iomem_resource") + + +LxIOMem() + + +class LxIOPorts(gdb.Command): + """Identify the IO port resource locations defined by the kernel + +Equivalent to cat /proc/ioports on a running target""" + + def __init__(self): + super(LxIOPorts, self).__init__("lx-ioports", gdb.COMMAND_DATA) + + def invoke(self, arg, from_tty): + return show_lx_resources("ioport_resource") + + +LxIOPorts() + + +# Mount namespace viewer +# /proc/mounts + +def info_opts(lst, opt): + opts = "" + for key, string in lst.items(): + if opt & key: + opts += string + return opts + + +FS_INFO = {constants.LX_SB_SYNCHRONOUS: ",sync", + constants.LX_SB_MANDLOCK: ",mand", + constants.LX_SB_DIRSYNC: ",dirsync", + constants.LX_SB_NOATIME: ",noatime", + constants.LX_SB_NODIRATIME: ",nodiratime"} + +MNT_INFO = {constants.LX_MNT_NOSUID: ",nosuid", + constants.LX_MNT_NODEV: ",nodev", + constants.LX_MNT_NOEXEC: ",noexec", + constants.LX_MNT_NOATIME: ",noatime", + constants.LX_MNT_NODIRATIME: ",nodiratime", + constants.LX_MNT_RELATIME: ",relatime"} + +mount_type = utils.CachedType("struct mount") +mount_ptr_type = mount_type.get_type().pointer() + + +class LxMounts(gdb.Command): + """Report the VFS mounts of the current process namespace. + +Equivalent to cat /proc/mounts on a running target +An integer value can be supplied to display the mount +values of that process namespace""" + + def __init__(self): + super(LxMounts, self).__init__("lx-mounts", gdb.COMMAND_DATA) + + # Equivalent to proc_namespace.c:show_vfsmnt + # However, that has the ability to call into s_op functions + # whereas we cannot and must make do with the information we can obtain. + def invoke(self, arg, from_tty): + argv = gdb.string_to_argv(arg) + if len(argv) >= 1: + try: + pid = int(argv[0]) + except gdb.error: + raise gdb.GdbError("Provide a PID as integer value") + else: + pid = 1 + + task = tasks.get_task_by_pid(pid) + if not task: + raise gdb.GdbError("Couldn't find a process with PID {}" + .format(pid)) + + namespace = task['nsproxy']['mnt_ns'] + if not namespace: + raise gdb.GdbError("No namespace for current process") + + gdb.write("{:^18} {:^15} {:>9} {} {} options\n".format( + "mount", "super_block", "devname", "pathname", "fstype")) + + for vfs in lists.list_for_each_entry(namespace['list'], + mount_ptr_type, "mnt_list"): + devname = vfs['mnt_devname'].string() + devname = devname if devname else "none" + + pathname = "" + parent = vfs + while True: + mntpoint = parent['mnt_mountpoint'] + pathname = utils.dentry_name(mntpoint) + pathname + if (parent == parent['mnt_parent']): + break + parent = parent['mnt_parent'] + + if (pathname == ""): + pathname = "/" + + superblock = vfs['mnt']['mnt_sb'] + fstype = superblock['s_type']['name'].string() + s_flags = int(superblock['s_flags']) + m_flags = int(vfs['mnt']['mnt_flags']) + rd = "ro" if (s_flags & constants.LX_SB_RDONLY) else "rw" + + gdb.write("{} {} {} {} {} {}{}{} 0 0\n".format( + vfs.format_string(), superblock.format_string(), devname, + pathname, fstype, rd, info_opts(FS_INFO, s_flags), + info_opts(MNT_INFO, m_flags))) + + +LxMounts() + + +class LxFdtDump(gdb.Command): + """Output Flattened Device Tree header and dump FDT blob to the filename + specified as the command argument. Equivalent to + 'cat /proc/fdt > fdtdump.dtb' on a running target""" + + def __init__(self): + super(LxFdtDump, self).__init__("lx-fdtdump", gdb.COMMAND_DATA, + gdb.COMPLETE_FILENAME) + + def fdthdr_to_cpu(self, fdt_header): + + fdt_header_be = ">IIIIIII" + fdt_header_le = "<IIIIIII" + + if utils.get_target_endianness() == 1: + output_fmt = fdt_header_le + else: + output_fmt = fdt_header_be + + return unpack(output_fmt, pack(fdt_header_be, + fdt_header['magic'], + fdt_header['totalsize'], + fdt_header['off_dt_struct'], + fdt_header['off_dt_strings'], + fdt_header['off_mem_rsvmap'], + fdt_header['version'], + fdt_header['last_comp_version'])) + + def invoke(self, arg, from_tty): + + if not constants.LX_CONFIG_OF: + raise gdb.GdbError("Kernel not compiled with CONFIG_OF\n") + + if len(arg) == 0: + filename = "fdtdump.dtb" + else: + filename = arg + + py_fdt_header_ptr = gdb.parse_and_eval( + "(const struct fdt_header *) initial_boot_params") + py_fdt_header = py_fdt_header_ptr.dereference() + + fdt_header = self.fdthdr_to_cpu(py_fdt_header) + + if fdt_header[0] != constants.LX_OF_DT_HEADER: + raise gdb.GdbError("No flattened device tree magic found\n") + + gdb.write("fdt_magic: 0x{:02X}\n".format(fdt_header[0])) + gdb.write("fdt_totalsize: 0x{:02X}\n".format(fdt_header[1])) + gdb.write("off_dt_struct: 0x{:02X}\n".format(fdt_header[2])) + gdb.write("off_dt_strings: 0x{:02X}\n".format(fdt_header[3])) + gdb.write("off_mem_rsvmap: 0x{:02X}\n".format(fdt_header[4])) + gdb.write("version: {}\n".format(fdt_header[5])) + gdb.write("last_comp_version: {}\n".format(fdt_header[6])) + + inf = gdb.inferiors()[0] + fdt_buf = utils.read_memoryview(inf, py_fdt_header_ptr, + fdt_header[1]).tobytes() + + try: + f = open(filename, 'wb') + except gdb.error: + raise gdb.GdbError("Could not open file to dump fdt") + + f.write(fdt_buf) + f.close() + + gdb.write("Dumped fdt blob to " + filename + "\n") + + +LxFdtDump() diff --git a/src/net/scripts/gdb/linux/rbtree.py b/src/net/scripts/gdb/linux/rbtree.py new file mode 100644 index 0000000..fe46285 --- /dev/null +++ b/src/net/scripts/gdb/linux/rbtree.py @@ -0,0 +1,177 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Copyright 2019 Google LLC. + +import gdb + +from linux import utils + +rb_root_type = utils.CachedType("struct rb_root") +rb_node_type = utils.CachedType("struct rb_node") + + +def rb_first(root): + if root.type == rb_root_type.get_type(): + node = root.address.cast(rb_root_type.get_type().pointer()) + elif root.type != rb_root_type.get_type().pointer(): + raise gdb.GdbError("Must be struct rb_root not {}".format(root.type)) + + node = root['rb_node'] + if node == 0: + return None + + while node['rb_left']: + node = node['rb_left'] + + return node + + +def rb_last(root): + if root.type == rb_root_type.get_type(): + node = root.address.cast(rb_root_type.get_type().pointer()) + elif root.type != rb_root_type.get_type().pointer(): + raise gdb.GdbError("Must be struct rb_root not {}".format(root.type)) + + node = root['rb_node'] + if node == 0: + return None + + while node['rb_right']: + node = node['rb_right'] + + return node + + +def rb_parent(node): + parent = gdb.Value(node['__rb_parent_color'] & ~3) + return parent.cast(rb_node_type.get_type().pointer()) + + +def rb_empty_node(node): + return node['__rb_parent_color'] == node.address + + +def rb_next(node): + if node.type == rb_node_type.get_type(): + node = node.address.cast(rb_node_type.get_type().pointer()) + elif node.type != rb_node_type.get_type().pointer(): + raise gdb.GdbError("Must be struct rb_node not {}".format(node.type)) + + if rb_empty_node(node): + return None + + if node['rb_right']: + node = node['rb_right'] + while node['rb_left']: + node = node['rb_left'] + return node + + parent = rb_parent(node) + while parent and node == parent['rb_right']: + node = parent + parent = rb_parent(node) + + return parent + + +def rb_prev(node): + if node.type == rb_node_type.get_type(): + node = node.address.cast(rb_node_type.get_type().pointer()) + elif node.type != rb_node_type.get_type().pointer(): + raise gdb.GdbError("Must be struct rb_node not {}".format(node.type)) + + if rb_empty_node(node): + return None + + if node['rb_left']: + node = node['rb_left'] + while node['rb_right']: + node = node['rb_right'] + return node.dereference() + + parent = rb_parent(node) + while parent and node == parent['rb_left'].dereference(): + node = parent + parent = rb_parent(node) + + return parent + + +class LxRbFirst(gdb.Function): + """Lookup and return a node from an RBTree + +$lx_rb_first(root): Return the node at the given index. +If index is omitted, the root node is dereferenced and returned.""" + + def __init__(self): + super(LxRbFirst, self).__init__("lx_rb_first") + + def invoke(self, root): + result = rb_first(root) + if result is None: + raise gdb.GdbError("No entry in tree") + + return result + + +LxRbFirst() + + +class LxRbLast(gdb.Function): + """Lookup and return a node from an RBTree. + +$lx_rb_last(root): Return the node at the given index. +If index is omitted, the root node is dereferenced and returned.""" + + def __init__(self): + super(LxRbLast, self).__init__("lx_rb_last") + + def invoke(self, root): + result = rb_last(root) + if result is None: + raise gdb.GdbError("No entry in tree") + + return result + + +LxRbLast() + + +class LxRbNext(gdb.Function): + """Lookup and return a node from an RBTree. + +$lx_rb_next(node): Return the node at the given index. +If index is omitted, the root node is dereferenced and returned.""" + + def __init__(self): + super(LxRbNext, self).__init__("lx_rb_next") + + def invoke(self, node): + result = rb_next(node) + if result is None: + raise gdb.GdbError("No entry in tree") + + return result + + +LxRbNext() + + +class LxRbPrev(gdb.Function): + """Lookup and return a node from an RBTree. + +$lx_rb_prev(node): Return the node at the given index. +If index is omitted, the root node is dereferenced and returned.""" + + def __init__(self): + super(LxRbPrev, self).__init__("lx_rb_prev") + + def invoke(self, node): + result = rb_prev(node) + if result is None: + raise gdb.GdbError("No entry in tree") + + return result + + +LxRbPrev() diff --git a/src/net/scripts/gdb/linux/symbols.py b/src/net/scripts/gdb/linux/symbols.py new file mode 100644 index 0000000..1be9763 --- /dev/null +++ b/src/net/scripts/gdb/linux/symbols.py @@ -0,0 +1,187 @@ +# +# gdb helper commands and functions for Linux kernel debugging +# +# load kernel and module symbols +# +# Copyright (c) Siemens AG, 2011-2013 +# +# Authors: +# Jan Kiszka <jan.kiszka@siemens.com> +# +# This work is licensed under the terms of the GNU GPL version 2. +# + +import gdb +import os +import re + +from linux import modules, utils + + +if hasattr(gdb, 'Breakpoint'): + class LoadModuleBreakpoint(gdb.Breakpoint): + def __init__(self, spec, gdb_command): + super(LoadModuleBreakpoint, self).__init__(spec, internal=True) + self.silent = True + self.gdb_command = gdb_command + + def stop(self): + module = gdb.parse_and_eval("mod") + module_name = module['name'].string() + cmd = self.gdb_command + + # enforce update if object file is not found + cmd.module_files_updated = False + + # Disable pagination while reporting symbol (re-)loading. + # The console input is blocked in this context so that we would + # get stuck waiting for the user to acknowledge paged output. + show_pagination = gdb.execute("show pagination", to_string=True) + pagination = show_pagination.endswith("on.\n") + gdb.execute("set pagination off") + + if module_name in cmd.loaded_modules: + gdb.write("refreshing all symbols to reload module " + "'{0}'\n".format(module_name)) + cmd.load_all_symbols() + else: + cmd.load_module_symbols(module) + + # restore pagination state + gdb.execute("set pagination %s" % ("on" if pagination else "off")) + + return False + + +class LxSymbols(gdb.Command): + """(Re-)load symbols of Linux kernel and currently loaded modules. + +The kernel (vmlinux) is taken from the current working directly. Modules (.ko) +are scanned recursively, starting in the same directory. Optionally, the module +search path can be extended by a space separated list of paths passed to the +lx-symbols command.""" + + module_paths = [] + module_files = [] + module_files_updated = False + loaded_modules = [] + breakpoint = None + + def __init__(self): + super(LxSymbols, self).__init__("lx-symbols", gdb.COMMAND_FILES, + gdb.COMPLETE_FILENAME) + + def _update_module_files(self): + self.module_files = [] + for path in self.module_paths: + gdb.write("scanning for modules in {0}\n".format(path)) + for root, dirs, files in os.walk(path): + for name in files: + if name.endswith(".ko") or name.endswith(".ko.debug"): + self.module_files.append(root + "/" + name) + self.module_files_updated = True + + def _get_module_file(self, module_name): + module_pattern = ".*/{0}\.ko(?:.debug)?$".format( + module_name.replace("_", r"[_\-]")) + for name in self.module_files: + if re.match(module_pattern, name) and os.path.exists(name): + return name + return None + + def _section_arguments(self, module): + try: + sect_attrs = module['sect_attrs'].dereference() + except gdb.error: + return "" + attrs = sect_attrs['attrs'] + section_name_to_address = { + attrs[n]['battr']['attr']['name'].string(): attrs[n]['address'] + for n in range(int(sect_attrs['nsections']))} + args = [] + for section_name in [".data", ".data..read_mostly", ".rodata", ".bss", + ".text", ".text.hot", ".text.unlikely"]: + address = section_name_to_address.get(section_name) + if address: + args.append(" -s {name} {addr}".format( + name=section_name, addr=str(address))) + return "".join(args) + + def load_module_symbols(self, module): + module_name = module['name'].string() + module_addr = str(module['core_layout']['base']).split()[0] + + module_file = self._get_module_file(module_name) + if not module_file and not self.module_files_updated: + self._update_module_files() + module_file = self._get_module_file(module_name) + + if module_file: + if utils.is_target_arch('s390'): + # Module text is preceded by PLT stubs on s390. + module_arch = module['arch'] + plt_offset = int(module_arch['plt_offset']) + plt_size = int(module_arch['plt_size']) + module_addr = hex(int(module_addr, 0) + plt_offset + plt_size) + gdb.write("loading @{addr}: {filename}\n".format( + addr=module_addr, filename=module_file)) + cmdline = "add-symbol-file {filename} {addr}{sections}".format( + filename=module_file, + addr=module_addr, + sections=self._section_arguments(module)) + gdb.execute(cmdline, to_string=True) + if module_name not in self.loaded_modules: + self.loaded_modules.append(module_name) + else: + gdb.write("no module object found for '{0}'\n".format(module_name)) + + def load_all_symbols(self): + gdb.write("loading vmlinux\n") + + # Dropping symbols will disable all breakpoints. So save their states + # and restore them afterward. + saved_states = [] + if hasattr(gdb, 'breakpoints') and not gdb.breakpoints() is None: + for bp in gdb.breakpoints(): + saved_states.append({'breakpoint': bp, 'enabled': bp.enabled}) + + # drop all current symbols and reload vmlinux + orig_vmlinux = 'vmlinux' + for obj in gdb.objfiles(): + if obj.filename.endswith('vmlinux'): + orig_vmlinux = obj.filename + gdb.execute("symbol-file", to_string=True) + gdb.execute("symbol-file {0}".format(orig_vmlinux)) + + self.loaded_modules = [] + module_list = modules.module_list() + if not module_list: + gdb.write("no modules found\n") + else: + [self.load_module_symbols(module) for module in module_list] + + for saved_state in saved_states: + saved_state['breakpoint'].enabled = saved_state['enabled'] + + def invoke(self, arg, from_tty): + self.module_paths = [os.path.expanduser(p) for p in arg.split()] + self.module_paths.append(os.getcwd()) + + # enforce update + self.module_files = [] + self.module_files_updated = False + + self.load_all_symbols() + + if hasattr(gdb, 'Breakpoint'): + if self.breakpoint is not None: + self.breakpoint.delete() + self.breakpoint = None + self.breakpoint = LoadModuleBreakpoint( + "kernel/module.c:do_init_module", self) + else: + gdb.write("Note: symbol update on module loading not supported " + "with this gdb version\n") + + +LxSymbols() diff --git a/src/net/scripts/gdb/linux/tasks.py b/src/net/scripts/gdb/linux/tasks.py new file mode 100644 index 0000000..17ec19e --- /dev/null +++ b/src/net/scripts/gdb/linux/tasks.py @@ -0,0 +1,140 @@ +# +# gdb helper commands and functions for Linux kernel debugging +# +# task & thread tools +# +# Copyright (c) Siemens AG, 2011-2013 +# +# Authors: +# Jan Kiszka <jan.kiszka@siemens.com> +# +# This work is licensed under the terms of the GNU GPL version 2. +# + +import gdb + +from linux import utils + + +task_type = utils.CachedType("struct task_struct") + + +def task_lists(): + task_ptr_type = task_type.get_type().pointer() + init_task = gdb.parse_and_eval("init_task").address + t = g = init_task + + while True: + while True: + yield t + + t = utils.container_of(t['thread_group']['next'], + task_ptr_type, "thread_group") + if t == g: + break + + t = g = utils.container_of(g['tasks']['next'], + task_ptr_type, "tasks") + if t == init_task: + return + + +def get_task_by_pid(pid): + for task in task_lists(): + if int(task['pid']) == pid: + return task + return None + + +class LxTaskByPidFunc(gdb.Function): + """Find Linux task by PID and return the task_struct variable. + +$lx_task_by_pid(PID): Given PID, iterate over all tasks of the target and +return that task_struct variable which PID matches.""" + + def __init__(self): + super(LxTaskByPidFunc, self).__init__("lx_task_by_pid") + + def invoke(self, pid): + task = get_task_by_pid(pid) + if task: + return task.dereference() + else: + raise gdb.GdbError("No task of PID " + str(pid)) + + +LxTaskByPidFunc() + + +class LxPs(gdb.Command): + """Dump Linux tasks.""" + + def __init__(self): + super(LxPs, self).__init__("lx-ps", gdb.COMMAND_DATA) + + def invoke(self, arg, from_tty): + gdb.write("{:>10} {:>12} {:>7}\n".format("TASK", "PID", "COMM")) + for task in task_lists(): + gdb.write("{} {:^5} {}\n".format( + task.format_string().split()[0], + task["pid"].format_string(), + task["comm"].string())) + + +LxPs() + + +thread_info_type = utils.CachedType("struct thread_info") + +ia64_task_size = None + + +def get_thread_info(task): + thread_info_ptr_type = thread_info_type.get_type().pointer() + if utils.is_target_arch("ia64"): + global ia64_task_size + if ia64_task_size is None: + ia64_task_size = gdb.parse_and_eval("sizeof(struct task_struct)") + thread_info_addr = task.address + ia64_task_size + thread_info = thread_info_addr.cast(thread_info_ptr_type) + else: + if task.type.fields()[0].type == thread_info_type.get_type(): + return task['thread_info'] + thread_info = task['stack'].cast(thread_info_ptr_type) + return thread_info.dereference() + + +class LxThreadInfoFunc (gdb.Function): + """Calculate Linux thread_info from task variable. + +$lx_thread_info(TASK): Given TASK, return the corresponding thread_info +variable.""" + + def __init__(self): + super(LxThreadInfoFunc, self).__init__("lx_thread_info") + + def invoke(self, task): + return get_thread_info(task) + + +LxThreadInfoFunc() + + +class LxThreadInfoByPidFunc (gdb.Function): + """Calculate Linux thread_info from task variable found by pid + +$lx_thread_info_by_pid(PID): Given PID, return the corresponding thread_info +variable.""" + + def __init__(self): + super(LxThreadInfoByPidFunc, self).__init__("lx_thread_info_by_pid") + + def invoke(self, pid): + task = get_task_by_pid(pid) + if task: + return get_thread_info(task.dereference()) + else: + raise gdb.GdbError("No task of PID " + str(pid)) + + +LxThreadInfoByPidFunc() diff --git a/src/net/scripts/gdb/linux/timerlist.py b/src/net/scripts/gdb/linux/timerlist.py new file mode 100644 index 0000000..071d0dd --- /dev/null +++ b/src/net/scripts/gdb/linux/timerlist.py @@ -0,0 +1,219 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Copyright 2019 Google LLC. + +import binascii +import gdb + +from linux import constants +from linux import cpus +from linux import rbtree +from linux import utils + +timerqueue_node_type = utils.CachedType("struct timerqueue_node").get_type() +hrtimer_type = utils.CachedType("struct hrtimer").get_type() + + +def ktime_get(): + """Returns the current time, but not very accurately + + We can't read the hardware timer itself to add any nanoseconds + that need to be added since we last stored the time in the + timekeeper. But this is probably good enough for debug purposes.""" + tk_core = gdb.parse_and_eval("&tk_core") + + return tk_core['timekeeper']['tkr_mono']['base'] + + +def print_timer(rb_node, idx): + timerqueue = utils.container_of(rb_node, timerqueue_node_type.pointer(), + "node") + timer = utils.container_of(timerqueue, hrtimer_type.pointer(), "node") + + function = str(timer['function']).split(" ")[1].strip("<>") + softexpires = timer['_softexpires'] + expires = timer['node']['expires'] + now = ktime_get() + + text = " #{}: <{}>, {}, ".format(idx, timer, function) + text += "S:{:02x}\n".format(int(timer['state'])) + text += " # expires at {}-{} nsecs [in {} to {} nsecs]\n".format( + softexpires, expires, softexpires - now, expires - now) + return text + + +def print_active_timers(base): + curr = base['active']['next']['node'] + curr = curr.address.cast(rbtree.rb_node_type.get_type().pointer()) + idx = 0 + while curr: + yield print_timer(curr, idx) + curr = rbtree.rb_next(curr) + idx += 1 + + +def print_base(base): + text = " .base: {}\n".format(base.address) + text += " .index: {}\n".format(base['index']) + + text += " .resolution: {} nsecs\n".format(constants.LX_hrtimer_resolution) + + text += " .get_time: {}\n".format(base['get_time']) + if constants.LX_CONFIG_HIGH_RES_TIMERS: + text += " .offset: {} nsecs\n".format(base['offset']) + text += "active timers:\n" + text += "".join([x for x in print_active_timers(base)]) + return text + + +def print_cpu(hrtimer_bases, cpu, max_clock_bases): + cpu_base = cpus.per_cpu(hrtimer_bases, cpu) + jiffies = gdb.parse_and_eval("jiffies_64") + tick_sched_ptr = gdb.parse_and_eval("&tick_cpu_sched") + ts = cpus.per_cpu(tick_sched_ptr, cpu) + + text = "cpu: {}\n".format(cpu) + for i in xrange(max_clock_bases): + text += " clock {}:\n".format(i) + text += print_base(cpu_base['clock_base'][i]) + + if constants.LX_CONFIG_HIGH_RES_TIMERS: + fmts = [(" .{} : {} nsecs", 'expires_next'), + (" .{} : {}", 'hres_active'), + (" .{} : {}", 'nr_events'), + (" .{} : {}", 'nr_retries'), + (" .{} : {}", 'nr_hangs'), + (" .{} : {}", 'max_hang_time')] + text += "\n".join([s.format(f, cpu_base[f]) for s, f in fmts]) + text += "\n" + + if constants.LX_CONFIG_TICK_ONESHOT: + fmts = [(" .{} : {}", 'nohz_mode'), + (" .{} : {} nsecs", 'last_tick'), + (" .{} : {}", 'tick_stopped'), + (" .{} : {}", 'idle_jiffies'), + (" .{} : {}", 'idle_calls'), + (" .{} : {}", 'idle_sleeps'), + (" .{} : {} nsecs", 'idle_entrytime'), + (" .{} : {} nsecs", 'idle_waketime'), + (" .{} : {} nsecs", 'idle_exittime'), + (" .{} : {} nsecs", 'idle_sleeptime'), + (" .{}: {} nsecs", 'iowait_sleeptime'), + (" .{} : {}", 'last_jiffies'), + (" .{} : {}", 'next_timer'), + (" .{} : {} nsecs", 'idle_expires')] + text += "\n".join([s.format(f, ts[f]) for s, f in fmts]) + text += "\njiffies: {}\n".format(jiffies) + + text += "\n" + + return text + + +def print_tickdevice(td, cpu): + dev = td['evtdev'] + text = "Tick Device: mode: {}\n".format(td['mode']) + if cpu < 0: + text += "Broadcast device\n" + else: + text += "Per CPU device: {}\n".format(cpu) + + text += "Clock Event Device: " + if dev == 0: + text += "<NULL>\n" + return text + + text += "{}\n".format(dev['name']) + text += " max_delta_ns: {}\n".format(dev['max_delta_ns']) + text += " min_delta_ns: {}\n".format(dev['min_delta_ns']) + text += " mult: {}\n".format(dev['mult']) + text += " shift: {}\n".format(dev['shift']) + text += " mode: {}\n".format(dev['state_use_accessors']) + text += " next_event: {} nsecs\n".format(dev['next_event']) + + text += " set_next_event: {}\n".format(dev['set_next_event']) + + members = [('set_state_shutdown', " shutdown: {}\n"), + ('set_state_periodic', " periodic: {}\n"), + ('set_state_oneshot', " oneshot: {}\n"), + ('set_state_oneshot_stopped', " oneshot stopped: {}\n"), + ('tick_resume', " resume: {}\n")] + for member, fmt in members: + if dev[member]: + text += fmt.format(dev[member]) + + text += " event_handler: {}\n".format(dev['event_handler']) + text += " retries: {}\n".format(dev['retries']) + + return text + + +def pr_cpumask(mask): + nr_cpu_ids = 1 + if constants.LX_NR_CPUS > 1: + nr_cpu_ids = gdb.parse_and_eval("nr_cpu_ids") + + inf = gdb.inferiors()[0] + bits = mask['bits'] + num_bytes = (nr_cpu_ids + 7) / 8 + buf = utils.read_memoryview(inf, bits, num_bytes).tobytes() + buf = binascii.b2a_hex(buf) + + chunks = [] + i = num_bytes + while i > 0: + i -= 1 + start = i * 2 + end = start + 2 + chunks.append(buf[start:end]) + if i != 0 and i % 4 == 0: + chunks.append(',') + + extra = nr_cpu_ids % 8 + if 0 < extra <= 4: + chunks[0] = chunks[0][0] # Cut off the first 0 + + return "".join(chunks) + + +class LxTimerList(gdb.Command): + """Print /proc/timer_list""" + + def __init__(self): + super(LxTimerList, self).__init__("lx-timerlist", gdb.COMMAND_DATA) + + def invoke(self, arg, from_tty): + hrtimer_bases = gdb.parse_and_eval("&hrtimer_bases") + max_clock_bases = gdb.parse_and_eval("HRTIMER_MAX_CLOCK_BASES") + + text = "Timer List Version: gdb scripts\n" + text += "HRTIMER_MAX_CLOCK_BASES: {}\n".format(max_clock_bases) + text += "now at {} nsecs\n".format(ktime_get()) + + for cpu in cpus.each_online_cpu(): + text += print_cpu(hrtimer_bases, cpu, max_clock_bases) + + if constants.LX_CONFIG_GENERIC_CLOCKEVENTS: + if constants.LX_CONFIG_GENERIC_CLOCKEVENTS_BROADCAST: + bc_dev = gdb.parse_and_eval("&tick_broadcast_device") + text += print_tickdevice(bc_dev, -1) + text += "\n" + mask = gdb.parse_and_eval("tick_broadcast_mask") + mask = pr_cpumask(mask) + text += "tick_broadcast_mask: {}\n".format(mask) + if constants.LX_CONFIG_TICK_ONESHOT: + mask = gdb.parse_and_eval("tick_broadcast_oneshot_mask") + mask = pr_cpumask(mask) + text += "tick_broadcast_oneshot_mask: {}\n".format(mask) + text += "\n" + + tick_cpu_devices = gdb.parse_and_eval("&tick_cpu_device") + for cpu in cpus.each_online_cpu(): + tick_dev = cpus.per_cpu(tick_cpu_devices, cpu) + text += print_tickdevice(tick_dev, cpu) + text += "\n" + + gdb.write(text) + + +LxTimerList() diff --git a/src/net/scripts/gdb/linux/utils.py b/src/net/scripts/gdb/linux/utils.py new file mode 100644 index 0000000..ff7c179 --- /dev/null +++ b/src/net/scripts/gdb/linux/utils.py @@ -0,0 +1,193 @@ +# +# gdb helper commands and functions for Linux kernel debugging +# +# common utilities +# +# Copyright (c) Siemens AG, 2011-2013 +# +# Authors: +# Jan Kiszka <jan.kiszka@siemens.com> +# +# This work is licensed under the terms of the GNU GPL version 2. +# + +import gdb + + +class CachedType: + def __init__(self, name): + self._type = None + self._name = name + + def _new_objfile_handler(self, event): + self._type = None + gdb.events.new_objfile.disconnect(self._new_objfile_handler) + + def get_type(self): + if self._type is None: + self._type = gdb.lookup_type(self._name) + if self._type is None: + raise gdb.GdbError( + "cannot resolve type '{0}'".format(self._name)) + if hasattr(gdb, 'events') and hasattr(gdb.events, 'new_objfile'): + gdb.events.new_objfile.connect(self._new_objfile_handler) + return self._type + + +long_type = CachedType("long") + + +def get_long_type(): + global long_type + return long_type.get_type() + + +def offset_of(typeobj, field): + element = gdb.Value(0).cast(typeobj) + return int(str(element[field].address).split()[0], 16) + + +def container_of(ptr, typeobj, member): + return (ptr.cast(get_long_type()) - + offset_of(typeobj, member)).cast(typeobj) + + +class ContainerOf(gdb.Function): + """Return pointer to containing data structure. + +$container_of(PTR, "TYPE", "ELEMENT"): Given PTR, return a pointer to the +data structure of the type TYPE in which PTR is the address of ELEMENT. +Note that TYPE and ELEMENT have to be quoted as strings.""" + + def __init__(self): + super(ContainerOf, self).__init__("container_of") + + def invoke(self, ptr, typename, elementname): + return container_of(ptr, gdb.lookup_type(typename.string()).pointer(), + elementname.string()) + + +ContainerOf() + + +BIG_ENDIAN = 0 +LITTLE_ENDIAN = 1 +target_endianness = None + + +def get_target_endianness(): + global target_endianness + if target_endianness is None: + endian = gdb.execute("show endian", to_string=True) + if "little endian" in endian: + target_endianness = LITTLE_ENDIAN + elif "big endian" in endian: + target_endianness = BIG_ENDIAN + else: + raise gdb.GdbError("unknown endianness '{0}'".format(str(endian))) + return target_endianness + + +def read_memoryview(inf, start, length): + return memoryview(inf.read_memory(start, length)) + + +def read_u16(buffer, offset): + buffer_val = buffer[offset:offset + 2] + value = [0, 0] + + if type(buffer_val[0]) is str: + value[0] = ord(buffer_val[0]) + value[1] = ord(buffer_val[1]) + else: + value[0] = buffer_val[0] + value[1] = buffer_val[1] + + if get_target_endianness() == LITTLE_ENDIAN: + return value[0] + (value[1] << 8) + else: + return value[1] + (value[0] << 8) + + +def read_u32(buffer, offset): + if get_target_endianness() == LITTLE_ENDIAN: + return read_u16(buffer, offset) + (read_u16(buffer, offset + 2) << 16) + else: + return read_u16(buffer, offset + 2) + (read_u16(buffer, offset) << 16) + + +def read_u64(buffer, offset): + if get_target_endianness() == LITTLE_ENDIAN: + return read_u32(buffer, offset) + (read_u32(buffer, offset + 4) << 32) + else: + return read_u32(buffer, offset + 4) + (read_u32(buffer, offset) << 32) + + +def read_ulong(buffer, offset): + if get_long_type().sizeof == 8: + return read_u64(buffer, offset) + else: + return read_u32(buffer, offset) + + +target_arch = None + + +def is_target_arch(arch): + if hasattr(gdb.Frame, 'architecture'): + return arch in gdb.newest_frame().architecture().name() + else: + global target_arch + if target_arch is None: + target_arch = gdb.execute("show architecture", to_string=True) + return arch in target_arch + + +GDBSERVER_QEMU = 0 +GDBSERVER_KGDB = 1 +gdbserver_type = None + + +def get_gdbserver_type(): + def exit_handler(event): + global gdbserver_type + gdbserver_type = None + gdb.events.exited.disconnect(exit_handler) + + def probe_qemu(): + try: + return gdb.execute("monitor info version", to_string=True) != "" + except gdb.error: + return False + + def probe_kgdb(): + try: + thread_info = gdb.execute("info thread 2", to_string=True) + return "shadowCPU0" in thread_info + except gdb.error: + return False + + global gdbserver_type + if gdbserver_type is None: + if probe_qemu(): + gdbserver_type = GDBSERVER_QEMU + elif probe_kgdb(): + gdbserver_type = GDBSERVER_KGDB + if gdbserver_type is not None and hasattr(gdb, 'events'): + gdb.events.exited.connect(exit_handler) + return gdbserver_type + + +def gdb_eval_or_none(expresssion): + try: + return gdb.parse_and_eval(expresssion) + except gdb.error: + return None + + +def dentry_name(d): + parent = d['d_parent'] + if parent == d or parent == 0: + return "" + p = dentry_name(d['d_parent']) + "/" + return p + d['d_iname'].string() diff --git a/src/net/scripts/gdb/vmlinux-gdb.py b/src/net/scripts/gdb/vmlinux-gdb.py new file mode 100644 index 0000000..4136dc2 --- /dev/null +++ b/src/net/scripts/gdb/vmlinux-gdb.py @@ -0,0 +1,39 @@ +# +# gdb helper commands and functions for Linux kernel debugging +# +# loader module +# +# Copyright (c) Siemens AG, 2012, 2013 +# +# Authors: +# Jan Kiszka <jan.kiszka@siemens.com> +# +# This work is licensed under the terms of the GNU GPL version 2. +# + +import os + +sys.path.insert(0, os.path.dirname(__file__) + "/scripts/gdb") + +try: + gdb.parse_and_eval("0") + gdb.execute("", to_string=True) +except: + gdb.write("NOTE: gdb 7.2 or later required for Linux helper scripts to " + "work.\n") +else: + import linux.utils + import linux.symbols + import linux.modules + import linux.dmesg + import linux.tasks + import linux.config + import linux.cpus + import linux.lists + import linux.rbtree + import linux.proc + import linux.constants + import linux.timerlist + import linux.clk + import linux.genpd + import linux.device diff --git a/src/net/scripts/gen_autoksyms.sh b/src/net/scripts/gen_autoksyms.sh new file mode 100755 index 0000000..d54dfba --- /dev/null +++ b/src/net/scripts/gen_autoksyms.sh @@ -0,0 +1,55 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0-only + +# Create an autoksyms.h header file from the list of all module's needed symbols +# as recorded on the second line of *.mod files and the user-provided symbol +# whitelist. + +set -e + +output_file="$1" + +# Use "make V=1" to debug this script. +case "$KBUILD_VERBOSE" in +*1*) + set -x + ;; +esac + +# We need access to CONFIG_ symbols +. include/config/auto.conf + +ksym_wl=/dev/null +if [ -n "$CONFIG_UNUSED_KSYMS_WHITELIST" ]; then + # Use 'eval' to expand the whitelist path and check if it is relative + eval ksym_wl="$CONFIG_UNUSED_KSYMS_WHITELIST" + [ "${ksym_wl}" != "${ksym_wl#/}" ] || ksym_wl="$abs_srctree/$ksym_wl" + if [ ! -f "$ksym_wl" ] || [ ! -r "$ksym_wl" ]; then + echo "ERROR: '$ksym_wl' whitelist file not found" >&2 + exit 1 + fi +fi + +# Generate a new ksym list file with symbols needed by the current +# set of modules. +cat > "$output_file" << EOT +/* + * Automatically generated file; DO NOT EDIT. + */ + +EOT + +[ -f modules.order ] && modlist=modules.order || modlist=/dev/null +sed 's/ko$/mod/' $modlist | +xargs -n1 sed -n -e '2{s/ /\n/g;/^$/!p;}' -- | +cat - "$ksym_wl" | +# Remove the dot prefix for ppc64; symbol names with a dot (.) hold entry +# point addresses. +sed -e 's/^\.//' | +sort -u | +sed -e 's/\(.*\)/#define __KSYM_\1 1/' >> "$output_file" + +# Special case for modversions (see modpost.c) +if [ -n "$CONFIG_MODVERSIONS" ]; then + echo "#define __KSYM_module_layout 1" >> "$output_file" +fi diff --git a/src/net/scripts/gen_ksymdeps.sh b/src/net/scripts/gen_ksymdeps.sh new file mode 100755 index 0000000..725e8c9 --- /dev/null +++ b/src/net/scripts/gen_ksymdeps.sh @@ -0,0 +1,31 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0 + +set -e + +# List of exported symbols +# +# If the object has no symbol, $NM warns 'no symbols'. +# Suppress the stderr. +# TODO: +# Use -q instead of 2>/dev/null when we upgrade the minimum version of +# binutils to 2.37, llvm to 13.0.0. +ksyms=$($NM $1 2>/dev/null | sed -n 's/.*__ksym_marker_\(.*\)/\1/p' | tr A-Z a-z) + +if [ -z "$ksyms" ]; then + exit 0 +fi + +echo +echo "ksymdeps_$1 := \\" + +for s in $ksyms +do + echo $s | sed -e 's:^_*: $(wildcard include/ksym/:' \ + -e 's:__*:/:g' -e 's/$/.h) \\/' +done + +echo +echo "$1: \$(ksymdeps_$1)" +echo +echo "\$(ksymdeps_$1):" diff --git a/src/net/scripts/genksyms/.gitignore b/src/net/scripts/genksyms/.gitignore new file mode 100644 index 0000000..999af71 --- /dev/null +++ b/src/net/scripts/genksyms/.gitignore @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +genksyms diff --git a/src/net/scripts/genksyms/Makefile b/src/net/scripts/genksyms/Makefile new file mode 100644 index 0000000..ce4f999 --- /dev/null +++ b/src/net/scripts/genksyms/Makefile @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: GPL-2.0 + +hostprogs-always-y += genksyms + +genksyms-objs := genksyms.o parse.tab.o lex.lex.o + +# FIXME: fix the ambiguous grammar in parse.y and delete this hack +# +# Suppress shift/reduce, reduce/reduce conflicts warnings +# unless W=1 is specified. +# +# Just in case, run "$(YACC) --version" without suppressing stderr +# so that 'bison: not found' will be displayed if it is missing. +ifeq ($(findstring 1,$(KBUILD_EXTRA_WARN)),) + +quiet_cmd_bison_no_warn = $(quiet_cmd_bison) + cmd_bison_no_warn = $(YACC) --version >/dev/null; \ + $(cmd_bison) 2>/dev/null + +$(obj)/pars%.tab.c $(obj)/pars%.tab.h: $(src)/pars%.y FORCE + $(call if_changed,bison_no_warn) + +endif + +# -I needed for generated C source (shipped source) +HOSTCFLAGS_parse.tab.o := -I $(srctree)/$(src) +HOSTCFLAGS_lex.lex.o := -I $(srctree)/$(src) + +# dependencies on generated files need to be listed explicitly +$(obj)/lex.lex.o: $(obj)/parse.tab.h diff --git a/src/net/scripts/genksyms/genksyms.c b/src/net/scripts/genksyms/genksyms.c new file mode 100644 index 0000000..23eff23 --- /dev/null +++ b/src/net/scripts/genksyms/genksyms.c @@ -0,0 +1,873 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* Generate kernel symbol version hashes. + Copyright 1996, 1997 Linux International. + + New implementation contributed by Richard Henderson <rth@tamu.edu> + Based on original work by Bjorn Ekwall <bj0rn@blox.se> + + This file was part of the Linux modutils 2.4.22: moved back into the + kernel sources by Rusty Russell/Kai Germaschewski. + + */ + +#include <stdio.h> +#include <string.h> +#include <stdlib.h> +#include <unistd.h> +#include <assert.h> +#include <stdarg.h> +#ifdef __GNU_LIBRARY__ +#include <getopt.h> +#endif /* __GNU_LIBRARY__ */ + +#include "genksyms.h" +/*----------------------------------------------------------------------*/ + +#define HASH_BUCKETS 4096 + +static struct symbol *symtab[HASH_BUCKETS]; +static FILE *debugfile; + +int cur_line = 1; +char *cur_filename, *source_file; +int in_source_file; + +static int flag_debug, flag_dump_defs, flag_reference, flag_dump_types, + flag_preserve, flag_warnings, flag_rel_crcs; + +static int errors; +static int nsyms; + +static struct symbol *expansion_trail; +static struct symbol *visited_symbols; + +static const struct { + int n; + const char *name; +} symbol_types[] = { + [SYM_NORMAL] = { 0, NULL}, + [SYM_TYPEDEF] = {'t', "typedef"}, + [SYM_ENUM] = {'e', "enum"}, + [SYM_STRUCT] = {'s', "struct"}, + [SYM_UNION] = {'u', "union"}, + [SYM_ENUM_CONST] = {'E', "enum constant"}, +}; + +static int equal_list(struct string_list *a, struct string_list *b); +static void print_list(FILE * f, struct string_list *list); +static struct string_list *concat_list(struct string_list *start, ...); +static struct string_list *mk_node(const char *string); +static void print_location(void); +static void print_type_name(enum symbol_type type, const char *name); + +/*----------------------------------------------------------------------*/ + +static const unsigned int crctab32[] = { + 0x00000000U, 0x77073096U, 0xee0e612cU, 0x990951baU, 0x076dc419U, + 0x706af48fU, 0xe963a535U, 0x9e6495a3U, 0x0edb8832U, 0x79dcb8a4U, + 0xe0d5e91eU, 0x97d2d988U, 0x09b64c2bU, 0x7eb17cbdU, 0xe7b82d07U, + 0x90bf1d91U, 0x1db71064U, 0x6ab020f2U, 0xf3b97148U, 0x84be41deU, + 0x1adad47dU, 0x6ddde4ebU, 0xf4d4b551U, 0x83d385c7U, 0x136c9856U, + 0x646ba8c0U, 0xfd62f97aU, 0x8a65c9ecU, 0x14015c4fU, 0x63066cd9U, + 0xfa0f3d63U, 0x8d080df5U, 0x3b6e20c8U, 0x4c69105eU, 0xd56041e4U, + 0xa2677172U, 0x3c03e4d1U, 0x4b04d447U, 0xd20d85fdU, 0xa50ab56bU, + 0x35b5a8faU, 0x42b2986cU, 0xdbbbc9d6U, 0xacbcf940U, 0x32d86ce3U, + 0x45df5c75U, 0xdcd60dcfU, 0xabd13d59U, 0x26d930acU, 0x51de003aU, + 0xc8d75180U, 0xbfd06116U, 0x21b4f4b5U, 0x56b3c423U, 0xcfba9599U, + 0xb8bda50fU, 0x2802b89eU, 0x5f058808U, 0xc60cd9b2U, 0xb10be924U, + 0x2f6f7c87U, 0x58684c11U, 0xc1611dabU, 0xb6662d3dU, 0x76dc4190U, + 0x01db7106U, 0x98d220bcU, 0xefd5102aU, 0x71b18589U, 0x06b6b51fU, + 0x9fbfe4a5U, 0xe8b8d433U, 0x7807c9a2U, 0x0f00f934U, 0x9609a88eU, + 0xe10e9818U, 0x7f6a0dbbU, 0x086d3d2dU, 0x91646c97U, 0xe6635c01U, + 0x6b6b51f4U, 0x1c6c6162U, 0x856530d8U, 0xf262004eU, 0x6c0695edU, + 0x1b01a57bU, 0x8208f4c1U, 0xf50fc457U, 0x65b0d9c6U, 0x12b7e950U, + 0x8bbeb8eaU, 0xfcb9887cU, 0x62dd1ddfU, 0x15da2d49U, 0x8cd37cf3U, + 0xfbd44c65U, 0x4db26158U, 0x3ab551ceU, 0xa3bc0074U, 0xd4bb30e2U, + 0x4adfa541U, 0x3dd895d7U, 0xa4d1c46dU, 0xd3d6f4fbU, 0x4369e96aU, + 0x346ed9fcU, 0xad678846U, 0xda60b8d0U, 0x44042d73U, 0x33031de5U, + 0xaa0a4c5fU, 0xdd0d7cc9U, 0x5005713cU, 0x270241aaU, 0xbe0b1010U, + 0xc90c2086U, 0x5768b525U, 0x206f85b3U, 0xb966d409U, 0xce61e49fU, + 0x5edef90eU, 0x29d9c998U, 0xb0d09822U, 0xc7d7a8b4U, 0x59b33d17U, + 0x2eb40d81U, 0xb7bd5c3bU, 0xc0ba6cadU, 0xedb88320U, 0x9abfb3b6U, + 0x03b6e20cU, 0x74b1d29aU, 0xead54739U, 0x9dd277afU, 0x04db2615U, + 0x73dc1683U, 0xe3630b12U, 0x94643b84U, 0x0d6d6a3eU, 0x7a6a5aa8U, + 0xe40ecf0bU, 0x9309ff9dU, 0x0a00ae27U, 0x7d079eb1U, 0xf00f9344U, + 0x8708a3d2U, 0x1e01f268U, 0x6906c2feU, 0xf762575dU, 0x806567cbU, + 0x196c3671U, 0x6e6b06e7U, 0xfed41b76U, 0x89d32be0U, 0x10da7a5aU, + 0x67dd4accU, 0xf9b9df6fU, 0x8ebeeff9U, 0x17b7be43U, 0x60b08ed5U, + 0xd6d6a3e8U, 0xa1d1937eU, 0x38d8c2c4U, 0x4fdff252U, 0xd1bb67f1U, + 0xa6bc5767U, 0x3fb506ddU, 0x48b2364bU, 0xd80d2bdaU, 0xaf0a1b4cU, + 0x36034af6U, 0x41047a60U, 0xdf60efc3U, 0xa867df55U, 0x316e8eefU, + 0x4669be79U, 0xcb61b38cU, 0xbc66831aU, 0x256fd2a0U, 0x5268e236U, + 0xcc0c7795U, 0xbb0b4703U, 0x220216b9U, 0x5505262fU, 0xc5ba3bbeU, + 0xb2bd0b28U, 0x2bb45a92U, 0x5cb36a04U, 0xc2d7ffa7U, 0xb5d0cf31U, + 0x2cd99e8bU, 0x5bdeae1dU, 0x9b64c2b0U, 0xec63f226U, 0x756aa39cU, + 0x026d930aU, 0x9c0906a9U, 0xeb0e363fU, 0x72076785U, 0x05005713U, + 0x95bf4a82U, 0xe2b87a14U, 0x7bb12baeU, 0x0cb61b38U, 0x92d28e9bU, + 0xe5d5be0dU, 0x7cdcefb7U, 0x0bdbdf21U, 0x86d3d2d4U, 0xf1d4e242U, + 0x68ddb3f8U, 0x1fda836eU, 0x81be16cdU, 0xf6b9265bU, 0x6fb077e1U, + 0x18b74777U, 0x88085ae6U, 0xff0f6a70U, 0x66063bcaU, 0x11010b5cU, + 0x8f659effU, 0xf862ae69U, 0x616bffd3U, 0x166ccf45U, 0xa00ae278U, + 0xd70dd2eeU, 0x4e048354U, 0x3903b3c2U, 0xa7672661U, 0xd06016f7U, + 0x4969474dU, 0x3e6e77dbU, 0xaed16a4aU, 0xd9d65adcU, 0x40df0b66U, + 0x37d83bf0U, 0xa9bcae53U, 0xdebb9ec5U, 0x47b2cf7fU, 0x30b5ffe9U, + 0xbdbdf21cU, 0xcabac28aU, 0x53b39330U, 0x24b4a3a6U, 0xbad03605U, + 0xcdd70693U, 0x54de5729U, 0x23d967bfU, 0xb3667a2eU, 0xc4614ab8U, + 0x5d681b02U, 0x2a6f2b94U, 0xb40bbe37U, 0xc30c8ea1U, 0x5a05df1bU, + 0x2d02ef8dU +}; + +static unsigned long partial_crc32_one(unsigned char c, unsigned long crc) +{ + return crctab32[(crc ^ c) & 0xff] ^ (crc >> 8); +} + +static unsigned long partial_crc32(const char *s, unsigned long crc) +{ + while (*s) + crc = partial_crc32_one(*s++, crc); + return crc; +} + +static unsigned long crc32(const char *s) +{ + return partial_crc32(s, 0xffffffff) ^ 0xffffffff; +} + +/*----------------------------------------------------------------------*/ + +static enum symbol_type map_to_ns(enum symbol_type t) +{ + switch (t) { + case SYM_ENUM_CONST: + case SYM_NORMAL: + case SYM_TYPEDEF: + return SYM_NORMAL; + case SYM_ENUM: + case SYM_STRUCT: + case SYM_UNION: + return SYM_STRUCT; + } + return t; +} + +struct symbol *find_symbol(const char *name, enum symbol_type ns, int exact) +{ + unsigned long h = crc32(name) % HASH_BUCKETS; + struct symbol *sym; + + for (sym = symtab[h]; sym; sym = sym->hash_next) + if (map_to_ns(sym->type) == map_to_ns(ns) && + strcmp(name, sym->name) == 0 && + sym->is_declared) + break; + + if (exact && sym && sym->type != ns) + return NULL; + return sym; +} + +static int is_unknown_symbol(struct symbol *sym) +{ + struct string_list *defn; + + return ((sym->type == SYM_STRUCT || + sym->type == SYM_UNION || + sym->type == SYM_ENUM) && + (defn = sym->defn) && defn->tag == SYM_NORMAL && + strcmp(defn->string, "}") == 0 && + (defn = defn->next) && defn->tag == SYM_NORMAL && + strcmp(defn->string, "UNKNOWN") == 0 && + (defn = defn->next) && defn->tag == SYM_NORMAL && + strcmp(defn->string, "{") == 0); +} + +static struct symbol *__add_symbol(const char *name, enum symbol_type type, + struct string_list *defn, int is_extern, + int is_reference) +{ + unsigned long h; + struct symbol *sym; + enum symbol_status status = STATUS_UNCHANGED; + /* The parser adds symbols in the order their declaration completes, + * so it is safe to store the value of the previous enum constant in + * a static variable. + */ + static int enum_counter; + static struct string_list *last_enum_expr; + + if (type == SYM_ENUM_CONST) { + if (defn) { + free_list(last_enum_expr, NULL); + last_enum_expr = copy_list_range(defn, NULL); + enum_counter = 1; + } else { + struct string_list *expr; + char buf[20]; + + snprintf(buf, sizeof(buf), "%d", enum_counter++); + if (last_enum_expr) { + expr = copy_list_range(last_enum_expr, NULL); + defn = concat_list(mk_node("("), + expr, + mk_node(")"), + mk_node("+"), + mk_node(buf), NULL); + } else { + defn = mk_node(buf); + } + } + } else if (type == SYM_ENUM) { + free_list(last_enum_expr, NULL); + last_enum_expr = NULL; + enum_counter = 0; + if (!name) + /* Anonymous enum definition, nothing more to do */ + return NULL; + } + + h = crc32(name) % HASH_BUCKETS; + for (sym = symtab[h]; sym; sym = sym->hash_next) { + if (map_to_ns(sym->type) == map_to_ns(type) && + strcmp(name, sym->name) == 0) { + if (is_reference) + /* fall through */ ; + else if (sym->type == type && + equal_list(sym->defn, defn)) { + if (!sym->is_declared && sym->is_override) { + print_location(); + print_type_name(type, name); + fprintf(stderr, " modversion is " + "unchanged\n"); + } + sym->is_declared = 1; + return sym; + } else if (!sym->is_declared) { + if (sym->is_override && flag_preserve) { + print_location(); + fprintf(stderr, "ignoring "); + print_type_name(type, name); + fprintf(stderr, " modversion change\n"); + sym->is_declared = 1; + return sym; + } else { + status = is_unknown_symbol(sym) ? + STATUS_DEFINED : STATUS_MODIFIED; + } + } else { + error_with_pos("redefinition of %s", name); + return sym; + } + break; + } + } + + if (sym) { + struct symbol **psym; + + for (psym = &symtab[h]; *psym; psym = &(*psym)->hash_next) { + if (*psym == sym) { + *psym = sym->hash_next; + break; + } + } + --nsyms; + } + + sym = xmalloc(sizeof(*sym)); + sym->name = name; + sym->type = type; + sym->defn = defn; + sym->expansion_trail = NULL; + sym->visited = NULL; + sym->is_extern = is_extern; + + sym->hash_next = symtab[h]; + symtab[h] = sym; + + sym->is_declared = !is_reference; + sym->status = status; + sym->is_override = 0; + + if (flag_debug) { + if (symbol_types[type].name) + fprintf(debugfile, "Defn for %s %s == <", + symbol_types[type].name, name); + else + fprintf(debugfile, "Defn for type%d %s == <", + type, name); + if (is_extern) + fputs("extern ", debugfile); + print_list(debugfile, defn); + fputs(">\n", debugfile); + } + + ++nsyms; + return sym; +} + +struct symbol *add_symbol(const char *name, enum symbol_type type, + struct string_list *defn, int is_extern) +{ + return __add_symbol(name, type, defn, is_extern, 0); +} + +static struct symbol *add_reference_symbol(const char *name, enum symbol_type type, + struct string_list *defn, int is_extern) +{ + return __add_symbol(name, type, defn, is_extern, 1); +} + +/*----------------------------------------------------------------------*/ + +void free_node(struct string_list *node) +{ + free(node->string); + free(node); +} + +void free_list(struct string_list *s, struct string_list *e) +{ + while (s != e) { + struct string_list *next = s->next; + free_node(s); + s = next; + } +} + +static struct string_list *mk_node(const char *string) +{ + struct string_list *newnode; + + newnode = xmalloc(sizeof(*newnode)); + newnode->string = xstrdup(string); + newnode->tag = SYM_NORMAL; + newnode->next = NULL; + + return newnode; +} + +static struct string_list *concat_list(struct string_list *start, ...) +{ + va_list ap; + struct string_list *n, *n2; + + if (!start) + return NULL; + for (va_start(ap, start); (n = va_arg(ap, struct string_list *));) { + for (n2 = n; n2->next; n2 = n2->next) + ; + n2->next = start; + start = n; + } + va_end(ap); + return start; +} + +struct string_list *copy_node(struct string_list *node) +{ + struct string_list *newnode; + + newnode = xmalloc(sizeof(*newnode)); + newnode->string = xstrdup(node->string); + newnode->tag = node->tag; + + return newnode; +} + +struct string_list *copy_list_range(struct string_list *start, + struct string_list *end) +{ + struct string_list *res, *n; + + if (start == end) + return NULL; + n = res = copy_node(start); + for (start = start->next; start != end; start = start->next) { + n->next = copy_node(start); + n = n->next; + } + n->next = NULL; + return res; +} + +static int equal_list(struct string_list *a, struct string_list *b) +{ + while (a && b) { + if (a->tag != b->tag || strcmp(a->string, b->string)) + return 0; + a = a->next; + b = b->next; + } + + return !a && !b; +} + +#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) + +static struct string_list *read_node(FILE *f) +{ + char buffer[256]; + struct string_list node = { + .string = buffer, + .tag = SYM_NORMAL }; + int c, in_string = 0; + + while ((c = fgetc(f)) != EOF) { + if (!in_string && c == ' ') { + if (node.string == buffer) + continue; + break; + } else if (c == '"') { + in_string = !in_string; + } else if (c == '\n') { + if (node.string == buffer) + return NULL; + ungetc(c, f); + break; + } + if (node.string >= buffer + sizeof(buffer) - 1) { + fprintf(stderr, "Token too long\n"); + exit(1); + } + *node.string++ = c; + } + if (node.string == buffer) + return NULL; + *node.string = 0; + node.string = buffer; + + if (node.string[1] == '#') { + size_t n; + + for (n = 0; n < ARRAY_SIZE(symbol_types); n++) { + if (node.string[0] == symbol_types[n].n) { + node.tag = n; + node.string += 2; + return copy_node(&node); + } + } + fprintf(stderr, "Unknown type %c\n", node.string[0]); + exit(1); + } + return copy_node(&node); +} + +static void read_reference(FILE *f) +{ + while (!feof(f)) { + struct string_list *defn = NULL; + struct string_list *sym, *def; + int is_extern = 0, is_override = 0; + struct symbol *subsym; + + sym = read_node(f); + if (sym && sym->tag == SYM_NORMAL && + !strcmp(sym->string, "override")) { + is_override = 1; + free_node(sym); + sym = read_node(f); + } + if (!sym) + continue; + def = read_node(f); + if (def && def->tag == SYM_NORMAL && + !strcmp(def->string, "extern")) { + is_extern = 1; + free_node(def); + def = read_node(f); + } + while (def) { + def->next = defn; + defn = def; + def = read_node(f); + } + subsym = add_reference_symbol(xstrdup(sym->string), sym->tag, + defn, is_extern); + subsym->is_override = is_override; + free_node(sym); + } +} + +static void print_node(FILE * f, struct string_list *list) +{ + if (symbol_types[list->tag].n) { + putc(symbol_types[list->tag].n, f); + putc('#', f); + } + fputs(list->string, f); +} + +static void print_list(FILE * f, struct string_list *list) +{ + struct string_list **e, **b; + struct string_list *tmp, **tmp2; + int elem = 1; + + if (list == NULL) { + fputs("(nil)", f); + return; + } + + tmp = list; + while ((tmp = tmp->next) != NULL) + elem++; + + b = alloca(elem * sizeof(*e)); + e = b + elem; + tmp2 = e - 1; + + (*tmp2--) = list; + while ((list = list->next) != NULL) + *(tmp2--) = list; + + while (b != e) { + print_node(f, *b++); + putc(' ', f); + } +} + +static unsigned long expand_and_crc_sym(struct symbol *sym, unsigned long crc) +{ + struct string_list *list = sym->defn; + struct string_list **e, **b; + struct string_list *tmp, **tmp2; + int elem = 1; + + if (!list) + return crc; + + tmp = list; + while ((tmp = tmp->next) != NULL) + elem++; + + b = alloca(elem * sizeof(*e)); + e = b + elem; + tmp2 = e - 1; + + *(tmp2--) = list; + while ((list = list->next) != NULL) + *(tmp2--) = list; + + while (b != e) { + struct string_list *cur; + struct symbol *subsym; + + cur = *(b++); + switch (cur->tag) { + case SYM_NORMAL: + if (flag_dump_defs) + fprintf(debugfile, "%s ", cur->string); + crc = partial_crc32(cur->string, crc); + crc = partial_crc32_one(' ', crc); + break; + + case SYM_ENUM_CONST: + case SYM_TYPEDEF: + subsym = find_symbol(cur->string, cur->tag, 0); + /* FIXME: Bad reference files can segfault here. */ + if (subsym->expansion_trail) { + if (flag_dump_defs) + fprintf(debugfile, "%s ", cur->string); + crc = partial_crc32(cur->string, crc); + crc = partial_crc32_one(' ', crc); + } else { + subsym->expansion_trail = expansion_trail; + expansion_trail = subsym; + crc = expand_and_crc_sym(subsym, crc); + } + break; + + case SYM_STRUCT: + case SYM_UNION: + case SYM_ENUM: + subsym = find_symbol(cur->string, cur->tag, 0); + if (!subsym) { + struct string_list *n; + + error_with_pos("expand undefined %s %s", + symbol_types[cur->tag].name, + cur->string); + n = concat_list(mk_node + (symbol_types[cur->tag].name), + mk_node(cur->string), + mk_node("{"), + mk_node("UNKNOWN"), + mk_node("}"), NULL); + subsym = + add_symbol(cur->string, cur->tag, n, 0); + } + if (subsym->expansion_trail) { + if (flag_dump_defs) { + fprintf(debugfile, "%s %s ", + symbol_types[cur->tag].name, + cur->string); + } + + crc = partial_crc32(symbol_types[cur->tag].name, + crc); + crc = partial_crc32_one(' ', crc); + crc = partial_crc32(cur->string, crc); + crc = partial_crc32_one(' ', crc); + } else { + subsym->expansion_trail = expansion_trail; + expansion_trail = subsym; + crc = expand_and_crc_sym(subsym, crc); + } + break; + } + } + + { + static struct symbol **end = &visited_symbols; + + if (!sym->visited) { + *end = sym; + end = &sym->visited; + sym->visited = (struct symbol *)-1L; + } + } + + return crc; +} + +void export_symbol(const char *name) +{ + struct symbol *sym; + + sym = find_symbol(name, SYM_NORMAL, 0); + if (!sym) + error_with_pos("export undefined symbol %s", name); + else { + unsigned long crc; + int has_changed = 0; + + if (flag_dump_defs) + fprintf(debugfile, "Export %s == <", name); + + expansion_trail = (struct symbol *)-1L; + + sym->expansion_trail = expansion_trail; + expansion_trail = sym; + crc = expand_and_crc_sym(sym, 0xffffffff) ^ 0xffffffff; + + sym = expansion_trail; + while (sym != (struct symbol *)-1L) { + struct symbol *n = sym->expansion_trail; + + if (sym->status != STATUS_UNCHANGED) { + if (!has_changed) { + print_location(); + fprintf(stderr, "%s: %s: modversion " + "changed because of changes " + "in ", flag_preserve ? "error" : + "warning", name); + } else + fprintf(stderr, ", "); + print_type_name(sym->type, sym->name); + if (sym->status == STATUS_DEFINED) + fprintf(stderr, " (became defined)"); + has_changed = 1; + if (flag_preserve) + errors++; + } + sym->expansion_trail = 0; + sym = n; + } + if (has_changed) + fprintf(stderr, "\n"); + + if (flag_dump_defs) + fputs(">\n", debugfile); + + /* Used as a linker script. */ + printf(!flag_rel_crcs ? "__crc_%s = 0x%08lx;\n" : + "SECTIONS { .rodata : ALIGN(4) { " + "__crc_%s = .; LONG(0x%08lx); } }\n", + name, crc); + } +} + +/*----------------------------------------------------------------------*/ + +static void print_location(void) +{ + fprintf(stderr, "%s:%d: ", cur_filename ? : "<stdin>", cur_line); +} + +static void print_type_name(enum symbol_type type, const char *name) +{ + if (symbol_types[type].name) + fprintf(stderr, "%s %s", symbol_types[type].name, name); + else + fprintf(stderr, "%s", name); +} + +void error_with_pos(const char *fmt, ...) +{ + va_list args; + + if (flag_warnings) { + print_location(); + + va_start(args, fmt); + vfprintf(stderr, fmt, args); + va_end(args); + putc('\n', stderr); + + errors++; + } +} + +static void genksyms_usage(void) +{ + fputs("Usage:\n" "genksyms [-adDTwqhVR] > /path/to/.tmp_obj.ver\n" "\n" +#ifdef __GNU_LIBRARY__ + " -s, --symbol-prefix Select symbol prefix\n" + " -d, --debug Increment the debug level (repeatable)\n" + " -D, --dump Dump expanded symbol defs (for debugging only)\n" + " -r, --reference file Read reference symbols from a file\n" + " -T, --dump-types file Dump expanded types into file\n" + " -p, --preserve Preserve reference modversions or fail\n" + " -w, --warnings Enable warnings\n" + " -q, --quiet Disable warnings (default)\n" + " -h, --help Print this message\n" + " -V, --version Print the release version\n" + " -R, --relative-crc Emit section relative symbol CRCs\n" +#else /* __GNU_LIBRARY__ */ + " -s Select symbol prefix\n" + " -d Increment the debug level (repeatable)\n" + " -D Dump expanded symbol defs (for debugging only)\n" + " -r file Read reference symbols from a file\n" + " -T file Dump expanded types into file\n" + " -p Preserve reference modversions or fail\n" + " -w Enable warnings\n" + " -q Disable warnings (default)\n" + " -h Print this message\n" + " -V Print the release version\n" + " -R Emit section relative symbol CRCs\n" +#endif /* __GNU_LIBRARY__ */ + , stderr); +} + +int main(int argc, char **argv) +{ + FILE *dumpfile = NULL, *ref_file = NULL; + int o; + +#ifdef __GNU_LIBRARY__ + struct option long_opts[] = { + {"debug", 0, 0, 'd'}, + {"warnings", 0, 0, 'w'}, + {"quiet", 0, 0, 'q'}, + {"dump", 0, 0, 'D'}, + {"reference", 1, 0, 'r'}, + {"dump-types", 1, 0, 'T'}, + {"preserve", 0, 0, 'p'}, + {"version", 0, 0, 'V'}, + {"help", 0, 0, 'h'}, + {"relative-crc", 0, 0, 'R'}, + {0, 0, 0, 0} + }; + + while ((o = getopt_long(argc, argv, "s:dwqVDr:T:phR", + &long_opts[0], NULL)) != EOF) +#else /* __GNU_LIBRARY__ */ + while ((o = getopt(argc, argv, "s:dwqVDr:T:phR")) != EOF) +#endif /* __GNU_LIBRARY__ */ + switch (o) { + case 'd': + flag_debug++; + break; + case 'w': + flag_warnings = 1; + break; + case 'q': + flag_warnings = 0; + break; + case 'V': + fputs("genksyms version 2.5.60\n", stderr); + break; + case 'D': + flag_dump_defs = 1; + break; + case 'r': + flag_reference = 1; + ref_file = fopen(optarg, "r"); + if (!ref_file) { + perror(optarg); + return 1; + } + break; + case 'T': + flag_dump_types = 1; + dumpfile = fopen(optarg, "w"); + if (!dumpfile) { + perror(optarg); + return 1; + } + break; + case 'p': + flag_preserve = 1; + break; + case 'h': + genksyms_usage(); + return 0; + case 'R': + flag_rel_crcs = 1; + break; + default: + genksyms_usage(); + return 1; + } + { + extern int yydebug; + extern int yy_flex_debug; + + yydebug = (flag_debug > 1); + yy_flex_debug = (flag_debug > 2); + + debugfile = stderr; + /* setlinebuf(debugfile); */ + } + + if (flag_reference) { + read_reference(ref_file); + fclose(ref_file); + } + + yyparse(); + + if (flag_dump_types && visited_symbols) { + while (visited_symbols != (struct symbol *)-1L) { + struct symbol *sym = visited_symbols; + + if (sym->is_override) + fputs("override ", dumpfile); + if (symbol_types[sym->type].n) { + putc(symbol_types[sym->type].n, dumpfile); + putc('#', dumpfile); + } + fputs(sym->name, dumpfile); + putc(' ', dumpfile); + if (sym->is_extern) + fputs("extern ", dumpfile); + print_list(dumpfile, sym->defn); + putc('\n', dumpfile); + + visited_symbols = sym->visited; + sym->visited = NULL; + } + } + + if (flag_debug) { + fprintf(debugfile, "Hash table occupancy %d/%d = %g\n", + nsyms, HASH_BUCKETS, + (double)nsyms / (double)HASH_BUCKETS); + } + + if (dumpfile) + fclose(dumpfile); + + return errors != 0; +} diff --git a/src/net/scripts/genksyms/genksyms.h b/src/net/scripts/genksyms/genksyms.h new file mode 100644 index 0000000..2bcdb9b --- /dev/null +++ b/src/net/scripts/genksyms/genksyms.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* Generate kernel symbol version hashes. + Copyright 1996, 1997 Linux International. + + New implementation contributed by Richard Henderson <rth@tamu.edu> + Based on original work by Bjorn Ekwall <bj0rn@blox.se> + + This file is part of the Linux modutils. + + */ + +#ifndef MODUTILS_GENKSYMS_H +#define MODUTILS_GENKSYMS_H 1 + +#include <stdio.h> + +enum symbol_type { + SYM_NORMAL, SYM_TYPEDEF, SYM_ENUM, SYM_STRUCT, SYM_UNION, + SYM_ENUM_CONST +}; + +enum symbol_status { + STATUS_UNCHANGED, STATUS_DEFINED, STATUS_MODIFIED +}; + +struct string_list { + struct string_list *next; + enum symbol_type tag; + int in_source_file; + char *string; +}; + +struct symbol { + struct symbol *hash_next; + const char *name; + enum symbol_type type; + struct string_list *defn; + struct symbol *expansion_trail; + struct symbol *visited; + int is_extern; + int is_declared; + enum symbol_status status; + int is_override; +}; + +typedef struct string_list **yystype; +#define YYSTYPE yystype + +extern int cur_line; +extern char *cur_filename, *source_file; +extern int in_source_file; + +struct symbol *find_symbol(const char *name, enum symbol_type ns, int exact); +struct symbol *add_symbol(const char *name, enum symbol_type type, + struct string_list *defn, int is_extern); +void export_symbol(const char *); + +void free_node(struct string_list *list); +void free_list(struct string_list *s, struct string_list *e); +struct string_list *copy_node(struct string_list *); +struct string_list *copy_list_range(struct string_list *start, + struct string_list *end); + +int yylex(void); +int yyparse(void); + +void error_with_pos(const char *, ...) __attribute__ ((format(printf, 1, 2))); + +/*----------------------------------------------------------------------*/ +#define xmalloc(size) ({ void *__ptr = malloc(size); \ + if(!__ptr && size != 0) { \ + fprintf(stderr, "out of memory\n"); \ + exit(1); \ + } \ + __ptr; }) +#define xstrdup(str) ({ char *__str = strdup(str); \ + if (!__str) { \ + fprintf(stderr, "out of memory\n"); \ + exit(1); \ + } \ + __str; }) + +#endif /* genksyms.h */ diff --git a/src/net/scripts/genksyms/keywords.c b/src/net/scripts/genksyms/keywords.c new file mode 100644 index 0000000..057c6ca --- /dev/null +++ b/src/net/scripts/genksyms/keywords.c @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0-only +static struct resword { + const char *name; + int token; +} keywords[] = { + { "__GENKSYMS_EXPORT_SYMBOL", EXPORT_SYMBOL_KEYW }, + { "__asm", ASM_KEYW }, + { "__asm__", ASM_KEYW }, + { "__attribute", ATTRIBUTE_KEYW }, + { "__attribute__", ATTRIBUTE_KEYW }, + { "__const", CONST_KEYW }, + { "__const__", CONST_KEYW }, + { "__extension__", EXTENSION_KEYW }, + { "__inline", INLINE_KEYW }, + { "__inline__", INLINE_KEYW }, + { "__signed", SIGNED_KEYW }, + { "__signed__", SIGNED_KEYW }, + { "__typeof", TYPEOF_KEYW }, + { "__typeof__", TYPEOF_KEYW }, + { "__volatile", VOLATILE_KEYW }, + { "__volatile__", VOLATILE_KEYW }, + { "__builtin_va_list", VA_LIST_KEYW }, + + { "__int128", BUILTIN_INT_KEYW }, + { "__int128_t", BUILTIN_INT_KEYW }, + { "__uint128_t", BUILTIN_INT_KEYW }, + + // According to rth, c99 defines "_Bool", "__restrict", "__restrict__", "restrict". KAO + { "_Bool", BOOL_KEYW }, + { "__restrict", RESTRICT_KEYW }, + { "__restrict__", RESTRICT_KEYW }, + { "restrict", RESTRICT_KEYW }, + { "asm", ASM_KEYW }, + + // attribute commented out in modutils 2.4.2. People are using 'attribute' as a + // field name which breaks the genksyms parser. It is not a gcc keyword anyway. + // KAO. }, + // { "attribute", ATTRIBUTE_KEYW }, + + { "auto", AUTO_KEYW }, + { "char", CHAR_KEYW }, + { "const", CONST_KEYW }, + { "double", DOUBLE_KEYW }, + { "enum", ENUM_KEYW }, + { "extern", EXTERN_KEYW }, + { "float", FLOAT_KEYW }, + { "inline", INLINE_KEYW }, + { "int", INT_KEYW }, + { "long", LONG_KEYW }, + { "register", REGISTER_KEYW }, + { "short", SHORT_KEYW }, + { "signed", SIGNED_KEYW }, + { "static", STATIC_KEYW }, + { "struct", STRUCT_KEYW }, + { "typedef", TYPEDEF_KEYW }, + { "typeof", TYPEOF_KEYW }, + { "union", UNION_KEYW }, + { "unsigned", UNSIGNED_KEYW }, + { "void", VOID_KEYW }, + { "volatile", VOLATILE_KEYW }, +}; + +#define NR_KEYWORDS (sizeof(keywords)/sizeof(struct resword)) + +static int is_reserved_word(register const char *str, register unsigned int len) +{ + int i; + for (i = 0; i < NR_KEYWORDS; i++) { + struct resword *r = keywords + i; + int l = strlen(r->name); + if (len == l && !memcmp(str, r->name, len)) + return r->token; + } + return -1; +} diff --git a/src/net/scripts/genksyms/lex.l b/src/net/scripts/genksyms/lex.l new file mode 100644 index 0000000..e265c5d --- /dev/null +++ b/src/net/scripts/genksyms/lex.l @@ -0,0 +1,469 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Lexical analysis for genksyms. + * Copyright 1996, 1997 Linux International. + * + * New implementation contributed by Richard Henderson <rth@tamu.edu> + * Based on original work by Bjorn Ekwall <bj0rn@blox.se> + * + * Taken from Linux modutils 2.4.22. + */ + +%{ + +#include <limits.h> +#include <stdlib.h> +#include <string.h> +#include <ctype.h> + +#include "genksyms.h" +#include "parse.tab.h" + +/* We've got a two-level lexer here. We let flex do basic tokenization + and then we categorize those basic tokens in the second stage. */ +#define YY_DECL static int yylex1(void) + +%} + +IDENT [A-Za-z_\$][A-Za-z0-9_\$]* + +O_INT 0[0-7]* +D_INT [1-9][0-9]* +X_INT 0[Xx][0-9A-Fa-f]+ +I_SUF [Uu]|[Ll]|[Uu][Ll]|[Ll][Uu] +INT ({O_INT}|{D_INT}|{X_INT}){I_SUF}? + +FRAC ([0-9]*\.[0-9]+)|([0-9]+\.) +EXP [Ee][+-]?[0-9]+ +F_SUF [FfLl] +REAL ({FRAC}{EXP}?{F_SUF}?)|([0-9]+{EXP}{F_SUF}?) + +STRING L?\"([^\\\"]*\\.)*[^\\\"]*\" +CHAR L?\'([^\\\']*\\.)*[^\\\']*\' + +MC_TOKEN ([~%^&*+=|<>/-]=)|(&&)|("||")|(->)|(<<)|(>>) + +/* We don't do multiple input files. */ +%option noyywrap + +%option noinput + +%% + + + /* Keep track of our location in the original source files. */ +^#[ \t]+{INT}[ \t]+\"[^\"\n]+\".*\n return FILENAME; +^#.*\n cur_line++; +\n cur_line++; + + /* Ignore all other whitespace. */ +[ \t\f\v\r]+ ; + + +{STRING} return STRING; +{CHAR} return CHAR; +{IDENT} return IDENT; + + /* The Pedant requires that the other C multi-character tokens be + recognized as tokens. We don't actually use them since we don't + parse expressions, but we do want whitespace to be arranged + around them properly. */ +{MC_TOKEN} return OTHER; +{INT} return INT; +{REAL} return REAL; + +"..." return DOTS; + + /* All other tokens are single characters. */ +. return yytext[0]; + + +%% + +/* Bring in the keyword recognizer. */ + +#include "keywords.c" + + +/* Macros to append to our phrase collection list. */ + +/* + * We mark any token, that that equals to a known enumerator, as + * SYM_ENUM_CONST. The parser will change this for struct and union tags later, + * the only problem is struct and union members: + * enum e { a, b }; struct s { int a, b; } + * but in this case, the only effect will be, that the ABI checksums become + * more volatile, which is acceptable. Also, such collisions are quite rare, + * so far it was only observed in include/linux/telephony.h. + */ +#define _APP(T,L) do { \ + cur_node = next_node; \ + next_node = xmalloc(sizeof(*next_node)); \ + next_node->next = cur_node; \ + cur_node->string = memcpy(xmalloc(L+1), T, L+1); \ + cur_node->tag = \ + find_symbol(cur_node->string, SYM_ENUM_CONST, 1)?\ + SYM_ENUM_CONST : SYM_NORMAL ; \ + cur_node->in_source_file = in_source_file; \ + } while (0) + +#define APP _APP(yytext, yyleng) + + +/* The second stage lexer. Here we incorporate knowledge of the state + of the parser to tailor the tokens that are returned. */ + +int +yylex(void) +{ + static enum { + ST_NOTSTARTED, ST_NORMAL, ST_ATTRIBUTE, ST_ASM, ST_TYPEOF, ST_TYPEOF_1, + ST_BRACKET, ST_BRACE, ST_EXPRESSION, + ST_TABLE_1, ST_TABLE_2, ST_TABLE_3, ST_TABLE_4, + ST_TABLE_5, ST_TABLE_6 + } lexstate = ST_NOTSTARTED; + + static int suppress_type_lookup, dont_want_brace_phrase; + static struct string_list *next_node; + + int token, count = 0; + struct string_list *cur_node; + + if (lexstate == ST_NOTSTARTED) + { + next_node = xmalloc(sizeof(*next_node)); + next_node->next = NULL; + lexstate = ST_NORMAL; + } + +repeat: + token = yylex1(); + + if (token == 0) + return 0; + else if (token == FILENAME) + { + char *file, *e; + + /* Save the filename and line number for later error messages. */ + + if (cur_filename) + free(cur_filename); + + file = strchr(yytext, '\"')+1; + e = strchr(file, '\"'); + *e = '\0'; + cur_filename = memcpy(xmalloc(e-file+1), file, e-file+1); + cur_line = atoi(yytext+2); + + if (!source_file) { + source_file = xstrdup(cur_filename); + in_source_file = 1; + } else { + in_source_file = (strcmp(cur_filename, source_file) == 0); + } + + goto repeat; + } + + switch (lexstate) + { + case ST_NORMAL: + switch (token) + { + case IDENT: + APP; + { + int r = is_reserved_word(yytext, yyleng); + if (r >= 0) + { + switch (token = r) + { + case ATTRIBUTE_KEYW: + lexstate = ST_ATTRIBUTE; + count = 0; + goto repeat; + case ASM_KEYW: + lexstate = ST_ASM; + count = 0; + goto repeat; + case TYPEOF_KEYW: + lexstate = ST_TYPEOF; + count = 0; + goto repeat; + + case STRUCT_KEYW: + case UNION_KEYW: + case ENUM_KEYW: + dont_want_brace_phrase = 3; + suppress_type_lookup = 2; + goto fini; + + case EXPORT_SYMBOL_KEYW: + goto fini; + } + } + if (!suppress_type_lookup) + { + if (find_symbol(yytext, SYM_TYPEDEF, 1)) + token = TYPE; + } + } + break; + + case '[': + APP; + lexstate = ST_BRACKET; + count = 1; + goto repeat; + + case '{': + APP; + if (dont_want_brace_phrase) + break; + lexstate = ST_BRACE; + count = 1; + goto repeat; + + case '=': case ':': + APP; + lexstate = ST_EXPRESSION; + break; + + case DOTS: + default: + APP; + break; + } + break; + + case ST_ATTRIBUTE: + APP; + switch (token) + { + case '(': + ++count; + goto repeat; + case ')': + if (--count == 0) + { + lexstate = ST_NORMAL; + token = ATTRIBUTE_PHRASE; + break; + } + goto repeat; + default: + goto repeat; + } + break; + + case ST_ASM: + APP; + switch (token) + { + case '(': + ++count; + goto repeat; + case ')': + if (--count == 0) + { + lexstate = ST_NORMAL; + token = ASM_PHRASE; + break; + } + goto repeat; + default: + goto repeat; + } + break; + + case ST_TYPEOF_1: + if (token == IDENT) + { + if (is_reserved_word(yytext, yyleng) >= 0 + || find_symbol(yytext, SYM_TYPEDEF, 1)) + { + yyless(0); + unput('('); + lexstate = ST_NORMAL; + token = TYPEOF_KEYW; + break; + } + _APP("(", 1); + } + lexstate = ST_TYPEOF; + /* FALLTHRU */ + + case ST_TYPEOF: + switch (token) + { + case '(': + if ( ++count == 1 ) + lexstate = ST_TYPEOF_1; + else + APP; + goto repeat; + case ')': + APP; + if (--count == 0) + { + lexstate = ST_NORMAL; + token = TYPEOF_PHRASE; + break; + } + goto repeat; + default: + APP; + goto repeat; + } + break; + + case ST_BRACKET: + APP; + switch (token) + { + case '[': + ++count; + goto repeat; + case ']': + if (--count == 0) + { + lexstate = ST_NORMAL; + token = BRACKET_PHRASE; + break; + } + goto repeat; + default: + goto repeat; + } + break; + + case ST_BRACE: + APP; + switch (token) + { + case '{': + ++count; + goto repeat; + case '}': + if (--count == 0) + { + lexstate = ST_NORMAL; + token = BRACE_PHRASE; + break; + } + goto repeat; + default: + goto repeat; + } + break; + + case ST_EXPRESSION: + switch (token) + { + case '(': case '[': case '{': + ++count; + APP; + goto repeat; + case '}': + /* is this the last line of an enum declaration? */ + if (count == 0) + { + /* Put back the token we just read so's we can find it again + after registering the expression. */ + unput(token); + + lexstate = ST_NORMAL; + token = EXPRESSION_PHRASE; + break; + } + /* FALLTHRU */ + case ')': case ']': + --count; + APP; + goto repeat; + case ',': case ';': + if (count == 0) + { + /* Put back the token we just read so's we can find it again + after registering the expression. */ + unput(token); + + lexstate = ST_NORMAL; + token = EXPRESSION_PHRASE; + break; + } + APP; + goto repeat; + default: + APP; + goto repeat; + } + break; + + case ST_TABLE_1: + goto repeat; + + case ST_TABLE_2: + if (token == IDENT && yyleng == 1 && yytext[0] == 'X') + { + token = EXPORT_SYMBOL_KEYW; + lexstate = ST_TABLE_5; + APP; + break; + } + lexstate = ST_TABLE_6; + /* FALLTHRU */ + + case ST_TABLE_6: + switch (token) + { + case '{': case '[': case '(': + ++count; + break; + case '}': case ']': case ')': + --count; + break; + case ',': + if (count == 0) + lexstate = ST_TABLE_2; + break; + }; + goto repeat; + + case ST_TABLE_3: + goto repeat; + + case ST_TABLE_4: + if (token == ';') + lexstate = ST_NORMAL; + goto repeat; + + case ST_TABLE_5: + switch (token) + { + case ',': + token = ';'; + lexstate = ST_TABLE_2; + APP; + break; + default: + APP; + break; + } + break; + + default: + exit(1); + } +fini: + + if (suppress_type_lookup > 0) + --suppress_type_lookup; + if (dont_want_brace_phrase > 0) + --dont_want_brace_phrase; + + yylval = &next_node->next; + + return token; +} diff --git a/src/net/scripts/genksyms/parse.y b/src/net/scripts/genksyms/parse.y new file mode 100644 index 0000000..e22b422 --- /dev/null +++ b/src/net/scripts/genksyms/parse.y @@ -0,0 +1,503 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * C global declaration parser for genksyms. + * Copyright 1996, 1997 Linux International. + * + * New implementation contributed by Richard Henderson <rth@tamu.edu> + * Based on original work by Bjorn Ekwall <bj0rn@blox.se> + * + * This file is part of the Linux modutils. + */ + +%{ + +#include <assert.h> +#include <stdlib.h> +#include <string.h> +#include "genksyms.h" + +static int is_typedef; +static int is_extern; +static char *current_name; +static struct string_list *decl_spec; + +static void yyerror(const char *); + +static inline void +remove_node(struct string_list **p) +{ + struct string_list *node = *p; + *p = node->next; + free_node(node); +} + +static inline void +remove_list(struct string_list **pb, struct string_list **pe) +{ + struct string_list *b = *pb, *e = *pe; + *pb = e; + free_list(b, e); +} + +/* Record definition of a struct/union/enum */ +static void record_compound(struct string_list **keyw, + struct string_list **ident, + struct string_list **body, + enum symbol_type type) +{ + struct string_list *b = *body, *i = *ident, *r; + + if (i->in_source_file) { + remove_node(keyw); + (*ident)->tag = type; + remove_list(body, ident); + return; + } + r = copy_node(i); r->tag = type; + r->next = (*keyw)->next; *body = r; (*keyw)->next = NULL; + add_symbol(i->string, type, b, is_extern); +} + +%} + +%token ASM_KEYW +%token ATTRIBUTE_KEYW +%token AUTO_KEYW +%token BOOL_KEYW +%token BUILTIN_INT_KEYW +%token CHAR_KEYW +%token CONST_KEYW +%token DOUBLE_KEYW +%token ENUM_KEYW +%token EXTERN_KEYW +%token EXTENSION_KEYW +%token FLOAT_KEYW +%token INLINE_KEYW +%token INT_KEYW +%token LONG_KEYW +%token REGISTER_KEYW +%token RESTRICT_KEYW +%token SHORT_KEYW +%token SIGNED_KEYW +%token STATIC_KEYW +%token STRUCT_KEYW +%token TYPEDEF_KEYW +%token UNION_KEYW +%token UNSIGNED_KEYW +%token VOID_KEYW +%token VOLATILE_KEYW +%token TYPEOF_KEYW +%token VA_LIST_KEYW + +%token EXPORT_SYMBOL_KEYW + +%token ASM_PHRASE +%token ATTRIBUTE_PHRASE +%token TYPEOF_PHRASE +%token BRACE_PHRASE +%token BRACKET_PHRASE +%token EXPRESSION_PHRASE + +%token CHAR +%token DOTS +%token IDENT +%token INT +%token REAL +%token STRING +%token TYPE +%token OTHER +%token FILENAME + +%% + +declaration_seq: + declaration + | declaration_seq declaration + ; + +declaration: + { is_typedef = 0; is_extern = 0; current_name = NULL; decl_spec = NULL; } + declaration1 + { free_list(*$2, NULL); *$2 = NULL; } + ; + +declaration1: + EXTENSION_KEYW TYPEDEF_KEYW { is_typedef = 1; } simple_declaration + { $$ = $4; } + | TYPEDEF_KEYW { is_typedef = 1; } simple_declaration + { $$ = $3; } + | simple_declaration + | function_definition + | asm_definition + | export_definition + | error ';' { $$ = $2; } + | error '}' { $$ = $2; } + ; + +simple_declaration: + decl_specifier_seq_opt init_declarator_list_opt ';' + { if (current_name) { + struct string_list *decl = (*$3)->next; + (*$3)->next = NULL; + add_symbol(current_name, + is_typedef ? SYM_TYPEDEF : SYM_NORMAL, + decl, is_extern); + current_name = NULL; + } + $$ = $3; + } + ; + +init_declarator_list_opt: + /* empty */ { $$ = NULL; } + | init_declarator_list + ; + +init_declarator_list: + init_declarator + { struct string_list *decl = *$1; + *$1 = NULL; + add_symbol(current_name, + is_typedef ? SYM_TYPEDEF : SYM_NORMAL, decl, is_extern); + current_name = NULL; + $$ = $1; + } + | init_declarator_list ',' init_declarator + { struct string_list *decl = *$3; + *$3 = NULL; + free_list(*$2, NULL); + *$2 = decl_spec; + add_symbol(current_name, + is_typedef ? SYM_TYPEDEF : SYM_NORMAL, decl, is_extern); + current_name = NULL; + $$ = $3; + } + ; + +init_declarator: + declarator asm_phrase_opt attribute_opt initializer_opt + { $$ = $4 ? $4 : $3 ? $3 : $2 ? $2 : $1; } + ; + +/* Hang on to the specifiers so that we can reuse them. */ +decl_specifier_seq_opt: + /* empty */ { decl_spec = NULL; } + | decl_specifier_seq + ; + +decl_specifier_seq: + decl_specifier { decl_spec = *$1; } + | decl_specifier_seq decl_specifier { decl_spec = *$2; } + ; + +decl_specifier: + storage_class_specifier + { /* Version 2 checksumming ignores storage class, as that + is really irrelevant to the linkage. */ + remove_node($1); + $$ = $1; + } + | type_specifier + ; + +storage_class_specifier: + AUTO_KEYW + | REGISTER_KEYW + | STATIC_KEYW + | EXTERN_KEYW { is_extern = 1; $$ = $1; } + | INLINE_KEYW { is_extern = 0; $$ = $1; } + ; + +type_specifier: + simple_type_specifier + | cvar_qualifier + | TYPEOF_KEYW '(' parameter_declaration ')' + | TYPEOF_PHRASE + + /* References to s/u/e's defined elsewhere. Rearrange things + so that it is easier to expand the definition fully later. */ + | STRUCT_KEYW IDENT + { remove_node($1); (*$2)->tag = SYM_STRUCT; $$ = $2; } + | UNION_KEYW IDENT + { remove_node($1); (*$2)->tag = SYM_UNION; $$ = $2; } + | ENUM_KEYW IDENT + { remove_node($1); (*$2)->tag = SYM_ENUM; $$ = $2; } + + /* Full definitions of an s/u/e. Record it. */ + | STRUCT_KEYW IDENT class_body + { record_compound($1, $2, $3, SYM_STRUCT); $$ = $3; } + | UNION_KEYW IDENT class_body + { record_compound($1, $2, $3, SYM_UNION); $$ = $3; } + | ENUM_KEYW IDENT enum_body + { record_compound($1, $2, $3, SYM_ENUM); $$ = $3; } + /* + * Anonymous enum definition. Tell add_symbol() to restart its counter. + */ + | ENUM_KEYW enum_body + { add_symbol(NULL, SYM_ENUM, NULL, 0); $$ = $2; } + /* Anonymous s/u definitions. Nothing needs doing. */ + | STRUCT_KEYW class_body { $$ = $2; } + | UNION_KEYW class_body { $$ = $2; } + ; + +simple_type_specifier: + CHAR_KEYW + | SHORT_KEYW + | INT_KEYW + | LONG_KEYW + | SIGNED_KEYW + | UNSIGNED_KEYW + | FLOAT_KEYW + | DOUBLE_KEYW + | VOID_KEYW + | BOOL_KEYW + | VA_LIST_KEYW + | BUILTIN_INT_KEYW + | TYPE { (*$1)->tag = SYM_TYPEDEF; $$ = $1; } + ; + +ptr_operator: + '*' cvar_qualifier_seq_opt + { $$ = $2 ? $2 : $1; } + ; + +cvar_qualifier_seq_opt: + /* empty */ { $$ = NULL; } + | cvar_qualifier_seq + ; + +cvar_qualifier_seq: + cvar_qualifier + | cvar_qualifier_seq cvar_qualifier { $$ = $2; } + ; + +cvar_qualifier: + CONST_KEYW | VOLATILE_KEYW | ATTRIBUTE_PHRASE + | RESTRICT_KEYW + { /* restrict has no effect in prototypes so ignore it */ + remove_node($1); + $$ = $1; + } + ; + +declarator: + ptr_operator declarator { $$ = $2; } + | direct_declarator + ; + +direct_declarator: + IDENT + { if (current_name != NULL) { + error_with_pos("unexpected second declaration name"); + YYERROR; + } else { + current_name = (*$1)->string; + $$ = $1; + } + } + | TYPE + { if (current_name != NULL) { + error_with_pos("unexpected second declaration name"); + YYERROR; + } else { + current_name = (*$1)->string; + $$ = $1; + } + } + | direct_declarator '(' parameter_declaration_clause ')' + { $$ = $4; } + | direct_declarator '(' error ')' + { $$ = $4; } + | direct_declarator BRACKET_PHRASE + { $$ = $2; } + | '(' declarator ')' + { $$ = $3; } + ; + +/* Nested declarators differ from regular declarators in that they do + not record the symbols they find in the global symbol table. */ +nested_declarator: + ptr_operator nested_declarator { $$ = $2; } + | direct_nested_declarator + ; + +direct_nested_declarator: + IDENT + | TYPE + | direct_nested_declarator '(' parameter_declaration_clause ')' + { $$ = $4; } + | direct_nested_declarator '(' error ')' + { $$ = $4; } + | direct_nested_declarator BRACKET_PHRASE + { $$ = $2; } + | '(' nested_declarator ')' + { $$ = $3; } + | '(' error ')' + { $$ = $3; } + ; + +parameter_declaration_clause: + parameter_declaration_list_opt DOTS { $$ = $2; } + | parameter_declaration_list_opt + | parameter_declaration_list ',' DOTS { $$ = $3; } + ; + +parameter_declaration_list_opt: + /* empty */ { $$ = NULL; } + | parameter_declaration_list + ; + +parameter_declaration_list: + parameter_declaration + | parameter_declaration_list ',' parameter_declaration + { $$ = $3; } + ; + +parameter_declaration: + decl_specifier_seq m_abstract_declarator + { $$ = $2 ? $2 : $1; } + ; + +m_abstract_declarator: + ptr_operator m_abstract_declarator + { $$ = $2 ? $2 : $1; } + | direct_m_abstract_declarator + ; + +direct_m_abstract_declarator: + /* empty */ { $$ = NULL; } + | IDENT + { /* For version 2 checksums, we don't want to remember + private parameter names. */ + remove_node($1); + $$ = $1; + } + /* This wasn't really a typedef name but an identifier that + shadows one. */ + | TYPE + { remove_node($1); + $$ = $1; + } + | direct_m_abstract_declarator '(' parameter_declaration_clause ')' + { $$ = $4; } + | direct_m_abstract_declarator '(' error ')' + { $$ = $4; } + | direct_m_abstract_declarator BRACKET_PHRASE + { $$ = $2; } + | '(' m_abstract_declarator ')' + { $$ = $3; } + | '(' error ')' + { $$ = $3; } + ; + +function_definition: + decl_specifier_seq_opt declarator BRACE_PHRASE + { struct string_list *decl = *$2; + *$2 = NULL; + add_symbol(current_name, SYM_NORMAL, decl, is_extern); + $$ = $3; + } + ; + +initializer_opt: + /* empty */ { $$ = NULL; } + | initializer + ; + +/* We never care about the contents of an initializer. */ +initializer: + '=' EXPRESSION_PHRASE + { remove_list($2, &(*$1)->next); $$ = $2; } + ; + +class_body: + '{' member_specification_opt '}' { $$ = $3; } + | '{' error '}' { $$ = $3; } + ; + +member_specification_opt: + /* empty */ { $$ = NULL; } + | member_specification + ; + +member_specification: + member_declaration + | member_specification member_declaration { $$ = $2; } + ; + +member_declaration: + decl_specifier_seq_opt member_declarator_list_opt ';' + { $$ = $3; } + | error ';' + { $$ = $2; } + ; + +member_declarator_list_opt: + /* empty */ { $$ = NULL; } + | member_declarator_list + ; + +member_declarator_list: + member_declarator + | member_declarator_list ',' member_declarator { $$ = $3; } + ; + +member_declarator: + nested_declarator attribute_opt { $$ = $2 ? $2 : $1; } + | IDENT member_bitfield_declarator { $$ = $2; } + | member_bitfield_declarator + ; + +member_bitfield_declarator: + ':' EXPRESSION_PHRASE { $$ = $2; } + ; + +attribute_opt: + /* empty */ { $$ = NULL; } + | attribute_opt ATTRIBUTE_PHRASE + ; + +enum_body: + '{' enumerator_list '}' { $$ = $3; } + | '{' enumerator_list ',' '}' { $$ = $4; } + ; + +enumerator_list: + enumerator + | enumerator_list ',' enumerator + +enumerator: + IDENT + { + const char *name = strdup((*$1)->string); + add_symbol(name, SYM_ENUM_CONST, NULL, 0); + } + | IDENT '=' EXPRESSION_PHRASE + { + const char *name = strdup((*$1)->string); + struct string_list *expr = copy_list_range(*$3, *$2); + add_symbol(name, SYM_ENUM_CONST, expr, 0); + } + +asm_definition: + ASM_PHRASE ';' { $$ = $2; } + ; + +asm_phrase_opt: + /* empty */ { $$ = NULL; } + | ASM_PHRASE + ; + +export_definition: + EXPORT_SYMBOL_KEYW '(' IDENT ')' ';' + { export_symbol((*$3)->string); $$ = $5; } + ; + + +%% + +static void +yyerror(const char *e) +{ + error_with_pos("%s", e); +} diff --git a/src/net/scripts/get_abi.pl b/src/net/scripts/get_abi.pl new file mode 100755 index 0000000..92d9aa6 --- /dev/null +++ b/src/net/scripts/get_abi.pl @@ -0,0 +1,628 @@ +#!/usr/bin/env perl +# SPDX-License-Identifier: GPL-2.0 + +use strict; +use warnings; +use utf8; +use Pod::Usage; +use Getopt::Long; +use File::Find; +use Fcntl ':mode'; + +my $help = 0; +my $man = 0; +my $debug = 0; +my $enable_lineno = 0; +my $prefix="Documentation/ABI"; + +# +# If true, assumes that the description is formatted with ReST +# +my $description_is_rst = 1; + +GetOptions( + "debug|d+" => \$debug, + "enable-lineno" => \$enable_lineno, + "rst-source!" => \$description_is_rst, + "dir=s" => \$prefix, + 'help|?' => \$help, + man => \$man +) or pod2usage(2); + +pod2usage(1) if $help; +pod2usage(-exitstatus => 0, -verbose => 2) if $man; + +pod2usage(2) if (scalar @ARGV < 1 || @ARGV > 2); + +my ($cmd, $arg) = @ARGV; + +pod2usage(2) if ($cmd ne "search" && $cmd ne "rest" && $cmd ne "validate"); +pod2usage(2) if ($cmd eq "search" && !$arg); + +require Data::Dumper if ($debug); + +my %data; +my %symbols; + +# +# Displays an error message, printing file name and line +# +sub parse_error($$$$) { + my ($file, $ln, $msg, $data) = @_; + + $data =~ s/\s+$/\n/; + + print STDERR "Warning: file $file#$ln:\n\t$msg"; + + if ($data ne "") { + print STDERR ". Line\n\t\t$data"; + } else { + print STDERR "\n"; + } +} + +# +# Parse an ABI file, storing its contents at %data +# +sub parse_abi { + my $file = $File::Find::name; + + my $mode = (stat($file))[2]; + return if ($mode & S_IFDIR); + return if ($file =~ m,/README,); + + my $name = $file; + $name =~ s,.*/,,; + + my $fn = $file; + $fn =~ s,Documentation/ABI/,,; + + my $nametag = "File $fn"; + $data{$nametag}->{what} = "File $name"; + $data{$nametag}->{type} = "File"; + $data{$nametag}->{file} = $name; + $data{$nametag}->{filepath} = $file; + $data{$nametag}->{is_file} = 1; + $data{$nametag}->{line_no} = 1; + + my $type = $file; + $type =~ s,.*/(.*)/.*,$1,; + + my $what; + my $new_what; + my $tag = ""; + my $ln; + my $xrefs; + my $space; + my @labels; + my $label = ""; + + print STDERR "Opening $file\n" if ($debug > 1); + open IN, $file; + while(<IN>) { + $ln++; + if (m/^(\S+)(:\s*)(.*)/i) { + my $new_tag = lc($1); + my $sep = $2; + my $content = $3; + + if (!($new_tag =~ m/(what|where|date|kernelversion|contact|description|users)/)) { + if ($tag eq "description") { + # New "tag" is actually part of + # description. Don't consider it a tag + $new_tag = ""; + } elsif ($tag ne "") { + parse_error($file, $ln, "tag '$tag' is invalid", $_); + } + } + + # Invalid, but it is a common mistake + if ($new_tag eq "where") { + parse_error($file, $ln, "tag 'Where' is invalid. Should be 'What:' instead", ""); + $new_tag = "what"; + } + + if ($new_tag =~ m/what/) { + $space = ""; + $content =~ s/[,.;]$//; + + push @{$symbols{$content}->{file}}, " $file:" . ($ln - 1); + + if ($tag =~ m/what/) { + $what .= ", " . $content; + } else { + if ($what) { + parse_error($file, $ln, "What '$what' doesn't have a description", "") if (!$data{$what}->{description}); + + foreach my $w(split /, /, $what) { + $symbols{$w}->{xref} = $what; + }; + } + + $what = $content; + $label = $content; + $new_what = 1; + } + push @labels, [($content, $label)]; + $tag = $new_tag; + + push @{$data{$nametag}->{symbols}}, $content if ($data{$nametag}->{what}); + next; + } + + if ($tag ne "" && $new_tag) { + $tag = $new_tag; + + if ($new_what) { + @{$data{$what}->{label_list}} = @labels if ($data{$nametag}->{what}); + @labels = (); + $label = ""; + $new_what = 0; + + $data{$what}->{type} = $type; + if (!defined($data{$what}->{file})) { + $data{$what}->{file} = $name; + $data{$what}->{filepath} = $file; + } else { + if ($name ne $data{$what}->{file}) { + $data{$what}->{file} .= " " . $name; + $data{$what}->{filepath} .= " " . $file; + } + } + print STDERR "\twhat: $what\n" if ($debug > 1); + $data{$what}->{line_no} = $ln; + } else { + $data{$what}->{line_no} = $ln if (!defined($data{$what}->{line_no})); + } + + if (!$what) { + parse_error($file, $ln, "'What:' should come first:", $_); + next; + } + if ($new_tag eq "description") { + $sep =~ s,:, ,; + $content = ' ' x length($new_tag) . $sep . $content; + while ($content =~ s/\t+/' ' x (length($&) * 8 - length($`) % 8)/e) {} + if ($content =~ m/^(\s*)(\S.*)$/) { + # Preserve initial spaces for the first line + $space = $1; + $content = "$2\n"; + $data{$what}->{$tag} .= $content; + } else { + undef($space); + } + + } else { + $data{$what}->{$tag} = $content; + } + next; + } + } + + # Store any contents before tags at the database + if (!$tag && $data{$nametag}->{what}) { + $data{$nametag}->{description} .= $_; + next; + } + + if ($tag eq "description") { + my $content = $_; + while ($content =~ s/\t+/' ' x (length($&) * 8 - length($`) % 8)/e) {} + if (m/^\s*\n/) { + $data{$what}->{$tag} .= "\n"; + next; + } + + if (!defined($space)) { + # Preserve initial spaces for the first line + if ($content =~ m/^(\s*)(\S.*)$/) { + $space = $1; + $content = "$2\n"; + } + } else { + $space = "" if (!($content =~ s/^($space)//)); + } + $data{$what}->{$tag} .= $content; + + next; + } + if (m/^\s*(.*)/) { + $data{$what}->{$tag} .= "\n$1"; + $data{$what}->{$tag} =~ s/\n+$//; + next; + } + + # Everything else is error + parse_error($file, $ln, "Unexpected content", $_); + } + $data{$nametag}->{description} =~ s/^\n+// if ($data{$nametag}->{description}); + if ($what) { + parse_error($file, $ln, "What '$what' doesn't have a description", "") if (!$data{$what}->{description}); + + foreach my $w(split /, /,$what) { + $symbols{$w}->{xref} = $what; + }; + } + close IN; +} + +sub create_labels { + my %labels; + + foreach my $what (keys %data) { + next if ($data{$what}->{file} eq "File"); + + foreach my $p (@{$data{$what}->{label_list}}) { + my ($content, $label) = @{$p}; + $label = "abi_" . $label . " "; + $label =~ tr/A-Z/a-z/; + + # Convert special chars to "_" + $label =~s/([\x00-\x2f\x3a-\x40\x5b-\x60\x7b-\xff])/_/g; + $label =~ s,_+,_,g; + $label =~ s,_$,,; + + # Avoid duplicated labels + while (defined($labels{$label})) { + my @chars = ("A".."Z", "a".."z"); + $label .= $chars[rand @chars]; + } + $labels{$label} = 1; + + $data{$what}->{label} = $label; + + # only one label is enough + last; + } + } +} + +# +# Outputs the book on ReST format +# + +# \b doesn't work well with paths. So, we need to define something else +my $bondary = qr { (?<![\w\/\`\{])(?=[\w\/\`\{])|(?<=[\w\/\`\{])(?![\w\/\`\{]) }x; + +sub output_rest { + create_labels(); + + my $part = ""; + + foreach my $what (sort { + ($data{$a}->{type} eq "File") cmp ($data{$b}->{type} eq "File") || + $a cmp $b + } keys %data) { + my $type = $data{$what}->{type}; + + my @file = split / /, $data{$what}->{file}; + my @filepath = split / /, $data{$what}->{filepath}; + + if ($enable_lineno) { + printf "#define LINENO %s%s#%s\n\n", + $prefix, $file[0], + $data{$what}->{line_no}; + } + + my $w = $what; + $w =~ s/([\(\)\_\-\*\=\^\~\\])/\\$1/g; + + if ($type ne "File") { + my $cur_part = $what; + if ($what =~ '/') { + if ($what =~ m#^(\/?(?:[\w\-]+\/?){1,2})#) { + $cur_part = "Symbols under $1"; + $cur_part =~ s,/$,,; + } + } + + if ($cur_part ne "" && $part ne $cur_part) { + $part = $cur_part; + my $bar = $part; + $bar =~ s/./-/g; + print "$part\n$bar\n\n"; + } + + printf ".. _%s:\n\n", $data{$what}->{label}; + + my @names = split /, /,$w; + my $len = 0; + + foreach my $name (@names) { + $name = "**$name**"; + $len = length($name) if (length($name) > $len); + } + + print "+-" . "-" x $len . "-+\n"; + foreach my $name (@names) { + printf "| %s", $name . " " x ($len - length($name)) . " |\n"; + print "+-" . "-" x $len . "-+\n"; + } + + print "\n"; + } + + for (my $i = 0; $i < scalar(@filepath); $i++) { + my $path = $filepath[$i]; + my $f = $file[$i]; + + $path =~ s,.*/(.*/.*),$1,;; + $path =~ s,[/\-],_,g;; + my $fileref = "abi_file_".$path; + + if ($type eq "File") { + print ".. _$fileref:\n\n"; + } else { + print "Defined on file :ref:`$f <$fileref>`\n\n"; + } + } + + if ($type eq "File") { + my $bar = $w; + $bar =~ s/./-/g; + print "$w\n$bar\n\n"; + } + + my $desc = ""; + $desc = $data{$what}->{description} if (defined($data{$what}->{description})); + $desc =~ s/\s+$/\n/; + + if (!($desc =~ /^\s*$/)) { + if ($description_is_rst) { + # Remove title markups from the description + # Having titles inside ABI files will only work if extra + # care would be taken in order to strictly follow the same + # level order for each markup. + $desc =~ s/\n[\-\*\=\^\~]+\n/\n\n/g; + + # Enrich text by creating cross-references + + $desc =~ s,Documentation/(?!devicetree)(\S+)\.rst,:doc:`/$1`,g; + + my @matches = $desc =~ m,Documentation/ABI/([\w\/\-]+),; + foreach my $f (@matches) { + my $xref = $f; + my $path = $f; + $path =~ s,.*/(.*/.*),$1,;; + $path =~ s,[/\-],_,g;; + $xref .= " <abi_file_" . $path . ">"; + $desc =~ s,\bDocumentation/ABI/$f\b,:ref:`$xref`,g; + } + + @matches = $desc =~ m,$bondary(/sys/[^\s\.\,\;\:\*\s\`\'\(\)]+)$bondary,; + + foreach my $s (@matches) { + if (defined($data{$s}) && defined($data{$s}->{label})) { + my $xref = $s; + + $xref =~ s/([\x00-\x1f\x21-\x2f\x3a-\x40\x7b-\xff])/\\$1/g; + $xref = ":ref:`$xref <" . $data{$s}->{label} . ">`"; + + $desc =~ s,$bondary$s$bondary,$xref,g; + } + } + + print "$desc\n\n"; + } else { + $desc =~ s/^\s+//; + + # Remove title markups from the description, as they won't work + $desc =~ s/\n[\-\*\=\^\~]+\n/\n\n/g; + + if ($desc =~ m/\:\n/ || $desc =~ m/\n[\t ]+/ || $desc =~ m/[\x00-\x08\x0b-\x1f\x7b-\xff]/) { + # put everything inside a code block + $desc =~ s/\n/\n /g; + + print "::\n\n"; + print " $desc\n\n"; + } else { + # Escape any special chars from description + $desc =~s/([\x00-\x08\x0b-\x1f\x21-\x2a\x2d\x2f\x3c-\x40\x5c\x5e-\x60\x7b-\xff])/\\$1/g; + print "$desc\n\n"; + } + } + } else { + print "DESCRIPTION MISSING for $what\n\n" if (!$data{$what}->{is_file}); + } + + if ($data{$what}->{symbols}) { + printf "Has the following ABI:\n\n"; + + foreach my $content(@{$data{$what}->{symbols}}) { + my $label = $data{$symbols{$content}->{xref}}->{label}; + + # Escape special chars from content + $content =~s/([\x00-\x1f\x21-\x2f\x3a-\x40\x7b-\xff])/\\$1/g; + + print "- :ref:`$content <$label>`\n\n"; + } + } + + if (defined($data{$what}->{users})) { + my $users = $data{$what}->{users}; + + $users =~ s/\n/\n\t/g; + printf "Users:\n\t%s\n\n", $users if ($users ne ""); + } + + } +} + +# +# Searches for ABI symbols +# +sub search_symbols { + foreach my $what (sort keys %data) { + next if (!($what =~ m/($arg)/)); + + my $type = $data{$what}->{type}; + next if ($type eq "File"); + + my $file = $data{$what}->{filepath}; + + my $bar = $what; + $bar =~ s/./-/g; + + print "\n$what\n$bar\n\n"; + + my $kernelversion = $data{$what}->{kernelversion} if (defined($data{$what}->{kernelversion})); + my $contact = $data{$what}->{contact} if (defined($data{$what}->{contact})); + my $users = $data{$what}->{users} if (defined($data{$what}->{users})); + my $date = $data{$what}->{date} if (defined($data{$what}->{date})); + my $desc = $data{$what}->{description} if (defined($data{$what}->{description})); + + $kernelversion =~ s/^\s+// if ($kernelversion); + $contact =~ s/^\s+// if ($contact); + if ($users) { + $users =~ s/^\s+//; + $users =~ s/\n//g; + } + $date =~ s/^\s+// if ($date); + $desc =~ s/^\s+// if ($desc); + + printf "Kernel version:\t\t%s\n", $kernelversion if ($kernelversion); + printf "Date:\t\t\t%s\n", $date if ($date); + printf "Contact:\t\t%s\n", $contact if ($contact); + printf "Users:\t\t\t%s\n", $users if ($users); + print "Defined on file(s):\t$file\n\n"; + print "Description:\n\n$desc"; + } +} + +# Ensure that the prefix will always end with a slash +# While this is not needed for find, it makes the patch nicer +# with --enable-lineno +$prefix =~ s,/?$,/,; + +# +# Parses all ABI files located at $prefix dir +# +find({wanted =>\&parse_abi, no_chdir => 1}, $prefix); + +print STDERR Data::Dumper->Dump([\%data], [qw(*data)]) if ($debug); + +# +# Handles the command +# +if ($cmd eq "search") { + search_symbols; +} else { + if ($cmd eq "rest") { + output_rest; + } + + # Warn about duplicated ABI entries + foreach my $what(sort keys %symbols) { + my @files = @{$symbols{$what}->{file}}; + + next if (scalar(@files) == 1); + + printf STDERR "Warning: $what is defined %d times: @files\n", + scalar(@files); + } +} + +__END__ + +=head1 NAME + +abi_book.pl - parse the Linux ABI files and produce a ReST book. + +=head1 SYNOPSIS + +B<abi_book.pl> [--debug] [--enable-lineno] [--man] [--help] + [--(no-)rst-source] [--dir=<dir>] <COMAND> [<ARGUMENT>] + +Where <COMMAND> can be: + +=over 8 + +B<search> [SEARCH_REGEX] - search for [SEARCH_REGEX] inside ABI + +B<rest> - output the ABI in ReST markup language + +B<validate> - validate the ABI contents + +=back + +=head1 OPTIONS + +=over 8 + +=item B<--dir> + +Changes the location of the ABI search. By default, it uses +the Documentation/ABI directory. + +=item B<--rst-source> and B<--no-rst-source> + +The input file may be using ReST syntax or not. Those two options allow +selecting between a rst-compliant source ABI (--rst-source), or a +plain text that may be violating ReST spec, so it requres some escaping +logic (--no-rst-source). + +=item B<--enable-lineno> + +Enable output of #define LINENO lines. + +=item B<--debug> + +Put the script in verbose mode, useful for debugging. Can be called multiple +times, to increase verbosity. + +=item B<--help> + +Prints a brief help message and exits. + +=item B<--man> + +Prints the manual page and exits. + +=back + +=head1 DESCRIPTION + +Parse the Linux ABI files from ABI DIR (usually located at Documentation/ABI), +allowing to search for ABI symbols or to produce a ReST book containing +the Linux ABI documentation. + +=head1 EXAMPLES + +Search for all stable symbols with the word "usb": + +=over 8 + +$ scripts/get_abi.pl search usb --dir Documentation/ABI/stable + +=back + +Search for all symbols that match the regex expression "usb.*cap": + +=over 8 + +$ scripts/get_abi.pl search usb.*cap + +=back + +Output all obsoleted symbols in ReST format + +=over 8 + +$ scripts/get_abi.pl rest --dir Documentation/ABI/obsolete + +=back + +=head1 BUGS + +Report bugs to Mauro Carvalho Chehab <mchehab+samsung@kernel.org> + +=head1 COPYRIGHT + +Copyright (c) 2016-2019 by Mauro Carvalho Chehab <mchehab+samsung@kernel.org>. + +License GPLv2: GNU GPL version 2 <http://gnu.org/licenses/gpl.html>. + +This is free software: you are free to change and redistribute it. +There is NO WARRANTY, to the extent permitted by law. + +=cut diff --git a/src/net/scripts/get_dvb_firmware b/src/net/scripts/get_dvb_firmware new file mode 100755 index 0000000..1a90802 --- /dev/null +++ b/src/net/scripts/get_dvb_firmware @@ -0,0 +1,929 @@ +#!/usr/bin/env perl +# SPDX-License-Identifier: GPL-2.0-or-later +# DVB firmware extractor +# +# (c) 2004 Andrew de Quincey +# + +use File::Temp qw/ tempdir /; +use IO::Handle; + +@components = ( "sp8870", "sp887x", "tda10045", "tda10046", + "tda10046lifeview", "av7110", "dec2000t", "dec2540t", + "dec3000s", "vp7041", "vp7049", "dibusb", "nxt2002", "nxt2004", + "or51211", "or51132_qam", "or51132_vsb", "bluebird", + "opera1", "cx231xx", "cx18", "cx23885", "pvrusb2", "mpc718", + "af9015", "ngene", "az6027", "lme2510_lg", "lme2510c_s7395", + "lme2510c_s7395_old", "drxk", "drxk_terratec_h5", + "drxk_hauppauge_hvr930c", "tda10071", "it9135", "drxk_pctv", + "drxk_terratec_htc_stick", "sms1xxx_hcw", "si2165"); + +# Check args +syntax() if (scalar(@ARGV) != 1); +$cid = $ARGV[0]; + +# Do it! +for ($i=0; $i < scalar(@components); $i++) { + if ($cid eq $components[$i]) { + $outfile = eval($cid); + die $@ if $@; + print STDERR <<EOF; +Firmware(s) $outfile extracted successfully. +Now copy it(them) to either /usr/lib/hotplug/firmware or /lib/firmware +(depending on configuration of firmware hotplug). +EOF + exit(0); + } +} + +# If we get here, it wasn't found +print STDERR "Unknown component \"$cid\"\n"; +syntax(); + + + + +# --------------------------------------------------------------- +# Firmware-specific extraction subroutines + +sub sp8870 { + my $sourcefile = "tt_Premium_217g.zip"; + my $url = "http://www.softwarepatch.pl/9999ccd06a4813cb827dbb0005071c71/$sourcefile"; + my $hash = "53970ec17a538945a6d8cb608a7b3899"; + my $outfile = "dvb-fe-sp8870.fw"; + my $tmpdir = tempdir(DIR => "/tmp", CLEANUP => 1); + + checkstandard(); + + wgetfile($sourcefile, $url); + unzip($sourcefile, $tmpdir); + verify("$tmpdir/software/OEM/HE/App/boot/SC_MAIN.MC", $hash); + copy("$tmpdir/software/OEM/HE/App/boot/SC_MAIN.MC", $outfile); + + $outfile; +} + +sub sp887x { + my $sourcefile = "Dvbt1.3.57.6.zip"; + my $url = "http://www.avermedia.com/software/$sourcefile"; + my $cabfile = "DVBT Net Ver1.3.57.6/disk1/data1.cab"; + my $hash = "237938d53a7f834c05c42b894ca68ac3"; + my $outfile = "dvb-fe-sp887x.fw"; + my $tmpdir = tempdir(DIR => "/tmp", CLEANUP => 1); + + checkstandard(); + checkunshield(); + + wgetfile($sourcefile, $url); + unzip($sourcefile, $tmpdir); + unshield("$tmpdir/$cabfile", $tmpdir); + verify("$tmpdir/ZEnglish/sc_main.mc", $hash); + copy("$tmpdir/ZEnglish/sc_main.mc", $outfile); + + $outfile; +} + +sub tda10045 { + my $sourcefile = "tt_budget_217g.zip"; + my $url = "http://www.technotrend.de/new/217g/$sourcefile"; + my $hash = "2105fd5bf37842fbcdfa4bfd58f3594a"; + my $outfile = "dvb-fe-tda10045.fw"; + my $tmpdir = tempdir(DIR => "/tmp", CLEANUP => 1); + + checkstandard(); + + wgetfile($sourcefile, $url); + unzip($sourcefile, $tmpdir); + extract("$tmpdir/software/OEM/PCI/App/ttlcdacc.dll", 0x37ef9, 30555, "$tmpdir/fwtmp"); + verify("$tmpdir/fwtmp", $hash); + copy("$tmpdir/fwtmp", $outfile); + + $outfile; +} + +sub tda10046 { + my $sourcefile = "TT_PCI_2.19h_28_11_2006.zip"; + my $url = "http://technotrend.com.ua/download/software/219/$sourcefile"; + my $hash = "6a7e1e2f2644b162ff0502367553c72d"; + my $outfile = "dvb-fe-tda10046.fw"; + my $tmpdir = tempdir(DIR => "/tmp", CLEANUP => 1); + + checkstandard(); + + wgetfile($sourcefile, $url); + unzip($sourcefile, $tmpdir); + extract("$tmpdir/TT_PCI_2.19h_28_11_2006/software/OEM/PCI/App/ttlcdacc.dll", 0x65389, 24478, "$tmpdir/fwtmp"); + verify("$tmpdir/fwtmp", $hash); + copy("$tmpdir/fwtmp", $outfile); + + $outfile; +} + +sub tda10046lifeview { + my $sourcefile = "7%5Cdrv_2.11.02.zip"; + my $url = "http://www.lifeview.hk/dbimages/document/$sourcefile"; + my $hash = "1ea24dee4eea8fe971686981f34fd2e0"; + my $outfile = "dvb-fe-tda10046.fw"; + my $tmpdir = tempdir(DIR => "/tmp", CLEANUP => 1); + + checkstandard(); + + wgetfile($sourcefile, $url); + unzip($sourcefile, $tmpdir); + extract("$tmpdir/LVHybrid.sys", 0x8b088, 24602, "$tmpdir/fwtmp"); + verify("$tmpdir/fwtmp", $hash); + copy("$tmpdir/fwtmp", $outfile); + + $outfile; +} + +sub av7110 { + my $sourcefile = "dvb-ttpci-01.fw-261d"; + my $url = "https://linuxtv.org/downloads/firmware/$sourcefile"; + my $hash = "603431b6259715a8e88f376a53b64e2f"; + my $outfile = "dvb-ttpci-01.fw"; + + checkstandard(); + + wgetfile($sourcefile, $url); + verify($sourcefile, $hash); + copy($sourcefile, $outfile); + + $outfile; +} + +sub dec2000t { + my $sourcefile = "dec217g.exe"; + my $url = "http://hauppauge.lightpath.net/de/$sourcefile"; + my $hash = "bd86f458cee4a8f0a8ce2d20c66215a9"; + my $outfile = "dvb-ttusb-dec-2000t.fw"; + my $tmpdir = tempdir(DIR => "/tmp", CLEANUP => 1); + + checkstandard(); + + wgetfile($sourcefile, $url); + unzip($sourcefile, $tmpdir); + verify("$tmpdir/software/OEM/STB/App/Boot/STB_PC_T.bin", $hash); + copy("$tmpdir/software/OEM/STB/App/Boot/STB_PC_T.bin", $outfile); + + $outfile; +} + +sub dec2540t { + my $sourcefile = "dec217g.exe"; + my $url = "http://hauppauge.lightpath.net/de/$sourcefile"; + my $hash = "53e58f4f5b5c2930beee74a7681fed92"; + my $outfile = "dvb-ttusb-dec-2540t.fw"; + my $tmpdir = tempdir(DIR => "/tmp", CLEANUP => 1); + + checkstandard(); + + wgetfile($sourcefile, $url); + unzip($sourcefile, $tmpdir); + verify("$tmpdir/software/OEM/STB/App/Boot/STB_PC_X.bin", $hash); + copy("$tmpdir/software/OEM/STB/App/Boot/STB_PC_X.bin", $outfile); + + $outfile; +} + +sub dec3000s { + my $sourcefile = "dec217g.exe"; + my $url = "http://hauppauge.lightpath.net/de/$sourcefile"; + my $hash = "b013ececea83f4d6d8d2a29ac7c1b448"; + my $outfile = "dvb-ttusb-dec-3000s.fw"; + my $tmpdir = tempdir(DIR => "/tmp", CLEANUP => 1); + + checkstandard(); + + wgetfile($sourcefile, $url); + unzip($sourcefile, $tmpdir); + verify("$tmpdir/software/OEM/STB/App/Boot/STB_PC_S.bin", $hash); + copy("$tmpdir/software/OEM/STB/App/Boot/STB_PC_S.bin", $outfile); + + $outfile; +} +sub opera1{ + my $tmpdir = tempdir(DIR => "/tmp", CLEANUP => 0); + + checkstandard(); + my $fwfile1="dvb-usb-opera1-fpga-01.fw"; + my $fwfile2="dvb-usb-opera-01.fw"; + extract("2830SCap2.sys", 0x62e8, 55024, "$tmpdir/opera1-fpga.fw"); + extract("2830SLoad2.sys",0x3178,0x3685-0x3178,"$tmpdir/fw1part1"); + extract("2830SLoad2.sys",0x0980,0x3150-0x0980,"$tmpdir/fw1part2"); + delzero("$tmpdir/fw1part1","$tmpdir/fw1part1-1"); + delzero("$tmpdir/fw1part2","$tmpdir/fw1part2-1"); + verify("$tmpdir/fw1part1-1","5e0909858fdf0b5b09ad48b9fe622e70"); + verify("$tmpdir/fw1part2-1","d6e146f321427e931df2c6fcadac37a1"); + verify("$tmpdir/opera1-fpga.fw","0f8133f5e9051f5f3c1928f7e5a1b07d"); + + my $RES1="\x01\x92\x7f\x00\x01\x00"; + my $RES0="\x01\x92\x7f\x00\x00\x00"; + my $DAT1="\x01\x00\xe6\x00\x01\x00"; + my $DAT0="\x01\x00\xe6\x00\x00\x00"; + open FW,">$tmpdir/opera.fw"; + print FW "$RES1"; + print FW "$DAT1"; + print FW "$RES1"; + print FW "$DAT1"; + appendfile(FW,"$tmpdir/fw1part1-1"); + print FW "$RES0"; + print FW "$DAT0"; + print FW "$RES1"; + print FW "$DAT1"; + appendfile(FW,"$tmpdir/fw1part2-1"); + print FW "$RES1"; + print FW "$DAT1"; + print FW "$RES0"; + print FW "$DAT0"; + copy ("$tmpdir/opera1-fpga.fw",$fwfile1); + copy ("$tmpdir/opera.fw",$fwfile2); + + $fwfile1.",".$fwfile2; +} + +sub vp7041 { + my $sourcefile = "2.422.zip"; + my $url = "http://www.twinhan.com/files/driver/USB-Ter/$sourcefile"; + my $hash = "e88c9372d1f66609a3e7b072c53fbcfe"; + my $outfile = "dvb-vp7041-2.422.fw"; + my $tmpdir = tempdir(DIR => "/tmp", CLEANUP => 1); + + checkstandard(); + + wgetfile($sourcefile, $url); + unzip($sourcefile, $tmpdir); + extract("$tmpdir/VisionDTV/Drivers/Win2K&XP/UDTTload.sys", 12503, 3036, "$tmpdir/fwtmp1"); + extract("$tmpdir/VisionDTV/Drivers/Win2K&XP/UDTTload.sys", 2207, 10274, "$tmpdir/fwtmp2"); + + my $CMD = "\000\001\000\222\177\000"; + my $PAD = "\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000"; + my ($FW); + open $FW, ">$tmpdir/fwtmp3"; + print $FW "$CMD\001$PAD"; + print $FW "$CMD\001$PAD"; + appendfile($FW, "$tmpdir/fwtmp1"); + print $FW "$CMD\000$PAD"; + print $FW "$CMD\001$PAD"; + appendfile($FW, "$tmpdir/fwtmp2"); + print $FW "$CMD\001$PAD"; + print $FW "$CMD\000$PAD"; + close($FW); + + verify("$tmpdir/fwtmp3", $hash); + copy("$tmpdir/fwtmp3", $outfile); + + $outfile; +} + +sub vp7049 { + my $fwfile = "dvb-usb-vp7049-0.95.fw"; + my $url = "http://ao2.it/sites/default/files/blog/2012/11/06/linux-support-digicom-digitune-s-vp7049-udtt7049/$fwfile"; + my $hash = "5609fd295168aea88b25ff43a6f79c36"; + + checkstandard(); + + wgetfile($fwfile, $url); + verify($fwfile, $hash); + + $fwfile; +} + +sub dibusb { + my $url = "https://linuxtv.org/downloads/firmware/dvb-usb-dibusb-5.0.0.11.fw"; + my $outfile = "dvb-dibusb-5.0.0.11.fw"; + my $hash = "fa490295a527360ca16dcdf3224ca243"; + + checkstandard(); + + wgetfile($outfile, $url); + verify($outfile,$hash); + + $outfile; +} + +sub nxt2002 { + my $sourcefile = "Technisat_DVB-PC_4_4_COMPACT.zip"; + my $url = "http://www.bbti.us/download/windows/$sourcefile"; + my $hash = "476befae8c7c1bb9648954060b1eec1f"; + my $outfile = "dvb-fe-nxt2002.fw"; + my $tmpdir = tempdir(DIR => "/tmp", CLEANUP => 1); + + checkstandard(); + + wgetfile($sourcefile, $url); + unzip($sourcefile, $tmpdir); + verify("$tmpdir/SkyNET.sys", $hash); + extract("$tmpdir/SkyNET.sys", 331624, 5908, $outfile); + + $outfile; +} + +sub nxt2004 { + my $sourcefile = "AVerTVHD_MCE_A180_Drv_v1.2.2.16.zip"; + my $url = "http://www.avermedia-usa.com/support/Drivers/$sourcefile"; + my $hash = "111cb885b1e009188346d72acfed024c"; + my $outfile = "dvb-fe-nxt2004.fw"; + my $tmpdir = tempdir(DIR => "/tmp", CLEANUP => 1); + + checkstandard(); + + wgetfile($sourcefile, $url); + unzip($sourcefile, $tmpdir); + verify("$tmpdir/3xHybrid.sys", $hash); + extract("$tmpdir/3xHybrid.sys", 465304, 9584, $outfile); + + $outfile; +} + +sub or51211 { + my $fwfile = "dvb-fe-or51211.fw"; + my $url = "https://linuxtv.org/downloads/firmware/$fwfile"; + my $hash = "d830949c771a289505bf9eafc225d491"; + + checkstandard(); + + wgetfile($fwfile, $url); + verify($fwfile, $hash); + + $fwfile; +} + +sub cx231xx { + my $fwfile = "v4l-cx231xx-avcore-01.fw"; + my $url = "https://linuxtv.org/downloads/firmware/$fwfile"; + my $hash = "7d3bb956dc9df0eafded2b56ba57cc42"; + + checkstandard(); + + wgetfile($fwfile, $url); + verify($fwfile, $hash); + + $fwfile; +} + +sub cx18 { + my $url = "https://linuxtv.org/downloads/firmware/"; + + my %files = ( + 'v4l-cx23418-apu.fw' => '588f081b562f5c653a3db1ad8f65939a', + 'v4l-cx23418-cpu.fw' => 'b6c7ed64bc44b1a6e0840adaeac39d79', + 'v4l-cx23418-dig.fw' => '95bc688d3e7599fd5800161e9971cc55', + ); + + checkstandard(); + + my $allfiles; + foreach my $fwfile (keys %files) { + wgetfile($fwfile, "$url/$fwfile"); + verify($fwfile, $files{$fwfile}); + $allfiles .= " $fwfile"; + } + + $allfiles =~ s/^\s//; + + $allfiles; +} + +sub mpc718 { + my $archive = 'Yuan MPC718 TV Tuner Card 2.13.10.1016.zip'; + my $url = "ftp://ftp.work.acer-euro.com/desktop/aspire_idea510/vista/Drivers/$archive"; + my $fwfile = "dvb-cx18-mpc718-mt352.fw"; + my $tmpdir = tempdir(DIR => "/tmp", CLEANUP => 1); + + checkstandard(); + wgetfile($archive, $url); + unzip($archive, $tmpdir); + + my $sourcefile = "$tmpdir/Yuan MPC718 TV Tuner Card 2.13.10.1016/mpc718_32bit/yuanrap.sys"; + my $found = 0; + + open IN, '<', $sourcefile or die "Couldn't open $sourcefile to extract $fwfile data\n"; + binmode IN; + open OUT, '>', $fwfile; + binmode OUT; + { + # Block scope because we change the line terminator variable $/ + my $prevlen = 0; + my $currlen; + + # Buried in the data segment are 3 runs of almost identical + # register-value pairs that end in 0x5d 0x01 which is a "TUNER GO" + # command for the MT352. + # Pull out the middle run (because it's easy) of register-value + # pairs to make the "firmware" file. + + local $/ = "\x5d\x01"; # MT352 "TUNER GO" + + while (<IN>) { + $currlen = length($_); + if ($prevlen == $currlen && $currlen <= 64) { + chop; chop; # Get rid of "TUNER GO" + s/^\0\0//; # get rid of leading 00 00 if it's there + printf OUT "$_"; + $found = 1; + last; + } + $prevlen = $currlen; + } + } + close OUT; + close IN; + if (!$found) { + unlink $fwfile; + die "Couldn't find valid register-value sequence in $sourcefile for $fwfile\n"; + } + $fwfile; +} + +sub cx23885 { + my $url = "https://linuxtv.org/downloads/firmware/"; + + my %files = ( + 'v4l-cx23885-avcore-01.fw' => 'a9f8f5d901a7fb42f552e1ee6384f3bb', + 'v4l-cx23885-enc.fw' => 'a9f8f5d901a7fb42f552e1ee6384f3bb', + ); + + checkstandard(); + + my $allfiles; + foreach my $fwfile (keys %files) { + wgetfile($fwfile, "$url/$fwfile"); + verify($fwfile, $files{$fwfile}); + $allfiles .= " $fwfile"; + } + + $allfiles =~ s/^\s//; + + $allfiles; +} + +sub pvrusb2 { + my $url = "https://linuxtv.org/downloads/firmware/"; + + my %files = ( + 'v4l-cx25840.fw' => 'dadb79e9904fc8af96e8111d9cb59320', + ); + + checkstandard(); + + my $allfiles; + foreach my $fwfile (keys %files) { + wgetfile($fwfile, "$url/$fwfile"); + verify($fwfile, $files{$fwfile}); + $allfiles .= " $fwfile"; + } + + $allfiles =~ s/^\s//; + + $allfiles; +} + +sub or51132_qam { + my $fwfile = "dvb-fe-or51132-qam.fw"; + my $url = "https://linuxtv.org/downloads/firmware/$fwfile"; + my $hash = "7702e8938612de46ccadfe9b413cb3b5"; + + checkstandard(); + + wgetfile($fwfile, $url); + verify($fwfile, $hash); + + $fwfile; +} + +sub or51132_vsb { + my $fwfile = "dvb-fe-or51132-vsb.fw"; + my $url = "https://linuxtv.org/downloads/firmware/$fwfile"; + my $hash = "c16208e02f36fc439a557ad4c613364a"; + + checkstandard(); + + wgetfile($fwfile, $url); + verify($fwfile, $hash); + + $fwfile; +} + +sub bluebird { + my $url = "https://linuxtv.org/download/dvb/firmware/dvb-usb-bluebird-01.fw"; + my $outfile = "dvb-usb-bluebird-01.fw"; + my $hash = "658397cb9eba9101af9031302671f49d"; + + checkstandard(); + + wgetfile($outfile, $url); + verify($outfile,$hash); + + $outfile; +} + +sub af9015 { + my $sourcefile = "download.ashx?file=57"; + my $url = "http://www.ite.com.tw/EN/Services/$sourcefile"; + my $hash = "e3f08935158038d385ad382442f4bb2d"; + my $outfile = "dvb-usb-af9015.fw"; + my $tmpdir = tempdir(DIR => "/tmp", CLEANUP => 1); + my $fwoffset = 0x25690; + my $fwlength = 18725; + my ($chunklength, $buf, $rcount); + + checkstandard(); + + wgetfile($sourcefile, $url); + unzip($sourcefile, $tmpdir); + verify("$tmpdir/Driver/Files/AF15BDA.sys", $hash); + + open INFILE, '<', "$tmpdir/Driver/Files/AF15BDA.sys"; + open OUTFILE, '>', $outfile; + + sysseek(INFILE, $fwoffset, SEEK_SET); + while($fwlength > 0) { + $chunklength = 55; + $chunklength = $fwlength if ($chunklength > $fwlength); + $rcount = sysread(INFILE, $buf, $chunklength); + die "Ran out of data\n" if ($rcount != $chunklength); + syswrite(OUTFILE, $buf); + sysread(INFILE, $buf, 8); + $fwlength -= $rcount + 8; + } + + close OUTFILE; + close INFILE; +} + +sub ngene { + my $url = "http://www.digitaldevices.de/download/"; + my $file1 = "ngene_15.fw"; + my $hash1 = "d798d5a757121174f0dbc5f2833c0c85"; + my $file2 = "ngene_17.fw"; + my $hash2 = "26b687136e127b8ac24b81e0eeafc20b"; + my $url2 = "http://l4m-daten.de/downloads/firmware/dvb-s2/linux/all/"; + my $file3 = "ngene_18.fw"; + my $hash3 = "ebce3ea769a53e3e0b0197c3b3f127e3"; + + checkstandard(); + + wgetfile($file1, $url . $file1); + verify($file1, $hash1); + + wgetfile($file2, $url . $file2); + verify($file2, $hash2); + + wgetfile($file3, $url2 . $file3); + verify($file3, $hash3); + + "$file1, $file2, $file3"; +} + +sub az6027{ + my $firmware = "dvb-usb-az6027-03.fw"; + my $url = "http://linux.terratec.de/files/TERRATEC_S7/$firmware"; + + wgetfile($firmware, $url); + + $firmware; +} + +sub lme2510_lg { + my $sourcefile = "LMEBDA_DVBS.sys"; + my $hash = "fc6017ad01e79890a97ec53bea157ed2"; + my $outfile = "dvb-usb-lme2510-lg.fw"; + my $hasho = "caa065d5fdbd2c09ad57b399bbf55cad"; + + checkstandard(); + + verify($sourcefile, $hash); + extract($sourcefile, 4168, 3841, $outfile); + verify($outfile, $hasho); + $outfile; +} + +sub lme2510c_s7395 { + my $sourcefile = "US2A0D.sys"; + my $hash = "b0155a8083fb822a3bd47bc360e74601"; + my $outfile = "dvb-usb-lme2510c-s7395.fw"; + my $hasho = "3a3cf1aeebd17b6ddc04cebe131e94cf"; + + checkstandard(); + + verify($sourcefile, $hash); + extract($sourcefile, 37248, 3720, $outfile); + verify($outfile, $hasho); + $outfile; +} + +sub lme2510c_s7395_old { + my $sourcefile = "LMEBDA_DVBS7395C.sys"; + my $hash = "7572ae0eb9cdf91baabd7c0ba9e09b31"; + my $outfile = "dvb-usb-lme2510c-s7395.fw"; + my $hasho = "90430c5b435eb5c6f88fd44a9d950674"; + + checkstandard(); + + verify($sourcefile, $hash); + extract($sourcefile, 4208, 3881, $outfile); + verify($outfile, $hasho); + $outfile; +} + +sub drxk { + my $url = "http://l4m-daten.de/files/"; + my $zipfile = "DDTuner.zip"; + my $hash = "f5a37b9a20a3534997997c0b1382a3e5"; + my $tmpdir = tempdir(DIR => "/tmp", CLEANUP => 1); + my $drvfile = "DDTuner.sys"; + my $fwfile = "drxk_a3.mc"; + + checkstandard(); + + wgetfile($zipfile, $url . $zipfile); + verify($zipfile, $hash); + unzip($zipfile, $tmpdir); + extract("$tmpdir/$drvfile", 0x14dd8, 15634, "$fwfile"); + + "$fwfile" +} + +sub drxk_hauppauge_hvr930c { + my $url = "http://www.wintvcd.co.uk/drivers/"; + my $zipfile = "HVR-9x0_5_10_325_28153_SIGNED.zip"; + my $hash = "83ab82e7e9480ec8bf1ae0155ca63c88"; + my $tmpdir = tempdir(DIR => "/tmp", CLEANUP => 1); + my $drvfile = "HVR-900/emOEM.sys"; + my $fwfile = "dvb-usb-hauppauge-hvr930c-drxk.fw"; + + checkstandard(); + + wgetfile($zipfile, $url . $zipfile); + verify($zipfile, $hash); + unzip($zipfile, $tmpdir); + extract("$tmpdir/$drvfile", 0x117b0, 42692, "$fwfile"); + + "$fwfile" +} + +sub drxk_terratec_h5 { + my $url = "https://linuxtv.org/downloads/firmware/"; + my $hash = "19000dada8e2741162ccc50cc91fa7f1"; + my $fwfile = "dvb-usb-terratec-h5-drxk.fw"; + + checkstandard(); + + wgetfile($fwfile, $url . $fwfile); + verify($fwfile, $hash); + + "$fwfile" +} + +sub drxk_terratec_htc_stick { + my $url = "http://ftp.terratec.de/Receiver/Cinergy_HTC_Stick/Updates/History/"; + my $zipfile = "Cinergy_HTC_Stick_Drv_5.09.1202.00_XP_Vista_7.exe"; + my $hash = "6722a2442a05423b781721fbc069ed5e"; + my $tmpdir = tempdir(DIR => "/tmp", CLEANUP => 0); + my $drvfile = "Cinergy HTC Stick/BDA Driver 5.09.1202.00/Windows 32 Bit/emOEM.sys"; + my $fwfile = "dvb-usb-terratec-htc-stick-drxk.fw"; + + checkstandard(); + + wgetfile($zipfile, $url . $zipfile); + verify($zipfile, $hash); + unzip($zipfile, $tmpdir); + extract("$tmpdir/$drvfile", 0x4e5c0, 42692, "$fwfile"); + + "$fwfile" +} + +sub it9135 { + my $url = "http://www.ite.com.tw/uploads/firmware/v3.25.0.0/"; + my $file1 = "dvb-usb-it9135-01.zip"; + my $fwfile1 = "dvb-usb-it9135-01.fw"; + my $hash1 = "02fcf11174eda84745dae7e61c5ff9ba"; + my $file2 = "dvb-usb-it9135-02.zip"; + my $fwfile2 = "dvb-usb-it9135-02.fw"; + my $hash2 = "d5e1437dc24358578e07999475d4cac9"; + + checkstandard(); + + wgetfile($file1, $url . $file1); + unzip($file1, ""); + verify("$fwfile1", $hash1); + + wgetfile($file2, $url . $file2); + unzip($file2, ""); + verify("$fwfile2", $hash2); + + "$file1 $file2" +} + +sub tda10071 { + my $sourcefile = "PCTV_460e_reference.zip"; + my $url = "ftp://ftp.pctvsystems.com/TV/driver/PCTV%2070e%2080e%20100e%20320e%20330e%20800e/"; + my $hash = "4403de903bf2593464c8d74bbc200a57"; + my $fwfile = "dvb-fe-tda10071.fw"; + my $tmpdir = tempdir(DIR => "/tmp", CLEANUP => 1); + + checkstandard(); + + wgetfile($sourcefile, $url . $sourcefile); + verify($sourcefile, $hash); + unzip($sourcefile, $tmpdir); + extract("$tmpdir/PCTV\ 70e\ 80e\ 100e\ 320e\ 330e\ 800e/32\ bit/emOEM.sys", 0x67d38, 40504, $fwfile); + + "$fwfile"; +} + +sub drxk_pctv { + my $sourcefile = "PCTV_460e_reference.zip"; + my $url = "ftp://ftp.pctvsystems.com/TV/driver/PCTV%2070e%2080e%20100e%20320e%20330e%20800e/"; + my $hash = "4403de903bf2593464c8d74bbc200a57"; + my $fwfile = "dvb-demod-drxk-pctv.fw"; + my $tmpdir = tempdir(DIR => "/tmp", CLEANUP => 1); + + checkstandard(); + + wgetfile($sourcefile, $url . $sourcefile); + verify($sourcefile, $hash); + unzip($sourcefile, $tmpdir); + extract("$tmpdir/PCTV\ 70e\ 80e\ 100e\ 320e\ 330e\ 800e/32\ bit/emOEM.sys", 0x72b80, 42692, $fwfile); + + "$fwfile"; +} + +sub sms1xxx_hcw { + my $url = "http://steventoth.net/linux/sms1xxx/"; + my %files = ( + 'sms1xxx-hcw-55xxx-dvbt-01.fw' => "afb6f9fb9a71d64392e8564ef9577e5a", + 'sms1xxx-hcw-55xxx-dvbt-02.fw' => "b44807098ba26e52cbedeadc052ba58f", + 'sms1xxx-hcw-55xxx-isdbt-02.fw' => "dae934eeea85225acbd63ce6cfe1c9e4", + ); + + checkstandard(); + + my $allfiles; + foreach my $fwfile (keys %files) { + wgetfile($fwfile, "$url/$fwfile"); + verify($fwfile, $files{$fwfile}); + $allfiles .= " $fwfile"; + } + + $allfiles =~ s/^\s//; + + $allfiles; +} + +sub si2165 { + my $sourcefile = "model_111xxx_122xxx_driver_6_0_119_31191_WHQL.zip"; + my $url = "http://www.hauppauge.de/files/drivers/"; + my $hash = "76633e7c76b0edee47c3ba18ded99336"; + my $fwfile = "dvb-demod-si2165.fw"; + my $tmpdir = tempdir(DIR => "/tmp", CLEANUP => 1); + + checkstandard(); + + wgetfile($sourcefile, $url . $sourcefile); + verify($sourcefile, $hash); + unzip($sourcefile, $tmpdir); + extract("$tmpdir/Driver10/Hcw10bda.sys", 0x80788, 0x81E08-0x80788, "$tmpdir/fw1"); + + delzero("$tmpdir/fw1","$tmpdir/fw1-1"); + #verify("$tmpdir/fw1","5e0909858fdf0b5b09ad48b9fe622e70"); + + my $CRC="\x0A\xCC"; + my $BLOCKS_MAIN="\x27"; + open FW,">$fwfile"; + print FW "\x01\x00"; # just a version id for the driver itself + print FW "\x9A"; # fw version + print FW "\x00"; # padding + print FW "$BLOCKS_MAIN"; # number of blocks of main part + print FW "\x00"; # padding + print FW "$CRC"; # 16bit crc value of main part + appendfile(FW,"$tmpdir/fw1"); + + "$fwfile"; +} + +# --------------------------------------------------------------- +# Utilities + +sub checkstandard { + if (system("which unzip > /dev/null 2>&1")) { + die "This firmware requires the unzip command - see ftp://ftp.info-zip.org/pub/infozip/UnZip.html\n"; + } + if (system("which md5sum > /dev/null 2>&1")) { + die "This firmware requires the md5sum command - see http://www.gnu.org/software/coreutils/\n"; + } + if (system("which wget > /dev/null 2>&1")) { + die "This firmware requires the wget command - see http://wget.sunsite.dk/\n"; + } +} + +sub checkunshield { + if (system("which unshield > /dev/null 2>&1")) { + die "This firmware requires the unshield command - see http://sourceforge.net/projects/synce/\n"; + } +} + +sub wgetfile { + my ($sourcefile, $url) = @_; + + if (! -f $sourcefile) { + system("wget -O \"$sourcefile\" \"$url\"") and die "wget failed - unable to download firmware"; + } +} + +sub unzip { + my ($sourcefile, $todir) = @_; + + $status = system("unzip -q -o -d \"$todir\" \"$sourcefile\" 2>/dev/null" ); + if ((($status >> 8) > 2) || (($status & 0xff) != 0)) { + die ("unzip failed - unable to extract firmware"); + } +} + +sub unshield { + my ($sourcefile, $todir) = @_; + + system("unshield x -d \"$todir\" \"$sourcefile\" > /dev/null" ) and die ("unshield failed - unable to extract firmware"); +} + +sub verify { + my ($filename, $hash) = @_; + my ($testhash); + + open(CMD, "md5sum \"$filename\"|"); + $testhash = <CMD>; + $testhash =~ /([a-zA-Z0-9]*)/; + $testhash = $1; + close CMD; + die "Hash of extracted file does not match!\n" if ($testhash ne $hash); +} + +sub copy { + my ($from, $to) = @_; + + system("cp -f \"$from\" \"$to\"") and die ("cp failed"); +} + +sub extract { + my ($infile, $offset, $length, $outfile) = @_; + my ($chunklength, $buf, $rcount); + + open INFILE, "<$infile"; + open OUTFILE, ">$outfile"; + sysseek(INFILE, $offset, SEEK_SET); + while($length > 0) { + # Calc chunk size + $chunklength = 2048; + $chunklength = $length if ($chunklength > $length); + + $rcount = sysread(INFILE, $buf, $chunklength); + die "Ran out of data\n" if ($rcount != $chunklength); + syswrite(OUTFILE, $buf); + $length -= $rcount; + } + close INFILE; + close OUTFILE; +} + +sub appendfile { + my ($FH, $infile) = @_; + my ($buf); + + open INFILE, "<$infile"; + while(1) { + $rcount = sysread(INFILE, $buf, 2048); + last if ($rcount == 0); + print $FH $buf; + } + close(INFILE); +} + +sub delzero{ + my ($infile,$outfile) =@_; + + open INFILE,"<$infile"; + open OUTFILE,">$outfile"; + while (1){ + $rcount=sysread(INFILE,$buf,22); + $len=ord(substr($buf,0,1)); + print OUTFILE substr($buf,0,1); + print OUTFILE substr($buf,2,$len+3); + last if ($rcount<1); + printf OUTFILE "%c",0; +#print $len." ".length($buf)."\n"; + + } + close(INFILE); + close(OUTFILE); +} + +sub syntax() { + print STDERR "syntax: get_dvb_firmware <component>\n"; + print STDERR "Supported components:\n"; + @components = sort @components; + for($i=0; $i < scalar(@components); $i++) { + print STDERR "\t" . $components[$i] . "\n"; + } + exit(1); +} diff --git a/src/net/scripts/get_maintainer.pl b/src/net/scripts/get_maintainer.pl new file mode 100755 index 0000000..2075db0 --- /dev/null +++ b/src/net/scripts/get_maintainer.pl @@ -0,0 +1,2618 @@ +#!/usr/bin/env perl +# SPDX-License-Identifier: GPL-2.0 +# +# (c) 2007, Joe Perches <joe@perches.com> +# created from checkpatch.pl +# +# Print selected MAINTAINERS information for +# the files modified in a patch or for a file +# +# usage: perl scripts/get_maintainer.pl [OPTIONS] <patch> +# perl scripts/get_maintainer.pl [OPTIONS] -f <file> + +use warnings; +use strict; + +my $P = $0; +my $V = '0.26'; + +use Getopt::Long qw(:config no_auto_abbrev); +use Cwd; +use File::Find; +use File::Spec::Functions; + +my $cur_path = fastgetcwd() . '/'; +my $lk_path = "./"; +my $email = 1; +my $email_usename = 1; +my $email_maintainer = 1; +my $email_reviewer = 1; +my $email_fixes = 1; +my $email_list = 1; +my $email_moderated_list = 1; +my $email_subscriber_list = 0; +my $email_git_penguin_chiefs = 0; +my $email_git = 0; +my $email_git_all_signature_types = 0; +my $email_git_blame = 0; +my $email_git_blame_signatures = 1; +my $email_git_fallback = 1; +my $email_git_min_signatures = 1; +my $email_git_max_maintainers = 5; +my $email_git_min_percent = 5; +my $email_git_since = "1-year-ago"; +my $email_hg_since = "-365"; +my $interactive = 0; +my $email_remove_duplicates = 1; +my $email_use_mailmap = 1; +my $output_multiline = 1; +my $output_separator = ", "; +my $output_roles = 0; +my $output_rolestats = 1; +my $output_section_maxlen = 50; +my $scm = 0; +my $tree = 1; +my $web = 0; +my $subsystem = 0; +my $status = 0; +my $letters = ""; +my $keywords = 1; +my $sections = 0; +my $email_file_emails = 0; +my $from_filename = 0; +my $pattern_depth = 0; +my $self_test = undef; +my $version = 0; +my $help = 0; +my $find_maintainer_files = 0; +my $maintainer_path; +my $vcs_used = 0; + +my $exit = 0; + +my @files = (); +my @fixes = (); # If a patch description includes Fixes: lines +my @range = (); +my @keyword_tvi = (); +my @file_emails = (); + +my %commit_author_hash; +my %commit_signer_hash; + +my @penguin_chief = (); +push(@penguin_chief, "Linus Torvalds:torvalds\@linux-foundation.org"); +#Andrew wants in on most everything - 2009/01/14 +#push(@penguin_chief, "Andrew Morton:akpm\@linux-foundation.org"); + +my @penguin_chief_names = (); +foreach my $chief (@penguin_chief) { + if ($chief =~ m/^(.*):(.*)/) { + my $chief_name = $1; + my $chief_addr = $2; + push(@penguin_chief_names, $chief_name); + } +} +my $penguin_chiefs = "\(" . join("|", @penguin_chief_names) . "\)"; + +# Signature types of people who are either +# a) responsible for the code in question, or +# b) familiar enough with it to give relevant feedback +my @signature_tags = (); +push(@signature_tags, "Signed-off-by:"); +push(@signature_tags, "Reviewed-by:"); +push(@signature_tags, "Acked-by:"); + +my $signature_pattern = "\(" . join("|", @signature_tags) . "\)"; + +# rfc822 email address - preloaded methods go here. +my $rfc822_lwsp = "(?:(?:\\r\\n)?[ \\t])"; +my $rfc822_char = '[\\000-\\377]'; + +# VCS command support: class-like functions and strings + +my %VCS_cmds; + +my %VCS_cmds_git = ( + "execute_cmd" => \&git_execute_cmd, + "available" => '(which("git") ne "") && (-e ".git")', + "find_signers_cmd" => + "git log --no-color --follow --since=\$email_git_since " . + '--numstat --no-merges ' . + '--format="GitCommit: %H%n' . + 'GitAuthor: %an <%ae>%n' . + 'GitDate: %aD%n' . + 'GitSubject: %s%n' . + '%b%n"' . + " -- \$file", + "find_commit_signers_cmd" => + "git log --no-color " . + '--numstat ' . + '--format="GitCommit: %H%n' . + 'GitAuthor: %an <%ae>%n' . + 'GitDate: %aD%n' . + 'GitSubject: %s%n' . + '%b%n"' . + " -1 \$commit", + "find_commit_author_cmd" => + "git log --no-color " . + '--numstat ' . + '--format="GitCommit: %H%n' . + 'GitAuthor: %an <%ae>%n' . + 'GitDate: %aD%n' . + 'GitSubject: %s%n"' . + " -1 \$commit", + "blame_range_cmd" => "git blame -l -L \$diff_start,+\$diff_length \$file", + "blame_file_cmd" => "git blame -l \$file", + "commit_pattern" => "^GitCommit: ([0-9a-f]{40,40})", + "blame_commit_pattern" => "^([0-9a-f]+) ", + "author_pattern" => "^GitAuthor: (.*)", + "subject_pattern" => "^GitSubject: (.*)", + "stat_pattern" => "^(\\d+)\\t(\\d+)\\t\$file\$", + "file_exists_cmd" => "git ls-files \$file", + "list_files_cmd" => "git ls-files \$file", +); + +my %VCS_cmds_hg = ( + "execute_cmd" => \&hg_execute_cmd, + "available" => '(which("hg") ne "") && (-d ".hg")', + "find_signers_cmd" => + "hg log --date=\$email_hg_since " . + "--template='HgCommit: {node}\\n" . + "HgAuthor: {author}\\n" . + "HgSubject: {desc}\\n'" . + " -- \$file", + "find_commit_signers_cmd" => + "hg log " . + "--template='HgSubject: {desc}\\n'" . + " -r \$commit", + "find_commit_author_cmd" => + "hg log " . + "--template='HgCommit: {node}\\n" . + "HgAuthor: {author}\\n" . + "HgSubject: {desc|firstline}\\n'" . + " -r \$commit", + "blame_range_cmd" => "", # not supported + "blame_file_cmd" => "hg blame -n \$file", + "commit_pattern" => "^HgCommit: ([0-9a-f]{40,40})", + "blame_commit_pattern" => "^([ 0-9a-f]+):", + "author_pattern" => "^HgAuthor: (.*)", + "subject_pattern" => "^HgSubject: (.*)", + "stat_pattern" => "^(\\d+)\t(\\d+)\t\$file\$", + "file_exists_cmd" => "hg files \$file", + "list_files_cmd" => "hg manifest -R \$file", +); + +my $conf = which_conf(".get_maintainer.conf"); +if (-f $conf) { + my @conf_args; + open(my $conffile, '<', "$conf") + or warn "$P: Can't find a readable .get_maintainer.conf file $!\n"; + + while (<$conffile>) { + my $line = $_; + + $line =~ s/\s*\n?$//g; + $line =~ s/^\s*//g; + $line =~ s/\s+/ /g; + + next if ($line =~ m/^\s*#/); + next if ($line =~ m/^\s*$/); + + my @words = split(" ", $line); + foreach my $word (@words) { + last if ($word =~ m/^#/); + push (@conf_args, $word); + } + } + close($conffile); + unshift(@ARGV, @conf_args) if @conf_args; +} + +my @ignore_emails = (); +my $ignore_file = which_conf(".get_maintainer.ignore"); +if (-f $ignore_file) { + open(my $ignore, '<', "$ignore_file") + or warn "$P: Can't find a readable .get_maintainer.ignore file $!\n"; + while (<$ignore>) { + my $line = $_; + + $line =~ s/\s*\n?$//; + $line =~ s/^\s*//; + $line =~ s/\s+$//; + $line =~ s/#.*$//; + + next if ($line =~ m/^\s*$/); + if (rfc822_valid($line)) { + push(@ignore_emails, $line); + } + } + close($ignore); +} + +if ($#ARGV > 0) { + foreach (@ARGV) { + if ($_ =~ /^-{1,2}self-test(?:=|$)/) { + die "$P: using --self-test does not allow any other option or argument\n"; + } + } +} + +if (!GetOptions( + 'email!' => \$email, + 'git!' => \$email_git, + 'git-all-signature-types!' => \$email_git_all_signature_types, + 'git-blame!' => \$email_git_blame, + 'git-blame-signatures!' => \$email_git_blame_signatures, + 'git-fallback!' => \$email_git_fallback, + 'git-chief-penguins!' => \$email_git_penguin_chiefs, + 'git-min-signatures=i' => \$email_git_min_signatures, + 'git-max-maintainers=i' => \$email_git_max_maintainers, + 'git-min-percent=i' => \$email_git_min_percent, + 'git-since=s' => \$email_git_since, + 'hg-since=s' => \$email_hg_since, + 'i|interactive!' => \$interactive, + 'remove-duplicates!' => \$email_remove_duplicates, + 'mailmap!' => \$email_use_mailmap, + 'm!' => \$email_maintainer, + 'r!' => \$email_reviewer, + 'n!' => \$email_usename, + 'l!' => \$email_list, + 'fixes!' => \$email_fixes, + 'moderated!' => \$email_moderated_list, + 's!' => \$email_subscriber_list, + 'multiline!' => \$output_multiline, + 'roles!' => \$output_roles, + 'rolestats!' => \$output_rolestats, + 'separator=s' => \$output_separator, + 'subsystem!' => \$subsystem, + 'status!' => \$status, + 'scm!' => \$scm, + 'tree!' => \$tree, + 'web!' => \$web, + 'letters=s' => \$letters, + 'pattern-depth=i' => \$pattern_depth, + 'k|keywords!' => \$keywords, + 'sections!' => \$sections, + 'fe|file-emails!' => \$email_file_emails, + 'f|file' => \$from_filename, + 'find-maintainer-files' => \$find_maintainer_files, + 'mpath|maintainer-path=s' => \$maintainer_path, + 'self-test:s' => \$self_test, + 'v|version' => \$version, + 'h|help|usage' => \$help, + )) { + die "$P: invalid argument - use --help if necessary\n"; +} + +if ($help != 0) { + usage(); + exit 0; +} + +if ($version != 0) { + print("${P} ${V}\n"); + exit 0; +} + +if (defined $self_test) { + read_all_maintainer_files(); + self_test(); + exit 0; +} + +if (-t STDIN && !@ARGV) { + # We're talking to a terminal, but have no command line arguments. + die "$P: missing patchfile or -f file - use --help if necessary\n"; +} + +$output_multiline = 0 if ($output_separator ne ", "); +$output_rolestats = 1 if ($interactive); +$output_roles = 1 if ($output_rolestats); + +if ($sections || $letters ne "") { + $sections = 1; + $email = 0; + $email_list = 0; + $scm = 0; + $status = 0; + $subsystem = 0; + $web = 0; + $keywords = 0; + $interactive = 0; +} else { + my $selections = $email + $scm + $status + $subsystem + $web; + if ($selections == 0) { + die "$P: Missing required option: email, scm, status, subsystem or web\n"; + } +} + +if ($email && + ($email_maintainer + $email_reviewer + + $email_list + $email_subscriber_list + + $email_git + $email_git_penguin_chiefs + $email_git_blame) == 0) { + die "$P: Please select at least 1 email option\n"; +} + +if ($tree && !top_of_kernel_tree($lk_path)) { + die "$P: The current directory does not appear to be " + . "a linux kernel source tree.\n"; +} + +## Read MAINTAINERS for type/value pairs + +my @typevalue = (); +my %keyword_hash; +my @mfiles = (); +my @self_test_info = (); + +sub read_maintainer_file { + my ($file) = @_; + + open (my $maint, '<', "$file") + or die "$P: Can't open MAINTAINERS file '$file': $!\n"; + my $i = 1; + while (<$maint>) { + my $line = $_; + chomp $line; + + if ($line =~ m/^([A-Z]):\s*(.*)/) { + my $type = $1; + my $value = $2; + + ##Filename pattern matching + if ($type eq "F" || $type eq "X") { + $value =~ s@\.@\\\.@g; ##Convert . to \. + $value =~ s/\*/\.\*/g; ##Convert * to .* + $value =~ s/\?/\./g; ##Convert ? to . + ##if pattern is a directory and it lacks a trailing slash, add one + if ((-d $value)) { + $value =~ s@([^/])$@$1/@; + } + } elsif ($type eq "K") { + $keyword_hash{@typevalue} = $value; + } + push(@typevalue, "$type:$value"); + } elsif (!(/^\s*$/ || /^\s*\#/)) { + push(@typevalue, $line); + } + if (defined $self_test) { + push(@self_test_info, {file=>$file, linenr=>$i, line=>$line}); + } + $i++; + } + close($maint); +} + +sub find_is_maintainer_file { + my ($file) = $_; + return if ($file !~ m@/MAINTAINERS$@); + $file = $File::Find::name; + return if (! -f $file); + push(@mfiles, $file); +} + +sub find_ignore_git { + return grep { $_ !~ /^\.git$/; } @_; +} + +read_all_maintainer_files(); + +sub read_all_maintainer_files { + my $path = "${lk_path}MAINTAINERS"; + if (defined $maintainer_path) { + $path = $maintainer_path; + # Perl Cookbook tilde expansion if necessary + $path =~ s@^~([^/]*)@ $1 ? (getpwnam($1))[7] : ( $ENV{HOME} || $ENV{LOGDIR} || (getpwuid($<))[7])@ex; + } + + if (-d $path) { + $path .= '/' if ($path !~ m@/$@); + if ($find_maintainer_files) { + find( { wanted => \&find_is_maintainer_file, + preprocess => \&find_ignore_git, + no_chdir => 1, + }, "$path"); + } else { + opendir(DIR, "$path") or die $!; + my @files = readdir(DIR); + closedir(DIR); + foreach my $file (@files) { + push(@mfiles, "$path$file") if ($file !~ /^\./); + } + } + } elsif (-f "$path") { + push(@mfiles, "$path"); + } else { + die "$P: MAINTAINER file not found '$path'\n"; + } + die "$P: No MAINTAINER files found in '$path'\n" if (scalar(@mfiles) == 0); + foreach my $file (@mfiles) { + read_maintainer_file("$file"); + } +} + +sub maintainers_in_file { + my ($file) = @_; + + return if ($file =~ m@\bMAINTAINERS$@); + + if (-f $file && ($email_file_emails || $file =~ /\.yaml$/)) { + open(my $f, '<', $file) + or die "$P: Can't open $file: $!\n"; + my $text = do { local($/) ; <$f> }; + close($f); + + my @poss_addr = $text =~ m$[A-Za-zÀ-ÿ\"\' \,\.\+-]*\s*[\,]*\s*[\(\<\{]{0,1}[A-Za-z0-9_\.\+-]+\@[A-Za-z0-9\.-]+\.[A-Za-z0-9]+[\)\>\}]{0,1}$g; + push(@file_emails, clean_file_emails(@poss_addr)); + } +} + +# +# Read mail address map +# + +my $mailmap; + +read_mailmap(); + +sub read_mailmap { + $mailmap = { + names => {}, + addresses => {} + }; + + return if (!$email_use_mailmap || !(-f "${lk_path}.mailmap")); + + open(my $mailmap_file, '<', "${lk_path}.mailmap") + or warn "$P: Can't open .mailmap: $!\n"; + + while (<$mailmap_file>) { + s/#.*$//; #strip comments + s/^\s+|\s+$//g; #trim + + next if (/^\s*$/); #skip empty lines + #entries have one of the following formats: + # name1 <mail1> + # <mail1> <mail2> + # name1 <mail1> <mail2> + # name1 <mail1> name2 <mail2> + # (see man git-shortlog) + + if (/^([^<]+)<([^>]+)>$/) { + my $real_name = $1; + my $address = $2; + + $real_name =~ s/\s+$//; + ($real_name, $address) = parse_email("$real_name <$address>"); + $mailmap->{names}->{$address} = $real_name; + + } elsif (/^<([^>]+)>\s*<([^>]+)>$/) { + my $real_address = $1; + my $wrong_address = $2; + + $mailmap->{addresses}->{$wrong_address} = $real_address; + + } elsif (/^(.+)<([^>]+)>\s*<([^>]+)>$/) { + my $real_name = $1; + my $real_address = $2; + my $wrong_address = $3; + + $real_name =~ s/\s+$//; + ($real_name, $real_address) = + parse_email("$real_name <$real_address>"); + $mailmap->{names}->{$wrong_address} = $real_name; + $mailmap->{addresses}->{$wrong_address} = $real_address; + + } elsif (/^(.+)<([^>]+)>\s*(.+)\s*<([^>]+)>$/) { + my $real_name = $1; + my $real_address = $2; + my $wrong_name = $3; + my $wrong_address = $4; + + $real_name =~ s/\s+$//; + ($real_name, $real_address) = + parse_email("$real_name <$real_address>"); + + $wrong_name =~ s/\s+$//; + ($wrong_name, $wrong_address) = + parse_email("$wrong_name <$wrong_address>"); + + my $wrong_email = format_email($wrong_name, $wrong_address, 1); + $mailmap->{names}->{$wrong_email} = $real_name; + $mailmap->{addresses}->{$wrong_email} = $real_address; + } + } + close($mailmap_file); +} + +## use the filenames on the command line or find the filenames in the patchfiles + +if (!@ARGV) { + push(@ARGV, "&STDIN"); +} + +foreach my $file (@ARGV) { + if ($file ne "&STDIN") { + $file = canonpath($file); + ##if $file is a directory and it lacks a trailing slash, add one + if ((-d $file)) { + $file =~ s@([^/])$@$1/@; + } elsif (!(-f $file)) { + die "$P: file '${file}' not found\n"; + } + } + if ($from_filename && (vcs_exists() && !vcs_file_exists($file))) { + warn "$P: file '$file' not found in version control $!\n"; + } + if ($from_filename || ($file ne "&STDIN" && vcs_file_exists($file))) { + $file =~ s/^\Q${cur_path}\E//; #strip any absolute path + $file =~ s/^\Q${lk_path}\E//; #or the path to the lk tree + push(@files, $file); + if ($file ne "MAINTAINERS" && -f $file && $keywords) { + open(my $f, '<', $file) + or die "$P: Can't open $file: $!\n"; + my $text = do { local($/) ; <$f> }; + close($f); + if ($keywords) { + foreach my $line (keys %keyword_hash) { + if ($text =~ m/$keyword_hash{$line}/x) { + push(@keyword_tvi, $line); + } + } + } + } + } else { + my $file_cnt = @files; + my $lastfile; + + open(my $patch, "< $file") + or die "$P: Can't open $file: $!\n"; + + # We can check arbitrary information before the patch + # like the commit message, mail headers, etc... + # This allows us to match arbitrary keywords against any part + # of a git format-patch generated file (subject tags, etc...) + + my $patch_prefix = ""; #Parsing the intro + + while (<$patch>) { + my $patch_line = $_; + if (m/^ mode change [0-7]+ => [0-7]+ (\S+)\s*$/) { + my $filename = $1; + push(@files, $filename); + } elsif (m/^rename (?:from|to) (\S+)\s*$/) { + my $filename = $1; + push(@files, $filename); + } elsif (m/^diff --git a\/(\S+) b\/(\S+)\s*$/) { + my $filename1 = $1; + my $filename2 = $2; + push(@files, $filename1); + push(@files, $filename2); + } elsif (m/^Fixes:\s+([0-9a-fA-F]{6,40})/) { + push(@fixes, $1) if ($email_fixes); + } elsif (m/^\+\+\+\s+(\S+)/ or m/^---\s+(\S+)/) { + my $filename = $1; + $filename =~ s@^[^/]*/@@; + $filename =~ s@\n@@; + $lastfile = $filename; + push(@files, $filename); + $patch_prefix = "^[+-].*"; #Now parsing the actual patch + } elsif (m/^\@\@ -(\d+),(\d+)/) { + if ($email_git_blame) { + push(@range, "$lastfile:$1:$2"); + } + } elsif ($keywords) { + foreach my $line (keys %keyword_hash) { + if ($patch_line =~ m/${patch_prefix}$keyword_hash{$line}/x) { + push(@keyword_tvi, $line); + } + } + } + } + close($patch); + + if ($file_cnt == @files) { + warn "$P: file '${file}' doesn't appear to be a patch. " + . "Add -f to options?\n"; + } + @files = sort_and_uniq(@files); + } +} + +@file_emails = uniq(@file_emails); +@fixes = uniq(@fixes); + +my %email_hash_name; +my %email_hash_address; +my @email_to = (); +my %hash_list_to; +my @list_to = (); +my @scm = (); +my @web = (); +my @subsystem = (); +my @status = (); +my %deduplicate_name_hash = (); +my %deduplicate_address_hash = (); + +my @maintainers = get_maintainers(); +if (@maintainers) { + @maintainers = merge_email(@maintainers); + output(@maintainers); +} + +if ($scm) { + @scm = uniq(@scm); + output(@scm); +} + +if ($status) { + @status = uniq(@status); + output(@status); +} + +if ($subsystem) { + @subsystem = uniq(@subsystem); + output(@subsystem); +} + +if ($web) { + @web = uniq(@web); + output(@web); +} + +exit($exit); + +sub self_test { + my @lsfiles = (); + my @good_links = (); + my @bad_links = (); + my @section_headers = (); + my $index = 0; + + @lsfiles = vcs_list_files($lk_path); + + for my $x (@self_test_info) { + $index++; + + ## Section header duplication and missing section content + if (($self_test eq "" || $self_test =~ /\bsections\b/) && + $x->{line} =~ /^\S[^:]/ && + defined $self_test_info[$index] && + $self_test_info[$index]->{line} =~ /^([A-Z]):\s*\S/) { + my $has_S = 0; + my $has_F = 0; + my $has_ML = 0; + my $status = ""; + if (grep(m@^\Q$x->{line}\E@, @section_headers)) { + print("$x->{file}:$x->{linenr}: warning: duplicate section header\t$x->{line}\n"); + } else { + push(@section_headers, $x->{line}); + } + my $nextline = $index; + while (defined $self_test_info[$nextline] && + $self_test_info[$nextline]->{line} =~ /^([A-Z]):\s*(\S.*)/) { + my $type = $1; + my $value = $2; + if ($type eq "S") { + $has_S = 1; + $status = $value; + } elsif ($type eq "F" || $type eq "N") { + $has_F = 1; + } elsif ($type eq "M" || $type eq "R" || $type eq "L") { + $has_ML = 1; + } + $nextline++; + } + if (!$has_ML && $status !~ /orphan|obsolete/i) { + print("$x->{file}:$x->{linenr}: warning: section without email address\t$x->{line}\n"); + } + if (!$has_S) { + print("$x->{file}:$x->{linenr}: warning: section without status \t$x->{line}\n"); + } + if (!$has_F) { + print("$x->{file}:$x->{linenr}: warning: section without file pattern\t$x->{line}\n"); + } + } + + next if ($x->{line} !~ /^([A-Z]):\s*(.*)/); + + my $type = $1; + my $value = $2; + + ## Filename pattern matching + if (($type eq "F" || $type eq "X") && + ($self_test eq "" || $self_test =~ /\bpatterns\b/)) { + $value =~ s@\.@\\\.@g; ##Convert . to \. + $value =~ s/\*/\.\*/g; ##Convert * to .* + $value =~ s/\?/\./g; ##Convert ? to . + ##if pattern is a directory and it lacks a trailing slash, add one + if ((-d $value)) { + $value =~ s@([^/])$@$1/@; + } + if (!grep(m@^$value@, @lsfiles)) { + print("$x->{file}:$x->{linenr}: warning: no file matches\t$x->{line}\n"); + } + + ## Link reachability + } elsif (($type eq "W" || $type eq "Q" || $type eq "B") && + $value =~ /^https?:/ && + ($self_test eq "" || $self_test =~ /\blinks\b/)) { + next if (grep(m@^\Q$value\E$@, @good_links)); + my $isbad = 0; + if (grep(m@^\Q$value\E$@, @bad_links)) { + $isbad = 1; + } else { + my $output = `wget --spider -q --no-check-certificate --timeout 10 --tries 1 $value`; + if ($? == 0) { + push(@good_links, $value); + } else { + push(@bad_links, $value); + $isbad = 1; + } + } + if ($isbad) { + print("$x->{file}:$x->{linenr}: warning: possible bad link\t$x->{line}\n"); + } + + ## SCM reachability + } elsif ($type eq "T" && + ($self_test eq "" || $self_test =~ /\bscm\b/)) { + next if (grep(m@^\Q$value\E$@, @good_links)); + my $isbad = 0; + if (grep(m@^\Q$value\E$@, @bad_links)) { + $isbad = 1; + } elsif ($value !~ /^(?:git|quilt|hg)\s+\S/) { + print("$x->{file}:$x->{linenr}: warning: malformed entry\t$x->{line}\n"); + } elsif ($value =~ /^git\s+(\S+)(\s+([^\(]+\S+))?/) { + my $url = $1; + my $branch = ""; + $branch = $3 if $3; + my $output = `git ls-remote --exit-code -h "$url" $branch > /dev/null 2>&1`; + if ($? == 0) { + push(@good_links, $value); + } else { + push(@bad_links, $value); + $isbad = 1; + } + } elsif ($value =~ /^(?:quilt|hg)\s+(https?:\S+)/) { + my $url = $1; + my $output = `wget --spider -q --no-check-certificate --timeout 10 --tries 1 $url`; + if ($? == 0) { + push(@good_links, $value); + } else { + push(@bad_links, $value); + $isbad = 1; + } + } + if ($isbad) { + print("$x->{file}:$x->{linenr}: warning: possible bad link\t$x->{line}\n"); + } + } + } +} + +sub ignore_email_address { + my ($address) = @_; + + foreach my $ignore (@ignore_emails) { + return 1 if ($ignore eq $address); + } + + return 0; +} + +sub range_is_maintained { + my ($start, $end) = @_; + + for (my $i = $start; $i < $end; $i++) { + my $line = $typevalue[$i]; + if ($line =~ m/^([A-Z]):\s*(.*)/) { + my $type = $1; + my $value = $2; + if ($type eq 'S') { + if ($value =~ /(maintain|support)/i) { + return 1; + } + } + } + } + return 0; +} + +sub range_has_maintainer { + my ($start, $end) = @_; + + for (my $i = $start; $i < $end; $i++) { + my $line = $typevalue[$i]; + if ($line =~ m/^([A-Z]):\s*(.*)/) { + my $type = $1; + my $value = $2; + if ($type eq 'M') { + return 1; + } + } + } + return 0; +} + +sub get_maintainers { + %email_hash_name = (); + %email_hash_address = (); + %commit_author_hash = (); + %commit_signer_hash = (); + @email_to = (); + %hash_list_to = (); + @list_to = (); + @scm = (); + @web = (); + @subsystem = (); + @status = (); + %deduplicate_name_hash = (); + %deduplicate_address_hash = (); + if ($email_git_all_signature_types) { + $signature_pattern = "(.+?)[Bb][Yy]:"; + } else { + $signature_pattern = "\(" . join("|", @signature_tags) . "\)"; + } + + # Find responsible parties + + my %exact_pattern_match_hash = (); + + foreach my $file (@files) { + + my %hash; + my $tvi = find_first_section(); + while ($tvi < @typevalue) { + my $start = find_starting_index($tvi); + my $end = find_ending_index($tvi); + my $exclude = 0; + my $i; + + #Do not match excluded file patterns + + for ($i = $start; $i < $end; $i++) { + my $line = $typevalue[$i]; + if ($line =~ m/^([A-Z]):\s*(.*)/) { + my $type = $1; + my $value = $2; + if ($type eq 'X') { + if (file_match_pattern($file, $value)) { + $exclude = 1; + last; + } + } + } + } + + if (!$exclude) { + for ($i = $start; $i < $end; $i++) { + my $line = $typevalue[$i]; + if ($line =~ m/^([A-Z]):\s*(.*)/) { + my $type = $1; + my $value = $2; + if ($type eq 'F') { + if (file_match_pattern($file, $value)) { + my $value_pd = ($value =~ tr@/@@); + my $file_pd = ($file =~ tr@/@@); + $value_pd++ if (substr($value,-1,1) ne "/"); + $value_pd = -1 if ($value =~ /^\.\*/); + if ($value_pd >= $file_pd && + range_is_maintained($start, $end) && + range_has_maintainer($start, $end)) { + $exact_pattern_match_hash{$file} = 1; + } + if ($pattern_depth == 0 || + (($file_pd - $value_pd) < $pattern_depth)) { + $hash{$tvi} = $value_pd; + } + } + } elsif ($type eq 'N') { + if ($file =~ m/$value/x) { + $hash{$tvi} = 0; + } + } + } + } + } + $tvi = $end + 1; + } + + foreach my $line (sort {$hash{$b} <=> $hash{$a}} keys %hash) { + add_categories($line); + if ($sections) { + my $i; + my $start = find_starting_index($line); + my $end = find_ending_index($line); + for ($i = $start; $i < $end; $i++) { + my $line = $typevalue[$i]; + if ($line =~ /^[FX]:/) { ##Restore file patterns + $line =~ s/([^\\])\.([^\*])/$1\?$2/g; + $line =~ s/([^\\])\.$/$1\?/g; ##Convert . back to ? + $line =~ s/\\\./\./g; ##Convert \. to . + $line =~ s/\.\*/\*/g; ##Convert .* to * + } + my $count = $line =~ s/^([A-Z]):/$1:\t/g; + if ($letters eq "" || (!$count || $letters =~ /$1/i)) { + print("$line\n"); + } + } + print("\n"); + } + } + + maintainers_in_file($file); + } + + if ($keywords) { + @keyword_tvi = sort_and_uniq(@keyword_tvi); + foreach my $line (@keyword_tvi) { + add_categories($line); + } + } + + foreach my $email (@email_to, @list_to) { + $email->[0] = deduplicate_email($email->[0]); + } + + foreach my $file (@files) { + if ($email && + ($email_git || + ($email_git_fallback && + $file !~ /MAINTAINERS$/ && + !$exact_pattern_match_hash{$file}))) { + vcs_file_signoffs($file); + } + if ($email && $email_git_blame) { + vcs_file_blame($file); + } + } + + if ($email) { + foreach my $chief (@penguin_chief) { + if ($chief =~ m/^(.*):(.*)/) { + my $email_address; + + $email_address = format_email($1, $2, $email_usename); + if ($email_git_penguin_chiefs) { + push(@email_to, [$email_address, 'chief penguin']); + } else { + @email_to = grep($_->[0] !~ /${email_address}/, @email_to); + } + } + } + + foreach my $email (@file_emails) { + my ($name, $address) = parse_email($email); + + my $tmp_email = format_email($name, $address, $email_usename); + push_email_address($tmp_email, ''); + add_role($tmp_email, 'in file'); + } + } + + foreach my $fix (@fixes) { + vcs_add_commit_signers($fix, "blamed_fixes"); + } + + my @to = (); + if ($email || $email_list) { + if ($email) { + @to = (@to, @email_to); + } + if ($email_list) { + @to = (@to, @list_to); + } + } + + if ($interactive) { + @to = interactive_get_maintainers(\@to); + } + + return @to; +} + +sub file_match_pattern { + my ($file, $pattern) = @_; + if (substr($pattern, -1) eq "/") { + if ($file =~ m@^$pattern@) { + return 1; + } + } else { + if ($file =~ m@^$pattern@) { + my $s1 = ($file =~ tr@/@@); + my $s2 = ($pattern =~ tr@/@@); + if ($s1 == $s2) { + return 1; + } + } + } + return 0; +} + +sub usage { + print <<EOT; +usage: $P [options] patchfile + $P [options] -f file|directory +version: $V + +MAINTAINER field selection options: + --email => print email address(es) if any + --git => include recent git \*-by: signers + --git-all-signature-types => include signers regardless of signature type + or use only ${signature_pattern} signers (default: $email_git_all_signature_types) + --git-fallback => use git when no exact MAINTAINERS pattern (default: $email_git_fallback) + --git-chief-penguins => include ${penguin_chiefs} + --git-min-signatures => number of signatures required (default: $email_git_min_signatures) + --git-max-maintainers => maximum maintainers to add (default: $email_git_max_maintainers) + --git-min-percent => minimum percentage of commits required (default: $email_git_min_percent) + --git-blame => use git blame to find modified commits for patch or file + --git-blame-signatures => when used with --git-blame, also include all commit signers + --git-since => git history to use (default: $email_git_since) + --hg-since => hg history to use (default: $email_hg_since) + --interactive => display a menu (mostly useful if used with the --git option) + --m => include maintainer(s) if any + --r => include reviewer(s) if any + --n => include name 'Full Name <addr\@domain.tld>' + --l => include list(s) if any + --moderated => include moderated lists(s) if any (default: true) + --s => include subscriber only list(s) if any (default: false) + --remove-duplicates => minimize duplicate email names/addresses + --roles => show roles (status:subsystem, git-signer, list, etc...) + --rolestats => show roles and statistics (commits/total_commits, %) + --file-emails => add email addresses found in -f file (default: 0 (off)) + --fixes => for patches, add signatures of commits with 'Fixes: <commit>' (default: 1 (on)) + --scm => print SCM tree(s) if any + --status => print status if any + --subsystem => print subsystem name if any + --web => print website(s) if any + +Output type options: + --separator [, ] => separator for multiple entries on 1 line + using --separator also sets --nomultiline if --separator is not [, ] + --multiline => print 1 entry per line + +Other options: + --pattern-depth => Number of pattern directory traversals (default: 0 (all)) + --keywords => scan patch for keywords (default: $keywords) + --sections => print all of the subsystem sections with pattern matches + --letters => print all matching 'letter' types from all matching sections + --mailmap => use .mailmap file (default: $email_use_mailmap) + --no-tree => run without a kernel tree + --self-test => show potential issues with MAINTAINERS file content + --version => show version + --help => show this help information + +Default options: + [--email --tree --nogit --git-fallback --m --r --n --l --multiline + --pattern-depth=0 --remove-duplicates --rolestats] + +Notes: + Using "-f directory" may give unexpected results: + Used with "--git", git signators for _all_ files in and below + directory are examined as git recurses directories. + Any specified X: (exclude) pattern matches are _not_ ignored. + Used with "--nogit", directory is used as a pattern match, + no individual file within the directory or subdirectory + is matched. + Used with "--git-blame", does not iterate all files in directory + Using "--git-blame" is slow and may add old committers and authors + that are no longer active maintainers to the output. + Using "--roles" or "--rolestats" with git send-email --cc-cmd or any + other automated tools that expect only ["name"] <email address> + may not work because of additional output after <email address>. + Using "--rolestats" and "--git-blame" shows the #/total=% commits, + not the percentage of the entire file authored. # of commits is + not a good measure of amount of code authored. 1 major commit may + contain a thousand lines, 5 trivial commits may modify a single line. + If git is not installed, but mercurial (hg) is installed and an .hg + repository exists, the following options apply to mercurial: + --git, + --git-min-signatures, --git-max-maintainers, --git-min-percent, and + --git-blame + Use --hg-since not --git-since to control date selection + File ".get_maintainer.conf", if it exists in the linux kernel source root + directory, can change whatever get_maintainer defaults are desired. + Entries in this file can be any command line argument. + This file is prepended to any additional command line arguments. + Multiple lines and # comments are allowed. + Most options have both positive and negative forms. + The negative forms for --<foo> are --no<foo> and --no-<foo>. + +EOT +} + +sub top_of_kernel_tree { + my ($lk_path) = @_; + + if ($lk_path ne "" && substr($lk_path,length($lk_path)-1,1) ne "/") { + $lk_path .= "/"; + } + if ( (-f "${lk_path}COPYING") + && (-f "${lk_path}CREDITS") + && (-f "${lk_path}Kbuild") + && (-e "${lk_path}MAINTAINERS") + && (-f "${lk_path}Makefile") + && (-f "${lk_path}README") + && (-d "${lk_path}Documentation") + && (-d "${lk_path}arch") + && (-d "${lk_path}include") + && (-d "${lk_path}drivers") + && (-d "${lk_path}fs") + && (-d "${lk_path}init") + && (-d "${lk_path}ipc") + && (-d "${lk_path}kernel") + && (-d "${lk_path}lib") + && (-d "${lk_path}scripts")) { + return 1; + } + return 0; +} + +sub parse_email { + my ($formatted_email) = @_; + + my $name = ""; + my $address = ""; + + if ($formatted_email =~ /^([^<]+)<(.+\@.*)>.*$/) { + $name = $1; + $address = $2; + } elsif ($formatted_email =~ /^\s*<(.+\@\S*)>.*$/) { + $address = $1; + } elsif ($formatted_email =~ /^(.+\@\S*).*$/) { + $address = $1; + } + + $name =~ s/^\s+|\s+$//g; + $name =~ s/^\"|\"$//g; + $address =~ s/^\s+|\s+$//g; + + if ($name =~ /[^\w \-]/i) { ##has "must quote" chars + $name =~ s/(?<!\\)"/\\"/g; ##escape quotes + $name = "\"$name\""; + } + + return ($name, $address); +} + +sub format_email { + my ($name, $address, $usename) = @_; + + my $formatted_email; + + $name =~ s/^\s+|\s+$//g; + $name =~ s/^\"|\"$//g; + $address =~ s/^\s+|\s+$//g; + + if ($name =~ /[^\w \-]/i) { ##has "must quote" chars + $name =~ s/(?<!\\)"/\\"/g; ##escape quotes + $name = "\"$name\""; + } + + if ($usename) { + if ("$name" eq "") { + $formatted_email = "$address"; + } else { + $formatted_email = "$name <$address>"; + } + } else { + $formatted_email = $address; + } + + return $formatted_email; +} + +sub find_first_section { + my $index = 0; + + while ($index < @typevalue) { + my $tv = $typevalue[$index]; + if (($tv =~ m/^([A-Z]):\s*(.*)/)) { + last; + } + $index++; + } + + return $index; +} + +sub find_starting_index { + my ($index) = @_; + + while ($index > 0) { + my $tv = $typevalue[$index]; + if (!($tv =~ m/^([A-Z]):\s*(.*)/)) { + last; + } + $index--; + } + + return $index; +} + +sub find_ending_index { + my ($index) = @_; + + while ($index < @typevalue) { + my $tv = $typevalue[$index]; + if (!($tv =~ m/^([A-Z]):\s*(.*)/)) { + last; + } + $index++; + } + + return $index; +} + +sub get_subsystem_name { + my ($index) = @_; + + my $start = find_starting_index($index); + + my $subsystem = $typevalue[$start]; + if ($output_section_maxlen && length($subsystem) > $output_section_maxlen) { + $subsystem = substr($subsystem, 0, $output_section_maxlen - 3); + $subsystem =~ s/\s*$//; + $subsystem = $subsystem . "..."; + } + return $subsystem; +} + +sub get_maintainer_role { + my ($index) = @_; + + my $i; + my $start = find_starting_index($index); + my $end = find_ending_index($index); + + my $role = "unknown"; + my $subsystem = get_subsystem_name($index); + + for ($i = $start + 1; $i < $end; $i++) { + my $tv = $typevalue[$i]; + if ($tv =~ m/^([A-Z]):\s*(.*)/) { + my $ptype = $1; + my $pvalue = $2; + if ($ptype eq "S") { + $role = $pvalue; + } + } + } + + $role = lc($role); + if ($role eq "supported") { + $role = "supporter"; + } elsif ($role eq "maintained") { + $role = "maintainer"; + } elsif ($role eq "odd fixes") { + $role = "odd fixer"; + } elsif ($role eq "orphan") { + $role = "orphan minder"; + } elsif ($role eq "obsolete") { + $role = "obsolete minder"; + } elsif ($role eq "buried alive in reporters") { + $role = "chief penguin"; + } + + return $role . ":" . $subsystem; +} + +sub get_list_role { + my ($index) = @_; + + my $subsystem = get_subsystem_name($index); + + if ($subsystem eq "THE REST") { + $subsystem = ""; + } + + return $subsystem; +} + +sub add_categories { + my ($index) = @_; + + my $i; + my $start = find_starting_index($index); + my $end = find_ending_index($index); + + push(@subsystem, $typevalue[$start]); + + for ($i = $start + 1; $i < $end; $i++) { + my $tv = $typevalue[$i]; + if ($tv =~ m/^([A-Z]):\s*(.*)/) { + my $ptype = $1; + my $pvalue = $2; + if ($ptype eq "L") { + my $list_address = $pvalue; + my $list_additional = ""; + my $list_role = get_list_role($i); + + if ($list_role ne "") { + $list_role = ":" . $list_role; + } + if ($list_address =~ m/([^\s]+)\s+(.*)$/) { + $list_address = $1; + $list_additional = $2; + } + if ($list_additional =~ m/subscribers-only/) { + if ($email_subscriber_list) { + if (!$hash_list_to{lc($list_address)}) { + $hash_list_to{lc($list_address)} = 1; + push(@list_to, [$list_address, + "subscriber list${list_role}"]); + } + } + } else { + if ($email_list) { + if (!$hash_list_to{lc($list_address)}) { + if ($list_additional =~ m/moderated/) { + if ($email_moderated_list) { + $hash_list_to{lc($list_address)} = 1; + push(@list_to, [$list_address, + "moderated list${list_role}"]); + } + } else { + $hash_list_to{lc($list_address)} = 1; + push(@list_to, [$list_address, + "open list${list_role}"]); + } + } + } + } + } elsif ($ptype eq "M") { + if ($email_maintainer) { + my $role = get_maintainer_role($i); + push_email_addresses($pvalue, $role); + } + } elsif ($ptype eq "R") { + if ($email_reviewer) { + my $subsystem = get_subsystem_name($i); + push_email_addresses($pvalue, "reviewer:$subsystem"); + } + } elsif ($ptype eq "T") { + push(@scm, $pvalue); + } elsif ($ptype eq "W") { + push(@web, $pvalue); + } elsif ($ptype eq "S") { + push(@status, $pvalue); + } + } + } +} + +sub email_inuse { + my ($name, $address) = @_; + + return 1 if (($name eq "") && ($address eq "")); + return 1 if (($name ne "") && exists($email_hash_name{lc($name)})); + return 1 if (($address ne "") && exists($email_hash_address{lc($address)})); + + return 0; +} + +sub push_email_address { + my ($line, $role) = @_; + + my ($name, $address) = parse_email($line); + + if ($address eq "") { + return 0; + } + + if (!$email_remove_duplicates) { + push(@email_to, [format_email($name, $address, $email_usename), $role]); + } elsif (!email_inuse($name, $address)) { + push(@email_to, [format_email($name, $address, $email_usename), $role]); + $email_hash_name{lc($name)}++ if ($name ne ""); + $email_hash_address{lc($address)}++; + } + + return 1; +} + +sub push_email_addresses { + my ($address, $role) = @_; + + my @address_list = (); + + if (rfc822_valid($address)) { + push_email_address($address, $role); + } elsif (@address_list = rfc822_validlist($address)) { + my $array_count = shift(@address_list); + while (my $entry = shift(@address_list)) { + push_email_address($entry, $role); + } + } else { + if (!push_email_address($address, $role)) { + warn("Invalid MAINTAINERS address: '" . $address . "'\n"); + } + } +} + +sub add_role { + my ($line, $role) = @_; + + my ($name, $address) = parse_email($line); + my $email = format_email($name, $address, $email_usename); + + foreach my $entry (@email_to) { + if ($email_remove_duplicates) { + my ($entry_name, $entry_address) = parse_email($entry->[0]); + if (($name eq $entry_name || $address eq $entry_address) + && ($role eq "" || !($entry->[1] =~ m/$role/)) + ) { + if ($entry->[1] eq "") { + $entry->[1] = "$role"; + } else { + $entry->[1] = "$entry->[1],$role"; + } + } + } else { + if ($email eq $entry->[0] + && ($role eq "" || !($entry->[1] =~ m/$role/)) + ) { + if ($entry->[1] eq "") { + $entry->[1] = "$role"; + } else { + $entry->[1] = "$entry->[1],$role"; + } + } + } + } +} + +sub which { + my ($bin) = @_; + + foreach my $path (split(/:/, $ENV{PATH})) { + if (-e "$path/$bin") { + return "$path/$bin"; + } + } + + return ""; +} + +sub which_conf { + my ($conf) = @_; + + foreach my $path (split(/:/, ".:$ENV{HOME}:.scripts")) { + if (-e "$path/$conf") { + return "$path/$conf"; + } + } + + return ""; +} + +sub mailmap_email { + my ($line) = @_; + + my ($name, $address) = parse_email($line); + my $email = format_email($name, $address, 1); + my $real_name = $name; + my $real_address = $address; + + if (exists $mailmap->{names}->{$email} || + exists $mailmap->{addresses}->{$email}) { + if (exists $mailmap->{names}->{$email}) { + $real_name = $mailmap->{names}->{$email}; + } + if (exists $mailmap->{addresses}->{$email}) { + $real_address = $mailmap->{addresses}->{$email}; + } + } else { + if (exists $mailmap->{names}->{$address}) { + $real_name = $mailmap->{names}->{$address}; + } + if (exists $mailmap->{addresses}->{$address}) { + $real_address = $mailmap->{addresses}->{$address}; + } + } + return format_email($real_name, $real_address, 1); +} + +sub mailmap { + my (@addresses) = @_; + + my @mapped_emails = (); + foreach my $line (@addresses) { + push(@mapped_emails, mailmap_email($line)); + } + merge_by_realname(@mapped_emails) if ($email_use_mailmap); + return @mapped_emails; +} + +sub merge_by_realname { + my %address_map; + my (@emails) = @_; + + foreach my $email (@emails) { + my ($name, $address) = parse_email($email); + if (exists $address_map{$name}) { + $address = $address_map{$name}; + $email = format_email($name, $address, 1); + } else { + $address_map{$name} = $address; + } + } +} + +sub git_execute_cmd { + my ($cmd) = @_; + my @lines = (); + + my $output = `$cmd`; + $output =~ s/^\s*//gm; + @lines = split("\n", $output); + + return @lines; +} + +sub hg_execute_cmd { + my ($cmd) = @_; + my @lines = (); + + my $output = `$cmd`; + @lines = split("\n", $output); + + return @lines; +} + +sub extract_formatted_signatures { + my (@signature_lines) = @_; + + my @type = @signature_lines; + + s/\s*(.*):.*/$1/ for (@type); + + # cut -f2- -d":" + s/\s*.*:\s*(.+)\s*/$1/ for (@signature_lines); + +## Reformat email addresses (with names) to avoid badly written signatures + + foreach my $signer (@signature_lines) { + $signer = deduplicate_email($signer); + } + + return (\@type, \@signature_lines); +} + +sub vcs_find_signers { + my ($cmd, $file) = @_; + my $commits; + my @lines = (); + my @signatures = (); + my @authors = (); + my @stats = (); + + @lines = &{$VCS_cmds{"execute_cmd"}}($cmd); + + my $pattern = $VCS_cmds{"commit_pattern"}; + my $author_pattern = $VCS_cmds{"author_pattern"}; + my $stat_pattern = $VCS_cmds{"stat_pattern"}; + + $stat_pattern =~ s/(\$\w+)/$1/eeg; #interpolate $stat_pattern + + $commits = grep(/$pattern/, @lines); # of commits + + @authors = grep(/$author_pattern/, @lines); + @signatures = grep(/^[ \t]*${signature_pattern}.*\@.*$/, @lines); + @stats = grep(/$stat_pattern/, @lines); + +# print("stats: <@stats>\n"); + + return (0, \@signatures, \@authors, \@stats) if !@signatures; + + save_commits_by_author(@lines) if ($interactive); + save_commits_by_signer(@lines) if ($interactive); + + if (!$email_git_penguin_chiefs) { + @signatures = grep(!/${penguin_chiefs}/i, @signatures); + } + + my ($author_ref, $authors_ref) = extract_formatted_signatures(@authors); + my ($types_ref, $signers_ref) = extract_formatted_signatures(@signatures); + + return ($commits, $signers_ref, $authors_ref, \@stats); +} + +sub vcs_find_author { + my ($cmd) = @_; + my @lines = (); + + @lines = &{$VCS_cmds{"execute_cmd"}}($cmd); + + if (!$email_git_penguin_chiefs) { + @lines = grep(!/${penguin_chiefs}/i, @lines); + } + + return @lines if !@lines; + + my @authors = (); + foreach my $line (@lines) { + if ($line =~ m/$VCS_cmds{"author_pattern"}/) { + my $author = $1; + my ($name, $address) = parse_email($author); + $author = format_email($name, $address, 1); + push(@authors, $author); + } + } + + save_commits_by_author(@lines) if ($interactive); + save_commits_by_signer(@lines) if ($interactive); + + return @authors; +} + +sub vcs_save_commits { + my ($cmd) = @_; + my @lines = (); + my @commits = (); + + @lines = &{$VCS_cmds{"execute_cmd"}}($cmd); + + foreach my $line (@lines) { + if ($line =~ m/$VCS_cmds{"blame_commit_pattern"}/) { + push(@commits, $1); + } + } + + return @commits; +} + +sub vcs_blame { + my ($file) = @_; + my $cmd; + my @commits = (); + + return @commits if (!(-f $file)); + + if (@range && $VCS_cmds{"blame_range_cmd"} eq "") { + my @all_commits = (); + + $cmd = $VCS_cmds{"blame_file_cmd"}; + $cmd =~ s/(\$\w+)/$1/eeg; #interpolate $cmd + @all_commits = vcs_save_commits($cmd); + + foreach my $file_range_diff (@range) { + next if (!($file_range_diff =~ m/(.+):(.+):(.+)/)); + my $diff_file = $1; + my $diff_start = $2; + my $diff_length = $3; + next if ("$file" ne "$diff_file"); + for (my $i = $diff_start; $i < $diff_start + $diff_length; $i++) { + push(@commits, $all_commits[$i]); + } + } + } elsif (@range) { + foreach my $file_range_diff (@range) { + next if (!($file_range_diff =~ m/(.+):(.+):(.+)/)); + my $diff_file = $1; + my $diff_start = $2; + my $diff_length = $3; + next if ("$file" ne "$diff_file"); + $cmd = $VCS_cmds{"blame_range_cmd"}; + $cmd =~ s/(\$\w+)/$1/eeg; #interpolate $cmd + push(@commits, vcs_save_commits($cmd)); + } + } else { + $cmd = $VCS_cmds{"blame_file_cmd"}; + $cmd =~ s/(\$\w+)/$1/eeg; #interpolate $cmd + @commits = vcs_save_commits($cmd); + } + + foreach my $commit (@commits) { + $commit =~ s/^\^//g; + } + + return @commits; +} + +my $printed_novcs = 0; +sub vcs_exists { + %VCS_cmds = %VCS_cmds_git; + return 1 if eval $VCS_cmds{"available"}; + %VCS_cmds = %VCS_cmds_hg; + return 2 if eval $VCS_cmds{"available"}; + %VCS_cmds = (); + if (!$printed_novcs) { + warn("$P: No supported VCS found. Add --nogit to options?\n"); + warn("Using a git repository produces better results.\n"); + warn("Try Linus Torvalds' latest git repository using:\n"); + warn("git clone git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git\n"); + $printed_novcs = 1; + } + return 0; +} + +sub vcs_is_git { + vcs_exists(); + return $vcs_used == 1; +} + +sub vcs_is_hg { + return $vcs_used == 2; +} + +sub vcs_add_commit_signers { + return if (!vcs_exists()); + + my ($commit, $desc) = @_; + my $commit_count = 0; + my $commit_authors_ref; + my $commit_signers_ref; + my $stats_ref; + my @commit_authors = (); + my @commit_signers = (); + my $cmd; + + $cmd = $VCS_cmds{"find_commit_signers_cmd"}; + $cmd =~ s/(\$\w+)/$1/eeg; #substitute variables in $cmd + + ($commit_count, $commit_signers_ref, $commit_authors_ref, $stats_ref) = vcs_find_signers($cmd, ""); + @commit_authors = @{$commit_authors_ref} if defined $commit_authors_ref; + @commit_signers = @{$commit_signers_ref} if defined $commit_signers_ref; + + foreach my $signer (@commit_signers) { + $signer = deduplicate_email($signer); + } + + vcs_assign($desc, 1, @commit_signers); +} + +sub interactive_get_maintainers { + my ($list_ref) = @_; + my @list = @$list_ref; + + vcs_exists(); + + my %selected; + my %authored; + my %signed; + my $count = 0; + my $maintained = 0; + foreach my $entry (@list) { + $maintained = 1 if ($entry->[1] =~ /^(maintainer|supporter)/i); + $selected{$count} = 1; + $authored{$count} = 0; + $signed{$count} = 0; + $count++; + } + + #menu loop + my $done = 0; + my $print_options = 0; + my $redraw = 1; + while (!$done) { + $count = 0; + if ($redraw) { + printf STDERR "\n%1s %2s %-65s", + "*", "#", "email/list and role:stats"; + if ($email_git || + ($email_git_fallback && !$maintained) || + $email_git_blame) { + print STDERR "auth sign"; + } + print STDERR "\n"; + foreach my $entry (@list) { + my $email = $entry->[0]; + my $role = $entry->[1]; + my $sel = ""; + $sel = "*" if ($selected{$count}); + my $commit_author = $commit_author_hash{$email}; + my $commit_signer = $commit_signer_hash{$email}; + my $authored = 0; + my $signed = 0; + $authored++ for (@{$commit_author}); + $signed++ for (@{$commit_signer}); + printf STDERR "%1s %2d %-65s", $sel, $count + 1, $email; + printf STDERR "%4d %4d", $authored, $signed + if ($authored > 0 || $signed > 0); + printf STDERR "\n %s\n", $role; + if ($authored{$count}) { + my $commit_author = $commit_author_hash{$email}; + foreach my $ref (@{$commit_author}) { + print STDERR " Author: @{$ref}[1]\n"; + } + } + if ($signed{$count}) { + my $commit_signer = $commit_signer_hash{$email}; + foreach my $ref (@{$commit_signer}) { + print STDERR " @{$ref}[2]: @{$ref}[1]\n"; + } + } + + $count++; + } + } + my $date_ref = \$email_git_since; + $date_ref = \$email_hg_since if (vcs_is_hg()); + if ($print_options) { + $print_options = 0; + if (vcs_exists()) { + print STDERR <<EOT + +Version Control options: +g use git history [$email_git] +gf use git-fallback [$email_git_fallback] +b use git blame [$email_git_blame] +bs use blame signatures [$email_git_blame_signatures] +c# minimum commits [$email_git_min_signatures] +%# min percent [$email_git_min_percent] +d# history to use [$$date_ref] +x# max maintainers [$email_git_max_maintainers] +t all signature types [$email_git_all_signature_types] +m use .mailmap [$email_use_mailmap] +EOT + } + print STDERR <<EOT + +Additional options: +0 toggle all +tm toggle maintainers +tg toggle git entries +tl toggle open list entries +ts toggle subscriber list entries +f emails in file [$email_file_emails] +k keywords in file [$keywords] +r remove duplicates [$email_remove_duplicates] +p# pattern match depth [$pattern_depth] +EOT + } + print STDERR +"\n#(toggle), A#(author), S#(signed) *(all), ^(none), O(options), Y(approve): "; + + my $input = <STDIN>; + chomp($input); + + $redraw = 1; + my $rerun = 0; + my @wish = split(/[, ]+/, $input); + foreach my $nr (@wish) { + $nr = lc($nr); + my $sel = substr($nr, 0, 1); + my $str = substr($nr, 1); + my $val = 0; + $val = $1 if $str =~ /^(\d+)$/; + + if ($sel eq "y") { + $interactive = 0; + $done = 1; + $output_rolestats = 0; + $output_roles = 0; + last; + } elsif ($nr =~ /^\d+$/ && $nr > 0 && $nr <= $count) { + $selected{$nr - 1} = !$selected{$nr - 1}; + } elsif ($sel eq "*" || $sel eq '^') { + my $toggle = 0; + $toggle = 1 if ($sel eq '*'); + for (my $i = 0; $i < $count; $i++) { + $selected{$i} = $toggle; + } + } elsif ($sel eq "0") { + for (my $i = 0; $i < $count; $i++) { + $selected{$i} = !$selected{$i}; + } + } elsif ($sel eq "t") { + if (lc($str) eq "m") { + for (my $i = 0; $i < $count; $i++) { + $selected{$i} = !$selected{$i} + if ($list[$i]->[1] =~ /^(maintainer|supporter)/i); + } + } elsif (lc($str) eq "g") { + for (my $i = 0; $i < $count; $i++) { + $selected{$i} = !$selected{$i} + if ($list[$i]->[1] =~ /^(author|commit|signer)/i); + } + } elsif (lc($str) eq "l") { + for (my $i = 0; $i < $count; $i++) { + $selected{$i} = !$selected{$i} + if ($list[$i]->[1] =~ /^(open list)/i); + } + } elsif (lc($str) eq "s") { + for (my $i = 0; $i < $count; $i++) { + $selected{$i} = !$selected{$i} + if ($list[$i]->[1] =~ /^(subscriber list)/i); + } + } + } elsif ($sel eq "a") { + if ($val > 0 && $val <= $count) { + $authored{$val - 1} = !$authored{$val - 1}; + } elsif ($str eq '*' || $str eq '^') { + my $toggle = 0; + $toggle = 1 if ($str eq '*'); + for (my $i = 0; $i < $count; $i++) { + $authored{$i} = $toggle; + } + } + } elsif ($sel eq "s") { + if ($val > 0 && $val <= $count) { + $signed{$val - 1} = !$signed{$val - 1}; + } elsif ($str eq '*' || $str eq '^') { + my $toggle = 0; + $toggle = 1 if ($str eq '*'); + for (my $i = 0; $i < $count; $i++) { + $signed{$i} = $toggle; + } + } + } elsif ($sel eq "o") { + $print_options = 1; + $redraw = 1; + } elsif ($sel eq "g") { + if ($str eq "f") { + bool_invert(\$email_git_fallback); + } else { + bool_invert(\$email_git); + } + $rerun = 1; + } elsif ($sel eq "b") { + if ($str eq "s") { + bool_invert(\$email_git_blame_signatures); + } else { + bool_invert(\$email_git_blame); + } + $rerun = 1; + } elsif ($sel eq "c") { + if ($val > 0) { + $email_git_min_signatures = $val; + $rerun = 1; + } + } elsif ($sel eq "x") { + if ($val > 0) { + $email_git_max_maintainers = $val; + $rerun = 1; + } + } elsif ($sel eq "%") { + if ($str ne "" && $val >= 0) { + $email_git_min_percent = $val; + $rerun = 1; + } + } elsif ($sel eq "d") { + if (vcs_is_git()) { + $email_git_since = $str; + } elsif (vcs_is_hg()) { + $email_hg_since = $str; + } + $rerun = 1; + } elsif ($sel eq "t") { + bool_invert(\$email_git_all_signature_types); + $rerun = 1; + } elsif ($sel eq "f") { + bool_invert(\$email_file_emails); + $rerun = 1; + } elsif ($sel eq "r") { + bool_invert(\$email_remove_duplicates); + $rerun = 1; + } elsif ($sel eq "m") { + bool_invert(\$email_use_mailmap); + read_mailmap(); + $rerun = 1; + } elsif ($sel eq "k") { + bool_invert(\$keywords); + $rerun = 1; + } elsif ($sel eq "p") { + if ($str ne "" && $val >= 0) { + $pattern_depth = $val; + $rerun = 1; + } + } elsif ($sel eq "h" || $sel eq "?") { + print STDERR <<EOT + +Interactive mode allows you to select the various maintainers, submitters, +commit signers and mailing lists that could be CC'd on a patch. + +Any *'d entry is selected. + +If you have git or hg installed, you can choose to summarize the commit +history of files in the patch. Also, each line of the current file can +be matched to its commit author and that commits signers with blame. + +Various knobs exist to control the length of time for active commit +tracking, the maximum number of commit authors and signers to add, +and such. + +Enter selections at the prompt until you are satisfied that the selected +maintainers are appropriate. You may enter multiple selections separated +by either commas or spaces. + +EOT + } else { + print STDERR "invalid option: '$nr'\n"; + $redraw = 0; + } + } + if ($rerun) { + print STDERR "git-blame can be very slow, please have patience..." + if ($email_git_blame); + goto &get_maintainers; + } + } + + #drop not selected entries + $count = 0; + my @new_emailto = (); + foreach my $entry (@list) { + if ($selected{$count}) { + push(@new_emailto, $list[$count]); + } + $count++; + } + return @new_emailto; +} + +sub bool_invert { + my ($bool_ref) = @_; + + if ($$bool_ref) { + $$bool_ref = 0; + } else { + $$bool_ref = 1; + } +} + +sub deduplicate_email { + my ($email) = @_; + + my $matched = 0; + my ($name, $address) = parse_email($email); + $email = format_email($name, $address, 1); + $email = mailmap_email($email); + + return $email if (!$email_remove_duplicates); + + ($name, $address) = parse_email($email); + + if ($name ne "" && $deduplicate_name_hash{lc($name)}) { + $name = $deduplicate_name_hash{lc($name)}->[0]; + $address = $deduplicate_name_hash{lc($name)}->[1]; + $matched = 1; + } elsif ($deduplicate_address_hash{lc($address)}) { + $name = $deduplicate_address_hash{lc($address)}->[0]; + $address = $deduplicate_address_hash{lc($address)}->[1]; + $matched = 1; + } + if (!$matched) { + $deduplicate_name_hash{lc($name)} = [ $name, $address ]; + $deduplicate_address_hash{lc($address)} = [ $name, $address ]; + } + $email = format_email($name, $address, 1); + $email = mailmap_email($email); + return $email; +} + +sub save_commits_by_author { + my (@lines) = @_; + + my @authors = (); + my @commits = (); + my @subjects = (); + + foreach my $line (@lines) { + if ($line =~ m/$VCS_cmds{"author_pattern"}/) { + my $author = $1; + $author = deduplicate_email($author); + push(@authors, $author); + } + push(@commits, $1) if ($line =~ m/$VCS_cmds{"commit_pattern"}/); + push(@subjects, $1) if ($line =~ m/$VCS_cmds{"subject_pattern"}/); + } + + for (my $i = 0; $i < @authors; $i++) { + my $exists = 0; + foreach my $ref(@{$commit_author_hash{$authors[$i]}}) { + if (@{$ref}[0] eq $commits[$i] && + @{$ref}[1] eq $subjects[$i]) { + $exists = 1; + last; + } + } + if (!$exists) { + push(@{$commit_author_hash{$authors[$i]}}, + [ ($commits[$i], $subjects[$i]) ]); + } + } +} + +sub save_commits_by_signer { + my (@lines) = @_; + + my $commit = ""; + my $subject = ""; + + foreach my $line (@lines) { + $commit = $1 if ($line =~ m/$VCS_cmds{"commit_pattern"}/); + $subject = $1 if ($line =~ m/$VCS_cmds{"subject_pattern"}/); + if ($line =~ /^[ \t]*${signature_pattern}.*\@.*$/) { + my @signatures = ($line); + my ($types_ref, $signers_ref) = extract_formatted_signatures(@signatures); + my @types = @$types_ref; + my @signers = @$signers_ref; + + my $type = $types[0]; + my $signer = $signers[0]; + + $signer = deduplicate_email($signer); + + my $exists = 0; + foreach my $ref(@{$commit_signer_hash{$signer}}) { + if (@{$ref}[0] eq $commit && + @{$ref}[1] eq $subject && + @{$ref}[2] eq $type) { + $exists = 1; + last; + } + } + if (!$exists) { + push(@{$commit_signer_hash{$signer}}, + [ ($commit, $subject, $type) ]); + } + } + } +} + +sub vcs_assign { + my ($role, $divisor, @lines) = @_; + + my %hash; + my $count = 0; + + return if (@lines <= 0); + + if ($divisor <= 0) { + warn("Bad divisor in " . (caller(0))[3] . ": $divisor\n"); + $divisor = 1; + } + + @lines = mailmap(@lines); + + return if (@lines <= 0); + + @lines = sort(@lines); + + # uniq -c + $hash{$_}++ for @lines; + + # sort -rn + foreach my $line (sort {$hash{$b} <=> $hash{$a}} keys %hash) { + my $sign_offs = $hash{$line}; + my $percent = $sign_offs * 100 / $divisor; + + $percent = 100 if ($percent > 100); + next if (ignore_email_address($line)); + $count++; + last if ($sign_offs < $email_git_min_signatures || + $count > $email_git_max_maintainers || + $percent < $email_git_min_percent); + push_email_address($line, ''); + if ($output_rolestats) { + my $fmt_percent = sprintf("%.0f", $percent); + add_role($line, "$role:$sign_offs/$divisor=$fmt_percent%"); + } else { + add_role($line, $role); + } + } +} + +sub vcs_file_signoffs { + my ($file) = @_; + + my $authors_ref; + my $signers_ref; + my $stats_ref; + my @authors = (); + my @signers = (); + my @stats = (); + my $commits; + + $vcs_used = vcs_exists(); + return if (!$vcs_used); + + my $cmd = $VCS_cmds{"find_signers_cmd"}; + $cmd =~ s/(\$\w+)/$1/eeg; # interpolate $cmd + + ($commits, $signers_ref, $authors_ref, $stats_ref) = vcs_find_signers($cmd, $file); + + @signers = @{$signers_ref} if defined $signers_ref; + @authors = @{$authors_ref} if defined $authors_ref; + @stats = @{$stats_ref} if defined $stats_ref; + +# print("commits: <$commits>\nsigners:<@signers>\nauthors: <@authors>\nstats: <@stats>\n"); + + foreach my $signer (@signers) { + $signer = deduplicate_email($signer); + } + + vcs_assign("commit_signer", $commits, @signers); + vcs_assign("authored", $commits, @authors); + if ($#authors == $#stats) { + my $stat_pattern = $VCS_cmds{"stat_pattern"}; + $stat_pattern =~ s/(\$\w+)/$1/eeg; #interpolate $stat_pattern + + my $added = 0; + my $deleted = 0; + for (my $i = 0; $i <= $#stats; $i++) { + if ($stats[$i] =~ /$stat_pattern/) { + $added += $1; + $deleted += $2; + } + } + my @tmp_authors = uniq(@authors); + foreach my $author (@tmp_authors) { + $author = deduplicate_email($author); + } + @tmp_authors = uniq(@tmp_authors); + my @list_added = (); + my @list_deleted = (); + foreach my $author (@tmp_authors) { + my $auth_added = 0; + my $auth_deleted = 0; + for (my $i = 0; $i <= $#stats; $i++) { + if ($author eq deduplicate_email($authors[$i]) && + $stats[$i] =~ /$stat_pattern/) { + $auth_added += $1; + $auth_deleted += $2; + } + } + for (my $i = 0; $i < $auth_added; $i++) { + push(@list_added, $author); + } + for (my $i = 0; $i < $auth_deleted; $i++) { + push(@list_deleted, $author); + } + } + vcs_assign("added_lines", $added, @list_added); + vcs_assign("removed_lines", $deleted, @list_deleted); + } +} + +sub vcs_file_blame { + my ($file) = @_; + + my @signers = (); + my @all_commits = (); + my @commits = (); + my $total_commits; + my $total_lines; + + $vcs_used = vcs_exists(); + return if (!$vcs_used); + + @all_commits = vcs_blame($file); + @commits = uniq(@all_commits); + $total_commits = @commits; + $total_lines = @all_commits; + + if ($email_git_blame_signatures) { + if (vcs_is_hg()) { + my $commit_count; + my $commit_authors_ref; + my $commit_signers_ref; + my $stats_ref; + my @commit_authors = (); + my @commit_signers = (); + my $commit = join(" -r ", @commits); + my $cmd; + + $cmd = $VCS_cmds{"find_commit_signers_cmd"}; + $cmd =~ s/(\$\w+)/$1/eeg; #substitute variables in $cmd + + ($commit_count, $commit_signers_ref, $commit_authors_ref, $stats_ref) = vcs_find_signers($cmd, $file); + @commit_authors = @{$commit_authors_ref} if defined $commit_authors_ref; + @commit_signers = @{$commit_signers_ref} if defined $commit_signers_ref; + + push(@signers, @commit_signers); + } else { + foreach my $commit (@commits) { + my $commit_count; + my $commit_authors_ref; + my $commit_signers_ref; + my $stats_ref; + my @commit_authors = (); + my @commit_signers = (); + my $cmd; + + $cmd = $VCS_cmds{"find_commit_signers_cmd"}; + $cmd =~ s/(\$\w+)/$1/eeg; #substitute variables in $cmd + + ($commit_count, $commit_signers_ref, $commit_authors_ref, $stats_ref) = vcs_find_signers($cmd, $file); + @commit_authors = @{$commit_authors_ref} if defined $commit_authors_ref; + @commit_signers = @{$commit_signers_ref} if defined $commit_signers_ref; + + push(@signers, @commit_signers); + } + } + } + + if ($from_filename) { + if ($output_rolestats) { + my @blame_signers; + if (vcs_is_hg()) {{ # Double brace for last exit + my $commit_count; + my @commit_signers = (); + @commits = uniq(@commits); + @commits = sort(@commits); + my $commit = join(" -r ", @commits); + my $cmd; + + $cmd = $VCS_cmds{"find_commit_author_cmd"}; + $cmd =~ s/(\$\w+)/$1/eeg; #substitute variables in $cmd + + my @lines = (); + + @lines = &{$VCS_cmds{"execute_cmd"}}($cmd); + + if (!$email_git_penguin_chiefs) { + @lines = grep(!/${penguin_chiefs}/i, @lines); + } + + last if !@lines; + + my @authors = (); + foreach my $line (@lines) { + if ($line =~ m/$VCS_cmds{"author_pattern"}/) { + my $author = $1; + $author = deduplicate_email($author); + push(@authors, $author); + } + } + + save_commits_by_author(@lines) if ($interactive); + save_commits_by_signer(@lines) if ($interactive); + + push(@signers, @authors); + }} + else { + foreach my $commit (@commits) { + my $i; + my $cmd = $VCS_cmds{"find_commit_author_cmd"}; + $cmd =~ s/(\$\w+)/$1/eeg; #interpolate $cmd + my @author = vcs_find_author($cmd); + next if !@author; + + my $formatted_author = deduplicate_email($author[0]); + + my $count = grep(/$commit/, @all_commits); + for ($i = 0; $i < $count ; $i++) { + push(@blame_signers, $formatted_author); + } + } + } + if (@blame_signers) { + vcs_assign("authored lines", $total_lines, @blame_signers); + } + } + foreach my $signer (@signers) { + $signer = deduplicate_email($signer); + } + vcs_assign("commits", $total_commits, @signers); + } else { + foreach my $signer (@signers) { + $signer = deduplicate_email($signer); + } + vcs_assign("modified commits", $total_commits, @signers); + } +} + +sub vcs_file_exists { + my ($file) = @_; + + my $exists; + + my $vcs_used = vcs_exists(); + return 0 if (!$vcs_used); + + my $cmd = $VCS_cmds{"file_exists_cmd"}; + $cmd =~ s/(\$\w+)/$1/eeg; # interpolate $cmd + $cmd .= " 2>&1"; + $exists = &{$VCS_cmds{"execute_cmd"}}($cmd); + + return 0 if ($? != 0); + + return $exists; +} + +sub vcs_list_files { + my ($file) = @_; + + my @lsfiles = (); + + my $vcs_used = vcs_exists(); + return 0 if (!$vcs_used); + + my $cmd = $VCS_cmds{"list_files_cmd"}; + $cmd =~ s/(\$\w+)/$1/eeg; # interpolate $cmd + @lsfiles = &{$VCS_cmds{"execute_cmd"}}($cmd); + + return () if ($? != 0); + + return @lsfiles; +} + +sub uniq { + my (@parms) = @_; + + my %saw; + @parms = grep(!$saw{$_}++, @parms); + return @parms; +} + +sub sort_and_uniq { + my (@parms) = @_; + + my %saw; + @parms = sort @parms; + @parms = grep(!$saw{$_}++, @parms); + return @parms; +} + +sub clean_file_emails { + my (@file_emails) = @_; + my @fmt_emails = (); + + foreach my $email (@file_emails) { + $email =~ s/[\(\<\{]{0,1}([A-Za-z0-9_\.\+-]+\@[A-Za-z0-9\.-]+)[\)\>\}]{0,1}/\<$1\>/g; + my ($name, $address) = parse_email($email); + if ($name eq '"[,\.]"') { + $name = ""; + } + + my @nw = split(/[^A-Za-zÀ-ÿ\'\,\.\+-]/, $name); + if (@nw > 2) { + my $first = $nw[@nw - 3]; + my $middle = $nw[@nw - 2]; + my $last = $nw[@nw - 1]; + + if (((length($first) == 1 && $first =~ m/[A-Za-z]/) || + (length($first) == 2 && substr($first, -1) eq ".")) || + (length($middle) == 1 || + (length($middle) == 2 && substr($middle, -1) eq "."))) { + $name = "$first $middle $last"; + } else { + $name = "$middle $last"; + } + } + + if (substr($name, -1) =~ /[,\.]/) { + $name = substr($name, 0, length($name) - 1); + } elsif (substr($name, -2) =~ /[,\.]"/) { + $name = substr($name, 0, length($name) - 2) . '"'; + } + + if (substr($name, 0, 1) =~ /[,\.]/) { + $name = substr($name, 1, length($name) - 1); + } elsif (substr($name, 0, 2) =~ /"[,\.]/) { + $name = '"' . substr($name, 2, length($name) - 2); + } + + my $fmt_email = format_email($name, $address, $email_usename); + push(@fmt_emails, $fmt_email); + } + return @fmt_emails; +} + +sub merge_email { + my @lines; + my %saw; + + for (@_) { + my ($address, $role) = @$_; + if (!$saw{$address}) { + if ($output_roles) { + push(@lines, "$address ($role)"); + } else { + push(@lines, $address); + } + $saw{$address} = 1; + } + } + + return @lines; +} + +sub output { + my (@parms) = @_; + + if ($output_multiline) { + foreach my $line (@parms) { + print("${line}\n"); + } + } else { + print(join($output_separator, @parms)); + print("\n"); + } +} + +my $rfc822re; + +sub make_rfc822re { +# Basic lexical tokens are specials, domain_literal, quoted_string, atom, and +# comment. We must allow for rfc822_lwsp (or comments) after each of these. +# This regexp will only work on addresses which have had comments stripped +# and replaced with rfc822_lwsp. + + my $specials = '()<>@,;:\\\\".\\[\\]'; + my $controls = '\\000-\\037\\177'; + + my $dtext = "[^\\[\\]\\r\\\\]"; + my $domain_literal = "\\[(?:$dtext|\\\\.)*\\]$rfc822_lwsp*"; + + my $quoted_string = "\"(?:[^\\\"\\r\\\\]|\\\\.|$rfc822_lwsp)*\"$rfc822_lwsp*"; + +# Use zero-width assertion to spot the limit of an atom. A simple +# $rfc822_lwsp* causes the regexp engine to hang occasionally. + my $atom = "[^$specials $controls]+(?:$rfc822_lwsp+|\\Z|(?=[\\[\"$specials]))"; + my $word = "(?:$atom|$quoted_string)"; + my $localpart = "$word(?:\\.$rfc822_lwsp*$word)*"; + + my $sub_domain = "(?:$atom|$domain_literal)"; + my $domain = "$sub_domain(?:\\.$rfc822_lwsp*$sub_domain)*"; + + my $addr_spec = "$localpart\@$rfc822_lwsp*$domain"; + + my $phrase = "$word*"; + my $route = "(?:\@$domain(?:,\@$rfc822_lwsp*$domain)*:$rfc822_lwsp*)"; + my $route_addr = "\\<$rfc822_lwsp*$route?$addr_spec\\>$rfc822_lwsp*"; + my $mailbox = "(?:$addr_spec|$phrase$route_addr)"; + + my $group = "$phrase:$rfc822_lwsp*(?:$mailbox(?:,\\s*$mailbox)*)?;\\s*"; + my $address = "(?:$mailbox|$group)"; + + return "$rfc822_lwsp*$address"; +} + +sub rfc822_strip_comments { + my $s = shift; +# Recursively remove comments, and replace with a single space. The simpler +# regexps in the Email Addressing FAQ are imperfect - they will miss escaped +# chars in atoms, for example. + + while ($s =~ s/^((?:[^"\\]|\\.)* + (?:"(?:[^"\\]|\\.)*"(?:[^"\\]|\\.)*)*) + \((?:[^()\\]|\\.)*\)/$1 /osx) {} + return $s; +} + +# valid: returns true if the parameter is an RFC822 valid address +# +sub rfc822_valid { + my $s = rfc822_strip_comments(shift); + + if (!$rfc822re) { + $rfc822re = make_rfc822re(); + } + + return $s =~ m/^$rfc822re$/so && $s =~ m/^$rfc822_char*$/; +} + +# validlist: In scalar context, returns true if the parameter is an RFC822 +# valid list of addresses. +# +# In list context, returns an empty list on failure (an invalid +# address was found); otherwise a list whose first element is the +# number of addresses found and whose remaining elements are the +# addresses. This is needed to disambiguate failure (invalid) +# from success with no addresses found, because an empty string is +# a valid list. + +sub rfc822_validlist { + my $s = rfc822_strip_comments(shift); + + if (!$rfc822re) { + $rfc822re = make_rfc822re(); + } + # * null list items are valid according to the RFC + # * the '1' business is to aid in distinguishing failure from no results + + my @r; + if ($s =~ m/^(?:$rfc822re)?(?:,(?:$rfc822re)?)*$/so && + $s =~ m/^$rfc822_char*$/) { + while ($s =~ m/(?:^|,$rfc822_lwsp*)($rfc822re)/gos) { + push(@r, $1); + } + return wantarray ? (scalar(@r), @r) : 1; + } + return wantarray ? () : 0; +} diff --git a/src/net/scripts/gfp-translate b/src/net/scripts/gfp-translate new file mode 100755 index 0000000..b2ce416 --- /dev/null +++ b/src/net/scripts/gfp-translate @@ -0,0 +1,86 @@ +#!/bin/bash +# SPDX-License-Identifier: GPL-2.0-only +# Translate the bits making up a GFP mask +# (c) 2009, Mel Gorman <mel@csn.ul.ie> +SOURCE= +GFPMASK=none + +# Helper function to report failures and exit +die() { + echo ERROR: $@ + if [ "$TMPFILE" != "" ]; then + rm -f $TMPFILE + fi + exit -1 +} + +usage() { + echo "usage: gfp-translate [-h] [ --source DIRECTORY ] gfpmask" + exit 0 +} + +# Parse command-line arguments +while [ $# -gt 0 ]; do + case $1 in + --source) + SOURCE=$2 + shift 2 + ;; + -h) + usage + ;; + --help) + usage + ;; + *) + GFPMASK=$1 + shift + ;; + esac +done + +# Guess the kernel source directory if it's not set. Preference is in order of +# o current directory +# o /usr/src/linux +if [ "$SOURCE" = "" ]; then + if [ -r "/usr/src/linux/Makefile" ]; then + SOURCE=/usr/src/linux + fi + if [ -r "`pwd`/Makefile" ]; then + SOURCE=`pwd` + fi +fi + +# Confirm that a source directory exists +if [ ! -r "$SOURCE/Makefile" ]; then + die "Could not locate kernel source directory or it is invalid" +fi + +# Confirm that a GFP mask has been specified +if [ "$GFPMASK" = "none" ]; then + usage +fi + +# Extract GFP flags from the kernel source +TMPFILE=`mktemp -t gfptranslate-XXXXXX` || exit 1 +grep -q ___GFP $SOURCE/include/linux/gfp.h +if [ $? -eq 0 ]; then + grep "^#define ___GFP" $SOURCE/include/linux/gfp.h | sed -e 's/u$//' | grep -v GFP_BITS > $TMPFILE +else + grep "^#define __GFP" $SOURCE/include/linux/gfp.h | sed -e 's/(__force gfp_t)//' | sed -e 's/u)/)/' | grep -v GFP_BITS | sed -e 's/)\//) \//' > $TMPFILE +fi + +# Parse the flags +IFS=" +" +echo Source: $SOURCE +echo Parsing: $GFPMASK +for LINE in `cat $TMPFILE`; do + MASK=`echo $LINE | awk '{print $3}'` + if [ $(($GFPMASK&$MASK)) -ne 0 ]; then + echo $LINE + fi +done + +rm -f $TMPFILE +exit 0 diff --git a/src/net/scripts/headerdep.pl b/src/net/scripts/headerdep.pl new file mode 100755 index 0000000..ebfcbef --- /dev/null +++ b/src/net/scripts/headerdep.pl @@ -0,0 +1,193 @@ +#! /usr/bin/env perl +# SPDX-License-Identifier: GPL-2.0 +# +# Detect cycles in the header file dependency graph +# Vegard Nossum <vegardno@ifi.uio.no> +# + +use strict; +use warnings; + +use Getopt::Long; + +my $opt_all; +my @opt_include; +my $opt_graph; + +&Getopt::Long::Configure(qw(bundling pass_through)); +&GetOptions( + help => \&help, + version => \&version, + + all => \$opt_all, + "I=s" => \@opt_include, + graph => \$opt_graph, +); + +push @opt_include, 'include'; +my %deps = (); +my %linenos = (); + +my @headers = grep { strip($_) } @ARGV; + +parse_all(@headers); + +if($opt_graph) { + graph(); +} else { + detect_cycles(@headers); +} + + +sub help { + print "Usage: $0 [options] file...\n"; + print "\n"; + print "Options:\n"; + print " --all\n"; + print " --graph\n"; + print "\n"; + print " -I includedir\n"; + print "\n"; + print "To make nice graphs, try:\n"; + print " $0 --graph include/linux/kernel.h | dot -Tpng -o graph.png\n"; + exit; +} + +sub version { + print "headerdep version 2\n"; + exit; +} + +# Get a file name that is relative to our include paths +sub strip { + my $filename = shift; + + for my $i (@opt_include) { + my $stripped = $filename; + $stripped =~ s/^$i\///; + + return $stripped if $stripped ne $filename; + } + + return $filename; +} + +# Search for the file name in the list of include paths +sub search { + my $filename = shift; + return $filename if -f $filename; + + for my $i (@opt_include) { + my $path = "$i/$filename"; + return $path if -f $path; + } + return; +} + +sub parse_all { + # Parse all the headers. + my @queue = @_; + while(@queue) { + my $header = pop @queue; + next if exists $deps{$header}; + + $deps{$header} = [] unless exists $deps{$header}; + + my $path = search($header); + next unless $path; + + open(my $file, '<', $path) or die($!); + chomp(my @lines = <$file>); + close($file); + + for my $i (0 .. $#lines) { + my $line = $lines[$i]; + if(my($dep) = ($line =~ m/^#\s*include\s*<(.*?)>/)) { + push @queue, $dep; + push @{$deps{$header}}, [$i + 1, $dep]; + } + } + } +} + +sub print_cycle { + # $cycle[n] includes $cycle[n + 1]; + # $cycle[-1] will be the culprit + my $cycle = shift; + + # Adjust the line numbers + for my $i (0 .. $#$cycle - 1) { + $cycle->[$i]->[0] = $cycle->[$i + 1]->[0]; + } + $cycle->[-1]->[0] = 0; + + my $first = shift @$cycle; + my $last = pop @$cycle; + + my $msg = "In file included"; + printf "%s from %s,\n", $msg, $last->[1] if defined $last; + + for my $header (reverse @$cycle) { + printf "%s from %s:%d%s\n", + " " x length $msg, + $header->[1], $header->[0], + $header->[1] eq $last->[1] ? ' <-- here' : ''; + } + + printf "%s:%d: warning: recursive header inclusion\n", + $first->[1], $first->[0]; +} + +# Find and print the smallest cycle starting in the specified node. +sub detect_cycles { + my @queue = map { [[0, $_]] } @_; + while(@queue) { + my $top = pop @queue; + my $name = $top->[-1]->[1]; + + for my $dep (@{$deps{$name}}) { + my $chain = [@$top, [$dep->[0], $dep->[1]]]; + + # If the dep already exists in the chain, we have a + # cycle... + if(grep { $_->[1] eq $dep->[1] } @$top) { + print_cycle($chain); + next if $opt_all; + return; + } + + push @queue, $chain; + } + } +} + +sub mangle { + $_ = shift; + s/\//__/g; + s/\./_/g; + s/-/_/g; + $_; +} + +# Output dependency graph in GraphViz language. +sub graph { + print "digraph {\n"; + + print "\t/* vertices */\n"; + for my $header (keys %deps) { + printf "\t%s [label=\"%s\"];\n", + mangle($header), $header; + } + + print "\n"; + + print "\t/* edges */\n"; + for my $header (keys %deps) { + for my $dep (@{$deps{$header}}) { + printf "\t%s -> %s;\n", + mangle($header), mangle($dep->[1]); + } + } + + print "}\n"; +} diff --git a/src/net/scripts/headers_check.pl b/src/net/scripts/headers_check.pl new file mode 100755 index 0000000..b6aec5e --- /dev/null +++ b/src/net/scripts/headers_check.pl @@ -0,0 +1,171 @@ +#!/usr/bin/env perl +# SPDX-License-Identifier: GPL-2.0 +# +# headers_check.pl execute a number of trivial consistency checks +# +# Usage: headers_check.pl dir arch [files...] +# dir: dir to look for included files +# arch: architecture +# files: list of files to check +# +# The script reads the supplied files line by line and: +# +# 1) for each include statement it checks if the +# included file actually exists. +# Only include files located in asm* and linux* are checked. +# The rest are assumed to be system include files. +# +# 2) It is checked that prototypes does not use "extern" +# +# 3) Check for leaked CONFIG_ symbols + +use warnings; +use strict; +use File::Basename; + +my ($dir, $arch, @files) = @ARGV; + +my $ret = 0; +my $line; +my $lineno = 0; +my $filename; + +foreach my $file (@files) { + $filename = $file; + + open(my $fh, '<', $filename) + or die "$filename: $!\n"; + $lineno = 0; + while ($line = <$fh>) { + $lineno++; + &check_include(); + &check_asm_types(); + &check_sizetypes(); + &check_declarations(); + # Dropped for now. Too much noise &check_config(); + } + close $fh; +} +exit $ret; + +sub check_include +{ + if ($line =~ m/^\s*#\s*include\s+<((asm|linux).*)>/) { + my $inc = $1; + my $found; + $found = stat($dir . "/" . $inc); + if (!$found) { + $inc =~ s#asm/#asm-$arch/#; + $found = stat($dir . "/" . $inc); + } + if (!$found) { + printf STDERR "$filename:$lineno: included file '$inc' is not exported\n"; + $ret = 1; + } + } +} + +sub check_declarations +{ + # soundcard.h is what it is + if ($line =~ m/^void seqbuf_dump\(void\);/) { + return; + } + # drm headers are being C++ friendly + if ($line =~ m/^extern "C"/) { + return; + } + if ($line =~ m/^(\s*extern|unsigned|char|short|int|long|void)\b/) { + printf STDERR "$filename:$lineno: " . + "userspace cannot reference function or " . + "variable defined in the kernel\n"; + } +} + +sub check_config +{ + if ($line =~ m/[^a-zA-Z0-9_]+CONFIG_([a-zA-Z0-9_]+)[^a-zA-Z0-9_]/) { + printf STDERR "$filename:$lineno: leaks CONFIG_$1 to userspace where it is not valid\n"; + } +} + +my $linux_asm_types; +sub check_asm_types +{ + if ($filename =~ /types.h|int-l64.h|int-ll64.h/o) { + return; + } + if ($lineno == 1) { + $linux_asm_types = 0; + } elsif ($linux_asm_types >= 1) { + return; + } + if ($line =~ m/^\s*#\s*include\s+<asm\/types.h>/) { + $linux_asm_types = 1; + printf STDERR "$filename:$lineno: " . + "include of <linux/types.h> is preferred over <asm/types.h>\n" + # Warn until headers are all fixed + #$ret = 1; + } +} + +my $linux_types; +my %import_stack = (); +sub check_include_typesh +{ + my $path = $_[0]; + my $import_path; + + my $fh; + my @file_paths = ($path, $dir . "/" . $path, dirname($filename) . "/" . $path); + for my $possible ( @file_paths ) { + if (not $import_stack{$possible} and open($fh, '<', $possible)) { + $import_path = $possible; + $import_stack{$import_path} = 1; + last; + } + } + if (eof $fh) { + return; + } + + my $line; + while ($line = <$fh>) { + if ($line =~ m/^\s*#\s*include\s+<linux\/types.h>/) { + $linux_types = 1; + last; + } + if (my $included = ($line =~ /^\s*#\s*include\s+[<"](\S+)[>"]/)[0]) { + check_include_typesh($included); + } + } + close $fh; + delete $import_stack{$import_path}; +} + +sub check_sizetypes +{ + if ($filename =~ /types.h|int-l64.h|int-ll64.h/o) { + return; + } + if ($lineno == 1) { + $linux_types = 0; + } elsif ($linux_types >= 1) { + return; + } + if ($line =~ m/^\s*#\s*include\s+<linux\/types.h>/) { + $linux_types = 1; + return; + } + if (my $included = ($line =~ /^\s*#\s*include\s+[<"](\S+)[>"]/)[0]) { + check_include_typesh($included); + } + if ($line =~ m/__[us](8|16|32|64)\b/) { + printf STDERR "$filename:$lineno: " . + "found __[us]{8,16,32,64} type " . + "without #include <linux/types.h>\n"; + $linux_types = 2; + # Warn until headers are all fixed + #$ret = 1; + } +} diff --git a/src/net/scripts/headers_install.sh b/src/net/scripts/headers_install.sh new file mode 100755 index 0000000..dd554bd --- /dev/null +++ b/src/net/scripts/headers_install.sh @@ -0,0 +1,113 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0 + +if [ $# -ne 2 ] +then + echo "Usage: headers_install.sh INFILE OUTFILE" + echo + echo "Prepares kernel header files for use by user space, by removing" + echo "all compiler.h definitions and #includes, removing any" + echo "#ifdef __KERNEL__ sections, and putting __underscores__ around" + echo "asm/inline/volatile keywords." + echo + echo "INFILE: header file to operate on" + echo "OUTFILE: output file which the processed header is written to" + + exit 1 +fi + +# Grab arguments +INFILE=$1 +OUTFILE=$2 +TMPFILE=$OUTFILE.tmp + +trap 'rm -f $OUTFILE $TMPFILE' EXIT + +# SPDX-License-Identifier with GPL variants must have "WITH Linux-syscall-note" +if [ -n "$(sed -n -e "/SPDX-License-Identifier:.*GPL-/{/WITH Linux-syscall-note/!p}" $INFILE)" ]; then + echo "error: $INFILE: missing \"WITH Linux-syscall-note\" for SPDX-License-Identifier" >&2 + exit 1 +fi + +sed -E -e ' + s/([[:space:](])(__user|__force|__iomem)[[:space:]]/\1/g + s/__attribute_const__([[:space:]]|$)/\1/g + s@^#include <linux/compiler(|_types).h>@@ + s/(^|[^a-zA-Z0-9])__packed([^a-zA-Z0-9_]|$)/\1__attribute__((packed))\2/g + s/(^|[[:space:](])(inline|asm|volatile)([[:space:](]|$)/\1__\2__\3/g + s@#(ifndef|define|endif[[:space:]]*/[*])[[:space:]]*_UAPI@#\1 @ +' $INFILE > $TMPFILE || exit 1 + +scripts/unifdef -U__KERNEL__ -D__EXPORTED_HEADERS__ $TMPFILE > $OUTFILE +[ $? -gt 1 ] && exit 1 + +# Remove /* ... */ style comments, and find CONFIG_ references in code +configs=$(sed -e ' +:comment + s:/\*[^*][^*]*:/*: + s:/\*\*\**\([^/]\):/*\1: + t comment + s:/\*\*/: : + t comment + /\/\*/! b check + N + b comment +:print + P + D +:check + s:^\(CONFIG_[[:alnum:]_]*\):\1\n: + t print + s:^[[:alnum:]_][[:alnum:]_]*:: + s:^[^[:alnum:]_][^[:alnum:]_]*:: + t check + d +' $OUTFILE) + +# The entries in the following list do not result in an error. +# Please do not add a new entry. This list is only for existing ones. +# The list will be reduced gradually, and deleted eventually. (hopefully) +# +# The format is <file-name>:<CONFIG-option> in each line. +config_leak_ignores=" +arch/alpha/include/uapi/asm/setup.h:CONFIG_ALPHA_LEGACY_START_ADDRESS +arch/arc/include/uapi/asm/page.h:CONFIG_ARC_PAGE_SIZE_16K +arch/arc/include/uapi/asm/page.h:CONFIG_ARC_PAGE_SIZE_4K +arch/arc/include/uapi/asm/swab.h:CONFIG_ARC_HAS_SWAPE +arch/arm/include/uapi/asm/ptrace.h:CONFIG_CPU_ENDIAN_BE8 +arch/hexagon/include/uapi/asm/ptrace.h:CONFIG_HEXAGON_ARCH_VERSION +arch/hexagon/include/uapi/asm/user.h:CONFIG_HEXAGON_ARCH_VERSION +arch/ia64/include/uapi/asm/cmpxchg.h:CONFIG_IA64_DEBUG_CMPXCHG +arch/m68k/include/uapi/asm/ptrace.h:CONFIG_COLDFIRE +arch/nios2/include/uapi/asm/swab.h:CONFIG_NIOS2_CI_SWAB_NO +arch/nios2/include/uapi/asm/swab.h:CONFIG_NIOS2_CI_SWAB_SUPPORT +arch/x86/include/uapi/asm/auxvec.h:CONFIG_IA32_EMULATION +arch/x86/include/uapi/asm/auxvec.h:CONFIG_X86_64 +arch/x86/include/uapi/asm/mman.h:CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS +include/uapi/asm-generic/fcntl.h:CONFIG_64BIT +include/uapi/linux/atmdev.h:CONFIG_COMPAT +include/uapi/linux/eventpoll.h:CONFIG_PM_SLEEP +include/uapi/linux/hw_breakpoint.h:CONFIG_HAVE_MIXED_BREAKPOINTS_REGS +include/uapi/linux/pktcdvd.h:CONFIG_CDROM_PKTCDVD_WCACHE +" + +for c in $configs +do + leak_error=1 + + for ignore in $config_leak_ignores + do + if echo "$INFILE:$c" | grep -q "$ignore$"; then + leak_error= + break + fi + done + + if [ "$leak_error" = 1 ]; then + echo "error: $INFILE: leak $c to user-space" >&2 + exit 1 + fi +done + +rm -f $TMPFILE +trap - EXIT diff --git a/src/net/scripts/insert-sys-cert.c b/src/net/scripts/insert-sys-cert.c new file mode 100644 index 0000000..8902836 --- /dev/null +++ b/src/net/scripts/insert-sys-cert.c @@ -0,0 +1,410 @@ +/* Write the contents of the <certfile> into kernel symbol system_extra_cert + * + * Copyright (C) IBM Corporation, 2015 + * + * Author: Mehmet Kayaalp <mkayaalp@linux.vnet.ibm.com> + * + * This software may be used and distributed according to the terms + * of the GNU General Public License, incorporated herein by reference. + * + * Usage: insert-sys-cert [-s <System.map> -b <vmlinux> -c <certfile> + */ + +#define _GNU_SOURCE +#include <stdio.h> +#include <ctype.h> +#include <string.h> +#include <limits.h> +#include <stdbool.h> +#include <errno.h> +#include <stdlib.h> +#include <stdarg.h> +#include <sys/types.h> +#include <sys/stat.h> +#include <sys/mman.h> +#include <fcntl.h> +#include <unistd.h> +#include <elf.h> + +#define CERT_SYM "system_extra_cert" +#define USED_SYM "system_extra_cert_used" +#define LSIZE_SYM "system_certificate_list_size" + +#define info(format, args...) fprintf(stderr, "INFO: " format, ## args) +#define warn(format, args...) fprintf(stdout, "WARNING: " format, ## args) +#define err(format, args...) fprintf(stderr, "ERROR: " format, ## args) + +#if UINTPTR_MAX == 0xffffffff +#define CURRENT_ELFCLASS ELFCLASS32 +#define Elf_Ehdr Elf32_Ehdr +#define Elf_Shdr Elf32_Shdr +#define Elf_Sym Elf32_Sym +#else +#define CURRENT_ELFCLASS ELFCLASS64 +#define Elf_Ehdr Elf64_Ehdr +#define Elf_Shdr Elf64_Shdr +#define Elf_Sym Elf64_Sym +#endif + +static unsigned char endianness(void) +{ + uint16_t two_byte = 0x00FF; + uint8_t low_address = *((uint8_t *)&two_byte); + + if (low_address == 0) + return ELFDATA2MSB; + else + return ELFDATA2LSB; +} + +struct sym { + char *name; + unsigned long address; + unsigned long offset; + void *content; + int size; +}; + +static unsigned long get_offset_from_address(Elf_Ehdr *hdr, unsigned long addr) +{ + Elf_Shdr *x; + unsigned int i, num_sections; + + x = (void *)hdr + hdr->e_shoff; + if (hdr->e_shnum == SHN_UNDEF) + num_sections = x[0].sh_size; + else + num_sections = hdr->e_shnum; + + for (i = 1; i < num_sections; i++) { + unsigned long start = x[i].sh_addr; + unsigned long end = start + x[i].sh_size; + unsigned long offset = x[i].sh_offset; + + if (addr >= start && addr <= end) + return addr - start + offset; + } + return 0; +} + + +#define LINE_SIZE 100 + +static void get_symbol_from_map(Elf_Ehdr *hdr, FILE *f, char *name, + struct sym *s) +{ + char l[LINE_SIZE]; + char *w, *p, *n; + + s->size = 0; + s->address = 0; + s->offset = 0; + if (fseek(f, 0, SEEK_SET) != 0) { + perror("File seek failed"); + exit(EXIT_FAILURE); + } + while (fgets(l, LINE_SIZE, f)) { + p = strchr(l, '\n'); + if (!p) { + err("Missing line ending.\n"); + return; + } + n = strstr(l, name); + if (n) + break; + } + if (!n) { + err("Unable to find symbol: %s\n", name); + return; + } + w = strchr(l, ' '); + if (!w) + return; + + *w = '\0'; + s->address = strtoul(l, NULL, 16); + if (s->address == 0) + return; + s->offset = get_offset_from_address(hdr, s->address); + s->name = name; + s->content = (void *)hdr + s->offset; +} + +static Elf_Sym *find_elf_symbol(Elf_Ehdr *hdr, Elf_Shdr *symtab, char *name) +{ + Elf_Sym *sym, *symtab_start; + char *strtab, *symname; + unsigned int link; + Elf_Shdr *x; + int i, n; + + x = (void *)hdr + hdr->e_shoff; + link = symtab->sh_link; + symtab_start = (void *)hdr + symtab->sh_offset; + n = symtab->sh_size / symtab->sh_entsize; + strtab = (void *)hdr + x[link].sh_offset; + + for (i = 0; i < n; i++) { + sym = &symtab_start[i]; + symname = strtab + sym->st_name; + if (strcmp(symname, name) == 0) + return sym; + } + err("Unable to find symbol: %s\n", name); + return NULL; +} + +static void get_symbol_from_table(Elf_Ehdr *hdr, Elf_Shdr *symtab, + char *name, struct sym *s) +{ + Elf_Shdr *sec; + int secndx; + Elf_Sym *elf_sym; + Elf_Shdr *x; + + x = (void *)hdr + hdr->e_shoff; + s->size = 0; + s->address = 0; + s->offset = 0; + elf_sym = find_elf_symbol(hdr, symtab, name); + if (!elf_sym) + return; + secndx = elf_sym->st_shndx; + if (!secndx) + return; + sec = &x[secndx]; + s->size = elf_sym->st_size; + s->address = elf_sym->st_value; + s->offset = s->address - sec->sh_addr + + sec->sh_offset; + s->name = name; + s->content = (void *)hdr + s->offset; +} + +static Elf_Shdr *get_symbol_table(Elf_Ehdr *hdr) +{ + Elf_Shdr *x; + unsigned int i, num_sections; + + x = (void *)hdr + hdr->e_shoff; + if (hdr->e_shnum == SHN_UNDEF) + num_sections = x[0].sh_size; + else + num_sections = hdr->e_shnum; + + for (i = 1; i < num_sections; i++) + if (x[i].sh_type == SHT_SYMTAB) + return &x[i]; + return NULL; +} + +static void *map_file(char *file_name, int *size) +{ + struct stat st; + void *map; + int fd; + + fd = open(file_name, O_RDWR); + if (fd < 0) { + perror(file_name); + return NULL; + } + if (fstat(fd, &st)) { + perror("Could not determine file size"); + close(fd); + return NULL; + } + *size = st.st_size; + map = mmap(NULL, *size, PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0); + if (map == MAP_FAILED) { + perror("Mapping to memory failed"); + close(fd); + return NULL; + } + close(fd); + return map; +} + +static char *read_file(char *file_name, int *size) +{ + struct stat st; + char *buf; + int fd; + + fd = open(file_name, O_RDONLY); + if (fd < 0) { + perror(file_name); + return NULL; + } + if (fstat(fd, &st)) { + perror("Could not determine file size"); + close(fd); + return NULL; + } + *size = st.st_size; + buf = malloc(*size); + if (!buf) { + perror("Allocating memory failed"); + close(fd); + return NULL; + } + if (read(fd, buf, *size) != *size) { + perror("File read failed"); + close(fd); + return NULL; + } + close(fd); + return buf; +} + +static void print_sym(Elf_Ehdr *hdr, struct sym *s) +{ + info("sym: %s\n", s->name); + info("addr: 0x%lx\n", s->address); + info("size: %d\n", s->size); + info("offset: 0x%lx\n", (unsigned long)s->offset); +} + +static void print_usage(char *e) +{ + printf("Usage %s [-s <System.map>] -b <vmlinux> -c <certfile>\n", e); +} + +int main(int argc, char **argv) +{ + char *system_map_file = NULL; + char *vmlinux_file = NULL; + char *cert_file = NULL; + int vmlinux_size; + int cert_size; + Elf_Ehdr *hdr; + char *cert; + FILE *system_map; + unsigned long *lsize; + int *used; + int opt; + Elf_Shdr *symtab = NULL; + struct sym cert_sym, lsize_sym, used_sym; + + while ((opt = getopt(argc, argv, "b:c:s:")) != -1) { + switch (opt) { + case 's': + system_map_file = optarg; + break; + case 'b': + vmlinux_file = optarg; + break; + case 'c': + cert_file = optarg; + break; + default: + break; + } + } + + if (!vmlinux_file || !cert_file) { + print_usage(argv[0]); + exit(EXIT_FAILURE); + } + + cert = read_file(cert_file, &cert_size); + if (!cert) + exit(EXIT_FAILURE); + + hdr = map_file(vmlinux_file, &vmlinux_size); + if (!hdr) + exit(EXIT_FAILURE); + + if (vmlinux_size < sizeof(*hdr)) { + err("Invalid ELF file.\n"); + exit(EXIT_FAILURE); + } + + if ((hdr->e_ident[EI_MAG0] != ELFMAG0) || + (hdr->e_ident[EI_MAG1] != ELFMAG1) || + (hdr->e_ident[EI_MAG2] != ELFMAG2) || + (hdr->e_ident[EI_MAG3] != ELFMAG3)) { + err("Invalid ELF magic.\n"); + exit(EXIT_FAILURE); + } + + if (hdr->e_ident[EI_CLASS] != CURRENT_ELFCLASS) { + err("ELF class mismatch.\n"); + exit(EXIT_FAILURE); + } + + if (hdr->e_ident[EI_DATA] != endianness()) { + err("ELF endian mismatch.\n"); + exit(EXIT_FAILURE); + } + + if (hdr->e_shoff > vmlinux_size) { + err("Could not find section header.\n"); + exit(EXIT_FAILURE); + } + + symtab = get_symbol_table(hdr); + if (!symtab) { + warn("Could not find the symbol table.\n"); + if (!system_map_file) { + err("Please provide a System.map file.\n"); + print_usage(argv[0]); + exit(EXIT_FAILURE); + } + + system_map = fopen(system_map_file, "r"); + if (!system_map) { + perror(system_map_file); + exit(EXIT_FAILURE); + } + get_symbol_from_map(hdr, system_map, CERT_SYM, &cert_sym); + get_symbol_from_map(hdr, system_map, USED_SYM, &used_sym); + get_symbol_from_map(hdr, system_map, LSIZE_SYM, &lsize_sym); + cert_sym.size = used_sym.address - cert_sym.address; + } else { + info("Symbol table found.\n"); + if (system_map_file) + warn("System.map is ignored.\n"); + get_symbol_from_table(hdr, symtab, CERT_SYM, &cert_sym); + get_symbol_from_table(hdr, symtab, USED_SYM, &used_sym); + get_symbol_from_table(hdr, symtab, LSIZE_SYM, &lsize_sym); + } + + if (!cert_sym.offset || !lsize_sym.offset || !used_sym.offset) + exit(EXIT_FAILURE); + + print_sym(hdr, &cert_sym); + print_sym(hdr, &used_sym); + print_sym(hdr, &lsize_sym); + + lsize = (unsigned long *)lsize_sym.content; + used = (int *)used_sym.content; + + if (cert_sym.size < cert_size) { + err("Certificate is larger than the reserved area!\n"); + exit(EXIT_FAILURE); + } + + /* If the existing cert is the same, don't overwrite */ + if (cert_size == *used && + strncmp(cert_sym.content, cert, cert_size) == 0) { + warn("Certificate was already inserted.\n"); + exit(EXIT_SUCCESS); + } + + if (*used > 0) + warn("Replacing previously inserted certificate.\n"); + + memcpy(cert_sym.content, cert, cert_size); + if (cert_size < cert_sym.size) + memset(cert_sym.content + cert_size, + 0, cert_sym.size - cert_size); + + *lsize = *lsize + cert_size - *used; + *used = cert_size; + info("Inserted the contents of %s into %lx.\n", cert_file, + cert_sym.address); + info("Used %d bytes out of %d bytes reserved.\n", *used, + cert_sym.size); + exit(EXIT_SUCCESS); +} diff --git a/src/net/scripts/jobserver-exec b/src/net/scripts/jobserver-exec new file mode 100755 index 0000000..0fdb31a --- /dev/null +++ b/src/net/scripts/jobserver-exec @@ -0,0 +1,66 @@ +#!/usr/bin/env python +# SPDX-License-Identifier: GPL-2.0+ +# +# This determines how many parallel tasks "make" is expecting, as it is +# not exposed via an special variables, reserves them all, runs a subprocess +# with PARALLELISM environment variable set, and releases the jobs back again. +# +# https://www.gnu.org/software/make/manual/html_node/POSIX-Jobserver.html#POSIX-Jobserver +from __future__ import print_function +import os, sys, errno +import subprocess + +# Extract and prepare jobserver file descriptors from envirnoment. +claim = 0 +jobs = b"" +try: + # Fetch the make environment options. + flags = os.environ['MAKEFLAGS'] + + # Look for "--jobserver=R,W" + # Note that GNU Make has used --jobserver-fds and --jobserver-auth + # so this handles all of them. + opts = [x for x in flags.split(" ") if x.startswith("--jobserver")] + + # Parse out R,W file descriptor numbers and set them nonblocking. + fds = opts[0].split("=", 1)[1] + reader, writer = [int(x) for x in fds.split(",", 1)] + # Open a private copy of reader to avoid setting nonblocking + # on an unexpecting process with the same reader fd. + reader = os.open("/proc/self/fd/%d" % (reader), + os.O_RDONLY | os.O_NONBLOCK) + + # Read out as many jobserver slots as possible. + while True: + try: + slot = os.read(reader, 8) + jobs += slot + except (OSError, IOError) as e: + if e.errno == errno.EWOULDBLOCK: + # Stop at the end of the jobserver queue. + break + # If something went wrong, give back the jobs. + if len(jobs): + os.write(writer, jobs) + raise e + # Add a bump for our caller's reserveration, since we're just going + # to sit here blocked on our child. + claim = len(jobs) + 1 +except (KeyError, IndexError, ValueError, OSError, IOError) as e: + # Any missing environment strings or bad fds should result in just + # not being parallel. + pass + +# We can only claim parallelism if there was a jobserver (i.e. a top-level +# "-jN" argument) and there were no other failures. Otherwise leave out the +# environment variable and let the child figure out what is best. +if claim > 0: + os.environ['PARALLELISM'] = '%d' % (claim) + +rc = subprocess.call(sys.argv[1:]) + +# Return all the reserved slots. +if len(jobs): + os.write(writer, jobs) + +sys.exit(rc) diff --git a/src/net/scripts/kallsyms.c b/src/net/scripts/kallsyms.c new file mode 100644 index 0000000..fa1cb7d --- /dev/null +++ b/src/net/scripts/kallsyms.c @@ -0,0 +1,832 @@ +/* Generate assembler source containing symbol information + * + * Copyright 2002 by Kai Germaschewski + * + * This software may be used and distributed according to the terms + * of the GNU General Public License, incorporated herein by reference. + * + * Usage: nm -n vmlinux | scripts/kallsyms [--all-symbols] > symbols.S + * + * Table compression uses all the unused char codes on the symbols and + * maps these to the most used substrings (tokens). For instance, it might + * map char code 0xF7 to represent "write_" and then in every symbol where + * "write_" appears it can be replaced by 0xF7, saving 5 bytes. + * The used codes themselves are also placed in the table so that the + * decompresion can work without "special cases". + * Applied to kernel symbols, this usually produces a compression ratio + * of about 50%. + * + */ + +#include <stdbool.h> +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <ctype.h> +#include <limits.h> + +#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof(arr[0])) + +#define _stringify_1(x) #x +#define _stringify(x) _stringify_1(x) + +#define KSYM_NAME_LEN 512 + +/* + * A substantially bigger size than the current maximum. + * + * It cannot be defined as an expression because it gets stringified + * for the fscanf() format string. Therefore, a _Static_assert() is + * used instead to maintain the relationship with KSYM_NAME_LEN. + */ +#define KSYM_NAME_LEN_BUFFER 2048 +_Static_assert( + KSYM_NAME_LEN_BUFFER == KSYM_NAME_LEN * 4, + "Please keep KSYM_NAME_LEN_BUFFER in sync with KSYM_NAME_LEN" +); + +struct sym_entry { + unsigned long long addr; + unsigned int len; + unsigned int start_pos; + unsigned int percpu_absolute; + unsigned char sym[]; +}; + +struct addr_range { + const char *start_sym, *end_sym; + unsigned long long start, end; +}; + +static unsigned long long _text; +static unsigned long long relative_base; +static struct addr_range text_ranges[] = { + { "_stext", "_etext" }, + { "_sinittext", "_einittext" }, +}; +#define text_range_text (&text_ranges[0]) +#define text_range_inittext (&text_ranges[1]) + +static struct addr_range percpu_range = { + "__per_cpu_start", "__per_cpu_end", -1ULL, 0 +}; + +static struct sym_entry **table; +static unsigned int table_size, table_cnt; +static int all_symbols; +static int absolute_percpu; +static int base_relative; + +static int token_profit[0x10000]; + +/* the table that holds the result of the compression */ +static unsigned char best_table[256][2]; +static unsigned char best_table_len[256]; + + +static void usage(void) +{ + fprintf(stderr, "Usage: kallsyms [--all-symbols] " + "[--base-relative] < in.map > out.S\n"); + exit(1); +} + +static char *sym_name(const struct sym_entry *s) +{ + return (char *)s->sym + 1; +} + +static bool is_ignored_symbol(const char *name, char type) +{ + /* Symbol names that exactly match to the following are ignored.*/ + static const char * const ignored_symbols[] = { + /* + * Symbols which vary between passes. Passes 1 and 2 must have + * identical symbol lists. The kallsyms_* symbols below are + * only added after pass 1, they would be included in pass 2 + * when --all-symbols is specified so exclude them to get a + * stable symbol list. + */ + "kallsyms_addresses", + "kallsyms_offsets", + "kallsyms_relative_base", + "kallsyms_num_syms", + "kallsyms_names", + "kallsyms_markers", + "kallsyms_token_table", + "kallsyms_token_index", + /* Exclude linker generated symbols which vary between passes */ + "_SDA_BASE_", /* ppc */ + "_SDA2_BASE_", /* ppc */ + NULL + }; + + /* Symbol names that begin with the following are ignored.*/ + static const char * const ignored_prefixes[] = { + "$", /* local symbols for ARM, MIPS, etc. */ + ".LASANPC", /* s390 kasan local symbols */ + "__crc_", /* modversions */ + "__efistub_", /* arm64 EFI stub namespace */ + "__kvm_nvhe_", /* arm64 non-VHE KVM namespace */ + "__AArch64ADRPThunk_", /* arm64 lld */ + "__ARMV5PILongThunk_", /* arm lld */ + "__ARMV7PILongThunk_", + "__ThumbV7PILongThunk_", + "__LA25Thunk_", /* mips lld */ + "__microLA25Thunk_", + NULL + }; + + /* Symbol names that end with the following are ignored.*/ + static const char * const ignored_suffixes[] = { + "_from_arm", /* arm */ + "_from_thumb", /* arm */ + "_veneer", /* arm */ + NULL + }; + + /* Symbol names that contain the following are ignored.*/ + static const char * const ignored_matches[] = { + ".long_branch.", /* ppc stub */ + ".plt_branch.", /* ppc stub */ + NULL + }; + + const char * const *p; + + for (p = ignored_symbols; *p; p++) + if (!strcmp(name, *p)) + return true; + + for (p = ignored_prefixes; *p; p++) + if (!strncmp(name, *p, strlen(*p))) + return true; + + for (p = ignored_suffixes; *p; p++) { + int l = strlen(name) - strlen(*p); + + if (l >= 0 && !strcmp(name + l, *p)) + return true; + } + + for (p = ignored_matches; *p; p++) { + if (strstr(name, *p)) + return true; + } + + if (type == 'U' || type == 'u') + return true; + /* exclude debugging symbols */ + if (type == 'N' || type == 'n') + return true; + + if (toupper(type) == 'A') { + /* Keep these useful absolute symbols */ + if (strcmp(name, "__kernel_syscall_via_break") && + strcmp(name, "__kernel_syscall_via_epc") && + strcmp(name, "__kernel_sigtramp") && + strcmp(name, "__gp")) + return true; + } + + return false; +} + +static void check_symbol_range(const char *sym, unsigned long long addr, + struct addr_range *ranges, int entries) +{ + size_t i; + struct addr_range *ar; + + for (i = 0; i < entries; ++i) { + ar = &ranges[i]; + + if (strcmp(sym, ar->start_sym) == 0) { + ar->start = addr; + return; + } else if (strcmp(sym, ar->end_sym) == 0) { + ar->end = addr; + return; + } + } +} + +static struct sym_entry *read_symbol(FILE *in) +{ + char name[KSYM_NAME_LEN_BUFFER+1], type; + unsigned long long addr; + unsigned int len; + struct sym_entry *sym; + int rc; + + rc = fscanf(in, "%llx %c %" _stringify(KSYM_NAME_LEN_BUFFER) "s\n", &addr, &type, name); + if (rc != 3) { + if (rc != EOF && fgets(name, ARRAY_SIZE(name), in) == NULL) + fprintf(stderr, "Read error or end of file.\n"); + return NULL; + } + if (strlen(name) >= KSYM_NAME_LEN) { + fprintf(stderr, "Symbol %s too long for kallsyms (%zu >= %d).\n" + "Please increase KSYM_NAME_LEN both in kernel and kallsyms.c\n", + name, strlen(name), KSYM_NAME_LEN); + return NULL; + } + + if (strcmp(name, "_text") == 0) + _text = addr; + + /* Ignore most absolute/undefined (?) symbols. */ + if (is_ignored_symbol(name, type)) + return NULL; + + check_symbol_range(name, addr, text_ranges, ARRAY_SIZE(text_ranges)); + check_symbol_range(name, addr, &percpu_range, 1); + + /* include the type field in the symbol name, so that it gets + * compressed together */ + + len = strlen(name) + 1; + + sym = malloc(sizeof(*sym) + len + 1); + if (!sym) { + fprintf(stderr, "kallsyms failure: " + "unable to allocate required amount of memory\n"); + exit(EXIT_FAILURE); + } + sym->addr = addr; + sym->len = len; + sym->sym[0] = type; + strcpy(sym_name(sym), name); + sym->percpu_absolute = 0; + + return sym; +} + +static int symbol_in_range(const struct sym_entry *s, + const struct addr_range *ranges, int entries) +{ + size_t i; + const struct addr_range *ar; + + for (i = 0; i < entries; ++i) { + ar = &ranges[i]; + + if (s->addr >= ar->start && s->addr <= ar->end) + return 1; + } + + return 0; +} + +static int symbol_valid(const struct sym_entry *s) +{ + const char *name = sym_name(s); + + /* if --all-symbols is not specified, then symbols outside the text + * and inittext sections are discarded */ + if (!all_symbols) { + if (symbol_in_range(s, text_ranges, + ARRAY_SIZE(text_ranges)) == 0) + return 0; + /* Corner case. Discard any symbols with the same value as + * _etext _einittext; they can move between pass 1 and 2 when + * the kallsyms data are added. If these symbols move then + * they may get dropped in pass 2, which breaks the kallsyms + * rules. + */ + if ((s->addr == text_range_text->end && + strcmp(name, text_range_text->end_sym)) || + (s->addr == text_range_inittext->end && + strcmp(name, text_range_inittext->end_sym))) + return 0; + } + + return 1; +} + +/* remove all the invalid symbols from the table */ +static void shrink_table(void) +{ + unsigned int i, pos; + + pos = 0; + for (i = 0; i < table_cnt; i++) { + if (symbol_valid(table[i])) { + if (pos != i) + table[pos] = table[i]; + pos++; + } else { + free(table[i]); + } + } + table_cnt = pos; + + /* When valid symbol is not registered, exit to error */ + if (!table_cnt) { + fprintf(stderr, "No valid symbol.\n"); + exit(1); + } +} + +static void read_map(FILE *in) +{ + struct sym_entry *sym; + + while (!feof(in)) { + sym = read_symbol(in); + if (!sym) + continue; + + sym->start_pos = table_cnt; + + if (table_cnt >= table_size) { + table_size += 10000; + table = realloc(table, sizeof(*table) * table_size); + if (!table) { + fprintf(stderr, "out of memory\n"); + exit (1); + } + } + + table[table_cnt++] = sym; + } +} + +static void output_label(const char *label) +{ + printf(".globl %s\n", label); + printf("\tALGN\n"); + printf("%s:\n", label); +} + +/* Provide proper symbols relocatability by their '_text' relativeness. */ +static void output_address(unsigned long long addr) +{ + if (_text <= addr) + printf("\tPTR\t_text + %#llx\n", addr - _text); + else + printf("\tPTR\t_text - %#llx\n", _text - addr); +} + +/* uncompress a compressed symbol. When this function is called, the best table + * might still be compressed itself, so the function needs to be recursive */ +static int expand_symbol(const unsigned char *data, int len, char *result) +{ + int c, rlen, total=0; + + while (len) { + c = *data; + /* if the table holds a single char that is the same as the one + * we are looking for, then end the search */ + if (best_table[c][0]==c && best_table_len[c]==1) { + *result++ = c; + total++; + } else { + /* if not, recurse and expand */ + rlen = expand_symbol(best_table[c], best_table_len[c], result); + total += rlen; + result += rlen; + } + data++; + len--; + } + *result=0; + + return total; +} + +static int symbol_absolute(const struct sym_entry *s) +{ + return s->percpu_absolute; +} + +static void write_src(void) +{ + unsigned int i, k, off; + unsigned int best_idx[256]; + unsigned int *markers; + char buf[KSYM_NAME_LEN]; + + printf("#include <asm/bitsperlong.h>\n"); + printf("#if BITS_PER_LONG == 64\n"); + printf("#define PTR .quad\n"); + printf("#define ALGN .balign 8\n"); + printf("#else\n"); + printf("#define PTR .long\n"); + printf("#define ALGN .balign 4\n"); + printf("#endif\n"); + + printf("\t.section .rodata, \"a\"\n"); + + if (!base_relative) + output_label("kallsyms_addresses"); + else + output_label("kallsyms_offsets"); + + for (i = 0; i < table_cnt; i++) { + if (base_relative) { + /* + * Use the offset relative to the lowest value + * encountered of all relative symbols, and emit + * non-relocatable fixed offsets that will be fixed + * up at runtime. + */ + + long long offset; + int overflow; + + if (!absolute_percpu) { + offset = table[i]->addr - relative_base; + overflow = (offset < 0 || offset > UINT_MAX); + } else if (symbol_absolute(table[i])) { + offset = table[i]->addr; + overflow = (offset < 0 || offset > INT_MAX); + } else { + offset = relative_base - table[i]->addr - 1; + overflow = (offset < INT_MIN || offset >= 0); + } + if (overflow) { + fprintf(stderr, "kallsyms failure: " + "%s symbol value %#llx out of range in relative mode\n", + symbol_absolute(table[i]) ? "absolute" : "relative", + table[i]->addr); + exit(EXIT_FAILURE); + } + printf("\t.long\t%#x\n", (int)offset); + } else if (!symbol_absolute(table[i])) { + output_address(table[i]->addr); + } else { + printf("\tPTR\t%#llx\n", table[i]->addr); + } + } + printf("\n"); + + if (base_relative) { + output_label("kallsyms_relative_base"); + output_address(relative_base); + printf("\n"); + } + + output_label("kallsyms_num_syms"); + printf("\t.long\t%u\n", table_cnt); + printf("\n"); + + /* table of offset markers, that give the offset in the compressed stream + * every 256 symbols */ + markers = malloc(sizeof(unsigned int) * ((table_cnt + 255) / 256)); + if (!markers) { + fprintf(stderr, "kallsyms failure: " + "unable to allocate required memory\n"); + exit(EXIT_FAILURE); + } + + output_label("kallsyms_names"); + off = 0; + for (i = 0; i < table_cnt; i++) { + if ((i & 0xFF) == 0) + markers[i >> 8] = off; + + /* There cannot be any symbol of length zero. */ + if (table[i]->len == 0) { + fprintf(stderr, "kallsyms failure: " + "unexpected zero symbol length\n"); + exit(EXIT_FAILURE); + } + + /* Only lengths that fit in up-to-two-byte ULEB128 are supported. */ + if (table[i]->len > 0x3FFF) { + fprintf(stderr, "kallsyms failure: " + "unexpected huge symbol length\n"); + exit(EXIT_FAILURE); + } + + /* Encode length with ULEB128. */ + if (table[i]->len <= 0x7F) { + /* Most symbols use a single byte for the length. */ + printf("\t.byte 0x%02x", table[i]->len); + off += table[i]->len + 1; + } else { + /* "Big" symbols use two bytes. */ + printf("\t.byte 0x%02x, 0x%02x", + (table[i]->len & 0x7F) | 0x80, + (table[i]->len >> 7) & 0x7F); + off += table[i]->len + 2; + } + for (k = 0; k < table[i]->len; k++) + printf(", 0x%02x", table[i]->sym[k]); + printf("\n"); + } + printf("\n"); + + output_label("kallsyms_markers"); + for (i = 0; i < ((table_cnt + 255) >> 8); i++) + printf("\t.long\t%u\n", markers[i]); + printf("\n"); + + free(markers); + + output_label("kallsyms_token_table"); + off = 0; + for (i = 0; i < 256; i++) { + best_idx[i] = off; + expand_symbol(best_table[i], best_table_len[i], buf); + printf("\t.asciz\t\"%s\"\n", buf); + off += strlen(buf) + 1; + } + printf("\n"); + + output_label("kallsyms_token_index"); + for (i = 0; i < 256; i++) + printf("\t.short\t%d\n", best_idx[i]); + printf("\n"); +} + + +/* table lookup compression functions */ + +/* count all the possible tokens in a symbol */ +static void learn_symbol(const unsigned char *symbol, int len) +{ + int i; + + for (i = 0; i < len - 1; i++) + token_profit[ symbol[i] + (symbol[i + 1] << 8) ]++; +} + +/* decrease the count for all the possible tokens in a symbol */ +static void forget_symbol(const unsigned char *symbol, int len) +{ + int i; + + for (i = 0; i < len - 1; i++) + token_profit[ symbol[i] + (symbol[i + 1] << 8) ]--; +} + +/* do the initial token count */ +static void build_initial_tok_table(void) +{ + unsigned int i; + + for (i = 0; i < table_cnt; i++) + learn_symbol(table[i]->sym, table[i]->len); +} + +static unsigned char *find_token(unsigned char *str, int len, + const unsigned char *token) +{ + int i; + + for (i = 0; i < len - 1; i++) { + if (str[i] == token[0] && str[i+1] == token[1]) + return &str[i]; + } + return NULL; +} + +/* replace a given token in all the valid symbols. Use the sampled symbols + * to update the counts */ +static void compress_symbols(const unsigned char *str, int idx) +{ + unsigned int i, len, size; + unsigned char *p1, *p2; + + for (i = 0; i < table_cnt; i++) { + + len = table[i]->len; + p1 = table[i]->sym; + + /* find the token on the symbol */ + p2 = find_token(p1, len, str); + if (!p2) continue; + + /* decrease the counts for this symbol's tokens */ + forget_symbol(table[i]->sym, len); + + size = len; + + do { + *p2 = idx; + p2++; + size -= (p2 - p1); + memmove(p2, p2 + 1, size); + p1 = p2; + len--; + + if (size < 2) break; + + /* find the token on the symbol */ + p2 = find_token(p1, size, str); + + } while (p2); + + table[i]->len = len; + + /* increase the counts for this symbol's new tokens */ + learn_symbol(table[i]->sym, len); + } +} + +/* search the token with the maximum profit */ +static int find_best_token(void) +{ + int i, best, bestprofit; + + bestprofit=-10000; + best = 0; + + for (i = 0; i < 0x10000; i++) { + if (token_profit[i] > bestprofit) { + best = i; + bestprofit = token_profit[i]; + } + } + return best; +} + +/* this is the core of the algorithm: calculate the "best" table */ +static void optimize_result(void) +{ + int i, best; + + /* using the '\0' symbol last allows compress_symbols to use standard + * fast string functions */ + for (i = 255; i >= 0; i--) { + + /* if this table slot is empty (it is not used by an actual + * original char code */ + if (!best_table_len[i]) { + + /* find the token with the best profit value */ + best = find_best_token(); + if (token_profit[best] == 0) + break; + + /* place it in the "best" table */ + best_table_len[i] = 2; + best_table[i][0] = best & 0xFF; + best_table[i][1] = (best >> 8) & 0xFF; + + /* replace this token in all the valid symbols */ + compress_symbols(best_table[i], i); + } + } +} + +/* start by placing the symbols that are actually used on the table */ +static void insert_real_symbols_in_table(void) +{ + unsigned int i, j, c; + + for (i = 0; i < table_cnt; i++) { + for (j = 0; j < table[i]->len; j++) { + c = table[i]->sym[j]; + best_table[c][0]=c; + best_table_len[c]=1; + } + } +} + +static void optimize_token_table(void) +{ + build_initial_tok_table(); + + insert_real_symbols_in_table(); + + optimize_result(); +} + +/* guess for "linker script provide" symbol */ +static int may_be_linker_script_provide_symbol(const struct sym_entry *se) +{ + const char *symbol = sym_name(se); + int len = se->len - 1; + + if (len < 8) + return 0; + + if (symbol[0] != '_' || symbol[1] != '_') + return 0; + + /* __start_XXXXX */ + if (!memcmp(symbol + 2, "start_", 6)) + return 1; + + /* __stop_XXXXX */ + if (!memcmp(symbol + 2, "stop_", 5)) + return 1; + + /* __end_XXXXX */ + if (!memcmp(symbol + 2, "end_", 4)) + return 1; + + /* __XXXXX_start */ + if (!memcmp(symbol + len - 6, "_start", 6)) + return 1; + + /* __XXXXX_end */ + if (!memcmp(symbol + len - 4, "_end", 4)) + return 1; + + return 0; +} + +static int compare_symbols(const void *a, const void *b) +{ + const struct sym_entry *sa = *(const struct sym_entry **)a; + const struct sym_entry *sb = *(const struct sym_entry **)b; + int wa, wb; + + /* sort by address first */ + if (sa->addr > sb->addr) + return 1; + if (sa->addr < sb->addr) + return -1; + + /* sort by "weakness" type */ + wa = (sa->sym[0] == 'w') || (sa->sym[0] == 'W'); + wb = (sb->sym[0] == 'w') || (sb->sym[0] == 'W'); + if (wa != wb) + return wa - wb; + + /* sort by "linker script provide" type */ + wa = may_be_linker_script_provide_symbol(sa); + wb = may_be_linker_script_provide_symbol(sb); + if (wa != wb) + return wa - wb; + + /* sort by the number of prefix underscores */ + wa = strspn(sym_name(sa), "_"); + wb = strspn(sym_name(sb), "_"); + if (wa != wb) + return wa - wb; + + /* sort by initial order, so that other symbols are left undisturbed */ + return sa->start_pos - sb->start_pos; +} + +static void sort_symbols(void) +{ + qsort(table, table_cnt, sizeof(table[0]), compare_symbols); +} + +static void make_percpus_absolute(void) +{ + unsigned int i; + + for (i = 0; i < table_cnt; i++) + if (symbol_in_range(table[i], &percpu_range, 1)) { + /* + * Keep the 'A' override for percpu symbols to + * ensure consistent behavior compared to older + * versions of this tool. + */ + table[i]->sym[0] = 'A'; + table[i]->percpu_absolute = 1; + } +} + +/* find the minimum non-absolute symbol address */ +static void record_relative_base(void) +{ + unsigned int i; + + for (i = 0; i < table_cnt; i++) + if (!symbol_absolute(table[i])) { + /* + * The table is sorted by address. + * Take the first non-absolute symbol value. + */ + relative_base = table[i]->addr; + return; + } +} + +int main(int argc, char **argv) +{ + if (argc >= 2) { + int i; + for (i = 1; i < argc; i++) { + if(strcmp(argv[i], "--all-symbols") == 0) + all_symbols = 1; + else if (strcmp(argv[i], "--absolute-percpu") == 0) + absolute_percpu = 1; + else if (strcmp(argv[i], "--base-relative") == 0) + base_relative = 1; + else + usage(); + } + } else if (argc != 1) + usage(); + + read_map(stdin); + shrink_table(); + if (absolute_percpu) + make_percpus_absolute(); + sort_symbols(); + if (base_relative) + record_relative_base(); + optimize_token_table(); + write_src(); + + return 0; +} diff --git a/src/net/scripts/kconfig/.gitignore b/src/net/scripts/kconfig/.gitignore new file mode 100644 index 0000000..c3d537c --- /dev/null +++ b/src/net/scripts/kconfig/.gitignore @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-only +/qconf-moc.cc +*conf-cfg + +# +# configuration programs +# +conf +mconf +nconf +qconf +gconf diff --git a/src/net/scripts/kconfig/Makefile b/src/net/scripts/kconfig/Makefile new file mode 100644 index 0000000..e46df0a --- /dev/null +++ b/src/net/scripts/kconfig/Makefile @@ -0,0 +1,216 @@ +# SPDX-License-Identifier: GPL-2.0 +# =========================================================================== +# Kernel configuration targets +# These targets are used from top-level makefile + +PHONY += xconfig gconfig menuconfig config localmodconfig localyesconfig \ + build_menuconfig build_nconfig build_gconfig build_xconfig + +ifdef KBUILD_KCONFIG +Kconfig := $(KBUILD_KCONFIG) +else +Kconfig := Kconfig +endif + +ifeq ($(quiet),silent_) +silent := -s +endif + +# We need this, in case the user has it in its environment +unexport CONFIG_ + +xconfig: $(obj)/qconf + $(Q)$< $(silent) $(Kconfig) + +gconfig: $(obj)/gconf + $(Q)$< $(silent) $(Kconfig) + +menuconfig: $(obj)/mconf + $(Q)$< $(silent) $(Kconfig) + +config: $(obj)/conf + $(Q)$< $(silent) --oldaskconfig $(Kconfig) + +nconfig: $(obj)/nconf + $(Q)$< $(silent) $(Kconfig) + +build_menuconfig: $(obj)/mconf + +build_nconfig: $(obj)/nconf + +build_gconfig: $(obj)/gconf + +build_xconfig: $(obj)/qconf + +localyesconfig localmodconfig: $(obj)/conf + $(Q)$(PERL) $(srctree)/$(src)/streamline_config.pl --$@ $(srctree) $(Kconfig) > .tmp.config + $(Q)if [ -f .config ]; then \ + cmp -s .tmp.config .config || \ + (mv -f .config .config.old.1; \ + mv -f .tmp.config .config; \ + $< $(silent) --oldconfig $(Kconfig); \ + mv -f .config.old.1 .config.old) \ + else \ + mv -f .tmp.config .config; \ + $< $(silent) --oldconfig $(Kconfig); \ + fi + $(Q)rm -f .tmp.config + +# These targets map 1:1 to the commandline options of 'conf' +# +# Note: +# syncconfig has become an internal implementation detail and is now +# deprecated for external use +simple-targets := oldconfig allnoconfig allyesconfig allmodconfig \ + alldefconfig randconfig listnewconfig olddefconfig syncconfig \ + helpnewconfig yes2modconfig mod2yesconfig + +PHONY += $(simple-targets) + +$(simple-targets): $(obj)/conf + $(Q)$< $(silent) --$@ $(Kconfig) + +PHONY += savedefconfig defconfig + +savedefconfig: $(obj)/conf + $(Q)$< $(silent) --$@=defconfig $(Kconfig) + +defconfig: $(obj)/conf +ifneq ($(wildcard $(srctree)/arch/$(SRCARCH)/configs/$(KBUILD_DEFCONFIG)),) + @$(kecho) "*** Default configuration is based on '$(KBUILD_DEFCONFIG)'" + $(Q)$< $(silent) --defconfig=arch/$(SRCARCH)/configs/$(KBUILD_DEFCONFIG) $(Kconfig) +else + @$(kecho) "*** Default configuration is based on target '$(KBUILD_DEFCONFIG)'" + $(Q)$(MAKE) -f $(srctree)/Makefile $(KBUILD_DEFCONFIG) +endif + +%_defconfig: $(obj)/conf + $(Q)$< $(silent) --defconfig=arch/$(SRCARCH)/configs/$@ $(Kconfig) + +configfiles=$(wildcard $(srctree)/kernel/configs/$@ $(srctree)/arch/$(SRCARCH)/configs/$@) + +%.config: $(obj)/conf + $(if $(call configfiles),, $(error No configuration exists for this target on this architecture)) + $(Q)$(CONFIG_SHELL) $(srctree)/scripts/kconfig/merge_config.sh -m .config $(configfiles) + $(Q)$(MAKE) -f $(srctree)/Makefile olddefconfig + +PHONY += kvmconfig +kvmconfig: kvm_guest.config + @echo >&2 "WARNING: 'make $@' will be removed after Linux 5.10" + @echo >&2 " Please use 'make $<' instead." + +PHONY += xenconfig +xenconfig: xen.config + @echo >&2 "WARNING: 'make $@' will be removed after Linux 5.10" + @echo >&2 " Please use 'make $<' instead." + +PHONY += tinyconfig +tinyconfig: + $(Q)$(MAKE) -f $(srctree)/Makefile allnoconfig tiny.config + +# CHECK: -o cache_dir=<path> working? +PHONY += testconfig +testconfig: $(obj)/conf + $(Q)$(PYTHON3) -B -m pytest $(srctree)/$(src)/tests \ + -o cache_dir=$(abspath $(obj)/tests/.cache) \ + $(if $(findstring 1,$(KBUILD_VERBOSE)),--capture=no) +clean-files += tests/.cache + +# Help text used by make help +help: + @echo ' config - Update current config utilising a line-oriented program' + @echo ' nconfig - Update current config utilising a ncurses menu based program' + @echo ' menuconfig - Update current config utilising a menu based program' + @echo ' xconfig - Update current config utilising a Qt based front-end' + @echo ' gconfig - Update current config utilising a GTK+ based front-end' + @echo ' oldconfig - Update current config utilising a provided .config as base' + @echo ' localmodconfig - Update current config disabling modules not loaded' + @echo ' except those preserved by LMC_KEEP environment variable' + @echo ' localyesconfig - Update current config converting local mods to core' + @echo ' except those preserved by LMC_KEEP environment variable' + @echo ' defconfig - New config with default from ARCH supplied defconfig' + @echo ' savedefconfig - Save current config as ./defconfig (minimal config)' + @echo ' allnoconfig - New config where all options are answered with no' + @echo ' allyesconfig - New config where all options are accepted with yes' + @echo ' allmodconfig - New config selecting modules when possible' + @echo ' alldefconfig - New config with all symbols set to default' + @echo ' randconfig - New config with random answer to all options' + @echo ' yes2modconfig - Change answers from yes to mod if possible' + @echo ' mod2yesconfig - Change answers from mod to yes if possible' + @echo ' listnewconfig - List new options' + @echo ' helpnewconfig - List new options and help text' + @echo ' olddefconfig - Same as oldconfig but sets new symbols to their' + @echo ' default value without prompting' + @echo ' tinyconfig - Configure the tiniest possible kernel' + @echo ' testconfig - Run Kconfig unit tests (requires python3 and pytest)' + +# =========================================================================== +# object files used by all kconfig flavours +common-objs := confdata.o expr.o lexer.lex.o parser.tab.o preprocess.o \ + symbol.o util.o + +$(obj)/lexer.lex.o: $(obj)/parser.tab.h +HOSTCFLAGS_lexer.lex.o := -I $(srctree)/$(src) +HOSTCFLAGS_parser.tab.o := -I $(srctree)/$(src) + +# conf: Used for defconfig, oldconfig and related targets +hostprogs += conf +conf-objs := conf.o $(common-objs) + +# nconf: Used for the nconfig target based on ncurses +hostprogs += nconf +nconf-objs := nconf.o nconf.gui.o $(common-objs) + +HOSTLDLIBS_nconf = $(shell . $(obj)/nconf-cfg && echo $$libs) +HOSTCFLAGS_nconf.o = $(shell . $(obj)/nconf-cfg && echo $$cflags) +HOSTCFLAGS_nconf.gui.o = $(shell . $(obj)/nconf-cfg && echo $$cflags) + +$(obj)/nconf.o $(obj)/nconf.gui.o: $(obj)/nconf-cfg + +# mconf: Used for the menuconfig target based on lxdialog +hostprogs += mconf +lxdialog := $(addprefix lxdialog/, \ + checklist.o inputbox.o menubox.o textbox.o util.o yesno.o) +mconf-objs := mconf.o $(lxdialog) $(common-objs) + +HOSTLDLIBS_mconf = $(shell . $(obj)/mconf-cfg && echo $$libs) +$(foreach f, mconf.o $(lxdialog), \ + $(eval HOSTCFLAGS_$f = $$(shell . $(obj)/mconf-cfg && echo $$$$cflags))) + +$(addprefix $(obj)/, mconf.o $(lxdialog)): $(obj)/mconf-cfg + +# qconf: Used for the xconfig target based on Qt +hostprogs += qconf +qconf-cxxobjs := qconf.o qconf-moc.o +qconf-objs := images.o $(common-objs) + +HOSTLDLIBS_qconf = $(shell . $(obj)/qconf-cfg && echo $$libs) +HOSTCXXFLAGS_qconf.o = $(shell . $(obj)/qconf-cfg && echo $$cflags) +HOSTCXXFLAGS_qconf-moc.o = $(shell . $(obj)/qconf-cfg && echo $$cflags) + +$(obj)/qconf.o: $(obj)/qconf-cfg + +quiet_cmd_moc = MOC $@ + cmd_moc = $(shell . $(obj)/qconf-cfg && echo $$moc) $< -o $@ + +$(obj)/qconf-moc.cc: $(src)/qconf.h $(obj)/qconf-cfg FORCE + $(call if_changed,moc) + +targets += qconf-moc.cc + +# gconf: Used for the gconfig target based on GTK+ +hostprogs += gconf +gconf-objs := gconf.o images.o $(common-objs) + +HOSTLDLIBS_gconf = $(shell . $(obj)/gconf-cfg && echo $$libs) +HOSTCFLAGS_gconf.o = $(shell . $(obj)/gconf-cfg && echo $$cflags) + +$(obj)/gconf.o: $(obj)/gconf-cfg + +# check if necessary packages are available, and configure build flags +filechk_conf_cfg = $(CONFIG_SHELL) $< + +$(obj)/%conf-cfg: $(src)/%conf-cfg.sh FORCE + $(call filechk,conf_cfg) + +clean-files += *conf-cfg diff --git a/src/net/scripts/kconfig/conf.c b/src/net/scripts/kconfig/conf.c new file mode 100644 index 0000000..f6e548b --- /dev/null +++ b/src/net/scripts/kconfig/conf.c @@ -0,0 +1,727 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2002 Roman Zippel <zippel@linux-m68k.org> + */ + +#include <ctype.h> +#include <limits.h> +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <time.h> +#include <unistd.h> +#include <getopt.h> +#include <sys/stat.h> +#include <sys/time.h> +#include <errno.h> + +#include "lkc.h" + +static void conf(struct menu *menu); +static void check_conf(struct menu *menu); + +enum input_mode { + oldaskconfig, + syncconfig, + oldconfig, + allnoconfig, + allyesconfig, + allmodconfig, + alldefconfig, + randconfig, + defconfig, + savedefconfig, + listnewconfig, + helpnewconfig, + olddefconfig, + yes2modconfig, + mod2yesconfig, +}; +static enum input_mode input_mode = oldaskconfig; + +static int indent = 1; +static int tty_stdio; +static int sync_kconfig; +static int conf_cnt; +static char line[PATH_MAX]; +static struct menu *rootEntry; + +static void print_help(struct menu *menu) +{ + struct gstr help = str_new(); + + menu_get_ext_help(menu, &help); + + printf("\n%s\n", str_get(&help)); + str_free(&help); +} + +static void strip(char *str) +{ + char *p = str; + int l; + + while ((isspace(*p))) + p++; + l = strlen(p); + if (p != str) + memmove(str, p, l + 1); + if (!l) + return; + p = str + l - 1; + while ((isspace(*p))) + *p-- = 0; +} + +/* Helper function to facilitate fgets() by Jean Sacren. */ +static void xfgets(char *str, int size, FILE *in) +{ + if (!fgets(str, size, in)) + fprintf(stderr, "\nError in reading or end of file.\n"); + + if (!tty_stdio) + printf("%s", str); +} + +static int conf_askvalue(struct symbol *sym, const char *def) +{ + enum symbol_type type = sym_get_type(sym); + + if (!sym_has_value(sym)) + printf("(NEW) "); + + line[0] = '\n'; + line[1] = 0; + + if (!sym_is_changeable(sym)) { + printf("%s\n", def); + line[0] = '\n'; + line[1] = 0; + return 0; + } + + switch (input_mode) { + case oldconfig: + case syncconfig: + if (sym_has_value(sym)) { + printf("%s\n", def); + return 0; + } + /* fall through */ + case oldaskconfig: + fflush(stdout); + xfgets(line, sizeof(line), stdin); + return 1; + default: + break; + } + + switch (type) { + case S_INT: + case S_HEX: + case S_STRING: + printf("%s\n", def); + return 1; + default: + ; + } + printf("%s", line); + return 1; +} + +static int conf_string(struct menu *menu) +{ + struct symbol *sym = menu->sym; + const char *def; + + while (1) { + printf("%*s%s ", indent - 1, "", menu->prompt->text); + printf("(%s) ", sym->name); + def = sym_get_string_value(sym); + if (sym_get_string_value(sym)) + printf("[%s] ", def); + if (!conf_askvalue(sym, def)) + return 0; + switch (line[0]) { + case '\n': + break; + case '?': + /* print help */ + if (line[1] == '\n') { + print_help(menu); + def = NULL; + break; + } + /* fall through */ + default: + line[strlen(line)-1] = 0; + def = line; + } + if (def && sym_set_string_value(sym, def)) + return 0; + } +} + +static int conf_sym(struct menu *menu) +{ + struct symbol *sym = menu->sym; + tristate oldval, newval; + + while (1) { + printf("%*s%s ", indent - 1, "", menu->prompt->text); + if (sym->name) + printf("(%s) ", sym->name); + putchar('['); + oldval = sym_get_tristate_value(sym); + switch (oldval) { + case no: + putchar('N'); + break; + case mod: + putchar('M'); + break; + case yes: + putchar('Y'); + break; + } + if (oldval != no && sym_tristate_within_range(sym, no)) + printf("/n"); + if (oldval != mod && sym_tristate_within_range(sym, mod)) + printf("/m"); + if (oldval != yes && sym_tristate_within_range(sym, yes)) + printf("/y"); + printf("/?] "); + if (!conf_askvalue(sym, sym_get_string_value(sym))) + return 0; + strip(line); + + switch (line[0]) { + case 'n': + case 'N': + newval = no; + if (!line[1] || !strcmp(&line[1], "o")) + break; + continue; + case 'm': + case 'M': + newval = mod; + if (!line[1]) + break; + continue; + case 'y': + case 'Y': + newval = yes; + if (!line[1] || !strcmp(&line[1], "es")) + break; + continue; + case 0: + newval = oldval; + break; + case '?': + goto help; + default: + continue; + } + if (sym_set_tristate_value(sym, newval)) + return 0; +help: + print_help(menu); + } +} + +static int conf_choice(struct menu *menu) +{ + struct symbol *sym, *def_sym; + struct menu *child; + bool is_new; + + sym = menu->sym; + is_new = !sym_has_value(sym); + if (sym_is_changeable(sym)) { + conf_sym(menu); + sym_calc_value(sym); + switch (sym_get_tristate_value(sym)) { + case no: + return 1; + case mod: + return 0; + case yes: + break; + } + } else { + switch (sym_get_tristate_value(sym)) { + case no: + return 1; + case mod: + printf("%*s%s\n", indent - 1, "", menu_get_prompt(menu)); + return 0; + case yes: + break; + } + } + + while (1) { + int cnt, def; + + printf("%*s%s\n", indent - 1, "", menu_get_prompt(menu)); + def_sym = sym_get_choice_value(sym); + cnt = def = 0; + line[0] = 0; + for (child = menu->list; child; child = child->next) { + if (!menu_is_visible(child)) + continue; + if (!child->sym) { + printf("%*c %s\n", indent, '*', menu_get_prompt(child)); + continue; + } + cnt++; + if (child->sym == def_sym) { + def = cnt; + printf("%*c", indent, '>'); + } else + printf("%*c", indent, ' '); + printf(" %d. %s", cnt, menu_get_prompt(child)); + if (child->sym->name) + printf(" (%s)", child->sym->name); + if (!sym_has_value(child->sym)) + printf(" (NEW)"); + printf("\n"); + } + printf("%*schoice", indent - 1, ""); + if (cnt == 1) { + printf("[1]: 1\n"); + goto conf_childs; + } + printf("[1-%d?]: ", cnt); + switch (input_mode) { + case oldconfig: + case syncconfig: + if (!is_new) { + cnt = def; + printf("%d\n", cnt); + break; + } + /* fall through */ + case oldaskconfig: + fflush(stdout); + xfgets(line, sizeof(line), stdin); + strip(line); + if (line[0] == '?') { + print_help(menu); + continue; + } + if (!line[0]) + cnt = def; + else if (isdigit(line[0])) + cnt = atoi(line); + else + continue; + break; + default: + break; + } + + conf_childs: + for (child = menu->list; child; child = child->next) { + if (!child->sym || !menu_is_visible(child)) + continue; + if (!--cnt) + break; + } + if (!child) + continue; + if (line[0] && line[strlen(line) - 1] == '?') { + print_help(child); + continue; + } + sym_set_choice_value(sym, child->sym); + for (child = child->list; child; child = child->next) { + indent += 2; + conf(child); + indent -= 2; + } + return 1; + } +} + +static void conf(struct menu *menu) +{ + struct symbol *sym; + struct property *prop; + struct menu *child; + + if (!menu_is_visible(menu)) + return; + + sym = menu->sym; + prop = menu->prompt; + if (prop) { + const char *prompt; + + switch (prop->type) { + case P_MENU: + /* + * Except in oldaskconfig mode, we show only menus that + * contain new symbols. + */ + if (input_mode != oldaskconfig && rootEntry != menu) { + check_conf(menu); + return; + } + /* fall through */ + case P_COMMENT: + prompt = menu_get_prompt(menu); + if (prompt) + printf("%*c\n%*c %s\n%*c\n", + indent, '*', + indent, '*', prompt, + indent, '*'); + default: + ; + } + } + + if (!sym) + goto conf_childs; + + if (sym_is_choice(sym)) { + conf_choice(menu); + if (sym->curr.tri != mod) + return; + goto conf_childs; + } + + switch (sym->type) { + case S_INT: + case S_HEX: + case S_STRING: + conf_string(menu); + break; + default: + conf_sym(menu); + break; + } + +conf_childs: + if (sym) + indent += 2; + for (child = menu->list; child; child = child->next) + conf(child); + if (sym) + indent -= 2; +} + +static void check_conf(struct menu *menu) +{ + struct symbol *sym; + struct menu *child; + + if (!menu_is_visible(menu)) + return; + + sym = menu->sym; + if (sym && !sym_has_value(sym)) { + if (sym_is_changeable(sym) || + (sym_is_choice(sym) && sym_get_tristate_value(sym) == yes)) { + if (input_mode == listnewconfig) { + if (sym->name) { + const char *str; + + if (sym->type == S_STRING) { + str = sym_get_string_value(sym); + str = sym_escape_string_value(str); + printf("%s%s=%s\n", CONFIG_, sym->name, str); + free((void *)str); + } else { + str = sym_get_string_value(sym); + printf("%s%s=%s\n", CONFIG_, sym->name, str); + } + } + } else if (input_mode == helpnewconfig) { + printf("-----\n"); + print_help(menu); + printf("-----\n"); + + } else { + if (!conf_cnt++) + printf("*\n* Restart config...\n*\n"); + rootEntry = menu_get_parent_menu(menu); + conf(rootEntry); + } + } + } + + for (child = menu->list; child; child = child->next) + check_conf(child); +} + +static struct option long_opts[] = { + {"oldaskconfig", no_argument, NULL, oldaskconfig}, + {"oldconfig", no_argument, NULL, oldconfig}, + {"syncconfig", no_argument, NULL, syncconfig}, + {"defconfig", required_argument, NULL, defconfig}, + {"savedefconfig", required_argument, NULL, savedefconfig}, + {"allnoconfig", no_argument, NULL, allnoconfig}, + {"allyesconfig", no_argument, NULL, allyesconfig}, + {"allmodconfig", no_argument, NULL, allmodconfig}, + {"alldefconfig", no_argument, NULL, alldefconfig}, + {"randconfig", no_argument, NULL, randconfig}, + {"listnewconfig", no_argument, NULL, listnewconfig}, + {"helpnewconfig", no_argument, NULL, helpnewconfig}, + {"olddefconfig", no_argument, NULL, olddefconfig}, + {"yes2modconfig", no_argument, NULL, yes2modconfig}, + {"mod2yesconfig", no_argument, NULL, mod2yesconfig}, + {NULL, 0, NULL, 0} +}; + +static void conf_usage(const char *progname) +{ + + printf("Usage: %s [-s] [option] <kconfig-file>\n", progname); + printf("[option] is _one_ of the following:\n"); + printf(" --listnewconfig List new options\n"); + printf(" --helpnewconfig List new options and help text\n"); + printf(" --oldaskconfig Start a new configuration using a line-oriented program\n"); + printf(" --oldconfig Update a configuration using a provided .config as base\n"); + printf(" --syncconfig Similar to oldconfig but generates configuration in\n" + " include/{generated/,config/}\n"); + printf(" --olddefconfig Same as oldconfig but sets new symbols to their default value\n"); + printf(" --defconfig <file> New config with default defined in <file>\n"); + printf(" --savedefconfig <file> Save the minimal current configuration to <file>\n"); + printf(" --allnoconfig New config where all options are answered with no\n"); + printf(" --allyesconfig New config where all options are answered with yes\n"); + printf(" --allmodconfig New config where all options are answered with mod\n"); + printf(" --alldefconfig New config with all symbols set to default\n"); + printf(" --randconfig New config with random answer to all options\n"); + printf(" --yes2modconfig Change answers from yes to mod if possible\n"); + printf(" --mod2yesconfig Change answers from mod to yes if possible\n"); +} + +int main(int ac, char **av) +{ + const char *progname = av[0]; + int opt; + const char *name, *defconfig_file = NULL /* gcc uninit */; + int no_conf_write = 0; + + tty_stdio = isatty(0) && isatty(1); + + while ((opt = getopt_long(ac, av, "s", long_opts, NULL)) != -1) { + if (opt == 's') { + conf_set_message_callback(NULL); + continue; + } + input_mode = (enum input_mode)opt; + switch (opt) { + case syncconfig: + /* + * syncconfig is invoked during the build stage. + * Suppress distracting "configuration written to ..." + */ + conf_set_message_callback(NULL); + sync_kconfig = 1; + break; + case defconfig: + case savedefconfig: + defconfig_file = optarg; + break; + case randconfig: + { + struct timeval now; + unsigned int seed; + char *seed_env; + + /* + * Use microseconds derived seed, + * compensate for systems where it may be zero + */ + gettimeofday(&now, NULL); + seed = (unsigned int)((now.tv_sec + 1) * (now.tv_usec + 1)); + + seed_env = getenv("KCONFIG_SEED"); + if( seed_env && *seed_env ) { + char *endp; + int tmp = (int)strtol(seed_env, &endp, 0); + if (*endp == '\0') { + seed = tmp; + } + } + fprintf( stderr, "KCONFIG_SEED=0x%X\n", seed ); + srand(seed); + break; + } + case oldaskconfig: + case oldconfig: + case allnoconfig: + case allyesconfig: + case allmodconfig: + case alldefconfig: + case listnewconfig: + case helpnewconfig: + case olddefconfig: + case yes2modconfig: + case mod2yesconfig: + break; + case '?': + conf_usage(progname); + exit(1); + break; + } + } + if (ac == optind) { + fprintf(stderr, "%s: Kconfig file missing\n", av[0]); + conf_usage(progname); + exit(1); + } + name = av[optind]; + conf_parse(name); + //zconfdump(stdout); + + switch (input_mode) { + case defconfig: + if (conf_read(defconfig_file)) { + fprintf(stderr, + "***\n" + "*** Can't find default configuration \"%s\"!\n" + "***\n", + defconfig_file); + exit(1); + } + break; + case savedefconfig: + case syncconfig: + case oldaskconfig: + case oldconfig: + case listnewconfig: + case helpnewconfig: + case olddefconfig: + case yes2modconfig: + case mod2yesconfig: + conf_read(NULL); + break; + case allnoconfig: + case allyesconfig: + case allmodconfig: + case alldefconfig: + case randconfig: + name = getenv("KCONFIG_ALLCONFIG"); + if (!name) + break; + if ((strcmp(name, "") != 0) && (strcmp(name, "1") != 0)) { + if (conf_read_simple(name, S_DEF_USER)) { + fprintf(stderr, + "*** Can't read seed configuration \"%s\"!\n", + name); + exit(1); + } + break; + } + switch (input_mode) { + case allnoconfig: name = "allno.config"; break; + case allyesconfig: name = "allyes.config"; break; + case allmodconfig: name = "allmod.config"; break; + case alldefconfig: name = "alldef.config"; break; + case randconfig: name = "allrandom.config"; break; + default: break; + } + if (conf_read_simple(name, S_DEF_USER) && + conf_read_simple("all.config", S_DEF_USER)) { + fprintf(stderr, + "*** KCONFIG_ALLCONFIG set, but no \"%s\" or \"all.config\" file found\n", + name); + exit(1); + } + break; + default: + break; + } + + if (sync_kconfig) { + name = getenv("KCONFIG_NOSILENTUPDATE"); + if (name && *name) { + if (conf_get_changed()) { + fprintf(stderr, + "\n*** The configuration requires explicit update.\n\n"); + return 1; + } + no_conf_write = 1; + } + } + + switch (input_mode) { + case allnoconfig: + conf_set_all_new_symbols(def_no); + break; + case allyesconfig: + conf_set_all_new_symbols(def_yes); + break; + case allmodconfig: + conf_set_all_new_symbols(def_mod); + break; + case alldefconfig: + conf_set_all_new_symbols(def_default); + break; + case randconfig: + /* Really nothing to do in this loop */ + while (conf_set_all_new_symbols(def_random)) ; + break; + case defconfig: + conf_set_all_new_symbols(def_default); + break; + case savedefconfig: + break; + case yes2modconfig: + conf_rewrite_mod_or_yes(def_y2m); + break; + case mod2yesconfig: + conf_rewrite_mod_or_yes(def_m2y); + break; + case oldaskconfig: + rootEntry = &rootmenu; + conf(&rootmenu); + input_mode = oldconfig; + /* fall through */ + case oldconfig: + case listnewconfig: + case helpnewconfig: + case syncconfig: + /* Update until a loop caused no more changes */ + do { + conf_cnt = 0; + check_conf(&rootmenu); + } while (conf_cnt); + break; + case olddefconfig: + default: + break; + } + + if (input_mode == savedefconfig) { + if (conf_write_defconfig(defconfig_file)) { + fprintf(stderr, "n*** Error while saving defconfig to: %s\n\n", + defconfig_file); + return 1; + } + } else if (input_mode != listnewconfig && input_mode != helpnewconfig) { + if (!no_conf_write && conf_write(NULL)) { + fprintf(stderr, "\n*** Error during writing of the configuration.\n\n"); + exit(1); + } + + /* + * Create auto.conf if it does not exist. + * This prevents GNU Make 4.1 or older from emitting + * "include/config/auto.conf: No such file or directory" + * in the top-level Makefile + * + * syncconfig always creates or updates auto.conf because it is + * used during the build. + */ + if (conf_write_autoconf(sync_kconfig) && sync_kconfig) { + fprintf(stderr, + "\n*** Error during sync of the configuration.\n\n"); + return 1; + } + } + return 0; +} diff --git a/src/net/scripts/kconfig/confdata.c b/src/net/scripts/kconfig/confdata.c new file mode 100644 index 0000000..867b06c --- /dev/null +++ b/src/net/scripts/kconfig/confdata.c @@ -0,0 +1,1343 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2002 Roman Zippel <zippel@linux-m68k.org> + */ + +#include <sys/mman.h> +#include <sys/stat.h> +#include <ctype.h> +#include <errno.h> +#include <fcntl.h> +#include <limits.h> +#include <stdarg.h> +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <time.h> +#include <unistd.h> + +#include "lkc.h" + +/* return true if 'path' exists, false otherwise */ +static bool is_present(const char *path) +{ + struct stat st; + + return !stat(path, &st); +} + +/* return true if 'path' exists and it is a directory, false otherwise */ +static bool is_dir(const char *path) +{ + struct stat st; + + if (stat(path, &st)) + return 0; + + return S_ISDIR(st.st_mode); +} + +/* return true if the given two files are the same, false otherwise */ +static bool is_same(const char *file1, const char *file2) +{ + int fd1, fd2; + struct stat st1, st2; + void *map1, *map2; + bool ret = false; + + fd1 = open(file1, O_RDONLY); + if (fd1 < 0) + return ret; + + fd2 = open(file2, O_RDONLY); + if (fd2 < 0) + goto close1; + + ret = fstat(fd1, &st1); + if (ret) + goto close2; + ret = fstat(fd2, &st2); + if (ret) + goto close2; + + if (st1.st_size != st2.st_size) + goto close2; + + map1 = mmap(NULL, st1.st_size, PROT_READ, MAP_PRIVATE, fd1, 0); + if (map1 == MAP_FAILED) + goto close2; + + map2 = mmap(NULL, st2.st_size, PROT_READ, MAP_PRIVATE, fd2, 0); + if (map2 == MAP_FAILED) + goto close2; + + if (bcmp(map1, map2, st1.st_size)) + goto close2; + + ret = true; +close2: + close(fd2); +close1: + close(fd1); + + return ret; +} + +/* + * Create the parent directory of the given path. + * + * For example, if 'include/config/auto.conf' is given, create 'include/config'. + */ +static int make_parent_dir(const char *path) +{ + char tmp[PATH_MAX + 1]; + char *p; + + strncpy(tmp, path, sizeof(tmp)); + tmp[sizeof(tmp) - 1] = 0; + + /* Remove the base name. Just return if nothing is left */ + p = strrchr(tmp, '/'); + if (!p) + return 0; + *(p + 1) = 0; + + /* Just in case it is an absolute path */ + p = tmp; + while (*p == '/') + p++; + + while ((p = strchr(p, '/'))) { + *p = 0; + + /* skip if the directory exists */ + if (!is_dir(tmp) && mkdir(tmp, 0755)) + return -1; + + *p = '/'; + while (*p == '/') + p++; + } + + return 0; +} + +static char depfile_path[PATH_MAX]; +static size_t depfile_prefix_len; + +/* touch depfile for symbol 'name' */ +static int conf_touch_dep(const char *name) +{ + int fd, ret; + const char *s; + char *d, c; + + /* check overflow: prefix + name + ".h" + '\0' must fit in buffer. */ + if (depfile_prefix_len + strlen(name) + 3 > sizeof(depfile_path)) + return -1; + + d = depfile_path + depfile_prefix_len; + s = name; + + while ((c = *s++)) + *d++ = (c == '_') ? '/' : tolower(c); + strcpy(d, ".h"); + + /* Assume directory path already exists. */ + fd = open(depfile_path, O_WRONLY | O_CREAT | O_TRUNC, 0644); + if (fd == -1) { + if (errno != ENOENT) + return -1; + + ret = make_parent_dir(depfile_path); + if (ret) + return ret; + + /* Try it again. */ + fd = open(depfile_path, O_WRONLY | O_CREAT | O_TRUNC, 0644); + if (fd == -1) + return -1; + } + close(fd); + + return 0; +} + +struct conf_printer { + void (*print_symbol)(FILE *, struct symbol *, const char *, void *); + void (*print_comment)(FILE *, const char *, void *); +}; + +static void conf_warning(const char *fmt, ...) + __attribute__ ((format (printf, 1, 2))); + +static void conf_message(const char *fmt, ...) + __attribute__ ((format (printf, 1, 2))); + +static const char *conf_filename; +static int conf_lineno, conf_warnings; + +static void conf_warning(const char *fmt, ...) +{ + va_list ap; + va_start(ap, fmt); + fprintf(stderr, "%s:%d:warning: ", conf_filename, conf_lineno); + vfprintf(stderr, fmt, ap); + fprintf(stderr, "\n"); + va_end(ap); + conf_warnings++; +} + +static void conf_default_message_callback(const char *s) +{ + printf("#\n# "); + printf("%s", s); + printf("\n#\n"); +} + +static void (*conf_message_callback)(const char *s) = + conf_default_message_callback; +void conf_set_message_callback(void (*fn)(const char *s)) +{ + conf_message_callback = fn; +} + +static void conf_message(const char *fmt, ...) +{ + va_list ap; + char buf[4096]; + + if (!conf_message_callback) + return; + + va_start(ap, fmt); + + vsnprintf(buf, sizeof(buf), fmt, ap); + conf_message_callback(buf); + va_end(ap); +} + +const char *conf_get_configname(void) +{ + char *name = getenv("KCONFIG_CONFIG"); + + return name ? name : ".config"; +} + +static const char *conf_get_autoconfig_name(void) +{ + char *name = getenv("KCONFIG_AUTOCONFIG"); + + return name ? name : "include/config/auto.conf"; +} + +static int conf_set_sym_val(struct symbol *sym, int def, int def_flags, char *p) +{ + char *p2; + + switch (sym->type) { + case S_TRISTATE: + if (p[0] == 'm') { + sym->def[def].tri = mod; + sym->flags |= def_flags; + break; + } + /* fall through */ + case S_BOOLEAN: + if (p[0] == 'y') { + sym->def[def].tri = yes; + sym->flags |= def_flags; + break; + } + if (p[0] == 'n') { + sym->def[def].tri = no; + sym->flags |= def_flags; + break; + } + if (def != S_DEF_AUTO) + conf_warning("symbol value '%s' invalid for %s", + p, sym->name); + return 1; + case S_STRING: + if (*p++ != '"') + break; + for (p2 = p; (p2 = strpbrk(p2, "\"\\")); p2++) { + if (*p2 == '"') { + *p2 = 0; + break; + } + memmove(p2, p2 + 1, strlen(p2)); + } + if (!p2) { + if (def != S_DEF_AUTO) + conf_warning("invalid string found"); + return 1; + } + /* fall through */ + case S_INT: + case S_HEX: + if (sym_string_valid(sym, p)) { + sym->def[def].val = xstrdup(p); + sym->flags |= def_flags; + } else { + if (def != S_DEF_AUTO) + conf_warning("symbol value '%s' invalid for %s", + p, sym->name); + return 1; + } + break; + default: + ; + } + return 0; +} + +#define LINE_GROWTH 16 +static int add_byte(int c, char **lineptr, size_t slen, size_t *n) +{ + char *nline; + size_t new_size = slen + 1; + if (new_size > *n) { + new_size += LINE_GROWTH - 1; + new_size *= 2; + nline = xrealloc(*lineptr, new_size); + if (!nline) + return -1; + + *lineptr = nline; + *n = new_size; + } + + (*lineptr)[slen] = c; + + return 0; +} + +static ssize_t compat_getline(char **lineptr, size_t *n, FILE *stream) +{ + char *line = *lineptr; + size_t slen = 0; + + for (;;) { + int c = getc(stream); + + switch (c) { + case '\n': + if (add_byte(c, &line, slen, n) < 0) + goto e_out; + slen++; + /* fall through */ + case EOF: + if (add_byte('\0', &line, slen, n) < 0) + goto e_out; + *lineptr = line; + if (slen == 0) + return -1; + return slen; + default: + if (add_byte(c, &line, slen, n) < 0) + goto e_out; + slen++; + } + } + +e_out: + line[slen-1] = '\0'; + *lineptr = line; + return -1; +} + +int conf_read_simple(const char *name, int def) +{ + FILE *in = NULL; + char *line = NULL; + size_t line_asize = 0; + char *p, *p2; + struct symbol *sym; + int i, def_flags; + + if (name) { + in = zconf_fopen(name); + } else { + struct property *prop; + + name = conf_get_configname(); + in = zconf_fopen(name); + if (in) + goto load; + sym_add_change_count(1); + if (!sym_defconfig_list) + return 1; + + for_all_defaults(sym_defconfig_list, prop) { + if (expr_calc_value(prop->visible.expr) == no || + prop->expr->type != E_SYMBOL) + continue; + sym_calc_value(prop->expr->left.sym); + name = sym_get_string_value(prop->expr->left.sym); + in = zconf_fopen(name); + if (in) { + conf_message("using defaults found in %s", + name); + goto load; + } + } + } + if (!in) + return 1; + +load: + conf_filename = name; + conf_lineno = 0; + conf_warnings = 0; + + def_flags = SYMBOL_DEF << def; + for_all_symbols(i, sym) { + sym->flags |= SYMBOL_CHANGED; + sym->flags &= ~(def_flags|SYMBOL_VALID); + if (sym_is_choice(sym)) + sym->flags |= def_flags; + switch (sym->type) { + case S_INT: + case S_HEX: + case S_STRING: + if (sym->def[def].val) + free(sym->def[def].val); + /* fall through */ + default: + sym->def[def].val = NULL; + sym->def[def].tri = no; + } + } + + while (compat_getline(&line, &line_asize, in) != -1) { + conf_lineno++; + sym = NULL; + if (line[0] == '#') { + if (memcmp(line + 2, CONFIG_, strlen(CONFIG_))) + continue; + p = strchr(line + 2 + strlen(CONFIG_), ' '); + if (!p) + continue; + *p++ = 0; + if (strncmp(p, "is not set", 10)) + continue; + if (def == S_DEF_USER) { + sym = sym_find(line + 2 + strlen(CONFIG_)); + if (!sym) { + sym_add_change_count(1); + continue; + } + } else { + sym = sym_lookup(line + 2 + strlen(CONFIG_), 0); + if (sym->type == S_UNKNOWN) + sym->type = S_BOOLEAN; + } + if (sym->flags & def_flags) { + conf_warning("override: reassigning to symbol %s", sym->name); + } + switch (sym->type) { + case S_BOOLEAN: + case S_TRISTATE: + sym->def[def].tri = no; + sym->flags |= def_flags; + break; + default: + ; + } + } else if (memcmp(line, CONFIG_, strlen(CONFIG_)) == 0) { + p = strchr(line + strlen(CONFIG_), '='); + if (!p) + continue; + *p++ = 0; + p2 = strchr(p, '\n'); + if (p2) { + *p2-- = 0; + if (*p2 == '\r') + *p2 = 0; + } + + sym = sym_find(line + strlen(CONFIG_)); + if (!sym) { + if (def == S_DEF_AUTO) + /* + * Reading from include/config/auto.conf + * If CONFIG_FOO previously existed in + * auto.conf but it is missing now, + * include/config/foo.h must be touched. + */ + conf_touch_dep(line + strlen(CONFIG_)); + else + sym_add_change_count(1); + continue; + } + + if (sym->flags & def_flags) { + conf_warning("override: reassigning to symbol %s", sym->name); + } + if (conf_set_sym_val(sym, def, def_flags, p)) + continue; + } else { + if (line[0] != '\r' && line[0] != '\n') + conf_warning("unexpected data: %.*s", + (int)strcspn(line, "\r\n"), line); + + continue; + } + + if (sym && sym_is_choice_value(sym)) { + struct symbol *cs = prop_get_symbol(sym_get_choice_prop(sym)); + switch (sym->def[def].tri) { + case no: + break; + case mod: + if (cs->def[def].tri == yes) { + conf_warning("%s creates inconsistent choice state", sym->name); + cs->flags &= ~def_flags; + } + break; + case yes: + if (cs->def[def].tri != no) + conf_warning("override: %s changes choice state", sym->name); + cs->def[def].val = sym; + break; + } + cs->def[def].tri = EXPR_OR(cs->def[def].tri, sym->def[def].tri); + } + } + free(line); + fclose(in); + return 0; +} + +int conf_read(const char *name) +{ + struct symbol *sym; + int conf_unsaved = 0; + int i; + + sym_set_change_count(0); + + if (conf_read_simple(name, S_DEF_USER)) { + sym_calc_value(modules_sym); + return 1; + } + + sym_calc_value(modules_sym); + + for_all_symbols(i, sym) { + sym_calc_value(sym); + if (sym_is_choice(sym) || (sym->flags & SYMBOL_NO_WRITE)) + continue; + if (sym_has_value(sym) && (sym->flags & SYMBOL_WRITE)) { + /* check that calculated value agrees with saved value */ + switch (sym->type) { + case S_BOOLEAN: + case S_TRISTATE: + if (sym->def[S_DEF_USER].tri == sym_get_tristate_value(sym)) + continue; + break; + default: + if (!strcmp(sym->curr.val, sym->def[S_DEF_USER].val)) + continue; + break; + } + } else if (!sym_has_value(sym) && !(sym->flags & SYMBOL_WRITE)) + /* no previous value and not saved */ + continue; + conf_unsaved++; + /* maybe print value in verbose mode... */ + } + + for_all_symbols(i, sym) { + if (sym_has_value(sym) && !sym_is_choice_value(sym)) { + /* Reset values of generates values, so they'll appear + * as new, if they should become visible, but that + * doesn't quite work if the Kconfig and the saved + * configuration disagree. + */ + if (sym->visible == no && !conf_unsaved) + sym->flags &= ~SYMBOL_DEF_USER; + switch (sym->type) { + case S_STRING: + case S_INT: + case S_HEX: + /* Reset a string value if it's out of range */ + if (sym_string_within_range(sym, sym->def[S_DEF_USER].val)) + break; + sym->flags &= ~(SYMBOL_VALID|SYMBOL_DEF_USER); + conf_unsaved++; + break; + default: + break; + } + } + } + + sym_add_change_count(conf_warnings || conf_unsaved); + + return 0; +} + +/* + * Kconfig configuration printer + * + * This printer is used when generating the resulting configuration after + * kconfig invocation and `defconfig' files. Unset symbol might be omitted by + * passing a non-NULL argument to the printer. + * + */ +static void +kconfig_print_symbol(FILE *fp, struct symbol *sym, const char *value, void *arg) +{ + + switch (sym->type) { + case S_BOOLEAN: + case S_TRISTATE: + if (*value == 'n') { + bool skip_unset = (arg != NULL); + + if (!skip_unset) + fprintf(fp, "# %s%s is not set\n", + CONFIG_, sym->name); + return; + } + break; + default: + break; + } + + fprintf(fp, "%s%s=%s\n", CONFIG_, sym->name, value); +} + +static void +kconfig_print_comment(FILE *fp, const char *value, void *arg) +{ + const char *p = value; + size_t l; + + for (;;) { + l = strcspn(p, "\n"); + fprintf(fp, "#"); + if (l) { + fprintf(fp, " "); + xfwrite(p, l, 1, fp); + p += l; + } + fprintf(fp, "\n"); + if (*p++ == '\0') + break; + } +} + +static struct conf_printer kconfig_printer_cb = +{ + .print_symbol = kconfig_print_symbol, + .print_comment = kconfig_print_comment, +}; + +/* + * Header printer + * + * This printer is used when generating the `include/generated/autoconf.h' file. + */ +static void +header_print_symbol(FILE *fp, struct symbol *sym, const char *value, void *arg) +{ + + switch (sym->type) { + case S_BOOLEAN: + case S_TRISTATE: { + const char *suffix = ""; + + switch (*value) { + case 'n': + break; + case 'm': + suffix = "_MODULE"; + /* fall through */ + default: + fprintf(fp, "#define %s%s%s 1\n", + CONFIG_, sym->name, suffix); + } + break; + } + case S_HEX: { + const char *prefix = ""; + + if (value[0] != '0' || (value[1] != 'x' && value[1] != 'X')) + prefix = "0x"; + fprintf(fp, "#define %s%s %s%s\n", + CONFIG_, sym->name, prefix, value); + break; + } + case S_STRING: + case S_INT: + fprintf(fp, "#define %s%s %s\n", + CONFIG_, sym->name, value); + break; + default: + break; + } + +} + +static void +header_print_comment(FILE *fp, const char *value, void *arg) +{ + const char *p = value; + size_t l; + + fprintf(fp, "/*\n"); + for (;;) { + l = strcspn(p, "\n"); + fprintf(fp, " *"); + if (l) { + fprintf(fp, " "); + xfwrite(p, l, 1, fp); + p += l; + } + fprintf(fp, "\n"); + if (*p++ == '\0') + break; + } + fprintf(fp, " */\n"); +} + +static struct conf_printer header_printer_cb = +{ + .print_symbol = header_print_symbol, + .print_comment = header_print_comment, +}; + +static void conf_write_symbol(FILE *fp, struct symbol *sym, + struct conf_printer *printer, void *printer_arg) +{ + const char *str; + + switch (sym->type) { + case S_UNKNOWN: + break; + case S_STRING: + str = sym_get_string_value(sym); + str = sym_escape_string_value(str); + printer->print_symbol(fp, sym, str, printer_arg); + free((void *)str); + break; + default: + str = sym_get_string_value(sym); + printer->print_symbol(fp, sym, str, printer_arg); + } +} + +static void +conf_write_heading(FILE *fp, struct conf_printer *printer, void *printer_arg) +{ + char buf[256]; + + snprintf(buf, sizeof(buf), + "\n" + "Automatically generated file; DO NOT EDIT.\n" + "%s\n", + rootmenu.prompt->text); + + printer->print_comment(fp, buf, printer_arg); +} + +/* + * Write out a minimal config. + * All values that has default values are skipped as this is redundant. + */ +int conf_write_defconfig(const char *filename) +{ + struct symbol *sym; + struct menu *menu; + FILE *out; + + out = fopen(filename, "w"); + if (!out) + return 1; + + sym_clear_all_valid(); + + /* Traverse all menus to find all relevant symbols */ + menu = rootmenu.list; + + while (menu != NULL) + { + sym = menu->sym; + if (sym == NULL) { + if (!menu_is_visible(menu)) + goto next_menu; + } else if (!sym_is_choice(sym)) { + sym_calc_value(sym); + if (!(sym->flags & SYMBOL_WRITE)) + goto next_menu; + sym->flags &= ~SYMBOL_WRITE; + /* If we cannot change the symbol - skip */ + if (!sym_is_changeable(sym)) + goto next_menu; + /* If symbol equals to default value - skip */ + if (strcmp(sym_get_string_value(sym), sym_get_string_default(sym)) == 0) + goto next_menu; + + /* + * If symbol is a choice value and equals to the + * default for a choice - skip. + * But only if value is bool and equal to "y" and + * choice is not "optional". + * (If choice is "optional" then all values can be "n") + */ + if (sym_is_choice_value(sym)) { + struct symbol *cs; + struct symbol *ds; + + cs = prop_get_symbol(sym_get_choice_prop(sym)); + ds = sym_choice_default(cs); + if (!sym_is_optional(cs) && sym == ds) { + if ((sym->type == S_BOOLEAN) && + sym_get_tristate_value(sym) == yes) + goto next_menu; + } + } + conf_write_symbol(out, sym, &kconfig_printer_cb, NULL); + } +next_menu: + if (menu->list != NULL) { + menu = menu->list; + } + else if (menu->next != NULL) { + menu = menu->next; + } else { + while ((menu = menu->parent)) { + if (menu->next != NULL) { + menu = menu->next; + break; + } + } + } + } + fclose(out); + return 0; +} + +int conf_write(const char *name) +{ + FILE *out; + struct symbol *sym; + struct menu *menu; + const char *str; + char tmpname[PATH_MAX + 1], oldname[PATH_MAX + 1]; + char *env; + int i; + bool need_newline = false; + + if (!name) + name = conf_get_configname(); + + if (!*name) { + fprintf(stderr, "config name is empty\n"); + return -1; + } + + if (is_dir(name)) { + fprintf(stderr, "%s: Is a directory\n", name); + return -1; + } + + if (make_parent_dir(name)) + return -1; + + env = getenv("KCONFIG_OVERWRITECONFIG"); + if (env && *env) { + *tmpname = 0; + out = fopen(name, "w"); + } else { + snprintf(tmpname, sizeof(tmpname), "%s.%d.tmp", + name, (int)getpid()); + out = fopen(tmpname, "w"); + } + if (!out) + return 1; + + conf_write_heading(out, &kconfig_printer_cb, NULL); + + if (!conf_get_changed()) + sym_clear_all_valid(); + + menu = rootmenu.list; + while (menu) { + sym = menu->sym; + if (!sym) { + if (!menu_is_visible(menu)) + goto next; + str = menu_get_prompt(menu); + fprintf(out, "\n" + "#\n" + "# %s\n" + "#\n", str); + need_newline = false; + } else if (!(sym->flags & SYMBOL_CHOICE) && + !(sym->flags & SYMBOL_WRITTEN)) { + sym_calc_value(sym); + if (!(sym->flags & SYMBOL_WRITE)) + goto next; + if (need_newline) { + fprintf(out, "\n"); + need_newline = false; + } + sym->flags |= SYMBOL_WRITTEN; + conf_write_symbol(out, sym, &kconfig_printer_cb, NULL); + } + +next: + if (menu->list) { + menu = menu->list; + continue; + } + if (menu->next) + menu = menu->next; + else while ((menu = menu->parent)) { + if (!menu->sym && menu_is_visible(menu) && + menu != &rootmenu) { + str = menu_get_prompt(menu); + fprintf(out, "# end of %s\n", str); + need_newline = true; + } + if (menu->next) { + menu = menu->next; + break; + } + } + } + fclose(out); + + for_all_symbols(i, sym) + sym->flags &= ~SYMBOL_WRITTEN; + + if (*tmpname) { + if (is_same(name, tmpname)) { + conf_message("No change to %s", name); + unlink(tmpname); + sym_set_change_count(0); + return 0; + } + + snprintf(oldname, sizeof(oldname), "%s.old", name); + rename(name, oldname); + if (rename(tmpname, name)) + return 1; + } + + conf_message("configuration written to %s", name); + + sym_set_change_count(0); + + return 0; +} + +/* write a dependency file as used by kbuild to track dependencies */ +static int conf_write_dep(const char *name) +{ + struct file *file; + FILE *out; + + out = fopen("..config.tmp", "w"); + if (!out) + return 1; + fprintf(out, "deps_config := \\\n"); + for (file = file_list; file; file = file->next) { + if (file->next) + fprintf(out, "\t%s \\\n", file->name); + else + fprintf(out, "\t%s\n", file->name); + } + fprintf(out, "\n%s: \\\n" + "\t$(deps_config)\n\n", conf_get_autoconfig_name()); + + env_write_dep(out, conf_get_autoconfig_name()); + + fprintf(out, "\n$(deps_config): ;\n"); + fclose(out); + + if (make_parent_dir(name)) + return 1; + rename("..config.tmp", name); + return 0; +} + +static int conf_touch_deps(void) +{ + const char *name, *tmp; + struct symbol *sym; + int res, i; + + name = conf_get_autoconfig_name(); + tmp = strrchr(name, '/'); + depfile_prefix_len = tmp ? tmp - name + 1 : 0; + if (depfile_prefix_len + 1 > sizeof(depfile_path)) + return -1; + + strncpy(depfile_path, name, depfile_prefix_len); + depfile_path[depfile_prefix_len] = 0; + + conf_read_simple(name, S_DEF_AUTO); + sym_calc_value(modules_sym); + + for_all_symbols(i, sym) { + sym_calc_value(sym); + if ((sym->flags & SYMBOL_NO_WRITE) || !sym->name) + continue; + if (sym->flags & SYMBOL_WRITE) { + if (sym->flags & SYMBOL_DEF_AUTO) { + /* + * symbol has old and new value, + * so compare them... + */ + switch (sym->type) { + case S_BOOLEAN: + case S_TRISTATE: + if (sym_get_tristate_value(sym) == + sym->def[S_DEF_AUTO].tri) + continue; + break; + case S_STRING: + case S_HEX: + case S_INT: + if (!strcmp(sym_get_string_value(sym), + sym->def[S_DEF_AUTO].val)) + continue; + break; + default: + break; + } + } else { + /* + * If there is no old value, only 'no' (unset) + * is allowed as new value. + */ + switch (sym->type) { + case S_BOOLEAN: + case S_TRISTATE: + if (sym_get_tristate_value(sym) == no) + continue; + break; + default: + break; + } + } + } else if (!(sym->flags & SYMBOL_DEF_AUTO)) + /* There is neither an old nor a new value. */ + continue; + /* else + * There is an old value, but no new value ('no' (unset) + * isn't saved in auto.conf, so the old value is always + * different from 'no'). + */ + + res = conf_touch_dep(sym->name); + if (res) + return res; + } + + return 0; +} + +int conf_write_autoconf(int overwrite) +{ + struct symbol *sym; + const char *name; + const char *autoconf_name = conf_get_autoconfig_name(); + FILE *out, *out_h; + int i; + + if (!overwrite && is_present(autoconf_name)) + return 0; + + conf_write_dep("include/config/auto.conf.cmd"); + + if (conf_touch_deps()) + return 1; + + out = fopen(".tmpconfig", "w"); + if (!out) + return 1; + + out_h = fopen(".tmpconfig.h", "w"); + if (!out_h) { + fclose(out); + return 1; + } + + conf_write_heading(out, &kconfig_printer_cb, NULL); + conf_write_heading(out_h, &header_printer_cb, NULL); + + for_all_symbols(i, sym) { + sym_calc_value(sym); + if (!(sym->flags & SYMBOL_WRITE) || !sym->name) + continue; + + /* write symbols to auto.conf and autoconf.h */ + conf_write_symbol(out, sym, &kconfig_printer_cb, (void *)1); + conf_write_symbol(out_h, sym, &header_printer_cb, NULL); + } + fclose(out); + fclose(out_h); + + name = getenv("KCONFIG_AUTOHEADER"); + if (!name) + name = "include/generated/autoconf.h"; + if (make_parent_dir(name)) + return 1; + if (rename(".tmpconfig.h", name)) + return 1; + + if (make_parent_dir(autoconf_name)) + return 1; + /* + * This must be the last step, kbuild has a dependency on auto.conf + * and this marks the successful completion of the previous steps. + */ + if (rename(".tmpconfig", autoconf_name)) + return 1; + + return 0; +} + +static int sym_change_count; +static void (*conf_changed_callback)(void); + +void sym_set_change_count(int count) +{ + int _sym_change_count = sym_change_count; + sym_change_count = count; + if (conf_changed_callback && + (bool)_sym_change_count != (bool)count) + conf_changed_callback(); +} + +void sym_add_change_count(int count) +{ + sym_set_change_count(count + sym_change_count); +} + +bool conf_get_changed(void) +{ + return sym_change_count; +} + +void conf_set_changed_callback(void (*fn)(void)) +{ + conf_changed_callback = fn; +} + +static bool randomize_choice_values(struct symbol *csym) +{ + struct property *prop; + struct symbol *sym; + struct expr *e; + int cnt, def; + + /* + * If choice is mod then we may have more items selected + * and if no then no-one. + * In both cases stop. + */ + if (csym->curr.tri != yes) + return false; + + prop = sym_get_choice_prop(csym); + + /* count entries in choice block */ + cnt = 0; + expr_list_for_each_sym(prop->expr, e, sym) + cnt++; + + /* + * find a random value and set it to yes, + * set the rest to no so we have only one set + */ + def = (rand() % cnt); + + cnt = 0; + expr_list_for_each_sym(prop->expr, e, sym) { + if (def == cnt++) { + sym->def[S_DEF_USER].tri = yes; + csym->def[S_DEF_USER].val = sym; + } + else { + sym->def[S_DEF_USER].tri = no; + } + sym->flags |= SYMBOL_DEF_USER; + /* clear VALID to get value calculated */ + sym->flags &= ~SYMBOL_VALID; + } + csym->flags |= SYMBOL_DEF_USER; + /* clear VALID to get value calculated */ + csym->flags &= ~(SYMBOL_VALID); + + return true; +} + +void set_all_choice_values(struct symbol *csym) +{ + struct property *prop; + struct symbol *sym; + struct expr *e; + + prop = sym_get_choice_prop(csym); + + /* + * Set all non-assinged choice values to no + */ + expr_list_for_each_sym(prop->expr, e, sym) { + if (!sym_has_value(sym)) + sym->def[S_DEF_USER].tri = no; + } + csym->flags |= SYMBOL_DEF_USER; + /* clear VALID to get value calculated */ + csym->flags &= ~(SYMBOL_VALID | SYMBOL_NEED_SET_CHOICE_VALUES); +} + +bool conf_set_all_new_symbols(enum conf_def_mode mode) +{ + struct symbol *sym, *csym; + int i, cnt, pby, pty, ptm; /* pby: probability of bool = y + * pty: probability of tristate = y + * ptm: probability of tristate = m + */ + + pby = 50; pty = ptm = 33; /* can't go as the default in switch-case + * below, otherwise gcc whines about + * -Wmaybe-uninitialized */ + if (mode == def_random) { + int n, p[3]; + char *env = getenv("KCONFIG_PROBABILITY"); + n = 0; + while( env && *env ) { + char *endp; + int tmp = strtol( env, &endp, 10 ); + if( tmp >= 0 && tmp <= 100 ) { + p[n++] = tmp; + } else { + errno = ERANGE; + perror( "KCONFIG_PROBABILITY" ); + exit( 1 ); + } + env = (*endp == ':') ? endp+1 : endp; + if( n >=3 ) { + break; + } + } + switch( n ) { + case 1: + pby = p[0]; ptm = pby/2; pty = pby-ptm; + break; + case 2: + pty = p[0]; ptm = p[1]; pby = pty + ptm; + break; + case 3: + pby = p[0]; pty = p[1]; ptm = p[2]; + break; + } + + if( pty+ptm > 100 ) { + errno = ERANGE; + perror( "KCONFIG_PROBABILITY" ); + exit( 1 ); + } + } + bool has_changed = false; + + for_all_symbols(i, sym) { + if (sym_has_value(sym) || (sym->flags & SYMBOL_VALID)) + continue; + switch (sym_get_type(sym)) { + case S_BOOLEAN: + case S_TRISTATE: + has_changed = true; + switch (mode) { + case def_yes: + sym->def[S_DEF_USER].tri = yes; + break; + case def_mod: + sym->def[S_DEF_USER].tri = mod; + break; + case def_no: + if (sym->flags & SYMBOL_ALLNOCONFIG_Y) + sym->def[S_DEF_USER].tri = yes; + else + sym->def[S_DEF_USER].tri = no; + break; + case def_random: + sym->def[S_DEF_USER].tri = no; + cnt = rand() % 100; + if (sym->type == S_TRISTATE) { + if (cnt < pty) + sym->def[S_DEF_USER].tri = yes; + else if (cnt < (pty+ptm)) + sym->def[S_DEF_USER].tri = mod; + } else if (cnt < pby) + sym->def[S_DEF_USER].tri = yes; + break; + default: + continue; + } + if (!(sym_is_choice(sym) && mode == def_random)) + sym->flags |= SYMBOL_DEF_USER; + break; + default: + break; + } + + } + + sym_clear_all_valid(); + + /* + * We have different type of choice blocks. + * If curr.tri equals to mod then we can select several + * choice symbols in one block. + * In this case we do nothing. + * If curr.tri equals yes then only one symbol can be + * selected in a choice block and we set it to yes, + * and the rest to no. + */ + if (mode != def_random) { + for_all_symbols(i, csym) { + if ((sym_is_choice(csym) && !sym_has_value(csym)) || + sym_is_choice_value(csym)) + csym->flags |= SYMBOL_NEED_SET_CHOICE_VALUES; + } + } + + for_all_symbols(i, csym) { + if (sym_has_value(csym) || !sym_is_choice(csym)) + continue; + + sym_calc_value(csym); + if (mode == def_random) + has_changed |= randomize_choice_values(csym); + else { + set_all_choice_values(csym); + has_changed = true; + } + } + + return has_changed; +} + +void conf_rewrite_mod_or_yes(enum conf_def_mode mode) +{ + struct symbol *sym; + int i; + tristate old_val = (mode == def_y2m) ? yes : mod; + tristate new_val = (mode == def_y2m) ? mod : yes; + + for_all_symbols(i, sym) { + if (sym_get_type(sym) == S_TRISTATE && + sym->def[S_DEF_USER].tri == old_val) + sym->def[S_DEF_USER].tri = new_val; + } + sym_clear_all_valid(); +} diff --git a/src/net/scripts/kconfig/expr.c b/src/net/scripts/kconfig/expr.c new file mode 100644 index 0000000..81ebf81 --- /dev/null +++ b/src/net/scripts/kconfig/expr.c @@ -0,0 +1,1303 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2002 Roman Zippel <zippel@linux-m68k.org> + */ + +#include <ctype.h> +#include <errno.h> +#include <stdio.h> +#include <stdlib.h> +#include <string.h> + +#include "lkc.h" + +#define DEBUG_EXPR 0 + +static struct expr *expr_eliminate_yn(struct expr *e); + +struct expr *expr_alloc_symbol(struct symbol *sym) +{ + struct expr *e = xcalloc(1, sizeof(*e)); + e->type = E_SYMBOL; + e->left.sym = sym; + return e; +} + +struct expr *expr_alloc_one(enum expr_type type, struct expr *ce) +{ + struct expr *e = xcalloc(1, sizeof(*e)); + e->type = type; + e->left.expr = ce; + return e; +} + +struct expr *expr_alloc_two(enum expr_type type, struct expr *e1, struct expr *e2) +{ + struct expr *e = xcalloc(1, sizeof(*e)); + e->type = type; + e->left.expr = e1; + e->right.expr = e2; + return e; +} + +struct expr *expr_alloc_comp(enum expr_type type, struct symbol *s1, struct symbol *s2) +{ + struct expr *e = xcalloc(1, sizeof(*e)); + e->type = type; + e->left.sym = s1; + e->right.sym = s2; + return e; +} + +struct expr *expr_alloc_and(struct expr *e1, struct expr *e2) +{ + if (!e1) + return e2; + return e2 ? expr_alloc_two(E_AND, e1, e2) : e1; +} + +struct expr *expr_alloc_or(struct expr *e1, struct expr *e2) +{ + if (!e1) + return e2; + return e2 ? expr_alloc_two(E_OR, e1, e2) : e1; +} + +struct expr *expr_copy(const struct expr *org) +{ + struct expr *e; + + if (!org) + return NULL; + + e = xmalloc(sizeof(*org)); + memcpy(e, org, sizeof(*org)); + switch (org->type) { + case E_SYMBOL: + e->left = org->left; + break; + case E_NOT: + e->left.expr = expr_copy(org->left.expr); + break; + case E_EQUAL: + case E_GEQ: + case E_GTH: + case E_LEQ: + case E_LTH: + case E_UNEQUAL: + e->left.sym = org->left.sym; + e->right.sym = org->right.sym; + break; + case E_AND: + case E_OR: + case E_LIST: + e->left.expr = expr_copy(org->left.expr); + e->right.expr = expr_copy(org->right.expr); + break; + default: + fprintf(stderr, "can't copy type %d\n", e->type); + free(e); + e = NULL; + break; + } + + return e; +} + +void expr_free(struct expr *e) +{ + if (!e) + return; + + switch (e->type) { + case E_SYMBOL: + break; + case E_NOT: + expr_free(e->left.expr); + break; + case E_EQUAL: + case E_GEQ: + case E_GTH: + case E_LEQ: + case E_LTH: + case E_UNEQUAL: + break; + case E_OR: + case E_AND: + expr_free(e->left.expr); + expr_free(e->right.expr); + break; + default: + fprintf(stderr, "how to free type %d?\n", e->type); + break; + } + free(e); +} + +static int trans_count; + +#define e1 (*ep1) +#define e2 (*ep2) + +/* + * expr_eliminate_eq() helper. + * + * Walks the two expression trees given in 'ep1' and 'ep2'. Any node that does + * not have type 'type' (E_OR/E_AND) is considered a leaf, and is compared + * against all other leaves. Two equal leaves are both replaced with either 'y' + * or 'n' as appropriate for 'type', to be eliminated later. + */ +static void __expr_eliminate_eq(enum expr_type type, struct expr **ep1, struct expr **ep2) +{ + /* Recurse down to leaves */ + + if (e1->type == type) { + __expr_eliminate_eq(type, &e1->left.expr, &e2); + __expr_eliminate_eq(type, &e1->right.expr, &e2); + return; + } + if (e2->type == type) { + __expr_eliminate_eq(type, &e1, &e2->left.expr); + __expr_eliminate_eq(type, &e1, &e2->right.expr); + return; + } + + /* e1 and e2 are leaves. Compare them. */ + + if (e1->type == E_SYMBOL && e2->type == E_SYMBOL && + e1->left.sym == e2->left.sym && + (e1->left.sym == &symbol_yes || e1->left.sym == &symbol_no)) + return; + if (!expr_eq(e1, e2)) + return; + + /* e1 and e2 are equal leaves. Prepare them for elimination. */ + + trans_count++; + expr_free(e1); expr_free(e2); + switch (type) { + case E_OR: + e1 = expr_alloc_symbol(&symbol_no); + e2 = expr_alloc_symbol(&symbol_no); + break; + case E_AND: + e1 = expr_alloc_symbol(&symbol_yes); + e2 = expr_alloc_symbol(&symbol_yes); + break; + default: + ; + } +} + +/* + * Rewrites the expressions 'ep1' and 'ep2' to remove operands common to both. + * Example reductions: + * + * ep1: A && B -> ep1: y + * ep2: A && B && C -> ep2: C + * + * ep1: A || B -> ep1: n + * ep2: A || B || C -> ep2: C + * + * ep1: A && (B && FOO) -> ep1: FOO + * ep2: (BAR && B) && A -> ep2: BAR + * + * ep1: A && (B || C) -> ep1: y + * ep2: (C || B) && A -> ep2: y + * + * Comparisons are done between all operands at the same "level" of && or ||. + * For example, in the expression 'e1 && (e2 || e3) && (e4 || e5)', the + * following operands will be compared: + * + * - 'e1', 'e2 || e3', and 'e4 || e5', against each other + * - e2 against e3 + * - e4 against e5 + * + * Parentheses are irrelevant within a single level. 'e1 && (e2 && e3)' and + * '(e1 && e2) && e3' are both a single level. + * + * See __expr_eliminate_eq() as well. + */ +void expr_eliminate_eq(struct expr **ep1, struct expr **ep2) +{ + if (!e1 || !e2) + return; + switch (e1->type) { + case E_OR: + case E_AND: + __expr_eliminate_eq(e1->type, ep1, ep2); + default: + ; + } + if (e1->type != e2->type) switch (e2->type) { + case E_OR: + case E_AND: + __expr_eliminate_eq(e2->type, ep1, ep2); + default: + ; + } + e1 = expr_eliminate_yn(e1); + e2 = expr_eliminate_yn(e2); +} + +#undef e1 +#undef e2 + +/* + * Returns true if 'e1' and 'e2' are equal, after minor simplification. Two + * &&/|| expressions are considered equal if every operand in one expression + * equals some operand in the other (operands do not need to appear in the same + * order), recursively. + */ +int expr_eq(struct expr *e1, struct expr *e2) +{ + int res, old_count; + + /* + * A NULL expr is taken to be yes, but there's also a different way to + * represent yes. expr_is_yes() checks for either representation. + */ + if (!e1 || !e2) + return expr_is_yes(e1) && expr_is_yes(e2); + + if (e1->type != e2->type) + return 0; + switch (e1->type) { + case E_EQUAL: + case E_GEQ: + case E_GTH: + case E_LEQ: + case E_LTH: + case E_UNEQUAL: + return e1->left.sym == e2->left.sym && e1->right.sym == e2->right.sym; + case E_SYMBOL: + return e1->left.sym == e2->left.sym; + case E_NOT: + return expr_eq(e1->left.expr, e2->left.expr); + case E_AND: + case E_OR: + e1 = expr_copy(e1); + e2 = expr_copy(e2); + old_count = trans_count; + expr_eliminate_eq(&e1, &e2); + res = (e1->type == E_SYMBOL && e2->type == E_SYMBOL && + e1->left.sym == e2->left.sym); + expr_free(e1); + expr_free(e2); + trans_count = old_count; + return res; + case E_LIST: + case E_RANGE: + case E_NONE: + /* panic */; + } + + if (DEBUG_EXPR) { + expr_fprint(e1, stdout); + printf(" = "); + expr_fprint(e2, stdout); + printf(" ?\n"); + } + + return 0; +} + +/* + * Recursively performs the following simplifications in-place (as well as the + * corresponding simplifications with swapped operands): + * + * expr && n -> n + * expr && y -> expr + * expr || n -> expr + * expr || y -> y + * + * Returns the optimized expression. + */ +static struct expr *expr_eliminate_yn(struct expr *e) +{ + struct expr *tmp; + + if (e) switch (e->type) { + case E_AND: + e->left.expr = expr_eliminate_yn(e->left.expr); + e->right.expr = expr_eliminate_yn(e->right.expr); + if (e->left.expr->type == E_SYMBOL) { + if (e->left.expr->left.sym == &symbol_no) { + expr_free(e->left.expr); + expr_free(e->right.expr); + e->type = E_SYMBOL; + e->left.sym = &symbol_no; + e->right.expr = NULL; + return e; + } else if (e->left.expr->left.sym == &symbol_yes) { + free(e->left.expr); + tmp = e->right.expr; + *e = *(e->right.expr); + free(tmp); + return e; + } + } + if (e->right.expr->type == E_SYMBOL) { + if (e->right.expr->left.sym == &symbol_no) { + expr_free(e->left.expr); + expr_free(e->right.expr); + e->type = E_SYMBOL; + e->left.sym = &symbol_no; + e->right.expr = NULL; + return e; + } else if (e->right.expr->left.sym == &symbol_yes) { + free(e->right.expr); + tmp = e->left.expr; + *e = *(e->left.expr); + free(tmp); + return e; + } + } + break; + case E_OR: + e->left.expr = expr_eliminate_yn(e->left.expr); + e->right.expr = expr_eliminate_yn(e->right.expr); + if (e->left.expr->type == E_SYMBOL) { + if (e->left.expr->left.sym == &symbol_no) { + free(e->left.expr); + tmp = e->right.expr; + *e = *(e->right.expr); + free(tmp); + return e; + } else if (e->left.expr->left.sym == &symbol_yes) { + expr_free(e->left.expr); + expr_free(e->right.expr); + e->type = E_SYMBOL; + e->left.sym = &symbol_yes; + e->right.expr = NULL; + return e; + } + } + if (e->right.expr->type == E_SYMBOL) { + if (e->right.expr->left.sym == &symbol_no) { + free(e->right.expr); + tmp = e->left.expr; + *e = *(e->left.expr); + free(tmp); + return e; + } else if (e->right.expr->left.sym == &symbol_yes) { + expr_free(e->left.expr); + expr_free(e->right.expr); + e->type = E_SYMBOL; + e->left.sym = &symbol_yes; + e->right.expr = NULL; + return e; + } + } + break; + default: + ; + } + return e; +} + +/* + * bool FOO!=n => FOO + */ +struct expr *expr_trans_bool(struct expr *e) +{ + if (!e) + return NULL; + switch (e->type) { + case E_AND: + case E_OR: + case E_NOT: + e->left.expr = expr_trans_bool(e->left.expr); + e->right.expr = expr_trans_bool(e->right.expr); + break; + case E_UNEQUAL: + // FOO!=n -> FOO + if (e->left.sym->type == S_TRISTATE) { + if (e->right.sym == &symbol_no) { + e->type = E_SYMBOL; + e->right.sym = NULL; + } + } + break; + default: + ; + } + return e; +} + +/* + * e1 || e2 -> ? + */ +static struct expr *expr_join_or(struct expr *e1, struct expr *e2) +{ + struct expr *tmp; + struct symbol *sym1, *sym2; + + if (expr_eq(e1, e2)) + return expr_copy(e1); + if (e1->type != E_EQUAL && e1->type != E_UNEQUAL && e1->type != E_SYMBOL && e1->type != E_NOT) + return NULL; + if (e2->type != E_EQUAL && e2->type != E_UNEQUAL && e2->type != E_SYMBOL && e2->type != E_NOT) + return NULL; + if (e1->type == E_NOT) { + tmp = e1->left.expr; + if (tmp->type != E_EQUAL && tmp->type != E_UNEQUAL && tmp->type != E_SYMBOL) + return NULL; + sym1 = tmp->left.sym; + } else + sym1 = e1->left.sym; + if (e2->type == E_NOT) { + if (e2->left.expr->type != E_SYMBOL) + return NULL; + sym2 = e2->left.expr->left.sym; + } else + sym2 = e2->left.sym; + if (sym1 != sym2) + return NULL; + if (sym1->type != S_BOOLEAN && sym1->type != S_TRISTATE) + return NULL; + if (sym1->type == S_TRISTATE) { + if (e1->type == E_EQUAL && e2->type == E_EQUAL && + ((e1->right.sym == &symbol_yes && e2->right.sym == &symbol_mod) || + (e1->right.sym == &symbol_mod && e2->right.sym == &symbol_yes))) { + // (a='y') || (a='m') -> (a!='n') + return expr_alloc_comp(E_UNEQUAL, sym1, &symbol_no); + } + if (e1->type == E_EQUAL && e2->type == E_EQUAL && + ((e1->right.sym == &symbol_yes && e2->right.sym == &symbol_no) || + (e1->right.sym == &symbol_no && e2->right.sym == &symbol_yes))) { + // (a='y') || (a='n') -> (a!='m') + return expr_alloc_comp(E_UNEQUAL, sym1, &symbol_mod); + } + if (e1->type == E_EQUAL && e2->type == E_EQUAL && + ((e1->right.sym == &symbol_mod && e2->right.sym == &symbol_no) || + (e1->right.sym == &symbol_no && e2->right.sym == &symbol_mod))) { + // (a='m') || (a='n') -> (a!='y') + return expr_alloc_comp(E_UNEQUAL, sym1, &symbol_yes); + } + } + if (sym1->type == S_BOOLEAN && sym1 == sym2) { + if ((e1->type == E_NOT && e1->left.expr->type == E_SYMBOL && e2->type == E_SYMBOL) || + (e2->type == E_NOT && e2->left.expr->type == E_SYMBOL && e1->type == E_SYMBOL)) + return expr_alloc_symbol(&symbol_yes); + } + + if (DEBUG_EXPR) { + printf("optimize ("); + expr_fprint(e1, stdout); + printf(") || ("); + expr_fprint(e2, stdout); + printf(")?\n"); + } + return NULL; +} + +static struct expr *expr_join_and(struct expr *e1, struct expr *e2) +{ + struct expr *tmp; + struct symbol *sym1, *sym2; + + if (expr_eq(e1, e2)) + return expr_copy(e1); + if (e1->type != E_EQUAL && e1->type != E_UNEQUAL && e1->type != E_SYMBOL && e1->type != E_NOT) + return NULL; + if (e2->type != E_EQUAL && e2->type != E_UNEQUAL && e2->type != E_SYMBOL && e2->type != E_NOT) + return NULL; + if (e1->type == E_NOT) { + tmp = e1->left.expr; + if (tmp->type != E_EQUAL && tmp->type != E_UNEQUAL && tmp->type != E_SYMBOL) + return NULL; + sym1 = tmp->left.sym; + } else + sym1 = e1->left.sym; + if (e2->type == E_NOT) { + if (e2->left.expr->type != E_SYMBOL) + return NULL; + sym2 = e2->left.expr->left.sym; + } else + sym2 = e2->left.sym; + if (sym1 != sym2) + return NULL; + if (sym1->type != S_BOOLEAN && sym1->type != S_TRISTATE) + return NULL; + + if ((e1->type == E_SYMBOL && e2->type == E_EQUAL && e2->right.sym == &symbol_yes) || + (e2->type == E_SYMBOL && e1->type == E_EQUAL && e1->right.sym == &symbol_yes)) + // (a) && (a='y') -> (a='y') + return expr_alloc_comp(E_EQUAL, sym1, &symbol_yes); + + if ((e1->type == E_SYMBOL && e2->type == E_UNEQUAL && e2->right.sym == &symbol_no) || + (e2->type == E_SYMBOL && e1->type == E_UNEQUAL && e1->right.sym == &symbol_no)) + // (a) && (a!='n') -> (a) + return expr_alloc_symbol(sym1); + + if ((e1->type == E_SYMBOL && e2->type == E_UNEQUAL && e2->right.sym == &symbol_mod) || + (e2->type == E_SYMBOL && e1->type == E_UNEQUAL && e1->right.sym == &symbol_mod)) + // (a) && (a!='m') -> (a='y') + return expr_alloc_comp(E_EQUAL, sym1, &symbol_yes); + + if (sym1->type == S_TRISTATE) { + if (e1->type == E_EQUAL && e2->type == E_UNEQUAL) { + // (a='b') && (a!='c') -> 'b'='c' ? 'n' : a='b' + sym2 = e1->right.sym; + if ((e2->right.sym->flags & SYMBOL_CONST) && (sym2->flags & SYMBOL_CONST)) + return sym2 != e2->right.sym ? expr_alloc_comp(E_EQUAL, sym1, sym2) + : expr_alloc_symbol(&symbol_no); + } + if (e1->type == E_UNEQUAL && e2->type == E_EQUAL) { + // (a='b') && (a!='c') -> 'b'='c' ? 'n' : a='b' + sym2 = e2->right.sym; + if ((e1->right.sym->flags & SYMBOL_CONST) && (sym2->flags & SYMBOL_CONST)) + return sym2 != e1->right.sym ? expr_alloc_comp(E_EQUAL, sym1, sym2) + : expr_alloc_symbol(&symbol_no); + } + if (e1->type == E_UNEQUAL && e2->type == E_UNEQUAL && + ((e1->right.sym == &symbol_yes && e2->right.sym == &symbol_no) || + (e1->right.sym == &symbol_no && e2->right.sym == &symbol_yes))) + // (a!='y') && (a!='n') -> (a='m') + return expr_alloc_comp(E_EQUAL, sym1, &symbol_mod); + + if (e1->type == E_UNEQUAL && e2->type == E_UNEQUAL && + ((e1->right.sym == &symbol_yes && e2->right.sym == &symbol_mod) || + (e1->right.sym == &symbol_mod && e2->right.sym == &symbol_yes))) + // (a!='y') && (a!='m') -> (a='n') + return expr_alloc_comp(E_EQUAL, sym1, &symbol_no); + + if (e1->type == E_UNEQUAL && e2->type == E_UNEQUAL && + ((e1->right.sym == &symbol_mod && e2->right.sym == &symbol_no) || + (e1->right.sym == &symbol_no && e2->right.sym == &symbol_mod))) + // (a!='m') && (a!='n') -> (a='m') + return expr_alloc_comp(E_EQUAL, sym1, &symbol_yes); + + if ((e1->type == E_SYMBOL && e2->type == E_EQUAL && e2->right.sym == &symbol_mod) || + (e2->type == E_SYMBOL && e1->type == E_EQUAL && e1->right.sym == &symbol_mod) || + (e1->type == E_SYMBOL && e2->type == E_UNEQUAL && e2->right.sym == &symbol_yes) || + (e2->type == E_SYMBOL && e1->type == E_UNEQUAL && e1->right.sym == &symbol_yes)) + return NULL; + } + + if (DEBUG_EXPR) { + printf("optimize ("); + expr_fprint(e1, stdout); + printf(") && ("); + expr_fprint(e2, stdout); + printf(")?\n"); + } + return NULL; +} + +/* + * expr_eliminate_dups() helper. + * + * Walks the two expression trees given in 'ep1' and 'ep2'. Any node that does + * not have type 'type' (E_OR/E_AND) is considered a leaf, and is compared + * against all other leaves to look for simplifications. + */ +static void expr_eliminate_dups1(enum expr_type type, struct expr **ep1, struct expr **ep2) +{ +#define e1 (*ep1) +#define e2 (*ep2) + struct expr *tmp; + + /* Recurse down to leaves */ + + if (e1->type == type) { + expr_eliminate_dups1(type, &e1->left.expr, &e2); + expr_eliminate_dups1(type, &e1->right.expr, &e2); + return; + } + if (e2->type == type) { + expr_eliminate_dups1(type, &e1, &e2->left.expr); + expr_eliminate_dups1(type, &e1, &e2->right.expr); + return; + } + + /* e1 and e2 are leaves. Compare and process them. */ + + if (e1 == e2) + return; + + switch (e1->type) { + case E_OR: case E_AND: + expr_eliminate_dups1(e1->type, &e1, &e1); + default: + ; + } + + switch (type) { + case E_OR: + tmp = expr_join_or(e1, e2); + if (tmp) { + expr_free(e1); expr_free(e2); + e1 = expr_alloc_symbol(&symbol_no); + e2 = tmp; + trans_count++; + } + break; + case E_AND: + tmp = expr_join_and(e1, e2); + if (tmp) { + expr_free(e1); expr_free(e2); + e1 = expr_alloc_symbol(&symbol_yes); + e2 = tmp; + trans_count++; + } + break; + default: + ; + } +#undef e1 +#undef e2 +} + +/* + * Rewrites 'e' in-place to remove ("join") duplicate and other redundant + * operands. + * + * Example simplifications: + * + * A || B || A -> A || B + * A && B && A=y -> A=y && B + * + * Returns the deduplicated expression. + */ +struct expr *expr_eliminate_dups(struct expr *e) +{ + int oldcount; + if (!e) + return e; + + oldcount = trans_count; + while (1) { + trans_count = 0; + switch (e->type) { + case E_OR: case E_AND: + expr_eliminate_dups1(e->type, &e, &e); + default: + ; + } + if (!trans_count) + /* No simplifications done in this pass. We're done */ + break; + e = expr_eliminate_yn(e); + } + trans_count = oldcount; + return e; +} + +/* + * Performs various simplifications involving logical operators and + * comparisons. + * + * Allocates and returns a new expression. + */ +struct expr *expr_transform(struct expr *e) +{ + struct expr *tmp; + + if (!e) + return NULL; + switch (e->type) { + case E_EQUAL: + case E_GEQ: + case E_GTH: + case E_LEQ: + case E_LTH: + case E_UNEQUAL: + case E_SYMBOL: + case E_LIST: + break; + default: + e->left.expr = expr_transform(e->left.expr); + e->right.expr = expr_transform(e->right.expr); + } + + switch (e->type) { + case E_EQUAL: + if (e->left.sym->type != S_BOOLEAN) + break; + if (e->right.sym == &symbol_no) { + e->type = E_NOT; + e->left.expr = expr_alloc_symbol(e->left.sym); + e->right.sym = NULL; + break; + } + if (e->right.sym == &symbol_mod) { + printf("boolean symbol %s tested for 'm'? test forced to 'n'\n", e->left.sym->name); + e->type = E_SYMBOL; + e->left.sym = &symbol_no; + e->right.sym = NULL; + break; + } + if (e->right.sym == &symbol_yes) { + e->type = E_SYMBOL; + e->right.sym = NULL; + break; + } + break; + case E_UNEQUAL: + if (e->left.sym->type != S_BOOLEAN) + break; + if (e->right.sym == &symbol_no) { + e->type = E_SYMBOL; + e->right.sym = NULL; + break; + } + if (e->right.sym == &symbol_mod) { + printf("boolean symbol %s tested for 'm'? test forced to 'y'\n", e->left.sym->name); + e->type = E_SYMBOL; + e->left.sym = &symbol_yes; + e->right.sym = NULL; + break; + } + if (e->right.sym == &symbol_yes) { + e->type = E_NOT; + e->left.expr = expr_alloc_symbol(e->left.sym); + e->right.sym = NULL; + break; + } + break; + case E_NOT: + switch (e->left.expr->type) { + case E_NOT: + // !!a -> a + tmp = e->left.expr->left.expr; + free(e->left.expr); + free(e); + e = tmp; + e = expr_transform(e); + break; + case E_EQUAL: + case E_UNEQUAL: + // !a='x' -> a!='x' + tmp = e->left.expr; + free(e); + e = tmp; + e->type = e->type == E_EQUAL ? E_UNEQUAL : E_EQUAL; + break; + case E_LEQ: + case E_GEQ: + // !a<='x' -> a>'x' + tmp = e->left.expr; + free(e); + e = tmp; + e->type = e->type == E_LEQ ? E_GTH : E_LTH; + break; + case E_LTH: + case E_GTH: + // !a<'x' -> a>='x' + tmp = e->left.expr; + free(e); + e = tmp; + e->type = e->type == E_LTH ? E_GEQ : E_LEQ; + break; + case E_OR: + // !(a || b) -> !a && !b + tmp = e->left.expr; + e->type = E_AND; + e->right.expr = expr_alloc_one(E_NOT, tmp->right.expr); + tmp->type = E_NOT; + tmp->right.expr = NULL; + e = expr_transform(e); + break; + case E_AND: + // !(a && b) -> !a || !b + tmp = e->left.expr; + e->type = E_OR; + e->right.expr = expr_alloc_one(E_NOT, tmp->right.expr); + tmp->type = E_NOT; + tmp->right.expr = NULL; + e = expr_transform(e); + break; + case E_SYMBOL: + if (e->left.expr->left.sym == &symbol_yes) { + // !'y' -> 'n' + tmp = e->left.expr; + free(e); + e = tmp; + e->type = E_SYMBOL; + e->left.sym = &symbol_no; + break; + } + if (e->left.expr->left.sym == &symbol_mod) { + // !'m' -> 'm' + tmp = e->left.expr; + free(e); + e = tmp; + e->type = E_SYMBOL; + e->left.sym = &symbol_mod; + break; + } + if (e->left.expr->left.sym == &symbol_no) { + // !'n' -> 'y' + tmp = e->left.expr; + free(e); + e = tmp; + e->type = E_SYMBOL; + e->left.sym = &symbol_yes; + break; + } + break; + default: + ; + } + break; + default: + ; + } + return e; +} + +int expr_contains_symbol(struct expr *dep, struct symbol *sym) +{ + if (!dep) + return 0; + + switch (dep->type) { + case E_AND: + case E_OR: + return expr_contains_symbol(dep->left.expr, sym) || + expr_contains_symbol(dep->right.expr, sym); + case E_SYMBOL: + return dep->left.sym == sym; + case E_EQUAL: + case E_GEQ: + case E_GTH: + case E_LEQ: + case E_LTH: + case E_UNEQUAL: + return dep->left.sym == sym || + dep->right.sym == sym; + case E_NOT: + return expr_contains_symbol(dep->left.expr, sym); + default: + ; + } + return 0; +} + +bool expr_depends_symbol(struct expr *dep, struct symbol *sym) +{ + if (!dep) + return false; + + switch (dep->type) { + case E_AND: + return expr_depends_symbol(dep->left.expr, sym) || + expr_depends_symbol(dep->right.expr, sym); + case E_SYMBOL: + return dep->left.sym == sym; + case E_EQUAL: + if (dep->left.sym == sym) { + if (dep->right.sym == &symbol_yes || dep->right.sym == &symbol_mod) + return true; + } + break; + case E_UNEQUAL: + if (dep->left.sym == sym) { + if (dep->right.sym == &symbol_no) + return true; + } + break; + default: + ; + } + return false; +} + +/* + * Inserts explicit comparisons of type 'type' to symbol 'sym' into the + * expression 'e'. + * + * Examples transformations for type == E_UNEQUAL, sym == &symbol_no: + * + * A -> A!=n + * !A -> A=n + * A && B -> !(A=n || B=n) + * A || B -> !(A=n && B=n) + * A && (B || C) -> !(A=n || (B=n && C=n)) + * + * Allocates and returns a new expression. + */ +struct expr *expr_trans_compare(struct expr *e, enum expr_type type, struct symbol *sym) +{ + struct expr *e1, *e2; + + if (!e) { + e = expr_alloc_symbol(sym); + if (type == E_UNEQUAL) + e = expr_alloc_one(E_NOT, e); + return e; + } + switch (e->type) { + case E_AND: + e1 = expr_trans_compare(e->left.expr, E_EQUAL, sym); + e2 = expr_trans_compare(e->right.expr, E_EQUAL, sym); + if (sym == &symbol_yes) + e = expr_alloc_two(E_AND, e1, e2); + if (sym == &symbol_no) + e = expr_alloc_two(E_OR, e1, e2); + if (type == E_UNEQUAL) + e = expr_alloc_one(E_NOT, e); + return e; + case E_OR: + e1 = expr_trans_compare(e->left.expr, E_EQUAL, sym); + e2 = expr_trans_compare(e->right.expr, E_EQUAL, sym); + if (sym == &symbol_yes) + e = expr_alloc_two(E_OR, e1, e2); + if (sym == &symbol_no) + e = expr_alloc_two(E_AND, e1, e2); + if (type == E_UNEQUAL) + e = expr_alloc_one(E_NOT, e); + return e; + case E_NOT: + return expr_trans_compare(e->left.expr, type == E_EQUAL ? E_UNEQUAL : E_EQUAL, sym); + case E_UNEQUAL: + case E_LTH: + case E_LEQ: + case E_GTH: + case E_GEQ: + case E_EQUAL: + if (type == E_EQUAL) { + if (sym == &symbol_yes) + return expr_copy(e); + if (sym == &symbol_mod) + return expr_alloc_symbol(&symbol_no); + if (sym == &symbol_no) + return expr_alloc_one(E_NOT, expr_copy(e)); + } else { + if (sym == &symbol_yes) + return expr_alloc_one(E_NOT, expr_copy(e)); + if (sym == &symbol_mod) + return expr_alloc_symbol(&symbol_yes); + if (sym == &symbol_no) + return expr_copy(e); + } + break; + case E_SYMBOL: + return expr_alloc_comp(type, e->left.sym, sym); + case E_LIST: + case E_RANGE: + case E_NONE: + /* panic */; + } + return NULL; +} + +enum string_value_kind { + k_string, + k_signed, + k_unsigned, +}; + +union string_value { + unsigned long long u; + signed long long s; +}; + +static enum string_value_kind expr_parse_string(const char *str, + enum symbol_type type, + union string_value *val) +{ + char *tail; + enum string_value_kind kind; + + errno = 0; + switch (type) { + case S_BOOLEAN: + case S_TRISTATE: + val->s = !strcmp(str, "n") ? 0 : + !strcmp(str, "m") ? 1 : + !strcmp(str, "y") ? 2 : -1; + return k_signed; + case S_INT: + val->s = strtoll(str, &tail, 10); + kind = k_signed; + break; + case S_HEX: + val->u = strtoull(str, &tail, 16); + kind = k_unsigned; + break; + default: + val->s = strtoll(str, &tail, 0); + kind = k_signed; + break; + } + return !errno && !*tail && tail > str && isxdigit(tail[-1]) + ? kind : k_string; +} + +tristate expr_calc_value(struct expr *e) +{ + tristate val1, val2; + const char *str1, *str2; + enum string_value_kind k1 = k_string, k2 = k_string; + union string_value lval = {}, rval = {}; + int res; + + if (!e) + return yes; + + switch (e->type) { + case E_SYMBOL: + sym_calc_value(e->left.sym); + return e->left.sym->curr.tri; + case E_AND: + val1 = expr_calc_value(e->left.expr); + val2 = expr_calc_value(e->right.expr); + return EXPR_AND(val1, val2); + case E_OR: + val1 = expr_calc_value(e->left.expr); + val2 = expr_calc_value(e->right.expr); + return EXPR_OR(val1, val2); + case E_NOT: + val1 = expr_calc_value(e->left.expr); + return EXPR_NOT(val1); + case E_EQUAL: + case E_GEQ: + case E_GTH: + case E_LEQ: + case E_LTH: + case E_UNEQUAL: + break; + default: + printf("expr_calc_value: %d?\n", e->type); + return no; + } + + sym_calc_value(e->left.sym); + sym_calc_value(e->right.sym); + str1 = sym_get_string_value(e->left.sym); + str2 = sym_get_string_value(e->right.sym); + + if (e->left.sym->type != S_STRING || e->right.sym->type != S_STRING) { + k1 = expr_parse_string(str1, e->left.sym->type, &lval); + k2 = expr_parse_string(str2, e->right.sym->type, &rval); + } + + if (k1 == k_string || k2 == k_string) + res = strcmp(str1, str2); + else if (k1 == k_unsigned || k2 == k_unsigned) + res = (lval.u > rval.u) - (lval.u < rval.u); + else /* if (k1 == k_signed && k2 == k_signed) */ + res = (lval.s > rval.s) - (lval.s < rval.s); + + switch(e->type) { + case E_EQUAL: + return res ? no : yes; + case E_GEQ: + return res >= 0 ? yes : no; + case E_GTH: + return res > 0 ? yes : no; + case E_LEQ: + return res <= 0 ? yes : no; + case E_LTH: + return res < 0 ? yes : no; + case E_UNEQUAL: + return res ? yes : no; + default: + printf("expr_calc_value: relation %d?\n", e->type); + return no; + } +} + +static int expr_compare_type(enum expr_type t1, enum expr_type t2) +{ + if (t1 == t2) + return 0; + switch (t1) { + case E_LEQ: + case E_LTH: + case E_GEQ: + case E_GTH: + if (t2 == E_EQUAL || t2 == E_UNEQUAL) + return 1; + case E_EQUAL: + case E_UNEQUAL: + if (t2 == E_NOT) + return 1; + case E_NOT: + if (t2 == E_AND) + return 1; + case E_AND: + if (t2 == E_OR) + return 1; + case E_OR: + if (t2 == E_LIST) + return 1; + case E_LIST: + if (t2 == 0) + return 1; + default: + return -1; + } + printf("[%dgt%d?]", t1, t2); + return 0; +} + +void expr_print(struct expr *e, + void (*fn)(void *, struct symbol *, const char *), + void *data, int prevtoken) +{ + if (!e) { + fn(data, NULL, "y"); + return; + } + + if (expr_compare_type(prevtoken, e->type) > 0) + fn(data, NULL, "("); + switch (e->type) { + case E_SYMBOL: + if (e->left.sym->name) + fn(data, e->left.sym, e->left.sym->name); + else + fn(data, NULL, "<choice>"); + break; + case E_NOT: + fn(data, NULL, "!"); + expr_print(e->left.expr, fn, data, E_NOT); + break; + case E_EQUAL: + if (e->left.sym->name) + fn(data, e->left.sym, e->left.sym->name); + else + fn(data, NULL, "<choice>"); + fn(data, NULL, "="); + fn(data, e->right.sym, e->right.sym->name); + break; + case E_LEQ: + case E_LTH: + if (e->left.sym->name) + fn(data, e->left.sym, e->left.sym->name); + else + fn(data, NULL, "<choice>"); + fn(data, NULL, e->type == E_LEQ ? "<=" : "<"); + fn(data, e->right.sym, e->right.sym->name); + break; + case E_GEQ: + case E_GTH: + if (e->left.sym->name) + fn(data, e->left.sym, e->left.sym->name); + else + fn(data, NULL, "<choice>"); + fn(data, NULL, e->type == E_GEQ ? ">=" : ">"); + fn(data, e->right.sym, e->right.sym->name); + break; + case E_UNEQUAL: + if (e->left.sym->name) + fn(data, e->left.sym, e->left.sym->name); + else + fn(data, NULL, "<choice>"); + fn(data, NULL, "!="); + fn(data, e->right.sym, e->right.sym->name); + break; + case E_OR: + expr_print(e->left.expr, fn, data, E_OR); + fn(data, NULL, " || "); + expr_print(e->right.expr, fn, data, E_OR); + break; + case E_AND: + expr_print(e->left.expr, fn, data, E_AND); + fn(data, NULL, " && "); + expr_print(e->right.expr, fn, data, E_AND); + break; + case E_LIST: + fn(data, e->right.sym, e->right.sym->name); + if (e->left.expr) { + fn(data, NULL, " ^ "); + expr_print(e->left.expr, fn, data, E_LIST); + } + break; + case E_RANGE: + fn(data, NULL, "["); + fn(data, e->left.sym, e->left.sym->name); + fn(data, NULL, " "); + fn(data, e->right.sym, e->right.sym->name); + fn(data, NULL, "]"); + break; + default: + { + char buf[32]; + sprintf(buf, "<unknown type %d>", e->type); + fn(data, NULL, buf); + break; + } + } + if (expr_compare_type(prevtoken, e->type) > 0) + fn(data, NULL, ")"); +} + +static void expr_print_file_helper(void *data, struct symbol *sym, const char *str) +{ + xfwrite(str, strlen(str), 1, data); +} + +void expr_fprint(struct expr *e, FILE *out) +{ + expr_print(e, expr_print_file_helper, out, E_NONE); +} + +static void expr_print_gstr_helper(void *data, struct symbol *sym, const char *str) +{ + struct gstr *gs = (struct gstr*)data; + const char *sym_str = NULL; + + if (sym) + sym_str = sym_get_string_value(sym); + + if (gs->max_width) { + unsigned extra_length = strlen(str); + const char *last_cr = strrchr(gs->s, '\n'); + unsigned last_line_length; + + if (sym_str) + extra_length += 4 + strlen(sym_str); + + if (!last_cr) + last_cr = gs->s; + + last_line_length = strlen(gs->s) - (last_cr - gs->s); + + if ((last_line_length + extra_length) > gs->max_width) + str_append(gs, "\\\n"); + } + + str_append(gs, str); + if (sym && sym->type != S_UNKNOWN) + str_printf(gs, " [=%s]", sym_str); +} + +void expr_gstr_print(struct expr *e, struct gstr *gs) +{ + expr_print(e, expr_print_gstr_helper, gs, E_NONE); +} + +/* + * Transform the top level "||" tokens into newlines and prepend each + * line with a minus. This makes expressions much easier to read. + * Suitable for reverse dependency expressions. + */ +static void expr_print_revdep(struct expr *e, + void (*fn)(void *, struct symbol *, const char *), + void *data, tristate pr_type, const char **title) +{ + if (e->type == E_OR) { + expr_print_revdep(e->left.expr, fn, data, pr_type, title); + expr_print_revdep(e->right.expr, fn, data, pr_type, title); + } else if (expr_calc_value(e) == pr_type) { + if (*title) { + fn(data, NULL, *title); + *title = NULL; + } + + fn(data, NULL, " - "); + expr_print(e, fn, data, E_NONE); + fn(data, NULL, "\n"); + } +} + +void expr_gstr_print_revdep(struct expr *e, struct gstr *gs, + tristate pr_type, const char *title) +{ + expr_print_revdep(e, expr_print_gstr_helper, gs, pr_type, &title); +} diff --git a/src/net/scripts/kconfig/expr.h b/src/net/scripts/kconfig/expr.h new file mode 100644 index 0000000..5c34436 --- /dev/null +++ b/src/net/scripts/kconfig/expr.h @@ -0,0 +1,332 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2002 Roman Zippel <zippel@linux-m68k.org> + */ + +#ifndef EXPR_H +#define EXPR_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include <assert.h> +#include <stdio.h> +#include "list.h" +#ifndef __cplusplus +#include <stdbool.h> +#endif + +struct file { + struct file *next; + struct file *parent; + const char *name; + int lineno; +}; + +typedef enum tristate { + no, mod, yes +} tristate; + +enum expr_type { + E_NONE, E_OR, E_AND, E_NOT, + E_EQUAL, E_UNEQUAL, E_LTH, E_LEQ, E_GTH, E_GEQ, + E_LIST, E_SYMBOL, E_RANGE +}; + +union expr_data { + struct expr *expr; + struct symbol *sym; +}; + +struct expr { + enum expr_type type; + union expr_data left, right; +}; + +#define EXPR_OR(dep1, dep2) (((dep1)>(dep2))?(dep1):(dep2)) +#define EXPR_AND(dep1, dep2) (((dep1)<(dep2))?(dep1):(dep2)) +#define EXPR_NOT(dep) (2-(dep)) + +#define expr_list_for_each_sym(l, e, s) \ + for (e = (l); e && (s = e->right.sym); e = e->left.expr) + +struct expr_value { + struct expr *expr; + tristate tri; +}; + +struct symbol_value { + void *val; + tristate tri; +}; + +enum symbol_type { + S_UNKNOWN, S_BOOLEAN, S_TRISTATE, S_INT, S_HEX, S_STRING +}; + +/* enum values are used as index to symbol.def[] */ +enum { + S_DEF_USER, /* main user value */ + S_DEF_AUTO, /* values read from auto.conf */ + S_DEF_DEF3, /* Reserved for UI usage */ + S_DEF_DEF4, /* Reserved for UI usage */ + S_DEF_COUNT +}; + +/* + * Represents a configuration symbol. + * + * Choices are represented as a special kind of symbol and have the + * SYMBOL_CHOICE bit set in 'flags'. + */ +struct symbol { + /* The next symbol in the same bucket in the symbol hash table */ + struct symbol *next; + + /* The name of the symbol, e.g. "FOO" for 'config FOO' */ + char *name; + + /* S_BOOLEAN, S_TRISTATE, ... */ + enum symbol_type type; + + /* + * The calculated value of the symbol. The SYMBOL_VALID bit is set in + * 'flags' when this is up to date. Note that this value might differ + * from the user value set in e.g. a .config file, due to visibility. + */ + struct symbol_value curr; + + /* + * Values for the symbol provided from outside. def[S_DEF_USER] holds + * the .config value. + */ + struct symbol_value def[S_DEF_COUNT]; + + /* + * An upper bound on the tristate value the user can set for the symbol + * if it is a boolean or tristate. Calculated from prompt dependencies, + * which also inherit dependencies from enclosing menus, choices, and + * ifs. If 'n', the user value will be ignored. + * + * Symbols lacking prompts always have visibility 'n'. + */ + tristate visible; + + /* SYMBOL_* flags */ + int flags; + + /* List of properties. See prop_type. */ + struct property *prop; + + /* Dependencies from enclosing menus, choices, and ifs */ + struct expr_value dir_dep; + + /* Reverse dependencies through being selected by other symbols */ + struct expr_value rev_dep; + + /* + * "Weak" reverse dependencies through being implied by other symbols + */ + struct expr_value implied; +}; + +#define for_all_symbols(i, sym) for (i = 0; i < SYMBOL_HASHSIZE; i++) for (sym = symbol_hash[i]; sym; sym = sym->next) + +#define SYMBOL_CONST 0x0001 /* symbol is const */ +#define SYMBOL_CHECK 0x0008 /* used during dependency checking */ +#define SYMBOL_CHOICE 0x0010 /* start of a choice block (null name) */ +#define SYMBOL_CHOICEVAL 0x0020 /* used as a value in a choice block */ +#define SYMBOL_VALID 0x0080 /* set when symbol.curr is calculated */ +#define SYMBOL_OPTIONAL 0x0100 /* choice is optional - values can be 'n' */ +#define SYMBOL_WRITE 0x0200 /* write symbol to file (KCONFIG_CONFIG) */ +#define SYMBOL_CHANGED 0x0400 /* ? */ +#define SYMBOL_WRITTEN 0x0800 /* track info to avoid double-write to .config */ +#define SYMBOL_NO_WRITE 0x1000 /* Symbol for internal use only; it will not be written */ +#define SYMBOL_CHECKED 0x2000 /* used during dependency checking */ +#define SYMBOL_WARNED 0x8000 /* warning has been issued */ + +/* Set when symbol.def[] is used */ +#define SYMBOL_DEF 0x10000 /* First bit of SYMBOL_DEF */ +#define SYMBOL_DEF_USER 0x10000 /* symbol.def[S_DEF_USER] is valid */ +#define SYMBOL_DEF_AUTO 0x20000 /* symbol.def[S_DEF_AUTO] is valid */ +#define SYMBOL_DEF3 0x40000 /* symbol.def[S_DEF_3] is valid */ +#define SYMBOL_DEF4 0x80000 /* symbol.def[S_DEF_4] is valid */ + +/* choice values need to be set before calculating this symbol value */ +#define SYMBOL_NEED_SET_CHOICE_VALUES 0x100000 + +/* Set symbol to y if allnoconfig; used for symbols that hide others */ +#define SYMBOL_ALLNOCONFIG_Y 0x200000 + +#define SYMBOL_MAXLENGTH 256 +#define SYMBOL_HASHSIZE 9973 + +/* A property represent the config options that can be associated + * with a config "symbol". + * Sample: + * config FOO + * default y + * prompt "foo prompt" + * select BAR + * config BAZ + * int "BAZ Value" + * range 1..255 + * + * Please, also check parser.y:print_symbol() when modifying the + * list of property types! + */ +enum prop_type { + P_UNKNOWN, + P_PROMPT, /* prompt "foo prompt" or "BAZ Value" */ + P_COMMENT, /* text associated with a comment */ + P_MENU, /* prompt associated with a menu or menuconfig symbol */ + P_DEFAULT, /* default y */ + P_CHOICE, /* choice value */ + P_SELECT, /* select BAR */ + P_IMPLY, /* imply BAR */ + P_RANGE, /* range 7..100 (for a symbol) */ + P_SYMBOL, /* where a symbol is defined */ +}; + +struct property { + struct property *next; /* next property - null if last */ + enum prop_type type; /* type of property */ + const char *text; /* the prompt value - P_PROMPT, P_MENU, P_COMMENT */ + struct expr_value visible; + struct expr *expr; /* the optional conditional part of the property */ + struct menu *menu; /* the menu the property are associated with + * valid for: P_SELECT, P_RANGE, P_CHOICE, + * P_PROMPT, P_DEFAULT, P_MENU, P_COMMENT */ + struct file *file; /* what file was this property defined */ + int lineno; /* what lineno was this property defined */ +}; + +#define for_all_properties(sym, st, tok) \ + for (st = sym->prop; st; st = st->next) \ + if (st->type == (tok)) +#define for_all_defaults(sym, st) for_all_properties(sym, st, P_DEFAULT) +#define for_all_choices(sym, st) for_all_properties(sym, st, P_CHOICE) +#define for_all_prompts(sym, st) \ + for (st = sym->prop; st; st = st->next) \ + if (st->text) + +/* + * Represents a node in the menu tree, as seen in e.g. menuconfig (though used + * for all front ends). Each symbol, menu, etc. defined in the Kconfig files + * gets a node. A symbol defined in multiple locations gets one node at each + * location. + */ +struct menu { + /* The next menu node at the same level */ + struct menu *next; + + /* The parent menu node, corresponding to e.g. a menu or choice */ + struct menu *parent; + + /* The first child menu node, for e.g. menus and choices */ + struct menu *list; + + /* + * The symbol associated with the menu node. Choices are implemented as + * a special kind of symbol. NULL for menus, comments, and ifs. + */ + struct symbol *sym; + + /* + * The prompt associated with the node. This holds the prompt for a + * symbol as well as the text for a menu or comment, along with the + * type (P_PROMPT, P_MENU, etc.) + */ + struct property *prompt; + + /* + * 'visible if' dependencies. If more than one is given, they will be + * ANDed together. + */ + struct expr *visibility; + + /* + * Ordinary dependencies from e.g. 'depends on' and 'if', ANDed + * together + */ + struct expr *dep; + + /* MENU_* flags */ + unsigned int flags; + + /* Any help text associated with the node */ + char *help; + + /* The location where the menu node appears in the Kconfig files */ + struct file *file; + int lineno; + + /* For use by front ends that need to store auxiliary data */ + void *data; +}; + +/* + * Set on a menu node when the corresponding symbol changes state in some way. + * Can be checked by front ends. + */ +#define MENU_CHANGED 0x0001 + +#define MENU_ROOT 0x0002 + +struct jump_key { + struct list_head entries; + size_t offset; + struct menu *target; + int index; +}; + +#define JUMP_NB 9 + +extern struct file *file_list; +extern struct file *current_file; +struct file *lookup_file(const char *name); + +extern struct symbol symbol_yes, symbol_no, symbol_mod; +extern struct symbol *modules_sym; +extern struct symbol *sym_defconfig_list; +extern int cdebug; +struct expr *expr_alloc_symbol(struct symbol *sym); +struct expr *expr_alloc_one(enum expr_type type, struct expr *ce); +struct expr *expr_alloc_two(enum expr_type type, struct expr *e1, struct expr *e2); +struct expr *expr_alloc_comp(enum expr_type type, struct symbol *s1, struct symbol *s2); +struct expr *expr_alloc_and(struct expr *e1, struct expr *e2); +struct expr *expr_alloc_or(struct expr *e1, struct expr *e2); +struct expr *expr_copy(const struct expr *org); +void expr_free(struct expr *e); +void expr_eliminate_eq(struct expr **ep1, struct expr **ep2); +int expr_eq(struct expr *e1, struct expr *e2); +tristate expr_calc_value(struct expr *e); +struct expr *expr_trans_bool(struct expr *e); +struct expr *expr_eliminate_dups(struct expr *e); +struct expr *expr_transform(struct expr *e); +int expr_contains_symbol(struct expr *dep, struct symbol *sym); +bool expr_depends_symbol(struct expr *dep, struct symbol *sym); +struct expr *expr_trans_compare(struct expr *e, enum expr_type type, struct symbol *sym); + +void expr_fprint(struct expr *e, FILE *out); +struct gstr; /* forward */ +void expr_gstr_print(struct expr *e, struct gstr *gs); +void expr_gstr_print_revdep(struct expr *e, struct gstr *gs, + tristate pr_type, const char *title); + +static inline int expr_is_yes(struct expr *e) +{ + return !e || (e->type == E_SYMBOL && e->left.sym == &symbol_yes); +} + +static inline int expr_is_no(struct expr *e) +{ + return e && (e->type == E_SYMBOL && e->left.sym == &symbol_no); +} + +#ifdef __cplusplus +} +#endif + +#endif /* EXPR_H */ diff --git a/src/net/scripts/kconfig/gconf-cfg.sh b/src/net/scripts/kconfig/gconf-cfg.sh new file mode 100755 index 0000000..480ecd8 --- /dev/null +++ b/src/net/scripts/kconfig/gconf-cfg.sh @@ -0,0 +1,30 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0 + +PKG="gtk+-2.0 gmodule-2.0 libglade-2.0" + +if [ -z "$(command -v pkg-config)" ]; then + echo >&2 "*" + echo >&2 "* 'make gconfig' requires 'pkg-config'. Please install it." + echo >&2 "*" + exit 1 +fi + +if ! pkg-config --exists $PKG; then + echo >&2 "*" + echo >&2 "* Unable to find the GTK+ installation. Please make sure that" + echo >&2 "* the GTK+ 2.0 development package is correctly installed." + echo >&2 "* You need $PKG" + echo >&2 "*" + exit 1 +fi + +if ! pkg-config --atleast-version=2.0.0 gtk+-2.0; then + echo >&2 "*" + echo >&2 "* GTK+ is present but version >= 2.0.0 is required." + echo >&2 "*" + exit 1 +fi + +echo cflags=\"$(pkg-config --cflags $PKG)\" +echo libs=\"$(pkg-config --libs $PKG)\" diff --git a/src/net/scripts/kconfig/gconf.c b/src/net/scripts/kconfig/gconf.c new file mode 100644 index 0000000..5527482 --- /dev/null +++ b/src/net/scripts/kconfig/gconf.c @@ -0,0 +1,1517 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2002-2003 Romain Lievin <roms@tilp.info> + */ + +#ifdef HAVE_CONFIG_H +# include <config.h> +#endif + +#include <stdlib.h> +#include "lkc.h" +#include "images.h" + +#include <glade/glade.h> +#include <gtk/gtk.h> +#include <glib.h> +#include <gdk/gdkkeysyms.h> + +#include <stdio.h> +#include <string.h> +#include <strings.h> +#include <unistd.h> +#include <time.h> + +//#define DEBUG + +enum { + SINGLE_VIEW, SPLIT_VIEW, FULL_VIEW +}; + +enum { + OPT_NORMAL, OPT_ALL, OPT_PROMPT +}; + +static gint view_mode = FULL_VIEW; +static gboolean show_name = TRUE; +static gboolean show_range = TRUE; +static gboolean show_value = TRUE; +static gboolean resizeable = FALSE; +static int opt_mode = OPT_NORMAL; + +GtkWidget *main_wnd = NULL; +GtkWidget *tree1_w = NULL; // left frame +GtkWidget *tree2_w = NULL; // right frame +GtkWidget *text_w = NULL; +GtkWidget *hpaned = NULL; +GtkWidget *vpaned = NULL; +GtkWidget *back_btn = NULL; +GtkWidget *save_btn = NULL; +GtkWidget *save_menu_item = NULL; + +GtkTextTag *tag1, *tag2; +GdkColor color; + +GtkTreeStore *tree1, *tree2, *tree; +GtkTreeModel *model1, *model2; +static GtkTreeIter *parents[256]; +static gint indent; + +static struct menu *current; // current node for SINGLE view +static struct menu *browsed; // browsed node for SPLIT view + +enum { + COL_OPTION, COL_NAME, COL_NO, COL_MOD, COL_YES, COL_VALUE, + COL_MENU, COL_COLOR, COL_EDIT, COL_PIXBUF, + COL_PIXVIS, COL_BTNVIS, COL_BTNACT, COL_BTNINC, COL_BTNRAD, + COL_NUMBER +}; + +static void display_list(void); +static void display_tree(struct menu *menu); +static void display_tree_part(void); +static void update_tree(struct menu *src, GtkTreeIter * dst); +static void set_node(GtkTreeIter * node, struct menu *menu, gchar ** row); +static gchar **fill_row(struct menu *menu); +static void conf_changed(void); + +/* Helping/Debugging Functions */ +#ifdef DEBUG +static const char *dbg_sym_flags(int val) +{ + static char buf[256]; + + bzero(buf, 256); + + if (val & SYMBOL_CONST) + strcat(buf, "const/"); + if (val & SYMBOL_CHECK) + strcat(buf, "check/"); + if (val & SYMBOL_CHOICE) + strcat(buf, "choice/"); + if (val & SYMBOL_CHOICEVAL) + strcat(buf, "choiceval/"); + if (val & SYMBOL_VALID) + strcat(buf, "valid/"); + if (val & SYMBOL_OPTIONAL) + strcat(buf, "optional/"); + if (val & SYMBOL_WRITE) + strcat(buf, "write/"); + if (val & SYMBOL_CHANGED) + strcat(buf, "changed/"); + if (val & SYMBOL_NO_WRITE) + strcat(buf, "no_write/"); + + buf[strlen(buf) - 1] = '\0'; + + return buf; +} +#endif + +static void replace_button_icon(GladeXML *xml, GdkDrawable *window, + GtkStyle *style, gchar *btn_name, gchar **xpm) +{ + GdkPixmap *pixmap; + GdkBitmap *mask; + GtkToolButton *button; + GtkWidget *image; + + pixmap = gdk_pixmap_create_from_xpm_d(window, &mask, + &style->bg[GTK_STATE_NORMAL], + xpm); + + button = GTK_TOOL_BUTTON(glade_xml_get_widget(xml, btn_name)); + image = gtk_image_new_from_pixmap(pixmap, mask); + gtk_widget_show(image); + gtk_tool_button_set_icon_widget(button, image); +} + +/* Main Window Initialization */ +static void init_main_window(const gchar *glade_file) +{ + GladeXML *xml; + GtkWidget *widget; + GtkTextBuffer *txtbuf; + GtkStyle *style; + + xml = glade_xml_new(glade_file, "window1", NULL); + if (!xml) + g_error("GUI loading failed !\n"); + glade_xml_signal_autoconnect(xml); + + main_wnd = glade_xml_get_widget(xml, "window1"); + hpaned = glade_xml_get_widget(xml, "hpaned1"); + vpaned = glade_xml_get_widget(xml, "vpaned1"); + tree1_w = glade_xml_get_widget(xml, "treeview1"); + tree2_w = glade_xml_get_widget(xml, "treeview2"); + text_w = glade_xml_get_widget(xml, "textview3"); + + back_btn = glade_xml_get_widget(xml, "button1"); + gtk_widget_set_sensitive(back_btn, FALSE); + + widget = glade_xml_get_widget(xml, "show_name1"); + gtk_check_menu_item_set_active((GtkCheckMenuItem *) widget, + show_name); + + widget = glade_xml_get_widget(xml, "show_range1"); + gtk_check_menu_item_set_active((GtkCheckMenuItem *) widget, + show_range); + + widget = glade_xml_get_widget(xml, "show_data1"); + gtk_check_menu_item_set_active((GtkCheckMenuItem *) widget, + show_value); + + save_btn = glade_xml_get_widget(xml, "button3"); + save_menu_item = glade_xml_get_widget(xml, "save1"); + conf_set_changed_callback(conf_changed); + + style = gtk_widget_get_style(main_wnd); + widget = glade_xml_get_widget(xml, "toolbar1"); + + replace_button_icon(xml, main_wnd->window, style, + "button4", (gchar **) xpm_single_view); + replace_button_icon(xml, main_wnd->window, style, + "button5", (gchar **) xpm_split_view); + replace_button_icon(xml, main_wnd->window, style, + "button6", (gchar **) xpm_tree_view); + + txtbuf = gtk_text_view_get_buffer(GTK_TEXT_VIEW(text_w)); + tag1 = gtk_text_buffer_create_tag(txtbuf, "mytag1", + "foreground", "red", + "weight", PANGO_WEIGHT_BOLD, + NULL); + tag2 = gtk_text_buffer_create_tag(txtbuf, "mytag2", + /*"style", PANGO_STYLE_OBLIQUE, */ + NULL); + + gtk_window_set_title(GTK_WINDOW(main_wnd), rootmenu.prompt->text); + + gtk_widget_show(main_wnd); +} + +static void init_tree_model(void) +{ + gint i; + + tree = tree2 = gtk_tree_store_new(COL_NUMBER, + G_TYPE_STRING, G_TYPE_STRING, + G_TYPE_STRING, G_TYPE_STRING, + G_TYPE_STRING, G_TYPE_STRING, + G_TYPE_POINTER, GDK_TYPE_COLOR, + G_TYPE_BOOLEAN, GDK_TYPE_PIXBUF, + G_TYPE_BOOLEAN, G_TYPE_BOOLEAN, + G_TYPE_BOOLEAN, G_TYPE_BOOLEAN, + G_TYPE_BOOLEAN); + model2 = GTK_TREE_MODEL(tree2); + + for (parents[0] = NULL, i = 1; i < 256; i++) + parents[i] = (GtkTreeIter *) g_malloc(sizeof(GtkTreeIter)); + + tree1 = gtk_tree_store_new(COL_NUMBER, + G_TYPE_STRING, G_TYPE_STRING, + G_TYPE_STRING, G_TYPE_STRING, + G_TYPE_STRING, G_TYPE_STRING, + G_TYPE_POINTER, GDK_TYPE_COLOR, + G_TYPE_BOOLEAN, GDK_TYPE_PIXBUF, + G_TYPE_BOOLEAN, G_TYPE_BOOLEAN, + G_TYPE_BOOLEAN, G_TYPE_BOOLEAN, + G_TYPE_BOOLEAN); + model1 = GTK_TREE_MODEL(tree1); +} + +static void init_left_tree(void) +{ + GtkTreeView *view = GTK_TREE_VIEW(tree1_w); + GtkCellRenderer *renderer; + GtkTreeSelection *sel; + GtkTreeViewColumn *column; + + gtk_tree_view_set_model(view, model1); + gtk_tree_view_set_headers_visible(view, TRUE); + gtk_tree_view_set_rules_hint(view, TRUE); + + column = gtk_tree_view_column_new(); + gtk_tree_view_append_column(view, column); + gtk_tree_view_column_set_title(column, "Options"); + + renderer = gtk_cell_renderer_toggle_new(); + gtk_tree_view_column_pack_start(GTK_TREE_VIEW_COLUMN(column), + renderer, FALSE); + gtk_tree_view_column_set_attributes(GTK_TREE_VIEW_COLUMN(column), + renderer, + "active", COL_BTNACT, + "inconsistent", COL_BTNINC, + "visible", COL_BTNVIS, + "radio", COL_BTNRAD, NULL); + renderer = gtk_cell_renderer_text_new(); + gtk_tree_view_column_pack_start(GTK_TREE_VIEW_COLUMN(column), + renderer, FALSE); + gtk_tree_view_column_set_attributes(GTK_TREE_VIEW_COLUMN(column), + renderer, + "text", COL_OPTION, + "foreground-gdk", + COL_COLOR, NULL); + + sel = gtk_tree_view_get_selection(view); + gtk_tree_selection_set_mode(sel, GTK_SELECTION_SINGLE); + gtk_widget_realize(tree1_w); +} + +static void renderer_edited(GtkCellRendererText * cell, + const gchar * path_string, + const gchar * new_text, gpointer user_data); + +static void init_right_tree(void) +{ + GtkTreeView *view = GTK_TREE_VIEW(tree2_w); + GtkCellRenderer *renderer; + GtkTreeSelection *sel; + GtkTreeViewColumn *column; + gint i; + + gtk_tree_view_set_model(view, model2); + gtk_tree_view_set_headers_visible(view, TRUE); + gtk_tree_view_set_rules_hint(view, TRUE); + + column = gtk_tree_view_column_new(); + gtk_tree_view_append_column(view, column); + gtk_tree_view_column_set_title(column, "Options"); + + renderer = gtk_cell_renderer_pixbuf_new(); + gtk_tree_view_column_pack_start(GTK_TREE_VIEW_COLUMN(column), + renderer, FALSE); + gtk_tree_view_column_set_attributes(GTK_TREE_VIEW_COLUMN(column), + renderer, + "pixbuf", COL_PIXBUF, + "visible", COL_PIXVIS, NULL); + renderer = gtk_cell_renderer_toggle_new(); + gtk_tree_view_column_pack_start(GTK_TREE_VIEW_COLUMN(column), + renderer, FALSE); + gtk_tree_view_column_set_attributes(GTK_TREE_VIEW_COLUMN(column), + renderer, + "active", COL_BTNACT, + "inconsistent", COL_BTNINC, + "visible", COL_BTNVIS, + "radio", COL_BTNRAD, NULL); + renderer = gtk_cell_renderer_text_new(); + gtk_tree_view_column_pack_start(GTK_TREE_VIEW_COLUMN(column), + renderer, FALSE); + gtk_tree_view_column_set_attributes(GTK_TREE_VIEW_COLUMN(column), + renderer, + "text", COL_OPTION, + "foreground-gdk", + COL_COLOR, NULL); + + renderer = gtk_cell_renderer_text_new(); + gtk_tree_view_insert_column_with_attributes(view, -1, + "Name", renderer, + "text", COL_NAME, + "foreground-gdk", + COL_COLOR, NULL); + renderer = gtk_cell_renderer_text_new(); + gtk_tree_view_insert_column_with_attributes(view, -1, + "N", renderer, + "text", COL_NO, + "foreground-gdk", + COL_COLOR, NULL); + renderer = gtk_cell_renderer_text_new(); + gtk_tree_view_insert_column_with_attributes(view, -1, + "M", renderer, + "text", COL_MOD, + "foreground-gdk", + COL_COLOR, NULL); + renderer = gtk_cell_renderer_text_new(); + gtk_tree_view_insert_column_with_attributes(view, -1, + "Y", renderer, + "text", COL_YES, + "foreground-gdk", + COL_COLOR, NULL); + renderer = gtk_cell_renderer_text_new(); + gtk_tree_view_insert_column_with_attributes(view, -1, + "Value", renderer, + "text", COL_VALUE, + "editable", + COL_EDIT, + "foreground-gdk", + COL_COLOR, NULL); + g_signal_connect(G_OBJECT(renderer), "edited", + G_CALLBACK(renderer_edited), NULL); + + column = gtk_tree_view_get_column(view, COL_NAME); + gtk_tree_view_column_set_visible(column, show_name); + column = gtk_tree_view_get_column(view, COL_NO); + gtk_tree_view_column_set_visible(column, show_range); + column = gtk_tree_view_get_column(view, COL_MOD); + gtk_tree_view_column_set_visible(column, show_range); + column = gtk_tree_view_get_column(view, COL_YES); + gtk_tree_view_column_set_visible(column, show_range); + column = gtk_tree_view_get_column(view, COL_VALUE); + gtk_tree_view_column_set_visible(column, show_value); + + if (resizeable) { + for (i = 0; i < COL_VALUE; i++) { + column = gtk_tree_view_get_column(view, i); + gtk_tree_view_column_set_resizable(column, TRUE); + } + } + + sel = gtk_tree_view_get_selection(view); + gtk_tree_selection_set_mode(sel, GTK_SELECTION_SINGLE); +} + + +/* Utility Functions */ + + +static void text_insert_help(struct menu *menu) +{ + GtkTextBuffer *buffer; + GtkTextIter start, end; + const char *prompt = menu_get_prompt(menu); + struct gstr help = str_new(); + + menu_get_ext_help(menu, &help); + + buffer = gtk_text_view_get_buffer(GTK_TEXT_VIEW(text_w)); + gtk_text_buffer_get_bounds(buffer, &start, &end); + gtk_text_buffer_delete(buffer, &start, &end); + gtk_text_view_set_left_margin(GTK_TEXT_VIEW(text_w), 15); + + gtk_text_buffer_get_end_iter(buffer, &end); + gtk_text_buffer_insert_with_tags(buffer, &end, prompt, -1, tag1, + NULL); + gtk_text_buffer_insert_at_cursor(buffer, "\n\n", 2); + gtk_text_buffer_get_end_iter(buffer, &end); + gtk_text_buffer_insert_with_tags(buffer, &end, str_get(&help), -1, tag2, + NULL); + str_free(&help); +} + + +static void text_insert_msg(const char *title, const char *message) +{ + GtkTextBuffer *buffer; + GtkTextIter start, end; + const char *msg = message; + + buffer = gtk_text_view_get_buffer(GTK_TEXT_VIEW(text_w)); + gtk_text_buffer_get_bounds(buffer, &start, &end); + gtk_text_buffer_delete(buffer, &start, &end); + gtk_text_view_set_left_margin(GTK_TEXT_VIEW(text_w), 15); + + gtk_text_buffer_get_end_iter(buffer, &end); + gtk_text_buffer_insert_with_tags(buffer, &end, title, -1, tag1, + NULL); + gtk_text_buffer_insert_at_cursor(buffer, "\n\n", 2); + gtk_text_buffer_get_end_iter(buffer, &end); + gtk_text_buffer_insert_with_tags(buffer, &end, msg, -1, tag2, + NULL); +} + + +/* Main Windows Callbacks */ + +void on_save_activate(GtkMenuItem * menuitem, gpointer user_data); +gboolean on_window1_delete_event(GtkWidget * widget, GdkEvent * event, + gpointer user_data) +{ + GtkWidget *dialog, *label; + gint result; + + if (!conf_get_changed()) + return FALSE; + + dialog = gtk_dialog_new_with_buttons("Warning !", + GTK_WINDOW(main_wnd), + (GtkDialogFlags) + (GTK_DIALOG_MODAL | + GTK_DIALOG_DESTROY_WITH_PARENT), + GTK_STOCK_OK, + GTK_RESPONSE_YES, + GTK_STOCK_NO, + GTK_RESPONSE_NO, + GTK_STOCK_CANCEL, + GTK_RESPONSE_CANCEL, NULL); + gtk_dialog_set_default_response(GTK_DIALOG(dialog), + GTK_RESPONSE_CANCEL); + + label = gtk_label_new("\nSave configuration ?\n"); + gtk_container_add(GTK_CONTAINER(GTK_DIALOG(dialog)->vbox), label); + gtk_widget_show(label); + + result = gtk_dialog_run(GTK_DIALOG(dialog)); + switch (result) { + case GTK_RESPONSE_YES: + on_save_activate(NULL, NULL); + return FALSE; + case GTK_RESPONSE_NO: + return FALSE; + case GTK_RESPONSE_CANCEL: + case GTK_RESPONSE_DELETE_EVENT: + default: + gtk_widget_destroy(dialog); + return TRUE; + } + + return FALSE; +} + + +void on_window1_destroy(GtkObject * object, gpointer user_data) +{ + gtk_main_quit(); +} + + +void +on_window1_size_request(GtkWidget * widget, + GtkRequisition * requisition, gpointer user_data) +{ + static gint old_h; + gint w, h; + + if (widget->window == NULL) + gtk_window_get_default_size(GTK_WINDOW(main_wnd), &w, &h); + else + gdk_window_get_size(widget->window, &w, &h); + + if (h == old_h) + return; + old_h = h; + + gtk_paned_set_position(GTK_PANED(vpaned), 2 * h / 3); +} + + +/* Menu & Toolbar Callbacks */ + + +static void +load_filename(GtkFileSelection * file_selector, gpointer user_data) +{ + const gchar *fn; + + fn = gtk_file_selection_get_filename(GTK_FILE_SELECTION + (user_data)); + + if (conf_read(fn)) + text_insert_msg("Error", "Unable to load configuration !"); + else + display_tree(&rootmenu); +} + +void on_load1_activate(GtkMenuItem * menuitem, gpointer user_data) +{ + GtkWidget *fs; + + fs = gtk_file_selection_new("Load file..."); + g_signal_connect(GTK_OBJECT(GTK_FILE_SELECTION(fs)->ok_button), + "clicked", + G_CALLBACK(load_filename), (gpointer) fs); + g_signal_connect_swapped(GTK_OBJECT + (GTK_FILE_SELECTION(fs)->ok_button), + "clicked", G_CALLBACK(gtk_widget_destroy), + (gpointer) fs); + g_signal_connect_swapped(GTK_OBJECT + (GTK_FILE_SELECTION(fs)->cancel_button), + "clicked", G_CALLBACK(gtk_widget_destroy), + (gpointer) fs); + gtk_widget_show(fs); +} + + +void on_save_activate(GtkMenuItem * menuitem, gpointer user_data) +{ + if (conf_write(NULL)) + text_insert_msg("Error", "Unable to save configuration !"); + conf_write_autoconf(0); +} + + +static void +store_filename(GtkFileSelection * file_selector, gpointer user_data) +{ + const gchar *fn; + + fn = gtk_file_selection_get_filename(GTK_FILE_SELECTION + (user_data)); + + if (conf_write(fn)) + text_insert_msg("Error", "Unable to save configuration !"); + + gtk_widget_destroy(GTK_WIDGET(user_data)); +} + +void on_save_as1_activate(GtkMenuItem * menuitem, gpointer user_data) +{ + GtkWidget *fs; + + fs = gtk_file_selection_new("Save file as..."); + g_signal_connect(GTK_OBJECT(GTK_FILE_SELECTION(fs)->ok_button), + "clicked", + G_CALLBACK(store_filename), (gpointer) fs); + g_signal_connect_swapped(GTK_OBJECT + (GTK_FILE_SELECTION(fs)->ok_button), + "clicked", G_CALLBACK(gtk_widget_destroy), + (gpointer) fs); + g_signal_connect_swapped(GTK_OBJECT + (GTK_FILE_SELECTION(fs)->cancel_button), + "clicked", G_CALLBACK(gtk_widget_destroy), + (gpointer) fs); + gtk_widget_show(fs); +} + + +void on_quit1_activate(GtkMenuItem * menuitem, gpointer user_data) +{ + if (!on_window1_delete_event(NULL, NULL, NULL)) + gtk_widget_destroy(GTK_WIDGET(main_wnd)); +} + + +void on_show_name1_activate(GtkMenuItem * menuitem, gpointer user_data) +{ + GtkTreeViewColumn *col; + + show_name = GTK_CHECK_MENU_ITEM(menuitem)->active; + col = gtk_tree_view_get_column(GTK_TREE_VIEW(tree2_w), COL_NAME); + if (col) + gtk_tree_view_column_set_visible(col, show_name); +} + + +void on_show_range1_activate(GtkMenuItem * menuitem, gpointer user_data) +{ + GtkTreeViewColumn *col; + + show_range = GTK_CHECK_MENU_ITEM(menuitem)->active; + col = gtk_tree_view_get_column(GTK_TREE_VIEW(tree2_w), COL_NO); + if (col) + gtk_tree_view_column_set_visible(col, show_range); + col = gtk_tree_view_get_column(GTK_TREE_VIEW(tree2_w), COL_MOD); + if (col) + gtk_tree_view_column_set_visible(col, show_range); + col = gtk_tree_view_get_column(GTK_TREE_VIEW(tree2_w), COL_YES); + if (col) + gtk_tree_view_column_set_visible(col, show_range); + +} + + +void on_show_data1_activate(GtkMenuItem * menuitem, gpointer user_data) +{ + GtkTreeViewColumn *col; + + show_value = GTK_CHECK_MENU_ITEM(menuitem)->active; + col = gtk_tree_view_get_column(GTK_TREE_VIEW(tree2_w), COL_VALUE); + if (col) + gtk_tree_view_column_set_visible(col, show_value); +} + + +void +on_set_option_mode1_activate(GtkMenuItem *menuitem, gpointer user_data) +{ + opt_mode = OPT_NORMAL; + gtk_tree_store_clear(tree2); + display_tree(&rootmenu); /* instead of update_tree to speed-up */ +} + + +void +on_set_option_mode2_activate(GtkMenuItem *menuitem, gpointer user_data) +{ + opt_mode = OPT_ALL; + gtk_tree_store_clear(tree2); + display_tree(&rootmenu); /* instead of update_tree to speed-up */ +} + + +void +on_set_option_mode3_activate(GtkMenuItem *menuitem, gpointer user_data) +{ + opt_mode = OPT_PROMPT; + gtk_tree_store_clear(tree2); + display_tree(&rootmenu); /* instead of update_tree to speed-up */ +} + + +void on_introduction1_activate(GtkMenuItem * menuitem, gpointer user_data) +{ + GtkWidget *dialog; + const gchar *intro_text = + "Welcome to gkc, the GTK+ graphical configuration tool\n" + "For each option, a blank box indicates the feature is disabled, a\n" + "check indicates it is enabled, and a dot indicates that it is to\n" + "be compiled as a module. Clicking on the box will cycle through the three states.\n" + "\n" + "If you do not see an option (e.g., a device driver) that you\n" + "believe should be present, try turning on Show All Options\n" + "under the Options menu.\n" + "Although there is no cross reference yet to help you figure out\n" + "what other options must be enabled to support the option you\n" + "are interested in, you can still view the help of a grayed-out\n" + "option.\n" + "\n" + "Toggling Show Debug Info under the Options menu will show \n" + "the dependencies, which you can then match by examining other options."; + + dialog = gtk_message_dialog_new(GTK_WINDOW(main_wnd), + GTK_DIALOG_DESTROY_WITH_PARENT, + GTK_MESSAGE_INFO, + GTK_BUTTONS_CLOSE, "%s", intro_text); + g_signal_connect_swapped(GTK_OBJECT(dialog), "response", + G_CALLBACK(gtk_widget_destroy), + GTK_OBJECT(dialog)); + gtk_widget_show_all(dialog); +} + + +void on_about1_activate(GtkMenuItem * menuitem, gpointer user_data) +{ + GtkWidget *dialog; + const gchar *about_text = + "gkc is copyright (c) 2002 Romain Lievin <roms@lpg.ticalc.org>.\n" + "Based on the source code from Roman Zippel.\n"; + + dialog = gtk_message_dialog_new(GTK_WINDOW(main_wnd), + GTK_DIALOG_DESTROY_WITH_PARENT, + GTK_MESSAGE_INFO, + GTK_BUTTONS_CLOSE, "%s", about_text); + g_signal_connect_swapped(GTK_OBJECT(dialog), "response", + G_CALLBACK(gtk_widget_destroy), + GTK_OBJECT(dialog)); + gtk_widget_show_all(dialog); +} + + +void on_license1_activate(GtkMenuItem * menuitem, gpointer user_data) +{ + GtkWidget *dialog; + const gchar *license_text = + "gkc is released under the terms of the GNU GPL v2.\n" + "For more information, please see the source code or\n" + "visit http://www.fsf.org/licenses/licenses.html\n"; + + dialog = gtk_message_dialog_new(GTK_WINDOW(main_wnd), + GTK_DIALOG_DESTROY_WITH_PARENT, + GTK_MESSAGE_INFO, + GTK_BUTTONS_CLOSE, "%s", license_text); + g_signal_connect_swapped(GTK_OBJECT(dialog), "response", + G_CALLBACK(gtk_widget_destroy), + GTK_OBJECT(dialog)); + gtk_widget_show_all(dialog); +} + + +void on_back_clicked(GtkButton * button, gpointer user_data) +{ + enum prop_type ptype; + + current = current->parent; + ptype = current->prompt ? current->prompt->type : P_UNKNOWN; + if (ptype != P_MENU) + current = current->parent; + display_tree_part(); + + if (current == &rootmenu) + gtk_widget_set_sensitive(back_btn, FALSE); +} + + +void on_load_clicked(GtkButton * button, gpointer user_data) +{ + on_load1_activate(NULL, user_data); +} + + +void on_single_clicked(GtkButton * button, gpointer user_data) +{ + view_mode = SINGLE_VIEW; + gtk_widget_hide(tree1_w); + current = &rootmenu; + display_tree_part(); +} + + +void on_split_clicked(GtkButton * button, gpointer user_data) +{ + gint w, h; + view_mode = SPLIT_VIEW; + gtk_widget_show(tree1_w); + gtk_window_get_default_size(GTK_WINDOW(main_wnd), &w, &h); + gtk_paned_set_position(GTK_PANED(hpaned), w / 2); + if (tree2) + gtk_tree_store_clear(tree2); + display_list(); + + /* Disable back btn, like in full mode. */ + gtk_widget_set_sensitive(back_btn, FALSE); +} + + +void on_full_clicked(GtkButton * button, gpointer user_data) +{ + view_mode = FULL_VIEW; + gtk_widget_hide(tree1_w); + if (tree2) + gtk_tree_store_clear(tree2); + display_tree(&rootmenu); + gtk_widget_set_sensitive(back_btn, FALSE); +} + + +void on_collapse_clicked(GtkButton * button, gpointer user_data) +{ + gtk_tree_view_collapse_all(GTK_TREE_VIEW(tree2_w)); +} + + +void on_expand_clicked(GtkButton * button, gpointer user_data) +{ + gtk_tree_view_expand_all(GTK_TREE_VIEW(tree2_w)); +} + + +/* CTree Callbacks */ + +/* Change hex/int/string value in the cell */ +static void renderer_edited(GtkCellRendererText * cell, + const gchar * path_string, + const gchar * new_text, gpointer user_data) +{ + GtkTreePath *path = gtk_tree_path_new_from_string(path_string); + GtkTreeIter iter; + const char *old_def, *new_def; + struct menu *menu; + struct symbol *sym; + + if (!gtk_tree_model_get_iter(model2, &iter, path)) + return; + + gtk_tree_model_get(model2, &iter, COL_MENU, &menu, -1); + sym = menu->sym; + + gtk_tree_model_get(model2, &iter, COL_VALUE, &old_def, -1); + new_def = new_text; + + sym_set_string_value(sym, new_def); + + update_tree(&rootmenu, NULL); + + gtk_tree_path_free(path); +} + +/* Change the value of a symbol and update the tree */ +static void change_sym_value(struct menu *menu, gint col) +{ + struct symbol *sym = menu->sym; + tristate newval; + + if (!sym) + return; + + if (col == COL_NO) + newval = no; + else if (col == COL_MOD) + newval = mod; + else if (col == COL_YES) + newval = yes; + else + return; + + switch (sym_get_type(sym)) { + case S_BOOLEAN: + case S_TRISTATE: + if (!sym_tristate_within_range(sym, newval)) + newval = yes; + sym_set_tristate_value(sym, newval); + if (view_mode == FULL_VIEW) + update_tree(&rootmenu, NULL); + else if (view_mode == SPLIT_VIEW) { + update_tree(browsed, NULL); + display_list(); + } + else if (view_mode == SINGLE_VIEW) + display_tree_part(); //fixme: keep exp/coll + break; + case S_INT: + case S_HEX: + case S_STRING: + default: + break; + } +} + +static void toggle_sym_value(struct menu *menu) +{ + if (!menu->sym) + return; + + sym_toggle_tristate_value(menu->sym); + if (view_mode == FULL_VIEW) + update_tree(&rootmenu, NULL); + else if (view_mode == SPLIT_VIEW) { + update_tree(browsed, NULL); + display_list(); + } + else if (view_mode == SINGLE_VIEW) + display_tree_part(); //fixme: keep exp/coll +} + +static gint column2index(GtkTreeViewColumn * column) +{ + gint i; + + for (i = 0; i < COL_NUMBER; i++) { + GtkTreeViewColumn *col; + + col = gtk_tree_view_get_column(GTK_TREE_VIEW(tree2_w), i); + if (col == column) + return i; + } + + return -1; +} + + +/* User click: update choice (full) or goes down (single) */ +gboolean +on_treeview2_button_press_event(GtkWidget * widget, + GdkEventButton * event, gpointer user_data) +{ + GtkTreeView *view = GTK_TREE_VIEW(widget); + GtkTreePath *path; + GtkTreeViewColumn *column; + GtkTreeIter iter; + struct menu *menu; + gint col; + +#if GTK_CHECK_VERSION(2,1,4) // bug in ctree with earlier version of GTK + gint tx = (gint) event->x; + gint ty = (gint) event->y; + gint cx, cy; + + gtk_tree_view_get_path_at_pos(view, tx, ty, &path, &column, &cx, + &cy); +#else + gtk_tree_view_get_cursor(view, &path, &column); +#endif + if (path == NULL) + return FALSE; + + if (!gtk_tree_model_get_iter(model2, &iter, path)) + return FALSE; + gtk_tree_model_get(model2, &iter, COL_MENU, &menu, -1); + + col = column2index(column); + if (event->type == GDK_2BUTTON_PRESS) { + enum prop_type ptype; + ptype = menu->prompt ? menu->prompt->type : P_UNKNOWN; + + if (ptype == P_MENU && view_mode != FULL_VIEW && col == COL_OPTION) { + // goes down into menu + current = menu; + display_tree_part(); + gtk_widget_set_sensitive(back_btn, TRUE); + } else if (col == COL_OPTION) { + toggle_sym_value(menu); + gtk_tree_view_expand_row(view, path, TRUE); + } + } else { + if (col == COL_VALUE) { + toggle_sym_value(menu); + gtk_tree_view_expand_row(view, path, TRUE); + } else if (col == COL_NO || col == COL_MOD + || col == COL_YES) { + change_sym_value(menu, col); + gtk_tree_view_expand_row(view, path, TRUE); + } + } + + return FALSE; +} + +/* Key pressed: update choice */ +gboolean +on_treeview2_key_press_event(GtkWidget * widget, + GdkEventKey * event, gpointer user_data) +{ + GtkTreeView *view = GTK_TREE_VIEW(widget); + GtkTreePath *path; + GtkTreeViewColumn *column; + GtkTreeIter iter; + struct menu *menu; + gint col; + + gtk_tree_view_get_cursor(view, &path, &column); + if (path == NULL) + return FALSE; + + if (event->keyval == GDK_space) { + if (gtk_tree_view_row_expanded(view, path)) + gtk_tree_view_collapse_row(view, path); + else + gtk_tree_view_expand_row(view, path, FALSE); + return TRUE; + } + if (event->keyval == GDK_KP_Enter) { + } + if (widget == tree1_w) + return FALSE; + + gtk_tree_model_get_iter(model2, &iter, path); + gtk_tree_model_get(model2, &iter, COL_MENU, &menu, -1); + + if (!strcasecmp(event->string, "n")) + col = COL_NO; + else if (!strcasecmp(event->string, "m")) + col = COL_MOD; + else if (!strcasecmp(event->string, "y")) + col = COL_YES; + else + col = -1; + change_sym_value(menu, col); + + return FALSE; +} + + +/* Row selection changed: update help */ +void +on_treeview2_cursor_changed(GtkTreeView * treeview, gpointer user_data) +{ + GtkTreeSelection *selection; + GtkTreeIter iter; + struct menu *menu; + + selection = gtk_tree_view_get_selection(treeview); + if (gtk_tree_selection_get_selected(selection, &model2, &iter)) { + gtk_tree_model_get(model2, &iter, COL_MENU, &menu, -1); + text_insert_help(menu); + } +} + + +/* User click: display sub-tree in the right frame. */ +gboolean +on_treeview1_button_press_event(GtkWidget * widget, + GdkEventButton * event, gpointer user_data) +{ + GtkTreeView *view = GTK_TREE_VIEW(widget); + GtkTreePath *path; + GtkTreeViewColumn *column; + GtkTreeIter iter; + struct menu *menu; + + gint tx = (gint) event->x; + gint ty = (gint) event->y; + gint cx, cy; + + gtk_tree_view_get_path_at_pos(view, tx, ty, &path, &column, &cx, + &cy); + if (path == NULL) + return FALSE; + + gtk_tree_model_get_iter(model1, &iter, path); + gtk_tree_model_get(model1, &iter, COL_MENU, &menu, -1); + + if (event->type == GDK_2BUTTON_PRESS) { + toggle_sym_value(menu); + current = menu; + display_tree_part(); + } else { + browsed = menu; + display_tree_part(); + } + + gtk_widget_realize(tree2_w); + gtk_tree_view_set_cursor(view, path, NULL, FALSE); + gtk_widget_grab_focus(tree2_w); + + return FALSE; +} + + +/* Fill a row of strings */ +static gchar **fill_row(struct menu *menu) +{ + static gchar *row[COL_NUMBER]; + struct symbol *sym = menu->sym; + const char *def; + int stype; + tristate val; + enum prop_type ptype; + int i; + + for (i = COL_OPTION; i <= COL_COLOR; i++) + g_free(row[i]); + bzero(row, sizeof(row)); + + row[COL_OPTION] = + g_strdup_printf("%s %s", menu_get_prompt(menu), + sym && !sym_has_value(sym) ? "(NEW)" : ""); + + if (opt_mode == OPT_ALL && !menu_is_visible(menu)) + row[COL_COLOR] = g_strdup("DarkGray"); + else if (opt_mode == OPT_PROMPT && + menu_has_prompt(menu) && !menu_is_visible(menu)) + row[COL_COLOR] = g_strdup("DarkGray"); + else + row[COL_COLOR] = g_strdup("Black"); + + ptype = menu->prompt ? menu->prompt->type : P_UNKNOWN; + switch (ptype) { + case P_MENU: + row[COL_PIXBUF] = (gchar *) xpm_menu; + if (view_mode == SINGLE_VIEW) + row[COL_PIXVIS] = GINT_TO_POINTER(TRUE); + row[COL_BTNVIS] = GINT_TO_POINTER(FALSE); + break; + case P_COMMENT: + row[COL_PIXBUF] = (gchar *) xpm_void; + row[COL_PIXVIS] = GINT_TO_POINTER(FALSE); + row[COL_BTNVIS] = GINT_TO_POINTER(FALSE); + break; + default: + row[COL_PIXBUF] = (gchar *) xpm_void; + row[COL_PIXVIS] = GINT_TO_POINTER(FALSE); + row[COL_BTNVIS] = GINT_TO_POINTER(TRUE); + break; + } + + if (!sym) + return row; + row[COL_NAME] = g_strdup(sym->name); + + sym_calc_value(sym); + sym->flags &= ~SYMBOL_CHANGED; + + if (sym_is_choice(sym)) { // parse childs for getting final value + struct menu *child; + struct symbol *def_sym = sym_get_choice_value(sym); + struct menu *def_menu = NULL; + + row[COL_BTNVIS] = GINT_TO_POINTER(FALSE); + + for (child = menu->list; child; child = child->next) { + if (menu_is_visible(child) + && child->sym == def_sym) + def_menu = child; + } + + if (def_menu) + row[COL_VALUE] = + g_strdup(menu_get_prompt(def_menu)); + } + if (sym->flags & SYMBOL_CHOICEVAL) + row[COL_BTNRAD] = GINT_TO_POINTER(TRUE); + + stype = sym_get_type(sym); + switch (stype) { + case S_BOOLEAN: + if (GPOINTER_TO_INT(row[COL_PIXVIS]) == FALSE) + row[COL_BTNVIS] = GINT_TO_POINTER(TRUE); + if (sym_is_choice(sym)) + break; + /* fall through */ + case S_TRISTATE: + val = sym_get_tristate_value(sym); + switch (val) { + case no: + row[COL_NO] = g_strdup("N"); + row[COL_VALUE] = g_strdup("N"); + row[COL_BTNACT] = GINT_TO_POINTER(FALSE); + row[COL_BTNINC] = GINT_TO_POINTER(FALSE); + break; + case mod: + row[COL_MOD] = g_strdup("M"); + row[COL_VALUE] = g_strdup("M"); + row[COL_BTNINC] = GINT_TO_POINTER(TRUE); + break; + case yes: + row[COL_YES] = g_strdup("Y"); + row[COL_VALUE] = g_strdup("Y"); + row[COL_BTNACT] = GINT_TO_POINTER(TRUE); + row[COL_BTNINC] = GINT_TO_POINTER(FALSE); + break; + } + + if (val != no && sym_tristate_within_range(sym, no)) + row[COL_NO] = g_strdup("_"); + if (val != mod && sym_tristate_within_range(sym, mod)) + row[COL_MOD] = g_strdup("_"); + if (val != yes && sym_tristate_within_range(sym, yes)) + row[COL_YES] = g_strdup("_"); + break; + case S_INT: + case S_HEX: + case S_STRING: + def = sym_get_string_value(sym); + row[COL_VALUE] = g_strdup(def); + row[COL_EDIT] = GINT_TO_POINTER(TRUE); + row[COL_BTNVIS] = GINT_TO_POINTER(FALSE); + break; + } + + return row; +} + + +/* Set the node content with a row of strings */ +static void set_node(GtkTreeIter * node, struct menu *menu, gchar ** row) +{ + GdkColor color; + gboolean success; + GdkPixbuf *pix; + + pix = gdk_pixbuf_new_from_xpm_data((const char **) + row[COL_PIXBUF]); + + gdk_color_parse(row[COL_COLOR], &color); + gdk_colormap_alloc_colors(gdk_colormap_get_system(), &color, 1, + FALSE, FALSE, &success); + + gtk_tree_store_set(tree, node, + COL_OPTION, row[COL_OPTION], + COL_NAME, row[COL_NAME], + COL_NO, row[COL_NO], + COL_MOD, row[COL_MOD], + COL_YES, row[COL_YES], + COL_VALUE, row[COL_VALUE], + COL_MENU, (gpointer) menu, + COL_COLOR, &color, + COL_EDIT, GPOINTER_TO_INT(row[COL_EDIT]), + COL_PIXBUF, pix, + COL_PIXVIS, GPOINTER_TO_INT(row[COL_PIXVIS]), + COL_BTNVIS, GPOINTER_TO_INT(row[COL_BTNVIS]), + COL_BTNACT, GPOINTER_TO_INT(row[COL_BTNACT]), + COL_BTNINC, GPOINTER_TO_INT(row[COL_BTNINC]), + COL_BTNRAD, GPOINTER_TO_INT(row[COL_BTNRAD]), + -1); + + g_object_unref(pix); +} + + +/* Add a node to the tree */ +static void place_node(struct menu *menu, char **row) +{ + GtkTreeIter *parent = parents[indent - 1]; + GtkTreeIter *node = parents[indent]; + + gtk_tree_store_append(tree, node, parent); + set_node(node, menu, row); +} + + +/* Find a node in the GTK+ tree */ +static GtkTreeIter found; + +/* + * Find a menu in the GtkTree starting at parent. + */ +static GtkTreeIter *gtktree_iter_find_node(GtkTreeIter *parent, + struct menu *tofind) +{ + GtkTreeIter iter; + GtkTreeIter *child = &iter; + gboolean valid; + GtkTreeIter *ret; + + valid = gtk_tree_model_iter_children(model2, child, parent); + while (valid) { + struct menu *menu; + + gtk_tree_model_get(model2, child, 6, &menu, -1); + + if (menu == tofind) { + memcpy(&found, child, sizeof(GtkTreeIter)); + return &found; + } + + ret = gtktree_iter_find_node(child, tofind); + if (ret) + return ret; + + valid = gtk_tree_model_iter_next(model2, child); + } + + return NULL; +} + + +/* + * Update the tree by adding/removing entries + * Does not change other nodes + */ +static void update_tree(struct menu *src, GtkTreeIter * dst) +{ + struct menu *child1; + GtkTreeIter iter, tmp; + GtkTreeIter *child2 = &iter; + gboolean valid; + GtkTreeIter *sibling; + struct symbol *sym; + struct menu *menu1, *menu2; + + if (src == &rootmenu) + indent = 1; + + valid = gtk_tree_model_iter_children(model2, child2, dst); + for (child1 = src->list; child1; child1 = child1->next) { + + sym = child1->sym; + + reparse: + menu1 = child1; + if (valid) + gtk_tree_model_get(model2, child2, COL_MENU, + &menu2, -1); + else + menu2 = NULL; // force adding of a first child + +#ifdef DEBUG + printf("%*c%s | %s\n", indent, ' ', + menu1 ? menu_get_prompt(menu1) : "nil", + menu2 ? menu_get_prompt(menu2) : "nil"); +#endif + + if ((opt_mode == OPT_NORMAL && !menu_is_visible(child1)) || + (opt_mode == OPT_PROMPT && !menu_has_prompt(child1)) || + (opt_mode == OPT_ALL && !menu_get_prompt(child1))) { + + /* remove node */ + if (gtktree_iter_find_node(dst, menu1) != NULL) { + memcpy(&tmp, child2, sizeof(GtkTreeIter)); + valid = gtk_tree_model_iter_next(model2, + child2); + gtk_tree_store_remove(tree2, &tmp); + if (!valid) + return; /* next parent */ + else + goto reparse; /* next child */ + } else + continue; + } + + if (menu1 != menu2) { + if (gtktree_iter_find_node(dst, menu1) == NULL) { // add node + if (!valid && !menu2) + sibling = NULL; + else + sibling = child2; + gtk_tree_store_insert_before(tree2, + child2, + dst, sibling); + set_node(child2, menu1, fill_row(menu1)); + if (menu2 == NULL) + valid = TRUE; + } else { // remove node + memcpy(&tmp, child2, sizeof(GtkTreeIter)); + valid = gtk_tree_model_iter_next(model2, + child2); + gtk_tree_store_remove(tree2, &tmp); + if (!valid) + return; // next parent + else + goto reparse; // next child + } + } else if (sym && (sym->flags & SYMBOL_CHANGED)) { + set_node(child2, menu1, fill_row(menu1)); + } + + indent++; + update_tree(child1, child2); + indent--; + + valid = gtk_tree_model_iter_next(model2, child2); + } +} + + +/* Display the whole tree (single/split/full view) */ +static void display_tree(struct menu *menu) +{ + struct symbol *sym; + struct property *prop; + struct menu *child; + enum prop_type ptype; + + if (menu == &rootmenu) { + indent = 1; + current = &rootmenu; + } + + for (child = menu->list; child; child = child->next) { + prop = child->prompt; + sym = child->sym; + ptype = prop ? prop->type : P_UNKNOWN; + + if (sym) + sym->flags &= ~SYMBOL_CHANGED; + + if ((view_mode == SPLIT_VIEW) + && !(child->flags & MENU_ROOT) && (tree == tree1)) + continue; + + if ((view_mode == SPLIT_VIEW) && (child->flags & MENU_ROOT) + && (tree == tree2)) + continue; + + if ((opt_mode == OPT_NORMAL && menu_is_visible(child)) || + (opt_mode == OPT_PROMPT && menu_has_prompt(child)) || + (opt_mode == OPT_ALL && menu_get_prompt(child))) + place_node(child, fill_row(child)); +#ifdef DEBUG + printf("%*c%s: ", indent, ' ', menu_get_prompt(child)); + printf("%s", child->flags & MENU_ROOT ? "rootmenu | " : ""); + printf("%s", prop_get_type_name(ptype)); + printf(" | "); + if (sym) { + printf("%s", sym_type_name(sym->type)); + printf(" | "); + printf("%s", dbg_sym_flags(sym->flags)); + printf("\n"); + } else + printf("\n"); +#endif + if ((view_mode != FULL_VIEW) && (ptype == P_MENU) + && (tree == tree2)) + continue; +/* + if (((menu != &rootmenu) && !(menu->flags & MENU_ROOT)) + || (view_mode == FULL_VIEW) + || (view_mode == SPLIT_VIEW))*/ + + /* Change paned position if the view is not in 'split mode' */ + if (view_mode == SINGLE_VIEW || view_mode == FULL_VIEW) { + gtk_paned_set_position(GTK_PANED(hpaned), 0); + } + + if (((view_mode == SINGLE_VIEW) && (menu->flags & MENU_ROOT)) + || (view_mode == FULL_VIEW) + || (view_mode == SPLIT_VIEW)) { + indent++; + display_tree(child); + indent--; + } + } +} + +/* Display a part of the tree starting at current node (single/split view) */ +static void display_tree_part(void) +{ + if (tree2) + gtk_tree_store_clear(tree2); + if (view_mode == SINGLE_VIEW) + display_tree(current); + else if (view_mode == SPLIT_VIEW) + display_tree(browsed); + gtk_tree_view_expand_all(GTK_TREE_VIEW(tree2_w)); +} + +/* Display the list in the left frame (split view) */ +static void display_list(void) +{ + if (tree1) + gtk_tree_store_clear(tree1); + + tree = tree1; + display_tree(&rootmenu); + gtk_tree_view_expand_all(GTK_TREE_VIEW(tree1_w)); + tree = tree2; +} + +static void fixup_rootmenu(struct menu *menu) +{ + struct menu *child; + static int menu_cnt = 0; + + menu->flags |= MENU_ROOT; + for (child = menu->list; child; child = child->next) { + if (child->prompt && child->prompt->type == P_MENU) { + menu_cnt++; + fixup_rootmenu(child); + menu_cnt--; + } else if (!menu_cnt) + fixup_rootmenu(child); + } +} + + +/* Main */ +int main(int ac, char *av[]) +{ + const char *name; + char *env; + gchar *glade_file; + + /* GTK stuffs */ + gtk_set_locale(); + gtk_init(&ac, &av); + glade_init(); + + //add_pixmap_directory (PACKAGE_DATA_DIR "/" PACKAGE "/pixmaps"); + //add_pixmap_directory (PACKAGE_SOURCE_DIR "/pixmaps"); + + /* Determine GUI path */ + env = getenv(SRCTREE); + if (env) + glade_file = g_strconcat(env, "/scripts/kconfig/gconf.glade", NULL); + else if (av[0][0] == '/') + glade_file = g_strconcat(av[0], ".glade", NULL); + else + glade_file = g_strconcat(g_get_current_dir(), "/", av[0], ".glade", NULL); + + /* Conf stuffs */ + if (ac > 1 && av[1][0] == '-') { + switch (av[1][1]) { + case 'a': + //showAll = 1; + break; + case 's': + conf_set_message_callback(NULL); + break; + case 'h': + case '?': + printf("%s [-s] <config>\n", av[0]); + exit(0); + } + name = av[2]; + } else + name = av[1]; + + conf_parse(name); + fixup_rootmenu(&rootmenu); + conf_read(NULL); + + /* Load the interface and connect signals */ + init_main_window(glade_file); + init_tree_model(); + init_left_tree(); + init_right_tree(); + + switch (view_mode) { + case SINGLE_VIEW: + display_tree_part(); + break; + case SPLIT_VIEW: + display_list(); + break; + case FULL_VIEW: + display_tree(&rootmenu); + break; + } + + gtk_main(); + + return 0; +} + +static void conf_changed(void) +{ + bool changed = conf_get_changed(); + gtk_widget_set_sensitive(save_btn, changed); + gtk_widget_set_sensitive(save_menu_item, changed); +} diff --git a/src/net/scripts/kconfig/gconf.glade b/src/net/scripts/kconfig/gconf.glade new file mode 100644 index 0000000..aa483cb --- /dev/null +++ b/src/net/scripts/kconfig/gconf.glade @@ -0,0 +1,661 @@ +<?xml version="1.0" standalone="no"?> <!--*- mode: xml -*--> + +<glade-interface> + +<widget class="GtkWindow" id="window1"> + <property name="visible">True</property> + <property name="title" translatable="yes">Gtk Kernel Configurator</property> + <property name="type">GTK_WINDOW_TOPLEVEL</property> + <property name="window_position">GTK_WIN_POS_NONE</property> + <property name="modal">False</property> + <property name="default_width">640</property> + <property name="default_height">480</property> + <property name="resizable">True</property> + <property name="destroy_with_parent">False</property> + <property name="decorated">True</property> + <property name="skip_taskbar_hint">False</property> + <property name="skip_pager_hint">False</property> + <property name="type_hint">GDK_WINDOW_TYPE_HINT_NORMAL</property> + <property name="gravity">GDK_GRAVITY_NORTH_WEST</property> + <signal name="destroy" handler="on_window1_destroy" object="window1"/> + <signal name="size_request" handler="on_window1_size_request" object="vpaned1" last_modification_time="Fri, 11 Jan 2002 16:17:11 GMT"/> + <signal name="delete_event" handler="on_window1_delete_event" object="window1" last_modification_time="Sun, 09 Mar 2003 19:42:46 GMT"/> + + <child> + <widget class="GtkVBox" id="vbox1"> + <property name="visible">True</property> + <property name="homogeneous">False</property> + <property name="spacing">0</property> + + <child> + <widget class="GtkMenuBar" id="menubar1"> + <property name="visible">True</property> + + <child> + <widget class="GtkMenuItem" id="file1"> + <property name="visible">True</property> + <property name="label" translatable="yes">_File</property> + <property name="use_underline">True</property> + + <child> + <widget class="GtkMenu" id="file1_menu"> + + <child> + <widget class="GtkImageMenuItem" id="load1"> + <property name="visible">True</property> + <property name="tooltip" translatable="yes">Load a config file</property> + <property name="label" translatable="yes">_Load</property> + <property name="use_underline">True</property> + <signal name="activate" handler="on_load1_activate"/> + <accelerator key="L" modifiers="GDK_CONTROL_MASK" signal="activate"/> + + <child internal-child="image"> + <widget class="GtkImage" id="image39"> + <property name="visible">True</property> + <property name="stock">gtk-open</property> + <property name="icon_size">1</property> + <property name="xalign">0.5</property> + <property name="yalign">0.5</property> + <property name="xpad">0</property> + <property name="ypad">0</property> + </widget> + </child> + </widget> + </child> + + <child> + <widget class="GtkImageMenuItem" id="save1"> + <property name="visible">True</property> + <property name="tooltip" translatable="yes">Save the config in .config</property> + <property name="label" translatable="yes">_Save</property> + <property name="use_underline">True</property> + <signal name="activate" handler="on_save_activate"/> + <accelerator key="S" modifiers="GDK_CONTROL_MASK" signal="activate"/> + + <child internal-child="image"> + <widget class="GtkImage" id="image40"> + <property name="visible">True</property> + <property name="stock">gtk-save</property> + <property name="icon_size">1</property> + <property name="xalign">0.5</property> + <property name="yalign">0.5</property> + <property name="xpad">0</property> + <property name="ypad">0</property> + </widget> + </child> + </widget> + </child> + + <child> + <widget class="GtkImageMenuItem" id="save_as1"> + <property name="visible">True</property> + <property name="tooltip" translatable="yes">Save the config in a file</property> + <property name="label" translatable="yes">Save _as</property> + <property name="use_underline">True</property> + <signal name="activate" handler="on_save_as1_activate"/> + + <child internal-child="image"> + <widget class="GtkImage" id="image41"> + <property name="visible">True</property> + <property name="stock">gtk-save-as</property> + <property name="icon_size">1</property> + <property name="xalign">0.5</property> + <property name="yalign">0.5</property> + <property name="xpad">0</property> + <property name="ypad">0</property> + </widget> + </child> + </widget> + </child> + + <child> + <widget class="GtkSeparatorMenuItem" id="separator1"> + <property name="visible">True</property> + </widget> + </child> + + <child> + <widget class="GtkImageMenuItem" id="quit1"> + <property name="visible">True</property> + <property name="label" translatable="yes">_Quit</property> + <property name="use_underline">True</property> + <signal name="activate" handler="on_quit1_activate"/> + <accelerator key="Q" modifiers="GDK_CONTROL_MASK" signal="activate"/> + + <child internal-child="image"> + <widget class="GtkImage" id="image42"> + <property name="visible">True</property> + <property name="stock">gtk-quit</property> + <property name="icon_size">1</property> + <property name="xalign">0.5</property> + <property name="yalign">0.5</property> + <property name="xpad">0</property> + <property name="ypad">0</property> + </widget> + </child> + </widget> + </child> + </widget> + </child> + </widget> + </child> + + <child> + <widget class="GtkMenuItem" id="options1"> + <property name="visible">True</property> + <property name="label" translatable="yes">_Options</property> + <property name="use_underline">True</property> + + <child> + <widget class="GtkMenu" id="options1_menu"> + + <child> + <widget class="GtkCheckMenuItem" id="show_name1"> + <property name="visible">True</property> + <property name="tooltip" translatable="yes">Show name</property> + <property name="label" translatable="yes">Show _name</property> + <property name="use_underline">True</property> + <property name="active">False</property> + <signal name="activate" handler="on_show_name1_activate"/> + </widget> + </child> + + <child> + <widget class="GtkCheckMenuItem" id="show_range1"> + <property name="visible">True</property> + <property name="tooltip" translatable="yes">Show range (Y/M/N)</property> + <property name="label" translatable="yes">Show _range</property> + <property name="use_underline">True</property> + <property name="active">False</property> + <signal name="activate" handler="on_show_range1_activate"/> + </widget> + </child> + + <child> + <widget class="GtkCheckMenuItem" id="show_data1"> + <property name="visible">True</property> + <property name="tooltip" translatable="yes">Show value of the option</property> + <property name="label" translatable="yes">Show _data</property> + <property name="use_underline">True</property> + <property name="active">False</property> + <signal name="activate" handler="on_show_data1_activate"/> + </widget> + </child> + + <child> + <widget class="GtkSeparatorMenuItem" id="separator2"> + <property name="visible">True</property> + </widget> + </child> + + <child> + <widget class="GtkRadioMenuItem" id="set_option_mode1"> + <property name="visible">True</property> + <property name="tooltip" translatable="yes">Show normal options</property> + <property name="label" translatable="yes">Show normal options</property> + <property name="use_underline">True</property> + <property name="active">True</property> + <signal name="activate" handler="on_set_option_mode1_activate"/> + </widget> + </child> + + <child> + <widget class="GtkRadioMenuItem" id="set_option_mode2"> + <property name="visible">True</property> + <property name="tooltip" translatable="yes">Show all options</property> + <property name="label" translatable="yes">Show all _options</property> + <property name="use_underline">True</property> + <property name="active">False</property> + <property name="group">set_option_mode1</property> + <signal name="activate" handler="on_set_option_mode2_activate"/> + </widget> + </child> + + <child> + <widget class="GtkRadioMenuItem" id="set_option_mode3"> + <property name="visible">True</property> + <property name="tooltip" translatable="yes">Show all options with prompts</property> + <property name="label" translatable="yes">Show all prompt options</property> + <property name="use_underline">True</property> + <property name="active">False</property> + <property name="group">set_option_mode1</property> + <signal name="activate" handler="on_set_option_mode3_activate"/> + </widget> + </child> + + </widget> + </child> + </widget> + </child> + + <child> + <widget class="GtkMenuItem" id="help1"> + <property name="visible">True</property> + <property name="label" translatable="yes">_Help</property> + <property name="use_underline">True</property> + + <child> + <widget class="GtkMenu" id="help1_menu"> + + <child> + <widget class="GtkImageMenuItem" id="introduction1"> + <property name="visible">True</property> + <property name="label" translatable="yes">_Introduction</property> + <property name="use_underline">True</property> + <signal name="activate" handler="on_introduction1_activate" last_modification_time="Fri, 15 Nov 2002 20:26:30 GMT"/> + <accelerator key="I" modifiers="GDK_CONTROL_MASK" signal="activate"/> + + <child internal-child="image"> + <widget class="GtkImage" id="image43"> + <property name="visible">True</property> + <property name="stock">gtk-dialog-question</property> + <property name="icon_size">1</property> + <property name="xalign">0.5</property> + <property name="yalign">0.5</property> + <property name="xpad">0</property> + <property name="ypad">0</property> + </widget> + </child> + </widget> + </child> + + <child> + <widget class="GtkImageMenuItem" id="about1"> + <property name="visible">True</property> + <property name="label" translatable="yes">_About</property> + <property name="use_underline">True</property> + <signal name="activate" handler="on_about1_activate" last_modification_time="Fri, 15 Nov 2002 20:26:30 GMT"/> + <accelerator key="A" modifiers="GDK_CONTROL_MASK" signal="activate"/> + + <child internal-child="image"> + <widget class="GtkImage" id="image44"> + <property name="visible">True</property> + <property name="stock">gtk-properties</property> + <property name="icon_size">1</property> + <property name="xalign">0.5</property> + <property name="yalign">0.5</property> + <property name="xpad">0</property> + <property name="ypad">0</property> + </widget> + </child> + </widget> + </child> + + <child> + <widget class="GtkImageMenuItem" id="license1"> + <property name="visible">True</property> + <property name="label" translatable="yes">_License</property> + <property name="use_underline">True</property> + <signal name="activate" handler="on_license1_activate" last_modification_time="Fri, 15 Nov 2002 20:26:30 GMT"/> + + <child internal-child="image"> + <widget class="GtkImage" id="image45"> + <property name="visible">True</property> + <property name="stock">gtk-justify-fill</property> + <property name="icon_size">1</property> + <property name="xalign">0.5</property> + <property name="yalign">0.5</property> + <property name="xpad">0</property> + <property name="ypad">0</property> + </widget> + </child> + </widget> + </child> + </widget> + </child> + </widget> + </child> + </widget> + <packing> + <property name="padding">0</property> + <property name="expand">False</property> + <property name="fill">False</property> + </packing> + </child> + + <child> + <widget class="GtkHandleBox" id="handlebox1"> + <property name="visible">True</property> + <property name="shadow_type">GTK_SHADOW_OUT</property> + <property name="handle_position">GTK_POS_LEFT</property> + <property name="snap_edge">GTK_POS_TOP</property> + + <child> + <widget class="GtkToolbar" id="toolbar1"> + <property name="visible">True</property> + <property name="orientation">GTK_ORIENTATION_HORIZONTAL</property> + <property name="toolbar_style">GTK_TOOLBAR_BOTH</property> + <property name="tooltips">True</property> + <property name="show_arrow">True</property> + + <child> + <widget class="GtkToolButton" id="button1"> + <property name="visible">True</property> + <property name="tooltip" translatable="yes">Goes up of one level (single view)</property> + <property name="label" translatable="yes">Back</property> + <property name="use_underline">True</property> + <property name="stock_id">gtk-undo</property> + <property name="visible_horizontal">True</property> + <property name="visible_vertical">True</property> + <property name="is_important">False</property> + <signal name="clicked" handler="on_back_clicked"/> + </widget> + <packing> + <property name="expand">False</property> + <property name="homogeneous">True</property> + </packing> + </child> + + <child> + <widget class="GtkToolItem" id="toolitem1"> + <property name="visible">True</property> + <property name="visible_horizontal">True</property> + <property name="visible_vertical">True</property> + <property name="is_important">False</property> + + <child> + <widget class="GtkVSeparator" id="vseparator1"> + <property name="visible">True</property> + </widget> + </child> + </widget> + <packing> + <property name="expand">False</property> + <property name="homogeneous">False</property> + </packing> + </child> + + <child> + <widget class="GtkToolButton" id="button2"> + <property name="visible">True</property> + <property name="tooltip" translatable="yes">Load a config file</property> + <property name="label" translatable="yes">Load</property> + <property name="use_underline">True</property> + <property name="stock_id">gtk-open</property> + <property name="visible_horizontal">True</property> + <property name="visible_vertical">True</property> + <property name="is_important">False</property> + <signal name="clicked" handler="on_load_clicked"/> + </widget> + <packing> + <property name="expand">False</property> + <property name="homogeneous">True</property> + </packing> + </child> + + <child> + <widget class="GtkToolButton" id="button3"> + <property name="visible">True</property> + <property name="tooltip" translatable="yes">Save a config file</property> + <property name="label" translatable="yes">Save</property> + <property name="use_underline">True</property> + <property name="stock_id">gtk-save</property> + <property name="visible_horizontal">True</property> + <property name="visible_vertical">True</property> + <property name="is_important">False</property> + <signal name="clicked" handler="on_save_activate"/> + </widget> + <packing> + <property name="expand">False</property> + <property name="homogeneous">True</property> + </packing> + </child> + + <child> + <widget class="GtkToolItem" id="toolitem2"> + <property name="visible">True</property> + <property name="visible_horizontal">True</property> + <property name="visible_vertical">True</property> + <property name="is_important">False</property> + + <child> + <widget class="GtkVSeparator" id="vseparator2"> + <property name="visible">True</property> + </widget> + </child> + </widget> + <packing> + <property name="expand">False</property> + <property name="homogeneous">False</property> + </packing> + </child> + + <child> + <widget class="GtkToolButton" id="button4"> + <property name="visible">True</property> + <property name="tooltip" translatable="yes">Single view</property> + <property name="label" translatable="yes">Single</property> + <property name="use_underline">True</property> + <property name="stock_id">gtk-missing-image</property> + <property name="visible_horizontal">True</property> + <property name="visible_vertical">True</property> + <property name="is_important">False</property> + <signal name="clicked" handler="on_single_clicked" last_modification_time="Sun, 12 Jan 2003 14:28:39 GMT"/> + </widget> + <packing> + <property name="expand">False</property> + <property name="homogeneous">True</property> + </packing> + </child> + + <child> + <widget class="GtkToolButton" id="button5"> + <property name="visible">True</property> + <property name="tooltip" translatable="yes">Split view</property> + <property name="label" translatable="yes">Split</property> + <property name="use_underline">True</property> + <property name="stock_id">gtk-missing-image</property> + <property name="visible_horizontal">True</property> + <property name="visible_vertical">True</property> + <property name="is_important">False</property> + <signal name="clicked" handler="on_split_clicked" last_modification_time="Sun, 12 Jan 2003 14:28:45 GMT"/> + </widget> + <packing> + <property name="expand">False</property> + <property name="homogeneous">True</property> + </packing> + </child> + + <child> + <widget class="GtkToolButton" id="button6"> + <property name="visible">True</property> + <property name="tooltip" translatable="yes">Full view</property> + <property name="label" translatable="yes">Full</property> + <property name="use_underline">True</property> + <property name="stock_id">gtk-missing-image</property> + <property name="visible_horizontal">True</property> + <property name="visible_vertical">True</property> + <property name="is_important">False</property> + <signal name="clicked" handler="on_full_clicked" last_modification_time="Sun, 12 Jan 2003 14:28:50 GMT"/> + </widget> + <packing> + <property name="expand">False</property> + <property name="homogeneous">True</property> + </packing> + </child> + + <child> + <widget class="GtkToolItem" id="toolitem3"> + <property name="visible">True</property> + <property name="visible_horizontal">True</property> + <property name="visible_vertical">True</property> + <property name="is_important">False</property> + + <child> + <widget class="GtkVSeparator" id="vseparator3"> + <property name="visible">True</property> + </widget> + </child> + </widget> + <packing> + <property name="expand">False</property> + <property name="homogeneous">False</property> + </packing> + </child> + + <child> + <widget class="GtkToolButton" id="button7"> + <property name="visible">True</property> + <property name="tooltip" translatable="yes">Collapse the whole tree in the right frame</property> + <property name="label" translatable="yes">Collapse</property> + <property name="use_underline">True</property> + <property name="stock_id">gtk-remove</property> + <property name="visible_horizontal">True</property> + <property name="visible_vertical">True</property> + <property name="is_important">False</property> + <signal name="clicked" handler="on_collapse_clicked"/> + </widget> + <packing> + <property name="expand">False</property> + <property name="homogeneous">True</property> + </packing> + </child> + + <child> + <widget class="GtkToolButton" id="button8"> + <property name="visible">True</property> + <property name="tooltip" translatable="yes">Expand the whole tree in the right frame</property> + <property name="label" translatable="yes">Expand</property> + <property name="use_underline">True</property> + <property name="stock_id">gtk-add</property> + <property name="visible_horizontal">True</property> + <property name="visible_vertical">True</property> + <property name="is_important">False</property> + <signal name="clicked" handler="on_expand_clicked"/> + </widget> + <packing> + <property name="expand">False</property> + <property name="homogeneous">True</property> + </packing> + </child> + </widget> + </child> + </widget> + <packing> + <property name="padding">0</property> + <property name="expand">False</property> + <property name="fill">False</property> + </packing> + </child> + + <child> + <widget class="GtkHPaned" id="hpaned1"> + <property name="width_request">1</property> + <property name="visible">True</property> + <property name="can_focus">True</property> + <property name="position">0</property> + + <child> + <widget class="GtkScrolledWindow" id="scrolledwindow1"> + <property name="visible">True</property> + <property name="hscrollbar_policy">GTK_POLICY_AUTOMATIC</property> + <property name="vscrollbar_policy">GTK_POLICY_AUTOMATIC</property> + <property name="shadow_type">GTK_SHADOW_IN</property> + <property name="window_placement">GTK_CORNER_TOP_LEFT</property> + + <child> + <widget class="GtkTreeView" id="treeview1"> + <property name="visible">True</property> + <property name="can_focus">True</property> + <property name="headers_visible">True</property> + <property name="rules_hint">False</property> + <property name="reorderable">False</property> + <property name="enable_search">False</property> + <signal name="cursor_changed" handler="on_treeview2_cursor_changed" last_modification_time="Sun, 12 Jan 2003 15:58:22 GMT"/> + <signal name="button_press_event" handler="on_treeview1_button_press_event" last_modification_time="Sun, 12 Jan 2003 16:03:52 GMT"/> + <signal name="key_press_event" handler="on_treeview2_key_press_event" last_modification_time="Sun, 12 Jan 2003 16:11:44 GMT"/> + </widget> + </child> + </widget> + <packing> + <property name="shrink">True</property> + <property name="resize">False</property> + </packing> + </child> + + <child> + <widget class="GtkVPaned" id="vpaned1"> + <property name="visible">True</property> + <property name="can_focus">True</property> + <property name="position">0</property> + + <child> + <widget class="GtkScrolledWindow" id="scrolledwindow2"> + <property name="visible">True</property> + <property name="hscrollbar_policy">GTK_POLICY_AUTOMATIC</property> + <property name="vscrollbar_policy">GTK_POLICY_AUTOMATIC</property> + <property name="shadow_type">GTK_SHADOW_IN</property> + <property name="window_placement">GTK_CORNER_TOP_LEFT</property> + + <child> + <widget class="GtkTreeView" id="treeview2"> + <property name="visible">True</property> + <property name="can_focus">True</property> + <property name="has_focus">True</property> + <property name="headers_visible">True</property> + <property name="rules_hint">False</property> + <property name="reorderable">False</property> + <property name="enable_search">False</property> + <signal name="cursor_changed" handler="on_treeview2_cursor_changed" last_modification_time="Sun, 12 Jan 2003 15:57:55 GMT"/> + <signal name="button_press_event" handler="on_treeview2_button_press_event" last_modification_time="Sun, 12 Jan 2003 15:57:58 GMT"/> + <signal name="key_press_event" handler="on_treeview2_key_press_event" last_modification_time="Sun, 12 Jan 2003 15:58:01 GMT"/> + </widget> + </child> + </widget> + <packing> + <property name="shrink">True</property> + <property name="resize">False</property> + </packing> + </child> + + <child> + <widget class="GtkScrolledWindow" id="scrolledwindow3"> + <property name="visible">True</property> + <property name="hscrollbar_policy">GTK_POLICY_NEVER</property> + <property name="vscrollbar_policy">GTK_POLICY_AUTOMATIC</property> + <property name="shadow_type">GTK_SHADOW_IN</property> + <property name="window_placement">GTK_CORNER_TOP_LEFT</property> + + <child> + <widget class="GtkTextView" id="textview3"> + <property name="visible">True</property> + <property name="can_focus">True</property> + <property name="editable">False</property> + <property name="overwrite">False</property> + <property name="accepts_tab">True</property> + <property name="justification">GTK_JUSTIFY_LEFT</property> + <property name="wrap_mode">GTK_WRAP_WORD</property> + <property name="cursor_visible">True</property> + <property name="pixels_above_lines">0</property> + <property name="pixels_below_lines">0</property> + <property name="pixels_inside_wrap">0</property> + <property name="left_margin">0</property> + <property name="right_margin">0</property> + <property name="indent">0</property> + <property name="text" translatable="yes">Sorry, no help available for this option yet.</property> + </widget> + </child> + </widget> + <packing> + <property name="shrink">True</property> + <property name="resize">True</property> + </packing> + </child> + </widget> + <packing> + <property name="shrink">True</property> + <property name="resize">True</property> + </packing> + </child> + </widget> + <packing> + <property name="padding">0</property> + <property name="expand">True</property> + <property name="fill">True</property> + </packing> + </child> + </widget> + </child> +</widget> + +</glade-interface> diff --git a/src/net/scripts/kconfig/images.c b/src/net/scripts/kconfig/images.c new file mode 100644 index 0000000..2f9afff --- /dev/null +++ b/src/net/scripts/kconfig/images.c @@ -0,0 +1,328 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2002 Roman Zippel <zippel@linux-m68k.org> + */ + +#include "images.h" + +const char * const xpm_load[] = { +"22 22 5 1", +". c None", +"# c #000000", +"c c #838100", +"a c #ffff00", +"b c #ffffff", +"......................", +"......................", +"......................", +"............####....#.", +"...........#....##.##.", +"..................###.", +".................####.", +".####...........#####.", +"#abab##########.......", +"#babababababab#.......", +"#ababababababa#.......", +"#babababababab#.......", +"#ababab###############", +"#babab##cccccccccccc##", +"#abab##cccccccccccc##.", +"#bab##cccccccccccc##..", +"#ab##cccccccccccc##...", +"#b##cccccccccccc##....", +"###cccccccccccc##.....", +"##cccccccccccc##......", +"###############.......", +"......................"}; + +const char * const xpm_save[] = { +"22 22 5 1", +". c None", +"# c #000000", +"a c #838100", +"b c #c5c2c5", +"c c #cdb6d5", +"......................", +".####################.", +".#aa#bbbbbbbbbbbb#bb#.", +".#aa#bbbbbbbbbbbb#bb#.", +".#aa#bbbbbbbbbcbb####.", +".#aa#bbbccbbbbbbb#aa#.", +".#aa#bbbccbbbbbbb#aa#.", +".#aa#bbbbbbbbbbbb#aa#.", +".#aa#bbbbbbbbbbbb#aa#.", +".#aa#bbbbbbbbbbbb#aa#.", +".#aa#bbbbbbbbbbbb#aa#.", +".#aaa############aaa#.", +".#aaaaaaaaaaaaaaaaaa#.", +".#aaaaaaaaaaaaaaaaaa#.", +".#aaa#############aa#.", +".#aaa#########bbb#aa#.", +".#aaa#########bbb#aa#.", +".#aaa#########bbb#aa#.", +".#aaa#########bbb#aa#.", +".#aaa#########bbb#aa#.", +"..##################..", +"......................"}; + +const char * const xpm_back[] = { +"22 22 3 1", +". c None", +"# c #000083", +"a c #838183", +"......................", +"......................", +"......................", +"......................", +"......................", +"...........######a....", +"..#......##########...", +"..##...####......##a..", +"..###.###.........##..", +"..######..........##..", +"..#####...........##..", +"..######..........##..", +"..#######.........##..", +"..########.......##a..", +"...............a###...", +"...............###....", +"......................", +"......................", +"......................", +"......................", +"......................", +"......................"}; + +const char * const xpm_tree_view[] = { +"22 22 2 1", +". c None", +"# c #000000", +"......................", +"......................", +"......#...............", +"......#...............", +"......#...............", +"......#...............", +"......#...............", +"......########........", +"......#...............", +"......#...............", +"......#...............", +"......#...............", +"......#...............", +"......########........", +"......#...............", +"......#...............", +"......#...............", +"......#...............", +"......#...............", +"......########........", +"......................", +"......................"}; + +const char * const xpm_single_view[] = { +"22 22 2 1", +". c None", +"# c #000000", +"......................", +"......................", +"..........#...........", +"..........#...........", +"..........#...........", +"..........#...........", +"..........#...........", +"..........#...........", +"..........#...........", +"..........#...........", +"..........#...........", +"..........#...........", +"..........#...........", +"..........#...........", +"..........#...........", +"..........#...........", +"..........#...........", +"..........#...........", +"..........#...........", +"..........#...........", +"......................", +"......................"}; + +const char * const xpm_split_view[] = { +"22 22 2 1", +". c None", +"# c #000000", +"......................", +"......................", +"......#......#........", +"......#......#........", +"......#......#........", +"......#......#........", +"......#......#........", +"......#......#........", +"......#......#........", +"......#......#........", +"......#......#........", +"......#......#........", +"......#......#........", +"......#......#........", +"......#......#........", +"......#......#........", +"......#......#........", +"......#......#........", +"......#......#........", +"......#......#........", +"......................", +"......................"}; + +const char * const xpm_symbol_no[] = { +"12 12 2 1", +" c white", +". c black", +" ", +" .......... ", +" . . ", +" . . ", +" . . ", +" . . ", +" . . ", +" . . ", +" . . ", +" . . ", +" .......... ", +" "}; + +const char * const xpm_symbol_mod[] = { +"12 12 2 1", +" c white", +". c black", +" ", +" .......... ", +" . . ", +" . . ", +" . .. . ", +" . .... . ", +" . .... . ", +" . .. . ", +" . . ", +" . . ", +" .......... ", +" "}; + +const char * const xpm_symbol_yes[] = { +"12 12 2 1", +" c white", +". c black", +" ", +" .......... ", +" . . ", +" . . ", +" . . . ", +" . .. . ", +" . . .. . ", +" . .... . ", +" . .. . ", +" . . ", +" .......... ", +" "}; + +const char * const xpm_choice_no[] = { +"12 12 2 1", +" c white", +". c black", +" ", +" .... ", +" .. .. ", +" . . ", +" . . ", +" . . ", +" . . ", +" . . ", +" . . ", +" .. .. ", +" .... ", +" "}; + +const char * const xpm_choice_yes[] = { +"12 12 2 1", +" c white", +". c black", +" ", +" .... ", +" .. .. ", +" . . ", +" . .. . ", +" . .... . ", +" . .... . ", +" . .. . ", +" . . ", +" .. .. ", +" .... ", +" "}; + +const char * const xpm_menu[] = { +"12 12 2 1", +" c white", +". c black", +" ", +" .......... ", +" . . ", +" . .. . ", +" . .... . ", +" . ...... . ", +" . ...... . ", +" . .... . ", +" . .. . ", +" . . ", +" .......... ", +" "}; + +const char * const xpm_menu_inv[] = { +"12 12 2 1", +" c white", +". c black", +" ", +" .......... ", +" .......... ", +" .. ...... ", +" .. .... ", +" .. .. ", +" .. .. ", +" .. .... ", +" .. ...... ", +" .......... ", +" .......... ", +" "}; + +const char * const xpm_menuback[] = { +"12 12 2 1", +" c white", +". c black", +" ", +" .......... ", +" . . ", +" . .. . ", +" . .... . ", +" . ...... . ", +" . ...... . ", +" . .... . ", +" . .. . ", +" . . ", +" .......... ", +" "}; + +const char * const xpm_void[] = { +"12 12 2 1", +" c white", +". c black", +" ", +" ", +" ", +" ", +" ", +" ", +" ", +" ", +" ", +" ", +" ", +" "}; diff --git a/src/net/scripts/kconfig/images.h b/src/net/scripts/kconfig/images.h new file mode 100644 index 0000000..7212dec --- /dev/null +++ b/src/net/scripts/kconfig/images.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2002 Roman Zippel <zippel@linux-m68k.org> + */ + +#ifndef IMAGES_H +#define IMAGES_H + +#ifdef __cplusplus +extern "C" { +#endif + +extern const char * const xpm_load[]; +extern const char * const xpm_save[]; +extern const char * const xpm_back[]; +extern const char * const xpm_tree_view[]; +extern const char * const xpm_single_view[]; +extern const char * const xpm_split_view[]; +extern const char * const xpm_symbol_no[]; +extern const char * const xpm_symbol_mod[]; +extern const char * const xpm_symbol_yes[]; +extern const char * const xpm_choice_no[]; +extern const char * const xpm_choice_yes[]; +extern const char * const xpm_menu[]; +extern const char * const xpm_menu_inv[]; +extern const char * const xpm_menuback[]; +extern const char * const xpm_void[]; + +#ifdef __cplusplus +} +#endif + +#endif /* IMAGES_H */ diff --git a/src/net/scripts/kconfig/lexer.l b/src/net/scripts/kconfig/lexer.l new file mode 100644 index 0000000..240109f --- /dev/null +++ b/src/net/scripts/kconfig/lexer.l @@ -0,0 +1,471 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2002 Roman Zippel <zippel@linux-m68k.org> + */ +%option nostdinit noyywrap never-interactive full ecs +%option 8bit nodefault yylineno +%x ASSIGN_VAL HELP STRING +%{ + +#include <assert.h> +#include <limits.h> +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <unistd.h> + +#include "lkc.h" +#include "parser.tab.h" + +#define YY_DECL static int yylex1(void) + +#define START_STRSIZE 16 + +static struct { + struct file *file; + int lineno; +} current_pos; + +static int prev_prev_token = T_EOL; +static int prev_token = T_EOL; +static char *text; +static int text_size, text_asize; + +struct buffer { + struct buffer *parent; + YY_BUFFER_STATE state; +}; + +static struct buffer *current_buf; + +static int last_ts, first_ts; + +static char *expand_token(const char *in, size_t n); +static void append_expanded_string(const char *in); +static void zconf_endhelp(void); +static void zconf_endfile(void); + +static void new_string(void) +{ + text = xmalloc(START_STRSIZE); + text_asize = START_STRSIZE; + text_size = 0; + *text = 0; +} + +static void append_string(const char *str, int size) +{ + int new_size = text_size + size + 1; + if (new_size > text_asize) { + new_size += START_STRSIZE - 1; + new_size &= -START_STRSIZE; + text = xrealloc(text, new_size); + text_asize = new_size; + } + memcpy(text + text_size, str, size); + text_size += size; + text[text_size] = 0; +} + +static void alloc_string(const char *str, int size) +{ + text = xmalloc(size + 1); + memcpy(text, str, size); + text[size] = 0; +} + +static void warn_ignored_character(char chr) +{ + fprintf(stderr, + "%s:%d:warning: ignoring unsupported character '%c'\n", + current_file->name, yylineno, chr); +} +%} + +n [A-Za-z0-9_-] + +%% + int str = 0; + int ts, i; + +#.* /* ignore comment */ +[ \t]* /* whitespaces */ +\\\n /* escaped new line */ +\n return T_EOL; +"allnoconfig_y" return T_ALLNOCONFIG_Y; +"bool" return T_BOOL; +"choice" return T_CHOICE; +"comment" return T_COMMENT; +"config" return T_CONFIG; +"def_bool" return T_DEF_BOOL; +"def_tristate" return T_DEF_TRISTATE; +"default" return T_DEFAULT; +"defconfig_list" return T_DEFCONFIG_LIST; +"depends" return T_DEPENDS; +"endchoice" return T_ENDCHOICE; +"endif" return T_ENDIF; +"endmenu" return T_ENDMENU; +"help" return T_HELP; +"hex" return T_HEX; +"if" return T_IF; +"imply" return T_IMPLY; +"int" return T_INT; +"mainmenu" return T_MAINMENU; +"menu" return T_MENU; +"menuconfig" return T_MENUCONFIG; +"modules" return T_MODULES; +"on" return T_ON; +"option" return T_OPTION; +"optional" return T_OPTIONAL; +"prompt" return T_PROMPT; +"range" return T_RANGE; +"select" return T_SELECT; +"source" return T_SOURCE; +"string" return T_STRING; +"tristate" return T_TRISTATE; +"visible" return T_VISIBLE; +"||" return T_OR; +"&&" return T_AND; +"=" return T_EQUAL; +"!=" return T_UNEQUAL; +"<" return T_LESS; +"<=" return T_LESS_EQUAL; +">" return T_GREATER; +">=" return T_GREATER_EQUAL; +"!" return T_NOT; +"(" return T_OPEN_PAREN; +")" return T_CLOSE_PAREN; +":=" return T_COLON_EQUAL; +"+=" return T_PLUS_EQUAL; +\"|\' { + str = yytext[0]; + new_string(); + BEGIN(STRING); + } +{n}+ { + alloc_string(yytext, yyleng); + yylval.string = text; + return T_WORD; + } +({n}|$)+ { + /* this token includes at least one '$' */ + yylval.string = expand_token(yytext, yyleng); + if (strlen(yylval.string)) + return T_WORD; + free(yylval.string); + } +. warn_ignored_character(*yytext); + +<ASSIGN_VAL>{ + [^[:blank:]\n]+.* { + alloc_string(yytext, yyleng); + yylval.string = text; + return T_ASSIGN_VAL; + } + \n { BEGIN(INITIAL); return T_EOL; } + . +} + +<STRING>{ + "$".* append_expanded_string(yytext); + [^$'"\\\n]+ { + append_string(yytext, yyleng); + } + \\.? { + append_string(yytext + 1, yyleng - 1); + } + \'|\" { + if (str == yytext[0]) { + BEGIN(INITIAL); + yylval.string = text; + return T_WORD_QUOTE; + } else + append_string(yytext, 1); + } + \n { + fprintf(stderr, + "%s:%d:warning: multi-line strings not supported\n", + zconf_curname(), zconf_lineno()); + unput('\n'); + BEGIN(INITIAL); + yylval.string = text; + return T_WORD_QUOTE; + } + <<EOF>> { + BEGIN(INITIAL); + yylval.string = text; + return T_WORD_QUOTE; + } +} + +<HELP>{ + [ \t]+ { + ts = 0; + for (i = 0; i < yyleng; i++) { + if (yytext[i] == '\t') + ts = (ts & ~7) + 8; + else + ts++; + } + last_ts = ts; + if (first_ts) { + if (ts < first_ts) { + zconf_endhelp(); + return T_HELPTEXT; + } + ts -= first_ts; + while (ts > 8) { + append_string(" ", 8); + ts -= 8; + } + append_string(" ", ts); + } + } + [ \t]*\n/[^ \t\n] { + zconf_endhelp(); + return T_HELPTEXT; + } + [ \t]*\n { + append_string("\n", 1); + } + [^ \t\n].* { + while (yyleng) { + if ((yytext[yyleng-1] != ' ') && (yytext[yyleng-1] != '\t')) + break; + yyleng--; + } + append_string(yytext, yyleng); + if (!first_ts) + first_ts = last_ts; + } + <<EOF>> { + zconf_endhelp(); + return T_HELPTEXT; + } +} + +<<EOF>> { + BEGIN(INITIAL); + + if (prev_token != T_EOL && prev_token != T_HELPTEXT) + fprintf(stderr, "%s:%d:warning: no new line at end of file\n", + current_file->name, yylineno); + + if (current_file) { + zconf_endfile(); + return T_EOL; + } + fclose(yyin); + yyterminate(); +} + +%% + +/* second stage lexer */ +int yylex(void) +{ + int token; + +repeat: + token = yylex1(); + + if (prev_token == T_EOL || prev_token == T_HELPTEXT) { + if (token == T_EOL) { + /* Do not pass unneeded T_EOL to the parser. */ + goto repeat; + } else { + /* + * For the parser, update file/lineno at the first token + * of each statement. Generally, \n is a statement + * terminator in Kconfig, but it is not always true + * because \n could be escaped by a backslash. + */ + current_pos.file = current_file; + current_pos.lineno = yylineno; + } + } + + if (prev_prev_token == T_EOL && prev_token == T_WORD && + (token == T_EQUAL || token == T_COLON_EQUAL || token == T_PLUS_EQUAL)) + BEGIN(ASSIGN_VAL); + + prev_prev_token = prev_token; + prev_token = token; + + return token; +} + +static char *expand_token(const char *in, size_t n) +{ + char *out; + int c; + char c2; + const char *rest, *end; + + new_string(); + append_string(in, n); + + /* get the whole line because we do not know the end of token. */ + while ((c = input()) != EOF) { + if (c == '\n') { + unput(c); + break; + } + c2 = c; + append_string(&c2, 1); + } + + rest = text; + out = expand_one_token(&rest); + + /* push back unused characters to the input stream */ + end = rest + strlen(rest); + while (end > rest) + unput(*--end); + + free(text); + + return out; +} + +static void append_expanded_string(const char *str) +{ + const char *end; + char *res; + + str++; + + res = expand_dollar(&str); + + /* push back unused characters to the input stream */ + end = str + strlen(str); + while (end > str) + unput(*--end); + + append_string(res, strlen(res)); + + free(res); +} + +void zconf_starthelp(void) +{ + new_string(); + last_ts = first_ts = 0; + BEGIN(HELP); +} + +static void zconf_endhelp(void) +{ + yylval.string = text; + BEGIN(INITIAL); +} + + +/* + * Try to open specified file with following names: + * ./name + * $(srctree)/name + * The latter is used when srctree is separate from objtree + * when compiling the kernel. + * Return NULL if file is not found. + */ +FILE *zconf_fopen(const char *name) +{ + char *env, fullname[PATH_MAX+1]; + FILE *f; + + f = fopen(name, "r"); + if (!f && name != NULL && name[0] != '/') { + env = getenv(SRCTREE); + if (env) { + snprintf(fullname, sizeof(fullname), + "%s/%s", env, name); + f = fopen(fullname, "r"); + } + } + return f; +} + +void zconf_initscan(const char *name) +{ + yyin = zconf_fopen(name); + if (!yyin) { + fprintf(stderr, "can't find file %s\n", name); + exit(1); + } + + current_buf = xmalloc(sizeof(*current_buf)); + memset(current_buf, 0, sizeof(*current_buf)); + + current_file = file_lookup(name); + yylineno = 1; +} + +void zconf_nextfile(const char *name) +{ + struct file *iter; + struct file *file = file_lookup(name); + struct buffer *buf = xmalloc(sizeof(*buf)); + memset(buf, 0, sizeof(*buf)); + + current_buf->state = YY_CURRENT_BUFFER; + yyin = zconf_fopen(file->name); + if (!yyin) { + fprintf(stderr, "%s:%d: can't open file \"%s\"\n", + zconf_curname(), zconf_lineno(), file->name); + exit(1); + } + yy_switch_to_buffer(yy_create_buffer(yyin, YY_BUF_SIZE)); + buf->parent = current_buf; + current_buf = buf; + + current_file->lineno = yylineno; + file->parent = current_file; + + for (iter = current_file; iter; iter = iter->parent) { + if (!strcmp(iter->name, file->name)) { + fprintf(stderr, + "Recursive inclusion detected.\n" + "Inclusion path:\n" + " current file : %s\n", file->name); + iter = file; + do { + iter = iter->parent; + fprintf(stderr, " included from: %s:%d\n", + iter->name, iter->lineno - 1); + } while (strcmp(iter->name, file->name)); + exit(1); + } + } + + yylineno = 1; + current_file = file; +} + +static void zconf_endfile(void) +{ + struct buffer *parent; + + current_file = current_file->parent; + if (current_file) + yylineno = current_file->lineno; + + parent = current_buf->parent; + if (parent) { + fclose(yyin); + yy_delete_buffer(YY_CURRENT_BUFFER); + yy_switch_to_buffer(parent->state); + } + free(current_buf); + current_buf = parent; +} + +int zconf_lineno(void) +{ + return current_pos.lineno; +} + +const char *zconf_curname(void) +{ + return current_pos.file ? current_pos.file->name : "<none>"; +} diff --git a/src/net/scripts/kconfig/list.h b/src/net/scripts/kconfig/list.h new file mode 100644 index 0000000..45cb237 --- /dev/null +++ b/src/net/scripts/kconfig/list.h @@ -0,0 +1,132 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef LIST_H +#define LIST_H + +/* + * Copied from include/linux/... + */ + +#undef offsetof +#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER) + +/** + * container_of - cast a member of a structure out to the containing structure + * @ptr: the pointer to the member. + * @type: the type of the container struct this is embedded in. + * @member: the name of the member within the struct. + * + */ +#define container_of(ptr, type, member) ({ \ + const typeof( ((type *)0)->member ) *__mptr = (ptr); \ + (type *)( (char *)__mptr - offsetof(type,member) );}) + + +struct list_head { + struct list_head *next, *prev; +}; + + +#define LIST_HEAD_INIT(name) { &(name), &(name) } + +#define LIST_HEAD(name) \ + struct list_head name = LIST_HEAD_INIT(name) + +/** + * list_entry - get the struct for this entry + * @ptr: the &struct list_head pointer. + * @type: the type of the struct this is embedded in. + * @member: the name of the list_head within the struct. + */ +#define list_entry(ptr, type, member) \ + container_of(ptr, type, member) + +/** + * list_for_each_entry - iterate over list of given type + * @pos: the type * to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the list_head within the struct. + */ +#define list_for_each_entry(pos, head, member) \ + for (pos = list_entry((head)->next, typeof(*pos), member); \ + &pos->member != (head); \ + pos = list_entry(pos->member.next, typeof(*pos), member)) + +/** + * list_for_each_entry_safe - iterate over list of given type safe against removal of list entry + * @pos: the type * to use as a loop cursor. + * @n: another type * to use as temporary storage + * @head: the head for your list. + * @member: the name of the list_head within the struct. + */ +#define list_for_each_entry_safe(pos, n, head, member) \ + for (pos = list_entry((head)->next, typeof(*pos), member), \ + n = list_entry(pos->member.next, typeof(*pos), member); \ + &pos->member != (head); \ + pos = n, n = list_entry(n->member.next, typeof(*n), member)) + +/** + * list_empty - tests whether a list is empty + * @head: the list to test. + */ +static inline int list_empty(const struct list_head *head) +{ + return head->next == head; +} + +/* + * Insert a new entry between two known consecutive entries. + * + * This is only for internal list manipulation where we know + * the prev/next entries already! + */ +static inline void __list_add(struct list_head *_new, + struct list_head *prev, + struct list_head *next) +{ + next->prev = _new; + _new->next = next; + _new->prev = prev; + prev->next = _new; +} + +/** + * list_add_tail - add a new entry + * @new: new entry to be added + * @head: list head to add it before + * + * Insert a new entry before the specified head. + * This is useful for implementing queues. + */ +static inline void list_add_tail(struct list_head *_new, struct list_head *head) +{ + __list_add(_new, head->prev, head); +} + +/* + * Delete a list entry by making the prev/next entries + * point to each other. + * + * This is only for internal list manipulation where we know + * the prev/next entries already! + */ +static inline void __list_del(struct list_head *prev, struct list_head *next) +{ + next->prev = prev; + prev->next = next; +} + +#define LIST_POISON1 ((void *) 0x00100100) +#define LIST_POISON2 ((void *) 0x00200200) +/** + * list_del - deletes entry from list. + * @entry: the element to delete from the list. + * Note: list_empty() on entry does not return true after this, the entry is + * in an undefined state. + */ +static inline void list_del(struct list_head *entry) +{ + __list_del(entry->prev, entry->next); + entry->next = (struct list_head*)LIST_POISON1; + entry->prev = (struct list_head*)LIST_POISON2; +} +#endif diff --git a/src/net/scripts/kconfig/lkc.h b/src/net/scripts/kconfig/lkc.h new file mode 100644 index 0000000..8454649 --- /dev/null +++ b/src/net/scripts/kconfig/lkc.h @@ -0,0 +1,173 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2002 Roman Zippel <zippel@linux-m68k.org> + */ + +#ifndef LKC_H +#define LKC_H + +#include "expr.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#include "lkc_proto.h" + +#define SRCTREE "srctree" + +#ifndef PACKAGE +#define PACKAGE "linux" +#endif + +#ifndef CONFIG_ +#define CONFIG_ "CONFIG_" +#endif +static inline const char *CONFIG_prefix(void) +{ + return getenv( "CONFIG_" ) ?: CONFIG_; +} +#undef CONFIG_ +#define CONFIG_ CONFIG_prefix() + +enum conf_def_mode { + def_default, + def_yes, + def_mod, + def_y2m, + def_m2y, + def_no, + def_random +}; + +extern int yylineno; +void zconfdump(FILE *out); +void zconf_starthelp(void); +FILE *zconf_fopen(const char *name); +void zconf_initscan(const char *name); +void zconf_nextfile(const char *name); +int zconf_lineno(void); +const char *zconf_curname(void); + +/* confdata.c */ +const char *conf_get_configname(void); +void sym_set_change_count(int count); +void sym_add_change_count(int count); +bool conf_set_all_new_symbols(enum conf_def_mode mode); +void conf_rewrite_mod_or_yes(enum conf_def_mode mode); +void set_all_choice_values(struct symbol *csym); + +/* confdata.c and expr.c */ +static inline void xfwrite(const void *str, size_t len, size_t count, FILE *out) +{ + assert(len != 0); + + if (fwrite(str, len, count, out) != count) + fprintf(stderr, "Error in writing or end of file.\n"); +} + +/* util.c */ +struct file *file_lookup(const char *name); +void *xmalloc(size_t size); +void *xcalloc(size_t nmemb, size_t size); +void *xrealloc(void *p, size_t size); +char *xstrdup(const char *s); +char *xstrndup(const char *s, size_t n); + +/* lexer.l */ +int yylex(void); + +struct gstr { + size_t len; + char *s; + /* + * when max_width is not zero long lines in string s (if any) get + * wrapped not to exceed the max_width value + */ + int max_width; +}; +struct gstr str_new(void); +void str_free(struct gstr *gs); +void str_append(struct gstr *gs, const char *s); +void str_printf(struct gstr *gs, const char *fmt, ...); +const char *str_get(struct gstr *gs); + +/* menu.c */ +void _menu_init(void); +void menu_warn(struct menu *menu, const char *fmt, ...); +struct menu *menu_add_menu(void); +void menu_end_menu(void); +void menu_add_entry(struct symbol *sym); +void menu_add_dep(struct expr *dep); +void menu_add_visibility(struct expr *dep); +struct property *menu_add_prompt(enum prop_type type, char *prompt, struct expr *dep); +void menu_add_expr(enum prop_type type, struct expr *expr, struct expr *dep); +void menu_add_symbol(enum prop_type type, struct symbol *sym, struct expr *dep); +void menu_add_option_modules(void); +void menu_add_option_defconfig_list(void); +void menu_add_option_allnoconfig_y(void); +void menu_finalize(struct menu *parent); +void menu_set_type(int type); + +extern struct menu rootmenu; + +bool menu_is_empty(struct menu *menu); +bool menu_is_visible(struct menu *menu); +bool menu_has_prompt(struct menu *menu); +const char *menu_get_prompt(struct menu *menu); +struct menu *menu_get_root_menu(struct menu *menu); +struct menu *menu_get_parent_menu(struct menu *menu); +bool menu_has_help(struct menu *menu); +const char *menu_get_help(struct menu *menu); +struct gstr get_relations_str(struct symbol **sym_arr, struct list_head *head); +void menu_get_ext_help(struct menu *menu, struct gstr *help); + +/* symbol.c */ +void sym_clear_all_valid(void); +struct symbol *sym_choice_default(struct symbol *sym); +struct property *sym_get_range_prop(struct symbol *sym); +const char *sym_get_string_default(struct symbol *sym); +struct symbol *sym_check_deps(struct symbol *sym); +struct symbol *prop_get_symbol(struct property *prop); + +static inline tristate sym_get_tristate_value(struct symbol *sym) +{ + return sym->curr.tri; +} + + +static inline struct symbol *sym_get_choice_value(struct symbol *sym) +{ + return (struct symbol *)sym->curr.val; +} + +static inline bool sym_set_choice_value(struct symbol *ch, struct symbol *chval) +{ + return sym_set_tristate_value(chval, yes); +} + +static inline bool sym_is_choice(struct symbol *sym) +{ + return sym->flags & SYMBOL_CHOICE ? true : false; +} + +static inline bool sym_is_choice_value(struct symbol *sym) +{ + return sym->flags & SYMBOL_CHOICEVAL ? true : false; +} + +static inline bool sym_is_optional(struct symbol *sym) +{ + return sym->flags & SYMBOL_OPTIONAL ? true : false; +} + +static inline bool sym_has_value(struct symbol *sym) +{ + return sym->flags & SYMBOL_DEF_USER ? true : false; +} + +#ifdef __cplusplus +} +#endif + +#endif /* LKC_H */ diff --git a/src/net/scripts/kconfig/lkc_proto.h b/src/net/scripts/kconfig/lkc_proto.h new file mode 100644 index 0000000..9e81be3 --- /dev/null +++ b/src/net/scripts/kconfig/lkc_proto.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#include <stdarg.h> + +/* confdata.c */ +void conf_parse(const char *name); +int conf_read(const char *name); +int conf_read_simple(const char *name, int); +int conf_write_defconfig(const char *name); +int conf_write(const char *name); +int conf_write_autoconf(int overwrite); +bool conf_get_changed(void); +void conf_set_changed_callback(void (*fn)(void)); +void conf_set_message_callback(void (*fn)(const char *s)); + +/* symbol.c */ +extern struct symbol * symbol_hash[SYMBOL_HASHSIZE]; + +struct symbol * sym_lookup(const char *name, int flags); +struct symbol * sym_find(const char *name); +const char * sym_escape_string_value(const char *in); +struct symbol ** sym_re_search(const char *pattern); +const char * sym_type_name(enum symbol_type type); +void sym_calc_value(struct symbol *sym); +enum symbol_type sym_get_type(struct symbol *sym); +bool sym_tristate_within_range(struct symbol *sym,tristate tri); +bool sym_set_tristate_value(struct symbol *sym,tristate tri); +tristate sym_toggle_tristate_value(struct symbol *sym); +bool sym_string_valid(struct symbol *sym, const char *newval); +bool sym_string_within_range(struct symbol *sym, const char *str); +bool sym_set_string_value(struct symbol *sym, const char *newval); +bool sym_is_changeable(struct symbol *sym); +struct property * sym_get_choice_prop(struct symbol *sym); +const char * sym_get_string_value(struct symbol *sym); + +const char * prop_get_type_name(enum prop_type type); + +/* preprocess.c */ +enum variable_flavor { + VAR_SIMPLE, + VAR_RECURSIVE, + VAR_APPEND, +}; +void env_write_dep(FILE *f, const char *auto_conf_name); +void variable_add(const char *name, const char *value, + enum variable_flavor flavor); +void variable_all_del(void); +char *expand_dollar(const char **str); +char *expand_one_token(const char **str); + +/* expr.c */ +void expr_print(struct expr *e, void (*fn)(void *, struct symbol *, const char *), void *data, int prevtoken); diff --git a/src/net/scripts/kconfig/lxdialog/BIG.FAT.WARNING b/src/net/scripts/kconfig/lxdialog/BIG.FAT.WARNING new file mode 100644 index 0000000..7cb5a7e --- /dev/null +++ b/src/net/scripts/kconfig/lxdialog/BIG.FAT.WARNING @@ -0,0 +1,4 @@ +This is NOT the official version of dialog. This version has been +significantly modified from the original. It is for use by the Linux +kernel configuration script. Please do not bother Savio Lam with +questions about this program. diff --git a/src/net/scripts/kconfig/lxdialog/checklist.c b/src/net/scripts/kconfig/lxdialog/checklist.c new file mode 100644 index 0000000..fd161cf --- /dev/null +++ b/src/net/scripts/kconfig/lxdialog/checklist.c @@ -0,0 +1,319 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * checklist.c -- implements the checklist box + * + * ORIGINAL AUTHOR: Savio Lam (lam836@cs.cuhk.hk) + * Stuart Herbert - S.Herbert@sheffield.ac.uk: radiolist extension + * Alessandro Rubini - rubini@ipvvis.unipv.it: merged the two + * MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcap@cfw.com) + */ + +#include "dialog.h" + +static int list_width, check_x, item_x; + +/* + * Print list item + */ +static void print_item(WINDOW * win, int choice, int selected) +{ + int i; + char *list_item = malloc(list_width + 1); + + strncpy(list_item, item_str(), list_width - item_x); + list_item[list_width - item_x] = '\0'; + + /* Clear 'residue' of last item */ + wattrset(win, dlg.menubox.atr); + wmove(win, choice, 0); + for (i = 0; i < list_width; i++) + waddch(win, ' '); + + wmove(win, choice, check_x); + wattrset(win, selected ? dlg.check_selected.atr + : dlg.check.atr); + if (!item_is_tag(':')) + wprintw(win, "(%c)", item_is_tag('X') ? 'X' : ' '); + + wattrset(win, selected ? dlg.tag_selected.atr : dlg.tag.atr); + mvwaddch(win, choice, item_x, list_item[0]); + wattrset(win, selected ? dlg.item_selected.atr : dlg.item.atr); + waddstr(win, list_item + 1); + if (selected) { + wmove(win, choice, check_x + 1); + wrefresh(win); + } + free(list_item); +} + +/* + * Print the scroll indicators. + */ +static void print_arrows(WINDOW * win, int choice, int item_no, int scroll, + int y, int x, int height) +{ + wmove(win, y, x); + + if (scroll > 0) { + wattrset(win, dlg.uarrow.atr); + waddch(win, ACS_UARROW); + waddstr(win, "(-)"); + } else { + wattrset(win, dlg.menubox.atr); + waddch(win, ACS_HLINE); + waddch(win, ACS_HLINE); + waddch(win, ACS_HLINE); + waddch(win, ACS_HLINE); + } + + y = y + height + 1; + wmove(win, y, x); + + if ((height < item_no) && (scroll + choice < item_no - 1)) { + wattrset(win, dlg.darrow.atr); + waddch(win, ACS_DARROW); + waddstr(win, "(+)"); + } else { + wattrset(win, dlg.menubox_border.atr); + waddch(win, ACS_HLINE); + waddch(win, ACS_HLINE); + waddch(win, ACS_HLINE); + waddch(win, ACS_HLINE); + } +} + +/* + * Display the termination buttons + */ +static void print_buttons(WINDOW * dialog, int height, int width, int selected) +{ + int x = width / 2 - 11; + int y = height - 2; + + print_button(dialog, "Select", y, x, selected == 0); + print_button(dialog, " Help ", y, x + 14, selected == 1); + + wmove(dialog, y, x + 1 + 14 * selected); + wrefresh(dialog); +} + +/* + * Display a dialog box with a list of options that can be turned on or off + * in the style of radiolist (only one option turned on at a time). + */ +int dialog_checklist(const char *title, const char *prompt, int height, + int width, int list_height) +{ + int i, x, y, box_x, box_y; + int key = 0, button = 0, choice = 0, scroll = 0, max_choice; + WINDOW *dialog, *list; + + /* which item to highlight */ + item_foreach() { + if (item_is_tag('X')) + choice = item_n(); + if (item_is_selected()) { + choice = item_n(); + break; + } + } + +do_resize: + if (getmaxy(stdscr) < (height + CHECKLIST_HEIGTH_MIN)) + return -ERRDISPLAYTOOSMALL; + if (getmaxx(stdscr) < (width + CHECKLIST_WIDTH_MIN)) + return -ERRDISPLAYTOOSMALL; + + max_choice = MIN(list_height, item_count()); + + /* center dialog box on screen */ + x = (getmaxx(stdscr) - width) / 2; + y = (getmaxy(stdscr) - height) / 2; + + draw_shadow(stdscr, y, x, height, width); + + dialog = newwin(height, width, y, x); + keypad(dialog, TRUE); + + draw_box(dialog, 0, 0, height, width, + dlg.dialog.atr, dlg.border.atr); + wattrset(dialog, dlg.border.atr); + mvwaddch(dialog, height - 3, 0, ACS_LTEE); + for (i = 0; i < width - 2; i++) + waddch(dialog, ACS_HLINE); + wattrset(dialog, dlg.dialog.atr); + waddch(dialog, ACS_RTEE); + + print_title(dialog, title, width); + + wattrset(dialog, dlg.dialog.atr); + print_autowrap(dialog, prompt, width - 2, 1, 3); + + list_width = width - 6; + box_y = height - list_height - 5; + box_x = (width - list_width) / 2 - 1; + + /* create new window for the list */ + list = subwin(dialog, list_height, list_width, y + box_y + 1, + x + box_x + 1); + + keypad(list, TRUE); + + /* draw a box around the list items */ + draw_box(dialog, box_y, box_x, list_height + 2, list_width + 2, + dlg.menubox_border.atr, dlg.menubox.atr); + + /* Find length of longest item in order to center checklist */ + check_x = 0; + item_foreach() + check_x = MAX(check_x, strlen(item_str()) + 4); + check_x = MIN(check_x, list_width); + + check_x = (list_width - check_x) / 2; + item_x = check_x + 4; + + if (choice >= list_height) { + scroll = choice - list_height + 1; + choice -= scroll; + } + + /* Print the list */ + for (i = 0; i < max_choice; i++) { + item_set(scroll + i); + print_item(list, i, i == choice); + } + + print_arrows(dialog, choice, item_count(), scroll, + box_y, box_x + check_x + 5, list_height); + + print_buttons(dialog, height, width, 0); + + wnoutrefresh(dialog); + wnoutrefresh(list); + doupdate(); + + while (key != KEY_ESC) { + key = wgetch(dialog); + + for (i = 0; i < max_choice; i++) { + item_set(i + scroll); + if (toupper(key) == toupper(item_str()[0])) + break; + } + + if (i < max_choice || key == KEY_UP || key == KEY_DOWN || + key == '+' || key == '-') { + if (key == KEY_UP || key == '-') { + if (!choice) { + if (!scroll) + continue; + /* Scroll list down */ + if (list_height > 1) { + /* De-highlight current first item */ + item_set(scroll); + print_item(list, 0, FALSE); + scrollok(list, TRUE); + wscrl(list, -1); + scrollok(list, FALSE); + } + scroll--; + item_set(scroll); + print_item(list, 0, TRUE); + print_arrows(dialog, choice, item_count(), + scroll, box_y, box_x + check_x + 5, list_height); + + wnoutrefresh(dialog); + wrefresh(list); + + continue; /* wait for another key press */ + } else + i = choice - 1; + } else if (key == KEY_DOWN || key == '+') { + if (choice == max_choice - 1) { + if (scroll + choice >= item_count() - 1) + continue; + /* Scroll list up */ + if (list_height > 1) { + /* De-highlight current last item before scrolling up */ + item_set(scroll + max_choice - 1); + print_item(list, + max_choice - 1, + FALSE); + scrollok(list, TRUE); + wscrl(list, 1); + scrollok(list, FALSE); + } + scroll++; + item_set(scroll + max_choice - 1); + print_item(list, max_choice - 1, TRUE); + + print_arrows(dialog, choice, item_count(), + scroll, box_y, box_x + check_x + 5, list_height); + + wnoutrefresh(dialog); + wrefresh(list); + + continue; /* wait for another key press */ + } else + i = choice + 1; + } + if (i != choice) { + /* De-highlight current item */ + item_set(scroll + choice); + print_item(list, choice, FALSE); + /* Highlight new item */ + choice = i; + item_set(scroll + choice); + print_item(list, choice, TRUE); + wnoutrefresh(dialog); + wrefresh(list); + } + continue; /* wait for another key press */ + } + switch (key) { + case 'H': + case 'h': + case '?': + button = 1; + /* fall-through */ + case 'S': + case 's': + case ' ': + case '\n': + item_foreach() + item_set_selected(0); + item_set(scroll + choice); + item_set_selected(1); + delwin(list); + delwin(dialog); + return button; + case TAB: + case KEY_LEFT: + case KEY_RIGHT: + button = ((key == KEY_LEFT ? --button : ++button) < 0) + ? 1 : (button > 1 ? 0 : button); + + print_buttons(dialog, height, width, button); + wrefresh(dialog); + break; + case 'X': + case 'x': + key = KEY_ESC; + break; + case KEY_ESC: + key = on_key_esc(dialog); + break; + case KEY_RESIZE: + delwin(list); + delwin(dialog); + on_key_resize(); + goto do_resize; + } + + /* Now, update everything... */ + doupdate(); + } + delwin(list); + delwin(dialog); + return key; /* ESC pressed */ +} diff --git a/src/net/scripts/kconfig/lxdialog/dialog.h b/src/net/scripts/kconfig/lxdialog/dialog.h new file mode 100644 index 0000000..68b565e --- /dev/null +++ b/src/net/scripts/kconfig/lxdialog/dialog.h @@ -0,0 +1,238 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * dialog.h -- common declarations for all dialog modules + * + * AUTHOR: Savio Lam (lam836@cs.cuhk.hk) + */ + +#include <sys/types.h> +#include <fcntl.h> +#include <unistd.h> +#include <ctype.h> +#include <stdlib.h> +#include <string.h> +#include <stdbool.h> + +#ifdef __sun__ +#define CURS_MACROS +#endif +#include <ncurses.h> + +/* + * Colors in ncurses 1.9.9e do not work properly since foreground and + * background colors are OR'd rather than separately masked. This version + * of dialog was hacked to work with ncurses 1.9.9e, making it incompatible + * with standard curses. The simplest fix (to make this work with standard + * curses) uses the wbkgdset() function, not used in the original hack. + * Turn it off if we're building with 1.9.9e, since it just confuses things. + */ +#if defined(NCURSES_VERSION) && defined(_NEED_WRAP) && !defined(GCC_PRINTFLIKE) +#define OLD_NCURSES 1 +#undef wbkgdset +#define wbkgdset(w,p) /*nothing */ +#else +#define OLD_NCURSES 0 +#endif + +#define TR(params) _tracef params + +#define KEY_ESC 27 +#define TAB 9 +#define MAX_LEN 2048 +#define BUF_SIZE (10*1024) +#define MIN(x,y) (x < y ? x : y) +#define MAX(x,y) (x > y ? x : y) + +#ifndef ACS_ULCORNER +#define ACS_ULCORNER '+' +#endif +#ifndef ACS_LLCORNER +#define ACS_LLCORNER '+' +#endif +#ifndef ACS_URCORNER +#define ACS_URCORNER '+' +#endif +#ifndef ACS_LRCORNER +#define ACS_LRCORNER '+' +#endif +#ifndef ACS_HLINE +#define ACS_HLINE '-' +#endif +#ifndef ACS_VLINE +#define ACS_VLINE '|' +#endif +#ifndef ACS_LTEE +#define ACS_LTEE '+' +#endif +#ifndef ACS_RTEE +#define ACS_RTEE '+' +#endif +#ifndef ACS_UARROW +#define ACS_UARROW '^' +#endif +#ifndef ACS_DARROW +#define ACS_DARROW 'v' +#endif + +/* error return codes */ +#define ERRDISPLAYTOOSMALL (KEY_MAX + 1) + +/* + * Color definitions + */ +struct dialog_color { + chtype atr; /* Color attribute */ + int fg; /* foreground */ + int bg; /* background */ + int hl; /* highlight this item */ +}; + +struct subtitle_list { + struct subtitle_list *next; + const char *text; +}; + +struct dialog_info { + const char *backtitle; + struct subtitle_list *subtitles; + struct dialog_color screen; + struct dialog_color shadow; + struct dialog_color dialog; + struct dialog_color title; + struct dialog_color border; + struct dialog_color button_active; + struct dialog_color button_inactive; + struct dialog_color button_key_active; + struct dialog_color button_key_inactive; + struct dialog_color button_label_active; + struct dialog_color button_label_inactive; + struct dialog_color inputbox; + struct dialog_color inputbox_border; + struct dialog_color searchbox; + struct dialog_color searchbox_title; + struct dialog_color searchbox_border; + struct dialog_color position_indicator; + struct dialog_color menubox; + struct dialog_color menubox_border; + struct dialog_color item; + struct dialog_color item_selected; + struct dialog_color tag; + struct dialog_color tag_selected; + struct dialog_color tag_key; + struct dialog_color tag_key_selected; + struct dialog_color check; + struct dialog_color check_selected; + struct dialog_color uarrow; + struct dialog_color darrow; +}; + +/* + * Global variables + */ +extern struct dialog_info dlg; +extern char dialog_input_result[]; +extern int saved_x, saved_y; /* Needed in signal handler in mconf.c */ + +/* + * Function prototypes + */ + +/* item list as used by checklist and menubox */ +void item_reset(void); +void item_make(const char *fmt, ...); +void item_add_str(const char *fmt, ...); +void item_set_tag(char tag); +void item_set_data(void *p); +void item_set_selected(int val); +int item_activate_selected(void); +void *item_data(void); +char item_tag(void); + +/* item list manipulation for lxdialog use */ +#define MAXITEMSTR 200 +struct dialog_item { + char str[MAXITEMSTR]; /* prompt displayed */ + char tag; + void *data; /* pointer to menu item - used by menubox+checklist */ + int selected; /* Set to 1 by dialog_*() function if selected. */ +}; + +/* list of lialog_items */ +struct dialog_list { + struct dialog_item node; + struct dialog_list *next; +}; + +extern struct dialog_list *item_cur; +extern struct dialog_list item_nil; +extern struct dialog_list *item_head; + +int item_count(void); +void item_set(int n); +int item_n(void); +const char *item_str(void); +int item_is_selected(void); +int item_is_tag(char tag); +#define item_foreach() \ + for (item_cur = item_head ? item_head: item_cur; \ + item_cur && (item_cur != &item_nil); item_cur = item_cur->next) + +/* generic key handlers */ +int on_key_esc(WINDOW *win); +int on_key_resize(void); + +/* minimum (re)size values */ +#define CHECKLIST_HEIGTH_MIN 6 /* For dialog_checklist() */ +#define CHECKLIST_WIDTH_MIN 6 +#define INPUTBOX_HEIGTH_MIN 2 /* For dialog_inputbox() */ +#define INPUTBOX_WIDTH_MIN 2 +#define MENUBOX_HEIGTH_MIN 15 /* For dialog_menu() */ +#define MENUBOX_WIDTH_MIN 65 +#define TEXTBOX_HEIGTH_MIN 8 /* For dialog_textbox() */ +#define TEXTBOX_WIDTH_MIN 8 +#define YESNO_HEIGTH_MIN 4 /* For dialog_yesno() */ +#define YESNO_WIDTH_MIN 4 +#define WINDOW_HEIGTH_MIN 19 /* For init_dialog() */ +#define WINDOW_WIDTH_MIN 80 + +int init_dialog(const char *backtitle); +void set_dialog_backtitle(const char *backtitle); +void set_dialog_subtitles(struct subtitle_list *subtitles); +void end_dialog(int x, int y); +void attr_clear(WINDOW * win, int height, int width, chtype attr); +void dialog_clear(void); +void print_autowrap(WINDOW * win, const char *prompt, int width, int y, int x); +void print_button(WINDOW * win, const char *label, int y, int x, int selected); +void print_title(WINDOW *dialog, const char *title, int width); +void draw_box(WINDOW * win, int y, int x, int height, int width, chtype box, + chtype border); +void draw_shadow(WINDOW * win, int y, int x, int height, int width); + +int first_alpha(const char *string, const char *exempt); +int dialog_yesno(const char *title, const char *prompt, int height, int width); +int dialog_msgbox(const char *title, const char *prompt, int height, + int width, int pause); + + +typedef void (*update_text_fn)(char *buf, size_t start, size_t end, void + *_data); +int dialog_textbox(const char *title, char *tbuf, int initial_height, + int initial_width, int *keys, int *_vscroll, int *_hscroll, + update_text_fn update_text, void *data); +int dialog_menu(const char *title, const char *prompt, + const void *selected, int *s_scroll); +int dialog_checklist(const char *title, const char *prompt, int height, + int width, int list_height); +int dialog_inputbox(const char *title, const char *prompt, int height, + int width, const char *init); + +/* + * This is the base for fictitious keys, which activate + * the buttons. + * + * Mouse-generated keys are the following: + * -- the first 32 are used as numbers, in addition to '0'-'9' + * -- the lowercase are used to signal mouse-enter events (M_EVENT + 'o') + * -- uppercase chars are used to invoke the button (M_EVENT + 'O') + */ +#define M_EVENT (KEY_MAX+1) diff --git a/src/net/scripts/kconfig/lxdialog/inputbox.c b/src/net/scripts/kconfig/lxdialog/inputbox.c new file mode 100644 index 0000000..1dcfb28 --- /dev/null +++ b/src/net/scripts/kconfig/lxdialog/inputbox.c @@ -0,0 +1,289 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * inputbox.c -- implements the input box + * + * ORIGINAL AUTHOR: Savio Lam (lam836@cs.cuhk.hk) + * MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcap@cfw.com) + */ + +#include "dialog.h" + +char dialog_input_result[MAX_LEN + 1]; + +/* + * Print the termination buttons + */ +static void print_buttons(WINDOW * dialog, int height, int width, int selected) +{ + int x = width / 2 - 11; + int y = height - 2; + + print_button(dialog, " Ok ", y, x, selected == 0); + print_button(dialog, " Help ", y, x + 14, selected == 1); + + wmove(dialog, y, x + 1 + 14 * selected); + wrefresh(dialog); +} + +/* + * Display a dialog box for inputing a string + */ +int dialog_inputbox(const char *title, const char *prompt, int height, int width, + const char *init) +{ + int i, x, y, box_y, box_x, box_width; + int input_x = 0, key = 0, button = -1; + int show_x, len, pos; + char *instr = dialog_input_result; + WINDOW *dialog; + + if (!init) + instr[0] = '\0'; + else + strcpy(instr, init); + +do_resize: + if (getmaxy(stdscr) <= (height - INPUTBOX_HEIGTH_MIN)) + return -ERRDISPLAYTOOSMALL; + if (getmaxx(stdscr) <= (width - INPUTBOX_WIDTH_MIN)) + return -ERRDISPLAYTOOSMALL; + + /* center dialog box on screen */ + x = (getmaxx(stdscr) - width) / 2; + y = (getmaxy(stdscr) - height) / 2; + + draw_shadow(stdscr, y, x, height, width); + + dialog = newwin(height, width, y, x); + keypad(dialog, TRUE); + + draw_box(dialog, 0, 0, height, width, + dlg.dialog.atr, dlg.border.atr); + wattrset(dialog, dlg.border.atr); + mvwaddch(dialog, height - 3, 0, ACS_LTEE); + for (i = 0; i < width - 2; i++) + waddch(dialog, ACS_HLINE); + wattrset(dialog, dlg.dialog.atr); + waddch(dialog, ACS_RTEE); + + print_title(dialog, title, width); + + wattrset(dialog, dlg.dialog.atr); + print_autowrap(dialog, prompt, width - 2, 1, 3); + + /* Draw the input field box */ + box_width = width - 6; + getyx(dialog, y, x); + box_y = y + 2; + box_x = (width - box_width) / 2; + draw_box(dialog, y + 1, box_x - 1, 3, box_width + 2, + dlg.dialog.atr, dlg.border.atr); + + print_buttons(dialog, height, width, 0); + + /* Set up the initial value */ + wmove(dialog, box_y, box_x); + wattrset(dialog, dlg.inputbox.atr); + + len = strlen(instr); + pos = len; + + if (len >= box_width) { + show_x = len - box_width + 1; + input_x = box_width - 1; + for (i = 0; i < box_width - 1; i++) + waddch(dialog, instr[show_x + i]); + } else { + show_x = 0; + input_x = len; + waddstr(dialog, instr); + } + + wmove(dialog, box_y, box_x + input_x); + + wrefresh(dialog); + + while (key != KEY_ESC) { + key = wgetch(dialog); + + if (button == -1) { /* Input box selected */ + switch (key) { + case TAB: + case KEY_UP: + case KEY_DOWN: + break; + case KEY_BACKSPACE: + case 8: /* ^H */ + case 127: /* ^? */ + if (pos) { + wattrset(dialog, dlg.inputbox.atr); + if (input_x == 0) { + show_x--; + } else + input_x--; + + if (pos < len) { + for (i = pos - 1; i < len; i++) { + instr[i] = instr[i+1]; + } + } + + pos--; + len--; + instr[len] = '\0'; + wmove(dialog, box_y, box_x); + for (i = 0; i < box_width; i++) { + if (!instr[show_x + i]) { + waddch(dialog, ' '); + break; + } + waddch(dialog, instr[show_x + i]); + } + wmove(dialog, box_y, input_x + box_x); + wrefresh(dialog); + } + continue; + case KEY_LEFT: + if (pos > 0) { + if (input_x > 0) { + wmove(dialog, box_y, --input_x + box_x); + } else if (input_x == 0) { + show_x--; + wmove(dialog, box_y, box_x); + for (i = 0; i < box_width; i++) { + if (!instr[show_x + i]) { + waddch(dialog, ' '); + break; + } + waddch(dialog, instr[show_x + i]); + } + wmove(dialog, box_y, box_x); + } + pos--; + } + continue; + case KEY_RIGHT: + if (pos < len) { + if (input_x < box_width - 1) { + wmove(dialog, box_y, ++input_x + box_x); + } else if (input_x == box_width - 1) { + show_x++; + wmove(dialog, box_y, box_x); + for (i = 0; i < box_width; i++) { + if (!instr[show_x + i]) { + waddch(dialog, ' '); + break; + } + waddch(dialog, instr[show_x + i]); + } + wmove(dialog, box_y, input_x + box_x); + } + pos++; + } + continue; + default: + if (key < 0x100 && isprint(key)) { + if (len < MAX_LEN) { + wattrset(dialog, dlg.inputbox.atr); + if (pos < len) { + for (i = len; i > pos; i--) + instr[i] = instr[i-1]; + instr[pos] = key; + } else { + instr[len] = key; + } + pos++; + len++; + instr[len] = '\0'; + + if (input_x == box_width - 1) { + show_x++; + } else { + input_x++; + } + + wmove(dialog, box_y, box_x); + for (i = 0; i < box_width; i++) { + if (!instr[show_x + i]) { + waddch(dialog, ' '); + break; + } + waddch(dialog, instr[show_x + i]); + } + wmove(dialog, box_y, input_x + box_x); + wrefresh(dialog); + } else + flash(); /* Alarm user about overflow */ + continue; + } + } + } + switch (key) { + case 'O': + case 'o': + delwin(dialog); + return 0; + case 'H': + case 'h': + delwin(dialog); + return 1; + case KEY_UP: + case KEY_LEFT: + switch (button) { + case -1: + button = 1; /* Indicates "Help" button is selected */ + print_buttons(dialog, height, width, 1); + break; + case 0: + button = -1; /* Indicates input box is selected */ + print_buttons(dialog, height, width, 0); + wmove(dialog, box_y, box_x + input_x); + wrefresh(dialog); + break; + case 1: + button = 0; /* Indicates "OK" button is selected */ + print_buttons(dialog, height, width, 0); + break; + } + break; + case TAB: + case KEY_DOWN: + case KEY_RIGHT: + switch (button) { + case -1: + button = 0; /* Indicates "OK" button is selected */ + print_buttons(dialog, height, width, 0); + break; + case 0: + button = 1; /* Indicates "Help" button is selected */ + print_buttons(dialog, height, width, 1); + break; + case 1: + button = -1; /* Indicates input box is selected */ + print_buttons(dialog, height, width, 0); + wmove(dialog, box_y, box_x + input_x); + wrefresh(dialog); + break; + } + break; + case ' ': + case '\n': + delwin(dialog); + return (button == -1 ? 0 : button); + case 'X': + case 'x': + key = KEY_ESC; + break; + case KEY_ESC: + key = on_key_esc(dialog); + break; + case KEY_RESIZE: + delwin(dialog); + on_key_resize(); + goto do_resize; + } + } + + delwin(dialog); + return KEY_ESC; /* ESC pressed */ +} diff --git a/src/net/scripts/kconfig/lxdialog/menubox.c b/src/net/scripts/kconfig/lxdialog/menubox.c new file mode 100644 index 0000000..58c2f8a --- /dev/null +++ b/src/net/scripts/kconfig/lxdialog/menubox.c @@ -0,0 +1,424 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * menubox.c -- implements the menu box + * + * ORIGINAL AUTHOR: Savio Lam (lam836@cs.cuhk.hk) + * MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcapw@cfw.com) + */ + +/* + * Changes by Clifford Wolf (god@clifford.at) + * + * [ 1998-06-13 ] + * + * *) A bugfix for the Page-Down problem + * + * *) Formerly when I used Page Down and Page Up, the cursor would be set + * to the first position in the menu box. Now lxdialog is a bit + * smarter and works more like other menu systems (just have a look at + * it). + * + * *) Formerly if I selected something my scrolling would be broken because + * lxdialog is re-invoked by the Menuconfig shell script, can't + * remember the last scrolling position, and just sets it so that the + * cursor is at the bottom of the box. Now it writes the temporary file + * lxdialog.scrltmp which contains this information. The file is + * deleted by lxdialog if the user leaves a submenu or enters a new + * one, but it would be nice if Menuconfig could make another "rm -f" + * just to be sure. Just try it out - you will recognise a difference! + * + * [ 1998-06-14 ] + * + * *) Now lxdialog is crash-safe against broken "lxdialog.scrltmp" files + * and menus change their size on the fly. + * + * *) If for some reason the last scrolling position is not saved by + * lxdialog, it sets the scrolling so that the selected item is in the + * middle of the menu box, not at the bottom. + * + * 02 January 1999, Michael Elizabeth Chastain (mec@shout.net) + * Reset 'scroll' to 0 if the value from lxdialog.scrltmp is bogus. + * This fixes a bug in Menuconfig where using ' ' to descend into menus + * would leave mis-synchronized lxdialog.scrltmp files lying around, + * fscanf would read in 'scroll', and eventually that value would get used. + */ + +#include "dialog.h" + +static int menu_width, item_x; + +/* + * Print menu item + */ +static void do_print_item(WINDOW * win, const char *item, int line_y, + int selected, int hotkey) +{ + int j; + char *menu_item = malloc(menu_width + 1); + + strncpy(menu_item, item, menu_width - item_x); + menu_item[menu_width - item_x] = '\0'; + j = first_alpha(menu_item, "YyNnMmHh"); + + /* Clear 'residue' of last item */ + wattrset(win, dlg.menubox.atr); + wmove(win, line_y, 0); +#if OLD_NCURSES + { + int i; + for (i = 0; i < menu_width; i++) + waddch(win, ' '); + } +#else + wclrtoeol(win); +#endif + wattrset(win, selected ? dlg.item_selected.atr : dlg.item.atr); + mvwaddstr(win, line_y, item_x, menu_item); + if (hotkey) { + wattrset(win, selected ? dlg.tag_key_selected.atr + : dlg.tag_key.atr); + mvwaddch(win, line_y, item_x + j, menu_item[j]); + } + if (selected) { + wmove(win, line_y, item_x + 1); + } + free(menu_item); + wrefresh(win); +} + +#define print_item(index, choice, selected) \ +do { \ + item_set(index); \ + do_print_item(menu, item_str(), choice, selected, !item_is_tag(':')); \ +} while (0) + +/* + * Print the scroll indicators. + */ +static void print_arrows(WINDOW * win, int item_no, int scroll, int y, int x, + int height) +{ + int cur_y, cur_x; + + getyx(win, cur_y, cur_x); + + wmove(win, y, x); + + if (scroll > 0) { + wattrset(win, dlg.uarrow.atr); + waddch(win, ACS_UARROW); + waddstr(win, "(-)"); + } else { + wattrset(win, dlg.menubox.atr); + waddch(win, ACS_HLINE); + waddch(win, ACS_HLINE); + waddch(win, ACS_HLINE); + waddch(win, ACS_HLINE); + } + + y = y + height + 1; + wmove(win, y, x); + wrefresh(win); + + if ((height < item_no) && (scroll + height < item_no)) { + wattrset(win, dlg.darrow.atr); + waddch(win, ACS_DARROW); + waddstr(win, "(+)"); + } else { + wattrset(win, dlg.menubox_border.atr); + waddch(win, ACS_HLINE); + waddch(win, ACS_HLINE); + waddch(win, ACS_HLINE); + waddch(win, ACS_HLINE); + } + + wmove(win, cur_y, cur_x); + wrefresh(win); +} + +/* + * Display the termination buttons. + */ +static void print_buttons(WINDOW * win, int height, int width, int selected) +{ + int x = width / 2 - 28; + int y = height - 2; + + print_button(win, "Select", y, x, selected == 0); + print_button(win, " Exit ", y, x + 12, selected == 1); + print_button(win, " Help ", y, x + 24, selected == 2); + print_button(win, " Save ", y, x + 36, selected == 3); + print_button(win, " Load ", y, x + 48, selected == 4); + + wmove(win, y, x + 1 + 12 * selected); + wrefresh(win); +} + +/* scroll up n lines (n may be negative) */ +static void do_scroll(WINDOW *win, int *scroll, int n) +{ + /* Scroll menu up */ + scrollok(win, TRUE); + wscrl(win, n); + scrollok(win, FALSE); + *scroll = *scroll + n; + wrefresh(win); +} + +/* + * Display a menu for choosing among a number of options + */ +int dialog_menu(const char *title, const char *prompt, + const void *selected, int *s_scroll) +{ + int i, j, x, y, box_x, box_y; + int height, width, menu_height; + int key = 0, button = 0, scroll = 0, choice = 0; + int first_item = 0, max_choice; + WINDOW *dialog, *menu; + +do_resize: + height = getmaxy(stdscr); + width = getmaxx(stdscr); + if (height < MENUBOX_HEIGTH_MIN || width < MENUBOX_WIDTH_MIN) + return -ERRDISPLAYTOOSMALL; + + height -= 4; + width -= 5; + menu_height = height - 10; + + max_choice = MIN(menu_height, item_count()); + + /* center dialog box on screen */ + x = (getmaxx(stdscr) - width) / 2; + y = (getmaxy(stdscr) - height) / 2; + + draw_shadow(stdscr, y, x, height, width); + + dialog = newwin(height, width, y, x); + keypad(dialog, TRUE); + + draw_box(dialog, 0, 0, height, width, + dlg.dialog.atr, dlg.border.atr); + wattrset(dialog, dlg.border.atr); + mvwaddch(dialog, height - 3, 0, ACS_LTEE); + for (i = 0; i < width - 2; i++) + waddch(dialog, ACS_HLINE); + wattrset(dialog, dlg.dialog.atr); + wbkgdset(dialog, dlg.dialog.atr & A_COLOR); + waddch(dialog, ACS_RTEE); + + print_title(dialog, title, width); + + wattrset(dialog, dlg.dialog.atr); + print_autowrap(dialog, prompt, width - 2, 1, 3); + + menu_width = width - 6; + box_y = height - menu_height - 5; + box_x = (width - menu_width) / 2 - 1; + + /* create new window for the menu */ + menu = subwin(dialog, menu_height, menu_width, + y + box_y + 1, x + box_x + 1); + keypad(menu, TRUE); + + /* draw a box around the menu items */ + draw_box(dialog, box_y, box_x, menu_height + 2, menu_width + 2, + dlg.menubox_border.atr, dlg.menubox.atr); + + if (menu_width >= 80) + item_x = (menu_width - 70) / 2; + else + item_x = 4; + + /* Set choice to default item */ + item_foreach() + if (selected && (selected == item_data())) + choice = item_n(); + /* get the saved scroll info */ + scroll = *s_scroll; + if ((scroll <= choice) && (scroll + max_choice > choice) && + (scroll >= 0) && (scroll + max_choice <= item_count())) { + first_item = scroll; + choice = choice - scroll; + } else { + scroll = 0; + } + if ((choice >= max_choice)) { + if (choice >= item_count() - max_choice / 2) + scroll = first_item = item_count() - max_choice; + else + scroll = first_item = choice - max_choice / 2; + choice = choice - scroll; + } + + /* Print the menu */ + for (i = 0; i < max_choice; i++) { + print_item(first_item + i, i, i == choice); + } + + wnoutrefresh(menu); + + print_arrows(dialog, item_count(), scroll, + box_y, box_x + item_x + 1, menu_height); + + print_buttons(dialog, height, width, 0); + wmove(menu, choice, item_x + 1); + wrefresh(menu); + + while (key != KEY_ESC) { + key = wgetch(menu); + + if (key < 256 && isalpha(key)) + key = tolower(key); + + if (strchr("ynmh", key)) + i = max_choice; + else { + for (i = choice + 1; i < max_choice; i++) { + item_set(scroll + i); + j = first_alpha(item_str(), "YyNnMmHh"); + if (key == tolower(item_str()[j])) + break; + } + if (i == max_choice) + for (i = 0; i < max_choice; i++) { + item_set(scroll + i); + j = first_alpha(item_str(), "YyNnMmHh"); + if (key == tolower(item_str()[j])) + break; + } + } + + if (item_count() != 0 && + (i < max_choice || + key == KEY_UP || key == KEY_DOWN || + key == '-' || key == '+' || + key == KEY_PPAGE || key == KEY_NPAGE)) { + /* Remove highligt of current item */ + print_item(scroll + choice, choice, FALSE); + + if (key == KEY_UP || key == '-') { + if (choice < 2 && scroll) { + /* Scroll menu down */ + do_scroll(menu, &scroll, -1); + + print_item(scroll, 0, FALSE); + } else + choice = MAX(choice - 1, 0); + + } else if (key == KEY_DOWN || key == '+') { + print_item(scroll+choice, choice, FALSE); + + if ((choice > max_choice - 3) && + (scroll + max_choice < item_count())) { + /* Scroll menu up */ + do_scroll(menu, &scroll, 1); + + print_item(scroll+max_choice - 1, + max_choice - 1, FALSE); + } else + choice = MIN(choice + 1, max_choice - 1); + + } else if (key == KEY_PPAGE) { + scrollok(menu, TRUE); + for (i = 0; (i < max_choice); i++) { + if (scroll > 0) { + do_scroll(menu, &scroll, -1); + print_item(scroll, 0, FALSE); + } else { + if (choice > 0) + choice--; + } + } + + } else if (key == KEY_NPAGE) { + for (i = 0; (i < max_choice); i++) { + if (scroll + max_choice < item_count()) { + do_scroll(menu, &scroll, 1); + print_item(scroll+max_choice-1, + max_choice - 1, FALSE); + } else { + if (choice + 1 < max_choice) + choice++; + } + } + } else + choice = i; + + print_item(scroll + choice, choice, TRUE); + + print_arrows(dialog, item_count(), scroll, + box_y, box_x + item_x + 1, menu_height); + + wnoutrefresh(dialog); + wrefresh(menu); + + continue; /* wait for another key press */ + } + + switch (key) { + case KEY_LEFT: + case TAB: + case KEY_RIGHT: + button = ((key == KEY_LEFT ? --button : ++button) < 0) + ? 4 : (button > 4 ? 0 : button); + + print_buttons(dialog, height, width, button); + wrefresh(menu); + break; + case ' ': + case 's': + case 'y': + case 'n': + case 'm': + case '/': + case 'h': + case '?': + case 'z': + case '\n': + /* save scroll info */ + *s_scroll = scroll; + delwin(menu); + delwin(dialog); + item_set(scroll + choice); + item_set_selected(1); + switch (key) { + case 'h': + case '?': + return 2; + case 's': + case 'y': + return 5; + case 'n': + return 6; + case 'm': + return 7; + case ' ': + return 8; + case '/': + return 9; + case 'z': + return 10; + case '\n': + return button; + } + return 0; + case 'e': + case 'x': + key = KEY_ESC; + break; + case KEY_ESC: + key = on_key_esc(menu); + break; + case KEY_RESIZE: + on_key_resize(); + delwin(menu); + delwin(dialog); + goto do_resize; + } + } + delwin(menu); + delwin(dialog); + return key; /* ESC pressed */ +} diff --git a/src/net/scripts/kconfig/lxdialog/textbox.c b/src/net/scripts/kconfig/lxdialog/textbox.c new file mode 100644 index 0000000..4e339b1 --- /dev/null +++ b/src/net/scripts/kconfig/lxdialog/textbox.c @@ -0,0 +1,395 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * textbox.c -- implements the text box + * + * ORIGINAL AUTHOR: Savio Lam (lam836@cs.cuhk.hk) + * MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcap@cfw.com) + */ + +#include "dialog.h" + +static void back_lines(int n); +static void print_page(WINDOW *win, int height, int width, update_text_fn + update_text, void *data); +static void print_line(WINDOW *win, int row, int width); +static char *get_line(void); +static void print_position(WINDOW * win); + +static int hscroll; +static int begin_reached, end_reached, page_length; +static char *buf; +static char *page; + +/* + * refresh window content + */ +static void refresh_text_box(WINDOW *dialog, WINDOW *box, int boxh, int boxw, + int cur_y, int cur_x, update_text_fn update_text, + void *data) +{ + print_page(box, boxh, boxw, update_text, data); + print_position(dialog); + wmove(dialog, cur_y, cur_x); /* Restore cursor position */ + wrefresh(dialog); +} + + +/* + * Display text from a file in a dialog box. + * + * keys is a null-terminated array + * update_text() may not add or remove any '\n' or '\0' in tbuf + */ +int dialog_textbox(const char *title, char *tbuf, int initial_height, + int initial_width, int *keys, int *_vscroll, int *_hscroll, + update_text_fn update_text, void *data) +{ + int i, x, y, cur_x, cur_y, key = 0; + int height, width, boxh, boxw; + WINDOW *dialog, *box; + bool done = false; + + begin_reached = 1; + end_reached = 0; + page_length = 0; + hscroll = 0; + buf = tbuf; + page = buf; /* page is pointer to start of page to be displayed */ + + if (_vscroll && *_vscroll) { + begin_reached = 0; + + for (i = 0; i < *_vscroll; i++) + get_line(); + } + if (_hscroll) + hscroll = *_hscroll; + +do_resize: + getmaxyx(stdscr, height, width); + if (height < TEXTBOX_HEIGTH_MIN || width < TEXTBOX_WIDTH_MIN) + return -ERRDISPLAYTOOSMALL; + if (initial_height != 0) + height = initial_height; + else + if (height > 4) + height -= 4; + else + height = 0; + if (initial_width != 0) + width = initial_width; + else + if (width > 5) + width -= 5; + else + width = 0; + + /* center dialog box on screen */ + x = (getmaxx(stdscr) - width) / 2; + y = (getmaxy(stdscr) - height) / 2; + + draw_shadow(stdscr, y, x, height, width); + + dialog = newwin(height, width, y, x); + keypad(dialog, TRUE); + + /* Create window for box region, used for scrolling text */ + boxh = height - 4; + boxw = width - 2; + box = subwin(dialog, boxh, boxw, y + 1, x + 1); + wattrset(box, dlg.dialog.atr); + wbkgdset(box, dlg.dialog.atr & A_COLOR); + + keypad(box, TRUE); + + /* register the new window, along with its borders */ + draw_box(dialog, 0, 0, height, width, + dlg.dialog.atr, dlg.border.atr); + + wattrset(dialog, dlg.border.atr); + mvwaddch(dialog, height - 3, 0, ACS_LTEE); + for (i = 0; i < width - 2; i++) + waddch(dialog, ACS_HLINE); + wattrset(dialog, dlg.dialog.atr); + wbkgdset(dialog, dlg.dialog.atr & A_COLOR); + waddch(dialog, ACS_RTEE); + + print_title(dialog, title, width); + + print_button(dialog, " Exit ", height - 2, width / 2 - 4, TRUE); + wnoutrefresh(dialog); + getyx(dialog, cur_y, cur_x); /* Save cursor position */ + + /* Print first page of text */ + attr_clear(box, boxh, boxw, dlg.dialog.atr); + refresh_text_box(dialog, box, boxh, boxw, cur_y, cur_x, update_text, + data); + + while (!done) { + key = wgetch(dialog); + switch (key) { + case 'E': /* Exit */ + case 'e': + case 'X': + case 'x': + case 'q': + case '\n': + done = true; + break; + case 'g': /* First page */ + case KEY_HOME: + if (!begin_reached) { + begin_reached = 1; + page = buf; + refresh_text_box(dialog, box, boxh, boxw, + cur_y, cur_x, update_text, + data); + } + break; + case 'G': /* Last page */ + case KEY_END: + + end_reached = 1; + /* point to last char in buf */ + page = buf + strlen(buf); + back_lines(boxh); + refresh_text_box(dialog, box, boxh, boxw, cur_y, + cur_x, update_text, data); + break; + case 'K': /* Previous line */ + case 'k': + case KEY_UP: + if (begin_reached) + break; + + back_lines(page_length + 1); + refresh_text_box(dialog, box, boxh, boxw, cur_y, + cur_x, update_text, data); + break; + case 'B': /* Previous page */ + case 'b': + case 'u': + case KEY_PPAGE: + if (begin_reached) + break; + back_lines(page_length + boxh); + refresh_text_box(dialog, box, boxh, boxw, cur_y, + cur_x, update_text, data); + break; + case 'J': /* Next line */ + case 'j': + case KEY_DOWN: + if (end_reached) + break; + + back_lines(page_length - 1); + refresh_text_box(dialog, box, boxh, boxw, cur_y, + cur_x, update_text, data); + break; + case KEY_NPAGE: /* Next page */ + case ' ': + case 'd': + if (end_reached) + break; + + begin_reached = 0; + refresh_text_box(dialog, box, boxh, boxw, cur_y, + cur_x, update_text, data); + break; + case '0': /* Beginning of line */ + case 'H': /* Scroll left */ + case 'h': + case KEY_LEFT: + if (hscroll <= 0) + break; + + if (key == '0') + hscroll = 0; + else + hscroll--; + /* Reprint current page to scroll horizontally */ + back_lines(page_length); + refresh_text_box(dialog, box, boxh, boxw, cur_y, + cur_x, update_text, data); + break; + case 'L': /* Scroll right */ + case 'l': + case KEY_RIGHT: + if (hscroll >= MAX_LEN) + break; + hscroll++; + /* Reprint current page to scroll horizontally */ + back_lines(page_length); + refresh_text_box(dialog, box, boxh, boxw, cur_y, + cur_x, update_text, data); + break; + case KEY_ESC: + if (on_key_esc(dialog) == KEY_ESC) + done = true; + break; + case KEY_RESIZE: + back_lines(height); + delwin(box); + delwin(dialog); + on_key_resize(); + goto do_resize; + default: + for (i = 0; keys[i]; i++) { + if (key == keys[i]) { + done = true; + break; + } + } + } + } + delwin(box); + delwin(dialog); + if (_vscroll) { + const char *s; + + s = buf; + *_vscroll = 0; + back_lines(page_length); + while (s < page && (s = strchr(s, '\n'))) { + (*_vscroll)++; + s++; + } + } + if (_hscroll) + *_hscroll = hscroll; + return key; +} + +/* + * Go back 'n' lines in text. Called by dialog_textbox(). + * 'page' will be updated to point to the desired line in 'buf'. + */ +static void back_lines(int n) +{ + int i; + + begin_reached = 0; + /* Go back 'n' lines */ + for (i = 0; i < n; i++) { + if (*page == '\0') { + if (end_reached) { + end_reached = 0; + continue; + } + } + if (page == buf) { + begin_reached = 1; + return; + } + page--; + do { + if (page == buf) { + begin_reached = 1; + return; + } + page--; + } while (*page != '\n'); + page++; + } +} + +/* + * Print a new page of text. + */ +static void print_page(WINDOW *win, int height, int width, update_text_fn + update_text, void *data) +{ + int i, passed_end = 0; + + if (update_text) { + char *end; + + for (i = 0; i < height; i++) + get_line(); + end = page; + back_lines(height); + update_text(buf, page - buf, end - buf, data); + } + + page_length = 0; + for (i = 0; i < height; i++) { + print_line(win, i, width); + if (!passed_end) + page_length++; + if (end_reached && !passed_end) + passed_end = 1; + } + wnoutrefresh(win); +} + +/* + * Print a new line of text. + */ +static void print_line(WINDOW * win, int row, int width) +{ + char *line; + + line = get_line(); + line += MIN(strlen(line), hscroll); /* Scroll horizontally */ + wmove(win, row, 0); /* move cursor to correct line */ + waddch(win, ' '); + waddnstr(win, line, MIN(strlen(line), width - 2)); + + /* Clear 'residue' of previous line */ +#if OLD_NCURSES + { + int x = getcurx(win); + int i; + for (i = 0; i < width - x; i++) + waddch(win, ' '); + } +#else + wclrtoeol(win); +#endif +} + +/* + * Return current line of text. Called by dialog_textbox() and print_line(). + * 'page' should point to start of current line before calling, and will be + * updated to point to start of next line. + */ +static char *get_line(void) +{ + int i = 0; + static char line[MAX_LEN + 1]; + + end_reached = 0; + while (*page != '\n') { + if (*page == '\0') { + end_reached = 1; + break; + } else if (i < MAX_LEN) + line[i++] = *(page++); + else { + /* Truncate lines longer than MAX_LEN characters */ + if (i == MAX_LEN) + line[i++] = '\0'; + page++; + } + } + if (i <= MAX_LEN) + line[i] = '\0'; + if (!end_reached) + page++; /* move past '\n' */ + + return line; +} + +/* + * Print current position + */ +static void print_position(WINDOW * win) +{ + int percent; + + wattrset(win, dlg.position_indicator.atr); + wbkgdset(win, dlg.position_indicator.atr & A_COLOR); + percent = (page - buf) * 100 / strlen(buf); + wmove(win, getmaxy(win) - 3, getmaxx(win) - 9); + wprintw(win, "(%3d%%)", percent); +} diff --git a/src/net/scripts/kconfig/lxdialog/util.c b/src/net/scripts/kconfig/lxdialog/util.c new file mode 100644 index 0000000..1b490d4 --- /dev/null +++ b/src/net/scripts/kconfig/lxdialog/util.c @@ -0,0 +1,700 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * util.c + * + * ORIGINAL AUTHOR: Savio Lam (lam836@cs.cuhk.hk) + * MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcap@cfw.com) + */ + +#include <stdarg.h> + +#include "dialog.h" + +/* Needed in signal handler in mconf.c */ +int saved_x, saved_y; + +struct dialog_info dlg; + +static void set_mono_theme(void) +{ + dlg.screen.atr = A_NORMAL; + dlg.shadow.atr = A_NORMAL; + dlg.dialog.atr = A_NORMAL; + dlg.title.atr = A_BOLD; + dlg.border.atr = A_NORMAL; + dlg.button_active.atr = A_REVERSE; + dlg.button_inactive.atr = A_DIM; + dlg.button_key_active.atr = A_REVERSE; + dlg.button_key_inactive.atr = A_BOLD; + dlg.button_label_active.atr = A_REVERSE; + dlg.button_label_inactive.atr = A_NORMAL; + dlg.inputbox.atr = A_NORMAL; + dlg.inputbox_border.atr = A_NORMAL; + dlg.searchbox.atr = A_NORMAL; + dlg.searchbox_title.atr = A_BOLD; + dlg.searchbox_border.atr = A_NORMAL; + dlg.position_indicator.atr = A_BOLD; + dlg.menubox.atr = A_NORMAL; + dlg.menubox_border.atr = A_NORMAL; + dlg.item.atr = A_NORMAL; + dlg.item_selected.atr = A_REVERSE; + dlg.tag.atr = A_BOLD; + dlg.tag_selected.atr = A_REVERSE; + dlg.tag_key.atr = A_BOLD; + dlg.tag_key_selected.atr = A_REVERSE; + dlg.check.atr = A_BOLD; + dlg.check_selected.atr = A_REVERSE; + dlg.uarrow.atr = A_BOLD; + dlg.darrow.atr = A_BOLD; +} + +#define DLG_COLOR(dialog, f, b, h) \ +do { \ + dlg.dialog.fg = (f); \ + dlg.dialog.bg = (b); \ + dlg.dialog.hl = (h); \ +} while (0) + +static void set_classic_theme(void) +{ + DLG_COLOR(screen, COLOR_CYAN, COLOR_BLUE, true); + DLG_COLOR(shadow, COLOR_BLACK, COLOR_BLACK, true); + DLG_COLOR(dialog, COLOR_BLACK, COLOR_WHITE, false); + DLG_COLOR(title, COLOR_YELLOW, COLOR_WHITE, true); + DLG_COLOR(border, COLOR_WHITE, COLOR_WHITE, true); + DLG_COLOR(button_active, COLOR_WHITE, COLOR_BLUE, true); + DLG_COLOR(button_inactive, COLOR_BLACK, COLOR_WHITE, false); + DLG_COLOR(button_key_active, COLOR_WHITE, COLOR_BLUE, true); + DLG_COLOR(button_key_inactive, COLOR_RED, COLOR_WHITE, false); + DLG_COLOR(button_label_active, COLOR_YELLOW, COLOR_BLUE, true); + DLG_COLOR(button_label_inactive, COLOR_BLACK, COLOR_WHITE, true); + DLG_COLOR(inputbox, COLOR_BLACK, COLOR_WHITE, false); + DLG_COLOR(inputbox_border, COLOR_BLACK, COLOR_WHITE, false); + DLG_COLOR(searchbox, COLOR_BLACK, COLOR_WHITE, false); + DLG_COLOR(searchbox_title, COLOR_YELLOW, COLOR_WHITE, true); + DLG_COLOR(searchbox_border, COLOR_WHITE, COLOR_WHITE, true); + DLG_COLOR(position_indicator, COLOR_YELLOW, COLOR_WHITE, true); + DLG_COLOR(menubox, COLOR_BLACK, COLOR_WHITE, false); + DLG_COLOR(menubox_border, COLOR_WHITE, COLOR_WHITE, true); + DLG_COLOR(item, COLOR_BLACK, COLOR_WHITE, false); + DLG_COLOR(item_selected, COLOR_WHITE, COLOR_BLUE, true); + DLG_COLOR(tag, COLOR_YELLOW, COLOR_WHITE, true); + DLG_COLOR(tag_selected, COLOR_YELLOW, COLOR_BLUE, true); + DLG_COLOR(tag_key, COLOR_YELLOW, COLOR_WHITE, true); + DLG_COLOR(tag_key_selected, COLOR_YELLOW, COLOR_BLUE, true); + DLG_COLOR(check, COLOR_BLACK, COLOR_WHITE, false); + DLG_COLOR(check_selected, COLOR_WHITE, COLOR_BLUE, true); + DLG_COLOR(uarrow, COLOR_GREEN, COLOR_WHITE, true); + DLG_COLOR(darrow, COLOR_GREEN, COLOR_WHITE, true); +} + +static void set_blackbg_theme(void) +{ + DLG_COLOR(screen, COLOR_RED, COLOR_BLACK, true); + DLG_COLOR(shadow, COLOR_BLACK, COLOR_BLACK, false); + DLG_COLOR(dialog, COLOR_WHITE, COLOR_BLACK, false); + DLG_COLOR(title, COLOR_RED, COLOR_BLACK, false); + DLG_COLOR(border, COLOR_BLACK, COLOR_BLACK, true); + + DLG_COLOR(button_active, COLOR_YELLOW, COLOR_RED, false); + DLG_COLOR(button_inactive, COLOR_YELLOW, COLOR_BLACK, false); + DLG_COLOR(button_key_active, COLOR_YELLOW, COLOR_RED, true); + DLG_COLOR(button_key_inactive, COLOR_RED, COLOR_BLACK, false); + DLG_COLOR(button_label_active, COLOR_WHITE, COLOR_RED, false); + DLG_COLOR(button_label_inactive, COLOR_BLACK, COLOR_BLACK, true); + + DLG_COLOR(inputbox, COLOR_YELLOW, COLOR_BLACK, false); + DLG_COLOR(inputbox_border, COLOR_YELLOW, COLOR_BLACK, false); + + DLG_COLOR(searchbox, COLOR_YELLOW, COLOR_BLACK, false); + DLG_COLOR(searchbox_title, COLOR_YELLOW, COLOR_BLACK, true); + DLG_COLOR(searchbox_border, COLOR_BLACK, COLOR_BLACK, true); + + DLG_COLOR(position_indicator, COLOR_RED, COLOR_BLACK, false); + + DLG_COLOR(menubox, COLOR_YELLOW, COLOR_BLACK, false); + DLG_COLOR(menubox_border, COLOR_BLACK, COLOR_BLACK, true); + + DLG_COLOR(item, COLOR_WHITE, COLOR_BLACK, false); + DLG_COLOR(item_selected, COLOR_WHITE, COLOR_RED, false); + + DLG_COLOR(tag, COLOR_RED, COLOR_BLACK, false); + DLG_COLOR(tag_selected, COLOR_YELLOW, COLOR_RED, true); + DLG_COLOR(tag_key, COLOR_RED, COLOR_BLACK, false); + DLG_COLOR(tag_key_selected, COLOR_YELLOW, COLOR_RED, true); + + DLG_COLOR(check, COLOR_YELLOW, COLOR_BLACK, false); + DLG_COLOR(check_selected, COLOR_YELLOW, COLOR_RED, true); + + DLG_COLOR(uarrow, COLOR_RED, COLOR_BLACK, false); + DLG_COLOR(darrow, COLOR_RED, COLOR_BLACK, false); +} + +static void set_bluetitle_theme(void) +{ + set_classic_theme(); + DLG_COLOR(title, COLOR_BLUE, COLOR_WHITE, true); + DLG_COLOR(button_key_active, COLOR_YELLOW, COLOR_BLUE, true); + DLG_COLOR(button_label_active, COLOR_WHITE, COLOR_BLUE, true); + DLG_COLOR(searchbox_title, COLOR_BLUE, COLOR_WHITE, true); + DLG_COLOR(position_indicator, COLOR_BLUE, COLOR_WHITE, true); + DLG_COLOR(tag, COLOR_BLUE, COLOR_WHITE, true); + DLG_COLOR(tag_key, COLOR_BLUE, COLOR_WHITE, true); + +} + +/* + * Select color theme + */ +static int set_theme(const char *theme) +{ + int use_color = 1; + if (!theme) + set_bluetitle_theme(); + else if (strcmp(theme, "classic") == 0) + set_classic_theme(); + else if (strcmp(theme, "bluetitle") == 0) + set_bluetitle_theme(); + else if (strcmp(theme, "blackbg") == 0) + set_blackbg_theme(); + else if (strcmp(theme, "mono") == 0) + use_color = 0; + + return use_color; +} + +static void init_one_color(struct dialog_color *color) +{ + static int pair = 0; + + pair++; + init_pair(pair, color->fg, color->bg); + if (color->hl) + color->atr = A_BOLD | COLOR_PAIR(pair); + else + color->atr = COLOR_PAIR(pair); +} + +static void init_dialog_colors(void) +{ + init_one_color(&dlg.screen); + init_one_color(&dlg.shadow); + init_one_color(&dlg.dialog); + init_one_color(&dlg.title); + init_one_color(&dlg.border); + init_one_color(&dlg.button_active); + init_one_color(&dlg.button_inactive); + init_one_color(&dlg.button_key_active); + init_one_color(&dlg.button_key_inactive); + init_one_color(&dlg.button_label_active); + init_one_color(&dlg.button_label_inactive); + init_one_color(&dlg.inputbox); + init_one_color(&dlg.inputbox_border); + init_one_color(&dlg.searchbox); + init_one_color(&dlg.searchbox_title); + init_one_color(&dlg.searchbox_border); + init_one_color(&dlg.position_indicator); + init_one_color(&dlg.menubox); + init_one_color(&dlg.menubox_border); + init_one_color(&dlg.item); + init_one_color(&dlg.item_selected); + init_one_color(&dlg.tag); + init_one_color(&dlg.tag_selected); + init_one_color(&dlg.tag_key); + init_one_color(&dlg.tag_key_selected); + init_one_color(&dlg.check); + init_one_color(&dlg.check_selected); + init_one_color(&dlg.uarrow); + init_one_color(&dlg.darrow); +} + +/* + * Setup for color display + */ +static void color_setup(const char *theme) +{ + int use_color; + + use_color = set_theme(theme); + if (use_color && has_colors()) { + start_color(); + init_dialog_colors(); + } else + set_mono_theme(); +} + +/* + * Set window to attribute 'attr' + */ +void attr_clear(WINDOW * win, int height, int width, chtype attr) +{ + int i, j; + + wattrset(win, attr); + for (i = 0; i < height; i++) { + wmove(win, i, 0); + for (j = 0; j < width; j++) + waddch(win, ' '); + } + touchwin(win); +} + +void dialog_clear(void) +{ + int lines, columns; + + lines = getmaxy(stdscr); + columns = getmaxx(stdscr); + + attr_clear(stdscr, lines, columns, dlg.screen.atr); + /* Display background title if it exists ... - SLH */ + if (dlg.backtitle != NULL) { + int i, len = 0, skip = 0; + struct subtitle_list *pos; + + wattrset(stdscr, dlg.screen.atr); + mvwaddstr(stdscr, 0, 1, (char *)dlg.backtitle); + + for (pos = dlg.subtitles; pos != NULL; pos = pos->next) { + /* 3 is for the arrow and spaces */ + len += strlen(pos->text) + 3; + } + + wmove(stdscr, 1, 1); + if (len > columns - 2) { + const char *ellipsis = "[...] "; + waddstr(stdscr, ellipsis); + skip = len - (columns - 2 - strlen(ellipsis)); + } + + for (pos = dlg.subtitles; pos != NULL; pos = pos->next) { + if (skip == 0) + waddch(stdscr, ACS_RARROW); + else + skip--; + + if (skip == 0) + waddch(stdscr, ' '); + else + skip--; + + if (skip < strlen(pos->text)) { + waddstr(stdscr, pos->text + skip); + skip = 0; + } else + skip -= strlen(pos->text); + + if (skip == 0) + waddch(stdscr, ' '); + else + skip--; + } + + for (i = len + 1; i < columns - 1; i++) + waddch(stdscr, ACS_HLINE); + } + wnoutrefresh(stdscr); +} + +/* + * Do some initialization for dialog + */ +int init_dialog(const char *backtitle) +{ + int height, width; + + initscr(); /* Init curses */ + + /* Get current cursor position for signal handler in mconf.c */ + getyx(stdscr, saved_y, saved_x); + + getmaxyx(stdscr, height, width); + if (height < WINDOW_HEIGTH_MIN || width < WINDOW_WIDTH_MIN) { + endwin(); + return -ERRDISPLAYTOOSMALL; + } + + dlg.backtitle = backtitle; + color_setup(getenv("MENUCONFIG_COLOR")); + + keypad(stdscr, TRUE); + cbreak(); + noecho(); + dialog_clear(); + + return 0; +} + +void set_dialog_backtitle(const char *backtitle) +{ + dlg.backtitle = backtitle; +} + +void set_dialog_subtitles(struct subtitle_list *subtitles) +{ + dlg.subtitles = subtitles; +} + +/* + * End using dialog functions. + */ +void end_dialog(int x, int y) +{ + /* move cursor back to original position */ + move(y, x); + refresh(); + endwin(); +} + +/* Print the title of the dialog. Center the title and truncate + * tile if wider than dialog (- 2 chars). + **/ +void print_title(WINDOW *dialog, const char *title, int width) +{ + if (title) { + int tlen = MIN(width - 2, strlen(title)); + wattrset(dialog, dlg.title.atr); + mvwaddch(dialog, 0, (width - tlen) / 2 - 1, ' '); + mvwaddnstr(dialog, 0, (width - tlen)/2, title, tlen); + waddch(dialog, ' '); + } +} + +/* + * Print a string of text in a window, automatically wrap around to the + * next line if the string is too long to fit on one line. Newline + * characters '\n' are propperly processed. We start on a new line + * if there is no room for at least 4 nonblanks following a double-space. + */ +void print_autowrap(WINDOW * win, const char *prompt, int width, int y, int x) +{ + int newl, cur_x, cur_y; + int prompt_len, room, wlen; + char tempstr[MAX_LEN + 1], *word, *sp, *sp2, *newline_separator = 0; + + strcpy(tempstr, prompt); + + prompt_len = strlen(tempstr); + + if (prompt_len <= width - x * 2) { /* If prompt is short */ + wmove(win, y, (width - prompt_len) / 2); + waddstr(win, tempstr); + } else { + cur_x = x; + cur_y = y; + newl = 1; + word = tempstr; + while (word && *word) { + sp = strpbrk(word, "\n "); + if (sp && *sp == '\n') + newline_separator = sp; + + if (sp) + *sp++ = 0; + + /* Wrap to next line if either the word does not fit, + or it is the first word of a new sentence, and it is + short, and the next word does not fit. */ + room = width - cur_x; + wlen = strlen(word); + if (wlen > room || + (newl && wlen < 4 && sp + && wlen + 1 + strlen(sp) > room + && (!(sp2 = strpbrk(sp, "\n ")) + || wlen + 1 + (sp2 - sp) > room))) { + cur_y++; + cur_x = x; + } + wmove(win, cur_y, cur_x); + waddstr(win, word); + getyx(win, cur_y, cur_x); + + /* Move to the next line if the word separator was a newline */ + if (newline_separator) { + cur_y++; + cur_x = x; + newline_separator = 0; + } else + cur_x++; + + if (sp && *sp == ' ') { + cur_x++; /* double space */ + while (*++sp == ' ') ; + newl = 1; + } else + newl = 0; + word = sp; + } + } +} + +/* + * Print a button + */ +void print_button(WINDOW * win, const char *label, int y, int x, int selected) +{ + int i, temp; + + wmove(win, y, x); + wattrset(win, selected ? dlg.button_active.atr + : dlg.button_inactive.atr); + waddstr(win, "<"); + temp = strspn(label, " "); + label += temp; + wattrset(win, selected ? dlg.button_label_active.atr + : dlg.button_label_inactive.atr); + for (i = 0; i < temp; i++) + waddch(win, ' '); + wattrset(win, selected ? dlg.button_key_active.atr + : dlg.button_key_inactive.atr); + waddch(win, label[0]); + wattrset(win, selected ? dlg.button_label_active.atr + : dlg.button_label_inactive.atr); + waddstr(win, (char *)label + 1); + wattrset(win, selected ? dlg.button_active.atr + : dlg.button_inactive.atr); + waddstr(win, ">"); + wmove(win, y, x + temp + 1); +} + +/* + * Draw a rectangular box with line drawing characters + */ +void +draw_box(WINDOW * win, int y, int x, int height, int width, + chtype box, chtype border) +{ + int i, j; + + wattrset(win, 0); + for (i = 0; i < height; i++) { + wmove(win, y + i, x); + for (j = 0; j < width; j++) + if (!i && !j) + waddch(win, border | ACS_ULCORNER); + else if (i == height - 1 && !j) + waddch(win, border | ACS_LLCORNER); + else if (!i && j == width - 1) + waddch(win, box | ACS_URCORNER); + else if (i == height - 1 && j == width - 1) + waddch(win, box | ACS_LRCORNER); + else if (!i) + waddch(win, border | ACS_HLINE); + else if (i == height - 1) + waddch(win, box | ACS_HLINE); + else if (!j) + waddch(win, border | ACS_VLINE); + else if (j == width - 1) + waddch(win, box | ACS_VLINE); + else + waddch(win, box | ' '); + } +} + +/* + * Draw shadows along the right and bottom edge to give a more 3D look + * to the boxes + */ +void draw_shadow(WINDOW * win, int y, int x, int height, int width) +{ + int i; + + if (has_colors()) { /* Whether terminal supports color? */ + wattrset(win, dlg.shadow.atr); + wmove(win, y + height, x + 2); + for (i = 0; i < width; i++) + waddch(win, winch(win) & A_CHARTEXT); + for (i = y + 1; i < y + height + 1; i++) { + wmove(win, i, x + width); + waddch(win, winch(win) & A_CHARTEXT); + waddch(win, winch(win) & A_CHARTEXT); + } + wnoutrefresh(win); + } +} + +/* + * Return the position of the first alphabetic character in a string. + */ +int first_alpha(const char *string, const char *exempt) +{ + int i, in_paren = 0, c; + + for (i = 0; i < strlen(string); i++) { + c = tolower(string[i]); + + if (strchr("<[(", c)) + ++in_paren; + if (strchr(">])", c) && in_paren > 0) + --in_paren; + + if ((!in_paren) && isalpha(c) && strchr(exempt, c) == 0) + return i; + } + + return 0; +} + +/* + * ncurses uses ESC to detect escaped char sequences. This resutl in + * a small timeout before ESC is actually delivered to the application. + * lxdialog suggest <ESC> <ESC> which is correctly translated to two + * times esc. But then we need to ignore the second esc to avoid stepping + * out one menu too much. Filter away all escaped key sequences since + * keypad(FALSE) turn off ncurses support for escape sequences - and thats + * needed to make notimeout() do as expected. + */ +int on_key_esc(WINDOW *win) +{ + int key; + int key2; + int key3; + + nodelay(win, TRUE); + keypad(win, FALSE); + key = wgetch(win); + key2 = wgetch(win); + do { + key3 = wgetch(win); + } while (key3 != ERR); + nodelay(win, FALSE); + keypad(win, TRUE); + if (key == KEY_ESC && key2 == ERR) + return KEY_ESC; + else if (key != ERR && key != KEY_ESC && key2 == ERR) + ungetch(key); + + return -1; +} + +/* redraw screen in new size */ +int on_key_resize(void) +{ + dialog_clear(); + return KEY_RESIZE; +} + +struct dialog_list *item_cur; +struct dialog_list item_nil; +struct dialog_list *item_head; + +void item_reset(void) +{ + struct dialog_list *p, *next; + + for (p = item_head; p; p = next) { + next = p->next; + free(p); + } + item_head = NULL; + item_cur = &item_nil; +} + +void item_make(const char *fmt, ...) +{ + va_list ap; + struct dialog_list *p = malloc(sizeof(*p)); + + if (item_head) + item_cur->next = p; + else + item_head = p; + item_cur = p; + memset(p, 0, sizeof(*p)); + + va_start(ap, fmt); + vsnprintf(item_cur->node.str, sizeof(item_cur->node.str), fmt, ap); + va_end(ap); +} + +void item_add_str(const char *fmt, ...) +{ + va_list ap; + size_t avail; + + avail = sizeof(item_cur->node.str) - strlen(item_cur->node.str); + + va_start(ap, fmt); + vsnprintf(item_cur->node.str + strlen(item_cur->node.str), + avail, fmt, ap); + item_cur->node.str[sizeof(item_cur->node.str) - 1] = '\0'; + va_end(ap); +} + +void item_set_tag(char tag) +{ + item_cur->node.tag = tag; +} +void item_set_data(void *ptr) +{ + item_cur->node.data = ptr; +} + +void item_set_selected(int val) +{ + item_cur->node.selected = val; +} + +int item_activate_selected(void) +{ + item_foreach() + if (item_is_selected()) + return 1; + return 0; +} + +void *item_data(void) +{ + return item_cur->node.data; +} + +char item_tag(void) +{ + return item_cur->node.tag; +} + +int item_count(void) +{ + int n = 0; + struct dialog_list *p; + + for (p = item_head; p; p = p->next) + n++; + return n; +} + +void item_set(int n) +{ + int i = 0; + item_foreach() + if (i++ == n) + return; +} + +int item_n(void) +{ + int n = 0; + struct dialog_list *p; + + for (p = item_head; p; p = p->next) { + if (p == item_cur) + return n; + n++; + } + return 0; +} + +const char *item_str(void) +{ + return item_cur->node.str; +} + +int item_is_selected(void) +{ + return (item_cur->node.selected != 0); +} + +int item_is_tag(char tag) +{ + return (item_cur->node.tag == tag); +} diff --git a/src/net/scripts/kconfig/lxdialog/yesno.c b/src/net/scripts/kconfig/lxdialog/yesno.c new file mode 100644 index 0000000..bcaac9b --- /dev/null +++ b/src/net/scripts/kconfig/lxdialog/yesno.c @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * yesno.c -- implements the yes/no box + * + * ORIGINAL AUTHOR: Savio Lam (lam836@cs.cuhk.hk) + * MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcap@cfw.com) + */ + +#include "dialog.h" + +/* + * Display termination buttons + */ +static void print_buttons(WINDOW * dialog, int height, int width, int selected) +{ + int x = width / 2 - 10; + int y = height - 2; + + print_button(dialog, " Yes ", y, x, selected == 0); + print_button(dialog, " No ", y, x + 13, selected == 1); + + wmove(dialog, y, x + 1 + 13 * selected); + wrefresh(dialog); +} + +/* + * Display a dialog box with two buttons - Yes and No + */ +int dialog_yesno(const char *title, const char *prompt, int height, int width) +{ + int i, x, y, key = 0, button = 0; + WINDOW *dialog; + +do_resize: + if (getmaxy(stdscr) < (height + YESNO_HEIGTH_MIN)) + return -ERRDISPLAYTOOSMALL; + if (getmaxx(stdscr) < (width + YESNO_WIDTH_MIN)) + return -ERRDISPLAYTOOSMALL; + + /* center dialog box on screen */ + x = (getmaxx(stdscr) - width) / 2; + y = (getmaxy(stdscr) - height) / 2; + + draw_shadow(stdscr, y, x, height, width); + + dialog = newwin(height, width, y, x); + keypad(dialog, TRUE); + + draw_box(dialog, 0, 0, height, width, + dlg.dialog.atr, dlg.border.atr); + wattrset(dialog, dlg.border.atr); + mvwaddch(dialog, height - 3, 0, ACS_LTEE); + for (i = 0; i < width - 2; i++) + waddch(dialog, ACS_HLINE); + wattrset(dialog, dlg.dialog.atr); + waddch(dialog, ACS_RTEE); + + print_title(dialog, title, width); + + wattrset(dialog, dlg.dialog.atr); + print_autowrap(dialog, prompt, width - 2, 1, 3); + + print_buttons(dialog, height, width, 0); + + while (key != KEY_ESC) { + key = wgetch(dialog); + switch (key) { + case 'Y': + case 'y': + delwin(dialog); + return 0; + case 'N': + case 'n': + delwin(dialog); + return 1; + + case TAB: + case KEY_LEFT: + case KEY_RIGHT: + button = ((key == KEY_LEFT ? --button : ++button) < 0) ? 1 : (button > 1 ? 0 : button); + + print_buttons(dialog, height, width, button); + wrefresh(dialog); + break; + case ' ': + case '\n': + delwin(dialog); + return button; + case KEY_ESC: + key = on_key_esc(dialog); + break; + case KEY_RESIZE: + delwin(dialog); + on_key_resize(); + goto do_resize; + } + } + + delwin(dialog); + return key; /* ESC pressed */ +} diff --git a/src/net/scripts/kconfig/mconf-cfg.sh b/src/net/scripts/kconfig/mconf-cfg.sh new file mode 100755 index 0000000..aa68ec9 --- /dev/null +++ b/src/net/scripts/kconfig/mconf-cfg.sh @@ -0,0 +1,50 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0 + +PKG="ncursesw" +PKG2="ncurses" + +if [ -n "$(command -v pkg-config)" ]; then + if pkg-config --exists $PKG; then + echo cflags=\"$(pkg-config --cflags $PKG)\" + echo libs=\"$(pkg-config --libs $PKG)\" + exit 0 + fi + + if pkg-config --exists $PKG2; then + echo cflags=\"$(pkg-config --cflags $PKG2)\" + echo libs=\"$(pkg-config --libs $PKG2)\" + exit 0 + fi +fi + +# Check the default paths in case pkg-config is not installed. +# (Even if it is installed, some distributions such as openSUSE cannot +# find ncurses by pkg-config.) +if [ -f /usr/include/ncursesw/ncurses.h ]; then + echo cflags=\"-D_GNU_SOURCE -I/usr/include/ncursesw\" + echo libs=\"-lncursesw\" + exit 0 +fi + +if [ -f /usr/include/ncurses/ncurses.h ]; then + echo cflags=\"-D_GNU_SOURCE -I/usr/include/ncurses\" + echo libs=\"-lncurses\" + exit 0 +fi + +if [ -f /usr/include/ncurses.h ]; then + echo cflags=\"-D_GNU_SOURCE\" + echo libs=\"-lncurses\" + exit 0 +fi + +echo >&2 "*" +echo >&2 "* Unable to find the ncurses package." +echo >&2 "* Install ncurses (ncurses-devel or libncurses-dev" +echo >&2 "* depending on your distribution)." +echo >&2 "*" +echo >&2 "* You may also need to install pkg-config to find the" +echo >&2 "* ncurses installed in a non-default location." +echo >&2 "*" +exit 1 diff --git a/src/net/scripts/kconfig/mconf.c b/src/net/scripts/kconfig/mconf.c new file mode 100644 index 0000000..4063dbc --- /dev/null +++ b/src/net/scripts/kconfig/mconf.c @@ -0,0 +1,1040 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2002 Roman Zippel <zippel@linux-m68k.org> + * + * Introduced single menu mode (show all sub-menus in one large tree). + * 2002-11-06 Petr Baudis <pasky@ucw.cz> + * + * i18n, 2005, Arnaldo Carvalho de Melo <acme@conectiva.com.br> + */ + +#include <ctype.h> +#include <errno.h> +#include <fcntl.h> +#include <limits.h> +#include <stdarg.h> +#include <stdlib.h> +#include <string.h> +#include <strings.h> +#include <signal.h> +#include <unistd.h> + +#include "lkc.h" +#include "lxdialog/dialog.h" + +static const char mconf_readme[] = +"Overview\n" +"--------\n" +"This interface lets you select features and parameters for the build.\n" +"Features can either be built-in, modularized, or ignored. Parameters\n" +"must be entered in as decimal or hexadecimal numbers or text.\n" +"\n" +"Menu items beginning with following braces represent features that\n" +" [ ] can be built in or removed\n" +" < > can be built in, modularized or removed\n" +" { } can be built in or modularized (selected by other feature)\n" +" - - are selected by other feature,\n" +"while *, M or whitespace inside braces means to build in, build as\n" +"a module or to exclude the feature respectively.\n" +"\n" +"To change any of these features, highlight it with the cursor\n" +"keys and press <Y> to build it in, <M> to make it a module or\n" +"<N> to remove it. You may also press the <Space Bar> to cycle\n" +"through the available options (i.e. Y->N->M->Y).\n" +"\n" +"Some additional keyboard hints:\n" +"\n" +"Menus\n" +"----------\n" +"o Use the Up/Down arrow keys (cursor keys) to highlight the item you\n" +" wish to change or the submenu you wish to select and press <Enter>.\n" +" Submenus are designated by \"--->\", empty ones by \"----\".\n" +"\n" +" Shortcut: Press the option's highlighted letter (hotkey).\n" +" Pressing a hotkey more than once will sequence\n" +" through all visible items which use that hotkey.\n" +"\n" +" You may also use the <PAGE UP> and <PAGE DOWN> keys to scroll\n" +" unseen options into view.\n" +"\n" +"o To exit a menu use the cursor keys to highlight the <Exit> button\n" +" and press <ENTER>.\n" +"\n" +" Shortcut: Press <ESC><ESC> or <E> or <X> if there is no hotkey\n" +" using those letters. You may press a single <ESC>, but\n" +" there is a delayed response which you may find annoying.\n" +"\n" +" Also, the <TAB> and cursor keys will cycle between <Select>,\n" +" <Exit>, <Help>, <Save>, and <Load>.\n" +"\n" +"o To get help with an item, use the cursor keys to highlight <Help>\n" +" and press <ENTER>.\n" +"\n" +" Shortcut: Press <H> or <?>.\n" +"\n" +"o To toggle the display of hidden options, press <Z>.\n" +"\n" +"\n" +"Radiolists (Choice lists)\n" +"-----------\n" +"o Use the cursor keys to select the option you wish to set and press\n" +" <S> or the <SPACE BAR>.\n" +"\n" +" Shortcut: Press the first letter of the option you wish to set then\n" +" press <S> or <SPACE BAR>.\n" +"\n" +"o To see available help for the item, use the cursor keys to highlight\n" +" <Help> and Press <ENTER>.\n" +"\n" +" Shortcut: Press <H> or <?>.\n" +"\n" +" Also, the <TAB> and cursor keys will cycle between <Select> and\n" +" <Help>\n" +"\n" +"\n" +"Data Entry\n" +"-----------\n" +"o Enter the requested information and press <ENTER>\n" +" If you are entering hexadecimal values, it is not necessary to\n" +" add the '0x' prefix to the entry.\n" +"\n" +"o For help, use the <TAB> or cursor keys to highlight the help option\n" +" and press <ENTER>. You can try <TAB><H> as well.\n" +"\n" +"\n" +"Text Box (Help Window)\n" +"--------\n" +"o Use the cursor keys to scroll up/down/left/right. The VI editor\n" +" keys h,j,k,l function here as do <u>, <d>, <SPACE BAR> and <B> for\n" +" those who are familiar with less and lynx.\n" +"\n" +"o Press <E>, <X>, <q>, <Enter> or <Esc><Esc> to exit.\n" +"\n" +"\n" +"Alternate Configuration Files\n" +"-----------------------------\n" +"Menuconfig supports the use of alternate configuration files for\n" +"those who, for various reasons, find it necessary to switch\n" +"between different configurations.\n" +"\n" +"The <Save> button will let you save the current configuration to\n" +"a file of your choosing. Use the <Load> button to load a previously\n" +"saved alternate configuration.\n" +"\n" +"Even if you don't use alternate configuration files, but you find\n" +"during a Menuconfig session that you have completely messed up your\n" +"settings, you may use the <Load> button to restore your previously\n" +"saved settings from \".config\" without restarting Menuconfig.\n" +"\n" +"Other information\n" +"-----------------\n" +"If you use Menuconfig in an XTERM window, make sure you have your\n" +"$TERM variable set to point to an xterm definition which supports\n" +"color. Otherwise, Menuconfig will look rather bad. Menuconfig will\n" +"not display correctly in an RXVT window because rxvt displays only one\n" +"intensity of color, bright.\n" +"\n" +"Menuconfig will display larger menus on screens or xterms which are\n" +"set to display more than the standard 25 row by 80 column geometry.\n" +"In order for this to work, the \"stty size\" command must be able to\n" +"display the screen's current row and column geometry. I STRONGLY\n" +"RECOMMEND that you make sure you do NOT have the shell variables\n" +"LINES and COLUMNS exported into your environment. Some distributions\n" +"export those variables via /etc/profile. Some ncurses programs can\n" +"become confused when those variables (LINES & COLUMNS) don't reflect\n" +"the true screen size.\n" +"\n" +"Optional personality available\n" +"------------------------------\n" +"If you prefer to have all of the options listed in a single menu,\n" +"rather than the default multimenu hierarchy, run the menuconfig with\n" +"MENUCONFIG_MODE environment variable set to single_menu. Example:\n" +"\n" +"make MENUCONFIG_MODE=single_menu menuconfig\n" +"\n" +"<Enter> will then unroll the appropriate category, or enfold it if it\n" +"is already unrolled.\n" +"\n" +"Note that this mode can eventually be a little more CPU expensive\n" +"(especially with a larger number of unrolled categories) than the\n" +"default mode.\n" +"\n" +"Different color themes available\n" +"--------------------------------\n" +"It is possible to select different color themes using the variable\n" +"MENUCONFIG_COLOR. To select a theme use:\n" +"\n" +"make MENUCONFIG_COLOR=<theme> menuconfig\n" +"\n" +"Available themes are\n" +" mono => selects colors suitable for monochrome displays\n" +" blackbg => selects a color scheme with black background\n" +" classic => theme with blue background. The classic look\n" +" bluetitle => an LCD friendly version of classic. (default)\n" +"\n", +menu_instructions[] = + "Arrow keys navigate the menu. " + "<Enter> selects submenus ---> (or empty submenus ----). " + "Highlighted letters are hotkeys. " + "Pressing <Y> includes, <N> excludes, <M> modularizes features. " + "Press <Esc><Esc> to exit, <?> for Help, </> for Search. " + "Legend: [*] built-in [ ] excluded <M> module < > module capable", +radiolist_instructions[] = + "Use the arrow keys to navigate this window or " + "press the hotkey of the item you wish to select " + "followed by the <SPACE BAR>. " + "Press <?> for additional information about this option.", +inputbox_instructions_int[] = + "Please enter a decimal value. " + "Fractions will not be accepted. " + "Use the <TAB> key to move from the input field to the buttons below it.", +inputbox_instructions_hex[] = + "Please enter a hexadecimal value. " + "Use the <TAB> key to move from the input field to the buttons below it.", +inputbox_instructions_string[] = + "Please enter a string value. " + "Use the <TAB> key to move from the input field to the buttons below it.", +setmod_text[] = + "This feature depends on another which has been configured as a module.\n" + "As a result, this feature will be built as a module.", +load_config_text[] = + "Enter the name of the configuration file you wish to load. " + "Accept the name shown to restore the configuration you " + "last retrieved. Leave blank to abort.", +load_config_help[] = + "\n" + "For various reasons, one may wish to keep several different\n" + "configurations available on a single machine.\n" + "\n" + "If you have saved a previous configuration in a file other than the\n" + "default one, entering its name here will allow you to modify that\n" + "configuration.\n" + "\n" + "If you are uncertain, then you have probably never used alternate\n" + "configuration files. You should therefore leave this blank to abort.\n", +save_config_text[] = + "Enter a filename to which this configuration should be saved " + "as an alternate. Leave blank to abort.", +save_config_help[] = + "\n" + "For various reasons, one may wish to keep different configurations\n" + "available on a single machine.\n" + "\n" + "Entering a file name here will allow you to later retrieve, modify\n" + "and use the current configuration as an alternate to whatever\n" + "configuration options you have selected at that time.\n" + "\n" + "If you are uncertain what all this means then you should probably\n" + "leave this blank.\n", +search_help[] = + "\n" + "Search for symbols and display their relations.\n" + "Regular expressions are allowed.\n" + "Example: search for \"^FOO\"\n" + "Result:\n" + "-----------------------------------------------------------------\n" + "Symbol: FOO [=m]\n" + "Type : tristate\n" + "Prompt: Foo bus is used to drive the bar HW\n" + " Location:\n" + " -> Bus options (PCI, PCMCIA, EISA, ISA)\n" + " -> PCI support (PCI [=y])\n" + "(1) -> PCI access mode (<choice> [=y])\n" + " Defined at drivers/pci/Kconfig:47\n" + " Depends on: X86_LOCAL_APIC && X86_IO_APIC || IA64\n" + " Selects: LIBCRC32\n" + " Selected by: BAR [=n]\n" + "-----------------------------------------------------------------\n" + "o The line 'Type:' shows the type of the configuration option for\n" + " this symbol (bool, tristate, string, ...)\n" + "o The line 'Prompt:' shows the text used in the menu structure for\n" + " this symbol\n" + "o The 'Defined at' line tells at what file / line number the symbol\n" + " is defined\n" + "o The 'Depends on:' line tells what symbols need to be defined for\n" + " this symbol to be visible in the menu (selectable)\n" + "o The 'Location:' lines tells where in the menu structure this symbol\n" + " is located\n" + " A location followed by a [=y] indicates that this is a\n" + " selectable menu item - and the current value is displayed inside\n" + " brackets.\n" + " Press the key in the (#) prefix to jump directly to that\n" + " location. You will be returned to the current search results\n" + " after exiting this new menu.\n" + "o The 'Selects:' line tells what symbols will be automatically\n" + " selected if this symbol is selected (y or m)\n" + "o The 'Selected by' line tells what symbol has selected this symbol\n" + "\n" + "Only relevant lines are shown.\n" + "\n\n" + "Search examples:\n" + "Examples: USB => find all symbols containing USB\n" + " ^USB => find all symbols starting with USB\n" + " USB$ => find all symbols ending with USB\n" + "\n"; + +static int indent; +static struct menu *current_menu; +static int child_count; +static int single_menu_mode; +static int show_all_options; +static int save_and_exit; +static int silent; + +static void conf(struct menu *menu, struct menu *active_menu); +static void conf_choice(struct menu *menu); +static void conf_string(struct menu *menu); +static void conf_load(void); +static void conf_save(void); +static int show_textbox_ext(const char *title, char *text, int r, int c, + int *keys, int *vscroll, int *hscroll, + update_text_fn update_text, void *data); +static void show_textbox(const char *title, const char *text, int r, int c); +static void show_helptext(const char *title, const char *text); +static void show_help(struct menu *menu); + +static char filename[PATH_MAX+1]; +static void set_config_filename(const char *config_filename) +{ + static char menu_backtitle[PATH_MAX+128]; + int size; + + size = snprintf(menu_backtitle, sizeof(menu_backtitle), + "%s - %s", config_filename, rootmenu.prompt->text); + if (size >= sizeof(menu_backtitle)) + menu_backtitle[sizeof(menu_backtitle)-1] = '\0'; + set_dialog_backtitle(menu_backtitle); + + size = snprintf(filename, sizeof(filename), "%s", config_filename); + if (size >= sizeof(filename)) + filename[sizeof(filename)-1] = '\0'; +} + +struct subtitle_part { + struct list_head entries; + const char *text; +}; +static LIST_HEAD(trail); + +static struct subtitle_list *subtitles; +static void set_subtitle(void) +{ + struct subtitle_part *sp; + struct subtitle_list *pos, *tmp; + + for (pos = subtitles; pos != NULL; pos = tmp) { + tmp = pos->next; + free(pos); + } + + subtitles = NULL; + list_for_each_entry(sp, &trail, entries) { + if (sp->text) { + if (pos) { + pos->next = xcalloc(1, sizeof(*pos)); + pos = pos->next; + } else { + subtitles = pos = xcalloc(1, sizeof(*pos)); + } + pos->text = sp->text; + } + } + + set_dialog_subtitles(subtitles); +} + +static void reset_subtitle(void) +{ + struct subtitle_list *pos, *tmp; + + for (pos = subtitles; pos != NULL; pos = tmp) { + tmp = pos->next; + free(pos); + } + subtitles = NULL; + set_dialog_subtitles(subtitles); +} + +struct search_data { + struct list_head *head; + struct menu **targets; + int *keys; +}; + +static void update_text(char *buf, size_t start, size_t end, void *_data) +{ + struct search_data *data = _data; + struct jump_key *pos; + int k = 0; + + list_for_each_entry(pos, data->head, entries) { + if (pos->offset >= start && pos->offset < end) { + char header[4]; + + if (k < JUMP_NB) { + int key = '0' + (pos->index % JUMP_NB) + 1; + + sprintf(header, "(%c)", key); + data->keys[k] = key; + data->targets[k] = pos->target; + k++; + } else { + sprintf(header, " "); + } + + memcpy(buf + pos->offset, header, sizeof(header) - 1); + } + } + data->keys[k] = 0; +} + +static void search_conf(void) +{ + struct symbol **sym_arr; + struct gstr res; + struct gstr title; + char *dialog_input; + int dres, vscroll = 0, hscroll = 0; + bool again; + struct gstr sttext; + struct subtitle_part stpart; + + title = str_new(); + str_printf( &title, "Enter (sub)string or regexp to search for " + "(with or without \"%s\")", CONFIG_); + +again: + dialog_clear(); + dres = dialog_inputbox("Search Configuration Parameter", + str_get(&title), + 10, 75, ""); + switch (dres) { + case 0: + break; + case 1: + show_helptext("Search Configuration", search_help); + goto again; + default: + str_free(&title); + return; + } + + /* strip the prefix if necessary */ + dialog_input = dialog_input_result; + if (strncasecmp(dialog_input_result, CONFIG_, strlen(CONFIG_)) == 0) + dialog_input += strlen(CONFIG_); + + sttext = str_new(); + str_printf(&sttext, "Search (%s)", dialog_input_result); + stpart.text = str_get(&sttext); + list_add_tail(&stpart.entries, &trail); + + sym_arr = sym_re_search(dialog_input); + do { + LIST_HEAD(head); + struct menu *targets[JUMP_NB]; + int keys[JUMP_NB + 1], i; + struct search_data data = { + .head = &head, + .targets = targets, + .keys = keys, + }; + struct jump_key *pos, *tmp; + + res = get_relations_str(sym_arr, &head); + set_subtitle(); + dres = show_textbox_ext("Search Results", (char *) + str_get(&res), 0, 0, keys, &vscroll, + &hscroll, &update_text, (void *) + &data); + again = false; + for (i = 0; i < JUMP_NB && keys[i]; i++) + if (dres == keys[i]) { + conf(targets[i]->parent, targets[i]); + again = true; + } + str_free(&res); + list_for_each_entry_safe(pos, tmp, &head, entries) + free(pos); + } while (again); + free(sym_arr); + str_free(&title); + list_del(trail.prev); + str_free(&sttext); +} + +static void build_conf(struct menu *menu) +{ + struct symbol *sym; + struct property *prop; + struct menu *child; + int type, tmp, doint = 2; + tristate val; + char ch; + bool visible; + + /* + * note: menu_is_visible() has side effect that it will + * recalc the value of the symbol. + */ + visible = menu_is_visible(menu); + if (show_all_options && !menu_has_prompt(menu)) + return; + else if (!show_all_options && !visible) + return; + + sym = menu->sym; + prop = menu->prompt; + if (!sym) { + if (prop && menu != current_menu) { + const char *prompt = menu_get_prompt(menu); + switch (prop->type) { + case P_MENU: + child_count++; + if (single_menu_mode) { + item_make("%s%*c%s", + menu->data ? "-->" : "++>", + indent + 1, ' ', prompt); + } else + item_make(" %*c%s %s", + indent + 1, ' ', prompt, + menu_is_empty(menu) ? "----" : "--->"); + item_set_tag('m'); + item_set_data(menu); + if (single_menu_mode && menu->data) + goto conf_childs; + return; + case P_COMMENT: + if (prompt) { + child_count++; + item_make(" %*c*** %s ***", indent + 1, ' ', prompt); + item_set_tag(':'); + item_set_data(menu); + } + break; + default: + if (prompt) { + child_count++; + item_make("---%*c%s", indent + 1, ' ', prompt); + item_set_tag(':'); + item_set_data(menu); + } + } + } else + doint = 0; + goto conf_childs; + } + + type = sym_get_type(sym); + if (sym_is_choice(sym)) { + struct symbol *def_sym = sym_get_choice_value(sym); + struct menu *def_menu = NULL; + + child_count++; + for (child = menu->list; child; child = child->next) { + if (menu_is_visible(child) && child->sym == def_sym) + def_menu = child; + } + + val = sym_get_tristate_value(sym); + if (sym_is_changeable(sym)) { + switch (type) { + case S_BOOLEAN: + item_make("[%c]", val == no ? ' ' : '*'); + break; + case S_TRISTATE: + switch (val) { + case yes: ch = '*'; break; + case mod: ch = 'M'; break; + default: ch = ' '; break; + } + item_make("<%c>", ch); + break; + } + item_set_tag('t'); + item_set_data(menu); + } else { + item_make(" "); + item_set_tag(def_menu ? 't' : ':'); + item_set_data(menu); + } + + item_add_str("%*c%s", indent + 1, ' ', menu_get_prompt(menu)); + if (val == yes) { + if (def_menu) { + item_add_str(" (%s)", menu_get_prompt(def_menu)); + item_add_str(" --->"); + if (def_menu->list) { + indent += 2; + build_conf(def_menu); + indent -= 2; + } + } + return; + } + } else { + if (menu == current_menu) { + item_make("---%*c%s", indent + 1, ' ', menu_get_prompt(menu)); + item_set_tag(':'); + item_set_data(menu); + goto conf_childs; + } + child_count++; + val = sym_get_tristate_value(sym); + if (sym_is_choice_value(sym) && val == yes) { + item_make(" "); + item_set_tag(':'); + item_set_data(menu); + } else { + switch (type) { + case S_BOOLEAN: + if (sym_is_changeable(sym)) + item_make("[%c]", val == no ? ' ' : '*'); + else + item_make("-%c-", val == no ? ' ' : '*'); + item_set_tag('t'); + item_set_data(menu); + break; + case S_TRISTATE: + switch (val) { + case yes: ch = '*'; break; + case mod: ch = 'M'; break; + default: ch = ' '; break; + } + if (sym_is_changeable(sym)) { + if (sym->rev_dep.tri == mod) + item_make("{%c}", ch); + else + item_make("<%c>", ch); + } else + item_make("-%c-", ch); + item_set_tag('t'); + item_set_data(menu); + break; + default: + tmp = 2 + strlen(sym_get_string_value(sym)); /* () = 2 */ + item_make("(%s)", sym_get_string_value(sym)); + tmp = indent - tmp + 4; + if (tmp < 0) + tmp = 0; + item_add_str("%*c%s%s", tmp, ' ', menu_get_prompt(menu), + (sym_has_value(sym) || !sym_is_changeable(sym)) ? + "" : " (NEW)"); + item_set_tag('s'); + item_set_data(menu); + goto conf_childs; + } + } + item_add_str("%*c%s%s", indent + 1, ' ', menu_get_prompt(menu), + (sym_has_value(sym) || !sym_is_changeable(sym)) ? + "" : " (NEW)"); + if (menu->prompt->type == P_MENU) { + item_add_str(" %s", menu_is_empty(menu) ? "----" : "--->"); + return; + } + } + +conf_childs: + indent += doint; + for (child = menu->list; child; child = child->next) + build_conf(child); + indent -= doint; +} + +static void conf(struct menu *menu, struct menu *active_menu) +{ + struct menu *submenu; + const char *prompt = menu_get_prompt(menu); + struct subtitle_part stpart; + struct symbol *sym; + int res; + int s_scroll = 0; + + if (menu != &rootmenu) + stpart.text = menu_get_prompt(menu); + else + stpart.text = NULL; + list_add_tail(&stpart.entries, &trail); + + while (1) { + item_reset(); + current_menu = menu; + build_conf(menu); + if (!child_count) + break; + set_subtitle(); + dialog_clear(); + res = dialog_menu(prompt ? prompt : "Main Menu", + menu_instructions, + active_menu, &s_scroll); + if (res == 1 || res == KEY_ESC || res == -ERRDISPLAYTOOSMALL) + break; + if (item_count() != 0) { + if (!item_activate_selected()) + continue; + if (!item_tag()) + continue; + } + submenu = item_data(); + active_menu = item_data(); + if (submenu) + sym = submenu->sym; + else + sym = NULL; + + switch (res) { + case 0: + switch (item_tag()) { + case 'm': + if (single_menu_mode) + submenu->data = (void *) (long) !submenu->data; + else + conf(submenu, NULL); + break; + case 't': + if (sym_is_choice(sym) && sym_get_tristate_value(sym) == yes) + conf_choice(submenu); + else if (submenu->prompt->type == P_MENU) + conf(submenu, NULL); + break; + case 's': + conf_string(submenu); + break; + } + break; + case 2: + if (sym) + show_help(submenu); + else { + reset_subtitle(); + show_helptext("README", mconf_readme); + } + break; + case 3: + reset_subtitle(); + conf_save(); + break; + case 4: + reset_subtitle(); + conf_load(); + break; + case 5: + if (item_is_tag('t')) { + if (sym_set_tristate_value(sym, yes)) + break; + if (sym_set_tristate_value(sym, mod)) + show_textbox(NULL, setmod_text, 6, 74); + } + break; + case 6: + if (item_is_tag('t')) + sym_set_tristate_value(sym, no); + break; + case 7: + if (item_is_tag('t')) + sym_set_tristate_value(sym, mod); + break; + case 8: + if (item_is_tag('t')) + sym_toggle_tristate_value(sym); + else if (item_is_tag('m')) + conf(submenu, NULL); + break; + case 9: + search_conf(); + break; + case 10: + show_all_options = !show_all_options; + break; + } + } + + list_del(trail.prev); +} + +static int show_textbox_ext(const char *title, char *text, int r, int c, int + *keys, int *vscroll, int *hscroll, update_text_fn + update_text, void *data) +{ + dialog_clear(); + return dialog_textbox(title, text, r, c, keys, vscroll, hscroll, + update_text, data); +} + +static void show_textbox(const char *title, const char *text, int r, int c) +{ + show_textbox_ext(title, (char *) text, r, c, (int []) {0}, NULL, NULL, + NULL, NULL); +} + +static void show_helptext(const char *title, const char *text) +{ + show_textbox(title, text, 0, 0); +} + +static void conf_message_callback(const char *s) +{ + if (save_and_exit) { + if (!silent) + printf("%s", s); + } else { + show_textbox(NULL, s, 6, 60); + } +} + +static void show_help(struct menu *menu) +{ + struct gstr help = str_new(); + + help.max_width = getmaxx(stdscr) - 10; + menu_get_ext_help(menu, &help); + + show_helptext(menu_get_prompt(menu), str_get(&help)); + str_free(&help); +} + +static void conf_choice(struct menu *menu) +{ + const char *prompt = menu_get_prompt(menu); + struct menu *child; + struct symbol *active; + + active = sym_get_choice_value(menu->sym); + while (1) { + int res; + int selected; + item_reset(); + + current_menu = menu; + for (child = menu->list; child; child = child->next) { + if (!menu_is_visible(child)) + continue; + if (child->sym) + item_make("%s", menu_get_prompt(child)); + else { + item_make("*** %s ***", menu_get_prompt(child)); + item_set_tag(':'); + } + item_set_data(child); + if (child->sym == active) + item_set_selected(1); + if (child->sym == sym_get_choice_value(menu->sym)) + item_set_tag('X'); + } + dialog_clear(); + res = dialog_checklist(prompt ? prompt : "Main Menu", + radiolist_instructions, + MENUBOX_HEIGTH_MIN, + MENUBOX_WIDTH_MIN, + CHECKLIST_HEIGTH_MIN); + selected = item_activate_selected(); + switch (res) { + case 0: + if (selected) { + child = item_data(); + if (!child->sym) + break; + + sym_set_tristate_value(child->sym, yes); + } + return; + case 1: + if (selected) { + child = item_data(); + show_help(child); + active = child->sym; + } else + show_help(menu); + break; + case KEY_ESC: + return; + case -ERRDISPLAYTOOSMALL: + return; + } + } +} + +static void conf_string(struct menu *menu) +{ + const char *prompt = menu_get_prompt(menu); + + while (1) { + int res; + const char *heading; + + switch (sym_get_type(menu->sym)) { + case S_INT: + heading = inputbox_instructions_int; + break; + case S_HEX: + heading = inputbox_instructions_hex; + break; + case S_STRING: + heading = inputbox_instructions_string; + break; + default: + heading = "Internal mconf error!"; + } + dialog_clear(); + res = dialog_inputbox(prompt ? prompt : "Main Menu", + heading, 10, 75, + sym_get_string_value(menu->sym)); + switch (res) { + case 0: + if (sym_set_string_value(menu->sym, dialog_input_result)) + return; + show_textbox(NULL, "You have made an invalid entry.", 5, 43); + break; + case 1: + show_help(menu); + break; + case KEY_ESC: + return; + } + } +} + +static void conf_load(void) +{ + + while (1) { + int res; + dialog_clear(); + res = dialog_inputbox(NULL, load_config_text, + 11, 55, filename); + switch(res) { + case 0: + if (!dialog_input_result[0]) + return; + if (!conf_read(dialog_input_result)) { + set_config_filename(dialog_input_result); + sym_set_change_count(1); + return; + } + show_textbox(NULL, "File does not exist!", 5, 38); + break; + case 1: + show_helptext("Load Alternate Configuration", load_config_help); + break; + case KEY_ESC: + return; + } + } +} + +static void conf_save(void) +{ + while (1) { + int res; + dialog_clear(); + res = dialog_inputbox(NULL, save_config_text, + 11, 55, filename); + switch(res) { + case 0: + if (!dialog_input_result[0]) + return; + if (!conf_write(dialog_input_result)) { + set_config_filename(dialog_input_result); + return; + } + show_textbox(NULL, "Can't create file!", 5, 60); + break; + case 1: + show_helptext("Save Alternate Configuration", save_config_help); + break; + case KEY_ESC: + return; + } + } +} + +static int handle_exit(void) +{ + int res; + + save_and_exit = 1; + reset_subtitle(); + dialog_clear(); + if (conf_get_changed()) + res = dialog_yesno(NULL, + "Do you wish to save your new configuration?\n" + "(Press <ESC><ESC> to continue kernel configuration.)", + 6, 60); + else + res = -1; + + end_dialog(saved_x, saved_y); + + switch (res) { + case 0: + if (conf_write(filename)) { + fprintf(stderr, "\n\n" + "Error while writing of the configuration.\n" + "Your configuration changes were NOT saved." + "\n\n"); + return 1; + } + conf_write_autoconf(0); + /* fall through */ + case -1: + if (!silent) + printf("\n\n" + "*** End of the configuration.\n" + "*** Execute 'make' to start the build or try 'make help'." + "\n\n"); + res = 0; + break; + default: + if (!silent) + fprintf(stderr, "\n\n" + "Your configuration changes were NOT saved." + "\n\n"); + if (res != KEY_ESC) + res = 0; + } + + return res; +} + +static void sig_handler(int signo) +{ + exit(handle_exit()); +} + +int main(int ac, char **av) +{ + char *mode; + int res; + + signal(SIGINT, sig_handler); + + if (ac > 1 && strcmp(av[1], "-s") == 0) { + silent = 1; + /* Silence conf_read() until the real callback is set up */ + conf_set_message_callback(NULL); + av++; + } + conf_parse(av[1]); + conf_read(NULL); + + mode = getenv("MENUCONFIG_MODE"); + if (mode) { + if (!strcasecmp(mode, "single_menu")) + single_menu_mode = 1; + } + + if (init_dialog(NULL)) { + fprintf(stderr, "Your display is too small to run Menuconfig!\n"); + fprintf(stderr, "It must be at least 19 lines by 80 columns.\n"); + return 1; + } + + set_config_filename(conf_get_configname()); + conf_set_message_callback(conf_message_callback); + do { + conf(&rootmenu, NULL); + res = handle_exit(); + } while (res == KEY_ESC); + + return res; +} diff --git a/src/net/scripts/kconfig/menu.c b/src/net/scripts/kconfig/menu.c new file mode 100644 index 0000000..a5fbd6c --- /dev/null +++ b/src/net/scripts/kconfig/menu.c @@ -0,0 +1,899 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2002 Roman Zippel <zippel@linux-m68k.org> + */ + +#include <ctype.h> +#include <stdarg.h> +#include <stdlib.h> +#include <string.h> + +#include "lkc.h" + +static const char nohelp_text[] = "There is no help available for this option."; + +struct menu rootmenu; +static struct menu **last_entry_ptr; + +struct file *file_list; +struct file *current_file; + +void menu_warn(struct menu *menu, const char *fmt, ...) +{ + va_list ap; + va_start(ap, fmt); + fprintf(stderr, "%s:%d:warning: ", menu->file->name, menu->lineno); + vfprintf(stderr, fmt, ap); + fprintf(stderr, "\n"); + va_end(ap); +} + +static void prop_warn(struct property *prop, const char *fmt, ...) +{ + va_list ap; + va_start(ap, fmt); + fprintf(stderr, "%s:%d:warning: ", prop->file->name, prop->lineno); + vfprintf(stderr, fmt, ap); + fprintf(stderr, "\n"); + va_end(ap); +} + +void _menu_init(void) +{ + current_entry = current_menu = &rootmenu; + last_entry_ptr = &rootmenu.list; +} + +void menu_add_entry(struct symbol *sym) +{ + struct menu *menu; + + menu = xmalloc(sizeof(*menu)); + memset(menu, 0, sizeof(*menu)); + menu->sym = sym; + menu->parent = current_menu; + menu->file = current_file; + menu->lineno = zconf_lineno(); + + *last_entry_ptr = menu; + last_entry_ptr = &menu->next; + current_entry = menu; + if (sym) + menu_add_symbol(P_SYMBOL, sym, NULL); +} + +struct menu *menu_add_menu(void) +{ + last_entry_ptr = ¤t_entry->list; + current_menu = current_entry; + return current_menu; +} + +void menu_end_menu(void) +{ + last_entry_ptr = ¤t_menu->next; + current_menu = current_menu->parent; +} + +/* + * Rewrites 'm' to 'm' && MODULES, so that it evaluates to 'n' when running + * without modules + */ +static struct expr *rewrite_m(struct expr *e) +{ + if (!e) + return e; + + switch (e->type) { + case E_NOT: + e->left.expr = rewrite_m(e->left.expr); + break; + case E_OR: + case E_AND: + e->left.expr = rewrite_m(e->left.expr); + e->right.expr = rewrite_m(e->right.expr); + break; + case E_SYMBOL: + /* change 'm' into 'm' && MODULES */ + if (e->left.sym == &symbol_mod) + return expr_alloc_and(e, expr_alloc_symbol(modules_sym)); + break; + default: + break; + } + return e; +} + +void menu_add_dep(struct expr *dep) +{ + current_entry->dep = expr_alloc_and(current_entry->dep, dep); +} + +void menu_set_type(int type) +{ + struct symbol *sym = current_entry->sym; + + if (sym->type == type) + return; + if (sym->type == S_UNKNOWN) { + sym->type = type; + return; + } + menu_warn(current_entry, + "ignoring type redefinition of '%s' from '%s' to '%s'", + sym->name ? sym->name : "<choice>", + sym_type_name(sym->type), sym_type_name(type)); +} + +static struct property *menu_add_prop(enum prop_type type, struct expr *expr, + struct expr *dep) +{ + struct property *prop; + + prop = xmalloc(sizeof(*prop)); + memset(prop, 0, sizeof(*prop)); + prop->type = type; + prop->file = current_file; + prop->lineno = zconf_lineno(); + prop->menu = current_entry; + prop->expr = expr; + prop->visible.expr = dep; + + /* append property to the prop list of symbol */ + if (current_entry->sym) { + struct property **propp; + + for (propp = ¤t_entry->sym->prop; + *propp; + propp = &(*propp)->next) + ; + *propp = prop; + } + + return prop; +} + +struct property *menu_add_prompt(enum prop_type type, char *prompt, + struct expr *dep) +{ + struct property *prop = menu_add_prop(type, NULL, dep); + + if (isspace(*prompt)) { + prop_warn(prop, "leading whitespace ignored"); + while (isspace(*prompt)) + prompt++; + } + if (current_entry->prompt) + prop_warn(prop, "prompt redefined"); + + /* Apply all upper menus' visibilities to actual prompts. */ + if (type == P_PROMPT) { + struct menu *menu = current_entry; + + while ((menu = menu->parent) != NULL) { + struct expr *dup_expr; + + if (!menu->visibility) + continue; + /* + * Do not add a reference to the menu's visibility + * expression but use a copy of it. Otherwise the + * expression reduction functions will modify + * expressions that have multiple references which + * can cause unwanted side effects. + */ + dup_expr = expr_copy(menu->visibility); + + prop->visible.expr = expr_alloc_and(prop->visible.expr, + dup_expr); + } + } + + current_entry->prompt = prop; + prop->text = prompt; + + return prop; +} + +void menu_add_visibility(struct expr *expr) +{ + current_entry->visibility = expr_alloc_and(current_entry->visibility, + expr); +} + +void menu_add_expr(enum prop_type type, struct expr *expr, struct expr *dep) +{ + menu_add_prop(type, expr, dep); +} + +void menu_add_symbol(enum prop_type type, struct symbol *sym, struct expr *dep) +{ + menu_add_prop(type, expr_alloc_symbol(sym), dep); +} + +void menu_add_option_modules(void) +{ + if (modules_sym) + zconf_error("symbol '%s' redefines option 'modules' already defined by symbol '%s'", + current_entry->sym->name, modules_sym->name); + modules_sym = current_entry->sym; +} + +void menu_add_option_defconfig_list(void) +{ + if (!sym_defconfig_list) + sym_defconfig_list = current_entry->sym; + else if (sym_defconfig_list != current_entry->sym) + zconf_error("trying to redefine defconfig symbol"); + sym_defconfig_list->flags |= SYMBOL_NO_WRITE; +} + +void menu_add_option_allnoconfig_y(void) +{ + current_entry->sym->flags |= SYMBOL_ALLNOCONFIG_Y; +} + +static int menu_validate_number(struct symbol *sym, struct symbol *sym2) +{ + return sym2->type == S_INT || sym2->type == S_HEX || + (sym2->type == S_UNKNOWN && sym_string_valid(sym, sym2->name)); +} + +static void sym_check_prop(struct symbol *sym) +{ + struct property *prop; + struct symbol *sym2; + char *use; + + for (prop = sym->prop; prop; prop = prop->next) { + switch (prop->type) { + case P_DEFAULT: + if ((sym->type == S_STRING || sym->type == S_INT || sym->type == S_HEX) && + prop->expr->type != E_SYMBOL) + prop_warn(prop, + "default for config symbol '%s'" + " must be a single symbol", sym->name); + if (prop->expr->type != E_SYMBOL) + break; + sym2 = prop_get_symbol(prop); + if (sym->type == S_HEX || sym->type == S_INT) { + if (!menu_validate_number(sym, sym2)) + prop_warn(prop, + "'%s': number is invalid", + sym->name); + } + if (sym_is_choice(sym)) { + struct property *choice_prop = + sym_get_choice_prop(sym2); + + if (!choice_prop || + prop_get_symbol(choice_prop) != sym) + prop_warn(prop, + "choice default symbol '%s' is not contained in the choice", + sym2->name); + } + break; + case P_SELECT: + case P_IMPLY: + use = prop->type == P_SELECT ? "select" : "imply"; + sym2 = prop_get_symbol(prop); + if (sym->type != S_BOOLEAN && sym->type != S_TRISTATE) + prop_warn(prop, + "config symbol '%s' uses %s, but is " + "not bool or tristate", sym->name, use); + else if (sym2->type != S_UNKNOWN && + sym2->type != S_BOOLEAN && + sym2->type != S_TRISTATE) + prop_warn(prop, + "'%s' has wrong type. '%s' only " + "accept arguments of bool and " + "tristate type", sym2->name, use); + break; + case P_RANGE: + if (sym->type != S_INT && sym->type != S_HEX) + prop_warn(prop, "range is only allowed " + "for int or hex symbols"); + if (!menu_validate_number(sym, prop->expr->left.sym) || + !menu_validate_number(sym, prop->expr->right.sym)) + prop_warn(prop, "range is invalid"); + break; + default: + ; + } + } +} + +void menu_finalize(struct menu *parent) +{ + struct menu *menu, *last_menu; + struct symbol *sym; + struct property *prop; + struct expr *parentdep, *basedep, *dep, *dep2, **ep; + + sym = parent->sym; + if (parent->list) { + /* + * This menu node has children. We (recursively) process them + * and propagate parent dependencies before moving on. + */ + + if (sym && sym_is_choice(sym)) { + if (sym->type == S_UNKNOWN) { + /* find the first choice value to find out choice type */ + current_entry = parent; + for (menu = parent->list; menu; menu = menu->next) { + if (menu->sym && menu->sym->type != S_UNKNOWN) { + menu_set_type(menu->sym->type); + break; + } + } + } + /* set the type of the remaining choice values */ + for (menu = parent->list; menu; menu = menu->next) { + current_entry = menu; + if (menu->sym && menu->sym->type == S_UNKNOWN) + menu_set_type(sym->type); + } + + /* + * Use the choice itself as the parent dependency of + * the contained items. This turns the mode of the + * choice into an upper bound on the visibility of the + * choice value symbols. + */ + parentdep = expr_alloc_symbol(sym); + } else { + /* Menu node for 'menu', 'if' */ + parentdep = parent->dep; + } + + /* For each child menu node... */ + for (menu = parent->list; menu; menu = menu->next) { + /* + * Propagate parent dependencies to the child menu + * node, also rewriting and simplifying expressions + */ + basedep = rewrite_m(menu->dep); + basedep = expr_transform(basedep); + basedep = expr_alloc_and(expr_copy(parentdep), basedep); + basedep = expr_eliminate_dups(basedep); + menu->dep = basedep; + + if (menu->sym) + /* + * Note: For symbols, all prompts are included + * too in the symbol's own property list + */ + prop = menu->sym->prop; + else + /* + * For non-symbol menu nodes, we just need to + * handle the prompt + */ + prop = menu->prompt; + + /* For each property... */ + for (; prop; prop = prop->next) { + if (prop->menu != menu) + /* + * Two possibilities: + * + * 1. The property lacks dependencies + * and so isn't location-specific, + * e.g. an 'option' + * + * 2. The property belongs to a symbol + * defined in multiple locations and + * is from some other location. It + * will be handled there in that + * case. + * + * Skip the property. + */ + continue; + + /* + * Propagate parent dependencies to the + * property's condition, rewriting and + * simplifying expressions at the same time + */ + dep = rewrite_m(prop->visible.expr); + dep = expr_transform(dep); + dep = expr_alloc_and(expr_copy(basedep), dep); + dep = expr_eliminate_dups(dep); + if (menu->sym && menu->sym->type != S_TRISTATE) + dep = expr_trans_bool(dep); + prop->visible.expr = dep; + + /* + * Handle selects and implies, which modify the + * dependencies of the selected/implied symbol + */ + if (prop->type == P_SELECT) { + struct symbol *es = prop_get_symbol(prop); + es->rev_dep.expr = expr_alloc_or(es->rev_dep.expr, + expr_alloc_and(expr_alloc_symbol(menu->sym), expr_copy(dep))); + } else if (prop->type == P_IMPLY) { + struct symbol *es = prop_get_symbol(prop); + es->implied.expr = expr_alloc_or(es->implied.expr, + expr_alloc_and(expr_alloc_symbol(menu->sym), expr_copy(dep))); + } + } + } + + if (sym && sym_is_choice(sym)) + expr_free(parentdep); + + /* + * Recursively process children in the same fashion before + * moving on + */ + for (menu = parent->list; menu; menu = menu->next) + menu_finalize(menu); + } else if (sym) { + /* + * Automatic submenu creation. If sym is a symbol and A, B, C, + * ... are consecutive items (symbols, menus, ifs, etc.) that + * all depend on sym, then the following menu structure is + * created: + * + * sym + * +-A + * +-B + * +-C + * ... + * + * This also works recursively, giving the following structure + * if A is a symbol and B depends on A: + * + * sym + * +-A + * | +-B + * +-C + * ... + */ + + basedep = parent->prompt ? parent->prompt->visible.expr : NULL; + basedep = expr_trans_compare(basedep, E_UNEQUAL, &symbol_no); + basedep = expr_eliminate_dups(expr_transform(basedep)); + + /* Examine consecutive elements after sym */ + last_menu = NULL; + for (menu = parent->next; menu; menu = menu->next) { + dep = menu->prompt ? menu->prompt->visible.expr : menu->dep; + if (!expr_contains_symbol(dep, sym)) + /* No dependency, quit */ + break; + if (expr_depends_symbol(dep, sym)) + /* Absolute dependency, put in submenu */ + goto next; + + /* + * Also consider it a dependency on sym if our + * dependencies contain sym and are a "superset" of + * sym's dependencies, e.g. '(sym || Q) && R' when sym + * depends on R. + * + * Note that 'R' might be from an enclosing menu or if, + * making this a more common case than it might seem. + */ + dep = expr_trans_compare(dep, E_UNEQUAL, &symbol_no); + dep = expr_eliminate_dups(expr_transform(dep)); + dep2 = expr_copy(basedep); + expr_eliminate_eq(&dep, &dep2); + expr_free(dep); + if (!expr_is_yes(dep2)) { + /* Not superset, quit */ + expr_free(dep2); + break; + } + /* Superset, put in submenu */ + expr_free(dep2); + next: + menu_finalize(menu); + menu->parent = parent; + last_menu = menu; + } + expr_free(basedep); + if (last_menu) { + parent->list = parent->next; + parent->next = last_menu->next; + last_menu->next = NULL; + } + + sym->dir_dep.expr = expr_alloc_or(sym->dir_dep.expr, parent->dep); + } + for (menu = parent->list; menu; menu = menu->next) { + if (sym && sym_is_choice(sym) && + menu->sym && !sym_is_choice_value(menu->sym)) { + current_entry = menu; + menu->sym->flags |= SYMBOL_CHOICEVAL; + if (!menu->prompt) + menu_warn(menu, "choice value must have a prompt"); + for (prop = menu->sym->prop; prop; prop = prop->next) { + if (prop->type == P_DEFAULT) + prop_warn(prop, "defaults for choice " + "values not supported"); + if (prop->menu == menu) + continue; + if (prop->type == P_PROMPT && + prop->menu->parent->sym != sym) + prop_warn(prop, "choice value used outside its choice group"); + } + /* Non-tristate choice values of tristate choices must + * depend on the choice being set to Y. The choice + * values' dependencies were propagated to their + * properties above, so the change here must be re- + * propagated. + */ + if (sym->type == S_TRISTATE && menu->sym->type != S_TRISTATE) { + basedep = expr_alloc_comp(E_EQUAL, sym, &symbol_yes); + menu->dep = expr_alloc_and(basedep, menu->dep); + for (prop = menu->sym->prop; prop; prop = prop->next) { + if (prop->menu != menu) + continue; + prop->visible.expr = expr_alloc_and(expr_copy(basedep), + prop->visible.expr); + } + } + menu_add_symbol(P_CHOICE, sym, NULL); + prop = sym_get_choice_prop(sym); + for (ep = &prop->expr; *ep; ep = &(*ep)->left.expr) + ; + *ep = expr_alloc_one(E_LIST, NULL); + (*ep)->right.sym = menu->sym; + } + + /* + * This code serves two purposes: + * + * (1) Flattening 'if' blocks, which do not specify a submenu + * and only add dependencies. + * + * (Automatic submenu creation might still create a submenu + * from an 'if' before this code runs.) + * + * (2) "Undoing" any automatic submenus created earlier below + * promptless symbols. + * + * Before: + * + * A + * if ... (or promptless symbol) + * +-B + * +-C + * D + * + * After: + * + * A + * if ... (or promptless symbol) + * B + * C + * D + */ + if (menu->list && (!menu->prompt || !menu->prompt->text)) { + for (last_menu = menu->list; ; last_menu = last_menu->next) { + last_menu->parent = parent; + if (!last_menu->next) + break; + } + last_menu->next = menu->next; + menu->next = menu->list; + menu->list = NULL; + } + } + + if (sym && !(sym->flags & SYMBOL_WARNED)) { + if (sym->type == S_UNKNOWN) + menu_warn(parent, "config symbol defined without type"); + + if (sym_is_choice(sym) && !parent->prompt) + menu_warn(parent, "choice must have a prompt"); + + /* Check properties connected to this symbol */ + sym_check_prop(sym); + sym->flags |= SYMBOL_WARNED; + } + + /* + * For non-optional choices, add a reverse dependency (corresponding to + * a select) of '<visibility> && m'. This prevents the user from + * setting the choice mode to 'n' when the choice is visible. + * + * This would also work for non-choice symbols, but only non-optional + * choices clear SYMBOL_OPTIONAL as of writing. Choices are implemented + * as a type of symbol. + */ + if (sym && !sym_is_optional(sym) && parent->prompt) { + sym->rev_dep.expr = expr_alloc_or(sym->rev_dep.expr, + expr_alloc_and(parent->prompt->visible.expr, + expr_alloc_symbol(&symbol_mod))); + } +} + +bool menu_has_prompt(struct menu *menu) +{ + if (!menu->prompt) + return false; + return true; +} + +/* + * Determine if a menu is empty. + * A menu is considered empty if it contains no or only + * invisible entries. + */ +bool menu_is_empty(struct menu *menu) +{ + struct menu *child; + + for (child = menu->list; child; child = child->next) { + if (menu_is_visible(child)) + return(false); + } + return(true); +} + +bool menu_is_visible(struct menu *menu) +{ + struct menu *child; + struct symbol *sym; + tristate visible; + + if (!menu->prompt) + return false; + + if (menu->visibility) { + if (expr_calc_value(menu->visibility) == no) + return false; + } + + sym = menu->sym; + if (sym) { + sym_calc_value(sym); + visible = menu->prompt->visible.tri; + } else + visible = menu->prompt->visible.tri = expr_calc_value(menu->prompt->visible.expr); + + if (visible != no) + return true; + + if (!sym || sym_get_tristate_value(menu->sym) == no) + return false; + + for (child = menu->list; child; child = child->next) { + if (menu_is_visible(child)) { + if (sym) + sym->flags |= SYMBOL_DEF_USER; + return true; + } + } + + return false; +} + +const char *menu_get_prompt(struct menu *menu) +{ + if (menu->prompt) + return menu->prompt->text; + else if (menu->sym) + return menu->sym->name; + return NULL; +} + +struct menu *menu_get_root_menu(struct menu *menu) +{ + return &rootmenu; +} + +struct menu *menu_get_parent_menu(struct menu *menu) +{ + enum prop_type type; + + for (; menu != &rootmenu; menu = menu->parent) { + type = menu->prompt ? menu->prompt->type : 0; + if (type == P_MENU) + break; + } + return menu; +} + +bool menu_has_help(struct menu *menu) +{ + return menu->help != NULL; +} + +const char *menu_get_help(struct menu *menu) +{ + if (menu->help) + return menu->help; + else + return ""; +} + +static void get_def_str(struct gstr *r, struct menu *menu) +{ + str_printf(r, "Defined at %s:%d\n", + menu->file->name, menu->lineno); +} + +static void get_dep_str(struct gstr *r, struct expr *expr, const char *prefix) +{ + if (!expr_is_yes(expr)) { + str_append(r, prefix); + expr_gstr_print(expr, r); + str_append(r, "\n"); + } +} + +static void get_prompt_str(struct gstr *r, struct property *prop, + struct list_head *head) +{ + int i, j; + struct menu *submenu[8], *menu, *location = NULL; + struct jump_key *jump = NULL; + + str_printf(r, " Prompt: %s\n", prop->text); + + get_dep_str(r, prop->menu->dep, " Depends on: "); + /* + * Most prompts in Linux have visibility that exactly matches their + * dependencies. For these, we print only the dependencies to improve + * readability. However, prompts with inline "if" expressions and + * prompts with a parent that has a "visible if" expression have + * differing dependencies and visibility. In these rare cases, we + * print both. + */ + if (!expr_eq(prop->menu->dep, prop->visible.expr)) + get_dep_str(r, prop->visible.expr, " Visible if: "); + + menu = prop->menu->parent; + for (i = 0; menu != &rootmenu && i < 8; menu = menu->parent) { + bool accessible = menu_is_visible(menu); + + submenu[i++] = menu; + if (location == NULL && accessible) + location = menu; + } + if (head && location) { + jump = xmalloc(sizeof(struct jump_key)); + + if (menu_is_visible(prop->menu)) { + /* + * There is not enough room to put the hint at the + * beginning of the "Prompt" line. Put the hint on the + * last "Location" line even when it would belong on + * the former. + */ + jump->target = prop->menu; + } else + jump->target = location; + + if (list_empty(head)) + jump->index = 0; + else + jump->index = list_entry(head->prev, struct jump_key, + entries)->index + 1; + + list_add_tail(&jump->entries, head); + } + + if (i > 0) { + str_printf(r, " Location:\n"); + for (j = 4; --i >= 0; j += 2) { + menu = submenu[i]; + if (jump && menu == location) + jump->offset = strlen(r->s); + str_printf(r, "%*c-> %s", j, ' ', + menu_get_prompt(menu)); + if (menu->sym) { + str_printf(r, " (%s [=%s])", menu->sym->name ? + menu->sym->name : "<choice>", + sym_get_string_value(menu->sym)); + } + str_append(r, "\n"); + } + } +} + +static void get_symbol_props_str(struct gstr *r, struct symbol *sym, + enum prop_type tok, const char *prefix) +{ + bool hit = false; + struct property *prop; + + for_all_properties(sym, prop, tok) { + if (!hit) { + str_append(r, prefix); + hit = true; + } else + str_printf(r, " && "); + expr_gstr_print(prop->expr, r); + } + if (hit) + str_append(r, "\n"); +} + +/* + * head is optional and may be NULL + */ +static void get_symbol_str(struct gstr *r, struct symbol *sym, + struct list_head *head) +{ + struct property *prop; + + if (sym && sym->name) { + str_printf(r, "Symbol: %s [=%s]\n", sym->name, + sym_get_string_value(sym)); + str_printf(r, "Type : %s\n", sym_type_name(sym->type)); + if (sym->type == S_INT || sym->type == S_HEX) { + prop = sym_get_range_prop(sym); + if (prop) { + str_printf(r, "Range : "); + expr_gstr_print(prop->expr, r); + str_append(r, "\n"); + } + } + } + + /* Print the definitions with prompts before the ones without */ + for_all_properties(sym, prop, P_SYMBOL) { + if (prop->menu->prompt) { + get_def_str(r, prop->menu); + get_prompt_str(r, prop->menu->prompt, head); + } + } + + for_all_properties(sym, prop, P_SYMBOL) { + if (!prop->menu->prompt) { + get_def_str(r, prop->menu); + get_dep_str(r, prop->menu->dep, " Depends on: "); + } + } + + get_symbol_props_str(r, sym, P_SELECT, "Selects: "); + if (sym->rev_dep.expr) { + expr_gstr_print_revdep(sym->rev_dep.expr, r, yes, "Selected by [y]:\n"); + expr_gstr_print_revdep(sym->rev_dep.expr, r, mod, "Selected by [m]:\n"); + expr_gstr_print_revdep(sym->rev_dep.expr, r, no, "Selected by [n]:\n"); + } + + get_symbol_props_str(r, sym, P_IMPLY, "Implies: "); + if (sym->implied.expr) { + expr_gstr_print_revdep(sym->implied.expr, r, yes, "Implied by [y]:\n"); + expr_gstr_print_revdep(sym->implied.expr, r, mod, "Implied by [m]:\n"); + expr_gstr_print_revdep(sym->implied.expr, r, no, "Implied by [n]:\n"); + } + + str_append(r, "\n\n"); +} + +struct gstr get_relations_str(struct symbol **sym_arr, struct list_head *head) +{ + struct symbol *sym; + struct gstr res = str_new(); + int i; + + for (i = 0; sym_arr && (sym = sym_arr[i]); i++) + get_symbol_str(&res, sym, head); + if (!i) + str_append(&res, "No matches found.\n"); + return res; +} + + +void menu_get_ext_help(struct menu *menu, struct gstr *help) +{ + struct symbol *sym = menu->sym; + const char *help_text = nohelp_text; + + if (menu_has_help(menu)) { + if (sym->name) + str_printf(help, "%s%s:\n\n", CONFIG_, sym->name); + help_text = menu_get_help(menu); + } + str_printf(help, "%s\n", help_text); + if (sym) + get_symbol_str(help, sym, NULL); +} diff --git a/src/net/scripts/kconfig/merge_config.sh b/src/net/scripts/kconfig/merge_config.sh new file mode 100755 index 0000000..63c8565 --- /dev/null +++ b/src/net/scripts/kconfig/merge_config.sh @@ -0,0 +1,189 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0 +# +# merge_config.sh - Takes a list of config fragment values, and merges +# them one by one. Provides warnings on overridden values, and specified +# values that did not make it to the resulting .config file (due to missed +# dependencies or config symbol removal). +# +# Portions reused from kconf_check and generate_cfg: +# http://git.yoctoproject.org/cgit/cgit.cgi/yocto-kernel-tools/tree/tools/kconf_check +# http://git.yoctoproject.org/cgit/cgit.cgi/yocto-kernel-tools/tree/tools/generate_cfg +# +# Copyright (c) 2009-2010 Wind River Systems, Inc. +# Copyright 2011 Linaro + +set -e + +clean_up() { + rm -f $TMP_FILE + rm -f $MERGE_FILE +} + +usage() { + echo "Usage: $0 [OPTIONS] [CONFIG [...]]" + echo " -h display this help text" + echo " -m only merge the fragments, do not execute the make command" + echo " -n use allnoconfig instead of alldefconfig" + echo " -r list redundant entries when merging fragments" + echo " -y make builtin have precedence over modules" + echo " -O dir to put generated output files. Consider setting \$KCONFIG_CONFIG instead." + echo + echo "Used prefix: '$CONFIG_PREFIX'. You can redefine it with \$CONFIG_ environment variable." +} + +RUNMAKE=true +ALLTARGET=alldefconfig +WARNREDUN=false +BUILTIN=false +OUTPUT=. +CONFIG_PREFIX=${CONFIG_-CONFIG_} + +while true; do + case $1 in + "-n") + ALLTARGET=allnoconfig + shift + continue + ;; + "-m") + RUNMAKE=false + shift + continue + ;; + "-h") + usage + exit + ;; + "-r") + WARNREDUN=true + shift + continue + ;; + "-y") + BUILTIN=true + shift + continue + ;; + "-O") + if [ -d $2 ];then + OUTPUT=$(echo $2 | sed 's/\/*$//') + else + echo "output directory $2 does not exist" 1>&2 + exit 1 + fi + shift 2 + continue + ;; + *) + break + ;; + esac +done + +if [ "$#" -lt 1 ] ; then + usage + exit +fi + +if [ -z "$KCONFIG_CONFIG" ]; then + if [ "$OUTPUT" != . ]; then + KCONFIG_CONFIG=$(readlink -m -- "$OUTPUT/.config") + else + KCONFIG_CONFIG=.config + fi +fi + +INITFILE=$1 +shift; + +if [ ! -r "$INITFILE" ]; then + echo "The base file '$INITFILE' does not exist. Exit." >&2 + exit 1 +fi + +MERGE_LIST=$* +SED_CONFIG_EXP1="s/^\(${CONFIG_PREFIX}[a-zA-Z0-9_]*\)=.*/\1/p" +SED_CONFIG_EXP2="s/^# \(${CONFIG_PREFIX}[a-zA-Z0-9_]*\) is not set$/\1/p" + +TMP_FILE=$(mktemp ./.tmp.config.XXXXXXXXXX) +MERGE_FILE=$(mktemp ./.merge_tmp.config.XXXXXXXXXX) + +echo "Using $INITFILE as base" + +trap clean_up EXIT + +cat $INITFILE > $TMP_FILE + +# Merge files, printing warnings on overridden values +for ORIG_MERGE_FILE in $MERGE_LIST ; do + echo "Merging $ORIG_MERGE_FILE" + if [ ! -r "$ORIG_MERGE_FILE" ]; then + echo "The merge file '$ORIG_MERGE_FILE' does not exist. Exit." >&2 + exit 1 + fi + cat $ORIG_MERGE_FILE > $MERGE_FILE + CFG_LIST=$(sed -n -e "$SED_CONFIG_EXP1" -e "$SED_CONFIG_EXP2" $MERGE_FILE) + + for CFG in $CFG_LIST ; do + grep -q -w $CFG $TMP_FILE || continue + PREV_VAL=$(grep -w $CFG $TMP_FILE) + NEW_VAL=$(grep -w $CFG $MERGE_FILE) + BUILTIN_FLAG=false + if [ "$BUILTIN" = "true" ] && [ "${NEW_VAL#CONFIG_*=}" = "m" ] && [ "${PREV_VAL#CONFIG_*=}" = "y" ]; then + echo Previous value: $PREV_VAL + echo New value: $NEW_VAL + echo -y passed, will not demote y to m + echo + BUILTIN_FLAG=true + elif [ "x$PREV_VAL" != "x$NEW_VAL" ] ; then + echo Value of $CFG is redefined by fragment $ORIG_MERGE_FILE: + echo Previous value: $PREV_VAL + echo New value: $NEW_VAL + echo + elif [ "$WARNREDUN" = "true" ]; then + echo Value of $CFG is redundant by fragment $ORIG_MERGE_FILE: + fi + if [ "$BUILTIN_FLAG" = "false" ]; then + sed -i "/$CFG[ =]/d" $TMP_FILE + else + sed -i "/$CFG[ =]/d" $MERGE_FILE + fi + done + cat $MERGE_FILE >> $TMP_FILE +done + +if [ "$RUNMAKE" = "false" ]; then + cp -T -- "$TMP_FILE" "$KCONFIG_CONFIG" + echo "#" + echo "# merged configuration written to $KCONFIG_CONFIG (needs make)" + echo "#" + exit +fi + +# If we have an output dir, setup the O= argument, otherwise leave +# it blank, since O=. will create an unnecessary ./source softlink +OUTPUT_ARG="" +if [ "$OUTPUT" != "." ] ; then + OUTPUT_ARG="O=$OUTPUT" +fi + + +# Use the merged file as the starting point for: +# alldefconfig: Fills in any missing symbols with Kconfig default +# allnoconfig: Fills in any missing symbols with # CONFIG_* is not set +make KCONFIG_ALLCONFIG=$TMP_FILE $OUTPUT_ARG $ALLTARGET + + +# Check all specified config values took (might have missed-dependency issues) +for CFG in $(sed -n -e "$SED_CONFIG_EXP1" -e "$SED_CONFIG_EXP2" $TMP_FILE); do + + REQUESTED_VAL=$(grep -w -e "$CFG" $TMP_FILE) + ACTUAL_VAL=$(grep -w -e "$CFG" "$KCONFIG_CONFIG" || true) + if [ "x$REQUESTED_VAL" != "x$ACTUAL_VAL" ] ; then + echo "Value requested for $CFG not in final .config" + echo "Requested value: $REQUESTED_VAL" + echo "Actual value: $ACTUAL_VAL" + echo "" + fi +done diff --git a/src/net/scripts/kconfig/nconf-cfg.sh b/src/net/scripts/kconfig/nconf-cfg.sh new file mode 100755 index 0000000..c212255 --- /dev/null +++ b/src/net/scripts/kconfig/nconf-cfg.sh @@ -0,0 +1,50 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0 + +PKG="ncursesw menuw panelw" +PKG2="ncurses menu panel" + +if [ -n "$(command -v pkg-config)" ]; then + if pkg-config --exists $PKG; then + echo cflags=\"$(pkg-config --cflags $PKG)\" + echo libs=\"$(pkg-config --libs $PKG)\" + exit 0 + fi + + if pkg-config --exists $PKG2; then + echo cflags=\"$(pkg-config --cflags $PKG2)\" + echo libs=\"$(pkg-config --libs $PKG2)\" + exit 0 + fi +fi + +# Check the default paths in case pkg-config is not installed. +# (Even if it is installed, some distributions such as openSUSE cannot +# find ncurses by pkg-config.) +if [ -f /usr/include/ncursesw/ncurses.h ]; then + echo cflags=\"-D_GNU_SOURCE -I/usr/include/ncursesw\" + echo libs=\"-lncursesw -lmenuw -lpanelw\" + exit 0 +fi + +if [ -f /usr/include/ncurses/ncurses.h ]; then + echo cflags=\"-D_GNU_SOURCE -I/usr/include/ncurses\" + echo libs=\"-lncurses -lmenu -lpanel\" + exit 0 +fi + +if [ -f /usr/include/ncurses.h ]; then + echo cflags=\"-D_GNU_SOURCE\" + echo libs=\"-lncurses -lmenu -lpanel\" + exit 0 +fi + +echo >&2 "*" +echo >&2 "* Unable to find the ncurses package." +echo >&2 "* Install ncurses (ncurses-devel or libncurses-dev" +echo >&2 "* depending on your distribution)." +echo >&2 "*" +echo >&2 "* You may also need to install pkg-config to find the" +echo >&2 "* ncurses installed in a non-default location." +echo >&2 "*" +exit 1 diff --git a/src/net/scripts/kconfig/nconf.c b/src/net/scripts/kconfig/nconf.c new file mode 100644 index 0000000..af814b3 --- /dev/null +++ b/src/net/scripts/kconfig/nconf.c @@ -0,0 +1,1555 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2008 Nir Tzachar <nir.tzachar@gmail.com> + * + * Derived from menuconfig. + */ +#ifndef _GNU_SOURCE +#define _GNU_SOURCE +#endif +#include <string.h> +#include <strings.h> +#include <stdlib.h> + +#include "lkc.h" +#include "nconf.h" +#include <ctype.h> + +static const char nconf_global_help[] = +"Help windows\n" +"------------\n" +"o Global help: Unless in a data entry window, pressing <F1> will give \n" +" you the global help window, which you are just reading.\n" +"\n" +"o A short version of the global help is available by pressing <F3>.\n" +"\n" +"o Local help: To get help related to the current menu entry, use any\n" +" of <?> <h>, or if in a data entry window then press <F1>.\n" +"\n" +"\n" +"Menu entries\n" +"------------\n" +"This interface lets you select features and parameters for the kernel\n" +"build. Kernel features can either be built-in, modularized, or removed.\n" +"Parameters must be entered as text or decimal or hexadecimal numbers.\n" +"\n" +"Menu entries beginning with following braces represent features that\n" +" [ ] can be built in or removed\n" +" < > can be built in, modularized or removed\n" +" { } can be built in or modularized, are selected by another feature\n" +" - - are selected by another feature\n" +" XXX cannot be selected. Symbol Info <F2> tells you why.\n" +"*, M or whitespace inside braces means to build in, build as a module\n" +"or to exclude the feature respectively.\n" +"\n" +"To change any of these features, highlight it with the movement keys\n" +"listed below and press <y> to build it in, <m> to make it a module or\n" +"<n> to remove it. You may press the <Space> key to cycle through the\n" +"available options.\n" +"\n" +"A trailing \"--->\" designates a submenu, a trailing \"----\" an\n" +"empty submenu.\n" +"\n" +"Menu navigation keys\n" +"----------------------------------------------------------------------\n" +"Linewise up <Up>\n" +"Linewise down <Down>\n" +"Pagewise up <Page Up>\n" +"Pagewise down <Page Down>\n" +"First entry <Home>\n" +"Last entry <End>\n" +"Enter a submenu <Right> <Enter>\n" +"Go back to parent menu <Left> <Esc> <F5>\n" +"Close a help window <Enter> <Esc> <F5>\n" +"Close entry window, apply <Enter>\n" +"Close entry window, forget <Esc> <F5>\n" +"Start incremental, case-insensitive search for STRING in menu entries,\n" +" no regex support, STRING is displayed in upper left corner\n" +" </>STRING\n" +" Remove last character <Backspace>\n" +" Jump to next hit <Down>\n" +" Jump to previous hit <Up>\n" +"Exit menu search mode </> <Esc>\n" +"Search for configuration variables with or without leading CONFIG_\n" +" <F8>RegExpr<Enter>\n" +"Verbose search help <F8><F1>\n" +"----------------------------------------------------------------------\n" +"\n" +"Unless in a data entry window, key <1> may be used instead of <F1>,\n" +"<2> instead of <F2>, etc.\n" +"\n" +"\n" +"Radiolist (Choice list)\n" +"-----------------------\n" +"Use the movement keys listed above to select the option you wish to set\n" +"and press <Space>.\n" +"\n" +"\n" +"Data entry\n" +"----------\n" +"Enter the requested information and press <Enter>. Hexadecimal values\n" +"may be entered without the \"0x\" prefix.\n" +"\n" +"\n" +"Text Box (Help Window)\n" +"----------------------\n" +"Use movement keys as listed in table above.\n" +"\n" +"Press any of <Enter> <Esc> <q> <F5> <F9> to exit.\n" +"\n" +"\n" +"Alternate configuration files\n" +"-----------------------------\n" +"nconfig supports switching between different configurations.\n" +"Press <F6> to save your current configuration. Press <F7> and enter\n" +"a file name to load a previously saved configuration.\n" +"\n" +"\n" +"Terminal configuration\n" +"----------------------\n" +"If you use nconfig in a xterm window, make sure your TERM environment\n" +"variable specifies a terminal configuration which supports at least\n" +"16 colors. Otherwise nconfig will look rather bad.\n" +"\n" +"If the \"stty size\" command reports the current terminalsize correctly,\n" +"nconfig will adapt to sizes larger than the traditional 80x25 \"standard\"\n" +"and display longer menus properly.\n" +"\n" +"\n" +"Single menu mode\n" +"----------------\n" +"If you prefer to have all of the menu entries listed in a single menu,\n" +"rather than the default multimenu hierarchy, run nconfig with\n" +"NCONFIG_MODE environment variable set to single_menu. Example:\n" +"\n" +"make NCONFIG_MODE=single_menu nconfig\n" +"\n" +"<Enter> will then unfold the appropriate category, or fold it if it\n" +"is already unfolded. Folded menu entries will be designated by a\n" +"leading \"++>\" and unfolded entries by a leading \"-->\".\n" +"\n" +"Note that this mode can eventually be a little more CPU expensive than\n" +"the default mode, especially with a larger number of unfolded submenus.\n" +"\n", +menu_no_f_instructions[] = +"Legend: [*] built-in [ ] excluded <M> module < > module capable.\n" +"Submenus are designated by a trailing \"--->\", empty ones by \"----\".\n" +"\n" +"Use the following keys to navigate the menus:\n" +"Move up or down with <Up> and <Down>.\n" +"Enter a submenu with <Enter> or <Right>.\n" +"Exit a submenu to its parent menu with <Esc> or <Left>.\n" +"Pressing <y> includes, <n> excludes, <m> modularizes features.\n" +"Pressing <Space> cycles through the available options.\n" +"To search for menu entries press </>.\n" +"<Esc> always leaves the current window.\n" +"\n" +"You do not have function keys support.\n" +"Press <1> instead of <F1>, <2> instead of <F2>, etc.\n" +"For verbose global help use key <1>.\n" +"For help related to the current menu entry press <?> or <h>.\n", +menu_instructions[] = +"Legend: [*] built-in [ ] excluded <M> module < > module capable.\n" +"Submenus are designated by a trailing \"--->\", empty ones by \"----\".\n" +"\n" +"Use the following keys to navigate the menus:\n" +"Move up or down with <Up> or <Down>.\n" +"Enter a submenu with <Enter> or <Right>.\n" +"Exit a submenu to its parent menu with <Esc> or <Left>.\n" +"Pressing <y> includes, <n> excludes, <m> modularizes features.\n" +"Pressing <Space> cycles through the available options.\n" +"To search for menu entries press </>.\n" +"<Esc> always leaves the current window.\n" +"\n" +"Pressing <1> may be used instead of <F1>, <2> instead of <F2>, etc.\n" +"For verbose global help press <F1>.\n" +"For help related to the current menu entry press <?> or <h>.\n", +radiolist_instructions[] = +"Press <Up>, <Down>, <Home> or <End> to navigate a radiolist, select\n" +"with <Space>.\n" +"For help related to the current entry press <?> or <h>.\n" +"For global help press <F1>.\n", +inputbox_instructions_int[] = +"Please enter a decimal value.\n" +"Fractions will not be accepted.\n" +"Press <Enter> to apply, <Esc> to cancel.", +inputbox_instructions_hex[] = +"Please enter a hexadecimal value.\n" +"Press <Enter> to apply, <Esc> to cancel.", +inputbox_instructions_string[] = +"Please enter a string value.\n" +"Press <Enter> to apply, <Esc> to cancel.", +setmod_text[] = +"This feature depends on another feature which has been configured as a\n" +"module. As a result, the current feature will be built as a module too.", +load_config_text[] = +"Enter the name of the configuration file you wish to load.\n" +"Accept the name shown to restore the configuration you last\n" +"retrieved. Leave empty to abort.", +load_config_help[] = +"For various reasons, one may wish to keep several different\n" +"configurations available on a single machine.\n" +"\n" +"If you have saved a previous configuration in a file other than the\n" +"default one, entering its name here will allow you to load and modify\n" +"that configuration.\n" +"\n" +"Leave empty to abort.\n", +save_config_text[] = +"Enter a filename to which this configuration should be saved\n" +"as an alternate. Leave empty to abort.", +save_config_help[] = +"For various reasons, one may wish to keep several different\n" +"configurations available on a single machine.\n" +"\n" +"Entering a file name here will allow you to later retrieve, modify\n" +"and use the current configuration as an alternate to whatever\n" +"configuration options you have selected at that time.\n" +"\n" +"Leave empty to abort.\n", +search_help[] = +"Search for symbols (configuration variable names CONFIG_*) and display\n" +"their relations. Regular expressions are supported.\n" +"Example: Search for \"^FOO\".\n" +"Result:\n" +"-----------------------------------------------------------------\n" +"Symbol: FOO [ = m]\n" +"Prompt: Foo bus is used to drive the bar HW\n" +"Defined at drivers/pci/Kconfig:47\n" +"Depends on: X86_LOCAL_APIC && X86_IO_APIC || IA64\n" +"Location:\n" +" -> Bus options (PCI, PCMCIA, EISA, ISA)\n" +" -> PCI support (PCI [ = y])\n" +" -> PCI access mode (<choice> [ = y])\n" +"Selects: LIBCRC32\n" +"Selected by: BAR\n" +"-----------------------------------------------------------------\n" +"o The line 'Prompt:' shows the text displayed for this symbol in\n" +" the menu hierarchy.\n" +"o The 'Defined at' line tells at what file / line number the symbol is\n" +" defined.\n" +"o The 'Depends on:' line lists symbols that need to be defined for\n" +" this symbol to be visible and selectable in the menu.\n" +"o The 'Location:' lines tell, where in the menu structure this symbol\n" +" is located. A location followed by a [ = y] indicates that this is\n" +" a selectable menu item, and the current value is displayed inside\n" +" brackets.\n" +"o The 'Selects:' line tells, what symbol will be automatically selected\n" +" if this symbol is selected (y or m).\n" +"o The 'Selected by' line tells what symbol has selected this symbol.\n" +"\n" +"Only relevant lines are shown.\n" +"\n\n" +"Search examples:\n" +"USB => find all symbols containing USB\n" +"^USB => find all symbols starting with USB\n" +"USB$ => find all symbols ending with USB\n" +"\n"; + +struct mitem { + char str[256]; + char tag; + void *usrptr; + int is_visible; +}; + +#define MAX_MENU_ITEMS 4096 +static int show_all_items; +static int indent; +static struct menu *current_menu; +static int child_count; +static int single_menu_mode; +/* the window in which all information appears */ +static WINDOW *main_window; +/* the largest size of the menu window */ +static int mwin_max_lines; +static int mwin_max_cols; +/* the window in which we show option buttons */ +static MENU *curses_menu; +static ITEM *curses_menu_items[MAX_MENU_ITEMS]; +static struct mitem k_menu_items[MAX_MENU_ITEMS]; +static int items_num; +static int global_exit; +/* the currently selected button */ +static const char *current_instructions = menu_instructions; + +static char *dialog_input_result; +static int dialog_input_result_len; + +static void conf(struct menu *menu); +static void conf_choice(struct menu *menu); +static void conf_string(struct menu *menu); +static void conf_load(void); +static void conf_save(void); +static void show_help(struct menu *menu); +static int do_exit(void); +static void setup_windows(void); +static void search_conf(void); + +typedef void (*function_key_handler_t)(int *key, struct menu *menu); +static void handle_f1(int *key, struct menu *current_item); +static void handle_f2(int *key, struct menu *current_item); +static void handle_f3(int *key, struct menu *current_item); +static void handle_f4(int *key, struct menu *current_item); +static void handle_f5(int *key, struct menu *current_item); +static void handle_f6(int *key, struct menu *current_item); +static void handle_f7(int *key, struct menu *current_item); +static void handle_f8(int *key, struct menu *current_item); +static void handle_f9(int *key, struct menu *current_item); + +struct function_keys { + const char *key_str; + const char *func; + function_key key; + function_key_handler_t handler; +}; + +static const int function_keys_num = 9; +static struct function_keys function_keys[] = { + { + .key_str = "F1", + .func = "Help", + .key = F_HELP, + .handler = handle_f1, + }, + { + .key_str = "F2", + .func = "SymInfo", + .key = F_SYMBOL, + .handler = handle_f2, + }, + { + .key_str = "F3", + .func = "Help 2", + .key = F_INSTS, + .handler = handle_f3, + }, + { + .key_str = "F4", + .func = "ShowAll", + .key = F_CONF, + .handler = handle_f4, + }, + { + .key_str = "F5", + .func = "Back", + .key = F_BACK, + .handler = handle_f5, + }, + { + .key_str = "F6", + .func = "Save", + .key = F_SAVE, + .handler = handle_f6, + }, + { + .key_str = "F7", + .func = "Load", + .key = F_LOAD, + .handler = handle_f7, + }, + { + .key_str = "F8", + .func = "SymSearch", + .key = F_SEARCH, + .handler = handle_f8, + }, + { + .key_str = "F9", + .func = "Exit", + .key = F_EXIT, + .handler = handle_f9, + }, +}; + +static void print_function_line(void) +{ + int i; + int offset = 1; + const int skip = 1; + int lines = getmaxy(stdscr); + + for (i = 0; i < function_keys_num; i++) { + (void) wattrset(main_window, attributes[FUNCTION_HIGHLIGHT]); + mvwprintw(main_window, lines-3, offset, + "%s", + function_keys[i].key_str); + (void) wattrset(main_window, attributes[FUNCTION_TEXT]); + offset += strlen(function_keys[i].key_str); + mvwprintw(main_window, lines-3, + offset, "%s", + function_keys[i].func); + offset += strlen(function_keys[i].func) + skip; + } + (void) wattrset(main_window, attributes[NORMAL]); +} + +/* help */ +static void handle_f1(int *key, struct menu *current_item) +{ + show_scroll_win(main_window, + "Global help", nconf_global_help); + return; +} + +/* symbole help */ +static void handle_f2(int *key, struct menu *current_item) +{ + show_help(current_item); + return; +} + +/* instructions */ +static void handle_f3(int *key, struct menu *current_item) +{ + show_scroll_win(main_window, + "Short help", + current_instructions); + return; +} + +/* config */ +static void handle_f4(int *key, struct menu *current_item) +{ + int res = btn_dialog(main_window, + "Show all symbols?", + 2, + " <Show All> ", + "<Don't show all>"); + if (res == 0) + show_all_items = 1; + else if (res == 1) + show_all_items = 0; + + return; +} + +/* back */ +static void handle_f5(int *key, struct menu *current_item) +{ + *key = KEY_LEFT; + return; +} + +/* save */ +static void handle_f6(int *key, struct menu *current_item) +{ + conf_save(); + return; +} + +/* load */ +static void handle_f7(int *key, struct menu *current_item) +{ + conf_load(); + return; +} + +/* search */ +static void handle_f8(int *key, struct menu *current_item) +{ + search_conf(); + return; +} + +/* exit */ +static void handle_f9(int *key, struct menu *current_item) +{ + do_exit(); + return; +} + +/* return != 0 to indicate the key was handles */ +static int process_special_keys(int *key, struct menu *menu) +{ + int i; + + if (*key == KEY_RESIZE) { + setup_windows(); + return 1; + } + + for (i = 0; i < function_keys_num; i++) { + if (*key == KEY_F(function_keys[i].key) || + *key == '0' + function_keys[i].key){ + function_keys[i].handler(key, menu); + return 1; + } + } + + return 0; +} + +static void clean_items(void) +{ + int i; + for (i = 0; curses_menu_items[i]; i++) + free_item(curses_menu_items[i]); + bzero(curses_menu_items, sizeof(curses_menu_items)); + bzero(k_menu_items, sizeof(k_menu_items)); + items_num = 0; +} + +typedef enum {MATCH_TINKER_PATTERN_UP, MATCH_TINKER_PATTERN_DOWN, + FIND_NEXT_MATCH_DOWN, FIND_NEXT_MATCH_UP} match_f; + +/* return the index of the matched item, or -1 if no such item exists */ +static int get_mext_match(const char *match_str, match_f flag) +{ + int match_start = item_index(current_item(curses_menu)); + int index; + + if (flag == FIND_NEXT_MATCH_DOWN) + ++match_start; + else if (flag == FIND_NEXT_MATCH_UP) + --match_start; + + match_start = (match_start + items_num) % items_num; + index = match_start; + while (true) { + char *str = k_menu_items[index].str; + if (strcasestr(str, match_str) != NULL) + return index; + if (flag == FIND_NEXT_MATCH_UP || + flag == MATCH_TINKER_PATTERN_UP) + --index; + else + ++index; + index = (index + items_num) % items_num; + if (index == match_start) + return -1; + } +} + +/* Make a new item. */ +static void item_make(struct menu *menu, char tag, const char *fmt, ...) +{ + va_list ap; + + if (items_num > MAX_MENU_ITEMS-1) + return; + + bzero(&k_menu_items[items_num], sizeof(k_menu_items[0])); + k_menu_items[items_num].tag = tag; + k_menu_items[items_num].usrptr = menu; + if (menu != NULL) + k_menu_items[items_num].is_visible = + menu_is_visible(menu); + else + k_menu_items[items_num].is_visible = 1; + + va_start(ap, fmt); + vsnprintf(k_menu_items[items_num].str, + sizeof(k_menu_items[items_num].str), + fmt, ap); + va_end(ap); + + if (!k_menu_items[items_num].is_visible) + memcpy(k_menu_items[items_num].str, "XXX", 3); + + curses_menu_items[items_num] = new_item( + k_menu_items[items_num].str, + k_menu_items[items_num].str); + set_item_userptr(curses_menu_items[items_num], + &k_menu_items[items_num]); + /* + if (!k_menu_items[items_num].is_visible) + item_opts_off(curses_menu_items[items_num], O_SELECTABLE); + */ + + items_num++; + curses_menu_items[items_num] = NULL; +} + +/* very hackish. adds a string to the last item added */ +static void item_add_str(const char *fmt, ...) +{ + va_list ap; + int index = items_num-1; + char new_str[256]; + char tmp_str[256]; + + if (index < 0) + return; + + va_start(ap, fmt); + vsnprintf(new_str, sizeof(new_str), fmt, ap); + va_end(ap); + snprintf(tmp_str, sizeof(tmp_str), "%s%s", + k_menu_items[index].str, new_str); + strncpy(k_menu_items[index].str, + tmp_str, + sizeof(k_menu_items[index].str)); + + free_item(curses_menu_items[index]); + curses_menu_items[index] = new_item( + k_menu_items[index].str, + k_menu_items[index].str); + set_item_userptr(curses_menu_items[index], + &k_menu_items[index]); +} + +/* get the tag of the currently selected item */ +static char item_tag(void) +{ + ITEM *cur; + struct mitem *mcur; + + cur = current_item(curses_menu); + if (cur == NULL) + return 0; + mcur = (struct mitem *) item_userptr(cur); + return mcur->tag; +} + +static int curses_item_index(void) +{ + return item_index(current_item(curses_menu)); +} + +static void *item_data(void) +{ + ITEM *cur; + struct mitem *mcur; + + cur = current_item(curses_menu); + if (!cur) + return NULL; + mcur = (struct mitem *) item_userptr(cur); + return mcur->usrptr; + +} + +static int item_is_tag(char tag) +{ + return item_tag() == tag; +} + +static char filename[PATH_MAX+1]; +static char menu_backtitle[PATH_MAX+128]; +static const char *set_config_filename(const char *config_filename) +{ + int size; + + size = snprintf(menu_backtitle, sizeof(menu_backtitle), + "%s - %s", config_filename, rootmenu.prompt->text); + if (size >= sizeof(menu_backtitle)) + menu_backtitle[sizeof(menu_backtitle)-1] = '\0'; + + size = snprintf(filename, sizeof(filename), "%s", config_filename); + if (size >= sizeof(filename)) + filename[sizeof(filename)-1] = '\0'; + return menu_backtitle; +} + +/* return = 0 means we are successful. + * -1 means go on doing what you were doing + */ +static int do_exit(void) +{ + int res; + if (!conf_get_changed()) { + global_exit = 1; + return 0; + } + res = btn_dialog(main_window, + "Do you wish to save your new configuration?\n" + "<ESC> to cancel and resume nconfig.", + 2, + " <save> ", + "<don't save>"); + if (res == KEY_EXIT) { + global_exit = 0; + return -1; + } + + /* if we got here, the user really wants to exit */ + switch (res) { + case 0: + res = conf_write(filename); + if (res) + btn_dialog( + main_window, + "Error during writing of configuration.\n" + "Your configuration changes were NOT saved.", + 1, + "<OK>"); + conf_write_autoconf(0); + break; + default: + btn_dialog( + main_window, + "Your configuration changes were NOT saved.", + 1, + "<OK>"); + break; + } + global_exit = 1; + return 0; +} + + +static void search_conf(void) +{ + struct symbol **sym_arr; + struct gstr res; + struct gstr title; + char *dialog_input; + int dres; + + title = str_new(); + str_printf( &title, "Enter (sub)string or regexp to search for " + "(with or without \"%s\")", CONFIG_); + +again: + dres = dialog_inputbox(main_window, + "Search Configuration Parameter", + str_get(&title), + "", &dialog_input_result, &dialog_input_result_len); + switch (dres) { + case 0: + break; + case 1: + show_scroll_win(main_window, + "Search Configuration", search_help); + goto again; + default: + str_free(&title); + return; + } + + /* strip the prefix if necessary */ + dialog_input = dialog_input_result; + if (strncasecmp(dialog_input_result, CONFIG_, strlen(CONFIG_)) == 0) + dialog_input += strlen(CONFIG_); + + sym_arr = sym_re_search(dialog_input); + res = get_relations_str(sym_arr, NULL); + free(sym_arr); + show_scroll_win(main_window, + "Search Results", str_get(&res)); + str_free(&res); + str_free(&title); +} + + +static void build_conf(struct menu *menu) +{ + struct symbol *sym; + struct property *prop; + struct menu *child; + int type, tmp, doint = 2; + tristate val; + char ch; + + if (!menu || (!show_all_items && !menu_is_visible(menu))) + return; + + sym = menu->sym; + prop = menu->prompt; + if (!sym) { + if (prop && menu != current_menu) { + const char *prompt = menu_get_prompt(menu); + enum prop_type ptype; + ptype = menu->prompt ? menu->prompt->type : P_UNKNOWN; + switch (ptype) { + case P_MENU: + child_count++; + if (single_menu_mode) { + item_make(menu, 'm', + "%s%*c%s", + menu->data ? "-->" : "++>", + indent + 1, ' ', prompt); + } else + item_make(menu, 'm', + " %*c%s %s", + indent + 1, ' ', prompt, + menu_is_empty(menu) ? "----" : "--->"); + + if (single_menu_mode && menu->data) + goto conf_childs; + return; + case P_COMMENT: + if (prompt) { + child_count++; + item_make(menu, ':', + " %*c*** %s ***", + indent + 1, ' ', + prompt); + } + break; + default: + if (prompt) { + child_count++; + item_make(menu, ':', "---%*c%s", + indent + 1, ' ', + prompt); + } + } + } else + doint = 0; + goto conf_childs; + } + + type = sym_get_type(sym); + if (sym_is_choice(sym)) { + struct symbol *def_sym = sym_get_choice_value(sym); + struct menu *def_menu = NULL; + + child_count++; + for (child = menu->list; child; child = child->next) { + if (menu_is_visible(child) && child->sym == def_sym) + def_menu = child; + } + + val = sym_get_tristate_value(sym); + if (sym_is_changeable(sym)) { + switch (type) { + case S_BOOLEAN: + item_make(menu, 't', "[%c]", + val == no ? ' ' : '*'); + break; + case S_TRISTATE: + switch (val) { + case yes: + ch = '*'; + break; + case mod: + ch = 'M'; + break; + default: + ch = ' '; + break; + } + item_make(menu, 't', "<%c>", ch); + break; + } + } else { + item_make(menu, def_menu ? 't' : ':', " "); + } + + item_add_str("%*c%s", indent + 1, + ' ', menu_get_prompt(menu)); + if (val == yes) { + if (def_menu) { + item_add_str(" (%s)", + menu_get_prompt(def_menu)); + item_add_str(" --->"); + if (def_menu->list) { + indent += 2; + build_conf(def_menu); + indent -= 2; + } + } + return; + } + } else { + if (menu == current_menu) { + item_make(menu, ':', + "---%*c%s", indent + 1, + ' ', menu_get_prompt(menu)); + goto conf_childs; + } + child_count++; + val = sym_get_tristate_value(sym); + if (sym_is_choice_value(sym) && val == yes) { + item_make(menu, ':', " "); + } else { + switch (type) { + case S_BOOLEAN: + if (sym_is_changeable(sym)) + item_make(menu, 't', "[%c]", + val == no ? ' ' : '*'); + else + item_make(menu, 't', "-%c-", + val == no ? ' ' : '*'); + break; + case S_TRISTATE: + switch (val) { + case yes: + ch = '*'; + break; + case mod: + ch = 'M'; + break; + default: + ch = ' '; + break; + } + if (sym_is_changeable(sym)) { + if (sym->rev_dep.tri == mod) + item_make(menu, + 't', "{%c}", ch); + else + item_make(menu, + 't', "<%c>", ch); + } else + item_make(menu, 't', "-%c-", ch); + break; + default: + tmp = 2 + strlen(sym_get_string_value(sym)); + item_make(menu, 's', " (%s)", + sym_get_string_value(sym)); + tmp = indent - tmp + 4; + if (tmp < 0) + tmp = 0; + item_add_str("%*c%s%s", tmp, ' ', + menu_get_prompt(menu), + (sym_has_value(sym) || + !sym_is_changeable(sym)) ? "" : + " (NEW)"); + goto conf_childs; + } + } + item_add_str("%*c%s%s", indent + 1, ' ', + menu_get_prompt(menu), + (sym_has_value(sym) || !sym_is_changeable(sym)) ? + "" : " (NEW)"); + if (menu->prompt && menu->prompt->type == P_MENU) { + item_add_str(" %s", menu_is_empty(menu) ? "----" : "--->"); + return; + } + } + +conf_childs: + indent += doint; + for (child = menu->list; child; child = child->next) + build_conf(child); + indent -= doint; +} + +static void reset_menu(void) +{ + unpost_menu(curses_menu); + clean_items(); +} + +/* adjust the menu to show this item. + * prefer not to scroll the menu if possible*/ +static void center_item(int selected_index, int *last_top_row) +{ + int toprow; + + set_top_row(curses_menu, *last_top_row); + toprow = top_row(curses_menu); + if (selected_index < toprow || + selected_index >= toprow+mwin_max_lines) { + toprow = max(selected_index-mwin_max_lines/2, 0); + if (toprow >= item_count(curses_menu)-mwin_max_lines) + toprow = item_count(curses_menu)-mwin_max_lines; + set_top_row(curses_menu, toprow); + } + set_current_item(curses_menu, + curses_menu_items[selected_index]); + *last_top_row = toprow; + post_menu(curses_menu); + refresh_all_windows(main_window); +} + +/* this function assumes reset_menu has been called before */ +static void show_menu(const char *prompt, const char *instructions, + int selected_index, int *last_top_row) +{ + int maxx, maxy; + WINDOW *menu_window; + + current_instructions = instructions; + + clear(); + (void) wattrset(main_window, attributes[NORMAL]); + print_in_middle(stdscr, 1, 0, getmaxx(stdscr), + menu_backtitle, + attributes[MAIN_HEADING]); + + (void) wattrset(main_window, attributes[MAIN_MENU_BOX]); + box(main_window, 0, 0); + (void) wattrset(main_window, attributes[MAIN_MENU_HEADING]); + mvwprintw(main_window, 0, 3, " %s ", prompt); + (void) wattrset(main_window, attributes[NORMAL]); + + set_menu_items(curses_menu, curses_menu_items); + + /* position the menu at the middle of the screen */ + scale_menu(curses_menu, &maxy, &maxx); + maxx = min(maxx, mwin_max_cols-2); + maxy = mwin_max_lines; + menu_window = derwin(main_window, + maxy, + maxx, + 2, + (mwin_max_cols-maxx)/2); + keypad(menu_window, TRUE); + set_menu_win(curses_menu, menu_window); + set_menu_sub(curses_menu, menu_window); + + /* must reassert this after changing items, otherwise returns to a + * default of 16 + */ + set_menu_format(curses_menu, maxy, 1); + center_item(selected_index, last_top_row); + set_menu_format(curses_menu, maxy, 1); + + print_function_line(); + + /* Post the menu */ + post_menu(curses_menu); + refresh_all_windows(main_window); +} + +static void adj_match_dir(match_f *match_direction) +{ + if (*match_direction == FIND_NEXT_MATCH_DOWN) + *match_direction = + MATCH_TINKER_PATTERN_DOWN; + else if (*match_direction == FIND_NEXT_MATCH_UP) + *match_direction = + MATCH_TINKER_PATTERN_UP; + /* else, do no change.. */ +} + +struct match_state +{ + int in_search; + match_f match_direction; + char pattern[256]; +}; + +/* Return 0 means I have handled the key. In such a case, ans should hold the + * item to center, or -1 otherwise. + * Else return -1 . + */ +static int do_match(int key, struct match_state *state, int *ans) +{ + char c = (char) key; + int terminate_search = 0; + *ans = -1; + if (key == '/' || (state->in_search && key == 27)) { + move(0, 0); + refresh(); + clrtoeol(); + state->in_search = 1-state->in_search; + bzero(state->pattern, sizeof(state->pattern)); + state->match_direction = MATCH_TINKER_PATTERN_DOWN; + return 0; + } else if (!state->in_search) + return 1; + + if (isalnum(c) || isgraph(c) || c == ' ') { + state->pattern[strlen(state->pattern)] = c; + state->pattern[strlen(state->pattern)] = '\0'; + adj_match_dir(&state->match_direction); + *ans = get_mext_match(state->pattern, + state->match_direction); + } else if (key == KEY_DOWN) { + state->match_direction = FIND_NEXT_MATCH_DOWN; + *ans = get_mext_match(state->pattern, + state->match_direction); + } else if (key == KEY_UP) { + state->match_direction = FIND_NEXT_MATCH_UP; + *ans = get_mext_match(state->pattern, + state->match_direction); + } else if (key == KEY_BACKSPACE || key == 8 || key == 127) { + state->pattern[strlen(state->pattern)-1] = '\0'; + adj_match_dir(&state->match_direction); + } else + terminate_search = 1; + + if (terminate_search) { + state->in_search = 0; + bzero(state->pattern, sizeof(state->pattern)); + move(0, 0); + refresh(); + clrtoeol(); + return -1; + } + return 0; +} + +static void conf(struct menu *menu) +{ + struct menu *submenu = NULL; + const char *prompt = menu_get_prompt(menu); + struct symbol *sym; + int res; + int current_index = 0; + int last_top_row = 0; + struct match_state match_state = { + .in_search = 0, + .match_direction = MATCH_TINKER_PATTERN_DOWN, + .pattern = "", + }; + + while (!global_exit) { + reset_menu(); + current_menu = menu; + build_conf(menu); + if (!child_count) + break; + + show_menu(prompt ? prompt : "Main Menu", + menu_instructions, + current_index, &last_top_row); + keypad((menu_win(curses_menu)), TRUE); + while (!global_exit) { + if (match_state.in_search) { + mvprintw(0, 0, + "searching: %s", match_state.pattern); + clrtoeol(); + } + refresh_all_windows(main_window); + res = wgetch(menu_win(curses_menu)); + if (!res) + break; + if (do_match(res, &match_state, ¤t_index) == 0) { + if (current_index != -1) + center_item(current_index, + &last_top_row); + continue; + } + if (process_special_keys(&res, + (struct menu *) item_data())) + break; + switch (res) { + case KEY_DOWN: + menu_driver(curses_menu, REQ_DOWN_ITEM); + break; + case KEY_UP: + menu_driver(curses_menu, REQ_UP_ITEM); + break; + case KEY_NPAGE: + menu_driver(curses_menu, REQ_SCR_DPAGE); + break; + case KEY_PPAGE: + menu_driver(curses_menu, REQ_SCR_UPAGE); + break; + case KEY_HOME: + menu_driver(curses_menu, REQ_FIRST_ITEM); + break; + case KEY_END: + menu_driver(curses_menu, REQ_LAST_ITEM); + break; + case 'h': + case '?': + show_help((struct menu *) item_data()); + break; + } + if (res == 10 || res == 27 || + res == 32 || res == 'n' || res == 'y' || + res == KEY_LEFT || res == KEY_RIGHT || + res == 'm') + break; + refresh_all_windows(main_window); + } + + refresh_all_windows(main_window); + /* if ESC or left*/ + if (res == 27 || (menu != &rootmenu && res == KEY_LEFT)) + break; + + /* remember location in the menu */ + last_top_row = top_row(curses_menu); + current_index = curses_item_index(); + + if (!item_tag()) + continue; + + submenu = (struct menu *) item_data(); + if (!submenu || !menu_is_visible(submenu)) + continue; + sym = submenu->sym; + + switch (res) { + case ' ': + if (item_is_tag('t')) + sym_toggle_tristate_value(sym); + else if (item_is_tag('m')) + conf(submenu); + break; + case KEY_RIGHT: + case 10: /* ENTER WAS PRESSED */ + switch (item_tag()) { + case 'm': + if (single_menu_mode) + submenu->data = + (void *) (long) !submenu->data; + else + conf(submenu); + break; + case 't': + if (sym_is_choice(sym) && + sym_get_tristate_value(sym) == yes) + conf_choice(submenu); + else if (submenu->prompt && + submenu->prompt->type == P_MENU) + conf(submenu); + else if (res == 10) + sym_toggle_tristate_value(sym); + break; + case 's': + conf_string(submenu); + break; + } + break; + case 'y': + if (item_is_tag('t')) { + if (sym_set_tristate_value(sym, yes)) + break; + if (sym_set_tristate_value(sym, mod)) + btn_dialog(main_window, setmod_text, 0); + } + break; + case 'n': + if (item_is_tag('t')) + sym_set_tristate_value(sym, no); + break; + case 'm': + if (item_is_tag('t')) + sym_set_tristate_value(sym, mod); + break; + } + } +} + +static void conf_message_callback(const char *s) +{ + btn_dialog(main_window, s, 1, "<OK>"); +} + +static void show_help(struct menu *menu) +{ + struct gstr help; + + if (!menu) + return; + + help = str_new(); + menu_get_ext_help(menu, &help); + show_scroll_win(main_window, menu_get_prompt(menu), str_get(&help)); + str_free(&help); +} + +static void conf_choice(struct menu *menu) +{ + const char *prompt = menu_get_prompt(menu); + struct menu *child = NULL; + struct symbol *active; + int selected_index = 0; + int last_top_row = 0; + int res, i = 0; + struct match_state match_state = { + .in_search = 0, + .match_direction = MATCH_TINKER_PATTERN_DOWN, + .pattern = "", + }; + + active = sym_get_choice_value(menu->sym); + /* this is mostly duplicated from the conf() function. */ + while (!global_exit) { + reset_menu(); + + for (i = 0, child = menu->list; child; child = child->next) { + if (!show_all_items && !menu_is_visible(child)) + continue; + + if (child->sym == sym_get_choice_value(menu->sym)) + item_make(child, ':', "<X> %s", + menu_get_prompt(child)); + else if (child->sym) + item_make(child, ':', " %s", + menu_get_prompt(child)); + else + item_make(child, ':', "*** %s ***", + menu_get_prompt(child)); + + if (child->sym == active){ + last_top_row = top_row(curses_menu); + selected_index = i; + } + i++; + } + show_menu(prompt ? prompt : "Choice Menu", + radiolist_instructions, + selected_index, + &last_top_row); + while (!global_exit) { + if (match_state.in_search) { + mvprintw(0, 0, "searching: %s", + match_state.pattern); + clrtoeol(); + } + refresh_all_windows(main_window); + res = wgetch(menu_win(curses_menu)); + if (!res) + break; + if (do_match(res, &match_state, &selected_index) == 0) { + if (selected_index != -1) + center_item(selected_index, + &last_top_row); + continue; + } + if (process_special_keys( + &res, + (struct menu *) item_data())) + break; + switch (res) { + case KEY_DOWN: + menu_driver(curses_menu, REQ_DOWN_ITEM); + break; + case KEY_UP: + menu_driver(curses_menu, REQ_UP_ITEM); + break; + case KEY_NPAGE: + menu_driver(curses_menu, REQ_SCR_DPAGE); + break; + case KEY_PPAGE: + menu_driver(curses_menu, REQ_SCR_UPAGE); + break; + case KEY_HOME: + menu_driver(curses_menu, REQ_FIRST_ITEM); + break; + case KEY_END: + menu_driver(curses_menu, REQ_LAST_ITEM); + break; + case 'h': + case '?': + show_help((struct menu *) item_data()); + break; + } + if (res == 10 || res == 27 || res == ' ' || + res == KEY_LEFT){ + break; + } + refresh_all_windows(main_window); + } + /* if ESC or left */ + if (res == 27 || res == KEY_LEFT) + break; + + child = item_data(); + if (!child || !menu_is_visible(child) || !child->sym) + continue; + switch (res) { + case ' ': + case 10: + case KEY_RIGHT: + sym_set_tristate_value(child->sym, yes); + return; + case 'h': + case '?': + show_help(child); + active = child->sym; + break; + case KEY_EXIT: + return; + } + } +} + +static void conf_string(struct menu *menu) +{ + const char *prompt = menu_get_prompt(menu); + + while (1) { + int res; + const char *heading; + + switch (sym_get_type(menu->sym)) { + case S_INT: + heading = inputbox_instructions_int; + break; + case S_HEX: + heading = inputbox_instructions_hex; + break; + case S_STRING: + heading = inputbox_instructions_string; + break; + default: + heading = "Internal nconf error!"; + } + res = dialog_inputbox(main_window, + prompt ? prompt : "Main Menu", + heading, + sym_get_string_value(menu->sym), + &dialog_input_result, + &dialog_input_result_len); + switch (res) { + case 0: + if (sym_set_string_value(menu->sym, + dialog_input_result)) + return; + btn_dialog(main_window, + "You have made an invalid entry.", 0); + break; + case 1: + show_help(menu); + break; + case KEY_EXIT: + return; + } + } +} + +static void conf_load(void) +{ + while (1) { + int res; + res = dialog_inputbox(main_window, + NULL, load_config_text, + filename, + &dialog_input_result, + &dialog_input_result_len); + switch (res) { + case 0: + if (!dialog_input_result[0]) + return; + if (!conf_read(dialog_input_result)) { + set_config_filename(dialog_input_result); + sym_set_change_count(1); + return; + } + btn_dialog(main_window, "File does not exist!", 0); + break; + case 1: + show_scroll_win(main_window, + "Load Alternate Configuration", + load_config_help); + break; + case KEY_EXIT: + return; + } + } +} + +static void conf_save(void) +{ + while (1) { + int res; + res = dialog_inputbox(main_window, + NULL, save_config_text, + filename, + &dialog_input_result, + &dialog_input_result_len); + switch (res) { + case 0: + if (!dialog_input_result[0]) + return; + res = conf_write(dialog_input_result); + if (!res) { + set_config_filename(dialog_input_result); + return; + } + btn_dialog(main_window, "Can't create file!", + 1, "<OK>"); + break; + case 1: + show_scroll_win(main_window, + "Save Alternate Configuration", + save_config_help); + break; + case KEY_EXIT: + return; + } + } +} + +static void setup_windows(void) +{ + int lines, columns; + + getmaxyx(stdscr, lines, columns); + + if (main_window != NULL) + delwin(main_window); + + /* set up the menu and menu window */ + main_window = newwin(lines-2, columns-2, 2, 1); + keypad(main_window, TRUE); + mwin_max_lines = lines-7; + mwin_max_cols = columns-6; + + /* panels order is from bottom to top */ + new_panel(main_window); +} + +int main(int ac, char **av) +{ + int lines, columns; + char *mode; + + if (ac > 1 && strcmp(av[1], "-s") == 0) { + /* Silence conf_read() until the real callback is set up */ + conf_set_message_callback(NULL); + av++; + } + conf_parse(av[1]); + conf_read(NULL); + + mode = getenv("NCONFIG_MODE"); + if (mode) { + if (!strcasecmp(mode, "single_menu")) + single_menu_mode = 1; + } + + /* Initialize curses */ + initscr(); + /* set color theme */ + set_colors(); + + cbreak(); + noecho(); + keypad(stdscr, TRUE); + curs_set(0); + + getmaxyx(stdscr, lines, columns); + if (columns < 75 || lines < 20) { + endwin(); + printf("Your terminal should have at " + "least 20 lines and 75 columns\n"); + return 1; + } + + notimeout(stdscr, FALSE); +#if NCURSES_REENTRANT + set_escdelay(1); +#else + ESCDELAY = 1; +#endif + + /* set btns menu */ + curses_menu = new_menu(curses_menu_items); + menu_opts_off(curses_menu, O_SHOWDESC); + menu_opts_on(curses_menu, O_SHOWMATCH); + menu_opts_on(curses_menu, O_ONEVALUE); + menu_opts_on(curses_menu, O_NONCYCLIC); + menu_opts_on(curses_menu, O_IGNORECASE); + set_menu_mark(curses_menu, " "); + set_menu_fore(curses_menu, attributes[MAIN_MENU_FORE]); + set_menu_back(curses_menu, attributes[MAIN_MENU_BACK]); + set_menu_grey(curses_menu, attributes[MAIN_MENU_GREY]); + + set_config_filename(conf_get_configname()); + setup_windows(); + + /* check for KEY_FUNC(1) */ + if (has_key(KEY_F(1)) == FALSE) { + show_scroll_win(main_window, + "Instructions", + menu_no_f_instructions); + } + + conf_set_message_callback(conf_message_callback); + /* do the work */ + while (!global_exit) { + conf(&rootmenu); + if (!global_exit && do_exit() == 0) + break; + } + /* ok, we are done */ + unpost_menu(curses_menu); + free_menu(curses_menu); + delwin(main_window); + clear(); + refresh(); + endwin(); + return 0; +} diff --git a/src/net/scripts/kconfig/nconf.gui.c b/src/net/scripts/kconfig/nconf.gui.c new file mode 100644 index 0000000..77f525a --- /dev/null +++ b/src/net/scripts/kconfig/nconf.gui.c @@ -0,0 +1,664 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2008 Nir Tzachar <nir.tzachar@gmail.com> + * + * Derived from menuconfig. + */ +#include "nconf.h" +#include "lkc.h" + +/* a list of all the different widgets we use */ +attributes_t attributes[ATTR_MAX+1] = {0}; + +/* available colors: + COLOR_BLACK 0 + COLOR_RED 1 + COLOR_GREEN 2 + COLOR_YELLOW 3 + COLOR_BLUE 4 + COLOR_MAGENTA 5 + COLOR_CYAN 6 + COLOR_WHITE 7 + */ +static void set_normal_colors(void) +{ + init_pair(NORMAL, -1, -1); + init_pair(MAIN_HEADING, COLOR_MAGENTA, -1); + + /* FORE is for the selected item */ + init_pair(MAIN_MENU_FORE, -1, -1); + /* BACK for all the rest */ + init_pair(MAIN_MENU_BACK, -1, -1); + init_pair(MAIN_MENU_GREY, -1, -1); + init_pair(MAIN_MENU_HEADING, COLOR_GREEN, -1); + init_pair(MAIN_MENU_BOX, COLOR_YELLOW, -1); + + init_pair(SCROLLWIN_TEXT, -1, -1); + init_pair(SCROLLWIN_HEADING, COLOR_GREEN, -1); + init_pair(SCROLLWIN_BOX, COLOR_YELLOW, -1); + + init_pair(DIALOG_TEXT, -1, -1); + init_pair(DIALOG_BOX, COLOR_YELLOW, -1); + init_pair(DIALOG_MENU_BACK, COLOR_YELLOW, -1); + init_pair(DIALOG_MENU_FORE, COLOR_RED, -1); + + init_pair(INPUT_BOX, COLOR_YELLOW, -1); + init_pair(INPUT_HEADING, COLOR_GREEN, -1); + init_pair(INPUT_TEXT, -1, -1); + init_pair(INPUT_FIELD, -1, -1); + + init_pair(FUNCTION_HIGHLIGHT, -1, -1); + init_pair(FUNCTION_TEXT, COLOR_YELLOW, -1); +} + +/* available attributes: + A_NORMAL Normal display (no highlight) + A_STANDOUT Best highlighting mode of the terminal. + A_UNDERLINE Underlining + A_REVERSE Reverse video + A_BLINK Blinking + A_DIM Half bright + A_BOLD Extra bright or bold + A_PROTECT Protected mode + A_INVIS Invisible or blank mode + A_ALTCHARSET Alternate character set + A_CHARTEXT Bit-mask to extract a character + COLOR_PAIR(n) Color-pair number n + */ +static void normal_color_theme(void) +{ + /* automatically add color... */ +#define mkattr(name, attr) do { \ +attributes[name] = attr | COLOR_PAIR(name); } while (0) + mkattr(NORMAL, NORMAL); + mkattr(MAIN_HEADING, A_BOLD | A_UNDERLINE); + + mkattr(MAIN_MENU_FORE, A_REVERSE); + mkattr(MAIN_MENU_BACK, A_NORMAL); + mkattr(MAIN_MENU_GREY, A_NORMAL); + mkattr(MAIN_MENU_HEADING, A_BOLD); + mkattr(MAIN_MENU_BOX, A_NORMAL); + + mkattr(SCROLLWIN_TEXT, A_NORMAL); + mkattr(SCROLLWIN_HEADING, A_BOLD); + mkattr(SCROLLWIN_BOX, A_BOLD); + + mkattr(DIALOG_TEXT, A_BOLD); + mkattr(DIALOG_BOX, A_BOLD); + mkattr(DIALOG_MENU_FORE, A_STANDOUT); + mkattr(DIALOG_MENU_BACK, A_NORMAL); + + mkattr(INPUT_BOX, A_NORMAL); + mkattr(INPUT_HEADING, A_BOLD); + mkattr(INPUT_TEXT, A_NORMAL); + mkattr(INPUT_FIELD, A_UNDERLINE); + + mkattr(FUNCTION_HIGHLIGHT, A_BOLD); + mkattr(FUNCTION_TEXT, A_REVERSE); +} + +static void no_colors_theme(void) +{ + /* automatically add highlight, no color */ +#define mkattrn(name, attr) { attributes[name] = attr; } + + mkattrn(NORMAL, NORMAL); + mkattrn(MAIN_HEADING, A_BOLD | A_UNDERLINE); + + mkattrn(MAIN_MENU_FORE, A_STANDOUT); + mkattrn(MAIN_MENU_BACK, A_NORMAL); + mkattrn(MAIN_MENU_GREY, A_NORMAL); + mkattrn(MAIN_MENU_HEADING, A_BOLD); + mkattrn(MAIN_MENU_BOX, A_NORMAL); + + mkattrn(SCROLLWIN_TEXT, A_NORMAL); + mkattrn(SCROLLWIN_HEADING, A_BOLD); + mkattrn(SCROLLWIN_BOX, A_BOLD); + + mkattrn(DIALOG_TEXT, A_NORMAL); + mkattrn(DIALOG_BOX, A_BOLD); + mkattrn(DIALOG_MENU_FORE, A_STANDOUT); + mkattrn(DIALOG_MENU_BACK, A_NORMAL); + + mkattrn(INPUT_BOX, A_BOLD); + mkattrn(INPUT_HEADING, A_BOLD); + mkattrn(INPUT_TEXT, A_NORMAL); + mkattrn(INPUT_FIELD, A_UNDERLINE); + + mkattrn(FUNCTION_HIGHLIGHT, A_BOLD); + mkattrn(FUNCTION_TEXT, A_REVERSE); +} + +void set_colors(void) +{ + start_color(); + use_default_colors(); + set_normal_colors(); + if (has_colors()) { + normal_color_theme(); + } else { + /* give defaults */ + no_colors_theme(); + } +} + + +/* this changes the windows attributes !!! */ +void print_in_middle(WINDOW *win, + int starty, + int startx, + int width, + const char *string, + chtype color) +{ int length, x, y; + float temp; + + + if (win == NULL) + win = stdscr; + getyx(win, y, x); + if (startx != 0) + x = startx; + if (starty != 0) + y = starty; + if (width == 0) + width = 80; + + length = strlen(string); + temp = (width - length) / 2; + x = startx + (int)temp; + (void) wattrset(win, color); + mvwprintw(win, y, x, "%s", string); + refresh(); +} + +int get_line_no(const char *text) +{ + int i; + int total = 1; + + if (!text) + return 0; + + for (i = 0; text[i] != '\0'; i++) + if (text[i] == '\n') + total++; + return total; +} + +const char *get_line(const char *text, int line_no) +{ + int i; + int lines = 0; + + if (!text) + return NULL; + + for (i = 0; text[i] != '\0' && lines < line_no; i++) + if (text[i] == '\n') + lines++; + return text+i; +} + +int get_line_length(const char *line) +{ + int res = 0; + while (*line != '\0' && *line != '\n') { + line++; + res++; + } + return res; +} + +/* print all lines to the window. */ +void fill_window(WINDOW *win, const char *text) +{ + int x, y; + int total_lines = get_line_no(text); + int i; + + getmaxyx(win, y, x); + /* do not go over end of line */ + total_lines = min(total_lines, y); + for (i = 0; i < total_lines; i++) { + char tmp[x+10]; + const char *line = get_line(text, i); + int len = get_line_length(line); + strncpy(tmp, line, min(len, x)); + tmp[len] = '\0'; + mvwprintw(win, i, 0, "%s", tmp); + } +} + +/* get the message, and buttons. + * each button must be a char* + * return the selected button + * + * this dialog is used for 2 different things: + * 1) show a text box, no buttons. + * 2) show a dialog, with horizontal buttons + */ +int btn_dialog(WINDOW *main_window, const char *msg, int btn_num, ...) +{ + va_list ap; + char *btn; + int btns_width = 0; + int msg_lines = 0; + int msg_width = 0; + int total_width; + int win_rows = 0; + WINDOW *win; + WINDOW *msg_win; + WINDOW *menu_win; + MENU *menu; + ITEM *btns[btn_num+1]; + int i, x, y; + int res = -1; + + + va_start(ap, btn_num); + for (i = 0; i < btn_num; i++) { + btn = va_arg(ap, char *); + btns[i] = new_item(btn, ""); + btns_width += strlen(btn)+1; + } + va_end(ap); + btns[btn_num] = NULL; + + /* find the widest line of msg: */ + msg_lines = get_line_no(msg); + for (i = 0; i < msg_lines; i++) { + const char *line = get_line(msg, i); + int len = get_line_length(line); + if (msg_width < len) + msg_width = len; + } + + total_width = max(msg_width, btns_width); + /* place dialog in middle of screen */ + y = (getmaxy(stdscr)-(msg_lines+4))/2; + x = (getmaxx(stdscr)-(total_width+4))/2; + + + /* create the windows */ + if (btn_num > 0) + win_rows = msg_lines+4; + else + win_rows = msg_lines+2; + + win = newwin(win_rows, total_width+4, y, x); + keypad(win, TRUE); + menu_win = derwin(win, 1, btns_width, win_rows-2, + 1+(total_width+2-btns_width)/2); + menu = new_menu(btns); + msg_win = derwin(win, win_rows-2, msg_width, 1, + 1+(total_width+2-msg_width)/2); + + set_menu_fore(menu, attributes[DIALOG_MENU_FORE]); + set_menu_back(menu, attributes[DIALOG_MENU_BACK]); + + (void) wattrset(win, attributes[DIALOG_BOX]); + box(win, 0, 0); + + /* print message */ + (void) wattrset(msg_win, attributes[DIALOG_TEXT]); + fill_window(msg_win, msg); + + set_menu_win(menu, win); + set_menu_sub(menu, menu_win); + set_menu_format(menu, 1, btn_num); + menu_opts_off(menu, O_SHOWDESC); + menu_opts_off(menu, O_SHOWMATCH); + menu_opts_on(menu, O_ONEVALUE); + menu_opts_on(menu, O_NONCYCLIC); + set_menu_mark(menu, ""); + post_menu(menu); + + + touchwin(win); + refresh_all_windows(main_window); + while ((res = wgetch(win))) { + switch (res) { + case KEY_LEFT: + menu_driver(menu, REQ_LEFT_ITEM); + break; + case KEY_RIGHT: + menu_driver(menu, REQ_RIGHT_ITEM); + break; + case 10: /* ENTER */ + case 27: /* ESCAPE */ + case ' ': + case KEY_F(F_BACK): + case KEY_F(F_EXIT): + break; + } + touchwin(win); + refresh_all_windows(main_window); + + if (res == 10 || res == ' ') { + res = item_index(current_item(menu)); + break; + } else if (res == 27 || res == KEY_F(F_BACK) || + res == KEY_F(F_EXIT)) { + res = KEY_EXIT; + break; + } + } + + unpost_menu(menu); + free_menu(menu); + for (i = 0; i < btn_num; i++) + free_item(btns[i]); + + delwin(win); + return res; +} + +int dialog_inputbox(WINDOW *main_window, + const char *title, const char *prompt, + const char *init, char **resultp, int *result_len) +{ + int prompt_lines = 0; + int prompt_width = 0; + WINDOW *win; + WINDOW *prompt_win; + WINDOW *form_win; + PANEL *panel; + int i, x, y, lines, columns, win_lines, win_cols; + int res = -1; + int cursor_position = strlen(init); + int cursor_form_win; + char *result = *resultp; + + getmaxyx(stdscr, lines, columns); + + if (strlen(init)+1 > *result_len) { + *result_len = strlen(init)+1; + *resultp = result = xrealloc(result, *result_len); + } + + /* find the widest line of msg: */ + prompt_lines = get_line_no(prompt); + for (i = 0; i < prompt_lines; i++) { + const char *line = get_line(prompt, i); + int len = get_line_length(line); + prompt_width = max(prompt_width, len); + } + + if (title) + prompt_width = max(prompt_width, strlen(title)); + + win_lines = min(prompt_lines+6, lines-2); + win_cols = min(prompt_width+7, columns-2); + prompt_lines = max(win_lines-6, 0); + prompt_width = max(win_cols-7, 0); + + /* place dialog in middle of screen */ + y = (lines-win_lines)/2; + x = (columns-win_cols)/2; + + strncpy(result, init, *result_len); + + /* create the windows */ + win = newwin(win_lines, win_cols, y, x); + prompt_win = derwin(win, prompt_lines+1, prompt_width, 2, 2); + form_win = derwin(win, 1, prompt_width, prompt_lines+3, 2); + keypad(form_win, TRUE); + + (void) wattrset(form_win, attributes[INPUT_FIELD]); + + (void) wattrset(win, attributes[INPUT_BOX]); + box(win, 0, 0); + (void) wattrset(win, attributes[INPUT_HEADING]); + if (title) + mvwprintw(win, 0, 3, "%s", title); + + /* print message */ + (void) wattrset(prompt_win, attributes[INPUT_TEXT]); + fill_window(prompt_win, prompt); + + mvwprintw(form_win, 0, 0, "%*s", prompt_width, " "); + cursor_form_win = min(cursor_position, prompt_width-1); + mvwprintw(form_win, 0, 0, "%s", + result + cursor_position-cursor_form_win); + + /* create panels */ + panel = new_panel(win); + + /* show the cursor */ + curs_set(1); + + touchwin(win); + refresh_all_windows(main_window); + while ((res = wgetch(form_win))) { + int len = strlen(result); + switch (res) { + case 10: /* ENTER */ + case 27: /* ESCAPE */ + case KEY_F(F_HELP): + case KEY_F(F_EXIT): + case KEY_F(F_BACK): + break; + case 8: /* ^H */ + case 127: /* ^? */ + case KEY_BACKSPACE: + if (cursor_position > 0) { + memmove(&result[cursor_position-1], + &result[cursor_position], + len-cursor_position+1); + cursor_position--; + cursor_form_win--; + len--; + } + break; + case KEY_DC: + if (cursor_position >= 0 && cursor_position < len) { + memmove(&result[cursor_position], + &result[cursor_position+1], + len-cursor_position+1); + len--; + } + break; + case KEY_UP: + case KEY_RIGHT: + if (cursor_position < len) { + cursor_position++; + cursor_form_win++; + } + break; + case KEY_DOWN: + case KEY_LEFT: + if (cursor_position > 0) { + cursor_position--; + cursor_form_win--; + } + break; + case KEY_HOME: + cursor_position = 0; + cursor_form_win = 0; + break; + case KEY_END: + cursor_position = len; + cursor_form_win = min(cursor_position, prompt_width-1); + break; + default: + if ((isgraph(res) || isspace(res))) { + /* one for new char, one for '\0' */ + if (len+2 > *result_len) { + *result_len = len+2; + *resultp = result = realloc(result, + *result_len); + } + /* insert the char at the proper position */ + memmove(&result[cursor_position+1], + &result[cursor_position], + len-cursor_position+1); + result[cursor_position] = res; + cursor_position++; + cursor_form_win++; + len++; + } else { + mvprintw(0, 0, "unknown key: %d\n", res); + } + break; + } + if (cursor_form_win < 0) + cursor_form_win = 0; + else if (cursor_form_win > prompt_width-1) + cursor_form_win = prompt_width-1; + + wmove(form_win, 0, 0); + wclrtoeol(form_win); + mvwprintw(form_win, 0, 0, "%*s", prompt_width, " "); + mvwprintw(form_win, 0, 0, "%s", + result + cursor_position-cursor_form_win); + wmove(form_win, 0, cursor_form_win); + touchwin(win); + refresh_all_windows(main_window); + + if (res == 10) { + res = 0; + break; + } else if (res == 27 || res == KEY_F(F_BACK) || + res == KEY_F(F_EXIT)) { + res = KEY_EXIT; + break; + } else if (res == KEY_F(F_HELP)) { + res = 1; + break; + } + } + + /* hide the cursor */ + curs_set(0); + del_panel(panel); + delwin(prompt_win); + delwin(form_win); + delwin(win); + return res; +} + +/* refresh all windows in the correct order */ +void refresh_all_windows(WINDOW *main_window) +{ + update_panels(); + touchwin(main_window); + refresh(); +} + +/* layman's scrollable window... */ +void show_scroll_win(WINDOW *main_window, + const char *title, + const char *text) +{ + int res; + int total_lines = get_line_no(text); + int x, y, lines, columns; + int start_x = 0, start_y = 0; + int text_lines = 0, text_cols = 0; + int total_cols = 0; + int win_cols = 0; + int win_lines = 0; + int i = 0; + WINDOW *win; + WINDOW *pad; + PANEL *panel; + + getmaxyx(stdscr, lines, columns); + + /* find the widest line of msg: */ + total_lines = get_line_no(text); + for (i = 0; i < total_lines; i++) { + const char *line = get_line(text, i); + int len = get_line_length(line); + total_cols = max(total_cols, len+2); + } + + /* create the pad */ + pad = newpad(total_lines+10, total_cols+10); + (void) wattrset(pad, attributes[SCROLLWIN_TEXT]); + fill_window(pad, text); + + win_lines = min(total_lines+4, lines-2); + win_cols = min(total_cols+2, columns-2); + text_lines = max(win_lines-4, 0); + text_cols = max(win_cols-2, 0); + + /* place window in middle of screen */ + y = (lines-win_lines)/2; + x = (columns-win_cols)/2; + + win = newwin(win_lines, win_cols, y, x); + keypad(win, TRUE); + /* show the help in the help window, and show the help panel */ + (void) wattrset(win, attributes[SCROLLWIN_BOX]); + box(win, 0, 0); + (void) wattrset(win, attributes[SCROLLWIN_HEADING]); + mvwprintw(win, 0, 3, " %s ", title); + panel = new_panel(win); + + /* handle scrolling */ + do { + + copywin(pad, win, start_y, start_x, 2, 2, text_lines, + text_cols, 0); + print_in_middle(win, + text_lines+2, + 0, + text_cols, + "<OK>", + attributes[DIALOG_MENU_FORE]); + wrefresh(win); + + res = wgetch(win); + switch (res) { + case KEY_NPAGE: + case ' ': + case 'd': + start_y += text_lines-2; + break; + case KEY_PPAGE: + case 'u': + start_y -= text_lines+2; + break; + case KEY_HOME: + start_y = 0; + break; + case KEY_END: + start_y = total_lines-text_lines; + break; + case KEY_DOWN: + case 'j': + start_y++; + break; + case KEY_UP: + case 'k': + start_y--; + break; + case KEY_LEFT: + case 'h': + start_x--; + break; + case KEY_RIGHT: + case 'l': + start_x++; + break; + } + if (res == 10 || res == 27 || res == 'q' || + res == KEY_F(F_HELP) || res == KEY_F(F_BACK) || + res == KEY_F(F_EXIT)) + break; + if (start_y < 0) + start_y = 0; + if (start_y >= total_lines-text_lines) + start_y = total_lines-text_lines; + if (start_x < 0) + start_x = 0; + if (start_x >= total_cols-text_cols) + start_x = total_cols-text_cols; + } while (res); + + del_panel(panel); + delwin(win); + refresh_all_windows(main_window); +} diff --git a/src/net/scripts/kconfig/nconf.h b/src/net/scripts/kconfig/nconf.h new file mode 100644 index 0000000..fa5245e --- /dev/null +++ b/src/net/scripts/kconfig/nconf.h @@ -0,0 +1,92 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2008 Nir Tzachar <nir.tzachar@gmail.com> + * + * Derived from menuconfig. + */ + +#include <ctype.h> +#include <errno.h> +#include <fcntl.h> +#include <limits.h> +#include <stdarg.h> +#include <stdlib.h> +#include <string.h> +#include <unistd.h> +#include <ncurses.h> +#include <menu.h> +#include <panel.h> +#include <form.h> + +#include <stdio.h> +#include <time.h> +#include <sys/time.h> + +#define max(a, b) ({\ + typeof(a) _a = a;\ + typeof(b) _b = b;\ + _a > _b ? _a : _b; }) + +#define min(a, b) ({\ + typeof(a) _a = a;\ + typeof(b) _b = b;\ + _a < _b ? _a : _b; }) + +typedef enum { + NORMAL = 1, + MAIN_HEADING, + MAIN_MENU_BOX, + MAIN_MENU_FORE, + MAIN_MENU_BACK, + MAIN_MENU_GREY, + MAIN_MENU_HEADING, + SCROLLWIN_TEXT, + SCROLLWIN_HEADING, + SCROLLWIN_BOX, + DIALOG_TEXT, + DIALOG_MENU_FORE, + DIALOG_MENU_BACK, + DIALOG_BOX, + INPUT_BOX, + INPUT_HEADING, + INPUT_TEXT, + INPUT_FIELD, + FUNCTION_TEXT, + FUNCTION_HIGHLIGHT, + ATTR_MAX +} attributes_t; +extern attributes_t attributes[]; + +typedef enum { + F_HELP = 1, + F_SYMBOL = 2, + F_INSTS = 3, + F_CONF = 4, + F_BACK = 5, + F_SAVE = 6, + F_LOAD = 7, + F_SEARCH = 8, + F_EXIT = 9, +} function_key; + +void set_colors(void); + +/* this changes the windows attributes !!! */ +void print_in_middle(WINDOW *win, + int starty, + int startx, + int width, + const char *string, + chtype color); +int get_line_length(const char *line); +int get_line_no(const char *text); +const char *get_line(const char *text, int line_no); +void fill_window(WINDOW *win, const char *text); +int btn_dialog(WINDOW *main_window, const char *msg, int btn_num, ...); +int dialog_inputbox(WINDOW *main_window, + const char *title, const char *prompt, + const char *init, char **resultp, int *result_len); +void refresh_all_windows(WINDOW *main_window); +void show_scroll_win(WINDOW *main_window, + const char *title, + const char *text); diff --git a/src/net/scripts/kconfig/parser.y b/src/net/scripts/kconfig/parser.y new file mode 100644 index 0000000..190f111 --- /dev/null +++ b/src/net/scripts/kconfig/parser.y @@ -0,0 +1,727 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2002 Roman Zippel <zippel@linux-m68k.org> + */ +%{ + +#include <ctype.h> +#include <stdarg.h> +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <stdbool.h> + +#include "lkc.h" + +#define printd(mask, fmt...) if (cdebug & (mask)) printf(fmt) + +#define PRINTD 0x0001 +#define DEBUG_PARSE 0x0002 + +int cdebug = PRINTD; + +static void yyerror(const char *err); +static void zconfprint(const char *err, ...); +static void zconf_error(const char *err, ...); +static bool zconf_endtoken(const char *tokenname, + const char *expected_tokenname); + +struct symbol *symbol_hash[SYMBOL_HASHSIZE]; + +static struct menu *current_menu, *current_entry; + +%} + +%union +{ + char *string; + struct symbol *symbol; + struct expr *expr; + struct menu *menu; + enum symbol_type type; + enum variable_flavor flavor; +} + +%token <string> T_HELPTEXT +%token <string> T_WORD +%token <string> T_WORD_QUOTE +%token T_ALLNOCONFIG_Y +%token T_BOOL +%token T_CHOICE +%token T_CLOSE_PAREN +%token T_COLON_EQUAL +%token T_COMMENT +%token T_CONFIG +%token T_DEFAULT +%token T_DEFCONFIG_LIST +%token T_DEF_BOOL +%token T_DEF_TRISTATE +%token T_DEPENDS +%token T_ENDCHOICE +%token T_ENDIF +%token T_ENDMENU +%token T_HELP +%token T_HEX +%token T_IF +%token T_IMPLY +%token T_INT +%token T_MAINMENU +%token T_MENU +%token T_MENUCONFIG +%token T_MODULES +%token T_ON +%token T_OPEN_PAREN +%token T_OPTION +%token T_OPTIONAL +%token T_PLUS_EQUAL +%token T_PROMPT +%token T_RANGE +%token T_SELECT +%token T_SOURCE +%token T_STRING +%token T_TRISTATE +%token T_VISIBLE +%token T_EOL +%token <string> T_ASSIGN_VAL + +%left T_OR +%left T_AND +%left T_EQUAL T_UNEQUAL +%left T_LESS T_LESS_EQUAL T_GREATER T_GREATER_EQUAL +%nonassoc T_NOT + +%type <symbol> nonconst_symbol +%type <symbol> symbol +%type <type> type logic_type default +%type <expr> expr +%type <expr> if_expr +%type <string> end +%type <menu> if_entry menu_entry choice_entry +%type <string> word_opt assign_val +%type <flavor> assign_op + +%destructor { + fprintf(stderr, "%s:%d: missing end statement for this entry\n", + $$->file->name, $$->lineno); + if (current_menu == $$) + menu_end_menu(); +} if_entry menu_entry choice_entry + +%% +input: mainmenu_stmt stmt_list | stmt_list; + +/* mainmenu entry */ + +mainmenu_stmt: T_MAINMENU T_WORD_QUOTE T_EOL +{ + menu_add_prompt(P_MENU, $2, NULL); +}; + +stmt_list: + /* empty */ + | stmt_list assignment_stmt + | stmt_list choice_stmt + | stmt_list comment_stmt + | stmt_list config_stmt + | stmt_list if_stmt + | stmt_list menu_stmt + | stmt_list menuconfig_stmt + | stmt_list source_stmt + | stmt_list T_WORD error T_EOL { zconf_error("unknown statement \"%s\"", $2); } + | stmt_list error T_EOL { zconf_error("invalid statement"); } +; + +stmt_list_in_choice: + /* empty */ + | stmt_list_in_choice comment_stmt + | stmt_list_in_choice config_stmt + | stmt_list_in_choice if_stmt_in_choice + | stmt_list_in_choice error T_EOL { zconf_error("invalid statement"); } +; + +/* config/menuconfig entry */ + +config_entry_start: T_CONFIG nonconst_symbol T_EOL +{ + $2->flags |= SYMBOL_OPTIONAL; + menu_add_entry($2); + printd(DEBUG_PARSE, "%s:%d:config %s\n", zconf_curname(), zconf_lineno(), $2->name); +}; + +config_stmt: config_entry_start config_option_list +{ + printd(DEBUG_PARSE, "%s:%d:endconfig\n", zconf_curname(), zconf_lineno()); +}; + +menuconfig_entry_start: T_MENUCONFIG nonconst_symbol T_EOL +{ + $2->flags |= SYMBOL_OPTIONAL; + menu_add_entry($2); + printd(DEBUG_PARSE, "%s:%d:menuconfig %s\n", zconf_curname(), zconf_lineno(), $2->name); +}; + +menuconfig_stmt: menuconfig_entry_start config_option_list +{ + if (current_entry->prompt) + current_entry->prompt->type = P_MENU; + else + zconfprint("warning: menuconfig statement without prompt"); + printd(DEBUG_PARSE, "%s:%d:endconfig\n", zconf_curname(), zconf_lineno()); +}; + +config_option_list: + /* empty */ + | config_option_list config_option + | config_option_list depends + | config_option_list help +; + +config_option: type prompt_stmt_opt T_EOL +{ + menu_set_type($1); + printd(DEBUG_PARSE, "%s:%d:type(%u)\n", + zconf_curname(), zconf_lineno(), + $1); +}; + +config_option: T_PROMPT T_WORD_QUOTE if_expr T_EOL +{ + menu_add_prompt(P_PROMPT, $2, $3); + printd(DEBUG_PARSE, "%s:%d:prompt\n", zconf_curname(), zconf_lineno()); +}; + +config_option: default expr if_expr T_EOL +{ + menu_add_expr(P_DEFAULT, $2, $3); + if ($1 != S_UNKNOWN) + menu_set_type($1); + printd(DEBUG_PARSE, "%s:%d:default(%u)\n", + zconf_curname(), zconf_lineno(), + $1); +}; + +config_option: T_SELECT nonconst_symbol if_expr T_EOL +{ + menu_add_symbol(P_SELECT, $2, $3); + printd(DEBUG_PARSE, "%s:%d:select\n", zconf_curname(), zconf_lineno()); +}; + +config_option: T_IMPLY nonconst_symbol if_expr T_EOL +{ + menu_add_symbol(P_IMPLY, $2, $3); + printd(DEBUG_PARSE, "%s:%d:imply\n", zconf_curname(), zconf_lineno()); +}; + +config_option: T_RANGE symbol symbol if_expr T_EOL +{ + menu_add_expr(P_RANGE, expr_alloc_comp(E_RANGE,$2, $3), $4); + printd(DEBUG_PARSE, "%s:%d:range\n", zconf_curname(), zconf_lineno()); +}; + +config_option: T_OPTION T_MODULES T_EOL +{ + menu_add_option_modules(); +}; + +config_option: T_OPTION T_DEFCONFIG_LIST T_EOL +{ + menu_add_option_defconfig_list(); +}; + +config_option: T_OPTION T_ALLNOCONFIG_Y T_EOL +{ + menu_add_option_allnoconfig_y(); +}; + +/* choice entry */ + +choice: T_CHOICE word_opt T_EOL +{ + struct symbol *sym = sym_lookup($2, SYMBOL_CHOICE); + sym->flags |= SYMBOL_NO_WRITE; + menu_add_entry(sym); + menu_add_expr(P_CHOICE, NULL, NULL); + free($2); + printd(DEBUG_PARSE, "%s:%d:choice\n", zconf_curname(), zconf_lineno()); +}; + +choice_entry: choice choice_option_list +{ + $$ = menu_add_menu(); +}; + +choice_end: end +{ + if (zconf_endtoken($1, "choice")) { + menu_end_menu(); + printd(DEBUG_PARSE, "%s:%d:endchoice\n", zconf_curname(), zconf_lineno()); + } +}; + +choice_stmt: choice_entry stmt_list_in_choice choice_end +; + +choice_option_list: + /* empty */ + | choice_option_list choice_option + | choice_option_list depends + | choice_option_list help +; + +choice_option: T_PROMPT T_WORD_QUOTE if_expr T_EOL +{ + menu_add_prompt(P_PROMPT, $2, $3); + printd(DEBUG_PARSE, "%s:%d:prompt\n", zconf_curname(), zconf_lineno()); +}; + +choice_option: logic_type prompt_stmt_opt T_EOL +{ + menu_set_type($1); + printd(DEBUG_PARSE, "%s:%d:type(%u)\n", + zconf_curname(), zconf_lineno(), $1); +}; + +choice_option: T_OPTIONAL T_EOL +{ + current_entry->sym->flags |= SYMBOL_OPTIONAL; + printd(DEBUG_PARSE, "%s:%d:optional\n", zconf_curname(), zconf_lineno()); +}; + +choice_option: T_DEFAULT nonconst_symbol if_expr T_EOL +{ + menu_add_symbol(P_DEFAULT, $2, $3); + printd(DEBUG_PARSE, "%s:%d:default\n", + zconf_curname(), zconf_lineno()); +}; + +type: + logic_type + | T_INT { $$ = S_INT; } + | T_HEX { $$ = S_HEX; } + | T_STRING { $$ = S_STRING; } + +logic_type: + T_BOOL { $$ = S_BOOLEAN; } + | T_TRISTATE { $$ = S_TRISTATE; } + +default: + T_DEFAULT { $$ = S_UNKNOWN; } + | T_DEF_BOOL { $$ = S_BOOLEAN; } + | T_DEF_TRISTATE { $$ = S_TRISTATE; } + +/* if entry */ + +if_entry: T_IF expr T_EOL +{ + printd(DEBUG_PARSE, "%s:%d:if\n", zconf_curname(), zconf_lineno()); + menu_add_entry(NULL); + menu_add_dep($2); + $$ = menu_add_menu(); +}; + +if_end: end +{ + if (zconf_endtoken($1, "if")) { + menu_end_menu(); + printd(DEBUG_PARSE, "%s:%d:endif\n", zconf_curname(), zconf_lineno()); + } +}; + +if_stmt: if_entry stmt_list if_end +; + +if_stmt_in_choice: if_entry stmt_list_in_choice if_end +; + +/* menu entry */ + +menu: T_MENU T_WORD_QUOTE T_EOL +{ + menu_add_entry(NULL); + menu_add_prompt(P_MENU, $2, NULL); + printd(DEBUG_PARSE, "%s:%d:menu\n", zconf_curname(), zconf_lineno()); +}; + +menu_entry: menu menu_option_list +{ + $$ = menu_add_menu(); +}; + +menu_end: end +{ + if (zconf_endtoken($1, "menu")) { + menu_end_menu(); + printd(DEBUG_PARSE, "%s:%d:endmenu\n", zconf_curname(), zconf_lineno()); + } +}; + +menu_stmt: menu_entry stmt_list menu_end +; + +menu_option_list: + /* empty */ + | menu_option_list visible + | menu_option_list depends +; + +source_stmt: T_SOURCE T_WORD_QUOTE T_EOL +{ + printd(DEBUG_PARSE, "%s:%d:source %s\n", zconf_curname(), zconf_lineno(), $2); + zconf_nextfile($2); + free($2); +}; + +/* comment entry */ + +comment: T_COMMENT T_WORD_QUOTE T_EOL +{ + menu_add_entry(NULL); + menu_add_prompt(P_COMMENT, $2, NULL); + printd(DEBUG_PARSE, "%s:%d:comment\n", zconf_curname(), zconf_lineno()); +}; + +comment_stmt: comment comment_option_list +; + +comment_option_list: + /* empty */ + | comment_option_list depends +; + +/* help option */ + +help_start: T_HELP T_EOL +{ + printd(DEBUG_PARSE, "%s:%d:help\n", zconf_curname(), zconf_lineno()); + zconf_starthelp(); +}; + +help: help_start T_HELPTEXT +{ + if (current_entry->help) { + free(current_entry->help); + zconfprint("warning: '%s' defined with more than one help text -- only the last one will be used", + current_entry->sym->name ?: "<choice>"); + } + + /* Is the help text empty or all whitespace? */ + if ($2[strspn($2, " \f\n\r\t\v")] == '\0') + zconfprint("warning: '%s' defined with blank help text", + current_entry->sym->name ?: "<choice>"); + + current_entry->help = $2; +}; + +/* depends option */ + +depends: T_DEPENDS T_ON expr T_EOL +{ + menu_add_dep($3); + printd(DEBUG_PARSE, "%s:%d:depends on\n", zconf_curname(), zconf_lineno()); +}; + +/* visibility option */ +visible: T_VISIBLE if_expr T_EOL +{ + menu_add_visibility($2); +}; + +/* prompt statement */ + +prompt_stmt_opt: + /* empty */ + | T_WORD_QUOTE if_expr +{ + menu_add_prompt(P_PROMPT, $1, $2); +}; + +end: T_ENDMENU T_EOL { $$ = "menu"; } + | T_ENDCHOICE T_EOL { $$ = "choice"; } + | T_ENDIF T_EOL { $$ = "if"; } +; + +if_expr: /* empty */ { $$ = NULL; } + | T_IF expr { $$ = $2; } +; + +expr: symbol { $$ = expr_alloc_symbol($1); } + | symbol T_LESS symbol { $$ = expr_alloc_comp(E_LTH, $1, $3); } + | symbol T_LESS_EQUAL symbol { $$ = expr_alloc_comp(E_LEQ, $1, $3); } + | symbol T_GREATER symbol { $$ = expr_alloc_comp(E_GTH, $1, $3); } + | symbol T_GREATER_EQUAL symbol { $$ = expr_alloc_comp(E_GEQ, $1, $3); } + | symbol T_EQUAL symbol { $$ = expr_alloc_comp(E_EQUAL, $1, $3); } + | symbol T_UNEQUAL symbol { $$ = expr_alloc_comp(E_UNEQUAL, $1, $3); } + | T_OPEN_PAREN expr T_CLOSE_PAREN { $$ = $2; } + | T_NOT expr { $$ = expr_alloc_one(E_NOT, $2); } + | expr T_OR expr { $$ = expr_alloc_two(E_OR, $1, $3); } + | expr T_AND expr { $$ = expr_alloc_two(E_AND, $1, $3); } +; + +/* For symbol definitions, selects, etc., where quotes are not accepted */ +nonconst_symbol: T_WORD { $$ = sym_lookup($1, 0); free($1); }; + +symbol: nonconst_symbol + | T_WORD_QUOTE { $$ = sym_lookup($1, SYMBOL_CONST); free($1); } +; + +word_opt: /* empty */ { $$ = NULL; } + | T_WORD + +/* assignment statement */ + +assignment_stmt: T_WORD assign_op assign_val T_EOL { variable_add($1, $3, $2); free($1); free($3); } + +assign_op: + T_EQUAL { $$ = VAR_RECURSIVE; } + | T_COLON_EQUAL { $$ = VAR_SIMPLE; } + | T_PLUS_EQUAL { $$ = VAR_APPEND; } +; + +assign_val: + /* empty */ { $$ = xstrdup(""); }; + | T_ASSIGN_VAL +; + +%% + +void conf_parse(const char *name) +{ + struct symbol *sym; + int i; + + zconf_initscan(name); + + _menu_init(); + + if (getenv("ZCONF_DEBUG")) + yydebug = 1; + yyparse(); + + /* Variables are expanded in the parse phase. We can free them here. */ + variable_all_del(); + + if (yynerrs) + exit(1); + if (!modules_sym) + modules_sym = sym_find( "n" ); + + if (!menu_has_prompt(&rootmenu)) { + current_entry = &rootmenu; + menu_add_prompt(P_MENU, "Main menu", NULL); + } + + menu_finalize(&rootmenu); + for_all_symbols(i, sym) { + if (sym_check_deps(sym)) + yynerrs++; + } + if (yynerrs) + exit(1); + sym_set_change_count(1); +} + +static bool zconf_endtoken(const char *tokenname, + const char *expected_tokenname) +{ + if (strcmp(tokenname, expected_tokenname)) { + zconf_error("unexpected '%s' within %s block", + tokenname, expected_tokenname); + yynerrs++; + return false; + } + if (current_menu->file != current_file) { + zconf_error("'%s' in different file than '%s'", + tokenname, expected_tokenname); + fprintf(stderr, "%s:%d: location of the '%s'\n", + current_menu->file->name, current_menu->lineno, + expected_tokenname); + yynerrs++; + return false; + } + return true; +} + +static void zconfprint(const char *err, ...) +{ + va_list ap; + + fprintf(stderr, "%s:%d: ", zconf_curname(), zconf_lineno()); + va_start(ap, err); + vfprintf(stderr, err, ap); + va_end(ap); + fprintf(stderr, "\n"); +} + +static void zconf_error(const char *err, ...) +{ + va_list ap; + + yynerrs++; + fprintf(stderr, "%s:%d: ", zconf_curname(), zconf_lineno()); + va_start(ap, err); + vfprintf(stderr, err, ap); + va_end(ap); + fprintf(stderr, "\n"); +} + +static void yyerror(const char *err) +{ + fprintf(stderr, "%s:%d: %s\n", zconf_curname(), zconf_lineno() + 1, err); +} + +static void print_quoted_string(FILE *out, const char *str) +{ + const char *p; + int len; + + putc('"', out); + while ((p = strchr(str, '"'))) { + len = p - str; + if (len) + fprintf(out, "%.*s", len, str); + fputs("\\\"", out); + str = p + 1; + } + fputs(str, out); + putc('"', out); +} + +static void print_symbol(FILE *out, struct menu *menu) +{ + struct symbol *sym = menu->sym; + struct property *prop; + + if (sym_is_choice(sym)) + fprintf(out, "\nchoice\n"); + else + fprintf(out, "\nconfig %s\n", sym->name); + switch (sym->type) { + case S_BOOLEAN: + fputs(" bool\n", out); + break; + case S_TRISTATE: + fputs(" tristate\n", out); + break; + case S_STRING: + fputs(" string\n", out); + break; + case S_INT: + fputs(" integer\n", out); + break; + case S_HEX: + fputs(" hex\n", out); + break; + default: + fputs(" ???\n", out); + break; + } + for (prop = sym->prop; prop; prop = prop->next) { + if (prop->menu != menu) + continue; + switch (prop->type) { + case P_PROMPT: + fputs(" prompt ", out); + print_quoted_string(out, prop->text); + if (!expr_is_yes(prop->visible.expr)) { + fputs(" if ", out); + expr_fprint(prop->visible.expr, out); + } + fputc('\n', out); + break; + case P_DEFAULT: + fputs( " default ", out); + expr_fprint(prop->expr, out); + if (!expr_is_yes(prop->visible.expr)) { + fputs(" if ", out); + expr_fprint(prop->visible.expr, out); + } + fputc('\n', out); + break; + case P_CHOICE: + fputs(" #choice value\n", out); + break; + case P_SELECT: + fputs( " select ", out); + expr_fprint(prop->expr, out); + fputc('\n', out); + break; + case P_IMPLY: + fputs( " imply ", out); + expr_fprint(prop->expr, out); + fputc('\n', out); + break; + case P_RANGE: + fputs( " range ", out); + expr_fprint(prop->expr, out); + fputc('\n', out); + break; + case P_MENU: + fputs( " menu ", out); + print_quoted_string(out, prop->text); + fputc('\n', out); + break; + case P_SYMBOL: + fputs( " symbol ", out); + fprintf(out, "%s\n", prop->menu->sym->name); + break; + default: + fprintf(out, " unknown prop %d!\n", prop->type); + break; + } + } + if (menu->help) { + int len = strlen(menu->help); + while (menu->help[--len] == '\n') + menu->help[len] = 0; + fprintf(out, " help\n%s\n", menu->help); + } +} + +void zconfdump(FILE *out) +{ + struct property *prop; + struct symbol *sym; + struct menu *menu; + + menu = rootmenu.list; + while (menu) { + if ((sym = menu->sym)) + print_symbol(out, menu); + else if ((prop = menu->prompt)) { + switch (prop->type) { + case P_COMMENT: + fputs("\ncomment ", out); + print_quoted_string(out, prop->text); + fputs("\n", out); + break; + case P_MENU: + fputs("\nmenu ", out); + print_quoted_string(out, prop->text); + fputs("\n", out); + break; + default: + ; + } + if (!expr_is_yes(prop->visible.expr)) { + fputs(" depends ", out); + expr_fprint(prop->visible.expr, out); + fputc('\n', out); + } + } + + if (menu->list) + menu = menu->list; + else if (menu->next) + menu = menu->next; + else while ((menu = menu->parent)) { + if (menu->prompt && menu->prompt->type == P_MENU) + fputs("\nendmenu\n", out); + if (menu->next) { + menu = menu->next; + break; + } + } + } +} + +#include "menu.c" diff --git a/src/net/scripts/kconfig/preprocess.c b/src/net/scripts/kconfig/preprocess.c new file mode 100644 index 0000000..748da57 --- /dev/null +++ b/src/net/scripts/kconfig/preprocess.c @@ -0,0 +1,574 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2018 Masahiro Yamada <yamada.masahiro@socionext.com> + +#include <ctype.h> +#include <stdarg.h> +#include <stdbool.h> +#include <stdio.h> +#include <stdlib.h> +#include <string.h> + +#include "list.h" +#include "lkc.h" + +#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) + +static char *expand_string_with_args(const char *in, int argc, char *argv[]); +static char *expand_string(const char *in); + +static void __attribute__((noreturn)) pperror(const char *format, ...) +{ + va_list ap; + + fprintf(stderr, "%s:%d: ", current_file->name, yylineno); + va_start(ap, format); + vfprintf(stderr, format, ap); + va_end(ap); + fprintf(stderr, "\n"); + + exit(1); +} + +/* + * Environment variables + */ +static LIST_HEAD(env_list); + +struct env { + char *name; + char *value; + struct list_head node; +}; + +static void env_add(const char *name, const char *value) +{ + struct env *e; + + e = xmalloc(sizeof(*e)); + e->name = xstrdup(name); + e->value = xstrdup(value); + + list_add_tail(&e->node, &env_list); +} + +static void env_del(struct env *e) +{ + list_del(&e->node); + free(e->name); + free(e->value); + free(e); +} + +/* The returned pointer must be freed when done */ +static char *env_expand(const char *name) +{ + struct env *e; + const char *value; + + if (!*name) + return NULL; + + list_for_each_entry(e, &env_list, node) { + if (!strcmp(name, e->name)) + return xstrdup(e->value); + } + + value = getenv(name); + if (!value) + return NULL; + + /* + * We need to remember all referenced environment variables. + * They will be written out to include/config/auto.conf.cmd + */ + env_add(name, value); + + return xstrdup(value); +} + +void env_write_dep(FILE *f, const char *autoconfig_name) +{ + struct env *e, *tmp; + + list_for_each_entry_safe(e, tmp, &env_list, node) { + fprintf(f, "ifneq \"$(%s)\" \"%s\"\n", e->name, e->value); + fprintf(f, "%s: FORCE\n", autoconfig_name); + fprintf(f, "endif\n"); + env_del(e); + } +} + +/* + * Built-in functions + */ +struct function { + const char *name; + unsigned int min_args; + unsigned int max_args; + char *(*func)(int argc, char *argv[]); +}; + +static char *do_error_if(int argc, char *argv[]) +{ + if (!strcmp(argv[0], "y")) + pperror("%s", argv[1]); + + return xstrdup(""); +} + +static char *do_filename(int argc, char *argv[]) +{ + return xstrdup(current_file->name); +} + +static char *do_info(int argc, char *argv[]) +{ + printf("%s\n", argv[0]); + + return xstrdup(""); +} + +static char *do_lineno(int argc, char *argv[]) +{ + char buf[16]; + + sprintf(buf, "%d", yylineno); + + return xstrdup(buf); +} + +static char *do_shell(int argc, char *argv[]) +{ + FILE *p; + char buf[4096]; + char *cmd; + size_t nread; + int i; + + cmd = argv[0]; + + p = popen(cmd, "r"); + if (!p) { + perror(cmd); + exit(1); + } + + nread = fread(buf, 1, sizeof(buf), p); + if (nread == sizeof(buf)) + nread--; + + /* remove trailing new lines */ + while (nread > 0 && buf[nread - 1] == '\n') + nread--; + + buf[nread] = 0; + + /* replace a new line with a space */ + for (i = 0; i < nread; i++) { + if (buf[i] == '\n') + buf[i] = ' '; + } + + if (pclose(p) == -1) { + perror(cmd); + exit(1); + } + + return xstrdup(buf); +} + +static char *do_warning_if(int argc, char *argv[]) +{ + if (!strcmp(argv[0], "y")) + fprintf(stderr, "%s:%d: %s\n", + current_file->name, yylineno, argv[1]); + + return xstrdup(""); +} + +static const struct function function_table[] = { + /* Name MIN MAX Function */ + { "error-if", 2, 2, do_error_if }, + { "filename", 0, 0, do_filename }, + { "info", 1, 1, do_info }, + { "lineno", 0, 0, do_lineno }, + { "shell", 1, 1, do_shell }, + { "warning-if", 2, 2, do_warning_if }, +}; + +#define FUNCTION_MAX_ARGS 16 + +static char *function_expand(const char *name, int argc, char *argv[]) +{ + const struct function *f; + int i; + + for (i = 0; i < ARRAY_SIZE(function_table); i++) { + f = &function_table[i]; + if (strcmp(f->name, name)) + continue; + + if (argc < f->min_args) + pperror("too few function arguments passed to '%s'", + name); + + if (argc > f->max_args) + pperror("too many function arguments passed to '%s'", + name); + + return f->func(argc, argv); + } + + return NULL; +} + +/* + * Variables (and user-defined functions) + */ +static LIST_HEAD(variable_list); + +struct variable { + char *name; + char *value; + enum variable_flavor flavor; + int exp_count; + struct list_head node; +}; + +static struct variable *variable_lookup(const char *name) +{ + struct variable *v; + + list_for_each_entry(v, &variable_list, node) { + if (!strcmp(name, v->name)) + return v; + } + + return NULL; +} + +static char *variable_expand(const char *name, int argc, char *argv[]) +{ + struct variable *v; + char *res; + + v = variable_lookup(name); + if (!v) + return NULL; + + if (argc == 0 && v->exp_count) + pperror("Recursive variable '%s' references itself (eventually)", + name); + + if (v->exp_count > 1000) + pperror("Too deep recursive expansion"); + + v->exp_count++; + + if (v->flavor == VAR_RECURSIVE) + res = expand_string_with_args(v->value, argc, argv); + else + res = xstrdup(v->value); + + v->exp_count--; + + return res; +} + +void variable_add(const char *name, const char *value, + enum variable_flavor flavor) +{ + struct variable *v; + char *new_value; + bool append = false; + + v = variable_lookup(name); + if (v) { + /* For defined variables, += inherits the existing flavor */ + if (flavor == VAR_APPEND) { + flavor = v->flavor; + append = true; + } else { + free(v->value); + } + } else { + /* For undefined variables, += assumes the recursive flavor */ + if (flavor == VAR_APPEND) + flavor = VAR_RECURSIVE; + + v = xmalloc(sizeof(*v)); + v->name = xstrdup(name); + v->exp_count = 0; + list_add_tail(&v->node, &variable_list); + } + + v->flavor = flavor; + + if (flavor == VAR_SIMPLE) + new_value = expand_string(value); + else + new_value = xstrdup(value); + + if (append) { + v->value = xrealloc(v->value, + strlen(v->value) + strlen(new_value) + 2); + strcat(v->value, " "); + strcat(v->value, new_value); + free(new_value); + } else { + v->value = new_value; + } +} + +static void variable_del(struct variable *v) +{ + list_del(&v->node); + free(v->name); + free(v->value); + free(v); +} + +void variable_all_del(void) +{ + struct variable *v, *tmp; + + list_for_each_entry_safe(v, tmp, &variable_list, node) + variable_del(v); +} + +/* + * Evaluate a clause with arguments. argc/argv are arguments from the upper + * function call. + * + * Returned string must be freed when done + */ +static char *eval_clause(const char *str, size_t len, int argc, char *argv[]) +{ + char *tmp, *name, *res, *endptr, *prev, *p; + int new_argc = 0; + char *new_argv[FUNCTION_MAX_ARGS]; + int nest = 0; + int i; + unsigned long n; + + tmp = xstrndup(str, len); + + /* + * If variable name is '1', '2', etc. It is generally an argument + * from a user-function call (i.e. local-scope variable). If not + * available, then look-up global-scope variables. + */ + n = strtoul(tmp, &endptr, 10); + if (!*endptr && n > 0 && n <= argc) { + res = xstrdup(argv[n - 1]); + goto free_tmp; + } + + prev = p = tmp; + + /* + * Split into tokens + * The function name and arguments are separated by a comma. + * For example, if the function call is like this: + * $(foo,$(x),$(y)) + * + * The input string for this helper should be: + * foo,$(x),$(y) + * + * and split into: + * new_argv[0] = 'foo' + * new_argv[1] = '$(x)' + * new_argv[2] = '$(y)' + */ + while (*p) { + if (nest == 0 && *p == ',') { + *p = 0; + if (new_argc >= FUNCTION_MAX_ARGS) + pperror("too many function arguments"); + new_argv[new_argc++] = prev; + prev = p + 1; + } else if (*p == '(') { + nest++; + } else if (*p == ')') { + nest--; + } + + p++; + } + new_argv[new_argc++] = prev; + + /* + * Shift arguments + * new_argv[0] represents a function name or a variable name. Put it + * into 'name', then shift the rest of the arguments. This simplifies + * 'const' handling. + */ + name = expand_string_with_args(new_argv[0], argc, argv); + new_argc--; + for (i = 0; i < new_argc; i++) + new_argv[i] = expand_string_with_args(new_argv[i + 1], + argc, argv); + + /* Search for variables */ + res = variable_expand(name, new_argc, new_argv); + if (res) + goto free; + + /* Look for built-in functions */ + res = function_expand(name, new_argc, new_argv); + if (res) + goto free; + + /* Last, try environment variable */ + if (new_argc == 0) { + res = env_expand(name); + if (res) + goto free; + } + + res = xstrdup(""); +free: + for (i = 0; i < new_argc; i++) + free(new_argv[i]); + free(name); +free_tmp: + free(tmp); + + return res; +} + +/* + * Expand a string that follows '$' + * + * For example, if the input string is + * ($(FOO)$($(BAR)))$(BAZ) + * this helper evaluates + * $($(FOO)$($(BAR))) + * and returns a new string containing the expansion (note that the string is + * recursively expanded), also advancing 'str' to point to the next character + * after the corresponding closing parenthesis, in this case, *str will be + * $(BAR) + */ +static char *expand_dollar_with_args(const char **str, int argc, char *argv[]) +{ + const char *p = *str; + const char *q; + int nest = 0; + + /* + * In Kconfig, variable/function references always start with "$(". + * Neither single-letter variables as in $A nor curly braces as in ${CC} + * are supported. '$' not followed by '(' loses its special meaning. + */ + if (*p != '(') { + *str = p; + return xstrdup("$"); + } + + p++; + q = p; + while (*q) { + if (*q == '(') { + nest++; + } else if (*q == ')') { + if (nest-- == 0) + break; + } + q++; + } + + if (!*q) + pperror("unterminated reference to '%s': missing ')'", p); + + /* Advance 'str' to after the expanded initial portion of the string */ + *str = q + 1; + + return eval_clause(p, q - p, argc, argv); +} + +char *expand_dollar(const char **str) +{ + return expand_dollar_with_args(str, 0, NULL); +} + +static char *__expand_string(const char **str, bool (*is_end)(char c), + int argc, char *argv[]) +{ + const char *in, *p; + char *expansion, *out; + size_t in_len, out_len; + + out = xmalloc(1); + *out = 0; + out_len = 1; + + p = in = *str; + + while (1) { + if (*p == '$') { + in_len = p - in; + p++; + expansion = expand_dollar_with_args(&p, argc, argv); + out_len += in_len + strlen(expansion); + out = xrealloc(out, out_len); + strncat(out, in, in_len); + strcat(out, expansion); + free(expansion); + in = p; + continue; + } + + if (is_end(*p)) + break; + + p++; + } + + in_len = p - in; + out_len += in_len; + out = xrealloc(out, out_len); + strncat(out, in, in_len); + + /* Advance 'str' to the end character */ + *str = p; + + return out; +} + +static bool is_end_of_str(char c) +{ + return !c; +} + +/* + * Expand variables and functions in the given string. Undefined variables + * expand to an empty string. + * The returned string must be freed when done. + */ +static char *expand_string_with_args(const char *in, int argc, char *argv[]) +{ + return __expand_string(&in, is_end_of_str, argc, argv); +} + +static char *expand_string(const char *in) +{ + return expand_string_with_args(in, 0, NULL); +} + +static bool is_end_of_token(char c) +{ + return !(isalnum(c) || c == '_' || c == '-'); +} + +/* + * Expand variables in a token. The parsing stops when a token separater + * (in most cases, it is a whitespace) is encountered. 'str' is updated to + * point to the next character. + * + * The returned string must be freed when done. + */ +char *expand_one_token(const char **str) +{ + return __expand_string(str, is_end_of_token, 0, NULL); +} diff --git a/src/net/scripts/kconfig/qconf-cfg.sh b/src/net/scripts/kconfig/qconf-cfg.sh new file mode 100755 index 0000000..02ccc0a --- /dev/null +++ b/src/net/scripts/kconfig/qconf-cfg.sh @@ -0,0 +1,32 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0 + +PKG="Qt5Core Qt5Gui Qt5Widgets" +PKG2="QtCore QtGui" + +if [ -z "$(command -v pkg-config)" ]; then + echo >&2 "*" + echo >&2 "* 'make xconfig' requires 'pkg-config'. Please install it." + echo >&2 "*" + exit 1 +fi + +if pkg-config --exists $PKG; then + echo cflags=\"-std=c++11 -fPIC $(pkg-config --cflags Qt5Core Qt5Gui Qt5Widgets)\" + echo libs=\"$(pkg-config --libs $PKG)\" + echo moc=\"$(pkg-config --variable=host_bins Qt5Core)/moc\" + exit 0 +fi + +if pkg-config --exists $PKG2; then + echo cflags=\"$(pkg-config --cflags $PKG2)\" + echo libs=\"$(pkg-config --libs $PKG2)\" + echo moc=\"$(pkg-config --variable=moc_location QtCore)\" + exit 0 +fi + +echo >&2 "*" +echo >&2 "* Could not find Qt via pkg-config." +echo >&2 "* Please install either Qt 4.8 or 5.x. and make sure it's in PKG_CONFIG_PATH" +echo >&2 "*" +exit 1 diff --git a/src/net/scripts/kconfig/qconf.cc b/src/net/scripts/kconfig/qconf.cc new file mode 100644 index 0000000..f7eb093 --- /dev/null +++ b/src/net/scripts/kconfig/qconf.cc @@ -0,0 +1,1892 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2002 Roman Zippel <zippel@linux-m68k.org> + * Copyright (C) 2015 Boris Barbulovski <bbarbulovski@gmail.com> + */ + +#include <QAction> +#include <QApplication> +#include <QCloseEvent> +#include <QDebug> +#include <QDesktopWidget> +#include <QFileDialog> +#include <QLabel> +#include <QLayout> +#include <QList> +#include <QMenu> +#include <QMenuBar> +#include <QMessageBox> +#include <QToolBar> + +#include <stdlib.h> + +#include "lkc.h" +#include "qconf.h" + +#include "images.h" + + +static QApplication *configApp; +static ConfigSettings *configSettings; + +QAction *ConfigMainWindow::saveAction; + +ConfigSettings::ConfigSettings() + : QSettings("kernel.org", "qconf") +{ +} + +/** + * Reads a list of integer values from the application settings. + */ +QList<int> ConfigSettings::readSizes(const QString& key, bool *ok) +{ + QList<int> result; + + if (contains(key)) + { + QStringList entryList = value(key).toStringList(); + QStringList::Iterator it; + + for (it = entryList.begin(); it != entryList.end(); ++it) + result.push_back((*it).toInt()); + + *ok = true; + } + else + *ok = false; + + return result; +} + +/** + * Writes a list of integer values to the application settings. + */ +bool ConfigSettings::writeSizes(const QString& key, const QList<int>& value) +{ + QStringList stringList; + QList<int>::ConstIterator it; + + for (it = value.begin(); it != value.end(); ++it) + stringList.push_back(QString::number(*it)); + setValue(key, stringList); + + return true; +} + +QIcon ConfigItem::symbolYesIcon; +QIcon ConfigItem::symbolModIcon; +QIcon ConfigItem::symbolNoIcon; +QIcon ConfigItem::choiceYesIcon; +QIcon ConfigItem::choiceNoIcon; +QIcon ConfigItem::menuIcon; +QIcon ConfigItem::menubackIcon; + +/* + * update the displayed of a menu entry + */ +void ConfigItem::updateMenu(void) +{ + ConfigList* list; + struct symbol* sym; + struct property *prop; + QString prompt; + int type; + tristate expr; + + list = listView(); + if (goParent) { + setIcon(promptColIdx, menubackIcon); + prompt = ".."; + goto set_prompt; + } + + sym = menu->sym; + prop = menu->prompt; + prompt = menu_get_prompt(menu); + + if (prop) switch (prop->type) { + case P_MENU: + if (list->mode == singleMode || list->mode == symbolMode) { + /* a menuconfig entry is displayed differently + * depending whether it's at the view root or a child. + */ + if (sym && list->rootEntry == menu) + break; + setIcon(promptColIdx, menuIcon); + } else { + if (sym) + break; + setIcon(promptColIdx, QIcon()); + } + goto set_prompt; + case P_COMMENT: + setIcon(promptColIdx, QIcon()); + goto set_prompt; + default: + ; + } + if (!sym) + goto set_prompt; + + setText(nameColIdx, sym->name); + + type = sym_get_type(sym); + switch (type) { + case S_BOOLEAN: + case S_TRISTATE: + char ch; + + if (!sym_is_changeable(sym) && list->optMode == normalOpt) { + setIcon(promptColIdx, QIcon()); + break; + } + expr = sym_get_tristate_value(sym); + switch (expr) { + case yes: + if (sym_is_choice_value(sym) && type == S_BOOLEAN) + setIcon(promptColIdx, choiceYesIcon); + else + setIcon(promptColIdx, symbolYesIcon); + ch = 'Y'; + break; + case mod: + setIcon(promptColIdx, symbolModIcon); + ch = 'M'; + break; + default: + if (sym_is_choice_value(sym) && type == S_BOOLEAN) + setIcon(promptColIdx, choiceNoIcon); + else + setIcon(promptColIdx, symbolNoIcon); + ch = 'N'; + break; + } + + setText(dataColIdx, QChar(ch)); + break; + case S_INT: + case S_HEX: + case S_STRING: + setText(dataColIdx, sym_get_string_value(sym)); + break; + } + if (!sym_has_value(sym) && visible) + prompt += " (NEW)"; +set_prompt: + setText(promptColIdx, prompt); +} + +void ConfigItem::testUpdateMenu(bool v) +{ + ConfigItem* i; + + visible = v; + if (!menu) + return; + + sym_calc_value(menu->sym); + if (menu->flags & MENU_CHANGED) { + /* the menu entry changed, so update all list items */ + menu->flags &= ~MENU_CHANGED; + for (i = (ConfigItem*)menu->data; i; i = i->nextItem) + i->updateMenu(); + } else if (listView()->updateAll) + updateMenu(); +} + + +/* + * construct a menu entry + */ +void ConfigItem::init(void) +{ + if (menu) { + ConfigList* list = listView(); + nextItem = (ConfigItem*)menu->data; + menu->data = this; + + if (list->mode != fullMode) + setExpanded(true); + sym_calc_value(menu->sym); + + if (menu->sym) { + enum symbol_type type = menu->sym->type; + + // Allow to edit "int", "hex", and "string" in-place in + // the data column. Unfortunately, you cannot specify + // the flags per column. Set ItemIsEditable for all + // columns here, and check the column in createEditor(). + if (type == S_INT || type == S_HEX || type == S_STRING) + setFlags(flags() | Qt::ItemIsEditable); + } + } + updateMenu(); +} + +/* + * destruct a menu entry + */ +ConfigItem::~ConfigItem(void) +{ + if (menu) { + ConfigItem** ip = (ConfigItem**)&menu->data; + for (; *ip; ip = &(*ip)->nextItem) { + if (*ip == this) { + *ip = nextItem; + break; + } + } + } +} + +QWidget *ConfigItemDelegate::createEditor(QWidget *parent, + const QStyleOptionViewItem &option, + const QModelIndex &index) const +{ + ConfigItem *item; + + // Only the data column is editable + if (index.column() != dataColIdx) + return nullptr; + + // You cannot edit invisible menus + item = static_cast<ConfigItem *>(index.internalPointer()); + if (!item || !item->menu || !menu_is_visible(item->menu)) + return nullptr; + + return QStyledItemDelegate::createEditor(parent, option, index); +} + +void ConfigItemDelegate::setModelData(QWidget *editor, + QAbstractItemModel *model, + const QModelIndex &index) const +{ + QLineEdit *lineEdit; + ConfigItem *item; + struct symbol *sym; + bool success; + + lineEdit = qobject_cast<QLineEdit *>(editor); + // If this is not a QLineEdit, use the parent's default. + // (does this happen?) + if (!lineEdit) + goto parent; + + item = static_cast<ConfigItem *>(index.internalPointer()); + if (!item || !item->menu) + goto parent; + + sym = item->menu->sym; + if (!sym) + goto parent; + + success = sym_set_string_value(sym, lineEdit->text().toUtf8().data()); + if (success) { + ConfigList::updateListForAll(); + } else { + QMessageBox::information(editor, "qconf", + "Cannot set the data (maybe due to out of range).\n" + "Setting the old value."); + lineEdit->setText(sym_get_string_value(sym)); + } + +parent: + QStyledItemDelegate::setModelData(editor, model, index); +} + +ConfigList::ConfigList(QWidget *parent, const char *name) + : QTreeWidget(parent), + updateAll(false), + showName(false), mode(singleMode), optMode(normalOpt), + rootEntry(0), headerPopup(0) +{ + setObjectName(name); + setSortingEnabled(false); + setRootIsDecorated(true); + + setVerticalScrollMode(ScrollPerPixel); + setHorizontalScrollMode(ScrollPerPixel); + + setHeaderLabels(QStringList() << "Option" << "Name" << "Value"); + + connect(this, SIGNAL(itemSelectionChanged(void)), + SLOT(updateSelection(void))); + + if (name) { + configSettings->beginGroup(name); + showName = configSettings->value("/showName", false).toBool(); + optMode = (enum optionMode)configSettings->value("/optionMode", 0).toInt(); + configSettings->endGroup(); + connect(configApp, SIGNAL(aboutToQuit()), SLOT(saveSettings())); + } + + showColumn(promptColIdx); + + setItemDelegate(new ConfigItemDelegate(this)); + + allLists.append(this); + + reinit(); +} + +ConfigList::~ConfigList() +{ + allLists.removeOne(this); +} + +bool ConfigList::menuSkip(struct menu *menu) +{ + if (optMode == normalOpt && menu_is_visible(menu)) + return false; + if (optMode == promptOpt && menu_has_prompt(menu)) + return false; + if (optMode == allOpt) + return false; + return true; +} + +void ConfigList::reinit(void) +{ + hideColumn(nameColIdx); + + if (showName) + showColumn(nameColIdx); + + updateListAll(); +} + +void ConfigList::setOptionMode(QAction *action) +{ + if (action == showNormalAction) + optMode = normalOpt; + else if (action == showAllAction) + optMode = allOpt; + else + optMode = promptOpt; + + updateListAll(); +} + +void ConfigList::saveSettings(void) +{ + if (!objectName().isEmpty()) { + configSettings->beginGroup(objectName()); + configSettings->setValue("/showName", showName); + configSettings->setValue("/optionMode", (int)optMode); + configSettings->endGroup(); + } +} + +ConfigItem* ConfigList::findConfigItem(struct menu *menu) +{ + ConfigItem* item = (ConfigItem*)menu->data; + + for (; item; item = item->nextItem) { + if (this == item->listView()) + break; + } + + return item; +} + +void ConfigList::updateSelection(void) +{ + struct menu *menu; + enum prop_type type; + + if (selectedItems().count() == 0) + return; + + ConfigItem* item = (ConfigItem*)selectedItems().first(); + if (!item) + return; + + menu = item->menu; + emit menuChanged(menu); + if (!menu) + return; + type = menu->prompt ? menu->prompt->type : P_UNKNOWN; + if (mode == menuMode && type == P_MENU) + emit menuSelected(menu); +} + +void ConfigList::updateList() +{ + ConfigItem* last = 0; + ConfigItem *item; + + if (!rootEntry) { + if (mode != listMode) + goto update; + QTreeWidgetItemIterator it(this); + + while (*it) { + item = (ConfigItem*)(*it); + if (!item->menu) + continue; + item->testUpdateMenu(menu_is_visible(item->menu)); + + ++it; + } + return; + } + + if (rootEntry != &rootmenu && (mode == singleMode || + (mode == symbolMode && rootEntry->parent != &rootmenu))) { + item = (ConfigItem *)topLevelItem(0); + if (!item) + item = new ConfigItem(this, 0, true); + last = item; + } + if ((mode == singleMode || (mode == symbolMode && !(rootEntry->flags & MENU_ROOT))) && + rootEntry->sym && rootEntry->prompt) { + item = last ? last->nextSibling() : nullptr; + if (!item) + item = new ConfigItem(this, last, rootEntry, true); + else + item->testUpdateMenu(true); + + updateMenuList(item, rootEntry); + update(); + resizeColumnToContents(0); + return; + } +update: + updateMenuList(rootEntry); + update(); + resizeColumnToContents(0); +} + +void ConfigList::updateListForAll() +{ + QListIterator<ConfigList *> it(allLists); + + while (it.hasNext()) { + ConfigList *list = it.next(); + + list->updateList(); + } +} + +void ConfigList::updateListAllForAll() +{ + QListIterator<ConfigList *> it(allLists); + + while (it.hasNext()) { + ConfigList *list = it.next(); + + list->updateList(); + } +} + +void ConfigList::setValue(ConfigItem* item, tristate val) +{ + struct symbol* sym; + int type; + tristate oldval; + + sym = item->menu ? item->menu->sym : 0; + if (!sym) + return; + + type = sym_get_type(sym); + switch (type) { + case S_BOOLEAN: + case S_TRISTATE: + oldval = sym_get_tristate_value(sym); + + if (!sym_set_tristate_value(sym, val)) + return; + if (oldval == no && item->menu->list) + item->setExpanded(true); + ConfigList::updateListForAll(); + break; + } +} + +void ConfigList::changeValue(ConfigItem* item) +{ + struct symbol* sym; + struct menu* menu; + int type, oldexpr, newexpr; + + menu = item->menu; + if (!menu) + return; + sym = menu->sym; + if (!sym) { + if (item->menu->list) + item->setExpanded(!item->isExpanded()); + return; + } + + type = sym_get_type(sym); + switch (type) { + case S_BOOLEAN: + case S_TRISTATE: + oldexpr = sym_get_tristate_value(sym); + newexpr = sym_toggle_tristate_value(sym); + if (item->menu->list) { + if (oldexpr == newexpr) + item->setExpanded(!item->isExpanded()); + else if (oldexpr == no) + item->setExpanded(true); + } + if (oldexpr != newexpr) + ConfigList::updateListForAll(); + break; + default: + break; + } +} + +void ConfigList::setRootMenu(struct menu *menu) +{ + enum prop_type type; + + if (rootEntry == menu) + return; + type = menu && menu->prompt ? menu->prompt->type : P_UNKNOWN; + if (type != P_MENU) + return; + updateMenuList(0); + rootEntry = menu; + updateListAll(); + if (currentItem()) { + setSelected(currentItem(), hasFocus()); + scrollToItem(currentItem()); + } +} + +void ConfigList::setParentMenu(void) +{ + ConfigItem* item; + struct menu *oldroot; + + oldroot = rootEntry; + if (rootEntry == &rootmenu) + return; + setRootMenu(menu_get_parent_menu(rootEntry->parent)); + + QTreeWidgetItemIterator it(this); + while (*it) { + item = (ConfigItem *)(*it); + if (item->menu == oldroot) { + setCurrentItem(item); + scrollToItem(item); + break; + } + + ++it; + } +} + +/* + * update all the children of a menu entry + * removes/adds the entries from the parent widget as necessary + * + * parent: either the menu list widget or a menu entry widget + * menu: entry to be updated + */ +void ConfigList::updateMenuList(ConfigItem *parent, struct menu* menu) +{ + struct menu* child; + ConfigItem* item; + ConfigItem* last; + bool visible; + enum prop_type type; + + if (!menu) { + while (parent->childCount() > 0) + { + delete parent->takeChild(0); + } + + return; + } + + last = parent->firstChild(); + if (last && !last->goParent) + last = 0; + for (child = menu->list; child; child = child->next) { + item = last ? last->nextSibling() : parent->firstChild(); + type = child->prompt ? child->prompt->type : P_UNKNOWN; + + switch (mode) { + case menuMode: + if (!(child->flags & MENU_ROOT)) + goto hide; + break; + case symbolMode: + if (child->flags & MENU_ROOT) + goto hide; + break; + default: + break; + } + + visible = menu_is_visible(child); + if (!menuSkip(child)) { + if (!child->sym && !child->list && !child->prompt) + continue; + if (!item || item->menu != child) + item = new ConfigItem(parent, last, child, visible); + else + item->testUpdateMenu(visible); + + if (mode == fullMode || mode == menuMode || type != P_MENU) + updateMenuList(item, child); + else + updateMenuList(item, 0); + last = item; + continue; + } +hide: + if (item && item->menu == child) { + last = parent->firstChild(); + if (last == item) + last = 0; + else while (last->nextSibling() != item) + last = last->nextSibling(); + delete item; + } + } +} + +void ConfigList::updateMenuList(struct menu *menu) +{ + struct menu* child; + ConfigItem* item; + ConfigItem* last; + bool visible; + enum prop_type type; + + if (!menu) { + while (topLevelItemCount() > 0) + { + delete takeTopLevelItem(0); + } + + return; + } + + last = (ConfigItem *)topLevelItem(0); + if (last && !last->goParent) + last = 0; + for (child = menu->list; child; child = child->next) { + item = last ? last->nextSibling() : (ConfigItem *)topLevelItem(0); + type = child->prompt ? child->prompt->type : P_UNKNOWN; + + switch (mode) { + case menuMode: + if (!(child->flags & MENU_ROOT)) + goto hide; + break; + case symbolMode: + if (child->flags & MENU_ROOT) + goto hide; + break; + default: + break; + } + + visible = menu_is_visible(child); + if (!menuSkip(child)) { + if (!child->sym && !child->list && !child->prompt) + continue; + if (!item || item->menu != child) + item = new ConfigItem(this, last, child, visible); + else + item->testUpdateMenu(visible); + + if (mode == fullMode || mode == menuMode || type != P_MENU) + updateMenuList(item, child); + else + updateMenuList(item, 0); + last = item; + continue; + } +hide: + if (item && item->menu == child) { + last = (ConfigItem *)topLevelItem(0); + if (last == item) + last = 0; + else while (last->nextSibling() != item) + last = last->nextSibling(); + delete item; + } + } +} + +void ConfigList::keyPressEvent(QKeyEvent* ev) +{ + QTreeWidgetItem* i = currentItem(); + ConfigItem* item; + struct menu *menu; + enum prop_type type; + + if (ev->key() == Qt::Key_Escape && mode != fullMode && mode != listMode) { + emit parentSelected(); + ev->accept(); + return; + } + + if (!i) { + Parent::keyPressEvent(ev); + return; + } + item = (ConfigItem*)i; + + switch (ev->key()) { + case Qt::Key_Return: + case Qt::Key_Enter: + if (item->goParent) { + emit parentSelected(); + break; + } + menu = item->menu; + if (!menu) + break; + type = menu->prompt ? menu->prompt->type : P_UNKNOWN; + if (type == P_MENU && rootEntry != menu && + mode != fullMode && mode != menuMode) { + if (mode == menuMode) + emit menuSelected(menu); + else + emit itemSelected(menu); + break; + } + case Qt::Key_Space: + changeValue(item); + break; + case Qt::Key_N: + setValue(item, no); + break; + case Qt::Key_M: + setValue(item, mod); + break; + case Qt::Key_Y: + setValue(item, yes); + break; + default: + Parent::keyPressEvent(ev); + return; + } + ev->accept(); +} + +void ConfigList::mousePressEvent(QMouseEvent* e) +{ + //QPoint p(contentsToViewport(e->pos())); + //printf("contentsMousePressEvent: %d,%d\n", p.x(), p.y()); + Parent::mousePressEvent(e); +} + +void ConfigList::mouseReleaseEvent(QMouseEvent* e) +{ + QPoint p = e->pos(); + ConfigItem* item = (ConfigItem*)itemAt(p); + struct menu *menu; + enum prop_type ptype; + QIcon icon; + int idx, x; + + if (!item) + goto skip; + + menu = item->menu; + x = header()->offset() + p.x(); + idx = header()->logicalIndexAt(x); + switch (idx) { + case promptColIdx: + icon = item->icon(promptColIdx); + if (!icon.isNull()) { + int off = header()->sectionPosition(0) + visualRect(indexAt(p)).x() + 4; // 4 is Hardcoded image offset. There might be a way to do it properly. + if (x >= off && x < off + icon.availableSizes().first().width()) { + if (item->goParent) { + emit parentSelected(); + break; + } else if (!menu) + break; + ptype = menu->prompt ? menu->prompt->type : P_UNKNOWN; + if (ptype == P_MENU && rootEntry != menu && + mode != fullMode && mode != menuMode && + mode != listMode) + emit menuSelected(menu); + else + changeValue(item); + } + } + break; + case dataColIdx: + changeValue(item); + break; + } + +skip: + //printf("contentsMouseReleaseEvent: %d,%d\n", p.x(), p.y()); + Parent::mouseReleaseEvent(e); +} + +void ConfigList::mouseMoveEvent(QMouseEvent* e) +{ + //QPoint p(contentsToViewport(e->pos())); + //printf("contentsMouseMoveEvent: %d,%d\n", p.x(), p.y()); + Parent::mouseMoveEvent(e); +} + +void ConfigList::mouseDoubleClickEvent(QMouseEvent* e) +{ + QPoint p = e->pos(); + ConfigItem* item = (ConfigItem*)itemAt(p); + struct menu *menu; + enum prop_type ptype; + + if (!item) + goto skip; + if (item->goParent) { + emit parentSelected(); + goto skip; + } + menu = item->menu; + if (!menu) + goto skip; + ptype = menu->prompt ? menu->prompt->type : P_UNKNOWN; + if (ptype == P_MENU && mode != listMode) { + if (mode == singleMode) + emit itemSelected(menu); + else if (mode == symbolMode) + emit menuSelected(menu); + } else if (menu->sym) + changeValue(item); + +skip: + //printf("contentsMouseDoubleClickEvent: %d,%d\n", p.x(), p.y()); + Parent::mouseDoubleClickEvent(e); +} + +void ConfigList::focusInEvent(QFocusEvent *e) +{ + struct menu *menu = NULL; + + Parent::focusInEvent(e); + + ConfigItem* item = (ConfigItem *)currentItem(); + if (item) { + setSelected(item, true); + menu = item->menu; + } + emit gotFocus(menu); +} + +void ConfigList::contextMenuEvent(QContextMenuEvent *e) +{ + if (!headerPopup) { + QAction *action; + + headerPopup = new QMenu(this); + action = new QAction("Show Name", this); + action->setCheckable(true); + connect(action, SIGNAL(toggled(bool)), + SLOT(setShowName(bool))); + connect(this, SIGNAL(showNameChanged(bool)), + action, SLOT(setChecked(bool))); + action->setChecked(showName); + headerPopup->addAction(action); + } + + headerPopup->exec(e->globalPos()); + e->accept(); +} + +void ConfigList::setShowName(bool on) +{ + if (showName == on) + return; + + showName = on; + reinit(); + emit showNameChanged(on); +} + +QList<ConfigList *> ConfigList::allLists; +QAction *ConfigList::showNormalAction; +QAction *ConfigList::showAllAction; +QAction *ConfigList::showPromptAction; + +void ConfigList::setAllOpen(bool open) +{ + QTreeWidgetItemIterator it(this); + + while (*it) { + (*it)->setExpanded(open); + + ++it; + } +} + +ConfigInfoView::ConfigInfoView(QWidget* parent, const char *name) + : Parent(parent), sym(0), _menu(0) +{ + setObjectName(name); + setOpenLinks(false); + + if (!objectName().isEmpty()) { + configSettings->beginGroup(objectName()); + setShowDebug(configSettings->value("/showDebug", false).toBool()); + configSettings->endGroup(); + connect(configApp, SIGNAL(aboutToQuit()), SLOT(saveSettings())); + } + + contextMenu = createStandardContextMenu(); + QAction *action = new QAction("Show Debug Info", contextMenu); + + action->setCheckable(true); + connect(action, SIGNAL(toggled(bool)), SLOT(setShowDebug(bool))); + connect(this, SIGNAL(showDebugChanged(bool)), action, SLOT(setChecked(bool))); + action->setChecked(showDebug()); + contextMenu->addSeparator(); + contextMenu->addAction(action); +} + +void ConfigInfoView::saveSettings(void) +{ + if (!objectName().isEmpty()) { + configSettings->beginGroup(objectName()); + configSettings->setValue("/showDebug", showDebug()); + configSettings->endGroup(); + } +} + +void ConfigInfoView::setShowDebug(bool b) +{ + if (_showDebug != b) { + _showDebug = b; + if (_menu) + menuInfo(); + else if (sym) + symbolInfo(); + emit showDebugChanged(b); + } +} + +void ConfigInfoView::setInfo(struct menu *m) +{ + if (_menu == m) + return; + _menu = m; + sym = NULL; + if (!_menu) + clear(); + else + menuInfo(); +} + +void ConfigInfoView::symbolInfo(void) +{ + QString str; + + str += "<big>Symbol: <b>"; + str += print_filter(sym->name); + str += "</b></big><br><br>value: "; + str += print_filter(sym_get_string_value(sym)); + str += "<br>visibility: "; + str += sym->visible == yes ? "y" : sym->visible == mod ? "m" : "n"; + str += "<br>"; + str += debug_info(sym); + + setText(str); +} + +void ConfigInfoView::menuInfo(void) +{ + struct symbol* sym; + QString info; + QTextStream stream(&info); + + sym = _menu->sym; + if (sym) { + if (_menu->prompt) { + stream << "<big><b>"; + stream << print_filter(_menu->prompt->text); + stream << "</b></big>"; + if (sym->name) { + stream << " ("; + if (showDebug()) + stream << "<a href=\"s" << sym->name << "\">"; + stream << print_filter(sym->name); + if (showDebug()) + stream << "</a>"; + stream << ")"; + } + } else if (sym->name) { + stream << "<big><b>"; + if (showDebug()) + stream << "<a href=\"s" << sym->name << "\">"; + stream << print_filter(sym->name); + if (showDebug()) + stream << "</a>"; + stream << "</b></big>"; + } + stream << "<br><br>"; + + if (showDebug()) + stream << debug_info(sym); + + struct gstr help_gstr = str_new(); + + menu_get_ext_help(_menu, &help_gstr); + stream << print_filter(str_get(&help_gstr)); + str_free(&help_gstr); + } else if (_menu->prompt) { + stream << "<big><b>"; + stream << print_filter(_menu->prompt->text); + stream << "</b></big><br><br>"; + if (showDebug()) { + if (_menu->prompt->visible.expr) { + stream << "  dep: "; + expr_print(_menu->prompt->visible.expr, + expr_print_help, &stream, E_NONE); + stream << "<br><br>"; + } + + stream << "defined at " << _menu->file->name << ":" + << _menu->lineno << "<br><br>"; + } + } + + setText(info); +} + +QString ConfigInfoView::debug_info(struct symbol *sym) +{ + QString debug; + QTextStream stream(&debug); + + stream << "type: "; + stream << print_filter(sym_type_name(sym->type)); + if (sym_is_choice(sym)) + stream << " (choice)"; + debug += "<br>"; + if (sym->rev_dep.expr) { + stream << "reverse dep: "; + expr_print(sym->rev_dep.expr, expr_print_help, &stream, E_NONE); + stream << "<br>"; + } + for (struct property *prop = sym->prop; prop; prop = prop->next) { + switch (prop->type) { + case P_PROMPT: + case P_MENU: + stream << "prompt: <a href=\"m" << sym->name << "\">"; + stream << print_filter(prop->text); + stream << "</a><br>"; + break; + case P_DEFAULT: + case P_SELECT: + case P_RANGE: + case P_COMMENT: + case P_IMPLY: + case P_SYMBOL: + stream << prop_get_type_name(prop->type); + stream << ": "; + expr_print(prop->expr, expr_print_help, + &stream, E_NONE); + stream << "<br>"; + break; + case P_CHOICE: + if (sym_is_choice(sym)) { + stream << "choice: "; + expr_print(prop->expr, expr_print_help, + &stream, E_NONE); + stream << "<br>"; + } + break; + default: + stream << "unknown property: "; + stream << prop_get_type_name(prop->type); + stream << "<br>"; + } + if (prop->visible.expr) { + stream << "    dep: "; + expr_print(prop->visible.expr, expr_print_help, + &stream, E_NONE); + stream << "<br>"; + } + } + stream << "<br>"; + + return debug; +} + +QString ConfigInfoView::print_filter(const QString &str) +{ + QRegExp re("[<>&\"\\n]"); + QString res = str; + for (int i = 0; (i = res.indexOf(re, i)) >= 0;) { + switch (res[i].toLatin1()) { + case '<': + res.replace(i, 1, "<"); + i += 4; + break; + case '>': + res.replace(i, 1, ">"); + i += 4; + break; + case '&': + res.replace(i, 1, "&"); + i += 5; + break; + case '"': + res.replace(i, 1, """); + i += 6; + break; + case '\n': + res.replace(i, 1, "<br>"); + i += 4; + break; + } + } + return res; +} + +void ConfigInfoView::expr_print_help(void *data, struct symbol *sym, const char *str) +{ + QTextStream *stream = reinterpret_cast<QTextStream *>(data); + + if (sym && sym->name && !(sym->flags & SYMBOL_CONST)) { + *stream << "<a href=\"s" << sym->name << "\">"; + *stream << print_filter(str); + *stream << "</a>"; + } else { + *stream << print_filter(str); + } +} + +void ConfigInfoView::clicked(const QUrl &url) +{ + QByteArray str = url.toEncoded(); + const std::size_t count = str.size(); + char *data = new char[count + 1]; + struct symbol **result; + struct menu *m = NULL; + + if (count < 1) { + delete[] data; + return; + } + + memcpy(data, str.constData(), count); + data[count] = '\0'; + + /* Seek for exact match */ + data[0] = '^'; + strcat(data, "$"); + result = sym_re_search(data); + if (!result) { + delete[] data; + return; + } + + sym = *result; + + /* Seek for the menu which holds the symbol */ + for (struct property *prop = sym->prop; prop; prop = prop->next) { + if (prop->type != P_PROMPT && prop->type != P_MENU) + continue; + m = prop->menu; + break; + } + + if (!m) { + /* Symbol is not visible as a menu */ + symbolInfo(); + emit showDebugChanged(true); + } else { + emit menuSelected(m); + } + + free(result); + delete[] data; +} + +void ConfigInfoView::contextMenuEvent(QContextMenuEvent *event) +{ + contextMenu->popup(event->globalPos()); + event->accept(); +} + +ConfigSearchWindow::ConfigSearchWindow(ConfigMainWindow *parent) + : Parent(parent), result(NULL) +{ + setObjectName("search"); + setWindowTitle("Search Config"); + + QVBoxLayout* layout1 = new QVBoxLayout(this); + layout1->setContentsMargins(11, 11, 11, 11); + layout1->setSpacing(6); + + QHBoxLayout* layout2 = new QHBoxLayout(); + layout2->setContentsMargins(0, 0, 0, 0); + layout2->setSpacing(6); + layout2->addWidget(new QLabel("Find:", this)); + editField = new QLineEdit(this); + connect(editField, SIGNAL(returnPressed()), SLOT(search())); + layout2->addWidget(editField); + searchButton = new QPushButton("Search", this); + searchButton->setAutoDefault(false); + connect(searchButton, SIGNAL(clicked()), SLOT(search())); + layout2->addWidget(searchButton); + layout1->addLayout(layout2); + + split = new QSplitter(this); + split->setOrientation(Qt::Vertical); + list = new ConfigList(split, "search"); + list->mode = listMode; + info = new ConfigInfoView(split, "search"); + connect(list, SIGNAL(menuChanged(struct menu *)), + info, SLOT(setInfo(struct menu *))); + connect(list, SIGNAL(menuChanged(struct menu *)), + parent, SLOT(setMenuLink(struct menu *))); + + layout1->addWidget(split); + + QVariant x, y; + int width, height; + bool ok; + + configSettings->beginGroup("search"); + width = configSettings->value("/window width", parent->width() / 2).toInt(); + height = configSettings->value("/window height", parent->height() / 2).toInt(); + resize(width, height); + x = configSettings->value("/window x"); + y = configSettings->value("/window y"); + if (x.isValid() && y.isValid()) + move(x.toInt(), y.toInt()); + QList<int> sizes = configSettings->readSizes("/split", &ok); + if (ok) + split->setSizes(sizes); + configSettings->endGroup(); + connect(configApp, SIGNAL(aboutToQuit()), SLOT(saveSettings())); +} + +void ConfigSearchWindow::saveSettings(void) +{ + if (!objectName().isEmpty()) { + configSettings->beginGroup(objectName()); + configSettings->setValue("/window x", pos().x()); + configSettings->setValue("/window y", pos().y()); + configSettings->setValue("/window width", size().width()); + configSettings->setValue("/window height", size().height()); + configSettings->writeSizes("/split", split->sizes()); + configSettings->endGroup(); + } +} + +void ConfigSearchWindow::search(void) +{ + struct symbol **p; + struct property *prop; + ConfigItem *lastItem = NULL; + + free(result); + list->clear(); + info->clear(); + + result = sym_re_search(editField->text().toLatin1()); + if (!result) + return; + for (p = result; *p; p++) { + for_all_prompts((*p), prop) + lastItem = new ConfigItem(list, lastItem, prop->menu, + menu_is_visible(prop->menu)); + } +} + +/* + * Construct the complete config widget + */ +ConfigMainWindow::ConfigMainWindow(void) + : searchWindow(0) +{ + bool ok = true; + QVariant x, y; + int width, height; + char title[256]; + + QDesktopWidget *d = configApp->desktop(); + snprintf(title, sizeof(title), "%s%s", + rootmenu.prompt->text, + "" + ); + setWindowTitle(title); + + width = configSettings->value("/window width", d->width() - 64).toInt(); + height = configSettings->value("/window height", d->height() - 64).toInt(); + resize(width, height); + x = configSettings->value("/window x"); + y = configSettings->value("/window y"); + if ((x.isValid())&&(y.isValid())) + move(x.toInt(), y.toInt()); + + // set up icons + ConfigItem::symbolYesIcon = QIcon(QPixmap(xpm_symbol_yes)); + ConfigItem::symbolModIcon = QIcon(QPixmap(xpm_symbol_mod)); + ConfigItem::symbolNoIcon = QIcon(QPixmap(xpm_symbol_no)); + ConfigItem::choiceYesIcon = QIcon(QPixmap(xpm_choice_yes)); + ConfigItem::choiceNoIcon = QIcon(QPixmap(xpm_choice_no)); + ConfigItem::menuIcon = QIcon(QPixmap(xpm_menu)); + ConfigItem::menubackIcon = QIcon(QPixmap(xpm_menuback)); + + QWidget *widget = new QWidget(this); + QVBoxLayout *layout = new QVBoxLayout(widget); + setCentralWidget(widget); + + split1 = new QSplitter(widget); + split1->setOrientation(Qt::Horizontal); + split1->setChildrenCollapsible(false); + + menuList = new ConfigList(widget, "menu"); + + split2 = new QSplitter(widget); + split2->setChildrenCollapsible(false); + split2->setOrientation(Qt::Vertical); + + // create config tree + configList = new ConfigList(widget, "config"); + + helpText = new ConfigInfoView(widget, "help"); + + layout->addWidget(split2); + split2->addWidget(split1); + split1->addWidget(configList); + split1->addWidget(menuList); + split2->addWidget(helpText); + + setTabOrder(configList, helpText); + configList->setFocus(); + + backAction = new QAction(QPixmap(xpm_back), "Back", this); + connect(backAction, SIGNAL(triggered(bool)), SLOT(goBack())); + + QAction *quitAction = new QAction("&Quit", this); + quitAction->setShortcut(Qt::CTRL + Qt::Key_Q); + connect(quitAction, SIGNAL(triggered(bool)), SLOT(close())); + + QAction *loadAction = new QAction(QPixmap(xpm_load), "&Load", this); + loadAction->setShortcut(Qt::CTRL + Qt::Key_L); + connect(loadAction, SIGNAL(triggered(bool)), SLOT(loadConfig())); + + saveAction = new QAction(QPixmap(xpm_save), "&Save", this); + saveAction->setShortcut(Qt::CTRL + Qt::Key_S); + connect(saveAction, SIGNAL(triggered(bool)), SLOT(saveConfig())); + + conf_set_changed_callback(conf_changed); + + // Set saveAction's initial state + conf_changed(); + configname = xstrdup(conf_get_configname()); + + QAction *saveAsAction = new QAction("Save &As...", this); + connect(saveAsAction, SIGNAL(triggered(bool)), SLOT(saveConfigAs())); + QAction *searchAction = new QAction("&Find", this); + searchAction->setShortcut(Qt::CTRL + Qt::Key_F); + connect(searchAction, SIGNAL(triggered(bool)), SLOT(searchConfig())); + singleViewAction = new QAction(QPixmap(xpm_single_view), "Single View", this); + singleViewAction->setCheckable(true); + connect(singleViewAction, SIGNAL(triggered(bool)), SLOT(showSingleView())); + splitViewAction = new QAction(QPixmap(xpm_split_view), "Split View", this); + splitViewAction->setCheckable(true); + connect(splitViewAction, SIGNAL(triggered(bool)), SLOT(showSplitView())); + fullViewAction = new QAction(QPixmap(xpm_tree_view), "Full View", this); + fullViewAction->setCheckable(true); + connect(fullViewAction, SIGNAL(triggered(bool)), SLOT(showFullView())); + + QAction *showNameAction = new QAction("Show Name", this); + showNameAction->setCheckable(true); + connect(showNameAction, SIGNAL(toggled(bool)), configList, SLOT(setShowName(bool))); + showNameAction->setChecked(configList->showName); + + QActionGroup *optGroup = new QActionGroup(this); + optGroup->setExclusive(true); + connect(optGroup, SIGNAL(triggered(QAction*)), configList, + SLOT(setOptionMode(QAction *))); + connect(optGroup, SIGNAL(triggered(QAction *)), menuList, + SLOT(setOptionMode(QAction *))); + + ConfigList::showNormalAction = new QAction("Show Normal Options", optGroup); + ConfigList::showNormalAction->setCheckable(true); + ConfigList::showAllAction = new QAction("Show All Options", optGroup); + ConfigList::showAllAction->setCheckable(true); + ConfigList::showPromptAction = new QAction("Show Prompt Options", optGroup); + ConfigList::showPromptAction->setCheckable(true); + + QAction *showDebugAction = new QAction("Show Debug Info", this); + showDebugAction->setCheckable(true); + connect(showDebugAction, SIGNAL(toggled(bool)), helpText, SLOT(setShowDebug(bool))); + showDebugAction->setChecked(helpText->showDebug()); + + QAction *showIntroAction = new QAction("Introduction", this); + connect(showIntroAction, SIGNAL(triggered(bool)), SLOT(showIntro())); + QAction *showAboutAction = new QAction("About", this); + connect(showAboutAction, SIGNAL(triggered(bool)), SLOT(showAbout())); + + // init tool bar + QToolBar *toolBar = addToolBar("Tools"); + toolBar->addAction(backAction); + toolBar->addSeparator(); + toolBar->addAction(loadAction); + toolBar->addAction(saveAction); + toolBar->addSeparator(); + toolBar->addAction(singleViewAction); + toolBar->addAction(splitViewAction); + toolBar->addAction(fullViewAction); + + // create file menu + QMenu *menu = menuBar()->addMenu("&File"); + menu->addAction(loadAction); + menu->addAction(saveAction); + menu->addAction(saveAsAction); + menu->addSeparator(); + menu->addAction(quitAction); + + // create edit menu + menu = menuBar()->addMenu("&Edit"); + menu->addAction(searchAction); + + // create options menu + menu = menuBar()->addMenu("&Option"); + menu->addAction(showNameAction); + menu->addSeparator(); + menu->addActions(optGroup->actions()); + menu->addSeparator(); + menu->addAction(showDebugAction); + + // create help menu + menu = menuBar()->addMenu("&Help"); + menu->addAction(showIntroAction); + menu->addAction(showAboutAction); + + connect (helpText, SIGNAL (anchorClicked (const QUrl &)), + helpText, SLOT (clicked (const QUrl &)) ); + + connect(configList, SIGNAL(menuChanged(struct menu *)), + helpText, SLOT(setInfo(struct menu *))); + connect(configList, SIGNAL(menuSelected(struct menu *)), + SLOT(changeMenu(struct menu *))); + connect(configList, SIGNAL(itemSelected(struct menu *)), + SLOT(changeItens(struct menu *))); + connect(configList, SIGNAL(parentSelected()), + SLOT(goBack())); + connect(menuList, SIGNAL(menuChanged(struct menu *)), + helpText, SLOT(setInfo(struct menu *))); + connect(menuList, SIGNAL(menuSelected(struct menu *)), + SLOT(changeMenu(struct menu *))); + + connect(configList, SIGNAL(gotFocus(struct menu *)), + helpText, SLOT(setInfo(struct menu *))); + connect(menuList, SIGNAL(gotFocus(struct menu *)), + helpText, SLOT(setInfo(struct menu *))); + connect(menuList, SIGNAL(gotFocus(struct menu *)), + SLOT(listFocusChanged(void))); + connect(helpText, SIGNAL(menuSelected(struct menu *)), + SLOT(setMenuLink(struct menu *))); + + QString listMode = configSettings->value("/listMode", "symbol").toString(); + if (listMode == "single") + showSingleView(); + else if (listMode == "full") + showFullView(); + else /*if (listMode == "split")*/ + showSplitView(); + + // UI setup done, restore splitter positions + QList<int> sizes = configSettings->readSizes("/split1", &ok); + if (ok) + split1->setSizes(sizes); + + sizes = configSettings->readSizes("/split2", &ok); + if (ok) + split2->setSizes(sizes); +} + +void ConfigMainWindow::loadConfig(void) +{ + QString str; + QByteArray ba; + const char *name; + + str = QFileDialog::getOpenFileName(this, "", configname); + if (str.isNull()) + return; + + ba = str.toLocal8Bit(); + name = ba.data(); + + if (conf_read(name)) + QMessageBox::information(this, "qconf", "Unable to load configuration!"); + + free(configname); + configname = xstrdup(name); + + ConfigList::updateListAllForAll(); +} + +bool ConfigMainWindow::saveConfig(void) +{ + if (conf_write(configname)) { + QMessageBox::information(this, "qconf", "Unable to save configuration!"); + return false; + } + conf_write_autoconf(0); + + return true; +} + +void ConfigMainWindow::saveConfigAs(void) +{ + QString str; + QByteArray ba; + const char *name; + + str = QFileDialog::getSaveFileName(this, "", configname); + if (str.isNull()) + return; + + ba = str.toLocal8Bit(); + name = ba.data(); + + if (conf_write(name)) { + QMessageBox::information(this, "qconf", "Unable to save configuration!"); + } + conf_write_autoconf(0); + + free(configname); + configname = xstrdup(name); +} + +void ConfigMainWindow::searchConfig(void) +{ + if (!searchWindow) + searchWindow = new ConfigSearchWindow(this); + searchWindow->show(); +} + +void ConfigMainWindow::changeItens(struct menu *menu) +{ + configList->setRootMenu(menu); +} + +void ConfigMainWindow::changeMenu(struct menu *menu) +{ + menuList->setRootMenu(menu); +} + +void ConfigMainWindow::setMenuLink(struct menu *menu) +{ + struct menu *parent; + ConfigList* list = NULL; + ConfigItem* item; + + if (configList->menuSkip(menu)) + return; + + switch (configList->mode) { + case singleMode: + list = configList; + parent = menu_get_parent_menu(menu); + if (!parent) + return; + list->setRootMenu(parent); + break; + case menuMode: + if (menu->flags & MENU_ROOT) { + menuList->setRootMenu(menu); + configList->clearSelection(); + list = configList; + } else { + parent = menu_get_parent_menu(menu->parent); + if (!parent) + return; + + /* Select the config view */ + item = configList->findConfigItem(parent); + if (item) { + configList->setSelected(item, true); + configList->scrollToItem(item); + } + + menuList->setRootMenu(parent); + menuList->clearSelection(); + list = menuList; + } + break; + case fullMode: + list = configList; + break; + default: + break; + } + + if (list) { + item = list->findConfigItem(menu); + if (item) { + list->setSelected(item, true); + list->scrollToItem(item); + list->setFocus(); + helpText->setInfo(menu); + } + } +} + +void ConfigMainWindow::listFocusChanged(void) +{ + if (menuList->mode == menuMode) + configList->clearSelection(); +} + +void ConfigMainWindow::goBack(void) +{ + if (configList->rootEntry == &rootmenu) + return; + + configList->setParentMenu(); +} + +void ConfigMainWindow::showSingleView(void) +{ + singleViewAction->setEnabled(false); + singleViewAction->setChecked(true); + splitViewAction->setEnabled(true); + splitViewAction->setChecked(false); + fullViewAction->setEnabled(true); + fullViewAction->setChecked(false); + + backAction->setEnabled(true); + + menuList->hide(); + menuList->setRootMenu(0); + configList->mode = singleMode; + if (configList->rootEntry == &rootmenu) + configList->updateListAll(); + else + configList->setRootMenu(&rootmenu); + configList->setFocus(); +} + +void ConfigMainWindow::showSplitView(void) +{ + singleViewAction->setEnabled(true); + singleViewAction->setChecked(false); + splitViewAction->setEnabled(false); + splitViewAction->setChecked(true); + fullViewAction->setEnabled(true); + fullViewAction->setChecked(false); + + backAction->setEnabled(false); + + configList->mode = menuMode; + if (configList->rootEntry == &rootmenu) + configList->updateListAll(); + else + configList->setRootMenu(&rootmenu); + configList->setAllOpen(true); + configApp->processEvents(); + menuList->mode = symbolMode; + menuList->setRootMenu(&rootmenu); + menuList->setAllOpen(true); + menuList->show(); + menuList->setFocus(); +} + +void ConfigMainWindow::showFullView(void) +{ + singleViewAction->setEnabled(true); + singleViewAction->setChecked(false); + splitViewAction->setEnabled(true); + splitViewAction->setChecked(false); + fullViewAction->setEnabled(false); + fullViewAction->setChecked(true); + + backAction->setEnabled(false); + + menuList->hide(); + menuList->setRootMenu(0); + configList->mode = fullMode; + if (configList->rootEntry == &rootmenu) + configList->updateListAll(); + else + configList->setRootMenu(&rootmenu); + configList->setFocus(); +} + +/* + * ask for saving configuration before quitting + */ +void ConfigMainWindow::closeEvent(QCloseEvent* e) +{ + if (!conf_get_changed()) { + e->accept(); + return; + } + QMessageBox mb("qconf", "Save configuration?", QMessageBox::Warning, + QMessageBox::Yes | QMessageBox::Default, QMessageBox::No, QMessageBox::Cancel | QMessageBox::Escape); + mb.setButtonText(QMessageBox::Yes, "&Save Changes"); + mb.setButtonText(QMessageBox::No, "&Discard Changes"); + mb.setButtonText(QMessageBox::Cancel, "Cancel Exit"); + switch (mb.exec()) { + case QMessageBox::Yes: + if (saveConfig()) + e->accept(); + else + e->ignore(); + break; + case QMessageBox::No: + e->accept(); + break; + case QMessageBox::Cancel: + e->ignore(); + break; + } +} + +void ConfigMainWindow::showIntro(void) +{ + static const QString str = + "Welcome to the qconf graphical configuration tool.\n" + "\n" + "For bool and tristate options, a blank box indicates the " + "feature is disabled, a check indicates it is enabled, and a " + "dot indicates that it is to be compiled as a module. Clicking " + "on the box will cycle through the three states. For int, hex, " + "and string options, double-clicking or pressing F2 on the " + "Value cell will allow you to edit the value.\n" + "\n" + "If you do not see an option (e.g., a device driver) that you " + "believe should be present, try turning on Show All Options " + "under the Options menu. Enabling Show Debug Info will help you" + "figure out what other options must be enabled to support the " + "option you are interested in, and hyperlinks will navigate to " + "them.\n" + "\n" + "Toggling Show Debug Info under the Options menu will show the " + "dependencies, which you can then match by examining other " + "options.\n"; + + QMessageBox::information(this, "qconf", str); +} + +void ConfigMainWindow::showAbout(void) +{ + static const QString str = "qconf is Copyright (C) 2002 Roman Zippel <zippel@linux-m68k.org>.\n" + "Copyright (C) 2015 Boris Barbulovski <bbarbulovski@gmail.com>.\n\n" + "Bug reports and feature request can also be entered at http://bugzilla.kernel.org/\n"; + + QMessageBox::information(this, "qconf", str); +} + +void ConfigMainWindow::saveSettings(void) +{ + configSettings->setValue("/window x", pos().x()); + configSettings->setValue("/window y", pos().y()); + configSettings->setValue("/window width", size().width()); + configSettings->setValue("/window height", size().height()); + + QString entry; + switch(configList->mode) { + case singleMode : + entry = "single"; + break; + + case symbolMode : + entry = "split"; + break; + + case fullMode : + entry = "full"; + break; + + default: + break; + } + configSettings->setValue("/listMode", entry); + + configSettings->writeSizes("/split1", split1->sizes()); + configSettings->writeSizes("/split2", split2->sizes()); +} + +void ConfigMainWindow::conf_changed(void) +{ + if (saveAction) + saveAction->setEnabled(conf_get_changed()); +} + +void fixup_rootmenu(struct menu *menu) +{ + struct menu *child; + static int menu_cnt = 0; + + menu->flags |= MENU_ROOT; + for (child = menu->list; child; child = child->next) { + if (child->prompt && child->prompt->type == P_MENU) { + menu_cnt++; + fixup_rootmenu(child); + menu_cnt--; + } else if (!menu_cnt) + fixup_rootmenu(child); + } +} + +static const char *progname; + +static void usage(void) +{ + printf("%s [-s] <config>\n", progname); + exit(0); +} + +int main(int ac, char** av) +{ + ConfigMainWindow* v; + const char *name; + + progname = av[0]; + if (ac > 1 && av[1][0] == '-') { + switch (av[1][1]) { + case 's': + conf_set_message_callback(NULL); + break; + case 'h': + case '?': + usage(); + } + name = av[2]; + } else + name = av[1]; + if (!name) + usage(); + + conf_parse(name); + fixup_rootmenu(&rootmenu); + conf_read(NULL); + //zconfdump(stdout); + + configApp = new QApplication(ac, av); + + configSettings = new ConfigSettings(); + configSettings->beginGroup("/kconfig/qconf"); + v = new ConfigMainWindow(); + + //zconfdump(stdout); + configApp->connect(configApp, SIGNAL(lastWindowClosed()), SLOT(quit())); + configApp->connect(configApp, SIGNAL(aboutToQuit()), v, SLOT(saveSettings())); + v->show(); + configApp->exec(); + + configSettings->endGroup(); + delete configSettings; + delete v; + delete configApp; + + return 0; +} diff --git a/src/net/scripts/kconfig/qconf.h b/src/net/scripts/kconfig/qconf.h new file mode 100644 index 0000000..78b0a1d --- /dev/null +++ b/src/net/scripts/kconfig/qconf.h @@ -0,0 +1,275 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2002 Roman Zippel <zippel@linux-m68k.org> + */ + +#include <QCheckBox> +#include <QDialog> +#include <QHeaderView> +#include <QLineEdit> +#include <QMainWindow> +#include <QPushButton> +#include <QSettings> +#include <QSplitter> +#include <QStyledItemDelegate> +#include <QTextBrowser> +#include <QTreeWidget> + +#include "expr.h" + +class ConfigList; +class ConfigItem; +class ConfigMainWindow; + +class ConfigSettings : public QSettings { +public: + ConfigSettings(); + QList<int> readSizes(const QString& key, bool *ok); + bool writeSizes(const QString& key, const QList<int>& value); +}; + +enum colIdx { + promptColIdx, nameColIdx, dataColIdx +}; +enum listMode { + singleMode, menuMode, symbolMode, fullMode, listMode +}; +enum optionMode { + normalOpt = 0, allOpt, promptOpt +}; + +class ConfigList : public QTreeWidget { + Q_OBJECT + typedef class QTreeWidget Parent; +public: + ConfigList(QWidget *parent, const char *name = 0); + ~ConfigList(); + void reinit(void); + ConfigItem* findConfigItem(struct menu *); + void setSelected(QTreeWidgetItem *item, bool enable) { + for (int i = 0; i < selectedItems().size(); i++) + selectedItems().at(i)->setSelected(false); + + item->setSelected(enable); + } + +protected: + void keyPressEvent(QKeyEvent *e); + void mousePressEvent(QMouseEvent *e); + void mouseReleaseEvent(QMouseEvent *e); + void mouseMoveEvent(QMouseEvent *e); + void mouseDoubleClickEvent(QMouseEvent *e); + void focusInEvent(QFocusEvent *e); + void contextMenuEvent(QContextMenuEvent *e); + +public slots: + void setRootMenu(struct menu *menu); + + void updateList(); + void setValue(ConfigItem* item, tristate val); + void changeValue(ConfigItem* item); + void updateSelection(void); + void saveSettings(void); + void setOptionMode(QAction *action); + void setShowName(bool on); + +signals: + void menuChanged(struct menu *menu); + void menuSelected(struct menu *menu); + void itemSelected(struct menu *menu); + void parentSelected(void); + void gotFocus(struct menu *); + void showNameChanged(bool on); + +public: + void updateListAll(void) + { + updateAll = true; + updateList(); + updateAll = false; + } + void setAllOpen(bool open); + void setParentMenu(void); + + bool menuSkip(struct menu *); + + void updateMenuList(ConfigItem *parent, struct menu*); + void updateMenuList(struct menu *menu); + + bool updateAll; + + bool showName; + enum listMode mode; + enum optionMode optMode; + struct menu *rootEntry; + QPalette disabledColorGroup; + QPalette inactivedColorGroup; + QMenu* headerPopup; + + static QList<ConfigList *> allLists; + static void updateListForAll(); + static void updateListAllForAll(); + + static QAction *showNormalAction, *showAllAction, *showPromptAction; +}; + +class ConfigItem : public QTreeWidgetItem { + typedef class QTreeWidgetItem Parent; +public: + ConfigItem(ConfigList *parent, ConfigItem *after, struct menu *m, bool v) + : Parent(parent, after), nextItem(0), menu(m), visible(v), goParent(false) + { + init(); + } + ConfigItem(ConfigItem *parent, ConfigItem *after, struct menu *m, bool v) + : Parent(parent, after), nextItem(0), menu(m), visible(v), goParent(false) + { + init(); + } + ConfigItem(ConfigList *parent, ConfigItem *after, bool v) + : Parent(parent, after), nextItem(0), menu(0), visible(v), goParent(true) + { + init(); + } + ~ConfigItem(void); + void init(void); + void updateMenu(void); + void testUpdateMenu(bool v); + ConfigList* listView() const + { + return (ConfigList*)Parent::treeWidget(); + } + ConfigItem* firstChild() const + { + return (ConfigItem *)Parent::child(0); + } + ConfigItem* nextSibling() + { + ConfigItem *ret = NULL; + ConfigItem *_parent = (ConfigItem *)parent(); + + if(_parent) { + ret = (ConfigItem *)_parent->child(_parent->indexOfChild(this)+1); + } else { + QTreeWidget *_treeWidget = treeWidget(); + ret = (ConfigItem *)_treeWidget->topLevelItem(_treeWidget->indexOfTopLevelItem(this)+1); + } + + return ret; + } + // TODO: Implement paintCell + + ConfigItem* nextItem; + struct menu *menu; + bool visible; + bool goParent; + + static QIcon symbolYesIcon, symbolModIcon, symbolNoIcon; + static QIcon choiceYesIcon, choiceNoIcon; + static QIcon menuIcon, menubackIcon; +}; + +class ConfigItemDelegate : public QStyledItemDelegate +{ +private: + struct menu *menu; +public: + ConfigItemDelegate(QObject *parent = nullptr) + : QStyledItemDelegate(parent) {} + QWidget *createEditor(QWidget *parent, + const QStyleOptionViewItem &option, + const QModelIndex &index) const override; + void setModelData(QWidget *editor, QAbstractItemModel *model, + const QModelIndex &index) const override; +}; + +class ConfigInfoView : public QTextBrowser { + Q_OBJECT + typedef class QTextBrowser Parent; + QMenu *contextMenu; +public: + ConfigInfoView(QWidget* parent, const char *name = 0); + bool showDebug(void) const { return _showDebug; } + +public slots: + void setInfo(struct menu *menu); + void saveSettings(void); + void setShowDebug(bool); + void clicked (const QUrl &url); + +signals: + void showDebugChanged(bool); + void menuSelected(struct menu *); + +protected: + void symbolInfo(void); + void menuInfo(void); + QString debug_info(struct symbol *sym); + static QString print_filter(const QString &str); + static void expr_print_help(void *data, struct symbol *sym, const char *str); + void contextMenuEvent(QContextMenuEvent *event); + + struct symbol *sym; + struct menu *_menu; + bool _showDebug; +}; + +class ConfigSearchWindow : public QDialog { + Q_OBJECT + typedef class QDialog Parent; +public: + ConfigSearchWindow(ConfigMainWindow *parent); + +public slots: + void saveSettings(void); + void search(void); + +protected: + QLineEdit* editField; + QPushButton* searchButton; + QSplitter* split; + ConfigList *list; + ConfigInfoView* info; + + struct symbol **result; +}; + +class ConfigMainWindow : public QMainWindow { + Q_OBJECT + + char *configname; + static QAction *saveAction; + static void conf_changed(void); +public: + ConfigMainWindow(void); +public slots: + void changeMenu(struct menu *); + void changeItens(struct menu *); + void setMenuLink(struct menu *); + void listFocusChanged(void); + void goBack(void); + void loadConfig(void); + bool saveConfig(void); + void saveConfigAs(void); + void searchConfig(void); + void showSingleView(void); + void showSplitView(void); + void showFullView(void); + void showIntro(void); + void showAbout(void); + void saveSettings(void); + +protected: + void closeEvent(QCloseEvent *e); + + ConfigSearchWindow *searchWindow; + ConfigList *menuList; + ConfigList *configList; + ConfigInfoView *helpText; + QAction *backAction; + QAction *singleViewAction; + QAction *splitViewAction; + QAction *fullViewAction; + QSplitter *split1; + QSplitter *split2; +}; diff --git a/src/net/scripts/kconfig/streamline_config.pl b/src/net/scripts/kconfig/streamline_config.pl new file mode 100755 index 0000000..1c78ba4 --- /dev/null +++ b/src/net/scripts/kconfig/streamline_config.pl @@ -0,0 +1,704 @@ +#!/usr/bin/env perl +# SPDX-License-Identifier: GPL-2.0 +# +# Copyright 2005-2009 - Steven Rostedt +# +# It's simple enough to figure out how this works. +# If not, then you can ask me at stripconfig@goodmis.org +# +# What it does? +# +# If you have installed a Linux kernel from a distribution +# that turns on way too many modules than you need, and +# you only want the modules you use, then this program +# is perfect for you. +# +# It gives you the ability to turn off all the modules that are +# not loaded on your system. +# +# Howto: +# +# 1. Boot up the kernel that you want to stream line the config on. +# 2. Change directory to the directory holding the source of the +# kernel that you just booted. +# 3. Copy the configuraton file to this directory as .config +# 4. Have all your devices that you need modules for connected and +# operational (make sure that their corresponding modules are loaded) +# 5. Run this script redirecting the output to some other file +# like config_strip. +# 6. Back up your old config (if you want too). +# 7. copy the config_strip file to .config +# 8. Run "make oldconfig" +# +# Now your kernel is ready to be built with only the modules that +# are loaded. +# +# Here's what I did with my Debian distribution. +# +# cd /usr/src/linux-2.6.10 +# cp /boot/config-2.6.10-1-686-smp .config +# ~/bin/streamline_config > config_strip +# mv .config config_sav +# mv config_strip .config +# make oldconfig +# +use warnings; +use strict; +use Getopt::Long; + +# set the environment variable LOCALMODCONFIG_DEBUG to get +# debug output. +my $debugprint = 0; +$debugprint = 1 if (defined($ENV{LOCALMODCONFIG_DEBUG})); + +sub dprint { + return if (!$debugprint); + print STDERR @_; +} + +my $uname = `uname -r`; +chomp $uname; + +my @searchconfigs = ( + { + "file" => ".config", + "exec" => "cat", + }, + { + "file" => "/proc/config.gz", + "exec" => "zcat", + }, + { + "file" => "/boot/config-$uname", + "exec" => "cat", + }, + { + "file" => "/boot/vmlinuz-$uname", + "exec" => "scripts/extract-ikconfig", + "test" => "scripts/extract-ikconfig", + }, + { + "file" => "vmlinux", + "exec" => "scripts/extract-ikconfig", + "test" => "scripts/extract-ikconfig", + }, + { + "file" => "/lib/modules/$uname/kernel/kernel/configs.ko", + "exec" => "scripts/extract-ikconfig", + "test" => "scripts/extract-ikconfig", + }, + { + "file" => "kernel/configs.ko", + "exec" => "scripts/extract-ikconfig", + "test" => "scripts/extract-ikconfig", + }, + { + "file" => "kernel/configs.o", + "exec" => "scripts/extract-ikconfig", + "test" => "scripts/extract-ikconfig", + }, +); + +sub read_config { + foreach my $conf (@searchconfigs) { + my $file = $conf->{"file"}; + + next if ( ! -f "$file"); + + if (defined($conf->{"test"})) { + `$conf->{"test"} $conf->{"file"} 2>/dev/null`; + next if ($?); + } + + my $exec = $conf->{"exec"}; + + print STDERR "using config: '$file'\n"; + + open(my $infile, '-|', "$exec $file") || die "Failed to run $exec $file"; + my @x = <$infile>; + close $infile; + return @x; + } + die "No config file found"; +} + +my @config_file = read_config; + +# Parse options +my $localmodconfig = 0; +my $localyesconfig = 0; + +GetOptions("localmodconfig" => \$localmodconfig, + "localyesconfig" => \$localyesconfig); + +# Get the build source and top level Kconfig file (passed in) +my $ksource = ($ARGV[0] ? $ARGV[0] : '.'); +my $kconfig = $ARGV[1]; +my $lsmod_file = $ENV{'LSMOD'}; + +my @makefiles = `find $ksource -name Makefile -or -name Kbuild 2>/dev/null`; +chomp @makefiles; + +my %depends; +my %selects; +my %prompts; +my %objects; +my %config2kfile; +my $var; +my $iflevel = 0; +my @ifdeps; + +# prevent recursion +my %read_kconfigs; + +sub read_kconfig { + my ($kconfig) = @_; + + my $state = "NONE"; + my $config; + + my $cont = 0; + my $line; + + my $source = "$ksource/$kconfig"; + my $last_source = ""; + + # Check for any environment variables used + while ($source =~ /\$\((\w+)\)/ && $last_source ne $source) { + my $env = $1; + $last_source = $source; + $source =~ s/\$\($env\)/$ENV{$env}/; + } + + open(my $kinfile, '<', $source) || die "Can't open $kconfig"; + while (<$kinfile>) { + chomp; + + # Make sure that lines ending with \ continue + if ($cont) { + $_ = $line . " " . $_; + } + + if (s/\\$//) { + $cont = 1; + $line = $_; + next; + } + + $cont = 0; + + # collect any Kconfig sources + if (/^source\s+"?([^"]+)/) { + my $kconfig = $1; + # prevent reading twice. + if (!defined($read_kconfigs{$kconfig})) { + $read_kconfigs{$kconfig} = 1; + read_kconfig($kconfig); + } + next; + } + + # configs found + if (/^\s*(menu)?config\s+(\S+)\s*$/) { + $state = "NEW"; + $config = $2; + $config2kfile{"CONFIG_$config"} = $kconfig; + + # Add depends for 'if' nesting + for (my $i = 0; $i < $iflevel; $i++) { + if ($i) { + $depends{$config} .= " " . $ifdeps[$i]; + } else { + $depends{$config} = $ifdeps[$i]; + } + $state = "DEP"; + } + + # collect the depends for the config + } elsif ($state eq "NEW" && /^\s*depends\s+on\s+(.*)$/) { + $state = "DEP"; + $depends{$config} = $1; + } elsif ($state eq "DEP" && /^\s*depends\s+on\s+(.*)$/) { + $depends{$config} .= " " . $1; + } elsif ($state eq "DEP" && /^\s*def(_(bool|tristate)|ault)\s+(\S.*)$/) { + my $dep = $3; + if ($dep !~ /^\s*(y|m|n)\s*$/) { + $dep =~ s/.*\sif\s+//; + $depends{$config} .= " " . $dep; + dprint "Added default depends $dep to $config\n"; + } + + # Get the configs that select this config + } elsif ($state ne "NONE" && /^\s*select\s+(\S+)/) { + my $conf = $1; + if (defined($selects{$conf})) { + $selects{$conf} .= " " . $config; + } else { + $selects{$conf} = $config; + } + + # configs without prompts must be selected + } elsif ($state ne "NONE" && /^\s*(tristate\s+\S|prompt\b)/) { + # note if the config has a prompt + $prompts{$config} = 1; + + # Check for if statements + } elsif (/^if\s+(.*\S)\s*$/) { + my $deps = $1; + # remove beginning and ending non text + $deps =~ s/^[^a-zA-Z0-9_]*//; + $deps =~ s/[^a-zA-Z0-9_]*$//; + + my @deps = split /[^a-zA-Z0-9_]+/, $deps; + + $ifdeps[$iflevel++] = join ':', @deps; + + } elsif (/^endif/) { + + $iflevel-- if ($iflevel); + + # stop on "help" and keywords that end a menu entry + } elsif (/^\s*(---)?help(---)?\s*$/ || /^(comment|choice|menu)\b/) { + $state = "NONE"; + } + } + close($kinfile); +} + +if ($kconfig) { + read_kconfig($kconfig); +} + +# Makefiles can use variables to define their dependencies +sub convert_vars { + my ($line, %vars) = @_; + + my $process = ""; + + while ($line =~ s/^(.*?)(\$\((.*?)\))//) { + my $start = $1; + my $variable = $2; + my $var = $3; + + if (defined($vars{$var})) { + $process .= $start . $vars{$var}; + } else { + $process .= $start . $variable; + } + } + + $process .= $line; + + return $process; +} + +# Read all Makefiles to map the configs to the objects +foreach my $makefile (@makefiles) { + + my $line = ""; + my %make_vars; + + open(my $infile, '<', $makefile) || die "Can't open $makefile"; + while (<$infile>) { + # if this line ends with a backslash, continue + chomp; + if (/^(.*)\\$/) { + $line .= $1; + next; + } + + $line .= $_; + $_ = $line; + $line = ""; + + my $objs; + + # Convert variables in a line (could define configs) + $_ = convert_vars($_, %make_vars); + + # collect objects after obj-$(CONFIG_FOO_BAR) + if (/obj-\$\((CONFIG_[^\)]*)\)\s*[+:]?=\s*(.*)/) { + $var = $1; + $objs = $2; + + # check if variables are set + } elsif (/^\s*(\S+)\s*[:]?=\s*(.*\S)/) { + $make_vars{$1} = $2; + } + if (defined($objs)) { + foreach my $obj (split /\s+/,$objs) { + $obj =~ s/-/_/g; + if ($obj =~ /(.*)\.o$/) { + # Objects may be enabled by more than one config. + # Store configs in an array. + my @arr; + + if (defined($objects{$1})) { + @arr = @{$objects{$1}}; + } + + $arr[$#arr+1] = $var; + + # The objects have a hash mapping to a reference + # of an array of configs. + $objects{$1} = \@arr; + } + } + } + } + close($infile); +} + +my %modules; +my $linfile; + +if (defined($lsmod_file)) { + if ( ! -f $lsmod_file) { + if ( -f $ENV{'objtree'}."/".$lsmod_file) { + $lsmod_file = $ENV{'objtree'}."/".$lsmod_file; + } else { + die "$lsmod_file not found"; + } + } + + my $otype = ( -x $lsmod_file) ? '-|' : '<'; + open($linfile, $otype, $lsmod_file); + +} else { + + # see what modules are loaded on this system + my $lsmod; + + foreach my $dir ( ("/sbin", "/bin", "/usr/sbin", "/usr/bin") ) { + if ( -x "$dir/lsmod" ) { + $lsmod = "$dir/lsmod"; + last; + } + } + if (!defined($lsmod)) { + # try just the path + $lsmod = "lsmod"; + } + + open($linfile, '-|', $lsmod) || die "Can not call lsmod with $lsmod"; +} + +while (<$linfile>) { + next if (/^Module/); # Skip the first line. + if (/^(\S+)/) { + $modules{$1} = 1; + } +} +close ($linfile); + +# add to the configs hash all configs that are needed to enable +# a loaded module. This is a direct obj-${CONFIG_FOO} += bar.o +# where we know we need bar.o so we add FOO to the list. +my %configs; +foreach my $module (keys(%modules)) { + if (defined($objects{$module})) { + my @arr = @{$objects{$module}}; + foreach my $conf (@arr) { + $configs{$conf} = $module; + dprint "$conf added by direct ($module)\n"; + if ($debugprint) { + my $c=$conf; + $c =~ s/^CONFIG_//; + if (defined($depends{$c})) { + dprint " deps = $depends{$c}\n"; + } else { + dprint " no deps\n"; + } + } + } + } else { + # Most likely, someone has a custom (binary?) module loaded. + print STDERR "$module config not found!!\n"; + } +} + +# Read the current config, and see what is enabled. We want to +# ignore configs that we would not enable anyway. + +my %orig_configs; +my $valid = "A-Za-z_0-9"; + +foreach my $line (@config_file) { + $_ = $line; + + if (/(CONFIG_[$valid]*)=(m|y)/) { + $orig_configs{$1} = $2; + } +} + +my $repeat = 1; + +my $depconfig; + +# +# Note, we do not care about operands (like: &&, ||, !) we want to add any +# config that is in the depend list of another config. This script does +# not enable configs that are not already enabled. If we come across a +# config A that depends on !B, we can still add B to the list of depends +# to keep on. If A was on in the original config, B would not have been +# and B would not be turned on by this script. +# +sub parse_config_depends +{ + my ($p) = @_; + + while ($p =~ /[$valid]/) { + + if ($p =~ /^[^$valid]*([$valid]+)/) { + my $conf = "CONFIG_" . $1; + + $p =~ s/^[^$valid]*[$valid]+//; + + # We only need to process if the depend config is a module + if (!defined($orig_configs{$conf}) || $orig_configs{$conf} eq "y") { + next; + } + + if (!defined($configs{$conf})) { + # We must make sure that this config has its + # dependencies met. + $repeat = 1; # do again + dprint "$conf selected by depend $depconfig\n"; + $configs{$conf} = 1; + } + } else { + die "this should never happen"; + } + } +} + +# Select is treated a bit differently than depends. We call this +# when a config has no prompt and requires another config to be +# selected. We use to just select all configs that selected this +# config, but found that that can balloon into enabling hundreds +# of configs that we do not care about. +# +# The idea is we look at all the configs that select it. If one +# is already in our list of configs to enable, then there's nothing +# else to do. If there isn't, we pick the first config that was +# enabled in the orignal config and use that. +sub parse_config_selects +{ + my ($config, $p) = @_; + + my $next_config; + + while ($p =~ /[$valid]/) { + + if ($p =~ /^[^$valid]*([$valid]+)/) { + my $conf = "CONFIG_" . $1; + + $p =~ s/^[^$valid]*[$valid]+//; + + # Make sure that this config exists in the current .config file + if (!defined($orig_configs{$conf})) { + dprint "$conf not set for $config select\n"; + next; + } + + # Check if something other than a module selects this config + if (defined($orig_configs{$conf}) && $orig_configs{$conf} ne "m") { + dprint "$conf (non module) selects config, we are good\n"; + # we are good with this + return; + } + if (defined($configs{$conf})) { + dprint "$conf selects $config so we are good\n"; + # A set config selects this config, we are good + return; + } + # Set this config to be selected + if (!defined($next_config)) { + $next_config = $conf; + } + } else { + die "this should never happen"; + } + } + + # If no possible config selected this, then something happened. + if (!defined($next_config)) { + print STDERR "WARNING: $config is required, but nothing in the\n"; + print STDERR " current config selects it.\n"; + return; + } + + # If we are here, then we found no config that is set and + # selects this config. Repeat. + $repeat = 1; + # Make this config need to be selected + $configs{$next_config} = 1; + dprint "$next_config selected by select $config\n"; +} + +my %process_selects; + +# loop through all configs, select their dependencies. +sub loop_depend { + $repeat = 1; + + while ($repeat) { + $repeat = 0; + + forloop: + foreach my $config (keys %configs) { + + # If this config is not a module, we do not need to process it + if (defined($orig_configs{$config}) && $orig_configs{$config} ne "m") { + next forloop; + } + + $config =~ s/^CONFIG_//; + $depconfig = $config; + + if (defined($depends{$config})) { + # This config has dependencies. Make sure they are also included + parse_config_depends $depends{$config}; + } + + # If the config has no prompt, then we need to check if a config + # that is enabled selected it. Or if we need to enable one. + if (!defined($prompts{$config}) && defined($selects{$config})) { + $process_selects{$config} = 1; + } + } + } +} + +sub loop_select { + + foreach my $config (keys %process_selects) { + $config =~ s/^CONFIG_//; + + dprint "Process select $config\n"; + + # config has no prompt and must be selected. + parse_config_selects $config, $selects{$config}; + } +} + +while ($repeat) { + # Get the first set of configs and their dependencies. + loop_depend; + + $repeat = 0; + + # Now we need to see if we have to check selects; + loop_select; +} + +my %setconfigs; +my @preserved_kconfigs; +if (defined($ENV{'LMC_KEEP'})) { + @preserved_kconfigs = split(/:/,$ENV{LMC_KEEP}); +} + +sub in_preserved_kconfigs { + my $kconfig = $config2kfile{$_[0]}; + if (!defined($kconfig)) { + return 0; + } + foreach my $excl (@preserved_kconfigs) { + if($kconfig =~ /^$excl/) { + return 1; + } + } + return 0; +} + +# Finally, read the .config file and turn off any module enabled that +# we could not find a reason to keep enabled. +foreach my $line (@config_file) { + $_ = $line; + + if (/CONFIG_IKCONFIG/) { + if (/# CONFIG_IKCONFIG is not set/) { + # enable IKCONFIG at least as a module + print "CONFIG_IKCONFIG=m\n"; + # don't ask about PROC + print "# CONFIG_IKCONFIG_PROC is not set\n"; + } else { + print; + } + next; + } + + if (/CONFIG_MODULE_SIG_KEY="(.+)"/) { + my $orig_cert = $1; + my $default_cert = "certs/signing_key.pem"; + + # Check that the logic in this script still matches the one in Kconfig + if (!defined($depends{"MODULE_SIG_KEY"}) || + $depends{"MODULE_SIG_KEY"} !~ /"\Q$default_cert\E"/) { + print STDERR "WARNING: MODULE_SIG_KEY assertion failure, ", + "update needed to ", __FILE__, " line ", __LINE__, "\n"; + print; + } elsif ($orig_cert ne $default_cert && ! -f $orig_cert) { + print STDERR "Module signature verification enabled but ", + "module signing key \"$orig_cert\" not found. Resetting ", + "signing key to default value.\n"; + print "CONFIG_MODULE_SIG_KEY=\"$default_cert\"\n"; + } else { + print; + } + next; + } + + if (/CONFIG_SYSTEM_TRUSTED_KEYS="(.+)"/) { + my $orig_keys = $1; + + if (! -f $orig_keys) { + print STDERR "System keyring enabled but keys \"$orig_keys\" ", + "not found. Resetting keys to default value.\n"; + print "CONFIG_SYSTEM_TRUSTED_KEYS=\"\"\n"; + } else { + print; + } + next; + } + + if (/^(CONFIG.*)=(m|y)/) { + if (in_preserved_kconfigs($1)) { + dprint "Preserve config $1"; + print; + next; + } + if (defined($configs{$1})) { + if ($localyesconfig) { + $setconfigs{$1} = 'y'; + print "$1=y\n"; + next; + } else { + $setconfigs{$1} = $2; + } + } elsif ($2 eq "m") { + print "# $1 is not set\n"; + next; + } + } + print; +} + +# Integrity check, make sure all modules that we want enabled do +# indeed have their configs set. +loop: +foreach my $module (keys(%modules)) { + if (defined($objects{$module})) { + my @arr = @{$objects{$module}}; + foreach my $conf (@arr) { + if (defined($setconfigs{$conf})) { + next loop; + } + } + print STDERR "module $module did not have configs"; + foreach my $conf (@arr) { + print STDERR " " , $conf; + } + print STDERR "\n"; + } +} diff --git a/src/net/scripts/kconfig/symbol.c b/src/net/scripts/kconfig/symbol.c new file mode 100644 index 0000000..ffa3ec6 --- /dev/null +++ b/src/net/scripts/kconfig/symbol.c @@ -0,0 +1,1314 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2002 Roman Zippel <zippel@linux-m68k.org> + */ + +#include <ctype.h> +#include <stdlib.h> +#include <string.h> +#include <regex.h> +#include <sys/utsname.h> + +#include "lkc.h" + +struct symbol symbol_yes = { + .name = "y", + .curr = { "y", yes }, + .flags = SYMBOL_CONST|SYMBOL_VALID, +}; + +struct symbol symbol_mod = { + .name = "m", + .curr = { "m", mod }, + .flags = SYMBOL_CONST|SYMBOL_VALID, +}; + +struct symbol symbol_no = { + .name = "n", + .curr = { "n", no }, + .flags = SYMBOL_CONST|SYMBOL_VALID, +}; + +static struct symbol symbol_empty = { + .name = "", + .curr = { "", no }, + .flags = SYMBOL_VALID, +}; + +struct symbol *sym_defconfig_list; +struct symbol *modules_sym; +static tristate modules_val; + +enum symbol_type sym_get_type(struct symbol *sym) +{ + enum symbol_type type = sym->type; + + if (type == S_TRISTATE) { + if (sym_is_choice_value(sym) && sym->visible == yes) + type = S_BOOLEAN; + else if (modules_val == no) + type = S_BOOLEAN; + } + return type; +} + +const char *sym_type_name(enum symbol_type type) +{ + switch (type) { + case S_BOOLEAN: + return "bool"; + case S_TRISTATE: + return "tristate"; + case S_INT: + return "integer"; + case S_HEX: + return "hex"; + case S_STRING: + return "string"; + case S_UNKNOWN: + return "unknown"; + } + return "???"; +} + +struct property *sym_get_choice_prop(struct symbol *sym) +{ + struct property *prop; + + for_all_choices(sym, prop) + return prop; + return NULL; +} + +static struct property *sym_get_default_prop(struct symbol *sym) +{ + struct property *prop; + + for_all_defaults(sym, prop) { + prop->visible.tri = expr_calc_value(prop->visible.expr); + if (prop->visible.tri != no) + return prop; + } + return NULL; +} + +struct property *sym_get_range_prop(struct symbol *sym) +{ + struct property *prop; + + for_all_properties(sym, prop, P_RANGE) { + prop->visible.tri = expr_calc_value(prop->visible.expr); + if (prop->visible.tri != no) + return prop; + } + return NULL; +} + +static long long sym_get_range_val(struct symbol *sym, int base) +{ + sym_calc_value(sym); + switch (sym->type) { + case S_INT: + base = 10; + break; + case S_HEX: + base = 16; + break; + default: + break; + } + return strtoll(sym->curr.val, NULL, base); +} + +static void sym_validate_range(struct symbol *sym) +{ + struct property *prop; + int base; + long long val, val2; + char str[64]; + + switch (sym->type) { + case S_INT: + base = 10; + break; + case S_HEX: + base = 16; + break; + default: + return; + } + prop = sym_get_range_prop(sym); + if (!prop) + return; + val = strtoll(sym->curr.val, NULL, base); + val2 = sym_get_range_val(prop->expr->left.sym, base); + if (val >= val2) { + val2 = sym_get_range_val(prop->expr->right.sym, base); + if (val <= val2) + return; + } + if (sym->type == S_INT) + sprintf(str, "%lld", val2); + else + sprintf(str, "0x%llx", val2); + sym->curr.val = xstrdup(str); +} + +static void sym_set_changed(struct symbol *sym) +{ + struct property *prop; + + sym->flags |= SYMBOL_CHANGED; + for (prop = sym->prop; prop; prop = prop->next) { + if (prop->menu) + prop->menu->flags |= MENU_CHANGED; + } +} + +static void sym_set_all_changed(void) +{ + struct symbol *sym; + int i; + + for_all_symbols(i, sym) + sym_set_changed(sym); +} + +static void sym_calc_visibility(struct symbol *sym) +{ + struct property *prop; + struct symbol *choice_sym = NULL; + tristate tri; + + /* any prompt visible? */ + tri = no; + + if (sym_is_choice_value(sym)) + choice_sym = prop_get_symbol(sym_get_choice_prop(sym)); + + for_all_prompts(sym, prop) { + prop->visible.tri = expr_calc_value(prop->visible.expr); + /* + * Tristate choice_values with visibility 'mod' are + * not visible if the corresponding choice's value is + * 'yes'. + */ + if (choice_sym && sym->type == S_TRISTATE && + prop->visible.tri == mod && choice_sym->curr.tri == yes) + prop->visible.tri = no; + + tri = EXPR_OR(tri, prop->visible.tri); + } + if (tri == mod && (sym->type != S_TRISTATE || modules_val == no)) + tri = yes; + if (sym->visible != tri) { + sym->visible = tri; + sym_set_changed(sym); + } + if (sym_is_choice_value(sym)) + return; + /* defaulting to "yes" if no explicit "depends on" are given */ + tri = yes; + if (sym->dir_dep.expr) + tri = expr_calc_value(sym->dir_dep.expr); + if (tri == mod && sym_get_type(sym) == S_BOOLEAN) + tri = yes; + if (sym->dir_dep.tri != tri) { + sym->dir_dep.tri = tri; + sym_set_changed(sym); + } + tri = no; + if (sym->rev_dep.expr) + tri = expr_calc_value(sym->rev_dep.expr); + if (tri == mod && sym_get_type(sym) == S_BOOLEAN) + tri = yes; + if (sym->rev_dep.tri != tri) { + sym->rev_dep.tri = tri; + sym_set_changed(sym); + } + tri = no; + if (sym->implied.expr) + tri = expr_calc_value(sym->implied.expr); + if (tri == mod && sym_get_type(sym) == S_BOOLEAN) + tri = yes; + if (sym->implied.tri != tri) { + sym->implied.tri = tri; + sym_set_changed(sym); + } +} + +/* + * Find the default symbol for a choice. + * First try the default values for the choice symbol + * Next locate the first visible choice value + * Return NULL if none was found + */ +struct symbol *sym_choice_default(struct symbol *sym) +{ + struct symbol *def_sym; + struct property *prop; + struct expr *e; + + /* any of the defaults visible? */ + for_all_defaults(sym, prop) { + prop->visible.tri = expr_calc_value(prop->visible.expr); + if (prop->visible.tri == no) + continue; + def_sym = prop_get_symbol(prop); + if (def_sym->visible != no) + return def_sym; + } + + /* just get the first visible value */ + prop = sym_get_choice_prop(sym); + expr_list_for_each_sym(prop->expr, e, def_sym) + if (def_sym->visible != no) + return def_sym; + + /* failed to locate any defaults */ + return NULL; +} + +static struct symbol *sym_calc_choice(struct symbol *sym) +{ + struct symbol *def_sym; + struct property *prop; + struct expr *e; + int flags; + + /* first calculate all choice values' visibilities */ + flags = sym->flags; + prop = sym_get_choice_prop(sym); + expr_list_for_each_sym(prop->expr, e, def_sym) { + sym_calc_visibility(def_sym); + if (def_sym->visible != no) + flags &= def_sym->flags; + } + + sym->flags &= flags | ~SYMBOL_DEF_USER; + + /* is the user choice visible? */ + def_sym = sym->def[S_DEF_USER].val; + if (def_sym && def_sym->visible != no) + return def_sym; + + def_sym = sym_choice_default(sym); + + if (def_sym == NULL) + /* no choice? reset tristate value */ + sym->curr.tri = no; + + return def_sym; +} + +static void sym_warn_unmet_dep(struct symbol *sym) +{ + struct gstr gs = str_new(); + + str_printf(&gs, + "\nWARNING: unmet direct dependencies detected for %s\n", + sym->name); + str_printf(&gs, + " Depends on [%c]: ", + sym->dir_dep.tri == mod ? 'm' : 'n'); + expr_gstr_print(sym->dir_dep.expr, &gs); + str_printf(&gs, "\n"); + + expr_gstr_print_revdep(sym->rev_dep.expr, &gs, yes, + " Selected by [y]:\n"); + expr_gstr_print_revdep(sym->rev_dep.expr, &gs, mod, + " Selected by [m]:\n"); + + fputs(str_get(&gs), stderr); +} + +void sym_calc_value(struct symbol *sym) +{ + struct symbol_value newval, oldval; + struct property *prop; + struct expr *e; + + if (!sym) + return; + + if (sym->flags & SYMBOL_VALID) + return; + + if (sym_is_choice_value(sym) && + sym->flags & SYMBOL_NEED_SET_CHOICE_VALUES) { + sym->flags &= ~SYMBOL_NEED_SET_CHOICE_VALUES; + prop = sym_get_choice_prop(sym); + sym_calc_value(prop_get_symbol(prop)); + } + + sym->flags |= SYMBOL_VALID; + + oldval = sym->curr; + + switch (sym->type) { + case S_INT: + case S_HEX: + case S_STRING: + newval = symbol_empty.curr; + break; + case S_BOOLEAN: + case S_TRISTATE: + newval = symbol_no.curr; + break; + default: + sym->curr.val = sym->name; + sym->curr.tri = no; + return; + } + sym->flags &= ~SYMBOL_WRITE; + + sym_calc_visibility(sym); + + if (sym->visible != no) + sym->flags |= SYMBOL_WRITE; + + /* set default if recursively called */ + sym->curr = newval; + + switch (sym_get_type(sym)) { + case S_BOOLEAN: + case S_TRISTATE: + if (sym_is_choice_value(sym) && sym->visible == yes) { + prop = sym_get_choice_prop(sym); + newval.tri = (prop_get_symbol(prop)->curr.val == sym) ? yes : no; + } else { + if (sym->visible != no) { + /* if the symbol is visible use the user value + * if available, otherwise try the default value + */ + if (sym_has_value(sym)) { + newval.tri = EXPR_AND(sym->def[S_DEF_USER].tri, + sym->visible); + goto calc_newval; + } + } + if (sym->rev_dep.tri != no) + sym->flags |= SYMBOL_WRITE; + if (!sym_is_choice(sym)) { + prop = sym_get_default_prop(sym); + if (prop) { + newval.tri = EXPR_AND(expr_calc_value(prop->expr), + prop->visible.tri); + if (newval.tri != no) + sym->flags |= SYMBOL_WRITE; + } + if (sym->implied.tri != no) { + sym->flags |= SYMBOL_WRITE; + newval.tri = EXPR_OR(newval.tri, sym->implied.tri); + newval.tri = EXPR_AND(newval.tri, + sym->dir_dep.tri); + } + } + calc_newval: + if (sym->dir_dep.tri < sym->rev_dep.tri) + sym_warn_unmet_dep(sym); + newval.tri = EXPR_OR(newval.tri, sym->rev_dep.tri); + } + if (newval.tri == mod && sym_get_type(sym) == S_BOOLEAN) + newval.tri = yes; + break; + case S_STRING: + case S_HEX: + case S_INT: + if (sym->visible != no && sym_has_value(sym)) { + newval.val = sym->def[S_DEF_USER].val; + break; + } + prop = sym_get_default_prop(sym); + if (prop) { + struct symbol *ds = prop_get_symbol(prop); + if (ds) { + sym->flags |= SYMBOL_WRITE; + sym_calc_value(ds); + newval.val = ds->curr.val; + } + } + break; + default: + ; + } + + sym->curr = newval; + if (sym_is_choice(sym) && newval.tri == yes) + sym->curr.val = sym_calc_choice(sym); + sym_validate_range(sym); + + if (memcmp(&oldval, &sym->curr, sizeof(oldval))) { + sym_set_changed(sym); + if (modules_sym == sym) { + sym_set_all_changed(); + modules_val = modules_sym->curr.tri; + } + } + + if (sym_is_choice(sym)) { + struct symbol *choice_sym; + + prop = sym_get_choice_prop(sym); + expr_list_for_each_sym(prop->expr, e, choice_sym) { + if ((sym->flags & SYMBOL_WRITE) && + choice_sym->visible != no) + choice_sym->flags |= SYMBOL_WRITE; + if (sym->flags & SYMBOL_CHANGED) + sym_set_changed(choice_sym); + } + } + + if (sym->flags & SYMBOL_NO_WRITE) + sym->flags &= ~SYMBOL_WRITE; + + if (sym->flags & SYMBOL_NEED_SET_CHOICE_VALUES) + set_all_choice_values(sym); +} + +void sym_clear_all_valid(void) +{ + struct symbol *sym; + int i; + + for_all_symbols(i, sym) + sym->flags &= ~SYMBOL_VALID; + sym_add_change_count(1); + sym_calc_value(modules_sym); +} + +bool sym_tristate_within_range(struct symbol *sym, tristate val) +{ + int type = sym_get_type(sym); + + if (sym->visible == no) + return false; + + if (type != S_BOOLEAN && type != S_TRISTATE) + return false; + + if (type == S_BOOLEAN && val == mod) + return false; + if (sym->visible <= sym->rev_dep.tri) + return false; + if (sym_is_choice_value(sym) && sym->visible == yes) + return val == yes; + return val >= sym->rev_dep.tri && val <= sym->visible; +} + +bool sym_set_tristate_value(struct symbol *sym, tristate val) +{ + tristate oldval = sym_get_tristate_value(sym); + + if (oldval != val && !sym_tristate_within_range(sym, val)) + return false; + + if (!(sym->flags & SYMBOL_DEF_USER)) { + sym->flags |= SYMBOL_DEF_USER; + sym_set_changed(sym); + } + /* + * setting a choice value also resets the new flag of the choice + * symbol and all other choice values. + */ + if (sym_is_choice_value(sym) && val == yes) { + struct symbol *cs = prop_get_symbol(sym_get_choice_prop(sym)); + struct property *prop; + struct expr *e; + + cs->def[S_DEF_USER].val = sym; + cs->flags |= SYMBOL_DEF_USER; + prop = sym_get_choice_prop(cs); + for (e = prop->expr; e; e = e->left.expr) { + if (e->right.sym->visible != no) + e->right.sym->flags |= SYMBOL_DEF_USER; + } + } + + sym->def[S_DEF_USER].tri = val; + if (oldval != val) + sym_clear_all_valid(); + + return true; +} + +tristate sym_toggle_tristate_value(struct symbol *sym) +{ + tristate oldval, newval; + + oldval = newval = sym_get_tristate_value(sym); + do { + switch (newval) { + case no: + newval = mod; + break; + case mod: + newval = yes; + break; + case yes: + newval = no; + break; + } + if (sym_set_tristate_value(sym, newval)) + break; + } while (oldval != newval); + return newval; +} + +bool sym_string_valid(struct symbol *sym, const char *str) +{ + signed char ch; + + switch (sym->type) { + case S_STRING: + return true; + case S_INT: + ch = *str++; + if (ch == '-') + ch = *str++; + if (!isdigit(ch)) + return false; + if (ch == '0' && *str != 0) + return false; + while ((ch = *str++)) { + if (!isdigit(ch)) + return false; + } + return true; + case S_HEX: + if (str[0] == '0' && (str[1] == 'x' || str[1] == 'X')) + str += 2; + ch = *str++; + do { + if (!isxdigit(ch)) + return false; + } while ((ch = *str++)); + return true; + case S_BOOLEAN: + case S_TRISTATE: + switch (str[0]) { + case 'y': case 'Y': + case 'm': case 'M': + case 'n': case 'N': + return true; + } + return false; + default: + return false; + } +} + +bool sym_string_within_range(struct symbol *sym, const char *str) +{ + struct property *prop; + long long val; + + switch (sym->type) { + case S_STRING: + return sym_string_valid(sym, str); + case S_INT: + if (!sym_string_valid(sym, str)) + return false; + prop = sym_get_range_prop(sym); + if (!prop) + return true; + val = strtoll(str, NULL, 10); + return val >= sym_get_range_val(prop->expr->left.sym, 10) && + val <= sym_get_range_val(prop->expr->right.sym, 10); + case S_HEX: + if (!sym_string_valid(sym, str)) + return false; + prop = sym_get_range_prop(sym); + if (!prop) + return true; + val = strtoll(str, NULL, 16); + return val >= sym_get_range_val(prop->expr->left.sym, 16) && + val <= sym_get_range_val(prop->expr->right.sym, 16); + case S_BOOLEAN: + case S_TRISTATE: + switch (str[0]) { + case 'y': case 'Y': + return sym_tristate_within_range(sym, yes); + case 'm': case 'M': + return sym_tristate_within_range(sym, mod); + case 'n': case 'N': + return sym_tristate_within_range(sym, no); + } + return false; + default: + return false; + } +} + +bool sym_set_string_value(struct symbol *sym, const char *newval) +{ + const char *oldval; + char *val; + int size; + + switch (sym->type) { + case S_BOOLEAN: + case S_TRISTATE: + switch (newval[0]) { + case 'y': case 'Y': + return sym_set_tristate_value(sym, yes); + case 'm': case 'M': + return sym_set_tristate_value(sym, mod); + case 'n': case 'N': + return sym_set_tristate_value(sym, no); + } + return false; + default: + ; + } + + if (!sym_string_within_range(sym, newval)) + return false; + + if (!(sym->flags & SYMBOL_DEF_USER)) { + sym->flags |= SYMBOL_DEF_USER; + sym_set_changed(sym); + } + + oldval = sym->def[S_DEF_USER].val; + size = strlen(newval) + 1; + if (sym->type == S_HEX && (newval[0] != '0' || (newval[1] != 'x' && newval[1] != 'X'))) { + size += 2; + sym->def[S_DEF_USER].val = val = xmalloc(size); + *val++ = '0'; + *val++ = 'x'; + } else if (!oldval || strcmp(oldval, newval)) + sym->def[S_DEF_USER].val = val = xmalloc(size); + else + return true; + + strcpy(val, newval); + free((void *)oldval); + sym_clear_all_valid(); + + return true; +} + +/* + * Find the default value associated to a symbol. + * For tristate symbol handle the modules=n case + * in which case "m" becomes "y". + * If the symbol does not have any default then fallback + * to the fixed default values. + */ +const char *sym_get_string_default(struct symbol *sym) +{ + struct property *prop; + struct symbol *ds; + const char *str; + tristate val; + + sym_calc_visibility(sym); + sym_calc_value(modules_sym); + val = symbol_no.curr.tri; + str = symbol_empty.curr.val; + + /* If symbol has a default value look it up */ + prop = sym_get_default_prop(sym); + if (prop != NULL) { + switch (sym->type) { + case S_BOOLEAN: + case S_TRISTATE: + /* The visibility may limit the value from yes => mod */ + val = EXPR_AND(expr_calc_value(prop->expr), prop->visible.tri); + break; + default: + /* + * The following fails to handle the situation + * where a default value is further limited by + * the valid range. + */ + ds = prop_get_symbol(prop); + if (ds != NULL) { + sym_calc_value(ds); + str = (const char *)ds->curr.val; + } + } + } + + /* Handle select statements */ + val = EXPR_OR(val, sym->rev_dep.tri); + + /* transpose mod to yes if modules are not enabled */ + if (val == mod) + if (!sym_is_choice_value(sym) && modules_sym->curr.tri == no) + val = yes; + + /* transpose mod to yes if type is bool */ + if (sym->type == S_BOOLEAN && val == mod) + val = yes; + + /* adjust the default value if this symbol is implied by another */ + if (val < sym->implied.tri) + val = sym->implied.tri; + + switch (sym->type) { + case S_BOOLEAN: + case S_TRISTATE: + switch (val) { + case no: return "n"; + case mod: return "m"; + case yes: return "y"; + } + case S_INT: + case S_HEX: + return str; + case S_STRING: + return str; + case S_UNKNOWN: + break; + } + return ""; +} + +const char *sym_get_string_value(struct symbol *sym) +{ + tristate val; + + switch (sym->type) { + case S_BOOLEAN: + case S_TRISTATE: + val = sym_get_tristate_value(sym); + switch (val) { + case no: + return "n"; + case mod: + sym_calc_value(modules_sym); + return (modules_sym->curr.tri == no) ? "n" : "m"; + case yes: + return "y"; + } + break; + default: + ; + } + return (const char *)sym->curr.val; +} + +bool sym_is_changeable(struct symbol *sym) +{ + return sym->visible > sym->rev_dep.tri; +} + +static unsigned strhash(const char *s) +{ + /* fnv32 hash */ + unsigned hash = 2166136261U; + for (; *s; s++) + hash = (hash ^ *s) * 0x01000193; + return hash; +} + +struct symbol *sym_lookup(const char *name, int flags) +{ + struct symbol *symbol; + char *new_name; + int hash; + + if (name) { + if (name[0] && !name[1]) { + switch (name[0]) { + case 'y': return &symbol_yes; + case 'm': return &symbol_mod; + case 'n': return &symbol_no; + } + } + hash = strhash(name) % SYMBOL_HASHSIZE; + + for (symbol = symbol_hash[hash]; symbol; symbol = symbol->next) { + if (symbol->name && + !strcmp(symbol->name, name) && + (flags ? symbol->flags & flags + : !(symbol->flags & (SYMBOL_CONST|SYMBOL_CHOICE)))) + return symbol; + } + new_name = xstrdup(name); + } else { + new_name = NULL; + hash = 0; + } + + symbol = xmalloc(sizeof(*symbol)); + memset(symbol, 0, sizeof(*symbol)); + symbol->name = new_name; + symbol->type = S_UNKNOWN; + symbol->flags = flags; + + symbol->next = symbol_hash[hash]; + symbol_hash[hash] = symbol; + + return symbol; +} + +struct symbol *sym_find(const char *name) +{ + struct symbol *symbol = NULL; + int hash = 0; + + if (!name) + return NULL; + + if (name[0] && !name[1]) { + switch (name[0]) { + case 'y': return &symbol_yes; + case 'm': return &symbol_mod; + case 'n': return &symbol_no; + } + } + hash = strhash(name) % SYMBOL_HASHSIZE; + + for (symbol = symbol_hash[hash]; symbol; symbol = symbol->next) { + if (symbol->name && + !strcmp(symbol->name, name) && + !(symbol->flags & SYMBOL_CONST)) + break; + } + + return symbol; +} + +const char *sym_escape_string_value(const char *in) +{ + const char *p; + size_t reslen; + char *res; + size_t l; + + reslen = strlen(in) + strlen("\"\"") + 1; + + p = in; + for (;;) { + l = strcspn(p, "\"\\"); + p += l; + + if (p[0] == '\0') + break; + + reslen++; + p++; + } + + res = xmalloc(reslen); + res[0] = '\0'; + + strcat(res, "\""); + + p = in; + for (;;) { + l = strcspn(p, "\"\\"); + strncat(res, p, l); + p += l; + + if (p[0] == '\0') + break; + + strcat(res, "\\"); + strncat(res, p++, 1); + } + + strcat(res, "\""); + return res; +} + +struct sym_match { + struct symbol *sym; + off_t so, eo; +}; + +/* Compare matched symbols as thus: + * - first, symbols that match exactly + * - then, alphabetical sort + */ +static int sym_rel_comp(const void *sym1, const void *sym2) +{ + const struct sym_match *s1 = sym1; + const struct sym_match *s2 = sym2; + int exact1, exact2; + + /* Exact match: + * - if matched length on symbol s1 is the length of that symbol, + * then this symbol should come first; + * - if matched length on symbol s2 is the length of that symbol, + * then this symbol should come first. + * Note: since the search can be a regexp, both symbols may match + * exactly; if this is the case, we can't decide which comes first, + * and we fallback to sorting alphabetically. + */ + exact1 = (s1->eo - s1->so) == strlen(s1->sym->name); + exact2 = (s2->eo - s2->so) == strlen(s2->sym->name); + if (exact1 && !exact2) + return -1; + if (!exact1 && exact2) + return 1; + + /* As a fallback, sort symbols alphabetically */ + return strcmp(s1->sym->name, s2->sym->name); +} + +struct symbol **sym_re_search(const char *pattern) +{ + struct symbol *sym, **sym_arr = NULL; + struct sym_match *sym_match_arr = NULL; + int i, cnt, size; + regex_t re; + regmatch_t match[1]; + + cnt = size = 0; + /* Skip if empty */ + if (strlen(pattern) == 0) + return NULL; + if (regcomp(&re, pattern, REG_EXTENDED|REG_ICASE)) + return NULL; + + for_all_symbols(i, sym) { + if (sym->flags & SYMBOL_CONST || !sym->name) + continue; + if (regexec(&re, sym->name, 1, match, 0)) + continue; + if (cnt >= size) { + void *tmp; + size += 16; + tmp = realloc(sym_match_arr, size * sizeof(struct sym_match)); + if (!tmp) + goto sym_re_search_free; + sym_match_arr = tmp; + } + sym_calc_value(sym); + /* As regexec returned 0, we know we have a match, so + * we can use match[0].rm_[se]o without further checks + */ + sym_match_arr[cnt].so = match[0].rm_so; + sym_match_arr[cnt].eo = match[0].rm_eo; + sym_match_arr[cnt++].sym = sym; + } + if (sym_match_arr) { + qsort(sym_match_arr, cnt, sizeof(struct sym_match), sym_rel_comp); + sym_arr = malloc((cnt+1) * sizeof(struct symbol *)); + if (!sym_arr) + goto sym_re_search_free; + for (i = 0; i < cnt; i++) + sym_arr[i] = sym_match_arr[i].sym; + sym_arr[cnt] = NULL; + } +sym_re_search_free: + /* sym_match_arr can be NULL if no match, but free(NULL) is OK */ + free(sym_match_arr); + regfree(&re); + + return sym_arr; +} + +/* + * When we check for recursive dependencies we use a stack to save + * current state so we can print out relevant info to user. + * The entries are located on the call stack so no need to free memory. + * Note insert() remove() must always match to properly clear the stack. + */ +static struct dep_stack { + struct dep_stack *prev, *next; + struct symbol *sym; + struct property *prop; + struct expr **expr; +} *check_top; + +static void dep_stack_insert(struct dep_stack *stack, struct symbol *sym) +{ + memset(stack, 0, sizeof(*stack)); + if (check_top) + check_top->next = stack; + stack->prev = check_top; + stack->sym = sym; + check_top = stack; +} + +static void dep_stack_remove(void) +{ + check_top = check_top->prev; + if (check_top) + check_top->next = NULL; +} + +/* + * Called when we have detected a recursive dependency. + * check_top point to the top of the stact so we use + * the ->prev pointer to locate the bottom of the stack. + */ +static void sym_check_print_recursive(struct symbol *last_sym) +{ + struct dep_stack *stack; + struct symbol *sym, *next_sym; + struct menu *menu = NULL; + struct property *prop; + struct dep_stack cv_stack; + + if (sym_is_choice_value(last_sym)) { + dep_stack_insert(&cv_stack, last_sym); + last_sym = prop_get_symbol(sym_get_choice_prop(last_sym)); + } + + for (stack = check_top; stack != NULL; stack = stack->prev) + if (stack->sym == last_sym) + break; + if (!stack) { + fprintf(stderr, "unexpected recursive dependency error\n"); + return; + } + + for (; stack; stack = stack->next) { + sym = stack->sym; + next_sym = stack->next ? stack->next->sym : last_sym; + prop = stack->prop; + if (prop == NULL) + prop = stack->sym->prop; + + /* for choice values find the menu entry (used below) */ + if (sym_is_choice(sym) || sym_is_choice_value(sym)) { + for (prop = sym->prop; prop; prop = prop->next) { + menu = prop->menu; + if (prop->menu) + break; + } + } + if (stack->sym == last_sym) + fprintf(stderr, "%s:%d:error: recursive dependency detected!\n", + prop->file->name, prop->lineno); + + if (sym_is_choice(sym)) { + fprintf(stderr, "%s:%d:\tchoice %s contains symbol %s\n", + menu->file->name, menu->lineno, + sym->name ? sym->name : "<choice>", + next_sym->name ? next_sym->name : "<choice>"); + } else if (sym_is_choice_value(sym)) { + fprintf(stderr, "%s:%d:\tsymbol %s is part of choice %s\n", + menu->file->name, menu->lineno, + sym->name ? sym->name : "<choice>", + next_sym->name ? next_sym->name : "<choice>"); + } else if (stack->expr == &sym->dir_dep.expr) { + fprintf(stderr, "%s:%d:\tsymbol %s depends on %s\n", + prop->file->name, prop->lineno, + sym->name ? sym->name : "<choice>", + next_sym->name ? next_sym->name : "<choice>"); + } else if (stack->expr == &sym->rev_dep.expr) { + fprintf(stderr, "%s:%d:\tsymbol %s is selected by %s\n", + prop->file->name, prop->lineno, + sym->name ? sym->name : "<choice>", + next_sym->name ? next_sym->name : "<choice>"); + } else if (stack->expr == &sym->implied.expr) { + fprintf(stderr, "%s:%d:\tsymbol %s is implied by %s\n", + prop->file->name, prop->lineno, + sym->name ? sym->name : "<choice>", + next_sym->name ? next_sym->name : "<choice>"); + } else if (stack->expr) { + fprintf(stderr, "%s:%d:\tsymbol %s %s value contains %s\n", + prop->file->name, prop->lineno, + sym->name ? sym->name : "<choice>", + prop_get_type_name(prop->type), + next_sym->name ? next_sym->name : "<choice>"); + } else { + fprintf(stderr, "%s:%d:\tsymbol %s %s is visible depending on %s\n", + prop->file->name, prop->lineno, + sym->name ? sym->name : "<choice>", + prop_get_type_name(prop->type), + next_sym->name ? next_sym->name : "<choice>"); + } + } + + fprintf(stderr, + "For a resolution refer to Documentation/kbuild/kconfig-language.rst\n" + "subsection \"Kconfig recursive dependency limitations\"\n" + "\n"); + + if (check_top == &cv_stack) + dep_stack_remove(); +} + +static struct symbol *sym_check_expr_deps(struct expr *e) +{ + struct symbol *sym; + + if (!e) + return NULL; + switch (e->type) { + case E_OR: + case E_AND: + sym = sym_check_expr_deps(e->left.expr); + if (sym) + return sym; + return sym_check_expr_deps(e->right.expr); + case E_NOT: + return sym_check_expr_deps(e->left.expr); + case E_EQUAL: + case E_GEQ: + case E_GTH: + case E_LEQ: + case E_LTH: + case E_UNEQUAL: + sym = sym_check_deps(e->left.sym); + if (sym) + return sym; + return sym_check_deps(e->right.sym); + case E_SYMBOL: + return sym_check_deps(e->left.sym); + default: + break; + } + fprintf(stderr, "Oops! How to check %d?\n", e->type); + return NULL; +} + +/* return NULL when dependencies are OK */ +static struct symbol *sym_check_sym_deps(struct symbol *sym) +{ + struct symbol *sym2; + struct property *prop; + struct dep_stack stack; + + dep_stack_insert(&stack, sym); + + stack.expr = &sym->dir_dep.expr; + sym2 = sym_check_expr_deps(sym->dir_dep.expr); + if (sym2) + goto out; + + stack.expr = &sym->rev_dep.expr; + sym2 = sym_check_expr_deps(sym->rev_dep.expr); + if (sym2) + goto out; + + stack.expr = &sym->implied.expr; + sym2 = sym_check_expr_deps(sym->implied.expr); + if (sym2) + goto out; + + stack.expr = NULL; + + for (prop = sym->prop; prop; prop = prop->next) { + if (prop->type == P_CHOICE || prop->type == P_SELECT || + prop->type == P_IMPLY) + continue; + stack.prop = prop; + sym2 = sym_check_expr_deps(prop->visible.expr); + if (sym2) + break; + if (prop->type != P_DEFAULT || sym_is_choice(sym)) + continue; + stack.expr = &prop->expr; + sym2 = sym_check_expr_deps(prop->expr); + if (sym2) + break; + stack.expr = NULL; + } + +out: + dep_stack_remove(); + + return sym2; +} + +static struct symbol *sym_check_choice_deps(struct symbol *choice) +{ + struct symbol *sym, *sym2; + struct property *prop; + struct expr *e; + struct dep_stack stack; + + dep_stack_insert(&stack, choice); + + prop = sym_get_choice_prop(choice); + expr_list_for_each_sym(prop->expr, e, sym) + sym->flags |= (SYMBOL_CHECK | SYMBOL_CHECKED); + + choice->flags |= (SYMBOL_CHECK | SYMBOL_CHECKED); + sym2 = sym_check_sym_deps(choice); + choice->flags &= ~SYMBOL_CHECK; + if (sym2) + goto out; + + expr_list_for_each_sym(prop->expr, e, sym) { + sym2 = sym_check_sym_deps(sym); + if (sym2) + break; + } +out: + expr_list_for_each_sym(prop->expr, e, sym) + sym->flags &= ~SYMBOL_CHECK; + + if (sym2 && sym_is_choice_value(sym2) && + prop_get_symbol(sym_get_choice_prop(sym2)) == choice) + sym2 = choice; + + dep_stack_remove(); + + return sym2; +} + +struct symbol *sym_check_deps(struct symbol *sym) +{ + struct symbol *sym2; + struct property *prop; + + if (sym->flags & SYMBOL_CHECK) { + sym_check_print_recursive(sym); + return sym; + } + if (sym->flags & SYMBOL_CHECKED) + return NULL; + + if (sym_is_choice_value(sym)) { + struct dep_stack stack; + + /* for choice groups start the check with main choice symbol */ + dep_stack_insert(&stack, sym); + prop = sym_get_choice_prop(sym); + sym2 = sym_check_deps(prop_get_symbol(prop)); + dep_stack_remove(); + } else if (sym_is_choice(sym)) { + sym2 = sym_check_choice_deps(sym); + } else { + sym->flags |= (SYMBOL_CHECK | SYMBOL_CHECKED); + sym2 = sym_check_sym_deps(sym); + sym->flags &= ~SYMBOL_CHECK; + } + + return sym2; +} + +struct symbol *prop_get_symbol(struct property *prop) +{ + if (prop->expr && (prop->expr->type == E_SYMBOL || + prop->expr->type == E_LIST)) + return prop->expr->left.sym; + return NULL; +} + +const char *prop_get_type_name(enum prop_type type) +{ + switch (type) { + case P_PROMPT: + return "prompt"; + case P_COMMENT: + return "comment"; + case P_MENU: + return "menu"; + case P_DEFAULT: + return "default"; + case P_CHOICE: + return "choice"; + case P_SELECT: + return "select"; + case P_IMPLY: + return "imply"; + case P_RANGE: + return "range"; + case P_SYMBOL: + return "symbol"; + case P_UNKNOWN: + break; + } + return "unknown"; +} diff --git a/src/net/scripts/kconfig/tests/auto_submenu/Kconfig b/src/net/scripts/kconfig/tests/auto_submenu/Kconfig new file mode 100644 index 0000000..b20761e --- /dev/null +++ b/src/net/scripts/kconfig/tests/auto_submenu/Kconfig @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: GPL-2.0 + +config A + bool "A" + default y + +config A0 + bool "A0" + depends on A + default y + help + This depends on A, so should be a submenu of A. + +config A0_0 + bool "A1_0" + depends on A0 + help + Submenus are created recursively. + This should be a submenu of A0. + +config A1 + bool "A1" + depends on A + default y + help + This should line up with A0. + +choice + prompt "choice" + depends on A1 + help + Choice should become a submenu as well. + +config A1_0 + bool "A1_0" + +config A1_1 + bool "A1_1" + +endchoice + +config B + bool "B" + help + This is independent of A. + +config C + bool "C" + depends on A + help + This depends on A, but not a consecutive item, so can/should not + be a submenu. diff --git a/src/net/scripts/kconfig/tests/auto_submenu/__init__.py b/src/net/scripts/kconfig/tests/auto_submenu/__init__.py new file mode 100644 index 0000000..25abd92 --- /dev/null +++ b/src/net/scripts/kconfig/tests/auto_submenu/__init__.py @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0 +""" +Create submenu for symbols that depend on the preceding one. + +If a symbols has dependency on the preceding symbol, the menu entry +should become the submenu of the preceding one, and displayed with +deeper indentation. +""" + + +def test(conf): + assert conf.oldaskconfig() == 0 + assert conf.stdout_contains('expected_stdout') diff --git a/src/net/scripts/kconfig/tests/auto_submenu/expected_stdout b/src/net/scripts/kconfig/tests/auto_submenu/expected_stdout new file mode 100644 index 0000000..bf5236f --- /dev/null +++ b/src/net/scripts/kconfig/tests/auto_submenu/expected_stdout @@ -0,0 +1,10 @@ +A (A) [Y/n/?] (NEW) + A0 (A0) [Y/n/?] (NEW) + A1_0 (A0_0) [N/y/?] (NEW) + A1 (A1) [Y/n/?] (NEW) + choice + > 1. A1_0 (A1_0) (NEW) + 2. A1_1 (A1_1) (NEW) + choice[1-2?]: +B (B) [N/y/?] (NEW) +C (C) [N/y/?] (NEW) diff --git a/src/net/scripts/kconfig/tests/choice/Kconfig b/src/net/scripts/kconfig/tests/choice/Kconfig new file mode 100644 index 0000000..a412205 --- /dev/null +++ b/src/net/scripts/kconfig/tests/choice/Kconfig @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: GPL-2.0 + +config MODULES + bool "Enable loadable module support" + option modules + default y + +choice + prompt "boolean choice" + default BOOL_CHOICE1 + +config BOOL_CHOICE0 + bool "choice 0" + +config BOOL_CHOICE1 + bool "choice 1" + +endchoice + +choice + prompt "optional boolean choice" + optional + default OPT_BOOL_CHOICE1 + +config OPT_BOOL_CHOICE0 + bool "choice 0" + +config OPT_BOOL_CHOICE1 + bool "choice 1" + +endchoice + +choice + prompt "tristate choice" + default TRI_CHOICE1 + +config TRI_CHOICE0 + tristate "choice 0" + +config TRI_CHOICE1 + tristate "choice 1" + +endchoice + +choice + prompt "optional tristate choice" + optional + default OPT_TRI_CHOICE1 + +config OPT_TRI_CHOICE0 + tristate "choice 0" + +config OPT_TRI_CHOICE1 + tristate "choice 1" + +endchoice diff --git a/src/net/scripts/kconfig/tests/choice/__init__.py b/src/net/scripts/kconfig/tests/choice/__init__.py new file mode 100644 index 0000000..4318fce --- /dev/null +++ b/src/net/scripts/kconfig/tests/choice/__init__.py @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: GPL-2.0 +""" +Basic choice tests. + +The handling of 'choice' is a bit complicated part in Kconfig. + +The behavior of 'y' choice is intuitive. If choice values are tristate, +the choice can be 'm' where each value can be enabled independently. +Also, if a choice is marked as 'optional', the whole choice can be +invisible. +""" + + +def test_oldask0(conf): + assert conf.oldaskconfig() == 0 + assert conf.stdout_contains('oldask0_expected_stdout') + + +def test_oldask1(conf): + assert conf.oldaskconfig('oldask1_config') == 0 + assert conf.stdout_contains('oldask1_expected_stdout') + + +def test_allyes(conf): + assert conf.allyesconfig() == 0 + assert conf.config_contains('allyes_expected_config') + + +def test_allmod(conf): + assert conf.allmodconfig() == 0 + assert conf.config_contains('allmod_expected_config') + + +def test_allno(conf): + assert conf.allnoconfig() == 0 + assert conf.config_contains('allno_expected_config') + + +def test_alldef(conf): + assert conf.alldefconfig() == 0 + assert conf.config_contains('alldef_expected_config') diff --git a/src/net/scripts/kconfig/tests/choice/alldef_expected_config b/src/net/scripts/kconfig/tests/choice/alldef_expected_config new file mode 100644 index 0000000..7a754bf --- /dev/null +++ b/src/net/scripts/kconfig/tests/choice/alldef_expected_config @@ -0,0 +1,5 @@ +CONFIG_MODULES=y +# CONFIG_BOOL_CHOICE0 is not set +CONFIG_BOOL_CHOICE1=y +# CONFIG_TRI_CHOICE0 is not set +# CONFIG_TRI_CHOICE1 is not set diff --git a/src/net/scripts/kconfig/tests/choice/allmod_expected_config b/src/net/scripts/kconfig/tests/choice/allmod_expected_config new file mode 100644 index 0000000..f1f5dcd --- /dev/null +++ b/src/net/scripts/kconfig/tests/choice/allmod_expected_config @@ -0,0 +1,9 @@ +CONFIG_MODULES=y +# CONFIG_BOOL_CHOICE0 is not set +CONFIG_BOOL_CHOICE1=y +# CONFIG_OPT_BOOL_CHOICE0 is not set +CONFIG_OPT_BOOL_CHOICE1=y +CONFIG_TRI_CHOICE0=m +CONFIG_TRI_CHOICE1=m +CONFIG_OPT_TRI_CHOICE0=m +CONFIG_OPT_TRI_CHOICE1=m diff --git a/src/net/scripts/kconfig/tests/choice/allno_expected_config b/src/net/scripts/kconfig/tests/choice/allno_expected_config new file mode 100644 index 0000000..b88ee7a --- /dev/null +++ b/src/net/scripts/kconfig/tests/choice/allno_expected_config @@ -0,0 +1,5 @@ +# CONFIG_MODULES is not set +# CONFIG_BOOL_CHOICE0 is not set +CONFIG_BOOL_CHOICE1=y +# CONFIG_TRI_CHOICE0 is not set +CONFIG_TRI_CHOICE1=y diff --git a/src/net/scripts/kconfig/tests/choice/allyes_expected_config b/src/net/scripts/kconfig/tests/choice/allyes_expected_config new file mode 100644 index 0000000..e5a062a --- /dev/null +++ b/src/net/scripts/kconfig/tests/choice/allyes_expected_config @@ -0,0 +1,9 @@ +CONFIG_MODULES=y +# CONFIG_BOOL_CHOICE0 is not set +CONFIG_BOOL_CHOICE1=y +# CONFIG_OPT_BOOL_CHOICE0 is not set +CONFIG_OPT_BOOL_CHOICE1=y +# CONFIG_TRI_CHOICE0 is not set +CONFIG_TRI_CHOICE1=y +# CONFIG_OPT_TRI_CHOICE0 is not set +CONFIG_OPT_TRI_CHOICE1=y diff --git a/src/net/scripts/kconfig/tests/choice/oldask0_expected_stdout b/src/net/scripts/kconfig/tests/choice/oldask0_expected_stdout new file mode 100644 index 0000000..b251bba --- /dev/null +++ b/src/net/scripts/kconfig/tests/choice/oldask0_expected_stdout @@ -0,0 +1,10 @@ +Enable loadable module support (MODULES) [Y/n/?] (NEW) +boolean choice + 1. choice 0 (BOOL_CHOICE0) (NEW) +> 2. choice 1 (BOOL_CHOICE1) (NEW) +choice[1-2?]: +optional boolean choice [N/y/?] (NEW) +tristate choice [M/y/?] (NEW) + choice 0 (TRI_CHOICE0) [N/m/?] (NEW) + choice 1 (TRI_CHOICE1) [N/m/?] (NEW) +optional tristate choice [N/m/y/?] (NEW) diff --git a/src/net/scripts/kconfig/tests/choice/oldask1_config b/src/net/scripts/kconfig/tests/choice/oldask1_config new file mode 100644 index 0000000..b67bfe3 --- /dev/null +++ b/src/net/scripts/kconfig/tests/choice/oldask1_config @@ -0,0 +1,2 @@ +# CONFIG_MODULES is not set +CONFIG_OPT_BOOL_CHOICE0=y diff --git a/src/net/scripts/kconfig/tests/choice/oldask1_expected_stdout b/src/net/scripts/kconfig/tests/choice/oldask1_expected_stdout new file mode 100644 index 0000000..c2125e9 --- /dev/null +++ b/src/net/scripts/kconfig/tests/choice/oldask1_expected_stdout @@ -0,0 +1,15 @@ +Enable loadable module support (MODULES) [N/y/?] +boolean choice + 1. choice 0 (BOOL_CHOICE0) (NEW) +> 2. choice 1 (BOOL_CHOICE1) (NEW) +choice[1-2?]: +optional boolean choice [Y/n/?] (NEW) +optional boolean choice +> 1. choice 0 (OPT_BOOL_CHOICE0) + 2. choice 1 (OPT_BOOL_CHOICE1) (NEW) +choice[1-2?]: +tristate choice + 1. choice 0 (TRI_CHOICE0) (NEW) +> 2. choice 1 (TRI_CHOICE1) (NEW) +choice[1-2?]: +optional tristate choice [N/y/?] diff --git a/src/net/scripts/kconfig/tests/choice_value_with_m_dep/Kconfig b/src/net/scripts/kconfig/tests/choice_value_with_m_dep/Kconfig new file mode 100644 index 0000000..7106c26 --- /dev/null +++ b/src/net/scripts/kconfig/tests/choice_value_with_m_dep/Kconfig @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: GPL-2.0 + +config MODULES + def_bool y + option modules + +config DEP + tristate + default m + +choice + prompt "Tristate Choice" + +config CHOICE0 + tristate "Choice 0" + +config CHOICE1 + tristate "Choice 1" + depends on DEP + +endchoice diff --git a/src/net/scripts/kconfig/tests/choice_value_with_m_dep/__init__.py b/src/net/scripts/kconfig/tests/choice_value_with_m_dep/__init__.py new file mode 100644 index 0000000..075b4e0 --- /dev/null +++ b/src/net/scripts/kconfig/tests/choice_value_with_m_dep/__init__.py @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0 +""" +Hide tristate choice values with mod dependency in y choice. + +If tristate choice values depend on symbols set to 'm', they should be +hidden when the choice containing them is changed from 'm' to 'y' +(i.e. exclusive choice). + +Related Linux commit: fa64e5f6a35efd5e77d639125d973077ca506074 +""" + + +def test(conf): + assert conf.oldaskconfig('config', 'y') == 0 + assert conf.config_contains('expected_config') + assert conf.stdout_contains('expected_stdout') diff --git a/src/net/scripts/kconfig/tests/choice_value_with_m_dep/config b/src/net/scripts/kconfig/tests/choice_value_with_m_dep/config new file mode 100644 index 0000000..3a126b7 --- /dev/null +++ b/src/net/scripts/kconfig/tests/choice_value_with_m_dep/config @@ -0,0 +1,2 @@ +CONFIG_CHOICE0=m +CONFIG_CHOICE1=m diff --git a/src/net/scripts/kconfig/tests/choice_value_with_m_dep/expected_config b/src/net/scripts/kconfig/tests/choice_value_with_m_dep/expected_config new file mode 100644 index 0000000..4d07b44 --- /dev/null +++ b/src/net/scripts/kconfig/tests/choice_value_with_m_dep/expected_config @@ -0,0 +1,3 @@ +CONFIG_MODULES=y +CONFIG_DEP=m +CONFIG_CHOICE0=y diff --git a/src/net/scripts/kconfig/tests/choice_value_with_m_dep/expected_stdout b/src/net/scripts/kconfig/tests/choice_value_with_m_dep/expected_stdout new file mode 100644 index 0000000..2b50ab6 --- /dev/null +++ b/src/net/scripts/kconfig/tests/choice_value_with_m_dep/expected_stdout @@ -0,0 +1,4 @@ +Tristate Choice [M/y/?] y +Tristate Choice +> 1. Choice 0 (CHOICE0) +choice[1]: 1 diff --git a/src/net/scripts/kconfig/tests/conftest.py b/src/net/scripts/kconfig/tests/conftest.py new file mode 100644 index 0000000..0345ef6 --- /dev/null +++ b/src/net/scripts/kconfig/tests/conftest.py @@ -0,0 +1,291 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Copyright (C) 2018 Masahiro Yamada <yamada.masahiro@socionext.com> +# + +""" +Kconfig unit testing framework. + +This provides fixture functions commonly used from test files. +""" + +import os +import pytest +import shutil +import subprocess +import tempfile + +CONF_PATH = os.path.abspath(os.path.join('scripts', 'kconfig', 'conf')) + + +class Conf: + """Kconfig runner and result checker. + + This class provides methods to run text-based interface of Kconfig + (scripts/kconfig/conf) and retrieve the resulted configuration, + stdout, and stderr. It also provides methods to compare those + results with expectations. + """ + + def __init__(self, request): + """Create a new Conf instance. + + request: object to introspect the requesting test module + """ + # the directory of the test being run + self._test_dir = os.path.dirname(str(request.fspath)) + + # runners + def _run_conf(self, mode, dot_config=None, out_file='.config', + interactive=False, in_keys=None, extra_env={}): + """Run text-based Kconfig executable and save the result. + + mode: input mode option (--oldaskconfig, --defconfig=<file> etc.) + dot_config: .config file to use for configuration base + out_file: file name to contain the output config data + interactive: flag to specify the interactive mode + in_keys: key inputs for interactive modes + extra_env: additional environments + returncode: exit status of the Kconfig executable + """ + command = [CONF_PATH, mode, 'Kconfig'] + + # Override 'srctree' environment to make the test as the top directory + extra_env['srctree'] = self._test_dir + + # Run Kconfig in a temporary directory. + # This directory is automatically removed when done. + with tempfile.TemporaryDirectory() as temp_dir: + + # if .config is given, copy it to the working directory + if dot_config: + shutil.copyfile(os.path.join(self._test_dir, dot_config), + os.path.join(temp_dir, '.config')) + + ps = subprocess.Popen(command, + stdin=subprocess.PIPE, + stdout=subprocess.PIPE, + stderr=subprocess.PIPE, + cwd=temp_dir, + env=dict(os.environ, **extra_env)) + + # If input key sequence is given, feed it to stdin. + if in_keys: + ps.stdin.write(in_keys.encode('utf-8')) + + while ps.poll() is None: + # For interactive modes such as oldaskconfig, oldconfig, + # send 'Enter' key until the program finishes. + if interactive: + ps.stdin.write(b'\n') + + self.retcode = ps.returncode + self.stdout = ps.stdout.read().decode() + self.stderr = ps.stderr.read().decode() + + # Retrieve the resulted config data only when .config is supposed + # to exist. If the command fails, the .config does not exist. + # 'listnewconfig' does not produce .config in the first place. + if self.retcode == 0 and out_file: + with open(os.path.join(temp_dir, out_file)) as f: + self.config = f.read() + else: + self.config = None + + # Logging: + # Pytest captures the following information by default. In failure + # of tests, the captured log will be displayed. This will be useful to + # figure out what has happened. + + print("[command]\n{}\n".format(' '.join(command))) + + print("[retcode]\n{}\n".format(self.retcode)) + + print("[stdout]") + print(self.stdout) + + print("[stderr]") + print(self.stderr) + + if self.config is not None: + print("[output for '{}']".format(out_file)) + print(self.config) + + return self.retcode + + def oldaskconfig(self, dot_config=None, in_keys=None): + """Run oldaskconfig. + + dot_config: .config file to use for configuration base (optional) + in_key: key inputs (optional) + returncode: exit status of the Kconfig executable + """ + return self._run_conf('--oldaskconfig', dot_config=dot_config, + interactive=True, in_keys=in_keys) + + def oldconfig(self, dot_config=None, in_keys=None): + """Run oldconfig. + + dot_config: .config file to use for configuration base (optional) + in_key: key inputs (optional) + returncode: exit status of the Kconfig executable + """ + return self._run_conf('--oldconfig', dot_config=dot_config, + interactive=True, in_keys=in_keys) + + def olddefconfig(self, dot_config=None): + """Run olddefconfig. + + dot_config: .config file to use for configuration base (optional) + returncode: exit status of the Kconfig executable + """ + return self._run_conf('--olddefconfig', dot_config=dot_config) + + def defconfig(self, defconfig): + """Run defconfig. + + defconfig: defconfig file for input + returncode: exit status of the Kconfig executable + """ + defconfig_path = os.path.join(self._test_dir, defconfig) + return self._run_conf('--defconfig={}'.format(defconfig_path)) + + def _allconfig(self, mode, all_config): + if all_config: + all_config_path = os.path.join(self._test_dir, all_config) + extra_env = {'KCONFIG_ALLCONFIG': all_config_path} + else: + extra_env = {} + + return self._run_conf('--{}config'.format(mode), extra_env=extra_env) + + def allyesconfig(self, all_config=None): + """Run allyesconfig. + + all_config: fragment config file for KCONFIG_ALLCONFIG (optional) + returncode: exit status of the Kconfig executable + """ + return self._allconfig('allyes', all_config) + + def allmodconfig(self, all_config=None): + """Run allmodconfig. + + all_config: fragment config file for KCONFIG_ALLCONFIG (optional) + returncode: exit status of the Kconfig executable + """ + return self._allconfig('allmod', all_config) + + def allnoconfig(self, all_config=None): + """Run allnoconfig. + + all_config: fragment config file for KCONFIG_ALLCONFIG (optional) + returncode: exit status of the Kconfig executable + """ + return self._allconfig('allno', all_config) + + def alldefconfig(self, all_config=None): + """Run alldefconfig. + + all_config: fragment config file for KCONFIG_ALLCONFIG (optional) + returncode: exit status of the Kconfig executable + """ + return self._allconfig('alldef', all_config) + + def randconfig(self, all_config=None): + """Run randconfig. + + all_config: fragment config file for KCONFIG_ALLCONFIG (optional) + returncode: exit status of the Kconfig executable + """ + return self._allconfig('rand', all_config) + + def savedefconfig(self, dot_config): + """Run savedefconfig. + + dot_config: .config file for input + returncode: exit status of the Kconfig executable + """ + return self._run_conf('--savedefconfig', out_file='defconfig') + + def listnewconfig(self, dot_config=None): + """Run listnewconfig. + + dot_config: .config file to use for configuration base (optional) + returncode: exit status of the Kconfig executable + """ + return self._run_conf('--listnewconfig', dot_config=dot_config, + out_file=None) + + # checkers + def _read_and_compare(self, compare, expected): + """Compare the result with expectation. + + compare: function to compare the result with expectation + expected: file that contains the expected data + """ + with open(os.path.join(self._test_dir, expected)) as f: + expected_data = f.read() + return compare(self, expected_data) + + def _contains(self, attr, expected): + return self._read_and_compare( + lambda s, e: getattr(s, attr).find(e) >= 0, + expected) + + def _matches(self, attr, expected): + return self._read_and_compare(lambda s, e: getattr(s, attr) == e, + expected) + + def config_contains(self, expected): + """Check if resulted configuration contains expected data. + + expected: file that contains the expected data + returncode: True if result contains the expected data, False otherwise + """ + return self._contains('config', expected) + + def config_matches(self, expected): + """Check if resulted configuration exactly matches expected data. + + expected: file that contains the expected data + returncode: True if result matches the expected data, False otherwise + """ + return self._matches('config', expected) + + def stdout_contains(self, expected): + """Check if resulted stdout contains expected data. + + expected: file that contains the expected data + returncode: True if result contains the expected data, False otherwise + """ + return self._contains('stdout', expected) + + def stdout_matches(self, expected): + """Check if resulted stdout exactly matches expected data. + + expected: file that contains the expected data + returncode: True if result matches the expected data, False otherwise + """ + return self._matches('stdout', expected) + + def stderr_contains(self, expected): + """Check if resulted stderr contains expected data. + + expected: file that contains the expected data + returncode: True if result contains the expected data, False otherwise + """ + return self._contains('stderr', expected) + + def stderr_matches(self, expected): + """Check if resulted stderr exactly matches expected data. + + expected: file that contains the expected data + returncode: True if result matches the expected data, False otherwise + """ + return self._matches('stderr', expected) + + +@pytest.fixture(scope="module") +def conf(request): + """Create a Conf instance and provide it to test functions.""" + return Conf(request) diff --git a/src/net/scripts/kconfig/tests/err_recursive_dep/Kconfig b/src/net/scripts/kconfig/tests/err_recursive_dep/Kconfig new file mode 100644 index 0000000..ebdb3ff --- /dev/null +++ b/src/net/scripts/kconfig/tests/err_recursive_dep/Kconfig @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: GPL-2.0 + +# depends on itself + +config A + bool "A" + depends on A + +# select itself + +config B + bool + select B + +# depends on each other + +config C1 + bool "C1" + depends on C2 + +config C2 + bool "C2" + depends on C1 + +# depends on and select + +config D1 + bool "D1" + depends on D2 + select D2 + +config D2 + bool + +# depends on and imply + +config E1 + bool "E1" + depends on E2 + imply E2 + +config E2 + bool "E2" + +# property + +config F1 + bool "F1" + default F2 + +config F2 + bool "F2" + depends on F1 + +# menu + +menu "menu depending on its content" + depends on G + +config G + bool "G" + +endmenu diff --git a/src/net/scripts/kconfig/tests/err_recursive_dep/__init__.py b/src/net/scripts/kconfig/tests/err_recursive_dep/__init__.py new file mode 100644 index 0000000..5f3821b --- /dev/null +++ b/src/net/scripts/kconfig/tests/err_recursive_dep/__init__.py @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0 +""" +Detect recursive dependency error. + +Recursive dependency should be treated as an error. +""" + +def test(conf): + assert conf.oldaskconfig() == 1 + assert conf.stderr_contains('expected_stderr') diff --git a/src/net/scripts/kconfig/tests/err_recursive_dep/expected_stderr b/src/net/scripts/kconfig/tests/err_recursive_dep/expected_stderr new file mode 100644 index 0000000..c9f4abf --- /dev/null +++ b/src/net/scripts/kconfig/tests/err_recursive_dep/expected_stderr @@ -0,0 +1,38 @@ +Kconfig:11:error: recursive dependency detected! +Kconfig:11: symbol B is selected by B +For a resolution refer to Documentation/kbuild/kconfig-language.rst +subsection "Kconfig recursive dependency limitations" + +Kconfig:5:error: recursive dependency detected! +Kconfig:5: symbol A depends on A +For a resolution refer to Documentation/kbuild/kconfig-language.rst +subsection "Kconfig recursive dependency limitations" + +Kconfig:17:error: recursive dependency detected! +Kconfig:17: symbol C1 depends on C2 +Kconfig:21: symbol C2 depends on C1 +For a resolution refer to Documentation/kbuild/kconfig-language.rst +subsection "Kconfig recursive dependency limitations" + +Kconfig:32:error: recursive dependency detected! +Kconfig:32: symbol D2 is selected by D1 +Kconfig:27: symbol D1 depends on D2 +For a resolution refer to Documentation/kbuild/kconfig-language.rst +subsection "Kconfig recursive dependency limitations" + +Kconfig:37:error: recursive dependency detected! +Kconfig:37: symbol E1 depends on E2 +Kconfig:42: symbol E2 is implied by E1 +For a resolution refer to Documentation/kbuild/kconfig-language.rst +subsection "Kconfig recursive dependency limitations" + +Kconfig:60:error: recursive dependency detected! +Kconfig:60: symbol G depends on G +For a resolution refer to Documentation/kbuild/kconfig-language.rst +subsection "Kconfig recursive dependency limitations" + +Kconfig:51:error: recursive dependency detected! +Kconfig:51: symbol F2 depends on F1 +Kconfig:49: symbol F1 default value contains F2 +For a resolution refer to Documentation/kbuild/kconfig-language.rst +subsection "Kconfig recursive dependency limitations" diff --git a/src/net/scripts/kconfig/tests/err_recursive_inc/Kconfig b/src/net/scripts/kconfig/tests/err_recursive_inc/Kconfig new file mode 100644 index 0000000..c6f4ade --- /dev/null +++ b/src/net/scripts/kconfig/tests/err_recursive_inc/Kconfig @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +source "Kconfig.inc1" diff --git a/src/net/scripts/kconfig/tests/err_recursive_inc/Kconfig.inc1 b/src/net/scripts/kconfig/tests/err_recursive_inc/Kconfig.inc1 new file mode 100644 index 0000000..01cbf0d --- /dev/null +++ b/src/net/scripts/kconfig/tests/err_recursive_inc/Kconfig.inc1 @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + + + +source "Kconfig.inc2" diff --git a/src/net/scripts/kconfig/tests/err_recursive_inc/Kconfig.inc2 b/src/net/scripts/kconfig/tests/err_recursive_inc/Kconfig.inc2 new file mode 100644 index 0000000..8235107 --- /dev/null +++ b/src/net/scripts/kconfig/tests/err_recursive_inc/Kconfig.inc2 @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + + +source "Kconfig.inc3" diff --git a/src/net/scripts/kconfig/tests/err_recursive_inc/Kconfig.inc3 b/src/net/scripts/kconfig/tests/err_recursive_inc/Kconfig.inc3 new file mode 100644 index 0000000..c6f4ade --- /dev/null +++ b/src/net/scripts/kconfig/tests/err_recursive_inc/Kconfig.inc3 @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +source "Kconfig.inc1" diff --git a/src/net/scripts/kconfig/tests/err_recursive_inc/__init__.py b/src/net/scripts/kconfig/tests/err_recursive_inc/__init__.py new file mode 100644 index 0000000..27aa189 --- /dev/null +++ b/src/net/scripts/kconfig/tests/err_recursive_inc/__init__.py @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0 +""" +Detect recursive inclusion error. + +If recursive inclusion is detected, it should fail with error messages. +""" + + +def test(conf): + assert conf.oldaskconfig() != 0 + assert conf.stderr_contains('expected_stderr') diff --git a/src/net/scripts/kconfig/tests/err_recursive_inc/expected_stderr b/src/net/scripts/kconfig/tests/err_recursive_inc/expected_stderr new file mode 100644 index 0000000..b070a31 --- /dev/null +++ b/src/net/scripts/kconfig/tests/err_recursive_inc/expected_stderr @@ -0,0 +1,6 @@ +Recursive inclusion detected. +Inclusion path: + current file : Kconfig.inc1 + included from: Kconfig.inc3:2 + included from: Kconfig.inc2:4 + included from: Kconfig.inc1:5 diff --git a/src/net/scripts/kconfig/tests/inter_choice/Kconfig b/src/net/scripts/kconfig/tests/inter_choice/Kconfig new file mode 100644 index 0000000..5698a40 --- /dev/null +++ b/src/net/scripts/kconfig/tests/inter_choice/Kconfig @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: GPL-2.0 + +config MODULES + def_bool y + option modules + +choice + prompt "Choice" + +config CHOICE_VAL0 + tristate "Choice 0" + +config CHOIVE_VAL1 + tristate "Choice 1" + +endchoice + +choice + prompt "Another choice" + depends on CHOICE_VAL0 + +config DUMMY + bool "dummy" + +endchoice diff --git a/src/net/scripts/kconfig/tests/inter_choice/__init__.py b/src/net/scripts/kconfig/tests/inter_choice/__init__.py new file mode 100644 index 0000000..ffea6b1 --- /dev/null +++ b/src/net/scripts/kconfig/tests/inter_choice/__init__.py @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0 +""" +Do not affect user-assigned choice value by another choice. + +Handling of state flags for choices is complecated. In old days, +the defconfig result of a choice could be affected by another choice +if those choices interact by 'depends on', 'select', etc. + +Related Linux commit: fbe98bb9ed3dae23e320c6b113e35f129538d14a +""" + + +def test(conf): + assert conf.defconfig('defconfig') == 0 + assert conf.config_contains('expected_config') diff --git a/src/net/scripts/kconfig/tests/inter_choice/defconfig b/src/net/scripts/kconfig/tests/inter_choice/defconfig new file mode 100644 index 0000000..162c414 --- /dev/null +++ b/src/net/scripts/kconfig/tests/inter_choice/defconfig @@ -0,0 +1 @@ +CONFIG_CHOICE_VAL0=y diff --git a/src/net/scripts/kconfig/tests/inter_choice/expected_config b/src/net/scripts/kconfig/tests/inter_choice/expected_config new file mode 100644 index 0000000..5dceefb --- /dev/null +++ b/src/net/scripts/kconfig/tests/inter_choice/expected_config @@ -0,0 +1,4 @@ +CONFIG_MODULES=y +CONFIG_CHOICE_VAL0=y +# CONFIG_CHOIVE_VAL1 is not set +CONFIG_DUMMY=y diff --git a/src/net/scripts/kconfig/tests/new_choice_with_dep/Kconfig b/src/net/scripts/kconfig/tests/new_choice_with_dep/Kconfig new file mode 100644 index 0000000..127731c --- /dev/null +++ b/src/net/scripts/kconfig/tests/new_choice_with_dep/Kconfig @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: GPL-2.0 + +config A + bool "A" + help + This is a new symbol. + +choice + prompt "Choice ?" + depends on A + help + "depends on A" has been newly added. + +config CHOICE_B + bool "Choice B" + +config CHOICE_C + bool "Choice C" + help + This is a new symbol, so should be asked. + +endchoice + +choice + prompt "Choice2 ?" + +config CHOICE_D + bool "Choice D" + +config CHOICE_E + bool "Choice E" + +config CHOICE_F + bool "Choice F" + depends on A + help + This is a new symbol, so should be asked. + +endchoice diff --git a/src/net/scripts/kconfig/tests/new_choice_with_dep/__init__.py b/src/net/scripts/kconfig/tests/new_choice_with_dep/__init__.py new file mode 100644 index 0000000..fe9d322 --- /dev/null +++ b/src/net/scripts/kconfig/tests/new_choice_with_dep/__init__.py @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0 +""" +Ask new choice values when they become visible. + +If new choice values are added with new dependency, and they become +visible during user configuration, oldconfig should recognize them +as (NEW), and ask the user for choice. + +Related Linux commit: 5d09598d488f081e3be23f885ed65cbbe2d073b5 +""" + + +def test(conf): + assert conf.oldconfig('config', 'y') == 0 + assert conf.stdout_contains('expected_stdout') diff --git a/src/net/scripts/kconfig/tests/new_choice_with_dep/config b/src/net/scripts/kconfig/tests/new_choice_with_dep/config new file mode 100644 index 0000000..47ef95d --- /dev/null +++ b/src/net/scripts/kconfig/tests/new_choice_with_dep/config @@ -0,0 +1,3 @@ +CONFIG_CHOICE_B=y +# CONFIG_CHOICE_D is not set +CONFIG_CHOICE_E=y diff --git a/src/net/scripts/kconfig/tests/new_choice_with_dep/expected_stdout b/src/net/scripts/kconfig/tests/new_choice_with_dep/expected_stdout new file mode 100644 index 0000000..74dc0bc --- /dev/null +++ b/src/net/scripts/kconfig/tests/new_choice_with_dep/expected_stdout @@ -0,0 +1,10 @@ +A (A) [N/y/?] (NEW) y + Choice ? + > 1. Choice B (CHOICE_B) + 2. Choice C (CHOICE_C) (NEW) + choice[1-2?]: +Choice2 ? + 1. Choice D (CHOICE_D) +> 2. Choice E (CHOICE_E) + 3. Choice F (CHOICE_F) (NEW) +choice[1-3?]: diff --git a/src/net/scripts/kconfig/tests/no_write_if_dep_unmet/Kconfig b/src/net/scripts/kconfig/tests/no_write_if_dep_unmet/Kconfig new file mode 100644 index 0000000..4767aab --- /dev/null +++ b/src/net/scripts/kconfig/tests/no_write_if_dep_unmet/Kconfig @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0 + +config A + bool "A" + +choice + prompt "Choice ?" + depends on A + +config CHOICE_B + bool "Choice B" + +config CHOICE_C + bool "Choice C" + +endchoice diff --git a/src/net/scripts/kconfig/tests/no_write_if_dep_unmet/__init__.py b/src/net/scripts/kconfig/tests/no_write_if_dep_unmet/__init__.py new file mode 100644 index 0000000..ffd469d --- /dev/null +++ b/src/net/scripts/kconfig/tests/no_write_if_dep_unmet/__init__.py @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0 +""" +Do not write choice values to .config if the dependency is unmet. + +"# CONFIG_... is not set" should not be written into the .config file +for symbols with unmet dependency. + +This was not working correctly for choice values because choice needs +a bit different symbol computation. + +This checks that no unneeded "# COFIG_... is not set" is contained in +the .config file. + +Related Linux commit: cb67ab2cd2b8abd9650292c986c79901e3073a59 +""" + + +def test(conf): + assert conf.oldaskconfig('config', 'n') == 0 + assert conf.config_matches('expected_config') diff --git a/src/net/scripts/kconfig/tests/no_write_if_dep_unmet/config b/src/net/scripts/kconfig/tests/no_write_if_dep_unmet/config new file mode 100644 index 0000000..abd280e --- /dev/null +++ b/src/net/scripts/kconfig/tests/no_write_if_dep_unmet/config @@ -0,0 +1 @@ +CONFIG_A=y diff --git a/src/net/scripts/kconfig/tests/no_write_if_dep_unmet/expected_config b/src/net/scripts/kconfig/tests/no_write_if_dep_unmet/expected_config new file mode 100644 index 0000000..4732288 --- /dev/null +++ b/src/net/scripts/kconfig/tests/no_write_if_dep_unmet/expected_config @@ -0,0 +1,5 @@ +# +# Automatically generated file; DO NOT EDIT. +# Main menu +# +# CONFIG_A is not set diff --git a/src/net/scripts/kconfig/tests/preprocess/builtin_func/Kconfig b/src/net/scripts/kconfig/tests/preprocess/builtin_func/Kconfig new file mode 100644 index 0000000..baa3288 --- /dev/null +++ b/src/net/scripts/kconfig/tests/preprocess/builtin_func/Kconfig @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: GPL-2.0 + +# 'info' prints the argument to stdout. +$(info,hello world 0) + +# 'warning-if', if the first argument is y, sends the second argument to stderr, +# and the message is prefixed with the current file name and line number. +$(warning-if,y,hello world 1) + +# 'error-if' is similar, but it terminates the parsing immediately. +# The following is just no-op since the first argument is not y. +$(error-if,n,this should not be printed) + +# Shorthand +warning = $(warning-if,y,$(1)) + +# 'shell' executes a command, and returns its stdout. +$(warning,$(shell,echo hello world 3)) + +# Every newline in the output is replaced with a space, +# but any trailing newlines are deleted. +$(warning,$(shell,printf 'hello\nworld\n\n4\n\n\n')) + +# 'filename' is expanded to the currently parsed file name, +# 'lineno' to the line number. +$(warning,filename=$(filename)) +$(warning,lineno=$(lineno)) diff --git a/src/net/scripts/kconfig/tests/preprocess/builtin_func/__init__.py b/src/net/scripts/kconfig/tests/preprocess/builtin_func/__init__.py new file mode 100644 index 0000000..2e53ba0 --- /dev/null +++ b/src/net/scripts/kconfig/tests/preprocess/builtin_func/__init__.py @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0 +""" +Built-in function tests. +""" + +def test(conf): + assert conf.oldaskconfig() == 0 + assert conf.stdout_contains('expected_stdout') + assert conf.stderr_matches('expected_stderr') diff --git a/src/net/scripts/kconfig/tests/preprocess/builtin_func/expected_stderr b/src/net/scripts/kconfig/tests/preprocess/builtin_func/expected_stderr new file mode 100644 index 0000000..33ea9ca --- /dev/null +++ b/src/net/scripts/kconfig/tests/preprocess/builtin_func/expected_stderr @@ -0,0 +1,5 @@ +Kconfig:8: hello world 1 +Kconfig:18: hello world 3 +Kconfig:22: hello world 4 +Kconfig:26: filename=Kconfig +Kconfig:27: lineno=27 diff --git a/src/net/scripts/kconfig/tests/preprocess/builtin_func/expected_stdout b/src/net/scripts/kconfig/tests/preprocess/builtin_func/expected_stdout new file mode 100644 index 0000000..82de3a7 --- /dev/null +++ b/src/net/scripts/kconfig/tests/preprocess/builtin_func/expected_stdout @@ -0,0 +1 @@ +hello world 0 diff --git a/src/net/scripts/kconfig/tests/preprocess/circular_expansion/Kconfig b/src/net/scripts/kconfig/tests/preprocess/circular_expansion/Kconfig new file mode 100644 index 0000000..6838997 --- /dev/null +++ b/src/net/scripts/kconfig/tests/preprocess/circular_expansion/Kconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0 + +X = $(Y) +Y = $(X) +$(info $(X)) diff --git a/src/net/scripts/kconfig/tests/preprocess/circular_expansion/__init__.py b/src/net/scripts/kconfig/tests/preprocess/circular_expansion/__init__.py new file mode 100644 index 0000000..419bda3 --- /dev/null +++ b/src/net/scripts/kconfig/tests/preprocess/circular_expansion/__init__.py @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0 +""" +Detect circular variable expansion. + +If a recursively expanded variable references itself (eventually), +it should fail with an error message. +""" + +def test(conf): + assert conf.oldaskconfig() != 0 + assert conf.stderr_matches('expected_stderr') diff --git a/src/net/scripts/kconfig/tests/preprocess/circular_expansion/expected_stderr b/src/net/scripts/kconfig/tests/preprocess/circular_expansion/expected_stderr new file mode 100644 index 0000000..cde68fa --- /dev/null +++ b/src/net/scripts/kconfig/tests/preprocess/circular_expansion/expected_stderr @@ -0,0 +1 @@ +Kconfig:5: Recursive variable 'X' references itself (eventually) diff --git a/src/net/scripts/kconfig/tests/preprocess/escape/Kconfig b/src/net/scripts/kconfig/tests/preprocess/escape/Kconfig new file mode 100644 index 0000000..4e3f444 --- /dev/null +++ b/src/net/scripts/kconfig/tests/preprocess/escape/Kconfig @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: GPL-2.0 + +# Shorthand +warning = $(warning-if,y,$(1)) + +# You can not pass commas directly to a function since they are treated as +# delimiters. You can use the following trick to do so. +comma := , +$(warning,hello$(comma) world) + +# Like Make, single quotes, double quotes, spaces are treated verbatim. +# The following prints the text as-is. +$(warning, ' " '" ' ''' "'") + +# Unlike Make, '$' has special meaning only when it is followed by '('. +# No need to escape '$' itself. +$(warning,$) +$(warning,$$) +$ := 1 +$(warning,$($)) + +# You need a trick to escape '$' followed by '(' +# The following should print "$(X)". It should not be expanded further. +dollar := $ +$(warning,$(dollar)(X)) + +# You need a trick to treat unbalanced parentheses. +# The following should print "(". +left_paren := ( +$(warning,$(left_paren)) + +# A simple expanded should not be expanded multiple times. +# The following should print "$(X)". It should not be expanded further. +Y := $(dollar)(X) +$(warning,$(Y)) + +# The following should print "$(X)" as well. +Y = $(dollar)(X) +$(warning,$(Y)) + +# The following should print "$(". +# It should not be emit "unterminated reference" error. +unterminated := $(dollar)( +$(warning,$(unterminated)) diff --git a/src/net/scripts/kconfig/tests/preprocess/escape/__init__.py b/src/net/scripts/kconfig/tests/preprocess/escape/__init__.py new file mode 100644 index 0000000..7ee8e74 --- /dev/null +++ b/src/net/scripts/kconfig/tests/preprocess/escape/__init__.py @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0 +""" +Escape sequence tests. +""" + +def test(conf): + assert conf.oldaskconfig() == 0 + assert conf.stderr_matches('expected_stderr') diff --git a/src/net/scripts/kconfig/tests/preprocess/escape/expected_stderr b/src/net/scripts/kconfig/tests/preprocess/escape/expected_stderr new file mode 100644 index 0000000..1c00957 --- /dev/null +++ b/src/net/scripts/kconfig/tests/preprocess/escape/expected_stderr @@ -0,0 +1,10 @@ +Kconfig:9: hello, world +Kconfig:13: ' " '" ' ''' "'" +Kconfig:17: $ +Kconfig:18: $$ +Kconfig:20: 1 +Kconfig:25: $(X) +Kconfig:30: ( +Kconfig:35: $(X) +Kconfig:39: $(X) +Kconfig:44: $( diff --git a/src/net/scripts/kconfig/tests/preprocess/variable/Kconfig b/src/net/scripts/kconfig/tests/preprocess/variable/Kconfig new file mode 100644 index 0000000..9ce2f95 --- /dev/null +++ b/src/net/scripts/kconfig/tests/preprocess/variable/Kconfig @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: GPL-2.0 + +# Shorthand +warning = $(warning-if,y,$(1)) + +# Simply expanded variable. +X := 1 +SIMPLE := $(X) +X := 2 +$(warning,SIMPLE = $(SIMPLE)) + +# Recursively expanded variable. +X := 1 +RECURSIVE = $(X) +X := 2 +$(warning,RECURSIVE = $(RECURSIVE)) + +# Append something to a simply expanded variable. +Y := 3 +SIMPLE += $(Y) +Y := 4 +$(warning,SIMPLE = $(SIMPLE)) + +# Append something to a recursively expanded variable. +Y := 3 +RECURSIVE += $(Y) +Y := 4 +$(warning,RECURSIVE = $(RECURSIVE)) + +# Use += operator to an undefined variable. +# This works as a recursively expanded variable. +Y := 3 +UNDEFINED_VARIABLE += $(Y) +Y := 4 +$(warning,UNDEFINED_VARIABLE = $(UNDEFINED_VARIABLE)) + +# You can use variable references for the lefthand side of assignment statement. +X := A +Y := B +$(X)$(Y) := 5 +$(warning,AB = $(AB)) + +# User-defined function. +greeting = $(1), my name is $(2). +$(warning,$(greeting,Hello,John)) + +# The number of arguments is not checked for user-defined functions. +# If some arguments are optional, it is useful to pass fewer parameters. +# $(2) will be blank in this case. +$(warning,$(greeting,Hello)) + +# Unreferenced parameters are just ignored. +$(warning,$(greeting,Hello,John,ignored,ignored)) diff --git a/src/net/scripts/kconfig/tests/preprocess/variable/__init__.py b/src/net/scripts/kconfig/tests/preprocess/variable/__init__.py new file mode 100644 index 0000000..e88b170 --- /dev/null +++ b/src/net/scripts/kconfig/tests/preprocess/variable/__init__.py @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0 +""" +Variable and user-defined function tests. +""" + +def test(conf): + assert conf.oldaskconfig() == 0 + assert conf.stderr_matches('expected_stderr') diff --git a/src/net/scripts/kconfig/tests/preprocess/variable/expected_stderr b/src/net/scripts/kconfig/tests/preprocess/variable/expected_stderr new file mode 100644 index 0000000..a4841c3 --- /dev/null +++ b/src/net/scripts/kconfig/tests/preprocess/variable/expected_stderr @@ -0,0 +1,9 @@ +Kconfig:10: SIMPLE = 1 +Kconfig:16: RECURSIVE = 2 +Kconfig:22: SIMPLE = 1 3 +Kconfig:28: RECURSIVE = 2 4 +Kconfig:35: UNDEFINED_VARIABLE = 4 +Kconfig:41: AB = 5 +Kconfig:45: Hello, my name is John. +Kconfig:50: Hello, my name is . +Kconfig:53: Hello, my name is John. diff --git a/src/net/scripts/kconfig/tests/pytest.ini b/src/net/scripts/kconfig/tests/pytest.ini new file mode 100644 index 0000000..85d7ce8 --- /dev/null +++ b/src/net/scripts/kconfig/tests/pytest.ini @@ -0,0 +1,7 @@ +[pytest] +addopts = --verbose + +# Pytest requires that test files have unique names, because pytest imports +# them as top-level modules. It is silly to prefix or suffix a test file with +# the directory name that contains it. Use __init__.py for all test files. +python_files = __init__.py diff --git a/src/net/scripts/kconfig/util.c b/src/net/scripts/kconfig/util.c new file mode 100644 index 0000000..2958539 --- /dev/null +++ b/src/net/scripts/kconfig/util.c @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2002-2005 Roman Zippel <zippel@linux-m68k.org> + * Copyright (C) 2002-2005 Sam Ravnborg <sam@ravnborg.org> + */ + +#include <stdarg.h> +#include <stdlib.h> +#include <string.h> +#include "lkc.h" + +/* file already present in list? If not add it */ +struct file *file_lookup(const char *name) +{ + struct file *file; + + for (file = file_list; file; file = file->next) { + if (!strcmp(name, file->name)) { + return file; + } + } + + file = xmalloc(sizeof(*file)); + memset(file, 0, sizeof(*file)); + file->name = xstrdup(name); + file->next = file_list; + file_list = file; + return file; +} + +/* Allocate initial growable string */ +struct gstr str_new(void) +{ + struct gstr gs; + gs.s = xmalloc(sizeof(char) * 64); + gs.len = 64; + gs.max_width = 0; + strcpy(gs.s, "\0"); + return gs; +} + +/* Free storage for growable string */ +void str_free(struct gstr *gs) +{ + if (gs->s) + free(gs->s); + gs->s = NULL; + gs->len = 0; +} + +/* Append to growable string */ +void str_append(struct gstr *gs, const char *s) +{ + size_t l; + if (s) { + l = strlen(gs->s) + strlen(s) + 1; + if (l > gs->len) { + gs->s = xrealloc(gs->s, l); + gs->len = l; + } + strcat(gs->s, s); + } +} + +/* Append printf formatted string to growable string */ +void str_printf(struct gstr *gs, const char *fmt, ...) +{ + va_list ap; + char s[10000]; /* big enough... */ + va_start(ap, fmt); + vsnprintf(s, sizeof(s), fmt, ap); + str_append(gs, s); + va_end(ap); +} + +/* Retrieve value of growable string */ +const char *str_get(struct gstr *gs) +{ + return gs->s; +} + +void *xmalloc(size_t size) +{ + void *p = malloc(size); + if (p) + return p; + fprintf(stderr, "Out of memory.\n"); + exit(1); +} + +void *xcalloc(size_t nmemb, size_t size) +{ + void *p = calloc(nmemb, size); + if (p) + return p; + fprintf(stderr, "Out of memory.\n"); + exit(1); +} + +void *xrealloc(void *p, size_t size) +{ + p = realloc(p, size); + if (p) + return p; + fprintf(stderr, "Out of memory.\n"); + exit(1); +} + +char *xstrdup(const char *s) +{ + char *p; + + p = strdup(s); + if (p) + return p; + fprintf(stderr, "Out of memory.\n"); + exit(1); +} + +char *xstrndup(const char *s, size_t n) +{ + char *p; + + p = strndup(s, n); + if (p) + return p; + fprintf(stderr, "Out of memory.\n"); + exit(1); +} diff --git a/src/net/scripts/kernel-doc b/src/net/scripts/kernel-doc new file mode 100755 index 0000000..6325bec --- /dev/null +++ b/src/net/scripts/kernel-doc @@ -0,0 +1,2439 @@ +#!/usr/bin/env perl +# SPDX-License-Identifier: GPL-2.0 + +use warnings; +use strict; + +## Copyright (c) 1998 Michael Zucchi, All Rights Reserved ## +## Copyright (C) 2000, 1 Tim Waugh <twaugh@redhat.com> ## +## Copyright (C) 2001 Simon Huggins ## +## Copyright (C) 2005-2012 Randy Dunlap ## +## Copyright (C) 2012 Dan Luedtke ## +## ## +## #define enhancements by Armin Kuster <akuster@mvista.com> ## +## Copyright (c) 2000 MontaVista Software, Inc. ## +## ## +## This software falls under the GNU General Public License. ## +## Please read the COPYING file for more information ## + +# 18/01/2001 - Cleanups +# Functions prototyped as foo(void) same as foo() +# Stop eval'ing where we don't need to. +# -- huggie@earth.li + +# 27/06/2001 - Allowed whitespace after initial "/**" and +# allowed comments before function declarations. +# -- Christian Kreibich <ck@whoop.org> + +# Still to do: +# - add perldoc documentation +# - Look more closely at some of the scarier bits :) + +# 26/05/2001 - Support for separate source and object trees. +# Return error code. +# Keith Owens <kaos@ocs.com.au> + +# 23/09/2001 - Added support for typedefs, structs, enums and unions +# Support for Context section; can be terminated using empty line +# Small fixes (like spaces vs. \s in regex) +# -- Tim Jansen <tim@tjansen.de> + +# 25/07/2012 - Added support for HTML5 +# -- Dan Luedtke <mail@danrl.de> + +sub usage { + my $message = <<"EOF"; +Usage: $0 [OPTION ...] FILE ... + +Read C language source or header FILEs, extract embedded documentation comments, +and print formatted documentation to standard output. + +The documentation comments are identified by "/**" opening comment mark. See +Documentation/doc-guide/kernel-doc.rst for the documentation comment syntax. + +Output format selection (mutually exclusive): + -man Output troff manual page format. This is the default. + -rst Output reStructuredText format. + -none Do not output documentation, only warnings. + +Output format selection modifier (affects only ReST output): + + -sphinx-version Use the ReST C domain dialect compatible with an + specific Sphinx Version. + If not specified, kernel-doc will auto-detect using + the sphinx-build version found on PATH. + +Output selection (mutually exclusive): + -export Only output documentation for symbols that have been + exported using EXPORT_SYMBOL() or EXPORT_SYMBOL_GPL() + in any input FILE or -export-file FILE. + -internal Only output documentation for symbols that have NOT been + exported using EXPORT_SYMBOL() or EXPORT_SYMBOL_GPL() + in any input FILE or -export-file FILE. + -function NAME Only output documentation for the given function(s) + or DOC: section title(s). All other functions and DOC: + sections are ignored. May be specified multiple times. + -nosymbol NAME Exclude the specified symbols from the output + documentation. May be specified multiple times. + +Output selection modifiers: + -no-doc-sections Do not output DOC: sections. + -enable-lineno Enable output of #define LINENO lines. Only works with + reStructuredText format. + -export-file FILE Specify an additional FILE in which to look for + EXPORT_SYMBOL() and EXPORT_SYMBOL_GPL(). To be used with + -export or -internal. May be specified multiple times. + +Other parameters: + -v Verbose output, more warnings and other information. + -h Print this help. + -Werror Treat warnings as errors. + +EOF + print $message; + exit 1; +} + +# +# format of comments. +# In the following table, (...)? signifies optional structure. +# (...)* signifies 0 or more structure elements +# /** +# * function_name(:)? (- short description)? +# (* @parameterx: (description of parameter x)?)* +# (* a blank line)? +# * (Description:)? (Description of function)? +# * (section header: (section description)? )* +# (*)?*/ +# +# So .. the trivial example would be: +# +# /** +# * my_function +# */ +# +# If the Description: header tag is omitted, then there must be a blank line +# after the last parameter specification. +# e.g. +# /** +# * my_function - does my stuff +# * @my_arg: its mine damnit +# * +# * Does my stuff explained. +# */ +# +# or, could also use: +# /** +# * my_function - does my stuff +# * @my_arg: its mine damnit +# * Description: Does my stuff explained. +# */ +# etc. +# +# Besides functions you can also write documentation for structs, unions, +# enums and typedefs. Instead of the function name you must write the name +# of the declaration; the struct/union/enum/typedef must always precede +# the name. Nesting of declarations is not supported. +# Use the argument mechanism to document members or constants. +# e.g. +# /** +# * struct my_struct - short description +# * @a: first member +# * @b: second member +# * +# * Longer description +# */ +# struct my_struct { +# int a; +# int b; +# /* private: */ +# int c; +# }; +# +# All descriptions can be multiline, except the short function description. +# +# For really longs structs, you can also describe arguments inside the +# body of the struct. +# eg. +# /** +# * struct my_struct - short description +# * @a: first member +# * @b: second member +# * +# * Longer description +# */ +# struct my_struct { +# int a; +# int b; +# /** +# * @c: This is longer description of C +# * +# * You can use paragraphs to describe arguments +# * using this method. +# */ +# int c; +# }; +# +# This should be use only for struct/enum members. +# +# You can also add additional sections. When documenting kernel functions you +# should document the "Context:" of the function, e.g. whether the functions +# can be called form interrupts. Unlike other sections you can end it with an +# empty line. +# A non-void function should have a "Return:" section describing the return +# value(s). +# Example-sections should contain the string EXAMPLE so that they are marked +# appropriately in DocBook. +# +# Example: +# /** +# * user_function - function that can only be called in user context +# * @a: some argument +# * Context: !in_interrupt() +# * +# * Some description +# * Example: +# * user_function(22); +# */ +# ... +# +# +# All descriptive text is further processed, scanning for the following special +# patterns, which are highlighted appropriately. +# +# 'funcname()' - function +# '$ENVVAR' - environmental variable +# '&struct_name' - name of a structure (up to two words including 'struct') +# '&struct_name.member' - name of a structure member +# '@parameter' - name of a parameter +# '%CONST' - name of a constant. +# '``LITERAL``' - literal string without any spaces on it. + +## init lots of data + +my $errors = 0; +my $warnings = 0; +my $anon_struct_union = 0; + +# match expressions used to find embedded type information +my $type_constant = '\b``([^\`]+)``\b'; +my $type_constant2 = '\%([-_\w]+)'; +my $type_func = '(\w+)\(\)'; +my $type_param = '\@(\w*((\.\w+)|(->\w+))*(\.\.\.)?)'; +my $type_param_ref = '([\!]?)\@(\w*((\.\w+)|(->\w+))*(\.\.\.)?)'; +my $type_fp_param = '\@(\w+)\(\)'; # Special RST handling for func ptr params +my $type_fp_param2 = '\@(\w+->\S+)\(\)'; # Special RST handling for structs with func ptr params +my $type_env = '(\$\w+)'; +my $type_enum = '\&(enum\s*([_\w]+))'; +my $type_struct = '\&(struct\s*([_\w]+))'; +my $type_typedef = '\&(typedef\s*([_\w]+))'; +my $type_union = '\&(union\s*([_\w]+))'; +my $type_member = '\&([_\w]+)(\.|->)([_\w]+)'; +my $type_fallback = '\&([_\w]+)'; +my $type_member_func = $type_member . '\(\)'; + +# Output conversion substitutions. +# One for each output format + +# these are pretty rough +my @highlights_man = ( + [$type_constant, "\$1"], + [$type_constant2, "\$1"], + [$type_func, "\\\\fB\$1\\\\fP"], + [$type_enum, "\\\\fI\$1\\\\fP"], + [$type_struct, "\\\\fI\$1\\\\fP"], + [$type_typedef, "\\\\fI\$1\\\\fP"], + [$type_union, "\\\\fI\$1\\\\fP"], + [$type_param, "\\\\fI\$1\\\\fP"], + [$type_param_ref, "\\\\fI\$1\$2\\\\fP"], + [$type_member, "\\\\fI\$1\$2\$3\\\\fP"], + [$type_fallback, "\\\\fI\$1\\\\fP"] + ); +my $blankline_man = ""; + +# rst-mode +my @highlights_rst = ( + [$type_constant, "``\$1``"], + [$type_constant2, "``\$1``"], + # Note: need to escape () to avoid func matching later + [$type_member_func, "\\:c\\:type\\:`\$1\$2\$3\\\\(\\\\) <\$1>`"], + [$type_member, "\\:c\\:type\\:`\$1\$2\$3 <\$1>`"], + [$type_fp_param, "**\$1\\\\(\\\\)**"], + [$type_fp_param2, "**\$1\\\\(\\\\)**"], + [$type_func, "\$1()"], + [$type_enum, "\\:c\\:type\\:`\$1 <\$2>`"], + [$type_struct, "\\:c\\:type\\:`\$1 <\$2>`"], + [$type_typedef, "\\:c\\:type\\:`\$1 <\$2>`"], + [$type_union, "\\:c\\:type\\:`\$1 <\$2>`"], + # in rst this can refer to any type + [$type_fallback, "\\:c\\:type\\:`\$1`"], + [$type_param_ref, "**\$1\$2**"] + ); +my $blankline_rst = "\n"; + +# read arguments +if ($#ARGV == -1) { + usage(); +} + +my $kernelversion; +my ($sphinx_major, $sphinx_minor, $sphinx_patch); + +my $dohighlight = ""; + +my $verbose = 0; +my $Werror = 0; +my $output_mode = "rst"; +my $output_preformatted = 0; +my $no_doc_sections = 0; +my $enable_lineno = 0; +my @highlights = @highlights_rst; +my $blankline = $blankline_rst; +my $modulename = "Kernel API"; + +use constant { + OUTPUT_ALL => 0, # output all symbols and doc sections + OUTPUT_INCLUDE => 1, # output only specified symbols + OUTPUT_EXPORTED => 2, # output exported symbols + OUTPUT_INTERNAL => 3, # output non-exported symbols +}; +my $output_selection = OUTPUT_ALL; +my $show_not_found = 0; # No longer used + +my @export_file_list; + +my @build_time; +if (defined($ENV{'KBUILD_BUILD_TIMESTAMP'}) && + (my $seconds = `date -d"${ENV{'KBUILD_BUILD_TIMESTAMP'}}" +%s`) ne '') { + @build_time = gmtime($seconds); +} else { + @build_time = localtime; +} + +my $man_date = ('January', 'February', 'March', 'April', 'May', 'June', + 'July', 'August', 'September', 'October', + 'November', 'December')[$build_time[4]] . + " " . ($build_time[5]+1900); + +# Essentially these are globals. +# They probably want to be tidied up, made more localised or something. +# CAVEAT EMPTOR! Some of the others I localised may not want to be, which +# could cause "use of undefined value" or other bugs. +my ($function, %function_table, %parametertypes, $declaration_purpose); +my %nosymbol_table = (); +my $declaration_start_line; +my ($type, $declaration_name, $return_type); +my ($newsection, $newcontents, $prototype, $brcount, %source_map); + +if (defined($ENV{'KBUILD_VERBOSE'})) { + $verbose = "$ENV{'KBUILD_VERBOSE'}"; +} + +if (defined($ENV{'KDOC_WERROR'})) { + $Werror = "$ENV{'KDOC_WERROR'}"; +} + +if (defined($ENV{'KCFLAGS'})) { + my $kcflags = "$ENV{'KCFLAGS'}"; + + if ($kcflags =~ /Werror/) { + $Werror = 1; + } +} + +# Generated docbook code is inserted in a template at a point where +# docbook v3.1 requires a non-zero sequence of RefEntry's; see: +# https://www.oasis-open.org/docbook/documentation/reference/html/refentry.html +# We keep track of number of generated entries and generate a dummy +# if needs be to ensure the expanded template can be postprocessed +# into html. +my $section_counter = 0; + +my $lineprefix=""; + +# Parser states +use constant { + STATE_NORMAL => 0, # normal code + STATE_NAME => 1, # looking for function name + STATE_BODY_MAYBE => 2, # body - or maybe more description + STATE_BODY => 3, # the body of the comment + STATE_BODY_WITH_BLANK_LINE => 4, # the body, which has a blank line + STATE_PROTO => 5, # scanning prototype + STATE_DOCBLOCK => 6, # documentation block + STATE_INLINE => 7, # gathering doc outside main block +}; +my $state; +my $in_doc_sect; +my $leading_space; + +# Inline documentation state +use constant { + STATE_INLINE_NA => 0, # not applicable ($state != STATE_INLINE) + STATE_INLINE_NAME => 1, # looking for member name (@foo:) + STATE_INLINE_TEXT => 2, # looking for member documentation + STATE_INLINE_END => 3, # done + STATE_INLINE_ERROR => 4, # error - Comment without header was found. + # Spit a warning as it's not + # proper kernel-doc and ignore the rest. +}; +my $inline_doc_state; + +#declaration types: can be +# 'function', 'struct', 'union', 'enum', 'typedef' +my $decl_type; + +my $doc_start = '^/\*\*\s*$'; # Allow whitespace at end of comment start. +my $doc_end = '\*/'; +my $doc_com = '\s*\*\s*'; +my $doc_com_body = '\s*\* ?'; +my $doc_decl = $doc_com . '(\w+)'; +# @params and a strictly limited set of supported section names +my $doc_sect = $doc_com . + '\s*(\@[.\w]+|\@\.\.\.|description|context|returns?|notes?|examples?)\s*:(.*)'; +my $doc_content = $doc_com_body . '(.*)'; +my $doc_block = $doc_com . 'DOC:\s*(.*)?'; +my $doc_inline_start = '^\s*/\*\*\s*$'; +my $doc_inline_sect = '\s*\*\s*(@\s*[\w][\w\.]*\s*):(.*)'; +my $doc_inline_end = '^\s*\*/\s*$'; +my $doc_inline_oneline = '^\s*/\*\*\s*(@[\w\s]+):\s*(.*)\s*\*/\s*$'; +my $export_symbol = '^\s*EXPORT_SYMBOL(_GPL)?\s*\(\s*(\w+)\s*\)\s*;'; + +my %parameterdescs; +my %parameterdesc_start_lines; +my @parameterlist; +my %sections; +my @sectionlist; +my %section_start_lines; +my $sectcheck; +my $struct_actual; + +my $contents = ""; +my $new_start_line = 0; + +# the canonical section names. see also $doc_sect above. +my $section_default = "Description"; # default section +my $section_intro = "Introduction"; +my $section = $section_default; +my $section_context = "Context"; +my $section_return = "Return"; + +my $undescribed = "-- undescribed --"; + +reset_state(); + +while ($ARGV[0] =~ m/^--?(.*)/) { + my $cmd = $1; + shift @ARGV; + if ($cmd eq "man") { + $output_mode = "man"; + @highlights = @highlights_man; + $blankline = $blankline_man; + } elsif ($cmd eq "rst") { + $output_mode = "rst"; + @highlights = @highlights_rst; + $blankline = $blankline_rst; + } elsif ($cmd eq "none") { + $output_mode = "none"; + } elsif ($cmd eq "module") { # not needed for XML, inherits from calling document + $modulename = shift @ARGV; + } elsif ($cmd eq "function") { # to only output specific functions + $output_selection = OUTPUT_INCLUDE; + $function = shift @ARGV; + $function_table{$function} = 1; + } elsif ($cmd eq "nosymbol") { # Exclude specific symbols + my $symbol = shift @ARGV; + $nosymbol_table{$symbol} = 1; + } elsif ($cmd eq "export") { # only exported symbols + $output_selection = OUTPUT_EXPORTED; + %function_table = (); + } elsif ($cmd eq "internal") { # only non-exported symbols + $output_selection = OUTPUT_INTERNAL; + %function_table = (); + } elsif ($cmd eq "export-file") { + my $file = shift @ARGV; + push(@export_file_list, $file); + } elsif ($cmd eq "v") { + $verbose = 1; + } elsif ($cmd eq "Werror") { + $Werror = 1; + } elsif (($cmd eq "h") || ($cmd eq "help")) { + usage(); + } elsif ($cmd eq 'no-doc-sections') { + $no_doc_sections = 1; + } elsif ($cmd eq 'enable-lineno') { + $enable_lineno = 1; + } elsif ($cmd eq 'show-not-found') { + $show_not_found = 1; # A no-op but don't fail + } elsif ($cmd eq "sphinx-version") { + my $ver_string = shift @ARGV; + if ($ver_string =~ m/^(\d+)(\.\d+)?(\.\d+)?/) { + $sphinx_major = $1; + if (defined($2)) { + $sphinx_minor = substr($2,1); + } else { + $sphinx_minor = 0; + } + if (defined($3)) { + $sphinx_patch = substr($3,1) + } else { + $sphinx_patch = 0; + } + } else { + die "Sphinx version should either major.minor or major.minor.patch format\n"; + } + } else { + # Unknown argument + usage(); + } +} + +# continue execution near EOF; + +# The C domain dialect changed on Sphinx 3. So, we need to check the +# version in order to produce the right tags. +sub findprog($) +{ + foreach(split(/:/, $ENV{PATH})) { + return "$_/$_[0]" if(-x "$_/$_[0]"); + } +} + +sub get_sphinx_version() +{ + my $ver; + + my $cmd = "sphinx-build"; + if (!findprog($cmd)) { + my $cmd = "sphinx-build3"; + if (!findprog($cmd)) { + $sphinx_major = 1; + $sphinx_minor = 2; + $sphinx_patch = 0; + printf STDERR "Warning: Sphinx version not found. Using default (Sphinx version %d.%d.%d)\n", + $sphinx_major, $sphinx_minor, $sphinx_patch; + return; + } + } + + open IN, "$cmd --version 2>&1 |"; + while (<IN>) { + if (m/^\s*sphinx-build\s+([\d]+)\.([\d\.]+)(\+\/[\da-f]+)?$/) { + $sphinx_major = $1; + $sphinx_minor = $2; + $sphinx_patch = $3; + last; + } + # Sphinx 1.2.x uses a different format + if (m/^\s*Sphinx.*\s+([\d]+)\.([\d\.]+)$/) { + $sphinx_major = $1; + $sphinx_minor = $2; + $sphinx_patch = $3; + last; + } + } + close IN; +} + +# get kernel version from env +sub get_kernel_version() { + my $version = 'unknown kernel version'; + + if (defined($ENV{'KERNELVERSION'})) { + $version = $ENV{'KERNELVERSION'}; + } + return $version; +} + +# +sub print_lineno { + my $lineno = shift; + if ($enable_lineno && defined($lineno)) { + print "#define LINENO " . $lineno . "\n"; + } +} +## +# dumps section contents to arrays/hashes intended for that purpose. +# +sub dump_section { + my $file = shift; + my $name = shift; + my $contents = join "\n", @_; + + if ($name =~ m/$type_param/) { + $name = $1; + $parameterdescs{$name} = $contents; + $sectcheck = $sectcheck . $name . " "; + $parameterdesc_start_lines{$name} = $new_start_line; + $new_start_line = 0; + } elsif ($name eq "@\.\.\.") { + $name = "..."; + $parameterdescs{$name} = $contents; + $sectcheck = $sectcheck . $name . " "; + $parameterdesc_start_lines{$name} = $new_start_line; + $new_start_line = 0; + } else { + if (defined($sections{$name}) && ($sections{$name} ne "")) { + # Only warn on user specified duplicate section names. + if ($name ne $section_default) { + print STDERR "${file}:$.: warning: duplicate section name '$name'\n"; + ++$warnings; + } + $sections{$name} .= $contents; + } else { + $sections{$name} = $contents; + push @sectionlist, $name; + $section_start_lines{$name} = $new_start_line; + $new_start_line = 0; + } + } +} + +## +# dump DOC: section after checking that it should go out +# +sub dump_doc_section { + my $file = shift; + my $name = shift; + my $contents = join "\n", @_; + + if ($no_doc_sections) { + return; + } + + return if (defined($nosymbol_table{$name})); + + if (($output_selection == OUTPUT_ALL) || + (($output_selection == OUTPUT_INCLUDE) && + defined($function_table{$name}))) + { + dump_section($file, $name, $contents); + output_blockhead({'sectionlist' => \@sectionlist, + 'sections' => \%sections, + 'module' => $modulename, + 'content-only' => ($output_selection != OUTPUT_ALL), }); + } +} + +## +# output function +# +# parameterdescs, a hash. +# function => "function name" +# parameterlist => @list of parameters +# parameterdescs => %parameter descriptions +# sectionlist => @list of sections +# sections => %section descriptions +# + +sub output_highlight { + my $contents = join "\n",@_; + my $line; + +# DEBUG +# if (!defined $contents) { +# use Carp; +# confess "output_highlight got called with no args?\n"; +# } + +# print STDERR "contents b4:$contents\n"; + eval $dohighlight; + die $@ if $@; +# print STDERR "contents af:$contents\n"; + + foreach $line (split "\n", $contents) { + if (! $output_preformatted) { + $line =~ s/^\s*//; + } + if ($line eq ""){ + if (! $output_preformatted) { + print $lineprefix, $blankline; + } + } else { + if ($output_mode eq "man" && substr($line, 0, 1) eq ".") { + print "\\&$line"; + } else { + print $lineprefix, $line; + } + } + print "\n"; + } +} + +## +# output function in man +sub output_function_man(%) { + my %args = %{$_[0]}; + my ($parameter, $section); + my $count; + + print ".TH \"$args{'function'}\" 9 \"$args{'function'}\" \"$man_date\" \"Kernel Hacker's Manual\" LINUX\n"; + + print ".SH NAME\n"; + print $args{'function'} . " \\- " . $args{'purpose'} . "\n"; + + print ".SH SYNOPSIS\n"; + if ($args{'functiontype'} ne "") { + print ".B \"" . $args{'functiontype'} . "\" " . $args{'function'} . "\n"; + } else { + print ".B \"" . $args{'function'} . "\n"; + } + $count = 0; + my $parenth = "("; + my $post = ","; + foreach my $parameter (@{$args{'parameterlist'}}) { + if ($count == $#{$args{'parameterlist'}}) { + $post = ");"; + } + $type = $args{'parametertypes'}{$parameter}; + if ($type =~ m/([^\(]*\(\*)\s*\)\s*\(([^\)]*)\)/) { + # pointer-to-function + print ".BI \"" . $parenth . $1 . "\" " . " \") (" . $2 . ")" . $post . "\"\n"; + } else { + $type =~ s/([^\*])$/$1 /; + print ".BI \"" . $parenth . $type . "\" " . " \"" . $post . "\"\n"; + } + $count++; + $parenth = ""; + } + + print ".SH ARGUMENTS\n"; + foreach $parameter (@{$args{'parameterlist'}}) { + my $parameter_name = $parameter; + $parameter_name =~ s/\[.*//; + + print ".IP \"" . $parameter . "\" 12\n"; + output_highlight($args{'parameterdescs'}{$parameter_name}); + } + foreach $section (@{$args{'sectionlist'}}) { + print ".SH \"", uc $section, "\"\n"; + output_highlight($args{'sections'}{$section}); + } +} + +## +# output enum in man +sub output_enum_man(%) { + my %args = %{$_[0]}; + my ($parameter, $section); + my $count; + + print ".TH \"$args{'module'}\" 9 \"enum $args{'enum'}\" \"$man_date\" \"API Manual\" LINUX\n"; + + print ".SH NAME\n"; + print "enum " . $args{'enum'} . " \\- " . $args{'purpose'} . "\n"; + + print ".SH SYNOPSIS\n"; + print "enum " . $args{'enum'} . " {\n"; + $count = 0; + foreach my $parameter (@{$args{'parameterlist'}}) { + print ".br\n.BI \" $parameter\"\n"; + if ($count == $#{$args{'parameterlist'}}) { + print "\n};\n"; + last; + } + else { + print ", \n.br\n"; + } + $count++; + } + + print ".SH Constants\n"; + foreach $parameter (@{$args{'parameterlist'}}) { + my $parameter_name = $parameter; + $parameter_name =~ s/\[.*//; + + print ".IP \"" . $parameter . "\" 12\n"; + output_highlight($args{'parameterdescs'}{$parameter_name}); + } + foreach $section (@{$args{'sectionlist'}}) { + print ".SH \"$section\"\n"; + output_highlight($args{'sections'}{$section}); + } +} + +## +# output struct in man +sub output_struct_man(%) { + my %args = %{$_[0]}; + my ($parameter, $section); + + print ".TH \"$args{'module'}\" 9 \"" . $args{'type'} . " " . $args{'struct'} . "\" \"$man_date\" \"API Manual\" LINUX\n"; + + print ".SH NAME\n"; + print $args{'type'} . " " . $args{'struct'} . " \\- " . $args{'purpose'} . "\n"; + + my $declaration = $args{'definition'}; + $declaration =~ s/\t/ /g; + $declaration =~ s/\n/"\n.br\n.BI \"/g; + print ".SH SYNOPSIS\n"; + print $args{'type'} . " " . $args{'struct'} . " {\n.br\n"; + print ".BI \"$declaration\n};\n.br\n\n"; + + print ".SH Members\n"; + foreach $parameter (@{$args{'parameterlist'}}) { + ($parameter =~ /^#/) && next; + + my $parameter_name = $parameter; + $parameter_name =~ s/\[.*//; + + ($args{'parameterdescs'}{$parameter_name} ne $undescribed) || next; + print ".IP \"" . $parameter . "\" 12\n"; + output_highlight($args{'parameterdescs'}{$parameter_name}); + } + foreach $section (@{$args{'sectionlist'}}) { + print ".SH \"$section\"\n"; + output_highlight($args{'sections'}{$section}); + } +} + +## +# output typedef in man +sub output_typedef_man(%) { + my %args = %{$_[0]}; + my ($parameter, $section); + + print ".TH \"$args{'module'}\" 9 \"$args{'typedef'}\" \"$man_date\" \"API Manual\" LINUX\n"; + + print ".SH NAME\n"; + print "typedef " . $args{'typedef'} . " \\- " . $args{'purpose'} . "\n"; + + foreach $section (@{$args{'sectionlist'}}) { + print ".SH \"$section\"\n"; + output_highlight($args{'sections'}{$section}); + } +} + +sub output_blockhead_man(%) { + my %args = %{$_[0]}; + my ($parameter, $section); + my $count; + + print ".TH \"$args{'module'}\" 9 \"$args{'module'}\" \"$man_date\" \"API Manual\" LINUX\n"; + + foreach $section (@{$args{'sectionlist'}}) { + print ".SH \"$section\"\n"; + output_highlight($args{'sections'}{$section}); + } +} + +## +# output in restructured text +# + +# +# This could use some work; it's used to output the DOC: sections, and +# starts by putting out the name of the doc section itself, but that tends +# to duplicate a header already in the template file. +# +sub output_blockhead_rst(%) { + my %args = %{$_[0]}; + my ($parameter, $section); + + foreach $section (@{$args{'sectionlist'}}) { + next if (defined($nosymbol_table{$section})); + + if ($output_selection != OUTPUT_INCLUDE) { + print "**$section**\n\n"; + } + print_lineno($section_start_lines{$section}); + output_highlight_rst($args{'sections'}{$section}); + print "\n"; + } +} + +# +# Apply the RST highlights to a sub-block of text. +# +sub highlight_block($) { + # The dohighlight kludge requires the text be called $contents + my $contents = shift; + eval $dohighlight; + die $@ if $@; + return $contents; +} + +# +# Regexes used only here. +# +my $sphinx_literal = '^[^.].*::$'; +my $sphinx_cblock = '^\.\.\ +code-block::'; + +sub output_highlight_rst { + my $input = join "\n",@_; + my $output = ""; + my $line; + my $in_literal = 0; + my $litprefix; + my $block = ""; + + foreach $line (split "\n",$input) { + # + # If we're in a literal block, see if we should drop out + # of it. Otherwise pass the line straight through unmunged. + # + if ($in_literal) { + if (! ($line =~ /^\s*$/)) { + # + # If this is the first non-blank line in a literal + # block we need to figure out what the proper indent is. + # + if ($litprefix eq "") { + $line =~ /^(\s*)/; + $litprefix = '^' . $1; + $output .= $line . "\n"; + } elsif (! ($line =~ /$litprefix/)) { + $in_literal = 0; + } else { + $output .= $line . "\n"; + } + } else { + $output .= $line . "\n"; + } + } + # + # Not in a literal block (or just dropped out) + # + if (! $in_literal) { + $block .= $line . "\n"; + if (($line =~ /$sphinx_literal/) || ($line =~ /$sphinx_cblock/)) { + $in_literal = 1; + $litprefix = ""; + $output .= highlight_block($block); + $block = "" + } + } + } + + if ($block) { + $output .= highlight_block($block); + } + foreach $line (split "\n", $output) { + print $lineprefix . $line . "\n"; + } +} + +sub output_function_rst(%) { + my %args = %{$_[0]}; + my ($parameter, $section); + my $oldprefix = $lineprefix; + my $start = ""; + my $is_macro = 0; + + if ($sphinx_major < 3) { + if ($args{'typedef'}) { + print ".. c:type:: ". $args{'function'} . "\n\n"; + print_lineno($declaration_start_line); + print " **Typedef**: "; + $lineprefix = ""; + output_highlight_rst($args{'purpose'}); + $start = "\n\n**Syntax**\n\n ``"; + $is_macro = 1; + } else { + print ".. c:function:: "; + } + } else { + if ($args{'typedef'} || $args{'functiontype'} eq "") { + $is_macro = 1; + print ".. c:macro:: ". $args{'function'} . "\n\n"; + } else { + print ".. c:function:: "; + } + + if ($args{'typedef'}) { + print_lineno($declaration_start_line); + print " **Typedef**: "; + $lineprefix = ""; + output_highlight_rst($args{'purpose'}); + $start = "\n\n**Syntax**\n\n ``"; + } else { + print "``" if ($is_macro); + } + } + if ($args{'functiontype'} ne "") { + $start .= $args{'functiontype'} . " " . $args{'function'} . " ("; + } else { + $start .= $args{'function'} . " ("; + } + print $start; + + my $count = 0; + foreach my $parameter (@{$args{'parameterlist'}}) { + if ($count ne 0) { + print ", "; + } + $count++; + $type = $args{'parametertypes'}{$parameter}; + + if ($type =~ m/([^\(]*\(\*)\s*\)\s*\(([^\)]*)\)/) { + # pointer-to-function + print $1 . $parameter . ") (" . $2 . ")"; + } else { + print $type; + } + } + if ($is_macro) { + print ")``\n\n"; + } else { + print ")\n\n"; + } + if (!$args{'typedef'}) { + print_lineno($declaration_start_line); + $lineprefix = " "; + output_highlight_rst($args{'purpose'}); + print "\n"; + } + + print "**Parameters**\n\n"; + $lineprefix = " "; + foreach $parameter (@{$args{'parameterlist'}}) { + my $parameter_name = $parameter; + $parameter_name =~ s/\[.*//; + $type = $args{'parametertypes'}{$parameter}; + + if ($type ne "") { + print "``$type``\n"; + } else { + print "``$parameter``\n"; + } + + print_lineno($parameterdesc_start_lines{$parameter_name}); + + if (defined($args{'parameterdescs'}{$parameter_name}) && + $args{'parameterdescs'}{$parameter_name} ne $undescribed) { + output_highlight_rst($args{'parameterdescs'}{$parameter_name}); + } else { + print " *undescribed*\n"; + } + print "\n"; + } + + $lineprefix = $oldprefix; + output_section_rst(@_); +} + +sub output_section_rst(%) { + my %args = %{$_[0]}; + my $section; + my $oldprefix = $lineprefix; + $lineprefix = ""; + + foreach $section (@{$args{'sectionlist'}}) { + print "**$section**\n\n"; + print_lineno($section_start_lines{$section}); + output_highlight_rst($args{'sections'}{$section}); + print "\n"; + } + print "\n"; + $lineprefix = $oldprefix; +} + +sub output_enum_rst(%) { + my %args = %{$_[0]}; + my ($parameter); + my $oldprefix = $lineprefix; + my $count; + + if ($sphinx_major < 3) { + my $name = "enum " . $args{'enum'}; + print "\n\n.. c:type:: " . $name . "\n\n"; + } else { + my $name = $args{'enum'}; + print "\n\n.. c:enum:: " . $name . "\n\n"; + } + print_lineno($declaration_start_line); + $lineprefix = " "; + output_highlight_rst($args{'purpose'}); + print "\n"; + + print "**Constants**\n\n"; + $lineprefix = " "; + foreach $parameter (@{$args{'parameterlist'}}) { + print "``$parameter``\n"; + if ($args{'parameterdescs'}{$parameter} ne $undescribed) { + output_highlight_rst($args{'parameterdescs'}{$parameter}); + } else { + print " *undescribed*\n"; + } + print "\n"; + } + + $lineprefix = $oldprefix; + output_section_rst(@_); +} + +sub output_typedef_rst(%) { + my %args = %{$_[0]}; + my ($parameter); + my $oldprefix = $lineprefix; + my $name; + + if ($sphinx_major < 3) { + $name = "typedef " . $args{'typedef'}; + } else { + $name = $args{'typedef'}; + } + print "\n\n.. c:type:: " . $name . "\n\n"; + print_lineno($declaration_start_line); + $lineprefix = " "; + output_highlight_rst($args{'purpose'}); + print "\n"; + + $lineprefix = $oldprefix; + output_section_rst(@_); +} + +sub output_struct_rst(%) { + my %args = %{$_[0]}; + my ($parameter); + my $oldprefix = $lineprefix; + + if ($sphinx_major < 3) { + my $name = $args{'type'} . " " . $args{'struct'}; + print "\n\n.. c:type:: " . $name . "\n\n"; + } else { + my $name = $args{'struct'}; + if ($args{'type'} eq 'union') { + print "\n\n.. c:union:: " . $name . "\n\n"; + } else { + print "\n\n.. c:struct:: " . $name . "\n\n"; + } + } + print_lineno($declaration_start_line); + $lineprefix = " "; + output_highlight_rst($args{'purpose'}); + print "\n"; + + print "**Definition**\n\n"; + print "::\n\n"; + my $declaration = $args{'definition'}; + $declaration =~ s/\t/ /g; + print " " . $args{'type'} . " " . $args{'struct'} . " {\n$declaration };\n\n"; + + print "**Members**\n\n"; + $lineprefix = " "; + foreach $parameter (@{$args{'parameterlist'}}) { + ($parameter =~ /^#/) && next; + + my $parameter_name = $parameter; + $parameter_name =~ s/\[.*//; + + ($args{'parameterdescs'}{$parameter_name} ne $undescribed) || next; + $type = $args{'parametertypes'}{$parameter}; + print_lineno($parameterdesc_start_lines{$parameter_name}); + print "``" . $parameter . "``\n"; + output_highlight_rst($args{'parameterdescs'}{$parameter_name}); + print "\n"; + } + print "\n"; + + $lineprefix = $oldprefix; + output_section_rst(@_); +} + +## none mode output functions + +sub output_function_none(%) { +} + +sub output_enum_none(%) { +} + +sub output_typedef_none(%) { +} + +sub output_struct_none(%) { +} + +sub output_blockhead_none(%) { +} + +## +# generic output function for all types (function, struct/union, typedef, enum); +# calls the generated, variable output_ function name based on +# functype and output_mode +sub output_declaration { + no strict 'refs'; + my $name = shift; + my $functype = shift; + my $func = "output_${functype}_$output_mode"; + + return if (defined($nosymbol_table{$name})); + + if (($output_selection == OUTPUT_ALL) || + (($output_selection == OUTPUT_INCLUDE || + $output_selection == OUTPUT_EXPORTED) && + defined($function_table{$name})) || + ($output_selection == OUTPUT_INTERNAL && + !($functype eq "function" && defined($function_table{$name})))) + { + &$func(@_); + $section_counter++; + } +} + +## +# generic output function - calls the right one based on current output mode. +sub output_blockhead { + no strict 'refs'; + my $func = "output_blockhead_" . $output_mode; + &$func(@_); + $section_counter++; +} + +## +# takes a declaration (struct, union, enum, typedef) and +# invokes the right handler. NOT called for functions. +sub dump_declaration($$) { + no strict 'refs'; + my ($prototype, $file) = @_; + my $func = "dump_" . $decl_type; + &$func(@_); +} + +sub dump_union($$) { + dump_struct(@_); +} + +sub dump_struct($$) { + my $x = shift; + my $file = shift; + + if ($x =~ /(struct|union)\s+(\w+)\s*\{(.*)\}(\s*(__packed|__aligned|____cacheline_aligned_in_smp|____cacheline_aligned|__attribute__\s*\(\([a-z0-9,_\s\(\)]*\)\)))*/) { + my $decl_type = $1; + $declaration_name = $2; + my $members = $3; + + # ignore members marked private: + $members =~ s/\/\*\s*private:.*?\/\*\s*public:.*?\*\///gosi; + $members =~ s/\/\*\s*private:.*//gosi; + # strip comments: + $members =~ s/\/\*.*?\*\///gos; + # strip attributes + $members =~ s/\s*__attribute__\s*\(\([a-z0-9,_\*\s\(\)]*\)\)/ /gi; + $members =~ s/\s*__aligned\s*\([^;]*\)/ /gos; + $members =~ s/\s*__packed\s*/ /gos; + $members =~ s/\s*CRYPTO_MINALIGN_ATTR/ /gos; + $members =~ s/\s*____cacheline_aligned_in_smp/ /gos; + $members =~ s/\s*____cacheline_aligned/ /gos; + + # replace DECLARE_BITMAP + $members =~ s/__ETHTOOL_DECLARE_LINK_MODE_MASK\s*\(([^\)]+)\)/DECLARE_BITMAP($1, __ETHTOOL_LINK_MODE_MASK_NBITS)/gos; + $members =~ s/DECLARE_BITMAP\s*\(([^,)]+),\s*([^,)]+)\)/unsigned long $1\[BITS_TO_LONGS($2)\]/gos; + # replace DECLARE_HASHTABLE + $members =~ s/DECLARE_HASHTABLE\s*\(([^,)]+),\s*([^,)]+)\)/unsigned long $1\[1 << (($2) - 1)\]/gos; + # replace DECLARE_KFIFO + $members =~ s/DECLARE_KFIFO\s*\(([^,)]+),\s*([^,)]+),\s*([^,)]+)\)/$2 \*$1/gos; + # replace DECLARE_KFIFO_PTR + $members =~ s/DECLARE_KFIFO_PTR\s*\(([^,)]+),\s*([^,)]+)\)/$2 \*$1/gos; + + my $declaration = $members; + + # Split nested struct/union elements as newer ones + while ($members =~ m/(struct|union)([^\{\};]+)\{([^\{\}]*)\}([^\{\}\;]*)\;/) { + my $newmember; + my $maintype = $1; + my $ids = $4; + my $content = $3; + foreach my $id(split /,/, $ids) { + $newmember .= "$maintype $id; "; + + $id =~ s/[:\[].*//; + $id =~ s/^\s*\**(\S+)\s*/$1/; + foreach my $arg (split /;/, $content) { + next if ($arg =~ m/^\s*$/); + if ($arg =~ m/^([^\(]+\(\*?\s*)([\w\.]*)(\s*\).*)/) { + # pointer-to-function + my $type = $1; + my $name = $2; + my $extra = $3; + next if (!$name); + if ($id =~ m/^\s*$/) { + # anonymous struct/union + $newmember .= "$type$name$extra; "; + } else { + $newmember .= "$type$id.$name$extra; "; + } + } else { + my $type; + my $names; + $arg =~ s/^\s+//; + $arg =~ s/\s+$//; + # Handle bitmaps + $arg =~ s/:\s*\d+\s*//g; + # Handle arrays + $arg =~ s/\[.*\]//g; + # The type may have multiple words, + # and multiple IDs can be defined, like: + # const struct foo, *bar, foobar + # So, we remove spaces when parsing the + # names, in order to match just names + # and commas for the names + $arg =~ s/\s*,\s*/,/g; + if ($arg =~ m/(.*)\s+([\S+,]+)/) { + $type = $1; + $names = $2; + } else { + $newmember .= "$arg; "; + next; + } + foreach my $name (split /,/, $names) { + $name =~ s/^\s*\**(\S+)\s*/$1/; + next if (($name =~ m/^\s*$/)); + if ($id =~ m/^\s*$/) { + # anonymous struct/union + $newmember .= "$type $name; "; + } else { + $newmember .= "$type $id.$name; "; + } + } + } + } + } + $members =~ s/(struct|union)([^\{\};]+)\{([^\{\}]*)\}([^\{\}\;]*)\;/$newmember/; + } + + # Ignore other nested elements, like enums + $members =~ s/(\{[^\{\}]*\})//g; + + create_parameterlist($members, ';', $file, $declaration_name); + check_sections($file, $declaration_name, $decl_type, $sectcheck, $struct_actual); + + # Adjust declaration for better display + $declaration =~ s/([\{;])/$1\n/g; + $declaration =~ s/\}\s+;/};/g; + # Better handle inlined enums + do {} while ($declaration =~ s/(enum\s+\{[^\}]+),([^\n])/$1,\n$2/); + + my @def_args = split /\n/, $declaration; + my $level = 1; + $declaration = ""; + foreach my $clause (@def_args) { + $clause =~ s/^\s+//; + $clause =~ s/\s+$//; + $clause =~ s/\s+/ /; + next if (!$clause); + $level-- if ($clause =~ m/(\})/ && $level > 1); + if (!($clause =~ m/^\s*#/)) { + $declaration .= "\t" x $level; + } + $declaration .= "\t" . $clause . "\n"; + $level++ if ($clause =~ m/(\{)/ && !($clause =~m/\}/)); + } + output_declaration($declaration_name, + 'struct', + {'struct' => $declaration_name, + 'module' => $modulename, + 'definition' => $declaration, + 'parameterlist' => \@parameterlist, + 'parameterdescs' => \%parameterdescs, + 'parametertypes' => \%parametertypes, + 'sectionlist' => \@sectionlist, + 'sections' => \%sections, + 'purpose' => $declaration_purpose, + 'type' => $decl_type + }); + } + else { + print STDERR "${file}:$.: error: Cannot parse struct or union!\n"; + ++$errors; + } +} + + +sub show_warnings($$) { + my $functype = shift; + my $name = shift; + + return 0 if (defined($nosymbol_table{$name})); + + return 1 if ($output_selection == OUTPUT_ALL); + + if ($output_selection == OUTPUT_EXPORTED) { + if (defined($function_table{$name})) { + return 1; + } else { + return 0; + } + } + if ($output_selection == OUTPUT_INTERNAL) { + if (!($functype eq "function" && defined($function_table{$name}))) { + return 1; + } else { + return 0; + } + } + if ($output_selection == OUTPUT_INCLUDE) { + if (defined($function_table{$name})) { + return 1; + } else { + return 0; + } + } + die("Please add the new output type at show_warnings()"); +} + +sub dump_enum($$) { + my $x = shift; + my $file = shift; + my $members; + + + $x =~ s@/\*.*?\*/@@gos; # strip comments. + # strip #define macros inside enums + $x =~ s@#\s*((define|ifdef)\s+|endif)[^;]*;@@gos; + + if ($x =~ /typedef\s+enum\s*\{(.*)\}\s*(\w*)\s*;/) { + $declaration_name = $2; + $members = $1; + } elsif ($x =~ /enum\s+(\w*)\s*\{(.*)\}/) { + $declaration_name = $1; + $members = $2; + } + + if ($members) { + my %_members; + + $members =~ s/\s+$//; + + foreach my $arg (split ',', $members) { + $arg =~ s/^\s*(\w+).*/$1/; + push @parameterlist, $arg; + if (!$parameterdescs{$arg}) { + $parameterdescs{$arg} = $undescribed; + if (show_warnings("enum", $declaration_name)) { + print STDERR "${file}:$.: warning: Enum value '$arg' not described in enum '$declaration_name'\n"; + } + } + $_members{$arg} = 1; + } + + while (my ($k, $v) = each %parameterdescs) { + if (!exists($_members{$k})) { + if (show_warnings("enum", $declaration_name)) { + print STDERR "${file}:$.: warning: Excess enum value '$k' description in '$declaration_name'\n"; + } + } + } + + output_declaration($declaration_name, + 'enum', + {'enum' => $declaration_name, + 'module' => $modulename, + 'parameterlist' => \@parameterlist, + 'parameterdescs' => \%parameterdescs, + 'sectionlist' => \@sectionlist, + 'sections' => \%sections, + 'purpose' => $declaration_purpose + }); + } else { + print STDERR "${file}:$.: error: Cannot parse enum!\n"; + ++$errors; + } +} + +my $typedef_type = qr { ((?:\s+[\w\*]+\b){1,8})\s* }x; +my $typedef_ident = qr { \*?\s*(\w\S+)\s* }x; +my $typedef_args = qr { \s*\((.*)\); }x; + +my $typedef1 = qr { typedef$typedef_type\($typedef_ident\)$typedef_args }x; +my $typedef2 = qr { typedef$typedef_type$typedef_ident$typedef_args }x; + +sub dump_typedef($$) { + my $x = shift; + my $file = shift; + + $x =~ s@/\*.*?\*/@@gos; # strip comments. + + # Parse function typedef prototypes + if ($x =~ $typedef1 || $x =~ $typedef2) { + $return_type = $1; + $declaration_name = $2; + my $args = $3; + $return_type =~ s/^\s+//; + + create_parameterlist($args, ',', $file, $declaration_name); + + output_declaration($declaration_name, + 'function', + {'function' => $declaration_name, + 'typedef' => 1, + 'module' => $modulename, + 'functiontype' => $return_type, + 'parameterlist' => \@parameterlist, + 'parameterdescs' => \%parameterdescs, + 'parametertypes' => \%parametertypes, + 'sectionlist' => \@sectionlist, + 'sections' => \%sections, + 'purpose' => $declaration_purpose + }); + return; + } + + while (($x =~ /\(*.\)\s*;$/) || ($x =~ /\[*.\]\s*;$/)) { + $x =~ s/\(*.\)\s*;$/;/; + $x =~ s/\[*.\]\s*;$/;/; + } + + if ($x =~ /typedef.*\s+(\w+)\s*;/) { + $declaration_name = $1; + + output_declaration($declaration_name, + 'typedef', + {'typedef' => $declaration_name, + 'module' => $modulename, + 'sectionlist' => \@sectionlist, + 'sections' => \%sections, + 'purpose' => $declaration_purpose + }); + } + else { + print STDERR "${file}:$.: error: Cannot parse typedef!\n"; + ++$errors; + } +} + +sub save_struct_actual($) { + my $actual = shift; + + # strip all spaces from the actual param so that it looks like one string item + $actual =~ s/\s*//g; + $struct_actual = $struct_actual . $actual . " "; +} + +sub create_parameterlist($$$$) { + my $args = shift; + my $splitter = shift; + my $file = shift; + my $declaration_name = shift; + my $type; + my $param; + + # temporarily replace commas inside function pointer definition + while ($args =~ /(\([^\),]+),/) { + $args =~ s/(\([^\),]+),/$1#/g; + } + + foreach my $arg (split($splitter, $args)) { + # strip comments + $arg =~ s/\/\*.*\*\///; + # strip leading/trailing spaces + $arg =~ s/^\s*//; + $arg =~ s/\s*$//; + $arg =~ s/\s+/ /; + + if ($arg =~ /^#/) { + # Treat preprocessor directive as a typeless variable just to fill + # corresponding data structures "correctly". Catch it later in + # output_* subs. + push_parameter($arg, "", "", $file); + } elsif ($arg =~ m/\(.+\)\s*\(/) { + # pointer-to-function + $arg =~ tr/#/,/; + $arg =~ m/[^\(]+\(\*?\s*([\w\.]*)\s*\)/; + $param = $1; + $type = $arg; + $type =~ s/([^\(]+\(\*?)\s*$param/$1/; + save_struct_actual($param); + push_parameter($param, $type, $arg, $file, $declaration_name); + } elsif ($arg) { + $arg =~ s/\s*:\s*/:/g; + $arg =~ s/\s*\[/\[/g; + + my @args = split('\s*,\s*', $arg); + if ($args[0] =~ m/\*/) { + $args[0] =~ s/(\*+)\s*/ $1/; + } + + my @first_arg; + if ($args[0] =~ /^(.*\s+)(.*?\[.*\].*)$/) { + shift @args; + push(@first_arg, split('\s+', $1)); + push(@first_arg, $2); + } else { + @first_arg = split('\s+', shift @args); + } + + unshift(@args, pop @first_arg); + $type = join " ", @first_arg; + + foreach $param (@args) { + if ($param =~ m/^(\*+)\s*(.*)/) { + save_struct_actual($2); + + push_parameter($2, "$type $1", $arg, $file, $declaration_name); + } + elsif ($param =~ m/(.*?):(\d+)/) { + if ($type ne "") { # skip unnamed bit-fields + save_struct_actual($1); + push_parameter($1, "$type:$2", $arg, $file, $declaration_name) + } + } + else { + save_struct_actual($param); + push_parameter($param, $type, $arg, $file, $declaration_name); + } + } + } + } +} + +sub push_parameter($$$$$) { + my $param = shift; + my $type = shift; + my $org_arg = shift; + my $file = shift; + my $declaration_name = shift; + + if (($anon_struct_union == 1) && ($type eq "") && + ($param eq "}")) { + return; # ignore the ending }; from anon. struct/union + } + + $anon_struct_union = 0; + $param =~ s/[\[\)].*//; + + if ($type eq "" && $param =~ /\.\.\.$/) + { + if (!$param =~ /\w\.\.\.$/) { + # handles unnamed variable parameters + $param = "..."; + } + elsif ($param =~ /\w\.\.\.$/) { + # for named variable parameters of the form `x...`, remove the dots + $param =~ s/\.\.\.$//; + } + if (!defined $parameterdescs{$param} || $parameterdescs{$param} eq "") { + $parameterdescs{$param} = "variable arguments"; + } + } + elsif ($type eq "" && ($param eq "" or $param eq "void")) + { + $param="void"; + $parameterdescs{void} = "no arguments"; + } + elsif ($type eq "" && ($param eq "struct" or $param eq "union")) + # handle unnamed (anonymous) union or struct: + { + $type = $param; + $param = "{unnamed_" . $param . "}"; + $parameterdescs{$param} = "anonymous\n"; + $anon_struct_union = 1; + } + + # warn if parameter has no description + # (but ignore ones starting with # as these are not parameters + # but inline preprocessor statements); + # Note: It will also ignore void params and unnamed structs/unions + if (!defined $parameterdescs{$param} && $param !~ /^#/) { + $parameterdescs{$param} = $undescribed; + + if (show_warnings($type, $declaration_name) && $param !~ /\./) { + print STDERR + "${file}:$.: warning: Function parameter or member '$param' not described in '$declaration_name'\n"; + ++$warnings; + } + } + + # strip spaces from $param so that it is one continuous string + # on @parameterlist; + # this fixes a problem where check_sections() cannot find + # a parameter like "addr[6 + 2]" because it actually appears + # as "addr[6", "+", "2]" on the parameter list; + # but it's better to maintain the param string unchanged for output, + # so just weaken the string compare in check_sections() to ignore + # "[blah" in a parameter string; + ###$param =~ s/\s*//g; + push @parameterlist, $param; + $org_arg =~ s/\s\s+/ /g; + $parametertypes{$param} = $org_arg; +} + +sub check_sections($$$$$) { + my ($file, $decl_name, $decl_type, $sectcheck, $prmscheck) = @_; + my @sects = split ' ', $sectcheck; + my @prms = split ' ', $prmscheck; + my $err; + my ($px, $sx); + my $prm_clean; # strip trailing "[array size]" and/or beginning "*" + + foreach $sx (0 .. $#sects) { + $err = 1; + foreach $px (0 .. $#prms) { + $prm_clean = $prms[$px]; + $prm_clean =~ s/\[.*\]//; + $prm_clean =~ s/__attribute__\s*\(\([a-z,_\*\s\(\)]*\)\)//i; + # ignore array size in a parameter string; + # however, the original param string may contain + # spaces, e.g.: addr[6 + 2] + # and this appears in @prms as "addr[6" since the + # parameter list is split at spaces; + # hence just ignore "[..." for the sections check; + $prm_clean =~ s/\[.*//; + + ##$prm_clean =~ s/^\**//; + if ($prm_clean eq $sects[$sx]) { + $err = 0; + last; + } + } + if ($err) { + if ($decl_type eq "function") { + print STDERR "${file}:$.: warning: " . + "Excess function parameter " . + "'$sects[$sx]' " . + "description in '$decl_name'\n"; + ++$warnings; + } + } + } +} + +## +# Checks the section describing the return value of a function. +sub check_return_section { + my $file = shift; + my $declaration_name = shift; + my $return_type = shift; + + # Ignore an empty return type (It's a macro) + # Ignore functions with a "void" return type. (But don't ignore "void *") + if (($return_type eq "") || ($return_type =~ /void\s*\w*\s*$/)) { + return; + } + + if (!defined($sections{$section_return}) || + $sections{$section_return} eq "") { + print STDERR "${file}:$.: warning: " . + "No description found for return value of " . + "'$declaration_name'\n"; + ++$warnings; + } +} + +## +# takes a function prototype and the name of the current file being +# processed and spits out all the details stored in the global +# arrays/hashes. +sub dump_function($$) { + my $prototype = shift; + my $file = shift; + my $noret = 0; + + print_lineno($new_start_line); + + $prototype =~ s/^static +//; + $prototype =~ s/^extern +//; + $prototype =~ s/^asmlinkage +//; + $prototype =~ s/^inline +//; + $prototype =~ s/^__inline__ +//; + $prototype =~ s/^__inline +//; + $prototype =~ s/^__always_inline +//; + $prototype =~ s/^noinline +//; + $prototype =~ s/__init +//; + $prototype =~ s/__init_or_module +//; + $prototype =~ s/__meminit +//; + $prototype =~ s/__must_check +//; + $prototype =~ s/__weak +//; + $prototype =~ s/__sched +//; + $prototype =~ s/__printf\s*\(\s*\d*\s*,\s*\d*\s*\) +//; + my $define = $prototype =~ s/^#\s*define\s+//; #ak added + $prototype =~ s/__attribute__\s*\(\( + (?: + [\w\s]++ # attribute name + (?:\([^)]*+\))? # attribute arguments + \s*+,? # optional comma at the end + )+ + \)\)\s+//x; + + # Yes, this truly is vile. We are looking for: + # 1. Return type (may be nothing if we're looking at a macro) + # 2. Function name + # 3. Function parameters. + # + # All the while we have to watch out for function pointer parameters + # (which IIRC is what the two sections are for), C types (these + # regexps don't even start to express all the possibilities), and + # so on. + # + # If you mess with these regexps, it's a good idea to check that + # the following functions' documentation still comes out right: + # - parport_register_device (function pointer parameters) + # - atomic_set (macro) + # - pci_match_device, __copy_to_user (long return type) + + if ($define && $prototype =~ m/^()([a-zA-Z0-9_~:]+)\s+/) { + # This is an object-like macro, it has no return type and no parameter + # list. + # Function-like macros are not allowed to have spaces between + # declaration_name and opening parenthesis (notice the \s+). + $return_type = $1; + $declaration_name = $2; + $noret = 1; + } elsif ($prototype =~ m/^()([a-zA-Z0-9_~:]+)\s*\(([^\(]*)\)/ || + $prototype =~ m/^(\w+)\s+([a-zA-Z0-9_~:]+)\s*\(([^\(]*)\)/ || + $prototype =~ m/^(\w+\s*\*+)\s*([a-zA-Z0-9_~:]+)\s*\(([^\(]*)\)/ || + $prototype =~ m/^(\w+\s+\w+)\s+([a-zA-Z0-9_~:]+)\s*\(([^\(]*)\)/ || + $prototype =~ m/^(\w+\s+\w+\s*\*+)\s*([a-zA-Z0-9_~:]+)\s*\(([^\(]*)\)/ || + $prototype =~ m/^(\w+\s+\w+\s+\w+)\s+([a-zA-Z0-9_~:]+)\s*\(([^\(]*)\)/ || + $prototype =~ m/^(\w+\s+\w+\s+\w+\s*\*+)\s*([a-zA-Z0-9_~:]+)\s*\(([^\(]*)\)/ || + $prototype =~ m/^()([a-zA-Z0-9_~:]+)\s*\(([^\{]*)\)/ || + $prototype =~ m/^(\w+)\s+([a-zA-Z0-9_~:]+)\s*\(([^\{]*)\)/ || + $prototype =~ m/^(\w+\s*\*+)\s*([a-zA-Z0-9_~:]+)\s*\(([^\{]*)\)/ || + $prototype =~ m/^(\w+\s+\w+)\s+([a-zA-Z0-9_~:]+)\s*\(([^\{]*)\)/ || + $prototype =~ m/^(\w+\s+\w+\s*\*+)\s*([a-zA-Z0-9_~:]+)\s*\(([^\{]*)\)/ || + $prototype =~ m/^(\w+\s+\w+\s+\w+)\s+([a-zA-Z0-9_~:]+)\s*\(([^\{]*)\)/ || + $prototype =~ m/^(\w+\s+\w+\s+\w+\s*\*+)\s*([a-zA-Z0-9_~:]+)\s*\(([^\{]*)\)/ || + $prototype =~ m/^(\w+\s+\w+\s+\w+\s+\w+)\s+([a-zA-Z0-9_~:]+)\s*\(([^\{]*)\)/ || + $prototype =~ m/^(\w+\s+\w+\s+\w+\s+\w+\s*\*+)\s*([a-zA-Z0-9_~:]+)\s*\(([^\{]*)\)/ || + $prototype =~ m/^(\w+\s+\w+\s*\*+\s*\w+\s*\*+\s*)\s*([a-zA-Z0-9_~:]+)\s*\(([^\{]*)\)/) { + $return_type = $1; + $declaration_name = $2; + my $args = $3; + + create_parameterlist($args, ',', $file, $declaration_name); + } else { + print STDERR "${file}:$.: warning: cannot understand function prototype: '$prototype'\n"; + return; + } + + my $prms = join " ", @parameterlist; + check_sections($file, $declaration_name, "function", $sectcheck, $prms); + + # This check emits a lot of warnings at the moment, because many + # functions don't have a 'Return' doc section. So until the number + # of warnings goes sufficiently down, the check is only performed in + # verbose mode. + # TODO: always perform the check. + if ($verbose && !$noret) { + check_return_section($file, $declaration_name, $return_type); + } + + # The function parser can be called with a typedef parameter. + # Handle it. + if ($return_type =~ /typedef/) { + output_declaration($declaration_name, + 'function', + {'function' => $declaration_name, + 'typedef' => 1, + 'module' => $modulename, + 'functiontype' => $return_type, + 'parameterlist' => \@parameterlist, + 'parameterdescs' => \%parameterdescs, + 'parametertypes' => \%parametertypes, + 'sectionlist' => \@sectionlist, + 'sections' => \%sections, + 'purpose' => $declaration_purpose + }); + } else { + output_declaration($declaration_name, + 'function', + {'function' => $declaration_name, + 'module' => $modulename, + 'functiontype' => $return_type, + 'parameterlist' => \@parameterlist, + 'parameterdescs' => \%parameterdescs, + 'parametertypes' => \%parametertypes, + 'sectionlist' => \@sectionlist, + 'sections' => \%sections, + 'purpose' => $declaration_purpose + }); + } +} + +sub reset_state { + $function = ""; + %parameterdescs = (); + %parametertypes = (); + @parameterlist = (); + %sections = (); + @sectionlist = (); + $sectcheck = ""; + $struct_actual = ""; + $prototype = ""; + + $state = STATE_NORMAL; + $inline_doc_state = STATE_INLINE_NA; +} + +sub tracepoint_munge($) { + my $file = shift; + my $tracepointname = 0; + my $tracepointargs = 0; + + if ($prototype =~ m/TRACE_EVENT\((.*?),/) { + $tracepointname = $1; + } + if ($prototype =~ m/DEFINE_SINGLE_EVENT\((.*?),/) { + $tracepointname = $1; + } + if ($prototype =~ m/DEFINE_EVENT\((.*?),(.*?),/) { + $tracepointname = $2; + } + $tracepointname =~ s/^\s+//; #strip leading whitespace + if ($prototype =~ m/TP_PROTO\((.*?)\)/) { + $tracepointargs = $1; + } + if (($tracepointname eq 0) || ($tracepointargs eq 0)) { + print STDERR "${file}:$.: warning: Unrecognized tracepoint format: \n". + "$prototype\n"; + } else { + $prototype = "static inline void trace_$tracepointname($tracepointargs)"; + } +} + +sub syscall_munge() { + my $void = 0; + + $prototype =~ s@[\r\n]+@ @gos; # strip newlines/CR's +## if ($prototype =~ m/SYSCALL_DEFINE0\s*\(\s*(a-zA-Z0-9_)*\s*\)/) { + if ($prototype =~ m/SYSCALL_DEFINE0/) { + $void = 1; +## $prototype = "long sys_$1(void)"; + } + + $prototype =~ s/SYSCALL_DEFINE.*\(/long sys_/; # fix return type & func name + if ($prototype =~ m/long (sys_.*?),/) { + $prototype =~ s/,/\(/; + } elsif ($void) { + $prototype =~ s/\)/\(void\)/; + } + + # now delete all of the odd-number commas in $prototype + # so that arg types & arg names don't have a comma between them + my $count = 0; + my $len = length($prototype); + if ($void) { + $len = 0; # skip the for-loop + } + for (my $ix = 0; $ix < $len; $ix++) { + if (substr($prototype, $ix, 1) eq ',') { + $count++; + if ($count % 2 == 1) { + substr($prototype, $ix, 1) = ' '; + } + } + } +} + +sub process_proto_function($$) { + my $x = shift; + my $file = shift; + + $x =~ s@\/\/.*$@@gos; # strip C99-style comments to end of line + + if ($x =~ m#\s*/\*\s+MACDOC\s*#io || ($x =~ /^#/ && $x !~ /^#\s*define/)) { + # do nothing + } + elsif ($x =~ /([^\{]*)/) { + $prototype .= $1; + } + + if (($x =~ /\{/) || ($x =~ /\#\s*define/) || ($x =~ /;/)) { + $prototype =~ s@/\*.*?\*/@@gos; # strip comments. + $prototype =~ s@[\r\n]+@ @gos; # strip newlines/cr's. + $prototype =~ s@^\s+@@gos; # strip leading spaces + + # Handle prototypes for function pointers like: + # int (*pcs_config)(struct foo) + $prototype =~ s@^(\S+\s+)\(\s*\*(\S+)\)@$1$2@gos; + + if ($prototype =~ /SYSCALL_DEFINE/) { + syscall_munge(); + } + if ($prototype =~ /TRACE_EVENT/ || $prototype =~ /DEFINE_EVENT/ || + $prototype =~ /DEFINE_SINGLE_EVENT/) + { + tracepoint_munge($file); + } + dump_function($prototype, $file); + reset_state(); + } +} + +sub process_proto_type($$) { + my $x = shift; + my $file = shift; + + $x =~ s@[\r\n]+@ @gos; # strip newlines/cr's. + $x =~ s@^\s+@@gos; # strip leading spaces + $x =~ s@\s+$@@gos; # strip trailing spaces + $x =~ s@\/\/.*$@@gos; # strip C99-style comments to end of line + + if ($x =~ /^#/) { + # To distinguish preprocessor directive from regular declaration later. + $x .= ";"; + } + + while (1) { + if ( $x =~ /([^\{\};]*)([\{\};])(.*)/ ) { + if( length $prototype ) { + $prototype .= " " + } + $prototype .= $1 . $2; + ($2 eq '{') && $brcount++; + ($2 eq '}') && $brcount--; + if (($2 eq ';') && ($brcount == 0)) { + dump_declaration($prototype, $file); + reset_state(); + last; + } + $x = $3; + } else { + $prototype .= $x; + last; + } + } +} + + +sub map_filename($) { + my $file; + my ($orig_file) = @_; + + if (defined($ENV{'SRCTREE'})) { + $file = "$ENV{'SRCTREE'}" . "/" . $orig_file; + } else { + $file = $orig_file; + } + + if (defined($source_map{$file})) { + $file = $source_map{$file}; + } + + return $file; +} + +sub process_export_file($) { + my ($orig_file) = @_; + my $file = map_filename($orig_file); + + if (!open(IN,"<$file")) { + print STDERR "Error: Cannot open file $file\n"; + ++$errors; + return; + } + + while (<IN>) { + if (/$export_symbol/) { + next if (defined($nosymbol_table{$2})); + $function_table{$2} = 1; + } + } + + close(IN); +} + +# +# Parsers for the various processing states. +# +# STATE_NORMAL: looking for the /** to begin everything. +# +sub process_normal() { + if (/$doc_start/o) { + $state = STATE_NAME; # next line is always the function name + $in_doc_sect = 0; + $declaration_start_line = $. + 1; + } +} + +# +# STATE_NAME: Looking for the "name - description" line +# +sub process_name($$) { + my $file = shift; + my $identifier; + my $descr; + + if (/$doc_block/o) { + $state = STATE_DOCBLOCK; + $contents = ""; + $new_start_line = $.; + + if ( $1 eq "" ) { + $section = $section_intro; + } else { + $section = $1; + } + } + elsif (/$doc_decl/o) { + $identifier = $1; + if (/\s*([\w\s]+?)(\(\))?\s*-/) { + $identifier = $1; + } + + $state = STATE_BODY; + # if there's no @param blocks need to set up default section + # here + $contents = ""; + $section = $section_default; + $new_start_line = $. + 1; + if (/-(.*)/) { + # strip leading/trailing/multiple spaces + $descr= $1; + $descr =~ s/^\s*//; + $descr =~ s/\s*$//; + $descr =~ s/\s+/ /g; + $declaration_purpose = $descr; + $state = STATE_BODY_MAYBE; + } else { + $declaration_purpose = ""; + } + + if (($declaration_purpose eq "") && $verbose) { + print STDERR "${file}:$.: warning: missing initial short description on line:\n"; + print STDERR $_; + ++$warnings; + } + + if ($identifier =~ m/^struct\b/) { + $decl_type = 'struct'; + } elsif ($identifier =~ m/^union\b/) { + $decl_type = 'union'; + } elsif ($identifier =~ m/^enum\b/) { + $decl_type = 'enum'; + } elsif ($identifier =~ m/^typedef\b/) { + $decl_type = 'typedef'; + } else { + $decl_type = 'function'; + } + + if ($verbose) { + print STDERR "${file}:$.: info: Scanning doc for $identifier\n"; + } + } else { + print STDERR "${file}:$.: warning: Cannot understand $_ on line $.", + " - I thought it was a doc line\n"; + ++$warnings; + $state = STATE_NORMAL; + } +} + + +# +# STATE_BODY and STATE_BODY_MAYBE: the bulk of a kerneldoc comment. +# +sub process_body($$) { + my $file = shift; + + # Until all named variable macro parameters are + # documented using the bare name (`x`) rather than with + # dots (`x...`), strip the dots: + if ($section =~ /\w\.\.\.$/) { + $section =~ s/\.\.\.$//; + + if ($verbose) { + print STDERR "${file}:$.: warning: Variable macro arguments should be documented without dots\n"; + ++$warnings; + } + } + + if ($state == STATE_BODY_WITH_BLANK_LINE && /^\s*\*\s?\S/) { + dump_section($file, $section, $contents); + $section = $section_default; + $new_start_line = $.; + $contents = ""; + } + + if (/$doc_sect/i) { # case insensitive for supported section names + $newsection = $1; + $newcontents = $2; + + # map the supported section names to the canonical names + if ($newsection =~ m/^description$/i) { + $newsection = $section_default; + } elsif ($newsection =~ m/^context$/i) { + $newsection = $section_context; + } elsif ($newsection =~ m/^returns?$/i) { + $newsection = $section_return; + } elsif ($newsection =~ m/^\@return$/) { + # special: @return is a section, not a param description + $newsection = $section_return; + } + + if (($contents ne "") && ($contents ne "\n")) { + if (!$in_doc_sect && $verbose) { + print STDERR "${file}:$.: warning: contents before sections\n"; + ++$warnings; + } + dump_section($file, $section, $contents); + $section = $section_default; + } + + $in_doc_sect = 1; + $state = STATE_BODY; + $contents = $newcontents; + $new_start_line = $.; + while (substr($contents, 0, 1) eq " ") { + $contents = substr($contents, 1); + } + if ($contents ne "") { + $contents .= "\n"; + } + $section = $newsection; + $leading_space = undef; + } elsif (/$doc_end/) { + if (($contents ne "") && ($contents ne "\n")) { + dump_section($file, $section, $contents); + $section = $section_default; + $contents = ""; + } + # look for doc_com + <text> + doc_end: + if ($_ =~ m'\s*\*\s*[a-zA-Z_0-9:\.]+\*/') { + print STDERR "${file}:$.: warning: suspicious ending line: $_"; + ++$warnings; + } + + $prototype = ""; + $state = STATE_PROTO; + $brcount = 0; + $new_start_line = $. + 1; + } elsif (/$doc_content/) { + if ($1 eq "") { + if ($section eq $section_context) { + dump_section($file, $section, $contents); + $section = $section_default; + $contents = ""; + $new_start_line = $.; + $state = STATE_BODY; + } else { + if ($section ne $section_default) { + $state = STATE_BODY_WITH_BLANK_LINE; + } else { + $state = STATE_BODY; + } + $contents .= "\n"; + } + } elsif ($state == STATE_BODY_MAYBE) { + # Continued declaration purpose + chomp($declaration_purpose); + $declaration_purpose .= " " . $1; + $declaration_purpose =~ s/\s+/ /g; + } else { + my $cont = $1; + if ($section =~ m/^@/ || $section eq $section_context) { + if (!defined $leading_space) { + if ($cont =~ m/^(\s+)/) { + $leading_space = $1; + } else { + $leading_space = ""; + } + } + $cont =~ s/^$leading_space//; + } + $contents .= $cont . "\n"; + } + } else { + # i dont know - bad line? ignore. + print STDERR "${file}:$.: warning: bad line: $_"; + ++$warnings; + } +} + + +# +# STATE_PROTO: reading a function/whatever prototype. +# +sub process_proto($$) { + my $file = shift; + + if (/$doc_inline_oneline/) { + $section = $1; + $contents = $2; + if ($contents ne "") { + $contents .= "\n"; + dump_section($file, $section, $contents); + $section = $section_default; + $contents = ""; + } + } elsif (/$doc_inline_start/) { + $state = STATE_INLINE; + $inline_doc_state = STATE_INLINE_NAME; + } elsif ($decl_type eq 'function') { + process_proto_function($_, $file); + } else { + process_proto_type($_, $file); + } +} + +# +# STATE_DOCBLOCK: within a DOC: block. +# +sub process_docblock($$) { + my $file = shift; + + if (/$doc_end/) { + dump_doc_section($file, $section, $contents); + $section = $section_default; + $contents = ""; + $function = ""; + %parameterdescs = (); + %parametertypes = (); + @parameterlist = (); + %sections = (); + @sectionlist = (); + $prototype = ""; + $state = STATE_NORMAL; + } elsif (/$doc_content/) { + if ( $1 eq "" ) { + $contents .= $blankline; + } else { + $contents .= $1 . "\n"; + } + } +} + +# +# STATE_INLINE: docbook comments within a prototype. +# +sub process_inline($$) { + my $file = shift; + + # First line (state 1) needs to be a @parameter + if ($inline_doc_state == STATE_INLINE_NAME && /$doc_inline_sect/o) { + $section = $1; + $contents = $2; + $new_start_line = $.; + if ($contents ne "") { + while (substr($contents, 0, 1) eq " ") { + $contents = substr($contents, 1); + } + $contents .= "\n"; + } + $inline_doc_state = STATE_INLINE_TEXT; + # Documentation block end */ + } elsif (/$doc_inline_end/) { + if (($contents ne "") && ($contents ne "\n")) { + dump_section($file, $section, $contents); + $section = $section_default; + $contents = ""; + } + $state = STATE_PROTO; + $inline_doc_state = STATE_INLINE_NA; + # Regular text + } elsif (/$doc_content/) { + if ($inline_doc_state == STATE_INLINE_TEXT) { + $contents .= $1 . "\n"; + # nuke leading blank lines + if ($contents =~ /^\s*$/) { + $contents = ""; + } + } elsif ($inline_doc_state == STATE_INLINE_NAME) { + $inline_doc_state = STATE_INLINE_ERROR; + print STDERR "${file}:$.: warning: "; + print STDERR "Incorrect use of kernel-doc format: $_"; + ++$warnings; + } + } +} + + +sub process_file($) { + my $file; + my $initial_section_counter = $section_counter; + my ($orig_file) = @_; + + $file = map_filename($orig_file); + + if (!open(IN_FILE,"<$file")) { + print STDERR "Error: Cannot open file $file\n"; + ++$errors; + return; + } + + $. = 1; + + $section_counter = 0; + while (<IN_FILE>) { + while (s/\\\s*$//) { + $_ .= <IN_FILE>; + } + # Replace tabs by spaces + while ($_ =~ s/\t+/' ' x (length($&) * 8 - length($`) % 8)/e) {}; + # Hand this line to the appropriate state handler + if ($state == STATE_NORMAL) { + process_normal(); + } elsif ($state == STATE_NAME) { + process_name($file, $_); + } elsif ($state == STATE_BODY || $state == STATE_BODY_MAYBE || + $state == STATE_BODY_WITH_BLANK_LINE) { + process_body($file, $_); + } elsif ($state == STATE_INLINE) { # scanning for inline parameters + process_inline($file, $_); + } elsif ($state == STATE_PROTO) { + process_proto($file, $_); + } elsif ($state == STATE_DOCBLOCK) { + process_docblock($file, $_); + } + } + + # Make sure we got something interesting. + if ($initial_section_counter == $section_counter && $ + output_mode ne "none") { + if ($output_selection == OUTPUT_INCLUDE) { + print STDERR "${file}:1: warning: '$_' not found\n" + for keys %function_table; + } + else { + print STDERR "${file}:1: warning: no structured comments found\n"; + } + } + close IN_FILE; +} + + +if ($output_mode eq "rst") { + get_sphinx_version() if (!$sphinx_major); +} + +$kernelversion = get_kernel_version(); + +# generate a sequence of code that will splice in highlighting information +# using the s// operator. +for (my $k = 0; $k < @highlights; $k++) { + my $pattern = $highlights[$k][0]; + my $result = $highlights[$k][1]; +# print STDERR "scanning pattern:$pattern, highlight:($result)\n"; + $dohighlight .= "\$contents =~ s:$pattern:$result:gs;\n"; +} + +# Read the file that maps relative names to absolute names for +# separate source and object directories and for shadow trees. +if (open(SOURCE_MAP, "<.tmp_filelist.txt")) { + my ($relname, $absname); + while(<SOURCE_MAP>) { + chop(); + ($relname, $absname) = (split())[0..1]; + $relname =~ s:^/+::; + $source_map{$relname} = $absname; + } + close(SOURCE_MAP); +} + +if ($output_selection == OUTPUT_EXPORTED || + $output_selection == OUTPUT_INTERNAL) { + + push(@export_file_list, @ARGV); + + foreach (@export_file_list) { + chomp; + process_export_file($_); + } +} + +foreach (@ARGV) { + chomp; + process_file($_); +} +if ($verbose && $errors) { + print STDERR "$errors errors\n"; +} +if ($verbose && $warnings) { + print STDERR "$warnings warnings\n"; +} + +if ($Werror && $warnings) { + print STDERR "$warnings warnings as Errors\n"; + exit($warnings); +} else { + exit($output_mode eq "none" ? 0 : $errors) +} diff --git a/src/net/scripts/ksymoops/README b/src/net/scripts/ksymoops/README new file mode 100644 index 0000000..4130439 --- /dev/null +++ b/src/net/scripts/ksymoops/README @@ -0,0 +1,7 @@ +ksymoops has been removed from the kernel. It was always meant to be a +free standing utility, not linked to any particular kernel version. +The latest version can be found in +https://www.kernel.org/pub/linux/utils/kernel/ksymoops together with patches to +other utilities in order to give more accurate Oops debugging. + +Keith Owens <kaos@ocs.com.au> Sat Jun 19 10:30:34 EST 1999 diff --git a/src/net/scripts/ld-version.sh b/src/net/scripts/ld-version.sh new file mode 100755 index 0000000..f2be0ff --- /dev/null +++ b/src/net/scripts/ld-version.sh @@ -0,0 +1,11 @@ +#!/usr/bin/awk -f +# SPDX-License-Identifier: GPL-2.0 +# extract linker version number from stdin and turn into single number + { + gsub(".*\\)", ""); + gsub(".*version ", ""); + gsub("-.*", ""); + split($1,a, "."); + print a[1]*100000000 + a[2]*1000000 + a[3]*10000; + exit + } diff --git a/src/net/scripts/leaking_addresses.pl b/src/net/scripts/leaking_addresses.pl new file mode 100755 index 0000000..8f636a2 --- /dev/null +++ b/src/net/scripts/leaking_addresses.pl @@ -0,0 +1,647 @@ +#!/usr/bin/env perl +# SPDX-License-Identifier: GPL-2.0-only +# +# (c) 2017 Tobin C. Harding <me@tobin.cc> +# +# leaking_addresses.pl: Scan the kernel for potential leaking addresses. +# - Scans dmesg output. +# - Walks directory tree and parses each file (for each directory in @DIRS). +# +# Use --debug to output path before parsing, this is useful to find files that +# cause the script to choke. + +# +# When the system is idle it is likely that most files under /proc/PID will be +# identical for various processes. Scanning _all_ the PIDs under /proc is +# unnecessary and implies that we are thoroughly scanning /proc. This is _not_ +# the case because there may be ways userspace can trigger creation of /proc +# files that leak addresses but were not present during a scan. For these two +# reasons we exclude all PID directories under /proc except '1/' + +use warnings; +use strict; +use POSIX; +use File::Basename; +use File::Spec; +use Cwd 'abs_path'; +use Term::ANSIColor qw(:constants); +use Getopt::Long qw(:config no_auto_abbrev); +use Config; +use bigint qw/hex/; +use feature 'state'; + +my $P = $0; + +# Directories to scan. +my @DIRS = ('/proc', '/sys'); + +# Timer for parsing each file, in seconds. +my $TIMEOUT = 10; + +# Kernel addresses vary by architecture. We can only auto-detect the following +# architectures (using `uname -m`). (flag --32-bit overrides auto-detection.) +my @SUPPORTED_ARCHITECTURES = ('x86_64', 'ppc64', 'x86'); + +# Command line options. +my $help = 0; +my $debug = 0; +my $raw = 0; +my $output_raw = ""; # Write raw results to file. +my $input_raw = ""; # Read raw results from file instead of scanning. +my $suppress_dmesg = 0; # Don't show dmesg in output. +my $squash_by_path = 0; # Summary report grouped by absolute path. +my $squash_by_filename = 0; # Summary report grouped by filename. +my $kernel_config_file = ""; # Kernel configuration file. +my $opt_32bit = 0; # Scan 32-bit kernel. +my $page_offset_32bit = 0; # Page offset for 32-bit kernel. + +# Skip these absolute paths. +my @skip_abs = ( + '/proc/kmsg', + '/proc/device-tree', + '/proc/1/syscall', + '/sys/firmware/devicetree', + '/sys/kernel/debug/tracing/trace_pipe', + '/sys/kernel/security/apparmor/revision'); + +# Skip these under any subdirectory. +my @skip_any = ( + 'pagemap', + 'events', + 'access', + 'registers', + 'snapshot_raw', + 'trace_pipe_raw', + 'ptmx', + 'trace_pipe', + 'fd', + 'usbmon'); + +sub help +{ + my ($exitcode) = @_; + + print << "EOM"; + +Usage: $P [OPTIONS] + +Options: + + -o, --output-raw=<file> Save results for future processing. + -i, --input-raw=<file> Read results from file instead of scanning. + --raw Show raw results (default). + --suppress-dmesg Do not show dmesg results. + --squash-by-path Show one result per unique path. + --squash-by-filename Show one result per unique filename. + --kernel-config-file=<file> Kernel configuration file (e.g /boot/config) + --32-bit Scan 32-bit kernel. + --page-offset-32-bit=o Page offset (for 32-bit kernel 0xABCD1234). + -d, --debug Display debugging output. + -h, --help Display this help and exit. + +Scans the running kernel for potential leaking addresses. + +EOM + exit($exitcode); +} + +GetOptions( + 'd|debug' => \$debug, + 'h|help' => \$help, + 'o|output-raw=s' => \$output_raw, + 'i|input-raw=s' => \$input_raw, + 'suppress-dmesg' => \$suppress_dmesg, + 'squash-by-path' => \$squash_by_path, + 'squash-by-filename' => \$squash_by_filename, + 'raw' => \$raw, + 'kernel-config-file=s' => \$kernel_config_file, + '32-bit' => \$opt_32bit, + 'page-offset-32-bit=o' => \$page_offset_32bit, +) or help(1); + +help(0) if ($help); + +if ($input_raw) { + format_output($input_raw); + exit(0); +} + +if (!$input_raw and ($squash_by_path or $squash_by_filename)) { + printf "\nSummary reporting only available with --input-raw=<file>\n"; + printf "(First run scan with --output-raw=<file>.)\n"; + exit(128); +} + +if (!(is_supported_architecture() or $opt_32bit or $page_offset_32bit)) { + printf "\nScript does not support your architecture, sorry.\n"; + printf "\nCurrently we support: \n\n"; + foreach(@SUPPORTED_ARCHITECTURES) { + printf "\t%s\n", $_; + } + printf("\n"); + + printf("If you are running a 32-bit architecture you may use:\n"); + printf("\n\t--32-bit or --page-offset-32-bit=<page offset>\n\n"); + + my $archname = `uname -m`; + printf("Machine hardware name (`uname -m`): %s\n", $archname); + + exit(129); +} + +if ($output_raw) { + open my $fh, '>', $output_raw or die "$0: $output_raw: $!\n"; + select $fh; +} + +parse_dmesg(); +walk(@DIRS); + +exit 0; + +sub dprint +{ + printf(STDERR @_) if $debug; +} + +sub is_supported_architecture +{ + return (is_x86_64() or is_ppc64() or is_ix86_32()); +} + +sub is_32bit +{ + # Allow --32-bit or --page-offset-32-bit to override + if ($opt_32bit or $page_offset_32bit) { + return 1; + } + + return is_ix86_32(); +} + +sub is_ix86_32 +{ + state $arch = `uname -m`; + + chomp $arch; + if ($arch =~ m/i[3456]86/) { + return 1; + } + return 0; +} + +sub is_arch +{ + my ($desc) = @_; + my $arch = `uname -m`; + + chomp $arch; + if ($arch eq $desc) { + return 1; + } + return 0; +} + +sub is_x86_64 +{ + state $is = is_arch('x86_64'); + return $is; +} + +sub is_ppc64 +{ + state $is = is_arch('ppc64'); + return $is; +} + +# Gets config option value from kernel config file. +# Returns "" on error or if config option not found. +sub get_kernel_config_option +{ + my ($option) = @_; + my $value = ""; + my $tmp_file = ""; + my @config_files; + + # Allow --kernel-config-file to override. + if ($kernel_config_file ne "") { + @config_files = ($kernel_config_file); + } elsif (-R "/proc/config.gz") { + my $tmp_file = "/tmp/tmpkconf"; + + if (system("gunzip < /proc/config.gz > $tmp_file")) { + dprint("system(gunzip < /proc/config.gz) failed\n"); + return ""; + } else { + @config_files = ($tmp_file); + } + } else { + my $file = '/boot/config-' . `uname -r`; + chomp $file; + @config_files = ($file, '/boot/config'); + } + + foreach my $file (@config_files) { + dprint("parsing config file: $file\n"); + $value = option_from_file($option, $file); + if ($value ne "") { + last; + } + } + + if ($tmp_file ne "") { + system("rm -f $tmp_file"); + } + + return $value; +} + +# Parses $file and returns kernel configuration option value. +sub option_from_file +{ + my ($option, $file) = @_; + my $str = ""; + my $val = ""; + + open(my $fh, "<", $file) or return ""; + while (my $line = <$fh> ) { + if ($line =~ /^$option/) { + ($str, $val) = split /=/, $line; + chomp $val; + last; + } + } + + close $fh; + return $val; +} + +sub is_false_positive +{ + my ($match) = @_; + + if (is_32bit()) { + return is_false_positive_32bit($match); + } + + # 64 bit false positives. + + if ($match =~ '\b(0x)?(f|F){16}\b' or + $match =~ '\b(0x)?0{16}\b') { + return 1; + } + + if (is_x86_64() and is_in_vsyscall_memory_region($match)) { + return 1; + } + + return 0; +} + +sub is_false_positive_32bit +{ + my ($match) = @_; + state $page_offset = get_page_offset(); + + if ($match =~ '\b(0x)?(f|F){8}\b') { + return 1; + } + + if (hex($match) < $page_offset) { + return 1; + } + + return 0; +} + +# returns integer value +sub get_page_offset +{ + my $page_offset; + my $default_offset = 0xc0000000; + + # Allow --page-offset-32bit to override. + if ($page_offset_32bit != 0) { + return $page_offset_32bit; + } + + $page_offset = get_kernel_config_option('CONFIG_PAGE_OFFSET'); + if (!$page_offset) { + return $default_offset; + } + return $page_offset; +} + +sub is_in_vsyscall_memory_region +{ + my ($match) = @_; + + my $hex = hex($match); + my $region_min = hex("0xffffffffff600000"); + my $region_max = hex("0xffffffffff601000"); + + return ($hex >= $region_min and $hex <= $region_max); +} + +# True if argument potentially contains a kernel address. +sub may_leak_address +{ + my ($line) = @_; + my $address_re; + + # Signal masks. + if ($line =~ '^SigBlk:' or + $line =~ '^SigIgn:' or + $line =~ '^SigCgt:') { + return 0; + } + + if ($line =~ '\bKEY=[[:xdigit:]]{14} [[:xdigit:]]{16} [[:xdigit:]]{16}\b' or + $line =~ '\b[[:xdigit:]]{14} [[:xdigit:]]{16} [[:xdigit:]]{16}\b') { + return 0; + } + + $address_re = get_address_re(); + while ($line =~ /($address_re)/g) { + if (!is_false_positive($1)) { + return 1; + } + } + + return 0; +} + +sub get_address_re +{ + if (is_ppc64()) { + return '\b(0x)?[89abcdef]00[[:xdigit:]]{13}\b'; + } elsif (is_32bit()) { + return '\b(0x)?[[:xdigit:]]{8}\b'; + } + + return get_x86_64_re(); +} + +sub get_x86_64_re +{ + # We handle page table levels but only if explicitly configured using + # CONFIG_PGTABLE_LEVELS. If config file parsing fails or config option + # is not found we default to using address regular expression suitable + # for 4 page table levels. + state $ptl = get_kernel_config_option('CONFIG_PGTABLE_LEVELS'); + + if ($ptl == 5) { + return '\b(0x)?ff[[:xdigit:]]{14}\b'; + } + return '\b(0x)?ffff[[:xdigit:]]{12}\b'; +} + +sub parse_dmesg +{ + open my $cmd, '-|', 'dmesg'; + while (<$cmd>) { + if (may_leak_address($_)) { + print 'dmesg: ' . $_; + } + } + close $cmd; +} + +# True if we should skip this path. +sub skip +{ + my ($path) = @_; + + foreach (@skip_abs) { + return 1 if (/^$path$/); + } + + my($filename, $dirs, $suffix) = fileparse($path); + foreach (@skip_any) { + return 1 if (/^$filename$/); + } + + return 0; +} + +sub timed_parse_file +{ + my ($file) = @_; + + eval { + local $SIG{ALRM} = sub { die "alarm\n" }; # NB: \n required. + alarm $TIMEOUT; + parse_file($file); + alarm 0; + }; + + if ($@) { + die unless $@ eq "alarm\n"; # Propagate unexpected errors. + printf STDERR "timed out parsing: %s\n", $file; + } +} + +sub parse_file +{ + my ($file) = @_; + + if (! -R $file) { + return; + } + + if (! -T $file) { + return; + } + + open my $fh, "<", $file or return; + while ( <$fh> ) { + chomp; + if (may_leak_address($_)) { + printf("$file: $_\n"); + } + } + close $fh; +} + +# Checks if the actual path name is leaking a kernel address. +sub check_path_for_leaks +{ + my ($path) = @_; + + if (may_leak_address($path)) { + printf("Path name may contain address: $path\n"); + } +} + +# Recursively walk directory tree. +sub walk +{ + my @dirs = @_; + + while (my $pwd = shift @dirs) { + next if (!opendir(DIR, $pwd)); + my @files = readdir(DIR); + closedir(DIR); + + foreach my $file (@files) { + next if ($file eq '.' or $file eq '..'); + + my $path = "$pwd/$file"; + next if (-l $path); + + # skip /proc/PID except /proc/1 + next if (($path =~ /^\/proc\/[0-9]+$/) && + ($path !~ /^\/proc\/1$/)); + + next if (skip($path)); + + check_path_for_leaks($path); + + if (-d $path) { + push @dirs, $path; + next; + } + + dprint("parsing: $path\n"); + timed_parse_file($path); + } + } +} + +sub format_output +{ + my ($file) = @_; + + # Default is to show raw results. + if ($raw or (!$squash_by_path and !$squash_by_filename)) { + dump_raw_output($file); + return; + } + + my ($total, $dmesg, $paths, $files) = parse_raw_file($file); + + printf "\nTotal number of results from scan (incl dmesg): %d\n", $total; + + if (!$suppress_dmesg) { + print_dmesg($dmesg); + } + + if ($squash_by_filename) { + squash_by($files, 'filename'); + } + + if ($squash_by_path) { + squash_by($paths, 'path'); + } +} + +sub dump_raw_output +{ + my ($file) = @_; + + open (my $fh, '<', $file) or die "$0: $file: $!\n"; + while (<$fh>) { + if ($suppress_dmesg) { + if ("dmesg:" eq substr($_, 0, 6)) { + next; + } + } + print $_; + } + close $fh; +} + +sub parse_raw_file +{ + my ($file) = @_; + + my $total = 0; # Total number of lines parsed. + my @dmesg; # dmesg output. + my %files; # Unique filenames containing leaks. + my %paths; # Unique paths containing leaks. + + open (my $fh, '<', $file) or die "$0: $file: $!\n"; + while (my $line = <$fh>) { + $total++; + + if ("dmesg:" eq substr($line, 0, 6)) { + push @dmesg, $line; + next; + } + + cache_path(\%paths, $line); + cache_filename(\%files, $line); + } + + return $total, \@dmesg, \%paths, \%files; +} + +sub print_dmesg +{ + my ($dmesg) = @_; + + print "\ndmesg output:\n"; + + if (@$dmesg == 0) { + print "<no results>\n"; + return; + } + + foreach(@$dmesg) { + my $index = index($_, ': '); + $index += 2; # skid ': ' + print substr($_, $index); + } +} + +sub squash_by +{ + my ($ref, $desc) = @_; + + print "\nResults squashed by $desc (excl dmesg). "; + print "Displaying [<number of results> <$desc>], <example result>\n"; + + if (keys %$ref == 0) { + print "<no results>\n"; + return; + } + + foreach(keys %$ref) { + my $lines = $ref->{$_}; + my $length = @$lines; + printf "[%d %s] %s", $length, $_, @$lines[0]; + } +} + +sub cache_path +{ + my ($paths, $line) = @_; + + my $index = index($line, ': '); + my $path = substr($line, 0, $index); + + $index += 2; # skip ': ' + add_to_cache($paths, $path, substr($line, $index)); +} + +sub cache_filename +{ + my ($files, $line) = @_; + + my $index = index($line, ': '); + my $path = substr($line, 0, $index); + my $filename = basename($path); + + $index += 2; # skip ': ' + add_to_cache($files, $filename, substr($line, $index)); +} + +sub add_to_cache +{ + my ($cache, $key, $value) = @_; + + if (!$cache->{$key}) { + $cache->{$key} = (); + } + push @{$cache->{$key}}, $value; +} diff --git a/src/net/scripts/link-vmlinux.sh b/src/net/scripts/link-vmlinux.sh new file mode 100755 index 0000000..22b6ca8 --- /dev/null +++ b/src/net/scripts/link-vmlinux.sh @@ -0,0 +1,375 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0 +# +# link vmlinux +# +# vmlinux is linked from the objects selected by $(KBUILD_VMLINUX_OBJS) and +# $(KBUILD_VMLINUX_LIBS). Most are built-in.a files from top-level directories +# in the kernel tree, others are specified in arch/$(ARCH)/Makefile. +# $(KBUILD_VMLINUX_LIBS) are archives which are linked conditionally +# (not within --whole-archive), and do not require symbol indexes added. +# +# vmlinux +# ^ +# | +# +--< $(KBUILD_VMLINUX_OBJS) +# | +--< init/built-in.a drivers/built-in.a mm/built-in.a + more +# | +# +--< $(KBUILD_VMLINUX_LIBS) +# | +--< lib/lib.a + more +# | +# +-< ${kallsymso} (see description in KALLSYMS section) +# +# vmlinux version (uname -v) cannot be updated during normal +# descending-into-subdirs phase since we do not yet know if we need to +# update vmlinux. +# Therefore this step is delayed until just before final link of vmlinux. +# +# System.map is generated to document addresses of all kernel symbols + +# Error out on error +set -e + +LD="$1" +KBUILD_LDFLAGS="$2" +LDFLAGS_vmlinux="$3" + +# Nice output in kbuild format +# Will be supressed by "make -s" +info() +{ + if [ "${quiet}" != "silent_" ]; then + printf " %-7s %s\n" "${1}" "${2}" + fi +} + +# Link of vmlinux.o used for section mismatch analysis +# ${1} output file +modpost_link() +{ + local objects + + objects="--whole-archive \ + ${KBUILD_VMLINUX_OBJS} \ + --no-whole-archive \ + --start-group \ + ${KBUILD_VMLINUX_LIBS} \ + --end-group" + + ${LD} ${KBUILD_LDFLAGS} -r -o ${1} ${objects} +} + +objtool_link() +{ + local objtoolopt; + + if [ -n "${CONFIG_VMLINUX_VALIDATION}" ]; then + objtoolopt="check" + if [ -n "${CONFIG_CPU_UNRET_ENTRY}" ]; then + objtoolopt="${objtoolopt} --unret" + fi + if [ -z "${CONFIG_FRAME_POINTER}" ]; then + objtoolopt="${objtoolopt} --no-fp" + fi + if [ -n "${CONFIG_GCOV_KERNEL}" ]; then + objtoolopt="${objtoolopt} --no-unreachable" + fi + if [ -n "${CONFIG_RETPOLINE}" ]; then + objtoolopt="${objtoolopt} --retpoline" + fi + if [ -n "${CONFIG_X86_SMAP}" ]; then + objtoolopt="${objtoolopt} --uaccess" + fi + if [ -n "${CONFIG_SLS}" ]; then + objtoolopt="${objtoolopt} --sls" + fi + info OBJTOOL ${1} + tools/objtool/objtool ${objtoolopt} ${1} + fi +} + +# Link of vmlinux +# ${1} - output file +# ${2}, ${3}, ... - optional extra .o files +vmlinux_link() +{ + local lds="${objtree}/${KBUILD_LDS}" + local output=${1} + local objects + local strip_debug + + info LD ${output} + + # skip output file argument + shift + + # The kallsyms linking does not need debug symbols included. + if [ "$output" != "${output#.tmp_vmlinux.kallsyms}" ] ; then + strip_debug=-Wl,--strip-debug + fi + + if [ "${SRCARCH}" != "um" ]; then + objects="--whole-archive \ + ${KBUILD_VMLINUX_OBJS} \ + --no-whole-archive \ + --start-group \ + ${KBUILD_VMLINUX_LIBS} \ + --end-group \ + ${@}" + + ${LD} ${KBUILD_LDFLAGS} ${LDFLAGS_vmlinux} \ + ${strip_debug#-Wl,} \ + -o ${output} \ + -T ${lds} ${objects} + else + objects="-Wl,--whole-archive \ + ${KBUILD_VMLINUX_OBJS} \ + -Wl,--no-whole-archive \ + -Wl,--start-group \ + ${KBUILD_VMLINUX_LIBS} \ + -Wl,--end-group \ + ${@}" + + ${CC} ${CFLAGS_vmlinux} \ + ${strip_debug} \ + -o ${output} \ + -Wl,-T,${lds} \ + ${objects} \ + -lutil -lrt -lpthread + rm -f linux + fi +} + +# generate .BTF typeinfo from DWARF debuginfo +# ${1} - vmlinux image +# ${2} - file to dump raw BTF data into +gen_btf() +{ + local pahole_ver + + if ! [ -x "$(command -v ${PAHOLE})" ]; then + echo >&2 "BTF: ${1}: pahole (${PAHOLE}) is not available" + return 1 + fi + + pahole_ver=$(${PAHOLE} --version | sed -E 's/v([0-9]+)\.([0-9]+)/\1\2/') + if [ "${pahole_ver}" -lt "116" ]; then + echo >&2 "BTF: ${1}: pahole version $(${PAHOLE} --version) is too old, need at least v1.16" + return 1 + fi + + vmlinux_link ${1} + + info "BTF" ${2} + LLVM_OBJCOPY="${OBJCOPY}" ${PAHOLE} -J ${PAHOLE_FLAGS} ${1} + + # Create ${2} which contains just .BTF section but no symbols. Add + # SHF_ALLOC because .BTF will be part of the vmlinux image. --strip-all + # deletes all symbols including __start_BTF and __stop_BTF, which will + # be redefined in the linker script. Add 2>/dev/null to suppress GNU + # objcopy warnings: "empty loadable segment detected at ..." + ${OBJCOPY} --only-section=.BTF --set-section-flags .BTF=alloc,readonly \ + --strip-all ${1} ${2} 2>/dev/null + # Change e_type to ET_REL so that it can be used to link final vmlinux. + # Unlike GNU ld, lld does not allow an ET_EXEC input. + printf '\1' | dd of=${2} conv=notrunc bs=1 seek=16 status=none +} + +# Create ${2} .S file with all symbols from the ${1} object file +kallsyms() +{ + local kallsymopt; + + if [ -n "${CONFIG_KALLSYMS_ALL}" ]; then + kallsymopt="${kallsymopt} --all-symbols" + fi + + if [ -n "${CONFIG_KALLSYMS_ABSOLUTE_PERCPU}" ]; then + kallsymopt="${kallsymopt} --absolute-percpu" + fi + + if [ -n "${CONFIG_KALLSYMS_BASE_RELATIVE}" ]; then + kallsymopt="${kallsymopt} --base-relative" + fi + + info KSYMS ${2} + ${NM} -n ${1} | scripts/kallsyms ${kallsymopt} > ${2} +} + +# Perform one step in kallsyms generation, including temporary linking of +# vmlinux. +kallsyms_step() +{ + kallsymso_prev=${kallsymso} + kallsyms_vmlinux=.tmp_vmlinux.kallsyms${1} + kallsymso=${kallsyms_vmlinux}.o + kallsyms_S=${kallsyms_vmlinux}.S + + vmlinux_link ${kallsyms_vmlinux} "${kallsymso_prev}" ${btf_vmlinux_bin_o} + kallsyms ${kallsyms_vmlinux} ${kallsyms_S} + + info AS ${kallsyms_S} + ${CC} ${NOSTDINC_FLAGS} ${LINUXINCLUDE} ${KBUILD_CPPFLAGS} \ + ${KBUILD_AFLAGS} ${KBUILD_AFLAGS_KERNEL} \ + -c -o ${kallsymso} ${kallsyms_S} +} + +# Create map file with all symbols from ${1} +# See mksymap for additional details +mksysmap() +{ + ${CONFIG_SHELL} "${srctree}/scripts/mksysmap" ${1} ${2} +} + +sorttable() +{ + ${objtree}/scripts/sorttable ${1} +} + +# Delete output files in case of error +cleanup() +{ + rm -f .btf.* + rm -f .tmp_System.map + rm -f .tmp_vmlinux* + rm -f System.map + rm -f vmlinux + rm -f vmlinux.o +} + +on_exit() +{ + if [ $? -ne 0 ]; then + cleanup + fi +} +trap on_exit EXIT + +on_signals() +{ + exit 1 +} +trap on_signals HUP INT QUIT TERM + +# Use "make V=1" to debug this script +case "${KBUILD_VERBOSE}" in +*1*) + set -x + ;; +esac + +if [ "$1" = "clean" ]; then + cleanup + exit 0 +fi + +# We need access to CONFIG_ symbols +. include/config/auto.conf + +# Update version +info GEN .version +if [ -r .version ]; then + VERSION=$(expr 0$(cat .version) + 1) + echo $VERSION > .version +else + rm -f .version + echo 1 > .version +fi; + +# final build of init/ +${MAKE} -f "${srctree}/scripts/Makefile.build" obj=init need-builtin=1 + +#link vmlinux.o +info LD vmlinux.o +modpost_link vmlinux.o +objtool_link vmlinux.o + +# modpost vmlinux.o to check for section mismatches +${MAKE} -f "${srctree}/scripts/Makefile.modpost" MODPOST_VMLINUX=1 + +info MODINFO modules.builtin.modinfo +${OBJCOPY} -j .modinfo -O binary vmlinux.o modules.builtin.modinfo +info GEN modules.builtin +# The second line aids cases where multiple modules share the same object. +tr '\0' '\n' < modules.builtin.modinfo | sed -n 's/^[[:alnum:]:_]*\.file=//p' | + tr ' ' '\n' | uniq | sed -e 's:^:kernel/:' -e 's/$/.ko/' > modules.builtin + +btf_vmlinux_bin_o="" +if [ -n "${CONFIG_DEBUG_INFO_BTF}" ]; then + btf_vmlinux_bin_o=.btf.vmlinux.bin.o + if ! gen_btf .tmp_vmlinux.btf $btf_vmlinux_bin_o ; then + echo >&2 "Failed to generate BTF for vmlinux" + echo >&2 "Try to disable CONFIG_DEBUG_INFO_BTF" + exit 1 + fi +fi + +kallsymso="" +kallsymso_prev="" +kallsyms_vmlinux="" +if [ -n "${CONFIG_KALLSYMS}" ]; then + + # kallsyms support + # Generate section listing all symbols and add it into vmlinux + # It's a three step process: + # 1) Link .tmp_vmlinux1 so it has all symbols and sections, + # but __kallsyms is empty. + # Running kallsyms on that gives us .tmp_kallsyms1.o with + # the right size + # 2) Link .tmp_vmlinux2 so it now has a __kallsyms section of + # the right size, but due to the added section, some + # addresses have shifted. + # From here, we generate a correct .tmp_kallsyms2.o + # 3) That link may have expanded the kernel image enough that + # more linker branch stubs / trampolines had to be added, which + # introduces new names, which further expands kallsyms. Do another + # pass if that is the case. In theory it's possible this results + # in even more stubs, but unlikely. + # KALLSYMS_EXTRA_PASS=1 may also used to debug or work around + # other bugs. + # 4) The correct ${kallsymso} is linked into the final vmlinux. + # + # a) Verify that the System.map from vmlinux matches the map from + # ${kallsymso}. + + kallsyms_step 1 + kallsyms_step 2 + + # step 3 + size1=$(${CONFIG_SHELL} "${srctree}/scripts/file-size.sh" ${kallsymso_prev}) + size2=$(${CONFIG_SHELL} "${srctree}/scripts/file-size.sh" ${kallsymso}) + + if [ $size1 -ne $size2 ] || [ -n "${KALLSYMS_EXTRA_PASS}" ]; then + kallsyms_step 3 + fi +fi + +vmlinux_link vmlinux "${kallsymso}" ${btf_vmlinux_bin_o} + +# fill in BTF IDs +if [ -n "${CONFIG_DEBUG_INFO_BTF}" -a -n "${CONFIG_BPF}" ]; then + info BTFIDS vmlinux + ${RESOLVE_BTFIDS} vmlinux +fi + +info SYSMAP System.map +mksysmap vmlinux System.map + +if [ -n "${CONFIG_BUILDTIME_TABLE_SORT}" ]; then + info SORTTAB vmlinux + if ! sorttable vmlinux; then + echo >&2 Failed to sort kernel tables + exit 1 + fi +fi + +# step a (see comment above) +if [ -n "${CONFIG_KALLSYMS}" ]; then + mksysmap ${kallsyms_vmlinux} .tmp_System.map + + if ! cmp -s System.map .tmp_System.map; then + echo >&2 Inconsistent kallsyms data + echo >&2 Try "make KALLSYMS_EXTRA_PASS=1" as a workaround + exit 1 + fi +fi diff --git a/src/net/scripts/lld-version.sh b/src/net/scripts/lld-version.sh new file mode 100755 index 0000000..f1eeee4 --- /dev/null +++ b/src/net/scripts/lld-version.sh @@ -0,0 +1,37 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0 +# +# Usage: $ ./scripts/lld-version.sh ld.lld +# +# Print the linker version of `ld.lld' in a 5 or 6-digit form +# such as `100001' for ld.lld 10.0.1 etc. + +set -e + +# Convert the version string x.y.z to a canonical 5 or 6-digit form. +get_canonical_version() +{ + IFS=. + set -- $1 + + # If the 2nd or 3rd field is missing, fill it with a zero. + echo $((10000 * $1 + 100 * ${2:-0} + ${3:-0})) +} + +# Get the first line of the --version output. +IFS=' +' +set -- $(LC_ALL=C "$@" --version) + +# Split the line on spaces. +IFS=' ' +set -- $1 + +while [ $# -gt 1 -a "$1" != "LLD" ]; do + shift +done +if [ "$1" = LLD ]; then + echo $(get_canonical_version ${2%-*}) +else + echo 0 +fi diff --git a/src/net/scripts/makelst b/src/net/scripts/makelst new file mode 100755 index 0000000..e432af0 --- /dev/null +++ b/src/net/scripts/makelst @@ -0,0 +1,32 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0 +# A script to dump mixed source code & assembly +# with correct relocations from System.map +# Requires the following lines in makefile: +#%.lst: %.c +# $(CC) $(c_flags) -g -c -o $*.o $< && +# $(srctree)/scripts/makelst $*.o System.map $(OBJDUMP) > $@ +# +# Copyright (C) 2000 IBM Corporation +# Author(s): DJ Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com) +# William Stearns <wstearns@pobox.com> +# + +# awk style field access +field() { + shift $1 ; echo $1 +} + +t1=`$3 --syms $1 | grep .text | grep -m1 " F "` +if [ -n "$t1" ]; then + t2=`field 6 $t1` + if [ ! -r $2 ]; then + echo "No System.map" >&2 + else + t3=`grep $t2 $2` + t4=`field 1 $t3` + t5=`field 1 $t1` + t6=`printf "%lu" $((0x$t4 - 0x$t5))` + fi +fi +$3 -r --source --adjust-vma=${t6:-0} $1 diff --git a/src/net/scripts/markup_oops.pl b/src/net/scripts/markup_oops.pl new file mode 100755 index 0000000..e476caf --- /dev/null +++ b/src/net/scripts/markup_oops.pl @@ -0,0 +1,366 @@ +#!/usr/bin/env perl +# SPDX-License-Identifier: GPL-2.0-only + +use File::Basename; +use Math::BigInt; +use Getopt::Long; + +# Copyright 2008, Intel Corporation +# +# This file is part of the Linux kernel +# +# Authors: +# Arjan van de Ven <arjan@linux.intel.com> + + +my $cross_compile = ""; +my $vmlinux_name = ""; +my $modulefile = ""; + +# Get options +Getopt::Long::GetOptions( + 'cross-compile|c=s' => \$cross_compile, + 'module|m=s' => \$modulefile, + 'help|h' => \&usage, +) || usage (); +my $vmlinux_name = $ARGV[0]; +if (!defined($vmlinux_name)) { + my $kerver = `uname -r`; + chomp($kerver); + $vmlinux_name = "/lib/modules/$kerver/build/vmlinux"; + print "No vmlinux specified, assuming $vmlinux_name\n"; +} +my $filename = $vmlinux_name; + +# Parse the oops to find the EIP value + +my $target = "0"; +my $function; +my $module = ""; +my $func_offset = 0; +my $vmaoffset = 0; + +my %regs; + + +sub parse_x86_regs +{ + my ($line) = @_; + if ($line =~ /EAX: ([0-9a-f]+) EBX: ([0-9a-f]+) ECX: ([0-9a-f]+) EDX: ([0-9a-f]+)/) { + $regs{"%eax"} = $1; + $regs{"%ebx"} = $2; + $regs{"%ecx"} = $3; + $regs{"%edx"} = $4; + } + if ($line =~ /ESI: ([0-9a-f]+) EDI: ([0-9a-f]+) EBP: ([0-9a-f]+) ESP: ([0-9a-f]+)/) { + $regs{"%esi"} = $1; + $regs{"%edi"} = $2; + $regs{"%esp"} = $4; + } + if ($line =~ /RAX: ([0-9a-f]+) RBX: ([0-9a-f]+) RCX: ([0-9a-f]+)/) { + $regs{"%eax"} = $1; + $regs{"%ebx"} = $2; + $regs{"%ecx"} = $3; + } + if ($line =~ /RDX: ([0-9a-f]+) RSI: ([0-9a-f]+) RDI: ([0-9a-f]+)/) { + $regs{"%edx"} = $1; + $regs{"%esi"} = $2; + $regs{"%edi"} = $3; + } + if ($line =~ /RBP: ([0-9a-f]+) R08: ([0-9a-f]+) R09: ([0-9a-f]+)/) { + $regs{"%r08"} = $2; + $regs{"%r09"} = $3; + } + if ($line =~ /R10: ([0-9a-f]+) R11: ([0-9a-f]+) R12: ([0-9a-f]+)/) { + $regs{"%r10"} = $1; + $regs{"%r11"} = $2; + $regs{"%r12"} = $3; + } + if ($line =~ /R13: ([0-9a-f]+) R14: ([0-9a-f]+) R15: ([0-9a-f]+)/) { + $regs{"%r13"} = $1; + $regs{"%r14"} = $2; + $regs{"%r15"} = $3; + } +} + +sub reg_name +{ + my ($reg) = @_; + $reg =~ s/r(.)x/e\1x/; + $reg =~ s/r(.)i/e\1i/; + $reg =~ s/r(.)p/e\1p/; + return $reg; +} + +sub process_x86_regs +{ + my ($line, $cntr) = @_; + my $str = ""; + if (length($line) < 40) { + return ""; # not an asm istruction + } + + # find the arguments to the instruction + if ($line =~ /([0-9a-zA-Z\,\%\(\)\-\+]+)$/) { + $lastword = $1; + } else { + return ""; + } + + # we need to find the registers that get clobbered, + # since their value is no longer relevant for previous + # instructions in the stream. + + $clobber = $lastword; + # first, remove all memory operands, they're read only + $clobber =~ s/\([a-z0-9\%\,]+\)//g; + # then, remove everything before the comma, thats the read part + $clobber =~ s/.*\,//g; + + # if this is the instruction that faulted, we haven't actually done + # the write yet... nothing is clobbered. + if ($cntr == 0) { + $clobber = ""; + } + + foreach $reg (keys(%regs)) { + my $clobberprime = reg_name($clobber); + my $lastwordprime = reg_name($lastword); + my $val = $regs{$reg}; + if ($val =~ /^[0]+$/) { + $val = "0"; + } else { + $val =~ s/^0*//; + } + + # first check if we're clobbering this register; if we do + # we print it with a =>, and then delete its value + if ($clobber =~ /$reg/ || $clobberprime =~ /$reg/) { + if (length($val) > 0) { + $str = $str . " $reg => $val "; + } + $regs{$reg} = ""; + $val = ""; + } + # now check if we're reading this register + if ($lastword =~ /$reg/ || $lastwordprime =~ /$reg/) { + if (length($val) > 0) { + $str = $str . " $reg = $val "; + } + } + } + return $str; +} + +# parse the oops +while (<STDIN>) { + my $line = $_; + if ($line =~ /EIP: 0060:\[\<([a-z0-9]+)\>\]/) { + $target = $1; + } + if ($line =~ /RIP: 0010:\[\<([a-z0-9]+)\>\]/) { + $target = $1; + } + if ($line =~ /EIP is at ([a-zA-Z0-9\_]+)\+0x([0-9a-f]+)\/0x[a-f0-9]/) { + $function = $1; + $func_offset = $2; + } + if ($line =~ /RIP: 0010:\[\<[0-9a-f]+\>\] \[\<[0-9a-f]+\>\] ([a-zA-Z0-9\_]+)\+0x([0-9a-f]+)\/0x[a-f0-9]/) { + $function = $1; + $func_offset = $2; + } + + # check if it's a module + if ($line =~ /EIP is at ([a-zA-Z0-9\_]+)\+(0x[0-9a-f]+)\/0x[a-f0-9]+\W\[([a-zA-Z0-9\_\-]+)\]/) { + $module = $3; + } + if ($line =~ /RIP: 0010:\[\<[0-9a-f]+\>\] \[\<[0-9a-f]+\>\] ([a-zA-Z0-9\_]+)\+(0x[0-9a-f]+)\/0x[a-f0-9]+\W\[([a-zA-Z0-9\_\-]+)\]/) { + $module = $3; + } + parse_x86_regs($line); +} + +my $decodestart = Math::BigInt->from_hex("0x$target") - Math::BigInt->from_hex("0x$func_offset"); +my $decodestop = Math::BigInt->from_hex("0x$target") + 8192; +if ($target eq "0") { + print "No oops found!\n"; + usage(); +} + +# if it's a module, we need to find the .ko file and calculate a load offset +if ($module ne "") { + if ($modulefile eq "") { + $modulefile = `modinfo -F filename $module`; + chomp($modulefile); + } + $filename = $modulefile; + if ($filename eq "") { + print "Module .ko file for $module not found. Aborting\n"; + exit; + } + # ok so we found the module, now we need to calculate the vma offset + open(FILE, $cross_compile."objdump -dS $filename |") || die "Cannot start objdump"; + while (<FILE>) { + if ($_ =~ /^([0-9a-f]+) \<$function\>\:/) { + my $fu = $1; + $vmaoffset = Math::BigInt->from_hex("0x$target") - Math::BigInt->from_hex("0x$fu") - Math::BigInt->from_hex("0x$func_offset"); + } + } + close(FILE); +} + +my $counter = 0; +my $state = 0; +my $center = -1; +my @lines; +my @reglines; + +sub InRange { + my ($address, $target) = @_; + my $ad = "0x".$address; + my $ta = "0x".$target; + my $delta = Math::BigInt->from_hex($ad) - Math::BigInt->from_hex($ta); + + if (($delta > -4096) && ($delta < 4096)) { + return 1; + } + return 0; +} + + + +# first, parse the input into the lines array, but to keep size down, +# we only do this for 4Kb around the sweet spot + +open(FILE, $cross_compile."objdump -dS --adjust-vma=$vmaoffset --start-address=$decodestart --stop-address=$decodestop $filename |") || die "Cannot start objdump"; + +while (<FILE>) { + my $line = $_; + chomp($line); + if ($state == 0) { + if ($line =~ /^([a-f0-9]+)\:/) { + if (InRange($1, $target)) { + $state = 1; + } + } + } + if ($state == 1) { + if ($line =~ /^([a-f0-9][a-f0-9][a-f0-9][a-f0-9][a-f0-9][a-f0-9]+)\:/) { + my $val = $1; + if (!InRange($val, $target)) { + last; + } + if ($val eq $target) { + $center = $counter; + } + } + $lines[$counter] = $line; + + $counter = $counter + 1; + } +} + +close(FILE); + +if ($counter == 0) { + print "No matching code found \n"; + exit; +} + +if ($center == -1) { + print "No matching code found \n"; + exit; +} + +my $start; +my $finish; +my $codelines = 0; +my $binarylines = 0; +# now we go up and down in the array to find how much we want to print + +$start = $center; + +while ($start > 1) { + $start = $start - 1; + my $line = $lines[$start]; + if ($line =~ /^([a-f0-9]+)\:/) { + $binarylines = $binarylines + 1; + } else { + $codelines = $codelines + 1; + } + if ($codelines > 10) { + last; + } + if ($binarylines > 20) { + last; + } +} + + +$finish = $center; +$codelines = 0; +$binarylines = 0; +while ($finish < $counter) { + $finish = $finish + 1; + my $line = $lines[$finish]; + if ($line =~ /^([a-f0-9]+)\:/) { + $binarylines = $binarylines + 1; + } else { + $codelines = $codelines + 1; + } + if ($codelines > 10) { + last; + } + if ($binarylines > 20) { + last; + } +} + + +my $i; + + +# start annotating the registers in the asm. +# this goes from the oopsing point back, so that the annotator +# can track (opportunistically) which registers got written and +# whos value no longer is relevant. + +$i = $center; +while ($i >= $start) { + $reglines[$i] = process_x86_regs($lines[$i], $center - $i); + $i = $i - 1; +} + +$i = $start; +while ($i < $finish) { + my $line; + if ($i == $center) { + $line = "*$lines[$i] "; + } else { + $line = " $lines[$i] "; + } + print $line; + if (defined($reglines[$i]) && length($reglines[$i]) > 0) { + my $c = 60 - length($line); + while ($c > 0) { print " "; $c = $c - 1; }; + print "| $reglines[$i]"; + } + if ($i == $center) { + print "<--- faulting instruction"; + } + print "\n"; + $i = $i +1; +} + +sub usage { + print <<EOT; +Usage: + dmesg | perl $0 [OPTION] [VMLINUX] + +OPTION: + -c, --cross-compile CROSS_COMPILE Specify the prefix used for toolchain. + -m, --module MODULE_DIRNAME Specify the module filename. + -h, --help Help. +EOT + exit; +} diff --git a/src/net/scripts/mkcompile_h b/src/net/scripts/mkcompile_h new file mode 100755 index 0000000..a72b154 --- /dev/null +++ b/src/net/scripts/mkcompile_h @@ -0,0 +1,96 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0 + +TARGET=$1 +ARCH=$2 +SMP=$3 +PREEMPT=$4 +PREEMPT_RT=$5 +CC_VERSION="$6" +LD=$7 + +vecho() { [ "${quiet}" = "silent_" ] || echo "$@" ; } + +# Do not expand names +set -f + +# Fix the language to get consistent output +LC_ALL=C +export LC_ALL + +if [ -z "$KBUILD_BUILD_VERSION" ]; then + VERSION=$(cat .version 2>/dev/null || echo 1) +else + VERSION=$KBUILD_BUILD_VERSION +fi + +if [ -z "$KBUILD_BUILD_TIMESTAMP" ]; then + TIMESTAMP=`date` +else + TIMESTAMP=$KBUILD_BUILD_TIMESTAMP +fi +if test -z "$KBUILD_BUILD_USER"; then + LINUX_COMPILE_BY=$(whoami | sed 's/\\/\\\\/') +else + LINUX_COMPILE_BY=$KBUILD_BUILD_USER +fi +if test -z "$KBUILD_BUILD_HOST"; then + LINUX_COMPILE_HOST=`uname -n` +else + LINUX_COMPILE_HOST=$KBUILD_BUILD_HOST +fi + +UTS_VERSION="#$VERSION" +CONFIG_FLAGS="" +if [ -n "$SMP" ] ; then CONFIG_FLAGS="SMP"; fi +if [ -n "$PREEMPT" ] ; then CONFIG_FLAGS="$CONFIG_FLAGS PREEMPT"; fi +if [ -n "$PREEMPT_RT" ] ; then CONFIG_FLAGS="$CONFIG_FLAGS PREEMPT_RT"; fi + +# Truncate to maximum length +UTS_LEN=64 +UTS_VERSION="$(echo $UTS_VERSION $CONFIG_FLAGS $TIMESTAMP | cut -b -$UTS_LEN)" + +# Generate a temporary compile.h + +{ echo /\* This file is auto generated, version $VERSION \*/ + if [ -n "$CONFIG_FLAGS" ] ; then echo "/* $CONFIG_FLAGS */"; fi + + echo \#define UTS_MACHINE \"$ARCH\" + + echo \#define UTS_VERSION \"$UTS_VERSION\" + + printf '#define LINUX_COMPILE_BY "%s"\n' "$LINUX_COMPILE_BY" + echo \#define LINUX_COMPILE_HOST \"$LINUX_COMPILE_HOST\" + + LD_VERSION=$($LD -v | head -n1 | sed 's/(compatible with [^)]*)//' \ + | sed 's/[[:space:]]*$//') + printf '#define LINUX_COMPILER "%s"\n' "$CC_VERSION, $LD_VERSION" +} > .tmpcompile + +# Only replace the real compile.h if the new one is different, +# in order to preserve the timestamp and avoid unnecessary +# recompilations. +# We don't consider the file changed if only the date/time changed, +# unless KBUILD_BUILD_TIMESTAMP was explicitly set (e.g. for +# reproducible builds with that value referring to a commit timestamp). +# A kernel config change will increase the generation number, thus +# causing compile.h to be updated (including date/time) due to the +# changed comment in the +# first line. + +if [ -z "$KBUILD_BUILD_TIMESTAMP" ]; then + IGNORE_PATTERN="UTS_VERSION" +else + IGNORE_PATTERN="NOT_A_PATTERN_TO_BE_MATCHED" +fi + +if [ -r $TARGET ] && \ + grep -v $IGNORE_PATTERN $TARGET > .tmpver.1 && \ + grep -v $IGNORE_PATTERN .tmpcompile > .tmpver.2 && \ + cmp -s .tmpver.1 .tmpver.2; then + rm -f .tmpcompile +else + vecho " UPD $TARGET" + mv -f .tmpcompile $TARGET +fi +rm -f .tmpver.1 .tmpver.2 diff --git a/src/net/scripts/mkmakefile b/src/net/scripts/mkmakefile new file mode 100755 index 0000000..1cb1747 --- /dev/null +++ b/src/net/scripts/mkmakefile @@ -0,0 +1,17 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0 +# Generates a small Makefile used in the root of the output +# directory, to allow make to be started from there. +# The Makefile also allow for more convinient build of external modules + +# Usage +# $1 - Kernel src directory + +if [ "${quiet}" != "silent_" ]; then + echo " GEN Makefile" +fi + +cat << EOF > Makefile +# Automatically generated by $0: don't edit +include $1/Makefile +EOF diff --git a/src/net/scripts/mksysmap b/src/net/scripts/mksysmap new file mode 100755 index 0000000..9aa23d1 --- /dev/null +++ b/src/net/scripts/mksysmap @@ -0,0 +1,44 @@ +#!/bin/sh -x +# Based on the vmlinux file create the System.map file +# System.map is used by module-init tools and some debugging +# tools to retrieve the actual addresses of symbols in the kernel. +# +# Usage +# mksysmap vmlinux System.map + + +##### +# Generate System.map (actual filename passed as second argument) + +# $NM produces the following output: +# f0081e80 T alloc_vfsmnt + +# The second row specify the type of the symbol: +# A = Absolute +# B = Uninitialised data (.bss) +# C = Common symbol +# D = Initialised data +# G = Initialised data for small objects +# I = Indirect reference to another symbol +# N = Debugging symbol +# R = Read only +# S = Uninitialised data for small objects +# T = Text code symbol +# U = Undefined symbol +# V = Weak symbol +# W = Weak symbol +# Corresponding small letters are local symbols + +# For System.map filter away: +# a - local absolute symbols +# U - undefined global symbols +# N - debugging symbols +# w - local weak symbols + +# readprofile starts reading symbols when _stext is found, and +# continue until it finds a symbol which is not either of 'T', 't', +# 'W' or 'w'. __crc_ are 'A' and placed in the middle +# so we just ignore them to let readprofile continue to work. +# (At least sparc64 has __crc_ in the middle). + +$NM -n $1 | grep -v '\( [aNUw] \)\|\(__crc_\)\|\( \$[adt]\)\|\( \.L\)' > $2 diff --git a/src/net/scripts/mkuboot.sh b/src/net/scripts/mkuboot.sh new file mode 100755 index 0000000..4b1fe09 --- /dev/null +++ b/src/net/scripts/mkuboot.sh @@ -0,0 +1,20 @@ +#!/bin/bash +# SPDX-License-Identifier: GPL-2.0 + +# +# Build U-Boot image when `mkimage' tool is available. +# + +MKIMAGE=$(type -path "${CROSS_COMPILE}mkimage") + +if [ -z "${MKIMAGE}" ]; then + MKIMAGE=$(type -path mkimage) + if [ -z "${MKIMAGE}" ]; then + # Doesn't exist + echo '"mkimage" command not found - U-Boot images will not be built' >&2 + exit 1; + fi +fi + +# Call "mkimage" to create U-Boot image +${MKIMAGE} "$@" diff --git a/src/net/scripts/mod/.gitignore b/src/net/scripts/mod/.gitignore new file mode 100644 index 0000000..07e4a39 --- /dev/null +++ b/src/net/scripts/mod/.gitignore @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only +elfconfig.h +mk_elfconfig +modpost +devicetable-offsets.h diff --git a/src/net/scripts/mod/Makefile b/src/net/scripts/mod/Makefile new file mode 100644 index 0000000..7807168 --- /dev/null +++ b/src/net/scripts/mod/Makefile @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: GPL-2.0 +OBJECT_FILES_NON_STANDARD := y + +hostprogs-always-y += modpost mk_elfconfig +always-y += empty.o + +modpost-objs := modpost.o file2alias.o sumversion.o + +devicetable-offsets-file := devicetable-offsets.h + +$(obj)/$(devicetable-offsets-file): $(obj)/devicetable-offsets.s FORCE + $(call filechk,offsets,__DEVICETABLE_OFFSETS_H__) + +targets += $(devicetable-offsets-file) devicetable-offsets.s + +# dependencies on generated files need to be listed explicitly + +$(obj)/modpost.o $(obj)/file2alias.o $(obj)/sumversion.o: $(obj)/elfconfig.h +$(obj)/file2alias.o: $(obj)/$(devicetable-offsets-file) + +quiet_cmd_elfconfig = MKELF $@ + cmd_elfconfig = $(obj)/mk_elfconfig < $< > $@ + +$(obj)/elfconfig.h: $(obj)/empty.o $(obj)/mk_elfconfig FORCE + $(call if_changed,elfconfig) + +targets += elfconfig.h diff --git a/src/net/scripts/mod/devicetable-offsets.c b/src/net/scripts/mod/devicetable-offsets.c new file mode 100644 index 0000000..e377f52 --- /dev/null +++ b/src/net/scripts/mod/devicetable-offsets.c @@ -0,0 +1,250 @@ +// SPDX-License-Identifier: GPL-2.0 +#include <linux/kbuild.h> +#include <linux/mod_devicetable.h> + +#define DEVID(devid) DEFINE(SIZE_##devid, sizeof(struct devid)) +#define DEVID_FIELD(devid, field) \ + DEFINE(OFF_##devid##_##field, offsetof(struct devid, field)) + +int main(void) +{ + DEVID(usb_device_id); + DEVID_FIELD(usb_device_id, match_flags); + DEVID_FIELD(usb_device_id, idVendor); + DEVID_FIELD(usb_device_id, idProduct); + DEVID_FIELD(usb_device_id, bcdDevice_lo); + DEVID_FIELD(usb_device_id, bcdDevice_hi); + DEVID_FIELD(usb_device_id, bDeviceClass); + DEVID_FIELD(usb_device_id, bDeviceSubClass); + DEVID_FIELD(usb_device_id, bDeviceProtocol); + DEVID_FIELD(usb_device_id, bInterfaceClass); + DEVID_FIELD(usb_device_id, bInterfaceSubClass); + DEVID_FIELD(usb_device_id, bInterfaceProtocol); + DEVID_FIELD(usb_device_id, bInterfaceNumber); + + DEVID(hid_device_id); + DEVID_FIELD(hid_device_id, bus); + DEVID_FIELD(hid_device_id, group); + DEVID_FIELD(hid_device_id, vendor); + DEVID_FIELD(hid_device_id, product); + + DEVID(ieee1394_device_id); + DEVID_FIELD(ieee1394_device_id, match_flags); + DEVID_FIELD(ieee1394_device_id, vendor_id); + DEVID_FIELD(ieee1394_device_id, model_id); + DEVID_FIELD(ieee1394_device_id, specifier_id); + DEVID_FIELD(ieee1394_device_id, version); + + DEVID(pci_device_id); + DEVID_FIELD(pci_device_id, vendor); + DEVID_FIELD(pci_device_id, device); + DEVID_FIELD(pci_device_id, subvendor); + DEVID_FIELD(pci_device_id, subdevice); + DEVID_FIELD(pci_device_id, class); + DEVID_FIELD(pci_device_id, class_mask); + + DEVID(ccw_device_id); + DEVID_FIELD(ccw_device_id, match_flags); + DEVID_FIELD(ccw_device_id, cu_type); + DEVID_FIELD(ccw_device_id, cu_model); + DEVID_FIELD(ccw_device_id, dev_type); + DEVID_FIELD(ccw_device_id, dev_model); + + DEVID(ap_device_id); + DEVID_FIELD(ap_device_id, dev_type); + + DEVID(css_device_id); + DEVID_FIELD(css_device_id, type); + + DEVID(serio_device_id); + DEVID_FIELD(serio_device_id, type); + DEVID_FIELD(serio_device_id, proto); + DEVID_FIELD(serio_device_id, id); + DEVID_FIELD(serio_device_id, extra); + + DEVID(acpi_device_id); + DEVID_FIELD(acpi_device_id, id); + DEVID_FIELD(acpi_device_id, cls); + DEVID_FIELD(acpi_device_id, cls_msk); + + DEVID(pnp_device_id); + DEVID_FIELD(pnp_device_id, id); + + DEVID(pnp_card_device_id); + DEVID_FIELD(pnp_card_device_id, devs); + + DEVID(pcmcia_device_id); + DEVID_FIELD(pcmcia_device_id, match_flags); + DEVID_FIELD(pcmcia_device_id, manf_id); + DEVID_FIELD(pcmcia_device_id, card_id); + DEVID_FIELD(pcmcia_device_id, func_id); + DEVID_FIELD(pcmcia_device_id, function); + DEVID_FIELD(pcmcia_device_id, device_no); + DEVID_FIELD(pcmcia_device_id, prod_id_hash); + + DEVID(of_device_id); + DEVID_FIELD(of_device_id, name); + DEVID_FIELD(of_device_id, type); + DEVID_FIELD(of_device_id, compatible); + + DEVID(vio_device_id); + DEVID_FIELD(vio_device_id, type); + DEVID_FIELD(vio_device_id, compat); + + DEVID(input_device_id); + DEVID_FIELD(input_device_id, flags); + DEVID_FIELD(input_device_id, bustype); + DEVID_FIELD(input_device_id, vendor); + DEVID_FIELD(input_device_id, product); + DEVID_FIELD(input_device_id, version); + DEVID_FIELD(input_device_id, evbit); + DEVID_FIELD(input_device_id, keybit); + DEVID_FIELD(input_device_id, relbit); + DEVID_FIELD(input_device_id, absbit); + DEVID_FIELD(input_device_id, mscbit); + DEVID_FIELD(input_device_id, ledbit); + DEVID_FIELD(input_device_id, sndbit); + DEVID_FIELD(input_device_id, ffbit); + DEVID_FIELD(input_device_id, swbit); + + DEVID(eisa_device_id); + DEVID_FIELD(eisa_device_id, sig); + + DEVID(parisc_device_id); + DEVID_FIELD(parisc_device_id, hw_type); + DEVID_FIELD(parisc_device_id, hversion); + DEVID_FIELD(parisc_device_id, hversion_rev); + DEVID_FIELD(parisc_device_id, sversion); + + DEVID(sdio_device_id); + DEVID_FIELD(sdio_device_id, class); + DEVID_FIELD(sdio_device_id, vendor); + DEVID_FIELD(sdio_device_id, device); + + DEVID(ssb_device_id); + DEVID_FIELD(ssb_device_id, vendor); + DEVID_FIELD(ssb_device_id, coreid); + DEVID_FIELD(ssb_device_id, revision); + + DEVID(bcma_device_id); + DEVID_FIELD(bcma_device_id, manuf); + DEVID_FIELD(bcma_device_id, id); + DEVID_FIELD(bcma_device_id, rev); + DEVID_FIELD(bcma_device_id, class); + + DEVID(virtio_device_id); + DEVID_FIELD(virtio_device_id, device); + DEVID_FIELD(virtio_device_id, vendor); + + DEVID(hv_vmbus_device_id); + DEVID_FIELD(hv_vmbus_device_id, guid); + + DEVID(rpmsg_device_id); + DEVID_FIELD(rpmsg_device_id, name); + + DEVID(i2c_device_id); + DEVID_FIELD(i2c_device_id, name); + + DEVID(i3c_device_id); + DEVID_FIELD(i3c_device_id, match_flags); + DEVID_FIELD(i3c_device_id, dcr); + DEVID_FIELD(i3c_device_id, manuf_id); + DEVID_FIELD(i3c_device_id, part_id); + DEVID_FIELD(i3c_device_id, extra_info); + + DEVID(spi_device_id); + DEVID_FIELD(spi_device_id, name); + + DEVID(dmi_system_id); + DEVID_FIELD(dmi_system_id, matches); + + DEVID(platform_device_id); + DEVID_FIELD(platform_device_id, name); + + DEVID(mdio_device_id); + DEVID_FIELD(mdio_device_id, phy_id); + DEVID_FIELD(mdio_device_id, phy_id_mask); + + DEVID(zorro_device_id); + DEVID_FIELD(zorro_device_id, id); + + DEVID(isapnp_device_id); + DEVID_FIELD(isapnp_device_id, vendor); + DEVID_FIELD(isapnp_device_id, function); + + DEVID(ipack_device_id); + DEVID_FIELD(ipack_device_id, format); + DEVID_FIELD(ipack_device_id, vendor); + DEVID_FIELD(ipack_device_id, device); + + DEVID(amba_id); + DEVID_FIELD(amba_id, id); + DEVID_FIELD(amba_id, mask); + + DEVID(mips_cdmm_device_id); + DEVID_FIELD(mips_cdmm_device_id, type); + + DEVID(x86_cpu_id); + DEVID_FIELD(x86_cpu_id, feature); + DEVID_FIELD(x86_cpu_id, family); + DEVID_FIELD(x86_cpu_id, model); + DEVID_FIELD(x86_cpu_id, vendor); + + DEVID(cpu_feature); + DEVID_FIELD(cpu_feature, feature); + + DEVID(mei_cl_device_id); + DEVID_FIELD(mei_cl_device_id, name); + DEVID_FIELD(mei_cl_device_id, uuid); + DEVID_FIELD(mei_cl_device_id, version); + + DEVID(rio_device_id); + DEVID_FIELD(rio_device_id, did); + DEVID_FIELD(rio_device_id, vid); + DEVID_FIELD(rio_device_id, asm_did); + DEVID_FIELD(rio_device_id, asm_vid); + + DEVID(ulpi_device_id); + DEVID_FIELD(ulpi_device_id, vendor); + DEVID_FIELD(ulpi_device_id, product); + + DEVID(hda_device_id); + DEVID_FIELD(hda_device_id, vendor_id); + DEVID_FIELD(hda_device_id, rev_id); + DEVID_FIELD(hda_device_id, api_version); + + DEVID(sdw_device_id); + DEVID_FIELD(sdw_device_id, mfg_id); + DEVID_FIELD(sdw_device_id, part_id); + DEVID_FIELD(sdw_device_id, sdw_version); + DEVID_FIELD(sdw_device_id, class_id); + + DEVID(fsl_mc_device_id); + DEVID_FIELD(fsl_mc_device_id, vendor); + DEVID_FIELD(fsl_mc_device_id, obj_type); + + DEVID(tb_service_id); + DEVID_FIELD(tb_service_id, match_flags); + DEVID_FIELD(tb_service_id, protocol_key); + DEVID_FIELD(tb_service_id, protocol_id); + DEVID_FIELD(tb_service_id, protocol_version); + DEVID_FIELD(tb_service_id, protocol_revision); + + DEVID(typec_device_id); + DEVID_FIELD(typec_device_id, svid); + DEVID_FIELD(typec_device_id, mode); + + DEVID(tee_client_device_id); + DEVID_FIELD(tee_client_device_id, uuid); + + DEVID(wmi_device_id); + DEVID_FIELD(wmi_device_id, guid_string); + + DEVID(mhi_device_id); + DEVID_FIELD(mhi_device_id, chan); + + DEVID(auxiliary_device_id); + DEVID_FIELD(auxiliary_device_id, name); + + return 0; +} diff --git a/src/net/scripts/mod/empty.c b/src/net/scripts/mod/empty.c new file mode 100644 index 0000000..49839cc --- /dev/null +++ b/src/net/scripts/mod/empty.c @@ -0,0 +1 @@ +/* empty file to figure out endianness / word size */ diff --git a/src/net/scripts/mod/file2alias.c b/src/net/scripts/mod/file2alias.c new file mode 100644 index 0000000..814204a --- /dev/null +++ b/src/net/scripts/mod/file2alias.c @@ -0,0 +1,1530 @@ +/* Simple code to turn various tables in an ELF file into alias definitions. + * This deals with kernel datastructures where they should be + * dealt with: in the kernel source. + * + * Copyright 2002-2003 Rusty Russell, IBM Corporation + * 2003 Kai Germaschewski + * + * + * This software may be used and distributed according to the terms + * of the GNU General Public License, incorporated herein by reference. + */ + +#include "modpost.h" +#include "devicetable-offsets.h" + +/* We use the ELF typedefs for kernel_ulong_t but bite the bullet and + * use either stdint.h or inttypes.h for the rest. */ +#if KERNEL_ELFCLASS == ELFCLASS32 +typedef Elf32_Addr kernel_ulong_t; +#define BITS_PER_LONG 32 +#else +typedef Elf64_Addr kernel_ulong_t; +#define BITS_PER_LONG 64 +#endif +#ifdef __sun__ +#include <inttypes.h> +#else +#include <stdint.h> +#endif + +#include <ctype.h> +#include <stdbool.h> + +typedef uint32_t __u32; +typedef uint16_t __u16; +typedef unsigned char __u8; +typedef struct { + __u8 b[16]; +} guid_t; + +/* backwards compatibility, don't use in new code */ +typedef struct { + __u8 b[16]; +} uuid_le; +typedef struct { + __u8 b[16]; +} uuid_t; +#define UUID_STRING_LEN 36 + +/* Big exception to the "don't include kernel headers into userspace, which + * even potentially has different endianness and word sizes, since + * we handle those differences explicitly below */ +#include "../../include/linux/mod_devicetable.h" + +/* This array collects all instances that use the generic do_table */ +struct devtable { + const char *device_id; /* name of table, __mod_<name>__*_device_table. */ + unsigned long id_size; + int (*do_entry)(const char *filename, void *symval, char *alias); +}; + +/* Size of alias provided to do_entry functions */ +#define ALIAS_SIZE 500 + +/* Define a variable f that holds the value of field f of struct devid + * based at address m. + */ +#define DEF_FIELD(m, devid, f) \ + typeof(((struct devid *)0)->f) f = TO_NATIVE(*(typeof(f) *)((m) + OFF_##devid##_##f)) + +/* Define a variable v that holds the address of field f of struct devid + * based at address m. Due to the way typeof works, for a field of type + * T[N] the variable has type T(*)[N], _not_ T*. + */ +#define DEF_FIELD_ADDR_VAR(m, devid, f, v) \ + typeof(((struct devid *)0)->f) *v = ((m) + OFF_##devid##_##f) + +/* Define a variable f that holds the address of field f of struct devid + * based at address m. Due to the way typeof works, for a field of type + * T[N] the variable has type T(*)[N], _not_ T*. + */ +#define DEF_FIELD_ADDR(m, devid, f) \ + DEF_FIELD_ADDR_VAR(m, devid, f, f) + +#define ADD(str, sep, cond, field) \ +do { \ + strcat(str, sep); \ + if (cond) \ + sprintf(str + strlen(str), \ + sizeof(field) == 1 ? "%02X" : \ + sizeof(field) == 2 ? "%04X" : \ + sizeof(field) == 4 ? "%08X" : "", \ + field); \ + else \ + sprintf(str + strlen(str), "*"); \ +} while(0) + +/* End in a wildcard, for future extension */ +static inline void add_wildcard(char *str) +{ + int len = strlen(str); + + if (str[len - 1] != '*') + strcat(str + len, "*"); +} + +static inline void add_uuid(char *str, uuid_le uuid) +{ + int len = strlen(str); + + sprintf(str + len, "%02x%02x%02x%02x-%02x%02x-%02x%02x-%02x%02x-%02x%02x%02x%02x%02x%02x", + uuid.b[3], uuid.b[2], uuid.b[1], uuid.b[0], + uuid.b[5], uuid.b[4], uuid.b[7], uuid.b[6], + uuid.b[8], uuid.b[9], uuid.b[10], uuid.b[11], + uuid.b[12], uuid.b[13], uuid.b[14], uuid.b[15]); +} + +/** + * Check that sizeof(device_id type) are consistent with size of section + * in .o file. If in-consistent then userspace and kernel does not agree + * on actual size which is a bug. + * Also verify that the final entry in the table is all zeros. + * Ignore both checks if build host differ from target host and size differs. + **/ +static void device_id_check(const char *modname, const char *device_id, + unsigned long size, unsigned long id_size, + void *symval) +{ + int i; + + if (size % id_size || size < id_size) { + fatal("%s: sizeof(struct %s_device_id)=%lu is not a modulo " + "of the size of " + "section __mod_%s__<identifier>_device_table=%lu.\n" + "Fix definition of struct %s_device_id " + "in mod_devicetable.h\n", + modname, device_id, id_size, device_id, size, device_id); + } + /* Verify last one is a terminator */ + for (i = 0; i < id_size; i++ ) { + if (*(uint8_t*)(symval+size-id_size+i)) { + fprintf(stderr,"%s: struct %s_device_id is %lu bytes. " + "The last of %lu is:\n", + modname, device_id, id_size, size / id_size); + for (i = 0; i < id_size; i++ ) + fprintf(stderr,"0x%02x ", + *(uint8_t*)(symval+size-id_size+i) ); + fprintf(stderr,"\n"); + fatal("%s: struct %s_device_id is not terminated " + "with a NULL entry!\n", modname, device_id); + } + } +} + +/* USB is special because the bcdDevice can be matched against a numeric range */ +/* Looks like "usb:vNpNdNdcNdscNdpNicNiscNipNinN" */ +static void do_usb_entry(void *symval, + unsigned int bcdDevice_initial, int bcdDevice_initial_digits, + unsigned char range_lo, unsigned char range_hi, + unsigned char max, struct module *mod) +{ + char alias[500]; + DEF_FIELD(symval, usb_device_id, match_flags); + DEF_FIELD(symval, usb_device_id, idVendor); + DEF_FIELD(symval, usb_device_id, idProduct); + DEF_FIELD(symval, usb_device_id, bcdDevice_lo); + DEF_FIELD(symval, usb_device_id, bDeviceClass); + DEF_FIELD(symval, usb_device_id, bDeviceSubClass); + DEF_FIELD(symval, usb_device_id, bDeviceProtocol); + DEF_FIELD(symval, usb_device_id, bInterfaceClass); + DEF_FIELD(symval, usb_device_id, bInterfaceSubClass); + DEF_FIELD(symval, usb_device_id, bInterfaceProtocol); + DEF_FIELD(symval, usb_device_id, bInterfaceNumber); + + strcpy(alias, "usb:"); + ADD(alias, "v", match_flags&USB_DEVICE_ID_MATCH_VENDOR, + idVendor); + ADD(alias, "p", match_flags&USB_DEVICE_ID_MATCH_PRODUCT, + idProduct); + + strcat(alias, "d"); + if (bcdDevice_initial_digits) + sprintf(alias + strlen(alias), "%0*X", + bcdDevice_initial_digits, bcdDevice_initial); + if (range_lo == range_hi) + sprintf(alias + strlen(alias), "%X", range_lo); + else if (range_lo > 0 || range_hi < max) { + if (range_lo > 0x9 || range_hi < 0xA) + sprintf(alias + strlen(alias), + "[%X-%X]", + range_lo, + range_hi); + else { + sprintf(alias + strlen(alias), + range_lo < 0x9 ? "[%X-9" : "[%X", + range_lo); + sprintf(alias + strlen(alias), + range_hi > 0xA ? "A-%X]" : "%X]", + range_hi); + } + } + if (bcdDevice_initial_digits < (sizeof(bcdDevice_lo) * 2 - 1)) + strcat(alias, "*"); + + ADD(alias, "dc", match_flags&USB_DEVICE_ID_MATCH_DEV_CLASS, + bDeviceClass); + ADD(alias, "dsc", match_flags&USB_DEVICE_ID_MATCH_DEV_SUBCLASS, + bDeviceSubClass); + ADD(alias, "dp", match_flags&USB_DEVICE_ID_MATCH_DEV_PROTOCOL, + bDeviceProtocol); + ADD(alias, "ic", match_flags&USB_DEVICE_ID_MATCH_INT_CLASS, + bInterfaceClass); + ADD(alias, "isc", match_flags&USB_DEVICE_ID_MATCH_INT_SUBCLASS, + bInterfaceSubClass); + ADD(alias, "ip", match_flags&USB_DEVICE_ID_MATCH_INT_PROTOCOL, + bInterfaceProtocol); + ADD(alias, "in", match_flags&USB_DEVICE_ID_MATCH_INT_NUMBER, + bInterfaceNumber); + + add_wildcard(alias); + buf_printf(&mod->dev_table_buf, + "MODULE_ALIAS(\"%s\");\n", alias); +} + +/* Handles increment/decrement of BCD formatted integers */ +/* Returns the previous value, so it works like i++ or i-- */ +static unsigned int incbcd(unsigned int *bcd, + int inc, + unsigned char max, + size_t chars) +{ + unsigned int init = *bcd, i, j; + unsigned long long c, dec = 0; + + /* If bcd is not in BCD format, just increment */ + if (max > 0x9) { + *bcd += inc; + return init; + } + + /* Convert BCD to Decimal */ + for (i=0 ; i < chars ; i++) { + c = (*bcd >> (i << 2)) & 0xf; + c = c > 9 ? 9 : c; /* force to bcd just in case */ + for (j=0 ; j < i ; j++) + c = c * 10; + dec += c; + } + + /* Do our increment/decrement */ + dec += inc; + *bcd = 0; + + /* Convert back to BCD */ + for (i=0 ; i < chars ; i++) { + for (c=1,j=0 ; j < i ; j++) + c = c * 10; + c = (dec / c) % 10; + *bcd += c << (i << 2); + } + return init; +} + +static void do_usb_entry_multi(void *symval, struct module *mod) +{ + unsigned int devlo, devhi; + unsigned char chi, clo, max; + int ndigits; + + DEF_FIELD(symval, usb_device_id, match_flags); + DEF_FIELD(symval, usb_device_id, idVendor); + DEF_FIELD(symval, usb_device_id, idProduct); + DEF_FIELD(symval, usb_device_id, bcdDevice_lo); + DEF_FIELD(symval, usb_device_id, bcdDevice_hi); + DEF_FIELD(symval, usb_device_id, bDeviceClass); + DEF_FIELD(symval, usb_device_id, bInterfaceClass); + + devlo = match_flags & USB_DEVICE_ID_MATCH_DEV_LO ? + bcdDevice_lo : 0x0U; + devhi = match_flags & USB_DEVICE_ID_MATCH_DEV_HI ? + bcdDevice_hi : ~0x0U; + + /* Figure out if this entry is in bcd or hex format */ + max = 0x9; /* Default to decimal format */ + for (ndigits = 0 ; ndigits < sizeof(bcdDevice_lo) * 2 ; ndigits++) { + clo = (devlo >> (ndigits << 2)) & 0xf; + chi = ((devhi > 0x9999 ? 0x9999 : devhi) >> (ndigits << 2)) & 0xf; + if (clo > max || chi > max) { + max = 0xf; + break; + } + } + + /* + * Some modules (visor) have empty slots as placeholder for + * run-time specification that results in catch-all alias + */ + if (!(idVendor | idProduct | bDeviceClass | bInterfaceClass)) + return; + + /* Convert numeric bcdDevice range into fnmatch-able pattern(s) */ + for (ndigits = sizeof(bcdDevice_lo) * 2 - 1; devlo <= devhi; ndigits--) { + clo = devlo & 0xf; + chi = devhi & 0xf; + if (chi > max) /* If we are in bcd mode, truncate if necessary */ + chi = max; + devlo >>= 4; + devhi >>= 4; + + if (devlo == devhi || !ndigits) { + do_usb_entry(symval, devlo, ndigits, clo, chi, max, mod); + break; + } + + if (clo > 0x0) + do_usb_entry(symval, + incbcd(&devlo, 1, max, + sizeof(bcdDevice_lo) * 2), + ndigits, clo, max, max, mod); + + if (chi < max) + do_usb_entry(symval, + incbcd(&devhi, -1, max, + sizeof(bcdDevice_lo) * 2), + ndigits, 0x0, chi, max, mod); + } +} + +static void do_usb_table(void *symval, unsigned long size, + struct module *mod) +{ + unsigned int i; + const unsigned long id_size = SIZE_usb_device_id; + + device_id_check(mod->name, "usb", size, id_size, symval); + + /* Leave last one: it's the terminator. */ + size -= id_size; + + for (i = 0; i < size; i += id_size) + do_usb_entry_multi(symval + i, mod); +} + +static void do_of_entry_multi(void *symval, struct module *mod) +{ + char alias[500]; + int len; + char *tmp; + + DEF_FIELD_ADDR(symval, of_device_id, name); + DEF_FIELD_ADDR(symval, of_device_id, type); + DEF_FIELD_ADDR(symval, of_device_id, compatible); + + len = sprintf(alias, "of:N%sT%s", (*name)[0] ? *name : "*", + (*type)[0] ? *type : "*"); + + if ((*compatible)[0]) + sprintf(&alias[len], "%sC%s", (*type)[0] ? "*" : "", + *compatible); + + /* Replace all whitespace with underscores */ + for (tmp = alias; tmp && *tmp; tmp++) + if (isspace(*tmp)) + *tmp = '_'; + + buf_printf(&mod->dev_table_buf, "MODULE_ALIAS(\"%s\");\n", alias); + strcat(alias, "C"); + add_wildcard(alias); + buf_printf(&mod->dev_table_buf, "MODULE_ALIAS(\"%s\");\n", alias); +} + +static void do_of_table(void *symval, unsigned long size, + struct module *mod) +{ + unsigned int i; + const unsigned long id_size = SIZE_of_device_id; + + device_id_check(mod->name, "of", size, id_size, symval); + + /* Leave last one: it's the terminator. */ + size -= id_size; + + for (i = 0; i < size; i += id_size) + do_of_entry_multi(symval + i, mod); +} + +/* Looks like: hid:bNvNpN */ +static int do_hid_entry(const char *filename, + void *symval, char *alias) +{ + DEF_FIELD(symval, hid_device_id, bus); + DEF_FIELD(symval, hid_device_id, group); + DEF_FIELD(symval, hid_device_id, vendor); + DEF_FIELD(symval, hid_device_id, product); + + sprintf(alias, "hid:"); + ADD(alias, "b", bus != HID_BUS_ANY, bus); + ADD(alias, "g", group != HID_GROUP_ANY, group); + ADD(alias, "v", vendor != HID_ANY_ID, vendor); + ADD(alias, "p", product != HID_ANY_ID, product); + + return 1; +} + +/* Looks like: ieee1394:venNmoNspNverN */ +static int do_ieee1394_entry(const char *filename, + void *symval, char *alias) +{ + DEF_FIELD(symval, ieee1394_device_id, match_flags); + DEF_FIELD(symval, ieee1394_device_id, vendor_id); + DEF_FIELD(symval, ieee1394_device_id, model_id); + DEF_FIELD(symval, ieee1394_device_id, specifier_id); + DEF_FIELD(symval, ieee1394_device_id, version); + + strcpy(alias, "ieee1394:"); + ADD(alias, "ven", match_flags & IEEE1394_MATCH_VENDOR_ID, + vendor_id); + ADD(alias, "mo", match_flags & IEEE1394_MATCH_MODEL_ID, + model_id); + ADD(alias, "sp", match_flags & IEEE1394_MATCH_SPECIFIER_ID, + specifier_id); + ADD(alias, "ver", match_flags & IEEE1394_MATCH_VERSION, + version); + + add_wildcard(alias); + return 1; +} + +/* Looks like: pci:vNdNsvNsdNbcNscNiN. */ +static int do_pci_entry(const char *filename, + void *symval, char *alias) +{ + /* Class field can be divided into these three. */ + unsigned char baseclass, subclass, interface, + baseclass_mask, subclass_mask, interface_mask; + + DEF_FIELD(symval, pci_device_id, vendor); + DEF_FIELD(symval, pci_device_id, device); + DEF_FIELD(symval, pci_device_id, subvendor); + DEF_FIELD(symval, pci_device_id, subdevice); + DEF_FIELD(symval, pci_device_id, class); + DEF_FIELD(symval, pci_device_id, class_mask); + + strcpy(alias, "pci:"); + ADD(alias, "v", vendor != PCI_ANY_ID, vendor); + ADD(alias, "d", device != PCI_ANY_ID, device); + ADD(alias, "sv", subvendor != PCI_ANY_ID, subvendor); + ADD(alias, "sd", subdevice != PCI_ANY_ID, subdevice); + + baseclass = (class) >> 16; + baseclass_mask = (class_mask) >> 16; + subclass = (class) >> 8; + subclass_mask = (class_mask) >> 8; + interface = class; + interface_mask = class_mask; + + if ((baseclass_mask != 0 && baseclass_mask != 0xFF) + || (subclass_mask != 0 && subclass_mask != 0xFF) + || (interface_mask != 0 && interface_mask != 0xFF)) { + warn("Can't handle masks in %s:%04X\n", + filename, class_mask); + return 0; + } + + ADD(alias, "bc", baseclass_mask == 0xFF, baseclass); + ADD(alias, "sc", subclass_mask == 0xFF, subclass); + ADD(alias, "i", interface_mask == 0xFF, interface); + add_wildcard(alias); + return 1; +} + +/* looks like: "ccw:tNmNdtNdmN" */ +static int do_ccw_entry(const char *filename, + void *symval, char *alias) +{ + DEF_FIELD(symval, ccw_device_id, match_flags); + DEF_FIELD(symval, ccw_device_id, cu_type); + DEF_FIELD(symval, ccw_device_id, cu_model); + DEF_FIELD(symval, ccw_device_id, dev_type); + DEF_FIELD(symval, ccw_device_id, dev_model); + + strcpy(alias, "ccw:"); + ADD(alias, "t", match_flags&CCW_DEVICE_ID_MATCH_CU_TYPE, + cu_type); + ADD(alias, "m", match_flags&CCW_DEVICE_ID_MATCH_CU_MODEL, + cu_model); + ADD(alias, "dt", match_flags&CCW_DEVICE_ID_MATCH_DEVICE_TYPE, + dev_type); + ADD(alias, "dm", match_flags&CCW_DEVICE_ID_MATCH_DEVICE_MODEL, + dev_model); + add_wildcard(alias); + return 1; +} + +/* looks like: "ap:tN" */ +static int do_ap_entry(const char *filename, + void *symval, char *alias) +{ + DEF_FIELD(symval, ap_device_id, dev_type); + + sprintf(alias, "ap:t%02X*", dev_type); + return 1; +} + +/* looks like: "css:tN" */ +static int do_css_entry(const char *filename, + void *symval, char *alias) +{ + DEF_FIELD(symval, css_device_id, type); + + sprintf(alias, "css:t%01X", type); + return 1; +} + +/* Looks like: "serio:tyNprNidNexN" */ +static int do_serio_entry(const char *filename, + void *symval, char *alias) +{ + DEF_FIELD(symval, serio_device_id, type); + DEF_FIELD(symval, serio_device_id, proto); + DEF_FIELD(symval, serio_device_id, id); + DEF_FIELD(symval, serio_device_id, extra); + + strcpy(alias, "serio:"); + ADD(alias, "ty", type != SERIO_ANY, type); + ADD(alias, "pr", proto != SERIO_ANY, proto); + ADD(alias, "id", id != SERIO_ANY, id); + ADD(alias, "ex", extra != SERIO_ANY, extra); + + add_wildcard(alias); + return 1; +} + +/* looks like: "acpi:ACPI0003" or "acpi:PNP0C0B" or "acpi:LNXVIDEO" or + * "acpi:bbsspp" (bb=base-class, ss=sub-class, pp=prog-if) + * + * NOTE: Each driver should use one of the following : _HID, _CIDs + * or _CLS. Also, bb, ss, and pp can be substituted with ?? + * as don't care byte. + */ +static int do_acpi_entry(const char *filename, + void *symval, char *alias) +{ + DEF_FIELD_ADDR(symval, acpi_device_id, id); + DEF_FIELD_ADDR(symval, acpi_device_id, cls); + DEF_FIELD_ADDR(symval, acpi_device_id, cls_msk); + + if (id && strlen((const char *)*id)) + sprintf(alias, "acpi*:%s:*", *id); + else if (cls) { + int i, byte_shift, cnt = 0; + unsigned int msk; + + sprintf(&alias[cnt], "acpi*:"); + cnt = 6; + for (i = 1; i <= 3; i++) { + byte_shift = 8 * (3-i); + msk = (*cls_msk >> byte_shift) & 0xFF; + if (msk) + sprintf(&alias[cnt], "%02x", + (*cls >> byte_shift) & 0xFF); + else + sprintf(&alias[cnt], "??"); + cnt += 2; + } + sprintf(&alias[cnt], ":*"); + } + return 1; +} + +/* looks like: "pnp:dD" */ +static void do_pnp_device_entry(void *symval, unsigned long size, + struct module *mod) +{ + const unsigned long id_size = SIZE_pnp_device_id; + const unsigned int count = (size / id_size)-1; + unsigned int i; + + device_id_check(mod->name, "pnp", size, id_size, symval); + + for (i = 0; i < count; i++) { + DEF_FIELD_ADDR(symval + i*id_size, pnp_device_id, id); + char acpi_id[sizeof(*id)]; + int j; + + buf_printf(&mod->dev_table_buf, + "MODULE_ALIAS(\"pnp:d%s*\");\n", *id); + + /* fix broken pnp bus lowercasing */ + for (j = 0; j < sizeof(acpi_id); j++) + acpi_id[j] = toupper((*id)[j]); + buf_printf(&mod->dev_table_buf, + "MODULE_ALIAS(\"acpi*:%s:*\");\n", acpi_id); + } +} + +/* looks like: "pnp:dD" for every device of the card */ +static void do_pnp_card_entries(void *symval, unsigned long size, + struct module *mod) +{ + const unsigned long id_size = SIZE_pnp_card_device_id; + const unsigned int count = (size / id_size)-1; + unsigned int i; + + device_id_check(mod->name, "pnp", size, id_size, symval); + + for (i = 0; i < count; i++) { + unsigned int j; + DEF_FIELD_ADDR(symval + i * id_size, pnp_card_device_id, devs); + + for (j = 0; j < PNP_MAX_DEVICES; j++) { + const char *id = (char *)(*devs)[j].id; + int i2, j2; + int dup = 0; + + if (!id[0]) + break; + + /* find duplicate, already added value */ + for (i2 = 0; i2 < i && !dup; i2++) { + DEF_FIELD_ADDR_VAR(symval + i2 * id_size, + pnp_card_device_id, + devs, devs_dup); + + for (j2 = 0; j2 < PNP_MAX_DEVICES; j2++) { + const char *id2 = + (char *)(*devs_dup)[j2].id; + + if (!id2[0]) + break; + + if (!strcmp(id, id2)) { + dup = 1; + break; + } + } + } + + /* add an individual alias for every device entry */ + if (!dup) { + char acpi_id[PNP_ID_LEN]; + int k; + + buf_printf(&mod->dev_table_buf, + "MODULE_ALIAS(\"pnp:d%s*\");\n", id); + + /* fix broken pnp bus lowercasing */ + for (k = 0; k < sizeof(acpi_id); k++) + acpi_id[k] = toupper(id[k]); + buf_printf(&mod->dev_table_buf, + "MODULE_ALIAS(\"acpi*:%s:*\");\n", acpi_id); + } + } + } +} + +/* Looks like: pcmcia:mNcNfNfnNpfnNvaNvbNvcNvdN. */ +static int do_pcmcia_entry(const char *filename, + void *symval, char *alias) +{ + unsigned int i; + DEF_FIELD(symval, pcmcia_device_id, match_flags); + DEF_FIELD(symval, pcmcia_device_id, manf_id); + DEF_FIELD(symval, pcmcia_device_id, card_id); + DEF_FIELD(symval, pcmcia_device_id, func_id); + DEF_FIELD(symval, pcmcia_device_id, function); + DEF_FIELD(symval, pcmcia_device_id, device_no); + DEF_FIELD_ADDR(symval, pcmcia_device_id, prod_id_hash); + + for (i=0; i<4; i++) { + (*prod_id_hash)[i] = TO_NATIVE((*prod_id_hash)[i]); + } + + strcpy(alias, "pcmcia:"); + ADD(alias, "m", match_flags & PCMCIA_DEV_ID_MATCH_MANF_ID, + manf_id); + ADD(alias, "c", match_flags & PCMCIA_DEV_ID_MATCH_CARD_ID, + card_id); + ADD(alias, "f", match_flags & PCMCIA_DEV_ID_MATCH_FUNC_ID, + func_id); + ADD(alias, "fn", match_flags & PCMCIA_DEV_ID_MATCH_FUNCTION, + function); + ADD(alias, "pfn", match_flags & PCMCIA_DEV_ID_MATCH_DEVICE_NO, + device_no); + ADD(alias, "pa", match_flags & PCMCIA_DEV_ID_MATCH_PROD_ID1, (*prod_id_hash)[0]); + ADD(alias, "pb", match_flags & PCMCIA_DEV_ID_MATCH_PROD_ID2, (*prod_id_hash)[1]); + ADD(alias, "pc", match_flags & PCMCIA_DEV_ID_MATCH_PROD_ID3, (*prod_id_hash)[2]); + ADD(alias, "pd", match_flags & PCMCIA_DEV_ID_MATCH_PROD_ID4, (*prod_id_hash)[3]); + + add_wildcard(alias); + return 1; +} + +static int do_vio_entry(const char *filename, void *symval, + char *alias) +{ + char *tmp; + DEF_FIELD_ADDR(symval, vio_device_id, type); + DEF_FIELD_ADDR(symval, vio_device_id, compat); + + sprintf(alias, "vio:T%sS%s", (*type)[0] ? *type : "*", + (*compat)[0] ? *compat : "*"); + + /* Replace all whitespace with underscores */ + for (tmp = alias; tmp && *tmp; tmp++) + if (isspace (*tmp)) + *tmp = '_'; + + add_wildcard(alias); + return 1; +} + +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) + +static void do_input(char *alias, + kernel_ulong_t *arr, unsigned int min, unsigned int max) +{ + unsigned int i; + + for (i = min / BITS_PER_LONG; i < max / BITS_PER_LONG + 1; i++) + arr[i] = TO_NATIVE(arr[i]); + for (i = min; i < max; i++) + if (arr[i / BITS_PER_LONG] & (1L << (i%BITS_PER_LONG))) + sprintf(alias + strlen(alias), "%X,*", i); +} + +/* input:b0v0p0e0-eXkXrXaXmXlXsXfXwX where X is comma-separated %02X. */ +static int do_input_entry(const char *filename, void *symval, + char *alias) +{ + DEF_FIELD(symval, input_device_id, flags); + DEF_FIELD(symval, input_device_id, bustype); + DEF_FIELD(symval, input_device_id, vendor); + DEF_FIELD(symval, input_device_id, product); + DEF_FIELD(symval, input_device_id, version); + DEF_FIELD_ADDR(symval, input_device_id, evbit); + DEF_FIELD_ADDR(symval, input_device_id, keybit); + DEF_FIELD_ADDR(symval, input_device_id, relbit); + DEF_FIELD_ADDR(symval, input_device_id, absbit); + DEF_FIELD_ADDR(symval, input_device_id, mscbit); + DEF_FIELD_ADDR(symval, input_device_id, ledbit); + DEF_FIELD_ADDR(symval, input_device_id, sndbit); + DEF_FIELD_ADDR(symval, input_device_id, ffbit); + DEF_FIELD_ADDR(symval, input_device_id, swbit); + + sprintf(alias, "input:"); + + ADD(alias, "b", flags & INPUT_DEVICE_ID_MATCH_BUS, bustype); + ADD(alias, "v", flags & INPUT_DEVICE_ID_MATCH_VENDOR, vendor); + ADD(alias, "p", flags & INPUT_DEVICE_ID_MATCH_PRODUCT, product); + ADD(alias, "e", flags & INPUT_DEVICE_ID_MATCH_VERSION, version); + + sprintf(alias + strlen(alias), "-e*"); + if (flags & INPUT_DEVICE_ID_MATCH_EVBIT) + do_input(alias, *evbit, 0, INPUT_DEVICE_ID_EV_MAX); + sprintf(alias + strlen(alias), "k*"); + if (flags & INPUT_DEVICE_ID_MATCH_KEYBIT) + do_input(alias, *keybit, + INPUT_DEVICE_ID_KEY_MIN_INTERESTING, + INPUT_DEVICE_ID_KEY_MAX); + sprintf(alias + strlen(alias), "r*"); + if (flags & INPUT_DEVICE_ID_MATCH_RELBIT) + do_input(alias, *relbit, 0, INPUT_DEVICE_ID_REL_MAX); + sprintf(alias + strlen(alias), "a*"); + if (flags & INPUT_DEVICE_ID_MATCH_ABSBIT) + do_input(alias, *absbit, 0, INPUT_DEVICE_ID_ABS_MAX); + sprintf(alias + strlen(alias), "m*"); + if (flags & INPUT_DEVICE_ID_MATCH_MSCIT) + do_input(alias, *mscbit, 0, INPUT_DEVICE_ID_MSC_MAX); + sprintf(alias + strlen(alias), "l*"); + if (flags & INPUT_DEVICE_ID_MATCH_LEDBIT) + do_input(alias, *ledbit, 0, INPUT_DEVICE_ID_LED_MAX); + sprintf(alias + strlen(alias), "s*"); + if (flags & INPUT_DEVICE_ID_MATCH_SNDBIT) + do_input(alias, *sndbit, 0, INPUT_DEVICE_ID_SND_MAX); + sprintf(alias + strlen(alias), "f*"); + if (flags & INPUT_DEVICE_ID_MATCH_FFBIT) + do_input(alias, *ffbit, 0, INPUT_DEVICE_ID_FF_MAX); + sprintf(alias + strlen(alias), "w*"); + if (flags & INPUT_DEVICE_ID_MATCH_SWBIT) + do_input(alias, *swbit, 0, INPUT_DEVICE_ID_SW_MAX); + return 1; +} + +static int do_eisa_entry(const char *filename, void *symval, + char *alias) +{ + DEF_FIELD_ADDR(symval, eisa_device_id, sig); + if (sig[0]) + sprintf(alias, EISA_DEVICE_MODALIAS_FMT "*", *sig); + else + strcat(alias, "*"); + return 1; +} + +/* Looks like: parisc:tNhvNrevNsvN */ +static int do_parisc_entry(const char *filename, void *symval, + char *alias) +{ + DEF_FIELD(symval, parisc_device_id, hw_type); + DEF_FIELD(symval, parisc_device_id, hversion); + DEF_FIELD(symval, parisc_device_id, hversion_rev); + DEF_FIELD(symval, parisc_device_id, sversion); + + strcpy(alias, "parisc:"); + ADD(alias, "t", hw_type != PA_HWTYPE_ANY_ID, hw_type); + ADD(alias, "hv", hversion != PA_HVERSION_ANY_ID, hversion); + ADD(alias, "rev", hversion_rev != PA_HVERSION_REV_ANY_ID, hversion_rev); + ADD(alias, "sv", sversion != PA_SVERSION_ANY_ID, sversion); + + add_wildcard(alias); + return 1; +} + +/* Looks like: sdio:cNvNdN. */ +static int do_sdio_entry(const char *filename, + void *symval, char *alias) +{ + DEF_FIELD(symval, sdio_device_id, class); + DEF_FIELD(symval, sdio_device_id, vendor); + DEF_FIELD(symval, sdio_device_id, device); + + strcpy(alias, "sdio:"); + ADD(alias, "c", class != (__u8)SDIO_ANY_ID, class); + ADD(alias, "v", vendor != (__u16)SDIO_ANY_ID, vendor); + ADD(alias, "d", device != (__u16)SDIO_ANY_ID, device); + add_wildcard(alias); + return 1; +} + +/* Looks like: ssb:vNidNrevN. */ +static int do_ssb_entry(const char *filename, + void *symval, char *alias) +{ + DEF_FIELD(symval, ssb_device_id, vendor); + DEF_FIELD(symval, ssb_device_id, coreid); + DEF_FIELD(symval, ssb_device_id, revision); + + strcpy(alias, "ssb:"); + ADD(alias, "v", vendor != SSB_ANY_VENDOR, vendor); + ADD(alias, "id", coreid != SSB_ANY_ID, coreid); + ADD(alias, "rev", revision != SSB_ANY_REV, revision); + add_wildcard(alias); + return 1; +} + +/* Looks like: bcma:mNidNrevNclN. */ +static int do_bcma_entry(const char *filename, + void *symval, char *alias) +{ + DEF_FIELD(symval, bcma_device_id, manuf); + DEF_FIELD(symval, bcma_device_id, id); + DEF_FIELD(symval, bcma_device_id, rev); + DEF_FIELD(symval, bcma_device_id, class); + + strcpy(alias, "bcma:"); + ADD(alias, "m", manuf != BCMA_ANY_MANUF, manuf); + ADD(alias, "id", id != BCMA_ANY_ID, id); + ADD(alias, "rev", rev != BCMA_ANY_REV, rev); + ADD(alias, "cl", class != BCMA_ANY_CLASS, class); + add_wildcard(alias); + return 1; +} + +/* Looks like: virtio:dNvN */ +static int do_virtio_entry(const char *filename, void *symval, + char *alias) +{ + DEF_FIELD(symval, virtio_device_id, device); + DEF_FIELD(symval, virtio_device_id, vendor); + + strcpy(alias, "virtio:"); + ADD(alias, "d", device != VIRTIO_DEV_ANY_ID, device); + ADD(alias, "v", vendor != VIRTIO_DEV_ANY_ID, vendor); + + add_wildcard(alias); + return 1; +} + +/* + * Looks like: vmbus:guid + * Each byte of the guid will be represented by two hex characters + * in the name. + */ + +static int do_vmbus_entry(const char *filename, void *symval, + char *alias) +{ + int i; + DEF_FIELD_ADDR(symval, hv_vmbus_device_id, guid); + char guid_name[(sizeof(*guid) + 1) * 2]; + + for (i = 0; i < (sizeof(*guid) * 2); i += 2) + sprintf(&guid_name[i], "%02x", TO_NATIVE((guid->b)[i/2])); + + strcpy(alias, "vmbus:"); + strcat(alias, guid_name); + + return 1; +} + +/* Looks like: rpmsg:S */ +static int do_rpmsg_entry(const char *filename, void *symval, + char *alias) +{ + DEF_FIELD_ADDR(symval, rpmsg_device_id, name); + sprintf(alias, RPMSG_DEVICE_MODALIAS_FMT, *name); + + return 1; +} + +/* Looks like: i2c:S */ +static int do_i2c_entry(const char *filename, void *symval, + char *alias) +{ + DEF_FIELD_ADDR(symval, i2c_device_id, name); + sprintf(alias, I2C_MODULE_PREFIX "%s", *name); + + return 1; +} + +static int do_i3c_entry(const char *filename, void *symval, + char *alias) +{ + DEF_FIELD(symval, i3c_device_id, match_flags); + DEF_FIELD(symval, i3c_device_id, dcr); + DEF_FIELD(symval, i3c_device_id, manuf_id); + DEF_FIELD(symval, i3c_device_id, part_id); + DEF_FIELD(symval, i3c_device_id, extra_info); + + strcpy(alias, "i3c:"); + ADD(alias, "dcr", match_flags & I3C_MATCH_DCR, dcr); + ADD(alias, "manuf", match_flags & I3C_MATCH_MANUF, manuf_id); + ADD(alias, "part", match_flags & I3C_MATCH_PART, part_id); + ADD(alias, "ext", match_flags & I3C_MATCH_EXTRA_INFO, extra_info); + + return 1; +} + +/* Looks like: spi:S */ +static int do_spi_entry(const char *filename, void *symval, + char *alias) +{ + DEF_FIELD_ADDR(symval, spi_device_id, name); + sprintf(alias, SPI_MODULE_PREFIX "%s", *name); + + return 1; +} + +static const struct dmifield { + const char *prefix; + int field; +} dmi_fields[] = { + { "bvn", DMI_BIOS_VENDOR }, + { "bvr", DMI_BIOS_VERSION }, + { "bd", DMI_BIOS_DATE }, + { "br", DMI_BIOS_RELEASE }, + { "efr", DMI_EC_FIRMWARE_RELEASE }, + { "svn", DMI_SYS_VENDOR }, + { "pn", DMI_PRODUCT_NAME }, + { "pvr", DMI_PRODUCT_VERSION }, + { "rvn", DMI_BOARD_VENDOR }, + { "rn", DMI_BOARD_NAME }, + { "rvr", DMI_BOARD_VERSION }, + { "cvn", DMI_CHASSIS_VENDOR }, + { "ct", DMI_CHASSIS_TYPE }, + { "cvr", DMI_CHASSIS_VERSION }, + { NULL, DMI_NONE } +}; + +static void dmi_ascii_filter(char *d, const char *s) +{ + /* Filter out characters we don't want to see in the modalias string */ + for (; *s; s++) + if (*s > ' ' && *s < 127 && *s != ':') + *(d++) = *s; + + *d = 0; +} + + +static int do_dmi_entry(const char *filename, void *symval, + char *alias) +{ + int i, j; + DEF_FIELD_ADDR(symval, dmi_system_id, matches); + sprintf(alias, "dmi*"); + + for (i = 0; i < ARRAY_SIZE(dmi_fields); i++) { + for (j = 0; j < 4; j++) { + if ((*matches)[j].slot && + (*matches)[j].slot == dmi_fields[i].field) { + sprintf(alias + strlen(alias), ":%s*", + dmi_fields[i].prefix); + dmi_ascii_filter(alias + strlen(alias), + (*matches)[j].substr); + strcat(alias, "*"); + } + } + } + + strcat(alias, ":"); + return 1; +} + +static int do_platform_entry(const char *filename, + void *symval, char *alias) +{ + DEF_FIELD_ADDR(symval, platform_device_id, name); + sprintf(alias, PLATFORM_MODULE_PREFIX "%s", *name); + return 1; +} + +static int do_mdio_entry(const char *filename, + void *symval, char *alias) +{ + int i; + DEF_FIELD(symval, mdio_device_id, phy_id); + DEF_FIELD(symval, mdio_device_id, phy_id_mask); + + alias += sprintf(alias, MDIO_MODULE_PREFIX); + + for (i = 0; i < 32; i++) { + if (!((phy_id_mask >> (31-i)) & 1)) + *(alias++) = '?'; + else if ((phy_id >> (31-i)) & 1) + *(alias++) = '1'; + else + *(alias++) = '0'; + } + + /* Terminate the string */ + *alias = 0; + + return 1; +} + +/* Looks like: zorro:iN. */ +static int do_zorro_entry(const char *filename, void *symval, + char *alias) +{ + DEF_FIELD(symval, zorro_device_id, id); + strcpy(alias, "zorro:"); + ADD(alias, "i", id != ZORRO_WILDCARD, id); + return 1; +} + +/* looks like: "pnp:dD" */ +static int do_isapnp_entry(const char *filename, + void *symval, char *alias) +{ + DEF_FIELD(symval, isapnp_device_id, vendor); + DEF_FIELD(symval, isapnp_device_id, function); + sprintf(alias, "pnp:d%c%c%c%x%x%x%x*", + 'A' + ((vendor >> 2) & 0x3f) - 1, + 'A' + (((vendor & 3) << 3) | ((vendor >> 13) & 7)) - 1, + 'A' + ((vendor >> 8) & 0x1f) - 1, + (function >> 4) & 0x0f, function & 0x0f, + (function >> 12) & 0x0f, (function >> 8) & 0x0f); + return 1; +} + +/* Looks like: "ipack:fNvNdN". */ +static int do_ipack_entry(const char *filename, + void *symval, char *alias) +{ + DEF_FIELD(symval, ipack_device_id, format); + DEF_FIELD(symval, ipack_device_id, vendor); + DEF_FIELD(symval, ipack_device_id, device); + strcpy(alias, "ipack:"); + ADD(alias, "f", format != IPACK_ANY_FORMAT, format); + ADD(alias, "v", vendor != IPACK_ANY_ID, vendor); + ADD(alias, "d", device != IPACK_ANY_ID, device); + add_wildcard(alias); + return 1; +} + +/* + * Append a match expression for a single masked hex digit. + * outp points to a pointer to the character at which to append. + * *outp is updated on return to point just after the appended text, + * to facilitate further appending. + */ +static void append_nibble_mask(char **outp, + unsigned int nibble, unsigned int mask) +{ + char *p = *outp; + unsigned int i; + + switch (mask) { + case 0: + *p++ = '?'; + break; + + case 0xf: + p += sprintf(p, "%X", nibble); + break; + + default: + /* + * Dumbly emit a match pattern for all possible matching + * digits. This could be improved in some cases using ranges, + * but it has the advantage of being trivially correct, and is + * often optimal. + */ + *p++ = '['; + for (i = 0; i < 0x10; i++) + if ((i & mask) == nibble) + p += sprintf(p, "%X", i); + *p++ = ']'; + } + + /* Ensure that the string remains NUL-terminated: */ + *p = '\0'; + + /* Advance the caller's end-of-string pointer: */ + *outp = p; +} + +/* + * looks like: "amba:dN" + * + * N is exactly 8 digits, where each is an upper-case hex digit, or + * a ? or [] pattern matching exactly one digit. + */ +static int do_amba_entry(const char *filename, + void *symval, char *alias) +{ + unsigned int digit; + char *p = alias; + DEF_FIELD(symval, amba_id, id); + DEF_FIELD(symval, amba_id, mask); + + if ((id & mask) != id) + fatal("%s: Masked-off bit(s) of AMBA device ID are non-zero: " + "id=0x%08X, mask=0x%08X. Please fix this driver.\n", + filename, id, mask); + + p += sprintf(alias, "amba:d"); + for (digit = 0; digit < 8; digit++) + append_nibble_mask(&p, + (id >> (4 * (7 - digit))) & 0xf, + (mask >> (4 * (7 - digit))) & 0xf); + + return 1; +} + +/* + * looks like: "mipscdmm:tN" + * + * N is exactly 2 digits, where each is an upper-case hex digit, or + * a ? or [] pattern matching exactly one digit. + */ +static int do_mips_cdmm_entry(const char *filename, + void *symval, char *alias) +{ + DEF_FIELD(symval, mips_cdmm_device_id, type); + + sprintf(alias, "mipscdmm:t%02X*", type); + return 1; +} + +/* LOOKS like cpu:type:x86,venVVVVfamFFFFmodMMMM:feature:*,FEAT,* + * All fields are numbers. It would be nicer to use strings for vendor + * and feature, but getting those out of the build system here is too + * complicated. + */ + +static int do_x86cpu_entry(const char *filename, void *symval, + char *alias) +{ + DEF_FIELD(symval, x86_cpu_id, feature); + DEF_FIELD(symval, x86_cpu_id, family); + DEF_FIELD(symval, x86_cpu_id, model); + DEF_FIELD(symval, x86_cpu_id, vendor); + + strcpy(alias, "cpu:type:x86,"); + ADD(alias, "ven", vendor != X86_VENDOR_ANY, vendor); + ADD(alias, "fam", family != X86_FAMILY_ANY, family); + ADD(alias, "mod", model != X86_MODEL_ANY, model); + strcat(alias, ":feature:*"); + if (feature != X86_FEATURE_ANY) + sprintf(alias + strlen(alias), "%04X*", feature); + return 1; +} + +/* LOOKS like cpu:type:*:feature:*FEAT* */ +static int do_cpu_entry(const char *filename, void *symval, char *alias) +{ + DEF_FIELD(symval, cpu_feature, feature); + + sprintf(alias, "cpu:type:*:feature:*%04X*", feature); + return 1; +} + +/* Looks like: mei:S:uuid:N:* */ +static int do_mei_entry(const char *filename, void *symval, + char *alias) +{ + DEF_FIELD_ADDR(symval, mei_cl_device_id, name); + DEF_FIELD_ADDR(symval, mei_cl_device_id, uuid); + DEF_FIELD(symval, mei_cl_device_id, version); + + sprintf(alias, MEI_CL_MODULE_PREFIX); + sprintf(alias + strlen(alias), "%s:", (*name)[0] ? *name : "*"); + add_uuid(alias, *uuid); + ADD(alias, ":", version != MEI_CL_VERSION_ANY, version); + + strcat(alias, ":*"); + + return 1; +} + +/* Looks like: rapidio:vNdNavNadN */ +static int do_rio_entry(const char *filename, + void *symval, char *alias) +{ + DEF_FIELD(symval, rio_device_id, did); + DEF_FIELD(symval, rio_device_id, vid); + DEF_FIELD(symval, rio_device_id, asm_did); + DEF_FIELD(symval, rio_device_id, asm_vid); + + strcpy(alias, "rapidio:"); + ADD(alias, "v", vid != RIO_ANY_ID, vid); + ADD(alias, "d", did != RIO_ANY_ID, did); + ADD(alias, "av", asm_vid != RIO_ANY_ID, asm_vid); + ADD(alias, "ad", asm_did != RIO_ANY_ID, asm_did); + + add_wildcard(alias); + return 1; +} + +/* Looks like: ulpi:vNpN */ +static int do_ulpi_entry(const char *filename, void *symval, + char *alias) +{ + DEF_FIELD(symval, ulpi_device_id, vendor); + DEF_FIELD(symval, ulpi_device_id, product); + + sprintf(alias, "ulpi:v%04xp%04x", vendor, product); + + return 1; +} + +/* Looks like: hdaudio:vNrNaN */ +static int do_hda_entry(const char *filename, void *symval, char *alias) +{ + DEF_FIELD(symval, hda_device_id, vendor_id); + DEF_FIELD(symval, hda_device_id, rev_id); + DEF_FIELD(symval, hda_device_id, api_version); + + strcpy(alias, "hdaudio:"); + ADD(alias, "v", vendor_id != 0, vendor_id); + ADD(alias, "r", rev_id != 0, rev_id); + ADD(alias, "a", api_version != 0, api_version); + + add_wildcard(alias); + return 1; +} + +/* Looks like: sdw:mNpNvNcN */ +static int do_sdw_entry(const char *filename, void *symval, char *alias) +{ + DEF_FIELD(symval, sdw_device_id, mfg_id); + DEF_FIELD(symval, sdw_device_id, part_id); + DEF_FIELD(symval, sdw_device_id, sdw_version); + DEF_FIELD(symval, sdw_device_id, class_id); + + strcpy(alias, "sdw:"); + ADD(alias, "m", mfg_id != 0, mfg_id); + ADD(alias, "p", part_id != 0, part_id); + ADD(alias, "v", sdw_version != 0, sdw_version); + ADD(alias, "c", class_id != 0, class_id); + + add_wildcard(alias); + return 1; +} + +/* Looks like: fsl-mc:vNdN */ +static int do_fsl_mc_entry(const char *filename, void *symval, + char *alias) +{ + DEF_FIELD(symval, fsl_mc_device_id, vendor); + DEF_FIELD_ADDR(symval, fsl_mc_device_id, obj_type); + + sprintf(alias, "fsl-mc:v%08Xd%s", vendor, *obj_type); + return 1; +} + +/* Looks like: tbsvc:kSpNvNrN */ +static int do_tbsvc_entry(const char *filename, void *symval, char *alias) +{ + DEF_FIELD(symval, tb_service_id, match_flags); + DEF_FIELD_ADDR(symval, tb_service_id, protocol_key); + DEF_FIELD(symval, tb_service_id, protocol_id); + DEF_FIELD(symval, tb_service_id, protocol_version); + DEF_FIELD(symval, tb_service_id, protocol_revision); + + strcpy(alias, "tbsvc:"); + if (match_flags & TBSVC_MATCH_PROTOCOL_KEY) + sprintf(alias + strlen(alias), "k%s", *protocol_key); + else + strcat(alias + strlen(alias), "k*"); + ADD(alias, "p", match_flags & TBSVC_MATCH_PROTOCOL_ID, protocol_id); + ADD(alias, "v", match_flags & TBSVC_MATCH_PROTOCOL_VERSION, + protocol_version); + ADD(alias, "r", match_flags & TBSVC_MATCH_PROTOCOL_REVISION, + protocol_revision); + + add_wildcard(alias); + return 1; +} + +/* Looks like: typec:idNmN */ +static int do_typec_entry(const char *filename, void *symval, char *alias) +{ + DEF_FIELD(symval, typec_device_id, svid); + DEF_FIELD(symval, typec_device_id, mode); + + sprintf(alias, "typec:id%04X", svid); + ADD(alias, "m", mode != TYPEC_ANY_MODE, mode); + + return 1; +} + +/* Looks like: tee:uuid */ +static int do_tee_entry(const char *filename, void *symval, char *alias) +{ + DEF_FIELD(symval, tee_client_device_id, uuid); + + sprintf(alias, "tee:%02x%02x%02x%02x-%02x%02x-%02x%02x-%02x%02x-%02x%02x%02x%02x%02x%02x", + uuid.b[0], uuid.b[1], uuid.b[2], uuid.b[3], uuid.b[4], + uuid.b[5], uuid.b[6], uuid.b[7], uuid.b[8], uuid.b[9], + uuid.b[10], uuid.b[11], uuid.b[12], uuid.b[13], uuid.b[14], + uuid.b[15]); + + add_wildcard(alias); + return 1; +} + +/* Looks like: wmi:guid */ +static int do_wmi_entry(const char *filename, void *symval, char *alias) +{ + int len; + DEF_FIELD_ADDR(symval, wmi_device_id, guid_string); + + if (strlen(*guid_string) != UUID_STRING_LEN) { + warn("Invalid WMI device id 'wmi:%s' in '%s'\n", + *guid_string, filename); + return 0; + } + + len = snprintf(alias, ALIAS_SIZE, WMI_MODULE_PREFIX "%s", *guid_string); + if (len < 0 || len >= ALIAS_SIZE) { + warn("Could not generate all MODULE_ALIAS's in '%s'\n", + filename); + return 0; + } + return 1; +} + +/* Looks like: mhi:S */ +static int do_mhi_entry(const char *filename, void *symval, char *alias) +{ + DEF_FIELD_ADDR(symval, mhi_device_id, chan); + sprintf(alias, MHI_DEVICE_MODALIAS_FMT, *chan); + + return 1; +} + +static int do_auxiliary_entry(const char *filename, void *symval, char *alias) +{ + DEF_FIELD_ADDR(symval, auxiliary_device_id, name); + sprintf(alias, AUXILIARY_MODULE_PREFIX "%s", *name); + + return 1; +} + +/* Does namelen bytes of name exactly match the symbol? */ +static bool sym_is(const char *name, unsigned namelen, const char *symbol) +{ + if (namelen != strlen(symbol)) + return false; + + return memcmp(name, symbol, namelen) == 0; +} + +static void do_table(void *symval, unsigned long size, + unsigned long id_size, + const char *device_id, + int (*do_entry)(const char *filename, void *symval, char *alias), + struct module *mod) +{ + unsigned int i; + char alias[ALIAS_SIZE]; + + device_id_check(mod->name, device_id, size, id_size, symval); + /* Leave last one: it's the terminator. */ + size -= id_size; + + for (i = 0; i < size; i += id_size) { + if (do_entry(mod->name, symval+i, alias)) { + buf_printf(&mod->dev_table_buf, + "MODULE_ALIAS(\"%s\");\n", alias); + } + } +} + +static const struct devtable devtable[] = { + {"hid", SIZE_hid_device_id, do_hid_entry}, + {"ieee1394", SIZE_ieee1394_device_id, do_ieee1394_entry}, + {"pci", SIZE_pci_device_id, do_pci_entry}, + {"ccw", SIZE_ccw_device_id, do_ccw_entry}, + {"ap", SIZE_ap_device_id, do_ap_entry}, + {"css", SIZE_css_device_id, do_css_entry}, + {"serio", SIZE_serio_device_id, do_serio_entry}, + {"acpi", SIZE_acpi_device_id, do_acpi_entry}, + {"pcmcia", SIZE_pcmcia_device_id, do_pcmcia_entry}, + {"vio", SIZE_vio_device_id, do_vio_entry}, + {"input", SIZE_input_device_id, do_input_entry}, + {"eisa", SIZE_eisa_device_id, do_eisa_entry}, + {"parisc", SIZE_parisc_device_id, do_parisc_entry}, + {"sdio", SIZE_sdio_device_id, do_sdio_entry}, + {"ssb", SIZE_ssb_device_id, do_ssb_entry}, + {"bcma", SIZE_bcma_device_id, do_bcma_entry}, + {"virtio", SIZE_virtio_device_id, do_virtio_entry}, + {"vmbus", SIZE_hv_vmbus_device_id, do_vmbus_entry}, + {"rpmsg", SIZE_rpmsg_device_id, do_rpmsg_entry}, + {"i2c", SIZE_i2c_device_id, do_i2c_entry}, + {"i3c", SIZE_i3c_device_id, do_i3c_entry}, + {"spi", SIZE_spi_device_id, do_spi_entry}, + {"dmi", SIZE_dmi_system_id, do_dmi_entry}, + {"platform", SIZE_platform_device_id, do_platform_entry}, + {"mdio", SIZE_mdio_device_id, do_mdio_entry}, + {"zorro", SIZE_zorro_device_id, do_zorro_entry}, + {"isapnp", SIZE_isapnp_device_id, do_isapnp_entry}, + {"ipack", SIZE_ipack_device_id, do_ipack_entry}, + {"amba", SIZE_amba_id, do_amba_entry}, + {"mipscdmm", SIZE_mips_cdmm_device_id, do_mips_cdmm_entry}, + {"x86cpu", SIZE_x86_cpu_id, do_x86cpu_entry}, + {"cpu", SIZE_cpu_feature, do_cpu_entry}, + {"mei", SIZE_mei_cl_device_id, do_mei_entry}, + {"rapidio", SIZE_rio_device_id, do_rio_entry}, + {"ulpi", SIZE_ulpi_device_id, do_ulpi_entry}, + {"hdaudio", SIZE_hda_device_id, do_hda_entry}, + {"sdw", SIZE_sdw_device_id, do_sdw_entry}, + {"fslmc", SIZE_fsl_mc_device_id, do_fsl_mc_entry}, + {"tbsvc", SIZE_tb_service_id, do_tbsvc_entry}, + {"typec", SIZE_typec_device_id, do_typec_entry}, + {"tee", SIZE_tee_client_device_id, do_tee_entry}, + {"wmi", SIZE_wmi_device_id, do_wmi_entry}, + {"mhi", SIZE_mhi_device_id, do_mhi_entry}, + {"auxiliary", SIZE_auxiliary_device_id, do_auxiliary_entry}, +}; + +/* Create MODULE_ALIAS() statements. + * At this time, we cannot write the actual output C source yet, + * so we write into the mod->dev_table_buf buffer. */ +void handle_moddevtable(struct module *mod, struct elf_info *info, + Elf_Sym *sym, const char *symname) +{ + void *symval; + char *zeros = NULL; + const char *name, *identifier; + unsigned int namelen; + + /* We're looking for a section relative symbol */ + if (!sym->st_shndx || get_secindex(info, sym) >= info->num_sections) + return; + + /* We're looking for an object */ + if (ELF_ST_TYPE(sym->st_info) != STT_OBJECT) + return; + + /* All our symbols are of form __mod_<name>__<identifier>_device_table. */ + if (strncmp(symname, "__mod_", strlen("__mod_"))) + return; + name = symname + strlen("__mod_"); + namelen = strlen(name); + if (namelen < strlen("_device_table")) + return; + if (strcmp(name + namelen - strlen("_device_table"), "_device_table")) + return; + identifier = strstr(name, "__"); + if (!identifier) + return; + namelen = identifier - name; + + /* Handle all-NULL symbols allocated into .bss */ + if (info->sechdrs[get_secindex(info, sym)].sh_type & SHT_NOBITS) { + zeros = calloc(1, sym->st_size); + symval = zeros; + } else { + symval = (void *)info->hdr + + info->sechdrs[get_secindex(info, sym)].sh_offset + + sym->st_value; + } + + /* First handle the "special" cases */ + if (sym_is(name, namelen, "usb")) + do_usb_table(symval, sym->st_size, mod); + if (sym_is(name, namelen, "of")) + do_of_table(symval, sym->st_size, mod); + else if (sym_is(name, namelen, "pnp")) + do_pnp_device_entry(symval, sym->st_size, mod); + else if (sym_is(name, namelen, "pnp_card")) + do_pnp_card_entries(symval, sym->st_size, mod); + else { + int i; + + for (i = 0; i < ARRAY_SIZE(devtable); i++) { + const struct devtable *p = &devtable[i]; + + if (sym_is(name, namelen, p->device_id)) { + do_table(symval, sym->st_size, p->id_size, + p->device_id, p->do_entry, mod); + break; + } + } + } + free(zeros); +} + +/* Now add out buffered information to the generated C source */ +void add_moddevtable(struct buffer *buf, struct module *mod) +{ + buf_printf(buf, "\n"); + buf_write(buf, mod->dev_table_buf.p, mod->dev_table_buf.pos); + free(mod->dev_table_buf.p); +} diff --git a/src/net/scripts/mod/mk_elfconfig.c b/src/net/scripts/mod/mk_elfconfig.c new file mode 100644 index 0000000..680eade --- /dev/null +++ b/src/net/scripts/mod/mk_elfconfig.c @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0 +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <elf.h> + +int +main(int argc, char **argv) +{ + unsigned char ei[EI_NIDENT]; + union { short s; char c[2]; } endian_test; + + if (fread(ei, 1, EI_NIDENT, stdin) != EI_NIDENT) { + fprintf(stderr, "Error: input truncated\n"); + return 1; + } + if (memcmp(ei, ELFMAG, SELFMAG) != 0) { + fprintf(stderr, "Error: not ELF\n"); + return 1; + } + switch (ei[EI_CLASS]) { + case ELFCLASS32: + printf("#define KERNEL_ELFCLASS ELFCLASS32\n"); + break; + case ELFCLASS64: + printf("#define KERNEL_ELFCLASS ELFCLASS64\n"); + break; + default: + exit(1); + } + switch (ei[EI_DATA]) { + case ELFDATA2LSB: + printf("#define KERNEL_ELFDATA ELFDATA2LSB\n"); + break; + case ELFDATA2MSB: + printf("#define KERNEL_ELFDATA ELFDATA2MSB\n"); + break; + default: + exit(1); + } + + if (sizeof(unsigned long) == 4) { + printf("#define HOST_ELFCLASS ELFCLASS32\n"); + } else if (sizeof(unsigned long) == 8) { + printf("#define HOST_ELFCLASS ELFCLASS64\n"); + } + + endian_test.s = 0x0102; + if (memcmp(endian_test.c, "\x01\x02", 2) == 0) + printf("#define HOST_ELFDATA ELFDATA2MSB\n"); + else if (memcmp(endian_test.c, "\x02\x01", 2) == 0) + printf("#define HOST_ELFDATA ELFDATA2LSB\n"); + else + exit(1); + + return 0; +} diff --git a/src/net/scripts/mod/modpost.c b/src/net/scripts/mod/modpost.c new file mode 100644 index 0000000..8545e49 --- /dev/null +++ b/src/net/scripts/mod/modpost.c @@ -0,0 +1,2678 @@ +/* Postprocess module symbol versions + * + * Copyright 2003 Kai Germaschewski + * Copyright 2002-2004 Rusty Russell, IBM Corporation + * Copyright 2006-2008 Sam Ravnborg + * Based in part on module-init-tools/depmod.c,file2alias + * + * This software may be used and distributed according to the terms + * of the GNU General Public License, incorporated herein by reference. + * + * Usage: modpost vmlinux module1.o module2.o ... + */ + +#define _GNU_SOURCE +#include <elf.h> +#include <stdio.h> +#include <ctype.h> +#include <string.h> +#include <limits.h> +#include <stdbool.h> +#include <errno.h> +#include "modpost.h" +#include "../../include/linux/license.h" + +/* Are we using CONFIG_MODVERSIONS? */ +static int modversions = 0; +/* Warn about undefined symbols? (do so if we have vmlinux) */ +static int have_vmlinux = 0; +/* Is CONFIG_MODULE_SRCVERSION_ALL set? */ +static int all_versions = 0; +/* If we are modposting external module set to 1 */ +static int external_module = 0; +/* Only warn about unresolved symbols */ +static int warn_unresolved = 0; +/* How a symbol is exported */ +static int sec_mismatch_count = 0; +static int sec_mismatch_fatal = 0; +/* ignore missing files */ +static int ignore_missing_files; +/* If set to 1, only warn (instead of error) about missing ns imports */ +static int allow_missing_ns_imports; + +enum export { + export_plain, export_unused, export_gpl, + export_unused_gpl, export_gpl_future, export_unknown +}; + +/* In kernel, this size is defined in linux/module.h; + * here we use Elf_Addr instead of long for covering cross-compile + */ + +#define MODULE_NAME_LEN (64 - sizeof(Elf_Addr)) + +void __attribute__((format(printf, 2, 3))) +modpost_log(enum loglevel loglevel, const char *fmt, ...) +{ + va_list arglist; + + switch (loglevel) { + case LOG_WARN: + fprintf(stderr, "WARNING: "); + break; + case LOG_ERROR: + fprintf(stderr, "ERROR: "); + break; + case LOG_FATAL: + fprintf(stderr, "FATAL: "); + break; + default: /* invalid loglevel, ignore */ + break; + } + + fprintf(stderr, "modpost: "); + + va_start(arglist, fmt); + vfprintf(stderr, fmt, arglist); + va_end(arglist); + + if (loglevel == LOG_FATAL) + exit(1); +} + +static inline bool strends(const char *str, const char *postfix) +{ + if (strlen(str) < strlen(postfix)) + return false; + + return strcmp(str + strlen(str) - strlen(postfix), postfix) == 0; +} + +void *do_nofail(void *ptr, const char *expr) +{ + if (!ptr) + fatal("Memory allocation failure: %s.\n", expr); + + return ptr; +} + +char *read_text_file(const char *filename) +{ + struct stat st; + size_t nbytes; + int fd; + char *buf; + + fd = open(filename, O_RDONLY); + if (fd < 0) { + perror(filename); + exit(1); + } + + if (fstat(fd, &st) < 0) { + perror(filename); + exit(1); + } + + buf = NOFAIL(malloc(st.st_size + 1)); + + nbytes = st.st_size; + + while (nbytes) { + ssize_t bytes_read; + + bytes_read = read(fd, buf, nbytes); + if (bytes_read < 0) { + perror(filename); + exit(1); + } + + nbytes -= bytes_read; + } + buf[st.st_size] = '\0'; + + close(fd); + + return buf; +} + +char *get_line(char **stringp) +{ + char *orig = *stringp, *next; + + /* do not return the unwanted extra line at EOF */ + if (!orig || *orig == '\0') + return NULL; + + /* don't use strsep here, it is not available everywhere */ + next = strchr(orig, '\n'); + if (next) + *next++ = '\0'; + + *stringp = next; + + return orig; +} + +/* A list of all modules we processed */ +static struct module *modules; + +static struct module *find_module(const char *modname) +{ + struct module *mod; + + for (mod = modules; mod; mod = mod->next) + if (strcmp(mod->name, modname) == 0) + break; + return mod; +} + +static struct module *new_module(const char *modname) +{ + struct module *mod; + + mod = NOFAIL(malloc(sizeof(*mod) + strlen(modname) + 1)); + memset(mod, 0, sizeof(*mod)); + + /* add to list */ + strcpy(mod->name, modname); + mod->is_vmlinux = (strcmp(modname, "vmlinux") == 0); + mod->gpl_compatible = -1; + mod->next = modules; + modules = mod; + + if (mod->is_vmlinux) + have_vmlinux = 1; + + return mod; +} + +/* A hash of all exported symbols, + * struct symbol is also used for lists of unresolved symbols */ + +#define SYMBOL_HASH_SIZE 1024 + +struct symbol { + struct symbol *next; + struct module *module; + unsigned int crc; + int crc_valid; + char *namespace; + unsigned int weak:1; + unsigned int is_static:1; /* 1 if symbol is not global */ + enum export export; /* Type of export */ + char name[]; +}; + +static struct symbol *symbolhash[SYMBOL_HASH_SIZE]; + +/* This is based on the hash agorithm from gdbm, via tdb */ +static inline unsigned int tdb_hash(const char *name) +{ + unsigned value; /* Used to compute the hash value. */ + unsigned i; /* Used to cycle through random values. */ + + /* Set the initial value from the key size. */ + for (value = 0x238F13AF * strlen(name), i = 0; name[i]; i++) + value = (value + (((unsigned char *)name)[i] << (i*5 % 24))); + + return (1103515243 * value + 12345); +} + +/** + * Allocate a new symbols for use in the hash of exported symbols or + * the list of unresolved symbols per module + **/ +static struct symbol *alloc_symbol(const char *name, unsigned int weak, + struct symbol *next) +{ + struct symbol *s = NOFAIL(malloc(sizeof(*s) + strlen(name) + 1)); + + memset(s, 0, sizeof(*s)); + strcpy(s->name, name); + s->weak = weak; + s->next = next; + s->is_static = 1; + return s; +} + +/* For the hash of exported symbols */ +static struct symbol *new_symbol(const char *name, struct module *module, + enum export export) +{ + unsigned int hash; + + hash = tdb_hash(name) % SYMBOL_HASH_SIZE; + symbolhash[hash] = alloc_symbol(name, 0, symbolhash[hash]); + + return symbolhash[hash]; +} + +static struct symbol *find_symbol(const char *name) +{ + struct symbol *s; + + /* For our purposes, .foo matches foo. PPC64 needs this. */ + if (name[0] == '.') + name++; + + for (s = symbolhash[tdb_hash(name) % SYMBOL_HASH_SIZE]; s; s = s->next) { + if (strcmp(s->name, name) == 0) + return s; + } + return NULL; +} + +static bool contains_namespace(struct namespace_list *list, + const char *namespace) +{ + for (; list; list = list->next) + if (!strcmp(list->namespace, namespace)) + return true; + + return false; +} + +static void add_namespace(struct namespace_list **list, const char *namespace) +{ + struct namespace_list *ns_entry; + + if (!contains_namespace(*list, namespace)) { + ns_entry = NOFAIL(malloc(sizeof(struct namespace_list) + + strlen(namespace) + 1)); + strcpy(ns_entry->namespace, namespace); + ns_entry->next = *list; + *list = ns_entry; + } +} + +static bool module_imports_namespace(struct module *module, + const char *namespace) +{ + return contains_namespace(module->imported_namespaces, namespace); +} + +static const struct { + const char *str; + enum export export; +} export_list[] = { + { .str = "EXPORT_SYMBOL", .export = export_plain }, + { .str = "EXPORT_UNUSED_SYMBOL", .export = export_unused }, + { .str = "EXPORT_SYMBOL_GPL", .export = export_gpl }, + { .str = "EXPORT_UNUSED_SYMBOL_GPL", .export = export_unused_gpl }, + { .str = "EXPORT_SYMBOL_GPL_FUTURE", .export = export_gpl_future }, + { .str = "(unknown)", .export = export_unknown }, +}; + + +static const char *export_str(enum export ex) +{ + return export_list[ex].str; +} + +static enum export export_no(const char *s) +{ + int i; + + if (!s) + return export_unknown; + for (i = 0; export_list[i].export != export_unknown; i++) { + if (strcmp(export_list[i].str, s) == 0) + return export_list[i].export; + } + return export_unknown; +} + +static void *sym_get_data_by_offset(const struct elf_info *info, + unsigned int secindex, unsigned long offset) +{ + Elf_Shdr *sechdr = &info->sechdrs[secindex]; + + if (info->hdr->e_type != ET_REL) + offset -= sechdr->sh_addr; + + return (void *)info->hdr + sechdr->sh_offset + offset; +} + +static void *sym_get_data(const struct elf_info *info, const Elf_Sym *sym) +{ + return sym_get_data_by_offset(info, get_secindex(info, sym), + sym->st_value); +} + +static const char *sech_name(const struct elf_info *info, Elf_Shdr *sechdr) +{ + return sym_get_data_by_offset(info, info->secindex_strings, + sechdr->sh_name); +} + +static const char *sec_name(const struct elf_info *info, int secindex) +{ + return sech_name(info, &info->sechdrs[secindex]); +} + +#define strstarts(str, prefix) (strncmp(str, prefix, strlen(prefix)) == 0) + +static enum export export_from_secname(struct elf_info *elf, unsigned int sec) +{ + const char *secname = sec_name(elf, sec); + + if (strstarts(secname, "___ksymtab+")) + return export_plain; + else if (strstarts(secname, "___ksymtab_unused+")) + return export_unused; + else if (strstarts(secname, "___ksymtab_gpl+")) + return export_gpl; + else if (strstarts(secname, "___ksymtab_unused_gpl+")) + return export_unused_gpl; + else if (strstarts(secname, "___ksymtab_gpl_future+")) + return export_gpl_future; + else + return export_unknown; +} + +static enum export export_from_sec(struct elf_info *elf, unsigned int sec) +{ + if (sec == elf->export_sec) + return export_plain; + else if (sec == elf->export_unused_sec) + return export_unused; + else if (sec == elf->export_gpl_sec) + return export_gpl; + else if (sec == elf->export_unused_gpl_sec) + return export_unused_gpl; + else if (sec == elf->export_gpl_future_sec) + return export_gpl_future; + else + return export_unknown; +} + +static const char *namespace_from_kstrtabns(const struct elf_info *info, + const Elf_Sym *sym) +{ + const char *value = sym_get_data(info, sym); + return value[0] ? value : NULL; +} + +static void sym_update_namespace(const char *symname, const char *namespace) +{ + struct symbol *s = find_symbol(symname); + + /* + * That symbol should have been created earlier and thus this is + * actually an assertion. + */ + if (!s) { + merror("Could not update namespace(%s) for symbol %s\n", + namespace, symname); + return; + } + + free(s->namespace); + s->namespace = + namespace && namespace[0] ? NOFAIL(strdup(namespace)) : NULL; +} + +/** + * Add an exported symbol - it may have already been added without a + * CRC, in this case just update the CRC + **/ +static struct symbol *sym_add_exported(const char *name, struct module *mod, + enum export export) +{ + struct symbol *s = find_symbol(name); + + if (!s) { + s = new_symbol(name, mod, export); + } else if (!external_module || s->module->is_vmlinux || + s->module == mod) { + warn("%s: '%s' exported twice. Previous export was in %s%s\n", + mod->name, name, s->module->name, + s->module->is_vmlinux ? "" : ".ko"); + return s; + } + + s->module = mod; + s->export = export; + return s; +} + +static void sym_set_crc(const char *name, unsigned int crc) +{ + struct symbol *s = find_symbol(name); + + /* + * Ignore stand-alone __crc_*, which might be auto-generated symbols + * such as __*_veneer in ARM ELF. + */ + if (!s) + return; + + s->crc = crc; + s->crc_valid = 1; +} + +static void *grab_file(const char *filename, size_t *size) +{ + struct stat st; + void *map = MAP_FAILED; + int fd; + + fd = open(filename, O_RDONLY); + if (fd < 0) + return NULL; + if (fstat(fd, &st)) + goto failed; + + *size = st.st_size; + map = mmap(NULL, *size, PROT_READ|PROT_WRITE, MAP_PRIVATE, fd, 0); + +failed: + close(fd); + if (map == MAP_FAILED) + return NULL; + return map; +} + +static void release_file(void *file, size_t size) +{ + munmap(file, size); +} + +static int parse_elf(struct elf_info *info, const char *filename) +{ + unsigned int i; + Elf_Ehdr *hdr; + Elf_Shdr *sechdrs; + Elf_Sym *sym; + const char *secstrings; + unsigned int symtab_idx = ~0U, symtab_shndx_idx = ~0U; + + hdr = grab_file(filename, &info->size); + if (!hdr) { + if (ignore_missing_files) { + fprintf(stderr, "%s: %s (ignored)\n", filename, + strerror(errno)); + return 0; + } + perror(filename); + exit(1); + } + info->hdr = hdr; + if (info->size < sizeof(*hdr)) { + /* file too small, assume this is an empty .o file */ + return 0; + } + /* Is this a valid ELF file? */ + if ((hdr->e_ident[EI_MAG0] != ELFMAG0) || + (hdr->e_ident[EI_MAG1] != ELFMAG1) || + (hdr->e_ident[EI_MAG2] != ELFMAG2) || + (hdr->e_ident[EI_MAG3] != ELFMAG3)) { + /* Not an ELF file - silently ignore it */ + return 0; + } + /* Fix endianness in ELF header */ + hdr->e_type = TO_NATIVE(hdr->e_type); + hdr->e_machine = TO_NATIVE(hdr->e_machine); + hdr->e_version = TO_NATIVE(hdr->e_version); + hdr->e_entry = TO_NATIVE(hdr->e_entry); + hdr->e_phoff = TO_NATIVE(hdr->e_phoff); + hdr->e_shoff = TO_NATIVE(hdr->e_shoff); + hdr->e_flags = TO_NATIVE(hdr->e_flags); + hdr->e_ehsize = TO_NATIVE(hdr->e_ehsize); + hdr->e_phentsize = TO_NATIVE(hdr->e_phentsize); + hdr->e_phnum = TO_NATIVE(hdr->e_phnum); + hdr->e_shentsize = TO_NATIVE(hdr->e_shentsize); + hdr->e_shnum = TO_NATIVE(hdr->e_shnum); + hdr->e_shstrndx = TO_NATIVE(hdr->e_shstrndx); + sechdrs = (void *)hdr + hdr->e_shoff; + info->sechdrs = sechdrs; + + /* Check if file offset is correct */ + if (hdr->e_shoff > info->size) { + fatal("section header offset=%lu in file '%s' is bigger than filesize=%zu\n", + (unsigned long)hdr->e_shoff, filename, info->size); + return 0; + } + + if (hdr->e_shnum == SHN_UNDEF) { + /* + * There are more than 64k sections, + * read count from .sh_size. + */ + info->num_sections = TO_NATIVE(sechdrs[0].sh_size); + } + else { + info->num_sections = hdr->e_shnum; + } + if (hdr->e_shstrndx == SHN_XINDEX) { + info->secindex_strings = TO_NATIVE(sechdrs[0].sh_link); + } + else { + info->secindex_strings = hdr->e_shstrndx; + } + + /* Fix endianness in section headers */ + for (i = 0; i < info->num_sections; i++) { + sechdrs[i].sh_name = TO_NATIVE(sechdrs[i].sh_name); + sechdrs[i].sh_type = TO_NATIVE(sechdrs[i].sh_type); + sechdrs[i].sh_flags = TO_NATIVE(sechdrs[i].sh_flags); + sechdrs[i].sh_addr = TO_NATIVE(sechdrs[i].sh_addr); + sechdrs[i].sh_offset = TO_NATIVE(sechdrs[i].sh_offset); + sechdrs[i].sh_size = TO_NATIVE(sechdrs[i].sh_size); + sechdrs[i].sh_link = TO_NATIVE(sechdrs[i].sh_link); + sechdrs[i].sh_info = TO_NATIVE(sechdrs[i].sh_info); + sechdrs[i].sh_addralign = TO_NATIVE(sechdrs[i].sh_addralign); + sechdrs[i].sh_entsize = TO_NATIVE(sechdrs[i].sh_entsize); + } + /* Find symbol table. */ + secstrings = (void *)hdr + sechdrs[info->secindex_strings].sh_offset; + for (i = 1; i < info->num_sections; i++) { + const char *secname; + int nobits = sechdrs[i].sh_type == SHT_NOBITS; + + if (!nobits && sechdrs[i].sh_offset > info->size) { + fatal("%s is truncated. sechdrs[i].sh_offset=%lu > " + "sizeof(*hrd)=%zu\n", filename, + (unsigned long)sechdrs[i].sh_offset, + sizeof(*hdr)); + return 0; + } + secname = secstrings + sechdrs[i].sh_name; + if (strcmp(secname, ".modinfo") == 0) { + if (nobits) + fatal("%s has NOBITS .modinfo\n", filename); + info->modinfo = (void *)hdr + sechdrs[i].sh_offset; + info->modinfo_len = sechdrs[i].sh_size; + } else if (strcmp(secname, "__ksymtab") == 0) + info->export_sec = i; + else if (strcmp(secname, "__ksymtab_unused") == 0) + info->export_unused_sec = i; + else if (strcmp(secname, "__ksymtab_gpl") == 0) + info->export_gpl_sec = i; + else if (strcmp(secname, "__ksymtab_unused_gpl") == 0) + info->export_unused_gpl_sec = i; + else if (strcmp(secname, "__ksymtab_gpl_future") == 0) + info->export_gpl_future_sec = i; + + if (sechdrs[i].sh_type == SHT_SYMTAB) { + unsigned int sh_link_idx; + symtab_idx = i; + info->symtab_start = (void *)hdr + + sechdrs[i].sh_offset; + info->symtab_stop = (void *)hdr + + sechdrs[i].sh_offset + sechdrs[i].sh_size; + sh_link_idx = sechdrs[i].sh_link; + info->strtab = (void *)hdr + + sechdrs[sh_link_idx].sh_offset; + } + + /* 32bit section no. table? ("more than 64k sections") */ + if (sechdrs[i].sh_type == SHT_SYMTAB_SHNDX) { + symtab_shndx_idx = i; + info->symtab_shndx_start = (void *)hdr + + sechdrs[i].sh_offset; + info->symtab_shndx_stop = (void *)hdr + + sechdrs[i].sh_offset + sechdrs[i].sh_size; + } + } + if (!info->symtab_start) + fatal("%s has no symtab?\n", filename); + + /* Fix endianness in symbols */ + for (sym = info->symtab_start; sym < info->symtab_stop; sym++) { + sym->st_shndx = TO_NATIVE(sym->st_shndx); + sym->st_name = TO_NATIVE(sym->st_name); + sym->st_value = TO_NATIVE(sym->st_value); + sym->st_size = TO_NATIVE(sym->st_size); + } + + if (symtab_shndx_idx != ~0U) { + Elf32_Word *p; + if (symtab_idx != sechdrs[symtab_shndx_idx].sh_link) + fatal("%s: SYMTAB_SHNDX has bad sh_link: %u!=%u\n", + filename, sechdrs[symtab_shndx_idx].sh_link, + symtab_idx); + /* Fix endianness */ + for (p = info->symtab_shndx_start; p < info->symtab_shndx_stop; + p++) + *p = TO_NATIVE(*p); + } + + return 1; +} + +static void parse_elf_finish(struct elf_info *info) +{ + release_file(info->hdr, info->size); +} + +static int ignore_undef_symbol(struct elf_info *info, const char *symname) +{ + /* ignore __this_module, it will be resolved shortly */ + if (strcmp(symname, "__this_module") == 0) + return 1; + /* ignore global offset table */ + if (strcmp(symname, "_GLOBAL_OFFSET_TABLE_") == 0) + return 1; + if (info->hdr->e_machine == EM_PPC) + /* Special register function linked on all modules during final link of .ko */ + if (strstarts(symname, "_restgpr_") || + strstarts(symname, "_savegpr_") || + strstarts(symname, "_rest32gpr_") || + strstarts(symname, "_save32gpr_") || + strstarts(symname, "_restvr_") || + strstarts(symname, "_savevr_")) + return 1; + if (info->hdr->e_machine == EM_PPC64) + /* Special register function linked on all modules during final link of .ko */ + if (strstarts(symname, "_restgpr0_") || + strstarts(symname, "_savegpr0_") || + strstarts(symname, "_restvr_") || + strstarts(symname, "_savevr_") || + strcmp(symname, ".TOC.") == 0) + return 1; + /* Do not ignore this symbol */ + return 0; +} + +static void handle_modversion(const struct module *mod, + const struct elf_info *info, + const Elf_Sym *sym, const char *symname) +{ + unsigned int crc; + + if (sym->st_shndx == SHN_UNDEF) { + warn("EXPORT symbol \"%s\" [%s%s] version generation failed, symbol will not be versioned.\n", + symname, mod->name, mod->is_vmlinux ? "" : ".ko"); + return; + } + + if (sym->st_shndx == SHN_ABS) { + crc = sym->st_value; + } else { + unsigned int *crcp; + + /* symbol points to the CRC in the ELF object */ + crcp = sym_get_data(info, sym); + crc = TO_NATIVE(*crcp); + } + sym_set_crc(symname, crc); +} + +static void handle_symbol(struct module *mod, struct elf_info *info, + const Elf_Sym *sym, const char *symname) +{ + enum export export; + const char *name; + + if (strstarts(symname, "__ksymtab")) + export = export_from_secname(info, get_secindex(info, sym)); + else + export = export_from_sec(info, get_secindex(info, sym)); + + switch (sym->st_shndx) { + case SHN_COMMON: + if (strstarts(symname, "__gnu_lto_")) { + /* Should warn here, but modpost runs before the linker */ + } else + warn("\"%s\" [%s] is COMMON symbol\n", symname, mod->name); + break; + case SHN_UNDEF: + /* undefined symbol */ + if (ELF_ST_BIND(sym->st_info) != STB_GLOBAL && + ELF_ST_BIND(sym->st_info) != STB_WEAK) + break; + if (ignore_undef_symbol(info, symname)) + break; + if (info->hdr->e_machine == EM_SPARC || + info->hdr->e_machine == EM_SPARCV9) { + /* Ignore register directives. */ + if (ELF_ST_TYPE(sym->st_info) == STT_SPARC_REGISTER) + break; + if (symname[0] == '.') { + char *munged = NOFAIL(strdup(symname)); + munged[0] = '_'; + munged[1] = toupper(munged[1]); + symname = munged; + } + } + + mod->unres = alloc_symbol(symname, + ELF_ST_BIND(sym->st_info) == STB_WEAK, + mod->unres); + break; + default: + /* All exported symbols */ + if (strstarts(symname, "__ksymtab_")) { + name = symname + strlen("__ksymtab_"); + sym_add_exported(name, mod, export); + } + if (strcmp(symname, "init_module") == 0) + mod->has_init = 1; + if (strcmp(symname, "cleanup_module") == 0) + mod->has_cleanup = 1; + break; + } +} + +/** + * Parse tag=value strings from .modinfo section + **/ +static char *next_string(char *string, unsigned long *secsize) +{ + /* Skip non-zero chars */ + while (string[0]) { + string++; + if ((*secsize)-- <= 1) + return NULL; + } + + /* Skip any zero padding. */ + while (!string[0]) { + string++; + if ((*secsize)-- <= 1) + return NULL; + } + return string; +} + +static char *get_next_modinfo(struct elf_info *info, const char *tag, + char *prev) +{ + char *p; + unsigned int taglen = strlen(tag); + char *modinfo = info->modinfo; + unsigned long size = info->modinfo_len; + + if (prev) { + size -= prev - modinfo; + modinfo = next_string(prev, &size); + } + + for (p = modinfo; p; p = next_string(p, &size)) { + if (strncmp(p, tag, taglen) == 0 && p[taglen] == '=') + return p + taglen + 1; + } + return NULL; +} + +static char *get_modinfo(struct elf_info *info, const char *tag) + +{ + return get_next_modinfo(info, tag, NULL); +} + +/** + * Test if string s ends in string sub + * return 0 if match + **/ +static int strrcmp(const char *s, const char *sub) +{ + int slen, sublen; + + if (!s || !sub) + return 1; + + slen = strlen(s); + sublen = strlen(sub); + + if ((slen == 0) || (sublen == 0)) + return 1; + + if (sublen > slen) + return 1; + + return memcmp(s + slen - sublen, sub, sublen); +} + +static const char *sym_name(struct elf_info *elf, Elf_Sym *sym) +{ + if (sym) + return elf->strtab + sym->st_name; + else + return "(unknown)"; +} + +/* The pattern is an array of simple patterns. + * "foo" will match an exact string equal to "foo" + * "*foo" will match a string that ends with "foo" + * "foo*" will match a string that begins with "foo" + * "*foo*" will match a string that contains "foo" + */ +static int match(const char *sym, const char * const pat[]) +{ + const char *p; + while (*pat) { + p = *pat++; + const char *endp = p + strlen(p) - 1; + + /* "*foo*" */ + if (*p == '*' && *endp == '*') { + char *bare = NOFAIL(strndup(p + 1, strlen(p) - 2)); + char *here = strstr(sym, bare); + + free(bare); + if (here != NULL) + return 1; + } + /* "*foo" */ + else if (*p == '*') { + if (strrcmp(sym, p + 1) == 0) + return 1; + } + /* "foo*" */ + else if (*endp == '*') { + if (strncmp(sym, p, strlen(p) - 1) == 0) + return 1; + } + /* no wildcards */ + else { + if (strcmp(p, sym) == 0) + return 1; + } + } + /* no match */ + return 0; +} + +/* sections that we do not want to do full section mismatch check on */ +static const char *const section_white_list[] = +{ + ".comment*", + ".debug*", + ".cranges", /* sh64 */ + ".zdebug*", /* Compressed debug sections. */ + ".GCC.command.line", /* record-gcc-switches */ + ".mdebug*", /* alpha, score, mips etc. */ + ".pdr", /* alpha, score, mips etc. */ + ".stab*", + ".note*", + ".got*", + ".toc*", + ".xt.prop", /* xtensa */ + ".xt.lit", /* xtensa */ + ".arcextmap*", /* arc */ + ".gnu.linkonce.arcext*", /* arc : modules */ + ".cmem*", /* EZchip */ + ".fmt_slot*", /* EZchip */ + ".gnu.lto*", + ".discard.*", + NULL +}; + +/* + * This is used to find sections missing the SHF_ALLOC flag. + * The cause of this is often a section specified in assembler + * without "ax" / "aw". + */ +static void check_section(const char *modname, struct elf_info *elf, + Elf_Shdr *sechdr) +{ + const char *sec = sech_name(elf, sechdr); + + if (sechdr->sh_type == SHT_PROGBITS && + !(sechdr->sh_flags & SHF_ALLOC) && + !match(sec, section_white_list)) { + warn("%s (%s): unexpected non-allocatable section.\n" + "Did you forget to use \"ax\"/\"aw\" in a .S file?\n" + "Note that for example <linux/init.h> contains\n" + "section definitions for use in .S files.\n\n", + modname, sec); + } +} + + + +#define ALL_INIT_DATA_SECTIONS \ + ".init.setup", ".init.rodata", ".meminit.rodata", \ + ".init.data", ".meminit.data" +#define ALL_EXIT_DATA_SECTIONS \ + ".exit.data", ".memexit.data" + +#define ALL_INIT_TEXT_SECTIONS \ + ".init.text", ".meminit.text" +#define ALL_EXIT_TEXT_SECTIONS \ + ".exit.text", ".memexit.text" + +#define ALL_PCI_INIT_SECTIONS \ + ".pci_fixup_early", ".pci_fixup_header", ".pci_fixup_final", \ + ".pci_fixup_enable", ".pci_fixup_resume", \ + ".pci_fixup_resume_early", ".pci_fixup_suspend" + +#define ALL_XXXINIT_SECTIONS MEM_INIT_SECTIONS +#define ALL_XXXEXIT_SECTIONS MEM_EXIT_SECTIONS + +#define ALL_INIT_SECTIONS INIT_SECTIONS, ALL_XXXINIT_SECTIONS +#define ALL_EXIT_SECTIONS EXIT_SECTIONS, ALL_XXXEXIT_SECTIONS + +#define DATA_SECTIONS ".data", ".data.rel" +#define TEXT_SECTIONS ".text", ".text.unlikely", ".sched.text", \ + ".kprobes.text", ".cpuidle.text", ".noinstr.text" +#define OTHER_TEXT_SECTIONS ".ref.text", ".head.text", ".spinlock.text", \ + ".fixup", ".entry.text", ".exception.text", ".text.*", \ + ".coldtext" + +#define INIT_SECTIONS ".init.*" +#define MEM_INIT_SECTIONS ".meminit.*" + +#define EXIT_SECTIONS ".exit.*" +#define MEM_EXIT_SECTIONS ".memexit.*" + +#define ALL_TEXT_SECTIONS ALL_INIT_TEXT_SECTIONS, ALL_EXIT_TEXT_SECTIONS, \ + TEXT_SECTIONS, OTHER_TEXT_SECTIONS + +/* init data sections */ +static const char *const init_data_sections[] = + { ALL_INIT_DATA_SECTIONS, NULL }; + +/* all init sections */ +static const char *const init_sections[] = { ALL_INIT_SECTIONS, NULL }; + +/* All init and exit sections (code + data) */ +static const char *const init_exit_sections[] = + {ALL_INIT_SECTIONS, ALL_EXIT_SECTIONS, NULL }; + +/* all text sections */ +static const char *const text_sections[] = { ALL_TEXT_SECTIONS, NULL }; + +/* data section */ +static const char *const data_sections[] = { DATA_SECTIONS, NULL }; + + +/* symbols in .data that may refer to init/exit sections */ +#define DEFAULT_SYMBOL_WHITE_LIST \ + "*driver", \ + "*_template", /* scsi uses *_template a lot */ \ + "*_timer", /* arm uses ops structures named _timer a lot */ \ + "*_sht", /* scsi also used *_sht to some extent */ \ + "*_ops", \ + "*_probe", \ + "*_probe_one", \ + "*_console" + +static const char *const head_sections[] = { ".head.text*", NULL }; +static const char *const linker_symbols[] = + { "__init_begin", "_sinittext", "_einittext", NULL }; +static const char *const optim_symbols[] = { "*.constprop.*", NULL }; + +enum mismatch { + TEXT_TO_ANY_INIT, + DATA_TO_ANY_INIT, + TEXT_TO_ANY_EXIT, + DATA_TO_ANY_EXIT, + XXXINIT_TO_SOME_INIT, + XXXEXIT_TO_SOME_EXIT, + ANY_INIT_TO_ANY_EXIT, + ANY_EXIT_TO_ANY_INIT, + EXPORT_TO_INIT_EXIT, + EXTABLE_TO_NON_TEXT, +}; + +/** + * Describe how to match sections on different criterias: + * + * @fromsec: Array of sections to be matched. + * + * @bad_tosec: Relocations applied to a section in @fromsec to a section in + * this array is forbidden (black-list). Can be empty. + * + * @good_tosec: Relocations applied to a section in @fromsec must be + * targetting sections in this array (white-list). Can be empty. + * + * @mismatch: Type of mismatch. + * + * @symbol_white_list: Do not match a relocation to a symbol in this list + * even if it is targetting a section in @bad_to_sec. + * + * @handler: Specific handler to call when a match is found. If NULL, + * default_mismatch_handler() will be called. + * + */ +struct sectioncheck { + const char *fromsec[20]; + const char *bad_tosec[20]; + const char *good_tosec[20]; + enum mismatch mismatch; + const char *symbol_white_list[20]; + void (*handler)(const char *modname, struct elf_info *elf, + const struct sectioncheck* const mismatch, + Elf_Rela *r, Elf_Sym *sym, const char *fromsec); + +}; + +static void extable_mismatch_handler(const char *modname, struct elf_info *elf, + const struct sectioncheck* const mismatch, + Elf_Rela *r, Elf_Sym *sym, + const char *fromsec); + +static const struct sectioncheck sectioncheck[] = { +/* Do not reference init/exit code/data from + * normal code and data + */ +{ + .fromsec = { TEXT_SECTIONS, NULL }, + .bad_tosec = { ALL_INIT_SECTIONS, NULL }, + .mismatch = TEXT_TO_ANY_INIT, + .symbol_white_list = { DEFAULT_SYMBOL_WHITE_LIST, NULL }, +}, +{ + .fromsec = { DATA_SECTIONS, NULL }, + .bad_tosec = { ALL_XXXINIT_SECTIONS, NULL }, + .mismatch = DATA_TO_ANY_INIT, + .symbol_white_list = { DEFAULT_SYMBOL_WHITE_LIST, NULL }, +}, +{ + .fromsec = { DATA_SECTIONS, NULL }, + .bad_tosec = { INIT_SECTIONS, NULL }, + .mismatch = DATA_TO_ANY_INIT, + .symbol_white_list = { + "*_template", "*_timer", "*_sht", "*_ops", + "*_probe", "*_probe_one", "*_console", NULL + }, +}, +{ + .fromsec = { TEXT_SECTIONS, NULL }, + .bad_tosec = { ALL_EXIT_SECTIONS, NULL }, + .mismatch = TEXT_TO_ANY_EXIT, + .symbol_white_list = { DEFAULT_SYMBOL_WHITE_LIST, NULL }, +}, +{ + .fromsec = { DATA_SECTIONS, NULL }, + .bad_tosec = { ALL_EXIT_SECTIONS, NULL }, + .mismatch = DATA_TO_ANY_EXIT, + .symbol_white_list = { DEFAULT_SYMBOL_WHITE_LIST, NULL }, +}, +/* Do not reference init code/data from meminit code/data */ +{ + .fromsec = { ALL_XXXINIT_SECTIONS, NULL }, + .bad_tosec = { INIT_SECTIONS, NULL }, + .mismatch = XXXINIT_TO_SOME_INIT, + .symbol_white_list = { DEFAULT_SYMBOL_WHITE_LIST, NULL }, +}, +/* Do not reference exit code/data from memexit code/data */ +{ + .fromsec = { ALL_XXXEXIT_SECTIONS, NULL }, + .bad_tosec = { EXIT_SECTIONS, NULL }, + .mismatch = XXXEXIT_TO_SOME_EXIT, + .symbol_white_list = { DEFAULT_SYMBOL_WHITE_LIST, NULL }, +}, +/* Do not use exit code/data from init code */ +{ + .fromsec = { ALL_INIT_SECTIONS, NULL }, + .bad_tosec = { ALL_EXIT_SECTIONS, NULL }, + .mismatch = ANY_INIT_TO_ANY_EXIT, + .symbol_white_list = { DEFAULT_SYMBOL_WHITE_LIST, NULL }, +}, +/* Do not use init code/data from exit code */ +{ + .fromsec = { ALL_EXIT_SECTIONS, NULL }, + .bad_tosec = { ALL_INIT_SECTIONS, NULL }, + .mismatch = ANY_EXIT_TO_ANY_INIT, + .symbol_white_list = { DEFAULT_SYMBOL_WHITE_LIST, NULL }, +}, +{ + .fromsec = { ALL_PCI_INIT_SECTIONS, NULL }, + .bad_tosec = { INIT_SECTIONS, NULL }, + .mismatch = ANY_INIT_TO_ANY_EXIT, + .symbol_white_list = { NULL }, +}, +/* Do not export init/exit functions or data */ +{ + .fromsec = { "___ksymtab*", NULL }, + .bad_tosec = { INIT_SECTIONS, EXIT_SECTIONS, NULL }, + .mismatch = EXPORT_TO_INIT_EXIT, + .symbol_white_list = { DEFAULT_SYMBOL_WHITE_LIST, NULL }, +}, +{ + .fromsec = { "__ex_table", NULL }, + /* If you're adding any new black-listed sections in here, consider + * adding a special 'printer' for them in scripts/check_extable. + */ + .bad_tosec = { ".altinstr_replacement", NULL }, + .good_tosec = {ALL_TEXT_SECTIONS , NULL}, + .mismatch = EXTABLE_TO_NON_TEXT, + .handler = extable_mismatch_handler, +} +}; + +static const struct sectioncheck *section_mismatch( + const char *fromsec, const char *tosec) +{ + int i; + int elems = sizeof(sectioncheck) / sizeof(struct sectioncheck); + const struct sectioncheck *check = §ioncheck[0]; + + /* + * The target section could be the SHT_NUL section when we're + * handling relocations to un-resolved symbols, trying to match it + * doesn't make much sense and causes build failures on parisc + * architectures. + */ + if (*tosec == '\0') + return NULL; + + for (i = 0; i < elems; i++) { + if (match(fromsec, check->fromsec)) { + if (check->bad_tosec[0] && match(tosec, check->bad_tosec)) + return check; + if (check->good_tosec[0] && !match(tosec, check->good_tosec)) + return check; + } + check++; + } + return NULL; +} + +/** + * Whitelist to allow certain references to pass with no warning. + * + * Pattern 1: + * If a module parameter is declared __initdata and permissions=0 + * then this is legal despite the warning generated. + * We cannot see value of permissions here, so just ignore + * this pattern. + * The pattern is identified by: + * tosec = .init.data + * fromsec = .data* + * atsym =__param* + * + * Pattern 1a: + * module_param_call() ops can refer to __init set function if permissions=0 + * The pattern is identified by: + * tosec = .init.text + * fromsec = .data* + * atsym = __param_ops_* + * + * Pattern 2: + * Many drivers utilise a *driver container with references to + * add, remove, probe functions etc. + * the pattern is identified by: + * tosec = init or exit section + * fromsec = data section + * atsym = *driver, *_template, *_sht, *_ops, *_probe, + * *probe_one, *_console, *_timer + * + * Pattern 3: + * Whitelist all references from .head.text to any init section + * + * Pattern 4: + * Some symbols belong to init section but still it is ok to reference + * these from non-init sections as these symbols don't have any memory + * allocated for them and symbol address and value are same. So even + * if init section is freed, its ok to reference those symbols. + * For ex. symbols marking the init section boundaries. + * This pattern is identified by + * refsymname = __init_begin, _sinittext, _einittext + * + * Pattern 5: + * GCC may optimize static inlines when fed constant arg(s) resulting + * in functions like cpumask_empty() -- generating an associated symbol + * cpumask_empty.constprop.3 that appears in the audit. If the const that + * is passed in comes from __init, like say nmi_ipi_mask, we get a + * meaningless section warning. May need to add isra symbols too... + * This pattern is identified by + * tosec = init section + * fromsec = text section + * refsymname = *.constprop.* + * + * Pattern 6: + * Hide section mismatch warnings for ELF local symbols. The goal + * is to eliminate false positive modpost warnings caused by + * compiler-generated ELF local symbol names such as ".LANCHOR1". + * Autogenerated symbol names bypass modpost's "Pattern 2" + * whitelisting, which relies on pattern-matching against symbol + * names to work. (One situation where gcc can autogenerate ELF + * local symbols is when "-fsection-anchors" is used.) + **/ +static int secref_whitelist(const struct sectioncheck *mismatch, + const char *fromsec, const char *fromsym, + const char *tosec, const char *tosym) +{ + /* Check for pattern 1 */ + if (match(tosec, init_data_sections) && + match(fromsec, data_sections) && + strstarts(fromsym, "__param")) + return 0; + + /* Check for pattern 1a */ + if (strcmp(tosec, ".init.text") == 0 && + match(fromsec, data_sections) && + strstarts(fromsym, "__param_ops_")) + return 0; + + /* Check for pattern 2 */ + if (match(tosec, init_exit_sections) && + match(fromsec, data_sections) && + match(fromsym, mismatch->symbol_white_list)) + return 0; + + /* Check for pattern 3 */ + if (match(fromsec, head_sections) && + match(tosec, init_sections)) + return 0; + + /* Check for pattern 4 */ + if (match(tosym, linker_symbols)) + return 0; + + /* Check for pattern 5 */ + if (match(fromsec, text_sections) && + match(tosec, init_sections) && + match(fromsym, optim_symbols)) + return 0; + + /* Check for pattern 6 */ + if (strstarts(fromsym, ".L")) + return 0; + + return 1; +} + +static inline int is_arm_mapping_symbol(const char *str) +{ + return str[0] == '$' && + (str[1] == 'a' || str[1] == 'd' || str[1] == 't' || str[1] == 'x') + && (str[2] == '\0' || str[2] == '.'); +} + +/* + * If there's no name there, ignore it; likewise, ignore it if it's + * one of the magic symbols emitted used by current ARM tools. + * + * Otherwise if find_symbols_between() returns those symbols, they'll + * fail the whitelist tests and cause lots of false alarms ... fixable + * only by merging __exit and __init sections into __text, bloating + * the kernel (which is especially evil on embedded platforms). + */ +static inline int is_valid_name(struct elf_info *elf, Elf_Sym *sym) +{ + const char *name = elf->strtab + sym->st_name; + + if (!name || !strlen(name)) + return 0; + return !is_arm_mapping_symbol(name); +} + +/** + * Find symbol based on relocation record info. + * In some cases the symbol supplied is a valid symbol so + * return refsym. If st_name != 0 we assume this is a valid symbol. + * In other cases the symbol needs to be looked up in the symbol table + * based on section and address. + * **/ +static Elf_Sym *find_elf_symbol(struct elf_info *elf, Elf64_Sword addr, + Elf_Sym *relsym) +{ + Elf_Sym *sym; + Elf_Sym *near = NULL; + Elf64_Sword distance = 20; + Elf64_Sword d; + unsigned int relsym_secindex; + + if (relsym->st_name != 0) + return relsym; + + relsym_secindex = get_secindex(elf, relsym); + for (sym = elf->symtab_start; sym < elf->symtab_stop; sym++) { + if (get_secindex(elf, sym) != relsym_secindex) + continue; + if (ELF_ST_TYPE(sym->st_info) == STT_SECTION) + continue; + if (!is_valid_name(elf, sym)) + continue; + if (sym->st_value == addr) + return sym; + /* Find a symbol nearby - addr are maybe negative */ + d = sym->st_value - addr; + if (d < 0) + d = addr - sym->st_value; + if (d < distance) { + distance = d; + near = sym; + } + } + /* We need a close match */ + if (distance < 20) + return near; + else + return NULL; +} + +/* + * Find symbols before or equal addr and after addr - in the section sec. + * If we find two symbols with equal offset prefer one with a valid name. + * The ELF format may have a better way to detect what type of symbol + * it is, but this works for now. + **/ +static Elf_Sym *find_elf_symbol2(struct elf_info *elf, Elf_Addr addr, + const char *sec) +{ + Elf_Sym *sym; + Elf_Sym *near = NULL; + Elf_Addr distance = ~0; + + for (sym = elf->symtab_start; sym < elf->symtab_stop; sym++) { + const char *symsec; + + if (is_shndx_special(sym->st_shndx)) + continue; + symsec = sec_name(elf, get_secindex(elf, sym)); + if (strcmp(symsec, sec) != 0) + continue; + if (!is_valid_name(elf, sym)) + continue; + if (sym->st_value <= addr) { + if ((addr - sym->st_value) < distance) { + distance = addr - sym->st_value; + near = sym; + } else if ((addr - sym->st_value) == distance) { + near = sym; + } + } + } + return near; +} + +/* + * Convert a section name to the function/data attribute + * .init.text => __init + * .memexitconst => __memconst + * etc. + * + * The memory of returned value has been allocated on a heap. The user of this + * method should free it after usage. +*/ +static char *sec2annotation(const char *s) +{ + if (match(s, init_exit_sections)) { + char *p = NOFAIL(malloc(20)); + char *r = p; + + *p++ = '_'; + *p++ = '_'; + if (*s == '.') + s++; + while (*s && *s != '.') + *p++ = *s++; + *p = '\0'; + if (*s == '.') + s++; + if (strstr(s, "rodata") != NULL) + strcat(p, "const "); + else if (strstr(s, "data") != NULL) + strcat(p, "data "); + else + strcat(p, " "); + return r; + } else { + return NOFAIL(strdup("")); + } +} + +static int is_function(Elf_Sym *sym) +{ + if (sym) + return ELF_ST_TYPE(sym->st_info) == STT_FUNC; + else + return -1; +} + +static void print_section_list(const char * const list[20]) +{ + const char *const *s = list; + + while (*s) { + fprintf(stderr, "%s", *s); + s++; + if (*s) + fprintf(stderr, ", "); + } + fprintf(stderr, "\n"); +} + +static inline void get_pretty_name(int is_func, const char** name, const char** name_p) +{ + switch (is_func) { + case 0: *name = "variable"; *name_p = ""; break; + case 1: *name = "function"; *name_p = "()"; break; + default: *name = "(unknown reference)"; *name_p = ""; break; + } +} + +/* + * Print a warning about a section mismatch. + * Try to find symbols near it so user can find it. + * Check whitelist before warning - it may be a false positive. + */ +static void report_sec_mismatch(const char *modname, + const struct sectioncheck *mismatch, + const char *fromsec, + unsigned long long fromaddr, + const char *fromsym, + int from_is_func, + const char *tosec, const char *tosym, + int to_is_func) +{ + const char *from, *from_p; + const char *to, *to_p; + char *prl_from; + char *prl_to; + + sec_mismatch_count++; + + get_pretty_name(from_is_func, &from, &from_p); + get_pretty_name(to_is_func, &to, &to_p); + + warn("%s(%s+0x%llx): Section mismatch in reference from the %s %s%s " + "to the %s %s:%s%s\n", + modname, fromsec, fromaddr, from, fromsym, from_p, to, tosec, + tosym, to_p); + + switch (mismatch->mismatch) { + case TEXT_TO_ANY_INIT: + prl_from = sec2annotation(fromsec); + prl_to = sec2annotation(tosec); + fprintf(stderr, + "The function %s%s() references\n" + "the %s %s%s%s.\n" + "This is often because %s lacks a %s\n" + "annotation or the annotation of %s is wrong.\n", + prl_from, fromsym, + to, prl_to, tosym, to_p, + fromsym, prl_to, tosym); + free(prl_from); + free(prl_to); + break; + case DATA_TO_ANY_INIT: { + prl_to = sec2annotation(tosec); + fprintf(stderr, + "The variable %s references\n" + "the %s %s%s%s\n" + "If the reference is valid then annotate the\n" + "variable with __init* or __refdata (see linux/init.h) " + "or name the variable:\n", + fromsym, to, prl_to, tosym, to_p); + print_section_list(mismatch->symbol_white_list); + free(prl_to); + break; + } + case TEXT_TO_ANY_EXIT: + prl_to = sec2annotation(tosec); + fprintf(stderr, + "The function %s() references a %s in an exit section.\n" + "Often the %s %s%s has valid usage outside the exit section\n" + "and the fix is to remove the %sannotation of %s.\n", + fromsym, to, to, tosym, to_p, prl_to, tosym); + free(prl_to); + break; + case DATA_TO_ANY_EXIT: { + prl_to = sec2annotation(tosec); + fprintf(stderr, + "The variable %s references\n" + "the %s %s%s%s\n" + "If the reference is valid then annotate the\n" + "variable with __exit* (see linux/init.h) or " + "name the variable:\n", + fromsym, to, prl_to, tosym, to_p); + print_section_list(mismatch->symbol_white_list); + free(prl_to); + break; + } + case XXXINIT_TO_SOME_INIT: + case XXXEXIT_TO_SOME_EXIT: + prl_from = sec2annotation(fromsec); + prl_to = sec2annotation(tosec); + fprintf(stderr, + "The %s %s%s%s references\n" + "a %s %s%s%s.\n" + "If %s is only used by %s then\n" + "annotate %s with a matching annotation.\n", + from, prl_from, fromsym, from_p, + to, prl_to, tosym, to_p, + tosym, fromsym, tosym); + free(prl_from); + free(prl_to); + break; + case ANY_INIT_TO_ANY_EXIT: + prl_from = sec2annotation(fromsec); + prl_to = sec2annotation(tosec); + fprintf(stderr, + "The %s %s%s%s references\n" + "a %s %s%s%s.\n" + "This is often seen when error handling " + "in the init function\n" + "uses functionality in the exit path.\n" + "The fix is often to remove the %sannotation of\n" + "%s%s so it may be used outside an exit section.\n", + from, prl_from, fromsym, from_p, + to, prl_to, tosym, to_p, + prl_to, tosym, to_p); + free(prl_from); + free(prl_to); + break; + case ANY_EXIT_TO_ANY_INIT: + prl_from = sec2annotation(fromsec); + prl_to = sec2annotation(tosec); + fprintf(stderr, + "The %s %s%s%s references\n" + "a %s %s%s%s.\n" + "This is often seen when error handling " + "in the exit function\n" + "uses functionality in the init path.\n" + "The fix is often to remove the %sannotation of\n" + "%s%s so it may be used outside an init section.\n", + from, prl_from, fromsym, from_p, + to, prl_to, tosym, to_p, + prl_to, tosym, to_p); + free(prl_from); + free(prl_to); + break; + case EXPORT_TO_INIT_EXIT: + prl_to = sec2annotation(tosec); + fprintf(stderr, + "The symbol %s is exported and annotated %s\n" + "Fix this by removing the %sannotation of %s " + "or drop the export.\n", + tosym, prl_to, prl_to, tosym); + free(prl_to); + break; + case EXTABLE_TO_NON_TEXT: + fatal("There's a special handler for this mismatch type, " + "we should never get here."); + break; + } + fprintf(stderr, "\n"); +} + +static void default_mismatch_handler(const char *modname, struct elf_info *elf, + const struct sectioncheck* const mismatch, + Elf_Rela *r, Elf_Sym *sym, const char *fromsec) +{ + const char *tosec; + Elf_Sym *to; + Elf_Sym *from; + const char *tosym; + const char *fromsym; + + from = find_elf_symbol2(elf, r->r_offset, fromsec); + fromsym = sym_name(elf, from); + + if (strstarts(fromsym, "reference___initcall")) + return; + + tosec = sec_name(elf, get_secindex(elf, sym)); + to = find_elf_symbol(elf, r->r_addend, sym); + tosym = sym_name(elf, to); + + /* check whitelist - we may ignore it */ + if (secref_whitelist(mismatch, + fromsec, fromsym, tosec, tosym)) { + report_sec_mismatch(modname, mismatch, + fromsec, r->r_offset, fromsym, + is_function(from), tosec, tosym, + is_function(to)); + } +} + +static int is_executable_section(struct elf_info* elf, unsigned int section_index) +{ + if (section_index > elf->num_sections) + fatal("section_index is outside elf->num_sections!\n"); + + return ((elf->sechdrs[section_index].sh_flags & SHF_EXECINSTR) == SHF_EXECINSTR); +} + +/* + * We rely on a gross hack in section_rel[a]() calling find_extable_entry_size() + * to know the sizeof(struct exception_table_entry) for the target architecture. + */ +static unsigned int extable_entry_size = 0; +static void find_extable_entry_size(const char* const sec, const Elf_Rela* r) +{ + /* + * If we're currently checking the second relocation within __ex_table, + * that relocation offset tells us the offsetof(struct + * exception_table_entry, fixup) which is equal to sizeof(struct + * exception_table_entry) divided by two. We use that to our advantage + * since there's no portable way to get that size as every architecture + * seems to go with different sized types. Not pretty but better than + * hard-coding the size for every architecture.. + */ + if (!extable_entry_size) + extable_entry_size = r->r_offset * 2; +} + +static inline bool is_extable_fault_address(Elf_Rela *r) +{ + /* + * extable_entry_size is only discovered after we've handled the + * _second_ relocation in __ex_table, so only abort when we're not + * handling the first reloc and extable_entry_size is zero. + */ + if (r->r_offset && extable_entry_size == 0) + fatal("extable_entry size hasn't been discovered!\n"); + + return ((r->r_offset == 0) || + (r->r_offset % extable_entry_size == 0)); +} + +#define is_second_extable_reloc(Start, Cur, Sec) \ + (((Cur) == (Start) + 1) && (strcmp("__ex_table", (Sec)) == 0)) + +static void report_extable_warnings(const char* modname, struct elf_info* elf, + const struct sectioncheck* const mismatch, + Elf_Rela* r, Elf_Sym* sym, + const char* fromsec, const char* tosec) +{ + Elf_Sym* fromsym = find_elf_symbol2(elf, r->r_offset, fromsec); + const char* fromsym_name = sym_name(elf, fromsym); + Elf_Sym* tosym = find_elf_symbol(elf, r->r_addend, sym); + const char* tosym_name = sym_name(elf, tosym); + const char* from_pretty_name; + const char* from_pretty_name_p; + const char* to_pretty_name; + const char* to_pretty_name_p; + + get_pretty_name(is_function(fromsym), + &from_pretty_name, &from_pretty_name_p); + get_pretty_name(is_function(tosym), + &to_pretty_name, &to_pretty_name_p); + + warn("%s(%s+0x%lx): Section mismatch in reference" + " from the %s %s%s to the %s %s:%s%s\n", + modname, fromsec, (long)r->r_offset, from_pretty_name, + fromsym_name, from_pretty_name_p, + to_pretty_name, tosec, tosym_name, to_pretty_name_p); + + if (!match(tosec, mismatch->bad_tosec) && + is_executable_section(elf, get_secindex(elf, sym))) + fprintf(stderr, + "The relocation at %s+0x%lx references\n" + "section \"%s\" which is not in the list of\n" + "authorized sections. If you're adding a new section\n" + "and/or if this reference is valid, add \"%s\" to the\n" + "list of authorized sections to jump to on fault.\n" + "This can be achieved by adding \"%s\" to \n" + "OTHER_TEXT_SECTIONS in scripts/mod/modpost.c.\n", + fromsec, (long)r->r_offset, tosec, tosec, tosec); +} + +static void extable_mismatch_handler(const char* modname, struct elf_info *elf, + const struct sectioncheck* const mismatch, + Elf_Rela* r, Elf_Sym* sym, + const char *fromsec) +{ + const char* tosec = sec_name(elf, get_secindex(elf, sym)); + + sec_mismatch_count++; + + report_extable_warnings(modname, elf, mismatch, r, sym, fromsec, tosec); + + if (match(tosec, mismatch->bad_tosec)) + fatal("The relocation at %s+0x%lx references\n" + "section \"%s\" which is black-listed.\n" + "Something is seriously wrong and should be fixed.\n" + "You might get more information about where this is\n" + "coming from by using scripts/check_extable.sh %s\n", + fromsec, (long)r->r_offset, tosec, modname); + else if (!is_executable_section(elf, get_secindex(elf, sym))) { + if (is_extable_fault_address(r)) + fatal("The relocation at %s+0x%lx references\n" + "section \"%s\" which is not executable, IOW\n" + "it is not possible for the kernel to fault\n" + "at that address. Something is seriously wrong\n" + "and should be fixed.\n", + fromsec, (long)r->r_offset, tosec); + else + fatal("The relocation at %s+0x%lx references\n" + "section \"%s\" which is not executable, IOW\n" + "the kernel will fault if it ever tries to\n" + "jump to it. Something is seriously wrong\n" + "and should be fixed.\n", + fromsec, (long)r->r_offset, tosec); + } +} + +static void check_section_mismatch(const char *modname, struct elf_info *elf, + Elf_Rela *r, Elf_Sym *sym, const char *fromsec) +{ + const char *tosec = sec_name(elf, get_secindex(elf, sym)); + const struct sectioncheck *mismatch = section_mismatch(fromsec, tosec); + + if (mismatch) { + if (mismatch->handler) + mismatch->handler(modname, elf, mismatch, + r, sym, fromsec); + else + default_mismatch_handler(modname, elf, mismatch, + r, sym, fromsec); + } +} + +static unsigned int *reloc_location(struct elf_info *elf, + Elf_Shdr *sechdr, Elf_Rela *r) +{ + return sym_get_data_by_offset(elf, sechdr->sh_info, r->r_offset); +} + +static int addend_386_rel(struct elf_info *elf, Elf_Shdr *sechdr, Elf_Rela *r) +{ + unsigned int r_typ = ELF_R_TYPE(r->r_info); + unsigned int *location = reloc_location(elf, sechdr, r); + + switch (r_typ) { + case R_386_32: + r->r_addend = TO_NATIVE(*location); + break; + case R_386_PC32: + r->r_addend = TO_NATIVE(*location) + 4; + /* For CONFIG_RELOCATABLE=y */ + if (elf->hdr->e_type == ET_EXEC) + r->r_addend += r->r_offset; + break; + } + return 0; +} + +#ifndef R_ARM_CALL +#define R_ARM_CALL 28 +#endif +#ifndef R_ARM_JUMP24 +#define R_ARM_JUMP24 29 +#endif + +#ifndef R_ARM_THM_CALL +#define R_ARM_THM_CALL 10 +#endif +#ifndef R_ARM_THM_JUMP24 +#define R_ARM_THM_JUMP24 30 +#endif +#ifndef R_ARM_THM_JUMP19 +#define R_ARM_THM_JUMP19 51 +#endif + +static int addend_arm_rel(struct elf_info *elf, Elf_Shdr *sechdr, Elf_Rela *r) +{ + unsigned int r_typ = ELF_R_TYPE(r->r_info); + + switch (r_typ) { + case R_ARM_ABS32: + /* From ARM ABI: (S + A) | T */ + r->r_addend = (int)(long) + (elf->symtab_start + ELF_R_SYM(r->r_info)); + break; + case R_ARM_PC24: + case R_ARM_CALL: + case R_ARM_JUMP24: + case R_ARM_THM_CALL: + case R_ARM_THM_JUMP24: + case R_ARM_THM_JUMP19: + /* From ARM ABI: ((S + A) | T) - P */ + r->r_addend = (int)(long)(elf->hdr + + sechdr->sh_offset + + (r->r_offset - sechdr->sh_addr)); + break; + default: + return 1; + } + return 0; +} + +static int addend_mips_rel(struct elf_info *elf, Elf_Shdr *sechdr, Elf_Rela *r) +{ + unsigned int r_typ = ELF_R_TYPE(r->r_info); + unsigned int *location = reloc_location(elf, sechdr, r); + unsigned int inst; + + if (r_typ == R_MIPS_HI16) + return 1; /* skip this */ + inst = TO_NATIVE(*location); + switch (r_typ) { + case R_MIPS_LO16: + r->r_addend = inst & 0xffff; + break; + case R_MIPS_26: + r->r_addend = (inst & 0x03ffffff) << 2; + break; + case R_MIPS_32: + r->r_addend = inst; + break; + } + return 0; +} + +#ifndef EM_LOONGARCH +#define EM_LOONGARCH 258 +#endif + +#ifndef R_LARCH_SUB32 +#define R_LARCH_SUB32 55 +#endif + +static void section_rela(const char *modname, struct elf_info *elf, + Elf_Shdr *sechdr) +{ + Elf_Sym *sym; + Elf_Rela *rela; + Elf_Rela r; + unsigned int r_sym; + const char *fromsec; + + Elf_Rela *start = (void *)elf->hdr + sechdr->sh_offset; + Elf_Rela *stop = (void *)start + sechdr->sh_size; + + fromsec = sech_name(elf, sechdr); + fromsec += strlen(".rela"); + /* if from section (name) is know good then skip it */ + if (match(fromsec, section_white_list)) + return; + + for (rela = start; rela < stop; rela++) { + r.r_offset = TO_NATIVE(rela->r_offset); +#if KERNEL_ELFCLASS == ELFCLASS64 + if (elf->hdr->e_machine == EM_MIPS) { + unsigned int r_typ; + r_sym = ELF64_MIPS_R_SYM(rela->r_info); + r_sym = TO_NATIVE(r_sym); + r_typ = ELF64_MIPS_R_TYPE(rela->r_info); + r.r_info = ELF64_R_INFO(r_sym, r_typ); + } else { + r.r_info = TO_NATIVE(rela->r_info); + r_sym = ELF_R_SYM(r.r_info); + } +#else + r.r_info = TO_NATIVE(rela->r_info); + r_sym = ELF_R_SYM(r.r_info); +#endif + r.r_addend = TO_NATIVE(rela->r_addend); + switch (elf->hdr->e_machine) { + case EM_LOONGARCH: + if (!strcmp("__ex_table", fromsec) && + ELF_R_TYPE(r.r_info) == R_LARCH_SUB32) + continue; + break; + } + sym = elf->symtab_start + r_sym; + /* Skip special sections */ + if (is_shndx_special(sym->st_shndx)) + continue; + if (is_second_extable_reloc(start, rela, fromsec)) + find_extable_entry_size(fromsec, &r); + check_section_mismatch(modname, elf, &r, sym, fromsec); + } +} + +static void section_rel(const char *modname, struct elf_info *elf, + Elf_Shdr *sechdr) +{ + Elf_Sym *sym; + Elf_Rel *rel; + Elf_Rela r; + unsigned int r_sym; + const char *fromsec; + + Elf_Rel *start = (void *)elf->hdr + sechdr->sh_offset; + Elf_Rel *stop = (void *)start + sechdr->sh_size; + + fromsec = sech_name(elf, sechdr); + fromsec += strlen(".rel"); + /* if from section (name) is know good then skip it */ + if (match(fromsec, section_white_list)) + return; + + for (rel = start; rel < stop; rel++) { + r.r_offset = TO_NATIVE(rel->r_offset); +#if KERNEL_ELFCLASS == ELFCLASS64 + if (elf->hdr->e_machine == EM_MIPS) { + unsigned int r_typ; + r_sym = ELF64_MIPS_R_SYM(rel->r_info); + r_sym = TO_NATIVE(r_sym); + r_typ = ELF64_MIPS_R_TYPE(rel->r_info); + r.r_info = ELF64_R_INFO(r_sym, r_typ); + } else { + r.r_info = TO_NATIVE(rel->r_info); + r_sym = ELF_R_SYM(r.r_info); + } +#else + r.r_info = TO_NATIVE(rel->r_info); + r_sym = ELF_R_SYM(r.r_info); +#endif + r.r_addend = 0; + switch (elf->hdr->e_machine) { + case EM_386: + if (addend_386_rel(elf, sechdr, &r)) + continue; + break; + case EM_ARM: + if (addend_arm_rel(elf, sechdr, &r)) + continue; + break; + case EM_MIPS: + if (addend_mips_rel(elf, sechdr, &r)) + continue; + break; + } + sym = elf->symtab_start + r_sym; + /* Skip special sections */ + if (is_shndx_special(sym->st_shndx)) + continue; + if (is_second_extable_reloc(start, rel, fromsec)) + find_extable_entry_size(fromsec, &r); + check_section_mismatch(modname, elf, &r, sym, fromsec); + } +} + +/** + * A module includes a number of sections that are discarded + * either when loaded or when used as built-in. + * For loaded modules all functions marked __init and all data + * marked __initdata will be discarded when the module has been initialized. + * Likewise for modules used built-in the sections marked __exit + * are discarded because __exit marked function are supposed to be called + * only when a module is unloaded which never happens for built-in modules. + * The check_sec_ref() function traverses all relocation records + * to find all references to a section that reference a section that will + * be discarded and warns about it. + **/ +static void check_sec_ref(struct module *mod, const char *modname, + struct elf_info *elf) +{ + int i; + Elf_Shdr *sechdrs = elf->sechdrs; + + /* Walk through all sections */ + for (i = 0; i < elf->num_sections; i++) { + check_section(modname, elf, &elf->sechdrs[i]); + /* We want to process only relocation sections and not .init */ + if (sechdrs[i].sh_type == SHT_RELA) + section_rela(modname, elf, &elf->sechdrs[i]); + else if (sechdrs[i].sh_type == SHT_REL) + section_rel(modname, elf, &elf->sechdrs[i]); + } +} + +static char *remove_dot(char *s) +{ + size_t n = strcspn(s, "."); + + if (n && s[n]) { + size_t m = strspn(s + n + 1, "0123456789"); + if (m && (s[n + m + 1] == '.' || s[n + m + 1] == 0)) + s[n] = 0; + } + return s; +} + +static void read_symbols(const char *modname) +{ + const char *symname; + char *version; + char *license; + char *namespace; + struct module *mod; + struct elf_info info = { }; + Elf_Sym *sym; + + if (!parse_elf(&info, modname)) + return; + + { + char *tmp; + + /* strip trailing .o */ + tmp = NOFAIL(strdup(modname)); + tmp[strlen(tmp) - 2] = '\0'; + mod = new_module(tmp); + free(tmp); + } + + if (!mod->is_vmlinux) { + license = get_modinfo(&info, "license"); + if (!license) + warn("missing MODULE_LICENSE() in %s\n", modname); + while (license) { + if (license_is_gpl_compatible(license)) + mod->gpl_compatible = 1; + else { + mod->gpl_compatible = 0; + break; + } + license = get_next_modinfo(&info, "license", license); + } + + namespace = get_modinfo(&info, "import_ns"); + while (namespace) { + add_namespace(&mod->imported_namespaces, namespace); + namespace = get_next_modinfo(&info, "import_ns", + namespace); + } + } + + for (sym = info.symtab_start; sym < info.symtab_stop; sym++) { + symname = remove_dot(info.strtab + sym->st_name); + + handle_symbol(mod, &info, sym, symname); + handle_moddevtable(mod, &info, sym, symname); + } + + for (sym = info.symtab_start; sym < info.symtab_stop; sym++) { + symname = remove_dot(info.strtab + sym->st_name); + + /* Apply symbol namespaces from __kstrtabns_<symbol> entries. */ + if (strstarts(symname, "__kstrtabns_")) + sym_update_namespace(symname + strlen("__kstrtabns_"), + namespace_from_kstrtabns(&info, + sym)); + + if (strstarts(symname, "__crc_")) + handle_modversion(mod, &info, sym, + symname + strlen("__crc_")); + } + + // check for static EXPORT_SYMBOL_* functions && global vars + for (sym = info.symtab_start; sym < info.symtab_stop; sym++) { + unsigned char bind = ELF_ST_BIND(sym->st_info); + + if (bind == STB_GLOBAL || bind == STB_WEAK) { + struct symbol *s = + find_symbol(remove_dot(info.strtab + + sym->st_name)); + + if (s) + s->is_static = 0; + } + } + + check_sec_ref(mod, modname, &info); + + if (!mod->is_vmlinux) { + version = get_modinfo(&info, "version"); + if (version || all_versions) + get_src_version(modname, mod->srcversion, + sizeof(mod->srcversion) - 1); + } + + parse_elf_finish(&info); + + /* Our trick to get versioning for module struct etc. - it's + * never passed as an argument to an exported function, so + * the automatic versioning doesn't pick it up, but it's really + * important anyhow */ + if (modversions) + mod->unres = alloc_symbol("module_layout", 0, mod->unres); +} + +static void read_symbols_from_files(const char *filename) +{ + FILE *in = stdin; + char fname[PATH_MAX]; + + if (strcmp(filename, "-") != 0) { + in = fopen(filename, "r"); + if (!in) + fatal("Can't open filenames file %s: %m", filename); + } + + while (fgets(fname, PATH_MAX, in) != NULL) { + if (strends(fname, "\n")) + fname[strlen(fname)-1] = '\0'; + read_symbols(fname); + } + + if (in != stdin) + fclose(in); +} + +#define SZ 500 + +/* We first write the generated file into memory using the + * following helper, then compare to the file on disk and + * only update the later if anything changed */ + +void __attribute__((format(printf, 2, 3))) buf_printf(struct buffer *buf, + const char *fmt, ...) +{ + char tmp[SZ]; + int len; + va_list ap; + + va_start(ap, fmt); + len = vsnprintf(tmp, SZ, fmt, ap); + buf_write(buf, tmp, len); + va_end(ap); +} + +void buf_write(struct buffer *buf, const char *s, int len) +{ + if (buf->size - buf->pos < len) { + buf->size += len + SZ; + buf->p = NOFAIL(realloc(buf->p, buf->size)); + } + strncpy(buf->p + buf->pos, s, len); + buf->pos += len; +} + +static void check_for_gpl_usage(enum export exp, const char *m, const char *s) +{ + switch (exp) { + case export_gpl: + fatal("GPL-incompatible module %s.ko uses GPL-only symbol '%s'\n", + m, s); + break; + case export_unused_gpl: + fatal("GPL-incompatible module %s.ko uses GPL-only symbol marked UNUSED '%s'\n", + m, s); + break; + case export_gpl_future: + warn("GPL-incompatible module %s.ko uses future GPL-only symbol '%s'\n", + m, s); + break; + case export_plain: + case export_unused: + case export_unknown: + /* ignore */ + break; + } +} + +static void check_for_unused(enum export exp, const char *m, const char *s) +{ + switch (exp) { + case export_unused: + case export_unused_gpl: + warn("module %s.ko uses symbol '%s' marked UNUSED\n", + m, s); + break; + default: + /* ignore */ + break; + } +} + +static int check_exports(struct module *mod) +{ + struct symbol *s, *exp; + int err = 0; + + for (s = mod->unres; s; s = s->next) { + const char *basename; + exp = find_symbol(s->name); + if (!exp || exp->module == mod) { + if (have_vmlinux && !s->weak) { + modpost_log(warn_unresolved ? LOG_WARN : LOG_ERROR, + "\"%s\" [%s.ko] undefined!\n", + s->name, mod->name); + if (!warn_unresolved) + err = 1; + } + continue; + } + basename = strrchr(mod->name, '/'); + if (basename) + basename++; + else + basename = mod->name; + + if (exp->namespace && + !module_imports_namespace(mod, exp->namespace)) { + modpost_log(allow_missing_ns_imports ? LOG_WARN : LOG_ERROR, + "module %s uses symbol %s from namespace %s, but does not import it.\n", + basename, exp->name, exp->namespace); + if (!allow_missing_ns_imports) + err = 1; + add_namespace(&mod->missing_namespaces, exp->namespace); + } + + if (!mod->gpl_compatible) + check_for_gpl_usage(exp->export, basename, exp->name); + check_for_unused(exp->export, basename, exp->name); + } + + return err; +} + +static int check_modname_len(struct module *mod) +{ + const char *mod_name; + + mod_name = strrchr(mod->name, '/'); + if (mod_name == NULL) + mod_name = mod->name; + else + mod_name++; + if (strlen(mod_name) >= MODULE_NAME_LEN) { + merror("module name is too long [%s.ko]\n", mod->name); + return 1; + } + + return 0; +} + +/** + * Header for the generated file + **/ +static void add_header(struct buffer *b, struct module *mod) +{ + buf_printf(b, "#include <linux/module.h>\n"); + /* + * Include build-salt.h after module.h in order to + * inherit the definitions. + */ + buf_printf(b, "#define INCLUDE_VERMAGIC\n"); + buf_printf(b, "#include <linux/build-salt.h>\n"); + buf_printf(b, "#include <linux/vermagic.h>\n"); + buf_printf(b, "#include <linux/compiler.h>\n"); + buf_printf(b, "\n"); + buf_printf(b, "BUILD_SALT;\n"); + buf_printf(b, "\n"); + buf_printf(b, "MODULE_INFO(vermagic, VERMAGIC_STRING);\n"); + buf_printf(b, "MODULE_INFO(name, KBUILD_MODNAME);\n"); + buf_printf(b, "\n"); + buf_printf(b, "__visible struct module __this_module\n"); + buf_printf(b, "__section(\".gnu.linkonce.this_module\") = {\n"); + buf_printf(b, "\t.name = KBUILD_MODNAME,\n"); + if (mod->has_init) + buf_printf(b, "\t.init = init_module,\n"); + if (mod->has_cleanup) + buf_printf(b, "#ifdef CONFIG_MODULE_UNLOAD\n" + "\t.exit = cleanup_module,\n" + "#endif\n"); + buf_printf(b, "\t.arch = MODULE_ARCH_INIT,\n"); + buf_printf(b, "};\n"); +} + +static void add_intree_flag(struct buffer *b, int is_intree) +{ + if (is_intree) + buf_printf(b, "\nMODULE_INFO(intree, \"Y\");\n"); +} + +/* Cannot check for assembler */ +static void add_retpoline(struct buffer *b) +{ + buf_printf(b, "\n#ifdef CONFIG_RETPOLINE\n"); + buf_printf(b, "MODULE_INFO(retpoline, \"Y\");\n"); + buf_printf(b, "#endif\n"); +} + +static void add_staging_flag(struct buffer *b, const char *name) +{ + if (strstarts(name, "drivers/staging")) + buf_printf(b, "\nMODULE_INFO(staging, \"Y\");\n"); +} + +/** + * Record CRCs for unresolved symbols + **/ +static int add_versions(struct buffer *b, struct module *mod) +{ + struct symbol *s, *exp; + int err = 0; + + for (s = mod->unres; s; s = s->next) { + exp = find_symbol(s->name); + if (!exp || exp->module == mod) + continue; + s->module = exp->module; + s->crc_valid = exp->crc_valid; + s->crc = exp->crc; + } + + if (!modversions) + return err; + + buf_printf(b, "\n"); + buf_printf(b, "static const struct modversion_info ____versions[]\n"); + buf_printf(b, "__used __section(\"__versions\") = {\n"); + + for (s = mod->unres; s; s = s->next) { + if (!s->module) + continue; + if (!s->crc_valid) { + warn("\"%s\" [%s.ko] has no CRC!\n", + s->name, mod->name); + continue; + } + if (strlen(s->name) >= MODULE_NAME_LEN) { + merror("too long symbol \"%s\" [%s.ko]\n", + s->name, mod->name); + err = 1; + break; + } + buf_printf(b, "\t{ %#8x, \"%s\" },\n", + s->crc, s->name); + } + + buf_printf(b, "};\n"); + + return err; +} + +static void add_depends(struct buffer *b, struct module *mod) +{ + struct symbol *s; + int first = 1; + + /* Clear ->seen flag of modules that own symbols needed by this. */ + for (s = mod->unres; s; s = s->next) + if (s->module) + s->module->seen = s->module->is_vmlinux; + + buf_printf(b, "\n"); + buf_printf(b, "MODULE_INFO(depends, \""); + for (s = mod->unres; s; s = s->next) { + const char *p; + if (!s->module) + continue; + + if (s->module->seen) + continue; + + s->module->seen = 1; + p = strrchr(s->module->name, '/'); + if (p) + p++; + else + p = s->module->name; + buf_printf(b, "%s%s", first ? "" : ",", p); + first = 0; + } + buf_printf(b, "\");\n"); +} + +static void add_srcversion(struct buffer *b, struct module *mod) +{ + if (mod->srcversion[0]) { + buf_printf(b, "\n"); + buf_printf(b, "MODULE_INFO(srcversion, \"%s\");\n", + mod->srcversion); + } +} + +static void write_buf(struct buffer *b, const char *fname) +{ + FILE *file; + + file = fopen(fname, "w"); + if (!file) { + perror(fname); + exit(1); + } + if (fwrite(b->p, 1, b->pos, file) != b->pos) { + perror(fname); + exit(1); + } + if (fclose(file) != 0) { + perror(fname); + exit(1); + } +} + +static void write_if_changed(struct buffer *b, const char *fname) +{ + char *tmp; + FILE *file; + struct stat st; + + file = fopen(fname, "r"); + if (!file) + goto write; + + if (fstat(fileno(file), &st) < 0) + goto close_write; + + if (st.st_size != b->pos) + goto close_write; + + tmp = NOFAIL(malloc(b->pos)); + if (fread(tmp, 1, b->pos, file) != b->pos) + goto free_write; + + if (memcmp(tmp, b->p, b->pos) != 0) + goto free_write; + + free(tmp); + fclose(file); + return; + + free_write: + free(tmp); + close_write: + fclose(file); + write: + write_buf(b, fname); +} + +/* parse Module.symvers file. line format: + * 0x12345678<tab>symbol<tab>module<tab>export<tab>namespace + **/ +static void read_dump(const char *fname) +{ + char *buf, *pos, *line; + + buf = read_text_file(fname); + if (!buf) + /* No symbol versions, silently ignore */ + return; + + pos = buf; + + while ((line = get_line(&pos))) { + char *symname, *namespace, *modname, *d, *export; + unsigned int crc; + struct module *mod; + struct symbol *s; + + if (!(symname = strchr(line, '\t'))) + goto fail; + *symname++ = '\0'; + if (!(modname = strchr(symname, '\t'))) + goto fail; + *modname++ = '\0'; + if (!(export = strchr(modname, '\t'))) + goto fail; + *export++ = '\0'; + if (!(namespace = strchr(export, '\t'))) + goto fail; + *namespace++ = '\0'; + + crc = strtoul(line, &d, 16); + if (*symname == '\0' || *modname == '\0' || *d != '\0') + goto fail; + mod = find_module(modname); + if (!mod) { + mod = new_module(modname); + mod->from_dump = 1; + } + s = sym_add_exported(symname, mod, export_no(export)); + s->is_static = 0; + sym_set_crc(symname, crc); + sym_update_namespace(symname, namespace); + } + free(buf); + return; +fail: + free(buf); + fatal("parse error in symbol dump file\n"); +} + +static void write_dump(const char *fname) +{ + struct buffer buf = { }; + struct symbol *symbol; + const char *namespace; + int n; + + for (n = 0; n < SYMBOL_HASH_SIZE ; n++) { + symbol = symbolhash[n]; + while (symbol) { + if (!symbol->module->from_dump) { + namespace = symbol->namespace; + buf_printf(&buf, "0x%08x\t%s\t%s\t%s\t%s\n", + symbol->crc, symbol->name, + symbol->module->name, + export_str(symbol->export), + namespace ? namespace : ""); + } + symbol = symbol->next; + } + } + write_buf(&buf, fname); + free(buf.p); +} + +static void write_namespace_deps_files(const char *fname) +{ + struct module *mod; + struct namespace_list *ns; + struct buffer ns_deps_buf = {}; + + for (mod = modules; mod; mod = mod->next) { + + if (mod->from_dump || !mod->missing_namespaces) + continue; + + buf_printf(&ns_deps_buf, "%s.ko:", mod->name); + + for (ns = mod->missing_namespaces; ns; ns = ns->next) + buf_printf(&ns_deps_buf, " %s", ns->namespace); + + buf_printf(&ns_deps_buf, "\n"); + } + + write_if_changed(&ns_deps_buf, fname); + free(ns_deps_buf.p); +} + +struct dump_list { + struct dump_list *next; + const char *file; +}; + +int main(int argc, char **argv) +{ + struct module *mod; + struct buffer buf = { }; + char *missing_namespace_deps = NULL; + char *dump_write = NULL, *files_source = NULL; + int opt; + int err; + int n; + struct dump_list *dump_read_start = NULL; + struct dump_list **dump_read_iter = &dump_read_start; + + while ((opt = getopt(argc, argv, "ei:mnT:o:awENd:")) != -1) { + switch (opt) { + case 'e': + external_module = 1; + break; + case 'i': + *dump_read_iter = + NOFAIL(calloc(1, sizeof(**dump_read_iter))); + (*dump_read_iter)->file = optarg; + dump_read_iter = &(*dump_read_iter)->next; + break; + case 'm': + modversions = 1; + break; + case 'n': + ignore_missing_files = 1; + break; + case 'o': + dump_write = optarg; + break; + case 'a': + all_versions = 1; + break; + case 'T': + files_source = optarg; + break; + case 'w': + warn_unresolved = 1; + break; + case 'E': + sec_mismatch_fatal = 1; + break; + case 'N': + allow_missing_ns_imports = 1; + break; + case 'd': + missing_namespace_deps = optarg; + break; + default: + exit(1); + } + } + + while (dump_read_start) { + struct dump_list *tmp; + + read_dump(dump_read_start->file); + tmp = dump_read_start->next; + free(dump_read_start); + dump_read_start = tmp; + } + + while (optind < argc) + read_symbols(argv[optind++]); + + if (files_source) + read_symbols_from_files(files_source); + + /* + * When there's no vmlinux, don't print warnings about + * unresolved symbols (since there'll be too many ;) + */ + if (!have_vmlinux) + warn("Symbol info of vmlinux is missing. Unresolved symbol check will be entirely skipped.\n"); + + err = 0; + + for (mod = modules; mod; mod = mod->next) { + char fname[PATH_MAX]; + + if (mod->is_vmlinux || mod->from_dump) + continue; + + buf.pos = 0; + + err |= check_modname_len(mod); + err |= check_exports(mod); + + add_header(&buf, mod); + add_intree_flag(&buf, !external_module); + add_retpoline(&buf); + add_staging_flag(&buf, mod->name); + err |= add_versions(&buf, mod); + add_depends(&buf, mod); + add_moddevtable(&buf, mod); + add_srcversion(&buf, mod); + + sprintf(fname, "%s.mod.c", mod->name); + write_if_changed(&buf, fname); + } + + if (missing_namespace_deps) + write_namespace_deps_files(missing_namespace_deps); + + if (dump_write) + write_dump(dump_write); + if (sec_mismatch_count && sec_mismatch_fatal) + fatal("Section mismatches detected.\n" + "Set CONFIG_SECTION_MISMATCH_WARN_ONLY=y to allow them.\n"); + for (n = 0; n < SYMBOL_HASH_SIZE; n++) { + struct symbol *s; + + for (s = symbolhash[n]; s; s = s->next) { + if (s->is_static) + warn("\"%s\" [%s] is a static %s\n", + s->name, s->module->name, + export_str(s->export)); + } + } + + free(buf.p); + + return err; +} diff --git a/src/net/scripts/mod/modpost.h b/src/net/scripts/mod/modpost.h new file mode 100644 index 0000000..3aa0527 --- /dev/null +++ b/src/net/scripts/mod/modpost.h @@ -0,0 +1,206 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#include <stdio.h> +#include <stdlib.h> +#include <stdarg.h> +#include <string.h> +#include <sys/types.h> +#include <sys/stat.h> +#include <sys/mman.h> +#include <fcntl.h> +#include <unistd.h> +#include <elf.h> + +#include "elfconfig.h" + +/* On BSD-alike OSes elf.h defines these according to host's word size */ +#undef ELF_ST_BIND +#undef ELF_ST_TYPE +#undef ELF_R_SYM +#undef ELF_R_TYPE + +#if KERNEL_ELFCLASS == ELFCLASS32 + +#define Elf_Ehdr Elf32_Ehdr +#define Elf_Shdr Elf32_Shdr +#define Elf_Sym Elf32_Sym +#define Elf_Addr Elf32_Addr +#define Elf_Sword Elf64_Sword +#define Elf_Section Elf32_Half +#define ELF_ST_BIND ELF32_ST_BIND +#define ELF_ST_TYPE ELF32_ST_TYPE + +#define Elf_Rel Elf32_Rel +#define Elf_Rela Elf32_Rela +#define ELF_R_SYM ELF32_R_SYM +#define ELF_R_TYPE ELF32_R_TYPE +#else + +#define Elf_Ehdr Elf64_Ehdr +#define Elf_Shdr Elf64_Shdr +#define Elf_Sym Elf64_Sym +#define Elf_Addr Elf64_Addr +#define Elf_Sword Elf64_Sxword +#define Elf_Section Elf64_Half +#define ELF_ST_BIND ELF64_ST_BIND +#define ELF_ST_TYPE ELF64_ST_TYPE + +#define Elf_Rel Elf64_Rel +#define Elf_Rela Elf64_Rela +#define ELF_R_SYM ELF64_R_SYM +#define ELF_R_TYPE ELF64_R_TYPE +#endif + +/* The 64-bit MIPS ELF ABI uses an unusual reloc format. */ +typedef struct +{ + Elf32_Word r_sym; /* Symbol index */ + unsigned char r_ssym; /* Special symbol for 2nd relocation */ + unsigned char r_type3; /* 3rd relocation type */ + unsigned char r_type2; /* 2nd relocation type */ + unsigned char r_type1; /* 1st relocation type */ +} _Elf64_Mips_R_Info; + +typedef union +{ + Elf64_Xword r_info_number; + _Elf64_Mips_R_Info r_info_fields; +} _Elf64_Mips_R_Info_union; + +#define ELF64_MIPS_R_SYM(i) \ + ((__extension__ (_Elf64_Mips_R_Info_union)(i)).r_info_fields.r_sym) + +#define ELF64_MIPS_R_TYPE(i) \ + ((__extension__ (_Elf64_Mips_R_Info_union)(i)).r_info_fields.r_type1) + +#if KERNEL_ELFDATA != HOST_ELFDATA + +static inline void __endian(const void *src, void *dest, unsigned int size) +{ + unsigned int i; + for (i = 0; i < size; i++) + ((unsigned char*)dest)[i] = ((unsigned char*)src)[size - i-1]; +} + +#define TO_NATIVE(x) \ +({ \ + typeof(x) __x; \ + __endian(&(x), &(__x), sizeof(__x)); \ + __x; \ +}) + +#else /* endianness matches */ + +#define TO_NATIVE(x) (x) + +#endif + +#define NOFAIL(ptr) do_nofail((ptr), #ptr) +void *do_nofail(void *ptr, const char *expr); + +struct buffer { + char *p; + int pos; + int size; +}; + +void __attribute__((format(printf, 2, 3))) +buf_printf(struct buffer *buf, const char *fmt, ...); + +void +buf_write(struct buffer *buf, const char *s, int len); + +struct namespace_list { + struct namespace_list *next; + char namespace[]; +}; + +struct module { + struct module *next; + int gpl_compatible; + struct symbol *unres; + int from_dump; /* 1 if module was loaded from *.symvers */ + int is_vmlinux; + int seen; + int has_init; + int has_cleanup; + struct buffer dev_table_buf; + char srcversion[25]; + // Missing namespace dependencies + struct namespace_list *missing_namespaces; + // Actual imported namespaces + struct namespace_list *imported_namespaces; + char name[]; +}; + +struct elf_info { + size_t size; + Elf_Ehdr *hdr; + Elf_Shdr *sechdrs; + Elf_Sym *symtab_start; + Elf_Sym *symtab_stop; + Elf_Section export_sec; + Elf_Section export_unused_sec; + Elf_Section export_gpl_sec; + Elf_Section export_unused_gpl_sec; + Elf_Section export_gpl_future_sec; + char *strtab; + char *modinfo; + unsigned int modinfo_len; + + /* support for 32bit section numbers */ + + unsigned int num_sections; /* max_secindex + 1 */ + unsigned int secindex_strings; + /* if Nth symbol table entry has .st_shndx = SHN_XINDEX, + * take shndx from symtab_shndx_start[N] instead */ + Elf32_Word *symtab_shndx_start; + Elf32_Word *symtab_shndx_stop; +}; + +static inline int is_shndx_special(unsigned int i) +{ + return i != SHN_XINDEX && i >= SHN_LORESERVE && i <= SHN_HIRESERVE; +} + +/* + * Move reserved section indices SHN_LORESERVE..SHN_HIRESERVE out of + * the way to -256..-1, to avoid conflicting with real section + * indices. + */ +#define SPECIAL(i) ((i) - (SHN_HIRESERVE + 1)) + +/* Accessor for sym->st_shndx, hides ugliness of "64k sections" */ +static inline unsigned int get_secindex(const struct elf_info *info, + const Elf_Sym *sym) +{ + if (is_shndx_special(sym->st_shndx)) + return SPECIAL(sym->st_shndx); + if (sym->st_shndx != SHN_XINDEX) + return sym->st_shndx; + return info->symtab_shndx_start[sym - info->symtab_start]; +} + +/* file2alias.c */ +extern unsigned int cross_build; +void handle_moddevtable(struct module *mod, struct elf_info *info, + Elf_Sym *sym, const char *symname); +void add_moddevtable(struct buffer *buf, struct module *mod); + +/* sumversion.c */ +void get_src_version(const char *modname, char sum[], unsigned sumlen); + +/* from modpost.c */ +char *read_text_file(const char *filename); +char *get_line(char **stringp); + +enum loglevel { + LOG_WARN, + LOG_ERROR, + LOG_FATAL +}; + +void modpost_log(enum loglevel loglevel, const char *fmt, ...); + +#define warn(fmt, args...) modpost_log(LOG_WARN, fmt, ##args) +#define merror(fmt, args...) modpost_log(LOG_ERROR, fmt, ##args) +#define fatal(fmt, args...) modpost_log(LOG_FATAL, fmt, ##args) diff --git a/src/net/scripts/mod/sumversion.c b/src/net/scripts/mod/sumversion.c new file mode 100644 index 0000000..d587f40 --- /dev/null +++ b/src/net/scripts/mod/sumversion.c @@ -0,0 +1,420 @@ +#include <netinet/in.h> +#ifdef __sun__ +#include <inttypes.h> +#else +#include <stdint.h> +#endif +#include <ctype.h> +#include <errno.h> +#include <string.h> +#include <limits.h> +#include "modpost.h" + +/* + * Stolen form Cryptographic API. + * + * MD4 Message Digest Algorithm (RFC1320). + * + * Implementation derived from Andrew Tridgell and Steve French's + * CIFS MD4 implementation, and the cryptoapi implementation + * originally based on the public domain implementation written + * by Colin Plumb in 1993. + * + * Copyright (c) Andrew Tridgell 1997-1998. + * Modified by Steve French (sfrench@us.ibm.com) 2002 + * Copyright (c) Cryptoapi developers. + * Copyright (c) 2002 David S. Miller (davem@redhat.com) + * Copyright (c) 2002 James Morris <jmorris@intercode.com.au> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ +#define MD4_DIGEST_SIZE 16 +#define MD4_HMAC_BLOCK_SIZE 64 +#define MD4_BLOCK_WORDS 16 +#define MD4_HASH_WORDS 4 + +struct md4_ctx { + uint32_t hash[MD4_HASH_WORDS]; + uint32_t block[MD4_BLOCK_WORDS]; + uint64_t byte_count; +}; + +static inline uint32_t lshift(uint32_t x, unsigned int s) +{ + x &= 0xFFFFFFFF; + return ((x << s) & 0xFFFFFFFF) | (x >> (32 - s)); +} + +static inline uint32_t F(uint32_t x, uint32_t y, uint32_t z) +{ + return (x & y) | ((~x) & z); +} + +static inline uint32_t G(uint32_t x, uint32_t y, uint32_t z) +{ + return (x & y) | (x & z) | (y & z); +} + +static inline uint32_t H(uint32_t x, uint32_t y, uint32_t z) +{ + return x ^ y ^ z; +} + +#define ROUND1(a,b,c,d,k,s) (a = lshift(a + F(b,c,d) + k, s)) +#define ROUND2(a,b,c,d,k,s) (a = lshift(a + G(b,c,d) + k + (uint32_t)0x5A827999,s)) +#define ROUND3(a,b,c,d,k,s) (a = lshift(a + H(b,c,d) + k + (uint32_t)0x6ED9EBA1,s)) + +/* XXX: this stuff can be optimized */ +static inline void le32_to_cpu_array(uint32_t *buf, unsigned int words) +{ + while (words--) { + *buf = ntohl(*buf); + buf++; + } +} + +static inline void cpu_to_le32_array(uint32_t *buf, unsigned int words) +{ + while (words--) { + *buf = htonl(*buf); + buf++; + } +} + +static void md4_transform(uint32_t *hash, uint32_t const *in) +{ + uint32_t a, b, c, d; + + a = hash[0]; + b = hash[1]; + c = hash[2]; + d = hash[3]; + + ROUND1(a, b, c, d, in[0], 3); + ROUND1(d, a, b, c, in[1], 7); + ROUND1(c, d, a, b, in[2], 11); + ROUND1(b, c, d, a, in[3], 19); + ROUND1(a, b, c, d, in[4], 3); + ROUND1(d, a, b, c, in[5], 7); + ROUND1(c, d, a, b, in[6], 11); + ROUND1(b, c, d, a, in[7], 19); + ROUND1(a, b, c, d, in[8], 3); + ROUND1(d, a, b, c, in[9], 7); + ROUND1(c, d, a, b, in[10], 11); + ROUND1(b, c, d, a, in[11], 19); + ROUND1(a, b, c, d, in[12], 3); + ROUND1(d, a, b, c, in[13], 7); + ROUND1(c, d, a, b, in[14], 11); + ROUND1(b, c, d, a, in[15], 19); + + ROUND2(a, b, c, d,in[ 0], 3); + ROUND2(d, a, b, c, in[4], 5); + ROUND2(c, d, a, b, in[8], 9); + ROUND2(b, c, d, a, in[12], 13); + ROUND2(a, b, c, d, in[1], 3); + ROUND2(d, a, b, c, in[5], 5); + ROUND2(c, d, a, b, in[9], 9); + ROUND2(b, c, d, a, in[13], 13); + ROUND2(a, b, c, d, in[2], 3); + ROUND2(d, a, b, c, in[6], 5); + ROUND2(c, d, a, b, in[10], 9); + ROUND2(b, c, d, a, in[14], 13); + ROUND2(a, b, c, d, in[3], 3); + ROUND2(d, a, b, c, in[7], 5); + ROUND2(c, d, a, b, in[11], 9); + ROUND2(b, c, d, a, in[15], 13); + + ROUND3(a, b, c, d,in[ 0], 3); + ROUND3(d, a, b, c, in[8], 9); + ROUND3(c, d, a, b, in[4], 11); + ROUND3(b, c, d, a, in[12], 15); + ROUND3(a, b, c, d, in[2], 3); + ROUND3(d, a, b, c, in[10], 9); + ROUND3(c, d, a, b, in[6], 11); + ROUND3(b, c, d, a, in[14], 15); + ROUND3(a, b, c, d, in[1], 3); + ROUND3(d, a, b, c, in[9], 9); + ROUND3(c, d, a, b, in[5], 11); + ROUND3(b, c, d, a, in[13], 15); + ROUND3(a, b, c, d, in[3], 3); + ROUND3(d, a, b, c, in[11], 9); + ROUND3(c, d, a, b, in[7], 11); + ROUND3(b, c, d, a, in[15], 15); + + hash[0] += a; + hash[1] += b; + hash[2] += c; + hash[3] += d; +} + +static inline void md4_transform_helper(struct md4_ctx *ctx) +{ + le32_to_cpu_array(ctx->block, sizeof(ctx->block) / sizeof(uint32_t)); + md4_transform(ctx->hash, ctx->block); +} + +static void md4_init(struct md4_ctx *mctx) +{ + mctx->hash[0] = 0x67452301; + mctx->hash[1] = 0xefcdab89; + mctx->hash[2] = 0x98badcfe; + mctx->hash[3] = 0x10325476; + mctx->byte_count = 0; +} + +static void md4_update(struct md4_ctx *mctx, + const unsigned char *data, unsigned int len) +{ + const uint32_t avail = sizeof(mctx->block) - (mctx->byte_count & 0x3f); + + mctx->byte_count += len; + + if (avail > len) { + memcpy((char *)mctx->block + (sizeof(mctx->block) - avail), + data, len); + return; + } + + memcpy((char *)mctx->block + (sizeof(mctx->block) - avail), + data, avail); + + md4_transform_helper(mctx); + data += avail; + len -= avail; + + while (len >= sizeof(mctx->block)) { + memcpy(mctx->block, data, sizeof(mctx->block)); + md4_transform_helper(mctx); + data += sizeof(mctx->block); + len -= sizeof(mctx->block); + } + + memcpy(mctx->block, data, len); +} + +static void md4_final_ascii(struct md4_ctx *mctx, char *out, unsigned int len) +{ + const unsigned int offset = mctx->byte_count & 0x3f; + char *p = (char *)mctx->block + offset; + int padding = 56 - (offset + 1); + + *p++ = 0x80; + if (padding < 0) { + memset(p, 0x00, padding + sizeof (uint64_t)); + md4_transform_helper(mctx); + p = (char *)mctx->block; + padding = 56; + } + + memset(p, 0, padding); + mctx->block[14] = mctx->byte_count << 3; + mctx->block[15] = mctx->byte_count >> 29; + le32_to_cpu_array(mctx->block, (sizeof(mctx->block) - + sizeof(uint64_t)) / sizeof(uint32_t)); + md4_transform(mctx->hash, mctx->block); + cpu_to_le32_array(mctx->hash, sizeof(mctx->hash) / sizeof(uint32_t)); + + snprintf(out, len, "%08X%08X%08X%08X", + mctx->hash[0], mctx->hash[1], mctx->hash[2], mctx->hash[3]); +} + +static inline void add_char(unsigned char c, struct md4_ctx *md) +{ + md4_update(md, &c, 1); +} + +static int parse_string(const char *file, unsigned long len, + struct md4_ctx *md) +{ + unsigned long i; + + add_char(file[0], md); + for (i = 1; i < len; i++) { + add_char(file[i], md); + if (file[i] == '"' && file[i-1] != '\\') + break; + } + return i; +} + +static int parse_comment(const char *file, unsigned long len) +{ + unsigned long i; + + for (i = 2; i < len; i++) { + if (file[i-1] == '*' && file[i] == '/') + break; + } + return i; +} + +/* FIXME: Handle .s files differently (eg. # starts comments) --RR */ +static int parse_file(const char *fname, struct md4_ctx *md) +{ + char *file; + unsigned long i, len; + + file = read_text_file(fname); + len = strlen(file); + + for (i = 0; i < len; i++) { + /* Collapse and ignore \ and CR. */ + if (file[i] == '\\' && (i+1 < len) && file[i+1] == '\n') { + i++; + continue; + } + + /* Ignore whitespace */ + if (isspace(file[i])) + continue; + + /* Handle strings as whole units */ + if (file[i] == '"') { + i += parse_string(file+i, len - i, md); + continue; + } + + /* Comments: ignore */ + if (file[i] == '/' && file[i+1] == '*') { + i += parse_comment(file+i, len - i); + continue; + } + + add_char(file[i], md); + } + free(file); + return 1; +} +/* Check whether the file is a static library or not */ +static int is_static_library(const char *objfile) +{ + int len = strlen(objfile); + if (objfile[len - 2] == '.' && objfile[len - 1] == 'a') + return 1; + else + return 0; +} + +/* We have dir/file.o. Open dir/.file.o.cmd, look for source_ and deps_ line + * to figure out source files. */ +static int parse_source_files(const char *objfile, struct md4_ctx *md) +{ + char *cmd, *file, *line, *dir, *pos; + const char *base; + int dirlen, ret = 0, check_files = 0; + + cmd = NOFAIL(malloc(strlen(objfile) + sizeof("..cmd"))); + + base = strrchr(objfile, '/'); + if (base) { + base++; + dirlen = base - objfile; + sprintf(cmd, "%.*s.%s.cmd", dirlen, objfile, base); + } else { + dirlen = 0; + sprintf(cmd, ".%s.cmd", objfile); + } + dir = NOFAIL(malloc(dirlen + 1)); + strncpy(dir, objfile, dirlen); + dir[dirlen] = '\0'; + + file = read_text_file(cmd); + + pos = file; + + /* Sum all files in the same dir or subdirs. */ + while ((line = get_line(&pos))) { + char* p = line; + + if (strncmp(line, "source_", sizeof("source_")-1) == 0) { + p = strrchr(line, ' '); + if (!p) { + warn("malformed line: %s\n", line); + goto out_file; + } + p++; + if (!parse_file(p, md)) { + warn("could not open %s: %s\n", + p, strerror(errno)); + goto out_file; + } + continue; + } + if (strncmp(line, "deps_", sizeof("deps_")-1) == 0) { + check_files = 1; + continue; + } + if (!check_files) + continue; + + /* Continue until line does not end with '\' */ + if ( *(p + strlen(p)-1) != '\\') + break; + /* Terminate line at first space, to get rid of final ' \' */ + while (*p) { + if (isspace(*p)) { + *p = '\0'; + break; + } + p++; + } + + /* Check if this file is in same dir as objfile */ + if ((strstr(line, dir)+strlen(dir)-1) == strrchr(line, '/')) { + if (!parse_file(line, md)) { + warn("could not open %s: %s\n", + line, strerror(errno)); + goto out_file; + } + + } + + } + + /* Everyone parsed OK */ + ret = 1; +out_file: + free(file); + free(dir); + free(cmd); + return ret; +} + +/* Calc and record src checksum. */ +void get_src_version(const char *modname, char sum[], unsigned sumlen) +{ + char *buf, *pos, *firstline; + struct md4_ctx md; + char *fname; + char filelist[PATH_MAX + 1]; + + /* objects for a module are listed in the first line of *.mod file. */ + snprintf(filelist, sizeof(filelist), "%.*smod", + (int)strlen(modname) - 1, modname); + + buf = read_text_file(filelist); + + pos = buf; + firstline = get_line(&pos); + if (!firstline) { + warn("bad ending versions file for %s\n", modname); + goto free; + } + + md4_init(&md); + while ((fname = strsep(&firstline, " "))) { + if (!*fname) + continue; + if (!(is_static_library(fname)) && + !parse_source_files(fname, &md)) + goto free; + } + + md4_final_ascii(&md, sum, sumlen); +free: + free(buf); +} diff --git a/src/net/scripts/module.lds.S b/src/net/scripts/module.lds.S new file mode 100644 index 0000000..c5f1219 --- /dev/null +++ b/src/net/scripts/module.lds.S @@ -0,0 +1,55 @@ +/* + * Common module linker script, always used when linking a module. + * Archs are free to supply their own linker scripts. ld will + * combine them automatically. + */ +SECTIONS { + /DISCARD/ : { + *(.discard) + *(.discard.*) + } + + __ksymtab 0 : { *(SORT(___ksymtab+*)) } + __ksymtab_gpl 0 : { *(SORT(___ksymtab_gpl+*)) } + __ksymtab_unused 0 : { *(SORT(___ksymtab_unused+*)) } + __ksymtab_unused_gpl 0 : { *(SORT(___ksymtab_unused_gpl+*)) } + __ksymtab_gpl_future 0 : { *(SORT(___ksymtab_gpl_future+*)) } + __kcrctab 0 : { *(SORT(___kcrctab+*)) } + __kcrctab_gpl 0 : { *(SORT(___kcrctab_gpl+*)) } + __kcrctab_unused 0 : { *(SORT(___kcrctab_unused+*)) } + __kcrctab_unused_gpl 0 : { *(SORT(___kcrctab_unused_gpl+*)) } + __kcrctab_gpl_future 0 : { *(SORT(___kcrctab_gpl_future+*)) } + + .init_array 0 : ALIGN(8) { *(SORT(.init_array.*)) *(.init_array) } + + __jump_table 0 : ALIGN(8) { KEEP(*(__jump_table)) } + + __patchable_function_entries : { *(__patchable_function_entries) } + +#ifdef CONFIG_LTO_CLANG + /* + * With CONFIG_LTO_CLANG, LLD always enables -fdata-sections and + * -ffunction-sections, which increases the size of the final module. + * Merge the split sections in the final binary. + */ + .bss : { + *(.bss .bss.[0-9a-zA-Z_]*) + *(.bss..L*) + } + + .data : { + *(.data .data.[0-9a-zA-Z_]*) + *(.data..L*) + } + + .rodata : { + *(.rodata .rodata.[0-9a-zA-Z_]*) + *(.rodata..L*) + } + + .text : { *(.text .text.[0-9a-zA-Z_]*) } +#endif +} + +/* bring in arch-specific sections */ +#include <asm/module.lds.h> diff --git a/src/net/scripts/modules-check.sh b/src/net/scripts/modules-check.sh new file mode 100755 index 0000000..43de226 --- /dev/null +++ b/src/net/scripts/modules-check.sh @@ -0,0 +1,26 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0 + +set -e + +if [ $# != 1 ]; then + echo "Usage: $0 <modules.order>" >& 2 + exit 1 +fi + +exit_code=0 + +# Check uniqueness of module names +check_same_name_modules() +{ + for m in $(sed 's:.*/::' $1 | sort | uniq -d) + do + echo "error: the following would cause module name conflict:" >&2 + sed -n "/\/$m/s:^: :p" modules.order >&2 + exit_code=1 + done +} + +check_same_name_modules "$1" + +exit $exit_code diff --git a/src/net/scripts/nsdeps b/src/net/scripts/nsdeps new file mode 100644 index 0000000..dab4c1a --- /dev/null +++ b/src/net/scripts/nsdeps @@ -0,0 +1,63 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0 +# Linux kernel symbol namespace import generator +# +# This script requires a minimum spatch version. +SPATCH_REQ_VERSION="1.0.4" + +DIR="$(dirname $(readlink -f $0))/.." +SPATCH="`which ${SPATCH:=spatch}`" +if [ ! -x "$SPATCH" ]; then + echo 'spatch is part of the Coccinelle project and is available at http://coccinelle.lip6.fr/' + exit 1 +fi + +SPATCH_REQ_VERSION_NUM=$(echo $SPATCH_REQ_VERSION | ${DIR}/scripts/ld-version.sh) +SPATCH_VERSION=$($SPATCH --version | head -1 | awk '{print $3}') +SPATCH_VERSION_NUM=$(echo $SPATCH_VERSION | ${DIR}/scripts/ld-version.sh) + +if [ "$SPATCH_VERSION_NUM" -lt "$SPATCH_REQ_VERSION_NUM" ] ; then + echo "spatch needs to be version $SPATCH_REQ_VERSION or higher" + exit 1 +fi + +if [ "$KBUILD_EXTMOD" ]; then + src_prefix= +else + src_prefix=$srctree/ +fi + +generate_deps_for_ns() { + $SPATCH --very-quiet --in-place --sp-file \ + $srctree/scripts/coccinelle/misc/add_namespace.cocci -D nsdeps -D ns=$1 $2 +} + +generate_deps() { + local mod=${1%.ko:} + shift + local namespaces="$*" + local mod_source_files="`cat $mod.mod | sed -n 1p \ + | sed -e 's/\.o/\.c/g' \ + | sed "s|[^ ]* *|${src_prefix}&|g"`" + for ns in $namespaces; do + echo "Adding namespace $ns to module $mod.ko." + generate_deps_for_ns $ns "$mod_source_files" + # sort the imports + for source_file in $mod_source_files; do + sed '/MODULE_IMPORT_NS/Q' $source_file > ${source_file}.tmp + offset=$(wc -l ${source_file}.tmp | awk '{print $1;}') + cat $source_file | grep MODULE_IMPORT_NS | LANG=C sort -u >> ${source_file}.tmp + tail -n +$((offset +1)) ${source_file} | grep -v MODULE_IMPORT_NS >> ${source_file}.tmp + if ! diff -q ${source_file} ${source_file}.tmp; then + mv ${source_file}.tmp ${source_file} + else + rm ${source_file}.tmp + fi + done + done +} + +while read line +do + generate_deps $line +done < $MODULES_NSDEPS diff --git a/src/net/scripts/objdiff b/src/net/scripts/objdiff new file mode 100755 index 0000000..72b0b63 --- /dev/null +++ b/src/net/scripts/objdiff @@ -0,0 +1,162 @@ +#!/bin/bash +# SPDX-License-Identifier: GPL-2.0-only + +# objdiff - a small script for validating that a commit or series of commits +# didn't change object code. +# +# Copyright 2014, Jason Cooper <jason@lakedaemon.net> +# + +# usage example: +# +# $ git checkout COMMIT_A +# $ <your fancy build command here> +# $ ./scripts/objdiff record path/to/*.o +# +# $ git checkout COMMIT_B +# $ <your fancy build command here> +# $ ./scripts/objdiff record path/to/*.o +# +# $ ./scripts/objdiff diff COMMIT_A COMMIT_B +# $ + +# And to clean up (everything is in .tmp_objdiff/*) +# $ ./scripts/objdiff clean all +# +# Note: 'make mrproper' will also remove .tmp_objdiff + +SRCTREE=$(cd $(git rev-parse --show-toplevel 2>/dev/null); pwd) + +if [ -z "$SRCTREE" ]; then + echo >&2 "ERROR: Not a git repository." + exit 1 +fi + +TMPD=$SRCTREE/.tmp_objdiff + +usage() { + echo >&2 "Usage: $0 <command> <args>" + echo >&2 " record <list of object files or directories>" + echo >&2 " diff <commitA> <commitB>" + echo >&2 " clean all | <commit>" + exit 1 +} + +get_output_dir() { + dir=${1%/*} + + if [ "$dir" = "$1" ]; then + dir=. + fi + + dir=$(cd $dir; pwd) + + echo $TMPD/$CMT${dir#$SRCTREE} +} + +do_objdump() { + dir=$(get_output_dir $1) + base=${1##*/} + stripped=$dir/${base%.o}.stripped + dis=$dir/${base%.o}.dis + + [ ! -d "$dir" ] && mkdir -p $dir + + # remove addresses for a cleaner diff + # http://dummdida.tumblr.com/post/60924060451/binary-diff-between-libc-from-scientificlinux-and + $STRIP -g $1 -R __bug_table -R .note -R .comment -o $stripped + $OBJDUMP -D $stripped | sed -e "s/^[[:space:]]\+[0-9a-f]\+//" -e "s:^$stripped:$1:" > $dis +} + +dorecord() { + [ $# -eq 0 ] && usage + + FILES="$*" + + CMT="`git rev-parse --short HEAD`" + + STRIP="${CROSS_COMPILE}strip" + OBJDUMP="${CROSS_COMPILE}objdump" + + for d in $FILES; do + if [ -d "$d" ]; then + for f in $(find $d -name '*.o') + do + do_objdump $f + done + else + do_objdump $d + fi + done +} + +dodiff() { + [ $# -ne 2 ] && [ $# -ne 0 ] && usage + + if [ $# -eq 0 ]; then + SRC="`git rev-parse --short HEAD^`" + DST="`git rev-parse --short HEAD`" + else + SRC="`git rev-parse --short $1`" + DST="`git rev-parse --short $2`" + fi + + DIFF="`which colordiff`" + + if [ ${#DIFF} -eq 0 ] || [ ! -x "$DIFF" ]; then + DIFF="`which diff`" + fi + + SRCD="$TMPD/$SRC" + DSTD="$TMPD/$DST" + + if [ ! -d "$SRCD" ]; then + echo >&2 "ERROR: $SRCD doesn't exist" + exit 1 + fi + + if [ ! -d "$DSTD" ]; then + echo >&2 "ERROR: $DSTD doesn't exist" + exit 1 + fi + + $DIFF -Nurd $SRCD $DSTD +} + +doclean() { + [ $# -eq 0 ] && usage + [ $# -gt 1 ] && usage + + if [ "x$1" = "xall" ]; then + rm -rf $TMPD/* + else + CMT="`git rev-parse --short $1`" + + if [ -d "$TMPD/$CMT" ]; then + rm -rf $TMPD/$CMT + else + echo >&2 "$CMT not found" + fi + fi +} + +[ $# -eq 0 ] && usage + +case "$1" in + record) + shift + dorecord $* + ;; + diff) + shift + dodiff $* + ;; + clean) + shift + doclean $* + ;; + *) + echo >&2 "Unrecognized command '$1'" + exit 1 + ;; +esac diff --git a/src/net/scripts/package/builddeb b/src/net/scripts/package/builddeb new file mode 100755 index 0000000..cd558ad --- /dev/null +++ b/src/net/scripts/package/builddeb @@ -0,0 +1,240 @@ +#!/bin/sh +# +# builddeb 1.3 +# Copyright 2003 Wichert Akkerman <wichert@wiggy.net> +# +# Simple script to generate a deb package for a Linux kernel. All the +# complexity of what to do with a kernel after it is installed or removed +# is left to other scripts and packages: they can install scripts in the +# /etc/kernel/{pre,post}{inst,rm}.d/ directories (or an alternative location +# specified in KDEB_HOOKDIR) that will be called on package install and +# removal. + +set -e + +is_enabled() { + grep -q "^$1=y" include/config/auto.conf +} + +if_enabled_echo() { + if is_enabled "$1"; then + echo -n "$2" + elif [ $# -ge 3 ]; then + echo -n "$3" + fi +} + +create_package() { + local pname="$1" pdir="$2" + local dpkg_deb_opts + + mkdir -m 755 -p "$pdir/DEBIAN" + mkdir -p "$pdir/usr/share/doc/$pname" + cp debian/copyright "$pdir/usr/share/doc/$pname/" + cp debian/changelog "$pdir/usr/share/doc/$pname/changelog.Debian" + gzip -n -9 "$pdir/usr/share/doc/$pname/changelog.Debian" + sh -c "cd '$pdir'; find . -type f ! -path './DEBIAN/*' -printf '%P\0' \ + | xargs -r0 md5sum > DEBIAN/md5sums" + + # Fix ownership and permissions + if [ "$DEB_RULES_REQUIRES_ROOT" = "no" ]; then + dpkg_deb_opts="--root-owner-group" + else + chown -R root:root "$pdir" + fi + chmod -R go-w "$pdir" + # in case we are in a restrictive umask environment like 0077 + chmod -R a+rX "$pdir" + # in case we build in a setuid/setgid directory + chmod -R ug-s "$pdir" + + # Create the package + dpkg-gencontrol -p$pname -P"$pdir" + dpkg-deb $dpkg_deb_opts ${KDEB_COMPRESS:+-Z$KDEB_COMPRESS} --build "$pdir" .. +} + +deploy_kernel_headers () { + pdir=$1 + + rm -rf $pdir + + ( + cd $srctree + find . arch/$SRCARCH -maxdepth 1 -name Makefile\* + find include scripts -type f -o -type l + find arch/$SRCARCH -name Kbuild.platforms -o -name Platform + find $(find arch/$SRCARCH -name include -o -name scripts -type d) -type f + ) > debian/hdrsrcfiles + + { + if is_enabled CONFIG_STACK_VALIDATION; then + echo tools/objtool/objtool + fi + + find arch/$SRCARCH/include Module.symvers include scripts -type f + + if is_enabled CONFIG_GCC_PLUGINS; then + find scripts/gcc-plugins -name \*.so + fi + } > debian/hdrobjfiles + + destdir=$pdir/usr/src/linux-headers-$version + mkdir -p $destdir + tar -c -f - -C $srctree -T debian/hdrsrcfiles | tar -xf - -C $destdir + tar -c -f - -T debian/hdrobjfiles | tar -xf - -C $destdir + rm -f debian/hdrsrcfiles debian/hdrobjfiles + + # copy .config manually to be where it's expected to be + cp $KCONFIG_CONFIG $destdir/.config + + mkdir -p $pdir/lib/modules/$version/ + ln -s /usr/src/linux-headers-$version $pdir/lib/modules/$version/build +} + +deploy_libc_headers () { + pdir=$1 + + rm -rf $pdir + + $MAKE -f $srctree/Makefile headers + $MAKE -f $srctree/Makefile headers_install INSTALL_HDR_PATH=$pdir/usr + + # move asm headers to /usr/include/<libc-machine>/asm to match the structure + # used by Debian-based distros (to support multi-arch) + host_arch=$(dpkg-architecture -a$(cat debian/arch) -qDEB_HOST_MULTIARCH) + mkdir $pdir/usr/include/$host_arch + mv $pdir/usr/include/asm $pdir/usr/include/$host_arch/ +} + +version=$KERNELRELEASE +tmpdir=debian/linux-image +dbg_dir=debian/linux-image-dbg +packagename=linux-image-$version +dbg_packagename=$packagename-dbg + +if [ "$ARCH" = "um" ] ; then + packagename=user-mode-linux-$version +fi + +# Not all arches have the same installed path in debian +# XXX: have each arch Makefile export a variable of the canonical image install +# path instead +case $ARCH in +um) + installed_image_path="usr/bin/linux-$version" + ;; +parisc|mips|powerpc) + installed_image_path="boot/vmlinux-$version" + ;; +sw_64) + installed_image_path="boot/vmlinux.bin-$version" + ;; +*) + installed_image_path="boot/vmlinuz-$version" +esac + +BUILD_DEBUG=$(if_enabled_echo CONFIG_DEBUG_INFO Yes) + +# Setup the directory structure +rm -rf "$tmpdir" "$dbg_dir" debian/files +mkdir -m 755 -p "$tmpdir/DEBIAN" +mkdir -p "$tmpdir/lib" "$tmpdir/boot" + +# Install the kernel +if [ "$ARCH" = "um" ] ; then + mkdir -p "$tmpdir/usr/lib/uml/modules/$version" "$tmpdir/usr/bin" "$tmpdir/usr/share/doc/$packagename" + cp System.map "$tmpdir/usr/lib/uml/modules/$version/System.map" + cp $KCONFIG_CONFIG "$tmpdir/usr/share/doc/$packagename/config" + gzip "$tmpdir/usr/share/doc/$packagename/config" +else + cp System.map "$tmpdir/boot/System.map-$version" + cp $KCONFIG_CONFIG "$tmpdir/boot/config-$version" +fi +cp "$($MAKE -s -f $srctree/Makefile image_name)" "$tmpdir/$installed_image_path" + +if is_enabled CONFIG_OF_EARLY_FLATTREE; then + # Only some architectures with OF support have this target + if [ -d "${srctree}/arch/$SRCARCH/boot/dts" ]; then + $MAKE -f $srctree/Makefile INSTALL_DTBS_PATH="$tmpdir/usr/lib/$packagename" dtbs_install + fi +fi + +if is_enabled CONFIG_MODULES; then + INSTALL_MOD_PATH="$tmpdir" $MAKE -f $srctree/Makefile modules_install + rm -f "$tmpdir/lib/modules/$version/build" + rm -f "$tmpdir/lib/modules/$version/source" + if [ "$ARCH" = "um" ] ; then + mv "$tmpdir/lib/modules/$version"/* "$tmpdir/usr/lib/uml/modules/$version/" + rmdir "$tmpdir/lib/modules/$version" + fi + if [ -n "$BUILD_DEBUG" ] ; then + for module in $(find $tmpdir/lib/modules/ -name *.ko -printf '%P\n'); do + module=lib/modules/$module + mkdir -p $(dirname $dbg_dir/usr/lib/debug/$module) + # only keep debug symbols in the debug file + $OBJCOPY --only-keep-debug $tmpdir/$module $dbg_dir/usr/lib/debug/$module + # strip original module from debug symbols + $OBJCOPY --strip-debug $tmpdir/$module + # then add a link to those + $OBJCOPY --add-gnu-debuglink=$dbg_dir/usr/lib/debug/$module $tmpdir/$module + done + + # resign stripped modules + if is_enabled CONFIG_MODULE_SIG_ALL; then + INSTALL_MOD_PATH="$tmpdir" $MAKE -f $srctree/Makefile modules_sign + fi + fi +fi + +# Install the maintainer scripts +# Note: hook scripts under /etc/kernel are also executed by official Debian +# kernel packages, as well as kernel packages built using make-kpkg. +# make-kpkg sets $INITRD to indicate whether an initramfs is wanted, and +# so do we; recent versions of dracut and initramfs-tools will obey this. +debhookdir=${KDEB_HOOKDIR:-/etc/kernel} +for script in postinst postrm preinst prerm ; do + mkdir -p "$tmpdir$debhookdir/$script.d" + cat <<EOF > "$tmpdir/DEBIAN/$script" +#!/bin/sh + +set -e + +# Pass maintainer script parameters to hook scripts +export DEB_MAINT_PARAMS="\$*" + +# Tell initramfs builder whether it's wanted +export INITRD=$(if_enabled_echo CONFIG_BLK_DEV_INITRD Yes No) + +test -d $debhookdir/$script.d && run-parts --arg="$version" --arg="/$installed_image_path" $debhookdir/$script.d +exit 0 +EOF + chmod 755 "$tmpdir/DEBIAN/$script" +done + +if [ "$ARCH" != "um" ]; then + if is_enabled CONFIG_MODULES; then + deploy_kernel_headers debian/linux-headers + create_package linux-headers-$version debian/linux-headers + fi + + deploy_libc_headers debian/linux-libc-dev + create_package linux-libc-dev debian/linux-libc-dev +fi + +create_package "$packagename" "$tmpdir" + +if [ -n "$BUILD_DEBUG" ] ; then + # Build debug package + # Different tools want the image in different locations + # perf + mkdir -p $dbg_dir/usr/lib/debug/lib/modules/$version/ + cp vmlinux $dbg_dir/usr/lib/debug/lib/modules/$version/ + # systemtap + mkdir -p $dbg_dir/usr/lib/debug/boot/ + ln -s ../lib/modules/$version/vmlinux $dbg_dir/usr/lib/debug/boot/vmlinux-$version + # kdump-tools + ln -s lib/modules/$version/vmlinux $dbg_dir/usr/lib/debug/vmlinux-$version + create_package "$dbg_packagename" "$dbg_dir" +fi + +exit 0 diff --git a/src/net/scripts/package/buildtar b/src/net/scripts/package/buildtar new file mode 100755 index 0000000..a0e4c7b --- /dev/null +++ b/src/net/scripts/package/buildtar @@ -0,0 +1,159 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0 + +# +# buildtar 0.0.5 +# +# (C) 2004-2006 by Jan-Benedict Glaw <jbglaw@lug-owl.de> +# +# This script is used to compile a tarball from the currently +# prepared kernel. Based upon the builddeb script from +# Wichert Akkerman <wichert@wiggy.net>. +# + +set -e + +# +# Some variables and settings used throughout the script +# +tmpdir="${objtree}/tar-install" +tarball="${objtree}/linux-${KERNELRELEASE}-${ARCH}.tar" + + +# +# Figure out how to compress, if requested at all +# +case "${1}" in + dir-pkg|tar-pkg) + opts= + ;; + targz-pkg) + opts="-I ${KGZIP}" + tarball=${tarball}.gz + ;; + tarbz2-pkg) + opts="-I ${KBZIP2}" + tarball=${tarball}.bz2 + ;; + tarxz-pkg) + opts="-I ${XZ}" + tarball=${tarball}.xz + ;; + *) + echo "Unknown tarball target \"${1}\" requested, please add it to ${0}." >&2 + exit 1 + ;; +esac + + +# +# Clean-up and re-create the temporary directory +# +rm -rf -- "${tmpdir}" +mkdir -p -- "${tmpdir}/boot" +dirs=boot + + +# +# Try to install dtbs +# +if grep -q '^CONFIG_OF_EARLY_FLATTREE=y' include/config/auto.conf; then + # Only some architectures with OF support have this target + if [ -d "${srctree}/arch/${SRCARCH}/boot/dts" ]; then + $MAKE ARCH="${ARCH}" -f ${srctree}/Makefile INSTALL_DTBS_PATH="${tmpdir}/boot/dtbs/${KERNELRELEASE}" dtbs_install + fi +fi + + +# +# Try to install modules +# +if grep -q '^CONFIG_MODULES=y' include/config/auto.conf; then + make ARCH="${ARCH}" -f ${srctree}/Makefile INSTALL_MOD_PATH="${tmpdir}" modules_install + dirs="$dirs lib" +fi + + +# +# Install basic kernel files +# +cp -v -- "${objtree}/System.map" "${tmpdir}/boot/System.map-${KERNELRELEASE}" +cp -v -- "${KCONFIG_CONFIG}" "${tmpdir}/boot/config-${KERNELRELEASE}" +cp -v -- "${objtree}/vmlinux" "${tmpdir}/boot/vmlinux-${KERNELRELEASE}" + + +# +# Install arch-specific kernel image(s) +# +case "${ARCH}" in + x86|i386|x86_64) + [ -f "${objtree}/arch/x86/boot/bzImage" ] && cp -v -- "${objtree}/arch/x86/boot/bzImage" "${tmpdir}/boot/vmlinuz-${KERNELRELEASE}" + ;; + alpha) + [ -f "${objtree}/arch/alpha/boot/vmlinux.gz" ] && cp -v -- "${objtree}/arch/alpha/boot/vmlinux.gz" "${tmpdir}/boot/vmlinuz-${KERNELRELEASE}" + ;; + sw_64) + [ -f "${objtree}/arch/sw_64/boot/vmlinux.bin" ] && cp -v -- "${objtree}/arch/sw_64/boot/vmlinux.bin" "${tmpdir}/boot/vmlinux-bin-${KERNELRELEASE}" + ;; + parisc*) + [ -f "${KBUILD_IMAGE}" ] && cp -v -- "${KBUILD_IMAGE}" "${tmpdir}/boot/vmlinux-${KERNELRELEASE}" + [ -f "${objtree}/lifimage" ] && cp -v -- "${objtree}/lifimage" "${tmpdir}/boot/lifimage-${KERNELRELEASE}" + ;; + mips) + if [ -f "${objtree}/arch/mips/boot/compressed/vmlinux.bin" ]; then + cp -v -- "${objtree}/arch/mips/boot/compressed/vmlinux.bin" "${tmpdir}/boot/vmlinuz-${KERNELRELEASE}" + elif [ -f "${objtree}/arch/mips/boot/compressed/vmlinux.ecoff" ]; then + cp -v -- "${objtree}/arch/mips/boot/compressed/vmlinux.ecoff" "${tmpdir}/boot/vmlinuz-${KERNELRELEASE}" + elif [ -f "${objtree}/arch/mips/boot/compressed/vmlinux.srec" ]; then + cp -v -- "${objtree}/arch/mips/boot/compressed/vmlinux.srec" "${tmpdir}/boot/vmlinuz-${KERNELRELEASE}" + elif [ -f "${objtree}/vmlinux.32" ]; then + cp -v -- "${objtree}/vmlinux.32" "${tmpdir}/boot/vmlinux-${KERNELRELEASE}" + elif [ -f "${objtree}/vmlinux.64" ]; then + cp -v -- "${objtree}/vmlinux.64" "${tmpdir}/boot/vmlinux-${KERNELRELEASE}" + elif [ -f "${objtree}/arch/mips/boot/vmlinux.bin" ]; then + cp -v -- "${objtree}/arch/mips/boot/vmlinux.bin" "${tmpdir}/boot/vmlinux-${KERNELRELEASE}" + elif [ -f "${objtree}/arch/mips/boot/vmlinux.ecoff" ]; then + cp -v -- "${objtree}/arch/mips/boot/vmlinux.ecoff" "${tmpdir}/boot/vmlinux-${KERNELRELEASE}" + elif [ -f "${objtree}/arch/mips/boot/vmlinux.srec" ]; then + cp -v -- "${objtree}/arch/mips/boot/vmlinux.srec" "${tmpdir}/boot/vmlinux-${KERNELRELEASE}" + elif [ -f "${objtree}/vmlinux" ]; then + cp -v -- "${objtree}/vmlinux" "${tmpdir}/boot/vmlinux-${KERNELRELEASE}" + fi + ;; + arm64) + for i in Image.bz2 Image.gz Image.lz4 Image.lzma Image.lzo ; do + if [ -f "${objtree}/arch/arm64/boot/${i}" ] ; then + cp -v -- "${objtree}/arch/arm64/boot/${i}" "${tmpdir}/boot/vmlinuz-${KERNELRELEASE}" + break + fi + done + ;; + *) + [ -f "${KBUILD_IMAGE}" ] && cp -v -- "${KBUILD_IMAGE}" "${tmpdir}/boot/vmlinux-kbuild-${KERNELRELEASE}" + echo "" >&2 + echo '** ** ** WARNING ** ** **' >&2 + echo "" >&2 + echo "Your architecture did not define any architecture-dependent files" >&2 + echo "to be placed into the tarball. Please add those to ${0} ..." >&2 + echo "" >&2 + sleep 5 + ;; +esac + +if [ "${1}" = dir-pkg ]; then + echo "Kernel tree successfully created in $tmpdir" + exit 0 +fi + +# +# Create the tarball +# +if tar --owner=root --group=root --help >/dev/null 2>&1; then + opts="$opts --owner=root --group=root" +fi + +tar cf $tarball -C $tmpdir $opts $dirs + +echo "Tarball successfully created in $tarball" + +exit 0 diff --git a/src/net/scripts/package/mkdebian b/src/net/scripts/package/mkdebian new file mode 100755 index 0000000..fdef3f5 --- /dev/null +++ b/src/net/scripts/package/mkdebian @@ -0,0 +1,246 @@ +#!/bin/sh +# +# Copyright 2003 Wichert Akkerman <wichert@wiggy.net> +# +# Simple script to generate a debian/ directory for a Linux kernel. + +set -e + +is_enabled() { + grep -q "^$1=y" include/config/auto.conf +} + +if_enabled_echo() { + if is_enabled "$1"; then + echo -n "$2" + elif [ $# -ge 3 ]; then + echo -n "$3" + fi +} + +set_debarch() { + if [ -n "$KBUILD_DEBARCH" ] ; then + debarch="$KBUILD_DEBARCH" + return + fi + + # Attempt to find the correct Debian architecture + case "$UTS_MACHINE" in + i386|ia64|alpha|m68k|riscv*|sw_64) + debarch="$UTS_MACHINE" ;; + x86_64) + debarch=amd64 ;; + sparc*) + debarch=sparc$(if_enabled_echo CONFIG_64BIT 64) ;; + s390*) + debarch=s390x ;; + ppc*) + if is_enabled CONFIG_64BIT; then + debarch=ppc64$(if_enabled_echo CONFIG_CPU_LITTLE_ENDIAN el) + else + debarch=powerpc$(if_enabled_echo CONFIG_SPE spe) + fi + ;; + parisc*) + debarch=hppa ;; + mips*) + if is_enabled CONFIG_CPU_LITTLE_ENDIAN; then + debarch=mips$(if_enabled_echo CONFIG_64BIT 64)$(if_enabled_echo CONFIG_CPU_MIPSR6 r6)el + elif is_enabled CONFIG_CPU_MIPSR6; then + debarch=mips$(if_enabled_echo CONFIG_64BIT 64)r6 + else + debarch=mips + fi + ;; + aarch64|arm64) + debarch=arm64 ;; + arm*) + if is_enabled CONFIG_AEABI; then + debarch=arm$(if_enabled_echo CONFIG_VFP hf el) + else + debarch=arm + fi + ;; + openrisc) + debarch=or1k ;; + sh) + if is_enabled CONFIG_CPU_SH3; then + debarch=sh3$(if_enabled_echo CONFIG_CPU_BIG_ENDIAN eb) + elif is_enabled CONFIG_CPU_SH4; then + debarch=sh4$(if_enabled_echo CONFIG_CPU_BIG_ENDIAN eb) + fi + ;; + esac + if [ -z "$debarch" ]; then + debarch=$(dpkg-architecture -qDEB_HOST_ARCH) + echo "" >&2 + echo "** ** ** WARNING ** ** **" >&2 + echo "" >&2 + echo "Your architecture doesn't have its equivalent" >&2 + echo "Debian userspace architecture defined!" >&2 + echo "Falling back to the current host architecture ($debarch)." >&2 + echo "Please add support for $UTS_MACHINE to ${0} ..." >&2 + echo "" >&2 + fi +} + +# Some variables and settings used throughout the script +version=$KERNELRELEASE +if [ -n "$KDEB_PKGVERSION" ]; then + packageversion=$KDEB_PKGVERSION + revision=${packageversion##*-} +else + revision=$(cat .version 2>/dev/null||echo 1) + packageversion=$version-$revision +fi +sourcename=$KDEB_SOURCENAME + +if [ "$ARCH" = "um" ] ; then + packagename=user-mode-linux +else + packagename=linux-image +fi + +debarch= +set_debarch + +email=${DEBEMAIL-$EMAIL} + +# use email string directly if it contains <email> +if echo $email | grep -q '<.*>'; then + maintainer=$email +else + # or construct the maintainer string + user=${KBUILD_BUILD_USER-$(id -nu)} + name=${DEBFULLNAME-$user} + if [ -z "$email" ]; then + buildhost=${KBUILD_BUILD_HOST-$(hostname -f 2>/dev/null || hostname)} + email="$user@$buildhost" + fi + maintainer="$name <$email>" +fi + +# Try to determine distribution +if [ -n "$KDEB_CHANGELOG_DIST" ]; then + distribution=$KDEB_CHANGELOG_DIST +# In some cases lsb_release returns the codename as n/a, which breaks dpkg-parsechangelog +elif distribution=$(lsb_release -cs 2>/dev/null) && [ -n "$distribution" ] && [ "$distribution" != "n/a" ]; then + : # nothing to do in this case +else + distribution="unstable" + echo >&2 "Using default distribution of 'unstable' in the changelog" + echo >&2 "Install lsb-release or set \$KDEB_CHANGELOG_DIST explicitly" +fi + +mkdir -p debian/source/ +echo "1.0" > debian/source/format + +echo $debarch > debian/arch +extra_build_depends=", $(if_enabled_echo CONFIG_UNWINDER_ORC libelf-dev:native)" +extra_build_depends="$extra_build_depends, $(if_enabled_echo CONFIG_SYSTEM_TRUSTED_KEYRING libssl-dev:native)" + +# Generate a simple changelog template +cat <<EOF > debian/changelog +$sourcename ($packageversion) $distribution; urgency=low + + * Custom built Linux kernel. + + -- $maintainer $(date -R) +EOF + +# Generate copyright file +cat <<EOF > debian/copyright +This is a packacked upstream version of the Linux kernel. + +The sources may be found at most Linux archive sites, including: +https://www.kernel.org/pub/linux/kernel + +Copyright: 1991 - 2018 Linus Torvalds and others. + +The git repository for mainline kernel development is at: +git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; version 2 dated June, 1991. + +On Debian GNU/Linux systems, the complete text of the GNU General Public +License version 2 can be found in \`/usr/share/common-licenses/GPL-2'. +EOF + +# Generate a control file +cat <<EOF > debian/control +Source: $sourcename +Section: kernel +Priority: optional +Maintainer: $maintainer +Rules-Requires-Root: no +Build-Depends: bc, rsync, kmod, cpio, bison, flex | flex:native $extra_build_depends +Homepage: https://www.kernel.org/ + +Package: $packagename-$version +Architecture: $debarch +Description: Linux kernel, version $version + This package contains the Linux kernel, modules and corresponding other + files, version: $version. + +Package: linux-libc-dev +Section: devel +Provides: linux-kernel-headers +Architecture: $debarch +Description: Linux support headers for userspace development + This package provides userspaces headers from the Linux kernel. These headers + are used by the installed headers for GNU glibc and other system libraries. +Multi-Arch: same +EOF + +if is_enabled CONFIG_MODULES; then +cat <<EOF >> debian/control + +Package: linux-headers-$version +Architecture: $debarch +Description: Linux kernel headers for $version on $debarch + This package provides kernel header files for $version on $debarch + . + This is useful for people who need to build external modules +EOF +fi + +if is_enabled CONFIG_DEBUG_INFO; then +cat <<EOF >> debian/control + +Package: linux-image-$version-dbg +Section: debug +Architecture: $debarch +Description: Linux kernel debugging symbols for $version + This package will come in handy if you need to debug the kernel. It provides + all the necessary debug symbols for the kernel and its modules. +EOF +fi + +cat <<EOF > debian/rules +#!$(command -v $MAKE) -f + +srctree ?= . + +build-indep: +build-arch: + \$(MAKE) KERNELRELEASE=${version} ARCH=${ARCH} \ + KBUILD_BUILD_VERSION=${revision} -f \$(srctree)/Makefile + +build: build-arch + +binary-indep: +binary-arch: build-arch + \$(MAKE) KERNELRELEASE=${version} ARCH=${ARCH} \ + KBUILD_BUILD_VERSION=${revision} -f \$(srctree)/Makefile intdeb-pkg + +clean: + rm -rf debian/*tmp debian/files + \$(MAKE) clean + +binary: binary-arch +EOF +chmod +x debian/rules + +exit 0 diff --git a/src/net/scripts/package/mkspec b/src/net/scripts/package/mkspec new file mode 100755 index 0000000..7c477ca --- /dev/null +++ b/src/net/scripts/package/mkspec @@ -0,0 +1,147 @@ +#!/bin/sh +# +# Output a simple RPM spec file. +# This version assumes a minimum of RPM 4.0.3. +# +# The only gothic bit here is redefining install_post to avoid +# stripping the symbols from files in the kernel which we want +# +# Patched for non-x86 by Opencon (L) 2002 <opencon@rio.skydome.net> +# + +# how we were called determines which rpms we build and how we build them +if [ "$1" = prebuilt ]; then + S=DEL + MAKE="$MAKE -f $srctree/Makefile" +else + S= +fi + +if grep -q CONFIG_MODULES=y .config; then + M= +else + M=DEL +fi + +if grep -q CONFIG_DRM=y .config; then + PROVIDES=kernel-drm +fi + +PROVIDES="$PROVIDES kernel-$KERNELRELEASE" +__KERNELRELEASE=$(echo $KERNELRELEASE | sed -e "s/-/_/g") +EXCLUDES="$RCS_TAR_IGNORE --exclude=*vmlinux* --exclude=*.mod \ +--exclude=*.o --exclude=*.ko --exclude=*.cmd --exclude=Documentation \ +--exclude=.config.old --exclude=.missing-syscalls.d --exclude=*.s" + +# We can label the here-doc lines for conditional output to the spec file +# +# Labels: +# $S: this line is enabled only when building source package +# $M: this line is enabled only when CONFIG_MODULES is enabled +sed -e '/^DEL/d' -e 's/^\t*//' <<EOF + Name: kernel + Summary: The Linux Kernel + Version: $__KERNELRELEASE + Release: $(cat .version 2>/dev/null || echo 1) + License: GPL + Group: System Environment/Kernel + Vendor: The Linux Community + URL: https://www.kernel.org +$S Source: kernel-$__KERNELRELEASE.tar.gz + Provides: $PROVIDES + %define __spec_install_post /usr/lib/rpm/brp-compress || : + %define debug_package %{nil} + + %description + The Linux Kernel, the operating system core itself + + %package headers + Summary: Header files for the Linux kernel for use by glibc + Group: Development/System + Obsoletes: kernel-headers + Provides: kernel-headers = %{version} + %description headers + Kernel-headers includes the C header files that specify the interface + between the Linux kernel and userspace libraries and programs. The + header files define structures and constants that are needed for + building most standard programs and are also needed for rebuilding the + glibc package. + +$S$M %package devel +$S$M Summary: Development package for building kernel modules to match the $__KERNELRELEASE kernel +$S$M Group: System Environment/Kernel +$S$M AutoReqProv: no +$S$M %description -n kernel-devel +$S$M This package provides kernel headers and makefiles sufficient to build modules +$S$M against the $__KERNELRELEASE kernel package. +$S$M +$S %prep +$S %setup -q +$S +$S %build +$S $MAKE %{?_smp_mflags} KBUILD_BUILD_VERSION=%{release} +$S + %install + mkdir -p %{buildroot}/boot + %ifarch ia64 + mkdir -p %{buildroot}/boot/efi + cp \$($MAKE image_name) %{buildroot}/boot/efi/vmlinuz-$KERNELRELEASE + ln -s efi/vmlinuz-$KERNELRELEASE %{buildroot}/boot/ + %else + cp \$($MAKE image_name) %{buildroot}/boot/vmlinuz-$KERNELRELEASE + %endif +$M $MAKE %{?_smp_mflags} INSTALL_MOD_PATH=%{buildroot} modules_install + $MAKE %{?_smp_mflags} INSTALL_HDR_PATH=%{buildroot}/usr headers_install + cp System.map %{buildroot}/boot/System.map-$KERNELRELEASE + cp .config %{buildroot}/boot/config-$KERNELRELEASE + bzip2 -9 --keep vmlinux + mv vmlinux.bz2 %{buildroot}/boot/vmlinux-$KERNELRELEASE.bz2 +$S$M rm -f %{buildroot}/lib/modules/$KERNELRELEASE/build +$S$M rm -f %{buildroot}/lib/modules/$KERNELRELEASE/source +$S$M mkdir -p %{buildroot}/usr/src/kernels/$KERNELRELEASE +$S$M tar cf - $EXCLUDES . | tar xf - -C %{buildroot}/usr/src/kernels/$KERNELRELEASE +$S$M cd %{buildroot}/lib/modules/$KERNELRELEASE +$S$M ln -sf /usr/src/kernels/$KERNELRELEASE build +$S$M ln -sf /usr/src/kernels/$KERNELRELEASE source + + %clean + rm -rf %{buildroot} + + %post + if [ -x /sbin/installkernel -a -r /boot/vmlinuz-$KERNELRELEASE -a -r /boot/System.map-$KERNELRELEASE ]; then + cp /boot/vmlinuz-$KERNELRELEASE /boot/.vmlinuz-$KERNELRELEASE-rpm + cp /boot/System.map-$KERNELRELEASE /boot/.System.map-$KERNELRELEASE-rpm + rm -f /boot/vmlinuz-$KERNELRELEASE /boot/System.map-$KERNELRELEASE + /sbin/installkernel $KERNELRELEASE /boot/.vmlinuz-$KERNELRELEASE-rpm /boot/.System.map-$KERNELRELEASE-rpm + rm -f /boot/.vmlinuz-$KERNELRELEASE-rpm /boot/.System.map-$KERNELRELEASE-rpm + fi + + %preun + if [ -x /sbin/new-kernel-pkg ]; then + new-kernel-pkg --remove $KERNELRELEASE --rminitrd --initrdfile=/boot/initramfs-$KERNELRELEASE.img + elif [ -x /usr/bin/kernel-install ]; then + kernel-install remove $KERNELRELEASE + fi + + %postun + if [ -x /sbin/update-bootloader ]; then + /sbin/update-bootloader --remove $KERNELRELEASE + fi + + %files + %defattr (-, root, root) +$M /lib/modules/$KERNELRELEASE +$M %exclude /lib/modules/$KERNELRELEASE/build +$M %exclude /lib/modules/$KERNELRELEASE/source + /boot/* + + %files headers + %defattr (-, root, root) + /usr/include +$S$M +$S$M %files devel +$S$M %defattr (-, root, root) +$S$M /usr/src/kernels/$KERNELRELEASE +$S$M /lib/modules/$KERNELRELEASE/build +$S$M /lib/modules/$KERNELRELEASE/source +EOF diff --git a/src/net/scripts/package/snapcraft.template b/src/net/scripts/package/snapcraft.template new file mode 100644 index 0000000..626d278 --- /dev/null +++ b/src/net/scripts/package/snapcraft.template @@ -0,0 +1,14 @@ +name: kernel +version: KERNELRELEASE +summary: Linux kernel +description: The upstream Linux kernel +grade: stable +confinement: strict +type: kernel + +parts: + kernel: + plugin: kernel + source: SRCTREE + source-type: tar + kernel-with-firmware: false diff --git a/src/net/scripts/pahole-flags.sh b/src/net/scripts/pahole-flags.sh new file mode 100755 index 0000000..8c82173 --- /dev/null +++ b/src/net/scripts/pahole-flags.sh @@ -0,0 +1,21 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0 + +extra_paholeopt= + +if ! [ -x "$(command -v ${PAHOLE})" ]; then + exit 0 +fi + +pahole_ver=$(${PAHOLE} --version | sed -E 's/v([0-9]+)\.([0-9]+)/\1\2/') + +if [ "${pahole_ver}" -ge "118" ] && [ "${pahole_ver}" -le "121" ]; then + # pahole 1.18 through 1.21 can't handle zero-sized per-CPU vars + extra_paholeopt="${extra_paholeopt} --skip_encoding_btf_vars" +fi + +if [ "${pahole_ver}" -ge "124" ]; then + extra_paholeopt="${extra_paholeopt} --skip_encoding_btf_enum64" +fi + +echo ${extra_paholeopt} diff --git a/src/net/scripts/parse-maintainers.pl b/src/net/scripts/parse-maintainers.pl new file mode 100755 index 0000000..2ca4eb3 --- /dev/null +++ b/src/net/scripts/parse-maintainers.pl @@ -0,0 +1,194 @@ +#!/usr/bin/perl -w +# SPDX-License-Identifier: GPL-2.0 + +use strict; +use Getopt::Long qw(:config no_auto_abbrev); + +my $input_file = "MAINTAINERS"; +my $output_file = "MAINTAINERS.new"; +my $output_section = "SECTION.new"; +my $help = 0; +my $order = 0; +my $P = $0; + +if (!GetOptions( + 'input=s' => \$input_file, + 'output=s' => \$output_file, + 'section=s' => \$output_section, + 'order!' => \$order, + 'h|help|usage' => \$help, + )) { + die "$P: invalid argument - use --help if necessary\n"; +} + +if ($help != 0) { + usage(); + exit 0; +} + +sub usage { + print <<EOT; +usage: $P [options] <pattern matching regexes> + + --input => MAINTAINERS file to read (default: MAINTAINERS) + --output => sorted MAINTAINERS file to write (default: MAINTAINERS.new) + --section => new sorted MAINTAINERS file to write to (default: SECTION.new) + --order => Use the preferred section content output ordering (default: 0) + Preferred ordering of section output is: + M: Person acting as a maintainer + R: Person acting as a patch reviewer + L: Mailing list where patches should be sent + S: Maintenance status + W: URI for general information + Q: URI for patchwork tracking + B: URI for bug tracking/submission + C: URI for chat + P: URI or file for subsystem specific coding styles + T: SCM tree type and location + F: File and directory pattern + X: File and directory exclusion pattern + N: File glob + K: Keyword - patch content regex + +If <pattern match regexes> exist, then the sections that match the +regexes are not written to the output file but are written to the +section file. + +EOT +} + +# sort comparison functions +sub by_category($$) { + my ($a, $b) = @_; + + $a = uc $a; + $b = uc $b; + + # This always sorts last + $a =~ s/THE REST/ZZZZZZ/g; + $b =~ s/THE REST/ZZZZZZ/g; + + return $a cmp $b; +} + +sub by_pattern($$) { + my ($a, $b) = @_; + my $preferred_order = 'MRLSWQBCPTFXNK'; + + my $a1 = uc(substr($a, 0, 1)); + my $b1 = uc(substr($b, 0, 1)); + + my $a_index = index($preferred_order, $a1); + my $b_index = index($preferred_order, $b1); + + $a_index = 1000 if ($a_index == -1); + $b_index = 1000 if ($b_index == -1); + + if (($a1 =~ /^F$/ && $b1 =~ /^F$/) || + ($a1 =~ /^X$/ && $b1 =~ /^X$/)) { + return $a cmp $b; + } + + if ($a_index < $b_index) { + return -1; + } elsif ($a_index == $b_index) { + return 0; + } else { + return 1; + } +} + +sub trim { + my $s = shift; + $s =~ s/\s+$//; + $s =~ s/^\s+//; + return $s; +} + +sub alpha_output { + my ($hashref, $filename) = (@_); + + return if ! scalar(keys %$hashref); + + open(my $file, '>', "$filename") or die "$P: $filename: open failed - $!\n"; + my $separator; + foreach my $key (sort by_category keys %$hashref) { + if ($key eq " ") { + print $file $$hashref{$key}; + } else { + if (! defined $separator) { + $separator = "\n"; + } else { + print $file $separator; + } + print $file $key . "\n"; + if ($order) { + foreach my $pattern (sort by_pattern split('\n', %$hashref{$key})) { + print $file ($pattern . "\n"); + } + } else { + foreach my $pattern (split('\n', %$hashref{$key})) { + print $file ($pattern . "\n"); + } + } + } + } + close($file); +} + +sub file_input { + my ($hashref, $filename) = (@_); + + my $lastline = ""; + my $case = " "; + $$hashref{$case} = ""; + + open(my $file, '<', "$filename") or die "$P: $filename: open failed - $!\n"; + + while (<$file>) { + my $line = $_; + + # Pattern line? + if ($line =~ m/^([A-Z]):\s*(.*)/) { + $line = $1 . ":\t" . trim($2) . "\n"; + if ($lastline eq "") { + $$hashref{$case} = $$hashref{$case} . $line; + next; + } + $case = trim($lastline); + exists $$hashref{$case} and die "Header '$case' already exists"; + $$hashref{$case} = $line; + $lastline = ""; + next; + } + + if ($case eq " ") { + $$hashref{$case} = $$hashref{$case} . $lastline; + $lastline = $line; + next; + } + trim($lastline) eq "" or die ("Odd non-pattern line '$lastline' for '$case'"); + $lastline = $line; + } + $$hashref{$case} = $$hashref{$case} . $lastline; + close($file); +} + +my %hash; +my %new_hash; + +file_input(\%hash, $input_file); + +foreach my $type (@ARGV) { + foreach my $key (keys %hash) { + if ($key =~ /$type/ || $hash{$key} =~ /$type/) { + $new_hash{$key} = $hash{$key}; + delete $hash{$key}; + } + } +} + +alpha_output(\%hash, $output_file); +alpha_output(\%new_hash, $output_section); + +exit(0); diff --git a/src/net/scripts/patch-kernel b/src/net/scripts/patch-kernel new file mode 100755 index 0000000..033d591 --- /dev/null +++ b/src/net/scripts/patch-kernel @@ -0,0 +1,332 @@ +#! /bin/sh +# SPDX-License-Identifier: GPL-2.0 +# Script to apply kernel patches. +# usage: patch-kernel [ sourcedir [ patchdir [ stopversion ] [ -acxx ] ] ] +# The source directory defaults to /usr/src/linux, and the patch +# directory defaults to the current directory. +# e.g. +# scripts/patch-kernel . .. +# Update the kernel tree in the current directory using patches in the +# directory above to the latest Linus kernel +# scripts/patch-kernel . .. -ac +# Get the latest Linux kernel and patch it with the latest ac patch +# scripts/patch-kernel . .. 2.4.9 +# Gets standard kernel 2.4.9 +# scripts/patch-kernel . .. 2.4.9 -ac +# Gets 2.4.9 with latest ac patches +# scripts/patch-kernel . .. 2.4.9 -ac11 +# Gets 2.4.9 with ac patch ac11 +# Note: It uses the patches relative to the Linus kernels, not the +# ac to ac relative patches +# +# It determines the current kernel version from the top-level Makefile. +# It then looks for patches for the next sublevel in the patch directory. +# This is applied using "patch -p1 -s" from within the kernel directory. +# A check is then made for "*.rej" files to see if the patch was +# successful. If it is, then all of the "*.orig" files are removed. +# +# Nick Holloway <Nick.Holloway@alfie.demon.co.uk>, 2nd January 1995. +# +# Added support for handling multiple types of compression. What includes +# gzip, bzip, bzip2, zip, compress, and plaintext. +# +# Adam Sulmicki <adam@cfar.umd.edu>, 1st January 1997. +# +# Added ability to stop at a given version number +# Put the full version number (i.e. 2.3.31) as the last parameter +# Dave Gilbert <linux@treblig.org>, 11th December 1999. + +# Fixed previous patch so that if we are already at the correct version +# not to patch up. +# +# Added -ac option, use -ac or -ac9 (say) to stop at a particular version +# Dave Gilbert <linux@treblig.org>, 29th September 2001. +# +# Add support for (use of) EXTRAVERSION (to support 2.6.8.x, e.g.); +# update usage message; +# fix some whitespace damage; +# be smarter about stopping when current version is larger than requested; +# Randy Dunlap <rdunlap@xenotime.net>, 2004-AUG-18. +# +# Add better support for (non-incremental) 2.6.x.y patches; +# If an ending version number if not specified, the script automatically +# increments the SUBLEVEL (x in 2.6.x.y) until no more patch files are found; +# however, EXTRAVERSION (y in 2.6.x.y) is never automatically incremented +# but must be specified fully. +# +# patch-kernel does not normally support reverse patching, but does so when +# applying EXTRAVERSION (x.y) patches, so that moving from 2.6.11.y to 2.6.11.z +# is easy and handled by the script (reverse 2.6.11.y and apply 2.6.11.z). +# Randy Dunlap <rdunlap@xenotime.net>, 2005-APR-08. + +PNAME=patch-kernel + +# Set directories from arguments, or use defaults. +sourcedir=${1-/usr/src/linux} +patchdir=${2-.} +stopvers=${3-default} + +if [ "$1" = -h -o "$1" = --help -o ! -r "$sourcedir/Makefile" ]; then +cat << USAGE +usage: $PNAME [-h] [ sourcedir [ patchdir [ stopversion ] [ -acxx ] ] ] + source directory defaults to /usr/src/linux, + patch directory defaults to the current directory, + stopversion defaults to <all in patchdir>. +USAGE +exit 1 +fi + +# See if we have any -ac options +for PARM in $* +do + case $PARM in + -ac*) + gotac=$PARM; + + esac; +done + +# --------------------------------------------------------------------------- +# arg1 is filename +noFile () { + echo "cannot find patch file: ${patch}" + exit 1 +} + +# --------------------------------------------------------------------------- +backwards () { + echo "$PNAME does not support reverse patching" + exit 1 +} + +# --------------------------------------------------------------------------- +# Find a file, first parameter is basename of file +# it tries many compression mechanisms and sets variables to say how to get it +findFile () { + filebase=$1; + + if [ -r ${filebase}.gz ]; then + ext=".gz" + name="gzip" + uncomp="gunzip -dc" + elif [ -r ${filebase}.bz ]; then + ext=".bz" + name="bzip" + uncomp="bunzip -dc" + elif [ -r ${filebase}.bz2 ]; then + ext=".bz2" + name="bzip2" + uncomp="bunzip2 -dc" + elif [ -r ${filebase}.xz ]; then + ext=".xz" + name="xz" + uncomp="xz -dc" + elif [ -r ${filebase}.zip ]; then + ext=".zip" + name="zip" + uncomp="unzip -d" + elif [ -r ${filebase}.Z ]; then + ext=".Z" + name="uncompress" + uncomp="uncompress -c" + elif [ -r ${filebase} ]; then + ext="" + name="plaintext" + uncomp="cat" + else + return 1; + fi + + return 0; +} + +# --------------------------------------------------------------------------- +# Apply a patch and check it goes in cleanly +# First param is patch name (e.g. patch-2.4.9-ac5) - without path or extension + +applyPatch () { + echo -n "Applying $1 (${name})... " + if $uncomp ${patchdir}/$1${ext} | patch -p1 -s -N -E -d $sourcedir + then + echo "done." + else + echo "failed. Clean up yourself." + return 1; + fi + if [ "`find $sourcedir/ '(' -name '*.rej' -o -name '.*.rej' ')' -print`" ] + then + echo "Aborting. Reject files found." + return 1; + fi + # Remove backup files + find $sourcedir/ '(' -name '*.orig' -o -name '.*.orig' ')' -exec rm -f {} \; + + return 0; +} + +# --------------------------------------------------------------------------- +# arg1 is patch filename +reversePatch () { + echo -n "Reversing $1 (${name}) ... " + if $uncomp ${patchdir}/"$1"${ext} | patch -p1 -Rs -N -E -d $sourcedir + then + echo "done." + else + echo "failed. Clean it up." + exit 1 + fi + if [ "`find $sourcedir/ '(' -name '*.rej' -o -name '.*.rej' ')' -print`" ] + then + echo "Aborting. Reject files found." + return 1 + fi + # Remove backup files + find $sourcedir/ '(' -name '*.orig' -o -name '.*.orig' ')' -exec rm -f {} \; + + return 0 +} + +# set current VERSION, PATCHLEVEL, SUBLEVEL, EXTRAVERSION +# force $TMPFILEs below to be in local directory: a slash character prevents +# the dot command from using the search path. +TMPFILE=`mktemp ./.tmpver.XXXXXX` || { echo "cannot make temp file" ; exit 1; } +grep -E "^(VERSION|PATCHLEVEL|SUBLEVEL|EXTRAVERSION)" $sourcedir/Makefile > $TMPFILE +tr -d [:blank:] < $TMPFILE > $TMPFILE.1 +. $TMPFILE.1 +rm -f $TMPFILE* +if [ -z "$VERSION" -o -z "$PATCHLEVEL" -o -z "$SUBLEVEL" ] +then + echo "unable to determine current kernel version" >&2 + exit 1 +fi + +NAME=`grep ^NAME $sourcedir/Makefile` +NAME=${NAME##*=} + +echo "Current kernel version is $VERSION.$PATCHLEVEL.$SUBLEVEL${EXTRAVERSION} ($NAME)" + +# strip EXTRAVERSION to just a number (drop leading '.' and trailing additions) +EXTRAVER= +if [ x$EXTRAVERSION != "x" ] +then + EXTRAVER=${EXTRAVERSION#.} + EXTRAVER=${EXTRAVER%%[[:punct:]]*} + #echo "$PNAME: changing EXTRAVERSION from $EXTRAVERSION to $EXTRAVER" +fi + +#echo "stopvers=$stopvers" +if [ $stopvers != "default" ]; then + STOPSUBLEVEL=`echo $stopvers | cut -d. -f3` + STOPEXTRA=`echo $stopvers | cut -d. -f4` + STOPFULLVERSION=${stopvers%%.$STOPEXTRA} + #echo "#___STOPSUBLEVEL=/$STOPSUBLEVEL/, STOPEXTRA=/$STOPEXTRA/" +else + STOPSUBLEVEL=9999 + STOPEXTRA=9999 +fi + +# This all assumes a 2.6.x[.y] kernel tree. +# Don't allow backwards/reverse patching. +if [ $STOPSUBLEVEL -lt $SUBLEVEL ]; then + backwards +fi + +if [ x$EXTRAVER != "x" ]; then + CURRENTFULLVERSION="$VERSION.$PATCHLEVEL.$SUBLEVEL.$EXTRAVER" +else + CURRENTFULLVERSION="$VERSION.$PATCHLEVEL.$SUBLEVEL" +fi + +if [ x$EXTRAVER != "x" ]; then + echo "backing up to: $VERSION.$PATCHLEVEL.$SUBLEVEL" + patch="patch-${CURRENTFULLVERSION}" + findFile $patchdir/${patch} || noFile ${patch} + reversePatch ${patch} || exit 1 +fi + +# now current is 2.6.x, with no EXTRA applied, +# so update to target SUBLEVEL (2.6.SUBLEVEL) +# and then to target EXTRAVER (2.6.SUB.EXTRAVER) if requested. +# If not ending sublevel is specified, it is incremented until +# no further sublevels are found. + +if [ $STOPSUBLEVEL -gt $SUBLEVEL ]; then +while : # incrementing SUBLEVEL (s in v.p.s) +do + CURRENTFULLVERSION="$VERSION.$PATCHLEVEL.$SUBLEVEL" + EXTRAVER= + if [ x$STOPFULLVERSION = x$CURRENTFULLVERSION ]; then + echo "Stopping at $CURRENTFULLVERSION base as requested." + break + fi + + SUBLEVEL=$(($SUBLEVEL + 1)) + FULLVERSION="$VERSION.$PATCHLEVEL.$SUBLEVEL" + #echo "#___ trying $FULLVERSION ___" + + if [ $(($SUBLEVEL)) -gt $(($STOPSUBLEVEL)) ]; then + echo "Stopping since sublevel ($SUBLEVEL) is beyond stop-sublevel ($STOPSUBLEVEL)" + exit 1 + fi + + patch=patch-$FULLVERSION + # See if the file exists and find extension + findFile $patchdir/${patch} || noFile ${patch} + + # Apply the patch and check all is OK + applyPatch $patch || break +done +#echo "#___sublevel all done" +fi + +# There is no incremental searching for extraversion... +if [ "$STOPEXTRA" != "" ]; then +while : # just to allow break +do +# apply STOPEXTRA directly (not incrementally) (x in v.p.s.x) + FULLVERSION="$VERSION.$PATCHLEVEL.$SUBLEVEL.$STOPEXTRA" + #echo "#... trying $FULLVERSION ..." + patch=patch-$FULLVERSION + + # See if the file exists and find extension + findFile $patchdir/${patch} || noFile ${patch} + + # Apply the patch and check all is OK + applyPatch $patch || break + #echo "#___extraver all done" + break +done +fi + +if [ x$gotac != x ]; then + # Out great user wants the -ac patches + # They could have done -ac (get latest) or -acxx where xx=version they want + if [ $gotac = "-ac" ]; then + # They want the latest version + HIGHESTPATCH=0 + for PATCHNAMES in $patchdir/patch-${CURRENTFULLVERSION}-ac*\.* + do + ACVALUE=`echo $PATCHNAMES | sed -e 's/^.*patch-[0-9.]*-ac\([0-9]*\).*/\1/'` + # Check it is actually a recognised patch type + findFile $patchdir/patch-${CURRENTFULLVERSION}-ac${ACVALUE} || break + + if [ $ACVALUE -gt $HIGHESTPATCH ]; then + HIGHESTPATCH=$ACVALUE + fi + done + + if [ $HIGHESTPATCH -ne 0 ]; then + findFile $patchdir/patch-${CURRENTFULLVERSION}-ac${HIGHESTPATCH} || break + applyPatch patch-${CURRENTFULLVERSION}-ac${HIGHESTPATCH} + else + echo "No -ac patches found" + fi + else + # They want an exact version + findFile $patchdir/patch-${CURRENTFULLVERSION}${gotac} || { + echo "Sorry, I couldn't find the $gotac patch for $CURRENTFULLVERSION. Hohum." + exit 1 + } + applyPatch patch-${CURRENTFULLVERSION}${gotac} + fi +fi diff --git a/src/net/scripts/profile2linkerlist.pl b/src/net/scripts/profile2linkerlist.pl new file mode 100755 index 0000000..316e719 --- /dev/null +++ b/src/net/scripts/profile2linkerlist.pl @@ -0,0 +1,20 @@ +#!/usr/bin/env perl +# SPDX-License-Identifier: GPL-2.0 + +# +# Takes a (sorted) output of readprofile and turns it into a list suitable for +# linker scripts +# +# usage: +# readprofile | sort -rn | perl profile2linkerlist.pl > functionlist +# +use strict; + +while (<>) { + my $line = $_; + + $_ =~ /\W*[0-9]+\W*([a-zA-Z\_0-9]+)\W*[0-9]+/; + + print "*(.text.$1)\n" + unless ($line =~ /unknown/) || ($line =~ /total/); +} diff --git a/src/net/scripts/prune-kernel b/src/net/scripts/prune-kernel new file mode 100755 index 0000000..e8aa940 --- /dev/null +++ b/src/net/scripts/prune-kernel @@ -0,0 +1,21 @@ +#!/bin/bash +# SPDX-License-Identifier: GPL-2.0 + +# because I use CONFIG_LOCALVERSION_AUTO, not the same version again and +# again, /boot and /lib/modules/ eventually fill up. +# Dumb script to purge that stuff: + +for f in "$@" +do + if rpm -qf "/lib/modules/$f" >/dev/null; then + echo "keeping $f (installed from rpm)" + elif [ $(uname -r) = "$f" ]; then + echo "keeping $f (running kernel) " + else + echo "removing $f" + rm -f "/boot/initramfs-$f.img" "/boot/System.map-$f" + rm -f "/boot/vmlinuz-$f" "/boot/config-$f" + rm -rf "/lib/modules/$f" + new-kernel-pkg --remove $f + fi +done diff --git a/src/net/scripts/recordmcount.c b/src/net/scripts/recordmcount.c new file mode 100644 index 0000000..f7cf4fd --- /dev/null +++ b/src/net/scripts/recordmcount.c @@ -0,0 +1,710 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * recordmcount.c: construct a table of the locations of calls to 'mcount' + * so that ftrace can find them quickly. + * Copyright 2009 John F. Reiser <jreiser@BitWagon.com>. All rights reserved. + * + * Restructured to fit Linux format, as well as other updates: + * Copyright 2010 Steven Rostedt <srostedt@redhat.com>, Red Hat Inc. + */ + +/* + * Strategy: alter the .o file in-place. + * + * Append a new STRTAB that has the new section names, followed by a new array + * ElfXX_Shdr[] that has the new section headers, followed by the section + * contents for __mcount_loc and its relocations. The old shstrtab strings, + * and the old ElfXX_Shdr[] array, remain as "garbage" (commonly, a couple + * kilobytes.) Subsequent processing by /bin/ld (or the kernel module loader) + * will ignore the garbage regions, because they are not designated by the + * new .e_shoff nor the new ElfXX_Shdr[]. [In order to remove the garbage, + * then use "ld -r" to create a new file that omits the garbage.] + */ + +#include <sys/types.h> +#include <sys/mman.h> +#include <sys/stat.h> +#include <getopt.h> +#include <elf.h> +#include <fcntl.h> +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <unistd.h> + +#ifndef EM_AARCH64 +#define EM_AARCH64 183 +#define R_AARCH64_NONE 0 +#define R_AARCH64_ABS64 257 +#endif + +#ifndef EM_SW64 +#define EM_SW64 0x9916 +#define R_SW64_NONE 0 +#define R_SW64_REFQUAD 2 /* Direct 64 bit */ +#endif + +#define R_ARM_PC24 1 +#define R_ARM_THM_CALL 10 +#define R_ARM_CALL 28 + +#define R_AARCH64_CALL26 283 + +static int fd_map; /* File descriptor for file being modified. */ +static int mmap_failed; /* Boolean flag. */ +static char gpfx; /* prefix for global symbol name (sometimes '_') */ +static struct stat sb; /* Remember .st_size, etc. */ +static const char *altmcount; /* alternate mcount symbol name */ +static int warn_on_notrace_sect; /* warn when section has mcount not being recorded */ +static void *file_map; /* pointer of the mapped file */ +static void *file_end; /* pointer to the end of the mapped file */ +static int file_updated; /* flag to state file was changed */ +static void *file_ptr; /* current file pointer location */ + +static void *file_append; /* added to the end of the file */ +static size_t file_append_size; /* how much is added to end of file */ + +/* Per-file resource cleanup when multiple files. */ +static void file_append_cleanup(void) +{ + free(file_append); + file_append = NULL; + file_append_size = 0; + file_updated = 0; +} + +static void mmap_cleanup(void) +{ + if (!mmap_failed) + munmap(file_map, sb.st_size); + else + free(file_map); + file_map = NULL; +} + +/* ulseek, uwrite, ...: Check return value for errors. */ + +static off_t ulseek(off_t const offset, int const whence) +{ + switch (whence) { + case SEEK_SET: + file_ptr = file_map + offset; + break; + case SEEK_CUR: + file_ptr += offset; + break; + case SEEK_END: + file_ptr = file_map + (sb.st_size - offset); + break; + } + if (file_ptr < file_map) { + fprintf(stderr, "lseek: seek before file\n"); + return -1; + } + return file_ptr - file_map; +} + +static ssize_t uwrite(void const *const buf, size_t const count) +{ + size_t cnt = count; + off_t idx = 0; + + file_updated = 1; + + if (file_ptr + count >= file_end) { + off_t aoffset = (file_ptr + count) - file_end; + + if (aoffset > file_append_size) { + file_append = realloc(file_append, aoffset); + file_append_size = aoffset; + } + if (!file_append) { + perror("write"); + file_append_cleanup(); + mmap_cleanup(); + return -1; + } + if (file_ptr < file_end) { + cnt = file_end - file_ptr; + } else { + cnt = 0; + idx = aoffset - count; + } + } + + if (cnt) + memcpy(file_ptr, buf, cnt); + + if (cnt < count) + memcpy(file_append + idx, buf + cnt, count - cnt); + + file_ptr += count; + return count; +} + +static void * umalloc(size_t size) +{ + void *const addr = malloc(size); + if (addr == 0) { + fprintf(stderr, "malloc failed: %zu bytes\n", size); + file_append_cleanup(); + mmap_cleanup(); + return NULL; + } + return addr; +} + +/* + * Get the whole file as a programming convenience in order to avoid + * malloc+lseek+read+free of many pieces. If successful, then mmap + * avoids copying unused pieces; else just read the whole file. + * Open for both read and write; new info will be appended to the file. + * Use MAP_PRIVATE so that a few changes to the in-memory ElfXX_Ehdr + * do not propagate to the file until an explicit overwrite at the last. + * This preserves most aspects of consistency (all except .st_size) + * for simultaneous readers of the file while we are appending to it. + * However, multiple writers still are bad. We choose not to use + * locking because it is expensive and the use case of kernel build + * makes multiple writers unlikely. + */ +static void *mmap_file(char const *fname) +{ + /* Avoid problems if early cleanup() */ + fd_map = -1; + mmap_failed = 1; + file_map = NULL; + file_ptr = NULL; + file_updated = 0; + sb.st_size = 0; + + fd_map = open(fname, O_RDONLY); + if (fd_map < 0) { + perror(fname); + return NULL; + } + if (fstat(fd_map, &sb) < 0) { + perror(fname); + goto out; + } + if (!S_ISREG(sb.st_mode)) { + fprintf(stderr, "not a regular file: %s\n", fname); + goto out; + } + file_map = mmap(0, sb.st_size, PROT_READ|PROT_WRITE, MAP_PRIVATE, + fd_map, 0); + if (file_map == MAP_FAILED) { + mmap_failed = 1; + file_map = umalloc(sb.st_size); + if (!file_map) { + perror(fname); + goto out; + } + if (read(fd_map, file_map, sb.st_size) != sb.st_size) { + perror(fname); + free(file_map); + file_map = NULL; + goto out; + } + } else + mmap_failed = 0; +out: + close(fd_map); + fd_map = -1; + + file_end = file_map + sb.st_size; + + return file_map; +} + + +static unsigned char ideal_nop5_x86_64[5] = { 0x0f, 0x1f, 0x44, 0x00, 0x00 }; +static unsigned char ideal_nop5_x86_32[5] = { 0x3e, 0x8d, 0x74, 0x26, 0x00 }; +static unsigned char *ideal_nop; + +static char rel_type_nop; + +static int (*make_nop)(void *map, size_t const offset); + +static int make_nop_x86(void *map, size_t const offset) +{ + uint32_t *ptr; + unsigned char *op; + + /* Confirm we have 0xe8 0x0 0x0 0x0 0x0 */ + ptr = map + offset; + if (*ptr != 0) + return -1; + + op = map + offset - 1; + if (*op != 0xe8) + return -1; + + /* convert to nop */ + if (ulseek(offset - 1, SEEK_SET) < 0) + return -1; + if (uwrite(ideal_nop, 5) < 0) + return -1; + return 0; +} + +static unsigned char ideal_nop4_arm_le[4] = { 0x00, 0x00, 0xa0, 0xe1 }; /* mov r0, r0 */ +static unsigned char ideal_nop4_arm_be[4] = { 0xe1, 0xa0, 0x00, 0x00 }; /* mov r0, r0 */ +static unsigned char *ideal_nop4_arm; + +static unsigned char bl_mcount_arm_le[4] = { 0xfe, 0xff, 0xff, 0xeb }; /* bl */ +static unsigned char bl_mcount_arm_be[4] = { 0xeb, 0xff, 0xff, 0xfe }; /* bl */ +static unsigned char *bl_mcount_arm; + +static unsigned char push_arm_le[4] = { 0x04, 0xe0, 0x2d, 0xe5 }; /* push {lr} */ +static unsigned char push_arm_be[4] = { 0xe5, 0x2d, 0xe0, 0x04 }; /* push {lr} */ +static unsigned char *push_arm; + +static unsigned char ideal_nop2_thumb_le[2] = { 0x00, 0xbf }; /* nop */ +static unsigned char ideal_nop2_thumb_be[2] = { 0xbf, 0x00 }; /* nop */ +static unsigned char *ideal_nop2_thumb; + +static unsigned char push_bl_mcount_thumb_le[6] = { 0x00, 0xb5, 0xff, 0xf7, 0xfe, 0xff }; /* push {lr}, bl */ +static unsigned char push_bl_mcount_thumb_be[6] = { 0xb5, 0x00, 0xf7, 0xff, 0xff, 0xfe }; /* push {lr}, bl */ +static unsigned char *push_bl_mcount_thumb; + +static int make_nop_arm(void *map, size_t const offset) +{ + char *ptr; + int cnt = 1; + int nop_size; + size_t off = offset; + + ptr = map + offset; + if (memcmp(ptr, bl_mcount_arm, 4) == 0) { + if (memcmp(ptr - 4, push_arm, 4) == 0) { + off -= 4; + cnt = 2; + } + ideal_nop = ideal_nop4_arm; + nop_size = 4; + } else if (memcmp(ptr - 2, push_bl_mcount_thumb, 6) == 0) { + cnt = 3; + nop_size = 2; + off -= 2; + ideal_nop = ideal_nop2_thumb; + } else + return -1; + + /* Convert to nop */ + if (ulseek(off, SEEK_SET) < 0) + return -1; + + do { + if (uwrite(ideal_nop, nop_size) < 0) + return -1; + } while (--cnt > 0); + + return 0; +} + +static unsigned char ideal_nop4_arm64[4] = {0x1f, 0x20, 0x03, 0xd5}; +static int make_nop_arm64(void *map, size_t const offset) +{ + uint32_t *ptr; + + ptr = map + offset; + /* bl <_mcount> is 0x94000000 before relocation */ + if (*ptr != 0x94000000) + return -1; + + /* Convert to nop */ + if (ulseek(offset, SEEK_SET) < 0) + return -1; + if (uwrite(ideal_nop, 4) < 0) + return -1; + return 0; +} + +static unsigned char ideal_nop4_sw64[4] = {0x5f, 0x07, 0xff, 0x43}; + +static int make_nop_sw64(void *map, size_t const offset) +{ + /* Convert to nop */ + ulseek(offset, SEEK_SET); + uwrite(ideal_nop, 4); + return 0; +} + +static int write_file(const char *fname) +{ + char tmp_file[strlen(fname) + 4]; + size_t n; + + if (!file_updated) + return 0; + + sprintf(tmp_file, "%s.rc", fname); + + /* + * After reading the entire file into memory, delete it + * and write it back, to prevent weird side effects of modifying + * an object file in place. + */ + fd_map = open(tmp_file, O_WRONLY | O_TRUNC | O_CREAT, sb.st_mode); + if (fd_map < 0) { + perror(fname); + return -1; + } + n = write(fd_map, file_map, sb.st_size); + if (n != sb.st_size) { + perror("write"); + close(fd_map); + return -1; + } + if (file_append_size) { + n = write(fd_map, file_append, file_append_size); + if (n != file_append_size) { + perror("write"); + close(fd_map); + return -1; + } + } + close(fd_map); + if (rename(tmp_file, fname) < 0) { + perror(fname); + return -1; + } + return 0; +} + +/* w8rev, w8nat, ...: Handle endianness. */ + +static uint64_t w8rev(uint64_t const x) +{ + return ((0xff & (x >> (0 * 8))) << (7 * 8)) + | ((0xff & (x >> (1 * 8))) << (6 * 8)) + | ((0xff & (x >> (2 * 8))) << (5 * 8)) + | ((0xff & (x >> (3 * 8))) << (4 * 8)) + | ((0xff & (x >> (4 * 8))) << (3 * 8)) + | ((0xff & (x >> (5 * 8))) << (2 * 8)) + | ((0xff & (x >> (6 * 8))) << (1 * 8)) + | ((0xff & (x >> (7 * 8))) << (0 * 8)); +} + +static uint32_t w4rev(uint32_t const x) +{ + return ((0xff & (x >> (0 * 8))) << (3 * 8)) + | ((0xff & (x >> (1 * 8))) << (2 * 8)) + | ((0xff & (x >> (2 * 8))) << (1 * 8)) + | ((0xff & (x >> (3 * 8))) << (0 * 8)); +} + +static uint32_t w2rev(uint16_t const x) +{ + return ((0xff & (x >> (0 * 8))) << (1 * 8)) + | ((0xff & (x >> (1 * 8))) << (0 * 8)); +} + +static uint64_t w8nat(uint64_t const x) +{ + return x; +} + +static uint32_t w4nat(uint32_t const x) +{ + return x; +} + +static uint32_t w2nat(uint16_t const x) +{ + return x; +} + +static uint64_t (*w8)(uint64_t); +static uint32_t (*w)(uint32_t); +static uint32_t (*w2)(uint16_t); + +/* Names of the sections that could contain calls to mcount. */ +static int is_mcounted_section_name(char const *const txtname) +{ + return strncmp(".text", txtname, 5) == 0 || + strcmp(".init.text", txtname) == 0 || + strcmp(".ref.text", txtname) == 0 || + strcmp(".sched.text", txtname) == 0 || + strcmp(".spinlock.text", txtname) == 0 || + strcmp(".irqentry.text", txtname) == 0 || + strcmp(".softirqentry.text", txtname) == 0 || + strcmp(".kprobes.text", txtname) == 0 || + strcmp(".cpuidle.text", txtname) == 0; +} + +static char const *already_has_rel_mcount = "success"; /* our work here is done! */ + +/* 32 bit and 64 bit are very similar */ +#include "recordmcount.h" +#define RECORD_MCOUNT_64 +#include "recordmcount.h" + +static int arm_is_fake_mcount(Elf32_Rel const *rp) +{ + switch (ELF32_R_TYPE(w(rp->r_info))) { + case R_ARM_THM_CALL: + case R_ARM_CALL: + case R_ARM_PC24: + return 0; + } + + return 1; +} + +static int arm64_is_fake_mcount(Elf64_Rel const *rp) +{ + return ELF64_R_TYPE(w8(rp->r_info)) != R_AARCH64_CALL26; +} + +#define SW64_FAKEMCOUNT_OFFSET 4 + +static int sw64_is_fake_mcount(Elf64_Rel const *rp) +{ + static Elf64_Addr old_r_offset = ~(Elf64_Addr)0; + Elf64_Addr current_r_offset = _w(rp->r_offset); + int is_fake; + + is_fake = (old_r_offset != ~(Elf64_Addr)0) && + (current_r_offset - old_r_offset == SW64_FAKEMCOUNT_OFFSET); + old_r_offset = current_r_offset; + + return is_fake; +} + +/* 64-bit EM_MIPS has weird ELF64_Rela.r_info. + * http://techpubs.sgi.com/library/manuals/4000/007-4658-001/pdf/007-4658-001.pdf + * We interpret Table 29 Relocation Operation (Elf64_Rel, Elf64_Rela) [p.40] + * to imply the order of the members; the spec does not say so. + * typedef unsigned char Elf64_Byte; + * fails on MIPS64 because their <elf.h> already has it! + */ + +typedef uint8_t myElf64_Byte; /* Type for a 8-bit quantity. */ + +union mips_r_info { + Elf64_Xword r_info; + struct { + Elf64_Word r_sym; /* Symbol index. */ + myElf64_Byte r_ssym; /* Special symbol. */ + myElf64_Byte r_type3; /* Third relocation. */ + myElf64_Byte r_type2; /* Second relocation. */ + myElf64_Byte r_type; /* First relocation. */ + } r_mips; +}; + +static uint64_t MIPS64_r_sym(Elf64_Rel const *rp) +{ + return w(((union mips_r_info){ .r_info = rp->r_info }).r_mips.r_sym); +} + +static void MIPS64_r_info(Elf64_Rel *const rp, unsigned sym, unsigned type) +{ + rp->r_info = ((union mips_r_info){ + .r_mips = { .r_sym = w(sym), .r_type = type } + }).r_info; +} + +static int do_file(char const *const fname) +{ + unsigned int reltype = 0; + Elf32_Ehdr *ehdr; + int rc = -1; + + ehdr = mmap_file(fname); + if (!ehdr) + goto out; + + w = w4nat; + w2 = w2nat; + w8 = w8nat; + switch (ehdr->e_ident[EI_DATA]) { + static unsigned int const endian = 1; + default: + fprintf(stderr, "unrecognized ELF data encoding %d: %s\n", + ehdr->e_ident[EI_DATA], fname); + goto out; + case ELFDATA2LSB: + if (*(unsigned char const *)&endian != 1) { + /* main() is big endian, file.o is little endian. */ + w = w4rev; + w2 = w2rev; + w8 = w8rev; + } + ideal_nop4_arm = ideal_nop4_arm_le; + bl_mcount_arm = bl_mcount_arm_le; + push_arm = push_arm_le; + ideal_nop2_thumb = ideal_nop2_thumb_le; + push_bl_mcount_thumb = push_bl_mcount_thumb_le; + break; + case ELFDATA2MSB: + if (*(unsigned char const *)&endian != 0) { + /* main() is little endian, file.o is big endian. */ + w = w4rev; + w2 = w2rev; + w8 = w8rev; + } + ideal_nop4_arm = ideal_nop4_arm_be; + bl_mcount_arm = bl_mcount_arm_be; + push_arm = push_arm_be; + ideal_nop2_thumb = ideal_nop2_thumb_be; + push_bl_mcount_thumb = push_bl_mcount_thumb_be; + break; + } /* end switch */ + if (memcmp(ELFMAG, ehdr->e_ident, SELFMAG) != 0 || + w2(ehdr->e_type) != ET_REL || + ehdr->e_ident[EI_VERSION] != EV_CURRENT) { + fprintf(stderr, "unrecognized ET_REL file %s\n", fname); + goto out; + } + + gpfx = '_'; + switch (w2(ehdr->e_machine)) { + default: + fprintf(stderr, "unrecognized e_machine %u %s\n", + w2(ehdr->e_machine), fname); + goto out; + case EM_386: + reltype = R_386_32; + rel_type_nop = R_386_NONE; + make_nop = make_nop_x86; + ideal_nop = ideal_nop5_x86_32; + mcount_adjust_32 = -1; + gpfx = 0; + break; + case EM_ARM: + reltype = R_ARM_ABS32; + altmcount = "__gnu_mcount_nc"; + make_nop = make_nop_arm; + rel_type_nop = R_ARM_NONE; + is_fake_mcount32 = arm_is_fake_mcount; + gpfx = 0; + break; + case EM_AARCH64: + reltype = R_AARCH64_ABS64; + make_nop = make_nop_arm64; + rel_type_nop = R_AARCH64_NONE; + ideal_nop = ideal_nop4_arm64; + is_fake_mcount64 = arm64_is_fake_mcount; + break; + case EM_SW64: + reltype = R_SW64_REFQUAD; + make_nop = make_nop_sw64; + rel_type_nop = R_SW64_NONE; + ideal_nop = ideal_nop4_sw64; + mcount_adjust_64 = -12; + is_fake_mcount64 = sw64_is_fake_mcount; + break; + case EM_IA_64: reltype = R_IA64_IMM64; break; + case EM_MIPS: /* reltype: e_class */ break; + case EM_PPC: reltype = R_PPC_ADDR32; break; + case EM_PPC64: reltype = R_PPC64_ADDR64; break; + case EM_S390: /* reltype: e_class */ break; + case EM_SH: reltype = R_SH_DIR32; gpfx = 0; break; + case EM_SPARCV9: reltype = R_SPARC_64; break; + case EM_X86_64: + make_nop = make_nop_x86; + ideal_nop = ideal_nop5_x86_64; + reltype = R_X86_64_64; + rel_type_nop = R_X86_64_NONE; + mcount_adjust_64 = -1; + gpfx = 0; + break; + } /* end switch */ + + switch (ehdr->e_ident[EI_CLASS]) { + default: + fprintf(stderr, "unrecognized ELF class %d %s\n", + ehdr->e_ident[EI_CLASS], fname); + goto out; + case ELFCLASS32: + if (w2(ehdr->e_ehsize) != sizeof(Elf32_Ehdr) + || w2(ehdr->e_shentsize) != sizeof(Elf32_Shdr)) { + fprintf(stderr, + "unrecognized ET_REL file: %s\n", fname); + goto out; + } + if (w2(ehdr->e_machine) == EM_MIPS) { + reltype = R_MIPS_32; + is_fake_mcount32 = MIPS32_is_fake_mcount; + } + if (do32(ehdr, fname, reltype) < 0) + goto out; + break; + case ELFCLASS64: { + Elf64_Ehdr *const ghdr = (Elf64_Ehdr *)ehdr; + if (w2(ghdr->e_ehsize) != sizeof(Elf64_Ehdr) + || w2(ghdr->e_shentsize) != sizeof(Elf64_Shdr)) { + fprintf(stderr, + "unrecognized ET_REL file: %s\n", fname); + goto out; + } + if (w2(ghdr->e_machine) == EM_S390) { + reltype = R_390_64; + mcount_adjust_64 = -14; + } + if (w2(ghdr->e_machine) == EM_MIPS) { + reltype = R_MIPS_64; + Elf64_r_sym = MIPS64_r_sym; + Elf64_r_info = MIPS64_r_info; + is_fake_mcount64 = MIPS64_is_fake_mcount; + } + if (do64(ghdr, fname, reltype) < 0) + goto out; + break; + } + } /* end switch */ + + rc = write_file(fname); +out: + file_append_cleanup(); + mmap_cleanup(); + return rc; +} + +int main(int argc, char *argv[]) +{ + const char ftrace[] = "/ftrace.o"; + int ftrace_size = sizeof(ftrace) - 1; + int n_error = 0; /* gcc-4.3.0 false positive complaint */ + int c; + int i; + + while ((c = getopt(argc, argv, "w")) >= 0) { + switch (c) { + case 'w': + warn_on_notrace_sect = 1; + break; + default: + fprintf(stderr, "usage: recordmcount [-w] file.o...\n"); + return 0; + } + } + + if ((argc - optind) < 1) { + fprintf(stderr, "usage: recordmcount [-w] file.o...\n"); + return 0; + } + + /* Process each file in turn, allowing deep failure. */ + for (i = optind; i < argc; i++) { + char *file = argv[i]; + int len; + + /* + * The file kernel/trace/ftrace.o references the mcount + * function but does not call it. Since ftrace.o should + * not be traced anyway, we just skip it. + */ + len = strlen(file); + if (len >= ftrace_size && + strcmp(file + (len - ftrace_size), ftrace) == 0) + continue; + + if (do_file(file)) { + fprintf(stderr, "%s: failed\n", file); + ++n_error; + } + } + return !!n_error; +} diff --git a/src/net/scripts/recordmcount.h b/src/net/scripts/recordmcount.h new file mode 100644 index 0000000..1e9baa5 --- /dev/null +++ b/src/net/scripts/recordmcount.h @@ -0,0 +1,697 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * recordmcount.h + * + * This code was taken out of recordmcount.c written by + * Copyright 2009 John F. Reiser <jreiser@BitWagon.com>. All rights reserved. + * + * The original code had the same algorithms for both 32bit + * and 64bit ELF files, but the code was duplicated to support + * the difference in structures that were used. This + * file creates a macro of everything that is different between + * the 64 and 32 bit code, such that by including this header + * twice we can create both sets of functions by including this + * header once with RECORD_MCOUNT_64 undefined, and again with + * it defined. + * + * This conversion to macros was done by: + * Copyright 2010 Steven Rostedt <srostedt@redhat.com>, Red Hat Inc. + */ +#undef append_func +#undef is_fake_mcount +#undef fn_is_fake_mcount +#undef MIPS_is_fake_mcount +#undef mcount_adjust +#undef sift_rel_mcount +#undef nop_mcount +#undef find_secsym_ndx +#undef __has_rel_mcount +#undef has_rel_mcount +#undef tot_relsize +#undef get_mcountsym +#undef find_symtab +#undef get_shnum +#undef set_shnum +#undef get_shstrndx +#undef get_symindex +#undef get_sym_str_and_relp +#undef do_func +#undef Elf_Addr +#undef Elf_Ehdr +#undef Elf_Shdr +#undef Elf_Rel +#undef Elf_Rela +#undef Elf_Sym +#undef ELF_R_SYM +#undef Elf_r_sym +#undef ELF_R_INFO +#undef Elf_r_info +#undef ELF_ST_BIND +#undef ELF_ST_TYPE +#undef fn_ELF_R_SYM +#undef fn_ELF_R_INFO +#undef uint_t +#undef _w +#undef _align +#undef _size + +#ifdef RECORD_MCOUNT_64 +# define append_func append64 +# define sift_rel_mcount sift64_rel_mcount +# define nop_mcount nop_mcount_64 +# define find_secsym_ndx find64_secsym_ndx +# define __has_rel_mcount __has64_rel_mcount +# define has_rel_mcount has64_rel_mcount +# define tot_relsize tot64_relsize +# define find_symtab find_symtab64 +# define get_shnum get_shnum64 +# define set_shnum set_shnum64 +# define get_shstrndx get_shstrndx64 +# define get_symindex get_symindex64 +# define get_sym_str_and_relp get_sym_str_and_relp_64 +# define do_func do64 +# define get_mcountsym get_mcountsym_64 +# define is_fake_mcount is_fake_mcount64 +# define fn_is_fake_mcount fn_is_fake_mcount64 +# define MIPS_is_fake_mcount MIPS64_is_fake_mcount +# define mcount_adjust mcount_adjust_64 +# define Elf_Addr Elf64_Addr +# define Elf_Ehdr Elf64_Ehdr +# define Elf_Shdr Elf64_Shdr +# define Elf_Rel Elf64_Rel +# define Elf_Rela Elf64_Rela +# define Elf_Sym Elf64_Sym +# define ELF_R_SYM ELF64_R_SYM +# define Elf_r_sym Elf64_r_sym +# define ELF_R_INFO ELF64_R_INFO +# define Elf_r_info Elf64_r_info +# define ELF_ST_BIND ELF64_ST_BIND +# define ELF_ST_TYPE ELF64_ST_TYPE +# define fn_ELF_R_SYM fn_ELF64_R_SYM +# define fn_ELF_R_INFO fn_ELF64_R_INFO +# define uint_t uint64_t +# define _w w8 +# define _align 7u +# define _size 8 +#else +# define append_func append32 +# define sift_rel_mcount sift32_rel_mcount +# define nop_mcount nop_mcount_32 +# define find_secsym_ndx find32_secsym_ndx +# define __has_rel_mcount __has32_rel_mcount +# define has_rel_mcount has32_rel_mcount +# define tot_relsize tot32_relsize +# define find_symtab find_symtab32 +# define get_shnum get_shnum32 +# define set_shnum set_shnum32 +# define get_shstrndx get_shstrndx32 +# define get_symindex get_symindex32 +# define get_sym_str_and_relp get_sym_str_and_relp_32 +# define do_func do32 +# define get_mcountsym get_mcountsym_32 +# define is_fake_mcount is_fake_mcount32 +# define fn_is_fake_mcount fn_is_fake_mcount32 +# define MIPS_is_fake_mcount MIPS32_is_fake_mcount +# define mcount_adjust mcount_adjust_32 +# define Elf_Addr Elf32_Addr +# define Elf_Ehdr Elf32_Ehdr +# define Elf_Shdr Elf32_Shdr +# define Elf_Rel Elf32_Rel +# define Elf_Rela Elf32_Rela +# define Elf_Sym Elf32_Sym +# define ELF_R_SYM ELF32_R_SYM +# define Elf_r_sym Elf32_r_sym +# define ELF_R_INFO ELF32_R_INFO +# define Elf_r_info Elf32_r_info +# define ELF_ST_BIND ELF32_ST_BIND +# define ELF_ST_TYPE ELF32_ST_TYPE +# define fn_ELF_R_SYM fn_ELF32_R_SYM +# define fn_ELF_R_INFO fn_ELF32_R_INFO +# define uint_t uint32_t +# define _w w +# define _align 3u +# define _size 4 +#endif + +/* Functions and pointers that do_file() may override for specific e_machine. */ +static int fn_is_fake_mcount(Elf_Rel const *rp) +{ + return 0; +} +static int (*is_fake_mcount)(Elf_Rel const *rp) = fn_is_fake_mcount; + +static uint_t fn_ELF_R_SYM(Elf_Rel const *rp) +{ + return ELF_R_SYM(_w(rp->r_info)); +} +static uint_t (*Elf_r_sym)(Elf_Rel const *rp) = fn_ELF_R_SYM; + +static void fn_ELF_R_INFO(Elf_Rel *const rp, unsigned sym, unsigned type) +{ + rp->r_info = _w(ELF_R_INFO(sym, type)); +} +static void (*Elf_r_info)(Elf_Rel *const rp, unsigned sym, unsigned type) = fn_ELF_R_INFO; + +static int mcount_adjust = 0; + +/* + * MIPS mcount long call has 2 _mcount symbols, only the position of the 1st + * _mcount symbol is needed for dynamic function tracer, with it, to disable + * tracing(ftrace_make_nop), the instruction in the position is replaced with + * the "b label" instruction, to enable tracing(ftrace_make_call), replace the + * instruction back. So, here, we set the 2nd one as fake and filter it. + * + * c: 3c030000 lui v1,0x0 <--> b label + * c: R_MIPS_HI16 _mcount + * c: R_MIPS_NONE *ABS* + * c: R_MIPS_NONE *ABS* + * 10: 64630000 daddiu v1,v1,0 + * 10: R_MIPS_LO16 _mcount + * 10: R_MIPS_NONE *ABS* + * 10: R_MIPS_NONE *ABS* + * 14: 03e0082d move at,ra + * 18: 0060f809 jalr v1 + * label: + */ +#define MIPS_FAKEMCOUNT_OFFSET 4 + +static int MIPS_is_fake_mcount(Elf_Rel const *rp) +{ + static Elf_Addr old_r_offset = ~(Elf_Addr)0; + Elf_Addr current_r_offset = _w(rp->r_offset); + int is_fake; + + is_fake = (old_r_offset != ~(Elf_Addr)0) && + (current_r_offset - old_r_offset == MIPS_FAKEMCOUNT_OFFSET); + old_r_offset = current_r_offset; + + return is_fake; +} + +static unsigned int get_symindex(Elf_Sym const *sym, Elf32_Word const *symtab, + Elf32_Word const *symtab_shndx) +{ + unsigned long offset; + unsigned short shndx = w2(sym->st_shndx); + int index; + + if (shndx > SHN_UNDEF && shndx < SHN_LORESERVE) + return shndx; + + if (shndx == SHN_XINDEX) { + offset = (unsigned long)sym - (unsigned long)symtab; + index = offset / sizeof(*sym); + + return w(symtab_shndx[index]); + } + + return 0; +} + +static unsigned int get_shnum(Elf_Ehdr const *ehdr, Elf_Shdr const *shdr0) +{ + if (shdr0 && !ehdr->e_shnum) + return w(shdr0->sh_size); + + return w2(ehdr->e_shnum); +} + +static void set_shnum(Elf_Ehdr *ehdr, Elf_Shdr *shdr0, unsigned int new_shnum) +{ + if (new_shnum >= SHN_LORESERVE) { + ehdr->e_shnum = 0; + shdr0->sh_size = w(new_shnum); + } else + ehdr->e_shnum = w2(new_shnum); +} + +static int get_shstrndx(Elf_Ehdr const *ehdr, Elf_Shdr const *shdr0) +{ + if (ehdr->e_shstrndx != SHN_XINDEX) + return w2(ehdr->e_shstrndx); + + return w(shdr0->sh_link); +} + +static void find_symtab(Elf_Ehdr *const ehdr, Elf_Shdr const *shdr0, + unsigned const nhdr, Elf32_Word **symtab, + Elf32_Word **symtab_shndx) +{ + Elf_Shdr const *relhdr; + unsigned k; + + *symtab = NULL; + *symtab_shndx = NULL; + + for (relhdr = shdr0, k = nhdr; k; --k, ++relhdr) { + if (relhdr->sh_type == SHT_SYMTAB) + *symtab = (void *)ehdr + relhdr->sh_offset; + else if (relhdr->sh_type == SHT_SYMTAB_SHNDX) + *symtab_shndx = (void *)ehdr + relhdr->sh_offset; + + if (*symtab && *symtab_shndx) + break; + } +} + +/* Append the new shstrtab, Elf_Shdr[], __mcount_loc and its relocations. */ +static int append_func(Elf_Ehdr *const ehdr, + Elf_Shdr *const shstr, + uint_t const *const mloc0, + uint_t const *const mlocp, + Elf_Rel const *const mrel0, + Elf_Rel const *const mrelp, + unsigned int const rel_entsize, + unsigned int const symsec_sh_link) +{ + /* Begin constructing output file */ + Elf_Shdr mcsec; + char const *mc_name = (sizeof(Elf_Rela) == rel_entsize) + ? ".rela__mcount_loc" + : ".rel__mcount_loc"; + uint_t const old_shoff = _w(ehdr->e_shoff); + uint_t const old_shstr_sh_size = _w(shstr->sh_size); + uint_t const old_shstr_sh_offset = _w(shstr->sh_offset); + Elf_Shdr *const shdr0 = (Elf_Shdr *)(old_shoff + (void *)ehdr); + unsigned int const old_shnum = get_shnum(ehdr, shdr0); + unsigned int const new_shnum = 2 + old_shnum; /* {.rel,}__mcount_loc */ + uint_t t = 1 + strlen(mc_name) + _w(shstr->sh_size); + uint_t new_e_shoff; + + shstr->sh_size = _w(t); + shstr->sh_offset = _w(sb.st_size); + t += sb.st_size; + t += (_align & -t); /* word-byte align */ + new_e_shoff = t; + + set_shnum(ehdr, shdr0, new_shnum); + + /* body for new shstrtab */ + if (ulseek(sb.st_size, SEEK_SET) < 0) + return -1; + if (uwrite(old_shstr_sh_offset + (void *)ehdr, old_shstr_sh_size) < 0) + return -1; + if (uwrite(mc_name, 1 + strlen(mc_name)) < 0) + return -1; + + /* old(modified) Elf_Shdr table, word-byte aligned */ + if (ulseek(t, SEEK_SET) < 0) + return -1; + t += sizeof(Elf_Shdr) * old_shnum; + if (uwrite(old_shoff + (void *)ehdr, + sizeof(Elf_Shdr) * old_shnum) < 0) + return -1; + + /* new sections __mcount_loc and .rel__mcount_loc */ + t += 2*sizeof(mcsec); + mcsec.sh_name = w((sizeof(Elf_Rela) == rel_entsize) + strlen(".rel") + + old_shstr_sh_size); + mcsec.sh_type = w(SHT_PROGBITS); + mcsec.sh_flags = _w(SHF_ALLOC); + mcsec.sh_addr = 0; + mcsec.sh_offset = _w(t); + mcsec.sh_size = _w((void *)mlocp - (void *)mloc0); + mcsec.sh_link = 0; + mcsec.sh_info = 0; + mcsec.sh_addralign = _w(_size); + mcsec.sh_entsize = _w(_size); + if (uwrite(&mcsec, sizeof(mcsec)) < 0) + return -1; + + mcsec.sh_name = w(old_shstr_sh_size); + mcsec.sh_type = (sizeof(Elf_Rela) == rel_entsize) + ? w(SHT_RELA) + : w(SHT_REL); + mcsec.sh_flags = 0; + mcsec.sh_addr = 0; + mcsec.sh_offset = _w((void *)mlocp - (void *)mloc0 + t); + mcsec.sh_size = _w((void *)mrelp - (void *)mrel0); + mcsec.sh_link = w(symsec_sh_link); + mcsec.sh_info = w(old_shnum); + mcsec.sh_addralign = _w(_size); + mcsec.sh_entsize = _w(rel_entsize); + + if (uwrite(&mcsec, sizeof(mcsec)) < 0) + return -1; + + if (uwrite(mloc0, (void *)mlocp - (void *)mloc0) < 0) + return -1; + if (uwrite(mrel0, (void *)mrelp - (void *)mrel0) < 0) + return -1; + + ehdr->e_shoff = _w(new_e_shoff); + if (ulseek(0, SEEK_SET) < 0) + return -1; + if (uwrite(ehdr, sizeof(*ehdr)) < 0) + return -1; + return 0; +} + +static unsigned get_mcountsym(Elf_Sym const *const sym0, + Elf_Rel const *relp, + char const *const str0) +{ + unsigned mcountsym = 0; + + Elf_Sym const *const symp = + &sym0[Elf_r_sym(relp)]; + char const *symname = &str0[w(symp->st_name)]; + char const *mcount = gpfx == '_' ? "_mcount" : "mcount"; + char const *fentry = "__fentry__"; + + if (symname[0] == '.') + ++symname; /* ppc64 hack */ + if (strcmp(mcount, symname) == 0 || + (altmcount && strcmp(altmcount, symname) == 0) || + (strcmp(fentry, symname) == 0)) + mcountsym = Elf_r_sym(relp); + + return mcountsym; +} + +static void get_sym_str_and_relp(Elf_Shdr const *const relhdr, + Elf_Ehdr const *const ehdr, + Elf_Sym const **sym0, + char const **str0, + Elf_Rel const **relp) +{ + Elf_Shdr *const shdr0 = (Elf_Shdr *)(_w(ehdr->e_shoff) + + (void *)ehdr); + unsigned const symsec_sh_link = w(relhdr->sh_link); + Elf_Shdr const *const symsec = &shdr0[symsec_sh_link]; + Elf_Shdr const *const strsec = &shdr0[w(symsec->sh_link)]; + Elf_Rel const *const rel0 = (Elf_Rel const *)(_w(relhdr->sh_offset) + + (void *)ehdr); + + *sym0 = (Elf_Sym const *)(_w(symsec->sh_offset) + + (void *)ehdr); + + *str0 = (char const *)(_w(strsec->sh_offset) + + (void *)ehdr); + + *relp = rel0; +} + +/* + * Look at the relocations in order to find the calls to mcount. + * Accumulate the section offsets that are found, and their relocation info, + * onto the end of the existing arrays. + */ +static uint_t *sift_rel_mcount(uint_t *mlocp, + unsigned const offbase, + Elf_Rel **const mrelpp, + Elf_Shdr const *const relhdr, + Elf_Ehdr const *const ehdr, + unsigned const recsym, + uint_t const recval, + unsigned const reltype) +{ + uint_t *const mloc0 = mlocp; + Elf_Rel *mrelp = *mrelpp; + Elf_Sym const *sym0; + char const *str0; + Elf_Rel const *relp; + unsigned rel_entsize = _w(relhdr->sh_entsize); + unsigned const nrel = _w(relhdr->sh_size) / rel_entsize; + unsigned mcountsym = 0; + unsigned t; + + get_sym_str_and_relp(relhdr, ehdr, &sym0, &str0, &relp); + + for (t = nrel; t; --t) { + if (!mcountsym) + mcountsym = get_mcountsym(sym0, relp, str0); + + if (mcountsym && mcountsym == Elf_r_sym(relp) && + !is_fake_mcount(relp)) { + uint_t const addend = + _w(_w(relp->r_offset) - recval + mcount_adjust); + mrelp->r_offset = _w(offbase + + ((void *)mlocp - (void *)mloc0)); + Elf_r_info(mrelp, recsym, reltype); + if (rel_entsize == sizeof(Elf_Rela)) { + ((Elf_Rela *)mrelp)->r_addend = addend; + *mlocp++ = 0; + } else + *mlocp++ = addend; + + mrelp = (Elf_Rel *)(rel_entsize + (void *)mrelp); + } + relp = (Elf_Rel const *)(rel_entsize + (void *)relp); + } + *mrelpp = mrelp; + return mlocp; +} + +/* + * Read the relocation table again, but this time its called on sections + * that are not going to be traced. The mcount calls here will be converted + * into nops. + */ +static int nop_mcount(Elf_Shdr const *const relhdr, + Elf_Ehdr const *const ehdr, + const char *const txtname) +{ + Elf_Shdr *const shdr0 = (Elf_Shdr *)(_w(ehdr->e_shoff) + + (void *)ehdr); + Elf_Sym const *sym0; + char const *str0; + Elf_Rel const *relp; + Elf_Shdr const *const shdr = &shdr0[w(relhdr->sh_info)]; + unsigned rel_entsize = _w(relhdr->sh_entsize); + unsigned const nrel = _w(relhdr->sh_size) / rel_entsize; + unsigned mcountsym = 0; + unsigned t; + int once = 0; + + get_sym_str_and_relp(relhdr, ehdr, &sym0, &str0, &relp); + + for (t = nrel; t; --t) { + int ret = -1; + + if (!mcountsym) + mcountsym = get_mcountsym(sym0, relp, str0); + + if (mcountsym == Elf_r_sym(relp) && !is_fake_mcount(relp)) { + if (make_nop) + ret = make_nop((void *)ehdr, _w(shdr->sh_offset) + _w(relp->r_offset)); + if (warn_on_notrace_sect && !once) { + printf("Section %s has mcount callers being ignored\n", + txtname); + once = 1; + /* just warn? */ + if (!make_nop) + return 0; + } + } + + /* + * If we successfully removed the mcount, mark the relocation + * as a nop (don't do anything with it). + */ + if (!ret) { + Elf_Rel rel; + rel = *(Elf_Rel *)relp; + Elf_r_info(&rel, Elf_r_sym(relp), rel_type_nop); + if (ulseek((void *)relp - (void *)ehdr, SEEK_SET) < 0) + return -1; + if (uwrite(&rel, sizeof(rel)) < 0) + return -1; + } + relp = (Elf_Rel const *)(rel_entsize + (void *)relp); + } + return 0; +} + +/* + * Find a symbol in the given section, to be used as the base for relocating + * the table of offsets of calls to mcount. A local or global symbol suffices, + * but avoid a Weak symbol because it may be overridden; the change in value + * would invalidate the relocations of the offsets of the calls to mcount. + * Often the found symbol will be the unnamed local symbol generated by + * GNU 'as' for the start of each section. For example: + * Num: Value Size Type Bind Vis Ndx Name + * 2: 00000000 0 SECTION LOCAL DEFAULT 1 + */ +static int find_secsym_ndx(unsigned const txtndx, + char const *const txtname, + uint_t *const recvalp, + unsigned int *sym_index, + Elf_Shdr const *const symhdr, + Elf32_Word const *symtab, + Elf32_Word const *symtab_shndx, + Elf_Ehdr const *const ehdr) +{ + Elf_Sym const *const sym0 = (Elf_Sym const *)(_w(symhdr->sh_offset) + + (void *)ehdr); + unsigned const nsym = _w(symhdr->sh_size) / _w(symhdr->sh_entsize); + Elf_Sym const *symp; + unsigned t; + + for (symp = sym0, t = nsym; t; --t, ++symp) { + unsigned int const st_bind = ELF_ST_BIND(symp->st_info); + + if (txtndx == get_symindex(symp, symtab, symtab_shndx) + /* avoid STB_WEAK */ + && (STB_LOCAL == st_bind || STB_GLOBAL == st_bind)) { + /* function symbols on ARM have quirks, avoid them */ + if (w2(ehdr->e_machine) == EM_ARM + && ELF_ST_TYPE(symp->st_info) == STT_FUNC) + continue; + + *recvalp = _w(symp->st_value); + *sym_index = symp - sym0; + return 0; + } + } + fprintf(stderr, "Cannot find symbol for section %u: %s.\n", + txtndx, txtname); + return -1; +} + +/* Evade ISO C restriction: no declaration after statement in has_rel_mcount. */ +static char const * __has_rel_mcount(Elf_Shdr const *const relhdr, /* reltype */ + Elf_Shdr const *const shdr0, + char const *const shstrtab, + char const *const fname) +{ + /* .sh_info depends on .sh_type == SHT_REL[,A] */ + Elf_Shdr const *const txthdr = &shdr0[w(relhdr->sh_info)]; + char const *const txtname = &shstrtab[w(txthdr->sh_name)]; + + if (strcmp("__mcount_loc", txtname) == 0) { + fprintf(stderr, "warning: __mcount_loc already exists: %s\n", + fname); + return already_has_rel_mcount; + } + if (w(txthdr->sh_type) != SHT_PROGBITS || + !(_w(txthdr->sh_flags) & SHF_EXECINSTR)) + return NULL; + return txtname; +} + +static char const *has_rel_mcount(Elf_Shdr const *const relhdr, + Elf_Shdr const *const shdr0, + char const *const shstrtab, + char const *const fname) +{ + if (w(relhdr->sh_type) != SHT_REL && w(relhdr->sh_type) != SHT_RELA) + return NULL; + return __has_rel_mcount(relhdr, shdr0, shstrtab, fname); +} + + +static unsigned tot_relsize(Elf_Shdr const *const shdr0, + unsigned nhdr, + const char *const shstrtab, + const char *const fname) +{ + unsigned totrelsz = 0; + Elf_Shdr const *shdrp = shdr0; + char const *txtname; + + for (; nhdr; --nhdr, ++shdrp) { + txtname = has_rel_mcount(shdrp, shdr0, shstrtab, fname); + if (txtname == already_has_rel_mcount) { + totrelsz = 0; + break; + } + if (txtname && is_mcounted_section_name(txtname)) + totrelsz += _w(shdrp->sh_size); + } + return totrelsz; +} + +/* Overall supervision for Elf32 ET_REL file. */ +static int do_func(Elf_Ehdr *const ehdr, char const *const fname, + unsigned const reltype) +{ + Elf_Shdr *const shdr0 = (Elf_Shdr *)(_w(ehdr->e_shoff) + + (void *)ehdr); + unsigned const nhdr = get_shnum(ehdr, shdr0); + Elf_Shdr *const shstr = &shdr0[get_shstrndx(ehdr, shdr0)]; + char const *const shstrtab = (char const *)(_w(shstr->sh_offset) + + (void *)ehdr); + + Elf_Shdr const *relhdr; + unsigned k; + + Elf32_Word *symtab; + Elf32_Word *symtab_shndx; + + /* Upper bound on space: assume all relevant relocs are for mcount. */ + unsigned totrelsz; + + Elf_Rel * mrel0; + Elf_Rel * mrelp; + + uint_t * mloc0; + uint_t * mlocp; + + unsigned rel_entsize = 0; + unsigned symsec_sh_link = 0; + + int result = 0; + + totrelsz = tot_relsize(shdr0, nhdr, shstrtab, fname); + if (totrelsz == 0) + return 0; + mrel0 = umalloc(totrelsz); + mrelp = mrel0; + if (!mrel0) + return -1; + + /* 2*sizeof(address) <= sizeof(Elf_Rel) */ + mloc0 = umalloc(totrelsz>>1); + mlocp = mloc0; + if (!mloc0) { + free(mrel0); + return -1; + } + + find_symtab(ehdr, shdr0, nhdr, &symtab, &symtab_shndx); + + for (relhdr = shdr0, k = nhdr; k; --k, ++relhdr) { + char const *const txtname = has_rel_mcount(relhdr, shdr0, + shstrtab, fname); + if (txtname == already_has_rel_mcount) { + result = 0; + file_updated = 0; + goto out; /* Nothing to be done; don't append! */ + } + if (txtname && is_mcounted_section_name(txtname)) { + unsigned int recsym; + uint_t recval = 0; + + symsec_sh_link = w(relhdr->sh_link); + result = find_secsym_ndx(w(relhdr->sh_info), txtname, + &recval, &recsym, + &shdr0[symsec_sh_link], + symtab, symtab_shndx, + ehdr); + if (result) + goto out; + + rel_entsize = _w(relhdr->sh_entsize); + mlocp = sift_rel_mcount(mlocp, + (void *)mlocp - (void *)mloc0, &mrelp, + relhdr, ehdr, recsym, recval, reltype); + } else if (txtname && (warn_on_notrace_sect || make_nop)) { + /* + * This section is ignored by ftrace, but still + * has mcount calls. Convert them to nops now. + */ + if (nop_mcount(relhdr, ehdr, txtname) < 0) { + result = -1; + goto out; + } + } + } + if (!result && mloc0 != mlocp) + result = append_func(ehdr, shstr, mloc0, mlocp, mrel0, mrelp, + rel_entsize, symsec_sh_link); +out: + free(mrel0); + free(mloc0); + return result; +} diff --git a/src/net/scripts/recordmcount.pl b/src/net/scripts/recordmcount.pl new file mode 100755 index 0000000..dc1d369 --- /dev/null +++ b/src/net/scripts/recordmcount.pl @@ -0,0 +1,647 @@ +#!/usr/bin/env perl +# SPDX-License-Identifier: GPL-2.0-only +# (c) 2008, Steven Rostedt <srostedt@redhat.com> +# +# recordmcount.pl - makes a section called __mcount_loc that holds +# all the offsets to the calls to mcount. +# +# +# What we want to end up with this is that each object file will have a +# section called __mcount_loc that will hold the list of pointers to mcount +# callers. After final linking, the vmlinux will have within .init.data the +# list of all callers to mcount between __start_mcount_loc and __stop_mcount_loc. +# Later on boot up, the kernel will read this list, save the locations and turn +# them into nops. When tracing or profiling is later enabled, these locations +# will then be converted back to pointers to some function. +# +# This is no easy feat. This script is called just after the original +# object is compiled and before it is linked. +# +# When parse this object file using 'objdump', the references to the call +# sites are offsets from the section that the call site is in. Hence, all +# functions in a section that has a call site to mcount, will have the +# offset from the beginning of the section and not the beginning of the +# function. +# +# But where this section will reside finally in vmlinx is undetermined at +# this point. So we can't use this kind of offsets to record the final +# address of this call site. +# +# The trick is to change the call offset referring the start of a section to +# referring a function symbol in this section. During the link step, 'ld' will +# compute the final address according to the information we record. +# +# e.g. +# +# .section ".sched.text", "ax" +# [...] +# func1: +# [...] +# call mcount (offset: 0x10) +# [...] +# ret +# .globl fun2 +# func2: (offset: 0x20) +# [...] +# [...] +# ret +# func3: +# [...] +# call mcount (offset: 0x30) +# [...] +# +# Both relocation offsets for the mcounts in the above example will be +# offset from .sched.text. If we choose global symbol func2 as a reference and +# make another file called tmp.s with the new offsets: +# +# .section __mcount_loc +# .quad func2 - 0x10 +# .quad func2 + 0x10 +# +# We can then compile this tmp.s into tmp.o, and link it back to the original +# object. +# +# In our algorithm, we will choose the first global function we meet in this +# section as the reference. But this gets hard if there is no global functions +# in this section. In such a case we have to select a local one. E.g. func1: +# +# .section ".sched.text", "ax" +# func1: +# [...] +# call mcount (offset: 0x10) +# [...] +# ret +# func2: +# [...] +# call mcount (offset: 0x20) +# [...] +# .section "other.section" +# +# If we make the tmp.s the same as above, when we link together with +# the original object, we will end up with two symbols for func1: +# one local, one global. After final compile, we will end up with +# an undefined reference to func1 or a wrong reference to another global +# func1 in other files. +# +# Since local objects can reference local variables, we need to find +# a way to make tmp.o reference the local objects of the original object +# file after it is linked together. To do this, we convert func1 +# into a global symbol before linking tmp.o. Then after we link tmp.o +# we will only have a single symbol for func1 that is global. +# We can convert func1 back into a local symbol and we are done. +# +# Here are the steps we take: +# +# 1) Record all the local and weak symbols by using 'nm' +# 2) Use objdump to find all the call site offsets and sections for +# mcount. +# 3) Compile the list into its own object. +# 4) Do we have to deal with local functions? If not, go to step 8. +# 5) Make an object that converts these local functions to global symbols +# with objcopy. +# 6) Link together this new object with the list object. +# 7) Convert the local functions back to local symbols and rename +# the result as the original object. +# 8) Link the object with the list object. +# 9) Move the result back to the original object. +# + +use warnings; +use strict; + +my $P = $0; +$P =~ s@.*/@@g; + +my $V = '0.1'; + +if ($#ARGV != 11) { + print "usage: $P arch endian bits objdump objcopy cc ld nm rm mv is_module inputfile\n"; + print "version: $V\n"; + exit(1); +} + +my ($arch, $endian, $bits, $objdump, $objcopy, $cc, + $ld, $nm, $rm, $mv, $is_module, $inputfile) = @ARGV; + +# This file refers to mcount and shouldn't be ftraced, so lets' ignore it +if ($inputfile =~ m,kernel/trace/ftrace\.o$,) { + exit(0); +} + +# Acceptable sections to record. +my %text_sections = ( + ".text" => 1, + ".init.text" => 1, + ".ref.text" => 1, + ".sched.text" => 1, + ".spinlock.text" => 1, + ".irqentry.text" => 1, + ".softirqentry.text" => 1, + ".kprobes.text" => 1, + ".cpuidle.text" => 1, + ".text.unlikely" => 1, +); + +# Acceptable section-prefixes to record. +my %text_section_prefixes = ( + ".text." => 1, +); + +# Note: we are nice to C-programmers here, thus we skip the '||='-idiom. +$objdump = 'objdump' if (!$objdump); +$objcopy = 'objcopy' if (!$objcopy); +$cc = 'gcc' if (!$cc); +$ld = 'ld' if (!$ld); +$nm = 'nm' if (!$nm); +$rm = 'rm' if (!$rm); +$mv = 'mv' if (!$mv); + +#print STDERR "running: $P '$arch' '$objdump' '$objcopy' '$cc' '$ld' " . +# "'$nm' '$rm' '$mv' '$inputfile'\n"; + +my %locals; # List of local (static) functions +my %weak; # List of weak functions +my %convert; # List of local functions used that needs conversion + +my $type; +my $local_regex; # Match a local function (return function) +my $weak_regex; # Match a weak function (return function) +my $section_regex; # Find the start of a section +my $function_regex; # Find the name of a function + # (return offset and func name) +my $mcount_regex; # Find the call site to mcount (return offset) +my $mcount_adjust; # Address adjustment to mcount offset +my $alignment; # The .align value to use for $mcount_section +my $section_type; # Section header plus possible alignment command +my $can_use_local = 0; # If we can use local function references + +# Shut up recordmcount if user has older objcopy +my $quiet_recordmcount = ".tmp_quiet_recordmcount"; +my $print_warning = 1; +$print_warning = 0 if ( -f $quiet_recordmcount); + +## +# check_objcopy - whether objcopy supports --globalize-symbols +# +# --globalize-symbols came out in 2.17, we must test the version +# of objcopy, and if it is less than 2.17, then we can not +# record local functions. +sub check_objcopy +{ + open (IN, "$objcopy --version |") or die "error running $objcopy"; + while (<IN>) { + if (/objcopy.*\s(\d+)\.(\d+)/) { + $can_use_local = 1 if ($1 > 2 || ($1 == 2 && $2 >= 17)); + last; + } + } + close (IN); + + if (!$can_use_local && $print_warning) { + print STDERR "WARNING: could not find objcopy version or version " . + "is less than 2.17.\n" . + "\tLocal function references are disabled.\n"; + open (QUIET, ">$quiet_recordmcount"); + printf QUIET "Disables the warning from recordmcount.pl\n"; + close QUIET; + } +} + +if ($arch =~ /(x86(_64)?)|(i386)/) { + if ($bits == 64) { + $arch = "x86_64"; + } else { + $arch = "i386"; + } +} + +# +# We base the defaults off of i386, the other archs may +# feel free to change them in the below if statements. +# +$local_regex = "^[0-9a-fA-F]+\\s+t\\s+(\\S+)"; +$weak_regex = "^[0-9a-fA-F]+\\s+([wW])\\s+(\\S+)"; +$section_regex = "Disassembly of section\\s+(\\S+):"; +$function_regex = "^([0-9a-fA-F]+)\\s+<([^^]*?)>:"; +$mcount_regex = "^\\s*([0-9a-fA-F]+):.*\\s(mcount|__fentry__)\$"; +$section_type = '@progbits'; +$mcount_adjust = 0; +$type = ".long"; + +if ($arch eq "x86_64") { + $mcount_regex = "^\\s*([0-9a-fA-F]+):.*\\s(mcount|__fentry__)([+-]0x[0-9a-zA-Z]+)?\$"; + $type = ".quad"; + $alignment = 8; + $mcount_adjust = -1; + + # force flags for this arch + $ld .= " -m elf_x86_64"; + $objdump .= " -M x86-64"; + $objcopy .= " -O elf64-x86-64"; + $cc .= " -m64"; + +} elsif ($arch eq "i386") { + $alignment = 4; + $mcount_adjust = -1; + + # force flags for this arch + $ld .= " -m elf_i386"; + $objdump .= " -M i386"; + $objcopy .= " -O elf32-i386"; + $cc .= " -m32"; + +} elsif ($arch eq "s390" && $bits == 64) { + if ($cc =~ /-DCC_USING_HOTPATCH/) { + $mcount_regex = "^\\s*([0-9a-fA-F]+):\\s*c0 04 00 00 00 00\\s*(brcl\\s*0,|jgnop\\s*)[0-9a-f]+ <([^\+]*)>\$"; + $mcount_adjust = 0; + } else { + $mcount_regex = "^\\s*([0-9a-fA-F]+):\\s*R_390_(PC|PLT)32DBL\\s+_mcount\\+0x2\$"; + $mcount_adjust = -14; + } + $alignment = 8; + $type = ".quad"; + $ld .= " -m elf64_s390"; + $cc .= " -m64"; + +} elsif ($arch eq "sh") { + $alignment = 2; + + # force flags for this arch + $ld .= " -m shlelf_linux"; + if ($endian eq "big") { + $objcopy .= " -O elf32-shbig-linux"; + } else { + $objcopy .= " -O elf32-sh-linux"; + } + +} elsif ($arch eq "powerpc") { + my $ldemulation; + + $local_regex = "^[0-9a-fA-F]+\\s+t\\s+(\\.?\\S+)"; + # See comment in the sparc64 section for why we use '\w'. + $function_regex = "^([0-9a-fA-F]+)\\s+<(\\.?\\w*?)>:"; + $mcount_regex = "^\\s*([0-9a-fA-F]+):.*\\s\\.?_mcount\$"; + + if ($endian eq "big") { + $cc .= " -mbig-endian "; + $ld .= " -EB "; + $ldemulation = "ppc" + } else { + $cc .= " -mlittle-endian "; + $ld .= " -EL "; + $ldemulation = "lppc" + } + if ($bits == 64) { + $type = ".quad"; + $cc .= " -m64 "; + $ld .= " -m elf64".$ldemulation." "; + } else { + $cc .= " -m32 "; + $ld .= " -m elf32".$ldemulation." "; + } + +} elsif ($arch eq "arm") { + $alignment = 2; + $section_type = '%progbits'; + $mcount_regex = "^\\s*([0-9a-fA-F]+):\\s*R_ARM_(CALL|PC24|THM_CALL)" . + "\\s+(__gnu_mcount_nc|mcount)\$"; + +} elsif ($arch eq "arm64") { + $alignment = 3; + $section_type = '%progbits'; + $mcount_regex = "^\\s*([0-9a-fA-F]+):\\s*R_AARCH64_CALL26\\s+_mcount\$"; + $type = ".quad"; +} elsif ($arch eq "ia64") { + $mcount_regex = "^\\s*([0-9a-fA-F]+):.*\\s_mcount\$"; + $type = "data8"; + + if ($is_module eq "0") { + $cc .= " -mconstant-gp"; + } +} elsif ($arch eq "sparc64") { + # In the objdump output there are giblets like: + # 0000000000000000 <igmp_net_exit-0x18>: + # As there's some data blobs that get emitted into the + # text section before the first instructions and the first + # real symbols. We don't want to match that, so to combat + # this we use '\w' so we'll match just plain symbol names, + # and not those that also include hex offsets inside of the + # '<>' brackets. Actually the generic function_regex setting + # could safely use this too. + $function_regex = "^([0-9a-fA-F]+)\\s+<(\\w*?)>:"; + + # Sparc64 calls '_mcount' instead of plain 'mcount'. + $mcount_regex = "^\\s*([0-9a-fA-F]+):.*\\s_mcount\$"; + + $alignment = 8; + $type = ".xword"; + $ld .= " -m elf64_sparc"; + $cc .= " -m64"; + $objcopy .= " -O elf64-sparc"; +} elsif ($arch eq "mips") { + # To enable module support, we need to enable the -mlong-calls option + # of gcc for module, after using this option, we can not get the real + # offset of the calling to _mcount, but the offset of the lui + # instruction or the addiu one. herein, we record the address of the + # first one, and then we can replace this instruction by a branch + # instruction to jump over the profiling function to filter the + # indicated functions, or switch back to the lui instruction to trace + # them, which means dynamic tracing. + # + # c: 3c030000 lui v1,0x0 + # c: R_MIPS_HI16 _mcount + # c: R_MIPS_NONE *ABS* + # c: R_MIPS_NONE *ABS* + # 10: 64630000 daddiu v1,v1,0 + # 10: R_MIPS_LO16 _mcount + # 10: R_MIPS_NONE *ABS* + # 10: R_MIPS_NONE *ABS* + # 14: 03e0082d move at,ra + # 18: 0060f809 jalr v1 + # + # for the kernel: + # + # 10: 03e0082d move at,ra + # 14: 0c000000 jal 0 <loongson_halt> + # 14: R_MIPS_26 _mcount + # 14: R_MIPS_NONE *ABS* + # 14: R_MIPS_NONE *ABS* + # 18: 00020021 nop + if ($is_module eq "0") { + $mcount_regex = "^\\s*([0-9a-fA-F]+): R_MIPS_26\\s+_mcount\$"; + } else { + $mcount_regex = "^\\s*([0-9a-fA-F]+): R_MIPS_HI16\\s+_mcount\$"; + } + $objdump .= " -Melf-trad".$endian."mips "; + + if ($endian eq "big") { + $endian = " -EB "; + $ld .= " -melf".$bits."btsmip"; + } else { + $endian = " -EL "; + $ld .= " -melf".$bits."ltsmip"; + } + + $cc .= " -mno-abicalls -fno-pic -mabi=" . $bits . $endian; + $ld .= $endian; + + if ($bits == 64) { + $function_regex = + "^([0-9a-fA-F]+)\\s+<(.|[^\$]L.*?|\$[^L].*?|[^\$][^L].*?)>:"; + $type = ".dword"; + } +} elsif ($arch eq "microblaze") { + # Microblaze calls '_mcount' instead of plain 'mcount'. + $mcount_regex = "^\\s*([0-9a-fA-F]+):.*\\s_mcount\$"; +} elsif ($arch eq "riscv") { + $function_regex = "^([0-9a-fA-F]+)\\s+<([^.0-9][0-9a-zA-Z_\\.]+)>:"; + $mcount_regex = "^\\s*([0-9a-fA-F]+):\\sR_RISCV_CALL(_PLT)?\\s_?mcount\$"; + $type = ".quad"; + $alignment = 2; +} elsif ($arch eq "nds32") { + $mcount_regex = "^\\s*([0-9a-fA-F]+):\\s*R_NDS32_HI20_RELA\\s+_mcount\$"; + $alignment = 2; +} elsif ($arch eq "csky") { + $mcount_regex = "^\\s*([0-9a-fA-F]+):\\s*R_CKCORE_PCREL_JSR_IMM26BY2\\s+_mcount\$"; + $alignment = 2; +} else { + die "Arch $arch is not supported with CONFIG_FTRACE_MCOUNT_RECORD"; +} + +my $text_found = 0; +my $read_function = 0; +my $opened = 0; +my $mcount_section = "__mcount_loc"; + +my $dirname; +my $filename; +my $prefix; +my $ext; + +if ($inputfile =~ m,^(.*)/([^/]*)$,) { + $dirname = $1; + $filename = $2; +} else { + $dirname = "."; + $filename = $inputfile; +} + +if ($filename =~ m,^(.*)(\.\S),) { + $prefix = $1; + $ext = $2; +} else { + $prefix = $filename; + $ext = ""; +} + +my $mcount_s = $dirname . "/.tmp_mc_" . $prefix . ".s"; +my $mcount_o = $dirname . "/.tmp_mc_" . $prefix . ".o"; + +check_objcopy(); + +# +# Step 1: find all the local (static functions) and weak symbols. +# 't' is local, 'w/W' is weak +# +open (IN, "$nm $inputfile|") || die "error running $nm"; +while (<IN>) { + if (/$local_regex/) { + $locals{$1} = 1; + } elsif (/$weak_regex/) { + $weak{$2} = $1; + } +} +close(IN); + +my @offsets; # Array of offsets of mcount callers +my $ref_func; # reference function to use for offsets +my $offset = 0; # offset of ref_func to section beginning + +## +# update_funcs - print out the current mcount callers +# +# Go through the list of offsets to callers and write them to +# the output file in a format that can be read by an assembler. +# +sub update_funcs +{ + return unless ($ref_func and @offsets); + + # Sanity check on weak function. A weak function may be overwritten by + # another function of the same name, making all these offsets incorrect. + if (defined $weak{$ref_func}) { + die "$inputfile: ERROR: referencing weak function" . + " $ref_func for mcount\n"; + } + + # is this function static? If so, note this fact. + if (defined $locals{$ref_func}) { + + # only use locals if objcopy supports globalize-symbols + if (!$can_use_local) { + return; + } + $convert{$ref_func} = 1; + } + + # Loop through all the mcount caller offsets and print a reference + # to the caller based from the ref_func. + if (!$opened) { + open(FILE, ">$mcount_s") || die "can't create $mcount_s\n"; + $opened = 1; + print FILE "\t.section $mcount_section,\"a\",$section_type\n"; + print FILE "\t.align $alignment\n" if (defined($alignment)); + } + foreach my $cur_offset (@offsets) { + printf FILE "\t%s %s + %d\n", $type, $ref_func, $cur_offset - $offset; + } +} + +# +# Step 2: find the sections and mcount call sites +# +open(IN, "LANG=C $objdump -hdr $inputfile|") || die "error running $objdump"; + +my $text; + + +# read headers first +my $read_headers = 1; + +while (<IN>) { + + if ($read_headers && /$mcount_section/) { + # + # Somehow the make process can execute this script on an + # object twice. If it does, we would duplicate the mcount + # section and it will cause the function tracer self test + # to fail. Check if the mcount section exists, and if it does, + # warn and exit. + # + print STDERR "ERROR: $mcount_section already in $inputfile\n" . + "\tThis may be an indication that your build is corrupted.\n" . + "\tDelete $inputfile and try again. If the same object file\n" . + "\tstill causes an issue, then disable CONFIG_DYNAMIC_FTRACE.\n"; + exit(-1); + } + + # is it a section? + if (/$section_regex/) { + $read_headers = 0; + + # Only record text sections that we know are safe + $read_function = defined($text_sections{$1}); + if (!$read_function) { + foreach my $prefix (keys %text_section_prefixes) { + if (substr($1, 0, length $prefix) eq $prefix) { + $read_function = 1; + last; + } + } + } + # print out any recorded offsets + update_funcs(); + + # reset all markers and arrays + $text_found = 0; + undef($ref_func); + undef(@offsets); + + # section found, now is this a start of a function? + } elsif ($read_function && /$function_regex/) { + $text_found = 1; + $text = $2; + + # if this is either a local function or a weak function + # keep looking for functions that are global that + # we can use safely. + if (!defined($locals{$text}) && !defined($weak{$text})) { + $ref_func = $text; + $read_function = 0; + $offset = hex $1; + } else { + # if we already have a function, and this is weak, skip it + if (!defined($ref_func) && !defined($weak{$text}) && + # PPC64 can have symbols that start with .L and + # gcc considers these special. Don't use them! + $text !~ /^\.L/) { + $ref_func = $text; + $offset = hex $1; + } + } + } + # is this a call site to mcount? If so, record it to print later + if ($text_found && /$mcount_regex/) { + push(@offsets, (hex $1) + $mcount_adjust); + } +} + +# dump out anymore offsets that may have been found +update_funcs(); + +# If we did not find any mcount callers, we are done (do nothing). +if (!$opened) { + exit(0); +} + +close(FILE); + +# +# Step 3: Compile the file that holds the list of call sites to mcount. +# +`$cc -o $mcount_o -c $mcount_s`; + +my @converts = keys %convert; + +# +# Step 4: Do we have sections that started with local functions? +# +if ($#converts >= 0) { + my $globallist = ""; + my $locallist = ""; + + foreach my $con (@converts) { + $globallist .= " --globalize-symbol $con"; + $locallist .= " --localize-symbol $con"; + } + + my $globalobj = $dirname . "/.tmp_gl_" . $filename; + my $globalmix = $dirname . "/.tmp_mx_" . $filename; + + # + # Step 5: set up each local function as a global + # + `$objcopy $globallist $inputfile $globalobj`; + + # + # Step 6: Link the global version to our list. + # + `$ld -r $globalobj $mcount_o -o $globalmix`; + + # + # Step 7: Convert the local functions back into local symbols + # + `$objcopy $locallist $globalmix $inputfile`; + + # Remove the temp files + `$rm $globalobj $globalmix`; + +} else { + + my $mix = $dirname . "/.tmp_mx_" . $filename; + + # + # Step 8: Link the object with our list of call sites object. + # + `$ld -r $inputfile $mcount_o -o $mix`; + + # + # Step 9: Move the result back to the original object. + # + `$mv $mix $inputfile`; +} + +# Clean up the temp files +`$rm $mcount_o $mcount_s`; + +exit(0); diff --git a/src/net/scripts/selinux/Makefile b/src/net/scripts/selinux/Makefile new file mode 100644 index 0000000..59494e1 --- /dev/null +++ b/src/net/scripts/selinux/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +subdir-y := mdp genheaders diff --git a/src/net/scripts/selinux/README b/src/net/scripts/selinux/README new file mode 100644 index 0000000..5ba679c --- /dev/null +++ b/src/net/scripts/selinux/README @@ -0,0 +1,2 @@ +Please see Documentation/admin-guide/LSM/SELinux.rst for information on +installing a dummy SELinux policy. diff --git a/src/net/scripts/selinux/genheaders/.gitignore b/src/net/scripts/selinux/genheaders/.gitignore new file mode 100644 index 0000000..5fcadd3 --- /dev/null +++ b/src/net/scripts/selinux/genheaders/.gitignore @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +genheaders diff --git a/src/net/scripts/selinux/genheaders/Makefile b/src/net/scripts/selinux/genheaders/Makefile new file mode 100644 index 0000000..1faf7f0 --- /dev/null +++ b/src/net/scripts/selinux/genheaders/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0 +hostprogs-always-y += genheaders +HOST_EXTRACFLAGS += \ + -I$(srctree)/include/uapi -I$(srctree)/include \ + -I$(srctree)/security/selinux/include diff --git a/src/net/scripts/selinux/genheaders/genheaders.c b/src/net/scripts/selinux/genheaders/genheaders.c new file mode 100644 index 0000000..f355b3e --- /dev/null +++ b/src/net/scripts/selinux/genheaders/genheaders.c @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* NOTE: we really do want to use the kernel headers here */ +#define __EXPORTED_HEADERS__ + +#include <stdio.h> +#include <stdlib.h> +#include <unistd.h> +#include <string.h> +#include <errno.h> +#include <ctype.h> + +struct security_class_mapping { + const char *name; + const char *perms[sizeof(unsigned) * 8 + 1]; +}; + +#include "classmap.h" +#include "initial_sid_to_string.h" + +const char *progname; + +static void usage(void) +{ + printf("usage: %s flask.h av_permissions.h\n", progname); + exit(1); +} + +static char *stoupperx(const char *s) +{ + char *s2 = strdup(s); + char *p; + + if (!s2) { + fprintf(stderr, "%s: out of memory\n", progname); + exit(3); + } + + for (p = s2; *p; p++) + *p = toupper(*p); + return s2; +} + +int main(int argc, char *argv[]) +{ + int i, j; + int isids_len; + FILE *fout; + + progname = argv[0]; + + if (argc < 3) + usage(); + + fout = fopen(argv[1], "w"); + if (!fout) { + fprintf(stderr, "Could not open %s for writing: %s\n", + argv[1], strerror(errno)); + exit(2); + } + + for (i = 0; secclass_map[i].name; i++) { + struct security_class_mapping *map = &secclass_map[i]; + map->name = stoupperx(map->name); + for (j = 0; map->perms[j]; j++) + map->perms[j] = stoupperx(map->perms[j]); + } + + isids_len = sizeof(initial_sid_to_string) / sizeof (char *); + for (i = 1; i < isids_len; i++) { + const char *s = initial_sid_to_string[i]; + + if (s) + initial_sid_to_string[i] = stoupperx(s); + } + + fprintf(fout, "/* This file is automatically generated. Do not edit. */\n"); + fprintf(fout, "#ifndef _SELINUX_FLASK_H_\n#define _SELINUX_FLASK_H_\n\n"); + + for (i = 0; secclass_map[i].name; i++) { + struct security_class_mapping *map = &secclass_map[i]; + fprintf(fout, "#define SECCLASS_%-39s %2d\n", map->name, i+1); + } + + fprintf(fout, "\n"); + + for (i = 1; i < isids_len; i++) { + const char *s = initial_sid_to_string[i]; + if (s) + fprintf(fout, "#define SECINITSID_%-39s %2d\n", s, i); + } + fprintf(fout, "\n#define SECINITSID_NUM %d\n", i-1); + fprintf(fout, "\nstatic inline bool security_is_socket_class(u16 kern_tclass)\n"); + fprintf(fout, "{\n"); + fprintf(fout, "\tbool sock = false;\n\n"); + fprintf(fout, "\tswitch (kern_tclass) {\n"); + for (i = 0; secclass_map[i].name; i++) { + static char s[] = "SOCKET"; + struct security_class_mapping *map = &secclass_map[i]; + int len = strlen(map->name), l = sizeof(s) - 1; + if (len >= l && memcmp(map->name + len - l, s, l) == 0) + fprintf(fout, "\tcase SECCLASS_%s:\n", map->name); + } + fprintf(fout, "\t\tsock = true;\n"); + fprintf(fout, "\t\tbreak;\n"); + fprintf(fout, "\tdefault:\n"); + fprintf(fout, "\t\tbreak;\n"); + fprintf(fout, "\t}\n\n"); + fprintf(fout, "\treturn sock;\n"); + fprintf(fout, "}\n"); + + fprintf(fout, "\n#endif\n"); + fclose(fout); + + fout = fopen(argv[2], "w"); + if (!fout) { + fprintf(stderr, "Could not open %s for writing: %s\n", + argv[2], strerror(errno)); + exit(4); + } + + fprintf(fout, "/* This file is automatically generated. Do not edit. */\n"); + fprintf(fout, "#ifndef _SELINUX_AV_PERMISSIONS_H_\n#define _SELINUX_AV_PERMISSIONS_H_\n\n"); + + for (i = 0; secclass_map[i].name; i++) { + struct security_class_mapping *map = &secclass_map[i]; + int len = strlen(map->name); + for (j = 0; map->perms[j]; j++) { + if (j >= 32) { + fprintf(stderr, "Too many permissions to fit into an access vector at (%s, %s).\n", + map->name, map->perms[j]); + exit(5); + } + fprintf(fout, "#define %s__%-*s 0x%08xU\n", map->name, + 39-len, map->perms[j], 1U<<j); + } + } + + fprintf(fout, "\n#endif\n"); + fclose(fout); + exit(0); +} diff --git a/src/net/scripts/selinux/install_policy.sh b/src/net/scripts/selinux/install_policy.sh new file mode 100755 index 0000000..2dccf14 --- /dev/null +++ b/src/net/scripts/selinux/install_policy.sh @@ -0,0 +1,85 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0 +set -e +if [ `id -u` -ne 0 ]; then + echo "$0: must be root to install the selinux policy" + exit 1 +fi + +SF=`which setfiles` +if [ $? -eq 1 ]; then + echo "Could not find setfiles" + echo "Do you have policycoreutils installed?" + exit 1 +fi + +CP=`which checkpolicy` +if [ $? -eq 1 ]; then + echo "Could not find checkpolicy" + echo "Do you have checkpolicy installed?" + exit 1 +fi +VERS=`$CP -V | awk '{print $1}'` + +ENABLED=`which selinuxenabled` +if [ $? -eq 1 ]; then + echo "Could not find selinuxenabled" + echo "Do you have libselinux-utils installed?" + exit 1 +fi + +if selinuxenabled; then + echo "SELinux is already enabled" + echo "This prevents safely relabeling all files." + echo "Boot with selinux=0 on the kernel command-line or" + echo "SELINUX=disabled in /etc/selinux/config." + exit 1 +fi + +cd mdp +./mdp -m policy.conf file_contexts +$CP -U allow -M -o policy.$VERS policy.conf + +mkdir -p /etc/selinux/dummy/policy +mkdir -p /etc/selinux/dummy/contexts/files + +echo "__default__:user_u:s0" > /etc/selinux/dummy/seusers +echo "base_r:base_t:s0" > /etc/selinux/dummy/contexts/failsafe_context +echo "base_r:base_t:s0 base_r:base_t:s0" > /etc/selinux/dummy/default_contexts +cat > /etc/selinux/dummy/contexts/x_contexts <<EOF +client * user_u:base_r:base_t:s0 +property * user_u:object_r:base_t:s0 +extension * user_u:object_r:base_t:s0 +selection * user_u:object_r:base_t:s0 +event * user_u:object_r:base_t:s0 +EOF +touch /etc/selinux/dummy/contexts/virtual_domain_context +touch /etc/selinux/dummy/contexts/virtual_image_context + +cp file_contexts /etc/selinux/dummy/contexts/files +cp dbus_contexts /etc/selinux/dummy/contexts +cp policy.$VERS /etc/selinux/dummy/policy +FC_FILE=/etc/selinux/dummy/contexts/files/file_contexts + +if [ ! -d /etc/selinux ]; then + mkdir -p /etc/selinux +fi +if [ -f /etc/selinux/config ]; then + echo "/etc/selinux/config exists, moving to /etc/selinux/config.bak." + mv /etc/selinux/config /etc/selinux/config.bak +fi +echo "Creating new /etc/selinux/config for dummy policy." +cat > /etc/selinux/config << EOF +SELINUX=permissive +SELINUXTYPE=dummy +EOF + +cd /etc/selinux/dummy/contexts/files +$SF -F file_contexts / + +mounts=`cat /proc/$$/mounts | \ + egrep "ext[234]|jfs|xfs|reiserfs|jffs2|gfs2|btrfs|f2fs|ocfs2" | \ + awk '{ print $2 '}` +$SF -F file_contexts $mounts + +echo "-F" > /.autorelabel diff --git a/src/net/scripts/selinux/mdp/.gitignore b/src/net/scripts/selinux/mdp/.gitignore new file mode 100644 index 0000000..a748228 --- /dev/null +++ b/src/net/scripts/selinux/mdp/.gitignore @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +mdp diff --git a/src/net/scripts/selinux/mdp/Makefile b/src/net/scripts/selinux/mdp/Makefile new file mode 100644 index 0000000..d61058d --- /dev/null +++ b/src/net/scripts/selinux/mdp/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0 +hostprogs-always-y += mdp +HOST_EXTRACFLAGS += \ + -I$(srctree)/include/uapi -I$(srctree)/include \ + -I$(srctree)/security/selinux/include -I$(objtree)/include + +clean-files := policy.* file_contexts diff --git a/src/net/scripts/selinux/mdp/dbus_contexts b/src/net/scripts/selinux/mdp/dbus_contexts new file mode 100644 index 0000000..116e684 --- /dev/null +++ b/src/net/scripts/selinux/mdp/dbus_contexts @@ -0,0 +1,6 @@ +<!DOCTYPE busconfig PUBLIC "-//freedesktop//DTD D-BUS Bus Configuration 1.0//EN" + "http://www.freedesktop.org/standards/dbus/1.0/busconfig.dtd"> +<busconfig> + <selinux> + </selinux> +</busconfig> diff --git a/src/net/scripts/selinux/mdp/mdp.c b/src/net/scripts/selinux/mdp/mdp.c new file mode 100644 index 0000000..105c1c3 --- /dev/null +++ b/src/net/scripts/selinux/mdp/mdp.c @@ -0,0 +1,273 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * + * mdp - make dummy policy + * + * When pointed at a kernel tree, builds a dummy policy for that kernel + * with exactly one type with full rights to itself. + * + * Copyright (C) IBM Corporation, 2006 + * + * Authors: Serge E. Hallyn <serue@us.ibm.com> + */ + + +/* NOTE: we really do want to use the kernel headers here */ +#define __EXPORTED_HEADERS__ + +#include <stdio.h> +#include <stdlib.h> +#include <unistd.h> +#include <string.h> +#include <linux/kconfig.h> + +static void usage(char *name) +{ + printf("usage: %s [-m] policy_file context_file\n", name); + exit(1); +} + +/* Class/perm mapping support */ +struct security_class_mapping { + const char *name; + const char *perms[sizeof(unsigned) * 8 + 1]; +}; + +#include "classmap.h" +#include "initial_sid_to_string.h" +#include "policycap_names.h" + +#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) + +int main(int argc, char *argv[]) +{ + int i, j, mls = 0; + int initial_sid_to_string_len; + char **arg, *polout, *ctxout; + + FILE *fout; + + if (argc < 3) + usage(argv[0]); + arg = argv+1; + if (argc==4 && strcmp(argv[1], "-m") == 0) { + mls = 1; + arg++; + } + polout = *arg++; + ctxout = *arg; + + fout = fopen(polout, "w"); + if (!fout) { + printf("Could not open %s for writing\n", polout); + usage(argv[0]); + } + + /* print out the classes */ + for (i = 0; secclass_map[i].name; i++) + fprintf(fout, "class %s\n", secclass_map[i].name); + fprintf(fout, "\n"); + + initial_sid_to_string_len = sizeof(initial_sid_to_string) / sizeof (char *); + /* print out the sids */ + for (i = 1; i < initial_sid_to_string_len; i++) { + const char *name = initial_sid_to_string[i]; + + if (name) + fprintf(fout, "sid %s\n", name); + else + fprintf(fout, "sid unused%d\n", i); + } + fprintf(fout, "\n"); + + /* print out the class permissions */ + for (i = 0; secclass_map[i].name; i++) { + struct security_class_mapping *map = &secclass_map[i]; + fprintf(fout, "class %s\n", map->name); + fprintf(fout, "{\n"); + for (j = 0; map->perms[j]; j++) + fprintf(fout, "\t%s\n", map->perms[j]); + fprintf(fout, "}\n\n"); + } + fprintf(fout, "\n"); + + /* print out mls declarations and constraints */ + if (mls) { + fprintf(fout, "sensitivity s0;\n"); + fprintf(fout, "sensitivity s1;\n"); + fprintf(fout, "dominance { s0 s1 }\n"); + fprintf(fout, "category c0;\n"); + fprintf(fout, "category c1;\n"); + fprintf(fout, "level s0:c0.c1;\n"); + fprintf(fout, "level s1:c0.c1;\n"); +#define SYSTEMLOW "s0" +#define SYSTEMHIGH "s1:c0.c1" + for (i = 0; secclass_map[i].name; i++) { + struct security_class_mapping *map = &secclass_map[i]; + + fprintf(fout, "mlsconstrain %s {\n", map->name); + for (j = 0; map->perms[j]; j++) + fprintf(fout, "\t%s\n", map->perms[j]); + /* + * This requires all subjects and objects to be + * single-level (l2 eq h2), and that the subject + * level dominate the object level (h1 dom h2) + * in order to have any permissions to it. + */ + fprintf(fout, "} (l2 eq h2 and h1 dom h2);\n\n"); + } + } + + /* enable all policy capabilities */ + for (i = 0; i < ARRAY_SIZE(selinux_policycap_names); i++) + fprintf(fout, "policycap %s;\n", selinux_policycap_names[i]); + + /* types, roles, and allows */ + fprintf(fout, "type base_t;\n"); + fprintf(fout, "role base_r;\n"); + fprintf(fout, "role base_r types { base_t };\n"); + for (i = 0; secclass_map[i].name; i++) + fprintf(fout, "allow base_t base_t:%s *;\n", + secclass_map[i].name); + fprintf(fout, "user user_u roles { base_r }"); + if (mls) + fprintf(fout, " level %s range %s - %s", SYSTEMLOW, + SYSTEMLOW, SYSTEMHIGH); + fprintf(fout, ";\n"); + +#define SUBJUSERROLETYPE "user_u:base_r:base_t" +#define OBJUSERROLETYPE "user_u:object_r:base_t" + + /* default sids */ + for (i = 1; i < initial_sid_to_string_len; i++) { + const char *name = initial_sid_to_string[i]; + + if (name) + fprintf(fout, "sid %s ", name); + else + fprintf(fout, "sid unused%d\n", i); + fprintf(fout, SUBJUSERROLETYPE "%s\n", + mls ? ":" SYSTEMLOW : ""); + } + fprintf(fout, "\n"); + +#define FS_USE(behavior, fstype) \ + fprintf(fout, "fs_use_%s %s " OBJUSERROLETYPE "%s;\n", \ + behavior, fstype, mls ? ":" SYSTEMLOW : "") + + /* + * Filesystems whose inode labels can be fetched via getxattr. + */ +#ifdef CONFIG_EXT2_FS_SECURITY + FS_USE("xattr", "ext2"); +#endif +#ifdef CONFIG_EXT4_FS_SECURITY +#ifdef CONFIG_EXT4_USE_FOR_EXT2 + FS_USE("xattr", "ext2"); +#endif + FS_USE("xattr", "ext3"); + FS_USE("xattr", "ext4"); +#endif +#ifdef CONFIG_JFS_SECURITY + FS_USE("xattr", "jfs"); +#endif +#ifdef CONFIG_REISERFS_FS_SECURITY + FS_USE("xattr", "reiserfs"); +#endif +#ifdef CONFIG_JFFS2_FS_SECURITY + FS_USE("xattr", "jffs2"); +#endif +#ifdef CONFIG_XFS_FS + FS_USE("xattr", "xfs"); +#endif +#ifdef CONFIG_GFS2_FS + FS_USE("xattr", "gfs2"); +#endif +#ifdef CONFIG_BTRFS_FS + FS_USE("xattr", "btrfs"); +#endif +#ifdef CONFIG_F2FS_FS_SECURITY + FS_USE("xattr", "f2fs"); +#endif +#ifdef CONFIG_OCFS2_FS + FS_USE("xattr", "ocsfs2"); +#endif +#ifdef CONFIG_OVERLAY_FS + FS_USE("xattr", "overlay"); +#endif +#ifdef CONFIG_SQUASHFS_XATTR + FS_USE("xattr", "squashfs"); +#endif + + /* + * Filesystems whose inodes are labeled from allocating task. + */ + FS_USE("task", "pipefs"); + FS_USE("task", "sockfs"); + + /* + * Filesystems whose inode labels are computed from both + * the allocating task and the superblock label. + */ +#ifdef CONFIG_UNIX98_PTYS + FS_USE("trans", "devpts"); +#endif +#ifdef CONFIG_HUGETLBFS + FS_USE("trans", "hugetlbfs"); +#endif +#ifdef CONFIG_TMPFS + FS_USE("trans", "tmpfs"); +#endif +#ifdef CONFIG_DEVTMPFS + FS_USE("trans", "devtmpfs"); +#endif +#ifdef CONFIG_POSIX_MQUEUE + FS_USE("trans", "mqueue"); +#endif + +#define GENFSCON(fstype, prefix) \ + fprintf(fout, "genfscon %s %s " OBJUSERROLETYPE "%s\n", \ + fstype, prefix, mls ? ":" SYSTEMLOW : "") + + /* + * Filesystems whose inodes are labeled from path prefix match + * relative to the filesystem root. Depending on the filesystem, + * only a single label for all inodes may be supported. Here + * we list the filesystem types for which per-file labeling is + * supported using genfscon; any other filesystem type can also + * be added by only with a single entry for all of its inodes. + */ +#ifdef CONFIG_PROC_FS + GENFSCON("proc", "/"); +#endif +#ifdef CONFIG_SECURITY_SELINUX + GENFSCON("selinuxfs", "/"); +#endif +#ifdef CONFIG_SYSFS + GENFSCON("sysfs", "/"); +#endif +#ifdef CONFIG_DEBUG_FS + GENFSCON("debugfs", "/"); +#endif +#ifdef CONFIG_TRACING + GENFSCON("tracefs", "/"); +#endif +#ifdef CONFIG_PSTORE + GENFSCON("pstore", "/"); +#endif + GENFSCON("cgroup", "/"); + GENFSCON("cgroup2", "/"); + + fclose(fout); + + fout = fopen(ctxout, "w"); + if (!fout) { + printf("Wrote policy, but cannot open %s for writing\n", ctxout); + usage(argv[0]); + } + fprintf(fout, "/ " OBJUSERROLETYPE "%s\n", mls ? ":" SYSTEMLOW : ""); + fprintf(fout, "/.* " OBJUSERROLETYPE "%s\n", mls ? ":" SYSTEMLOW : ""); + fclose(fout); + + return 0; +} diff --git a/src/net/scripts/setlocalversion b/src/net/scripts/setlocalversion new file mode 100755 index 0000000..bb709ed --- /dev/null +++ b/src/net/scripts/setlocalversion @@ -0,0 +1,194 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0 +# +# This scripts adds local version information from the version +# control systems git, mercurial (hg) and subversion (svn). +# +# If something goes wrong, send a mail the kernel build mailinglist +# (see MAINTAINERS) and CC Nico Schottelius +# <nico-linuxsetlocalversion -at- schottelius.org>. +# +# + +usage() { + echo "Usage: $0 [--save-scmversion] [srctree]" >&2 + exit 1 +} + +scm_only=false +srctree=. +if test "$1" = "--save-scmversion"; then + scm_only=true + shift +fi +if test $# -gt 0; then + srctree=$1 + shift +fi +if test $# -gt 0 -o ! -d "$srctree"; then + usage +fi + +scm_version() +{ + local short + short=false + + cd "$srctree" + if test -e .scmversion; then + cat .scmversion + return + fi + if test "$1" = "--short"; then + short=true + fi + + # Check for git and a git repo. + if test -z "$(git rev-parse --show-cdup 2>/dev/null)" && + head=$(git rev-parse --verify HEAD 2>/dev/null); then + + # If we are at a tagged commit (like "v2.6.30-rc6"), we ignore + # it, because this version is defined in the top level Makefile. + if [ -z "$(git describe --exact-match 2>/dev/null)" ]; then + + # If only the short version is requested, don't bother + # running further git commands + if $short; then + echo "+" + return + fi + # If we are past a tagged commit (like + # "v2.6.30-rc5-302-g72357d5"), we pretty print it. + # + # Ensure the abbreviated sha1 has exactly 12 + # hex characters, to make the output + # independent of git version, local + # core.abbrev settings and/or total number of + # objects in the current repository - passing + # --abbrev=12 ensures a minimum of 12, and the + # awk substr() then picks the 'g' and first 12 + # hex chars. + if atag="$(git describe --abbrev=12 2>/dev/null)"; then + echo "$atag" | awk -F- '{printf("-%05d-%s", $(NF-1),substr($(NF),0,13))}' + + # If we don't have a tag at all we print -g{commitish}, + # again using exactly 12 hex chars. + else + head="$(echo $head | cut -c1-12)" + printf '%s%s' -g $head + fi + fi + + # Is this git on svn? + if git config --get svn-remote.svn.url >/dev/null; then + printf -- '-svn%s' "$(git svn find-rev $head)" + fi + + # Check for uncommitted changes. + # First, with git-status, but --no-optional-locks is only + # supported in git >= 2.14, so fall back to git-diff-index if + # it fails. Note that git-diff-index does not refresh the + # index, so it may give misleading results. See + # git-update-index(1), git-diff-index(1), and git-status(1). + if { + git --no-optional-locks status -uno --porcelain 2>/dev/null || + git diff-index --name-only HEAD + } | grep -qvE '^(.. )?scripts/package'; then + printf '%s' -dirty + fi + + # All done with git + return + fi + + # Check for mercurial and a mercurial repo. + if test -d .hg && hgid=$(hg id 2>/dev/null); then + # Do we have an tagged version? If so, latesttagdistance == 1 + if [ "$(hg log -r . --template '{latesttagdistance}')" = "1" ]; then + id=$(hg log -r . --template '{latesttag}') + printf '%s%s' -hg "$id" + else + tag=$(printf '%s' "$hgid" | cut -d' ' -f2) + if [ -z "$tag" -o "$tag" = tip ]; then + id=$(printf '%s' "$hgid" | sed 's/[+ ].*//') + printf '%s%s' -hg "$id" + fi + fi + + # Are there uncommitted changes? + # These are represented by + after the changeset id. + case "$hgid" in + *+|*+\ *) printf '%s' -dirty ;; + esac + + # All done with mercurial + return + fi + + # Check for svn and a svn repo. + if rev=$(LANG= LC_ALL= LC_MESSAGES=C svn info 2>/dev/null | grep '^Last Changed Rev'); then + rev=$(echo $rev | awk '{print $NF}') + printf -- '-svn%s' "$rev" + + # All done with svn + return + fi +} + +collect_files() +{ + local file res= + + for file; do + case "$file" in + *\~*) + continue + ;; + esac + if test -e "$file"; then + res="$res$(cat "$file")" + fi + done + echo "$res" +} + +if $scm_only; then + if test ! -e .scmversion; then + res=$(scm_version) + echo "$res" >.scmversion + fi + exit +fi + +if test -e include/config/auto.conf; then + . include/config/auto.conf +else + echo "Error: kernelrelease not valid - run 'make prepare' to update it" >&2 + exit 1 +fi + +# localversion* files in the build and source directory +res="$(collect_files localversion*)" +if test ! "$srctree" -ef .; then + res="$res$(collect_files "$srctree"/localversion*)" +fi + +# CONFIG_LOCALVERSION and LOCALVERSION (if set) +res="${res}${CONFIG_LOCALVERSION}${LOCALVERSION}" + +# scm version string if not at a tagged commit +if test "$CONFIG_LOCALVERSION_AUTO" = "y"; then + # full scm version string + res="$res$(scm_version)" +else + # append a plus sign if the repository is not in a clean + # annotated or signed tagged state (as git describe only + # looks at signed or annotated tags - git tag -a/-s) and + # LOCALVERSION= is not specified + if test "${LOCALVERSION+set}" != "set"; then + scm=$(scm_version --short) + res="$res${scm:++}" + fi +fi + +echo "$res" diff --git a/src/net/scripts/show_delta b/src/net/scripts/show_delta new file mode 100755 index 0000000..28e67e1 --- /dev/null +++ b/src/net/scripts/show_delta @@ -0,0 +1,128 @@ +#!/usr/bin/env python +# SPDX-License-Identifier: GPL-2.0-only +# +# show_deltas: Read list of printk messages instrumented with +# time data, and format with time deltas. +# +# Also, you can show the times relative to a fixed point. +# +# Copyright 2003 Sony Corporation +# + +import sys +import string + +def usage(): + print ("""usage: show_delta [<options>] <filename> + +This program parses the output from a set of printk message lines which +have time data prefixed because the CONFIG_PRINTK_TIME option is set, or +the kernel command line option "time" is specified. When run with no +options, the time information is converted to show the time delta between +each printk line and the next. When run with the '-b' option, all times +are relative to a single (base) point in time. + +Options: + -h Show this usage help. + -b <base> Specify a base for time references. + <base> can be a number or a string. + If it is a string, the first message line + which matches (at the beginning of the + line) is used as the time reference. + +ex: $ dmesg >timefile + $ show_delta -b NET4 timefile + +will show times relative to the line in the kernel output +starting with "NET4". +""") + sys.exit(1) + +# returns a tuple containing the seconds and text for each message line +# seconds is returned as a float +# raise an exception if no timing data was found +def get_time(line): + if line[0]!="[": + raise ValueError + + # split on closing bracket + (time_str, rest) = string.split(line[1:],']',1) + time = string.atof(time_str) + + #print "time=", time + return (time, rest) + + +# average line looks like: +# [ 0.084282] VFS: Mounted root (romfs filesystem) readonly +# time data is expressed in seconds.useconds, +# convert_line adds a delta for each line +last_time = 0.0 +def convert_line(line, base_time): + global last_time + + try: + (time, rest) = get_time(line) + except: + # if any problem parsing time, don't convert anything + return line + + if base_time: + # show time from base + delta = time - base_time + else: + # just show time from last line + delta = time - last_time + last_time = time + + return ("[%5.6f < %5.6f >]" % (time, delta)) + rest + +def main(): + base_str = "" + filein = "" + for arg in sys.argv[1:]: + if arg=="-b": + base_str = sys.argv[sys.argv.index("-b")+1] + elif arg=="-h": + usage() + else: + filein = arg + + if not filein: + usage() + + try: + lines = open(filein,"r").readlines() + except: + print ("Problem opening file: %s" % filein) + sys.exit(1) + + if base_str: + print ('base= "%s"' % base_str) + # assume a numeric base. If that fails, try searching + # for a matching line. + try: + base_time = float(base_str) + except: + # search for line matching <base> string + found = 0 + for line in lines: + try: + (time, rest) = get_time(line) + except: + continue + if string.find(rest, base_str)==1: + base_time = time + found = 1 + # stop at first match + break + if not found: + print ('Couldn\'t find line matching base pattern "%s"' % base_str) + sys.exit(1) + else: + base_time = 0.0 + + for line in lines: + print (convert_line(line, base_time),) + +main() diff --git a/src/net/scripts/sign-file.c b/src/net/scripts/sign-file.c new file mode 100644 index 0000000..77bc5d2 --- /dev/null +++ b/src/net/scripts/sign-file.c @@ -0,0 +1,423 @@ +/* Sign a module file using the given key. + * + * Copyright © 2014-2016 Red Hat, Inc. All Rights Reserved. + * Copyright © 2015 Intel Corporation. + * Copyright © 2016 Hewlett Packard Enterprise Development LP + * + * Authors: David Howells <dhowells@redhat.com> + * David Woodhouse <dwmw2@infradead.org> + * Juerg Haefliger <juerg.haefliger@hpe.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public License + * as published by the Free Software Foundation; either version 2.1 + * of the licence, or (at your option) any later version. + */ +#define _GNU_SOURCE +#include <stdio.h> +#include <stdlib.h> +#include <stdint.h> +#include <stdbool.h> +#include <string.h> +#include <getopt.h> +#include <err.h> +#include <arpa/inet.h> +#include <openssl/opensslv.h> +#include <openssl/bio.h> +#include <openssl/evp.h> +#include <openssl/pem.h> +#include <openssl/err.h> +#include <openssl/engine.h> + +/* + * Use CMS if we have openssl-1.0.0 or newer available - otherwise we have to + * assume that it's not available and its header file is missing and that we + * should use PKCS#7 instead. Switching to the older PKCS#7 format restricts + * the options we have on specifying the X.509 certificate we want. + * + * Further, older versions of OpenSSL don't support manually adding signers to + * the PKCS#7 message so have to accept that we get a certificate included in + * the signature message. Nor do such older versions of OpenSSL support + * signing with anything other than SHA1 - so we're stuck with that if such is + * the case. + */ +#if defined(LIBRESSL_VERSION_NUMBER) || \ + OPENSSL_VERSION_NUMBER < 0x10000000L || \ + defined(OPENSSL_NO_CMS) +#define USE_PKCS7 +#endif +#ifndef USE_PKCS7 +#include <openssl/cms.h> +#else +#include <openssl/pkcs7.h> +#endif + +struct module_signature { + uint8_t algo; /* Public-key crypto algorithm [0] */ + uint8_t hash; /* Digest algorithm [0] */ + uint8_t id_type; /* Key identifier type [PKEY_ID_PKCS7] */ + uint8_t signer_len; /* Length of signer's name [0] */ + uint8_t key_id_len; /* Length of key identifier [0] */ + uint8_t __pad[3]; + uint32_t sig_len; /* Length of signature data */ +}; + +#define PKEY_ID_PKCS7 2 + +static char magic_number[] = "~Module signature appended~\n"; + +static __attribute__((noreturn)) +void format(void) +{ + fprintf(stderr, + "Usage: scripts/sign-file [-dp] <hash algo> <key> <x509> <module> [<dest>]\n"); + fprintf(stderr, + " scripts/sign-file -s <raw sig> <hash algo> <x509> <module> [<dest>]\n"); + exit(2); +} + +static void display_openssl_errors(int l) +{ + const char *file; + char buf[120]; + int e, line; + + if (ERR_peek_error() == 0) + return; + fprintf(stderr, "At main.c:%d:\n", l); + + while ((e = ERR_get_error_line(&file, &line))) { + ERR_error_string(e, buf); + fprintf(stderr, "- SSL %s: %s:%d\n", buf, file, line); + } +} + +static void drain_openssl_errors(void) +{ + const char *file; + int line; + + if (ERR_peek_error() == 0) + return; + while (ERR_get_error_line(&file, &line)) {} +} + +#define ERR(cond, fmt, ...) \ + do { \ + bool __cond = (cond); \ + display_openssl_errors(__LINE__); \ + if (__cond) { \ + errx(1, fmt, ## __VA_ARGS__); \ + } \ + } while(0) + +static const char *key_pass; + +static int pem_pw_cb(char *buf, int len, int w, void *v) +{ + int pwlen; + + if (!key_pass) + return -1; + + pwlen = strlen(key_pass); + if (pwlen >= len) + return -1; + + strcpy(buf, key_pass); + + /* If it's wrong, don't keep trying it. */ + key_pass = NULL; + + return pwlen; +} + +static EVP_PKEY *read_private_key(const char *private_key_name) +{ + EVP_PKEY *private_key; + + if (!strncmp(private_key_name, "pkcs11:", 7)) { + ENGINE *e; + + ENGINE_load_builtin_engines(); + drain_openssl_errors(); + e = ENGINE_by_id("pkcs11"); + ERR(!e, "Load PKCS#11 ENGINE"); + if (ENGINE_init(e)) + drain_openssl_errors(); + else + ERR(1, "ENGINE_init"); + if (key_pass) + ERR(!ENGINE_ctrl_cmd_string(e, "PIN", key_pass, 0), + "Set PKCS#11 PIN"); + private_key = ENGINE_load_private_key(e, private_key_name, + NULL, NULL); + ERR(!private_key, "%s", private_key_name); + } else { + BIO *b; + + b = BIO_new_file(private_key_name, "rb"); + ERR(!b, "%s", private_key_name); + private_key = PEM_read_bio_PrivateKey(b, NULL, pem_pw_cb, + NULL); + ERR(!private_key, "%s", private_key_name); + BIO_free(b); + } + + return private_key; +} + +static X509 *read_x509(const char *x509_name) +{ + unsigned char buf[2]; + X509 *x509; + BIO *b; + int n; + + b = BIO_new_file(x509_name, "rb"); + ERR(!b, "%s", x509_name); + + /* Look at the first two bytes of the file to determine the encoding */ + n = BIO_read(b, buf, 2); + if (n != 2) { + if (BIO_should_retry(b)) { + fprintf(stderr, "%s: Read wanted retry\n", x509_name); + exit(1); + } + if (n >= 0) { + fprintf(stderr, "%s: Short read\n", x509_name); + exit(1); + } + ERR(1, "%s", x509_name); + } + + ERR(BIO_reset(b) != 0, "%s", x509_name); + + if (buf[0] == 0x30 && buf[1] >= 0x81 && buf[1] <= 0x84) + /* Assume raw DER encoded X.509 */ + x509 = d2i_X509_bio(b, NULL); + else + /* Assume PEM encoded X.509 */ + x509 = PEM_read_bio_X509(b, NULL, NULL, NULL); + + BIO_free(b); + ERR(!x509, "%s", x509_name); + + return x509; +} + +int main(int argc, char **argv) +{ + struct module_signature sig_info = { .id_type = PKEY_ID_PKCS7 }; + char *hash_algo = NULL; + char *private_key_name = NULL, *raw_sig_name = NULL; + char *x509_name, *module_name, *dest_name; + bool save_sig = false, replace_orig; + bool sign_only = false; + bool raw_sig = false; + unsigned char buf[4096]; + unsigned long module_size, sig_size; + unsigned int use_signed_attrs; + const EVP_MD *digest_algo; + EVP_PKEY *private_key; +#if defined(EVP_PKEY_SM2) && OPENSSL_VERSION_NUMBER < 0x30000000 + EVP_PKEY *pkey; +#endif +#ifndef USE_PKCS7 + CMS_ContentInfo *cms = NULL; + unsigned int use_keyid = 0; +#else + PKCS7 *pkcs7 = NULL; +#endif + X509 *x509; + BIO *bd, *bm; + int opt, n; + OpenSSL_add_all_algorithms(); + ERR_load_crypto_strings(); + ERR_clear_error(); + + key_pass = getenv("KBUILD_SIGN_PIN"); + +#ifndef USE_PKCS7 + use_signed_attrs = CMS_NOATTR; +#else + use_signed_attrs = PKCS7_NOATTR; +#endif + + do { + opt = getopt(argc, argv, "sdpk"); + switch (opt) { + case 's': raw_sig = true; break; + case 'p': save_sig = true; break; + case 'd': sign_only = true; save_sig = true; break; +#ifndef USE_PKCS7 + case 'k': use_keyid = CMS_USE_KEYID; break; +#endif + case -1: break; + default: format(); + } + } while (opt != -1); + + argc -= optind; + argv += optind; + if (argc < 4 || argc > 5) + format(); + + if (raw_sig) { + raw_sig_name = argv[0]; + hash_algo = argv[1]; + } else { + hash_algo = argv[0]; + private_key_name = argv[1]; + } + x509_name = argv[2]; + module_name = argv[3]; + if (argc == 5 && strcmp(argv[3], argv[4]) != 0) { + dest_name = argv[4]; + replace_orig = false; + } else { + ERR(asprintf(&dest_name, "%s.~signed~", module_name) < 0, + "asprintf"); + replace_orig = true; + } + +#ifdef USE_PKCS7 + if (strcmp(hash_algo, "sha1") != 0) { + fprintf(stderr, "sign-file: %s only supports SHA1 signing\n", + OPENSSL_VERSION_TEXT); + exit(3); + } +#endif + + /* Open the module file */ + bm = BIO_new_file(module_name, "rb"); + ERR(!bm, "%s", module_name); + + if (!raw_sig) { + /* Read the private key and the X.509 cert the PKCS#7 message + * will point to. + */ + private_key = read_private_key(private_key_name); + x509 = read_x509(x509_name); + + /* Digest the module data. */ + OpenSSL_add_all_digests(); + display_openssl_errors(__LINE__); + digest_algo = EVP_get_digestbyname(hash_algo); + ERR(!digest_algo, "EVP_get_digestbyname"); + +#if defined(EVP_PKEY_SM2) && OPENSSL_VERSION_NUMBER < 0x30000000 + /* If EC key are used, check whether it is SM2 key */ + if (EVP_PKEY_id(private_key) == EVP_PKEY_EC) { + EC_KEY *ec = EVP_PKEY_get0_EC_KEY(private_key); + int curve = EC_GROUP_get_curve_name(EC_KEY_get0_group(ec)); + + if (curve == NID_sm2) + EVP_PKEY_set_alias_type(private_key, EVP_PKEY_SM2); + } + + pkey = X509_get0_pubkey(x509); + /* If EC key are used, check whether it is SM2 key */ + if (EVP_PKEY_id(pkey) == EVP_PKEY_EC) { + EC_KEY *ec = EVP_PKEY_get0_EC_KEY(pkey); + int curve = EC_GROUP_get_curve_name(EC_KEY_get0_group(ec)); + + if (curve == NID_sm2) + EVP_PKEY_set_alias_type(pkey, EVP_PKEY_SM2); + } +#endif + +#ifndef USE_PKCS7 + /* Load the signature message from the digest buffer. */ + cms = CMS_sign(NULL, NULL, NULL, NULL, + CMS_NOCERTS | CMS_PARTIAL | CMS_BINARY | + CMS_DETACHED | CMS_STREAM); + ERR(!cms, "CMS_sign"); + + ERR(!CMS_add1_signer(cms, x509, private_key, digest_algo, + CMS_NOCERTS | CMS_BINARY | + CMS_NOSMIMECAP | use_keyid | + use_signed_attrs), + "CMS_add1_signer"); + ERR(CMS_final(cms, bm, NULL, CMS_NOCERTS | CMS_BINARY) < 0, + "CMS_final"); + +#else + pkcs7 = PKCS7_sign(x509, private_key, NULL, bm, + PKCS7_NOCERTS | PKCS7_BINARY | + PKCS7_DETACHED | use_signed_attrs); + ERR(!pkcs7, "PKCS7_sign"); +#endif + + if (save_sig) { + char *sig_file_name; + BIO *b; + + ERR(asprintf(&sig_file_name, "%s.p7s", module_name) < 0, + "asprintf"); + b = BIO_new_file(sig_file_name, "wb"); + ERR(!b, "%s", sig_file_name); +#ifndef USE_PKCS7 + ERR(i2d_CMS_bio_stream(b, cms, NULL, 0) < 0, + "%s", sig_file_name); +#else + ERR(i2d_PKCS7_bio(b, pkcs7) < 0, + "%s", sig_file_name); +#endif + BIO_free(b); + } + + if (sign_only) { + BIO_free(bm); + return 0; + } + } + + /* Open the destination file now so that we can shovel the module data + * across as we read it. + */ + bd = BIO_new_file(dest_name, "wb"); + ERR(!bd, "%s", dest_name); + + /* Append the marker and the PKCS#7 message to the destination file */ + ERR(BIO_reset(bm) < 0, "%s", module_name); + while ((n = BIO_read(bm, buf, sizeof(buf))), + n > 0) { + ERR(BIO_write(bd, buf, n) < 0, "%s", dest_name); + } + BIO_free(bm); + ERR(n < 0, "%s", module_name); + module_size = BIO_number_written(bd); + + if (!raw_sig) { +#ifndef USE_PKCS7 + ERR(i2d_CMS_bio_stream(bd, cms, NULL, 0) < 0, "%s", dest_name); +#else + ERR(i2d_PKCS7_bio(bd, pkcs7) < 0, "%s", dest_name); +#endif + } else { + BIO *b; + + /* Read the raw signature file and write the data to the + * destination file + */ + b = BIO_new_file(raw_sig_name, "rb"); + ERR(!b, "%s", raw_sig_name); + while ((n = BIO_read(b, buf, sizeof(buf))), n > 0) + ERR(BIO_write(bd, buf, n) < 0, "%s", dest_name); + BIO_free(b); + } + + sig_size = BIO_number_written(bd) - module_size; + sig_info.sig_len = htonl(sig_size); + ERR(BIO_write(bd, &sig_info, sizeof(sig_info)) < 0, "%s", dest_name); + ERR(BIO_write(bd, magic_number, sizeof(magic_number) - 1) < 0, "%s", dest_name); + + ERR(BIO_free(bd) < 0, "%s", dest_name); + + /* Finally, if we're signing in place, replace the original. */ + if (replace_orig) + ERR(rename(dest_name, module_name) < 0, "%s", dest_name); + + return 0; +} diff --git a/src/net/scripts/sorttable.c b/src/net/scripts/sorttable.c new file mode 100644 index 0000000..8028567 --- /dev/null +++ b/src/net/scripts/sorttable.c @@ -0,0 +1,485 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * sorttable.c: Sort the kernel's table + * + * Added ORC unwind tables sort support and other updates: + * Copyright (C) 1999-2019 Alibaba Group Holding Limited. by: + * Shile Zhang <shile.zhang@linux.alibaba.com> + * + * Copyright 2011 - 2012 Cavium, Inc. + * + * Based on code taken from recortmcount.c which is: + * + * Copyright 2009 John F. Reiser <jreiser@BitWagon.com>. All rights reserved. + * + * Restructured to fit Linux format, as well as other updates: + * Copyright 2010 Steven Rostedt <srostedt@redhat.com>, Red Hat Inc. + */ + +/* + * Strategy: alter the vmlinux file in-place. + */ + +#include <sys/types.h> +#include <sys/mman.h> +#include <sys/stat.h> +#include <getopt.h> +#include <elf.h> +#include <fcntl.h> +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <unistd.h> +#include <errno.h> +#include <pthread.h> + +#include <tools/be_byteshift.h> +#include <tools/le_byteshift.h> + +#ifndef EM_ARCOMPACT +#define EM_ARCOMPACT 93 +#endif + +#ifndef EM_XTENSA +#define EM_XTENSA 94 +#endif + +#ifndef EM_AARCH64 +#define EM_AARCH64 183 +#endif + +#ifndef EM_MICROBLAZE +#define EM_MICROBLAZE 189 +#endif + +#ifndef EM_ARCV2 +#define EM_ARCV2 195 +#endif + +#ifndef EM_LOONGARCH +#define EM_LOONGARCH 258 +#endif + +static uint32_t (*r)(const uint32_t *); +static uint16_t (*r2)(const uint16_t *); +static uint64_t (*r8)(const uint64_t *); +static void (*w)(uint32_t, uint32_t *); +static void (*w2)(uint16_t, uint16_t *); +static void (*w8)(uint64_t, uint64_t *); +typedef void (*table_sort_t)(char *, int); + +/* + * Get the whole file as a programming convenience in order to avoid + * malloc+lseek+read+free of many pieces. If successful, then mmap + * avoids copying unused pieces; else just read the whole file. + * Open for both read and write. + */ +static void *mmap_file(char const *fname, size_t *size) +{ + int fd; + struct stat sb; + void *addr = NULL; + + fd = open(fname, O_RDWR); + if (fd < 0) { + perror(fname); + return NULL; + } + if (fstat(fd, &sb) < 0) { + perror(fname); + goto out; + } + if (!S_ISREG(sb.st_mode)) { + fprintf(stderr, "not a regular file: %s\n", fname); + goto out; + } + + addr = mmap(0, sb.st_size, PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0); + if (addr == MAP_FAILED) { + fprintf(stderr, "Could not mmap file: %s\n", fname); + goto out; + } + + *size = sb.st_size; + +out: + close(fd); + return addr; +} + +static uint32_t rbe(const uint32_t *x) +{ + return get_unaligned_be32(x); +} + +static uint16_t r2be(const uint16_t *x) +{ + return get_unaligned_be16(x); +} + +static uint64_t r8be(const uint64_t *x) +{ + return get_unaligned_be64(x); +} + +static uint32_t rle(const uint32_t *x) +{ + return get_unaligned_le32(x); +} + +static uint16_t r2le(const uint16_t *x) +{ + return get_unaligned_le16(x); +} + +static uint64_t r8le(const uint64_t *x) +{ + return get_unaligned_le64(x); +} + +static void wbe(uint32_t val, uint32_t *x) +{ + put_unaligned_be32(val, x); +} + +static void w2be(uint16_t val, uint16_t *x) +{ + put_unaligned_be16(val, x); +} + +static void w8be(uint64_t val, uint64_t *x) +{ + put_unaligned_be64(val, x); +} + +static void wle(uint32_t val, uint32_t *x) +{ + put_unaligned_le32(val, x); +} + +static void w2le(uint16_t val, uint16_t *x) +{ + put_unaligned_le16(val, x); +} + +static void w8le(uint64_t val, uint64_t *x) +{ + put_unaligned_le64(val, x); +} + +/* + * Move reserved section indices SHN_LORESERVE..SHN_HIRESERVE out of + * the way to -256..-1, to avoid conflicting with real section + * indices. + */ +#define SPECIAL(i) ((i) - (SHN_HIRESERVE + 1)) + +static inline int is_shndx_special(unsigned int i) +{ + return i != SHN_XINDEX && i >= SHN_LORESERVE && i <= SHN_HIRESERVE; +} + +/* Accessor for sym->st_shndx, hides ugliness of "64k sections" */ +static inline unsigned int get_secindex(unsigned int shndx, + unsigned int sym_offs, + const Elf32_Word *symtab_shndx_start) +{ + if (is_shndx_special(shndx)) + return SPECIAL(shndx); + if (shndx != SHN_XINDEX) + return shndx; + return r(&symtab_shndx_start[sym_offs]); +} + +/* 32 bit and 64 bit are very similar */ +#include "sorttable.h" +#define SORTTABLE_64 +#include "sorttable.h" + +static int compare_relative_table(const void *a, const void *b) +{ + int32_t av = (int32_t)r(a); + int32_t bv = (int32_t)r(b); + + if (av < bv) + return -1; + if (av > bv) + return 1; + return 0; +} + +static void sort_relative_table(char *extab_image, int image_size) +{ + int i = 0; + + /* + * Do the same thing the runtime sort does, first normalize to + * being relative to the start of the section. + */ + while (i < image_size) { + uint32_t *loc = (uint32_t *)(extab_image + i); + w(r(loc) + i, loc); + i += 4; + } + + qsort(extab_image, image_size / 8, 8, compare_relative_table); + + /* Now denormalize. */ + i = 0; + while (i < image_size) { + uint32_t *loc = (uint32_t *)(extab_image + i); + w(r(loc) - i, loc); + i += 4; + } +} + +static void arm64_sort_relative_table(char *extab_image, int image_size) +{ + int i = 0; + + while (i < image_size) { + uint32_t *loc = (uint32_t *)(extab_image + i); + + w(r(loc) + i, loc); + w(r(loc + 1) + i + 4, loc + 1); + /* Don't touch the fixup type or data */ + + i += sizeof(uint32_t) * 3; + } + + qsort(extab_image, image_size / 12, 12, compare_relative_table); + + i = 0; + while (i < image_size) { + uint32_t *loc = (uint32_t *)(extab_image + i); + + w(r(loc) - i, loc); + w(r(loc + 1) - (i + 4), loc + 1); + /* Don't touch the fixup type or data */ + + i += sizeof(uint32_t) * 3; + } +} + +static void sort_relative_table_with_data(char *extab_image, int image_size) +{ + int i = 0; + + while (i < image_size) { + uint32_t *loc = (uint32_t *)(extab_image + i); + + w(r(loc) + i, loc); + w(r(loc + 1) + i + 4, loc + 1); + /* Don't touch the fixup type or data */ + + i += sizeof(uint32_t) * 3; + } + + qsort(extab_image, image_size / 12, 12, compare_relative_table); + + i = 0; + while (i < image_size) { + uint32_t *loc = (uint32_t *)(extab_image + i); + + w(r(loc) - i, loc); + w(r(loc + 1) - (i + 4), loc + 1); + /* Don't touch the fixup type or data */ + + i += sizeof(uint32_t) * 3; + } +} + +static void x86_sort_relative_table(char *extab_image, int image_size) +{ + int i = 0; + + while (i < image_size) { + uint32_t *loc = (uint32_t *)(extab_image + i); + + w(r(loc) + i, loc); + w(r(loc + 1) + i + 4, loc + 1); + /* Don't touch the fixup type */ + + i += sizeof(uint32_t) * 3; + } + + qsort(extab_image, image_size / 12, 12, compare_relative_table); + + i = 0; + while (i < image_size) { + uint32_t *loc = (uint32_t *)(extab_image + i); + + w(r(loc) - i, loc); + w(r(loc + 1) - (i + 4), loc + 1); + /* Don't touch the fixup type */ + + i += sizeof(uint32_t) * 3; + } +} + +static void s390_sort_relative_table(char *extab_image, int image_size) +{ + int i; + + for (i = 0; i < image_size; i += 16) { + char *loc = extab_image + i; + uint64_t handler; + + w(r((uint32_t *)loc) + i, (uint32_t *)loc); + w(r((uint32_t *)(loc + 4)) + (i + 4), (uint32_t *)(loc + 4)); + /* + * 0 is a special self-relative handler value, which means that + * handler should be ignored. It is safe, because it means that + * handler field points to itself, which should never happen. + * When creating extable-relative values, keep it as 0, since + * this should never occur either: it would mean that handler + * field points to the first extable entry. + */ + handler = r8((uint64_t *)(loc + 8)); + if (handler) + handler += i + 8; + w8(handler, (uint64_t *)(loc + 8)); + } + + qsort(extab_image, image_size / 16, 16, compare_relative_table); + + for (i = 0; i < image_size; i += 16) { + char *loc = extab_image + i; + uint64_t handler; + + w(r((uint32_t *)loc) - i, (uint32_t *)loc); + w(r((uint32_t *)(loc + 4)) - (i + 4), (uint32_t *)(loc + 4)); + handler = r8((uint64_t *)(loc + 8)); + if (handler) + handler -= i + 8; + w8(handler, (uint64_t *)(loc + 8)); + } +} + +static int do_file(char const *const fname, void *addr) +{ + int rc = -1; + Elf32_Ehdr *ehdr = addr; + table_sort_t custom_sort = NULL; + + switch (ehdr->e_ident[EI_DATA]) { + case ELFDATA2LSB: + r = rle; + r2 = r2le; + r8 = r8le; + w = wle; + w2 = w2le; + w8 = w8le; + break; + case ELFDATA2MSB: + r = rbe; + r2 = r2be; + r8 = r8be; + w = wbe; + w2 = w2be; + w8 = w8be; + break; + default: + fprintf(stderr, "unrecognized ELF data encoding %d: %s\n", + ehdr->e_ident[EI_DATA], fname); + return -1; + } + + if (memcmp(ELFMAG, ehdr->e_ident, SELFMAG) != 0 || + (r2(&ehdr->e_type) != ET_EXEC && r2(&ehdr->e_type) != ET_DYN) || + ehdr->e_ident[EI_VERSION] != EV_CURRENT) { + fprintf(stderr, "unrecognized ET_EXEC/ET_DYN file %s\n", fname); + return -1; + } + + switch (r2(&ehdr->e_machine)) { + case EM_386: + case EM_X86_64: + custom_sort = x86_sort_relative_table; + break; + case EM_LOONGARCH: + custom_sort = sort_relative_table_with_data; + break; + case EM_S390: + custom_sort = s390_sort_relative_table; + break; + case EM_AARCH64: + custom_sort = arm64_sort_relative_table; + break; + case EM_PARISC: + case EM_PPC: + case EM_PPC64: + custom_sort = sort_relative_table; + break; + case EM_ARCOMPACT: + case EM_ARCV2: + case EM_ARM: + case EM_MICROBLAZE: + case EM_MIPS: + case EM_XTENSA: + break; + default: + fprintf(stderr, "unrecognized e_machine %d %s\n", + r2(&ehdr->e_machine), fname); + return -1; + } + + switch (ehdr->e_ident[EI_CLASS]) { + case ELFCLASS32: + if (r2(&ehdr->e_ehsize) != sizeof(Elf32_Ehdr) || + r2(&ehdr->e_shentsize) != sizeof(Elf32_Shdr)) { + fprintf(stderr, + "unrecognized ET_EXEC/ET_DYN file: %s\n", fname); + break; + } + rc = do_sort_32(ehdr, fname, custom_sort); + break; + case ELFCLASS64: + { + Elf64_Ehdr *const ghdr = (Elf64_Ehdr *)ehdr; + if (r2(&ghdr->e_ehsize) != sizeof(Elf64_Ehdr) || + r2(&ghdr->e_shentsize) != sizeof(Elf64_Shdr)) { + fprintf(stderr, + "unrecognized ET_EXEC/ET_DYN file: %s\n", + fname); + break; + } + rc = do_sort_64(ghdr, fname, custom_sort); + } + break; + default: + fprintf(stderr, "unrecognized ELF class %d %s\n", + ehdr->e_ident[EI_CLASS], fname); + break; + } + + return rc; +} + +int main(int argc, char *argv[]) +{ + int i, n_error = 0; /* gcc-4.3.0 false positive complaint */ + size_t size = 0; + void *addr = NULL; + + if (argc < 2) { + fprintf(stderr, "usage: sorttable vmlinux...\n"); + return 0; + } + + /* Process each file in turn, allowing deep failure. */ + for (i = 1; i < argc; i++) { + addr = mmap_file(argv[i], &size); + if (!addr) { + ++n_error; + continue; + } + + if (do_file(argv[i], addr)) + ++n_error; + + munmap(addr, size); + } + + return !!n_error; +} diff --git a/src/net/scripts/sorttable.h b/src/net/scripts/sorttable.h new file mode 100644 index 0000000..4ce32e8 --- /dev/null +++ b/src/net/scripts/sorttable.h @@ -0,0 +1,497 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * sorttable.h + * + * Added ORC unwind tables sort support and other updates: + * Copyright (C) 1999-2019 Alibaba Group Holding Limited. by: + * Shile Zhang <shile.zhang@linux.alibaba.com> + * + * Copyright 2011 - 2012 Cavium, Inc. + * + * Some of code was taken out of arch/x86/kernel/unwind_orc.c, written by: + * Copyright (C) 2017 Josh Poimboeuf <jpoimboe@redhat.com> + * + * Some of this code was taken out of recordmcount.h written by: + * + * Copyright 2009 John F. Reiser <jreiser@BitWagon.com>. All rights reserved. + * Copyright 2010 Steven Rostedt <srostedt@redhat.com>, Red Hat Inc. + */ + +#undef extable_ent_size +#undef compare_extable +#undef get_mcount_loc +#undef sort_mcount_loc +#undef elf_mcount_loc +#undef do_sort +#undef Elf_Addr +#undef Elf_Ehdr +#undef Elf_Shdr +#undef Elf_Rel +#undef Elf_Rela +#undef Elf_Sym +#undef ELF_R_SYM +#undef Elf_r_sym +#undef ELF_R_INFO +#undef Elf_r_info +#undef ELF_ST_BIND +#undef ELF_ST_TYPE +#undef fn_ELF_R_SYM +#undef fn_ELF_R_INFO +#undef uint_t +#undef _r +#undef _w + +#ifdef SORTTABLE_64 +# define extable_ent_size 16 +# define compare_extable compare_extable_64 +# define get_mcount_loc get_mcount_loc_64 +# define sort_mcount_loc sort_mcount_loc_64 +# define elf_mcount_loc elf_mcount_loc_64 +# define do_sort do_sort_64 +# define Elf_Addr Elf64_Addr +# define Elf_Ehdr Elf64_Ehdr +# define Elf_Shdr Elf64_Shdr +# define Elf_Rel Elf64_Rel +# define Elf_Rela Elf64_Rela +# define Elf_Sym Elf64_Sym +# define ELF_R_SYM ELF64_R_SYM +# define Elf_r_sym Elf64_r_sym +# define ELF_R_INFO ELF64_R_INFO +# define Elf_r_info Elf64_r_info +# define ELF_ST_BIND ELF64_ST_BIND +# define ELF_ST_TYPE ELF64_ST_TYPE +# define fn_ELF_R_SYM fn_ELF64_R_SYM +# define fn_ELF_R_INFO fn_ELF64_R_INFO +# define uint_t uint64_t +# define _r r8 +# define _w w8 +#else +# define extable_ent_size 8 +# define compare_extable compare_extable_32 +# define get_mcount_loc get_mcount_loc_32 +# define sort_mcount_loc sort_mcount_loc_32 +# define elf_mcount_loc elf_mcount_loc_32 +# define do_sort do_sort_32 +# define Elf_Addr Elf32_Addr +# define Elf_Ehdr Elf32_Ehdr +# define Elf_Shdr Elf32_Shdr +# define Elf_Rel Elf32_Rel +# define Elf_Rela Elf32_Rela +# define Elf_Sym Elf32_Sym +# define ELF_R_SYM ELF32_R_SYM +# define Elf_r_sym Elf32_r_sym +# define ELF_R_INFO ELF32_R_INFO +# define Elf_r_info Elf32_r_info +# define ELF_ST_BIND ELF32_ST_BIND +# define ELF_ST_TYPE ELF32_ST_TYPE +# define fn_ELF_R_SYM fn_ELF32_R_SYM +# define fn_ELF_R_INFO fn_ELF32_R_INFO +# define uint_t uint32_t +# define _r r +# define _w w +#endif + +#if defined(SORTTABLE_64) && defined(UNWINDER_ORC_ENABLED) +/* ORC unwinder only support X86_64 */ +#include <asm/orc_types.h> + +#define ERRSTR_MAXSZ 256 + +char g_err[ERRSTR_MAXSZ]; +int *g_orc_ip_table; +struct orc_entry *g_orc_table; + +pthread_t orc_sort_thread; + +static inline unsigned long orc_ip(const int *ip) +{ + return (unsigned long)ip + *ip; +} + +static int orc_sort_cmp(const void *_a, const void *_b) +{ + struct orc_entry *orc_a; + const int *a = g_orc_ip_table + *(int *)_a; + const int *b = g_orc_ip_table + *(int *)_b; + unsigned long a_val = orc_ip(a); + unsigned long b_val = orc_ip(b); + + if (a_val > b_val) + return 1; + if (a_val < b_val) + return -1; + + /* + * The "weak" section terminator entries need to always be on the left + * to ensure the lookup code skips them in favor of real entries. + * These terminator entries exist to handle any gaps created by + * whitelisted .o files which didn't get objtool generation. + */ + orc_a = g_orc_table + (a - g_orc_ip_table); + return orc_a->sp_reg == ORC_REG_UNDEFINED && !orc_a->end ? -1 : 1; +} + +static void *sort_orctable(void *arg) +{ + int i; + int *idxs = NULL; + int *tmp_orc_ip_table = NULL; + struct orc_entry *tmp_orc_table = NULL; + unsigned int *orc_ip_size = (unsigned int *)arg; + unsigned int num_entries = *orc_ip_size / sizeof(int); + unsigned int orc_size = num_entries * sizeof(struct orc_entry); + + idxs = (int *)malloc(*orc_ip_size); + if (!idxs) { + snprintf(g_err, ERRSTR_MAXSZ, "malloc idxs: %s", + strerror(errno)); + pthread_exit(g_err); + } + + tmp_orc_ip_table = (int *)malloc(*orc_ip_size); + if (!tmp_orc_ip_table) { + snprintf(g_err, ERRSTR_MAXSZ, "malloc tmp_orc_ip_table: %s", + strerror(errno)); + pthread_exit(g_err); + } + + tmp_orc_table = (struct orc_entry *)malloc(orc_size); + if (!tmp_orc_table) { + snprintf(g_err, ERRSTR_MAXSZ, "malloc tmp_orc_table: %s", + strerror(errno)); + pthread_exit(g_err); + } + + /* initialize indices array, convert ip_table to absolute address */ + for (i = 0; i < num_entries; i++) { + idxs[i] = i; + tmp_orc_ip_table[i] = g_orc_ip_table[i] + i * sizeof(int); + } + memcpy(tmp_orc_table, g_orc_table, orc_size); + + qsort(idxs, num_entries, sizeof(int), orc_sort_cmp); + + for (i = 0; i < num_entries; i++) { + if (idxs[i] == i) + continue; + + /* convert back to relative address */ + g_orc_ip_table[i] = tmp_orc_ip_table[idxs[i]] - i * sizeof(int); + g_orc_table[i] = tmp_orc_table[idxs[i]]; + } + + free(idxs); + free(tmp_orc_ip_table); + free(tmp_orc_table); + pthread_exit(NULL); +} +#endif + +static int compare_extable(const void *a, const void *b) +{ + Elf_Addr av = _r(a); + Elf_Addr bv = _r(b); + + if (av < bv) + return -1; + if (av > bv) + return 1; + return 0; +} +#ifdef MCOUNT_SORT_ENABLED +pthread_t mcount_sort_thread; + +struct elf_mcount_loc { + Elf_Ehdr *ehdr; + Elf_Shdr *init_data_sec; + uint_t start_mcount_loc; + uint_t stop_mcount_loc; +}; + +/* Sort the addresses stored between __start_mcount_loc to __stop_mcount_loc in vmlinux */ +static void *sort_mcount_loc(void *arg) +{ + struct elf_mcount_loc *emloc = (struct elf_mcount_loc *)arg; + uint_t offset = emloc->start_mcount_loc - _r(&(emloc->init_data_sec)->sh_addr) + + _r(&(emloc->init_data_sec)->sh_offset); + uint_t count = emloc->stop_mcount_loc - emloc->start_mcount_loc; + unsigned char *start_loc = (void *)emloc->ehdr + offset; + + qsort(start_loc, count/sizeof(uint_t), sizeof(uint_t), compare_extable); + return NULL; +} + +/* Get the address of __start_mcount_loc and __stop_mcount_loc in System.map */ +static void get_mcount_loc(uint_t *_start, uint_t *_stop) +{ + FILE *file_start, *file_stop; + char start_buff[20]; + char stop_buff[20]; + int len = 0; + + file_start = popen(" grep start_mcount System.map | awk '{print $1}' ", "r"); + if (!file_start) { + fprintf(stderr, "get start_mcount_loc error!"); + return; + } + + file_stop = popen(" grep stop_mcount System.map | awk '{print $1}' ", "r"); + if (!file_stop) { + fprintf(stderr, "get stop_mcount_loc error!"); + pclose(file_start); + return; + } + + while (fgets(start_buff, sizeof(start_buff), file_start) != NULL) { + len = strlen(start_buff); + start_buff[len - 1] = '\0'; + } + *_start = strtoul(start_buff, NULL, 16); + + while (fgets(stop_buff, sizeof(stop_buff), file_stop) != NULL) { + len = strlen(stop_buff); + stop_buff[len - 1] = '\0'; + } + *_stop = strtoul(stop_buff, NULL, 16); + + pclose(file_start); + pclose(file_stop); +} +#endif +static int do_sort(Elf_Ehdr *ehdr, + char const *const fname, + table_sort_t custom_sort) +{ + int rc = -1; + Elf_Shdr *s, *shdr = (Elf_Shdr *)((char *)ehdr + _r(&ehdr->e_shoff)); + Elf_Shdr *strtab_sec = NULL; + Elf_Shdr *symtab_sec = NULL; + Elf_Shdr *extab_sec = NULL; + Elf_Sym *sym; + const Elf_Sym *symtab; + Elf32_Word *symtab_shndx = NULL; + Elf_Sym *sort_needed_sym = NULL; + Elf_Shdr *sort_needed_sec; + Elf_Rel *relocs = NULL; + int relocs_size = 0; + uint32_t *sort_needed_loc; + const char *secstrings; + const char *strtab; + char *extab_image; + int extab_index = 0; + int i; + int idx; + unsigned int shnum; + unsigned int shstrndx; +#ifdef MCOUNT_SORT_ENABLED + struct elf_mcount_loc mstruct = {0}; + uint_t _start_mcount_loc = 0; + uint_t _stop_mcount_loc = 0; +#endif +#if defined(SORTTABLE_64) && defined(UNWINDER_ORC_ENABLED) + unsigned int orc_ip_size = 0; + unsigned int orc_size = 0; + unsigned int orc_num_entries = 0; +#endif + + shstrndx = r2(&ehdr->e_shstrndx); + if (shstrndx == SHN_XINDEX) + shstrndx = r(&shdr[0].sh_link); + secstrings = (const char *)ehdr + _r(&shdr[shstrndx].sh_offset); + + shnum = r2(&ehdr->e_shnum); + if (shnum == SHN_UNDEF) + shnum = _r(&shdr[0].sh_size); + + for (i = 0, s = shdr; s < shdr + shnum; i++, s++) { + idx = r(&s->sh_name); + if (!strcmp(secstrings + idx, "__ex_table")) { + extab_sec = s; + extab_index = i; + } + if (!strcmp(secstrings + idx, ".symtab")) + symtab_sec = s; + if (!strcmp(secstrings + idx, ".strtab")) + strtab_sec = s; + + if ((r(&s->sh_type) == SHT_REL || + r(&s->sh_type) == SHT_RELA) && + r(&s->sh_info) == extab_index) { + relocs = (void *)ehdr + _r(&s->sh_offset); + relocs_size = _r(&s->sh_size); + } + if (r(&s->sh_type) == SHT_SYMTAB_SHNDX) + symtab_shndx = (Elf32_Word *)((const char *)ehdr + + _r(&s->sh_offset)); + +#ifdef MCOUNT_SORT_ENABLED + /* locate the .init.data section in vmlinux */ + if (!strcmp(secstrings + idx, ".init.data")) { + get_mcount_loc(&_start_mcount_loc, &_stop_mcount_loc); + mstruct.ehdr = ehdr; + mstruct.init_data_sec = s; + mstruct.start_mcount_loc = _start_mcount_loc; + mstruct.stop_mcount_loc = _stop_mcount_loc; + } +#endif + +#if defined(SORTTABLE_64) && defined(UNWINDER_ORC_ENABLED) + /* locate the ORC unwind tables */ + if (!strcmp(secstrings + idx, ".orc_unwind_ip")) { + orc_ip_size = s->sh_size; + g_orc_ip_table = (int *)((void *)ehdr + + s->sh_offset); + } + if (!strcmp(secstrings + idx, ".orc_unwind")) { + orc_size = s->sh_size; + g_orc_table = (struct orc_entry *)((void *)ehdr + + s->sh_offset); + } +#endif + } /* for loop */ + +#if defined(SORTTABLE_64) && defined(UNWINDER_ORC_ENABLED) + if (!g_orc_ip_table || !g_orc_table) { + fprintf(stderr, + "incomplete ORC unwind tables in file: %s\n", fname); + goto out; + } + + orc_num_entries = orc_ip_size / sizeof(int); + if (orc_ip_size % sizeof(int) != 0 || + orc_size % sizeof(struct orc_entry) != 0 || + orc_num_entries != orc_size / sizeof(struct orc_entry)) { + fprintf(stderr, + "inconsistent ORC unwind table entries in file: %s\n", + fname); + goto out; + } + + /* create thread to sort ORC unwind tables concurrently */ + if (pthread_create(&orc_sort_thread, NULL, + sort_orctable, &orc_ip_size)) { + fprintf(stderr, + "pthread_create orc_sort_thread failed '%s': %s\n", + strerror(errno), fname); + goto out; + } +#endif + +#ifdef MCOUNT_SORT_ENABLED + if (!mstruct.init_data_sec || !_start_mcount_loc || !_stop_mcount_loc) { + fprintf(stderr, + "incomplete mcount's sort in file: %s\n", + fname); + goto out; + } + + /* create thread to sort mcount_loc concurrently */ + if (pthread_create(&mcount_sort_thread, NULL, &sort_mcount_loc, &mstruct)) { + fprintf(stderr, + "pthread_create mcount_sort_thread failed '%s': %s\n", + strerror(errno), fname); + goto out; + } +#endif + if (!extab_sec) { + fprintf(stderr, "no __ex_table in file: %s\n", fname); + goto out; + } + + if (!symtab_sec) { + fprintf(stderr, "no .symtab in file: %s\n", fname); + goto out; + } + + if (!strtab_sec) { + fprintf(stderr, "no .strtab in file: %s\n", fname); + goto out; + } + + extab_image = (void *)ehdr + _r(&extab_sec->sh_offset); + strtab = (const char *)ehdr + _r(&strtab_sec->sh_offset); + symtab = (const Elf_Sym *)((const char *)ehdr + + _r(&symtab_sec->sh_offset)); + + if (custom_sort) { + custom_sort(extab_image, _r(&extab_sec->sh_size)); + } else { + int num_entries = _r(&extab_sec->sh_size) / extable_ent_size; + qsort(extab_image, num_entries, + extable_ent_size, compare_extable); + } + + /* If there were relocations, we no longer need them. */ + if (relocs) + memset(relocs, 0, relocs_size); + + /* find the flag main_extable_sort_needed */ + for (sym = (void *)ehdr + _r(&symtab_sec->sh_offset); + sym < sym + _r(&symtab_sec->sh_size) / sizeof(Elf_Sym); + sym++) { + if (ELF_ST_TYPE(sym->st_info) != STT_OBJECT) + continue; + if (!strcmp(strtab + r(&sym->st_name), + "main_extable_sort_needed")) { + sort_needed_sym = sym; + break; + } + } + + if (!sort_needed_sym) { + fprintf(stderr, + "no main_extable_sort_needed symbol in file: %s\n", + fname); + goto out; + } + + sort_needed_sec = &shdr[get_secindex(r2(&sym->st_shndx), + sort_needed_sym - symtab, + symtab_shndx)]; + sort_needed_loc = (void *)ehdr + + _r(&sort_needed_sec->sh_offset) + + _r(&sort_needed_sym->st_value) - + _r(&sort_needed_sec->sh_addr); + + /* extable has been sorted, clear the flag */ + w(0, sort_needed_loc); + rc = 0; + +out: +#if defined(SORTTABLE_64) && defined(UNWINDER_ORC_ENABLED) + if (orc_sort_thread) { + void *retval = NULL; + /* wait for ORC tables sort done */ + rc = pthread_join(orc_sort_thread, &retval); + if (rc) + fprintf(stderr, + "pthread_join failed '%s': %s\n", + strerror(errno), fname); + else if (retval) { + rc = -1; + fprintf(stderr, + "failed to sort ORC tables '%s': %s\n", + (char *)retval, fname); + } + } +#endif + +#ifdef MCOUNT_SORT_ENABLED + if (mcount_sort_thread) { + void *retval = NULL; + /* wait for mcount sort done */ + rc = pthread_join(mcount_sort_thread, &retval); + if (rc) { + fprintf(stderr, + "pthread_join failed '%s': %s\n", + strerror(errno), fname); + } else if (retval) { + rc = -1; + fprintf(stderr, + "failed to sort mcount '%s': %s\n", + (char *)retval, fname); + } + } +#endif + return rc; +} diff --git a/src/net/scripts/spdxcheck-test.sh b/src/net/scripts/spdxcheck-test.sh new file mode 100644 index 0000000..cfea6a0 --- /dev/null +++ b/src/net/scripts/spdxcheck-test.sh @@ -0,0 +1,12 @@ +#!/bin/sh + +for PYTHON in python2 python3; do + # run check on a text and a binary file + for FILE in Makefile Documentation/logo.gif; do + $PYTHON scripts/spdxcheck.py $FILE + $PYTHON scripts/spdxcheck.py - < $FILE + done + + # run check on complete tree to catch any other issues + $PYTHON scripts/spdxcheck.py > /dev/null +done diff --git a/src/net/scripts/spdxcheck.py b/src/net/scripts/spdxcheck.py new file mode 100755 index 0000000..2288192 --- /dev/null +++ b/src/net/scripts/spdxcheck.py @@ -0,0 +1,296 @@ +#!/usr/bin/env python +# SPDX-License-Identifier: GPL-2.0 +# Copyright Thomas Gleixner <tglx@linutronix.de> + +from argparse import ArgumentParser +from ply import lex, yacc +import locale +import traceback +import sys +import git +import re +import os + +class ParserException(Exception): + def __init__(self, tok, txt): + self.tok = tok + self.txt = txt + +class SPDXException(Exception): + def __init__(self, el, txt): + self.el = el + self.txt = txt + +class SPDXdata(object): + def __init__(self): + self.license_files = 0 + self.exception_files = 0 + self.licenses = [ ] + self.exceptions = { } + +# Read the spdx data from the LICENSES directory +def read_spdxdata(repo): + + # The subdirectories of LICENSES in the kernel source + # Note: exceptions needs to be parsed as last directory. + license_dirs = [ "preferred", "dual", "deprecated", "exceptions" ] + lictree = repo.head.commit.tree['LICENSES'] + + spdx = SPDXdata() + + for d in license_dirs: + for el in lictree[d].traverse(): + if not os.path.isfile(el.path): + continue + + exception = None + for l in open(el.path).readlines(): + if l.startswith('Valid-License-Identifier:'): + lid = l.split(':')[1].strip().upper() + if lid in spdx.licenses: + raise SPDXException(el, 'Duplicate License Identifier: %s' %lid) + else: + spdx.licenses.append(lid) + + elif l.startswith('SPDX-Exception-Identifier:'): + exception = l.split(':')[1].strip().upper() + spdx.exceptions[exception] = [] + + elif l.startswith('SPDX-Licenses:'): + for lic in l.split(':')[1].upper().strip().replace(' ', '').replace('\t', '').split(','): + if not lic in spdx.licenses: + raise SPDXException(None, 'Exception %s missing license %s' %(exception, lic)) + spdx.exceptions[exception].append(lic) + + elif l.startswith("License-Text:"): + if exception: + if not len(spdx.exceptions[exception]): + raise SPDXException(el, 'Exception %s is missing SPDX-Licenses' %exception) + spdx.exception_files += 1 + else: + spdx.license_files += 1 + break + return spdx + +class id_parser(object): + + reserved = [ 'AND', 'OR', 'WITH' ] + tokens = [ 'LPAR', 'RPAR', 'ID', 'EXC' ] + reserved + + precedence = ( ('nonassoc', 'AND', 'OR'), ) + + t_ignore = ' \t' + + def __init__(self, spdx): + self.spdx = spdx + self.lasttok = None + self.lastid = None + self.lexer = lex.lex(module = self, reflags = re.UNICODE) + # Initialize the parser. No debug file and no parser rules stored on disk + # The rules are small enough to be generated on the fly + self.parser = yacc.yacc(module = self, write_tables = False, debug = False) + self.lines_checked = 0 + self.checked = 0 + self.spdx_valid = 0 + self.spdx_errors = 0 + self.curline = 0 + self.deepest = 0 + + # Validate License and Exception IDs + def validate(self, tok): + id = tok.value.upper() + if tok.type == 'ID': + if not id in self.spdx.licenses: + raise ParserException(tok, 'Invalid License ID') + self.lastid = id + elif tok.type == 'EXC': + if id not in self.spdx.exceptions: + raise ParserException(tok, 'Invalid Exception ID') + if self.lastid not in self.spdx.exceptions[id]: + raise ParserException(tok, 'Exception not valid for license %s' %self.lastid) + self.lastid = None + elif tok.type != 'WITH': + self.lastid = None + + # Lexer functions + def t_RPAR(self, tok): + r'\)' + self.lasttok = tok.type + return tok + + def t_LPAR(self, tok): + r'\(' + self.lasttok = tok.type + return tok + + def t_ID(self, tok): + r'[A-Za-z.0-9\-+]+' + + if self.lasttok == 'EXC': + print(tok) + raise ParserException(tok, 'Missing parentheses') + + tok.value = tok.value.strip() + val = tok.value.upper() + + if val in self.reserved: + tok.type = val + elif self.lasttok == 'WITH': + tok.type = 'EXC' + + self.lasttok = tok.type + self.validate(tok) + return tok + + def t_error(self, tok): + raise ParserException(tok, 'Invalid token') + + def p_expr(self, p): + '''expr : ID + | ID WITH EXC + | expr AND expr + | expr OR expr + | LPAR expr RPAR''' + pass + + def p_error(self, p): + if not p: + raise ParserException(None, 'Unfinished license expression') + else: + raise ParserException(p, 'Syntax error') + + def parse(self, expr): + self.lasttok = None + self.lastid = None + self.parser.parse(expr, lexer = self.lexer) + + def parse_lines(self, fd, maxlines, fname): + self.checked += 1 + self.curline = 0 + try: + for line in fd: + line = line.decode(locale.getpreferredencoding(False), errors='ignore') + self.curline += 1 + if self.curline > maxlines: + break + self.lines_checked += 1 + if line.find("SPDX-License-Identifier:") < 0: + continue + expr = line.split(':')[1].strip() + # Remove trailing comment closure + if line.strip().endswith('*/'): + expr = expr.rstrip('*/').strip() + # Remove trailing xml comment closure + if line.strip().endswith('-->'): + expr = expr.rstrip('-->').strip() + # Special case for SH magic boot code files + if line.startswith('LIST \"'): + expr = expr.rstrip('\"').strip() + self.parse(expr) + self.spdx_valid += 1 + # + # Should we check for more SPDX ids in the same file and + # complain if there are any? + # + break + + except ParserException as pe: + if pe.tok: + col = line.find(expr) + pe.tok.lexpos + tok = pe.tok.value + sys.stdout.write('%s: %d:%d %s: %s\n' %(fname, self.curline, col, pe.txt, tok)) + else: + sys.stdout.write('%s: %d:0 %s\n' %(fname, self.curline, pe.txt)) + self.spdx_errors += 1 + +def scan_git_tree(tree): + for el in tree.traverse(): + # Exclude stuff which would make pointless noise + # FIXME: Put this somewhere more sensible + if el.path.startswith("LICENSES"): + continue + if el.path.find("license-rules.rst") >= 0: + continue + if not os.path.isfile(el.path): + continue + with open(el.path, 'rb') as fd: + parser.parse_lines(fd, args.maxlines, el.path) + +def scan_git_subtree(tree, path): + for p in path.strip('/').split('/'): + tree = tree[p] + scan_git_tree(tree) + +if __name__ == '__main__': + + ap = ArgumentParser(description='SPDX expression checker') + ap.add_argument('path', nargs='*', help='Check path or file. If not given full git tree scan. For stdin use "-"') + ap.add_argument('-m', '--maxlines', type=int, default=15, + help='Maximum number of lines to scan in a file. Default 15') + ap.add_argument('-v', '--verbose', action='store_true', help='Verbose statistics output') + args = ap.parse_args() + + # Sanity check path arguments + if '-' in args.path and len(args.path) > 1: + sys.stderr.write('stdin input "-" must be the only path argument\n') + sys.exit(1) + + try: + # Use git to get the valid license expressions + repo = git.Repo(os.getcwd()) + assert not repo.bare + + # Initialize SPDX data + spdx = read_spdxdata(repo) + + # Initilize the parser + parser = id_parser(spdx) + + except SPDXException as se: + if se.el: + sys.stderr.write('%s: %s\n' %(se.el.path, se.txt)) + else: + sys.stderr.write('%s\n' %se.txt) + sys.exit(1) + + except Exception as ex: + sys.stderr.write('FAIL: %s\n' %ex) + sys.stderr.write('%s\n' %traceback.format_exc()) + sys.exit(1) + + try: + if len(args.path) and args.path[0] == '-': + stdin = os.fdopen(sys.stdin.fileno(), 'rb') + parser.parse_lines(stdin, args.maxlines, '-') + else: + if args.path: + for p in args.path: + if os.path.isfile(p): + parser.parse_lines(open(p, 'rb'), args.maxlines, p) + elif os.path.isdir(p): + scan_git_subtree(repo.head.reference.commit.tree, p) + else: + sys.stderr.write('path %s does not exist\n' %p) + sys.exit(1) + else: + # Full git tree scan + scan_git_tree(repo.head.commit.tree) + + if args.verbose: + sys.stderr.write('\n') + sys.stderr.write('License files: %12d\n' %spdx.license_files) + sys.stderr.write('Exception files: %12d\n' %spdx.exception_files) + sys.stderr.write('License IDs %12d\n' %len(spdx.licenses)) + sys.stderr.write('Exception IDs %12d\n' %len(spdx.exceptions)) + sys.stderr.write('\n') + sys.stderr.write('Files checked: %12d\n' %parser.checked) + sys.stderr.write('Lines checked: %12d\n' %parser.lines_checked) + sys.stderr.write('Files with SPDX: %12d\n' %parser.spdx_valid) + sys.stderr.write('Files with errors: %12d\n' %parser.spdx_errors) + + sys.exit(0) + + except Exception as ex: + sys.stderr.write('FAIL: %s\n' %ex) + sys.stderr.write('%s\n' %traceback.format_exc()) + sys.exit(1) diff --git a/src/net/scripts/spelling.txt b/src/net/scripts/spelling.txt new file mode 100644 index 0000000..953f4a2 --- /dev/null +++ b/src/net/scripts/spelling.txt @@ -0,0 +1,1536 @@ +# Originally from Debian's Lintian tool. Various false positives have been +# removed, and various additions have been made as they've been discovered +# in the kernel source. +# +# License: GPLv2 +# +# The format of each line is: +# mistake||correction +# +abandonning||abandoning +abigious||ambiguous +abitrary||arbitrary +abitrate||arbitrate +abnornally||abnormally +abnrormal||abnormal +abord||abort +aboslute||absolute +abov||above +abreviated||abbreviated +absense||absence +absolut||absolute +absoulte||absolute +acccess||access +acceess||access +acceleratoin||acceleration +accelleration||acceleration +accesing||accessing +accesnt||accent +accessable||accessible +accesss||access +accidentaly||accidentally +accidentually||accidentally +acclerated||accelerated +accoding||according +accomodate||accommodate +accomodates||accommodates +accordign||according +accoring||according +accout||account +accquire||acquire +accquired||acquired +accross||across +accumalate||accumulate +accumalator||accumulator +acessable||accessible +acess||access +acessing||accessing +achitecture||architecture +acient||ancient +acitions||actions +acitve||active +acknowldegement||acknowledgment +acknowledgement||acknowledgment +ackowledge||acknowledge +ackowledged||acknowledged +acording||according +activete||activate +actived||activated +actualy||actually +acumulating||accumulating +acumulative||accumulative +acumulator||accumulator +acutally||actually +adapater||adapter +addional||additional +additionaly||additionally +additonal||additional +addres||address +adddress||address +addreses||addresses +addresss||address +addrress||address +aditional||additional +aditionally||additionally +aditionaly||additionally +adminstrative||administrative +adress||address +adresses||addresses +adrresses||addresses +advertisment||advertisement +adviced||advised +afecting||affecting +againt||against +agaist||against +aggreataon||aggregation +aggreation||aggregation +albumns||albums +alegorical||allegorical +algined||aligned +algorith||algorithm +algorithmical||algorithmically +algoritm||algorithm +algoritms||algorithms +algorithmn||algorithm +algorrithm||algorithm +algorritm||algorithm +aligment||alignment +alignement||alignment +allign||align +alligned||aligned +alllocate||allocate +alloated||allocated +allocatote||allocate +allocatrd||allocated +allocte||allocate +allpication||application +alocate||allocate +alogirhtms||algorithms +alogrithm||algorithm +alot||a lot +alow||allow +alows||allows +alreay||already +alredy||already +altough||although +alue||value +ambigious||ambiguous +ambigous||ambiguous +amoung||among +amout||amount +amplifer||amplifier +amplifyer||amplifier +an union||a union +an user||a user +an userspace||a userspace +an one||a one +analysator||analyzer +ang||and +anniversery||anniversary +annoucement||announcement +anomolies||anomalies +anomoly||anomaly +anway||anyway +aplication||application +appearence||appearance +applicaion||application +appliction||application +applictions||applications +applys||applies +appplications||applications +appropiate||appropriate +appropriatly||appropriately +approriate||appropriate +approriately||appropriately +apropriate||appropriate +aquainted||acquainted +aquired||acquired +aquisition||acquisition +arbitary||arbitrary +architechture||architecture +arguement||argument +arguements||arguments +arithmatic||arithmetic +aritmetic||arithmetic +arne't||aren't +arraival||arrival +artifical||artificial +artillary||artillery +asign||assign +asser||assert +assertation||assertion +assertting||asserting +assiged||assigned +assigment||assignment +assigments||assignments +assistent||assistant +assocation||association +associcated||associated +assotiated||associated +asssert||assert +assum||assume +assumtpion||assumption +asuming||assuming +asycronous||asynchronous +asynchnous||asynchronous +asynchromous||asynchronous +asymetric||asymmetric +asymmeric||asymmetric +atomatically||automatically +atomicly||atomically +atempt||attempt +attachement||attachment +attatch||attach +attched||attached +attemp||attempt +attemps||attempts +attemping||attempting +attepmpt||attempt +attnetion||attention +attruibutes||attributes +authentification||authentication +authenicated||authenticated +automaticaly||automatically +automaticly||automatically +automatize||automate +automatized||automated +automatizes||automates +autonymous||autonomous +auxillary||auxiliary +auxilliary||auxiliary +avaiable||available +avaible||available +availabe||available +availabled||available +availablity||availability +availaible||available +availale||available +availavility||availability +availble||available +availiable||available +availible||available +avalable||available +avaliable||available +aysnc||async +backgroud||background +backword||backward +backwords||backwards +bahavior||behavior +bakup||backup +baloon||balloon +baloons||balloons +bandwith||bandwidth +banlance||balance +batery||battery +beacuse||because +becasue||because +becomming||becoming +becuase||because +beeing||being +befor||before +begining||beginning +beter||better +betweeen||between +bianries||binaries +bitmast||bitmask +boardcast||broadcast +borad||board +boundry||boundary +brievely||briefly +brigde||bridge +broadcase||broadcast +broadcat||broadcast +bufer||buffer +bufufer||buffer +cacluated||calculated +caculate||calculate +caculation||calculation +cadidate||candidate +cahces||caches +calender||calendar +calescing||coalescing +calle||called +callibration||calibration +callled||called +callser||caller +calucate||calculate +calulate||calculate +cancelation||cancellation +cancle||cancel +capabilites||capabilities +capabilties||capabilities +capabilty||capability +capabitilies||capabilities +capablity||capability +capatibilities||capabilities +capapbilities||capabilities +caputure||capture +carefuly||carefully +cariage||carriage +catagory||category +cehck||check +challange||challenge +challanges||challenges +chache||cache +chanell||channel +changable||changeable +chanined||chained +channle||channel +channnel||channel +charachter||character +charachters||characters +charactor||character +charater||character +charaters||characters +charcter||character +chcek||check +chck||check +checksumed||checksummed +checksuming||checksumming +childern||children +childs||children +chiled||child +chked||checked +chnage||change +chnages||changes +chnnel||channel +choosen||chosen +chouse||chose +circumvernt||circumvent +claread||cleared +clared||cleared +closeing||closing +clustred||clustered +cnfiguration||configuration +coexistance||coexistence +colescing||coalescing +collapsable||collapsible +colorfull||colorful +comand||command +comit||commit +commerical||commercial +comming||coming +comminucation||communication +commited||committed +commiting||committing +committ||commit +commoditiy||commodity +comsume||consume +comsumer||consumer +comsuming||consuming +compability||compatibility +compaibility||compatibility +comparsion||comparison +compatability||compatibility +compatable||compatible +compatibililty||compatibility +compatibiliy||compatibility +compatibilty||compatibility +compatiblity||compatibility +competion||completion +compilant||compliant +compleatly||completely +completition||completion +completly||completely +complient||compliant +componnents||components +compoment||component +comppatible||compatible +compres||compress +compresion||compression +comression||compression +comunication||communication +conbination||combination +conditionaly||conditionally +conditon||condition +condtion||condition +conected||connected +conector||connector +configration||configuration +configuartion||configuration +configuation||configuration +configued||configured +configuratoin||configuration +configuraton||configuration +configuretion||configuration +configutation||configuration +conider||consider +conjuction||conjunction +connecetd||connected +connectinos||connections +connetor||connector +connnection||connection +connnections||connections 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+unvalid||invalid +upate||update +upsupported||unsupported +usefule||useful +usefull||useful +usege||usage +usera||users +usualy||usually +usupported||unsupported +utilites||utilities +utillities||utilities +utilties||utilities +utiltity||utility +utitity||utility +utitlty||utility +vaid||valid +vaild||valid +valide||valid +variantions||variations +varible||variable +varient||variant +vaule||value +verbse||verbose +veify||verify +verisons||versions +verison||version +verson||version +vicefersa||vice-versa +virtal||virtual +virtaul||virtual +virtiual||virtual +visiters||visitors +vitual||virtual +vunerable||vulnerable +wakeus||wakeups +wathdog||watchdog +wating||waiting +wiat||wait +wether||whether +whataver||whatever +whcih||which +whenver||whenever +wheter||whether +whe||when +wierd||weird +wiil||will +wirte||write +withing||within +wnat||want +workarould||workaround +writeing||writing +writting||writing +wtih||with +zombe||zombie +zomebie||zombie diff --git a/src/net/scripts/sphinx-pre-install b/src/net/scripts/sphinx-pre-install new file mode 100755 index 0000000..8fcea76 --- /dev/null +++ b/src/net/scripts/sphinx-pre-install @@ -0,0 +1,925 @@ +#!/usr/bin/env perl +# SPDX-License-Identifier: GPL-2.0-or-later +use strict; + +# Copyright (c) 2017-2020 Mauro Carvalho Chehab <mchehab@kernel.org> +# + +my $prefix = "./"; +$prefix = "$ENV{'srctree'}/" if ($ENV{'srctree'}); + +my $conf = $prefix . "Documentation/conf.py"; +my $requirement_file = $prefix . "Documentation/sphinx/requirements.txt"; +my $virtenv_prefix = "sphinx_"; + +# +# Static vars +# + +my %missing; +my $system_release; +my $need = 0; +my $optional = 0; +my $need_symlink = 0; +my $need_sphinx = 0; +my $need_venv = 0; +my $need_virtualenv = 0; +my $rec_sphinx_upgrade = 0; +my $install = ""; +my $virtenv_dir = ""; +my $python_cmd = ""; +my $min_version; +my $cur_version; +my $rec_version = "1.7.9"; # PDF won't build here +my $min_pdf_version = "2.4.4"; # Min version where pdf builds + +# +# Command line arguments +# + +my $pdf = 1; +my $virtualenv = 1; +my $version_check = 0; + +# +# List of required texlive packages on Fedora and OpenSuse +# + +my %texlive = ( + 'amsfonts.sty' => 'texlive-amsfonts', + 'amsmath.sty' => 'texlive-amsmath', + 'amssymb.sty' => 'texlive-amsfonts', + 'amsthm.sty' => 'texlive-amscls', + 'anyfontsize.sty' => 'texlive-anyfontsize', + 'atbegshi.sty' => 'texlive-oberdiek', + 'bm.sty' => 'texlive-tools', + 'capt-of.sty' => 'texlive-capt-of', + 'cmap.sty' => 'texlive-cmap', + 'ecrm1000.tfm' => 'texlive-ec', + 'eqparbox.sty' => 'texlive-eqparbox', + 'eu1enc.def' => 'texlive-euenc', + 'fancybox.sty' => 'texlive-fancybox', + 'fancyvrb.sty' => 'texlive-fancyvrb', + 'float.sty' => 'texlive-float', + 'fncychap.sty' => 'texlive-fncychap', + 'footnote.sty' => 'texlive-mdwtools', + 'framed.sty' => 'texlive-framed', + 'luatex85.sty' => 'texlive-luatex85', + 'multirow.sty' => 'texlive-multirow', + 'needspace.sty' => 'texlive-needspace', + 'palatino.sty' => 'texlive-psnfss', + 'parskip.sty' => 'texlive-parskip', + 'polyglossia.sty' => 'texlive-polyglossia', + 'tabulary.sty' => 'texlive-tabulary', + 'threeparttable.sty' => 'texlive-threeparttable', + 'titlesec.sty' => 'texlive-titlesec', + 'ucs.sty' => 'texlive-ucs', + 'upquote.sty' => 'texlive-upquote', + 'wrapfig.sty' => 'texlive-wrapfig', + 'ctexhook.sty' => 'texlive-ctex', +); + +# +# Subroutines that checks if a feature exists +# + +sub check_missing(%) +{ + my %map = %{$_[0]}; + + foreach my $prog (sort keys %missing) { + my $is_optional = $missing{$prog}; + + # At least on some LTS distros like CentOS 7, texlive doesn't + # provide all packages we need. When such distros are + # detected, we have to disable PDF output. + # + # So, we need to ignore the packages that distros would + # need for LaTeX to work + if ($is_optional == 2 && !$pdf) { + $optional--; + next; + } + + if ($is_optional) { + print "Warning: better to also install \"$prog\".\n"; + } else { + print "ERROR: please install \"$prog\", otherwise, build won't work.\n"; + } + if (defined($map{$prog})) { + $install .= " " . $map{$prog}; + } else { + $install .= " " . $prog; + } + } + + $install =~ s/^\s//; +} + +sub add_package($$) +{ + my $package = shift; + my $is_optional = shift; + + $missing{$package} = $is_optional; + if ($is_optional) { + $optional++; + } else { + $need++; + } +} + +sub check_missing_file($$$) +{ + my $files = shift; + my $package = shift; + my $is_optional = shift; + + for (@$files) { + return if(-e $_); + } + + add_package($package, $is_optional); +} + +sub findprog($) +{ + foreach(split(/:/, $ENV{PATH})) { + return "$_/$_[0]" if(-x "$_/$_[0]"); + } +} + +sub find_python_no_venv() +{ + my $prog = shift; + + my $cur_dir = qx(pwd); + $cur_dir =~ s/\s+$//; + + foreach my $dir (split(/:/, $ENV{PATH})) { + next if ($dir =~ m,($cur_dir)/sphinx,); + return "$dir/python3" if(-x "$dir/python3"); + } + foreach my $dir (split(/:/, $ENV{PATH})) { + next if ($dir =~ m,($cur_dir)/sphinx,); + return "$dir/python" if(-x "$dir/python"); + } + return "python"; +} + +sub check_program($$) +{ + my $prog = shift; + my $is_optional = shift; + + return $prog if findprog($prog); + + add_package($prog, $is_optional); +} + +sub check_perl_module($$) +{ + my $prog = shift; + my $is_optional = shift; + + my $err = system("perl -M$prog -e 1 2>/dev/null /dev/null"); + return if ($err == 0); + + add_package($prog, $is_optional); +} + +sub check_python_module($$) +{ + my $prog = shift; + my $is_optional = shift; + + return if (!$python_cmd); + + my $err = system("$python_cmd -c 'import $prog' 2>/dev/null /dev/null"); + return if ($err == 0); + + add_package($prog, $is_optional); +} + +sub check_rpm_missing($$) +{ + my @pkgs = @{$_[0]}; + my $is_optional = $_[1]; + + foreach my $prog(@pkgs) { + my $err = system("rpm -q '$prog' 2>/dev/null >/dev/null"); + add_package($prog, $is_optional) if ($err); + } +} + +sub check_pacman_missing($$) +{ + my @pkgs = @{$_[0]}; + my $is_optional = $_[1]; + + foreach my $prog(@pkgs) { + my $err = system("pacman -Q '$prog' 2>/dev/null >/dev/null"); + add_package($prog, $is_optional) if ($err); + } +} + +sub check_missing_tex($) +{ + my $is_optional = shift; + my $kpsewhich = findprog("kpsewhich"); + + foreach my $prog(keys %texlive) { + my $package = $texlive{$prog}; + if (!$kpsewhich) { + add_package($package, $is_optional); + next; + } + my $file = qx($kpsewhich $prog); + add_package($package, $is_optional) if ($file =~ /^\s*$/); + } +} + +sub get_sphinx_fname() +{ + my $fname = "sphinx-build"; + return $fname if findprog($fname); + + $fname = "sphinx-build-3"; + if (findprog($fname)) { + $need_symlink = 1; + return $fname; + } + + return ""; +} + +sub get_sphinx_version($) +{ + my $cmd = shift; + my $ver; + + open IN, "$cmd --version 2>&1 |"; + while (<IN>) { + if (m/^\s*sphinx-build\s+([\d\.]+)(\+\/[\da-f]+)?$/) { + $ver=$1; + last; + } + # Sphinx 1.2.x uses a different format + if (m/^\s*Sphinx.*\s+([\d\.]+)$/) { + $ver=$1; + last; + } + } + close IN; + return $ver; +} + +sub check_sphinx() +{ + my $default_version; + + open IN, $conf or die "Can't open $conf"; + while (<IN>) { + if (m/^\s*needs_sphinx\s*=\s*[\'\"]([\d\.]+)[\'\"]/) { + $min_version=$1; + last; + } + } + close IN; + + die "Can't get needs_sphinx version from $conf" if (!$min_version); + + open IN, $requirement_file or die "Can't open $requirement_file"; + while (<IN>) { + if (m/^\s*Sphinx\s*==\s*([\d\.]+)$/) { + $default_version=$1; + last; + } + } + close IN; + + die "Can't get default sphinx version from $requirement_file" if (!$default_version); + + $virtenv_dir = $virtenv_prefix . $default_version; + + my $sphinx = get_sphinx_fname(); + if ($sphinx eq "") { + $need_sphinx = 1; + return; + } + + $cur_version = get_sphinx_version($sphinx); + die ("$sphinx returned an error") if (!$cur_version); + + die "$sphinx didn't return its version" if (!$cur_version); + + if ($cur_version lt $min_version) { + printf "ERROR: Sphinx version is %s. It should be >= %s (recommended >= %s)\n", + $cur_version, $min_version, $default_version; + $need_sphinx = 1; + return; + } + + if ($cur_version lt $rec_version) { + $rec_sphinx_upgrade = 1; + return; + } + + # On version check mode, just assume Sphinx has all mandatory deps + exit (0) if ($version_check); +} + +# +# Ancillary subroutines +# + +sub catcheck($) +{ + my $res = ""; + $res = qx(cat $_[0]) if (-r $_[0]); + return $res; +} + +sub which($) +{ + my $file = shift; + my @path = split ":", $ENV{PATH}; + + foreach my $dir(@path) { + my $name = $dir.'/'.$file; + return $name if (-x $name ); + } + return undef; +} + +# +# Subroutines that check distro-specific hints +# + +sub give_debian_hints() +{ + my %map = ( + "python-sphinx" => "python3-sphinx", + "sphinx_rtd_theme" => "python3-sphinx-rtd-theme", + "ensurepip" => "python3-venv", + "virtualenv" => "virtualenv", + "dot" => "graphviz", + "convert" => "imagemagick", + "Pod::Usage" => "perl-modules", + "xelatex" => "texlive-xetex", + "rsvg-convert" => "librsvg2-bin", + ); + + if ($pdf) { + check_missing_file(["/usr/share/texlive/texmf-dist/tex/latex/ctex/ctexhook.sty"], + "texlive-lang-chinese", 2); + + check_missing_file(["/usr/share/fonts/truetype/dejavu/DejaVuSans.ttf"], + "fonts-dejavu", 2); + + check_missing_file(["/usr/share/fonts/noto-cjk/NotoSansCJK-Regular.ttc", + "/usr/share/fonts/opentype/noto/NotoSansCJK-Regular.ttc", + "/usr/share/fonts/opentype/noto/NotoSerifCJK-Regular.ttc"], + "fonts-noto-cjk", 2); + } + + check_program("dvipng", 2) if ($pdf); + check_missing(\%map); + + return if (!$need && !$optional); + printf("You should run:\n\n\tsudo apt-get install $install\n"); +} + +sub give_redhat_hints() +{ + my %map = ( + "python-sphinx" => "python3-sphinx", + "sphinx_rtd_theme" => "python3-sphinx_rtd_theme", + "virtualenv" => "python3-virtualenv", + "dot" => "graphviz", + "convert" => "ImageMagick", + "Pod::Usage" => "perl-Pod-Usage", + "xelatex" => "texlive-xetex-bin", + "rsvg-convert" => "librsvg2-tools", + ); + + my @fedora26_opt_pkgs = ( + "graphviz-gd", # Fedora 26: needed for PDF support + ); + + my @fedora_tex_pkgs = ( + "texlive-collection-fontsrecommended", + "texlive-collection-latex", + "texlive-xecjk", + "dejavu-sans-fonts", + "dejavu-serif-fonts", + "dejavu-sans-mono-fonts", + ); + + # + # Checks valid for RHEL/CentOS version 7.x. + # + my $old = 0; + my $rel; + $rel = $1 if ($system_release =~ /release\s+(\d+)/); + + if (!($system_release =~ /Fedora/)) { + $map{"virtualenv"} = "python-virtualenv"; + + if ($rel && $rel < 8) { + $old = 1; + $pdf = 0; + + printf("Note: texlive packages on RHEL/CENTOS <= 7 are incomplete. Can't support PDF output\n"); + printf("If you want to build PDF, please read:\n"); + printf("\thttps://www.systutorials.com/241660/how-to-install-tex-live-on-centos-7-linux/\n"); + } + } else { + if ($rel && $rel < 26) { + $old = 1; + } + } + if (!$rel) { + printf("Couldn't identify release number\n"); + $old = 1; + $pdf = 0; + } + + if ($pdf) { + check_missing_file(["/usr/share/fonts/google-noto-cjk/NotoSansCJK-Regular.ttc"], + "google-noto-sans-cjk-ttc-fonts", 2); + } + + check_rpm_missing(\@fedora26_opt_pkgs, 2) if ($pdf && !$old); + check_rpm_missing(\@fedora_tex_pkgs, 2) if ($pdf); + check_missing_tex(2) if ($pdf); + check_missing(\%map); + + return if (!$need && !$optional); + + if (!$old) { + # dnf, for Fedora 18+ + printf("You should run:\n\n\tsudo dnf install -y $install\n"); + } else { + # yum, for RHEL (and clones) or Fedora version < 18 + printf("You should run:\n\n\tsudo yum install -y $install\n"); + } +} + +sub give_opensuse_hints() +{ + my %map = ( + "python-sphinx" => "python3-sphinx", + "sphinx_rtd_theme" => "python3-sphinx_rtd_theme", + "virtualenv" => "python3-virtualenv", + "dot" => "graphviz", + "convert" => "ImageMagick", + "Pod::Usage" => "perl-Pod-Usage", + "xelatex" => "texlive-xetex-bin", + ); + + # On Tumbleweed, this package is also named rsvg-convert + $map{"rsvg-convert"} = "rsvg-view" if (!($system_release =~ /Tumbleweed/)); + + my @suse_tex_pkgs = ( + "texlive-babel-english", + "texlive-caption", + "texlive-colortbl", + "texlive-courier", + "texlive-dvips", + "texlive-helvetic", + "texlive-makeindex", + "texlive-metafont", + "texlive-metapost", + "texlive-palatino", + "texlive-preview", + "texlive-times", + "texlive-zapfchan", + "texlive-zapfding", + ); + + $map{"latexmk"} = "texlive-latexmk-bin"; + + # FIXME: add support for installing CJK fonts + # + # I tried hard, but was unable to find a way to install + # "Noto Sans CJK SC" on openSUSE + + check_rpm_missing(\@suse_tex_pkgs, 2) if ($pdf); + check_missing_tex(2) if ($pdf); + check_missing(\%map); + + return if (!$need && !$optional); + printf("You should run:\n\n\tsudo zypper install --no-recommends $install\n"); +} + +sub give_mageia_hints() +{ + my %map = ( + "python-sphinx" => "python3-sphinx", + "sphinx_rtd_theme" => "python3-sphinx_rtd_theme", + "virtualenv" => "python3-virtualenv", + "dot" => "graphviz", + "convert" => "ImageMagick", + "Pod::Usage" => "perl-Pod-Usage", + "xelatex" => "texlive", + "rsvg-convert" => "librsvg2", + ); + + my @tex_pkgs = ( + "texlive-fontsextra", + ); + + $map{"latexmk"} = "texlive-collection-basic"; + + my $packager_cmd; + my $noto_sans; + if ($system_release =~ /OpenMandriva/) { + $packager_cmd = "dnf install"; + $noto_sans = "noto-sans-cjk-fonts"; + @tex_pkgs = ( "texlive-collection-fontsextra" ); + } else { + $packager_cmd = "urpmi"; + $noto_sans = "google-noto-sans-cjk-ttc-fonts"; + } + + + if ($pdf) { + check_missing_file(["/usr/share/fonts/google-noto-cjk/NotoSansCJK-Regular.ttc", + "/usr/share/fonts/TTF/NotoSans-Regular.ttf"], + $noto_sans, 2); + } + + check_rpm_missing(\@tex_pkgs, 2) if ($pdf); + check_missing(\%map); + + return if (!$need && !$optional); + printf("You should run:\n\n\tsudo $packager_cmd $install\n"); +} + +sub give_arch_linux_hints() +{ + my %map = ( + "sphinx_rtd_theme" => "python-sphinx_rtd_theme", + "virtualenv" => "python-virtualenv", + "dot" => "graphviz", + "convert" => "imagemagick", + "xelatex" => "texlive-bin", + "latexmk" => "texlive-core", + "rsvg-convert" => "extra/librsvg", + ); + + my @archlinux_tex_pkgs = ( + "texlive-core", + "texlive-latexextra", + "ttf-dejavu", + ); + check_pacman_missing(\@archlinux_tex_pkgs, 2) if ($pdf); + + if ($pdf) { + check_missing_file(["/usr/share/fonts/noto-cjk/NotoSansCJK-Regular.ttc"], + "noto-fonts-cjk", 2); + } + + check_missing(\%map); + + return if (!$need && !$optional); + printf("You should run:\n\n\tsudo pacman -S $install\n"); +} + +sub give_gentoo_hints() +{ + my %map = ( + "sphinx_rtd_theme" => "dev-python/sphinx_rtd_theme", + "virtualenv" => "dev-python/virtualenv", + "dot" => "media-gfx/graphviz", + "convert" => "media-gfx/imagemagick", + "xelatex" => "dev-texlive/texlive-xetex media-fonts/dejavu", + "rsvg-convert" => "gnome-base/librsvg", + ); + + check_missing_file(["/usr/share/fonts/dejavu/DejaVuSans.ttf"], + "media-fonts/dejavu", 2) if ($pdf); + + if ($pdf) { + check_missing_file(["/usr/share/fonts/noto-cjk/NotoSansCJKsc-Regular.otf", + "/usr/share/fonts/noto-cjk/NotoSerifCJK-Regular.ttc"], + "media-fonts/noto-cjk", 2); + } + + check_missing(\%map); + + return if (!$need && !$optional); + + printf("You should run:\n\n"); + + my $imagemagick = "media-gfx/imagemagick svg png"; + my $cairo = "media-gfx/graphviz cairo pdf"; + my $portage_imagemagick = "/etc/portage/package.use/imagemagick"; + my $portage_cairo = "/etc/portage/package.use/graphviz"; + + if (qx(grep imagemagick $portage_imagemagick 2>/dev/null) eq "") { + printf("\tsudo su -c 'echo \"$imagemagick\" > $portage_imagemagick'\n") + } + if (qx(grep graphviz $portage_cairo 2>/dev/null) eq "") { + printf("\tsudo su -c 'echo \"$cairo\" > $portage_cairo'\n"); + } + + printf("\tsudo emerge --ask $install\n"); + +} + +sub check_distros() +{ + # Distro-specific hints + if ($system_release =~ /Red Hat Enterprise Linux/) { + give_redhat_hints; + return; + } + if ($system_release =~ /CentOS/) { + give_redhat_hints; + return; + } + if ($system_release =~ /Scientific Linux/) { + give_redhat_hints; + return; + } + if ($system_release =~ /Oracle Linux Server/) { + give_redhat_hints; + return; + } + if ($system_release =~ /Fedora/) { + give_redhat_hints; + return; + } + if ($system_release =~ /Ubuntu/) { + give_debian_hints; + return; + } + if ($system_release =~ /Debian/) { + give_debian_hints; + return; + } + if ($system_release =~ /openSUSE/) { + give_opensuse_hints; + return; + } + if ($system_release =~ /Mageia/) { + give_mageia_hints; + return; + } + if ($system_release =~ /OpenMandriva/) { + give_mageia_hints; + return; + } + if ($system_release =~ /Arch Linux/) { + give_arch_linux_hints; + return; + } + if ($system_release =~ /Gentoo/) { + give_gentoo_hints; + return; + } + + # + # Fall-back to generic hint code for other distros + # That's far from ideal, specially for LaTeX dependencies. + # + my %map = ( + "sphinx-build" => "sphinx" + ); + check_missing_tex(2) if ($pdf); + check_missing(\%map); + print "I don't know distro $system_release.\n"; + print "So, I can't provide you a hint with the install procedure.\n"; + print "There are likely missing dependencies.\n"; +} + +# +# Common dependencies +# + +sub deactivate_help() +{ + printf "\nIf you want to exit the virtualenv, you can use:\n"; + printf "\tdeactivate\n"; +} + +sub check_needs() +{ + # Check if Sphinx is already accessible from current environment + check_sphinx(); + + if ($system_release) { + print "Detected OS: $system_release.\n"; + } else { + print "Unknown OS\n"; + } + printf "Sphinx version: %s\n\n", $cur_version if ($cur_version); + + # Check python command line, trying first python3 + $python_cmd = findprog("python3"); + $python_cmd = check_program("python", 0) if (!$python_cmd); + + # Check the type of virtual env, depending on Python version + if ($python_cmd) { + if ($virtualenv) { + my $tmp = qx($python_cmd --version 2>&1); + if ($tmp =~ m/(\d+\.)(\d+\.)/) { + if ($1 >= 3 && $2 >= 3) { + $need_venv = 1; # python 3.3 or upper + } else { + $need_virtualenv = 1; + } + if ($1 < 3) { + # Complain if it finds python2 (or worse) + printf "Warning: python$1 support is deprecated. Use it with caution!\n"; + } + } else { + die "Warning: couldn't identify $python_cmd version!"; + } + } else { + add_package("python-sphinx", 0); + } + } + + # Set virtualenv command line, if python < 3.3 + my $virtualenv_cmd; + if ($need_virtualenv) { + $virtualenv_cmd = findprog("virtualenv-3"); + $virtualenv_cmd = findprog("virtualenv-3.5") if (!$virtualenv_cmd); + if (!$virtualenv_cmd) { + check_program("virtualenv", 0); + $virtualenv_cmd = "virtualenv"; + } + } + + # Check for needed programs/tools + check_perl_module("Pod::Usage", 0); + check_program("make", 0); + check_program("gcc", 0); + check_python_module("sphinx_rtd_theme", 1) if (!$virtualenv); + check_program("dot", 1); + check_program("convert", 1); + + # Extra PDF files - should use 2 for is_optional + check_program("xelatex", 2) if ($pdf); + check_program("rsvg-convert", 2) if ($pdf); + check_program("latexmk", 2) if ($pdf); + + if ($need_sphinx || $rec_sphinx_upgrade) { + check_python_module("ensurepip", 0) if ($need_venv); + } + + # Do distro-specific checks and output distro-install commands + check_distros(); + + if (!$python_cmd) { + if ($need == 1) { + die "Can't build as $need mandatory dependency is missing"; + } elsif ($need) { + die "Can't build as $need mandatory dependencies are missing"; + } + } + + # Check if sphinx-build is called sphinx-build-3 + if ($need_symlink) { + printf "\tsudo ln -sf %s /usr/bin/sphinx-build\n\n", + which("sphinx-build-3"); + } + + # NOTE: if the system has a too old Sphinx version installed, + # it will recommend installing a newer version using virtualenv + + if ($need_sphinx || $rec_sphinx_upgrade) { + my $min_activate = "$ENV{'PWD'}/${virtenv_prefix}${min_version}/bin/activate"; + my @activates = glob "$ENV{'PWD'}/${virtenv_prefix}*/bin/activate"; + + if ($cur_version lt $rec_version) { + print "Warning: It is recommended at least Sphinx version $rec_version.\n"; + print " If you want pdf, you need at least $min_pdf_version.\n"; + } + if ($cur_version lt $min_pdf_version) { + print "Note: It is recommended at least Sphinx version $min_pdf_version if you need PDF support.\n"; + } + @activates = sort {$b cmp $a} @activates; + my ($activate, $ver); + foreach my $f (@activates) { + next if ($f lt $min_activate); + + my $sphinx_cmd = $f; + $sphinx_cmd =~ s/activate/sphinx-build/; + next if (! -f $sphinx_cmd); + + $ver = get_sphinx_version($sphinx_cmd); + if ($need_sphinx && ($ver ge $min_version)) { + $activate = $f; + last; + } elsif ($ver gt $cur_version) { + $activate = $f; + last; + } + } + if ($activate ne "") { + if ($need_sphinx) { + printf "\nNeed to activate Sphinx (version $ver) on virtualenv with:\n"; + printf "\t. $activate\n"; + deactivate_help(); + exit (1); + } else { + printf "\nYou may also use a newer Sphinx (version $ver) with:\n"; + printf "\tdeactivate && . $activate\n"; + } + } else { + my $rec_activate = "$virtenv_dir/bin/activate"; + + print "To upgrade Sphinx, use:\n\n" if ($rec_sphinx_upgrade); + + $python_cmd = find_python_no_venv(); + + if ($need_venv) { + printf "\t$python_cmd -m venv $virtenv_dir\n"; + } else { + printf "\t$virtualenv_cmd $virtenv_dir\n"; + } + printf "\t. $rec_activate\n"; + printf "\tpip install -r $requirement_file\n"; + deactivate_help(); + + $need++ if (!$rec_sphinx_upgrade); + } + } + printf "\n"; + + print "All optional dependencies are met.\n" if (!$optional); + + if ($need == 1) { + die "Can't build as $need mandatory dependency is missing"; + } elsif ($need) { + die "Can't build as $need mandatory dependencies are missing"; + } + + print "Needed package dependencies are met.\n"; +} + +# +# Main +# + +while (@ARGV) { + my $arg = shift(@ARGV); + + if ($arg eq "--no-virtualenv") { + $virtualenv = 0; + } elsif ($arg eq "--no-pdf"){ + $pdf = 0; + } elsif ($arg eq "--version-check"){ + $version_check = 1; + } else { + print "Usage:\n\t$0 <--no-virtualenv> <--no-pdf> <--version-check>\n\n"; + print "Where:\n"; + print "\t--no-virtualenv\t- Recommend installing Sphinx instead of using a virtualenv\n"; + print "\t--version-check\t- if version is compatible, don't check for missing dependencies\n"; + print "\t--no-pdf\t- don't check for dependencies required to build PDF docs\n\n"; + exit -1; + } +} + +# +# Determine the system type. There's no standard unique way that would +# work with all distros with a minimal package install. So, several +# methods are used here. +# +# By default, it will use lsb_release function. If not available, it will +# fail back to reading the known different places where the distro name +# is stored +# + +$system_release = qx(lsb_release -d) if which("lsb_release"); +$system_release =~ s/Description:\s*// if ($system_release); +$system_release = catcheck("/etc/system-release") if !$system_release; +$system_release = catcheck("/etc/redhat-release") if !$system_release; +$system_release = catcheck("/etc/lsb-release") if !$system_release; +$system_release = catcheck("/etc/gentoo-release") if !$system_release; + +# This seems more common than LSB these days +if (!$system_release) { + my %os_var; + if (open IN, "cat /etc/os-release|") { + while (<IN>) { + if (m/^([\w\d\_]+)=\"?([^\"]*)\"?\n/) { + $os_var{$1}=$2; + } + } + $system_release = $os_var{"NAME"}; + if (defined($os_var{"VERSION_ID"})) { + $system_release .= " " . $os_var{"VERSION_ID"} if (defined($os_var{"VERSION_ID"})); + } else { + $system_release .= " " . $os_var{"VERSION"}; + } + } +} +$system_release = catcheck("/etc/issue") if !$system_release; +$system_release =~ s/\s+$//; + +check_needs; diff --git a/src/net/scripts/split-man.pl b/src/net/scripts/split-man.pl new file mode 100755 index 0000000..96bd99d --- /dev/null +++ b/src/net/scripts/split-man.pl @@ -0,0 +1,28 @@ +#!/usr/bin/env perl +# SPDX-License-Identifier: GPL-2.0 +# +# Author: Mauro Carvalho Chehab <mchehab+samsung@kernel.org> +# +# Produce manpages from kernel-doc. +# See Documentation/doc-guide/kernel-doc.rst for instructions + +if ($#ARGV < 0) { + die "where do I put the results?\n"; +} + +mkdir $ARGV[0],0777; +$state = 0; +while (<STDIN>) { + if (/^\.TH \"[^\"]*\" 9 \"([^\"]*)\"/) { + if ($state == 1) { close OUT } + $state = 1; + $fn = "$ARGV[0]/$1.9"; + print STDERR "Creating $fn\n"; + open OUT, ">$fn" or die "can't open $fn: $!\n"; + print OUT $_; + } elsif ($state != 0) { + print OUT $_; + } +} + +close OUT; diff --git a/src/net/scripts/stackdelta b/src/net/scripts/stackdelta new file mode 100755 index 0000000..44d2dfd --- /dev/null +++ b/src/net/scripts/stackdelta @@ -0,0 +1,60 @@ +#!/usr/bin/env perl +# SPDX-License-Identifier: GPL-2.0 + +# Read two files produced by the stackusage script, and show the +# delta between them. +# +# Currently, only shows changes for functions listed in both files. We +# could add an option to show also functions which have vanished or +# appeared (which would often be due to gcc making other inlining +# decisions). +# +# Another possible option would be a minimum absolute value for the +# delta. +# +# A third possibility is for sorting by delta, but that can be +# achieved by piping to sort -k5,5g. + +sub read_stack_usage_file { + my %su; + my $f = shift; + open(my $fh, '<', $f) + or die "cannot open $f: $!"; + while (<$fh>) { + chomp; + my ($file, $func, $size, $type) = split; + # Old versions of gcc (at least 4.7) have an annoying quirk in + # that a (static) function whose name has been changed into + # for example ext4_find_unwritten_pgoff.isra.11 will show up + # in the .su file with a name of just "11". Since such a + # numeric suffix is likely to change across different + # commits/compilers/.configs or whatever else we're trying to + # tweak, we can't really track those functions, so we just + # silently skip them. + # + # Newer gcc (at least 5.0) report the full name, so again, + # since the suffix is likely to change, we strip it. + next if $func =~ m/^[0-9]+$/; + $func =~ s/\..*$//; + # Line numbers are likely to change; strip those. + $file =~ s/:[0-9]+$//; + $su{"${file}\t${func}"} = {size => $size, type => $type}; + } + close($fh); + return \%su; +} + +@ARGV == 2 + or die "usage: $0 <old> <new>"; + +my $old = read_stack_usage_file($ARGV[0]); +my $new = read_stack_usage_file($ARGV[1]); +my @common = sort grep {exists $new->{$_}} keys %$old; +for (@common) { + my $x = $old->{$_}{size}; + my $y = $new->{$_}{size}; + my $delta = $y - $x; + if ($delta) { + printf "%s\t%d\t%d\t%+d\n", $_, $x, $y, $delta; + } +} diff --git a/src/net/scripts/stackusage b/src/net/scripts/stackusage new file mode 100755 index 0000000..56ef1ab --- /dev/null +++ b/src/net/scripts/stackusage @@ -0,0 +1,34 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0 + +outfile="" +now=`date +%s` + +while [ $# -gt 0 ] +do + case "$1" in + -o) + outfile="$2" + shift 2;; + -h) + echo "usage: $0 [-o outfile] <make options/args>" + exit 0;; + *) break;; + esac +done + +if [ -z "$outfile" ] +then + outfile=`mktemp --tmpdir stackusage.$$.XXXX` +fi + +KCFLAGS="${KCFLAGS} -fstack-usage" make "$@" + +# Prepend directory name to file names, remove column information, +# make file:line/function/size/type properly tab-separated. +find . -name '*.su' -newermt "@${now}" -print | \ + xargs perl -MFile::Basename -pe \ + '$d = dirname($ARGV); s#([^:]+:[0-9]+):[0-9]+:#$d/$1\t#;' | \ + sort -k3,3nr > "${outfile}" + +echo "$0: output written to ${outfile}" diff --git a/src/net/scripts/subarch.include b/src/net/scripts/subarch.include new file mode 100644 index 0000000..c79e0d0 --- /dev/null +++ b/src/net/scripts/subarch.include @@ -0,0 +1,13 @@ +# SUBARCH tells the usermode build what the underlying arch is. That is set +# first, and if a usermode build is happening, the "ARCH=um" on the command +# line overrides the setting of ARCH below. If a native build is happening, +# then ARCH is assigned, getting whatever value it gets normally, and +# SUBARCH is subsequently ignored. + +SUBARCH := $(shell uname -m | sed -e s/i.86/x86/ -e s/x86_64/x86/ \ + -e s/sun4u/sparc64/ \ + -e s/arm.*/arm/ -e s/sa110/arm/ \ + -e s/s390x/s390/ -e s/parisc64/parisc/ \ + -e s/ppc.*/powerpc/ -e s/mips.*/mips/ \ + -e s/sh[234].*/sh/ -e s/aarch64.*/arm64/ \ + -e s/riscv.*/riscv/ -e s/loongarch.*/loongarch/) diff --git a/src/net/scripts/tags.sh b/src/net/scripts/tags.sh new file mode 100755 index 0000000..fd96734 --- /dev/null +++ b/src/net/scripts/tags.sh @@ -0,0 +1,330 @@ +#!/bin/bash +# SPDX-License-Identifier: GPL-2.0-only +# Generate tags or cscope files +# Usage tags.sh <mode> +# +# mode may be any of: tags, TAGS, cscope +# +# Uses the following environment variables: +# SUBARCH, SRCARCH, srctree + +if [ "$KBUILD_VERBOSE" = "1" ]; then + set -x +fi + +# RCS_FIND_IGNORE has escaped ()s -- remove them. +ignore="$(echo "$RCS_FIND_IGNORE" | sed 's|\\||g' )" +# tags and cscope files should also ignore MODVERSION *.mod.c files +ignore="$ignore ( -name *.mod.c ) -prune -o" + +# Use make KBUILD_ABS_SRCTREE=1 {tags|cscope} +# to force full paths for a non-O= build +if [ "${srctree}" = "." -o -z "${srctree}" ]; then + tree= +else + tree=${srctree}/ +fi + +# ignore userspace tools +if [ -n "$COMPILED_SOURCE" ]; then + ignore="$ignore ( -path ./tools ) -prune -o" +else + ignore="$ignore ( -path ${tree}tools ) -prune -o" +fi + +# Detect if ALLSOURCE_ARCHS is set. If not, we assume SRCARCH +if [ "${ALLSOURCE_ARCHS}" = "" ]; then + ALLSOURCE_ARCHS=${SRCARCH} +elif [ "${ALLSOURCE_ARCHS}" = "all" ]; then + ALLSOURCE_ARCHS=$(find ${tree}arch/ -mindepth 1 -maxdepth 1 -type d -printf '%f ') +fi + +# find sources in arch/$1 +find_arch_sources() +{ + for i in $archincludedir; do + prune="$prune -wholename $i -prune -o" + done + find ${tree}arch/$1 $ignore $prune -name "$2" -not -type l -print; +} + +# find sources in arch/$1/include +find_arch_include_sources() +{ + include=$(find ${tree}arch/$1/ -name include -type d -print); + if [ -n "$include" ]; then + archincludedir="$archincludedir $include" + find $include $ignore -name "$2" -not -type l -print; + fi +} + +# find sources in include/ +find_include_sources() +{ + find ${tree}include $ignore -name config -prune -o -name "$1" \ + -not -type l -print; +} + +# find sources in rest of tree +# we could benefit from a list of dirs to search in here +find_other_sources() +{ + find ${tree}* $ignore \ + \( -path ${tree}include -o -path ${tree}arch -o -name '.tmp_*' \) -prune -o \ + -name "$1" -not -type l -print; +} + +find_sources() +{ + find_arch_sources $1 "$2" +} + +all_sources() +{ + find_arch_include_sources ${SRCARCH} '*.[chS]' + if [ ! -z "$archinclude" ]; then + find_arch_include_sources $archinclude '*.[chS]' + fi + find_include_sources '*.[chS]' + for arch in $ALLSOURCE_ARCHS + do + find_sources $arch '*.[chS]' + done + find_other_sources '*.[chS]' +} + +all_compiled_sources() +{ + realpath -es $([ -z "$KBUILD_ABS_SRCTREE" ] && echo --relative-to=.) \ + include/generated/autoconf.h $(find $ignore -name "*.cmd" -exec \ + grep -Poh '(?(?=^source_.* \K).*|(?=^ \K\S).*(?= \\))' {} \+ | + awk '!a[$0]++') | sort -u +} + +all_target_sources() +{ + if [ -n "$COMPILED_SOURCE" ]; then + all_compiled_sources + else + all_sources + fi +} + +all_kconfigs() +{ + find ${tree}arch/ -maxdepth 1 $ignore \ + -name "Kconfig*" -not -type l -print; + for arch in $ALLSOURCE_ARCHS; do + find_sources $arch 'Kconfig*' + done + find_other_sources 'Kconfig*' +} + +docscope() +{ + (echo \-k; echo \-q; all_target_sources) > cscope.files + cscope -b -f cscope.out +} + +dogtags() +{ + all_target_sources | gtags -i -f - +} + +# Basic regular expressions with an optional /kind-spec/ for ctags and +# the following limitations: +# - No regex modifiers +# - Use \{0,1\} instead of \?, because etags expects an unescaped ? +# - \s is not working with etags, use a space or [ \t] +# - \w works, but does not match underscores in etags +# - etags regular expressions have to match at the start of a line; +# a ^[^#] is prepended by setup_regex unless an anchor is already present +regex_asm=( + '/^\(ENTRY\|_GLOBAL\)(\([[:alnum:]_\\]*\)).*/\2/' +) +regex_c=( + '/^SYSCALL_DEFINE[0-9](\([[:alnum:]_]*\).*/sys_\1/' + '/^BPF_CALL_[0-9](\([[:alnum:]_]*\).*/\1/' + '/^COMPAT_SYSCALL_DEFINE[0-9](\([[:alnum:]_]*\).*/compat_sys_\1/' + '/^TRACE_EVENT(\([[:alnum:]_]*\).*/trace_\1/' + '/^TRACE_EVENT(\([[:alnum:]_]*\).*/trace_\1_rcuidle/' + '/^DEFINE_EVENT([^,)]*, *\([[:alnum:]_]*\).*/trace_\1/' + '/^DEFINE_EVENT([^,)]*, *\([[:alnum:]_]*\).*/trace_\1_rcuidle/' + '/^DEFINE_INSN_CACHE_OPS(\([[:alnum:]_]*\).*/get_\1_slot/' + '/^DEFINE_INSN_CACHE_OPS(\([[:alnum:]_]*\).*/free_\1_slot/' + '/^PAGEFLAG(\([[:alnum:]_]*\).*/Page\1/' + '/^PAGEFLAG(\([[:alnum:]_]*\).*/SetPage\1/' + '/^PAGEFLAG(\([[:alnum:]_]*\).*/ClearPage\1/' + '/^TESTSETFLAG(\([[:alnum:]_]*\).*/TestSetPage\1/' + '/^TESTPAGEFLAG(\([[:alnum:]_]*\).*/Page\1/' + '/^SETPAGEFLAG(\([[:alnum:]_]*\).*/SetPage\1/' + '/\<__SETPAGEFLAG(\([[:alnum:]_]*\).*/__SetPage\1/' + '/\<TESTCLEARFLAG(\([[:alnum:]_]*\).*/TestClearPage\1/' + '/\<__TESTCLEARFLAG(\([[:alnum:]_]*\).*/TestClearPage\1/' + '/\<CLEARPAGEFLAG(\([[:alnum:]_]*\).*/ClearPage\1/' + '/\<__CLEARPAGEFLAG(\([[:alnum:]_]*\).*/__ClearPage\1/' + '/^__PAGEFLAG(\([[:alnum:]_]*\).*/__SetPage\1/' + '/^__PAGEFLAG(\([[:alnum:]_]*\).*/__ClearPage\1/' + '/^PAGEFLAG_FALSE(\([[:alnum:]_]*\).*/Page\1/' + '/\<TESTSCFLAG(\([[:alnum:]_]*\).*/TestSetPage\1/' + '/\<TESTSCFLAG(\([[:alnum:]_]*\).*/TestClearPage\1/' + '/\<SETPAGEFLAG_NOOP(\([[:alnum:]_]*\).*/SetPage\1/' + '/\<CLEARPAGEFLAG_NOOP(\([[:alnum:]_]*\).*/ClearPage\1/' + '/\<__CLEARPAGEFLAG_NOOP(\([[:alnum:]_]*\).*/__ClearPage\1/' + '/\<TESTCLEARFLAG_FALSE(\([[:alnum:]_]*\).*/TestClearPage\1/' + '/^PAGE_TYPE_OPS(\([[:alnum:]_]*\).*/Page\1/' + '/^PAGE_TYPE_OPS(\([[:alnum:]_]*\).*/__SetPage\1/' + '/^PAGE_TYPE_OPS(\([[:alnum:]_]*\).*/__ClearPage\1/' + '/^TASK_PFA_TEST([^,]*, *\([[:alnum:]_]*\))/task_\1/' + '/^TASK_PFA_SET([^,]*, *\([[:alnum:]_]*\))/task_set_\1/' + '/^TASK_PFA_CLEAR([^,]*, *\([[:alnum:]_]*\))/task_clear_\1/' + '/^DEF_MMIO_\(IN\|OUT\)_[XD](\([[:alnum:]_]*\),[^)]*)/\2/' + '/^DEBUGGER_BOILERPLATE(\([[:alnum:]_]*\))/\1/' + '/^DEF_PCI_AC_\(\|NO\)RET(\([[:alnum:]_]*\).*/\2/' + '/^PCI_OP_READ(\(\w*\).*[1-4])/pci_bus_read_config_\1/' + '/^PCI_OP_WRITE(\(\w*\).*[1-4])/pci_bus_write_config_\1/' + '/\<DEFINE_\(RT_MUTEX\|MUTEX\|SEMAPHORE\|SPINLOCK\)(\([[:alnum:]_]*\)/\2/v/' + '/\<DEFINE_\(RAW_SPINLOCK\|RWLOCK\|SEQLOCK\)(\([[:alnum:]_]*\)/\2/v/' + '/\<DECLARE_\(RWSEM\|COMPLETION\)(\([[:alnum:]_]\+\)/\2/v/' + '/\<DECLARE_BITMAP(\([[:alnum:]_]*\)/\1/v/' + '/\(^\|\s\)\(\|L\|H\)LIST_HEAD(\([[:alnum:]_]*\)/\3/v/' + '/\(^\|\s\)RADIX_TREE(\([[:alnum:]_]*\)/\2/v/' + '/\<DEFINE_PER_CPU([^,]*, *\([[:alnum:]_]*\)/\1/v/' + '/\<DEFINE_PER_CPU_SHARED_ALIGNED([^,]*, *\([[:alnum:]_]*\)/\1/v/' + '/\<DECLARE_WAIT_QUEUE_HEAD(\([[:alnum:]_]*\)/\1/v/' + '/\<DECLARE_\(TASKLET\|WORK\|DELAYED_WORK\)(\([[:alnum:]_]*\)/\2/v/' + '/\(^\s\)OFFSET(\([[:alnum:]_]*\)/\2/v/' + '/\(^\s\)DEFINE(\([[:alnum:]_]*\)/\2/v/' + '/\<\(DEFINE\|DECLARE\)_HASHTABLE(\([[:alnum:]_]*\)/\2/v/' + '/\<DEFINE_ID\(R\|A\)(\([[:alnum:]_]\+\)/\2/' + '/\<DEFINE_WD_CLASS(\([[:alnum:]_]\+\)/\1/' + '/\<ATOMIC_NOTIFIER_HEAD(\([[:alnum:]_]\+\)/\1/' + '/\<RAW_NOTIFIER_HEAD(\([[:alnum:]_]\+\)/\1/' + '/\<DECLARE_FAULT_ATTR(\([[:alnum:]_]\+\)/\1/' + '/\<BLOCKING_NOTIFIER_HEAD(\([[:alnum:]_]\+\)/\1/' + '/\<DEVICE_ATTR_\(RW\|RO\|WO\)(\([[:alnum:]_]\+\)/dev_attr_\2/' + '/\<DRIVER_ATTR_\(RW\|RO\|WO\)(\([[:alnum:]_]\+\)/driver_attr_\2/' + '/\<\(DEFINE\|DECLARE\)_STATIC_KEY_\(TRUE\|FALSE\)\(\|_RO\)(\([[:alnum:]_]\+\)/\4/' + '/^SEQCOUNT_LOCKTYPE(\([^,]*\),[[:space:]]*\([^,]*\),[^)]*)/seqcount_\2_t/' + '/^SEQCOUNT_LOCKTYPE(\([^,]*\),[[:space:]]*\([^,]*\),[^)]*)/seqcount_\2_init/' +) +regex_kconfig=( + '/^[[:blank:]]*\(menu\|\)config[[:blank:]]\+\([[:alnum:]_]\+\)/\2/' + '/^[[:blank:]]*\(menu\|\)config[[:blank:]]\+\([[:alnum:]_]\+\)/CONFIG_\2/' +) +setup_regex() +{ + local mode=$1 lang tmp=() r + shift + + regex=() + for lang; do + case "$lang" in + asm) tmp=("${regex_asm[@]}") ;; + c) tmp=("${regex_c[@]}") ;; + kconfig) tmp=("${regex_kconfig[@]}") ;; + esac + for r in "${tmp[@]}"; do + if test "$mode" = "exuberant"; then + regex[${#regex[@]}]="--regex-$lang=${r}b" + else + # Remove ctags /kind-spec/ + case "$r" in + /*/*/?/) + r=${r%?/} + esac + # Prepend ^[^#] unless already anchored + case "$r" in + /^*) ;; + *) + r="/^[^#]*${r#/}" + esac + regex[${#regex[@]}]="--regex=$r" + fi + done + done +} + +exuberant() +{ + setup_regex exuberant asm c + all_target_sources | xargs $1 -a \ + -I __initdata,__exitdata,__initconst,__ro_after_init \ + -I __initdata_memblock \ + -I __refdata,__attribute,__maybe_unused,__always_unused \ + -I __acquires,__releases,__deprecated,__always_inline \ + -I __read_mostly,__aligned,____cacheline_aligned \ + -I ____cacheline_aligned_in_smp \ + -I __cacheline_aligned,__cacheline_aligned_in_smp \ + -I ____cacheline_internodealigned_in_smp \ + -I __used,__packed,__packed2__,__must_check,__must_hold \ + -I EXPORT_SYMBOL,EXPORT_SYMBOL_GPL,ACPI_EXPORT_SYMBOL \ + -I DEFINE_TRACE,EXPORT_TRACEPOINT_SYMBOL,EXPORT_TRACEPOINT_SYMBOL_GPL \ + -I static,const \ + --extra=+fq --c-kinds=+px --fields=+iaS --langmap=c:+.h \ + "${regex[@]}" + + setup_regex exuberant kconfig + all_kconfigs | xargs $1 -a \ + --langdef=kconfig --language-force=kconfig "${regex[@]}" + +} + +emacs() +{ + setup_regex emacs asm c + all_target_sources | xargs $1 -a "${regex[@]}" + + setup_regex emacs kconfig + all_kconfigs | xargs $1 -a "${regex[@]}" +} + +xtags() +{ + if $1 --version 2>&1 | grep -iq exuberant; then + exuberant $1 + elif $1 --version 2>&1 | grep -iq emacs; then + emacs $1 + else + all_target_sources | xargs $1 -a + fi +} + +# Support um (which uses SUBARCH) +if [ "${ARCH}" = "um" ]; then + if [ "$SUBARCH" = "i386" ]; then + archinclude=x86 + elif [ "$SUBARCH" = "x86_64" ]; then + archinclude=x86 + else + archinclude=${SUBARCH} + fi +fi + +remove_structs= +case "$1" in + "cscope") + docscope + ;; + + "gtags") + dogtags + ;; + + "tags") + rm -f tags + xtags ctags + remove_structs=y + ;; + + "TAGS") + rm -f TAGS + xtags etags + remove_structs=y + ;; +esac + +# Remove structure forward declarations. +if [ -n "$remove_structs" ]; then + LANG=C sed -i -e '/^\([a-zA-Z_][a-zA-Z0-9_]*\)\t.*\t\/\^struct \1;.*\$\/;"\tx$/d' $1 +fi diff --git a/src/net/scripts/tools-support-relr.sh b/src/net/scripts/tools-support-relr.sh new file mode 100755 index 0000000..cb55878 --- /dev/null +++ b/src/net/scripts/tools-support-relr.sh @@ -0,0 +1,17 @@ +#!/bin/sh -eu +# SPDX-License-Identifier: GPL-2.0 + +tmp_file=$(mktemp) +trap "rm -f $tmp_file.o $tmp_file $tmp_file.bin" EXIT + +cat << "END" | $CC -c -x c - -o $tmp_file.o >/dev/null 2>&1 +void *p = &p; +END +$LD $tmp_file.o -shared -Bsymbolic --pack-dyn-relocs=relr \ + --use-android-relr-tags -o $tmp_file + +# Despite printing an error message, GNU nm still exits with exit code 0 if it +# sees a relr section. So we need to check that nothing is printed to stderr. +test -z "$($NM $tmp_file 2>&1 >/dev/null)" + +$OBJCOPY -O binary $tmp_file $tmp_file.bin diff --git a/src/net/scripts/tracing/draw_functrace.py b/src/net/scripts/tracing/draw_functrace.py new file mode 100755 index 0000000..7011fbe --- /dev/null +++ b/src/net/scripts/tracing/draw_functrace.py @@ -0,0 +1,129 @@ +#!/usr/bin/env python +# SPDX-License-Identifier: GPL-2.0-only + +""" +Copyright 2008 (c) Frederic Weisbecker <fweisbec@gmail.com> + +This script parses a trace provided by the function tracer in +kernel/trace/trace_functions.c +The resulted trace is processed into a tree to produce a more human +view of the call stack by drawing textual but hierarchical tree of +calls. Only the functions's names and the the call time are provided. + +Usage: + Be sure that you have CONFIG_FUNCTION_TRACER + # mount -t debugfs nodev /sys/kernel/debug + # echo function > /sys/kernel/debug/tracing/current_tracer + $ cat /sys/kernel/debug/tracing/trace_pipe > ~/raw_trace_func + Wait some times but not too much, the script is a bit slow. + Break the pipe (Ctrl + Z) + $ scripts/tracing/draw_functrace.py < ~/raw_trace_func > draw_functrace + Then you have your drawn trace in draw_functrace +""" + + +import sys, re + +class CallTree: + """ This class provides a tree representation of the functions + call stack. If a function has no parent in the kernel (interrupt, + syscall, kernel thread...) then it is attached to a virtual parent + called ROOT. + """ + ROOT = None + + def __init__(self, func, time = None, parent = None): + self._func = func + self._time = time + if parent is None: + self._parent = CallTree.ROOT + else: + self._parent = parent + self._children = [] + + def calls(self, func, calltime): + """ If a function calls another one, call this method to insert it + into the tree at the appropriate place. + @return: A reference to the newly created child node. + """ + child = CallTree(func, calltime, self) + self._children.append(child) + return child + + def getParent(self, func): + """ Retrieve the last parent of the current node that + has the name given by func. If this function is not + on a parent, then create it as new child of root + @return: A reference to the parent. + """ + tree = self + while tree != CallTree.ROOT and tree._func != func: + tree = tree._parent + if tree == CallTree.ROOT: + child = CallTree.ROOT.calls(func, None) + return child + return tree + + def __repr__(self): + return self.__toString("", True) + + def __toString(self, branch, lastChild): + if self._time is not None: + s = "%s----%s (%s)\n" % (branch, self._func, self._time) + else: + s = "%s----%s\n" % (branch, self._func) + + i = 0 + if lastChild: + branch = branch[:-1] + " " + while i < len(self._children): + if i != len(self._children) - 1: + s += "%s" % self._children[i].__toString(branch +\ + " |", False) + else: + s += "%s" % self._children[i].__toString(branch +\ + " |", True) + i += 1 + return s + +class BrokenLineException(Exception): + """If the last line is not complete because of the pipe breakage, + we want to stop the processing and ignore this line. + """ + pass + +class CommentLineException(Exception): + """ If the line is a comment (as in the beginning of the trace file), + just ignore it. + """ + pass + + +def parseLine(line): + line = line.strip() + if line.startswith("#"): + raise CommentLineException + m = re.match("[^]]+?\\] +([a-z.]+) +([0-9.]+): (\\w+) <-(\\w+)", line) + if m is None: + raise BrokenLineException + return (m.group(2), m.group(3), m.group(4)) + + +def main(): + CallTree.ROOT = CallTree("Root (Nowhere)", None, None) + tree = CallTree.ROOT + + for line in sys.stdin: + try: + calltime, callee, caller = parseLine(line) + except BrokenLineException: + break + except CommentLineException: + continue + tree = tree.getParent(caller) + tree = tree.calls(callee, calltime) + + print(CallTree.ROOT) + +if __name__ == "__main__": + main() diff --git a/src/net/scripts/tracing/ftrace-bisect.sh b/src/net/scripts/tracing/ftrace-bisect.sh new file mode 100755 index 0000000..9267011 --- /dev/null +++ b/src/net/scripts/tracing/ftrace-bisect.sh @@ -0,0 +1,116 @@ +#!/bin/bash +# SPDX-License-Identifier: GPL-2.0 +# +# Here's how to use this: +# +# This script is used to help find functions that are being traced by function +# tracer or function graph tracing that causes the machine to reboot, hang, or +# crash. Here's the steps to take. +# +# First, determine if function tracing is working with a single function: +# +# (note, if this is a problem with function_graph tracing, then simply +# replace "function" with "function_graph" in the following steps). +# +# # cd /sys/kernel/debug/tracing +# # echo schedule > set_ftrace_filter +# # echo function > current_tracer +# +# If this works, then we know that something is being traced that shouldn't be. +# +# # echo nop > current_tracer +# +# # cat available_filter_functions > ~/full-file +# # ftrace-bisect ~/full-file ~/test-file ~/non-test-file +# # cat ~/test-file > set_ftrace_filter +# +# *** Note *** this will take several minutes. Setting multiple functions is +# an O(n^2) operation, and we are dealing with thousands of functions. So go +# have coffee, talk with your coworkers, read facebook. And eventually, this +# operation will end. +# +# # echo function > current_tracer +# +# If it crashes, we know that ~/test-file has a bad function. +# +# Reboot back to test kernel. +# +# # cd /sys/kernel/debug/tracing +# # mv ~/test-file ~/full-file +# +# If it didn't crash. +# +# # echo nop > current_tracer +# # mv ~/non-test-file ~/full-file +# +# Get rid of the other test file from previous run (or save them off somewhere). +# # rm -f ~/test-file ~/non-test-file +# +# And start again: +# +# # ftrace-bisect ~/full-file ~/test-file ~/non-test-file +# +# The good thing is, because this cuts the number of functions in ~/test-file +# by half, the cat of it into set_ftrace_filter takes half as long each +# iteration, so don't talk so much at the water cooler the second time. +# +# Eventually, if you did this correctly, you will get down to the problem +# function, and all we need to do is to notrace it. +# +# The way to figure out if the problem function is bad, just do: +# +# # echo <problem-function> > set_ftrace_notrace +# # echo > set_ftrace_filter +# # echo function > current_tracer +# +# And if it doesn't crash, we are done. +# +# If it does crash, do this again (there's more than one problem function) +# but you need to echo the problem function(s) into set_ftrace_notrace before +# enabling function tracing in the above steps. Or if you can compile the +# kernel, annotate the problem functions with "notrace" and start again. +# + + +if [ $# -ne 3 ]; then + echo 'usage: ftrace-bisect full-file test-file non-test-file' + exit +fi + +full=$1 +test=$2 +nontest=$3 + +x=`cat $full | wc -l` +if [ $x -eq 1 ]; then + echo "There's only one function left, must be the bad one" + cat $full + exit 0 +fi + +let x=$x/2 +let y=$x+1 + +if [ ! -f $full ]; then + echo "$full does not exist" + exit 1 +fi + +if [ -f $test ]; then + echo -n "$test exists, delete it? [y/N]" + read a + if [ "$a" != "y" -a "$a" != "Y" ]; then + exit 1 + fi +fi + +if [ -f $nontest ]; then + echo -n "$nontest exists, delete it? [y/N]" + read a + if [ "$a" != "y" -a "$a" != "Y" ]; then + exit 1 + fi +fi + +sed -ne "1,${x}p" $full > $test +sed -ne "$y,\$p" $full > $nontest diff --git a/src/net/scripts/unifdef.c b/src/net/scripts/unifdef.c new file mode 100644 index 0000000..db00e3e --- /dev/null +++ b/src/net/scripts/unifdef.c @@ -0,0 +1,1225 @@ +/* + * Copyright (c) 2002 - 2011 Tony Finch <dot@dotat.at> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * unifdef - remove ifdef'ed lines + * + * This code was derived from software contributed to Berkeley by Dave Yost. + * It was rewritten to support ANSI C by Tony Finch. The original version + * of unifdef carried the 4-clause BSD copyright licence. None of its code + * remains in this version (though some of the names remain) so it now + * carries a more liberal licence. + * + * Wishlist: + * provide an option which will append the name of the + * appropriate symbol after #else's and #endif's + * provide an option which will check symbols after + * #else's and #endif's to see that they match their + * corresponding #ifdef or #ifndef + * + * These require better buffer handling, which would also make + * it possible to handle all "dodgy" directives correctly. + */ + +#include <sys/types.h> +#include <sys/stat.h> + +#include <ctype.h> +#include <err.h> +#include <errno.h> +#include <stdarg.h> +#include <stdbool.h> +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <unistd.h> + +const char copyright[] = + "@(#) $Version: unifdef-2.5 $\n" + "@(#) $Author: Tony Finch (dot@dotat.at) $\n" + "@(#) $URL: http://dotat.at/prog/unifdef $\n" +; + +/* types of input lines: */ +typedef enum { + LT_TRUEI, /* a true #if with ignore flag */ + LT_FALSEI, /* a false #if with ignore flag */ + LT_IF, /* an unknown #if */ + LT_TRUE, /* a true #if */ + LT_FALSE, /* a false #if */ + LT_ELIF, /* an unknown #elif */ + LT_ELTRUE, /* a true #elif */ + LT_ELFALSE, /* a false #elif */ + LT_ELSE, /* #else */ + LT_ENDIF, /* #endif */ + LT_DODGY, /* flag: directive is not on one line */ + LT_DODGY_LAST = LT_DODGY + LT_ENDIF, + LT_PLAIN, /* ordinary line */ + LT_EOF, /* end of file */ + LT_ERROR, /* unevaluable #if */ + LT_COUNT +} Linetype; + +static char const * const linetype_name[] = { + "TRUEI", "FALSEI", "IF", "TRUE", "FALSE", + "ELIF", "ELTRUE", "ELFALSE", "ELSE", "ENDIF", + "DODGY TRUEI", "DODGY FALSEI", + "DODGY IF", "DODGY TRUE", "DODGY FALSE", + "DODGY ELIF", "DODGY ELTRUE", "DODGY ELFALSE", + "DODGY ELSE", "DODGY ENDIF", + "PLAIN", "EOF", "ERROR" +}; + +/* state of #if processing */ +typedef enum { + IS_OUTSIDE, + IS_FALSE_PREFIX, /* false #if followed by false #elifs */ + IS_TRUE_PREFIX, /* first non-false #(el)if is true */ + IS_PASS_MIDDLE, /* first non-false #(el)if is unknown */ + IS_FALSE_MIDDLE, /* a false #elif after a pass state */ + IS_TRUE_MIDDLE, /* a true #elif after a pass state */ + IS_PASS_ELSE, /* an else after a pass state */ + IS_FALSE_ELSE, /* an else after a true state */ + IS_TRUE_ELSE, /* an else after only false states */ + IS_FALSE_TRAILER, /* #elifs after a true are false */ + IS_COUNT +} Ifstate; + +static char const * const ifstate_name[] = { + "OUTSIDE", "FALSE_PREFIX", "TRUE_PREFIX", + "PASS_MIDDLE", "FALSE_MIDDLE", "TRUE_MIDDLE", + "PASS_ELSE", "FALSE_ELSE", "TRUE_ELSE", + "FALSE_TRAILER" +}; + +/* state of comment parser */ +typedef enum { + NO_COMMENT = false, /* outside a comment */ + C_COMMENT, /* in a comment like this one */ + CXX_COMMENT, /* between // and end of line */ + STARTING_COMMENT, /* just after slash-backslash-newline */ + FINISHING_COMMENT, /* star-backslash-newline in a C comment */ + CHAR_LITERAL, /* inside '' */ + STRING_LITERAL /* inside "" */ +} Comment_state; + +static char const * const comment_name[] = { + "NO", "C", "CXX", "STARTING", "FINISHING", "CHAR", "STRING" +}; + +/* state of preprocessor line parser */ +typedef enum { + LS_START, /* only space and comments on this line */ + LS_HASH, /* only space, comments, and a hash */ + LS_DIRTY /* this line can't be a preprocessor line */ +} Line_state; + +static char const * const linestate_name[] = { + "START", "HASH", "DIRTY" +}; + +/* + * Minimum translation limits from ISO/IEC 9899:1999 5.2.4.1 + */ +#define MAXDEPTH 64 /* maximum #if nesting */ +#define MAXLINE 4096 /* maximum length of line */ +#define MAXSYMS 4096 /* maximum number of symbols */ + +/* + * Sometimes when editing a keyword the replacement text is longer, so + * we leave some space at the end of the tline buffer to accommodate this. + */ +#define EDITSLOP 10 + +/* + * For temporary filenames + */ +#define TEMPLATE "unifdef.XXXXXX" + +/* + * Globals. + */ + +static bool compblank; /* -B: compress blank lines */ +static bool lnblank; /* -b: blank deleted lines */ +static bool complement; /* -c: do the complement */ +static bool debugging; /* -d: debugging reports */ +static bool iocccok; /* -e: fewer IOCCC errors */ +static bool strictlogic; /* -K: keep ambiguous #ifs */ +static bool killconsts; /* -k: eval constant #ifs */ +static bool lnnum; /* -n: add #line directives */ +static bool symlist; /* -s: output symbol list */ +static bool symdepth; /* -S: output symbol depth */ +static bool text; /* -t: this is a text file */ + +static const char *symname[MAXSYMS]; /* symbol name */ +static const char *value[MAXSYMS]; /* -Dsym=value */ +static bool ignore[MAXSYMS]; /* -iDsym or -iUsym */ +static int nsyms; /* number of symbols */ + +static FILE *input; /* input file pointer */ +static const char *filename; /* input file name */ +static int linenum; /* current line number */ +static FILE *output; /* output file pointer */ +static const char *ofilename; /* output file name */ +static bool overwriting; /* output overwrites input */ +static char tempname[FILENAME_MAX]; /* used when overwriting */ + +static char tline[MAXLINE+EDITSLOP];/* input buffer plus space */ +static char *keyword; /* used for editing #elif's */ + +static const char *newline; /* input file format */ +static const char newline_unix[] = "\n"; +static const char newline_crlf[] = "\r\n"; + +static Comment_state incomment; /* comment parser state */ +static Line_state linestate; /* #if line parser state */ +static Ifstate ifstate[MAXDEPTH]; /* #if processor state */ +static bool ignoring[MAXDEPTH]; /* ignore comments state */ +static int stifline[MAXDEPTH]; /* start of current #if */ +static int depth; /* current #if nesting */ +static int delcount; /* count of deleted lines */ +static unsigned blankcount; /* count of blank lines */ +static unsigned blankmax; /* maximum recent blankcount */ +static bool constexpr; /* constant #if expression */ +static bool zerosyms = true; /* to format symdepth output */ +static bool firstsym; /* ditto */ + +static int exitstat; /* program exit status */ + +static void addsym(bool, bool, char *); +static void closeout(void); +static void debug(const char *, ...); +static void done(void); +static void error(const char *); +static int findsym(const char *); +static void flushline(bool); +static Linetype parseline(void); +static Linetype ifeval(const char **); +static void ignoreoff(void); +static void ignoreon(void); +static void keywordedit(const char *); +static void nest(void); +static void process(void); +static const char *skipargs(const char *); +static const char *skipcomment(const char *); +static const char *skipsym(const char *); +static void state(Ifstate); +static int strlcmp(const char *, const char *, size_t); +static void unnest(void); +static void usage(void); +static void version(void); + +#define endsym(c) (!isalnum((unsigned char)c) && c != '_') + +/* + * The main program. + */ +int +main(int argc, char *argv[]) +{ + int opt; + + while ((opt = getopt(argc, argv, "i:D:U:I:o:bBcdeKklnsStV")) != -1) + switch (opt) { + case 'i': /* treat stuff controlled by these symbols as text */ + /* + * For strict backwards-compatibility the U or D + * should be immediately after the -i but it doesn't + * matter much if we relax that requirement. + */ + opt = *optarg++; + if (opt == 'D') + addsym(true, true, optarg); + else if (opt == 'U') + addsym(true, false, optarg); + else + usage(); + break; + case 'D': /* define a symbol */ + addsym(false, true, optarg); + break; + case 'U': /* undef a symbol */ + addsym(false, false, optarg); + break; + case 'I': /* no-op for compatibility with cpp */ + break; + case 'b': /* blank deleted lines instead of omitting them */ + case 'l': /* backwards compatibility */ + lnblank = true; + break; + case 'B': /* compress blank lines around removed section */ + compblank = true; + break; + case 'c': /* treat -D as -U and vice versa */ + complement = true; + break; + case 'd': + debugging = true; + break; + case 'e': /* fewer errors from dodgy lines */ + iocccok = true; + break; + case 'K': /* keep ambiguous #ifs */ + strictlogic = true; + break; + case 'k': /* process constant #ifs */ + killconsts = true; + break; + case 'n': /* add #line directive after deleted lines */ + lnnum = true; + break; + case 'o': /* output to a file */ + ofilename = optarg; + break; + case 's': /* only output list of symbols that control #ifs */ + symlist = true; + break; + case 'S': /* list symbols with their nesting depth */ + symlist = symdepth = true; + break; + case 't': /* don't parse C comments */ + text = true; + break; + case 'V': /* print version */ + version(); + default: + usage(); + } + argc -= optind; + argv += optind; + if (compblank && lnblank) + errx(2, "-B and -b are mutually exclusive"); + if (argc > 1) { + errx(2, "can only do one file"); + } else if (argc == 1 && strcmp(*argv, "-") != 0) { + filename = *argv; + input = fopen(filename, "rb"); + if (input == NULL) + err(2, "can't open %s", filename); + } else { + filename = "[stdin]"; + input = stdin; + } + if (ofilename == NULL) { + ofilename = "[stdout]"; + output = stdout; + } else { + struct stat ist, ost; + if (stat(ofilename, &ost) == 0 && + fstat(fileno(input), &ist) == 0) + overwriting = (ist.st_dev == ost.st_dev + && ist.st_ino == ost.st_ino); + if (overwriting) { + const char *dirsep; + int ofd; + + dirsep = strrchr(ofilename, '/'); + if (dirsep != NULL) + snprintf(tempname, sizeof(tempname), + "%.*s/" TEMPLATE, + (int)(dirsep - ofilename), ofilename); + else + snprintf(tempname, sizeof(tempname), + TEMPLATE); + ofd = mkstemp(tempname); + if (ofd != -1) + output = fdopen(ofd, "wb+"); + if (output == NULL) + err(2, "can't create temporary file"); + fchmod(ofd, ist.st_mode & (S_IRWXU|S_IRWXG|S_IRWXO)); + } else { + output = fopen(ofilename, "wb"); + if (output == NULL) + err(2, "can't open %s", ofilename); + } + } + process(); + abort(); /* bug */ +} + +static void +version(void) +{ + const char *c = copyright; + for (;;) { + while (*++c != '$') + if (*c == '\0') + exit(0); + while (*++c != '$') + putc(*c, stderr); + putc('\n', stderr); + } +} + +static void +usage(void) +{ + fprintf(stderr, "usage: unifdef [-bBcdeKknsStV] [-Ipath]" + " [-Dsym[=val]] [-Usym] [-iDsym[=val]] [-iUsym] ... [file]\n"); + exit(2); +} + +/* + * A state transition function alters the global #if processing state + * in a particular way. The table below is indexed by the current + * processing state and the type of the current line. + * + * Nesting is handled by keeping a stack of states; some transition + * functions increase or decrease the depth. They also maintain the + * ignore state on a stack. In some complicated cases they have to + * alter the preprocessor directive, as follows. + * + * When we have processed a group that starts off with a known-false + * #if/#elif sequence (which has therefore been deleted) followed by a + * #elif that we don't understand and therefore must keep, we edit the + * latter into a #if to keep the nesting correct. We use memcpy() to + * overwrite the 4 byte token "elif" with "if " without a '\0' byte. + * + * When we find a true #elif in a group, the following block will + * always be kept and the rest of the sequence after the next #elif or + * #else will be discarded. We edit the #elif into a #else and the + * following directive to #endif since this has the desired behaviour. + * + * "Dodgy" directives are split across multiple lines, the most common + * example being a multi-line comment hanging off the right of the + * directive. We can handle them correctly only if there is no change + * from printing to dropping (or vice versa) caused by that directive. + * If the directive is the first of a group we have a choice between + * failing with an error, or passing it through unchanged instead of + * evaluating it. The latter is not the default to avoid questions from + * users about unifdef unexpectedly leaving behind preprocessor directives. + */ +typedef void state_fn(void); + +/* report an error */ +static void Eelif (void) { error("Inappropriate #elif"); } +static void Eelse (void) { error("Inappropriate #else"); } +static void Eendif(void) { error("Inappropriate #endif"); } +static void Eeof (void) { error("Premature EOF"); } +static void Eioccc(void) { error("Obfuscated preprocessor control line"); } +/* plain line handling */ +static void print (void) { flushline(true); } +static void drop (void) { flushline(false); } +/* output lacks group's start line */ +static void Strue (void) { drop(); ignoreoff(); state(IS_TRUE_PREFIX); } +static void Sfalse(void) { drop(); ignoreoff(); state(IS_FALSE_PREFIX); } +static void Selse (void) { drop(); state(IS_TRUE_ELSE); } +/* print/pass this block */ +static void Pelif (void) { print(); ignoreoff(); state(IS_PASS_MIDDLE); } +static void Pelse (void) { print(); state(IS_PASS_ELSE); } +static void Pendif(void) { print(); unnest(); } +/* discard this block */ +static void Dfalse(void) { drop(); ignoreoff(); state(IS_FALSE_TRAILER); } +static void Delif (void) { drop(); ignoreoff(); state(IS_FALSE_MIDDLE); } +static void Delse (void) { drop(); state(IS_FALSE_ELSE); } +static void Dendif(void) { drop(); unnest(); } +/* first line of group */ +static void Fdrop (void) { nest(); Dfalse(); } +static void Fpass (void) { nest(); Pelif(); } +static void Ftrue (void) { nest(); Strue(); } +static void Ffalse(void) { nest(); Sfalse(); } +/* variable pedantry for obfuscated lines */ +static void Oiffy (void) { if (!iocccok) Eioccc(); Fpass(); ignoreon(); } +static void Oif (void) { if (!iocccok) Eioccc(); Fpass(); } +static void Oelif (void) { if (!iocccok) Eioccc(); Pelif(); } +/* ignore comments in this block */ +static void Idrop (void) { Fdrop(); ignoreon(); } +static void Itrue (void) { Ftrue(); ignoreon(); } +static void Ifalse(void) { Ffalse(); ignoreon(); } +/* modify this line */ +static void Mpass (void) { memcpy(keyword, "if ", 4); Pelif(); } +static void Mtrue (void) { keywordedit("else"); state(IS_TRUE_MIDDLE); } +static void Melif (void) { keywordedit("endif"); state(IS_FALSE_TRAILER); } +static void Melse (void) { keywordedit("endif"); state(IS_FALSE_ELSE); } + +static state_fn * const trans_table[IS_COUNT][LT_COUNT] = { +/* IS_OUTSIDE */ +{ Itrue, Ifalse,Fpass, Ftrue, Ffalse,Eelif, Eelif, Eelif, Eelse, Eendif, + Oiffy, Oiffy, Fpass, Oif, Oif, Eelif, Eelif, Eelif, Eelse, Eendif, + print, done, abort }, +/* IS_FALSE_PREFIX */ +{ Idrop, Idrop, Fdrop, Fdrop, Fdrop, Mpass, Strue, Sfalse,Selse, Dendif, + Idrop, Idrop, Fdrop, Fdrop, Fdrop, Mpass, Eioccc,Eioccc,Eioccc,Eioccc, + drop, Eeof, abort }, +/* IS_TRUE_PREFIX */ +{ Itrue, Ifalse,Fpass, Ftrue, Ffalse,Dfalse,Dfalse,Dfalse,Delse, Dendif, + Oiffy, Oiffy, Fpass, Oif, Oif, Eioccc,Eioccc,Eioccc,Eioccc,Eioccc, + print, Eeof, abort }, +/* IS_PASS_MIDDLE */ +{ Itrue, Ifalse,Fpass, Ftrue, Ffalse,Pelif, Mtrue, Delif, Pelse, Pendif, + Oiffy, Oiffy, Fpass, Oif, Oif, Pelif, Oelif, Oelif, Pelse, Pendif, + print, Eeof, abort }, +/* IS_FALSE_MIDDLE */ +{ Idrop, Idrop, Fdrop, Fdrop, Fdrop, Pelif, Mtrue, Delif, Pelse, Pendif, + Idrop, Idrop, Fdrop, Fdrop, Fdrop, Eioccc,Eioccc,Eioccc,Eioccc,Eioccc, + drop, Eeof, abort }, +/* IS_TRUE_MIDDLE */ +{ Itrue, Ifalse,Fpass, Ftrue, Ffalse,Melif, Melif, Melif, Melse, Pendif, + Oiffy, Oiffy, Fpass, Oif, Oif, Eioccc,Eioccc,Eioccc,Eioccc,Pendif, + print, Eeof, abort }, +/* IS_PASS_ELSE */ +{ Itrue, Ifalse,Fpass, Ftrue, Ffalse,Eelif, Eelif, Eelif, Eelse, Pendif, + Oiffy, Oiffy, Fpass, Oif, Oif, Eelif, Eelif, Eelif, Eelse, Pendif, + print, Eeof, abort }, +/* IS_FALSE_ELSE */ +{ Idrop, Idrop, Fdrop, Fdrop, Fdrop, Eelif, Eelif, Eelif, Eelse, Dendif, + Idrop, Idrop, Fdrop, Fdrop, Fdrop, Eelif, Eelif, Eelif, Eelse, Eioccc, + drop, Eeof, abort }, +/* IS_TRUE_ELSE */ +{ Itrue, Ifalse,Fpass, Ftrue, Ffalse,Eelif, Eelif, Eelif, Eelse, Dendif, + Oiffy, Oiffy, Fpass, Oif, Oif, Eelif, Eelif, Eelif, Eelse, Eioccc, + print, Eeof, abort }, +/* IS_FALSE_TRAILER */ +{ Idrop, Idrop, Fdrop, Fdrop, Fdrop, Dfalse,Dfalse,Dfalse,Delse, Dendif, + Idrop, Idrop, Fdrop, Fdrop, Fdrop, Dfalse,Dfalse,Dfalse,Delse, Eioccc, + drop, Eeof, abort } +/*TRUEI FALSEI IF TRUE FALSE ELIF ELTRUE ELFALSE ELSE ENDIF + TRUEI FALSEI IF TRUE FALSE ELIF ELTRUE ELFALSE ELSE ENDIF (DODGY) + PLAIN EOF ERROR */ +}; + +/* + * State machine utility functions + */ +static void +ignoreoff(void) +{ + if (depth == 0) + abort(); /* bug */ + ignoring[depth] = ignoring[depth-1]; +} +static void +ignoreon(void) +{ + ignoring[depth] = true; +} +static void +keywordedit(const char *replacement) +{ + snprintf(keyword, tline + sizeof(tline) - keyword, + "%s%s", replacement, newline); + print(); +} +static void +nest(void) +{ + if (depth > MAXDEPTH-1) + abort(); /* bug */ + if (depth == MAXDEPTH-1) + error("Too many levels of nesting"); + depth += 1; + stifline[depth] = linenum; +} +static void +unnest(void) +{ + if (depth == 0) + abort(); /* bug */ + depth -= 1; +} +static void +state(Ifstate is) +{ + ifstate[depth] = is; +} + +/* + * Write a line to the output or not, according to command line options. + */ +static void +flushline(bool keep) +{ + if (symlist) + return; + if (keep ^ complement) { + bool blankline = tline[strspn(tline, " \t\r\n")] == '\0'; + if (blankline && compblank && blankcount != blankmax) { + delcount += 1; + blankcount += 1; + } else { + if (lnnum && delcount > 0) + printf("#line %d%s", linenum, newline); + fputs(tline, output); + delcount = 0; + blankmax = blankcount = blankline ? blankcount + 1 : 0; + } + } else { + if (lnblank) + fputs(newline, output); + exitstat = 1; + delcount += 1; + blankcount = 0; + } + if (debugging) + fflush(output); +} + +/* + * The driver for the state machine. + */ +static void +process(void) +{ + /* When compressing blank lines, act as if the file + is preceded by a large number of blank lines. */ + blankmax = blankcount = 1000; + for (;;) { + Linetype lineval = parseline(); + trans_table[ifstate[depth]][lineval](); + debug("process line %d %s -> %s depth %d", + linenum, linetype_name[lineval], + ifstate_name[ifstate[depth]], depth); + } +} + +/* + * Flush the output and handle errors. + */ +static void +closeout(void) +{ + if (symdepth && !zerosyms) + printf("\n"); + if (fclose(output) == EOF) { + warn("couldn't write to %s", ofilename); + if (overwriting) { + unlink(tempname); + errx(2, "%s unchanged", filename); + } else { + exit(2); + } + } +} + +/* + * Clean up and exit. + */ +static void +done(void) +{ + if (incomment) + error("EOF in comment"); + closeout(); + if (overwriting && rename(tempname, ofilename) == -1) { + warn("couldn't rename temporary file"); + unlink(tempname); + errx(2, "%s unchanged", ofilename); + } + exit(exitstat); +} + +/* + * Parse a line and determine its type. We keep the preprocessor line + * parser state between calls in the global variable linestate, with + * help from skipcomment(). + */ +static Linetype +parseline(void) +{ + const char *cp; + int cursym; + int kwlen; + Linetype retval; + Comment_state wascomment; + + linenum++; + if (fgets(tline, MAXLINE, input) == NULL) + return (LT_EOF); + if (newline == NULL) { + if (strrchr(tline, '\n') == strrchr(tline, '\r') + 1) + newline = newline_crlf; + else + newline = newline_unix; + } + retval = LT_PLAIN; + wascomment = incomment; + cp = skipcomment(tline); + if (linestate == LS_START) { + if (*cp == '#') { + linestate = LS_HASH; + firstsym = true; + cp = skipcomment(cp + 1); + } else if (*cp != '\0') + linestate = LS_DIRTY; + } + if (!incomment && linestate == LS_HASH) { + keyword = tline + (cp - tline); + cp = skipsym(cp); + kwlen = cp - keyword; + /* no way can we deal with a continuation inside a keyword */ + if (strncmp(cp, "\\\r\n", 3) == 0 || + strncmp(cp, "\\\n", 2) == 0) + Eioccc(); + if (strlcmp("ifdef", keyword, kwlen) == 0 || + strlcmp("ifndef", keyword, kwlen) == 0) { + cp = skipcomment(cp); + if ((cursym = findsym(cp)) < 0) + retval = LT_IF; + else { + retval = (keyword[2] == 'n') + ? LT_FALSE : LT_TRUE; + if (value[cursym] == NULL) + retval = (retval == LT_TRUE) + ? LT_FALSE : LT_TRUE; + if (ignore[cursym]) + retval = (retval == LT_TRUE) + ? LT_TRUEI : LT_FALSEI; + } + cp = skipsym(cp); + } else if (strlcmp("if", keyword, kwlen) == 0) + retval = ifeval(&cp); + else if (strlcmp("elif", keyword, kwlen) == 0) + retval = ifeval(&cp) - LT_IF + LT_ELIF; + else if (strlcmp("else", keyword, kwlen) == 0) + retval = LT_ELSE; + else if (strlcmp("endif", keyword, kwlen) == 0) + retval = LT_ENDIF; + else { + linestate = LS_DIRTY; + retval = LT_PLAIN; + } + cp = skipcomment(cp); + if (*cp != '\0') { + linestate = LS_DIRTY; + if (retval == LT_TRUE || retval == LT_FALSE || + retval == LT_TRUEI || retval == LT_FALSEI) + retval = LT_IF; + if (retval == LT_ELTRUE || retval == LT_ELFALSE) + retval = LT_ELIF; + } + if (retval != LT_PLAIN && (wascomment || incomment)) { + retval += LT_DODGY; + if (incomment) + linestate = LS_DIRTY; + } + /* skipcomment normally changes the state, except + if the last line of the file lacks a newline, or + if there is too much whitespace in a directive */ + if (linestate == LS_HASH) { + size_t len = cp - tline; + if (fgets(tline + len, MAXLINE - len, input) == NULL) { + /* append the missing newline */ + strcpy(tline + len, newline); + cp += strlen(newline); + linestate = LS_START; + } else { + linestate = LS_DIRTY; + } + } + } + if (linestate == LS_DIRTY) { + while (*cp != '\0') + cp = skipcomment(cp + 1); + } + debug("parser line %d state %s comment %s line", linenum, + comment_name[incomment], linestate_name[linestate]); + return (retval); +} + +/* + * These are the binary operators that are supported by the expression + * evaluator. + */ +static Linetype op_strict(int *p, int v, Linetype at, Linetype bt) { + if(at == LT_IF || bt == LT_IF) return (LT_IF); + return (*p = v, v ? LT_TRUE : LT_FALSE); +} +static Linetype op_lt(int *p, Linetype at, int a, Linetype bt, int b) { + return op_strict(p, a < b, at, bt); +} +static Linetype op_gt(int *p, Linetype at, int a, Linetype bt, int b) { + return op_strict(p, a > b, at, bt); +} +static Linetype op_le(int *p, Linetype at, int a, Linetype bt, int b) { + return op_strict(p, a <= b, at, bt); +} +static Linetype op_ge(int *p, Linetype at, int a, Linetype bt, int b) { + return op_strict(p, a >= b, at, bt); +} +static Linetype op_eq(int *p, Linetype at, int a, Linetype bt, int b) { + return op_strict(p, a == b, at, bt); +} +static Linetype op_ne(int *p, Linetype at, int a, Linetype bt, int b) { + return op_strict(p, a != b, at, bt); +} +static Linetype op_or(int *p, Linetype at, int a, Linetype bt, int b) { + if (!strictlogic && (at == LT_TRUE || bt == LT_TRUE)) + return (*p = 1, LT_TRUE); + return op_strict(p, a || b, at, bt); +} +static Linetype op_and(int *p, Linetype at, int a, Linetype bt, int b) { + if (!strictlogic && (at == LT_FALSE || bt == LT_FALSE)) + return (*p = 0, LT_FALSE); + return op_strict(p, a && b, at, bt); +} + +/* + * An evaluation function takes three arguments, as follows: (1) a pointer to + * an element of the precedence table which lists the operators at the current + * level of precedence; (2) a pointer to an integer which will receive the + * value of the expression; and (3) a pointer to a char* that points to the + * expression to be evaluated and that is updated to the end of the expression + * when evaluation is complete. The function returns LT_FALSE if the value of + * the expression is zero, LT_TRUE if it is non-zero, LT_IF if the expression + * depends on an unknown symbol, or LT_ERROR if there is a parse failure. + */ +struct ops; + +typedef Linetype eval_fn(const struct ops *, int *, const char **); + +static eval_fn eval_table, eval_unary; + +/* + * The precedence table. Expressions involving binary operators are evaluated + * in a table-driven way by eval_table. When it evaluates a subexpression it + * calls the inner function with its first argument pointing to the next + * element of the table. Innermost expressions have special non-table-driven + * handling. + */ +static const struct ops { + eval_fn *inner; + struct op { + const char *str; + Linetype (*fn)(int *, Linetype, int, Linetype, int); + } op[5]; +} eval_ops[] = { + { eval_table, { { "||", op_or } } }, + { eval_table, { { "&&", op_and } } }, + { eval_table, { { "==", op_eq }, + { "!=", op_ne } } }, + { eval_unary, { { "<=", op_le }, + { ">=", op_ge }, + { "<", op_lt }, + { ">", op_gt } } } +}; + +/* + * Function for evaluating the innermost parts of expressions, + * viz. !expr (expr) number defined(symbol) symbol + * We reset the constexpr flag in the last two cases. + */ +static Linetype +eval_unary(const struct ops *ops, int *valp, const char **cpp) +{ + const char *cp; + char *ep; + int sym; + bool defparen; + Linetype lt; + + cp = skipcomment(*cpp); + if (*cp == '!') { + debug("eval%d !", ops - eval_ops); + cp++; + lt = eval_unary(ops, valp, &cp); + if (lt == LT_ERROR) + return (LT_ERROR); + if (lt != LT_IF) { + *valp = !*valp; + lt = *valp ? LT_TRUE : LT_FALSE; + } + } else if (*cp == '(') { + cp++; + debug("eval%d (", ops - eval_ops); + lt = eval_table(eval_ops, valp, &cp); + if (lt == LT_ERROR) + return (LT_ERROR); + cp = skipcomment(cp); + if (*cp++ != ')') + return (LT_ERROR); + } else if (isdigit((unsigned char)*cp)) { + debug("eval%d number", ops - eval_ops); + *valp = strtol(cp, &ep, 0); + if (ep == cp) + return (LT_ERROR); + lt = *valp ? LT_TRUE : LT_FALSE; + cp = skipsym(cp); + } else if (strncmp(cp, "defined", 7) == 0 && endsym(cp[7])) { + cp = skipcomment(cp+7); + debug("eval%d defined", ops - eval_ops); + if (*cp == '(') { + cp = skipcomment(cp+1); + defparen = true; + } else { + defparen = false; + } + sym = findsym(cp); + if (sym < 0) { + lt = LT_IF; + } else { + *valp = (value[sym] != NULL); + lt = *valp ? LT_TRUE : LT_FALSE; + } + cp = skipsym(cp); + cp = skipcomment(cp); + if (defparen && *cp++ != ')') + return (LT_ERROR); + constexpr = false; + } else if (!endsym(*cp)) { + debug("eval%d symbol", ops - eval_ops); + sym = findsym(cp); + cp = skipsym(cp); + if (sym < 0) { + lt = LT_IF; + cp = skipargs(cp); + } else if (value[sym] == NULL) { + *valp = 0; + lt = LT_FALSE; + } else { + *valp = strtol(value[sym], &ep, 0); + if (*ep != '\0' || ep == value[sym]) + return (LT_ERROR); + lt = *valp ? LT_TRUE : LT_FALSE; + cp = skipargs(cp); + } + constexpr = false; + } else { + debug("eval%d bad expr", ops - eval_ops); + return (LT_ERROR); + } + + *cpp = cp; + debug("eval%d = %d", ops - eval_ops, *valp); + return (lt); +} + +/* + * Table-driven evaluation of binary operators. + */ +static Linetype +eval_table(const struct ops *ops, int *valp, const char **cpp) +{ + const struct op *op; + const char *cp; + int val; + Linetype lt, rt; + + debug("eval%d", ops - eval_ops); + cp = *cpp; + lt = ops->inner(ops+1, valp, &cp); + if (lt == LT_ERROR) + return (LT_ERROR); + for (;;) { + cp = skipcomment(cp); + for (op = ops->op; op->str != NULL; op++) + if (strncmp(cp, op->str, strlen(op->str)) == 0) + break; + if (op->str == NULL) + break; + cp += strlen(op->str); + debug("eval%d %s", ops - eval_ops, op->str); + rt = ops->inner(ops+1, &val, &cp); + if (rt == LT_ERROR) + return (LT_ERROR); + lt = op->fn(valp, lt, *valp, rt, val); + } + + *cpp = cp; + debug("eval%d = %d", ops - eval_ops, *valp); + debug("eval%d lt = %s", ops - eval_ops, linetype_name[lt]); + return (lt); +} + +/* + * Evaluate the expression on a #if or #elif line. If we can work out + * the result we return LT_TRUE or LT_FALSE accordingly, otherwise we + * return just a generic LT_IF. + */ +static Linetype +ifeval(const char **cpp) +{ + int ret; + int val = 0; + + debug("eval %s", *cpp); + constexpr = killconsts ? false : true; + ret = eval_table(eval_ops, &val, cpp); + debug("eval = %d", val); + return (constexpr ? LT_IF : ret == LT_ERROR ? LT_IF : ret); +} + +/* + * Skip over comments, strings, and character literals and stop at the + * next character position that is not whitespace. Between calls we keep + * the comment state in the global variable incomment, and we also adjust + * the global variable linestate when we see a newline. + * XXX: doesn't cope with the buffer splitting inside a state transition. + */ +static const char * +skipcomment(const char *cp) +{ + if (text || ignoring[depth]) { + for (; isspace((unsigned char)*cp); cp++) + if (*cp == '\n') + linestate = LS_START; + return (cp); + } + while (*cp != '\0') + /* don't reset to LS_START after a line continuation */ + if (strncmp(cp, "\\\r\n", 3) == 0) + cp += 3; + else if (strncmp(cp, "\\\n", 2) == 0) + cp += 2; + else switch (incomment) { + case NO_COMMENT: + if (strncmp(cp, "/\\\r\n", 4) == 0) { + incomment = STARTING_COMMENT; + cp += 4; + } else if (strncmp(cp, "/\\\n", 3) == 0) { + incomment = STARTING_COMMENT; + cp += 3; + } else if (strncmp(cp, "/*", 2) == 0) { + incomment = C_COMMENT; + cp += 2; + } else if (strncmp(cp, "//", 2) == 0) { + incomment = CXX_COMMENT; + cp += 2; + } else if (strncmp(cp, "\'", 1) == 0) { + incomment = CHAR_LITERAL; + linestate = LS_DIRTY; + cp += 1; + } else if (strncmp(cp, "\"", 1) == 0) { + incomment = STRING_LITERAL; + linestate = LS_DIRTY; + cp += 1; + } else if (strncmp(cp, "\n", 1) == 0) { + linestate = LS_START; + cp += 1; + } else if (strchr(" \r\t", *cp) != NULL) { + cp += 1; + } else + return (cp); + continue; + case CXX_COMMENT: + if (strncmp(cp, "\n", 1) == 0) { + incomment = NO_COMMENT; + linestate = LS_START; + } + cp += 1; + continue; + case CHAR_LITERAL: + case STRING_LITERAL: + if ((incomment == CHAR_LITERAL && cp[0] == '\'') || + (incomment == STRING_LITERAL && cp[0] == '\"')) { + incomment = NO_COMMENT; + cp += 1; + } else if (cp[0] == '\\') { + if (cp[1] == '\0') + cp += 1; + else + cp += 2; + } else if (strncmp(cp, "\n", 1) == 0) { + if (incomment == CHAR_LITERAL) + error("unterminated char literal"); + else + error("unterminated string literal"); + } else + cp += 1; + continue; + case C_COMMENT: + if (strncmp(cp, "*\\\r\n", 4) == 0) { + incomment = FINISHING_COMMENT; + cp += 4; + } else if (strncmp(cp, "*\\\n", 3) == 0) { + incomment = FINISHING_COMMENT; + cp += 3; + } else if (strncmp(cp, "*/", 2) == 0) { + incomment = NO_COMMENT; + cp += 2; + } else + cp += 1; + continue; + case STARTING_COMMENT: + if (*cp == '*') { + incomment = C_COMMENT; + cp += 1; + } else if (*cp == '/') { + incomment = CXX_COMMENT; + cp += 1; + } else { + incomment = NO_COMMENT; + linestate = LS_DIRTY; + } + continue; + case FINISHING_COMMENT: + if (*cp == '/') { + incomment = NO_COMMENT; + cp += 1; + } else + incomment = C_COMMENT; + continue; + default: + abort(); /* bug */ + } + return (cp); +} + +/* + * Skip macro arguments. + */ +static const char * +skipargs(const char *cp) +{ + const char *ocp = cp; + int level = 0; + cp = skipcomment(cp); + if (*cp != '(') + return (cp); + do { + if (*cp == '(') + level++; + if (*cp == ')') + level--; + cp = skipcomment(cp+1); + } while (level != 0 && *cp != '\0'); + if (level == 0) + return (cp); + else + /* Rewind and re-detect the syntax error later. */ + return (ocp); +} + +/* + * Skip over an identifier. + */ +static const char * +skipsym(const char *cp) +{ + while (!endsym(*cp)) + ++cp; + return (cp); +} + +/* + * Look for the symbol in the symbol table. If it is found, we return + * the symbol table index, else we return -1. + */ +static int +findsym(const char *str) +{ + const char *cp; + int symind; + + cp = skipsym(str); + if (cp == str) + return (-1); + if (symlist) { + if (symdepth && firstsym) + printf("%s%3d", zerosyms ? "" : "\n", depth); + firstsym = zerosyms = false; + printf("%s%.*s%s", + symdepth ? " " : "", + (int)(cp-str), str, + symdepth ? "" : "\n"); + /* we don't care about the value of the symbol */ + return (0); + } + for (symind = 0; symind < nsyms; ++symind) { + if (strlcmp(symname[symind], str, cp-str) == 0) { + debug("findsym %s %s", symname[symind], + value[symind] ? value[symind] : ""); + return (symind); + } + } + return (-1); +} + +/* + * Add a symbol to the symbol table. + */ +static void +addsym(bool ignorethis, bool definethis, char *sym) +{ + int symind; + char *val; + + symind = findsym(sym); + if (symind < 0) { + if (nsyms >= MAXSYMS) + errx(2, "too many symbols"); + symind = nsyms++; + } + symname[symind] = sym; + ignore[symind] = ignorethis; + val = sym + (skipsym(sym) - sym); + if (definethis) { + if (*val == '=') { + value[symind] = val+1; + *val = '\0'; + } else if (*val == '\0') + value[symind] = "1"; + else + usage(); + } else { + if (*val != '\0') + usage(); + value[symind] = NULL; + } + debug("addsym %s=%s", symname[symind], + value[symind] ? value[symind] : "undef"); +} + +/* + * Compare s with n characters of t. + * The same as strncmp() except that it checks that s[n] == '\0'. + */ +static int +strlcmp(const char *s, const char *t, size_t n) +{ + while (n-- && *t != '\0') + if (*s != *t) + return ((unsigned char)*s - (unsigned char)*t); + else + ++s, ++t; + return ((unsigned char)*s); +} + +/* + * Diagnostics. + */ +static void +debug(const char *msg, ...) +{ + va_list ap; + + if (debugging) { + va_start(ap, msg); + vwarnx(msg, ap); + va_end(ap); + } +} + +static void +error(const char *msg) +{ + if (depth == 0) + warnx("%s: %d: %s", filename, linenum, msg); + else + warnx("%s: %d: %s (#if line %d depth %d)", + filename, linenum, msg, stifline[depth], depth); + closeout(); + errx(2, "output may be truncated"); +} diff --git a/src/net/scripts/ver_linux b/src/net/scripts/ver_linux new file mode 100755 index 0000000..0968a30 --- /dev/null +++ b/src/net/scripts/ver_linux @@ -0,0 +1,81 @@ +#!/usr/bin/awk -f +# SPDX-License-Identifier: GPL-2.0 +# Before running this script please ensure that your PATH is +# typical as you use for compilation/installation. I use +# /bin /sbin /usr/bin /usr/sbin /usr/local/bin, but it may +# differ on your system. + +BEGIN { + usage = "If some fields are empty or look unusual you may have an old version.\n" + usage = usage "Compare to the current minimal requirements in Documentation/Changes.\n" + print usage + + system("uname -a") + printf("\n") + + vernum = "[0-9]+([.]?[0-9]+)+" + libc = "libc[.]so[.][0-9]+$" + libcpp = "(libg|stdc)[+]+[.]so[.][0-9]+$" + + printversion("GNU C", version("gcc -dumpversion")) + printversion("GNU Make", version("make --version")) + printversion("Binutils", version("ld -v")) + printversion("Util-linux", version("mount --version")) + printversion("Mount", version("mount --version")) + printversion("Module-init-tools", version("depmod -V")) + printversion("E2fsprogs", version("tune2fs")) + printversion("Jfsutils", version("fsck.jfs -V")) + printversion("Reiserfsprogs", version("reiserfsck -V")) + printversion("Reiser4fsprogs", version("fsck.reiser4 -V")) + printversion("Xfsprogs", version("xfs_db -V")) + printversion("Pcmciautils", version("pccardctl -V")) + printversion("Pcmcia-cs", version("cardmgr -V")) + printversion("Quota-tools", version("quota -V")) + printversion("PPP", version("pppd --version")) + printversion("Isdn4k-utils", version("isdnctrl")) + printversion("Nfs-utils", version("showmount --version")) + printversion("Bison", version("bison --version")) + printversion("Flex", version("flex --version")) + + while ("ldconfig -p 2>/dev/null" | getline > 0) { + if ($NF ~ libc && !seen[ver = version("readlink " $NF)]++) + printversion("Linux C Library", ver) + else if ($NF ~ libcpp && !seen[ver = version("readlink " $NF)]++) + printversion("Linux C++ Library", ver) + } + + printversion("Dynamic linker (ldd)", version("ldd --version")) + printversion("Procps", version("ps --version")) + printversion("Net-tools", version("ifconfig --version")) + printversion("Kbd", version("loadkeys -V")) + printversion("Console-tools", version("loadkeys -V")) + printversion("Oprofile", version("oprofiled --version")) + printversion("Sh-utils", version("expr --v")) + printversion("Udev", version("udevadm --version")) + printversion("Wireless-tools", version("iwconfig --version")) + + while ("sort /proc/modules" | getline > 0) { + mods = mods sep $1 + sep = " " + } + printversion("Modules Loaded", mods) +} + +function version(cmd, ver) { + cmd = cmd " 2>&1" + while (cmd | getline > 0) { + if (match($0, vernum)) { + ver = substr($0, RSTART, RLENGTH) + break + } + } + close(cmd) + return ver +} + +function printversion(name, value, ofmt) { + if (value != "") { + ofmt = "%-20s\t%s\n" + printf(ofmt, name, value) + } +} diff --git a/src/net/scripts/xen-hypercalls.sh b/src/net/scripts/xen-hypercalls.sh new file mode 100644 index 0000000..f18b008 --- /dev/null +++ b/src/net/scripts/xen-hypercalls.sh @@ -0,0 +1,13 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0 +out="$1" +shift +in="$@" + +for i in $in; do + eval $CPP $LINUXINCLUDE -dD -imacros "$i" -x c /dev/null +done | \ +awk '$1 == "#define" && $2 ~ /__HYPERVISOR_[a-z][a-z_0-9]*/ { v[$3] = $2 } + END { print "/* auto-generated by scripts/xen-hypercall.sh */" + for (i in v) if (!(v[i] in v)) + print "HYPERCALL("substr(v[i], 14)")"}' | sort -u >$out diff --git a/src/net/scripts/xz_wrap.sh b/src/net/scripts/xz_wrap.sh new file mode 100755 index 0000000..76e9cbc --- /dev/null +++ b/src/net/scripts/xz_wrap.sh @@ -0,0 +1,23 @@ +#!/bin/sh +# +# This is a wrapper for xz to compress the kernel image using appropriate +# compression options depending on the architecture. +# +# Author: Lasse Collin <lasse.collin@tukaani.org> +# +# This file has been put into the public domain. +# You can do whatever you want with this file. +# + +BCJ= +LZMA2OPTS= + +case $SRCARCH in + x86) BCJ=--x86 ;; + powerpc) BCJ=--powerpc ;; + ia64) BCJ=--ia64; LZMA2OPTS=pb=4 ;; + arm) BCJ=--arm ;; + sparc) BCJ=--sparc ;; +esac + +exec $XZ --check=crc32 $BCJ --lzma2=$LZMA2OPTS,dict=32MiB diff --git a/src/net/smoke.sh b/src/net/smoke.sh new file mode 100755 index 0000000..dffa23b --- /dev/null +++ b/src/net/smoke.sh @@ -0,0 +1,16 @@ +#!/bin/bash + +#接收参数 +smoke_stage=$1 #两种取值：gateci、versionci + +#暂时没实现的，固定返回0，后期如果实现，根据各组件自身需求调整该脚本 +if [ $smoke_stage = "gateci" ]; then + echo "gateci compile success" + exit 0 +fi + +if [ $smoke_stage = "versionci" ]; then + echo "versionci compile success" + exit 0 +fi + diff --git a/src/net/test b/src/net/test new file mode 100755 index 0000000..6d54b09 --- /dev/null +++ b/src/net/test @@ -0,0 +1,2 @@ + +#define CONFIG_MLX5_SF 1 diff --git a/src/net/test_tools/Makefile b/src/net/test_tools/Makefile new file mode 100644 index 0000000..a2b723a --- /dev/null +++ b/src/net/test_tools/Makefile @@ -0,0 +1,9 @@ +cc = gcc +prom = zxdh_net_test +source = zxdh_net_test.c + +$(prom): $(source) + $(cc) -o $(prom) $(source) + +clean: + @-rm -rf $(prom) diff --git a/src/net/test_tools/pkt_dtp_nopi_parse.txt b/src/net/test_tools/pkt_dtp_nopi_parse.txt new file mode 100644 index 0000000..a4d1846 --- /dev/null +++ b/src/net/test_tools/pkt_dtp_nopi_parse.txt @@ -0,0 +1,34 @@ +#[type] +02 1a 00 00 +#[pi] +81 23 00 00 00 00 00 00 00 56 00 46 00 30 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +#[pd] +00 00 00 00 00 00 00 00 88 a8 00 00 81 00 00 00 +#[dst mac] +22 22 22 22 22 1f +#[src mac] +22 22 22 22 22 2f +#[vlan] +81 00 00 64 +#[eth type] +08 00 +#[ip header] +45 00 00 32 c9 51 00 00 64 +#[ip protocol] +11 +#[ip checksum] +fb d5 +#[src ip] +c8 c8 00 01 +#[dst ip] +c8 c8 00 02 +#[src port] +f9 63 +#[dst port] +12 34 +#[udp len] +00 08 +#[udp checksum] +4c dc +#[payload] +00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 \ No newline at end of file diff --git a/src/net/test_tools/pkt_dtp_pi_parse.txt b/src/net/test_tools/pkt_dtp_pi_parse.txt new file mode 100644 index 0000000..91835d9 --- /dev/null +++ b/src/net/test_tools/pkt_dtp_pi_parse.txt @@ -0,0 +1,34 @@ +#[type] +02 1a 00 00 +#[pi] +01 23 00 00 00 00 00 00 00 46 00 5a 00 30 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +#[pd] +00 00 00 00 00 00 00 00 88 a8 00 00 81 00 00 00 +#[dst mac] +22 22 22 22 22 1f +#[src mac] +22 22 22 22 22 2f +#[vlan] +81 00 00 64 +#[eth type] +08 00 +#[ip header] +45 00 00 32 c9 51 00 00 64 +#[ip protocol] +11 +#[ip checksum] +fb d5 +#[src ip] +c8 c8 00 01 +#[dst ip] +c8 c8 00 02 +#[src port] +f9 63 +#[dst port] +12 34 +#[udp len] +00 08 +#[udp checksum] +4c dc +#[payload] +00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 \ No newline at end of file diff --git a/src/net/test_tools/pkt_dtp_pi_parse_lookside.txt b/src/net/test_tools/pkt_dtp_pi_parse_lookside.txt new file mode 100644 index 0000000..ee85868 --- /dev/null +++ b/src/net/test_tools/pkt_dtp_pi_parse_lookside.txt @@ -0,0 +1,34 @@ +#[type] +02 20 00 00 +#[pi] +01 27 00 00 00 00 00 00 00 56 00 6a 00 30 20 00 12 34 56 78 1a 2a 3a 4a 11 22 33 44 55 66 77 88 33 11 87 0b 13 30 ea 71 74 65 fd c3 46 6c 21 e5 +#[pd] +00 00 00 00 00 00 00 00 88 a8 00 00 81 00 00 00 +#[dst mac] +22 22 22 22 22 1f +#[src mac] +22 22 22 22 22 2f +#[vlan] +81 00 00 64 +#[eth type] +08 00 +#[ip header] +45 00 00 32 c9 51 00 00 64 +#[ip protocol] +11 +#[ip checksum] +fb d5 +#[src ip] +c8 c8 00 01 +#[dst ip] +c8 c8 00 02 +#[src port] +f9 63 +#[dst port] +12 34 +#[udp len] +00 08 +#[udp checksum] +4c dc +#[payload] +00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 \ No newline at end of file diff --git a/src/net/test_tools/pkt_np_128.txt b/src/net/test_tools/pkt_np_128.txt new file mode 100644 index 0000000..b31d068 --- /dev/null +++ b/src/net/test_tools/pkt_np_128.txt @@ -0,0 +1,35 @@ +#[type] +00 1a 00 00 +#[pi] +01 a9 00 00 00 00 00 00 32 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +#[pd] +00 00 00 00 00 00 00 00 88 a8 00 00 81 00 00 00 +#[dst mac] +22 22 22 22 22 0f +#[src mac] +22 22 22 22 22 2f +#[vlan] +81 00 00 64 +#[eth type] +08 00 +#[ip header] +45 00 00 32 c9 51 00 00 64 +#[ip protocol] +11 +#[ip checksum] +fb d5 +#[src ip] +c8 c8 00 01 +#[dst ip] +c8 c8 00 02 +#[src port] +f9 63 +#[dst port] +12 34 +#[udp len] +00 08 +#[udp checksum] +4c dc +#[payload] +00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 +00 00 00 00 00 00 01 28 \ No newline at end of file diff --git a/src/net/test_tools/zxdh_net_test.c b/src/net/test_tools/zxdh_net_test.c new file mode 100644 index 0000000..2bfc08a --- /dev/null +++ b/src/net/test_tools/zxdh_net_test.c @@ -0,0 +1,496 @@ +#include "zxdh_net_test.h" + + +cmd_table_t CMD_TABLE[] = +{ + {"h", HELP_CMD, CMD_PARA_NUM_TWO, zxdh_net_test_usage}, + {"r", GET_REG_CMD, CMD_PARA_NUM_FIVE, zxdh_get_reg}, + {"w", SET_REG_CMD, CMD_PARA_NUM_FIVE, zxdh_set_reg}, + {"vring", GET_VQ_INFO, CMD_PARA_NUM_SIX, zxdh_get_vring_info}, + {"msgq_config", SET_MSGQ_INFO, CMD_PARA_NUM_FOUR, zxdh_set_msgq_info}, + {"msgq_send", MSGQ_MSG_SEND, CMD_PARA_NUM_FIVE, zxdh_msgq_send_pkt}, + {"send_file_pkt", SEND_FILE_PKT, CMD_PARA_NUM_THREE, zxdh_send_file_pkt}, +}; +#define CMD_NUM(table) (sizeof(table) / sizeof(table[0])) + +uint32_t htoi(int8_t *str) +{ + int32_t i = 0; + uint32_t n = 0; + + if (NULL == str) + { + return ERR_INPUT_CMD_PARAMS; + } + + if ((str[0] == '0') && (str[1] == 'x' || str[1] == 'X')) + { + i = 2; + } + else + { + i = 0; + } + + for (; (str[i] >= '0' && str[i] <= '9') || (str[i] >= 'a' && str[i] <= 'f') || (str[i] >= 'A' && str[i] <= 'F'); ++i) + { + if (tolower(str[i]) > '9') + { + n = 16 * n + (10 + tolower(str[i]) - 'a'); + } + else + { + n = 16 * n + (tolower(str[i]) - '0'); + } + } + return n; +} + +int32_t zxdh_net_test_usage(__attribute__((unused)) const int32_t skfd, __attribute__((unused)) const int8_t *ifrname, + __attribute__((unused)) struct zxdh_en_reg *reg) +{ + printf("\nUsage: zxdh_net_test\n" + "Version: 1.0\n" + "[zxdh_net_test options]\n" + "./zxdh_net_test h print usage\n" + "./zxdh_net_test netdev_name r addr_offset reg_num read the register\n" + "./zxdh_net_test netdev_name w addr_offset value write the register\n" + "./zxdh_net_test netdev_name vring queue desc_index desc_num get the vring and desc_num desc informations from the desc_index\n" + "./zxdh_net_test netdev_name msgq_config loop_back print_data config msgq para\n" + "./zxdh_net_test netdev_name msgq_send pkt_len no_reps send_cnt msgq send pkt\n" + "./zxdh_net_test netdev_name send_file_pkt ./pkt.txt send packets with the specified packet contents including the self-defined header\n" + "\n"); + + return 0; +} + +int32_t zxdh_get_reg(const int32_t skfd, const int8_t *ifrname, struct zxdh_en_reg *reg) +{ + struct ifreq ifr; + int32_t i = 0; + + memset(&ifr, 0, sizeof(struct ifreq)); + strncpy(ifr.ifr_name, ifrname, IFNAMSIZ); + ifr.ifr_ifru.ifru_data = (void *)reg; + + if ((reg->offset + reg->num * 4) >= MAX_IOMAP_RANGE) + { + fprintf(stdout, "the offset:%#x, num=%#x is out of pci io map range!\n", reg->offset, reg->num); + return ERR_IOMAP_RANGE; + } + + if (ioctl(skfd, SIOCGMIIREG, &ifr) < 0) + { + fprintf(stderr, "SIOCGMIIREG on %s failed: %s\n", ifrname, strerror(errno)); + return ERRCMD; + } + + fprintf(stdout, "read register offset:%#x, num=%#x\n", reg->offset, reg->num); + for (i = 0; i < reg->num; i++) + { + fprintf(stdout, "0x%.8x: 0x%.8x ", reg->offset + i * 4, reg->data[i]); + if(((i + 1) % 4) == 0) + { + fprintf(stdout, "\n"); + } + } + fprintf(stdout, "\n"); + + return 0; +} + +int32_t zxdh_set_reg(const int32_t skfd, const int8_t *ifrname, struct zxdh_en_reg *reg) +{ + struct ifreq ifr; + int32_t i = 0; + + memset(&ifr, 0, sizeof(struct ifreq)); + strncpy(ifr.ifr_name, ifrname, IFNAMSIZ); + ifr.ifr_ifru.ifru_data = (void *)reg; + + if ((reg->offset + reg->num * 4) >= MAX_IOMAP_RANGE) + { + fprintf(stderr, "the offset:%#x, num=%#x is out of pci io map range!\n", reg->offset, reg->num); + return ERR_IOMAP_RANGE; + } + + if (ioctl(skfd, SIOCSMIIREG, &ifr) < 0) + { + fprintf(stderr, "SIOCSMIIREG on %s failed: %s\n", ifrname, strerror(errno)); + return ERRCMD; + } + + fprintf(stdout, "write register offset:%#x, num=%#x\n", reg->offset, reg->num); + for (i = 0; i < reg->num; i++) + { + if(((i + 1) % 4) == 0) + { + fprintf(stdout, "\n"); + } + fprintf(stdout, "0x%.8x: 0x%.8x ", reg->offset + i * 4, reg->data[i]); + } + fprintf(stdout, "\n"); + + return 0; +} + +int32_t zxdh_get_vring_info(const int32_t skfd, const int8_t *ifrname, struct zxdh_en_reg *reg) +{ + struct ifreq ifr; + + memset(&ifr, 0, sizeof(struct ifreq)); + strncpy(ifr.ifr_name, ifrname, IFNAMSIZ); + ifr.ifr_ifru.ifru_data = (void *)reg; + + if (ioctl(skfd, SIOCDEVPRIVATE_VQ_INFO, &ifr) < 0) + { + fprintf(stderr, "SIOCDEVPRIVATE_VQ_INFO on %s failed: %s\n", ifrname, strerror(errno)); + return ERRCMD; + } + + return 0; +} + +int32_t zxdh_set_msgq_info(const int32_t skfd, const int8_t *ifrname, struct zxdh_en_reg *reg) +{ + struct ifreq ifr; + int32_t i = 0; + + memset(&ifr, 0, sizeof(struct ifreq)); + strncpy(ifr.ifr_name, ifrname, IFNAMSIZ); + ifr.ifr_ifru.ifru_data = (void *)reg; + + if (ioctl(skfd, SIOCDEVPRIVATE_MSGQ_CONFIG, &ifr) < 0) + { + fprintf(stderr, "SIOCDEVPRIVATE_MSGQ_CONFIG on %s failed: %s\n", ifrname, strerror(errno)); + return ERRCMD; + } + + fprintf(stdout, "set msgq loop_back:%d\n", reg->data[0]); + fprintf(stdout, "set msgq print_flag:%d\n", reg->data[1]); + + return 0; +} + +int32_t zxdh_msgq_send_pkt(const int32_t skfd, const int8_t *ifrname, struct zxdh_en_reg *reg) +{ + struct ifreq ifr; + int32_t i = 0; + + memset(&ifr, 0, sizeof(struct ifreq)); + strncpy(ifr.ifr_name, ifrname, IFNAMSIZ); + ifr.ifr_ifru.ifru_data = (void *)reg; + + if (ioctl(skfd, SIOCDEVPRIVATE_MSGQ_SNED, &ifr) < 0) + { + fprintf(stderr, "SIOCDEVPRIVATE_MSGQ_SNED on %s failed: %s\n", ifrname, strerror(errno)); + return ERRCMD; + } + + return -reg->num; +} + +int32_t zxdh_send_file_pkt(const int32_t skfd, const int8_t *ifrname, struct zxdh_en_reg *reg) +{ + struct ifreq ifr; + + memset(&ifr, 0, sizeof(struct ifreq)); + strncpy(ifr.ifr_name, ifrname, IFNAMSIZ); + ifr.ifr_ifru.ifru_data = (void *)reg; + + if (ioctl(skfd, SIOCDEVPRIVATE_SEND_FILE_PKT, &ifr) < 0) + { + fprintf(stderr, "SIOCDEVPRIVATE_SEND_FILE_PKT on %s failed: %s\n", ifrname, strerror(errno)); + return ERRCMD; + } + + fprintf(stdout, "try to send file packets success\n"); + + return 0; +} + +bool is_cmd_valid(const int32_t cmd) +{ + if ((cmd < MIN_CMD) || (cmd > MAX_CMD)) + { + return false; + } + return true; +} + +int32_t get_cmd(int8_t *cmd_argv) +{ + int32_t cmd = 0; + int32_t i = 0; + + for (i = 0; i < CMD_NUM(CMD_TABLE); i++) + { + if (cmd_argv == NULL) + { + cmd = CMD_TABLE[i].cmd; + return cmd; + } + + if (strcmp(cmd_argv, CMD_TABLE[i].argv) == 0) + { + cmd = CMD_TABLE[i].cmd; + } + } + return cmd; +} + +int32_t check_cmd_para_num(const int32_t cmd, const int32_t para_num) +{ + int32_t cmd_para_num = 0; + int32_t i = 0; + + for (i = 0; i < CMD_NUM(CMD_TABLE); i++) + { + if (CMD_TABLE[i].cmd == cmd) + { + cmd_para_num = CMD_TABLE[i].para_num; + break; + } + } + + if (para_num < cmd_para_num) + { + fprintf(stderr, "cmd %d need para_num =%d, but %d paras input is given!\n", cmd, cmd_para_num, para_num); + return ERRCMD; + } + return 0; +} + +int32_t get_reg_cmd_para(int8_t **argv, struct zxdh_en_reg *reg) +{ + reg->offset = htoi(argv[3]); + reg->num = (uint32_t)atoi(argv[4]); + + return 0; +} + +int32_t set_reg_cmd_para(int8_t **argv, struct zxdh_en_reg *reg) +{ + int32_t i = 0; + + reg->offset = htoi(argv[3]); + reg->num = (uint32_t)atoi(argv[4]); + + while ((i < reg->num) && argv[5 + i]) + { + reg->data[i] = htoi(argv[5 + i]); + i++; + } + + return 0; +} + +int32_t get_vring_info_cmd_para(int8_t **argv, struct zxdh_en_reg *reg) +{ + reg->offset = (uint32_t)atoi(argv[3]); + reg->num = (uint32_t)atoi(argv[4]); + reg->data[0] = (uint32_t)atoi(argv[5]); + + return 0; +} + +int32_t set_msgq_info_para(int8_t **argv, struct zxdh_en_reg *reg) +{ + reg->data[0] = (uint32_t)atoi(argv[3]); + reg->data[1] = (uint32_t)atoi(argv[4]); + return 0; +} + +int32_t msgq_msg_send_para(int8_t **argv, struct zxdh_en_reg *reg) +{ + reg->data[0] = (uint32_t)atoi(argv[3]); + reg->data[1] = (uint32_t)atoi(argv[4]); + reg->data[2] = (uint32_t)atoi(argv[5]); + return 0; +} + +uint32_t delet_str_spec(uint8_t *pstr, uint32_t len) +{ + uint16_t i = 0; + uint16_t j = 0; + uint8_t *buf = pstr; + + for (i = 0; i < len; i++) + { + if (pstr[i] == '\0') + { + break; + } + + if ((pstr[i] != ' ') && (pstr[i] != '\n')) + { + *(buf + j) = pstr[i]; + j++; + } + } + if (j < i) + { + memset(buf + j, 0, (i - j)); + } + + return j; +} + +uint32_t hexstr_to_data(uint8_t *pstr, uint32_t len, uint32_t *data) +{ + int8_t hexbuf[3] = {0}; + uint32_t i = 0; + uint32_t loop = 0; + + if (len % 2) + { + len -= 1; + } + loop = len / 2; + for (i = 0; i < loop; i++) + { + memset(hexbuf, 0, sizeof(hexbuf)); + memcpy(hexbuf, &pstr[2*i], 2); + data[i] = htoi(hexbuf); + fprintf(stdout, "%.2x ", data[i]); + } + fprintf(stdout, "\n"); + + return i; +} + +int32_t get_para_from_file(int8_t **argv, struct zxdh_en_reg *reg) +{ + int8_t filename[100] = {0}; + int8_t buf[1000] = {0}; + int32_t i = 0; + FILE *f = NULL; + uint32_t len = 0; + + strncpy(filename, argv[3], strlen(argv[3])); + filename[strlen(argv[3])] = '\0'; + if ((f = fopen(filename, "r")) == NULL) + { + fprintf(stdout, "get_para_from_file: cannot open %s\n", filename); + return ERR_INPUT_CMD_PARAMS; + } + memset(reg, 0, sizeof(struct zxdh_en_reg)); + + fprintf(stdout, "read file pkt:\n"); + while (fgets(buf, sizeof(buf), f) != NULL) + { + if ((buf[0] != '\n') && (buf[0] != '#')) + { + len = delet_str_spec(buf, strlen(buf)); + reg->num += hexstr_to_data(buf, len, (uint32_t *)®->data[reg->num]); + } + } + fprintf(stdout, "pkt len: %d\n\n", reg->num); + + fclose(f); + + return 0; +} + +struct get_cmd_para_table cmd_para_table[] = +{ + {HELP_CMD, NULL}, + {GET_REG_CMD, get_reg_cmd_para}, + {SET_REG_CMD, set_reg_cmd_para}, + {GET_VQ_INFO, get_vring_info_cmd_para}, + {SET_MSGQ_INFO, set_msgq_info_para}, + {MSGQ_MSG_SEND, msgq_msg_send_para}, + {SEND_FILE_PKT, get_para_from_file}, +}; + +int32_t get_cmd_para(const int32_t cmd, int8_t **argv, struct zxdh_en_reg *reg) +{ + int32_t i = 0; + int32_t ret = 0; + + if (NULL == argv) + { + fprintf(stdout, "%s %d pointer is null!\n", __FUNCTION__, __LINE__); + return ERR_INPUT_CMD_PARAMS; + } + + memset((void *)reg, 0, sizeof(struct zxdh_en_reg)); + for (i = 0; i < CMD_NUM(cmd_para_table); i++) + { + if ((cmd == cmd_para_table[i].cmd) && (cmd_para_table[i].func)) + { + ret = cmd_para_table[i].func(argv, reg); + } + } + + return ret; +} + +int32_t get_cmd_and_para(const int32_t argc, int8_t **argv, int8_t *ifrname, struct zxdh_en_reg *reg) +{ + int32_t cmd = 0; + int32_t ret = 0; + + cmd = get_cmd(argv[2]); + fprintf(stdout, "cmd = %d\n", cmd); + + if (!is_cmd_valid(cmd)) + { + fprintf(stderr, "cmd %d invalid\n", cmd); + return ERRCMD; + } + + if (check_cmd_para_num(cmd, argc) < 0) + { + fprintf(stderr, "para num check failed!\n"); + return ERRCMD; + } + + ifrname = argv[1]; + ret = get_cmd_para(cmd, argv, reg); + if (ret < 0) + { + fprintf(stderr, "get detail cmd para failed, ret %d!\n", ret); + return ERRCMD; + } + + return cmd; +} + +int32_t main(int32_t argc, int8_t **argv) +{ + int8_t *ifrname = NULL; + int32_t skfd = -1; + int32_t ret = 0; + int32_t cmd = 0; + uint32_t num = 0; + uint32_t i = 0; + struct zxdh_en_reg reg = {0}; + + for (num = 0; num < argc; num++) + { + fprintf(stdout, "argv[%d]: %s\n", num, argv[num]); + } + + memset(®, 0, sizeof(struct zxdh_en_reg)); + ifrname = argv[1]; + cmd = get_cmd_and_para(argc, argv, ifrname, ®); + + if ((skfd = socket(AF_INET, SOCK_DGRAM, 0)) < 0 ) + { + fprintf(stderr, "socket error\n"); + return ERR_SOCKET; + } + + for (i = 0; i < CMD_NUM(CMD_TABLE); i++) + { + if ((cmd == CMD_TABLE[i].cmd) && (CMD_TABLE[i].func)) + { + ret = CMD_TABLE[i].func(skfd, ifrname, ®); + } + } + + close(skfd); + fprintf(stdout, "ret=%d\n", ret); + return ret; +} diff --git a/src/net/test_tools/zxdh_net_test.h b/src/net/test_tools/zxdh_net_test.h new file mode 100644 index 0000000..d716959 --- /dev/null +++ b/src/net/test_tools/zxdh_net_test.h @@ -0,0 +1,100 @@ +#ifndef _ZXDH_NET_TEST_ +#define _ZXDH_NET_TEST_ + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + + +#include <stdio.h> +#include <stdint.h> +#include <stdbool.h> +#include <string.h> +#include <errno.h> +#include <fcntl.h> +#include <getopt.h> +#include <sys/socket.h> +#include <sys/ioctl.h> +#include <net/if.h> +#include <stdlib.h> +#include <unistd.h> +#include <linux/ethtool.h> +#include <linux/sockios.h> +#include <sys/mman.h> +#include <pthread.h> +#include <time.h> +#include <sys/types.h> +#include <dirent.h> +#include <ctype.h> + + +/* command */ +#define ERRCMD (-1) +#define MIN_CMD 0 +#define MAX_CMD 6 +#define HELP_CMD MIN_CMD +#define GET_REG_CMD 1 +#define SET_REG_CMD 2 +#define GET_VQ_INFO 3 +#define SET_MSGQ_INFO 4 +#define MSGQ_MSG_SEND 5 +#define SEND_FILE_PKT MAX_CMD + +#define MAX_IOMAP_RANGE (256 * 1024) + +#define ERR_SOCKET (-1) +#define ERR_IOMAP_RANGE (-3) +#define ERR_INPUT_CMD_PARAMS (-4) + +#define CMD_PARA_NUM_TWO 2 +#define CMD_PARA_NUM_THREE 3 +#define CMD_PARA_NUM_FOUR 4 +#define CMD_PARA_NUM_FIVE 5 +#define CMD_PARA_NUM_SIX 6 +#define CMD_PARA_NUM_EIGHT 8 +#define CMD_PARA_NUM_NINE 9 + +#define SIOCDEVPRIVATE_VQ_INFO (SIOCDEVPRIVATE + 2) +#define SIOCDEVPRIVATE_MSGQ_SNED (SIOCDEVPRIVATE + 3) +#define SIOCDEVPRIVATE_MSGQ_CONFIG (SIOCDEVPRIVATE + 4) +#define SIOCDEVPRIVATE_SEND_FILE_PKT (SIOCDEVPRIVATE + 6) + +#define MAX_ACCESS_NUM 500 +struct zxdh_en_reg +{ + uint32_t offset; + uint32_t num; + uint32_t data[MAX_ACCESS_NUM]; +}; + +typedef int32_t (*function)(const int32_t skfd, const int8_t *ifrname, struct zxdh_en_reg *reg); + +typedef struct +{ + int8_t *argv; + int32_t cmd; + int32_t para_num; + function func; +}cmd_table_t; + +struct get_cmd_para_table +{ + int32_t cmd; + int32_t (*func)(int8_t **argv, struct zxdh_en_reg *reg); +}; + +int32_t zxdh_net_test_usage(__attribute__((unused)) const int32_t skfd, __attribute__((unused)) const int8_t *ifrname, + __attribute__((unused)) struct zxdh_en_reg *reg); +int32_t zxdh_get_reg(const int32_t skfd, const int8_t *ifrname, struct zxdh_en_reg *reg); +int32_t zxdh_set_reg(const int32_t skfd, const int8_t *ifrname, struct zxdh_en_reg *reg); +int32_t zxdh_get_vring_info(const int32_t skfd, const int8_t *ifrname, struct zxdh_en_reg *reg); +int32_t zxdh_set_msgq_info(const int32_t skfd, const int8_t *ifrname, struct zxdh_en_reg *reg); +int32_t zxdh_msgq_send_pkt(const int32_t skfd, const int8_t *ifrname, struct zxdh_en_reg *reg); +int32_t zxdh_send_file_pkt(const int32_t skfd, const int8_t *ifrname, struct zxdh_en_reg *reg); + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* _ZXDH_NET_TEST_ */ diff --git a/src/net/upload.sh b/src/net/upload.sh new file mode 100755 index 0000000..869e21d --- /dev/null +++ b/src/net/upload.sh @@ -0,0 +1,201 @@ +#!/bin/bash + +#接收参数 +upload_stage=$1 +chg_branch=$2 +env_user=$3 +env_pwd=$4 + +#ver_path固定不变，各组件需要修改的只有root_dir +ver_path=/zte +root_dir=$ver_path/zxdh_kernel #（各组件根据实际调整） + + +#获取库下面的制品名称(制品在前面compile阶段已生成) +cd ${root_dir}/kernel-src + +if [ "$upload_stage" = "versionci" ]; then + echo "versionci upload start" + pf_tgz_name=$(ls | grep "^zxdh-eth-.*daily\.src\.tgz$") + host_hpf_tgz_name=$(ls | grep "^zxdh-neo-host-hpf-.*daily\.src\.tgz$") + zf_mpf_tgz_name=$(ls | grep "^zxdh-neo-mpf-.*daily\.src\.tgz$") +fi + +if [ "$upload_stage" = "postci" ]; then + echo "postci upload start" + pf_tgz_name=$(ls | grep "^zxdh-eth-.*\.src\.tgz$") + host_hpf_tgz_name=$(ls | grep "^zxdh-neo-host-hpf-.*\.src\.tgz$") + zf_mpf_tgz_name=$(ls | grep "^zxdh-neo-mpf-.*\.src\.tgz$") +fi + +if [ "$pf_tgz_name" = "" -o "$host_hpf_tgz_name" = "" -o "$zf_mpf_tgz_name" = "" ]; then + echo "找不到相关制品" + exit 1 +fi + +cd ${root_dir} +host_arm_en_pf_rpm=$(ls | grep "^zxdh-eth-.*\.cgsl${NXI_Host_CGS_kernel_aarch64:1}\.aarch64\.rpm$") +host_x86_en_pf_rpm=$(ls | grep "^zxdh-eth-.*\.cgsl${NXI_Host_CGS_kernel_X86:1}\.x86_64\.rpm$") +host_arm_hpf_rpm=$(ls | grep "^zxdh-hpf-.*\.cgsl${NXI_Host_CGS_kernel_aarch64:1}\.aarch64\.rpm$") +host_x86_hpf_rpm=$(ls | grep "^zxdh-hpf-.*\.cgsl${NXI_Host_CGS_kernel_X86:1}\.x86_64\.rpm$") +zf_arm_en_pf_rpm=$(ls | grep "^zxdh-eth-.*\.cgsl${DPU_CGS_kernel_aarch64:1}\.aarch64\.rpm$") +zf_arm_zf_mpf_rpm=$(ls | grep "^zxdh-zf-mpf-.*\.cgsl${DPU_CGS_kernel_aarch64:1}\.aarch64\.rpm$") +dpu_config_rpm=$(ls | grep "zxdh-dpu-config") +smartnic_config_rpm=$(ls | grep "zxdh-smartnic-config") + +if [ "$host_arm_en_pf_rpm" = "" ]; then + echo "找不到 host-arm en_pf rpm制品" + exit 1 +fi +if [ "$host_x86_en_pf_rpm" = "" ]; then + echo "找不到 host-x86 en_pf rpm制品" + exit 1 +fi +if [ "$host_arm_hpf_rpm" = "" ]; then + echo "找不到 host-arm hpf rpm制品" + exit 1 +fi +if [ "$host_x86_hpf_rpm" = "" ]; then + echo "找不到 host-x86 hpf rpm制品" + exit 1 +fi +if [ "$zf_arm_zf_mpf_rpm" = "" ]; then + echo "找不到 zf-arm zf_mpf rpm制品" + exit 1 +fi +if [ "$zf_arm_en_pf_rpm" = "" ]; then + echo "找不到 zf-arm en_pf rpm制品" + exit 1 +fi +if [ "$dpu_config_rpm" = "" ]; then + echo "找不到dpu_config rpm制品" + exit 1 +fi +if [ "$smartnic_config_rpm" = "" ]; then + echo "找不到smartnic_config rpm制品" + exit 1 +fi + +echo "全部找到" +echo "pf_tgz_name ${pf_tgz_name}" +echo "host_hpf_tgz_name ${host_hpf_tgz_name}" +echo "zf_mpf_tgz_name ${zf_mpf_tgz_name}" +echo "host_arm_en_pf_rpm ${host_arm_en_pf_rpm}" +echo "host_x86_en_pf_rpm ${host_x86_en_pf_rpm}" +echo "host_arm_hpf_rpm ${host_arm_hpf_rpm}" +echo "host_x86_hpf_rpm ${host_x86_hpf_rpm}" +echo "zf_arm_en_pf_rpm ${zf_arm_en_pf_rpm}" +echo "zf_arm_zf_mpf_rpm ${zf_arm_zf_mpf_rpm}" +echo "dpu_config_rpm ${dpu_config_rpm}" +echo "smartnic_config_rpm ${smartnic_config_rpm}" + +#制品库路径：即各组件版本/制品在制品库上的存放目录 +art_path="https://artsz.zte.com.cn:443/artifactory/dinghai-snapshot-generic/dpu_sdk/net/driver/zxdh_kernel/${chg_branch}" #（各组件根据实际调整） + +#版本/制品本地路径：即各组件版本/制品在库下面的存放（生成）路径+制品/版本名称 +art_pf_tgz_src="${root_dir}/kernel-src/${pf_tgz_name}" +art_host_hpf_src="${root_dir}/kernel-src/${host_hpf_tgz_name}" +art_zf_mpf_src="${root_dir}/kernel-src/${zf_mpf_tgz_name}" +art_host_arm_en_pf_src="${root_dir}/${host_arm_en_pf_rpm}" +art_host_x86_en_pf_src="${root_dir}/${host_x86_en_pf_rpm}" +art_host_arm_hpf_src="${root_dir}/${host_arm_hpf_rpm}" +art_host_x86_hpf_src="${root_dir}/${host_x86_hpf_rpm}" +art_zf_arm_en_pf_src="${root_dir}/${zf_arm_en_pf_rpm}" +art_zf_arm_zf_mpf_src="${root_dir}/${zf_arm_zf_mpf_rpm}" +art_src2="${root_dir}/${dpu_config_rpm}" +art_src3="${root_dir}/${smartnic_config_rpm}" + +art_user="-u${env_user}:${env_pwd}" + +#版本/制品名：（按照规范来） +art_pf_tgz_name="${pf_tgz_name}" +art_host_hpf_name="${host_hpf_tgz_name}" +art_zf_mpf_name="${zf_mpf_tgz_name}" +art_host_arm_en_pf_name="${host_arm_en_pf_rpm}" +art_host_x86_en_pf_name="${host_x86_en_pf_rpm}" +art_host_arm_hpf_name="${host_arm_hpf_rpm}" +art_host_x86_hpf_name="${host_x86_hpf_rpm}" +art_zf_arm_en_pf_name="${zf_arm_en_pf_rpm}" +art_zf_arm_zf_mpf_name="${zf_arm_zf_mpf_rpm}" +art_name2="${dpu_config_rpm}" +art_name3="${smartnic_config_rpm}" + +regex="202[3-9]{1}(0[1-9]|1[0-2])(0[1-9]|[12][0-9]|3[01])([01][0-9]|2[0-3])([0-5][0-9])" +gen_data=$(echo ${art_host_x86_en_pf_name} | grep -oE "$regex") +git_ver_path="git_ver/${gen_data}" +#一次只上传单个制品/版本以下内容无需修改，如果需要一次上传多个制品，增加art_dst和curl操作 +art_pf_tgz_dst1="${art_path}/${git_ver_path}/${art_pf_tgz_name}" +art_pf_tgz_dst2="${art_path}/last/${art_pf_tgz_name}" +art_host_hpf_dst1="${art_path}/${git_ver_path}/${art_host_hpf_name}" +art_host_hpf_dst2="${art_path}/last/${art_host_hpf_name}" +art_zf_mpf_dst1="${art_path}/${git_ver_path}/${art_zf_mpf_name}" +art_zf_mpf_dst2="${art_path}/last/${art_zf_mpf_name}" + +art_host_arm_en_pf_dst1="${art_path}/${git_ver_path}/${art_host_arm_en_pf_name}" +art_host_arm_en_pf_dst2="${art_path}/last/${art_host_arm_en_pf_name}" + +art_host_x86_en_pf_dst1="${art_path}/${git_ver_path}/${art_host_x86_en_pf_name}" +art_host_x86_en_pf_dst2="${art_path}/last/${art_host_x86_en_pf_name}" + +art_host_arm_hpf_dst1="${art_path}/${git_ver_path}/${art_host_arm_hpf_name}" +art_host_arm_hpf_dst2="${art_path}/last/${art_host_arm_hpf_name}" + +art_host_x86_hpf_dst1="${art_path}/${git_ver_path}/${art_host_x86_hpf_name}" +art_host_x86_hpf_dst2="${art_path}/last/${art_host_x86_hpf_name}" + +art_zf_arm_en_pf_dst1="${art_path}/${git_ver_path}/${art_zf_arm_en_pf_name}" +art_zf_arm_en_pf_dst2="${art_path}/last/${art_zf_arm_en_pf_name}" + +art_zf_arm_zf_mpf_dst1="${art_path}/${git_ver_path}/${art_zf_arm_zf_mpf_name}" +art_zf_arm_zf_mpf_dst2="${art_path}/last/${art_zf_arm_zf_mpf_name}" + +art_dst5="${art_path}/${git_ver_path}/${art_name2}" +art_dst6="${art_path}/last/${art_name2}" + +art_dst7="${art_path}/${git_ver_path}/${art_name3}" +art_dst8="${art_path}/last/${art_name3}" + +last_files=$(curl -k ${art_user} -X GET ${art_path}/last/) + +for file in ${last_files} +do + if [[ ${file} =~ "href=" ]] + then + file_name=$(echo ${file#*>} | sed -e 's/<\/a>//') + if [[ ${file_name} != "../" ]] + then + curl -k ${art_user} -X DELETE ${art_path}/last/${file_name} + fi + fi +done +curl -k ${art_user} -T ${art_pf_tgz_src} ${art_pf_tgz_dst1} +curl -k ${art_user} -T ${art_pf_tgz_src} ${art_pf_tgz_dst2} +curl -k ${art_user} -T ${art_host_hpf_src} ${art_host_hpf_dst1} +curl -k ${art_user} -T ${art_host_hpf_src} ${art_host_hpf_dst2} +curl -k ${art_user} -T ${art_zf_mpf_src} ${art_zf_mpf_dst1} +curl -k ${art_user} -T ${art_zf_mpf_src} ${art_zf_mpf_dst2} + +curl -k ${art_user} -T ${art_host_arm_en_pf_src} ${art_host_arm_en_pf_dst1} +curl -k ${art_user} -T ${art_host_arm_en_pf_src} ${art_host_arm_en_pf_dst2} + +curl -k ${art_user} -T ${art_host_x86_en_pf_src} ${art_host_x86_en_pf_dst1} +curl -k ${art_user} -T ${art_host_x86_en_pf_src} ${art_host_x86_en_pf_dst2} + +curl -k ${art_user} -T ${art_host_arm_hpf_src} ${art_host_arm_hpf_dst1} +curl -k ${art_user} -T ${art_host_arm_hpf_src} ${art_host_arm_hpf_dst2} + +curl -k ${art_user} -T ${art_host_x86_hpf_src} ${art_host_x86_hpf_dst1} +curl -k ${art_user} -T ${art_host_x86_hpf_src} ${art_host_x86_hpf_dst2} + +curl -k ${art_user} -T ${art_zf_arm_en_pf_src} ${art_zf_arm_en_pf_dst1} +curl -k ${art_user} -T ${art_zf_arm_en_pf_src} ${art_zf_arm_en_pf_dst2} + +curl -k ${art_user} -T ${art_zf_arm_zf_mpf_src} ${art_zf_arm_zf_mpf_dst1} +curl -k ${art_user} -T ${art_zf_arm_zf_mpf_src} ${art_zf_arm_zf_mpf_dst2} + +curl -k ${art_user} -T ${art_src2} ${art_dst5} +curl -k ${art_user} -T ${art_src2} ${art_dst6} + +curl -k ${art_user} -T ${art_src3} ${art_dst7} +curl -k ${art_user} -T ${art_src3} ${art_dst8} +exit 0 diff --git a/src/net/ut.sh b/src/net/ut.sh new file mode 100755 index 0000000..2dfe825 --- /dev/null +++ b/src/net/ut.sh @@ -0,0 +1,6 @@ +#!/bin/bash + + +#暂时没实现的，固定返回0，后期如果实现，根据各组件自身需求调整该脚本 +exit 0 + diff --git a/src/net/zxdh_eth_rpm_build.sh b/src/net/zxdh_eth_rpm_build.sh new file mode 100755 index 0000000..ae96d67 --- /dev/null +++ b/src/net/zxdh_eth_rpm_build.sh @@ -0,0 +1,276 @@ +#!/bin/bash +host_arch=$(uname -m) +dist=$(rpm --eval %{dist}) +build_kernel=$(uname -r) + +usage() +{ +cat <<EOF +Usage: + ${0##*/} --rpm-driver-name <driver_name> + --rpm-driver-version <driver_version> + --rpm-driver-release <driver_release> + --rpm-config-name <config_name> [ zxdh-smartnic-config | zxdh-dpu-config ] + --rpm-config-version <config_version> + --rpm-config-release <config_release> + --eth-driver-version <eth_driver_version> + --ksrc <kernel_source_path> + --cross-compile <cross_compile_path> + --target-arch <target_arch> [ x86_64 | aarch64 ] + --dist <kernel source dist> [ .el8 | .zncgsl6 ] + --output-dir <outputdir> [options] + +Options: + --rpm-driver-name <driver_name> Set rpm driver name (default: zxdh-eth) + --rpm-driver-version <driver_version> Set rpm driver version (default: 1.0) + --rpm-driver-release <driver_release> Set rpm driver release (default: 1) + --rpm-config-name <config_name> Set rpm config name (default: zxdh-smartnic-config) + --rpm-config-version <config_version> Set rpm config version (default: 1.0) + --rpm-config-release <config_release> Set rpm config release (default: 1) + --eth-driver-version <eth_driver_version> Set eth driver version (default: 1.0-0) + --ksrc <kernel_source> Set kernel source path (default: /lib/modules/$(uname -r)/source) + --cross-compile <cross_compile_path> Set cross compile tools path (default(Don't cross compile): None) + --target-arch <traget_arch> Set the target arch (default(current arch): $(uname -m)) + --dist <kernel source dist> Set the kernel source dist (default(current dist): $(rpm --eval %{dist})) + --output-dir <outputdir> Change rpm output dir (default(working dir): $(pwd)) + -h, --help Show help message + +Output: + - build driver binary rpm package(eg: zxdh-eth-1.0-1$(rpm --eval %{dist}).$(uname -m).rpm) and copy it to dir (--output-dir eg: $(pwd)) + - build config rpm package(eg: zxdh-smartnic-config-1.0-1.rpm) and copy it to dir (--output-dir eg: $(pwd)) +EOF +} + +show_args() +{ +cat <<EOF +********************************************** +kernel source: $ksrc +kernel dist: $dist +host arch: $host_arch +target arch: $target_arch_info +cross compile: $cross_compile_info +eth driver version: $eth_driver_version +********************************************** +rpm dirver name: $rpm_driver_name +rpm driver version: $rpm_driver_version +rpm driver release: $rpm_driver_release +********************************************** +rpm config name: $rpm_config_name +rpm config version: $rpm_config_version +rpm config release: $rpm_config_release +********************************************** +output dir: $output_dir +********************************************** +EOF +} + +while [ ! -z "$1" ] +do + case "$1" in + --rpm-driver-name) + rpm_driver_name="$2" + shift + ;; + --rpm-driver-version) + rpm_driver_version="$2" + shift + ;; + --rpm-driver-release) + rpm_driver_release="$2" + shift + ;; + --rpm-mpf-name) + rpm_mpf_name="$2" + shift + ;; + --rpm-mpf-version) + rpm_mpf_version="$2" + shift + ;; + --rpm-mpf-release) + rpm_mpf_release="$2" + shift + ;; + --rpm-config-name) + rpm_config_name="$2" + shift + ;; + --rpm-config-version) + rpm_config_version="$2" + shift + ;; + --rpm-config-release) + rpm_config_release="$2" + shift + ;; + --eth-driver-version) + eth_driver_version="$2" + shift + ;; + --ksrc) + ksrc="$2" + shift + ;; + --build-mpf) + build_mpf="$2" + shift + ;; + --cross-compile) + cross_compile="$2" + shift + ;; + --target-arch) + target_arch="$2" + shift + ;; + --dist) + dist="$2" + shift + ;; + --output-dir) + output_dir="$2" + shift + ;; + -h | *help) + usage + exit 0 + ;; + *) + echo "-E- Unsupported option: $1" >&2 + exit 1 + ;; + esac + shift +done + +# Some input verification +if [ -z "$rpm_driver_name" ]; then + rpm_driver_name="zxdh-eth" +fi +if [ -z "$rpm_driver_version" ]; then + rpm_driver_version="1.0" +fi +if [ -z "$rpm_driver_release" ]; then + rpm_driver_release="1" +fi +if [ -z "$rpm_config_name" ]; then + rpm_config_name="zxdh-smartnic-config" +fi +if [ -z "$rpm_config_version" ]; then + rpm_config_version="1.0" +fi +if [ -z "$rpm_config_release" ]; then + rpm_config_release="1" +fi +if [ -z "$eth_driver_version" ]; then + eth_driver_version="1.0-1" +fi +if [ -z "$ksrc" ]; then + ksrc="/lib/modules/$(uname -r)/source" +fi +if [ -z "$cross_compile" ]; then + cross_compile_info="Don't corss compile..." +else + cross_compile_info=$cross_compile +fi +if [ -z "$target_arch" ]; then + target_arch=$host_arch + target_arch_info="$target_arch (Don't corss compile, same as host arch)" +else + target_arch_info=$target_arch +fi +if [ -z "$output_dir" ]; then + output_dir=$(pwd) +fi +if [ ! -d $ksrc ]; then + echo "-E- $ksrc is not exists" >&2 + exit 1 +fi +if [ ! -d $output_dir ]; then + mkdir -p $output_dir + if [ $? -ne 0 ]; then + echo "-E- Failed to create $outputdir" >&2 + exit 1 + fi +fi + +show_args +sleep 3 + +tmpdir=$(mktemp -d /tmp/$rpm_driver_name.XXXXXX) +if [ ! -d "$tmpdir" ]; then + echo "-E- Failed to create $tmpdir!" >&2 + exit 1 +fi +trap "/bin/rm -rf $tmpdir" EXIT + +cp -r ../zxdh_kernel $tmpdir +cd $tmpdir +cd zxdh_kernel + +# 将spec文件拷贝到zxdh_kernel目录下 制作rpm包 +cp build/spec/zxdh-eth.spec.example ./zxdh-eth.spec +cd $tmpdir +tar czf $rpm_driver_name-$rpm_driver_version-$rpm_driver_release.tar.gz ./zxdh_kernel/ + +zxdh_eth_rpm=$rpm_driver_name-$rpm_driver_version-$rpm_driver_release$dist.$target_arch.rpm +zxdh_config_rpm=$rpm_config_name-$rpm_config_version-$rpm_config_release.noarch.rpm + +if [ -d "$HOME/rpmbuild/RPMS/$target_arch" ]; then + cd $HOME/rpmbuild/RPMS/$target_arch + if [ -f "$zxdh_eth_rpm" ]; then + rm $zxdh_eth_rpm + fi +fi + +if [ -d "$HOME/rpmbuild/RPMS/noarch" ]; then + cd $HOME/rpmbuild/RPMS/noarch + if [ -f "$zxdh_config_rpm" ]; then + rm $zxdh_config_rpm + fi +fi + +cd $tmpdir + +# make rpmbuild parameters +rpm_build_args=() +if [ "$target_arch" != "$host_arch" ]; then + # 交叉编译 + rpm_build_args+=( --target $target_arch) + rpm_build_args+=( --define "target $target_arch") + rpm_build_args+=( --define "CROSS_COMPILE $cross_compile") +fi + +rpm_build_args+=( --define "_name $rpm_driver_name") +rpm_build_args+=( --define "_version $rpm_driver_version") +rpm_build_args+=( --define "_release $rpm_driver_release") + +rpm_build_args+=( --define "_config_name $rpm_config_name") +rpm_build_args+=( --define "_config_version $rpm_config_version") +rpm_build_args+=( --define "_config_release $rpm_config_release") + +rpm_build_args+=( --define "ETH_DRI_VER $eth_driver_version") + +rpm_build_args+=( --define "KSRC $ksrc") + +rpm_build_args+=( --define "dist $dist") +rpm_build_args+=( ./$rpm_driver_name-$rpm_driver_version-$rpm_driver_release.tar.gz) + +rpmbuild -tb "${rpm_build_args[@]}" + +cd $HOME/rpmbuild/RPMS/$target_arch + +if [ -f "$zxdh_eth_rpm" ]; then + cp $zxdh_eth_rpm $output_dir + rm $zxdh_eth_rpm +fi + +cd $HOME/rpmbuild/RPMS/noarch + +if [ -f "$zxdh_config_rpm" ]; then + cp $zxdh_config_rpm $output_dir + rm $zxdh_config_rpm +fi + +exit 0 diff --git a/src/net/zxdh_hpf_rpm_build.sh b/src/net/zxdh_hpf_rpm_build.sh new file mode 100755 index 0000000..a746d71 --- /dev/null +++ b/src/net/zxdh_hpf_rpm_build.sh @@ -0,0 +1,209 @@ +#!/bin/bash +host_arch=$(uname -m) +dist=$(rpm --eval %{dist}) +build_kernel=$(uname -r) + +usage() +{ +cat <<EOF +Usage: + ${0##*/} --rpm-driver-name <driver_name> + --rpm-driver-version <driver_version> + --rpm-driver-release <driver_release> + --hpf-driver-version <hpf_driver_version> + --ksrc <kernel_source_path> + --cross-compile <cross_compile_path> + --target-arch <target_arch> [ x86_64 | aarch64 ] + --dist <kernel source dist> [ .el8 | .zncgsl6 ] + --output-dir <outputdir> [options] + +Options: + --rpm-driver-name <driver_name> Set rpm driver name (default: zxdh-hpf) + --rpm-driver-version <driver_version> Set rpm driver version (default: 1.0) + --rpm-driver-release <driver_release> Set rpm driver release (default: 1) + --hpf-driver-version <hpf_driver_version> Set hpf driver version (default: 1.0-0) + --ksrc <kernel_source> Set kernel source path (default: /lib/modules/$(uname -r)/source) + --cross-compile <cross_compile_path> Set cross compile tools path (default(Don't cross compile): None) + --target-arch <traget_arch> Set the target arch (default(current arch): $(uname -m)) + --dist <kernel source dist> Set the kernel source dist (default(current dist): $(rpm --eval %{dist})) + --output-dir <outputdir> Change rpm output dir (default(working dir): $(pwd)) + -h, --help Show help message + +Output: + - build driver binary rpm package(eg: zxdh-hpf-1.0-1$(rpm --eval %{dist}).$(uname -m).rpm) and copy it to dir (--output-dir eg: $(pwd)) +EOF +} + +show_args() +{ +cat <<EOF +********************************************** +kernel source: $ksrc +kernel dist: $dist +host arch: $host_arch +target arch: $target_arch_info +cross compile: $cross_compile_info +hpf driver version: $hpf_driver_version +********************************************** +rpm dirver name: $rpm_driver_name +rpm driver version: $rpm_driver_version +rpm driver release: $rpm_driver_release +********************************************** +output dir: $output_dir +********************************************** +EOF +} + +while [ ! -z "$1" ] +do + case "$1" in + --rpm-driver-name) + rpm_driver_name="$2" + shift + ;; + --rpm-driver-version) + rpm_driver_version="$2" + shift + ;; + --rpm-driver-release) + rpm_driver_release="$2" + shift + ;; + --hpf-driver-version) + hpf_driver_version="$2" + shift + ;; + --ksrc) + ksrc="$2" + shift + ;; + --cross-compile) + cross_compile="$2" + shift + ;; + --target-arch) + target_arch="$2" + shift + ;; + --dist) + dist="$2" + shift + ;; + --output-dir) + output_dir="$2" + shift + ;; + -h | *help) + usage + exit 0 + ;; + *) + echo "-E- Unsupported option: $1" >&2 + exit 1 + ;; + esac + shift +done + +# Some input verification +if [ -z "$rpm_driver_name" ]; then + rpm_driver_name="zxdh-hpf" +fi +if [ -z "$rpm_driver_version" ]; then + rpm_driver_version="1.0" +fi +if [ -z "$rpm_driver_release" ]; then + rpm_driver_release="1" +fi +if [ -z "$hpf_driver_version" ]; then + hpf_driver_version="1.0-1" +fi +if [ -z "$ksrc" ]; then + ksrc="/lib/modules/$(uname -r)/source" +fi +if [ -z "$cross_compile" ]; then + cross_compile_info="Don't corss compile..." +else + cross_compile_info=$cross_compile +fi +if [ -z "$target_arch" ]; then + target_arch=$host_arch + target_arch_info="$target_arch (Don't corss compile, same as host arch)" +else + target_arch_info=$target_arch +fi +if [ -z "$output_dir" ]; then + output_dir=$(pwd) +fi +if [ ! -d $ksrc ]; then + echo "-E- $ksrc is not exists" >&2 + exit 1 +fi +if [ ! -d $output_dir ]; then + mkdir -p $output_dir + if [ $? -ne 0 ]; then + echo "-E- Failed to create $outputdir" >&2 + exit 1 + fi +fi + +show_args +sleep 3 + +tmpdir=$(mktemp -d /tmp/$rpm_driver_name.XXXXXX) +if [ ! -d "$tmpdir" ]; then + echo "-E- Failed to create $tmpdir!" >&2 + exit 1 +fi +trap "/bin/rm -rf $tmpdir" EXIT + +cp -r ../zxdh_kernel $tmpdir +cd $tmpdir +cd zxdh_kernel + +# 将spec文件拷贝到zxdh_kernel目录下 制作rpm包 +cp build/spec/zxdh-hpf.spec.example ./zxdh-hpf.spec +cd $tmpdir +tar czf $rpm_driver_name-$rpm_driver_version-$rpm_driver_release.tar.gz ./zxdh_kernel/ + +zxdh_hpf_rpm=$rpm_driver_name-$rpm_driver_version-$rpm_driver_release$dist.$target_arch.rpm + +if [ -d "$HOME/rpmbuild/RPMS/$target_arch" ]; then + cd $HOME/rpmbuild/RPMS/$target_arch + if [ -f "$zxdh_hpf_rpm" ]; then + rm $zxdh_hpf_rpm + fi +fi + +cd $tmpdir + +# make rpmbuild parameters +rpm_build_args=() +if [ "$target_arch" != "$host_arch" ]; then + # 交叉编译 + rpm_build_args+=( --target $target_arch) + rpm_build_args+=( --define "target $target_arch") + rpm_build_args+=( --define "CROSS_COMPILE $cross_compile") +fi + +rpm_build_args+=( --define "_name $rpm_driver_name") +rpm_build_args+=( --define "_version $rpm_driver_version") +rpm_build_args+=( --define "_release $rpm_driver_release") + +rpm_build_args+=( --define "HPF_DRI_VER $hpf_driver_version") + +rpm_build_args+=( --define "KSRC $ksrc") + +rpm_build_args+=( --define "dist $dist") +rpm_build_args+=( ./$rpm_driver_name-$rpm_driver_version-$rpm_driver_release.tar.gz) + +rpmbuild -tb "${rpm_build_args[@]}" + +cd $HOME/rpmbuild/RPMS/$target_arch + +if [ -f "$zxdh_hpf_rpm" ]; then + cp $zxdh_hpf_rpm $output_dir + rm $zxdh_hpf_rpm +fi + +exit 0 diff --git a/src/net/zxdh_kernel.sh b/src/net/zxdh_kernel.sh new file mode 100755 index 0000000..b6a852f --- /dev/null +++ b/src/net/zxdh_kernel.sh @@ -0,0 +1,127 @@ +#!/bin/bash + +cmd=$1 + +ver_path=/zte +root_dir=$ver_path/zxdh_kernel + +if ! yum list installed | grep -q Data-Dumper; then + yum install 'perl(Data::Dumper)' +fi + +function get_submit_info(){ + cd $1 + commit_id=$(git log --pretty=format:"%H" | head -n 1) + chg_no=$(git ls-remote | awk '/'${commit_id}'/&&/changes/' | sed 's/\//\n/g' | tail -n 2 | head -1) + title=$(git log --pretty=format:"%s" ${commit_id} -1) + cd - + echo "${commit_id} ${chg_no} ${title}" +} + +function get_chg_no(){ + cd $1 + commit_id=$(git log --pretty=format:"%H" | head -n 1) + chg_no=$(git ls-remote | awk '/'${commit_id}'/&&/changes/' | sed 's/\//\n/g' | tail -n 2 | head -1) + cd - + echo "${chg_no}" +} + +if [ $cmd = "compile" ]; then + yum -y install autoconf + file_name=$(uname -r) + echo ${file_name} + directory=/lib/modules/${file_name} + unzip -o $ver_path/driver/5.10.134-13.1.zncgsl6.x86_64.zip -d /lib/modules + if [ ! -d "$directory" ]; then + mv /lib/modules/5.10.134-13.1.zncgsl6.x86_64 /lib/modules/${file_name} + ls /lib/modules + ls /usr/lib/modules + fi + cd $root_dir/build + ./build.pl -t kernel -m CONFIG_DINGHAI_ETH -m CONFIG_ZXDH_AUXILIARY -m CONFIG_DINGHAI_MPF \ + -m CONFIG_DINGHAI_PF -m CONFIG_ZXDH_SF -m CONFIG_DINGHAI_EN_AUX -m HAVE_DEVLINK_ALLOC_GET_1_PARAMS \ + -m HAVE_DEV_PM_DOMAIN_ATTACH -m HAVE_BUS_FIND_DEVICE_GET_CONST -m CONFIG_DINGHAI_DH_CMD -m CONFIG_DINGHAI_NP + ret=$? + exit ${ret} +fi + +if [ $cmd = "upload_gerrit" ]; then + build_no=$2 + chg_no=$3 + chg_branch=$4 + env_user=$5 + env_pwd=$6 + date=$(date +%Y%m%d%H%M%S) + + cd $root_dir + zip -j kofile_${build_no}.${chg_no}.${date}.zip $root_dir/drivers/base/zxdh_auxiliary.ko \ + $root_dir/drivers/net/ethernet/dinghai/zxdh_en_aux.ko $root_dir/drivers/net/ethernet/dinghai/zxdh_mpf.ko \ + $root_dir/drivers/net/ethernet/dinghai/zxdh_np.ko $root_dir/drivers/net/ethernet/dinghai/zxdh_pf.ko + art_path="https://artsz.zte.com.cn:443/artifactory/dinghai-snapshot-generic/dpu_sdk/net/driver/zxdh_kernel/${chg_branch}" + art_src="${root_dir}/kofile_${build_no}.${chg_no}.${date}.zip" + art_user="-u${env_user}:${env_pwd}" + art_name="kofile_${build_no}.${chg_no}.${date}.zip" + art_dst1="${art_path}/${art_name}" + art_dst2="${art_path}/last/${art_name}" + last_files=$(curl -k ${art_user} -X GET ${art_path}/last/) + for file in ${last_files} + do + #echo "new line:"${file} + if [[ ${file} =~ "href=" ]] + then + file_name=$(echo ${file#*>} | sed -e 's/<\/a>//') + #echo "file:"$file_name + if [[ ${file_name} != "../" ]] + then + curl -k ${art_user} -X DELETE ${art_path}/last/${file_name} + fi + fi + done + curl -k ${art_user} -T ${art_src} ${art_dst1} + curl -k ${art_user} -T ${art_src} ${art_dst2} + exit 0 +fi + +if [ $cmd = "upload_versionci" ]; then + build_no=$2 + chg_branch=$3 + env_user=$4 + env_pwd=$5 + chg_no=`get_chg_no ./ | tail -n 1` + art_user="-u${env_user}:${env_pwd}" + date=$(date +%Y%m%d%H%M%S) + + cd ${root_dir} + art_path="https://artsz.zte.com.cn:443/artifactory/dinghai-snapshot-generic/dpu_sdk/net/driver/zxdh_kernel/${chg_branch}" + art_src="${root_dir}/kofile_${build_no}.${chg_no}.${date}.zip" + art_user="-u${env_user}:${env_pwd}" + art_name="kofile_${build_no}.${chg_no}.${date}.zip" + art_dst1="${art_path}/${art_name}" + art_dst2="${art_path}/last/${art_name}" + last_files=$(curl -k ${art_user} -X GET ${art_path}/last/) + for file in ${last_files} + do + #echo "new line:"${file} + if [[ ${file} =~ "href=" ]] + then + file_name=$(echo ${file#*>} | sed -e 's/<\/a>//') + #echo "file:"$file_name + if [[ ${file_name} != "../" ]] + then + curl -k ${art_user} -X DELETE ${art_path}/last/${file_name} + fi + fi + done + # get_submit_info ./ | tail -n 1 >> mcode_${build_no}.${chg_no}.${date}-daily.txt + # art_src1="${root_dir}/mcode_${build_no}.${chg_no}.${date}-daily.txt" + curl -k ${art_user} -T ${art_src} ${art_dst1} + curl -k ${art_user} -T ${art_src} ${art_dst2} + # curl -k ${art_user} -T ${art_src1} ${art_dst1} + # curl -k ${art_user} -T ${art_src1} ${art_dst2} + exit 0 +fi + +echo "unknow cmd" +exit 1 + + diff --git a/src/net/zxdh_zf_mpf_rpm_build.sh b/src/net/zxdh_zf_mpf_rpm_build.sh new file mode 100755 index 0000000..96938fd --- /dev/null +++ b/src/net/zxdh_zf_mpf_rpm_build.sh @@ -0,0 +1,201 @@ +#!/bin/bash +host_arch=$(uname -m) +dist=$(rpm --eval %{dist}) +build_kernel=$(uname -r) + +usage() +{ +cat <<EOF +Usage: + ${0##*/} --rpm-driver-name <driver_name> + --rpm-driver-version <driver_version> + --rpm-driver-release <driver_release> + --zf-mpf-driver-version <zf_mpf_driver_version> + --ksrc <kernel_source_path> + --cross-compile <cross_compile_path> + --dist <kernel source dist> [ .el8 | .zncgsl6 ] + --output-dir <outputdir> [options] + +Options: + --rpm-driver-name <driver_name> Set rpm driver name (default: zxdh-zf-mpf) + --rpm-driver-version <driver_version> Set rpm driver version (default: 1.0) + --rpm-driver-release <driver_release> Set rpm driver release (default: 1) + --zf-mpf-driver-version <zf_mpf_driver_version> Set zf_mpf driver version (default: 1.0-0) + --ksrc <kernel_source> Set kernel source path (default: /lib/modules/$(uname -r)/source) + --cross-compile <cross_compile_path> Set cross compile tools path + --dist <kernel source dist> Set the kernel source dist (default(current dist): $(rpm --eval %{dist})) + --output-dir <outputdir> Change rpm output dir (default(working dir): $(pwd)) + -h, --help Show help message + +Output: + - build driver binary rpm package(eg: zxdh-zf-mpf-1.0-1$(rpm --eval %{dist}).aarch64.rpm) and copy it to dir (--output-dir eg: $(pwd)) +EOF +} + +show_args() +{ +cat <<EOF +********************************************** +kernel source: $ksrc +kernel dist: $dist +host arch: $host_arch +target arch: $target_arch_info +cross compile: $cross_compile_info +zf_mpf driver version:$zf_mpf_driver_version +********************************************** +rpm dirver name: $rpm_driver_name +rpm driver version: $rpm_driver_version +rpm driver release: $rpm_driver_release +********************************************** +output dir: $output_dir +********************************************** +EOF +} + +while [ ! -z "$1" ] +do + case "$1" in + --rpm-driver-name) + rpm_driver_name="$2" + shift + ;; + --rpm-driver-version) + rpm_driver_version="$2" + shift + ;; + --rpm-driver-release) + rpm_driver_release="$2" + shift + ;; + --zf-mpf-driver-version) + zf_mpf_driver_version="$2" + shift + ;; + --ksrc) + ksrc="$2" + shift + ;; + --cross-compile) + cross_compile="$2" + shift + ;; + --dist) + dist="$2" + shift + ;; + --output-dir) + output_dir="$2" + shift + ;; + -h | *help) + usage + exit 0 + ;; + *) + echo "-E- Unsupported option: $1" >&2 + exit 1 + ;; + esac + shift +done + +# Some input verification +if [ -z "$rpm_driver_name" ]; then + rpm_driver_name="zxdh-zf-mpf" +fi +if [ -z "$rpm_driver_version" ]; then + rpm_driver_version="1.0" +fi +if [ -z "$rpm_driver_release" ]; then + rpm_driver_release="1" +fi +if [ -z "$zf_mpf_driver_version" ]; then + zf_mpf_driver_version="1.0-1" +fi +if [ -z "$ksrc" ]; then + ksrc="/lib/modules/$(uname -r)/source" +fi +if [ -z "$cross_compile" ]; then + cross_compile_info="Don't corss compile..." +else + cross_compile_info=$cross_compile +fi + +target_arch="aarch64" +target_arch_info="$target_arch (target arch must be aarch64)" + +if [ -z "$output_dir" ]; then + output_dir=$(pwd) +fi +if [ ! -d $ksrc ]; then + echo "-E- $ksrc is not exists" >&2 + exit 1 +fi +if [ ! -d $output_dir ]; then + mkdir -p $output_dir + if [ $? -ne 0 ]; then + echo "-E- Failed to create $outputdir" >&2 + exit 1 + fi +fi + +show_args +sleep 3 + +tmpdir=$(mktemp -d /tmp/$rpm_driver_name.XXXXXX) +if [ ! -d "$tmpdir" ]; then + echo "-E- Failed to create $tmpdir!" >&2 + exit 1 +fi +trap "/bin/rm -rf $tmpdir" EXIT + +cp -r ../zxdh_kernel $tmpdir +cd $tmpdir +cd zxdh_kernel + +# 将spec文件拷贝到zxdh_kernel目录下 制作rpm包 +cp build/spec/zxdh-zf-mpf.spec.example ./zxdh-zf-mpf.spec +cd $tmpdir +tar czf $rpm_driver_name-$rpm_driver_version-$rpm_driver_release.tar.gz ./zxdh_kernel/ + +zxdh_zf_mpf_rpm=$rpm_driver_name-$rpm_driver_version-$rpm_driver_release$dist.$target_arch.rpm + +if [ -d "$HOME/rpmbuild/RPMS/$target_arch" ]; then + cd $HOME/rpmbuild/RPMS/$target_arch + if [ -f "$zxdh_zf_mpf_rpm" ]; then + rm $zxdh_zf_mpf_rpm + fi +fi + +cd $tmpdir + +# make rpmbuild parameters +rpm_build_args=() +if [ "$target_arch" != "$host_arch" ]; then + # 交叉编译 + rpm_build_args+=( --target $target_arch) + rpm_build_args+=( --define "target $target_arch") + rpm_build_args+=( --define "CROSS_COMPILE $cross_compile") +fi + +rpm_build_args+=( --define "_name $rpm_driver_name") +rpm_build_args+=( --define "_version $rpm_driver_version") +rpm_build_args+=( --define "_release $rpm_driver_release") + +rpm_build_args+=( --define "ZF_MPF_DRI_VER $zf_mpf_driver_version") + +rpm_build_args+=( --define "KSRC $ksrc") + +rpm_build_args+=( --define "dist $dist") +rpm_build_args+=( ./$rpm_driver_name-$rpm_driver_version-$rpm_driver_release.tar.gz) + +rpmbuild -tb "${rpm_build_args[@]}" + +cd $HOME/rpmbuild/RPMS/$target_arch + +if [ -f "$zxdh_zf_mpf_rpm" ]; then + cp $zxdh_zf_mpf_rpm $output_dir + rm $zxdh_zf_mpf_rpm +fi + +exit 0 -- Gitee From 245ad62e6fb9eb0c2a6483916adc5a9321ff7516 Mon Sep 17 00:00:00 2001 From: hcf <11636549+hcf85679@user.noreply.gitee.com> Date: Fri, 14 Jun 2024 11:18:13 +0800 Subject: [PATCH 2/3] modify spec kernel version --- kmod-zxdh.spec | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kmod-zxdh.spec b/kmod-zxdh.spec index 4db6f9f..b97474b 100644 --- a/kmod-zxdh.spec +++ b/kmod-zxdh.spec @@ -1,5 +1,5 @@ %global pkg zxdh -%global kernel 5.10.134-16.2.an8 +%global kernel kernel version %define pkg_version 1.13.1 %define anolis_release 1 -- Gitee From aa97ccada4e8836bb79e02ef179fc5d135fa4aad Mon Sep 17 00:00:00 2001 From: hcf <11636549+hcf85679@user.noreply.gitee.com> Date: Fri, 14 Jun 2024 14:58:23 +0800 Subject: [PATCH 3/3] modify spec kernel version --- kmod-zxdh.spec => kmod-dinghai.spec | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) rename kmod-zxdh.spec => kmod-dinghai.spec (99%) diff --git a/kmod-zxdh.spec b/kmod-dinghai.spec similarity index 99% rename from kmod-zxdh.spec rename to kmod-dinghai.spec index b97474b..1dbffbb 100644 --- a/kmod-zxdh.spec +++ b/kmod-dinghai.spec @@ -1,6 +1,6 @@ -%global pkg zxdh +%global pkg dinghai %global kernel kernel version -%define pkg_version 1.13.1 +%define pkg_version 2.24.20 %define anolis_release 1 %global debug_package %{nil} -- Gitee

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